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// SPDX-License-Identifier: GPL-2.0
/*
* Support for Intel Camera Imaging ISP subsystem.
* Copyright (c) 2015, Intel Corporation.
*/
#include "hmm.h"
#include "ia_css_frame_public.h"
#define IA_CSS_INCLUDE_CONFIGURATIONS
#include "ia_css_isp_configs.h"
#include "ia_css_types.h"
#include "ia_css_host_data.h"
#include "sh_css_param_dvs.h"
#include "sh_css_params.h"
#include "ia_css_binary.h"
#include "ia_css_debug.h"
#include "assert_support.h"
#include "ia_css_dvs.host.h"
static const struct ia_css_dvs_configuration default_config = {
.info = (struct ia_css_frame_info *)NULL,
};
void
ia_css_dvs_config(
struct sh_css_isp_dvs_isp_config *to,
const struct ia_css_dvs_configuration *from,
unsigned int size)
{
(void)size;
to->num_horizontal_blocks =
DVS_NUM_BLOCKS_X(from->info->res.width);
to->num_vertical_blocks =
DVS_NUM_BLOCKS_Y(from->info->res.height);
}
int ia_css_dvs_configure(const struct ia_css_binary *binary,
const struct ia_css_frame_info *info)
{
struct ia_css_dvs_configuration config = default_config;
config.info = info;
return ia_css_configure_dvs(binary, &config);
}
static void
convert_coords_to_ispparams(
struct ia_css_host_data *gdc_warp_table,
const struct ia_css_dvs_6axis_config *config,
unsigned int i_stride,
unsigned int o_width,
unsigned int o_height,
unsigned int uv_flag)
{
unsigned int i, j;
gdc_warp_param_mem_t s = { 0 };
unsigned int x00, x01, x10, x11,
y00, y01, y10, y11;
unsigned int xmin, ymin, xmax, ymax;
unsigned int topleft_x, topleft_y, bottom_x, bottom_y,
topleft_x_frac, topleft_y_frac;
unsigned int dvs_interp_envelope = (DVS_GDC_INTERP_METHOD == HRT_GDC_BLI_MODE ?
DVS_GDC_BLI_INTERP_ENVELOPE : DVS_GDC_BCI_INTERP_ENVELOPE);
/* number of blocks per height and width */
unsigned int num_blocks_y = (uv_flag ? DVS_NUM_BLOCKS_Y_CHROMA(
o_height) : DVS_NUM_BLOCKS_Y(o_height));
unsigned int num_blocks_x = (uv_flag ? DVS_NUM_BLOCKS_X_CHROMA(
o_width) : DVS_NUM_BLOCKS_X(
o_width)); // round num_x up to blockdim_x, if it concerns the Y0Y1 block (uv_flag==0) round up to even
unsigned int in_stride = i_stride * DVS_INPUT_BYTES_PER_PIXEL;
unsigned int width, height;
unsigned int *xbuff = NULL;
unsigned int *ybuff = NULL;
struct gdc_warp_param_mem_s *ptr;
assert(config);
assert(gdc_warp_table);
assert(gdc_warp_table->address);
ptr = (struct gdc_warp_param_mem_s *)gdc_warp_table->address;
ptr += (2 * uv_flag); /* format is Y0 Y1 UV, so UV starts at 3rd position */
if (uv_flag == 0) {
xbuff = config->xcoords_y;
ybuff = config->ycoords_y;
width = config->width_y;
height = config->height_y;
} else {
xbuff = config->xcoords_uv;
ybuff = config->ycoords_uv;
width = config->width_uv;
height = config->height_uv;
}
IA_CSS_LOG("blockdim_x %d blockdim_y %d",
DVS_BLOCKDIM_X, DVS_BLOCKDIM_Y_LUMA >> uv_flag);
IA_CSS_LOG("num_blocks_x %d num_blocks_y %d", num_blocks_x, num_blocks_y);
IA_CSS_LOG("width %d height %d", width, height);
assert(width == num_blocks_x +
1); // the width and height of the provided morphing table should be 1 more than the number of blocks
assert(height == num_blocks_y + 1);
for (j = 0; j < num_blocks_y; j++) {
for (i = 0; i < num_blocks_x; i++) {
x00 = xbuff[j * width + i];
x01 = xbuff[j * width + (i + 1)];
x10 = xbuff[(j + 1) * width + i];
x11 = xbuff[(j + 1) * width + (i + 1)];
y00 = ybuff[j * width + i];
y01 = ybuff[j * width + (i + 1)];
y10 = ybuff[(j + 1) * width + i];
y11 = ybuff[(j + 1) * width + (i + 1)];
xmin = min(x00, x10);
xmax = max(x01, x11);
ymin = min(y00, y01);
ymax = max(y10, y11);
/* Assert that right column's X is greater */
assert(x01 >= xmin);
assert(x11 >= xmin);
/* Assert that bottom row's Y is greater */
assert(y10 >= ymin);
assert(y11 >= ymin);
topleft_y = ymin >> DVS_COORD_FRAC_BITS;
topleft_x = ((xmin >> DVS_COORD_FRAC_BITS)
>> XMEM_ALIGN_LOG2)
<< (XMEM_ALIGN_LOG2);
s.in_addr_offset = topleft_y * in_stride + topleft_x;
/* similar to topleft_y calculation, but round up if ymax
* has any fraction bits */
bottom_y = CEIL_DIV(ymax, 1 << DVS_COORD_FRAC_BITS);
s.in_block_height = bottom_y - topleft_y + dvs_interp_envelope;
bottom_x = CEIL_DIV(xmax, 1 << DVS_COORD_FRAC_BITS);
s.in_block_width = bottom_x - topleft_x + dvs_interp_envelope;
topleft_x_frac = topleft_x << (DVS_COORD_FRAC_BITS);
topleft_y_frac = topleft_y << (DVS_COORD_FRAC_BITS);
s.p0_x = x00 - topleft_x_frac;
s.p1_x = x01 - topleft_x_frac;
s.p2_x = x10 - topleft_x_frac;
s.p3_x = x11 - topleft_x_frac;
s.p0_y = y00 - topleft_y_frac;
s.p1_y = y01 - topleft_y_frac;
s.p2_y = y10 - topleft_y_frac;
s.p3_y = y11 - topleft_y_frac;
// block should fit within the boundingbox.
assert(s.p0_x < (s.in_block_width << DVS_COORD_FRAC_BITS));
assert(s.p1_x < (s.in_block_width << DVS_COORD_FRAC_BITS));
assert(s.p2_x < (s.in_block_width << DVS_COORD_FRAC_BITS));
assert(s.p3_x < (s.in_block_width << DVS_COORD_FRAC_BITS));
assert(s.p0_y < (s.in_block_height << DVS_COORD_FRAC_BITS));
assert(s.p1_y < (s.in_block_height << DVS_COORD_FRAC_BITS));
assert(s.p2_y < (s.in_block_height << DVS_COORD_FRAC_BITS));
assert(s.p3_y < (s.in_block_height << DVS_COORD_FRAC_BITS));
// block size should be greater than zero.
assert(s.p0_x < s.p1_x);
assert(s.p2_x < s.p3_x);
assert(s.p0_y < s.p2_y);
assert(s.p1_y < s.p3_y);
#if 0
printf("j: %d\ti:%d\n", j, i);
printf("offset: %d\n", s.in_addr_offset);
printf("p0_x: %d\n", s.p0_x);
printf("p0_y: %d\n", s.p0_y);
printf("p1_x: %d\n", s.p1_x);
printf("p1_y: %d\n", s.p1_y);
printf("p2_x: %d\n", s.p2_x);
printf("p2_y: %d\n", s.p2_y);
printf("p3_x: %d\n", s.p3_x);
printf("p3_y: %d\n", s.p3_y);
printf("p0_x_nofrac[0]: %d\n", s.p0_x >> DVS_COORD_FRAC_BITS);
printf("p0_y_nofrac[1]: %d\n", s.p0_y >> DVS_COORD_FRAC_BITS);
printf("p1_x_nofrac[2]: %d\n", s.p1_x >> DVS_COORD_FRAC_BITS);
printf("p1_y_nofrac[3]: %d\n", s.p1_y >> DVS_COORD_FRAC_BITS);
printf("p2_x_nofrac[0]: %d\n", s.p2_x >> DVS_COORD_FRAC_BITS);
printf("p2_y_nofrac[1]: %d\n", s.p2_y >> DVS_COORD_FRAC_BITS);
printf("p3_x_nofrac[2]: %d\n", s.p3_x >> DVS_COORD_FRAC_BITS);
printf("p3_y_nofrac[3]: %d\n", s.p3_y >> DVS_COORD_FRAC_BITS);
printf("\n");
#endif
*ptr = s;
// storage format:
// Y0 Y1 UV0 Y2 Y3 UV1
/* if uv_flag equals true increment with 2 incase x is odd, this to
skip the uv position. */
if (uv_flag)
ptr += 3;
else
ptr += (1 + (i & 1));
}
}
}
struct ia_css_host_data *
convert_allocate_dvs_6axis_config(
const struct ia_css_dvs_6axis_config *dvs_6axis_config,
const struct ia_css_binary *binary,
const struct ia_css_frame_info *dvs_in_frame_info)
{
unsigned int i_stride;
unsigned int o_width;
unsigned int o_height;
struct ia_css_host_data *me;
assert(binary);
assert(dvs_6axis_config);
assert(dvs_in_frame_info);
me = ia_css_host_data_allocate((size_t)((DVS_6AXIS_BYTES(binary) / 2) * 3));
if (!me)
return NULL;
/*DVS only supports input frame of YUV420 or NV12. Fail for all other cases*/
assert((dvs_in_frame_info->format == IA_CSS_FRAME_FORMAT_NV12)
|| (dvs_in_frame_info->format == IA_CSS_FRAME_FORMAT_YUV420));
i_stride = dvs_in_frame_info->padded_width;
o_width = binary->out_frame_info[0].res.width;
o_height = binary->out_frame_info[0].res.height;
/* Y plane */
convert_coords_to_ispparams(me, dvs_6axis_config,
i_stride, o_width, o_height, 0);
if (dvs_in_frame_info->format == IA_CSS_FRAME_FORMAT_YUV420) {
/*YUV420 has half the stride for U/V plane*/
i_stride /= 2;
}
/* UV plane (packed inside the y plane) */
convert_coords_to_ispparams(me, dvs_6axis_config,
i_stride, o_width / 2, o_height / 2, 1);
return me;
}
int
store_dvs_6axis_config(
const struct ia_css_dvs_6axis_config *dvs_6axis_config,
const struct ia_css_binary *binary,
const struct ia_css_frame_info *dvs_in_frame_info,
ia_css_ptr ddr_addr_y) {
struct ia_css_host_data *me;
assert(dvs_6axis_config);
assert(ddr_addr_y != mmgr_NULL);
assert(dvs_in_frame_info);
me = convert_allocate_dvs_6axis_config(dvs_6axis_config,
binary,
dvs_in_frame_info);
if (!me)
{
IA_CSS_LEAVE_ERR_PRIVATE(-ENOMEM);
return -ENOMEM;
}
ia_css_params_store_ia_css_host_data(
ddr_addr_y,
me);
ia_css_host_data_free(me);
return 0;
}
|
// SPDX-License-Identifier: GPL-2.0+
/*
* multiq3.c
* Hardware driver for Quanser Consulting MultiQ-3 board
*
* COMEDI - Linux Control and Measurement Device Interface
* Copyright (C) 1999 Anders Blomdell <[email protected]>
*/
/*
* Driver: multiq3
* Description: Quanser Consulting MultiQ-3
* Devices: [Quanser Consulting] MultiQ-3 (multiq3)
* Author: Anders Blomdell <[email protected]>
* Status: works
*
* Configuration Options:
* [0] - I/O port base address
* [1] - IRQ (not used)
* [2] - Number of optional encoder chips installed on board
* 0 = none
* 1 = 2 inputs (Model -2E)
* 2 = 4 inputs (Model -4E)
* 3 = 6 inputs (Model -6E)
* 4 = 8 inputs (Model -8E)
*/
#include <linux/module.h>
#include <linux/comedi/comedidev.h>
/*
* Register map
*/
#define MULTIQ3_DI_REG 0x00
#define MULTIQ3_DO_REG 0x00
#define MULTIQ3_AO_REG 0x02
#define MULTIQ3_AI_REG 0x04
#define MULTIQ3_AI_CONV_REG 0x04
#define MULTIQ3_STATUS_REG 0x06
#define MULTIQ3_STATUS_EOC BIT(3)
#define MULTIQ3_STATUS_EOC_I BIT(4)
#define MULTIQ3_CTRL_REG 0x06
#define MULTIQ3_CTRL_AO_CHAN(x) (((x) & 0x7) << 0)
#define MULTIQ3_CTRL_RC(x) (((x) & 0x3) << 0)
#define MULTIQ3_CTRL_AI_CHAN(x) (((x) & 0x7) << 3)
#define MULTIQ3_CTRL_E_CHAN(x) (((x) & 0x7) << 3)
#define MULTIQ3_CTRL_EN BIT(6)
#define MULTIQ3_CTRL_AZ BIT(7)
#define MULTIQ3_CTRL_CAL BIT(8)
#define MULTIQ3_CTRL_SH BIT(9)
#define MULTIQ3_CTRL_CLK BIT(10)
#define MULTIQ3_CTRL_LD (3 << 11)
#define MULTIQ3_CLK_REG 0x08
#define MULTIQ3_ENC_DATA_REG 0x0c
#define MULTIQ3_ENC_CTRL_REG 0x0e
/*
* Encoder chip commands (from the programming manual)
*/
#define MULTIQ3_CLOCK_DATA 0x00 /* FCK frequency divider */
#define MULTIQ3_CLOCK_SETUP 0x18 /* xfer PR0 to PSC */
#define MULTIQ3_INPUT_SETUP 0x41 /* enable inputs A and B */
#define MULTIQ3_QUAD_X4 0x38 /* quadrature */
#define MULTIQ3_BP_RESET 0x01 /* reset byte pointer */
#define MULTIQ3_CNTR_RESET 0x02 /* reset counter */
#define MULTIQ3_TRSFRPR_CTR 0x08 /* xfre preset reg to counter */
#define MULTIQ3_TRSFRCNTR_OL 0x10 /* xfer CNTR to OL (x and y) */
#define MULTIQ3_EFLAG_RESET 0x06 /* reset E bit of flag reg */
static void multiq3_set_ctrl(struct comedi_device *dev, unsigned int bits)
{
/*
* According to the programming manual, the SH and CLK bits should
* be kept high at all times.
*/
outw(MULTIQ3_CTRL_SH | MULTIQ3_CTRL_CLK | bits,
dev->iobase + MULTIQ3_CTRL_REG);
}
static int multiq3_ai_status(struct comedi_device *dev,
struct comedi_subdevice *s,
struct comedi_insn *insn,
unsigned long context)
{
unsigned int status;
status = inw(dev->iobase + MULTIQ3_STATUS_REG);
if (status & context)
return 0;
return -EBUSY;
}
static int multiq3_ai_insn_read(struct comedi_device *dev,
struct comedi_subdevice *s,
struct comedi_insn *insn,
unsigned int *data)
{
unsigned int chan = CR_CHAN(insn->chanspec);
unsigned int val;
int ret;
int i;
multiq3_set_ctrl(dev, MULTIQ3_CTRL_EN | MULTIQ3_CTRL_AI_CHAN(chan));
ret = comedi_timeout(dev, s, insn, multiq3_ai_status,
MULTIQ3_STATUS_EOC);
if (ret)
return ret;
for (i = 0; i < insn->n; i++) {
outw(0, dev->iobase + MULTIQ3_AI_CONV_REG);
ret = comedi_timeout(dev, s, insn, multiq3_ai_status,
MULTIQ3_STATUS_EOC_I);
if (ret)
return ret;
/* get a 16-bit sample; mask it to the subdevice resolution */
val = inb(dev->iobase + MULTIQ3_AI_REG) << 8;
val |= inb(dev->iobase + MULTIQ3_AI_REG);
val &= s->maxdata;
/* munge the 2's complement value to offset binary */
data[i] = comedi_offset_munge(s, val);
}
return insn->n;
}
static int multiq3_ao_insn_write(struct comedi_device *dev,
struct comedi_subdevice *s,
struct comedi_insn *insn,
unsigned int *data)
{
unsigned int chan = CR_CHAN(insn->chanspec);
unsigned int val = s->readback[chan];
int i;
for (i = 0; i < insn->n; i++) {
val = data[i];
multiq3_set_ctrl(dev, MULTIQ3_CTRL_LD |
MULTIQ3_CTRL_AO_CHAN(chan));
outw(val, dev->iobase + MULTIQ3_AO_REG);
multiq3_set_ctrl(dev, 0);
}
s->readback[chan] = val;
return insn->n;
}
static int multiq3_di_insn_bits(struct comedi_device *dev,
struct comedi_subdevice *s,
struct comedi_insn *insn, unsigned int *data)
{
data[1] = inw(dev->iobase + MULTIQ3_DI_REG);
return insn->n;
}
static int multiq3_do_insn_bits(struct comedi_device *dev,
struct comedi_subdevice *s,
struct comedi_insn *insn,
unsigned int *data)
{
if (comedi_dio_update_state(s, data))
outw(s->state, dev->iobase + MULTIQ3_DO_REG);
data[1] = s->state;
return insn->n;
}
static int multiq3_encoder_insn_read(struct comedi_device *dev,
struct comedi_subdevice *s,
struct comedi_insn *insn,
unsigned int *data)
{
unsigned int chan = CR_CHAN(insn->chanspec);
unsigned int val;
int i;
for (i = 0; i < insn->n; i++) {
/* select encoder channel */
multiq3_set_ctrl(dev, MULTIQ3_CTRL_EN |
MULTIQ3_CTRL_E_CHAN(chan));
/* reset the byte pointer */
outb(MULTIQ3_BP_RESET, dev->iobase + MULTIQ3_ENC_CTRL_REG);
/* latch the data */
outb(MULTIQ3_TRSFRCNTR_OL, dev->iobase + MULTIQ3_ENC_CTRL_REG);
/* read the 24-bit encoder data (lsb/mid/msb) */
val = inb(dev->iobase + MULTIQ3_ENC_DATA_REG);
val |= (inb(dev->iobase + MULTIQ3_ENC_DATA_REG) << 8);
val |= (inb(dev->iobase + MULTIQ3_ENC_DATA_REG) << 16);
/*
* Munge the data so that the reset value is in the middle
* of the maxdata range, i.e.:
*
* real value comedi value
* 0xffffff 0x7fffff 1 negative count
* 0x000000 0x800000 reset value
* 0x000001 0x800001 1 positive count
*
* It's possible for the 24-bit counter to overflow but it
* would normally take _quite_ a few turns. A 2000 line
* encoder in quadrature results in 8000 counts/rev. So about
* 1048 turns in either direction can be measured without
* an overflow.
*/
data[i] = (val + ((s->maxdata + 1) >> 1)) & s->maxdata;
}
return insn->n;
}
static void multiq3_encoder_reset(struct comedi_device *dev,
unsigned int chan)
{
multiq3_set_ctrl(dev, MULTIQ3_CTRL_EN | MULTIQ3_CTRL_E_CHAN(chan));
outb(MULTIQ3_EFLAG_RESET, dev->iobase + MULTIQ3_ENC_CTRL_REG);
outb(MULTIQ3_BP_RESET, dev->iobase + MULTIQ3_ENC_CTRL_REG);
outb(MULTIQ3_CLOCK_DATA, dev->iobase + MULTIQ3_ENC_DATA_REG);
outb(MULTIQ3_CLOCK_SETUP, dev->iobase + MULTIQ3_ENC_CTRL_REG);
outb(MULTIQ3_INPUT_SETUP, dev->iobase + MULTIQ3_ENC_CTRL_REG);
outb(MULTIQ3_QUAD_X4, dev->iobase + MULTIQ3_ENC_CTRL_REG);
outb(MULTIQ3_CNTR_RESET, dev->iobase + MULTIQ3_ENC_CTRL_REG);
}
static int multiq3_encoder_insn_config(struct comedi_device *dev,
struct comedi_subdevice *s,
struct comedi_insn *insn,
unsigned int *data)
{
unsigned int chan = CR_CHAN(insn->chanspec);
switch (data[0]) {
case INSN_CONFIG_RESET:
multiq3_encoder_reset(dev, chan);
break;
default:
return -EINVAL;
}
return insn->n;
}
static int multiq3_attach(struct comedi_device *dev,
struct comedi_devconfig *it)
{
struct comedi_subdevice *s;
int ret;
int i;
ret = comedi_request_region(dev, it->options[0], 0x10);
if (ret)
return ret;
ret = comedi_alloc_subdevices(dev, 5);
if (ret)
return ret;
/* Analog Input subdevice */
s = &dev->subdevices[0];
s->type = COMEDI_SUBD_AI;
s->subdev_flags = SDF_READABLE | SDF_GROUND;
s->n_chan = 8;
s->maxdata = 0x1fff;
s->range_table = &range_bipolar5;
s->insn_read = multiq3_ai_insn_read;
/* Analog Output subdevice */
s = &dev->subdevices[1];
s->type = COMEDI_SUBD_AO;
s->subdev_flags = SDF_WRITABLE;
s->n_chan = 8;
s->maxdata = 0x0fff;
s->range_table = &range_bipolar5;
s->insn_write = multiq3_ao_insn_write;
ret = comedi_alloc_subdev_readback(s);
if (ret)
return ret;
/* Digital Input subdevice */
s = &dev->subdevices[2];
s->type = COMEDI_SUBD_DI;
s->subdev_flags = SDF_READABLE;
s->n_chan = 16;
s->maxdata = 1;
s->range_table = &range_digital;
s->insn_bits = multiq3_di_insn_bits;
/* Digital Output subdevice */
s = &dev->subdevices[3];
s->type = COMEDI_SUBD_DO;
s->subdev_flags = SDF_WRITABLE;
s->n_chan = 16;
s->maxdata = 1;
s->range_table = &range_digital;
s->insn_bits = multiq3_do_insn_bits;
/* Encoder (Counter) subdevice */
s = &dev->subdevices[4];
s->type = COMEDI_SUBD_COUNTER;
s->subdev_flags = SDF_READABLE | SDF_LSAMPL;
s->n_chan = it->options[2] * 2;
s->maxdata = 0x00ffffff;
s->range_table = &range_unknown;
s->insn_read = multiq3_encoder_insn_read;
s->insn_config = multiq3_encoder_insn_config;
for (i = 0; i < s->n_chan; i++)
multiq3_encoder_reset(dev, i);
return 0;
}
static struct comedi_driver multiq3_driver = {
.driver_name = "multiq3",
.module = THIS_MODULE,
.attach = multiq3_attach,
.detach = comedi_legacy_detach,
};
module_comedi_driver(multiq3_driver);
MODULE_AUTHOR("Comedi https://www.comedi.org");
MODULE_DESCRIPTION("Comedi driver for Quanser Consulting MultiQ-3 board");
MODULE_LICENSE("GPL");
|
// SPDX-License-Identifier: GPL-2.0-only
/*
* Kernel Panic LED Trigger
*
* Copyright 2016 Ezequiel Garcia <[email protected]>
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/notifier.h>
#include <linux/panic_notifier.h>
#include <linux/leds.h>
#include "../leds.h"
static struct led_trigger *trigger;
/*
* This is called in a special context by the atomic panic
* notifier. This means the trigger can be changed without
* worrying about locking.
*/
static void led_trigger_set_panic(struct led_classdev *led_cdev)
{
if (led_cdev->trigger)
list_del(&led_cdev->trig_list);
list_add_tail(&led_cdev->trig_list, &trigger->led_cdevs);
/* Avoid the delayed blink path */
led_cdev->blink_delay_on = 0;
led_cdev->blink_delay_off = 0;
led_cdev->trigger = trigger;
}
static int led_trigger_panic_notifier(struct notifier_block *nb,
unsigned long code, void *unused)
{
struct led_classdev *led_cdev;
list_for_each_entry(led_cdev, &leds_list, node)
if (led_cdev->flags & LED_PANIC_INDICATOR)
led_trigger_set_panic(led_cdev);
return NOTIFY_DONE;
}
static struct notifier_block led_trigger_panic_nb = {
.notifier_call = led_trigger_panic_notifier,
};
static long led_panic_blink(int state)
{
led_trigger_event(trigger, state ? LED_FULL : LED_OFF);
return 0;
}
static int __init ledtrig_panic_init(void)
{
led_trigger_register_simple("panic", &trigger);
if (!trigger)
return -ENOMEM;
atomic_notifier_chain_register(&panic_notifier_list,
&led_trigger_panic_nb);
panic_blink = led_panic_blink;
return 0;
}
device_initcall(ledtrig_panic_init);
|
/*
* Copyright 2012 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Ben Skeggs
*/
#include "nouveau_drv.h"
#include "nouveau_dma.h"
#include "nouveau_fence.h"
#include "nouveau_vmm.h"
#include "nv50_display.h"
#include <nvif/push206e.h>
#include <nvhw/class/cl826f.h>
static int
nv84_fence_emit32(struct nouveau_channel *chan, u64 virtual, u32 sequence)
{
struct nvif_push *push = &chan->chan.push;
int ret = PUSH_WAIT(push, 8);
if (ret == 0) {
PUSH_MTHD(push, NV826F, SET_CONTEXT_DMA_SEMAPHORE, chan->vram.handle);
PUSH_MTHD(push, NV826F, SEMAPHOREA,
NVVAL(NV826F, SEMAPHOREA, OFFSET_UPPER, upper_32_bits(virtual)),
SEMAPHOREB, lower_32_bits(virtual),
SEMAPHOREC, sequence,
SEMAPHORED,
NVDEF(NV826F, SEMAPHORED, OPERATION, RELEASE),
NON_STALLED_INTERRUPT, 0);
PUSH_KICK(push);
}
return ret;
}
static int
nv84_fence_sync32(struct nouveau_channel *chan, u64 virtual, u32 sequence)
{
struct nvif_push *push = &chan->chan.push;
int ret = PUSH_WAIT(push, 7);
if (ret == 0) {
PUSH_MTHD(push, NV826F, SET_CONTEXT_DMA_SEMAPHORE, chan->vram.handle);
PUSH_MTHD(push, NV826F, SEMAPHOREA,
NVVAL(NV826F, SEMAPHOREA, OFFSET_UPPER, upper_32_bits(virtual)),
SEMAPHOREB, lower_32_bits(virtual),
SEMAPHOREC, sequence,
SEMAPHORED,
NVDEF(NV826F, SEMAPHORED, OPERATION, ACQ_GEQ));
PUSH_KICK(push);
}
return ret;
}
static inline u32
nv84_fence_chid(struct nouveau_channel *chan)
{
return chan->cli->drm->runl[chan->runlist].chan_id_base + chan->chid;
}
static int
nv84_fence_emit(struct nouveau_fence *fence)
{
struct nouveau_channel *chan = fence->channel;
struct nv84_fence_chan *fctx = chan->fence;
u64 addr = fctx->vma->addr + nv84_fence_chid(chan) * 16;
return fctx->base.emit32(chan, addr, fence->base.seqno);
}
static int
nv84_fence_sync(struct nouveau_fence *fence,
struct nouveau_channel *prev, struct nouveau_channel *chan)
{
struct nv84_fence_chan *fctx = chan->fence;
u64 addr = fctx->vma->addr + nv84_fence_chid(prev) * 16;
return fctx->base.sync32(chan, addr, fence->base.seqno);
}
static u32
nv84_fence_read(struct nouveau_channel *chan)
{
struct nv84_fence_priv *priv = chan->cli->drm->fence;
return nouveau_bo_rd32(priv->bo, nv84_fence_chid(chan) * 16/4);
}
static void
nv84_fence_context_del(struct nouveau_channel *chan)
{
struct nv84_fence_priv *priv = chan->cli->drm->fence;
struct nv84_fence_chan *fctx = chan->fence;
nouveau_bo_wr32(priv->bo, nv84_fence_chid(chan) * 16 / 4, fctx->base.sequence);
mutex_lock(&priv->mutex);
nouveau_vma_del(&fctx->vma);
mutex_unlock(&priv->mutex);
nouveau_fence_context_del(&fctx->base);
chan->fence = NULL;
nouveau_fence_context_free(&fctx->base);
}
int
nv84_fence_context_new(struct nouveau_channel *chan)
{
struct nv84_fence_priv *priv = chan->cli->drm->fence;
struct nv84_fence_chan *fctx;
int ret;
fctx = chan->fence = kzalloc(sizeof(*fctx), GFP_KERNEL);
if (!fctx)
return -ENOMEM;
nouveau_fence_context_new(chan, &fctx->base);
fctx->base.emit = nv84_fence_emit;
fctx->base.sync = nv84_fence_sync;
fctx->base.read = nv84_fence_read;
fctx->base.emit32 = nv84_fence_emit32;
fctx->base.sync32 = nv84_fence_sync32;
fctx->base.sequence = nv84_fence_read(chan);
mutex_lock(&priv->mutex);
ret = nouveau_vma_new(priv->bo, chan->vmm, &fctx->vma);
mutex_unlock(&priv->mutex);
if (ret)
nv84_fence_context_del(chan);
return ret;
}
static bool
nv84_fence_suspend(struct nouveau_drm *drm)
{
struct nv84_fence_priv *priv = drm->fence;
int i;
priv->suspend = vmalloc(array_size(sizeof(u32), drm->chan_total));
if (priv->suspend) {
for (i = 0; i < drm->chan_total; i++)
priv->suspend[i] = nouveau_bo_rd32(priv->bo, i*4);
}
return priv->suspend != NULL;
}
static void
nv84_fence_resume(struct nouveau_drm *drm)
{
struct nv84_fence_priv *priv = drm->fence;
int i;
if (priv->suspend) {
for (i = 0; i < drm->chan_total; i++)
nouveau_bo_wr32(priv->bo, i*4, priv->suspend[i]);
vfree(priv->suspend);
priv->suspend = NULL;
}
}
static void
nv84_fence_destroy(struct nouveau_drm *drm)
{
struct nv84_fence_priv *priv = drm->fence;
nouveau_bo_unmap(priv->bo);
if (priv->bo)
nouveau_bo_unpin(priv->bo);
nouveau_bo_fini(priv->bo);
drm->fence = NULL;
kfree(priv);
}
int
nv84_fence_create(struct nouveau_drm *drm)
{
struct nv84_fence_priv *priv;
u32 domain;
int ret;
priv = drm->fence = kzalloc(sizeof(*priv), GFP_KERNEL);
if (!priv)
return -ENOMEM;
priv->base.dtor = nv84_fence_destroy;
priv->base.suspend = nv84_fence_suspend;
priv->base.resume = nv84_fence_resume;
priv->base.context_new = nv84_fence_context_new;
priv->base.context_del = nv84_fence_context_del;
priv->base.uevent = true;
mutex_init(&priv->mutex);
/* Use VRAM if there is any ; otherwise fallback to system memory */
domain = drm->client.device.info.ram_size != 0 ?
NOUVEAU_GEM_DOMAIN_VRAM :
/*
* fences created in sysmem must be non-cached or we
* will lose CPU/GPU coherency!
*/
NOUVEAU_GEM_DOMAIN_GART | NOUVEAU_GEM_DOMAIN_COHERENT;
ret = nouveau_bo_new(&drm->client, 16 * drm->chan_total, 0,
domain, 0, 0, NULL, NULL, &priv->bo);
if (ret == 0) {
ret = nouveau_bo_pin(priv->bo, domain, false);
if (ret == 0) {
ret = nouveau_bo_map(priv->bo);
if (ret)
nouveau_bo_unpin(priv->bo);
}
if (ret)
nouveau_bo_fini(priv->bo);
}
if (ret)
nv84_fence_destroy(drm);
return ret;
}
|
/*
* Copyright (C) 2017 Chen-Yu Tsai <[email protected]>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef _DT_BINDINGS_RESET_SUN8I_A83T_CCU_H_
#define _DT_BINDINGS_RESET_SUN8I_A83T_CCU_H_
#define RST_USB_PHY0 0
#define RST_USB_PHY1 1
#define RST_USB_HSIC 2
#define RST_DRAM 3
#define RST_MBUS 4
#define RST_BUS_MIPI_DSI 5
#define RST_BUS_SS 6
#define RST_BUS_DMA 7
#define RST_BUS_MMC0 8
#define RST_BUS_MMC1 9
#define RST_BUS_MMC2 10
#define RST_BUS_NAND 11
#define RST_BUS_DRAM 12
#define RST_BUS_EMAC 13
#define RST_BUS_HSTIMER 14
#define RST_BUS_SPI0 15
#define RST_BUS_SPI1 16
#define RST_BUS_OTG 17
#define RST_BUS_EHCI0 18
#define RST_BUS_EHCI1 19
#define RST_BUS_OHCI0 20
#define RST_BUS_VE 21
#define RST_BUS_TCON0 22
#define RST_BUS_TCON1 23
#define RST_BUS_CSI 24
#define RST_BUS_HDMI0 25
#define RST_BUS_HDMI1 26
#define RST_BUS_DE 27
#define RST_BUS_GPU 28
#define RST_BUS_MSGBOX 29
#define RST_BUS_SPINLOCK 30
#define RST_BUS_LVDS 31
#define RST_BUS_SPDIF 32
#define RST_BUS_I2S0 33
#define RST_BUS_I2S1 34
#define RST_BUS_I2S2 35
#define RST_BUS_TDM 36
#define RST_BUS_I2C0 37
#define RST_BUS_I2C1 38
#define RST_BUS_I2C2 39
#define RST_BUS_UART0 40
#define RST_BUS_UART1 41
#define RST_BUS_UART2 42
#define RST_BUS_UART3 43
#define RST_BUS_UART4 44
#endif /* _DT_BINDINGS_RESET_SUN8I_A83T_CCU_H_ */
|
// SPDX-License-Identifier: GPL-2.0-only
/*
* OCB mode implementation
*
* Copyright: (c) 2014 Czech Technical University in Prague
* (c) 2014 Volkswagen Group Research
* Copyright (C) 2022 - 2024 Intel Corporation
* Author: Rostislav Lisovy <[email protected]>
* Funded by: Volkswagen Group Research
*/
#include <linux/delay.h>
#include <linux/if_ether.h>
#include <linux/skbuff.h>
#include <linux/if_arp.h>
#include <linux/etherdevice.h>
#include <linux/rtnetlink.h>
#include <net/mac80211.h>
#include <linux/unaligned.h>
#include "ieee80211_i.h"
#include "driver-ops.h"
#include "rate.h"
#define IEEE80211_OCB_HOUSEKEEPING_INTERVAL (60 * HZ)
#define IEEE80211_OCB_PEER_INACTIVITY_LIMIT (240 * HZ)
#define IEEE80211_OCB_MAX_STA_ENTRIES 128
/**
* enum ocb_deferred_task_flags - mac80211 OCB deferred tasks
* @OCB_WORK_HOUSEKEEPING: run the periodic OCB housekeeping tasks
*
* These flags are used in @wrkq_flags field of &struct ieee80211_if_ocb
*/
enum ocb_deferred_task_flags {
OCB_WORK_HOUSEKEEPING,
};
void ieee80211_ocb_rx_no_sta(struct ieee80211_sub_if_data *sdata,
const u8 *bssid, const u8 *addr,
u32 supp_rates)
{
struct ieee80211_if_ocb *ifocb = &sdata->u.ocb;
struct ieee80211_local *local = sdata->local;
struct ieee80211_chanctx_conf *chanctx_conf;
struct ieee80211_supported_band *sband;
struct sta_info *sta;
int band;
/* XXX: Consider removing the least recently used entry and
* allow new one to be added.
*/
if (local->num_sta >= IEEE80211_OCB_MAX_STA_ENTRIES) {
net_info_ratelimited("%s: No room for a new OCB STA entry %pM\n",
sdata->name, addr);
return;
}
ocb_dbg(sdata, "Adding new OCB station %pM\n", addr);
rcu_read_lock();
chanctx_conf = rcu_dereference(sdata->vif.bss_conf.chanctx_conf);
if (WARN_ON_ONCE(!chanctx_conf)) {
rcu_read_unlock();
return;
}
band = chanctx_conf->def.chan->band;
rcu_read_unlock();
sta = sta_info_alloc(sdata, addr, GFP_ATOMIC);
if (!sta)
return;
/* Add only mandatory rates for now */
sband = local->hw.wiphy->bands[band];
sta->sta.deflink.supp_rates[band] = ieee80211_mandatory_rates(sband);
spin_lock(&ifocb->incomplete_lock);
list_add(&sta->list, &ifocb->incomplete_stations);
spin_unlock(&ifocb->incomplete_lock);
wiphy_work_queue(local->hw.wiphy, &sdata->work);
}
static struct sta_info *ieee80211_ocb_finish_sta(struct sta_info *sta)
__acquires(RCU)
{
struct ieee80211_sub_if_data *sdata = sta->sdata;
u8 addr[ETH_ALEN];
memcpy(addr, sta->sta.addr, ETH_ALEN);
ocb_dbg(sdata, "Adding new IBSS station %pM (dev=%s)\n",
addr, sdata->name);
sta_info_move_state(sta, IEEE80211_STA_AUTH);
sta_info_move_state(sta, IEEE80211_STA_ASSOC);
sta_info_move_state(sta, IEEE80211_STA_AUTHORIZED);
rate_control_rate_init(&sta->deflink);
/* If it fails, maybe we raced another insertion? */
if (sta_info_insert_rcu(sta))
return sta_info_get(sdata, addr);
return sta;
}
static void ieee80211_ocb_housekeeping(struct ieee80211_sub_if_data *sdata)
{
struct ieee80211_if_ocb *ifocb = &sdata->u.ocb;
ocb_dbg(sdata, "Running ocb housekeeping\n");
ieee80211_sta_expire(sdata, IEEE80211_OCB_PEER_INACTIVITY_LIMIT);
mod_timer(&ifocb->housekeeping_timer,
round_jiffies(jiffies + IEEE80211_OCB_HOUSEKEEPING_INTERVAL));
}
void ieee80211_ocb_work(struct ieee80211_sub_if_data *sdata)
{
struct ieee80211_if_ocb *ifocb = &sdata->u.ocb;
struct sta_info *sta;
lockdep_assert_wiphy(sdata->local->hw.wiphy);
if (ifocb->joined != true)
return;
spin_lock_bh(&ifocb->incomplete_lock);
while (!list_empty(&ifocb->incomplete_stations)) {
sta = list_first_entry(&ifocb->incomplete_stations,
struct sta_info, list);
list_del(&sta->list);
spin_unlock_bh(&ifocb->incomplete_lock);
ieee80211_ocb_finish_sta(sta);
rcu_read_unlock();
spin_lock_bh(&ifocb->incomplete_lock);
}
spin_unlock_bh(&ifocb->incomplete_lock);
if (test_and_clear_bit(OCB_WORK_HOUSEKEEPING, &ifocb->wrkq_flags))
ieee80211_ocb_housekeeping(sdata);
}
static void ieee80211_ocb_housekeeping_timer(struct timer_list *t)
{
struct ieee80211_sub_if_data *sdata =
from_timer(sdata, t, u.ocb.housekeeping_timer);
struct ieee80211_local *local = sdata->local;
struct ieee80211_if_ocb *ifocb = &sdata->u.ocb;
set_bit(OCB_WORK_HOUSEKEEPING, &ifocb->wrkq_flags);
wiphy_work_queue(local->hw.wiphy, &sdata->work);
}
void ieee80211_ocb_setup_sdata(struct ieee80211_sub_if_data *sdata)
{
struct ieee80211_if_ocb *ifocb = &sdata->u.ocb;
timer_setup(&ifocb->housekeeping_timer,
ieee80211_ocb_housekeeping_timer, 0);
INIT_LIST_HEAD(&ifocb->incomplete_stations);
spin_lock_init(&ifocb->incomplete_lock);
}
int ieee80211_ocb_join(struct ieee80211_sub_if_data *sdata,
struct ocb_setup *setup)
{
struct ieee80211_chan_req chanreq = { .oper = setup->chandef };
struct ieee80211_local *local = sdata->local;
struct ieee80211_if_ocb *ifocb = &sdata->u.ocb;
u64 changed = BSS_CHANGED_OCB | BSS_CHANGED_BSSID;
int err;
lockdep_assert_wiphy(sdata->local->hw.wiphy);
if (ifocb->joined == true)
return -EINVAL;
sdata->deflink.operating_11g_mode = true;
sdata->deflink.smps_mode = IEEE80211_SMPS_OFF;
sdata->deflink.needed_rx_chains = sdata->local->rx_chains;
err = ieee80211_link_use_channel(&sdata->deflink, &chanreq,
IEEE80211_CHANCTX_SHARED);
if (err)
return err;
ieee80211_bss_info_change_notify(sdata, changed);
ifocb->joined = true;
set_bit(OCB_WORK_HOUSEKEEPING, &ifocb->wrkq_flags);
wiphy_work_queue(local->hw.wiphy, &sdata->work);
netif_carrier_on(sdata->dev);
return 0;
}
int ieee80211_ocb_leave(struct ieee80211_sub_if_data *sdata)
{
struct ieee80211_if_ocb *ifocb = &sdata->u.ocb;
struct ieee80211_local *local = sdata->local;
struct sta_info *sta;
lockdep_assert_wiphy(sdata->local->hw.wiphy);
ifocb->joined = false;
sta_info_flush(sdata, -1);
spin_lock_bh(&ifocb->incomplete_lock);
while (!list_empty(&ifocb->incomplete_stations)) {
sta = list_first_entry(&ifocb->incomplete_stations,
struct sta_info, list);
list_del(&sta->list);
spin_unlock_bh(&ifocb->incomplete_lock);
sta_info_free(local, sta);
spin_lock_bh(&ifocb->incomplete_lock);
}
spin_unlock_bh(&ifocb->incomplete_lock);
netif_carrier_off(sdata->dev);
clear_bit(SDATA_STATE_OFFCHANNEL, &sdata->state);
ieee80211_bss_info_change_notify(sdata, BSS_CHANGED_OCB);
ieee80211_link_release_channel(&sdata->deflink);
skb_queue_purge(&sdata->skb_queue);
del_timer_sync(&sdata->u.ocb.housekeeping_timer);
/* If the timer fired while we waited for it, it will have
* requeued the work. Now the work will be running again
* but will not rearm the timer again because it checks
* whether we are connected to the network or not -- at this
* point we shouldn't be anymore.
*/
return 0;
}
|
// SPDX-License-Identifier: LGPL-2.1
#ifndef EFD_SEMAPHORE
#define EFD_SEMAPHORE 1
#endif
#ifndef EFD_NONBLOCK
#define EFD_NONBLOCK 00004000
#endif
#ifndef EFD_CLOEXEC
#define EFD_CLOEXEC 02000000
#endif
static size_t syscall_arg__scnprintf_eventfd_flags(char *bf, size_t size, struct syscall_arg *arg)
{
bool show_prefix = arg->show_string_prefix;
const char *prefix = "EFD_";
int printed = 0, flags = arg->val;
if (flags == 0)
return scnprintf(bf, size, "NONE");
#define P_FLAG(n) \
if (flags & EFD_##n) { \
printed += scnprintf(bf + printed, size - printed, "%s%s%s", printed ? "|" : "", show_prefix ? prefix : "", #n); \
flags &= ~EFD_##n; \
}
P_FLAG(SEMAPHORE);
P_FLAG(CLOEXEC);
P_FLAG(NONBLOCK);
#undef P_FLAG
if (flags)
printed += scnprintf(bf + printed, size - printed, "%s%#x", printed ? "|" : "", flags);
return printed;
}
#define SCA_EFD_FLAGS syscall_arg__scnprintf_eventfd_flags
|
/*
* Copyright 2015 Advanced Micro Devices, Inc.
* All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the
* "Software"), to deal in the Software without restriction, including
* without limitation the rights to use, copy, modify, merge, publish,
* distribute, sub license, and/or sell copies of the Software, and to
* permit persons to whom the Software is furnished to do so, subject to
* the following conditions:
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
* OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
* USE OR OTHER DEALINGS IN THE SOFTWARE.
*
* The above copyright notice and this permission notice (including the
* next paragraph) shall be included in all copies or substantial portions
* of the Software.
*
*/
/*
* Authors:
* Christian König <[email protected]>
*/
#include <linux/sort.h>
#include <linux/uaccess.h>
#include "amdgpu.h"
#include "amdgpu_trace.h"
#define AMDGPU_BO_LIST_MAX_PRIORITY 32u
#define AMDGPU_BO_LIST_NUM_BUCKETS (AMDGPU_BO_LIST_MAX_PRIORITY + 1)
static void amdgpu_bo_list_free_rcu(struct rcu_head *rcu)
{
struct amdgpu_bo_list *list = container_of(rcu, struct amdgpu_bo_list,
rhead);
mutex_destroy(&list->bo_list_mutex);
kvfree(list);
}
static void amdgpu_bo_list_free(struct kref *ref)
{
struct amdgpu_bo_list *list = container_of(ref, struct amdgpu_bo_list,
refcount);
struct amdgpu_bo_list_entry *e;
amdgpu_bo_list_for_each_entry(e, list)
amdgpu_bo_unref(&e->bo);
call_rcu(&list->rhead, amdgpu_bo_list_free_rcu);
}
static int amdgpu_bo_list_entry_cmp(const void *_a, const void *_b)
{
const struct amdgpu_bo_list_entry *a = _a, *b = _b;
if (a->priority > b->priority)
return 1;
if (a->priority < b->priority)
return -1;
return 0;
}
int amdgpu_bo_list_create(struct amdgpu_device *adev, struct drm_file *filp,
struct drm_amdgpu_bo_list_entry *info,
size_t num_entries, struct amdgpu_bo_list **result)
{
unsigned last_entry = 0, first_userptr = num_entries;
struct amdgpu_bo_list_entry *array;
struct amdgpu_bo_list *list;
uint64_t total_size = 0;
unsigned i;
int r;
list = kvzalloc(struct_size(list, entries, num_entries), GFP_KERNEL);
if (!list)
return -ENOMEM;
kref_init(&list->refcount);
list->num_entries = num_entries;
array = list->entries;
for (i = 0; i < num_entries; ++i) {
struct amdgpu_bo_list_entry *entry;
struct drm_gem_object *gobj;
struct amdgpu_bo *bo;
struct mm_struct *usermm;
gobj = drm_gem_object_lookup(filp, info[i].bo_handle);
if (!gobj) {
r = -ENOENT;
goto error_free;
}
bo = amdgpu_bo_ref(gem_to_amdgpu_bo(gobj));
drm_gem_object_put(gobj);
usermm = amdgpu_ttm_tt_get_usermm(bo->tbo.ttm);
if (usermm) {
if (usermm != current->mm) {
amdgpu_bo_unref(&bo);
r = -EPERM;
goto error_free;
}
entry = &array[--first_userptr];
} else {
entry = &array[last_entry++];
}
entry->priority = min(info[i].bo_priority,
AMDGPU_BO_LIST_MAX_PRIORITY);
entry->bo = bo;
if (bo->preferred_domains == AMDGPU_GEM_DOMAIN_GDS)
list->gds_obj = bo;
if (bo->preferred_domains == AMDGPU_GEM_DOMAIN_GWS)
list->gws_obj = bo;
if (bo->preferred_domains == AMDGPU_GEM_DOMAIN_OA)
list->oa_obj = bo;
total_size += amdgpu_bo_size(bo);
trace_amdgpu_bo_list_set(list, bo);
}
list->first_userptr = first_userptr;
sort(array, last_entry, sizeof(struct amdgpu_bo_list_entry),
amdgpu_bo_list_entry_cmp, NULL);
trace_amdgpu_cs_bo_status(list->num_entries, total_size);
mutex_init(&list->bo_list_mutex);
*result = list;
return 0;
error_free:
for (i = 0; i < last_entry; ++i)
amdgpu_bo_unref(&array[i].bo);
for (i = first_userptr; i < num_entries; ++i)
amdgpu_bo_unref(&array[i].bo);
kvfree(list);
return r;
}
static void amdgpu_bo_list_destroy(struct amdgpu_fpriv *fpriv, int id)
{
struct amdgpu_bo_list *list;
mutex_lock(&fpriv->bo_list_lock);
list = idr_remove(&fpriv->bo_list_handles, id);
mutex_unlock(&fpriv->bo_list_lock);
if (list)
kref_put(&list->refcount, amdgpu_bo_list_free);
}
int amdgpu_bo_list_get(struct amdgpu_fpriv *fpriv, int id,
struct amdgpu_bo_list **result)
{
rcu_read_lock();
*result = idr_find(&fpriv->bo_list_handles, id);
if (*result && kref_get_unless_zero(&(*result)->refcount)) {
rcu_read_unlock();
return 0;
}
rcu_read_unlock();
*result = NULL;
return -ENOENT;
}
void amdgpu_bo_list_put(struct amdgpu_bo_list *list)
{
kref_put(&list->refcount, amdgpu_bo_list_free);
}
int amdgpu_bo_create_list_entry_array(struct drm_amdgpu_bo_list_in *in,
struct drm_amdgpu_bo_list_entry **info_param)
{
const void __user *uptr = u64_to_user_ptr(in->bo_info_ptr);
const uint32_t info_size = sizeof(struct drm_amdgpu_bo_list_entry);
struct drm_amdgpu_bo_list_entry *info;
int r;
info = kvmalloc_array(in->bo_number, info_size, GFP_KERNEL);
if (!info)
return -ENOMEM;
/* copy the handle array from userspace to a kernel buffer */
r = -EFAULT;
if (likely(info_size == in->bo_info_size)) {
unsigned long bytes = in->bo_number *
in->bo_info_size;
if (copy_from_user(info, uptr, bytes))
goto error_free;
} else {
unsigned long bytes = min(in->bo_info_size, info_size);
unsigned i;
memset(info, 0, in->bo_number * info_size);
for (i = 0; i < in->bo_number; ++i) {
if (copy_from_user(&info[i], uptr, bytes))
goto error_free;
uptr += in->bo_info_size;
}
}
*info_param = info;
return 0;
error_free:
kvfree(info);
return r;
}
int amdgpu_bo_list_ioctl(struct drm_device *dev, void *data,
struct drm_file *filp)
{
struct amdgpu_device *adev = drm_to_adev(dev);
struct amdgpu_fpriv *fpriv = filp->driver_priv;
union drm_amdgpu_bo_list *args = data;
uint32_t handle = args->in.list_handle;
struct drm_amdgpu_bo_list_entry *info = NULL;
struct amdgpu_bo_list *list, *old;
int r;
r = amdgpu_bo_create_list_entry_array(&args->in, &info);
if (r)
return r;
switch (args->in.operation) {
case AMDGPU_BO_LIST_OP_CREATE:
r = amdgpu_bo_list_create(adev, filp, info, args->in.bo_number,
&list);
if (r)
goto error_free;
mutex_lock(&fpriv->bo_list_lock);
r = idr_alloc(&fpriv->bo_list_handles, list, 1, 0, GFP_KERNEL);
mutex_unlock(&fpriv->bo_list_lock);
if (r < 0) {
goto error_put_list;
}
handle = r;
break;
case AMDGPU_BO_LIST_OP_DESTROY:
amdgpu_bo_list_destroy(fpriv, handle);
handle = 0;
break;
case AMDGPU_BO_LIST_OP_UPDATE:
r = amdgpu_bo_list_create(adev, filp, info, args->in.bo_number,
&list);
if (r)
goto error_free;
mutex_lock(&fpriv->bo_list_lock);
old = idr_replace(&fpriv->bo_list_handles, list, handle);
mutex_unlock(&fpriv->bo_list_lock);
if (IS_ERR(old)) {
r = PTR_ERR(old);
goto error_put_list;
}
amdgpu_bo_list_put(old);
break;
default:
r = -EINVAL;
goto error_free;
}
memset(args, 0, sizeof(*args));
args->out.list_handle = handle;
kvfree(info);
return 0;
error_put_list:
amdgpu_bo_list_put(list);
error_free:
kvfree(info);
return r;
}
|
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Imagination E5010 JPEG Encoder driver.
*
* Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/
*
* Author: David Huang <[email protected]>
* Author: Devarsh Thakkar <[email protected]>
*/
#ifndef _E5010_JPEG_ENC_HW_H
#define _E5010_JPEG_ENC_HW_H
#include "e5010-core-regs.h"
#include "e5010-mmu-regs.h"
int e5010_hw_enable_output_address_error_irq(void __iomem *core_offset, u32 enable);
int e5010_hw_enable_picture_done_irq(void __iomem *core_offset, u32 enable);
int e5010_hw_enable_auto_clock_gating(void __iomem *core_offset, u32 enable);
int e5010_hw_enable_manual_clock_gating(void __iomem *core_offset, u32 enable);
int e5010_hw_enable_crc_check(void __iomem *core_offset, u32 enable);
int e5010_hw_set_input_source_to_memory(void __iomem *core_offset, u32 set);
int e5010_hw_set_input_luma_addr(void __iomem *core_offset, u32 val);
int e5010_hw_set_input_chroma_addr(void __iomem *core_offset, u32 val);
int e5010_hw_set_output_base_addr(void __iomem *core_offset, u32 val);
int e5010_hw_get_output_size(void __iomem *core_offset);
int e5010_hw_set_horizontal_size(void __iomem *core_offset, u32 val);
int e5010_hw_set_vertical_size(void __iomem *core_offset, u32 val);
int e5010_hw_set_luma_stride(void __iomem *core_offset, u32 bytesperline);
int e5010_hw_set_chroma_stride(void __iomem *core_offset, u32 bytesperline);
int e5010_hw_set_input_subsampling(void __iomem *core_offset, u32 val);
int e5010_hw_set_chroma_order(void __iomem *core_offset, u32 val);
int e5010_hw_set_qpvalue(void __iomem *core_offset, u32 offset, u32 value);
void e5010_reset(struct device *dev, void __iomem *core_offset, void __iomem *mmu_offset);
void e5010_hw_set_output_max_size(void __iomem *core_offset, u32 val);
void e5010_hw_clear_picture_done(void __iomem *core_offset, u32 clear);
void e5010_hw_encode_start(void __iomem *core_offset, u32 start);
void e5010_hw_clear_output_error(void __iomem *core_offset, u32 clear);
void e5010_hw_bypass_mmu(void __iomem *mmu_base, u32 enable);
bool e5010_hw_pic_done_irq(void __iomem *core_base);
bool e5010_hw_output_address_irq(void __iomem *core_base);
#endif
|
// SPDX-License-Identifier: GPL-2.0+ OR MIT
/*
* Apple iPhone 5s (LTE), N53, iPhone6,2 (A1457/A1518/A1528/A1530)
* Copyright (c) 2022, Konrad Dybcio <[email protected]>
*/
/dts-v1/;
#include "s5l8960x-5s.dtsi"
/ {
compatible = "apple,n53", "apple,s5l8960x", "apple,arm-platform";
model = "Apple iPhone 5s (LTE)";
};
|
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2014 Samsung Electronics Co., Ltd.
* Copyright (c) 2016 Krzysztof Kozlowski
*
* Device Tree binding constants for Exynos5421 clock controller.
*/
#ifndef _DT_BINDINGS_CLOCK_EXYNOS_5410_H
#define _DT_BINDINGS_CLOCK_EXYNOS_5410_H
/* core clocks */
#define CLK_FIN_PLL 1
#define CLK_FOUT_APLL 2
#define CLK_FOUT_CPLL 3
#define CLK_FOUT_MPLL 4
#define CLK_FOUT_BPLL 5
#define CLK_FOUT_KPLL 6
#define CLK_FOUT_EPLL 7
/* gate for special clocks (sclk) */
#define CLK_SCLK_UART0 128
#define CLK_SCLK_UART1 129
#define CLK_SCLK_UART2 130
#define CLK_SCLK_UART3 131
#define CLK_SCLK_MMC0 132
#define CLK_SCLK_MMC1 133
#define CLK_SCLK_MMC2 134
#define CLK_SCLK_USBD300 150
#define CLK_SCLK_USBD301 151
#define CLK_SCLK_USBPHY300 152
#define CLK_SCLK_USBPHY301 153
#define CLK_SCLK_PWM 155
/* gate clocks */
#define CLK_UART0 257
#define CLK_UART1 258
#define CLK_UART2 259
#define CLK_UART3 260
#define CLK_I2C0 261
#define CLK_I2C1 262
#define CLK_I2C2 263
#define CLK_I2C3 264
#define CLK_USI0 265
#define CLK_USI1 266
#define CLK_USI2 267
#define CLK_USI3 268
#define CLK_TSADC 270
#define CLK_PWM 279
#define CLK_MCT 315
#define CLK_WDT 316
#define CLK_RTC 317
#define CLK_TMU 318
#define CLK_MMC0 351
#define CLK_MMC1 352
#define CLK_MMC2 353
#define CLK_PDMA0 362
#define CLK_PDMA1 363
#define CLK_USBH20 365
#define CLK_USBD300 366
#define CLK_USBD301 367
#define CLK_SSS 471
#endif /* _DT_BINDINGS_CLOCK_EXYNOS_5410_H */
|
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* max98371.h -- MAX98371 ALSA SoC Audio driver
*
* Copyright 2011-2012 Maxim Integrated Products
*/
#ifndef _MAX98371_H
#define _MAX98371_H
#define MAX98371_IRQ_CLEAR1 0x01
#define MAX98371_IRQ_CLEAR2 0x02
#define MAX98371_IRQ_CLEAR3 0x03
#define MAX98371_DAI_CLK 0x10
#define MAX98371_DAI_BSEL_MASK 0xF
#define MAX98371_DAI_BSEL_32 2
#define MAX98371_DAI_BSEL_48 3
#define MAX98371_DAI_BSEL_64 4
#define MAX98371_SPK_SR 0x11
#define MAX98371_SPK_SR_MASK 0xF
#define MAX98371_SPK_SR_32 6
#define MAX98371_SPK_SR_44 7
#define MAX98371_SPK_SR_48 8
#define MAX98371_SPK_SR_88 10
#define MAX98371_SPK_SR_96 11
#define MAX98371_DAI_CHANNEL 0x15
#define MAX98371_CHANNEL_MASK 0x3
#define MAX98371_MONOMIX_SRC 0x18
#define MAX98371_MONOMIX_CFG 0x19
#define MAX98371_HPF 0x1C
#define MAX98371_MONOMIX_SRC_MASK 0xFF
#define MONOMIX_RX_0_1 ((0x1)<<(4))
#define M98371_DAI_CHANNEL_I2S 0x3
#define MAX98371_DIGITAL_GAIN 0x2D
#define MAX98371_DIGITAL_GAIN_WIDTH 0x7
#define MAX98371_GAIN 0x2E
#define MAX98371_GAIN_SHIFT 0x4
#define MAX98371_GAIN_WIDTH 0x4
#define MAX98371_DHT_MAX_WIDTH 4
#define MAX98371_FMT 0x14
#define MAX98371_CHANSZ_WIDTH 6
#define MAX98371_FMT_MASK ((0x3)<<(MAX98371_CHANSZ_WIDTH))
#define MAX98371_FMT_MODE_MASK ((0x7)<<(3))
#define MAX98371_DAI_LEFT ((0x1)<<(3))
#define MAX98371_DAI_RIGHT ((0x2)<<(3))
#define MAX98371_DAI_CHANSZ_16 ((1)<<(MAX98371_CHANSZ_WIDTH))
#define MAX98371_DAI_CHANSZ_24 ((2)<<(MAX98371_CHANSZ_WIDTH))
#define MAX98371_DAI_CHANSZ_32 ((3)<<(MAX98371_CHANSZ_WIDTH))
#define MAX98371_DHT 0x32
#define MAX98371_DHT_STEP 0x3
#define MAX98371_DHT_GAIN 0x31
#define MAX98371_DHT_GAIN_WIDTH 0x4
#define MAX98371_DHT_ROT_WIDTH 0x4
#define MAX98371_SPK_ENABLE 0x4A
#define MAX98371_GLOBAL_ENABLE 0x50
#define MAX98371_SOFT_RESET 0x51
#define MAX98371_VERSION 0xFF
struct max98371_priv {
struct regmap *regmap;
};
#endif
|
/*
* QorIQ GPIO device tree stub [ controller @ offset 0x133000 ]
*
* Copyright 2013 Freescale Semiconductor Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Freescale Semiconductor nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
*
* ALTERNATIVELY, this software may be distributed under the terms of the
* GNU General Public License ("GPL") as published by the Free Software
* Foundation, either version 2 of that License or (at your option) any
* later version.
*
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
gpio3: gpio@133000 {
compatible = "fsl,qoriq-gpio";
reg = <0x133000 0x1000>;
interrupts = <87 2 0 0>;
#gpio-cells = <2>;
gpio-controller;
};
|
// SPDX-License-Identifier: GPL-2.0+ OR MIT
/*
* Apple iPad mini 2 common device tree
* Based on A7 (APL0698), up to 1.3GHz
*
* Copyright (c) 2022, Konrad Dybcio <[email protected]>
*/
#include "s5l8960x.dtsi"
#include "s5l8960x-common.dtsi"
#include <dt-bindings/input/input.h>
/ {
chassis-type = "tablet";
gpio-keys {
compatible = "gpio-keys";
button-home {
label = "Home Button";
gpios = <&pinctrl 2 GPIO_ACTIVE_LOW>;
linux,code = <KEY_HOMEPAGE>;
wakeup-source;
};
button-power {
label = "Power Button";
gpios = <&pinctrl 3 GPIO_ACTIVE_LOW>;
linux,code = <KEY_POWER>;
wakeup-source;
};
button-voldown {
label = "Volume Down";
gpios = <&pinctrl 5 GPIO_ACTIVE_LOW>;
linux,code = <KEY_VOLUMEDOWN>;
};
button-volup {
label = "Volume Up";
gpios = <&pinctrl 4 GPIO_ACTIVE_LOW>;
linux,code = <KEY_VOLUMEUP>;
};
switch-mute {
label = "Mute Switch";
gpios = <&pinctrl 6 GPIO_ACTIVE_LOW>;
linux,code = <KEY_MUTE>;
};
};
};
|
/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* cx25840.h - definition for cx25840/1/2/3 inputs
*
* Copyright (C) 2006 Hans Verkuil ([email protected])
*/
#ifndef _CX25840_H_
#define _CX25840_H_
/*
* Note that the cx25840 driver requires that the bridge driver calls the
* v4l2_subdev's load_fw operation in order to load the driver's firmware.
* This will load the firmware on the first invocation (further ones are NOP).
* Without this the audio standard detection will fail and you will
* only get mono.
* Alternatively, you can call the reset operation (this can be done
* multiple times if needed, each invocation will fully reinitialize
* the device).
*
* Since loading the firmware is often problematic when the driver is
* compiled into the kernel I recommend postponing calling this function
* until the first open of the video device. Another reason for
* postponing it is that loading this firmware takes a long time (seconds)
* due to the slow i2c bus speed. So it will speed up the boot process if
* you can avoid loading the fw as long as the video device isn't used.
*/
enum cx25840_video_input {
/* Composite video inputs In1-In8 */
CX25840_COMPOSITE1 = 1,
CX25840_COMPOSITE2,
CX25840_COMPOSITE3,
CX25840_COMPOSITE4,
CX25840_COMPOSITE5,
CX25840_COMPOSITE6,
CX25840_COMPOSITE7,
CX25840_COMPOSITE8,
/*
* S-Video inputs consist of one luma input (In1-In8) ORed with one
* chroma input (In5-In8)
*/
CX25840_SVIDEO_LUMA1 = 0x10,
CX25840_SVIDEO_LUMA2 = 0x20,
CX25840_SVIDEO_LUMA3 = 0x30,
CX25840_SVIDEO_LUMA4 = 0x40,
CX25840_SVIDEO_LUMA5 = 0x50,
CX25840_SVIDEO_LUMA6 = 0x60,
CX25840_SVIDEO_LUMA7 = 0x70,
CX25840_SVIDEO_LUMA8 = 0x80,
CX25840_SVIDEO_CHROMA4 = 0x400,
CX25840_SVIDEO_CHROMA5 = 0x500,
CX25840_SVIDEO_CHROMA6 = 0x600,
CX25840_SVIDEO_CHROMA7 = 0x700,
CX25840_SVIDEO_CHROMA8 = 0x800,
/* S-Video aliases for common luma/chroma combinations */
CX25840_SVIDEO1 = 0x510,
CX25840_SVIDEO2 = 0x620,
CX25840_SVIDEO3 = 0x730,
CX25840_SVIDEO4 = 0x840,
/* Allow frames to specify specific input configurations */
CX25840_VIN1_CH1 = 0x80000000,
CX25840_VIN2_CH1 = 0x80000001,
CX25840_VIN3_CH1 = 0x80000002,
CX25840_VIN4_CH1 = 0x80000003,
CX25840_VIN5_CH1 = 0x80000004,
CX25840_VIN6_CH1 = 0x80000005,
CX25840_VIN7_CH1 = 0x80000006,
CX25840_VIN8_CH1 = 0x80000007,
CX25840_VIN4_CH2 = 0x80000000,
CX25840_VIN5_CH2 = 0x80000010,
CX25840_VIN6_CH2 = 0x80000020,
CX25840_NONE_CH2 = 0x80000030,
CX25840_VIN7_CH3 = 0x80000000,
CX25840_VIN8_CH3 = 0x80000040,
CX25840_NONE0_CH3 = 0x80000080,
CX25840_NONE1_CH3 = 0x800000c0,
CX25840_SVIDEO_ON = 0x80000100,
CX25840_COMPONENT_ON = 0x80000200,
CX25840_DIF_ON = 0x80000400,
};
/*
* The defines below are used to set the chip video output settings
* in the generic mode that can be enabled by calling the subdevice
* init core op.
*
* The requested settings can be passed to the init core op as
* @val parameter and to the s_routing video op as @config parameter.
*
* For details please refer to the section 3.7 Video Output Formatting and
* to Video Out Control 1 to 4 registers in the section 5.6 Video Decoder Core
* of the chip datasheet.
*/
#define CX25840_VCONFIG_FMT_SHIFT 0
#define CX25840_VCONFIG_FMT_MASK GENMASK(2, 0)
#define CX25840_VCONFIG_FMT_BT601 BIT(0)
#define CX25840_VCONFIG_FMT_BT656 BIT(1)
#define CX25840_VCONFIG_FMT_VIP11 GENMASK(1, 0)
#define CX25840_VCONFIG_FMT_VIP2 BIT(2)
#define CX25840_VCONFIG_RES_SHIFT 3
#define CX25840_VCONFIG_RES_MASK GENMASK(4, 3)
#define CX25840_VCONFIG_RES_8BIT BIT(3)
#define CX25840_VCONFIG_RES_10BIT BIT(4)
#define CX25840_VCONFIG_VBIRAW_SHIFT 5
#define CX25840_VCONFIG_VBIRAW_MASK GENMASK(6, 5)
#define CX25840_VCONFIG_VBIRAW_DISABLED BIT(5)
#define CX25840_VCONFIG_VBIRAW_ENABLED BIT(6)
#define CX25840_VCONFIG_ANCDATA_SHIFT 7
#define CX25840_VCONFIG_ANCDATA_MASK GENMASK(8, 7)
#define CX25840_VCONFIG_ANCDATA_DISABLED BIT(7)
#define CX25840_VCONFIG_ANCDATA_ENABLED BIT(8)
#define CX25840_VCONFIG_TASKBIT_SHIFT 9
#define CX25840_VCONFIG_TASKBIT_MASK GENMASK(10, 9)
#define CX25840_VCONFIG_TASKBIT_ZERO BIT(9)
#define CX25840_VCONFIG_TASKBIT_ONE BIT(10)
#define CX25840_VCONFIG_ACTIVE_SHIFT 11
#define CX25840_VCONFIG_ACTIVE_MASK GENMASK(12, 11)
#define CX25840_VCONFIG_ACTIVE_COMPOSITE BIT(11)
#define CX25840_VCONFIG_ACTIVE_HORIZONTAL BIT(12)
#define CX25840_VCONFIG_VALID_SHIFT 13
#define CX25840_VCONFIG_VALID_MASK GENMASK(14, 13)
#define CX25840_VCONFIG_VALID_NORMAL BIT(13)
#define CX25840_VCONFIG_VALID_ANDACTIVE BIT(14)
#define CX25840_VCONFIG_HRESETW_SHIFT 15
#define CX25840_VCONFIG_HRESETW_MASK GENMASK(16, 15)
#define CX25840_VCONFIG_HRESETW_NORMAL BIT(15)
#define CX25840_VCONFIG_HRESETW_PIXCLK BIT(16)
#define CX25840_VCONFIG_CLKGATE_SHIFT 17
#define CX25840_VCONFIG_CLKGATE_MASK GENMASK(18, 17)
#define CX25840_VCONFIG_CLKGATE_NONE BIT(17)
#define CX25840_VCONFIG_CLKGATE_VALID BIT(18)
#define CX25840_VCONFIG_CLKGATE_VALIDACTIVE GENMASK(18, 17)
#define CX25840_VCONFIG_DCMODE_SHIFT 19
#define CX25840_VCONFIG_DCMODE_MASK GENMASK(20, 19)
#define CX25840_VCONFIG_DCMODE_DWORDS BIT(19)
#define CX25840_VCONFIG_DCMODE_BYTES BIT(20)
#define CX25840_VCONFIG_IDID0S_SHIFT 21
#define CX25840_VCONFIG_IDID0S_MASK GENMASK(22, 21)
#define CX25840_VCONFIG_IDID0S_NORMAL BIT(21)
#define CX25840_VCONFIG_IDID0S_LINECNT BIT(22)
#define CX25840_VCONFIG_VIPCLAMP_SHIFT 23
#define CX25840_VCONFIG_VIPCLAMP_MASK GENMASK(24, 23)
#define CX25840_VCONFIG_VIPCLAMP_ENABLED BIT(23)
#define CX25840_VCONFIG_VIPCLAMP_DISABLED BIT(24)
enum cx25840_audio_input {
/* Audio inputs: serial or In4-In8 */
CX25840_AUDIO_SERIAL,
CX25840_AUDIO4 = 4,
CX25840_AUDIO5,
CX25840_AUDIO6,
CX25840_AUDIO7,
CX25840_AUDIO8,
};
enum cx25840_io_pin {
CX25840_PIN_DVALID_PRGM0 = 0,
CX25840_PIN_FIELD_PRGM1,
CX25840_PIN_HRESET_PRGM2,
CX25840_PIN_VRESET_HCTL_PRGM3,
CX25840_PIN_IRQ_N_PRGM4,
CX25840_PIN_IR_TX_PRGM6,
CX25840_PIN_IR_RX_PRGM5,
CX25840_PIN_GPIO0_PRGM8,
CX25840_PIN_GPIO1_PRGM9,
CX25840_PIN_SA_SDIN, /* Alternate GP Input only */
CX25840_PIN_SA_SDOUT, /* Alternate GP Input only */
CX25840_PIN_PLL_CLK_PRGM7,
CX25840_PIN_CHIP_SEL_VIPCLK, /* Output only */
};
enum cx25840_io_pad {
/* Output pads, these must match the actual chip register values */
CX25840_PAD_DEFAULT = 0,
CX25840_PAD_ACTIVE,
CX25840_PAD_VACTIVE,
CX25840_PAD_CBFLAG,
CX25840_PAD_VID_DATA_EXT0,
CX25840_PAD_VID_DATA_EXT1,
CX25840_PAD_GPO0,
CX25840_PAD_GPO1,
CX25840_PAD_GPO2,
CX25840_PAD_GPO3,
CX25840_PAD_IRQ_N,
CX25840_PAD_AC_SYNC,
CX25840_PAD_AC_SDOUT,
CX25840_PAD_PLL_CLK,
CX25840_PAD_VRESET,
CX25840_PAD_RESERVED,
/* Pads for PLL_CLK output only */
CX25840_PAD_XTI_X5_DLL,
CX25840_PAD_AUX_PLL,
CX25840_PAD_VID_PLL,
CX25840_PAD_XTI,
/* Input Pads */
CX25840_PAD_GPI0,
CX25840_PAD_GPI1,
CX25840_PAD_GPI2,
CX25840_PAD_GPI3,
};
enum cx25840_io_pin_strength {
CX25840_PIN_DRIVE_MEDIUM = 0,
CX25840_PIN_DRIVE_SLOW,
CX25840_PIN_DRIVE_FAST,
};
enum cx23885_io_pin {
CX23885_PIN_IR_RX_GPIO19,
CX23885_PIN_IR_TX_GPIO20,
CX23885_PIN_I2S_SDAT_GPIO21,
CX23885_PIN_I2S_WCLK_GPIO22,
CX23885_PIN_I2S_BCLK_GPIO23,
CX23885_PIN_IRQ_N_GPIO16,
};
enum cx23885_io_pad {
CX23885_PAD_IR_RX,
CX23885_PAD_GPIO19,
CX23885_PAD_IR_TX,
CX23885_PAD_GPIO20,
CX23885_PAD_I2S_SDAT,
CX23885_PAD_GPIO21,
CX23885_PAD_I2S_WCLK,
CX23885_PAD_GPIO22,
CX23885_PAD_I2S_BCLK,
CX23885_PAD_GPIO23,
CX23885_PAD_IRQ_N,
CX23885_PAD_GPIO16,
};
/*
* pvr150_workaround activates a workaround for a hardware bug that is
* present in Hauppauge PVR-150 (and possibly PVR-500) cards that have
* certain NTSC tuners (tveeprom tuner model numbers 85, 99 and 112). The
* audio autodetect fails on some channels for these models and the workaround
* is to select the audio standard explicitly. Many thanks to Hauppauge for
* providing this information.
*
* This platform data only needs to be supplied by the ivtv driver.
*/
struct cx25840_platform_data {
int pvr150_workaround;
};
#endif
|
// SPDX-License-Identifier: GPL-2.0
/* sercos3: UIO driver for the Automata Sercos III PCI card
Copyright (C) 2008 Linutronix GmbH
Author: John Ogness <[email protected]>
This is a straight-forward UIO driver, where interrupts are disabled
by the interrupt handler and re-enabled via a write to the UIO device
by the userspace-part.
The only part that may seem odd is the use of a logical OR when
storing and restoring enabled interrupts. This is done because the
userspace-part could directly modify the Interrupt Enable Register
at any time. To reduce possible conflicts, the kernel driver uses
a logical OR to make more controlled changes (rather than blindly
overwriting previous values).
Race conditions exist if the userspace-part directly modifies the
Interrupt Enable Register while in operation. The consequences are
that certain interrupts would fail to be enabled or disabled. For
this reason, the userspace-part should only directly modify the
Interrupt Enable Register at the beginning (to get things going).
The userspace-part can safely disable interrupts at any time using
a write to the UIO device.
*/
#include <linux/device.h>
#include <linux/module.h>
#include <linux/pci.h>
#include <linux/uio_driver.h>
#include <linux/io.h>
#include <linux/slab.h>
/* ID's for SERCOS III PCI card (PLX 9030) */
#define SERCOS_SUB_VENDOR_ID 0x1971
#define SERCOS_SUB_SYSID_3530 0x3530
#define SERCOS_SUB_SYSID_3535 0x3535
#define SERCOS_SUB_SYSID_3780 0x3780
/* Interrupt Enable Register */
#define IER0_OFFSET 0x08
/* Interrupt Status Register */
#define ISR0_OFFSET 0x18
struct sercos3_priv {
u32 ier0_cache;
spinlock_t ier0_cache_lock;
};
/* this function assumes ier0_cache_lock is locked! */
static void sercos3_disable_interrupts(struct uio_info *info,
struct sercos3_priv *priv)
{
void __iomem *ier0 = info->mem[3].internal_addr + IER0_OFFSET;
/* add enabled interrupts to cache */
priv->ier0_cache |= ioread32(ier0);
/* disable interrupts */
iowrite32(0, ier0);
}
/* this function assumes ier0_cache_lock is locked! */
static void sercos3_enable_interrupts(struct uio_info *info,
struct sercos3_priv *priv)
{
void __iomem *ier0 = info->mem[3].internal_addr + IER0_OFFSET;
/* restore previously enabled interrupts */
iowrite32(ioread32(ier0) | priv->ier0_cache, ier0);
priv->ier0_cache = 0;
}
static irqreturn_t sercos3_handler(int irq, struct uio_info *info)
{
struct sercos3_priv *priv = info->priv;
void __iomem *isr0 = info->mem[3].internal_addr + ISR0_OFFSET;
void __iomem *ier0 = info->mem[3].internal_addr + IER0_OFFSET;
if (!(ioread32(isr0) & ioread32(ier0)))
return IRQ_NONE;
spin_lock(&priv->ier0_cache_lock);
sercos3_disable_interrupts(info, priv);
spin_unlock(&priv->ier0_cache_lock);
return IRQ_HANDLED;
}
static int sercos3_irqcontrol(struct uio_info *info, s32 irq_on)
{
struct sercos3_priv *priv = info->priv;
spin_lock_irq(&priv->ier0_cache_lock);
if (irq_on)
sercos3_enable_interrupts(info, priv);
else
sercos3_disable_interrupts(info, priv);
spin_unlock_irq(&priv->ier0_cache_lock);
return 0;
}
static int sercos3_setup_iomem(struct pci_dev *dev, struct uio_info *info,
int n, int pci_bar)
{
info->mem[n].addr = pci_resource_start(dev, pci_bar);
if (!info->mem[n].addr)
return -1;
info->mem[n].internal_addr = ioremap(pci_resource_start(dev, pci_bar),
pci_resource_len(dev, pci_bar));
if (!info->mem[n].internal_addr)
return -1;
info->mem[n].size = pci_resource_len(dev, pci_bar);
info->mem[n].memtype = UIO_MEM_PHYS;
return 0;
}
static int sercos3_pci_probe(struct pci_dev *dev,
const struct pci_device_id *id)
{
struct uio_info *info;
struct sercos3_priv *priv;
int i;
info = devm_kzalloc(&dev->dev, sizeof(struct uio_info), GFP_KERNEL);
if (!info)
return -ENOMEM;
priv = devm_kzalloc(&dev->dev, sizeof(struct sercos3_priv), GFP_KERNEL);
if (!priv)
return -ENOMEM;
if (pci_enable_device(dev))
return -ENODEV;
if (pci_request_regions(dev, "sercos3"))
goto out_disable;
/* we only need PCI BAR's 0, 2, 3, 4, 5 */
if (sercos3_setup_iomem(dev, info, 0, 0))
goto out_unmap;
if (sercos3_setup_iomem(dev, info, 1, 2))
goto out_unmap;
if (sercos3_setup_iomem(dev, info, 2, 3))
goto out_unmap;
if (sercos3_setup_iomem(dev, info, 3, 4))
goto out_unmap;
if (sercos3_setup_iomem(dev, info, 4, 5))
goto out_unmap;
spin_lock_init(&priv->ier0_cache_lock);
info->priv = priv;
info->name = "Sercos_III_PCI";
info->version = "0.0.1";
info->irq = dev->irq;
info->irq_flags = IRQF_SHARED;
info->handler = sercos3_handler;
info->irqcontrol = sercos3_irqcontrol;
pci_set_drvdata(dev, info);
if (uio_register_device(&dev->dev, info))
goto out_unmap;
return 0;
out_unmap:
for (i = 0; i < 5; i++) {
if (info->mem[i].internal_addr)
iounmap(info->mem[i].internal_addr);
}
pci_release_regions(dev);
out_disable:
pci_disable_device(dev);
return -ENODEV;
}
static void sercos3_pci_remove(struct pci_dev *dev)
{
struct uio_info *info = pci_get_drvdata(dev);
int i;
uio_unregister_device(info);
pci_release_regions(dev);
pci_disable_device(dev);
for (i = 0; i < 5; i++) {
if (info->mem[i].internal_addr)
iounmap(info->mem[i].internal_addr);
}
}
static struct pci_device_id sercos3_pci_ids[] = {
{
.vendor = PCI_VENDOR_ID_PLX,
.device = PCI_DEVICE_ID_PLX_9030,
.subvendor = SERCOS_SUB_VENDOR_ID,
.subdevice = SERCOS_SUB_SYSID_3530,
},
{
.vendor = PCI_VENDOR_ID_PLX,
.device = PCI_DEVICE_ID_PLX_9030,
.subvendor = SERCOS_SUB_VENDOR_ID,
.subdevice = SERCOS_SUB_SYSID_3535,
},
{
.vendor = PCI_VENDOR_ID_PLX,
.device = PCI_DEVICE_ID_PLX_9030,
.subvendor = SERCOS_SUB_VENDOR_ID,
.subdevice = SERCOS_SUB_SYSID_3780,
},
{ 0, }
};
static struct pci_driver sercos3_pci_driver = {
.name = "sercos3",
.id_table = sercos3_pci_ids,
.probe = sercos3_pci_probe,
.remove = sercos3_pci_remove,
};
module_pci_driver(sercos3_pci_driver);
MODULE_DESCRIPTION("UIO driver for the Automata Sercos III PCI card");
MODULE_AUTHOR("John Ogness <[email protected]>");
MODULE_LICENSE("GPL v2");
|
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.
*/
#ifndef __DRIVERS_INTERCONNECT_QCOM_SDX65_H
#define __DRIVERS_INTERCONNECT_QCOM_SDX65_H
#define SDX65_MASTER_TCU_0 0
#define SDX65_MASTER_LLCC 1
#define SDX65_MASTER_AUDIO 2
#define SDX65_MASTER_BLSP_1 3
#define SDX65_MASTER_QDSS_BAM 4
#define SDX65_MASTER_QPIC 5
#define SDX65_MASTER_SNOC_CFG 6
#define SDX65_MASTER_SPMI_FETCHER 7
#define SDX65_MASTER_ANOC_SNOC 8
#define SDX65_MASTER_IPA 9
#define SDX65_MASTER_MEM_NOC_SNOC 10
#define SDX65_MASTER_MEM_NOC_PCIE_SNOC 11
#define SDX65_MASTER_SNOC_GC_MEM_NOC 12
#define SDX65_MASTER_CRYPTO 13
#define SDX65_MASTER_APPSS_PROC 14
#define SDX65_MASTER_IPA_PCIE 15
#define SDX65_MASTER_PCIE_0 16
#define SDX65_MASTER_QDSS_ETR 17
#define SDX65_MASTER_SDCC_1 18
#define SDX65_MASTER_USB3 19
#define SDX65_SLAVE_EBI1 512
#define SDX65_SLAVE_AOSS 513
#define SDX65_SLAVE_APPSS 514
#define SDX65_SLAVE_AUDIO 515
#define SDX65_SLAVE_BLSP_1 516
#define SDX65_SLAVE_CLK_CTL 517
#define SDX65_SLAVE_CRYPTO_0_CFG 518
#define SDX65_SLAVE_CNOC_DDRSS 519
#define SDX65_SLAVE_ECC_CFG 520
#define SDX65_SLAVE_IMEM_CFG 521
#define SDX65_SLAVE_IPA_CFG 522
#define SDX65_SLAVE_CNOC_MSS 523
#define SDX65_SLAVE_PCIE_PARF 524
#define SDX65_SLAVE_PDM 525
#define SDX65_SLAVE_PRNG 526
#define SDX65_SLAVE_QDSS_CFG 527
#define SDX65_SLAVE_QPIC 528
#define SDX65_SLAVE_SDCC_1 529
#define SDX65_SLAVE_SNOC_CFG 530
#define SDX65_SLAVE_SPMI_FETCHER 531
#define SDX65_SLAVE_SPMI_VGI_COEX 532
#define SDX65_SLAVE_TCSR 533
#define SDX65_SLAVE_TLMM 534
#define SDX65_SLAVE_USB3 535
#define SDX65_SLAVE_USB3_PHY_CFG 536
#define SDX65_SLAVE_ANOC_SNOC 537
#define SDX65_SLAVE_LLCC 538
#define SDX65_SLAVE_MEM_NOC_SNOC 539
#define SDX65_SLAVE_SNOC_MEM_NOC_GC 540
#define SDX65_SLAVE_MEM_NOC_PCIE_SNOC 541
#define SDX65_SLAVE_IMEM 542
#define SDX65_SLAVE_SERVICE_SNOC 543
#define SDX65_SLAVE_PCIE_0 544
#define SDX65_SLAVE_QDSS_STM 545
#define SDX65_SLAVE_TCU 546
#endif
|
/*
* T4240 Silicon/SoC Device Tree Source (pre include)
*
* Copyright 2012 - 2015 Freescale Semiconductor Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Freescale Semiconductor nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
*
* ALTERNATIVELY, this software may be distributed under the terms of the
* GNU General Public License ("GPL") as published by the Free Software
* Foundation, either version 2 of that License or (at your option) any
* later version.
*
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/dts-v1/;
/include/ "e6500_power_isa.dtsi"
/ {
compatible = "fsl,T4240";
#address-cells = <2>;
#size-cells = <2>;
interrupt-parent = <&mpic>;
aliases {
ccsr = &soc;
dcsr = &dcsr;
serial0 = &serial0;
serial1 = &serial1;
serial2 = &serial2;
serial3 = &serial3;
crypto = &crypto;
pci0 = &pci0;
pci1 = &pci1;
pci2 = &pci2;
pci3 = &pci3;
usb0 = &usb0;
usb1 = &usb1;
dma0 = &dma0;
dma1 = &dma1;
dma2 = &dma2;
sdhc = &sdhc;
fman0 = &fman0;
fman1 = &fman1;
ethernet0 = &enet0;
ethernet1 = &enet1;
ethernet2 = &enet2;
ethernet3 = &enet3;
ethernet4 = &enet4;
ethernet5 = &enet5;
ethernet6 = &enet6;
ethernet7 = &enet7;
ethernet8 = &enet8;
ethernet9 = &enet9;
ethernet10 = &enet10;
ethernet11 = &enet11;
ethernet12 = &enet12;
ethernet13 = &enet13;
ethernet14 = &enet14;
ethernet15 = &enet15;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu0: PowerPC,e6500@0 {
device_type = "cpu";
reg = <0 1>;
clocks = <&clockgen 1 0>;
next-level-cache = <&L2_1>;
fsl,portid-mapping = <0x80000000>;
};
cpu1: PowerPC,e6500@2 {
device_type = "cpu";
reg = <2 3>;
clocks = <&clockgen 1 0>;
next-level-cache = <&L2_1>;
fsl,portid-mapping = <0x80000000>;
};
cpu2: PowerPC,e6500@4 {
device_type = "cpu";
reg = <4 5>;
clocks = <&clockgen 1 0>;
next-level-cache = <&L2_1>;
fsl,portid-mapping = <0x80000000>;
};
cpu3: PowerPC,e6500@6 {
device_type = "cpu";
reg = <6 7>;
clocks = <&clockgen 1 0>;
next-level-cache = <&L2_1>;
fsl,portid-mapping = <0x80000000>;
};
cpu4: PowerPC,e6500@8 {
device_type = "cpu";
reg = <8 9>;
clocks = <&clockgen 1 1>;
next-level-cache = <&L2_2>;
fsl,portid-mapping = <0x40000000>;
};
cpu5: PowerPC,e6500@10 {
device_type = "cpu";
reg = <10 11>;
clocks = <&clockgen 1 1>;
next-level-cache = <&L2_2>;
fsl,portid-mapping = <0x40000000>;
};
cpu6: PowerPC,e6500@12 {
device_type = "cpu";
reg = <12 13>;
clocks = <&clockgen 1 1>;
next-level-cache = <&L2_2>;
fsl,portid-mapping = <0x40000000>;
};
cpu7: PowerPC,e6500@14 {
device_type = "cpu";
reg = <14 15>;
clocks = <&clockgen 1 1>;
next-level-cache = <&L2_2>;
fsl,portid-mapping = <0x40000000>;
};
cpu8: PowerPC,e6500@16 {
device_type = "cpu";
reg = <16 17>;
clocks = <&clockgen 1 2>;
next-level-cache = <&L2_3>;
fsl,portid-mapping = <0x20000000>;
};
cpu9: PowerPC,e6500@18 {
device_type = "cpu";
reg = <18 19>;
clocks = <&clockgen 1 2>;
next-level-cache = <&L2_3>;
fsl,portid-mapping = <0x20000000>;
};
cpu10: PowerPC,e6500@20 {
device_type = "cpu";
reg = <20 21>;
clocks = <&clockgen 1 2>;
next-level-cache = <&L2_3>;
fsl,portid-mapping = <0x20000000>;
};
cpu11: PowerPC,e6500@22 {
device_type = "cpu";
reg = <22 23>;
clocks = <&clockgen 1 2>;
next-level-cache = <&L2_3>;
fsl,portid-mapping = <0x20000000>;
};
};
};
|
/* SPDX-License-Identifier: GPL-2.0 */
#ifndef LCDC_H
#define LCDC_H
/*
* Copyright (C) 2004 Nokia Corporation
* Author: Imre Deak <[email protected]>
*/
#define OMAP_LCDC_BASE 0xfffec000
#define OMAP_LCDC_SIZE 256
#define OMAP_LCDC_IRQ INT_LCD_CTRL
#define OMAP_LCDC_CONTROL (OMAP_LCDC_BASE + 0x00)
#define OMAP_LCDC_TIMING0 (OMAP_LCDC_BASE + 0x04)
#define OMAP_LCDC_TIMING1 (OMAP_LCDC_BASE + 0x08)
#define OMAP_LCDC_TIMING2 (OMAP_LCDC_BASE + 0x0c)
#define OMAP_LCDC_STATUS (OMAP_LCDC_BASE + 0x10)
#define OMAP_LCDC_SUBPANEL (OMAP_LCDC_BASE + 0x14)
#define OMAP_LCDC_LINE_INT (OMAP_LCDC_BASE + 0x18)
#define OMAP_LCDC_DISPLAY_STATUS (OMAP_LCDC_BASE + 0x1c)
#define OMAP_LCDC_STAT_DONE (1 << 0)
#define OMAP_LCDC_STAT_VSYNC (1 << 1)
#define OMAP_LCDC_STAT_SYNC_LOST (1 << 2)
#define OMAP_LCDC_STAT_ABC (1 << 3)
#define OMAP_LCDC_STAT_LINE_INT (1 << 4)
#define OMAP_LCDC_STAT_FUF (1 << 5)
#define OMAP_LCDC_STAT_LOADED_PALETTE (1 << 6)
#define OMAP_LCDC_CTRL_LCD_EN (1 << 0)
#define OMAP_LCDC_CTRL_LCD_TFT (1 << 7)
#define OMAP_LCDC_CTRL_LINE_IRQ_CLR_SEL (1 << 10)
#define OMAP_LCDC_IRQ_VSYNC (1 << 2)
#define OMAP_LCDC_IRQ_DONE (1 << 3)
#define OMAP_LCDC_IRQ_LOADED_PALETTE (1 << 4)
#define OMAP_LCDC_IRQ_LINE_NIRQ (1 << 5)
#define OMAP_LCDC_IRQ_LINE (1 << 6)
#define OMAP_LCDC_IRQ_MASK (((1 << 5) - 1) << 2)
int omap_lcdc_set_dma_callback(void (*callback)(void *data), void *data);
void omap_lcdc_free_dma_callback(void);
extern const struct lcd_ctrl omap1_int_ctrl;
#endif
|
/*
* Copyright (c) 2005-2008 Chelsio, Inc. All rights reserved.
*
* This software is available to you under a choice of one of two
* licenses. You may choose to be licensed under the terms of the GNU
* General Public License (GPL) Version 2, available from the file
* COPYING in the main directory of this source tree, or the
* OpenIB.org BSD license below:
*
* Redistribution and use in source and binary forms, with or
* without modification, are permitted provided that the following
* conditions are met:
*
* - Redistributions of source code must retain the above
* copyright notice, this list of conditions and the following
* disclaimer.
*
* - Redistributions in binary form must reproduce the above
* copyright notice, this list of conditions and the following
* disclaimer in the documentation and/or other materials
* provided with the distribution.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*/
#include "common.h"
#include "regs.h"
enum {
AEL100X_TX_CONFIG1 = 0xc002,
AEL1002_PWR_DOWN_HI = 0xc011,
AEL1002_PWR_DOWN_LO = 0xc012,
AEL1002_XFI_EQL = 0xc015,
AEL1002_LB_EN = 0xc017,
AEL_OPT_SETTINGS = 0xc017,
AEL_I2C_CTRL = 0xc30a,
AEL_I2C_DATA = 0xc30b,
AEL_I2C_STAT = 0xc30c,
AEL2005_GPIO_CTRL = 0xc214,
AEL2005_GPIO_STAT = 0xc215,
AEL2020_GPIO_INTR = 0xc103, /* Latch High (LH) */
AEL2020_GPIO_CTRL = 0xc108, /* Store Clear (SC) */
AEL2020_GPIO_STAT = 0xc10c, /* Read Only (RO) */
AEL2020_GPIO_CFG = 0xc110, /* Read Write (RW) */
AEL2020_GPIO_SDA = 0, /* IN: i2c serial data */
AEL2020_GPIO_MODDET = 1, /* IN: Module Detect */
AEL2020_GPIO_0 = 3, /* IN: unassigned */
AEL2020_GPIO_1 = 2, /* OUT: unassigned */
AEL2020_GPIO_LSTAT = AEL2020_GPIO_1, /* wired to link status LED */
};
enum { edc_none, edc_sr, edc_twinax };
/* PHY module I2C device address */
enum {
MODULE_DEV_ADDR = 0xa0,
SFF_DEV_ADDR = 0xa2,
};
/* PHY transceiver type */
enum {
phy_transtype_unknown = 0,
phy_transtype_sfp = 3,
phy_transtype_xfp = 6,
};
#define AEL2005_MODDET_IRQ 4
struct reg_val {
unsigned short mmd_addr;
unsigned short reg_addr;
unsigned short clear_bits;
unsigned short set_bits;
};
static int set_phy_regs(struct cphy *phy, const struct reg_val *rv)
{
int err;
for (err = 0; rv->mmd_addr && !err; rv++) {
if (rv->clear_bits == 0xffff)
err = t3_mdio_write(phy, rv->mmd_addr, rv->reg_addr,
rv->set_bits);
else
err = t3_mdio_change_bits(phy, rv->mmd_addr,
rv->reg_addr, rv->clear_bits,
rv->set_bits);
}
return err;
}
static void ael100x_txon(struct cphy *phy)
{
int tx_on_gpio =
phy->mdio.prtad == 0 ? F_GPIO7_OUT_VAL : F_GPIO2_OUT_VAL;
msleep(100);
t3_set_reg_field(phy->adapter, A_T3DBG_GPIO_EN, 0, tx_on_gpio);
msleep(30);
}
/*
* Read an 8-bit word from a device attached to the PHY's i2c bus.
*/
static int ael_i2c_rd(struct cphy *phy, int dev_addr, int word_addr)
{
int i, err;
unsigned int stat, data;
err = t3_mdio_write(phy, MDIO_MMD_PMAPMD, AEL_I2C_CTRL,
(dev_addr << 8) | (1 << 8) | word_addr);
if (err)
return err;
for (i = 0; i < 200; i++) {
msleep(1);
err = t3_mdio_read(phy, MDIO_MMD_PMAPMD, AEL_I2C_STAT, &stat);
if (err)
return err;
if ((stat & 3) == 1) {
err = t3_mdio_read(phy, MDIO_MMD_PMAPMD, AEL_I2C_DATA,
&data);
if (err)
return err;
return data >> 8;
}
}
CH_WARN(phy->adapter, "PHY %u i2c read of dev.addr %#x.%#x timed out\n",
phy->mdio.prtad, dev_addr, word_addr);
return -ETIMEDOUT;
}
static int ael1002_power_down(struct cphy *phy, int enable)
{
int err;
err = t3_mdio_write(phy, MDIO_MMD_PMAPMD, MDIO_PMA_TXDIS, !!enable);
if (!err)
err = mdio_set_flag(&phy->mdio, phy->mdio.prtad,
MDIO_MMD_PMAPMD, MDIO_CTRL1,
MDIO_CTRL1_LPOWER, enable);
return err;
}
static int ael1002_reset(struct cphy *phy, int wait)
{
int err;
if ((err = ael1002_power_down(phy, 0)) ||
(err = t3_mdio_write(phy, MDIO_MMD_PMAPMD, AEL100X_TX_CONFIG1, 1)) ||
(err = t3_mdio_write(phy, MDIO_MMD_PMAPMD, AEL1002_PWR_DOWN_HI, 0)) ||
(err = t3_mdio_write(phy, MDIO_MMD_PMAPMD, AEL1002_PWR_DOWN_LO, 0)) ||
(err = t3_mdio_write(phy, MDIO_MMD_PMAPMD, AEL1002_XFI_EQL, 0x18)) ||
(err = t3_mdio_change_bits(phy, MDIO_MMD_PMAPMD, AEL1002_LB_EN,
0, 1 << 5)))
return err;
return 0;
}
static int ael1002_intr_noop(struct cphy *phy)
{
return 0;
}
/*
* Get link status for a 10GBASE-R device.
*/
static int get_link_status_r(struct cphy *phy, int *link_ok, int *speed,
int *duplex, int *fc)
{
if (link_ok) {
unsigned int stat0, stat1, stat2;
int err = t3_mdio_read(phy, MDIO_MMD_PMAPMD,
MDIO_PMA_RXDET, &stat0);
if (!err)
err = t3_mdio_read(phy, MDIO_MMD_PCS,
MDIO_PCS_10GBRT_STAT1, &stat1);
if (!err)
err = t3_mdio_read(phy, MDIO_MMD_PHYXS,
MDIO_PHYXS_LNSTAT, &stat2);
if (err)
return err;
*link_ok = (stat0 & stat1 & (stat2 >> 12)) & 1;
}
if (speed)
*speed = SPEED_10000;
if (duplex)
*duplex = DUPLEX_FULL;
return 0;
}
static const struct cphy_ops ael1002_ops = {
.reset = ael1002_reset,
.intr_enable = ael1002_intr_noop,
.intr_disable = ael1002_intr_noop,
.intr_clear = ael1002_intr_noop,
.intr_handler = ael1002_intr_noop,
.get_link_status = get_link_status_r,
.power_down = ael1002_power_down,
.mmds = MDIO_DEVS_PMAPMD | MDIO_DEVS_PCS | MDIO_DEVS_PHYXS,
};
int t3_ael1002_phy_prep(struct cphy *phy, struct adapter *adapter,
int phy_addr, const struct mdio_ops *mdio_ops)
{
cphy_init(phy, adapter, phy_addr, &ael1002_ops, mdio_ops,
SUPPORTED_10000baseT_Full | SUPPORTED_AUI | SUPPORTED_FIBRE,
"10GBASE-R");
ael100x_txon(phy);
return 0;
}
static int ael1006_reset(struct cphy *phy, int wait)
{
return t3_phy_reset(phy, MDIO_MMD_PMAPMD, wait);
}
static const struct cphy_ops ael1006_ops = {
.reset = ael1006_reset,
.intr_enable = t3_phy_lasi_intr_enable,
.intr_disable = t3_phy_lasi_intr_disable,
.intr_clear = t3_phy_lasi_intr_clear,
.intr_handler = t3_phy_lasi_intr_handler,
.get_link_status = get_link_status_r,
.power_down = ael1002_power_down,
.mmds = MDIO_DEVS_PMAPMD | MDIO_DEVS_PCS | MDIO_DEVS_PHYXS,
};
int t3_ael1006_phy_prep(struct cphy *phy, struct adapter *adapter,
int phy_addr, const struct mdio_ops *mdio_ops)
{
cphy_init(phy, adapter, phy_addr, &ael1006_ops, mdio_ops,
SUPPORTED_10000baseT_Full | SUPPORTED_AUI | SUPPORTED_FIBRE,
"10GBASE-SR");
ael100x_txon(phy);
return 0;
}
/*
* Decode our module type.
*/
static int ael2xxx_get_module_type(struct cphy *phy, int delay_ms)
{
int v;
if (delay_ms)
msleep(delay_ms);
/* see SFF-8472 for below */
v = ael_i2c_rd(phy, MODULE_DEV_ADDR, 3);
if (v < 0)
return v;
if (v == 0x10)
return phy_modtype_sr;
if (v == 0x20)
return phy_modtype_lr;
if (v == 0x40)
return phy_modtype_lrm;
v = ael_i2c_rd(phy, MODULE_DEV_ADDR, 6);
if (v < 0)
return v;
if (v != 4)
goto unknown;
v = ael_i2c_rd(phy, MODULE_DEV_ADDR, 10);
if (v < 0)
return v;
if (v & 0x80) {
v = ael_i2c_rd(phy, MODULE_DEV_ADDR, 0x12);
if (v < 0)
return v;
return v > 10 ? phy_modtype_twinax_long : phy_modtype_twinax;
}
unknown:
return phy_modtype_unknown;
}
/*
* Code to support the Aeluros/NetLogic 2005 10Gb PHY.
*/
static int ael2005_setup_sr_edc(struct cphy *phy)
{
static const struct reg_val regs[] = {
{ MDIO_MMD_PMAPMD, 0xc003, 0xffff, 0x181 },
{ MDIO_MMD_PMAPMD, 0xc010, 0xffff, 0x448a },
{ MDIO_MMD_PMAPMD, 0xc04a, 0xffff, 0x5200 },
{ 0, 0, 0, 0 }
};
int i, err;
err = set_phy_regs(phy, regs);
if (err)
return err;
msleep(50);
if (phy->priv != edc_sr)
err = t3_get_edc_fw(phy, EDC_OPT_AEL2005,
EDC_OPT_AEL2005_SIZE);
if (err)
return err;
for (i = 0; i < EDC_OPT_AEL2005_SIZE / sizeof(u16) && !err; i += 2)
err = t3_mdio_write(phy, MDIO_MMD_PMAPMD,
phy->phy_cache[i],
phy->phy_cache[i + 1]);
if (!err)
phy->priv = edc_sr;
return err;
}
static int ael2005_setup_twinax_edc(struct cphy *phy, int modtype)
{
static const struct reg_val regs[] = {
{ MDIO_MMD_PMAPMD, 0xc04a, 0xffff, 0x5a00 },
{ 0, 0, 0, 0 }
};
static const struct reg_val preemphasis[] = {
{ MDIO_MMD_PMAPMD, 0xc014, 0xffff, 0xfe16 },
{ MDIO_MMD_PMAPMD, 0xc015, 0xffff, 0xa000 },
{ 0, 0, 0, 0 }
};
int i, err;
err = set_phy_regs(phy, regs);
if (!err && modtype == phy_modtype_twinax_long)
err = set_phy_regs(phy, preemphasis);
if (err)
return err;
msleep(50);
if (phy->priv != edc_twinax)
err = t3_get_edc_fw(phy, EDC_TWX_AEL2005,
EDC_TWX_AEL2005_SIZE);
if (err)
return err;
for (i = 0; i < EDC_TWX_AEL2005_SIZE / sizeof(u16) && !err; i += 2)
err = t3_mdio_write(phy, MDIO_MMD_PMAPMD,
phy->phy_cache[i],
phy->phy_cache[i + 1]);
if (!err)
phy->priv = edc_twinax;
return err;
}
static int ael2005_get_module_type(struct cphy *phy, int delay_ms)
{
int v;
unsigned int stat;
v = t3_mdio_read(phy, MDIO_MMD_PMAPMD, AEL2005_GPIO_CTRL, &stat);
if (v)
return v;
if (stat & (1 << 8)) /* module absent */
return phy_modtype_none;
return ael2xxx_get_module_type(phy, delay_ms);
}
static int ael2005_intr_enable(struct cphy *phy)
{
int err = t3_mdio_write(phy, MDIO_MMD_PMAPMD, AEL2005_GPIO_CTRL, 0x200);
return err ? err : t3_phy_lasi_intr_enable(phy);
}
static int ael2005_intr_disable(struct cphy *phy)
{
int err = t3_mdio_write(phy, MDIO_MMD_PMAPMD, AEL2005_GPIO_CTRL, 0x100);
return err ? err : t3_phy_lasi_intr_disable(phy);
}
static int ael2005_intr_clear(struct cphy *phy)
{
int err = t3_mdio_write(phy, MDIO_MMD_PMAPMD, AEL2005_GPIO_CTRL, 0xd00);
return err ? err : t3_phy_lasi_intr_clear(phy);
}
static int ael2005_reset(struct cphy *phy, int wait)
{
static const struct reg_val regs0[] = {
{ MDIO_MMD_PMAPMD, 0xc001, 0, 1 << 5 },
{ MDIO_MMD_PMAPMD, 0xc017, 0, 1 << 5 },
{ MDIO_MMD_PMAPMD, 0xc013, 0xffff, 0xf341 },
{ MDIO_MMD_PMAPMD, 0xc210, 0xffff, 0x8000 },
{ MDIO_MMD_PMAPMD, 0xc210, 0xffff, 0x8100 },
{ MDIO_MMD_PMAPMD, 0xc210, 0xffff, 0x8000 },
{ MDIO_MMD_PMAPMD, 0xc210, 0xffff, 0 },
{ 0, 0, 0, 0 }
};
static const struct reg_val regs1[] = {
{ MDIO_MMD_PMAPMD, 0xca00, 0xffff, 0x0080 },
{ MDIO_MMD_PMAPMD, 0xca12, 0xffff, 0 },
{ 0, 0, 0, 0 }
};
int err;
unsigned int lasi_ctrl;
err = t3_mdio_read(phy, MDIO_MMD_PMAPMD, MDIO_PMA_LASI_CTRL,
&lasi_ctrl);
if (err)
return err;
err = t3_phy_reset(phy, MDIO_MMD_PMAPMD, 0);
if (err)
return err;
msleep(125);
phy->priv = edc_none;
err = set_phy_regs(phy, regs0);
if (err)
return err;
msleep(50);
err = ael2005_get_module_type(phy, 0);
if (err < 0)
return err;
phy->modtype = err;
if (err == phy_modtype_twinax || err == phy_modtype_twinax_long)
err = ael2005_setup_twinax_edc(phy, err);
else
err = ael2005_setup_sr_edc(phy);
if (err)
return err;
err = set_phy_regs(phy, regs1);
if (err)
return err;
/* reset wipes out interrupts, reenable them if they were on */
if (lasi_ctrl & 1)
err = ael2005_intr_enable(phy);
return err;
}
static int ael2005_intr_handler(struct cphy *phy)
{
unsigned int stat;
int ret, edc_needed, cause = 0;
ret = t3_mdio_read(phy, MDIO_MMD_PMAPMD, AEL2005_GPIO_STAT, &stat);
if (ret)
return ret;
if (stat & AEL2005_MODDET_IRQ) {
ret = t3_mdio_write(phy, MDIO_MMD_PMAPMD, AEL2005_GPIO_CTRL,
0xd00);
if (ret)
return ret;
/* modules have max 300 ms init time after hot plug */
ret = ael2005_get_module_type(phy, 300);
if (ret < 0)
return ret;
phy->modtype = ret;
if (ret == phy_modtype_none)
edc_needed = phy->priv; /* on unplug retain EDC */
else if (ret == phy_modtype_twinax ||
ret == phy_modtype_twinax_long)
edc_needed = edc_twinax;
else
edc_needed = edc_sr;
if (edc_needed != phy->priv) {
ret = ael2005_reset(phy, 0);
return ret ? ret : cphy_cause_module_change;
}
cause = cphy_cause_module_change;
}
ret = t3_phy_lasi_intr_handler(phy);
if (ret < 0)
return ret;
ret |= cause;
return ret ? ret : cphy_cause_link_change;
}
static const struct cphy_ops ael2005_ops = {
.reset = ael2005_reset,
.intr_enable = ael2005_intr_enable,
.intr_disable = ael2005_intr_disable,
.intr_clear = ael2005_intr_clear,
.intr_handler = ael2005_intr_handler,
.get_link_status = get_link_status_r,
.power_down = ael1002_power_down,
.mmds = MDIO_DEVS_PMAPMD | MDIO_DEVS_PCS | MDIO_DEVS_PHYXS,
};
int t3_ael2005_phy_prep(struct cphy *phy, struct adapter *adapter,
int phy_addr, const struct mdio_ops *mdio_ops)
{
cphy_init(phy, adapter, phy_addr, &ael2005_ops, mdio_ops,
SUPPORTED_10000baseT_Full | SUPPORTED_AUI | SUPPORTED_FIBRE |
SUPPORTED_IRQ, "10GBASE-R");
msleep(125);
return t3_mdio_change_bits(phy, MDIO_MMD_PMAPMD, AEL_OPT_SETTINGS, 0,
1 << 5);
}
/*
* Setup EDC and other parameters for operation with an optical module.
*/
static int ael2020_setup_sr_edc(struct cphy *phy)
{
static const struct reg_val regs[] = {
/* set CDR offset to 10 */
{ MDIO_MMD_PMAPMD, 0xcc01, 0xffff, 0x488a },
/* adjust 10G RX bias current */
{ MDIO_MMD_PMAPMD, 0xcb1b, 0xffff, 0x0200 },
{ MDIO_MMD_PMAPMD, 0xcb1c, 0xffff, 0x00f0 },
{ MDIO_MMD_PMAPMD, 0xcc06, 0xffff, 0x00e0 },
/* end */
{ 0, 0, 0, 0 }
};
int err;
err = set_phy_regs(phy, regs);
msleep(50);
if (err)
return err;
phy->priv = edc_sr;
return 0;
}
/*
* Setup EDC and other parameters for operation with an TWINAX module.
*/
static int ael2020_setup_twinax_edc(struct cphy *phy, int modtype)
{
/* set uC to 40MHz */
static const struct reg_val uCclock40MHz[] = {
{ MDIO_MMD_PMAPMD, 0xff28, 0xffff, 0x4001 },
{ MDIO_MMD_PMAPMD, 0xff2a, 0xffff, 0x0002 },
{ 0, 0, 0, 0 }
};
/* activate uC clock */
static const struct reg_val uCclockActivate[] = {
{ MDIO_MMD_PMAPMD, 0xd000, 0xffff, 0x5200 },
{ 0, 0, 0, 0 }
};
/* set PC to start of SRAM and activate uC */
static const struct reg_val uCactivate[] = {
{ MDIO_MMD_PMAPMD, 0xd080, 0xffff, 0x0100 },
{ MDIO_MMD_PMAPMD, 0xd092, 0xffff, 0x0000 },
{ 0, 0, 0, 0 }
};
int i, err;
/* set uC clock and activate it */
err = set_phy_regs(phy, uCclock40MHz);
msleep(500);
if (err)
return err;
err = set_phy_regs(phy, uCclockActivate);
msleep(500);
if (err)
return err;
if (phy->priv != edc_twinax)
err = t3_get_edc_fw(phy, EDC_TWX_AEL2020,
EDC_TWX_AEL2020_SIZE);
if (err)
return err;
for (i = 0; i < EDC_TWX_AEL2020_SIZE / sizeof(u16) && !err; i += 2)
err = t3_mdio_write(phy, MDIO_MMD_PMAPMD,
phy->phy_cache[i],
phy->phy_cache[i + 1]);
/* activate uC */
err = set_phy_regs(phy, uCactivate);
if (!err)
phy->priv = edc_twinax;
return err;
}
/*
* Return Module Type.
*/
static int ael2020_get_module_type(struct cphy *phy, int delay_ms)
{
int v;
unsigned int stat;
v = t3_mdio_read(phy, MDIO_MMD_PMAPMD, AEL2020_GPIO_STAT, &stat);
if (v)
return v;
if (stat & (0x1 << (AEL2020_GPIO_MODDET*4))) {
/* module absent */
return phy_modtype_none;
}
return ael2xxx_get_module_type(phy, delay_ms);
}
/*
* Enable PHY interrupts. We enable "Module Detection" interrupts (on any
* state transition) and then generic Link Alarm Status Interrupt (LASI).
*/
static int ael2020_intr_enable(struct cphy *phy)
{
static const struct reg_val regs[] = {
/* output Module's Loss Of Signal (LOS) to LED */
{ MDIO_MMD_PMAPMD, AEL2020_GPIO_CFG+AEL2020_GPIO_LSTAT,
0xffff, 0x4 },
{ MDIO_MMD_PMAPMD, AEL2020_GPIO_CTRL,
0xffff, 0x8 << (AEL2020_GPIO_LSTAT*4) },
/* enable module detect status change interrupts */
{ MDIO_MMD_PMAPMD, AEL2020_GPIO_CTRL,
0xffff, 0x2 << (AEL2020_GPIO_MODDET*4) },
/* end */
{ 0, 0, 0, 0 }
};
int err, link_ok = 0;
/* set up "link status" LED and enable module change interrupts */
err = set_phy_regs(phy, regs);
if (err)
return err;
err = get_link_status_r(phy, &link_ok, NULL, NULL, NULL);
if (err)
return err;
if (link_ok)
t3_link_changed(phy->adapter,
phy2portid(phy));
err = t3_phy_lasi_intr_enable(phy);
if (err)
return err;
return 0;
}
/*
* Disable PHY interrupts. The mirror of the above ...
*/
static int ael2020_intr_disable(struct cphy *phy)
{
static const struct reg_val regs[] = {
/* reset "link status" LED to "off" */
{ MDIO_MMD_PMAPMD, AEL2020_GPIO_CTRL,
0xffff, 0xb << (AEL2020_GPIO_LSTAT*4) },
/* disable module detect status change interrupts */
{ MDIO_MMD_PMAPMD, AEL2020_GPIO_CTRL,
0xffff, 0x1 << (AEL2020_GPIO_MODDET*4) },
/* end */
{ 0, 0, 0, 0 }
};
int err;
/* turn off "link status" LED and disable module change interrupts */
err = set_phy_regs(phy, regs);
if (err)
return err;
return t3_phy_lasi_intr_disable(phy);
}
/*
* Clear PHY interrupt state.
*/
static int ael2020_intr_clear(struct cphy *phy)
{
/*
* The GPIO Interrupt register on the AEL2020 is a "Latching High"
* (LH) register which is cleared to the current state when it's read.
* Thus, we simply read the register and discard the result.
*/
unsigned int stat;
int err = t3_mdio_read(phy, MDIO_MMD_PMAPMD, AEL2020_GPIO_INTR, &stat);
return err ? err : t3_phy_lasi_intr_clear(phy);
}
static const struct reg_val ael2020_reset_regs[] = {
/* Erratum #2: CDRLOL asserted, causing PMA link down status */
{ MDIO_MMD_PMAPMD, 0xc003, 0xffff, 0x3101 },
/* force XAUI to send LF when RX_LOS is asserted */
{ MDIO_MMD_PMAPMD, 0xcd40, 0xffff, 0x0001 },
/* allow writes to transceiver module EEPROM on i2c bus */
{ MDIO_MMD_PMAPMD, 0xff02, 0xffff, 0x0023 },
{ MDIO_MMD_PMAPMD, 0xff03, 0xffff, 0x0000 },
{ MDIO_MMD_PMAPMD, 0xff04, 0xffff, 0x0000 },
/* end */
{ 0, 0, 0, 0 }
};
/*
* Reset the PHY and put it into a canonical operating state.
*/
static int ael2020_reset(struct cphy *phy, int wait)
{
int err;
unsigned int lasi_ctrl;
/* grab current interrupt state */
err = t3_mdio_read(phy, MDIO_MMD_PMAPMD, MDIO_PMA_LASI_CTRL,
&lasi_ctrl);
if (err)
return err;
err = t3_phy_reset(phy, MDIO_MMD_PMAPMD, 125);
if (err)
return err;
msleep(100);
/* basic initialization for all module types */
phy->priv = edc_none;
err = set_phy_regs(phy, ael2020_reset_regs);
if (err)
return err;
/* determine module type and perform appropriate initialization */
err = ael2020_get_module_type(phy, 0);
if (err < 0)
return err;
phy->modtype = (u8)err;
if (err == phy_modtype_twinax || err == phy_modtype_twinax_long)
err = ael2020_setup_twinax_edc(phy, err);
else
err = ael2020_setup_sr_edc(phy);
if (err)
return err;
/* reset wipes out interrupts, reenable them if they were on */
if (lasi_ctrl & 1)
err = ael2005_intr_enable(phy);
return err;
}
/*
* Handle a PHY interrupt.
*/
static int ael2020_intr_handler(struct cphy *phy)
{
unsigned int stat;
int ret, edc_needed, cause = 0;
ret = t3_mdio_read(phy, MDIO_MMD_PMAPMD, AEL2020_GPIO_INTR, &stat);
if (ret)
return ret;
if (stat & (0x1 << AEL2020_GPIO_MODDET)) {
/* modules have max 300 ms init time after hot plug */
ret = ael2020_get_module_type(phy, 300);
if (ret < 0)
return ret;
phy->modtype = (u8)ret;
if (ret == phy_modtype_none)
edc_needed = phy->priv; /* on unplug retain EDC */
else if (ret == phy_modtype_twinax ||
ret == phy_modtype_twinax_long)
edc_needed = edc_twinax;
else
edc_needed = edc_sr;
if (edc_needed != phy->priv) {
ret = ael2020_reset(phy, 0);
return ret ? ret : cphy_cause_module_change;
}
cause = cphy_cause_module_change;
}
ret = t3_phy_lasi_intr_handler(phy);
if (ret < 0)
return ret;
ret |= cause;
return ret ? ret : cphy_cause_link_change;
}
static const struct cphy_ops ael2020_ops = {
.reset = ael2020_reset,
.intr_enable = ael2020_intr_enable,
.intr_disable = ael2020_intr_disable,
.intr_clear = ael2020_intr_clear,
.intr_handler = ael2020_intr_handler,
.get_link_status = get_link_status_r,
.power_down = ael1002_power_down,
.mmds = MDIO_DEVS_PMAPMD | MDIO_DEVS_PCS | MDIO_DEVS_PHYXS,
};
int t3_ael2020_phy_prep(struct cphy *phy, struct adapter *adapter, int phy_addr,
const struct mdio_ops *mdio_ops)
{
cphy_init(phy, adapter, phy_addr, &ael2020_ops, mdio_ops,
SUPPORTED_10000baseT_Full | SUPPORTED_AUI | SUPPORTED_FIBRE |
SUPPORTED_IRQ, "10GBASE-R");
msleep(125);
return set_phy_regs(phy, ael2020_reset_regs);
}
/*
* Get link status for a 10GBASE-X device.
*/
static int get_link_status_x(struct cphy *phy, int *link_ok, int *speed,
int *duplex, int *fc)
{
if (link_ok) {
unsigned int stat0, stat1, stat2;
int err = t3_mdio_read(phy, MDIO_MMD_PMAPMD,
MDIO_PMA_RXDET, &stat0);
if (!err)
err = t3_mdio_read(phy, MDIO_MMD_PCS,
MDIO_PCS_10GBX_STAT1, &stat1);
if (!err)
err = t3_mdio_read(phy, MDIO_MMD_PHYXS,
MDIO_PHYXS_LNSTAT, &stat2);
if (err)
return err;
*link_ok = (stat0 & (stat1 >> 12) & (stat2 >> 12)) & 1;
}
if (speed)
*speed = SPEED_10000;
if (duplex)
*duplex = DUPLEX_FULL;
return 0;
}
static const struct cphy_ops qt2045_ops = {
.reset = ael1006_reset,
.intr_enable = t3_phy_lasi_intr_enable,
.intr_disable = t3_phy_lasi_intr_disable,
.intr_clear = t3_phy_lasi_intr_clear,
.intr_handler = t3_phy_lasi_intr_handler,
.get_link_status = get_link_status_x,
.power_down = ael1002_power_down,
.mmds = MDIO_DEVS_PMAPMD | MDIO_DEVS_PCS | MDIO_DEVS_PHYXS,
};
int t3_qt2045_phy_prep(struct cphy *phy, struct adapter *adapter,
int phy_addr, const struct mdio_ops *mdio_ops)
{
unsigned int stat;
cphy_init(phy, adapter, phy_addr, &qt2045_ops, mdio_ops,
SUPPORTED_10000baseT_Full | SUPPORTED_AUI | SUPPORTED_TP,
"10GBASE-CX4");
/*
* Some cards where the PHY is supposed to be at address 0 actually
* have it at 1.
*/
if (!phy_addr &&
!t3_mdio_read(phy, MDIO_MMD_PMAPMD, MDIO_STAT1, &stat) &&
stat == 0xffff)
phy->mdio.prtad = 1;
return 0;
}
static int xaui_direct_reset(struct cphy *phy, int wait)
{
return 0;
}
static int xaui_direct_get_link_status(struct cphy *phy, int *link_ok,
int *speed, int *duplex, int *fc)
{
if (link_ok) {
unsigned int status;
int prtad = phy->mdio.prtad;
status = t3_read_reg(phy->adapter,
XGM_REG(A_XGM_SERDES_STAT0, prtad)) |
t3_read_reg(phy->adapter,
XGM_REG(A_XGM_SERDES_STAT1, prtad)) |
t3_read_reg(phy->adapter,
XGM_REG(A_XGM_SERDES_STAT2, prtad)) |
t3_read_reg(phy->adapter,
XGM_REG(A_XGM_SERDES_STAT3, prtad));
*link_ok = !(status & F_LOWSIG0);
}
if (speed)
*speed = SPEED_10000;
if (duplex)
*duplex = DUPLEX_FULL;
return 0;
}
static int xaui_direct_power_down(struct cphy *phy, int enable)
{
return 0;
}
static const struct cphy_ops xaui_direct_ops = {
.reset = xaui_direct_reset,
.intr_enable = ael1002_intr_noop,
.intr_disable = ael1002_intr_noop,
.intr_clear = ael1002_intr_noop,
.intr_handler = ael1002_intr_noop,
.get_link_status = xaui_direct_get_link_status,
.power_down = xaui_direct_power_down,
};
int t3_xaui_direct_phy_prep(struct cphy *phy, struct adapter *adapter,
int phy_addr, const struct mdio_ops *mdio_ops)
{
cphy_init(phy, adapter, phy_addr, &xaui_direct_ops, mdio_ops,
SUPPORTED_10000baseT_Full | SUPPORTED_AUI | SUPPORTED_TP,
"10GBASE-CX4");
return 0;
}
|
/* SPDX-License-Identifier: GPL-2.0 */
#ifndef LINUX_SSB_EMBEDDED_H_
#define LINUX_SSB_EMBEDDED_H_
#include <linux/types.h>
#include <linux/ssb/ssb.h>
extern int ssb_watchdog_timer_set(struct ssb_bus *bus, u32 ticks);
/* Generic GPIO API */
u32 ssb_gpio_in(struct ssb_bus *bus, u32 mask);
u32 ssb_gpio_out(struct ssb_bus *bus, u32 mask, u32 value);
u32 ssb_gpio_outen(struct ssb_bus *bus, u32 mask, u32 value);
u32 ssb_gpio_control(struct ssb_bus *bus, u32 mask, u32 value);
u32 ssb_gpio_intmask(struct ssb_bus *bus, u32 mask, u32 value);
u32 ssb_gpio_polarity(struct ssb_bus *bus, u32 mask, u32 value);
#endif /* LINUX_SSB_EMBEDDED_H_ */
|
/* SPDX-License-Identifier: GPL-2.0 */
#ifndef __ASM_CSKY_CKMMUV1_H
#define __ASM_CSKY_CKMMUV1_H
#include <abi/reg_ops.h>
static inline int read_mmu_index(void)
{
return cprcr("cpcr0");
}
static inline void write_mmu_index(int value)
{
cpwcr("cpcr0", value);
}
static inline int read_mmu_entrylo0(void)
{
return cprcr("cpcr2") << 6;
}
static inline int read_mmu_entrylo1(void)
{
return cprcr("cpcr3") << 6;
}
static inline void write_mmu_pagemask(int value)
{
cpwcr("cpcr6", value);
}
static inline int read_mmu_entryhi(void)
{
return cprcr("cpcr4");
}
static inline void write_mmu_entryhi(int value)
{
cpwcr("cpcr4", value);
}
static inline unsigned long read_mmu_msa0(void)
{
return cprcr("cpcr30");
}
static inline void write_mmu_msa0(unsigned long value)
{
cpwcr("cpcr30", value);
}
static inline unsigned long read_mmu_msa1(void)
{
return cprcr("cpcr31");
}
static inline void write_mmu_msa1(unsigned long value)
{
cpwcr("cpcr31", value);
}
/*
* TLB operations.
*/
static inline void tlb_probe(void)
{
cpwcr("cpcr8", 0x80000000);
}
static inline void tlb_read(void)
{
cpwcr("cpcr8", 0x40000000);
}
static inline void tlb_invalid_all(void)
{
cpwcr("cpcr8", 0x04000000);
}
static inline void local_tlb_invalid_all(void)
{
tlb_invalid_all();
}
static inline void tlb_invalid_indexed(void)
{
cpwcr("cpcr8", 0x02000000);
}
static inline void setup_pgd(pgd_t *pgd, int asid)
{
cpwcr("cpcr29", __pa(pgd) | BIT(0));
write_mmu_entryhi(asid);
}
static inline pgd_t *get_pgd(void)
{
return __va(cprcr("cpcr29") & ~BIT(0));
}
#endif /* __ASM_CSKY_CKMMUV1_H */
|
// SPDX-License-Identifier: GPL-2.0-or-later
/*
yuv support
Copyright (C) 2007 Ian Armstrong <[email protected]>
*/
#include "ivtv-driver.h"
#include "ivtv-udma.h"
#include "ivtv-yuv.h"
/* YUV buffer offsets */
const u32 yuv_offset[IVTV_YUV_BUFFERS] = {
0x001a8600,
0x00240400,
0x002d8200,
0x00370000,
0x00029000,
0x000C0E00,
0x006B0400,
0x00748200
};
static int ivtv_yuv_prep_user_dma(struct ivtv *itv, struct ivtv_user_dma *dma,
struct ivtv_dma_frame *args)
{
struct ivtv_dma_page_info y_dma;
struct ivtv_dma_page_info uv_dma;
struct yuv_playback_info *yi = &itv->yuv_info;
u8 frame = yi->draw_frame;
struct yuv_frame_info *f = &yi->new_frame_info[frame];
int y_pages, uv_pages;
unsigned long y_buffer_offset, uv_buffer_offset;
int y_decode_height, uv_decode_height, y_size;
y_buffer_offset = IVTV_DECODER_OFFSET + yuv_offset[frame];
uv_buffer_offset = y_buffer_offset + IVTV_YUV_BUFFER_UV_OFFSET;
y_decode_height = uv_decode_height = f->src_h + f->src_y;
if (f->offset_y)
y_buffer_offset += 720 * 16;
if (y_decode_height & 15)
y_decode_height = (y_decode_height + 16) & ~15;
if (uv_decode_height & 31)
uv_decode_height = (uv_decode_height + 32) & ~31;
y_size = 720 * y_decode_height;
/* Still in USE */
if (dma->SG_length || dma->page_count) {
IVTV_DEBUG_WARN
("prep_user_dma: SG_length %d page_count %d still full?\n",
dma->SG_length, dma->page_count);
return -EBUSY;
}
ivtv_udma_get_page_info (&y_dma, (unsigned long)args->y_source, 720 * y_decode_height);
ivtv_udma_get_page_info (&uv_dma, (unsigned long)args->uv_source, 360 * uv_decode_height);
/* Pin user pages for DMA Xfer */
y_pages = pin_user_pages_unlocked(y_dma.uaddr,
y_dma.page_count, &dma->map[0], 0);
uv_pages = 0; /* silence gcc. value is set and consumed only if: */
if (y_pages == y_dma.page_count) {
uv_pages = pin_user_pages_unlocked(uv_dma.uaddr,
uv_dma.page_count, &dma->map[y_pages], 0);
}
if (y_pages != y_dma.page_count || uv_pages != uv_dma.page_count) {
int rc = -EFAULT;
if (y_pages == y_dma.page_count) {
IVTV_DEBUG_WARN
("failed to map uv user pages, returned %d expecting %d\n",
uv_pages, uv_dma.page_count);
if (uv_pages >= 0) {
unpin_user_pages(&dma->map[y_pages], uv_pages);
rc = -EFAULT;
} else {
rc = uv_pages;
}
} else {
IVTV_DEBUG_WARN
("failed to map y user pages, returned %d expecting %d\n",
y_pages, y_dma.page_count);
}
if (y_pages >= 0) {
unpin_user_pages(dma->map, y_pages);
/*
* Inherit the -EFAULT from rc's
* initialization, but allow it to be
* overridden by uv_pages above if it was an
* actual errno.
*/
} else {
rc = y_pages;
}
return rc;
}
dma->page_count = y_pages + uv_pages;
/* Fill & map SG List */
if (ivtv_udma_fill_sg_list (dma, &uv_dma, ivtv_udma_fill_sg_list (dma, &y_dma, 0)) < 0) {
IVTV_DEBUG_WARN("could not allocate bounce buffers for highmem userspace buffers\n");
unpin_user_pages(dma->map, dma->page_count);
dma->page_count = 0;
return -ENOMEM;
}
dma->SG_length = dma_map_sg(&itv->pdev->dev, dma->SGlist,
dma->page_count, DMA_TO_DEVICE);
if (!dma->SG_length) {
IVTV_DEBUG_WARN("%s: DMA map error, SG_length is 0\n", __func__);
unpin_user_pages(dma->map, dma->page_count);
dma->page_count = 0;
return -EINVAL;
}
/* Fill SG Array with new values */
ivtv_udma_fill_sg_array(dma, y_buffer_offset, uv_buffer_offset, y_size);
/* If we've offset the y plane, ensure top area is blanked */
if (f->offset_y && yi->blanking_dmaptr) {
dma->SGarray[dma->SG_length].size = cpu_to_le32(720*16);
dma->SGarray[dma->SG_length].src = cpu_to_le32(yi->blanking_dmaptr);
dma->SGarray[dma->SG_length].dst = cpu_to_le32(IVTV_DECODER_OFFSET + yuv_offset[frame]);
dma->SG_length++;
}
/* Tag SG Array with Interrupt Bit */
dma->SGarray[dma->SG_length - 1].size |= cpu_to_le32(0x80000000);
ivtv_udma_sync_for_device(itv);
return 0;
}
/* We rely on a table held in the firmware - Quick check. */
int ivtv_yuv_filter_check(struct ivtv *itv)
{
int i, y, uv;
for (i = 0, y = 16, uv = 4; i < 16; i++, y += 24, uv += 12) {
if ((read_dec(IVTV_YUV_HORIZONTAL_FILTER_OFFSET + y) != i << 16) ||
(read_dec(IVTV_YUV_VERTICAL_FILTER_OFFSET + uv) != i << 16)) {
IVTV_WARN ("YUV filter table not found in firmware.\n");
return -1;
}
}
return 0;
}
static void ivtv_yuv_filter(struct ivtv *itv, int h_filter, int v_filter_1, int v_filter_2)
{
u32 i, line;
/* If any filter is -1, then don't update it */
if (h_filter > -1) {
if (h_filter > 4)
h_filter = 4;
i = IVTV_YUV_HORIZONTAL_FILTER_OFFSET + (h_filter * 384);
for (line = 0; line < 16; line++) {
write_reg(read_dec(i), 0x02804);
write_reg(read_dec(i), 0x0281c);
i += 4;
write_reg(read_dec(i), 0x02808);
write_reg(read_dec(i), 0x02820);
i += 4;
write_reg(read_dec(i), 0x0280c);
write_reg(read_dec(i), 0x02824);
i += 4;
write_reg(read_dec(i), 0x02810);
write_reg(read_dec(i), 0x02828);
i += 4;
write_reg(read_dec(i), 0x02814);
write_reg(read_dec(i), 0x0282c);
i += 8;
write_reg(0, 0x02818);
write_reg(0, 0x02830);
}
IVTV_DEBUG_YUV("h_filter -> %d\n", h_filter);
}
if (v_filter_1 > -1) {
if (v_filter_1 > 4)
v_filter_1 = 4;
i = IVTV_YUV_VERTICAL_FILTER_OFFSET + (v_filter_1 * 192);
for (line = 0; line < 16; line++) {
write_reg(read_dec(i), 0x02900);
i += 4;
write_reg(read_dec(i), 0x02904);
i += 8;
write_reg(0, 0x02908);
}
IVTV_DEBUG_YUV("v_filter_1 -> %d\n", v_filter_1);
}
if (v_filter_2 > -1) {
if (v_filter_2 > 4)
v_filter_2 = 4;
i = IVTV_YUV_VERTICAL_FILTER_OFFSET + (v_filter_2 * 192);
for (line = 0; line < 16; line++) {
write_reg(read_dec(i), 0x0290c);
i += 4;
write_reg(read_dec(i), 0x02910);
i += 8;
write_reg(0, 0x02914);
}
IVTV_DEBUG_YUV("v_filter_2 -> %d\n", v_filter_2);
}
}
static void ivtv_yuv_handle_horizontal(struct ivtv *itv, struct yuv_frame_info *f)
{
struct yuv_playback_info *yi = &itv->yuv_info;
u32 reg_2834, reg_2838, reg_283c;
u32 reg_2844, reg_2854, reg_285c;
u32 reg_2864, reg_2874, reg_2890;
u32 reg_2870, reg_2870_base, reg_2870_offset;
int x_cutoff;
int h_filter;
u32 master_width;
IVTV_DEBUG_WARN
("Adjust to width %d src_w %d dst_w %d src_x %d dst_x %d\n",
f->tru_w, f->src_w, f->dst_w, f->src_x, f->dst_x);
/* How wide is the src image */
x_cutoff = f->src_w + f->src_x;
/* Set the display width */
reg_2834 = f->dst_w;
reg_2838 = reg_2834;
/* Set the display position */
reg_2890 = f->dst_x;
/* Index into the image horizontally */
reg_2870 = 0;
/* 2870 is normally fudged to align video coords with osd coords.
If running full screen, it causes an unwanted left shift
Remove the fudge if we almost fill the screen.
Gradually adjust the offset to avoid the video 'snapping'
left/right if it gets dragged through this region.
Only do this if osd is full width. */
if (f->vis_w == 720) {
if ((f->tru_x - f->pan_x > -1) && (f->tru_x - f->pan_x <= 40) && (f->dst_w >= 680))
reg_2870 = 10 - (f->tru_x - f->pan_x) / 4;
else if ((f->tru_x - f->pan_x < 0) && (f->tru_x - f->pan_x >= -20) && (f->dst_w >= 660))
reg_2870 = (10 + (f->tru_x - f->pan_x) / 2);
if (f->dst_w >= f->src_w)
reg_2870 = reg_2870 << 16 | reg_2870;
else
reg_2870 = ((reg_2870 & ~1) << 15) | (reg_2870 & ~1);
}
if (f->dst_w < f->src_w)
reg_2870 = 0x000d000e - reg_2870;
else
reg_2870 = 0x0012000e - reg_2870;
/* We're also using 2870 to shift the image left (src_x & negative dst_x) */
reg_2870_offset = (f->src_x * ((f->dst_w << 21) / f->src_w)) >> 19;
if (f->dst_w >= f->src_w) {
x_cutoff &= ~1;
master_width = (f->src_w * 0x00200000) / (f->dst_w);
if (master_width * f->dst_w != f->src_w * 0x00200000)
master_width++;
reg_2834 = (reg_2834 << 16) | x_cutoff;
reg_2838 = (reg_2838 << 16) | x_cutoff;
reg_283c = master_width >> 2;
reg_2844 = master_width >> 2;
reg_2854 = master_width;
reg_285c = master_width >> 1;
reg_2864 = master_width >> 1;
/* We also need to factor in the scaling
(src_w - dst_w) / (src_w / 4) */
if (f->dst_w > f->src_w)
reg_2870_base = ((f->dst_w - f->src_w)<<16) / (f->src_w <<14);
else
reg_2870_base = 0;
reg_2870 += (((reg_2870_offset << 14) & 0xFFFF0000) | reg_2870_offset >> 2) + (reg_2870_base << 17 | reg_2870_base);
reg_2874 = 0;
} else if (f->dst_w < f->src_w / 2) {
master_width = (f->src_w * 0x00080000) / f->dst_w;
if (master_width * f->dst_w != f->src_w * 0x00080000)
master_width++;
reg_2834 = (reg_2834 << 16) | x_cutoff;
reg_2838 = (reg_2838 << 16) | x_cutoff;
reg_283c = master_width >> 2;
reg_2844 = master_width >> 1;
reg_2854 = master_width;
reg_285c = master_width >> 1;
reg_2864 = master_width >> 1;
reg_2870 += ((reg_2870_offset << 15) & 0xFFFF0000) | reg_2870_offset;
reg_2870 += (5 - (((f->src_w + f->src_w / 2) - 1) / f->dst_w)) << 16;
reg_2874 = 0x00000012;
} else {
master_width = (f->src_w * 0x00100000) / f->dst_w;
if (master_width * f->dst_w != f->src_w * 0x00100000)
master_width++;
reg_2834 = (reg_2834 << 16) | x_cutoff;
reg_2838 = (reg_2838 << 16) | x_cutoff;
reg_283c = master_width >> 2;
reg_2844 = master_width >> 1;
reg_2854 = master_width;
reg_285c = master_width >> 1;
reg_2864 = master_width >> 1;
reg_2870 += ((reg_2870_offset << 14) & 0xFFFF0000) | reg_2870_offset >> 1;
reg_2870 += (5 - (((f->src_w * 3) - 1) / f->dst_w)) << 16;
reg_2874 = 0x00000001;
}
/* Select the horizontal filter */
if (f->src_w == f->dst_w) {
/* An exact size match uses filter 0 */
h_filter = 0;
} else {
/* Figure out which filter to use */
h_filter = ((f->src_w << 16) / f->dst_w) >> 15;
h_filter = (h_filter >> 1) + (h_filter & 1);
/* Only an exact size match can use filter 0 */
h_filter += !h_filter;
}
write_reg(reg_2834, 0x02834);
write_reg(reg_2838, 0x02838);
IVTV_DEBUG_YUV("Update reg 0x2834 %08x->%08x 0x2838 %08x->%08x\n",
yi->reg_2834, reg_2834, yi->reg_2838, reg_2838);
write_reg(reg_283c, 0x0283c);
write_reg(reg_2844, 0x02844);
IVTV_DEBUG_YUV("Update reg 0x283c %08x->%08x 0x2844 %08x->%08x\n",
yi->reg_283c, reg_283c, yi->reg_2844, reg_2844);
write_reg(0x00080514, 0x02840);
write_reg(0x00100514, 0x02848);
IVTV_DEBUG_YUV("Update reg 0x2840 %08x->%08x 0x2848 %08x->%08x\n",
yi->reg_2840, 0x00080514, yi->reg_2848, 0x00100514);
write_reg(reg_2854, 0x02854);
IVTV_DEBUG_YUV("Update reg 0x2854 %08x->%08x \n",
yi->reg_2854, reg_2854);
write_reg(reg_285c, 0x0285c);
write_reg(reg_2864, 0x02864);
IVTV_DEBUG_YUV("Update reg 0x285c %08x->%08x 0x2864 %08x->%08x\n",
yi->reg_285c, reg_285c, yi->reg_2864, reg_2864);
write_reg(reg_2874, 0x02874);
IVTV_DEBUG_YUV("Update reg 0x2874 %08x->%08x\n",
yi->reg_2874, reg_2874);
write_reg(reg_2870, 0x02870);
IVTV_DEBUG_YUV("Update reg 0x2870 %08x->%08x\n",
yi->reg_2870, reg_2870);
write_reg(reg_2890, 0x02890);
IVTV_DEBUG_YUV("Update reg 0x2890 %08x->%08x\n",
yi->reg_2890, reg_2890);
/* Only update the filter if we really need to */
if (h_filter != yi->h_filter) {
ivtv_yuv_filter(itv, h_filter, -1, -1);
yi->h_filter = h_filter;
}
}
static void ivtv_yuv_handle_vertical(struct ivtv *itv, struct yuv_frame_info *f)
{
struct yuv_playback_info *yi = &itv->yuv_info;
u32 master_height;
u32 reg_2918, reg_291c, reg_2920, reg_2928;
u32 reg_2930, reg_2934, reg_293c;
u32 reg_2940, reg_2944, reg_294c;
u32 reg_2950, reg_2954, reg_2958, reg_295c;
u32 reg_2960, reg_2964, reg_2968, reg_296c;
u32 reg_289c;
u32 src_major_y, src_minor_y;
u32 src_major_uv, src_minor_uv;
u32 reg_2964_base, reg_2968_base;
int v_filter_1, v_filter_2;
IVTV_DEBUG_WARN
("Adjust to height %d src_h %d dst_h %d src_y %d dst_y %d\n",
f->tru_h, f->src_h, f->dst_h, f->src_y, f->dst_y);
/* What scaling mode is being used... */
IVTV_DEBUG_YUV("Scaling mode Y: %s\n",
f->interlaced_y ? "Interlaced" : "Progressive");
IVTV_DEBUG_YUV("Scaling mode UV: %s\n",
f->interlaced_uv ? "Interlaced" : "Progressive");
/* What is the source video being treated as... */
IVTV_DEBUG_WARN("Source video: %s\n",
f->interlaced ? "Interlaced" : "Progressive");
/* We offset into the image using two different index methods, so split
the y source coord into two parts. */
if (f->src_y < 8) {
src_minor_uv = f->src_y;
src_major_uv = 0;
} else {
src_minor_uv = 8;
src_major_uv = f->src_y - 8;
}
src_minor_y = src_minor_uv;
src_major_y = src_major_uv;
if (f->offset_y)
src_minor_y += 16;
if (f->interlaced_y)
reg_2918 = (f->dst_h << 16) | (f->src_h + src_minor_y);
else
reg_2918 = (f->dst_h << 16) | ((f->src_h + src_minor_y) << 1);
if (f->interlaced_uv)
reg_291c = (f->dst_h << 16) | ((f->src_h + src_minor_uv) >> 1);
else
reg_291c = (f->dst_h << 16) | (f->src_h + src_minor_uv);
reg_2964_base = (src_minor_y * ((f->dst_h << 16) / f->src_h)) >> 14;
reg_2968_base = (src_minor_uv * ((f->dst_h << 16) / f->src_h)) >> 14;
if (f->dst_h / 2 >= f->src_h && !f->interlaced_y) {
master_height = (f->src_h * 0x00400000) / f->dst_h;
if ((f->src_h * 0x00400000) - (master_height * f->dst_h) >= f->dst_h / 2)
master_height++;
reg_2920 = master_height >> 2;
reg_2928 = master_height >> 3;
reg_2930 = master_height;
reg_2940 = master_height >> 1;
reg_2964_base >>= 3;
reg_2968_base >>= 3;
reg_296c = 0x00000000;
} else if (f->dst_h >= f->src_h) {
master_height = (f->src_h * 0x00400000) / f->dst_h;
master_height = (master_height >> 1) + (master_height & 1);
reg_2920 = master_height >> 2;
reg_2928 = master_height >> 2;
reg_2930 = master_height;
reg_2940 = master_height >> 1;
reg_296c = 0x00000000;
if (f->interlaced_y) {
reg_2964_base >>= 3;
} else {
reg_296c++;
reg_2964_base >>= 2;
}
if (f->interlaced_uv)
reg_2928 >>= 1;
reg_2968_base >>= 3;
} else if (f->dst_h >= f->src_h / 2) {
master_height = (f->src_h * 0x00200000) / f->dst_h;
master_height = (master_height >> 1) + (master_height & 1);
reg_2920 = master_height >> 2;
reg_2928 = master_height >> 2;
reg_2930 = master_height;
reg_2940 = master_height;
reg_296c = 0x00000101;
if (f->interlaced_y) {
reg_2964_base >>= 2;
} else {
reg_296c++;
reg_2964_base >>= 1;
}
if (f->interlaced_uv)
reg_2928 >>= 1;
reg_2968_base >>= 2;
} else {
master_height = (f->src_h * 0x00100000) / f->dst_h;
master_height = (master_height >> 1) + (master_height & 1);
reg_2920 = master_height >> 2;
reg_2928 = master_height >> 2;
reg_2930 = master_height;
reg_2940 = master_height;
reg_2964_base >>= 1;
reg_2968_base >>= 2;
reg_296c = 0x00000102;
}
/* FIXME These registers change depending on scaled / unscaled output
We really need to work out what they should be */
if (f->src_h == f->dst_h) {
reg_2934 = 0x00020000;
reg_293c = 0x00100000;
reg_2944 = 0x00040000;
reg_294c = 0x000b0000;
} else {
reg_2934 = 0x00000FF0;
reg_293c = 0x00000FF0;
reg_2944 = 0x00000FF0;
reg_294c = 0x00000FF0;
}
/* The first line to be displayed */
reg_2950 = 0x00010000 + src_major_y;
if (f->interlaced_y)
reg_2950 += 0x00010000;
reg_2954 = reg_2950 + 1;
reg_2958 = 0x00010000 + (src_major_y >> 1);
if (f->interlaced_uv)
reg_2958 += 0x00010000;
reg_295c = reg_2958 + 1;
if (yi->decode_height == 480)
reg_289c = 0x011e0017;
else
reg_289c = 0x01500017;
if (f->dst_y < 0)
reg_289c = (reg_289c - ((f->dst_y & ~1)<<15))-(f->dst_y >>1);
else
reg_289c = (reg_289c + ((f->dst_y & ~1)<<15))+(f->dst_y >>1);
/* How much of the source to decode.
Take into account the source offset */
reg_2960 = ((src_minor_y + f->src_h + src_major_y) - 1) |
(((src_minor_uv + f->src_h + src_major_uv - 1) & ~1) << 15);
/* Calculate correct value for register 2964 */
if (f->src_h == f->dst_h) {
reg_2964 = 1;
} else {
reg_2964 = 2 + ((f->dst_h << 1) / f->src_h);
reg_2964 = (reg_2964 >> 1) + (reg_2964 & 1);
}
reg_2968 = (reg_2964 << 16) + reg_2964 + (reg_2964 >> 1);
reg_2964 = (reg_2964 << 16) + reg_2964 + (reg_2964 * 46 / 94);
/* Okay, we've wasted time working out the correct value,
but if we use it, it fouls the window alignment.
Fudge it to what we want... */
reg_2964 = 0x00010001 + ((reg_2964 & 0x0000FFFF) - (reg_2964 >> 16));
reg_2968 = 0x00010001 + ((reg_2968 & 0x0000FFFF) - (reg_2968 >> 16));
/* Deviate further from what it should be. I find the flicker headache
inducing so try to reduce it slightly. Leave 2968 as-is otherwise
colours foul. */
if ((reg_2964 != 0x00010001) && (f->dst_h / 2 <= f->src_h))
reg_2964 = (reg_2964 & 0xFFFF0000) + ((reg_2964 & 0x0000FFFF) / 2);
if (!f->interlaced_y)
reg_2964 -= 0x00010001;
if (!f->interlaced_uv)
reg_2968 -= 0x00010001;
reg_2964 += ((reg_2964_base << 16) | reg_2964_base);
reg_2968 += ((reg_2968_base << 16) | reg_2968_base);
/* Select the vertical filter */
if (f->src_h == f->dst_h) {
/* An exact size match uses filter 0/1 */
v_filter_1 = 0;
v_filter_2 = 1;
} else {
/* Figure out which filter to use */
v_filter_1 = ((f->src_h << 16) / f->dst_h) >> 15;
v_filter_1 = (v_filter_1 >> 1) + (v_filter_1 & 1);
/* Only an exact size match can use filter 0 */
v_filter_1 += !v_filter_1;
v_filter_2 = v_filter_1;
}
write_reg(reg_2934, 0x02934);
write_reg(reg_293c, 0x0293c);
IVTV_DEBUG_YUV("Update reg 0x2934 %08x->%08x 0x293c %08x->%08x\n",
yi->reg_2934, reg_2934, yi->reg_293c, reg_293c);
write_reg(reg_2944, 0x02944);
write_reg(reg_294c, 0x0294c);
IVTV_DEBUG_YUV("Update reg 0x2944 %08x->%08x 0x294c %08x->%08x\n",
yi->reg_2944, reg_2944, yi->reg_294c, reg_294c);
/* Ensure 2970 is 0 (does it ever change ?) */
/* write_reg(0,0x02970); */
/* IVTV_DEBUG_YUV("Update reg 0x2970 %08x->%08x\n", yi->reg_2970, 0); */
write_reg(reg_2930, 0x02938);
write_reg(reg_2930, 0x02930);
IVTV_DEBUG_YUV("Update reg 0x2930 %08x->%08x 0x2938 %08x->%08x\n",
yi->reg_2930, reg_2930, yi->reg_2938, reg_2930);
write_reg(reg_2928, 0x02928);
write_reg(reg_2928 + 0x514, 0x0292C);
IVTV_DEBUG_YUV("Update reg 0x2928 %08x->%08x 0x292c %08x->%08x\n",
yi->reg_2928, reg_2928, yi->reg_292c, reg_2928 + 0x514);
write_reg(reg_2920, 0x02920);
write_reg(reg_2920 + 0x514, 0x02924);
IVTV_DEBUG_YUV("Update reg 0x2920 %08x->%08x 0x2924 %08x->%08x\n",
yi->reg_2920, reg_2920, yi->reg_2924, reg_2920 + 0x514);
write_reg(reg_2918, 0x02918);
write_reg(reg_291c, 0x0291C);
IVTV_DEBUG_YUV("Update reg 0x2918 %08x->%08x 0x291C %08x->%08x\n",
yi->reg_2918, reg_2918, yi->reg_291c, reg_291c);
write_reg(reg_296c, 0x0296c);
IVTV_DEBUG_YUV("Update reg 0x296c %08x->%08x\n",
yi->reg_296c, reg_296c);
write_reg(reg_2940, 0x02948);
write_reg(reg_2940, 0x02940);
IVTV_DEBUG_YUV("Update reg 0x2940 %08x->%08x 0x2948 %08x->%08x\n",
yi->reg_2940, reg_2940, yi->reg_2948, reg_2940);
write_reg(reg_2950, 0x02950);
write_reg(reg_2954, 0x02954);
IVTV_DEBUG_YUV("Update reg 0x2950 %08x->%08x 0x2954 %08x->%08x\n",
yi->reg_2950, reg_2950, yi->reg_2954, reg_2954);
write_reg(reg_2958, 0x02958);
write_reg(reg_295c, 0x0295C);
IVTV_DEBUG_YUV("Update reg 0x2958 %08x->%08x 0x295C %08x->%08x\n",
yi->reg_2958, reg_2958, yi->reg_295c, reg_295c);
write_reg(reg_2960, 0x02960);
IVTV_DEBUG_YUV("Update reg 0x2960 %08x->%08x \n",
yi->reg_2960, reg_2960);
write_reg(reg_2964, 0x02964);
write_reg(reg_2968, 0x02968);
IVTV_DEBUG_YUV("Update reg 0x2964 %08x->%08x 0x2968 %08x->%08x\n",
yi->reg_2964, reg_2964, yi->reg_2968, reg_2968);
write_reg(reg_289c, 0x0289c);
IVTV_DEBUG_YUV("Update reg 0x289c %08x->%08x\n",
yi->reg_289c, reg_289c);
/* Only update filter 1 if we really need to */
if (v_filter_1 != yi->v_filter_1) {
ivtv_yuv_filter(itv, -1, v_filter_1, -1);
yi->v_filter_1 = v_filter_1;
}
/* Only update filter 2 if we really need to */
if (v_filter_2 != yi->v_filter_2) {
ivtv_yuv_filter(itv, -1, -1, v_filter_2);
yi->v_filter_2 = v_filter_2;
}
}
/* Modify the supplied coordinate information to fit the visible osd area */
static u32 ivtv_yuv_window_setup(struct ivtv *itv, struct yuv_frame_info *f)
{
struct yuv_frame_info *of = &itv->yuv_info.old_frame_info;
int osd_crop;
u32 osd_scale;
u32 yuv_update = 0;
/* Sorry, but no negative coords for src */
if (f->src_x < 0)
f->src_x = 0;
if (f->src_y < 0)
f->src_y = 0;
/* Can only reduce width down to 1/4 original size */
if ((osd_crop = f->src_w - 4 * f->dst_w) > 0) {
f->src_x += osd_crop / 2;
f->src_w = (f->src_w - osd_crop) & ~3;
f->dst_w = f->src_w / 4;
f->dst_w += f->dst_w & 1;
}
/* Can only reduce height down to 1/4 original size */
if (f->src_h / f->dst_h >= 2) {
/* Overflow may be because we're running progressive,
so force mode switch */
f->interlaced_y = 1;
/* Make sure we're still within limits for interlace */
if ((osd_crop = f->src_h - 4 * f->dst_h) > 0) {
/* If we reach here we'll have to force the height. */
f->src_y += osd_crop / 2;
f->src_h = (f->src_h - osd_crop) & ~3;
f->dst_h = f->src_h / 4;
f->dst_h += f->dst_h & 1;
}
}
/* If there's nothing to safe to display, we may as well stop now */
if ((int)f->dst_w <= 2 || (int)f->dst_h <= 2 ||
(int)f->src_w <= 2 || (int)f->src_h <= 2) {
return IVTV_YUV_UPDATE_INVALID;
}
/* Ensure video remains inside OSD area */
osd_scale = (f->src_h << 16) / f->dst_h;
if ((osd_crop = f->pan_y - f->dst_y) > 0) {
/* Falls off the upper edge - crop */
f->src_y += (osd_scale * osd_crop) >> 16;
f->src_h -= (osd_scale * osd_crop) >> 16;
f->dst_h -= osd_crop;
f->dst_y = 0;
} else {
f->dst_y -= f->pan_y;
}
if ((osd_crop = f->dst_h + f->dst_y - f->vis_h) > 0) {
/* Falls off the lower edge - crop */
f->dst_h -= osd_crop;
f->src_h -= (osd_scale * osd_crop) >> 16;
}
osd_scale = (f->src_w << 16) / f->dst_w;
if ((osd_crop = f->pan_x - f->dst_x) > 0) {
/* Fall off the left edge - crop */
f->src_x += (osd_scale * osd_crop) >> 16;
f->src_w -= (osd_scale * osd_crop) >> 16;
f->dst_w -= osd_crop;
f->dst_x = 0;
} else {
f->dst_x -= f->pan_x;
}
if ((osd_crop = f->dst_w + f->dst_x - f->vis_w) > 0) {
/* Falls off the right edge - crop */
f->dst_w -= osd_crop;
f->src_w -= (osd_scale * osd_crop) >> 16;
}
if (itv->yuv_info.track_osd) {
/* The OSD can be moved. Track to it */
f->dst_x += itv->yuv_info.osd_x_offset;
f->dst_y += itv->yuv_info.osd_y_offset;
}
/* Width & height for both src & dst must be even.
Same for coordinates. */
f->dst_w &= ~1;
f->dst_x &= ~1;
f->src_w += f->src_x & 1;
f->src_x &= ~1;
f->src_w &= ~1;
f->dst_w &= ~1;
f->dst_h &= ~1;
f->dst_y &= ~1;
f->src_h += f->src_y & 1;
f->src_y &= ~1;
f->src_h &= ~1;
f->dst_h &= ~1;
/* Due to rounding, we may have reduced the output size to <1/4 of
the source. Check again, but this time just resize. Don't change
source coordinates */
if (f->dst_w < f->src_w / 4) {
f->src_w &= ~3;
f->dst_w = f->src_w / 4;
f->dst_w += f->dst_w & 1;
}
if (f->dst_h < f->src_h / 4) {
f->src_h &= ~3;
f->dst_h = f->src_h / 4;
f->dst_h += f->dst_h & 1;
}
/* Check again. If there's nothing to safe to display, stop now */
if ((int)f->dst_w <= 2 || (int)f->dst_h <= 2 ||
(int)f->src_w <= 2 || (int)f->src_h <= 2) {
return IVTV_YUV_UPDATE_INVALID;
}
/* Both x offset & width are linked, so they have to be done together */
if ((of->dst_w != f->dst_w) || (of->src_w != f->src_w) ||
(of->dst_x != f->dst_x) || (of->src_x != f->src_x) ||
(of->pan_x != f->pan_x) || (of->vis_w != f->vis_w)) {
yuv_update |= IVTV_YUV_UPDATE_HORIZONTAL;
}
if ((of->src_h != f->src_h) || (of->dst_h != f->dst_h) ||
(of->dst_y != f->dst_y) || (of->src_y != f->src_y) ||
(of->pan_y != f->pan_y) || (of->vis_h != f->vis_h) ||
(of->lace_mode != f->lace_mode) ||
(of->interlaced_y != f->interlaced_y) ||
(of->interlaced_uv != f->interlaced_uv)) {
yuv_update |= IVTV_YUV_UPDATE_VERTICAL;
}
return yuv_update;
}
/* Update the scaling register to the requested value */
void ivtv_yuv_work_handler(struct ivtv *itv)
{
struct yuv_playback_info *yi = &itv->yuv_info;
struct yuv_frame_info f;
int frame = yi->update_frame;
u32 yuv_update;
IVTV_DEBUG_YUV("Update yuv registers for frame %d\n", frame);
f = yi->new_frame_info[frame];
if (yi->track_osd) {
/* Snapshot the osd pan info */
f.pan_x = yi->osd_x_pan;
f.pan_y = yi->osd_y_pan;
f.vis_w = yi->osd_vis_w;
f.vis_h = yi->osd_vis_h;
} else {
/* Not tracking the osd, so assume full screen */
f.pan_x = 0;
f.pan_y = 0;
f.vis_w = 720;
f.vis_h = yi->decode_height;
}
/* Calculate the display window coordinates. Exit if nothing left */
if (!(yuv_update = ivtv_yuv_window_setup(itv, &f)))
return;
if (yuv_update & IVTV_YUV_UPDATE_INVALID) {
write_reg(0x01008080, 0x2898);
} else if (yuv_update) {
write_reg(0x00108080, 0x2898);
if (yuv_update & IVTV_YUV_UPDATE_HORIZONTAL)
ivtv_yuv_handle_horizontal(itv, &f);
if (yuv_update & IVTV_YUV_UPDATE_VERTICAL)
ivtv_yuv_handle_vertical(itv, &f);
}
yi->old_frame_info = f;
}
static void ivtv_yuv_init(struct ivtv *itv)
{
struct yuv_playback_info *yi = &itv->yuv_info;
IVTV_DEBUG_YUV("ivtv_yuv_init\n");
/* Take a snapshot of the current register settings */
yi->reg_2834 = read_reg(0x02834);
yi->reg_2838 = read_reg(0x02838);
yi->reg_283c = read_reg(0x0283c);
yi->reg_2840 = read_reg(0x02840);
yi->reg_2844 = read_reg(0x02844);
yi->reg_2848 = read_reg(0x02848);
yi->reg_2854 = read_reg(0x02854);
yi->reg_285c = read_reg(0x0285c);
yi->reg_2864 = read_reg(0x02864);
yi->reg_2870 = read_reg(0x02870);
yi->reg_2874 = read_reg(0x02874);
yi->reg_2898 = read_reg(0x02898);
yi->reg_2890 = read_reg(0x02890);
yi->reg_289c = read_reg(0x0289c);
yi->reg_2918 = read_reg(0x02918);
yi->reg_291c = read_reg(0x0291c);
yi->reg_2920 = read_reg(0x02920);
yi->reg_2924 = read_reg(0x02924);
yi->reg_2928 = read_reg(0x02928);
yi->reg_292c = read_reg(0x0292c);
yi->reg_2930 = read_reg(0x02930);
yi->reg_2934 = read_reg(0x02934);
yi->reg_2938 = read_reg(0x02938);
yi->reg_293c = read_reg(0x0293c);
yi->reg_2940 = read_reg(0x02940);
yi->reg_2944 = read_reg(0x02944);
yi->reg_2948 = read_reg(0x02948);
yi->reg_294c = read_reg(0x0294c);
yi->reg_2950 = read_reg(0x02950);
yi->reg_2954 = read_reg(0x02954);
yi->reg_2958 = read_reg(0x02958);
yi->reg_295c = read_reg(0x0295c);
yi->reg_2960 = read_reg(0x02960);
yi->reg_2964 = read_reg(0x02964);
yi->reg_2968 = read_reg(0x02968);
yi->reg_296c = read_reg(0x0296c);
yi->reg_2970 = read_reg(0x02970);
yi->v_filter_1 = -1;
yi->v_filter_2 = -1;
yi->h_filter = -1;
/* Set some valid size info */
yi->osd_x_offset = read_reg(0x02a04) & 0x00000FFF;
yi->osd_y_offset = (read_reg(0x02a04) >> 16) & 0x00000FFF;
/* Bit 2 of reg 2878 indicates current decoder output format
0 : NTSC 1 : PAL */
if (read_reg(0x2878) & 4)
yi->decode_height = 576;
else
yi->decode_height = 480;
if (!itv->osd_info) {
yi->osd_vis_w = 720 - yi->osd_x_offset;
yi->osd_vis_h = yi->decode_height - yi->osd_y_offset;
} else {
/* If no visible size set, assume full size */
if (!yi->osd_vis_w)
yi->osd_vis_w = 720 - yi->osd_x_offset;
if (!yi->osd_vis_h) {
yi->osd_vis_h = yi->decode_height - yi->osd_y_offset;
} else if (yi->osd_vis_h + yi->osd_y_offset > yi->decode_height) {
/* If output video standard has changed, requested height may
not be legal */
IVTV_DEBUG_WARN("Clipping yuv output - fb size (%d) exceeds video standard limit (%d)\n",
yi->osd_vis_h + yi->osd_y_offset,
yi->decode_height);
yi->osd_vis_h = yi->decode_height - yi->osd_y_offset;
}
}
/* We need a buffer for blanking when Y plane is offset - non-fatal if we can't get one */
yi->blanking_ptr = kzalloc(720 * 16, GFP_ATOMIC|__GFP_NOWARN);
if (yi->blanking_ptr) {
yi->blanking_dmaptr = dma_map_single(&itv->pdev->dev,
yi->blanking_ptr,
720 * 16, DMA_TO_DEVICE);
} else {
yi->blanking_dmaptr = 0;
IVTV_DEBUG_WARN("Failed to allocate yuv blanking buffer\n");
}
/* Enable YUV decoder output */
write_reg_sync(0x01, IVTV_REG_VDM);
set_bit(IVTV_F_I_DECODING_YUV, &itv->i_flags);
atomic_set(&yi->next_dma_frame, 0);
}
/* Get next available yuv buffer on PVR350 */
static void ivtv_yuv_next_free(struct ivtv *itv)
{
int draw, display;
struct yuv_playback_info *yi = &itv->yuv_info;
if (atomic_read(&yi->next_dma_frame) == -1)
ivtv_yuv_init(itv);
draw = atomic_read(&yi->next_fill_frame);
display = atomic_read(&yi->next_dma_frame);
if (display > draw)
display -= IVTV_YUV_BUFFERS;
if (draw - display >= yi->max_frames_buffered)
draw = (u8)(draw - 1) % IVTV_YUV_BUFFERS;
else
yi->new_frame_info[draw].update = 0;
yi->draw_frame = draw;
}
/* Set up frame according to ivtv_dma_frame parameters */
static void ivtv_yuv_setup_frame(struct ivtv *itv, struct ivtv_dma_frame *args)
{
struct yuv_playback_info *yi = &itv->yuv_info;
u8 frame = yi->draw_frame;
u8 last_frame = (u8)(frame - 1) % IVTV_YUV_BUFFERS;
struct yuv_frame_info *nf = &yi->new_frame_info[frame];
struct yuv_frame_info *of = &yi->new_frame_info[last_frame];
int lace_threshold = yi->lace_threshold;
/* Preserve old update flag in case we're overwriting a queued frame */
int update = nf->update;
/* Take a snapshot of the yuv coordinate information */
nf->src_x = args->src.left;
nf->src_y = args->src.top;
nf->src_w = args->src.width;
nf->src_h = args->src.height;
nf->dst_x = args->dst.left;
nf->dst_y = args->dst.top;
nf->dst_w = args->dst.width;
nf->dst_h = args->dst.height;
nf->tru_x = args->dst.left;
nf->tru_w = args->src_width;
nf->tru_h = args->src_height;
/* Are we going to offset the Y plane */
nf->offset_y = (nf->tru_h + nf->src_x < 512 - 16) ? 1 : 0;
nf->update = 0;
nf->interlaced_y = 0;
nf->interlaced_uv = 0;
nf->delay = 0;
nf->sync_field = 0;
nf->lace_mode = yi->lace_mode & IVTV_YUV_MODE_MASK;
if (lace_threshold < 0)
lace_threshold = yi->decode_height - 1;
/* Work out the lace settings */
switch (nf->lace_mode) {
case IVTV_YUV_MODE_PROGRESSIVE: /* Progressive mode */
nf->interlaced = 0;
if (nf->tru_h < 512 || (nf->tru_h > 576 && nf->tru_h < 1021))
nf->interlaced_y = 0;
else
nf->interlaced_y = 1;
if (nf->tru_h < 1021 && (nf->dst_h >= nf->src_h / 2))
nf->interlaced_uv = 0;
else
nf->interlaced_uv = 1;
break;
case IVTV_YUV_MODE_AUTO:
if (nf->tru_h <= lace_threshold || nf->tru_h > 576 || nf->tru_w > 720) {
nf->interlaced = 0;
if ((nf->tru_h < 512) ||
(nf->tru_h > 576 && nf->tru_h < 1021) ||
(nf->tru_w > 720 && nf->tru_h < 1021))
nf->interlaced_y = 0;
else
nf->interlaced_y = 1;
if (nf->tru_h < 1021 && (nf->dst_h >= nf->src_h / 2))
nf->interlaced_uv = 0;
else
nf->interlaced_uv = 1;
} else {
nf->interlaced = 1;
nf->interlaced_y = 1;
nf->interlaced_uv = 1;
}
break;
case IVTV_YUV_MODE_INTERLACED: /* Interlace mode */
default:
nf->interlaced = 1;
nf->interlaced_y = 1;
nf->interlaced_uv = 1;
break;
}
if (memcmp(&yi->old_frame_info_args, nf, sizeof(*nf))) {
yi->old_frame_info_args = *nf;
nf->update = 1;
IVTV_DEBUG_YUV("Requesting reg update for frame %d\n", frame);
}
nf->update |= update;
nf->sync_field = yi->lace_sync_field;
nf->delay = nf->sync_field != of->sync_field;
}
/* Frame is complete & ready for display */
void ivtv_yuv_frame_complete(struct ivtv *itv)
{
atomic_set(&itv->yuv_info.next_fill_frame,
(itv->yuv_info.draw_frame + 1) % IVTV_YUV_BUFFERS);
}
static int ivtv_yuv_udma_frame(struct ivtv *itv, struct ivtv_dma_frame *args)
{
DEFINE_WAIT(wait);
int rc = 0;
int got_sig = 0;
/* DMA the frame */
mutex_lock(&itv->udma.lock);
if ((rc = ivtv_yuv_prep_user_dma(itv, &itv->udma, args)) != 0) {
mutex_unlock(&itv->udma.lock);
return rc;
}
ivtv_udma_prepare(itv);
prepare_to_wait(&itv->dma_waitq, &wait, TASK_INTERRUPTIBLE);
/* if no UDMA is pending and no UDMA is in progress, then the DMA
is finished */
while (test_bit(IVTV_F_I_UDMA_PENDING, &itv->i_flags) ||
test_bit(IVTV_F_I_UDMA, &itv->i_flags)) {
/* don't interrupt if the DMA is in progress but break off
a still pending DMA. */
got_sig = signal_pending(current);
if (got_sig && test_and_clear_bit(IVTV_F_I_UDMA_PENDING, &itv->i_flags))
break;
got_sig = 0;
schedule();
}
finish_wait(&itv->dma_waitq, &wait);
/* Unmap Last DMA Xfer */
ivtv_udma_unmap(itv);
if (got_sig) {
IVTV_DEBUG_INFO("User stopped YUV UDMA\n");
mutex_unlock(&itv->udma.lock);
return -EINTR;
}
ivtv_yuv_frame_complete(itv);
mutex_unlock(&itv->udma.lock);
return rc;
}
/* Setup frame according to V4L2 parameters */
void ivtv_yuv_setup_stream_frame(struct ivtv *itv)
{
struct yuv_playback_info *yi = &itv->yuv_info;
struct ivtv_dma_frame dma_args;
ivtv_yuv_next_free(itv);
/* Copy V4L2 parameters to an ivtv_dma_frame struct... */
dma_args.y_source = NULL;
dma_args.uv_source = NULL;
dma_args.src.left = 0;
dma_args.src.top = 0;
dma_args.src.width = yi->v4l2_src_w;
dma_args.src.height = yi->v4l2_src_h;
dma_args.dst = yi->main_rect;
dma_args.src_width = yi->v4l2_src_w;
dma_args.src_height = yi->v4l2_src_h;
/* ... and use the same setup routine as ivtv_yuv_prep_frame */
ivtv_yuv_setup_frame(itv, &dma_args);
if (!itv->dma_data_req_offset)
itv->dma_data_req_offset = yuv_offset[yi->draw_frame];
}
/* Attempt to dma a frame from a user buffer */
int ivtv_yuv_udma_stream_frame(struct ivtv *itv, void __user *src)
{
struct yuv_playback_info *yi = &itv->yuv_info;
struct ivtv_dma_frame dma_args;
int res;
ivtv_yuv_setup_stream_frame(itv);
/* We only need to supply source addresses for this */
dma_args.y_source = src;
dma_args.uv_source = src + 720 * ((yi->v4l2_src_h + 31) & ~31);
/* Wait for frame DMA. Note that serialize_lock is locked,
so to allow other processes to access the driver while
we are waiting unlock first and later lock again. */
mutex_unlock(&itv->serialize_lock);
res = ivtv_yuv_udma_frame(itv, &dma_args);
mutex_lock(&itv->serialize_lock);
return res;
}
/* IVTV_IOC_DMA_FRAME ioctl handler */
int ivtv_yuv_prep_frame(struct ivtv *itv, struct ivtv_dma_frame *args)
{
int res;
/* IVTV_DEBUG_INFO("yuv_prep_frame\n"); */
ivtv_yuv_next_free(itv);
ivtv_yuv_setup_frame(itv, args);
/* Wait for frame DMA. Note that serialize_lock is locked,
so to allow other processes to access the driver while
we are waiting unlock first and later lock again. */
mutex_unlock(&itv->serialize_lock);
res = ivtv_yuv_udma_frame(itv, args);
mutex_lock(&itv->serialize_lock);
return res;
}
void ivtv_yuv_close(struct ivtv *itv)
{
struct yuv_playback_info *yi = &itv->yuv_info;
int h_filter, v_filter_1, v_filter_2;
IVTV_DEBUG_YUV("ivtv_yuv_close\n");
mutex_unlock(&itv->serialize_lock);
ivtv_waitq(&itv->vsync_waitq);
mutex_lock(&itv->serialize_lock);
yi->running = 0;
atomic_set(&yi->next_dma_frame, -1);
atomic_set(&yi->next_fill_frame, 0);
/* Reset registers we have changed so mpeg playback works */
/* If we fully restore this register, the display may remain active.
Restore, but set one bit to blank the video. Firmware will always
clear this bit when needed, so not a problem. */
write_reg(yi->reg_2898 | 0x01000000, 0x2898);
write_reg(yi->reg_2834, 0x02834);
write_reg(yi->reg_2838, 0x02838);
write_reg(yi->reg_283c, 0x0283c);
write_reg(yi->reg_2840, 0x02840);
write_reg(yi->reg_2844, 0x02844);
write_reg(yi->reg_2848, 0x02848);
write_reg(yi->reg_2854, 0x02854);
write_reg(yi->reg_285c, 0x0285c);
write_reg(yi->reg_2864, 0x02864);
write_reg(yi->reg_2870, 0x02870);
write_reg(yi->reg_2874, 0x02874);
write_reg(yi->reg_2890, 0x02890);
write_reg(yi->reg_289c, 0x0289c);
write_reg(yi->reg_2918, 0x02918);
write_reg(yi->reg_291c, 0x0291c);
write_reg(yi->reg_2920, 0x02920);
write_reg(yi->reg_2924, 0x02924);
write_reg(yi->reg_2928, 0x02928);
write_reg(yi->reg_292c, 0x0292c);
write_reg(yi->reg_2930, 0x02930);
write_reg(yi->reg_2934, 0x02934);
write_reg(yi->reg_2938, 0x02938);
write_reg(yi->reg_293c, 0x0293c);
write_reg(yi->reg_2940, 0x02940);
write_reg(yi->reg_2944, 0x02944);
write_reg(yi->reg_2948, 0x02948);
write_reg(yi->reg_294c, 0x0294c);
write_reg(yi->reg_2950, 0x02950);
write_reg(yi->reg_2954, 0x02954);
write_reg(yi->reg_2958, 0x02958);
write_reg(yi->reg_295c, 0x0295c);
write_reg(yi->reg_2960, 0x02960);
write_reg(yi->reg_2964, 0x02964);
write_reg(yi->reg_2968, 0x02968);
write_reg(yi->reg_296c, 0x0296c);
write_reg(yi->reg_2970, 0x02970);
/* Prepare to restore filters */
/* First the horizontal filter */
if ((yi->reg_2834 & 0x0000FFFF) == (yi->reg_2834 >> 16)) {
/* An exact size match uses filter 0 */
h_filter = 0;
} else {
/* Figure out which filter to use */
h_filter = ((yi->reg_2834 << 16) / (yi->reg_2834 >> 16)) >> 15;
h_filter = (h_filter >> 1) + (h_filter & 1);
/* Only an exact size match can use filter 0. */
h_filter += !h_filter;
}
/* Now the vertical filter */
if ((yi->reg_2918 & 0x0000FFFF) == (yi->reg_2918 >> 16)) {
/* An exact size match uses filter 0/1 */
v_filter_1 = 0;
v_filter_2 = 1;
} else {
/* Figure out which filter to use */
v_filter_1 = ((yi->reg_2918 << 16) / (yi->reg_2918 >> 16)) >> 15;
v_filter_1 = (v_filter_1 >> 1) + (v_filter_1 & 1);
/* Only an exact size match can use filter 0 */
v_filter_1 += !v_filter_1;
v_filter_2 = v_filter_1;
}
/* Now restore the filters */
ivtv_yuv_filter(itv, h_filter, v_filter_1, v_filter_2);
/* and clear a few registers */
write_reg(0, 0x02814);
write_reg(0, 0x0282c);
write_reg(0, 0x02904);
write_reg(0, 0x02910);
/* Release the blanking buffer */
if (yi->blanking_ptr) {
kfree(yi->blanking_ptr);
yi->blanking_ptr = NULL;
dma_unmap_single(&itv->pdev->dev, yi->blanking_dmaptr,
720 * 16, DMA_TO_DEVICE);
}
/* Invalidate the old dimension information */
yi->old_frame_info.src_w = 0;
yi->old_frame_info.src_h = 0;
yi->old_frame_info_args.src_w = 0;
yi->old_frame_info_args.src_h = 0;
/* All done. */
clear_bit(IVTV_F_I_DECODING_YUV, &itv->i_flags);
}
|
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Copyright (C) 2021 MediaTek Inc.
* Authors: Sam.Shih <[email protected]>
* Frank Wunderlich <[email protected]>
* Daniel Golle <[email protected]>
*/
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/leds/common.h>
#include <dt-bindings/pinctrl/mt65xx.h>
#include "mt7986a.dtsi"
/ {
model = "Bananapi BPI-R3";
chassis-type = "embedded";
compatible = "bananapi,bpi-r3", "mediatek,mt7986a";
aliases {
serial0 = &uart0;
ethernet0 = &gmac0;
ethernet1 = &gmac1;
};
chosen {
stdout-path = "serial0:115200n8";
};
dcin: regulator-12vd {
compatible = "regulator-fixed";
regulator-name = "12vd";
regulator-min-microvolt = <12000000>;
regulator-max-microvolt = <12000000>;
regulator-boot-on;
regulator-always-on;
};
fan: pwm-fan {
compatible = "pwm-fan";
#cooling-cells = <2>;
/* cooling level (0, 1, 2) - pwm inverted */
cooling-levels = <255 96 0>;
pwms = <&pwm 0 10000>;
status = "okay";
};
gpio-keys {
compatible = "gpio-keys";
reset-key {
label = "reset";
linux,code = <KEY_RESTART>;
gpios = <&pio 9 GPIO_ACTIVE_LOW>;
};
wps-key {
label = "wps";
linux,code = <KEY_WPS_BUTTON>;
gpios = <&pio 10 GPIO_ACTIVE_LOW>;
};
};
/* i2c of the left SFP cage (wan) */
i2c_sfp1: i2c-gpio-0 {
compatible = "i2c-gpio";
sda-gpios = <&pio 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
scl-gpios = <&pio 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
i2c-gpio,delay-us = <2>;
#address-cells = <1>;
#size-cells = <0>;
};
/* i2c of the right SFP cage (lan) */
i2c_sfp2: i2c-gpio-1 {
compatible = "i2c-gpio";
sda-gpios = <&pio 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
scl-gpios = <&pio 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
i2c-gpio,delay-us = <2>;
#address-cells = <1>;
#size-cells = <0>;
};
leds {
compatible = "gpio-leds";
green_led: led-0 {
color = <LED_COLOR_ID_GREEN>;
function = LED_FUNCTION_POWER;
gpios = <&pio 69 GPIO_ACTIVE_HIGH>;
default-state = "on";
};
blue_led: led-1 {
color = <LED_COLOR_ID_BLUE>;
function = LED_FUNCTION_STATUS;
gpios = <&pio 86 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
};
reg_1p8v: regulator-1p8v {
compatible = "regulator-fixed";
regulator-name = "1.8vd";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
vin-supply = <&dcin>;
};
reg_3p3v: regulator-3p3v {
compatible = "regulator-fixed";
regulator-name = "3.3vd";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
vin-supply = <&dcin>;
};
/* left SFP cage (wan) */
sfp1: sfp-1 {
compatible = "sff,sfp";
i2c-bus = <&i2c_sfp1>;
los-gpios = <&pio 46 GPIO_ACTIVE_HIGH>;
maximum-power-milliwatt = <3000>;
mod-def0-gpios = <&pio 49 GPIO_ACTIVE_LOW>;
tx-disable-gpios = <&pio 20 GPIO_ACTIVE_HIGH>;
tx-fault-gpios = <&pio 7 GPIO_ACTIVE_HIGH>;
};
/* right SFP cage (lan) */
sfp2: sfp-2 {
compatible = "sff,sfp";
i2c-bus = <&i2c_sfp2>;
los-gpios = <&pio 31 GPIO_ACTIVE_HIGH>;
mod-def0-gpios = <&pio 47 GPIO_ACTIVE_LOW>;
maximum-power-milliwatt = <3000>;
tx-disable-gpios = <&pio 15 GPIO_ACTIVE_HIGH>;
tx-fault-gpios = <&pio 48 GPIO_ACTIVE_HIGH>;
};
};
&cpu_thermal {
cooling-maps {
map-cpu-active-high {
/* active: set fan to cooling level 2 */
cooling-device = <&fan 2 2>;
trip = <&cpu_trip_active_high>;
};
map-cpu-active-med {
/* active: set fan to cooling level 1 */
cooling-device = <&fan 1 1>;
trip = <&cpu_trip_active_med>;
};
map-cpu-active-low {
/* active: set fan to cooling level 0 */
cooling-device = <&fan 0 0>;
trip = <&cpu_trip_active_low>;
};
};
};
&crypto {
status = "okay";
};
ð {
status = "okay";
gmac0: mac@0 {
compatible = "mediatek,eth-mac";
reg = <0>;
phy-mode = "2500base-x";
fixed-link {
speed = <2500>;
full-duplex;
pause;
};
};
gmac1: mac@1 {
compatible = "mediatek,eth-mac";
reg = <1>;
phy-mode = "2500base-x";
sfp = <&sfp1>;
managed = "in-band-status";
};
mdio: mdio-bus {
#address-cells = <1>;
#size-cells = <0>;
};
};
&mdio {
switch: switch@31 {
compatible = "mediatek,mt7531";
reg = <31>;
interrupt-controller;
#interrupt-cells = <1>;
interrupts-extended = <&pio 66 IRQ_TYPE_LEVEL_HIGH>;
reset-gpios = <&pio 5 GPIO_ACTIVE_HIGH>;
};
};
&mmc0 {
pinctrl-names = "default", "state_uhs";
pinctrl-0 = <&mmc0_pins_default>;
pinctrl-1 = <&mmc0_pins_uhs>;
vmmc-supply = <®_3p3v>;
vqmmc-supply = <®_1p8v>;
};
&i2c0 {
pinctrl-names = "default";
pinctrl-0 = <&i2c_pins>;
status = "okay";
};
&pcie {
pinctrl-names = "default";
pinctrl-0 = <&pcie_pins>;
status = "okay";
};
&pcie_phy {
status = "okay";
};
&pio {
i2c_pins: i2c-pins {
mux {
function = "i2c";
groups = "i2c";
};
};
mmc0_pins_default: mmc0-pins {
mux {
function = "emmc";
groups = "emmc_51";
};
conf-cmd-dat {
pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2",
"EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5",
"EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD";
input-enable;
drive-strength = <4>;
bias-pull-up = <MTK_PUPD_SET_R1R0_01>; /* pull-up 10K */
};
conf-clk {
pins = "EMMC_CK";
drive-strength = <6>;
bias-pull-down = <MTK_PUPD_SET_R1R0_10>; /* pull-down 50K */
};
conf-ds {
pins = "EMMC_DSL";
bias-pull-down = <MTK_PUPD_SET_R1R0_10>; /* pull-down 50K */
};
conf-rst {
pins = "EMMC_RSTB";
drive-strength = <4>;
bias-pull-up = <MTK_PUPD_SET_R1R0_01>; /* pull-up 10K */
};
};
mmc0_pins_uhs: mmc0-uhs-pins {
mux {
function = "emmc";
groups = "emmc_51";
};
conf-cmd-dat {
pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2",
"EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5",
"EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD";
input-enable;
drive-strength = <4>;
bias-pull-up = <MTK_PUPD_SET_R1R0_01>; /* pull-up 10K */
};
conf-clk {
pins = "EMMC_CK";
drive-strength = <6>;
bias-pull-down = <MTK_PUPD_SET_R1R0_10>; /* pull-down 50K */
};
conf-ds {
pins = "EMMC_DSL";
bias-pull-down = <MTK_PUPD_SET_R1R0_10>; /* pull-down 50K */
};
conf-rst {
pins = "EMMC_RSTB";
drive-strength = <4>;
bias-pull-up = <MTK_PUPD_SET_R1R0_01>; /* pull-up 10K */
};
};
pcie_pins: pcie-pins {
mux {
function = "pcie";
groups = "pcie_clk", "pcie_pereset";
};
};
pwm_pins: pwm-pins {
mux {
function = "pwm";
groups = "pwm0", "pwm1_0";
};
};
spi_flash_pins: spi-flash-pins {
mux {
function = "spi";
groups = "spi0", "spi0_wp_hold";
};
};
spic_pins: spic-pins {
mux {
function = "spi";
groups = "spi1_0";
};
};
uart1_pins: uart1-pins {
mux {
function = "uart";
groups = "uart1_rx_tx";
};
};
uart2_pins: uart2-pins {
mux {
function = "uart";
groups = "uart2_0_rx_tx";
};
};
wf_2g_5g_pins: wf-2g-5g-pins {
mux {
function = "wifi";
groups = "wf_2g", "wf_5g";
};
conf {
pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",
"WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",
"WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",
"WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1",
"WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0",
"WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8",
"WF1_TOP_CLK", "WF1_TOP_DATA";
drive-strength = <4>;
};
};
wf_dbdc_pins: wf-dbdc-pins {
mux {
function = "wifi";
groups = "wf_dbdc";
};
conf {
pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",
"WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",
"WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",
"WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1",
"WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0",
"WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8",
"WF1_TOP_CLK", "WF1_TOP_DATA";
drive-strength = <4>;
};
};
wf_led_pins: wf-led-pins {
mux {
function = "led";
groups = "wifi_led";
};
};
};
&pwm {
pinctrl-names = "default";
pinctrl-0 = <&pwm_pins>;
status = "okay";
};
&spi0 {
pinctrl-names = "default";
pinctrl-0 = <&spi_flash_pins>;
status = "okay";
};
&spi1 {
pinctrl-names = "default";
pinctrl-0 = <&spic_pins>;
status = "okay";
};
&ssusb {
status = "okay";
};
&switch {
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
label = "wan";
};
port@1 {
reg = <1>;
label = "lan0";
};
port@2 {
reg = <2>;
label = "lan1";
};
port@3 {
reg = <3>;
label = "lan2";
};
port@4 {
reg = <4>;
label = "lan3";
};
port5: port@5 {
reg = <5>;
label = "lan4";
phy-mode = "2500base-x";
sfp = <&sfp2>;
managed = "in-band-status";
};
port@6 {
reg = <6>;
label = "cpu";
ethernet = <&gmac0>;
phy-mode = "2500base-x";
fixed-link {
speed = <2500>;
full-duplex;
pause;
};
};
};
};
&trng {
status = "okay";
};
&uart0 {
status = "okay";
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&uart1_pins>;
status = "okay";
};
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&uart2_pins>;
status = "okay";
};
&usb_phy {
status = "okay";
};
&watchdog {
status = "okay";
};
&wifi {
status = "okay";
pinctrl-names = "default", "dbdc";
pinctrl-0 = <&wf_2g_5g_pins>, <&wf_led_pins>;
pinctrl-1 = <&wf_dbdc_pins>, <&wf_led_pins>;
led {
led-active-low;
};
};
|
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
/*
* Copyright (C) 2022 MediaTek Inc.
* Author: Hui Liu <[email protected]>
*/
#ifndef __MEDIATEK_MT8188_PINFUNC_H
#define __MEDIATEK_MT8188_PINFUNC_H
#include "mt65xx.h"
#define PINMUX_GPIO0__FUNC_B_GPIO0 (MTK_PIN_NO(0) | 0)
#define PINMUX_GPIO0__FUNC_B0_TP_GPIO0_AO (MTK_PIN_NO(0) | 1)
#define PINMUX_GPIO0__FUNC_O_SPIM5_CSB (MTK_PIN_NO(0) | 2)
#define PINMUX_GPIO0__FUNC_O_UTXD1 (MTK_PIN_NO(0) | 3)
#define PINMUX_GPIO0__FUNC_O_DMIC3_CLK (MTK_PIN_NO(0) | 4)
#define PINMUX_GPIO0__FUNC_B0_I2SIN_MCK (MTK_PIN_NO(0) | 5)
#define PINMUX_GPIO0__FUNC_O_I2SO2_MCK (MTK_PIN_NO(0) | 6)
#define PINMUX_GPIO0__FUNC_B0_DBG_MON_A0 (MTK_PIN_NO(0) | 7)
#define PINMUX_GPIO1__FUNC_B_GPIO1 (MTK_PIN_NO(1) | 0)
#define PINMUX_GPIO1__FUNC_B0_TP_GPIO1_AO (MTK_PIN_NO(1) | 1)
#define PINMUX_GPIO1__FUNC_O_SPIM5_CLK (MTK_PIN_NO(1) | 2)
#define PINMUX_GPIO1__FUNC_I1_URXD1 (MTK_PIN_NO(1) | 3)
#define PINMUX_GPIO1__FUNC_I0_DMIC3_DAT (MTK_PIN_NO(1) | 4)
#define PINMUX_GPIO1__FUNC_B0_I2SIN_BCK (MTK_PIN_NO(1) | 5)
#define PINMUX_GPIO1__FUNC_B0_I2SO2_BCK (MTK_PIN_NO(1) | 6)
#define PINMUX_GPIO1__FUNC_B0_DBG_MON_A1 (MTK_PIN_NO(1) | 7)
#define PINMUX_GPIO2__FUNC_B_GPIO2 (MTK_PIN_NO(2) | 0)
#define PINMUX_GPIO2__FUNC_B0_TP_GPIO2_AO (MTK_PIN_NO(2) | 1)
#define PINMUX_GPIO2__FUNC_B0_SPIM5_MOSI (MTK_PIN_NO(2) | 2)
#define PINMUX_GPIO2__FUNC_O_URTS1 (MTK_PIN_NO(2) | 3)
#define PINMUX_GPIO2__FUNC_I0_DMIC3_DAT_R (MTK_PIN_NO(2) | 4)
#define PINMUX_GPIO2__FUNC_B0_I2SIN_WS (MTK_PIN_NO(2) | 5)
#define PINMUX_GPIO2__FUNC_B0_I2SO2_WS (MTK_PIN_NO(2) | 6)
#define PINMUX_GPIO2__FUNC_B0_DBG_MON_A2 (MTK_PIN_NO(2) | 7)
#define PINMUX_GPIO3__FUNC_B_GPIO3 (MTK_PIN_NO(3) | 0)
#define PINMUX_GPIO3__FUNC_B0_TP_GPIO3_AO (MTK_PIN_NO(3) | 1)
#define PINMUX_GPIO3__FUNC_B0_SPIM5_MISO (MTK_PIN_NO(3) | 2)
#define PINMUX_GPIO3__FUNC_I1_UCTS1 (MTK_PIN_NO(3) | 3)
#define PINMUX_GPIO3__FUNC_O_DMIC4_CLK (MTK_PIN_NO(3) | 4)
#define PINMUX_GPIO3__FUNC_I0_I2SIN_D0 (MTK_PIN_NO(3) | 5)
#define PINMUX_GPIO3__FUNC_O_I2SO2_D0 (MTK_PIN_NO(3) | 6)
#define PINMUX_GPIO3__FUNC_B0_DBG_MON_A3 (MTK_PIN_NO(3) | 7)
#define PINMUX_GPIO4__FUNC_B_GPIO4 (MTK_PIN_NO(4) | 0)
#define PINMUX_GPIO4__FUNC_B0_TP_GPIO4_AO (MTK_PIN_NO(4) | 1)
#define PINMUX_GPIO4__FUNC_I0_SPDIF_IN2 (MTK_PIN_NO(4) | 2)
#define PINMUX_GPIO4__FUNC_O_I2SO1_MCK (MTK_PIN_NO(4) | 3)
#define PINMUX_GPIO4__FUNC_I0_DMIC4_DAT (MTK_PIN_NO(4) | 4)
#define PINMUX_GPIO4__FUNC_I0_I2SIN_D1 (MTK_PIN_NO(4) | 5)
#define PINMUX_GPIO4__FUNC_O_I2SO2_D1 (MTK_PIN_NO(4) | 6)
#define PINMUX_GPIO4__FUNC_B0_DBG_MON_A4 (MTK_PIN_NO(4) | 7)
#define PINMUX_GPIO5__FUNC_B_GPIO5 (MTK_PIN_NO(5) | 0)
#define PINMUX_GPIO5__FUNC_B0_TP_GPIO5_AO (MTK_PIN_NO(5) | 1)
#define PINMUX_GPIO5__FUNC_I0_SPDIF_IN1 (MTK_PIN_NO(5) | 2)
#define PINMUX_GPIO5__FUNC_O_I2SO1_BCK (MTK_PIN_NO(5) | 3)
#define PINMUX_GPIO5__FUNC_I0_DMIC4_DAT_R (MTK_PIN_NO(5) | 4)
#define PINMUX_GPIO5__FUNC_I0_I2SIN_D2 (MTK_PIN_NO(5) | 5)
#define PINMUX_GPIO5__FUNC_O_I2SO2_D2 (MTK_PIN_NO(5) | 6)
#define PINMUX_GPIO5__FUNC_B0_DBG_MON_A5 (MTK_PIN_NO(5) | 7)
#define PINMUX_GPIO6__FUNC_B_GPIO6 (MTK_PIN_NO(6) | 0)
#define PINMUX_GPIO6__FUNC_B0_TP_GPIO6_AO (MTK_PIN_NO(6) | 1)
#define PINMUX_GPIO6__FUNC_I0_SPDIF_IN0 (MTK_PIN_NO(6) | 2)
#define PINMUX_GPIO6__FUNC_O_I2SO1_WS (MTK_PIN_NO(6) | 3)
#define PINMUX_GPIO6__FUNC_O_DMIC1_CLK (MTK_PIN_NO(6) | 4)
#define PINMUX_GPIO6__FUNC_I0_I2SIN_D3 (MTK_PIN_NO(6) | 5)
#define PINMUX_GPIO6__FUNC_O_I2SO2_D3 (MTK_PIN_NO(6) | 6)
#define PINMUX_GPIO6__FUNC_B0_MD32_0_GPIO0 (MTK_PIN_NO(6) | 7)
#define PINMUX_GPIO7__FUNC_B_GPIO7 (MTK_PIN_NO(7) | 0)
#define PINMUX_GPIO7__FUNC_B0_TP_GPIO7_AO (MTK_PIN_NO(7) | 1)
#define PINMUX_GPIO7__FUNC_O_SPIM3_CSB (MTK_PIN_NO(7) | 2)
#define PINMUX_GPIO7__FUNC_B0_TDMIN_MCK (MTK_PIN_NO(7) | 3)
#define PINMUX_GPIO7__FUNC_I0_DMIC1_DAT (MTK_PIN_NO(7) | 4)
#define PINMUX_GPIO7__FUNC_O_CMVREF0 (MTK_PIN_NO(7) | 5)
#define PINMUX_GPIO7__FUNC_O_CLKM0 (MTK_PIN_NO(7) | 6)
#define PINMUX_GPIO7__FUNC_B0_DBG_MON_A6 (MTK_PIN_NO(7) | 7)
#define PINMUX_GPIO8__FUNC_B_GPIO8 (MTK_PIN_NO(8) | 0)
#define PINMUX_GPIO8__FUNC_B0_TP_GPIO0_AO (MTK_PIN_NO(8) | 1)
#define PINMUX_GPIO8__FUNC_O_SPIM3_CLK (MTK_PIN_NO(8) | 2)
#define PINMUX_GPIO8__FUNC_B0_TDMIN_BCK (MTK_PIN_NO(8) | 3)
#define PINMUX_GPIO8__FUNC_I0_DMIC1_DAT_R (MTK_PIN_NO(8) | 4)
#define PINMUX_GPIO8__FUNC_O_CMVREF1 (MTK_PIN_NO(8) | 5)
#define PINMUX_GPIO8__FUNC_O_CLKM1 (MTK_PIN_NO(8) | 6)
#define PINMUX_GPIO8__FUNC_B0_DBG_MON_A7 (MTK_PIN_NO(8) | 7)
#define PINMUX_GPIO9__FUNC_B_GPIO9 (MTK_PIN_NO(9) | 0)
#define PINMUX_GPIO9__FUNC_B0_TP_GPIO1_AO (MTK_PIN_NO(9) | 1)
#define PINMUX_GPIO9__FUNC_B0_SPIM3_MOSI (MTK_PIN_NO(9) | 2)
#define PINMUX_GPIO9__FUNC_B0_TDMIN_LRCK (MTK_PIN_NO(9) | 3)
#define PINMUX_GPIO9__FUNC_O_DMIC2_CLK (MTK_PIN_NO(9) | 4)
#define PINMUX_GPIO9__FUNC_O_CMFLASH0 (MTK_PIN_NO(9) | 5)
#define PINMUX_GPIO9__FUNC_O_PWM_0 (MTK_PIN_NO(9) | 6)
#define PINMUX_GPIO9__FUNC_B0_DBG_MON_A8 (MTK_PIN_NO(9) | 7)
#define PINMUX_GPIO10__FUNC_B_GPIO10 (MTK_PIN_NO(10) | 0)
#define PINMUX_GPIO10__FUNC_B0_TP_GPIO2_AO (MTK_PIN_NO(10) | 1)
#define PINMUX_GPIO10__FUNC_B0_SPIM3_MISO (MTK_PIN_NO(10) | 2)
#define PINMUX_GPIO10__FUNC_I0_TDMIN_DI (MTK_PIN_NO(10) | 3)
#define PINMUX_GPIO10__FUNC_I0_DMIC2_DAT (MTK_PIN_NO(10) | 4)
#define PINMUX_GPIO10__FUNC_O_CMFLASH1 (MTK_PIN_NO(10) | 5)
#define PINMUX_GPIO10__FUNC_O_PWM_1 (MTK_PIN_NO(10) | 6)
#define PINMUX_GPIO10__FUNC_B0_DBG_MON_A9 (MTK_PIN_NO(10) | 7)
#define PINMUX_GPIO11__FUNC_B_GPIO11 (MTK_PIN_NO(11) | 0)
#define PINMUX_GPIO11__FUNC_B0_TP_GPIO3_AO (MTK_PIN_NO(11) | 1)
#define PINMUX_GPIO11__FUNC_O_SPDIF_OUT (MTK_PIN_NO(11) | 2)
#define PINMUX_GPIO11__FUNC_O_I2SO1_D0 (MTK_PIN_NO(11) | 3)
#define PINMUX_GPIO11__FUNC_I0_DMIC2_DAT_R (MTK_PIN_NO(11) | 4)
#define PINMUX_GPIO11__FUNC_I0_DVFSRC_EXT_REQ (MTK_PIN_NO(11) | 5)
#define PINMUX_GPIO11__FUNC_O_CMVREF6 (MTK_PIN_NO(11) | 6)
#define PINMUX_GPIO11__FUNC_B0_DBG_MON_A10 (MTK_PIN_NO(11) | 7)
#define PINMUX_GPIO12__FUNC_B_GPIO12 (MTK_PIN_NO(12) | 0)
#define PINMUX_GPIO12__FUNC_B0_TP_GPIO4_AO (MTK_PIN_NO(12) | 1)
#define PINMUX_GPIO12__FUNC_O_SPIM4_CSB (MTK_PIN_NO(12) | 2)
#define PINMUX_GPIO12__FUNC_B1_JTMS_SEL3 (MTK_PIN_NO(12) | 3)
#define PINMUX_GPIO12__FUNC_B1_APU_JTAG_TMS (MTK_PIN_NO(12) | 4)
#define PINMUX_GPIO12__FUNC_I0_VPU_UDI_TMS (MTK_PIN_NO(12) | 5)
#define PINMUX_GPIO12__FUNC_I0_IPU_JTAG_TMS (MTK_PIN_NO(12) | 6)
#define PINMUX_GPIO12__FUNC_I0_HDMITX20_HTPLG (MTK_PIN_NO(12) | 7)
#define PINMUX_GPIO13__FUNC_B_GPIO13 (MTK_PIN_NO(13) | 0)
#define PINMUX_GPIO13__FUNC_B0_TP_GPIO5_AO (MTK_PIN_NO(13) | 1)
#define PINMUX_GPIO13__FUNC_O_SPIM4_CLK (MTK_PIN_NO(13) | 2)
#define PINMUX_GPIO13__FUNC_I0_JTCK_SEL3 (MTK_PIN_NO(13) | 3)
#define PINMUX_GPIO13__FUNC_I0_APU_JTAG_TCK (MTK_PIN_NO(13) | 4)
#define PINMUX_GPIO13__FUNC_I0_VPU_UDI_TCK (MTK_PIN_NO(13) | 5)
#define PINMUX_GPIO13__FUNC_I0_IPU_JTAG_TCK (MTK_PIN_NO(13) | 6)
#define PINMUX_GPIO13__FUNC_B1_HDMITX20_CEC (MTK_PIN_NO(13) | 7)
#define PINMUX_GPIO14__FUNC_B_GPIO14 (MTK_PIN_NO(14) | 0)
#define PINMUX_GPIO14__FUNC_B0_TP_GPIO6_AO (MTK_PIN_NO(14) | 1)
#define PINMUX_GPIO14__FUNC_B0_SPIM4_MOSI (MTK_PIN_NO(14) | 2)
#define PINMUX_GPIO14__FUNC_I1_JTDI_SEL3 (MTK_PIN_NO(14) | 3)
#define PINMUX_GPIO14__FUNC_I1_APU_JTAG_TDI (MTK_PIN_NO(14) | 4)
#define PINMUX_GPIO14__FUNC_I0_VPU_UDI_TDI (MTK_PIN_NO(14) | 5)
#define PINMUX_GPIO14__FUNC_I0_IPU_JTAG_TDI (MTK_PIN_NO(14) | 6)
#define PINMUX_GPIO14__FUNC_B1_HDMITX20_SCL (MTK_PIN_NO(14) | 7)
#define PINMUX_GPIO15__FUNC_B_GPIO15 (MTK_PIN_NO(15) | 0)
#define PINMUX_GPIO15__FUNC_B0_TP_GPIO7_AO (MTK_PIN_NO(15) | 1)
#define PINMUX_GPIO15__FUNC_B0_SPIM4_MISO (MTK_PIN_NO(15) | 2)
#define PINMUX_GPIO15__FUNC_O_JTDO_SEL3 (MTK_PIN_NO(15) | 3)
#define PINMUX_GPIO15__FUNC_O_APU_JTAG_TDO (MTK_PIN_NO(15) | 4)
#define PINMUX_GPIO15__FUNC_O_VPU_UDI_TDO (MTK_PIN_NO(15) | 5)
#define PINMUX_GPIO15__FUNC_O_IPU_JTAG_TDO (MTK_PIN_NO(15) | 6)
#define PINMUX_GPIO15__FUNC_B1_HDMITX20_SDA (MTK_PIN_NO(15) | 7)
#define PINMUX_GPIO16__FUNC_B_GPIO16 (MTK_PIN_NO(16) | 0)
#define PINMUX_GPIO16__FUNC_B0_TP_GPIO0_AO (MTK_PIN_NO(16) | 1)
#define PINMUX_GPIO16__FUNC_O_UTXD3 (MTK_PIN_NO(16) | 2)
#define PINMUX_GPIO16__FUNC_I1_JTRSTn_SEL3 (MTK_PIN_NO(16) | 3)
#define PINMUX_GPIO16__FUNC_I0_APU_JTAG_TRST (MTK_PIN_NO(16) | 4)
#define PINMUX_GPIO16__FUNC_I0_VPU_UDI_NTRST (MTK_PIN_NO(16) | 5)
#define PINMUX_GPIO16__FUNC_I0_IPU_JTAG_TRST (MTK_PIN_NO(16) | 6)
#define PINMUX_GPIO16__FUNC_O_HDMITX20_PWR5V (MTK_PIN_NO(16) | 7)
#define PINMUX_GPIO17__FUNC_B_GPIO17 (MTK_PIN_NO(17) | 0)
#define PINMUX_GPIO17__FUNC_B0_TP_GPIO1_AO (MTK_PIN_NO(17) | 1)
#define PINMUX_GPIO17__FUNC_I1_URXD3 (MTK_PIN_NO(17) | 2)
#define PINMUX_GPIO17__FUNC_O_CMFLASH2 (MTK_PIN_NO(17) | 3)
#define PINMUX_GPIO17__FUNC_I0_EDP_TX_HPD (MTK_PIN_NO(17) | 4)
#define PINMUX_GPIO17__FUNC_I0_DVFSRC_EXT_REQ (MTK_PIN_NO(17) | 5)
#define PINMUX_GPIO17__FUNC_O_CMVREF7 (MTK_PIN_NO(17) | 6)
#define PINMUX_GPIO17__FUNC_B0_MD32_0_GPIO1 (MTK_PIN_NO(17) | 7)
#define PINMUX_GPIO18__FUNC_B_GPIO18 (MTK_PIN_NO(18) | 0)
#define PINMUX_GPIO18__FUNC_B0_TP_GPIO2_AO (MTK_PIN_NO(18) | 1)
#define PINMUX_GPIO18__FUNC_O_CMFLASH0 (MTK_PIN_NO(18) | 2)
#define PINMUX_GPIO18__FUNC_O_CMVREF4 (MTK_PIN_NO(18) | 3)
#define PINMUX_GPIO18__FUNC_B0_TDMIN_MCK (MTK_PIN_NO(18) | 4)
#define PINMUX_GPIO18__FUNC_O_UTXD1 (MTK_PIN_NO(18) | 5)
#define PINMUX_GPIO18__FUNC_O_TP_UTXD1_AO (MTK_PIN_NO(18) | 6)
#define PINMUX_GPIO18__FUNC_B0_DBG_MON_A11 (MTK_PIN_NO(18) | 7)
#define PINMUX_GPIO19__FUNC_B_GPIO19 (MTK_PIN_NO(19) | 0)
#define PINMUX_GPIO19__FUNC_B0_TP_GPIO3_AO (MTK_PIN_NO(19) | 1)
#define PINMUX_GPIO19__FUNC_O_CMFLASH1 (MTK_PIN_NO(19) | 2)
#define PINMUX_GPIO19__FUNC_O_CMVREF5 (MTK_PIN_NO(19) | 3)
#define PINMUX_GPIO19__FUNC_B0_TDMIN_BCK (MTK_PIN_NO(19) | 4)
#define PINMUX_GPIO19__FUNC_I1_URXD1 (MTK_PIN_NO(19) | 5)
#define PINMUX_GPIO19__FUNC_I1_TP_URXD1_AO (MTK_PIN_NO(19) | 6)
#define PINMUX_GPIO19__FUNC_B0_DBG_MON_A12 (MTK_PIN_NO(19) | 7)
#define PINMUX_GPIO20__FUNC_B_GPIO20 (MTK_PIN_NO(20) | 0)
#define PINMUX_GPIO20__FUNC_B0_TP_GPIO4_AO (MTK_PIN_NO(20) | 1)
#define PINMUX_GPIO20__FUNC_O_CMFLASH2 (MTK_PIN_NO(20) | 2)
#define PINMUX_GPIO20__FUNC_O_CLKM2 (MTK_PIN_NO(20) | 3)
#define PINMUX_GPIO20__FUNC_B0_TDMIN_LRCK (MTK_PIN_NO(20) | 4)
#define PINMUX_GPIO20__FUNC_O_URTS1 (MTK_PIN_NO(20) | 5)
#define PINMUX_GPIO20__FUNC_O_TP_URTS1_AO (MTK_PIN_NO(20) | 6)
#define PINMUX_GPIO20__FUNC_B0_DBG_MON_A13 (MTK_PIN_NO(20) | 7)
#define PINMUX_GPIO21__FUNC_B_GPIO21 (MTK_PIN_NO(21) | 0)
#define PINMUX_GPIO21__FUNC_B0_TP_GPIO5_AO (MTK_PIN_NO(21) | 1)
#define PINMUX_GPIO21__FUNC_O_CMFLASH3 (MTK_PIN_NO(21) | 2)
#define PINMUX_GPIO21__FUNC_O_CLKM3 (MTK_PIN_NO(21) | 3)
#define PINMUX_GPIO21__FUNC_I0_TDMIN_DI (MTK_PIN_NO(21) | 4)
#define PINMUX_GPIO21__FUNC_I1_UCTS1 (MTK_PIN_NO(21) | 5)
#define PINMUX_GPIO21__FUNC_I1_TP_UCTS1_AO (MTK_PIN_NO(21) | 6)
#define PINMUX_GPIO21__FUNC_B0_DBG_MON_A14 (MTK_PIN_NO(21) | 7)
#define PINMUX_GPIO22__FUNC_B_GPIO22 (MTK_PIN_NO(22) | 0)
#define PINMUX_GPIO22__FUNC_O_CMMCLK0 (MTK_PIN_NO(22) | 1)
#define PINMUX_GPIO22__FUNC_B0_TP_GPIO6_AO (MTK_PIN_NO(22) | 5)
#define PINMUX_GPIO22__FUNC_B0_DBG_MON_A15 (MTK_PIN_NO(22) | 7)
#define PINMUX_GPIO23__FUNC_B_GPIO23 (MTK_PIN_NO(23) | 0)
#define PINMUX_GPIO23__FUNC_O_CMMCLK1 (MTK_PIN_NO(23) | 1)
#define PINMUX_GPIO23__FUNC_O_PWM_2 (MTK_PIN_NO(23) | 3)
#define PINMUX_GPIO23__FUNC_B1_PCIE_PHY_I2C_SCL (MTK_PIN_NO(23) | 4)
#define PINMUX_GPIO23__FUNC_B0_TP_GPIO7_AO (MTK_PIN_NO(23) | 5)
#define PINMUX_GPIO23__FUNC_I0_DP_TX_HPD (MTK_PIN_NO(23) | 6)
#define PINMUX_GPIO23__FUNC_B0_DBG_MON_A16 (MTK_PIN_NO(23) | 7)
#define PINMUX_GPIO24__FUNC_B_GPIO24 (MTK_PIN_NO(24) | 0)
#define PINMUX_GPIO24__FUNC_O_CMMCLK2 (MTK_PIN_NO(24) | 1)
#define PINMUX_GPIO24__FUNC_O_PWM_3 (MTK_PIN_NO(24) | 3)
#define PINMUX_GPIO24__FUNC_B1_PCIE_PHY_I2C_SDA (MTK_PIN_NO(24) | 4)
#define PINMUX_GPIO24__FUNC_I0_DVFSRC_EXT_REQ (MTK_PIN_NO(24) | 5)
#define PINMUX_GPIO24__FUNC_I0_EDP_TX_HPD (MTK_PIN_NO(24) | 6)
#define PINMUX_GPIO24__FUNC_B0_MD32_0_GPIO2 (MTK_PIN_NO(24) | 7)
#define PINMUX_GPIO25__FUNC_B_GPIO25 (MTK_PIN_NO(25) | 0)
#define PINMUX_GPIO25__FUNC_O_LCM_RST (MTK_PIN_NO(25) | 1)
#define PINMUX_GPIO25__FUNC_O_LCM1_RST (MTK_PIN_NO(25) | 2)
#define PINMUX_GPIO25__FUNC_I0_DP_TX_HPD (MTK_PIN_NO(25) | 3)
#define PINMUX_GPIO26__FUNC_B_GPIO26 (MTK_PIN_NO(26) | 0)
#define PINMUX_GPIO26__FUNC_I0_DSI_TE (MTK_PIN_NO(26) | 1)
#define PINMUX_GPIO26__FUNC_I0_DSI1_TE (MTK_PIN_NO(26) | 2)
#define PINMUX_GPIO26__FUNC_I0_EDP_TX_HPD (MTK_PIN_NO(26) | 3)
#define PINMUX_GPIO27__FUNC_B_GPIO27 (MTK_PIN_NO(27) | 0)
#define PINMUX_GPIO27__FUNC_O_LCM1_RST (MTK_PIN_NO(27) | 1)
#define PINMUX_GPIO27__FUNC_O_LCM_RST (MTK_PIN_NO(27) | 2)
#define PINMUX_GPIO27__FUNC_I0_DP_TX_HPD (MTK_PIN_NO(27) | 3)
#define PINMUX_GPIO27__FUNC_O_CMVREF2 (MTK_PIN_NO(27) | 4)
#define PINMUX_GPIO27__FUNC_O_mbistwriteen_trigger (MTK_PIN_NO(27) | 5)
#define PINMUX_GPIO27__FUNC_O_PWM_2 (MTK_PIN_NO(27) | 6)
#define PINMUX_GPIO27__FUNC_B0_DBG_MON_A17 (MTK_PIN_NO(27) | 7)
#define PINMUX_GPIO28__FUNC_B_GPIO28 (MTK_PIN_NO(28) | 0)
#define PINMUX_GPIO28__FUNC_I0_DSI1_TE (MTK_PIN_NO(28) | 1)
#define PINMUX_GPIO28__FUNC_I0_DSI_TE (MTK_PIN_NO(28) | 2)
#define PINMUX_GPIO28__FUNC_I0_EDP_TX_HPD (MTK_PIN_NO(28) | 3)
#define PINMUX_GPIO28__FUNC_O_CMVREF3 (MTK_PIN_NO(28) | 4)
#define PINMUX_GPIO28__FUNC_O_mbistreaden_trigger (MTK_PIN_NO(28) | 5)
#define PINMUX_GPIO28__FUNC_O_PWM_3 (MTK_PIN_NO(28) | 6)
#define PINMUX_GPIO28__FUNC_B0_DBG_MON_A18 (MTK_PIN_NO(28) | 7)
#define PINMUX_GPIO29__FUNC_B_GPIO29 (MTK_PIN_NO(29) | 0)
#define PINMUX_GPIO29__FUNC_O_DISP_PWM0 (MTK_PIN_NO(29) | 1)
#define PINMUX_GPIO29__FUNC_O_DISP_PWM1 (MTK_PIN_NO(29) | 2)
#define PINMUX_GPIO30__FUNC_B_GPIO30 (MTK_PIN_NO(30) | 0)
#define PINMUX_GPIO30__FUNC_O_DISP_PWM1 (MTK_PIN_NO(30) | 1)
#define PINMUX_GPIO30__FUNC_O_DISP_PWM0 (MTK_PIN_NO(30) | 2)
#define PINMUX_GPIO30__FUNC_O_CMFLASH3 (MTK_PIN_NO(30) | 3)
#define PINMUX_GPIO30__FUNC_O_PWM_1 (MTK_PIN_NO(30) | 4)
#define PINMUX_GPIO30__FUNC_B0_DBG_MON_A19 (MTK_PIN_NO(30) | 7)
#define PINMUX_GPIO31__FUNC_B_GPIO31 (MTK_PIN_NO(31) | 0)
#define PINMUX_GPIO31__FUNC_O_UTXD0 (MTK_PIN_NO(31) | 1)
#define PINMUX_GPIO31__FUNC_O_TP_UTXD1_AO (MTK_PIN_NO(31) | 2)
#define PINMUX_GPIO31__FUNC_O_ADSP_UTXD0 (MTK_PIN_NO(31) | 3)
#define PINMUX_GPIO31__FUNC_O_TP_UTXD2_AO (MTK_PIN_NO(31) | 4)
#define PINMUX_GPIO31__FUNC_O_MD32_0_TXD (MTK_PIN_NO(31) | 5)
#define PINMUX_GPIO31__FUNC_O_MD32_1_TXD (MTK_PIN_NO(31) | 6)
#define PINMUX_GPIO31__FUNC_O_SSPM_UTXD_AO (MTK_PIN_NO(31) | 7)
#define PINMUX_GPIO32__FUNC_B_GPIO32 (MTK_PIN_NO(32) | 0)
#define PINMUX_GPIO32__FUNC_I1_URXD0 (MTK_PIN_NO(32) | 1)
#define PINMUX_GPIO32__FUNC_I1_TP_URXD1_AO (MTK_PIN_NO(32) | 2)
#define PINMUX_GPIO32__FUNC_I1_ADSP_URXD0 (MTK_PIN_NO(32) | 3)
#define PINMUX_GPIO32__FUNC_I1_TP_URXD2_AO (MTK_PIN_NO(32) | 4)
#define PINMUX_GPIO32__FUNC_I1_MD32_0_RXD (MTK_PIN_NO(32) | 5)
#define PINMUX_GPIO32__FUNC_I1_MD32_1_RXD (MTK_PIN_NO(32) | 6)
#define PINMUX_GPIO32__FUNC_I1_SSPM_URXD_AO (MTK_PIN_NO(32) | 7)
#define PINMUX_GPIO33__FUNC_B_GPIO33 (MTK_PIN_NO(33) | 0)
#define PINMUX_GPIO33__FUNC_O_UTXD1 (MTK_PIN_NO(33) | 1)
#define PINMUX_GPIO33__FUNC_O_URTS2 (MTK_PIN_NO(33) | 2)
#define PINMUX_GPIO33__FUNC_O_ADSP_UTXD0 (MTK_PIN_NO(33) | 3)
#define PINMUX_GPIO33__FUNC_O_TP_UTXD1_AO (MTK_PIN_NO(33) | 4)
#define PINMUX_GPIO33__FUNC_O_mbistwriteen_trigger (MTK_PIN_NO(33) | 5)
#define PINMUX_GPIO33__FUNC_O_MD32_0_TXD (MTK_PIN_NO(33) | 6)
#define PINMUX_GPIO33__FUNC_O_SSPM_UTXD_AO (MTK_PIN_NO(33) | 7)
#define PINMUX_GPIO34__FUNC_B_GPIO34 (MTK_PIN_NO(34) | 0)
#define PINMUX_GPIO34__FUNC_I1_URXD1 (MTK_PIN_NO(34) | 1)
#define PINMUX_GPIO34__FUNC_I1_UCTS2 (MTK_PIN_NO(34) | 2)
#define PINMUX_GPIO34__FUNC_I1_ADSP_URXD0 (MTK_PIN_NO(34) | 3)
#define PINMUX_GPIO34__FUNC_I1_TP_URXD1_AO (MTK_PIN_NO(34) | 4)
#define PINMUX_GPIO34__FUNC_O_mbistreaden_trigger (MTK_PIN_NO(34) | 5)
#define PINMUX_GPIO34__FUNC_I1_MD32_0_RXD (MTK_PIN_NO(34) | 6)
#define PINMUX_GPIO34__FUNC_I1_SSPM_URXD_AO (MTK_PIN_NO(34) | 7)
#define PINMUX_GPIO35__FUNC_B_GPIO35 (MTK_PIN_NO(35) | 0)
#define PINMUX_GPIO35__FUNC_O_UTXD2 (MTK_PIN_NO(35) | 1)
#define PINMUX_GPIO35__FUNC_O_URTS1 (MTK_PIN_NO(35) | 2)
#define PINMUX_GPIO35__FUNC_O_ADSP_UTXD0 (MTK_PIN_NO(35) | 3)
#define PINMUX_GPIO35__FUNC_O_TP_URTS1_AO (MTK_PIN_NO(35) | 4)
#define PINMUX_GPIO35__FUNC_O_TP_UTXD2_AO (MTK_PIN_NO(35) | 5)
#define PINMUX_GPIO35__FUNC_O_MD32_1_TXD (MTK_PIN_NO(35) | 6)
#define PINMUX_GPIO35__FUNC_B0_DBG_MON_A20 (MTK_PIN_NO(35) | 7)
#define PINMUX_GPIO36__FUNC_B_GPIO36 (MTK_PIN_NO(36) | 0)
#define PINMUX_GPIO36__FUNC_I1_URXD2 (MTK_PIN_NO(36) | 1)
#define PINMUX_GPIO36__FUNC_I1_UCTS1 (MTK_PIN_NO(36) | 2)
#define PINMUX_GPIO36__FUNC_I1_ADSP_URXD0 (MTK_PIN_NO(36) | 3)
#define PINMUX_GPIO36__FUNC_I1_TP_UCTS1_AO (MTK_PIN_NO(36) | 4)
#define PINMUX_GPIO36__FUNC_I1_TP_URXD2_AO (MTK_PIN_NO(36) | 5)
#define PINMUX_GPIO36__FUNC_I1_MD32_1_RXD (MTK_PIN_NO(36) | 6)
#define PINMUX_GPIO36__FUNC_B0_DBG_MON_A21 (MTK_PIN_NO(36) | 7)
#define PINMUX_GPIO37__FUNC_B_GPIO37 (MTK_PIN_NO(37) | 0)
#define PINMUX_GPIO37__FUNC_B1_JTMS_SEL1 (MTK_PIN_NO(37) | 1)
#define PINMUX_GPIO37__FUNC_I0_UDI_TMS (MTK_PIN_NO(37) | 2)
#define PINMUX_GPIO37__FUNC_I1_SPM_JTAG_TMS (MTK_PIN_NO(37) | 3)
#define PINMUX_GPIO37__FUNC_I1_ADSP_JTAG0_TMS (MTK_PIN_NO(37) | 4)
#define PINMUX_GPIO37__FUNC_I1_SCP_JTAG0_TMS (MTK_PIN_NO(37) | 5)
#define PINMUX_GPIO37__FUNC_I1_CCU0_JTAG_TMS (MTK_PIN_NO(37) | 6)
#define PINMUX_GPIO37__FUNC_I1_MCUPM_JTAG_TMS (MTK_PIN_NO(37) | 7)
#define PINMUX_GPIO38__FUNC_B_GPIO38 (MTK_PIN_NO(38) | 0)
#define PINMUX_GPIO38__FUNC_I0_JTCK_SEL1 (MTK_PIN_NO(38) | 1)
#define PINMUX_GPIO38__FUNC_I0_UDI_TCK (MTK_PIN_NO(38) | 2)
#define PINMUX_GPIO38__FUNC_I1_SPM_JTAG_TCK (MTK_PIN_NO(38) | 3)
#define PINMUX_GPIO38__FUNC_I0_ADSP_JTAG0_TCK (MTK_PIN_NO(38) | 4)
#define PINMUX_GPIO38__FUNC_I1_SCP_JTAG0_TCK (MTK_PIN_NO(38) | 5)
#define PINMUX_GPIO38__FUNC_I1_CCU0_JTAG_TCK (MTK_PIN_NO(38) | 6)
#define PINMUX_GPIO38__FUNC_I1_MCUPM_JTAG_TCK (MTK_PIN_NO(38) | 7)
#define PINMUX_GPIO39__FUNC_B_GPIO39 (MTK_PIN_NO(39) | 0)
#define PINMUX_GPIO39__FUNC_I1_JTDI_SEL1 (MTK_PIN_NO(39) | 1)
#define PINMUX_GPIO39__FUNC_I0_UDI_TDI (MTK_PIN_NO(39) | 2)
#define PINMUX_GPIO39__FUNC_I1_SPM_JTAG_TDI (MTK_PIN_NO(39) | 3)
#define PINMUX_GPIO39__FUNC_I1_ADSP_JTAG0_TDI (MTK_PIN_NO(39) | 4)
#define PINMUX_GPIO39__FUNC_I1_SCP_JTAG0_TDI (MTK_PIN_NO(39) | 5)
#define PINMUX_GPIO39__FUNC_I1_CCU0_JTAG_TDI (MTK_PIN_NO(39) | 6)
#define PINMUX_GPIO39__FUNC_I1_MCUPM_JTAG_TDI (MTK_PIN_NO(39) | 7)
#define PINMUX_GPIO40__FUNC_B_GPIO40 (MTK_PIN_NO(40) | 0)
#define PINMUX_GPIO40__FUNC_O_JTDO_SEL1 (MTK_PIN_NO(40) | 1)
#define PINMUX_GPIO40__FUNC_O_UDI_TDO (MTK_PIN_NO(40) | 2)
#define PINMUX_GPIO40__FUNC_O_SPM_JTAG_TDO (MTK_PIN_NO(40) | 3)
#define PINMUX_GPIO40__FUNC_O_ADSP_JTAG0_TDO (MTK_PIN_NO(40) | 4)
#define PINMUX_GPIO40__FUNC_O_SCP_JTAG0_TDO (MTK_PIN_NO(40) | 5)
#define PINMUX_GPIO40__FUNC_O_CCU0_JTAG_TDO (MTK_PIN_NO(40) | 6)
#define PINMUX_GPIO40__FUNC_O_MCUPM_JTAG_TDO (MTK_PIN_NO(40) | 7)
#define PINMUX_GPIO41__FUNC_B_GPIO41 (MTK_PIN_NO(41) | 0)
#define PINMUX_GPIO41__FUNC_I1_JTRSTn_SEL1 (MTK_PIN_NO(41) | 1)
#define PINMUX_GPIO41__FUNC_I0_UDI_NTRST (MTK_PIN_NO(41) | 2)
#define PINMUX_GPIO41__FUNC_I0_SPM_JTAG_TRSTN (MTK_PIN_NO(41) | 3)
#define PINMUX_GPIO41__FUNC_I1_ADSP_JTAG0_TRSTN (MTK_PIN_NO(41) | 4)
#define PINMUX_GPIO41__FUNC_I0_SCP_JTAG0_TRSTN (MTK_PIN_NO(41) | 5)
#define PINMUX_GPIO41__FUNC_I1_CCU0_JTAG_TRST (MTK_PIN_NO(41) | 6)
#define PINMUX_GPIO41__FUNC_I0_MCUPM_JTAG_TRSTN (MTK_PIN_NO(41) | 7)
#define PINMUX_GPIO42__FUNC_B_GPIO42 (MTK_PIN_NO(42) | 0)
#define PINMUX_GPIO42__FUNC_B1_KPCOL0 (MTK_PIN_NO(42) | 1)
#define PINMUX_GPIO43__FUNC_B_GPIO43 (MTK_PIN_NO(43) | 0)
#define PINMUX_GPIO43__FUNC_B1_KPCOL1 (MTK_PIN_NO(43) | 1)
#define PINMUX_GPIO43__FUNC_I0_DP_TX_HPD (MTK_PIN_NO(43) | 2)
#define PINMUX_GPIO43__FUNC_O_CMFLASH2 (MTK_PIN_NO(43) | 3)
#define PINMUX_GPIO43__FUNC_I0_DVFSRC_EXT_REQ (MTK_PIN_NO(43) | 4)
#define PINMUX_GPIO43__FUNC_O_mbistwriteen_trigger (MTK_PIN_NO(43) | 7)
#define PINMUX_GPIO44__FUNC_B_GPIO44 (MTK_PIN_NO(44) | 0)
#define PINMUX_GPIO44__FUNC_B1_KPROW0 (MTK_PIN_NO(44) | 1)
#define PINMUX_GPIO45__FUNC_B_GPIO45 (MTK_PIN_NO(45) | 0)
#define PINMUX_GPIO45__FUNC_B1_KPROW1 (MTK_PIN_NO(45) | 1)
#define PINMUX_GPIO45__FUNC_I0_EDP_TX_HPD (MTK_PIN_NO(45) | 2)
#define PINMUX_GPIO45__FUNC_O_CMFLASH3 (MTK_PIN_NO(45) | 3)
#define PINMUX_GPIO45__FUNC_B0_I2SIN_MCK (MTK_PIN_NO(45) | 4)
#define PINMUX_GPIO45__FUNC_O_mbistreaden_trigger (MTK_PIN_NO(45) | 7)
#define PINMUX_GPIO46__FUNC_B_GPIO46 (MTK_PIN_NO(46) | 0)
#define PINMUX_GPIO46__FUNC_I0_DP_TX_HPD (MTK_PIN_NO(46) | 1)
#define PINMUX_GPIO46__FUNC_O_PWM_0 (MTK_PIN_NO(46) | 2)
#define PINMUX_GPIO46__FUNC_I0_VBUSVALID_2P (MTK_PIN_NO(46) | 3)
#define PINMUX_GPIO46__FUNC_B0_DBG_MON_A22 (MTK_PIN_NO(46) | 7)
#define PINMUX_GPIO47__FUNC_B_GPIO47 (MTK_PIN_NO(47) | 0)
#define PINMUX_GPIO47__FUNC_I1_WAKEN (MTK_PIN_NO(47) | 1)
#define PINMUX_GPIO47__FUNC_O_GDU_TROOPS_DET0 (MTK_PIN_NO(47) | 6)
#define PINMUX_GPIO48__FUNC_B_GPIO48 (MTK_PIN_NO(48) | 0)
#define PINMUX_GPIO48__FUNC_O_PERSTN (MTK_PIN_NO(48) | 1)
#define PINMUX_GPIO48__FUNC_O_GDU_TROOPS_DET1 (MTK_PIN_NO(48) | 6)
#define PINMUX_GPIO49__FUNC_B_GPIO49 (MTK_PIN_NO(49) | 0)
#define PINMUX_GPIO49__FUNC_B1_CLKREQN (MTK_PIN_NO(49) | 1)
#define PINMUX_GPIO49__FUNC_O_GDU_TROOPS_DET2 (MTK_PIN_NO(49) | 6)
#define PINMUX_GPIO50__FUNC_B_GPIO50 (MTK_PIN_NO(50) | 0)
#define PINMUX_GPIO50__FUNC_O_HDMITX20_PWR5V (MTK_PIN_NO(50) | 1)
#define PINMUX_GPIO50__FUNC_I1_IDDIG_1P (MTK_PIN_NO(50) | 3)
#define PINMUX_GPIO50__FUNC_I1_SCP_JTAG1_TMS (MTK_PIN_NO(50) | 4)
#define PINMUX_GPIO50__FUNC_I1_SSPM_JTAG_TMS (MTK_PIN_NO(50) | 5)
#define PINMUX_GPIO50__FUNC_I1_MD32_0_JTAG_TMS (MTK_PIN_NO(50) | 6)
#define PINMUX_GPIO50__FUNC_I1_MD32_1_JTAG_TMS (MTK_PIN_NO(50) | 7)
#define PINMUX_GPIO51__FUNC_B_GPIO51 (MTK_PIN_NO(51) | 0)
#define PINMUX_GPIO51__FUNC_I0_HDMITX20_HTPLG (MTK_PIN_NO(51) | 1)
#define PINMUX_GPIO51__FUNC_I0_EDP_TX_HPD (MTK_PIN_NO(51) | 2)
#define PINMUX_GPIO51__FUNC_O_USB_DRVVBUS_1P (MTK_PIN_NO(51) | 3)
#define PINMUX_GPIO51__FUNC_I1_SCP_JTAG1_TCK (MTK_PIN_NO(51) | 4)
#define PINMUX_GPIO51__FUNC_I1_SSPM_JTAG_TCK (MTK_PIN_NO(51) | 5)
#define PINMUX_GPIO51__FUNC_I1_MD32_0_JTAG_TCK (MTK_PIN_NO(51) | 6)
#define PINMUX_GPIO51__FUNC_I1_MD32_1_JTAG_TCK (MTK_PIN_NO(51) | 7)
#define PINMUX_GPIO52__FUNC_B_GPIO52 (MTK_PIN_NO(52) | 0)
#define PINMUX_GPIO52__FUNC_B1_HDMITX20_CEC (MTK_PIN_NO(52) | 1)
#define PINMUX_GPIO52__FUNC_I0_VBUSVALID_1P (MTK_PIN_NO(52) | 3)
#define PINMUX_GPIO52__FUNC_I1_SCP_JTAG1_TDI (MTK_PIN_NO(52) | 4)
#define PINMUX_GPIO52__FUNC_I1_SSPM_JTAG_TDI (MTK_PIN_NO(52) | 5)
#define PINMUX_GPIO52__FUNC_I1_MD32_0_JTAG_TDI (MTK_PIN_NO(52) | 6)
#define PINMUX_GPIO52__FUNC_I1_MD32_1_JTAG_TDI (MTK_PIN_NO(52) | 7)
#define PINMUX_GPIO53__FUNC_B_GPIO53 (MTK_PIN_NO(53) | 0)
#define PINMUX_GPIO53__FUNC_B1_HDMITX20_SCL (MTK_PIN_NO(53) | 1)
#define PINMUX_GPIO53__FUNC_I1_IDDIG_2P (MTK_PIN_NO(53) | 3)
#define PINMUX_GPIO53__FUNC_O_SCP_JTAG1_TDO (MTK_PIN_NO(53) | 4)
#define PINMUX_GPIO53__FUNC_O_SSPM_JTAG_TDO (MTK_PIN_NO(53) | 5)
#define PINMUX_GPIO53__FUNC_O_MD32_0_JTAG_TDO (MTK_PIN_NO(53) | 6)
#define PINMUX_GPIO53__FUNC_O_MD32_1_JTAG_TDO (MTK_PIN_NO(53) | 7)
#define PINMUX_GPIO54__FUNC_B_GPIO54 (MTK_PIN_NO(54) | 0)
#define PINMUX_GPIO54__FUNC_B1_HDMITX20_SDA (MTK_PIN_NO(54) | 1)
#define PINMUX_GPIO54__FUNC_O_USB_DRVVBUS_2P (MTK_PIN_NO(54) | 3)
#define PINMUX_GPIO54__FUNC_I0_SCP_JTAG1_TRSTN (MTK_PIN_NO(54) | 4)
#define PINMUX_GPIO54__FUNC_I0_SSPM_JTAG_TRSTN (MTK_PIN_NO(54) | 5)
#define PINMUX_GPIO54__FUNC_I1_MD32_0_JTAG_TRST (MTK_PIN_NO(54) | 6)
#define PINMUX_GPIO54__FUNC_I1_MD32_1_JTAG_TRST (MTK_PIN_NO(54) | 7)
#define PINMUX_GPIO55__FUNC_B_GPIO55 (MTK_PIN_NO(55) | 0)
#define PINMUX_GPIO55__FUNC_B1_SCL0 (MTK_PIN_NO(55) | 1)
#define PINMUX_GPIO55__FUNC_B1_SCP_SCL0 (MTK_PIN_NO(55) | 2)
#define PINMUX_GPIO55__FUNC_B1_SCP_SCL1 (MTK_PIN_NO(55) | 3)
#define PINMUX_GPIO55__FUNC_B1_PCIE_PHY_I2C_SCL (MTK_PIN_NO(55) | 4)
#define PINMUX_GPIO56__FUNC_B_GPIO56 (MTK_PIN_NO(56) | 0)
#define PINMUX_GPIO56__FUNC_B1_SDA0 (MTK_PIN_NO(56) | 1)
#define PINMUX_GPIO56__FUNC_B1_SCP_SDA0 (MTK_PIN_NO(56) | 2)
#define PINMUX_GPIO56__FUNC_B1_SCP_SDA1 (MTK_PIN_NO(56) | 3)
#define PINMUX_GPIO56__FUNC_B1_PCIE_PHY_I2C_SDA (MTK_PIN_NO(56) | 4)
#define PINMUX_GPIO57__FUNC_B_GPIO57 (MTK_PIN_NO(57) | 0)
#define PINMUX_GPIO57__FUNC_B1_SCL1 (MTK_PIN_NO(57) | 1)
#define PINMUX_GPIO58__FUNC_B_GPIO58 (MTK_PIN_NO(58) | 0)
#define PINMUX_GPIO58__FUNC_B1_SDA1 (MTK_PIN_NO(58) | 1)
#define PINMUX_GPIO59__FUNC_B_GPIO59 (MTK_PIN_NO(59) | 0)
#define PINMUX_GPIO59__FUNC_B1_SCL2 (MTK_PIN_NO(59) | 1)
#define PINMUX_GPIO59__FUNC_B1_SCP_SCL0 (MTK_PIN_NO(59) | 2)
#define PINMUX_GPIO59__FUNC_B1_SCP_SCL1 (MTK_PIN_NO(59) | 3)
#define PINMUX_GPIO60__FUNC_B_GPIO60 (MTK_PIN_NO(60) | 0)
#define PINMUX_GPIO60__FUNC_B1_SDA2 (MTK_PIN_NO(60) | 1)
#define PINMUX_GPIO60__FUNC_B1_SCP_SDA0 (MTK_PIN_NO(60) | 2)
#define PINMUX_GPIO60__FUNC_B1_SCP_SDA1 (MTK_PIN_NO(60) | 3)
#define PINMUX_GPIO61__FUNC_B_GPIO61 (MTK_PIN_NO(61) | 0)
#define PINMUX_GPIO61__FUNC_B1_SCL3 (MTK_PIN_NO(61) | 1)
#define PINMUX_GPIO61__FUNC_B1_SCP_SCL0 (MTK_PIN_NO(61) | 2)
#define PINMUX_GPIO61__FUNC_B1_SCP_SCL1 (MTK_PIN_NO(61) | 3)
#define PINMUX_GPIO61__FUNC_B1_PCIE_PHY_I2C_SCL (MTK_PIN_NO(61) | 4)
#define PINMUX_GPIO62__FUNC_B_GPIO62 (MTK_PIN_NO(62) | 0)
#define PINMUX_GPIO62__FUNC_B1_SDA3 (MTK_PIN_NO(62) | 1)
#define PINMUX_GPIO62__FUNC_B1_SCP_SDA0 (MTK_PIN_NO(62) | 2)
#define PINMUX_GPIO62__FUNC_B1_SCP_SDA1 (MTK_PIN_NO(62) | 3)
#define PINMUX_GPIO62__FUNC_B1_PCIE_PHY_I2C_SDA (MTK_PIN_NO(62) | 4)
#define PINMUX_GPIO63__FUNC_B_GPIO63 (MTK_PIN_NO(63) | 0)
#define PINMUX_GPIO63__FUNC_B1_SCL4 (MTK_PIN_NO(63) | 1)
#define PINMUX_GPIO64__FUNC_B_GPIO64 (MTK_PIN_NO(64) | 0)
#define PINMUX_GPIO64__FUNC_B1_SDA4 (MTK_PIN_NO(64) | 1)
#define PINMUX_GPIO65__FUNC_B_GPIO65 (MTK_PIN_NO(65) | 0)
#define PINMUX_GPIO65__FUNC_B1_SCL5 (MTK_PIN_NO(65) | 1)
#define PINMUX_GPIO65__FUNC_B1_SCP_SCL0 (MTK_PIN_NO(65) | 2)
#define PINMUX_GPIO65__FUNC_B1_SCP_SCL1 (MTK_PIN_NO(65) | 3)
#define PINMUX_GPIO66__FUNC_B_GPIO66 (MTK_PIN_NO(66) | 0)
#define PINMUX_GPIO66__FUNC_B1_SDA5 (MTK_PIN_NO(66) | 1)
#define PINMUX_GPIO66__FUNC_B1_SCP_SDA0 (MTK_PIN_NO(66) | 2)
#define PINMUX_GPIO66__FUNC_B1_SCP_SDA1 (MTK_PIN_NO(66) | 3)
#define PINMUX_GPIO67__FUNC_B_GPIO67 (MTK_PIN_NO(67) | 0)
#define PINMUX_GPIO67__FUNC_B1_SCL6 (MTK_PIN_NO(67) | 1)
#define PINMUX_GPIO67__FUNC_B1_SCP_SCL0 (MTK_PIN_NO(67) | 2)
#define PINMUX_GPIO67__FUNC_B1_SCP_SCL1 (MTK_PIN_NO(67) | 3)
#define PINMUX_GPIO67__FUNC_B1_PCIE_PHY_I2C_SCL (MTK_PIN_NO(67) | 4)
#define PINMUX_GPIO68__FUNC_B_GPIO68 (MTK_PIN_NO(68) | 0)
#define PINMUX_GPIO68__FUNC_B1_SDA6 (MTK_PIN_NO(68) | 1)
#define PINMUX_GPIO68__FUNC_B1_SCP_SDA0 (MTK_PIN_NO(68) | 2)
#define PINMUX_GPIO68__FUNC_B1_SCP_SDA1 (MTK_PIN_NO(68) | 3)
#define PINMUX_GPIO68__FUNC_B1_PCIE_PHY_I2C_SDA (MTK_PIN_NO(68) | 4)
#define PINMUX_GPIO69__FUNC_B_GPIO69 (MTK_PIN_NO(69) | 0)
#define PINMUX_GPIO69__FUNC_O_SPIM0_CSB (MTK_PIN_NO(69) | 1)
#define PINMUX_GPIO69__FUNC_O_SCP_SPI0_CS (MTK_PIN_NO(69) | 2)
#define PINMUX_GPIO69__FUNC_O_DMIC3_CLK (MTK_PIN_NO(69) | 3)
#define PINMUX_GPIO69__FUNC_B0_MD32_1_GPIO0 (MTK_PIN_NO(69) | 4)
#define PINMUX_GPIO69__FUNC_O_CMVREF0 (MTK_PIN_NO(69) | 5)
#define PINMUX_GPIO69__FUNC_O_GDU_SUM_TROOP0_0 (MTK_PIN_NO(69) | 6)
#define PINMUX_GPIO69__FUNC_B0_DBG_MON_A23 (MTK_PIN_NO(69) | 7)
#define PINMUX_GPIO70__FUNC_B_GPIO70 (MTK_PIN_NO(70) | 0)
#define PINMUX_GPIO70__FUNC_O_SPIM0_CLK (MTK_PIN_NO(70) | 1)
#define PINMUX_GPIO70__FUNC_O_SCP_SPI0_CK (MTK_PIN_NO(70) | 2)
#define PINMUX_GPIO70__FUNC_I0_DMIC3_DAT (MTK_PIN_NO(70) | 3)
#define PINMUX_GPIO70__FUNC_B0_MD32_1_GPIO1 (MTK_PIN_NO(70) | 4)
#define PINMUX_GPIO70__FUNC_O_CMVREF1 (MTK_PIN_NO(70) | 5)
#define PINMUX_GPIO70__FUNC_O_GDU_SUM_TROOP0_1 (MTK_PIN_NO(70) | 6)
#define PINMUX_GPIO70__FUNC_B0_DBG_MON_A24 (MTK_PIN_NO(70) | 7)
#define PINMUX_GPIO71__FUNC_B_GPIO71 (MTK_PIN_NO(71) | 0)
#define PINMUX_GPIO71__FUNC_B0_SPIM0_MOSI (MTK_PIN_NO(71) | 1)
#define PINMUX_GPIO71__FUNC_O_SCP_SPI0_MO (MTK_PIN_NO(71) | 2)
#define PINMUX_GPIO71__FUNC_I0_DMIC3_DAT_R (MTK_PIN_NO(71) | 3)
#define PINMUX_GPIO71__FUNC_B0_MD32_1_GPIO2 (MTK_PIN_NO(71) | 4)
#define PINMUX_GPIO71__FUNC_O_CMVREF2 (MTK_PIN_NO(71) | 5)
#define PINMUX_GPIO71__FUNC_O_GDU_SUM_TROOP0_2 (MTK_PIN_NO(71) | 6)
#define PINMUX_GPIO71__FUNC_B0_DBG_MON_A25 (MTK_PIN_NO(71) | 7)
#define PINMUX_GPIO72__FUNC_B_GPIO72 (MTK_PIN_NO(72) | 0)
#define PINMUX_GPIO72__FUNC_B0_SPIM0_MISO (MTK_PIN_NO(72) | 1)
#define PINMUX_GPIO72__FUNC_I0_SCP_SPI0_MI (MTK_PIN_NO(72) | 2)
#define PINMUX_GPIO72__FUNC_O_DMIC4_CLK (MTK_PIN_NO(72) | 3)
#define PINMUX_GPIO72__FUNC_O_CMVREF3 (MTK_PIN_NO(72) | 5)
#define PINMUX_GPIO72__FUNC_O_GDU_SUM_TROOP1_0 (MTK_PIN_NO(72) | 6)
#define PINMUX_GPIO72__FUNC_B0_DBG_MON_A26 (MTK_PIN_NO(72) | 7)
#define PINMUX_GPIO73__FUNC_B_GPIO73 (MTK_PIN_NO(73) | 0)
#define PINMUX_GPIO73__FUNC_B0_SPIM0_MIO2 (MTK_PIN_NO(73) | 1)
#define PINMUX_GPIO73__FUNC_O_UTXD3 (MTK_PIN_NO(73) | 2)
#define PINMUX_GPIO73__FUNC_I0_DMIC4_DAT (MTK_PIN_NO(73) | 3)
#define PINMUX_GPIO73__FUNC_O_CLKM0 (MTK_PIN_NO(73) | 4)
#define PINMUX_GPIO73__FUNC_O_CMVREF4 (MTK_PIN_NO(73) | 5)
#define PINMUX_GPIO73__FUNC_O_GDU_SUM_TROOP1_1 (MTK_PIN_NO(73) | 6)
#define PINMUX_GPIO73__FUNC_B0_DBG_MON_A27 (MTK_PIN_NO(73) | 7)
#define PINMUX_GPIO74__FUNC_B_GPIO74 (MTK_PIN_NO(74) | 0)
#define PINMUX_GPIO74__FUNC_B0_SPIM0_MIO3 (MTK_PIN_NO(74) | 1)
#define PINMUX_GPIO74__FUNC_I1_URXD3 (MTK_PIN_NO(74) | 2)
#define PINMUX_GPIO74__FUNC_I0_DMIC4_DAT_R (MTK_PIN_NO(74) | 3)
#define PINMUX_GPIO74__FUNC_O_CLKM1 (MTK_PIN_NO(74) | 4)
#define PINMUX_GPIO74__FUNC_O_CMVREF5 (MTK_PIN_NO(74) | 5)
#define PINMUX_GPIO74__FUNC_O_GDU_SUM_TROOP1_2 (MTK_PIN_NO(74) | 6)
#define PINMUX_GPIO74__FUNC_B0_DBG_MON_A28 (MTK_PIN_NO(74) | 7)
#define PINMUX_GPIO75__FUNC_B_GPIO75 (MTK_PIN_NO(75) | 0)
#define PINMUX_GPIO75__FUNC_O_SPIM1_CSB (MTK_PIN_NO(75) | 1)
#define PINMUX_GPIO75__FUNC_O_SCP_SPI1_A_CS (MTK_PIN_NO(75) | 2)
#define PINMUX_GPIO75__FUNC_B0_TDMIN_MCK (MTK_PIN_NO(75) | 3)
#define PINMUX_GPIO75__FUNC_B1_SCP_SCL0 (MTK_PIN_NO(75) | 4)
#define PINMUX_GPIO75__FUNC_O_CMVREF6 (MTK_PIN_NO(75) | 5)
#define PINMUX_GPIO75__FUNC_O_GDU_SUM_TROOP2_0 (MTK_PIN_NO(75) | 6)
#define PINMUX_GPIO75__FUNC_B0_DBG_MON_A29 (MTK_PIN_NO(75) | 7)
#define PINMUX_GPIO76__FUNC_B_GPIO76 (MTK_PIN_NO(76) | 0)
#define PINMUX_GPIO76__FUNC_O_SPIM1_CLK (MTK_PIN_NO(76) | 1)
#define PINMUX_GPIO76__FUNC_O_SCP_SPI1_A_CK (MTK_PIN_NO(76) | 2)
#define PINMUX_GPIO76__FUNC_B0_TDMIN_BCK (MTK_PIN_NO(76) | 3)
#define PINMUX_GPIO76__FUNC_B1_SCP_SDA0 (MTK_PIN_NO(76) | 4)
#define PINMUX_GPIO76__FUNC_O_CMVREF7 (MTK_PIN_NO(76) | 5)
#define PINMUX_GPIO76__FUNC_O_GDU_SUM_TROOP2_1 (MTK_PIN_NO(76) | 6)
#define PINMUX_GPIO76__FUNC_B0_DBG_MON_A30 (MTK_PIN_NO(76) | 7)
#define PINMUX_GPIO77__FUNC_B_GPIO77 (MTK_PIN_NO(77) | 0)
#define PINMUX_GPIO77__FUNC_B0_SPIM1_MOSI (MTK_PIN_NO(77) | 1)
#define PINMUX_GPIO77__FUNC_O_SCP_SPI1_A_MO (MTK_PIN_NO(77) | 2)
#define PINMUX_GPIO77__FUNC_B0_TDMIN_LRCK (MTK_PIN_NO(77) | 3)
#define PINMUX_GPIO77__FUNC_B1_SCP_SCL1 (MTK_PIN_NO(77) | 4)
#define PINMUX_GPIO77__FUNC_O_GDU_SUM_TROOP2_2 (MTK_PIN_NO(77) | 6)
#define PINMUX_GPIO77__FUNC_B0_DBG_MON_A31 (MTK_PIN_NO(77) | 7)
#define PINMUX_GPIO78__FUNC_B_GPIO78 (MTK_PIN_NO(78) | 0)
#define PINMUX_GPIO78__FUNC_B0_SPIM1_MISO (MTK_PIN_NO(78) | 1)
#define PINMUX_GPIO78__FUNC_I0_SCP_SPI1_A_MI (MTK_PIN_NO(78) | 2)
#define PINMUX_GPIO78__FUNC_I0_TDMIN_DI (MTK_PIN_NO(78) | 3)
#define PINMUX_GPIO78__FUNC_B1_SCP_SDA1 (MTK_PIN_NO(78) | 4)
#define PINMUX_GPIO78__FUNC_B0_DBG_MON_A32 (MTK_PIN_NO(78) | 7)
#define PINMUX_GPIO79__FUNC_B_GPIO79 (MTK_PIN_NO(79) | 0)
#define PINMUX_GPIO79__FUNC_O_SPIM2_CSB (MTK_PIN_NO(79) | 1)
#define PINMUX_GPIO79__FUNC_O_SCP_SPI2_CS (MTK_PIN_NO(79) | 2)
#define PINMUX_GPIO79__FUNC_O_I2SO1_MCK (MTK_PIN_NO(79) | 3)
#define PINMUX_GPIO79__FUNC_O_UTXD2 (MTK_PIN_NO(79) | 4)
#define PINMUX_GPIO79__FUNC_O_TP_UTXD2_AO (MTK_PIN_NO(79) | 5)
#define PINMUX_GPIO79__FUNC_B0_PCM_SYNC (MTK_PIN_NO(79) | 6)
#define PINMUX_GPIO79__FUNC_B0_DBG_MON_B0 (MTK_PIN_NO(79) | 7)
#define PINMUX_GPIO80__FUNC_B_GPIO80 (MTK_PIN_NO(80) | 0)
#define PINMUX_GPIO80__FUNC_O_SPIM2_CLK (MTK_PIN_NO(80) | 1)
#define PINMUX_GPIO80__FUNC_O_SCP_SPI2_CK (MTK_PIN_NO(80) | 2)
#define PINMUX_GPIO80__FUNC_O_I2SO1_BCK (MTK_PIN_NO(80) | 3)
#define PINMUX_GPIO80__FUNC_I1_URXD2 (MTK_PIN_NO(80) | 4)
#define PINMUX_GPIO80__FUNC_I1_TP_URXD2_AO (MTK_PIN_NO(80) | 5)
#define PINMUX_GPIO80__FUNC_B0_PCM_CLK (MTK_PIN_NO(80) | 6)
#define PINMUX_GPIO80__FUNC_B0_DBG_MON_B1 (MTK_PIN_NO(80) | 7)
#define PINMUX_GPIO81__FUNC_B_GPIO81 (MTK_PIN_NO(81) | 0)
#define PINMUX_GPIO81__FUNC_B0_SPIM2_MOSI (MTK_PIN_NO(81) | 1)
#define PINMUX_GPIO81__FUNC_O_SCP_SPI2_MO (MTK_PIN_NO(81) | 2)
#define PINMUX_GPIO81__FUNC_O_I2SO1_WS (MTK_PIN_NO(81) | 3)
#define PINMUX_GPIO81__FUNC_O_URTS2 (MTK_PIN_NO(81) | 4)
#define PINMUX_GPIO81__FUNC_O_TP_URTS2_AO (MTK_PIN_NO(81) | 5)
#define PINMUX_GPIO81__FUNC_O_PCM_DO (MTK_PIN_NO(81) | 6)
#define PINMUX_GPIO81__FUNC_B0_DBG_MON_B2 (MTK_PIN_NO(81) | 7)
#define PINMUX_GPIO82__FUNC_B_GPIO82 (MTK_PIN_NO(82) | 0)
#define PINMUX_GPIO82__FUNC_B0_SPIM2_MISO (MTK_PIN_NO(82) | 1)
#define PINMUX_GPIO82__FUNC_I0_SCP_SPI2_MI (MTK_PIN_NO(82) | 2)
#define PINMUX_GPIO82__FUNC_O_I2SO1_D0 (MTK_PIN_NO(82) | 3)
#define PINMUX_GPIO82__FUNC_I1_UCTS2 (MTK_PIN_NO(82) | 4)
#define PINMUX_GPIO82__FUNC_I1_TP_UCTS2_AO (MTK_PIN_NO(82) | 5)
#define PINMUX_GPIO82__FUNC_I0_PCM_DI (MTK_PIN_NO(82) | 6)
#define PINMUX_GPIO82__FUNC_B0_DBG_MON_B3 (MTK_PIN_NO(82) | 7)
#define PINMUX_GPIO83__FUNC_B_GPIO83 (MTK_PIN_NO(83) | 0)
#define PINMUX_GPIO83__FUNC_I1_IDDIG (MTK_PIN_NO(83) | 1)
#define PINMUX_GPIO84__FUNC_B_GPIO84 (MTK_PIN_NO(84) | 0)
#define PINMUX_GPIO84__FUNC_O_USB_DRVVBUS (MTK_PIN_NO(84) | 1)
#define PINMUX_GPIO85__FUNC_B_GPIO85 (MTK_PIN_NO(85) | 0)
#define PINMUX_GPIO85__FUNC_I0_VBUSVALID (MTK_PIN_NO(85) | 1)
#define PINMUX_GPIO86__FUNC_B_GPIO86 (MTK_PIN_NO(86) | 0)
#define PINMUX_GPIO86__FUNC_I1_IDDIG_1P (MTK_PIN_NO(86) | 1)
#define PINMUX_GPIO86__FUNC_O_UTXD1 (MTK_PIN_NO(86) | 2)
#define PINMUX_GPIO86__FUNC_O_URTS2 (MTK_PIN_NO(86) | 3)
#define PINMUX_GPIO86__FUNC_O_PWM_2 (MTK_PIN_NO(86) | 4)
#define PINMUX_GPIO86__FUNC_B0_TP_GPIO4_AO (MTK_PIN_NO(86) | 5)
#define PINMUX_GPIO86__FUNC_O_AUXIF_ST0 (MTK_PIN_NO(86) | 6)
#define PINMUX_GPIO86__FUNC_B0_DBG_MON_B4 (MTK_PIN_NO(86) | 7)
#define PINMUX_GPIO87__FUNC_B_GPIO87 (MTK_PIN_NO(87) | 0)
#define PINMUX_GPIO87__FUNC_O_USB_DRVVBUS_1P (MTK_PIN_NO(87) | 1)
#define PINMUX_GPIO87__FUNC_I1_URXD1 (MTK_PIN_NO(87) | 2)
#define PINMUX_GPIO87__FUNC_I1_UCTS2 (MTK_PIN_NO(87) | 3)
#define PINMUX_GPIO87__FUNC_O_PWM_3 (MTK_PIN_NO(87) | 4)
#define PINMUX_GPIO87__FUNC_B0_TP_GPIO5_AO (MTK_PIN_NO(87) | 5)
#define PINMUX_GPIO87__FUNC_O_AUXIF_CLK0 (MTK_PIN_NO(87) | 6)
#define PINMUX_GPIO87__FUNC_B0_DBG_MON_B5 (MTK_PIN_NO(87) | 7)
#define PINMUX_GPIO88__FUNC_B_GPIO88 (MTK_PIN_NO(88) | 0)
#define PINMUX_GPIO88__FUNC_I0_VBUSVALID_1P (MTK_PIN_NO(88) | 1)
#define PINMUX_GPIO88__FUNC_O_UTXD2 (MTK_PIN_NO(88) | 2)
#define PINMUX_GPIO88__FUNC_O_URTS1 (MTK_PIN_NO(88) | 3)
#define PINMUX_GPIO88__FUNC_O_CLKM2 (MTK_PIN_NO(88) | 4)
#define PINMUX_GPIO88__FUNC_B0_TP_GPIO6_AO (MTK_PIN_NO(88) | 5)
#define PINMUX_GPIO88__FUNC_O_AUXIF_ST1 (MTK_PIN_NO(88) | 6)
#define PINMUX_GPIO88__FUNC_B0_DBG_MON_B6 (MTK_PIN_NO(88) | 7)
#define PINMUX_GPIO89__FUNC_B_GPIO89 (MTK_PIN_NO(89) | 0)
#define PINMUX_GPIO89__FUNC_I1_IDDIG_2P (MTK_PIN_NO(89) | 1)
#define PINMUX_GPIO89__FUNC_I1_URXD2 (MTK_PIN_NO(89) | 2)
#define PINMUX_GPIO89__FUNC_I1_UCTS1 (MTK_PIN_NO(89) | 3)
#define PINMUX_GPIO89__FUNC_O_CLKM3 (MTK_PIN_NO(89) | 4)
#define PINMUX_GPIO89__FUNC_B0_TP_GPIO7_AO (MTK_PIN_NO(89) | 5)
#define PINMUX_GPIO89__FUNC_O_AUXIF_CLK1 (MTK_PIN_NO(89) | 6)
#define PINMUX_GPIO89__FUNC_B0_DBG_MON_B7 (MTK_PIN_NO(89) | 7)
#define PINMUX_GPIO90__FUNC_B_GPIO90 (MTK_PIN_NO(90) | 0)
#define PINMUX_GPIO90__FUNC_O_USB_DRVVBUS_2P (MTK_PIN_NO(90) | 1)
#define PINMUX_GPIO90__FUNC_O_UTXD3 (MTK_PIN_NO(90) | 2)
#define PINMUX_GPIO90__FUNC_O_ADSP_UTXD0 (MTK_PIN_NO(90) | 3)
#define PINMUX_GPIO90__FUNC_O_SSPM_UTXD_AO (MTK_PIN_NO(90) | 4)
#define PINMUX_GPIO90__FUNC_O_MD32_0_TXD (MTK_PIN_NO(90) | 5)
#define PINMUX_GPIO90__FUNC_O_MD32_1_TXD (MTK_PIN_NO(90) | 6)
#define PINMUX_GPIO90__FUNC_B0_DBG_MON_B8 (MTK_PIN_NO(90) | 7)
#define PINMUX_GPIO91__FUNC_B_GPIO91 (MTK_PIN_NO(91) | 0)
#define PINMUX_GPIO91__FUNC_I0_VBUSVALID_2P (MTK_PIN_NO(91) | 1)
#define PINMUX_GPIO91__FUNC_I1_URXD3 (MTK_PIN_NO(91) | 2)
#define PINMUX_GPIO91__FUNC_I1_ADSP_URXD0 (MTK_PIN_NO(91) | 3)
#define PINMUX_GPIO91__FUNC_I1_SSPM_URXD_AO (MTK_PIN_NO(91) | 4)
#define PINMUX_GPIO91__FUNC_I1_MD32_0_RXD (MTK_PIN_NO(91) | 5)
#define PINMUX_GPIO91__FUNC_I1_MD32_1_RXD (MTK_PIN_NO(91) | 6)
#define PINMUX_GPIO91__FUNC_B0_DBG_MON_B9 (MTK_PIN_NO(91) | 7)
#define PINMUX_GPIO92__FUNC_B_GPIO92 (MTK_PIN_NO(92) | 0)
#define PINMUX_GPIO92__FUNC_O_PWRAP_SPI0_CSN (MTK_PIN_NO(92) | 1)
#define PINMUX_GPIO93__FUNC_B_GPIO93 (MTK_PIN_NO(93) | 0)
#define PINMUX_GPIO93__FUNC_O_PWRAP_SPI0_CK (MTK_PIN_NO(93) | 1)
#define PINMUX_GPIO94__FUNC_B_GPIO94 (MTK_PIN_NO(94) | 0)
#define PINMUX_GPIO94__FUNC_B0_PWRAP_SPI0_MO (MTK_PIN_NO(94) | 1)
#define PINMUX_GPIO94__FUNC_B0_PWRAP_SPI0_MI (MTK_PIN_NO(94) | 2)
#define PINMUX_GPIO95__FUNC_B_GPIO95 (MTK_PIN_NO(95) | 0)
#define PINMUX_GPIO95__FUNC_B0_PWRAP_SPI0_MI (MTK_PIN_NO(95) | 1)
#define PINMUX_GPIO95__FUNC_B0_PWRAP_SPI0_MO (MTK_PIN_NO(95) | 2)
#define PINMUX_GPIO96__FUNC_B_GPIO96 (MTK_PIN_NO(96) | 0)
#define PINMUX_GPIO96__FUNC_O_SRCLKENA0 (MTK_PIN_NO(96) | 1)
#define PINMUX_GPIO97__FUNC_B_GPIO97 (MTK_PIN_NO(97) | 0)
#define PINMUX_GPIO97__FUNC_O_SRCLKENA1 (MTK_PIN_NO(97) | 1)
#define PINMUX_GPIO98__FUNC_B_GPIO98 (MTK_PIN_NO(98) | 0)
#define PINMUX_GPIO98__FUNC_O_SCP_VREQ_VAO (MTK_PIN_NO(98) | 1)
#define PINMUX_GPIO98__FUNC_I0_DVFSRC_EXT_REQ (MTK_PIN_NO(98) | 2)
#define PINMUX_GPIO99__FUNC_B_GPIO99 (MTK_PIN_NO(99) | 0)
#define PINMUX_GPIO99__FUNC_I0_RTC32K_CK (MTK_PIN_NO(99) | 1)
#define PINMUX_GPIO100__FUNC_B_GPIO100 (MTK_PIN_NO(100) | 0)
#define PINMUX_GPIO100__FUNC_O_WATCHDOG (MTK_PIN_NO(100) | 1)
#define PINMUX_GPIO101__FUNC_B_GPIO101 (MTK_PIN_NO(101) | 0)
#define PINMUX_GPIO101__FUNC_O_AUD_CLK_MOSI (MTK_PIN_NO(101) | 1)
#define PINMUX_GPIO101__FUNC_O_I2SO1_MCK (MTK_PIN_NO(101) | 2)
#define PINMUX_GPIO101__FUNC_B0_I2SIN_BCK (MTK_PIN_NO(101) | 3)
#define PINMUX_GPIO102__FUNC_B_GPIO102 (MTK_PIN_NO(102) | 0)
#define PINMUX_GPIO102__FUNC_O_AUD_SYNC_MOSI (MTK_PIN_NO(102) | 1)
#define PINMUX_GPIO102__FUNC_O_I2SO1_BCK (MTK_PIN_NO(102) | 2)
#define PINMUX_GPIO102__FUNC_B0_I2SIN_WS (MTK_PIN_NO(102) | 3)
#define PINMUX_GPIO103__FUNC_B_GPIO103 (MTK_PIN_NO(103) | 0)
#define PINMUX_GPIO103__FUNC_O_AUD_DAT_MOSI0 (MTK_PIN_NO(103) | 1)
#define PINMUX_GPIO103__FUNC_O_I2SO1_WS (MTK_PIN_NO(103) | 2)
#define PINMUX_GPIO103__FUNC_I0_I2SIN_D0 (MTK_PIN_NO(103) | 3)
#define PINMUX_GPIO104__FUNC_B_GPIO104 (MTK_PIN_NO(104) | 0)
#define PINMUX_GPIO104__FUNC_O_AUD_DAT_MOSI1 (MTK_PIN_NO(104) | 1)
#define PINMUX_GPIO104__FUNC_O_I2SO1_D0 (MTK_PIN_NO(104) | 2)
#define PINMUX_GPIO104__FUNC_I0_I2SIN_D1 (MTK_PIN_NO(104) | 3)
#define PINMUX_GPIO105__FUNC_B_GPIO105 (MTK_PIN_NO(105) | 0)
#define PINMUX_GPIO105__FUNC_I0_AUD_DAT_MISO0 (MTK_PIN_NO(105) | 1)
#define PINMUX_GPIO105__FUNC_I0_VOW_DAT_MISO (MTK_PIN_NO(105) | 2)
#define PINMUX_GPIO105__FUNC_I0_I2SIN_D2 (MTK_PIN_NO(105) | 3)
#define PINMUX_GPIO106__FUNC_B_GPIO106 (MTK_PIN_NO(106) | 0)
#define PINMUX_GPIO106__FUNC_I0_AUD_DAT_MISO1 (MTK_PIN_NO(106) | 1)
#define PINMUX_GPIO106__FUNC_I0_VOW_CLK_MISO (MTK_PIN_NO(106) | 2)
#define PINMUX_GPIO106__FUNC_I0_I2SIN_D3 (MTK_PIN_NO(106) | 3)
#define PINMUX_GPIO107__FUNC_B_GPIO107 (MTK_PIN_NO(107) | 0)
#define PINMUX_GPIO107__FUNC_B0_I2SIN_MCK (MTK_PIN_NO(107) | 1)
#define PINMUX_GPIO107__FUNC_I0_SPLIN_MCK (MTK_PIN_NO(107) | 2)
#define PINMUX_GPIO107__FUNC_I0_SPDIF_IN0 (MTK_PIN_NO(107) | 3)
#define PINMUX_GPIO107__FUNC_O_CMVREF4 (MTK_PIN_NO(107) | 4)
#define PINMUX_GPIO107__FUNC_O_AUXIF_ST0 (MTK_PIN_NO(107) | 5)
#define PINMUX_GPIO107__FUNC_O_PGD_LV_LSC_PWR0 (MTK_PIN_NO(107) | 6)
#define PINMUX_GPIO108__FUNC_B_GPIO108 (MTK_PIN_NO(108) | 0)
#define PINMUX_GPIO108__FUNC_B0_I2SIN_BCK (MTK_PIN_NO(108) | 1)
#define PINMUX_GPIO108__FUNC_I0_SPLIN_LRCK (MTK_PIN_NO(108) | 2)
#define PINMUX_GPIO108__FUNC_O_DMIC4_CLK (MTK_PIN_NO(108) | 3)
#define PINMUX_GPIO108__FUNC_O_CMVREF5 (MTK_PIN_NO(108) | 4)
#define PINMUX_GPIO108__FUNC_O_AUXIF_CLK0 (MTK_PIN_NO(108) | 5)
#define PINMUX_GPIO108__FUNC_O_PGD_LV_LSC_PWR1 (MTK_PIN_NO(108) | 6)
#define PINMUX_GPIO108__FUNC_B0_DBG_MON_B10 (MTK_PIN_NO(108) | 7)
#define PINMUX_GPIO109__FUNC_B_GPIO109 (MTK_PIN_NO(109) | 0)
#define PINMUX_GPIO109__FUNC_B0_I2SIN_WS (MTK_PIN_NO(109) | 1)
#define PINMUX_GPIO109__FUNC_I0_SPLIN_BCK (MTK_PIN_NO(109) | 2)
#define PINMUX_GPIO109__FUNC_I0_DMIC4_DAT (MTK_PIN_NO(109) | 3)
#define PINMUX_GPIO109__FUNC_O_CMVREF6 (MTK_PIN_NO(109) | 4)
#define PINMUX_GPIO109__FUNC_O_AUXIF_ST1 (MTK_PIN_NO(109) | 5)
#define PINMUX_GPIO109__FUNC_O_PGD_LV_LSC_PWR2 (MTK_PIN_NO(109) | 6)
#define PINMUX_GPIO109__FUNC_B0_DBG_MON_B11 (MTK_PIN_NO(109) | 7)
#define PINMUX_GPIO110__FUNC_B_GPIO110 (MTK_PIN_NO(110) | 0)
#define PINMUX_GPIO110__FUNC_I0_I2SIN_D0 (MTK_PIN_NO(110) | 1)
#define PINMUX_GPIO110__FUNC_I0_SPLIN_D0 (MTK_PIN_NO(110) | 2)
#define PINMUX_GPIO110__FUNC_I0_DMIC4_DAT_R (MTK_PIN_NO(110) | 3)
#define PINMUX_GPIO110__FUNC_O_CMVREF7 (MTK_PIN_NO(110) | 4)
#define PINMUX_GPIO110__FUNC_O_AUXIF_CLK1 (MTK_PIN_NO(110) | 5)
#define PINMUX_GPIO110__FUNC_O_PGD_LV_LSC_PWR3 (MTK_PIN_NO(110) | 6)
#define PINMUX_GPIO110__FUNC_B0_DBG_MON_B12 (MTK_PIN_NO(110) | 7)
#define PINMUX_GPIO111__FUNC_B_GPIO111 (MTK_PIN_NO(111) | 0)
#define PINMUX_GPIO111__FUNC_I0_I2SIN_D1 (MTK_PIN_NO(111) | 1)
#define PINMUX_GPIO111__FUNC_I0_SPLIN_D1 (MTK_PIN_NO(111) | 2)
#define PINMUX_GPIO111__FUNC_O_DMIC3_CLK (MTK_PIN_NO(111) | 3)
#define PINMUX_GPIO111__FUNC_O_SPDIF_OUT (MTK_PIN_NO(111) | 4)
#define PINMUX_GPIO111__FUNC_O_PGD_LV_LSC_PWR4 (MTK_PIN_NO(111) | 6)
#define PINMUX_GPIO111__FUNC_B0_DBG_MON_B13 (MTK_PIN_NO(111) | 7)
#define PINMUX_GPIO112__FUNC_B_GPIO112 (MTK_PIN_NO(112) | 0)
#define PINMUX_GPIO112__FUNC_I0_I2SIN_D2 (MTK_PIN_NO(112) | 1)
#define PINMUX_GPIO112__FUNC_I0_SPLIN_D2 (MTK_PIN_NO(112) | 2)
#define PINMUX_GPIO112__FUNC_I0_DMIC3_DAT (MTK_PIN_NO(112) | 3)
#define PINMUX_GPIO112__FUNC_B0_TDMIN_MCK (MTK_PIN_NO(112) | 4)
#define PINMUX_GPIO112__FUNC_O_I2SO1_WS (MTK_PIN_NO(112) | 5)
#define PINMUX_GPIO112__FUNC_O_PGD_LV_LSC_PWR5 (MTK_PIN_NO(112) | 6)
#define PINMUX_GPIO112__FUNC_B0_DBG_MON_B14 (MTK_PIN_NO(112) | 7)
#define PINMUX_GPIO113__FUNC_B_GPIO113 (MTK_PIN_NO(113) | 0)
#define PINMUX_GPIO113__FUNC_I0_I2SIN_D3 (MTK_PIN_NO(113) | 1)
#define PINMUX_GPIO113__FUNC_I0_SPLIN_D3 (MTK_PIN_NO(113) | 2)
#define PINMUX_GPIO113__FUNC_I0_DMIC3_DAT_R (MTK_PIN_NO(113) | 3)
#define PINMUX_GPIO113__FUNC_B0_TDMIN_BCK (MTK_PIN_NO(113) | 4)
#define PINMUX_GPIO113__FUNC_O_I2SO1_D0 (MTK_PIN_NO(113) | 5)
#define PINMUX_GPIO113__FUNC_B0_DBG_MON_B15 (MTK_PIN_NO(113) | 7)
#define PINMUX_GPIO114__FUNC_B_GPIO114 (MTK_PIN_NO(114) | 0)
#define PINMUX_GPIO114__FUNC_O_I2SO2_MCK (MTK_PIN_NO(114) | 1)
#define PINMUX_GPIO114__FUNC_B0_I2SIN_MCK (MTK_PIN_NO(114) | 2)
#define PINMUX_GPIO114__FUNC_I1_MCUPM_JTAG_TMS (MTK_PIN_NO(114) | 3)
#define PINMUX_GPIO114__FUNC_B1_APU_JTAG_TMS (MTK_PIN_NO(114) | 4)
#define PINMUX_GPIO114__FUNC_I1_SCP_JTAG1_TMS (MTK_PIN_NO(114) | 5)
#define PINMUX_GPIO114__FUNC_I1_SPM_JTAG_TMS (MTK_PIN_NO(114) | 6)
#define PINMUX_GPIO114__FUNC_B0_DBG_MON_B16 (MTK_PIN_NO(114) | 7)
#define PINMUX_GPIO115__FUNC_B_GPIO115 (MTK_PIN_NO(115) | 0)
#define PINMUX_GPIO115__FUNC_B0_I2SO2_BCK (MTK_PIN_NO(115) | 1)
#define PINMUX_GPIO115__FUNC_B0_I2SIN_BCK (MTK_PIN_NO(115) | 2)
#define PINMUX_GPIO115__FUNC_I1_MCUPM_JTAG_TCK (MTK_PIN_NO(115) | 3)
#define PINMUX_GPIO115__FUNC_I0_APU_JTAG_TCK (MTK_PIN_NO(115) | 4)
#define PINMUX_GPIO115__FUNC_I1_SCP_JTAG1_TCK (MTK_PIN_NO(115) | 5)
#define PINMUX_GPIO115__FUNC_I1_SPM_JTAG_TCK (MTK_PIN_NO(115) | 6)
#define PINMUX_GPIO115__FUNC_B0_DBG_MON_B17 (MTK_PIN_NO(115) | 7)
#define PINMUX_GPIO116__FUNC_B_GPIO116 (MTK_PIN_NO(116) | 0)
#define PINMUX_GPIO116__FUNC_B0_I2SO2_WS (MTK_PIN_NO(116) | 1)
#define PINMUX_GPIO116__FUNC_B0_I2SIN_WS (MTK_PIN_NO(116) | 2)
#define PINMUX_GPIO116__FUNC_I1_MCUPM_JTAG_TDI (MTK_PIN_NO(116) | 3)
#define PINMUX_GPIO116__FUNC_I1_APU_JTAG_TDI (MTK_PIN_NO(116) | 4)
#define PINMUX_GPIO116__FUNC_I1_SCP_JTAG1_TDI (MTK_PIN_NO(116) | 5)
#define PINMUX_GPIO116__FUNC_I1_SPM_JTAG_TDI (MTK_PIN_NO(116) | 6)
#define PINMUX_GPIO116__FUNC_B0_DBG_MON_B18 (MTK_PIN_NO(116) | 7)
#define PINMUX_GPIO117__FUNC_B_GPIO117 (MTK_PIN_NO(117) | 0)
#define PINMUX_GPIO117__FUNC_O_I2SO2_D0 (MTK_PIN_NO(117) | 1)
#define PINMUX_GPIO117__FUNC_I0_I2SIN_D0 (MTK_PIN_NO(117) | 2)
#define PINMUX_GPIO117__FUNC_O_MCUPM_JTAG_TDO (MTK_PIN_NO(117) | 3)
#define PINMUX_GPIO117__FUNC_O_APU_JTAG_TDO (MTK_PIN_NO(117) | 4)
#define PINMUX_GPIO117__FUNC_O_SCP_JTAG1_TDO (MTK_PIN_NO(117) | 5)
#define PINMUX_GPIO117__FUNC_O_SPM_JTAG_TDO (MTK_PIN_NO(117) | 6)
#define PINMUX_GPIO117__FUNC_B0_DBG_MON_B19 (MTK_PIN_NO(117) | 7)
#define PINMUX_GPIO118__FUNC_B_GPIO118 (MTK_PIN_NO(118) | 0)
#define PINMUX_GPIO118__FUNC_O_I2SO2_D1 (MTK_PIN_NO(118) | 1)
#define PINMUX_GPIO118__FUNC_I0_I2SIN_D1 (MTK_PIN_NO(118) | 2)
#define PINMUX_GPIO118__FUNC_I0_MCUPM_JTAG_TRSTN (MTK_PIN_NO(118) | 3)
#define PINMUX_GPIO118__FUNC_I0_APU_JTAG_TRST (MTK_PIN_NO(118) | 4)
#define PINMUX_GPIO118__FUNC_I0_SCP_JTAG1_TRSTN (MTK_PIN_NO(118) | 5)
#define PINMUX_GPIO118__FUNC_I0_SPM_JTAG_TRSTN (MTK_PIN_NO(118) | 6)
#define PINMUX_GPIO118__FUNC_B0_DBG_MON_B20 (MTK_PIN_NO(118) | 7)
#define PINMUX_GPIO119__FUNC_B_GPIO119 (MTK_PIN_NO(119) | 0)
#define PINMUX_GPIO119__FUNC_O_I2SO2_D2 (MTK_PIN_NO(119) | 1)
#define PINMUX_GPIO119__FUNC_I0_I2SIN_D2 (MTK_PIN_NO(119) | 2)
#define PINMUX_GPIO119__FUNC_O_UTXD3 (MTK_PIN_NO(119) | 3)
#define PINMUX_GPIO119__FUNC_B0_TDMIN_LRCK (MTK_PIN_NO(119) | 4)
#define PINMUX_GPIO119__FUNC_O_I2SO1_MCK (MTK_PIN_NO(119) | 5)
#define PINMUX_GPIO119__FUNC_O_SSPM_UTXD_AO (MTK_PIN_NO(119) | 6)
#define PINMUX_GPIO119__FUNC_B0_DBG_MON_B21 (MTK_PIN_NO(119) | 7)
#define PINMUX_GPIO120__FUNC_B_GPIO120 (MTK_PIN_NO(120) | 0)
#define PINMUX_GPIO120__FUNC_O_I2SO2_D3 (MTK_PIN_NO(120) | 1)
#define PINMUX_GPIO120__FUNC_I0_I2SIN_D3 (MTK_PIN_NO(120) | 2)
#define PINMUX_GPIO120__FUNC_I1_URXD3 (MTK_PIN_NO(120) | 3)
#define PINMUX_GPIO120__FUNC_I0_TDMIN_DI (MTK_PIN_NO(120) | 4)
#define PINMUX_GPIO120__FUNC_O_I2SO1_BCK (MTK_PIN_NO(120) | 5)
#define PINMUX_GPIO120__FUNC_I1_SSPM_URXD_AO (MTK_PIN_NO(120) | 6)
#define PINMUX_GPIO120__FUNC_B0_DBG_MON_B22 (MTK_PIN_NO(120) | 7)
#define PINMUX_GPIO121__FUNC_B_GPIO121 (MTK_PIN_NO(121) | 0)
#define PINMUX_GPIO121__FUNC_B0_PCM_CLK (MTK_PIN_NO(121) | 1)
#define PINMUX_GPIO121__FUNC_O_SPIM4_CSB (MTK_PIN_NO(121) | 2)
#define PINMUX_GPIO121__FUNC_O_SCP_SPI1_B_CS (MTK_PIN_NO(121) | 3)
#define PINMUX_GPIO121__FUNC_O_TP_UTXD2_AO (MTK_PIN_NO(121) | 4)
#define PINMUX_GPIO121__FUNC_O_AUXIF_ST0 (MTK_PIN_NO(121) | 5)
#define PINMUX_GPIO121__FUNC_O_PGD_DA_EFUSE_RDY (MTK_PIN_NO(121) | 6)
#define PINMUX_GPIO121__FUNC_B0_DBG_MON_B23 (MTK_PIN_NO(121) | 7)
#define PINMUX_GPIO122__FUNC_B_GPIO122 (MTK_PIN_NO(122) | 0)
#define PINMUX_GPIO122__FUNC_B0_PCM_SYNC (MTK_PIN_NO(122) | 1)
#define PINMUX_GPIO122__FUNC_O_SPIM4_CLK (MTK_PIN_NO(122) | 2)
#define PINMUX_GPIO122__FUNC_O_SCP_SPI1_B_CK (MTK_PIN_NO(122) | 3)
#define PINMUX_GPIO122__FUNC_I1_TP_URXD2_AO (MTK_PIN_NO(122) | 4)
#define PINMUX_GPIO122__FUNC_O_AUXIF_CLK0 (MTK_PIN_NO(122) | 5)
#define PINMUX_GPIO122__FUNC_O_PGD_DA_EFUSE_RDY_PRE (MTK_PIN_NO(122) | 6)
#define PINMUX_GPIO122__FUNC_B0_DBG_MON_B24 (MTK_PIN_NO(122) | 7)
#define PINMUX_GPIO123__FUNC_B_GPIO123 (MTK_PIN_NO(123) | 0)
#define PINMUX_GPIO123__FUNC_O_PCM_DO (MTK_PIN_NO(123) | 1)
#define PINMUX_GPIO123__FUNC_B0_SPIM4_MOSI (MTK_PIN_NO(123) | 2)
#define PINMUX_GPIO123__FUNC_O_SCP_SPI1_B_MO (MTK_PIN_NO(123) | 3)
#define PINMUX_GPIO123__FUNC_O_TP_URTS2_AO (MTK_PIN_NO(123) | 4)
#define PINMUX_GPIO123__FUNC_O_AUXIF_ST1 (MTK_PIN_NO(123) | 5)
#define PINMUX_GPIO123__FUNC_O_PGD_DA_PWRGD_RESET (MTK_PIN_NO(123) | 6)
#define PINMUX_GPIO123__FUNC_B0_DBG_MON_B25 (MTK_PIN_NO(123) | 7)
#define PINMUX_GPIO124__FUNC_B_GPIO124 (MTK_PIN_NO(124) | 0)
#define PINMUX_GPIO124__FUNC_I0_PCM_DI (MTK_PIN_NO(124) | 1)
#define PINMUX_GPIO124__FUNC_B0_SPIM4_MISO (MTK_PIN_NO(124) | 2)
#define PINMUX_GPIO124__FUNC_I0_SCP_SPI1_B_MI (MTK_PIN_NO(124) | 3)
#define PINMUX_GPIO124__FUNC_I1_TP_UCTS2_AO (MTK_PIN_NO(124) | 4)
#define PINMUX_GPIO124__FUNC_O_AUXIF_CLK1 (MTK_PIN_NO(124) | 5)
#define PINMUX_GPIO124__FUNC_O_PGD_DA_PWRGD_ENB (MTK_PIN_NO(124) | 6)
#define PINMUX_GPIO124__FUNC_B0_DBG_MON_B26 (MTK_PIN_NO(124) | 7)
#define PINMUX_GPIO125__FUNC_B_GPIO125 (MTK_PIN_NO(125) | 0)
#define PINMUX_GPIO125__FUNC_O_DMIC1_CLK (MTK_PIN_NO(125) | 1)
#define PINMUX_GPIO125__FUNC_O_SPINOR_CK (MTK_PIN_NO(125) | 2)
#define PINMUX_GPIO125__FUNC_B0_TDMIN_MCK (MTK_PIN_NO(125) | 3)
#define PINMUX_GPIO125__FUNC_O_LVTS_FOUT (MTK_PIN_NO(125) | 6)
#define PINMUX_GPIO125__FUNC_B0_DBG_MON_B27 (MTK_PIN_NO(125) | 7)
#define PINMUX_GPIO126__FUNC_B_GPIO126 (MTK_PIN_NO(126) | 0)
#define PINMUX_GPIO126__FUNC_I0_DMIC1_DAT (MTK_PIN_NO(126) | 1)
#define PINMUX_GPIO126__FUNC_O_SPINOR_CS (MTK_PIN_NO(126) | 2)
#define PINMUX_GPIO126__FUNC_B0_TDMIN_BCK (MTK_PIN_NO(126) | 3)
#define PINMUX_GPIO126__FUNC_O_LVTS_SDO (MTK_PIN_NO(126) | 6)
#define PINMUX_GPIO126__FUNC_B0_DBG_MON_B28 (MTK_PIN_NO(126) | 7)
#define PINMUX_GPIO127__FUNC_B_GPIO127 (MTK_PIN_NO(127) | 0)
#define PINMUX_GPIO127__FUNC_I0_DMIC1_DAT_R (MTK_PIN_NO(127) | 1)
#define PINMUX_GPIO127__FUNC_B0_SPINOR_IO0 (MTK_PIN_NO(127) | 2)
#define PINMUX_GPIO127__FUNC_B0_TDMIN_LRCK (MTK_PIN_NO(127) | 3)
#define PINMUX_GPIO127__FUNC_I0_LVTS_26M (MTK_PIN_NO(127) | 6)
#define PINMUX_GPIO127__FUNC_B0_DBG_MON_B29 (MTK_PIN_NO(127) | 7)
#define PINMUX_GPIO128__FUNC_B_GPIO128 (MTK_PIN_NO(128) | 0)
#define PINMUX_GPIO128__FUNC_O_DMIC2_CLK (MTK_PIN_NO(128) | 1)
#define PINMUX_GPIO128__FUNC_B0_SPINOR_IO1 (MTK_PIN_NO(128) | 2)
#define PINMUX_GPIO128__FUNC_I0_TDMIN_DI (MTK_PIN_NO(128) | 3)
#define PINMUX_GPIO128__FUNC_I0_LVTS_SCF (MTK_PIN_NO(128) | 6)
#define PINMUX_GPIO128__FUNC_B0_DBG_MON_B30 (MTK_PIN_NO(128) | 7)
#define PINMUX_GPIO129__FUNC_B_GPIO129 (MTK_PIN_NO(129) | 0)
#define PINMUX_GPIO129__FUNC_I0_DMIC2_DAT (MTK_PIN_NO(129) | 1)
#define PINMUX_GPIO129__FUNC_B0_SPINOR_IO2 (MTK_PIN_NO(129) | 2)
#define PINMUX_GPIO129__FUNC_I0_SPDIF_IN1 (MTK_PIN_NO(129) | 3)
#define PINMUX_GPIO129__FUNC_I0_LVTS_SCK (MTK_PIN_NO(129) | 6)
#define PINMUX_GPIO129__FUNC_B0_DBG_MON_B31 (MTK_PIN_NO(129) | 7)
#define PINMUX_GPIO130__FUNC_B_GPIO130 (MTK_PIN_NO(130) | 0)
#define PINMUX_GPIO130__FUNC_I0_DMIC2_DAT_R (MTK_PIN_NO(130) | 1)
#define PINMUX_GPIO130__FUNC_B0_SPINOR_IO3 (MTK_PIN_NO(130) | 2)
#define PINMUX_GPIO130__FUNC_I0_SPDIF_IN2 (MTK_PIN_NO(130) | 3)
#define PINMUX_GPIO130__FUNC_I0_LVTS_SDI (MTK_PIN_NO(130) | 6)
#define PINMUX_GPIO130__FUNC_B0_DBG_MON_B32 (MTK_PIN_NO(130) | 7)
#define PINMUX_GPIO131__FUNC_B_GPIO131 (MTK_PIN_NO(131) | 0)
#define PINMUX_GPIO131__FUNC_O_DPI_D0 (MTK_PIN_NO(131) | 1)
#define PINMUX_GPIO131__FUNC_O_GBE_TXD3 (MTK_PIN_NO(131) | 2)
#define PINMUX_GPIO131__FUNC_O_DMIC1_CLK (MTK_PIN_NO(131) | 3)
#define PINMUX_GPIO131__FUNC_O_I2SO2_MCK (MTK_PIN_NO(131) | 4)
#define PINMUX_GPIO131__FUNC_B0_TP_GPIO0_AO (MTK_PIN_NO(131) | 5)
#define PINMUX_GPIO131__FUNC_O_SPIM5_CSB (MTK_PIN_NO(131) | 6)
#define PINMUX_GPIO131__FUNC_O_PGD_LV_HSC_PWR0 (MTK_PIN_NO(131) | 7)
#define PINMUX_GPIO132__FUNC_B_GPIO132 (MTK_PIN_NO(132) | 0)
#define PINMUX_GPIO132__FUNC_O_DPI_D1 (MTK_PIN_NO(132) | 1)
#define PINMUX_GPIO132__FUNC_O_GBE_TXD2 (MTK_PIN_NO(132) | 2)
#define PINMUX_GPIO132__FUNC_I0_DMIC1_DAT (MTK_PIN_NO(132) | 3)
#define PINMUX_GPIO132__FUNC_B0_I2SO2_BCK (MTK_PIN_NO(132) | 4)
#define PINMUX_GPIO132__FUNC_B0_TP_GPIO1_AO (MTK_PIN_NO(132) | 5)
#define PINMUX_GPIO132__FUNC_O_SPIM5_CLK (MTK_PIN_NO(132) | 6)
#define PINMUX_GPIO132__FUNC_O_PGD_LV_HSC_PWR1 (MTK_PIN_NO(132) | 7)
#define PINMUX_GPIO133__FUNC_B_GPIO133 (MTK_PIN_NO(133) | 0)
#define PINMUX_GPIO133__FUNC_O_DPI_D2 (MTK_PIN_NO(133) | 1)
#define PINMUX_GPIO133__FUNC_O_GBE_TXD1 (MTK_PIN_NO(133) | 2)
#define PINMUX_GPIO133__FUNC_I0_DMIC1_DAT_R (MTK_PIN_NO(133) | 3)
#define PINMUX_GPIO133__FUNC_B0_I2SO2_WS (MTK_PIN_NO(133) | 4)
#define PINMUX_GPIO133__FUNC_B0_TP_GPIO2_AO (MTK_PIN_NO(133) | 5)
#define PINMUX_GPIO133__FUNC_B0_SPIM5_MOSI (MTK_PIN_NO(133) | 6)
#define PINMUX_GPIO133__FUNC_O_PGD_LV_HSC_PWR2 (MTK_PIN_NO(133) | 7)
#define PINMUX_GPIO134__FUNC_B_GPIO134 (MTK_PIN_NO(134) | 0)
#define PINMUX_GPIO134__FUNC_O_DPI_D3 (MTK_PIN_NO(134) | 1)
#define PINMUX_GPIO134__FUNC_O_GBE_TXD0 (MTK_PIN_NO(134) | 2)
#define PINMUX_GPIO134__FUNC_O_DMIC2_CLK (MTK_PIN_NO(134) | 3)
#define PINMUX_GPIO134__FUNC_O_I2SO2_D0 (MTK_PIN_NO(134) | 4)
#define PINMUX_GPIO134__FUNC_B0_TP_GPIO3_AO (MTK_PIN_NO(134) | 5)
#define PINMUX_GPIO134__FUNC_B0_SPIM5_MISO (MTK_PIN_NO(134) | 6)
#define PINMUX_GPIO134__FUNC_O_PGD_LV_HSC_PWR3 (MTK_PIN_NO(134) | 7)
#define PINMUX_GPIO135__FUNC_B_GPIO135 (MTK_PIN_NO(135) | 0)
#define PINMUX_GPIO135__FUNC_O_DPI_D4 (MTK_PIN_NO(135) | 1)
#define PINMUX_GPIO135__FUNC_I0_GBE_RXD3 (MTK_PIN_NO(135) | 2)
#define PINMUX_GPIO135__FUNC_I0_DMIC2_DAT (MTK_PIN_NO(135) | 3)
#define PINMUX_GPIO135__FUNC_O_I2SO2_D1 (MTK_PIN_NO(135) | 4)
#define PINMUX_GPIO135__FUNC_B0_TP_GPIO4_AO (MTK_PIN_NO(135) | 5)
#define PINMUX_GPIO135__FUNC_I1_WAKEN (MTK_PIN_NO(135) | 6)
#define PINMUX_GPIO135__FUNC_O_PGD_LV_HSC_PWR4 (MTK_PIN_NO(135) | 7)
#define PINMUX_GPIO136__FUNC_B_GPIO136 (MTK_PIN_NO(136) | 0)
#define PINMUX_GPIO136__FUNC_O_DPI_D5 (MTK_PIN_NO(136) | 1)
#define PINMUX_GPIO136__FUNC_I0_GBE_RXD2 (MTK_PIN_NO(136) | 2)
#define PINMUX_GPIO136__FUNC_I0_DMIC2_DAT_R (MTK_PIN_NO(136) | 3)
#define PINMUX_GPIO136__FUNC_O_I2SO2_D2 (MTK_PIN_NO(136) | 4)
#define PINMUX_GPIO136__FUNC_B0_TP_GPIO5_AO (MTK_PIN_NO(136) | 5)
#define PINMUX_GPIO136__FUNC_O_PERSTN (MTK_PIN_NO(136) | 6)
#define PINMUX_GPIO136__FUNC_O_PGD_LV_HSC_PWR5 (MTK_PIN_NO(136) | 7)
#define PINMUX_GPIO137__FUNC_B_GPIO137 (MTK_PIN_NO(137) | 0)
#define PINMUX_GPIO137__FUNC_O_DPI_D6 (MTK_PIN_NO(137) | 1)
#define PINMUX_GPIO137__FUNC_I0_GBE_RXD1 (MTK_PIN_NO(137) | 2)
#define PINMUX_GPIO137__FUNC_O_DMIC3_CLK (MTK_PIN_NO(137) | 3)
#define PINMUX_GPIO137__FUNC_O_I2SO2_D3 (MTK_PIN_NO(137) | 4)
#define PINMUX_GPIO137__FUNC_B0_TP_GPIO6_AO (MTK_PIN_NO(137) | 5)
#define PINMUX_GPIO137__FUNC_B1_CLKREQN (MTK_PIN_NO(137) | 6)
#define PINMUX_GPIO137__FUNC_O_PWM_0 (MTK_PIN_NO(137) | 7)
#define PINMUX_GPIO138__FUNC_B_GPIO138 (MTK_PIN_NO(138) | 0)
#define PINMUX_GPIO138__FUNC_O_DPI_D7 (MTK_PIN_NO(138) | 1)
#define PINMUX_GPIO138__FUNC_I0_GBE_RXD0 (MTK_PIN_NO(138) | 2)
#define PINMUX_GPIO138__FUNC_I0_DMIC3_DAT (MTK_PIN_NO(138) | 3)
#define PINMUX_GPIO138__FUNC_O_CLKM2 (MTK_PIN_NO(138) | 4)
#define PINMUX_GPIO138__FUNC_B0_TP_GPIO7_AO (MTK_PIN_NO(138) | 5)
#define PINMUX_GPIO138__FUNC_B0_MD32_0_GPIO0 (MTK_PIN_NO(138) | 7)
#define PINMUX_GPIO139__FUNC_B_GPIO139 (MTK_PIN_NO(139) | 0)
#define PINMUX_GPIO139__FUNC_O_DPI_D8 (MTK_PIN_NO(139) | 1)
#define PINMUX_GPIO139__FUNC_B0_GBE_TXC (MTK_PIN_NO(139) | 2)
#define PINMUX_GPIO139__FUNC_I0_DMIC3_DAT_R (MTK_PIN_NO(139) | 3)
#define PINMUX_GPIO139__FUNC_O_CLKM3 (MTK_PIN_NO(139) | 4)
#define PINMUX_GPIO139__FUNC_O_TP_UTXD2_AO (MTK_PIN_NO(139) | 5)
#define PINMUX_GPIO139__FUNC_O_UTXD2 (MTK_PIN_NO(139) | 6)
#define PINMUX_GPIO139__FUNC_B0_MD32_0_GPIO1 (MTK_PIN_NO(139) | 7)
#define PINMUX_GPIO140__FUNC_B_GPIO140 (MTK_PIN_NO(140) | 0)
#define PINMUX_GPIO140__FUNC_O_DPI_D9 (MTK_PIN_NO(140) | 1)
#define PINMUX_GPIO140__FUNC_I0_GBE_RXC (MTK_PIN_NO(140) | 2)
#define PINMUX_GPIO140__FUNC_O_DMIC4_CLK (MTK_PIN_NO(140) | 3)
#define PINMUX_GPIO140__FUNC_O_PWM_2 (MTK_PIN_NO(140) | 4)
#define PINMUX_GPIO140__FUNC_I1_TP_URXD2_AO (MTK_PIN_NO(140) | 5)
#define PINMUX_GPIO140__FUNC_I1_URXD2 (MTK_PIN_NO(140) | 6)
#define PINMUX_GPIO140__FUNC_B0_MD32_0_GPIO2 (MTK_PIN_NO(140) | 7)
#define PINMUX_GPIO141__FUNC_B_GPIO141 (MTK_PIN_NO(141) | 0)
#define PINMUX_GPIO141__FUNC_O_DPI_D10 (MTK_PIN_NO(141) | 1)
#define PINMUX_GPIO141__FUNC_I0_GBE_RXDV (MTK_PIN_NO(141) | 2)
#define PINMUX_GPIO141__FUNC_I0_DMIC4_DAT (MTK_PIN_NO(141) | 3)
#define PINMUX_GPIO141__FUNC_O_PWM_3 (MTK_PIN_NO(141) | 4)
#define PINMUX_GPIO141__FUNC_O_TP_URTS2_AO (MTK_PIN_NO(141) | 5)
#define PINMUX_GPIO141__FUNC_O_URTS2 (MTK_PIN_NO(141) | 6)
#define PINMUX_GPIO141__FUNC_B0_MD32_1_GPIO0 (MTK_PIN_NO(141) | 7)
#define PINMUX_GPIO142__FUNC_B_GPIO142 (MTK_PIN_NO(142) | 0)
#define PINMUX_GPIO142__FUNC_O_DPI_D11 (MTK_PIN_NO(142) | 1)
#define PINMUX_GPIO142__FUNC_O_GBE_TXEN (MTK_PIN_NO(142) | 2)
#define PINMUX_GPIO142__FUNC_I0_DMIC4_DAT_R (MTK_PIN_NO(142) | 3)
#define PINMUX_GPIO142__FUNC_O_PWM_1 (MTK_PIN_NO(142) | 4)
#define PINMUX_GPIO142__FUNC_I1_TP_UCTS2_AO (MTK_PIN_NO(142) | 5)
#define PINMUX_GPIO142__FUNC_I1_UCTS2 (MTK_PIN_NO(142) | 6)
#define PINMUX_GPIO142__FUNC_B0_MD32_1_GPIO1 (MTK_PIN_NO(142) | 7)
#define PINMUX_GPIO143__FUNC_B_GPIO143 (MTK_PIN_NO(143) | 0)
#define PINMUX_GPIO143__FUNC_O_DPI_D12 (MTK_PIN_NO(143) | 1)
#define PINMUX_GPIO143__FUNC_O_GBE_MDC (MTK_PIN_NO(143) | 2)
#define PINMUX_GPIO143__FUNC_B0_MD32_0_GPIO0 (MTK_PIN_NO(143) | 3)
#define PINMUX_GPIO143__FUNC_O_CLKM0 (MTK_PIN_NO(143) | 4)
#define PINMUX_GPIO143__FUNC_O_SPIM3_CSB (MTK_PIN_NO(143) | 5)
#define PINMUX_GPIO143__FUNC_O_UTXD1 (MTK_PIN_NO(143) | 6)
#define PINMUX_GPIO143__FUNC_B0_MD32_1_GPIO2 (MTK_PIN_NO(143) | 7)
#define PINMUX_GPIO144__FUNC_B_GPIO144 (MTK_PIN_NO(144) | 0)
#define PINMUX_GPIO144__FUNC_O_DPI_D13 (MTK_PIN_NO(144) | 1)
#define PINMUX_GPIO144__FUNC_B1_GBE_MDIO (MTK_PIN_NO(144) | 2)
#define PINMUX_GPIO144__FUNC_B0_MD32_0_GPIO1 (MTK_PIN_NO(144) | 3)
#define PINMUX_GPIO144__FUNC_O_CLKM1 (MTK_PIN_NO(144) | 4)
#define PINMUX_GPIO144__FUNC_O_SPIM3_CLK (MTK_PIN_NO(144) | 5)
#define PINMUX_GPIO144__FUNC_I1_URXD1 (MTK_PIN_NO(144) | 6)
#define PINMUX_GPIO144__FUNC_O_PGD_HV_HSC_PWR0 (MTK_PIN_NO(144) | 7)
#define PINMUX_GPIO145__FUNC_B_GPIO145 (MTK_PIN_NO(145) | 0)
#define PINMUX_GPIO145__FUNC_O_DPI_D14 (MTK_PIN_NO(145) | 1)
#define PINMUX_GPIO145__FUNC_O_GBE_TXER (MTK_PIN_NO(145) | 2)
#define PINMUX_GPIO145__FUNC_B0_MD32_1_GPIO0 (MTK_PIN_NO(145) | 3)
#define PINMUX_GPIO145__FUNC_O_CMFLASH0 (MTK_PIN_NO(145) | 4)
#define PINMUX_GPIO145__FUNC_B0_SPIM3_MOSI (MTK_PIN_NO(145) | 5)
#define PINMUX_GPIO145__FUNC_B0_GBE_AUX_PPS2 (MTK_PIN_NO(145) | 6)
#define PINMUX_GPIO145__FUNC_O_PGD_HV_HSC_PWR1 (MTK_PIN_NO(145) | 7)
#define PINMUX_GPIO146__FUNC_B_GPIO146 (MTK_PIN_NO(146) | 0)
#define PINMUX_GPIO146__FUNC_O_DPI_D15 (MTK_PIN_NO(146) | 1)
#define PINMUX_GPIO146__FUNC_I0_GBE_RXER (MTK_PIN_NO(146) | 2)
#define PINMUX_GPIO146__FUNC_B0_MD32_1_GPIO1 (MTK_PIN_NO(146) | 3)
#define PINMUX_GPIO146__FUNC_O_CMFLASH1 (MTK_PIN_NO(146) | 4)
#define PINMUX_GPIO146__FUNC_B0_SPIM3_MISO (MTK_PIN_NO(146) | 5)
#define PINMUX_GPIO146__FUNC_B0_GBE_AUX_PPS3 (MTK_PIN_NO(146) | 6)
#define PINMUX_GPIO146__FUNC_O_PGD_HV_HSC_PWR2 (MTK_PIN_NO(146) | 7)
#define PINMUX_GPIO147__FUNC_B_GPIO147 (MTK_PIN_NO(147) | 0)
#define PINMUX_GPIO147__FUNC_O_DPI_HSYNC (MTK_PIN_NO(147) | 1)
#define PINMUX_GPIO147__FUNC_I0_GBE_COL (MTK_PIN_NO(147) | 2)
#define PINMUX_GPIO147__FUNC_O_I2SO1_MCK (MTK_PIN_NO(147) | 3)
#define PINMUX_GPIO147__FUNC_O_CMVREF0 (MTK_PIN_NO(147) | 4)
#define PINMUX_GPIO147__FUNC_O_SPDIF_OUT (MTK_PIN_NO(147) | 5)
#define PINMUX_GPIO147__FUNC_O_URTS1 (MTK_PIN_NO(147) | 6)
#define PINMUX_GPIO147__FUNC_O_PGD_HV_HSC_PWR3 (MTK_PIN_NO(147) | 7)
#define PINMUX_GPIO148__FUNC_B_GPIO148 (MTK_PIN_NO(148) | 0)
#define PINMUX_GPIO148__FUNC_O_DPI_VSYNC (MTK_PIN_NO(148) | 1)
#define PINMUX_GPIO148__FUNC_I0_GBE_INTR (MTK_PIN_NO(148) | 2)
#define PINMUX_GPIO148__FUNC_O_I2SO1_BCK (MTK_PIN_NO(148) | 3)
#define PINMUX_GPIO148__FUNC_O_CMVREF1 (MTK_PIN_NO(148) | 4)
#define PINMUX_GPIO148__FUNC_I0_SPDIF_IN0 (MTK_PIN_NO(148) | 5)
#define PINMUX_GPIO148__FUNC_I1_UCTS1 (MTK_PIN_NO(148) | 6)
#define PINMUX_GPIO148__FUNC_O_PGD_HV_HSC_PWR4 (MTK_PIN_NO(148) | 7)
#define PINMUX_GPIO149__FUNC_B_GPIO149 (MTK_PIN_NO(149) | 0)
#define PINMUX_GPIO149__FUNC_O_DPI_DE (MTK_PIN_NO(149) | 1)
#define PINMUX_GPIO149__FUNC_B0_GBE_AUX_PPS0 (MTK_PIN_NO(149) | 2)
#define PINMUX_GPIO149__FUNC_O_I2SO1_WS (MTK_PIN_NO(149) | 3)
#define PINMUX_GPIO149__FUNC_O_CMVREF2 (MTK_PIN_NO(149) | 4)
#define PINMUX_GPIO149__FUNC_I0_SPDIF_IN1 (MTK_PIN_NO(149) | 5)
#define PINMUX_GPIO149__FUNC_O_UTXD3 (MTK_PIN_NO(149) | 6)
#define PINMUX_GPIO149__FUNC_O_PGD_HV_HSC_PWR5 (MTK_PIN_NO(149) | 7)
#define PINMUX_GPIO150__FUNC_B_GPIO150 (MTK_PIN_NO(150) | 0)
#define PINMUX_GPIO150__FUNC_O_DPI_CK (MTK_PIN_NO(150) | 1)
#define PINMUX_GPIO150__FUNC_B0_GBE_AUX_PPS1 (MTK_PIN_NO(150) | 2)
#define PINMUX_GPIO150__FUNC_O_I2SO1_D0 (MTK_PIN_NO(150) | 3)
#define PINMUX_GPIO150__FUNC_O_CMVREF3 (MTK_PIN_NO(150) | 4)
#define PINMUX_GPIO150__FUNC_I0_SPDIF_IN2 (MTK_PIN_NO(150) | 5)
#define PINMUX_GPIO150__FUNC_I1_URXD3 (MTK_PIN_NO(150) | 6)
#define PINMUX_GPIO151__FUNC_B_GPIO151 (MTK_PIN_NO(151) | 0)
#define PINMUX_GPIO151__FUNC_B1_MSDC0_DAT7 (MTK_PIN_NO(151) | 1)
#define PINMUX_GPIO152__FUNC_B_GPIO152 (MTK_PIN_NO(152) | 0)
#define PINMUX_GPIO152__FUNC_B1_MSDC0_DAT6 (MTK_PIN_NO(152) | 1)
#define PINMUX_GPIO153__FUNC_B_GPIO153 (MTK_PIN_NO(153) | 0)
#define PINMUX_GPIO153__FUNC_B1_MSDC0_DAT5 (MTK_PIN_NO(153) | 1)
#define PINMUX_GPIO154__FUNC_B_GPIO154 (MTK_PIN_NO(154) | 0)
#define PINMUX_GPIO154__FUNC_B1_MSDC0_DAT4 (MTK_PIN_NO(154) | 1)
#define PINMUX_GPIO155__FUNC_B_GPIO155 (MTK_PIN_NO(155) | 0)
#define PINMUX_GPIO155__FUNC_O_MSDC0_RSTB (MTK_PIN_NO(155) | 1)
#define PINMUX_GPIO156__FUNC_B_GPIO156 (MTK_PIN_NO(156) | 0)
#define PINMUX_GPIO156__FUNC_B1_MSDC0_CMD (MTK_PIN_NO(156) | 1)
#define PINMUX_GPIO157__FUNC_B_GPIO157 (MTK_PIN_NO(157) | 0)
#define PINMUX_GPIO157__FUNC_B1_MSDC0_CLK (MTK_PIN_NO(157) | 1)
#define PINMUX_GPIO158__FUNC_B_GPIO158 (MTK_PIN_NO(158) | 0)
#define PINMUX_GPIO158__FUNC_B1_MSDC0_DAT3 (MTK_PIN_NO(158) | 1)
#define PINMUX_GPIO159__FUNC_B_GPIO159 (MTK_PIN_NO(159) | 0)
#define PINMUX_GPIO159__FUNC_B1_MSDC0_DAT2 (MTK_PIN_NO(159) | 1)
#define PINMUX_GPIO160__FUNC_B_GPIO160 (MTK_PIN_NO(160) | 0)
#define PINMUX_GPIO160__FUNC_B1_MSDC0_DAT1 (MTK_PIN_NO(160) | 1)
#define PINMUX_GPIO161__FUNC_B_GPIO161 (MTK_PIN_NO(161) | 0)
#define PINMUX_GPIO161__FUNC_B1_MSDC0_DAT0 (MTK_PIN_NO(161) | 1)
#define PINMUX_GPIO162__FUNC_B_GPIO162 (MTK_PIN_NO(162) | 0)
#define PINMUX_GPIO162__FUNC_B0_MSDC0_DSL (MTK_PIN_NO(162) | 1)
#define PINMUX_GPIO163__FUNC_B_GPIO163 (MTK_PIN_NO(163) | 0)
#define PINMUX_GPIO163__FUNC_B1_MSDC1_CMD (MTK_PIN_NO(163) | 1)
#define PINMUX_GPIO163__FUNC_O_SPDIF_OUT (MTK_PIN_NO(163) | 2)
#define PINMUX_GPIO163__FUNC_I1_MD32_0_JTAG_TMS (MTK_PIN_NO(163) | 3)
#define PINMUX_GPIO163__FUNC_I1_ADSP_JTAG0_TMS (MTK_PIN_NO(163) | 4)
#define PINMUX_GPIO163__FUNC_I1_SCP_JTAG0_TMS (MTK_PIN_NO(163) | 5)
#define PINMUX_GPIO163__FUNC_I1_CCU0_JTAG_TMS (MTK_PIN_NO(163) | 6)
#define PINMUX_GPIO163__FUNC_I0_IPU_JTAG_TMS (MTK_PIN_NO(163) | 7)
#define PINMUX_GPIO164__FUNC_B_GPIO164 (MTK_PIN_NO(164) | 0)
#define PINMUX_GPIO164__FUNC_B1_MSDC1_CLK (MTK_PIN_NO(164) | 1)
#define PINMUX_GPIO164__FUNC_I0_SPDIF_IN0 (MTK_PIN_NO(164) | 2)
#define PINMUX_GPIO164__FUNC_I1_MD32_0_JTAG_TCK (MTK_PIN_NO(164) | 3)
#define PINMUX_GPIO164__FUNC_I0_ADSP_JTAG0_TCK (MTK_PIN_NO(164) | 4)
#define PINMUX_GPIO164__FUNC_I1_SCP_JTAG0_TCK (MTK_PIN_NO(164) | 5)
#define PINMUX_GPIO164__FUNC_I1_CCU0_JTAG_TCK (MTK_PIN_NO(164) | 6)
#define PINMUX_GPIO164__FUNC_I0_IPU_JTAG_TCK (MTK_PIN_NO(164) | 7)
#define PINMUX_GPIO165__FUNC_B_GPIO165 (MTK_PIN_NO(165) | 0)
#define PINMUX_GPIO165__FUNC_B1_MSDC1_DAT0 (MTK_PIN_NO(165) | 1)
#define PINMUX_GPIO165__FUNC_I0_SPDIF_IN1 (MTK_PIN_NO(165) | 2)
#define PINMUX_GPIO165__FUNC_I1_MD32_0_JTAG_TDI (MTK_PIN_NO(165) | 3)
#define PINMUX_GPIO165__FUNC_I1_ADSP_JTAG0_TDI (MTK_PIN_NO(165) | 4)
#define PINMUX_GPIO165__FUNC_I1_SCP_JTAG0_TDI (MTK_PIN_NO(165) | 5)
#define PINMUX_GPIO165__FUNC_I1_CCU0_JTAG_TDI (MTK_PIN_NO(165) | 6)
#define PINMUX_GPIO165__FUNC_I0_IPU_JTAG_TDI (MTK_PIN_NO(165) | 7)
#define PINMUX_GPIO166__FUNC_B_GPIO166 (MTK_PIN_NO(166) | 0)
#define PINMUX_GPIO166__FUNC_B1_MSDC1_DAT1 (MTK_PIN_NO(166) | 1)
#define PINMUX_GPIO166__FUNC_I0_SPDIF_IN2 (MTK_PIN_NO(166) | 2)
#define PINMUX_GPIO166__FUNC_O_MD32_0_JTAG_TDO (MTK_PIN_NO(166) | 3)
#define PINMUX_GPIO166__FUNC_O_ADSP_JTAG0_TDO (MTK_PIN_NO(166) | 4)
#define PINMUX_GPIO166__FUNC_O_SCP_JTAG0_TDO (MTK_PIN_NO(166) | 5)
#define PINMUX_GPIO166__FUNC_O_CCU0_JTAG_TDO (MTK_PIN_NO(166) | 6)
#define PINMUX_GPIO166__FUNC_O_IPU_JTAG_TDO (MTK_PIN_NO(166) | 7)
#define PINMUX_GPIO167__FUNC_B_GPIO167 (MTK_PIN_NO(167) | 0)
#define PINMUX_GPIO167__FUNC_B1_MSDC1_DAT2 (MTK_PIN_NO(167) | 1)
#define PINMUX_GPIO167__FUNC_O_PWM_0 (MTK_PIN_NO(167) | 2)
#define PINMUX_GPIO167__FUNC_I1_MD32_0_JTAG_TRST (MTK_PIN_NO(167) | 3)
#define PINMUX_GPIO167__FUNC_I1_ADSP_JTAG0_TRSTN (MTK_PIN_NO(167) | 4)
#define PINMUX_GPIO167__FUNC_I0_SCP_JTAG0_TRSTN (MTK_PIN_NO(167) | 5)
#define PINMUX_GPIO167__FUNC_I1_CCU0_JTAG_TRST (MTK_PIN_NO(167) | 6)
#define PINMUX_GPIO167__FUNC_I0_IPU_JTAG_TRST (MTK_PIN_NO(167) | 7)
#define PINMUX_GPIO168__FUNC_B_GPIO168 (MTK_PIN_NO(168) | 0)
#define PINMUX_GPIO168__FUNC_B1_MSDC1_DAT3 (MTK_PIN_NO(168) | 1)
#define PINMUX_GPIO168__FUNC_O_PWM_1 (MTK_PIN_NO(168) | 2)
#define PINMUX_GPIO168__FUNC_O_CLKM0 (MTK_PIN_NO(168) | 3)
#define PINMUX_GPIO169__FUNC_B_GPIO169 (MTK_PIN_NO(169) | 0)
#define PINMUX_GPIO169__FUNC_B1_MSDC2_CMD (MTK_PIN_NO(169) | 1)
#define PINMUX_GPIO169__FUNC_O_LVTS_FOUT (MTK_PIN_NO(169) | 2)
#define PINMUX_GPIO169__FUNC_I1_MD32_1_JTAG_TMS (MTK_PIN_NO(169) | 3)
#define PINMUX_GPIO169__FUNC_I0_UDI_TMS (MTK_PIN_NO(169) | 4)
#define PINMUX_GPIO169__FUNC_I0_VPU_UDI_TMS (MTK_PIN_NO(169) | 5)
#define PINMUX_GPIO169__FUNC_B0_TDMIN_MCK (MTK_PIN_NO(169) | 6)
#define PINMUX_GPIO169__FUNC_I1_SSPM_JTAG_TMS (MTK_PIN_NO(169) | 7)
#define PINMUX_GPIO170__FUNC_B_GPIO170 (MTK_PIN_NO(170) | 0)
#define PINMUX_GPIO170__FUNC_B1_MSDC2_CLK (MTK_PIN_NO(170) | 1)
#define PINMUX_GPIO170__FUNC_O_LVTS_SDO (MTK_PIN_NO(170) | 2)
#define PINMUX_GPIO170__FUNC_I1_MD32_1_JTAG_TCK (MTK_PIN_NO(170) | 3)
#define PINMUX_GPIO170__FUNC_I0_UDI_TCK (MTK_PIN_NO(170) | 4)
#define PINMUX_GPIO170__FUNC_I0_VPU_UDI_TCK (MTK_PIN_NO(170) | 5)
#define PINMUX_GPIO170__FUNC_B0_TDMIN_BCK (MTK_PIN_NO(170) | 6)
#define PINMUX_GPIO170__FUNC_I1_SSPM_JTAG_TCK (MTK_PIN_NO(170) | 7)
#define PINMUX_GPIO171__FUNC_B_GPIO171 (MTK_PIN_NO(171) | 0)
#define PINMUX_GPIO171__FUNC_B1_MSDC2_DAT0 (MTK_PIN_NO(171) | 1)
#define PINMUX_GPIO171__FUNC_I0_LVTS_26M (MTK_PIN_NO(171) | 2)
#define PINMUX_GPIO171__FUNC_I1_MD32_1_JTAG_TDI (MTK_PIN_NO(171) | 3)
#define PINMUX_GPIO171__FUNC_I0_UDI_TDI (MTK_PIN_NO(171) | 4)
#define PINMUX_GPIO171__FUNC_I0_VPU_UDI_TDI (MTK_PIN_NO(171) | 5)
#define PINMUX_GPIO171__FUNC_B0_TDMIN_LRCK (MTK_PIN_NO(171) | 6)
#define PINMUX_GPIO171__FUNC_I1_SSPM_JTAG_TDI (MTK_PIN_NO(171) | 7)
#define PINMUX_GPIO172__FUNC_B_GPIO172 (MTK_PIN_NO(172) | 0)
#define PINMUX_GPIO172__FUNC_B1_MSDC2_DAT1 (MTK_PIN_NO(172) | 1)
#define PINMUX_GPIO172__FUNC_I0_LVTS_SCF (MTK_PIN_NO(172) | 2)
#define PINMUX_GPIO172__FUNC_O_MD32_1_JTAG_TDO (MTK_PIN_NO(172) | 3)
#define PINMUX_GPIO172__FUNC_O_UDI_TDO (MTK_PIN_NO(172) | 4)
#define PINMUX_GPIO172__FUNC_O_VPU_UDI_TDO (MTK_PIN_NO(172) | 5)
#define PINMUX_GPIO172__FUNC_I0_TDMIN_DI (MTK_PIN_NO(172) | 6)
#define PINMUX_GPIO172__FUNC_O_SSPM_JTAG_TDO (MTK_PIN_NO(172) | 7)
#define PINMUX_GPIO173__FUNC_B_GPIO173 (MTK_PIN_NO(173) | 0)
#define PINMUX_GPIO173__FUNC_B1_MSDC2_DAT2 (MTK_PIN_NO(173) | 1)
#define PINMUX_GPIO173__FUNC_I0_LVTS_SCK (MTK_PIN_NO(173) | 2)
#define PINMUX_GPIO173__FUNC_I1_MD32_1_JTAG_TRST (MTK_PIN_NO(173) | 3)
#define PINMUX_GPIO173__FUNC_I0_UDI_NTRST (MTK_PIN_NO(173) | 4)
#define PINMUX_GPIO173__FUNC_I0_VPU_UDI_NTRST (MTK_PIN_NO(173) | 5)
#define PINMUX_GPIO173__FUNC_I0_SSPM_JTAG_TRSTN (MTK_PIN_NO(173) | 7)
#define PINMUX_GPIO174__FUNC_B_GPIO174 (MTK_PIN_NO(174) | 0)
#define PINMUX_GPIO174__FUNC_B1_MSDC2_DAT3 (MTK_PIN_NO(174) | 1)
#define PINMUX_GPIO174__FUNC_I0_LVTS_SDI (MTK_PIN_NO(174) | 2)
#define PINMUX_GPIO175__FUNC_B_GPIO175 (MTK_PIN_NO(175) | 0)
#define PINMUX_GPIO175__FUNC_B0_SPMI_M_SCL (MTK_PIN_NO(175) | 1)
#define PINMUX_GPIO176__FUNC_B_GPIO176 (MTK_PIN_NO(176) | 0)
#define PINMUX_GPIO176__FUNC_B0_SPMI_M_SDA (MTK_PIN_NO(176) | 1)
#endif /* __MEDIATEK_MT8188-PINFUNC_H */
|
// SPDX-License-Identifier: GPL-2.0
/******************************************************************************
*
* Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved.
*
******************************************************************************/
#include <drv_types.h>
#include <rtl8723b_hal.h>
static u8 rtw_sdio_wait_enough_TxOQT_space(struct adapter *padapter, u8 agg_num)
{
u32 n = 0;
struct hal_com_data *pHalData = GET_HAL_DATA(padapter);
while (pHalData->SdioTxOQTFreeSpace < agg_num) {
if (
(padapter->bSurpriseRemoved) ||
(padapter->bDriverStopped)
)
return false;
HalQueryTxOQTBufferStatus8723BSdio(padapter);
if ((++n % 60) == 0) {
msleep(1);
/* yield(); */
}
}
pHalData->SdioTxOQTFreeSpace -= agg_num;
return true;
}
static s32 rtl8723_dequeue_writeport(struct adapter *padapter)
{
struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
struct xmit_priv *pxmitpriv = &padapter->xmitpriv;
struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter);
struct xmit_buf *pxmitbuf;
struct adapter *pri_padapter = padapter;
s32 ret = 0;
u8 PageIdx = 0;
u32 deviceId;
u8 bUpdatePageNum = false;
ret = ret || check_fwstate(pmlmepriv, _FW_UNDER_SURVEY);
if (ret)
pxmitbuf = dequeue_pending_xmitbuf_under_survey(pxmitpriv);
else
pxmitbuf = dequeue_pending_xmitbuf(pxmitpriv);
if (!pxmitbuf)
return true;
deviceId = ffaddr2deviceId(pdvobjpriv, pxmitbuf->ff_hwaddr);
/* translate fifo addr to queue index */
switch (deviceId) {
case WLAN_TX_HIQ_DEVICE_ID:
PageIdx = HI_QUEUE_IDX;
break;
case WLAN_TX_MIQ_DEVICE_ID:
PageIdx = MID_QUEUE_IDX;
break;
case WLAN_TX_LOQ_DEVICE_ID:
PageIdx = LOW_QUEUE_IDX;
break;
}
query_free_page:
/* check if hardware tx fifo page is enough */
if (!rtw_hal_sdio_query_tx_freepage(pri_padapter, PageIdx, pxmitbuf->pg_num)) {
if (!bUpdatePageNum) {
/* Total number of page is NOT available, so update current FIFO status */
HalQueryTxBufferStatus8723BSdio(padapter);
bUpdatePageNum = true;
goto query_free_page;
} else {
bUpdatePageNum = false;
enqueue_pending_xmitbuf_to_head(pxmitpriv, pxmitbuf);
return true;
}
}
if (
(padapter->bSurpriseRemoved) ||
(padapter->bDriverStopped)
)
goto free_xmitbuf;
if (rtw_sdio_wait_enough_TxOQT_space(padapter, pxmitbuf->agg_num) == false)
goto free_xmitbuf;
traffic_check_for_leave_lps(padapter, true, pxmitbuf->agg_num);
rtw_write_port(padapter, deviceId, pxmitbuf->len, (u8 *)pxmitbuf);
rtw_hal_sdio_update_tx_freepage(pri_padapter, PageIdx, pxmitbuf->pg_num);
free_xmitbuf:
/* rtw_free_xmitframe(pxmitpriv, pframe); */
/* pxmitbuf->priv_data = NULL; */
rtw_free_xmitbuf(pxmitpriv, pxmitbuf);
return _FAIL;
}
/*
* Description
*Transmit xmitbuf to hardware tx fifo
*
* Return
*_SUCCESS ok
*_FAIL something error
*/
s32 rtl8723bs_xmit_buf_handler(struct adapter *padapter)
{
struct xmit_priv *pxmitpriv;
u8 queue_empty, queue_pending;
s32 ret;
pxmitpriv = &padapter->xmitpriv;
if (wait_for_completion_interruptible(&pxmitpriv->xmit_comp)) {
netdev_emerg(padapter->pnetdev,
"%s: down SdioXmitBufSema fail!\n", __func__);
return _FAIL;
}
ret = (padapter->bDriverStopped) || (padapter->bSurpriseRemoved);
if (ret)
return _FAIL;
queue_pending = check_pending_xmitbuf(pxmitpriv);
if (!queue_pending)
return _SUCCESS;
ret = rtw_register_tx_alive(padapter);
if (ret != _SUCCESS) {
return _SUCCESS;
}
do {
queue_empty = rtl8723_dequeue_writeport(padapter);
/* dump secondary adapter xmitbuf */
} while (!queue_empty);
rtw_unregister_tx_alive(padapter);
return _SUCCESS;
}
/*
* Description:
*Aggregation packets and send to hardware
*
* Return:
*0 Success
*-1 Hardware resource(TX FIFO) not ready
*-2 Software resource(xmitbuf) not ready
*/
static s32 xmit_xmitframes(struct adapter *padapter, struct xmit_priv *pxmitpriv)
{
s32 err, ret;
u32 k = 0;
struct hw_xmit *hwxmits, *phwxmit;
u8 idx, hwentry;
struct tx_servq *ptxservq;
struct list_head *sta_plist, *sta_phead, *frame_plist, *frame_phead, *tmp;
struct xmit_frame *pxmitframe;
struct __queue *pframe_queue;
struct xmit_buf *pxmitbuf;
u32 txlen, max_xmit_len;
u8 txdesc_size = TXDESC_SIZE;
int inx[4];
err = 0;
hwxmits = pxmitpriv->hwxmits;
hwentry = pxmitpriv->hwxmit_entry;
ptxservq = NULL;
pxmitframe = NULL;
pframe_queue = NULL;
pxmitbuf = NULL;
if (padapter->registrypriv.wifi_spec == 1) {
for (idx = 0; idx < 4; idx++)
inx[idx] = pxmitpriv->wmm_para_seq[idx];
} else {
inx[0] = 0;
inx[1] = 1;
inx[2] = 2;
inx[3] = 3;
}
/* 0(VO), 1(VI), 2(BE), 3(BK) */
for (idx = 0; idx < hwentry; idx++) {
phwxmit = hwxmits + inx[idx];
if (
(check_pending_xmitbuf(pxmitpriv)) &&
(padapter->mlmepriv.LinkDetectInfo.bHigherBusyTxTraffic)
) {
if ((phwxmit->accnt > 0) && (phwxmit->accnt < 5)) {
err = -2;
break;
}
}
max_xmit_len = rtw_hal_get_sdio_tx_max_length(padapter, inx[idx]);
spin_lock_bh(&pxmitpriv->lock);
sta_phead = get_list_head(phwxmit->sta_queue);
/* because stop_sta_xmit may delete sta_plist at any time */
/* so we should add lock here, or while loop can not exit */
list_for_each_safe(sta_plist, tmp, sta_phead) {
ptxservq = list_entry(sta_plist, struct tx_servq,
tx_pending);
pframe_queue = &ptxservq->sta_pending;
frame_phead = get_list_head(pframe_queue);
while (list_empty(frame_phead) == false) {
frame_plist = get_next(frame_phead);
pxmitframe = container_of(frame_plist, struct xmit_frame, list);
/* check xmit_buf size enough or not */
txlen = txdesc_size + rtw_wlan_pkt_size(pxmitframe);
if (!pxmitbuf ||
((_RND(pxmitbuf->len, 8) + txlen) > max_xmit_len) ||
(k >= (rtw_hal_sdio_max_txoqt_free_space(padapter) - 1))
) {
if (pxmitbuf) {
/* pxmitbuf->priv_data will be NULL, and will crash here */
if (pxmitbuf->len > 0 &&
pxmitbuf->priv_data) {
struct xmit_frame *pframe;
pframe = (struct xmit_frame *)pxmitbuf->priv_data;
pframe->agg_num = k;
pxmitbuf->agg_num = k;
rtl8723b_update_txdesc(pframe, pframe->buf_addr);
rtw_free_xmitframe(pxmitpriv, pframe);
pxmitbuf->priv_data = NULL;
enqueue_pending_xmitbuf(pxmitpriv, pxmitbuf);
/* can not yield under lock */
/* yield(); */
} else
rtw_free_xmitbuf(pxmitpriv, pxmitbuf);
}
pxmitbuf = rtw_alloc_xmitbuf(pxmitpriv);
if (!pxmitbuf) {
#ifdef DBG_XMIT_BUF
netdev_err(padapter->pnetdev,
"%s: xmit_buf is not enough!\n",
__func__);
#endif
err = -2;
complete(&(pxmitpriv->xmit_comp));
break;
}
k = 0;
}
/* ok to send, remove frame from queue */
if (check_fwstate(&padapter->mlmepriv, WIFI_AP_STATE) == true)
if (
(pxmitframe->attrib.psta->state & WIFI_SLEEP_STATE) &&
(pxmitframe->attrib.triggered == 0)
)
break;
list_del_init(&pxmitframe->list);
ptxservq->qcnt--;
phwxmit->accnt--;
if (k == 0) {
pxmitbuf->ff_hwaddr = rtw_get_ff_hwaddr(pxmitframe);
pxmitbuf->priv_data = (u8 *)pxmitframe;
}
/* coalesce the xmitframe to xmitbuf */
pxmitframe->pxmitbuf = pxmitbuf;
pxmitframe->buf_addr = pxmitbuf->ptail;
ret = rtw_xmitframe_coalesce(padapter, pxmitframe->pkt, pxmitframe);
if (ret == _FAIL) {
netdev_err(padapter->pnetdev,
"%s: coalesce FAIL!",
__func__);
/* Todo: error handler */
} else {
k++;
if (k != 1)
rtl8723b_update_txdesc(pxmitframe, pxmitframe->buf_addr);
rtw_count_tx_stats(padapter, pxmitframe, pxmitframe->attrib.last_txcmdsz);
txlen = txdesc_size + pxmitframe->attrib.last_txcmdsz;
pxmitframe->pg_num = (txlen + 127) / 128;
pxmitbuf->pg_num += (txlen + 127) / 128;
pxmitbuf->ptail += _RND(txlen, 8); /* round to 8 bytes alignment */
pxmitbuf->len = _RND(pxmitbuf->len, 8) + txlen;
}
if (k != 1)
rtw_free_xmitframe(pxmitpriv, pxmitframe);
pxmitframe = NULL;
}
if (list_empty(&pframe_queue->queue))
list_del_init(&ptxservq->tx_pending);
if (err)
break;
}
spin_unlock_bh(&pxmitpriv->lock);
/* dump xmit_buf to hw tx fifo */
if (pxmitbuf) {
if (pxmitbuf->len > 0) {
struct xmit_frame *pframe;
pframe = (struct xmit_frame *)pxmitbuf->priv_data;
pframe->agg_num = k;
pxmitbuf->agg_num = k;
rtl8723b_update_txdesc(pframe, pframe->buf_addr);
rtw_free_xmitframe(pxmitpriv, pframe);
pxmitbuf->priv_data = NULL;
enqueue_pending_xmitbuf(pxmitpriv, pxmitbuf);
yield();
} else
rtw_free_xmitbuf(pxmitpriv, pxmitbuf);
pxmitbuf = NULL;
}
if (err)
break;
}
return err;
}
/*
* Description
*Transmit xmitframe from queue
*
* Return
*_SUCCESS ok
*_FAIL something error
*/
static s32 rtl8723bs_xmit_handler(struct adapter *padapter)
{
struct xmit_priv *pxmitpriv;
s32 ret;
pxmitpriv = &padapter->xmitpriv;
if (wait_for_completion_interruptible(&pxmitpriv->SdioXmitStart)) {
netdev_emerg(padapter->pnetdev, "%s: SdioXmitStart fail!\n",
__func__);
return _FAIL;
}
next:
if (
(padapter->bDriverStopped) ||
(padapter->bSurpriseRemoved)
)
return _FAIL;
spin_lock_bh(&pxmitpriv->lock);
ret = rtw_txframes_pending(padapter);
spin_unlock_bh(&pxmitpriv->lock);
if (ret == 0) {
return _SUCCESS;
}
/* dequeue frame and write to hardware */
ret = xmit_xmitframes(padapter, pxmitpriv);
if (ret == -2) {
/* here sleep 1ms will cause big TP loss of TX */
/* from 50+ to 40+ */
if (padapter->registrypriv.wifi_spec)
msleep(1);
else
yield();
goto next;
}
spin_lock_bh(&pxmitpriv->lock);
ret = rtw_txframes_pending(padapter);
spin_unlock_bh(&pxmitpriv->lock);
if (ret == 1) {
goto next;
}
return _SUCCESS;
}
int rtl8723bs_xmit_thread(void *context)
{
s32 ret;
struct adapter *padapter;
struct xmit_priv *pxmitpriv;
ret = _SUCCESS;
padapter = context;
pxmitpriv = &padapter->xmitpriv;
allow_signal(SIGTERM);
do {
ret = rtl8723bs_xmit_handler(padapter);
if (signal_pending(current)) {
flush_signals(current);
}
} while (_SUCCESS == ret);
complete(&pxmitpriv->SdioXmitTerminate);
return 0;
}
s32 rtl8723bs_mgnt_xmit(
struct adapter *padapter, struct xmit_frame *pmgntframe
)
{
s32 ret = _SUCCESS;
struct pkt_attrib *pattrib;
struct xmit_buf *pxmitbuf;
struct xmit_priv *pxmitpriv = &padapter->xmitpriv;
struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter);
u8 *pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET;
u8 txdesc_size = TXDESC_SIZE;
pattrib = &pmgntframe->attrib;
pxmitbuf = pmgntframe->pxmitbuf;
rtl8723b_update_txdesc(pmgntframe, pmgntframe->buf_addr);
pxmitbuf->len = txdesc_size + pattrib->last_txcmdsz;
pxmitbuf->pg_num = (pxmitbuf->len + 127) / 128; /* 128 is tx page size */
pxmitbuf->ptail = pmgntframe->buf_addr + pxmitbuf->len;
pxmitbuf->ff_hwaddr = rtw_get_ff_hwaddr(pmgntframe);
rtw_count_tx_stats(padapter, pmgntframe, pattrib->last_txcmdsz);
rtw_free_xmitframe(pxmitpriv, pmgntframe);
pxmitbuf->priv_data = NULL;
if (GetFrameSubType(pframe) == WIFI_BEACON) { /* dump beacon directly */
ret = rtw_write_port(padapter, pdvobjpriv->Queue2Pipe[pxmitbuf->ff_hwaddr], pxmitbuf->len, (u8 *)pxmitbuf);
if (ret != _SUCCESS)
rtw_sctx_done_err(&pxmitbuf->sctx, RTW_SCTX_DONE_WRITE_PORT_ERR);
rtw_free_xmitbuf(pxmitpriv, pxmitbuf);
} else
enqueue_pending_xmitbuf(pxmitpriv, pxmitbuf);
return ret;
}
/*
* Description:
*Handle xmitframe(packet) come from rtw_xmit()
*
* Return:
*true dump packet directly ok
*false enqueue, temporary can't transmit packets to hardware
*/
s32 rtl8723bs_hal_xmit(
struct adapter *padapter, struct xmit_frame *pxmitframe
)
{
struct xmit_priv *pxmitpriv;
s32 err;
pxmitframe->attrib.qsel = pxmitframe->attrib.priority;
pxmitpriv = &padapter->xmitpriv;
if (
(pxmitframe->frame_tag == DATA_FRAMETAG) &&
(pxmitframe->attrib.ether_type != 0x0806) &&
(pxmitframe->attrib.ether_type != 0x888e) &&
(pxmitframe->attrib.dhcp_pkt != 1)
) {
if (padapter->mlmepriv.LinkDetectInfo.bBusyTraffic)
rtw_issue_addbareq_cmd(padapter, pxmitframe);
}
spin_lock_bh(&pxmitpriv->lock);
err = rtw_xmitframe_enqueue(padapter, pxmitframe);
spin_unlock_bh(&pxmitpriv->lock);
if (err != _SUCCESS) {
rtw_free_xmitframe(pxmitpriv, pxmitframe);
pxmitpriv->tx_drop++;
return true;
}
complete(&pxmitpriv->SdioXmitStart);
return false;
}
s32 rtl8723bs_hal_xmitframe_enqueue(
struct adapter *padapter, struct xmit_frame *pxmitframe
)
{
struct xmit_priv *pxmitpriv = &padapter->xmitpriv;
s32 err;
err = rtw_xmitframe_enqueue(padapter, pxmitframe);
if (err != _SUCCESS) {
rtw_free_xmitframe(pxmitpriv, pxmitframe);
pxmitpriv->tx_drop++;
} else {
complete(&pxmitpriv->SdioXmitStart);
}
return err;
}
/*
* Return
*_SUCCESS start thread ok
*_FAIL start thread fail
*
*/
s32 rtl8723bs_init_xmit_priv(struct adapter *padapter)
{
struct xmit_priv *xmitpriv = &padapter->xmitpriv;
struct hal_com_data *phal;
phal = GET_HAL_DATA(padapter);
spin_lock_init(&phal->SdioTxFIFOFreePageLock);
init_completion(&xmitpriv->SdioXmitStart);
init_completion(&xmitpriv->SdioXmitTerminate);
return _SUCCESS;
}
void rtl8723bs_free_xmit_priv(struct adapter *padapter)
{
struct xmit_priv *pxmitpriv;
struct xmit_buf *pxmitbuf;
struct __queue *pqueue;
struct list_head *plist, *phead;
struct list_head tmplist;
pxmitpriv = &padapter->xmitpriv;
pqueue = &pxmitpriv->pending_xmitbuf_queue;
phead = get_list_head(pqueue);
INIT_LIST_HEAD(&tmplist);
spin_lock_bh(&pqueue->lock);
if (!list_empty(&pqueue->queue)) {
/* Insert tmplist to end of queue, and delete phead */
/* then tmplist become head of queue. */
list_add_tail(&tmplist, phead);
list_del_init(phead);
}
spin_unlock_bh(&pqueue->lock);
phead = &tmplist;
while (list_empty(phead) == false) {
plist = get_next(phead);
list_del_init(plist);
pxmitbuf = container_of(plist, struct xmit_buf, list);
rtw_free_xmitframe(pxmitpriv, (struct xmit_frame *)pxmitbuf->priv_data);
pxmitbuf->priv_data = NULL;
rtw_free_xmitbuf(pxmitpriv, pxmitbuf);
}
}
|
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2023, Linaro Limited
*/
#ifndef QCOM_PHY_QMP_PCS_SGMII_H_
#define QCOM_PHY_QMP_PCS_SGMII_H_
#define QPHY_PCS_PHY_START 0x000
#define QPHY_PCS_POWER_DOWN_CONTROL 0x004
#define QPHY_PCS_SW_RESET 0x008
#define QPHY_PCS_LINE_RESET_TIME 0x00c
#define QPHY_PCS_TX_LARGE_AMP_DRV_LVL 0x020
#define QPHY_PCS_TX_SMALL_AMP_DRV_LVL 0x028
#define QPHY_PCS_PCS_READY_STATUS 0x094
#define QPHY_PCS_TX_MID_TERM_CTRL1 0x0d8
#define QPHY_PCS_TX_MID_TERM_CTRL2 0x0dc
#define QPHY_PCS_SGMII_MISC_CTRL8 0x118
#endif
|
/*
* Copyright 2016 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
*/
#ifndef __MMHUB_V1_0_H__
#define __MMHUB_V1_0_H__
extern const struct amdgpu_mmhub_funcs mmhub_v1_0_funcs;
extern struct amdgpu_mmhub_ras mmhub_v1_0_ras;
#endif
|
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2017 SiFive
*/
#include <linux/acpi.h>
#include <linux/of.h>
#include <linux/prctl.h>
#include <asm/acpi.h>
#include <asm/cacheflush.h>
#ifdef CONFIG_SMP
#include <asm/sbi.h>
static void ipi_remote_fence_i(void *info)
{
return local_flush_icache_all();
}
void flush_icache_all(void)
{
local_flush_icache_all();
if (num_online_cpus() < 2)
return;
else if (riscv_use_sbi_for_rfence())
sbi_remote_fence_i(NULL);
else
on_each_cpu(ipi_remote_fence_i, NULL, 1);
}
EXPORT_SYMBOL(flush_icache_all);
/*
* Performs an icache flush for the given MM context. RISC-V has no direct
* mechanism for instruction cache shoot downs, so instead we send an IPI that
* informs the remote harts they need to flush their local instruction caches.
* To avoid pathologically slow behavior in a common case (a bunch of
* single-hart processes on a many-hart machine, ie 'make -j') we avoid the
* IPIs for harts that are not currently executing a MM context and instead
* schedule a deferred local instruction cache flush to be performed before
* execution resumes on each hart.
*/
void flush_icache_mm(struct mm_struct *mm, bool local)
{
unsigned int cpu;
cpumask_t others, *mask;
preempt_disable();
/* Mark every hart's icache as needing a flush for this MM. */
mask = &mm->context.icache_stale_mask;
cpumask_setall(mask);
/* Flush this hart's I$ now, and mark it as flushed. */
cpu = smp_processor_id();
cpumask_clear_cpu(cpu, mask);
local_flush_icache_all();
/*
* Flush the I$ of other harts concurrently executing, and mark them as
* flushed.
*/
cpumask_andnot(&others, mm_cpumask(mm), cpumask_of(cpu));
local |= cpumask_empty(&others);
if (mm == current->active_mm && local) {
/*
* It's assumed that at least one strongly ordered operation is
* performed on this hart between setting a hart's cpumask bit
* and scheduling this MM context on that hart. Sending an SBI
* remote message will do this, but in the case where no
* messages are sent we still need to order this hart's writes
* with flush_icache_deferred().
*/
smp_mb();
} else if (riscv_use_sbi_for_rfence()) {
sbi_remote_fence_i(&others);
} else {
on_each_cpu_mask(&others, ipi_remote_fence_i, NULL, 1);
}
preempt_enable();
}
#endif /* CONFIG_SMP */
#ifdef CONFIG_MMU
void flush_icache_pte(struct mm_struct *mm, pte_t pte)
{
struct folio *folio = page_folio(pte_page(pte));
if (!test_bit(PG_dcache_clean, &folio->flags)) {
flush_icache_mm(mm, false);
set_bit(PG_dcache_clean, &folio->flags);
}
}
#endif /* CONFIG_MMU */
unsigned int riscv_cbom_block_size;
EXPORT_SYMBOL_GPL(riscv_cbom_block_size);
unsigned int riscv_cboz_block_size;
EXPORT_SYMBOL_GPL(riscv_cboz_block_size);
static void __init cbo_get_block_size(struct device_node *node,
const char *name, u32 *block_size,
unsigned long *first_hartid)
{
unsigned long hartid;
u32 val;
if (riscv_of_processor_hartid(node, &hartid))
return;
if (of_property_read_u32(node, name, &val))
return;
if (!*block_size) {
*block_size = val;
*first_hartid = hartid;
} else if (*block_size != val) {
pr_warn("%s mismatched between harts %lu and %lu\n",
name, *first_hartid, hartid);
}
}
void __init riscv_init_cbo_blocksizes(void)
{
unsigned long cbom_hartid, cboz_hartid;
u32 cbom_block_size = 0, cboz_block_size = 0;
struct device_node *node;
struct acpi_table_header *rhct;
acpi_status status;
if (acpi_disabled) {
for_each_of_cpu_node(node) {
/* set block-size for cbom and/or cboz extension if available */
cbo_get_block_size(node, "riscv,cbom-block-size",
&cbom_block_size, &cbom_hartid);
cbo_get_block_size(node, "riscv,cboz-block-size",
&cboz_block_size, &cboz_hartid);
}
} else {
status = acpi_get_table(ACPI_SIG_RHCT, 0, &rhct);
if (ACPI_FAILURE(status))
return;
acpi_get_cbo_block_size(rhct, &cbom_block_size, &cboz_block_size, NULL);
acpi_put_table((struct acpi_table_header *)rhct);
}
if (cbom_block_size)
riscv_cbom_block_size = cbom_block_size;
if (cboz_block_size)
riscv_cboz_block_size = cboz_block_size;
}
#ifdef CONFIG_SMP
static void set_icache_stale_mask(void)
{
int cpu = get_cpu();
cpumask_t *mask;
bool stale_cpu;
/*
* Mark every other hart's icache as needing a flush for
* this MM. Maintain the previous value of the current
* cpu to handle the case when this function is called
* concurrently on different harts.
*/
mask = ¤t->mm->context.icache_stale_mask;
stale_cpu = cpumask_test_cpu(cpu, mask);
cpumask_setall(mask);
cpumask_assign_cpu(cpu, mask, stale_cpu);
put_cpu();
}
#endif
/**
* riscv_set_icache_flush_ctx() - Enable/disable icache flushing instructions in
* userspace.
* @ctx: Set the type of icache flushing instructions permitted/prohibited in
* userspace. Supported values described below.
*
* Supported values for ctx:
*
* * %PR_RISCV_CTX_SW_FENCEI_ON: Allow fence.i in user space.
*
* * %PR_RISCV_CTX_SW_FENCEI_OFF: Disallow fence.i in user space. All threads in
* a process will be affected when ``scope == PR_RISCV_SCOPE_PER_PROCESS``.
* Therefore, caution must be taken; use this flag only when you can guarantee
* that no thread in the process will emit fence.i from this point onward.
*
* @scope: Set scope of where icache flushing instructions are allowed to be
* emitted. Supported values described below.
*
* Supported values for scope:
*
* * %PR_RISCV_SCOPE_PER_PROCESS: Ensure the icache of any thread in this process
* is coherent with instruction storage upon
* migration.
*
* * %PR_RISCV_SCOPE_PER_THREAD: Ensure the icache of the current thread is
* coherent with instruction storage upon
* migration.
*
* When ``scope == PR_RISCV_SCOPE_PER_PROCESS``, all threads in the process are
* permitted to emit icache flushing instructions. Whenever any thread in the
* process is migrated, the corresponding hart's icache will be guaranteed to be
* consistent with instruction storage. This does not enforce any guarantees
* outside of migration. If a thread modifies an instruction that another thread
* may attempt to execute, the other thread must still emit an icache flushing
* instruction before attempting to execute the potentially modified
* instruction. This must be performed by the user-space program.
*
* In per-thread context (eg. ``scope == PR_RISCV_SCOPE_PER_THREAD``) only the
* thread calling this function is permitted to emit icache flushing
* instructions. When the thread is migrated, the corresponding hart's icache
* will be guaranteed to be consistent with instruction storage.
*
* On kernels configured without SMP, this function is a nop as migrations
* across harts will not occur.
*/
int riscv_set_icache_flush_ctx(unsigned long ctx, unsigned long scope)
{
#ifdef CONFIG_SMP
switch (ctx) {
case PR_RISCV_CTX_SW_FENCEI_ON:
switch (scope) {
case PR_RISCV_SCOPE_PER_PROCESS:
current->mm->context.force_icache_flush = true;
break;
case PR_RISCV_SCOPE_PER_THREAD:
current->thread.force_icache_flush = true;
break;
default:
return -EINVAL;
}
break;
case PR_RISCV_CTX_SW_FENCEI_OFF:
switch (scope) {
case PR_RISCV_SCOPE_PER_PROCESS:
set_icache_stale_mask();
current->mm->context.force_icache_flush = false;
break;
case PR_RISCV_SCOPE_PER_THREAD:
set_icache_stale_mask();
current->thread.force_icache_flush = false;
break;
default:
return -EINVAL;
}
break;
default:
return -EINVAL;
}
return 0;
#else
switch (ctx) {
case PR_RISCV_CTX_SW_FENCEI_ON:
case PR_RISCV_CTX_SW_FENCEI_OFF:
return 0;
default:
return -EINVAL;
}
#endif
}
|
// SPDX-License-Identifier: GPL-2.0-only
/* envctrl.c: Temperature and Fan monitoring on Machines providing it.
*
* Copyright (C) 1998 Eddie C. Dost ([email protected])
* Copyright (C) 2000 Vinh Truong ([email protected])
* VT - The implementation is to support Sun Microelectronics (SME) platform
* environment monitoring. SME platforms use pcf8584 as the i2c bus
* controller to access pcf8591 (8-bit A/D and D/A converter) and
* pcf8571 (256 x 8-bit static low-voltage RAM with I2C-bus interface).
* At board level, it follows SME Firmware I2C Specification. Reference:
* http://www-eu2.semiconductors.com/pip/PCF8584P
* http://www-eu2.semiconductors.com/pip/PCF8574AP
* http://www-eu2.semiconductors.com/pip/PCF8591P
*
* EB - Added support for CP1500 Global Address and PS/Voltage monitoring.
* Eric Brower <[email protected]>
*
* DB - Audit every copy_to_user in envctrl_read.
* Daniele Bellucci <[email protected]>
*/
#include <linux/module.h>
#include <linux/kthread.h>
#include <linux/delay.h>
#include <linux/ioport.h>
#include <linux/miscdevice.h>
#include <linux/kmod.h>
#include <linux/reboot.h>
#include <linux/slab.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/uaccess.h>
#include <asm/envctrl.h>
#include <asm/io.h>
#define DRIVER_NAME "envctrl"
#define PFX DRIVER_NAME ": "
#define PCF8584_ADDRESS 0x55
#define CONTROL_PIN 0x80
#define CONTROL_ES0 0x40
#define CONTROL_ES1 0x20
#define CONTROL_ES2 0x10
#define CONTROL_ENI 0x08
#define CONTROL_STA 0x04
#define CONTROL_STO 0x02
#define CONTROL_ACK 0x01
#define STATUS_PIN 0x80
#define STATUS_STS 0x20
#define STATUS_BER 0x10
#define STATUS_LRB 0x08
#define STATUS_AD0 0x08
#define STATUS_AAB 0x04
#define STATUS_LAB 0x02
#define STATUS_BB 0x01
/*
* CLK Mode Register.
*/
#define BUS_CLK_90 0x00
#define BUS_CLK_45 0x01
#define BUS_CLK_11 0x02
#define BUS_CLK_1_5 0x03
#define CLK_3 0x00
#define CLK_4_43 0x10
#define CLK_6 0x14
#define CLK_8 0x18
#define CLK_12 0x1c
#define OBD_SEND_START 0xc5 /* value to generate I2c_bus START condition */
#define OBD_SEND_STOP 0xc3 /* value to generate I2c_bus STOP condition */
/* Monitor type of i2c child device.
* Firmware definitions.
*/
#define PCF8584_MAX_CHANNELS 8
#define PCF8584_GLOBALADDR_TYPE 6 /* global address monitor */
#define PCF8584_FANSTAT_TYPE 3 /* fan status monitor */
#define PCF8584_VOLTAGE_TYPE 2 /* voltage monitor */
#define PCF8584_TEMP_TYPE 1 /* temperature monitor*/
/* Monitor type of i2c child device.
* Driver definitions.
*/
#define ENVCTRL_NOMON 0
#define ENVCTRL_CPUTEMP_MON 1 /* cpu temperature monitor */
#define ENVCTRL_CPUVOLTAGE_MON 2 /* voltage monitor */
#define ENVCTRL_FANSTAT_MON 3 /* fan status monitor */
#define ENVCTRL_ETHERTEMP_MON 4 /* ethernet temperature */
/* monitor */
#define ENVCTRL_VOLTAGESTAT_MON 5 /* voltage status monitor */
#define ENVCTRL_MTHRBDTEMP_MON 6 /* motherboard temperature */
#define ENVCTRL_SCSITEMP_MON 7 /* scsi temperature */
#define ENVCTRL_GLOBALADDR_MON 8 /* global address */
/* Child device type.
* Driver definitions.
*/
#define I2C_ADC 0 /* pcf8591 */
#define I2C_GPIO 1 /* pcf8571 */
/* Data read from child device may need to decode
* through a data table and a scale.
* Translation type as defined by firmware.
*/
#define ENVCTRL_TRANSLATE_NO 0
#define ENVCTRL_TRANSLATE_PARTIAL 1
#define ENVCTRL_TRANSLATE_COMBINED 2
#define ENVCTRL_TRANSLATE_FULL 3 /* table[data] */
#define ENVCTRL_TRANSLATE_SCALE 4 /* table[data]/scale */
/* Driver miscellaneous definitions. */
#define ENVCTRL_MAX_CPU 4
#define CHANNEL_DESC_SZ 256
/* Mask values for combined GlobalAddress/PowerStatus node */
#define ENVCTRL_GLOBALADDR_ADDR_MASK 0x1F
#define ENVCTRL_GLOBALADDR_PSTAT_MASK 0x60
/* Node 0x70 ignored on CompactPCI CP1400/1500 platforms
* (see envctrl_init_i2c_child)
*/
#define ENVCTRL_CPCI_IGNORED_NODE 0x70
#define PCF8584_DATA 0x00
#define PCF8584_CSR 0x01
/* Each child device can be monitored by up to PCF8584_MAX_CHANNELS.
* Property of a port or channel as defined by the firmware.
*/
struct pcf8584_channel {
unsigned char chnl_no;
unsigned char io_direction;
unsigned char type;
unsigned char last;
};
/* Each child device may have one or more tables of bytes to help decode
* data. Table property as defined by the firmware.
*/
struct pcf8584_tblprop {
unsigned int type;
unsigned int scale;
unsigned int offset; /* offset from the beginning of the table */
unsigned int size;
};
/* i2c child */
struct i2c_child_t {
/* Either ADC or GPIO. */
unsigned char i2ctype;
unsigned long addr;
struct pcf8584_channel chnl_array[PCF8584_MAX_CHANNELS];
/* Channel info. */
unsigned int total_chnls; /* Number of monitor channels. */
unsigned char fan_mask; /* Byte mask for fan status channels. */
unsigned char voltage_mask; /* Byte mask for voltage status channels. */
struct pcf8584_tblprop tblprop_array[PCF8584_MAX_CHANNELS];
/* Properties of all monitor channels. */
unsigned int total_tbls; /* Number of monitor tables. */
char *tables; /* Pointer to table(s). */
char chnls_desc[CHANNEL_DESC_SZ]; /* Channel description. */
char mon_type[PCF8584_MAX_CHANNELS];
};
static void __iomem *i2c;
static struct i2c_child_t i2c_childlist[ENVCTRL_MAX_CPU*2];
static unsigned char chnls_mask[] = { 0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80 };
static unsigned int warning_temperature = 0;
static unsigned int shutdown_temperature = 0;
static char read_cpu;
/* Forward declarations. */
static struct i2c_child_t *envctrl_get_i2c_child(unsigned char);
/* Function Description: Test the PIN bit (Pending Interrupt Not)
* to test when serial transmission is completed .
* Return : None.
*/
static void envtrl_i2c_test_pin(void)
{
int limit = 1000000;
while (--limit > 0) {
if (!(readb(i2c + PCF8584_CSR) & STATUS_PIN))
break;
udelay(1);
}
if (limit <= 0)
printk(KERN_INFO PFX "Pin status will not clear.\n");
}
/* Function Description: Test busy bit.
* Return : None.
*/
static void envctrl_i2c_test_bb(void)
{
int limit = 1000000;
while (--limit > 0) {
/* Busy bit 0 means busy. */
if (readb(i2c + PCF8584_CSR) & STATUS_BB)
break;
udelay(1);
}
if (limit <= 0)
printk(KERN_INFO PFX "Busy bit will not clear.\n");
}
/* Function Description: Send the address for a read access.
* Return : 0 if not acknowledged, otherwise acknowledged.
*/
static int envctrl_i2c_read_addr(unsigned char addr)
{
envctrl_i2c_test_bb();
/* Load address. */
writeb(addr + 1, i2c + PCF8584_DATA);
envctrl_i2c_test_bb();
writeb(OBD_SEND_START, i2c + PCF8584_CSR);
/* Wait for PIN. */
envtrl_i2c_test_pin();
/* CSR 0 means acknowledged. */
if (!(readb(i2c + PCF8584_CSR) & STATUS_LRB)) {
return readb(i2c + PCF8584_DATA);
} else {
writeb(OBD_SEND_STOP, i2c + PCF8584_CSR);
return 0;
}
}
/* Function Description: Send the address for write mode.
* Return : None.
*/
static void envctrl_i2c_write_addr(unsigned char addr)
{
envctrl_i2c_test_bb();
writeb(addr, i2c + PCF8584_DATA);
/* Generate Start condition. */
writeb(OBD_SEND_START, i2c + PCF8584_CSR);
}
/* Function Description: Read 1 byte of data from addr
* set by envctrl_i2c_read_addr()
* Return : Data from address set by envctrl_i2c_read_addr().
*/
static unsigned char envctrl_i2c_read_data(void)
{
envtrl_i2c_test_pin();
writeb(CONTROL_ES0, i2c + PCF8584_CSR); /* Send neg ack. */
return readb(i2c + PCF8584_DATA);
}
/* Function Description: Instruct the device which port to read data from.
* Return : None.
*/
static void envctrl_i2c_write_data(unsigned char port)
{
envtrl_i2c_test_pin();
writeb(port, i2c + PCF8584_DATA);
}
/* Function Description: Generate Stop condition after last byte is sent.
* Return : None.
*/
static void envctrl_i2c_stop(void)
{
envtrl_i2c_test_pin();
writeb(OBD_SEND_STOP, i2c + PCF8584_CSR);
}
/* Function Description: Read adc device.
* Return : Data at address and port.
*/
static unsigned char envctrl_i2c_read_8591(unsigned char addr, unsigned char port)
{
/* Send address. */
envctrl_i2c_write_addr(addr);
/* Setup port to read. */
envctrl_i2c_write_data(port);
envctrl_i2c_stop();
/* Read port. */
envctrl_i2c_read_addr(addr);
/* Do a single byte read and send stop. */
envctrl_i2c_read_data();
envctrl_i2c_stop();
return readb(i2c + PCF8584_DATA);
}
/* Function Description: Read gpio device.
* Return : Data at address.
*/
static unsigned char envctrl_i2c_read_8574(unsigned char addr)
{
unsigned char rd;
envctrl_i2c_read_addr(addr);
/* Do a single byte read and send stop. */
rd = envctrl_i2c_read_data();
envctrl_i2c_stop();
return rd;
}
/* Function Description: Decode data read from an adc device using firmware
* table.
* Return: Number of read bytes. Data is stored in bufdata in ascii format.
*/
static int envctrl_i2c_data_translate(unsigned char data, int translate_type,
int scale, char *tbl, char *bufdata)
{
int len = 0;
switch (translate_type) {
case ENVCTRL_TRANSLATE_NO:
/* No decode necessary. */
len = 1;
bufdata[0] = data;
break;
case ENVCTRL_TRANSLATE_FULL:
/* Decode this way: data = table[data]. */
len = 1;
bufdata[0] = tbl[data];
break;
case ENVCTRL_TRANSLATE_SCALE:
/* Decode this way: data = table[data]/scale */
sprintf(bufdata,"%d ", (tbl[data] * 10) / (scale));
len = strlen(bufdata);
bufdata[len - 1] = bufdata[len - 2];
bufdata[len - 2] = '.';
break;
default:
break;
}
return len;
}
/* Function Description: Read cpu-related data such as cpu temperature, voltage.
* Return: Number of read bytes. Data is stored in bufdata in ascii format.
*/
static int envctrl_read_cpu_info(int cpu, struct i2c_child_t *pchild,
char mon_type, unsigned char *bufdata)
{
unsigned char data;
int i, j = -1;
char *tbl;
/* Find the right monitor type and channel. */
for (i = 0; i < PCF8584_MAX_CHANNELS; i++) {
if (pchild->mon_type[i] == mon_type) {
if (++j == cpu) {
break;
}
}
}
if (j != cpu)
return 0;
/* Read data from address and port. */
data = envctrl_i2c_read_8591((unsigned char)pchild->addr,
(unsigned char)pchild->chnl_array[i].chnl_no);
/* Find decoding table. */
tbl = pchild->tables + pchild->tblprop_array[i].offset;
return envctrl_i2c_data_translate(data, pchild->tblprop_array[i].type,
pchild->tblprop_array[i].scale,
tbl, bufdata);
}
/* Function Description: Read noncpu-related data such as motherboard
* temperature.
* Return: Number of read bytes. Data is stored in bufdata in ascii format.
*/
static int envctrl_read_noncpu_info(struct i2c_child_t *pchild,
char mon_type, unsigned char *bufdata)
{
unsigned char data;
int i;
char *tbl = NULL;
for (i = 0; i < PCF8584_MAX_CHANNELS; i++) {
if (pchild->mon_type[i] == mon_type)
break;
}
if (i >= PCF8584_MAX_CHANNELS)
return 0;
/* Read data from address and port. */
data = envctrl_i2c_read_8591((unsigned char)pchild->addr,
(unsigned char)pchild->chnl_array[i].chnl_no);
/* Find decoding table. */
tbl = pchild->tables + pchild->tblprop_array[i].offset;
return envctrl_i2c_data_translate(data, pchild->tblprop_array[i].type,
pchild->tblprop_array[i].scale,
tbl, bufdata);
}
/* Function Description: Read fan status.
* Return : Always 1 byte. Status stored in bufdata.
*/
static int envctrl_i2c_fan_status(struct i2c_child_t *pchild,
unsigned char data,
char *bufdata)
{
unsigned char tmp, ret = 0;
int i, j = 0;
tmp = data & pchild->fan_mask;
if (tmp == pchild->fan_mask) {
/* All bits are on. All fans are functioning. */
ret = ENVCTRL_ALL_FANS_GOOD;
} else if (tmp == 0) {
/* No bits are on. No fans are functioning. */
ret = ENVCTRL_ALL_FANS_BAD;
} else {
/* Go through all channels, mark 'on' the matched bits.
* Notice that fan_mask may have discontiguous bits but
* return mask are always contiguous. For example if we
* monitor 4 fans at channels 0,1,2,4, the return mask
* should be 00010000 if only fan at channel 4 is working.
*/
for (i = 0; i < PCF8584_MAX_CHANNELS;i++) {
if (pchild->fan_mask & chnls_mask[i]) {
if (!(chnls_mask[i] & tmp))
ret |= chnls_mask[j];
j++;
}
}
}
bufdata[0] = ret;
return 1;
}
/* Function Description: Read global addressing line.
* Return : Always 1 byte. Status stored in bufdata.
*/
static int envctrl_i2c_globaladdr(struct i2c_child_t *pchild,
unsigned char data,
char *bufdata)
{
/* Translatation table is not necessary, as global
* addr is the integer value of the GA# bits.
*
* NOTE: MSB is documented as zero, but I see it as '1' always....
*
* -----------------------------------------------
* | 0 | FAL | DEG | GA4 | GA3 | GA2 | GA1 | GA0 |
* -----------------------------------------------
* GA0 - GA4 integer value of Global Address (backplane slot#)
* DEG 0 = cPCI Power supply output is starting to degrade
* 1 = cPCI Power supply output is OK
* FAL 0 = cPCI Power supply has failed
* 1 = cPCI Power supply output is OK
*/
bufdata[0] = (data & ENVCTRL_GLOBALADDR_ADDR_MASK);
return 1;
}
/* Function Description: Read standard voltage and power supply status.
* Return : Always 1 byte. Status stored in bufdata.
*/
static unsigned char envctrl_i2c_voltage_status(struct i2c_child_t *pchild,
unsigned char data,
char *bufdata)
{
unsigned char tmp, ret = 0;
int i, j = 0;
tmp = data & pchild->voltage_mask;
/* Two channels are used to monitor voltage and power supply. */
if (tmp == pchild->voltage_mask) {
/* All bits are on. Voltage and power supply are okay. */
ret = ENVCTRL_VOLTAGE_POWERSUPPLY_GOOD;
} else if (tmp == 0) {
/* All bits are off. Voltage and power supply are bad */
ret = ENVCTRL_VOLTAGE_POWERSUPPLY_BAD;
} else {
/* Either voltage or power supply has problem. */
for (i = 0; i < PCF8584_MAX_CHANNELS; i++) {
if (pchild->voltage_mask & chnls_mask[i]) {
j++;
/* Break out when there is a mismatch. */
if (!(chnls_mask[i] & tmp))
break;
}
}
/* Make a wish that hardware will always use the
* first channel for voltage and the second for
* power supply.
*/
if (j == 1)
ret = ENVCTRL_VOLTAGE_BAD;
else
ret = ENVCTRL_POWERSUPPLY_BAD;
}
bufdata[0] = ret;
return 1;
}
/* Function Description: Read a byte from /dev/envctrl. Mapped to user read().
* Return: Number of read bytes. 0 for error.
*/
static ssize_t
envctrl_read(struct file *file, char __user *buf, size_t count, loff_t *ppos)
{
struct i2c_child_t *pchild;
unsigned char data[10];
int ret = 0;
/* Get the type of read as decided in ioctl() call.
* Find the appropriate i2c child.
* Get the data and put back to the user buffer.
*/
switch ((int)(long)file->private_data) {
case ENVCTRL_RD_WARNING_TEMPERATURE:
if (warning_temperature == 0)
return 0;
data[0] = (unsigned char)(warning_temperature);
ret = 1;
if (copy_to_user(buf, data, ret))
ret = -EFAULT;
break;
case ENVCTRL_RD_SHUTDOWN_TEMPERATURE:
if (shutdown_temperature == 0)
return 0;
data[0] = (unsigned char)(shutdown_temperature);
ret = 1;
if (copy_to_user(buf, data, ret))
ret = -EFAULT;
break;
case ENVCTRL_RD_MTHRBD_TEMPERATURE:
if (!(pchild = envctrl_get_i2c_child(ENVCTRL_MTHRBDTEMP_MON)))
return 0;
ret = envctrl_read_noncpu_info(pchild, ENVCTRL_MTHRBDTEMP_MON, data);
if (copy_to_user(buf, data, ret))
ret = -EFAULT;
break;
case ENVCTRL_RD_CPU_TEMPERATURE:
if (!(pchild = envctrl_get_i2c_child(ENVCTRL_CPUTEMP_MON)))
return 0;
ret = envctrl_read_cpu_info(read_cpu, pchild, ENVCTRL_CPUTEMP_MON, data);
/* Reset cpu to the default cpu0. */
if (copy_to_user(buf, data, ret))
ret = -EFAULT;
break;
case ENVCTRL_RD_CPU_VOLTAGE:
if (!(pchild = envctrl_get_i2c_child(ENVCTRL_CPUVOLTAGE_MON)))
return 0;
ret = envctrl_read_cpu_info(read_cpu, pchild, ENVCTRL_CPUVOLTAGE_MON, data);
/* Reset cpu to the default cpu0. */
if (copy_to_user(buf, data, ret))
ret = -EFAULT;
break;
case ENVCTRL_RD_SCSI_TEMPERATURE:
if (!(pchild = envctrl_get_i2c_child(ENVCTRL_SCSITEMP_MON)))
return 0;
ret = envctrl_read_noncpu_info(pchild, ENVCTRL_SCSITEMP_MON, data);
if (copy_to_user(buf, data, ret))
ret = -EFAULT;
break;
case ENVCTRL_RD_ETHERNET_TEMPERATURE:
if (!(pchild = envctrl_get_i2c_child(ENVCTRL_ETHERTEMP_MON)))
return 0;
ret = envctrl_read_noncpu_info(pchild, ENVCTRL_ETHERTEMP_MON, data);
if (copy_to_user(buf, data, ret))
ret = -EFAULT;
break;
case ENVCTRL_RD_FAN_STATUS:
if (!(pchild = envctrl_get_i2c_child(ENVCTRL_FANSTAT_MON)))
return 0;
data[0] = envctrl_i2c_read_8574(pchild->addr);
ret = envctrl_i2c_fan_status(pchild,data[0], data);
if (copy_to_user(buf, data, ret))
ret = -EFAULT;
break;
case ENVCTRL_RD_GLOBALADDRESS:
if (!(pchild = envctrl_get_i2c_child(ENVCTRL_GLOBALADDR_MON)))
return 0;
data[0] = envctrl_i2c_read_8574(pchild->addr);
ret = envctrl_i2c_globaladdr(pchild, data[0], data);
if (copy_to_user(buf, data, ret))
ret = -EFAULT;
break;
case ENVCTRL_RD_VOLTAGE_STATUS:
if (!(pchild = envctrl_get_i2c_child(ENVCTRL_VOLTAGESTAT_MON)))
/* If voltage monitor not present, check for CPCI equivalent */
if (!(pchild = envctrl_get_i2c_child(ENVCTRL_GLOBALADDR_MON)))
return 0;
data[0] = envctrl_i2c_read_8574(pchild->addr);
ret = envctrl_i2c_voltage_status(pchild, data[0], data);
if (copy_to_user(buf, data, ret))
ret = -EFAULT;
break;
default:
break;
}
return ret;
}
/* Function Description: Command what to read. Mapped to user ioctl().
* Return: Gives 0 for implemented commands, -EINVAL otherwise.
*/
static long
envctrl_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
{
char __user *infobuf;
switch (cmd) {
case ENVCTRL_RD_WARNING_TEMPERATURE:
case ENVCTRL_RD_SHUTDOWN_TEMPERATURE:
case ENVCTRL_RD_MTHRBD_TEMPERATURE:
case ENVCTRL_RD_FAN_STATUS:
case ENVCTRL_RD_VOLTAGE_STATUS:
case ENVCTRL_RD_ETHERNET_TEMPERATURE:
case ENVCTRL_RD_SCSI_TEMPERATURE:
case ENVCTRL_RD_GLOBALADDRESS:
file->private_data = (void *)(long)cmd;
break;
case ENVCTRL_RD_CPU_TEMPERATURE:
case ENVCTRL_RD_CPU_VOLTAGE:
/* Check to see if application passes in any cpu number,
* the default is cpu0.
*/
infobuf = (char __user *) arg;
if (infobuf == NULL) {
read_cpu = 0;
}else {
get_user(read_cpu, infobuf);
}
/* Save the command for use when reading. */
file->private_data = (void *)(long)cmd;
break;
default:
return -EINVAL;
}
return 0;
}
/* Function Description: open device. Mapped to user open().
* Return: Always 0.
*/
static int
envctrl_open(struct inode *inode, struct file *file)
{
file->private_data = NULL;
return 0;
}
/* Function Description: Open device. Mapped to user close().
* Return: Always 0.
*/
static int
envctrl_release(struct inode *inode, struct file *file)
{
return 0;
}
static const struct file_operations envctrl_fops = {
.owner = THIS_MODULE,
.read = envctrl_read,
.unlocked_ioctl = envctrl_ioctl,
.compat_ioctl = compat_ptr_ioctl,
.open = envctrl_open,
.release = envctrl_release,
.llseek = noop_llseek,
};
static struct miscdevice envctrl_dev = {
ENVCTRL_MINOR,
"envctrl",
&envctrl_fops
};
/* Function Description: Set monitor type based on firmware description.
* Return: None.
*/
static void envctrl_set_mon(struct i2c_child_t *pchild,
const char *chnl_desc,
int chnl_no)
{
/* Firmware only has temperature type. It does not distinguish
* different kinds of temperatures. We use channel description
* to disinguish them.
*/
if (!(strcmp(chnl_desc,"temp,cpu")) ||
!(strcmp(chnl_desc,"temp,cpu0")) ||
!(strcmp(chnl_desc,"temp,cpu1")) ||
!(strcmp(chnl_desc,"temp,cpu2")) ||
!(strcmp(chnl_desc,"temp,cpu3")))
pchild->mon_type[chnl_no] = ENVCTRL_CPUTEMP_MON;
if (!(strcmp(chnl_desc,"vddcore,cpu0")) ||
!(strcmp(chnl_desc,"vddcore,cpu1")) ||
!(strcmp(chnl_desc,"vddcore,cpu2")) ||
!(strcmp(chnl_desc,"vddcore,cpu3")))
pchild->mon_type[chnl_no] = ENVCTRL_CPUVOLTAGE_MON;
if (!(strcmp(chnl_desc,"temp,motherboard")))
pchild->mon_type[chnl_no] = ENVCTRL_MTHRBDTEMP_MON;
if (!(strcmp(chnl_desc,"temp,scsi")))
pchild->mon_type[chnl_no] = ENVCTRL_SCSITEMP_MON;
if (!(strcmp(chnl_desc,"temp,ethernet")))
pchild->mon_type[chnl_no] = ENVCTRL_ETHERTEMP_MON;
}
/* Function Description: Initialize monitor channel with channel desc,
* decoding tables, monitor type, optional properties.
* Return: None.
*/
static void envctrl_init_adc(struct i2c_child_t *pchild, struct device_node *dp)
{
int i = 0, len;
const char *pos;
const unsigned int *pval;
/* Firmware describe channels into a stream separated by a '\0'. */
pos = of_get_property(dp, "channels-description", &len);
while (len > 0) {
int l = strlen(pos) + 1;
envctrl_set_mon(pchild, pos, i++);
len -= l;
pos += l;
}
/* Get optional properties. */
pval = of_get_property(dp, "warning-temp", NULL);
if (pval)
warning_temperature = *pval;
pval = of_get_property(dp, "shutdown-temp", NULL);
if (pval)
shutdown_temperature = *pval;
}
/* Function Description: Initialize child device monitoring fan status.
* Return: None.
*/
static void envctrl_init_fanstat(struct i2c_child_t *pchild)
{
int i;
/* Go through all channels and set up the mask. */
for (i = 0; i < pchild->total_chnls; i++)
pchild->fan_mask |= chnls_mask[(pchild->chnl_array[i]).chnl_no];
/* We only need to know if this child has fan status monitored.
* We don't care which channels since we have the mask already.
*/
pchild->mon_type[0] = ENVCTRL_FANSTAT_MON;
}
/* Function Description: Initialize child device for global addressing line.
* Return: None.
*/
static void envctrl_init_globaladdr(struct i2c_child_t *pchild)
{
int i;
/* Voltage/PowerSupply monitoring is piggybacked
* with Global Address on CompactPCI. See comments
* within envctrl_i2c_globaladdr for bit assignments.
*
* The mask is created here by assigning mask bits to each
* bit position that represents PCF8584_VOLTAGE_TYPE data.
* Channel numbers are not consecutive within the globaladdr
* node (why?), so we use the actual counter value as chnls_mask
* index instead of the chnl_array[x].chnl_no value.
*
* NOTE: This loop could be replaced with a constant representing
* a mask of bits 5&6 (ENVCTRL_GLOBALADDR_PSTAT_MASK).
*/
for (i = 0; i < pchild->total_chnls; i++) {
if (PCF8584_VOLTAGE_TYPE == pchild->chnl_array[i].type) {
pchild->voltage_mask |= chnls_mask[i];
}
}
/* We only need to know if this child has global addressing
* line monitored. We don't care which channels since we know
* the mask already (ENVCTRL_GLOBALADDR_ADDR_MASK).
*/
pchild->mon_type[0] = ENVCTRL_GLOBALADDR_MON;
}
/* Initialize child device monitoring voltage status. */
static void envctrl_init_voltage_status(struct i2c_child_t *pchild)
{
int i;
/* Go through all channels and set up the mask. */
for (i = 0; i < pchild->total_chnls; i++)
pchild->voltage_mask |= chnls_mask[(pchild->chnl_array[i]).chnl_no];
/* We only need to know if this child has voltage status monitored.
* We don't care which channels since we have the mask already.
*/
pchild->mon_type[0] = ENVCTRL_VOLTAGESTAT_MON;
}
/* Function Description: Initialize i2c child device.
* Return: None.
*/
static void envctrl_init_i2c_child(struct device_node *dp,
struct i2c_child_t *pchild)
{
int len, i, tbls_size = 0;
const void *pval;
/* Get device address. */
pval = of_get_property(dp, "reg", &len);
memcpy(&pchild->addr, pval, len);
/* Get tables property. Read firmware temperature tables. */
pval = of_get_property(dp, "translation", &len);
if (pval && len > 0) {
memcpy(pchild->tblprop_array, pval, len);
pchild->total_tbls = len / sizeof(struct pcf8584_tblprop);
for (i = 0; i < pchild->total_tbls; i++) {
if ((pchild->tblprop_array[i].size + pchild->tblprop_array[i].offset) > tbls_size) {
tbls_size = pchild->tblprop_array[i].size + pchild->tblprop_array[i].offset;
}
}
pchild->tables = kmalloc(tbls_size, GFP_KERNEL);
if (pchild->tables == NULL){
printk(KERN_ERR PFX "Failed to allocate table.\n");
return;
}
pval = of_get_property(dp, "tables", &len);
if (!pval || len <= 0) {
printk(KERN_ERR PFX "Failed to get table.\n");
return;
}
memcpy(pchild->tables, pval, len);
}
/* SPARCengine ASM Reference Manual (ref. SMI doc 805-7581-04)
* sections 2.5, 3.5, 4.5 state node 0x70 for CP1400/1500 is
* "For Factory Use Only."
*
* We ignore the node on these platforms by assigning the
* 'NULL' monitor type.
*/
if (ENVCTRL_CPCI_IGNORED_NODE == pchild->addr) {
struct device_node *root_node;
int len;
root_node = of_find_node_by_path("/");
if (of_node_name_eq(root_node, "SUNW,UltraSPARC-IIi-cEngine")) {
for (len = 0; len < PCF8584_MAX_CHANNELS; ++len) {
pchild->mon_type[len] = ENVCTRL_NOMON;
}
of_node_put(root_node);
return;
}
of_node_put(root_node);
}
/* Get the monitor channels. */
pval = of_get_property(dp, "channels-in-use", &len);
memcpy(pchild->chnl_array, pval, len);
pchild->total_chnls = len / sizeof(struct pcf8584_channel);
for (i = 0; i < pchild->total_chnls; i++) {
switch (pchild->chnl_array[i].type) {
case PCF8584_TEMP_TYPE:
envctrl_init_adc(pchild, dp);
break;
case PCF8584_GLOBALADDR_TYPE:
envctrl_init_globaladdr(pchild);
i = pchild->total_chnls;
break;
case PCF8584_FANSTAT_TYPE:
envctrl_init_fanstat(pchild);
i = pchild->total_chnls;
break;
case PCF8584_VOLTAGE_TYPE:
if (pchild->i2ctype == I2C_ADC) {
envctrl_init_adc(pchild,dp);
} else {
envctrl_init_voltage_status(pchild);
}
i = pchild->total_chnls;
break;
default:
break;
}
}
}
/* Function Description: Search the child device list for a device.
* Return : The i2c child if found. NULL otherwise.
*/
static struct i2c_child_t *envctrl_get_i2c_child(unsigned char mon_type)
{
int i, j;
for (i = 0; i < ENVCTRL_MAX_CPU*2; i++) {
for (j = 0; j < PCF8584_MAX_CHANNELS; j++) {
if (i2c_childlist[i].mon_type[j] == mon_type) {
return (struct i2c_child_t *)(&(i2c_childlist[i]));
}
}
}
return NULL;
}
static void envctrl_do_shutdown(void)
{
static int inprog = 0;
if (inprog != 0)
return;
inprog = 1;
printk(KERN_CRIT "kenvctrld: WARNING: Shutting down the system now.\n");
orderly_poweroff(true);
}
static struct task_struct *kenvctrld_task;
static int kenvctrld(void *__unused)
{
int poll_interval;
int whichcpu;
char tempbuf[10];
struct i2c_child_t *cputemp;
if (NULL == (cputemp = envctrl_get_i2c_child(ENVCTRL_CPUTEMP_MON))) {
printk(KERN_ERR PFX
"kenvctrld unable to monitor CPU temp-- exiting\n");
return -ENODEV;
}
poll_interval = 5000; /* TODO env_mon_interval */
printk(KERN_INFO PFX "%s starting...\n", current->comm);
for (;;) {
msleep_interruptible(poll_interval);
if (kthread_should_stop())
break;
for (whichcpu = 0; whichcpu < ENVCTRL_MAX_CPU; ++whichcpu) {
if (0 < envctrl_read_cpu_info(whichcpu, cputemp,
ENVCTRL_CPUTEMP_MON,
tempbuf)) {
if (tempbuf[0] >= shutdown_temperature) {
printk(KERN_CRIT
"%s: WARNING: CPU%i temperature %i C meets or exceeds "\
"shutdown threshold %i C\n",
current->comm, whichcpu,
tempbuf[0], shutdown_temperature);
envctrl_do_shutdown();
}
}
}
}
printk(KERN_INFO PFX "%s exiting...\n", current->comm);
return 0;
}
static int envctrl_probe(struct platform_device *op)
{
struct device_node *dp;
int index, err;
if (i2c)
return -EINVAL;
i2c = of_ioremap(&op->resource[0], 0, 0x2, DRIVER_NAME);
if (!i2c)
return -ENOMEM;
index = 0;
dp = op->dev.of_node->child;
while (dp) {
if (of_node_name_eq(dp, "gpio")) {
i2c_childlist[index].i2ctype = I2C_GPIO;
envctrl_init_i2c_child(dp, &(i2c_childlist[index++]));
} else if (of_node_name_eq(dp, "adc")) {
i2c_childlist[index].i2ctype = I2C_ADC;
envctrl_init_i2c_child(dp, &(i2c_childlist[index++]));
}
dp = dp->sibling;
}
/* Set device address. */
writeb(CONTROL_PIN, i2c + PCF8584_CSR);
writeb(PCF8584_ADDRESS, i2c + PCF8584_DATA);
/* Set system clock and SCL frequencies. */
writeb(CONTROL_PIN | CONTROL_ES1, i2c + PCF8584_CSR);
writeb(CLK_4_43 | BUS_CLK_90, i2c + PCF8584_DATA);
/* Enable serial interface. */
writeb(CONTROL_PIN | CONTROL_ES0 | CONTROL_ACK, i2c + PCF8584_CSR);
udelay(200);
/* Register the device as a minor miscellaneous device. */
err = misc_register(&envctrl_dev);
if (err) {
printk(KERN_ERR PFX "Unable to get misc minor %d\n",
envctrl_dev.minor);
goto out_iounmap;
}
/* Note above traversal routine post-incremented 'i' to accommodate
* a next child device, so we decrement before reverse-traversal of
* child devices.
*/
printk(KERN_INFO PFX "Initialized ");
for (--index; index >= 0; --index) {
printk("[%s 0x%lx]%s",
(I2C_ADC == i2c_childlist[index].i2ctype) ? "adc" :
((I2C_GPIO == i2c_childlist[index].i2ctype) ? "gpio" : "unknown"),
i2c_childlist[index].addr, (0 == index) ? "\n" : " ");
}
kenvctrld_task = kthread_run(kenvctrld, NULL, "kenvctrld");
if (IS_ERR(kenvctrld_task)) {
err = PTR_ERR(kenvctrld_task);
goto out_deregister;
}
return 0;
out_deregister:
misc_deregister(&envctrl_dev);
out_iounmap:
of_iounmap(&op->resource[0], i2c, 0x2);
for (index = 0; index < ENVCTRL_MAX_CPU * 2; index++)
kfree(i2c_childlist[index].tables);
return err;
}
static void envctrl_remove(struct platform_device *op)
{
int index;
kthread_stop(kenvctrld_task);
of_iounmap(&op->resource[0], i2c, 0x2);
misc_deregister(&envctrl_dev);
for (index = 0; index < ENVCTRL_MAX_CPU * 2; index++)
kfree(i2c_childlist[index].tables);
}
static const struct of_device_id envctrl_match[] = {
{
.name = "i2c",
.compatible = "i2cpcf,8584",
},
{},
};
MODULE_DEVICE_TABLE(of, envctrl_match);
static struct platform_driver envctrl_driver = {
.driver = {
.name = DRIVER_NAME,
.of_match_table = envctrl_match,
},
.probe = envctrl_probe,
.remove = envctrl_remove,
};
module_platform_driver(envctrl_driver);
MODULE_DESCRIPTION("SUN environment monitoring device driver");
MODULE_LICENSE("GPL");
|
/*
* Telecom Clock driver for Intel NetStructure(tm) MPCBL0010
*
* Copyright (C) 2005 Kontron Canada
*
* All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or (at
* your option) any later version.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
* NON INFRINGEMENT. See the GNU General Public License for more
* details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*
* Send feedback to <[email protected]> and the current
* Maintainer <[email protected]>
*
* Description : This is the TELECOM CLOCK module driver for the ATCA
* MPCBL0010 ATCA computer.
*/
#include <linux/module.h>
#include <linux/init.h>
#include <linux/kernel.h> /* printk() */
#include <linux/fs.h> /* everything... */
#include <linux/errno.h> /* error codes */
#include <linux/sched.h>
#include <linux/slab.h>
#include <linux/ioport.h>
#include <linux/interrupt.h>
#include <linux/spinlock.h>
#include <linux/mutex.h>
#include <linux/timer.h>
#include <linux/sysfs.h>
#include <linux/device.h>
#include <linux/miscdevice.h>
#include <linux/platform_device.h>
#include <asm/io.h> /* inb/outb */
#include <linux/uaccess.h>
MODULE_AUTHOR("Sebastien Bouchard <[email protected]>");
MODULE_DESCRIPTION("Telecom Clock driver for Intel NetStructure(tm) MPCBL0010");
MODULE_LICENSE("GPL");
/*Hardware Reset of the PLL */
#define RESET_ON 0x00
#define RESET_OFF 0x01
/* MODE SELECT */
#define NORMAL_MODE 0x00
#define HOLDOVER_MODE 0x10
#define FREERUN_MODE 0x20
/* FILTER SELECT */
#define FILTER_6HZ 0x04
#define FILTER_12HZ 0x00
/* SELECT REFERENCE FREQUENCY */
#define REF_CLK1_8kHz 0x00
#define REF_CLK2_19_44MHz 0x02
/* Select primary or secondary redundant clock */
#define PRIMARY_CLOCK 0x00
#define SECONDARY_CLOCK 0x01
/* CLOCK TRANSMISSION DEFINE */
#define CLK_8kHz 0xff
#define CLK_16_384MHz 0xfb
#define CLK_1_544MHz 0x00
#define CLK_2_048MHz 0x01
#define CLK_4_096MHz 0x02
#define CLK_6_312MHz 0x03
#define CLK_8_192MHz 0x04
#define CLK_19_440MHz 0x06
#define CLK_8_592MHz 0x08
#define CLK_11_184MHz 0x09
#define CLK_34_368MHz 0x0b
#define CLK_44_736MHz 0x0a
/* RECEIVED REFERENCE */
#define AMC_B1 0
#define AMC_B2 1
/* HARDWARE SWITCHING DEFINE */
#define HW_ENABLE 0x80
#define HW_DISABLE 0x00
/* HARDWARE SWITCHING MODE DEFINE */
#define PLL_HOLDOVER 0x40
#define LOST_CLOCK 0x00
/* ALARMS DEFINE */
#define UNLOCK_MASK 0x10
#define HOLDOVER_MASK 0x20
#define SEC_LOST_MASK 0x40
#define PRI_LOST_MASK 0x80
/* INTERRUPT CAUSE DEFINE */
#define PRI_LOS_01_MASK 0x01
#define PRI_LOS_10_MASK 0x02
#define SEC_LOS_01_MASK 0x04
#define SEC_LOS_10_MASK 0x08
#define HOLDOVER_01_MASK 0x10
#define HOLDOVER_10_MASK 0x20
#define UNLOCK_01_MASK 0x40
#define UNLOCK_10_MASK 0x80
struct tlclk_alarms {
__u32 lost_clocks;
__u32 lost_primary_clock;
__u32 lost_secondary_clock;
__u32 primary_clock_back;
__u32 secondary_clock_back;
__u32 switchover_primary;
__u32 switchover_secondary;
__u32 pll_holdover;
__u32 pll_end_holdover;
__u32 pll_lost_sync;
__u32 pll_sync;
};
/* Telecom clock I/O register definition */
#define TLCLK_BASE 0xa08
#define TLCLK_REG0 TLCLK_BASE
#define TLCLK_REG1 (TLCLK_BASE+1)
#define TLCLK_REG2 (TLCLK_BASE+2)
#define TLCLK_REG3 (TLCLK_BASE+3)
#define TLCLK_REG4 (TLCLK_BASE+4)
#define TLCLK_REG5 (TLCLK_BASE+5)
#define TLCLK_REG6 (TLCLK_BASE+6)
#define TLCLK_REG7 (TLCLK_BASE+7)
#define SET_PORT_BITS(port, mask, val) outb(((inb(port) & mask) | val), port)
/* 0 = Dynamic allocation of the major device number */
#define TLCLK_MAJOR 0
/* sysfs interface definition:
Upon loading the driver will create a sysfs directory under
/sys/devices/platform/telco_clock.
This directory exports the following interfaces. There operation is
documented in the MCPBL0010 TPS under the Telecom Clock API section, 11.4.
alarms :
current_ref :
received_ref_clk3a :
received_ref_clk3b :
enable_clk3a_output :
enable_clk3b_output :
enable_clka0_output :
enable_clka1_output :
enable_clkb0_output :
enable_clkb1_output :
filter_select :
hardware_switching :
hardware_switching_mode :
telclock_version :
mode_select :
refalign :
reset :
select_amcb1_transmit_clock :
select_amcb2_transmit_clock :
select_redundant_clock :
select_ref_frequency :
All sysfs interfaces are integers in hex format, i.e echo 99 > refalign
has the same effect as echo 0x99 > refalign.
*/
static unsigned int telclk_interrupt;
static int int_events; /* Event that generate a interrupt */
static int got_event; /* if events processing have been done */
static void switchover_timeout(struct timer_list *t);
static struct timer_list switchover_timer;
static unsigned long tlclk_timer_data;
static struct tlclk_alarms *alarm_events;
static DEFINE_SPINLOCK(event_lock);
static int tlclk_major = TLCLK_MAJOR;
static irqreturn_t tlclk_interrupt(int irq, void *dev_id);
static DECLARE_WAIT_QUEUE_HEAD(wq);
static unsigned long useflags;
static DEFINE_MUTEX(tlclk_mutex);
static int tlclk_open(struct inode *inode, struct file *filp)
{
int result;
mutex_lock(&tlclk_mutex);
if (test_and_set_bit(0, &useflags)) {
result = -EBUSY;
/* this legacy device is always one per system and it doesn't
* know how to handle multiple concurrent clients.
*/
goto out;
}
/* Make sure there is no interrupt pending while
* initialising interrupt handler */
inb(TLCLK_REG6);
/* This device is wired through the FPGA IO space of the ATCA blade
* we can't share this IRQ */
result = request_irq(telclk_interrupt, &tlclk_interrupt,
0, "telco_clock", tlclk_interrupt);
if (result == -EBUSY)
printk(KERN_ERR "tlclk: Interrupt can't be reserved.\n");
else
inb(TLCLK_REG6); /* Clear interrupt events */
out:
mutex_unlock(&tlclk_mutex);
return result;
}
static int tlclk_release(struct inode *inode, struct file *filp)
{
free_irq(telclk_interrupt, tlclk_interrupt);
clear_bit(0, &useflags);
return 0;
}
static ssize_t tlclk_read(struct file *filp, char __user *buf, size_t count,
loff_t *f_pos)
{
if (count < sizeof(struct tlclk_alarms))
return -EIO;
if (mutex_lock_interruptible(&tlclk_mutex))
return -EINTR;
wait_event_interruptible(wq, got_event);
if (copy_to_user(buf, alarm_events, sizeof(struct tlclk_alarms))) {
mutex_unlock(&tlclk_mutex);
return -EFAULT;
}
memset(alarm_events, 0, sizeof(struct tlclk_alarms));
got_event = 0;
mutex_unlock(&tlclk_mutex);
return sizeof(struct tlclk_alarms);
}
static const struct file_operations tlclk_fops = {
.read = tlclk_read,
.open = tlclk_open,
.release = tlclk_release,
.llseek = noop_llseek,
};
static struct miscdevice tlclk_miscdev = {
.minor = MISC_DYNAMIC_MINOR,
.name = "telco_clock",
.fops = &tlclk_fops,
};
static ssize_t show_current_ref(struct device *d,
struct device_attribute *attr, char *buf)
{
unsigned long ret_val;
unsigned long flags;
spin_lock_irqsave(&event_lock, flags);
ret_val = ((inb(TLCLK_REG1) & 0x08) >> 3);
spin_unlock_irqrestore(&event_lock, flags);
return sprintf(buf, "0x%lX\n", ret_val);
}
static DEVICE_ATTR(current_ref, S_IRUGO, show_current_ref, NULL);
static ssize_t show_telclock_version(struct device *d,
struct device_attribute *attr, char *buf)
{
unsigned long ret_val;
unsigned long flags;
spin_lock_irqsave(&event_lock, flags);
ret_val = inb(TLCLK_REG5);
spin_unlock_irqrestore(&event_lock, flags);
return sprintf(buf, "0x%lX\n", ret_val);
}
static DEVICE_ATTR(telclock_version, S_IRUGO,
show_telclock_version, NULL);
static ssize_t show_alarms(struct device *d,
struct device_attribute *attr, char *buf)
{
unsigned long ret_val;
unsigned long flags;
spin_lock_irqsave(&event_lock, flags);
ret_val = (inb(TLCLK_REG2) & 0xf0);
spin_unlock_irqrestore(&event_lock, flags);
return sprintf(buf, "0x%lX\n", ret_val);
}
static DEVICE_ATTR(alarms, S_IRUGO, show_alarms, NULL);
static ssize_t store_received_ref_clk3a(struct device *d,
struct device_attribute *attr, const char *buf, size_t count)
{
unsigned long tmp;
unsigned char val;
unsigned long flags;
sscanf(buf, "%lX", &tmp);
dev_dbg(d, ": tmp = 0x%lX\n", tmp);
val = (unsigned char)tmp;
spin_lock_irqsave(&event_lock, flags);
SET_PORT_BITS(TLCLK_REG1, 0xef, val);
spin_unlock_irqrestore(&event_lock, flags);
return strnlen(buf, count);
}
static DEVICE_ATTR(received_ref_clk3a, (S_IWUSR|S_IWGRP), NULL,
store_received_ref_clk3a);
static ssize_t store_received_ref_clk3b(struct device *d,
struct device_attribute *attr, const char *buf, size_t count)
{
unsigned long tmp;
unsigned char val;
unsigned long flags;
sscanf(buf, "%lX", &tmp);
dev_dbg(d, ": tmp = 0x%lX\n", tmp);
val = (unsigned char)tmp;
spin_lock_irqsave(&event_lock, flags);
SET_PORT_BITS(TLCLK_REG1, 0xdf, val << 1);
spin_unlock_irqrestore(&event_lock, flags);
return strnlen(buf, count);
}
static DEVICE_ATTR(received_ref_clk3b, (S_IWUSR|S_IWGRP), NULL,
store_received_ref_clk3b);
static ssize_t store_enable_clk3b_output(struct device *d,
struct device_attribute *attr, const char *buf, size_t count)
{
unsigned long tmp;
unsigned char val;
unsigned long flags;
sscanf(buf, "%lX", &tmp);
dev_dbg(d, ": tmp = 0x%lX\n", tmp);
val = (unsigned char)tmp;
spin_lock_irqsave(&event_lock, flags);
SET_PORT_BITS(TLCLK_REG3, 0x7f, val << 7);
spin_unlock_irqrestore(&event_lock, flags);
return strnlen(buf, count);
}
static DEVICE_ATTR(enable_clk3b_output, (S_IWUSR|S_IWGRP), NULL,
store_enable_clk3b_output);
static ssize_t store_enable_clk3a_output(struct device *d,
struct device_attribute *attr, const char *buf, size_t count)
{
unsigned long flags;
unsigned long tmp;
unsigned char val;
sscanf(buf, "%lX", &tmp);
dev_dbg(d, "tmp = 0x%lX\n", tmp);
val = (unsigned char)tmp;
spin_lock_irqsave(&event_lock, flags);
SET_PORT_BITS(TLCLK_REG3, 0xbf, val << 6);
spin_unlock_irqrestore(&event_lock, flags);
return strnlen(buf, count);
}
static DEVICE_ATTR(enable_clk3a_output, (S_IWUSR|S_IWGRP), NULL,
store_enable_clk3a_output);
static ssize_t store_enable_clkb1_output(struct device *d,
struct device_attribute *attr, const char *buf, size_t count)
{
unsigned long flags;
unsigned long tmp;
unsigned char val;
sscanf(buf, "%lX", &tmp);
dev_dbg(d, "tmp = 0x%lX\n", tmp);
val = (unsigned char)tmp;
spin_lock_irqsave(&event_lock, flags);
SET_PORT_BITS(TLCLK_REG2, 0xf7, val << 3);
spin_unlock_irqrestore(&event_lock, flags);
return strnlen(buf, count);
}
static DEVICE_ATTR(enable_clkb1_output, (S_IWUSR|S_IWGRP), NULL,
store_enable_clkb1_output);
static ssize_t store_enable_clka1_output(struct device *d,
struct device_attribute *attr, const char *buf, size_t count)
{
unsigned long flags;
unsigned long tmp;
unsigned char val;
sscanf(buf, "%lX", &tmp);
dev_dbg(d, "tmp = 0x%lX\n", tmp);
val = (unsigned char)tmp;
spin_lock_irqsave(&event_lock, flags);
SET_PORT_BITS(TLCLK_REG2, 0xfb, val << 2);
spin_unlock_irqrestore(&event_lock, flags);
return strnlen(buf, count);
}
static DEVICE_ATTR(enable_clka1_output, (S_IWUSR|S_IWGRP), NULL,
store_enable_clka1_output);
static ssize_t store_enable_clkb0_output(struct device *d,
struct device_attribute *attr, const char *buf, size_t count)
{
unsigned long flags;
unsigned long tmp;
unsigned char val;
sscanf(buf, "%lX", &tmp);
dev_dbg(d, "tmp = 0x%lX\n", tmp);
val = (unsigned char)tmp;
spin_lock_irqsave(&event_lock, flags);
SET_PORT_BITS(TLCLK_REG2, 0xfd, val << 1);
spin_unlock_irqrestore(&event_lock, flags);
return strnlen(buf, count);
}
static DEVICE_ATTR(enable_clkb0_output, (S_IWUSR|S_IWGRP), NULL,
store_enable_clkb0_output);
static ssize_t store_enable_clka0_output(struct device *d,
struct device_attribute *attr, const char *buf, size_t count)
{
unsigned long flags;
unsigned long tmp;
unsigned char val;
sscanf(buf, "%lX", &tmp);
dev_dbg(d, "tmp = 0x%lX\n", tmp);
val = (unsigned char)tmp;
spin_lock_irqsave(&event_lock, flags);
SET_PORT_BITS(TLCLK_REG2, 0xfe, val);
spin_unlock_irqrestore(&event_lock, flags);
return strnlen(buf, count);
}
static DEVICE_ATTR(enable_clka0_output, (S_IWUSR|S_IWGRP), NULL,
store_enable_clka0_output);
static ssize_t store_select_amcb2_transmit_clock(struct device *d,
struct device_attribute *attr, const char *buf, size_t count)
{
unsigned long flags;
unsigned long tmp;
unsigned char val;
sscanf(buf, "%lX", &tmp);
dev_dbg(d, "tmp = 0x%lX\n", tmp);
val = (unsigned char)tmp;
spin_lock_irqsave(&event_lock, flags);
if ((val == CLK_8kHz) || (val == CLK_16_384MHz)) {
SET_PORT_BITS(TLCLK_REG3, 0xc7, 0x28);
SET_PORT_BITS(TLCLK_REG1, 0xfb, ~val);
} else if (val >= CLK_8_592MHz) {
SET_PORT_BITS(TLCLK_REG3, 0xc7, 0x38);
switch (val) {
case CLK_8_592MHz:
SET_PORT_BITS(TLCLK_REG0, 0xfc, 2);
break;
case CLK_11_184MHz:
SET_PORT_BITS(TLCLK_REG0, 0xfc, 0);
break;
case CLK_34_368MHz:
SET_PORT_BITS(TLCLK_REG0, 0xfc, 3);
break;
case CLK_44_736MHz:
SET_PORT_BITS(TLCLK_REG0, 0xfc, 1);
break;
}
} else {
SET_PORT_BITS(TLCLK_REG3, 0xc7, val << 3);
}
spin_unlock_irqrestore(&event_lock, flags);
return strnlen(buf, count);
}
static DEVICE_ATTR(select_amcb2_transmit_clock, (S_IWUSR|S_IWGRP), NULL,
store_select_amcb2_transmit_clock);
static ssize_t store_select_amcb1_transmit_clock(struct device *d,
struct device_attribute *attr, const char *buf, size_t count)
{
unsigned long tmp;
unsigned char val;
unsigned long flags;
sscanf(buf, "%lX", &tmp);
dev_dbg(d, "tmp = 0x%lX\n", tmp);
val = (unsigned char)tmp;
spin_lock_irqsave(&event_lock, flags);
if ((val == CLK_8kHz) || (val == CLK_16_384MHz)) {
SET_PORT_BITS(TLCLK_REG3, 0xf8, 0x5);
SET_PORT_BITS(TLCLK_REG1, 0xfb, ~val);
} else if (val >= CLK_8_592MHz) {
SET_PORT_BITS(TLCLK_REG3, 0xf8, 0x7);
switch (val) {
case CLK_8_592MHz:
SET_PORT_BITS(TLCLK_REG0, 0xfc, 2);
break;
case CLK_11_184MHz:
SET_PORT_BITS(TLCLK_REG0, 0xfc, 0);
break;
case CLK_34_368MHz:
SET_PORT_BITS(TLCLK_REG0, 0xfc, 3);
break;
case CLK_44_736MHz:
SET_PORT_BITS(TLCLK_REG0, 0xfc, 1);
break;
}
} else {
SET_PORT_BITS(TLCLK_REG3, 0xf8, val);
}
spin_unlock_irqrestore(&event_lock, flags);
return strnlen(buf, count);
}
static DEVICE_ATTR(select_amcb1_transmit_clock, (S_IWUSR|S_IWGRP), NULL,
store_select_amcb1_transmit_clock);
static ssize_t store_select_redundant_clock(struct device *d,
struct device_attribute *attr, const char *buf, size_t count)
{
unsigned long tmp;
unsigned char val;
unsigned long flags;
sscanf(buf, "%lX", &tmp);
dev_dbg(d, "tmp = 0x%lX\n", tmp);
val = (unsigned char)tmp;
spin_lock_irqsave(&event_lock, flags);
SET_PORT_BITS(TLCLK_REG1, 0xfe, val);
spin_unlock_irqrestore(&event_lock, flags);
return strnlen(buf, count);
}
static DEVICE_ATTR(select_redundant_clock, (S_IWUSR|S_IWGRP), NULL,
store_select_redundant_clock);
static ssize_t store_select_ref_frequency(struct device *d,
struct device_attribute *attr, const char *buf, size_t count)
{
unsigned long tmp;
unsigned char val;
unsigned long flags;
sscanf(buf, "%lX", &tmp);
dev_dbg(d, "tmp = 0x%lX\n", tmp);
val = (unsigned char)tmp;
spin_lock_irqsave(&event_lock, flags);
SET_PORT_BITS(TLCLK_REG1, 0xfd, val);
spin_unlock_irqrestore(&event_lock, flags);
return strnlen(buf, count);
}
static DEVICE_ATTR(select_ref_frequency, (S_IWUSR|S_IWGRP), NULL,
store_select_ref_frequency);
static ssize_t store_filter_select(struct device *d,
struct device_attribute *attr, const char *buf, size_t count)
{
unsigned long tmp;
unsigned char val;
unsigned long flags;
sscanf(buf, "%lX", &tmp);
dev_dbg(d, "tmp = 0x%lX\n", tmp);
val = (unsigned char)tmp;
spin_lock_irqsave(&event_lock, flags);
SET_PORT_BITS(TLCLK_REG0, 0xfb, val);
spin_unlock_irqrestore(&event_lock, flags);
return strnlen(buf, count);
}
static DEVICE_ATTR(filter_select, (S_IWUSR|S_IWGRP), NULL, store_filter_select);
static ssize_t store_hardware_switching_mode(struct device *d,
struct device_attribute *attr, const char *buf, size_t count)
{
unsigned long tmp;
unsigned char val;
unsigned long flags;
sscanf(buf, "%lX", &tmp);
dev_dbg(d, "tmp = 0x%lX\n", tmp);
val = (unsigned char)tmp;
spin_lock_irqsave(&event_lock, flags);
SET_PORT_BITS(TLCLK_REG0, 0xbf, val);
spin_unlock_irqrestore(&event_lock, flags);
return strnlen(buf, count);
}
static DEVICE_ATTR(hardware_switching_mode, (S_IWUSR|S_IWGRP), NULL,
store_hardware_switching_mode);
static ssize_t store_hardware_switching(struct device *d,
struct device_attribute *attr, const char *buf, size_t count)
{
unsigned long tmp;
unsigned char val;
unsigned long flags;
sscanf(buf, "%lX", &tmp);
dev_dbg(d, "tmp = 0x%lX\n", tmp);
val = (unsigned char)tmp;
spin_lock_irqsave(&event_lock, flags);
SET_PORT_BITS(TLCLK_REG0, 0x7f, val);
spin_unlock_irqrestore(&event_lock, flags);
return strnlen(buf, count);
}
static DEVICE_ATTR(hardware_switching, (S_IWUSR|S_IWGRP), NULL,
store_hardware_switching);
static ssize_t store_refalign (struct device *d,
struct device_attribute *attr, const char *buf, size_t count)
{
unsigned long tmp;
unsigned long flags;
sscanf(buf, "%lX", &tmp);
dev_dbg(d, "tmp = 0x%lX\n", tmp);
spin_lock_irqsave(&event_lock, flags);
SET_PORT_BITS(TLCLK_REG0, 0xf7, 0);
SET_PORT_BITS(TLCLK_REG0, 0xf7, 0x08);
SET_PORT_BITS(TLCLK_REG0, 0xf7, 0);
spin_unlock_irqrestore(&event_lock, flags);
return strnlen(buf, count);
}
static DEVICE_ATTR(refalign, (S_IWUSR|S_IWGRP), NULL, store_refalign);
static ssize_t store_mode_select (struct device *d,
struct device_attribute *attr, const char *buf, size_t count)
{
unsigned long tmp;
unsigned char val;
unsigned long flags;
sscanf(buf, "%lX", &tmp);
dev_dbg(d, "tmp = 0x%lX\n", tmp);
val = (unsigned char)tmp;
spin_lock_irqsave(&event_lock, flags);
SET_PORT_BITS(TLCLK_REG0, 0xcf, val);
spin_unlock_irqrestore(&event_lock, flags);
return strnlen(buf, count);
}
static DEVICE_ATTR(mode_select, (S_IWUSR|S_IWGRP), NULL, store_mode_select);
static ssize_t store_reset (struct device *d,
struct device_attribute *attr, const char *buf, size_t count)
{
unsigned long tmp;
unsigned char val;
unsigned long flags;
sscanf(buf, "%lX", &tmp);
dev_dbg(d, "tmp = 0x%lX\n", tmp);
val = (unsigned char)tmp;
spin_lock_irqsave(&event_lock, flags);
SET_PORT_BITS(TLCLK_REG4, 0xfd, val);
spin_unlock_irqrestore(&event_lock, flags);
return strnlen(buf, count);
}
static DEVICE_ATTR(reset, (S_IWUSR|S_IWGRP), NULL, store_reset);
static struct attribute *tlclk_sysfs_entries[] = {
&dev_attr_current_ref.attr,
&dev_attr_telclock_version.attr,
&dev_attr_alarms.attr,
&dev_attr_received_ref_clk3a.attr,
&dev_attr_received_ref_clk3b.attr,
&dev_attr_enable_clk3a_output.attr,
&dev_attr_enable_clk3b_output.attr,
&dev_attr_enable_clkb1_output.attr,
&dev_attr_enable_clka1_output.attr,
&dev_attr_enable_clkb0_output.attr,
&dev_attr_enable_clka0_output.attr,
&dev_attr_select_amcb1_transmit_clock.attr,
&dev_attr_select_amcb2_transmit_clock.attr,
&dev_attr_select_redundant_clock.attr,
&dev_attr_select_ref_frequency.attr,
&dev_attr_filter_select.attr,
&dev_attr_hardware_switching_mode.attr,
&dev_attr_hardware_switching.attr,
&dev_attr_refalign.attr,
&dev_attr_mode_select.attr,
&dev_attr_reset.attr,
NULL
};
static const struct attribute_group tlclk_attribute_group = {
.name = NULL, /* put in device directory */
.attrs = tlclk_sysfs_entries,
};
static struct platform_device *tlclk_device;
static int __init tlclk_init(void)
{
int ret;
telclk_interrupt = (inb(TLCLK_REG7) & 0x0f);
alarm_events = kzalloc( sizeof(struct tlclk_alarms), GFP_KERNEL);
if (!alarm_events) {
ret = -ENOMEM;
goto out1;
}
ret = register_chrdev(tlclk_major, "telco_clock", &tlclk_fops);
if (ret < 0) {
printk(KERN_ERR "tlclk: can't get major %d.\n", tlclk_major);
kfree(alarm_events);
return ret;
}
tlclk_major = ret;
/* Read telecom clock IRQ number (Set by BIOS) */
if (!request_region(TLCLK_BASE, 8, "telco_clock")) {
printk(KERN_ERR "tlclk: request_region 0x%X failed.\n",
TLCLK_BASE);
ret = -EBUSY;
goto out2;
}
if (0x0F == telclk_interrupt ) { /* not MCPBL0010 ? */
printk(KERN_ERR "telclk_interrupt = 0x%x non-mcpbl0010 hw.\n",
telclk_interrupt);
ret = -ENXIO;
goto out3;
}
timer_setup(&switchover_timer, switchover_timeout, 0);
ret = misc_register(&tlclk_miscdev);
if (ret < 0) {
printk(KERN_ERR "tlclk: misc_register returns %d.\n", ret);
goto out3;
}
tlclk_device = platform_device_register_simple("telco_clock",
-1, NULL, 0);
if (IS_ERR(tlclk_device)) {
printk(KERN_ERR "tlclk: platform_device_register failed.\n");
ret = PTR_ERR(tlclk_device);
goto out4;
}
ret = sysfs_create_group(&tlclk_device->dev.kobj,
&tlclk_attribute_group);
if (ret) {
printk(KERN_ERR "tlclk: failed to create sysfs device attributes.\n");
goto out5;
}
return 0;
out5:
platform_device_unregister(tlclk_device);
out4:
misc_deregister(&tlclk_miscdev);
out3:
release_region(TLCLK_BASE, 8);
out2:
kfree(alarm_events);
unregister_chrdev(tlclk_major, "telco_clock");
out1:
return ret;
}
static void __exit tlclk_cleanup(void)
{
sysfs_remove_group(&tlclk_device->dev.kobj, &tlclk_attribute_group);
platform_device_unregister(tlclk_device);
misc_deregister(&tlclk_miscdev);
unregister_chrdev(tlclk_major, "telco_clock");
release_region(TLCLK_BASE, 8);
del_timer_sync(&switchover_timer);
kfree(alarm_events);
}
static void switchover_timeout(struct timer_list *unused)
{
unsigned long flags = tlclk_timer_data;
if ((flags & 1)) {
if ((inb(TLCLK_REG1) & 0x08) != (flags & 0x08))
alarm_events->switchover_primary++;
} else {
if ((inb(TLCLK_REG1) & 0x08) != (flags & 0x08))
alarm_events->switchover_secondary++;
}
/* Alarm processing is done, wake up read task */
del_timer(&switchover_timer);
got_event = 1;
wake_up(&wq);
}
static irqreturn_t tlclk_interrupt(int irq, void *dev_id)
{
unsigned long flags;
spin_lock_irqsave(&event_lock, flags);
/* Read and clear interrupt events */
int_events = inb(TLCLK_REG6);
/* Primary_Los changed from 0 to 1 ? */
if (int_events & PRI_LOS_01_MASK) {
if (inb(TLCLK_REG2) & SEC_LOST_MASK)
alarm_events->lost_clocks++;
else
alarm_events->lost_primary_clock++;
}
/* Primary_Los changed from 1 to 0 ? */
if (int_events & PRI_LOS_10_MASK) {
alarm_events->primary_clock_back++;
SET_PORT_BITS(TLCLK_REG1, 0xFE, 1);
}
/* Secondary_Los changed from 0 to 1 ? */
if (int_events & SEC_LOS_01_MASK) {
if (inb(TLCLK_REG2) & PRI_LOST_MASK)
alarm_events->lost_clocks++;
else
alarm_events->lost_secondary_clock++;
}
/* Secondary_Los changed from 1 to 0 ? */
if (int_events & SEC_LOS_10_MASK) {
alarm_events->secondary_clock_back++;
SET_PORT_BITS(TLCLK_REG1, 0xFE, 0);
}
if (int_events & HOLDOVER_10_MASK)
alarm_events->pll_end_holdover++;
if (int_events & UNLOCK_01_MASK)
alarm_events->pll_lost_sync++;
if (int_events & UNLOCK_10_MASK)
alarm_events->pll_sync++;
/* Holdover changed from 0 to 1 ? */
if (int_events & HOLDOVER_01_MASK) {
alarm_events->pll_holdover++;
/* TIMEOUT in ~10ms */
switchover_timer.expires = jiffies + msecs_to_jiffies(10);
tlclk_timer_data = inb(TLCLK_REG1);
mod_timer(&switchover_timer, switchover_timer.expires);
} else {
got_event = 1;
wake_up(&wq);
}
spin_unlock_irqrestore(&event_lock, flags);
return IRQ_HANDLED;
}
module_init(tlclk_init);
module_exit(tlclk_cleanup);
|
// SPDX-License-Identifier: GPL-2.0-or-later
/* keytable for Twinhan DTV CAB CI Remote Controller
*
* Copyright (c) 2010 by Igor M. Liplianin <[email protected]>
*/
#include <media/rc-map.h>
#include <linux/module.h>
static struct rc_map_table twinhan_dtv_cab_ci[] = {
{ 0x29, KEY_POWER},
{ 0x28, KEY_FAVORITES},
{ 0x30, KEY_TEXT},
{ 0x17, KEY_INFO}, /* Preview */
{ 0x23, KEY_EPG},
{ 0x3b, KEY_F22}, /* Record List */
{ 0x3c, KEY_NUMERIC_1},
{ 0x3e, KEY_NUMERIC_2},
{ 0x39, KEY_NUMERIC_3},
{ 0x36, KEY_NUMERIC_4},
{ 0x22, KEY_NUMERIC_5},
{ 0x20, KEY_NUMERIC_6},
{ 0x32, KEY_NUMERIC_7},
{ 0x26, KEY_NUMERIC_8},
{ 0x24, KEY_NUMERIC_9},
{ 0x2a, KEY_NUMERIC_0},
{ 0x33, KEY_CANCEL},
{ 0x2c, KEY_BACK},
{ 0x15, KEY_CLEAR},
{ 0x3f, KEY_TAB},
{ 0x10, KEY_ENTER},
{ 0x14, KEY_UP},
{ 0x0d, KEY_RIGHT},
{ 0x0e, KEY_DOWN},
{ 0x11, KEY_LEFT},
{ 0x21, KEY_VOLUMEUP},
{ 0x35, KEY_VOLUMEDOWN},
{ 0x3d, KEY_CHANNELDOWN},
{ 0x3a, KEY_CHANNELUP},
{ 0x2e, KEY_RECORD},
{ 0x2b, KEY_PLAY},
{ 0x13, KEY_PAUSE},
{ 0x25, KEY_STOP},
{ 0x1f, KEY_REWIND},
{ 0x2d, KEY_FASTFORWARD},
{ 0x1e, KEY_PREVIOUS}, /* Replay |< */
{ 0x1d, KEY_NEXT}, /* Skip >| */
{ 0x0b, KEY_CAMERA}, /* Capture */
{ 0x0f, KEY_LANGUAGE}, /* SAP */
{ 0x18, KEY_MODE}, /* PIP */
{ 0x12, KEY_ZOOM}, /* Full screen */
{ 0x1c, KEY_SUBTITLE},
{ 0x2f, KEY_MUTE},
{ 0x16, KEY_F20}, /* L/R */
{ 0x38, KEY_F21}, /* Hibernate */
{ 0x37, KEY_SWITCHVIDEOMODE}, /* A/V */
{ 0x31, KEY_AGAIN}, /* Recall */
{ 0x1a, KEY_KPPLUS}, /* Zoom+ */
{ 0x19, KEY_KPMINUS}, /* Zoom- */
{ 0x27, KEY_RED},
{ 0x0C, KEY_GREEN},
{ 0x01, KEY_YELLOW},
{ 0x00, KEY_BLUE},
};
static struct rc_map_list twinhan_dtv_cab_ci_map = {
.map = {
.scan = twinhan_dtv_cab_ci,
.size = ARRAY_SIZE(twinhan_dtv_cab_ci),
.rc_proto = RC_PROTO_UNKNOWN, /* Legacy IR type */
.name = RC_MAP_TWINHAN_DTV_CAB_CI,
}
};
static int __init init_rc_map_twinhan_dtv_cab_ci(void)
{
return rc_map_register(&twinhan_dtv_cab_ci_map);
}
static void __exit exit_rc_map_twinhan_dtv_cab_ci(void)
{
rc_map_unregister(&twinhan_dtv_cab_ci_map);
}
module_init(init_rc_map_twinhan_dtv_cab_ci);
module_exit(exit_rc_map_twinhan_dtv_cab_ci);
MODULE_LICENSE("GPL");
MODULE_DESCRIPTION("Twinhan DTV CAB CI remote controller keytable");
|
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2015-2016 Texas Instruments Incorporated - https://www.ti.com/
*/
/dts-v1/;
#include "am5728.dtsi"
#include "dra7-mmc-iodelay.dtsi"
#include "dra74x-mmc-iodelay.dtsi"
#include "am572x-idk-common.dtsi"
/ {
model = "TI AM5728 IDK";
compatible = "ti,am5728-idk", "ti,am5728", "ti,dra7";
};
&mmc1 {
pinctrl-names = "default", "hs";
pinctrl-0 = <&mmc1_pins_default_no_clk_pu>;
pinctrl-1 = <&mmc1_pins_hs>;
};
&mmc2 {
pinctrl-names = "default", "hs", "ddr_3_3v";
pinctrl-0 = <&mmc2_pins_default>;
pinctrl-1 = <&mmc2_pins_hs>;
pinctrl-2 = <&mmc2_pins_ddr_rev20>;
};
&pruss1_mdio {
status = "disabled";
};
&pruss2_mdio {
status = "disabled";
};
|
// SPDX-License-Identifier: GPL-2.0-only
//
// Copyright (c) 2021 MediaTek Inc.
// Author: Chun-Jie Chen <[email protected]>
#include "clk-gate.h"
#include "clk-mtk.h"
#include <dt-bindings/clock/mt8195-clk.h>
#include <linux/clk-provider.h>
#include <linux/platform_device.h>
static const struct mtk_gate_regs ipe_cg_regs = {
.set_ofs = 0x0,
.clr_ofs = 0x0,
.sta_ofs = 0x0,
};
#define GATE_IPE(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &ipe_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr)
static const struct mtk_gate ipe_clks[] = {
GATE_IPE(CLK_IPE_DPE, "ipe_dpe", "top_ipe", 0),
GATE_IPE(CLK_IPE_FDVT, "ipe_fdvt", "top_ipe", 1),
GATE_IPE(CLK_IPE_ME, "ipe_me", "top_ipe", 2),
GATE_IPE(CLK_IPE_TOP, "ipe_top", "top_ipe", 3),
GATE_IPE(CLK_IPE_SMI_LARB12, "ipe_smi_larb12", "top_ipe", 4),
};
static const struct mtk_clk_desc ipe_desc = {
.clks = ipe_clks,
.num_clks = ARRAY_SIZE(ipe_clks),
};
static const struct of_device_id of_match_clk_mt8195_ipe[] = {
{
.compatible = "mediatek,mt8195-ipesys",
.data = &ipe_desc,
}, {
/* sentinel */
}
};
MODULE_DEVICE_TABLE(of, of_match_clk_mt8195_ipe);
static struct platform_driver clk_mt8195_ipe_drv = {
.probe = mtk_clk_simple_probe,
.remove = mtk_clk_simple_remove,
.driver = {
.name = "clk-mt8195-ipe",
.of_match_table = of_match_clk_mt8195_ipe,
},
};
module_platform_driver(clk_mt8195_ipe_drv);
MODULE_DESCRIPTION("MediaTek MT8195 Image Processing Engine clocks driver");
MODULE_LICENSE("GPL");
|
// SPDX-License-Identifier: GPL-2.0
//
// ctu.c
//
// Copyright (c) 2015 Kuninori Morimoto <[email protected]>
#include "rsnd.h"
#define CTU_NAME_SIZE 16
#define CTU_NAME "ctu"
/*
* User needs to setup CTU by amixer, and its settings are
* based on below registers
*
* CTUn_CPMDR : amixser set "CTU Pass"
* CTUn_SV0xR : amixser set "CTU SV0"
* CTUn_SV1xR : amixser set "CTU SV1"
* CTUn_SV2xR : amixser set "CTU SV2"
* CTUn_SV3xR : amixser set "CTU SV3"
*
* [CTU Pass]
* 0000: default
* 0001: Connect input data of channel 0
* 0010: Connect input data of channel 1
* 0011: Connect input data of channel 2
* 0100: Connect input data of channel 3
* 0101: Connect input data of channel 4
* 0110: Connect input data of channel 5
* 0111: Connect input data of channel 6
* 1000: Connect input data of channel 7
* 1001: Connect calculated data by scale values of matrix row 0
* 1010: Connect calculated data by scale values of matrix row 1
* 1011: Connect calculated data by scale values of matrix row 2
* 1100: Connect calculated data by scale values of matrix row 3
*
* [CTU SVx]
* [Output0] = [SV00, SV01, SV02, SV03, SV04, SV05, SV06, SV07]
* [Output1] = [SV10, SV11, SV12, SV13, SV14, SV15, SV16, SV17]
* [Output2] = [SV20, SV21, SV22, SV23, SV24, SV25, SV26, SV27]
* [Output3] = [SV30, SV31, SV32, SV33, SV34, SV35, SV36, SV37]
* [Output4] = [ 0, 0, 0, 0, 0, 0, 0, 0 ]
* [Output5] = [ 0, 0, 0, 0, 0, 0, 0, 0 ]
* [Output6] = [ 0, 0, 0, 0, 0, 0, 0, 0 ]
* [Output7] = [ 0, 0, 0, 0, 0, 0, 0, 0 ]
*
* [SVxx]
* Plus Minus
* value time dB value time dB
* -----------------------------------------------------------------------
* H'7F_FFFF 2 6 H'80_0000 2 6
* ...
* H'40_0000 1 0 H'C0_0000 1 0
* ...
* H'00_0001 2.38 x 10^-7 -132
* H'00_0000 0 Mute H'FF_FFFF 2.38 x 10^-7 -132
*
*
* Ex) Input ch -> Output ch
* 1ch -> 0ch
* 0ch -> 1ch
*
* amixer set "CTU Reset" on
* amixer set "CTU Pass" 9,10
* amixer set "CTU SV0" 0,4194304
* amixer set "CTU SV1" 4194304,0
* or
* amixer set "CTU Reset" on
* amixer set "CTU Pass" 2,1
*/
struct rsnd_ctu {
struct rsnd_mod mod;
struct rsnd_kctrl_cfg_m pass;
struct rsnd_kctrl_cfg_m sv[4];
struct rsnd_kctrl_cfg_s reset;
int channels;
u32 flags;
};
#define KCTRL_INITIALIZED (1 << 0)
#define rsnd_ctu_nr(priv) ((priv)->ctu_nr)
#define for_each_rsnd_ctu(pos, priv, i) \
for ((i) = 0; \
((i) < rsnd_ctu_nr(priv)) && \
((pos) = (struct rsnd_ctu *)(priv)->ctu + i); \
i++)
#define rsnd_mod_to_ctu(_mod) \
container_of((_mod), struct rsnd_ctu, mod)
#define rsnd_ctu_get(priv, id) ((struct rsnd_ctu *)(priv->ctu) + id)
static void rsnd_ctu_activation(struct rsnd_mod *mod)
{
rsnd_mod_write(mod, CTU_SWRSR, 0);
rsnd_mod_write(mod, CTU_SWRSR, 1);
}
static void rsnd_ctu_halt(struct rsnd_mod *mod)
{
rsnd_mod_write(mod, CTU_CTUIR, 1);
rsnd_mod_write(mod, CTU_SWRSR, 0);
}
static int rsnd_ctu_probe_(struct rsnd_mod *mod,
struct rsnd_dai_stream *io,
struct rsnd_priv *priv)
{
return rsnd_cmd_attach(io, rsnd_mod_id(mod));
}
static void rsnd_ctu_value_init(struct rsnd_dai_stream *io,
struct rsnd_mod *mod)
{
struct rsnd_ctu *ctu = rsnd_mod_to_ctu(mod);
u32 cpmdr = 0;
u32 scmdr = 0;
int i, j;
for (i = 0; i < RSND_MAX_CHANNELS; i++) {
u32 val = rsnd_kctrl_valm(ctu->pass, i);
cpmdr |= val << (28 - (i * 4));
if ((val > 0x8) && (scmdr < (val - 0x8)))
scmdr = val - 0x8;
}
rsnd_mod_write(mod, CTU_CTUIR, 1);
rsnd_mod_write(mod, CTU_ADINR, rsnd_runtime_channel_original(io));
rsnd_mod_write(mod, CTU_CPMDR, cpmdr);
rsnd_mod_write(mod, CTU_SCMDR, scmdr);
for (i = 0; i < 4; i++) {
if (i >= scmdr)
break;
for (j = 0; j < RSND_MAX_CHANNELS; j++)
rsnd_mod_write(mod, CTU_SVxxR(i, j), rsnd_kctrl_valm(ctu->sv[i], j));
}
rsnd_mod_write(mod, CTU_CTUIR, 0);
}
static void rsnd_ctu_value_reset(struct rsnd_dai_stream *io,
struct rsnd_mod *mod)
{
struct rsnd_ctu *ctu = rsnd_mod_to_ctu(mod);
int i;
if (!rsnd_kctrl_vals(ctu->reset))
return;
for (i = 0; i < RSND_MAX_CHANNELS; i++) {
rsnd_kctrl_valm(ctu->pass, i) = 0;
rsnd_kctrl_valm(ctu->sv[0], i) = 0;
rsnd_kctrl_valm(ctu->sv[1], i) = 0;
rsnd_kctrl_valm(ctu->sv[2], i) = 0;
rsnd_kctrl_valm(ctu->sv[3], i) = 0;
}
rsnd_kctrl_vals(ctu->reset) = 0;
}
static int rsnd_ctu_init(struct rsnd_mod *mod,
struct rsnd_dai_stream *io,
struct rsnd_priv *priv)
{
int ret;
ret = rsnd_mod_power_on(mod);
if (ret < 0)
return ret;
rsnd_ctu_activation(mod);
rsnd_ctu_value_init(io, mod);
return 0;
}
static int rsnd_ctu_quit(struct rsnd_mod *mod,
struct rsnd_dai_stream *io,
struct rsnd_priv *priv)
{
rsnd_ctu_halt(mod);
rsnd_mod_power_off(mod);
return 0;
}
static int rsnd_ctu_pcm_new(struct rsnd_mod *mod,
struct rsnd_dai_stream *io,
struct snd_soc_pcm_runtime *rtd)
{
struct rsnd_ctu *ctu = rsnd_mod_to_ctu(mod);
int ret;
if (rsnd_flags_has(ctu, KCTRL_INITIALIZED))
return 0;
/* CTU Pass */
ret = rsnd_kctrl_new_m(mod, io, rtd, "CTU Pass",
rsnd_kctrl_accept_anytime,
NULL,
&ctu->pass, RSND_MAX_CHANNELS,
0xC);
if (ret < 0)
return ret;
/* ROW0 */
ret = rsnd_kctrl_new_m(mod, io, rtd, "CTU SV0",
rsnd_kctrl_accept_anytime,
NULL,
&ctu->sv[0], RSND_MAX_CHANNELS,
0x00FFFFFF);
if (ret < 0)
return ret;
/* ROW1 */
ret = rsnd_kctrl_new_m(mod, io, rtd, "CTU SV1",
rsnd_kctrl_accept_anytime,
NULL,
&ctu->sv[1], RSND_MAX_CHANNELS,
0x00FFFFFF);
if (ret < 0)
return ret;
/* ROW2 */
ret = rsnd_kctrl_new_m(mod, io, rtd, "CTU SV2",
rsnd_kctrl_accept_anytime,
NULL,
&ctu->sv[2], RSND_MAX_CHANNELS,
0x00FFFFFF);
if (ret < 0)
return ret;
/* ROW3 */
ret = rsnd_kctrl_new_m(mod, io, rtd, "CTU SV3",
rsnd_kctrl_accept_anytime,
NULL,
&ctu->sv[3], RSND_MAX_CHANNELS,
0x00FFFFFF);
if (ret < 0)
return ret;
/* Reset */
ret = rsnd_kctrl_new_s(mod, io, rtd, "CTU Reset",
rsnd_kctrl_accept_anytime,
rsnd_ctu_value_reset,
&ctu->reset, 1);
rsnd_flags_set(ctu, KCTRL_INITIALIZED);
return ret;
}
static int rsnd_ctu_id(struct rsnd_mod *mod)
{
/*
* ctu00: -> 0, ctu01: -> 0, ctu02: -> 0, ctu03: -> 0
* ctu10: -> 1, ctu11: -> 1, ctu12: -> 1, ctu13: -> 1
*/
return mod->id / 4;
}
static int rsnd_ctu_id_sub(struct rsnd_mod *mod)
{
/*
* ctu00: -> 0, ctu01: -> 1, ctu02: -> 2, ctu03: -> 3
* ctu10: -> 0, ctu11: -> 1, ctu12: -> 2, ctu13: -> 3
*/
return mod->id % 4;
}
#ifdef CONFIG_DEBUG_FS
static void rsnd_ctu_debug_info(struct seq_file *m,
struct rsnd_dai_stream *io,
struct rsnd_mod *mod)
{
rsnd_debugfs_mod_reg_show(m, mod, RSND_BASE_SCU,
0x500 + rsnd_mod_id_raw(mod) * 0x100, 0x100);
}
#define DEBUG_INFO .debug_info = rsnd_ctu_debug_info
#else
#define DEBUG_INFO
#endif
static struct rsnd_mod_ops rsnd_ctu_ops = {
.name = CTU_NAME,
.probe = rsnd_ctu_probe_,
.init = rsnd_ctu_init,
.quit = rsnd_ctu_quit,
.pcm_new = rsnd_ctu_pcm_new,
.get_status = rsnd_mod_get_status,
.id = rsnd_ctu_id,
.id_sub = rsnd_ctu_id_sub,
.id_cmd = rsnd_mod_id_raw,
DEBUG_INFO
};
struct rsnd_mod *rsnd_ctu_mod_get(struct rsnd_priv *priv, int id)
{
if (WARN_ON(id < 0 || id >= rsnd_ctu_nr(priv)))
id = 0;
return rsnd_mod_get(rsnd_ctu_get(priv, id));
}
int rsnd_ctu_probe(struct rsnd_priv *priv)
{
struct device_node *node;
struct device_node *np;
struct device *dev = rsnd_priv_to_dev(priv);
struct rsnd_ctu *ctu;
struct clk *clk;
char name[CTU_NAME_SIZE];
int i, nr, ret;
node = rsnd_ctu_of_node(priv);
if (!node)
return 0; /* not used is not error */
nr = of_get_child_count(node);
if (!nr) {
ret = -EINVAL;
goto rsnd_ctu_probe_done;
}
ctu = devm_kcalloc(dev, nr, sizeof(*ctu), GFP_KERNEL);
if (!ctu) {
ret = -ENOMEM;
goto rsnd_ctu_probe_done;
}
priv->ctu_nr = nr;
priv->ctu = ctu;
i = 0;
ret = 0;
for_each_child_of_node(node, np) {
ctu = rsnd_ctu_get(priv, i);
/*
* CTU00, CTU01, CTU02, CTU03 => CTU0
* CTU10, CTU11, CTU12, CTU13 => CTU1
*/
snprintf(name, CTU_NAME_SIZE, "%s.%d",
CTU_NAME, i / 4);
clk = devm_clk_get(dev, name);
if (IS_ERR(clk)) {
ret = PTR_ERR(clk);
of_node_put(np);
goto rsnd_ctu_probe_done;
}
ret = rsnd_mod_init(priv, rsnd_mod_get(ctu), &rsnd_ctu_ops,
clk, RSND_MOD_CTU, i);
if (ret) {
of_node_put(np);
goto rsnd_ctu_probe_done;
}
i++;
}
rsnd_ctu_probe_done:
of_node_put(node);
return ret;
}
void rsnd_ctu_remove(struct rsnd_priv *priv)
{
struct rsnd_ctu *ctu;
int i;
for_each_rsnd_ctu(ctu, priv, i) {
rsnd_mod_quit(rsnd_mod_get(ctu));
}
}
|
#include <soc/fsl/cpm.h>
|
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2019 Bootlin
* Author: Paul Kocialkowski <[email protected]>
*/
#include <linux/err.h>
#include <linux/gpio/driver.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <linux/mfd/syscon.h>
#define LOGICVC_CTRL_REG 0x40
#define LOGICVC_CTRL_GPIO_SHIFT 11
#define LOGICVC_CTRL_GPIO_BITS 5
#define LOGICVC_POWER_CTRL_REG 0x78
#define LOGICVC_POWER_CTRL_GPIO_SHIFT 0
#define LOGICVC_POWER_CTRL_GPIO_BITS 4
struct logicvc_gpio {
struct gpio_chip chip;
struct regmap *regmap;
};
static void logicvc_gpio_offset(struct logicvc_gpio *logicvc, unsigned offset,
unsigned int *reg, unsigned int *bit)
{
if (offset >= LOGICVC_CTRL_GPIO_BITS) {
*reg = LOGICVC_POWER_CTRL_REG;
/* To the (virtual) power ctrl offset. */
offset -= LOGICVC_CTRL_GPIO_BITS;
/* To the actual bit offset in reg. */
offset += LOGICVC_POWER_CTRL_GPIO_SHIFT;
} else {
*reg = LOGICVC_CTRL_REG;
/* To the actual bit offset in reg. */
offset += LOGICVC_CTRL_GPIO_SHIFT;
}
*bit = BIT(offset);
}
static int logicvc_gpio_get(struct gpio_chip *chip, unsigned offset)
{
struct logicvc_gpio *logicvc = gpiochip_get_data(chip);
unsigned int reg, bit, value;
int ret;
logicvc_gpio_offset(logicvc, offset, ®, &bit);
ret = regmap_read(logicvc->regmap, reg, &value);
if (ret)
return ret;
return !!(value & bit);
}
static void logicvc_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
{
struct logicvc_gpio *logicvc = gpiochip_get_data(chip);
unsigned int reg, bit;
logicvc_gpio_offset(logicvc, offset, ®, &bit);
regmap_update_bits(logicvc->regmap, reg, bit, value ? bit : 0);
}
static int logicvc_gpio_direction_output(struct gpio_chip *chip,
unsigned offset, int value)
{
/* Pins are always configured as output, so just set the value. */
logicvc_gpio_set(chip, offset, value);
return 0;
}
static struct regmap_config logicvc_gpio_regmap_config = {
.reg_bits = 32,
.val_bits = 32,
.reg_stride = 4,
.name = "logicvc-gpio",
};
static int logicvc_gpio_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct device_node *of_node = dev->of_node;
struct logicvc_gpio *logicvc;
int ret;
logicvc = devm_kzalloc(dev, sizeof(*logicvc), GFP_KERNEL);
if (!logicvc)
return -ENOMEM;
/* Try to get regmap from parent first. */
logicvc->regmap = syscon_node_to_regmap(of_node->parent);
/* Grab our own regmap if that fails. */
if (IS_ERR(logicvc->regmap)) {
struct resource res;
void __iomem *base;
ret = of_address_to_resource(of_node, 0, &res);
if (ret) {
dev_err(dev, "Failed to get resource from address\n");
return ret;
}
base = devm_ioremap_resource(dev, &res);
if (IS_ERR(base))
return PTR_ERR(base);
logicvc_gpio_regmap_config.max_register = resource_size(&res) -
logicvc_gpio_regmap_config.reg_stride;
logicvc->regmap =
devm_regmap_init_mmio(dev, base,
&logicvc_gpio_regmap_config);
if (IS_ERR(logicvc->regmap)) {
dev_err(dev, "Failed to create regmap for I/O\n");
return PTR_ERR(logicvc->regmap);
}
}
logicvc->chip.parent = dev;
logicvc->chip.owner = THIS_MODULE;
logicvc->chip.label = dev_name(dev);
logicvc->chip.base = -1;
logicvc->chip.ngpio = LOGICVC_CTRL_GPIO_BITS +
LOGICVC_POWER_CTRL_GPIO_BITS;
logicvc->chip.get = logicvc_gpio_get;
logicvc->chip.set = logicvc_gpio_set;
logicvc->chip.direction_output = logicvc_gpio_direction_output;
return devm_gpiochip_add_data(dev, &logicvc->chip, logicvc);
}
static const struct of_device_id logicivc_gpio_of_table[] = {
{
.compatible = "xylon,logicvc-3.02.a-gpio",
},
{ }
};
MODULE_DEVICE_TABLE(of, logicivc_gpio_of_table);
static struct platform_driver logicvc_gpio_driver = {
.driver = {
.name = "gpio-logicvc",
.of_match_table = logicivc_gpio_of_table,
},
.probe = logicvc_gpio_probe,
};
module_platform_driver(logicvc_gpio_driver);
MODULE_AUTHOR("Paul Kocialkowski <[email protected]>");
MODULE_DESCRIPTION("Xylon LogiCVC GPIO driver");
MODULE_LICENSE("GPL");
|
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Support for Intel Camera Imaging ISP subsystem.
* Copyright (c) 2015, Intel Corporation.
*/
#ifndef __INPUT_SYSTEM_2401_PRIVATE_H_INCLUDED__
#define __INPUT_SYSTEM_2401_PRIVATE_H_INCLUDED__
#include "input_system_public.h"
#include "device_access.h" /* ia_css_device_load_uint32 */
#include "assert_support.h" /* assert */
#include "print_support.h" /* print */
/* Load the register value */
static inline hrt_data ibuf_ctrl_reg_load(const ibuf_ctrl_ID_t ID,
const hrt_address reg)
{
assert(ID < N_IBUF_CTRL_ID);
assert(IBUF_CTRL_BASE[ID] != (hrt_address)-1);
return ia_css_device_load_uint32(IBUF_CTRL_BASE[ID] + reg * sizeof(hrt_data));
}
/* Store a value to the register */
static inline void ibuf_ctrl_reg_store(const ibuf_ctrl_ID_t ID,
const hrt_address reg,
const hrt_data value)
{
assert(ID < N_IBUF_CTRL_ID);
assert(IBUF_CTRL_BASE[ID] != (hrt_address)-1);
ia_css_device_store_uint32(IBUF_CTRL_BASE[ID] + reg * sizeof(hrt_data), value);
}
/* Get the state of the ibuf-controller process */
static inline void ibuf_ctrl_get_proc_state(const ibuf_ctrl_ID_t ID,
const u32 proc_id,
ibuf_ctrl_proc_state_t *state)
{
hrt_address reg_bank_offset;
reg_bank_offset =
_IBUF_CNTRL_PROC_REG_ALIGN * (1 + proc_id);
state->num_items =
ibuf_ctrl_reg_load(ID, reg_bank_offset + _IBUF_CNTRL_NUM_ITEMS_PER_STORE);
state->num_stores =
ibuf_ctrl_reg_load(ID, reg_bank_offset + _IBUF_CNTRL_NUM_STORES_PER_FRAME);
state->dma_channel =
ibuf_ctrl_reg_load(ID, reg_bank_offset + _IBUF_CNTRL_DMA_CHANNEL);
state->dma_command =
ibuf_ctrl_reg_load(ID, reg_bank_offset + _IBUF_CNTRL_DMA_CMD);
state->ibuf_st_addr =
ibuf_ctrl_reg_load(ID, reg_bank_offset + _IBUF_CNTRL_BUFFER_START_ADDRESS);
state->ibuf_stride =
ibuf_ctrl_reg_load(ID, reg_bank_offset + _IBUF_CNTRL_BUFFER_STRIDE);
state->ibuf_end_addr =
ibuf_ctrl_reg_load(ID, reg_bank_offset + _IBUF_CNTRL_BUFFER_END_ADDRESS);
state->dest_st_addr =
ibuf_ctrl_reg_load(ID, reg_bank_offset + _IBUF_CNTRL_DEST_START_ADDRESS);
state->dest_stride =
ibuf_ctrl_reg_load(ID, reg_bank_offset + _IBUF_CNTRL_DEST_STRIDE);
state->dest_end_addr =
ibuf_ctrl_reg_load(ID, reg_bank_offset + _IBUF_CNTRL_DEST_END_ADDRESS);
state->sync_frame =
ibuf_ctrl_reg_load(ID, reg_bank_offset + _IBUF_CNTRL_SYNC_FRAME);
state->sync_command =
ibuf_ctrl_reg_load(ID, reg_bank_offset + _IBUF_CNTRL_STR2MMIO_SYNC_CMD);
state->store_command =
ibuf_ctrl_reg_load(ID, reg_bank_offset + _IBUF_CNTRL_STR2MMIO_STORE_CMD);
state->shift_returned_items =
ibuf_ctrl_reg_load(ID, reg_bank_offset + _IBUF_CNTRL_SHIFT_ITEMS);
state->elems_ibuf =
ibuf_ctrl_reg_load(ID, reg_bank_offset + _IBUF_CNTRL_ELEMS_P_WORD_IBUF);
state->elems_dest =
ibuf_ctrl_reg_load(ID, reg_bank_offset + _IBUF_CNTRL_ELEMS_P_WORD_DEST);
state->cur_stores =
ibuf_ctrl_reg_load(ID, reg_bank_offset + _IBUF_CNTRL_CUR_STORES);
state->cur_acks =
ibuf_ctrl_reg_load(ID, reg_bank_offset + _IBUF_CNTRL_CUR_ACKS);
state->cur_s2m_ibuf_addr =
ibuf_ctrl_reg_load(ID, reg_bank_offset + _IBUF_CNTRL_CUR_S2M_IBUF_ADDR);
state->cur_dma_ibuf_addr =
ibuf_ctrl_reg_load(ID, reg_bank_offset + _IBUF_CNTRL_CUR_DMA_IBUF_ADDR);
state->cur_dma_dest_addr =
ibuf_ctrl_reg_load(ID, reg_bank_offset + _IBUF_CNTRL_CUR_DMA_DEST_ADDR);
state->cur_isp_dest_addr =
ibuf_ctrl_reg_load(ID, reg_bank_offset + _IBUF_CNTRL_CUR_ISP_DEST_ADDR);
state->dma_cmds_send =
ibuf_ctrl_reg_load(ID, reg_bank_offset + _IBUF_CNTRL_CUR_NR_DMA_CMDS_SEND);
state->main_cntrl_state =
ibuf_ctrl_reg_load(ID, reg_bank_offset + _IBUF_CNTRL_MAIN_CNTRL_STATE);
state->dma_sync_state =
ibuf_ctrl_reg_load(ID, reg_bank_offset + _IBUF_CNTRL_DMA_SYNC_STATE);
state->isp_sync_state =
ibuf_ctrl_reg_load(ID, reg_bank_offset + _IBUF_CNTRL_ISP_SYNC_STATE);
}
/* Get the ibuf-controller state. */
static inline void ibuf_ctrl_get_state(const ibuf_ctrl_ID_t ID,
ibuf_ctrl_state_t *state)
{
u32 i;
state->recalc_words =
ibuf_ctrl_reg_load(ID, _IBUF_CNTRL_RECALC_WORDS_STATUS);
state->arbiters =
ibuf_ctrl_reg_load(ID, _IBUF_CNTRL_ARBITERS_STATUS);
/*
* Get the values of the register-set per
* ibuf-controller process.
*/
for (i = 0; i < N_IBUF_CTRL_PROCS[ID]; i++) {
ibuf_ctrl_get_proc_state(
ID,
i,
&state->proc_state[i]);
}
}
/* Dump the ibuf-controller state */
static inline void ibuf_ctrl_dump_state(const ibuf_ctrl_ID_t ID,
ibuf_ctrl_state_t *state)
{
u32 i;
ia_css_print("IBUF controller ID %d recalculate words 0x%x\n", ID,
state->recalc_words);
ia_css_print("IBUF controller ID %d arbiters 0x%x\n", ID, state->arbiters);
/*
* Dump the values of the register-set per
* ibuf-controller process.
*/
for (i = 0; i < N_IBUF_CTRL_PROCS[ID]; i++) {
ia_css_print("IBUF controller ID %d Process ID %d num_items 0x%x\n", ID, i,
state->proc_state[i].num_items);
ia_css_print("IBUF controller ID %d Process ID %d num_stores 0x%x\n", ID, i,
state->proc_state[i].num_stores);
ia_css_print("IBUF controller ID %d Process ID %d dma_channel 0x%x\n", ID, i,
state->proc_state[i].dma_channel);
ia_css_print("IBUF controller ID %d Process ID %d dma_command 0x%x\n", ID, i,
state->proc_state[i].dma_command);
ia_css_print("IBUF controller ID %d Process ID %d ibuf_st_addr 0x%x\n", ID, i,
state->proc_state[i].ibuf_st_addr);
ia_css_print("IBUF controller ID %d Process ID %d ibuf_stride 0x%x\n", ID, i,
state->proc_state[i].ibuf_stride);
ia_css_print("IBUF controller ID %d Process ID %d ibuf_end_addr 0x%x\n", ID, i,
state->proc_state[i].ibuf_end_addr);
ia_css_print("IBUF controller ID %d Process ID %d dest_st_addr 0x%x\n", ID, i,
state->proc_state[i].dest_st_addr);
ia_css_print("IBUF controller ID %d Process ID %d dest_stride 0x%x\n", ID, i,
state->proc_state[i].dest_stride);
ia_css_print("IBUF controller ID %d Process ID %d dest_end_addr 0x%x\n", ID, i,
state->proc_state[i].dest_end_addr);
ia_css_print("IBUF controller ID %d Process ID %d sync_frame 0x%x\n", ID, i,
state->proc_state[i].sync_frame);
ia_css_print("IBUF controller ID %d Process ID %d sync_command 0x%x\n", ID, i,
state->proc_state[i].sync_command);
ia_css_print("IBUF controller ID %d Process ID %d store_command 0x%x\n", ID, i,
state->proc_state[i].store_command);
ia_css_print("IBUF controller ID %d Process ID %d shift_returned_items 0x%x\n",
ID, i,
state->proc_state[i].shift_returned_items);
ia_css_print("IBUF controller ID %d Process ID %d elems_ibuf 0x%x\n", ID, i,
state->proc_state[i].elems_ibuf);
ia_css_print("IBUF controller ID %d Process ID %d elems_dest 0x%x\n", ID, i,
state->proc_state[i].elems_dest);
ia_css_print("IBUF controller ID %d Process ID %d cur_stores 0x%x\n", ID, i,
state->proc_state[i].cur_stores);
ia_css_print("IBUF controller ID %d Process ID %d cur_acks 0x%x\n", ID, i,
state->proc_state[i].cur_acks);
ia_css_print("IBUF controller ID %d Process ID %d cur_s2m_ibuf_addr 0x%x\n", ID,
i,
state->proc_state[i].cur_s2m_ibuf_addr);
ia_css_print("IBUF controller ID %d Process ID %d cur_dma_ibuf_addr 0x%x\n", ID,
i,
state->proc_state[i].cur_dma_ibuf_addr);
ia_css_print("IBUF controller ID %d Process ID %d cur_dma_dest_addr 0x%x\n", ID,
i,
state->proc_state[i].cur_dma_dest_addr);
ia_css_print("IBUF controller ID %d Process ID %d cur_isp_dest_addr 0x%x\n", ID,
i,
state->proc_state[i].cur_isp_dest_addr);
ia_css_print("IBUF controller ID %d Process ID %d dma_cmds_send 0x%x\n", ID, i,
state->proc_state[i].dma_cmds_send);
ia_css_print("IBUF controller ID %d Process ID %d main_cntrl_state 0x%x\n", ID,
i,
state->proc_state[i].main_cntrl_state);
ia_css_print("IBUF controller ID %d Process ID %d dma_sync_state 0x%x\n", ID, i,
state->proc_state[i].dma_sync_state);
ia_css_print("IBUF controller ID %d Process ID %d isp_sync_state 0x%x\n", ID, i,
state->proc_state[i].isp_sync_state);
}
}
#endif /* __INPUT_SYSTEM_PRIVATE_H_INCLUDED__ */
|
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* cobalt interrupt handling
*
* Copyright 2012-2015 Cisco Systems, Inc. and/or its affiliates.
* All rights reserved.
*/
#include <linux/interrupt.h>
irqreturn_t cobalt_irq_handler(int irq, void *dev_id);
void cobalt_irq_work_handler(struct work_struct *work);
void cobalt_irq_log_status(struct cobalt *cobalt);
|
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* OPAL asynchronus Memory error handling support in PowerNV.
*
* Copyright 2013 IBM Corporation
* Author: Mahesh Salgaonkar <[email protected]>
*/
#undef DEBUG
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/of.h>
#include <linux/mm.h>
#include <linux/slab.h>
#include <asm/machdep.h>
#include <asm/opal.h>
#include <asm/cputable.h>
static int opal_mem_err_nb_init;
static LIST_HEAD(opal_memory_err_list);
static DEFINE_SPINLOCK(opal_mem_err_lock);
struct OpalMsgNode {
struct list_head list;
struct opal_msg msg;
};
static void handle_memory_error_event(struct OpalMemoryErrorData *merr_evt)
{
uint64_t paddr_start, paddr_end;
pr_debug("%s: Retrieved memory error event, type: 0x%x\n",
__func__, merr_evt->type);
switch (merr_evt->type) {
case OPAL_MEM_ERR_TYPE_RESILIENCE:
paddr_start = be64_to_cpu(merr_evt->u.resilience.physical_address_start);
paddr_end = be64_to_cpu(merr_evt->u.resilience.physical_address_end);
break;
case OPAL_MEM_ERR_TYPE_DYN_DALLOC:
paddr_start = be64_to_cpu(merr_evt->u.dyn_dealloc.physical_address_start);
paddr_end = be64_to_cpu(merr_evt->u.dyn_dealloc.physical_address_end);
break;
default:
return;
}
for (; paddr_start < paddr_end; paddr_start += PAGE_SIZE) {
memory_failure(paddr_start >> PAGE_SHIFT, 0);
}
}
static void handle_memory_error(void)
{
unsigned long flags;
struct OpalMemoryErrorData *merr_evt;
struct OpalMsgNode *msg_node;
spin_lock_irqsave(&opal_mem_err_lock, flags);
while (!list_empty(&opal_memory_err_list)) {
msg_node = list_entry(opal_memory_err_list.next,
struct OpalMsgNode, list);
list_del(&msg_node->list);
spin_unlock_irqrestore(&opal_mem_err_lock, flags);
merr_evt = (struct OpalMemoryErrorData *)
&msg_node->msg.params[0];
handle_memory_error_event(merr_evt);
kfree(msg_node);
spin_lock_irqsave(&opal_mem_err_lock, flags);
}
spin_unlock_irqrestore(&opal_mem_err_lock, flags);
}
static void mem_error_handler(struct work_struct *work)
{
handle_memory_error();
}
static DECLARE_WORK(mem_error_work, mem_error_handler);
/*
* opal_memory_err_event - notifier handler that queues up the opal message
* to be processed later.
*/
static int opal_memory_err_event(struct notifier_block *nb,
unsigned long msg_type, void *msg)
{
unsigned long flags;
struct OpalMsgNode *msg_node;
if (msg_type != OPAL_MSG_MEM_ERR)
return 0;
msg_node = kzalloc(sizeof(*msg_node), GFP_ATOMIC);
if (!msg_node) {
pr_err("MEMORY_ERROR: out of memory, Opal message event not"
"handled\n");
return -ENOMEM;
}
memcpy(&msg_node->msg, msg, sizeof(msg_node->msg));
spin_lock_irqsave(&opal_mem_err_lock, flags);
list_add(&msg_node->list, &opal_memory_err_list);
spin_unlock_irqrestore(&opal_mem_err_lock, flags);
schedule_work(&mem_error_work);
return 0;
}
static struct notifier_block opal_mem_err_nb = {
.notifier_call = opal_memory_err_event,
.next = NULL,
.priority = 0,
};
static int __init opal_mem_err_init(void)
{
int ret;
if (!opal_mem_err_nb_init) {
ret = opal_message_notifier_register(
OPAL_MSG_MEM_ERR, &opal_mem_err_nb);
if (ret) {
pr_err("%s: Can't register OPAL event notifier (%d)\n",
__func__, ret);
return ret;
}
opal_mem_err_nb_init = 1;
}
return 0;
}
machine_device_initcall(powernv, opal_mem_err_init);
|
/*
* GFX_8_0 Register documentation
*
* Copyright (C) 2014 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
* AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef GFX_8_0_SH_MASK_H
#define GFX_8_0_SH_MASK_H
#define CB_BLEND_RED__BLEND_RED_MASK 0xffffffff
#define CB_BLEND_RED__BLEND_RED__SHIFT 0x0
#define CB_BLEND_GREEN__BLEND_GREEN_MASK 0xffffffff
#define CB_BLEND_GREEN__BLEND_GREEN__SHIFT 0x0
#define CB_BLEND_BLUE__BLEND_BLUE_MASK 0xffffffff
#define CB_BLEND_BLUE__BLEND_BLUE__SHIFT 0x0
#define CB_BLEND_ALPHA__BLEND_ALPHA_MASK 0xffffffff
#define CB_BLEND_ALPHA__BLEND_ALPHA__SHIFT 0x0
#define CB_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x1
#define CB_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0
#define CB_DCC_CONTROL__OVERWRITE_COMBINER_MRT_SHARING_DISABLE_MASK 0x2
#define CB_DCC_CONTROL__OVERWRITE_COMBINER_MRT_SHARING_DISABLE__SHIFT 0x1
#define CB_DCC_CONTROL__OVERWRITE_COMBINER_WATERMARK_MASK 0x7c
#define CB_DCC_CONTROL__OVERWRITE_COMBINER_WATERMARK__SHIFT 0x2
#define CB_COLOR_CONTROL__DEGAMMA_ENABLE_MASK 0x8
#define CB_COLOR_CONTROL__DEGAMMA_ENABLE__SHIFT 0x3
#define CB_COLOR_CONTROL__MODE_MASK 0x70
#define CB_COLOR_CONTROL__MODE__SHIFT 0x4
#define CB_COLOR_CONTROL__ROP3_MASK 0xff0000
#define CB_COLOR_CONTROL__ROP3__SHIFT 0x10
#define CB_BLEND0_CONTROL__COLOR_SRCBLEND_MASK 0x1f
#define CB_BLEND0_CONTROL__COLOR_SRCBLEND__SHIFT 0x0
#define CB_BLEND0_CONTROL__COLOR_COMB_FCN_MASK 0xe0
#define CB_BLEND0_CONTROL__COLOR_COMB_FCN__SHIFT 0x5
#define CB_BLEND0_CONTROL__COLOR_DESTBLEND_MASK 0x1f00
#define CB_BLEND0_CONTROL__COLOR_DESTBLEND__SHIFT 0x8
#define CB_BLEND0_CONTROL__ALPHA_SRCBLEND_MASK 0x1f0000
#define CB_BLEND0_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10
#define CB_BLEND0_CONTROL__ALPHA_COMB_FCN_MASK 0xe00000
#define CB_BLEND0_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15
#define CB_BLEND0_CONTROL__ALPHA_DESTBLEND_MASK 0x1f000000
#define CB_BLEND0_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18
#define CB_BLEND0_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000
#define CB_BLEND0_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d
#define CB_BLEND0_CONTROL__ENABLE_MASK 0x40000000
#define CB_BLEND0_CONTROL__ENABLE__SHIFT 0x1e
#define CB_BLEND0_CONTROL__DISABLE_ROP3_MASK 0x80000000
#define CB_BLEND0_CONTROL__DISABLE_ROP3__SHIFT 0x1f
#define CB_BLEND1_CONTROL__COLOR_SRCBLEND_MASK 0x1f
#define CB_BLEND1_CONTROL__COLOR_SRCBLEND__SHIFT 0x0
#define CB_BLEND1_CONTROL__COLOR_COMB_FCN_MASK 0xe0
#define CB_BLEND1_CONTROL__COLOR_COMB_FCN__SHIFT 0x5
#define CB_BLEND1_CONTROL__COLOR_DESTBLEND_MASK 0x1f00
#define CB_BLEND1_CONTROL__COLOR_DESTBLEND__SHIFT 0x8
#define CB_BLEND1_CONTROL__ALPHA_SRCBLEND_MASK 0x1f0000
#define CB_BLEND1_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10
#define CB_BLEND1_CONTROL__ALPHA_COMB_FCN_MASK 0xe00000
#define CB_BLEND1_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15
#define CB_BLEND1_CONTROL__ALPHA_DESTBLEND_MASK 0x1f000000
#define CB_BLEND1_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18
#define CB_BLEND1_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000
#define CB_BLEND1_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d
#define CB_BLEND1_CONTROL__ENABLE_MASK 0x40000000
#define CB_BLEND1_CONTROL__ENABLE__SHIFT 0x1e
#define CB_BLEND1_CONTROL__DISABLE_ROP3_MASK 0x80000000
#define CB_BLEND1_CONTROL__DISABLE_ROP3__SHIFT 0x1f
#define CB_BLEND2_CONTROL__COLOR_SRCBLEND_MASK 0x1f
#define CB_BLEND2_CONTROL__COLOR_SRCBLEND__SHIFT 0x0
#define CB_BLEND2_CONTROL__COLOR_COMB_FCN_MASK 0xe0
#define CB_BLEND2_CONTROL__COLOR_COMB_FCN__SHIFT 0x5
#define CB_BLEND2_CONTROL__COLOR_DESTBLEND_MASK 0x1f00
#define CB_BLEND2_CONTROL__COLOR_DESTBLEND__SHIFT 0x8
#define CB_BLEND2_CONTROL__ALPHA_SRCBLEND_MASK 0x1f0000
#define CB_BLEND2_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10
#define CB_BLEND2_CONTROL__ALPHA_COMB_FCN_MASK 0xe00000
#define CB_BLEND2_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15
#define CB_BLEND2_CONTROL__ALPHA_DESTBLEND_MASK 0x1f000000
#define CB_BLEND2_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18
#define CB_BLEND2_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000
#define CB_BLEND2_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d
#define CB_BLEND2_CONTROL__ENABLE_MASK 0x40000000
#define CB_BLEND2_CONTROL__ENABLE__SHIFT 0x1e
#define CB_BLEND2_CONTROL__DISABLE_ROP3_MASK 0x80000000
#define CB_BLEND2_CONTROL__DISABLE_ROP3__SHIFT 0x1f
#define CB_BLEND3_CONTROL__COLOR_SRCBLEND_MASK 0x1f
#define CB_BLEND3_CONTROL__COLOR_SRCBLEND__SHIFT 0x0
#define CB_BLEND3_CONTROL__COLOR_COMB_FCN_MASK 0xe0
#define CB_BLEND3_CONTROL__COLOR_COMB_FCN__SHIFT 0x5
#define CB_BLEND3_CONTROL__COLOR_DESTBLEND_MASK 0x1f00
#define CB_BLEND3_CONTROL__COLOR_DESTBLEND__SHIFT 0x8
#define CB_BLEND3_CONTROL__ALPHA_SRCBLEND_MASK 0x1f0000
#define CB_BLEND3_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10
#define CB_BLEND3_CONTROL__ALPHA_COMB_FCN_MASK 0xe00000
#define CB_BLEND3_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15
#define CB_BLEND3_CONTROL__ALPHA_DESTBLEND_MASK 0x1f000000
#define CB_BLEND3_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18
#define CB_BLEND3_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000
#define CB_BLEND3_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d
#define CB_BLEND3_CONTROL__ENABLE_MASK 0x40000000
#define CB_BLEND3_CONTROL__ENABLE__SHIFT 0x1e
#define CB_BLEND3_CONTROL__DISABLE_ROP3_MASK 0x80000000
#define CB_BLEND3_CONTROL__DISABLE_ROP3__SHIFT 0x1f
#define CB_BLEND4_CONTROL__COLOR_SRCBLEND_MASK 0x1f
#define CB_BLEND4_CONTROL__COLOR_SRCBLEND__SHIFT 0x0
#define CB_BLEND4_CONTROL__COLOR_COMB_FCN_MASK 0xe0
#define CB_BLEND4_CONTROL__COLOR_COMB_FCN__SHIFT 0x5
#define CB_BLEND4_CONTROL__COLOR_DESTBLEND_MASK 0x1f00
#define CB_BLEND4_CONTROL__COLOR_DESTBLEND__SHIFT 0x8
#define CB_BLEND4_CONTROL__ALPHA_SRCBLEND_MASK 0x1f0000
#define CB_BLEND4_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10
#define CB_BLEND4_CONTROL__ALPHA_COMB_FCN_MASK 0xe00000
#define CB_BLEND4_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15
#define CB_BLEND4_CONTROL__ALPHA_DESTBLEND_MASK 0x1f000000
#define CB_BLEND4_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18
#define CB_BLEND4_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000
#define CB_BLEND4_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d
#define CB_BLEND4_CONTROL__ENABLE_MASK 0x40000000
#define CB_BLEND4_CONTROL__ENABLE__SHIFT 0x1e
#define CB_BLEND4_CONTROL__DISABLE_ROP3_MASK 0x80000000
#define CB_BLEND4_CONTROL__DISABLE_ROP3__SHIFT 0x1f
#define CB_BLEND5_CONTROL__COLOR_SRCBLEND_MASK 0x1f
#define CB_BLEND5_CONTROL__COLOR_SRCBLEND__SHIFT 0x0
#define CB_BLEND5_CONTROL__COLOR_COMB_FCN_MASK 0xe0
#define CB_BLEND5_CONTROL__COLOR_COMB_FCN__SHIFT 0x5
#define CB_BLEND5_CONTROL__COLOR_DESTBLEND_MASK 0x1f00
#define CB_BLEND5_CONTROL__COLOR_DESTBLEND__SHIFT 0x8
#define CB_BLEND5_CONTROL__ALPHA_SRCBLEND_MASK 0x1f0000
#define CB_BLEND5_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10
#define CB_BLEND5_CONTROL__ALPHA_COMB_FCN_MASK 0xe00000
#define CB_BLEND5_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15
#define CB_BLEND5_CONTROL__ALPHA_DESTBLEND_MASK 0x1f000000
#define CB_BLEND5_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18
#define CB_BLEND5_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000
#define CB_BLEND5_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d
#define CB_BLEND5_CONTROL__ENABLE_MASK 0x40000000
#define CB_BLEND5_CONTROL__ENABLE__SHIFT 0x1e
#define CB_BLEND5_CONTROL__DISABLE_ROP3_MASK 0x80000000
#define CB_BLEND5_CONTROL__DISABLE_ROP3__SHIFT 0x1f
#define CB_BLEND6_CONTROL__COLOR_SRCBLEND_MASK 0x1f
#define CB_BLEND6_CONTROL__COLOR_SRCBLEND__SHIFT 0x0
#define CB_BLEND6_CONTROL__COLOR_COMB_FCN_MASK 0xe0
#define CB_BLEND6_CONTROL__COLOR_COMB_FCN__SHIFT 0x5
#define CB_BLEND6_CONTROL__COLOR_DESTBLEND_MASK 0x1f00
#define CB_BLEND6_CONTROL__COLOR_DESTBLEND__SHIFT 0x8
#define CB_BLEND6_CONTROL__ALPHA_SRCBLEND_MASK 0x1f0000
#define CB_BLEND6_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10
#define CB_BLEND6_CONTROL__ALPHA_COMB_FCN_MASK 0xe00000
#define CB_BLEND6_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15
#define CB_BLEND6_CONTROL__ALPHA_DESTBLEND_MASK 0x1f000000
#define CB_BLEND6_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18
#define CB_BLEND6_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000
#define CB_BLEND6_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d
#define CB_BLEND6_CONTROL__ENABLE_MASK 0x40000000
#define CB_BLEND6_CONTROL__ENABLE__SHIFT 0x1e
#define CB_BLEND6_CONTROL__DISABLE_ROP3_MASK 0x80000000
#define CB_BLEND6_CONTROL__DISABLE_ROP3__SHIFT 0x1f
#define CB_BLEND7_CONTROL__COLOR_SRCBLEND_MASK 0x1f
#define CB_BLEND7_CONTROL__COLOR_SRCBLEND__SHIFT 0x0
#define CB_BLEND7_CONTROL__COLOR_COMB_FCN_MASK 0xe0
#define CB_BLEND7_CONTROL__COLOR_COMB_FCN__SHIFT 0x5
#define CB_BLEND7_CONTROL__COLOR_DESTBLEND_MASK 0x1f00
#define CB_BLEND7_CONTROL__COLOR_DESTBLEND__SHIFT 0x8
#define CB_BLEND7_CONTROL__ALPHA_SRCBLEND_MASK 0x1f0000
#define CB_BLEND7_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10
#define CB_BLEND7_CONTROL__ALPHA_COMB_FCN_MASK 0xe00000
#define CB_BLEND7_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15
#define CB_BLEND7_CONTROL__ALPHA_DESTBLEND_MASK 0x1f000000
#define CB_BLEND7_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18
#define CB_BLEND7_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000
#define CB_BLEND7_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d
#define CB_BLEND7_CONTROL__ENABLE_MASK 0x40000000
#define CB_BLEND7_CONTROL__ENABLE__SHIFT 0x1e
#define CB_BLEND7_CONTROL__DISABLE_ROP3_MASK 0x80000000
#define CB_BLEND7_CONTROL__DISABLE_ROP3__SHIFT 0x1f
#define CB_COLOR0_BASE__BASE_256B_MASK 0xffffffff
#define CB_COLOR0_BASE__BASE_256B__SHIFT 0x0
#define CB_COLOR1_BASE__BASE_256B_MASK 0xffffffff
#define CB_COLOR1_BASE__BASE_256B__SHIFT 0x0
#define CB_COLOR2_BASE__BASE_256B_MASK 0xffffffff
#define CB_COLOR2_BASE__BASE_256B__SHIFT 0x0
#define CB_COLOR3_BASE__BASE_256B_MASK 0xffffffff
#define CB_COLOR3_BASE__BASE_256B__SHIFT 0x0
#define CB_COLOR4_BASE__BASE_256B_MASK 0xffffffff
#define CB_COLOR4_BASE__BASE_256B__SHIFT 0x0
#define CB_COLOR5_BASE__BASE_256B_MASK 0xffffffff
#define CB_COLOR5_BASE__BASE_256B__SHIFT 0x0
#define CB_COLOR6_BASE__BASE_256B_MASK 0xffffffff
#define CB_COLOR6_BASE__BASE_256B__SHIFT 0x0
#define CB_COLOR7_BASE__BASE_256B_MASK 0xffffffff
#define CB_COLOR7_BASE__BASE_256B__SHIFT 0x0
#define CB_COLOR0_PITCH__TILE_MAX_MASK 0x7ff
#define CB_COLOR0_PITCH__TILE_MAX__SHIFT 0x0
#define CB_COLOR0_PITCH__FMASK_TILE_MAX_MASK 0x7ff00000
#define CB_COLOR0_PITCH__FMASK_TILE_MAX__SHIFT 0x14
#define CB_COLOR1_PITCH__TILE_MAX_MASK 0x7ff
#define CB_COLOR1_PITCH__TILE_MAX__SHIFT 0x0
#define CB_COLOR1_PITCH__FMASK_TILE_MAX_MASK 0x7ff00000
#define CB_COLOR1_PITCH__FMASK_TILE_MAX__SHIFT 0x14
#define CB_COLOR2_PITCH__TILE_MAX_MASK 0x7ff
#define CB_COLOR2_PITCH__TILE_MAX__SHIFT 0x0
#define CB_COLOR2_PITCH__FMASK_TILE_MAX_MASK 0x7ff00000
#define CB_COLOR2_PITCH__FMASK_TILE_MAX__SHIFT 0x14
#define CB_COLOR3_PITCH__TILE_MAX_MASK 0x7ff
#define CB_COLOR3_PITCH__TILE_MAX__SHIFT 0x0
#define CB_COLOR3_PITCH__FMASK_TILE_MAX_MASK 0x7ff00000
#define CB_COLOR3_PITCH__FMASK_TILE_MAX__SHIFT 0x14
#define CB_COLOR4_PITCH__TILE_MAX_MASK 0x7ff
#define CB_COLOR4_PITCH__TILE_MAX__SHIFT 0x0
#define CB_COLOR4_PITCH__FMASK_TILE_MAX_MASK 0x7ff00000
#define CB_COLOR4_PITCH__FMASK_TILE_MAX__SHIFT 0x14
#define CB_COLOR5_PITCH__TILE_MAX_MASK 0x7ff
#define CB_COLOR5_PITCH__TILE_MAX__SHIFT 0x0
#define CB_COLOR5_PITCH__FMASK_TILE_MAX_MASK 0x7ff00000
#define CB_COLOR5_PITCH__FMASK_TILE_MAX__SHIFT 0x14
#define CB_COLOR6_PITCH__TILE_MAX_MASK 0x7ff
#define CB_COLOR6_PITCH__TILE_MAX__SHIFT 0x0
#define CB_COLOR6_PITCH__FMASK_TILE_MAX_MASK 0x7ff00000
#define CB_COLOR6_PITCH__FMASK_TILE_MAX__SHIFT 0x14
#define CB_COLOR7_PITCH__TILE_MAX_MASK 0x7ff
#define CB_COLOR7_PITCH__TILE_MAX__SHIFT 0x0
#define CB_COLOR7_PITCH__FMASK_TILE_MAX_MASK 0x7ff00000
#define CB_COLOR7_PITCH__FMASK_TILE_MAX__SHIFT 0x14
#define CB_COLOR0_SLICE__TILE_MAX_MASK 0x3fffff
#define CB_COLOR0_SLICE__TILE_MAX__SHIFT 0x0
#define CB_COLOR1_SLICE__TILE_MAX_MASK 0x3fffff
#define CB_COLOR1_SLICE__TILE_MAX__SHIFT 0x0
#define CB_COLOR2_SLICE__TILE_MAX_MASK 0x3fffff
#define CB_COLOR2_SLICE__TILE_MAX__SHIFT 0x0
#define CB_COLOR3_SLICE__TILE_MAX_MASK 0x3fffff
#define CB_COLOR3_SLICE__TILE_MAX__SHIFT 0x0
#define CB_COLOR4_SLICE__TILE_MAX_MASK 0x3fffff
#define CB_COLOR4_SLICE__TILE_MAX__SHIFT 0x0
#define CB_COLOR5_SLICE__TILE_MAX_MASK 0x3fffff
#define CB_COLOR5_SLICE__TILE_MAX__SHIFT 0x0
#define CB_COLOR6_SLICE__TILE_MAX_MASK 0x3fffff
#define CB_COLOR6_SLICE__TILE_MAX__SHIFT 0x0
#define CB_COLOR7_SLICE__TILE_MAX_MASK 0x3fffff
#define CB_COLOR7_SLICE__TILE_MAX__SHIFT 0x0
#define CB_COLOR0_VIEW__SLICE_START_MASK 0x7ff
#define CB_COLOR0_VIEW__SLICE_START__SHIFT 0x0
#define CB_COLOR0_VIEW__SLICE_MAX_MASK 0xffe000
#define CB_COLOR0_VIEW__SLICE_MAX__SHIFT 0xd
#define CB_COLOR1_VIEW__SLICE_START_MASK 0x7ff
#define CB_COLOR1_VIEW__SLICE_START__SHIFT 0x0
#define CB_COLOR1_VIEW__SLICE_MAX_MASK 0xffe000
#define CB_COLOR1_VIEW__SLICE_MAX__SHIFT 0xd
#define CB_COLOR2_VIEW__SLICE_START_MASK 0x7ff
#define CB_COLOR2_VIEW__SLICE_START__SHIFT 0x0
#define CB_COLOR2_VIEW__SLICE_MAX_MASK 0xffe000
#define CB_COLOR2_VIEW__SLICE_MAX__SHIFT 0xd
#define CB_COLOR3_VIEW__SLICE_START_MASK 0x7ff
#define CB_COLOR3_VIEW__SLICE_START__SHIFT 0x0
#define CB_COLOR3_VIEW__SLICE_MAX_MASK 0xffe000
#define CB_COLOR3_VIEW__SLICE_MAX__SHIFT 0xd
#define CB_COLOR4_VIEW__SLICE_START_MASK 0x7ff
#define CB_COLOR4_VIEW__SLICE_START__SHIFT 0x0
#define CB_COLOR4_VIEW__SLICE_MAX_MASK 0xffe000
#define CB_COLOR4_VIEW__SLICE_MAX__SHIFT 0xd
#define CB_COLOR5_VIEW__SLICE_START_MASK 0x7ff
#define CB_COLOR5_VIEW__SLICE_START__SHIFT 0x0
#define CB_COLOR5_VIEW__SLICE_MAX_MASK 0xffe000
#define CB_COLOR5_VIEW__SLICE_MAX__SHIFT 0xd
#define CB_COLOR6_VIEW__SLICE_START_MASK 0x7ff
#define CB_COLOR6_VIEW__SLICE_START__SHIFT 0x0
#define CB_COLOR6_VIEW__SLICE_MAX_MASK 0xffe000
#define CB_COLOR6_VIEW__SLICE_MAX__SHIFT 0xd
#define CB_COLOR7_VIEW__SLICE_START_MASK 0x7ff
#define CB_COLOR7_VIEW__SLICE_START__SHIFT 0x0
#define CB_COLOR7_VIEW__SLICE_MAX_MASK 0xffe000
#define CB_COLOR7_VIEW__SLICE_MAX__SHIFT 0xd
#define CB_COLOR0_INFO__ENDIAN_MASK 0x3
#define CB_COLOR0_INFO__ENDIAN__SHIFT 0x0
#define CB_COLOR0_INFO__FORMAT_MASK 0x7c
#define CB_COLOR0_INFO__FORMAT__SHIFT 0x2
#define CB_COLOR0_INFO__LINEAR_GENERAL_MASK 0x80
#define CB_COLOR0_INFO__LINEAR_GENERAL__SHIFT 0x7
#define CB_COLOR0_INFO__NUMBER_TYPE_MASK 0x700
#define CB_COLOR0_INFO__NUMBER_TYPE__SHIFT 0x8
#define CB_COLOR0_INFO__COMP_SWAP_MASK 0x1800
#define CB_COLOR0_INFO__COMP_SWAP__SHIFT 0xb
#define CB_COLOR0_INFO__FAST_CLEAR_MASK 0x2000
#define CB_COLOR0_INFO__FAST_CLEAR__SHIFT 0xd
#define CB_COLOR0_INFO__COMPRESSION_MASK 0x4000
#define CB_COLOR0_INFO__COMPRESSION__SHIFT 0xe
#define CB_COLOR0_INFO__BLEND_CLAMP_MASK 0x8000
#define CB_COLOR0_INFO__BLEND_CLAMP__SHIFT 0xf
#define CB_COLOR0_INFO__BLEND_BYPASS_MASK 0x10000
#define CB_COLOR0_INFO__BLEND_BYPASS__SHIFT 0x10
#define CB_COLOR0_INFO__SIMPLE_FLOAT_MASK 0x20000
#define CB_COLOR0_INFO__SIMPLE_FLOAT__SHIFT 0x11
#define CB_COLOR0_INFO__ROUND_MODE_MASK 0x40000
#define CB_COLOR0_INFO__ROUND_MODE__SHIFT 0x12
#define CB_COLOR0_INFO__CMASK_IS_LINEAR_MASK 0x80000
#define CB_COLOR0_INFO__CMASK_IS_LINEAR__SHIFT 0x13
#define CB_COLOR0_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x700000
#define CB_COLOR0_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14
#define CB_COLOR0_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x3800000
#define CB_COLOR0_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17
#define CB_COLOR0_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x4000000
#define CB_COLOR0_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a
#define CB_COLOR0_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK 0x8000000
#define CB_COLOR0_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT 0x1b
#define CB_COLOR0_INFO__DCC_ENABLE_MASK 0x10000000
#define CB_COLOR0_INFO__DCC_ENABLE__SHIFT 0x1c
#define CB_COLOR0_INFO__CMASK_ADDR_TYPE_MASK 0x60000000
#define CB_COLOR0_INFO__CMASK_ADDR_TYPE__SHIFT 0x1d
#define CB_COLOR1_INFO__ENDIAN_MASK 0x3
#define CB_COLOR1_INFO__ENDIAN__SHIFT 0x0
#define CB_COLOR1_INFO__FORMAT_MASK 0x7c
#define CB_COLOR1_INFO__FORMAT__SHIFT 0x2
#define CB_COLOR1_INFO__LINEAR_GENERAL_MASK 0x80
#define CB_COLOR1_INFO__LINEAR_GENERAL__SHIFT 0x7
#define CB_COLOR1_INFO__NUMBER_TYPE_MASK 0x700
#define CB_COLOR1_INFO__NUMBER_TYPE__SHIFT 0x8
#define CB_COLOR1_INFO__COMP_SWAP_MASK 0x1800
#define CB_COLOR1_INFO__COMP_SWAP__SHIFT 0xb
#define CB_COLOR1_INFO__FAST_CLEAR_MASK 0x2000
#define CB_COLOR1_INFO__FAST_CLEAR__SHIFT 0xd
#define CB_COLOR1_INFO__COMPRESSION_MASK 0x4000
#define CB_COLOR1_INFO__COMPRESSION__SHIFT 0xe
#define CB_COLOR1_INFO__BLEND_CLAMP_MASK 0x8000
#define CB_COLOR1_INFO__BLEND_CLAMP__SHIFT 0xf
#define CB_COLOR1_INFO__BLEND_BYPASS_MASK 0x10000
#define CB_COLOR1_INFO__BLEND_BYPASS__SHIFT 0x10
#define CB_COLOR1_INFO__SIMPLE_FLOAT_MASK 0x20000
#define CB_COLOR1_INFO__SIMPLE_FLOAT__SHIFT 0x11
#define CB_COLOR1_INFO__ROUND_MODE_MASK 0x40000
#define CB_COLOR1_INFO__ROUND_MODE__SHIFT 0x12
#define CB_COLOR1_INFO__CMASK_IS_LINEAR_MASK 0x80000
#define CB_COLOR1_INFO__CMASK_IS_LINEAR__SHIFT 0x13
#define CB_COLOR1_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x700000
#define CB_COLOR1_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14
#define CB_COLOR1_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x3800000
#define CB_COLOR1_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17
#define CB_COLOR1_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x4000000
#define CB_COLOR1_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a
#define CB_COLOR1_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK 0x8000000
#define CB_COLOR1_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT 0x1b
#define CB_COLOR1_INFO__DCC_ENABLE_MASK 0x10000000
#define CB_COLOR1_INFO__DCC_ENABLE__SHIFT 0x1c
#define CB_COLOR1_INFO__CMASK_ADDR_TYPE_MASK 0x60000000
#define CB_COLOR1_INFO__CMASK_ADDR_TYPE__SHIFT 0x1d
#define CB_COLOR2_INFO__ENDIAN_MASK 0x3
#define CB_COLOR2_INFO__ENDIAN__SHIFT 0x0
#define CB_COLOR2_INFO__FORMAT_MASK 0x7c
#define CB_COLOR2_INFO__FORMAT__SHIFT 0x2
#define CB_COLOR2_INFO__LINEAR_GENERAL_MASK 0x80
#define CB_COLOR2_INFO__LINEAR_GENERAL__SHIFT 0x7
#define CB_COLOR2_INFO__NUMBER_TYPE_MASK 0x700
#define CB_COLOR2_INFO__NUMBER_TYPE__SHIFT 0x8
#define CB_COLOR2_INFO__COMP_SWAP_MASK 0x1800
#define CB_COLOR2_INFO__COMP_SWAP__SHIFT 0xb
#define CB_COLOR2_INFO__FAST_CLEAR_MASK 0x2000
#define CB_COLOR2_INFO__FAST_CLEAR__SHIFT 0xd
#define CB_COLOR2_INFO__COMPRESSION_MASK 0x4000
#define CB_COLOR2_INFO__COMPRESSION__SHIFT 0xe
#define CB_COLOR2_INFO__BLEND_CLAMP_MASK 0x8000
#define CB_COLOR2_INFO__BLEND_CLAMP__SHIFT 0xf
#define CB_COLOR2_INFO__BLEND_BYPASS_MASK 0x10000
#define CB_COLOR2_INFO__BLEND_BYPASS__SHIFT 0x10
#define CB_COLOR2_INFO__SIMPLE_FLOAT_MASK 0x20000
#define CB_COLOR2_INFO__SIMPLE_FLOAT__SHIFT 0x11
#define CB_COLOR2_INFO__ROUND_MODE_MASK 0x40000
#define CB_COLOR2_INFO__ROUND_MODE__SHIFT 0x12
#define CB_COLOR2_INFO__CMASK_IS_LINEAR_MASK 0x80000
#define CB_COLOR2_INFO__CMASK_IS_LINEAR__SHIFT 0x13
#define CB_COLOR2_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x700000
#define CB_COLOR2_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14
#define CB_COLOR2_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x3800000
#define CB_COLOR2_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17
#define CB_COLOR2_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x4000000
#define CB_COLOR2_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a
#define CB_COLOR2_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK 0x8000000
#define CB_COLOR2_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT 0x1b
#define CB_COLOR2_INFO__DCC_ENABLE_MASK 0x10000000
#define CB_COLOR2_INFO__DCC_ENABLE__SHIFT 0x1c
#define CB_COLOR2_INFO__CMASK_ADDR_TYPE_MASK 0x60000000
#define CB_COLOR2_INFO__CMASK_ADDR_TYPE__SHIFT 0x1d
#define CB_COLOR3_INFO__ENDIAN_MASK 0x3
#define CB_COLOR3_INFO__ENDIAN__SHIFT 0x0
#define CB_COLOR3_INFO__FORMAT_MASK 0x7c
#define CB_COLOR3_INFO__FORMAT__SHIFT 0x2
#define CB_COLOR3_INFO__LINEAR_GENERAL_MASK 0x80
#define CB_COLOR3_INFO__LINEAR_GENERAL__SHIFT 0x7
#define CB_COLOR3_INFO__NUMBER_TYPE_MASK 0x700
#define CB_COLOR3_INFO__NUMBER_TYPE__SHIFT 0x8
#define CB_COLOR3_INFO__COMP_SWAP_MASK 0x1800
#define CB_COLOR3_INFO__COMP_SWAP__SHIFT 0xb
#define CB_COLOR3_INFO__FAST_CLEAR_MASK 0x2000
#define CB_COLOR3_INFO__FAST_CLEAR__SHIFT 0xd
#define CB_COLOR3_INFO__COMPRESSION_MASK 0x4000
#define CB_COLOR3_INFO__COMPRESSION__SHIFT 0xe
#define CB_COLOR3_INFO__BLEND_CLAMP_MASK 0x8000
#define CB_COLOR3_INFO__BLEND_CLAMP__SHIFT 0xf
#define CB_COLOR3_INFO__BLEND_BYPASS_MASK 0x10000
#define CB_COLOR3_INFO__BLEND_BYPASS__SHIFT 0x10
#define CB_COLOR3_INFO__SIMPLE_FLOAT_MASK 0x20000
#define CB_COLOR3_INFO__SIMPLE_FLOAT__SHIFT 0x11
#define CB_COLOR3_INFO__ROUND_MODE_MASK 0x40000
#define CB_COLOR3_INFO__ROUND_MODE__SHIFT 0x12
#define CB_COLOR3_INFO__CMASK_IS_LINEAR_MASK 0x80000
#define CB_COLOR3_INFO__CMASK_IS_LINEAR__SHIFT 0x13
#define CB_COLOR3_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x700000
#define CB_COLOR3_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14
#define CB_COLOR3_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x3800000
#define CB_COLOR3_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17
#define CB_COLOR3_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x4000000
#define CB_COLOR3_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a
#define CB_COLOR3_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK 0x8000000
#define CB_COLOR3_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT 0x1b
#define CB_COLOR3_INFO__DCC_ENABLE_MASK 0x10000000
#define CB_COLOR3_INFO__DCC_ENABLE__SHIFT 0x1c
#define CB_COLOR3_INFO__CMASK_ADDR_TYPE_MASK 0x60000000
#define CB_COLOR3_INFO__CMASK_ADDR_TYPE__SHIFT 0x1d
#define CB_COLOR4_INFO__ENDIAN_MASK 0x3
#define CB_COLOR4_INFO__ENDIAN__SHIFT 0x0
#define CB_COLOR4_INFO__FORMAT_MASK 0x7c
#define CB_COLOR4_INFO__FORMAT__SHIFT 0x2
#define CB_COLOR4_INFO__LINEAR_GENERAL_MASK 0x80
#define CB_COLOR4_INFO__LINEAR_GENERAL__SHIFT 0x7
#define CB_COLOR4_INFO__NUMBER_TYPE_MASK 0x700
#define CB_COLOR4_INFO__NUMBER_TYPE__SHIFT 0x8
#define CB_COLOR4_INFO__COMP_SWAP_MASK 0x1800
#define CB_COLOR4_INFO__COMP_SWAP__SHIFT 0xb
#define CB_COLOR4_INFO__FAST_CLEAR_MASK 0x2000
#define CB_COLOR4_INFO__FAST_CLEAR__SHIFT 0xd
#define CB_COLOR4_INFO__COMPRESSION_MASK 0x4000
#define CB_COLOR4_INFO__COMPRESSION__SHIFT 0xe
#define CB_COLOR4_INFO__BLEND_CLAMP_MASK 0x8000
#define CB_COLOR4_INFO__BLEND_CLAMP__SHIFT 0xf
#define CB_COLOR4_INFO__BLEND_BYPASS_MASK 0x10000
#define CB_COLOR4_INFO__BLEND_BYPASS__SHIFT 0x10
#define CB_COLOR4_INFO__SIMPLE_FLOAT_MASK 0x20000
#define CB_COLOR4_INFO__SIMPLE_FLOAT__SHIFT 0x11
#define CB_COLOR4_INFO__ROUND_MODE_MASK 0x40000
#define CB_COLOR4_INFO__ROUND_MODE__SHIFT 0x12
#define CB_COLOR4_INFO__CMASK_IS_LINEAR_MASK 0x80000
#define CB_COLOR4_INFO__CMASK_IS_LINEAR__SHIFT 0x13
#define CB_COLOR4_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x700000
#define CB_COLOR4_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14
#define CB_COLOR4_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x3800000
#define CB_COLOR4_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17
#define CB_COLOR4_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x4000000
#define CB_COLOR4_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a
#define CB_COLOR4_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK 0x8000000
#define CB_COLOR4_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT 0x1b
#define CB_COLOR4_INFO__DCC_ENABLE_MASK 0x10000000
#define CB_COLOR4_INFO__DCC_ENABLE__SHIFT 0x1c
#define CB_COLOR4_INFO__CMASK_ADDR_TYPE_MASK 0x60000000
#define CB_COLOR4_INFO__CMASK_ADDR_TYPE__SHIFT 0x1d
#define CB_COLOR5_INFO__ENDIAN_MASK 0x3
#define CB_COLOR5_INFO__ENDIAN__SHIFT 0x0
#define CB_COLOR5_INFO__FORMAT_MASK 0x7c
#define CB_COLOR5_INFO__FORMAT__SHIFT 0x2
#define CB_COLOR5_INFO__LINEAR_GENERAL_MASK 0x80
#define CB_COLOR5_INFO__LINEAR_GENERAL__SHIFT 0x7
#define CB_COLOR5_INFO__NUMBER_TYPE_MASK 0x700
#define CB_COLOR5_INFO__NUMBER_TYPE__SHIFT 0x8
#define CB_COLOR5_INFO__COMP_SWAP_MASK 0x1800
#define CB_COLOR5_INFO__COMP_SWAP__SHIFT 0xb
#define CB_COLOR5_INFO__FAST_CLEAR_MASK 0x2000
#define CB_COLOR5_INFO__FAST_CLEAR__SHIFT 0xd
#define CB_COLOR5_INFO__COMPRESSION_MASK 0x4000
#define CB_COLOR5_INFO__COMPRESSION__SHIFT 0xe
#define CB_COLOR5_INFO__BLEND_CLAMP_MASK 0x8000
#define CB_COLOR5_INFO__BLEND_CLAMP__SHIFT 0xf
#define CB_COLOR5_INFO__BLEND_BYPASS_MASK 0x10000
#define CB_COLOR5_INFO__BLEND_BYPASS__SHIFT 0x10
#define CB_COLOR5_INFO__SIMPLE_FLOAT_MASK 0x20000
#define CB_COLOR5_INFO__SIMPLE_FLOAT__SHIFT 0x11
#define CB_COLOR5_INFO__ROUND_MODE_MASK 0x40000
#define CB_COLOR5_INFO__ROUND_MODE__SHIFT 0x12
#define CB_COLOR5_INFO__CMASK_IS_LINEAR_MASK 0x80000
#define CB_COLOR5_INFO__CMASK_IS_LINEAR__SHIFT 0x13
#define CB_COLOR5_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x700000
#define CB_COLOR5_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14
#define CB_COLOR5_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x3800000
#define CB_COLOR5_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17
#define CB_COLOR5_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x4000000
#define CB_COLOR5_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a
#define CB_COLOR5_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK 0x8000000
#define CB_COLOR5_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT 0x1b
#define CB_COLOR5_INFO__DCC_ENABLE_MASK 0x10000000
#define CB_COLOR5_INFO__DCC_ENABLE__SHIFT 0x1c
#define CB_COLOR5_INFO__CMASK_ADDR_TYPE_MASK 0x60000000
#define CB_COLOR5_INFO__CMASK_ADDR_TYPE__SHIFT 0x1d
#define CB_COLOR6_INFO__ENDIAN_MASK 0x3
#define CB_COLOR6_INFO__ENDIAN__SHIFT 0x0
#define CB_COLOR6_INFO__FORMAT_MASK 0x7c
#define CB_COLOR6_INFO__FORMAT__SHIFT 0x2
#define CB_COLOR6_INFO__LINEAR_GENERAL_MASK 0x80
#define CB_COLOR6_INFO__LINEAR_GENERAL__SHIFT 0x7
#define CB_COLOR6_INFO__NUMBER_TYPE_MASK 0x700
#define CB_COLOR6_INFO__NUMBER_TYPE__SHIFT 0x8
#define CB_COLOR6_INFO__COMP_SWAP_MASK 0x1800
#define CB_COLOR6_INFO__COMP_SWAP__SHIFT 0xb
#define CB_COLOR6_INFO__FAST_CLEAR_MASK 0x2000
#define CB_COLOR6_INFO__FAST_CLEAR__SHIFT 0xd
#define CB_COLOR6_INFO__COMPRESSION_MASK 0x4000
#define CB_COLOR6_INFO__COMPRESSION__SHIFT 0xe
#define CB_COLOR6_INFO__BLEND_CLAMP_MASK 0x8000
#define CB_COLOR6_INFO__BLEND_CLAMP__SHIFT 0xf
#define CB_COLOR6_INFO__BLEND_BYPASS_MASK 0x10000
#define CB_COLOR6_INFO__BLEND_BYPASS__SHIFT 0x10
#define CB_COLOR6_INFO__SIMPLE_FLOAT_MASK 0x20000
#define CB_COLOR6_INFO__SIMPLE_FLOAT__SHIFT 0x11
#define CB_COLOR6_INFO__ROUND_MODE_MASK 0x40000
#define CB_COLOR6_INFO__ROUND_MODE__SHIFT 0x12
#define CB_COLOR6_INFO__CMASK_IS_LINEAR_MASK 0x80000
#define CB_COLOR6_INFO__CMASK_IS_LINEAR__SHIFT 0x13
#define CB_COLOR6_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x700000
#define CB_COLOR6_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14
#define CB_COLOR6_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x3800000
#define CB_COLOR6_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17
#define CB_COLOR6_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x4000000
#define CB_COLOR6_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a
#define CB_COLOR6_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK 0x8000000
#define CB_COLOR6_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT 0x1b
#define CB_COLOR6_INFO__DCC_ENABLE_MASK 0x10000000
#define CB_COLOR6_INFO__DCC_ENABLE__SHIFT 0x1c
#define CB_COLOR6_INFO__CMASK_ADDR_TYPE_MASK 0x60000000
#define CB_COLOR6_INFO__CMASK_ADDR_TYPE__SHIFT 0x1d
#define CB_COLOR7_INFO__ENDIAN_MASK 0x3
#define CB_COLOR7_INFO__ENDIAN__SHIFT 0x0
#define CB_COLOR7_INFO__FORMAT_MASK 0x7c
#define CB_COLOR7_INFO__FORMAT__SHIFT 0x2
#define CB_COLOR7_INFO__LINEAR_GENERAL_MASK 0x80
#define CB_COLOR7_INFO__LINEAR_GENERAL__SHIFT 0x7
#define CB_COLOR7_INFO__NUMBER_TYPE_MASK 0x700
#define CB_COLOR7_INFO__NUMBER_TYPE__SHIFT 0x8
#define CB_COLOR7_INFO__COMP_SWAP_MASK 0x1800
#define CB_COLOR7_INFO__COMP_SWAP__SHIFT 0xb
#define CB_COLOR7_INFO__FAST_CLEAR_MASK 0x2000
#define CB_COLOR7_INFO__FAST_CLEAR__SHIFT 0xd
#define CB_COLOR7_INFO__COMPRESSION_MASK 0x4000
#define CB_COLOR7_INFO__COMPRESSION__SHIFT 0xe
#define CB_COLOR7_INFO__BLEND_CLAMP_MASK 0x8000
#define CB_COLOR7_INFO__BLEND_CLAMP__SHIFT 0xf
#define CB_COLOR7_INFO__BLEND_BYPASS_MASK 0x10000
#define CB_COLOR7_INFO__BLEND_BYPASS__SHIFT 0x10
#define CB_COLOR7_INFO__SIMPLE_FLOAT_MASK 0x20000
#define CB_COLOR7_INFO__SIMPLE_FLOAT__SHIFT 0x11
#define CB_COLOR7_INFO__ROUND_MODE_MASK 0x40000
#define CB_COLOR7_INFO__ROUND_MODE__SHIFT 0x12
#define CB_COLOR7_INFO__CMASK_IS_LINEAR_MASK 0x80000
#define CB_COLOR7_INFO__CMASK_IS_LINEAR__SHIFT 0x13
#define CB_COLOR7_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x700000
#define CB_COLOR7_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14
#define CB_COLOR7_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x3800000
#define CB_COLOR7_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17
#define CB_COLOR7_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x4000000
#define CB_COLOR7_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a
#define CB_COLOR7_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK 0x8000000
#define CB_COLOR7_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT 0x1b
#define CB_COLOR7_INFO__DCC_ENABLE_MASK 0x10000000
#define CB_COLOR7_INFO__DCC_ENABLE__SHIFT 0x1c
#define CB_COLOR7_INFO__CMASK_ADDR_TYPE_MASK 0x60000000
#define CB_COLOR7_INFO__CMASK_ADDR_TYPE__SHIFT 0x1d
#define CB_COLOR0_ATTRIB__TILE_MODE_INDEX_MASK 0x1f
#define CB_COLOR0_ATTRIB__TILE_MODE_INDEX__SHIFT 0x0
#define CB_COLOR0_ATTRIB__FMASK_TILE_MODE_INDEX_MASK 0x3e0
#define CB_COLOR0_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT 0x5
#define CB_COLOR0_ATTRIB__FMASK_BANK_HEIGHT_MASK 0xc00
#define CB_COLOR0_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0xa
#define CB_COLOR0_ATTRIB__NUM_SAMPLES_MASK 0x7000
#define CB_COLOR0_ATTRIB__NUM_SAMPLES__SHIFT 0xc
#define CB_COLOR0_ATTRIB__NUM_FRAGMENTS_MASK 0x18000
#define CB_COLOR0_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf
#define CB_COLOR0_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x20000
#define CB_COLOR0_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11
#define CB_COLOR1_ATTRIB__TILE_MODE_INDEX_MASK 0x1f
#define CB_COLOR1_ATTRIB__TILE_MODE_INDEX__SHIFT 0x0
#define CB_COLOR1_ATTRIB__FMASK_TILE_MODE_INDEX_MASK 0x3e0
#define CB_COLOR1_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT 0x5
#define CB_COLOR1_ATTRIB__FMASK_BANK_HEIGHT_MASK 0xc00
#define CB_COLOR1_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0xa
#define CB_COLOR1_ATTRIB__NUM_SAMPLES_MASK 0x7000
#define CB_COLOR1_ATTRIB__NUM_SAMPLES__SHIFT 0xc
#define CB_COLOR1_ATTRIB__NUM_FRAGMENTS_MASK 0x18000
#define CB_COLOR1_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf
#define CB_COLOR1_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x20000
#define CB_COLOR1_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11
#define CB_COLOR2_ATTRIB__TILE_MODE_INDEX_MASK 0x1f
#define CB_COLOR2_ATTRIB__TILE_MODE_INDEX__SHIFT 0x0
#define CB_COLOR2_ATTRIB__FMASK_TILE_MODE_INDEX_MASK 0x3e0
#define CB_COLOR2_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT 0x5
#define CB_COLOR2_ATTRIB__FMASK_BANK_HEIGHT_MASK 0xc00
#define CB_COLOR2_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0xa
#define CB_COLOR2_ATTRIB__NUM_SAMPLES_MASK 0x7000
#define CB_COLOR2_ATTRIB__NUM_SAMPLES__SHIFT 0xc
#define CB_COLOR2_ATTRIB__NUM_FRAGMENTS_MASK 0x18000
#define CB_COLOR2_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf
#define CB_COLOR2_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x20000
#define CB_COLOR2_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11
#define CB_COLOR3_ATTRIB__TILE_MODE_INDEX_MASK 0x1f
#define CB_COLOR3_ATTRIB__TILE_MODE_INDEX__SHIFT 0x0
#define CB_COLOR3_ATTRIB__FMASK_TILE_MODE_INDEX_MASK 0x3e0
#define CB_COLOR3_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT 0x5
#define CB_COLOR3_ATTRIB__FMASK_BANK_HEIGHT_MASK 0xc00
#define CB_COLOR3_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0xa
#define CB_COLOR3_ATTRIB__NUM_SAMPLES_MASK 0x7000
#define CB_COLOR3_ATTRIB__NUM_SAMPLES__SHIFT 0xc
#define CB_COLOR3_ATTRIB__NUM_FRAGMENTS_MASK 0x18000
#define CB_COLOR3_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf
#define CB_COLOR3_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x20000
#define CB_COLOR3_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11
#define CB_COLOR4_ATTRIB__TILE_MODE_INDEX_MASK 0x1f
#define CB_COLOR4_ATTRIB__TILE_MODE_INDEX__SHIFT 0x0
#define CB_COLOR4_ATTRIB__FMASK_TILE_MODE_INDEX_MASK 0x3e0
#define CB_COLOR4_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT 0x5
#define CB_COLOR4_ATTRIB__FMASK_BANK_HEIGHT_MASK 0xc00
#define CB_COLOR4_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0xa
#define CB_COLOR4_ATTRIB__NUM_SAMPLES_MASK 0x7000
#define CB_COLOR4_ATTRIB__NUM_SAMPLES__SHIFT 0xc
#define CB_COLOR4_ATTRIB__NUM_FRAGMENTS_MASK 0x18000
#define CB_COLOR4_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf
#define CB_COLOR4_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x20000
#define CB_COLOR4_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11
#define CB_COLOR5_ATTRIB__TILE_MODE_INDEX_MASK 0x1f
#define CB_COLOR5_ATTRIB__TILE_MODE_INDEX__SHIFT 0x0
#define CB_COLOR5_ATTRIB__FMASK_TILE_MODE_INDEX_MASK 0x3e0
#define CB_COLOR5_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT 0x5
#define CB_COLOR5_ATTRIB__FMASK_BANK_HEIGHT_MASK 0xc00
#define CB_COLOR5_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0xa
#define CB_COLOR5_ATTRIB__NUM_SAMPLES_MASK 0x7000
#define CB_COLOR5_ATTRIB__NUM_SAMPLES__SHIFT 0xc
#define CB_COLOR5_ATTRIB__NUM_FRAGMENTS_MASK 0x18000
#define CB_COLOR5_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf
#define CB_COLOR5_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x20000
#define CB_COLOR5_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11
#define CB_COLOR6_ATTRIB__TILE_MODE_INDEX_MASK 0x1f
#define CB_COLOR6_ATTRIB__TILE_MODE_INDEX__SHIFT 0x0
#define CB_COLOR6_ATTRIB__FMASK_TILE_MODE_INDEX_MASK 0x3e0
#define CB_COLOR6_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT 0x5
#define CB_COLOR6_ATTRIB__FMASK_BANK_HEIGHT_MASK 0xc00
#define CB_COLOR6_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0xa
#define CB_COLOR6_ATTRIB__NUM_SAMPLES_MASK 0x7000
#define CB_COLOR6_ATTRIB__NUM_SAMPLES__SHIFT 0xc
#define CB_COLOR6_ATTRIB__NUM_FRAGMENTS_MASK 0x18000
#define CB_COLOR6_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf
#define CB_COLOR6_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x20000
#define CB_COLOR6_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11
#define CB_COLOR7_ATTRIB__TILE_MODE_INDEX_MASK 0x1f
#define CB_COLOR7_ATTRIB__TILE_MODE_INDEX__SHIFT 0x0
#define CB_COLOR7_ATTRIB__FMASK_TILE_MODE_INDEX_MASK 0x3e0
#define CB_COLOR7_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT 0x5
#define CB_COLOR7_ATTRIB__FMASK_BANK_HEIGHT_MASK 0xc00
#define CB_COLOR7_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0xa
#define CB_COLOR7_ATTRIB__NUM_SAMPLES_MASK 0x7000
#define CB_COLOR7_ATTRIB__NUM_SAMPLES__SHIFT 0xc
#define CB_COLOR7_ATTRIB__NUM_FRAGMENTS_MASK 0x18000
#define CB_COLOR7_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf
#define CB_COLOR7_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x20000
#define CB_COLOR7_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11
#define CB_COLOR0_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x1
#define CB_COLOR0_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0
#define CB_COLOR0_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK 0x2
#define CB_COLOR0_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT 0x1
#define CB_COLOR0_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0xc
#define CB_COLOR0_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2
#define CB_COLOR0_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK 0x10
#define CB_COLOR0_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT 0x4
#define CB_COLOR0_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x60
#define CB_COLOR0_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5
#define CB_COLOR0_DCC_CONTROL__COLOR_TRANSFORM_MASK 0x180
#define CB_COLOR0_DCC_CONTROL__COLOR_TRANSFORM__SHIFT 0x7
#define CB_COLOR0_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK 0x200
#define CB_COLOR0_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT 0x9
#define CB_COLOR0_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK 0x3c00
#define CB_COLOR0_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa
#define CB_COLOR0_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK 0x3c000
#define CB_COLOR0_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT 0xe
#define CB_COLOR1_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x1
#define CB_COLOR1_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0
#define CB_COLOR1_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK 0x2
#define CB_COLOR1_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT 0x1
#define CB_COLOR1_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0xc
#define CB_COLOR1_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2
#define CB_COLOR1_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK 0x10
#define CB_COLOR1_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT 0x4
#define CB_COLOR1_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x60
#define CB_COLOR1_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5
#define CB_COLOR1_DCC_CONTROL__COLOR_TRANSFORM_MASK 0x180
#define CB_COLOR1_DCC_CONTROL__COLOR_TRANSFORM__SHIFT 0x7
#define CB_COLOR1_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK 0x200
#define CB_COLOR1_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT 0x9
#define CB_COLOR1_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK 0x3c00
#define CB_COLOR1_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa
#define CB_COLOR1_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK 0x3c000
#define CB_COLOR1_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT 0xe
#define CB_COLOR2_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x1
#define CB_COLOR2_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0
#define CB_COLOR2_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK 0x2
#define CB_COLOR2_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT 0x1
#define CB_COLOR2_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0xc
#define CB_COLOR2_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2
#define CB_COLOR2_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK 0x10
#define CB_COLOR2_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT 0x4
#define CB_COLOR2_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x60
#define CB_COLOR2_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5
#define CB_COLOR2_DCC_CONTROL__COLOR_TRANSFORM_MASK 0x180
#define CB_COLOR2_DCC_CONTROL__COLOR_TRANSFORM__SHIFT 0x7
#define CB_COLOR2_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK 0x200
#define CB_COLOR2_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT 0x9
#define CB_COLOR2_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK 0x3c00
#define CB_COLOR2_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa
#define CB_COLOR2_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK 0x3c000
#define CB_COLOR2_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT 0xe
#define CB_COLOR3_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x1
#define CB_COLOR3_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0
#define CB_COLOR3_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK 0x2
#define CB_COLOR3_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT 0x1
#define CB_COLOR3_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0xc
#define CB_COLOR3_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2
#define CB_COLOR3_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK 0x10
#define CB_COLOR3_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT 0x4
#define CB_COLOR3_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x60
#define CB_COLOR3_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5
#define CB_COLOR3_DCC_CONTROL__COLOR_TRANSFORM_MASK 0x180
#define CB_COLOR3_DCC_CONTROL__COLOR_TRANSFORM__SHIFT 0x7
#define CB_COLOR3_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK 0x200
#define CB_COLOR3_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT 0x9
#define CB_COLOR3_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK 0x3c00
#define CB_COLOR3_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa
#define CB_COLOR3_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK 0x3c000
#define CB_COLOR3_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT 0xe
#define CB_COLOR4_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x1
#define CB_COLOR4_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0
#define CB_COLOR4_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK 0x2
#define CB_COLOR4_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT 0x1
#define CB_COLOR4_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0xc
#define CB_COLOR4_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2
#define CB_COLOR4_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK 0x10
#define CB_COLOR4_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT 0x4
#define CB_COLOR4_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x60
#define CB_COLOR4_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5
#define CB_COLOR4_DCC_CONTROL__COLOR_TRANSFORM_MASK 0x180
#define CB_COLOR4_DCC_CONTROL__COLOR_TRANSFORM__SHIFT 0x7
#define CB_COLOR4_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK 0x200
#define CB_COLOR4_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT 0x9
#define CB_COLOR4_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK 0x3c00
#define CB_COLOR4_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa
#define CB_COLOR4_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK 0x3c000
#define CB_COLOR4_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT 0xe
#define CB_COLOR5_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x1
#define CB_COLOR5_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0
#define CB_COLOR5_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK 0x2
#define CB_COLOR5_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT 0x1
#define CB_COLOR5_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0xc
#define CB_COLOR5_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2
#define CB_COLOR5_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK 0x10
#define CB_COLOR5_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT 0x4
#define CB_COLOR5_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x60
#define CB_COLOR5_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5
#define CB_COLOR5_DCC_CONTROL__COLOR_TRANSFORM_MASK 0x180
#define CB_COLOR5_DCC_CONTROL__COLOR_TRANSFORM__SHIFT 0x7
#define CB_COLOR5_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK 0x200
#define CB_COLOR5_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT 0x9
#define CB_COLOR5_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK 0x3c00
#define CB_COLOR5_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa
#define CB_COLOR5_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK 0x3c000
#define CB_COLOR5_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT 0xe
#define CB_COLOR6_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x1
#define CB_COLOR6_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0
#define CB_COLOR6_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK 0x2
#define CB_COLOR6_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT 0x1
#define CB_COLOR6_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0xc
#define CB_COLOR6_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2
#define CB_COLOR6_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK 0x10
#define CB_COLOR6_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT 0x4
#define CB_COLOR6_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x60
#define CB_COLOR6_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5
#define CB_COLOR6_DCC_CONTROL__COLOR_TRANSFORM_MASK 0x180
#define CB_COLOR6_DCC_CONTROL__COLOR_TRANSFORM__SHIFT 0x7
#define CB_COLOR6_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK 0x200
#define CB_COLOR6_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT 0x9
#define CB_COLOR6_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK 0x3c00
#define CB_COLOR6_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa
#define CB_COLOR6_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK 0x3c000
#define CB_COLOR6_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT 0xe
#define CB_COLOR7_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x1
#define CB_COLOR7_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0
#define CB_COLOR7_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK 0x2
#define CB_COLOR7_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT 0x1
#define CB_COLOR7_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0xc
#define CB_COLOR7_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2
#define CB_COLOR7_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK 0x10
#define CB_COLOR7_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT 0x4
#define CB_COLOR7_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x60
#define CB_COLOR7_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5
#define CB_COLOR7_DCC_CONTROL__COLOR_TRANSFORM_MASK 0x180
#define CB_COLOR7_DCC_CONTROL__COLOR_TRANSFORM__SHIFT 0x7
#define CB_COLOR7_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK 0x200
#define CB_COLOR7_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT 0x9
#define CB_COLOR7_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK 0x3c00
#define CB_COLOR7_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa
#define CB_COLOR7_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK 0x3c000
#define CB_COLOR7_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT 0xe
#define CB_COLOR0_CMASK__BASE_256B_MASK 0xffffffff
#define CB_COLOR0_CMASK__BASE_256B__SHIFT 0x0
#define CB_COLOR1_CMASK__BASE_256B_MASK 0xffffffff
#define CB_COLOR1_CMASK__BASE_256B__SHIFT 0x0
#define CB_COLOR2_CMASK__BASE_256B_MASK 0xffffffff
#define CB_COLOR2_CMASK__BASE_256B__SHIFT 0x0
#define CB_COLOR3_CMASK__BASE_256B_MASK 0xffffffff
#define CB_COLOR3_CMASK__BASE_256B__SHIFT 0x0
#define CB_COLOR4_CMASK__BASE_256B_MASK 0xffffffff
#define CB_COLOR4_CMASK__BASE_256B__SHIFT 0x0
#define CB_COLOR5_CMASK__BASE_256B_MASK 0xffffffff
#define CB_COLOR5_CMASK__BASE_256B__SHIFT 0x0
#define CB_COLOR6_CMASK__BASE_256B_MASK 0xffffffff
#define CB_COLOR6_CMASK__BASE_256B__SHIFT 0x0
#define CB_COLOR7_CMASK__BASE_256B_MASK 0xffffffff
#define CB_COLOR7_CMASK__BASE_256B__SHIFT 0x0
#define CB_COLOR0_CMASK_SLICE__TILE_MAX_MASK 0x3fff
#define CB_COLOR0_CMASK_SLICE__TILE_MAX__SHIFT 0x0
#define CB_COLOR1_CMASK_SLICE__TILE_MAX_MASK 0x3fff
#define CB_COLOR1_CMASK_SLICE__TILE_MAX__SHIFT 0x0
#define CB_COLOR2_CMASK_SLICE__TILE_MAX_MASK 0x3fff
#define CB_COLOR2_CMASK_SLICE__TILE_MAX__SHIFT 0x0
#define CB_COLOR3_CMASK_SLICE__TILE_MAX_MASK 0x3fff
#define CB_COLOR3_CMASK_SLICE__TILE_MAX__SHIFT 0x0
#define CB_COLOR4_CMASK_SLICE__TILE_MAX_MASK 0x3fff
#define CB_COLOR4_CMASK_SLICE__TILE_MAX__SHIFT 0x0
#define CB_COLOR5_CMASK_SLICE__TILE_MAX_MASK 0x3fff
#define CB_COLOR5_CMASK_SLICE__TILE_MAX__SHIFT 0x0
#define CB_COLOR6_CMASK_SLICE__TILE_MAX_MASK 0x3fff
#define CB_COLOR6_CMASK_SLICE__TILE_MAX__SHIFT 0x0
#define CB_COLOR7_CMASK_SLICE__TILE_MAX_MASK 0x3fff
#define CB_COLOR7_CMASK_SLICE__TILE_MAX__SHIFT 0x0
#define CB_COLOR0_FMASK__BASE_256B_MASK 0xffffffff
#define CB_COLOR0_FMASK__BASE_256B__SHIFT 0x0
#define CB_COLOR1_FMASK__BASE_256B_MASK 0xffffffff
#define CB_COLOR1_FMASK__BASE_256B__SHIFT 0x0
#define CB_COLOR2_FMASK__BASE_256B_MASK 0xffffffff
#define CB_COLOR2_FMASK__BASE_256B__SHIFT 0x0
#define CB_COLOR3_FMASK__BASE_256B_MASK 0xffffffff
#define CB_COLOR3_FMASK__BASE_256B__SHIFT 0x0
#define CB_COLOR4_FMASK__BASE_256B_MASK 0xffffffff
#define CB_COLOR4_FMASK__BASE_256B__SHIFT 0x0
#define CB_COLOR5_FMASK__BASE_256B_MASK 0xffffffff
#define CB_COLOR5_FMASK__BASE_256B__SHIFT 0x0
#define CB_COLOR6_FMASK__BASE_256B_MASK 0xffffffff
#define CB_COLOR6_FMASK__BASE_256B__SHIFT 0x0
#define CB_COLOR7_FMASK__BASE_256B_MASK 0xffffffff
#define CB_COLOR7_FMASK__BASE_256B__SHIFT 0x0
#define CB_COLOR0_FMASK_SLICE__TILE_MAX_MASK 0x3fffff
#define CB_COLOR0_FMASK_SLICE__TILE_MAX__SHIFT 0x0
#define CB_COLOR1_FMASK_SLICE__TILE_MAX_MASK 0x3fffff
#define CB_COLOR1_FMASK_SLICE__TILE_MAX__SHIFT 0x0
#define CB_COLOR2_FMASK_SLICE__TILE_MAX_MASK 0x3fffff
#define CB_COLOR2_FMASK_SLICE__TILE_MAX__SHIFT 0x0
#define CB_COLOR3_FMASK_SLICE__TILE_MAX_MASK 0x3fffff
#define CB_COLOR3_FMASK_SLICE__TILE_MAX__SHIFT 0x0
#define CB_COLOR4_FMASK_SLICE__TILE_MAX_MASK 0x3fffff
#define CB_COLOR4_FMASK_SLICE__TILE_MAX__SHIFT 0x0
#define CB_COLOR5_FMASK_SLICE__TILE_MAX_MASK 0x3fffff
#define CB_COLOR5_FMASK_SLICE__TILE_MAX__SHIFT 0x0
#define CB_COLOR6_FMASK_SLICE__TILE_MAX_MASK 0x3fffff
#define CB_COLOR6_FMASK_SLICE__TILE_MAX__SHIFT 0x0
#define CB_COLOR7_FMASK_SLICE__TILE_MAX_MASK 0x3fffff
#define CB_COLOR7_FMASK_SLICE__TILE_MAX__SHIFT 0x0
#define CB_COLOR0_CLEAR_WORD0__CLEAR_WORD0_MASK 0xffffffff
#define CB_COLOR0_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0
#define CB_COLOR1_CLEAR_WORD0__CLEAR_WORD0_MASK 0xffffffff
#define CB_COLOR1_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0
#define CB_COLOR2_CLEAR_WORD0__CLEAR_WORD0_MASK 0xffffffff
#define CB_COLOR2_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0
#define CB_COLOR3_CLEAR_WORD0__CLEAR_WORD0_MASK 0xffffffff
#define CB_COLOR3_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0
#define CB_COLOR4_CLEAR_WORD0__CLEAR_WORD0_MASK 0xffffffff
#define CB_COLOR4_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0
#define CB_COLOR5_CLEAR_WORD0__CLEAR_WORD0_MASK 0xffffffff
#define CB_COLOR5_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0
#define CB_COLOR6_CLEAR_WORD0__CLEAR_WORD0_MASK 0xffffffff
#define CB_COLOR6_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0
#define CB_COLOR7_CLEAR_WORD0__CLEAR_WORD0_MASK 0xffffffff
#define CB_COLOR7_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0
#define CB_COLOR0_CLEAR_WORD1__CLEAR_WORD1_MASK 0xffffffff
#define CB_COLOR0_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0
#define CB_COLOR1_CLEAR_WORD1__CLEAR_WORD1_MASK 0xffffffff
#define CB_COLOR1_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0
#define CB_COLOR2_CLEAR_WORD1__CLEAR_WORD1_MASK 0xffffffff
#define CB_COLOR2_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0
#define CB_COLOR3_CLEAR_WORD1__CLEAR_WORD1_MASK 0xffffffff
#define CB_COLOR3_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0
#define CB_COLOR4_CLEAR_WORD1__CLEAR_WORD1_MASK 0xffffffff
#define CB_COLOR4_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0
#define CB_COLOR5_CLEAR_WORD1__CLEAR_WORD1_MASK 0xffffffff
#define CB_COLOR5_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0
#define CB_COLOR6_CLEAR_WORD1__CLEAR_WORD1_MASK 0xffffffff
#define CB_COLOR6_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0
#define CB_COLOR7_CLEAR_WORD1__CLEAR_WORD1_MASK 0xffffffff
#define CB_COLOR7_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0
#define CB_COLOR0_DCC_BASE__BASE_256B_MASK 0xffffffff
#define CB_COLOR0_DCC_BASE__BASE_256B__SHIFT 0x0
#define CB_COLOR1_DCC_BASE__BASE_256B_MASK 0xffffffff
#define CB_COLOR1_DCC_BASE__BASE_256B__SHIFT 0x0
#define CB_COLOR2_DCC_BASE__BASE_256B_MASK 0xffffffff
#define CB_COLOR2_DCC_BASE__BASE_256B__SHIFT 0x0
#define CB_COLOR3_DCC_BASE__BASE_256B_MASK 0xffffffff
#define CB_COLOR3_DCC_BASE__BASE_256B__SHIFT 0x0
#define CB_COLOR4_DCC_BASE__BASE_256B_MASK 0xffffffff
#define CB_COLOR4_DCC_BASE__BASE_256B__SHIFT 0x0
#define CB_COLOR5_DCC_BASE__BASE_256B_MASK 0xffffffff
#define CB_COLOR5_DCC_BASE__BASE_256B__SHIFT 0x0
#define CB_COLOR6_DCC_BASE__BASE_256B_MASK 0xffffffff
#define CB_COLOR6_DCC_BASE__BASE_256B__SHIFT 0x0
#define CB_COLOR7_DCC_BASE__BASE_256B_MASK 0xffffffff
#define CB_COLOR7_DCC_BASE__BASE_256B__SHIFT 0x0
#define CB_TARGET_MASK__TARGET0_ENABLE_MASK 0xf
#define CB_TARGET_MASK__TARGET0_ENABLE__SHIFT 0x0
#define CB_TARGET_MASK__TARGET1_ENABLE_MASK 0xf0
#define CB_TARGET_MASK__TARGET1_ENABLE__SHIFT 0x4
#define CB_TARGET_MASK__TARGET2_ENABLE_MASK 0xf00
#define CB_TARGET_MASK__TARGET2_ENABLE__SHIFT 0x8
#define CB_TARGET_MASK__TARGET3_ENABLE_MASK 0xf000
#define CB_TARGET_MASK__TARGET3_ENABLE__SHIFT 0xc
#define CB_TARGET_MASK__TARGET4_ENABLE_MASK 0xf0000
#define CB_TARGET_MASK__TARGET4_ENABLE__SHIFT 0x10
#define CB_TARGET_MASK__TARGET5_ENABLE_MASK 0xf00000
#define CB_TARGET_MASK__TARGET5_ENABLE__SHIFT 0x14
#define CB_TARGET_MASK__TARGET6_ENABLE_MASK 0xf000000
#define CB_TARGET_MASK__TARGET6_ENABLE__SHIFT 0x18
#define CB_TARGET_MASK__TARGET7_ENABLE_MASK 0xf0000000
#define CB_TARGET_MASK__TARGET7_ENABLE__SHIFT 0x1c
#define CB_SHADER_MASK__OUTPUT0_ENABLE_MASK 0xf
#define CB_SHADER_MASK__OUTPUT0_ENABLE__SHIFT 0x0
#define CB_SHADER_MASK__OUTPUT1_ENABLE_MASK 0xf0
#define CB_SHADER_MASK__OUTPUT1_ENABLE__SHIFT 0x4
#define CB_SHADER_MASK__OUTPUT2_ENABLE_MASK 0xf00
#define CB_SHADER_MASK__OUTPUT2_ENABLE__SHIFT 0x8
#define CB_SHADER_MASK__OUTPUT3_ENABLE_MASK 0xf000
#define CB_SHADER_MASK__OUTPUT3_ENABLE__SHIFT 0xc
#define CB_SHADER_MASK__OUTPUT4_ENABLE_MASK 0xf0000
#define CB_SHADER_MASK__OUTPUT4_ENABLE__SHIFT 0x10
#define CB_SHADER_MASK__OUTPUT5_ENABLE_MASK 0xf00000
#define CB_SHADER_MASK__OUTPUT5_ENABLE__SHIFT 0x14
#define CB_SHADER_MASK__OUTPUT6_ENABLE_MASK 0xf000000
#define CB_SHADER_MASK__OUTPUT6_ENABLE__SHIFT 0x18
#define CB_SHADER_MASK__OUTPUT7_ENABLE_MASK 0xf0000000
#define CB_SHADER_MASK__OUTPUT7_ENABLE__SHIFT 0x1c
#define CB_HW_CONTROL__CM_CACHE_EVICT_POINT_MASK 0xf
#define CB_HW_CONTROL__CM_CACHE_EVICT_POINT__SHIFT 0x0
#define CB_HW_CONTROL__FC_CACHE_EVICT_POINT_MASK 0x3c0
#define CB_HW_CONTROL__FC_CACHE_EVICT_POINT__SHIFT 0x6
#define CB_HW_CONTROL__CC_CACHE_EVICT_POINT_MASK 0xf000
#define CB_HW_CONTROL__CC_CACHE_EVICT_POINT__SHIFT 0xc
#define CB_HW_CONTROL__ALLOW_MRT_WITH_DUAL_SOURCE_MASK 0x10000
#define CB_HW_CONTROL__ALLOW_MRT_WITH_DUAL_SOURCE__SHIFT 0x10
#define CB_HW_CONTROL__DISABLE_INTNORM_LE11BPC_CLAMPING_MASK 0x40000
#define CB_HW_CONTROL__DISABLE_INTNORM_LE11BPC_CLAMPING__SHIFT 0x12
#define CB_HW_CONTROL__FORCE_NEEDS_DST_MASK 0x80000
#define CB_HW_CONTROL__FORCE_NEEDS_DST__SHIFT 0x13
#define CB_HW_CONTROL__FORCE_ALWAYS_TOGGLE_MASK 0x100000
#define CB_HW_CONTROL__FORCE_ALWAYS_TOGGLE__SHIFT 0x14
#define CB_HW_CONTROL__DISABLE_BLEND_OPT_RESULT_EQ_DEST_MASK 0x200000
#define CB_HW_CONTROL__DISABLE_BLEND_OPT_RESULT_EQ_DEST__SHIFT 0x15
#define CB_HW_CONTROL__DISABLE_FULL_WRITE_MASK_MASK 0x400000
#define CB_HW_CONTROL__DISABLE_FULL_WRITE_MASK__SHIFT 0x16
#define CB_HW_CONTROL__DISABLE_RESOLVE_OPT_FOR_SINGLE_FRAG_MASK 0x800000
#define CB_HW_CONTROL__DISABLE_RESOLVE_OPT_FOR_SINGLE_FRAG__SHIFT 0x17
#define CB_HW_CONTROL__DISABLE_BLEND_OPT_DONT_RD_DST_MASK 0x1000000
#define CB_HW_CONTROL__DISABLE_BLEND_OPT_DONT_RD_DST__SHIFT 0x18
#define CB_HW_CONTROL__DISABLE_BLEND_OPT_BYPASS_MASK 0x2000000
#define CB_HW_CONTROL__DISABLE_BLEND_OPT_BYPASS__SHIFT 0x19
#define CB_HW_CONTROL__DISABLE_BLEND_OPT_DISCARD_PIXEL_MASK 0x4000000
#define CB_HW_CONTROL__DISABLE_BLEND_OPT_DISCARD_PIXEL__SHIFT 0x1a
#define CB_HW_CONTROL__DISABLE_BLEND_OPT_WHEN_DISABLED_SRCALPHA_IS_USED_MASK 0x8000000
#define CB_HW_CONTROL__DISABLE_BLEND_OPT_WHEN_DISABLED_SRCALPHA_IS_USED__SHIFT 0x1b
#define CB_HW_CONTROL__PRIORITIZE_FC_WR_OVER_FC_RD_ON_CMASK_CONFLICT_MASK 0x10000000
#define CB_HW_CONTROL__PRIORITIZE_FC_WR_OVER_FC_RD_ON_CMASK_CONFLICT__SHIFT 0x1c
#define CB_HW_CONTROL__PRIORITIZE_FC_EVICT_OVER_FOP_RD_ON_BANK_CONFLICT_MASK 0x20000000
#define CB_HW_CONTROL__PRIORITIZE_FC_EVICT_OVER_FOP_RD_ON_BANK_CONFLICT__SHIFT 0x1d
#define CB_HW_CONTROL__DISABLE_CC_IB_SERIALIZER_STATE_OPT_MASK 0x40000000
#define CB_HW_CONTROL__DISABLE_CC_IB_SERIALIZER_STATE_OPT__SHIFT 0x1e
#define CB_HW_CONTROL__DISABLE_PIXEL_IN_QUAD_FIX_FOR_LINEAR_SURFACE_MASK 0x80000000
#define CB_HW_CONTROL__DISABLE_PIXEL_IN_QUAD_FIX_FOR_LINEAR_SURFACE__SHIFT 0x1f
#define CB_HW_CONTROL_1__CM_CACHE_NUM_TAGS_MASK 0x1f
#define CB_HW_CONTROL_1__CM_CACHE_NUM_TAGS__SHIFT 0x0
#define CB_HW_CONTROL_1__FC_CACHE_NUM_TAGS_MASK 0x7e0
#define CB_HW_CONTROL_1__FC_CACHE_NUM_TAGS__SHIFT 0x5
#define CB_HW_CONTROL_1__CC_CACHE_NUM_TAGS_MASK 0x1f800
#define CB_HW_CONTROL_1__CC_CACHE_NUM_TAGS__SHIFT 0xb
#define CB_HW_CONTROL_1__CM_TILE_FIFO_DEPTH_MASK 0x3fe0000
#define CB_HW_CONTROL_1__CM_TILE_FIFO_DEPTH__SHIFT 0x11
#define CB_HW_CONTROL_1__CHICKEN_BITS_MASK 0xfc000000
#define CB_HW_CONTROL_1__CHICKEN_BITS__SHIFT 0x1a
#define CB_HW_CONTROL_2__CC_EVEN_ODD_FIFO_DEPTH_MASK 0xff
#define CB_HW_CONTROL_2__CC_EVEN_ODD_FIFO_DEPTH__SHIFT 0x0
#define CB_HW_CONTROL_2__FC_RDLAT_TILE_FIFO_DEPTH_MASK 0x7f00
#define CB_HW_CONTROL_2__FC_RDLAT_TILE_FIFO_DEPTH__SHIFT 0x8
#define CB_HW_CONTROL_2__FC_RDLAT_QUAD_FIFO_DEPTH_MASK 0x7f8000
#define CB_HW_CONTROL_2__FC_RDLAT_QUAD_FIFO_DEPTH__SHIFT 0xf
#define CB_HW_CONTROL_2__DRR_ASSUMED_FIFO_DEPTH_DIV8_MASK 0xf000000
#define CB_HW_CONTROL_2__DRR_ASSUMED_FIFO_DEPTH_DIV8__SHIFT 0x18
#define CB_HW_CONTROL_2__CHICKEN_BITS_MASK 0xf0000000
#define CB_HW_CONTROL_2__CHICKEN_BITS__SHIFT 0x1c
#define CB_HW_CONTROL_3__DISABLE_SLOW_MODE_EMPTY_HALF_QUAD_KILL_MASK 0x1
#define CB_HW_CONTROL_3__DISABLE_SLOW_MODE_EMPTY_HALF_QUAD_KILL__SHIFT 0x0
#define CB_HW_CONTROL_3__RAM_ADDRESS_CONFLICTS_DISALLOWED_MASK 0x2
#define CB_HW_CONTROL_3__RAM_ADDRESS_CONFLICTS_DISALLOWED__SHIFT 0x1
#define CB_HW_CONTROL_3__DISABLE_FAST_CLEAR_FETCH_OPT_MASK 0x4
#define CB_HW_CONTROL_3__DISABLE_FAST_CLEAR_FETCH_OPT__SHIFT 0x2
#define CB_HW_CONTROL_3__DISABLE_QUAD_MARKER_DROP_STOP_MASK 0x8
#define CB_HW_CONTROL_3__DISABLE_QUAD_MARKER_DROP_STOP__SHIFT 0x3
#define CB_HW_CONTROL_3__DISABLE_OVERWRITE_COMBINER_CAM_CLR_MASK 0x10
#define CB_HW_CONTROL_3__DISABLE_OVERWRITE_COMBINER_CAM_CLR__SHIFT 0x4
#define CB_HW_CONTROL_3__DISABLE_CC_CACHE_OVWR_STATUS_ACCUM_MASK 0x20
#define CB_HW_CONTROL_3__DISABLE_CC_CACHE_OVWR_STATUS_ACCUM__SHIFT 0x5
#define CB_HW_CONTROL_3__DISABLE_CC_CACHE_OVWR_KEY_MOD_MASK 0x40
#define CB_HW_CONTROL_3__DISABLE_CC_CACHE_OVWR_KEY_MOD__SHIFT 0x6
#define CB_HW_CONTROL_3__DISABLE_CC_CACHE_PANIC_GATING_MASK 0x80
#define CB_HW_CONTROL_3__DISABLE_CC_CACHE_PANIC_GATING__SHIFT 0x7
#define CB_HW_CONTROL_3__DISABLE_OVERWRITE_COMBINER_TARGET_MASK_VALIDATION_MASK 0x100
#define CB_HW_CONTROL_3__DISABLE_OVERWRITE_COMBINER_TARGET_MASK_VALIDATION__SHIFT 0x8
#define CB_DCC_CONFIG__OVERWRITE_COMBINER_DEPTH_MASK 0x1f
#define CB_DCC_CONFIG__OVERWRITE_COMBINER_DEPTH__SHIFT 0x0
#define CB_DCC_CONFIG__OVERWRITE_COMBINER_DISABLE_MASK 0x20
#define CB_DCC_CONFIG__OVERWRITE_COMBINER_DISABLE__SHIFT 0x5
#define CB_DCC_CONFIG__OVERWRITE_COMBINER_CC_POP_DISABLE_MASK 0x40
#define CB_DCC_CONFIG__OVERWRITE_COMBINER_CC_POP_DISABLE__SHIFT 0x6
#define CB_DCC_CONFIG__FC_RDLAT_KEYID_FIFO_DEPTH_MASK 0xff00
#define CB_DCC_CONFIG__FC_RDLAT_KEYID_FIFO_DEPTH__SHIFT 0x8
#define CB_DCC_CONFIG__READ_RETURN_SKID_FIFO_DEPTH_MASK 0x7f0000
#define CB_DCC_CONFIG__READ_RETURN_SKID_FIFO_DEPTH__SHIFT 0x10
#define CB_DCC_CONFIG__DCC_CACHE_EVICT_POINT_MASK 0xf000000
#define CB_DCC_CONFIG__DCC_CACHE_EVICT_POINT__SHIFT 0x18
#define CB_DCC_CONFIG__DCC_CACHE_NUM_TAGS_MASK 0xf0000000
#define CB_DCC_CONFIG__DCC_CACHE_NUM_TAGS__SHIFT 0x1c
#define CB_PERFCOUNTER_FILTER__OP_FILTER_ENABLE_MASK 0x1
#define CB_PERFCOUNTER_FILTER__OP_FILTER_ENABLE__SHIFT 0x0
#define CB_PERFCOUNTER_FILTER__OP_FILTER_SEL_MASK 0xe
#define CB_PERFCOUNTER_FILTER__OP_FILTER_SEL__SHIFT 0x1
#define CB_PERFCOUNTER_FILTER__FORMAT_FILTER_ENABLE_MASK 0x10
#define CB_PERFCOUNTER_FILTER__FORMAT_FILTER_ENABLE__SHIFT 0x4
#define CB_PERFCOUNTER_FILTER__FORMAT_FILTER_SEL_MASK 0x3e0
#define CB_PERFCOUNTER_FILTER__FORMAT_FILTER_SEL__SHIFT 0x5
#define CB_PERFCOUNTER_FILTER__CLEAR_FILTER_ENABLE_MASK 0x400
#define CB_PERFCOUNTER_FILTER__CLEAR_FILTER_ENABLE__SHIFT 0xa
#define CB_PERFCOUNTER_FILTER__CLEAR_FILTER_SEL_MASK 0x800
#define CB_PERFCOUNTER_FILTER__CLEAR_FILTER_SEL__SHIFT 0xb
#define CB_PERFCOUNTER_FILTER__MRT_FILTER_ENABLE_MASK 0x1000
#define CB_PERFCOUNTER_FILTER__MRT_FILTER_ENABLE__SHIFT 0xc
#define CB_PERFCOUNTER_FILTER__MRT_FILTER_SEL_MASK 0xe000
#define CB_PERFCOUNTER_FILTER__MRT_FILTER_SEL__SHIFT 0xd
#define CB_PERFCOUNTER_FILTER__NUM_SAMPLES_FILTER_ENABLE_MASK 0x20000
#define CB_PERFCOUNTER_FILTER__NUM_SAMPLES_FILTER_ENABLE__SHIFT 0x11
#define CB_PERFCOUNTER_FILTER__NUM_SAMPLES_FILTER_SEL_MASK 0x1c0000
#define CB_PERFCOUNTER_FILTER__NUM_SAMPLES_FILTER_SEL__SHIFT 0x12
#define CB_PERFCOUNTER_FILTER__NUM_FRAGMENTS_FILTER_ENABLE_MASK 0x200000
#define CB_PERFCOUNTER_FILTER__NUM_FRAGMENTS_FILTER_ENABLE__SHIFT 0x15
#define CB_PERFCOUNTER_FILTER__NUM_FRAGMENTS_FILTER_SEL_MASK 0xc00000
#define CB_PERFCOUNTER_FILTER__NUM_FRAGMENTS_FILTER_SEL__SHIFT 0x16
#define CB_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x1ff
#define CB_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
#define CB_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x7fc00
#define CB_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
#define CB_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000
#define CB_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
#define CB_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0xf000000
#define CB_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18
#define CB_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xf0000000
#define CB_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c
#define CB_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x1ff
#define CB_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0
#define CB_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x7fc00
#define CB_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
#define CB_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0xf000000
#define CB_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18
#define CB_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xf0000000
#define CB_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c
#define CB_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x1ff
#define CB_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
#define CB_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xf0000000
#define CB_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c
#define CB_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x1ff
#define CB_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0
#define CB_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xf0000000
#define CB_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c
#define CB_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x1ff
#define CB_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0
#define CB_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xf0000000
#define CB_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c
#define CB_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff
#define CB_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
#define CB_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff
#define CB_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
#define CB_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffff
#define CB_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0
#define CB_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffff
#define CB_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0
#define CB_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff
#define CB_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
#define CB_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff
#define CB_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
#define CB_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffff
#define CB_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0
#define CB_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffff
#define CB_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0
#define CB_CGTT_SCLK_CTRL__ON_DELAY_MASK 0xf
#define CB_CGTT_SCLK_CTRL__ON_DELAY__SHIFT 0x0
#define CB_CGTT_SCLK_CTRL__OFF_HYSTERESIS_MASK 0xff0
#define CB_CGTT_SCLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE7_MASK 0x1000000
#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18
#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE6_MASK 0x2000000
#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19
#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE5_MASK 0x4000000
#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a
#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE4_MASK 0x8000000
#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b
#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000
#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c
#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000
#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d
#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000
#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e
#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000
#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f
#define CB_DEBUG_BUS_17__TILE_INTFC_BUSY_MASK 0x1
#define CB_DEBUG_BUS_17__TILE_INTFC_BUSY__SHIFT 0x0
#define CB_DEBUG_BUS_17__MU_BUSY_MASK 0x2
#define CB_DEBUG_BUS_17__MU_BUSY__SHIFT 0x1
#define CB_DEBUG_BUS_17__TQ_BUSY_MASK 0x4
#define CB_DEBUG_BUS_17__TQ_BUSY__SHIFT 0x2
#define CB_DEBUG_BUS_17__AC_BUSY_MASK 0x8
#define CB_DEBUG_BUS_17__AC_BUSY__SHIFT 0x3
#define CB_DEBUG_BUS_17__CRW_BUSY_MASK 0x10
#define CB_DEBUG_BUS_17__CRW_BUSY__SHIFT 0x4
#define CB_DEBUG_BUS_17__CACHE_CTRL_BUSY_MASK 0x20
#define CB_DEBUG_BUS_17__CACHE_CTRL_BUSY__SHIFT 0x5
#define CB_DEBUG_BUS_17__MC_WR_PENDING_MASK 0x40
#define CB_DEBUG_BUS_17__MC_WR_PENDING__SHIFT 0x6
#define CB_DEBUG_BUS_17__FC_WR_PENDING_MASK 0x80
#define CB_DEBUG_BUS_17__FC_WR_PENDING__SHIFT 0x7
#define CB_DEBUG_BUS_17__FC_RD_PENDING_MASK 0x100
#define CB_DEBUG_BUS_17__FC_RD_PENDING__SHIFT 0x8
#define CB_DEBUG_BUS_17__EVICT_PENDING_MASK 0x200
#define CB_DEBUG_BUS_17__EVICT_PENDING__SHIFT 0x9
#define CB_DEBUG_BUS_17__LAST_RD_ARB_WINNER_MASK 0x400
#define CB_DEBUG_BUS_17__LAST_RD_ARB_WINNER__SHIFT 0xa
#define CB_DEBUG_BUS_17__MU_STATE_MASK 0x7f800
#define CB_DEBUG_BUS_17__MU_STATE__SHIFT 0xb
#define CB_DEBUG_BUS_18__TILE_RETIREMENT_BUSY_MASK 0x1
#define CB_DEBUG_BUS_18__TILE_RETIREMENT_BUSY__SHIFT 0x0
#define CB_DEBUG_BUS_18__FOP_BUSY_MASK 0x2
#define CB_DEBUG_BUS_18__FOP_BUSY__SHIFT 0x1
#define CB_DEBUG_BUS_18__CLEAR_BUSY_MASK 0x4
#define CB_DEBUG_BUS_18__CLEAR_BUSY__SHIFT 0x2
#define CB_DEBUG_BUS_18__LAT_BUSY_MASK 0x8
#define CB_DEBUG_BUS_18__LAT_BUSY__SHIFT 0x3
#define CB_DEBUG_BUS_18__CACHE_CTL_BUSY_MASK 0x10
#define CB_DEBUG_BUS_18__CACHE_CTL_BUSY__SHIFT 0x4
#define CB_DEBUG_BUS_18__ADDR_BUSY_MASK 0x20
#define CB_DEBUG_BUS_18__ADDR_BUSY__SHIFT 0x5
#define CB_DEBUG_BUS_18__MERGE_BUSY_MASK 0x40
#define CB_DEBUG_BUS_18__MERGE_BUSY__SHIFT 0x6
#define CB_DEBUG_BUS_18__QUAD_BUSY_MASK 0x80
#define CB_DEBUG_BUS_18__QUAD_BUSY__SHIFT 0x7
#define CB_DEBUG_BUS_18__TILE_BUSY_MASK 0x100
#define CB_DEBUG_BUS_18__TILE_BUSY__SHIFT 0x8
#define CB_DEBUG_BUS_18__DCC_BUSY_MASK 0x200
#define CB_DEBUG_BUS_18__DCC_BUSY__SHIFT 0x9
#define CB_DEBUG_BUS_18__DOC_BUSY_MASK 0x400
#define CB_DEBUG_BUS_18__DOC_BUSY__SHIFT 0xa
#define CB_DEBUG_BUS_18__DAG_BUSY_MASK 0x800
#define CB_DEBUG_BUS_18__DAG_BUSY__SHIFT 0xb
#define CB_DEBUG_BUS_18__DOC_STALL_MASK 0x1000
#define CB_DEBUG_BUS_18__DOC_STALL__SHIFT 0xc
#define CB_DEBUG_BUS_18__DOC_QT_CAM_FULL_MASK 0x2000
#define CB_DEBUG_BUS_18__DOC_QT_CAM_FULL__SHIFT 0xd
#define CB_DEBUG_BUS_18__DOC_CL_CAM_FULL_MASK 0x4000
#define CB_DEBUG_BUS_18__DOC_CL_CAM_FULL__SHIFT 0xe
#define CB_DEBUG_BUS_18__DOC_QUAD_PTR_FIFO_FULL_MASK 0x8000
#define CB_DEBUG_BUS_18__DOC_QUAD_PTR_FIFO_FULL__SHIFT 0xf
#define CB_DEBUG_BUS_18__DOC_SECTOR_MASK_FIFO_FULL_MASK 0x10000
#define CB_DEBUG_BUS_18__DOC_SECTOR_MASK_FIFO_FULL__SHIFT 0x10
#define CB_DEBUG_BUS_18__DCS_READ_WINNER_LAST_MASK 0x20000
#define CB_DEBUG_BUS_18__DCS_READ_WINNER_LAST__SHIFT 0x11
#define CB_DEBUG_BUS_18__DCS_READ_EV_PENDING_MASK 0x40000
#define CB_DEBUG_BUS_18__DCS_READ_EV_PENDING__SHIFT 0x12
#define CB_DEBUG_BUS_18__DCS_WRITE_CC_PENDING_MASK 0x80000
#define CB_DEBUG_BUS_18__DCS_WRITE_CC_PENDING__SHIFT 0x13
#define CB_DEBUG_BUS_18__DCS_READ_CC_PENDING_MASK 0x100000
#define CB_DEBUG_BUS_18__DCS_READ_CC_PENDING__SHIFT 0x14
#define CB_DEBUG_BUS_18__DCS_WRITE_MC_PENDING_MASK 0x200000
#define CB_DEBUG_BUS_18__DCS_WRITE_MC_PENDING__SHIFT 0x15
#define CB_DEBUG_BUS_19__SURF_SYNC_STATE_MASK 0x3
#define CB_DEBUG_BUS_19__SURF_SYNC_STATE__SHIFT 0x0
#define CB_DEBUG_BUS_19__SURF_SYNC_START_MASK 0x4
#define CB_DEBUG_BUS_19__SURF_SYNC_START__SHIFT 0x2
#define CB_DEBUG_BUS_19__SF_BUSY_MASK 0x8
#define CB_DEBUG_BUS_19__SF_BUSY__SHIFT 0x3
#define CB_DEBUG_BUS_19__CS_BUSY_MASK 0x10
#define CB_DEBUG_BUS_19__CS_BUSY__SHIFT 0x4
#define CB_DEBUG_BUS_19__RB_BUSY_MASK 0x20
#define CB_DEBUG_BUS_19__RB_BUSY__SHIFT 0x5
#define CB_DEBUG_BUS_19__DS_BUSY_MASK 0x40
#define CB_DEBUG_BUS_19__DS_BUSY__SHIFT 0x6
#define CB_DEBUG_BUS_19__TB_BUSY_MASK 0x80
#define CB_DEBUG_BUS_19__TB_BUSY__SHIFT 0x7
#define CB_DEBUG_BUS_19__IB_BUSY_MASK 0x100
#define CB_DEBUG_BUS_19__IB_BUSY__SHIFT 0x8
#define CB_DEBUG_BUS_19__DRR_BUSY_MASK 0x200
#define CB_DEBUG_BUS_19__DRR_BUSY__SHIFT 0x9
#define CB_DEBUG_BUS_19__DF_BUSY_MASK 0x400
#define CB_DEBUG_BUS_19__DF_BUSY__SHIFT 0xa
#define CB_DEBUG_BUS_19__DD_BUSY_MASK 0x800
#define CB_DEBUG_BUS_19__DD_BUSY__SHIFT 0xb
#define CB_DEBUG_BUS_19__DC_BUSY_MASK 0x1000
#define CB_DEBUG_BUS_19__DC_BUSY__SHIFT 0xc
#define CB_DEBUG_BUS_19__DK_BUSY_MASK 0x2000
#define CB_DEBUG_BUS_19__DK_BUSY__SHIFT 0xd
#define CB_DEBUG_BUS_19__DF_SKID_FIFO_EMPTY_MASK 0x4000
#define CB_DEBUG_BUS_19__DF_SKID_FIFO_EMPTY__SHIFT 0xe
#define CB_DEBUG_BUS_19__DF_CLEAR_FIFO_EMPTY_MASK 0x8000
#define CB_DEBUG_BUS_19__DF_CLEAR_FIFO_EMPTY__SHIFT 0xf
#define CB_DEBUG_BUS_19__DD_READY_MASK 0x10000
#define CB_DEBUG_BUS_19__DD_READY__SHIFT 0x10
#define CB_DEBUG_BUS_19__DC_FIFO_FULL_MASK 0x20000
#define CB_DEBUG_BUS_19__DC_FIFO_FULL__SHIFT 0x11
#define CB_DEBUG_BUS_19__DC_READY_MASK 0x40000
#define CB_DEBUG_BUS_19__DC_READY__SHIFT 0x12
#define CB_DEBUG_BUS_20__MC_RDREQ_CREDITS_MASK 0x3f
#define CB_DEBUG_BUS_20__MC_RDREQ_CREDITS__SHIFT 0x0
#define CB_DEBUG_BUS_20__MC_WRREQ_CREDITS_MASK 0xfc0
#define CB_DEBUG_BUS_20__MC_WRREQ_CREDITS__SHIFT 0x6
#define CB_DEBUG_BUS_20__CC_RDREQ_HAD_ITS_TURN_MASK 0x1000
#define CB_DEBUG_BUS_20__CC_RDREQ_HAD_ITS_TURN__SHIFT 0xc
#define CB_DEBUG_BUS_20__FC_RDREQ_HAD_ITS_TURN_MASK 0x2000
#define CB_DEBUG_BUS_20__FC_RDREQ_HAD_ITS_TURN__SHIFT 0xd
#define CB_DEBUG_BUS_20__CM_RDREQ_HAD_ITS_TURN_MASK 0x4000
#define CB_DEBUG_BUS_20__CM_RDREQ_HAD_ITS_TURN__SHIFT 0xe
#define CB_DEBUG_BUS_20__CC_WRREQ_HAD_ITS_TURN_MASK 0x10000
#define CB_DEBUG_BUS_20__CC_WRREQ_HAD_ITS_TURN__SHIFT 0x10
#define CB_DEBUG_BUS_20__FC_WRREQ_HAD_ITS_TURN_MASK 0x20000
#define CB_DEBUG_BUS_20__FC_WRREQ_HAD_ITS_TURN__SHIFT 0x11
#define CB_DEBUG_BUS_20__CM_WRREQ_HAD_ITS_TURN_MASK 0x40000
#define CB_DEBUG_BUS_20__CM_WRREQ_HAD_ITS_TURN__SHIFT 0x12
#define CB_DEBUG_BUS_20__CC_WRREQ_FIFO_EMPTY_MASK 0x100000
#define CB_DEBUG_BUS_20__CC_WRREQ_FIFO_EMPTY__SHIFT 0x14
#define CB_DEBUG_BUS_20__FC_WRREQ_FIFO_EMPTY_MASK 0x200000
#define CB_DEBUG_BUS_20__FC_WRREQ_FIFO_EMPTY__SHIFT 0x15
#define CB_DEBUG_BUS_20__CM_WRREQ_FIFO_EMPTY_MASK 0x400000
#define CB_DEBUG_BUS_20__CM_WRREQ_FIFO_EMPTY__SHIFT 0x16
#define CB_DEBUG_BUS_20__DCC_WRREQ_FIFO_EMPTY_MASK 0x800000
#define CB_DEBUG_BUS_20__DCC_WRREQ_FIFO_EMPTY__SHIFT 0x17
#define CB_DEBUG_BUS_21__CM_BUSY_MASK 0x1
#define CB_DEBUG_BUS_21__CM_BUSY__SHIFT 0x0
#define CB_DEBUG_BUS_21__FC_BUSY_MASK 0x2
#define CB_DEBUG_BUS_21__FC_BUSY__SHIFT 0x1
#define CB_DEBUG_BUS_21__CC_BUSY_MASK 0x4
#define CB_DEBUG_BUS_21__CC_BUSY__SHIFT 0x2
#define CB_DEBUG_BUS_21__BB_BUSY_MASK 0x8
#define CB_DEBUG_BUS_21__BB_BUSY__SHIFT 0x3
#define CB_DEBUG_BUS_21__MA_BUSY_MASK 0x10
#define CB_DEBUG_BUS_21__MA_BUSY__SHIFT 0x4
#define CB_DEBUG_BUS_21__CORE_SCLK_VLD_MASK 0x20
#define CB_DEBUG_BUS_21__CORE_SCLK_VLD__SHIFT 0x5
#define CB_DEBUG_BUS_21__REG_SCLK1_VLD_MASK 0x40
#define CB_DEBUG_BUS_21__REG_SCLK1_VLD__SHIFT 0x6
#define CB_DEBUG_BUS_21__REG_SCLK0_VLD_MASK 0x80
#define CB_DEBUG_BUS_21__REG_SCLK0_VLD__SHIFT 0x7
#define CB_DEBUG_BUS_22__OUTSTANDING_MC_READS_MASK 0xfff
#define CB_DEBUG_BUS_22__OUTSTANDING_MC_READS__SHIFT 0x0
#define CB_DEBUG_BUS_22__OUTSTANDING_MC_WRITES_MASK 0xfff000
#define CB_DEBUG_BUS_22__OUTSTANDING_MC_WRITES__SHIFT 0xc
#define CP_DFY_CNTL__POLICY_MASK 0x1
#define CP_DFY_CNTL__POLICY__SHIFT 0x0
#define CP_DFY_CNTL__MTYPE_MASK 0xc
#define CP_DFY_CNTL__MTYPE__SHIFT 0x2
#define CP_DFY_CNTL__LFSR_RESET_MASK 0x10000000
#define CP_DFY_CNTL__LFSR_RESET__SHIFT 0x1c
#define CP_DFY_CNTL__MODE_MASK 0x60000000
#define CP_DFY_CNTL__MODE__SHIFT 0x1d
#define CP_DFY_CNTL__ENABLE_MASK 0x80000000
#define CP_DFY_CNTL__ENABLE__SHIFT 0x1f
#define CP_DFY_STAT__BURST_COUNT_MASK 0xffff
#define CP_DFY_STAT__BURST_COUNT__SHIFT 0x0
#define CP_DFY_STAT__TAGS_PENDING_MASK 0x1ff0000
#define CP_DFY_STAT__TAGS_PENDING__SHIFT 0x10
#define CP_DFY_STAT__BUSY_MASK 0x80000000
#define CP_DFY_STAT__BUSY__SHIFT 0x1f
#define CP_DFY_ADDR_HI__ADDR_HI_MASK 0xffffffff
#define CP_DFY_ADDR_HI__ADDR_HI__SHIFT 0x0
#define CP_DFY_ADDR_LO__ADDR_LO_MASK 0xffffffe0
#define CP_DFY_ADDR_LO__ADDR_LO__SHIFT 0x5
#define CP_DFY_DATA_0__DATA_MASK 0xffffffff
#define CP_DFY_DATA_0__DATA__SHIFT 0x0
#define CP_DFY_DATA_1__DATA_MASK 0xffffffff
#define CP_DFY_DATA_1__DATA__SHIFT 0x0
#define CP_DFY_DATA_2__DATA_MASK 0xffffffff
#define CP_DFY_DATA_2__DATA__SHIFT 0x0
#define CP_DFY_DATA_3__DATA_MASK 0xffffffff
#define CP_DFY_DATA_3__DATA__SHIFT 0x0
#define CP_DFY_DATA_4__DATA_MASK 0xffffffff
#define CP_DFY_DATA_4__DATA__SHIFT 0x0
#define CP_DFY_DATA_5__DATA_MASK 0xffffffff
#define CP_DFY_DATA_5__DATA__SHIFT 0x0
#define CP_DFY_DATA_6__DATA_MASK 0xffffffff
#define CP_DFY_DATA_6__DATA__SHIFT 0x0
#define CP_DFY_DATA_7__DATA_MASK 0xffffffff
#define CP_DFY_DATA_7__DATA__SHIFT 0x0
#define CP_DFY_DATA_8__DATA_MASK 0xffffffff
#define CP_DFY_DATA_8__DATA__SHIFT 0x0
#define CP_DFY_DATA_9__DATA_MASK 0xffffffff
#define CP_DFY_DATA_9__DATA__SHIFT 0x0
#define CP_DFY_DATA_10__DATA_MASK 0xffffffff
#define CP_DFY_DATA_10__DATA__SHIFT 0x0
#define CP_DFY_DATA_11__DATA_MASK 0xffffffff
#define CP_DFY_DATA_11__DATA__SHIFT 0x0
#define CP_DFY_DATA_12__DATA_MASK 0xffffffff
#define CP_DFY_DATA_12__DATA__SHIFT 0x0
#define CP_DFY_DATA_13__DATA_MASK 0xffffffff
#define CP_DFY_DATA_13__DATA__SHIFT 0x0
#define CP_DFY_DATA_14__DATA_MASK 0xffffffff
#define CP_DFY_DATA_14__DATA__SHIFT 0x0
#define CP_DFY_DATA_15__DATA_MASK 0xffffffff
#define CP_DFY_DATA_15__DATA__SHIFT 0x0
#define CP_DFY_CMD__OFFSET_MASK 0x1ff
#define CP_DFY_CMD__OFFSET__SHIFT 0x0
#define CP_DFY_CMD__SIZE_MASK 0xffff0000
#define CP_DFY_CMD__SIZE__SHIFT 0x10
#define CP_CPC_MGCG_SYNC_CNTL__COOLDOWN_PERIOD_MASK 0xff
#define CP_CPC_MGCG_SYNC_CNTL__COOLDOWN_PERIOD__SHIFT 0x0
#define CP_CPC_MGCG_SYNC_CNTL__WARMUP_PERIOD_MASK 0xff00
#define CP_CPC_MGCG_SYNC_CNTL__WARMUP_PERIOD__SHIFT 0x8
#define CP_RB0_BASE__RB_BASE_MASK 0xffffffff
#define CP_RB0_BASE__RB_BASE__SHIFT 0x0
#define CP_RB0_BASE_HI__RB_BASE_HI_MASK 0xff
#define CP_RB0_BASE_HI__RB_BASE_HI__SHIFT 0x0
#define CP_RB_BASE__RB_BASE_MASK 0xffffffff
#define CP_RB_BASE__RB_BASE__SHIFT 0x0
#define CP_RB1_BASE__RB_BASE_MASK 0xffffffff
#define CP_RB1_BASE__RB_BASE__SHIFT 0x0
#define CP_RB1_BASE_HI__RB_BASE_HI_MASK 0xff
#define CP_RB1_BASE_HI__RB_BASE_HI__SHIFT 0x0
#define CP_RB2_BASE__RB_BASE_MASK 0xffffffff
#define CP_RB2_BASE__RB_BASE__SHIFT 0x0
#define CP_RB0_CNTL__RB_BUFSZ_MASK 0x3f
#define CP_RB0_CNTL__RB_BUFSZ__SHIFT 0x0
#define CP_RB0_CNTL__RB_BLKSZ_MASK 0x3f00
#define CP_RB0_CNTL__RB_BLKSZ__SHIFT 0x8
#define CP_RB0_CNTL__MTYPE_MASK 0x18000
#define CP_RB0_CNTL__MTYPE__SHIFT 0xf
#define CP_RB0_CNTL__BUF_SWAP_MASK 0x60000
#define CP_RB0_CNTL__BUF_SWAP__SHIFT 0x11
#define CP_RB0_CNTL__MIN_AVAILSZ_MASK 0x300000
#define CP_RB0_CNTL__MIN_AVAILSZ__SHIFT 0x14
#define CP_RB0_CNTL__MIN_IB_AVAILSZ_MASK 0xc00000
#define CP_RB0_CNTL__MIN_IB_AVAILSZ__SHIFT 0x16
#define CP_RB0_CNTL__CACHE_POLICY_MASK 0x1000000
#define CP_RB0_CNTL__CACHE_POLICY__SHIFT 0x18
#define CP_RB0_CNTL__RB_NO_UPDATE_MASK 0x8000000
#define CP_RB0_CNTL__RB_NO_UPDATE__SHIFT 0x1b
#define CP_RB0_CNTL__RB_RPTR_WR_ENA_MASK 0x80000000
#define CP_RB0_CNTL__RB_RPTR_WR_ENA__SHIFT 0x1f
#define CP_RB_CNTL__RB_BUFSZ_MASK 0x3f
#define CP_RB_CNTL__RB_BUFSZ__SHIFT 0x0
#define CP_RB_CNTL__RB_BLKSZ_MASK 0x3f00
#define CP_RB_CNTL__RB_BLKSZ__SHIFT 0x8
#define CP_RB_CNTL__MTYPE_MASK 0x18000
#define CP_RB_CNTL__MTYPE__SHIFT 0xf
#define CP_RB_CNTL__BUF_SWAP_MASK 0x60000
#define CP_RB_CNTL__BUF_SWAP__SHIFT 0x11
#define CP_RB_CNTL__MIN_AVAILSZ_MASK 0x300000
#define CP_RB_CNTL__MIN_AVAILSZ__SHIFT 0x14
#define CP_RB_CNTL__MIN_IB_AVAILSZ_MASK 0xc00000
#define CP_RB_CNTL__MIN_IB_AVAILSZ__SHIFT 0x16
#define CP_RB_CNTL__CACHE_POLICY_MASK 0x1000000
#define CP_RB_CNTL__CACHE_POLICY__SHIFT 0x18
#define CP_RB_CNTL__RB_NO_UPDATE_MASK 0x8000000
#define CP_RB_CNTL__RB_NO_UPDATE__SHIFT 0x1b
#define CP_RB_CNTL__RB_RPTR_WR_ENA_MASK 0x80000000
#define CP_RB_CNTL__RB_RPTR_WR_ENA__SHIFT 0x1f
#define CP_RB1_CNTL__RB_BUFSZ_MASK 0x3f
#define CP_RB1_CNTL__RB_BUFSZ__SHIFT 0x0
#define CP_RB1_CNTL__RB_BLKSZ_MASK 0x3f00
#define CP_RB1_CNTL__RB_BLKSZ__SHIFT 0x8
#define CP_RB1_CNTL__MTYPE_MASK 0x18000
#define CP_RB1_CNTL__MTYPE__SHIFT 0xf
#define CP_RB1_CNTL__MIN_AVAILSZ_MASK 0x300000
#define CP_RB1_CNTL__MIN_AVAILSZ__SHIFT 0x14
#define CP_RB1_CNTL__MIN_IB_AVAILSZ_MASK 0xc00000
#define CP_RB1_CNTL__MIN_IB_AVAILSZ__SHIFT 0x16
#define CP_RB1_CNTL__CACHE_POLICY_MASK 0x1000000
#define CP_RB1_CNTL__CACHE_POLICY__SHIFT 0x18
#define CP_RB1_CNTL__RB_NO_UPDATE_MASK 0x8000000
#define CP_RB1_CNTL__RB_NO_UPDATE__SHIFT 0x1b
#define CP_RB1_CNTL__RB_RPTR_WR_ENA_MASK 0x80000000
#define CP_RB1_CNTL__RB_RPTR_WR_ENA__SHIFT 0x1f
#define CP_RB2_CNTL__RB_BUFSZ_MASK 0x3f
#define CP_RB2_CNTL__RB_BUFSZ__SHIFT 0x0
#define CP_RB2_CNTL__RB_BLKSZ_MASK 0x3f00
#define CP_RB2_CNTL__RB_BLKSZ__SHIFT 0x8
#define CP_RB2_CNTL__MTYPE_MASK 0x18000
#define CP_RB2_CNTL__MTYPE__SHIFT 0xf
#define CP_RB2_CNTL__MIN_AVAILSZ_MASK 0x300000
#define CP_RB2_CNTL__MIN_AVAILSZ__SHIFT 0x14
#define CP_RB2_CNTL__MIN_IB_AVAILSZ_MASK 0xc00000
#define CP_RB2_CNTL__MIN_IB_AVAILSZ__SHIFT 0x16
#define CP_RB2_CNTL__CACHE_POLICY_MASK 0x1000000
#define CP_RB2_CNTL__CACHE_POLICY__SHIFT 0x18
#define CP_RB2_CNTL__RB_NO_UPDATE_MASK 0x8000000
#define CP_RB2_CNTL__RB_NO_UPDATE__SHIFT 0x1b
#define CP_RB2_CNTL__RB_RPTR_WR_ENA_MASK 0x80000000
#define CP_RB2_CNTL__RB_RPTR_WR_ENA__SHIFT 0x1f
#define CP_RB_RPTR_WR__RB_RPTR_WR_MASK 0xfffff
#define CP_RB_RPTR_WR__RB_RPTR_WR__SHIFT 0x0
#define CP_RB0_RPTR_ADDR__RB_RPTR_SWAP_MASK 0x3
#define CP_RB0_RPTR_ADDR__RB_RPTR_SWAP__SHIFT 0x0
#define CP_RB0_RPTR_ADDR__RB_RPTR_ADDR_MASK 0xfffffffc
#define CP_RB0_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x2
#define CP_RB_RPTR_ADDR__RB_RPTR_SWAP_MASK 0x3
#define CP_RB_RPTR_ADDR__RB_RPTR_SWAP__SHIFT 0x0
#define CP_RB_RPTR_ADDR__RB_RPTR_ADDR_MASK 0xfffffffc
#define CP_RB_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x2
#define CP_RB1_RPTR_ADDR__RB_RPTR_SWAP_MASK 0x3
#define CP_RB1_RPTR_ADDR__RB_RPTR_SWAP__SHIFT 0x0
#define CP_RB1_RPTR_ADDR__RB_RPTR_ADDR_MASK 0xfffffffc
#define CP_RB1_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x2
#define CP_RB2_RPTR_ADDR__RB_RPTR_SWAP_MASK 0x3
#define CP_RB2_RPTR_ADDR__RB_RPTR_SWAP__SHIFT 0x0
#define CP_RB2_RPTR_ADDR__RB_RPTR_ADDR_MASK 0xfffffffc
#define CP_RB2_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x2
#define CP_RB0_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK 0xffff
#define CP_RB0_RPTR_ADDR_HI__RB_RPTR_ADDR_HI__SHIFT 0x0
#define CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK 0xffff
#define CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI__SHIFT 0x0
#define CP_RB1_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK 0xffff
#define CP_RB1_RPTR_ADDR_HI__RB_RPTR_ADDR_HI__SHIFT 0x0
#define CP_RB2_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK 0xffff
#define CP_RB2_RPTR_ADDR_HI__RB_RPTR_ADDR_HI__SHIFT 0x0
#define CP_RB0_WPTR__RB_WPTR_MASK 0xfffff
#define CP_RB0_WPTR__RB_WPTR__SHIFT 0x0
#define CP_RB_WPTR__RB_WPTR_MASK 0xfffff
#define CP_RB_WPTR__RB_WPTR__SHIFT 0x0
#define CP_RB1_WPTR__RB_WPTR_MASK 0xfffff
#define CP_RB1_WPTR__RB_WPTR__SHIFT 0x0
#define CP_RB2_WPTR__RB_WPTR_MASK 0xfffff
#define CP_RB2_WPTR__RB_WPTR__SHIFT 0x0
#define CP_RB_WPTR_POLL_ADDR_LO__RB_WPTR_POLL_ADDR_LO_MASK 0xfffffffc
#define CP_RB_WPTR_POLL_ADDR_LO__RB_WPTR_POLL_ADDR_LO__SHIFT 0x2
#define CP_RB_WPTR_POLL_ADDR_HI__RB_WPTR_POLL_ADDR_HI_MASK 0xff
#define CP_RB_WPTR_POLL_ADDR_HI__RB_WPTR_POLL_ADDR_HI__SHIFT 0x0
#define CP_INT_CNTL__CP_VM_DOORBELL_WR_INT_ENABLE_MASK 0x800
#define CP_INT_CNTL__CP_VM_DOORBELL_WR_INT_ENABLE__SHIFT 0xb
#define CP_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000
#define CP_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
#define CP_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000
#define CP_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
#define CP_INT_CNTL__CMP_BUSY_INT_ENABLE_MASK 0x40000
#define CP_INT_CNTL__CMP_BUSY_INT_ENABLE__SHIFT 0x12
#define CP_INT_CNTL__CNTX_BUSY_INT_ENABLE_MASK 0x80000
#define CP_INT_CNTL__CNTX_BUSY_INT_ENABLE__SHIFT 0x13
#define CP_INT_CNTL__CNTX_EMPTY_INT_ENABLE_MASK 0x100000
#define CP_INT_CNTL__CNTX_EMPTY_INT_ENABLE__SHIFT 0x14
#define CP_INT_CNTL__GFX_IDLE_INT_ENABLE_MASK 0x200000
#define CP_INT_CNTL__GFX_IDLE_INT_ENABLE__SHIFT 0x15
#define CP_INT_CNTL__PRIV_INSTR_INT_ENABLE_MASK 0x400000
#define CP_INT_CNTL__PRIV_INSTR_INT_ENABLE__SHIFT 0x16
#define CP_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x800000
#define CP_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17
#define CP_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000
#define CP_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
#define CP_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x4000000
#define CP_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
#define CP_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000
#define CP_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
#define CP_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000
#define CP_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d
#define CP_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000
#define CP_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e
#define CP_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000
#define CP_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f
#define CP_INT_CNTL_RING0__CP_VM_DOORBELL_WR_INT_ENABLE_MASK 0x800
#define CP_INT_CNTL_RING0__CP_VM_DOORBELL_WR_INT_ENABLE__SHIFT 0xb
#define CP_INT_CNTL_RING0__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000
#define CP_INT_CNTL_RING0__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
#define CP_INT_CNTL_RING0__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000
#define CP_INT_CNTL_RING0__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
#define CP_INT_CNTL_RING0__CMP_BUSY_INT_ENABLE_MASK 0x40000
#define CP_INT_CNTL_RING0__CMP_BUSY_INT_ENABLE__SHIFT 0x12
#define CP_INT_CNTL_RING0__CNTX_BUSY_INT_ENABLE_MASK 0x80000
#define CP_INT_CNTL_RING0__CNTX_BUSY_INT_ENABLE__SHIFT 0x13
#define CP_INT_CNTL_RING0__CNTX_EMPTY_INT_ENABLE_MASK 0x100000
#define CP_INT_CNTL_RING0__CNTX_EMPTY_INT_ENABLE__SHIFT 0x14
#define CP_INT_CNTL_RING0__GFX_IDLE_INT_ENABLE_MASK 0x200000
#define CP_INT_CNTL_RING0__GFX_IDLE_INT_ENABLE__SHIFT 0x15
#define CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK 0x400000
#define CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE__SHIFT 0x16
#define CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK 0x800000
#define CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE__SHIFT 0x17
#define CP_INT_CNTL_RING0__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000
#define CP_INT_CNTL_RING0__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
#define CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK 0x4000000
#define CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
#define CP_INT_CNTL_RING0__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000
#define CP_INT_CNTL_RING0__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
#define CP_INT_CNTL_RING0__GENERIC2_INT_ENABLE_MASK 0x20000000
#define CP_INT_CNTL_RING0__GENERIC2_INT_ENABLE__SHIFT 0x1d
#define CP_INT_CNTL_RING0__GENERIC1_INT_ENABLE_MASK 0x40000000
#define CP_INT_CNTL_RING0__GENERIC1_INT_ENABLE__SHIFT 0x1e
#define CP_INT_CNTL_RING0__GENERIC0_INT_ENABLE_MASK 0x80000000
#define CP_INT_CNTL_RING0__GENERIC0_INT_ENABLE__SHIFT 0x1f
#define CP_INT_CNTL_RING1__CP_VM_DOORBELL_WR_INT_ENABLE_MASK 0x800
#define CP_INT_CNTL_RING1__CP_VM_DOORBELL_WR_INT_ENABLE__SHIFT 0xb
#define CP_INT_CNTL_RING1__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000
#define CP_INT_CNTL_RING1__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
#define CP_INT_CNTL_RING1__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000
#define CP_INT_CNTL_RING1__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
#define CP_INT_CNTL_RING1__CMP_BUSY_INT_ENABLE_MASK 0x40000
#define CP_INT_CNTL_RING1__CMP_BUSY_INT_ENABLE__SHIFT 0x12
#define CP_INT_CNTL_RING1__CNTX_BUSY_INT_ENABLE_MASK 0x80000
#define CP_INT_CNTL_RING1__CNTX_BUSY_INT_ENABLE__SHIFT 0x13
#define CP_INT_CNTL_RING1__CNTX_EMPTY_INT_ENABLE_MASK 0x100000
#define CP_INT_CNTL_RING1__CNTX_EMPTY_INT_ENABLE__SHIFT 0x14
#define CP_INT_CNTL_RING1__GFX_IDLE_INT_ENABLE_MASK 0x200000
#define CP_INT_CNTL_RING1__GFX_IDLE_INT_ENABLE__SHIFT 0x15
#define CP_INT_CNTL_RING1__PRIV_INSTR_INT_ENABLE_MASK 0x400000
#define CP_INT_CNTL_RING1__PRIV_INSTR_INT_ENABLE__SHIFT 0x16
#define CP_INT_CNTL_RING1__PRIV_REG_INT_ENABLE_MASK 0x800000
#define CP_INT_CNTL_RING1__PRIV_REG_INT_ENABLE__SHIFT 0x17
#define CP_INT_CNTL_RING1__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000
#define CP_INT_CNTL_RING1__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
#define CP_INT_CNTL_RING1__TIME_STAMP_INT_ENABLE_MASK 0x4000000
#define CP_INT_CNTL_RING1__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
#define CP_INT_CNTL_RING1__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000
#define CP_INT_CNTL_RING1__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
#define CP_INT_CNTL_RING1__GENERIC2_INT_ENABLE_MASK 0x20000000
#define CP_INT_CNTL_RING1__GENERIC2_INT_ENABLE__SHIFT 0x1d
#define CP_INT_CNTL_RING1__GENERIC1_INT_ENABLE_MASK 0x40000000
#define CP_INT_CNTL_RING1__GENERIC1_INT_ENABLE__SHIFT 0x1e
#define CP_INT_CNTL_RING1__GENERIC0_INT_ENABLE_MASK 0x80000000
#define CP_INT_CNTL_RING1__GENERIC0_INT_ENABLE__SHIFT 0x1f
#define CP_INT_CNTL_RING2__CP_VM_DOORBELL_WR_INT_ENABLE_MASK 0x800
#define CP_INT_CNTL_RING2__CP_VM_DOORBELL_WR_INT_ENABLE__SHIFT 0xb
#define CP_INT_CNTL_RING2__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000
#define CP_INT_CNTL_RING2__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
#define CP_INT_CNTL_RING2__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000
#define CP_INT_CNTL_RING2__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
#define CP_INT_CNTL_RING2__CMP_BUSY_INT_ENABLE_MASK 0x40000
#define CP_INT_CNTL_RING2__CMP_BUSY_INT_ENABLE__SHIFT 0x12
#define CP_INT_CNTL_RING2__CNTX_BUSY_INT_ENABLE_MASK 0x80000
#define CP_INT_CNTL_RING2__CNTX_BUSY_INT_ENABLE__SHIFT 0x13
#define CP_INT_CNTL_RING2__CNTX_EMPTY_INT_ENABLE_MASK 0x100000
#define CP_INT_CNTL_RING2__CNTX_EMPTY_INT_ENABLE__SHIFT 0x14
#define CP_INT_CNTL_RING2__GFX_IDLE_INT_ENABLE_MASK 0x200000
#define CP_INT_CNTL_RING2__GFX_IDLE_INT_ENABLE__SHIFT 0x15
#define CP_INT_CNTL_RING2__PRIV_INSTR_INT_ENABLE_MASK 0x400000
#define CP_INT_CNTL_RING2__PRIV_INSTR_INT_ENABLE__SHIFT 0x16
#define CP_INT_CNTL_RING2__PRIV_REG_INT_ENABLE_MASK 0x800000
#define CP_INT_CNTL_RING2__PRIV_REG_INT_ENABLE__SHIFT 0x17
#define CP_INT_CNTL_RING2__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000
#define CP_INT_CNTL_RING2__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
#define CP_INT_CNTL_RING2__TIME_STAMP_INT_ENABLE_MASK 0x4000000
#define CP_INT_CNTL_RING2__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
#define CP_INT_CNTL_RING2__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000
#define CP_INT_CNTL_RING2__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
#define CP_INT_CNTL_RING2__GENERIC2_INT_ENABLE_MASK 0x20000000
#define CP_INT_CNTL_RING2__GENERIC2_INT_ENABLE__SHIFT 0x1d
#define CP_INT_CNTL_RING2__GENERIC1_INT_ENABLE_MASK 0x40000000
#define CP_INT_CNTL_RING2__GENERIC1_INT_ENABLE__SHIFT 0x1e
#define CP_INT_CNTL_RING2__GENERIC0_INT_ENABLE_MASK 0x80000000
#define CP_INT_CNTL_RING2__GENERIC0_INT_ENABLE__SHIFT 0x1f
#define CP_INT_STATUS__CP_VM_DOORBELL_WR_INT_STAT_MASK 0x800
#define CP_INT_STATUS__CP_VM_DOORBELL_WR_INT_STAT__SHIFT 0xb
#define CP_INT_STATUS__CP_ECC_ERROR_INT_STAT_MASK 0x4000
#define CP_INT_STATUS__CP_ECC_ERROR_INT_STAT__SHIFT 0xe
#define CP_INT_STATUS__WRM_POLL_TIMEOUT_INT_STAT_MASK 0x20000
#define CP_INT_STATUS__WRM_POLL_TIMEOUT_INT_STAT__SHIFT 0x11
#define CP_INT_STATUS__CMP_BUSY_INT_STAT_MASK 0x40000
#define CP_INT_STATUS__CMP_BUSY_INT_STAT__SHIFT 0x12
#define CP_INT_STATUS__CNTX_BUSY_INT_STAT_MASK 0x80000
#define CP_INT_STATUS__CNTX_BUSY_INT_STAT__SHIFT 0x13
#define CP_INT_STATUS__CNTX_EMPTY_INT_STAT_MASK 0x100000
#define CP_INT_STATUS__CNTX_EMPTY_INT_STAT__SHIFT 0x14
#define CP_INT_STATUS__GFX_IDLE_INT_STAT_MASK 0x200000
#define CP_INT_STATUS__GFX_IDLE_INT_STAT__SHIFT 0x15
#define CP_INT_STATUS__PRIV_INSTR_INT_STAT_MASK 0x400000
#define CP_INT_STATUS__PRIV_INSTR_INT_STAT__SHIFT 0x16
#define CP_INT_STATUS__PRIV_REG_INT_STAT_MASK 0x800000
#define CP_INT_STATUS__PRIV_REG_INT_STAT__SHIFT 0x17
#define CP_INT_STATUS__OPCODE_ERROR_INT_STAT_MASK 0x1000000
#define CP_INT_STATUS__OPCODE_ERROR_INT_STAT__SHIFT 0x18
#define CP_INT_STATUS__TIME_STAMP_INT_STAT_MASK 0x4000000
#define CP_INT_STATUS__TIME_STAMP_INT_STAT__SHIFT 0x1a
#define CP_INT_STATUS__RESERVED_BIT_ERROR_INT_STAT_MASK 0x8000000
#define CP_INT_STATUS__RESERVED_BIT_ERROR_INT_STAT__SHIFT 0x1b
#define CP_INT_STATUS__GENERIC2_INT_STAT_MASK 0x20000000
#define CP_INT_STATUS__GENERIC2_INT_STAT__SHIFT 0x1d
#define CP_INT_STATUS__GENERIC1_INT_STAT_MASK 0x40000000
#define CP_INT_STATUS__GENERIC1_INT_STAT__SHIFT 0x1e
#define CP_INT_STATUS__GENERIC0_INT_STAT_MASK 0x80000000
#define CP_INT_STATUS__GENERIC0_INT_STAT__SHIFT 0x1f
#define CP_INT_STATUS_RING0__CP_VM_DOORBELL_WR_INT_STAT_MASK 0x800
#define CP_INT_STATUS_RING0__CP_VM_DOORBELL_WR_INT_STAT__SHIFT 0xb
#define CP_INT_STATUS_RING0__CP_ECC_ERROR_INT_STAT_MASK 0x4000
#define CP_INT_STATUS_RING0__CP_ECC_ERROR_INT_STAT__SHIFT 0xe
#define CP_INT_STATUS_RING0__WRM_POLL_TIMEOUT_INT_STAT_MASK 0x20000
#define CP_INT_STATUS_RING0__WRM_POLL_TIMEOUT_INT_STAT__SHIFT 0x11
#define CP_INT_STATUS_RING0__CMP_BUSY_INT_STAT_MASK 0x40000
#define CP_INT_STATUS_RING0__CMP_BUSY_INT_STAT__SHIFT 0x12
#define CP_INT_STATUS_RING0__GCNTX_BUSY_INT_STAT_MASK 0x80000
#define CP_INT_STATUS_RING0__GCNTX_BUSY_INT_STAT__SHIFT 0x13
#define CP_INT_STATUS_RING0__CNTX_EMPTY_INT_STAT_MASK 0x100000
#define CP_INT_STATUS_RING0__CNTX_EMPTY_INT_STAT__SHIFT 0x14
#define CP_INT_STATUS_RING0__GFX_IDLE_INT_STAT_MASK 0x200000
#define CP_INT_STATUS_RING0__GFX_IDLE_INT_STAT__SHIFT 0x15
#define CP_INT_STATUS_RING0__PRIV_INSTR_INT_STAT_MASK 0x400000
#define CP_INT_STATUS_RING0__PRIV_INSTR_INT_STAT__SHIFT 0x16
#define CP_INT_STATUS_RING0__PRIV_REG_INT_STAT_MASK 0x800000
#define CP_INT_STATUS_RING0__PRIV_REG_INT_STAT__SHIFT 0x17
#define CP_INT_STATUS_RING0__OPCODE_ERROR_INT_STAT_MASK 0x1000000
#define CP_INT_STATUS_RING0__OPCODE_ERROR_INT_STAT__SHIFT 0x18
#define CP_INT_STATUS_RING0__TIME_STAMP_INT_STAT_MASK 0x4000000
#define CP_INT_STATUS_RING0__TIME_STAMP_INT_STAT__SHIFT 0x1a
#define CP_INT_STATUS_RING0__RESERVED_BIT_ERROR_INT_STAT_MASK 0x8000000
#define CP_INT_STATUS_RING0__RESERVED_BIT_ERROR_INT_STAT__SHIFT 0x1b
#define CP_INT_STATUS_RING0__GENERIC2_INT_STAT_MASK 0x20000000
#define CP_INT_STATUS_RING0__GENERIC2_INT_STAT__SHIFT 0x1d
#define CP_INT_STATUS_RING0__GENERIC1_INT_STAT_MASK 0x40000000
#define CP_INT_STATUS_RING0__GENERIC1_INT_STAT__SHIFT 0x1e
#define CP_INT_STATUS_RING0__GENERIC0_INT_STAT_MASK 0x80000000
#define CP_INT_STATUS_RING0__GENERIC0_INT_STAT__SHIFT 0x1f
#define CP_INT_STATUS_RING1__CP_VM_DOORBELL_WR_INT_STAT_MASK 0x800
#define CP_INT_STATUS_RING1__CP_VM_DOORBELL_WR_INT_STAT__SHIFT 0xb
#define CP_INT_STATUS_RING1__CP_ECC_ERROR_INT_STAT_MASK 0x4000
#define CP_INT_STATUS_RING1__CP_ECC_ERROR_INT_STAT__SHIFT 0xe
#define CP_INT_STATUS_RING1__WRM_POLL_TIMEOUT_INT_STAT_MASK 0x20000
#define CP_INT_STATUS_RING1__WRM_POLL_TIMEOUT_INT_STAT__SHIFT 0x11
#define CP_INT_STATUS_RING1__CMP_BUSY_INT_STAT_MASK 0x40000
#define CP_INT_STATUS_RING1__CMP_BUSY_INT_STAT__SHIFT 0x12
#define CP_INT_STATUS_RING1__CNTX_BUSY_INT_STAT_MASK 0x80000
#define CP_INT_STATUS_RING1__CNTX_BUSY_INT_STAT__SHIFT 0x13
#define CP_INT_STATUS_RING1__CNTX_EMPTY_INT_STAT_MASK 0x100000
#define CP_INT_STATUS_RING1__CNTX_EMPTY_INT_STAT__SHIFT 0x14
#define CP_INT_STATUS_RING1__GFX_IDLE_INT_STAT_MASK 0x200000
#define CP_INT_STATUS_RING1__GFX_IDLE_INT_STAT__SHIFT 0x15
#define CP_INT_STATUS_RING1__PRIV_INSTR_INT_STAT_MASK 0x400000
#define CP_INT_STATUS_RING1__PRIV_INSTR_INT_STAT__SHIFT 0x16
#define CP_INT_STATUS_RING1__PRIV_REG_INT_STAT_MASK 0x800000
#define CP_INT_STATUS_RING1__PRIV_REG_INT_STAT__SHIFT 0x17
#define CP_INT_STATUS_RING1__OPCODE_ERROR_INT_STAT_MASK 0x1000000
#define CP_INT_STATUS_RING1__OPCODE_ERROR_INT_STAT__SHIFT 0x18
#define CP_INT_STATUS_RING1__TIME_STAMP_INT_STAT_MASK 0x4000000
#define CP_INT_STATUS_RING1__TIME_STAMP_INT_STAT__SHIFT 0x1a
#define CP_INT_STATUS_RING1__RESERVED_BIT_ERROR_INT_STAT_MASK 0x8000000
#define CP_INT_STATUS_RING1__RESERVED_BIT_ERROR_INT_STAT__SHIFT 0x1b
#define CP_INT_STATUS_RING1__GENERIC2_INT_STAT_MASK 0x20000000
#define CP_INT_STATUS_RING1__GENERIC2_INT_STAT__SHIFT 0x1d
#define CP_INT_STATUS_RING1__GENERIC1_INT_STAT_MASK 0x40000000
#define CP_INT_STATUS_RING1__GENERIC1_INT_STAT__SHIFT 0x1e
#define CP_INT_STATUS_RING1__GENERIC0_INT_STAT_MASK 0x80000000
#define CP_INT_STATUS_RING1__GENERIC0_INT_STAT__SHIFT 0x1f
#define CP_INT_STATUS_RING2__CP_VM_DOORBELL_WR_INT_STAT_MASK 0x800
#define CP_INT_STATUS_RING2__CP_VM_DOORBELL_WR_INT_STAT__SHIFT 0xb
#define CP_INT_STATUS_RING2__CP_ECC_ERROR_INT_STAT_MASK 0x4000
#define CP_INT_STATUS_RING2__CP_ECC_ERROR_INT_STAT__SHIFT 0xe
#define CP_INT_STATUS_RING2__WRM_POLL_TIMEOUT_INT_STAT_MASK 0x20000
#define CP_INT_STATUS_RING2__WRM_POLL_TIMEOUT_INT_STAT__SHIFT 0x11
#define CP_INT_STATUS_RING2__CMP_BUSY_INT_STAT_MASK 0x40000
#define CP_INT_STATUS_RING2__CMP_BUSY_INT_STAT__SHIFT 0x12
#define CP_INT_STATUS_RING2__CNTX_BUSY_INT_STAT_MASK 0x80000
#define CP_INT_STATUS_RING2__CNTX_BUSY_INT_STAT__SHIFT 0x13
#define CP_INT_STATUS_RING2__CNTX_EMPTY_INT_STAT_MASK 0x100000
#define CP_INT_STATUS_RING2__CNTX_EMPTY_INT_STAT__SHIFT 0x14
#define CP_INT_STATUS_RING2__GFX_IDLE_INT_STAT_MASK 0x200000
#define CP_INT_STATUS_RING2__GFX_IDLE_INT_STAT__SHIFT 0x15
#define CP_INT_STATUS_RING2__PRIV_INSTR_INT_STAT_MASK 0x400000
#define CP_INT_STATUS_RING2__PRIV_INSTR_INT_STAT__SHIFT 0x16
#define CP_INT_STATUS_RING2__PRIV_REG_INT_STAT_MASK 0x800000
#define CP_INT_STATUS_RING2__PRIV_REG_INT_STAT__SHIFT 0x17
#define CP_INT_STATUS_RING2__OPCODE_ERROR_INT_STAT_MASK 0x1000000
#define CP_INT_STATUS_RING2__OPCODE_ERROR_INT_STAT__SHIFT 0x18
#define CP_INT_STATUS_RING2__TIME_STAMP_INT_STAT_MASK 0x4000000
#define CP_INT_STATUS_RING2__TIME_STAMP_INT_STAT__SHIFT 0x1a
#define CP_INT_STATUS_RING2__RESERVED_BIT_ERROR_INT_STAT_MASK 0x8000000
#define CP_INT_STATUS_RING2__RESERVED_BIT_ERROR_INT_STAT__SHIFT 0x1b
#define CP_INT_STATUS_RING2__GENERIC2_INT_STAT_MASK 0x20000000
#define CP_INT_STATUS_RING2__GENERIC2_INT_STAT__SHIFT 0x1d
#define CP_INT_STATUS_RING2__GENERIC1_INT_STAT_MASK 0x40000000
#define CP_INT_STATUS_RING2__GENERIC1_INT_STAT__SHIFT 0x1e
#define CP_INT_STATUS_RING2__GENERIC0_INT_STAT_MASK 0x80000000
#define CP_INT_STATUS_RING2__GENERIC0_INT_STAT__SHIFT 0x1f
#define CP_DEVICE_ID__DEVICE_ID_MASK 0xff
#define CP_DEVICE_ID__DEVICE_ID__SHIFT 0x0
#define CP_RING_PRIORITY_CNTS__PRIORITY1_CNT_MASK 0xff
#define CP_RING_PRIORITY_CNTS__PRIORITY1_CNT__SHIFT 0x0
#define CP_RING_PRIORITY_CNTS__PRIORITY2A_CNT_MASK 0xff00
#define CP_RING_PRIORITY_CNTS__PRIORITY2A_CNT__SHIFT 0x8
#define CP_RING_PRIORITY_CNTS__PRIORITY2B_CNT_MASK 0xff0000
#define CP_RING_PRIORITY_CNTS__PRIORITY2B_CNT__SHIFT 0x10
#define CP_RING_PRIORITY_CNTS__PRIORITY3_CNT_MASK 0xff000000
#define CP_RING_PRIORITY_CNTS__PRIORITY3_CNT__SHIFT 0x18
#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY1_CNT_MASK 0xff
#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY1_CNT__SHIFT 0x0
#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT_MASK 0xff00
#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT__SHIFT 0x8
#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT_MASK 0xff0000
#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT__SHIFT 0x10
#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY3_CNT_MASK 0xff000000
#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY3_CNT__SHIFT 0x18
#define CP_RING0_PRIORITY__PRIORITY_MASK 0x3
#define CP_RING0_PRIORITY__PRIORITY__SHIFT 0x0
#define CP_ME0_PIPE0_PRIORITY__PRIORITY_MASK 0x3
#define CP_ME0_PIPE0_PRIORITY__PRIORITY__SHIFT 0x0
#define CP_RING1_PRIORITY__PRIORITY_MASK 0x3
#define CP_RING1_PRIORITY__PRIORITY__SHIFT 0x0
#define CP_ME0_PIPE1_PRIORITY__PRIORITY_MASK 0x3
#define CP_ME0_PIPE1_PRIORITY__PRIORITY__SHIFT 0x0
#define CP_RING2_PRIORITY__PRIORITY_MASK 0x3
#define CP_RING2_PRIORITY__PRIORITY__SHIFT 0x0
#define CP_ME0_PIPE2_PRIORITY__PRIORITY_MASK 0x3
#define CP_ME0_PIPE2_PRIORITY__PRIORITY__SHIFT 0x0
#define CP_ENDIAN_SWAP__ENDIAN_SWAP_MASK 0x3
#define CP_ENDIAN_SWAP__ENDIAN_SWAP__SHIFT 0x0
#define CP_RB_VMID__RB0_VMID_MASK 0xf
#define CP_RB_VMID__RB0_VMID__SHIFT 0x0
#define CP_RB_VMID__RB1_VMID_MASK 0xf00
#define CP_RB_VMID__RB1_VMID__SHIFT 0x8
#define CP_RB_VMID__RB2_VMID_MASK 0xf0000
#define CP_RB_VMID__RB2_VMID__SHIFT 0x10
#define CP_ME0_PIPE0_VMID__VMID_MASK 0xf
#define CP_ME0_PIPE0_VMID__VMID__SHIFT 0x0
#define CP_ME0_PIPE1_VMID__VMID_MASK 0xf
#define CP_ME0_PIPE1_VMID__VMID__SHIFT 0x0
#define CP_RB_DOORBELL_CONTROL__DOORBELL_OFFSET_MASK 0x7ffffc
#define CP_RB_DOORBELL_CONTROL__DOORBELL_OFFSET__SHIFT 0x2
#define CP_RB_DOORBELL_CONTROL__DOORBELL_EN_MASK 0x40000000
#define CP_RB_DOORBELL_CONTROL__DOORBELL_EN__SHIFT 0x1e
#define CP_RB_DOORBELL_CONTROL__DOORBELL_HIT_MASK 0x80000000
#define CP_RB_DOORBELL_CONTROL__DOORBELL_HIT__SHIFT 0x1f
#define CP_RB_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER_MASK 0x7ffffc
#define CP_RB_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER__SHIFT 0x2
#define CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK 0x7ffffc
#define CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER__SHIFT 0x2
#define CP_MEC_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER_MASK 0x7ffffc
#define CP_MEC_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER__SHIFT 0x2
#define CP_MEC_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK 0x7ffffc
#define CP_MEC_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER__SHIFT 0x2
#define CP_PFP_UCODE_ADDR__UCODE_ADDR_MASK 0x1fff
#define CP_PFP_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0
#define CP_PFP_UCODE_DATA__UCODE_DATA_MASK 0xffffffff
#define CP_PFP_UCODE_DATA__UCODE_DATA__SHIFT 0x0
#define CP_ME_RAM_RADDR__ME_RAM_RADDR_MASK 0x1fff
#define CP_ME_RAM_RADDR__ME_RAM_RADDR__SHIFT 0x0
#define CP_ME_RAM_WADDR__ME_RAM_WADDR_MASK 0x1fff
#define CP_ME_RAM_WADDR__ME_RAM_WADDR__SHIFT 0x0
#define CP_ME_RAM_DATA__ME_RAM_DATA_MASK 0xffffffff
#define CP_ME_RAM_DATA__ME_RAM_DATA__SHIFT 0x0
#define CGTT_CPC_CLK_CTRL__ON_DELAY_MASK 0xf
#define CGTT_CPC_CLK_CTRL__ON_DELAY__SHIFT 0x0
#define CGTT_CPC_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0
#define CGTT_CPC_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
#define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_PERFMON_MASK 0x20000000
#define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_PERFMON__SHIFT 0x1d
#define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_DYN_MASK 0x40000000
#define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_DYN__SHIFT 0x1e
#define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_REG_MASK 0x80000000
#define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_REG__SHIFT 0x1f
#define CGTT_CPF_CLK_CTRL__ON_DELAY_MASK 0xf
#define CGTT_CPF_CLK_CTRL__ON_DELAY__SHIFT 0x0
#define CGTT_CPF_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0
#define CGTT_CPF_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
#define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_PERFMON_MASK 0x20000000
#define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_PERFMON__SHIFT 0x1d
#define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_DYN_MASK 0x40000000
#define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_DYN__SHIFT 0x1e
#define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_REG_MASK 0x80000000
#define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_REG__SHIFT 0x1f
#define CGTT_CP_CLK_CTRL__ON_DELAY_MASK 0xf
#define CGTT_CP_CLK_CTRL__ON_DELAY__SHIFT 0x0
#define CGTT_CP_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0
#define CGTT_CP_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
#define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_PERFMON_MASK 0x20000000
#define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_PERFMON__SHIFT 0x1d
#define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_DYN_MASK 0x40000000
#define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_DYN__SHIFT 0x1e
#define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_REG_MASK 0x80000000
#define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_REG__SHIFT 0x1f
#define CP_CE_UCODE_ADDR__UCODE_ADDR_MASK 0xfff
#define CP_CE_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0
#define CP_CE_UCODE_DATA__UCODE_DATA_MASK 0xffffffff
#define CP_CE_UCODE_DATA__UCODE_DATA__SHIFT 0x0
#define CP_MEC_ME1_UCODE_ADDR__UCODE_ADDR_MASK 0x1ffff
#define CP_MEC_ME1_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0
#define CP_MEC_ME1_UCODE_DATA__UCODE_DATA_MASK 0xffffffff
#define CP_MEC_ME1_UCODE_DATA__UCODE_DATA__SHIFT 0x0
#define CP_MEC_ME2_UCODE_ADDR__UCODE_ADDR_MASK 0x1ffff
#define CP_MEC_ME2_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0
#define CP_MEC_ME2_UCODE_DATA__UCODE_DATA_MASK 0xffffffff
#define CP_MEC_ME2_UCODE_DATA__UCODE_DATA__SHIFT 0x0
#define CP_PFP_F32_INTERRUPT__PRIV_REG_INT_MASK 0x2
#define CP_PFP_F32_INTERRUPT__PRIV_REG_INT__SHIFT 0x1
#define CP_MEC1_F32_INTERRUPT__PRIV_REG_INT_MASK 0x2
#define CP_MEC1_F32_INTERRUPT__PRIV_REG_INT__SHIFT 0x1
#define CP_MEC2_F32_INTERRUPT__PRIV_REG_INT_MASK 0x2
#define CP_MEC2_F32_INTERRUPT__PRIV_REG_INT__SHIFT 0x1
#define CP_MEC1_F32_INT_DIS__EDC_ROQ_FED_INT_MASK 0x1
#define CP_MEC1_F32_INT_DIS__EDC_ROQ_FED_INT__SHIFT 0x0
#define CP_MEC1_F32_INT_DIS__PRIV_REG_INT_MASK 0x2
#define CP_MEC1_F32_INT_DIS__PRIV_REG_INT__SHIFT 0x1
#define CP_MEC1_F32_INT_DIS__RESERVED_BIT_ERR_INT_MASK 0x4
#define CP_MEC1_F32_INT_DIS__RESERVED_BIT_ERR_INT__SHIFT 0x2
#define CP_MEC1_F32_INT_DIS__EDC_TC_FED_INT_MASK 0x8
#define CP_MEC1_F32_INT_DIS__EDC_TC_FED_INT__SHIFT 0x3
#define CP_MEC1_F32_INT_DIS__EDC_GDS_FED_INT_MASK 0x10
#define CP_MEC1_F32_INT_DIS__EDC_GDS_FED_INT__SHIFT 0x4
#define CP_MEC1_F32_INT_DIS__EDC_SCRATCH_FED_INT_MASK 0x20
#define CP_MEC1_F32_INT_DIS__EDC_SCRATCH_FED_INT__SHIFT 0x5
#define CP_MEC1_F32_INT_DIS__WAVE_RESTORE_INT_MASK 0x40
#define CP_MEC1_F32_INT_DIS__WAVE_RESTORE_INT__SHIFT 0x6
#define CP_MEC1_F32_INT_DIS__SUA_VIOLATION_INT_MASK 0x80
#define CP_MEC1_F32_INT_DIS__SUA_VIOLATION_INT__SHIFT 0x7
#define CP_MEC1_F32_INT_DIS__EDC_DMA_FED_INT_MASK 0x100
#define CP_MEC1_F32_INT_DIS__EDC_DMA_FED_INT__SHIFT 0x8
#define CP_MEC1_F32_INT_DIS__IQ_TIMER_INT_MASK 0x200
#define CP_MEC1_F32_INT_DIS__IQ_TIMER_INT__SHIFT 0x9
#define CP_MEC2_F32_INT_DIS__EDC_ROQ_FED_INT_MASK 0x1
#define CP_MEC2_F32_INT_DIS__EDC_ROQ_FED_INT__SHIFT 0x0
#define CP_MEC2_F32_INT_DIS__PRIV_REG_INT_MASK 0x2
#define CP_MEC2_F32_INT_DIS__PRIV_REG_INT__SHIFT 0x1
#define CP_MEC2_F32_INT_DIS__RESERVED_BIT_ERR_INT_MASK 0x4
#define CP_MEC2_F32_INT_DIS__RESERVED_BIT_ERR_INT__SHIFT 0x2
#define CP_MEC2_F32_INT_DIS__EDC_TC_FED_INT_MASK 0x8
#define CP_MEC2_F32_INT_DIS__EDC_TC_FED_INT__SHIFT 0x3
#define CP_MEC2_F32_INT_DIS__EDC_GDS_FED_INT_MASK 0x10
#define CP_MEC2_F32_INT_DIS__EDC_GDS_FED_INT__SHIFT 0x4
#define CP_MEC2_F32_INT_DIS__EDC_SCRATCH_FED_INT_MASK 0x20
#define CP_MEC2_F32_INT_DIS__EDC_SCRATCH_FED_INT__SHIFT 0x5
#define CP_MEC2_F32_INT_DIS__WAVE_RESTORE_INT_MASK 0x40
#define CP_MEC2_F32_INT_DIS__WAVE_RESTORE_INT__SHIFT 0x6
#define CP_MEC2_F32_INT_DIS__SUA_VIOLATION_INT_MASK 0x80
#define CP_MEC2_F32_INT_DIS__SUA_VIOLATION_INT__SHIFT 0x7
#define CP_MEC2_F32_INT_DIS__EDC_DMA_FED_INT_MASK 0x100
#define CP_MEC2_F32_INT_DIS__EDC_DMA_FED_INT__SHIFT 0x8
#define CP_MEC2_F32_INT_DIS__IQ_TIMER_INT_MASK 0x200
#define CP_MEC2_F32_INT_DIS__IQ_TIMER_INT__SHIFT 0x9
#define CP_VIRT_STATUS__VIRT_STATUS_MASK 0xffffffff
#define CP_VIRT_STATUS__VIRT_STATUS__SHIFT 0x0
#define CP_PWR_CNTL__GFX_CLK_HALT_ME0_PIPE0_MASK 0x1
#define CP_PWR_CNTL__GFX_CLK_HALT_ME0_PIPE0__SHIFT 0x0
#define CP_PWR_CNTL__GFX_CLK_HALT_ME0_PIPE1_MASK 0x2
#define CP_PWR_CNTL__GFX_CLK_HALT_ME0_PIPE1__SHIFT 0x1
#define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE0_MASK 0x100
#define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE0__SHIFT 0x8
#define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE1_MASK 0x200
#define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE1__SHIFT 0x9
#define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE2_MASK 0x400
#define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE2__SHIFT 0xa
#define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE3_MASK 0x800
#define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE3__SHIFT 0xb
#define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE0_MASK 0x10000
#define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE0__SHIFT 0x10
#define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE1_MASK 0x20000
#define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE1__SHIFT 0x11
#define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE2_MASK 0x40000
#define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE2__SHIFT 0x12
#define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE3_MASK 0x80000
#define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE3__SHIFT 0x13
#define CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK 0x1
#define CP_MEM_SLP_CNTL__CP_MEM_LS_EN__SHIFT 0x0
#define CP_MEM_SLP_CNTL__CP_MEM_DS_EN_MASK 0x2
#define CP_MEM_SLP_CNTL__CP_MEM_DS_EN__SHIFT 0x1
#define CP_MEM_SLP_CNTL__RESERVED_MASK 0x7c
#define CP_MEM_SLP_CNTL__RESERVED__SHIFT 0x2
#define CP_MEM_SLP_CNTL__CP_LS_DS_BUSY_OVERRIDE_MASK 0x80
#define CP_MEM_SLP_CNTL__CP_LS_DS_BUSY_OVERRIDE__SHIFT 0x7
#define CP_MEM_SLP_CNTL__CP_MEM_LS_ON_DELAY_MASK 0xff00
#define CP_MEM_SLP_CNTL__CP_MEM_LS_ON_DELAY__SHIFT 0x8
#define CP_MEM_SLP_CNTL__CP_MEM_LS_OFF_DELAY_MASK 0xff0000
#define CP_MEM_SLP_CNTL__CP_MEM_LS_OFF_DELAY__SHIFT 0x10
#define CP_MEM_SLP_CNTL__RESERVED1_MASK 0xff000000
#define CP_MEM_SLP_CNTL__RESERVED1__SHIFT 0x18
#define CP_ECC_FIRSTOCCURRENCE__INTERFACE_MASK 0x3
#define CP_ECC_FIRSTOCCURRENCE__INTERFACE__SHIFT 0x0
#define CP_ECC_FIRSTOCCURRENCE__CLIENT_MASK 0xf0
#define CP_ECC_FIRSTOCCURRENCE__CLIENT__SHIFT 0x4
#define CP_ECC_FIRSTOCCURRENCE__ME_MASK 0x300
#define CP_ECC_FIRSTOCCURRENCE__ME__SHIFT 0x8
#define CP_ECC_FIRSTOCCURRENCE__PIPE_MASK 0xc00
#define CP_ECC_FIRSTOCCURRENCE__PIPE__SHIFT 0xa
#define CP_ECC_FIRSTOCCURRENCE__QUEUE_MASK 0x7000
#define CP_ECC_FIRSTOCCURRENCE__QUEUE__SHIFT 0xc
#define CP_ECC_FIRSTOCCURRENCE__VMID_MASK 0xf0000
#define CP_ECC_FIRSTOCCURRENCE__VMID__SHIFT 0x10
#define CP_ECC_FIRSTOCCURRENCE_RING0__OBSOLETE_MASK 0xffffffff
#define CP_ECC_FIRSTOCCURRENCE_RING0__OBSOLETE__SHIFT 0x0
#define CP_ECC_FIRSTOCCURRENCE_RING1__OBSOLETE_MASK 0xffffffff
#define CP_ECC_FIRSTOCCURRENCE_RING1__OBSOLETE__SHIFT 0x0
#define CP_ECC_FIRSTOCCURRENCE_RING2__OBSOLETE_MASK 0xffffffff
#define CP_ECC_FIRSTOCCURRENCE_RING2__OBSOLETE__SHIFT 0x0
#define CP_PQ_WPTR_POLL_CNTL__PERIOD_MASK 0xff
#define CP_PQ_WPTR_POLL_CNTL__PERIOD__SHIFT 0x0
#define CP_PQ_WPTR_POLL_CNTL__POLL_ACTIVE_MASK 0x40000000
#define CP_PQ_WPTR_POLL_CNTL__POLL_ACTIVE__SHIFT 0x1e
#define CP_PQ_WPTR_POLL_CNTL__EN_MASK 0x80000000
#define CP_PQ_WPTR_POLL_CNTL__EN__SHIFT 0x1f
#define CP_PQ_WPTR_POLL_CNTL1__QUEUE_MASK_MASK 0xffffffff
#define CP_PQ_WPTR_POLL_CNTL1__QUEUE_MASK__SHIFT 0x0
#define CPC_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x1000
#define CPC_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc
#define CPC_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x2000
#define CPC_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd
#define CPC_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000
#define CPC_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
#define CPC_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x8000
#define CPC_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf
#define CPC_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000
#define CPC_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
#define CPC_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x800000
#define CPC_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17
#define CPC_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000
#define CPC_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
#define CPC_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x4000000
#define CPC_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
#define CPC_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000
#define CPC_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
#define CPC_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000
#define CPC_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d
#define CPC_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000
#define CPC_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e
#define CPC_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000
#define CPC_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f
#define CP_ME1_PIPE0_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x1000
#define CP_ME1_PIPE0_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc
#define CP_ME1_PIPE0_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x2000
#define CP_ME1_PIPE0_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd
#define CP_ME1_PIPE0_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000
#define CP_ME1_PIPE0_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
#define CP_ME1_PIPE0_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x8000
#define CP_ME1_PIPE0_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf
#define CP_ME1_PIPE0_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000
#define CP_ME1_PIPE0_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
#define CP_ME1_PIPE0_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x800000
#define CP_ME1_PIPE0_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17
#define CP_ME1_PIPE0_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000
#define CP_ME1_PIPE0_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
#define CP_ME1_PIPE0_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x4000000
#define CP_ME1_PIPE0_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
#define CP_ME1_PIPE0_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000
#define CP_ME1_PIPE0_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
#define CP_ME1_PIPE0_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000
#define CP_ME1_PIPE0_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d
#define CP_ME1_PIPE0_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000
#define CP_ME1_PIPE0_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e
#define CP_ME1_PIPE0_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000
#define CP_ME1_PIPE0_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f
#define CP_ME1_PIPE1_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x1000
#define CP_ME1_PIPE1_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc
#define CP_ME1_PIPE1_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x2000
#define CP_ME1_PIPE1_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd
#define CP_ME1_PIPE1_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000
#define CP_ME1_PIPE1_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
#define CP_ME1_PIPE1_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x8000
#define CP_ME1_PIPE1_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf
#define CP_ME1_PIPE1_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000
#define CP_ME1_PIPE1_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
#define CP_ME1_PIPE1_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x800000
#define CP_ME1_PIPE1_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17
#define CP_ME1_PIPE1_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000
#define CP_ME1_PIPE1_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
#define CP_ME1_PIPE1_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x4000000
#define CP_ME1_PIPE1_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
#define CP_ME1_PIPE1_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000
#define CP_ME1_PIPE1_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
#define CP_ME1_PIPE1_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000
#define CP_ME1_PIPE1_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d
#define CP_ME1_PIPE1_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000
#define CP_ME1_PIPE1_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e
#define CP_ME1_PIPE1_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000
#define CP_ME1_PIPE1_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f
#define CP_ME1_PIPE2_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x1000
#define CP_ME1_PIPE2_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc
#define CP_ME1_PIPE2_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x2000
#define CP_ME1_PIPE2_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd
#define CP_ME1_PIPE2_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000
#define CP_ME1_PIPE2_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
#define CP_ME1_PIPE2_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x8000
#define CP_ME1_PIPE2_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf
#define CP_ME1_PIPE2_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000
#define CP_ME1_PIPE2_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
#define CP_ME1_PIPE2_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x800000
#define CP_ME1_PIPE2_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17
#define CP_ME1_PIPE2_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000
#define CP_ME1_PIPE2_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
#define CP_ME1_PIPE2_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x4000000
#define CP_ME1_PIPE2_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
#define CP_ME1_PIPE2_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000
#define CP_ME1_PIPE2_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
#define CP_ME1_PIPE2_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000
#define CP_ME1_PIPE2_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d
#define CP_ME1_PIPE2_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000
#define CP_ME1_PIPE2_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e
#define CP_ME1_PIPE2_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000
#define CP_ME1_PIPE2_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f
#define CP_ME1_PIPE3_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x1000
#define CP_ME1_PIPE3_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc
#define CP_ME1_PIPE3_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x2000
#define CP_ME1_PIPE3_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd
#define CP_ME1_PIPE3_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000
#define CP_ME1_PIPE3_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
#define CP_ME1_PIPE3_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x8000
#define CP_ME1_PIPE3_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf
#define CP_ME1_PIPE3_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000
#define CP_ME1_PIPE3_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
#define CP_ME1_PIPE3_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x800000
#define CP_ME1_PIPE3_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17
#define CP_ME1_PIPE3_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000
#define CP_ME1_PIPE3_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
#define CP_ME1_PIPE3_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x4000000
#define CP_ME1_PIPE3_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
#define CP_ME1_PIPE3_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000
#define CP_ME1_PIPE3_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
#define CP_ME1_PIPE3_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000
#define CP_ME1_PIPE3_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d
#define CP_ME1_PIPE3_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000
#define CP_ME1_PIPE3_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e
#define CP_ME1_PIPE3_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000
#define CP_ME1_PIPE3_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f
#define CP_ME2_PIPE0_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x1000
#define CP_ME2_PIPE0_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc
#define CP_ME2_PIPE0_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x2000
#define CP_ME2_PIPE0_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd
#define CP_ME2_PIPE0_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000
#define CP_ME2_PIPE0_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
#define CP_ME2_PIPE0_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x8000
#define CP_ME2_PIPE0_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf
#define CP_ME2_PIPE0_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000
#define CP_ME2_PIPE0_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
#define CP_ME2_PIPE0_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x800000
#define CP_ME2_PIPE0_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17
#define CP_ME2_PIPE0_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000
#define CP_ME2_PIPE0_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
#define CP_ME2_PIPE0_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x4000000
#define CP_ME2_PIPE0_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
#define CP_ME2_PIPE0_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000
#define CP_ME2_PIPE0_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
#define CP_ME2_PIPE0_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000
#define CP_ME2_PIPE0_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d
#define CP_ME2_PIPE0_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000
#define CP_ME2_PIPE0_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e
#define CP_ME2_PIPE0_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000
#define CP_ME2_PIPE0_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f
#define CP_ME2_PIPE1_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x1000
#define CP_ME2_PIPE1_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc
#define CP_ME2_PIPE1_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x2000
#define CP_ME2_PIPE1_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd
#define CP_ME2_PIPE1_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000
#define CP_ME2_PIPE1_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
#define CP_ME2_PIPE1_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x8000
#define CP_ME2_PIPE1_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf
#define CP_ME2_PIPE1_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000
#define CP_ME2_PIPE1_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
#define CP_ME2_PIPE1_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x800000
#define CP_ME2_PIPE1_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17
#define CP_ME2_PIPE1_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000
#define CP_ME2_PIPE1_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
#define CP_ME2_PIPE1_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x4000000
#define CP_ME2_PIPE1_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
#define CP_ME2_PIPE1_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000
#define CP_ME2_PIPE1_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
#define CP_ME2_PIPE1_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000
#define CP_ME2_PIPE1_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d
#define CP_ME2_PIPE1_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000
#define CP_ME2_PIPE1_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e
#define CP_ME2_PIPE1_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000
#define CP_ME2_PIPE1_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f
#define CP_ME2_PIPE2_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x1000
#define CP_ME2_PIPE2_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc
#define CP_ME2_PIPE2_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x2000
#define CP_ME2_PIPE2_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd
#define CP_ME2_PIPE2_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000
#define CP_ME2_PIPE2_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
#define CP_ME2_PIPE2_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x8000
#define CP_ME2_PIPE2_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf
#define CP_ME2_PIPE2_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000
#define CP_ME2_PIPE2_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
#define CP_ME2_PIPE2_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x800000
#define CP_ME2_PIPE2_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17
#define CP_ME2_PIPE2_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000
#define CP_ME2_PIPE2_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
#define CP_ME2_PIPE2_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x4000000
#define CP_ME2_PIPE2_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
#define CP_ME2_PIPE2_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000
#define CP_ME2_PIPE2_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
#define CP_ME2_PIPE2_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000
#define CP_ME2_PIPE2_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d
#define CP_ME2_PIPE2_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000
#define CP_ME2_PIPE2_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e
#define CP_ME2_PIPE2_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000
#define CP_ME2_PIPE2_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f
#define CP_ME2_PIPE3_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x1000
#define CP_ME2_PIPE3_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc
#define CP_ME2_PIPE3_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x2000
#define CP_ME2_PIPE3_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd
#define CP_ME2_PIPE3_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000
#define CP_ME2_PIPE3_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
#define CP_ME2_PIPE3_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x8000
#define CP_ME2_PIPE3_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf
#define CP_ME2_PIPE3_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000
#define CP_ME2_PIPE3_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
#define CP_ME2_PIPE3_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x800000
#define CP_ME2_PIPE3_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17
#define CP_ME2_PIPE3_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000
#define CP_ME2_PIPE3_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
#define CP_ME2_PIPE3_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x4000000
#define CP_ME2_PIPE3_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
#define CP_ME2_PIPE3_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000
#define CP_ME2_PIPE3_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
#define CP_ME2_PIPE3_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000
#define CP_ME2_PIPE3_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d
#define CP_ME2_PIPE3_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000
#define CP_ME2_PIPE3_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e
#define CP_ME2_PIPE3_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000
#define CP_ME2_PIPE3_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f
#define CPC_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x1000
#define CPC_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc
#define CPC_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x2000
#define CPC_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd
#define CPC_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x4000
#define CPC_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe
#define CPC_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x8000
#define CPC_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf
#define CPC_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x20000
#define CPC_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11
#define CPC_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x800000
#define CPC_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17
#define CPC_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x1000000
#define CPC_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18
#define CPC_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x4000000
#define CPC_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a
#define CPC_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x8000000
#define CPC_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b
#define CPC_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000
#define CPC_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d
#define CPC_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000
#define CPC_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e
#define CPC_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000
#define CPC_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f
#define CP_ME1_PIPE0_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x1000
#define CP_ME1_PIPE0_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc
#define CP_ME1_PIPE0_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x2000
#define CP_ME1_PIPE0_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd
#define CP_ME1_PIPE0_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x4000
#define CP_ME1_PIPE0_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe
#define CP_ME1_PIPE0_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x8000
#define CP_ME1_PIPE0_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf
#define CP_ME1_PIPE0_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x20000
#define CP_ME1_PIPE0_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11
#define CP_ME1_PIPE0_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x800000
#define CP_ME1_PIPE0_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17
#define CP_ME1_PIPE0_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x1000000
#define CP_ME1_PIPE0_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18
#define CP_ME1_PIPE0_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x4000000
#define CP_ME1_PIPE0_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a
#define CP_ME1_PIPE0_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x8000000
#define CP_ME1_PIPE0_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b
#define CP_ME1_PIPE0_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000
#define CP_ME1_PIPE0_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d
#define CP_ME1_PIPE0_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000
#define CP_ME1_PIPE0_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e
#define CP_ME1_PIPE0_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000
#define CP_ME1_PIPE0_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f
#define CP_ME1_PIPE1_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x1000
#define CP_ME1_PIPE1_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc
#define CP_ME1_PIPE1_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x2000
#define CP_ME1_PIPE1_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd
#define CP_ME1_PIPE1_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x4000
#define CP_ME1_PIPE1_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe
#define CP_ME1_PIPE1_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x8000
#define CP_ME1_PIPE1_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf
#define CP_ME1_PIPE1_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x20000
#define CP_ME1_PIPE1_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11
#define CP_ME1_PIPE1_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x800000
#define CP_ME1_PIPE1_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17
#define CP_ME1_PIPE1_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x1000000
#define CP_ME1_PIPE1_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18
#define CP_ME1_PIPE1_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x4000000
#define CP_ME1_PIPE1_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a
#define CP_ME1_PIPE1_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x8000000
#define CP_ME1_PIPE1_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b
#define CP_ME1_PIPE1_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000
#define CP_ME1_PIPE1_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d
#define CP_ME1_PIPE1_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000
#define CP_ME1_PIPE1_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e
#define CP_ME1_PIPE1_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000
#define CP_ME1_PIPE1_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f
#define CP_ME1_PIPE2_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x1000
#define CP_ME1_PIPE2_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc
#define CP_ME1_PIPE2_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x2000
#define CP_ME1_PIPE2_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd
#define CP_ME1_PIPE2_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x4000
#define CP_ME1_PIPE2_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe
#define CP_ME1_PIPE2_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x8000
#define CP_ME1_PIPE2_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf
#define CP_ME1_PIPE2_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x20000
#define CP_ME1_PIPE2_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11
#define CP_ME1_PIPE2_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x800000
#define CP_ME1_PIPE2_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17
#define CP_ME1_PIPE2_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x1000000
#define CP_ME1_PIPE2_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18
#define CP_ME1_PIPE2_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x4000000
#define CP_ME1_PIPE2_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a
#define CP_ME1_PIPE2_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x8000000
#define CP_ME1_PIPE2_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b
#define CP_ME1_PIPE2_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000
#define CP_ME1_PIPE2_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d
#define CP_ME1_PIPE2_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000
#define CP_ME1_PIPE2_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e
#define CP_ME1_PIPE2_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000
#define CP_ME1_PIPE2_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f
#define CP_ME1_PIPE3_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x1000
#define CP_ME1_PIPE3_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc
#define CP_ME1_PIPE3_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x2000
#define CP_ME1_PIPE3_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd
#define CP_ME1_PIPE3_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x4000
#define CP_ME1_PIPE3_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe
#define CP_ME1_PIPE3_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x8000
#define CP_ME1_PIPE3_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf
#define CP_ME1_PIPE3_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x20000
#define CP_ME1_PIPE3_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11
#define CP_ME1_PIPE3_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x800000
#define CP_ME1_PIPE3_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17
#define CP_ME1_PIPE3_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x1000000
#define CP_ME1_PIPE3_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18
#define CP_ME1_PIPE3_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x4000000
#define CP_ME1_PIPE3_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a
#define CP_ME1_PIPE3_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x8000000
#define CP_ME1_PIPE3_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b
#define CP_ME1_PIPE3_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000
#define CP_ME1_PIPE3_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d
#define CP_ME1_PIPE3_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000
#define CP_ME1_PIPE3_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e
#define CP_ME1_PIPE3_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000
#define CP_ME1_PIPE3_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f
#define CP_ME2_PIPE0_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x1000
#define CP_ME2_PIPE0_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc
#define CP_ME2_PIPE0_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x2000
#define CP_ME2_PIPE0_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd
#define CP_ME2_PIPE0_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x4000
#define CP_ME2_PIPE0_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe
#define CP_ME2_PIPE0_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x8000
#define CP_ME2_PIPE0_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf
#define CP_ME2_PIPE0_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x20000
#define CP_ME2_PIPE0_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11
#define CP_ME2_PIPE0_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x800000
#define CP_ME2_PIPE0_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17
#define CP_ME2_PIPE0_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x1000000
#define CP_ME2_PIPE0_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18
#define CP_ME2_PIPE0_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x4000000
#define CP_ME2_PIPE0_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a
#define CP_ME2_PIPE0_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x8000000
#define CP_ME2_PIPE0_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b
#define CP_ME2_PIPE0_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000
#define CP_ME2_PIPE0_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d
#define CP_ME2_PIPE0_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000
#define CP_ME2_PIPE0_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e
#define CP_ME2_PIPE0_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000
#define CP_ME2_PIPE0_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f
#define CP_ME2_PIPE1_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x1000
#define CP_ME2_PIPE1_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc
#define CP_ME2_PIPE1_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x2000
#define CP_ME2_PIPE1_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd
#define CP_ME2_PIPE1_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x4000
#define CP_ME2_PIPE1_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe
#define CP_ME2_PIPE1_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x8000
#define CP_ME2_PIPE1_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf
#define CP_ME2_PIPE1_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x20000
#define CP_ME2_PIPE1_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11
#define CP_ME2_PIPE1_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x800000
#define CP_ME2_PIPE1_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17
#define CP_ME2_PIPE1_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x1000000
#define CP_ME2_PIPE1_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18
#define CP_ME2_PIPE1_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x4000000
#define CP_ME2_PIPE1_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a
#define CP_ME2_PIPE1_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x8000000
#define CP_ME2_PIPE1_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b
#define CP_ME2_PIPE1_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000
#define CP_ME2_PIPE1_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d
#define CP_ME2_PIPE1_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000
#define CP_ME2_PIPE1_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e
#define CP_ME2_PIPE1_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000
#define CP_ME2_PIPE1_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f
#define CP_ME2_PIPE2_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x1000
#define CP_ME2_PIPE2_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc
#define CP_ME2_PIPE2_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x2000
#define CP_ME2_PIPE2_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd
#define CP_ME2_PIPE2_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x4000
#define CP_ME2_PIPE2_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe
#define CP_ME2_PIPE2_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x8000
#define CP_ME2_PIPE2_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf
#define CP_ME2_PIPE2_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x20000
#define CP_ME2_PIPE2_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11
#define CP_ME2_PIPE2_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x800000
#define CP_ME2_PIPE2_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17
#define CP_ME2_PIPE2_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x1000000
#define CP_ME2_PIPE2_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18
#define CP_ME2_PIPE2_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x4000000
#define CP_ME2_PIPE2_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a
#define CP_ME2_PIPE2_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x8000000
#define CP_ME2_PIPE2_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b
#define CP_ME2_PIPE2_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000
#define CP_ME2_PIPE2_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d
#define CP_ME2_PIPE2_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000
#define CP_ME2_PIPE2_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e
#define CP_ME2_PIPE2_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000
#define CP_ME2_PIPE2_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f
#define CP_ME2_PIPE3_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x1000
#define CP_ME2_PIPE3_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc
#define CP_ME2_PIPE3_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x2000
#define CP_ME2_PIPE3_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd
#define CP_ME2_PIPE3_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x4000
#define CP_ME2_PIPE3_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe
#define CP_ME2_PIPE3_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x8000
#define CP_ME2_PIPE3_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf
#define CP_ME2_PIPE3_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x20000
#define CP_ME2_PIPE3_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11
#define CP_ME2_PIPE3_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x800000
#define CP_ME2_PIPE3_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17
#define CP_ME2_PIPE3_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x1000000
#define CP_ME2_PIPE3_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18
#define CP_ME2_PIPE3_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x4000000
#define CP_ME2_PIPE3_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a
#define CP_ME2_PIPE3_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x8000000
#define CP_ME2_PIPE3_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b
#define CP_ME2_PIPE3_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000
#define CP_ME2_PIPE3_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d
#define CP_ME2_PIPE3_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000
#define CP_ME2_PIPE3_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e
#define CP_ME2_PIPE3_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000
#define CP_ME2_PIPE3_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f
#define CP_ME1_INT_STAT_DEBUG__CMP_QUERY_STATUS_INT_ASSERTED_MASK 0x1000
#define CP_ME1_INT_STAT_DEBUG__CMP_QUERY_STATUS_INT_ASSERTED__SHIFT 0xc
#define CP_ME1_INT_STAT_DEBUG__DEQUEUE_REQUEST_INT_ASSERTED_MASK 0x2000
#define CP_ME1_INT_STAT_DEBUG__DEQUEUE_REQUEST_INT_ASSERTED__SHIFT 0xd
#define CP_ME1_INT_STAT_DEBUG__CP_ECC_ERROR_INT_ASSERTED_MASK 0x4000
#define CP_ME1_INT_STAT_DEBUG__CP_ECC_ERROR_INT_ASSERTED__SHIFT 0xe
#define CP_ME1_INT_STAT_DEBUG__SUA_VIOLATION_INT_STATUS_MASK 0x8000
#define CP_ME1_INT_STAT_DEBUG__SUA_VIOLATION_INT_STATUS__SHIFT 0xf
#define CP_ME1_INT_STAT_DEBUG__WRM_POLL_TIMEOUT_INT_ASSERTED_MASK 0x20000
#define CP_ME1_INT_STAT_DEBUG__WRM_POLL_TIMEOUT_INT_ASSERTED__SHIFT 0x11
#define CP_ME1_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED_MASK 0x800000
#define CP_ME1_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED__SHIFT 0x17
#define CP_ME1_INT_STAT_DEBUG__OPCODE_ERROR_INT_ASSERTED_MASK 0x1000000
#define CP_ME1_INT_STAT_DEBUG__OPCODE_ERROR_INT_ASSERTED__SHIFT 0x18
#define CP_ME1_INT_STAT_DEBUG__TIME_STAMP_INT_ASSERTED_MASK 0x4000000
#define CP_ME1_INT_STAT_DEBUG__TIME_STAMP_INT_ASSERTED__SHIFT 0x1a
#define CP_ME1_INT_STAT_DEBUG__RESERVED_BIT_ERROR_INT_ASSERTED_MASK 0x8000000
#define CP_ME1_INT_STAT_DEBUG__RESERVED_BIT_ERROR_INT_ASSERTED__SHIFT 0x1b
#define CP_ME1_INT_STAT_DEBUG__GENERIC2_INT_ASSERTED_MASK 0x20000000
#define CP_ME1_INT_STAT_DEBUG__GENERIC2_INT_ASSERTED__SHIFT 0x1d
#define CP_ME1_INT_STAT_DEBUG__GENERIC1_INT_ASSERTED_MASK 0x40000000
#define CP_ME1_INT_STAT_DEBUG__GENERIC1_INT_ASSERTED__SHIFT 0x1e
#define CP_ME1_INT_STAT_DEBUG__GENERIC0_INT_ASSERTED_MASK 0x80000000
#define CP_ME1_INT_STAT_DEBUG__GENERIC0_INT_ASSERTED__SHIFT 0x1f
#define CP_ME2_INT_STAT_DEBUG__CMP_QUERY_STATUS_INT_ASSERTED_MASK 0x1000
#define CP_ME2_INT_STAT_DEBUG__CMP_QUERY_STATUS_INT_ASSERTED__SHIFT 0xc
#define CP_ME2_INT_STAT_DEBUG__DEQUEUE_REQUEST_INT_ASSERTED_MASK 0x2000
#define CP_ME2_INT_STAT_DEBUG__DEQUEUE_REQUEST_INT_ASSERTED__SHIFT 0xd
#define CP_ME2_INT_STAT_DEBUG__CP_ECC_ERROR_INT_ASSERTED_MASK 0x4000
#define CP_ME2_INT_STAT_DEBUG__CP_ECC_ERROR_INT_ASSERTED__SHIFT 0xe
#define CP_ME2_INT_STAT_DEBUG__SUA_VIOLATION_INT_STATUS_MASK 0x8000
#define CP_ME2_INT_STAT_DEBUG__SUA_VIOLATION_INT_STATUS__SHIFT 0xf
#define CP_ME2_INT_STAT_DEBUG__WRM_POLL_TIMEOUT_INT_ASSERTED_MASK 0x20000
#define CP_ME2_INT_STAT_DEBUG__WRM_POLL_TIMEOUT_INT_ASSERTED__SHIFT 0x11
#define CP_ME2_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED_MASK 0x800000
#define CP_ME2_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED__SHIFT 0x17
#define CP_ME2_INT_STAT_DEBUG__OPCODE_ERROR_INT_ASSERTED_MASK 0x1000000
#define CP_ME2_INT_STAT_DEBUG__OPCODE_ERROR_INT_ASSERTED__SHIFT 0x18
#define CP_ME2_INT_STAT_DEBUG__TIME_STAMP_INT_ASSERTED_MASK 0x4000000
#define CP_ME2_INT_STAT_DEBUG__TIME_STAMP_INT_ASSERTED__SHIFT 0x1a
#define CP_ME2_INT_STAT_DEBUG__RESERVED_BIT_ERROR_INT_ASSERTED_MASK 0x8000000
#define CP_ME2_INT_STAT_DEBUG__RESERVED_BIT_ERROR_INT_ASSERTED__SHIFT 0x1b
#define CP_ME2_INT_STAT_DEBUG__GENERIC2_INT_ASSERTED_MASK 0x20000000
#define CP_ME2_INT_STAT_DEBUG__GENERIC2_INT_ASSERTED__SHIFT 0x1d
#define CP_ME2_INT_STAT_DEBUG__GENERIC1_INT_ASSERTED_MASK 0x40000000
#define CP_ME2_INT_STAT_DEBUG__GENERIC1_INT_ASSERTED__SHIFT 0x1e
#define CP_ME2_INT_STAT_DEBUG__GENERIC0_INT_ASSERTED_MASK 0x80000000
#define CP_ME2_INT_STAT_DEBUG__GENERIC0_INT_ASSERTED__SHIFT 0x1f
#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY1_CNT_MASK 0xff
#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY1_CNT__SHIFT 0x0
#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT_MASK 0xff00
#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT__SHIFT 0x8
#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT_MASK 0xff0000
#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT__SHIFT 0x10
#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY3_CNT_MASK 0xff000000
#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY3_CNT__SHIFT 0x18
#define CP_ME1_PIPE0_PRIORITY__PRIORITY_MASK 0x3
#define CP_ME1_PIPE0_PRIORITY__PRIORITY__SHIFT 0x0
#define CP_ME1_PIPE1_PRIORITY__PRIORITY_MASK 0x3
#define CP_ME1_PIPE1_PRIORITY__PRIORITY__SHIFT 0x0
#define CP_ME1_PIPE2_PRIORITY__PRIORITY_MASK 0x3
#define CP_ME1_PIPE2_PRIORITY__PRIORITY__SHIFT 0x0
#define CP_ME1_PIPE3_PRIORITY__PRIORITY_MASK 0x3
#define CP_ME1_PIPE3_PRIORITY__PRIORITY__SHIFT 0x0
#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY1_CNT_MASK 0xff
#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY1_CNT__SHIFT 0x0
#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT_MASK 0xff00
#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT__SHIFT 0x8
#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT_MASK 0xff0000
#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT__SHIFT 0x10
#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY3_CNT_MASK 0xff000000
#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY3_CNT__SHIFT 0x18
#define CP_ME2_PIPE0_PRIORITY__PRIORITY_MASK 0x3
#define CP_ME2_PIPE0_PRIORITY__PRIORITY__SHIFT 0x0
#define CP_ME2_PIPE1_PRIORITY__PRIORITY_MASK 0x3
#define CP_ME2_PIPE1_PRIORITY__PRIORITY__SHIFT 0x0
#define CP_ME2_PIPE2_PRIORITY__PRIORITY_MASK 0x3
#define CP_ME2_PIPE2_PRIORITY__PRIORITY__SHIFT 0x0
#define CP_ME2_PIPE3_PRIORITY__PRIORITY_MASK 0x3
#define CP_ME2_PIPE3_PRIORITY__PRIORITY__SHIFT 0x0
#define CP_CE_PRGRM_CNTR_START__IP_START_MASK 0x7ff
#define CP_CE_PRGRM_CNTR_START__IP_START__SHIFT 0x0
#define CP_PFP_PRGRM_CNTR_START__IP_START_MASK 0xfff
#define CP_PFP_PRGRM_CNTR_START__IP_START__SHIFT 0x0
#define CP_ME_PRGRM_CNTR_START__IP_START_MASK 0xfff
#define CP_ME_PRGRM_CNTR_START__IP_START__SHIFT 0x0
#define CP_MEC1_PRGRM_CNTR_START__IP_START_MASK 0xffff
#define CP_MEC1_PRGRM_CNTR_START__IP_START__SHIFT 0x0
#define CP_MEC2_PRGRM_CNTR_START__IP_START_MASK 0xffff
#define CP_MEC2_PRGRM_CNTR_START__IP_START__SHIFT 0x0
#define CP_CE_INTR_ROUTINE_START__IR_START_MASK 0x7ff
#define CP_CE_INTR_ROUTINE_START__IR_START__SHIFT 0x0
#define CP_PFP_INTR_ROUTINE_START__IR_START_MASK 0xfff
#define CP_PFP_INTR_ROUTINE_START__IR_START__SHIFT 0x0
#define CP_ME_INTR_ROUTINE_START__IR_START_MASK 0xfff
#define CP_ME_INTR_ROUTINE_START__IR_START__SHIFT 0x0
#define CP_MEC1_INTR_ROUTINE_START__IR_START_MASK 0xffff
#define CP_MEC1_INTR_ROUTINE_START__IR_START__SHIFT 0x0
#define CP_MEC2_INTR_ROUTINE_START__IR_START_MASK 0xffff
#define CP_MEC2_INTR_ROUTINE_START__IR_START__SHIFT 0x0
#define CP_CONTEXT_CNTL__ME0PIPE0_MAX_WD_CNTX_MASK 0x7
#define CP_CONTEXT_CNTL__ME0PIPE0_MAX_WD_CNTX__SHIFT 0x0
#define CP_CONTEXT_CNTL__ME0PIPE0_MAX_PIPE_CNTX_MASK 0x70
#define CP_CONTEXT_CNTL__ME0PIPE0_MAX_PIPE_CNTX__SHIFT 0x4
#define CP_CONTEXT_CNTL__ME0PIPE1_MAX_WD_CNTX_MASK 0x70000
#define CP_CONTEXT_CNTL__ME0PIPE1_MAX_WD_CNTX__SHIFT 0x10
#define CP_CONTEXT_CNTL__ME0PIPE1_MAX_PIPE_CNTX_MASK 0x700000
#define CP_CONTEXT_CNTL__ME0PIPE1_MAX_PIPE_CNTX__SHIFT 0x14
#define CP_MAX_CONTEXT__MAX_CONTEXT_MASK 0x7
#define CP_MAX_CONTEXT__MAX_CONTEXT__SHIFT 0x0
#define CP_IQ_WAIT_TIME1__IB_OFFLOAD_MASK 0xff
#define CP_IQ_WAIT_TIME1__IB_OFFLOAD__SHIFT 0x0
#define CP_IQ_WAIT_TIME1__ATOMIC_OFFLOAD_MASK 0xff00
#define CP_IQ_WAIT_TIME1__ATOMIC_OFFLOAD__SHIFT 0x8
#define CP_IQ_WAIT_TIME1__WRM_OFFLOAD_MASK 0xff0000
#define CP_IQ_WAIT_TIME1__WRM_OFFLOAD__SHIFT 0x10
#define CP_IQ_WAIT_TIME1__GWS_MASK 0xff000000
#define CP_IQ_WAIT_TIME1__GWS__SHIFT 0x18
#define CP_IQ_WAIT_TIME2__QUE_SLEEP_MASK 0xff
#define CP_IQ_WAIT_TIME2__QUE_SLEEP__SHIFT 0x0
#define CP_IQ_WAIT_TIME2__SCH_WAVE_MASK 0xff00
#define CP_IQ_WAIT_TIME2__SCH_WAVE__SHIFT 0x8
#define CP_IQ_WAIT_TIME2__SEM_REARM_MASK 0xff0000
#define CP_IQ_WAIT_TIME2__SEM_REARM__SHIFT 0x10
#define CP_IQ_WAIT_TIME2__DEQ_RETRY_MASK 0xff000000
#define CP_IQ_WAIT_TIME2__DEQ_RETRY__SHIFT 0x18
#define CP_VMID_RESET__RESET_REQUEST_MASK 0xffff
#define CP_VMID_RESET__RESET_REQUEST__SHIFT 0x0
#define CP_VMID_RESET__RESET_STATUS_MASK 0xffff0000
#define CP_VMID_RESET__RESET_STATUS__SHIFT 0x10
#define CP_VMID_PREEMPT__PREEMPT_REQUEST_MASK 0xffff
#define CP_VMID_PREEMPT__PREEMPT_REQUEST__SHIFT 0x0
#define CP_VMID_PREEMPT__VIRT_COMMAND_MASK 0xf0000
#define CP_VMID_PREEMPT__VIRT_COMMAND__SHIFT 0x10
#define CP_VMID_STATUS__PREEMPT_DE_STATUS_MASK 0xffff
#define CP_VMID_STATUS__PREEMPT_DE_STATUS__SHIFT 0x0
#define CP_VMID_STATUS__PREEMPT_CE_STATUS_MASK 0xffff0000
#define CP_VMID_STATUS__PREEMPT_CE_STATUS__SHIFT 0x10
#define CPC_INT_CNTX_ID__CNTX_ID_MASK 0xfffffff
#define CPC_INT_CNTX_ID__CNTX_ID__SHIFT 0x0
#define CPC_INT_CNTX_ID__QUEUE_ID_MASK 0x70000000
#define CPC_INT_CNTX_ID__QUEUE_ID__SHIFT 0x1c
#define CP_PQ_STATUS__DOORBELL_UPDATED_MASK 0x1
#define CP_PQ_STATUS__DOORBELL_UPDATED__SHIFT 0x0
#define CP_PQ_STATUS__DOORBELL_ENABLE_MASK 0x2
#define CP_PQ_STATUS__DOORBELL_ENABLE__SHIFT 0x1
#define CP_CPC_IC_BASE_LO__IC_BASE_LO_MASK 0xfffff000
#define CP_CPC_IC_BASE_LO__IC_BASE_LO__SHIFT 0xc
#define CP_CPC_IC_BASE_HI__IC_BASE_HI_MASK 0xffff
#define CP_CPC_IC_BASE_HI__IC_BASE_HI__SHIFT 0x0
#define CP_CPC_IC_BASE_CNTL__VMID_MASK 0xf
#define CP_CPC_IC_BASE_CNTL__VMID__SHIFT 0x0
#define CP_CPC_IC_BASE_CNTL__ATC_MASK 0x800000
#define CP_CPC_IC_BASE_CNTL__ATC__SHIFT 0x17
#define CP_CPC_IC_BASE_CNTL__CACHE_POLICY_MASK 0x1000000
#define CP_CPC_IC_BASE_CNTL__CACHE_POLICY__SHIFT 0x18
#define CP_CPC_IC_BASE_CNTL__MTYPE_MASK 0x18000000
#define CP_CPC_IC_BASE_CNTL__MTYPE__SHIFT 0x1b
#define CP_CPC_IC_OP_CNTL__INVALIDATE_CACHE_MASK 0x1
#define CP_CPC_IC_OP_CNTL__INVALIDATE_CACHE__SHIFT 0x0
#define CP_CPC_IC_OP_CNTL__PRIME_ICACHE_MASK 0x10
#define CP_CPC_IC_OP_CNTL__PRIME_ICACHE__SHIFT 0x4
#define CP_CPC_IC_OP_CNTL__ICACHE_PRIMED_MASK 0x20
#define CP_CPC_IC_OP_CNTL__ICACHE_PRIMED__SHIFT 0x5
#define CP_CPC_STATUS__MEC1_BUSY_MASK 0x1
#define CP_CPC_STATUS__MEC1_BUSY__SHIFT 0x0
#define CP_CPC_STATUS__MEC2_BUSY_MASK 0x2
#define CP_CPC_STATUS__MEC2_BUSY__SHIFT 0x1
#define CP_CPC_STATUS__DC0_BUSY_MASK 0x4
#define CP_CPC_STATUS__DC0_BUSY__SHIFT 0x2
#define CP_CPC_STATUS__DC1_BUSY_MASK 0x8
#define CP_CPC_STATUS__DC1_BUSY__SHIFT 0x3
#define CP_CPC_STATUS__RCIU1_BUSY_MASK 0x10
#define CP_CPC_STATUS__RCIU1_BUSY__SHIFT 0x4
#define CP_CPC_STATUS__RCIU2_BUSY_MASK 0x20
#define CP_CPC_STATUS__RCIU2_BUSY__SHIFT 0x5
#define CP_CPC_STATUS__ROQ1_BUSY_MASK 0x40
#define CP_CPC_STATUS__ROQ1_BUSY__SHIFT 0x6
#define CP_CPC_STATUS__ROQ2_BUSY_MASK 0x80
#define CP_CPC_STATUS__ROQ2_BUSY__SHIFT 0x7
#define CP_CPC_STATUS__TCIU_BUSY_MASK 0x400
#define CP_CPC_STATUS__TCIU_BUSY__SHIFT 0xa
#define CP_CPC_STATUS__SCRATCH_RAM_BUSY_MASK 0x800
#define CP_CPC_STATUS__SCRATCH_RAM_BUSY__SHIFT 0xb
#define CP_CPC_STATUS__QU_BUSY_MASK 0x1000
#define CP_CPC_STATUS__QU_BUSY__SHIFT 0xc
#define CP_CPC_STATUS__ATCL2IU_BUSY_MASK 0x2000
#define CP_CPC_STATUS__ATCL2IU_BUSY__SHIFT 0xd
#define CP_CPC_STATUS__CPG_CPC_BUSY_MASK 0x20000000
#define CP_CPC_STATUS__CPG_CPC_BUSY__SHIFT 0x1d
#define CP_CPC_STATUS__CPF_CPC_BUSY_MASK 0x40000000
#define CP_CPC_STATUS__CPF_CPC_BUSY__SHIFT 0x1e
#define CP_CPC_STATUS__CPC_BUSY_MASK 0x80000000
#define CP_CPC_STATUS__CPC_BUSY__SHIFT 0x1f
#define CP_CPC_BUSY_STAT__MEC1_LOAD_BUSY_MASK 0x1
#define CP_CPC_BUSY_STAT__MEC1_LOAD_BUSY__SHIFT 0x0
#define CP_CPC_BUSY_STAT__MEC1_SEMAPOHRE_BUSY_MASK 0x2
#define CP_CPC_BUSY_STAT__MEC1_SEMAPOHRE_BUSY__SHIFT 0x1
#define CP_CPC_BUSY_STAT__MEC1_MUTEX_BUSY_MASK 0x4
#define CP_CPC_BUSY_STAT__MEC1_MUTEX_BUSY__SHIFT 0x2
#define CP_CPC_BUSY_STAT__MEC1_MESSAGE_BUSY_MASK 0x8
#define CP_CPC_BUSY_STAT__MEC1_MESSAGE_BUSY__SHIFT 0x3
#define CP_CPC_BUSY_STAT__MEC1_EOP_QUEUE_BUSY_MASK 0x10
#define CP_CPC_BUSY_STAT__MEC1_EOP_QUEUE_BUSY__SHIFT 0x4
#define CP_CPC_BUSY_STAT__MEC1_IQ_QUEUE_BUSY_MASK 0x20
#define CP_CPC_BUSY_STAT__MEC1_IQ_QUEUE_BUSY__SHIFT 0x5
#define CP_CPC_BUSY_STAT__MEC1_IB_QUEUE_BUSY_MASK 0x40
#define CP_CPC_BUSY_STAT__MEC1_IB_QUEUE_BUSY__SHIFT 0x6
#define CP_CPC_BUSY_STAT__MEC1_TC_BUSY_MASK 0x80
#define CP_CPC_BUSY_STAT__MEC1_TC_BUSY__SHIFT 0x7
#define CP_CPC_BUSY_STAT__MEC1_DMA_BUSY_MASK 0x100
#define CP_CPC_BUSY_STAT__MEC1_DMA_BUSY__SHIFT 0x8
#define CP_CPC_BUSY_STAT__MEC1_PARTIAL_FLUSH_BUSY_MASK 0x200
#define CP_CPC_BUSY_STAT__MEC1_PARTIAL_FLUSH_BUSY__SHIFT 0x9
#define CP_CPC_BUSY_STAT__MEC1_PIPE0_BUSY_MASK 0x400
#define CP_CPC_BUSY_STAT__MEC1_PIPE0_BUSY__SHIFT 0xa
#define CP_CPC_BUSY_STAT__MEC1_PIPE1_BUSY_MASK 0x800
#define CP_CPC_BUSY_STAT__MEC1_PIPE1_BUSY__SHIFT 0xb
#define CP_CPC_BUSY_STAT__MEC1_PIPE2_BUSY_MASK 0x1000
#define CP_CPC_BUSY_STAT__MEC1_PIPE2_BUSY__SHIFT 0xc
#define CP_CPC_BUSY_STAT__MEC1_PIPE3_BUSY_MASK 0x2000
#define CP_CPC_BUSY_STAT__MEC1_PIPE3_BUSY__SHIFT 0xd
#define CP_CPC_BUSY_STAT__MEC2_LOAD_BUSY_MASK 0x10000
#define CP_CPC_BUSY_STAT__MEC2_LOAD_BUSY__SHIFT 0x10
#define CP_CPC_BUSY_STAT__MEC2_SEMAPOHRE_BUSY_MASK 0x20000
#define CP_CPC_BUSY_STAT__MEC2_SEMAPOHRE_BUSY__SHIFT 0x11
#define CP_CPC_BUSY_STAT__MEC2_MUTEX_BUSY_MASK 0x40000
#define CP_CPC_BUSY_STAT__MEC2_MUTEX_BUSY__SHIFT 0x12
#define CP_CPC_BUSY_STAT__MEC2_MESSAGE_BUSY_MASK 0x80000
#define CP_CPC_BUSY_STAT__MEC2_MESSAGE_BUSY__SHIFT 0x13
#define CP_CPC_BUSY_STAT__MEC2_EOP_QUEUE_BUSY_MASK 0x100000
#define CP_CPC_BUSY_STAT__MEC2_EOP_QUEUE_BUSY__SHIFT 0x14
#define CP_CPC_BUSY_STAT__MEC2_IQ_QUEUE_BUSY_MASK 0x200000
#define CP_CPC_BUSY_STAT__MEC2_IQ_QUEUE_BUSY__SHIFT 0x15
#define CP_CPC_BUSY_STAT__MEC2_IB_QUEUE_BUSY_MASK 0x400000
#define CP_CPC_BUSY_STAT__MEC2_IB_QUEUE_BUSY__SHIFT 0x16
#define CP_CPC_BUSY_STAT__MEC2_TC_BUSY_MASK 0x800000
#define CP_CPC_BUSY_STAT__MEC2_TC_BUSY__SHIFT 0x17
#define CP_CPC_BUSY_STAT__MEC2_DMA_BUSY_MASK 0x1000000
#define CP_CPC_BUSY_STAT__MEC2_DMA_BUSY__SHIFT 0x18
#define CP_CPC_BUSY_STAT__MEC2_PARTIAL_FLUSH_BUSY_MASK 0x2000000
#define CP_CPC_BUSY_STAT__MEC2_PARTIAL_FLUSH_BUSY__SHIFT 0x19
#define CP_CPC_BUSY_STAT__MEC2_PIPE0_BUSY_MASK 0x4000000
#define CP_CPC_BUSY_STAT__MEC2_PIPE0_BUSY__SHIFT 0x1a
#define CP_CPC_BUSY_STAT__MEC2_PIPE1_BUSY_MASK 0x8000000
#define CP_CPC_BUSY_STAT__MEC2_PIPE1_BUSY__SHIFT 0x1b
#define CP_CPC_BUSY_STAT__MEC2_PIPE2_BUSY_MASK 0x10000000
#define CP_CPC_BUSY_STAT__MEC2_PIPE2_BUSY__SHIFT 0x1c
#define CP_CPC_BUSY_STAT__MEC2_PIPE3_BUSY_MASK 0x20000000
#define CP_CPC_BUSY_STAT__MEC2_PIPE3_BUSY__SHIFT 0x1d
#define CP_CPC_STALLED_STAT1__RCIU_TX_FREE_STALL_MASK 0x8
#define CP_CPC_STALLED_STAT1__RCIU_TX_FREE_STALL__SHIFT 0x3
#define CP_CPC_STALLED_STAT1__RCIU_PRIV_VIOLATION_MASK 0x10
#define CP_CPC_STALLED_STAT1__RCIU_PRIV_VIOLATION__SHIFT 0x4
#define CP_CPC_STALLED_STAT1__TCIU_TX_FREE_STALL_MASK 0x40
#define CP_CPC_STALLED_STAT1__TCIU_TX_FREE_STALL__SHIFT 0x6
#define CP_CPC_STALLED_STAT1__MEC1_DECODING_PACKET_MASK 0x100
#define CP_CPC_STALLED_STAT1__MEC1_DECODING_PACKET__SHIFT 0x8
#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_RCIU_MASK 0x200
#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_RCIU__SHIFT 0x9
#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_RCIU_READ_MASK 0x400
#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_RCIU_READ__SHIFT 0xa
#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_ROQ_DATA_MASK 0x2000
#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_ROQ_DATA__SHIFT 0xd
#define CP_CPC_STALLED_STAT1__MEC2_DECODING_PACKET_MASK 0x10000
#define CP_CPC_STALLED_STAT1__MEC2_DECODING_PACKET__SHIFT 0x10
#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_RCIU_MASK 0x20000
#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_RCIU__SHIFT 0x11
#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_RCIU_READ_MASK 0x40000
#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_RCIU_READ__SHIFT 0x12
#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_ROQ_DATA_MASK 0x200000
#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_ROQ_DATA__SHIFT 0x15
#define CP_CPC_STALLED_STAT1__ATCL2IU_WAITING_ON_FREE_MASK 0x400000
#define CP_CPC_STALLED_STAT1__ATCL2IU_WAITING_ON_FREE__SHIFT 0x16
#define CP_CPC_STALLED_STAT1__ATCL2IU_WAITING_ON_TAGS_MASK 0x800000
#define CP_CPC_STALLED_STAT1__ATCL2IU_WAITING_ON_TAGS__SHIFT 0x17
#define CP_CPC_STALLED_STAT1__ATCL1_WAITING_ON_TRANS_MASK 0x1000000
#define CP_CPC_STALLED_STAT1__ATCL1_WAITING_ON_TRANS__SHIFT 0x18
#define CP_CPF_STATUS__POST_WPTR_GFX_BUSY_MASK 0x1
#define CP_CPF_STATUS__POST_WPTR_GFX_BUSY__SHIFT 0x0
#define CP_CPF_STATUS__CSF_BUSY_MASK 0x2
#define CP_CPF_STATUS__CSF_BUSY__SHIFT 0x1
#define CP_CPF_STATUS__ROQ_ALIGN_BUSY_MASK 0x10
#define CP_CPF_STATUS__ROQ_ALIGN_BUSY__SHIFT 0x4
#define CP_CPF_STATUS__ROQ_RING_BUSY_MASK 0x20
#define CP_CPF_STATUS__ROQ_RING_BUSY__SHIFT 0x5
#define CP_CPF_STATUS__ROQ_INDIRECT1_BUSY_MASK 0x40
#define CP_CPF_STATUS__ROQ_INDIRECT1_BUSY__SHIFT 0x6
#define CP_CPF_STATUS__ROQ_INDIRECT2_BUSY_MASK 0x80
#define CP_CPF_STATUS__ROQ_INDIRECT2_BUSY__SHIFT 0x7
#define CP_CPF_STATUS__ROQ_STATE_BUSY_MASK 0x100
#define CP_CPF_STATUS__ROQ_STATE_BUSY__SHIFT 0x8
#define CP_CPF_STATUS__ROQ_CE_RING_BUSY_MASK 0x200
#define CP_CPF_STATUS__ROQ_CE_RING_BUSY__SHIFT 0x9
#define CP_CPF_STATUS__ROQ_CE_INDIRECT1_BUSY_MASK 0x400
#define CP_CPF_STATUS__ROQ_CE_INDIRECT1_BUSY__SHIFT 0xa
#define CP_CPF_STATUS__ROQ_CE_INDIRECT2_BUSY_MASK 0x800
#define CP_CPF_STATUS__ROQ_CE_INDIRECT2_BUSY__SHIFT 0xb
#define CP_CPF_STATUS__SEMAPHORE_BUSY_MASK 0x1000
#define CP_CPF_STATUS__SEMAPHORE_BUSY__SHIFT 0xc
#define CP_CPF_STATUS__INTERRUPT_BUSY_MASK 0x2000
#define CP_CPF_STATUS__INTERRUPT_BUSY__SHIFT 0xd
#define CP_CPF_STATUS__TCIU_BUSY_MASK 0x4000
#define CP_CPF_STATUS__TCIU_BUSY__SHIFT 0xe
#define CP_CPF_STATUS__HQD_BUSY_MASK 0x8000
#define CP_CPF_STATUS__HQD_BUSY__SHIFT 0xf
#define CP_CPF_STATUS__PRT_BUSY_MASK 0x10000
#define CP_CPF_STATUS__PRT_BUSY__SHIFT 0x10
#define CP_CPF_STATUS__ATCL2IU_BUSY_MASK 0x20000
#define CP_CPF_STATUS__ATCL2IU_BUSY__SHIFT 0x11
#define CP_CPF_STATUS__CPF_GFX_BUSY_MASK 0x4000000
#define CP_CPF_STATUS__CPF_GFX_BUSY__SHIFT 0x1a
#define CP_CPF_STATUS__CPF_CMP_BUSY_MASK 0x8000000
#define CP_CPF_STATUS__CPF_CMP_BUSY__SHIFT 0x1b
#define CP_CPF_STATUS__GRBM_CPF_STAT_BUSY_MASK 0x30000000
#define CP_CPF_STATUS__GRBM_CPF_STAT_BUSY__SHIFT 0x1c
#define CP_CPF_STATUS__CPC_CPF_BUSY_MASK 0x40000000
#define CP_CPF_STATUS__CPC_CPF_BUSY__SHIFT 0x1e
#define CP_CPF_STATUS__CPF_BUSY_MASK 0x80000000
#define CP_CPF_STATUS__CPF_BUSY__SHIFT 0x1f
#define CP_CPF_BUSY_STAT__REG_BUS_FIFO_BUSY_MASK 0x1
#define CP_CPF_BUSY_STAT__REG_BUS_FIFO_BUSY__SHIFT 0x0
#define CP_CPF_BUSY_STAT__CSF_RING_BUSY_MASK 0x2
#define CP_CPF_BUSY_STAT__CSF_RING_BUSY__SHIFT 0x1
#define CP_CPF_BUSY_STAT__CSF_INDIRECT1_BUSY_MASK 0x4
#define CP_CPF_BUSY_STAT__CSF_INDIRECT1_BUSY__SHIFT 0x2
#define CP_CPF_BUSY_STAT__CSF_INDIRECT2_BUSY_MASK 0x8
#define CP_CPF_BUSY_STAT__CSF_INDIRECT2_BUSY__SHIFT 0x3
#define CP_CPF_BUSY_STAT__CSF_STATE_BUSY_MASK 0x10
#define CP_CPF_BUSY_STAT__CSF_STATE_BUSY__SHIFT 0x4
#define CP_CPF_BUSY_STAT__CSF_CE_INDR1_BUSY_MASK 0x20
#define CP_CPF_BUSY_STAT__CSF_CE_INDR1_BUSY__SHIFT 0x5
#define CP_CPF_BUSY_STAT__CSF_CE_INDR2_BUSY_MASK 0x40
#define CP_CPF_BUSY_STAT__CSF_CE_INDR2_BUSY__SHIFT 0x6
#define CP_CPF_BUSY_STAT__CSF_ARBITER_BUSY_MASK 0x80
#define CP_CPF_BUSY_STAT__CSF_ARBITER_BUSY__SHIFT 0x7
#define CP_CPF_BUSY_STAT__CSF_INPUT_BUSY_MASK 0x100
#define CP_CPF_BUSY_STAT__CSF_INPUT_BUSY__SHIFT 0x8
#define CP_CPF_BUSY_STAT__OUTSTANDING_READ_TAGS_MASK 0x200
#define CP_CPF_BUSY_STAT__OUTSTANDING_READ_TAGS__SHIFT 0x9
#define CP_CPF_BUSY_STAT__HPD_PROCESSING_EOP_BUSY_MASK 0x800
#define CP_CPF_BUSY_STAT__HPD_PROCESSING_EOP_BUSY__SHIFT 0xb
#define CP_CPF_BUSY_STAT__HQD_DISPATCH_BUSY_MASK 0x1000
#define CP_CPF_BUSY_STAT__HQD_DISPATCH_BUSY__SHIFT 0xc
#define CP_CPF_BUSY_STAT__HQD_IQ_TIMER_BUSY_MASK 0x2000
#define CP_CPF_BUSY_STAT__HQD_IQ_TIMER_BUSY__SHIFT 0xd
#define CP_CPF_BUSY_STAT__HQD_DMA_OFFLOAD_BUSY_MASK 0x4000
#define CP_CPF_BUSY_STAT__HQD_DMA_OFFLOAD_BUSY__SHIFT 0xe
#define CP_CPF_BUSY_STAT__HQD_WAIT_SEMAPHORE_BUSY_MASK 0x8000
#define CP_CPF_BUSY_STAT__HQD_WAIT_SEMAPHORE_BUSY__SHIFT 0xf
#define CP_CPF_BUSY_STAT__HQD_SIGNAL_SEMAPHORE_BUSY_MASK 0x10000
#define CP_CPF_BUSY_STAT__HQD_SIGNAL_SEMAPHORE_BUSY__SHIFT 0x10
#define CP_CPF_BUSY_STAT__HQD_MESSAGE_BUSY_MASK 0x20000
#define CP_CPF_BUSY_STAT__HQD_MESSAGE_BUSY__SHIFT 0x11
#define CP_CPF_BUSY_STAT__HQD_PQ_FETCHER_BUSY_MASK 0x40000
#define CP_CPF_BUSY_STAT__HQD_PQ_FETCHER_BUSY__SHIFT 0x12
#define CP_CPF_BUSY_STAT__HQD_IB_FETCHER_BUSY_MASK 0x80000
#define CP_CPF_BUSY_STAT__HQD_IB_FETCHER_BUSY__SHIFT 0x13
#define CP_CPF_BUSY_STAT__HQD_IQ_FETCHER_BUSY_MASK 0x100000
#define CP_CPF_BUSY_STAT__HQD_IQ_FETCHER_BUSY__SHIFT 0x14
#define CP_CPF_BUSY_STAT__HQD_EOP_FETCHER_BUSY_MASK 0x200000
#define CP_CPF_BUSY_STAT__HQD_EOP_FETCHER_BUSY__SHIFT 0x15
#define CP_CPF_BUSY_STAT__HQD_CONSUMED_RPTR_BUSY_MASK 0x400000
#define CP_CPF_BUSY_STAT__HQD_CONSUMED_RPTR_BUSY__SHIFT 0x16
#define CP_CPF_BUSY_STAT__HQD_FETCHER_ARB_BUSY_MASK 0x800000
#define CP_CPF_BUSY_STAT__HQD_FETCHER_ARB_BUSY__SHIFT 0x17
#define CP_CPF_BUSY_STAT__HQD_ROQ_ALIGN_BUSY_MASK 0x1000000
#define CP_CPF_BUSY_STAT__HQD_ROQ_ALIGN_BUSY__SHIFT 0x18
#define CP_CPF_BUSY_STAT__HQD_ROQ_EOP_BUSY_MASK 0x2000000
#define CP_CPF_BUSY_STAT__HQD_ROQ_EOP_BUSY__SHIFT 0x19
#define CP_CPF_BUSY_STAT__HQD_ROQ_IQ_BUSY_MASK 0x4000000
#define CP_CPF_BUSY_STAT__HQD_ROQ_IQ_BUSY__SHIFT 0x1a
#define CP_CPF_BUSY_STAT__HQD_ROQ_PQ_BUSY_MASK 0x8000000
#define CP_CPF_BUSY_STAT__HQD_ROQ_PQ_BUSY__SHIFT 0x1b
#define CP_CPF_BUSY_STAT__HQD_ROQ_IB_BUSY_MASK 0x10000000
#define CP_CPF_BUSY_STAT__HQD_ROQ_IB_BUSY__SHIFT 0x1c
#define CP_CPF_BUSY_STAT__HQD_WPTR_POLL_BUSY_MASK 0x20000000
#define CP_CPF_BUSY_STAT__HQD_WPTR_POLL_BUSY__SHIFT 0x1d
#define CP_CPF_BUSY_STAT__HQD_PQ_BUSY_MASK 0x40000000
#define CP_CPF_BUSY_STAT__HQD_PQ_BUSY__SHIFT 0x1e
#define CP_CPF_BUSY_STAT__HQD_IB_BUSY_MASK 0x80000000
#define CP_CPF_BUSY_STAT__HQD_IB_BUSY__SHIFT 0x1f
#define CP_CPF_STALLED_STAT1__RING_FETCHING_DATA_MASK 0x1
#define CP_CPF_STALLED_STAT1__RING_FETCHING_DATA__SHIFT 0x0
#define CP_CPF_STALLED_STAT1__INDR1_FETCHING_DATA_MASK 0x2
#define CP_CPF_STALLED_STAT1__INDR1_FETCHING_DATA__SHIFT 0x1
#define CP_CPF_STALLED_STAT1__INDR2_FETCHING_DATA_MASK 0x4
#define CP_CPF_STALLED_STAT1__INDR2_FETCHING_DATA__SHIFT 0x2
#define CP_CPF_STALLED_STAT1__STATE_FETCHING_DATA_MASK 0x8
#define CP_CPF_STALLED_STAT1__STATE_FETCHING_DATA__SHIFT 0x3
#define CP_CPF_STALLED_STAT1__TCIU_WAITING_ON_FREE_MASK 0x20
#define CP_CPF_STALLED_STAT1__TCIU_WAITING_ON_FREE__SHIFT 0x5
#define CP_CPF_STALLED_STAT1__TCIU_WAITING_ON_TAGS_MASK 0x40
#define CP_CPF_STALLED_STAT1__TCIU_WAITING_ON_TAGS__SHIFT 0x6
#define CP_CPF_STALLED_STAT1__ATCL2IU_WAITING_ON_FREE_MASK 0x80
#define CP_CPF_STALLED_STAT1__ATCL2IU_WAITING_ON_FREE__SHIFT 0x7
#define CP_CPF_STALLED_STAT1__ATCL2IU_WAITING_ON_TAGS_MASK 0x100
#define CP_CPF_STALLED_STAT1__ATCL2IU_WAITING_ON_TAGS__SHIFT 0x8
#define CP_CPF_STALLED_STAT1__ATCL1_WAITING_ON_TRANS_MASK 0x200
#define CP_CPF_STALLED_STAT1__ATCL1_WAITING_ON_TRANS__SHIFT 0x9
#define CP_CPC_GRBM_FREE_COUNT__FREE_COUNT_MASK 0x3f
#define CP_CPC_GRBM_FREE_COUNT__FREE_COUNT__SHIFT 0x0
#define CP_MEC_CNTL__MEC_INVALIDATE_ICACHE_MASK 0x10
#define CP_MEC_CNTL__MEC_INVALIDATE_ICACHE__SHIFT 0x4
#define CP_MEC_CNTL__MEC_ME1_PIPE0_RESET_MASK 0x10000
#define CP_MEC_CNTL__MEC_ME1_PIPE0_RESET__SHIFT 0x10
#define CP_MEC_CNTL__MEC_ME1_PIPE1_RESET_MASK 0x20000
#define CP_MEC_CNTL__MEC_ME1_PIPE1_RESET__SHIFT 0x11
#define CP_MEC_CNTL__MEC_ME1_PIPE2_RESET_MASK 0x40000
#define CP_MEC_CNTL__MEC_ME1_PIPE2_RESET__SHIFT 0x12
#define CP_MEC_CNTL__MEC_ME1_PIPE3_RESET_MASK 0x80000
#define CP_MEC_CNTL__MEC_ME1_PIPE3_RESET__SHIFT 0x13
#define CP_MEC_CNTL__MEC_ME2_PIPE0_RESET_MASK 0x100000
#define CP_MEC_CNTL__MEC_ME2_PIPE0_RESET__SHIFT 0x14
#define CP_MEC_CNTL__MEC_ME2_PIPE1_RESET_MASK 0x200000
#define CP_MEC_CNTL__MEC_ME2_PIPE1_RESET__SHIFT 0x15
#define CP_MEC_CNTL__MEC_ME2_HALT_MASK 0x10000000
#define CP_MEC_CNTL__MEC_ME2_HALT__SHIFT 0x1c
#define CP_MEC_CNTL__MEC_ME2_STEP_MASK 0x20000000
#define CP_MEC_CNTL__MEC_ME2_STEP__SHIFT 0x1d
#define CP_MEC_CNTL__MEC_ME1_HALT_MASK 0x40000000
#define CP_MEC_CNTL__MEC_ME1_HALT__SHIFT 0x1e
#define CP_MEC_CNTL__MEC_ME1_STEP_MASK 0x80000000
#define CP_MEC_CNTL__MEC_ME1_STEP__SHIFT 0x1f
#define CP_MEC_ME1_HEADER_DUMP__HEADER_DUMP_MASK 0xffffffff
#define CP_MEC_ME1_HEADER_DUMP__HEADER_DUMP__SHIFT 0x0
#define CP_MEC_ME2_HEADER_DUMP__HEADER_DUMP_MASK 0xffffffff
#define CP_MEC_ME2_HEADER_DUMP__HEADER_DUMP__SHIFT 0x0
#define CP_CPC_SCRATCH_INDEX__SCRATCH_INDEX_MASK 0x1ff
#define CP_CPC_SCRATCH_INDEX__SCRATCH_INDEX__SHIFT 0x0
#define CP_CPC_SCRATCH_DATA__SCRATCH_DATA_MASK 0xffffffff
#define CP_CPC_SCRATCH_DATA__SCRATCH_DATA__SHIFT 0x0
#define CPG_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x3f
#define CPG_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
#define CPG_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff
#define CPG_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
#define CPG_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff
#define CPG_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
#define CPG_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x3f
#define CPG_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0
#define CPG_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0xfc00
#define CPG_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
#define CPG_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x3f
#define CPG_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
#define CPG_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0xfc00
#define CPG_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
#define CPG_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000
#define CPG_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
#define CPG_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff
#define CPG_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
#define CPG_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff
#define CPG_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
#define CPC_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x3f
#define CPC_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
#define CPC_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff
#define CPC_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
#define CPC_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff
#define CPC_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
#define CPC_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x3f
#define CPC_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0
#define CPC_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0xfc00
#define CPC_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
#define CPC_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x3f
#define CPC_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
#define CPC_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0xfc00
#define CPC_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
#define CPC_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000
#define CPC_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
#define CPC_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff
#define CPC_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
#define CPC_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff
#define CPC_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
#define CPF_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x3f
#define CPF_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
#define CPF_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff
#define CPF_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
#define CPF_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff
#define CPF_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
#define CPF_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x3f
#define CPF_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0
#define CPF_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0xfc00
#define CPF_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
#define CPF_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x3f
#define CPF_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
#define CPF_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0xfc00
#define CPF_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
#define CPF_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000
#define CPF_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
#define CPF_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff
#define CPF_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
#define CPF_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff
#define CPF_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
#define CP_CPC_HALT_HYST_COUNT__COUNT_MASK 0xf
#define CP_CPC_HALT_HYST_COUNT__COUNT__SHIFT 0x0
#define CP_DRAW_OBJECT__OBJECT_MASK 0xffffffff
#define CP_DRAW_OBJECT__OBJECT__SHIFT 0x0
#define CP_DRAW_OBJECT_COUNTER__COUNT_MASK 0xffff
#define CP_DRAW_OBJECT_COUNTER__COUNT__SHIFT 0x0
#define CP_DRAW_WINDOW_MASK_HI__WINDOW_MASK_HI_MASK 0xffffffff
#define CP_DRAW_WINDOW_MASK_HI__WINDOW_MASK_HI__SHIFT 0x0
#define CP_DRAW_WINDOW_HI__WINDOW_HI_MASK 0xffffffff
#define CP_DRAW_WINDOW_HI__WINDOW_HI__SHIFT 0x0
#define CP_DRAW_WINDOW_LO__MIN_MASK 0xffff
#define CP_DRAW_WINDOW_LO__MIN__SHIFT 0x0
#define CP_DRAW_WINDOW_LO__MAX_MASK 0xffff0000
#define CP_DRAW_WINDOW_LO__MAX__SHIFT 0x10
#define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_LO_MAX_MASK 0x1
#define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_LO_MAX__SHIFT 0x0
#define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_LO_MIN_MASK 0x2
#define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_LO_MIN__SHIFT 0x1
#define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_HI_MASK 0x4
#define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_HI__SHIFT 0x2
#define CP_DRAW_WINDOW_CNTL__MODE_MASK 0x100
#define CP_DRAW_WINDOW_CNTL__MODE__SHIFT 0x8
#define CP_PRT_LOD_STATS_CNTL0__BU_SIZE_MASK 0xffffffff
#define CP_PRT_LOD_STATS_CNTL0__BU_SIZE__SHIFT 0x0
#define CP_PRT_LOD_STATS_CNTL1__BASE_LO_MASK 0xffffffff
#define CP_PRT_LOD_STATS_CNTL1__BASE_LO__SHIFT 0x0
#define CP_PRT_LOD_STATS_CNTL2__BASE_HI_MASK 0x3
#define CP_PRT_LOD_STATS_CNTL2__BASE_HI__SHIFT 0x0
#define CP_PRT_LOD_STATS_CNTL2__INTERVAL_MASK 0x3fc
#define CP_PRT_LOD_STATS_CNTL2__INTERVAL__SHIFT 0x2
#define CP_PRT_LOD_STATS_CNTL2__RESET_CNT_MASK 0x3fc00
#define CP_PRT_LOD_STATS_CNTL2__RESET_CNT__SHIFT 0xa
#define CP_PRT_LOD_STATS_CNTL2__RESET_FORCE_MASK 0x40000
#define CP_PRT_LOD_STATS_CNTL2__RESET_FORCE__SHIFT 0x12
#define CP_PRT_LOD_STATS_CNTL2__REPORT_AND_RESET_MASK 0x80000
#define CP_PRT_LOD_STATS_CNTL2__REPORT_AND_RESET__SHIFT 0x13
#define CP_PRT_LOD_STATS_CNTL2__MC_VMID_MASK 0x7800000
#define CP_PRT_LOD_STATS_CNTL2__MC_VMID__SHIFT 0x17
#define CP_PRT_LOD_STATS_CNTL2__CACHE_POLICY_MASK 0x10000000
#define CP_PRT_LOD_STATS_CNTL2__CACHE_POLICY__SHIFT 0x1c
#define CP_PRT_LOD_STATS_CNTL2__MTYPE_MASK 0xc0000000
#define CP_PRT_LOD_STATS_CNTL2__MTYPE__SHIFT 0x1e
#define CP_CE_COMPARE_COUNT__COMPARE_COUNT_MASK 0xffffffff
#define CP_CE_COMPARE_COUNT__COMPARE_COUNT__SHIFT 0x0
#define CP_CE_DE_COUNT__DRAW_ENGINE_COUNT_MASK 0xffffffff
#define CP_CE_DE_COUNT__DRAW_ENGINE_COUNT__SHIFT 0x0
#define CP_DE_CE_COUNT__CONST_ENGINE_COUNT_MASK 0xffffffff
#define CP_DE_CE_COUNT__CONST_ENGINE_COUNT__SHIFT 0x0
#define CP_DE_LAST_INVAL_COUNT__LAST_INVAL_COUNT_MASK 0xffffffff
#define CP_DE_LAST_INVAL_COUNT__LAST_INVAL_COUNT__SHIFT 0x0
#define CP_DE_DE_COUNT__DRAW_ENGINE_COUNT_MASK 0xffffffff
#define CP_DE_DE_COUNT__DRAW_ENGINE_COUNT__SHIFT 0x0
#define CP_EOP_DONE_EVENT_CNTL__WBINV_TC_OP_MASK 0x7f
#define CP_EOP_DONE_EVENT_CNTL__WBINV_TC_OP__SHIFT 0x0
#define CP_EOP_DONE_EVENT_CNTL__WBINV_ACTION_ENA_MASK 0x3f000
#define CP_EOP_DONE_EVENT_CNTL__WBINV_ACTION_ENA__SHIFT 0xc
#define CP_EOP_DONE_EVENT_CNTL__CACHE_CONTROL_MASK 0x2000000
#define CP_EOP_DONE_EVENT_CNTL__CACHE_CONTROL__SHIFT 0x19
#define CP_EOP_DONE_EVENT_CNTL__MTYPE_MASK 0x18000000
#define CP_EOP_DONE_EVENT_CNTL__MTYPE__SHIFT 0x1b
#define CP_EOP_DONE_DATA_CNTL__CNTX_ID_MASK 0xffff
#define CP_EOP_DONE_DATA_CNTL__CNTX_ID__SHIFT 0x0
#define CP_EOP_DONE_DATA_CNTL__DST_SEL_MASK 0x30000
#define CP_EOP_DONE_DATA_CNTL__DST_SEL__SHIFT 0x10
#define CP_EOP_DONE_DATA_CNTL__INT_SEL_MASK 0x7000000
#define CP_EOP_DONE_DATA_CNTL__INT_SEL__SHIFT 0x18
#define CP_EOP_DONE_DATA_CNTL__DATA_SEL_MASK 0xe0000000
#define CP_EOP_DONE_DATA_CNTL__DATA_SEL__SHIFT 0x1d
#define CP_EOP_DONE_CNTX_ID__CNTX_ID_MASK 0xfffffff
#define CP_EOP_DONE_CNTX_ID__CNTX_ID__SHIFT 0x0
#define CP_EOP_DONE_ADDR_LO__ADDR_LO_MASK 0xfffffffc
#define CP_EOP_DONE_ADDR_LO__ADDR_LO__SHIFT 0x2
#define CP_EOP_DONE_ADDR_HI__ADDR_HI_MASK 0xffff
#define CP_EOP_DONE_ADDR_HI__ADDR_HI__SHIFT 0x0
#define CP_EOP_DONE_DATA_LO__DATA_LO_MASK 0xffffffff
#define CP_EOP_DONE_DATA_LO__DATA_LO__SHIFT 0x0
#define CP_EOP_DONE_DATA_HI__DATA_HI_MASK 0xffffffff
#define CP_EOP_DONE_DATA_HI__DATA_HI__SHIFT 0x0
#define CP_EOP_LAST_FENCE_LO__LAST_FENCE_LO_MASK 0xffffffff
#define CP_EOP_LAST_FENCE_LO__LAST_FENCE_LO__SHIFT 0x0
#define CP_EOP_LAST_FENCE_HI__LAST_FENCE_HI_MASK 0xffffffff
#define CP_EOP_LAST_FENCE_HI__LAST_FENCE_HI__SHIFT 0x0
#define CP_STREAM_OUT_ADDR_LO__STREAM_OUT_ADDR_LO_MASK 0xfffffffc
#define CP_STREAM_OUT_ADDR_LO__STREAM_OUT_ADDR_LO__SHIFT 0x2
#define CP_STREAM_OUT_ADDR_HI__STREAM_OUT_ADDR_HI_MASK 0xffff
#define CP_STREAM_OUT_ADDR_HI__STREAM_OUT_ADDR_HI__SHIFT 0x0
#define CP_NUM_PRIM_WRITTEN_COUNT0_LO__NUM_PRIM_WRITTEN_CNT0_LO_MASK 0xffffffff
#define CP_NUM_PRIM_WRITTEN_COUNT0_LO__NUM_PRIM_WRITTEN_CNT0_LO__SHIFT 0x0
#define CP_NUM_PRIM_WRITTEN_COUNT0_HI__NUM_PRIM_WRITTEN_CNT0_HI_MASK 0xffffffff
#define CP_NUM_PRIM_WRITTEN_COUNT0_HI__NUM_PRIM_WRITTEN_CNT0_HI__SHIFT 0x0
#define CP_NUM_PRIM_NEEDED_COUNT0_LO__NUM_PRIM_NEEDED_CNT0_LO_MASK 0xffffffff
#define CP_NUM_PRIM_NEEDED_COUNT0_LO__NUM_PRIM_NEEDED_CNT0_LO__SHIFT 0x0
#define CP_NUM_PRIM_NEEDED_COUNT0_HI__NUM_PRIM_NEEDED_CNT0_HI_MASK 0xffffffff
#define CP_NUM_PRIM_NEEDED_COUNT0_HI__NUM_PRIM_NEEDED_CNT0_HI__SHIFT 0x0
#define CP_NUM_PRIM_WRITTEN_COUNT1_LO__NUM_PRIM_WRITTEN_CNT1_LO_MASK 0xffffffff
#define CP_NUM_PRIM_WRITTEN_COUNT1_LO__NUM_PRIM_WRITTEN_CNT1_LO__SHIFT 0x0
#define CP_NUM_PRIM_WRITTEN_COUNT1_HI__NUM_PRIM_WRITTEN_CNT1_HI_MASK 0xffffffff
#define CP_NUM_PRIM_WRITTEN_COUNT1_HI__NUM_PRIM_WRITTEN_CNT1_HI__SHIFT 0x0
#define CP_NUM_PRIM_NEEDED_COUNT1_LO__NUM_PRIM_NEEDED_CNT1_LO_MASK 0xffffffff
#define CP_NUM_PRIM_NEEDED_COUNT1_LO__NUM_PRIM_NEEDED_CNT1_LO__SHIFT 0x0
#define CP_NUM_PRIM_NEEDED_COUNT1_HI__NUM_PRIM_NEEDED_CNT1_HI_MASK 0xffffffff
#define CP_NUM_PRIM_NEEDED_COUNT1_HI__NUM_PRIM_NEEDED_CNT1_HI__SHIFT 0x0
#define CP_NUM_PRIM_WRITTEN_COUNT2_LO__NUM_PRIM_WRITTEN_CNT2_LO_MASK 0xffffffff
#define CP_NUM_PRIM_WRITTEN_COUNT2_LO__NUM_PRIM_WRITTEN_CNT2_LO__SHIFT 0x0
#define CP_NUM_PRIM_WRITTEN_COUNT2_HI__NUM_PRIM_WRITTEN_CNT2_HI_MASK 0xffffffff
#define CP_NUM_PRIM_WRITTEN_COUNT2_HI__NUM_PRIM_WRITTEN_CNT2_HI__SHIFT 0x0
#define CP_NUM_PRIM_NEEDED_COUNT2_LO__NUM_PRIM_NEEDED_CNT2_LO_MASK 0xffffffff
#define CP_NUM_PRIM_NEEDED_COUNT2_LO__NUM_PRIM_NEEDED_CNT2_LO__SHIFT 0x0
#define CP_NUM_PRIM_NEEDED_COUNT2_HI__NUM_PRIM_NEEDED_CNT2_HI_MASK 0xffffffff
#define CP_NUM_PRIM_NEEDED_COUNT2_HI__NUM_PRIM_NEEDED_CNT2_HI__SHIFT 0x0
#define CP_NUM_PRIM_WRITTEN_COUNT3_LO__NUM_PRIM_WRITTEN_CNT3_LO_MASK 0xffffffff
#define CP_NUM_PRIM_WRITTEN_COUNT3_LO__NUM_PRIM_WRITTEN_CNT3_LO__SHIFT 0x0
#define CP_NUM_PRIM_WRITTEN_COUNT3_HI__NUM_PRIM_WRITTEN_CNT3_HI_MASK 0xffffffff
#define CP_NUM_PRIM_WRITTEN_COUNT3_HI__NUM_PRIM_WRITTEN_CNT3_HI__SHIFT 0x0
#define CP_NUM_PRIM_NEEDED_COUNT3_LO__NUM_PRIM_NEEDED_CNT3_LO_MASK 0xffffffff
#define CP_NUM_PRIM_NEEDED_COUNT3_LO__NUM_PRIM_NEEDED_CNT3_LO__SHIFT 0x0
#define CP_NUM_PRIM_NEEDED_COUNT3_HI__NUM_PRIM_NEEDED_CNT3_HI_MASK 0xffffffff
#define CP_NUM_PRIM_NEEDED_COUNT3_HI__NUM_PRIM_NEEDED_CNT3_HI__SHIFT 0x0
#define CP_PIPE_STATS_ADDR_LO__PIPE_STATS_ADDR_LO_MASK 0xfffffffc
#define CP_PIPE_STATS_ADDR_LO__PIPE_STATS_ADDR_LO__SHIFT 0x2
#define CP_PIPE_STATS_ADDR_HI__PIPE_STATS_ADDR_HI_MASK 0xffff
#define CP_PIPE_STATS_ADDR_HI__PIPE_STATS_ADDR_HI__SHIFT 0x0
#define CP_VGT_IAVERT_COUNT_LO__IAVERT_COUNT_LO_MASK 0xffffffff
#define CP_VGT_IAVERT_COUNT_LO__IAVERT_COUNT_LO__SHIFT 0x0
#define CP_VGT_IAVERT_COUNT_HI__IAVERT_COUNT_HI_MASK 0xffffffff
#define CP_VGT_IAVERT_COUNT_HI__IAVERT_COUNT_HI__SHIFT 0x0
#define CP_VGT_IAPRIM_COUNT_LO__IAPRIM_COUNT_LO_MASK 0xffffffff
#define CP_VGT_IAPRIM_COUNT_LO__IAPRIM_COUNT_LO__SHIFT 0x0
#define CP_VGT_IAPRIM_COUNT_HI__IAPRIM_COUNT_HI_MASK 0xffffffff
#define CP_VGT_IAPRIM_COUNT_HI__IAPRIM_COUNT_HI__SHIFT 0x0
#define CP_VGT_GSPRIM_COUNT_LO__GSPRIM_COUNT_LO_MASK 0xffffffff
#define CP_VGT_GSPRIM_COUNT_LO__GSPRIM_COUNT_LO__SHIFT 0x0
#define CP_VGT_GSPRIM_COUNT_HI__GSPRIM_COUNT_HI_MASK 0xffffffff
#define CP_VGT_GSPRIM_COUNT_HI__GSPRIM_COUNT_HI__SHIFT 0x0
#define CP_VGT_VSINVOC_COUNT_LO__VSINVOC_COUNT_LO_MASK 0xffffffff
#define CP_VGT_VSINVOC_COUNT_LO__VSINVOC_COUNT_LO__SHIFT 0x0
#define CP_VGT_VSINVOC_COUNT_HI__VSINVOC_COUNT_HI_MASK 0xffffffff
#define CP_VGT_VSINVOC_COUNT_HI__VSINVOC_COUNT_HI__SHIFT 0x0
#define CP_VGT_GSINVOC_COUNT_LO__GSINVOC_COUNT_LO_MASK 0xffffffff
#define CP_VGT_GSINVOC_COUNT_LO__GSINVOC_COUNT_LO__SHIFT 0x0
#define CP_VGT_GSINVOC_COUNT_HI__GSINVOC_COUNT_HI_MASK 0xffffffff
#define CP_VGT_GSINVOC_COUNT_HI__GSINVOC_COUNT_HI__SHIFT 0x0
#define CP_VGT_HSINVOC_COUNT_LO__HSINVOC_COUNT_LO_MASK 0xffffffff
#define CP_VGT_HSINVOC_COUNT_LO__HSINVOC_COUNT_LO__SHIFT 0x0
#define CP_VGT_HSINVOC_COUNT_HI__HSINVOC_COUNT_HI_MASK 0xffffffff
#define CP_VGT_HSINVOC_COUNT_HI__HSINVOC_COUNT_HI__SHIFT 0x0
#define CP_VGT_DSINVOC_COUNT_LO__DSINVOC_COUNT_LO_MASK 0xffffffff
#define CP_VGT_DSINVOC_COUNT_LO__DSINVOC_COUNT_LO__SHIFT 0x0
#define CP_VGT_DSINVOC_COUNT_HI__DSINVOC_COUNT_HI_MASK 0xffffffff
#define CP_VGT_DSINVOC_COUNT_HI__DSINVOC_COUNT_HI__SHIFT 0x0
#define CP_PA_CINVOC_COUNT_LO__CINVOC_COUNT_LO_MASK 0xffffffff
#define CP_PA_CINVOC_COUNT_LO__CINVOC_COUNT_LO__SHIFT 0x0
#define CP_PA_CINVOC_COUNT_HI__CINVOC_COUNT_HI_MASK 0xffffffff
#define CP_PA_CINVOC_COUNT_HI__CINVOC_COUNT_HI__SHIFT 0x0
#define CP_PA_CPRIM_COUNT_LO__CPRIM_COUNT_LO_MASK 0xffffffff
#define CP_PA_CPRIM_COUNT_LO__CPRIM_COUNT_LO__SHIFT 0x0
#define CP_PA_CPRIM_COUNT_HI__CPRIM_COUNT_HI_MASK 0xffffffff
#define CP_PA_CPRIM_COUNT_HI__CPRIM_COUNT_HI__SHIFT 0x0
#define CP_SC_PSINVOC_COUNT0_LO__PSINVOC_COUNT0_LO_MASK 0xffffffff
#define CP_SC_PSINVOC_COUNT0_LO__PSINVOC_COUNT0_LO__SHIFT 0x0
#define CP_SC_PSINVOC_COUNT0_HI__PSINVOC_COUNT0_HI_MASK 0xffffffff
#define CP_SC_PSINVOC_COUNT0_HI__PSINVOC_COUNT0_HI__SHIFT 0x0
#define CP_SC_PSINVOC_COUNT1_LO__OBSOLETE_MASK 0xffffffff
#define CP_SC_PSINVOC_COUNT1_LO__OBSOLETE__SHIFT 0x0
#define CP_SC_PSINVOC_COUNT1_HI__OBSOLETE_MASK 0xffffffff
#define CP_SC_PSINVOC_COUNT1_HI__OBSOLETE__SHIFT 0x0
#define CP_VGT_CSINVOC_COUNT_LO__CSINVOC_COUNT_LO_MASK 0xffffffff
#define CP_VGT_CSINVOC_COUNT_LO__CSINVOC_COUNT_LO__SHIFT 0x0
#define CP_VGT_CSINVOC_COUNT_HI__CSINVOC_COUNT_HI_MASK 0xffffffff
#define CP_VGT_CSINVOC_COUNT_HI__CSINVOC_COUNT_HI__SHIFT 0x0
#define CP_PIPE_STATS_CONTROL__CACHE_CONTROL_MASK 0x2000000
#define CP_PIPE_STATS_CONTROL__CACHE_CONTROL__SHIFT 0x19
#define CP_PIPE_STATS_CONTROL__MTYPE_MASK 0x18000000
#define CP_PIPE_STATS_CONTROL__MTYPE__SHIFT 0x1b
#define CP_STREAM_OUT_CONTROL__CACHE_CONTROL_MASK 0x2000000
#define CP_STREAM_OUT_CONTROL__CACHE_CONTROL__SHIFT 0x19
#define CP_STREAM_OUT_CONTROL__MTYPE_MASK 0x18000000
#define CP_STREAM_OUT_CONTROL__MTYPE__SHIFT 0x1b
#define CP_STRMOUT_CNTL__OFFSET_UPDATE_DONE_MASK 0x1
#define CP_STRMOUT_CNTL__OFFSET_UPDATE_DONE__SHIFT 0x0
#define SCRATCH_REG0__SCRATCH_REG0_MASK 0xffffffff
#define SCRATCH_REG0__SCRATCH_REG0__SHIFT 0x0
#define SCRATCH_REG1__SCRATCH_REG1_MASK 0xffffffff
#define SCRATCH_REG1__SCRATCH_REG1__SHIFT 0x0
#define SCRATCH_REG2__SCRATCH_REG2_MASK 0xffffffff
#define SCRATCH_REG2__SCRATCH_REG2__SHIFT 0x0
#define SCRATCH_REG3__SCRATCH_REG3_MASK 0xffffffff
#define SCRATCH_REG3__SCRATCH_REG3__SHIFT 0x0
#define SCRATCH_REG4__SCRATCH_REG4_MASK 0xffffffff
#define SCRATCH_REG4__SCRATCH_REG4__SHIFT 0x0
#define SCRATCH_REG5__SCRATCH_REG5_MASK 0xffffffff
#define SCRATCH_REG5__SCRATCH_REG5__SHIFT 0x0
#define SCRATCH_REG6__SCRATCH_REG6_MASK 0xffffffff
#define SCRATCH_REG6__SCRATCH_REG6__SHIFT 0x0
#define SCRATCH_REG7__SCRATCH_REG7_MASK 0xffffffff
#define SCRATCH_REG7__SCRATCH_REG7__SHIFT 0x0
#define SCRATCH_UMSK__OBSOLETE_UMSK_MASK 0xff
#define SCRATCH_UMSK__OBSOLETE_UMSK__SHIFT 0x0
#define SCRATCH_UMSK__OBSOLETE_SWAP_MASK 0x30000
#define SCRATCH_UMSK__OBSOLETE_SWAP__SHIFT 0x10
#define SCRATCH_ADDR__OBSOLETE_ADDR_MASK 0xffffffff
#define SCRATCH_ADDR__OBSOLETE_ADDR__SHIFT 0x0
#define CP_PFP_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO_MASK 0xffffffff
#define CP_PFP_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO__SHIFT 0x0
#define CP_PFP_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI_MASK 0xffffffff
#define CP_PFP_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI__SHIFT 0x0
#define CP_PFP_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO_MASK 0xffffffff
#define CP_PFP_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO__SHIFT 0x0
#define CP_PFP_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI_MASK 0xffffffff
#define CP_PFP_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI__SHIFT 0x0
#define CP_PFP_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO_MASK 0xffffffff
#define CP_PFP_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO__SHIFT 0x0
#define CP_PFP_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI_MASK 0xffffffff
#define CP_PFP_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI__SHIFT 0x0
#define CP_APPEND_ADDR_LO__MEM_ADDR_LO_MASK 0xfffffffc
#define CP_APPEND_ADDR_LO__MEM_ADDR_LO__SHIFT 0x2
#define CP_APPEND_ADDR_HI__MEM_ADDR_HI_MASK 0xffff
#define CP_APPEND_ADDR_HI__MEM_ADDR_HI__SHIFT 0x0
#define CP_APPEND_ADDR_HI__CS_PS_SEL_MASK 0x10000
#define CP_APPEND_ADDR_HI__CS_PS_SEL__SHIFT 0x10
#define CP_APPEND_ADDR_HI__CACHE_POLICY_MASK 0x2000000
#define CP_APPEND_ADDR_HI__CACHE_POLICY__SHIFT 0x19
#define CP_APPEND_ADDR_HI__MTYPE_MASK 0x18000000
#define CP_APPEND_ADDR_HI__MTYPE__SHIFT 0x1b
#define CP_APPEND_ADDR_HI__COMMAND_MASK 0xe0000000
#define CP_APPEND_ADDR_HI__COMMAND__SHIFT 0x1d
#define CP_APPEND_DATA__DATA_MASK 0xffffffff
#define CP_APPEND_DATA__DATA__SHIFT 0x0
#define CP_APPEND_LAST_CS_FENCE__LAST_FENCE_MASK 0xffffffff
#define CP_APPEND_LAST_CS_FENCE__LAST_FENCE__SHIFT 0x0
#define CP_APPEND_LAST_PS_FENCE__LAST_FENCE_MASK 0xffffffff
#define CP_APPEND_LAST_PS_FENCE__LAST_FENCE__SHIFT 0x0
#define CP_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO_MASK 0xffffffff
#define CP_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO__SHIFT 0x0
#define CP_ME_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO_MASK 0xffffffff
#define CP_ME_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO__SHIFT 0x0
#define CP_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI_MASK 0xffffffff
#define CP_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI__SHIFT 0x0
#define CP_ME_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI_MASK 0xffffffff
#define CP_ME_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI__SHIFT 0x0
#define CP_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO_MASK 0xffffffff
#define CP_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO__SHIFT 0x0
#define CP_ME_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO_MASK 0xffffffff
#define CP_ME_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO__SHIFT 0x0
#define CP_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI_MASK 0xffffffff
#define CP_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI__SHIFT 0x0
#define CP_ME_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI_MASK 0xffffffff
#define CP_ME_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI__SHIFT 0x0
#define CP_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO_MASK 0xffffffff
#define CP_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO__SHIFT 0x0
#define CP_ME_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO_MASK 0xffffffff
#define CP_ME_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO__SHIFT 0x0
#define CP_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI_MASK 0xffffffff
#define CP_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI__SHIFT 0x0
#define CP_ME_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI_MASK 0xffffffff
#define CP_ME_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI__SHIFT 0x0
#define CP_ME_MC_WADDR_LO__ME_MC_WADDR_SWAP_MASK 0x3
#define CP_ME_MC_WADDR_LO__ME_MC_WADDR_SWAP__SHIFT 0x0
#define CP_ME_MC_WADDR_LO__ME_MC_WADDR_LO_MASK 0xfffffffc
#define CP_ME_MC_WADDR_LO__ME_MC_WADDR_LO__SHIFT 0x2
#define CP_ME_MC_WADDR_HI__ME_MC_WADDR_HI_MASK 0xffff
#define CP_ME_MC_WADDR_HI__ME_MC_WADDR_HI__SHIFT 0x0
#define CP_ME_MC_WADDR_HI__MTYPE_MASK 0x300000
#define CP_ME_MC_WADDR_HI__MTYPE__SHIFT 0x14
#define CP_ME_MC_WADDR_HI__CACHE_POLICY_MASK 0x400000
#define CP_ME_MC_WADDR_HI__CACHE_POLICY__SHIFT 0x16
#define CP_ME_MC_WDATA_LO__ME_MC_WDATA_LO_MASK 0xffffffff
#define CP_ME_MC_WDATA_LO__ME_MC_WDATA_LO__SHIFT 0x0
#define CP_ME_MC_WDATA_HI__ME_MC_WDATA_HI_MASK 0xffffffff
#define CP_ME_MC_WDATA_HI__ME_MC_WDATA_HI__SHIFT 0x0
#define CP_ME_MC_RADDR_LO__ME_MC_RADDR_SWAP_MASK 0x3
#define CP_ME_MC_RADDR_LO__ME_MC_RADDR_SWAP__SHIFT 0x0
#define CP_ME_MC_RADDR_LO__ME_MC_RADDR_LO_MASK 0xfffffffc
#define CP_ME_MC_RADDR_LO__ME_MC_RADDR_LO__SHIFT 0x2
#define CP_ME_MC_RADDR_HI__ME_MC_RADDR_HI_MASK 0xffff
#define CP_ME_MC_RADDR_HI__ME_MC_RADDR_HI__SHIFT 0x0
#define CP_ME_MC_RADDR_HI__MTYPE_MASK 0x300000
#define CP_ME_MC_RADDR_HI__MTYPE__SHIFT 0x14
#define CP_ME_MC_RADDR_HI__CACHE_POLICY_MASK 0x400000
#define CP_ME_MC_RADDR_HI__CACHE_POLICY__SHIFT 0x16
#define CP_SEM_WAIT_TIMER__SEM_WAIT_TIMER_MASK 0xffffffff
#define CP_SEM_WAIT_TIMER__SEM_WAIT_TIMER__SHIFT 0x0
#define CP_SIG_SEM_ADDR_LO__SEM_ADDR_SWAP_MASK 0x3
#define CP_SIG_SEM_ADDR_LO__SEM_ADDR_SWAP__SHIFT 0x0
#define CP_SIG_SEM_ADDR_LO__SEM_ADDR_LO_MASK 0xfffffff8
#define CP_SIG_SEM_ADDR_LO__SEM_ADDR_LO__SHIFT 0x3
#define CP_SIG_SEM_ADDR_HI__SEM_ADDR_HI_MASK 0xffff
#define CP_SIG_SEM_ADDR_HI__SEM_ADDR_HI__SHIFT 0x0
#define CP_SIG_SEM_ADDR_HI__SEM_USE_MAILBOX_MASK 0x10000
#define CP_SIG_SEM_ADDR_HI__SEM_USE_MAILBOX__SHIFT 0x10
#define CP_SIG_SEM_ADDR_HI__SEM_SIGNAL_TYPE_MASK 0x100000
#define CP_SIG_SEM_ADDR_HI__SEM_SIGNAL_TYPE__SHIFT 0x14
#define CP_SIG_SEM_ADDR_HI__SEM_CLIENT_CODE_MASK 0x3000000
#define CP_SIG_SEM_ADDR_HI__SEM_CLIENT_CODE__SHIFT 0x18
#define CP_SIG_SEM_ADDR_HI__SEM_SELECT_MASK 0xe0000000
#define CP_SIG_SEM_ADDR_HI__SEM_SELECT__SHIFT 0x1d
#define CP_WAIT_SEM_ADDR_LO__SEM_ADDR_SWAP_MASK 0x3
#define CP_WAIT_SEM_ADDR_LO__SEM_ADDR_SWAP__SHIFT 0x0
#define CP_WAIT_SEM_ADDR_LO__SEM_ADDR_LO_MASK 0xfffffff8
#define CP_WAIT_SEM_ADDR_LO__SEM_ADDR_LO__SHIFT 0x3
#define CP_WAIT_SEM_ADDR_HI__SEM_ADDR_HI_MASK 0xffff
#define CP_WAIT_SEM_ADDR_HI__SEM_ADDR_HI__SHIFT 0x0
#define CP_WAIT_SEM_ADDR_HI__SEM_USE_MAILBOX_MASK 0x10000
#define CP_WAIT_SEM_ADDR_HI__SEM_USE_MAILBOX__SHIFT 0x10
#define CP_WAIT_SEM_ADDR_HI__SEM_SIGNAL_TYPE_MASK 0x100000
#define CP_WAIT_SEM_ADDR_HI__SEM_SIGNAL_TYPE__SHIFT 0x14
#define CP_WAIT_SEM_ADDR_HI__SEM_CLIENT_CODE_MASK 0x3000000
#define CP_WAIT_SEM_ADDR_HI__SEM_CLIENT_CODE__SHIFT 0x18
#define CP_WAIT_SEM_ADDR_HI__SEM_SELECT_MASK 0xe0000000
#define CP_WAIT_SEM_ADDR_HI__SEM_SELECT__SHIFT 0x1d
#define CP_WAIT_REG_MEM_TIMEOUT__WAIT_REG_MEM_TIMEOUT_MASK 0xffffffff
#define CP_WAIT_REG_MEM_TIMEOUT__WAIT_REG_MEM_TIMEOUT__SHIFT 0x0
#define CP_COHER_START_DELAY__START_DELAY_COUNT_MASK 0x3f
#define CP_COHER_START_DELAY__START_DELAY_COUNT__SHIFT 0x0
#define CP_COHER_CNTL__DEST_BASE_0_ENA_MASK 0x1
#define CP_COHER_CNTL__DEST_BASE_0_ENA__SHIFT 0x0
#define CP_COHER_CNTL__DEST_BASE_1_ENA_MASK 0x2
#define CP_COHER_CNTL__DEST_BASE_1_ENA__SHIFT 0x1
#define CP_COHER_CNTL__TC_SD_ACTION_ENA_MASK 0x4
#define CP_COHER_CNTL__TC_SD_ACTION_ENA__SHIFT 0x2
#define CP_COHER_CNTL__TC_NC_ACTION_ENA_MASK 0x8
#define CP_COHER_CNTL__TC_NC_ACTION_ENA__SHIFT 0x3
#define CP_COHER_CNTL__CB0_DEST_BASE_ENA_MASK 0x40
#define CP_COHER_CNTL__CB0_DEST_BASE_ENA__SHIFT 0x6
#define CP_COHER_CNTL__CB1_DEST_BASE_ENA_MASK 0x80
#define CP_COHER_CNTL__CB1_DEST_BASE_ENA__SHIFT 0x7
#define CP_COHER_CNTL__CB2_DEST_BASE_ENA_MASK 0x100
#define CP_COHER_CNTL__CB2_DEST_BASE_ENA__SHIFT 0x8
#define CP_COHER_CNTL__CB3_DEST_BASE_ENA_MASK 0x200
#define CP_COHER_CNTL__CB3_DEST_BASE_ENA__SHIFT 0x9
#define CP_COHER_CNTL__CB4_DEST_BASE_ENA_MASK 0x400
#define CP_COHER_CNTL__CB4_DEST_BASE_ENA__SHIFT 0xa
#define CP_COHER_CNTL__CB5_DEST_BASE_ENA_MASK 0x800
#define CP_COHER_CNTL__CB5_DEST_BASE_ENA__SHIFT 0xb
#define CP_COHER_CNTL__CB6_DEST_BASE_ENA_MASK 0x1000
#define CP_COHER_CNTL__CB6_DEST_BASE_ENA__SHIFT 0xc
#define CP_COHER_CNTL__CB7_DEST_BASE_ENA_MASK 0x2000
#define CP_COHER_CNTL__CB7_DEST_BASE_ENA__SHIFT 0xd
#define CP_COHER_CNTL__DB_DEST_BASE_ENA_MASK 0x4000
#define CP_COHER_CNTL__DB_DEST_BASE_ENA__SHIFT 0xe
#define CP_COHER_CNTL__TCL1_VOL_ACTION_ENA_MASK 0x8000
#define CP_COHER_CNTL__TCL1_VOL_ACTION_ENA__SHIFT 0xf
#define CP_COHER_CNTL__TC_WB_ACTION_ENA_MASK 0x40000
#define CP_COHER_CNTL__TC_WB_ACTION_ENA__SHIFT 0x12
#define CP_COHER_CNTL__DEST_BASE_2_ENA_MASK 0x80000
#define CP_COHER_CNTL__DEST_BASE_2_ENA__SHIFT 0x13
#define CP_COHER_CNTL__DEST_BASE_3_ENA_MASK 0x200000
#define CP_COHER_CNTL__DEST_BASE_3_ENA__SHIFT 0x15
#define CP_COHER_CNTL__TCL1_ACTION_ENA_MASK 0x400000
#define CP_COHER_CNTL__TCL1_ACTION_ENA__SHIFT 0x16
#define CP_COHER_CNTL__TC_ACTION_ENA_MASK 0x800000
#define CP_COHER_CNTL__TC_ACTION_ENA__SHIFT 0x17
#define CP_COHER_CNTL__CB_ACTION_ENA_MASK 0x2000000
#define CP_COHER_CNTL__CB_ACTION_ENA__SHIFT 0x19
#define CP_COHER_CNTL__DB_ACTION_ENA_MASK 0x4000000
#define CP_COHER_CNTL__DB_ACTION_ENA__SHIFT 0x1a
#define CP_COHER_CNTL__SH_KCACHE_ACTION_ENA_MASK 0x8000000
#define CP_COHER_CNTL__SH_KCACHE_ACTION_ENA__SHIFT 0x1b
#define CP_COHER_CNTL__SH_KCACHE_VOL_ACTION_ENA_MASK 0x10000000
#define CP_COHER_CNTL__SH_KCACHE_VOL_ACTION_ENA__SHIFT 0x1c
#define CP_COHER_CNTL__SH_ICACHE_ACTION_ENA_MASK 0x20000000
#define CP_COHER_CNTL__SH_ICACHE_ACTION_ENA__SHIFT 0x1d
#define CP_COHER_CNTL__SH_KCACHE_WB_ACTION_ENA_MASK 0x40000000
#define CP_COHER_CNTL__SH_KCACHE_WB_ACTION_ENA__SHIFT 0x1e
#define CP_COHER_CNTL__SH_SD_ACTION_ENA_MASK 0x80000000
#define CP_COHER_CNTL__SH_SD_ACTION_ENA__SHIFT 0x1f
#define CP_COHER_SIZE__COHER_SIZE_256B_MASK 0xffffffff
#define CP_COHER_SIZE__COHER_SIZE_256B__SHIFT 0x0
#define CP_COHER_SIZE_HI__COHER_SIZE_HI_256B_MASK 0xff
#define CP_COHER_SIZE_HI__COHER_SIZE_HI_256B__SHIFT 0x0
#define CP_COHER_BASE__COHER_BASE_256B_MASK 0xffffffff
#define CP_COHER_BASE__COHER_BASE_256B__SHIFT 0x0
#define CP_COHER_BASE_HI__COHER_BASE_HI_256B_MASK 0xff
#define CP_COHER_BASE_HI__COHER_BASE_HI_256B__SHIFT 0x0
#define CP_COHER_STATUS__MATCHING_GFX_CNTX_MASK 0xff
#define CP_COHER_STATUS__MATCHING_GFX_CNTX__SHIFT 0x0
#define CP_COHER_STATUS__MEID_MASK 0x3000000
#define CP_COHER_STATUS__MEID__SHIFT 0x18
#define CP_COHER_STATUS__PHASE1_STATUS_MASK 0x40000000
#define CP_COHER_STATUS__PHASE1_STATUS__SHIFT 0x1e
#define CP_COHER_STATUS__STATUS_MASK 0x80000000
#define CP_COHER_STATUS__STATUS__SHIFT 0x1f
#define COHER_DEST_BASE_0__DEST_BASE_256B_MASK 0xffffffff
#define COHER_DEST_BASE_0__DEST_BASE_256B__SHIFT 0x0
#define COHER_DEST_BASE_1__DEST_BASE_256B_MASK 0xffffffff
#define COHER_DEST_BASE_1__DEST_BASE_256B__SHIFT 0x0
#define COHER_DEST_BASE_2__DEST_BASE_256B_MASK 0xffffffff
#define COHER_DEST_BASE_2__DEST_BASE_256B__SHIFT 0x0
#define COHER_DEST_BASE_3__DEST_BASE_256B_MASK 0xffffffff
#define COHER_DEST_BASE_3__DEST_BASE_256B__SHIFT 0x0
#define COHER_DEST_BASE_HI_0__DEST_BASE_HI_256B_MASK 0xffffffff
#define COHER_DEST_BASE_HI_0__DEST_BASE_HI_256B__SHIFT 0x0
#define COHER_DEST_BASE_HI_1__DEST_BASE_HI_256B_MASK 0xffffffff
#define COHER_DEST_BASE_HI_1__DEST_BASE_HI_256B__SHIFT 0x0
#define COHER_DEST_BASE_HI_2__DEST_BASE_HI_256B_MASK 0xffffffff
#define COHER_DEST_BASE_HI_2__DEST_BASE_HI_256B__SHIFT 0x0
#define COHER_DEST_BASE_HI_3__DEST_BASE_HI_256B_MASK 0xffffffff
#define COHER_DEST_BASE_HI_3__DEST_BASE_HI_256B__SHIFT 0x0
#define CP_DMA_ME_SRC_ADDR__SRC_ADDR_MASK 0xffffffff
#define CP_DMA_ME_SRC_ADDR__SRC_ADDR__SHIFT 0x0
#define CP_DMA_ME_SRC_ADDR_HI__SRC_ADDR_HI_MASK 0xffff
#define CP_DMA_ME_SRC_ADDR_HI__SRC_ADDR_HI__SHIFT 0x0
#define CP_DMA_ME_DST_ADDR__DST_ADDR_MASK 0xffffffff
#define CP_DMA_ME_DST_ADDR__DST_ADDR__SHIFT 0x0
#define CP_DMA_ME_DST_ADDR_HI__DST_ADDR_HI_MASK 0xffff
#define CP_DMA_ME_DST_ADDR_HI__DST_ADDR_HI__SHIFT 0x0
#define CP_DMA_ME_CONTROL__SRC_MTYPE_MASK 0xc00
#define CP_DMA_ME_CONTROL__SRC_MTYPE__SHIFT 0xa
#define CP_DMA_ME_CONTROL__SRC_ATC_MASK 0x1000
#define CP_DMA_ME_CONTROL__SRC_ATC__SHIFT 0xc
#define CP_DMA_ME_CONTROL__SRC_CACHE_POLICY_MASK 0x2000
#define CP_DMA_ME_CONTROL__SRC_CACHE_POLICY__SHIFT 0xd
#define CP_DMA_ME_CONTROL__DST_SELECT_MASK 0x300000
#define CP_DMA_ME_CONTROL__DST_SELECT__SHIFT 0x14
#define CP_DMA_ME_CONTROL__DST_MTYPE_MASK 0xc00000
#define CP_DMA_ME_CONTROL__DST_MTYPE__SHIFT 0x16
#define CP_DMA_ME_CONTROL__DST_ATC_MASK 0x1000000
#define CP_DMA_ME_CONTROL__DST_ATC__SHIFT 0x18
#define CP_DMA_ME_CONTROL__DST_CACHE_POLICY_MASK 0x2000000
#define CP_DMA_ME_CONTROL__DST_CACHE_POLICY__SHIFT 0x19
#define CP_DMA_ME_CONTROL__SRC_SELECT_MASK 0x60000000
#define CP_DMA_ME_CONTROL__SRC_SELECT__SHIFT 0x1d
#define CP_DMA_ME_COMMAND__BYTE_COUNT_MASK 0x1fffff
#define CP_DMA_ME_COMMAND__BYTE_COUNT__SHIFT 0x0
#define CP_DMA_ME_COMMAND__DIS_WC_MASK 0x200000
#define CP_DMA_ME_COMMAND__DIS_WC__SHIFT 0x15
#define CP_DMA_ME_COMMAND__SRC_SWAP_MASK 0xc00000
#define CP_DMA_ME_COMMAND__SRC_SWAP__SHIFT 0x16
#define CP_DMA_ME_COMMAND__DST_SWAP_MASK 0x3000000
#define CP_DMA_ME_COMMAND__DST_SWAP__SHIFT 0x18
#define CP_DMA_ME_COMMAND__SAS_MASK 0x4000000
#define CP_DMA_ME_COMMAND__SAS__SHIFT 0x1a
#define CP_DMA_ME_COMMAND__DAS_MASK 0x8000000
#define CP_DMA_ME_COMMAND__DAS__SHIFT 0x1b
#define CP_DMA_ME_COMMAND__SAIC_MASK 0x10000000
#define CP_DMA_ME_COMMAND__SAIC__SHIFT 0x1c
#define CP_DMA_ME_COMMAND__DAIC_MASK 0x20000000
#define CP_DMA_ME_COMMAND__DAIC__SHIFT 0x1d
#define CP_DMA_ME_COMMAND__RAW_WAIT_MASK 0x40000000
#define CP_DMA_ME_COMMAND__RAW_WAIT__SHIFT 0x1e
#define CP_DMA_PFP_SRC_ADDR__SRC_ADDR_MASK 0xffffffff
#define CP_DMA_PFP_SRC_ADDR__SRC_ADDR__SHIFT 0x0
#define CP_DMA_PFP_SRC_ADDR_HI__SRC_ADDR_HI_MASK 0xffff
#define CP_DMA_PFP_SRC_ADDR_HI__SRC_ADDR_HI__SHIFT 0x0
#define CP_DMA_PFP_DST_ADDR__DST_ADDR_MASK 0xffffffff
#define CP_DMA_PFP_DST_ADDR__DST_ADDR__SHIFT 0x0
#define CP_DMA_PFP_DST_ADDR_HI__DST_ADDR_HI_MASK 0xffff
#define CP_DMA_PFP_DST_ADDR_HI__DST_ADDR_HI__SHIFT 0x0
#define CP_DMA_PFP_CONTROL__SRC_MTYPE_MASK 0xc00
#define CP_DMA_PFP_CONTROL__SRC_MTYPE__SHIFT 0xa
#define CP_DMA_PFP_CONTROL__SRC_ATC_MASK 0x1000
#define CP_DMA_PFP_CONTROL__SRC_ATC__SHIFT 0xc
#define CP_DMA_PFP_CONTROL__SRC_CACHE_POLICY_MASK 0x2000
#define CP_DMA_PFP_CONTROL__SRC_CACHE_POLICY__SHIFT 0xd
#define CP_DMA_PFP_CONTROL__DST_SELECT_MASK 0x300000
#define CP_DMA_PFP_CONTROL__DST_SELECT__SHIFT 0x14
#define CP_DMA_PFP_CONTROL__DST_MTYPE_MASK 0xc00000
#define CP_DMA_PFP_CONTROL__DST_MTYPE__SHIFT 0x16
#define CP_DMA_PFP_CONTROL__DST_ATC_MASK 0x1000000
#define CP_DMA_PFP_CONTROL__DST_ATC__SHIFT 0x18
#define CP_DMA_PFP_CONTROL__DST_CACHE_POLICY_MASK 0x2000000
#define CP_DMA_PFP_CONTROL__DST_CACHE_POLICY__SHIFT 0x19
#define CP_DMA_PFP_CONTROL__SRC_SELECT_MASK 0x60000000
#define CP_DMA_PFP_CONTROL__SRC_SELECT__SHIFT 0x1d
#define CP_DMA_PFP_COMMAND__BYTE_COUNT_MASK 0x1fffff
#define CP_DMA_PFP_COMMAND__BYTE_COUNT__SHIFT 0x0
#define CP_DMA_PFP_COMMAND__DIS_WC_MASK 0x200000
#define CP_DMA_PFP_COMMAND__DIS_WC__SHIFT 0x15
#define CP_DMA_PFP_COMMAND__SRC_SWAP_MASK 0xc00000
#define CP_DMA_PFP_COMMAND__SRC_SWAP__SHIFT 0x16
#define CP_DMA_PFP_COMMAND__DST_SWAP_MASK 0x3000000
#define CP_DMA_PFP_COMMAND__DST_SWAP__SHIFT 0x18
#define CP_DMA_PFP_COMMAND__SAS_MASK 0x4000000
#define CP_DMA_PFP_COMMAND__SAS__SHIFT 0x1a
#define CP_DMA_PFP_COMMAND__DAS_MASK 0x8000000
#define CP_DMA_PFP_COMMAND__DAS__SHIFT 0x1b
#define CP_DMA_PFP_COMMAND__SAIC_MASK 0x10000000
#define CP_DMA_PFP_COMMAND__SAIC__SHIFT 0x1c
#define CP_DMA_PFP_COMMAND__DAIC_MASK 0x20000000
#define CP_DMA_PFP_COMMAND__DAIC__SHIFT 0x1d
#define CP_DMA_PFP_COMMAND__RAW_WAIT_MASK 0x40000000
#define CP_DMA_PFP_COMMAND__RAW_WAIT__SHIFT 0x1e
#define CP_DMA_CNTL__MIN_AVAILSZ_MASK 0x30
#define CP_DMA_CNTL__MIN_AVAILSZ__SHIFT 0x4
#define CP_DMA_CNTL__BUFFER_DEPTH_MASK 0xf0000
#define CP_DMA_CNTL__BUFFER_DEPTH__SHIFT 0x10
#define CP_DMA_CNTL__PIO_FIFO_EMPTY_MASK 0x10000000
#define CP_DMA_CNTL__PIO_FIFO_EMPTY__SHIFT 0x1c
#define CP_DMA_CNTL__PIO_FIFO_FULL_MASK 0x20000000
#define CP_DMA_CNTL__PIO_FIFO_FULL__SHIFT 0x1d
#define CP_DMA_CNTL__PIO_COUNT_MASK 0xc0000000
#define CP_DMA_CNTL__PIO_COUNT__SHIFT 0x1e
#define CP_DMA_READ_TAGS__DMA_READ_TAG_MASK 0x3ffffff
#define CP_DMA_READ_TAGS__DMA_READ_TAG__SHIFT 0x0
#define CP_DMA_READ_TAGS__DMA_READ_TAG_VALID_MASK 0x10000000
#define CP_DMA_READ_TAGS__DMA_READ_TAG_VALID__SHIFT 0x1c
#define CP_PFP_IB_CONTROL__IB_EN_MASK 0xff
#define CP_PFP_IB_CONTROL__IB_EN__SHIFT 0x0
#define CP_PFP_LOAD_CONTROL__CONFIG_REG_EN_MASK 0x1
#define CP_PFP_LOAD_CONTROL__CONFIG_REG_EN__SHIFT 0x0
#define CP_PFP_LOAD_CONTROL__CNTX_REG_EN_MASK 0x2
#define CP_PFP_LOAD_CONTROL__CNTX_REG_EN__SHIFT 0x1
#define CP_PFP_LOAD_CONTROL__SH_GFX_REG_EN_MASK 0x10000
#define CP_PFP_LOAD_CONTROL__SH_GFX_REG_EN__SHIFT 0x10
#define CP_PFP_LOAD_CONTROL__SH_CS_REG_EN_MASK 0x1000000
#define CP_PFP_LOAD_CONTROL__SH_CS_REG_EN__SHIFT 0x18
#define CP_SCRATCH_INDEX__SCRATCH_INDEX_MASK 0xff
#define CP_SCRATCH_INDEX__SCRATCH_INDEX__SHIFT 0x0
#define CP_SCRATCH_DATA__SCRATCH_DATA_MASK 0xffffffff
#define CP_SCRATCH_DATA__SCRATCH_DATA__SHIFT 0x0
#define CP_RB_OFFSET__RB_OFFSET_MASK 0xfffff
#define CP_RB_OFFSET__RB_OFFSET__SHIFT 0x0
#define CP_IB1_OFFSET__IB1_OFFSET_MASK 0xfffff
#define CP_IB1_OFFSET__IB1_OFFSET__SHIFT 0x0
#define CP_IB2_OFFSET__IB2_OFFSET_MASK 0xfffff
#define CP_IB2_OFFSET__IB2_OFFSET__SHIFT 0x0
#define CP_IB1_PREAMBLE_BEGIN__IB1_PREAMBLE_BEGIN_MASK 0xfffff
#define CP_IB1_PREAMBLE_BEGIN__IB1_PREAMBLE_BEGIN__SHIFT 0x0
#define CP_IB1_PREAMBLE_END__IB1_PREAMBLE_END_MASK 0xfffff
#define CP_IB1_PREAMBLE_END__IB1_PREAMBLE_END__SHIFT 0x0
#define CP_IB2_PREAMBLE_BEGIN__IB2_PREAMBLE_BEGIN_MASK 0xfffff
#define CP_IB2_PREAMBLE_BEGIN__IB2_PREAMBLE_BEGIN__SHIFT 0x0
#define CP_IB2_PREAMBLE_END__IB2_PREAMBLE_END_MASK 0xfffff
#define CP_IB2_PREAMBLE_END__IB2_PREAMBLE_END__SHIFT 0x0
#define CP_CE_IB1_OFFSET__IB1_OFFSET_MASK 0xfffff
#define CP_CE_IB1_OFFSET__IB1_OFFSET__SHIFT 0x0
#define CP_CE_IB2_OFFSET__IB2_OFFSET_MASK 0xfffff
#define CP_CE_IB2_OFFSET__IB2_OFFSET__SHIFT 0x0
#define CP_CE_COUNTER__CONST_ENGINE_COUNT_MASK 0xffffffff
#define CP_CE_COUNTER__CONST_ENGINE_COUNT__SHIFT 0x0
#define CP_CE_RB_OFFSET__RB_OFFSET_MASK 0xfffff
#define CP_CE_RB_OFFSET__RB_OFFSET__SHIFT 0x0
#define CP_PFP_COMPLETION_STATUS__STATUS_MASK 0x3
#define CP_PFP_COMPLETION_STATUS__STATUS__SHIFT 0x0
#define CP_CE_COMPLETION_STATUS__STATUS_MASK 0x3
#define CP_CE_COMPLETION_STATUS__STATUS__SHIFT 0x0
#define CP_PRED_NOT_VISIBLE__NOT_VISIBLE_MASK 0x1
#define CP_PRED_NOT_VISIBLE__NOT_VISIBLE__SHIFT 0x0
#define CP_PFP_METADATA_BASE_ADDR__ADDR_LO_MASK 0xffffffff
#define CP_PFP_METADATA_BASE_ADDR__ADDR_LO__SHIFT 0x0
#define CP_PFP_METADATA_BASE_ADDR_HI__ADDR_HI_MASK 0xffff
#define CP_PFP_METADATA_BASE_ADDR_HI__ADDR_HI__SHIFT 0x0
#define CP_CE_METADATA_BASE_ADDR__ADDR_LO_MASK 0xffffffff
#define CP_CE_METADATA_BASE_ADDR__ADDR_LO__SHIFT 0x0
#define CP_CE_METADATA_BASE_ADDR_HI__ADDR_HI_MASK 0xffff
#define CP_CE_METADATA_BASE_ADDR_HI__ADDR_HI__SHIFT 0x0
#define CP_DRAW_INDX_INDR_ADDR__ADDR_LO_MASK 0xffffffff
#define CP_DRAW_INDX_INDR_ADDR__ADDR_LO__SHIFT 0x0
#define CP_DRAW_INDX_INDR_ADDR_HI__ADDR_HI_MASK 0xffff
#define CP_DRAW_INDX_INDR_ADDR_HI__ADDR_HI__SHIFT 0x0
#define CP_DISPATCH_INDR_ADDR__ADDR_LO_MASK 0xffffffff
#define CP_DISPATCH_INDR_ADDR__ADDR_LO__SHIFT 0x0
#define CP_DISPATCH_INDR_ADDR_HI__ADDR_HI_MASK 0xffff
#define CP_DISPATCH_INDR_ADDR_HI__ADDR_HI__SHIFT 0x0
#define CP_INDEX_BASE_ADDR__ADDR_LO_MASK 0xffffffff
#define CP_INDEX_BASE_ADDR__ADDR_LO__SHIFT 0x0
#define CP_INDEX_BASE_ADDR_HI__ADDR_HI_MASK 0xffff
#define CP_INDEX_BASE_ADDR_HI__ADDR_HI__SHIFT 0x0
#define CP_INDEX_TYPE__INDEX_TYPE_MASK 0x3
#define CP_INDEX_TYPE__INDEX_TYPE__SHIFT 0x0
#define CP_GDS_BKUP_ADDR__ADDR_LO_MASK 0xffffffff
#define CP_GDS_BKUP_ADDR__ADDR_LO__SHIFT 0x0
#define CP_GDS_BKUP_ADDR_HI__ADDR_HI_MASK 0xffff
#define CP_GDS_BKUP_ADDR_HI__ADDR_HI__SHIFT 0x0
#define CP_SAMPLE_STATUS__Z_PASS_ACITVE_MASK 0x1
#define CP_SAMPLE_STATUS__Z_PASS_ACITVE__SHIFT 0x0
#define CP_SAMPLE_STATUS__STREAMOUT_ACTIVE_MASK 0x2
#define CP_SAMPLE_STATUS__STREAMOUT_ACTIVE__SHIFT 0x1
#define CP_SAMPLE_STATUS__PIPELINE_ACTIVE_MASK 0x4
#define CP_SAMPLE_STATUS__PIPELINE_ACTIVE__SHIFT 0x2
#define CP_SAMPLE_STATUS__STIPPLE_ACTIVE_MASK 0x8
#define CP_SAMPLE_STATUS__STIPPLE_ACTIVE__SHIFT 0x3
#define CP_SAMPLE_STATUS__VGT_BUFFERS_ACTIVE_MASK 0x10
#define CP_SAMPLE_STATUS__VGT_BUFFERS_ACTIVE__SHIFT 0x4
#define CP_SAMPLE_STATUS__SCREEN_EXT_ACTIVE_MASK 0x20
#define CP_SAMPLE_STATUS__SCREEN_EXT_ACTIVE__SHIFT 0x5
#define CP_SAMPLE_STATUS__DRAW_INDIRECT_ACTIVE_MASK 0x40
#define CP_SAMPLE_STATUS__DRAW_INDIRECT_ACTIVE__SHIFT 0x6
#define CP_SAMPLE_STATUS__DISP_INDIRECT_ACTIVE_MASK 0x80
#define CP_SAMPLE_STATUS__DISP_INDIRECT_ACTIVE__SHIFT 0x7
#define CP_STALLED_STAT1__RBIU_TO_DMA_NOT_RDY_TO_RCV_MASK 0x1
#define CP_STALLED_STAT1__RBIU_TO_DMA_NOT_RDY_TO_RCV__SHIFT 0x0
#define CP_STALLED_STAT1__RBIU_TO_SEM_NOT_RDY_TO_RCV_MASK 0x4
#define CP_STALLED_STAT1__RBIU_TO_SEM_NOT_RDY_TO_RCV__SHIFT 0x2
#define CP_STALLED_STAT1__RBIU_TO_MEMWR_NOT_RDY_TO_RCV_MASK 0x10
#define CP_STALLED_STAT1__RBIU_TO_MEMWR_NOT_RDY_TO_RCV__SHIFT 0x4
#define CP_STALLED_STAT1__ME_HAS_ACTIVE_CE_BUFFER_FLAG_MASK 0x400
#define CP_STALLED_STAT1__ME_HAS_ACTIVE_CE_BUFFER_FLAG__SHIFT 0xa
#define CP_STALLED_STAT1__ME_HAS_ACTIVE_DE_BUFFER_FLAG_MASK 0x800
#define CP_STALLED_STAT1__ME_HAS_ACTIVE_DE_BUFFER_FLAG__SHIFT 0xb
#define CP_STALLED_STAT1__ME_STALLED_ON_TC_WR_CONFIRM_MASK 0x1000
#define CP_STALLED_STAT1__ME_STALLED_ON_TC_WR_CONFIRM__SHIFT 0xc
#define CP_STALLED_STAT1__ME_STALLED_ON_ATOMIC_RTN_DATA_MASK 0x2000
#define CP_STALLED_STAT1__ME_STALLED_ON_ATOMIC_RTN_DATA__SHIFT 0xd
#define CP_STALLED_STAT1__ME_WAITING_ON_TC_READ_DATA_MASK 0x4000
#define CP_STALLED_STAT1__ME_WAITING_ON_TC_READ_DATA__SHIFT 0xe
#define CP_STALLED_STAT1__ME_WAITING_ON_REG_READ_DATA_MASK 0x8000
#define CP_STALLED_STAT1__ME_WAITING_ON_REG_READ_DATA__SHIFT 0xf
#define CP_STALLED_STAT1__RCIU_WAITING_ON_GDS_FREE_MASK 0x800000
#define CP_STALLED_STAT1__RCIU_WAITING_ON_GDS_FREE__SHIFT 0x17
#define CP_STALLED_STAT1__RCIU_WAITING_ON_GRBM_FREE_MASK 0x1000000
#define CP_STALLED_STAT1__RCIU_WAITING_ON_GRBM_FREE__SHIFT 0x18
#define CP_STALLED_STAT1__RCIU_WAITING_ON_VGT_FREE_MASK 0x2000000
#define CP_STALLED_STAT1__RCIU_WAITING_ON_VGT_FREE__SHIFT 0x19
#define CP_STALLED_STAT1__RCIU_STALLED_ON_ME_READ_MASK 0x4000000
#define CP_STALLED_STAT1__RCIU_STALLED_ON_ME_READ__SHIFT 0x1a
#define CP_STALLED_STAT1__RCIU_STALLED_ON_DMA_READ_MASK 0x8000000
#define CP_STALLED_STAT1__RCIU_STALLED_ON_DMA_READ__SHIFT 0x1b
#define CP_STALLED_STAT1__RCIU_STALLED_ON_APPEND_READ_MASK 0x10000000
#define CP_STALLED_STAT1__RCIU_STALLED_ON_APPEND_READ__SHIFT 0x1c
#define CP_STALLED_STAT1__RCIU_HALTED_BY_REG_VIOLATION_MASK 0x20000000
#define CP_STALLED_STAT1__RCIU_HALTED_BY_REG_VIOLATION__SHIFT 0x1d
#define CP_STALLED_STAT2__PFP_TO_CSF_NOT_RDY_TO_RCV_MASK 0x1
#define CP_STALLED_STAT2__PFP_TO_CSF_NOT_RDY_TO_RCV__SHIFT 0x0
#define CP_STALLED_STAT2__PFP_TO_MEQ_NOT_RDY_TO_RCV_MASK 0x2
#define CP_STALLED_STAT2__PFP_TO_MEQ_NOT_RDY_TO_RCV__SHIFT 0x1
#define CP_STALLED_STAT2__PFP_TO_RCIU_NOT_RDY_TO_RCV_MASK 0x4
#define CP_STALLED_STAT2__PFP_TO_RCIU_NOT_RDY_TO_RCV__SHIFT 0x2
#define CP_STALLED_STAT2__PFP_TO_VGT_WRITES_PENDING_MASK 0x10
#define CP_STALLED_STAT2__PFP_TO_VGT_WRITES_PENDING__SHIFT 0x4
#define CP_STALLED_STAT2__PFP_RCIU_READ_PENDING_MASK 0x20
#define CP_STALLED_STAT2__PFP_RCIU_READ_PENDING__SHIFT 0x5
#define CP_STALLED_STAT2__PFP_WAITING_ON_BUFFER_DATA_MASK 0x100
#define CP_STALLED_STAT2__PFP_WAITING_ON_BUFFER_DATA__SHIFT 0x8
#define CP_STALLED_STAT2__ME_WAIT_ON_CE_COUNTER_MASK 0x200
#define CP_STALLED_STAT2__ME_WAIT_ON_CE_COUNTER__SHIFT 0x9
#define CP_STALLED_STAT2__ME_WAIT_ON_AVAIL_BUFFER_MASK 0x400
#define CP_STALLED_STAT2__ME_WAIT_ON_AVAIL_BUFFER__SHIFT 0xa
#define CP_STALLED_STAT2__GFX_CNTX_NOT_AVAIL_TO_ME_MASK 0x800
#define CP_STALLED_STAT2__GFX_CNTX_NOT_AVAIL_TO_ME__SHIFT 0xb
#define CP_STALLED_STAT2__ME_RCIU_NOT_RDY_TO_RCV_MASK 0x1000
#define CP_STALLED_STAT2__ME_RCIU_NOT_RDY_TO_RCV__SHIFT 0xc
#define CP_STALLED_STAT2__ME_TO_CONST_NOT_RDY_TO_RCV_MASK 0x2000
#define CP_STALLED_STAT2__ME_TO_CONST_NOT_RDY_TO_RCV__SHIFT 0xd
#define CP_STALLED_STAT2__ME_WAITING_DATA_FROM_PFP_MASK 0x4000
#define CP_STALLED_STAT2__ME_WAITING_DATA_FROM_PFP__SHIFT 0xe
#define CP_STALLED_STAT2__ME_WAITING_ON_PARTIAL_FLUSH_MASK 0x8000
#define CP_STALLED_STAT2__ME_WAITING_ON_PARTIAL_FLUSH__SHIFT 0xf
#define CP_STALLED_STAT2__MEQ_TO_ME_NOT_RDY_TO_RCV_MASK 0x10000
#define CP_STALLED_STAT2__MEQ_TO_ME_NOT_RDY_TO_RCV__SHIFT 0x10
#define CP_STALLED_STAT2__STQ_TO_ME_NOT_RDY_TO_RCV_MASK 0x20000
#define CP_STALLED_STAT2__STQ_TO_ME_NOT_RDY_TO_RCV__SHIFT 0x11
#define CP_STALLED_STAT2__ME_WAITING_DATA_FROM_STQ_MASK 0x40000
#define CP_STALLED_STAT2__ME_WAITING_DATA_FROM_STQ__SHIFT 0x12
#define CP_STALLED_STAT2__PFP_STALLED_ON_TC_WR_CONFIRM_MASK 0x80000
#define CP_STALLED_STAT2__PFP_STALLED_ON_TC_WR_CONFIRM__SHIFT 0x13
#define CP_STALLED_STAT2__PFP_STALLED_ON_ATOMIC_RTN_DATA_MASK 0x100000
#define CP_STALLED_STAT2__PFP_STALLED_ON_ATOMIC_RTN_DATA__SHIFT 0x14
#define CP_STALLED_STAT2__EOPD_FIFO_NEEDS_SC_EOP_DONE_MASK 0x200000
#define CP_STALLED_STAT2__EOPD_FIFO_NEEDS_SC_EOP_DONE__SHIFT 0x15
#define CP_STALLED_STAT2__EOPD_FIFO_NEEDS_WR_CONFIRM_MASK 0x400000
#define CP_STALLED_STAT2__EOPD_FIFO_NEEDS_WR_CONFIRM__SHIFT 0x16
#define CP_STALLED_STAT2__STRMO_WR_OF_PRIM_DATA_PENDING_MASK 0x800000
#define CP_STALLED_STAT2__STRMO_WR_OF_PRIM_DATA_PENDING__SHIFT 0x17
#define CP_STALLED_STAT2__PIPE_STATS_WR_DATA_PENDING_MASK 0x1000000
#define CP_STALLED_STAT2__PIPE_STATS_WR_DATA_PENDING__SHIFT 0x18
#define CP_STALLED_STAT2__APPEND_RDY_WAIT_ON_CS_DONE_MASK 0x2000000
#define CP_STALLED_STAT2__APPEND_RDY_WAIT_ON_CS_DONE__SHIFT 0x19
#define CP_STALLED_STAT2__APPEND_RDY_WAIT_ON_PS_DONE_MASK 0x4000000
#define CP_STALLED_STAT2__APPEND_RDY_WAIT_ON_PS_DONE__SHIFT 0x1a
#define CP_STALLED_STAT2__APPEND_WAIT_ON_WR_CONFIRM_MASK 0x8000000
#define CP_STALLED_STAT2__APPEND_WAIT_ON_WR_CONFIRM__SHIFT 0x1b
#define CP_STALLED_STAT2__APPEND_ACTIVE_PARTITION_MASK 0x10000000
#define CP_STALLED_STAT2__APPEND_ACTIVE_PARTITION__SHIFT 0x1c
#define CP_STALLED_STAT2__APPEND_WAITING_TO_SEND_MEMWRITE_MASK 0x20000000
#define CP_STALLED_STAT2__APPEND_WAITING_TO_SEND_MEMWRITE__SHIFT 0x1d
#define CP_STALLED_STAT2__SURF_SYNC_NEEDS_IDLE_CNTXS_MASK 0x40000000
#define CP_STALLED_STAT2__SURF_SYNC_NEEDS_IDLE_CNTXS__SHIFT 0x1e
#define CP_STALLED_STAT2__SURF_SYNC_NEEDS_ALL_CLEAN_MASK 0x80000000
#define CP_STALLED_STAT2__SURF_SYNC_NEEDS_ALL_CLEAN__SHIFT 0x1f
#define CP_STALLED_STAT3__CE_TO_CSF_NOT_RDY_TO_RCV_MASK 0x1
#define CP_STALLED_STAT3__CE_TO_CSF_NOT_RDY_TO_RCV__SHIFT 0x0
#define CP_STALLED_STAT3__CE_TO_RAM_INIT_FETCHER_NOT_RDY_TO_RCV_MASK 0x2
#define CP_STALLED_STAT3__CE_TO_RAM_INIT_FETCHER_NOT_RDY_TO_RCV__SHIFT 0x1
#define CP_STALLED_STAT3__CE_WAITING_ON_DATA_FROM_RAM_INIT_FETCHER_MASK 0x4
#define CP_STALLED_STAT3__CE_WAITING_ON_DATA_FROM_RAM_INIT_FETCHER__SHIFT 0x2
#define CP_STALLED_STAT3__CE_TO_RAM_INIT_NOT_RDY_MASK 0x8
#define CP_STALLED_STAT3__CE_TO_RAM_INIT_NOT_RDY__SHIFT 0x3
#define CP_STALLED_STAT3__CE_TO_RAM_DUMP_NOT_RDY_MASK 0x10
#define CP_STALLED_STAT3__CE_TO_RAM_DUMP_NOT_RDY__SHIFT 0x4
#define CP_STALLED_STAT3__CE_TO_RAM_WRITE_NOT_RDY_MASK 0x20
#define CP_STALLED_STAT3__CE_TO_RAM_WRITE_NOT_RDY__SHIFT 0x5
#define CP_STALLED_STAT3__CE_TO_INC_FIFO_NOT_RDY_TO_RCV_MASK 0x40
#define CP_STALLED_STAT3__CE_TO_INC_FIFO_NOT_RDY_TO_RCV__SHIFT 0x6
#define CP_STALLED_STAT3__CE_TO_WR_FIFO_NOT_RDY_TO_RCV_MASK 0x80
#define CP_STALLED_STAT3__CE_TO_WR_FIFO_NOT_RDY_TO_RCV__SHIFT 0x7
#define CP_STALLED_STAT3__CE_WAITING_ON_BUFFER_DATA_MASK 0x400
#define CP_STALLED_STAT3__CE_WAITING_ON_BUFFER_DATA__SHIFT 0xa
#define CP_STALLED_STAT3__CE_WAITING_ON_CE_BUFFER_FLAG_MASK 0x800
#define CP_STALLED_STAT3__CE_WAITING_ON_CE_BUFFER_FLAG__SHIFT 0xb
#define CP_STALLED_STAT3__CE_WAITING_ON_DE_COUNTER_MASK 0x1000
#define CP_STALLED_STAT3__CE_WAITING_ON_DE_COUNTER__SHIFT 0xc
#define CP_STALLED_STAT3__CE_WAITING_ON_DE_COUNTER_UNDERFLOW_MASK 0x2000
#define CP_STALLED_STAT3__CE_WAITING_ON_DE_COUNTER_UNDERFLOW__SHIFT 0xd
#define CP_STALLED_STAT3__TCIU_WAITING_ON_FREE_MASK 0x4000
#define CP_STALLED_STAT3__TCIU_WAITING_ON_FREE__SHIFT 0xe
#define CP_STALLED_STAT3__TCIU_WAITING_ON_TAGS_MASK 0x8000
#define CP_STALLED_STAT3__TCIU_WAITING_ON_TAGS__SHIFT 0xf
#define CP_STALLED_STAT3__CE_STALLED_ON_TC_WR_CONFIRM_MASK 0x10000
#define CP_STALLED_STAT3__CE_STALLED_ON_TC_WR_CONFIRM__SHIFT 0x10
#define CP_STALLED_STAT3__CE_STALLED_ON_ATOMIC_RTN_DATA_MASK 0x20000
#define CP_STALLED_STAT3__CE_STALLED_ON_ATOMIC_RTN_DATA__SHIFT 0x11
#define CP_STALLED_STAT3__ATCL2IU_WAITING_ON_FREE_MASK 0x40000
#define CP_STALLED_STAT3__ATCL2IU_WAITING_ON_FREE__SHIFT 0x12
#define CP_STALLED_STAT3__ATCL2IU_WAITING_ON_TAGS_MASK 0x80000
#define CP_STALLED_STAT3__ATCL2IU_WAITING_ON_TAGS__SHIFT 0x13
#define CP_STALLED_STAT3__ATCL1_WAITING_ON_TRANS_MASK 0x100000
#define CP_STALLED_STAT3__ATCL1_WAITING_ON_TRANS__SHIFT 0x14
#define CP_BUSY_STAT__REG_BUS_FIFO_BUSY_MASK 0x1
#define CP_BUSY_STAT__REG_BUS_FIFO_BUSY__SHIFT 0x0
#define CP_BUSY_STAT__COHER_CNT_NEQ_ZERO_MASK 0x40
#define CP_BUSY_STAT__COHER_CNT_NEQ_ZERO__SHIFT 0x6
#define CP_BUSY_STAT__PFP_PARSING_PACKETS_MASK 0x80
#define CP_BUSY_STAT__PFP_PARSING_PACKETS__SHIFT 0x7
#define CP_BUSY_STAT__ME_PARSING_PACKETS_MASK 0x100
#define CP_BUSY_STAT__ME_PARSING_PACKETS__SHIFT 0x8
#define CP_BUSY_STAT__RCIU_PFP_BUSY_MASK 0x200
#define CP_BUSY_STAT__RCIU_PFP_BUSY__SHIFT 0x9
#define CP_BUSY_STAT__RCIU_ME_BUSY_MASK 0x400
#define CP_BUSY_STAT__RCIU_ME_BUSY__SHIFT 0xa
#define CP_BUSY_STAT__SEM_CMDFIFO_NOT_EMPTY_MASK 0x1000
#define CP_BUSY_STAT__SEM_CMDFIFO_NOT_EMPTY__SHIFT 0xc
#define CP_BUSY_STAT__SEM_FAILED_AND_HOLDING_MASK 0x2000
#define CP_BUSY_STAT__SEM_FAILED_AND_HOLDING__SHIFT 0xd
#define CP_BUSY_STAT__SEM_POLLING_FOR_PASS_MASK 0x4000
#define CP_BUSY_STAT__SEM_POLLING_FOR_PASS__SHIFT 0xe
#define CP_BUSY_STAT__GFX_CONTEXT_BUSY_MASK 0x8000
#define CP_BUSY_STAT__GFX_CONTEXT_BUSY__SHIFT 0xf
#define CP_BUSY_STAT__ME_PARSER_BUSY_MASK 0x20000
#define CP_BUSY_STAT__ME_PARSER_BUSY__SHIFT 0x11
#define CP_BUSY_STAT__EOP_DONE_BUSY_MASK 0x40000
#define CP_BUSY_STAT__EOP_DONE_BUSY__SHIFT 0x12
#define CP_BUSY_STAT__STRM_OUT_BUSY_MASK 0x80000
#define CP_BUSY_STAT__STRM_OUT_BUSY__SHIFT 0x13
#define CP_BUSY_STAT__PIPE_STATS_BUSY_MASK 0x100000
#define CP_BUSY_STAT__PIPE_STATS_BUSY__SHIFT 0x14
#define CP_BUSY_STAT__RCIU_CE_BUSY_MASK 0x200000
#define CP_BUSY_STAT__RCIU_CE_BUSY__SHIFT 0x15
#define CP_BUSY_STAT__CE_PARSING_PACKETS_MASK 0x400000
#define CP_BUSY_STAT__CE_PARSING_PACKETS__SHIFT 0x16
#define CP_STAT__ROQ_RING_BUSY_MASK 0x200
#define CP_STAT__ROQ_RING_BUSY__SHIFT 0x9
#define CP_STAT__ROQ_INDIRECT1_BUSY_MASK 0x400
#define CP_STAT__ROQ_INDIRECT1_BUSY__SHIFT 0xa
#define CP_STAT__ROQ_INDIRECT2_BUSY_MASK 0x800
#define CP_STAT__ROQ_INDIRECT2_BUSY__SHIFT 0xb
#define CP_STAT__ROQ_STATE_BUSY_MASK 0x1000
#define CP_STAT__ROQ_STATE_BUSY__SHIFT 0xc
#define CP_STAT__DC_BUSY_MASK 0x2000
#define CP_STAT__DC_BUSY__SHIFT 0xd
#define CP_STAT__ATCL2IU_BUSY_MASK 0x4000
#define CP_STAT__ATCL2IU_BUSY__SHIFT 0xe
#define CP_STAT__PFP_BUSY_MASK 0x8000
#define CP_STAT__PFP_BUSY__SHIFT 0xf
#define CP_STAT__MEQ_BUSY_MASK 0x10000
#define CP_STAT__MEQ_BUSY__SHIFT 0x10
#define CP_STAT__ME_BUSY_MASK 0x20000
#define CP_STAT__ME_BUSY__SHIFT 0x11
#define CP_STAT__QUERY_BUSY_MASK 0x40000
#define CP_STAT__QUERY_BUSY__SHIFT 0x12
#define CP_STAT__SEMAPHORE_BUSY_MASK 0x80000
#define CP_STAT__SEMAPHORE_BUSY__SHIFT 0x13
#define CP_STAT__INTERRUPT_BUSY_MASK 0x100000
#define CP_STAT__INTERRUPT_BUSY__SHIFT 0x14
#define CP_STAT__SURFACE_SYNC_BUSY_MASK 0x200000
#define CP_STAT__SURFACE_SYNC_BUSY__SHIFT 0x15
#define CP_STAT__DMA_BUSY_MASK 0x400000
#define CP_STAT__DMA_BUSY__SHIFT 0x16
#define CP_STAT__RCIU_BUSY_MASK 0x800000
#define CP_STAT__RCIU_BUSY__SHIFT 0x17
#define CP_STAT__SCRATCH_RAM_BUSY_MASK 0x1000000
#define CP_STAT__SCRATCH_RAM_BUSY__SHIFT 0x18
#define CP_STAT__CPC_CPG_BUSY_MASK 0x2000000
#define CP_STAT__CPC_CPG_BUSY__SHIFT 0x19
#define CP_STAT__CE_BUSY_MASK 0x4000000
#define CP_STAT__CE_BUSY__SHIFT 0x1a
#define CP_STAT__TCIU_BUSY_MASK 0x8000000
#define CP_STAT__TCIU_BUSY__SHIFT 0x1b
#define CP_STAT__ROQ_CE_RING_BUSY_MASK 0x10000000
#define CP_STAT__ROQ_CE_RING_BUSY__SHIFT 0x1c
#define CP_STAT__ROQ_CE_INDIRECT1_BUSY_MASK 0x20000000
#define CP_STAT__ROQ_CE_INDIRECT1_BUSY__SHIFT 0x1d
#define CP_STAT__ROQ_CE_INDIRECT2_BUSY_MASK 0x40000000
#define CP_STAT__ROQ_CE_INDIRECT2_BUSY__SHIFT 0x1e
#define CP_STAT__CP_BUSY_MASK 0x80000000
#define CP_STAT__CP_BUSY__SHIFT 0x1f
#define CP_ME_HEADER_DUMP__ME_HEADER_DUMP_MASK 0xffffffff
#define CP_ME_HEADER_DUMP__ME_HEADER_DUMP__SHIFT 0x0
#define CP_PFP_HEADER_DUMP__PFP_HEADER_DUMP_MASK 0xffffffff
#define CP_PFP_HEADER_DUMP__PFP_HEADER_DUMP__SHIFT 0x0
#define CP_GRBM_FREE_COUNT__FREE_COUNT_MASK 0x3f
#define CP_GRBM_FREE_COUNT__FREE_COUNT__SHIFT 0x0
#define CP_GRBM_FREE_COUNT__FREE_COUNT_GDS_MASK 0x3f00
#define CP_GRBM_FREE_COUNT__FREE_COUNT_GDS__SHIFT 0x8
#define CP_GRBM_FREE_COUNT__FREE_COUNT_PFP_MASK 0x3f0000
#define CP_GRBM_FREE_COUNT__FREE_COUNT_PFP__SHIFT 0x10
#define CP_CE_HEADER_DUMP__CE_HEADER_DUMP_MASK 0xffffffff
#define CP_CE_HEADER_DUMP__CE_HEADER_DUMP__SHIFT 0x0
#define CP_CSF_STAT__BUFFER_SLOTS_ALLOCATED_MASK 0xf
#define CP_CSF_STAT__BUFFER_SLOTS_ALLOCATED__SHIFT 0x0
#define CP_CSF_STAT__BUFFER_REQUEST_COUNT_MASK 0x1ff00
#define CP_CSF_STAT__BUFFER_REQUEST_COUNT__SHIFT 0x8
#define CP_CSF_CNTL__FETCH_BUFFER_DEPTH_MASK 0xf
#define CP_CSF_CNTL__FETCH_BUFFER_DEPTH__SHIFT 0x0
#define CP_ME_CNTL__CE_INVALIDATE_ICACHE_MASK 0x10
#define CP_ME_CNTL__CE_INVALIDATE_ICACHE__SHIFT 0x4
#define CP_ME_CNTL__PFP_INVALIDATE_ICACHE_MASK 0x40
#define CP_ME_CNTL__PFP_INVALIDATE_ICACHE__SHIFT 0x6
#define CP_ME_CNTL__ME_INVALIDATE_ICACHE_MASK 0x100
#define CP_ME_CNTL__ME_INVALIDATE_ICACHE__SHIFT 0x8
#define CP_ME_CNTL__CE_PIPE0_RESET_MASK 0x10000
#define CP_ME_CNTL__CE_PIPE0_RESET__SHIFT 0x10
#define CP_ME_CNTL__PFP_PIPE0_RESET_MASK 0x40000
#define CP_ME_CNTL__PFP_PIPE0_RESET__SHIFT 0x12
#define CP_ME_CNTL__ME_PIPE0_RESET_MASK 0x100000
#define CP_ME_CNTL__ME_PIPE0_RESET__SHIFT 0x14
#define CP_ME_CNTL__CE_HALT_MASK 0x1000000
#define CP_ME_CNTL__CE_HALT__SHIFT 0x18
#define CP_ME_CNTL__CE_STEP_MASK 0x2000000
#define CP_ME_CNTL__CE_STEP__SHIFT 0x19
#define CP_ME_CNTL__PFP_HALT_MASK 0x4000000
#define CP_ME_CNTL__PFP_HALT__SHIFT 0x1a
#define CP_ME_CNTL__PFP_STEP_MASK 0x8000000
#define CP_ME_CNTL__PFP_STEP__SHIFT 0x1b
#define CP_ME_CNTL__ME_HALT_MASK 0x10000000
#define CP_ME_CNTL__ME_HALT__SHIFT 0x1c
#define CP_ME_CNTL__ME_STEP_MASK 0x20000000
#define CP_ME_CNTL__ME_STEP__SHIFT 0x1d
#define CP_CNTX_STAT__ACTIVE_HP3D_CONTEXTS_MASK 0xff
#define CP_CNTX_STAT__ACTIVE_HP3D_CONTEXTS__SHIFT 0x0
#define CP_CNTX_STAT__CURRENT_HP3D_CONTEXT_MASK 0x700
#define CP_CNTX_STAT__CURRENT_HP3D_CONTEXT__SHIFT 0x8
#define CP_CNTX_STAT__ACTIVE_GFX_CONTEXTS_MASK 0xff00000
#define CP_CNTX_STAT__ACTIVE_GFX_CONTEXTS__SHIFT 0x14
#define CP_CNTX_STAT__CURRENT_GFX_CONTEXT_MASK 0x70000000
#define CP_CNTX_STAT__CURRENT_GFX_CONTEXT__SHIFT 0x1c
#define CP_ME_PREEMPTION__OBSOLETE_MASK 0x1
#define CP_ME_PREEMPTION__OBSOLETE__SHIFT 0x0
#define CP_RB0_RPTR__RB_RPTR_MASK 0xfffff
#define CP_RB0_RPTR__RB_RPTR__SHIFT 0x0
#define CP_RB_RPTR__RB_RPTR_MASK 0xfffff
#define CP_RB_RPTR__RB_RPTR__SHIFT 0x0
#define CP_RB1_RPTR__RB_RPTR_MASK 0xfffff
#define CP_RB1_RPTR__RB_RPTR__SHIFT 0x0
#define CP_RB2_RPTR__RB_RPTR_MASK 0xfffff
#define CP_RB2_RPTR__RB_RPTR__SHIFT 0x0
#define CP_RB_WPTR_DELAY__PRE_WRITE_TIMER_MASK 0xfffffff
#define CP_RB_WPTR_DELAY__PRE_WRITE_TIMER__SHIFT 0x0
#define CP_RB_WPTR_DELAY__PRE_WRITE_LIMIT_MASK 0xf0000000
#define CP_RB_WPTR_DELAY__PRE_WRITE_LIMIT__SHIFT 0x1c
#define CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY_MASK 0xffff
#define CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT 0x0
#define CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xffff0000
#define CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10
#define CP_CE_INIT_BASE_LO__INIT_BASE_LO_MASK 0xffffffe0
#define CP_CE_INIT_BASE_LO__INIT_BASE_LO__SHIFT 0x5
#define CP_CE_INIT_BASE_HI__INIT_BASE_HI_MASK 0xffff
#define CP_CE_INIT_BASE_HI__INIT_BASE_HI__SHIFT 0x0
#define CP_CE_INIT_BUFSZ__INIT_BUFSZ_MASK 0xfff
#define CP_CE_INIT_BUFSZ__INIT_BUFSZ__SHIFT 0x0
#define CP_CE_IB1_BASE_LO__IB1_BASE_LO_MASK 0xfffffffc
#define CP_CE_IB1_BASE_LO__IB1_BASE_LO__SHIFT 0x2
#define CP_CE_IB1_BASE_HI__IB1_BASE_HI_MASK 0xffff
#define CP_CE_IB1_BASE_HI__IB1_BASE_HI__SHIFT 0x0
#define CP_CE_IB1_BUFSZ__IB1_BUFSZ_MASK 0xfffff
#define CP_CE_IB1_BUFSZ__IB1_BUFSZ__SHIFT 0x0
#define CP_CE_IB2_BASE_LO__IB2_BASE_LO_MASK 0xfffffffc
#define CP_CE_IB2_BASE_LO__IB2_BASE_LO__SHIFT 0x2
#define CP_CE_IB2_BASE_HI__IB2_BASE_HI_MASK 0xffff
#define CP_CE_IB2_BASE_HI__IB2_BASE_HI__SHIFT 0x0
#define CP_CE_IB2_BUFSZ__IB2_BUFSZ_MASK 0xfffff
#define CP_CE_IB2_BUFSZ__IB2_BUFSZ__SHIFT 0x0
#define CP_IB1_BASE_LO__IB1_BASE_LO_MASK 0xfffffffc
#define CP_IB1_BASE_LO__IB1_BASE_LO__SHIFT 0x2
#define CP_IB1_BASE_HI__IB1_BASE_HI_MASK 0xffff
#define CP_IB1_BASE_HI__IB1_BASE_HI__SHIFT 0x0
#define CP_IB1_BUFSZ__IB1_BUFSZ_MASK 0xfffff
#define CP_IB1_BUFSZ__IB1_BUFSZ__SHIFT 0x0
#define CP_IB2_BASE_LO__IB2_BASE_LO_MASK 0xfffffffc
#define CP_IB2_BASE_LO__IB2_BASE_LO__SHIFT 0x2
#define CP_IB2_BASE_HI__IB2_BASE_HI_MASK 0xffff
#define CP_IB2_BASE_HI__IB2_BASE_HI__SHIFT 0x0
#define CP_IB2_BUFSZ__IB2_BUFSZ_MASK 0xfffff
#define CP_IB2_BUFSZ__IB2_BUFSZ__SHIFT 0x0
#define CP_ST_BASE_LO__ST_BASE_LO_MASK 0xfffffffc
#define CP_ST_BASE_LO__ST_BASE_LO__SHIFT 0x2
#define CP_ST_BASE_HI__ST_BASE_HI_MASK 0xffff
#define CP_ST_BASE_HI__ST_BASE_HI__SHIFT 0x0
#define CP_ST_BUFSZ__ST_BUFSZ_MASK 0xfffff
#define CP_ST_BUFSZ__ST_BUFSZ__SHIFT 0x0
#define CP_ROQ_THRESHOLDS__IB1_START_MASK 0xff
#define CP_ROQ_THRESHOLDS__IB1_START__SHIFT 0x0
#define CP_ROQ_THRESHOLDS__IB2_START_MASK 0xff00
#define CP_ROQ_THRESHOLDS__IB2_START__SHIFT 0x8
#define CP_MEQ_STQ_THRESHOLD__STQ_START_MASK 0xff
#define CP_MEQ_STQ_THRESHOLD__STQ_START__SHIFT 0x0
#define CP_ROQ1_THRESHOLDS__RB1_START_MASK 0xff
#define CP_ROQ1_THRESHOLDS__RB1_START__SHIFT 0x0
#define CP_ROQ1_THRESHOLDS__RB2_START_MASK 0xff00
#define CP_ROQ1_THRESHOLDS__RB2_START__SHIFT 0x8
#define CP_ROQ1_THRESHOLDS__R0_IB1_START_MASK 0xff0000
#define CP_ROQ1_THRESHOLDS__R0_IB1_START__SHIFT 0x10
#define CP_ROQ1_THRESHOLDS__R1_IB1_START_MASK 0xff000000
#define CP_ROQ1_THRESHOLDS__R1_IB1_START__SHIFT 0x18
#define CP_ROQ2_THRESHOLDS__R2_IB1_START_MASK 0xff
#define CP_ROQ2_THRESHOLDS__R2_IB1_START__SHIFT 0x0
#define CP_ROQ2_THRESHOLDS__R0_IB2_START_MASK 0xff00
#define CP_ROQ2_THRESHOLDS__R0_IB2_START__SHIFT 0x8
#define CP_ROQ2_THRESHOLDS__R1_IB2_START_MASK 0xff0000
#define CP_ROQ2_THRESHOLDS__R1_IB2_START__SHIFT 0x10
#define CP_ROQ2_THRESHOLDS__R2_IB2_START_MASK 0xff000000
#define CP_ROQ2_THRESHOLDS__R2_IB2_START__SHIFT 0x18
#define CP_STQ_THRESHOLDS__STQ0_START_MASK 0xff
#define CP_STQ_THRESHOLDS__STQ0_START__SHIFT 0x0
#define CP_STQ_THRESHOLDS__STQ1_START_MASK 0xff00
#define CP_STQ_THRESHOLDS__STQ1_START__SHIFT 0x8
#define CP_STQ_THRESHOLDS__STQ2_START_MASK 0xff0000
#define CP_STQ_THRESHOLDS__STQ2_START__SHIFT 0x10
#define CP_QUEUE_THRESHOLDS__ROQ_IB1_START_MASK 0x3f
#define CP_QUEUE_THRESHOLDS__ROQ_IB1_START__SHIFT 0x0
#define CP_QUEUE_THRESHOLDS__ROQ_IB2_START_MASK 0x3f00
#define CP_QUEUE_THRESHOLDS__ROQ_IB2_START__SHIFT 0x8
#define CP_MEQ_THRESHOLDS__MEQ1_START_MASK 0xff
#define CP_MEQ_THRESHOLDS__MEQ1_START__SHIFT 0x0
#define CP_MEQ_THRESHOLDS__MEQ2_START_MASK 0xff00
#define CP_MEQ_THRESHOLDS__MEQ2_START__SHIFT 0x8
#define CP_ROQ_AVAIL__ROQ_CNT_RING_MASK 0x7ff
#define CP_ROQ_AVAIL__ROQ_CNT_RING__SHIFT 0x0
#define CP_ROQ_AVAIL__ROQ_CNT_IB1_MASK 0x7ff0000
#define CP_ROQ_AVAIL__ROQ_CNT_IB1__SHIFT 0x10
#define CP_STQ_AVAIL__STQ_CNT_MASK 0x1ff
#define CP_STQ_AVAIL__STQ_CNT__SHIFT 0x0
#define CP_ROQ2_AVAIL__ROQ_CNT_IB2_MASK 0x7ff
#define CP_ROQ2_AVAIL__ROQ_CNT_IB2__SHIFT 0x0
#define CP_MEQ_AVAIL__MEQ_CNT_MASK 0x3ff
#define CP_MEQ_AVAIL__MEQ_CNT__SHIFT 0x0
#define CP_CMD_INDEX__CMD_INDEX_MASK 0x7ff
#define CP_CMD_INDEX__CMD_INDEX__SHIFT 0x0
#define CP_CMD_INDEX__CMD_ME_SEL_MASK 0x3000
#define CP_CMD_INDEX__CMD_ME_SEL__SHIFT 0xc
#define CP_CMD_INDEX__CMD_QUEUE_SEL_MASK 0x70000
#define CP_CMD_INDEX__CMD_QUEUE_SEL__SHIFT 0x10
#define CP_CMD_DATA__CMD_DATA_MASK 0xffffffff
#define CP_CMD_DATA__CMD_DATA__SHIFT 0x0
#define CP_ROQ_RB_STAT__ROQ_RPTR_PRIMARY_MASK 0x3ff
#define CP_ROQ_RB_STAT__ROQ_RPTR_PRIMARY__SHIFT 0x0
#define CP_ROQ_RB_STAT__ROQ_WPTR_PRIMARY_MASK 0x3ff0000
#define CP_ROQ_RB_STAT__ROQ_WPTR_PRIMARY__SHIFT 0x10
#define CP_ROQ_IB1_STAT__ROQ_RPTR_INDIRECT1_MASK 0x3ff
#define CP_ROQ_IB1_STAT__ROQ_RPTR_INDIRECT1__SHIFT 0x0
#define CP_ROQ_IB1_STAT__ROQ_WPTR_INDIRECT1_MASK 0x3ff0000
#define CP_ROQ_IB1_STAT__ROQ_WPTR_INDIRECT1__SHIFT 0x10
#define CP_ROQ_IB2_STAT__ROQ_RPTR_INDIRECT2_MASK 0x3ff
#define CP_ROQ_IB2_STAT__ROQ_RPTR_INDIRECT2__SHIFT 0x0
#define CP_ROQ_IB2_STAT__ROQ_WPTR_INDIRECT2_MASK 0x3ff0000
#define CP_ROQ_IB2_STAT__ROQ_WPTR_INDIRECT2__SHIFT 0x10
#define CP_STQ_STAT__STQ_RPTR_MASK 0x3ff
#define CP_STQ_STAT__STQ_RPTR__SHIFT 0x0
#define CP_STQ_WR_STAT__STQ_WPTR_MASK 0x3ff
#define CP_STQ_WR_STAT__STQ_WPTR__SHIFT 0x0
#define CP_MEQ_STAT__MEQ_RPTR_MASK 0x3ff
#define CP_MEQ_STAT__MEQ_RPTR__SHIFT 0x0
#define CP_MEQ_STAT__MEQ_WPTR_MASK 0x3ff0000
#define CP_MEQ_STAT__MEQ_WPTR__SHIFT 0x10
#define CP_CEQ1_AVAIL__CEQ_CNT_RING_MASK 0x7ff
#define CP_CEQ1_AVAIL__CEQ_CNT_RING__SHIFT 0x0
#define CP_CEQ1_AVAIL__CEQ_CNT_IB1_MASK 0x7ff0000
#define CP_CEQ1_AVAIL__CEQ_CNT_IB1__SHIFT 0x10
#define CP_CEQ2_AVAIL__CEQ_CNT_IB2_MASK 0x7ff
#define CP_CEQ2_AVAIL__CEQ_CNT_IB2__SHIFT 0x0
#define CP_CE_ROQ_RB_STAT__CEQ_RPTR_PRIMARY_MASK 0x3ff
#define CP_CE_ROQ_RB_STAT__CEQ_RPTR_PRIMARY__SHIFT 0x0
#define CP_CE_ROQ_RB_STAT__CEQ_WPTR_PRIMARY_MASK 0x3ff0000
#define CP_CE_ROQ_RB_STAT__CEQ_WPTR_PRIMARY__SHIFT 0x10
#define CP_CE_ROQ_IB1_STAT__CEQ_RPTR_INDIRECT1_MASK 0x3ff
#define CP_CE_ROQ_IB1_STAT__CEQ_RPTR_INDIRECT1__SHIFT 0x0
#define CP_CE_ROQ_IB1_STAT__CEQ_WPTR_INDIRECT1_MASK 0x3ff0000
#define CP_CE_ROQ_IB1_STAT__CEQ_WPTR_INDIRECT1__SHIFT 0x10
#define CP_CE_ROQ_IB2_STAT__CEQ_RPTR_INDIRECT2_MASK 0x3ff
#define CP_CE_ROQ_IB2_STAT__CEQ_RPTR_INDIRECT2__SHIFT 0x0
#define CP_CE_ROQ_IB2_STAT__CEQ_WPTR_INDIRECT2_MASK 0x3ff0000
#define CP_CE_ROQ_IB2_STAT__CEQ_WPTR_INDIRECT2__SHIFT 0x10
#define CP_INT_STAT_DEBUG__CP_VM_DOORBELL_WR_INT_ASSERTED_MASK 0x800
#define CP_INT_STAT_DEBUG__CP_VM_DOORBELL_WR_INT_ASSERTED__SHIFT 0xb
#define CP_INT_STAT_DEBUG__CP_ECC_ERROR_INT_ASSERTED_MASK 0x4000
#define CP_INT_STAT_DEBUG__CP_ECC_ERROR_INT_ASSERTED__SHIFT 0xe
#define CP_INT_STAT_DEBUG__WRM_POLL_TIMEOUT_INT_ASSERTED_MASK 0x20000
#define CP_INT_STAT_DEBUG__WRM_POLL_TIMEOUT_INT_ASSERTED__SHIFT 0x11
#define CP_INT_STAT_DEBUG__CMP_BUSY_INT_ASSERTED_MASK 0x40000
#define CP_INT_STAT_DEBUG__CMP_BUSY_INT_ASSERTED__SHIFT 0x12
#define CP_INT_STAT_DEBUG__CNTX_BUSY_INT_ASSERTED_MASK 0x80000
#define CP_INT_STAT_DEBUG__CNTX_BUSY_INT_ASSERTED__SHIFT 0x13
#define CP_INT_STAT_DEBUG__CNTX_EMPTY_INT_ASSERTED_MASK 0x100000
#define CP_INT_STAT_DEBUG__CNTX_EMPTY_INT_ASSERTED__SHIFT 0x14
#define CP_INT_STAT_DEBUG__GFX_IDLE_INT_ASSERTED_MASK 0x200000
#define CP_INT_STAT_DEBUG__GFX_IDLE_INT_ASSERTED__SHIFT 0x15
#define CP_INT_STAT_DEBUG__PRIV_INSTR_INT_ASSERTED_MASK 0x400000
#define CP_INT_STAT_DEBUG__PRIV_INSTR_INT_ASSERTED__SHIFT 0x16
#define CP_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED_MASK 0x800000
#define CP_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED__SHIFT 0x17
#define CP_INT_STAT_DEBUG__OPCODE_ERROR_INT_ASSERTED_MASK 0x1000000
#define CP_INT_STAT_DEBUG__OPCODE_ERROR_INT_ASSERTED__SHIFT 0x18
#define CP_INT_STAT_DEBUG__TIME_STAMP_INT_ASSERTED_MASK 0x4000000
#define CP_INT_STAT_DEBUG__TIME_STAMP_INT_ASSERTED__SHIFT 0x1a
#define CP_INT_STAT_DEBUG__RESERVED_BIT_ERROR_INT_ASSERTED_MASK 0x8000000
#define CP_INT_STAT_DEBUG__RESERVED_BIT_ERROR_INT_ASSERTED__SHIFT 0x1b
#define CP_INT_STAT_DEBUG__GENERIC2_INT_ASSERTED_MASK 0x20000000
#define CP_INT_STAT_DEBUG__GENERIC2_INT_ASSERTED__SHIFT 0x1d
#define CP_INT_STAT_DEBUG__GENERIC1_INT_ASSERTED_MASK 0x40000000
#define CP_INT_STAT_DEBUG__GENERIC1_INT_ASSERTED__SHIFT 0x1e
#define CP_INT_STAT_DEBUG__GENERIC0_INT_ASSERTED_MASK 0x80000000
#define CP_INT_STAT_DEBUG__GENERIC0_INT_ASSERTED__SHIFT 0x1f
#define CP_PERFMON_CNTL__PERFMON_STATE_MASK 0xf
#define CP_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0
#define CP_PERFMON_CNTL__SPM_PERFMON_STATE_MASK 0xf0
#define CP_PERFMON_CNTL__SPM_PERFMON_STATE__SHIFT 0x4
#define CP_PERFMON_CNTL__PERFMON_ENABLE_MODE_MASK 0x300
#define CP_PERFMON_CNTL__PERFMON_ENABLE_MODE__SHIFT 0x8
#define CP_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE_MASK 0x400
#define CP_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE__SHIFT 0xa
#define CP_PERFMON_CNTX_CNTL__PERFMON_ENABLE_MASK 0x80000000
#define CP_PERFMON_CNTX_CNTL__PERFMON_ENABLE__SHIFT 0x1f
#define CP_RINGID__RINGID_MASK 0x3
#define CP_RINGID__RINGID__SHIFT 0x0
#define CP_PIPEID__PIPE_ID_MASK 0x3
#define CP_PIPEID__PIPE_ID__SHIFT 0x0
#define CP_VMID__VMID_MASK 0xf
#define CP_VMID__VMID__SHIFT 0x0
#define CP_HPD_ROQ_OFFSETS__IQ_OFFSET_MASK 0x7
#define CP_HPD_ROQ_OFFSETS__IQ_OFFSET__SHIFT 0x0
#define CP_HPD_ROQ_OFFSETS__PQ_OFFSET_MASK 0x3f00
#define CP_HPD_ROQ_OFFSETS__PQ_OFFSET__SHIFT 0x8
#define CP_HPD_ROQ_OFFSETS__IB_OFFSET_MASK 0x3f0000
#define CP_HPD_ROQ_OFFSETS__IB_OFFSET__SHIFT 0x10
#define CP_HPD_STATUS0__QUEUE_STATE_MASK 0x1f
#define CP_HPD_STATUS0__QUEUE_STATE__SHIFT 0x0
#define CP_HPD_STATUS0__MAPPED_QUEUE_MASK 0xe0
#define CP_HPD_STATUS0__MAPPED_QUEUE__SHIFT 0x5
#define CP_HPD_STATUS0__QUEUE_AVAILABLE_MASK 0xff00
#define CP_HPD_STATUS0__QUEUE_AVAILABLE__SHIFT 0x8
#define CP_MQD_BASE_ADDR__BASE_ADDR_MASK 0xfffffffc
#define CP_MQD_BASE_ADDR__BASE_ADDR__SHIFT 0x2
#define CP_MQD_BASE_ADDR_HI__BASE_ADDR_HI_MASK 0xffff
#define CP_MQD_BASE_ADDR_HI__BASE_ADDR_HI__SHIFT 0x0
#define CP_HQD_ACTIVE__ACTIVE_MASK 0x1
#define CP_HQD_ACTIVE__ACTIVE__SHIFT 0x0
#define CP_HQD_ACTIVE__BUSY_GATE_MASK 0x2
#define CP_HQD_ACTIVE__BUSY_GATE__SHIFT 0x1
#define CP_HQD_VMID__VMID_MASK 0xf
#define CP_HQD_VMID__VMID__SHIFT 0x0
#define CP_HQD_VMID__IB_VMID_MASK 0xf00
#define CP_HQD_VMID__IB_VMID__SHIFT 0x8
#define CP_HQD_VMID__VQID_MASK 0x3ff0000
#define CP_HQD_VMID__VQID__SHIFT 0x10
#define CP_HQD_PERSISTENT_STATE__PRELOAD_REQ_MASK 0x1
#define CP_HQD_PERSISTENT_STATE__PRELOAD_REQ__SHIFT 0x0
#define CP_HQD_PERSISTENT_STATE__PRELOAD_SIZE_MASK 0x3ff00
#define CP_HQD_PERSISTENT_STATE__PRELOAD_SIZE__SHIFT 0x8
#define CP_HQD_PERSISTENT_STATE__RESTORE_ACTIVE_MASK 0x10000000
#define CP_HQD_PERSISTENT_STATE__RESTORE_ACTIVE__SHIFT 0x1c
#define CP_HQD_PERSISTENT_STATE__RELAUNCH_WAVES_MASK 0x20000000
#define CP_HQD_PERSISTENT_STATE__RELAUNCH_WAVES__SHIFT 0x1d
#define CP_HQD_PERSISTENT_STATE__QSWITCH_MODE_MASK 0x40000000
#define CP_HQD_PERSISTENT_STATE__QSWITCH_MODE__SHIFT 0x1e
#define CP_HQD_PERSISTENT_STATE__DISP_ACTIVE_MASK 0x80000000
#define CP_HQD_PERSISTENT_STATE__DISP_ACTIVE__SHIFT 0x1f
#define CP_HQD_PIPE_PRIORITY__PIPE_PRIORITY_MASK 0x3
#define CP_HQD_PIPE_PRIORITY__PIPE_PRIORITY__SHIFT 0x0
#define CP_HQD_QUEUE_PRIORITY__PRIORITY_LEVEL_MASK 0xf
#define CP_HQD_QUEUE_PRIORITY__PRIORITY_LEVEL__SHIFT 0x0
#define CP_HQD_QUANTUM__QUANTUM_EN_MASK 0x1
#define CP_HQD_QUANTUM__QUANTUM_EN__SHIFT 0x0
#define CP_HQD_QUANTUM__QUANTUM_SCALE_MASK 0x10
#define CP_HQD_QUANTUM__QUANTUM_SCALE__SHIFT 0x4
#define CP_HQD_QUANTUM__QUANTUM_DURATION_MASK 0x3f00
#define CP_HQD_QUANTUM__QUANTUM_DURATION__SHIFT 0x8
#define CP_HQD_QUANTUM__QUANTUM_ACTIVE_MASK 0x80000000
#define CP_HQD_QUANTUM__QUANTUM_ACTIVE__SHIFT 0x1f
#define CP_HQD_PQ_BASE__ADDR_MASK 0xffffffff
#define CP_HQD_PQ_BASE__ADDR__SHIFT 0x0
#define CP_HQD_PQ_BASE_HI__ADDR_HI_MASK 0xff
#define CP_HQD_PQ_BASE_HI__ADDR_HI__SHIFT 0x0
#define CP_HQD_PQ_RPTR__CONSUMED_OFFSET_MASK 0xffffffff
#define CP_HQD_PQ_RPTR__CONSUMED_OFFSET__SHIFT 0x0
#define CP_HQD_PQ_RPTR_REPORT_ADDR__RPTR_REPORT_ADDR_MASK 0xfffffffc
#define CP_HQD_PQ_RPTR_REPORT_ADDR__RPTR_REPORT_ADDR__SHIFT 0x2
#define CP_HQD_PQ_RPTR_REPORT_ADDR_HI__RPTR_REPORT_ADDR_HI_MASK 0xffff
#define CP_HQD_PQ_RPTR_REPORT_ADDR_HI__RPTR_REPORT_ADDR_HI__SHIFT 0x0
#define CP_HQD_PQ_WPTR_POLL_ADDR__WPTR_ADDR_MASK 0xfffffffc
#define CP_HQD_PQ_WPTR_POLL_ADDR__WPTR_ADDR__SHIFT 0x2
#define CP_HQD_PQ_WPTR_POLL_ADDR_HI__WPTR_ADDR_HI_MASK 0xffff
#define CP_HQD_PQ_WPTR_POLL_ADDR_HI__WPTR_ADDR_HI__SHIFT 0x0
#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_MODE_MASK 0x1
#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_MODE__SHIFT 0x0
#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_BIF_DROP_MASK 0x2
#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_BIF_DROP__SHIFT 0x1
#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET_MASK 0x7ffffc
#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET__SHIFT 0x2
#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_CARRY_BITS_MASK 0x3800000
#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_CARRY_BITS__SHIFT 0x17
#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_SOURCE_MASK 0x10000000
#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_SOURCE__SHIFT 0x1c
#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_SCHD_HIT_MASK 0x20000000
#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_SCHD_HIT__SHIFT 0x1d
#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_EN_MASK 0x40000000
#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_EN__SHIFT 0x1e
#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_HIT_MASK 0x80000000
#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_HIT__SHIFT 0x1f
#define CP_HQD_PQ_WPTR__OFFSET_MASK 0xffffffff
#define CP_HQD_PQ_WPTR__OFFSET__SHIFT 0x0
#define CP_HQD_PQ_CONTROL__QUEUE_SIZE_MASK 0x3f
#define CP_HQD_PQ_CONTROL__QUEUE_SIZE__SHIFT 0x0
#define CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE_MASK 0x3f00
#define CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE__SHIFT 0x8
#define CP_HQD_PQ_CONTROL__MTYPE_MASK 0x18000
#define CP_HQD_PQ_CONTROL__MTYPE__SHIFT 0xf
#define CP_HQD_PQ_CONTROL__ENDIAN_SWAP_MASK 0x60000
#define CP_HQD_PQ_CONTROL__ENDIAN_SWAP__SHIFT 0x11
#define CP_HQD_PQ_CONTROL__MIN_AVAIL_SIZE_MASK 0x300000
#define CP_HQD_PQ_CONTROL__MIN_AVAIL_SIZE__SHIFT 0x14
#define CP_HQD_PQ_CONTROL__PQ_ATC_MASK 0x800000
#define CP_HQD_PQ_CONTROL__PQ_ATC__SHIFT 0x17
#define CP_HQD_PQ_CONTROL__CACHE_POLICY_MASK 0x1000000
#define CP_HQD_PQ_CONTROL__CACHE_POLICY__SHIFT 0x18
#define CP_HQD_PQ_CONTROL__SLOT_BASED_WPTR_MASK 0x6000000
#define CP_HQD_PQ_CONTROL__SLOT_BASED_WPTR__SHIFT 0x19
#define CP_HQD_PQ_CONTROL__NO_UPDATE_RPTR_MASK 0x8000000
#define CP_HQD_PQ_CONTROL__NO_UPDATE_RPTR__SHIFT 0x1b
#define CP_HQD_PQ_CONTROL__UNORD_DISPATCH_MASK 0x10000000
#define CP_HQD_PQ_CONTROL__UNORD_DISPATCH__SHIFT 0x1c
#define CP_HQD_PQ_CONTROL__ROQ_PQ_IB_FLIP_MASK 0x20000000
#define CP_HQD_PQ_CONTROL__ROQ_PQ_IB_FLIP__SHIFT 0x1d
#define CP_HQD_PQ_CONTROL__PRIV_STATE_MASK 0x40000000
#define CP_HQD_PQ_CONTROL__PRIV_STATE__SHIFT 0x1e
#define CP_HQD_PQ_CONTROL__KMD_QUEUE_MASK 0x80000000
#define CP_HQD_PQ_CONTROL__KMD_QUEUE__SHIFT 0x1f
#define CP_HQD_IB_BASE_ADDR__IB_BASE_ADDR_MASK 0xfffffffc
#define CP_HQD_IB_BASE_ADDR__IB_BASE_ADDR__SHIFT 0x2
#define CP_HQD_IB_BASE_ADDR_HI__IB_BASE_ADDR_HI_MASK 0xffff
#define CP_HQD_IB_BASE_ADDR_HI__IB_BASE_ADDR_HI__SHIFT 0x0
#define CP_HQD_IB_RPTR__CONSUMED_OFFSET_MASK 0xfffff
#define CP_HQD_IB_RPTR__CONSUMED_OFFSET__SHIFT 0x0
#define CP_HQD_IB_CONTROL__IB_SIZE_MASK 0xfffff
#define CP_HQD_IB_CONTROL__IB_SIZE__SHIFT 0x0
#define CP_HQD_IB_CONTROL__MIN_IB_AVAIL_SIZE_MASK 0x300000
#define CP_HQD_IB_CONTROL__MIN_IB_AVAIL_SIZE__SHIFT 0x14
#define CP_HQD_IB_CONTROL__IB_ATC_MASK 0x800000
#define CP_HQD_IB_CONTROL__IB_ATC__SHIFT 0x17
#define CP_HQD_IB_CONTROL__IB_CACHE_POLICY_MASK 0x1000000
#define CP_HQD_IB_CONTROL__IB_CACHE_POLICY__SHIFT 0x18
#define CP_HQD_IB_CONTROL__MTYPE_MASK 0x18000000
#define CP_HQD_IB_CONTROL__MTYPE__SHIFT 0x1b
#define CP_HQD_IB_CONTROL__PROCESSING_IB_MASK 0x80000000
#define CP_HQD_IB_CONTROL__PROCESSING_IB__SHIFT 0x1f
#define CP_HQD_IQ_TIMER__WAIT_TIME_MASK 0xff
#define CP_HQD_IQ_TIMER__WAIT_TIME__SHIFT 0x0
#define CP_HQD_IQ_TIMER__RETRY_TYPE_MASK 0x700
#define CP_HQD_IQ_TIMER__RETRY_TYPE__SHIFT 0x8
#define CP_HQD_IQ_TIMER__IMMEDIATE_EXPIRE_MASK 0x800
#define CP_HQD_IQ_TIMER__IMMEDIATE_EXPIRE__SHIFT 0xb
#define CP_HQD_IQ_TIMER__INTERRUPT_TYPE_MASK 0x3000
#define CP_HQD_IQ_TIMER__INTERRUPT_TYPE__SHIFT 0xc
#define CP_HQD_IQ_TIMER__CLOCK_COUNT_MASK 0xc000
#define CP_HQD_IQ_TIMER__CLOCK_COUNT__SHIFT 0xe
#define CP_HQD_IQ_TIMER__INTERRUPT_SIZE_MASK 0x3f0000
#define CP_HQD_IQ_TIMER__INTERRUPT_SIZE__SHIFT 0x10
#define CP_HQD_IQ_TIMER__QUANTUM_TIMER_MASK 0x400000
#define CP_HQD_IQ_TIMER__QUANTUM_TIMER__SHIFT 0x16
#define CP_HQD_IQ_TIMER__IQ_ATC_MASK 0x800000
#define CP_HQD_IQ_TIMER__IQ_ATC__SHIFT 0x17
#define CP_HQD_IQ_TIMER__CACHE_POLICY_MASK 0x1000000
#define CP_HQD_IQ_TIMER__CACHE_POLICY__SHIFT 0x18
#define CP_HQD_IQ_TIMER__MTYPE_MASK 0x18000000
#define CP_HQD_IQ_TIMER__MTYPE__SHIFT 0x1b
#define CP_HQD_IQ_TIMER__PROCESS_IQ_EN_MASK 0x20000000
#define CP_HQD_IQ_TIMER__PROCESS_IQ_EN__SHIFT 0x1d
#define CP_HQD_IQ_TIMER__PROCESSING_IQ_MASK 0x40000000
#define CP_HQD_IQ_TIMER__PROCESSING_IQ__SHIFT 0x1e
#define CP_HQD_IQ_TIMER__ACTIVE_MASK 0x80000000
#define CP_HQD_IQ_TIMER__ACTIVE__SHIFT 0x1f
#define CP_HQD_IQ_RPTR__OFFSET_MASK 0x3f
#define CP_HQD_IQ_RPTR__OFFSET__SHIFT 0x0
#define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_REQ_MASK 0x7
#define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_REQ__SHIFT 0x0
#define CP_HQD_DEQUEUE_REQUEST__IQ_REQ_PEND_MASK 0x10
#define CP_HQD_DEQUEUE_REQUEST__IQ_REQ_PEND__SHIFT 0x4
#define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_INT_MASK 0x100
#define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_INT__SHIFT 0x8
#define CP_HQD_DEQUEUE_REQUEST__IQ_REQ_PEND_EN_MASK 0x200
#define CP_HQD_DEQUEUE_REQUEST__IQ_REQ_PEND_EN__SHIFT 0x9
#define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_REQ_EN_MASK 0x400
#define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_REQ_EN__SHIFT 0xa
#define CP_HQD_DMA_OFFLOAD__DMA_OFFLOAD_MASK 0x1
#define CP_HQD_DMA_OFFLOAD__DMA_OFFLOAD__SHIFT 0x0
#define CP_HQD_OFFLOAD__DMA_OFFLOAD_MASK 0x1
#define CP_HQD_OFFLOAD__DMA_OFFLOAD__SHIFT 0x0
#define CP_HQD_OFFLOAD__DMA_OFFLOAD_EN_MASK 0x2
#define CP_HQD_OFFLOAD__DMA_OFFLOAD_EN__SHIFT 0x1
#define CP_HQD_OFFLOAD__EOP_OFFLOAD_MASK 0x10
#define CP_HQD_OFFLOAD__EOP_OFFLOAD__SHIFT 0x4
#define CP_HQD_OFFLOAD__EOP_OFFLOAD_EN_MASK 0x20
#define CP_HQD_OFFLOAD__EOP_OFFLOAD_EN__SHIFT 0x5
#define CP_HQD_SEMA_CMD__RETRY_MASK 0x1
#define CP_HQD_SEMA_CMD__RETRY__SHIFT 0x0
#define CP_HQD_SEMA_CMD__RESULT_MASK 0x6
#define CP_HQD_SEMA_CMD__RESULT__SHIFT 0x1
#define CP_HQD_MSG_TYPE__ACTION_MASK 0x7
#define CP_HQD_MSG_TYPE__ACTION__SHIFT 0x0
#define CP_HQD_MSG_TYPE__SAVE_STATE_MASK 0x70
#define CP_HQD_MSG_TYPE__SAVE_STATE__SHIFT 0x4
#define CP_HQD_ATOMIC0_PREOP_LO__ATOMIC0_PREOP_LO_MASK 0xffffffff
#define CP_HQD_ATOMIC0_PREOP_LO__ATOMIC0_PREOP_LO__SHIFT 0x0
#define CP_HQD_ATOMIC0_PREOP_HI__ATOMIC0_PREOP_HI_MASK 0xffffffff
#define CP_HQD_ATOMIC0_PREOP_HI__ATOMIC0_PREOP_HI__SHIFT 0x0
#define CP_HQD_ATOMIC1_PREOP_LO__ATOMIC1_PREOP_LO_MASK 0xffffffff
#define CP_HQD_ATOMIC1_PREOP_LO__ATOMIC1_PREOP_LO__SHIFT 0x0
#define CP_HQD_ATOMIC1_PREOP_HI__ATOMIC1_PREOP_HI_MASK 0xffffffff
#define CP_HQD_ATOMIC1_PREOP_HI__ATOMIC1_PREOP_HI__SHIFT 0x0
#define CP_HQD_HQ_SCHEDULER0__SCHEDULER_MASK 0xffffffff
#define CP_HQD_HQ_SCHEDULER0__SCHEDULER__SHIFT 0x0
#define CP_HQD_HQ_STATUS0__DEQUEUE_STATUS_MASK 0x3
#define CP_HQD_HQ_STATUS0__DEQUEUE_STATUS__SHIFT 0x0
#define CP_HQD_HQ_STATUS0__DEQUEUE_RETRY_CNT_MASK 0xc
#define CP_HQD_HQ_STATUS0__DEQUEUE_RETRY_CNT__SHIFT 0x2
#define CP_HQD_HQ_STATUS0__RSV_6_4_MASK 0x70
#define CP_HQD_HQ_STATUS0__RSV_6_4__SHIFT 0x4
#define CP_HQD_HQ_STATUS0__SCRATCH_RAM_INIT_MASK 0x80
#define CP_HQD_HQ_STATUS0__SCRATCH_RAM_INIT__SHIFT 0x7
#define CP_HQD_HQ_STATUS0__TCL2_DIRTY_MASK 0x100
#define CP_HQD_HQ_STATUS0__TCL2_DIRTY__SHIFT 0x8
#define CP_HQD_HQ_STATUS0__PG_ACTIVATED_MASK 0x200
#define CP_HQD_HQ_STATUS0__PG_ACTIVATED__SHIFT 0x9
#define CP_HQD_HQ_STATUS0__RSVR_31_10_MASK 0xfffffc00
#define CP_HQD_HQ_STATUS0__RSVR_31_10__SHIFT 0xa
#define CP_HQD_HQ_SCHEDULER1__SCHEDULER_MASK 0xffffffff
#define CP_HQD_HQ_SCHEDULER1__SCHEDULER__SHIFT 0x0
#define CP_HQD_HQ_CONTROL0__CONTROL_MASK 0xffffffff
#define CP_HQD_HQ_CONTROL0__CONTROL__SHIFT 0x0
#define CP_MQD_CONTROL__VMID_MASK 0xf
#define CP_MQD_CONTROL__VMID__SHIFT 0x0
#define CP_MQD_CONTROL__PROCESSING_MQD_MASK 0x1000
#define CP_MQD_CONTROL__PROCESSING_MQD__SHIFT 0xc
#define CP_MQD_CONTROL__PROCESSING_MQD_EN_MASK 0x2000
#define CP_MQD_CONTROL__PROCESSING_MQD_EN__SHIFT 0xd
#define CP_MQD_CONTROL__MQD_ATC_MASK 0x800000
#define CP_MQD_CONTROL__MQD_ATC__SHIFT 0x17
#define CP_MQD_CONTROL__CACHE_POLICY_MASK 0x1000000
#define CP_MQD_CONTROL__CACHE_POLICY__SHIFT 0x18
#define CP_MQD_CONTROL__MTYPE_MASK 0x18000000
#define CP_MQD_CONTROL__MTYPE__SHIFT 0x1b
#define CP_HQD_HQ_STATUS1__STATUS_MASK 0xffffffff
#define CP_HQD_HQ_STATUS1__STATUS__SHIFT 0x0
#define CP_HQD_HQ_CONTROL1__CONTROL_MASK 0xffffffff
#define CP_HQD_HQ_CONTROL1__CONTROL__SHIFT 0x0
#define CP_HQD_EOP_BASE_ADDR__BASE_ADDR_MASK 0xffffffff
#define CP_HQD_EOP_BASE_ADDR__BASE_ADDR__SHIFT 0x0
#define CP_HQD_EOP_BASE_ADDR_HI__BASE_ADDR_HI_MASK 0xff
#define CP_HQD_EOP_BASE_ADDR_HI__BASE_ADDR_HI__SHIFT 0x0
#define CP_HQD_EOP_CONTROL__EOP_SIZE_MASK 0x3f
#define CP_HQD_EOP_CONTROL__EOP_SIZE__SHIFT 0x0
#define CP_HQD_EOP_CONTROL__PROCESSING_EOP_MASK 0x100
#define CP_HQD_EOP_CONTROL__PROCESSING_EOP__SHIFT 0x8
#define CP_HQD_EOP_CONTROL__PROCESS_EOP_EN_MASK 0x1000
#define CP_HQD_EOP_CONTROL__PROCESS_EOP_EN__SHIFT 0xc
#define CP_HQD_EOP_CONTROL__PROCESSING_EOPIB_MASK 0x2000
#define CP_HQD_EOP_CONTROL__PROCESSING_EOPIB__SHIFT 0xd
#define CP_HQD_EOP_CONTROL__PROCESS_EOPIB_EN_MASK 0x4000
#define CP_HQD_EOP_CONTROL__PROCESS_EOPIB_EN__SHIFT 0xe
#define CP_HQD_EOP_CONTROL__MTYPE_MASK 0x18000
#define CP_HQD_EOP_CONTROL__MTYPE__SHIFT 0xf
#define CP_HQD_EOP_CONTROL__EOP_ATC_MASK 0x800000
#define CP_HQD_EOP_CONTROL__EOP_ATC__SHIFT 0x17
#define CP_HQD_EOP_CONTROL__CACHE_POLICY_MASK 0x1000000
#define CP_HQD_EOP_CONTROL__CACHE_POLICY__SHIFT 0x18
#define CP_HQD_EOP_CONTROL__SIG_SEM_RESULT_MASK 0x60000000
#define CP_HQD_EOP_CONTROL__SIG_SEM_RESULT__SHIFT 0x1d
#define CP_HQD_EOP_CONTROL__PEND_SIG_SEM_MASK 0x80000000
#define CP_HQD_EOP_CONTROL__PEND_SIG_SEM__SHIFT 0x1f
#define CP_HQD_EOP_RPTR__RPTR_MASK 0x1fff
#define CP_HQD_EOP_RPTR__RPTR__SHIFT 0x0
#define CP_HQD_EOP_RPTR__RPTR_EQ_CSMD_WPTR_MASK 0x40000000
#define CP_HQD_EOP_RPTR__RPTR_EQ_CSMD_WPTR__SHIFT 0x1e
#define CP_HQD_EOP_RPTR__INIT_FETCHER_MASK 0x80000000
#define CP_HQD_EOP_RPTR__INIT_FETCHER__SHIFT 0x1f
#define CP_HQD_EOP_WPTR__WPTR_MASK 0x1fff
#define CP_HQD_EOP_WPTR__WPTR__SHIFT 0x0
#define CP_HQD_EOP_WPTR__EOP_AVAIL_MASK 0x1fff0000
#define CP_HQD_EOP_WPTR__EOP_AVAIL__SHIFT 0x10
#define CP_HQD_EOP_EVENTS__EVENT_COUNT_MASK 0xfff
#define CP_HQD_EOP_EVENTS__EVENT_COUNT__SHIFT 0x0
#define CP_HQD_EOP_EVENTS__CS_PARTIAL_FLUSH_PEND_MASK 0x10000
#define CP_HQD_EOP_EVENTS__CS_PARTIAL_FLUSH_PEND__SHIFT 0x10
#define CP_HQD_CTX_SAVE_BASE_ADDR_LO__ADDR_MASK 0xfffff000
#define CP_HQD_CTX_SAVE_BASE_ADDR_LO__ADDR__SHIFT 0xc
#define CP_HQD_CTX_SAVE_BASE_ADDR_HI__ADDR_HI_MASK 0xffff
#define CP_HQD_CTX_SAVE_BASE_ADDR_HI__ADDR_HI__SHIFT 0x0
#define CP_HQD_CTX_SAVE_CONTROL__ATC_MASK 0x1
#define CP_HQD_CTX_SAVE_CONTROL__ATC__SHIFT 0x0
#define CP_HQD_CTX_SAVE_CONTROL__MTYPE_MASK 0x6
#define CP_HQD_CTX_SAVE_CONTROL__MTYPE__SHIFT 0x1
#define CP_HQD_CTX_SAVE_CONTROL__POLICY_MASK 0x8
#define CP_HQD_CTX_SAVE_CONTROL__POLICY__SHIFT 0x3
#define CP_HQD_CNTL_STACK_OFFSET__OFFSET_MASK 0x7ffc
#define CP_HQD_CNTL_STACK_OFFSET__OFFSET__SHIFT 0x2
#define CP_HQD_CNTL_STACK_SIZE__SIZE_MASK 0x7000
#define CP_HQD_CNTL_STACK_SIZE__SIZE__SHIFT 0xc
#define CP_HQD_WG_STATE_OFFSET__OFFSET_MASK 0x1fffffc
#define CP_HQD_WG_STATE_OFFSET__OFFSET__SHIFT 0x2
#define CP_HQD_CTX_SAVE_SIZE__SIZE_MASK 0x1fff000
#define CP_HQD_CTX_SAVE_SIZE__SIZE__SHIFT 0xc
#define CP_HQD_GDS_RESOURCE_STATE__OA_REQUIRED_MASK 0x1
#define CP_HQD_GDS_RESOURCE_STATE__OA_REQUIRED__SHIFT 0x0
#define CP_HQD_GDS_RESOURCE_STATE__OA_ACQUIRED_MASK 0x2
#define CP_HQD_GDS_RESOURCE_STATE__OA_ACQUIRED__SHIFT 0x1
#define CP_HQD_GDS_RESOURCE_STATE__GWS_SIZE_MASK 0x3f0
#define CP_HQD_GDS_RESOURCE_STATE__GWS_SIZE__SHIFT 0x4
#define CP_HQD_GDS_RESOURCE_STATE__GWS_PNTR_MASK 0x3f000
#define CP_HQD_GDS_RESOURCE_STATE__GWS_PNTR__SHIFT 0xc
#define CP_HQD_ERROR__EDC_ERROR_ID_MASK 0xf
#define CP_HQD_ERROR__EDC_ERROR_ID__SHIFT 0x0
#define CP_HQD_ERROR__SUA_ERROR_MASK 0x10
#define CP_HQD_ERROR__SUA_ERROR__SHIFT 0x4
#define CP_HQD_EOP_WPTR_MEM__WPTR_MASK 0x1fff
#define CP_HQD_EOP_WPTR_MEM__WPTR__SHIFT 0x0
#define CP_HQD_EOP_DONES__DONE_COUNT_MASK 0xffffffff
#define CP_HQD_EOP_DONES__DONE_COUNT__SHIFT 0x0
#define DB_Z_READ_BASE__BASE_256B_MASK 0xffffffff
#define DB_Z_READ_BASE__BASE_256B__SHIFT 0x0
#define DB_STENCIL_READ_BASE__BASE_256B_MASK 0xffffffff
#define DB_STENCIL_READ_BASE__BASE_256B__SHIFT 0x0
#define DB_Z_WRITE_BASE__BASE_256B_MASK 0xffffffff
#define DB_Z_WRITE_BASE__BASE_256B__SHIFT 0x0
#define DB_STENCIL_WRITE_BASE__BASE_256B_MASK 0xffffffff
#define DB_STENCIL_WRITE_BASE__BASE_256B__SHIFT 0x0
#define DB_DEPTH_INFO__ADDR5_SWIZZLE_MASK_MASK 0xf
#define DB_DEPTH_INFO__ADDR5_SWIZZLE_MASK__SHIFT 0x0
#define DB_DEPTH_INFO__ARRAY_MODE_MASK 0xf0
#define DB_DEPTH_INFO__ARRAY_MODE__SHIFT 0x4
#define DB_DEPTH_INFO__PIPE_CONFIG_MASK 0x1f00
#define DB_DEPTH_INFO__PIPE_CONFIG__SHIFT 0x8
#define DB_DEPTH_INFO__BANK_WIDTH_MASK 0x6000
#define DB_DEPTH_INFO__BANK_WIDTH__SHIFT 0xd
#define DB_DEPTH_INFO__BANK_HEIGHT_MASK 0x18000
#define DB_DEPTH_INFO__BANK_HEIGHT__SHIFT 0xf
#define DB_DEPTH_INFO__MACRO_TILE_ASPECT_MASK 0x60000
#define DB_DEPTH_INFO__MACRO_TILE_ASPECT__SHIFT 0x11
#define DB_DEPTH_INFO__NUM_BANKS_MASK 0x180000
#define DB_DEPTH_INFO__NUM_BANKS__SHIFT 0x13
#define DB_Z_INFO__FORMAT_MASK 0x3
#define DB_Z_INFO__FORMAT__SHIFT 0x0
#define DB_Z_INFO__NUM_SAMPLES_MASK 0xc
#define DB_Z_INFO__NUM_SAMPLES__SHIFT 0x2
#define DB_Z_INFO__TILE_SPLIT_MASK 0xe000
#define DB_Z_INFO__TILE_SPLIT__SHIFT 0xd
#define DB_Z_INFO__TILE_MODE_INDEX_MASK 0x700000
#define DB_Z_INFO__TILE_MODE_INDEX__SHIFT 0x14
#define DB_Z_INFO__DECOMPRESS_ON_N_ZPLANES_MASK 0x7800000
#define DB_Z_INFO__DECOMPRESS_ON_N_ZPLANES__SHIFT 0x17
#define DB_Z_INFO__ALLOW_EXPCLEAR_MASK 0x8000000
#define DB_Z_INFO__ALLOW_EXPCLEAR__SHIFT 0x1b
#define DB_Z_INFO__READ_SIZE_MASK 0x10000000
#define DB_Z_INFO__READ_SIZE__SHIFT 0x1c
#define DB_Z_INFO__TILE_SURFACE_ENABLE_MASK 0x20000000
#define DB_Z_INFO__TILE_SURFACE_ENABLE__SHIFT 0x1d
#define DB_Z_INFO__CLEAR_DISALLOWED_MASK 0x40000000
#define DB_Z_INFO__CLEAR_DISALLOWED__SHIFT 0x1e
#define DB_Z_INFO__ZRANGE_PRECISION_MASK 0x80000000
#define DB_Z_INFO__ZRANGE_PRECISION__SHIFT 0x1f
#define DB_STENCIL_INFO__FORMAT_MASK 0x1
#define DB_STENCIL_INFO__FORMAT__SHIFT 0x0
#define DB_STENCIL_INFO__TILE_SPLIT_MASK 0xe000
#define DB_STENCIL_INFO__TILE_SPLIT__SHIFT 0xd
#define DB_STENCIL_INFO__TILE_MODE_INDEX_MASK 0x700000
#define DB_STENCIL_INFO__TILE_MODE_INDEX__SHIFT 0x14
#define DB_STENCIL_INFO__ALLOW_EXPCLEAR_MASK 0x8000000
#define DB_STENCIL_INFO__ALLOW_EXPCLEAR__SHIFT 0x1b
#define DB_STENCIL_INFO__TILE_STENCIL_DISABLE_MASK 0x20000000
#define DB_STENCIL_INFO__TILE_STENCIL_DISABLE__SHIFT 0x1d
#define DB_STENCIL_INFO__CLEAR_DISALLOWED_MASK 0x40000000
#define DB_STENCIL_INFO__CLEAR_DISALLOWED__SHIFT 0x1e
#define DB_DEPTH_SIZE__PITCH_TILE_MAX_MASK 0x7ff
#define DB_DEPTH_SIZE__PITCH_TILE_MAX__SHIFT 0x0
#define DB_DEPTH_SIZE__HEIGHT_TILE_MAX_MASK 0x3ff800
#define DB_DEPTH_SIZE__HEIGHT_TILE_MAX__SHIFT 0xb
#define DB_DEPTH_SLICE__SLICE_TILE_MAX_MASK 0x3fffff
#define DB_DEPTH_SLICE__SLICE_TILE_MAX__SHIFT 0x0
#define DB_DEPTH_VIEW__SLICE_START_MASK 0x7ff
#define DB_DEPTH_VIEW__SLICE_START__SHIFT 0x0
#define DB_DEPTH_VIEW__SLICE_MAX_MASK 0xffe000
#define DB_DEPTH_VIEW__SLICE_MAX__SHIFT 0xd
#define DB_DEPTH_VIEW__Z_READ_ONLY_MASK 0x1000000
#define DB_DEPTH_VIEW__Z_READ_ONLY__SHIFT 0x18
#define DB_DEPTH_VIEW__STENCIL_READ_ONLY_MASK 0x2000000
#define DB_DEPTH_VIEW__STENCIL_READ_ONLY__SHIFT 0x19
#define DB_RENDER_CONTROL__DEPTH_CLEAR_ENABLE_MASK 0x1
#define DB_RENDER_CONTROL__DEPTH_CLEAR_ENABLE__SHIFT 0x0
#define DB_RENDER_CONTROL__STENCIL_CLEAR_ENABLE_MASK 0x2
#define DB_RENDER_CONTROL__STENCIL_CLEAR_ENABLE__SHIFT 0x1
#define DB_RENDER_CONTROL__DEPTH_COPY_MASK 0x4
#define DB_RENDER_CONTROL__DEPTH_COPY__SHIFT 0x2
#define DB_RENDER_CONTROL__STENCIL_COPY_MASK 0x8
#define DB_RENDER_CONTROL__STENCIL_COPY__SHIFT 0x3
#define DB_RENDER_CONTROL__RESUMMARIZE_ENABLE_MASK 0x10
#define DB_RENDER_CONTROL__RESUMMARIZE_ENABLE__SHIFT 0x4
#define DB_RENDER_CONTROL__STENCIL_COMPRESS_DISABLE_MASK 0x20
#define DB_RENDER_CONTROL__STENCIL_COMPRESS_DISABLE__SHIFT 0x5
#define DB_RENDER_CONTROL__DEPTH_COMPRESS_DISABLE_MASK 0x40
#define DB_RENDER_CONTROL__DEPTH_COMPRESS_DISABLE__SHIFT 0x6
#define DB_RENDER_CONTROL__COPY_CENTROID_MASK 0x80
#define DB_RENDER_CONTROL__COPY_CENTROID__SHIFT 0x7
#define DB_RENDER_CONTROL__COPY_SAMPLE_MASK 0xf00
#define DB_RENDER_CONTROL__COPY_SAMPLE__SHIFT 0x8
#define DB_RENDER_CONTROL__DECOMPRESS_ENABLE_MASK 0x1000
#define DB_RENDER_CONTROL__DECOMPRESS_ENABLE__SHIFT 0xc
#define DB_COUNT_CONTROL__ZPASS_INCREMENT_DISABLE_MASK 0x1
#define DB_COUNT_CONTROL__ZPASS_INCREMENT_DISABLE__SHIFT 0x0
#define DB_COUNT_CONTROL__PERFECT_ZPASS_COUNTS_MASK 0x2
#define DB_COUNT_CONTROL__PERFECT_ZPASS_COUNTS__SHIFT 0x1
#define DB_COUNT_CONTROL__SAMPLE_RATE_MASK 0x70
#define DB_COUNT_CONTROL__SAMPLE_RATE__SHIFT 0x4
#define DB_COUNT_CONTROL__ZPASS_ENABLE_MASK 0xf00
#define DB_COUNT_CONTROL__ZPASS_ENABLE__SHIFT 0x8
#define DB_COUNT_CONTROL__ZFAIL_ENABLE_MASK 0xf000
#define DB_COUNT_CONTROL__ZFAIL_ENABLE__SHIFT 0xc
#define DB_COUNT_CONTROL__SFAIL_ENABLE_MASK 0xf0000
#define DB_COUNT_CONTROL__SFAIL_ENABLE__SHIFT 0x10
#define DB_COUNT_CONTROL__DBFAIL_ENABLE_MASK 0xf00000
#define DB_COUNT_CONTROL__DBFAIL_ENABLE__SHIFT 0x14
#define DB_COUNT_CONTROL__SLICE_EVEN_ENABLE_MASK 0xf000000
#define DB_COUNT_CONTROL__SLICE_EVEN_ENABLE__SHIFT 0x18
#define DB_COUNT_CONTROL__SLICE_ODD_ENABLE_MASK 0xf0000000
#define DB_COUNT_CONTROL__SLICE_ODD_ENABLE__SHIFT 0x1c
#define DB_RENDER_OVERRIDE__FORCE_HIZ_ENABLE_MASK 0x3
#define DB_RENDER_OVERRIDE__FORCE_HIZ_ENABLE__SHIFT 0x0
#define DB_RENDER_OVERRIDE__FORCE_HIS_ENABLE0_MASK 0xc
#define DB_RENDER_OVERRIDE__FORCE_HIS_ENABLE0__SHIFT 0x2
#define DB_RENDER_OVERRIDE__FORCE_HIS_ENABLE1_MASK 0x30
#define DB_RENDER_OVERRIDE__FORCE_HIS_ENABLE1__SHIFT 0x4
#define DB_RENDER_OVERRIDE__FORCE_SHADER_Z_ORDER_MASK 0x40
#define DB_RENDER_OVERRIDE__FORCE_SHADER_Z_ORDER__SHIFT 0x6
#define DB_RENDER_OVERRIDE__FAST_Z_DISABLE_MASK 0x80
#define DB_RENDER_OVERRIDE__FAST_Z_DISABLE__SHIFT 0x7
#define DB_RENDER_OVERRIDE__FAST_STENCIL_DISABLE_MASK 0x100
#define DB_RENDER_OVERRIDE__FAST_STENCIL_DISABLE__SHIFT 0x8
#define DB_RENDER_OVERRIDE__NOOP_CULL_DISABLE_MASK 0x200
#define DB_RENDER_OVERRIDE__NOOP_CULL_DISABLE__SHIFT 0x9
#define DB_RENDER_OVERRIDE__FORCE_COLOR_KILL_MASK 0x400
#define DB_RENDER_OVERRIDE__FORCE_COLOR_KILL__SHIFT 0xa
#define DB_RENDER_OVERRIDE__FORCE_Z_READ_MASK 0x800
#define DB_RENDER_OVERRIDE__FORCE_Z_READ__SHIFT 0xb
#define DB_RENDER_OVERRIDE__FORCE_STENCIL_READ_MASK 0x1000
#define DB_RENDER_OVERRIDE__FORCE_STENCIL_READ__SHIFT 0xc
#define DB_RENDER_OVERRIDE__FORCE_FULL_Z_RANGE_MASK 0x6000
#define DB_RENDER_OVERRIDE__FORCE_FULL_Z_RANGE__SHIFT 0xd
#define DB_RENDER_OVERRIDE__FORCE_QC_SMASK_CONFLICT_MASK 0x8000
#define DB_RENDER_OVERRIDE__FORCE_QC_SMASK_CONFLICT__SHIFT 0xf
#define DB_RENDER_OVERRIDE__DISABLE_VIEWPORT_CLAMP_MASK 0x10000
#define DB_RENDER_OVERRIDE__DISABLE_VIEWPORT_CLAMP__SHIFT 0x10
#define DB_RENDER_OVERRIDE__IGNORE_SC_ZRANGE_MASK 0x20000
#define DB_RENDER_OVERRIDE__IGNORE_SC_ZRANGE__SHIFT 0x11
#define DB_RENDER_OVERRIDE__DISABLE_FULLY_COVERED_MASK 0x40000
#define DB_RENDER_OVERRIDE__DISABLE_FULLY_COVERED__SHIFT 0x12
#define DB_RENDER_OVERRIDE__FORCE_Z_LIMIT_SUMM_MASK 0x180000
#define DB_RENDER_OVERRIDE__FORCE_Z_LIMIT_SUMM__SHIFT 0x13
#define DB_RENDER_OVERRIDE__MAX_TILES_IN_DTT_MASK 0x3e00000
#define DB_RENDER_OVERRIDE__MAX_TILES_IN_DTT__SHIFT 0x15
#define DB_RENDER_OVERRIDE__DISABLE_TILE_RATE_TILES_MASK 0x4000000
#define DB_RENDER_OVERRIDE__DISABLE_TILE_RATE_TILES__SHIFT 0x1a
#define DB_RENDER_OVERRIDE__FORCE_Z_DIRTY_MASK 0x8000000
#define DB_RENDER_OVERRIDE__FORCE_Z_DIRTY__SHIFT 0x1b
#define DB_RENDER_OVERRIDE__FORCE_STENCIL_DIRTY_MASK 0x10000000
#define DB_RENDER_OVERRIDE__FORCE_STENCIL_DIRTY__SHIFT 0x1c
#define DB_RENDER_OVERRIDE__FORCE_Z_VALID_MASK 0x20000000
#define DB_RENDER_OVERRIDE__FORCE_Z_VALID__SHIFT 0x1d
#define DB_RENDER_OVERRIDE__FORCE_STENCIL_VALID_MASK 0x40000000
#define DB_RENDER_OVERRIDE__FORCE_STENCIL_VALID__SHIFT 0x1e
#define DB_RENDER_OVERRIDE__PRESERVE_COMPRESSION_MASK 0x80000000
#define DB_RENDER_OVERRIDE__PRESERVE_COMPRESSION__SHIFT 0x1f
#define DB_RENDER_OVERRIDE2__PARTIAL_SQUAD_LAUNCH_CONTROL_MASK 0x3
#define DB_RENDER_OVERRIDE2__PARTIAL_SQUAD_LAUNCH_CONTROL__SHIFT 0x0
#define DB_RENDER_OVERRIDE2__PARTIAL_SQUAD_LAUNCH_COUNTDOWN_MASK 0x1c
#define DB_RENDER_OVERRIDE2__PARTIAL_SQUAD_LAUNCH_COUNTDOWN__SHIFT 0x2
#define DB_RENDER_OVERRIDE2__DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION_MASK 0x20
#define DB_RENDER_OVERRIDE2__DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION__SHIFT 0x5
#define DB_RENDER_OVERRIDE2__DISABLE_SMEM_EXPCLEAR_OPTIMIZATION_MASK 0x40
#define DB_RENDER_OVERRIDE2__DISABLE_SMEM_EXPCLEAR_OPTIMIZATION__SHIFT 0x6
#define DB_RENDER_OVERRIDE2__DISABLE_COLOR_ON_VALIDATION_MASK 0x80
#define DB_RENDER_OVERRIDE2__DISABLE_COLOR_ON_VALIDATION__SHIFT 0x7
#define DB_RENDER_OVERRIDE2__DECOMPRESS_Z_ON_FLUSH_MASK 0x100
#define DB_RENDER_OVERRIDE2__DECOMPRESS_Z_ON_FLUSH__SHIFT 0x8
#define DB_RENDER_OVERRIDE2__DISABLE_REG_SNOOP_MASK 0x200
#define DB_RENDER_OVERRIDE2__DISABLE_REG_SNOOP__SHIFT 0x9
#define DB_RENDER_OVERRIDE2__DEPTH_BOUNDS_HIER_DEPTH_DISABLE_MASK 0x400
#define DB_RENDER_OVERRIDE2__DEPTH_BOUNDS_HIER_DEPTH_DISABLE__SHIFT 0xa
#define DB_RENDER_OVERRIDE2__SEPARATE_HIZS_FUNC_ENABLE_MASK 0x800
#define DB_RENDER_OVERRIDE2__SEPARATE_HIZS_FUNC_ENABLE__SHIFT 0xb
#define DB_RENDER_OVERRIDE2__HIZ_ZFUNC_MASK 0x7000
#define DB_RENDER_OVERRIDE2__HIZ_ZFUNC__SHIFT 0xc
#define DB_RENDER_OVERRIDE2__HIS_SFUNC_FF_MASK 0x38000
#define DB_RENDER_OVERRIDE2__HIS_SFUNC_FF__SHIFT 0xf
#define DB_RENDER_OVERRIDE2__HIS_SFUNC_BF_MASK 0x1c0000
#define DB_RENDER_OVERRIDE2__HIS_SFUNC_BF__SHIFT 0x12
#define DB_RENDER_OVERRIDE2__PRESERVE_ZRANGE_MASK 0x200000
#define DB_RENDER_OVERRIDE2__PRESERVE_ZRANGE__SHIFT 0x15
#define DB_RENDER_OVERRIDE2__PRESERVE_SRESULTS_MASK 0x400000
#define DB_RENDER_OVERRIDE2__PRESERVE_SRESULTS__SHIFT 0x16
#define DB_RENDER_OVERRIDE2__DISABLE_FAST_PASS_MASK 0x800000
#define DB_RENDER_OVERRIDE2__DISABLE_FAST_PASS__SHIFT 0x17
#define DB_EQAA__MAX_ANCHOR_SAMPLES_MASK 0x7
#define DB_EQAA__MAX_ANCHOR_SAMPLES__SHIFT 0x0
#define DB_EQAA__PS_ITER_SAMPLES_MASK 0x70
#define DB_EQAA__PS_ITER_SAMPLES__SHIFT 0x4
#define DB_EQAA__MASK_EXPORT_NUM_SAMPLES_MASK 0x700
#define DB_EQAA__MASK_EXPORT_NUM_SAMPLES__SHIFT 0x8
#define DB_EQAA__ALPHA_TO_MASK_NUM_SAMPLES_MASK 0x7000
#define DB_EQAA__ALPHA_TO_MASK_NUM_SAMPLES__SHIFT 0xc
#define DB_EQAA__HIGH_QUALITY_INTERSECTIONS_MASK 0x10000
#define DB_EQAA__HIGH_QUALITY_INTERSECTIONS__SHIFT 0x10
#define DB_EQAA__INCOHERENT_EQAA_READS_MASK 0x20000
#define DB_EQAA__INCOHERENT_EQAA_READS__SHIFT 0x11
#define DB_EQAA__INTERPOLATE_COMP_Z_MASK 0x40000
#define DB_EQAA__INTERPOLATE_COMP_Z__SHIFT 0x12
#define DB_EQAA__INTERPOLATE_SRC_Z_MASK 0x80000
#define DB_EQAA__INTERPOLATE_SRC_Z__SHIFT 0x13
#define DB_EQAA__STATIC_ANCHOR_ASSOCIATIONS_MASK 0x100000
#define DB_EQAA__STATIC_ANCHOR_ASSOCIATIONS__SHIFT 0x14
#define DB_EQAA__ALPHA_TO_MASK_EQAA_DISABLE_MASK 0x200000
#define DB_EQAA__ALPHA_TO_MASK_EQAA_DISABLE__SHIFT 0x15
#define DB_EQAA__OVERRASTERIZATION_AMOUNT_MASK 0x7000000
#define DB_EQAA__OVERRASTERIZATION_AMOUNT__SHIFT 0x18
#define DB_EQAA__ENABLE_POSTZ_OVERRASTERIZATION_MASK 0x8000000
#define DB_EQAA__ENABLE_POSTZ_OVERRASTERIZATION__SHIFT 0x1b
#define DB_SHADER_CONTROL__Z_EXPORT_ENABLE_MASK 0x1
#define DB_SHADER_CONTROL__Z_EXPORT_ENABLE__SHIFT 0x0
#define DB_SHADER_CONTROL__STENCIL_TEST_VAL_EXPORT_ENABLE_MASK 0x2
#define DB_SHADER_CONTROL__STENCIL_TEST_VAL_EXPORT_ENABLE__SHIFT 0x1
#define DB_SHADER_CONTROL__STENCIL_OP_VAL_EXPORT_ENABLE_MASK 0x4
#define DB_SHADER_CONTROL__STENCIL_OP_VAL_EXPORT_ENABLE__SHIFT 0x2
#define DB_SHADER_CONTROL__Z_ORDER_MASK 0x30
#define DB_SHADER_CONTROL__Z_ORDER__SHIFT 0x4
#define DB_SHADER_CONTROL__KILL_ENABLE_MASK 0x40
#define DB_SHADER_CONTROL__KILL_ENABLE__SHIFT 0x6
#define DB_SHADER_CONTROL__COVERAGE_TO_MASK_ENABLE_MASK 0x80
#define DB_SHADER_CONTROL__COVERAGE_TO_MASK_ENABLE__SHIFT 0x7
#define DB_SHADER_CONTROL__MASK_EXPORT_ENABLE_MASK 0x100
#define DB_SHADER_CONTROL__MASK_EXPORT_ENABLE__SHIFT 0x8
#define DB_SHADER_CONTROL__EXEC_ON_HIER_FAIL_MASK 0x200
#define DB_SHADER_CONTROL__EXEC_ON_HIER_FAIL__SHIFT 0x9
#define DB_SHADER_CONTROL__EXEC_ON_NOOP_MASK 0x400
#define DB_SHADER_CONTROL__EXEC_ON_NOOP__SHIFT 0xa
#define DB_SHADER_CONTROL__ALPHA_TO_MASK_DISABLE_MASK 0x800
#define DB_SHADER_CONTROL__ALPHA_TO_MASK_DISABLE__SHIFT 0xb
#define DB_SHADER_CONTROL__DEPTH_BEFORE_SHADER_MASK 0x1000
#define DB_SHADER_CONTROL__DEPTH_BEFORE_SHADER__SHIFT 0xc
#define DB_SHADER_CONTROL__CONSERVATIVE_Z_EXPORT_MASK 0x6000
#define DB_SHADER_CONTROL__CONSERVATIVE_Z_EXPORT__SHIFT 0xd
#define DB_DEPTH_BOUNDS_MIN__MIN_MASK 0xffffffff
#define DB_DEPTH_BOUNDS_MIN__MIN__SHIFT 0x0
#define DB_DEPTH_BOUNDS_MAX__MAX_MASK 0xffffffff
#define DB_DEPTH_BOUNDS_MAX__MAX__SHIFT 0x0
#define DB_STENCIL_CLEAR__CLEAR_MASK 0xff
#define DB_STENCIL_CLEAR__CLEAR__SHIFT 0x0
#define DB_DEPTH_CLEAR__DEPTH_CLEAR_MASK 0xffffffff
#define DB_DEPTH_CLEAR__DEPTH_CLEAR__SHIFT 0x0
#define DB_HTILE_DATA_BASE__BASE_256B_MASK 0xffffffff
#define DB_HTILE_DATA_BASE__BASE_256B__SHIFT 0x0
#define DB_HTILE_SURFACE__LINEAR_MASK 0x1
#define DB_HTILE_SURFACE__LINEAR__SHIFT 0x0
#define DB_HTILE_SURFACE__FULL_CACHE_MASK 0x2
#define DB_HTILE_SURFACE__FULL_CACHE__SHIFT 0x1
#define DB_HTILE_SURFACE__HTILE_USES_PRELOAD_WIN_MASK 0x4
#define DB_HTILE_SURFACE__HTILE_USES_PRELOAD_WIN__SHIFT 0x2
#define DB_HTILE_SURFACE__PRELOAD_MASK 0x8
#define DB_HTILE_SURFACE__PRELOAD__SHIFT 0x3
#define DB_HTILE_SURFACE__PREFETCH_WIDTH_MASK 0x3f0
#define DB_HTILE_SURFACE__PREFETCH_WIDTH__SHIFT 0x4
#define DB_HTILE_SURFACE__PREFETCH_HEIGHT_MASK 0xfc00
#define DB_HTILE_SURFACE__PREFETCH_HEIGHT__SHIFT 0xa
#define DB_HTILE_SURFACE__DST_OUTSIDE_ZERO_TO_ONE_MASK 0x10000
#define DB_HTILE_SURFACE__DST_OUTSIDE_ZERO_TO_ONE__SHIFT 0x10
#define DB_HTILE_SURFACE__TC_COMPATIBLE_MASK 0x20000
#define DB_HTILE_SURFACE__TC_COMPATIBLE__SHIFT 0x11
#define DB_PRELOAD_CONTROL__START_X_MASK 0xff
#define DB_PRELOAD_CONTROL__START_X__SHIFT 0x0
#define DB_PRELOAD_CONTROL__START_Y_MASK 0xff00
#define DB_PRELOAD_CONTROL__START_Y__SHIFT 0x8
#define DB_PRELOAD_CONTROL__MAX_X_MASK 0xff0000
#define DB_PRELOAD_CONTROL__MAX_X__SHIFT 0x10
#define DB_PRELOAD_CONTROL__MAX_Y_MASK 0xff000000
#define DB_PRELOAD_CONTROL__MAX_Y__SHIFT 0x18
#define DB_STENCILREFMASK__STENCILTESTVAL_MASK 0xff
#define DB_STENCILREFMASK__STENCILTESTVAL__SHIFT 0x0
#define DB_STENCILREFMASK__STENCILMASK_MASK 0xff00
#define DB_STENCILREFMASK__STENCILMASK__SHIFT 0x8
#define DB_STENCILREFMASK__STENCILWRITEMASK_MASK 0xff0000
#define DB_STENCILREFMASK__STENCILWRITEMASK__SHIFT 0x10
#define DB_STENCILREFMASK__STENCILOPVAL_MASK 0xff000000
#define DB_STENCILREFMASK__STENCILOPVAL__SHIFT 0x18
#define DB_STENCILREFMASK_BF__STENCILTESTVAL_BF_MASK 0xff
#define DB_STENCILREFMASK_BF__STENCILTESTVAL_BF__SHIFT 0x0
#define DB_STENCILREFMASK_BF__STENCILMASK_BF_MASK 0xff00
#define DB_STENCILREFMASK_BF__STENCILMASK_BF__SHIFT 0x8
#define DB_STENCILREFMASK_BF__STENCILWRITEMASK_BF_MASK 0xff0000
#define DB_STENCILREFMASK_BF__STENCILWRITEMASK_BF__SHIFT 0x10
#define DB_STENCILREFMASK_BF__STENCILOPVAL_BF_MASK 0xff000000
#define DB_STENCILREFMASK_BF__STENCILOPVAL_BF__SHIFT 0x18
#define DB_SRESULTS_COMPARE_STATE0__COMPAREFUNC0_MASK 0x7
#define DB_SRESULTS_COMPARE_STATE0__COMPAREFUNC0__SHIFT 0x0
#define DB_SRESULTS_COMPARE_STATE0__COMPAREVALUE0_MASK 0xff0
#define DB_SRESULTS_COMPARE_STATE0__COMPAREVALUE0__SHIFT 0x4
#define DB_SRESULTS_COMPARE_STATE0__COMPAREMASK0_MASK 0xff000
#define DB_SRESULTS_COMPARE_STATE0__COMPAREMASK0__SHIFT 0xc
#define DB_SRESULTS_COMPARE_STATE0__ENABLE0_MASK 0x1000000
#define DB_SRESULTS_COMPARE_STATE0__ENABLE0__SHIFT 0x18
#define DB_SRESULTS_COMPARE_STATE1__COMPAREFUNC1_MASK 0x7
#define DB_SRESULTS_COMPARE_STATE1__COMPAREFUNC1__SHIFT 0x0
#define DB_SRESULTS_COMPARE_STATE1__COMPAREVALUE1_MASK 0xff0
#define DB_SRESULTS_COMPARE_STATE1__COMPAREVALUE1__SHIFT 0x4
#define DB_SRESULTS_COMPARE_STATE1__COMPAREMASK1_MASK 0xff000
#define DB_SRESULTS_COMPARE_STATE1__COMPAREMASK1__SHIFT 0xc
#define DB_SRESULTS_COMPARE_STATE1__ENABLE1_MASK 0x1000000
#define DB_SRESULTS_COMPARE_STATE1__ENABLE1__SHIFT 0x18
#define DB_DEPTH_CONTROL__STENCIL_ENABLE_MASK 0x1
#define DB_DEPTH_CONTROL__STENCIL_ENABLE__SHIFT 0x0
#define DB_DEPTH_CONTROL__Z_ENABLE_MASK 0x2
#define DB_DEPTH_CONTROL__Z_ENABLE__SHIFT 0x1
#define DB_DEPTH_CONTROL__Z_WRITE_ENABLE_MASK 0x4
#define DB_DEPTH_CONTROL__Z_WRITE_ENABLE__SHIFT 0x2
#define DB_DEPTH_CONTROL__DEPTH_BOUNDS_ENABLE_MASK 0x8
#define DB_DEPTH_CONTROL__DEPTH_BOUNDS_ENABLE__SHIFT 0x3
#define DB_DEPTH_CONTROL__ZFUNC_MASK 0x70
#define DB_DEPTH_CONTROL__ZFUNC__SHIFT 0x4
#define DB_DEPTH_CONTROL__BACKFACE_ENABLE_MASK 0x80
#define DB_DEPTH_CONTROL__BACKFACE_ENABLE__SHIFT 0x7
#define DB_DEPTH_CONTROL__STENCILFUNC_MASK 0x700
#define DB_DEPTH_CONTROL__STENCILFUNC__SHIFT 0x8
#define DB_DEPTH_CONTROL__STENCILFUNC_BF_MASK 0x700000
#define DB_DEPTH_CONTROL__STENCILFUNC_BF__SHIFT 0x14
#define DB_DEPTH_CONTROL__ENABLE_COLOR_WRITES_ON_DEPTH_FAIL_MASK 0x40000000
#define DB_DEPTH_CONTROL__ENABLE_COLOR_WRITES_ON_DEPTH_FAIL__SHIFT 0x1e
#define DB_DEPTH_CONTROL__DISABLE_COLOR_WRITES_ON_DEPTH_PASS_MASK 0x80000000
#define DB_DEPTH_CONTROL__DISABLE_COLOR_WRITES_ON_DEPTH_PASS__SHIFT 0x1f
#define DB_STENCIL_CONTROL__STENCILFAIL_MASK 0xf
#define DB_STENCIL_CONTROL__STENCILFAIL__SHIFT 0x0
#define DB_STENCIL_CONTROL__STENCILZPASS_MASK 0xf0
#define DB_STENCIL_CONTROL__STENCILZPASS__SHIFT 0x4
#define DB_STENCIL_CONTROL__STENCILZFAIL_MASK 0xf00
#define DB_STENCIL_CONTROL__STENCILZFAIL__SHIFT 0x8
#define DB_STENCIL_CONTROL__STENCILFAIL_BF_MASK 0xf000
#define DB_STENCIL_CONTROL__STENCILFAIL_BF__SHIFT 0xc
#define DB_STENCIL_CONTROL__STENCILZPASS_BF_MASK 0xf0000
#define DB_STENCIL_CONTROL__STENCILZPASS_BF__SHIFT 0x10
#define DB_STENCIL_CONTROL__STENCILZFAIL_BF_MASK 0xf00000
#define DB_STENCIL_CONTROL__STENCILZFAIL_BF__SHIFT 0x14
#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_ENABLE_MASK 0x1
#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_ENABLE__SHIFT 0x0
#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET0_MASK 0x300
#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET0__SHIFT 0x8
#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET1_MASK 0xc00
#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET1__SHIFT 0xa
#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET2_MASK 0x3000
#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET2__SHIFT 0xc
#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET3_MASK 0xc000
#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET3__SHIFT 0xe
#define DB_ALPHA_TO_MASK__OFFSET_ROUND_MASK 0x10000
#define DB_ALPHA_TO_MASK__OFFSET_ROUND__SHIFT 0x10
#define DB_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x3ff
#define DB_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
#define DB_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0xffc00
#define DB_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
#define DB_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000
#define DB_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
#define DB_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0xf000000
#define DB_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18
#define DB_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xf0000000
#define DB_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c
#define DB_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x3ff
#define DB_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
#define DB_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0xffc00
#define DB_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa
#define DB_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0xf00000
#define DB_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14
#define DB_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0xf000000
#define DB_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18
#define DB_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xf0000000
#define DB_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c
#define DB_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x3ff
#define DB_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0
#define DB_PERFCOUNTER2_SELECT__PERF_SEL1_MASK 0xffc00
#define DB_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT 0xa
#define DB_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0xf00000
#define DB_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14
#define DB_PERFCOUNTER2_SELECT__PERF_MODE1_MASK 0xf000000
#define DB_PERFCOUNTER2_SELECT__PERF_MODE1__SHIFT 0x18
#define DB_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xf0000000
#define DB_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c
#define DB_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x3ff
#define DB_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0
#define DB_PERFCOUNTER3_SELECT__PERF_SEL1_MASK 0xffc00
#define DB_PERFCOUNTER3_SELECT__PERF_SEL1__SHIFT 0xa
#define DB_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0xf00000
#define DB_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14
#define DB_PERFCOUNTER3_SELECT__PERF_MODE1_MASK 0xf000000
#define DB_PERFCOUNTER3_SELECT__PERF_MODE1__SHIFT 0x18
#define DB_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xf0000000
#define DB_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c
#define DB_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x3ff
#define DB_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0
#define DB_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0xffc00
#define DB_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
#define DB_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0xf000000
#define DB_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18
#define DB_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xf0000000
#define DB_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c
#define DB_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x3ff
#define DB_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0
#define DB_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0xffc00
#define DB_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa
#define DB_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0xf000000
#define DB_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x18
#define DB_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0xf0000000
#define DB_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x1c
#define DB_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff
#define DB_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
#define DB_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff
#define DB_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
#define DB_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffff
#define DB_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0
#define DB_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffff
#define DB_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0
#define DB_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff
#define DB_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
#define DB_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff
#define DB_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
#define DB_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffff
#define DB_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0
#define DB_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffff
#define DB_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0
#define DB_DEBUG__DEBUG_STENCIL_COMPRESS_DISABLE_MASK 0x1
#define DB_DEBUG__DEBUG_STENCIL_COMPRESS_DISABLE__SHIFT 0x0
#define DB_DEBUG__DEBUG_DEPTH_COMPRESS_DISABLE_MASK 0x2
#define DB_DEBUG__DEBUG_DEPTH_COMPRESS_DISABLE__SHIFT 0x1
#define DB_DEBUG__FETCH_FULL_Z_TILE_MASK 0x4
#define DB_DEBUG__FETCH_FULL_Z_TILE__SHIFT 0x2
#define DB_DEBUG__FETCH_FULL_STENCIL_TILE_MASK 0x8
#define DB_DEBUG__FETCH_FULL_STENCIL_TILE__SHIFT 0x3
#define DB_DEBUG__FORCE_Z_MODE_MASK 0x30
#define DB_DEBUG__FORCE_Z_MODE__SHIFT 0x4
#define DB_DEBUG__DEBUG_FORCE_DEPTH_READ_MASK 0x40
#define DB_DEBUG__DEBUG_FORCE_DEPTH_READ__SHIFT 0x6
#define DB_DEBUG__DEBUG_FORCE_STENCIL_READ_MASK 0x80
#define DB_DEBUG__DEBUG_FORCE_STENCIL_READ__SHIFT 0x7
#define DB_DEBUG__DEBUG_FORCE_HIZ_ENABLE_MASK 0x300
#define DB_DEBUG__DEBUG_FORCE_HIZ_ENABLE__SHIFT 0x8
#define DB_DEBUG__DEBUG_FORCE_HIS_ENABLE0_MASK 0xc00
#define DB_DEBUG__DEBUG_FORCE_HIS_ENABLE0__SHIFT 0xa
#define DB_DEBUG__DEBUG_FORCE_HIS_ENABLE1_MASK 0x3000
#define DB_DEBUG__DEBUG_FORCE_HIS_ENABLE1__SHIFT 0xc
#define DB_DEBUG__DEBUG_FAST_Z_DISABLE_MASK 0x4000
#define DB_DEBUG__DEBUG_FAST_Z_DISABLE__SHIFT 0xe
#define DB_DEBUG__DEBUG_FAST_STENCIL_DISABLE_MASK 0x8000
#define DB_DEBUG__DEBUG_FAST_STENCIL_DISABLE__SHIFT 0xf
#define DB_DEBUG__DEBUG_NOOP_CULL_DISABLE_MASK 0x10000
#define DB_DEBUG__DEBUG_NOOP_CULL_DISABLE__SHIFT 0x10
#define DB_DEBUG__DISABLE_SUMM_SQUADS_MASK 0x20000
#define DB_DEBUG__DISABLE_SUMM_SQUADS__SHIFT 0x11
#define DB_DEBUG__DEPTH_CACHE_FORCE_MISS_MASK 0x40000
#define DB_DEBUG__DEPTH_CACHE_FORCE_MISS__SHIFT 0x12
#define DB_DEBUG__DEBUG_FORCE_FULL_Z_RANGE_MASK 0x180000
#define DB_DEBUG__DEBUG_FORCE_FULL_Z_RANGE__SHIFT 0x13
#define DB_DEBUG__NEVER_FREE_Z_ONLY_MASK 0x200000
#define DB_DEBUG__NEVER_FREE_Z_ONLY__SHIFT 0x15
#define DB_DEBUG__ZPASS_COUNTS_LOOK_AT_PIPE_STAT_EVENTS_MASK 0x400000
#define DB_DEBUG__ZPASS_COUNTS_LOOK_AT_PIPE_STAT_EVENTS__SHIFT 0x16
#define DB_DEBUG__DISABLE_VPORT_ZPLANE_OPTIMIZATION_MASK 0x800000
#define DB_DEBUG__DISABLE_VPORT_ZPLANE_OPTIMIZATION__SHIFT 0x17
#define DB_DEBUG__DECOMPRESS_AFTER_N_ZPLANES_MASK 0xf000000
#define DB_DEBUG__DECOMPRESS_AFTER_N_ZPLANES__SHIFT 0x18
#define DB_DEBUG__ONE_FREE_IN_FLIGHT_MASK 0x10000000
#define DB_DEBUG__ONE_FREE_IN_FLIGHT__SHIFT 0x1c
#define DB_DEBUG__FORCE_MISS_IF_NOT_INFLIGHT_MASK 0x20000000
#define DB_DEBUG__FORCE_MISS_IF_NOT_INFLIGHT__SHIFT 0x1d
#define DB_DEBUG__DISABLE_DEPTH_SURFACE_SYNC_MASK 0x40000000
#define DB_DEBUG__DISABLE_DEPTH_SURFACE_SYNC__SHIFT 0x1e
#define DB_DEBUG__DISABLE_HTILE_SURFACE_SYNC_MASK 0x80000000
#define DB_DEBUG__DISABLE_HTILE_SURFACE_SYNC__SHIFT 0x1f
#define DB_DEBUG2__ALLOW_COMPZ_BYTE_MASKING_MASK 0x1
#define DB_DEBUG2__ALLOW_COMPZ_BYTE_MASKING__SHIFT 0x0
#define DB_DEBUG2__DISABLE_TC_ZRANGE_L0_CACHE_MASK 0x2
#define DB_DEBUG2__DISABLE_TC_ZRANGE_L0_CACHE__SHIFT 0x1
#define DB_DEBUG2__DISABLE_TC_MASK_L0_CACHE_MASK 0x4
#define DB_DEBUG2__DISABLE_TC_MASK_L0_CACHE__SHIFT 0x2
#define DB_DEBUG2__DTR_ROUND_ROBIN_ARB_MASK 0x8
#define DB_DEBUG2__DTR_ROUND_ROBIN_ARB__SHIFT 0x3
#define DB_DEBUG2__DTR_PREZ_STALLS_FOR_ETF_ROOM_MASK 0x10
#define DB_DEBUG2__DTR_PREZ_STALLS_FOR_ETF_ROOM__SHIFT 0x4
#define DB_DEBUG2__DISABLE_PREZL_LPF_STALL_MASK 0x20
#define DB_DEBUG2__DISABLE_PREZL_LPF_STALL__SHIFT 0x5
#define DB_DEBUG2__ENABLE_PREZL_CB_STALL_MASK 0x40
#define DB_DEBUG2__ENABLE_PREZL_CB_STALL__SHIFT 0x6
#define DB_DEBUG2__DISABLE_PREZL_LPF_STALL_REZ_MASK 0x80
#define DB_DEBUG2__DISABLE_PREZL_LPF_STALL_REZ__SHIFT 0x7
#define DB_DEBUG2__DISABLE_PREZL_CB_STALL_REZ_MASK 0x100
#define DB_DEBUG2__DISABLE_PREZL_CB_STALL_REZ__SHIFT 0x8
#define DB_DEBUG2__CLK_OFF_DELAY_MASK 0x3e00
#define DB_DEBUG2__CLK_OFF_DELAY__SHIFT 0x9
#define DB_DEBUG2__DISABLE_TILE_COVERED_FOR_PS_ITER_MASK 0x4000
#define DB_DEBUG2__DISABLE_TILE_COVERED_FOR_PS_ITER__SHIFT 0xe
#define DB_DEBUG2__ENABLE_SUBTILE_GROUPING_MASK 0x8000
#define DB_DEBUG2__ENABLE_SUBTILE_GROUPING__SHIFT 0xf
#define DB_DEBUG2__DISABLE_HTILE_PAIRED_PIPES_MASK 0x10000
#define DB_DEBUG2__DISABLE_HTILE_PAIRED_PIPES__SHIFT 0x10
#define DB_DEBUG2__DISABLE_NULL_EOT_FORWARDING_MASK 0x20000
#define DB_DEBUG2__DISABLE_NULL_EOT_FORWARDING__SHIFT 0x11
#define DB_DEBUG2__DISABLE_DTT_DATA_FORWARDING_MASK 0x40000
#define DB_DEBUG2__DISABLE_DTT_DATA_FORWARDING__SHIFT 0x12
#define DB_DEBUG2__DISABLE_QUAD_COHERENCY_STALL_MASK 0x80000
#define DB_DEBUG2__DISABLE_QUAD_COHERENCY_STALL__SHIFT 0x13
#define DB_DEBUG2__ENABLE_PREZ_OF_REZ_SUMM_MASK 0x10000000
#define DB_DEBUG2__ENABLE_PREZ_OF_REZ_SUMM__SHIFT 0x1c
#define DB_DEBUG2__DISABLE_PREZL_VIEWPORT_STALL_MASK 0x20000000
#define DB_DEBUG2__DISABLE_PREZL_VIEWPORT_STALL__SHIFT 0x1d
#define DB_DEBUG2__DISABLE_SINGLE_STENCIL_QUAD_SUMM_MASK 0x40000000
#define DB_DEBUG2__DISABLE_SINGLE_STENCIL_QUAD_SUMM__SHIFT 0x1e
#define DB_DEBUG2__DISABLE_WRITE_STALL_ON_RDWR_CONFLICT_MASK 0x80000000
#define DB_DEBUG2__DISABLE_WRITE_STALL_ON_RDWR_CONFLICT__SHIFT 0x1f
#define DB_DEBUG3__FORCE_DB_IS_GOOD_MASK 0x4
#define DB_DEBUG3__FORCE_DB_IS_GOOD__SHIFT 0x2
#define DB_DEBUG3__DISABLE_TL_SSO_NULL_SUPPRESSION_MASK 0x8
#define DB_DEBUG3__DISABLE_TL_SSO_NULL_SUPPRESSION__SHIFT 0x3
#define DB_DEBUG3__DISABLE_HIZ_ON_VPORT_CLAMP_MASK 0x10
#define DB_DEBUG3__DISABLE_HIZ_ON_VPORT_CLAMP__SHIFT 0x4
#define DB_DEBUG3__EQAA_INTERPOLATE_COMP_Z_MASK 0x20
#define DB_DEBUG3__EQAA_INTERPOLATE_COMP_Z__SHIFT 0x5
#define DB_DEBUG3__EQAA_INTERPOLATE_SRC_Z_MASK 0x40
#define DB_DEBUG3__EQAA_INTERPOLATE_SRC_Z__SHIFT 0x6
#define DB_DEBUG3__DISABLE_TCP_CAM_BYPASS_MASK 0x80
#define DB_DEBUG3__DISABLE_TCP_CAM_BYPASS__SHIFT 0x7
#define DB_DEBUG3__DISABLE_ZCMP_DIRTY_SUPPRESSION_MASK 0x100
#define DB_DEBUG3__DISABLE_ZCMP_DIRTY_SUPPRESSION__SHIFT 0x8
#define DB_DEBUG3__DISABLE_REDUNDANT_PLANE_FLUSHES_OPT_MASK 0x200
#define DB_DEBUG3__DISABLE_REDUNDANT_PLANE_FLUSHES_OPT__SHIFT 0x9
#define DB_DEBUG3__DISABLE_RECOMP_TO_1ZPLANE_WITHOUT_FASTOP_MASK 0x400
#define DB_DEBUG3__DISABLE_RECOMP_TO_1ZPLANE_WITHOUT_FASTOP__SHIFT 0xa
#define DB_DEBUG3__ENABLE_INCOHERENT_EQAA_READS_MASK 0x800
#define DB_DEBUG3__ENABLE_INCOHERENT_EQAA_READS__SHIFT 0xb
#define DB_DEBUG3__DISABLE_OP_Z_DATA_FORWARDING_MASK 0x1000
#define DB_DEBUG3__DISABLE_OP_Z_DATA_FORWARDING__SHIFT 0xc
#define DB_DEBUG3__DISABLE_OP_DF_BYPASS_MASK 0x2000
#define DB_DEBUG3__DISABLE_OP_DF_BYPASS__SHIFT 0xd
#define DB_DEBUG3__DISABLE_OP_DF_WRITE_COMBINE_MASK 0x4000
#define DB_DEBUG3__DISABLE_OP_DF_WRITE_COMBINE__SHIFT 0xe
#define DB_DEBUG3__DISABLE_OP_DF_DIRECT_FEEDBACK_MASK 0x8000
#define DB_DEBUG3__DISABLE_OP_DF_DIRECT_FEEDBACK__SHIFT 0xf
#define DB_DEBUG3__ALLOW_RF2P_RW_COLLISION_MASK 0x10000
#define DB_DEBUG3__ALLOW_RF2P_RW_COLLISION__SHIFT 0x10
#define DB_DEBUG3__SLOW_PREZ_TO_A2M_OMASK_RATE_MASK 0x20000
#define DB_DEBUG3__SLOW_PREZ_TO_A2M_OMASK_RATE__SHIFT 0x11
#define DB_DEBUG3__DISABLE_OP_S_DATA_FORWARDING_MASK 0x40000
#define DB_DEBUG3__DISABLE_OP_S_DATA_FORWARDING__SHIFT 0x12
#define DB_DEBUG3__DISABLE_TC_UPDATE_WRITE_COMBINE_MASK 0x80000
#define DB_DEBUG3__DISABLE_TC_UPDATE_WRITE_COMBINE__SHIFT 0x13
#define DB_DEBUG3__DISABLE_HZ_TC_WRITE_COMBINE_MASK 0x100000
#define DB_DEBUG3__DISABLE_HZ_TC_WRITE_COMBINE__SHIFT 0x14
#define DB_DEBUG3__ENABLE_RECOMP_ZDIRTY_SUPPRESSION_OPT_MASK 0x200000
#define DB_DEBUG3__ENABLE_RECOMP_ZDIRTY_SUPPRESSION_OPT__SHIFT 0x15
#define DB_DEBUG3__ENABLE_TC_MA_ROUND_ROBIN_ARB_MASK 0x400000
#define DB_DEBUG3__ENABLE_TC_MA_ROUND_ROBIN_ARB__SHIFT 0x16
#define DB_DEBUG3__DISABLE_RAM_READ_SUPPRESION_ON_FWD_MASK 0x800000
#define DB_DEBUG3__DISABLE_RAM_READ_SUPPRESION_ON_FWD__SHIFT 0x17
#define DB_DEBUG3__DISABLE_EQAA_A2M_PERF_OPT_MASK 0x1000000
#define DB_DEBUG3__DISABLE_EQAA_A2M_PERF_OPT__SHIFT 0x18
#define DB_DEBUG3__DISABLE_DI_DT_STALL_MASK 0x2000000
#define DB_DEBUG3__DISABLE_DI_DT_STALL__SHIFT 0x19
#define DB_DEBUG3__ENABLE_DB_PROCESS_RESET_MASK 0x4000000
#define DB_DEBUG3__ENABLE_DB_PROCESS_RESET__SHIFT 0x1a
#define DB_DEBUG3__DISABLE_OVERRASTERIZATION_FIX_MASK 0x8000000
#define DB_DEBUG3__DISABLE_OVERRASTERIZATION_FIX__SHIFT 0x1b
#define DB_DEBUG3__DONT_INSERT_CONTEXT_SUSPEND_MASK 0x10000000
#define DB_DEBUG3__DONT_INSERT_CONTEXT_SUSPEND__SHIFT 0x1c
#define DB_DEBUG3__DONT_DELETE_CONTEXT_SUSPEND_MASK 0x20000000
#define DB_DEBUG3__DONT_DELETE_CONTEXT_SUSPEND__SHIFT 0x1d
#define DB_DEBUG3__DISABLE_4XAA_2P_DELAYED_WRITE_MASK 0x40000000
#define DB_DEBUG3__DISABLE_4XAA_2P_DELAYED_WRITE__SHIFT 0x1e
#define DB_DEBUG3__DISABLE_4XAA_2P_INTERLEAVED_PMASK_MASK 0x80000000
#define DB_DEBUG3__DISABLE_4XAA_2P_INTERLEAVED_PMASK__SHIFT 0x1f
#define DB_DEBUG4__DISABLE_QC_Z_MASK_SUMMATION_MASK 0x1
#define DB_DEBUG4__DISABLE_QC_Z_MASK_SUMMATION__SHIFT 0x0
#define DB_DEBUG4__DISABLE_QC_STENCIL_MASK_SUMMATION_MASK 0x2
#define DB_DEBUG4__DISABLE_QC_STENCIL_MASK_SUMMATION__SHIFT 0x1
#define DB_DEBUG4__DISABLE_RESUMM_TO_SINGLE_STENCIL_MASK 0x4
#define DB_DEBUG4__DISABLE_RESUMM_TO_SINGLE_STENCIL__SHIFT 0x2
#define DB_DEBUG4__DISABLE_PREZ_POSTZ_DTILE_CONFLICT_STALL_MASK 0x8
#define DB_DEBUG4__DISABLE_PREZ_POSTZ_DTILE_CONFLICT_STALL__SHIFT 0x3
#define DB_DEBUG4__DB_EXTRA_DEBUG4_MASK 0xfffffff0
#define DB_DEBUG4__DB_EXTRA_DEBUG4__SHIFT 0x4
#define DB_CREDIT_LIMIT__DB_SC_TILE_CREDITS_MASK 0x1f
#define DB_CREDIT_LIMIT__DB_SC_TILE_CREDITS__SHIFT 0x0
#define DB_CREDIT_LIMIT__DB_SC_QUAD_CREDITS_MASK 0x3e0
#define DB_CREDIT_LIMIT__DB_SC_QUAD_CREDITS__SHIFT 0x5
#define DB_CREDIT_LIMIT__DB_CB_LQUAD_CREDITS_MASK 0x1c00
#define DB_CREDIT_LIMIT__DB_CB_LQUAD_CREDITS__SHIFT 0xa
#define DB_CREDIT_LIMIT__DB_CB_TILE_CREDITS_MASK 0x7f000000
#define DB_CREDIT_LIMIT__DB_CB_TILE_CREDITS__SHIFT 0x18
#define DB_WATERMARKS__DEPTH_FREE_MASK 0x1f
#define DB_WATERMARKS__DEPTH_FREE__SHIFT 0x0
#define DB_WATERMARKS__DEPTH_FLUSH_MASK 0x7e0
#define DB_WATERMARKS__DEPTH_FLUSH__SHIFT 0x5
#define DB_WATERMARKS__FORCE_SUMMARIZE_MASK 0x7800
#define DB_WATERMARKS__FORCE_SUMMARIZE__SHIFT 0xb
#define DB_WATERMARKS__DEPTH_PENDING_FREE_MASK 0xf8000
#define DB_WATERMARKS__DEPTH_PENDING_FREE__SHIFT 0xf
#define DB_WATERMARKS__DEPTH_CACHELINE_FREE_MASK 0x7f00000
#define DB_WATERMARKS__DEPTH_CACHELINE_FREE__SHIFT 0x14
#define DB_WATERMARKS__EARLY_Z_PANIC_DISABLE_MASK 0x8000000
#define DB_WATERMARKS__EARLY_Z_PANIC_DISABLE__SHIFT 0x1b
#define DB_WATERMARKS__LATE_Z_PANIC_DISABLE_MASK 0x10000000
#define DB_WATERMARKS__LATE_Z_PANIC_DISABLE__SHIFT 0x1c
#define DB_WATERMARKS__RE_Z_PANIC_DISABLE_MASK 0x20000000
#define DB_WATERMARKS__RE_Z_PANIC_DISABLE__SHIFT 0x1d
#define DB_WATERMARKS__AUTO_FLUSH_HTILE_MASK 0x40000000
#define DB_WATERMARKS__AUTO_FLUSH_HTILE__SHIFT 0x1e
#define DB_WATERMARKS__AUTO_FLUSH_QUAD_MASK 0x80000000
#define DB_WATERMARKS__AUTO_FLUSH_QUAD__SHIFT 0x1f
#define DB_SUBTILE_CONTROL__MSAA1_X_MASK 0x3
#define DB_SUBTILE_CONTROL__MSAA1_X__SHIFT 0x0
#define DB_SUBTILE_CONTROL__MSAA1_Y_MASK 0xc
#define DB_SUBTILE_CONTROL__MSAA1_Y__SHIFT 0x2
#define DB_SUBTILE_CONTROL__MSAA2_X_MASK 0x30
#define DB_SUBTILE_CONTROL__MSAA2_X__SHIFT 0x4
#define DB_SUBTILE_CONTROL__MSAA2_Y_MASK 0xc0
#define DB_SUBTILE_CONTROL__MSAA2_Y__SHIFT 0x6
#define DB_SUBTILE_CONTROL__MSAA4_X_MASK 0x300
#define DB_SUBTILE_CONTROL__MSAA4_X__SHIFT 0x8
#define DB_SUBTILE_CONTROL__MSAA4_Y_MASK 0xc00
#define DB_SUBTILE_CONTROL__MSAA4_Y__SHIFT 0xa
#define DB_SUBTILE_CONTROL__MSAA8_X_MASK 0x3000
#define DB_SUBTILE_CONTROL__MSAA8_X__SHIFT 0xc
#define DB_SUBTILE_CONTROL__MSAA8_Y_MASK 0xc000
#define DB_SUBTILE_CONTROL__MSAA8_Y__SHIFT 0xe
#define DB_SUBTILE_CONTROL__MSAA16_X_MASK 0x30000
#define DB_SUBTILE_CONTROL__MSAA16_X__SHIFT 0x10
#define DB_SUBTILE_CONTROL__MSAA16_Y_MASK 0xc0000
#define DB_SUBTILE_CONTROL__MSAA16_Y__SHIFT 0x12
#define DB_FREE_CACHELINES__FREE_DTILE_DEPTH_MASK 0x7f
#define DB_FREE_CACHELINES__FREE_DTILE_DEPTH__SHIFT 0x0
#define DB_FREE_CACHELINES__FREE_PLANE_DEPTH_MASK 0x3f80
#define DB_FREE_CACHELINES__FREE_PLANE_DEPTH__SHIFT 0x7
#define DB_FREE_CACHELINES__FREE_Z_DEPTH_MASK 0x1fc000
#define DB_FREE_CACHELINES__FREE_Z_DEPTH__SHIFT 0xe
#define DB_FREE_CACHELINES__FREE_HTILE_DEPTH_MASK 0x1e00000
#define DB_FREE_CACHELINES__FREE_HTILE_DEPTH__SHIFT 0x15
#define DB_FREE_CACHELINES__QUAD_READ_REQS_MASK 0xfe000000
#define DB_FREE_CACHELINES__QUAD_READ_REQS__SHIFT 0x19
#define DB_FIFO_DEPTH1__MI_RDREQ_FIFO_DEPTH_MASK 0x1f
#define DB_FIFO_DEPTH1__MI_RDREQ_FIFO_DEPTH__SHIFT 0x0
#define DB_FIFO_DEPTH1__MI_WRREQ_FIFO_DEPTH_MASK 0x3e0
#define DB_FIFO_DEPTH1__MI_WRREQ_FIFO_DEPTH__SHIFT 0x5
#define DB_FIFO_DEPTH1__MCC_DEPTH_MASK 0xfc00
#define DB_FIFO_DEPTH1__MCC_DEPTH__SHIFT 0xa
#define DB_FIFO_DEPTH1__QC_DEPTH_MASK 0x1f0000
#define DB_FIFO_DEPTH1__QC_DEPTH__SHIFT 0x10
#define DB_FIFO_DEPTH1__LTILE_PROBE_FIFO_DEPTH_MASK 0x1fe00000
#define DB_FIFO_DEPTH1__LTILE_PROBE_FIFO_DEPTH__SHIFT 0x15
#define DB_FIFO_DEPTH2__EQUAD_FIFO_DEPTH_MASK 0xff
#define DB_FIFO_DEPTH2__EQUAD_FIFO_DEPTH__SHIFT 0x0
#define DB_FIFO_DEPTH2__ETILE_OP_FIFO_DEPTH_MASK 0x7f00
#define DB_FIFO_DEPTH2__ETILE_OP_FIFO_DEPTH__SHIFT 0x8
#define DB_FIFO_DEPTH2__LQUAD_FIFO_DEPTH_MASK 0x1ff8000
#define DB_FIFO_DEPTH2__LQUAD_FIFO_DEPTH__SHIFT 0xf
#define DB_FIFO_DEPTH2__LTILE_OP_FIFO_DEPTH_MASK 0xfe000000
#define DB_FIFO_DEPTH2__LTILE_OP_FIFO_DEPTH__SHIFT 0x19
#define DB_CGTT_CLK_CTRL_0__ON_DELAY_MASK 0xf
#define DB_CGTT_CLK_CTRL_0__ON_DELAY__SHIFT 0x0
#define DB_CGTT_CLK_CTRL_0__OFF_HYSTERESIS_MASK 0xff0
#define DB_CGTT_CLK_CTRL_0__OFF_HYSTERESIS__SHIFT 0x4
#define DB_CGTT_CLK_CTRL_0__RESERVED_MASK 0xfff000
#define DB_CGTT_CLK_CTRL_0__RESERVED__SHIFT 0xc
#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE7_MASK 0x1000000
#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE7__SHIFT 0x18
#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE6_MASK 0x2000000
#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE6__SHIFT 0x19
#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE5_MASK 0x4000000
#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE5__SHIFT 0x1a
#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE4_MASK 0x8000000
#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE4__SHIFT 0x1b
#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE3_MASK 0x10000000
#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE3__SHIFT 0x1c
#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE2_MASK 0x20000000
#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE2__SHIFT 0x1d
#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE1_MASK 0x40000000
#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE1__SHIFT 0x1e
#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE0_MASK 0x80000000
#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE0__SHIFT 0x1f
#define DB_ZPASS_COUNT_LOW__COUNT_LOW_MASK 0xffffffff
#define DB_ZPASS_COUNT_LOW__COUNT_LOW__SHIFT 0x0
#define DB_ZPASS_COUNT_HI__COUNT_HI_MASK 0x7fffffff
#define DB_ZPASS_COUNT_HI__COUNT_HI__SHIFT 0x0
#define DB_RING_CONTROL__COUNTER_CONTROL_MASK 0x3
#define DB_RING_CONTROL__COUNTER_CONTROL__SHIFT 0x0
#define DB_READ_DEBUG_0__BUSY_DATA0_MASK 0xffffffff
#define DB_READ_DEBUG_0__BUSY_DATA0__SHIFT 0x0
#define DB_READ_DEBUG_1__BUSY_DATA1_MASK 0xffffffff
#define DB_READ_DEBUG_1__BUSY_DATA1__SHIFT 0x0
#define DB_READ_DEBUG_2__BUSY_DATA2_MASK 0xffffffff
#define DB_READ_DEBUG_2__BUSY_DATA2__SHIFT 0x0
#define DB_READ_DEBUG_3__DEBUG_DATA_MASK 0xffffffff
#define DB_READ_DEBUG_3__DEBUG_DATA__SHIFT 0x0
#define DB_READ_DEBUG_4__DEBUG_DATA_MASK 0xffffffff
#define DB_READ_DEBUG_4__DEBUG_DATA__SHIFT 0x0
#define DB_READ_DEBUG_5__DEBUG_DATA_MASK 0xffffffff
#define DB_READ_DEBUG_5__DEBUG_DATA__SHIFT 0x0
#define DB_READ_DEBUG_6__DEBUG_DATA_MASK 0xffffffff
#define DB_READ_DEBUG_6__DEBUG_DATA__SHIFT 0x0
#define DB_READ_DEBUG_7__DEBUG_DATA_MASK 0xffffffff
#define DB_READ_DEBUG_7__DEBUG_DATA__SHIFT 0x0
#define DB_READ_DEBUG_8__DEBUG_DATA_MASK 0xffffffff
#define DB_READ_DEBUG_8__DEBUG_DATA__SHIFT 0x0
#define DB_READ_DEBUG_9__DEBUG_DATA_MASK 0xffffffff
#define DB_READ_DEBUG_9__DEBUG_DATA__SHIFT 0x0
#define DB_READ_DEBUG_A__DEBUG_DATA_MASK 0xffffffff
#define DB_READ_DEBUG_A__DEBUG_DATA__SHIFT 0x0
#define DB_READ_DEBUG_B__DEBUG_DATA_MASK 0xffffffff
#define DB_READ_DEBUG_B__DEBUG_DATA__SHIFT 0x0
#define DB_READ_DEBUG_C__DEBUG_DATA_MASK 0xffffffff
#define DB_READ_DEBUG_C__DEBUG_DATA__SHIFT 0x0
#define DB_READ_DEBUG_D__DEBUG_DATA_MASK 0xffffffff
#define DB_READ_DEBUG_D__DEBUG_DATA__SHIFT 0x0
#define DB_READ_DEBUG_E__DEBUG_DATA_MASK 0xffffffff
#define DB_READ_DEBUG_E__DEBUG_DATA__SHIFT 0x0
#define DB_READ_DEBUG_F__DEBUG_DATA_MASK 0xffffffff
#define DB_READ_DEBUG_F__DEBUG_DATA__SHIFT 0x0
#define DB_OCCLUSION_COUNT0_LOW__COUNT_LOW_MASK 0xffffffff
#define DB_OCCLUSION_COUNT0_LOW__COUNT_LOW__SHIFT 0x0
#define DB_OCCLUSION_COUNT0_HI__COUNT_HI_MASK 0x7fffffff
#define DB_OCCLUSION_COUNT0_HI__COUNT_HI__SHIFT 0x0
#define DB_OCCLUSION_COUNT1_LOW__COUNT_LOW_MASK 0xffffffff
#define DB_OCCLUSION_COUNT1_LOW__COUNT_LOW__SHIFT 0x0
#define DB_OCCLUSION_COUNT1_HI__COUNT_HI_MASK 0x7fffffff
#define DB_OCCLUSION_COUNT1_HI__COUNT_HI__SHIFT 0x0
#define DB_OCCLUSION_COUNT2_LOW__COUNT_LOW_MASK 0xffffffff
#define DB_OCCLUSION_COUNT2_LOW__COUNT_LOW__SHIFT 0x0
#define DB_OCCLUSION_COUNT2_HI__COUNT_HI_MASK 0x7fffffff
#define DB_OCCLUSION_COUNT2_HI__COUNT_HI__SHIFT 0x0
#define DB_OCCLUSION_COUNT3_LOW__COUNT_LOW_MASK 0xffffffff
#define DB_OCCLUSION_COUNT3_LOW__COUNT_LOW__SHIFT 0x0
#define DB_OCCLUSION_COUNT3_HI__COUNT_HI_MASK 0x7fffffff
#define DB_OCCLUSION_COUNT3_HI__COUNT_HI__SHIFT 0x0
#define CC_RB_REDUNDANCY__FAILED_RB0_MASK 0xf00
#define CC_RB_REDUNDANCY__FAILED_RB0__SHIFT 0x8
#define CC_RB_REDUNDANCY__EN_REDUNDANCY0_MASK 0x1000
#define CC_RB_REDUNDANCY__EN_REDUNDANCY0__SHIFT 0xc
#define CC_RB_REDUNDANCY__FAILED_RB1_MASK 0xf0000
#define CC_RB_REDUNDANCY__FAILED_RB1__SHIFT 0x10
#define CC_RB_REDUNDANCY__EN_REDUNDANCY1_MASK 0x100000
#define CC_RB_REDUNDANCY__EN_REDUNDANCY1__SHIFT 0x14
#define CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK 0xff0000
#define CC_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT 0x10
#define GC_USER_RB_REDUNDANCY__FAILED_RB0_MASK 0xf00
#define GC_USER_RB_REDUNDANCY__FAILED_RB0__SHIFT 0x8
#define GC_USER_RB_REDUNDANCY__EN_REDUNDANCY0_MASK 0x1000
#define GC_USER_RB_REDUNDANCY__EN_REDUNDANCY0__SHIFT 0xc
#define GC_USER_RB_REDUNDANCY__FAILED_RB1_MASK 0xf0000
#define GC_USER_RB_REDUNDANCY__FAILED_RB1__SHIFT 0x10
#define GC_USER_RB_REDUNDANCY__EN_REDUNDANCY1_MASK 0x100000
#define GC_USER_RB_REDUNDANCY__EN_REDUNDANCY1__SHIFT 0x14
#define GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK 0xff0000
#define GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT 0x10
#define GB_ADDR_CONFIG__NUM_PIPES_MASK 0x7
#define GB_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0
#define GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x70
#define GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4
#define GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x700
#define GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8
#define GB_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x3000
#define GB_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0xc
#define GB_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x70000
#define GB_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10
#define GB_ADDR_CONFIG__NUM_GPUS_MASK 0x700000
#define GB_ADDR_CONFIG__NUM_GPUS__SHIFT 0x14
#define GB_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x3000000
#define GB_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x18
#define GB_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000
#define GB_ADDR_CONFIG__ROW_SIZE__SHIFT 0x1c
#define GB_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000
#define GB_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x1e
#define GB_BACKEND_MAP__BACKEND_MAP_MASK 0xffffffff
#define GB_BACKEND_MAP__BACKEND_MAP__SHIFT 0x0
#define GB_GPU_ID__GPU_ID_MASK 0xf
#define GB_GPU_ID__GPU_ID__SHIFT 0x0
#define CC_RB_DAISY_CHAIN__RB_0_MASK 0xf
#define CC_RB_DAISY_CHAIN__RB_0__SHIFT 0x0
#define CC_RB_DAISY_CHAIN__RB_1_MASK 0xf0
#define CC_RB_DAISY_CHAIN__RB_1__SHIFT 0x4
#define CC_RB_DAISY_CHAIN__RB_2_MASK 0xf00
#define CC_RB_DAISY_CHAIN__RB_2__SHIFT 0x8
#define CC_RB_DAISY_CHAIN__RB_3_MASK 0xf000
#define CC_RB_DAISY_CHAIN__RB_3__SHIFT 0xc
#define CC_RB_DAISY_CHAIN__RB_4_MASK 0xf0000
#define CC_RB_DAISY_CHAIN__RB_4__SHIFT 0x10
#define CC_RB_DAISY_CHAIN__RB_5_MASK 0xf00000
#define CC_RB_DAISY_CHAIN__RB_5__SHIFT 0x14
#define CC_RB_DAISY_CHAIN__RB_6_MASK 0xf000000
#define CC_RB_DAISY_CHAIN__RB_6__SHIFT 0x18
#define CC_RB_DAISY_CHAIN__RB_7_MASK 0xf0000000
#define CC_RB_DAISY_CHAIN__RB_7__SHIFT 0x1c
#define GB_TILE_MODE0__ARRAY_MODE_MASK 0x3c
#define GB_TILE_MODE0__ARRAY_MODE__SHIFT 0x2
#define GB_TILE_MODE0__PIPE_CONFIG_MASK 0x7c0
#define GB_TILE_MODE0__PIPE_CONFIG__SHIFT 0x6
#define GB_TILE_MODE0__TILE_SPLIT_MASK 0x3800
#define GB_TILE_MODE0__TILE_SPLIT__SHIFT 0xb
#define GB_TILE_MODE0__MICRO_TILE_MODE_NEW_MASK 0x1c00000
#define GB_TILE_MODE0__MICRO_TILE_MODE_NEW__SHIFT 0x16
#define GB_TILE_MODE0__SAMPLE_SPLIT_MASK 0x6000000
#define GB_TILE_MODE0__SAMPLE_SPLIT__SHIFT 0x19
#define GB_TILE_MODE1__ARRAY_MODE_MASK 0x3c
#define GB_TILE_MODE1__ARRAY_MODE__SHIFT 0x2
#define GB_TILE_MODE1__PIPE_CONFIG_MASK 0x7c0
#define GB_TILE_MODE1__PIPE_CONFIG__SHIFT 0x6
#define GB_TILE_MODE1__TILE_SPLIT_MASK 0x3800
#define GB_TILE_MODE1__TILE_SPLIT__SHIFT 0xb
#define GB_TILE_MODE1__MICRO_TILE_MODE_NEW_MASK 0x1c00000
#define GB_TILE_MODE1__MICRO_TILE_MODE_NEW__SHIFT 0x16
#define GB_TILE_MODE1__SAMPLE_SPLIT_MASK 0x6000000
#define GB_TILE_MODE1__SAMPLE_SPLIT__SHIFT 0x19
#define GB_TILE_MODE2__ARRAY_MODE_MASK 0x3c
#define GB_TILE_MODE2__ARRAY_MODE__SHIFT 0x2
#define GB_TILE_MODE2__PIPE_CONFIG_MASK 0x7c0
#define GB_TILE_MODE2__PIPE_CONFIG__SHIFT 0x6
#define GB_TILE_MODE2__TILE_SPLIT_MASK 0x3800
#define GB_TILE_MODE2__TILE_SPLIT__SHIFT 0xb
#define GB_TILE_MODE2__MICRO_TILE_MODE_NEW_MASK 0x1c00000
#define GB_TILE_MODE2__MICRO_TILE_MODE_NEW__SHIFT 0x16
#define GB_TILE_MODE2__SAMPLE_SPLIT_MASK 0x6000000
#define GB_TILE_MODE2__SAMPLE_SPLIT__SHIFT 0x19
#define GB_TILE_MODE3__ARRAY_MODE_MASK 0x3c
#define GB_TILE_MODE3__ARRAY_MODE__SHIFT 0x2
#define GB_TILE_MODE3__PIPE_CONFIG_MASK 0x7c0
#define GB_TILE_MODE3__PIPE_CONFIG__SHIFT 0x6
#define GB_TILE_MODE3__TILE_SPLIT_MASK 0x3800
#define GB_TILE_MODE3__TILE_SPLIT__SHIFT 0xb
#define GB_TILE_MODE3__MICRO_TILE_MODE_NEW_MASK 0x1c00000
#define GB_TILE_MODE3__MICRO_TILE_MODE_NEW__SHIFT 0x16
#define GB_TILE_MODE3__SAMPLE_SPLIT_MASK 0x6000000
#define GB_TILE_MODE3__SAMPLE_SPLIT__SHIFT 0x19
#define GB_TILE_MODE4__ARRAY_MODE_MASK 0x3c
#define GB_TILE_MODE4__ARRAY_MODE__SHIFT 0x2
#define GB_TILE_MODE4__PIPE_CONFIG_MASK 0x7c0
#define GB_TILE_MODE4__PIPE_CONFIG__SHIFT 0x6
#define GB_TILE_MODE4__TILE_SPLIT_MASK 0x3800
#define GB_TILE_MODE4__TILE_SPLIT__SHIFT 0xb
#define GB_TILE_MODE4__MICRO_TILE_MODE_NEW_MASK 0x1c00000
#define GB_TILE_MODE4__MICRO_TILE_MODE_NEW__SHIFT 0x16
#define GB_TILE_MODE4__SAMPLE_SPLIT_MASK 0x6000000
#define GB_TILE_MODE4__SAMPLE_SPLIT__SHIFT 0x19
#define GB_TILE_MODE5__ARRAY_MODE_MASK 0x3c
#define GB_TILE_MODE5__ARRAY_MODE__SHIFT 0x2
#define GB_TILE_MODE5__PIPE_CONFIG_MASK 0x7c0
#define GB_TILE_MODE5__PIPE_CONFIG__SHIFT 0x6
#define GB_TILE_MODE5__TILE_SPLIT_MASK 0x3800
#define GB_TILE_MODE5__TILE_SPLIT__SHIFT 0xb
#define GB_TILE_MODE5__MICRO_TILE_MODE_NEW_MASK 0x1c00000
#define GB_TILE_MODE5__MICRO_TILE_MODE_NEW__SHIFT 0x16
#define GB_TILE_MODE5__SAMPLE_SPLIT_MASK 0x6000000
#define GB_TILE_MODE5__SAMPLE_SPLIT__SHIFT 0x19
#define GB_TILE_MODE6__ARRAY_MODE_MASK 0x3c
#define GB_TILE_MODE6__ARRAY_MODE__SHIFT 0x2
#define GB_TILE_MODE6__PIPE_CONFIG_MASK 0x7c0
#define GB_TILE_MODE6__PIPE_CONFIG__SHIFT 0x6
#define GB_TILE_MODE6__TILE_SPLIT_MASK 0x3800
#define GB_TILE_MODE6__TILE_SPLIT__SHIFT 0xb
#define GB_TILE_MODE6__MICRO_TILE_MODE_NEW_MASK 0x1c00000
#define GB_TILE_MODE6__MICRO_TILE_MODE_NEW__SHIFT 0x16
#define GB_TILE_MODE6__SAMPLE_SPLIT_MASK 0x6000000
#define GB_TILE_MODE6__SAMPLE_SPLIT__SHIFT 0x19
#define GB_TILE_MODE7__ARRAY_MODE_MASK 0x3c
#define GB_TILE_MODE7__ARRAY_MODE__SHIFT 0x2
#define GB_TILE_MODE7__PIPE_CONFIG_MASK 0x7c0
#define GB_TILE_MODE7__PIPE_CONFIG__SHIFT 0x6
#define GB_TILE_MODE7__TILE_SPLIT_MASK 0x3800
#define GB_TILE_MODE7__TILE_SPLIT__SHIFT 0xb
#define GB_TILE_MODE7__MICRO_TILE_MODE_NEW_MASK 0x1c00000
#define GB_TILE_MODE7__MICRO_TILE_MODE_NEW__SHIFT 0x16
#define GB_TILE_MODE7__SAMPLE_SPLIT_MASK 0x6000000
#define GB_TILE_MODE7__SAMPLE_SPLIT__SHIFT 0x19
#define GB_TILE_MODE8__ARRAY_MODE_MASK 0x3c
#define GB_TILE_MODE8__ARRAY_MODE__SHIFT 0x2
#define GB_TILE_MODE8__PIPE_CONFIG_MASK 0x7c0
#define GB_TILE_MODE8__PIPE_CONFIG__SHIFT 0x6
#define GB_TILE_MODE8__TILE_SPLIT_MASK 0x3800
#define GB_TILE_MODE8__TILE_SPLIT__SHIFT 0xb
#define GB_TILE_MODE8__MICRO_TILE_MODE_NEW_MASK 0x1c00000
#define GB_TILE_MODE8__MICRO_TILE_MODE_NEW__SHIFT 0x16
#define GB_TILE_MODE8__SAMPLE_SPLIT_MASK 0x6000000
#define GB_TILE_MODE8__SAMPLE_SPLIT__SHIFT 0x19
#define GB_TILE_MODE9__ARRAY_MODE_MASK 0x3c
#define GB_TILE_MODE9__ARRAY_MODE__SHIFT 0x2
#define GB_TILE_MODE9__PIPE_CONFIG_MASK 0x7c0
#define GB_TILE_MODE9__PIPE_CONFIG__SHIFT 0x6
#define GB_TILE_MODE9__TILE_SPLIT_MASK 0x3800
#define GB_TILE_MODE9__TILE_SPLIT__SHIFT 0xb
#define GB_TILE_MODE9__MICRO_TILE_MODE_NEW_MASK 0x1c00000
#define GB_TILE_MODE9__MICRO_TILE_MODE_NEW__SHIFT 0x16
#define GB_TILE_MODE9__SAMPLE_SPLIT_MASK 0x6000000
#define GB_TILE_MODE9__SAMPLE_SPLIT__SHIFT 0x19
#define GB_TILE_MODE10__ARRAY_MODE_MASK 0x3c
#define GB_TILE_MODE10__ARRAY_MODE__SHIFT 0x2
#define GB_TILE_MODE10__PIPE_CONFIG_MASK 0x7c0
#define GB_TILE_MODE10__PIPE_CONFIG__SHIFT 0x6
#define GB_TILE_MODE10__TILE_SPLIT_MASK 0x3800
#define GB_TILE_MODE10__TILE_SPLIT__SHIFT 0xb
#define GB_TILE_MODE10__MICRO_TILE_MODE_NEW_MASK 0x1c00000
#define GB_TILE_MODE10__MICRO_TILE_MODE_NEW__SHIFT 0x16
#define GB_TILE_MODE10__SAMPLE_SPLIT_MASK 0x6000000
#define GB_TILE_MODE10__SAMPLE_SPLIT__SHIFT 0x19
#define GB_TILE_MODE11__ARRAY_MODE_MASK 0x3c
#define GB_TILE_MODE11__ARRAY_MODE__SHIFT 0x2
#define GB_TILE_MODE11__PIPE_CONFIG_MASK 0x7c0
#define GB_TILE_MODE11__PIPE_CONFIG__SHIFT 0x6
#define GB_TILE_MODE11__TILE_SPLIT_MASK 0x3800
#define GB_TILE_MODE11__TILE_SPLIT__SHIFT 0xb
#define GB_TILE_MODE11__MICRO_TILE_MODE_NEW_MASK 0x1c00000
#define GB_TILE_MODE11__MICRO_TILE_MODE_NEW__SHIFT 0x16
#define GB_TILE_MODE11__SAMPLE_SPLIT_MASK 0x6000000
#define GB_TILE_MODE11__SAMPLE_SPLIT__SHIFT 0x19
#define GB_TILE_MODE12__ARRAY_MODE_MASK 0x3c
#define GB_TILE_MODE12__ARRAY_MODE__SHIFT 0x2
#define GB_TILE_MODE12__PIPE_CONFIG_MASK 0x7c0
#define GB_TILE_MODE12__PIPE_CONFIG__SHIFT 0x6
#define GB_TILE_MODE12__TILE_SPLIT_MASK 0x3800
#define GB_TILE_MODE12__TILE_SPLIT__SHIFT 0xb
#define GB_TILE_MODE12__MICRO_TILE_MODE_NEW_MASK 0x1c00000
#define GB_TILE_MODE12__MICRO_TILE_MODE_NEW__SHIFT 0x16
#define GB_TILE_MODE12__SAMPLE_SPLIT_MASK 0x6000000
#define GB_TILE_MODE12__SAMPLE_SPLIT__SHIFT 0x19
#define GB_TILE_MODE13__ARRAY_MODE_MASK 0x3c
#define GB_TILE_MODE13__ARRAY_MODE__SHIFT 0x2
#define GB_TILE_MODE13__PIPE_CONFIG_MASK 0x7c0
#define GB_TILE_MODE13__PIPE_CONFIG__SHIFT 0x6
#define GB_TILE_MODE13__TILE_SPLIT_MASK 0x3800
#define GB_TILE_MODE13__TILE_SPLIT__SHIFT 0xb
#define GB_TILE_MODE13__MICRO_TILE_MODE_NEW_MASK 0x1c00000
#define GB_TILE_MODE13__MICRO_TILE_MODE_NEW__SHIFT 0x16
#define GB_TILE_MODE13__SAMPLE_SPLIT_MASK 0x6000000
#define GB_TILE_MODE13__SAMPLE_SPLIT__SHIFT 0x19
#define GB_TILE_MODE14__ARRAY_MODE_MASK 0x3c
#define GB_TILE_MODE14__ARRAY_MODE__SHIFT 0x2
#define GB_TILE_MODE14__PIPE_CONFIG_MASK 0x7c0
#define GB_TILE_MODE14__PIPE_CONFIG__SHIFT 0x6
#define GB_TILE_MODE14__TILE_SPLIT_MASK 0x3800
#define GB_TILE_MODE14__TILE_SPLIT__SHIFT 0xb
#define GB_TILE_MODE14__MICRO_TILE_MODE_NEW_MASK 0x1c00000
#define GB_TILE_MODE14__MICRO_TILE_MODE_NEW__SHIFT 0x16
#define GB_TILE_MODE14__SAMPLE_SPLIT_MASK 0x6000000
#define GB_TILE_MODE14__SAMPLE_SPLIT__SHIFT 0x19
#define GB_TILE_MODE15__ARRAY_MODE_MASK 0x3c
#define GB_TILE_MODE15__ARRAY_MODE__SHIFT 0x2
#define GB_TILE_MODE15__PIPE_CONFIG_MASK 0x7c0
#define GB_TILE_MODE15__PIPE_CONFIG__SHIFT 0x6
#define GB_TILE_MODE15__TILE_SPLIT_MASK 0x3800
#define GB_TILE_MODE15__TILE_SPLIT__SHIFT 0xb
#define GB_TILE_MODE15__MICRO_TILE_MODE_NEW_MASK 0x1c00000
#define GB_TILE_MODE15__MICRO_TILE_MODE_NEW__SHIFT 0x16
#define GB_TILE_MODE15__SAMPLE_SPLIT_MASK 0x6000000
#define GB_TILE_MODE15__SAMPLE_SPLIT__SHIFT 0x19
#define GB_TILE_MODE16__ARRAY_MODE_MASK 0x3c
#define GB_TILE_MODE16__ARRAY_MODE__SHIFT 0x2
#define GB_TILE_MODE16__PIPE_CONFIG_MASK 0x7c0
#define GB_TILE_MODE16__PIPE_CONFIG__SHIFT 0x6
#define GB_TILE_MODE16__TILE_SPLIT_MASK 0x3800
#define GB_TILE_MODE16__TILE_SPLIT__SHIFT 0xb
#define GB_TILE_MODE16__MICRO_TILE_MODE_NEW_MASK 0x1c00000
#define GB_TILE_MODE16__MICRO_TILE_MODE_NEW__SHIFT 0x16
#define GB_TILE_MODE16__SAMPLE_SPLIT_MASK 0x6000000
#define GB_TILE_MODE16__SAMPLE_SPLIT__SHIFT 0x19
#define GB_TILE_MODE17__ARRAY_MODE_MASK 0x3c
#define GB_TILE_MODE17__ARRAY_MODE__SHIFT 0x2
#define GB_TILE_MODE17__PIPE_CONFIG_MASK 0x7c0
#define GB_TILE_MODE17__PIPE_CONFIG__SHIFT 0x6
#define GB_TILE_MODE17__TILE_SPLIT_MASK 0x3800
#define GB_TILE_MODE17__TILE_SPLIT__SHIFT 0xb
#define GB_TILE_MODE17__MICRO_TILE_MODE_NEW_MASK 0x1c00000
#define GB_TILE_MODE17__MICRO_TILE_MODE_NEW__SHIFT 0x16
#define GB_TILE_MODE17__SAMPLE_SPLIT_MASK 0x6000000
#define GB_TILE_MODE17__SAMPLE_SPLIT__SHIFT 0x19
#define GB_TILE_MODE18__ARRAY_MODE_MASK 0x3c
#define GB_TILE_MODE18__ARRAY_MODE__SHIFT 0x2
#define GB_TILE_MODE18__PIPE_CONFIG_MASK 0x7c0
#define GB_TILE_MODE18__PIPE_CONFIG__SHIFT 0x6
#define GB_TILE_MODE18__TILE_SPLIT_MASK 0x3800
#define GB_TILE_MODE18__TILE_SPLIT__SHIFT 0xb
#define GB_TILE_MODE18__MICRO_TILE_MODE_NEW_MASK 0x1c00000
#define GB_TILE_MODE18__MICRO_TILE_MODE_NEW__SHIFT 0x16
#define GB_TILE_MODE18__SAMPLE_SPLIT_MASK 0x6000000
#define GB_TILE_MODE18__SAMPLE_SPLIT__SHIFT 0x19
#define GB_TILE_MODE19__ARRAY_MODE_MASK 0x3c
#define GB_TILE_MODE19__ARRAY_MODE__SHIFT 0x2
#define GB_TILE_MODE19__PIPE_CONFIG_MASK 0x7c0
#define GB_TILE_MODE19__PIPE_CONFIG__SHIFT 0x6
#define GB_TILE_MODE19__TILE_SPLIT_MASK 0x3800
#define GB_TILE_MODE19__TILE_SPLIT__SHIFT 0xb
#define GB_TILE_MODE19__MICRO_TILE_MODE_NEW_MASK 0x1c00000
#define GB_TILE_MODE19__MICRO_TILE_MODE_NEW__SHIFT 0x16
#define GB_TILE_MODE19__SAMPLE_SPLIT_MASK 0x6000000
#define GB_TILE_MODE19__SAMPLE_SPLIT__SHIFT 0x19
#define GB_TILE_MODE20__ARRAY_MODE_MASK 0x3c
#define GB_TILE_MODE20__ARRAY_MODE__SHIFT 0x2
#define GB_TILE_MODE20__PIPE_CONFIG_MASK 0x7c0
#define GB_TILE_MODE20__PIPE_CONFIG__SHIFT 0x6
#define GB_TILE_MODE20__TILE_SPLIT_MASK 0x3800
#define GB_TILE_MODE20__TILE_SPLIT__SHIFT 0xb
#define GB_TILE_MODE20__MICRO_TILE_MODE_NEW_MASK 0x1c00000
#define GB_TILE_MODE20__MICRO_TILE_MODE_NEW__SHIFT 0x16
#define GB_TILE_MODE20__SAMPLE_SPLIT_MASK 0x6000000
#define GB_TILE_MODE20__SAMPLE_SPLIT__SHIFT 0x19
#define GB_TILE_MODE21__ARRAY_MODE_MASK 0x3c
#define GB_TILE_MODE21__ARRAY_MODE__SHIFT 0x2
#define GB_TILE_MODE21__PIPE_CONFIG_MASK 0x7c0
#define GB_TILE_MODE21__PIPE_CONFIG__SHIFT 0x6
#define GB_TILE_MODE21__TILE_SPLIT_MASK 0x3800
#define GB_TILE_MODE21__TILE_SPLIT__SHIFT 0xb
#define GB_TILE_MODE21__MICRO_TILE_MODE_NEW_MASK 0x1c00000
#define GB_TILE_MODE21__MICRO_TILE_MODE_NEW__SHIFT 0x16
#define GB_TILE_MODE21__SAMPLE_SPLIT_MASK 0x6000000
#define GB_TILE_MODE21__SAMPLE_SPLIT__SHIFT 0x19
#define GB_TILE_MODE22__ARRAY_MODE_MASK 0x3c
#define GB_TILE_MODE22__ARRAY_MODE__SHIFT 0x2
#define GB_TILE_MODE22__PIPE_CONFIG_MASK 0x7c0
#define GB_TILE_MODE22__PIPE_CONFIG__SHIFT 0x6
#define GB_TILE_MODE22__TILE_SPLIT_MASK 0x3800
#define GB_TILE_MODE22__TILE_SPLIT__SHIFT 0xb
#define GB_TILE_MODE22__MICRO_TILE_MODE_NEW_MASK 0x1c00000
#define GB_TILE_MODE22__MICRO_TILE_MODE_NEW__SHIFT 0x16
#define GB_TILE_MODE22__SAMPLE_SPLIT_MASK 0x6000000
#define GB_TILE_MODE22__SAMPLE_SPLIT__SHIFT 0x19
#define GB_TILE_MODE23__ARRAY_MODE_MASK 0x3c
#define GB_TILE_MODE23__ARRAY_MODE__SHIFT 0x2
#define GB_TILE_MODE23__PIPE_CONFIG_MASK 0x7c0
#define GB_TILE_MODE23__PIPE_CONFIG__SHIFT 0x6
#define GB_TILE_MODE23__TILE_SPLIT_MASK 0x3800
#define GB_TILE_MODE23__TILE_SPLIT__SHIFT 0xb
#define GB_TILE_MODE23__MICRO_TILE_MODE_NEW_MASK 0x1c00000
#define GB_TILE_MODE23__MICRO_TILE_MODE_NEW__SHIFT 0x16
#define GB_TILE_MODE23__SAMPLE_SPLIT_MASK 0x6000000
#define GB_TILE_MODE23__SAMPLE_SPLIT__SHIFT 0x19
#define GB_TILE_MODE24__ARRAY_MODE_MASK 0x3c
#define GB_TILE_MODE24__ARRAY_MODE__SHIFT 0x2
#define GB_TILE_MODE24__PIPE_CONFIG_MASK 0x7c0
#define GB_TILE_MODE24__PIPE_CONFIG__SHIFT 0x6
#define GB_TILE_MODE24__TILE_SPLIT_MASK 0x3800
#define GB_TILE_MODE24__TILE_SPLIT__SHIFT 0xb
#define GB_TILE_MODE24__MICRO_TILE_MODE_NEW_MASK 0x1c00000
#define GB_TILE_MODE24__MICRO_TILE_MODE_NEW__SHIFT 0x16
#define GB_TILE_MODE24__SAMPLE_SPLIT_MASK 0x6000000
#define GB_TILE_MODE24__SAMPLE_SPLIT__SHIFT 0x19
#define GB_TILE_MODE25__ARRAY_MODE_MASK 0x3c
#define GB_TILE_MODE25__ARRAY_MODE__SHIFT 0x2
#define GB_TILE_MODE25__PIPE_CONFIG_MASK 0x7c0
#define GB_TILE_MODE25__PIPE_CONFIG__SHIFT 0x6
#define GB_TILE_MODE25__TILE_SPLIT_MASK 0x3800
#define GB_TILE_MODE25__TILE_SPLIT__SHIFT 0xb
#define GB_TILE_MODE25__MICRO_TILE_MODE_NEW_MASK 0x1c00000
#define GB_TILE_MODE25__MICRO_TILE_MODE_NEW__SHIFT 0x16
#define GB_TILE_MODE25__SAMPLE_SPLIT_MASK 0x6000000
#define GB_TILE_MODE25__SAMPLE_SPLIT__SHIFT 0x19
#define GB_TILE_MODE26__ARRAY_MODE_MASK 0x3c
#define GB_TILE_MODE26__ARRAY_MODE__SHIFT 0x2
#define GB_TILE_MODE26__PIPE_CONFIG_MASK 0x7c0
#define GB_TILE_MODE26__PIPE_CONFIG__SHIFT 0x6
#define GB_TILE_MODE26__TILE_SPLIT_MASK 0x3800
#define GB_TILE_MODE26__TILE_SPLIT__SHIFT 0xb
#define GB_TILE_MODE26__MICRO_TILE_MODE_NEW_MASK 0x1c00000
#define GB_TILE_MODE26__MICRO_TILE_MODE_NEW__SHIFT 0x16
#define GB_TILE_MODE26__SAMPLE_SPLIT_MASK 0x6000000
#define GB_TILE_MODE26__SAMPLE_SPLIT__SHIFT 0x19
#define GB_TILE_MODE27__ARRAY_MODE_MASK 0x3c
#define GB_TILE_MODE27__ARRAY_MODE__SHIFT 0x2
#define GB_TILE_MODE27__PIPE_CONFIG_MASK 0x7c0
#define GB_TILE_MODE27__PIPE_CONFIG__SHIFT 0x6
#define GB_TILE_MODE27__TILE_SPLIT_MASK 0x3800
#define GB_TILE_MODE27__TILE_SPLIT__SHIFT 0xb
#define GB_TILE_MODE27__MICRO_TILE_MODE_NEW_MASK 0x1c00000
#define GB_TILE_MODE27__MICRO_TILE_MODE_NEW__SHIFT 0x16
#define GB_TILE_MODE27__SAMPLE_SPLIT_MASK 0x6000000
#define GB_TILE_MODE27__SAMPLE_SPLIT__SHIFT 0x19
#define GB_TILE_MODE28__ARRAY_MODE_MASK 0x3c
#define GB_TILE_MODE28__ARRAY_MODE__SHIFT 0x2
#define GB_TILE_MODE28__PIPE_CONFIG_MASK 0x7c0
#define GB_TILE_MODE28__PIPE_CONFIG__SHIFT 0x6
#define GB_TILE_MODE28__TILE_SPLIT_MASK 0x3800
#define GB_TILE_MODE28__TILE_SPLIT__SHIFT 0xb
#define GB_TILE_MODE28__MICRO_TILE_MODE_NEW_MASK 0x1c00000
#define GB_TILE_MODE28__MICRO_TILE_MODE_NEW__SHIFT 0x16
#define GB_TILE_MODE28__SAMPLE_SPLIT_MASK 0x6000000
#define GB_TILE_MODE28__SAMPLE_SPLIT__SHIFT 0x19
#define GB_TILE_MODE29__ARRAY_MODE_MASK 0x3c
#define GB_TILE_MODE29__ARRAY_MODE__SHIFT 0x2
#define GB_TILE_MODE29__PIPE_CONFIG_MASK 0x7c0
#define GB_TILE_MODE29__PIPE_CONFIG__SHIFT 0x6
#define GB_TILE_MODE29__TILE_SPLIT_MASK 0x3800
#define GB_TILE_MODE29__TILE_SPLIT__SHIFT 0xb
#define GB_TILE_MODE29__MICRO_TILE_MODE_NEW_MASK 0x1c00000
#define GB_TILE_MODE29__MICRO_TILE_MODE_NEW__SHIFT 0x16
#define GB_TILE_MODE29__SAMPLE_SPLIT_MASK 0x6000000
#define GB_TILE_MODE29__SAMPLE_SPLIT__SHIFT 0x19
#define GB_TILE_MODE30__ARRAY_MODE_MASK 0x3c
#define GB_TILE_MODE30__ARRAY_MODE__SHIFT 0x2
#define GB_TILE_MODE30__PIPE_CONFIG_MASK 0x7c0
#define GB_TILE_MODE30__PIPE_CONFIG__SHIFT 0x6
#define GB_TILE_MODE30__TILE_SPLIT_MASK 0x3800
#define GB_TILE_MODE30__TILE_SPLIT__SHIFT 0xb
#define GB_TILE_MODE30__MICRO_TILE_MODE_NEW_MASK 0x1c00000
#define GB_TILE_MODE30__MICRO_TILE_MODE_NEW__SHIFT 0x16
#define GB_TILE_MODE30__SAMPLE_SPLIT_MASK 0x6000000
#define GB_TILE_MODE30__SAMPLE_SPLIT__SHIFT 0x19
#define GB_TILE_MODE31__ARRAY_MODE_MASK 0x3c
#define GB_TILE_MODE31__ARRAY_MODE__SHIFT 0x2
#define GB_TILE_MODE31__PIPE_CONFIG_MASK 0x7c0
#define GB_TILE_MODE31__PIPE_CONFIG__SHIFT 0x6
#define GB_TILE_MODE31__TILE_SPLIT_MASK 0x3800
#define GB_TILE_MODE31__TILE_SPLIT__SHIFT 0xb
#define GB_TILE_MODE31__MICRO_TILE_MODE_NEW_MASK 0x1c00000
#define GB_TILE_MODE31__MICRO_TILE_MODE_NEW__SHIFT 0x16
#define GB_TILE_MODE31__SAMPLE_SPLIT_MASK 0x6000000
#define GB_TILE_MODE31__SAMPLE_SPLIT__SHIFT 0x19
#define GB_MACROTILE_MODE0__BANK_WIDTH_MASK 0x3
#define GB_MACROTILE_MODE0__BANK_WIDTH__SHIFT 0x0
#define GB_MACROTILE_MODE0__BANK_HEIGHT_MASK 0xc
#define GB_MACROTILE_MODE0__BANK_HEIGHT__SHIFT 0x2
#define GB_MACROTILE_MODE0__MACRO_TILE_ASPECT_MASK 0x30
#define GB_MACROTILE_MODE0__MACRO_TILE_ASPECT__SHIFT 0x4
#define GB_MACROTILE_MODE0__NUM_BANKS_MASK 0xc0
#define GB_MACROTILE_MODE0__NUM_BANKS__SHIFT 0x6
#define GB_MACROTILE_MODE1__BANK_WIDTH_MASK 0x3
#define GB_MACROTILE_MODE1__BANK_WIDTH__SHIFT 0x0
#define GB_MACROTILE_MODE1__BANK_HEIGHT_MASK 0xc
#define GB_MACROTILE_MODE1__BANK_HEIGHT__SHIFT 0x2
#define GB_MACROTILE_MODE1__MACRO_TILE_ASPECT_MASK 0x30
#define GB_MACROTILE_MODE1__MACRO_TILE_ASPECT__SHIFT 0x4
#define GB_MACROTILE_MODE1__NUM_BANKS_MASK 0xc0
#define GB_MACROTILE_MODE1__NUM_BANKS__SHIFT 0x6
#define GB_MACROTILE_MODE2__BANK_WIDTH_MASK 0x3
#define GB_MACROTILE_MODE2__BANK_WIDTH__SHIFT 0x0
#define GB_MACROTILE_MODE2__BANK_HEIGHT_MASK 0xc
#define GB_MACROTILE_MODE2__BANK_HEIGHT__SHIFT 0x2
#define GB_MACROTILE_MODE2__MACRO_TILE_ASPECT_MASK 0x30
#define GB_MACROTILE_MODE2__MACRO_TILE_ASPECT__SHIFT 0x4
#define GB_MACROTILE_MODE2__NUM_BANKS_MASK 0xc0
#define GB_MACROTILE_MODE2__NUM_BANKS__SHIFT 0x6
#define GB_MACROTILE_MODE3__BANK_WIDTH_MASK 0x3
#define GB_MACROTILE_MODE3__BANK_WIDTH__SHIFT 0x0
#define GB_MACROTILE_MODE3__BANK_HEIGHT_MASK 0xc
#define GB_MACROTILE_MODE3__BANK_HEIGHT__SHIFT 0x2
#define GB_MACROTILE_MODE3__MACRO_TILE_ASPECT_MASK 0x30
#define GB_MACROTILE_MODE3__MACRO_TILE_ASPECT__SHIFT 0x4
#define GB_MACROTILE_MODE3__NUM_BANKS_MASK 0xc0
#define GB_MACROTILE_MODE3__NUM_BANKS__SHIFT 0x6
#define GB_MACROTILE_MODE4__BANK_WIDTH_MASK 0x3
#define GB_MACROTILE_MODE4__BANK_WIDTH__SHIFT 0x0
#define GB_MACROTILE_MODE4__BANK_HEIGHT_MASK 0xc
#define GB_MACROTILE_MODE4__BANK_HEIGHT__SHIFT 0x2
#define GB_MACROTILE_MODE4__MACRO_TILE_ASPECT_MASK 0x30
#define GB_MACROTILE_MODE4__MACRO_TILE_ASPECT__SHIFT 0x4
#define GB_MACROTILE_MODE4__NUM_BANKS_MASK 0xc0
#define GB_MACROTILE_MODE4__NUM_BANKS__SHIFT 0x6
#define GB_MACROTILE_MODE5__BANK_WIDTH_MASK 0x3
#define GB_MACROTILE_MODE5__BANK_WIDTH__SHIFT 0x0
#define GB_MACROTILE_MODE5__BANK_HEIGHT_MASK 0xc
#define GB_MACROTILE_MODE5__BANK_HEIGHT__SHIFT 0x2
#define GB_MACROTILE_MODE5__MACRO_TILE_ASPECT_MASK 0x30
#define GB_MACROTILE_MODE5__MACRO_TILE_ASPECT__SHIFT 0x4
#define GB_MACROTILE_MODE5__NUM_BANKS_MASK 0xc0
#define GB_MACROTILE_MODE5__NUM_BANKS__SHIFT 0x6
#define GB_MACROTILE_MODE6__BANK_WIDTH_MASK 0x3
#define GB_MACROTILE_MODE6__BANK_WIDTH__SHIFT 0x0
#define GB_MACROTILE_MODE6__BANK_HEIGHT_MASK 0xc
#define GB_MACROTILE_MODE6__BANK_HEIGHT__SHIFT 0x2
#define GB_MACROTILE_MODE6__MACRO_TILE_ASPECT_MASK 0x30
#define GB_MACROTILE_MODE6__MACRO_TILE_ASPECT__SHIFT 0x4
#define GB_MACROTILE_MODE6__NUM_BANKS_MASK 0xc0
#define GB_MACROTILE_MODE6__NUM_BANKS__SHIFT 0x6
#define GB_MACROTILE_MODE7__BANK_WIDTH_MASK 0x3
#define GB_MACROTILE_MODE7__BANK_WIDTH__SHIFT 0x0
#define GB_MACROTILE_MODE7__BANK_HEIGHT_MASK 0xc
#define GB_MACROTILE_MODE7__BANK_HEIGHT__SHIFT 0x2
#define GB_MACROTILE_MODE7__MACRO_TILE_ASPECT_MASK 0x30
#define GB_MACROTILE_MODE7__MACRO_TILE_ASPECT__SHIFT 0x4
#define GB_MACROTILE_MODE7__NUM_BANKS_MASK 0xc0
#define GB_MACROTILE_MODE7__NUM_BANKS__SHIFT 0x6
#define GB_MACROTILE_MODE8__BANK_WIDTH_MASK 0x3
#define GB_MACROTILE_MODE8__BANK_WIDTH__SHIFT 0x0
#define GB_MACROTILE_MODE8__BANK_HEIGHT_MASK 0xc
#define GB_MACROTILE_MODE8__BANK_HEIGHT__SHIFT 0x2
#define GB_MACROTILE_MODE8__MACRO_TILE_ASPECT_MASK 0x30
#define GB_MACROTILE_MODE8__MACRO_TILE_ASPECT__SHIFT 0x4
#define GB_MACROTILE_MODE8__NUM_BANKS_MASK 0xc0
#define GB_MACROTILE_MODE8__NUM_BANKS__SHIFT 0x6
#define GB_MACROTILE_MODE9__BANK_WIDTH_MASK 0x3
#define GB_MACROTILE_MODE9__BANK_WIDTH__SHIFT 0x0
#define GB_MACROTILE_MODE9__BANK_HEIGHT_MASK 0xc
#define GB_MACROTILE_MODE9__BANK_HEIGHT__SHIFT 0x2
#define GB_MACROTILE_MODE9__MACRO_TILE_ASPECT_MASK 0x30
#define GB_MACROTILE_MODE9__MACRO_TILE_ASPECT__SHIFT 0x4
#define GB_MACROTILE_MODE9__NUM_BANKS_MASK 0xc0
#define GB_MACROTILE_MODE9__NUM_BANKS__SHIFT 0x6
#define GB_MACROTILE_MODE10__BANK_WIDTH_MASK 0x3
#define GB_MACROTILE_MODE10__BANK_WIDTH__SHIFT 0x0
#define GB_MACROTILE_MODE10__BANK_HEIGHT_MASK 0xc
#define GB_MACROTILE_MODE10__BANK_HEIGHT__SHIFT 0x2
#define GB_MACROTILE_MODE10__MACRO_TILE_ASPECT_MASK 0x30
#define GB_MACROTILE_MODE10__MACRO_TILE_ASPECT__SHIFT 0x4
#define GB_MACROTILE_MODE10__NUM_BANKS_MASK 0xc0
#define GB_MACROTILE_MODE10__NUM_BANKS__SHIFT 0x6
#define GB_MACROTILE_MODE11__BANK_WIDTH_MASK 0x3
#define GB_MACROTILE_MODE11__BANK_WIDTH__SHIFT 0x0
#define GB_MACROTILE_MODE11__BANK_HEIGHT_MASK 0xc
#define GB_MACROTILE_MODE11__BANK_HEIGHT__SHIFT 0x2
#define GB_MACROTILE_MODE11__MACRO_TILE_ASPECT_MASK 0x30
#define GB_MACROTILE_MODE11__MACRO_TILE_ASPECT__SHIFT 0x4
#define GB_MACROTILE_MODE11__NUM_BANKS_MASK 0xc0
#define GB_MACROTILE_MODE11__NUM_BANKS__SHIFT 0x6
#define GB_MACROTILE_MODE12__BANK_WIDTH_MASK 0x3
#define GB_MACROTILE_MODE12__BANK_WIDTH__SHIFT 0x0
#define GB_MACROTILE_MODE12__BANK_HEIGHT_MASK 0xc
#define GB_MACROTILE_MODE12__BANK_HEIGHT__SHIFT 0x2
#define GB_MACROTILE_MODE12__MACRO_TILE_ASPECT_MASK 0x30
#define GB_MACROTILE_MODE12__MACRO_TILE_ASPECT__SHIFT 0x4
#define GB_MACROTILE_MODE12__NUM_BANKS_MASK 0xc0
#define GB_MACROTILE_MODE12__NUM_BANKS__SHIFT 0x6
#define GB_MACROTILE_MODE13__BANK_WIDTH_MASK 0x3
#define GB_MACROTILE_MODE13__BANK_WIDTH__SHIFT 0x0
#define GB_MACROTILE_MODE13__BANK_HEIGHT_MASK 0xc
#define GB_MACROTILE_MODE13__BANK_HEIGHT__SHIFT 0x2
#define GB_MACROTILE_MODE13__MACRO_TILE_ASPECT_MASK 0x30
#define GB_MACROTILE_MODE13__MACRO_TILE_ASPECT__SHIFT 0x4
#define GB_MACROTILE_MODE13__NUM_BANKS_MASK 0xc0
#define GB_MACROTILE_MODE13__NUM_BANKS__SHIFT 0x6
#define GB_MACROTILE_MODE14__BANK_WIDTH_MASK 0x3
#define GB_MACROTILE_MODE14__BANK_WIDTH__SHIFT 0x0
#define GB_MACROTILE_MODE14__BANK_HEIGHT_MASK 0xc
#define GB_MACROTILE_MODE14__BANK_HEIGHT__SHIFT 0x2
#define GB_MACROTILE_MODE14__MACRO_TILE_ASPECT_MASK 0x30
#define GB_MACROTILE_MODE14__MACRO_TILE_ASPECT__SHIFT 0x4
#define GB_MACROTILE_MODE14__NUM_BANKS_MASK 0xc0
#define GB_MACROTILE_MODE14__NUM_BANKS__SHIFT 0x6
#define GB_MACROTILE_MODE15__BANK_WIDTH_MASK 0x3
#define GB_MACROTILE_MODE15__BANK_WIDTH__SHIFT 0x0
#define GB_MACROTILE_MODE15__BANK_HEIGHT_MASK 0xc
#define GB_MACROTILE_MODE15__BANK_HEIGHT__SHIFT 0x2
#define GB_MACROTILE_MODE15__MACRO_TILE_ASPECT_MASK 0x30
#define GB_MACROTILE_MODE15__MACRO_TILE_ASPECT__SHIFT 0x4
#define GB_MACROTILE_MODE15__NUM_BANKS_MASK 0xc0
#define GB_MACROTILE_MODE15__NUM_BANKS__SHIFT 0x6
#define GB_EDC_MODE__FORCE_SEC_ON_DED_MASK 0x10000
#define GB_EDC_MODE__FORCE_SEC_ON_DED__SHIFT 0x10
#define GB_EDC_MODE__DED_MODE_MASK 0x300000
#define GB_EDC_MODE__DED_MODE__SHIFT 0x14
#define GB_EDC_MODE__PROP_FED_MASK 0x20000000
#define GB_EDC_MODE__PROP_FED__SHIFT 0x1d
#define GB_EDC_MODE__BYPASS_MASK 0x80000000
#define GB_EDC_MODE__BYPASS__SHIFT 0x1f
#define CC_GC_EDC_CONFIG__DIS_EDC_MASK 0x2
#define CC_GC_EDC_CONFIG__DIS_EDC__SHIFT 0x1
#define RAS_SIGNATURE_CONTROL__ENABLE_MASK 0x1
#define RAS_SIGNATURE_CONTROL__ENABLE__SHIFT 0x0
#define RAS_SIGNATURE_MASK__INPUT_BUS_MASK_MASK 0xffffffff
#define RAS_SIGNATURE_MASK__INPUT_BUS_MASK__SHIFT 0x0
#define RAS_SX_SIGNATURE0__SIGNATURE_MASK 0xffffffff
#define RAS_SX_SIGNATURE0__SIGNATURE__SHIFT 0x0
#define RAS_SX_SIGNATURE1__SIGNATURE_MASK 0xffffffff
#define RAS_SX_SIGNATURE1__SIGNATURE__SHIFT 0x0
#define RAS_SX_SIGNATURE2__SIGNATURE_MASK 0xffffffff
#define RAS_SX_SIGNATURE2__SIGNATURE__SHIFT 0x0
#define RAS_SX_SIGNATURE3__SIGNATURE_MASK 0xffffffff
#define RAS_SX_SIGNATURE3__SIGNATURE__SHIFT 0x0
#define RAS_DB_SIGNATURE0__SIGNATURE_MASK 0xffffffff
#define RAS_DB_SIGNATURE0__SIGNATURE__SHIFT 0x0
#define RAS_PA_SIGNATURE0__SIGNATURE_MASK 0xffffffff
#define RAS_PA_SIGNATURE0__SIGNATURE__SHIFT 0x0
#define RAS_VGT_SIGNATURE0__SIGNATURE_MASK 0xffffffff
#define RAS_VGT_SIGNATURE0__SIGNATURE__SHIFT 0x0
#define RAS_SQ_SIGNATURE0__SIGNATURE_MASK 0xffffffff
#define RAS_SQ_SIGNATURE0__SIGNATURE__SHIFT 0x0
#define RAS_SC_SIGNATURE0__SIGNATURE_MASK 0xffffffff
#define RAS_SC_SIGNATURE0__SIGNATURE__SHIFT 0x0
#define RAS_SC_SIGNATURE1__SIGNATURE_MASK 0xffffffff
#define RAS_SC_SIGNATURE1__SIGNATURE__SHIFT 0x0
#define RAS_SC_SIGNATURE2__SIGNATURE_MASK 0xffffffff
#define RAS_SC_SIGNATURE2__SIGNATURE__SHIFT 0x0
#define RAS_SC_SIGNATURE3__SIGNATURE_MASK 0xffffffff
#define RAS_SC_SIGNATURE3__SIGNATURE__SHIFT 0x0
#define RAS_SC_SIGNATURE4__SIGNATURE_MASK 0xffffffff
#define RAS_SC_SIGNATURE4__SIGNATURE__SHIFT 0x0
#define RAS_SC_SIGNATURE5__SIGNATURE_MASK 0xffffffff
#define RAS_SC_SIGNATURE5__SIGNATURE__SHIFT 0x0
#define RAS_SC_SIGNATURE6__SIGNATURE_MASK 0xffffffff
#define RAS_SC_SIGNATURE6__SIGNATURE__SHIFT 0x0
#define RAS_SC_SIGNATURE7__SIGNATURE_MASK 0xffffffff
#define RAS_SC_SIGNATURE7__SIGNATURE__SHIFT 0x0
#define RAS_IA_SIGNATURE0__SIGNATURE_MASK 0xffffffff
#define RAS_IA_SIGNATURE0__SIGNATURE__SHIFT 0x0
#define RAS_IA_SIGNATURE1__SIGNATURE_MASK 0xffffffff
#define RAS_IA_SIGNATURE1__SIGNATURE__SHIFT 0x0
#define RAS_SPI_SIGNATURE0__SIGNATURE_MASK 0xffffffff
#define RAS_SPI_SIGNATURE0__SIGNATURE__SHIFT 0x0
#define RAS_SPI_SIGNATURE1__SIGNATURE_MASK 0xffffffff
#define RAS_SPI_SIGNATURE1__SIGNATURE__SHIFT 0x0
#define RAS_TA_SIGNATURE0__SIGNATURE_MASK 0xffffffff
#define RAS_TA_SIGNATURE0__SIGNATURE__SHIFT 0x0
#define RAS_TD_SIGNATURE0__SIGNATURE_MASK 0xffffffff
#define RAS_TD_SIGNATURE0__SIGNATURE__SHIFT 0x0
#define RAS_CB_SIGNATURE0__SIGNATURE_MASK 0xffffffff
#define RAS_CB_SIGNATURE0__SIGNATURE__SHIFT 0x0
#define RAS_BCI_SIGNATURE0__SIGNATURE_MASK 0xffffffff
#define RAS_BCI_SIGNATURE0__SIGNATURE__SHIFT 0x0
#define RAS_BCI_SIGNATURE1__SIGNATURE_MASK 0xffffffff
#define RAS_BCI_SIGNATURE1__SIGNATURE__SHIFT 0x0
#define RAS_TA_SIGNATURE1__SIGNATURE_MASK 0xffffffff
#define RAS_TA_SIGNATURE1__SIGNATURE__SHIFT 0x0
#define GRBM_HYP_CAM_INDEX__CAM_INDEX_MASK 0x7
#define GRBM_HYP_CAM_INDEX__CAM_INDEX__SHIFT 0x0
#define GRBM_CAM_INDEX__CAM_INDEX_MASK 0x7
#define GRBM_CAM_INDEX__CAM_INDEX__SHIFT 0x0
#define GRBM_HYP_CAM_DATA__CAM_ADDR_MASK 0xffff
#define GRBM_HYP_CAM_DATA__CAM_ADDR__SHIFT 0x0
#define GRBM_HYP_CAM_DATA__CAM_REMAPADDR_MASK 0xffff0000
#define GRBM_HYP_CAM_DATA__CAM_REMAPADDR__SHIFT 0x10
#define GRBM_CAM_DATA__CAM_ADDR_MASK 0xffff
#define GRBM_CAM_DATA__CAM_ADDR__SHIFT 0x0
#define GRBM_CAM_DATA__CAM_REMAPADDR_MASK 0xffff0000
#define GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT 0x10
#define GRBM_CNTL__READ_TIMEOUT_MASK 0xff
#define GRBM_CNTL__READ_TIMEOUT__SHIFT 0x0
#define GRBM_CNTL__REPORT_LAST_RDERR_MASK 0x80000000
#define GRBM_CNTL__REPORT_LAST_RDERR__SHIFT 0x1f
#define GRBM_SKEW_CNTL__SKEW_TOP_THRESHOLD_MASK 0x3f
#define GRBM_SKEW_CNTL__SKEW_TOP_THRESHOLD__SHIFT 0x0
#define GRBM_SKEW_CNTL__SKEW_COUNT_MASK 0xfc0
#define GRBM_SKEW_CNTL__SKEW_COUNT__SHIFT 0x6
#define GRBM_PWR_CNTL__ALL_REQ_TYPE_MASK 0x3
#define GRBM_PWR_CNTL__ALL_REQ_TYPE__SHIFT 0x0
#define GRBM_PWR_CNTL__GFX_REQ_TYPE_MASK 0xc
#define GRBM_PWR_CNTL__GFX_REQ_TYPE__SHIFT 0x2
#define GRBM_PWR_CNTL__ALL_RSP_TYPE_MASK 0x30
#define GRBM_PWR_CNTL__ALL_RSP_TYPE__SHIFT 0x4
#define GRBM_PWR_CNTL__GFX_RSP_TYPE_MASK 0xc0
#define GRBM_PWR_CNTL__GFX_RSP_TYPE__SHIFT 0x6
#define GRBM_PWR_CNTL__GFX_REQ_EN_MASK 0x4000
#define GRBM_PWR_CNTL__GFX_REQ_EN__SHIFT 0xe
#define GRBM_PWR_CNTL__ALL_REQ_EN_MASK 0x8000
#define GRBM_PWR_CNTL__ALL_REQ_EN__SHIFT 0xf
#define GRBM_STATUS__ME0PIPE0_CMDFIFO_AVAIL_MASK 0xf
#define GRBM_STATUS__ME0PIPE0_CMDFIFO_AVAIL__SHIFT 0x0
#define GRBM_STATUS__SRBM_RQ_PENDING_MASK 0x20
#define GRBM_STATUS__SRBM_RQ_PENDING__SHIFT 0x5
#define GRBM_STATUS__ME0PIPE0_CF_RQ_PENDING_MASK 0x80
#define GRBM_STATUS__ME0PIPE0_CF_RQ_PENDING__SHIFT 0x7
#define GRBM_STATUS__ME0PIPE0_PF_RQ_PENDING_MASK 0x100
#define GRBM_STATUS__ME0PIPE0_PF_RQ_PENDING__SHIFT 0x8
#define GRBM_STATUS__GDS_DMA_RQ_PENDING_MASK 0x200
#define GRBM_STATUS__GDS_DMA_RQ_PENDING__SHIFT 0x9
#define GRBM_STATUS__DB_CLEAN_MASK 0x1000
#define GRBM_STATUS__DB_CLEAN__SHIFT 0xc
#define GRBM_STATUS__CB_CLEAN_MASK 0x2000
#define GRBM_STATUS__CB_CLEAN__SHIFT 0xd
#define GRBM_STATUS__TA_BUSY_MASK 0x4000
#define GRBM_STATUS__TA_BUSY__SHIFT 0xe
#define GRBM_STATUS__GDS_BUSY_MASK 0x8000
#define GRBM_STATUS__GDS_BUSY__SHIFT 0xf
#define GRBM_STATUS__WD_BUSY_NO_DMA_MASK 0x10000
#define GRBM_STATUS__WD_BUSY_NO_DMA__SHIFT 0x10
#define GRBM_STATUS__VGT_BUSY_MASK 0x20000
#define GRBM_STATUS__VGT_BUSY__SHIFT 0x11
#define GRBM_STATUS__IA_BUSY_NO_DMA_MASK 0x40000
#define GRBM_STATUS__IA_BUSY_NO_DMA__SHIFT 0x12
#define GRBM_STATUS__IA_BUSY_MASK 0x80000
#define GRBM_STATUS__IA_BUSY__SHIFT 0x13
#define GRBM_STATUS__SX_BUSY_MASK 0x100000
#define GRBM_STATUS__SX_BUSY__SHIFT 0x14
#define GRBM_STATUS__WD_BUSY_MASK 0x200000
#define GRBM_STATUS__WD_BUSY__SHIFT 0x15
#define GRBM_STATUS__SPI_BUSY_MASK 0x400000
#define GRBM_STATUS__SPI_BUSY__SHIFT 0x16
#define GRBM_STATUS__BCI_BUSY_MASK 0x800000
#define GRBM_STATUS__BCI_BUSY__SHIFT 0x17
#define GRBM_STATUS__SC_BUSY_MASK 0x1000000
#define GRBM_STATUS__SC_BUSY__SHIFT 0x18
#define GRBM_STATUS__PA_BUSY_MASK 0x2000000
#define GRBM_STATUS__PA_BUSY__SHIFT 0x19
#define GRBM_STATUS__DB_BUSY_MASK 0x4000000
#define GRBM_STATUS__DB_BUSY__SHIFT 0x1a
#define GRBM_STATUS__CP_COHERENCY_BUSY_MASK 0x10000000
#define GRBM_STATUS__CP_COHERENCY_BUSY__SHIFT 0x1c
#define GRBM_STATUS__CP_BUSY_MASK 0x20000000
#define GRBM_STATUS__CP_BUSY__SHIFT 0x1d
#define GRBM_STATUS__CB_BUSY_MASK 0x40000000
#define GRBM_STATUS__CB_BUSY__SHIFT 0x1e
#define GRBM_STATUS__GUI_ACTIVE_MASK 0x80000000
#define GRBM_STATUS__GUI_ACTIVE__SHIFT 0x1f
#define GRBM_STATUS2__ME0PIPE1_CMDFIFO_AVAIL_MASK 0xf
#define GRBM_STATUS2__ME0PIPE1_CMDFIFO_AVAIL__SHIFT 0x0
#define GRBM_STATUS2__ME0PIPE1_CF_RQ_PENDING_MASK 0x10
#define GRBM_STATUS2__ME0PIPE1_CF_RQ_PENDING__SHIFT 0x4
#define GRBM_STATUS2__ME0PIPE1_PF_RQ_PENDING_MASK 0x20
#define GRBM_STATUS2__ME0PIPE1_PF_RQ_PENDING__SHIFT 0x5
#define GRBM_STATUS2__ME1PIPE0_RQ_PENDING_MASK 0x40
#define GRBM_STATUS2__ME1PIPE0_RQ_PENDING__SHIFT 0x6
#define GRBM_STATUS2__ME1PIPE1_RQ_PENDING_MASK 0x80
#define GRBM_STATUS2__ME1PIPE1_RQ_PENDING__SHIFT 0x7
#define GRBM_STATUS2__ME1PIPE2_RQ_PENDING_MASK 0x100
#define GRBM_STATUS2__ME1PIPE2_RQ_PENDING__SHIFT 0x8
#define GRBM_STATUS2__ME1PIPE3_RQ_PENDING_MASK 0x200
#define GRBM_STATUS2__ME1PIPE3_RQ_PENDING__SHIFT 0x9
#define GRBM_STATUS2__ME2PIPE0_RQ_PENDING_MASK 0x400
#define GRBM_STATUS2__ME2PIPE0_RQ_PENDING__SHIFT 0xa
#define GRBM_STATUS2__ME2PIPE1_RQ_PENDING_MASK 0x800
#define GRBM_STATUS2__ME2PIPE1_RQ_PENDING__SHIFT 0xb
#define GRBM_STATUS2__ME2PIPE2_RQ_PENDING_MASK 0x1000
#define GRBM_STATUS2__ME2PIPE2_RQ_PENDING__SHIFT 0xc
#define GRBM_STATUS2__ME2PIPE3_RQ_PENDING_MASK 0x2000
#define GRBM_STATUS2__ME2PIPE3_RQ_PENDING__SHIFT 0xd
#define GRBM_STATUS2__RLC_RQ_PENDING_MASK 0x4000
#define GRBM_STATUS2__RLC_RQ_PENDING__SHIFT 0xe
#define GRBM_STATUS2__RLC_BUSY_MASK 0x1000000
#define GRBM_STATUS2__RLC_BUSY__SHIFT 0x18
#define GRBM_STATUS2__TC_BUSY_MASK 0x2000000
#define GRBM_STATUS2__TC_BUSY__SHIFT 0x19
#define GRBM_STATUS2__TCC_CC_RESIDENT_MASK 0x4000000
#define GRBM_STATUS2__TCC_CC_RESIDENT__SHIFT 0x1a
#define GRBM_STATUS2__CPF_BUSY_MASK 0x10000000
#define GRBM_STATUS2__CPF_BUSY__SHIFT 0x1c
#define GRBM_STATUS2__CPC_BUSY_MASK 0x20000000
#define GRBM_STATUS2__CPC_BUSY__SHIFT 0x1d
#define GRBM_STATUS2__CPG_BUSY_MASK 0x40000000
#define GRBM_STATUS2__CPG_BUSY__SHIFT 0x1e
#define GRBM_STATUS_SE0__DB_CLEAN_MASK 0x2
#define GRBM_STATUS_SE0__DB_CLEAN__SHIFT 0x1
#define GRBM_STATUS_SE0__CB_CLEAN_MASK 0x4
#define GRBM_STATUS_SE0__CB_CLEAN__SHIFT 0x2
#define GRBM_STATUS_SE0__BCI_BUSY_MASK 0x400000
#define GRBM_STATUS_SE0__BCI_BUSY__SHIFT 0x16
#define GRBM_STATUS_SE0__VGT_BUSY_MASK 0x800000
#define GRBM_STATUS_SE0__VGT_BUSY__SHIFT 0x17
#define GRBM_STATUS_SE0__PA_BUSY_MASK 0x1000000
#define GRBM_STATUS_SE0__PA_BUSY__SHIFT 0x18
#define GRBM_STATUS_SE0__TA_BUSY_MASK 0x2000000
#define GRBM_STATUS_SE0__TA_BUSY__SHIFT 0x19
#define GRBM_STATUS_SE0__SX_BUSY_MASK 0x4000000
#define GRBM_STATUS_SE0__SX_BUSY__SHIFT 0x1a
#define GRBM_STATUS_SE0__SPI_BUSY_MASK 0x8000000
#define GRBM_STATUS_SE0__SPI_BUSY__SHIFT 0x1b
#define GRBM_STATUS_SE0__SC_BUSY_MASK 0x20000000
#define GRBM_STATUS_SE0__SC_BUSY__SHIFT 0x1d
#define GRBM_STATUS_SE0__DB_BUSY_MASK 0x40000000
#define GRBM_STATUS_SE0__DB_BUSY__SHIFT 0x1e
#define GRBM_STATUS_SE0__CB_BUSY_MASK 0x80000000
#define GRBM_STATUS_SE0__CB_BUSY__SHIFT 0x1f
#define GRBM_STATUS_SE1__DB_CLEAN_MASK 0x2
#define GRBM_STATUS_SE1__DB_CLEAN__SHIFT 0x1
#define GRBM_STATUS_SE1__CB_CLEAN_MASK 0x4
#define GRBM_STATUS_SE1__CB_CLEAN__SHIFT 0x2
#define GRBM_STATUS_SE1__BCI_BUSY_MASK 0x400000
#define GRBM_STATUS_SE1__BCI_BUSY__SHIFT 0x16
#define GRBM_STATUS_SE1__VGT_BUSY_MASK 0x800000
#define GRBM_STATUS_SE1__VGT_BUSY__SHIFT 0x17
#define GRBM_STATUS_SE1__PA_BUSY_MASK 0x1000000
#define GRBM_STATUS_SE1__PA_BUSY__SHIFT 0x18
#define GRBM_STATUS_SE1__TA_BUSY_MASK 0x2000000
#define GRBM_STATUS_SE1__TA_BUSY__SHIFT 0x19
#define GRBM_STATUS_SE1__SX_BUSY_MASK 0x4000000
#define GRBM_STATUS_SE1__SX_BUSY__SHIFT 0x1a
#define GRBM_STATUS_SE1__SPI_BUSY_MASK 0x8000000
#define GRBM_STATUS_SE1__SPI_BUSY__SHIFT 0x1b
#define GRBM_STATUS_SE1__SC_BUSY_MASK 0x20000000
#define GRBM_STATUS_SE1__SC_BUSY__SHIFT 0x1d
#define GRBM_STATUS_SE1__DB_BUSY_MASK 0x40000000
#define GRBM_STATUS_SE1__DB_BUSY__SHIFT 0x1e
#define GRBM_STATUS_SE1__CB_BUSY_MASK 0x80000000
#define GRBM_STATUS_SE1__CB_BUSY__SHIFT 0x1f
#define GRBM_STATUS_SE2__DB_CLEAN_MASK 0x2
#define GRBM_STATUS_SE2__DB_CLEAN__SHIFT 0x1
#define GRBM_STATUS_SE2__CB_CLEAN_MASK 0x4
#define GRBM_STATUS_SE2__CB_CLEAN__SHIFT 0x2
#define GRBM_STATUS_SE2__BCI_BUSY_MASK 0x400000
#define GRBM_STATUS_SE2__BCI_BUSY__SHIFT 0x16
#define GRBM_STATUS_SE2__VGT_BUSY_MASK 0x800000
#define GRBM_STATUS_SE2__VGT_BUSY__SHIFT 0x17
#define GRBM_STATUS_SE2__PA_BUSY_MASK 0x1000000
#define GRBM_STATUS_SE2__PA_BUSY__SHIFT 0x18
#define GRBM_STATUS_SE2__TA_BUSY_MASK 0x2000000
#define GRBM_STATUS_SE2__TA_BUSY__SHIFT 0x19
#define GRBM_STATUS_SE2__SX_BUSY_MASK 0x4000000
#define GRBM_STATUS_SE2__SX_BUSY__SHIFT 0x1a
#define GRBM_STATUS_SE2__SPI_BUSY_MASK 0x8000000
#define GRBM_STATUS_SE2__SPI_BUSY__SHIFT 0x1b
#define GRBM_STATUS_SE2__SC_BUSY_MASK 0x20000000
#define GRBM_STATUS_SE2__SC_BUSY__SHIFT 0x1d
#define GRBM_STATUS_SE2__DB_BUSY_MASK 0x40000000
#define GRBM_STATUS_SE2__DB_BUSY__SHIFT 0x1e
#define GRBM_STATUS_SE2__CB_BUSY_MASK 0x80000000
#define GRBM_STATUS_SE2__CB_BUSY__SHIFT 0x1f
#define GRBM_STATUS_SE3__DB_CLEAN_MASK 0x2
#define GRBM_STATUS_SE3__DB_CLEAN__SHIFT 0x1
#define GRBM_STATUS_SE3__CB_CLEAN_MASK 0x4
#define GRBM_STATUS_SE3__CB_CLEAN__SHIFT 0x2
#define GRBM_STATUS_SE3__BCI_BUSY_MASK 0x400000
#define GRBM_STATUS_SE3__BCI_BUSY__SHIFT 0x16
#define GRBM_STATUS_SE3__VGT_BUSY_MASK 0x800000
#define GRBM_STATUS_SE3__VGT_BUSY__SHIFT 0x17
#define GRBM_STATUS_SE3__PA_BUSY_MASK 0x1000000
#define GRBM_STATUS_SE3__PA_BUSY__SHIFT 0x18
#define GRBM_STATUS_SE3__TA_BUSY_MASK 0x2000000
#define GRBM_STATUS_SE3__TA_BUSY__SHIFT 0x19
#define GRBM_STATUS_SE3__SX_BUSY_MASK 0x4000000
#define GRBM_STATUS_SE3__SX_BUSY__SHIFT 0x1a
#define GRBM_STATUS_SE3__SPI_BUSY_MASK 0x8000000
#define GRBM_STATUS_SE3__SPI_BUSY__SHIFT 0x1b
#define GRBM_STATUS_SE3__SC_BUSY_MASK 0x20000000
#define GRBM_STATUS_SE3__SC_BUSY__SHIFT 0x1d
#define GRBM_STATUS_SE3__DB_BUSY_MASK 0x40000000
#define GRBM_STATUS_SE3__DB_BUSY__SHIFT 0x1e
#define GRBM_STATUS_SE3__CB_BUSY_MASK 0x80000000
#define GRBM_STATUS_SE3__CB_BUSY__SHIFT 0x1f
#define GRBM_SOFT_RESET__SOFT_RESET_CP_MASK 0x1
#define GRBM_SOFT_RESET__SOFT_RESET_CP__SHIFT 0x0
#define GRBM_SOFT_RESET__SOFT_RESET_RLC_MASK 0x4
#define GRBM_SOFT_RESET__SOFT_RESET_RLC__SHIFT 0x2
#define GRBM_SOFT_RESET__SOFT_RESET_GFX_MASK 0x10000
#define GRBM_SOFT_RESET__SOFT_RESET_GFX__SHIFT 0x10
#define GRBM_SOFT_RESET__SOFT_RESET_CPF_MASK 0x20000
#define GRBM_SOFT_RESET__SOFT_RESET_CPF__SHIFT 0x11
#define GRBM_SOFT_RESET__SOFT_RESET_CPC_MASK 0x40000
#define GRBM_SOFT_RESET__SOFT_RESET_CPC__SHIFT 0x12
#define GRBM_SOFT_RESET__SOFT_RESET_CPG_MASK 0x80000
#define GRBM_SOFT_RESET__SOFT_RESET_CPG__SHIFT 0x13
#define GRBM_SOFT_RESET__SOFT_RESET_CAC_MASK 0x100000
#define GRBM_SOFT_RESET__SOFT_RESET_CAC__SHIFT 0x14
#define GRBM_DEBUG_CNTL__GRBM_DEBUG_INDEX_MASK 0x3f
#define GRBM_DEBUG_CNTL__GRBM_DEBUG_INDEX__SHIFT 0x0
#define GRBM_DEBUG_DATA__DATA_MASK 0xffffffff
#define GRBM_DEBUG_DATA__DATA__SHIFT 0x0
#define GRBM_GFX_INDEX__INSTANCE_INDEX_MASK 0xff
#define GRBM_GFX_INDEX__INSTANCE_INDEX__SHIFT 0x0
#define GRBM_GFX_INDEX__SH_INDEX_MASK 0xff00
#define GRBM_GFX_INDEX__SH_INDEX__SHIFT 0x8
#define GRBM_GFX_INDEX__SE_INDEX_MASK 0xff0000
#define GRBM_GFX_INDEX__SE_INDEX__SHIFT 0x10
#define GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK 0x20000000
#define GRBM_GFX_INDEX__SH_BROADCAST_WRITES__SHIFT 0x1d
#define GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES_MASK 0x40000000
#define GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES__SHIFT 0x1e
#define GRBM_GFX_INDEX__SE_BROADCAST_WRITES_MASK 0x80000000
#define GRBM_GFX_INDEX__SE_BROADCAST_WRITES__SHIFT 0x1f
#define GRBM_GFX_CLKEN_CNTL__PREFIX_DELAY_CNT_MASK 0xf
#define GRBM_GFX_CLKEN_CNTL__PREFIX_DELAY_CNT__SHIFT 0x0
#define GRBM_GFX_CLKEN_CNTL__POST_DELAY_CNT_MASK 0x1f00
#define GRBM_GFX_CLKEN_CNTL__POST_DELAY_CNT__SHIFT 0x8
#define GRBM_WAIT_IDLE_CLOCKS__WAIT_IDLE_CLOCKS_MASK 0xff
#define GRBM_WAIT_IDLE_CLOCKS__WAIT_IDLE_CLOCKS__SHIFT 0x0
#define GRBM_DEBUG__IGNORE_RDY_MASK 0x2
#define GRBM_DEBUG__IGNORE_RDY__SHIFT 0x1
#define GRBM_DEBUG__IGNORE_FAO_MASK 0x20
#define GRBM_DEBUG__IGNORE_FAO__SHIFT 0x5
#define GRBM_DEBUG__DISABLE_READ_TIMEOUT_MASK 0x40
#define GRBM_DEBUG__DISABLE_READ_TIMEOUT__SHIFT 0x6
#define GRBM_DEBUG__SNAPSHOT_FREE_CNTRS_MASK 0x80
#define GRBM_DEBUG__SNAPSHOT_FREE_CNTRS__SHIFT 0x7
#define GRBM_DEBUG__HYSTERESIS_GUI_ACTIVE_MASK 0xf00
#define GRBM_DEBUG__HYSTERESIS_GUI_ACTIVE__SHIFT 0x8
#define GRBM_DEBUG__GFX_CLOCK_DOMAIN_OVERRIDE_MASK 0x1000
#define GRBM_DEBUG__GFX_CLOCK_DOMAIN_OVERRIDE__SHIFT 0xc
#define GRBM_DEBUG__GRBM_TRAP_ENABLE_MASK 0x2000
#define GRBM_DEBUG__GRBM_TRAP_ENABLE__SHIFT 0xd
#define GRBM_DEBUG__DEBUG_BUS_FGCG_EN_MASK 0x80000000
#define GRBM_DEBUG__DEBUG_BUS_FGCG_EN__SHIFT 0x1f
#define GRBM_DEBUG_SNAPSHOT__CPF_RDY_MASK 0x1
#define GRBM_DEBUG_SNAPSHOT__CPF_RDY__SHIFT 0x0
#define GRBM_DEBUG_SNAPSHOT__CPG_RDY_MASK 0x2
#define GRBM_DEBUG_SNAPSHOT__CPG_RDY__SHIFT 0x1
#define GRBM_DEBUG_SNAPSHOT__SRBM_RDY_MASK 0x4
#define GRBM_DEBUG_SNAPSHOT__SRBM_RDY__SHIFT 0x2
#define GRBM_DEBUG_SNAPSHOT__WD_ME0PIPE0_RDY_MASK 0x8
#define GRBM_DEBUG_SNAPSHOT__WD_ME0PIPE0_RDY__SHIFT 0x3
#define GRBM_DEBUG_SNAPSHOT__WD_ME0PIPE1_RDY_MASK 0x10
#define GRBM_DEBUG_SNAPSHOT__WD_ME0PIPE1_RDY__SHIFT 0x4
#define GRBM_DEBUG_SNAPSHOT__GDS_RDY_MASK 0x20
#define GRBM_DEBUG_SNAPSHOT__GDS_RDY__SHIFT 0x5
#define GRBM_DEBUG_SNAPSHOT__SE0SPI_ME0PIPE0_RDY0_MASK 0x40
#define GRBM_DEBUG_SNAPSHOT__SE0SPI_ME0PIPE0_RDY0__SHIFT 0x6
#define GRBM_DEBUG_SNAPSHOT__SE0SPI_ME0PIPE1_RDY0_MASK 0x80
#define GRBM_DEBUG_SNAPSHOT__SE0SPI_ME0PIPE1_RDY0__SHIFT 0x7
#define GRBM_DEBUG_SNAPSHOT__SE1SPI_ME0PIPE0_RDY0_MASK 0x100
#define GRBM_DEBUG_SNAPSHOT__SE1SPI_ME0PIPE0_RDY0__SHIFT 0x8
#define GRBM_DEBUG_SNAPSHOT__SE1SPI_ME0PIPE1_RDY0_MASK 0x200
#define GRBM_DEBUG_SNAPSHOT__SE1SPI_ME0PIPE1_RDY0__SHIFT 0x9
#define GRBM_DEBUG_SNAPSHOT__SE2SPI_ME0PIPE0_RDY0_MASK 0x400
#define GRBM_DEBUG_SNAPSHOT__SE2SPI_ME0PIPE0_RDY0__SHIFT 0xa
#define GRBM_DEBUG_SNAPSHOT__SE2SPI_ME0PIPE1_RDY0_MASK 0x800
#define GRBM_DEBUG_SNAPSHOT__SE2SPI_ME0PIPE1_RDY0__SHIFT 0xb
#define GRBM_DEBUG_SNAPSHOT__SE3SPI_ME0PIPE0_RDY0_MASK 0x1000
#define GRBM_DEBUG_SNAPSHOT__SE3SPI_ME0PIPE0_RDY0__SHIFT 0xc
#define GRBM_DEBUG_SNAPSHOT__SE3SPI_ME0PIPE1_RDY0_MASK 0x2000
#define GRBM_DEBUG_SNAPSHOT__SE3SPI_ME0PIPE1_RDY0__SHIFT 0xd
#define GRBM_DEBUG_SNAPSHOT__SE0SPI_ME0PIPE0_RDY1_MASK 0x4000
#define GRBM_DEBUG_SNAPSHOT__SE0SPI_ME0PIPE0_RDY1__SHIFT 0xe
#define GRBM_DEBUG_SNAPSHOT__SE0SPI_ME0PIPE1_RDY1_MASK 0x8000
#define GRBM_DEBUG_SNAPSHOT__SE0SPI_ME0PIPE1_RDY1__SHIFT 0xf
#define GRBM_DEBUG_SNAPSHOT__SE1SPI_ME0PIPE0_RDY1_MASK 0x10000
#define GRBM_DEBUG_SNAPSHOT__SE1SPI_ME0PIPE0_RDY1__SHIFT 0x10
#define GRBM_DEBUG_SNAPSHOT__SE1SPI_ME0PIPE1_RDY1_MASK 0x20000
#define GRBM_DEBUG_SNAPSHOT__SE1SPI_ME0PIPE1_RDY1__SHIFT 0x11
#define GRBM_DEBUG_SNAPSHOT__SE2SPI_ME0PIPE0_RDY1_MASK 0x40000
#define GRBM_DEBUG_SNAPSHOT__SE2SPI_ME0PIPE0_RDY1__SHIFT 0x12
#define GRBM_DEBUG_SNAPSHOT__SE2SPI_ME0PIPE1_RDY1_MASK 0x80000
#define GRBM_DEBUG_SNAPSHOT__SE2SPI_ME0PIPE1_RDY1__SHIFT 0x13
#define GRBM_DEBUG_SNAPSHOT__SE3SPI_ME0PIPE0_RDY1_MASK 0x100000
#define GRBM_DEBUG_SNAPSHOT__SE3SPI_ME0PIPE0_RDY1__SHIFT 0x14
#define GRBM_DEBUG_SNAPSHOT__SE3SPI_ME0PIPE1_RDY1_MASK 0x200000
#define GRBM_DEBUG_SNAPSHOT__SE3SPI_ME0PIPE1_RDY1__SHIFT 0x15
#define GRBM_READ_ERROR__READ_ADDRESS_MASK 0x3fffc
#define GRBM_READ_ERROR__READ_ADDRESS__SHIFT 0x2
#define GRBM_READ_ERROR__READ_PIPEID_MASK 0x300000
#define GRBM_READ_ERROR__READ_PIPEID__SHIFT 0x14
#define GRBM_READ_ERROR__READ_MEID_MASK 0xc00000
#define GRBM_READ_ERROR__READ_MEID__SHIFT 0x16
#define GRBM_READ_ERROR__READ_ERROR_MASK 0x80000000
#define GRBM_READ_ERROR__READ_ERROR__SHIFT 0x1f
#define GRBM_READ_ERROR2__READ_REQUESTER_SRBM_MASK 0x20000
#define GRBM_READ_ERROR2__READ_REQUESTER_SRBM__SHIFT 0x11
#define GRBM_READ_ERROR2__READ_REQUESTER_RLC_MASK 0x40000
#define GRBM_READ_ERROR2__READ_REQUESTER_RLC__SHIFT 0x12
#define GRBM_READ_ERROR2__READ_REQUESTER_GDS_DMA_MASK 0x80000
#define GRBM_READ_ERROR2__READ_REQUESTER_GDS_DMA__SHIFT 0x13
#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE0_CF_MASK 0x100000
#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE0_CF__SHIFT 0x14
#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE0_PF_MASK 0x200000
#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE0_PF__SHIFT 0x15
#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE1_CF_MASK 0x400000
#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE1_CF__SHIFT 0x16
#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE1_PF_MASK 0x800000
#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE1_PF__SHIFT 0x17
#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE0_MASK 0x1000000
#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE0__SHIFT 0x18
#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE1_MASK 0x2000000
#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE1__SHIFT 0x19
#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE2_MASK 0x4000000
#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE2__SHIFT 0x1a
#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE3_MASK 0x8000000
#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE3__SHIFT 0x1b
#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE0_MASK 0x10000000
#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE0__SHIFT 0x1c
#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE1_MASK 0x20000000
#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE1__SHIFT 0x1d
#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE2_MASK 0x40000000
#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE2__SHIFT 0x1e
#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE3_MASK 0x80000000
#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE3__SHIFT 0x1f
#define GRBM_INT_CNTL__RDERR_INT_ENABLE_MASK 0x1
#define GRBM_INT_CNTL__RDERR_INT_ENABLE__SHIFT 0x0
#define GRBM_INT_CNTL__GUI_IDLE_INT_ENABLE_MASK 0x80000
#define GRBM_INT_CNTL__GUI_IDLE_INT_ENABLE__SHIFT 0x13
#define GRBM_TRAP_OP__RW_MASK 0x1
#define GRBM_TRAP_OP__RW__SHIFT 0x0
#define GRBM_TRAP_ADDR__DATA_MASK 0xffff
#define GRBM_TRAP_ADDR__DATA__SHIFT 0x0
#define GRBM_TRAP_ADDR_MSK__DATA_MASK 0xffff
#define GRBM_TRAP_ADDR_MSK__DATA__SHIFT 0x0
#define GRBM_TRAP_WD__DATA_MASK 0xffffffff
#define GRBM_TRAP_WD__DATA__SHIFT 0x0
#define GRBM_TRAP_WD_MSK__DATA_MASK 0xffffffff
#define GRBM_TRAP_WD_MSK__DATA__SHIFT 0x0
#define GRBM_DSM_BYPASS__BYPASS_BITS_MASK 0x3
#define GRBM_DSM_BYPASS__BYPASS_BITS__SHIFT 0x0
#define GRBM_DSM_BYPASS__BYPASS_EN_MASK 0x4
#define GRBM_DSM_BYPASS__BYPASS_EN__SHIFT 0x2
#define GRBM_WRITE_ERROR__WRITE_REQUESTER_RLC_MASK 0x1
#define GRBM_WRITE_ERROR__WRITE_REQUESTER_RLC__SHIFT 0x0
#define GRBM_WRITE_ERROR__WRITE_REQUESTER_SRBM_MASK 0x2
#define GRBM_WRITE_ERROR__WRITE_REQUESTER_SRBM__SHIFT 0x1
#define GRBM_WRITE_ERROR__WRITE_SSRCID_MASK 0x1c
#define GRBM_WRITE_ERROR__WRITE_SSRCID__SHIFT 0x2
#define GRBM_WRITE_ERROR__WRITE_VFID_MASK 0x1e0
#define GRBM_WRITE_ERROR__WRITE_VFID__SHIFT 0x5
#define GRBM_WRITE_ERROR__WRITE_VF_MASK 0x1000
#define GRBM_WRITE_ERROR__WRITE_VF__SHIFT 0xc
#define GRBM_WRITE_ERROR__WRITE_VMID_MASK 0x1e000
#define GRBM_WRITE_ERROR__WRITE_VMID__SHIFT 0xd
#define GRBM_WRITE_ERROR__WRITE_PIPEID_MASK 0x300000
#define GRBM_WRITE_ERROR__WRITE_PIPEID__SHIFT 0x14
#define GRBM_WRITE_ERROR__WRITE_MEID_MASK 0xc00000
#define GRBM_WRITE_ERROR__WRITE_MEID__SHIFT 0x16
#define GRBM_WRITE_ERROR__WRITE_ERROR_MASK 0x80000000
#define GRBM_WRITE_ERROR__WRITE_ERROR__SHIFT 0x1f
#define GRBM_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x3f
#define GRBM_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
#define GRBM_PERFCOUNTER0_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK 0x400
#define GRBM_PERFCOUNTER0_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0xa
#define GRBM_PERFCOUNTER0_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK 0x800
#define GRBM_PERFCOUNTER0_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT 0xb
#define GRBM_PERFCOUNTER0_SELECT__VGT_BUSY_USER_DEFINED_MASK_MASK 0x1000
#define GRBM_PERFCOUNTER0_SELECT__VGT_BUSY_USER_DEFINED_MASK__SHIFT 0xc
#define GRBM_PERFCOUNTER0_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK 0x2000
#define GRBM_PERFCOUNTER0_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT 0xd
#define GRBM_PERFCOUNTER0_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK 0x4000
#define GRBM_PERFCOUNTER0_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT 0xe
#define GRBM_PERFCOUNTER0_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK 0x10000
#define GRBM_PERFCOUNTER0_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT 0x10
#define GRBM_PERFCOUNTER0_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK 0x20000
#define GRBM_PERFCOUNTER0_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT 0x11
#define GRBM_PERFCOUNTER0_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK 0x40000
#define GRBM_PERFCOUNTER0_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT 0x12
#define GRBM_PERFCOUNTER0_SELECT__GRBM_BUSY_USER_DEFINED_MASK_MASK 0x80000
#define GRBM_PERFCOUNTER0_SELECT__GRBM_BUSY_USER_DEFINED_MASK__SHIFT 0x13
#define GRBM_PERFCOUNTER0_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK 0x100000
#define GRBM_PERFCOUNTER0_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT 0x14
#define GRBM_PERFCOUNTER0_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK 0x200000
#define GRBM_PERFCOUNTER0_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT 0x15
#define GRBM_PERFCOUNTER0_SELECT__CP_BUSY_USER_DEFINED_MASK_MASK 0x400000
#define GRBM_PERFCOUNTER0_SELECT__CP_BUSY_USER_DEFINED_MASK__SHIFT 0x16
#define GRBM_PERFCOUNTER0_SELECT__IA_BUSY_USER_DEFINED_MASK_MASK 0x800000
#define GRBM_PERFCOUNTER0_SELECT__IA_BUSY_USER_DEFINED_MASK__SHIFT 0x17
#define GRBM_PERFCOUNTER0_SELECT__GDS_BUSY_USER_DEFINED_MASK_MASK 0x1000000
#define GRBM_PERFCOUNTER0_SELECT__GDS_BUSY_USER_DEFINED_MASK__SHIFT 0x18
#define GRBM_PERFCOUNTER0_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK 0x2000000
#define GRBM_PERFCOUNTER0_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT 0x19
#define GRBM_PERFCOUNTER0_SELECT__RLC_BUSY_USER_DEFINED_MASK_MASK 0x4000000
#define GRBM_PERFCOUNTER0_SELECT__RLC_BUSY_USER_DEFINED_MASK__SHIFT 0x1a
#define GRBM_PERFCOUNTER0_SELECT__TC_BUSY_USER_DEFINED_MASK_MASK 0x8000000
#define GRBM_PERFCOUNTER0_SELECT__TC_BUSY_USER_DEFINED_MASK__SHIFT 0x1b
#define GRBM_PERFCOUNTER0_SELECT__WD_BUSY_USER_DEFINED_MASK_MASK 0x10000000
#define GRBM_PERFCOUNTER0_SELECT__WD_BUSY_USER_DEFINED_MASK__SHIFT 0x1c
#define GRBM_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x3f
#define GRBM_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
#define GRBM_PERFCOUNTER1_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK 0x400
#define GRBM_PERFCOUNTER1_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0xa
#define GRBM_PERFCOUNTER1_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK 0x800
#define GRBM_PERFCOUNTER1_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT 0xb
#define GRBM_PERFCOUNTER1_SELECT__VGT_BUSY_USER_DEFINED_MASK_MASK 0x1000
#define GRBM_PERFCOUNTER1_SELECT__VGT_BUSY_USER_DEFINED_MASK__SHIFT 0xc
#define GRBM_PERFCOUNTER1_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK 0x2000
#define GRBM_PERFCOUNTER1_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT 0xd
#define GRBM_PERFCOUNTER1_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK 0x4000
#define GRBM_PERFCOUNTER1_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT 0xe
#define GRBM_PERFCOUNTER1_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK 0x10000
#define GRBM_PERFCOUNTER1_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT 0x10
#define GRBM_PERFCOUNTER1_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK 0x20000
#define GRBM_PERFCOUNTER1_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT 0x11
#define GRBM_PERFCOUNTER1_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK 0x40000
#define GRBM_PERFCOUNTER1_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT 0x12
#define GRBM_PERFCOUNTER1_SELECT__GRBM_BUSY_USER_DEFINED_MASK_MASK 0x80000
#define GRBM_PERFCOUNTER1_SELECT__GRBM_BUSY_USER_DEFINED_MASK__SHIFT 0x13
#define GRBM_PERFCOUNTER1_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK 0x100000
#define GRBM_PERFCOUNTER1_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT 0x14
#define GRBM_PERFCOUNTER1_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK 0x200000
#define GRBM_PERFCOUNTER1_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT 0x15
#define GRBM_PERFCOUNTER1_SELECT__CP_BUSY_USER_DEFINED_MASK_MASK 0x400000
#define GRBM_PERFCOUNTER1_SELECT__CP_BUSY_USER_DEFINED_MASK__SHIFT 0x16
#define GRBM_PERFCOUNTER1_SELECT__IA_BUSY_USER_DEFINED_MASK_MASK 0x800000
#define GRBM_PERFCOUNTER1_SELECT__IA_BUSY_USER_DEFINED_MASK__SHIFT 0x17
#define GRBM_PERFCOUNTER1_SELECT__GDS_BUSY_USER_DEFINED_MASK_MASK 0x1000000
#define GRBM_PERFCOUNTER1_SELECT__GDS_BUSY_USER_DEFINED_MASK__SHIFT 0x18
#define GRBM_PERFCOUNTER1_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK 0x2000000
#define GRBM_PERFCOUNTER1_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT 0x19
#define GRBM_PERFCOUNTER1_SELECT__RLC_BUSY_USER_DEFINED_MASK_MASK 0x4000000
#define GRBM_PERFCOUNTER1_SELECT__RLC_BUSY_USER_DEFINED_MASK__SHIFT 0x1a
#define GRBM_PERFCOUNTER1_SELECT__TC_BUSY_USER_DEFINED_MASK_MASK 0x8000000
#define GRBM_PERFCOUNTER1_SELECT__TC_BUSY_USER_DEFINED_MASK__SHIFT 0x1b
#define GRBM_PERFCOUNTER1_SELECT__WD_BUSY_USER_DEFINED_MASK_MASK 0x10000000
#define GRBM_PERFCOUNTER1_SELECT__WD_BUSY_USER_DEFINED_MASK__SHIFT 0x1c
#define GRBM_SE0_PERFCOUNTER_SELECT__PERF_SEL_MASK 0x3f
#define GRBM_SE0_PERFCOUNTER_SELECT__PERF_SEL__SHIFT 0x0
#define GRBM_SE0_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK 0x400
#define GRBM_SE0_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0xa
#define GRBM_SE0_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK 0x800
#define GRBM_SE0_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT 0xb
#define GRBM_SE0_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK 0x1000
#define GRBM_SE0_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT 0xc
#define GRBM_SE0_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK 0x2000
#define GRBM_SE0_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT 0xd
#define GRBM_SE0_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK 0x8000
#define GRBM_SE0_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT 0xf
#define GRBM_SE0_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK 0x10000
#define GRBM_SE0_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT 0x10
#define GRBM_SE0_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK 0x20000
#define GRBM_SE0_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT 0x11
#define GRBM_SE0_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK 0x40000
#define GRBM_SE0_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT 0x12
#define GRBM_SE0_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK_MASK 0x80000
#define GRBM_SE0_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK__SHIFT 0x13
#define GRBM_SE0_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK 0x100000
#define GRBM_SE0_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT 0x14
#define GRBM_SE0_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK 0x200000
#define GRBM_SE0_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT 0x15
#define GRBM_SE1_PERFCOUNTER_SELECT__PERF_SEL_MASK 0x3f
#define GRBM_SE1_PERFCOUNTER_SELECT__PERF_SEL__SHIFT 0x0
#define GRBM_SE1_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK 0x400
#define GRBM_SE1_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0xa
#define GRBM_SE1_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK 0x800
#define GRBM_SE1_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT 0xb
#define GRBM_SE1_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK 0x1000
#define GRBM_SE1_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT 0xc
#define GRBM_SE1_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK 0x2000
#define GRBM_SE1_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT 0xd
#define GRBM_SE1_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK 0x8000
#define GRBM_SE1_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT 0xf
#define GRBM_SE1_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK 0x10000
#define GRBM_SE1_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT 0x10
#define GRBM_SE1_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK 0x20000
#define GRBM_SE1_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT 0x11
#define GRBM_SE1_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK 0x40000
#define GRBM_SE1_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT 0x12
#define GRBM_SE1_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK_MASK 0x80000
#define GRBM_SE1_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK__SHIFT 0x13
#define GRBM_SE1_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK 0x100000
#define GRBM_SE1_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT 0x14
#define GRBM_SE1_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK 0x200000
#define GRBM_SE1_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT 0x15
#define GRBM_SE2_PERFCOUNTER_SELECT__PERF_SEL_MASK 0x3f
#define GRBM_SE2_PERFCOUNTER_SELECT__PERF_SEL__SHIFT 0x0
#define GRBM_SE2_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK 0x400
#define GRBM_SE2_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0xa
#define GRBM_SE2_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK 0x800
#define GRBM_SE2_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT 0xb
#define GRBM_SE2_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK 0x1000
#define GRBM_SE2_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT 0xc
#define GRBM_SE2_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK 0x2000
#define GRBM_SE2_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT 0xd
#define GRBM_SE2_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK 0x8000
#define GRBM_SE2_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT 0xf
#define GRBM_SE2_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK 0x10000
#define GRBM_SE2_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT 0x10
#define GRBM_SE2_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK 0x20000
#define GRBM_SE2_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT 0x11
#define GRBM_SE2_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK 0x40000
#define GRBM_SE2_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT 0x12
#define GRBM_SE2_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK_MASK 0x80000
#define GRBM_SE2_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK__SHIFT 0x13
#define GRBM_SE2_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK 0x100000
#define GRBM_SE2_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT 0x14
#define GRBM_SE2_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK 0x200000
#define GRBM_SE2_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT 0x15
#define GRBM_SE3_PERFCOUNTER_SELECT__PERF_SEL_MASK 0x3f
#define GRBM_SE3_PERFCOUNTER_SELECT__PERF_SEL__SHIFT 0x0
#define GRBM_SE3_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK 0x400
#define GRBM_SE3_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0xa
#define GRBM_SE3_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK 0x800
#define GRBM_SE3_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT 0xb
#define GRBM_SE3_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK 0x1000
#define GRBM_SE3_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT 0xc
#define GRBM_SE3_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK 0x2000
#define GRBM_SE3_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT 0xd
#define GRBM_SE3_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK 0x8000
#define GRBM_SE3_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT 0xf
#define GRBM_SE3_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK 0x10000
#define GRBM_SE3_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT 0x10
#define GRBM_SE3_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK 0x20000
#define GRBM_SE3_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT 0x11
#define GRBM_SE3_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK 0x40000
#define GRBM_SE3_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT 0x12
#define GRBM_SE3_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK_MASK 0x80000
#define GRBM_SE3_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK__SHIFT 0x13
#define GRBM_SE3_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK 0x100000
#define GRBM_SE3_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT 0x14
#define GRBM_SE3_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK 0x200000
#define GRBM_SE3_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT 0x15
#define GRBM_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff
#define GRBM_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
#define GRBM_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff
#define GRBM_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
#define GRBM_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff
#define GRBM_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
#define GRBM_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff
#define GRBM_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
#define GRBM_SE0_PERFCOUNTER_LO__PERFCOUNTER_LO_MASK 0xffffffff
#define GRBM_SE0_PERFCOUNTER_LO__PERFCOUNTER_LO__SHIFT 0x0
#define GRBM_SE0_PERFCOUNTER_HI__PERFCOUNTER_HI_MASK 0xffffffff
#define GRBM_SE0_PERFCOUNTER_HI__PERFCOUNTER_HI__SHIFT 0x0
#define GRBM_SE1_PERFCOUNTER_LO__PERFCOUNTER_LO_MASK 0xffffffff
#define GRBM_SE1_PERFCOUNTER_LO__PERFCOUNTER_LO__SHIFT 0x0
#define GRBM_SE1_PERFCOUNTER_HI__PERFCOUNTER_HI_MASK 0xffffffff
#define GRBM_SE1_PERFCOUNTER_HI__PERFCOUNTER_HI__SHIFT 0x0
#define GRBM_SE2_PERFCOUNTER_LO__PERFCOUNTER_LO_MASK 0xffffffff
#define GRBM_SE2_PERFCOUNTER_LO__PERFCOUNTER_LO__SHIFT 0x0
#define GRBM_SE2_PERFCOUNTER_HI__PERFCOUNTER_HI_MASK 0xffffffff
#define GRBM_SE2_PERFCOUNTER_HI__PERFCOUNTER_HI__SHIFT 0x0
#define GRBM_SE3_PERFCOUNTER_LO__PERFCOUNTER_LO_MASK 0xffffffff
#define GRBM_SE3_PERFCOUNTER_LO__PERFCOUNTER_LO__SHIFT 0x0
#define GRBM_SE3_PERFCOUNTER_HI__PERFCOUNTER_HI_MASK 0xffffffff
#define GRBM_SE3_PERFCOUNTER_HI__PERFCOUNTER_HI__SHIFT 0x0
#define GRBM_SCRATCH_REG0__SCRATCH_REG0_MASK 0xffffffff
#define GRBM_SCRATCH_REG0__SCRATCH_REG0__SHIFT 0x0
#define GRBM_SCRATCH_REG1__SCRATCH_REG1_MASK 0xffffffff
#define GRBM_SCRATCH_REG1__SCRATCH_REG1__SHIFT 0x0
#define GRBM_SCRATCH_REG2__SCRATCH_REG2_MASK 0xffffffff
#define GRBM_SCRATCH_REG2__SCRATCH_REG2__SHIFT 0x0
#define GRBM_SCRATCH_REG3__SCRATCH_REG3_MASK 0xffffffff
#define GRBM_SCRATCH_REG3__SCRATCH_REG3__SHIFT 0x0
#define GRBM_SCRATCH_REG4__SCRATCH_REG4_MASK 0xffffffff
#define GRBM_SCRATCH_REG4__SCRATCH_REG4__SHIFT 0x0
#define GRBM_SCRATCH_REG5__SCRATCH_REG5_MASK 0xffffffff
#define GRBM_SCRATCH_REG5__SCRATCH_REG5__SHIFT 0x0
#define GRBM_SCRATCH_REG6__SCRATCH_REG6_MASK 0xffffffff
#define GRBM_SCRATCH_REG6__SCRATCH_REG6__SHIFT 0x0
#define GRBM_SCRATCH_REG7__SCRATCH_REG7_MASK 0xffffffff
#define GRBM_SCRATCH_REG7__SCRATCH_REG7__SHIFT 0x0
#define DEBUG_INDEX__DEBUG_INDEX_MASK 0x3ffff
#define DEBUG_INDEX__DEBUG_INDEX__SHIFT 0x0
#define DEBUG_DATA__DEBUG_DATA_MASK 0xffffffff
#define DEBUG_DATA__DEBUG_DATA__SHIFT 0x0
#define GRBM_NOWHERE__DATA_MASK 0xffffffff
#define GRBM_NOWHERE__DATA__SHIFT 0x0
#define PA_CL_VPORT_XSCALE__VPORT_XSCALE_MASK 0xffffffff
#define PA_CL_VPORT_XSCALE__VPORT_XSCALE__SHIFT 0x0
#define PA_CL_VPORT_XOFFSET__VPORT_XOFFSET_MASK 0xffffffff
#define PA_CL_VPORT_XOFFSET__VPORT_XOFFSET__SHIFT 0x0
#define PA_CL_VPORT_YSCALE__VPORT_YSCALE_MASK 0xffffffff
#define PA_CL_VPORT_YSCALE__VPORT_YSCALE__SHIFT 0x0
#define PA_CL_VPORT_YOFFSET__VPORT_YOFFSET_MASK 0xffffffff
#define PA_CL_VPORT_YOFFSET__VPORT_YOFFSET__SHIFT 0x0
#define PA_CL_VPORT_ZSCALE__VPORT_ZSCALE_MASK 0xffffffff
#define PA_CL_VPORT_ZSCALE__VPORT_ZSCALE__SHIFT 0x0
#define PA_CL_VPORT_ZOFFSET__VPORT_ZOFFSET_MASK 0xffffffff
#define PA_CL_VPORT_ZOFFSET__VPORT_ZOFFSET__SHIFT 0x0
#define PA_CL_VPORT_XSCALE_1__VPORT_XSCALE_MASK 0xffffffff
#define PA_CL_VPORT_XSCALE_1__VPORT_XSCALE__SHIFT 0x0
#define PA_CL_VPORT_XSCALE_2__VPORT_XSCALE_MASK 0xffffffff
#define PA_CL_VPORT_XSCALE_2__VPORT_XSCALE__SHIFT 0x0
#define PA_CL_VPORT_XSCALE_3__VPORT_XSCALE_MASK 0xffffffff
#define PA_CL_VPORT_XSCALE_3__VPORT_XSCALE__SHIFT 0x0
#define PA_CL_VPORT_XSCALE_4__VPORT_XSCALE_MASK 0xffffffff
#define PA_CL_VPORT_XSCALE_4__VPORT_XSCALE__SHIFT 0x0
#define PA_CL_VPORT_XSCALE_5__VPORT_XSCALE_MASK 0xffffffff
#define PA_CL_VPORT_XSCALE_5__VPORT_XSCALE__SHIFT 0x0
#define PA_CL_VPORT_XSCALE_6__VPORT_XSCALE_MASK 0xffffffff
#define PA_CL_VPORT_XSCALE_6__VPORT_XSCALE__SHIFT 0x0
#define PA_CL_VPORT_XSCALE_7__VPORT_XSCALE_MASK 0xffffffff
#define PA_CL_VPORT_XSCALE_7__VPORT_XSCALE__SHIFT 0x0
#define PA_CL_VPORT_XSCALE_8__VPORT_XSCALE_MASK 0xffffffff
#define PA_CL_VPORT_XSCALE_8__VPORT_XSCALE__SHIFT 0x0
#define PA_CL_VPORT_XSCALE_9__VPORT_XSCALE_MASK 0xffffffff
#define PA_CL_VPORT_XSCALE_9__VPORT_XSCALE__SHIFT 0x0
#define PA_CL_VPORT_XSCALE_10__VPORT_XSCALE_MASK 0xffffffff
#define PA_CL_VPORT_XSCALE_10__VPORT_XSCALE__SHIFT 0x0
#define PA_CL_VPORT_XSCALE_11__VPORT_XSCALE_MASK 0xffffffff
#define PA_CL_VPORT_XSCALE_11__VPORT_XSCALE__SHIFT 0x0
#define PA_CL_VPORT_XSCALE_12__VPORT_XSCALE_MASK 0xffffffff
#define PA_CL_VPORT_XSCALE_12__VPORT_XSCALE__SHIFT 0x0
#define PA_CL_VPORT_XSCALE_13__VPORT_XSCALE_MASK 0xffffffff
#define PA_CL_VPORT_XSCALE_13__VPORT_XSCALE__SHIFT 0x0
#define PA_CL_VPORT_XSCALE_14__VPORT_XSCALE_MASK 0xffffffff
#define PA_CL_VPORT_XSCALE_14__VPORT_XSCALE__SHIFT 0x0
#define PA_CL_VPORT_XSCALE_15__VPORT_XSCALE_MASK 0xffffffff
#define PA_CL_VPORT_XSCALE_15__VPORT_XSCALE__SHIFT 0x0
#define PA_CL_VPORT_XOFFSET_1__VPORT_XOFFSET_MASK 0xffffffff
#define PA_CL_VPORT_XOFFSET_1__VPORT_XOFFSET__SHIFT 0x0
#define PA_CL_VPORT_XOFFSET_2__VPORT_XOFFSET_MASK 0xffffffff
#define PA_CL_VPORT_XOFFSET_2__VPORT_XOFFSET__SHIFT 0x0
#define PA_CL_VPORT_XOFFSET_3__VPORT_XOFFSET_MASK 0xffffffff
#define PA_CL_VPORT_XOFFSET_3__VPORT_XOFFSET__SHIFT 0x0
#define PA_CL_VPORT_XOFFSET_4__VPORT_XOFFSET_MASK 0xffffffff
#define PA_CL_VPORT_XOFFSET_4__VPORT_XOFFSET__SHIFT 0x0
#define PA_CL_VPORT_XOFFSET_5__VPORT_XOFFSET_MASK 0xffffffff
#define PA_CL_VPORT_XOFFSET_5__VPORT_XOFFSET__SHIFT 0x0
#define PA_CL_VPORT_XOFFSET_6__VPORT_XOFFSET_MASK 0xffffffff
#define PA_CL_VPORT_XOFFSET_6__VPORT_XOFFSET__SHIFT 0x0
#define PA_CL_VPORT_XOFFSET_7__VPORT_XOFFSET_MASK 0xffffffff
#define PA_CL_VPORT_XOFFSET_7__VPORT_XOFFSET__SHIFT 0x0
#define PA_CL_VPORT_XOFFSET_8__VPORT_XOFFSET_MASK 0xffffffff
#define PA_CL_VPORT_XOFFSET_8__VPORT_XOFFSET__SHIFT 0x0
#define PA_CL_VPORT_XOFFSET_9__VPORT_XOFFSET_MASK 0xffffffff
#define PA_CL_VPORT_XOFFSET_9__VPORT_XOFFSET__SHIFT 0x0
#define PA_CL_VPORT_XOFFSET_10__VPORT_XOFFSET_MASK 0xffffffff
#define PA_CL_VPORT_XOFFSET_10__VPORT_XOFFSET__SHIFT 0x0
#define PA_CL_VPORT_XOFFSET_11__VPORT_XOFFSET_MASK 0xffffffff
#define PA_CL_VPORT_XOFFSET_11__VPORT_XOFFSET__SHIFT 0x0
#define PA_CL_VPORT_XOFFSET_12__VPORT_XOFFSET_MASK 0xffffffff
#define PA_CL_VPORT_XOFFSET_12__VPORT_XOFFSET__SHIFT 0x0
#define PA_CL_VPORT_XOFFSET_13__VPORT_XOFFSET_MASK 0xffffffff
#define PA_CL_VPORT_XOFFSET_13__VPORT_XOFFSET__SHIFT 0x0
#define PA_CL_VPORT_XOFFSET_14__VPORT_XOFFSET_MASK 0xffffffff
#define PA_CL_VPORT_XOFFSET_14__VPORT_XOFFSET__SHIFT 0x0
#define PA_CL_VPORT_XOFFSET_15__VPORT_XOFFSET_MASK 0xffffffff
#define PA_CL_VPORT_XOFFSET_15__VPORT_XOFFSET__SHIFT 0x0
#define PA_CL_VPORT_YSCALE_1__VPORT_YSCALE_MASK 0xffffffff
#define PA_CL_VPORT_YSCALE_1__VPORT_YSCALE__SHIFT 0x0
#define PA_CL_VPORT_YSCALE_2__VPORT_YSCALE_MASK 0xffffffff
#define PA_CL_VPORT_YSCALE_2__VPORT_YSCALE__SHIFT 0x0
#define PA_CL_VPORT_YSCALE_3__VPORT_YSCALE_MASK 0xffffffff
#define PA_CL_VPORT_YSCALE_3__VPORT_YSCALE__SHIFT 0x0
#define PA_CL_VPORT_YSCALE_4__VPORT_YSCALE_MASK 0xffffffff
#define PA_CL_VPORT_YSCALE_4__VPORT_YSCALE__SHIFT 0x0
#define PA_CL_VPORT_YSCALE_5__VPORT_YSCALE_MASK 0xffffffff
#define PA_CL_VPORT_YSCALE_5__VPORT_YSCALE__SHIFT 0x0
#define PA_CL_VPORT_YSCALE_6__VPORT_YSCALE_MASK 0xffffffff
#define PA_CL_VPORT_YSCALE_6__VPORT_YSCALE__SHIFT 0x0
#define PA_CL_VPORT_YSCALE_7__VPORT_YSCALE_MASK 0xffffffff
#define PA_CL_VPORT_YSCALE_7__VPORT_YSCALE__SHIFT 0x0
#define PA_CL_VPORT_YSCALE_8__VPORT_YSCALE_MASK 0xffffffff
#define PA_CL_VPORT_YSCALE_8__VPORT_YSCALE__SHIFT 0x0
#define PA_CL_VPORT_YSCALE_9__VPORT_YSCALE_MASK 0xffffffff
#define PA_CL_VPORT_YSCALE_9__VPORT_YSCALE__SHIFT 0x0
#define PA_CL_VPORT_YSCALE_10__VPORT_YSCALE_MASK 0xffffffff
#define PA_CL_VPORT_YSCALE_10__VPORT_YSCALE__SHIFT 0x0
#define PA_CL_VPORT_YSCALE_11__VPORT_YSCALE_MASK 0xffffffff
#define PA_CL_VPORT_YSCALE_11__VPORT_YSCALE__SHIFT 0x0
#define PA_CL_VPORT_YSCALE_12__VPORT_YSCALE_MASK 0xffffffff
#define PA_CL_VPORT_YSCALE_12__VPORT_YSCALE__SHIFT 0x0
#define PA_CL_VPORT_YSCALE_13__VPORT_YSCALE_MASK 0xffffffff
#define PA_CL_VPORT_YSCALE_13__VPORT_YSCALE__SHIFT 0x0
#define PA_CL_VPORT_YSCALE_14__VPORT_YSCALE_MASK 0xffffffff
#define PA_CL_VPORT_YSCALE_14__VPORT_YSCALE__SHIFT 0x0
#define PA_CL_VPORT_YSCALE_15__VPORT_YSCALE_MASK 0xffffffff
#define PA_CL_VPORT_YSCALE_15__VPORT_YSCALE__SHIFT 0x0
#define PA_CL_VPORT_YOFFSET_1__VPORT_YOFFSET_MASK 0xffffffff
#define PA_CL_VPORT_YOFFSET_1__VPORT_YOFFSET__SHIFT 0x0
#define PA_CL_VPORT_YOFFSET_2__VPORT_YOFFSET_MASK 0xffffffff
#define PA_CL_VPORT_YOFFSET_2__VPORT_YOFFSET__SHIFT 0x0
#define PA_CL_VPORT_YOFFSET_3__VPORT_YOFFSET_MASK 0xffffffff
#define PA_CL_VPORT_YOFFSET_3__VPORT_YOFFSET__SHIFT 0x0
#define PA_CL_VPORT_YOFFSET_4__VPORT_YOFFSET_MASK 0xffffffff
#define PA_CL_VPORT_YOFFSET_4__VPORT_YOFFSET__SHIFT 0x0
#define PA_CL_VPORT_YOFFSET_5__VPORT_YOFFSET_MASK 0xffffffff
#define PA_CL_VPORT_YOFFSET_5__VPORT_YOFFSET__SHIFT 0x0
#define PA_CL_VPORT_YOFFSET_6__VPORT_YOFFSET_MASK 0xffffffff
#define PA_CL_VPORT_YOFFSET_6__VPORT_YOFFSET__SHIFT 0x0
#define PA_CL_VPORT_YOFFSET_7__VPORT_YOFFSET_MASK 0xffffffff
#define PA_CL_VPORT_YOFFSET_7__VPORT_YOFFSET__SHIFT 0x0
#define PA_CL_VPORT_YOFFSET_8__VPORT_YOFFSET_MASK 0xffffffff
#define PA_CL_VPORT_YOFFSET_8__VPORT_YOFFSET__SHIFT 0x0
#define PA_CL_VPORT_YOFFSET_9__VPORT_YOFFSET_MASK 0xffffffff
#define PA_CL_VPORT_YOFFSET_9__VPORT_YOFFSET__SHIFT 0x0
#define PA_CL_VPORT_YOFFSET_10__VPORT_YOFFSET_MASK 0xffffffff
#define PA_CL_VPORT_YOFFSET_10__VPORT_YOFFSET__SHIFT 0x0
#define PA_CL_VPORT_YOFFSET_11__VPORT_YOFFSET_MASK 0xffffffff
#define PA_CL_VPORT_YOFFSET_11__VPORT_YOFFSET__SHIFT 0x0
#define PA_CL_VPORT_YOFFSET_12__VPORT_YOFFSET_MASK 0xffffffff
#define PA_CL_VPORT_YOFFSET_12__VPORT_YOFFSET__SHIFT 0x0
#define PA_CL_VPORT_YOFFSET_13__VPORT_YOFFSET_MASK 0xffffffff
#define PA_CL_VPORT_YOFFSET_13__VPORT_YOFFSET__SHIFT 0x0
#define PA_CL_VPORT_YOFFSET_14__VPORT_YOFFSET_MASK 0xffffffff
#define PA_CL_VPORT_YOFFSET_14__VPORT_YOFFSET__SHIFT 0x0
#define PA_CL_VPORT_YOFFSET_15__VPORT_YOFFSET_MASK 0xffffffff
#define PA_CL_VPORT_YOFFSET_15__VPORT_YOFFSET__SHIFT 0x0
#define PA_CL_VPORT_ZSCALE_1__VPORT_ZSCALE_MASK 0xffffffff
#define PA_CL_VPORT_ZSCALE_1__VPORT_ZSCALE__SHIFT 0x0
#define PA_CL_VPORT_ZSCALE_2__VPORT_ZSCALE_MASK 0xffffffff
#define PA_CL_VPORT_ZSCALE_2__VPORT_ZSCALE__SHIFT 0x0
#define PA_CL_VPORT_ZSCALE_3__VPORT_ZSCALE_MASK 0xffffffff
#define PA_CL_VPORT_ZSCALE_3__VPORT_ZSCALE__SHIFT 0x0
#define PA_CL_VPORT_ZSCALE_4__VPORT_ZSCALE_MASK 0xffffffff
#define PA_CL_VPORT_ZSCALE_4__VPORT_ZSCALE__SHIFT 0x0
#define PA_CL_VPORT_ZSCALE_5__VPORT_ZSCALE_MASK 0xffffffff
#define PA_CL_VPORT_ZSCALE_5__VPORT_ZSCALE__SHIFT 0x0
#define PA_CL_VPORT_ZSCALE_6__VPORT_ZSCALE_MASK 0xffffffff
#define PA_CL_VPORT_ZSCALE_6__VPORT_ZSCALE__SHIFT 0x0
#define PA_CL_VPORT_ZSCALE_7__VPORT_ZSCALE_MASK 0xffffffff
#define PA_CL_VPORT_ZSCALE_7__VPORT_ZSCALE__SHIFT 0x0
#define PA_CL_VPORT_ZSCALE_8__VPORT_ZSCALE_MASK 0xffffffff
#define PA_CL_VPORT_ZSCALE_8__VPORT_ZSCALE__SHIFT 0x0
#define PA_CL_VPORT_ZSCALE_9__VPORT_ZSCALE_MASK 0xffffffff
#define PA_CL_VPORT_ZSCALE_9__VPORT_ZSCALE__SHIFT 0x0
#define PA_CL_VPORT_ZSCALE_10__VPORT_ZSCALE_MASK 0xffffffff
#define PA_CL_VPORT_ZSCALE_10__VPORT_ZSCALE__SHIFT 0x0
#define PA_CL_VPORT_ZSCALE_11__VPORT_ZSCALE_MASK 0xffffffff
#define PA_CL_VPORT_ZSCALE_11__VPORT_ZSCALE__SHIFT 0x0
#define PA_CL_VPORT_ZSCALE_12__VPORT_ZSCALE_MASK 0xffffffff
#define PA_CL_VPORT_ZSCALE_12__VPORT_ZSCALE__SHIFT 0x0
#define PA_CL_VPORT_ZSCALE_13__VPORT_ZSCALE_MASK 0xffffffff
#define PA_CL_VPORT_ZSCALE_13__VPORT_ZSCALE__SHIFT 0x0
#define PA_CL_VPORT_ZSCALE_14__VPORT_ZSCALE_MASK 0xffffffff
#define PA_CL_VPORT_ZSCALE_14__VPORT_ZSCALE__SHIFT 0x0
#define PA_CL_VPORT_ZSCALE_15__VPORT_ZSCALE_MASK 0xffffffff
#define PA_CL_VPORT_ZSCALE_15__VPORT_ZSCALE__SHIFT 0x0
#define PA_CL_VPORT_ZOFFSET_1__VPORT_ZOFFSET_MASK 0xffffffff
#define PA_CL_VPORT_ZOFFSET_1__VPORT_ZOFFSET__SHIFT 0x0
#define PA_CL_VPORT_ZOFFSET_2__VPORT_ZOFFSET_MASK 0xffffffff
#define PA_CL_VPORT_ZOFFSET_2__VPORT_ZOFFSET__SHIFT 0x0
#define PA_CL_VPORT_ZOFFSET_3__VPORT_ZOFFSET_MASK 0xffffffff
#define PA_CL_VPORT_ZOFFSET_3__VPORT_ZOFFSET__SHIFT 0x0
#define PA_CL_VPORT_ZOFFSET_4__VPORT_ZOFFSET_MASK 0xffffffff
#define PA_CL_VPORT_ZOFFSET_4__VPORT_ZOFFSET__SHIFT 0x0
#define PA_CL_VPORT_ZOFFSET_5__VPORT_ZOFFSET_MASK 0xffffffff
#define PA_CL_VPORT_ZOFFSET_5__VPORT_ZOFFSET__SHIFT 0x0
#define PA_CL_VPORT_ZOFFSET_6__VPORT_ZOFFSET_MASK 0xffffffff
#define PA_CL_VPORT_ZOFFSET_6__VPORT_ZOFFSET__SHIFT 0x0
#define PA_CL_VPORT_ZOFFSET_7__VPORT_ZOFFSET_MASK 0xffffffff
#define PA_CL_VPORT_ZOFFSET_7__VPORT_ZOFFSET__SHIFT 0x0
#define PA_CL_VPORT_ZOFFSET_8__VPORT_ZOFFSET_MASK 0xffffffff
#define PA_CL_VPORT_ZOFFSET_8__VPORT_ZOFFSET__SHIFT 0x0
#define PA_CL_VPORT_ZOFFSET_9__VPORT_ZOFFSET_MASK 0xffffffff
#define PA_CL_VPORT_ZOFFSET_9__VPORT_ZOFFSET__SHIFT 0x0
#define PA_CL_VPORT_ZOFFSET_10__VPORT_ZOFFSET_MASK 0xffffffff
#define PA_CL_VPORT_ZOFFSET_10__VPORT_ZOFFSET__SHIFT 0x0
#define PA_CL_VPORT_ZOFFSET_11__VPORT_ZOFFSET_MASK 0xffffffff
#define PA_CL_VPORT_ZOFFSET_11__VPORT_ZOFFSET__SHIFT 0x0
#define PA_CL_VPORT_ZOFFSET_12__VPORT_ZOFFSET_MASK 0xffffffff
#define PA_CL_VPORT_ZOFFSET_12__VPORT_ZOFFSET__SHIFT 0x0
#define PA_CL_VPORT_ZOFFSET_13__VPORT_ZOFFSET_MASK 0xffffffff
#define PA_CL_VPORT_ZOFFSET_13__VPORT_ZOFFSET__SHIFT 0x0
#define PA_CL_VPORT_ZOFFSET_14__VPORT_ZOFFSET_MASK 0xffffffff
#define PA_CL_VPORT_ZOFFSET_14__VPORT_ZOFFSET__SHIFT 0x0
#define PA_CL_VPORT_ZOFFSET_15__VPORT_ZOFFSET_MASK 0xffffffff
#define PA_CL_VPORT_ZOFFSET_15__VPORT_ZOFFSET__SHIFT 0x0
#define PA_CL_VTE_CNTL__VPORT_X_SCALE_ENA_MASK 0x1
#define PA_CL_VTE_CNTL__VPORT_X_SCALE_ENA__SHIFT 0x0
#define PA_CL_VTE_CNTL__VPORT_X_OFFSET_ENA_MASK 0x2
#define PA_CL_VTE_CNTL__VPORT_X_OFFSET_ENA__SHIFT 0x1
#define PA_CL_VTE_CNTL__VPORT_Y_SCALE_ENA_MASK 0x4
#define PA_CL_VTE_CNTL__VPORT_Y_SCALE_ENA__SHIFT 0x2
#define PA_CL_VTE_CNTL__VPORT_Y_OFFSET_ENA_MASK 0x8
#define PA_CL_VTE_CNTL__VPORT_Y_OFFSET_ENA__SHIFT 0x3
#define PA_CL_VTE_CNTL__VPORT_Z_SCALE_ENA_MASK 0x10
#define PA_CL_VTE_CNTL__VPORT_Z_SCALE_ENA__SHIFT 0x4
#define PA_CL_VTE_CNTL__VPORT_Z_OFFSET_ENA_MASK 0x20
#define PA_CL_VTE_CNTL__VPORT_Z_OFFSET_ENA__SHIFT 0x5
#define PA_CL_VTE_CNTL__VTX_XY_FMT_MASK 0x100
#define PA_CL_VTE_CNTL__VTX_XY_FMT__SHIFT 0x8
#define PA_CL_VTE_CNTL__VTX_Z_FMT_MASK 0x200
#define PA_CL_VTE_CNTL__VTX_Z_FMT__SHIFT 0x9
#define PA_CL_VTE_CNTL__VTX_W0_FMT_MASK 0x400
#define PA_CL_VTE_CNTL__VTX_W0_FMT__SHIFT 0xa
#define PA_CL_VTE_CNTL__PERFCOUNTER_REF_MASK 0x800
#define PA_CL_VTE_CNTL__PERFCOUNTER_REF__SHIFT 0xb
#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_0_MASK 0x1
#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_0__SHIFT 0x0
#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_1_MASK 0x2
#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_1__SHIFT 0x1
#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_2_MASK 0x4
#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_2__SHIFT 0x2
#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_3_MASK 0x8
#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_3__SHIFT 0x3
#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_4_MASK 0x10
#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_4__SHIFT 0x4
#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_5_MASK 0x20
#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_5__SHIFT 0x5
#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_6_MASK 0x40
#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_6__SHIFT 0x6
#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_7_MASK 0x80
#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_7__SHIFT 0x7
#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_0_MASK 0x100
#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_0__SHIFT 0x8
#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_1_MASK 0x200
#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_1__SHIFT 0x9
#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_2_MASK 0x400
#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_2__SHIFT 0xa
#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_3_MASK 0x800
#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_3__SHIFT 0xb
#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_4_MASK 0x1000
#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_4__SHIFT 0xc
#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_5_MASK 0x2000
#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_5__SHIFT 0xd
#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_6_MASK 0x4000
#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_6__SHIFT 0xe
#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_7_MASK 0x8000
#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_7__SHIFT 0xf
#define PA_CL_VS_OUT_CNTL__USE_VTX_POINT_SIZE_MASK 0x10000
#define PA_CL_VS_OUT_CNTL__USE_VTX_POINT_SIZE__SHIFT 0x10
#define PA_CL_VS_OUT_CNTL__USE_VTX_EDGE_FLAG_MASK 0x20000
#define PA_CL_VS_OUT_CNTL__USE_VTX_EDGE_FLAG__SHIFT 0x11
#define PA_CL_VS_OUT_CNTL__USE_VTX_RENDER_TARGET_INDX_MASK 0x40000
#define PA_CL_VS_OUT_CNTL__USE_VTX_RENDER_TARGET_INDX__SHIFT 0x12
#define PA_CL_VS_OUT_CNTL__USE_VTX_VIEWPORT_INDX_MASK 0x80000
#define PA_CL_VS_OUT_CNTL__USE_VTX_VIEWPORT_INDX__SHIFT 0x13
#define PA_CL_VS_OUT_CNTL__USE_VTX_KILL_FLAG_MASK 0x100000
#define PA_CL_VS_OUT_CNTL__USE_VTX_KILL_FLAG__SHIFT 0x14
#define PA_CL_VS_OUT_CNTL__VS_OUT_MISC_VEC_ENA_MASK 0x200000
#define PA_CL_VS_OUT_CNTL__VS_OUT_MISC_VEC_ENA__SHIFT 0x15
#define PA_CL_VS_OUT_CNTL__VS_OUT_CCDIST0_VEC_ENA_MASK 0x400000
#define PA_CL_VS_OUT_CNTL__VS_OUT_CCDIST0_VEC_ENA__SHIFT 0x16
#define PA_CL_VS_OUT_CNTL__VS_OUT_CCDIST1_VEC_ENA_MASK 0x800000
#define PA_CL_VS_OUT_CNTL__VS_OUT_CCDIST1_VEC_ENA__SHIFT 0x17
#define PA_CL_VS_OUT_CNTL__VS_OUT_MISC_SIDE_BUS_ENA_MASK 0x1000000
#define PA_CL_VS_OUT_CNTL__VS_OUT_MISC_SIDE_BUS_ENA__SHIFT 0x18
#define PA_CL_VS_OUT_CNTL__USE_VTX_GS_CUT_FLAG_MASK 0x2000000
#define PA_CL_VS_OUT_CNTL__USE_VTX_GS_CUT_FLAG__SHIFT 0x19
#define PA_CL_VS_OUT_CNTL__USE_VTX_LINE_WIDTH_MASK 0x4000000
#define PA_CL_VS_OUT_CNTL__USE_VTX_LINE_WIDTH__SHIFT 0x1a
#define PA_CL_NANINF_CNTL__VTE_XY_INF_DISCARD_MASK 0x1
#define PA_CL_NANINF_CNTL__VTE_XY_INF_DISCARD__SHIFT 0x0
#define PA_CL_NANINF_CNTL__VTE_Z_INF_DISCARD_MASK 0x2
#define PA_CL_NANINF_CNTL__VTE_Z_INF_DISCARD__SHIFT 0x1
#define PA_CL_NANINF_CNTL__VTE_W_INF_DISCARD_MASK 0x4
#define PA_CL_NANINF_CNTL__VTE_W_INF_DISCARD__SHIFT 0x2
#define PA_CL_NANINF_CNTL__VTE_0XNANINF_IS_0_MASK 0x8
#define PA_CL_NANINF_CNTL__VTE_0XNANINF_IS_0__SHIFT 0x3
#define PA_CL_NANINF_CNTL__VTE_XY_NAN_RETAIN_MASK 0x10
#define PA_CL_NANINF_CNTL__VTE_XY_NAN_RETAIN__SHIFT 0x4
#define PA_CL_NANINF_CNTL__VTE_Z_NAN_RETAIN_MASK 0x20
#define PA_CL_NANINF_CNTL__VTE_Z_NAN_RETAIN__SHIFT 0x5
#define PA_CL_NANINF_CNTL__VTE_W_NAN_RETAIN_MASK 0x40
#define PA_CL_NANINF_CNTL__VTE_W_NAN_RETAIN__SHIFT 0x6
#define PA_CL_NANINF_CNTL__VTE_W_RECIP_NAN_IS_0_MASK 0x80
#define PA_CL_NANINF_CNTL__VTE_W_RECIP_NAN_IS_0__SHIFT 0x7
#define PA_CL_NANINF_CNTL__VS_XY_NAN_TO_INF_MASK 0x100
#define PA_CL_NANINF_CNTL__VS_XY_NAN_TO_INF__SHIFT 0x8
#define PA_CL_NANINF_CNTL__VS_XY_INF_RETAIN_MASK 0x200
#define PA_CL_NANINF_CNTL__VS_XY_INF_RETAIN__SHIFT 0x9
#define PA_CL_NANINF_CNTL__VS_Z_NAN_TO_INF_MASK 0x400
#define PA_CL_NANINF_CNTL__VS_Z_NAN_TO_INF__SHIFT 0xa
#define PA_CL_NANINF_CNTL__VS_Z_INF_RETAIN_MASK 0x800
#define PA_CL_NANINF_CNTL__VS_Z_INF_RETAIN__SHIFT 0xb
#define PA_CL_NANINF_CNTL__VS_W_NAN_TO_INF_MASK 0x1000
#define PA_CL_NANINF_CNTL__VS_W_NAN_TO_INF__SHIFT 0xc
#define PA_CL_NANINF_CNTL__VS_W_INF_RETAIN_MASK 0x2000
#define PA_CL_NANINF_CNTL__VS_W_INF_RETAIN__SHIFT 0xd
#define PA_CL_NANINF_CNTL__VS_CLIP_DIST_INF_DISCARD_MASK 0x4000
#define PA_CL_NANINF_CNTL__VS_CLIP_DIST_INF_DISCARD__SHIFT 0xe
#define PA_CL_NANINF_CNTL__VTE_NO_OUTPUT_NEG_0_MASK 0x100000
#define PA_CL_NANINF_CNTL__VTE_NO_OUTPUT_NEG_0__SHIFT 0x14
#define PA_CL_CLIP_CNTL__UCP_ENA_0_MASK 0x1
#define PA_CL_CLIP_CNTL__UCP_ENA_0__SHIFT 0x0
#define PA_CL_CLIP_CNTL__UCP_ENA_1_MASK 0x2
#define PA_CL_CLIP_CNTL__UCP_ENA_1__SHIFT 0x1
#define PA_CL_CLIP_CNTL__UCP_ENA_2_MASK 0x4
#define PA_CL_CLIP_CNTL__UCP_ENA_2__SHIFT 0x2
#define PA_CL_CLIP_CNTL__UCP_ENA_3_MASK 0x8
#define PA_CL_CLIP_CNTL__UCP_ENA_3__SHIFT 0x3
#define PA_CL_CLIP_CNTL__UCP_ENA_4_MASK 0x10
#define PA_CL_CLIP_CNTL__UCP_ENA_4__SHIFT 0x4
#define PA_CL_CLIP_CNTL__UCP_ENA_5_MASK 0x20
#define PA_CL_CLIP_CNTL__UCP_ENA_5__SHIFT 0x5
#define PA_CL_CLIP_CNTL__PS_UCP_Y_SCALE_NEG_MASK 0x2000
#define PA_CL_CLIP_CNTL__PS_UCP_Y_SCALE_NEG__SHIFT 0xd
#define PA_CL_CLIP_CNTL__PS_UCP_MODE_MASK 0xc000
#define PA_CL_CLIP_CNTL__PS_UCP_MODE__SHIFT 0xe
#define PA_CL_CLIP_CNTL__CLIP_DISABLE_MASK 0x10000
#define PA_CL_CLIP_CNTL__CLIP_DISABLE__SHIFT 0x10
#define PA_CL_CLIP_CNTL__UCP_CULL_ONLY_ENA_MASK 0x20000
#define PA_CL_CLIP_CNTL__UCP_CULL_ONLY_ENA__SHIFT 0x11
#define PA_CL_CLIP_CNTL__BOUNDARY_EDGE_FLAG_ENA_MASK 0x40000
#define PA_CL_CLIP_CNTL__BOUNDARY_EDGE_FLAG_ENA__SHIFT 0x12
#define PA_CL_CLIP_CNTL__DX_CLIP_SPACE_DEF_MASK 0x80000
#define PA_CL_CLIP_CNTL__DX_CLIP_SPACE_DEF__SHIFT 0x13
#define PA_CL_CLIP_CNTL__DIS_CLIP_ERR_DETECT_MASK 0x100000
#define PA_CL_CLIP_CNTL__DIS_CLIP_ERR_DETECT__SHIFT 0x14
#define PA_CL_CLIP_CNTL__VTX_KILL_OR_MASK 0x200000
#define PA_CL_CLIP_CNTL__VTX_KILL_OR__SHIFT 0x15
#define PA_CL_CLIP_CNTL__DX_RASTERIZATION_KILL_MASK 0x400000
#define PA_CL_CLIP_CNTL__DX_RASTERIZATION_KILL__SHIFT 0x16
#define PA_CL_CLIP_CNTL__DX_LINEAR_ATTR_CLIP_ENA_MASK 0x1000000
#define PA_CL_CLIP_CNTL__DX_LINEAR_ATTR_CLIP_ENA__SHIFT 0x18
#define PA_CL_CLIP_CNTL__VTE_VPORT_PROVOKE_DISABLE_MASK 0x2000000
#define PA_CL_CLIP_CNTL__VTE_VPORT_PROVOKE_DISABLE__SHIFT 0x19
#define PA_CL_CLIP_CNTL__ZCLIP_NEAR_DISABLE_MASK 0x4000000
#define PA_CL_CLIP_CNTL__ZCLIP_NEAR_DISABLE__SHIFT 0x1a
#define PA_CL_CLIP_CNTL__ZCLIP_FAR_DISABLE_MASK 0x8000000
#define PA_CL_CLIP_CNTL__ZCLIP_FAR_DISABLE__SHIFT 0x1b
#define PA_CL_GB_VERT_CLIP_ADJ__DATA_REGISTER_MASK 0xffffffff
#define PA_CL_GB_VERT_CLIP_ADJ__DATA_REGISTER__SHIFT 0x0
#define PA_CL_GB_VERT_DISC_ADJ__DATA_REGISTER_MASK 0xffffffff
#define PA_CL_GB_VERT_DISC_ADJ__DATA_REGISTER__SHIFT 0x0
#define PA_CL_GB_HORZ_CLIP_ADJ__DATA_REGISTER_MASK 0xffffffff
#define PA_CL_GB_HORZ_CLIP_ADJ__DATA_REGISTER__SHIFT 0x0
#define PA_CL_GB_HORZ_DISC_ADJ__DATA_REGISTER_MASK 0xffffffff
#define PA_CL_GB_HORZ_DISC_ADJ__DATA_REGISTER__SHIFT 0x0
#define PA_CL_UCP_0_X__DATA_REGISTER_MASK 0xffffffff
#define PA_CL_UCP_0_X__DATA_REGISTER__SHIFT 0x0
#define PA_CL_UCP_0_Y__DATA_REGISTER_MASK 0xffffffff
#define PA_CL_UCP_0_Y__DATA_REGISTER__SHIFT 0x0
#define PA_CL_UCP_0_Z__DATA_REGISTER_MASK 0xffffffff
#define PA_CL_UCP_0_Z__DATA_REGISTER__SHIFT 0x0
#define PA_CL_UCP_0_W__DATA_REGISTER_MASK 0xffffffff
#define PA_CL_UCP_0_W__DATA_REGISTER__SHIFT 0x0
#define PA_CL_UCP_1_X__DATA_REGISTER_MASK 0xffffffff
#define PA_CL_UCP_1_X__DATA_REGISTER__SHIFT 0x0
#define PA_CL_UCP_1_Y__DATA_REGISTER_MASK 0xffffffff
#define PA_CL_UCP_1_Y__DATA_REGISTER__SHIFT 0x0
#define PA_CL_UCP_1_Z__DATA_REGISTER_MASK 0xffffffff
#define PA_CL_UCP_1_Z__DATA_REGISTER__SHIFT 0x0
#define PA_CL_UCP_1_W__DATA_REGISTER_MASK 0xffffffff
#define PA_CL_UCP_1_W__DATA_REGISTER__SHIFT 0x0
#define PA_CL_UCP_2_X__DATA_REGISTER_MASK 0xffffffff
#define PA_CL_UCP_2_X__DATA_REGISTER__SHIFT 0x0
#define PA_CL_UCP_2_Y__DATA_REGISTER_MASK 0xffffffff
#define PA_CL_UCP_2_Y__DATA_REGISTER__SHIFT 0x0
#define PA_CL_UCP_2_Z__DATA_REGISTER_MASK 0xffffffff
#define PA_CL_UCP_2_Z__DATA_REGISTER__SHIFT 0x0
#define PA_CL_UCP_2_W__DATA_REGISTER_MASK 0xffffffff
#define PA_CL_UCP_2_W__DATA_REGISTER__SHIFT 0x0
#define PA_CL_UCP_3_X__DATA_REGISTER_MASK 0xffffffff
#define PA_CL_UCP_3_X__DATA_REGISTER__SHIFT 0x0
#define PA_CL_UCP_3_Y__DATA_REGISTER_MASK 0xffffffff
#define PA_CL_UCP_3_Y__DATA_REGISTER__SHIFT 0x0
#define PA_CL_UCP_3_Z__DATA_REGISTER_MASK 0xffffffff
#define PA_CL_UCP_3_Z__DATA_REGISTER__SHIFT 0x0
#define PA_CL_UCP_3_W__DATA_REGISTER_MASK 0xffffffff
#define PA_CL_UCP_3_W__DATA_REGISTER__SHIFT 0x0
#define PA_CL_UCP_4_X__DATA_REGISTER_MASK 0xffffffff
#define PA_CL_UCP_4_X__DATA_REGISTER__SHIFT 0x0
#define PA_CL_UCP_4_Y__DATA_REGISTER_MASK 0xffffffff
#define PA_CL_UCP_4_Y__DATA_REGISTER__SHIFT 0x0
#define PA_CL_UCP_4_Z__DATA_REGISTER_MASK 0xffffffff
#define PA_CL_UCP_4_Z__DATA_REGISTER__SHIFT 0x0
#define PA_CL_UCP_4_W__DATA_REGISTER_MASK 0xffffffff
#define PA_CL_UCP_4_W__DATA_REGISTER__SHIFT 0x0
#define PA_CL_UCP_5_X__DATA_REGISTER_MASK 0xffffffff
#define PA_CL_UCP_5_X__DATA_REGISTER__SHIFT 0x0
#define PA_CL_UCP_5_Y__DATA_REGISTER_MASK 0xffffffff
#define PA_CL_UCP_5_Y__DATA_REGISTER__SHIFT 0x0
#define PA_CL_UCP_5_Z__DATA_REGISTER_MASK 0xffffffff
#define PA_CL_UCP_5_Z__DATA_REGISTER__SHIFT 0x0
#define PA_CL_UCP_5_W__DATA_REGISTER_MASK 0xffffffff
#define PA_CL_UCP_5_W__DATA_REGISTER__SHIFT 0x0
#define PA_CL_POINT_X_RAD__DATA_REGISTER_MASK 0xffffffff
#define PA_CL_POINT_X_RAD__DATA_REGISTER__SHIFT 0x0
#define PA_CL_POINT_Y_RAD__DATA_REGISTER_MASK 0xffffffff
#define PA_CL_POINT_Y_RAD__DATA_REGISTER__SHIFT 0x0
#define PA_CL_POINT_SIZE__DATA_REGISTER_MASK 0xffffffff
#define PA_CL_POINT_SIZE__DATA_REGISTER__SHIFT 0x0
#define PA_CL_POINT_CULL_RAD__DATA_REGISTER_MASK 0xffffffff
#define PA_CL_POINT_CULL_RAD__DATA_REGISTER__SHIFT 0x0
#define PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA_MASK 0x1
#define PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA__SHIFT 0x0
#define PA_CL_ENHANCE__NUM_CLIP_SEQ_MASK 0x6
#define PA_CL_ENHANCE__NUM_CLIP_SEQ__SHIFT 0x1
#define PA_CL_ENHANCE__CLIPPED_PRIM_SEQ_STALL_MASK 0x8
#define PA_CL_ENHANCE__CLIPPED_PRIM_SEQ_STALL__SHIFT 0x3
#define PA_CL_ENHANCE__VE_NAN_PROC_DISABLE_MASK 0x10
#define PA_CL_ENHANCE__VE_NAN_PROC_DISABLE__SHIFT 0x4
#define PA_CL_ENHANCE__XTRA_DEBUG_REG_SEL_MASK 0x20
#define PA_CL_ENHANCE__XTRA_DEBUG_REG_SEL__SHIFT 0x5
#define PA_CL_ENHANCE__ECO_SPARE3_MASK 0x10000000
#define PA_CL_ENHANCE__ECO_SPARE3__SHIFT 0x1c
#define PA_CL_ENHANCE__ECO_SPARE2_MASK 0x20000000
#define PA_CL_ENHANCE__ECO_SPARE2__SHIFT 0x1d
#define PA_CL_ENHANCE__ECO_SPARE1_MASK 0x40000000
#define PA_CL_ENHANCE__ECO_SPARE1__SHIFT 0x1e
#define PA_CL_ENHANCE__ECO_SPARE0_MASK 0x80000000
#define PA_CL_ENHANCE__ECO_SPARE0__SHIFT 0x1f
#define PA_CL_RESET_DEBUG__CL_TRIV_DISC_DISABLE_MASK 0x1
#define PA_CL_RESET_DEBUG__CL_TRIV_DISC_DISABLE__SHIFT 0x0
#define PA_SU_VTX_CNTL__PIX_CENTER_MASK 0x1
#define PA_SU_VTX_CNTL__PIX_CENTER__SHIFT 0x0
#define PA_SU_VTX_CNTL__ROUND_MODE_MASK 0x6
#define PA_SU_VTX_CNTL__ROUND_MODE__SHIFT 0x1
#define PA_SU_VTX_CNTL__QUANT_MODE_MASK 0x38
#define PA_SU_VTX_CNTL__QUANT_MODE__SHIFT 0x3
#define PA_SU_POINT_SIZE__HEIGHT_MASK 0xffff
#define PA_SU_POINT_SIZE__HEIGHT__SHIFT 0x0
#define PA_SU_POINT_SIZE__WIDTH_MASK 0xffff0000
#define PA_SU_POINT_SIZE__WIDTH__SHIFT 0x10
#define PA_SU_POINT_MINMAX__MIN_SIZE_MASK 0xffff
#define PA_SU_POINT_MINMAX__MIN_SIZE__SHIFT 0x0
#define PA_SU_POINT_MINMAX__MAX_SIZE_MASK 0xffff0000
#define PA_SU_POINT_MINMAX__MAX_SIZE__SHIFT 0x10
#define PA_SU_LINE_CNTL__WIDTH_MASK 0xffff
#define PA_SU_LINE_CNTL__WIDTH__SHIFT 0x0
#define PA_SU_LINE_STIPPLE_CNTL__LINE_STIPPLE_RESET_MASK 0x3
#define PA_SU_LINE_STIPPLE_CNTL__LINE_STIPPLE_RESET__SHIFT 0x0
#define PA_SU_LINE_STIPPLE_CNTL__EXPAND_FULL_LENGTH_MASK 0x4
#define PA_SU_LINE_STIPPLE_CNTL__EXPAND_FULL_LENGTH__SHIFT 0x2
#define PA_SU_LINE_STIPPLE_CNTL__FRACTIONAL_ACCUM_MASK 0x8
#define PA_SU_LINE_STIPPLE_CNTL__FRACTIONAL_ACCUM__SHIFT 0x3
#define PA_SU_LINE_STIPPLE_CNTL__DIAMOND_ADJUST_MASK 0x10
#define PA_SU_LINE_STIPPLE_CNTL__DIAMOND_ADJUST__SHIFT 0x4
#define PA_SU_LINE_STIPPLE_SCALE__LINE_STIPPLE_SCALE_MASK 0xffffffff
#define PA_SU_LINE_STIPPLE_SCALE__LINE_STIPPLE_SCALE__SHIFT 0x0
#define PA_SU_PRIM_FILTER_CNTL__TRIANGLE_FILTER_DISABLE_MASK 0x1
#define PA_SU_PRIM_FILTER_CNTL__TRIANGLE_FILTER_DISABLE__SHIFT 0x0
#define PA_SU_PRIM_FILTER_CNTL__LINE_FILTER_DISABLE_MASK 0x2
#define PA_SU_PRIM_FILTER_CNTL__LINE_FILTER_DISABLE__SHIFT 0x1
#define PA_SU_PRIM_FILTER_CNTL__POINT_FILTER_DISABLE_MASK 0x4
#define PA_SU_PRIM_FILTER_CNTL__POINT_FILTER_DISABLE__SHIFT 0x2
#define PA_SU_PRIM_FILTER_CNTL__RECTANGLE_FILTER_DISABLE_MASK 0x8
#define PA_SU_PRIM_FILTER_CNTL__RECTANGLE_FILTER_DISABLE__SHIFT 0x3
#define PA_SU_PRIM_FILTER_CNTL__TRIANGLE_EXPAND_ENA_MASK 0x10
#define PA_SU_PRIM_FILTER_CNTL__TRIANGLE_EXPAND_ENA__SHIFT 0x4
#define PA_SU_PRIM_FILTER_CNTL__LINE_EXPAND_ENA_MASK 0x20
#define PA_SU_PRIM_FILTER_CNTL__LINE_EXPAND_ENA__SHIFT 0x5
#define PA_SU_PRIM_FILTER_CNTL__POINT_EXPAND_ENA_MASK 0x40
#define PA_SU_PRIM_FILTER_CNTL__POINT_EXPAND_ENA__SHIFT 0x6
#define PA_SU_PRIM_FILTER_CNTL__RECTANGLE_EXPAND_ENA_MASK 0x80
#define PA_SU_PRIM_FILTER_CNTL__RECTANGLE_EXPAND_ENA__SHIFT 0x7
#define PA_SU_PRIM_FILTER_CNTL__PRIM_EXPAND_CONSTANT_MASK 0xff00
#define PA_SU_PRIM_FILTER_CNTL__PRIM_EXPAND_CONSTANT__SHIFT 0x8
#define PA_SU_PRIM_FILTER_CNTL__XMAX_RIGHT_EXCLUSION_MASK 0x40000000
#define PA_SU_PRIM_FILTER_CNTL__XMAX_RIGHT_EXCLUSION__SHIFT 0x1e
#define PA_SU_PRIM_FILTER_CNTL__YMAX_BOTTOM_EXCLUSION_MASK 0x80000000
#define PA_SU_PRIM_FILTER_CNTL__YMAX_BOTTOM_EXCLUSION__SHIFT 0x1f
#define PA_SU_SC_MODE_CNTL__CULL_FRONT_MASK 0x1
#define PA_SU_SC_MODE_CNTL__CULL_FRONT__SHIFT 0x0
#define PA_SU_SC_MODE_CNTL__CULL_BACK_MASK 0x2
#define PA_SU_SC_MODE_CNTL__CULL_BACK__SHIFT 0x1
#define PA_SU_SC_MODE_CNTL__FACE_MASK 0x4
#define PA_SU_SC_MODE_CNTL__FACE__SHIFT 0x2
#define PA_SU_SC_MODE_CNTL__POLY_MODE_MASK 0x18
#define PA_SU_SC_MODE_CNTL__POLY_MODE__SHIFT 0x3
#define PA_SU_SC_MODE_CNTL__POLYMODE_FRONT_PTYPE_MASK 0xe0
#define PA_SU_SC_MODE_CNTL__POLYMODE_FRONT_PTYPE__SHIFT 0x5
#define PA_SU_SC_MODE_CNTL__POLYMODE_BACK_PTYPE_MASK 0x700
#define PA_SU_SC_MODE_CNTL__POLYMODE_BACK_PTYPE__SHIFT 0x8
#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_FRONT_ENABLE_MASK 0x800
#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_FRONT_ENABLE__SHIFT 0xb
#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_BACK_ENABLE_MASK 0x1000
#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_BACK_ENABLE__SHIFT 0xc
#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_PARA_ENABLE_MASK 0x2000
#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_PARA_ENABLE__SHIFT 0xd
#define PA_SU_SC_MODE_CNTL__VTX_WINDOW_OFFSET_ENABLE_MASK 0x10000
#define PA_SU_SC_MODE_CNTL__VTX_WINDOW_OFFSET_ENABLE__SHIFT 0x10
#define PA_SU_SC_MODE_CNTL__PROVOKING_VTX_LAST_MASK 0x80000
#define PA_SU_SC_MODE_CNTL__PROVOKING_VTX_LAST__SHIFT 0x13
#define PA_SU_SC_MODE_CNTL__PERSP_CORR_DIS_MASK 0x100000
#define PA_SU_SC_MODE_CNTL__PERSP_CORR_DIS__SHIFT 0x14
#define PA_SU_SC_MODE_CNTL__MULTI_PRIM_IB_ENA_MASK 0x200000
#define PA_SU_SC_MODE_CNTL__MULTI_PRIM_IB_ENA__SHIFT 0x15
#define PA_SU_POLY_OFFSET_DB_FMT_CNTL__POLY_OFFSET_NEG_NUM_DB_BITS_MASK 0xff
#define PA_SU_POLY_OFFSET_DB_FMT_CNTL__POLY_OFFSET_NEG_NUM_DB_BITS__SHIFT 0x0
#define PA_SU_POLY_OFFSET_DB_FMT_CNTL__POLY_OFFSET_DB_IS_FLOAT_FMT_MASK 0x100
#define PA_SU_POLY_OFFSET_DB_FMT_CNTL__POLY_OFFSET_DB_IS_FLOAT_FMT__SHIFT 0x8
#define PA_SU_POLY_OFFSET_CLAMP__CLAMP_MASK 0xffffffff
#define PA_SU_POLY_OFFSET_CLAMP__CLAMP__SHIFT 0x0
#define PA_SU_POLY_OFFSET_FRONT_SCALE__SCALE_MASK 0xffffffff
#define PA_SU_POLY_OFFSET_FRONT_SCALE__SCALE__SHIFT 0x0
#define PA_SU_POLY_OFFSET_FRONT_OFFSET__OFFSET_MASK 0xffffffff
#define PA_SU_POLY_OFFSET_FRONT_OFFSET__OFFSET__SHIFT 0x0
#define PA_SU_POLY_OFFSET_BACK_SCALE__SCALE_MASK 0xffffffff
#define PA_SU_POLY_OFFSET_BACK_SCALE__SCALE__SHIFT 0x0
#define PA_SU_POLY_OFFSET_BACK_OFFSET__OFFSET_MASK 0xffffffff
#define PA_SU_POLY_OFFSET_BACK_OFFSET__OFFSET__SHIFT 0x0
#define PA_SU_HARDWARE_SCREEN_OFFSET__HW_SCREEN_OFFSET_X_MASK 0x1ff
#define PA_SU_HARDWARE_SCREEN_OFFSET__HW_SCREEN_OFFSET_X__SHIFT 0x0
#define PA_SU_HARDWARE_SCREEN_OFFSET__HW_SCREEN_OFFSET_Y_MASK 0x1ff0000
#define PA_SU_HARDWARE_SCREEN_OFFSET__HW_SCREEN_OFFSET_Y__SHIFT 0x10
#define PA_SU_LINE_STIPPLE_VALUE__LINE_STIPPLE_VALUE_MASK 0xffffff
#define PA_SU_LINE_STIPPLE_VALUE__LINE_STIPPLE_VALUE__SHIFT 0x0
#define PA_SU_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x3ff
#define PA_SU_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
#define PA_SU_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0xffc00
#define PA_SU_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
#define PA_SU_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000
#define PA_SU_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
#define PA_SU_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x3ff
#define PA_SU_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0
#define PA_SU_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0xffc00
#define PA_SU_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
#define PA_SU_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x3ff
#define PA_SU_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
#define PA_SU_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0xffc00
#define PA_SU_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa
#define PA_SU_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0xf00000
#define PA_SU_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14
#define PA_SU_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x3ff
#define PA_SU_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0
#define PA_SU_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0xffc00
#define PA_SU_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa
#define PA_SU_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x3ff
#define PA_SU_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0
#define PA_SU_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0xf00000
#define PA_SU_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14
#define PA_SU_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x3ff
#define PA_SU_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0
#define PA_SU_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0xf00000
#define PA_SU_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14
#define PA_SU_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff
#define PA_SU_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
#define PA_SU_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffff
#define PA_SU_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
#define PA_SU_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff
#define PA_SU_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
#define PA_SU_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffff
#define PA_SU_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
#define PA_SU_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffff
#define PA_SU_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0
#define PA_SU_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffff
#define PA_SU_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0
#define PA_SU_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffff
#define PA_SU_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0
#define PA_SU_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffff
#define PA_SU_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0
#define PA_SC_AA_CONFIG__MSAA_NUM_SAMPLES_MASK 0x7
#define PA_SC_AA_CONFIG__MSAA_NUM_SAMPLES__SHIFT 0x0
#define PA_SC_AA_CONFIG__AA_MASK_CENTROID_DTMN_MASK 0x10
#define PA_SC_AA_CONFIG__AA_MASK_CENTROID_DTMN__SHIFT 0x4
#define PA_SC_AA_CONFIG__MAX_SAMPLE_DIST_MASK 0x1e000
#define PA_SC_AA_CONFIG__MAX_SAMPLE_DIST__SHIFT 0xd
#define PA_SC_AA_CONFIG__MSAA_EXPOSED_SAMPLES_MASK 0x700000
#define PA_SC_AA_CONFIG__MSAA_EXPOSED_SAMPLES__SHIFT 0x14
#define PA_SC_AA_CONFIG__DETAIL_TO_EXPOSED_MODE_MASK 0x3000000
#define PA_SC_AA_CONFIG__DETAIL_TO_EXPOSED_MODE__SHIFT 0x18
#define PA_SC_AA_MASK_X0Y0_X1Y0__AA_MASK_X0Y0_MASK 0xffff
#define PA_SC_AA_MASK_X0Y0_X1Y0__AA_MASK_X0Y0__SHIFT 0x0
#define PA_SC_AA_MASK_X0Y0_X1Y0__AA_MASK_X1Y0_MASK 0xffff0000
#define PA_SC_AA_MASK_X0Y0_X1Y0__AA_MASK_X1Y0__SHIFT 0x10
#define PA_SC_AA_MASK_X0Y1_X1Y1__AA_MASK_X0Y1_MASK 0xffff
#define PA_SC_AA_MASK_X0Y1_X1Y1__AA_MASK_X0Y1__SHIFT 0x0
#define PA_SC_AA_MASK_X0Y1_X1Y1__AA_MASK_X1Y1_MASK 0xffff0000
#define PA_SC_AA_MASK_X0Y1_X1Y1__AA_MASK_X1Y1__SHIFT 0x10
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S0_X_MASK 0xf
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S0_X__SHIFT 0x0
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S0_Y_MASK 0xf0
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S0_Y__SHIFT 0x4
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S1_X_MASK 0xf00
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S1_X__SHIFT 0x8
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S1_Y_MASK 0xf000
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S1_Y__SHIFT 0xc
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S2_X_MASK 0xf0000
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S2_X__SHIFT 0x10
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S2_Y_MASK 0xf00000
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S2_Y__SHIFT 0x14
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S3_X_MASK 0xf000000
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S3_X__SHIFT 0x18
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S3_Y_MASK 0xf0000000
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S3_Y__SHIFT 0x1c
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S4_X_MASK 0xf
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S4_X__SHIFT 0x0
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S4_Y_MASK 0xf0
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S4_Y__SHIFT 0x4
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S5_X_MASK 0xf00
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S5_X__SHIFT 0x8
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S5_Y_MASK 0xf000
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S5_Y__SHIFT 0xc
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S6_X_MASK 0xf0000
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S6_X__SHIFT 0x10
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S6_Y_MASK 0xf00000
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S6_Y__SHIFT 0x14
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S7_X_MASK 0xf000000
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S7_X__SHIFT 0x18
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S7_Y_MASK 0xf0000000
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S7_Y__SHIFT 0x1c
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S8_X_MASK 0xf
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S8_X__SHIFT 0x0
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S8_Y_MASK 0xf0
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S8_Y__SHIFT 0x4
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S9_X_MASK 0xf00
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S9_X__SHIFT 0x8
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S9_Y_MASK 0xf000
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S9_Y__SHIFT 0xc
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S10_X_MASK 0xf0000
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S10_X__SHIFT 0x10
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S10_Y_MASK 0xf00000
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S10_Y__SHIFT 0x14
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S11_X_MASK 0xf000000
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S11_X__SHIFT 0x18
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S11_Y_MASK 0xf0000000
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S11_Y__SHIFT 0x1c
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S12_X_MASK 0xf
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S12_X__SHIFT 0x0
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S12_Y_MASK 0xf0
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S12_Y__SHIFT 0x4
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S13_X_MASK 0xf00
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S13_X__SHIFT 0x8
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S13_Y_MASK 0xf000
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S13_Y__SHIFT 0xc
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S14_X_MASK 0xf0000
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S14_X__SHIFT 0x10
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S14_Y_MASK 0xf00000
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S14_Y__SHIFT 0x14
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S15_X_MASK 0xf000000
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S15_X__SHIFT 0x18
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S15_Y_MASK 0xf0000000
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S15_Y__SHIFT 0x1c
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S0_X_MASK 0xf
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S0_X__SHIFT 0x0
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S0_Y_MASK 0xf0
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S0_Y__SHIFT 0x4
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S1_X_MASK 0xf00
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S1_X__SHIFT 0x8
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S1_Y_MASK 0xf000
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S1_Y__SHIFT 0xc
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S2_X_MASK 0xf0000
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S2_X__SHIFT 0x10
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S2_Y_MASK 0xf00000
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S2_Y__SHIFT 0x14
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S3_X_MASK 0xf000000
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S3_X__SHIFT 0x18
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S3_Y_MASK 0xf0000000
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S3_Y__SHIFT 0x1c
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S4_X_MASK 0xf
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S4_X__SHIFT 0x0
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S4_Y_MASK 0xf0
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S4_Y__SHIFT 0x4
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S5_X_MASK 0xf00
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S5_X__SHIFT 0x8
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S5_Y_MASK 0xf000
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S5_Y__SHIFT 0xc
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S6_X_MASK 0xf0000
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S6_X__SHIFT 0x10
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S6_Y_MASK 0xf00000
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S6_Y__SHIFT 0x14
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S7_X_MASK 0xf000000
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S7_X__SHIFT 0x18
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S7_Y_MASK 0xf0000000
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S7_Y__SHIFT 0x1c
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S8_X_MASK 0xf
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S8_X__SHIFT 0x0
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S8_Y_MASK 0xf0
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S8_Y__SHIFT 0x4
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S9_X_MASK 0xf00
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S9_X__SHIFT 0x8
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S9_Y_MASK 0xf000
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S9_Y__SHIFT 0xc
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S10_X_MASK 0xf0000
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S10_X__SHIFT 0x10
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S10_Y_MASK 0xf00000
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S10_Y__SHIFT 0x14
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S11_X_MASK 0xf000000
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S11_X__SHIFT 0x18
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S11_Y_MASK 0xf0000000
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S11_Y__SHIFT 0x1c
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S12_X_MASK 0xf
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S12_X__SHIFT 0x0
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S12_Y_MASK 0xf0
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S12_Y__SHIFT 0x4
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S13_X_MASK 0xf00
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S13_X__SHIFT 0x8
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S13_Y_MASK 0xf000
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S13_Y__SHIFT 0xc
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S14_X_MASK 0xf0000
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S14_X__SHIFT 0x10
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S14_Y_MASK 0xf00000
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S14_Y__SHIFT 0x14
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S15_X_MASK 0xf000000
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S15_X__SHIFT 0x18
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S15_Y_MASK 0xf0000000
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S15_Y__SHIFT 0x1c
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S0_X_MASK 0xf
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S0_X__SHIFT 0x0
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S0_Y_MASK 0xf0
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S0_Y__SHIFT 0x4
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S1_X_MASK 0xf00
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S1_X__SHIFT 0x8
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S1_Y_MASK 0xf000
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S1_Y__SHIFT 0xc
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S2_X_MASK 0xf0000
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S2_X__SHIFT 0x10
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S2_Y_MASK 0xf00000
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S2_Y__SHIFT 0x14
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S3_X_MASK 0xf000000
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S3_X__SHIFT 0x18
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S3_Y_MASK 0xf0000000
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S3_Y__SHIFT 0x1c
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S4_X_MASK 0xf
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S4_X__SHIFT 0x0
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S4_Y_MASK 0xf0
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S4_Y__SHIFT 0x4
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S5_X_MASK 0xf00
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S5_X__SHIFT 0x8
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S5_Y_MASK 0xf000
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S5_Y__SHIFT 0xc
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S6_X_MASK 0xf0000
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S6_X__SHIFT 0x10
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S6_Y_MASK 0xf00000
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S6_Y__SHIFT 0x14
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S7_X_MASK 0xf000000
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S7_X__SHIFT 0x18
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S7_Y_MASK 0xf0000000
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S7_Y__SHIFT 0x1c
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S8_X_MASK 0xf
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S8_X__SHIFT 0x0
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S8_Y_MASK 0xf0
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S8_Y__SHIFT 0x4
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S9_X_MASK 0xf00
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S9_X__SHIFT 0x8
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S9_Y_MASK 0xf000
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S9_Y__SHIFT 0xc
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S10_X_MASK 0xf0000
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S10_X__SHIFT 0x10
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S10_Y_MASK 0xf00000
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S10_Y__SHIFT 0x14
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S11_X_MASK 0xf000000
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S11_X__SHIFT 0x18
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S11_Y_MASK 0xf0000000
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S11_Y__SHIFT 0x1c
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S12_X_MASK 0xf
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S12_X__SHIFT 0x0
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S12_Y_MASK 0xf0
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S12_Y__SHIFT 0x4
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S13_X_MASK 0xf00
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S13_X__SHIFT 0x8
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S13_Y_MASK 0xf000
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S13_Y__SHIFT 0xc
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S14_X_MASK 0xf0000
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S14_X__SHIFT 0x10
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S14_Y_MASK 0xf00000
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S14_Y__SHIFT 0x14
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S15_X_MASK 0xf000000
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S15_X__SHIFT 0x18
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S15_Y_MASK 0xf0000000
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S15_Y__SHIFT 0x1c
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S0_X_MASK 0xf
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S0_X__SHIFT 0x0
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S0_Y_MASK 0xf0
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S0_Y__SHIFT 0x4
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S1_X_MASK 0xf00
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S1_X__SHIFT 0x8
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S1_Y_MASK 0xf000
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S1_Y__SHIFT 0xc
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S2_X_MASK 0xf0000
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S2_X__SHIFT 0x10
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S2_Y_MASK 0xf00000
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S2_Y__SHIFT 0x14
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S3_X_MASK 0xf000000
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S3_X__SHIFT 0x18
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S3_Y_MASK 0xf0000000
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S3_Y__SHIFT 0x1c
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S4_X_MASK 0xf
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S4_X__SHIFT 0x0
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S4_Y_MASK 0xf0
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S4_Y__SHIFT 0x4
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S5_X_MASK 0xf00
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S5_X__SHIFT 0x8
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S5_Y_MASK 0xf000
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S5_Y__SHIFT 0xc
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S6_X_MASK 0xf0000
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S6_X__SHIFT 0x10
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S6_Y_MASK 0xf00000
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S6_Y__SHIFT 0x14
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S7_X_MASK 0xf000000
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S7_X__SHIFT 0x18
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S7_Y_MASK 0xf0000000
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S7_Y__SHIFT 0x1c
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S8_X_MASK 0xf
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S8_X__SHIFT 0x0
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S8_Y_MASK 0xf0
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S8_Y__SHIFT 0x4
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S9_X_MASK 0xf00
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S9_X__SHIFT 0x8
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S9_Y_MASK 0xf000
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S9_Y__SHIFT 0xc
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S10_X_MASK 0xf0000
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S10_X__SHIFT 0x10
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S10_Y_MASK 0xf00000
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S10_Y__SHIFT 0x14
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S11_X_MASK 0xf000000
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S11_X__SHIFT 0x18
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S11_Y_MASK 0xf0000000
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S11_Y__SHIFT 0x1c
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S12_X_MASK 0xf
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S12_X__SHIFT 0x0
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S12_Y_MASK 0xf0
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S12_Y__SHIFT 0x4
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S13_X_MASK 0xf00
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S13_X__SHIFT 0x8
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S13_Y_MASK 0xf000
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S13_Y__SHIFT 0xc
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S14_X_MASK 0xf0000
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S14_X__SHIFT 0x10
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S14_Y_MASK 0xf00000
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S14_Y__SHIFT 0x14
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S15_X_MASK 0xf000000
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S15_X__SHIFT 0x18
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S15_Y_MASK 0xf0000000
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S15_Y__SHIFT 0x1c
#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_0_MASK 0xf
#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_0__SHIFT 0x0
#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_1_MASK 0xf0
#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_1__SHIFT 0x4
#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_2_MASK 0xf00
#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_2__SHIFT 0x8
#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_3_MASK 0xf000
#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_3__SHIFT 0xc
#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_4_MASK 0xf0000
#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_4__SHIFT 0x10
#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_5_MASK 0xf00000
#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_5__SHIFT 0x14
#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_6_MASK 0xf000000
#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_6__SHIFT 0x18
#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_7_MASK 0xf0000000
#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_7__SHIFT 0x1c
#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_8_MASK 0xf
#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_8__SHIFT 0x0
#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_9_MASK 0xf0
#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_9__SHIFT 0x4
#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_10_MASK 0xf00
#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_10__SHIFT 0x8
#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_11_MASK 0xf000
#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_11__SHIFT 0xc
#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_12_MASK 0xf0000
#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_12__SHIFT 0x10
#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_13_MASK 0xf00000
#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_13__SHIFT 0x14
#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_14_MASK 0xf000000
#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_14__SHIFT 0x18
#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_15_MASK 0xf0000000
#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_15__SHIFT 0x1c
#define PA_SC_CLIPRECT_0_TL__TL_X_MASK 0x7fff
#define PA_SC_CLIPRECT_0_TL__TL_X__SHIFT 0x0
#define PA_SC_CLIPRECT_0_TL__TL_Y_MASK 0x7fff0000
#define PA_SC_CLIPRECT_0_TL__TL_Y__SHIFT 0x10
#define PA_SC_CLIPRECT_0_BR__BR_X_MASK 0x7fff
#define PA_SC_CLIPRECT_0_BR__BR_X__SHIFT 0x0
#define PA_SC_CLIPRECT_0_BR__BR_Y_MASK 0x7fff0000
#define PA_SC_CLIPRECT_0_BR__BR_Y__SHIFT 0x10
#define PA_SC_CLIPRECT_1_TL__TL_X_MASK 0x7fff
#define PA_SC_CLIPRECT_1_TL__TL_X__SHIFT 0x0
#define PA_SC_CLIPRECT_1_TL__TL_Y_MASK 0x7fff0000
#define PA_SC_CLIPRECT_1_TL__TL_Y__SHIFT 0x10
#define PA_SC_CLIPRECT_1_BR__BR_X_MASK 0x7fff
#define PA_SC_CLIPRECT_1_BR__BR_X__SHIFT 0x0
#define PA_SC_CLIPRECT_1_BR__BR_Y_MASK 0x7fff0000
#define PA_SC_CLIPRECT_1_BR__BR_Y__SHIFT 0x10
#define PA_SC_CLIPRECT_2_TL__TL_X_MASK 0x7fff
#define PA_SC_CLIPRECT_2_TL__TL_X__SHIFT 0x0
#define PA_SC_CLIPRECT_2_TL__TL_Y_MASK 0x7fff0000
#define PA_SC_CLIPRECT_2_TL__TL_Y__SHIFT 0x10
#define PA_SC_CLIPRECT_2_BR__BR_X_MASK 0x7fff
#define PA_SC_CLIPRECT_2_BR__BR_X__SHIFT 0x0
#define PA_SC_CLIPRECT_2_BR__BR_Y_MASK 0x7fff0000
#define PA_SC_CLIPRECT_2_BR__BR_Y__SHIFT 0x10
#define PA_SC_CLIPRECT_3_TL__TL_X_MASK 0x7fff
#define PA_SC_CLIPRECT_3_TL__TL_X__SHIFT 0x0
#define PA_SC_CLIPRECT_3_TL__TL_Y_MASK 0x7fff0000
#define PA_SC_CLIPRECT_3_TL__TL_Y__SHIFT 0x10
#define PA_SC_CLIPRECT_3_BR__BR_X_MASK 0x7fff
#define PA_SC_CLIPRECT_3_BR__BR_X__SHIFT 0x0
#define PA_SC_CLIPRECT_3_BR__BR_Y_MASK 0x7fff0000
#define PA_SC_CLIPRECT_3_BR__BR_Y__SHIFT 0x10
#define PA_SC_CLIPRECT_RULE__CLIP_RULE_MASK 0xffff
#define PA_SC_CLIPRECT_RULE__CLIP_RULE__SHIFT 0x0
#define PA_SC_EDGERULE__ER_TRI_MASK 0xf
#define PA_SC_EDGERULE__ER_TRI__SHIFT 0x0
#define PA_SC_EDGERULE__ER_POINT_MASK 0xf0
#define PA_SC_EDGERULE__ER_POINT__SHIFT 0x4
#define PA_SC_EDGERULE__ER_RECT_MASK 0xf00
#define PA_SC_EDGERULE__ER_RECT__SHIFT 0x8
#define PA_SC_EDGERULE__ER_LINE_LR_MASK 0x3f000
#define PA_SC_EDGERULE__ER_LINE_LR__SHIFT 0xc
#define PA_SC_EDGERULE__ER_LINE_RL_MASK 0xfc0000
#define PA_SC_EDGERULE__ER_LINE_RL__SHIFT 0x12
#define PA_SC_EDGERULE__ER_LINE_TB_MASK 0xf000000
#define PA_SC_EDGERULE__ER_LINE_TB__SHIFT 0x18
#define PA_SC_EDGERULE__ER_LINE_BT_MASK 0xf0000000
#define PA_SC_EDGERULE__ER_LINE_BT__SHIFT 0x1c
#define PA_SC_LINE_CNTL__EXPAND_LINE_WIDTH_MASK 0x200
#define PA_SC_LINE_CNTL__EXPAND_LINE_WIDTH__SHIFT 0x9
#define PA_SC_LINE_CNTL__LAST_PIXEL_MASK 0x400
#define PA_SC_LINE_CNTL__LAST_PIXEL__SHIFT 0xa
#define PA_SC_LINE_CNTL__PERPENDICULAR_ENDCAP_ENA_MASK 0x800
#define PA_SC_LINE_CNTL__PERPENDICULAR_ENDCAP_ENA__SHIFT 0xb
#define PA_SC_LINE_CNTL__DX10_DIAMOND_TEST_ENA_MASK 0x1000
#define PA_SC_LINE_CNTL__DX10_DIAMOND_TEST_ENA__SHIFT 0xc
#define PA_SC_LINE_STIPPLE__LINE_PATTERN_MASK 0xffff
#define PA_SC_LINE_STIPPLE__LINE_PATTERN__SHIFT 0x0
#define PA_SC_LINE_STIPPLE__REPEAT_COUNT_MASK 0xff0000
#define PA_SC_LINE_STIPPLE__REPEAT_COUNT__SHIFT 0x10
#define PA_SC_LINE_STIPPLE__PATTERN_BIT_ORDER_MASK 0x10000000
#define PA_SC_LINE_STIPPLE__PATTERN_BIT_ORDER__SHIFT 0x1c
#define PA_SC_LINE_STIPPLE__AUTO_RESET_CNTL_MASK 0x60000000
#define PA_SC_LINE_STIPPLE__AUTO_RESET_CNTL__SHIFT 0x1d
#define PA_SC_MODE_CNTL_0__MSAA_ENABLE_MASK 0x1
#define PA_SC_MODE_CNTL_0__MSAA_ENABLE__SHIFT 0x0
#define PA_SC_MODE_CNTL_0__VPORT_SCISSOR_ENABLE_MASK 0x2
#define PA_SC_MODE_CNTL_0__VPORT_SCISSOR_ENABLE__SHIFT 0x1
#define PA_SC_MODE_CNTL_0__LINE_STIPPLE_ENABLE_MASK 0x4
#define PA_SC_MODE_CNTL_0__LINE_STIPPLE_ENABLE__SHIFT 0x2
#define PA_SC_MODE_CNTL_0__SEND_UNLIT_STILES_TO_PKR_MASK 0x8
#define PA_SC_MODE_CNTL_0__SEND_UNLIT_STILES_TO_PKR__SHIFT 0x3
#define PA_SC_MODE_CNTL_1__WALK_SIZE_MASK 0x1
#define PA_SC_MODE_CNTL_1__WALK_SIZE__SHIFT 0x0
#define PA_SC_MODE_CNTL_1__WALK_ALIGNMENT_MASK 0x2
#define PA_SC_MODE_CNTL_1__WALK_ALIGNMENT__SHIFT 0x1
#define PA_SC_MODE_CNTL_1__WALK_ALIGN8_PRIM_FITS_ST_MASK 0x4
#define PA_SC_MODE_CNTL_1__WALK_ALIGN8_PRIM_FITS_ST__SHIFT 0x2
#define PA_SC_MODE_CNTL_1__WALK_FENCE_ENABLE_MASK 0x8
#define PA_SC_MODE_CNTL_1__WALK_FENCE_ENABLE__SHIFT 0x3
#define PA_SC_MODE_CNTL_1__WALK_FENCE_SIZE_MASK 0x70
#define PA_SC_MODE_CNTL_1__WALK_FENCE_SIZE__SHIFT 0x4
#define PA_SC_MODE_CNTL_1__SUPERTILE_WALK_ORDER_ENABLE_MASK 0x80
#define PA_SC_MODE_CNTL_1__SUPERTILE_WALK_ORDER_ENABLE__SHIFT 0x7
#define PA_SC_MODE_CNTL_1__TILE_WALK_ORDER_ENABLE_MASK 0x100
#define PA_SC_MODE_CNTL_1__TILE_WALK_ORDER_ENABLE__SHIFT 0x8
#define PA_SC_MODE_CNTL_1__TILE_COVER_DISABLE_MASK 0x200
#define PA_SC_MODE_CNTL_1__TILE_COVER_DISABLE__SHIFT 0x9
#define PA_SC_MODE_CNTL_1__TILE_COVER_NO_SCISSOR_MASK 0x400
#define PA_SC_MODE_CNTL_1__TILE_COVER_NO_SCISSOR__SHIFT 0xa
#define PA_SC_MODE_CNTL_1__ZMM_LINE_EXTENT_MASK 0x800
#define PA_SC_MODE_CNTL_1__ZMM_LINE_EXTENT__SHIFT 0xb
#define PA_SC_MODE_CNTL_1__ZMM_LINE_OFFSET_MASK 0x1000
#define PA_SC_MODE_CNTL_1__ZMM_LINE_OFFSET__SHIFT 0xc
#define PA_SC_MODE_CNTL_1__ZMM_RECT_EXTENT_MASK 0x2000
#define PA_SC_MODE_CNTL_1__ZMM_RECT_EXTENT__SHIFT 0xd
#define PA_SC_MODE_CNTL_1__KILL_PIX_POST_HI_Z_MASK 0x4000
#define PA_SC_MODE_CNTL_1__KILL_PIX_POST_HI_Z__SHIFT 0xe
#define PA_SC_MODE_CNTL_1__KILL_PIX_POST_DETAIL_MASK_MASK 0x8000
#define PA_SC_MODE_CNTL_1__KILL_PIX_POST_DETAIL_MASK__SHIFT 0xf
#define PA_SC_MODE_CNTL_1__PS_ITER_SAMPLE_MASK 0x10000
#define PA_SC_MODE_CNTL_1__PS_ITER_SAMPLE__SHIFT 0x10
#define PA_SC_MODE_CNTL_1__MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE_MASK 0x20000
#define PA_SC_MODE_CNTL_1__MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE__SHIFT 0x11
#define PA_SC_MODE_CNTL_1__MULTI_GPU_SUPERTILE_ENABLE_MASK 0x40000
#define PA_SC_MODE_CNTL_1__MULTI_GPU_SUPERTILE_ENABLE__SHIFT 0x12
#define PA_SC_MODE_CNTL_1__GPU_ID_OVERRIDE_ENABLE_MASK 0x80000
#define PA_SC_MODE_CNTL_1__GPU_ID_OVERRIDE_ENABLE__SHIFT 0x13
#define PA_SC_MODE_CNTL_1__GPU_ID_OVERRIDE_MASK 0xf00000
#define PA_SC_MODE_CNTL_1__GPU_ID_OVERRIDE__SHIFT 0x14
#define PA_SC_MODE_CNTL_1__MULTI_GPU_PRIM_DISCARD_ENABLE_MASK 0x1000000
#define PA_SC_MODE_CNTL_1__MULTI_GPU_PRIM_DISCARD_ENABLE__SHIFT 0x18
#define PA_SC_MODE_CNTL_1__FORCE_EOV_CNTDWN_ENABLE_MASK 0x2000000
#define PA_SC_MODE_CNTL_1__FORCE_EOV_CNTDWN_ENABLE__SHIFT 0x19
#define PA_SC_MODE_CNTL_1__FORCE_EOV_REZ_ENABLE_MASK 0x4000000
#define PA_SC_MODE_CNTL_1__FORCE_EOV_REZ_ENABLE__SHIFT 0x1a
#define PA_SC_MODE_CNTL_1__OUT_OF_ORDER_PRIMITIVE_ENABLE_MASK 0x8000000
#define PA_SC_MODE_CNTL_1__OUT_OF_ORDER_PRIMITIVE_ENABLE__SHIFT 0x1b
#define PA_SC_MODE_CNTL_1__OUT_OF_ORDER_WATER_MARK_MASK 0x70000000
#define PA_SC_MODE_CNTL_1__OUT_OF_ORDER_WATER_MARK__SHIFT 0x1c
#define PA_SC_RASTER_CONFIG__RB_MAP_PKR0_MASK 0x3
#define PA_SC_RASTER_CONFIG__RB_MAP_PKR0__SHIFT 0x0
#define PA_SC_RASTER_CONFIG__RB_MAP_PKR1_MASK 0xc
#define PA_SC_RASTER_CONFIG__RB_MAP_PKR1__SHIFT 0x2
#define PA_SC_RASTER_CONFIG__RB_XSEL2_MASK 0x30
#define PA_SC_RASTER_CONFIG__RB_XSEL2__SHIFT 0x4
#define PA_SC_RASTER_CONFIG__RB_XSEL_MASK 0x40
#define PA_SC_RASTER_CONFIG__RB_XSEL__SHIFT 0x6
#define PA_SC_RASTER_CONFIG__RB_YSEL_MASK 0x80
#define PA_SC_RASTER_CONFIG__RB_YSEL__SHIFT 0x7
#define PA_SC_RASTER_CONFIG__PKR_MAP_MASK 0x300
#define PA_SC_RASTER_CONFIG__PKR_MAP__SHIFT 0x8
#define PA_SC_RASTER_CONFIG__PKR_XSEL_MASK 0xc00
#define PA_SC_RASTER_CONFIG__PKR_XSEL__SHIFT 0xa
#define PA_SC_RASTER_CONFIG__PKR_YSEL_MASK 0x3000
#define PA_SC_RASTER_CONFIG__PKR_YSEL__SHIFT 0xc
#define PA_SC_RASTER_CONFIG__PKR_XSEL2_MASK 0xc000
#define PA_SC_RASTER_CONFIG__PKR_XSEL2__SHIFT 0xe
#define PA_SC_RASTER_CONFIG__SC_MAP_MASK 0x30000
#define PA_SC_RASTER_CONFIG__SC_MAP__SHIFT 0x10
#define PA_SC_RASTER_CONFIG__SC_XSEL_MASK 0xc0000
#define PA_SC_RASTER_CONFIG__SC_XSEL__SHIFT 0x12
#define PA_SC_RASTER_CONFIG__SC_YSEL_MASK 0x300000
#define PA_SC_RASTER_CONFIG__SC_YSEL__SHIFT 0x14
#define PA_SC_RASTER_CONFIG__SE_MAP_MASK 0x3000000
#define PA_SC_RASTER_CONFIG__SE_MAP__SHIFT 0x18
#define PA_SC_RASTER_CONFIG__SE_XSEL_MASK 0xc000000
#define PA_SC_RASTER_CONFIG__SE_XSEL__SHIFT 0x1a
#define PA_SC_RASTER_CONFIG__SE_YSEL_MASK 0x30000000
#define PA_SC_RASTER_CONFIG__SE_YSEL__SHIFT 0x1c
#define PA_SC_RASTER_CONFIG_1__SE_PAIR_MAP_MASK 0x3
#define PA_SC_RASTER_CONFIG_1__SE_PAIR_MAP__SHIFT 0x0
#define PA_SC_RASTER_CONFIG_1__SE_PAIR_XSEL_MASK 0xc
#define PA_SC_RASTER_CONFIG_1__SE_PAIR_XSEL__SHIFT 0x2
#define PA_SC_RASTER_CONFIG_1__SE_PAIR_YSEL_MASK 0x30
#define PA_SC_RASTER_CONFIG_1__SE_PAIR_YSEL__SHIFT 0x4
#define PA_SC_SCREEN_EXTENT_CONTROL__SLICE_EVEN_ENABLE_MASK 0x3
#define PA_SC_SCREEN_EXTENT_CONTROL__SLICE_EVEN_ENABLE__SHIFT 0x0
#define PA_SC_SCREEN_EXTENT_CONTROL__SLICE_ODD_ENABLE_MASK 0xc
#define PA_SC_SCREEN_EXTENT_CONTROL__SLICE_ODD_ENABLE__SHIFT 0x2
#define PA_SC_GENERIC_SCISSOR_TL__TL_X_MASK 0x7fff
#define PA_SC_GENERIC_SCISSOR_TL__TL_X__SHIFT 0x0
#define PA_SC_GENERIC_SCISSOR_TL__TL_Y_MASK 0x7fff0000
#define PA_SC_GENERIC_SCISSOR_TL__TL_Y__SHIFT 0x10
#define PA_SC_GENERIC_SCISSOR_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000
#define PA_SC_GENERIC_SCISSOR_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
#define PA_SC_GENERIC_SCISSOR_BR__BR_X_MASK 0x7fff
#define PA_SC_GENERIC_SCISSOR_BR__BR_X__SHIFT 0x0
#define PA_SC_GENERIC_SCISSOR_BR__BR_Y_MASK 0x7fff0000
#define PA_SC_GENERIC_SCISSOR_BR__BR_Y__SHIFT 0x10
#define PA_SC_SCREEN_SCISSOR_TL__TL_X_MASK 0xffff
#define PA_SC_SCREEN_SCISSOR_TL__TL_X__SHIFT 0x0
#define PA_SC_SCREEN_SCISSOR_TL__TL_Y_MASK 0xffff0000
#define PA_SC_SCREEN_SCISSOR_TL__TL_Y__SHIFT 0x10
#define PA_SC_SCREEN_SCISSOR_BR__BR_X_MASK 0xffff
#define PA_SC_SCREEN_SCISSOR_BR__BR_X__SHIFT 0x0
#define PA_SC_SCREEN_SCISSOR_BR__BR_Y_MASK 0xffff0000
#define PA_SC_SCREEN_SCISSOR_BR__BR_Y__SHIFT 0x10
#define PA_SC_WINDOW_OFFSET__WINDOW_X_OFFSET_MASK 0xffff
#define PA_SC_WINDOW_OFFSET__WINDOW_X_OFFSET__SHIFT 0x0
#define PA_SC_WINDOW_OFFSET__WINDOW_Y_OFFSET_MASK 0xffff0000
#define PA_SC_WINDOW_OFFSET__WINDOW_Y_OFFSET__SHIFT 0x10
#define PA_SC_WINDOW_SCISSOR_TL__TL_X_MASK 0x7fff
#define PA_SC_WINDOW_SCISSOR_TL__TL_X__SHIFT 0x0
#define PA_SC_WINDOW_SCISSOR_TL__TL_Y_MASK 0x7fff0000
#define PA_SC_WINDOW_SCISSOR_TL__TL_Y__SHIFT 0x10
#define PA_SC_WINDOW_SCISSOR_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000
#define PA_SC_WINDOW_SCISSOR_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
#define PA_SC_WINDOW_SCISSOR_BR__BR_X_MASK 0x7fff
#define PA_SC_WINDOW_SCISSOR_BR__BR_X__SHIFT 0x0
#define PA_SC_WINDOW_SCISSOR_BR__BR_Y_MASK 0x7fff0000
#define PA_SC_WINDOW_SCISSOR_BR__BR_Y__SHIFT 0x10
#define PA_SC_VPORT_SCISSOR_0_TL__TL_X_MASK 0x7fff
#define PA_SC_VPORT_SCISSOR_0_TL__TL_X__SHIFT 0x0
#define PA_SC_VPORT_SCISSOR_0_TL__TL_Y_MASK 0x7fff0000
#define PA_SC_VPORT_SCISSOR_0_TL__TL_Y__SHIFT 0x10
#define PA_SC_VPORT_SCISSOR_0_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000
#define PA_SC_VPORT_SCISSOR_0_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
#define PA_SC_VPORT_SCISSOR_1_TL__TL_X_MASK 0x7fff
#define PA_SC_VPORT_SCISSOR_1_TL__TL_X__SHIFT 0x0
#define PA_SC_VPORT_SCISSOR_1_TL__TL_Y_MASK 0x7fff0000
#define PA_SC_VPORT_SCISSOR_1_TL__TL_Y__SHIFT 0x10
#define PA_SC_VPORT_SCISSOR_1_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000
#define PA_SC_VPORT_SCISSOR_1_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
#define PA_SC_VPORT_SCISSOR_2_TL__TL_X_MASK 0x7fff
#define PA_SC_VPORT_SCISSOR_2_TL__TL_X__SHIFT 0x0
#define PA_SC_VPORT_SCISSOR_2_TL__TL_Y_MASK 0x7fff0000
#define PA_SC_VPORT_SCISSOR_2_TL__TL_Y__SHIFT 0x10
#define PA_SC_VPORT_SCISSOR_2_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000
#define PA_SC_VPORT_SCISSOR_2_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
#define PA_SC_VPORT_SCISSOR_3_TL__TL_X_MASK 0x7fff
#define PA_SC_VPORT_SCISSOR_3_TL__TL_X__SHIFT 0x0
#define PA_SC_VPORT_SCISSOR_3_TL__TL_Y_MASK 0x7fff0000
#define PA_SC_VPORT_SCISSOR_3_TL__TL_Y__SHIFT 0x10
#define PA_SC_VPORT_SCISSOR_3_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000
#define PA_SC_VPORT_SCISSOR_3_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
#define PA_SC_VPORT_SCISSOR_4_TL__TL_X_MASK 0x7fff
#define PA_SC_VPORT_SCISSOR_4_TL__TL_X__SHIFT 0x0
#define PA_SC_VPORT_SCISSOR_4_TL__TL_Y_MASK 0x7fff0000
#define PA_SC_VPORT_SCISSOR_4_TL__TL_Y__SHIFT 0x10
#define PA_SC_VPORT_SCISSOR_4_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000
#define PA_SC_VPORT_SCISSOR_4_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
#define PA_SC_VPORT_SCISSOR_5_TL__TL_X_MASK 0x7fff
#define PA_SC_VPORT_SCISSOR_5_TL__TL_X__SHIFT 0x0
#define PA_SC_VPORT_SCISSOR_5_TL__TL_Y_MASK 0x7fff0000
#define PA_SC_VPORT_SCISSOR_5_TL__TL_Y__SHIFT 0x10
#define PA_SC_VPORT_SCISSOR_5_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000
#define PA_SC_VPORT_SCISSOR_5_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
#define PA_SC_VPORT_SCISSOR_6_TL__TL_X_MASK 0x7fff
#define PA_SC_VPORT_SCISSOR_6_TL__TL_X__SHIFT 0x0
#define PA_SC_VPORT_SCISSOR_6_TL__TL_Y_MASK 0x7fff0000
#define PA_SC_VPORT_SCISSOR_6_TL__TL_Y__SHIFT 0x10
#define PA_SC_VPORT_SCISSOR_6_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000
#define PA_SC_VPORT_SCISSOR_6_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
#define PA_SC_VPORT_SCISSOR_7_TL__TL_X_MASK 0x7fff
#define PA_SC_VPORT_SCISSOR_7_TL__TL_X__SHIFT 0x0
#define PA_SC_VPORT_SCISSOR_7_TL__TL_Y_MASK 0x7fff0000
#define PA_SC_VPORT_SCISSOR_7_TL__TL_Y__SHIFT 0x10
#define PA_SC_VPORT_SCISSOR_7_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000
#define PA_SC_VPORT_SCISSOR_7_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
#define PA_SC_VPORT_SCISSOR_8_TL__TL_X_MASK 0x7fff
#define PA_SC_VPORT_SCISSOR_8_TL__TL_X__SHIFT 0x0
#define PA_SC_VPORT_SCISSOR_8_TL__TL_Y_MASK 0x7fff0000
#define PA_SC_VPORT_SCISSOR_8_TL__TL_Y__SHIFT 0x10
#define PA_SC_VPORT_SCISSOR_8_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000
#define PA_SC_VPORT_SCISSOR_8_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
#define PA_SC_VPORT_SCISSOR_9_TL__TL_X_MASK 0x7fff
#define PA_SC_VPORT_SCISSOR_9_TL__TL_X__SHIFT 0x0
#define PA_SC_VPORT_SCISSOR_9_TL__TL_Y_MASK 0x7fff0000
#define PA_SC_VPORT_SCISSOR_9_TL__TL_Y__SHIFT 0x10
#define PA_SC_VPORT_SCISSOR_9_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000
#define PA_SC_VPORT_SCISSOR_9_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
#define PA_SC_VPORT_SCISSOR_10_TL__TL_X_MASK 0x7fff
#define PA_SC_VPORT_SCISSOR_10_TL__TL_X__SHIFT 0x0
#define PA_SC_VPORT_SCISSOR_10_TL__TL_Y_MASK 0x7fff0000
#define PA_SC_VPORT_SCISSOR_10_TL__TL_Y__SHIFT 0x10
#define PA_SC_VPORT_SCISSOR_10_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000
#define PA_SC_VPORT_SCISSOR_10_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
#define PA_SC_VPORT_SCISSOR_11_TL__TL_X_MASK 0x7fff
#define PA_SC_VPORT_SCISSOR_11_TL__TL_X__SHIFT 0x0
#define PA_SC_VPORT_SCISSOR_11_TL__TL_Y_MASK 0x7fff0000
#define PA_SC_VPORT_SCISSOR_11_TL__TL_Y__SHIFT 0x10
#define PA_SC_VPORT_SCISSOR_11_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000
#define PA_SC_VPORT_SCISSOR_11_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
#define PA_SC_VPORT_SCISSOR_12_TL__TL_X_MASK 0x7fff
#define PA_SC_VPORT_SCISSOR_12_TL__TL_X__SHIFT 0x0
#define PA_SC_VPORT_SCISSOR_12_TL__TL_Y_MASK 0x7fff0000
#define PA_SC_VPORT_SCISSOR_12_TL__TL_Y__SHIFT 0x10
#define PA_SC_VPORT_SCISSOR_12_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000
#define PA_SC_VPORT_SCISSOR_12_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
#define PA_SC_VPORT_SCISSOR_13_TL__TL_X_MASK 0x7fff
#define PA_SC_VPORT_SCISSOR_13_TL__TL_X__SHIFT 0x0
#define PA_SC_VPORT_SCISSOR_13_TL__TL_Y_MASK 0x7fff0000
#define PA_SC_VPORT_SCISSOR_13_TL__TL_Y__SHIFT 0x10
#define PA_SC_VPORT_SCISSOR_13_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000
#define PA_SC_VPORT_SCISSOR_13_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
#define PA_SC_VPORT_SCISSOR_14_TL__TL_X_MASK 0x7fff
#define PA_SC_VPORT_SCISSOR_14_TL__TL_X__SHIFT 0x0
#define PA_SC_VPORT_SCISSOR_14_TL__TL_Y_MASK 0x7fff0000
#define PA_SC_VPORT_SCISSOR_14_TL__TL_Y__SHIFT 0x10
#define PA_SC_VPORT_SCISSOR_14_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000
#define PA_SC_VPORT_SCISSOR_14_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
#define PA_SC_VPORT_SCISSOR_15_TL__TL_X_MASK 0x7fff
#define PA_SC_VPORT_SCISSOR_15_TL__TL_X__SHIFT 0x0
#define PA_SC_VPORT_SCISSOR_15_TL__TL_Y_MASK 0x7fff0000
#define PA_SC_VPORT_SCISSOR_15_TL__TL_Y__SHIFT 0x10
#define PA_SC_VPORT_SCISSOR_15_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000
#define PA_SC_VPORT_SCISSOR_15_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
#define PA_SC_VPORT_SCISSOR_0_BR__BR_X_MASK 0x7fff
#define PA_SC_VPORT_SCISSOR_0_BR__BR_X__SHIFT 0x0
#define PA_SC_VPORT_SCISSOR_0_BR__BR_Y_MASK 0x7fff0000
#define PA_SC_VPORT_SCISSOR_0_BR__BR_Y__SHIFT 0x10
#define PA_SC_VPORT_SCISSOR_1_BR__BR_X_MASK 0x7fff
#define PA_SC_VPORT_SCISSOR_1_BR__BR_X__SHIFT 0x0
#define PA_SC_VPORT_SCISSOR_1_BR__BR_Y_MASK 0x7fff0000
#define PA_SC_VPORT_SCISSOR_1_BR__BR_Y__SHIFT 0x10
#define PA_SC_VPORT_SCISSOR_2_BR__BR_X_MASK 0x7fff
#define PA_SC_VPORT_SCISSOR_2_BR__BR_X__SHIFT 0x0
#define PA_SC_VPORT_SCISSOR_2_BR__BR_Y_MASK 0x7fff0000
#define PA_SC_VPORT_SCISSOR_2_BR__BR_Y__SHIFT 0x10
#define PA_SC_VPORT_SCISSOR_3_BR__BR_X_MASK 0x7fff
#define PA_SC_VPORT_SCISSOR_3_BR__BR_X__SHIFT 0x0
#define PA_SC_VPORT_SCISSOR_3_BR__BR_Y_MASK 0x7fff0000
#define PA_SC_VPORT_SCISSOR_3_BR__BR_Y__SHIFT 0x10
#define PA_SC_VPORT_SCISSOR_4_BR__BR_X_MASK 0x7fff
#define PA_SC_VPORT_SCISSOR_4_BR__BR_X__SHIFT 0x0
#define PA_SC_VPORT_SCISSOR_4_BR__BR_Y_MASK 0x7fff0000
#define PA_SC_VPORT_SCISSOR_4_BR__BR_Y__SHIFT 0x10
#define PA_SC_VPORT_SCISSOR_5_BR__BR_X_MASK 0x7fff
#define PA_SC_VPORT_SCISSOR_5_BR__BR_X__SHIFT 0x0
#define PA_SC_VPORT_SCISSOR_5_BR__BR_Y_MASK 0x7fff0000
#define PA_SC_VPORT_SCISSOR_5_BR__BR_Y__SHIFT 0x10
#define PA_SC_VPORT_SCISSOR_6_BR__BR_X_MASK 0x7fff
#define PA_SC_VPORT_SCISSOR_6_BR__BR_X__SHIFT 0x0
#define PA_SC_VPORT_SCISSOR_6_BR__BR_Y_MASK 0x7fff0000
#define PA_SC_VPORT_SCISSOR_6_BR__BR_Y__SHIFT 0x10
#define PA_SC_VPORT_SCISSOR_7_BR__BR_X_MASK 0x7fff
#define PA_SC_VPORT_SCISSOR_7_BR__BR_X__SHIFT 0x0
#define PA_SC_VPORT_SCISSOR_7_BR__BR_Y_MASK 0x7fff0000
#define PA_SC_VPORT_SCISSOR_7_BR__BR_Y__SHIFT 0x10
#define PA_SC_VPORT_SCISSOR_8_BR__BR_X_MASK 0x7fff
#define PA_SC_VPORT_SCISSOR_8_BR__BR_X__SHIFT 0x0
#define PA_SC_VPORT_SCISSOR_8_BR__BR_Y_MASK 0x7fff0000
#define PA_SC_VPORT_SCISSOR_8_BR__BR_Y__SHIFT 0x10
#define PA_SC_VPORT_SCISSOR_9_BR__BR_X_MASK 0x7fff
#define PA_SC_VPORT_SCISSOR_9_BR__BR_X__SHIFT 0x0
#define PA_SC_VPORT_SCISSOR_9_BR__BR_Y_MASK 0x7fff0000
#define PA_SC_VPORT_SCISSOR_9_BR__BR_Y__SHIFT 0x10
#define PA_SC_VPORT_SCISSOR_10_BR__BR_X_MASK 0x7fff
#define PA_SC_VPORT_SCISSOR_10_BR__BR_X__SHIFT 0x0
#define PA_SC_VPORT_SCISSOR_10_BR__BR_Y_MASK 0x7fff0000
#define PA_SC_VPORT_SCISSOR_10_BR__BR_Y__SHIFT 0x10
#define PA_SC_VPORT_SCISSOR_11_BR__BR_X_MASK 0x7fff
#define PA_SC_VPORT_SCISSOR_11_BR__BR_X__SHIFT 0x0
#define PA_SC_VPORT_SCISSOR_11_BR__BR_Y_MASK 0x7fff0000
#define PA_SC_VPORT_SCISSOR_11_BR__BR_Y__SHIFT 0x10
#define PA_SC_VPORT_SCISSOR_12_BR__BR_X_MASK 0x7fff
#define PA_SC_VPORT_SCISSOR_12_BR__BR_X__SHIFT 0x0
#define PA_SC_VPORT_SCISSOR_12_BR__BR_Y_MASK 0x7fff0000
#define PA_SC_VPORT_SCISSOR_12_BR__BR_Y__SHIFT 0x10
#define PA_SC_VPORT_SCISSOR_13_BR__BR_X_MASK 0x7fff
#define PA_SC_VPORT_SCISSOR_13_BR__BR_X__SHIFT 0x0
#define PA_SC_VPORT_SCISSOR_13_BR__BR_Y_MASK 0x7fff0000
#define PA_SC_VPORT_SCISSOR_13_BR__BR_Y__SHIFT 0x10
#define PA_SC_VPORT_SCISSOR_14_BR__BR_X_MASK 0x7fff
#define PA_SC_VPORT_SCISSOR_14_BR__BR_X__SHIFT 0x0
#define PA_SC_VPORT_SCISSOR_14_BR__BR_Y_MASK 0x7fff0000
#define PA_SC_VPORT_SCISSOR_14_BR__BR_Y__SHIFT 0x10
#define PA_SC_VPORT_SCISSOR_15_BR__BR_X_MASK 0x7fff
#define PA_SC_VPORT_SCISSOR_15_BR__BR_X__SHIFT 0x0
#define PA_SC_VPORT_SCISSOR_15_BR__BR_Y_MASK 0x7fff0000
#define PA_SC_VPORT_SCISSOR_15_BR__BR_Y__SHIFT 0x10
#define PA_SC_VPORT_ZMIN_0__VPORT_ZMIN_MASK 0xffffffff
#define PA_SC_VPORT_ZMIN_0__VPORT_ZMIN__SHIFT 0x0
#define PA_SC_VPORT_ZMIN_1__VPORT_ZMIN_MASK 0xffffffff
#define PA_SC_VPORT_ZMIN_1__VPORT_ZMIN__SHIFT 0x0
#define PA_SC_VPORT_ZMIN_2__VPORT_ZMIN_MASK 0xffffffff
#define PA_SC_VPORT_ZMIN_2__VPORT_ZMIN__SHIFT 0x0
#define PA_SC_VPORT_ZMIN_3__VPORT_ZMIN_MASK 0xffffffff
#define PA_SC_VPORT_ZMIN_3__VPORT_ZMIN__SHIFT 0x0
#define PA_SC_VPORT_ZMIN_4__VPORT_ZMIN_MASK 0xffffffff
#define PA_SC_VPORT_ZMIN_4__VPORT_ZMIN__SHIFT 0x0
#define PA_SC_VPORT_ZMIN_5__VPORT_ZMIN_MASK 0xffffffff
#define PA_SC_VPORT_ZMIN_5__VPORT_ZMIN__SHIFT 0x0
#define PA_SC_VPORT_ZMIN_6__VPORT_ZMIN_MASK 0xffffffff
#define PA_SC_VPORT_ZMIN_6__VPORT_ZMIN__SHIFT 0x0
#define PA_SC_VPORT_ZMIN_7__VPORT_ZMIN_MASK 0xffffffff
#define PA_SC_VPORT_ZMIN_7__VPORT_ZMIN__SHIFT 0x0
#define PA_SC_VPORT_ZMIN_8__VPORT_ZMIN_MASK 0xffffffff
#define PA_SC_VPORT_ZMIN_8__VPORT_ZMIN__SHIFT 0x0
#define PA_SC_VPORT_ZMIN_9__VPORT_ZMIN_MASK 0xffffffff
#define PA_SC_VPORT_ZMIN_9__VPORT_ZMIN__SHIFT 0x0
#define PA_SC_VPORT_ZMIN_10__VPORT_ZMIN_MASK 0xffffffff
#define PA_SC_VPORT_ZMIN_10__VPORT_ZMIN__SHIFT 0x0
#define PA_SC_VPORT_ZMIN_11__VPORT_ZMIN_MASK 0xffffffff
#define PA_SC_VPORT_ZMIN_11__VPORT_ZMIN__SHIFT 0x0
#define PA_SC_VPORT_ZMIN_12__VPORT_ZMIN_MASK 0xffffffff
#define PA_SC_VPORT_ZMIN_12__VPORT_ZMIN__SHIFT 0x0
#define PA_SC_VPORT_ZMIN_13__VPORT_ZMIN_MASK 0xffffffff
#define PA_SC_VPORT_ZMIN_13__VPORT_ZMIN__SHIFT 0x0
#define PA_SC_VPORT_ZMIN_14__VPORT_ZMIN_MASK 0xffffffff
#define PA_SC_VPORT_ZMIN_14__VPORT_ZMIN__SHIFT 0x0
#define PA_SC_VPORT_ZMIN_15__VPORT_ZMIN_MASK 0xffffffff
#define PA_SC_VPORT_ZMIN_15__VPORT_ZMIN__SHIFT 0x0
#define PA_SC_VPORT_ZMAX_0__VPORT_ZMAX_MASK 0xffffffff
#define PA_SC_VPORT_ZMAX_0__VPORT_ZMAX__SHIFT 0x0
#define PA_SC_VPORT_ZMAX_1__VPORT_ZMAX_MASK 0xffffffff
#define PA_SC_VPORT_ZMAX_1__VPORT_ZMAX__SHIFT 0x0
#define PA_SC_VPORT_ZMAX_2__VPORT_ZMAX_MASK 0xffffffff
#define PA_SC_VPORT_ZMAX_2__VPORT_ZMAX__SHIFT 0x0
#define PA_SC_VPORT_ZMAX_3__VPORT_ZMAX_MASK 0xffffffff
#define PA_SC_VPORT_ZMAX_3__VPORT_ZMAX__SHIFT 0x0
#define PA_SC_VPORT_ZMAX_4__VPORT_ZMAX_MASK 0xffffffff
#define PA_SC_VPORT_ZMAX_4__VPORT_ZMAX__SHIFT 0x0
#define PA_SC_VPORT_ZMAX_5__VPORT_ZMAX_MASK 0xffffffff
#define PA_SC_VPORT_ZMAX_5__VPORT_ZMAX__SHIFT 0x0
#define PA_SC_VPORT_ZMAX_6__VPORT_ZMAX_MASK 0xffffffff
#define PA_SC_VPORT_ZMAX_6__VPORT_ZMAX__SHIFT 0x0
#define PA_SC_VPORT_ZMAX_7__VPORT_ZMAX_MASK 0xffffffff
#define PA_SC_VPORT_ZMAX_7__VPORT_ZMAX__SHIFT 0x0
#define PA_SC_VPORT_ZMAX_8__VPORT_ZMAX_MASK 0xffffffff
#define PA_SC_VPORT_ZMAX_8__VPORT_ZMAX__SHIFT 0x0
#define PA_SC_VPORT_ZMAX_9__VPORT_ZMAX_MASK 0xffffffff
#define PA_SC_VPORT_ZMAX_9__VPORT_ZMAX__SHIFT 0x0
#define PA_SC_VPORT_ZMAX_10__VPORT_ZMAX_MASK 0xffffffff
#define PA_SC_VPORT_ZMAX_10__VPORT_ZMAX__SHIFT 0x0
#define PA_SC_VPORT_ZMAX_11__VPORT_ZMAX_MASK 0xffffffff
#define PA_SC_VPORT_ZMAX_11__VPORT_ZMAX__SHIFT 0x0
#define PA_SC_VPORT_ZMAX_12__VPORT_ZMAX_MASK 0xffffffff
#define PA_SC_VPORT_ZMAX_12__VPORT_ZMAX__SHIFT 0x0
#define PA_SC_VPORT_ZMAX_13__VPORT_ZMAX_MASK 0xffffffff
#define PA_SC_VPORT_ZMAX_13__VPORT_ZMAX__SHIFT 0x0
#define PA_SC_VPORT_ZMAX_14__VPORT_ZMAX_MASK 0xffffffff
#define PA_SC_VPORT_ZMAX_14__VPORT_ZMAX__SHIFT 0x0
#define PA_SC_VPORT_ZMAX_15__VPORT_ZMAX_MASK 0xffffffff
#define PA_SC_VPORT_ZMAX_15__VPORT_ZMAX__SHIFT 0x0
#define PA_SC_ENHANCE__ENABLE_PA_SC_OUT_OF_ORDER_MASK 0x1
#define PA_SC_ENHANCE__ENABLE_PA_SC_OUT_OF_ORDER__SHIFT 0x0
#define PA_SC_ENHANCE__DISABLE_SC_DB_TILE_FIX_MASK 0x2
#define PA_SC_ENHANCE__DISABLE_SC_DB_TILE_FIX__SHIFT 0x1
#define PA_SC_ENHANCE__DISABLE_AA_MASK_FULL_FIX_MASK 0x4
#define PA_SC_ENHANCE__DISABLE_AA_MASK_FULL_FIX__SHIFT 0x2
#define PA_SC_ENHANCE__ENABLE_1XMSAA_SAMPLE_LOCATIONS_MASK 0x8
#define PA_SC_ENHANCE__ENABLE_1XMSAA_SAMPLE_LOCATIONS__SHIFT 0x3
#define PA_SC_ENHANCE__ENABLE_1XMSAA_SAMPLE_LOC_CENTROID_MASK 0x10
#define PA_SC_ENHANCE__ENABLE_1XMSAA_SAMPLE_LOC_CENTROID__SHIFT 0x4
#define PA_SC_ENHANCE__DISABLE_SCISSOR_FIX_MASK 0x20
#define PA_SC_ENHANCE__DISABLE_SCISSOR_FIX__SHIFT 0x5
#define PA_SC_ENHANCE__DISABLE_PW_BUBBLE_COLLAPSE_MASK 0xc0
#define PA_SC_ENHANCE__DISABLE_PW_BUBBLE_COLLAPSE__SHIFT 0x6
#define PA_SC_ENHANCE__SEND_UNLIT_STILES_TO_PACKER_MASK 0x100
#define PA_SC_ENHANCE__SEND_UNLIT_STILES_TO_PACKER__SHIFT 0x8
#define PA_SC_ENHANCE__DISABLE_DUALGRAD_PERF_OPTIMIZATION_MASK 0x200
#define PA_SC_ENHANCE__DISABLE_DUALGRAD_PERF_OPTIMIZATION__SHIFT 0x9
#define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_PRIM_MASK 0x400
#define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_PRIM__SHIFT 0xa
#define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_SUPERTILE_MASK 0x800
#define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_SUPERTILE__SHIFT 0xb
#define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_TILE_MASK 0x1000
#define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_TILE__SHIFT 0xc
#define PA_SC_ENHANCE__DISABLE_PA_SC_GUIDANCE_MASK 0x2000
#define PA_SC_ENHANCE__DISABLE_PA_SC_GUIDANCE__SHIFT 0xd
#define PA_SC_ENHANCE__DISABLE_EOV_ALL_CTRL_ONLY_COMBINATIONS_MASK 0x4000
#define PA_SC_ENHANCE__DISABLE_EOV_ALL_CTRL_ONLY_COMBINATIONS__SHIFT 0xe
#define PA_SC_ENHANCE__ENABLE_MULTICYCLE_BUBBLE_FREEZE_MASK 0x8000
#define PA_SC_ENHANCE__ENABLE_MULTICYCLE_BUBBLE_FREEZE__SHIFT 0xf
#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_PA_SC_GUIDANCE_MASK 0x10000
#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_PA_SC_GUIDANCE__SHIFT 0x10
#define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_POLY_MODE_MASK 0x20000
#define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_POLY_MODE__SHIFT 0x11
#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_EOP_SYNC_NULL_PRIMS_LAST_MASK 0x40000
#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_EOP_SYNC_NULL_PRIMS_LAST__SHIFT 0x12
#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_THRESHOLD_SWITCHING_MASK 0x80000
#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_THRESHOLD_SWITCHING__SHIFT 0x13
#define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_THRESHOLD_SWITCH_AT_EOPG_ONLY_MASK 0x100000
#define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_THRESHOLD_SWITCH_AT_EOPG_ONLY__SHIFT 0x14
#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_DESIRED_FIFO_EMPTY_SWITCHING_MASK 0x200000
#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_DESIRED_FIFO_EMPTY_SWITCHING__SHIFT 0x15
#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_SELECTED_FIFO_EMPTY_SWITCHING_MASK 0x400000
#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_SELECTED_FIFO_EMPTY_SWITCHING__SHIFT 0x16
#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_EMPTY_SWITCHING_HYSTERYSIS_MASK 0x800000
#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_EMPTY_SWITCHING_HYSTERYSIS__SHIFT 0x17
#define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_DESIRED_FIFO_IS_NEXT_FEID_MASK 0x1000000
#define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_DESIRED_FIFO_IS_NEXT_FEID__SHIFT 0x18
#define PA_SC_ENHANCE__DISABLE_OOO_NO_EOPG_SKEW_DESIRED_FIFO_IS_CURRENT_FIFO_MASK 0x2000000
#define PA_SC_ENHANCE__DISABLE_OOO_NO_EOPG_SKEW_DESIRED_FIFO_IS_CURRENT_FIFO__SHIFT 0x19
#define PA_SC_ENHANCE__OOO_DISABLE_EOP_ON_FIRST_LIVE_PRIM_HIT_MASK 0x4000000
#define PA_SC_ENHANCE__OOO_DISABLE_EOP_ON_FIRST_LIVE_PRIM_HIT__SHIFT 0x1a
#define PA_SC_ENHANCE__OOO_DISABLE_EOPG_SKEW_THRESHOLD_SWITCHING_MASK 0x8000000
#define PA_SC_ENHANCE__OOO_DISABLE_EOPG_SKEW_THRESHOLD_SWITCHING__SHIFT 0x1b
#define PA_SC_ENHANCE__DISABLE_EOP_LINE_STIPPLE_RESET_MASK 0x10000000
#define PA_SC_ENHANCE__DISABLE_EOP_LINE_STIPPLE_RESET__SHIFT 0x1c
#define PA_SC_ENHANCE__DISABLE_VPZ_EOP_LINE_STIPPLE_RESET_MASK 0x20000000
#define PA_SC_ENHANCE__DISABLE_VPZ_EOP_LINE_STIPPLE_RESET__SHIFT 0x1d
#define PA_SC_ENHANCE__ECO_SPARE1_MASK 0x40000000
#define PA_SC_ENHANCE__ECO_SPARE1__SHIFT 0x1e
#define PA_SC_ENHANCE__ECO_SPARE0_MASK 0x80000000
#define PA_SC_ENHANCE__ECO_SPARE0__SHIFT 0x1f
#define PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE_MASK 0x3f
#define PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE__SHIFT 0x0
#define PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE_MASK 0x7fc0
#define PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT 0x6
#define PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE_MASK 0x1f8000
#define PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE__SHIFT 0xf
#define PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE_MASK 0xff800000
#define PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE__SHIFT 0x17
#define PA_SC_IF_FIFO_SIZE__SC_DB_TILE_IF_FIFO_SIZE_MASK 0x3f
#define PA_SC_IF_FIFO_SIZE__SC_DB_TILE_IF_FIFO_SIZE__SHIFT 0x0
#define PA_SC_IF_FIFO_SIZE__SC_DB_QUAD_IF_FIFO_SIZE_MASK 0xfc0
#define PA_SC_IF_FIFO_SIZE__SC_DB_QUAD_IF_FIFO_SIZE__SHIFT 0x6
#define PA_SC_IF_FIFO_SIZE__SC_SPI_IF_FIFO_SIZE_MASK 0x3f000
#define PA_SC_IF_FIFO_SIZE__SC_SPI_IF_FIFO_SIZE__SHIFT 0xc
#define PA_SC_IF_FIFO_SIZE__SC_BCI_IF_FIFO_SIZE_MASK 0xfc0000
#define PA_SC_IF_FIFO_SIZE__SC_BCI_IF_FIFO_SIZE__SHIFT 0x12
#define PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_CLK_CNT_MASK 0xffff
#define PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_CLK_CNT__SHIFT 0x0
#define PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_REZ_CNT_MASK 0xffff0000
#define PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_REZ_CNT__SHIFT 0x10
#define PA_SC_LINE_STIPPLE_STATE__CURRENT_PTR_MASK 0xf
#define PA_SC_LINE_STIPPLE_STATE__CURRENT_PTR__SHIFT 0x0
#define PA_SC_LINE_STIPPLE_STATE__CURRENT_COUNT_MASK 0xff00
#define PA_SC_LINE_STIPPLE_STATE__CURRENT_COUNT__SHIFT 0x8
#define PA_SC_SCREEN_EXTENT_MIN_0__X_MASK 0xffff
#define PA_SC_SCREEN_EXTENT_MIN_0__X__SHIFT 0x0
#define PA_SC_SCREEN_EXTENT_MIN_0__Y_MASK 0xffff0000
#define PA_SC_SCREEN_EXTENT_MIN_0__Y__SHIFT 0x10
#define PA_SC_SCREEN_EXTENT_MAX_0__X_MASK 0xffff
#define PA_SC_SCREEN_EXTENT_MAX_0__X__SHIFT 0x0
#define PA_SC_SCREEN_EXTENT_MAX_0__Y_MASK 0xffff0000
#define PA_SC_SCREEN_EXTENT_MAX_0__Y__SHIFT 0x10
#define PA_SC_SCREEN_EXTENT_MIN_1__X_MASK 0xffff
#define PA_SC_SCREEN_EXTENT_MIN_1__X__SHIFT 0x0
#define PA_SC_SCREEN_EXTENT_MIN_1__Y_MASK 0xffff0000
#define PA_SC_SCREEN_EXTENT_MIN_1__Y__SHIFT 0x10
#define PA_SC_SCREEN_EXTENT_MAX_1__X_MASK 0xffff
#define PA_SC_SCREEN_EXTENT_MAX_1__X__SHIFT 0x0
#define PA_SC_SCREEN_EXTENT_MAX_1__Y_MASK 0xffff0000
#define PA_SC_SCREEN_EXTENT_MAX_1__Y__SHIFT 0x10
#define PA_SC_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x3ff
#define PA_SC_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
#define PA_SC_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0xffc00
#define PA_SC_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
#define PA_SC_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000
#define PA_SC_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
#define PA_SC_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x3ff
#define PA_SC_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0
#define PA_SC_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0xffc00
#define PA_SC_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
#define PA_SC_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x3ff
#define PA_SC_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
#define PA_SC_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x3ff
#define PA_SC_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0
#define PA_SC_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x3ff
#define PA_SC_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0
#define PA_SC_PERFCOUNTER4_SELECT__PERF_SEL_MASK 0x3ff
#define PA_SC_PERFCOUNTER4_SELECT__PERF_SEL__SHIFT 0x0
#define PA_SC_PERFCOUNTER5_SELECT__PERF_SEL_MASK 0x3ff
#define PA_SC_PERFCOUNTER5_SELECT__PERF_SEL__SHIFT 0x0
#define PA_SC_PERFCOUNTER6_SELECT__PERF_SEL_MASK 0x3ff
#define PA_SC_PERFCOUNTER6_SELECT__PERF_SEL__SHIFT 0x0
#define PA_SC_PERFCOUNTER7_SELECT__PERF_SEL_MASK 0x3ff
#define PA_SC_PERFCOUNTER7_SELECT__PERF_SEL__SHIFT 0x0
#define PA_SC_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff
#define PA_SC_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
#define PA_SC_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff
#define PA_SC_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
#define PA_SC_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff
#define PA_SC_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
#define PA_SC_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff
#define PA_SC_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
#define PA_SC_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffff
#define PA_SC_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0
#define PA_SC_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffff
#define PA_SC_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0
#define PA_SC_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffff
#define PA_SC_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0
#define PA_SC_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffff
#define PA_SC_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0
#define PA_SC_PERFCOUNTER4_LO__PERFCOUNTER_LO_MASK 0xffffffff
#define PA_SC_PERFCOUNTER4_LO__PERFCOUNTER_LO__SHIFT 0x0
#define PA_SC_PERFCOUNTER4_HI__PERFCOUNTER_HI_MASK 0xffffffff
#define PA_SC_PERFCOUNTER4_HI__PERFCOUNTER_HI__SHIFT 0x0
#define PA_SC_PERFCOUNTER5_LO__PERFCOUNTER_LO_MASK 0xffffffff
#define PA_SC_PERFCOUNTER5_LO__PERFCOUNTER_LO__SHIFT 0x0
#define PA_SC_PERFCOUNTER5_HI__PERFCOUNTER_HI_MASK 0xffffffff
#define PA_SC_PERFCOUNTER5_HI__PERFCOUNTER_HI__SHIFT 0x0
#define PA_SC_PERFCOUNTER6_LO__PERFCOUNTER_LO_MASK 0xffffffff
#define PA_SC_PERFCOUNTER6_LO__PERFCOUNTER_LO__SHIFT 0x0
#define PA_SC_PERFCOUNTER6_HI__PERFCOUNTER_HI_MASK 0xffffffff
#define PA_SC_PERFCOUNTER6_HI__PERFCOUNTER_HI__SHIFT 0x0
#define PA_SC_PERFCOUNTER7_LO__PERFCOUNTER_LO_MASK 0xffffffff
#define PA_SC_PERFCOUNTER7_LO__PERFCOUNTER_LO__SHIFT 0x0
#define PA_SC_PERFCOUNTER7_HI__PERFCOUNTER_HI_MASK 0xffffffff
#define PA_SC_PERFCOUNTER7_HI__PERFCOUNTER_HI__SHIFT 0x0
#define PA_SC_P3D_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER_MASK 0x1
#define PA_SC_P3D_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER__SHIFT 0x0
#define PA_SC_P3D_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS_MASK 0x2
#define PA_SC_P3D_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS__SHIFT 0x1
#define PA_SC_P3D_TRAP_SCREEN_H__X_COORD_MASK 0x3fff
#define PA_SC_P3D_TRAP_SCREEN_H__X_COORD__SHIFT 0x0
#define PA_SC_P3D_TRAP_SCREEN_V__Y_COORD_MASK 0x3fff
#define PA_SC_P3D_TRAP_SCREEN_V__Y_COORD__SHIFT 0x0
#define PA_SC_P3D_TRAP_SCREEN_OCCURRENCE__COUNT_MASK 0xffff
#define PA_SC_P3D_TRAP_SCREEN_OCCURRENCE__COUNT__SHIFT 0x0
#define PA_SC_P3D_TRAP_SCREEN_COUNT__COUNT_MASK 0xffff
#define PA_SC_P3D_TRAP_SCREEN_COUNT__COUNT__SHIFT 0x0
#define PA_SC_HP3D_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER_MASK 0x1
#define PA_SC_HP3D_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER__SHIFT 0x0
#define PA_SC_HP3D_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS_MASK 0x2
#define PA_SC_HP3D_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS__SHIFT 0x1
#define PA_SC_HP3D_TRAP_SCREEN_H__X_COORD_MASK 0x3fff
#define PA_SC_HP3D_TRAP_SCREEN_H__X_COORD__SHIFT 0x0
#define PA_SC_HP3D_TRAP_SCREEN_V__Y_COORD_MASK 0x3fff
#define PA_SC_HP3D_TRAP_SCREEN_V__Y_COORD__SHIFT 0x0
#define PA_SC_HP3D_TRAP_SCREEN_OCCURRENCE__COUNT_MASK 0xffff
#define PA_SC_HP3D_TRAP_SCREEN_OCCURRENCE__COUNT__SHIFT 0x0
#define PA_SC_HP3D_TRAP_SCREEN_COUNT__COUNT_MASK 0xffff
#define PA_SC_HP3D_TRAP_SCREEN_COUNT__COUNT__SHIFT 0x0
#define PA_SC_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER_MASK 0x1
#define PA_SC_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER__SHIFT 0x0
#define PA_SC_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS_MASK 0x2
#define PA_SC_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS__SHIFT 0x1
#define PA_SC_TRAP_SCREEN_H__X_COORD_MASK 0x3fff
#define PA_SC_TRAP_SCREEN_H__X_COORD__SHIFT 0x0
#define PA_SC_TRAP_SCREEN_V__Y_COORD_MASK 0x3fff
#define PA_SC_TRAP_SCREEN_V__Y_COORD__SHIFT 0x0
#define PA_SC_TRAP_SCREEN_OCCURRENCE__COUNT_MASK 0xffff
#define PA_SC_TRAP_SCREEN_OCCURRENCE__COUNT__SHIFT 0x0
#define PA_SC_TRAP_SCREEN_COUNT__COUNT_MASK 0xffff
#define PA_SC_TRAP_SCREEN_COUNT__COUNT__SHIFT 0x0
#define PA_SC_P3D_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES_MASK 0x1
#define PA_SC_P3D_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES__SHIFT 0x0
#define PA_SC_HP3D_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES_MASK 0x1
#define PA_SC_HP3D_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES__SHIFT 0x0
#define PA_SC_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES_MASK 0x1
#define PA_SC_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES__SHIFT 0x0
#define PA_CL_CNTL_STATUS__CL_BUSY_MASK 0x80000000
#define PA_CL_CNTL_STATUS__CL_BUSY__SHIFT 0x1f
#define PA_SU_CNTL_STATUS__SU_BUSY_MASK 0x80000000
#define PA_SU_CNTL_STATUS__SU_BUSY__SHIFT 0x1f
#define PA_SC_FIFO_DEPTH_CNTL__DEPTH_MASK 0x3ff
#define PA_SC_FIFO_DEPTH_CNTL__DEPTH__SHIFT 0x0
#define CGTT_PA_CLK_CTRL__ON_DELAY_MASK 0xf
#define CGTT_PA_CLK_CTRL__ON_DELAY__SHIFT 0x0
#define CGTT_PA_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0
#define CGTT_PA_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x1000000
#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18
#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x2000000
#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19
#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x4000000
#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a
#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x8000000
#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b
#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000
#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c
#define CGTT_PA_CLK_CTRL__SU_CLK_OVERRIDE_MASK 0x20000000
#define CGTT_PA_CLK_CTRL__SU_CLK_OVERRIDE__SHIFT 0x1d
#define CGTT_PA_CLK_CTRL__CL_CLK_OVERRIDE_MASK 0x40000000
#define CGTT_PA_CLK_CTRL__CL_CLK_OVERRIDE__SHIFT 0x1e
#define CGTT_PA_CLK_CTRL__REG_CLK_OVERRIDE_MASK 0x80000000
#define CGTT_PA_CLK_CTRL__REG_CLK_OVERRIDE__SHIFT 0x1f
#define CGTT_SC_CLK_CTRL__ON_DELAY_MASK 0xf
#define CGTT_SC_CLK_CTRL__ON_DELAY__SHIFT 0x0
#define CGTT_SC_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0
#define CGTT_SC_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x1000000
#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18
#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x2000000
#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19
#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x4000000
#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a
#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x8000000
#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b
#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000
#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c
#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000
#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d
#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000
#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e
#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000
#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f
#define PA_SU_DEBUG_CNTL__SU_DEBUG_INDX_MASK 0x1f
#define PA_SU_DEBUG_CNTL__SU_DEBUG_INDX__SHIFT 0x0
#define PA_SU_DEBUG_DATA__DATA_MASK 0xffffffff
#define PA_SU_DEBUG_DATA__DATA__SHIFT 0x0
#define PA_SC_DEBUG_CNTL__SC_DEBUG_INDX_MASK 0x3f
#define PA_SC_DEBUG_CNTL__SC_DEBUG_INDX__SHIFT 0x0
#define PA_SC_DEBUG_DATA__DATA_MASK 0xffffffff
#define PA_SC_DEBUG_DATA__DATA__SHIFT 0x0
#define CLIPPER_DEBUG_REG00__ALWAYS_ZERO_MASK 0xff
#define CLIPPER_DEBUG_REG00__ALWAYS_ZERO__SHIFT 0x0
#define CLIPPER_DEBUG_REG00__clip_ga_bc_fifo_write_MASK 0x100
#define CLIPPER_DEBUG_REG00__clip_ga_bc_fifo_write__SHIFT 0x8
#define CLIPPER_DEBUG_REG00__su_clip_baryc_free_MASK 0x600
#define CLIPPER_DEBUG_REG00__su_clip_baryc_free__SHIFT 0x9
#define CLIPPER_DEBUG_REG00__clip_to_ga_fifo_write_MASK 0x800
#define CLIPPER_DEBUG_REG00__clip_to_ga_fifo_write__SHIFT 0xb
#define CLIPPER_DEBUG_REG00__clip_to_ga_fifo_full_MASK 0x1000
#define CLIPPER_DEBUG_REG00__clip_to_ga_fifo_full__SHIFT 0xc
#define CLIPPER_DEBUG_REG00__primic_to_clprim_fifo_empty_MASK 0x2000
#define CLIPPER_DEBUG_REG00__primic_to_clprim_fifo_empty__SHIFT 0xd
#define CLIPPER_DEBUG_REG00__primic_to_clprim_fifo_full_MASK 0x4000
#define CLIPPER_DEBUG_REG00__primic_to_clprim_fifo_full__SHIFT 0xe
#define CLIPPER_DEBUG_REG00__clip_to_outsm_fifo_empty_MASK 0x8000
#define CLIPPER_DEBUG_REG00__clip_to_outsm_fifo_empty__SHIFT 0xf
#define CLIPPER_DEBUG_REG00__clip_to_outsm_fifo_full_MASK 0x10000
#define CLIPPER_DEBUG_REG00__clip_to_outsm_fifo_full__SHIFT 0x10
#define CLIPPER_DEBUG_REG00__vgt_to_clipp_fifo_empty_MASK 0x20000
#define CLIPPER_DEBUG_REG00__vgt_to_clipp_fifo_empty__SHIFT 0x11
#define CLIPPER_DEBUG_REG00__vgt_to_clipp_fifo_full_MASK 0x40000
#define CLIPPER_DEBUG_REG00__vgt_to_clipp_fifo_full__SHIFT 0x12
#define CLIPPER_DEBUG_REG00__vgt_to_clips_fifo_empty_MASK 0x80000
#define CLIPPER_DEBUG_REG00__vgt_to_clips_fifo_empty__SHIFT 0x13
#define CLIPPER_DEBUG_REG00__vgt_to_clips_fifo_full_MASK 0x100000
#define CLIPPER_DEBUG_REG00__vgt_to_clips_fifo_full__SHIFT 0x14
#define CLIPPER_DEBUG_REG00__clipcode_fifo_fifo_empty_MASK 0x200000
#define CLIPPER_DEBUG_REG00__clipcode_fifo_fifo_empty__SHIFT 0x15
#define CLIPPER_DEBUG_REG00__clipcode_fifo_full_MASK 0x400000
#define CLIPPER_DEBUG_REG00__clipcode_fifo_full__SHIFT 0x16
#define CLIPPER_DEBUG_REG00__vte_out_clip_fifo_fifo_empty_MASK 0x800000
#define CLIPPER_DEBUG_REG00__vte_out_clip_fifo_fifo_empty__SHIFT 0x17
#define CLIPPER_DEBUG_REG00__vte_out_clip_fifo_fifo_full_MASK 0x1000000
#define CLIPPER_DEBUG_REG00__vte_out_clip_fifo_fifo_full__SHIFT 0x18
#define CLIPPER_DEBUG_REG00__vte_out_orig_fifo_fifo_empty_MASK 0x2000000
#define CLIPPER_DEBUG_REG00__vte_out_orig_fifo_fifo_empty__SHIFT 0x19
#define CLIPPER_DEBUG_REG00__vte_out_orig_fifo_fifo_full_MASK 0x4000000
#define CLIPPER_DEBUG_REG00__vte_out_orig_fifo_fifo_full__SHIFT 0x1a
#define CLIPPER_DEBUG_REG00__ccgen_to_clipcc_fifo_empty_MASK 0x8000000
#define CLIPPER_DEBUG_REG00__ccgen_to_clipcc_fifo_empty__SHIFT 0x1b
#define CLIPPER_DEBUG_REG00__ccgen_to_clipcc_fifo_full_MASK 0x10000000
#define CLIPPER_DEBUG_REG00__ccgen_to_clipcc_fifo_full__SHIFT 0x1c
#define CLIPPER_DEBUG_REG00__clip_to_outsm_fifo_write_MASK 0x20000000
#define CLIPPER_DEBUG_REG00__clip_to_outsm_fifo_write__SHIFT 0x1d
#define CLIPPER_DEBUG_REG00__vte_out_orig_fifo_fifo_write_MASK 0x40000000
#define CLIPPER_DEBUG_REG00__vte_out_orig_fifo_fifo_write__SHIFT 0x1e
#define CLIPPER_DEBUG_REG00__vgt_to_clipp_fifo_write_MASK 0x80000000
#define CLIPPER_DEBUG_REG00__vgt_to_clipp_fifo_write__SHIFT 0x1f
#define CLIPPER_DEBUG_REG01__ALWAYS_ZERO_MASK 0xff
#define CLIPPER_DEBUG_REG01__ALWAYS_ZERO__SHIFT 0x0
#define CLIPPER_DEBUG_REG01__clip_extra_bc_valid_MASK 0x700
#define CLIPPER_DEBUG_REG01__clip_extra_bc_valid__SHIFT 0x8
#define CLIPPER_DEBUG_REG01__clip_vert_vte_valid_MASK 0x3800
#define CLIPPER_DEBUG_REG01__clip_vert_vte_valid__SHIFT 0xb
#define CLIPPER_DEBUG_REG01__clip_to_outsm_vertex_deallocate_MASK 0x1c000
#define CLIPPER_DEBUG_REG01__clip_to_outsm_vertex_deallocate__SHIFT 0xe
#define CLIPPER_DEBUG_REG01__clip_to_outsm_deallocate_slot_MASK 0xe0000
#define CLIPPER_DEBUG_REG01__clip_to_outsm_deallocate_slot__SHIFT 0x11
#define CLIPPER_DEBUG_REG01__clip_to_outsm_null_primitive_MASK 0x100000
#define CLIPPER_DEBUG_REG01__clip_to_outsm_null_primitive__SHIFT 0x14
#define CLIPPER_DEBUG_REG01__vte_positions_vte_clip_vte_naninf_kill_2_MASK 0x200000
#define CLIPPER_DEBUG_REG01__vte_positions_vte_clip_vte_naninf_kill_2__SHIFT 0x15
#define CLIPPER_DEBUG_REG01__vte_positions_vte_clip_vte_naninf_kill_1_MASK 0x400000
#define CLIPPER_DEBUG_REG01__vte_positions_vte_clip_vte_naninf_kill_1__SHIFT 0x16
#define CLIPPER_DEBUG_REG01__vte_positions_vte_clip_vte_naninf_kill_0_MASK 0x800000
#define CLIPPER_DEBUG_REG01__vte_positions_vte_clip_vte_naninf_kill_0__SHIFT 0x17
#define CLIPPER_DEBUG_REG01__vte_out_clip_rd_extra_bc_valid_MASK 0x1000000
#define CLIPPER_DEBUG_REG01__vte_out_clip_rd_extra_bc_valid__SHIFT 0x18
#define CLIPPER_DEBUG_REG01__vte_out_clip_rd_vte_naninf_kill_MASK 0x2000000
#define CLIPPER_DEBUG_REG01__vte_out_clip_rd_vte_naninf_kill__SHIFT 0x19
#define CLIPPER_DEBUG_REG01__vte_out_clip_rd_vertex_store_indx_MASK 0xc000000
#define CLIPPER_DEBUG_REG01__vte_out_clip_rd_vertex_store_indx__SHIFT 0x1a
#define CLIPPER_DEBUG_REG01__clip_ga_bc_fifo_write_MASK 0x10000000
#define CLIPPER_DEBUG_REG01__clip_ga_bc_fifo_write__SHIFT 0x1c
#define CLIPPER_DEBUG_REG01__clip_to_ga_fifo_write_MASK 0x20000000
#define CLIPPER_DEBUG_REG01__clip_to_ga_fifo_write__SHIFT 0x1d
#define CLIPPER_DEBUG_REG01__vte_out_clip_fifo_fifo_advanceread_MASK 0x40000000
#define CLIPPER_DEBUG_REG01__vte_out_clip_fifo_fifo_advanceread__SHIFT 0x1e
#define CLIPPER_DEBUG_REG01__vte_out_clip_fifo_fifo_empty_MASK 0x80000000
#define CLIPPER_DEBUG_REG01__vte_out_clip_fifo_fifo_empty__SHIFT 0x1f
#define CLIPPER_DEBUG_REG02__clip_extra_bc_valid_MASK 0x7
#define CLIPPER_DEBUG_REG02__clip_extra_bc_valid__SHIFT 0x0
#define CLIPPER_DEBUG_REG02__clip_vert_vte_valid_MASK 0x38
#define CLIPPER_DEBUG_REG02__clip_vert_vte_valid__SHIFT 0x3
#define CLIPPER_DEBUG_REG02__clip_to_outsm_clip_seq_indx_MASK 0xc0
#define CLIPPER_DEBUG_REG02__clip_to_outsm_clip_seq_indx__SHIFT 0x6
#define CLIPPER_DEBUG_REG02__clip_to_outsm_vertex_store_indx_2_MASK 0xf00
#define CLIPPER_DEBUG_REG02__clip_to_outsm_vertex_store_indx_2__SHIFT 0x8
#define CLIPPER_DEBUG_REG02__clip_to_outsm_vertex_store_indx_1_MASK 0xf000
#define CLIPPER_DEBUG_REG02__clip_to_outsm_vertex_store_indx_1__SHIFT 0xc
#define CLIPPER_DEBUG_REG02__clip_to_outsm_vertex_store_indx_0_MASK 0xf0000
#define CLIPPER_DEBUG_REG02__clip_to_outsm_vertex_store_indx_0__SHIFT 0x10
#define CLIPPER_DEBUG_REG02__clip_to_clipga_extra_bc_coords_MASK 0x100000
#define CLIPPER_DEBUG_REG02__clip_to_clipga_extra_bc_coords__SHIFT 0x14
#define CLIPPER_DEBUG_REG02__clip_to_clipga_vte_naninf_kill_MASK 0x200000
#define CLIPPER_DEBUG_REG02__clip_to_clipga_vte_naninf_kill__SHIFT 0x15
#define CLIPPER_DEBUG_REG02__clip_to_outsm_end_of_packet_MASK 0x400000
#define CLIPPER_DEBUG_REG02__clip_to_outsm_end_of_packet__SHIFT 0x16
#define CLIPPER_DEBUG_REG02__clip_to_outsm_first_prim_of_slot_MASK 0x800000
#define CLIPPER_DEBUG_REG02__clip_to_outsm_first_prim_of_slot__SHIFT 0x17
#define CLIPPER_DEBUG_REG02__clip_to_outsm_clipped_prim_MASK 0x1000000
#define CLIPPER_DEBUG_REG02__clip_to_outsm_clipped_prim__SHIFT 0x18
#define CLIPPER_DEBUG_REG02__clip_to_outsm_null_primitive_MASK 0x2000000
#define CLIPPER_DEBUG_REG02__clip_to_outsm_null_primitive__SHIFT 0x19
#define CLIPPER_DEBUG_REG02__clip_ga_bc_fifo_full_MASK 0x4000000
#define CLIPPER_DEBUG_REG02__clip_ga_bc_fifo_full__SHIFT 0x1a
#define CLIPPER_DEBUG_REG02__clip_to_ga_fifo_full_MASK 0x8000000
#define CLIPPER_DEBUG_REG02__clip_to_ga_fifo_full__SHIFT 0x1b
#define CLIPPER_DEBUG_REG02__clip_ga_bc_fifo_write_MASK 0x10000000
#define CLIPPER_DEBUG_REG02__clip_ga_bc_fifo_write__SHIFT 0x1c
#define CLIPPER_DEBUG_REG02__clip_to_ga_fifo_write_MASK 0x20000000
#define CLIPPER_DEBUG_REG02__clip_to_ga_fifo_write__SHIFT 0x1d
#define CLIPPER_DEBUG_REG02__clip_to_outsm_fifo_advanceread_MASK 0x40000000
#define CLIPPER_DEBUG_REG02__clip_to_outsm_fifo_advanceread__SHIFT 0x1e
#define CLIPPER_DEBUG_REG02__clip_to_outsm_fifo_empty_MASK 0x80000000
#define CLIPPER_DEBUG_REG02__clip_to_outsm_fifo_empty__SHIFT 0x1f
#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_clip_code_or_MASK 0x3fff
#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_clip_code_or__SHIFT 0x0
#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_event_id_MASK 0xfc000
#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_event_id__SHIFT 0xe
#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_state_var_indx_MASK 0x700000
#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_state_var_indx__SHIFT 0x14
#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_clip_primitive_MASK 0x800000
#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_clip_primitive__SHIFT 0x17
#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_deallocate_slot_MASK 0x7000000
#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_deallocate_slot__SHIFT 0x18
#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_first_prim_of_slot_MASK 0x8000000
#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_first_prim_of_slot__SHIFT 0x1b
#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_end_of_packet_MASK 0x10000000
#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_end_of_packet__SHIFT 0x1c
#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_event_MASK 0x20000000
#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_event__SHIFT 0x1d
#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_null_primitive_MASK 0x40000000
#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_null_primitive__SHIFT 0x1e
#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_prim_valid_MASK 0x80000000
#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_prim_valid__SHIFT 0x1f
#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_param_cache_indx_0_MASK 0x7fe
#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_param_cache_indx_0__SHIFT 0x1
#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_vertex_store_indx_2_MASK 0x1f800
#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_vertex_store_indx_2__SHIFT 0xb
#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_vertex_store_indx_1_MASK 0x7e0000
#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_vertex_store_indx_1__SHIFT 0x11
#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_vertex_store_indx_0_MASK 0x1f800000
#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_vertex_store_indx_0__SHIFT 0x17
#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_event_MASK 0x20000000
#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_event__SHIFT 0x1d
#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_null_primitive_MASK 0x40000000
#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_null_primitive__SHIFT 0x1e
#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_prim_valid_MASK 0x80000000
#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_prim_valid__SHIFT 0x1f
#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_clip_code_or_MASK 0x3fff
#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_clip_code_or__SHIFT 0x0
#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_event_id_MASK 0xfc000
#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_event_id__SHIFT 0xe
#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_state_var_indx_MASK 0x700000
#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_state_var_indx__SHIFT 0x14
#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_clip_primitive_MASK 0x800000
#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_clip_primitive__SHIFT 0x17
#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_deallocate_slot_MASK 0x7000000
#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_deallocate_slot__SHIFT 0x18
#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_first_prim_of_slot_MASK 0x8000000
#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_first_prim_of_slot__SHIFT 0x1b
#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_end_of_packet_MASK 0x10000000
#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_end_of_packet__SHIFT 0x1c
#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_event_MASK 0x20000000
#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_event__SHIFT 0x1d
#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_null_primitive_MASK 0x40000000
#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_null_primitive__SHIFT 0x1e
#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_prim_valid_MASK 0x80000000
#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_prim_valid__SHIFT 0x1f
#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_param_cache_indx_0_MASK 0x7fe
#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_param_cache_indx_0__SHIFT 0x1
#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_vertex_store_indx_2_MASK 0x1f800
#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_vertex_store_indx_2__SHIFT 0xb
#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_vertex_store_indx_1_MASK 0x7e0000
#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_vertex_store_indx_1__SHIFT 0x11
#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_vertex_store_indx_0_MASK 0x1f800000
#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_vertex_store_indx_0__SHIFT 0x17
#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_event_MASK 0x20000000
#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_event__SHIFT 0x1d
#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_null_primitive_MASK 0x40000000
#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_null_primitive__SHIFT 0x1e
#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_prim_valid_MASK 0x80000000
#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_prim_valid__SHIFT 0x1f
#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_clip_code_or_MASK 0x3fff
#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_clip_code_or__SHIFT 0x0
#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_event_id_MASK 0xfc000
#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_event_id__SHIFT 0xe
#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_state_var_indx_MASK 0x700000
#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_state_var_indx__SHIFT 0x14
#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_clip_primitive_MASK 0x800000
#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_clip_primitive__SHIFT 0x17
#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_deallocate_slot_MASK 0x7000000
#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_deallocate_slot__SHIFT 0x18
#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_first_prim_of_slot_MASK 0x8000000
#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_first_prim_of_slot__SHIFT 0x1b
#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_end_of_packet_MASK 0x10000000
#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_end_of_packet__SHIFT 0x1c
#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_event_MASK 0x20000000
#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_event__SHIFT 0x1d
#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_null_primitive_MASK 0x40000000
#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_null_primitive__SHIFT 0x1e
#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_prim_valid_MASK 0x80000000
#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_prim_valid__SHIFT 0x1f
#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_param_cache_indx_0_MASK 0x7fe
#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_param_cache_indx_0__SHIFT 0x1
#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_vertex_store_indx_2_MASK 0x1f800
#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_vertex_store_indx_2__SHIFT 0xb
#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_vertex_store_indx_1_MASK 0x7e0000
#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_vertex_store_indx_1__SHIFT 0x11
#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_vertex_store_indx_0_MASK 0x1f800000
#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_vertex_store_indx_0__SHIFT 0x17
#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_event_MASK 0x20000000
#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_event__SHIFT 0x1d
#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_null_primitive_MASK 0x40000000
#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_null_primitive__SHIFT 0x1e
#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_prim_valid_MASK 0x80000000
#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_prim_valid__SHIFT 0x1f
#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_clip_code_or_MASK 0x3fff
#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_clip_code_or__SHIFT 0x0
#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_event_id_MASK 0xfc000
#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_event_id__SHIFT 0xe
#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_state_var_indx_MASK 0x700000
#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_state_var_indx__SHIFT 0x14
#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_clip_primitive_MASK 0x800000
#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_clip_primitive__SHIFT 0x17
#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_deallocate_slot_MASK 0x7000000
#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_deallocate_slot__SHIFT 0x18
#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_first_prim_of_slot_MASK 0x8000000
#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_first_prim_of_slot__SHIFT 0x1b
#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_end_of_packet_MASK 0x10000000
#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_end_of_packet__SHIFT 0x1c
#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_event_MASK 0x20000000
#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_event__SHIFT 0x1d
#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_null_primitive_MASK 0x40000000
#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_null_primitive__SHIFT 0x1e
#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_prim_valid_MASK 0x80000000
#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_prim_valid__SHIFT 0x1f
#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_param_cache_indx_0_MASK 0x7fe
#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_param_cache_indx_0__SHIFT 0x1
#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_vertex_store_indx_2_MASK 0x1f800
#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_vertex_store_indx_2__SHIFT 0xb
#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_vertex_store_indx_1_MASK 0x7e0000
#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_vertex_store_indx_1__SHIFT 0x11
#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_vertex_store_indx_0_MASK 0x1f800000
#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_vertex_store_indx_0__SHIFT 0x17
#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_event_MASK 0x20000000
#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_event__SHIFT 0x1d
#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_null_primitive_MASK 0x40000000
#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_null_primitive__SHIFT 0x1e
#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_prim_valid_MASK 0x80000000
#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_prim_valid__SHIFT 0x1f
#define CLIPPER_DEBUG_REG11__clipsm3_clip_to_clipga_event_MASK 0x1
#define CLIPPER_DEBUG_REG11__clipsm3_clip_to_clipga_event__SHIFT 0x0
#define CLIPPER_DEBUG_REG11__clipsm2_clip_to_clipga_event_MASK 0x2
#define CLIPPER_DEBUG_REG11__clipsm2_clip_to_clipga_event__SHIFT 0x1
#define CLIPPER_DEBUG_REG11__clipsm1_clip_to_clipga_event_MASK 0x4
#define CLIPPER_DEBUG_REG11__clipsm1_clip_to_clipga_event__SHIFT 0x2
#define CLIPPER_DEBUG_REG11__clipsm0_clip_to_clipga_event_MASK 0x8
#define CLIPPER_DEBUG_REG11__clipsm0_clip_to_clipga_event__SHIFT 0x3
#define CLIPPER_DEBUG_REG11__clipsm3_clip_to_clipga_clip_primitive_MASK 0x10
#define CLIPPER_DEBUG_REG11__clipsm3_clip_to_clipga_clip_primitive__SHIFT 0x4
#define CLIPPER_DEBUG_REG11__clipsm2_clip_to_clipga_clip_primitive_MASK 0x20
#define CLIPPER_DEBUG_REG11__clipsm2_clip_to_clipga_clip_primitive__SHIFT 0x5
#define CLIPPER_DEBUG_REG11__clipsm1_clip_to_clipga_clip_primitive_MASK 0x40
#define CLIPPER_DEBUG_REG11__clipsm1_clip_to_clipga_clip_primitive__SHIFT 0x6
#define CLIPPER_DEBUG_REG11__clipsm0_clip_to_clipga_clip_primitive_MASK 0x80
#define CLIPPER_DEBUG_REG11__clipsm0_clip_to_clipga_clip_primitive__SHIFT 0x7
#define CLIPPER_DEBUG_REG11__clipsm3_clip_to_clipga_clip_to_outsm_cnt_MASK 0xf00
#define CLIPPER_DEBUG_REG11__clipsm3_clip_to_clipga_clip_to_outsm_cnt__SHIFT 0x8
#define CLIPPER_DEBUG_REG11__clipsm2_clip_to_clipga_clip_to_outsm_cnt_MASK 0xf000
#define CLIPPER_DEBUG_REG11__clipsm2_clip_to_clipga_clip_to_outsm_cnt__SHIFT 0xc
#define CLIPPER_DEBUG_REG11__clipsm1_clip_to_clipga_clip_to_outsm_cnt_MASK 0xf0000
#define CLIPPER_DEBUG_REG11__clipsm1_clip_to_clipga_clip_to_outsm_cnt__SHIFT 0x10
#define CLIPPER_DEBUG_REG11__clipsm0_clip_to_clipga_clip_to_outsm_cnt_MASK 0xf00000
#define CLIPPER_DEBUG_REG11__clipsm0_clip_to_clipga_clip_to_outsm_cnt__SHIFT 0x14
#define CLIPPER_DEBUG_REG11__clipsm3_clip_to_clipga_prim_valid_MASK 0x1000000
#define CLIPPER_DEBUG_REG11__clipsm3_clip_to_clipga_prim_valid__SHIFT 0x18
#define CLIPPER_DEBUG_REG11__clipsm2_clip_to_clipga_prim_valid_MASK 0x2000000
#define CLIPPER_DEBUG_REG11__clipsm2_clip_to_clipga_prim_valid__SHIFT 0x19
#define CLIPPER_DEBUG_REG11__clipsm1_clip_to_clipga_prim_valid_MASK 0x4000000
#define CLIPPER_DEBUG_REG11__clipsm1_clip_to_clipga_prim_valid__SHIFT 0x1a
#define CLIPPER_DEBUG_REG11__clipsm0_clip_to_clipga_prim_valid_MASK 0x8000000
#define CLIPPER_DEBUG_REG11__clipsm0_clip_to_clipga_prim_valid__SHIFT 0x1b
#define CLIPPER_DEBUG_REG11__clipsm3_inc_clip_to_clipga_clip_to_outsm_cnt_MASK 0x10000000
#define CLIPPER_DEBUG_REG11__clipsm3_inc_clip_to_clipga_clip_to_outsm_cnt__SHIFT 0x1c
#define CLIPPER_DEBUG_REG11__clipsm2_inc_clip_to_clipga_clip_to_outsm_cnt_MASK 0x20000000
#define CLIPPER_DEBUG_REG11__clipsm2_inc_clip_to_clipga_clip_to_outsm_cnt__SHIFT 0x1d
#define CLIPPER_DEBUG_REG11__clipsm1_inc_clip_to_clipga_clip_to_outsm_cnt_MASK 0x40000000
#define CLIPPER_DEBUG_REG11__clipsm1_inc_clip_to_clipga_clip_to_outsm_cnt__SHIFT 0x1e
#define CLIPPER_DEBUG_REG11__clipsm0_inc_clip_to_clipga_clip_to_outsm_cnt_MASK 0x80000000
#define CLIPPER_DEBUG_REG11__clipsm0_inc_clip_to_clipga_clip_to_outsm_cnt__SHIFT 0x1f
#define CLIPPER_DEBUG_REG12__ALWAYS_ZERO_MASK 0xff
#define CLIPPER_DEBUG_REG12__ALWAYS_ZERO__SHIFT 0x0
#define CLIPPER_DEBUG_REG12__clip_priority_available_vte_out_clip_MASK 0x1f00
#define CLIPPER_DEBUG_REG12__clip_priority_available_vte_out_clip__SHIFT 0x8
#define CLIPPER_DEBUG_REG12__clip_priority_available_clip_verts_MASK 0x3e000
#define CLIPPER_DEBUG_REG12__clip_priority_available_clip_verts__SHIFT 0xd
#define CLIPPER_DEBUG_REG12__clip_priority_seq_indx_out_MASK 0xc0000
#define CLIPPER_DEBUG_REG12__clip_priority_seq_indx_out__SHIFT 0x12
#define CLIPPER_DEBUG_REG12__clip_priority_seq_indx_vert_MASK 0x300000
#define CLIPPER_DEBUG_REG12__clip_priority_seq_indx_vert__SHIFT 0x14
#define CLIPPER_DEBUG_REG12__clip_priority_seq_indx_load_MASK 0xc00000
#define CLIPPER_DEBUG_REG12__clip_priority_seq_indx_load__SHIFT 0x16
#define CLIPPER_DEBUG_REG12__clipsm3_clprim_to_clip_clip_primitive_MASK 0x1000000
#define CLIPPER_DEBUG_REG12__clipsm3_clprim_to_clip_clip_primitive__SHIFT 0x18
#define CLIPPER_DEBUG_REG12__clipsm3_clprim_to_clip_prim_valid_MASK 0x2000000
#define CLIPPER_DEBUG_REG12__clipsm3_clprim_to_clip_prim_valid__SHIFT 0x19
#define CLIPPER_DEBUG_REG12__clipsm2_clprim_to_clip_clip_primitive_MASK 0x4000000
#define CLIPPER_DEBUG_REG12__clipsm2_clprim_to_clip_clip_primitive__SHIFT 0x1a
#define CLIPPER_DEBUG_REG12__clipsm2_clprim_to_clip_prim_valid_MASK 0x8000000
#define CLIPPER_DEBUG_REG12__clipsm2_clprim_to_clip_prim_valid__SHIFT 0x1b
#define CLIPPER_DEBUG_REG12__clipsm1_clprim_to_clip_clip_primitive_MASK 0x10000000
#define CLIPPER_DEBUG_REG12__clipsm1_clprim_to_clip_clip_primitive__SHIFT 0x1c
#define CLIPPER_DEBUG_REG12__clipsm1_clprim_to_clip_prim_valid_MASK 0x20000000
#define CLIPPER_DEBUG_REG12__clipsm1_clprim_to_clip_prim_valid__SHIFT 0x1d
#define CLIPPER_DEBUG_REG12__clipsm0_clprim_to_clip_clip_primitive_MASK 0x40000000
#define CLIPPER_DEBUG_REG12__clipsm0_clprim_to_clip_clip_primitive__SHIFT 0x1e
#define CLIPPER_DEBUG_REG12__clipsm0_clprim_to_clip_prim_valid_MASK 0x80000000
#define CLIPPER_DEBUG_REG12__clipsm0_clprim_to_clip_prim_valid__SHIFT 0x1f
#define CLIPPER_DEBUG_REG13__clprim_in_back_state_var_indx_MASK 0x7
#define CLIPPER_DEBUG_REG13__clprim_in_back_state_var_indx__SHIFT 0x0
#define CLIPPER_DEBUG_REG13__point_clip_candidate_MASK 0x8
#define CLIPPER_DEBUG_REG13__point_clip_candidate__SHIFT 0x3
#define CLIPPER_DEBUG_REG13__prim_nan_kill_MASK 0x10
#define CLIPPER_DEBUG_REG13__prim_nan_kill__SHIFT 0x4
#define CLIPPER_DEBUG_REG13__clprim_clip_primitive_MASK 0x20
#define CLIPPER_DEBUG_REG13__clprim_clip_primitive__SHIFT 0x5
#define CLIPPER_DEBUG_REG13__clprim_cull_primitive_MASK 0x40
#define CLIPPER_DEBUG_REG13__clprim_cull_primitive__SHIFT 0x6
#define CLIPPER_DEBUG_REG13__prim_back_valid_MASK 0x80
#define CLIPPER_DEBUG_REG13__prim_back_valid__SHIFT 0x7
#define CLIPPER_DEBUG_REG13__vertval_bits_vertex_cc_next_valid_MASK 0xf00
#define CLIPPER_DEBUG_REG13__vertval_bits_vertex_cc_next_valid__SHIFT 0x8
#define CLIPPER_DEBUG_REG13__clipcc_vertex_store_indx_MASK 0x3000
#define CLIPPER_DEBUG_REG13__clipcc_vertex_store_indx__SHIFT 0xc
#define CLIPPER_DEBUG_REG13__vte_out_orig_fifo_fifo_empty_MASK 0x4000
#define CLIPPER_DEBUG_REG13__vte_out_orig_fifo_fifo_empty__SHIFT 0xe
#define CLIPPER_DEBUG_REG13__clipcode_fifo_fifo_empty_MASK 0x8000
#define CLIPPER_DEBUG_REG13__clipcode_fifo_fifo_empty__SHIFT 0xf
#define CLIPPER_DEBUG_REG13__ccgen_to_clipcc_fifo_empty_MASK 0x10000
#define CLIPPER_DEBUG_REG13__ccgen_to_clipcc_fifo_empty__SHIFT 0x10
#define CLIPPER_DEBUG_REG13__clip_priority_seq_indx_out_cnt_MASK 0x1e0000
#define CLIPPER_DEBUG_REG13__clip_priority_seq_indx_out_cnt__SHIFT 0x11
#define CLIPPER_DEBUG_REG13__outsm_clr_rd_orig_vertices_MASK 0x600000
#define CLIPPER_DEBUG_REG13__outsm_clr_rd_orig_vertices__SHIFT 0x15
#define CLIPPER_DEBUG_REG13__outsm_clr_rd_clipsm_wait_MASK 0x800000
#define CLIPPER_DEBUG_REG13__outsm_clr_rd_clipsm_wait__SHIFT 0x17
#define CLIPPER_DEBUG_REG13__outsm_clr_fifo_contents_MASK 0x1f000000
#define CLIPPER_DEBUG_REG13__outsm_clr_fifo_contents__SHIFT 0x18
#define CLIPPER_DEBUG_REG13__outsm_clr_fifo_full_MASK 0x20000000
#define CLIPPER_DEBUG_REG13__outsm_clr_fifo_full__SHIFT 0x1d
#define CLIPPER_DEBUG_REG13__outsm_clr_fifo_advanceread_MASK 0x40000000
#define CLIPPER_DEBUG_REG13__outsm_clr_fifo_advanceread__SHIFT 0x1e
#define CLIPPER_DEBUG_REG13__outsm_clr_fifo_write_MASK 0x80000000
#define CLIPPER_DEBUG_REG13__outsm_clr_fifo_write__SHIFT 0x1f
#define CLIPPER_DEBUG_REG14__clprim_in_back_vertex_store_indx_2_MASK 0x3f
#define CLIPPER_DEBUG_REG14__clprim_in_back_vertex_store_indx_2__SHIFT 0x0
#define CLIPPER_DEBUG_REG14__clprim_in_back_vertex_store_indx_1_MASK 0xfc0
#define CLIPPER_DEBUG_REG14__clprim_in_back_vertex_store_indx_1__SHIFT 0x6
#define CLIPPER_DEBUG_REG14__clprim_in_back_vertex_store_indx_0_MASK 0x3f000
#define CLIPPER_DEBUG_REG14__clprim_in_back_vertex_store_indx_0__SHIFT 0xc
#define CLIPPER_DEBUG_REG14__outputclprimtoclip_null_primitive_MASK 0x40000
#define CLIPPER_DEBUG_REG14__outputclprimtoclip_null_primitive__SHIFT 0x12
#define CLIPPER_DEBUG_REG14__clprim_in_back_end_of_packet_MASK 0x80000
#define CLIPPER_DEBUG_REG14__clprim_in_back_end_of_packet__SHIFT 0x13
#define CLIPPER_DEBUG_REG14__clprim_in_back_first_prim_of_slot_MASK 0x100000
#define CLIPPER_DEBUG_REG14__clprim_in_back_first_prim_of_slot__SHIFT 0x14
#define CLIPPER_DEBUG_REG14__clprim_in_back_deallocate_slot_MASK 0xe00000
#define CLIPPER_DEBUG_REG14__clprim_in_back_deallocate_slot__SHIFT 0x15
#define CLIPPER_DEBUG_REG14__clprim_in_back_event_id_MASK 0x3f000000
#define CLIPPER_DEBUG_REG14__clprim_in_back_event_id__SHIFT 0x18
#define CLIPPER_DEBUG_REG14__clprim_in_back_event_MASK 0x40000000
#define CLIPPER_DEBUG_REG14__clprim_in_back_event__SHIFT 0x1e
#define CLIPPER_DEBUG_REG14__prim_back_valid_MASK 0x80000000
#define CLIPPER_DEBUG_REG14__prim_back_valid__SHIFT 0x1f
#define CLIPPER_DEBUG_REG15__vertval_bits_vertex_vertex_store_msb_MASK 0xffff
#define CLIPPER_DEBUG_REG15__vertval_bits_vertex_vertex_store_msb__SHIFT 0x0
#define CLIPPER_DEBUG_REG15__primic_to_clprim_fifo_vertex_store_indx_2_MASK 0x1f0000
#define CLIPPER_DEBUG_REG15__primic_to_clprim_fifo_vertex_store_indx_2__SHIFT 0x10
#define CLIPPER_DEBUG_REG15__primic_to_clprim_fifo_vertex_store_indx_1_MASK 0x3e00000
#define CLIPPER_DEBUG_REG15__primic_to_clprim_fifo_vertex_store_indx_1__SHIFT 0x15
#define CLIPPER_DEBUG_REG15__primic_to_clprim_fifo_vertex_store_indx_0_MASK 0x7c000000
#define CLIPPER_DEBUG_REG15__primic_to_clprim_fifo_vertex_store_indx_0__SHIFT 0x1a
#define CLIPPER_DEBUG_REG15__primic_to_clprim_valid_MASK 0x80000000
#define CLIPPER_DEBUG_REG15__primic_to_clprim_valid__SHIFT 0x1f
#define CLIPPER_DEBUG_REG16__sm0_prim_end_state_MASK 0x7f
#define CLIPPER_DEBUG_REG16__sm0_prim_end_state__SHIFT 0x0
#define CLIPPER_DEBUG_REG16__sm0_ps_expand_MASK 0x80
#define CLIPPER_DEBUG_REG16__sm0_ps_expand__SHIFT 0x7
#define CLIPPER_DEBUG_REG16__sm0_clip_vert_cnt_MASK 0x1f00
#define CLIPPER_DEBUG_REG16__sm0_clip_vert_cnt__SHIFT 0x8
#define CLIPPER_DEBUG_REG16__sm0_vertex_clip_cnt_MASK 0x3e000
#define CLIPPER_DEBUG_REG16__sm0_vertex_clip_cnt__SHIFT 0xd
#define CLIPPER_DEBUG_REG16__sm0_inv_to_clip_data_valid_1_MASK 0x40000
#define CLIPPER_DEBUG_REG16__sm0_inv_to_clip_data_valid_1__SHIFT 0x12
#define CLIPPER_DEBUG_REG16__sm0_inv_to_clip_data_valid_0_MASK 0x80000
#define CLIPPER_DEBUG_REG16__sm0_inv_to_clip_data_valid_0__SHIFT 0x13
#define CLIPPER_DEBUG_REG16__sm0_current_state_MASK 0x7f00000
#define CLIPPER_DEBUG_REG16__sm0_current_state__SHIFT 0x14
#define CLIPPER_DEBUG_REG16__sm0_clip_to_clipga_clip_to_outsm_cnt_eq0_MASK 0x8000000
#define CLIPPER_DEBUG_REG16__sm0_clip_to_clipga_clip_to_outsm_cnt_eq0__SHIFT 0x1b
#define CLIPPER_DEBUG_REG16__sm0_clip_to_outsm_fifo_full_MASK 0x10000000
#define CLIPPER_DEBUG_REG16__sm0_clip_to_outsm_fifo_full__SHIFT 0x1c
#define CLIPPER_DEBUG_REG16__sm0_highest_priority_seq_MASK 0x20000000
#define CLIPPER_DEBUG_REG16__sm0_highest_priority_seq__SHIFT 0x1d
#define CLIPPER_DEBUG_REG16__sm0_outputcliptoclipga_0_MASK 0x40000000
#define CLIPPER_DEBUG_REG16__sm0_outputcliptoclipga_0__SHIFT 0x1e
#define CLIPPER_DEBUG_REG16__sm0_clprim_to_clip_prim_valid_MASK 0x80000000
#define CLIPPER_DEBUG_REG16__sm0_clprim_to_clip_prim_valid__SHIFT 0x1f
#define CLIPPER_DEBUG_REG17__sm1_prim_end_state_MASK 0x7f
#define CLIPPER_DEBUG_REG17__sm1_prim_end_state__SHIFT 0x0
#define CLIPPER_DEBUG_REG17__sm1_ps_expand_MASK 0x80
#define CLIPPER_DEBUG_REG17__sm1_ps_expand__SHIFT 0x7
#define CLIPPER_DEBUG_REG17__sm1_clip_vert_cnt_MASK 0x1f00
#define CLIPPER_DEBUG_REG17__sm1_clip_vert_cnt__SHIFT 0x8
#define CLIPPER_DEBUG_REG17__sm1_vertex_clip_cnt_MASK 0x3e000
#define CLIPPER_DEBUG_REG17__sm1_vertex_clip_cnt__SHIFT 0xd
#define CLIPPER_DEBUG_REG17__sm1_inv_to_clip_data_valid_1_MASK 0x40000
#define CLIPPER_DEBUG_REG17__sm1_inv_to_clip_data_valid_1__SHIFT 0x12
#define CLIPPER_DEBUG_REG17__sm1_inv_to_clip_data_valid_0_MASK 0x80000
#define CLIPPER_DEBUG_REG17__sm1_inv_to_clip_data_valid_0__SHIFT 0x13
#define CLIPPER_DEBUG_REG17__sm1_current_state_MASK 0x7f00000
#define CLIPPER_DEBUG_REG17__sm1_current_state__SHIFT 0x14
#define CLIPPER_DEBUG_REG17__sm1_clip_to_clipga_clip_to_outsm_cnt_eq0_MASK 0x8000000
#define CLIPPER_DEBUG_REG17__sm1_clip_to_clipga_clip_to_outsm_cnt_eq0__SHIFT 0x1b
#define CLIPPER_DEBUG_REG17__sm1_clip_to_outsm_fifo_full_MASK 0x10000000
#define CLIPPER_DEBUG_REG17__sm1_clip_to_outsm_fifo_full__SHIFT 0x1c
#define CLIPPER_DEBUG_REG17__sm1_highest_priority_seq_MASK 0x20000000
#define CLIPPER_DEBUG_REG17__sm1_highest_priority_seq__SHIFT 0x1d
#define CLIPPER_DEBUG_REG17__sm1_outputcliptoclipga_0_MASK 0x40000000
#define CLIPPER_DEBUG_REG17__sm1_outputcliptoclipga_0__SHIFT 0x1e
#define CLIPPER_DEBUG_REG17__sm1_clprim_to_clip_prim_valid_MASK 0x80000000
#define CLIPPER_DEBUG_REG17__sm1_clprim_to_clip_prim_valid__SHIFT 0x1f
#define CLIPPER_DEBUG_REG18__sm2_prim_end_state_MASK 0x7f
#define CLIPPER_DEBUG_REG18__sm2_prim_end_state__SHIFT 0x0
#define CLIPPER_DEBUG_REG18__sm2_ps_expand_MASK 0x80
#define CLIPPER_DEBUG_REG18__sm2_ps_expand__SHIFT 0x7
#define CLIPPER_DEBUG_REG18__sm2_clip_vert_cnt_MASK 0x1f00
#define CLIPPER_DEBUG_REG18__sm2_clip_vert_cnt__SHIFT 0x8
#define CLIPPER_DEBUG_REG18__sm2_vertex_clip_cnt_MASK 0x3e000
#define CLIPPER_DEBUG_REG18__sm2_vertex_clip_cnt__SHIFT 0xd
#define CLIPPER_DEBUG_REG18__sm2_inv_to_clip_data_valid_1_MASK 0x40000
#define CLIPPER_DEBUG_REG18__sm2_inv_to_clip_data_valid_1__SHIFT 0x12
#define CLIPPER_DEBUG_REG18__sm2_inv_to_clip_data_valid_0_MASK 0x80000
#define CLIPPER_DEBUG_REG18__sm2_inv_to_clip_data_valid_0__SHIFT 0x13
#define CLIPPER_DEBUG_REG18__sm2_current_state_MASK 0x7f00000
#define CLIPPER_DEBUG_REG18__sm2_current_state__SHIFT 0x14
#define CLIPPER_DEBUG_REG18__sm2_clip_to_clipga_clip_to_outsm_cnt_eq0_MASK 0x8000000
#define CLIPPER_DEBUG_REG18__sm2_clip_to_clipga_clip_to_outsm_cnt_eq0__SHIFT 0x1b
#define CLIPPER_DEBUG_REG18__sm2_clip_to_outsm_fifo_full_MASK 0x10000000
#define CLIPPER_DEBUG_REG18__sm2_clip_to_outsm_fifo_full__SHIFT 0x1c
#define CLIPPER_DEBUG_REG18__sm2_highest_priority_seq_MASK 0x20000000
#define CLIPPER_DEBUG_REG18__sm2_highest_priority_seq__SHIFT 0x1d
#define CLIPPER_DEBUG_REG18__sm2_outputcliptoclipga_0_MASK 0x40000000
#define CLIPPER_DEBUG_REG18__sm2_outputcliptoclipga_0__SHIFT 0x1e
#define CLIPPER_DEBUG_REG18__sm2_clprim_to_clip_prim_valid_MASK 0x80000000
#define CLIPPER_DEBUG_REG18__sm2_clprim_to_clip_prim_valid__SHIFT 0x1f
#define CLIPPER_DEBUG_REG19__sm3_prim_end_state_MASK 0x7f
#define CLIPPER_DEBUG_REG19__sm3_prim_end_state__SHIFT 0x0
#define CLIPPER_DEBUG_REG19__sm3_ps_expand_MASK 0x80
#define CLIPPER_DEBUG_REG19__sm3_ps_expand__SHIFT 0x7
#define CLIPPER_DEBUG_REG19__sm3_clip_vert_cnt_MASK 0x1f00
#define CLIPPER_DEBUG_REG19__sm3_clip_vert_cnt__SHIFT 0x8
#define CLIPPER_DEBUG_REG19__sm3_vertex_clip_cnt_MASK 0x3e000
#define CLIPPER_DEBUG_REG19__sm3_vertex_clip_cnt__SHIFT 0xd
#define CLIPPER_DEBUG_REG19__sm3_inv_to_clip_data_valid_1_MASK 0x40000
#define CLIPPER_DEBUG_REG19__sm3_inv_to_clip_data_valid_1__SHIFT 0x12
#define CLIPPER_DEBUG_REG19__sm3_inv_to_clip_data_valid_0_MASK 0x80000
#define CLIPPER_DEBUG_REG19__sm3_inv_to_clip_data_valid_0__SHIFT 0x13
#define CLIPPER_DEBUG_REG19__sm3_current_state_MASK 0x7f00000
#define CLIPPER_DEBUG_REG19__sm3_current_state__SHIFT 0x14
#define CLIPPER_DEBUG_REG19__sm3_clip_to_clipga_clip_to_outsm_cnt_eq0_MASK 0x8000000
#define CLIPPER_DEBUG_REG19__sm3_clip_to_clipga_clip_to_outsm_cnt_eq0__SHIFT 0x1b
#define CLIPPER_DEBUG_REG19__sm3_clip_to_outsm_fifo_full_MASK 0x10000000
#define CLIPPER_DEBUG_REG19__sm3_clip_to_outsm_fifo_full__SHIFT 0x1c
#define CLIPPER_DEBUG_REG19__sm3_highest_priority_seq_MASK 0x20000000
#define CLIPPER_DEBUG_REG19__sm3_highest_priority_seq__SHIFT 0x1d
#define CLIPPER_DEBUG_REG19__sm3_outputcliptoclipga_0_MASK 0x40000000
#define CLIPPER_DEBUG_REG19__sm3_outputcliptoclipga_0__SHIFT 0x1e
#define CLIPPER_DEBUG_REG19__sm3_clprim_to_clip_prim_valid_MASK 0x80000000
#define CLIPPER_DEBUG_REG19__sm3_clprim_to_clip_prim_valid__SHIFT 0x1f
#define SXIFCCG_DEBUG_REG0__position_address_MASK 0x3f
#define SXIFCCG_DEBUG_REG0__position_address__SHIFT 0x0
#define SXIFCCG_DEBUG_REG0__point_address_MASK 0x1c0
#define SXIFCCG_DEBUG_REG0__point_address__SHIFT 0x6
#define SXIFCCG_DEBUG_REG0__sx_pending_rd_state_var_indx_MASK 0xe00
#define SXIFCCG_DEBUG_REG0__sx_pending_rd_state_var_indx__SHIFT 0x9
#define SXIFCCG_DEBUG_REG0__sx_pending_rd_req_mask_MASK 0xf000
#define SXIFCCG_DEBUG_REG0__sx_pending_rd_req_mask__SHIFT 0xc
#define SXIFCCG_DEBUG_REG0__sx_pending_rd_pci_MASK 0x3ff0000
#define SXIFCCG_DEBUG_REG0__sx_pending_rd_pci__SHIFT 0x10
#define SXIFCCG_DEBUG_REG0__sx_pending_rd_aux_sel_MASK 0xc000000
#define SXIFCCG_DEBUG_REG0__sx_pending_rd_aux_sel__SHIFT 0x1a
#define SXIFCCG_DEBUG_REG0__sx_pending_rd_sp_id_MASK 0x30000000
#define SXIFCCG_DEBUG_REG0__sx_pending_rd_sp_id__SHIFT 0x1c
#define SXIFCCG_DEBUG_REG0__sx_pending_rd_aux_inc_MASK 0x40000000
#define SXIFCCG_DEBUG_REG0__sx_pending_rd_aux_inc__SHIFT 0x1e
#define SXIFCCG_DEBUG_REG0__sx_pending_rd_advance_MASK 0x80000000
#define SXIFCCG_DEBUG_REG0__sx_pending_rd_advance__SHIFT 0x1f
#define SXIFCCG_DEBUG_REG1__available_positions_MASK 0x7f
#define SXIFCCG_DEBUG_REG1__available_positions__SHIFT 0x0
#define SXIFCCG_DEBUG_REG1__sx_receive_indx_MASK 0x380
#define SXIFCCG_DEBUG_REG1__sx_receive_indx__SHIFT 0x7
#define SXIFCCG_DEBUG_REG1__sx_pending_fifo_contents_MASK 0x7c00
#define SXIFCCG_DEBUG_REG1__sx_pending_fifo_contents__SHIFT 0xa
#define SXIFCCG_DEBUG_REG1__statevar_bits_vs_out_misc_vec_ena_MASK 0x8000
#define SXIFCCG_DEBUG_REG1__statevar_bits_vs_out_misc_vec_ena__SHIFT 0xf
#define SXIFCCG_DEBUG_REG1__statevar_bits_disable_sp_MASK 0xf0000
#define SXIFCCG_DEBUG_REG1__statevar_bits_disable_sp__SHIFT 0x10
#define SXIFCCG_DEBUG_REG1__aux_sel_MASK 0x300000
#define SXIFCCG_DEBUG_REG1__aux_sel__SHIFT 0x14
#define SXIFCCG_DEBUG_REG1__sx_to_pa_empty_1_MASK 0x400000
#define SXIFCCG_DEBUG_REG1__sx_to_pa_empty_1__SHIFT 0x16
#define SXIFCCG_DEBUG_REG1__sx_to_pa_empty_0_MASK 0x800000
#define SXIFCCG_DEBUG_REG1__sx_to_pa_empty_0__SHIFT 0x17
#define SXIFCCG_DEBUG_REG1__pasx_req_cnt_1_MASK 0xf000000
#define SXIFCCG_DEBUG_REG1__pasx_req_cnt_1__SHIFT 0x18
#define SXIFCCG_DEBUG_REG1__pasx_req_cnt_0_MASK 0xf0000000
#define SXIFCCG_DEBUG_REG1__pasx_req_cnt_0__SHIFT 0x1c
#define SXIFCCG_DEBUG_REG2__param_cache_base_MASK 0x7f
#define SXIFCCG_DEBUG_REG2__param_cache_base__SHIFT 0x0
#define SXIFCCG_DEBUG_REG2__sx_aux_MASK 0x180
#define SXIFCCG_DEBUG_REG2__sx_aux__SHIFT 0x7
#define SXIFCCG_DEBUG_REG2__sx_request_indx_MASK 0x7e00
#define SXIFCCG_DEBUG_REG2__sx_request_indx__SHIFT 0x9
#define SXIFCCG_DEBUG_REG2__req_active_verts_loaded_MASK 0x8000
#define SXIFCCG_DEBUG_REG2__req_active_verts_loaded__SHIFT 0xf
#define SXIFCCG_DEBUG_REG2__req_active_verts_MASK 0x7f0000
#define SXIFCCG_DEBUG_REG2__req_active_verts__SHIFT 0x10
#define SXIFCCG_DEBUG_REG2__vgt_to_ccgen_state_var_indx_MASK 0x3800000
#define SXIFCCG_DEBUG_REG2__vgt_to_ccgen_state_var_indx__SHIFT 0x17
#define SXIFCCG_DEBUG_REG2__vgt_to_ccgen_active_verts_MASK 0xfc000000
#define SXIFCCG_DEBUG_REG2__vgt_to_ccgen_active_verts__SHIFT 0x1a
#define SXIFCCG_DEBUG_REG3__ALWAYS_ZERO_MASK 0xff
#define SXIFCCG_DEBUG_REG3__ALWAYS_ZERO__SHIFT 0x0
#define SXIFCCG_DEBUG_REG3__vertex_fifo_entriesavailable_MASK 0xf00
#define SXIFCCG_DEBUG_REG3__vertex_fifo_entriesavailable__SHIFT 0x8
#define SXIFCCG_DEBUG_REG3__statevar_bits_vs_out_ccdist1_vec_ena_MASK 0x1000
#define SXIFCCG_DEBUG_REG3__statevar_bits_vs_out_ccdist1_vec_ena__SHIFT 0xc
#define SXIFCCG_DEBUG_REG3__statevar_bits_vs_out_ccdist0_vec_ena_MASK 0x2000
#define SXIFCCG_DEBUG_REG3__statevar_bits_vs_out_ccdist0_vec_ena__SHIFT 0xd
#define SXIFCCG_DEBUG_REG3__available_positions_MASK 0x1fc000
#define SXIFCCG_DEBUG_REG3__available_positions__SHIFT 0xe
#define SXIFCCG_DEBUG_REG3__current_state_MASK 0x600000
#define SXIFCCG_DEBUG_REG3__current_state__SHIFT 0x15
#define SXIFCCG_DEBUG_REG3__vertex_fifo_empty_MASK 0x800000
#define SXIFCCG_DEBUG_REG3__vertex_fifo_empty__SHIFT 0x17
#define SXIFCCG_DEBUG_REG3__vertex_fifo_full_MASK 0x1000000
#define SXIFCCG_DEBUG_REG3__vertex_fifo_full__SHIFT 0x18
#define SXIFCCG_DEBUG_REG3__sx0_receive_fifo_empty_MASK 0x2000000
#define SXIFCCG_DEBUG_REG3__sx0_receive_fifo_empty__SHIFT 0x19
#define SXIFCCG_DEBUG_REG3__sx0_receive_fifo_full_MASK 0x4000000
#define SXIFCCG_DEBUG_REG3__sx0_receive_fifo_full__SHIFT 0x1a
#define SXIFCCG_DEBUG_REG3__vgt_to_ccgen_fifo_empty_MASK 0x8000000
#define SXIFCCG_DEBUG_REG3__vgt_to_ccgen_fifo_empty__SHIFT 0x1b
#define SXIFCCG_DEBUG_REG3__vgt_to_ccgen_fifo_full_MASK 0x10000000
#define SXIFCCG_DEBUG_REG3__vgt_to_ccgen_fifo_full__SHIFT 0x1c
#define SXIFCCG_DEBUG_REG3__ccgen_to_clipcc_fifo_full_MASK 0x20000000
#define SXIFCCG_DEBUG_REG3__ccgen_to_clipcc_fifo_full__SHIFT 0x1d
#define SXIFCCG_DEBUG_REG3__sx0_receive_fifo_write_MASK 0x40000000
#define SXIFCCG_DEBUG_REG3__sx0_receive_fifo_write__SHIFT 0x1e
#define SXIFCCG_DEBUG_REG3__ccgen_to_clipcc_write_MASK 0x80000000
#define SXIFCCG_DEBUG_REG3__ccgen_to_clipcc_write__SHIFT 0x1f
#define SETUP_DEBUG_REG0__su_baryc_cntl_state_MASK 0x3
#define SETUP_DEBUG_REG0__su_baryc_cntl_state__SHIFT 0x0
#define SETUP_DEBUG_REG0__su_cntl_state_MASK 0x3c
#define SETUP_DEBUG_REG0__su_cntl_state__SHIFT 0x2
#define SETUP_DEBUG_REG0__pmode_state_MASK 0x3f00
#define SETUP_DEBUG_REG0__pmode_state__SHIFT 0x8
#define SETUP_DEBUG_REG0__ge_stallb_MASK 0x4000
#define SETUP_DEBUG_REG0__ge_stallb__SHIFT 0xe
#define SETUP_DEBUG_REG0__geom_enable_MASK 0x8000
#define SETUP_DEBUG_REG0__geom_enable__SHIFT 0xf
#define SETUP_DEBUG_REG0__su_clip_baryc_free_MASK 0x30000
#define SETUP_DEBUG_REG0__su_clip_baryc_free__SHIFT 0x10
#define SETUP_DEBUG_REG0__su_clip_rtr_MASK 0x40000
#define SETUP_DEBUG_REG0__su_clip_rtr__SHIFT 0x12
#define SETUP_DEBUG_REG0__pfifo_busy_MASK 0x80000
#define SETUP_DEBUG_REG0__pfifo_busy__SHIFT 0x13
#define SETUP_DEBUG_REG0__su_cntl_busy_MASK 0x100000
#define SETUP_DEBUG_REG0__su_cntl_busy__SHIFT 0x14
#define SETUP_DEBUG_REG0__geom_busy_MASK 0x200000
#define SETUP_DEBUG_REG0__geom_busy__SHIFT 0x15
#define SETUP_DEBUG_REG0__event_id_gated_MASK 0xfc00000
#define SETUP_DEBUG_REG0__event_id_gated__SHIFT 0x16
#define SETUP_DEBUG_REG0__event_gated_MASK 0x10000000
#define SETUP_DEBUG_REG0__event_gated__SHIFT 0x1c
#define SETUP_DEBUG_REG0__pmode_prim_gated_MASK 0x20000000
#define SETUP_DEBUG_REG0__pmode_prim_gated__SHIFT 0x1d
#define SETUP_DEBUG_REG0__su_dyn_sclk_vld_MASK 0x40000000
#define SETUP_DEBUG_REG0__su_dyn_sclk_vld__SHIFT 0x1e
#define SETUP_DEBUG_REG0__cl_dyn_sclk_vld_MASK 0x80000000
#define SETUP_DEBUG_REG0__cl_dyn_sclk_vld__SHIFT 0x1f
#define SETUP_DEBUG_REG1__y_sort0_gated_23_8_MASK 0xffff
#define SETUP_DEBUG_REG1__y_sort0_gated_23_8__SHIFT 0x0
#define SETUP_DEBUG_REG1__x_sort0_gated_23_8_MASK 0xffff0000
#define SETUP_DEBUG_REG1__x_sort0_gated_23_8__SHIFT 0x10
#define SETUP_DEBUG_REG2__y_sort1_gated_23_8_MASK 0xffff
#define SETUP_DEBUG_REG2__y_sort1_gated_23_8__SHIFT 0x0
#define SETUP_DEBUG_REG2__x_sort1_gated_23_8_MASK 0xffff0000
#define SETUP_DEBUG_REG2__x_sort1_gated_23_8__SHIFT 0x10
#define SETUP_DEBUG_REG3__y_sort2_gated_23_8_MASK 0xffff
#define SETUP_DEBUG_REG3__y_sort2_gated_23_8__SHIFT 0x0
#define SETUP_DEBUG_REG3__x_sort2_gated_23_8_MASK 0xffff0000
#define SETUP_DEBUG_REG3__x_sort2_gated_23_8__SHIFT 0x10
#define SETUP_DEBUG_REG4__attr_indx_sort0_gated_MASK 0x3fff
#define SETUP_DEBUG_REG4__attr_indx_sort0_gated__SHIFT 0x0
#define SETUP_DEBUG_REG4__null_prim_gated_MASK 0x4000
#define SETUP_DEBUG_REG4__null_prim_gated__SHIFT 0xe
#define SETUP_DEBUG_REG4__backfacing_gated_MASK 0x8000
#define SETUP_DEBUG_REG4__backfacing_gated__SHIFT 0xf
#define SETUP_DEBUG_REG4__st_indx_gated_MASK 0x70000
#define SETUP_DEBUG_REG4__st_indx_gated__SHIFT 0x10
#define SETUP_DEBUG_REG4__clipped_gated_MASK 0x80000
#define SETUP_DEBUG_REG4__clipped_gated__SHIFT 0x13
#define SETUP_DEBUG_REG4__dealloc_slot_gated_MASK 0x700000
#define SETUP_DEBUG_REG4__dealloc_slot_gated__SHIFT 0x14
#define SETUP_DEBUG_REG4__xmajor_gated_MASK 0x800000
#define SETUP_DEBUG_REG4__xmajor_gated__SHIFT 0x17
#define SETUP_DEBUG_REG4__diamond_rule_gated_MASK 0x3000000
#define SETUP_DEBUG_REG4__diamond_rule_gated__SHIFT 0x18
#define SETUP_DEBUG_REG4__type_gated_MASK 0x1c000000
#define SETUP_DEBUG_REG4__type_gated__SHIFT 0x1a
#define SETUP_DEBUG_REG4__fpov_gated_MASK 0x60000000
#define SETUP_DEBUG_REG4__fpov_gated__SHIFT 0x1d
#define SETUP_DEBUG_REG4__eop_gated_MASK 0x80000000
#define SETUP_DEBUG_REG4__eop_gated__SHIFT 0x1f
#define SETUP_DEBUG_REG5__attr_indx_sort2_gated_MASK 0x3fff
#define SETUP_DEBUG_REG5__attr_indx_sort2_gated__SHIFT 0x0
#define SETUP_DEBUG_REG5__attr_indx_sort1_gated_MASK 0xfffc000
#define SETUP_DEBUG_REG5__attr_indx_sort1_gated__SHIFT 0xe
#define SETUP_DEBUG_REG5__provoking_vtx_gated_MASK 0x30000000
#define SETUP_DEBUG_REG5__provoking_vtx_gated__SHIFT 0x1c
#define SETUP_DEBUG_REG5__valid_prim_gated_MASK 0x40000000
#define SETUP_DEBUG_REG5__valid_prim_gated__SHIFT 0x1e
#define SETUP_DEBUG_REG5__pa_reg_sclk_vld_MASK 0x80000000
#define SETUP_DEBUG_REG5__pa_reg_sclk_vld__SHIFT 0x1f
#define PA_SC_DEBUG_REG0__REG0_FIELD0_MASK 0x3
#define PA_SC_DEBUG_REG0__REG0_FIELD0__SHIFT 0x0
#define PA_SC_DEBUG_REG0__REG0_FIELD1_MASK 0xc
#define PA_SC_DEBUG_REG0__REG0_FIELD1__SHIFT 0x2
#define PA_SC_DEBUG_REG1__REG1_FIELD0_MASK 0x3
#define PA_SC_DEBUG_REG1__REG1_FIELD0__SHIFT 0x0
#define PA_SC_DEBUG_REG1__REG1_FIELD1_MASK 0xc
#define PA_SC_DEBUG_REG1__REG1_FIELD1__SHIFT 0x2
#define COMPUTE_DISPATCH_INITIATOR__COMPUTE_SHADER_EN_MASK 0x1
#define COMPUTE_DISPATCH_INITIATOR__COMPUTE_SHADER_EN__SHIFT 0x0
#define COMPUTE_DISPATCH_INITIATOR__PARTIAL_TG_EN_MASK 0x2
#define COMPUTE_DISPATCH_INITIATOR__PARTIAL_TG_EN__SHIFT 0x1
#define COMPUTE_DISPATCH_INITIATOR__FORCE_START_AT_000_MASK 0x4
#define COMPUTE_DISPATCH_INITIATOR__FORCE_START_AT_000__SHIFT 0x2
#define COMPUTE_DISPATCH_INITIATOR__ORDERED_APPEND_ENBL_MASK 0x8
#define COMPUTE_DISPATCH_INITIATOR__ORDERED_APPEND_ENBL__SHIFT 0x3
#define COMPUTE_DISPATCH_INITIATOR__ORDERED_APPEND_MODE_MASK 0x10
#define COMPUTE_DISPATCH_INITIATOR__ORDERED_APPEND_MODE__SHIFT 0x4
#define COMPUTE_DISPATCH_INITIATOR__USE_THREAD_DIMENSIONS_MASK 0x20
#define COMPUTE_DISPATCH_INITIATOR__USE_THREAD_DIMENSIONS__SHIFT 0x5
#define COMPUTE_DISPATCH_INITIATOR__ORDER_MODE_MASK 0x40
#define COMPUTE_DISPATCH_INITIATOR__ORDER_MODE__SHIFT 0x6
#define COMPUTE_DISPATCH_INITIATOR__DISPATCH_CACHE_CNTL_MASK 0x380
#define COMPUTE_DISPATCH_INITIATOR__DISPATCH_CACHE_CNTL__SHIFT 0x7
#define COMPUTE_DISPATCH_INITIATOR__SCALAR_L1_INV_VOL_MASK 0x400
#define COMPUTE_DISPATCH_INITIATOR__SCALAR_L1_INV_VOL__SHIFT 0xa
#define COMPUTE_DISPATCH_INITIATOR__VECTOR_L1_INV_VOL_MASK 0x800
#define COMPUTE_DISPATCH_INITIATOR__VECTOR_L1_INV_VOL__SHIFT 0xb
#define COMPUTE_DISPATCH_INITIATOR__DATA_ATC_MASK 0x1000
#define COMPUTE_DISPATCH_INITIATOR__DATA_ATC__SHIFT 0xc
#define COMPUTE_DISPATCH_INITIATOR__RESTORE_MASK 0x4000
#define COMPUTE_DISPATCH_INITIATOR__RESTORE__SHIFT 0xe
#define COMPUTE_DIM_X__SIZE_MASK 0xffffffff
#define COMPUTE_DIM_X__SIZE__SHIFT 0x0
#define COMPUTE_DIM_Y__SIZE_MASK 0xffffffff
#define COMPUTE_DIM_Y__SIZE__SHIFT 0x0
#define COMPUTE_DIM_Z__SIZE_MASK 0xffffffff
#define COMPUTE_DIM_Z__SIZE__SHIFT 0x0
#define COMPUTE_START_X__START_MASK 0xffffffff
#define COMPUTE_START_X__START__SHIFT 0x0
#define COMPUTE_START_Y__START_MASK 0xffffffff
#define COMPUTE_START_Y__START__SHIFT 0x0
#define COMPUTE_START_Z__START_MASK 0xffffffff
#define COMPUTE_START_Z__START__SHIFT 0x0
#define COMPUTE_NUM_THREAD_X__NUM_THREAD_FULL_MASK 0xffff
#define COMPUTE_NUM_THREAD_X__NUM_THREAD_FULL__SHIFT 0x0
#define COMPUTE_NUM_THREAD_X__NUM_THREAD_PARTIAL_MASK 0xffff0000
#define COMPUTE_NUM_THREAD_X__NUM_THREAD_PARTIAL__SHIFT 0x10
#define COMPUTE_NUM_THREAD_Y__NUM_THREAD_FULL_MASK 0xffff
#define COMPUTE_NUM_THREAD_Y__NUM_THREAD_FULL__SHIFT 0x0
#define COMPUTE_NUM_THREAD_Y__NUM_THREAD_PARTIAL_MASK 0xffff0000
#define COMPUTE_NUM_THREAD_Y__NUM_THREAD_PARTIAL__SHIFT 0x10
#define COMPUTE_NUM_THREAD_Z__NUM_THREAD_FULL_MASK 0xffff
#define COMPUTE_NUM_THREAD_Z__NUM_THREAD_FULL__SHIFT 0x0
#define COMPUTE_NUM_THREAD_Z__NUM_THREAD_PARTIAL_MASK 0xffff0000
#define COMPUTE_NUM_THREAD_Z__NUM_THREAD_PARTIAL__SHIFT 0x10
#define COMPUTE_PIPELINESTAT_ENABLE__PIPELINESTAT_ENABLE_MASK 0x1
#define COMPUTE_PIPELINESTAT_ENABLE__PIPELINESTAT_ENABLE__SHIFT 0x0
#define COMPUTE_PERFCOUNT_ENABLE__PERFCOUNT_ENABLE_MASK 0x1
#define COMPUTE_PERFCOUNT_ENABLE__PERFCOUNT_ENABLE__SHIFT 0x0
#define COMPUTE_PGM_LO__DATA_MASK 0xffffffff
#define COMPUTE_PGM_LO__DATA__SHIFT 0x0
#define COMPUTE_PGM_HI__DATA_MASK 0xff
#define COMPUTE_PGM_HI__DATA__SHIFT 0x0
#define COMPUTE_PGM_HI__INST_ATC_MASK 0x100
#define COMPUTE_PGM_HI__INST_ATC__SHIFT 0x8
#define COMPUTE_TBA_LO__DATA_MASK 0xffffffff
#define COMPUTE_TBA_LO__DATA__SHIFT 0x0
#define COMPUTE_TBA_HI__DATA_MASK 0xff
#define COMPUTE_TBA_HI__DATA__SHIFT 0x0
#define COMPUTE_TMA_LO__DATA_MASK 0xffffffff
#define COMPUTE_TMA_LO__DATA__SHIFT 0x0
#define COMPUTE_TMA_HI__DATA_MASK 0xff
#define COMPUTE_TMA_HI__DATA__SHIFT 0x0
#define COMPUTE_PGM_RSRC1__VGPRS_MASK 0x3f
#define COMPUTE_PGM_RSRC1__VGPRS__SHIFT 0x0
#define COMPUTE_PGM_RSRC1__SGPRS_MASK 0x3c0
#define COMPUTE_PGM_RSRC1__SGPRS__SHIFT 0x6
#define COMPUTE_PGM_RSRC1__PRIORITY_MASK 0xc00
#define COMPUTE_PGM_RSRC1__PRIORITY__SHIFT 0xa
#define COMPUTE_PGM_RSRC1__FLOAT_MODE_MASK 0xff000
#define COMPUTE_PGM_RSRC1__FLOAT_MODE__SHIFT 0xc
#define COMPUTE_PGM_RSRC1__PRIV_MASK 0x100000
#define COMPUTE_PGM_RSRC1__PRIV__SHIFT 0x14
#define COMPUTE_PGM_RSRC1__DX10_CLAMP_MASK 0x200000
#define COMPUTE_PGM_RSRC1__DX10_CLAMP__SHIFT 0x15
#define COMPUTE_PGM_RSRC1__DEBUG_MODE_MASK 0x400000
#define COMPUTE_PGM_RSRC1__DEBUG_MODE__SHIFT 0x16
#define COMPUTE_PGM_RSRC1__IEEE_MODE_MASK 0x800000
#define COMPUTE_PGM_RSRC1__IEEE_MODE__SHIFT 0x17
#define COMPUTE_PGM_RSRC1__BULKY_MASK 0x1000000
#define COMPUTE_PGM_RSRC1__BULKY__SHIFT 0x18
#define COMPUTE_PGM_RSRC1__CDBG_USER_MASK 0x2000000
#define COMPUTE_PGM_RSRC1__CDBG_USER__SHIFT 0x19
#define COMPUTE_PGM_RSRC2__SCRATCH_EN_MASK 0x1
#define COMPUTE_PGM_RSRC2__SCRATCH_EN__SHIFT 0x0
#define COMPUTE_PGM_RSRC2__USER_SGPR_MASK 0x3e
#define COMPUTE_PGM_RSRC2__USER_SGPR__SHIFT 0x1
#define COMPUTE_PGM_RSRC2__TRAP_PRESENT_MASK 0x40
#define COMPUTE_PGM_RSRC2__TRAP_PRESENT__SHIFT 0x6
#define COMPUTE_PGM_RSRC2__TGID_X_EN_MASK 0x80
#define COMPUTE_PGM_RSRC2__TGID_X_EN__SHIFT 0x7
#define COMPUTE_PGM_RSRC2__TGID_Y_EN_MASK 0x100
#define COMPUTE_PGM_RSRC2__TGID_Y_EN__SHIFT 0x8
#define COMPUTE_PGM_RSRC2__TGID_Z_EN_MASK 0x200
#define COMPUTE_PGM_RSRC2__TGID_Z_EN__SHIFT 0x9
#define COMPUTE_PGM_RSRC2__TG_SIZE_EN_MASK 0x400
#define COMPUTE_PGM_RSRC2__TG_SIZE_EN__SHIFT 0xa
#define COMPUTE_PGM_RSRC2__TIDIG_COMP_CNT_MASK 0x1800
#define COMPUTE_PGM_RSRC2__TIDIG_COMP_CNT__SHIFT 0xb
#define COMPUTE_PGM_RSRC2__EXCP_EN_MSB_MASK 0x6000
#define COMPUTE_PGM_RSRC2__EXCP_EN_MSB__SHIFT 0xd
#define COMPUTE_PGM_RSRC2__LDS_SIZE_MASK 0xff8000
#define COMPUTE_PGM_RSRC2__LDS_SIZE__SHIFT 0xf
#define COMPUTE_PGM_RSRC2__EXCP_EN_MASK 0x7f000000
#define COMPUTE_PGM_RSRC2__EXCP_EN__SHIFT 0x18
#define COMPUTE_VMID__DATA_MASK 0xf
#define COMPUTE_VMID__DATA__SHIFT 0x0
#define COMPUTE_RESOURCE_LIMITS__WAVES_PER_SH_MASK 0x3ff
#define COMPUTE_RESOURCE_LIMITS__WAVES_PER_SH__SHIFT 0x0
#define COMPUTE_RESOURCE_LIMITS__TG_PER_CU_MASK 0xf000
#define COMPUTE_RESOURCE_LIMITS__TG_PER_CU__SHIFT 0xc
#define COMPUTE_RESOURCE_LIMITS__LOCK_THRESHOLD_MASK 0x3f0000
#define COMPUTE_RESOURCE_LIMITS__LOCK_THRESHOLD__SHIFT 0x10
#define COMPUTE_RESOURCE_LIMITS__SIMD_DEST_CNTL_MASK 0x400000
#define COMPUTE_RESOURCE_LIMITS__SIMD_DEST_CNTL__SHIFT 0x16
#define COMPUTE_RESOURCE_LIMITS__FORCE_SIMD_DIST_MASK 0x800000
#define COMPUTE_RESOURCE_LIMITS__FORCE_SIMD_DIST__SHIFT 0x17
#define COMPUTE_RESOURCE_LIMITS__CU_GROUP_COUNT_MASK 0x7000000
#define COMPUTE_RESOURCE_LIMITS__CU_GROUP_COUNT__SHIFT 0x18
#define COMPUTE_STATIC_THREAD_MGMT_SE0__SH0_CU_EN_MASK 0xffff
#define COMPUTE_STATIC_THREAD_MGMT_SE0__SH0_CU_EN__SHIFT 0x0
#define COMPUTE_STATIC_THREAD_MGMT_SE0__SH1_CU_EN_MASK 0xffff0000
#define COMPUTE_STATIC_THREAD_MGMT_SE0__SH1_CU_EN__SHIFT 0x10
#define COMPUTE_STATIC_THREAD_MGMT_SE1__SH0_CU_EN_MASK 0xffff
#define COMPUTE_STATIC_THREAD_MGMT_SE1__SH0_CU_EN__SHIFT 0x0
#define COMPUTE_STATIC_THREAD_MGMT_SE1__SH1_CU_EN_MASK 0xffff0000
#define COMPUTE_STATIC_THREAD_MGMT_SE1__SH1_CU_EN__SHIFT 0x10
#define COMPUTE_TMPRING_SIZE__WAVES_MASK 0xfff
#define COMPUTE_TMPRING_SIZE__WAVES__SHIFT 0x0
#define COMPUTE_TMPRING_SIZE__WAVESIZE_MASK 0x1fff000
#define COMPUTE_TMPRING_SIZE__WAVESIZE__SHIFT 0xc
#define COMPUTE_STATIC_THREAD_MGMT_SE2__SH0_CU_EN_MASK 0xffff
#define COMPUTE_STATIC_THREAD_MGMT_SE2__SH0_CU_EN__SHIFT 0x0
#define COMPUTE_STATIC_THREAD_MGMT_SE2__SH1_CU_EN_MASK 0xffff0000
#define COMPUTE_STATIC_THREAD_MGMT_SE2__SH1_CU_EN__SHIFT 0x10
#define COMPUTE_STATIC_THREAD_MGMT_SE3__SH0_CU_EN_MASK 0xffff
#define COMPUTE_STATIC_THREAD_MGMT_SE3__SH0_CU_EN__SHIFT 0x0
#define COMPUTE_STATIC_THREAD_MGMT_SE3__SH1_CU_EN_MASK 0xffff0000
#define COMPUTE_STATIC_THREAD_MGMT_SE3__SH1_CU_EN__SHIFT 0x10
#define COMPUTE_RESTART_X__RESTART_MASK 0xffffffff
#define COMPUTE_RESTART_X__RESTART__SHIFT 0x0
#define COMPUTE_RESTART_Y__RESTART_MASK 0xffffffff
#define COMPUTE_RESTART_Y__RESTART__SHIFT 0x0
#define COMPUTE_RESTART_Z__RESTART_MASK 0xffffffff
#define COMPUTE_RESTART_Z__RESTART__SHIFT 0x0
#define COMPUTE_THREAD_TRACE_ENABLE__THREAD_TRACE_ENABLE_MASK 0x1
#define COMPUTE_THREAD_TRACE_ENABLE__THREAD_TRACE_ENABLE__SHIFT 0x0
#define COMPUTE_MISC_RESERVED__SEND_SEID_MASK 0x3
#define COMPUTE_MISC_RESERVED__SEND_SEID__SHIFT 0x0
#define COMPUTE_MISC_RESERVED__RESERVED2_MASK 0x4
#define COMPUTE_MISC_RESERVED__RESERVED2__SHIFT 0x2
#define COMPUTE_MISC_RESERVED__RESERVED3_MASK 0x8
#define COMPUTE_MISC_RESERVED__RESERVED3__SHIFT 0x3
#define COMPUTE_MISC_RESERVED__RESERVED4_MASK 0x10
#define COMPUTE_MISC_RESERVED__RESERVED4__SHIFT 0x4
#define COMPUTE_MISC_RESERVED__WAVE_ID_BASE_MASK 0x1ffe0
#define COMPUTE_MISC_RESERVED__WAVE_ID_BASE__SHIFT 0x5
#define COMPUTE_DISPATCH_ID__DISPATCH_ID_MASK 0xffffffff
#define COMPUTE_DISPATCH_ID__DISPATCH_ID__SHIFT 0x0
#define COMPUTE_THREADGROUP_ID__THREADGROUP_ID_MASK 0xffffffff
#define COMPUTE_THREADGROUP_ID__THREADGROUP_ID__SHIFT 0x0
#define COMPUTE_RELAUNCH__PAYLOAD_MASK 0x3fffffff
#define COMPUTE_RELAUNCH__PAYLOAD__SHIFT 0x0
#define COMPUTE_RELAUNCH__IS_EVENT_MASK 0x40000000
#define COMPUTE_RELAUNCH__IS_EVENT__SHIFT 0x1e
#define COMPUTE_RELAUNCH__IS_STATE_MASK 0x80000000
#define COMPUTE_RELAUNCH__IS_STATE__SHIFT 0x1f
#define COMPUTE_WAVE_RESTORE_ADDR_LO__ADDR_MASK 0xffffffff
#define COMPUTE_WAVE_RESTORE_ADDR_LO__ADDR__SHIFT 0x0
#define COMPUTE_WAVE_RESTORE_ADDR_HI__ADDR_MASK 0xffff
#define COMPUTE_WAVE_RESTORE_ADDR_HI__ADDR__SHIFT 0x0
#define COMPUTE_WAVE_RESTORE_CONTROL__ATC_MASK 0x1
#define COMPUTE_WAVE_RESTORE_CONTROL__ATC__SHIFT 0x0
#define COMPUTE_WAVE_RESTORE_CONTROL__MTYPE_MASK 0x6
#define COMPUTE_WAVE_RESTORE_CONTROL__MTYPE__SHIFT 0x1
#define COMPUTE_USER_DATA_0__DATA_MASK 0xffffffff
#define COMPUTE_USER_DATA_0__DATA__SHIFT 0x0
#define COMPUTE_USER_DATA_1__DATA_MASK 0xffffffff
#define COMPUTE_USER_DATA_1__DATA__SHIFT 0x0
#define COMPUTE_USER_DATA_2__DATA_MASK 0xffffffff
#define COMPUTE_USER_DATA_2__DATA__SHIFT 0x0
#define COMPUTE_USER_DATA_3__DATA_MASK 0xffffffff
#define COMPUTE_USER_DATA_3__DATA__SHIFT 0x0
#define COMPUTE_USER_DATA_4__DATA_MASK 0xffffffff
#define COMPUTE_USER_DATA_4__DATA__SHIFT 0x0
#define COMPUTE_USER_DATA_5__DATA_MASK 0xffffffff
#define COMPUTE_USER_DATA_5__DATA__SHIFT 0x0
#define COMPUTE_USER_DATA_6__DATA_MASK 0xffffffff
#define COMPUTE_USER_DATA_6__DATA__SHIFT 0x0
#define COMPUTE_USER_DATA_7__DATA_MASK 0xffffffff
#define COMPUTE_USER_DATA_7__DATA__SHIFT 0x0
#define COMPUTE_USER_DATA_8__DATA_MASK 0xffffffff
#define COMPUTE_USER_DATA_8__DATA__SHIFT 0x0
#define COMPUTE_USER_DATA_9__DATA_MASK 0xffffffff
#define COMPUTE_USER_DATA_9__DATA__SHIFT 0x0
#define COMPUTE_USER_DATA_10__DATA_MASK 0xffffffff
#define COMPUTE_USER_DATA_10__DATA__SHIFT 0x0
#define COMPUTE_USER_DATA_11__DATA_MASK 0xffffffff
#define COMPUTE_USER_DATA_11__DATA__SHIFT 0x0
#define COMPUTE_USER_DATA_12__DATA_MASK 0xffffffff
#define COMPUTE_USER_DATA_12__DATA__SHIFT 0x0
#define COMPUTE_USER_DATA_13__DATA_MASK 0xffffffff
#define COMPUTE_USER_DATA_13__DATA__SHIFT 0x0
#define COMPUTE_USER_DATA_14__DATA_MASK 0xffffffff
#define COMPUTE_USER_DATA_14__DATA__SHIFT 0x0
#define COMPUTE_USER_DATA_15__DATA_MASK 0xffffffff
#define COMPUTE_USER_DATA_15__DATA__SHIFT 0x0
#define COMPUTE_NOWHERE__DATA_MASK 0xffffffff
#define COMPUTE_NOWHERE__DATA__SHIFT 0x0
#define CSPRIV_CONNECT__DOORBELL_OFFSET_MASK 0x1fffff
#define CSPRIV_CONNECT__DOORBELL_OFFSET__SHIFT 0x0
#define CSPRIV_CONNECT__QUEUE_ID_MASK 0xe00000
#define CSPRIV_CONNECT__QUEUE_ID__SHIFT 0x15
#define CSPRIV_CONNECT__VMID_MASK 0x3c000000
#define CSPRIV_CONNECT__VMID__SHIFT 0x1a
#define CSPRIV_CONNECT__UNORD_DISP_MASK 0x80000000
#define CSPRIV_CONNECT__UNORD_DISP__SHIFT 0x1f
#define CSPRIV_THREAD_TRACE_TG0__TGID_X_MASK 0xffffffff
#define CSPRIV_THREAD_TRACE_TG0__TGID_X__SHIFT 0x0
#define CSPRIV_THREAD_TRACE_TG1__TGID_Y_MASK 0xffffffff
#define CSPRIV_THREAD_TRACE_TG1__TGID_Y__SHIFT 0x0
#define CSPRIV_THREAD_TRACE_TG2__TGID_Z_MASK 0xffffffff
#define CSPRIV_THREAD_TRACE_TG2__TGID_Z__SHIFT 0x0
#define CSPRIV_THREAD_TRACE_TG3__WAVE_ID_BASE_MASK 0xfff
#define CSPRIV_THREAD_TRACE_TG3__WAVE_ID_BASE__SHIFT 0x0
#define CSPRIV_THREAD_TRACE_TG3__THREADS_IN_GROUP_MASK 0xfff000
#define CSPRIV_THREAD_TRACE_TG3__THREADS_IN_GROUP__SHIFT 0xc
#define CSPRIV_THREAD_TRACE_TG3__PARTIAL_X_FLAG_MASK 0x1000000
#define CSPRIV_THREAD_TRACE_TG3__PARTIAL_X_FLAG__SHIFT 0x18
#define CSPRIV_THREAD_TRACE_TG3__PARTIAL_Y_FLAG_MASK 0x2000000
#define CSPRIV_THREAD_TRACE_TG3__PARTIAL_Y_FLAG__SHIFT 0x19
#define CSPRIV_THREAD_TRACE_TG3__PARTIAL_Z_FLAG_MASK 0x4000000
#define CSPRIV_THREAD_TRACE_TG3__PARTIAL_Z_FLAG__SHIFT 0x1a
#define CSPRIV_THREAD_TRACE_TG3__LAST_TG_MASK 0x8000000
#define CSPRIV_THREAD_TRACE_TG3__LAST_TG__SHIFT 0x1b
#define CSPRIV_THREAD_TRACE_TG3__FIRST_TG_MASK 0x10000000
#define CSPRIV_THREAD_TRACE_TG3__FIRST_TG__SHIFT 0x1c
#define CSPRIV_THREAD_TRACE_EVENT__EVENT_ID_MASK 0x1f
#define CSPRIV_THREAD_TRACE_EVENT__EVENT_ID__SHIFT 0x0
#define RLC_CNTL__RLC_ENABLE_F32_MASK 0x1
#define RLC_CNTL__RLC_ENABLE_F32__SHIFT 0x0
#define RLC_CNTL__FORCE_RETRY_MASK 0x2
#define RLC_CNTL__FORCE_RETRY__SHIFT 0x1
#define RLC_CNTL__READ_CACHE_DISABLE_MASK 0x4
#define RLC_CNTL__READ_CACHE_DISABLE__SHIFT 0x2
#define RLC_CNTL__RLC_STEP_F32_MASK 0x8
#define RLC_CNTL__RLC_STEP_F32__SHIFT 0x3
#define RLC_CNTL__SOFT_RESET_DEBUG_MODE_MASK 0x10
#define RLC_CNTL__SOFT_RESET_DEBUG_MODE__SHIFT 0x4
#define RLC_CNTL__RESERVED_MASK 0xffffff00
#define RLC_CNTL__RESERVED__SHIFT 0x8
#define RLC_DEBUG_SELECT__SELECT_MASK 0xff
#define RLC_DEBUG_SELECT__SELECT__SHIFT 0x0
#define RLC_DEBUG_SELECT__RESERVED_MASK 0xffffff00
#define RLC_DEBUG_SELECT__RESERVED__SHIFT 0x8
#define RLC_DEBUG__DATA_MASK 0xffffffff
#define RLC_DEBUG__DATA__SHIFT 0x0
#define RLC_MC_CNTL__WRREQ_SWAP_MASK 0x3
#define RLC_MC_CNTL__WRREQ_SWAP__SHIFT 0x0
#define RLC_MC_CNTL__WRREQ_TRAN_MASK 0x4
#define RLC_MC_CNTL__WRREQ_TRAN__SHIFT 0x2
#define RLC_MC_CNTL__WRREQ_PRIV_MASK 0x8
#define RLC_MC_CNTL__WRREQ_PRIV__SHIFT 0x3
#define RLC_MC_CNTL__WRNFO_STALL_MASK 0x10
#define RLC_MC_CNTL__WRNFO_STALL__SHIFT 0x4
#define RLC_MC_CNTL__WRNFO_URG_MASK 0x1e0
#define RLC_MC_CNTL__WRNFO_URG__SHIFT 0x5
#define RLC_MC_CNTL__WRREQ_DW_IMASK_MASK 0x1e00
#define RLC_MC_CNTL__WRREQ_DW_IMASK__SHIFT 0x9
#define RLC_MC_CNTL__RESERVED_B_MASK 0xfe000
#define RLC_MC_CNTL__RESERVED_B__SHIFT 0xd
#define RLC_MC_CNTL__RDNFO_URG_MASK 0xf00000
#define RLC_MC_CNTL__RDNFO_URG__SHIFT 0x14
#define RLC_MC_CNTL__RDREQ_SWAP_MASK 0x3000000
#define RLC_MC_CNTL__RDREQ_SWAP__SHIFT 0x18
#define RLC_MC_CNTL__RDREQ_TRAN_MASK 0x4000000
#define RLC_MC_CNTL__RDREQ_TRAN__SHIFT 0x1a
#define RLC_MC_CNTL__RDREQ_PRIV_MASK 0x8000000
#define RLC_MC_CNTL__RDREQ_PRIV__SHIFT 0x1b
#define RLC_MC_CNTL__RDNFO_STALL_MASK 0x10000000
#define RLC_MC_CNTL__RDNFO_STALL__SHIFT 0x1c
#define RLC_MC_CNTL__RESERVED_MASK 0xe0000000
#define RLC_MC_CNTL__RESERVED__SHIFT 0x1d
#define RLC_STAT__RLC_BUSY_MASK 0x1
#define RLC_STAT__RLC_BUSY__SHIFT 0x0
#define RLC_STAT__RLC_GPM_BUSY_MASK 0x2
#define RLC_STAT__RLC_GPM_BUSY__SHIFT 0x1
#define RLC_STAT__RLC_SPM_BUSY_MASK 0x4
#define RLC_STAT__RLC_SPM_BUSY__SHIFT 0x2
#define RLC_STAT__RESERVED_MASK 0xfffffff8
#define RLC_STAT__RESERVED__SHIFT 0x3
#define RLC_SAFE_MODE__CMD_MASK 0x1
#define RLC_SAFE_MODE__CMD__SHIFT 0x0
#define RLC_SAFE_MODE__MESSAGE_MASK 0x1e
#define RLC_SAFE_MODE__MESSAGE__SHIFT 0x1
#define RLC_SAFE_MODE__RESERVED1_MASK 0xe0
#define RLC_SAFE_MODE__RESERVED1__SHIFT 0x5
#define RLC_SAFE_MODE__RESPONSE_MASK 0xf00
#define RLC_SAFE_MODE__RESPONSE__SHIFT 0x8
#define RLC_SAFE_MODE__RESERVED_MASK 0xfffff000
#define RLC_SAFE_MODE__RESERVED__SHIFT 0xc
#define RLC_SOFT_RESET_GPU__SOFT_RESET_GPU_MASK 0x1
#define RLC_SOFT_RESET_GPU__SOFT_RESET_GPU__SHIFT 0x0
#define RLC_SOFT_RESET_GPU__RESERVED_MASK 0xfffffffe
#define RLC_SOFT_RESET_GPU__RESERVED__SHIFT 0x1
#define RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK 0x1
#define RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN__SHIFT 0x0
#define RLC_MEM_SLP_CNTL__RLC_MEM_DS_EN_MASK 0x2
#define RLC_MEM_SLP_CNTL__RLC_MEM_DS_EN__SHIFT 0x1
#define RLC_MEM_SLP_CNTL__RESERVED_MASK 0x7c
#define RLC_MEM_SLP_CNTL__RESERVED__SHIFT 0x2
#define RLC_MEM_SLP_CNTL__RLC_LS_DS_BUSY_OVERRIDE_MASK 0x80
#define RLC_MEM_SLP_CNTL__RLC_LS_DS_BUSY_OVERRIDE__SHIFT 0x7
#define RLC_MEM_SLP_CNTL__RLC_MEM_LS_ON_DELAY_MASK 0xff00
#define RLC_MEM_SLP_CNTL__RLC_MEM_LS_ON_DELAY__SHIFT 0x8
#define RLC_MEM_SLP_CNTL__RLC_MEM_LS_OFF_DELAY_MASK 0xff0000
#define RLC_MEM_SLP_CNTL__RLC_MEM_LS_OFF_DELAY__SHIFT 0x10
#define RLC_MEM_SLP_CNTL__RESERVED1_MASK 0xff000000
#define RLC_MEM_SLP_CNTL__RESERVED1__SHIFT 0x18
#define SMU_RLC_RESPONSE__RESP_MASK 0xffffffff
#define SMU_RLC_RESPONSE__RESP__SHIFT 0x0
#define RLC_RLCV_SAFE_MODE__CMD_MASK 0x1
#define RLC_RLCV_SAFE_MODE__CMD__SHIFT 0x0
#define RLC_RLCV_SAFE_MODE__MESSAGE_MASK 0x1e
#define RLC_RLCV_SAFE_MODE__MESSAGE__SHIFT 0x1
#define RLC_RLCV_SAFE_MODE__RESERVED1_MASK 0xe0
#define RLC_RLCV_SAFE_MODE__RESERVED1__SHIFT 0x5
#define RLC_RLCV_SAFE_MODE__RESPONSE_MASK 0xf00
#define RLC_RLCV_SAFE_MODE__RESPONSE__SHIFT 0x8
#define RLC_RLCV_SAFE_MODE__RESERVED_MASK 0xfffff000
#define RLC_RLCV_SAFE_MODE__RESERVED__SHIFT 0xc
#define RLC_SMU_SAFE_MODE__CMD_MASK 0x1
#define RLC_SMU_SAFE_MODE__CMD__SHIFT 0x0
#define RLC_SMU_SAFE_MODE__MESSAGE_MASK 0x1e
#define RLC_SMU_SAFE_MODE__MESSAGE__SHIFT 0x1
#define RLC_SMU_SAFE_MODE__RESERVED1_MASK 0xe0
#define RLC_SMU_SAFE_MODE__RESERVED1__SHIFT 0x5
#define RLC_SMU_SAFE_MODE__RESPONSE_MASK 0xf00
#define RLC_SMU_SAFE_MODE__RESPONSE__SHIFT 0x8
#define RLC_SMU_SAFE_MODE__RESERVED_MASK 0xfffff000
#define RLC_SMU_SAFE_MODE__RESERVED__SHIFT 0xc
#define RLC_RLCV_COMMAND__CMD_MASK 0xf
#define RLC_RLCV_COMMAND__CMD__SHIFT 0x0
#define RLC_RLCV_COMMAND__RESERVED_MASK 0xfffffff0
#define RLC_RLCV_COMMAND__RESERVED__SHIFT 0x4
#define RLC_PERFMON_CLK_CNTL__PERFMON_CLOCK_STATE_MASK 0x1
#define RLC_PERFMON_CLK_CNTL__PERFMON_CLOCK_STATE__SHIFT 0x0
#define RLC_PERFMON_CNTL__PERFMON_STATE_MASK 0x7
#define RLC_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0
#define RLC_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE_MASK 0x400
#define RLC_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE__SHIFT 0xa
#define RLC_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT_MASK 0xff
#define RLC_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT__SHIFT 0x0
#define RLC_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT_MASK 0xff
#define RLC_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT__SHIFT 0x0
#define RLC_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff
#define RLC_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
#define RLC_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff
#define RLC_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
#define RLC_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff
#define RLC_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
#define RLC_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff
#define RLC_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
#define CGTT_RLC_CLK_CTRL__ON_DELAY_MASK 0xf
#define CGTT_RLC_CLK_CTRL__ON_DELAY__SHIFT 0x0
#define CGTT_RLC_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0
#define CGTT_RLC_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
#define CGTT_RLC_CLK_CTRL__SOFT_OVERRIDE_DYN_MASK 0x40000000
#define CGTT_RLC_CLK_CTRL__SOFT_OVERRIDE_DYN__SHIFT 0x1e
#define CGTT_RLC_CLK_CTRL__SOFT_OVERRIDE_REG_MASK 0x80000000
#define CGTT_RLC_CLK_CTRL__SOFT_OVERRIDE_REG__SHIFT 0x1f
#define RLC_LB_CNTL__LOAD_BALANCE_ENABLE_MASK 0x1
#define RLC_LB_CNTL__LOAD_BALANCE_ENABLE__SHIFT 0x0
#define RLC_LB_CNTL__LB_CNT_CP_BUSY_MASK 0x2
#define RLC_LB_CNTL__LB_CNT_CP_BUSY__SHIFT 0x1
#define RLC_LB_CNTL__LB_CNT_SPIM_ACTIVE_MASK 0x4
#define RLC_LB_CNTL__LB_CNT_SPIM_ACTIVE__SHIFT 0x2
#define RLC_LB_CNTL__LB_CNT_REG_INC_MASK 0x8
#define RLC_LB_CNTL__LB_CNT_REG_INC__SHIFT 0x3
#define RLC_LB_CNTL__CU_MASK_USED_OFF_HYST_MASK 0xff0
#define RLC_LB_CNTL__CU_MASK_USED_OFF_HYST__SHIFT 0x4
#define RLC_LB_CNTL__RESERVED_MASK 0xfffff000
#define RLC_LB_CNTL__RESERVED__SHIFT 0xc
#define RLC_LB_CNTR_MAX__LB_CNTR_MAX_MASK 0xffffffff
#define RLC_LB_CNTR_MAX__LB_CNTR_MAX__SHIFT 0x0
#define RLC_LB_CNTR_INIT__LB_CNTR_INIT_MASK 0xffffffff
#define RLC_LB_CNTR_INIT__LB_CNTR_INIT__SHIFT 0x0
#define RLC_LOAD_BALANCE_CNTR__RLC_LOAD_BALANCE_CNTR_MASK 0xffffffff
#define RLC_LOAD_BALANCE_CNTR__RLC_LOAD_BALANCE_CNTR__SHIFT 0x0
#define RLC_SAVE_AND_RESTORE_BASE__BASE_MASK 0xffffffff
#define RLC_SAVE_AND_RESTORE_BASE__BASE__SHIFT 0x0
#define RLC_JUMP_TABLE_RESTORE__ADDR_MASK 0xffffffff
#define RLC_JUMP_TABLE_RESTORE__ADDR__SHIFT 0x0
#define RLC_DRIVER_CPDMA_STATUS__DRIVER_REQUEST_MASK 0x1
#define RLC_DRIVER_CPDMA_STATUS__DRIVER_REQUEST__SHIFT 0x0
#define RLC_DRIVER_CPDMA_STATUS__RESERVED1_MASK 0xe
#define RLC_DRIVER_CPDMA_STATUS__RESERVED1__SHIFT 0x1
#define RLC_DRIVER_CPDMA_STATUS__DRIVER_ACK_MASK 0x10
#define RLC_DRIVER_CPDMA_STATUS__DRIVER_ACK__SHIFT 0x4
#define RLC_DRIVER_CPDMA_STATUS__RESERVED_MASK 0xffffffe0
#define RLC_DRIVER_CPDMA_STATUS__RESERVED__SHIFT 0x5
#define RLC_PG_DELAY_2__SERDES_TIMEOUT_VALUE_MASK 0xff
#define RLC_PG_DELAY_2__SERDES_TIMEOUT_VALUE__SHIFT 0x0
#define RLC_PG_DELAY_2__SERDES_CMD_DELAY_MASK 0xff00
#define RLC_PG_DELAY_2__SERDES_CMD_DELAY__SHIFT 0x8
#define RLC_PG_DELAY_2__PERCU_TIMEOUT_VALUE_MASK 0xffff0000
#define RLC_PG_DELAY_2__PERCU_TIMEOUT_VALUE__SHIFT 0x10
#define RLC_GPM_DEBUG_SELECT__SELECT_MASK 0xff
#define RLC_GPM_DEBUG_SELECT__SELECT__SHIFT 0x0
#define RLC_GPM_DEBUG_SELECT__F32_DEBUG_SELECT_MASK 0x300
#define RLC_GPM_DEBUG_SELECT__F32_DEBUG_SELECT__SHIFT 0x8
#define RLC_GPM_DEBUG_SELECT__RESERVED_MASK 0xfffffc00
#define RLC_GPM_DEBUG_SELECT__RESERVED__SHIFT 0xa
#define RLC_GPM_DEBUG__DATA_MASK 0xffffffff
#define RLC_GPM_DEBUG__DATA__SHIFT 0x0
#define RLC_HYP_GPM_UCODE_ADDR__UCODE_ADDR_MASK 0xfff
#define RLC_HYP_GPM_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0
#define RLC_HYP_GPM_UCODE_ADDR__RESERVED_MASK 0xfffff000
#define RLC_HYP_GPM_UCODE_ADDR__RESERVED__SHIFT 0xc
#define RLC_GPM_UCODE_ADDR__UCODE_ADDR_MASK 0xfff
#define RLC_GPM_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0
#define RLC_GPM_UCODE_ADDR__RESERVED_MASK 0xfffff000
#define RLC_GPM_UCODE_ADDR__RESERVED__SHIFT 0xc
#define RLC_HYP_GPM_UCODE_DATA__UCODE_DATA_MASK 0xffffffff
#define RLC_HYP_GPM_UCODE_DATA__UCODE_DATA__SHIFT 0x0
#define RLC_GPM_UCODE_DATA__UCODE_DATA_MASK 0xffffffff
#define RLC_GPM_UCODE_DATA__UCODE_DATA__SHIFT 0x0
#define GPU_BIST_CONTROL__STOP_ON_FAIL_HW_MASK 0x1
#define GPU_BIST_CONTROL__STOP_ON_FAIL_HW__SHIFT 0x0
#define GPU_BIST_CONTROL__STOP_ON_FAIL_CU_HARV_MASK 0x2
#define GPU_BIST_CONTROL__STOP_ON_FAIL_CU_HARV__SHIFT 0x1
#define GPU_BIST_CONTROL__CU_HARV_LOOP_COUNT_MASK 0x3c
#define GPU_BIST_CONTROL__CU_HARV_LOOP_COUNT__SHIFT 0x2
#define GPU_BIST_CONTROL__RESERVED_MASK 0xffff80
#define GPU_BIST_CONTROL__RESERVED__SHIFT 0x7
#define GPU_BIST_CONTROL__GLOBAL_LOOP_COUNT_MASK 0xff000000
#define GPU_BIST_CONTROL__GLOBAL_LOOP_COUNT__SHIFT 0x18
#define RLC_ROM_CNTL__USE_ROM_MASK 0x1
#define RLC_ROM_CNTL__USE_ROM__SHIFT 0x0
#define RLC_ROM_CNTL__SLP_MODE_EN_MASK 0x2
#define RLC_ROM_CNTL__SLP_MODE_EN__SHIFT 0x1
#define RLC_ROM_CNTL__EFUSE_DISTRIB_EN_MASK 0x4
#define RLC_ROM_CNTL__EFUSE_DISTRIB_EN__SHIFT 0x2
#define RLC_ROM_CNTL__HELLOWORLD_EN_MASK 0x8
#define RLC_ROM_CNTL__HELLOWORLD_EN__SHIFT 0x3
#define RLC_ROM_CNTL__CU_HARVEST_EN_MASK 0x10
#define RLC_ROM_CNTL__CU_HARVEST_EN__SHIFT 0x4
#define RLC_ROM_CNTL__RESERVED_MASK 0xffffffe0
#define RLC_ROM_CNTL__RESERVED__SHIFT 0x5
#define RLC_GPU_CLOCK_COUNT_LSB__GPU_CLOCKS_LSB_MASK 0xffffffff
#define RLC_GPU_CLOCK_COUNT_LSB__GPU_CLOCKS_LSB__SHIFT 0x0
#define RLC_GPU_CLOCK_COUNT_MSB__GPU_CLOCKS_MSB_MASK 0xffffffff
#define RLC_GPU_CLOCK_COUNT_MSB__GPU_CLOCKS_MSB__SHIFT 0x0
#define RLC_CAPTURE_GPU_CLOCK_COUNT__CAPTURE_MASK 0x1
#define RLC_CAPTURE_GPU_CLOCK_COUNT__CAPTURE__SHIFT 0x0
#define RLC_CAPTURE_GPU_CLOCK_COUNT__RESERVED_MASK 0xfffffffe
#define RLC_CAPTURE_GPU_CLOCK_COUNT__RESERVED__SHIFT 0x1
#define RLC_UCODE_CNTL__RLC_UCODE_FLAGS_MASK 0xffffffff
#define RLC_UCODE_CNTL__RLC_UCODE_FLAGS__SHIFT 0x0
#define RLC_GPM_STAT__RLC_BUSY_MASK 0x1
#define RLC_GPM_STAT__RLC_BUSY__SHIFT 0x0
#define RLC_GPM_STAT__GFX_POWER_STATUS_MASK 0x2
#define RLC_GPM_STAT__GFX_POWER_STATUS__SHIFT 0x1
#define RLC_GPM_STAT__GFX_CLOCK_STATUS_MASK 0x4
#define RLC_GPM_STAT__GFX_CLOCK_STATUS__SHIFT 0x2
#define RLC_GPM_STAT__GFX_LS_STATUS_MASK 0x8
#define RLC_GPM_STAT__GFX_LS_STATUS__SHIFT 0x3
#define RLC_GPM_STAT__GFX_PIPELINE_POWER_STATUS_MASK 0x10
#define RLC_GPM_STAT__GFX_PIPELINE_POWER_STATUS__SHIFT 0x4
#define RLC_GPM_STAT__CNTX_IDLE_BEING_PROCESSED_MASK 0x20
#define RLC_GPM_STAT__CNTX_IDLE_BEING_PROCESSED__SHIFT 0x5
#define RLC_GPM_STAT__CNTX_BUSY_BEING_PROCESSED_MASK 0x40
#define RLC_GPM_STAT__CNTX_BUSY_BEING_PROCESSED__SHIFT 0x6
#define RLC_GPM_STAT__GFX_IDLE_BEING_PROCESSED_MASK 0x80
#define RLC_GPM_STAT__GFX_IDLE_BEING_PROCESSED__SHIFT 0x7
#define RLC_GPM_STAT__CMP_BUSY_BEING_PROCESSED_MASK 0x100
#define RLC_GPM_STAT__CMP_BUSY_BEING_PROCESSED__SHIFT 0x8
#define RLC_GPM_STAT__SAVING_REGISTERS_MASK 0x200
#define RLC_GPM_STAT__SAVING_REGISTERS__SHIFT 0x9
#define RLC_GPM_STAT__RESTORING_REGISTERS_MASK 0x400
#define RLC_GPM_STAT__RESTORING_REGISTERS__SHIFT 0xa
#define RLC_GPM_STAT__GFX3D_BLOCKS_CHANGING_POWER_STATE_MASK 0x800
#define RLC_GPM_STAT__GFX3D_BLOCKS_CHANGING_POWER_STATE__SHIFT 0xb
#define RLC_GPM_STAT__CMP_BLOCKS_CHANGING_POWER_STATE_MASK 0x1000
#define RLC_GPM_STAT__CMP_BLOCKS_CHANGING_POWER_STATE__SHIFT 0xc
#define RLC_GPM_STAT__STATIC_CU_POWERING_UP_MASK 0x2000
#define RLC_GPM_STAT__STATIC_CU_POWERING_UP__SHIFT 0xd
#define RLC_GPM_STAT__STATIC_CU_POWERING_DOWN_MASK 0x4000
#define RLC_GPM_STAT__STATIC_CU_POWERING_DOWN__SHIFT 0xe
#define RLC_GPM_STAT__DYN_CU_POWERING_UP_MASK 0x8000
#define RLC_GPM_STAT__DYN_CU_POWERING_UP__SHIFT 0xf
#define RLC_GPM_STAT__DYN_CU_POWERING_DOWN_MASK 0x10000
#define RLC_GPM_STAT__DYN_CU_POWERING_DOWN__SHIFT 0x10
#define RLC_GPM_STAT__ABORTED_PD_SEQUENCE_MASK 0x20000
#define RLC_GPM_STAT__ABORTED_PD_SEQUENCE__SHIFT 0x11
#define RLC_GPM_STAT__PG_ERROR_STATUS_MASK 0xff000000
#define RLC_GPM_STAT__PG_ERROR_STATUS__SHIFT 0x18
#define RLC_GPU_CLOCK_32_RES_SEL__RES_SEL_MASK 0x3f
#define RLC_GPU_CLOCK_32_RES_SEL__RES_SEL__SHIFT 0x0
#define RLC_GPU_CLOCK_32_RES_SEL__RESERVED_MASK 0xffffffc0
#define RLC_GPU_CLOCK_32_RES_SEL__RESERVED__SHIFT 0x6
#define RLC_GPU_CLOCK_32__GPU_CLOCK_32_MASK 0xffffffff
#define RLC_GPU_CLOCK_32__GPU_CLOCK_32__SHIFT 0x0
#define RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK 0x1
#define RLC_PG_CNTL__GFX_POWER_GATING_ENABLE__SHIFT 0x0
#define RLC_PG_CNTL__GFX_POWER_GATING_SRC_MASK 0x2
#define RLC_PG_CNTL__GFX_POWER_GATING_SRC__SHIFT 0x1
#define RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK 0x4
#define RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE__SHIFT 0x2
#define RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE_MASK 0x8
#define RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE__SHIFT 0x3
#define RLC_PG_CNTL__GFX_PIPELINE_PG_ENABLE_MASK 0x10
#define RLC_PG_CNTL__GFX_PIPELINE_PG_ENABLE__SHIFT 0x4
#define RLC_PG_CNTL__RESERVED_MASK 0x3fe0
#define RLC_PG_CNTL__RESERVED__SHIFT 0x5
#define RLC_PG_CNTL__PG_OVERRIDE_MASK 0x4000
#define RLC_PG_CNTL__PG_OVERRIDE__SHIFT 0xe
#define RLC_PG_CNTL__CP_PG_DISABLE_MASK 0x8000
#define RLC_PG_CNTL__CP_PG_DISABLE__SHIFT 0xf
#define RLC_PG_CNTL__CHUB_HANDSHAKE_ENABLE_MASK 0x10000
#define RLC_PG_CNTL__CHUB_HANDSHAKE_ENABLE__SHIFT 0x10
#define RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PU_ENABLE_MASK 0x20000
#define RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PU_ENABLE__SHIFT 0x11
#define RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PD_ENABLE_MASK 0x40000
#define RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PD_ENABLE__SHIFT 0x12
#define RLC_PG_CNTL__SMU_HANDSHAKE_ENABLE_MASK 0x80000
#define RLC_PG_CNTL__SMU_HANDSHAKE_ENABLE__SHIFT 0x13
#define RLC_PG_CNTL__QUICK_PG_ENABLE_MASK 0x100000
#define RLC_PG_CNTL__QUICK_PG_ENABLE__SHIFT 0x14
#define RLC_PG_CNTL__RESERVED1_MASK 0xe00000
#define RLC_PG_CNTL__RESERVED1__SHIFT 0x15
#define RLC_GPM_THREAD_PRIORITY__THREAD0_PRIORITY_MASK 0xff
#define RLC_GPM_THREAD_PRIORITY__THREAD0_PRIORITY__SHIFT 0x0
#define RLC_GPM_THREAD_PRIORITY__THREAD1_PRIORITY_MASK 0xff00
#define RLC_GPM_THREAD_PRIORITY__THREAD1_PRIORITY__SHIFT 0x8
#define RLC_GPM_THREAD_PRIORITY__THREAD2_PRIORITY_MASK 0xff0000
#define RLC_GPM_THREAD_PRIORITY__THREAD2_PRIORITY__SHIFT 0x10
#define RLC_GPM_THREAD_PRIORITY__THREAD3_PRIORITY_MASK 0xff000000
#define RLC_GPM_THREAD_PRIORITY__THREAD3_PRIORITY__SHIFT 0x18
#define RLC_GPM_THREAD_ENABLE__THREAD0_ENABLE_MASK 0x1
#define RLC_GPM_THREAD_ENABLE__THREAD0_ENABLE__SHIFT 0x0
#define RLC_GPM_THREAD_ENABLE__THREAD1_ENABLE_MASK 0x2
#define RLC_GPM_THREAD_ENABLE__THREAD1_ENABLE__SHIFT 0x1
#define RLC_GPM_THREAD_ENABLE__THREAD2_ENABLE_MASK 0x4
#define RLC_GPM_THREAD_ENABLE__THREAD2_ENABLE__SHIFT 0x2
#define RLC_GPM_THREAD_ENABLE__THREAD3_ENABLE_MASK 0x8
#define RLC_GPM_THREAD_ENABLE__THREAD3_ENABLE__SHIFT 0x3
#define RLC_GPM_THREAD_ENABLE__RESERVED_MASK 0xfffffff0
#define RLC_GPM_THREAD_ENABLE__RESERVED__SHIFT 0x4
#define RLC_GPM_VMID_THREAD0__RLC_VMID_MASK 0xf
#define RLC_GPM_VMID_THREAD0__RLC_VMID__SHIFT 0x0
#define RLC_GPM_VMID_THREAD0__RESERVED0_MASK 0xf0
#define RLC_GPM_VMID_THREAD0__RESERVED0__SHIFT 0x4
#define RLC_GPM_VMID_THREAD0__RLC_QUEUEID_MASK 0x700
#define RLC_GPM_VMID_THREAD0__RLC_QUEUEID__SHIFT 0x8
#define RLC_GPM_VMID_THREAD0__RESERVED1_MASK 0xfffff800
#define RLC_GPM_VMID_THREAD0__RESERVED1__SHIFT 0xb
#define RLC_GPM_VMID_THREAD1__RLC_VMID_MASK 0xf
#define RLC_GPM_VMID_THREAD1__RLC_VMID__SHIFT 0x0
#define RLC_GPM_VMID_THREAD1__RESERVED0_MASK 0xf0
#define RLC_GPM_VMID_THREAD1__RESERVED0__SHIFT 0x4
#define RLC_GPM_VMID_THREAD1__RLC_QUEUEID_MASK 0x700
#define RLC_GPM_VMID_THREAD1__RLC_QUEUEID__SHIFT 0x8
#define RLC_GPM_VMID_THREAD1__RESERVED1_MASK 0xfffff800
#define RLC_GPM_VMID_THREAD1__RESERVED1__SHIFT 0xb
#define RLC_CGTT_MGCG_OVERRIDE__OVERRIDE_MASK 0xffffffff
#define RLC_CGTT_MGCG_OVERRIDE__OVERRIDE__SHIFT 0x0
#define RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK 0x1
#define RLC_CGCG_CGLS_CTRL__CGCG_EN__SHIFT 0x0
#define RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK 0x2
#define RLC_CGCG_CGLS_CTRL__CGLS_EN__SHIFT 0x1
#define RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY_MASK 0xfc
#define RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT 0x2
#define RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD_MASK 0x7ffff00
#define RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT 0x8
#define RLC_CGCG_CGLS_CTRL__CGCG_CONTROLLER_MASK 0x8000000
#define RLC_CGCG_CGLS_CTRL__CGCG_CONTROLLER__SHIFT 0x1b
#define RLC_CGCG_CGLS_CTRL__CGCG_REG_CTRL_MASK 0x10000000
#define RLC_CGCG_CGLS_CTRL__CGCG_REG_CTRL__SHIFT 0x1c
#define RLC_CGCG_CGLS_CTRL__SLEEP_MODE_MASK 0x60000000
#define RLC_CGCG_CGLS_CTRL__SLEEP_MODE__SHIFT 0x1d
#define RLC_CGCG_CGLS_CTRL__SIM_SILICON_EN_MASK 0x80000000
#define RLC_CGCG_CGLS_CTRL__SIM_SILICON_EN__SHIFT 0x1f
#define RLC_CGCG_RAMP_CTRL__DOWN_DIV_START_UNIT_MASK 0xf
#define RLC_CGCG_RAMP_CTRL__DOWN_DIV_START_UNIT__SHIFT 0x0
#define RLC_CGCG_RAMP_CTRL__DOWN_DIV_STEP_UNIT_MASK 0xf0
#define RLC_CGCG_RAMP_CTRL__DOWN_DIV_STEP_UNIT__SHIFT 0x4
#define RLC_CGCG_RAMP_CTRL__UP_DIV_START_UNIT_MASK 0xf00
#define RLC_CGCG_RAMP_CTRL__UP_DIV_START_UNIT__SHIFT 0x8
#define RLC_CGCG_RAMP_CTRL__UP_DIV_STEP_UNIT_MASK 0xf000
#define RLC_CGCG_RAMP_CTRL__UP_DIV_STEP_UNIT__SHIFT 0xc
#define RLC_CGCG_RAMP_CTRL__STEP_DELAY_CNT_MASK 0xfff0000
#define RLC_CGCG_RAMP_CTRL__STEP_DELAY_CNT__SHIFT 0x10
#define RLC_CGCG_RAMP_CTRL__STEP_DELAY_UNIT_MASK 0xf0000000
#define RLC_CGCG_RAMP_CTRL__STEP_DELAY_UNIT__SHIFT 0x1c
#define RLC_DYN_PG_STATUS__PG_STATUS_CU_MASK_MASK 0xffffffff
#define RLC_DYN_PG_STATUS__PG_STATUS_CU_MASK__SHIFT 0x0
#define RLC_DYN_PG_REQUEST__PG_REQUEST_CU_MASK_MASK 0xffffffff
#define RLC_DYN_PG_REQUEST__PG_REQUEST_CU_MASK__SHIFT 0x0
#define RLC_PG_DELAY__POWER_UP_DELAY_MASK 0xff
#define RLC_PG_DELAY__POWER_UP_DELAY__SHIFT 0x0
#define RLC_PG_DELAY__POWER_DOWN_DELAY_MASK 0xff00
#define RLC_PG_DELAY__POWER_DOWN_DELAY__SHIFT 0x8
#define RLC_PG_DELAY__CMD_PROPAGATE_DELAY_MASK 0xff0000
#define RLC_PG_DELAY__CMD_PROPAGATE_DELAY__SHIFT 0x10
#define RLC_PG_DELAY__MEM_SLEEP_DELAY_MASK 0xff000000
#define RLC_PG_DELAY__MEM_SLEEP_DELAY__SHIFT 0x18
#define RLC_CU_STATUS__WORK_PENDING_MASK 0xffffffff
#define RLC_CU_STATUS__WORK_PENDING__SHIFT 0x0
#define RLC_LB_INIT_CU_MASK__INIT_CU_MASK_MASK 0xffffffff
#define RLC_LB_INIT_CU_MASK__INIT_CU_MASK__SHIFT 0x0
#define RLC_LB_ALWAYS_ACTIVE_CU_MASK__ALWAYS_ACTIVE_CU_MASK_MASK 0xffffffff
#define RLC_LB_ALWAYS_ACTIVE_CU_MASK__ALWAYS_ACTIVE_CU_MASK__SHIFT 0x0
#define RLC_LB_PARAMS__SKIP_L2_CHECK_MASK 0x1
#define RLC_LB_PARAMS__SKIP_L2_CHECK__SHIFT 0x0
#define RLC_LB_PARAMS__FIFO_SAMPLES_MASK 0xfe
#define RLC_LB_PARAMS__FIFO_SAMPLES__SHIFT 0x1
#define RLC_LB_PARAMS__PG_IDLE_SAMPLES_MASK 0xff00
#define RLC_LB_PARAMS__PG_IDLE_SAMPLES__SHIFT 0x8
#define RLC_LB_PARAMS__PG_IDLE_SAMPLE_INTERVAL_MASK 0xffff0000
#define RLC_LB_PARAMS__PG_IDLE_SAMPLE_INTERVAL__SHIFT 0x10
#define RLC_THREAD1_DELAY__CU_IDEL_DELAY_MASK 0xff
#define RLC_THREAD1_DELAY__CU_IDEL_DELAY__SHIFT 0x0
#define RLC_THREAD1_DELAY__LBPW_INNER_LOOP_DELAY_MASK 0xff00
#define RLC_THREAD1_DELAY__LBPW_INNER_LOOP_DELAY__SHIFT 0x8
#define RLC_THREAD1_DELAY__LBPW_OUTER_LOOP_DELAY_MASK 0xff0000
#define RLC_THREAD1_DELAY__LBPW_OUTER_LOOP_DELAY__SHIFT 0x10
#define RLC_THREAD1_DELAY__SPARE_MASK 0xff000000
#define RLC_THREAD1_DELAY__SPARE__SHIFT 0x18
#define RLC_PG_ALWAYS_ON_CU_MASK__AON_CU_MASK_MASK 0xffffffff
#define RLC_PG_ALWAYS_ON_CU_MASK__AON_CU_MASK__SHIFT 0x0
#define RLC_MAX_PG_CU__MAX_POWERED_UP_CU_MASK 0xff
#define RLC_MAX_PG_CU__MAX_POWERED_UP_CU__SHIFT 0x0
#define RLC_MAX_PG_CU__SPARE_MASK 0xffffff00
#define RLC_MAX_PG_CU__SPARE__SHIFT 0x8
#define RLC_AUTO_PG_CTRL__AUTO_PG_EN_MASK 0x1
#define RLC_AUTO_PG_CTRL__AUTO_PG_EN__SHIFT 0x0
#define RLC_AUTO_PG_CTRL__AUTO_GRBM_REG_SAVE_ON_IDLE_EN_MASK 0x2
#define RLC_AUTO_PG_CTRL__AUTO_GRBM_REG_SAVE_ON_IDLE_EN__SHIFT 0x1
#define RLC_AUTO_PG_CTRL__AUTO_WAKE_UP_EN_MASK 0x4
#define RLC_AUTO_PG_CTRL__AUTO_WAKE_UP_EN__SHIFT 0x2
#define RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD_MASK 0x7fff8
#define RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD__SHIFT 0x3
#define RLC_AUTO_PG_CTRL__PG_AFTER_GRBM_REG_SAVE_THRESHOLD_MASK 0xfff80000
#define RLC_AUTO_PG_CTRL__PG_AFTER_GRBM_REG_SAVE_THRESHOLD__SHIFT 0x13
#define RLC_SMU_GRBM_REG_SAVE_CTRL__START_GRBM_REG_SAVE_MASK 0x1
#define RLC_SMU_GRBM_REG_SAVE_CTRL__START_GRBM_REG_SAVE__SHIFT 0x0
#define RLC_SMU_GRBM_REG_SAVE_CTRL__SPARE_MASK 0xfffffffe
#define RLC_SMU_GRBM_REG_SAVE_CTRL__SPARE__SHIFT 0x1
#define RLC_SMU_PG_CTRL__START_PG_MASK 0x1
#define RLC_SMU_PG_CTRL__START_PG__SHIFT 0x0
#define RLC_SMU_PG_CTRL__SPARE_MASK 0xfffffffe
#define RLC_SMU_PG_CTRL__SPARE__SHIFT 0x1
#define RLC_SMU_PG_WAKE_UP_CTRL__START_PG_WAKE_UP_MASK 0x1
#define RLC_SMU_PG_WAKE_UP_CTRL__START_PG_WAKE_UP__SHIFT 0x0
#define RLC_SMU_PG_WAKE_UP_CTRL__SPARE_MASK 0xfffffffe
#define RLC_SMU_PG_WAKE_UP_CTRL__SPARE__SHIFT 0x1
#define RLC_SERDES_RD_MASTER_INDEX__CU_ID_MASK 0xf
#define RLC_SERDES_RD_MASTER_INDEX__CU_ID__SHIFT 0x0
#define RLC_SERDES_RD_MASTER_INDEX__SH_ID_MASK 0x30
#define RLC_SERDES_RD_MASTER_INDEX__SH_ID__SHIFT 0x4
#define RLC_SERDES_RD_MASTER_INDEX__SE_ID_MASK 0x1c0
#define RLC_SERDES_RD_MASTER_INDEX__SE_ID__SHIFT 0x6
#define RLC_SERDES_RD_MASTER_INDEX__SE_NONCU_ID_MASK 0x200
#define RLC_SERDES_RD_MASTER_INDEX__SE_NONCU_ID__SHIFT 0x9
#define RLC_SERDES_RD_MASTER_INDEX__SE_NONCU_MASK 0x400
#define RLC_SERDES_RD_MASTER_INDEX__SE_NONCU__SHIFT 0xa
#define RLC_SERDES_RD_MASTER_INDEX__NON_SE_MASK 0x7800
#define RLC_SERDES_RD_MASTER_INDEX__NON_SE__SHIFT 0xb
#define RLC_SERDES_RD_MASTER_INDEX__DATA_REG_ID_MASK 0x18000
#define RLC_SERDES_RD_MASTER_INDEX__DATA_REG_ID__SHIFT 0xf
#define RLC_SERDES_RD_MASTER_INDEX__SPARE_MASK 0xfffe0000
#define RLC_SERDES_RD_MASTER_INDEX__SPARE__SHIFT 0x11
#define RLC_SERDES_RD_DATA_0__DATA_MASK 0xffffffff
#define RLC_SERDES_RD_DATA_0__DATA__SHIFT 0x0
#define RLC_SERDES_RD_DATA_1__DATA_MASK 0xffffffff
#define RLC_SERDES_RD_DATA_1__DATA__SHIFT 0x0
#define RLC_SERDES_RD_DATA_2__DATA_MASK 0xffffffff
#define RLC_SERDES_RD_DATA_2__DATA__SHIFT 0x0
#define RLC_SERDES_WR_CU_MASTER_MASK__MASTER_MASK_MASK 0xffffffff
#define RLC_SERDES_WR_CU_MASTER_MASK__MASTER_MASK__SHIFT 0x0
#define RLC_SERDES_WR_NONCU_MASTER_MASK__SE_MASTER_MASK_MASK 0xffff
#define RLC_SERDES_WR_NONCU_MASTER_MASK__SE_MASTER_MASK__SHIFT 0x0
#define RLC_SERDES_WR_NONCU_MASTER_MASK__GC_MASTER_MASK_MASK 0x10000
#define RLC_SERDES_WR_NONCU_MASTER_MASK__GC_MASTER_MASK__SHIFT 0x10
#define RLC_SERDES_WR_NONCU_MASTER_MASK__GC_GFX_MASTER_MASK_MASK 0x20000
#define RLC_SERDES_WR_NONCU_MASTER_MASK__GC_GFX_MASTER_MASK__SHIFT 0x11
#define RLC_SERDES_WR_NONCU_MASTER_MASK__TC0_MASTER_MASK_MASK 0x40000
#define RLC_SERDES_WR_NONCU_MASTER_MASK__TC0_MASTER_MASK__SHIFT 0x12
#define RLC_SERDES_WR_NONCU_MASTER_MASK__TC1_MASTER_MASK_MASK 0x80000
#define RLC_SERDES_WR_NONCU_MASTER_MASK__TC1_MASTER_MASK__SHIFT 0x13
#define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE0_MASTER_MASK_MASK 0x100000
#define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE0_MASTER_MASK__SHIFT 0x14
#define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE1_MASTER_MASK_MASK 0x200000
#define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE1_MASTER_MASK__SHIFT 0x15
#define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE2_MASTER_MASK_MASK 0x400000
#define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE2_MASTER_MASK__SHIFT 0x16
#define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE3_MASTER_MASK_MASK 0x800000
#define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE3_MASTER_MASK__SHIFT 0x17
#define RLC_SERDES_WR_NONCU_MASTER_MASK__RESERVED_MASK 0xff000000
#define RLC_SERDES_WR_NONCU_MASTER_MASK__RESERVED__SHIFT 0x18
#define RLC_SERDES_WR_CTRL__BPM_ADDR_MASK 0xff
#define RLC_SERDES_WR_CTRL__BPM_ADDR__SHIFT 0x0
#define RLC_SERDES_WR_CTRL__POWER_DOWN_MASK 0x100
#define RLC_SERDES_WR_CTRL__POWER_DOWN__SHIFT 0x8
#define RLC_SERDES_WR_CTRL__POWER_UP_MASK 0x200
#define RLC_SERDES_WR_CTRL__POWER_UP__SHIFT 0x9
#define RLC_SERDES_WR_CTRL__P1_SELECT_MASK 0x400
#define RLC_SERDES_WR_CTRL__P1_SELECT__SHIFT 0xa
#define RLC_SERDES_WR_CTRL__P2_SELECT_MASK 0x800
#define RLC_SERDES_WR_CTRL__P2_SELECT__SHIFT 0xb
#define RLC_SERDES_WR_CTRL__WRITE_COMMAND_MASK 0x1000
#define RLC_SERDES_WR_CTRL__WRITE_COMMAND__SHIFT 0xc
#define RLC_SERDES_WR_CTRL__READ_COMMAND_MASK 0x2000
#define RLC_SERDES_WR_CTRL__READ_COMMAND__SHIFT 0xd
#define RLC_SERDES_WR_CTRL__RDDATA_RESET_MASK 0x4000
#define RLC_SERDES_WR_CTRL__RDDATA_RESET__SHIFT 0xe
#define RLC_SERDES_WR_CTRL__SHORT_FORMAT_MASK 0x8000
#define RLC_SERDES_WR_CTRL__SHORT_FORMAT__SHIFT 0xf
#define RLC_SERDES_WR_CTRL__BPM_DATA_MASK 0x3ff0000
#define RLC_SERDES_WR_CTRL__BPM_DATA__SHIFT 0x10
#define RLC_SERDES_WR_CTRL__SRBM_OVERRIDE_MASK 0x4000000
#define RLC_SERDES_WR_CTRL__SRBM_OVERRIDE__SHIFT 0x1a
#define RLC_SERDES_WR_CTRL__RSVD_BPM_ADDR_MASK 0x8000000
#define RLC_SERDES_WR_CTRL__RSVD_BPM_ADDR__SHIFT 0x1b
#define RLC_SERDES_WR_CTRL__REG_ADDR_MASK 0xf0000000
#define RLC_SERDES_WR_CTRL__REG_ADDR__SHIFT 0x1c
#define RLC_SERDES_WR_DATA__DATA_MASK 0xffffffff
#define RLC_SERDES_WR_DATA__DATA__SHIFT 0x0
#define RLC_SERDES_CU_MASTER_BUSY__BUSY_BUSY_MASK 0xffffffff
#define RLC_SERDES_CU_MASTER_BUSY__BUSY_BUSY__SHIFT 0x0
#define RLC_SERDES_NONCU_MASTER_BUSY__SE_MASTER_BUSY_MASK 0xffff
#define RLC_SERDES_NONCU_MASTER_BUSY__SE_MASTER_BUSY__SHIFT 0x0
#define RLC_SERDES_NONCU_MASTER_BUSY__GC_MASTER_BUSY_MASK 0x10000
#define RLC_SERDES_NONCU_MASTER_BUSY__GC_MASTER_BUSY__SHIFT 0x10
#define RLC_SERDES_NONCU_MASTER_BUSY__GC_GFX_MASTER_BUSY_MASK 0x20000
#define RLC_SERDES_NONCU_MASTER_BUSY__GC_GFX_MASTER_BUSY__SHIFT 0x11
#define RLC_SERDES_NONCU_MASTER_BUSY__TC0_MASTER_BUSY_MASK 0x40000
#define RLC_SERDES_NONCU_MASTER_BUSY__TC0_MASTER_BUSY__SHIFT 0x12
#define RLC_SERDES_NONCU_MASTER_BUSY__TC1_MASTER_BUSY_MASK 0x80000
#define RLC_SERDES_NONCU_MASTER_BUSY__TC1_MASTER_BUSY__SHIFT 0x13
#define RLC_SERDES_NONCU_MASTER_BUSY__SPARE0_MASTER_BUSY_MASK 0x100000
#define RLC_SERDES_NONCU_MASTER_BUSY__SPARE0_MASTER_BUSY__SHIFT 0x14
#define RLC_SERDES_NONCU_MASTER_BUSY__SPARE1_MASTER_BUSY_MASK 0x200000
#define RLC_SERDES_NONCU_MASTER_BUSY__SPARE1_MASTER_BUSY__SHIFT 0x15
#define RLC_SERDES_NONCU_MASTER_BUSY__SPARE2_MASTER_BUSY_MASK 0x400000
#define RLC_SERDES_NONCU_MASTER_BUSY__SPARE2_MASTER_BUSY__SHIFT 0x16
#define RLC_SERDES_NONCU_MASTER_BUSY__SPARE3_MASTER_BUSY_MASK 0x800000
#define RLC_SERDES_NONCU_MASTER_BUSY__SPARE3_MASTER_BUSY__SHIFT 0x17
#define RLC_SERDES_NONCU_MASTER_BUSY__RESERVED_MASK 0xff000000
#define RLC_SERDES_NONCU_MASTER_BUSY__RESERVED__SHIFT 0x18
#define RLC_GPM_GENERAL_0__DATA_MASK 0xffffffff
#define RLC_GPM_GENERAL_0__DATA__SHIFT 0x0
#define RLC_GPM_GENERAL_1__DATA_MASK 0xffffffff
#define RLC_GPM_GENERAL_1__DATA__SHIFT 0x0
#define RLC_GPM_GENERAL_2__DATA_MASK 0xffffffff
#define RLC_GPM_GENERAL_2__DATA__SHIFT 0x0
#define RLC_GPM_GENERAL_3__DATA_MASK 0xffffffff
#define RLC_GPM_GENERAL_3__DATA__SHIFT 0x0
#define RLC_GPM_GENERAL_4__DATA_MASK 0xffffffff
#define RLC_GPM_GENERAL_4__DATA__SHIFT 0x0
#define RLC_GPM_GENERAL_5__DATA_MASK 0xffffffff
#define RLC_GPM_GENERAL_5__DATA__SHIFT 0x0
#define RLC_GPM_GENERAL_6__DATA_MASK 0xffffffff
#define RLC_GPM_GENERAL_6__DATA__SHIFT 0x0
#define RLC_GPM_GENERAL_7__DATA_MASK 0xffffffff
#define RLC_GPM_GENERAL_7__DATA__SHIFT 0x0
#define RLC_GPM_CU_PD_TIMEOUT__TIMEOUT_MASK 0xffffffff
#define RLC_GPM_CU_PD_TIMEOUT__TIMEOUT__SHIFT 0x0
#define RLC_GPM_SCRATCH_ADDR__ADDR_MASK 0x1ff
#define RLC_GPM_SCRATCH_ADDR__ADDR__SHIFT 0x0
#define RLC_GPM_SCRATCH_ADDR__RESERVED_MASK 0xfffffe00
#define RLC_GPM_SCRATCH_ADDR__RESERVED__SHIFT 0x9
#define RLC_GPM_SCRATCH_DATA__DATA_MASK 0xffffffff
#define RLC_GPM_SCRATCH_DATA__DATA__SHIFT 0x0
#define RLC_STATIC_PG_STATUS__PG_STATUS_CU_MASK_MASK 0xffffffff
#define RLC_STATIC_PG_STATUS__PG_STATUS_CU_MASK__SHIFT 0x0
#define RLC_GPM_PERF_COUNT_0__FEATURE_SEL_MASK 0xf
#define RLC_GPM_PERF_COUNT_0__FEATURE_SEL__SHIFT 0x0
#define RLC_GPM_PERF_COUNT_0__SE_INDEX_MASK 0xf0
#define RLC_GPM_PERF_COUNT_0__SE_INDEX__SHIFT 0x4
#define RLC_GPM_PERF_COUNT_0__SH_INDEX_MASK 0xf00
#define RLC_GPM_PERF_COUNT_0__SH_INDEX__SHIFT 0x8
#define RLC_GPM_PERF_COUNT_0__CU_INDEX_MASK 0xf000
#define RLC_GPM_PERF_COUNT_0__CU_INDEX__SHIFT 0xc
#define RLC_GPM_PERF_COUNT_0__EVENT_SEL_MASK 0x30000
#define RLC_GPM_PERF_COUNT_0__EVENT_SEL__SHIFT 0x10
#define RLC_GPM_PERF_COUNT_0__UNUSED_MASK 0xc0000
#define RLC_GPM_PERF_COUNT_0__UNUSED__SHIFT 0x12
#define RLC_GPM_PERF_COUNT_0__ENABLE_MASK 0x100000
#define RLC_GPM_PERF_COUNT_0__ENABLE__SHIFT 0x14
#define RLC_GPM_PERF_COUNT_0__RESERVED_MASK 0xffe00000
#define RLC_GPM_PERF_COUNT_0__RESERVED__SHIFT 0x15
#define RLC_GPM_PERF_COUNT_1__FEATURE_SEL_MASK 0xf
#define RLC_GPM_PERF_COUNT_1__FEATURE_SEL__SHIFT 0x0
#define RLC_GPM_PERF_COUNT_1__SE_INDEX_MASK 0xf0
#define RLC_GPM_PERF_COUNT_1__SE_INDEX__SHIFT 0x4
#define RLC_GPM_PERF_COUNT_1__SH_INDEX_MASK 0xf00
#define RLC_GPM_PERF_COUNT_1__SH_INDEX__SHIFT 0x8
#define RLC_GPM_PERF_COUNT_1__CU_INDEX_MASK 0xf000
#define RLC_GPM_PERF_COUNT_1__CU_INDEX__SHIFT 0xc
#define RLC_GPM_PERF_COUNT_1__EVENT_SEL_MASK 0x30000
#define RLC_GPM_PERF_COUNT_1__EVENT_SEL__SHIFT 0x10
#define RLC_GPM_PERF_COUNT_1__UNUSED_MASK 0xc0000
#define RLC_GPM_PERF_COUNT_1__UNUSED__SHIFT 0x12
#define RLC_GPM_PERF_COUNT_1__ENABLE_MASK 0x100000
#define RLC_GPM_PERF_COUNT_1__ENABLE__SHIFT 0x14
#define RLC_GPM_PERF_COUNT_1__RESERVED_MASK 0xffe00000
#define RLC_GPM_PERF_COUNT_1__RESERVED__SHIFT 0x15
#define RLC_GPR_REG1__DATA_MASK 0xffffffff
#define RLC_GPR_REG1__DATA__SHIFT 0x0
#define RLC_GPR_REG2__DATA_MASK 0xffffffff
#define RLC_GPR_REG2__DATA__SHIFT 0x0
#define RLC_MGCG_CTRL__MGCG_EN_MASK 0x1
#define RLC_MGCG_CTRL__MGCG_EN__SHIFT 0x0
#define RLC_MGCG_CTRL__SILICON_EN_MASK 0x2
#define RLC_MGCG_CTRL__SILICON_EN__SHIFT 0x1
#define RLC_MGCG_CTRL__SIMULATION_EN_MASK 0x4
#define RLC_MGCG_CTRL__SIMULATION_EN__SHIFT 0x2
#define RLC_MGCG_CTRL__ON_DELAY_MASK 0x78
#define RLC_MGCG_CTRL__ON_DELAY__SHIFT 0x3
#define RLC_MGCG_CTRL__OFF_HYSTERESIS_MASK 0x7f80
#define RLC_MGCG_CTRL__OFF_HYSTERESIS__SHIFT 0x7
#define RLC_MGCG_CTRL__SPARE_MASK 0xffff8000
#define RLC_MGCG_CTRL__SPARE__SHIFT 0xf
#define RLC_GPM_THREAD_RESET__THREAD0_RESET_MASK 0x1
#define RLC_GPM_THREAD_RESET__THREAD0_RESET__SHIFT 0x0
#define RLC_GPM_THREAD_RESET__THREAD1_RESET_MASK 0x2
#define RLC_GPM_THREAD_RESET__THREAD1_RESET__SHIFT 0x1
#define RLC_GPM_THREAD_RESET__THREAD2_RESET_MASK 0x4
#define RLC_GPM_THREAD_RESET__THREAD2_RESET__SHIFT 0x2
#define RLC_GPM_THREAD_RESET__THREAD3_RESET_MASK 0x8
#define RLC_GPM_THREAD_RESET__THREAD3_RESET__SHIFT 0x3
#define RLC_GPM_THREAD_RESET__RESERVED_MASK 0xfffffff0
#define RLC_GPM_THREAD_RESET__RESERVED__SHIFT 0x4
#define RLC_SPM_VMID__RLC_SPM_VMID_MASK 0xf
#define RLC_SPM_VMID__RLC_SPM_VMID__SHIFT 0x0
#define RLC_SPM_VMID__RESERVED_MASK 0xfffffff0
#define RLC_SPM_VMID__RESERVED__SHIFT 0x4
#define RLC_SPM_INT_CNTL__RLC_SPM_INT_CNTL_MASK 0x1
#define RLC_SPM_INT_CNTL__RLC_SPM_INT_CNTL__SHIFT 0x0
#define RLC_SPM_INT_CNTL__RESERVED_MASK 0xfffffffe
#define RLC_SPM_INT_CNTL__RESERVED__SHIFT 0x1
#define RLC_SPM_INT_STATUS__RLC_SPM_INT_STATUS_MASK 0x1
#define RLC_SPM_INT_STATUS__RLC_SPM_INT_STATUS__SHIFT 0x0
#define RLC_SPM_INT_STATUS__RESERVED_MASK 0xfffffffe
#define RLC_SPM_INT_STATUS__RESERVED__SHIFT 0x1
#define RLC_SPM_DEBUG_SELECT__SELECT_MASK 0xff
#define RLC_SPM_DEBUG_SELECT__SELECT__SHIFT 0x0
#define RLC_SPM_DEBUG_SELECT__RESERVED_MASK 0x7f00
#define RLC_SPM_DEBUG_SELECT__RESERVED__SHIFT 0x8
#define RLC_SPM_DEBUG_SELECT__RLC_SPM_DEBUG_MODE_MASK 0x8000
#define RLC_SPM_DEBUG_SELECT__RLC_SPM_DEBUG_MODE__SHIFT 0xf
#define RLC_SPM_DEBUG_SELECT__RLC_SPM_NUM_SAMPLE_MASK 0xffff0000
#define RLC_SPM_DEBUG_SELECT__RLC_SPM_NUM_SAMPLE__SHIFT 0x10
#define RLC_SPM_DEBUG__DATA_MASK 0xffffffff
#define RLC_SPM_DEBUG__DATA__SHIFT 0x0
#define RLC_GPM_LOG_ADDR__ADDR_MASK 0xffffffff
#define RLC_GPM_LOG_ADDR__ADDR__SHIFT 0x0
#define RLC_SMU_MESSAGE__CMD_MASK 0xffffffff
#define RLC_SMU_MESSAGE__CMD__SHIFT 0x0
#define RLC_GPM_LOG_SIZE__SIZE_MASK 0xffffffff
#define RLC_GPM_LOG_SIZE__SIZE__SHIFT 0x0
#define RLC_GPM_LOG_CONT__CONT_MASK 0xffffffff
#define RLC_GPM_LOG_CONT__CONT__SHIFT 0x0
#define RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG_MASK 0xff
#define RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG__SHIFT 0x0
#define RLC_GPM_INT_DISABLE_TH0__DISABLE_MASK 0xffffffff
#define RLC_GPM_INT_DISABLE_TH0__DISABLE__SHIFT 0x0
#define RLC_GPM_INT_DISABLE_TH1__DISABLE_MASK 0xffffffff
#define RLC_GPM_INT_DISABLE_TH1__DISABLE__SHIFT 0x0
#define RLC_GPM_INT_FORCE_TH0__FORCE_MASK 0xffffffff
#define RLC_GPM_INT_FORCE_TH0__FORCE__SHIFT 0x0
#define RLC_GPM_INT_FORCE_TH1__FORCE_MASK 0xffffffff
#define RLC_GPM_INT_FORCE_TH1__FORCE__SHIFT 0x0
#define RLC_SRM_CNTL__SRM_ENABLE_MASK 0x1
#define RLC_SRM_CNTL__SRM_ENABLE__SHIFT 0x0
#define RLC_SRM_CNTL__AUTO_INCR_ADDR_MASK 0x2
#define RLC_SRM_CNTL__AUTO_INCR_ADDR__SHIFT 0x1
#define RLC_SRM_CNTL__RESERVED_MASK 0xfffffffc
#define RLC_SRM_CNTL__RESERVED__SHIFT 0x2
#define RLC_SRM_DEBUG_SELECT__SELECT_MASK 0xff
#define RLC_SRM_DEBUG_SELECT__SELECT__SHIFT 0x0
#define RLC_SRM_DEBUG_SELECT__RESERVED_MASK 0xffffff00
#define RLC_SRM_DEBUG_SELECT__RESERVED__SHIFT 0x8
#define RLC_SRM_DEBUG__DATA_MASK 0xffffffff
#define RLC_SRM_DEBUG__DATA__SHIFT 0x0
#define RLC_SRM_ARAM_DATA__DATA_MASK 0xffffffff
#define RLC_SRM_ARAM_DATA__DATA__SHIFT 0x0
#define RLC_SRM_DRAM_ADDR__RESERVED_MASK 0xfffffc00
#define RLC_SRM_DRAM_ADDR__RESERVED__SHIFT 0xa
#define RLC_SRM_DRAM_DATA__DATA_MASK 0xffffffff
#define RLC_SRM_DRAM_DATA__DATA__SHIFT 0x0
#define RLC_SRM_GPM_COMMAND__OP_MASK 0x1
#define RLC_SRM_GPM_COMMAND__OP__SHIFT 0x0
#define RLC_SRM_GPM_COMMAND__INDEX_CNTL_MASK 0x2
#define RLC_SRM_GPM_COMMAND__INDEX_CNTL__SHIFT 0x1
#define RLC_SRM_GPM_COMMAND__INDEX_CNTL_NUM_MASK 0x1c
#define RLC_SRM_GPM_COMMAND__INDEX_CNTL_NUM__SHIFT 0x2
#define RLC_SRM_GPM_COMMAND__SIZE_MASK 0x1ffe0
#define RLC_SRM_GPM_COMMAND__SIZE__SHIFT 0x5
#define RLC_SRM_GPM_COMMAND__START_OFFSET_MASK 0x1ffe0000
#define RLC_SRM_GPM_COMMAND__START_OFFSET__SHIFT 0x11
#define RLC_SRM_GPM_COMMAND__RESERVED1_MASK 0x60000000
#define RLC_SRM_GPM_COMMAND__RESERVED1__SHIFT 0x1d
#define RLC_SRM_GPM_COMMAND__DEST_MEMORY_MASK 0x80000000
#define RLC_SRM_GPM_COMMAND__DEST_MEMORY__SHIFT 0x1f
#define RLC_SRM_GPM_COMMAND_STATUS__FIFO_EMPTY_MASK 0x1
#define RLC_SRM_GPM_COMMAND_STATUS__FIFO_EMPTY__SHIFT 0x0
#define RLC_SRM_GPM_COMMAND_STATUS__FIFO_FULL_MASK 0x2
#define RLC_SRM_GPM_COMMAND_STATUS__FIFO_FULL__SHIFT 0x1
#define RLC_SRM_GPM_COMMAND_STATUS__RESERVED_MASK 0xfffffffc
#define RLC_SRM_GPM_COMMAND_STATUS__RESERVED__SHIFT 0x2
#define RLC_SRM_RLCV_COMMAND__OP_MASK 0x1
#define RLC_SRM_RLCV_COMMAND__OP__SHIFT 0x0
#define RLC_SRM_RLCV_COMMAND__RESERVED_MASK 0xe
#define RLC_SRM_RLCV_COMMAND__RESERVED__SHIFT 0x1
#define RLC_SRM_RLCV_COMMAND__SIZE_MASK 0xfff0
#define RLC_SRM_RLCV_COMMAND__SIZE__SHIFT 0x4
#define RLC_SRM_RLCV_COMMAND__START_OFFSET_MASK 0xfff0000
#define RLC_SRM_RLCV_COMMAND__START_OFFSET__SHIFT 0x10
#define RLC_SRM_RLCV_COMMAND__RESERVED1_MASK 0x70000000
#define RLC_SRM_RLCV_COMMAND__RESERVED1__SHIFT 0x1c
#define RLC_SRM_RLCV_COMMAND__DEST_MEMORY_MASK 0x80000000
#define RLC_SRM_RLCV_COMMAND__DEST_MEMORY__SHIFT 0x1f
#define RLC_SRM_RLCV_COMMAND_STATUS__FIFO_EMPTY_MASK 0x1
#define RLC_SRM_RLCV_COMMAND_STATUS__FIFO_EMPTY__SHIFT 0x0
#define RLC_SRM_RLCV_COMMAND_STATUS__FIFO_FULL_MASK 0x2
#define RLC_SRM_RLCV_COMMAND_STATUS__FIFO_FULL__SHIFT 0x1
#define RLC_SRM_RLCV_COMMAND_STATUS__RESERVED_MASK 0xfffffffc
#define RLC_SRM_RLCV_COMMAND_STATUS__RESERVED__SHIFT 0x2
#define RLC_SRM_INDEX_CNTL_ADDR_0__ADDRESS_MASK 0xffff
#define RLC_SRM_INDEX_CNTL_ADDR_0__ADDRESS__SHIFT 0x0
#define RLC_SRM_INDEX_CNTL_ADDR_0__RESERVED_MASK 0xffff0000
#define RLC_SRM_INDEX_CNTL_ADDR_0__RESERVED__SHIFT 0x10
#define RLC_SRM_INDEX_CNTL_ADDR_1__ADDRESS_MASK 0xffff
#define RLC_SRM_INDEX_CNTL_ADDR_1__ADDRESS__SHIFT 0x0
#define RLC_SRM_INDEX_CNTL_ADDR_1__RESERVED_MASK 0xffff0000
#define RLC_SRM_INDEX_CNTL_ADDR_1__RESERVED__SHIFT 0x10
#define RLC_SRM_INDEX_CNTL_ADDR_2__ADDRESS_MASK 0xffff
#define RLC_SRM_INDEX_CNTL_ADDR_2__ADDRESS__SHIFT 0x0
#define RLC_SRM_INDEX_CNTL_ADDR_2__RESERVED_MASK 0xffff0000
#define RLC_SRM_INDEX_CNTL_ADDR_2__RESERVED__SHIFT 0x10
#define RLC_SRM_INDEX_CNTL_ADDR_3__ADDRESS_MASK 0xffff
#define RLC_SRM_INDEX_CNTL_ADDR_3__ADDRESS__SHIFT 0x0
#define RLC_SRM_INDEX_CNTL_ADDR_3__RESERVED_MASK 0xffff0000
#define RLC_SRM_INDEX_CNTL_ADDR_3__RESERVED__SHIFT 0x10
#define RLC_SRM_INDEX_CNTL_ADDR_4__ADDRESS_MASK 0xffff
#define RLC_SRM_INDEX_CNTL_ADDR_4__ADDRESS__SHIFT 0x0
#define RLC_SRM_INDEX_CNTL_ADDR_4__RESERVED_MASK 0xffff0000
#define RLC_SRM_INDEX_CNTL_ADDR_4__RESERVED__SHIFT 0x10
#define RLC_SRM_INDEX_CNTL_ADDR_5__ADDRESS_MASK 0xffff
#define RLC_SRM_INDEX_CNTL_ADDR_5__ADDRESS__SHIFT 0x0
#define RLC_SRM_INDEX_CNTL_ADDR_5__RESERVED_MASK 0xffff0000
#define RLC_SRM_INDEX_CNTL_ADDR_5__RESERVED__SHIFT 0x10
#define RLC_SRM_INDEX_CNTL_ADDR_6__ADDRESS_MASK 0xffff
#define RLC_SRM_INDEX_CNTL_ADDR_6__ADDRESS__SHIFT 0x0
#define RLC_SRM_INDEX_CNTL_ADDR_6__RESERVED_MASK 0xffff0000
#define RLC_SRM_INDEX_CNTL_ADDR_6__RESERVED__SHIFT 0x10
#define RLC_SRM_INDEX_CNTL_ADDR_7__ADDRESS_MASK 0xffff
#define RLC_SRM_INDEX_CNTL_ADDR_7__ADDRESS__SHIFT 0x0
#define RLC_SRM_INDEX_CNTL_ADDR_7__RESERVED_MASK 0xffff0000
#define RLC_SRM_INDEX_CNTL_ADDR_7__RESERVED__SHIFT 0x10
#define RLC_SRM_INDEX_CNTL_DATA_0__DATA_MASK 0xffffffff
#define RLC_SRM_INDEX_CNTL_DATA_0__DATA__SHIFT 0x0
#define RLC_SRM_INDEX_CNTL_DATA_1__DATA_MASK 0xffffffff
#define RLC_SRM_INDEX_CNTL_DATA_1__DATA__SHIFT 0x0
#define RLC_SRM_INDEX_CNTL_DATA_2__DATA_MASK 0xffffffff
#define RLC_SRM_INDEX_CNTL_DATA_2__DATA__SHIFT 0x0
#define RLC_SRM_INDEX_CNTL_DATA_3__DATA_MASK 0xffffffff
#define RLC_SRM_INDEX_CNTL_DATA_3__DATA__SHIFT 0x0
#define RLC_SRM_INDEX_CNTL_DATA_4__DATA_MASK 0xffffffff
#define RLC_SRM_INDEX_CNTL_DATA_4__DATA__SHIFT 0x0
#define RLC_SRM_INDEX_CNTL_DATA_5__DATA_MASK 0xffffffff
#define RLC_SRM_INDEX_CNTL_DATA_5__DATA__SHIFT 0x0
#define RLC_SRM_INDEX_CNTL_DATA_6__DATA_MASK 0xffffffff
#define RLC_SRM_INDEX_CNTL_DATA_6__DATA__SHIFT 0x0
#define RLC_SRM_INDEX_CNTL_DATA_7__DATA_MASK 0xffffffff
#define RLC_SRM_INDEX_CNTL_DATA_7__DATA__SHIFT 0x0
#define RLC_SRM_STAT__SRM_STATUS_MASK 0x1
#define RLC_SRM_STAT__SRM_STATUS__SHIFT 0x0
#define RLC_SRM_STAT__RESERVED_MASK 0xfffffffe
#define RLC_SRM_STAT__RESERVED__SHIFT 0x1
#define RLC_SRM_GPM_ABORT__ABORT_MASK 0x1
#define RLC_SRM_GPM_ABORT__ABORT__SHIFT 0x0
#define RLC_SRM_GPM_ABORT__RESERVED_MASK 0xfffffffe
#define RLC_SRM_GPM_ABORT__RESERVED__SHIFT 0x1
#define RLC_CSIB_ADDR_LO__ADDRESS_MASK 0xffffffff
#define RLC_CSIB_ADDR_LO__ADDRESS__SHIFT 0x0
#define RLC_CSIB_ADDR_HI__ADDRESS_MASK 0xffff
#define RLC_CSIB_ADDR_HI__ADDRESS__SHIFT 0x0
#define RLC_CSIB_LENGTH__LENGTH_MASK 0xffffffff
#define RLC_CSIB_LENGTH__LENGTH__SHIFT 0x0
#define RLC_CP_RESPONSE0__RESPONSE_MASK 0xffffffff
#define RLC_CP_RESPONSE0__RESPONSE__SHIFT 0x0
#define RLC_CP_RESPONSE1__RESPONSE_MASK 0xffffffff
#define RLC_CP_RESPONSE1__RESPONSE__SHIFT 0x0
#define RLC_CP_RESPONSE2__RESPONSE_MASK 0xffffffff
#define RLC_CP_RESPONSE2__RESPONSE__SHIFT 0x0
#define RLC_CP_RESPONSE3__RESPONSE_MASK 0xffffffff
#define RLC_CP_RESPONSE3__RESPONSE__SHIFT 0x0
#define RLC_SMU_COMMAND__CMD_MASK 0xffffffff
#define RLC_SMU_COMMAND__CMD__SHIFT 0x0
#define RLC_CP_SCHEDULERS__scheduler0_MASK 0xff
#define RLC_CP_SCHEDULERS__scheduler0__SHIFT 0x0
#define RLC_CP_SCHEDULERS__scheduler1_MASK 0xff00
#define RLC_CP_SCHEDULERS__scheduler1__SHIFT 0x8
#define RLC_CP_SCHEDULERS__scheduler2_MASK 0xff0000
#define RLC_CP_SCHEDULERS__scheduler2__SHIFT 0x10
#define RLC_CP_SCHEDULERS__scheduler3_MASK 0xff000000
#define RLC_CP_SCHEDULERS__scheduler3__SHIFT 0x18
#define RLC_SPM_PERFMON_CNTL__RESERVED1_MASK 0xfff
#define RLC_SPM_PERFMON_CNTL__RESERVED1__SHIFT 0x0
#define RLC_SPM_PERFMON_CNTL__PERFMON_RING_MODE_MASK 0x3000
#define RLC_SPM_PERFMON_CNTL__PERFMON_RING_MODE__SHIFT 0xc
#define RLC_SPM_PERFMON_CNTL__RESERVED_MASK 0xc000
#define RLC_SPM_PERFMON_CNTL__RESERVED__SHIFT 0xe
#define RLC_SPM_PERFMON_CNTL__PERFMON_SAMPLE_INTERVAL_MASK 0xffff0000
#define RLC_SPM_PERFMON_CNTL__PERFMON_SAMPLE_INTERVAL__SHIFT 0x10
#define RLC_SPM_PERFMON_RING_BASE_LO__RING_BASE_LO_MASK 0xffffffff
#define RLC_SPM_PERFMON_RING_BASE_LO__RING_BASE_LO__SHIFT 0x0
#define RLC_SPM_PERFMON_RING_BASE_HI__RING_BASE_HI_MASK 0xffff
#define RLC_SPM_PERFMON_RING_BASE_HI__RING_BASE_HI__SHIFT 0x0
#define RLC_SPM_PERFMON_RING_BASE_HI__RESERVED_MASK 0xffff0000
#define RLC_SPM_PERFMON_RING_BASE_HI__RESERVED__SHIFT 0x10
#define RLC_SPM_PERFMON_RING_SIZE__RING_BASE_SIZE_MASK 0xffffffff
#define RLC_SPM_PERFMON_RING_SIZE__RING_BASE_SIZE__SHIFT 0x0
#define RLC_SPM_PERFMON_SEGMENT_SIZE__PERFMON_SEGMENT_SIZE_MASK 0xff
#define RLC_SPM_PERFMON_SEGMENT_SIZE__PERFMON_SEGMENT_SIZE__SHIFT 0x0
#define RLC_SPM_PERFMON_SEGMENT_SIZE__RESERVED1_MASK 0x700
#define RLC_SPM_PERFMON_SEGMENT_SIZE__RESERVED1__SHIFT 0x8
#define RLC_SPM_PERFMON_SEGMENT_SIZE__GLOBAL_NUM_LINE_MASK 0xf800
#define RLC_SPM_PERFMON_SEGMENT_SIZE__GLOBAL_NUM_LINE__SHIFT 0xb
#define RLC_SPM_PERFMON_SEGMENT_SIZE__SE0_NUM_LINE_MASK 0x1f0000
#define RLC_SPM_PERFMON_SEGMENT_SIZE__SE0_NUM_LINE__SHIFT 0x10
#define RLC_SPM_PERFMON_SEGMENT_SIZE__SE1_NUM_LINE_MASK 0x3e00000
#define RLC_SPM_PERFMON_SEGMENT_SIZE__SE1_NUM_LINE__SHIFT 0x15
#define RLC_SPM_PERFMON_SEGMENT_SIZE__SE2_NUM_LINE_MASK 0x7c000000
#define RLC_SPM_PERFMON_SEGMENT_SIZE__SE2_NUM_LINE__SHIFT 0x1a
#define RLC_SPM_PERFMON_SEGMENT_SIZE__RESERVED_MASK 0x80000000
#define RLC_SPM_PERFMON_SEGMENT_SIZE__RESERVED__SHIFT 0x1f
#define RLC_SPM_SE_MUXSEL_ADDR__PERFMON_SEL_ADDR_MASK 0xffffffff
#define RLC_SPM_SE_MUXSEL_ADDR__PERFMON_SEL_ADDR__SHIFT 0x0
#define RLC_SPM_SE_MUXSEL_DATA__PERFMON_SEL_DATA_MASK 0xffffffff
#define RLC_SPM_SE_MUXSEL_DATA__PERFMON_SEL_DATA__SHIFT 0x0
#define RLC_SPM_CPG_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff
#define RLC_SPM_CPG_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
#define RLC_SPM_CPG_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00
#define RLC_SPM_CPG_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
#define RLC_SPM_CPC_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff
#define RLC_SPM_CPC_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
#define RLC_SPM_CPC_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00
#define RLC_SPM_CPC_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
#define RLC_SPM_CPF_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff
#define RLC_SPM_CPF_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
#define RLC_SPM_CPF_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00
#define RLC_SPM_CPF_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
#define RLC_SPM_CB_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff
#define RLC_SPM_CB_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
#define RLC_SPM_CB_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00
#define RLC_SPM_CB_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
#define RLC_SPM_DB_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff
#define RLC_SPM_DB_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
#define RLC_SPM_DB_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00
#define RLC_SPM_DB_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
#define RLC_SPM_PA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff
#define RLC_SPM_PA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
#define RLC_SPM_PA_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00
#define RLC_SPM_PA_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
#define RLC_SPM_GDS_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff
#define RLC_SPM_GDS_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
#define RLC_SPM_GDS_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00
#define RLC_SPM_GDS_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
#define RLC_SPM_IA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff
#define RLC_SPM_IA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
#define RLC_SPM_IA_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00
#define RLC_SPM_IA_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
#define RLC_SPM_SC_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff
#define RLC_SPM_SC_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
#define RLC_SPM_SC_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00
#define RLC_SPM_SC_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
#define RLC_SPM_TCC_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff
#define RLC_SPM_TCC_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
#define RLC_SPM_TCC_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00
#define RLC_SPM_TCC_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
#define RLC_SPM_TCA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff
#define RLC_SPM_TCA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
#define RLC_SPM_TCA_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00
#define RLC_SPM_TCA_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
#define RLC_SPM_TCP_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff
#define RLC_SPM_TCP_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
#define RLC_SPM_TCP_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00
#define RLC_SPM_TCP_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
#define RLC_SPM_TA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff
#define RLC_SPM_TA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
#define RLC_SPM_TA_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00
#define RLC_SPM_TA_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
#define RLC_SPM_TD_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff
#define RLC_SPM_TD_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
#define RLC_SPM_TD_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00
#define RLC_SPM_TD_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
#define RLC_SPM_VGT_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff
#define RLC_SPM_VGT_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
#define RLC_SPM_VGT_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00
#define RLC_SPM_VGT_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
#define RLC_SPM_SPI_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff
#define RLC_SPM_SPI_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
#define RLC_SPM_SPI_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00
#define RLC_SPM_SPI_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
#define RLC_SPM_SQG_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff
#define RLC_SPM_SQG_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
#define RLC_SPM_SQG_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00
#define RLC_SPM_SQG_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
#define RLC_SPM_SX_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff
#define RLC_SPM_SX_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
#define RLC_SPM_SX_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00
#define RLC_SPM_SX_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
#define RLC_SPM_GLOBAL_MUXSEL_ADDR__PERFMON_SEL_ADDR_MASK 0xffffffff
#define RLC_SPM_GLOBAL_MUXSEL_ADDR__PERFMON_SEL_ADDR__SHIFT 0x0
#define RLC_SPM_GLOBAL_MUXSEL_DATA__PERFMON_SEL_DATA_MASK 0xffffffff
#define RLC_SPM_GLOBAL_MUXSEL_DATA__PERFMON_SEL_DATA__SHIFT 0x0
#define RLC_SPM_RING_RDPTR__PERFMON_RING_RDPTR_MASK 0xffffffff
#define RLC_SPM_RING_RDPTR__PERFMON_RING_RDPTR__SHIFT 0x0
#define RLC_SPM_SEGMENT_THRESHOLD__NUM_SEGMENT_THRESHOLD_MASK 0xffffffff
#define RLC_SPM_SEGMENT_THRESHOLD__NUM_SEGMENT_THRESHOLD__SHIFT 0x0
#define RLC_SPM_DBR0_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff
#define RLC_SPM_DBR0_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
#define RLC_SPM_DBR0_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00
#define RLC_SPM_DBR0_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
#define RLC_SPM_DBR1_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff
#define RLC_SPM_DBR1_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
#define RLC_SPM_DBR1_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00
#define RLC_SPM_DBR1_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
#define RLC_SPM_CBR0_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff
#define RLC_SPM_CBR0_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
#define RLC_SPM_CBR0_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00
#define RLC_SPM_CBR0_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
#define RLC_SPM_CBR1_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff
#define RLC_SPM_CBR1_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
#define RLC_SPM_CBR1_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00
#define RLC_SPM_CBR1_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
#define RLC_GPU_IOV_VF_ENABLE__VF_ENABLE_MASK 0x1
#define RLC_GPU_IOV_VF_ENABLE__VF_ENABLE__SHIFT 0x0
#define RLC_GPU_IOV_VF_ENABLE__RESERVED_MASK 0xfffe
#define RLC_GPU_IOV_VF_ENABLE__RESERVED__SHIFT 0x1
#define RLC_GPU_IOV_VF_ENABLE__VF_NUM_MASK 0xffff0000
#define RLC_GPU_IOV_VF_ENABLE__VF_NUM__SHIFT 0x10
#define RLC_GPU_IOV_CFG_REG1__CMD_TYPE_MASK 0xf
#define RLC_GPU_IOV_CFG_REG1__CMD_TYPE__SHIFT 0x0
#define RLC_GPU_IOV_CFG_REG1__CMD_EXECUTE_MASK 0x10
#define RLC_GPU_IOV_CFG_REG1__CMD_EXECUTE__SHIFT 0x4
#define RLC_GPU_IOV_CFG_REG1__CMD_EXECUTE_INTR_EN_MASK 0x20
#define RLC_GPU_IOV_CFG_REG1__CMD_EXECUTE_INTR_EN__SHIFT 0x5
#define RLC_GPU_IOV_CFG_REG1__RESERVED_MASK 0xc0
#define RLC_GPU_IOV_CFG_REG1__RESERVED__SHIFT 0x6
#define RLC_GPU_IOV_CFG_REG1__FCN_ID_MASK 0xff00
#define RLC_GPU_IOV_CFG_REG1__FCN_ID__SHIFT 0x8
#define RLC_GPU_IOV_CFG_REG1__NEXT_FCN_ID_MASK 0xff0000
#define RLC_GPU_IOV_CFG_REG1__NEXT_FCN_ID__SHIFT 0x10
#define RLC_GPU_IOV_CFG_REG1__RESERVED1_MASK 0xff000000
#define RLC_GPU_IOV_CFG_REG1__RESERVED1__SHIFT 0x18
#define RLC_GPU_IOV_CFG_REG2__CMD_STATUS_MASK 0xf
#define RLC_GPU_IOV_CFG_REG2__CMD_STATUS__SHIFT 0x0
#define RLC_GPU_IOV_CFG_REG2__RESERVED_MASK 0xfffffff0
#define RLC_GPU_IOV_CFG_REG2__RESERVED__SHIFT 0x4
#define RLC_GPU_IOV_CFG_REG6__CNTXT_SIZE_MASK 0x7f
#define RLC_GPU_IOV_CFG_REG6__CNTXT_SIZE__SHIFT 0x0
#define RLC_GPU_IOV_CFG_REG6__CNTXT_LOCATION_MASK 0x80
#define RLC_GPU_IOV_CFG_REG6__CNTXT_LOCATION__SHIFT 0x7
#define RLC_GPU_IOV_CFG_REG6__RESERVED_MASK 0x300
#define RLC_GPU_IOV_CFG_REG6__RESERVED__SHIFT 0x8
#define RLC_GPU_IOV_CFG_REG6__CNTXT_OFFSET_MASK 0xfffffc00
#define RLC_GPU_IOV_CFG_REG6__CNTXT_OFFSET__SHIFT 0xa
#define RLC_GPU_IOV_CFG_REG8__VM_BUSY_STATUS_MASK 0xffffffff
#define RLC_GPU_IOV_CFG_REG8__VM_BUSY_STATUS__SHIFT 0x0
#define RLC_GPU_IOV_CFG_REG9__ACTIVE_FCN_ID_MASK 0xff
#define RLC_GPU_IOV_CFG_REG9__ACTIVE_FCN_ID__SHIFT 0x0
#define RLC_GPU_IOV_CFG_REG9__ACTIVE_FCN_ID_STATUS_MASK 0xf00
#define RLC_GPU_IOV_CFG_REG9__ACTIVE_FCN_ID_STATUS__SHIFT 0x8
#define RLC_GPU_IOV_CFG_REG9__RESERVED_MASK 0xfffff000
#define RLC_GPU_IOV_CFG_REG9__RESERVED__SHIFT 0xc
#define RLC_GPU_IOV_CFG_REG10__TIME_QUANTA_PF_MASK 0xffff
#define RLC_GPU_IOV_CFG_REG10__TIME_QUANTA_PF__SHIFT 0x0
#define RLC_GPU_IOV_CFG_REG10__RESERVED_MASK 0xffff0000
#define RLC_GPU_IOV_CFG_REG10__RESERVED__SHIFT 0x10
#define RLC_GPU_IOV_CFG_REG11__YIELD_MASK 0xffffffff
#define RLC_GPU_IOV_CFG_REG11__YIELD__SHIFT 0x0
#define RLC_GPU_IOV_CFG_REG12__TIME_QUANTA_VF0_MASK 0xff
#define RLC_GPU_IOV_CFG_REG12__TIME_QUANTA_VF0__SHIFT 0x0
#define RLC_GPU_IOV_CFG_REG12__TIME_QUANTA_VF1_MASK 0xff00
#define RLC_GPU_IOV_CFG_REG12__TIME_QUANTA_VF1__SHIFT 0x8
#define RLC_GPU_IOV_CFG_REG12__TIME_QUANTA_VF2_MASK 0xff0000
#define RLC_GPU_IOV_CFG_REG12__TIME_QUANTA_VF2__SHIFT 0x10
#define RLC_GPU_IOV_CFG_REG12__TIME_QUANTA_VF3_MASK 0xff000000
#define RLC_GPU_IOV_CFG_REG12__TIME_QUANTA_VF3__SHIFT 0x18
#define RLC_GPU_IOV_CFG_REG13__TIME_QUANTA_VF4_MASK 0xff
#define RLC_GPU_IOV_CFG_REG13__TIME_QUANTA_VF4__SHIFT 0x0
#define RLC_GPU_IOV_CFG_REG13__TIME_QUANTA_VF5_MASK 0xff00
#define RLC_GPU_IOV_CFG_REG13__TIME_QUANTA_VF5__SHIFT 0x8
#define RLC_GPU_IOV_CFG_REG13__TIME_QUANTA_VF6_MASK 0xff0000
#define RLC_GPU_IOV_CFG_REG13__TIME_QUANTA_VF6__SHIFT 0x10
#define RLC_GPU_IOV_CFG_REG13__TIME_QUANTA_VF7_MASK 0xff000000
#define RLC_GPU_IOV_CFG_REG13__TIME_QUANTA_VF7__SHIFT 0x18
#define RLC_GPU_IOV_CFG_REG14__TIME_QUANTA_VF8_MASK 0xff
#define RLC_GPU_IOV_CFG_REG14__TIME_QUANTA_VF8__SHIFT 0x0
#define RLC_GPU_IOV_CFG_REG14__TIME_QUANTA_VF9_MASK 0xff00
#define RLC_GPU_IOV_CFG_REG14__TIME_QUANTA_VF9__SHIFT 0x8
#define RLC_GPU_IOV_CFG_REG14__TIME_QUANTA_VF10_MASK 0xff0000
#define RLC_GPU_IOV_CFG_REG14__TIME_QUANTA_VF10__SHIFT 0x10
#define RLC_GPU_IOV_CFG_REG14__TIME_QUANTA_VF11_MASK 0xff000000
#define RLC_GPU_IOV_CFG_REG14__TIME_QUANTA_VF11__SHIFT 0x18
#define RLC_GPU_IOV_CFG_REG15__TIME_QUANTA_VF12_MASK 0xff
#define RLC_GPU_IOV_CFG_REG15__TIME_QUANTA_VF12__SHIFT 0x0
#define RLC_GPU_IOV_CFG_REG15__TIME_QUANTA_VF13_MASK 0xff00
#define RLC_GPU_IOV_CFG_REG15__TIME_QUANTA_VF13__SHIFT 0x8
#define RLC_GPU_IOV_CFG_REG15__TIME_QUANTA_VF14_MASK 0xff0000
#define RLC_GPU_IOV_CFG_REG15__TIME_QUANTA_VF14__SHIFT 0x10
#define RLC_GPU_IOV_CFG_REG15__TIME_QUANTA_VF15_MASK 0xff000000
#define RLC_GPU_IOV_CFG_REG15__TIME_QUANTA_VF15__SHIFT 0x18
#define RLC_GPU_IOV_ACTIVE_FCN_ID__VF_ID_MASK 0xf
#define RLC_GPU_IOV_ACTIVE_FCN_ID__VF_ID__SHIFT 0x0
#define RLC_GPU_IOV_ACTIVE_FCN_ID__RESERVED_MASK 0x7ffffff0
#define RLC_GPU_IOV_ACTIVE_FCN_ID__RESERVED__SHIFT 0x4
#define RLC_GPU_IOV_ACTIVE_FCN_ID__PF_VF_MASK 0x80000000
#define RLC_GPU_IOV_ACTIVE_FCN_ID__PF_VF__SHIFT 0x1f
#define RLC_GPM_VMID_THREAD2__RLC_VMID_MASK 0xf
#define RLC_GPM_VMID_THREAD2__RLC_VMID__SHIFT 0x0
#define RLC_GPM_VMID_THREAD2__RESERVED0_MASK 0xf0
#define RLC_GPM_VMID_THREAD2__RESERVED0__SHIFT 0x4
#define RLC_GPM_VMID_THREAD2__RLC_QUEUEID_MASK 0x700
#define RLC_GPM_VMID_THREAD2__RLC_QUEUEID__SHIFT 0x8
#define RLC_GPM_VMID_THREAD2__RESERVED1_MASK 0xfffff800
#define RLC_GPM_VMID_THREAD2__RESERVED1__SHIFT 0xb
#define RLC_GPU_IOV_UCODE_ADDR__UCODE_ADDR_MASK 0xfff
#define RLC_GPU_IOV_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0
#define RLC_GPU_IOV_UCODE_ADDR__RESERVED_MASK 0xfffff000
#define RLC_GPU_IOV_UCODE_ADDR__RESERVED__SHIFT 0xc
#define RLC_GPU_IOV_UCODE_DATA__UCODE_DATA_MASK 0xffffffff
#define RLC_GPU_IOV_UCODE_DATA__UCODE_DATA__SHIFT 0x0
#define RLC_GPU_IOV_SCRATCH_ADDR__ADDR_MASK 0x1ff
#define RLC_GPU_IOV_SCRATCH_ADDR__ADDR__SHIFT 0x0
#define RLC_GPU_IOV_SCRATCH_ADDR__RESERVED_MASK 0xfffffe00
#define RLC_GPU_IOV_SCRATCH_ADDR__RESERVED__SHIFT 0x9
#define RLC_GPU_IOV_SCRATCH_DATA__DATA_MASK 0xffffffff
#define RLC_GPU_IOV_SCRATCH_DATA__DATA__SHIFT 0x0
#define RLC_GPU_IOV_F32_CNTL__ENABLE_MASK 0x1
#define RLC_GPU_IOV_F32_CNTL__ENABLE__SHIFT 0x0
#define RLC_GPU_IOV_F32_CNTL__RESERVED_MASK 0xfffffffe
#define RLC_GPU_IOV_F32_CNTL__RESERVED__SHIFT 0x1
#define RLC_GPU_IOV_F32_RESET__RESET_MASK 0x1
#define RLC_GPU_IOV_F32_RESET__RESET__SHIFT 0x0
#define RLC_GPU_IOV_F32_RESET__RESERVED_MASK 0xfffffffe
#define RLC_GPU_IOV_F32_RESET__RESERVED__SHIFT 0x1
#define RLC_GPU_IOV_SDMA0_STATUS__PREEMPTED_MASK 0x1
#define RLC_GPU_IOV_SDMA0_STATUS__PREEMPTED__SHIFT 0x0
#define RLC_GPU_IOV_SDMA0_STATUS__RESERVED_MASK 0xfe
#define RLC_GPU_IOV_SDMA0_STATUS__RESERVED__SHIFT 0x1
#define RLC_GPU_IOV_SDMA0_STATUS__SAVED_MASK 0x100
#define RLC_GPU_IOV_SDMA0_STATUS__SAVED__SHIFT 0x8
#define RLC_GPU_IOV_SDMA0_STATUS__RESERVED1_MASK 0xe00
#define RLC_GPU_IOV_SDMA0_STATUS__RESERVED1__SHIFT 0x9
#define RLC_GPU_IOV_SDMA0_STATUS__RESTORED_MASK 0x1000
#define RLC_GPU_IOV_SDMA0_STATUS__RESTORED__SHIFT 0xc
#define RLC_GPU_IOV_SDMA0_STATUS__RESERVED2_MASK 0xffffe000
#define RLC_GPU_IOV_SDMA0_STATUS__RESERVED2__SHIFT 0xd
#define RLC_GPU_IOV_SDMA1_STATUS__PREEMPTED_MASK 0x1
#define RLC_GPU_IOV_SDMA1_STATUS__PREEMPTED__SHIFT 0x0
#define RLC_GPU_IOV_SDMA1_STATUS__RESERVED_MASK 0xfe
#define RLC_GPU_IOV_SDMA1_STATUS__RESERVED__SHIFT 0x1
#define RLC_GPU_IOV_SDMA1_STATUS__SAVED_MASK 0x100
#define RLC_GPU_IOV_SDMA1_STATUS__SAVED__SHIFT 0x8
#define RLC_GPU_IOV_SDMA1_STATUS__RESERVED1_MASK 0xe00
#define RLC_GPU_IOV_SDMA1_STATUS__RESERVED1__SHIFT 0x9
#define RLC_GPU_IOV_SDMA1_STATUS__RESTORED_MASK 0x1000
#define RLC_GPU_IOV_SDMA1_STATUS__RESTORED__SHIFT 0xc
#define RLC_GPU_IOV_SDMA1_STATUS__RESERVED2_MASK 0xffffe000
#define RLC_GPU_IOV_SDMA1_STATUS__RESERVED2__SHIFT 0xd
#define RLC_GPU_IOV_SMU_RESPONSE__RESP_MASK 0xffffffff
#define RLC_GPU_IOV_SMU_RESPONSE__RESP__SHIFT 0x0
#define RLC_GPU_IOV_VIRT_RESET_REQ__VF_FLR_MASK 0xffff
#define RLC_GPU_IOV_VIRT_RESET_REQ__VF_FLR__SHIFT 0x0
#define RLC_GPU_IOV_VIRT_RESET_REQ__RESERVED_MASK 0x7fff0000
#define RLC_GPU_IOV_VIRT_RESET_REQ__RESERVED__SHIFT 0x10
#define RLC_GPU_IOV_VIRT_RESET_REQ__SOFT_PF_FLR_MASK 0x80000000
#define RLC_GPU_IOV_VIRT_RESET_REQ__SOFT_PF_FLR__SHIFT 0x1f
#define RLC_GPU_IOV_RLC_RESPONSE__RESP_MASK 0xffffffff
#define RLC_GPU_IOV_RLC_RESPONSE__RESP__SHIFT 0x0
#define RLC_GPU_IOV_INT_DISABLE__DISABLE_MASK 0xffffffff
#define RLC_GPU_IOV_INT_DISABLE__DISABLE__SHIFT 0x0
#define RLC_GPU_IOV_INT_FORCE__FORCE_MASK 0xffffffff
#define RLC_GPU_IOV_INT_FORCE__FORCE__SHIFT 0x0
#define RLC_GPU_IOV_SDMA0_BUSY_STATUS__VM_BUSY_STATUS_MASK 0xffffffff
#define RLC_GPU_IOV_SDMA0_BUSY_STATUS__VM_BUSY_STATUS__SHIFT 0x0
#define RLC_GPU_IOV_SDMA1_BUSY_STATUS__VM_BUSY_STATUS_MASK 0xffffffff
#define RLC_GPU_IOV_SDMA1_BUSY_STATUS__VM_BUSY_STATUS__SHIFT 0x0
#define RLC_GPU_IOV_SCH_0__DATA_MASK 0xffffffff
#define RLC_GPU_IOV_SCH_0__DATA__SHIFT 0x0
#define RLC_GPU_IOV_SCH_1__DATA_MASK 0xffffffff
#define RLC_GPU_IOV_SCH_1__DATA__SHIFT 0x0
#define RLC_GPU_IOV_SCH_2__DATA_MASK 0xffffffff
#define RLC_GPU_IOV_SCH_2__DATA__SHIFT 0x0
#define RLC_GPU_IOV_SCH_3__DATA_MASK 0xffffffff
#define RLC_GPU_IOV_SCH_3__DATA__SHIFT 0x0
#define RLC_GPU_IOV_SCH_INT__interrupt_MASK 0xffffffff
#define RLC_GPU_IOV_SCH_INT__interrupt__SHIFT 0x0
#define SPI_PS_INPUT_CNTL_0__OFFSET_MASK 0x3f
#define SPI_PS_INPUT_CNTL_0__OFFSET__SHIFT 0x0
#define SPI_PS_INPUT_CNTL_0__DEFAULT_VAL_MASK 0x300
#define SPI_PS_INPUT_CNTL_0__DEFAULT_VAL__SHIFT 0x8
#define SPI_PS_INPUT_CNTL_0__FLAT_SHADE_MASK 0x400
#define SPI_PS_INPUT_CNTL_0__FLAT_SHADE__SHIFT 0xa
#define SPI_PS_INPUT_CNTL_0__CYL_WRAP_MASK 0x1e000
#define SPI_PS_INPUT_CNTL_0__CYL_WRAP__SHIFT 0xd
#define SPI_PS_INPUT_CNTL_0__PT_SPRITE_TEX_MASK 0x20000
#define SPI_PS_INPUT_CNTL_0__PT_SPRITE_TEX__SHIFT 0x11
#define SPI_PS_INPUT_CNTL_0__DUP_MASK 0x40000
#define SPI_PS_INPUT_CNTL_0__DUP__SHIFT 0x12
#define SPI_PS_INPUT_CNTL_0__FP16_INTERP_MODE_MASK 0x80000
#define SPI_PS_INPUT_CNTL_0__FP16_INTERP_MODE__SHIFT 0x13
#define SPI_PS_INPUT_CNTL_0__USE_DEFAULT_ATTR1_MASK 0x100000
#define SPI_PS_INPUT_CNTL_0__USE_DEFAULT_ATTR1__SHIFT 0x14
#define SPI_PS_INPUT_CNTL_0__DEFAULT_VAL_ATTR1_MASK 0x600000
#define SPI_PS_INPUT_CNTL_0__DEFAULT_VAL_ATTR1__SHIFT 0x15
#define SPI_PS_INPUT_CNTL_0__PT_SPRITE_TEX_ATTR1_MASK 0x800000
#define SPI_PS_INPUT_CNTL_0__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
#define SPI_PS_INPUT_CNTL_0__ATTR0_VALID_MASK 0x1000000
#define SPI_PS_INPUT_CNTL_0__ATTR0_VALID__SHIFT 0x18
#define SPI_PS_INPUT_CNTL_0__ATTR1_VALID_MASK 0x2000000
#define SPI_PS_INPUT_CNTL_0__ATTR1_VALID__SHIFT 0x19
#define SPI_PS_INPUT_CNTL_1__OFFSET_MASK 0x3f
#define SPI_PS_INPUT_CNTL_1__OFFSET__SHIFT 0x0
#define SPI_PS_INPUT_CNTL_1__DEFAULT_VAL_MASK 0x300
#define SPI_PS_INPUT_CNTL_1__DEFAULT_VAL__SHIFT 0x8
#define SPI_PS_INPUT_CNTL_1__FLAT_SHADE_MASK 0x400
#define SPI_PS_INPUT_CNTL_1__FLAT_SHADE__SHIFT 0xa
#define SPI_PS_INPUT_CNTL_1__CYL_WRAP_MASK 0x1e000
#define SPI_PS_INPUT_CNTL_1__CYL_WRAP__SHIFT 0xd
#define SPI_PS_INPUT_CNTL_1__PT_SPRITE_TEX_MASK 0x20000
#define SPI_PS_INPUT_CNTL_1__PT_SPRITE_TEX__SHIFT 0x11
#define SPI_PS_INPUT_CNTL_1__DUP_MASK 0x40000
#define SPI_PS_INPUT_CNTL_1__DUP__SHIFT 0x12
#define SPI_PS_INPUT_CNTL_1__FP16_INTERP_MODE_MASK 0x80000
#define SPI_PS_INPUT_CNTL_1__FP16_INTERP_MODE__SHIFT 0x13
#define SPI_PS_INPUT_CNTL_1__USE_DEFAULT_ATTR1_MASK 0x100000
#define SPI_PS_INPUT_CNTL_1__USE_DEFAULT_ATTR1__SHIFT 0x14
#define SPI_PS_INPUT_CNTL_1__DEFAULT_VAL_ATTR1_MASK 0x600000
#define SPI_PS_INPUT_CNTL_1__DEFAULT_VAL_ATTR1__SHIFT 0x15
#define SPI_PS_INPUT_CNTL_1__PT_SPRITE_TEX_ATTR1_MASK 0x800000
#define SPI_PS_INPUT_CNTL_1__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
#define SPI_PS_INPUT_CNTL_1__ATTR0_VALID_MASK 0x1000000
#define SPI_PS_INPUT_CNTL_1__ATTR0_VALID__SHIFT 0x18
#define SPI_PS_INPUT_CNTL_1__ATTR1_VALID_MASK 0x2000000
#define SPI_PS_INPUT_CNTL_1__ATTR1_VALID__SHIFT 0x19
#define SPI_PS_INPUT_CNTL_2__OFFSET_MASK 0x3f
#define SPI_PS_INPUT_CNTL_2__OFFSET__SHIFT 0x0
#define SPI_PS_INPUT_CNTL_2__DEFAULT_VAL_MASK 0x300
#define SPI_PS_INPUT_CNTL_2__DEFAULT_VAL__SHIFT 0x8
#define SPI_PS_INPUT_CNTL_2__FLAT_SHADE_MASK 0x400
#define SPI_PS_INPUT_CNTL_2__FLAT_SHADE__SHIFT 0xa
#define SPI_PS_INPUT_CNTL_2__CYL_WRAP_MASK 0x1e000
#define SPI_PS_INPUT_CNTL_2__CYL_WRAP__SHIFT 0xd
#define SPI_PS_INPUT_CNTL_2__PT_SPRITE_TEX_MASK 0x20000
#define SPI_PS_INPUT_CNTL_2__PT_SPRITE_TEX__SHIFT 0x11
#define SPI_PS_INPUT_CNTL_2__DUP_MASK 0x40000
#define SPI_PS_INPUT_CNTL_2__DUP__SHIFT 0x12
#define SPI_PS_INPUT_CNTL_2__FP16_INTERP_MODE_MASK 0x80000
#define SPI_PS_INPUT_CNTL_2__FP16_INTERP_MODE__SHIFT 0x13
#define SPI_PS_INPUT_CNTL_2__USE_DEFAULT_ATTR1_MASK 0x100000
#define SPI_PS_INPUT_CNTL_2__USE_DEFAULT_ATTR1__SHIFT 0x14
#define SPI_PS_INPUT_CNTL_2__DEFAULT_VAL_ATTR1_MASK 0x600000
#define SPI_PS_INPUT_CNTL_2__DEFAULT_VAL_ATTR1__SHIFT 0x15
#define SPI_PS_INPUT_CNTL_2__PT_SPRITE_TEX_ATTR1_MASK 0x800000
#define SPI_PS_INPUT_CNTL_2__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
#define SPI_PS_INPUT_CNTL_2__ATTR0_VALID_MASK 0x1000000
#define SPI_PS_INPUT_CNTL_2__ATTR0_VALID__SHIFT 0x18
#define SPI_PS_INPUT_CNTL_2__ATTR1_VALID_MASK 0x2000000
#define SPI_PS_INPUT_CNTL_2__ATTR1_VALID__SHIFT 0x19
#define SPI_PS_INPUT_CNTL_3__OFFSET_MASK 0x3f
#define SPI_PS_INPUT_CNTL_3__OFFSET__SHIFT 0x0
#define SPI_PS_INPUT_CNTL_3__DEFAULT_VAL_MASK 0x300
#define SPI_PS_INPUT_CNTL_3__DEFAULT_VAL__SHIFT 0x8
#define SPI_PS_INPUT_CNTL_3__FLAT_SHADE_MASK 0x400
#define SPI_PS_INPUT_CNTL_3__FLAT_SHADE__SHIFT 0xa
#define SPI_PS_INPUT_CNTL_3__CYL_WRAP_MASK 0x1e000
#define SPI_PS_INPUT_CNTL_3__CYL_WRAP__SHIFT 0xd
#define SPI_PS_INPUT_CNTL_3__PT_SPRITE_TEX_MASK 0x20000
#define SPI_PS_INPUT_CNTL_3__PT_SPRITE_TEX__SHIFT 0x11
#define SPI_PS_INPUT_CNTL_3__DUP_MASK 0x40000
#define SPI_PS_INPUT_CNTL_3__DUP__SHIFT 0x12
#define SPI_PS_INPUT_CNTL_3__FP16_INTERP_MODE_MASK 0x80000
#define SPI_PS_INPUT_CNTL_3__FP16_INTERP_MODE__SHIFT 0x13
#define SPI_PS_INPUT_CNTL_3__USE_DEFAULT_ATTR1_MASK 0x100000
#define SPI_PS_INPUT_CNTL_3__USE_DEFAULT_ATTR1__SHIFT 0x14
#define SPI_PS_INPUT_CNTL_3__DEFAULT_VAL_ATTR1_MASK 0x600000
#define SPI_PS_INPUT_CNTL_3__DEFAULT_VAL_ATTR1__SHIFT 0x15
#define SPI_PS_INPUT_CNTL_3__PT_SPRITE_TEX_ATTR1_MASK 0x800000
#define SPI_PS_INPUT_CNTL_3__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
#define SPI_PS_INPUT_CNTL_3__ATTR0_VALID_MASK 0x1000000
#define SPI_PS_INPUT_CNTL_3__ATTR0_VALID__SHIFT 0x18
#define SPI_PS_INPUT_CNTL_3__ATTR1_VALID_MASK 0x2000000
#define SPI_PS_INPUT_CNTL_3__ATTR1_VALID__SHIFT 0x19
#define SPI_PS_INPUT_CNTL_4__OFFSET_MASK 0x3f
#define SPI_PS_INPUT_CNTL_4__OFFSET__SHIFT 0x0
#define SPI_PS_INPUT_CNTL_4__DEFAULT_VAL_MASK 0x300
#define SPI_PS_INPUT_CNTL_4__DEFAULT_VAL__SHIFT 0x8
#define SPI_PS_INPUT_CNTL_4__FLAT_SHADE_MASK 0x400
#define SPI_PS_INPUT_CNTL_4__FLAT_SHADE__SHIFT 0xa
#define SPI_PS_INPUT_CNTL_4__CYL_WRAP_MASK 0x1e000
#define SPI_PS_INPUT_CNTL_4__CYL_WRAP__SHIFT 0xd
#define SPI_PS_INPUT_CNTL_4__PT_SPRITE_TEX_MASK 0x20000
#define SPI_PS_INPUT_CNTL_4__PT_SPRITE_TEX__SHIFT 0x11
#define SPI_PS_INPUT_CNTL_4__DUP_MASK 0x40000
#define SPI_PS_INPUT_CNTL_4__DUP__SHIFT 0x12
#define SPI_PS_INPUT_CNTL_4__FP16_INTERP_MODE_MASK 0x80000
#define SPI_PS_INPUT_CNTL_4__FP16_INTERP_MODE__SHIFT 0x13
#define SPI_PS_INPUT_CNTL_4__USE_DEFAULT_ATTR1_MASK 0x100000
#define SPI_PS_INPUT_CNTL_4__USE_DEFAULT_ATTR1__SHIFT 0x14
#define SPI_PS_INPUT_CNTL_4__DEFAULT_VAL_ATTR1_MASK 0x600000
#define SPI_PS_INPUT_CNTL_4__DEFAULT_VAL_ATTR1__SHIFT 0x15
#define SPI_PS_INPUT_CNTL_4__PT_SPRITE_TEX_ATTR1_MASK 0x800000
#define SPI_PS_INPUT_CNTL_4__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
#define SPI_PS_INPUT_CNTL_4__ATTR0_VALID_MASK 0x1000000
#define SPI_PS_INPUT_CNTL_4__ATTR0_VALID__SHIFT 0x18
#define SPI_PS_INPUT_CNTL_4__ATTR1_VALID_MASK 0x2000000
#define SPI_PS_INPUT_CNTL_4__ATTR1_VALID__SHIFT 0x19
#define SPI_PS_INPUT_CNTL_5__OFFSET_MASK 0x3f
#define SPI_PS_INPUT_CNTL_5__OFFSET__SHIFT 0x0
#define SPI_PS_INPUT_CNTL_5__DEFAULT_VAL_MASK 0x300
#define SPI_PS_INPUT_CNTL_5__DEFAULT_VAL__SHIFT 0x8
#define SPI_PS_INPUT_CNTL_5__FLAT_SHADE_MASK 0x400
#define SPI_PS_INPUT_CNTL_5__FLAT_SHADE__SHIFT 0xa
#define SPI_PS_INPUT_CNTL_5__CYL_WRAP_MASK 0x1e000
#define SPI_PS_INPUT_CNTL_5__CYL_WRAP__SHIFT 0xd
#define SPI_PS_INPUT_CNTL_5__PT_SPRITE_TEX_MASK 0x20000
#define SPI_PS_INPUT_CNTL_5__PT_SPRITE_TEX__SHIFT 0x11
#define SPI_PS_INPUT_CNTL_5__DUP_MASK 0x40000
#define SPI_PS_INPUT_CNTL_5__DUP__SHIFT 0x12
#define SPI_PS_INPUT_CNTL_5__FP16_INTERP_MODE_MASK 0x80000
#define SPI_PS_INPUT_CNTL_5__FP16_INTERP_MODE__SHIFT 0x13
#define SPI_PS_INPUT_CNTL_5__USE_DEFAULT_ATTR1_MASK 0x100000
#define SPI_PS_INPUT_CNTL_5__USE_DEFAULT_ATTR1__SHIFT 0x14
#define SPI_PS_INPUT_CNTL_5__DEFAULT_VAL_ATTR1_MASK 0x600000
#define SPI_PS_INPUT_CNTL_5__DEFAULT_VAL_ATTR1__SHIFT 0x15
#define SPI_PS_INPUT_CNTL_5__PT_SPRITE_TEX_ATTR1_MASK 0x800000
#define SPI_PS_INPUT_CNTL_5__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
#define SPI_PS_INPUT_CNTL_5__ATTR0_VALID_MASK 0x1000000
#define SPI_PS_INPUT_CNTL_5__ATTR0_VALID__SHIFT 0x18
#define SPI_PS_INPUT_CNTL_5__ATTR1_VALID_MASK 0x2000000
#define SPI_PS_INPUT_CNTL_5__ATTR1_VALID__SHIFT 0x19
#define SPI_PS_INPUT_CNTL_6__OFFSET_MASK 0x3f
#define SPI_PS_INPUT_CNTL_6__OFFSET__SHIFT 0x0
#define SPI_PS_INPUT_CNTL_6__DEFAULT_VAL_MASK 0x300
#define SPI_PS_INPUT_CNTL_6__DEFAULT_VAL__SHIFT 0x8
#define SPI_PS_INPUT_CNTL_6__FLAT_SHADE_MASK 0x400
#define SPI_PS_INPUT_CNTL_6__FLAT_SHADE__SHIFT 0xa
#define SPI_PS_INPUT_CNTL_6__CYL_WRAP_MASK 0x1e000
#define SPI_PS_INPUT_CNTL_6__CYL_WRAP__SHIFT 0xd
#define SPI_PS_INPUT_CNTL_6__PT_SPRITE_TEX_MASK 0x20000
#define SPI_PS_INPUT_CNTL_6__PT_SPRITE_TEX__SHIFT 0x11
#define SPI_PS_INPUT_CNTL_6__DUP_MASK 0x40000
#define SPI_PS_INPUT_CNTL_6__DUP__SHIFT 0x12
#define SPI_PS_INPUT_CNTL_6__FP16_INTERP_MODE_MASK 0x80000
#define SPI_PS_INPUT_CNTL_6__FP16_INTERP_MODE__SHIFT 0x13
#define SPI_PS_INPUT_CNTL_6__USE_DEFAULT_ATTR1_MASK 0x100000
#define SPI_PS_INPUT_CNTL_6__USE_DEFAULT_ATTR1__SHIFT 0x14
#define SPI_PS_INPUT_CNTL_6__DEFAULT_VAL_ATTR1_MASK 0x600000
#define SPI_PS_INPUT_CNTL_6__DEFAULT_VAL_ATTR1__SHIFT 0x15
#define SPI_PS_INPUT_CNTL_6__PT_SPRITE_TEX_ATTR1_MASK 0x800000
#define SPI_PS_INPUT_CNTL_6__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
#define SPI_PS_INPUT_CNTL_6__ATTR0_VALID_MASK 0x1000000
#define SPI_PS_INPUT_CNTL_6__ATTR0_VALID__SHIFT 0x18
#define SPI_PS_INPUT_CNTL_6__ATTR1_VALID_MASK 0x2000000
#define SPI_PS_INPUT_CNTL_6__ATTR1_VALID__SHIFT 0x19
#define SPI_PS_INPUT_CNTL_7__OFFSET_MASK 0x3f
#define SPI_PS_INPUT_CNTL_7__OFFSET__SHIFT 0x0
#define SPI_PS_INPUT_CNTL_7__DEFAULT_VAL_MASK 0x300
#define SPI_PS_INPUT_CNTL_7__DEFAULT_VAL__SHIFT 0x8
#define SPI_PS_INPUT_CNTL_7__FLAT_SHADE_MASK 0x400
#define SPI_PS_INPUT_CNTL_7__FLAT_SHADE__SHIFT 0xa
#define SPI_PS_INPUT_CNTL_7__CYL_WRAP_MASK 0x1e000
#define SPI_PS_INPUT_CNTL_7__CYL_WRAP__SHIFT 0xd
#define SPI_PS_INPUT_CNTL_7__PT_SPRITE_TEX_MASK 0x20000
#define SPI_PS_INPUT_CNTL_7__PT_SPRITE_TEX__SHIFT 0x11
#define SPI_PS_INPUT_CNTL_7__DUP_MASK 0x40000
#define SPI_PS_INPUT_CNTL_7__DUP__SHIFT 0x12
#define SPI_PS_INPUT_CNTL_7__FP16_INTERP_MODE_MASK 0x80000
#define SPI_PS_INPUT_CNTL_7__FP16_INTERP_MODE__SHIFT 0x13
#define SPI_PS_INPUT_CNTL_7__USE_DEFAULT_ATTR1_MASK 0x100000
#define SPI_PS_INPUT_CNTL_7__USE_DEFAULT_ATTR1__SHIFT 0x14
#define SPI_PS_INPUT_CNTL_7__DEFAULT_VAL_ATTR1_MASK 0x600000
#define SPI_PS_INPUT_CNTL_7__DEFAULT_VAL_ATTR1__SHIFT 0x15
#define SPI_PS_INPUT_CNTL_7__PT_SPRITE_TEX_ATTR1_MASK 0x800000
#define SPI_PS_INPUT_CNTL_7__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
#define SPI_PS_INPUT_CNTL_7__ATTR0_VALID_MASK 0x1000000
#define SPI_PS_INPUT_CNTL_7__ATTR0_VALID__SHIFT 0x18
#define SPI_PS_INPUT_CNTL_7__ATTR1_VALID_MASK 0x2000000
#define SPI_PS_INPUT_CNTL_7__ATTR1_VALID__SHIFT 0x19
#define SPI_PS_INPUT_CNTL_8__OFFSET_MASK 0x3f
#define SPI_PS_INPUT_CNTL_8__OFFSET__SHIFT 0x0
#define SPI_PS_INPUT_CNTL_8__DEFAULT_VAL_MASK 0x300
#define SPI_PS_INPUT_CNTL_8__DEFAULT_VAL__SHIFT 0x8
#define SPI_PS_INPUT_CNTL_8__FLAT_SHADE_MASK 0x400
#define SPI_PS_INPUT_CNTL_8__FLAT_SHADE__SHIFT 0xa
#define SPI_PS_INPUT_CNTL_8__CYL_WRAP_MASK 0x1e000
#define SPI_PS_INPUT_CNTL_8__CYL_WRAP__SHIFT 0xd
#define SPI_PS_INPUT_CNTL_8__PT_SPRITE_TEX_MASK 0x20000
#define SPI_PS_INPUT_CNTL_8__PT_SPRITE_TEX__SHIFT 0x11
#define SPI_PS_INPUT_CNTL_8__DUP_MASK 0x40000
#define SPI_PS_INPUT_CNTL_8__DUP__SHIFT 0x12
#define SPI_PS_INPUT_CNTL_8__FP16_INTERP_MODE_MASK 0x80000
#define SPI_PS_INPUT_CNTL_8__FP16_INTERP_MODE__SHIFT 0x13
#define SPI_PS_INPUT_CNTL_8__USE_DEFAULT_ATTR1_MASK 0x100000
#define SPI_PS_INPUT_CNTL_8__USE_DEFAULT_ATTR1__SHIFT 0x14
#define SPI_PS_INPUT_CNTL_8__DEFAULT_VAL_ATTR1_MASK 0x600000
#define SPI_PS_INPUT_CNTL_8__DEFAULT_VAL_ATTR1__SHIFT 0x15
#define SPI_PS_INPUT_CNTL_8__PT_SPRITE_TEX_ATTR1_MASK 0x800000
#define SPI_PS_INPUT_CNTL_8__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
#define SPI_PS_INPUT_CNTL_8__ATTR0_VALID_MASK 0x1000000
#define SPI_PS_INPUT_CNTL_8__ATTR0_VALID__SHIFT 0x18
#define SPI_PS_INPUT_CNTL_8__ATTR1_VALID_MASK 0x2000000
#define SPI_PS_INPUT_CNTL_8__ATTR1_VALID__SHIFT 0x19
#define SPI_PS_INPUT_CNTL_9__OFFSET_MASK 0x3f
#define SPI_PS_INPUT_CNTL_9__OFFSET__SHIFT 0x0
#define SPI_PS_INPUT_CNTL_9__DEFAULT_VAL_MASK 0x300
#define SPI_PS_INPUT_CNTL_9__DEFAULT_VAL__SHIFT 0x8
#define SPI_PS_INPUT_CNTL_9__FLAT_SHADE_MASK 0x400
#define SPI_PS_INPUT_CNTL_9__FLAT_SHADE__SHIFT 0xa
#define SPI_PS_INPUT_CNTL_9__CYL_WRAP_MASK 0x1e000
#define SPI_PS_INPUT_CNTL_9__CYL_WRAP__SHIFT 0xd
#define SPI_PS_INPUT_CNTL_9__PT_SPRITE_TEX_MASK 0x20000
#define SPI_PS_INPUT_CNTL_9__PT_SPRITE_TEX__SHIFT 0x11
#define SPI_PS_INPUT_CNTL_9__DUP_MASK 0x40000
#define SPI_PS_INPUT_CNTL_9__DUP__SHIFT 0x12
#define SPI_PS_INPUT_CNTL_9__FP16_INTERP_MODE_MASK 0x80000
#define SPI_PS_INPUT_CNTL_9__FP16_INTERP_MODE__SHIFT 0x13
#define SPI_PS_INPUT_CNTL_9__USE_DEFAULT_ATTR1_MASK 0x100000
#define SPI_PS_INPUT_CNTL_9__USE_DEFAULT_ATTR1__SHIFT 0x14
#define SPI_PS_INPUT_CNTL_9__DEFAULT_VAL_ATTR1_MASK 0x600000
#define SPI_PS_INPUT_CNTL_9__DEFAULT_VAL_ATTR1__SHIFT 0x15
#define SPI_PS_INPUT_CNTL_9__PT_SPRITE_TEX_ATTR1_MASK 0x800000
#define SPI_PS_INPUT_CNTL_9__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
#define SPI_PS_INPUT_CNTL_9__ATTR0_VALID_MASK 0x1000000
#define SPI_PS_INPUT_CNTL_9__ATTR0_VALID__SHIFT 0x18
#define SPI_PS_INPUT_CNTL_9__ATTR1_VALID_MASK 0x2000000
#define SPI_PS_INPUT_CNTL_9__ATTR1_VALID__SHIFT 0x19
#define SPI_PS_INPUT_CNTL_10__OFFSET_MASK 0x3f
#define SPI_PS_INPUT_CNTL_10__OFFSET__SHIFT 0x0
#define SPI_PS_INPUT_CNTL_10__DEFAULT_VAL_MASK 0x300
#define SPI_PS_INPUT_CNTL_10__DEFAULT_VAL__SHIFT 0x8
#define SPI_PS_INPUT_CNTL_10__FLAT_SHADE_MASK 0x400
#define SPI_PS_INPUT_CNTL_10__FLAT_SHADE__SHIFT 0xa
#define SPI_PS_INPUT_CNTL_10__CYL_WRAP_MASK 0x1e000
#define SPI_PS_INPUT_CNTL_10__CYL_WRAP__SHIFT 0xd
#define SPI_PS_INPUT_CNTL_10__PT_SPRITE_TEX_MASK 0x20000
#define SPI_PS_INPUT_CNTL_10__PT_SPRITE_TEX__SHIFT 0x11
#define SPI_PS_INPUT_CNTL_10__DUP_MASK 0x40000
#define SPI_PS_INPUT_CNTL_10__DUP__SHIFT 0x12
#define SPI_PS_INPUT_CNTL_10__FP16_INTERP_MODE_MASK 0x80000
#define SPI_PS_INPUT_CNTL_10__FP16_INTERP_MODE__SHIFT 0x13
#define SPI_PS_INPUT_CNTL_10__USE_DEFAULT_ATTR1_MASK 0x100000
#define SPI_PS_INPUT_CNTL_10__USE_DEFAULT_ATTR1__SHIFT 0x14
#define SPI_PS_INPUT_CNTL_10__DEFAULT_VAL_ATTR1_MASK 0x600000
#define SPI_PS_INPUT_CNTL_10__DEFAULT_VAL_ATTR1__SHIFT 0x15
#define SPI_PS_INPUT_CNTL_10__PT_SPRITE_TEX_ATTR1_MASK 0x800000
#define SPI_PS_INPUT_CNTL_10__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
#define SPI_PS_INPUT_CNTL_10__ATTR0_VALID_MASK 0x1000000
#define SPI_PS_INPUT_CNTL_10__ATTR0_VALID__SHIFT 0x18
#define SPI_PS_INPUT_CNTL_10__ATTR1_VALID_MASK 0x2000000
#define SPI_PS_INPUT_CNTL_10__ATTR1_VALID__SHIFT 0x19
#define SPI_PS_INPUT_CNTL_11__OFFSET_MASK 0x3f
#define SPI_PS_INPUT_CNTL_11__OFFSET__SHIFT 0x0
#define SPI_PS_INPUT_CNTL_11__DEFAULT_VAL_MASK 0x300
#define SPI_PS_INPUT_CNTL_11__DEFAULT_VAL__SHIFT 0x8
#define SPI_PS_INPUT_CNTL_11__FLAT_SHADE_MASK 0x400
#define SPI_PS_INPUT_CNTL_11__FLAT_SHADE__SHIFT 0xa
#define SPI_PS_INPUT_CNTL_11__CYL_WRAP_MASK 0x1e000
#define SPI_PS_INPUT_CNTL_11__CYL_WRAP__SHIFT 0xd
#define SPI_PS_INPUT_CNTL_11__PT_SPRITE_TEX_MASK 0x20000
#define SPI_PS_INPUT_CNTL_11__PT_SPRITE_TEX__SHIFT 0x11
#define SPI_PS_INPUT_CNTL_11__DUP_MASK 0x40000
#define SPI_PS_INPUT_CNTL_11__DUP__SHIFT 0x12
#define SPI_PS_INPUT_CNTL_11__FP16_INTERP_MODE_MASK 0x80000
#define SPI_PS_INPUT_CNTL_11__FP16_INTERP_MODE__SHIFT 0x13
#define SPI_PS_INPUT_CNTL_11__USE_DEFAULT_ATTR1_MASK 0x100000
#define SPI_PS_INPUT_CNTL_11__USE_DEFAULT_ATTR1__SHIFT 0x14
#define SPI_PS_INPUT_CNTL_11__DEFAULT_VAL_ATTR1_MASK 0x600000
#define SPI_PS_INPUT_CNTL_11__DEFAULT_VAL_ATTR1__SHIFT 0x15
#define SPI_PS_INPUT_CNTL_11__PT_SPRITE_TEX_ATTR1_MASK 0x800000
#define SPI_PS_INPUT_CNTL_11__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
#define SPI_PS_INPUT_CNTL_11__ATTR0_VALID_MASK 0x1000000
#define SPI_PS_INPUT_CNTL_11__ATTR0_VALID__SHIFT 0x18
#define SPI_PS_INPUT_CNTL_11__ATTR1_VALID_MASK 0x2000000
#define SPI_PS_INPUT_CNTL_11__ATTR1_VALID__SHIFT 0x19
#define SPI_PS_INPUT_CNTL_12__OFFSET_MASK 0x3f
#define SPI_PS_INPUT_CNTL_12__OFFSET__SHIFT 0x0
#define SPI_PS_INPUT_CNTL_12__DEFAULT_VAL_MASK 0x300
#define SPI_PS_INPUT_CNTL_12__DEFAULT_VAL__SHIFT 0x8
#define SPI_PS_INPUT_CNTL_12__FLAT_SHADE_MASK 0x400
#define SPI_PS_INPUT_CNTL_12__FLAT_SHADE__SHIFT 0xa
#define SPI_PS_INPUT_CNTL_12__CYL_WRAP_MASK 0x1e000
#define SPI_PS_INPUT_CNTL_12__CYL_WRAP__SHIFT 0xd
#define SPI_PS_INPUT_CNTL_12__PT_SPRITE_TEX_MASK 0x20000
#define SPI_PS_INPUT_CNTL_12__PT_SPRITE_TEX__SHIFT 0x11
#define SPI_PS_INPUT_CNTL_12__DUP_MASK 0x40000
#define SPI_PS_INPUT_CNTL_12__DUP__SHIFT 0x12
#define SPI_PS_INPUT_CNTL_12__FP16_INTERP_MODE_MASK 0x80000
#define SPI_PS_INPUT_CNTL_12__FP16_INTERP_MODE__SHIFT 0x13
#define SPI_PS_INPUT_CNTL_12__USE_DEFAULT_ATTR1_MASK 0x100000
#define SPI_PS_INPUT_CNTL_12__USE_DEFAULT_ATTR1__SHIFT 0x14
#define SPI_PS_INPUT_CNTL_12__DEFAULT_VAL_ATTR1_MASK 0x600000
#define SPI_PS_INPUT_CNTL_12__DEFAULT_VAL_ATTR1__SHIFT 0x15
#define SPI_PS_INPUT_CNTL_12__PT_SPRITE_TEX_ATTR1_MASK 0x800000
#define SPI_PS_INPUT_CNTL_12__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
#define SPI_PS_INPUT_CNTL_12__ATTR0_VALID_MASK 0x1000000
#define SPI_PS_INPUT_CNTL_12__ATTR0_VALID__SHIFT 0x18
#define SPI_PS_INPUT_CNTL_12__ATTR1_VALID_MASK 0x2000000
#define SPI_PS_INPUT_CNTL_12__ATTR1_VALID__SHIFT 0x19
#define SPI_PS_INPUT_CNTL_13__OFFSET_MASK 0x3f
#define SPI_PS_INPUT_CNTL_13__OFFSET__SHIFT 0x0
#define SPI_PS_INPUT_CNTL_13__DEFAULT_VAL_MASK 0x300
#define SPI_PS_INPUT_CNTL_13__DEFAULT_VAL__SHIFT 0x8
#define SPI_PS_INPUT_CNTL_13__FLAT_SHADE_MASK 0x400
#define SPI_PS_INPUT_CNTL_13__FLAT_SHADE__SHIFT 0xa
#define SPI_PS_INPUT_CNTL_13__CYL_WRAP_MASK 0x1e000
#define SPI_PS_INPUT_CNTL_13__CYL_WRAP__SHIFT 0xd
#define SPI_PS_INPUT_CNTL_13__PT_SPRITE_TEX_MASK 0x20000
#define SPI_PS_INPUT_CNTL_13__PT_SPRITE_TEX__SHIFT 0x11
#define SPI_PS_INPUT_CNTL_13__DUP_MASK 0x40000
#define SPI_PS_INPUT_CNTL_13__DUP__SHIFT 0x12
#define SPI_PS_INPUT_CNTL_13__FP16_INTERP_MODE_MASK 0x80000
#define SPI_PS_INPUT_CNTL_13__FP16_INTERP_MODE__SHIFT 0x13
#define SPI_PS_INPUT_CNTL_13__USE_DEFAULT_ATTR1_MASK 0x100000
#define SPI_PS_INPUT_CNTL_13__USE_DEFAULT_ATTR1__SHIFT 0x14
#define SPI_PS_INPUT_CNTL_13__DEFAULT_VAL_ATTR1_MASK 0x600000
#define SPI_PS_INPUT_CNTL_13__DEFAULT_VAL_ATTR1__SHIFT 0x15
#define SPI_PS_INPUT_CNTL_13__PT_SPRITE_TEX_ATTR1_MASK 0x800000
#define SPI_PS_INPUT_CNTL_13__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
#define SPI_PS_INPUT_CNTL_13__ATTR0_VALID_MASK 0x1000000
#define SPI_PS_INPUT_CNTL_13__ATTR0_VALID__SHIFT 0x18
#define SPI_PS_INPUT_CNTL_13__ATTR1_VALID_MASK 0x2000000
#define SPI_PS_INPUT_CNTL_13__ATTR1_VALID__SHIFT 0x19
#define SPI_PS_INPUT_CNTL_14__OFFSET_MASK 0x3f
#define SPI_PS_INPUT_CNTL_14__OFFSET__SHIFT 0x0
#define SPI_PS_INPUT_CNTL_14__DEFAULT_VAL_MASK 0x300
#define SPI_PS_INPUT_CNTL_14__DEFAULT_VAL__SHIFT 0x8
#define SPI_PS_INPUT_CNTL_14__FLAT_SHADE_MASK 0x400
#define SPI_PS_INPUT_CNTL_14__FLAT_SHADE__SHIFT 0xa
#define SPI_PS_INPUT_CNTL_14__CYL_WRAP_MASK 0x1e000
#define SPI_PS_INPUT_CNTL_14__CYL_WRAP__SHIFT 0xd
#define SPI_PS_INPUT_CNTL_14__PT_SPRITE_TEX_MASK 0x20000
#define SPI_PS_INPUT_CNTL_14__PT_SPRITE_TEX__SHIFT 0x11
#define SPI_PS_INPUT_CNTL_14__DUP_MASK 0x40000
#define SPI_PS_INPUT_CNTL_14__DUP__SHIFT 0x12
#define SPI_PS_INPUT_CNTL_14__FP16_INTERP_MODE_MASK 0x80000
#define SPI_PS_INPUT_CNTL_14__FP16_INTERP_MODE__SHIFT 0x13
#define SPI_PS_INPUT_CNTL_14__USE_DEFAULT_ATTR1_MASK 0x100000
#define SPI_PS_INPUT_CNTL_14__USE_DEFAULT_ATTR1__SHIFT 0x14
#define SPI_PS_INPUT_CNTL_14__DEFAULT_VAL_ATTR1_MASK 0x600000
#define SPI_PS_INPUT_CNTL_14__DEFAULT_VAL_ATTR1__SHIFT 0x15
#define SPI_PS_INPUT_CNTL_14__PT_SPRITE_TEX_ATTR1_MASK 0x800000
#define SPI_PS_INPUT_CNTL_14__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
#define SPI_PS_INPUT_CNTL_14__ATTR0_VALID_MASK 0x1000000
#define SPI_PS_INPUT_CNTL_14__ATTR0_VALID__SHIFT 0x18
#define SPI_PS_INPUT_CNTL_14__ATTR1_VALID_MASK 0x2000000
#define SPI_PS_INPUT_CNTL_14__ATTR1_VALID__SHIFT 0x19
#define SPI_PS_INPUT_CNTL_15__OFFSET_MASK 0x3f
#define SPI_PS_INPUT_CNTL_15__OFFSET__SHIFT 0x0
#define SPI_PS_INPUT_CNTL_15__DEFAULT_VAL_MASK 0x300
#define SPI_PS_INPUT_CNTL_15__DEFAULT_VAL__SHIFT 0x8
#define SPI_PS_INPUT_CNTL_15__FLAT_SHADE_MASK 0x400
#define SPI_PS_INPUT_CNTL_15__FLAT_SHADE__SHIFT 0xa
#define SPI_PS_INPUT_CNTL_15__CYL_WRAP_MASK 0x1e000
#define SPI_PS_INPUT_CNTL_15__CYL_WRAP__SHIFT 0xd
#define SPI_PS_INPUT_CNTL_15__PT_SPRITE_TEX_MASK 0x20000
#define SPI_PS_INPUT_CNTL_15__PT_SPRITE_TEX__SHIFT 0x11
#define SPI_PS_INPUT_CNTL_15__DUP_MASK 0x40000
#define SPI_PS_INPUT_CNTL_15__DUP__SHIFT 0x12
#define SPI_PS_INPUT_CNTL_15__FP16_INTERP_MODE_MASK 0x80000
#define SPI_PS_INPUT_CNTL_15__FP16_INTERP_MODE__SHIFT 0x13
#define SPI_PS_INPUT_CNTL_15__USE_DEFAULT_ATTR1_MASK 0x100000
#define SPI_PS_INPUT_CNTL_15__USE_DEFAULT_ATTR1__SHIFT 0x14
#define SPI_PS_INPUT_CNTL_15__DEFAULT_VAL_ATTR1_MASK 0x600000
#define SPI_PS_INPUT_CNTL_15__DEFAULT_VAL_ATTR1__SHIFT 0x15
#define SPI_PS_INPUT_CNTL_15__PT_SPRITE_TEX_ATTR1_MASK 0x800000
#define SPI_PS_INPUT_CNTL_15__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
#define SPI_PS_INPUT_CNTL_15__ATTR0_VALID_MASK 0x1000000
#define SPI_PS_INPUT_CNTL_15__ATTR0_VALID__SHIFT 0x18
#define SPI_PS_INPUT_CNTL_15__ATTR1_VALID_MASK 0x2000000
#define SPI_PS_INPUT_CNTL_15__ATTR1_VALID__SHIFT 0x19
#define SPI_PS_INPUT_CNTL_16__OFFSET_MASK 0x3f
#define SPI_PS_INPUT_CNTL_16__OFFSET__SHIFT 0x0
#define SPI_PS_INPUT_CNTL_16__DEFAULT_VAL_MASK 0x300
#define SPI_PS_INPUT_CNTL_16__DEFAULT_VAL__SHIFT 0x8
#define SPI_PS_INPUT_CNTL_16__FLAT_SHADE_MASK 0x400
#define SPI_PS_INPUT_CNTL_16__FLAT_SHADE__SHIFT 0xa
#define SPI_PS_INPUT_CNTL_16__CYL_WRAP_MASK 0x1e000
#define SPI_PS_INPUT_CNTL_16__CYL_WRAP__SHIFT 0xd
#define SPI_PS_INPUT_CNTL_16__PT_SPRITE_TEX_MASK 0x20000
#define SPI_PS_INPUT_CNTL_16__PT_SPRITE_TEX__SHIFT 0x11
#define SPI_PS_INPUT_CNTL_16__DUP_MASK 0x40000
#define SPI_PS_INPUT_CNTL_16__DUP__SHIFT 0x12
#define SPI_PS_INPUT_CNTL_16__FP16_INTERP_MODE_MASK 0x80000
#define SPI_PS_INPUT_CNTL_16__FP16_INTERP_MODE__SHIFT 0x13
#define SPI_PS_INPUT_CNTL_16__USE_DEFAULT_ATTR1_MASK 0x100000
#define SPI_PS_INPUT_CNTL_16__USE_DEFAULT_ATTR1__SHIFT 0x14
#define SPI_PS_INPUT_CNTL_16__DEFAULT_VAL_ATTR1_MASK 0x600000
#define SPI_PS_INPUT_CNTL_16__DEFAULT_VAL_ATTR1__SHIFT 0x15
#define SPI_PS_INPUT_CNTL_16__PT_SPRITE_TEX_ATTR1_MASK 0x800000
#define SPI_PS_INPUT_CNTL_16__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
#define SPI_PS_INPUT_CNTL_16__ATTR0_VALID_MASK 0x1000000
#define SPI_PS_INPUT_CNTL_16__ATTR0_VALID__SHIFT 0x18
#define SPI_PS_INPUT_CNTL_16__ATTR1_VALID_MASK 0x2000000
#define SPI_PS_INPUT_CNTL_16__ATTR1_VALID__SHIFT 0x19
#define SPI_PS_INPUT_CNTL_17__OFFSET_MASK 0x3f
#define SPI_PS_INPUT_CNTL_17__OFFSET__SHIFT 0x0
#define SPI_PS_INPUT_CNTL_17__DEFAULT_VAL_MASK 0x300
#define SPI_PS_INPUT_CNTL_17__DEFAULT_VAL__SHIFT 0x8
#define SPI_PS_INPUT_CNTL_17__FLAT_SHADE_MASK 0x400
#define SPI_PS_INPUT_CNTL_17__FLAT_SHADE__SHIFT 0xa
#define SPI_PS_INPUT_CNTL_17__CYL_WRAP_MASK 0x1e000
#define SPI_PS_INPUT_CNTL_17__CYL_WRAP__SHIFT 0xd
#define SPI_PS_INPUT_CNTL_17__PT_SPRITE_TEX_MASK 0x20000
#define SPI_PS_INPUT_CNTL_17__PT_SPRITE_TEX__SHIFT 0x11
#define SPI_PS_INPUT_CNTL_17__DUP_MASK 0x40000
#define SPI_PS_INPUT_CNTL_17__DUP__SHIFT 0x12
#define SPI_PS_INPUT_CNTL_17__FP16_INTERP_MODE_MASK 0x80000
#define SPI_PS_INPUT_CNTL_17__FP16_INTERP_MODE__SHIFT 0x13
#define SPI_PS_INPUT_CNTL_17__USE_DEFAULT_ATTR1_MASK 0x100000
#define SPI_PS_INPUT_CNTL_17__USE_DEFAULT_ATTR1__SHIFT 0x14
#define SPI_PS_INPUT_CNTL_17__DEFAULT_VAL_ATTR1_MASK 0x600000
#define SPI_PS_INPUT_CNTL_17__DEFAULT_VAL_ATTR1__SHIFT 0x15
#define SPI_PS_INPUT_CNTL_17__PT_SPRITE_TEX_ATTR1_MASK 0x800000
#define SPI_PS_INPUT_CNTL_17__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
#define SPI_PS_INPUT_CNTL_17__ATTR0_VALID_MASK 0x1000000
#define SPI_PS_INPUT_CNTL_17__ATTR0_VALID__SHIFT 0x18
#define SPI_PS_INPUT_CNTL_17__ATTR1_VALID_MASK 0x2000000
#define SPI_PS_INPUT_CNTL_17__ATTR1_VALID__SHIFT 0x19
#define SPI_PS_INPUT_CNTL_18__OFFSET_MASK 0x3f
#define SPI_PS_INPUT_CNTL_18__OFFSET__SHIFT 0x0
#define SPI_PS_INPUT_CNTL_18__DEFAULT_VAL_MASK 0x300
#define SPI_PS_INPUT_CNTL_18__DEFAULT_VAL__SHIFT 0x8
#define SPI_PS_INPUT_CNTL_18__FLAT_SHADE_MASK 0x400
#define SPI_PS_INPUT_CNTL_18__FLAT_SHADE__SHIFT 0xa
#define SPI_PS_INPUT_CNTL_18__CYL_WRAP_MASK 0x1e000
#define SPI_PS_INPUT_CNTL_18__CYL_WRAP__SHIFT 0xd
#define SPI_PS_INPUT_CNTL_18__PT_SPRITE_TEX_MASK 0x20000
#define SPI_PS_INPUT_CNTL_18__PT_SPRITE_TEX__SHIFT 0x11
#define SPI_PS_INPUT_CNTL_18__DUP_MASK 0x40000
#define SPI_PS_INPUT_CNTL_18__DUP__SHIFT 0x12
#define SPI_PS_INPUT_CNTL_18__FP16_INTERP_MODE_MASK 0x80000
#define SPI_PS_INPUT_CNTL_18__FP16_INTERP_MODE__SHIFT 0x13
#define SPI_PS_INPUT_CNTL_18__USE_DEFAULT_ATTR1_MASK 0x100000
#define SPI_PS_INPUT_CNTL_18__USE_DEFAULT_ATTR1__SHIFT 0x14
#define SPI_PS_INPUT_CNTL_18__DEFAULT_VAL_ATTR1_MASK 0x600000
#define SPI_PS_INPUT_CNTL_18__DEFAULT_VAL_ATTR1__SHIFT 0x15
#define SPI_PS_INPUT_CNTL_18__PT_SPRITE_TEX_ATTR1_MASK 0x800000
#define SPI_PS_INPUT_CNTL_18__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
#define SPI_PS_INPUT_CNTL_18__ATTR0_VALID_MASK 0x1000000
#define SPI_PS_INPUT_CNTL_18__ATTR0_VALID__SHIFT 0x18
#define SPI_PS_INPUT_CNTL_18__ATTR1_VALID_MASK 0x2000000
#define SPI_PS_INPUT_CNTL_18__ATTR1_VALID__SHIFT 0x19
#define SPI_PS_INPUT_CNTL_19__OFFSET_MASK 0x3f
#define SPI_PS_INPUT_CNTL_19__OFFSET__SHIFT 0x0
#define SPI_PS_INPUT_CNTL_19__DEFAULT_VAL_MASK 0x300
#define SPI_PS_INPUT_CNTL_19__DEFAULT_VAL__SHIFT 0x8
#define SPI_PS_INPUT_CNTL_19__FLAT_SHADE_MASK 0x400
#define SPI_PS_INPUT_CNTL_19__FLAT_SHADE__SHIFT 0xa
#define SPI_PS_INPUT_CNTL_19__CYL_WRAP_MASK 0x1e000
#define SPI_PS_INPUT_CNTL_19__CYL_WRAP__SHIFT 0xd
#define SPI_PS_INPUT_CNTL_19__PT_SPRITE_TEX_MASK 0x20000
#define SPI_PS_INPUT_CNTL_19__PT_SPRITE_TEX__SHIFT 0x11
#define SPI_PS_INPUT_CNTL_19__DUP_MASK 0x40000
#define SPI_PS_INPUT_CNTL_19__DUP__SHIFT 0x12
#define SPI_PS_INPUT_CNTL_19__FP16_INTERP_MODE_MASK 0x80000
#define SPI_PS_INPUT_CNTL_19__FP16_INTERP_MODE__SHIFT 0x13
#define SPI_PS_INPUT_CNTL_19__USE_DEFAULT_ATTR1_MASK 0x100000
#define SPI_PS_INPUT_CNTL_19__USE_DEFAULT_ATTR1__SHIFT 0x14
#define SPI_PS_INPUT_CNTL_19__DEFAULT_VAL_ATTR1_MASK 0x600000
#define SPI_PS_INPUT_CNTL_19__DEFAULT_VAL_ATTR1__SHIFT 0x15
#define SPI_PS_INPUT_CNTL_19__PT_SPRITE_TEX_ATTR1_MASK 0x800000
#define SPI_PS_INPUT_CNTL_19__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
#define SPI_PS_INPUT_CNTL_19__ATTR0_VALID_MASK 0x1000000
#define SPI_PS_INPUT_CNTL_19__ATTR0_VALID__SHIFT 0x18
#define SPI_PS_INPUT_CNTL_19__ATTR1_VALID_MASK 0x2000000
#define SPI_PS_INPUT_CNTL_19__ATTR1_VALID__SHIFT 0x19
#define SPI_PS_INPUT_CNTL_20__OFFSET_MASK 0x3f
#define SPI_PS_INPUT_CNTL_20__OFFSET__SHIFT 0x0
#define SPI_PS_INPUT_CNTL_20__DEFAULT_VAL_MASK 0x300
#define SPI_PS_INPUT_CNTL_20__DEFAULT_VAL__SHIFT 0x8
#define SPI_PS_INPUT_CNTL_20__FLAT_SHADE_MASK 0x400
#define SPI_PS_INPUT_CNTL_20__FLAT_SHADE__SHIFT 0xa
#define SPI_PS_INPUT_CNTL_20__DUP_MASK 0x40000
#define SPI_PS_INPUT_CNTL_20__DUP__SHIFT 0x12
#define SPI_PS_INPUT_CNTL_20__FP16_INTERP_MODE_MASK 0x80000
#define SPI_PS_INPUT_CNTL_20__FP16_INTERP_MODE__SHIFT 0x13
#define SPI_PS_INPUT_CNTL_20__USE_DEFAULT_ATTR1_MASK 0x100000
#define SPI_PS_INPUT_CNTL_20__USE_DEFAULT_ATTR1__SHIFT 0x14
#define SPI_PS_INPUT_CNTL_20__DEFAULT_VAL_ATTR1_MASK 0x600000
#define SPI_PS_INPUT_CNTL_20__DEFAULT_VAL_ATTR1__SHIFT 0x15
#define SPI_PS_INPUT_CNTL_20__ATTR0_VALID_MASK 0x1000000
#define SPI_PS_INPUT_CNTL_20__ATTR0_VALID__SHIFT 0x18
#define SPI_PS_INPUT_CNTL_20__ATTR1_VALID_MASK 0x2000000
#define SPI_PS_INPUT_CNTL_20__ATTR1_VALID__SHIFT 0x19
#define SPI_PS_INPUT_CNTL_21__OFFSET_MASK 0x3f
#define SPI_PS_INPUT_CNTL_21__OFFSET__SHIFT 0x0
#define SPI_PS_INPUT_CNTL_21__DEFAULT_VAL_MASK 0x300
#define SPI_PS_INPUT_CNTL_21__DEFAULT_VAL__SHIFT 0x8
#define SPI_PS_INPUT_CNTL_21__FLAT_SHADE_MASK 0x400
#define SPI_PS_INPUT_CNTL_21__FLAT_SHADE__SHIFT 0xa
#define SPI_PS_INPUT_CNTL_21__DUP_MASK 0x40000
#define SPI_PS_INPUT_CNTL_21__DUP__SHIFT 0x12
#define SPI_PS_INPUT_CNTL_21__FP16_INTERP_MODE_MASK 0x80000
#define SPI_PS_INPUT_CNTL_21__FP16_INTERP_MODE__SHIFT 0x13
#define SPI_PS_INPUT_CNTL_21__USE_DEFAULT_ATTR1_MASK 0x100000
#define SPI_PS_INPUT_CNTL_21__USE_DEFAULT_ATTR1__SHIFT 0x14
#define SPI_PS_INPUT_CNTL_21__DEFAULT_VAL_ATTR1_MASK 0x600000
#define SPI_PS_INPUT_CNTL_21__DEFAULT_VAL_ATTR1__SHIFT 0x15
#define SPI_PS_INPUT_CNTL_21__ATTR0_VALID_MASK 0x1000000
#define SPI_PS_INPUT_CNTL_21__ATTR0_VALID__SHIFT 0x18
#define SPI_PS_INPUT_CNTL_21__ATTR1_VALID_MASK 0x2000000
#define SPI_PS_INPUT_CNTL_21__ATTR1_VALID__SHIFT 0x19
#define SPI_PS_INPUT_CNTL_22__OFFSET_MASK 0x3f
#define SPI_PS_INPUT_CNTL_22__OFFSET__SHIFT 0x0
#define SPI_PS_INPUT_CNTL_22__DEFAULT_VAL_MASK 0x300
#define SPI_PS_INPUT_CNTL_22__DEFAULT_VAL__SHIFT 0x8
#define SPI_PS_INPUT_CNTL_22__FLAT_SHADE_MASK 0x400
#define SPI_PS_INPUT_CNTL_22__FLAT_SHADE__SHIFT 0xa
#define SPI_PS_INPUT_CNTL_22__DUP_MASK 0x40000
#define SPI_PS_INPUT_CNTL_22__DUP__SHIFT 0x12
#define SPI_PS_INPUT_CNTL_22__FP16_INTERP_MODE_MASK 0x80000
#define SPI_PS_INPUT_CNTL_22__FP16_INTERP_MODE__SHIFT 0x13
#define SPI_PS_INPUT_CNTL_22__USE_DEFAULT_ATTR1_MASK 0x100000
#define SPI_PS_INPUT_CNTL_22__USE_DEFAULT_ATTR1__SHIFT 0x14
#define SPI_PS_INPUT_CNTL_22__DEFAULT_VAL_ATTR1_MASK 0x600000
#define SPI_PS_INPUT_CNTL_22__DEFAULT_VAL_ATTR1__SHIFT 0x15
#define SPI_PS_INPUT_CNTL_22__ATTR0_VALID_MASK 0x1000000
#define SPI_PS_INPUT_CNTL_22__ATTR0_VALID__SHIFT 0x18
#define SPI_PS_INPUT_CNTL_22__ATTR1_VALID_MASK 0x2000000
#define SPI_PS_INPUT_CNTL_22__ATTR1_VALID__SHIFT 0x19
#define SPI_PS_INPUT_CNTL_23__OFFSET_MASK 0x3f
#define SPI_PS_INPUT_CNTL_23__OFFSET__SHIFT 0x0
#define SPI_PS_INPUT_CNTL_23__DEFAULT_VAL_MASK 0x300
#define SPI_PS_INPUT_CNTL_23__DEFAULT_VAL__SHIFT 0x8
#define SPI_PS_INPUT_CNTL_23__FLAT_SHADE_MASK 0x400
#define SPI_PS_INPUT_CNTL_23__FLAT_SHADE__SHIFT 0xa
#define SPI_PS_INPUT_CNTL_23__DUP_MASK 0x40000
#define SPI_PS_INPUT_CNTL_23__DUP__SHIFT 0x12
#define SPI_PS_INPUT_CNTL_23__FP16_INTERP_MODE_MASK 0x80000
#define SPI_PS_INPUT_CNTL_23__FP16_INTERP_MODE__SHIFT 0x13
#define SPI_PS_INPUT_CNTL_23__USE_DEFAULT_ATTR1_MASK 0x100000
#define SPI_PS_INPUT_CNTL_23__USE_DEFAULT_ATTR1__SHIFT 0x14
#define SPI_PS_INPUT_CNTL_23__DEFAULT_VAL_ATTR1_MASK 0x600000
#define SPI_PS_INPUT_CNTL_23__DEFAULT_VAL_ATTR1__SHIFT 0x15
#define SPI_PS_INPUT_CNTL_23__ATTR0_VALID_MASK 0x1000000
#define SPI_PS_INPUT_CNTL_23__ATTR0_VALID__SHIFT 0x18
#define SPI_PS_INPUT_CNTL_23__ATTR1_VALID_MASK 0x2000000
#define SPI_PS_INPUT_CNTL_23__ATTR1_VALID__SHIFT 0x19
#define SPI_PS_INPUT_CNTL_24__OFFSET_MASK 0x3f
#define SPI_PS_INPUT_CNTL_24__OFFSET__SHIFT 0x0
#define SPI_PS_INPUT_CNTL_24__DEFAULT_VAL_MASK 0x300
#define SPI_PS_INPUT_CNTL_24__DEFAULT_VAL__SHIFT 0x8
#define SPI_PS_INPUT_CNTL_24__FLAT_SHADE_MASK 0x400
#define SPI_PS_INPUT_CNTL_24__FLAT_SHADE__SHIFT 0xa
#define SPI_PS_INPUT_CNTL_24__DUP_MASK 0x40000
#define SPI_PS_INPUT_CNTL_24__DUP__SHIFT 0x12
#define SPI_PS_INPUT_CNTL_24__FP16_INTERP_MODE_MASK 0x80000
#define SPI_PS_INPUT_CNTL_24__FP16_INTERP_MODE__SHIFT 0x13
#define SPI_PS_INPUT_CNTL_24__USE_DEFAULT_ATTR1_MASK 0x100000
#define SPI_PS_INPUT_CNTL_24__USE_DEFAULT_ATTR1__SHIFT 0x14
#define SPI_PS_INPUT_CNTL_24__DEFAULT_VAL_ATTR1_MASK 0x600000
#define SPI_PS_INPUT_CNTL_24__DEFAULT_VAL_ATTR1__SHIFT 0x15
#define SPI_PS_INPUT_CNTL_24__ATTR0_VALID_MASK 0x1000000
#define SPI_PS_INPUT_CNTL_24__ATTR0_VALID__SHIFT 0x18
#define SPI_PS_INPUT_CNTL_24__ATTR1_VALID_MASK 0x2000000
#define SPI_PS_INPUT_CNTL_24__ATTR1_VALID__SHIFT 0x19
#define SPI_PS_INPUT_CNTL_25__OFFSET_MASK 0x3f
#define SPI_PS_INPUT_CNTL_25__OFFSET__SHIFT 0x0
#define SPI_PS_INPUT_CNTL_25__DEFAULT_VAL_MASK 0x300
#define SPI_PS_INPUT_CNTL_25__DEFAULT_VAL__SHIFT 0x8
#define SPI_PS_INPUT_CNTL_25__FLAT_SHADE_MASK 0x400
#define SPI_PS_INPUT_CNTL_25__FLAT_SHADE__SHIFT 0xa
#define SPI_PS_INPUT_CNTL_25__DUP_MASK 0x40000
#define SPI_PS_INPUT_CNTL_25__DUP__SHIFT 0x12
#define SPI_PS_INPUT_CNTL_25__FP16_INTERP_MODE_MASK 0x80000
#define SPI_PS_INPUT_CNTL_25__FP16_INTERP_MODE__SHIFT 0x13
#define SPI_PS_INPUT_CNTL_25__USE_DEFAULT_ATTR1_MASK 0x100000
#define SPI_PS_INPUT_CNTL_25__USE_DEFAULT_ATTR1__SHIFT 0x14
#define SPI_PS_INPUT_CNTL_25__DEFAULT_VAL_ATTR1_MASK 0x600000
#define SPI_PS_INPUT_CNTL_25__DEFAULT_VAL_ATTR1__SHIFT 0x15
#define SPI_PS_INPUT_CNTL_25__ATTR0_VALID_MASK 0x1000000
#define SPI_PS_INPUT_CNTL_25__ATTR0_VALID__SHIFT 0x18
#define SPI_PS_INPUT_CNTL_25__ATTR1_VALID_MASK 0x2000000
#define SPI_PS_INPUT_CNTL_25__ATTR1_VALID__SHIFT 0x19
#define SPI_PS_INPUT_CNTL_26__OFFSET_MASK 0x3f
#define SPI_PS_INPUT_CNTL_26__OFFSET__SHIFT 0x0
#define SPI_PS_INPUT_CNTL_26__DEFAULT_VAL_MASK 0x300
#define SPI_PS_INPUT_CNTL_26__DEFAULT_VAL__SHIFT 0x8
#define SPI_PS_INPUT_CNTL_26__FLAT_SHADE_MASK 0x400
#define SPI_PS_INPUT_CNTL_26__FLAT_SHADE__SHIFT 0xa
#define SPI_PS_INPUT_CNTL_26__DUP_MASK 0x40000
#define SPI_PS_INPUT_CNTL_26__DUP__SHIFT 0x12
#define SPI_PS_INPUT_CNTL_26__FP16_INTERP_MODE_MASK 0x80000
#define SPI_PS_INPUT_CNTL_26__FP16_INTERP_MODE__SHIFT 0x13
#define SPI_PS_INPUT_CNTL_26__USE_DEFAULT_ATTR1_MASK 0x100000
#define SPI_PS_INPUT_CNTL_26__USE_DEFAULT_ATTR1__SHIFT 0x14
#define SPI_PS_INPUT_CNTL_26__DEFAULT_VAL_ATTR1_MASK 0x600000
#define SPI_PS_INPUT_CNTL_26__DEFAULT_VAL_ATTR1__SHIFT 0x15
#define SPI_PS_INPUT_CNTL_26__ATTR0_VALID_MASK 0x1000000
#define SPI_PS_INPUT_CNTL_26__ATTR0_VALID__SHIFT 0x18
#define SPI_PS_INPUT_CNTL_26__ATTR1_VALID_MASK 0x2000000
#define SPI_PS_INPUT_CNTL_26__ATTR1_VALID__SHIFT 0x19
#define SPI_PS_INPUT_CNTL_27__OFFSET_MASK 0x3f
#define SPI_PS_INPUT_CNTL_27__OFFSET__SHIFT 0x0
#define SPI_PS_INPUT_CNTL_27__DEFAULT_VAL_MASK 0x300
#define SPI_PS_INPUT_CNTL_27__DEFAULT_VAL__SHIFT 0x8
#define SPI_PS_INPUT_CNTL_27__FLAT_SHADE_MASK 0x400
#define SPI_PS_INPUT_CNTL_27__FLAT_SHADE__SHIFT 0xa
#define SPI_PS_INPUT_CNTL_27__DUP_MASK 0x40000
#define SPI_PS_INPUT_CNTL_27__DUP__SHIFT 0x12
#define SPI_PS_INPUT_CNTL_27__FP16_INTERP_MODE_MASK 0x80000
#define SPI_PS_INPUT_CNTL_27__FP16_INTERP_MODE__SHIFT 0x13
#define SPI_PS_INPUT_CNTL_27__USE_DEFAULT_ATTR1_MASK 0x100000
#define SPI_PS_INPUT_CNTL_27__USE_DEFAULT_ATTR1__SHIFT 0x14
#define SPI_PS_INPUT_CNTL_27__DEFAULT_VAL_ATTR1_MASK 0x600000
#define SPI_PS_INPUT_CNTL_27__DEFAULT_VAL_ATTR1__SHIFT 0x15
#define SPI_PS_INPUT_CNTL_27__ATTR0_VALID_MASK 0x1000000
#define SPI_PS_INPUT_CNTL_27__ATTR0_VALID__SHIFT 0x18
#define SPI_PS_INPUT_CNTL_27__ATTR1_VALID_MASK 0x2000000
#define SPI_PS_INPUT_CNTL_27__ATTR1_VALID__SHIFT 0x19
#define SPI_PS_INPUT_CNTL_28__OFFSET_MASK 0x3f
#define SPI_PS_INPUT_CNTL_28__OFFSET__SHIFT 0x0
#define SPI_PS_INPUT_CNTL_28__DEFAULT_VAL_MASK 0x300
#define SPI_PS_INPUT_CNTL_28__DEFAULT_VAL__SHIFT 0x8
#define SPI_PS_INPUT_CNTL_28__FLAT_SHADE_MASK 0x400
#define SPI_PS_INPUT_CNTL_28__FLAT_SHADE__SHIFT 0xa
#define SPI_PS_INPUT_CNTL_28__DUP_MASK 0x40000
#define SPI_PS_INPUT_CNTL_28__DUP__SHIFT 0x12
#define SPI_PS_INPUT_CNTL_28__FP16_INTERP_MODE_MASK 0x80000
#define SPI_PS_INPUT_CNTL_28__FP16_INTERP_MODE__SHIFT 0x13
#define SPI_PS_INPUT_CNTL_28__USE_DEFAULT_ATTR1_MASK 0x100000
#define SPI_PS_INPUT_CNTL_28__USE_DEFAULT_ATTR1__SHIFT 0x14
#define SPI_PS_INPUT_CNTL_28__DEFAULT_VAL_ATTR1_MASK 0x600000
#define SPI_PS_INPUT_CNTL_28__DEFAULT_VAL_ATTR1__SHIFT 0x15
#define SPI_PS_INPUT_CNTL_28__ATTR0_VALID_MASK 0x1000000
#define SPI_PS_INPUT_CNTL_28__ATTR0_VALID__SHIFT 0x18
#define SPI_PS_INPUT_CNTL_28__ATTR1_VALID_MASK 0x2000000
#define SPI_PS_INPUT_CNTL_28__ATTR1_VALID__SHIFT 0x19
#define SPI_PS_INPUT_CNTL_29__OFFSET_MASK 0x3f
#define SPI_PS_INPUT_CNTL_29__OFFSET__SHIFT 0x0
#define SPI_PS_INPUT_CNTL_29__DEFAULT_VAL_MASK 0x300
#define SPI_PS_INPUT_CNTL_29__DEFAULT_VAL__SHIFT 0x8
#define SPI_PS_INPUT_CNTL_29__FLAT_SHADE_MASK 0x400
#define SPI_PS_INPUT_CNTL_29__FLAT_SHADE__SHIFT 0xa
#define SPI_PS_INPUT_CNTL_29__DUP_MASK 0x40000
#define SPI_PS_INPUT_CNTL_29__DUP__SHIFT 0x12
#define SPI_PS_INPUT_CNTL_29__FP16_INTERP_MODE_MASK 0x80000
#define SPI_PS_INPUT_CNTL_29__FP16_INTERP_MODE__SHIFT 0x13
#define SPI_PS_INPUT_CNTL_29__USE_DEFAULT_ATTR1_MASK 0x100000
#define SPI_PS_INPUT_CNTL_29__USE_DEFAULT_ATTR1__SHIFT 0x14
#define SPI_PS_INPUT_CNTL_29__DEFAULT_VAL_ATTR1_MASK 0x600000
#define SPI_PS_INPUT_CNTL_29__DEFAULT_VAL_ATTR1__SHIFT 0x15
#define SPI_PS_INPUT_CNTL_29__ATTR0_VALID_MASK 0x1000000
#define SPI_PS_INPUT_CNTL_29__ATTR0_VALID__SHIFT 0x18
#define SPI_PS_INPUT_CNTL_29__ATTR1_VALID_MASK 0x2000000
#define SPI_PS_INPUT_CNTL_29__ATTR1_VALID__SHIFT 0x19
#define SPI_PS_INPUT_CNTL_30__OFFSET_MASK 0x3f
#define SPI_PS_INPUT_CNTL_30__OFFSET__SHIFT 0x0
#define SPI_PS_INPUT_CNTL_30__DEFAULT_VAL_MASK 0x300
#define SPI_PS_INPUT_CNTL_30__DEFAULT_VAL__SHIFT 0x8
#define SPI_PS_INPUT_CNTL_30__FLAT_SHADE_MASK 0x400
#define SPI_PS_INPUT_CNTL_30__FLAT_SHADE__SHIFT 0xa
#define SPI_PS_INPUT_CNTL_30__DUP_MASK 0x40000
#define SPI_PS_INPUT_CNTL_30__DUP__SHIFT 0x12
#define SPI_PS_INPUT_CNTL_30__FP16_INTERP_MODE_MASK 0x80000
#define SPI_PS_INPUT_CNTL_30__FP16_INTERP_MODE__SHIFT 0x13
#define SPI_PS_INPUT_CNTL_30__USE_DEFAULT_ATTR1_MASK 0x100000
#define SPI_PS_INPUT_CNTL_30__USE_DEFAULT_ATTR1__SHIFT 0x14
#define SPI_PS_INPUT_CNTL_30__DEFAULT_VAL_ATTR1_MASK 0x600000
#define SPI_PS_INPUT_CNTL_30__DEFAULT_VAL_ATTR1__SHIFT 0x15
#define SPI_PS_INPUT_CNTL_30__ATTR0_VALID_MASK 0x1000000
#define SPI_PS_INPUT_CNTL_30__ATTR0_VALID__SHIFT 0x18
#define SPI_PS_INPUT_CNTL_30__ATTR1_VALID_MASK 0x2000000
#define SPI_PS_INPUT_CNTL_30__ATTR1_VALID__SHIFT 0x19
#define SPI_PS_INPUT_CNTL_31__OFFSET_MASK 0x3f
#define SPI_PS_INPUT_CNTL_31__OFFSET__SHIFT 0x0
#define SPI_PS_INPUT_CNTL_31__DEFAULT_VAL_MASK 0x300
#define SPI_PS_INPUT_CNTL_31__DEFAULT_VAL__SHIFT 0x8
#define SPI_PS_INPUT_CNTL_31__FLAT_SHADE_MASK 0x400
#define SPI_PS_INPUT_CNTL_31__FLAT_SHADE__SHIFT 0xa
#define SPI_PS_INPUT_CNTL_31__DUP_MASK 0x40000
#define SPI_PS_INPUT_CNTL_31__DUP__SHIFT 0x12
#define SPI_PS_INPUT_CNTL_31__FP16_INTERP_MODE_MASK 0x80000
#define SPI_PS_INPUT_CNTL_31__FP16_INTERP_MODE__SHIFT 0x13
#define SPI_PS_INPUT_CNTL_31__USE_DEFAULT_ATTR1_MASK 0x100000
#define SPI_PS_INPUT_CNTL_31__USE_DEFAULT_ATTR1__SHIFT 0x14
#define SPI_PS_INPUT_CNTL_31__DEFAULT_VAL_ATTR1_MASK 0x600000
#define SPI_PS_INPUT_CNTL_31__DEFAULT_VAL_ATTR1__SHIFT 0x15
#define SPI_PS_INPUT_CNTL_31__ATTR0_VALID_MASK 0x1000000
#define SPI_PS_INPUT_CNTL_31__ATTR0_VALID__SHIFT 0x18
#define SPI_PS_INPUT_CNTL_31__ATTR1_VALID_MASK 0x2000000
#define SPI_PS_INPUT_CNTL_31__ATTR1_VALID__SHIFT 0x19
#define SPI_VS_OUT_CONFIG__VS_EXPORT_COUNT_MASK 0x3e
#define SPI_VS_OUT_CONFIG__VS_EXPORT_COUNT__SHIFT 0x1
#define SPI_VS_OUT_CONFIG__VS_HALF_PACK_MASK 0x40
#define SPI_VS_OUT_CONFIG__VS_HALF_PACK__SHIFT 0x6
#define SPI_PS_INPUT_ENA__PERSP_SAMPLE_ENA_MASK 0x1
#define SPI_PS_INPUT_ENA__PERSP_SAMPLE_ENA__SHIFT 0x0
#define SPI_PS_INPUT_ENA__PERSP_CENTER_ENA_MASK 0x2
#define SPI_PS_INPUT_ENA__PERSP_CENTER_ENA__SHIFT 0x1
#define SPI_PS_INPUT_ENA__PERSP_CENTROID_ENA_MASK 0x4
#define SPI_PS_INPUT_ENA__PERSP_CENTROID_ENA__SHIFT 0x2
#define SPI_PS_INPUT_ENA__PERSP_PULL_MODEL_ENA_MASK 0x8
#define SPI_PS_INPUT_ENA__PERSP_PULL_MODEL_ENA__SHIFT 0x3
#define SPI_PS_INPUT_ENA__LINEAR_SAMPLE_ENA_MASK 0x10
#define SPI_PS_INPUT_ENA__LINEAR_SAMPLE_ENA__SHIFT 0x4
#define SPI_PS_INPUT_ENA__LINEAR_CENTER_ENA_MASK 0x20
#define SPI_PS_INPUT_ENA__LINEAR_CENTER_ENA__SHIFT 0x5
#define SPI_PS_INPUT_ENA__LINEAR_CENTROID_ENA_MASK 0x40
#define SPI_PS_INPUT_ENA__LINEAR_CENTROID_ENA__SHIFT 0x6
#define SPI_PS_INPUT_ENA__LINE_STIPPLE_TEX_ENA_MASK 0x80
#define SPI_PS_INPUT_ENA__LINE_STIPPLE_TEX_ENA__SHIFT 0x7
#define SPI_PS_INPUT_ENA__POS_X_FLOAT_ENA_MASK 0x100
#define SPI_PS_INPUT_ENA__POS_X_FLOAT_ENA__SHIFT 0x8
#define SPI_PS_INPUT_ENA__POS_Y_FLOAT_ENA_MASK 0x200
#define SPI_PS_INPUT_ENA__POS_Y_FLOAT_ENA__SHIFT 0x9
#define SPI_PS_INPUT_ENA__POS_Z_FLOAT_ENA_MASK 0x400
#define SPI_PS_INPUT_ENA__POS_Z_FLOAT_ENA__SHIFT 0xa
#define SPI_PS_INPUT_ENA__POS_W_FLOAT_ENA_MASK 0x800
#define SPI_PS_INPUT_ENA__POS_W_FLOAT_ENA__SHIFT 0xb
#define SPI_PS_INPUT_ENA__FRONT_FACE_ENA_MASK 0x1000
#define SPI_PS_INPUT_ENA__FRONT_FACE_ENA__SHIFT 0xc
#define SPI_PS_INPUT_ENA__ANCILLARY_ENA_MASK 0x2000
#define SPI_PS_INPUT_ENA__ANCILLARY_ENA__SHIFT 0xd
#define SPI_PS_INPUT_ENA__SAMPLE_COVERAGE_ENA_MASK 0x4000
#define SPI_PS_INPUT_ENA__SAMPLE_COVERAGE_ENA__SHIFT 0xe
#define SPI_PS_INPUT_ENA__POS_FIXED_PT_ENA_MASK 0x8000
#define SPI_PS_INPUT_ENA__POS_FIXED_PT_ENA__SHIFT 0xf
#define SPI_PS_INPUT_ADDR__PERSP_SAMPLE_ENA_MASK 0x1
#define SPI_PS_INPUT_ADDR__PERSP_SAMPLE_ENA__SHIFT 0x0
#define SPI_PS_INPUT_ADDR__PERSP_CENTER_ENA_MASK 0x2
#define SPI_PS_INPUT_ADDR__PERSP_CENTER_ENA__SHIFT 0x1
#define SPI_PS_INPUT_ADDR__PERSP_CENTROID_ENA_MASK 0x4
#define SPI_PS_INPUT_ADDR__PERSP_CENTROID_ENA__SHIFT 0x2
#define SPI_PS_INPUT_ADDR__PERSP_PULL_MODEL_ENA_MASK 0x8
#define SPI_PS_INPUT_ADDR__PERSP_PULL_MODEL_ENA__SHIFT 0x3
#define SPI_PS_INPUT_ADDR__LINEAR_SAMPLE_ENA_MASK 0x10
#define SPI_PS_INPUT_ADDR__LINEAR_SAMPLE_ENA__SHIFT 0x4
#define SPI_PS_INPUT_ADDR__LINEAR_CENTER_ENA_MASK 0x20
#define SPI_PS_INPUT_ADDR__LINEAR_CENTER_ENA__SHIFT 0x5
#define SPI_PS_INPUT_ADDR__LINEAR_CENTROID_ENA_MASK 0x40
#define SPI_PS_INPUT_ADDR__LINEAR_CENTROID_ENA__SHIFT 0x6
#define SPI_PS_INPUT_ADDR__LINE_STIPPLE_TEX_ENA_MASK 0x80
#define SPI_PS_INPUT_ADDR__LINE_STIPPLE_TEX_ENA__SHIFT 0x7
#define SPI_PS_INPUT_ADDR__POS_X_FLOAT_ENA_MASK 0x100
#define SPI_PS_INPUT_ADDR__POS_X_FLOAT_ENA__SHIFT 0x8
#define SPI_PS_INPUT_ADDR__POS_Y_FLOAT_ENA_MASK 0x200
#define SPI_PS_INPUT_ADDR__POS_Y_FLOAT_ENA__SHIFT 0x9
#define SPI_PS_INPUT_ADDR__POS_Z_FLOAT_ENA_MASK 0x400
#define SPI_PS_INPUT_ADDR__POS_Z_FLOAT_ENA__SHIFT 0xa
#define SPI_PS_INPUT_ADDR__POS_W_FLOAT_ENA_MASK 0x800
#define SPI_PS_INPUT_ADDR__POS_W_FLOAT_ENA__SHIFT 0xb
#define SPI_PS_INPUT_ADDR__FRONT_FACE_ENA_MASK 0x1000
#define SPI_PS_INPUT_ADDR__FRONT_FACE_ENA__SHIFT 0xc
#define SPI_PS_INPUT_ADDR__ANCILLARY_ENA_MASK 0x2000
#define SPI_PS_INPUT_ADDR__ANCILLARY_ENA__SHIFT 0xd
#define SPI_PS_INPUT_ADDR__SAMPLE_COVERAGE_ENA_MASK 0x4000
#define SPI_PS_INPUT_ADDR__SAMPLE_COVERAGE_ENA__SHIFT 0xe
#define SPI_PS_INPUT_ADDR__POS_FIXED_PT_ENA_MASK 0x8000
#define SPI_PS_INPUT_ADDR__POS_FIXED_PT_ENA__SHIFT 0xf
#define SPI_INTERP_CONTROL_0__FLAT_SHADE_ENA_MASK 0x1
#define SPI_INTERP_CONTROL_0__FLAT_SHADE_ENA__SHIFT 0x0
#define SPI_INTERP_CONTROL_0__PNT_SPRITE_ENA_MASK 0x2
#define SPI_INTERP_CONTROL_0__PNT_SPRITE_ENA__SHIFT 0x1
#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_X_MASK 0x1c
#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_X__SHIFT 0x2
#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_Y_MASK 0xe0
#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_Y__SHIFT 0x5
#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_Z_MASK 0x700
#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_Z__SHIFT 0x8
#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_W_MASK 0x3800
#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_W__SHIFT 0xb
#define SPI_INTERP_CONTROL_0__PNT_SPRITE_TOP_1_MASK 0x4000
#define SPI_INTERP_CONTROL_0__PNT_SPRITE_TOP_1__SHIFT 0xe
#define SPI_PS_IN_CONTROL__NUM_INTERP_MASK 0x3f
#define SPI_PS_IN_CONTROL__NUM_INTERP__SHIFT 0x0
#define SPI_PS_IN_CONTROL__PARAM_GEN_MASK 0x40
#define SPI_PS_IN_CONTROL__PARAM_GEN__SHIFT 0x6
#define SPI_PS_IN_CONTROL__BC_OPTIMIZE_DISABLE_MASK 0x4000
#define SPI_PS_IN_CONTROL__BC_OPTIMIZE_DISABLE__SHIFT 0xe
#define SPI_BARYC_CNTL__PERSP_CENTER_CNTL_MASK 0x1
#define SPI_BARYC_CNTL__PERSP_CENTER_CNTL__SHIFT 0x0
#define SPI_BARYC_CNTL__PERSP_CENTROID_CNTL_MASK 0x10
#define SPI_BARYC_CNTL__PERSP_CENTROID_CNTL__SHIFT 0x4
#define SPI_BARYC_CNTL__LINEAR_CENTER_CNTL_MASK 0x100
#define SPI_BARYC_CNTL__LINEAR_CENTER_CNTL__SHIFT 0x8
#define SPI_BARYC_CNTL__LINEAR_CENTROID_CNTL_MASK 0x1000
#define SPI_BARYC_CNTL__LINEAR_CENTROID_CNTL__SHIFT 0xc
#define SPI_BARYC_CNTL__POS_FLOAT_LOCATION_MASK 0x30000
#define SPI_BARYC_CNTL__POS_FLOAT_LOCATION__SHIFT 0x10
#define SPI_BARYC_CNTL__POS_FLOAT_ULC_MASK 0x100000
#define SPI_BARYC_CNTL__POS_FLOAT_ULC__SHIFT 0x14
#define SPI_BARYC_CNTL__FRONT_FACE_ALL_BITS_MASK 0x1000000
#define SPI_BARYC_CNTL__FRONT_FACE_ALL_BITS__SHIFT 0x18
#define SPI_TMPRING_SIZE__WAVES_MASK 0xfff
#define SPI_TMPRING_SIZE__WAVES__SHIFT 0x0
#define SPI_TMPRING_SIZE__WAVESIZE_MASK 0x1fff000
#define SPI_TMPRING_SIZE__WAVESIZE__SHIFT 0xc
#define SPI_SHADER_POS_FORMAT__POS0_EXPORT_FORMAT_MASK 0xf
#define SPI_SHADER_POS_FORMAT__POS0_EXPORT_FORMAT__SHIFT 0x0
#define SPI_SHADER_POS_FORMAT__POS1_EXPORT_FORMAT_MASK 0xf0
#define SPI_SHADER_POS_FORMAT__POS1_EXPORT_FORMAT__SHIFT 0x4
#define SPI_SHADER_POS_FORMAT__POS2_EXPORT_FORMAT_MASK 0xf00
#define SPI_SHADER_POS_FORMAT__POS2_EXPORT_FORMAT__SHIFT 0x8
#define SPI_SHADER_POS_FORMAT__POS3_EXPORT_FORMAT_MASK 0xf000
#define SPI_SHADER_POS_FORMAT__POS3_EXPORT_FORMAT__SHIFT 0xc
#define SPI_SHADER_Z_FORMAT__Z_EXPORT_FORMAT_MASK 0xf
#define SPI_SHADER_Z_FORMAT__Z_EXPORT_FORMAT__SHIFT 0x0
#define SPI_SHADER_COL_FORMAT__COL0_EXPORT_FORMAT_MASK 0xf
#define SPI_SHADER_COL_FORMAT__COL0_EXPORT_FORMAT__SHIFT 0x0
#define SPI_SHADER_COL_FORMAT__COL1_EXPORT_FORMAT_MASK 0xf0
#define SPI_SHADER_COL_FORMAT__COL1_EXPORT_FORMAT__SHIFT 0x4
#define SPI_SHADER_COL_FORMAT__COL2_EXPORT_FORMAT_MASK 0xf00
#define SPI_SHADER_COL_FORMAT__COL2_EXPORT_FORMAT__SHIFT 0x8
#define SPI_SHADER_COL_FORMAT__COL3_EXPORT_FORMAT_MASK 0xf000
#define SPI_SHADER_COL_FORMAT__COL3_EXPORT_FORMAT__SHIFT 0xc
#define SPI_SHADER_COL_FORMAT__COL4_EXPORT_FORMAT_MASK 0xf0000
#define SPI_SHADER_COL_FORMAT__COL4_EXPORT_FORMAT__SHIFT 0x10
#define SPI_SHADER_COL_FORMAT__COL5_EXPORT_FORMAT_MASK 0xf00000
#define SPI_SHADER_COL_FORMAT__COL5_EXPORT_FORMAT__SHIFT 0x14
#define SPI_SHADER_COL_FORMAT__COL6_EXPORT_FORMAT_MASK 0xf000000
#define SPI_SHADER_COL_FORMAT__COL6_EXPORT_FORMAT__SHIFT 0x18
#define SPI_SHADER_COL_FORMAT__COL7_EXPORT_FORMAT_MASK 0xf0000000
#define SPI_SHADER_COL_FORMAT__COL7_EXPORT_FORMAT__SHIFT 0x1c
#define SPI_ARB_PRIORITY__PIPE_ORDER_TS0_MASK 0x7
#define SPI_ARB_PRIORITY__PIPE_ORDER_TS0__SHIFT 0x0
#define SPI_ARB_PRIORITY__PIPE_ORDER_TS1_MASK 0x38
#define SPI_ARB_PRIORITY__PIPE_ORDER_TS1__SHIFT 0x3
#define SPI_ARB_PRIORITY__PIPE_ORDER_TS2_MASK 0x1c0
#define SPI_ARB_PRIORITY__PIPE_ORDER_TS2__SHIFT 0x6
#define SPI_ARB_PRIORITY__PIPE_ORDER_TS3_MASK 0xe00
#define SPI_ARB_PRIORITY__PIPE_ORDER_TS3__SHIFT 0x9
#define SPI_ARB_PRIORITY__TS0_DUR_MULT_MASK 0x3000
#define SPI_ARB_PRIORITY__TS0_DUR_MULT__SHIFT 0xc
#define SPI_ARB_PRIORITY__TS1_DUR_MULT_MASK 0xc000
#define SPI_ARB_PRIORITY__TS1_DUR_MULT__SHIFT 0xe
#define SPI_ARB_PRIORITY__TS2_DUR_MULT_MASK 0x30000
#define SPI_ARB_PRIORITY__TS2_DUR_MULT__SHIFT 0x10
#define SPI_ARB_PRIORITY__TS3_DUR_MULT_MASK 0xc0000
#define SPI_ARB_PRIORITY__TS3_DUR_MULT__SHIFT 0x12
#define SPI_ARB_CYCLES_0__TS0_DURATION_MASK 0xffff
#define SPI_ARB_CYCLES_0__TS0_DURATION__SHIFT 0x0
#define SPI_ARB_CYCLES_0__TS1_DURATION_MASK 0xffff0000
#define SPI_ARB_CYCLES_0__TS1_DURATION__SHIFT 0x10
#define SPI_ARB_CYCLES_1__TS2_DURATION_MASK 0xffff
#define SPI_ARB_CYCLES_1__TS2_DURATION__SHIFT 0x0
#define SPI_ARB_CYCLES_1__TS3_DURATION_MASK 0xffff0000
#define SPI_ARB_CYCLES_1__TS3_DURATION__SHIFT 0x10
#define SPI_CDBG_SYS_GFX__PS_EN_MASK 0x1
#define SPI_CDBG_SYS_GFX__PS_EN__SHIFT 0x0
#define SPI_CDBG_SYS_GFX__VS_EN_MASK 0x2
#define SPI_CDBG_SYS_GFX__VS_EN__SHIFT 0x1
#define SPI_CDBG_SYS_GFX__GS_EN_MASK 0x4
#define SPI_CDBG_SYS_GFX__GS_EN__SHIFT 0x2
#define SPI_CDBG_SYS_GFX__ES_EN_MASK 0x8
#define SPI_CDBG_SYS_GFX__ES_EN__SHIFT 0x3
#define SPI_CDBG_SYS_GFX__HS_EN_MASK 0x10
#define SPI_CDBG_SYS_GFX__HS_EN__SHIFT 0x4
#define SPI_CDBG_SYS_GFX__LS_EN_MASK 0x20
#define SPI_CDBG_SYS_GFX__LS_EN__SHIFT 0x5
#define SPI_CDBG_SYS_GFX__CS_EN_MASK 0x40
#define SPI_CDBG_SYS_GFX__CS_EN__SHIFT 0x6
#define SPI_CDBG_SYS_HP3D__PS_EN_MASK 0x1
#define SPI_CDBG_SYS_HP3D__PS_EN__SHIFT 0x0
#define SPI_CDBG_SYS_HP3D__VS_EN_MASK 0x2
#define SPI_CDBG_SYS_HP3D__VS_EN__SHIFT 0x1
#define SPI_CDBG_SYS_HP3D__GS_EN_MASK 0x4
#define SPI_CDBG_SYS_HP3D__GS_EN__SHIFT 0x2
#define SPI_CDBG_SYS_HP3D__ES_EN_MASK 0x8
#define SPI_CDBG_SYS_HP3D__ES_EN__SHIFT 0x3
#define SPI_CDBG_SYS_HP3D__HS_EN_MASK 0x10
#define SPI_CDBG_SYS_HP3D__HS_EN__SHIFT 0x4
#define SPI_CDBG_SYS_HP3D__LS_EN_MASK 0x20
#define SPI_CDBG_SYS_HP3D__LS_EN__SHIFT 0x5
#define SPI_CDBG_SYS_CS0__PIPE0_MASK 0xff
#define SPI_CDBG_SYS_CS0__PIPE0__SHIFT 0x0
#define SPI_CDBG_SYS_CS0__PIPE1_MASK 0xff00
#define SPI_CDBG_SYS_CS0__PIPE1__SHIFT 0x8
#define SPI_CDBG_SYS_CS0__PIPE2_MASK 0xff0000
#define SPI_CDBG_SYS_CS0__PIPE2__SHIFT 0x10
#define SPI_CDBG_SYS_CS0__PIPE3_MASK 0xff000000
#define SPI_CDBG_SYS_CS0__PIPE3__SHIFT 0x18
#define SPI_CDBG_SYS_CS1__PIPE0_MASK 0xff
#define SPI_CDBG_SYS_CS1__PIPE0__SHIFT 0x0
#define SPI_CDBG_SYS_CS1__PIPE1_MASK 0xff00
#define SPI_CDBG_SYS_CS1__PIPE1__SHIFT 0x8
#define SPI_CDBG_SYS_CS1__PIPE2_MASK 0xff0000
#define SPI_CDBG_SYS_CS1__PIPE2__SHIFT 0x10
#define SPI_CDBG_SYS_CS1__PIPE3_MASK 0xff000000
#define SPI_CDBG_SYS_CS1__PIPE3__SHIFT 0x18
#define SPI_WCL_PIPE_PERCENT_GFX__VALUE_MASK 0x7f
#define SPI_WCL_PIPE_PERCENT_GFX__VALUE__SHIFT 0x0
#define SPI_WCL_PIPE_PERCENT_GFX__LS_GRP_VALUE_MASK 0xf80
#define SPI_WCL_PIPE_PERCENT_GFX__LS_GRP_VALUE__SHIFT 0x7
#define SPI_WCL_PIPE_PERCENT_GFX__HS_GRP_VALUE_MASK 0x1f000
#define SPI_WCL_PIPE_PERCENT_GFX__HS_GRP_VALUE__SHIFT 0xc
#define SPI_WCL_PIPE_PERCENT_GFX__ES_GRP_VALUE_MASK 0x3e0000
#define SPI_WCL_PIPE_PERCENT_GFX__ES_GRP_VALUE__SHIFT 0x11
#define SPI_WCL_PIPE_PERCENT_GFX__GS_GRP_VALUE_MASK 0x7c00000
#define SPI_WCL_PIPE_PERCENT_GFX__GS_GRP_VALUE__SHIFT 0x16
#define SPI_WCL_PIPE_PERCENT_HP3D__VALUE_MASK 0x7f
#define SPI_WCL_PIPE_PERCENT_HP3D__VALUE__SHIFT 0x0
#define SPI_WCL_PIPE_PERCENT_HP3D__LS_GRP_VALUE_MASK 0xf80
#define SPI_WCL_PIPE_PERCENT_HP3D__LS_GRP_VALUE__SHIFT 0x7
#define SPI_WCL_PIPE_PERCENT_HP3D__HS_GRP_VALUE_MASK 0x1f000
#define SPI_WCL_PIPE_PERCENT_HP3D__HS_GRP_VALUE__SHIFT 0xc
#define SPI_WCL_PIPE_PERCENT_HP3D__ES_GRP_VALUE_MASK 0x3e0000
#define SPI_WCL_PIPE_PERCENT_HP3D__ES_GRP_VALUE__SHIFT 0x11
#define SPI_WCL_PIPE_PERCENT_HP3D__GS_GRP_VALUE_MASK 0x7c00000
#define SPI_WCL_PIPE_PERCENT_HP3D__GS_GRP_VALUE__SHIFT 0x16
#define SPI_WCL_PIPE_PERCENT_CS0__VALUE_MASK 0x7f
#define SPI_WCL_PIPE_PERCENT_CS0__VALUE__SHIFT 0x0
#define SPI_WCL_PIPE_PERCENT_CS1__VALUE_MASK 0x7f
#define SPI_WCL_PIPE_PERCENT_CS1__VALUE__SHIFT 0x0
#define SPI_WCL_PIPE_PERCENT_CS2__VALUE_MASK 0x7f
#define SPI_WCL_PIPE_PERCENT_CS2__VALUE__SHIFT 0x0
#define SPI_WCL_PIPE_PERCENT_CS3__VALUE_MASK 0x7f
#define SPI_WCL_PIPE_PERCENT_CS3__VALUE__SHIFT 0x0
#define SPI_WCL_PIPE_PERCENT_CS4__VALUE_MASK 0x7f
#define SPI_WCL_PIPE_PERCENT_CS4__VALUE__SHIFT 0x0
#define SPI_WCL_PIPE_PERCENT_CS5__VALUE_MASK 0x7f
#define SPI_WCL_PIPE_PERCENT_CS5__VALUE__SHIFT 0x0
#define SPI_WCL_PIPE_PERCENT_CS6__VALUE_MASK 0x7f
#define SPI_WCL_PIPE_PERCENT_CS6__VALUE__SHIFT 0x0
#define SPI_WCL_PIPE_PERCENT_CS7__VALUE_MASK 0x7f
#define SPI_WCL_PIPE_PERCENT_CS7__VALUE__SHIFT 0x0
#define SPI_GDBG_WAVE_CNTL__STALL_RA_MASK 0x1
#define SPI_GDBG_WAVE_CNTL__STALL_RA__SHIFT 0x0
#define SPI_GDBG_WAVE_CNTL__STALL_VMID_MASK 0x1fffe
#define SPI_GDBG_WAVE_CNTL__STALL_VMID__SHIFT 0x1
#define SPI_GDBG_TRAP_CONFIG__ME_SEL_MASK 0x3
#define SPI_GDBG_TRAP_CONFIG__ME_SEL__SHIFT 0x0
#define SPI_GDBG_TRAP_CONFIG__PIPE_SEL_MASK 0xc
#define SPI_GDBG_TRAP_CONFIG__PIPE_SEL__SHIFT 0x2
#define SPI_GDBG_TRAP_CONFIG__QUEUE_SEL_MASK 0x70
#define SPI_GDBG_TRAP_CONFIG__QUEUE_SEL__SHIFT 0x4
#define SPI_GDBG_TRAP_CONFIG__ME_MATCH_MASK 0x80
#define SPI_GDBG_TRAP_CONFIG__ME_MATCH__SHIFT 0x7
#define SPI_GDBG_TRAP_CONFIG__PIPE_MATCH_MASK 0x100
#define SPI_GDBG_TRAP_CONFIG__PIPE_MATCH__SHIFT 0x8
#define SPI_GDBG_TRAP_CONFIG__QUEUE_MATCH_MASK 0x200
#define SPI_GDBG_TRAP_CONFIG__QUEUE_MATCH__SHIFT 0x9
#define SPI_GDBG_TRAP_CONFIG__TRAP_EN_MASK 0x8000
#define SPI_GDBG_TRAP_CONFIG__TRAP_EN__SHIFT 0xf
#define SPI_GDBG_TRAP_CONFIG__VMID_SEL_MASK 0xffff0000
#define SPI_GDBG_TRAP_CONFIG__VMID_SEL__SHIFT 0x10
#define SPI_GDBG_TRAP_MASK__EXCP_EN_MASK 0x1ff
#define SPI_GDBG_TRAP_MASK__EXCP_EN__SHIFT 0x0
#define SPI_GDBG_TRAP_MASK__REPLACE_MASK 0x200
#define SPI_GDBG_TRAP_MASK__REPLACE__SHIFT 0x9
#define SPI_GDBG_TBA_LO__MEM_BASE_MASK 0xffffffff
#define SPI_GDBG_TBA_LO__MEM_BASE__SHIFT 0x0
#define SPI_GDBG_TBA_HI__MEM_BASE_MASK 0xff
#define SPI_GDBG_TBA_HI__MEM_BASE__SHIFT 0x0
#define SPI_GDBG_TMA_LO__MEM_BASE_MASK 0xffffffff
#define SPI_GDBG_TMA_LO__MEM_BASE__SHIFT 0x0
#define SPI_GDBG_TMA_HI__MEM_BASE_MASK 0xff
#define SPI_GDBG_TMA_HI__MEM_BASE__SHIFT 0x0
#define SPI_GDBG_TRAP_DATA0__DATA_MASK 0xffffffff
#define SPI_GDBG_TRAP_DATA0__DATA__SHIFT 0x0
#define SPI_GDBG_TRAP_DATA1__DATA_MASK 0xffffffff
#define SPI_GDBG_TRAP_DATA1__DATA__SHIFT 0x0
#define SPI_RESET_DEBUG__DISABLE_GFX_RESET_MASK 0x1
#define SPI_RESET_DEBUG__DISABLE_GFX_RESET__SHIFT 0x0
#define SPI_RESET_DEBUG__DISABLE_GFX_RESET_PER_VMID_MASK 0x2
#define SPI_RESET_DEBUG__DISABLE_GFX_RESET_PER_VMID__SHIFT 0x1
#define SPI_RESET_DEBUG__DISABLE_GFX_RESET_ALL_VMID_MASK 0x4
#define SPI_RESET_DEBUG__DISABLE_GFX_RESET_ALL_VMID__SHIFT 0x2
#define SPI_RESET_DEBUG__DISABLE_GFX_RESET_RESOURCE_MASK 0x8
#define SPI_RESET_DEBUG__DISABLE_GFX_RESET_RESOURCE__SHIFT 0x3
#define SPI_RESET_DEBUG__DISABLE_GFX_RESET_PRIORITY_MASK 0x10
#define SPI_RESET_DEBUG__DISABLE_GFX_RESET_PRIORITY__SHIFT 0x4
#define SPI_COMPUTE_QUEUE_RESET__RESET_MASK 0x1
#define SPI_COMPUTE_QUEUE_RESET__RESET__SHIFT 0x0
#define SPI_RESOURCE_RESERVE_CU_0__VGPR_MASK 0xf
#define SPI_RESOURCE_RESERVE_CU_0__VGPR__SHIFT 0x0
#define SPI_RESOURCE_RESERVE_CU_0__SGPR_MASK 0xf0
#define SPI_RESOURCE_RESERVE_CU_0__SGPR__SHIFT 0x4
#define SPI_RESOURCE_RESERVE_CU_0__LDS_MASK 0xf00
#define SPI_RESOURCE_RESERVE_CU_0__LDS__SHIFT 0x8
#define SPI_RESOURCE_RESERVE_CU_0__WAVES_MASK 0x7000
#define SPI_RESOURCE_RESERVE_CU_0__WAVES__SHIFT 0xc
#define SPI_RESOURCE_RESERVE_CU_0__BARRIERS_MASK 0x78000
#define SPI_RESOURCE_RESERVE_CU_0__BARRIERS__SHIFT 0xf
#define SPI_RESOURCE_RESERVE_CU_1__VGPR_MASK 0xf
#define SPI_RESOURCE_RESERVE_CU_1__VGPR__SHIFT 0x0
#define SPI_RESOURCE_RESERVE_CU_1__SGPR_MASK 0xf0
#define SPI_RESOURCE_RESERVE_CU_1__SGPR__SHIFT 0x4
#define SPI_RESOURCE_RESERVE_CU_1__LDS_MASK 0xf00
#define SPI_RESOURCE_RESERVE_CU_1__LDS__SHIFT 0x8
#define SPI_RESOURCE_RESERVE_CU_1__WAVES_MASK 0x7000
#define SPI_RESOURCE_RESERVE_CU_1__WAVES__SHIFT 0xc
#define SPI_RESOURCE_RESERVE_CU_1__BARRIERS_MASK 0x78000
#define SPI_RESOURCE_RESERVE_CU_1__BARRIERS__SHIFT 0xf
#define SPI_RESOURCE_RESERVE_CU_2__VGPR_MASK 0xf
#define SPI_RESOURCE_RESERVE_CU_2__VGPR__SHIFT 0x0
#define SPI_RESOURCE_RESERVE_CU_2__SGPR_MASK 0xf0
#define SPI_RESOURCE_RESERVE_CU_2__SGPR__SHIFT 0x4
#define SPI_RESOURCE_RESERVE_CU_2__LDS_MASK 0xf00
#define SPI_RESOURCE_RESERVE_CU_2__LDS__SHIFT 0x8
#define SPI_RESOURCE_RESERVE_CU_2__WAVES_MASK 0x7000
#define SPI_RESOURCE_RESERVE_CU_2__WAVES__SHIFT 0xc
#define SPI_RESOURCE_RESERVE_CU_2__BARRIERS_MASK 0x78000
#define SPI_RESOURCE_RESERVE_CU_2__BARRIERS__SHIFT 0xf
#define SPI_RESOURCE_RESERVE_CU_3__VGPR_MASK 0xf
#define SPI_RESOURCE_RESERVE_CU_3__VGPR__SHIFT 0x0
#define SPI_RESOURCE_RESERVE_CU_3__SGPR_MASK 0xf0
#define SPI_RESOURCE_RESERVE_CU_3__SGPR__SHIFT 0x4
#define SPI_RESOURCE_RESERVE_CU_3__LDS_MASK 0xf00
#define SPI_RESOURCE_RESERVE_CU_3__LDS__SHIFT 0x8
#define SPI_RESOURCE_RESERVE_CU_3__WAVES_MASK 0x7000
#define SPI_RESOURCE_RESERVE_CU_3__WAVES__SHIFT 0xc
#define SPI_RESOURCE_RESERVE_CU_3__BARRIERS_MASK 0x78000
#define SPI_RESOURCE_RESERVE_CU_3__BARRIERS__SHIFT 0xf
#define SPI_RESOURCE_RESERVE_CU_4__VGPR_MASK 0xf
#define SPI_RESOURCE_RESERVE_CU_4__VGPR__SHIFT 0x0
#define SPI_RESOURCE_RESERVE_CU_4__SGPR_MASK 0xf0
#define SPI_RESOURCE_RESERVE_CU_4__SGPR__SHIFT 0x4
#define SPI_RESOURCE_RESERVE_CU_4__LDS_MASK 0xf00
#define SPI_RESOURCE_RESERVE_CU_4__LDS__SHIFT 0x8
#define SPI_RESOURCE_RESERVE_CU_4__WAVES_MASK 0x7000
#define SPI_RESOURCE_RESERVE_CU_4__WAVES__SHIFT 0xc
#define SPI_RESOURCE_RESERVE_CU_4__BARRIERS_MASK 0x78000
#define SPI_RESOURCE_RESERVE_CU_4__BARRIERS__SHIFT 0xf
#define SPI_RESOURCE_RESERVE_CU_5__VGPR_MASK 0xf
#define SPI_RESOURCE_RESERVE_CU_5__VGPR__SHIFT 0x0
#define SPI_RESOURCE_RESERVE_CU_5__SGPR_MASK 0xf0
#define SPI_RESOURCE_RESERVE_CU_5__SGPR__SHIFT 0x4
#define SPI_RESOURCE_RESERVE_CU_5__LDS_MASK 0xf00
#define SPI_RESOURCE_RESERVE_CU_5__LDS__SHIFT 0x8
#define SPI_RESOURCE_RESERVE_CU_5__WAVES_MASK 0x7000
#define SPI_RESOURCE_RESERVE_CU_5__WAVES__SHIFT 0xc
#define SPI_RESOURCE_RESERVE_CU_5__BARRIERS_MASK 0x78000
#define SPI_RESOURCE_RESERVE_CU_5__BARRIERS__SHIFT 0xf
#define SPI_RESOURCE_RESERVE_CU_6__VGPR_MASK 0xf
#define SPI_RESOURCE_RESERVE_CU_6__VGPR__SHIFT 0x0
#define SPI_RESOURCE_RESERVE_CU_6__SGPR_MASK 0xf0
#define SPI_RESOURCE_RESERVE_CU_6__SGPR__SHIFT 0x4
#define SPI_RESOURCE_RESERVE_CU_6__LDS_MASK 0xf00
#define SPI_RESOURCE_RESERVE_CU_6__LDS__SHIFT 0x8
#define SPI_RESOURCE_RESERVE_CU_6__WAVES_MASK 0x7000
#define SPI_RESOURCE_RESERVE_CU_6__WAVES__SHIFT 0xc
#define SPI_RESOURCE_RESERVE_CU_6__BARRIERS_MASK 0x78000
#define SPI_RESOURCE_RESERVE_CU_6__BARRIERS__SHIFT 0xf
#define SPI_RESOURCE_RESERVE_CU_7__VGPR_MASK 0xf
#define SPI_RESOURCE_RESERVE_CU_7__VGPR__SHIFT 0x0
#define SPI_RESOURCE_RESERVE_CU_7__SGPR_MASK 0xf0
#define SPI_RESOURCE_RESERVE_CU_7__SGPR__SHIFT 0x4
#define SPI_RESOURCE_RESERVE_CU_7__LDS_MASK 0xf00
#define SPI_RESOURCE_RESERVE_CU_7__LDS__SHIFT 0x8
#define SPI_RESOURCE_RESERVE_CU_7__WAVES_MASK 0x7000
#define SPI_RESOURCE_RESERVE_CU_7__WAVES__SHIFT 0xc
#define SPI_RESOURCE_RESERVE_CU_7__BARRIERS_MASK 0x78000
#define SPI_RESOURCE_RESERVE_CU_7__BARRIERS__SHIFT 0xf
#define SPI_RESOURCE_RESERVE_CU_8__VGPR_MASK 0xf
#define SPI_RESOURCE_RESERVE_CU_8__VGPR__SHIFT 0x0
#define SPI_RESOURCE_RESERVE_CU_8__SGPR_MASK 0xf0
#define SPI_RESOURCE_RESERVE_CU_8__SGPR__SHIFT 0x4
#define SPI_RESOURCE_RESERVE_CU_8__LDS_MASK 0xf00
#define SPI_RESOURCE_RESERVE_CU_8__LDS__SHIFT 0x8
#define SPI_RESOURCE_RESERVE_CU_8__WAVES_MASK 0x7000
#define SPI_RESOURCE_RESERVE_CU_8__WAVES__SHIFT 0xc
#define SPI_RESOURCE_RESERVE_CU_8__BARRIERS_MASK 0x78000
#define SPI_RESOURCE_RESERVE_CU_8__BARRIERS__SHIFT 0xf
#define SPI_RESOURCE_RESERVE_CU_9__VGPR_MASK 0xf
#define SPI_RESOURCE_RESERVE_CU_9__VGPR__SHIFT 0x0
#define SPI_RESOURCE_RESERVE_CU_9__SGPR_MASK 0xf0
#define SPI_RESOURCE_RESERVE_CU_9__SGPR__SHIFT 0x4
#define SPI_RESOURCE_RESERVE_CU_9__LDS_MASK 0xf00
#define SPI_RESOURCE_RESERVE_CU_9__LDS__SHIFT 0x8
#define SPI_RESOURCE_RESERVE_CU_9__WAVES_MASK 0x7000
#define SPI_RESOURCE_RESERVE_CU_9__WAVES__SHIFT 0xc
#define SPI_RESOURCE_RESERVE_CU_9__BARRIERS_MASK 0x78000
#define SPI_RESOURCE_RESERVE_CU_9__BARRIERS__SHIFT 0xf
#define SPI_RESOURCE_RESERVE_CU_10__VGPR_MASK 0xf
#define SPI_RESOURCE_RESERVE_CU_10__VGPR__SHIFT 0x0
#define SPI_RESOURCE_RESERVE_CU_10__SGPR_MASK 0xf0
#define SPI_RESOURCE_RESERVE_CU_10__SGPR__SHIFT 0x4
#define SPI_RESOURCE_RESERVE_CU_10__LDS_MASK 0xf00
#define SPI_RESOURCE_RESERVE_CU_10__LDS__SHIFT 0x8
#define SPI_RESOURCE_RESERVE_CU_10__WAVES_MASK 0x7000
#define SPI_RESOURCE_RESERVE_CU_10__WAVES__SHIFT 0xc
#define SPI_RESOURCE_RESERVE_CU_10__BARRIERS_MASK 0x78000
#define SPI_RESOURCE_RESERVE_CU_10__BARRIERS__SHIFT 0xf
#define SPI_RESOURCE_RESERVE_CU_11__VGPR_MASK 0xf
#define SPI_RESOURCE_RESERVE_CU_11__VGPR__SHIFT 0x0
#define SPI_RESOURCE_RESERVE_CU_11__SGPR_MASK 0xf0
#define SPI_RESOURCE_RESERVE_CU_11__SGPR__SHIFT 0x4
#define SPI_RESOURCE_RESERVE_CU_11__LDS_MASK 0xf00
#define SPI_RESOURCE_RESERVE_CU_11__LDS__SHIFT 0x8
#define SPI_RESOURCE_RESERVE_CU_11__WAVES_MASK 0x7000
#define SPI_RESOURCE_RESERVE_CU_11__WAVES__SHIFT 0xc
#define SPI_RESOURCE_RESERVE_CU_11__BARRIERS_MASK 0x78000
#define SPI_RESOURCE_RESERVE_CU_11__BARRIERS__SHIFT 0xf
#define SPI_RESOURCE_RESERVE_CU_12__VGPR_MASK 0xf
#define SPI_RESOURCE_RESERVE_CU_12__VGPR__SHIFT 0x0
#define SPI_RESOURCE_RESERVE_CU_12__SGPR_MASK 0xf0
#define SPI_RESOURCE_RESERVE_CU_12__SGPR__SHIFT 0x4
#define SPI_RESOURCE_RESERVE_CU_12__LDS_MASK 0xf00
#define SPI_RESOURCE_RESERVE_CU_12__LDS__SHIFT 0x8
#define SPI_RESOURCE_RESERVE_CU_12__WAVES_MASK 0x7000
#define SPI_RESOURCE_RESERVE_CU_12__WAVES__SHIFT 0xc
#define SPI_RESOURCE_RESERVE_CU_12__BARRIERS_MASK 0x78000
#define SPI_RESOURCE_RESERVE_CU_12__BARRIERS__SHIFT 0xf
#define SPI_RESOURCE_RESERVE_CU_13__VGPR_MASK 0xf
#define SPI_RESOURCE_RESERVE_CU_13__VGPR__SHIFT 0x0
#define SPI_RESOURCE_RESERVE_CU_13__SGPR_MASK 0xf0
#define SPI_RESOURCE_RESERVE_CU_13__SGPR__SHIFT 0x4
#define SPI_RESOURCE_RESERVE_CU_13__LDS_MASK 0xf00
#define SPI_RESOURCE_RESERVE_CU_13__LDS__SHIFT 0x8
#define SPI_RESOURCE_RESERVE_CU_13__WAVES_MASK 0x7000
#define SPI_RESOURCE_RESERVE_CU_13__WAVES__SHIFT 0xc
#define SPI_RESOURCE_RESERVE_CU_13__BARRIERS_MASK 0x78000
#define SPI_RESOURCE_RESERVE_CU_13__BARRIERS__SHIFT 0xf
#define SPI_RESOURCE_RESERVE_CU_14__VGPR_MASK 0xf
#define SPI_RESOURCE_RESERVE_CU_14__VGPR__SHIFT 0x0
#define SPI_RESOURCE_RESERVE_CU_14__SGPR_MASK 0xf0
#define SPI_RESOURCE_RESERVE_CU_14__SGPR__SHIFT 0x4
#define SPI_RESOURCE_RESERVE_CU_14__LDS_MASK 0xf00
#define SPI_RESOURCE_RESERVE_CU_14__LDS__SHIFT 0x8
#define SPI_RESOURCE_RESERVE_CU_14__WAVES_MASK 0x7000
#define SPI_RESOURCE_RESERVE_CU_14__WAVES__SHIFT 0xc
#define SPI_RESOURCE_RESERVE_CU_14__BARRIERS_MASK 0x78000
#define SPI_RESOURCE_RESERVE_CU_14__BARRIERS__SHIFT 0xf
#define SPI_RESOURCE_RESERVE_CU_15__VGPR_MASK 0xf
#define SPI_RESOURCE_RESERVE_CU_15__VGPR__SHIFT 0x0
#define SPI_RESOURCE_RESERVE_CU_15__SGPR_MASK 0xf0
#define SPI_RESOURCE_RESERVE_CU_15__SGPR__SHIFT 0x4
#define SPI_RESOURCE_RESERVE_CU_15__LDS_MASK 0xf00
#define SPI_RESOURCE_RESERVE_CU_15__LDS__SHIFT 0x8
#define SPI_RESOURCE_RESERVE_CU_15__WAVES_MASK 0x7000
#define SPI_RESOURCE_RESERVE_CU_15__WAVES__SHIFT 0xc
#define SPI_RESOURCE_RESERVE_CU_15__BARRIERS_MASK 0x78000
#define SPI_RESOURCE_RESERVE_CU_15__BARRIERS__SHIFT 0xf
#define SPI_RESOURCE_RESERVE_EN_CU_0__EN_MASK 0x1
#define SPI_RESOURCE_RESERVE_EN_CU_0__EN__SHIFT 0x0
#define SPI_RESOURCE_RESERVE_EN_CU_0__TYPE_MASK_MASK 0xfffe
#define SPI_RESOURCE_RESERVE_EN_CU_0__TYPE_MASK__SHIFT 0x1
#define SPI_RESOURCE_RESERVE_EN_CU_0__QUEUE_MASK_MASK 0xff0000
#define SPI_RESOURCE_RESERVE_EN_CU_0__QUEUE_MASK__SHIFT 0x10
#define SPI_RESOURCE_RESERVE_EN_CU_0__RESERVE_SPACE_ONLY_MASK 0x1000000
#define SPI_RESOURCE_RESERVE_EN_CU_0__RESERVE_SPACE_ONLY__SHIFT 0x18
#define SPI_RESOURCE_RESERVE_EN_CU_1__EN_MASK 0x1
#define SPI_RESOURCE_RESERVE_EN_CU_1__EN__SHIFT 0x0
#define SPI_RESOURCE_RESERVE_EN_CU_1__TYPE_MASK_MASK 0xfffe
#define SPI_RESOURCE_RESERVE_EN_CU_1__TYPE_MASK__SHIFT 0x1
#define SPI_RESOURCE_RESERVE_EN_CU_1__QUEUE_MASK_MASK 0xff0000
#define SPI_RESOURCE_RESERVE_EN_CU_1__QUEUE_MASK__SHIFT 0x10
#define SPI_RESOURCE_RESERVE_EN_CU_1__RESERVE_SPACE_ONLY_MASK 0x1000000
#define SPI_RESOURCE_RESERVE_EN_CU_1__RESERVE_SPACE_ONLY__SHIFT 0x18
#define SPI_RESOURCE_RESERVE_EN_CU_2__EN_MASK 0x1
#define SPI_RESOURCE_RESERVE_EN_CU_2__EN__SHIFT 0x0
#define SPI_RESOURCE_RESERVE_EN_CU_2__TYPE_MASK_MASK 0xfffe
#define SPI_RESOURCE_RESERVE_EN_CU_2__TYPE_MASK__SHIFT 0x1
#define SPI_RESOURCE_RESERVE_EN_CU_2__QUEUE_MASK_MASK 0xff0000
#define SPI_RESOURCE_RESERVE_EN_CU_2__QUEUE_MASK__SHIFT 0x10
#define SPI_RESOURCE_RESERVE_EN_CU_2__RESERVE_SPACE_ONLY_MASK 0x1000000
#define SPI_RESOURCE_RESERVE_EN_CU_2__RESERVE_SPACE_ONLY__SHIFT 0x18
#define SPI_RESOURCE_RESERVE_EN_CU_3__EN_MASK 0x1
#define SPI_RESOURCE_RESERVE_EN_CU_3__EN__SHIFT 0x0
#define SPI_RESOURCE_RESERVE_EN_CU_3__TYPE_MASK_MASK 0xfffe
#define SPI_RESOURCE_RESERVE_EN_CU_3__TYPE_MASK__SHIFT 0x1
#define SPI_RESOURCE_RESERVE_EN_CU_3__QUEUE_MASK_MASK 0xff0000
#define SPI_RESOURCE_RESERVE_EN_CU_3__QUEUE_MASK__SHIFT 0x10
#define SPI_RESOURCE_RESERVE_EN_CU_3__RESERVE_SPACE_ONLY_MASK 0x1000000
#define SPI_RESOURCE_RESERVE_EN_CU_3__RESERVE_SPACE_ONLY__SHIFT 0x18
#define SPI_RESOURCE_RESERVE_EN_CU_4__EN_MASK 0x1
#define SPI_RESOURCE_RESERVE_EN_CU_4__EN__SHIFT 0x0
#define SPI_RESOURCE_RESERVE_EN_CU_4__TYPE_MASK_MASK 0xfffe
#define SPI_RESOURCE_RESERVE_EN_CU_4__TYPE_MASK__SHIFT 0x1
#define SPI_RESOURCE_RESERVE_EN_CU_4__QUEUE_MASK_MASK 0xff0000
#define SPI_RESOURCE_RESERVE_EN_CU_4__QUEUE_MASK__SHIFT 0x10
#define SPI_RESOURCE_RESERVE_EN_CU_4__RESERVE_SPACE_ONLY_MASK 0x1000000
#define SPI_RESOURCE_RESERVE_EN_CU_4__RESERVE_SPACE_ONLY__SHIFT 0x18
#define SPI_RESOURCE_RESERVE_EN_CU_5__EN_MASK 0x1
#define SPI_RESOURCE_RESERVE_EN_CU_5__EN__SHIFT 0x0
#define SPI_RESOURCE_RESERVE_EN_CU_5__TYPE_MASK_MASK 0xfffe
#define SPI_RESOURCE_RESERVE_EN_CU_5__TYPE_MASK__SHIFT 0x1
#define SPI_RESOURCE_RESERVE_EN_CU_5__QUEUE_MASK_MASK 0xff0000
#define SPI_RESOURCE_RESERVE_EN_CU_5__QUEUE_MASK__SHIFT 0x10
#define SPI_RESOURCE_RESERVE_EN_CU_5__RESERVE_SPACE_ONLY_MASK 0x1000000
#define SPI_RESOURCE_RESERVE_EN_CU_5__RESERVE_SPACE_ONLY__SHIFT 0x18
#define SPI_RESOURCE_RESERVE_EN_CU_6__EN_MASK 0x1
#define SPI_RESOURCE_RESERVE_EN_CU_6__EN__SHIFT 0x0
#define SPI_RESOURCE_RESERVE_EN_CU_6__TYPE_MASK_MASK 0xfffe
#define SPI_RESOURCE_RESERVE_EN_CU_6__TYPE_MASK__SHIFT 0x1
#define SPI_RESOURCE_RESERVE_EN_CU_6__QUEUE_MASK_MASK 0xff0000
#define SPI_RESOURCE_RESERVE_EN_CU_6__QUEUE_MASK__SHIFT 0x10
#define SPI_RESOURCE_RESERVE_EN_CU_6__RESERVE_SPACE_ONLY_MASK 0x1000000
#define SPI_RESOURCE_RESERVE_EN_CU_6__RESERVE_SPACE_ONLY__SHIFT 0x18
#define SPI_RESOURCE_RESERVE_EN_CU_7__EN_MASK 0x1
#define SPI_RESOURCE_RESERVE_EN_CU_7__EN__SHIFT 0x0
#define SPI_RESOURCE_RESERVE_EN_CU_7__TYPE_MASK_MASK 0xfffe
#define SPI_RESOURCE_RESERVE_EN_CU_7__TYPE_MASK__SHIFT 0x1
#define SPI_RESOURCE_RESERVE_EN_CU_7__QUEUE_MASK_MASK 0xff0000
#define SPI_RESOURCE_RESERVE_EN_CU_7__QUEUE_MASK__SHIFT 0x10
#define SPI_RESOURCE_RESERVE_EN_CU_7__RESERVE_SPACE_ONLY_MASK 0x1000000
#define SPI_RESOURCE_RESERVE_EN_CU_7__RESERVE_SPACE_ONLY__SHIFT 0x18
#define SPI_RESOURCE_RESERVE_EN_CU_8__EN_MASK 0x1
#define SPI_RESOURCE_RESERVE_EN_CU_8__EN__SHIFT 0x0
#define SPI_RESOURCE_RESERVE_EN_CU_8__TYPE_MASK_MASK 0xfffe
#define SPI_RESOURCE_RESERVE_EN_CU_8__TYPE_MASK__SHIFT 0x1
#define SPI_RESOURCE_RESERVE_EN_CU_8__QUEUE_MASK_MASK 0xff0000
#define SPI_RESOURCE_RESERVE_EN_CU_8__QUEUE_MASK__SHIFT 0x10
#define SPI_RESOURCE_RESERVE_EN_CU_8__RESERVE_SPACE_ONLY_MASK 0x1000000
#define SPI_RESOURCE_RESERVE_EN_CU_8__RESERVE_SPACE_ONLY__SHIFT 0x18
#define SPI_RESOURCE_RESERVE_EN_CU_9__EN_MASK 0x1
#define SPI_RESOURCE_RESERVE_EN_CU_9__EN__SHIFT 0x0
#define SPI_RESOURCE_RESERVE_EN_CU_9__TYPE_MASK_MASK 0xfffe
#define SPI_RESOURCE_RESERVE_EN_CU_9__TYPE_MASK__SHIFT 0x1
#define SPI_RESOURCE_RESERVE_EN_CU_9__QUEUE_MASK_MASK 0xff0000
#define SPI_RESOURCE_RESERVE_EN_CU_9__QUEUE_MASK__SHIFT 0x10
#define SPI_RESOURCE_RESERVE_EN_CU_9__RESERVE_SPACE_ONLY_MASK 0x1000000
#define SPI_RESOURCE_RESERVE_EN_CU_9__RESERVE_SPACE_ONLY__SHIFT 0x18
#define SPI_RESOURCE_RESERVE_EN_CU_10__EN_MASK 0x1
#define SPI_RESOURCE_RESERVE_EN_CU_10__EN__SHIFT 0x0
#define SPI_RESOURCE_RESERVE_EN_CU_10__TYPE_MASK_MASK 0xfffe
#define SPI_RESOURCE_RESERVE_EN_CU_10__TYPE_MASK__SHIFT 0x1
#define SPI_RESOURCE_RESERVE_EN_CU_10__QUEUE_MASK_MASK 0xff0000
#define SPI_RESOURCE_RESERVE_EN_CU_10__QUEUE_MASK__SHIFT 0x10
#define SPI_RESOURCE_RESERVE_EN_CU_10__RESERVE_SPACE_ONLY_MASK 0x1000000
#define SPI_RESOURCE_RESERVE_EN_CU_10__RESERVE_SPACE_ONLY__SHIFT 0x18
#define SPI_RESOURCE_RESERVE_EN_CU_11__EN_MASK 0x1
#define SPI_RESOURCE_RESERVE_EN_CU_11__EN__SHIFT 0x0
#define SPI_RESOURCE_RESERVE_EN_CU_11__TYPE_MASK_MASK 0xfffe
#define SPI_RESOURCE_RESERVE_EN_CU_11__TYPE_MASK__SHIFT 0x1
#define SPI_RESOURCE_RESERVE_EN_CU_11__QUEUE_MASK_MASK 0xff0000
#define SPI_RESOURCE_RESERVE_EN_CU_11__QUEUE_MASK__SHIFT 0x10
#define SPI_RESOURCE_RESERVE_EN_CU_11__RESERVE_SPACE_ONLY_MASK 0x1000000
#define SPI_RESOURCE_RESERVE_EN_CU_11__RESERVE_SPACE_ONLY__SHIFT 0x18
#define SPI_RESOURCE_RESERVE_EN_CU_12__EN_MASK 0x1
#define SPI_RESOURCE_RESERVE_EN_CU_12__EN__SHIFT 0x0
#define SPI_RESOURCE_RESERVE_EN_CU_12__TYPE_MASK_MASK 0xfffe
#define SPI_RESOURCE_RESERVE_EN_CU_12__TYPE_MASK__SHIFT 0x1
#define SPI_RESOURCE_RESERVE_EN_CU_12__QUEUE_MASK_MASK 0xff0000
#define SPI_RESOURCE_RESERVE_EN_CU_12__QUEUE_MASK__SHIFT 0x10
#define SPI_RESOURCE_RESERVE_EN_CU_12__RESERVE_SPACE_ONLY_MASK 0x1000000
#define SPI_RESOURCE_RESERVE_EN_CU_12__RESERVE_SPACE_ONLY__SHIFT 0x18
#define SPI_RESOURCE_RESERVE_EN_CU_13__EN_MASK 0x1
#define SPI_RESOURCE_RESERVE_EN_CU_13__EN__SHIFT 0x0
#define SPI_RESOURCE_RESERVE_EN_CU_13__TYPE_MASK_MASK 0xfffe
#define SPI_RESOURCE_RESERVE_EN_CU_13__TYPE_MASK__SHIFT 0x1
#define SPI_RESOURCE_RESERVE_EN_CU_13__QUEUE_MASK_MASK 0xff0000
#define SPI_RESOURCE_RESERVE_EN_CU_13__QUEUE_MASK__SHIFT 0x10
#define SPI_RESOURCE_RESERVE_EN_CU_13__RESERVE_SPACE_ONLY_MASK 0x1000000
#define SPI_RESOURCE_RESERVE_EN_CU_13__RESERVE_SPACE_ONLY__SHIFT 0x18
#define SPI_RESOURCE_RESERVE_EN_CU_14__EN_MASK 0x1
#define SPI_RESOURCE_RESERVE_EN_CU_14__EN__SHIFT 0x0
#define SPI_RESOURCE_RESERVE_EN_CU_14__TYPE_MASK_MASK 0xfffe
#define SPI_RESOURCE_RESERVE_EN_CU_14__TYPE_MASK__SHIFT 0x1
#define SPI_RESOURCE_RESERVE_EN_CU_14__QUEUE_MASK_MASK 0xff0000
#define SPI_RESOURCE_RESERVE_EN_CU_14__QUEUE_MASK__SHIFT 0x10
#define SPI_RESOURCE_RESERVE_EN_CU_14__RESERVE_SPACE_ONLY_MASK 0x1000000
#define SPI_RESOURCE_RESERVE_EN_CU_14__RESERVE_SPACE_ONLY__SHIFT 0x18
#define SPI_RESOURCE_RESERVE_EN_CU_15__EN_MASK 0x1
#define SPI_RESOURCE_RESERVE_EN_CU_15__EN__SHIFT 0x0
#define SPI_RESOURCE_RESERVE_EN_CU_15__TYPE_MASK_MASK 0xfffe
#define SPI_RESOURCE_RESERVE_EN_CU_15__TYPE_MASK__SHIFT 0x1
#define SPI_RESOURCE_RESERVE_EN_CU_15__QUEUE_MASK_MASK 0xff0000
#define SPI_RESOURCE_RESERVE_EN_CU_15__QUEUE_MASK__SHIFT 0x10
#define SPI_RESOURCE_RESERVE_EN_CU_15__RESERVE_SPACE_ONLY_MASK 0x1000000
#define SPI_RESOURCE_RESERVE_EN_CU_15__RESERVE_SPACE_ONLY__SHIFT 0x18
#define SPI_COMPUTE_WF_CTX_SAVE__INITIATE_MASK 0x1
#define SPI_COMPUTE_WF_CTX_SAVE__INITIATE__SHIFT 0x0
#define SPI_COMPUTE_WF_CTX_SAVE__GDS_INTERRUPT_EN_MASK 0x2
#define SPI_COMPUTE_WF_CTX_SAVE__GDS_INTERRUPT_EN__SHIFT 0x1
#define SPI_COMPUTE_WF_CTX_SAVE__DONE_INTERRUPT_EN_MASK 0x4
#define SPI_COMPUTE_WF_CTX_SAVE__DONE_INTERRUPT_EN__SHIFT 0x2
#define SPI_COMPUTE_WF_CTX_SAVE__GDS_REQ_BUSY_MASK 0x40000000
#define SPI_COMPUTE_WF_CTX_SAVE__GDS_REQ_BUSY__SHIFT 0x1e
#define SPI_COMPUTE_WF_CTX_SAVE__SAVE_BUSY_MASK 0x80000000
#define SPI_COMPUTE_WF_CTX_SAVE__SAVE_BUSY__SHIFT 0x1f
#define SPI_PS_MAX_WAVE_ID__MAX_WAVE_ID_MASK 0xfff
#define SPI_PS_MAX_WAVE_ID__MAX_WAVE_ID__SHIFT 0x0
#define SPI_START_PHASE__VGPR_START_PHASE_MASK 0x3
#define SPI_START_PHASE__VGPR_START_PHASE__SHIFT 0x0
#define SPI_START_PHASE__SGPR_START_PHASE_MASK 0xc
#define SPI_START_PHASE__SGPR_START_PHASE__SHIFT 0x2
#define SPI_START_PHASE__WAVE_START_PHASE_MASK 0x30
#define SPI_START_PHASE__WAVE_START_PHASE__SHIFT 0x4
#define SPI_GFX_CNTL__RESET_COUNTS_MASK 0x1
#define SPI_GFX_CNTL__RESET_COUNTS__SHIFT 0x0
#define SPI_CONFIG_CNTL__GPR_WRITE_PRIORITY_MASK 0x1fffff
#define SPI_CONFIG_CNTL__GPR_WRITE_PRIORITY__SHIFT 0x0
#define SPI_CONFIG_CNTL__EXP_PRIORITY_ORDER_MASK 0xe00000
#define SPI_CONFIG_CNTL__EXP_PRIORITY_ORDER__SHIFT 0x15
#define SPI_CONFIG_CNTL__ENABLE_SQG_TOP_EVENTS_MASK 0x1000000
#define SPI_CONFIG_CNTL__ENABLE_SQG_TOP_EVENTS__SHIFT 0x18
#define SPI_CONFIG_CNTL__ENABLE_SQG_BOP_EVENTS_MASK 0x2000000
#define SPI_CONFIG_CNTL__ENABLE_SQG_BOP_EVENTS__SHIFT 0x19
#define SPI_CONFIG_CNTL__RSRC_MGMT_RESET_MASK 0x4000000
#define SPI_CONFIG_CNTL__RSRC_MGMT_RESET__SHIFT 0x1a
#define SPI_CONFIG_CNTL__TTRACE_STALL_ALL_MASK 0x8000000
#define SPI_CONFIG_CNTL__TTRACE_STALL_ALL__SHIFT 0x1b
#define SPI_DEBUG_CNTL__DEBUG_GRBM_OVERRIDE_MASK 0x1
#define SPI_DEBUG_CNTL__DEBUG_GRBM_OVERRIDE__SHIFT 0x0
#define SPI_DEBUG_CNTL__DEBUG_THREAD_TYPE_SEL_MASK 0xe
#define SPI_DEBUG_CNTL__DEBUG_THREAD_TYPE_SEL__SHIFT 0x1
#define SPI_DEBUG_CNTL__DEBUG_GROUP_SEL_MASK 0x3f0
#define SPI_DEBUG_CNTL__DEBUG_GROUP_SEL__SHIFT 0x4
#define SPI_DEBUG_CNTL__DEBUG_SIMD_SEL_MASK 0xfc00
#define SPI_DEBUG_CNTL__DEBUG_SIMD_SEL__SHIFT 0xa
#define SPI_DEBUG_CNTL__DEBUG_SH_SEL_MASK 0x10000
#define SPI_DEBUG_CNTL__DEBUG_SH_SEL__SHIFT 0x10
#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_0_MASK 0x20000
#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_0__SHIFT 0x11
#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_1_MASK 0x40000
#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_1__SHIFT 0x12
#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_2_MASK 0x80000
#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_2__SHIFT 0x13
#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_3_MASK 0x100000
#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_3__SHIFT 0x14
#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_4_MASK 0x200000
#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_4__SHIFT 0x15
#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_5_MASK 0x400000
#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_5__SHIFT 0x16
#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_6_MASK 0x800000
#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_6__SHIFT 0x17
#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_7_MASK 0x1000000
#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_7__SHIFT 0x18
#define SPI_DEBUG_CNTL__DEBUG_PIPE_SEL_MASK 0xe000000
#define SPI_DEBUG_CNTL__DEBUG_PIPE_SEL__SHIFT 0x19
#define SPI_DEBUG_CNTL__DEBUG_REG_EN_MASK 0x80000000
#define SPI_DEBUG_CNTL__DEBUG_REG_EN__SHIFT 0x1f
#define SPI_DEBUG_READ__DATA_MASK 0xffffff
#define SPI_DEBUG_READ__DATA__SHIFT 0x0
#define SPI_DSM_CNTL__Sel_DSM_SPI_Irritator_data0_MASK 0x1
#define SPI_DSM_CNTL__Sel_DSM_SPI_Irritator_data0__SHIFT 0x0
#define SPI_DSM_CNTL__Sel_DSM_SPI_Irritator_data1_MASK 0x2
#define SPI_DSM_CNTL__Sel_DSM_SPI_Irritator_data1__SHIFT 0x1
#define SPI_DSM_CNTL__SPI_Enable_Single_Write_MASK 0x4
#define SPI_DSM_CNTL__SPI_Enable_Single_Write__SHIFT 0x2
#define SPI_DSM_CNTL__UNUSED_MASK 0xfffffff8
#define SPI_DSM_CNTL__UNUSED__SHIFT 0x3
#define SPI_EDC_CNT__SED_MASK 0xff
#define SPI_EDC_CNT__SED__SHIFT 0x0
#define SPI_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x3ff
#define SPI_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
#define SPI_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0xffc00
#define SPI_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
#define SPI_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000
#define SPI_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
#define SPI_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x3ff
#define SPI_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
#define SPI_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0xffc00
#define SPI_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa
#define SPI_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0xf00000
#define SPI_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14
#define SPI_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x3ff
#define SPI_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0
#define SPI_PERFCOUNTER2_SELECT__PERF_SEL1_MASK 0xffc00
#define SPI_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT 0xa
#define SPI_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0xf00000
#define SPI_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14
#define SPI_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x3ff
#define SPI_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0
#define SPI_PERFCOUNTER3_SELECT__PERF_SEL1_MASK 0xffc00
#define SPI_PERFCOUNTER3_SELECT__PERF_SEL1__SHIFT 0xa
#define SPI_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0xf00000
#define SPI_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14
#define SPI_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x3ff
#define SPI_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0
#define SPI_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0xffc00
#define SPI_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
#define SPI_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x3ff
#define SPI_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0
#define SPI_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0xffc00
#define SPI_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa
#define SPI_PERFCOUNTER2_SELECT1__PERF_SEL2_MASK 0x3ff
#define SPI_PERFCOUNTER2_SELECT1__PERF_SEL2__SHIFT 0x0
#define SPI_PERFCOUNTER2_SELECT1__PERF_SEL3_MASK 0xffc00
#define SPI_PERFCOUNTER2_SELECT1__PERF_SEL3__SHIFT 0xa
#define SPI_PERFCOUNTER3_SELECT1__PERF_SEL2_MASK 0x3ff
#define SPI_PERFCOUNTER3_SELECT1__PERF_SEL2__SHIFT 0x0
#define SPI_PERFCOUNTER3_SELECT1__PERF_SEL3_MASK 0xffc00
#define SPI_PERFCOUNTER3_SELECT1__PERF_SEL3__SHIFT 0xa
#define SPI_PERFCOUNTER4_SELECT__PERF_SEL_MASK 0xff
#define SPI_PERFCOUNTER4_SELECT__PERF_SEL__SHIFT 0x0
#define SPI_PERFCOUNTER5_SELECT__PERF_SEL_MASK 0xff
#define SPI_PERFCOUNTER5_SELECT__PERF_SEL__SHIFT 0x0
#define SPI_PERFCOUNTER_BINS__BIN0_MIN_MASK 0xf
#define SPI_PERFCOUNTER_BINS__BIN0_MIN__SHIFT 0x0
#define SPI_PERFCOUNTER_BINS__BIN0_MAX_MASK 0xf0
#define SPI_PERFCOUNTER_BINS__BIN0_MAX__SHIFT 0x4
#define SPI_PERFCOUNTER_BINS__BIN1_MIN_MASK 0xf00
#define SPI_PERFCOUNTER_BINS__BIN1_MIN__SHIFT 0x8
#define SPI_PERFCOUNTER_BINS__BIN1_MAX_MASK 0xf000
#define SPI_PERFCOUNTER_BINS__BIN1_MAX__SHIFT 0xc
#define SPI_PERFCOUNTER_BINS__BIN2_MIN_MASK 0xf0000
#define SPI_PERFCOUNTER_BINS__BIN2_MIN__SHIFT 0x10
#define SPI_PERFCOUNTER_BINS__BIN2_MAX_MASK 0xf00000
#define SPI_PERFCOUNTER_BINS__BIN2_MAX__SHIFT 0x14
#define SPI_PERFCOUNTER_BINS__BIN3_MIN_MASK 0xf000000
#define SPI_PERFCOUNTER_BINS__BIN3_MIN__SHIFT 0x18
#define SPI_PERFCOUNTER_BINS__BIN3_MAX_MASK 0xf0000000
#define SPI_PERFCOUNTER_BINS__BIN3_MAX__SHIFT 0x1c
#define SPI_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff
#define SPI_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
#define SPI_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff
#define SPI_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
#define SPI_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff
#define SPI_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
#define SPI_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff
#define SPI_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
#define SPI_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffff
#define SPI_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0
#define SPI_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffff
#define SPI_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0
#define SPI_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffff
#define SPI_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0
#define SPI_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffff
#define SPI_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0
#define SPI_PERFCOUNTER4_HI__PERFCOUNTER_HI_MASK 0xffffffff
#define SPI_PERFCOUNTER4_HI__PERFCOUNTER_HI__SHIFT 0x0
#define SPI_PERFCOUNTER4_LO__PERFCOUNTER_LO_MASK 0xffffffff
#define SPI_PERFCOUNTER4_LO__PERFCOUNTER_LO__SHIFT 0x0
#define SPI_PERFCOUNTER5_HI__PERFCOUNTER_HI_MASK 0xffffffff
#define SPI_PERFCOUNTER5_HI__PERFCOUNTER_HI__SHIFT 0x0
#define SPI_PERFCOUNTER5_LO__PERFCOUNTER_LO_MASK 0xffffffff
#define SPI_PERFCOUNTER5_LO__PERFCOUNTER_LO__SHIFT 0x0
#define SPI_CONFIG_CNTL_1__VTX_DONE_DELAY_MASK 0xf
#define SPI_CONFIG_CNTL_1__VTX_DONE_DELAY__SHIFT 0x0
#define SPI_CONFIG_CNTL_1__INTERP_ONE_PRIM_PER_ROW_MASK 0x10
#define SPI_CONFIG_CNTL_1__INTERP_ONE_PRIM_PER_ROW__SHIFT 0x4
#define SPI_CONFIG_CNTL_1__PC_LIMIT_ENABLE_MASK 0x40
#define SPI_CONFIG_CNTL_1__PC_LIMIT_ENABLE__SHIFT 0x6
#define SPI_CONFIG_CNTL_1__PC_LIMIT_STRICT_MASK 0x80
#define SPI_CONFIG_CNTL_1__PC_LIMIT_STRICT__SHIFT 0x7
#define SPI_CONFIG_CNTL_1__CRC_SIMD_ID_WADDR_DISABLE_MASK 0x100
#define SPI_CONFIG_CNTL_1__CRC_SIMD_ID_WADDR_DISABLE__SHIFT 0x8
#define SPI_CONFIG_CNTL_1__LBPW_CU_CHK_MODE_MASK 0x200
#define SPI_CONFIG_CNTL_1__LBPW_CU_CHK_MODE__SHIFT 0x9
#define SPI_CONFIG_CNTL_1__LBPW_CU_CHK_CNT_MASK 0x3c00
#define SPI_CONFIG_CNTL_1__LBPW_CU_CHK_CNT__SHIFT 0xa
#define SPI_CONFIG_CNTL_1__PC_LIMIT_SIZE_MASK 0xffff0000
#define SPI_CONFIG_CNTL_1__PC_LIMIT_SIZE__SHIFT 0x10
#define SPI_DEBUG_BUSY__LS_BUSY_MASK 0x1
#define SPI_DEBUG_BUSY__LS_BUSY__SHIFT 0x0
#define SPI_DEBUG_BUSY__HS_BUSY_MASK 0x2
#define SPI_DEBUG_BUSY__HS_BUSY__SHIFT 0x1
#define SPI_DEBUG_BUSY__ES_BUSY_MASK 0x4
#define SPI_DEBUG_BUSY__ES_BUSY__SHIFT 0x2
#define SPI_DEBUG_BUSY__GS_BUSY_MASK 0x8
#define SPI_DEBUG_BUSY__GS_BUSY__SHIFT 0x3
#define SPI_DEBUG_BUSY__VS_BUSY_MASK 0x10
#define SPI_DEBUG_BUSY__VS_BUSY__SHIFT 0x4
#define SPI_DEBUG_BUSY__PS0_BUSY_MASK 0x20
#define SPI_DEBUG_BUSY__PS0_BUSY__SHIFT 0x5
#define SPI_DEBUG_BUSY__PS1_BUSY_MASK 0x40
#define SPI_DEBUG_BUSY__PS1_BUSY__SHIFT 0x6
#define SPI_DEBUG_BUSY__CSG_BUSY_MASK 0x80
#define SPI_DEBUG_BUSY__CSG_BUSY__SHIFT 0x7
#define SPI_DEBUG_BUSY__CS0_BUSY_MASK 0x100
#define SPI_DEBUG_BUSY__CS0_BUSY__SHIFT 0x8
#define SPI_DEBUG_BUSY__CS1_BUSY_MASK 0x200
#define SPI_DEBUG_BUSY__CS1_BUSY__SHIFT 0x9
#define SPI_DEBUG_BUSY__CS2_BUSY_MASK 0x400
#define SPI_DEBUG_BUSY__CS2_BUSY__SHIFT 0xa
#define SPI_DEBUG_BUSY__CS3_BUSY_MASK 0x800
#define SPI_DEBUG_BUSY__CS3_BUSY__SHIFT 0xb
#define SPI_DEBUG_BUSY__CS4_BUSY_MASK 0x1000
#define SPI_DEBUG_BUSY__CS4_BUSY__SHIFT 0xc
#define SPI_DEBUG_BUSY__CS5_BUSY_MASK 0x2000
#define SPI_DEBUG_BUSY__CS5_BUSY__SHIFT 0xd
#define SPI_DEBUG_BUSY__CS6_BUSY_MASK 0x4000
#define SPI_DEBUG_BUSY__CS6_BUSY__SHIFT 0xe
#define SPI_DEBUG_BUSY__CS7_BUSY_MASK 0x8000
#define SPI_DEBUG_BUSY__CS7_BUSY__SHIFT 0xf
#define SPI_DEBUG_BUSY__LDS_WR_CTL0_BUSY_MASK 0x10000
#define SPI_DEBUG_BUSY__LDS_WR_CTL0_BUSY__SHIFT 0x10
#define SPI_DEBUG_BUSY__LDS_WR_CTL1_BUSY_MASK 0x20000
#define SPI_DEBUG_BUSY__LDS_WR_CTL1_BUSY__SHIFT 0x11
#define SPI_DEBUG_BUSY__RSRC_ALLOC0_BUSY_MASK 0x40000
#define SPI_DEBUG_BUSY__RSRC_ALLOC0_BUSY__SHIFT 0x12
#define SPI_DEBUG_BUSY__RSRC_ALLOC1_BUSY_MASK 0x80000
#define SPI_DEBUG_BUSY__RSRC_ALLOC1_BUSY__SHIFT 0x13
#define SPI_DEBUG_BUSY__PC_DEALLOC_BUSY_MASK 0x100000
#define SPI_DEBUG_BUSY__PC_DEALLOC_BUSY__SHIFT 0x14
#define SPI_DEBUG_BUSY__EVENT_CLCTR_BUSY_MASK 0x200000
#define SPI_DEBUG_BUSY__EVENT_CLCTR_BUSY__SHIFT 0x15
#define SPI_DEBUG_BUSY__GRBM_BUSY_MASK 0x400000
#define SPI_DEBUG_BUSY__GRBM_BUSY__SHIFT 0x16
#define SPI_DEBUG_BUSY__SPIS_BUSY_MASK 0x800000
#define SPI_DEBUG_BUSY__SPIS_BUSY__SHIFT 0x17
#define SPI_CONFIG_CNTL_2__CONTEXT_SAVE_WAIT_GDS_REQUEST_CYCLE_OVHD_MASK 0xf
#define SPI_CONFIG_CNTL_2__CONTEXT_SAVE_WAIT_GDS_REQUEST_CYCLE_OVHD__SHIFT 0x0
#define SPI_CONFIG_CNTL_2__CONTEXT_SAVE_WAIT_GDS_GRANT_CYCLE_OVHD_MASK 0xf0
#define SPI_CONFIG_CNTL_2__CONTEXT_SAVE_WAIT_GDS_GRANT_CYCLE_OVHD__SHIFT 0x4
#define CGTS_SM_CTRL_REG__ON_SEQ_DELAY_MASK 0xf
#define CGTS_SM_CTRL_REG__ON_SEQ_DELAY__SHIFT 0x0
#define CGTS_SM_CTRL_REG__OFF_SEQ_DELAY_MASK 0xff0
#define CGTS_SM_CTRL_REG__OFF_SEQ_DELAY__SHIFT 0x4
#define CGTS_SM_CTRL_REG__MGCG_ENABLED_MASK 0x1000
#define CGTS_SM_CTRL_REG__MGCG_ENABLED__SHIFT 0xc
#define CGTS_SM_CTRL_REG__BASE_MODE_MASK 0x10000
#define CGTS_SM_CTRL_REG__BASE_MODE__SHIFT 0x10
#define CGTS_SM_CTRL_REG__SM_MODE_MASK 0xe0000
#define CGTS_SM_CTRL_REG__SM_MODE__SHIFT 0x11
#define CGTS_SM_CTRL_REG__SM_MODE_ENABLE_MASK 0x100000
#define CGTS_SM_CTRL_REG__SM_MODE_ENABLE__SHIFT 0x14
#define CGTS_SM_CTRL_REG__OVERRIDE_MASK 0x200000
#define CGTS_SM_CTRL_REG__OVERRIDE__SHIFT 0x15
#define CGTS_SM_CTRL_REG__LS_OVERRIDE_MASK 0x400000
#define CGTS_SM_CTRL_REG__LS_OVERRIDE__SHIFT 0x16
#define CGTS_SM_CTRL_REG__ON_MONITOR_ADD_EN_MASK 0x800000
#define CGTS_SM_CTRL_REG__ON_MONITOR_ADD_EN__SHIFT 0x17
#define CGTS_SM_CTRL_REG__ON_MONITOR_ADD_MASK 0xff000000
#define CGTS_SM_CTRL_REG__ON_MONITOR_ADD__SHIFT 0x18
#define CGTS_RD_CTRL_REG__ROW_MUX_SEL_MASK 0x1f
#define CGTS_RD_CTRL_REG__ROW_MUX_SEL__SHIFT 0x0
#define CGTS_RD_CTRL_REG__REG_MUX_SEL_MASK 0x1f00
#define CGTS_RD_CTRL_REG__REG_MUX_SEL__SHIFT 0x8
#define CGTS_RD_REG__READ_DATA_MASK 0x3fff
#define CGTS_RD_REG__READ_DATA__SHIFT 0x0
#define CGTS_TCC_DISABLE__TCC_DISABLE_MASK 0xffff0000
#define CGTS_TCC_DISABLE__TCC_DISABLE__SHIFT 0x10
#define CGTS_USER_TCC_DISABLE__TCC_DISABLE_MASK 0xffff0000
#define CGTS_USER_TCC_DISABLE__TCC_DISABLE__SHIFT 0x10
#define CGTS_CU0_SP0_CTRL_REG__SP00_MASK 0x7f
#define CGTS_CU0_SP0_CTRL_REG__SP00__SHIFT 0x0
#define CGTS_CU0_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x80
#define CGTS_CU0_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7
#define CGTS_CU0_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x300
#define CGTS_CU0_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8
#define CGTS_CU0_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x400
#define CGTS_CU0_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa
#define CGTS_CU0_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x800
#define CGTS_CU0_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb
#define CGTS_CU0_SP0_CTRL_REG__SP01_MASK 0x7f0000
#define CGTS_CU0_SP0_CTRL_REG__SP01__SHIFT 0x10
#define CGTS_CU0_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x800000
#define CGTS_CU0_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17
#define CGTS_CU0_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x3000000
#define CGTS_CU0_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18
#define CGTS_CU0_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x4000000
#define CGTS_CU0_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a
#define CGTS_CU0_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x8000000
#define CGTS_CU0_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b
#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_MASK 0x7f
#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0
#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x80
#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7
#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x300
#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8
#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x400
#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa
#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x800
#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb
#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_MASK 0x7f0000
#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10
#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x800000
#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17
#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x3000000
#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18
#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x4000000
#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a
#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x8000000
#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b
#define CGTS_CU0_TA_SQC_CTRL_REG__TA_MASK 0x7f
#define CGTS_CU0_TA_SQC_CTRL_REG__TA__SHIFT 0x0
#define CGTS_CU0_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x80
#define CGTS_CU0_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7
#define CGTS_CU0_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x300
#define CGTS_CU0_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8
#define CGTS_CU0_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x400
#define CGTS_CU0_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa
#define CGTS_CU0_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x800
#define CGTS_CU0_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb
#define CGTS_CU0_TA_SQC_CTRL_REG__SQC_MASK 0x7f0000
#define CGTS_CU0_TA_SQC_CTRL_REG__SQC__SHIFT 0x10
#define CGTS_CU0_TA_SQC_CTRL_REG__SQC_OVERRIDE_MASK 0x800000
#define CGTS_CU0_TA_SQC_CTRL_REG__SQC_OVERRIDE__SHIFT 0x17
#define CGTS_CU0_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE_MASK 0x3000000
#define CGTS_CU0_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE__SHIFT 0x18
#define CGTS_CU0_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE_MASK 0x4000000
#define CGTS_CU0_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE__SHIFT 0x1a
#define CGTS_CU0_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE_MASK 0x8000000
#define CGTS_CU0_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE__SHIFT 0x1b
#define CGTS_CU0_SP1_CTRL_REG__SP10_MASK 0x7f
#define CGTS_CU0_SP1_CTRL_REG__SP10__SHIFT 0x0
#define CGTS_CU0_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x80
#define CGTS_CU0_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7
#define CGTS_CU0_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x300
#define CGTS_CU0_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8
#define CGTS_CU0_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x400
#define CGTS_CU0_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa
#define CGTS_CU0_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x800
#define CGTS_CU0_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb
#define CGTS_CU0_SP1_CTRL_REG__SP11_MASK 0x7f0000
#define CGTS_CU0_SP1_CTRL_REG__SP11__SHIFT 0x10
#define CGTS_CU0_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x800000
#define CGTS_CU0_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17
#define CGTS_CU0_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x3000000
#define CGTS_CU0_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18
#define CGTS_CU0_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x4000000
#define CGTS_CU0_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a
#define CGTS_CU0_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x8000000
#define CGTS_CU0_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b
#define CGTS_CU0_TD_TCP_CTRL_REG__TD_MASK 0x7f
#define CGTS_CU0_TD_TCP_CTRL_REG__TD__SHIFT 0x0
#define CGTS_CU0_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x80
#define CGTS_CU0_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7
#define CGTS_CU0_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x300
#define CGTS_CU0_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8
#define CGTS_CU0_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x400
#define CGTS_CU0_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa
#define CGTS_CU0_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x800
#define CGTS_CU0_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb
#define CGTS_CU0_TD_TCP_CTRL_REG__TCP_MASK 0x7f0000
#define CGTS_CU0_TD_TCP_CTRL_REG__TCP__SHIFT 0x10
#define CGTS_CU0_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK 0x800000
#define CGTS_CU0_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT 0x17
#define CGTS_CU0_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK 0x3000000
#define CGTS_CU0_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT 0x18
#define CGTS_CU0_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK 0x4000000
#define CGTS_CU0_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT 0x1a
#define CGTS_CU0_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK 0x8000000
#define CGTS_CU0_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT 0x1b
#define CGTS_CU1_SP0_CTRL_REG__SP00_MASK 0x7f
#define CGTS_CU1_SP0_CTRL_REG__SP00__SHIFT 0x0
#define CGTS_CU1_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x80
#define CGTS_CU1_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7
#define CGTS_CU1_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x300
#define CGTS_CU1_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8
#define CGTS_CU1_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x400
#define CGTS_CU1_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa
#define CGTS_CU1_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x800
#define CGTS_CU1_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb
#define CGTS_CU1_SP0_CTRL_REG__SP01_MASK 0x7f0000
#define CGTS_CU1_SP0_CTRL_REG__SP01__SHIFT 0x10
#define CGTS_CU1_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x800000
#define CGTS_CU1_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17
#define CGTS_CU1_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x3000000
#define CGTS_CU1_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18
#define CGTS_CU1_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x4000000
#define CGTS_CU1_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a
#define CGTS_CU1_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x8000000
#define CGTS_CU1_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b
#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_MASK 0x7f
#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0
#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x80
#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7
#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x300
#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8
#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x400
#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa
#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x800
#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb
#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_MASK 0x7f0000
#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10
#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x800000
#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17
#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x3000000
#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18
#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x4000000
#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a
#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x8000000
#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b
#define CGTS_CU1_TA_CTRL_REG__TA_MASK 0x7f
#define CGTS_CU1_TA_CTRL_REG__TA__SHIFT 0x0
#define CGTS_CU1_TA_CTRL_REG__TA_OVERRIDE_MASK 0x80
#define CGTS_CU1_TA_CTRL_REG__TA_OVERRIDE__SHIFT 0x7
#define CGTS_CU1_TA_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x300
#define CGTS_CU1_TA_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8
#define CGTS_CU1_TA_CTRL_REG__TA_LS_OVERRIDE_MASK 0x400
#define CGTS_CU1_TA_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa
#define CGTS_CU1_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x800
#define CGTS_CU1_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb
#define CGTS_CU1_SP1_CTRL_REG__SP10_MASK 0x7f
#define CGTS_CU1_SP1_CTRL_REG__SP10__SHIFT 0x0
#define CGTS_CU1_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x80
#define CGTS_CU1_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7
#define CGTS_CU1_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x300
#define CGTS_CU1_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8
#define CGTS_CU1_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x400
#define CGTS_CU1_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa
#define CGTS_CU1_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x800
#define CGTS_CU1_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb
#define CGTS_CU1_SP1_CTRL_REG__SP11_MASK 0x7f0000
#define CGTS_CU1_SP1_CTRL_REG__SP11__SHIFT 0x10
#define CGTS_CU1_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x800000
#define CGTS_CU1_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17
#define CGTS_CU1_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x3000000
#define CGTS_CU1_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18
#define CGTS_CU1_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x4000000
#define CGTS_CU1_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a
#define CGTS_CU1_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x8000000
#define CGTS_CU1_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b
#define CGTS_CU1_TD_TCP_CTRL_REG__TD_MASK 0x7f
#define CGTS_CU1_TD_TCP_CTRL_REG__TD__SHIFT 0x0
#define CGTS_CU1_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x80
#define CGTS_CU1_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7
#define CGTS_CU1_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x300
#define CGTS_CU1_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8
#define CGTS_CU1_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x400
#define CGTS_CU1_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa
#define CGTS_CU1_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x800
#define CGTS_CU1_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb
#define CGTS_CU1_TD_TCP_CTRL_REG__TCP_MASK 0x7f0000
#define CGTS_CU1_TD_TCP_CTRL_REG__TCP__SHIFT 0x10
#define CGTS_CU1_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK 0x800000
#define CGTS_CU1_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT 0x17
#define CGTS_CU1_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK 0x3000000
#define CGTS_CU1_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT 0x18
#define CGTS_CU1_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK 0x4000000
#define CGTS_CU1_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT 0x1a
#define CGTS_CU1_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK 0x8000000
#define CGTS_CU1_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT 0x1b
#define CGTS_CU2_SP0_CTRL_REG__SP00_MASK 0x7f
#define CGTS_CU2_SP0_CTRL_REG__SP00__SHIFT 0x0
#define CGTS_CU2_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x80
#define CGTS_CU2_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7
#define CGTS_CU2_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x300
#define CGTS_CU2_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8
#define CGTS_CU2_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x400
#define CGTS_CU2_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa
#define CGTS_CU2_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x800
#define CGTS_CU2_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb
#define CGTS_CU2_SP0_CTRL_REG__SP01_MASK 0x7f0000
#define CGTS_CU2_SP0_CTRL_REG__SP01__SHIFT 0x10
#define CGTS_CU2_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x800000
#define CGTS_CU2_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17
#define CGTS_CU2_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x3000000
#define CGTS_CU2_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18
#define CGTS_CU2_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x4000000
#define CGTS_CU2_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a
#define CGTS_CU2_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x8000000
#define CGTS_CU2_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b
#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_MASK 0x7f
#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0
#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x80
#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7
#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x300
#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8
#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x400
#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa
#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x800
#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb
#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_MASK 0x7f0000
#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10
#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x800000
#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17
#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x3000000
#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18
#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x4000000
#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a
#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x8000000
#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b
#define CGTS_CU2_TA_CTRL_REG__TA_MASK 0x7f
#define CGTS_CU2_TA_CTRL_REG__TA__SHIFT 0x0
#define CGTS_CU2_TA_CTRL_REG__TA_OVERRIDE_MASK 0x80
#define CGTS_CU2_TA_CTRL_REG__TA_OVERRIDE__SHIFT 0x7
#define CGTS_CU2_TA_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x300
#define CGTS_CU2_TA_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8
#define CGTS_CU2_TA_CTRL_REG__TA_LS_OVERRIDE_MASK 0x400
#define CGTS_CU2_TA_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa
#define CGTS_CU2_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x800
#define CGTS_CU2_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb
#define CGTS_CU2_SP1_CTRL_REG__SP10_MASK 0x7f
#define CGTS_CU2_SP1_CTRL_REG__SP10__SHIFT 0x0
#define CGTS_CU2_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x80
#define CGTS_CU2_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7
#define CGTS_CU2_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x300
#define CGTS_CU2_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8
#define CGTS_CU2_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x400
#define CGTS_CU2_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa
#define CGTS_CU2_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x800
#define CGTS_CU2_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb
#define CGTS_CU2_SP1_CTRL_REG__SP11_MASK 0x7f0000
#define CGTS_CU2_SP1_CTRL_REG__SP11__SHIFT 0x10
#define CGTS_CU2_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x800000
#define CGTS_CU2_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17
#define CGTS_CU2_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x3000000
#define CGTS_CU2_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18
#define CGTS_CU2_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x4000000
#define CGTS_CU2_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a
#define CGTS_CU2_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x8000000
#define CGTS_CU2_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b
#define CGTS_CU2_TD_TCP_CTRL_REG__TD_MASK 0x7f
#define CGTS_CU2_TD_TCP_CTRL_REG__TD__SHIFT 0x0
#define CGTS_CU2_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x80
#define CGTS_CU2_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7
#define CGTS_CU2_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x300
#define CGTS_CU2_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8
#define CGTS_CU2_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x400
#define CGTS_CU2_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa
#define CGTS_CU2_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x800
#define CGTS_CU2_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb
#define CGTS_CU2_TD_TCP_CTRL_REG__TCP_MASK 0x7f0000
#define CGTS_CU2_TD_TCP_CTRL_REG__TCP__SHIFT 0x10
#define CGTS_CU2_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK 0x800000
#define CGTS_CU2_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT 0x17
#define CGTS_CU2_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK 0x3000000
#define CGTS_CU2_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT 0x18
#define CGTS_CU2_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK 0x4000000
#define CGTS_CU2_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT 0x1a
#define CGTS_CU2_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK 0x8000000
#define CGTS_CU2_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT 0x1b
#define CGTS_CU3_SP0_CTRL_REG__SP00_MASK 0x7f
#define CGTS_CU3_SP0_CTRL_REG__SP00__SHIFT 0x0
#define CGTS_CU3_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x80
#define CGTS_CU3_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7
#define CGTS_CU3_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x300
#define CGTS_CU3_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8
#define CGTS_CU3_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x400
#define CGTS_CU3_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa
#define CGTS_CU3_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x800
#define CGTS_CU3_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb
#define CGTS_CU3_SP0_CTRL_REG__SP01_MASK 0x7f0000
#define CGTS_CU3_SP0_CTRL_REG__SP01__SHIFT 0x10
#define CGTS_CU3_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x800000
#define CGTS_CU3_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17
#define CGTS_CU3_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x3000000
#define CGTS_CU3_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18
#define CGTS_CU3_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x4000000
#define CGTS_CU3_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a
#define CGTS_CU3_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x8000000
#define CGTS_CU3_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b
#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_MASK 0x7f
#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0
#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x80
#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7
#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x300
#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8
#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x400
#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa
#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x800
#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb
#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_MASK 0x7f0000
#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10
#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x800000
#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17
#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x3000000
#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18
#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x4000000
#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a
#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x8000000
#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b
#define CGTS_CU3_TA_CTRL_REG__TA_MASK 0x7f
#define CGTS_CU3_TA_CTRL_REG__TA__SHIFT 0x0
#define CGTS_CU3_TA_CTRL_REG__TA_OVERRIDE_MASK 0x80
#define CGTS_CU3_TA_CTRL_REG__TA_OVERRIDE__SHIFT 0x7
#define CGTS_CU3_TA_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x300
#define CGTS_CU3_TA_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8
#define CGTS_CU3_TA_CTRL_REG__TA_LS_OVERRIDE_MASK 0x400
#define CGTS_CU3_TA_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa
#define CGTS_CU3_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x800
#define CGTS_CU3_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb
#define CGTS_CU3_SP1_CTRL_REG__SP10_MASK 0x7f
#define CGTS_CU3_SP1_CTRL_REG__SP10__SHIFT 0x0
#define CGTS_CU3_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x80
#define CGTS_CU3_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7
#define CGTS_CU3_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x300
#define CGTS_CU3_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8
#define CGTS_CU3_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x400
#define CGTS_CU3_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa
#define CGTS_CU3_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x800
#define CGTS_CU3_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb
#define CGTS_CU3_SP1_CTRL_REG__SP11_MASK 0x7f0000
#define CGTS_CU3_SP1_CTRL_REG__SP11__SHIFT 0x10
#define CGTS_CU3_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x800000
#define CGTS_CU3_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17
#define CGTS_CU3_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x3000000
#define CGTS_CU3_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18
#define CGTS_CU3_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x4000000
#define CGTS_CU3_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a
#define CGTS_CU3_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x8000000
#define CGTS_CU3_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b
#define CGTS_CU3_TD_TCP_CTRL_REG__TD_MASK 0x7f
#define CGTS_CU3_TD_TCP_CTRL_REG__TD__SHIFT 0x0
#define CGTS_CU3_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x80
#define CGTS_CU3_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7
#define CGTS_CU3_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x300
#define CGTS_CU3_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8
#define CGTS_CU3_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x400
#define CGTS_CU3_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa
#define CGTS_CU3_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x800
#define CGTS_CU3_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb
#define CGTS_CU3_TD_TCP_CTRL_REG__TCP_MASK 0x7f0000
#define CGTS_CU3_TD_TCP_CTRL_REG__TCP__SHIFT 0x10
#define CGTS_CU3_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK 0x800000
#define CGTS_CU3_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT 0x17
#define CGTS_CU3_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK 0x3000000
#define CGTS_CU3_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT 0x18
#define CGTS_CU3_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK 0x4000000
#define CGTS_CU3_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT 0x1a
#define CGTS_CU3_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK 0x8000000
#define CGTS_CU3_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT 0x1b
#define CGTS_CU4_SP0_CTRL_REG__SP00_MASK 0x7f
#define CGTS_CU4_SP0_CTRL_REG__SP00__SHIFT 0x0
#define CGTS_CU4_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x80
#define CGTS_CU4_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7
#define CGTS_CU4_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x300
#define CGTS_CU4_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8
#define CGTS_CU4_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x400
#define CGTS_CU4_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa
#define CGTS_CU4_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x800
#define CGTS_CU4_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb
#define CGTS_CU4_SP0_CTRL_REG__SP01_MASK 0x7f0000
#define CGTS_CU4_SP0_CTRL_REG__SP01__SHIFT 0x10
#define CGTS_CU4_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x800000
#define CGTS_CU4_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17
#define CGTS_CU4_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x3000000
#define CGTS_CU4_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18
#define CGTS_CU4_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x4000000
#define CGTS_CU4_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a
#define CGTS_CU4_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x8000000
#define CGTS_CU4_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b
#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_MASK 0x7f
#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0
#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x80
#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7
#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x300
#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8
#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x400
#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa
#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x800
#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb
#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_MASK 0x7f0000
#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10
#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x800000
#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17
#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x3000000
#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18
#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x4000000
#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a
#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x8000000
#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b
#define CGTS_CU4_TA_SQC_CTRL_REG__TA_MASK 0x7f
#define CGTS_CU4_TA_SQC_CTRL_REG__TA__SHIFT 0x0
#define CGTS_CU4_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x80
#define CGTS_CU4_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7
#define CGTS_CU4_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x300
#define CGTS_CU4_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8
#define CGTS_CU4_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x400
#define CGTS_CU4_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa
#define CGTS_CU4_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x800
#define CGTS_CU4_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb
#define CGTS_CU4_TA_SQC_CTRL_REG__SQC_MASK 0x7f0000
#define CGTS_CU4_TA_SQC_CTRL_REG__SQC__SHIFT 0x10
#define CGTS_CU4_TA_SQC_CTRL_REG__SQC_OVERRIDE_MASK 0x800000
#define CGTS_CU4_TA_SQC_CTRL_REG__SQC_OVERRIDE__SHIFT 0x17
#define CGTS_CU4_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE_MASK 0x3000000
#define CGTS_CU4_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE__SHIFT 0x18
#define CGTS_CU4_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE_MASK 0x4000000
#define CGTS_CU4_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE__SHIFT 0x1a
#define CGTS_CU4_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE_MASK 0x8000000
#define CGTS_CU4_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE__SHIFT 0x1b
#define CGTS_CU4_SP1_CTRL_REG__SP10_MASK 0x7f
#define CGTS_CU4_SP1_CTRL_REG__SP10__SHIFT 0x0
#define CGTS_CU4_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x80
#define CGTS_CU4_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7
#define CGTS_CU4_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x300
#define CGTS_CU4_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8
#define CGTS_CU4_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x400
#define CGTS_CU4_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa
#define CGTS_CU4_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x800
#define CGTS_CU4_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb
#define CGTS_CU4_SP1_CTRL_REG__SP11_MASK 0x7f0000
#define CGTS_CU4_SP1_CTRL_REG__SP11__SHIFT 0x10
#define CGTS_CU4_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x800000
#define CGTS_CU4_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17
#define CGTS_CU4_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x3000000
#define CGTS_CU4_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18
#define CGTS_CU4_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x4000000
#define CGTS_CU4_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a
#define CGTS_CU4_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x8000000
#define CGTS_CU4_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b
#define CGTS_CU4_TD_TCP_CTRL_REG__TD_MASK 0x7f
#define CGTS_CU4_TD_TCP_CTRL_REG__TD__SHIFT 0x0
#define CGTS_CU4_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x80
#define CGTS_CU4_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7
#define CGTS_CU4_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x300
#define CGTS_CU4_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8
#define CGTS_CU4_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x400
#define CGTS_CU4_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa
#define CGTS_CU4_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x800
#define CGTS_CU4_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb
#define CGTS_CU4_TD_TCP_CTRL_REG__TCP_MASK 0x7f0000
#define CGTS_CU4_TD_TCP_CTRL_REG__TCP__SHIFT 0x10
#define CGTS_CU4_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK 0x800000
#define CGTS_CU4_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT 0x17
#define CGTS_CU4_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK 0x3000000
#define CGTS_CU4_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT 0x18
#define CGTS_CU4_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK 0x4000000
#define CGTS_CU4_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT 0x1a
#define CGTS_CU4_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK 0x8000000
#define CGTS_CU4_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT 0x1b
#define CGTS_CU5_SP0_CTRL_REG__SP00_MASK 0x7f
#define CGTS_CU5_SP0_CTRL_REG__SP00__SHIFT 0x0
#define CGTS_CU5_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x80
#define CGTS_CU5_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7
#define CGTS_CU5_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x300
#define CGTS_CU5_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8
#define CGTS_CU5_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x400
#define CGTS_CU5_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa
#define CGTS_CU5_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x800
#define CGTS_CU5_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb
#define CGTS_CU5_SP0_CTRL_REG__SP01_MASK 0x7f0000
#define CGTS_CU5_SP0_CTRL_REG__SP01__SHIFT 0x10
#define CGTS_CU5_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x800000
#define CGTS_CU5_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17
#define CGTS_CU5_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x3000000
#define CGTS_CU5_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18
#define CGTS_CU5_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x4000000
#define CGTS_CU5_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a
#define CGTS_CU5_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x8000000
#define CGTS_CU5_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b
#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_MASK 0x7f
#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0
#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x80
#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7
#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x300
#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8
#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x400
#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa
#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x800
#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb
#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_MASK 0x7f0000
#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10
#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x800000
#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17
#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x3000000
#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18
#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x4000000
#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a
#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x8000000
#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b
#define CGTS_CU5_TA_CTRL_REG__TA_MASK 0x7f
#define CGTS_CU5_TA_CTRL_REG__TA__SHIFT 0x0
#define CGTS_CU5_TA_CTRL_REG__TA_OVERRIDE_MASK 0x80
#define CGTS_CU5_TA_CTRL_REG__TA_OVERRIDE__SHIFT 0x7
#define CGTS_CU5_TA_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x300
#define CGTS_CU5_TA_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8
#define CGTS_CU5_TA_CTRL_REG__TA_LS_OVERRIDE_MASK 0x400
#define CGTS_CU5_TA_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa
#define CGTS_CU5_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x800
#define CGTS_CU5_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb
#define CGTS_CU5_SP1_CTRL_REG__SP10_MASK 0x7f
#define CGTS_CU5_SP1_CTRL_REG__SP10__SHIFT 0x0
#define CGTS_CU5_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x80
#define CGTS_CU5_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7
#define CGTS_CU5_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x300
#define CGTS_CU5_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8
#define CGTS_CU5_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x400
#define CGTS_CU5_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa
#define CGTS_CU5_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x800
#define CGTS_CU5_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb
#define CGTS_CU5_SP1_CTRL_REG__SP11_MASK 0x7f0000
#define CGTS_CU5_SP1_CTRL_REG__SP11__SHIFT 0x10
#define CGTS_CU5_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x800000
#define CGTS_CU5_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17
#define CGTS_CU5_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x3000000
#define CGTS_CU5_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18
#define CGTS_CU5_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x4000000
#define CGTS_CU5_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a
#define CGTS_CU5_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x8000000
#define CGTS_CU5_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b
#define CGTS_CU5_TD_TCP_CTRL_REG__TD_MASK 0x7f
#define CGTS_CU5_TD_TCP_CTRL_REG__TD__SHIFT 0x0
#define CGTS_CU5_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x80
#define CGTS_CU5_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7
#define CGTS_CU5_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x300
#define CGTS_CU5_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8
#define CGTS_CU5_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x400
#define CGTS_CU5_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa
#define CGTS_CU5_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x800
#define CGTS_CU5_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb
#define CGTS_CU5_TD_TCP_CTRL_REG__TCP_MASK 0x7f0000
#define CGTS_CU5_TD_TCP_CTRL_REG__TCP__SHIFT 0x10
#define CGTS_CU5_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK 0x800000
#define CGTS_CU5_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT 0x17
#define CGTS_CU5_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK 0x3000000
#define CGTS_CU5_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT 0x18
#define CGTS_CU5_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK 0x4000000
#define CGTS_CU5_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT 0x1a
#define CGTS_CU5_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK 0x8000000
#define CGTS_CU5_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT 0x1b
#define CGTS_CU6_SP0_CTRL_REG__SP00_MASK 0x7f
#define CGTS_CU6_SP0_CTRL_REG__SP00__SHIFT 0x0
#define CGTS_CU6_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x80
#define CGTS_CU6_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7
#define CGTS_CU6_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x300
#define CGTS_CU6_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8
#define CGTS_CU6_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x400
#define CGTS_CU6_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa
#define CGTS_CU6_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x800
#define CGTS_CU6_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb
#define CGTS_CU6_SP0_CTRL_REG__SP01_MASK 0x7f0000
#define CGTS_CU6_SP0_CTRL_REG__SP01__SHIFT 0x10
#define CGTS_CU6_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x800000
#define CGTS_CU6_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17
#define CGTS_CU6_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x3000000
#define CGTS_CU6_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18
#define CGTS_CU6_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x4000000
#define CGTS_CU6_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a
#define CGTS_CU6_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x8000000
#define CGTS_CU6_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b
#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_MASK 0x7f
#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0
#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x80
#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7
#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x300
#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8
#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x400
#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa
#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x800
#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb
#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_MASK 0x7f0000
#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10
#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x800000
#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17
#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x3000000
#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18
#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x4000000
#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a
#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x8000000
#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b
#define CGTS_CU6_TA_CTRL_REG__TA_MASK 0x7f
#define CGTS_CU6_TA_CTRL_REG__TA__SHIFT 0x0
#define CGTS_CU6_TA_CTRL_REG__TA_OVERRIDE_MASK 0x80
#define CGTS_CU6_TA_CTRL_REG__TA_OVERRIDE__SHIFT 0x7
#define CGTS_CU6_TA_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x300
#define CGTS_CU6_TA_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8
#define CGTS_CU6_TA_CTRL_REG__TA_LS_OVERRIDE_MASK 0x400
#define CGTS_CU6_TA_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa
#define CGTS_CU6_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x800
#define CGTS_CU6_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb
#define CGTS_CU6_SP1_CTRL_REG__SP10_MASK 0x7f
#define CGTS_CU6_SP1_CTRL_REG__SP10__SHIFT 0x0
#define CGTS_CU6_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x80
#define CGTS_CU6_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7
#define CGTS_CU6_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x300
#define CGTS_CU6_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8
#define CGTS_CU6_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x400
#define CGTS_CU6_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa
#define CGTS_CU6_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x800
#define CGTS_CU6_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb
#define CGTS_CU6_SP1_CTRL_REG__SP11_MASK 0x7f0000
#define CGTS_CU6_SP1_CTRL_REG__SP11__SHIFT 0x10
#define CGTS_CU6_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x800000
#define CGTS_CU6_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17
#define CGTS_CU6_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x3000000
#define CGTS_CU6_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18
#define CGTS_CU6_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x4000000
#define CGTS_CU6_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a
#define CGTS_CU6_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x8000000
#define CGTS_CU6_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b
#define CGTS_CU6_TD_TCP_CTRL_REG__TD_MASK 0x7f
#define CGTS_CU6_TD_TCP_CTRL_REG__TD__SHIFT 0x0
#define CGTS_CU6_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x80
#define CGTS_CU6_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7
#define CGTS_CU6_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x300
#define CGTS_CU6_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8
#define CGTS_CU6_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x400
#define CGTS_CU6_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa
#define CGTS_CU6_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x800
#define CGTS_CU6_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb
#define CGTS_CU6_TD_TCP_CTRL_REG__TCP_MASK 0x7f0000
#define CGTS_CU6_TD_TCP_CTRL_REG__TCP__SHIFT 0x10
#define CGTS_CU6_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK 0x800000
#define CGTS_CU6_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT 0x17
#define CGTS_CU6_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK 0x3000000
#define CGTS_CU6_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT 0x18
#define CGTS_CU6_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK 0x4000000
#define CGTS_CU6_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT 0x1a
#define CGTS_CU6_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK 0x8000000
#define CGTS_CU6_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT 0x1b
#define CGTS_CU7_SP0_CTRL_REG__SP00_MASK 0x7f
#define CGTS_CU7_SP0_CTRL_REG__SP00__SHIFT 0x0
#define CGTS_CU7_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x80
#define CGTS_CU7_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7
#define CGTS_CU7_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x300
#define CGTS_CU7_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8
#define CGTS_CU7_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x400
#define CGTS_CU7_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa
#define CGTS_CU7_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x800
#define CGTS_CU7_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb
#define CGTS_CU7_SP0_CTRL_REG__SP01_MASK 0x7f0000
#define CGTS_CU7_SP0_CTRL_REG__SP01__SHIFT 0x10
#define CGTS_CU7_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x800000
#define CGTS_CU7_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17
#define CGTS_CU7_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x3000000
#define CGTS_CU7_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18
#define CGTS_CU7_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x4000000
#define CGTS_CU7_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a
#define CGTS_CU7_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x8000000
#define CGTS_CU7_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b
#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_MASK 0x7f
#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0
#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x80
#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7
#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x300
#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8
#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x400
#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa
#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x800
#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb
#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_MASK 0x7f0000
#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10
#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x800000
#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17
#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x3000000
#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18
#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x4000000
#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a
#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x8000000
#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b
#define CGTS_CU7_TA_CTRL_REG__TA_MASK 0x7f
#define CGTS_CU7_TA_CTRL_REG__TA__SHIFT 0x0
#define CGTS_CU7_TA_CTRL_REG__TA_OVERRIDE_MASK 0x80
#define CGTS_CU7_TA_CTRL_REG__TA_OVERRIDE__SHIFT 0x7
#define CGTS_CU7_TA_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x300
#define CGTS_CU7_TA_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8
#define CGTS_CU7_TA_CTRL_REG__TA_LS_OVERRIDE_MASK 0x400
#define CGTS_CU7_TA_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa
#define CGTS_CU7_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x800
#define CGTS_CU7_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb
#define CGTS_CU7_SP1_CTRL_REG__SP10_MASK 0x7f
#define CGTS_CU7_SP1_CTRL_REG__SP10__SHIFT 0x0
#define CGTS_CU7_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x80
#define CGTS_CU7_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7
#define CGTS_CU7_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x300
#define CGTS_CU7_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8
#define CGTS_CU7_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x400
#define CGTS_CU7_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa
#define CGTS_CU7_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x800
#define CGTS_CU7_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb
#define CGTS_CU7_SP1_CTRL_REG__SP11_MASK 0x7f0000
#define CGTS_CU7_SP1_CTRL_REG__SP11__SHIFT 0x10
#define CGTS_CU7_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x800000
#define CGTS_CU7_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17
#define CGTS_CU7_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x3000000
#define CGTS_CU7_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18
#define CGTS_CU7_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x4000000
#define CGTS_CU7_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a
#define CGTS_CU7_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x8000000
#define CGTS_CU7_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b
#define CGTS_CU7_TD_TCP_CTRL_REG__TD_MASK 0x7f
#define CGTS_CU7_TD_TCP_CTRL_REG__TD__SHIFT 0x0
#define CGTS_CU7_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x80
#define CGTS_CU7_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7
#define CGTS_CU7_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x300
#define CGTS_CU7_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8
#define CGTS_CU7_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x400
#define CGTS_CU7_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa
#define CGTS_CU7_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x800
#define CGTS_CU7_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb
#define CGTS_CU7_TD_TCP_CTRL_REG__TCP_MASK 0x7f0000
#define CGTS_CU7_TD_TCP_CTRL_REG__TCP__SHIFT 0x10
#define CGTS_CU7_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK 0x800000
#define CGTS_CU7_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT 0x17
#define CGTS_CU7_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK 0x3000000
#define CGTS_CU7_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT 0x18
#define CGTS_CU7_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK 0x4000000
#define CGTS_CU7_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT 0x1a
#define CGTS_CU7_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK 0x8000000
#define CGTS_CU7_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT 0x1b
#define CGTS_CU8_SP0_CTRL_REG__SP00_MASK 0x7f
#define CGTS_CU8_SP0_CTRL_REG__SP00__SHIFT 0x0
#define CGTS_CU8_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x80
#define CGTS_CU8_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7
#define CGTS_CU8_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x300
#define CGTS_CU8_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8
#define CGTS_CU8_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x400
#define CGTS_CU8_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa
#define CGTS_CU8_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x800
#define CGTS_CU8_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb
#define CGTS_CU8_SP0_CTRL_REG__SP01_MASK 0x7f0000
#define CGTS_CU8_SP0_CTRL_REG__SP01__SHIFT 0x10
#define CGTS_CU8_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x800000
#define CGTS_CU8_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17
#define CGTS_CU8_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x3000000
#define CGTS_CU8_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18
#define CGTS_CU8_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x4000000
#define CGTS_CU8_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a
#define CGTS_CU8_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x8000000
#define CGTS_CU8_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b
#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_MASK 0x7f
#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0
#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x80
#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7
#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x300
#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8
#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x400
#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa
#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x800
#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb
#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_MASK 0x7f0000
#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10
#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x800000
#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17
#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x3000000
#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18
#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x4000000
#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a
#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x8000000
#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b
#define CGTS_CU8_TA_SQC_CTRL_REG__TA_MASK 0x7f
#define CGTS_CU8_TA_SQC_CTRL_REG__TA__SHIFT 0x0
#define CGTS_CU8_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x80
#define CGTS_CU8_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7
#define CGTS_CU8_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x300
#define CGTS_CU8_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8
#define CGTS_CU8_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x400
#define CGTS_CU8_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa
#define CGTS_CU8_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x800
#define CGTS_CU8_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb
#define CGTS_CU8_TA_SQC_CTRL_REG__SQC_MASK 0x7f0000
#define CGTS_CU8_TA_SQC_CTRL_REG__SQC__SHIFT 0x10
#define CGTS_CU8_TA_SQC_CTRL_REG__SQC_OVERRIDE_MASK 0x800000
#define CGTS_CU8_TA_SQC_CTRL_REG__SQC_OVERRIDE__SHIFT 0x17
#define CGTS_CU8_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE_MASK 0x3000000
#define CGTS_CU8_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE__SHIFT 0x18
#define CGTS_CU8_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE_MASK 0x4000000
#define CGTS_CU8_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE__SHIFT 0x1a
#define CGTS_CU8_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE_MASK 0x8000000
#define CGTS_CU8_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE__SHIFT 0x1b
#define CGTS_CU8_SP1_CTRL_REG__SP10_MASK 0x7f
#define CGTS_CU8_SP1_CTRL_REG__SP10__SHIFT 0x0
#define CGTS_CU8_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x80
#define CGTS_CU8_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7
#define CGTS_CU8_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x300
#define CGTS_CU8_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8
#define CGTS_CU8_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x400
#define CGTS_CU8_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa
#define CGTS_CU8_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x800
#define CGTS_CU8_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb
#define CGTS_CU8_SP1_CTRL_REG__SP11_MASK 0x7f0000
#define CGTS_CU8_SP1_CTRL_REG__SP11__SHIFT 0x10
#define CGTS_CU8_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x800000
#define CGTS_CU8_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17
#define CGTS_CU8_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x3000000
#define CGTS_CU8_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18
#define CGTS_CU8_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x4000000
#define CGTS_CU8_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a
#define CGTS_CU8_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x8000000
#define CGTS_CU8_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b
#define CGTS_CU8_TD_TCP_CTRL_REG__TD_MASK 0x7f
#define CGTS_CU8_TD_TCP_CTRL_REG__TD__SHIFT 0x0
#define CGTS_CU8_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x80
#define CGTS_CU8_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7
#define CGTS_CU8_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x300
#define CGTS_CU8_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8
#define CGTS_CU8_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x400
#define CGTS_CU8_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa
#define CGTS_CU8_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x800
#define CGTS_CU8_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb
#define CGTS_CU8_TD_TCP_CTRL_REG__TCP_MASK 0x7f0000
#define CGTS_CU8_TD_TCP_CTRL_REG__TCP__SHIFT 0x10
#define CGTS_CU8_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK 0x800000
#define CGTS_CU8_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT 0x17
#define CGTS_CU8_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK 0x3000000
#define CGTS_CU8_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT 0x18
#define CGTS_CU8_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK 0x4000000
#define CGTS_CU8_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT 0x1a
#define CGTS_CU8_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK 0x8000000
#define CGTS_CU8_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT 0x1b
#define CGTS_CU9_SP0_CTRL_REG__SP00_MASK 0x7f
#define CGTS_CU9_SP0_CTRL_REG__SP00__SHIFT 0x0
#define CGTS_CU9_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x80
#define CGTS_CU9_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7
#define CGTS_CU9_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x300
#define CGTS_CU9_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8
#define CGTS_CU9_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x400
#define CGTS_CU9_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa
#define CGTS_CU9_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x800
#define CGTS_CU9_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb
#define CGTS_CU9_SP0_CTRL_REG__SP01_MASK 0x7f0000
#define CGTS_CU9_SP0_CTRL_REG__SP01__SHIFT 0x10
#define CGTS_CU9_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x800000
#define CGTS_CU9_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17
#define CGTS_CU9_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x3000000
#define CGTS_CU9_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18
#define CGTS_CU9_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x4000000
#define CGTS_CU9_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a
#define CGTS_CU9_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x8000000
#define CGTS_CU9_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b
#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_MASK 0x7f
#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0
#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x80
#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7
#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x300
#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8
#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x400
#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa
#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x800
#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb
#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_MASK 0x7f0000
#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10
#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x800000
#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17
#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x3000000
#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18
#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x4000000
#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a
#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x8000000
#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b
#define CGTS_CU9_TA_CTRL_REG__TA_MASK 0x7f
#define CGTS_CU9_TA_CTRL_REG__TA__SHIFT 0x0
#define CGTS_CU9_TA_CTRL_REG__TA_OVERRIDE_MASK 0x80
#define CGTS_CU9_TA_CTRL_REG__TA_OVERRIDE__SHIFT 0x7
#define CGTS_CU9_TA_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x300
#define CGTS_CU9_TA_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8
#define CGTS_CU9_TA_CTRL_REG__TA_LS_OVERRIDE_MASK 0x400
#define CGTS_CU9_TA_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa
#define CGTS_CU9_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x800
#define CGTS_CU9_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb
#define CGTS_CU9_SP1_CTRL_REG__SP10_MASK 0x7f
#define CGTS_CU9_SP1_CTRL_REG__SP10__SHIFT 0x0
#define CGTS_CU9_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x80
#define CGTS_CU9_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7
#define CGTS_CU9_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x300
#define CGTS_CU9_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8
#define CGTS_CU9_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x400
#define CGTS_CU9_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa
#define CGTS_CU9_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x800
#define CGTS_CU9_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb
#define CGTS_CU9_SP1_CTRL_REG__SP11_MASK 0x7f0000
#define CGTS_CU9_SP1_CTRL_REG__SP11__SHIFT 0x10
#define CGTS_CU9_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x800000
#define CGTS_CU9_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17
#define CGTS_CU9_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x3000000
#define CGTS_CU9_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18
#define CGTS_CU9_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x4000000
#define CGTS_CU9_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a
#define CGTS_CU9_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x8000000
#define CGTS_CU9_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b
#define CGTS_CU9_TD_TCP_CTRL_REG__TD_MASK 0x7f
#define CGTS_CU9_TD_TCP_CTRL_REG__TD__SHIFT 0x0
#define CGTS_CU9_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x80
#define CGTS_CU9_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7
#define CGTS_CU9_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x300
#define CGTS_CU9_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8
#define CGTS_CU9_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x400
#define CGTS_CU9_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa
#define CGTS_CU9_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x800
#define CGTS_CU9_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb
#define CGTS_CU9_TD_TCP_CTRL_REG__TCP_MASK 0x7f0000
#define CGTS_CU9_TD_TCP_CTRL_REG__TCP__SHIFT 0x10
#define CGTS_CU9_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK 0x800000
#define CGTS_CU9_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT 0x17
#define CGTS_CU9_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK 0x3000000
#define CGTS_CU9_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT 0x18
#define CGTS_CU9_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK 0x4000000
#define CGTS_CU9_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT 0x1a
#define CGTS_CU9_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK 0x8000000
#define CGTS_CU9_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT 0x1b
#define CGTS_CU10_SP0_CTRL_REG__SP00_MASK 0x7f
#define CGTS_CU10_SP0_CTRL_REG__SP00__SHIFT 0x0
#define CGTS_CU10_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x80
#define CGTS_CU10_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7
#define CGTS_CU10_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x300
#define CGTS_CU10_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8
#define CGTS_CU10_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x400
#define CGTS_CU10_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa
#define CGTS_CU10_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x800
#define CGTS_CU10_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb
#define CGTS_CU10_SP0_CTRL_REG__SP01_MASK 0x7f0000
#define CGTS_CU10_SP0_CTRL_REG__SP01__SHIFT 0x10
#define CGTS_CU10_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x800000
#define CGTS_CU10_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17
#define CGTS_CU10_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x3000000
#define CGTS_CU10_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18
#define CGTS_CU10_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x4000000
#define CGTS_CU10_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a
#define CGTS_CU10_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x8000000
#define CGTS_CU10_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b
#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_MASK 0x7f
#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0
#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x80
#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7
#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x300
#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8
#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x400
#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa
#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x800
#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb
#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_MASK 0x7f0000
#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10
#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x800000
#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17
#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x3000000
#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18
#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x4000000
#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a
#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x8000000
#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b
#define CGTS_CU10_TA_CTRL_REG__TA_MASK 0x7f
#define CGTS_CU10_TA_CTRL_REG__TA__SHIFT 0x0
#define CGTS_CU10_TA_CTRL_REG__TA_OVERRIDE_MASK 0x80
#define CGTS_CU10_TA_CTRL_REG__TA_OVERRIDE__SHIFT 0x7
#define CGTS_CU10_TA_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x300
#define CGTS_CU10_TA_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8
#define CGTS_CU10_TA_CTRL_REG__TA_LS_OVERRIDE_MASK 0x400
#define CGTS_CU10_TA_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa
#define CGTS_CU10_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x800
#define CGTS_CU10_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb
#define CGTS_CU10_SP1_CTRL_REG__SP10_MASK 0x7f
#define CGTS_CU10_SP1_CTRL_REG__SP10__SHIFT 0x0
#define CGTS_CU10_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x80
#define CGTS_CU10_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7
#define CGTS_CU10_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x300
#define CGTS_CU10_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8
#define CGTS_CU10_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x400
#define CGTS_CU10_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa
#define CGTS_CU10_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x800
#define CGTS_CU10_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb
#define CGTS_CU10_SP1_CTRL_REG__SP11_MASK 0x7f0000
#define CGTS_CU10_SP1_CTRL_REG__SP11__SHIFT 0x10
#define CGTS_CU10_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x800000
#define CGTS_CU10_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17
#define CGTS_CU10_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x3000000
#define CGTS_CU10_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18
#define CGTS_CU10_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x4000000
#define CGTS_CU10_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a
#define CGTS_CU10_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x8000000
#define CGTS_CU10_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b
#define CGTS_CU10_TD_TCP_CTRL_REG__TD_MASK 0x7f
#define CGTS_CU10_TD_TCP_CTRL_REG__TD__SHIFT 0x0
#define CGTS_CU10_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x80
#define CGTS_CU10_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7
#define CGTS_CU10_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x300
#define CGTS_CU10_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8
#define CGTS_CU10_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x400
#define CGTS_CU10_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa
#define CGTS_CU10_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x800
#define CGTS_CU10_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb
#define CGTS_CU10_TD_TCP_CTRL_REG__TCP_MASK 0x7f0000
#define CGTS_CU10_TD_TCP_CTRL_REG__TCP__SHIFT 0x10
#define CGTS_CU10_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK 0x800000
#define CGTS_CU10_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT 0x17
#define CGTS_CU10_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK 0x3000000
#define CGTS_CU10_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT 0x18
#define CGTS_CU10_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK 0x4000000
#define CGTS_CU10_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT 0x1a
#define CGTS_CU10_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK 0x8000000
#define CGTS_CU10_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT 0x1b
#define CGTS_CU11_SP0_CTRL_REG__SP00_MASK 0x7f
#define CGTS_CU11_SP0_CTRL_REG__SP00__SHIFT 0x0
#define CGTS_CU11_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x80
#define CGTS_CU11_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7
#define CGTS_CU11_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x300
#define CGTS_CU11_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8
#define CGTS_CU11_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x400
#define CGTS_CU11_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa
#define CGTS_CU11_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x800
#define CGTS_CU11_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb
#define CGTS_CU11_SP0_CTRL_REG__SP01_MASK 0x7f0000
#define CGTS_CU11_SP0_CTRL_REG__SP01__SHIFT 0x10
#define CGTS_CU11_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x800000
#define CGTS_CU11_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17
#define CGTS_CU11_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x3000000
#define CGTS_CU11_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18
#define CGTS_CU11_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x4000000
#define CGTS_CU11_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a
#define CGTS_CU11_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x8000000
#define CGTS_CU11_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b
#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_MASK 0x7f
#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0
#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x80
#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7
#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x300
#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8
#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x400
#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa
#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x800
#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb
#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_MASK 0x7f0000
#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10
#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x800000
#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17
#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x3000000
#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18
#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x4000000
#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a
#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x8000000
#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b
#define CGTS_CU11_TA_CTRL_REG__TA_MASK 0x7f
#define CGTS_CU11_TA_CTRL_REG__TA__SHIFT 0x0
#define CGTS_CU11_TA_CTRL_REG__TA_OVERRIDE_MASK 0x80
#define CGTS_CU11_TA_CTRL_REG__TA_OVERRIDE__SHIFT 0x7
#define CGTS_CU11_TA_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x300
#define CGTS_CU11_TA_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8
#define CGTS_CU11_TA_CTRL_REG__TA_LS_OVERRIDE_MASK 0x400
#define CGTS_CU11_TA_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa
#define CGTS_CU11_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x800
#define CGTS_CU11_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb
#define CGTS_CU11_SP1_CTRL_REG__SP10_MASK 0x7f
#define CGTS_CU11_SP1_CTRL_REG__SP10__SHIFT 0x0
#define CGTS_CU11_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x80
#define CGTS_CU11_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7
#define CGTS_CU11_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x300
#define CGTS_CU11_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8
#define CGTS_CU11_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x400
#define CGTS_CU11_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa
#define CGTS_CU11_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x800
#define CGTS_CU11_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb
#define CGTS_CU11_SP1_CTRL_REG__SP11_MASK 0x7f0000
#define CGTS_CU11_SP1_CTRL_REG__SP11__SHIFT 0x10
#define CGTS_CU11_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x800000
#define CGTS_CU11_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17
#define CGTS_CU11_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x3000000
#define CGTS_CU11_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18
#define CGTS_CU11_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x4000000
#define CGTS_CU11_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a
#define CGTS_CU11_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x8000000
#define CGTS_CU11_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b
#define CGTS_CU11_TD_TCP_CTRL_REG__TD_MASK 0x7f
#define CGTS_CU11_TD_TCP_CTRL_REG__TD__SHIFT 0x0
#define CGTS_CU11_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x80
#define CGTS_CU11_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7
#define CGTS_CU11_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x300
#define CGTS_CU11_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8
#define CGTS_CU11_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x400
#define CGTS_CU11_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa
#define CGTS_CU11_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x800
#define CGTS_CU11_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb
#define CGTS_CU11_TD_TCP_CTRL_REG__TCP_MASK 0x7f0000
#define CGTS_CU11_TD_TCP_CTRL_REG__TCP__SHIFT 0x10
#define CGTS_CU11_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK 0x800000
#define CGTS_CU11_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT 0x17
#define CGTS_CU11_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK 0x3000000
#define CGTS_CU11_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT 0x18
#define CGTS_CU11_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK 0x4000000
#define CGTS_CU11_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT 0x1a
#define CGTS_CU11_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK 0x8000000
#define CGTS_CU11_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT 0x1b
#define CGTS_CU12_SP0_CTRL_REG__SP00_MASK 0x7f
#define CGTS_CU12_SP0_CTRL_REG__SP00__SHIFT 0x0
#define CGTS_CU12_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x80
#define CGTS_CU12_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7
#define CGTS_CU12_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x300
#define CGTS_CU12_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8
#define CGTS_CU12_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x400
#define CGTS_CU12_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa
#define CGTS_CU12_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x800
#define CGTS_CU12_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb
#define CGTS_CU12_SP0_CTRL_REG__SP01_MASK 0x7f0000
#define CGTS_CU12_SP0_CTRL_REG__SP01__SHIFT 0x10
#define CGTS_CU12_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x800000
#define CGTS_CU12_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17
#define CGTS_CU12_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x3000000
#define CGTS_CU12_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18
#define CGTS_CU12_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x4000000
#define CGTS_CU12_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a
#define CGTS_CU12_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x8000000
#define CGTS_CU12_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b
#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_MASK 0x7f
#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0
#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x80
#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7
#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x300
#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8
#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x400
#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa
#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x800
#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb
#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_MASK 0x7f0000
#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10
#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x800000
#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17
#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x3000000
#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18
#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x4000000
#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a
#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x8000000
#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b
#define CGTS_CU12_TA_SQC_CTRL_REG__TA_MASK 0x7f
#define CGTS_CU12_TA_SQC_CTRL_REG__TA__SHIFT 0x0
#define CGTS_CU12_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x80
#define CGTS_CU12_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7
#define CGTS_CU12_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x300
#define CGTS_CU12_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8
#define CGTS_CU12_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x400
#define CGTS_CU12_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa
#define CGTS_CU12_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x800
#define CGTS_CU12_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb
#define CGTS_CU12_TA_SQC_CTRL_REG__SQC_MASK 0x7f0000
#define CGTS_CU12_TA_SQC_CTRL_REG__SQC__SHIFT 0x10
#define CGTS_CU12_TA_SQC_CTRL_REG__SQC_OVERRIDE_MASK 0x800000
#define CGTS_CU12_TA_SQC_CTRL_REG__SQC_OVERRIDE__SHIFT 0x17
#define CGTS_CU12_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE_MASK 0x3000000
#define CGTS_CU12_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE__SHIFT 0x18
#define CGTS_CU12_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE_MASK 0x4000000
#define CGTS_CU12_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE__SHIFT 0x1a
#define CGTS_CU12_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE_MASK 0x8000000
#define CGTS_CU12_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE__SHIFT 0x1b
#define CGTS_CU12_SP1_CTRL_REG__SP10_MASK 0x7f
#define CGTS_CU12_SP1_CTRL_REG__SP10__SHIFT 0x0
#define CGTS_CU12_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x80
#define CGTS_CU12_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7
#define CGTS_CU12_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x300
#define CGTS_CU12_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8
#define CGTS_CU12_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x400
#define CGTS_CU12_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa
#define CGTS_CU12_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x800
#define CGTS_CU12_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb
#define CGTS_CU12_SP1_CTRL_REG__SP11_MASK 0x7f0000
#define CGTS_CU12_SP1_CTRL_REG__SP11__SHIFT 0x10
#define CGTS_CU12_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x800000
#define CGTS_CU12_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17
#define CGTS_CU12_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x3000000
#define CGTS_CU12_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18
#define CGTS_CU12_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x4000000
#define CGTS_CU12_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a
#define CGTS_CU12_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x8000000
#define CGTS_CU12_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b
#define CGTS_CU12_TD_TCP_CTRL_REG__TD_MASK 0x7f
#define CGTS_CU12_TD_TCP_CTRL_REG__TD__SHIFT 0x0
#define CGTS_CU12_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x80
#define CGTS_CU12_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7
#define CGTS_CU12_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x300
#define CGTS_CU12_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8
#define CGTS_CU12_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x400
#define CGTS_CU12_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa
#define CGTS_CU12_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x800
#define CGTS_CU12_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb
#define CGTS_CU12_TD_TCP_CTRL_REG__TCP_MASK 0x7f0000
#define CGTS_CU12_TD_TCP_CTRL_REG__TCP__SHIFT 0x10
#define CGTS_CU12_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK 0x800000
#define CGTS_CU12_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT 0x17
#define CGTS_CU12_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK 0x3000000
#define CGTS_CU12_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT 0x18
#define CGTS_CU12_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK 0x4000000
#define CGTS_CU12_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT 0x1a
#define CGTS_CU12_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK 0x8000000
#define CGTS_CU12_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT 0x1b
#define CGTS_CU13_SP0_CTRL_REG__SP00_MASK 0x7f
#define CGTS_CU13_SP0_CTRL_REG__SP00__SHIFT 0x0
#define CGTS_CU13_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x80
#define CGTS_CU13_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7
#define CGTS_CU13_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x300
#define CGTS_CU13_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8
#define CGTS_CU13_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x400
#define CGTS_CU13_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa
#define CGTS_CU13_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x800
#define CGTS_CU13_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb
#define CGTS_CU13_SP0_CTRL_REG__SP01_MASK 0x7f0000
#define CGTS_CU13_SP0_CTRL_REG__SP01__SHIFT 0x10
#define CGTS_CU13_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x800000
#define CGTS_CU13_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17
#define CGTS_CU13_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x3000000
#define CGTS_CU13_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18
#define CGTS_CU13_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x4000000
#define CGTS_CU13_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a
#define CGTS_CU13_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x8000000
#define CGTS_CU13_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b
#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_MASK 0x7f
#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0
#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x80
#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7
#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x300
#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8
#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x400
#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa
#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x800
#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb
#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_MASK 0x7f0000
#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10
#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x800000
#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17
#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x3000000
#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18
#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x4000000
#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a
#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x8000000
#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b
#define CGTS_CU13_TA_CTRL_REG__TA_MASK 0x7f
#define CGTS_CU13_TA_CTRL_REG__TA__SHIFT 0x0
#define CGTS_CU13_TA_CTRL_REG__TA_OVERRIDE_MASK 0x80
#define CGTS_CU13_TA_CTRL_REG__TA_OVERRIDE__SHIFT 0x7
#define CGTS_CU13_TA_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x300
#define CGTS_CU13_TA_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8
#define CGTS_CU13_TA_CTRL_REG__TA_LS_OVERRIDE_MASK 0x400
#define CGTS_CU13_TA_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa
#define CGTS_CU13_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x800
#define CGTS_CU13_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb
#define CGTS_CU13_SP1_CTRL_REG__SP10_MASK 0x7f
#define CGTS_CU13_SP1_CTRL_REG__SP10__SHIFT 0x0
#define CGTS_CU13_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x80
#define CGTS_CU13_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7
#define CGTS_CU13_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x300
#define CGTS_CU13_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8
#define CGTS_CU13_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x400
#define CGTS_CU13_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa
#define CGTS_CU13_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x800
#define CGTS_CU13_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb
#define CGTS_CU13_SP1_CTRL_REG__SP11_MASK 0x7f0000
#define CGTS_CU13_SP1_CTRL_REG__SP11__SHIFT 0x10
#define CGTS_CU13_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x800000
#define CGTS_CU13_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17
#define CGTS_CU13_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x3000000
#define CGTS_CU13_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18
#define CGTS_CU13_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x4000000
#define CGTS_CU13_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a
#define CGTS_CU13_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x8000000
#define CGTS_CU13_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b
#define CGTS_CU13_TD_TCP_CTRL_REG__TD_MASK 0x7f
#define CGTS_CU13_TD_TCP_CTRL_REG__TD__SHIFT 0x0
#define CGTS_CU13_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x80
#define CGTS_CU13_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7
#define CGTS_CU13_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x300
#define CGTS_CU13_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8
#define CGTS_CU13_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x400
#define CGTS_CU13_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa
#define CGTS_CU13_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x800
#define CGTS_CU13_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb
#define CGTS_CU13_TD_TCP_CTRL_REG__TCP_MASK 0x7f0000
#define CGTS_CU13_TD_TCP_CTRL_REG__TCP__SHIFT 0x10
#define CGTS_CU13_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK 0x800000
#define CGTS_CU13_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT 0x17
#define CGTS_CU13_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK 0x3000000
#define CGTS_CU13_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT 0x18
#define CGTS_CU13_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK 0x4000000
#define CGTS_CU13_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT 0x1a
#define CGTS_CU13_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK 0x8000000
#define CGTS_CU13_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT 0x1b
#define CGTS_CU14_SP0_CTRL_REG__SP00_MASK 0x7f
#define CGTS_CU14_SP0_CTRL_REG__SP00__SHIFT 0x0
#define CGTS_CU14_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x80
#define CGTS_CU14_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7
#define CGTS_CU14_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x300
#define CGTS_CU14_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8
#define CGTS_CU14_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x400
#define CGTS_CU14_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa
#define CGTS_CU14_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x800
#define CGTS_CU14_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb
#define CGTS_CU14_SP0_CTRL_REG__SP01_MASK 0x7f0000
#define CGTS_CU14_SP0_CTRL_REG__SP01__SHIFT 0x10
#define CGTS_CU14_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x800000
#define CGTS_CU14_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17
#define CGTS_CU14_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x3000000
#define CGTS_CU14_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18
#define CGTS_CU14_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x4000000
#define CGTS_CU14_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a
#define CGTS_CU14_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x8000000
#define CGTS_CU14_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b
#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_MASK 0x7f
#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0
#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x80
#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7
#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x300
#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8
#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x400
#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa
#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x800
#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb
#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_MASK 0x7f0000
#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10
#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x800000
#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17
#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x3000000
#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18
#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x4000000
#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a
#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x8000000
#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b
#define CGTS_CU14_TA_CTRL_REG__TA_MASK 0x7f
#define CGTS_CU14_TA_CTRL_REG__TA__SHIFT 0x0
#define CGTS_CU14_TA_CTRL_REG__TA_OVERRIDE_MASK 0x80
#define CGTS_CU14_TA_CTRL_REG__TA_OVERRIDE__SHIFT 0x7
#define CGTS_CU14_TA_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x300
#define CGTS_CU14_TA_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8
#define CGTS_CU14_TA_CTRL_REG__TA_LS_OVERRIDE_MASK 0x400
#define CGTS_CU14_TA_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa
#define CGTS_CU14_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x800
#define CGTS_CU14_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb
#define CGTS_CU14_SP1_CTRL_REG__SP10_MASK 0x7f
#define CGTS_CU14_SP1_CTRL_REG__SP10__SHIFT 0x0
#define CGTS_CU14_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x80
#define CGTS_CU14_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7
#define CGTS_CU14_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x300
#define CGTS_CU14_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8
#define CGTS_CU14_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x400
#define CGTS_CU14_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa
#define CGTS_CU14_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x800
#define CGTS_CU14_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb
#define CGTS_CU14_SP1_CTRL_REG__SP11_MASK 0x7f0000
#define CGTS_CU14_SP1_CTRL_REG__SP11__SHIFT 0x10
#define CGTS_CU14_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x800000
#define CGTS_CU14_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17
#define CGTS_CU14_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x3000000
#define CGTS_CU14_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18
#define CGTS_CU14_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x4000000
#define CGTS_CU14_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a
#define CGTS_CU14_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x8000000
#define CGTS_CU14_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b
#define CGTS_CU14_TD_TCP_CTRL_REG__TD_MASK 0x7f
#define CGTS_CU14_TD_TCP_CTRL_REG__TD__SHIFT 0x0
#define CGTS_CU14_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x80
#define CGTS_CU14_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7
#define CGTS_CU14_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x300
#define CGTS_CU14_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8
#define CGTS_CU14_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x400
#define CGTS_CU14_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa
#define CGTS_CU14_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x800
#define CGTS_CU14_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb
#define CGTS_CU14_TD_TCP_CTRL_REG__TCP_MASK 0x7f0000
#define CGTS_CU14_TD_TCP_CTRL_REG__TCP__SHIFT 0x10
#define CGTS_CU14_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK 0x800000
#define CGTS_CU14_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT 0x17
#define CGTS_CU14_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK 0x3000000
#define CGTS_CU14_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT 0x18
#define CGTS_CU14_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK 0x4000000
#define CGTS_CU14_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT 0x1a
#define CGTS_CU14_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK 0x8000000
#define CGTS_CU14_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT 0x1b
#define CGTS_CU15_SP0_CTRL_REG__SP00_MASK 0x7f
#define CGTS_CU15_SP0_CTRL_REG__SP00__SHIFT 0x0
#define CGTS_CU15_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x80
#define CGTS_CU15_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7
#define CGTS_CU15_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x300
#define CGTS_CU15_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8
#define CGTS_CU15_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x400
#define CGTS_CU15_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa
#define CGTS_CU15_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x800
#define CGTS_CU15_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb
#define CGTS_CU15_SP0_CTRL_REG__SP01_MASK 0x7f0000
#define CGTS_CU15_SP0_CTRL_REG__SP01__SHIFT 0x10
#define CGTS_CU15_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x800000
#define CGTS_CU15_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17
#define CGTS_CU15_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x3000000
#define CGTS_CU15_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18
#define CGTS_CU15_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x4000000
#define CGTS_CU15_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a
#define CGTS_CU15_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x8000000
#define CGTS_CU15_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b
#define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_MASK 0x7f
#define CGTS_CU15_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0
#define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x80
#define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7
#define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x300
#define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8
#define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x400
#define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa
#define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x800
#define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb
#define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_MASK 0x7f0000
#define CGTS_CU15_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10
#define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x800000
#define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17
#define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x3000000
#define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18
#define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x4000000
#define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a
#define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x8000000
#define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b
#define CGTS_CU15_TA_CTRL_REG__TA_MASK 0x7f
#define CGTS_CU15_TA_CTRL_REG__TA__SHIFT 0x0
#define CGTS_CU15_TA_CTRL_REG__TA_OVERRIDE_MASK 0x80
#define CGTS_CU15_TA_CTRL_REG__TA_OVERRIDE__SHIFT 0x7
#define CGTS_CU15_TA_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x300
#define CGTS_CU15_TA_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8
#define CGTS_CU15_TA_CTRL_REG__TA_LS_OVERRIDE_MASK 0x400
#define CGTS_CU15_TA_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa
#define CGTS_CU15_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x800
#define CGTS_CU15_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb
#define CGTS_CU15_SP1_CTRL_REG__SP10_MASK 0x7f
#define CGTS_CU15_SP1_CTRL_REG__SP10__SHIFT 0x0
#define CGTS_CU15_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x80
#define CGTS_CU15_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7
#define CGTS_CU15_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x300
#define CGTS_CU15_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8
#define CGTS_CU15_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x400
#define CGTS_CU15_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa
#define CGTS_CU15_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x800
#define CGTS_CU15_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb
#define CGTS_CU15_SP1_CTRL_REG__SP11_MASK 0x7f0000
#define CGTS_CU15_SP1_CTRL_REG__SP11__SHIFT 0x10
#define CGTS_CU15_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x800000
#define CGTS_CU15_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17
#define CGTS_CU15_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x3000000
#define CGTS_CU15_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18
#define CGTS_CU15_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x4000000
#define CGTS_CU15_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a
#define CGTS_CU15_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x8000000
#define CGTS_CU15_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b
#define CGTS_CU15_TD_TCP_CTRL_REG__TD_MASK 0x7f
#define CGTS_CU15_TD_TCP_CTRL_REG__TD__SHIFT 0x0
#define CGTS_CU15_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x80
#define CGTS_CU15_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7
#define CGTS_CU15_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x300
#define CGTS_CU15_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8
#define CGTS_CU15_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x400
#define CGTS_CU15_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa
#define CGTS_CU15_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x800
#define CGTS_CU15_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb
#define CGTS_CU15_TD_TCP_CTRL_REG__TCP_MASK 0x7f0000
#define CGTS_CU15_TD_TCP_CTRL_REG__TCP__SHIFT 0x10
#define CGTS_CU15_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK 0x800000
#define CGTS_CU15_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT 0x17
#define CGTS_CU15_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK 0x3000000
#define CGTS_CU15_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT 0x18
#define CGTS_CU15_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK 0x4000000
#define CGTS_CU15_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT 0x1a
#define CGTS_CU15_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK 0x8000000
#define CGTS_CU15_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT 0x1b
#define CGTT_SPI_CLK_CTRL__ON_DELAY_MASK 0xf
#define CGTT_SPI_CLK_CTRL__ON_DELAY__SHIFT 0x0
#define CGTT_SPI_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0
#define CGTT_SPI_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
#define CGTT_SPI_CLK_CTRL__GRP5_CG_OFF_HYST_MASK 0xfc0000
#define CGTT_SPI_CLK_CTRL__GRP5_CG_OFF_HYST__SHIFT 0x12
#define CGTT_SPI_CLK_CTRL__GRP5_CG_OVERRIDE_MASK 0x1000000
#define CGTT_SPI_CLK_CTRL__GRP5_CG_OVERRIDE__SHIFT 0x18
#define CGTT_SPI_CLK_CTRL__ALL_CLK_ON_OVERRIDE_MASK 0x4000000
#define CGTT_SPI_CLK_CTRL__ALL_CLK_ON_OVERRIDE__SHIFT 0x1a
#define CGTT_SPI_CLK_CTRL__GRP3_OVERRIDE_MASK 0x8000000
#define CGTT_SPI_CLK_CTRL__GRP3_OVERRIDE__SHIFT 0x1b
#define CGTT_SPI_CLK_CTRL__GRP2_OVERRIDE_MASK 0x10000000
#define CGTT_SPI_CLK_CTRL__GRP2_OVERRIDE__SHIFT 0x1c
#define CGTT_SPI_CLK_CTRL__GRP1_OVERRIDE_MASK 0x20000000
#define CGTT_SPI_CLK_CTRL__GRP1_OVERRIDE__SHIFT 0x1d
#define CGTT_SPI_CLK_CTRL__GRP0_OVERRIDE_MASK 0x40000000
#define CGTT_SPI_CLK_CTRL__GRP0_OVERRIDE__SHIFT 0x1e
#define CGTT_SPI_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000
#define CGTT_SPI_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f
#define CGTT_PC_CLK_CTRL__ON_DELAY_MASK 0xf
#define CGTT_PC_CLK_CTRL__ON_DELAY__SHIFT 0x0
#define CGTT_PC_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0
#define CGTT_PC_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
#define CGTT_PC_CLK_CTRL__GRP5_CG_OFF_HYST_MASK 0xfc0000
#define CGTT_PC_CLK_CTRL__GRP5_CG_OFF_HYST__SHIFT 0x12
#define CGTT_PC_CLK_CTRL__GRP5_CG_OVERRIDE_MASK 0x1000000
#define CGTT_PC_CLK_CTRL__GRP5_CG_OVERRIDE__SHIFT 0x18
#define CGTT_PC_CLK_CTRL__BACK_CLK_ON_OVERRIDE_MASK 0x2000000
#define CGTT_PC_CLK_CTRL__BACK_CLK_ON_OVERRIDE__SHIFT 0x19
#define CGTT_PC_CLK_CTRL__FRONT_CLK_ON_OVERRIDE_MASK 0x4000000
#define CGTT_PC_CLK_CTRL__FRONT_CLK_ON_OVERRIDE__SHIFT 0x1a
#define CGTT_PC_CLK_CTRL__CORE3_OVERRIDE_MASK 0x8000000
#define CGTT_PC_CLK_CTRL__CORE3_OVERRIDE__SHIFT 0x1b
#define CGTT_PC_CLK_CTRL__CORE2_OVERRIDE_MASK 0x10000000
#define CGTT_PC_CLK_CTRL__CORE2_OVERRIDE__SHIFT 0x1c
#define CGTT_PC_CLK_CTRL__CORE1_OVERRIDE_MASK 0x20000000
#define CGTT_PC_CLK_CTRL__CORE1_OVERRIDE__SHIFT 0x1d
#define CGTT_PC_CLK_CTRL__CORE0_OVERRIDE_MASK 0x40000000
#define CGTT_PC_CLK_CTRL__CORE0_OVERRIDE__SHIFT 0x1e
#define CGTT_PC_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000
#define CGTT_PC_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f
#define CGTT_BCI_CLK_CTRL__ON_DELAY_MASK 0xf
#define CGTT_BCI_CLK_CTRL__ON_DELAY__SHIFT 0x0
#define CGTT_BCI_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0
#define CGTT_BCI_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
#define CGTT_BCI_CLK_CTRL__RESERVED_MASK 0xfff000
#define CGTT_BCI_CLK_CTRL__RESERVED__SHIFT 0xc
#define CGTT_BCI_CLK_CTRL__CORE6_OVERRIDE_MASK 0x1000000
#define CGTT_BCI_CLK_CTRL__CORE6_OVERRIDE__SHIFT 0x18
#define CGTT_BCI_CLK_CTRL__CORE5_OVERRIDE_MASK 0x2000000
#define CGTT_BCI_CLK_CTRL__CORE5_OVERRIDE__SHIFT 0x19
#define CGTT_BCI_CLK_CTRL__CORE4_OVERRIDE_MASK 0x4000000
#define CGTT_BCI_CLK_CTRL__CORE4_OVERRIDE__SHIFT 0x1a
#define CGTT_BCI_CLK_CTRL__CORE3_OVERRIDE_MASK 0x8000000
#define CGTT_BCI_CLK_CTRL__CORE3_OVERRIDE__SHIFT 0x1b
#define CGTT_BCI_CLK_CTRL__CORE2_OVERRIDE_MASK 0x10000000
#define CGTT_BCI_CLK_CTRL__CORE2_OVERRIDE__SHIFT 0x1c
#define CGTT_BCI_CLK_CTRL__CORE1_OVERRIDE_MASK 0x20000000
#define CGTT_BCI_CLK_CTRL__CORE1_OVERRIDE__SHIFT 0x1d
#define CGTT_BCI_CLK_CTRL__CORE0_OVERRIDE_MASK 0x40000000
#define CGTT_BCI_CLK_CTRL__CORE0_OVERRIDE__SHIFT 0x1e
#define CGTT_BCI_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000
#define CGTT_BCI_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f
#define SPI_WF_LIFETIME_CNTL__SAMPLE_PERIOD_MASK 0xf
#define SPI_WF_LIFETIME_CNTL__SAMPLE_PERIOD__SHIFT 0x0
#define SPI_WF_LIFETIME_CNTL__EN_MASK 0x10
#define SPI_WF_LIFETIME_CNTL__EN__SHIFT 0x4
#define SPI_WF_LIFETIME_LIMIT_0__MAX_CNT_MASK 0x7fffffff
#define SPI_WF_LIFETIME_LIMIT_0__MAX_CNT__SHIFT 0x0
#define SPI_WF_LIFETIME_LIMIT_0__EN_WARN_MASK 0x80000000
#define SPI_WF_LIFETIME_LIMIT_0__EN_WARN__SHIFT 0x1f
#define SPI_WF_LIFETIME_LIMIT_1__MAX_CNT_MASK 0x7fffffff
#define SPI_WF_LIFETIME_LIMIT_1__MAX_CNT__SHIFT 0x0
#define SPI_WF_LIFETIME_LIMIT_1__EN_WARN_MASK 0x80000000
#define SPI_WF_LIFETIME_LIMIT_1__EN_WARN__SHIFT 0x1f
#define SPI_WF_LIFETIME_LIMIT_2__MAX_CNT_MASK 0x7fffffff
#define SPI_WF_LIFETIME_LIMIT_2__MAX_CNT__SHIFT 0x0
#define SPI_WF_LIFETIME_LIMIT_2__EN_WARN_MASK 0x80000000
#define SPI_WF_LIFETIME_LIMIT_2__EN_WARN__SHIFT 0x1f
#define SPI_WF_LIFETIME_LIMIT_3__MAX_CNT_MASK 0x7fffffff
#define SPI_WF_LIFETIME_LIMIT_3__MAX_CNT__SHIFT 0x0
#define SPI_WF_LIFETIME_LIMIT_3__EN_WARN_MASK 0x80000000
#define SPI_WF_LIFETIME_LIMIT_3__EN_WARN__SHIFT 0x1f
#define SPI_WF_LIFETIME_LIMIT_4__MAX_CNT_MASK 0x7fffffff
#define SPI_WF_LIFETIME_LIMIT_4__MAX_CNT__SHIFT 0x0
#define SPI_WF_LIFETIME_LIMIT_4__EN_WARN_MASK 0x80000000
#define SPI_WF_LIFETIME_LIMIT_4__EN_WARN__SHIFT 0x1f
#define SPI_WF_LIFETIME_LIMIT_5__MAX_CNT_MASK 0x7fffffff
#define SPI_WF_LIFETIME_LIMIT_5__MAX_CNT__SHIFT 0x0
#define SPI_WF_LIFETIME_LIMIT_5__EN_WARN_MASK 0x80000000
#define SPI_WF_LIFETIME_LIMIT_5__EN_WARN__SHIFT 0x1f
#define SPI_WF_LIFETIME_LIMIT_6__MAX_CNT_MASK 0x7fffffff
#define SPI_WF_LIFETIME_LIMIT_6__MAX_CNT__SHIFT 0x0
#define SPI_WF_LIFETIME_LIMIT_6__EN_WARN_MASK 0x80000000
#define SPI_WF_LIFETIME_LIMIT_6__EN_WARN__SHIFT 0x1f
#define SPI_WF_LIFETIME_LIMIT_7__MAX_CNT_MASK 0x7fffffff
#define SPI_WF_LIFETIME_LIMIT_7__MAX_CNT__SHIFT 0x0
#define SPI_WF_LIFETIME_LIMIT_7__EN_WARN_MASK 0x80000000
#define SPI_WF_LIFETIME_LIMIT_7__EN_WARN__SHIFT 0x1f
#define SPI_WF_LIFETIME_LIMIT_8__MAX_CNT_MASK 0x7fffffff
#define SPI_WF_LIFETIME_LIMIT_8__MAX_CNT__SHIFT 0x0
#define SPI_WF_LIFETIME_LIMIT_8__EN_WARN_MASK 0x80000000
#define SPI_WF_LIFETIME_LIMIT_8__EN_WARN__SHIFT 0x1f
#define SPI_WF_LIFETIME_LIMIT_9__MAX_CNT_MASK 0x7fffffff
#define SPI_WF_LIFETIME_LIMIT_9__MAX_CNT__SHIFT 0x0
#define SPI_WF_LIFETIME_LIMIT_9__EN_WARN_MASK 0x80000000
#define SPI_WF_LIFETIME_LIMIT_9__EN_WARN__SHIFT 0x1f
#define SPI_WF_LIFETIME_STATUS_0__MAX_CNT_MASK 0x7fffffff
#define SPI_WF_LIFETIME_STATUS_0__MAX_CNT__SHIFT 0x0
#define SPI_WF_LIFETIME_STATUS_0__INT_SENT_MASK 0x80000000
#define SPI_WF_LIFETIME_STATUS_0__INT_SENT__SHIFT 0x1f
#define SPI_WF_LIFETIME_STATUS_1__MAX_CNT_MASK 0x7fffffff
#define SPI_WF_LIFETIME_STATUS_1__MAX_CNT__SHIFT 0x0
#define SPI_WF_LIFETIME_STATUS_1__INT_SENT_MASK 0x80000000
#define SPI_WF_LIFETIME_STATUS_1__INT_SENT__SHIFT 0x1f
#define SPI_WF_LIFETIME_STATUS_2__MAX_CNT_MASK 0x7fffffff
#define SPI_WF_LIFETIME_STATUS_2__MAX_CNT__SHIFT 0x0
#define SPI_WF_LIFETIME_STATUS_2__INT_SENT_MASK 0x80000000
#define SPI_WF_LIFETIME_STATUS_2__INT_SENT__SHIFT 0x1f
#define SPI_WF_LIFETIME_STATUS_3__MAX_CNT_MASK 0x7fffffff
#define SPI_WF_LIFETIME_STATUS_3__MAX_CNT__SHIFT 0x0
#define SPI_WF_LIFETIME_STATUS_3__INT_SENT_MASK 0x80000000
#define SPI_WF_LIFETIME_STATUS_3__INT_SENT__SHIFT 0x1f
#define SPI_WF_LIFETIME_STATUS_4__MAX_CNT_MASK 0x7fffffff
#define SPI_WF_LIFETIME_STATUS_4__MAX_CNT__SHIFT 0x0
#define SPI_WF_LIFETIME_STATUS_4__INT_SENT_MASK 0x80000000
#define SPI_WF_LIFETIME_STATUS_4__INT_SENT__SHIFT 0x1f
#define SPI_WF_LIFETIME_STATUS_5__MAX_CNT_MASK 0x7fffffff
#define SPI_WF_LIFETIME_STATUS_5__MAX_CNT__SHIFT 0x0
#define SPI_WF_LIFETIME_STATUS_5__INT_SENT_MASK 0x80000000
#define SPI_WF_LIFETIME_STATUS_5__INT_SENT__SHIFT 0x1f
#define SPI_WF_LIFETIME_STATUS_6__MAX_CNT_MASK 0x7fffffff
#define SPI_WF_LIFETIME_STATUS_6__MAX_CNT__SHIFT 0x0
#define SPI_WF_LIFETIME_STATUS_6__INT_SENT_MASK 0x80000000
#define SPI_WF_LIFETIME_STATUS_6__INT_SENT__SHIFT 0x1f
#define SPI_WF_LIFETIME_STATUS_7__MAX_CNT_MASK 0x7fffffff
#define SPI_WF_LIFETIME_STATUS_7__MAX_CNT__SHIFT 0x0
#define SPI_WF_LIFETIME_STATUS_7__INT_SENT_MASK 0x80000000
#define SPI_WF_LIFETIME_STATUS_7__INT_SENT__SHIFT 0x1f
#define SPI_WF_LIFETIME_STATUS_8__MAX_CNT_MASK 0x7fffffff
#define SPI_WF_LIFETIME_STATUS_8__MAX_CNT__SHIFT 0x0
#define SPI_WF_LIFETIME_STATUS_8__INT_SENT_MASK 0x80000000
#define SPI_WF_LIFETIME_STATUS_8__INT_SENT__SHIFT 0x1f
#define SPI_WF_LIFETIME_STATUS_9__MAX_CNT_MASK 0x7fffffff
#define SPI_WF_LIFETIME_STATUS_9__MAX_CNT__SHIFT 0x0
#define SPI_WF_LIFETIME_STATUS_9__INT_SENT_MASK 0x80000000
#define SPI_WF_LIFETIME_STATUS_9__INT_SENT__SHIFT 0x1f
#define SPI_WF_LIFETIME_STATUS_10__MAX_CNT_MASK 0x7fffffff
#define SPI_WF_LIFETIME_STATUS_10__MAX_CNT__SHIFT 0x0
#define SPI_WF_LIFETIME_STATUS_10__INT_SENT_MASK 0x80000000
#define SPI_WF_LIFETIME_STATUS_10__INT_SENT__SHIFT 0x1f
#define SPI_WF_LIFETIME_STATUS_11__MAX_CNT_MASK 0x7fffffff
#define SPI_WF_LIFETIME_STATUS_11__MAX_CNT__SHIFT 0x0
#define SPI_WF_LIFETIME_STATUS_11__INT_SENT_MASK 0x80000000
#define SPI_WF_LIFETIME_STATUS_11__INT_SENT__SHIFT 0x1f
#define SPI_WF_LIFETIME_STATUS_12__MAX_CNT_MASK 0x7fffffff
#define SPI_WF_LIFETIME_STATUS_12__MAX_CNT__SHIFT 0x0
#define SPI_WF_LIFETIME_STATUS_12__INT_SENT_MASK 0x80000000
#define SPI_WF_LIFETIME_STATUS_12__INT_SENT__SHIFT 0x1f
#define SPI_WF_LIFETIME_STATUS_13__MAX_CNT_MASK 0x7fffffff
#define SPI_WF_LIFETIME_STATUS_13__MAX_CNT__SHIFT 0x0
#define SPI_WF_LIFETIME_STATUS_13__INT_SENT_MASK 0x80000000
#define SPI_WF_LIFETIME_STATUS_13__INT_SENT__SHIFT 0x1f
#define SPI_WF_LIFETIME_STATUS_14__MAX_CNT_MASK 0x7fffffff
#define SPI_WF_LIFETIME_STATUS_14__MAX_CNT__SHIFT 0x0
#define SPI_WF_LIFETIME_STATUS_14__INT_SENT_MASK 0x80000000
#define SPI_WF_LIFETIME_STATUS_14__INT_SENT__SHIFT 0x1f
#define SPI_WF_LIFETIME_STATUS_15__MAX_CNT_MASK 0x7fffffff
#define SPI_WF_LIFETIME_STATUS_15__MAX_CNT__SHIFT 0x0
#define SPI_WF_LIFETIME_STATUS_15__INT_SENT_MASK 0x80000000
#define SPI_WF_LIFETIME_STATUS_15__INT_SENT__SHIFT 0x1f
#define SPI_WF_LIFETIME_STATUS_16__MAX_CNT_MASK 0x7fffffff
#define SPI_WF_LIFETIME_STATUS_16__MAX_CNT__SHIFT 0x0
#define SPI_WF_LIFETIME_STATUS_16__INT_SENT_MASK 0x80000000
#define SPI_WF_LIFETIME_STATUS_16__INT_SENT__SHIFT 0x1f
#define SPI_WF_LIFETIME_STATUS_17__MAX_CNT_MASK 0x7fffffff
#define SPI_WF_LIFETIME_STATUS_17__MAX_CNT__SHIFT 0x0
#define SPI_WF_LIFETIME_STATUS_17__INT_SENT_MASK 0x80000000
#define SPI_WF_LIFETIME_STATUS_17__INT_SENT__SHIFT 0x1f
#define SPI_WF_LIFETIME_STATUS_18__MAX_CNT_MASK 0x7fffffff
#define SPI_WF_LIFETIME_STATUS_18__MAX_CNT__SHIFT 0x0
#define SPI_WF_LIFETIME_STATUS_18__INT_SENT_MASK 0x80000000
#define SPI_WF_LIFETIME_STATUS_18__INT_SENT__SHIFT 0x1f
#define SPI_WF_LIFETIME_STATUS_19__MAX_CNT_MASK 0x7fffffff
#define SPI_WF_LIFETIME_STATUS_19__MAX_CNT__SHIFT 0x0
#define SPI_WF_LIFETIME_STATUS_19__INT_SENT_MASK 0x80000000
#define SPI_WF_LIFETIME_STATUS_19__INT_SENT__SHIFT 0x1f
#define SPI_WF_LIFETIME_STATUS_20__MAX_CNT_MASK 0x7fffffff
#define SPI_WF_LIFETIME_STATUS_20__MAX_CNT__SHIFT 0x0
#define SPI_WF_LIFETIME_STATUS_20__INT_SENT_MASK 0x80000000
#define SPI_WF_LIFETIME_STATUS_20__INT_SENT__SHIFT 0x1f
#define SPI_WF_LIFETIME_DEBUG__START_VALUE_MASK 0x7fffffff
#define SPI_WF_LIFETIME_DEBUG__START_VALUE__SHIFT 0x0
#define SPI_WF_LIFETIME_DEBUG__OVERRIDE_EN_MASK 0x80000000
#define SPI_WF_LIFETIME_DEBUG__OVERRIDE_EN__SHIFT 0x1f
#define SPI_SLAVE_DEBUG_BUSY__LS_VTX_BUSY_MASK 0x1
#define SPI_SLAVE_DEBUG_BUSY__LS_VTX_BUSY__SHIFT 0x0
#define SPI_SLAVE_DEBUG_BUSY__HS_VTX_BUSY_MASK 0x2
#define SPI_SLAVE_DEBUG_BUSY__HS_VTX_BUSY__SHIFT 0x1
#define SPI_SLAVE_DEBUG_BUSY__ES_VTX_BUSY_MASK 0x4
#define SPI_SLAVE_DEBUG_BUSY__ES_VTX_BUSY__SHIFT 0x2
#define SPI_SLAVE_DEBUG_BUSY__GS_VTX_BUSY_MASK 0x8
#define SPI_SLAVE_DEBUG_BUSY__GS_VTX_BUSY__SHIFT 0x3
#define SPI_SLAVE_DEBUG_BUSY__VS_VTX_BUSY_MASK 0x10
#define SPI_SLAVE_DEBUG_BUSY__VS_VTX_BUSY__SHIFT 0x4
#define SPI_SLAVE_DEBUG_BUSY__VGPR_WC00_BUSY_MASK 0x20
#define SPI_SLAVE_DEBUG_BUSY__VGPR_WC00_BUSY__SHIFT 0x5
#define SPI_SLAVE_DEBUG_BUSY__VGPR_WC01_BUSY_MASK 0x40
#define SPI_SLAVE_DEBUG_BUSY__VGPR_WC01_BUSY__SHIFT 0x6
#define SPI_SLAVE_DEBUG_BUSY__VGPR_WC10_BUSY_MASK 0x80
#define SPI_SLAVE_DEBUG_BUSY__VGPR_WC10_BUSY__SHIFT 0x7
#define SPI_SLAVE_DEBUG_BUSY__VGPR_WC11_BUSY_MASK 0x100
#define SPI_SLAVE_DEBUG_BUSY__VGPR_WC11_BUSY__SHIFT 0x8
#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC00_BUSY_MASK 0x200
#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC00_BUSY__SHIFT 0x9
#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC01_BUSY_MASK 0x400
#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC01_BUSY__SHIFT 0xa
#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC02_BUSY_MASK 0x800
#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC02_BUSY__SHIFT 0xb
#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC03_BUSY_MASK 0x1000
#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC03_BUSY__SHIFT 0xc
#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC10_BUSY_MASK 0x2000
#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC10_BUSY__SHIFT 0xd
#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC11_BUSY_MASK 0x4000
#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC11_BUSY__SHIFT 0xe
#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC12_BUSY_MASK 0x8000
#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC12_BUSY__SHIFT 0xf
#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC13_BUSY_MASK 0x10000
#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC13_BUSY__SHIFT 0x10
#define SPI_SLAVE_DEBUG_BUSY__WAVEBUFFER0_BUSY_MASK 0x20000
#define SPI_SLAVE_DEBUG_BUSY__WAVEBUFFER0_BUSY__SHIFT 0x11
#define SPI_SLAVE_DEBUG_BUSY__WAVEBUFFER1_BUSY_MASK 0x40000
#define SPI_SLAVE_DEBUG_BUSY__WAVEBUFFER1_BUSY__SHIFT 0x12
#define SPI_SLAVE_DEBUG_BUSY__WAVE_WC0_BUSY_MASK 0x80000
#define SPI_SLAVE_DEBUG_BUSY__WAVE_WC0_BUSY__SHIFT 0x13
#define SPI_SLAVE_DEBUG_BUSY__WAVE_WC1_BUSY_MASK 0x100000
#define SPI_SLAVE_DEBUG_BUSY__WAVE_WC1_BUSY__SHIFT 0x14
#define SPI_SLAVE_DEBUG_BUSY__EVENT_CNTL_BUSY_MASK 0x200000
#define SPI_SLAVE_DEBUG_BUSY__EVENT_CNTL_BUSY__SHIFT 0x15
#define SPI_SLAVE_DEBUG_BUSY__SAVE_CTX_BUSY_MASK 0x400000
#define SPI_SLAVE_DEBUG_BUSY__SAVE_CTX_BUSY__SHIFT 0x16
#define SPI_LB_CTR_CTRL__LOAD_MASK 0x1
#define SPI_LB_CTR_CTRL__LOAD__SHIFT 0x0
#define SPI_LB_CU_MASK__CU_MASK_MASK 0xffff
#define SPI_LB_CU_MASK__CU_MASK__SHIFT 0x0
#define SPI_LB_DATA_REG__CNT_DATA_MASK 0xffffffff
#define SPI_LB_DATA_REG__CNT_DATA__SHIFT 0x0
#define SPI_PG_ENABLE_STATIC_CU_MASK__CU_MASK_MASK 0xffff
#define SPI_PG_ENABLE_STATIC_CU_MASK__CU_MASK__SHIFT 0x0
#define SPI_GDS_CREDITS__DS_DATA_CREDITS_MASK 0xff
#define SPI_GDS_CREDITS__DS_DATA_CREDITS__SHIFT 0x0
#define SPI_GDS_CREDITS__DS_CMD_CREDITS_MASK 0xff00
#define SPI_GDS_CREDITS__DS_CMD_CREDITS__SHIFT 0x8
#define SPI_GDS_CREDITS__UNUSED_MASK 0xffff0000
#define SPI_GDS_CREDITS__UNUSED__SHIFT 0x10
#define SPI_SX_EXPORT_BUFFER_SIZES__COLOR_BUFFER_SIZE_MASK 0xffff
#define SPI_SX_EXPORT_BUFFER_SIZES__COLOR_BUFFER_SIZE__SHIFT 0x0
#define SPI_SX_EXPORT_BUFFER_SIZES__POSITION_BUFFER_SIZE_MASK 0xffff0000
#define SPI_SX_EXPORT_BUFFER_SIZES__POSITION_BUFFER_SIZE__SHIFT 0x10
#define SPI_SX_SCOREBOARD_BUFFER_SIZES__COLOR_SCOREBOARD_SIZE_MASK 0xffff
#define SPI_SX_SCOREBOARD_BUFFER_SIZES__COLOR_SCOREBOARD_SIZE__SHIFT 0x0
#define SPI_SX_SCOREBOARD_BUFFER_SIZES__POSITION_SCOREBOARD_SIZE_MASK 0xffff0000
#define SPI_SX_SCOREBOARD_BUFFER_SIZES__POSITION_SCOREBOARD_SIZE__SHIFT 0x10
#define SPI_CSQ_WF_ACTIVE_STATUS__ACTIVE_MASK 0xffffffff
#define SPI_CSQ_WF_ACTIVE_STATUS__ACTIVE__SHIFT 0x0
#define SPI_CSQ_WF_ACTIVE_COUNT_0__COUNT_MASK 0x7ff
#define SPI_CSQ_WF_ACTIVE_COUNT_0__COUNT__SHIFT 0x0
#define SPI_CSQ_WF_ACTIVE_COUNT_1__COUNT_MASK 0x7ff
#define SPI_CSQ_WF_ACTIVE_COUNT_1__COUNT__SHIFT 0x0
#define SPI_CSQ_WF_ACTIVE_COUNT_2__COUNT_MASK 0x7ff
#define SPI_CSQ_WF_ACTIVE_COUNT_2__COUNT__SHIFT 0x0
#define SPI_CSQ_WF_ACTIVE_COUNT_3__COUNT_MASK 0x7ff
#define SPI_CSQ_WF_ACTIVE_COUNT_3__COUNT__SHIFT 0x0
#define SPI_CSQ_WF_ACTIVE_COUNT_4__COUNT_MASK 0x7ff
#define SPI_CSQ_WF_ACTIVE_COUNT_4__COUNT__SHIFT 0x0
#define SPI_CSQ_WF_ACTIVE_COUNT_5__COUNT_MASK 0x7ff
#define SPI_CSQ_WF_ACTIVE_COUNT_5__COUNT__SHIFT 0x0
#define SPI_CSQ_WF_ACTIVE_COUNT_6__COUNT_MASK 0x7ff
#define SPI_CSQ_WF_ACTIVE_COUNT_6__COUNT__SHIFT 0x0
#define SPI_CSQ_WF_ACTIVE_COUNT_7__COUNT_MASK 0x7ff
#define SPI_CSQ_WF_ACTIVE_COUNT_7__COUNT__SHIFT 0x0
#define BCI_DEBUG_READ__DATA_MASK 0xffffff
#define BCI_DEBUG_READ__DATA__SHIFT 0x0
#define SPI_P0_TRAP_SCREEN_PSBA_LO__MEM_BASE_MASK 0xffffffff
#define SPI_P0_TRAP_SCREEN_PSBA_LO__MEM_BASE__SHIFT 0x0
#define SPI_P0_TRAP_SCREEN_PSBA_HI__MEM_BASE_MASK 0xff
#define SPI_P0_TRAP_SCREEN_PSBA_HI__MEM_BASE__SHIFT 0x0
#define SPI_P0_TRAP_SCREEN_PSMA_LO__MEM_BASE_MASK 0xffffffff
#define SPI_P0_TRAP_SCREEN_PSMA_LO__MEM_BASE__SHIFT 0x0
#define SPI_P0_TRAP_SCREEN_PSMA_HI__MEM_BASE_MASK 0xff
#define SPI_P0_TRAP_SCREEN_PSMA_HI__MEM_BASE__SHIFT 0x0
#define SPI_P0_TRAP_SCREEN_GPR_MIN__VGPR_MIN_MASK 0x3f
#define SPI_P0_TRAP_SCREEN_GPR_MIN__VGPR_MIN__SHIFT 0x0
#define SPI_P0_TRAP_SCREEN_GPR_MIN__SGPR_MIN_MASK 0x3c0
#define SPI_P0_TRAP_SCREEN_GPR_MIN__SGPR_MIN__SHIFT 0x6
#define SPI_P1_TRAP_SCREEN_PSBA_LO__MEM_BASE_MASK 0xffffffff
#define SPI_P1_TRAP_SCREEN_PSBA_LO__MEM_BASE__SHIFT 0x0
#define SPI_P1_TRAP_SCREEN_PSBA_HI__MEM_BASE_MASK 0xff
#define SPI_P1_TRAP_SCREEN_PSBA_HI__MEM_BASE__SHIFT 0x0
#define SPI_P1_TRAP_SCREEN_PSMA_LO__MEM_BASE_MASK 0xffffffff
#define SPI_P1_TRAP_SCREEN_PSMA_LO__MEM_BASE__SHIFT 0x0
#define SPI_P1_TRAP_SCREEN_PSMA_HI__MEM_BASE_MASK 0xff
#define SPI_P1_TRAP_SCREEN_PSMA_HI__MEM_BASE__SHIFT 0x0
#define SPI_P1_TRAP_SCREEN_GPR_MIN__VGPR_MIN_MASK 0x3f
#define SPI_P1_TRAP_SCREEN_GPR_MIN__VGPR_MIN__SHIFT 0x0
#define SPI_P1_TRAP_SCREEN_GPR_MIN__SGPR_MIN_MASK 0x3c0
#define SPI_P1_TRAP_SCREEN_GPR_MIN__SGPR_MIN__SHIFT 0x6
#define SPI_SHADER_TBA_LO_PS__MEM_BASE_MASK 0xffffffff
#define SPI_SHADER_TBA_LO_PS__MEM_BASE__SHIFT 0x0
#define SPI_SHADER_TBA_HI_PS__MEM_BASE_MASK 0xff
#define SPI_SHADER_TBA_HI_PS__MEM_BASE__SHIFT 0x0
#define SPI_SHADER_TMA_LO_PS__MEM_BASE_MASK 0xffffffff
#define SPI_SHADER_TMA_LO_PS__MEM_BASE__SHIFT 0x0
#define SPI_SHADER_TMA_HI_PS__MEM_BASE_MASK 0xff
#define SPI_SHADER_TMA_HI_PS__MEM_BASE__SHIFT 0x0
#define SPI_SHADER_PGM_LO_PS__MEM_BASE_MASK 0xffffffff
#define SPI_SHADER_PGM_LO_PS__MEM_BASE__SHIFT 0x0
#define SPI_SHADER_PGM_HI_PS__MEM_BASE_MASK 0xff
#define SPI_SHADER_PGM_HI_PS__MEM_BASE__SHIFT 0x0
#define SPI_SHADER_PGM_RSRC1_PS__VGPRS_MASK 0x3f
#define SPI_SHADER_PGM_RSRC1_PS__VGPRS__SHIFT 0x0
#define SPI_SHADER_PGM_RSRC1_PS__SGPRS_MASK 0x3c0
#define SPI_SHADER_PGM_RSRC1_PS__SGPRS__SHIFT 0x6
#define SPI_SHADER_PGM_RSRC1_PS__PRIORITY_MASK 0xc00
#define SPI_SHADER_PGM_RSRC1_PS__PRIORITY__SHIFT 0xa
#define SPI_SHADER_PGM_RSRC1_PS__FLOAT_MODE_MASK 0xff000
#define SPI_SHADER_PGM_RSRC1_PS__FLOAT_MODE__SHIFT 0xc
#define SPI_SHADER_PGM_RSRC1_PS__PRIV_MASK 0x100000
#define SPI_SHADER_PGM_RSRC1_PS__PRIV__SHIFT 0x14
#define SPI_SHADER_PGM_RSRC1_PS__DX10_CLAMP_MASK 0x200000
#define SPI_SHADER_PGM_RSRC1_PS__DX10_CLAMP__SHIFT 0x15
#define SPI_SHADER_PGM_RSRC1_PS__DEBUG_MODE_MASK 0x400000
#define SPI_SHADER_PGM_RSRC1_PS__DEBUG_MODE__SHIFT 0x16
#define SPI_SHADER_PGM_RSRC1_PS__IEEE_MODE_MASK 0x800000
#define SPI_SHADER_PGM_RSRC1_PS__IEEE_MODE__SHIFT 0x17
#define SPI_SHADER_PGM_RSRC1_PS__CU_GROUP_DISABLE_MASK 0x1000000
#define SPI_SHADER_PGM_RSRC1_PS__CU_GROUP_DISABLE__SHIFT 0x18
#define SPI_SHADER_PGM_RSRC1_PS__CACHE_CTL_MASK 0xe000000
#define SPI_SHADER_PGM_RSRC1_PS__CACHE_CTL__SHIFT 0x19
#define SPI_SHADER_PGM_RSRC1_PS__CDBG_USER_MASK 0x10000000
#define SPI_SHADER_PGM_RSRC1_PS__CDBG_USER__SHIFT 0x1c
#define SPI_SHADER_PGM_RSRC2_PS__SCRATCH_EN_MASK 0x1
#define SPI_SHADER_PGM_RSRC2_PS__SCRATCH_EN__SHIFT 0x0
#define SPI_SHADER_PGM_RSRC2_PS__USER_SGPR_MASK 0x3e
#define SPI_SHADER_PGM_RSRC2_PS__USER_SGPR__SHIFT 0x1
#define SPI_SHADER_PGM_RSRC2_PS__TRAP_PRESENT_MASK 0x40
#define SPI_SHADER_PGM_RSRC2_PS__TRAP_PRESENT__SHIFT 0x6
#define SPI_SHADER_PGM_RSRC2_PS__WAVE_CNT_EN_MASK 0x80
#define SPI_SHADER_PGM_RSRC2_PS__WAVE_CNT_EN__SHIFT 0x7
#define SPI_SHADER_PGM_RSRC2_PS__EXTRA_LDS_SIZE_MASK 0xff00
#define SPI_SHADER_PGM_RSRC2_PS__EXTRA_LDS_SIZE__SHIFT 0x8
#define SPI_SHADER_PGM_RSRC2_PS__EXCP_EN_MASK 0x1ff0000
#define SPI_SHADER_PGM_RSRC2_PS__EXCP_EN__SHIFT 0x10
#define SPI_SHADER_PGM_RSRC3_PS__CU_EN_MASK 0xffff
#define SPI_SHADER_PGM_RSRC3_PS__CU_EN__SHIFT 0x0
#define SPI_SHADER_PGM_RSRC3_PS__WAVE_LIMIT_MASK 0x3f0000
#define SPI_SHADER_PGM_RSRC3_PS__WAVE_LIMIT__SHIFT 0x10
#define SPI_SHADER_PGM_RSRC3_PS__LOCK_LOW_THRESHOLD_MASK 0x3c00000
#define SPI_SHADER_PGM_RSRC3_PS__LOCK_LOW_THRESHOLD__SHIFT 0x16
#define SPI_SHADER_USER_DATA_PS_0__DATA_MASK 0xffffffff
#define SPI_SHADER_USER_DATA_PS_0__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_PS_1__DATA_MASK 0xffffffff
#define SPI_SHADER_USER_DATA_PS_1__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_PS_2__DATA_MASK 0xffffffff
#define SPI_SHADER_USER_DATA_PS_2__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_PS_3__DATA_MASK 0xffffffff
#define SPI_SHADER_USER_DATA_PS_3__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_PS_4__DATA_MASK 0xffffffff
#define SPI_SHADER_USER_DATA_PS_4__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_PS_5__DATA_MASK 0xffffffff
#define SPI_SHADER_USER_DATA_PS_5__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_PS_6__DATA_MASK 0xffffffff
#define SPI_SHADER_USER_DATA_PS_6__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_PS_7__DATA_MASK 0xffffffff
#define SPI_SHADER_USER_DATA_PS_7__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_PS_8__DATA_MASK 0xffffffff
#define SPI_SHADER_USER_DATA_PS_8__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_PS_9__DATA_MASK 0xffffffff
#define SPI_SHADER_USER_DATA_PS_9__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_PS_10__DATA_MASK 0xffffffff
#define SPI_SHADER_USER_DATA_PS_10__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_PS_11__DATA_MASK 0xffffffff
#define SPI_SHADER_USER_DATA_PS_11__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_PS_12__DATA_MASK 0xffffffff
#define SPI_SHADER_USER_DATA_PS_12__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_PS_13__DATA_MASK 0xffffffff
#define SPI_SHADER_USER_DATA_PS_13__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_PS_14__DATA_MASK 0xffffffff
#define SPI_SHADER_USER_DATA_PS_14__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_PS_15__DATA_MASK 0xffffffff
#define SPI_SHADER_USER_DATA_PS_15__DATA__SHIFT 0x0
#define SPI_SHADER_TBA_LO_VS__MEM_BASE_MASK 0xffffffff
#define SPI_SHADER_TBA_LO_VS__MEM_BASE__SHIFT 0x0
#define SPI_SHADER_TBA_HI_VS__MEM_BASE_MASK 0xff
#define SPI_SHADER_TBA_HI_VS__MEM_BASE__SHIFT 0x0
#define SPI_SHADER_TMA_LO_VS__MEM_BASE_MASK 0xffffffff
#define SPI_SHADER_TMA_LO_VS__MEM_BASE__SHIFT 0x0
#define SPI_SHADER_TMA_HI_VS__MEM_BASE_MASK 0xff
#define SPI_SHADER_TMA_HI_VS__MEM_BASE__SHIFT 0x0
#define SPI_SHADER_PGM_LO_VS__MEM_BASE_MASK 0xffffffff
#define SPI_SHADER_PGM_LO_VS__MEM_BASE__SHIFT 0x0
#define SPI_SHADER_PGM_HI_VS__MEM_BASE_MASK 0xff
#define SPI_SHADER_PGM_HI_VS__MEM_BASE__SHIFT 0x0
#define SPI_SHADER_PGM_RSRC1_VS__VGPRS_MASK 0x3f
#define SPI_SHADER_PGM_RSRC1_VS__VGPRS__SHIFT 0x0
#define SPI_SHADER_PGM_RSRC1_VS__SGPRS_MASK 0x3c0
#define SPI_SHADER_PGM_RSRC1_VS__SGPRS__SHIFT 0x6
#define SPI_SHADER_PGM_RSRC1_VS__PRIORITY_MASK 0xc00
#define SPI_SHADER_PGM_RSRC1_VS__PRIORITY__SHIFT 0xa
#define SPI_SHADER_PGM_RSRC1_VS__FLOAT_MODE_MASK 0xff000
#define SPI_SHADER_PGM_RSRC1_VS__FLOAT_MODE__SHIFT 0xc
#define SPI_SHADER_PGM_RSRC1_VS__PRIV_MASK 0x100000
#define SPI_SHADER_PGM_RSRC1_VS__PRIV__SHIFT 0x14
#define SPI_SHADER_PGM_RSRC1_VS__DX10_CLAMP_MASK 0x200000
#define SPI_SHADER_PGM_RSRC1_VS__DX10_CLAMP__SHIFT 0x15
#define SPI_SHADER_PGM_RSRC1_VS__DEBUG_MODE_MASK 0x400000
#define SPI_SHADER_PGM_RSRC1_VS__DEBUG_MODE__SHIFT 0x16
#define SPI_SHADER_PGM_RSRC1_VS__IEEE_MODE_MASK 0x800000
#define SPI_SHADER_PGM_RSRC1_VS__IEEE_MODE__SHIFT 0x17
#define SPI_SHADER_PGM_RSRC1_VS__VGPR_COMP_CNT_MASK 0x3000000
#define SPI_SHADER_PGM_RSRC1_VS__VGPR_COMP_CNT__SHIFT 0x18
#define SPI_SHADER_PGM_RSRC1_VS__CU_GROUP_ENABLE_MASK 0x4000000
#define SPI_SHADER_PGM_RSRC1_VS__CU_GROUP_ENABLE__SHIFT 0x1a
#define SPI_SHADER_PGM_RSRC1_VS__CACHE_CTL_MASK 0x38000000
#define SPI_SHADER_PGM_RSRC1_VS__CACHE_CTL__SHIFT 0x1b
#define SPI_SHADER_PGM_RSRC1_VS__CDBG_USER_MASK 0x40000000
#define SPI_SHADER_PGM_RSRC1_VS__CDBG_USER__SHIFT 0x1e
#define SPI_SHADER_PGM_RSRC2_VS__SCRATCH_EN_MASK 0x1
#define SPI_SHADER_PGM_RSRC2_VS__SCRATCH_EN__SHIFT 0x0
#define SPI_SHADER_PGM_RSRC2_VS__USER_SGPR_MASK 0x3e
#define SPI_SHADER_PGM_RSRC2_VS__USER_SGPR__SHIFT 0x1
#define SPI_SHADER_PGM_RSRC2_VS__TRAP_PRESENT_MASK 0x40
#define SPI_SHADER_PGM_RSRC2_VS__TRAP_PRESENT__SHIFT 0x6
#define SPI_SHADER_PGM_RSRC2_VS__OC_LDS_EN_MASK 0x80
#define SPI_SHADER_PGM_RSRC2_VS__OC_LDS_EN__SHIFT 0x7
#define SPI_SHADER_PGM_RSRC2_VS__SO_BASE0_EN_MASK 0x100
#define SPI_SHADER_PGM_RSRC2_VS__SO_BASE0_EN__SHIFT 0x8
#define SPI_SHADER_PGM_RSRC2_VS__SO_BASE1_EN_MASK 0x200
#define SPI_SHADER_PGM_RSRC2_VS__SO_BASE1_EN__SHIFT 0x9
#define SPI_SHADER_PGM_RSRC2_VS__SO_BASE2_EN_MASK 0x400
#define SPI_SHADER_PGM_RSRC2_VS__SO_BASE2_EN__SHIFT 0xa
#define SPI_SHADER_PGM_RSRC2_VS__SO_BASE3_EN_MASK 0x800
#define SPI_SHADER_PGM_RSRC2_VS__SO_BASE3_EN__SHIFT 0xb
#define SPI_SHADER_PGM_RSRC2_VS__SO_EN_MASK 0x1000
#define SPI_SHADER_PGM_RSRC2_VS__SO_EN__SHIFT 0xc
#define SPI_SHADER_PGM_RSRC2_VS__EXCP_EN_MASK 0x3fe000
#define SPI_SHADER_PGM_RSRC2_VS__EXCP_EN__SHIFT 0xd
#define SPI_SHADER_PGM_RSRC2_VS__DISPATCH_DRAW_EN_MASK 0x1000000
#define SPI_SHADER_PGM_RSRC2_VS__DISPATCH_DRAW_EN__SHIFT 0x18
#define SPI_SHADER_PGM_RSRC3_VS__CU_EN_MASK 0xffff
#define SPI_SHADER_PGM_RSRC3_VS__CU_EN__SHIFT 0x0
#define SPI_SHADER_PGM_RSRC3_VS__WAVE_LIMIT_MASK 0x3f0000
#define SPI_SHADER_PGM_RSRC3_VS__WAVE_LIMIT__SHIFT 0x10
#define SPI_SHADER_PGM_RSRC3_VS__LOCK_LOW_THRESHOLD_MASK 0x3c00000
#define SPI_SHADER_PGM_RSRC3_VS__LOCK_LOW_THRESHOLD__SHIFT 0x16
#define SPI_SHADER_LATE_ALLOC_VS__LIMIT_MASK 0x3f
#define SPI_SHADER_LATE_ALLOC_VS__LIMIT__SHIFT 0x0
#define SPI_SHADER_USER_DATA_VS_0__DATA_MASK 0xffffffff
#define SPI_SHADER_USER_DATA_VS_0__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_VS_1__DATA_MASK 0xffffffff
#define SPI_SHADER_USER_DATA_VS_1__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_VS_2__DATA_MASK 0xffffffff
#define SPI_SHADER_USER_DATA_VS_2__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_VS_3__DATA_MASK 0xffffffff
#define SPI_SHADER_USER_DATA_VS_3__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_VS_4__DATA_MASK 0xffffffff
#define SPI_SHADER_USER_DATA_VS_4__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_VS_5__DATA_MASK 0xffffffff
#define SPI_SHADER_USER_DATA_VS_5__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_VS_6__DATA_MASK 0xffffffff
#define SPI_SHADER_USER_DATA_VS_6__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_VS_7__DATA_MASK 0xffffffff
#define SPI_SHADER_USER_DATA_VS_7__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_VS_8__DATA_MASK 0xffffffff
#define SPI_SHADER_USER_DATA_VS_8__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_VS_9__DATA_MASK 0xffffffff
#define SPI_SHADER_USER_DATA_VS_9__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_VS_10__DATA_MASK 0xffffffff
#define SPI_SHADER_USER_DATA_VS_10__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_VS_11__DATA_MASK 0xffffffff
#define SPI_SHADER_USER_DATA_VS_11__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_VS_12__DATA_MASK 0xffffffff
#define SPI_SHADER_USER_DATA_VS_12__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_VS_13__DATA_MASK 0xffffffff
#define SPI_SHADER_USER_DATA_VS_13__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_VS_14__DATA_MASK 0xffffffff
#define SPI_SHADER_USER_DATA_VS_14__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_VS_15__DATA_MASK 0xffffffff
#define SPI_SHADER_USER_DATA_VS_15__DATA__SHIFT 0x0
#define SPI_SHADER_PGM_RSRC2_ES_VS__SCRATCH_EN_MASK 0x1
#define SPI_SHADER_PGM_RSRC2_ES_VS__SCRATCH_EN__SHIFT 0x0
#define SPI_SHADER_PGM_RSRC2_ES_VS__USER_SGPR_MASK 0x3e
#define SPI_SHADER_PGM_RSRC2_ES_VS__USER_SGPR__SHIFT 0x1
#define SPI_SHADER_PGM_RSRC2_ES_VS__TRAP_PRESENT_MASK 0x40
#define SPI_SHADER_PGM_RSRC2_ES_VS__TRAP_PRESENT__SHIFT 0x6
#define SPI_SHADER_PGM_RSRC2_ES_VS__OC_LDS_EN_MASK 0x80
#define SPI_SHADER_PGM_RSRC2_ES_VS__OC_LDS_EN__SHIFT 0x7
#define SPI_SHADER_PGM_RSRC2_ES_VS__EXCP_EN_MASK 0x1ff00
#define SPI_SHADER_PGM_RSRC2_ES_VS__EXCP_EN__SHIFT 0x8
#define SPI_SHADER_PGM_RSRC2_ES_VS__LDS_SIZE_MASK 0x1ff00000
#define SPI_SHADER_PGM_RSRC2_ES_VS__LDS_SIZE__SHIFT 0x14
#define SPI_SHADER_PGM_RSRC2_LS_VS__SCRATCH_EN_MASK 0x1
#define SPI_SHADER_PGM_RSRC2_LS_VS__SCRATCH_EN__SHIFT 0x0
#define SPI_SHADER_PGM_RSRC2_LS_VS__USER_SGPR_MASK 0x3e
#define SPI_SHADER_PGM_RSRC2_LS_VS__USER_SGPR__SHIFT 0x1
#define SPI_SHADER_PGM_RSRC2_LS_VS__TRAP_PRESENT_MASK 0x40
#define SPI_SHADER_PGM_RSRC2_LS_VS__TRAP_PRESENT__SHIFT 0x6
#define SPI_SHADER_PGM_RSRC2_LS_VS__LDS_SIZE_MASK 0xff80
#define SPI_SHADER_PGM_RSRC2_LS_VS__LDS_SIZE__SHIFT 0x7
#define SPI_SHADER_PGM_RSRC2_LS_VS__EXCP_EN_MASK 0x1ff0000
#define SPI_SHADER_PGM_RSRC2_LS_VS__EXCP_EN__SHIFT 0x10
#define SPI_SHADER_TBA_LO_GS__MEM_BASE_MASK 0xffffffff
#define SPI_SHADER_TBA_LO_GS__MEM_BASE__SHIFT 0x0
#define SPI_SHADER_TBA_HI_GS__MEM_BASE_MASK 0xff
#define SPI_SHADER_TBA_HI_GS__MEM_BASE__SHIFT 0x0
#define SPI_SHADER_TMA_LO_GS__MEM_BASE_MASK 0xffffffff
#define SPI_SHADER_TMA_LO_GS__MEM_BASE__SHIFT 0x0
#define SPI_SHADER_TMA_HI_GS__MEM_BASE_MASK 0xff
#define SPI_SHADER_TMA_HI_GS__MEM_BASE__SHIFT 0x0
#define SPI_SHADER_PGM_LO_GS__MEM_BASE_MASK 0xffffffff
#define SPI_SHADER_PGM_LO_GS__MEM_BASE__SHIFT 0x0
#define SPI_SHADER_PGM_HI_GS__MEM_BASE_MASK 0xff
#define SPI_SHADER_PGM_HI_GS__MEM_BASE__SHIFT 0x0
#define SPI_SHADER_PGM_RSRC1_GS__VGPRS_MASK 0x3f
#define SPI_SHADER_PGM_RSRC1_GS__VGPRS__SHIFT 0x0
#define SPI_SHADER_PGM_RSRC1_GS__SGPRS_MASK 0x3c0
#define SPI_SHADER_PGM_RSRC1_GS__SGPRS__SHIFT 0x6
#define SPI_SHADER_PGM_RSRC1_GS__PRIORITY_MASK 0xc00
#define SPI_SHADER_PGM_RSRC1_GS__PRIORITY__SHIFT 0xa
#define SPI_SHADER_PGM_RSRC1_GS__FLOAT_MODE_MASK 0xff000
#define SPI_SHADER_PGM_RSRC1_GS__FLOAT_MODE__SHIFT 0xc
#define SPI_SHADER_PGM_RSRC1_GS__PRIV_MASK 0x100000
#define SPI_SHADER_PGM_RSRC1_GS__PRIV__SHIFT 0x14
#define SPI_SHADER_PGM_RSRC1_GS__DX10_CLAMP_MASK 0x200000
#define SPI_SHADER_PGM_RSRC1_GS__DX10_CLAMP__SHIFT 0x15
#define SPI_SHADER_PGM_RSRC1_GS__DEBUG_MODE_MASK 0x400000
#define SPI_SHADER_PGM_RSRC1_GS__DEBUG_MODE__SHIFT 0x16
#define SPI_SHADER_PGM_RSRC1_GS__IEEE_MODE_MASK 0x800000
#define SPI_SHADER_PGM_RSRC1_GS__IEEE_MODE__SHIFT 0x17
#define SPI_SHADER_PGM_RSRC1_GS__CU_GROUP_ENABLE_MASK 0x1000000
#define SPI_SHADER_PGM_RSRC1_GS__CU_GROUP_ENABLE__SHIFT 0x18
#define SPI_SHADER_PGM_RSRC1_GS__CACHE_CTL_MASK 0xe000000
#define SPI_SHADER_PGM_RSRC1_GS__CACHE_CTL__SHIFT 0x19
#define SPI_SHADER_PGM_RSRC1_GS__CDBG_USER_MASK 0x10000000
#define SPI_SHADER_PGM_RSRC1_GS__CDBG_USER__SHIFT 0x1c
#define SPI_SHADER_PGM_RSRC2_GS__SCRATCH_EN_MASK 0x1
#define SPI_SHADER_PGM_RSRC2_GS__SCRATCH_EN__SHIFT 0x0
#define SPI_SHADER_PGM_RSRC2_GS__USER_SGPR_MASK 0x3e
#define SPI_SHADER_PGM_RSRC2_GS__USER_SGPR__SHIFT 0x1
#define SPI_SHADER_PGM_RSRC2_GS__TRAP_PRESENT_MASK 0x40
#define SPI_SHADER_PGM_RSRC2_GS__TRAP_PRESENT__SHIFT 0x6
#define SPI_SHADER_PGM_RSRC2_GS__EXCP_EN_MASK 0xff80
#define SPI_SHADER_PGM_RSRC2_GS__EXCP_EN__SHIFT 0x7
#define SPI_SHADER_PGM_RSRC3_GS__CU_EN_MASK 0xffff
#define SPI_SHADER_PGM_RSRC3_GS__CU_EN__SHIFT 0x0
#define SPI_SHADER_PGM_RSRC3_GS__WAVE_LIMIT_MASK 0x3f0000
#define SPI_SHADER_PGM_RSRC3_GS__WAVE_LIMIT__SHIFT 0x10
#define SPI_SHADER_PGM_RSRC3_GS__LOCK_LOW_THRESHOLD_MASK 0x3c00000
#define SPI_SHADER_PGM_RSRC3_GS__LOCK_LOW_THRESHOLD__SHIFT 0x16
#define SPI_SHADER_PGM_RSRC3_GS__GROUP_FIFO_DEPTH_MASK 0xfc000000
#define SPI_SHADER_PGM_RSRC3_GS__GROUP_FIFO_DEPTH__SHIFT 0x1a
#define SPI_SHADER_USER_DATA_GS_0__DATA_MASK 0xffffffff
#define SPI_SHADER_USER_DATA_GS_0__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_GS_1__DATA_MASK 0xffffffff
#define SPI_SHADER_USER_DATA_GS_1__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_GS_2__DATA_MASK 0xffffffff
#define SPI_SHADER_USER_DATA_GS_2__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_GS_3__DATA_MASK 0xffffffff
#define SPI_SHADER_USER_DATA_GS_3__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_GS_4__DATA_MASK 0xffffffff
#define SPI_SHADER_USER_DATA_GS_4__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_GS_5__DATA_MASK 0xffffffff
#define SPI_SHADER_USER_DATA_GS_5__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_GS_6__DATA_MASK 0xffffffff
#define SPI_SHADER_USER_DATA_GS_6__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_GS_7__DATA_MASK 0xffffffff
#define SPI_SHADER_USER_DATA_GS_7__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_GS_8__DATA_MASK 0xffffffff
#define SPI_SHADER_USER_DATA_GS_8__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_GS_9__DATA_MASK 0xffffffff
#define SPI_SHADER_USER_DATA_GS_9__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_GS_10__DATA_MASK 0xffffffff
#define SPI_SHADER_USER_DATA_GS_10__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_GS_11__DATA_MASK 0xffffffff
#define SPI_SHADER_USER_DATA_GS_11__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_GS_12__DATA_MASK 0xffffffff
#define SPI_SHADER_USER_DATA_GS_12__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_GS_13__DATA_MASK 0xffffffff
#define SPI_SHADER_USER_DATA_GS_13__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_GS_14__DATA_MASK 0xffffffff
#define SPI_SHADER_USER_DATA_GS_14__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_GS_15__DATA_MASK 0xffffffff
#define SPI_SHADER_USER_DATA_GS_15__DATA__SHIFT 0x0
#define SPI_SHADER_PGM_RSRC2_ES_GS__SCRATCH_EN_MASK 0x1
#define SPI_SHADER_PGM_RSRC2_ES_GS__SCRATCH_EN__SHIFT 0x0
#define SPI_SHADER_PGM_RSRC2_ES_GS__USER_SGPR_MASK 0x3e
#define SPI_SHADER_PGM_RSRC2_ES_GS__USER_SGPR__SHIFT 0x1
#define SPI_SHADER_PGM_RSRC2_ES_GS__TRAP_PRESENT_MASK 0x40
#define SPI_SHADER_PGM_RSRC2_ES_GS__TRAP_PRESENT__SHIFT 0x6
#define SPI_SHADER_PGM_RSRC2_ES_GS__OC_LDS_EN_MASK 0x80
#define SPI_SHADER_PGM_RSRC2_ES_GS__OC_LDS_EN__SHIFT 0x7
#define SPI_SHADER_PGM_RSRC2_ES_GS__EXCP_EN_MASK 0x1ff00
#define SPI_SHADER_PGM_RSRC2_ES_GS__EXCP_EN__SHIFT 0x8
#define SPI_SHADER_PGM_RSRC2_ES_GS__LDS_SIZE_MASK 0x1ff00000
#define SPI_SHADER_PGM_RSRC2_ES_GS__LDS_SIZE__SHIFT 0x14
#define SPI_SHADER_TBA_LO_ES__MEM_BASE_MASK 0xffffffff
#define SPI_SHADER_TBA_LO_ES__MEM_BASE__SHIFT 0x0
#define SPI_SHADER_TBA_HI_ES__MEM_BASE_MASK 0xff
#define SPI_SHADER_TBA_HI_ES__MEM_BASE__SHIFT 0x0
#define SPI_SHADER_TMA_LO_ES__MEM_BASE_MASK 0xffffffff
#define SPI_SHADER_TMA_LO_ES__MEM_BASE__SHIFT 0x0
#define SPI_SHADER_TMA_HI_ES__MEM_BASE_MASK 0xff
#define SPI_SHADER_TMA_HI_ES__MEM_BASE__SHIFT 0x0
#define SPI_SHADER_PGM_LO_ES__MEM_BASE_MASK 0xffffffff
#define SPI_SHADER_PGM_LO_ES__MEM_BASE__SHIFT 0x0
#define SPI_SHADER_PGM_HI_ES__MEM_BASE_MASK 0xff
#define SPI_SHADER_PGM_HI_ES__MEM_BASE__SHIFT 0x0
#define SPI_SHADER_PGM_RSRC1_ES__VGPRS_MASK 0x3f
#define SPI_SHADER_PGM_RSRC1_ES__VGPRS__SHIFT 0x0
#define SPI_SHADER_PGM_RSRC1_ES__SGPRS_MASK 0x3c0
#define SPI_SHADER_PGM_RSRC1_ES__SGPRS__SHIFT 0x6
#define SPI_SHADER_PGM_RSRC1_ES__PRIORITY_MASK 0xc00
#define SPI_SHADER_PGM_RSRC1_ES__PRIORITY__SHIFT 0xa
#define SPI_SHADER_PGM_RSRC1_ES__FLOAT_MODE_MASK 0xff000
#define SPI_SHADER_PGM_RSRC1_ES__FLOAT_MODE__SHIFT 0xc
#define SPI_SHADER_PGM_RSRC1_ES__PRIV_MASK 0x100000
#define SPI_SHADER_PGM_RSRC1_ES__PRIV__SHIFT 0x14
#define SPI_SHADER_PGM_RSRC1_ES__DX10_CLAMP_MASK 0x200000
#define SPI_SHADER_PGM_RSRC1_ES__DX10_CLAMP__SHIFT 0x15
#define SPI_SHADER_PGM_RSRC1_ES__DEBUG_MODE_MASK 0x400000
#define SPI_SHADER_PGM_RSRC1_ES__DEBUG_MODE__SHIFT 0x16
#define SPI_SHADER_PGM_RSRC1_ES__IEEE_MODE_MASK 0x800000
#define SPI_SHADER_PGM_RSRC1_ES__IEEE_MODE__SHIFT 0x17
#define SPI_SHADER_PGM_RSRC1_ES__VGPR_COMP_CNT_MASK 0x3000000
#define SPI_SHADER_PGM_RSRC1_ES__VGPR_COMP_CNT__SHIFT 0x18
#define SPI_SHADER_PGM_RSRC1_ES__CU_GROUP_ENABLE_MASK 0x4000000
#define SPI_SHADER_PGM_RSRC1_ES__CU_GROUP_ENABLE__SHIFT 0x1a
#define SPI_SHADER_PGM_RSRC1_ES__CACHE_CTL_MASK 0x38000000
#define SPI_SHADER_PGM_RSRC1_ES__CACHE_CTL__SHIFT 0x1b
#define SPI_SHADER_PGM_RSRC1_ES__CDBG_USER_MASK 0x40000000
#define SPI_SHADER_PGM_RSRC1_ES__CDBG_USER__SHIFT 0x1e
#define SPI_SHADER_PGM_RSRC2_ES__SCRATCH_EN_MASK 0x1
#define SPI_SHADER_PGM_RSRC2_ES__SCRATCH_EN__SHIFT 0x0
#define SPI_SHADER_PGM_RSRC2_ES__USER_SGPR_MASK 0x3e
#define SPI_SHADER_PGM_RSRC2_ES__USER_SGPR__SHIFT 0x1
#define SPI_SHADER_PGM_RSRC2_ES__TRAP_PRESENT_MASK 0x40
#define SPI_SHADER_PGM_RSRC2_ES__TRAP_PRESENT__SHIFT 0x6
#define SPI_SHADER_PGM_RSRC2_ES__OC_LDS_EN_MASK 0x80
#define SPI_SHADER_PGM_RSRC2_ES__OC_LDS_EN__SHIFT 0x7
#define SPI_SHADER_PGM_RSRC2_ES__EXCP_EN_MASK 0x1ff00
#define SPI_SHADER_PGM_RSRC2_ES__EXCP_EN__SHIFT 0x8
#define SPI_SHADER_PGM_RSRC2_ES__LDS_SIZE_MASK 0x1ff00000
#define SPI_SHADER_PGM_RSRC2_ES__LDS_SIZE__SHIFT 0x14
#define SPI_SHADER_PGM_RSRC3_ES__CU_EN_MASK 0xffff
#define SPI_SHADER_PGM_RSRC3_ES__CU_EN__SHIFT 0x0
#define SPI_SHADER_PGM_RSRC3_ES__WAVE_LIMIT_MASK 0x3f0000
#define SPI_SHADER_PGM_RSRC3_ES__WAVE_LIMIT__SHIFT 0x10
#define SPI_SHADER_PGM_RSRC3_ES__LOCK_LOW_THRESHOLD_MASK 0x3c00000
#define SPI_SHADER_PGM_RSRC3_ES__LOCK_LOW_THRESHOLD__SHIFT 0x16
#define SPI_SHADER_PGM_RSRC3_ES__GROUP_FIFO_DEPTH_MASK 0xfc000000
#define SPI_SHADER_PGM_RSRC3_ES__GROUP_FIFO_DEPTH__SHIFT 0x1a
#define SPI_SHADER_USER_DATA_ES_0__DATA_MASK 0xffffffff
#define SPI_SHADER_USER_DATA_ES_0__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_ES_1__DATA_MASK 0xffffffff
#define SPI_SHADER_USER_DATA_ES_1__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_ES_2__DATA_MASK 0xffffffff
#define SPI_SHADER_USER_DATA_ES_2__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_ES_3__DATA_MASK 0xffffffff
#define SPI_SHADER_USER_DATA_ES_3__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_ES_4__DATA_MASK 0xffffffff
#define SPI_SHADER_USER_DATA_ES_4__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_ES_5__DATA_MASK 0xffffffff
#define SPI_SHADER_USER_DATA_ES_5__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_ES_6__DATA_MASK 0xffffffff
#define SPI_SHADER_USER_DATA_ES_6__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_ES_7__DATA_MASK 0xffffffff
#define SPI_SHADER_USER_DATA_ES_7__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_ES_8__DATA_MASK 0xffffffff
#define SPI_SHADER_USER_DATA_ES_8__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_ES_9__DATA_MASK 0xffffffff
#define SPI_SHADER_USER_DATA_ES_9__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_ES_10__DATA_MASK 0xffffffff
#define SPI_SHADER_USER_DATA_ES_10__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_ES_11__DATA_MASK 0xffffffff
#define SPI_SHADER_USER_DATA_ES_11__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_ES_12__DATA_MASK 0xffffffff
#define SPI_SHADER_USER_DATA_ES_12__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_ES_13__DATA_MASK 0xffffffff
#define SPI_SHADER_USER_DATA_ES_13__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_ES_14__DATA_MASK 0xffffffff
#define SPI_SHADER_USER_DATA_ES_14__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_ES_15__DATA_MASK 0xffffffff
#define SPI_SHADER_USER_DATA_ES_15__DATA__SHIFT 0x0
#define SPI_SHADER_PGM_RSRC2_LS_ES__SCRATCH_EN_MASK 0x1
#define SPI_SHADER_PGM_RSRC2_LS_ES__SCRATCH_EN__SHIFT 0x0
#define SPI_SHADER_PGM_RSRC2_LS_ES__USER_SGPR_MASK 0x3e
#define SPI_SHADER_PGM_RSRC2_LS_ES__USER_SGPR__SHIFT 0x1
#define SPI_SHADER_PGM_RSRC2_LS_ES__TRAP_PRESENT_MASK 0x40
#define SPI_SHADER_PGM_RSRC2_LS_ES__TRAP_PRESENT__SHIFT 0x6
#define SPI_SHADER_PGM_RSRC2_LS_ES__LDS_SIZE_MASK 0xff80
#define SPI_SHADER_PGM_RSRC2_LS_ES__LDS_SIZE__SHIFT 0x7
#define SPI_SHADER_PGM_RSRC2_LS_ES__EXCP_EN_MASK 0x1ff0000
#define SPI_SHADER_PGM_RSRC2_LS_ES__EXCP_EN__SHIFT 0x10
#define SPI_SHADER_TBA_LO_HS__MEM_BASE_MASK 0xffffffff
#define SPI_SHADER_TBA_LO_HS__MEM_BASE__SHIFT 0x0
#define SPI_SHADER_TBA_HI_HS__MEM_BASE_MASK 0xff
#define SPI_SHADER_TBA_HI_HS__MEM_BASE__SHIFT 0x0
#define SPI_SHADER_TMA_LO_HS__MEM_BASE_MASK 0xffffffff
#define SPI_SHADER_TMA_LO_HS__MEM_BASE__SHIFT 0x0
#define SPI_SHADER_TMA_HI_HS__MEM_BASE_MASK 0xff
#define SPI_SHADER_TMA_HI_HS__MEM_BASE__SHIFT 0x0
#define SPI_SHADER_PGM_LO_HS__MEM_BASE_MASK 0xffffffff
#define SPI_SHADER_PGM_LO_HS__MEM_BASE__SHIFT 0x0
#define SPI_SHADER_PGM_HI_HS__MEM_BASE_MASK 0xff
#define SPI_SHADER_PGM_HI_HS__MEM_BASE__SHIFT 0x0
#define SPI_SHADER_PGM_RSRC1_HS__VGPRS_MASK 0x3f
#define SPI_SHADER_PGM_RSRC1_HS__VGPRS__SHIFT 0x0
#define SPI_SHADER_PGM_RSRC1_HS__SGPRS_MASK 0x3c0
#define SPI_SHADER_PGM_RSRC1_HS__SGPRS__SHIFT 0x6
#define SPI_SHADER_PGM_RSRC1_HS__PRIORITY_MASK 0xc00
#define SPI_SHADER_PGM_RSRC1_HS__PRIORITY__SHIFT 0xa
#define SPI_SHADER_PGM_RSRC1_HS__FLOAT_MODE_MASK 0xff000
#define SPI_SHADER_PGM_RSRC1_HS__FLOAT_MODE__SHIFT 0xc
#define SPI_SHADER_PGM_RSRC1_HS__PRIV_MASK 0x100000
#define SPI_SHADER_PGM_RSRC1_HS__PRIV__SHIFT 0x14
#define SPI_SHADER_PGM_RSRC1_HS__DX10_CLAMP_MASK 0x200000
#define SPI_SHADER_PGM_RSRC1_HS__DX10_CLAMP__SHIFT 0x15
#define SPI_SHADER_PGM_RSRC1_HS__DEBUG_MODE_MASK 0x400000
#define SPI_SHADER_PGM_RSRC1_HS__DEBUG_MODE__SHIFT 0x16
#define SPI_SHADER_PGM_RSRC1_HS__IEEE_MODE_MASK 0x800000
#define SPI_SHADER_PGM_RSRC1_HS__IEEE_MODE__SHIFT 0x17
#define SPI_SHADER_PGM_RSRC1_HS__CACHE_CTL_MASK 0x7000000
#define SPI_SHADER_PGM_RSRC1_HS__CACHE_CTL__SHIFT 0x18
#define SPI_SHADER_PGM_RSRC1_HS__CDBG_USER_MASK 0x8000000
#define SPI_SHADER_PGM_RSRC1_HS__CDBG_USER__SHIFT 0x1b
#define SPI_SHADER_PGM_RSRC2_HS__SCRATCH_EN_MASK 0x1
#define SPI_SHADER_PGM_RSRC2_HS__SCRATCH_EN__SHIFT 0x0
#define SPI_SHADER_PGM_RSRC2_HS__USER_SGPR_MASK 0x3e
#define SPI_SHADER_PGM_RSRC2_HS__USER_SGPR__SHIFT 0x1
#define SPI_SHADER_PGM_RSRC2_HS__TRAP_PRESENT_MASK 0x40
#define SPI_SHADER_PGM_RSRC2_HS__TRAP_PRESENT__SHIFT 0x6
#define SPI_SHADER_PGM_RSRC2_HS__OC_LDS_EN_MASK 0x80
#define SPI_SHADER_PGM_RSRC2_HS__OC_LDS_EN__SHIFT 0x7
#define SPI_SHADER_PGM_RSRC2_HS__TG_SIZE_EN_MASK 0x100
#define SPI_SHADER_PGM_RSRC2_HS__TG_SIZE_EN__SHIFT 0x8
#define SPI_SHADER_PGM_RSRC2_HS__EXCP_EN_MASK 0x3fe00
#define SPI_SHADER_PGM_RSRC2_HS__EXCP_EN__SHIFT 0x9
#define SPI_SHADER_PGM_RSRC3_HS__WAVE_LIMIT_MASK 0x3f
#define SPI_SHADER_PGM_RSRC3_HS__WAVE_LIMIT__SHIFT 0x0
#define SPI_SHADER_PGM_RSRC3_HS__LOCK_LOW_THRESHOLD_MASK 0x3c0
#define SPI_SHADER_PGM_RSRC3_HS__LOCK_LOW_THRESHOLD__SHIFT 0x6
#define SPI_SHADER_PGM_RSRC3_HS__GROUP_FIFO_DEPTH_MASK 0xfc00
#define SPI_SHADER_PGM_RSRC3_HS__GROUP_FIFO_DEPTH__SHIFT 0xa
#define SPI_SHADER_USER_DATA_HS_0__DATA_MASK 0xffffffff
#define SPI_SHADER_USER_DATA_HS_0__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_HS_1__DATA_MASK 0xffffffff
#define SPI_SHADER_USER_DATA_HS_1__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_HS_2__DATA_MASK 0xffffffff
#define SPI_SHADER_USER_DATA_HS_2__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_HS_3__DATA_MASK 0xffffffff
#define SPI_SHADER_USER_DATA_HS_3__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_HS_4__DATA_MASK 0xffffffff
#define SPI_SHADER_USER_DATA_HS_4__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_HS_5__DATA_MASK 0xffffffff
#define SPI_SHADER_USER_DATA_HS_5__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_HS_6__DATA_MASK 0xffffffff
#define SPI_SHADER_USER_DATA_HS_6__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_HS_7__DATA_MASK 0xffffffff
#define SPI_SHADER_USER_DATA_HS_7__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_HS_8__DATA_MASK 0xffffffff
#define SPI_SHADER_USER_DATA_HS_8__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_HS_9__DATA_MASK 0xffffffff
#define SPI_SHADER_USER_DATA_HS_9__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_HS_10__DATA_MASK 0xffffffff
#define SPI_SHADER_USER_DATA_HS_10__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_HS_11__DATA_MASK 0xffffffff
#define SPI_SHADER_USER_DATA_HS_11__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_HS_12__DATA_MASK 0xffffffff
#define SPI_SHADER_USER_DATA_HS_12__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_HS_13__DATA_MASK 0xffffffff
#define SPI_SHADER_USER_DATA_HS_13__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_HS_14__DATA_MASK 0xffffffff
#define SPI_SHADER_USER_DATA_HS_14__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_HS_15__DATA_MASK 0xffffffff
#define SPI_SHADER_USER_DATA_HS_15__DATA__SHIFT 0x0
#define SPI_SHADER_PGM_RSRC2_LS_HS__SCRATCH_EN_MASK 0x1
#define SPI_SHADER_PGM_RSRC2_LS_HS__SCRATCH_EN__SHIFT 0x0
#define SPI_SHADER_PGM_RSRC2_LS_HS__USER_SGPR_MASK 0x3e
#define SPI_SHADER_PGM_RSRC2_LS_HS__USER_SGPR__SHIFT 0x1
#define SPI_SHADER_PGM_RSRC2_LS_HS__TRAP_PRESENT_MASK 0x40
#define SPI_SHADER_PGM_RSRC2_LS_HS__TRAP_PRESENT__SHIFT 0x6
#define SPI_SHADER_PGM_RSRC2_LS_HS__LDS_SIZE_MASK 0xff80
#define SPI_SHADER_PGM_RSRC2_LS_HS__LDS_SIZE__SHIFT 0x7
#define SPI_SHADER_PGM_RSRC2_LS_HS__EXCP_EN_MASK 0x1ff0000
#define SPI_SHADER_PGM_RSRC2_LS_HS__EXCP_EN__SHIFT 0x10
#define SPI_SHADER_TBA_LO_LS__MEM_BASE_MASK 0xffffffff
#define SPI_SHADER_TBA_LO_LS__MEM_BASE__SHIFT 0x0
#define SPI_SHADER_TBA_HI_LS__MEM_BASE_MASK 0xff
#define SPI_SHADER_TBA_HI_LS__MEM_BASE__SHIFT 0x0
#define SPI_SHADER_TMA_LO_LS__MEM_BASE_MASK 0xffffffff
#define SPI_SHADER_TMA_LO_LS__MEM_BASE__SHIFT 0x0
#define SPI_SHADER_TMA_HI_LS__MEM_BASE_MASK 0xff
#define SPI_SHADER_TMA_HI_LS__MEM_BASE__SHIFT 0x0
#define SPI_SHADER_PGM_LO_LS__MEM_BASE_MASK 0xffffffff
#define SPI_SHADER_PGM_LO_LS__MEM_BASE__SHIFT 0x0
#define SPI_SHADER_PGM_HI_LS__MEM_BASE_MASK 0xff
#define SPI_SHADER_PGM_HI_LS__MEM_BASE__SHIFT 0x0
#define SPI_SHADER_PGM_RSRC1_LS__VGPRS_MASK 0x3f
#define SPI_SHADER_PGM_RSRC1_LS__VGPRS__SHIFT 0x0
#define SPI_SHADER_PGM_RSRC1_LS__SGPRS_MASK 0x3c0
#define SPI_SHADER_PGM_RSRC1_LS__SGPRS__SHIFT 0x6
#define SPI_SHADER_PGM_RSRC1_LS__PRIORITY_MASK 0xc00
#define SPI_SHADER_PGM_RSRC1_LS__PRIORITY__SHIFT 0xa
#define SPI_SHADER_PGM_RSRC1_LS__FLOAT_MODE_MASK 0xff000
#define SPI_SHADER_PGM_RSRC1_LS__FLOAT_MODE__SHIFT 0xc
#define SPI_SHADER_PGM_RSRC1_LS__PRIV_MASK 0x100000
#define SPI_SHADER_PGM_RSRC1_LS__PRIV__SHIFT 0x14
#define SPI_SHADER_PGM_RSRC1_LS__DX10_CLAMP_MASK 0x200000
#define SPI_SHADER_PGM_RSRC1_LS__DX10_CLAMP__SHIFT 0x15
#define SPI_SHADER_PGM_RSRC1_LS__DEBUG_MODE_MASK 0x400000
#define SPI_SHADER_PGM_RSRC1_LS__DEBUG_MODE__SHIFT 0x16
#define SPI_SHADER_PGM_RSRC1_LS__IEEE_MODE_MASK 0x800000
#define SPI_SHADER_PGM_RSRC1_LS__IEEE_MODE__SHIFT 0x17
#define SPI_SHADER_PGM_RSRC1_LS__VGPR_COMP_CNT_MASK 0x3000000
#define SPI_SHADER_PGM_RSRC1_LS__VGPR_COMP_CNT__SHIFT 0x18
#define SPI_SHADER_PGM_RSRC1_LS__CACHE_CTL_MASK 0x1c000000
#define SPI_SHADER_PGM_RSRC1_LS__CACHE_CTL__SHIFT 0x1a
#define SPI_SHADER_PGM_RSRC1_LS__CDBG_USER_MASK 0x20000000
#define SPI_SHADER_PGM_RSRC1_LS__CDBG_USER__SHIFT 0x1d
#define SPI_SHADER_PGM_RSRC2_LS__SCRATCH_EN_MASK 0x1
#define SPI_SHADER_PGM_RSRC2_LS__SCRATCH_EN__SHIFT 0x0
#define SPI_SHADER_PGM_RSRC2_LS__USER_SGPR_MASK 0x3e
#define SPI_SHADER_PGM_RSRC2_LS__USER_SGPR__SHIFT 0x1
#define SPI_SHADER_PGM_RSRC2_LS__TRAP_PRESENT_MASK 0x40
#define SPI_SHADER_PGM_RSRC2_LS__TRAP_PRESENT__SHIFT 0x6
#define SPI_SHADER_PGM_RSRC2_LS__LDS_SIZE_MASK 0xff80
#define SPI_SHADER_PGM_RSRC2_LS__LDS_SIZE__SHIFT 0x7
#define SPI_SHADER_PGM_RSRC2_LS__EXCP_EN_MASK 0x1ff0000
#define SPI_SHADER_PGM_RSRC2_LS__EXCP_EN__SHIFT 0x10
#define SPI_SHADER_PGM_RSRC3_LS__CU_EN_MASK 0xffff
#define SPI_SHADER_PGM_RSRC3_LS__CU_EN__SHIFT 0x0
#define SPI_SHADER_PGM_RSRC3_LS__WAVE_LIMIT_MASK 0x3f0000
#define SPI_SHADER_PGM_RSRC3_LS__WAVE_LIMIT__SHIFT 0x10
#define SPI_SHADER_PGM_RSRC3_LS__LOCK_LOW_THRESHOLD_MASK 0x3c00000
#define SPI_SHADER_PGM_RSRC3_LS__LOCK_LOW_THRESHOLD__SHIFT 0x16
#define SPI_SHADER_PGM_RSRC3_LS__GROUP_FIFO_DEPTH_MASK 0xfc000000
#define SPI_SHADER_PGM_RSRC3_LS__GROUP_FIFO_DEPTH__SHIFT 0x1a
#define SPI_SHADER_USER_DATA_LS_0__DATA_MASK 0xffffffff
#define SPI_SHADER_USER_DATA_LS_0__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_LS_1__DATA_MASK 0xffffffff
#define SPI_SHADER_USER_DATA_LS_1__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_LS_2__DATA_MASK 0xffffffff
#define SPI_SHADER_USER_DATA_LS_2__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_LS_3__DATA_MASK 0xffffffff
#define SPI_SHADER_USER_DATA_LS_3__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_LS_4__DATA_MASK 0xffffffff
#define SPI_SHADER_USER_DATA_LS_4__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_LS_5__DATA_MASK 0xffffffff
#define SPI_SHADER_USER_DATA_LS_5__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_LS_6__DATA_MASK 0xffffffff
#define SPI_SHADER_USER_DATA_LS_6__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_LS_7__DATA_MASK 0xffffffff
#define SPI_SHADER_USER_DATA_LS_7__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_LS_8__DATA_MASK 0xffffffff
#define SPI_SHADER_USER_DATA_LS_8__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_LS_9__DATA_MASK 0xffffffff
#define SPI_SHADER_USER_DATA_LS_9__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_LS_10__DATA_MASK 0xffffffff
#define SPI_SHADER_USER_DATA_LS_10__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_LS_11__DATA_MASK 0xffffffff
#define SPI_SHADER_USER_DATA_LS_11__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_LS_12__DATA_MASK 0xffffffff
#define SPI_SHADER_USER_DATA_LS_12__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_LS_13__DATA_MASK 0xffffffff
#define SPI_SHADER_USER_DATA_LS_13__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_LS_14__DATA_MASK 0xffffffff
#define SPI_SHADER_USER_DATA_LS_14__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_LS_15__DATA_MASK 0xffffffff
#define SPI_SHADER_USER_DATA_LS_15__DATA__SHIFT 0x0
#define SQ_CONFIG__UNUSED_MASK 0xff
#define SQ_CONFIG__UNUSED__SHIFT 0x0
#define SQ_CONFIG__DEBUG_EN_MASK 0x100
#define SQ_CONFIG__DEBUG_EN__SHIFT 0x8
#define SQ_CONFIG__DEBUG_SINGLE_MEMOP_MASK 0x200
#define SQ_CONFIG__DEBUG_SINGLE_MEMOP__SHIFT 0x9
#define SQ_CONFIG__DEBUG_ONE_INST_CLAUSE_MASK 0x400
#define SQ_CONFIG__DEBUG_ONE_INST_CLAUSE__SHIFT 0xa
#define SQ_CONFIG__EARLY_TA_DONE_DISABLE_MASK 0x1000
#define SQ_CONFIG__EARLY_TA_DONE_DISABLE__SHIFT 0xc
#define SQ_CONFIG__DUA_FLAT_LOCK_ENABLE_MASK 0x2000
#define SQ_CONFIG__DUA_FLAT_LOCK_ENABLE__SHIFT 0xd
#define SQ_CONFIG__DUA_LDS_BYPASS_DISABLE_MASK 0x4000
#define SQ_CONFIG__DUA_LDS_BYPASS_DISABLE__SHIFT 0xe
#define SQ_CONFIG__DUA_FLAT_LDS_PINGPONG_DISABLE_MASK 0x8000
#define SQ_CONFIG__DUA_FLAT_LDS_PINGPONG_DISABLE__SHIFT 0xf
#define SQ_CONFIG__DISABLE_VMEM_SOFT_CLAUSE_MASK 0x10000
#define SQ_CONFIG__DISABLE_VMEM_SOFT_CLAUSE__SHIFT 0x10
#define SQ_CONFIG__DISABLE_SMEM_SOFT_CLAUSE_MASK 0x20000
#define SQ_CONFIG__DISABLE_SMEM_SOFT_CLAUSE__SHIFT 0x11
#define SQ_CONFIG__ENABLE_HIPRIO_ON_EXP_RDY_VS_MASK 0x40000
#define SQ_CONFIG__ENABLE_HIPRIO_ON_EXP_RDY_VS__SHIFT 0x12
#define SQ_CONFIG__PRIO_VAL_ON_EXP_RDY_VS_MASK 0x180000
#define SQ_CONFIG__PRIO_VAL_ON_EXP_RDY_VS__SHIFT 0x13
#define SQ_CONFIG__REPLAY_SLEEP_CNT_MASK 0x1e00000
#define SQ_CONFIG__REPLAY_SLEEP_CNT__SHIFT 0x15
#define SQC_CONFIG__INST_CACHE_SIZE_MASK 0x3
#define SQC_CONFIG__INST_CACHE_SIZE__SHIFT 0x0
#define SQC_CONFIG__DATA_CACHE_SIZE_MASK 0xc
#define SQC_CONFIG__DATA_CACHE_SIZE__SHIFT 0x2
#define SQC_CONFIG__MISS_FIFO_DEPTH_MASK 0x30
#define SQC_CONFIG__MISS_FIFO_DEPTH__SHIFT 0x4
#define SQC_CONFIG__HIT_FIFO_DEPTH_MASK 0x40
#define SQC_CONFIG__HIT_FIFO_DEPTH__SHIFT 0x6
#define SQC_CONFIG__FORCE_ALWAYS_MISS_MASK 0x80
#define SQC_CONFIG__FORCE_ALWAYS_MISS__SHIFT 0x7
#define SQC_CONFIG__FORCE_IN_ORDER_MASK 0x100
#define SQC_CONFIG__FORCE_IN_ORDER__SHIFT 0x8
#define SQC_CONFIG__IDENTITY_HASH_BANK_MASK 0x200
#define SQC_CONFIG__IDENTITY_HASH_BANK__SHIFT 0x9
#define SQC_CONFIG__IDENTITY_HASH_SET_MASK 0x400
#define SQC_CONFIG__IDENTITY_HASH_SET__SHIFT 0xa
#define SQC_CONFIG__PER_VMID_INV_DISABLE_MASK 0x800
#define SQC_CONFIG__PER_VMID_INV_DISABLE__SHIFT 0xb
#define SQC_CONFIG__EVICT_LRU_MASK 0x3000
#define SQC_CONFIG__EVICT_LRU__SHIFT 0xc
#define SQC_CONFIG__FORCE_2_BANK_MASK 0x4000
#define SQC_CONFIG__FORCE_2_BANK__SHIFT 0xe
#define SQC_CONFIG__FORCE_1_BANK_MASK 0x8000
#define SQC_CONFIG__FORCE_1_BANK__SHIFT 0xf
#define SQC_CONFIG__LS_DISABLE_CLOCKS_MASK 0xff0000
#define SQC_CONFIG__LS_DISABLE_CLOCKS__SHIFT 0x10
#define SQC_CACHES__TARGET_INST_MASK 0x1
#define SQC_CACHES__TARGET_INST__SHIFT 0x0
#define SQC_CACHES__TARGET_DATA_MASK 0x2
#define SQC_CACHES__TARGET_DATA__SHIFT 0x1
#define SQC_CACHES__INVALIDATE_MASK 0x4
#define SQC_CACHES__INVALIDATE__SHIFT 0x2
#define SQC_CACHES__WRITEBACK_MASK 0x8
#define SQC_CACHES__WRITEBACK__SHIFT 0x3
#define SQC_CACHES__VOL_MASK 0x10
#define SQC_CACHES__VOL__SHIFT 0x4
#define SQC_CACHES__COMPLETE_MASK 0x10000
#define SQC_CACHES__COMPLETE__SHIFT 0x10
#define SQC_WRITEBACK__DWB_MASK 0x1
#define SQC_WRITEBACK__DWB__SHIFT 0x0
#define SQC_WRITEBACK__DIRTY_MASK 0x2
#define SQC_WRITEBACK__DIRTY__SHIFT 0x1
#define SQC_DSM_CNTL__SEL_DATA_ICACHE_BANKA_MASK 0x3
#define SQC_DSM_CNTL__SEL_DATA_ICACHE_BANKA__SHIFT 0x0
#define SQC_DSM_CNTL__EN_SINGLE_WR_ICACHE_BANKA_MASK 0x4
#define SQC_DSM_CNTL__EN_SINGLE_WR_ICACHE_BANKA__SHIFT 0x2
#define SQC_DSM_CNTL__SEL_DATA_ICACHE_BANKB_MASK 0x18
#define SQC_DSM_CNTL__SEL_DATA_ICACHE_BANKB__SHIFT 0x3
#define SQC_DSM_CNTL__EN_SINGLE_WR_ICACHE_BANKB_MASK 0x20
#define SQC_DSM_CNTL__EN_SINGLE_WR_ICACHE_BANKB__SHIFT 0x5
#define SQC_DSM_CNTL__SEL_DATA_ICACHE_BANKC_MASK 0xc0
#define SQC_DSM_CNTL__SEL_DATA_ICACHE_BANKC__SHIFT 0x6
#define SQC_DSM_CNTL__EN_SINGLE_WR_ICACHE_BANKC_MASK 0x100
#define SQC_DSM_CNTL__EN_SINGLE_WR_ICACHE_BANKC__SHIFT 0x8
#define SQC_DSM_CNTL__SEL_DATA_ICACHE_BANKD_MASK 0x600
#define SQC_DSM_CNTL__SEL_DATA_ICACHE_BANKD__SHIFT 0x9
#define SQC_DSM_CNTL__EN_SINGLE_WR_ICACHE_BANKD_MASK 0x800
#define SQC_DSM_CNTL__EN_SINGLE_WR_ICACHE_BANKD__SHIFT 0xb
#define SQC_DSM_CNTL__SEL_DATA_ICACHE_GATCL1_MASK 0x3000
#define SQC_DSM_CNTL__SEL_DATA_ICACHE_GATCL1__SHIFT 0xc
#define SQC_DSM_CNTL__EN_SINGLE_WR_ICACHE_GATCL1_MASK 0x4000
#define SQC_DSM_CNTL__EN_SINGLE_WR_ICACHE_GATCL1__SHIFT 0xe
#define SQC_DSM_CNTL__SEL_DATA_DCACHE_BANKA_MASK 0x18000
#define SQC_DSM_CNTL__SEL_DATA_DCACHE_BANKA__SHIFT 0xf
#define SQC_DSM_CNTL__EN_SINGLE_WR_DCACHE_BANKA_MASK 0x20000
#define SQC_DSM_CNTL__EN_SINGLE_WR_DCACHE_BANKA__SHIFT 0x11
#define SQC_DSM_CNTL__SEL_DATA_DCACHE_BANKB_MASK 0xc0000
#define SQC_DSM_CNTL__SEL_DATA_DCACHE_BANKB__SHIFT 0x12
#define SQC_DSM_CNTL__EN_SINGLE_WR_DCACHE_BANKB_MASK 0x100000
#define SQC_DSM_CNTL__EN_SINGLE_WR_DCACHE_BANKB__SHIFT 0x14
#define SQC_DSM_CNTL__SEL_DATA_DCACHE_BANKC_MASK 0x600000
#define SQC_DSM_CNTL__SEL_DATA_DCACHE_BANKC__SHIFT 0x15
#define SQC_DSM_CNTL__EN_SINGLE_WR_DCACHE_BANKC_MASK 0x800000
#define SQC_DSM_CNTL__EN_SINGLE_WR_DCACHE_BANKC__SHIFT 0x17
#define SQC_DSM_CNTL__SEL_DATA_DCACHE_BANKD_MASK 0x3000000
#define SQC_DSM_CNTL__SEL_DATA_DCACHE_BANKD__SHIFT 0x18
#define SQC_DSM_CNTL__EN_SINGLE_WR_DCACHE_BANKD_MASK 0x4000000
#define SQC_DSM_CNTL__EN_SINGLE_WR_DCACHE_BANKD__SHIFT 0x1a
#define SQC_DSM_CNTL__SEL_DATA_DCACHE_GATCL1_MASK 0x18000000
#define SQC_DSM_CNTL__SEL_DATA_DCACHE_GATCL1__SHIFT 0x1b
#define SQC_DSM_CNTL__EN_SINGLE_WR_DCACHE_GATCL1_MASK 0x20000000
#define SQC_DSM_CNTL__EN_SINGLE_WR_DCACHE_GATCL1__SHIFT 0x1d
#define SQ_RANDOM_WAVE_PRI__RET_MASK 0x7f
#define SQ_RANDOM_WAVE_PRI__RET__SHIFT 0x0
#define SQ_RANDOM_WAVE_PRI__RUI_MASK 0x380
#define SQ_RANDOM_WAVE_PRI__RUI__SHIFT 0x7
#define SQ_RANDOM_WAVE_PRI__RNG_MASK 0x1ffc00
#define SQ_RANDOM_WAVE_PRI__RNG__SHIFT 0xa
#define SQ_REG_CREDITS__SRBM_CREDITS_MASK 0x3f
#define SQ_REG_CREDITS__SRBM_CREDITS__SHIFT 0x0
#define SQ_REG_CREDITS__CMD_CREDITS_MASK 0xf00
#define SQ_REG_CREDITS__CMD_CREDITS__SHIFT 0x8
#define SQ_REG_CREDITS__REG_BUSY_MASK 0x10000000
#define SQ_REG_CREDITS__REG_BUSY__SHIFT 0x1c
#define SQ_REG_CREDITS__SRBM_OVERFLOW_MASK 0x20000000
#define SQ_REG_CREDITS__SRBM_OVERFLOW__SHIFT 0x1d
#define SQ_REG_CREDITS__IMMED_OVERFLOW_MASK 0x40000000
#define SQ_REG_CREDITS__IMMED_OVERFLOW__SHIFT 0x1e
#define SQ_REG_CREDITS__CMD_OVERFLOW_MASK 0x80000000
#define SQ_REG_CREDITS__CMD_OVERFLOW__SHIFT 0x1f
#define SQ_FIFO_SIZES__INTERRUPT_FIFO_SIZE_MASK 0xf
#define SQ_FIFO_SIZES__INTERRUPT_FIFO_SIZE__SHIFT 0x0
#define SQ_FIFO_SIZES__TTRACE_FIFO_SIZE_MASK 0xf00
#define SQ_FIFO_SIZES__TTRACE_FIFO_SIZE__SHIFT 0x8
#define SQ_FIFO_SIZES__EXPORT_BUF_SIZE_MASK 0x30000
#define SQ_FIFO_SIZES__EXPORT_BUF_SIZE__SHIFT 0x10
#define SQ_FIFO_SIZES__VMEM_DATA_FIFO_SIZE_MASK 0xc0000
#define SQ_FIFO_SIZES__VMEM_DATA_FIFO_SIZE__SHIFT 0x12
#define SQ_DSM_CNTL__WAVEFRONT_STALL_0_MASK 0x1
#define SQ_DSM_CNTL__WAVEFRONT_STALL_0__SHIFT 0x0
#define SQ_DSM_CNTL__WAVEFRONT_STALL_1_MASK 0x2
#define SQ_DSM_CNTL__WAVEFRONT_STALL_1__SHIFT 0x1
#define SQ_DSM_CNTL__SPI_BACKPRESSURE_0_MASK 0x4
#define SQ_DSM_CNTL__SPI_BACKPRESSURE_0__SHIFT 0x2
#define SQ_DSM_CNTL__SPI_BACKPRESSURE_1_MASK 0x8
#define SQ_DSM_CNTL__SPI_BACKPRESSURE_1__SHIFT 0x3
#define SQ_DSM_CNTL__SEL_DSM_SGPR_IRRITATOR_DATA0_MASK 0x100
#define SQ_DSM_CNTL__SEL_DSM_SGPR_IRRITATOR_DATA0__SHIFT 0x8
#define SQ_DSM_CNTL__SEL_DSM_SGPR_IRRITATOR_DATA1_MASK 0x200
#define SQ_DSM_CNTL__SEL_DSM_SGPR_IRRITATOR_DATA1__SHIFT 0x9
#define SQ_DSM_CNTL__SGPR_ENABLE_SINGLE_WRITE_MASK 0x400
#define SQ_DSM_CNTL__SGPR_ENABLE_SINGLE_WRITE__SHIFT 0xa
#define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA0_MASK 0x10000
#define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA0__SHIFT 0x10
#define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA1_MASK 0x20000
#define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA1__SHIFT 0x11
#define SQ_DSM_CNTL__LDS_ENABLE_SINGLE_WRITE01_MASK 0x40000
#define SQ_DSM_CNTL__LDS_ENABLE_SINGLE_WRITE01__SHIFT 0x12
#define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA2_MASK 0x80000
#define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA2__SHIFT 0x13
#define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA3_MASK 0x100000
#define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA3__SHIFT 0x14
#define SQ_DSM_CNTL__LDS_ENABLE_SINGLE_WRITE23_MASK 0x200000
#define SQ_DSM_CNTL__LDS_ENABLE_SINGLE_WRITE23__SHIFT 0x15
#define SQ_DSM_CNTL__SEL_DSM_SP_IRRITATOR_DATA0_MASK 0x1000000
#define SQ_DSM_CNTL__SEL_DSM_SP_IRRITATOR_DATA0__SHIFT 0x18
#define SQ_DSM_CNTL__SEL_DSM_SP_IRRITATOR_DATA1_MASK 0x2000000
#define SQ_DSM_CNTL__SEL_DSM_SP_IRRITATOR_DATA1__SHIFT 0x19
#define SQ_DSM_CNTL__SP_ENABLE_SINGLE_WRITE_MASK 0x4000000
#define SQ_DSM_CNTL__SP_ENABLE_SINGLE_WRITE__SHIFT 0x1a
#define CC_GC_SHADER_RATE_CONFIG__DPFP_RATE_MASK 0x6
#define CC_GC_SHADER_RATE_CONFIG__DPFP_RATE__SHIFT 0x1
#define CC_GC_SHADER_RATE_CONFIG__SQC_BALANCE_DISABLE_MASK 0x8
#define CC_GC_SHADER_RATE_CONFIG__SQC_BALANCE_DISABLE__SHIFT 0x3
#define CC_GC_SHADER_RATE_CONFIG__HALF_LDS_MASK 0x10
#define CC_GC_SHADER_RATE_CONFIG__HALF_LDS__SHIFT 0x4
#define GC_USER_SHADER_RATE_CONFIG__DPFP_RATE_MASK 0x6
#define GC_USER_SHADER_RATE_CONFIG__DPFP_RATE__SHIFT 0x1
#define GC_USER_SHADER_RATE_CONFIG__SQC_BALANCE_DISABLE_MASK 0x8
#define GC_USER_SHADER_RATE_CONFIG__SQC_BALANCE_DISABLE__SHIFT 0x3
#define GC_USER_SHADER_RATE_CONFIG__HALF_LDS_MASK 0x10
#define GC_USER_SHADER_RATE_CONFIG__HALF_LDS__SHIFT 0x4
#define SQ_INTERRUPT_AUTO_MASK__MASK_MASK 0xffffff
#define SQ_INTERRUPT_AUTO_MASK__MASK__SHIFT 0x0
#define SQ_INTERRUPT_MSG_CTRL__STALL_MASK 0x1
#define SQ_INTERRUPT_MSG_CTRL__STALL__SHIFT 0x0
#define SQ_PERFCOUNTER_CTRL__PS_EN_MASK 0x1
#define SQ_PERFCOUNTER_CTRL__PS_EN__SHIFT 0x0
#define SQ_PERFCOUNTER_CTRL__VS_EN_MASK 0x2
#define SQ_PERFCOUNTER_CTRL__VS_EN__SHIFT 0x1
#define SQ_PERFCOUNTER_CTRL__GS_EN_MASK 0x4
#define SQ_PERFCOUNTER_CTRL__GS_EN__SHIFT 0x2
#define SQ_PERFCOUNTER_CTRL__ES_EN_MASK 0x8
#define SQ_PERFCOUNTER_CTRL__ES_EN__SHIFT 0x3
#define SQ_PERFCOUNTER_CTRL__HS_EN_MASK 0x10
#define SQ_PERFCOUNTER_CTRL__HS_EN__SHIFT 0x4
#define SQ_PERFCOUNTER_CTRL__LS_EN_MASK 0x20
#define SQ_PERFCOUNTER_CTRL__LS_EN__SHIFT 0x5
#define SQ_PERFCOUNTER_CTRL__CS_EN_MASK 0x40
#define SQ_PERFCOUNTER_CTRL__CS_EN__SHIFT 0x6
#define SQ_PERFCOUNTER_CTRL__CNTR_RATE_MASK 0x1f00
#define SQ_PERFCOUNTER_CTRL__CNTR_RATE__SHIFT 0x8
#define SQ_PERFCOUNTER_CTRL__DISABLE_FLUSH_MASK 0x2000
#define SQ_PERFCOUNTER_CTRL__DISABLE_FLUSH__SHIFT 0xd
#define SQ_PERFCOUNTER_MASK__SH0_MASK_MASK 0xffff
#define SQ_PERFCOUNTER_MASK__SH0_MASK__SHIFT 0x0
#define SQ_PERFCOUNTER_MASK__SH1_MASK_MASK 0xffff0000
#define SQ_PERFCOUNTER_MASK__SH1_MASK__SHIFT 0x10
#define SQ_PERFCOUNTER_CTRL2__FORCE_EN_MASK 0x1
#define SQ_PERFCOUNTER_CTRL2__FORCE_EN__SHIFT 0x0
#define CC_SQC_BANK_DISABLE__SQC0_BANK_DISABLE_MASK 0xf0000
#define CC_SQC_BANK_DISABLE__SQC0_BANK_DISABLE__SHIFT 0x10
#define CC_SQC_BANK_DISABLE__SQC1_BANK_DISABLE_MASK 0xf00000
#define CC_SQC_BANK_DISABLE__SQC1_BANK_DISABLE__SHIFT 0x14
#define CC_SQC_BANK_DISABLE__SQC2_BANK_DISABLE_MASK 0xf000000
#define CC_SQC_BANK_DISABLE__SQC2_BANK_DISABLE__SHIFT 0x18
#define CC_SQC_BANK_DISABLE__SQC3_BANK_DISABLE_MASK 0xf0000000
#define CC_SQC_BANK_DISABLE__SQC3_BANK_DISABLE__SHIFT 0x1c
#define USER_SQC_BANK_DISABLE__SQC0_BANK_DISABLE_MASK 0xf0000
#define USER_SQC_BANK_DISABLE__SQC0_BANK_DISABLE__SHIFT 0x10
#define USER_SQC_BANK_DISABLE__SQC1_BANK_DISABLE_MASK 0xf00000
#define USER_SQC_BANK_DISABLE__SQC1_BANK_DISABLE__SHIFT 0x14
#define USER_SQC_BANK_DISABLE__SQC2_BANK_DISABLE_MASK 0xf000000
#define USER_SQC_BANK_DISABLE__SQC2_BANK_DISABLE__SHIFT 0x18
#define USER_SQC_BANK_DISABLE__SQC3_BANK_DISABLE_MASK 0xf0000000
#define USER_SQC_BANK_DISABLE__SQC3_BANK_DISABLE__SHIFT 0x1c
#define SQ_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff
#define SQ_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
#define SQ_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff
#define SQ_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
#define SQ_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffff
#define SQ_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0
#define SQ_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffff
#define SQ_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0
#define SQ_PERFCOUNTER4_LO__PERFCOUNTER_LO_MASK 0xffffffff
#define SQ_PERFCOUNTER4_LO__PERFCOUNTER_LO__SHIFT 0x0
#define SQ_PERFCOUNTER5_LO__PERFCOUNTER_LO_MASK 0xffffffff
#define SQ_PERFCOUNTER5_LO__PERFCOUNTER_LO__SHIFT 0x0
#define SQ_PERFCOUNTER6_LO__PERFCOUNTER_LO_MASK 0xffffffff
#define SQ_PERFCOUNTER6_LO__PERFCOUNTER_LO__SHIFT 0x0
#define SQ_PERFCOUNTER7_LO__PERFCOUNTER_LO_MASK 0xffffffff
#define SQ_PERFCOUNTER7_LO__PERFCOUNTER_LO__SHIFT 0x0
#define SQ_PERFCOUNTER8_LO__PERFCOUNTER_LO_MASK 0xffffffff
#define SQ_PERFCOUNTER8_LO__PERFCOUNTER_LO__SHIFT 0x0
#define SQ_PERFCOUNTER9_LO__PERFCOUNTER_LO_MASK 0xffffffff
#define SQ_PERFCOUNTER9_LO__PERFCOUNTER_LO__SHIFT 0x0
#define SQ_PERFCOUNTER10_LO__PERFCOUNTER_LO_MASK 0xffffffff
#define SQ_PERFCOUNTER10_LO__PERFCOUNTER_LO__SHIFT 0x0
#define SQ_PERFCOUNTER11_LO__PERFCOUNTER_LO_MASK 0xffffffff
#define SQ_PERFCOUNTER11_LO__PERFCOUNTER_LO__SHIFT 0x0
#define SQ_PERFCOUNTER12_LO__PERFCOUNTER_LO_MASK 0xffffffff
#define SQ_PERFCOUNTER12_LO__PERFCOUNTER_LO__SHIFT 0x0
#define SQ_PERFCOUNTER13_LO__PERFCOUNTER_LO_MASK 0xffffffff
#define SQ_PERFCOUNTER13_LO__PERFCOUNTER_LO__SHIFT 0x0
#define SQ_PERFCOUNTER14_LO__PERFCOUNTER_LO_MASK 0xffffffff
#define SQ_PERFCOUNTER14_LO__PERFCOUNTER_LO__SHIFT 0x0
#define SQ_PERFCOUNTER15_LO__PERFCOUNTER_LO_MASK 0xffffffff
#define SQ_PERFCOUNTER15_LO__PERFCOUNTER_LO__SHIFT 0x0
#define SQ_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff
#define SQ_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
#define SQ_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff
#define SQ_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
#define SQ_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffff
#define SQ_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0
#define SQ_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffff
#define SQ_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0
#define SQ_PERFCOUNTER4_HI__PERFCOUNTER_HI_MASK 0xffffffff
#define SQ_PERFCOUNTER4_HI__PERFCOUNTER_HI__SHIFT 0x0
#define SQ_PERFCOUNTER5_HI__PERFCOUNTER_HI_MASK 0xffffffff
#define SQ_PERFCOUNTER5_HI__PERFCOUNTER_HI__SHIFT 0x0
#define SQ_PERFCOUNTER6_HI__PERFCOUNTER_HI_MASK 0xffffffff
#define SQ_PERFCOUNTER6_HI__PERFCOUNTER_HI__SHIFT 0x0
#define SQ_PERFCOUNTER7_HI__PERFCOUNTER_HI_MASK 0xffffffff
#define SQ_PERFCOUNTER7_HI__PERFCOUNTER_HI__SHIFT 0x0
#define SQ_PERFCOUNTER8_HI__PERFCOUNTER_HI_MASK 0xffffffff
#define SQ_PERFCOUNTER8_HI__PERFCOUNTER_HI__SHIFT 0x0
#define SQ_PERFCOUNTER9_HI__PERFCOUNTER_HI_MASK 0xffffffff
#define SQ_PERFCOUNTER9_HI__PERFCOUNTER_HI__SHIFT 0x0
#define SQ_PERFCOUNTER10_HI__PERFCOUNTER_HI_MASK 0xffffffff
#define SQ_PERFCOUNTER10_HI__PERFCOUNTER_HI__SHIFT 0x0
#define SQ_PERFCOUNTER11_HI__PERFCOUNTER_HI_MASK 0xffffffff
#define SQ_PERFCOUNTER11_HI__PERFCOUNTER_HI__SHIFT 0x0
#define SQ_PERFCOUNTER12_HI__PERFCOUNTER_HI_MASK 0xffffffff
#define SQ_PERFCOUNTER12_HI__PERFCOUNTER_HI__SHIFT 0x0
#define SQ_PERFCOUNTER13_HI__PERFCOUNTER_HI_MASK 0xffffffff
#define SQ_PERFCOUNTER13_HI__PERFCOUNTER_HI__SHIFT 0x0
#define SQ_PERFCOUNTER14_HI__PERFCOUNTER_HI_MASK 0xffffffff
#define SQ_PERFCOUNTER14_HI__PERFCOUNTER_HI__SHIFT 0x0
#define SQ_PERFCOUNTER15_HI__PERFCOUNTER_HI_MASK 0xffffffff
#define SQ_PERFCOUNTER15_HI__PERFCOUNTER_HI__SHIFT 0x0
#define SQ_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x1ff
#define SQ_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
#define SQ_PERFCOUNTER0_SELECT__SQC_BANK_MASK_MASK 0xf000
#define SQ_PERFCOUNTER0_SELECT__SQC_BANK_MASK__SHIFT 0xc
#define SQ_PERFCOUNTER0_SELECT__SQC_CLIENT_MASK_MASK 0xf0000
#define SQ_PERFCOUNTER0_SELECT__SQC_CLIENT_MASK__SHIFT 0x10
#define SQ_PERFCOUNTER0_SELECT__SPM_MODE_MASK 0xf00000
#define SQ_PERFCOUNTER0_SELECT__SPM_MODE__SHIFT 0x14
#define SQ_PERFCOUNTER0_SELECT__SIMD_MASK_MASK 0xf000000
#define SQ_PERFCOUNTER0_SELECT__SIMD_MASK__SHIFT 0x18
#define SQ_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xf0000000
#define SQ_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c
#define SQ_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x1ff
#define SQ_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
#define SQ_PERFCOUNTER1_SELECT__SQC_BANK_MASK_MASK 0xf000
#define SQ_PERFCOUNTER1_SELECT__SQC_BANK_MASK__SHIFT 0xc
#define SQ_PERFCOUNTER1_SELECT__SQC_CLIENT_MASK_MASK 0xf0000
#define SQ_PERFCOUNTER1_SELECT__SQC_CLIENT_MASK__SHIFT 0x10
#define SQ_PERFCOUNTER1_SELECT__SPM_MODE_MASK 0xf00000
#define SQ_PERFCOUNTER1_SELECT__SPM_MODE__SHIFT 0x14
#define SQ_PERFCOUNTER1_SELECT__SIMD_MASK_MASK 0xf000000
#define SQ_PERFCOUNTER1_SELECT__SIMD_MASK__SHIFT 0x18
#define SQ_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xf0000000
#define SQ_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c
#define SQ_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x1ff
#define SQ_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0
#define SQ_PERFCOUNTER2_SELECT__SQC_BANK_MASK_MASK 0xf000
#define SQ_PERFCOUNTER2_SELECT__SQC_BANK_MASK__SHIFT 0xc
#define SQ_PERFCOUNTER2_SELECT__SQC_CLIENT_MASK_MASK 0xf0000
#define SQ_PERFCOUNTER2_SELECT__SQC_CLIENT_MASK__SHIFT 0x10
#define SQ_PERFCOUNTER2_SELECT__SPM_MODE_MASK 0xf00000
#define SQ_PERFCOUNTER2_SELECT__SPM_MODE__SHIFT 0x14
#define SQ_PERFCOUNTER2_SELECT__SIMD_MASK_MASK 0xf000000
#define SQ_PERFCOUNTER2_SELECT__SIMD_MASK__SHIFT 0x18
#define SQ_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xf0000000
#define SQ_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c
#define SQ_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x1ff
#define SQ_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0
#define SQ_PERFCOUNTER3_SELECT__SQC_BANK_MASK_MASK 0xf000
#define SQ_PERFCOUNTER3_SELECT__SQC_BANK_MASK__SHIFT 0xc
#define SQ_PERFCOUNTER3_SELECT__SQC_CLIENT_MASK_MASK 0xf0000
#define SQ_PERFCOUNTER3_SELECT__SQC_CLIENT_MASK__SHIFT 0x10
#define SQ_PERFCOUNTER3_SELECT__SPM_MODE_MASK 0xf00000
#define SQ_PERFCOUNTER3_SELECT__SPM_MODE__SHIFT 0x14
#define SQ_PERFCOUNTER3_SELECT__SIMD_MASK_MASK 0xf000000
#define SQ_PERFCOUNTER3_SELECT__SIMD_MASK__SHIFT 0x18
#define SQ_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xf0000000
#define SQ_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c
#define SQ_PERFCOUNTER4_SELECT__PERF_SEL_MASK 0x1ff
#define SQ_PERFCOUNTER4_SELECT__PERF_SEL__SHIFT 0x0
#define SQ_PERFCOUNTER4_SELECT__SQC_BANK_MASK_MASK 0xf000
#define SQ_PERFCOUNTER4_SELECT__SQC_BANK_MASK__SHIFT 0xc
#define SQ_PERFCOUNTER4_SELECT__SQC_CLIENT_MASK_MASK 0xf0000
#define SQ_PERFCOUNTER4_SELECT__SQC_CLIENT_MASK__SHIFT 0x10
#define SQ_PERFCOUNTER4_SELECT__SPM_MODE_MASK 0xf00000
#define SQ_PERFCOUNTER4_SELECT__SPM_MODE__SHIFT 0x14
#define SQ_PERFCOUNTER4_SELECT__SIMD_MASK_MASK 0xf000000
#define SQ_PERFCOUNTER4_SELECT__SIMD_MASK__SHIFT 0x18
#define SQ_PERFCOUNTER4_SELECT__PERF_MODE_MASK 0xf0000000
#define SQ_PERFCOUNTER4_SELECT__PERF_MODE__SHIFT 0x1c
#define SQ_PERFCOUNTER5_SELECT__PERF_SEL_MASK 0x1ff
#define SQ_PERFCOUNTER5_SELECT__PERF_SEL__SHIFT 0x0
#define SQ_PERFCOUNTER5_SELECT__SQC_BANK_MASK_MASK 0xf000
#define SQ_PERFCOUNTER5_SELECT__SQC_BANK_MASK__SHIFT 0xc
#define SQ_PERFCOUNTER5_SELECT__SQC_CLIENT_MASK_MASK 0xf0000
#define SQ_PERFCOUNTER5_SELECT__SQC_CLIENT_MASK__SHIFT 0x10
#define SQ_PERFCOUNTER5_SELECT__SPM_MODE_MASK 0xf00000
#define SQ_PERFCOUNTER5_SELECT__SPM_MODE__SHIFT 0x14
#define SQ_PERFCOUNTER5_SELECT__SIMD_MASK_MASK 0xf000000
#define SQ_PERFCOUNTER5_SELECT__SIMD_MASK__SHIFT 0x18
#define SQ_PERFCOUNTER5_SELECT__PERF_MODE_MASK 0xf0000000
#define SQ_PERFCOUNTER5_SELECT__PERF_MODE__SHIFT 0x1c
#define SQ_PERFCOUNTER6_SELECT__PERF_SEL_MASK 0x1ff
#define SQ_PERFCOUNTER6_SELECT__PERF_SEL__SHIFT 0x0
#define SQ_PERFCOUNTER6_SELECT__SQC_BANK_MASK_MASK 0xf000
#define SQ_PERFCOUNTER6_SELECT__SQC_BANK_MASK__SHIFT 0xc
#define SQ_PERFCOUNTER6_SELECT__SQC_CLIENT_MASK_MASK 0xf0000
#define SQ_PERFCOUNTER6_SELECT__SQC_CLIENT_MASK__SHIFT 0x10
#define SQ_PERFCOUNTER6_SELECT__SPM_MODE_MASK 0xf00000
#define SQ_PERFCOUNTER6_SELECT__SPM_MODE__SHIFT 0x14
#define SQ_PERFCOUNTER6_SELECT__SIMD_MASK_MASK 0xf000000
#define SQ_PERFCOUNTER6_SELECT__SIMD_MASK__SHIFT 0x18
#define SQ_PERFCOUNTER6_SELECT__PERF_MODE_MASK 0xf0000000
#define SQ_PERFCOUNTER6_SELECT__PERF_MODE__SHIFT 0x1c
#define SQ_PERFCOUNTER7_SELECT__PERF_SEL_MASK 0x1ff
#define SQ_PERFCOUNTER7_SELECT__PERF_SEL__SHIFT 0x0
#define SQ_PERFCOUNTER7_SELECT__SQC_BANK_MASK_MASK 0xf000
#define SQ_PERFCOUNTER7_SELECT__SQC_BANK_MASK__SHIFT 0xc
#define SQ_PERFCOUNTER7_SELECT__SQC_CLIENT_MASK_MASK 0xf0000
#define SQ_PERFCOUNTER7_SELECT__SQC_CLIENT_MASK__SHIFT 0x10
#define SQ_PERFCOUNTER7_SELECT__SPM_MODE_MASK 0xf00000
#define SQ_PERFCOUNTER7_SELECT__SPM_MODE__SHIFT 0x14
#define SQ_PERFCOUNTER7_SELECT__SIMD_MASK_MASK 0xf000000
#define SQ_PERFCOUNTER7_SELECT__SIMD_MASK__SHIFT 0x18
#define SQ_PERFCOUNTER7_SELECT__PERF_MODE_MASK 0xf0000000
#define SQ_PERFCOUNTER7_SELECT__PERF_MODE__SHIFT 0x1c
#define SQ_PERFCOUNTER8_SELECT__PERF_SEL_MASK 0x1ff
#define SQ_PERFCOUNTER8_SELECT__PERF_SEL__SHIFT 0x0
#define SQ_PERFCOUNTER8_SELECT__SQC_BANK_MASK_MASK 0xf000
#define SQ_PERFCOUNTER8_SELECT__SQC_BANK_MASK__SHIFT 0xc
#define SQ_PERFCOUNTER8_SELECT__SQC_CLIENT_MASK_MASK 0xf0000
#define SQ_PERFCOUNTER8_SELECT__SQC_CLIENT_MASK__SHIFT 0x10
#define SQ_PERFCOUNTER8_SELECT__SPM_MODE_MASK 0xf00000
#define SQ_PERFCOUNTER8_SELECT__SPM_MODE__SHIFT 0x14
#define SQ_PERFCOUNTER8_SELECT__SIMD_MASK_MASK 0xf000000
#define SQ_PERFCOUNTER8_SELECT__SIMD_MASK__SHIFT 0x18
#define SQ_PERFCOUNTER8_SELECT__PERF_MODE_MASK 0xf0000000
#define SQ_PERFCOUNTER8_SELECT__PERF_MODE__SHIFT 0x1c
#define SQ_PERFCOUNTER9_SELECT__PERF_SEL_MASK 0x1ff
#define SQ_PERFCOUNTER9_SELECT__PERF_SEL__SHIFT 0x0
#define SQ_PERFCOUNTER9_SELECT__SQC_BANK_MASK_MASK 0xf000
#define SQ_PERFCOUNTER9_SELECT__SQC_BANK_MASK__SHIFT 0xc
#define SQ_PERFCOUNTER9_SELECT__SQC_CLIENT_MASK_MASK 0xf0000
#define SQ_PERFCOUNTER9_SELECT__SQC_CLIENT_MASK__SHIFT 0x10
#define SQ_PERFCOUNTER9_SELECT__SPM_MODE_MASK 0xf00000
#define SQ_PERFCOUNTER9_SELECT__SPM_MODE__SHIFT 0x14
#define SQ_PERFCOUNTER9_SELECT__SIMD_MASK_MASK 0xf000000
#define SQ_PERFCOUNTER9_SELECT__SIMD_MASK__SHIFT 0x18
#define SQ_PERFCOUNTER9_SELECT__PERF_MODE_MASK 0xf0000000
#define SQ_PERFCOUNTER9_SELECT__PERF_MODE__SHIFT 0x1c
#define SQ_PERFCOUNTER10_SELECT__PERF_SEL_MASK 0x1ff
#define SQ_PERFCOUNTER10_SELECT__PERF_SEL__SHIFT 0x0
#define SQ_PERFCOUNTER10_SELECT__SQC_BANK_MASK_MASK 0xf000
#define SQ_PERFCOUNTER10_SELECT__SQC_BANK_MASK__SHIFT 0xc
#define SQ_PERFCOUNTER10_SELECT__SQC_CLIENT_MASK_MASK 0xf0000
#define SQ_PERFCOUNTER10_SELECT__SQC_CLIENT_MASK__SHIFT 0x10
#define SQ_PERFCOUNTER10_SELECT__SPM_MODE_MASK 0xf00000
#define SQ_PERFCOUNTER10_SELECT__SPM_MODE__SHIFT 0x14
#define SQ_PERFCOUNTER10_SELECT__SIMD_MASK_MASK 0xf000000
#define SQ_PERFCOUNTER10_SELECT__SIMD_MASK__SHIFT 0x18
#define SQ_PERFCOUNTER10_SELECT__PERF_MODE_MASK 0xf0000000
#define SQ_PERFCOUNTER10_SELECT__PERF_MODE__SHIFT 0x1c
#define SQ_PERFCOUNTER11_SELECT__PERF_SEL_MASK 0x1ff
#define SQ_PERFCOUNTER11_SELECT__PERF_SEL__SHIFT 0x0
#define SQ_PERFCOUNTER11_SELECT__SQC_BANK_MASK_MASK 0xf000
#define SQ_PERFCOUNTER11_SELECT__SQC_BANK_MASK__SHIFT 0xc
#define SQ_PERFCOUNTER11_SELECT__SQC_CLIENT_MASK_MASK 0xf0000
#define SQ_PERFCOUNTER11_SELECT__SQC_CLIENT_MASK__SHIFT 0x10
#define SQ_PERFCOUNTER11_SELECT__SPM_MODE_MASK 0xf00000
#define SQ_PERFCOUNTER11_SELECT__SPM_MODE__SHIFT 0x14
#define SQ_PERFCOUNTER11_SELECT__SIMD_MASK_MASK 0xf000000
#define SQ_PERFCOUNTER11_SELECT__SIMD_MASK__SHIFT 0x18
#define SQ_PERFCOUNTER11_SELECT__PERF_MODE_MASK 0xf0000000
#define SQ_PERFCOUNTER11_SELECT__PERF_MODE__SHIFT 0x1c
#define SQ_PERFCOUNTER12_SELECT__PERF_SEL_MASK 0x1ff
#define SQ_PERFCOUNTER12_SELECT__PERF_SEL__SHIFT 0x0
#define SQ_PERFCOUNTER12_SELECT__SQC_BANK_MASK_MASK 0xf000
#define SQ_PERFCOUNTER12_SELECT__SQC_BANK_MASK__SHIFT 0xc
#define SQ_PERFCOUNTER12_SELECT__SQC_CLIENT_MASK_MASK 0xf0000
#define SQ_PERFCOUNTER12_SELECT__SQC_CLIENT_MASK__SHIFT 0x10
#define SQ_PERFCOUNTER12_SELECT__SPM_MODE_MASK 0xf00000
#define SQ_PERFCOUNTER12_SELECT__SPM_MODE__SHIFT 0x14
#define SQ_PERFCOUNTER12_SELECT__SIMD_MASK_MASK 0xf000000
#define SQ_PERFCOUNTER12_SELECT__SIMD_MASK__SHIFT 0x18
#define SQ_PERFCOUNTER12_SELECT__PERF_MODE_MASK 0xf0000000
#define SQ_PERFCOUNTER12_SELECT__PERF_MODE__SHIFT 0x1c
#define SQ_PERFCOUNTER13_SELECT__PERF_SEL_MASK 0x1ff
#define SQ_PERFCOUNTER13_SELECT__PERF_SEL__SHIFT 0x0
#define SQ_PERFCOUNTER13_SELECT__SQC_BANK_MASK_MASK 0xf000
#define SQ_PERFCOUNTER13_SELECT__SQC_BANK_MASK__SHIFT 0xc
#define SQ_PERFCOUNTER13_SELECT__SQC_CLIENT_MASK_MASK 0xf0000
#define SQ_PERFCOUNTER13_SELECT__SQC_CLIENT_MASK__SHIFT 0x10
#define SQ_PERFCOUNTER13_SELECT__SPM_MODE_MASK 0xf00000
#define SQ_PERFCOUNTER13_SELECT__SPM_MODE__SHIFT 0x14
#define SQ_PERFCOUNTER13_SELECT__SIMD_MASK_MASK 0xf000000
#define SQ_PERFCOUNTER13_SELECT__SIMD_MASK__SHIFT 0x18
#define SQ_PERFCOUNTER13_SELECT__PERF_MODE_MASK 0xf0000000
#define SQ_PERFCOUNTER13_SELECT__PERF_MODE__SHIFT 0x1c
#define SQ_PERFCOUNTER14_SELECT__PERF_SEL_MASK 0x1ff
#define SQ_PERFCOUNTER14_SELECT__PERF_SEL__SHIFT 0x0
#define SQ_PERFCOUNTER14_SELECT__SQC_BANK_MASK_MASK 0xf000
#define SQ_PERFCOUNTER14_SELECT__SQC_BANK_MASK__SHIFT 0xc
#define SQ_PERFCOUNTER14_SELECT__SQC_CLIENT_MASK_MASK 0xf0000
#define SQ_PERFCOUNTER14_SELECT__SQC_CLIENT_MASK__SHIFT 0x10
#define SQ_PERFCOUNTER14_SELECT__SPM_MODE_MASK 0xf00000
#define SQ_PERFCOUNTER14_SELECT__SPM_MODE__SHIFT 0x14
#define SQ_PERFCOUNTER14_SELECT__SIMD_MASK_MASK 0xf000000
#define SQ_PERFCOUNTER14_SELECT__SIMD_MASK__SHIFT 0x18
#define SQ_PERFCOUNTER14_SELECT__PERF_MODE_MASK 0xf0000000
#define SQ_PERFCOUNTER14_SELECT__PERF_MODE__SHIFT 0x1c
#define SQ_PERFCOUNTER15_SELECT__PERF_SEL_MASK 0x1ff
#define SQ_PERFCOUNTER15_SELECT__PERF_SEL__SHIFT 0x0
#define SQ_PERFCOUNTER15_SELECT__SQC_BANK_MASK_MASK 0xf000
#define SQ_PERFCOUNTER15_SELECT__SQC_BANK_MASK__SHIFT 0xc
#define SQ_PERFCOUNTER15_SELECT__SQC_CLIENT_MASK_MASK 0xf0000
#define SQ_PERFCOUNTER15_SELECT__SQC_CLIENT_MASK__SHIFT 0x10
#define SQ_PERFCOUNTER15_SELECT__SPM_MODE_MASK 0xf00000
#define SQ_PERFCOUNTER15_SELECT__SPM_MODE__SHIFT 0x14
#define SQ_PERFCOUNTER15_SELECT__SIMD_MASK_MASK 0xf000000
#define SQ_PERFCOUNTER15_SELECT__SIMD_MASK__SHIFT 0x18
#define SQ_PERFCOUNTER15_SELECT__PERF_MODE_MASK 0xf0000000
#define SQ_PERFCOUNTER15_SELECT__PERF_MODE__SHIFT 0x1c
#define CGTT_SQ_CLK_CTRL__ON_DELAY_MASK 0xf
#define CGTT_SQ_CLK_CTRL__ON_DELAY__SHIFT 0x0
#define CGTT_SQ_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0
#define CGTT_SQ_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
#define CGTT_SQ_CLK_CTRL__PERFMON_OVERRIDE_MASK 0x20000000
#define CGTT_SQ_CLK_CTRL__PERFMON_OVERRIDE__SHIFT 0x1d
#define CGTT_SQ_CLK_CTRL__CORE_OVERRIDE_MASK 0x40000000
#define CGTT_SQ_CLK_CTRL__CORE_OVERRIDE__SHIFT 0x1e
#define CGTT_SQ_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000
#define CGTT_SQ_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f
#define CGTT_SQG_CLK_CTRL__ON_DELAY_MASK 0xf
#define CGTT_SQG_CLK_CTRL__ON_DELAY__SHIFT 0x0
#define CGTT_SQG_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0
#define CGTT_SQG_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
#define CGTT_SQG_CLK_CTRL__TTRACE_OVERRIDE_MASK 0x10000000
#define CGTT_SQG_CLK_CTRL__TTRACE_OVERRIDE__SHIFT 0x1c
#define CGTT_SQG_CLK_CTRL__PERFMON_OVERRIDE_MASK 0x20000000
#define CGTT_SQG_CLK_CTRL__PERFMON_OVERRIDE__SHIFT 0x1d
#define CGTT_SQG_CLK_CTRL__CORE_OVERRIDE_MASK 0x40000000
#define CGTT_SQG_CLK_CTRL__CORE_OVERRIDE__SHIFT 0x1e
#define CGTT_SQG_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000
#define CGTT_SQG_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f
#define SQ_ALU_CLK_CTRL__FORCE_CU_ON_SH0_MASK 0xffff
#define SQ_ALU_CLK_CTRL__FORCE_CU_ON_SH0__SHIFT 0x0
#define SQ_ALU_CLK_CTRL__FORCE_CU_ON_SH1_MASK 0xffff0000
#define SQ_ALU_CLK_CTRL__FORCE_CU_ON_SH1__SHIFT 0x10
#define SQ_TEX_CLK_CTRL__FORCE_CU_ON_SH0_MASK 0xffff
#define SQ_TEX_CLK_CTRL__FORCE_CU_ON_SH0__SHIFT 0x0
#define SQ_TEX_CLK_CTRL__FORCE_CU_ON_SH1_MASK 0xffff0000
#define SQ_TEX_CLK_CTRL__FORCE_CU_ON_SH1__SHIFT 0x10
#define SQ_LDS_CLK_CTRL__FORCE_CU_ON_SH0_MASK 0xffff
#define SQ_LDS_CLK_CTRL__FORCE_CU_ON_SH0__SHIFT 0x0
#define SQ_LDS_CLK_CTRL__FORCE_CU_ON_SH1_MASK 0xffff0000
#define SQ_LDS_CLK_CTRL__FORCE_CU_ON_SH1__SHIFT 0x10
#define SQ_POWER_THROTTLE__MIN_POWER_MASK 0x3fff
#define SQ_POWER_THROTTLE__MIN_POWER__SHIFT 0x0
#define SQ_POWER_THROTTLE__MAX_POWER_MASK 0x3fff0000
#define SQ_POWER_THROTTLE__MAX_POWER__SHIFT 0x10
#define SQ_POWER_THROTTLE__PHASE_OFFSET_MASK 0xc0000000
#define SQ_POWER_THROTTLE__PHASE_OFFSET__SHIFT 0x1e
#define SQ_POWER_THROTTLE2__MAX_POWER_DELTA_MASK 0x3fff
#define SQ_POWER_THROTTLE2__MAX_POWER_DELTA__SHIFT 0x0
#define SQ_POWER_THROTTLE2__SHORT_TERM_INTERVAL_SIZE_MASK 0x3ff0000
#define SQ_POWER_THROTTLE2__SHORT_TERM_INTERVAL_SIZE__SHIFT 0x10
#define SQ_POWER_THROTTLE2__LONG_TERM_INTERVAL_RATIO_MASK 0x78000000
#define SQ_POWER_THROTTLE2__LONG_TERM_INTERVAL_RATIO__SHIFT 0x1b
#define SQ_POWER_THROTTLE2__USE_REF_CLOCK_MASK 0x80000000
#define SQ_POWER_THROTTLE2__USE_REF_CLOCK__SHIFT 0x1f
#define SQ_TIME_HI__TIME_MASK 0xffffffff
#define SQ_TIME_HI__TIME__SHIFT 0x0
#define SQ_TIME_LO__TIME_MASK 0xffffffff
#define SQ_TIME_LO__TIME__SHIFT 0x0
#define SQ_THREAD_TRACE_BASE__ADDR_MASK 0xffffffff
#define SQ_THREAD_TRACE_BASE__ADDR__SHIFT 0x0
#define SQ_THREAD_TRACE_BASE2__ADDR_HI_MASK 0xf
#define SQ_THREAD_TRACE_BASE2__ADDR_HI__SHIFT 0x0
#define SQ_THREAD_TRACE_SIZE__SIZE_MASK 0x3fffff
#define SQ_THREAD_TRACE_SIZE__SIZE__SHIFT 0x0
#define SQ_THREAD_TRACE_MASK__CU_SEL_MASK 0x1f
#define SQ_THREAD_TRACE_MASK__CU_SEL__SHIFT 0x0
#define SQ_THREAD_TRACE_MASK__SH_SEL_MASK 0x20
#define SQ_THREAD_TRACE_MASK__SH_SEL__SHIFT 0x5
#define SQ_THREAD_TRACE_MASK__REG_STALL_EN_MASK 0x80
#define SQ_THREAD_TRACE_MASK__REG_STALL_EN__SHIFT 0x7
#define SQ_THREAD_TRACE_MASK__SIMD_EN_MASK 0xf00
#define SQ_THREAD_TRACE_MASK__SIMD_EN__SHIFT 0x8
#define SQ_THREAD_TRACE_MASK__VM_ID_MASK_MASK 0x3000
#define SQ_THREAD_TRACE_MASK__VM_ID_MASK__SHIFT 0xc
#define SQ_THREAD_TRACE_MASK__SPI_STALL_EN_MASK 0x4000
#define SQ_THREAD_TRACE_MASK__SPI_STALL_EN__SHIFT 0xe
#define SQ_THREAD_TRACE_MASK__SQ_STALL_EN_MASK 0x8000
#define SQ_THREAD_TRACE_MASK__SQ_STALL_EN__SHIFT 0xf
#define SQ_THREAD_TRACE_USERDATA_0__DATA_MASK 0xffffffff
#define SQ_THREAD_TRACE_USERDATA_0__DATA__SHIFT 0x0
#define SQ_THREAD_TRACE_USERDATA_1__DATA_MASK 0xffffffff
#define SQ_THREAD_TRACE_USERDATA_1__DATA__SHIFT 0x0
#define SQ_THREAD_TRACE_USERDATA_2__DATA_MASK 0xffffffff
#define SQ_THREAD_TRACE_USERDATA_2__DATA__SHIFT 0x0
#define SQ_THREAD_TRACE_USERDATA_3__DATA_MASK 0xffffffff
#define SQ_THREAD_TRACE_USERDATA_3__DATA__SHIFT 0x0
#define SQ_THREAD_TRACE_MODE__MASK_PS_MASK 0x7
#define SQ_THREAD_TRACE_MODE__MASK_PS__SHIFT 0x0
#define SQ_THREAD_TRACE_MODE__MASK_VS_MASK 0x38
#define SQ_THREAD_TRACE_MODE__MASK_VS__SHIFT 0x3
#define SQ_THREAD_TRACE_MODE__MASK_GS_MASK 0x1c0
#define SQ_THREAD_TRACE_MODE__MASK_GS__SHIFT 0x6
#define SQ_THREAD_TRACE_MODE__MASK_ES_MASK 0xe00
#define SQ_THREAD_TRACE_MODE__MASK_ES__SHIFT 0x9
#define SQ_THREAD_TRACE_MODE__MASK_HS_MASK 0x7000
#define SQ_THREAD_TRACE_MODE__MASK_HS__SHIFT 0xc
#define SQ_THREAD_TRACE_MODE__MASK_LS_MASK 0x38000
#define SQ_THREAD_TRACE_MODE__MASK_LS__SHIFT 0xf
#define SQ_THREAD_TRACE_MODE__MASK_CS_MASK 0x1c0000
#define SQ_THREAD_TRACE_MODE__MASK_CS__SHIFT 0x12
#define SQ_THREAD_TRACE_MODE__MODE_MASK 0x600000
#define SQ_THREAD_TRACE_MODE__MODE__SHIFT 0x15
#define SQ_THREAD_TRACE_MODE__CAPTURE_MODE_MASK 0x1800000
#define SQ_THREAD_TRACE_MODE__CAPTURE_MODE__SHIFT 0x17
#define SQ_THREAD_TRACE_MODE__AUTOFLUSH_EN_MASK 0x2000000
#define SQ_THREAD_TRACE_MODE__AUTOFLUSH_EN__SHIFT 0x19
#define SQ_THREAD_TRACE_MODE__PRIV_MASK 0x4000000
#define SQ_THREAD_TRACE_MODE__PRIV__SHIFT 0x1a
#define SQ_THREAD_TRACE_MODE__ISSUE_MASK_MASK 0x18000000
#define SQ_THREAD_TRACE_MODE__ISSUE_MASK__SHIFT 0x1b
#define SQ_THREAD_TRACE_MODE__TEST_MODE_MASK 0x20000000
#define SQ_THREAD_TRACE_MODE__TEST_MODE__SHIFT 0x1d
#define SQ_THREAD_TRACE_MODE__INTERRUPT_EN_MASK 0x40000000
#define SQ_THREAD_TRACE_MODE__INTERRUPT_EN__SHIFT 0x1e
#define SQ_THREAD_TRACE_MODE__WRAP_MASK 0x80000000
#define SQ_THREAD_TRACE_MODE__WRAP__SHIFT 0x1f
#define SQ_THREAD_TRACE_CTRL__RESET_BUFFER_MASK 0x80000000
#define SQ_THREAD_TRACE_CTRL__RESET_BUFFER__SHIFT 0x1f
#define SQ_THREAD_TRACE_TOKEN_MASK__TOKEN_MASK_MASK 0xffff
#define SQ_THREAD_TRACE_TOKEN_MASK__TOKEN_MASK__SHIFT 0x0
#define SQ_THREAD_TRACE_TOKEN_MASK__REG_MASK_MASK 0xff0000
#define SQ_THREAD_TRACE_TOKEN_MASK__REG_MASK__SHIFT 0x10
#define SQ_THREAD_TRACE_TOKEN_MASK__REG_DROP_ON_STALL_MASK 0x1000000
#define SQ_THREAD_TRACE_TOKEN_MASK__REG_DROP_ON_STALL__SHIFT 0x18
#define SQ_THREAD_TRACE_TOKEN_MASK2__INST_MASK_MASK 0xffffffff
#define SQ_THREAD_TRACE_TOKEN_MASK2__INST_MASK__SHIFT 0x0
#define SQ_THREAD_TRACE_PERF_MASK__SH0_MASK_MASK 0xffff
#define SQ_THREAD_TRACE_PERF_MASK__SH0_MASK__SHIFT 0x0
#define SQ_THREAD_TRACE_PERF_MASK__SH1_MASK_MASK 0xffff0000
#define SQ_THREAD_TRACE_PERF_MASK__SH1_MASK__SHIFT 0x10
#define SQ_THREAD_TRACE_WPTR__WPTR_MASK 0x3fffffff
#define SQ_THREAD_TRACE_WPTR__WPTR__SHIFT 0x0
#define SQ_THREAD_TRACE_WPTR__READ_OFFSET_MASK 0xc0000000
#define SQ_THREAD_TRACE_WPTR__READ_OFFSET__SHIFT 0x1e
#define SQ_THREAD_TRACE_STATUS__FINISH_PENDING_MASK 0x3ff
#define SQ_THREAD_TRACE_STATUS__FINISH_PENDING__SHIFT 0x0
#define SQ_THREAD_TRACE_STATUS__FINISH_DONE_MASK 0x3ff0000
#define SQ_THREAD_TRACE_STATUS__FINISH_DONE__SHIFT 0x10
#define SQ_THREAD_TRACE_STATUS__NEW_BUF_MASK 0x20000000
#define SQ_THREAD_TRACE_STATUS__NEW_BUF__SHIFT 0x1d
#define SQ_THREAD_TRACE_STATUS__BUSY_MASK 0x40000000
#define SQ_THREAD_TRACE_STATUS__BUSY__SHIFT 0x1e
#define SQ_THREAD_TRACE_STATUS__FULL_MASK 0x80000000
#define SQ_THREAD_TRACE_STATUS__FULL__SHIFT 0x1f
#define SQ_THREAD_TRACE_CNTR__CNTR_MASK 0xffffffff
#define SQ_THREAD_TRACE_CNTR__CNTR__SHIFT 0x0
#define SQ_THREAD_TRACE_HIWATER__HIWATER_MASK 0x7
#define SQ_THREAD_TRACE_HIWATER__HIWATER__SHIFT 0x0
#define SQ_LB_CTR_CTRL__START_MASK 0x1
#define SQ_LB_CTR_CTRL__START__SHIFT 0x0
#define SQ_LB_CTR_CTRL__LOAD_MASK 0x2
#define SQ_LB_CTR_CTRL__LOAD__SHIFT 0x1
#define SQ_LB_CTR_CTRL__CLEAR_MASK 0x4
#define SQ_LB_CTR_CTRL__CLEAR__SHIFT 0x2
#define SQ_LB_DATA_ALU_CYCLES__DATA_MASK 0xffffffff
#define SQ_LB_DATA_ALU_CYCLES__DATA__SHIFT 0x0
#define SQ_LB_DATA_TEX_CYCLES__DATA_MASK 0xffffffff
#define SQ_LB_DATA_TEX_CYCLES__DATA__SHIFT 0x0
#define SQ_LB_DATA_ALU_STALLS__DATA_MASK 0xffffffff
#define SQ_LB_DATA_ALU_STALLS__DATA__SHIFT 0x0
#define SQ_LB_DATA_TEX_STALLS__DATA_MASK 0xffffffff
#define SQ_LB_DATA_TEX_STALLS__DATA__SHIFT 0x0
#define SQC_EDC_CNT__INST_SEC_MASK 0xff
#define SQC_EDC_CNT__INST_SEC__SHIFT 0x0
#define SQC_EDC_CNT__INST_DED_MASK 0xff00
#define SQC_EDC_CNT__INST_DED__SHIFT 0x8
#define SQC_EDC_CNT__DATA_SEC_MASK 0xff0000
#define SQC_EDC_CNT__DATA_SEC__SHIFT 0x10
#define SQC_EDC_CNT__DATA_DED_MASK 0xff000000
#define SQC_EDC_CNT__DATA_DED__SHIFT 0x18
#define SQ_EDC_SEC_CNT__LDS_SEC_MASK 0xff
#define SQ_EDC_SEC_CNT__LDS_SEC__SHIFT 0x0
#define SQ_EDC_SEC_CNT__SGPR_SEC_MASK 0xff00
#define SQ_EDC_SEC_CNT__SGPR_SEC__SHIFT 0x8
#define SQ_EDC_SEC_CNT__VGPR_SEC_MASK 0xff0000
#define SQ_EDC_SEC_CNT__VGPR_SEC__SHIFT 0x10
#define SQ_EDC_DED_CNT__LDS_DED_MASK 0xff
#define SQ_EDC_DED_CNT__LDS_DED__SHIFT 0x0
#define SQ_EDC_DED_CNT__SGPR_DED_MASK 0xff00
#define SQ_EDC_DED_CNT__SGPR_DED__SHIFT 0x8
#define SQ_EDC_DED_CNT__VGPR_DED_MASK 0xff0000
#define SQ_EDC_DED_CNT__VGPR_DED__SHIFT 0x10
#define SQ_EDC_INFO__WAVE_ID_MASK 0xf
#define SQ_EDC_INFO__WAVE_ID__SHIFT 0x0
#define SQ_EDC_INFO__SIMD_ID_MASK 0x30
#define SQ_EDC_INFO__SIMD_ID__SHIFT 0x4
#define SQ_EDC_INFO__SOURCE_MASK 0x1c0
#define SQ_EDC_INFO__SOURCE__SHIFT 0x6
#define SQ_EDC_INFO__VM_ID_MASK 0x1e00
#define SQ_EDC_INFO__VM_ID__SHIFT 0x9
#define SQ_BUF_RSRC_WORD0__BASE_ADDRESS_MASK 0xffffffff
#define SQ_BUF_RSRC_WORD0__BASE_ADDRESS__SHIFT 0x0
#define SQ_BUF_RSRC_WORD1__BASE_ADDRESS_HI_MASK 0xffff
#define SQ_BUF_RSRC_WORD1__BASE_ADDRESS_HI__SHIFT 0x0
#define SQ_BUF_RSRC_WORD1__STRIDE_MASK 0x3fff0000
#define SQ_BUF_RSRC_WORD1__STRIDE__SHIFT 0x10
#define SQ_BUF_RSRC_WORD1__CACHE_SWIZZLE_MASK 0x40000000
#define SQ_BUF_RSRC_WORD1__CACHE_SWIZZLE__SHIFT 0x1e
#define SQ_BUF_RSRC_WORD1__SWIZZLE_ENABLE_MASK 0x80000000
#define SQ_BUF_RSRC_WORD1__SWIZZLE_ENABLE__SHIFT 0x1f
#define SQ_BUF_RSRC_WORD2__NUM_RECORDS_MASK 0xffffffff
#define SQ_BUF_RSRC_WORD2__NUM_RECORDS__SHIFT 0x0
#define SQ_BUF_RSRC_WORD3__DST_SEL_X_MASK 0x7
#define SQ_BUF_RSRC_WORD3__DST_SEL_X__SHIFT 0x0
#define SQ_BUF_RSRC_WORD3__DST_SEL_Y_MASK 0x38
#define SQ_BUF_RSRC_WORD3__DST_SEL_Y__SHIFT 0x3
#define SQ_BUF_RSRC_WORD3__DST_SEL_Z_MASK 0x1c0
#define SQ_BUF_RSRC_WORD3__DST_SEL_Z__SHIFT 0x6
#define SQ_BUF_RSRC_WORD3__DST_SEL_W_MASK 0xe00
#define SQ_BUF_RSRC_WORD3__DST_SEL_W__SHIFT 0x9
#define SQ_BUF_RSRC_WORD3__NUM_FORMAT_MASK 0x7000
#define SQ_BUF_RSRC_WORD3__NUM_FORMAT__SHIFT 0xc
#define SQ_BUF_RSRC_WORD3__DATA_FORMAT_MASK 0x78000
#define SQ_BUF_RSRC_WORD3__DATA_FORMAT__SHIFT 0xf
#define SQ_BUF_RSRC_WORD3__ELEMENT_SIZE_MASK 0x180000
#define SQ_BUF_RSRC_WORD3__ELEMENT_SIZE__SHIFT 0x13
#define SQ_BUF_RSRC_WORD3__INDEX_STRIDE_MASK 0x600000
#define SQ_BUF_RSRC_WORD3__INDEX_STRIDE__SHIFT 0x15
#define SQ_BUF_RSRC_WORD3__ADD_TID_ENABLE_MASK 0x800000
#define SQ_BUF_RSRC_WORD3__ADD_TID_ENABLE__SHIFT 0x17
#define SQ_BUF_RSRC_WORD3__ATC_MASK 0x1000000
#define SQ_BUF_RSRC_WORD3__ATC__SHIFT 0x18
#define SQ_BUF_RSRC_WORD3__HASH_ENABLE_MASK 0x2000000
#define SQ_BUF_RSRC_WORD3__HASH_ENABLE__SHIFT 0x19
#define SQ_BUF_RSRC_WORD3__HEAP_MASK 0x4000000
#define SQ_BUF_RSRC_WORD3__HEAP__SHIFT 0x1a
#define SQ_BUF_RSRC_WORD3__MTYPE_MASK 0x38000000
#define SQ_BUF_RSRC_WORD3__MTYPE__SHIFT 0x1b
#define SQ_BUF_RSRC_WORD3__TYPE_MASK 0xc0000000
#define SQ_BUF_RSRC_WORD3__TYPE__SHIFT 0x1e
#define SQ_IMG_RSRC_WORD0__BASE_ADDRESS_MASK 0xffffffff
#define SQ_IMG_RSRC_WORD0__BASE_ADDRESS__SHIFT 0x0
#define SQ_IMG_RSRC_WORD1__BASE_ADDRESS_HI_MASK 0xff
#define SQ_IMG_RSRC_WORD1__BASE_ADDRESS_HI__SHIFT 0x0
#define SQ_IMG_RSRC_WORD1__MIN_LOD_MASK 0xfff00
#define SQ_IMG_RSRC_WORD1__MIN_LOD__SHIFT 0x8
#define SQ_IMG_RSRC_WORD1__DATA_FORMAT_MASK 0x3f00000
#define SQ_IMG_RSRC_WORD1__DATA_FORMAT__SHIFT 0x14
#define SQ_IMG_RSRC_WORD1__NUM_FORMAT_MASK 0x3c000000
#define SQ_IMG_RSRC_WORD1__NUM_FORMAT__SHIFT 0x1a
#define SQ_IMG_RSRC_WORD1__MTYPE_MASK 0xc0000000
#define SQ_IMG_RSRC_WORD1__MTYPE__SHIFT 0x1e
#define SQ_IMG_RSRC_WORD2__WIDTH_MASK 0x3fff
#define SQ_IMG_RSRC_WORD2__WIDTH__SHIFT 0x0
#define SQ_IMG_RSRC_WORD2__HEIGHT_MASK 0xfffc000
#define SQ_IMG_RSRC_WORD2__HEIGHT__SHIFT 0xe
#define SQ_IMG_RSRC_WORD2__PERF_MOD_MASK 0x70000000
#define SQ_IMG_RSRC_WORD2__PERF_MOD__SHIFT 0x1c
#define SQ_IMG_RSRC_WORD2__INTERLACED_MASK 0x80000000
#define SQ_IMG_RSRC_WORD2__INTERLACED__SHIFT 0x1f
#define SQ_IMG_RSRC_WORD3__DST_SEL_X_MASK 0x7
#define SQ_IMG_RSRC_WORD3__DST_SEL_X__SHIFT 0x0
#define SQ_IMG_RSRC_WORD3__DST_SEL_Y_MASK 0x38
#define SQ_IMG_RSRC_WORD3__DST_SEL_Y__SHIFT 0x3
#define SQ_IMG_RSRC_WORD3__DST_SEL_Z_MASK 0x1c0
#define SQ_IMG_RSRC_WORD3__DST_SEL_Z__SHIFT 0x6
#define SQ_IMG_RSRC_WORD3__DST_SEL_W_MASK 0xe00
#define SQ_IMG_RSRC_WORD3__DST_SEL_W__SHIFT 0x9
#define SQ_IMG_RSRC_WORD3__BASE_LEVEL_MASK 0xf000
#define SQ_IMG_RSRC_WORD3__BASE_LEVEL__SHIFT 0xc
#define SQ_IMG_RSRC_WORD3__LAST_LEVEL_MASK 0xf0000
#define SQ_IMG_RSRC_WORD3__LAST_LEVEL__SHIFT 0x10
#define SQ_IMG_RSRC_WORD3__TILING_INDEX_MASK 0x1f00000
#define SQ_IMG_RSRC_WORD3__TILING_INDEX__SHIFT 0x14
#define SQ_IMG_RSRC_WORD3__POW2_PAD_MASK 0x2000000
#define SQ_IMG_RSRC_WORD3__POW2_PAD__SHIFT 0x19
#define SQ_IMG_RSRC_WORD3__MTYPE_MASK 0x4000000
#define SQ_IMG_RSRC_WORD3__MTYPE__SHIFT 0x1a
#define SQ_IMG_RSRC_WORD3__ATC_MASK 0x8000000
#define SQ_IMG_RSRC_WORD3__ATC__SHIFT 0x1b
#define SQ_IMG_RSRC_WORD3__TYPE_MASK 0xf0000000
#define SQ_IMG_RSRC_WORD3__TYPE__SHIFT 0x1c
#define SQ_IMG_RSRC_WORD4__DEPTH_MASK 0x1fff
#define SQ_IMG_RSRC_WORD4__DEPTH__SHIFT 0x0
#define SQ_IMG_RSRC_WORD4__PITCH_MASK 0x7ffe000
#define SQ_IMG_RSRC_WORD4__PITCH__SHIFT 0xd
#define SQ_IMG_RSRC_WORD5__BASE_ARRAY_MASK 0x1fff
#define SQ_IMG_RSRC_WORD5__BASE_ARRAY__SHIFT 0x0
#define SQ_IMG_RSRC_WORD5__LAST_ARRAY_MASK 0x3ffe000
#define SQ_IMG_RSRC_WORD5__LAST_ARRAY__SHIFT 0xd
#define SQ_IMG_RSRC_WORD6__MIN_LOD_WARN_MASK 0xfff
#define SQ_IMG_RSRC_WORD6__MIN_LOD_WARN__SHIFT 0x0
#define SQ_IMG_RSRC_WORD6__COUNTER_BANK_ID_MASK 0xff000
#define SQ_IMG_RSRC_WORD6__COUNTER_BANK_ID__SHIFT 0xc
#define SQ_IMG_RSRC_WORD6__LOD_HDW_CNT_EN_MASK 0x100000
#define SQ_IMG_RSRC_WORD6__LOD_HDW_CNT_EN__SHIFT 0x14
#define SQ_IMG_RSRC_WORD6__COMPRESSION_EN_MASK 0x200000
#define SQ_IMG_RSRC_WORD6__COMPRESSION_EN__SHIFT 0x15
#define SQ_IMG_RSRC_WORD6__ALPHA_IS_ON_MSB_MASK 0x400000
#define SQ_IMG_RSRC_WORD6__ALPHA_IS_ON_MSB__SHIFT 0x16
#define SQ_IMG_RSRC_WORD6__COLOR_TRANSFORM_MASK 0x800000
#define SQ_IMG_RSRC_WORD6__COLOR_TRANSFORM__SHIFT 0x17
#define SQ_IMG_RSRC_WORD6__LOST_ALPHA_BITS_MASK 0xf000000
#define SQ_IMG_RSRC_WORD6__LOST_ALPHA_BITS__SHIFT 0x18
#define SQ_IMG_RSRC_WORD6__LOST_COLOR_BITS_MASK 0xf0000000
#define SQ_IMG_RSRC_WORD6__LOST_COLOR_BITS__SHIFT 0x1c
#define SQ_IMG_RSRC_WORD7__META_DATA_ADDRESS_MASK 0xffffffff
#define SQ_IMG_RSRC_WORD7__META_DATA_ADDRESS__SHIFT 0x0
#define SQ_IMG_SAMP_WORD0__CLAMP_X_MASK 0x7
#define SQ_IMG_SAMP_WORD0__CLAMP_X__SHIFT 0x0
#define SQ_IMG_SAMP_WORD0__CLAMP_Y_MASK 0x38
#define SQ_IMG_SAMP_WORD0__CLAMP_Y__SHIFT 0x3
#define SQ_IMG_SAMP_WORD0__CLAMP_Z_MASK 0x1c0
#define SQ_IMG_SAMP_WORD0__CLAMP_Z__SHIFT 0x6
#define SQ_IMG_SAMP_WORD0__MAX_ANISO_RATIO_MASK 0xe00
#define SQ_IMG_SAMP_WORD0__MAX_ANISO_RATIO__SHIFT 0x9
#define SQ_IMG_SAMP_WORD0__DEPTH_COMPARE_FUNC_MASK 0x7000
#define SQ_IMG_SAMP_WORD0__DEPTH_COMPARE_FUNC__SHIFT 0xc
#define SQ_IMG_SAMP_WORD0__FORCE_UNNORMALIZED_MASK 0x8000
#define SQ_IMG_SAMP_WORD0__FORCE_UNNORMALIZED__SHIFT 0xf
#define SQ_IMG_SAMP_WORD0__ANISO_THRESHOLD_MASK 0x70000
#define SQ_IMG_SAMP_WORD0__ANISO_THRESHOLD__SHIFT 0x10
#define SQ_IMG_SAMP_WORD0__MC_COORD_TRUNC_MASK 0x80000
#define SQ_IMG_SAMP_WORD0__MC_COORD_TRUNC__SHIFT 0x13
#define SQ_IMG_SAMP_WORD0__FORCE_DEGAMMA_MASK 0x100000
#define SQ_IMG_SAMP_WORD0__FORCE_DEGAMMA__SHIFT 0x14
#define SQ_IMG_SAMP_WORD0__ANISO_BIAS_MASK 0x7e00000
#define SQ_IMG_SAMP_WORD0__ANISO_BIAS__SHIFT 0x15
#define SQ_IMG_SAMP_WORD0__TRUNC_COORD_MASK 0x8000000
#define SQ_IMG_SAMP_WORD0__TRUNC_COORD__SHIFT 0x1b
#define SQ_IMG_SAMP_WORD0__DISABLE_CUBE_WRAP_MASK 0x10000000
#define SQ_IMG_SAMP_WORD0__DISABLE_CUBE_WRAP__SHIFT 0x1c
#define SQ_IMG_SAMP_WORD0__FILTER_MODE_MASK 0x60000000
#define SQ_IMG_SAMP_WORD0__FILTER_MODE__SHIFT 0x1d
#define SQ_IMG_SAMP_WORD0__COMPAT_MODE_MASK 0x80000000
#define SQ_IMG_SAMP_WORD0__COMPAT_MODE__SHIFT 0x1f
#define SQ_IMG_SAMP_WORD1__MIN_LOD_MASK 0xfff
#define SQ_IMG_SAMP_WORD1__MIN_LOD__SHIFT 0x0
#define SQ_IMG_SAMP_WORD1__MAX_LOD_MASK 0xfff000
#define SQ_IMG_SAMP_WORD1__MAX_LOD__SHIFT 0xc
#define SQ_IMG_SAMP_WORD1__PERF_MIP_MASK 0xf000000
#define SQ_IMG_SAMP_WORD1__PERF_MIP__SHIFT 0x18
#define SQ_IMG_SAMP_WORD1__PERF_Z_MASK 0xf0000000
#define SQ_IMG_SAMP_WORD1__PERF_Z__SHIFT 0x1c
#define SQ_IMG_SAMP_WORD2__LOD_BIAS_MASK 0x3fff
#define SQ_IMG_SAMP_WORD2__LOD_BIAS__SHIFT 0x0
#define SQ_IMG_SAMP_WORD2__LOD_BIAS_SEC_MASK 0xfc000
#define SQ_IMG_SAMP_WORD2__LOD_BIAS_SEC__SHIFT 0xe
#define SQ_IMG_SAMP_WORD2__XY_MAG_FILTER_MASK 0x300000
#define SQ_IMG_SAMP_WORD2__XY_MAG_FILTER__SHIFT 0x14
#define SQ_IMG_SAMP_WORD2__XY_MIN_FILTER_MASK 0xc00000
#define SQ_IMG_SAMP_WORD2__XY_MIN_FILTER__SHIFT 0x16
#define SQ_IMG_SAMP_WORD2__Z_FILTER_MASK 0x3000000
#define SQ_IMG_SAMP_WORD2__Z_FILTER__SHIFT 0x18
#define SQ_IMG_SAMP_WORD2__MIP_FILTER_MASK 0xc000000
#define SQ_IMG_SAMP_WORD2__MIP_FILTER__SHIFT 0x1a
#define SQ_IMG_SAMP_WORD2__MIP_POINT_PRECLAMP_MASK 0x10000000
#define SQ_IMG_SAMP_WORD2__MIP_POINT_PRECLAMP__SHIFT 0x1c
#define SQ_IMG_SAMP_WORD2__DISABLE_LSB_CEIL_MASK 0x20000000
#define SQ_IMG_SAMP_WORD2__DISABLE_LSB_CEIL__SHIFT 0x1d
#define SQ_IMG_SAMP_WORD2__FILTER_PREC_FIX_MASK 0x40000000
#define SQ_IMG_SAMP_WORD2__FILTER_PREC_FIX__SHIFT 0x1e
#define SQ_IMG_SAMP_WORD2__ANISO_OVERRIDE_MASK 0x80000000
#define SQ_IMG_SAMP_WORD2__ANISO_OVERRIDE__SHIFT 0x1f
#define SQ_IMG_SAMP_WORD3__BORDER_COLOR_PTR_MASK 0xfff
#define SQ_IMG_SAMP_WORD3__BORDER_COLOR_PTR__SHIFT 0x0
#define SQ_IMG_SAMP_WORD3__BORDER_COLOR_TYPE_MASK 0xc0000000
#define SQ_IMG_SAMP_WORD3__BORDER_COLOR_TYPE__SHIFT 0x1e
#define SQ_FLAT_SCRATCH_WORD0__SIZE_MASK 0x7ffff
#define SQ_FLAT_SCRATCH_WORD0__SIZE__SHIFT 0x0
#define SQ_FLAT_SCRATCH_WORD1__OFFSET_MASK 0xffffff
#define SQ_FLAT_SCRATCH_WORD1__OFFSET__SHIFT 0x0
#define SQ_M0_GPR_IDX_WORD__INDEX_MASK 0xff
#define SQ_M0_GPR_IDX_WORD__INDEX__SHIFT 0x0
#define SQ_M0_GPR_IDX_WORD__VSRC0_REL_MASK 0x1000
#define SQ_M0_GPR_IDX_WORD__VSRC0_REL__SHIFT 0xc
#define SQ_M0_GPR_IDX_WORD__VSRC1_REL_MASK 0x2000
#define SQ_M0_GPR_IDX_WORD__VSRC1_REL__SHIFT 0xd
#define SQ_M0_GPR_IDX_WORD__VSRC2_REL_MASK 0x4000
#define SQ_M0_GPR_IDX_WORD__VSRC2_REL__SHIFT 0xe
#define SQ_M0_GPR_IDX_WORD__VDST_REL_MASK 0x8000
#define SQ_M0_GPR_IDX_WORD__VDST_REL__SHIFT 0xf
#define SQ_IND_INDEX__WAVE_ID_MASK 0xf
#define SQ_IND_INDEX__WAVE_ID__SHIFT 0x0
#define SQ_IND_INDEX__SIMD_ID_MASK 0x30
#define SQ_IND_INDEX__SIMD_ID__SHIFT 0x4
#define SQ_IND_INDEX__THREAD_ID_MASK 0xfc0
#define SQ_IND_INDEX__THREAD_ID__SHIFT 0x6
#define SQ_IND_INDEX__AUTO_INCR_MASK 0x1000
#define SQ_IND_INDEX__AUTO_INCR__SHIFT 0xc
#define SQ_IND_INDEX__FORCE_READ_MASK 0x2000
#define SQ_IND_INDEX__FORCE_READ__SHIFT 0xd
#define SQ_IND_INDEX__READ_TIMEOUT_MASK 0x4000
#define SQ_IND_INDEX__READ_TIMEOUT__SHIFT 0xe
#define SQ_IND_INDEX__UNINDEXED_MASK 0x8000
#define SQ_IND_INDEX__UNINDEXED__SHIFT 0xf
#define SQ_IND_INDEX__INDEX_MASK 0xffff0000
#define SQ_IND_INDEX__INDEX__SHIFT 0x10
#define SQ_CMD__CMD_MASK 0x7
#define SQ_CMD__CMD__SHIFT 0x0
#define SQ_CMD__MODE_MASK 0x70
#define SQ_CMD__MODE__SHIFT 0x4
#define SQ_CMD__CHECK_VMID_MASK 0x80
#define SQ_CMD__CHECK_VMID__SHIFT 0x7
#define SQ_CMD__DATA_MASK 0x700
#define SQ_CMD__DATA__SHIFT 0x8
#define SQ_CMD__WAVE_ID_MASK 0xf0000
#define SQ_CMD__WAVE_ID__SHIFT 0x10
#define SQ_CMD__SIMD_ID_MASK 0x300000
#define SQ_CMD__SIMD_ID__SHIFT 0x14
#define SQ_CMD__QUEUE_ID_MASK 0x7000000
#define SQ_CMD__QUEUE_ID__SHIFT 0x18
#define SQ_CMD__VM_ID_MASK 0xf0000000
#define SQ_CMD__VM_ID__SHIFT 0x1c
#define SQ_IND_DATA__DATA_MASK 0xffffffff
#define SQ_IND_DATA__DATA__SHIFT 0x0
#define SQ_REG_TIMESTAMP__TIMESTAMP_MASK 0xff
#define SQ_REG_TIMESTAMP__TIMESTAMP__SHIFT 0x0
#define SQ_CMD_TIMESTAMP__TIMESTAMP_MASK 0xff
#define SQ_CMD_TIMESTAMP__TIMESTAMP__SHIFT 0x0
#define SQ_HV_VMID_CTRL__DEFAULT_VMID_MASK 0xf
#define SQ_HV_VMID_CTRL__DEFAULT_VMID__SHIFT 0x0
#define SQ_HV_VMID_CTRL__ALLOWED_VMID_MASK_MASK 0xffff0
#define SQ_HV_VMID_CTRL__ALLOWED_VMID_MASK__SHIFT 0x4
#define SQ_WAVE_INST_DW0__INST_DW0_MASK 0xffffffff
#define SQ_WAVE_INST_DW0__INST_DW0__SHIFT 0x0
#define SQ_WAVE_INST_DW1__INST_DW1_MASK 0xffffffff
#define SQ_WAVE_INST_DW1__INST_DW1__SHIFT 0x0
#define SQ_WAVE_PC_LO__PC_LO_MASK 0xffffffff
#define SQ_WAVE_PC_LO__PC_LO__SHIFT 0x0
#define SQ_WAVE_PC_HI__PC_HI_MASK 0xff
#define SQ_WAVE_PC_HI__PC_HI__SHIFT 0x0
#define SQ_WAVE_IB_DBG0__IBUF_ST_MASK 0x7
#define SQ_WAVE_IB_DBG0__IBUF_ST__SHIFT 0x0
#define SQ_WAVE_IB_DBG0__PC_INVALID_MASK 0x8
#define SQ_WAVE_IB_DBG0__PC_INVALID__SHIFT 0x3
#define SQ_WAVE_IB_DBG0__NEED_NEXT_DW_MASK 0x10
#define SQ_WAVE_IB_DBG0__NEED_NEXT_DW__SHIFT 0x4
#define SQ_WAVE_IB_DBG0__NO_PREFETCH_CNT_MASK 0xe0
#define SQ_WAVE_IB_DBG0__NO_PREFETCH_CNT__SHIFT 0x5
#define SQ_WAVE_IB_DBG0__IBUF_RPTR_MASK 0x300
#define SQ_WAVE_IB_DBG0__IBUF_RPTR__SHIFT 0x8
#define SQ_WAVE_IB_DBG0__IBUF_WPTR_MASK 0xc00
#define SQ_WAVE_IB_DBG0__IBUF_WPTR__SHIFT 0xa
#define SQ_WAVE_IB_DBG0__INST_STR_ST_MASK 0xf0000
#define SQ_WAVE_IB_DBG0__INST_STR_ST__SHIFT 0x10
#define SQ_WAVE_IB_DBG0__MISC_CNT_MASK 0xf00000
#define SQ_WAVE_IB_DBG0__MISC_CNT__SHIFT 0x14
#define SQ_WAVE_IB_DBG0__ECC_ST_MASK 0x3000000
#define SQ_WAVE_IB_DBG0__ECC_ST__SHIFT 0x18
#define SQ_WAVE_IB_DBG0__IS_HYB_MASK 0x4000000
#define SQ_WAVE_IB_DBG0__IS_HYB__SHIFT 0x1a
#define SQ_WAVE_IB_DBG0__HYB_CNT_MASK 0x18000000
#define SQ_WAVE_IB_DBG0__HYB_CNT__SHIFT 0x1b
#define SQ_WAVE_IB_DBG0__KILL_MASK 0x20000000
#define SQ_WAVE_IB_DBG0__KILL__SHIFT 0x1d
#define SQ_WAVE_IB_DBG0__NEED_KILL_IFETCH_MASK 0x40000000
#define SQ_WAVE_IB_DBG0__NEED_KILL_IFETCH__SHIFT 0x1e
#define SQ_WAVE_IB_DBG1__IXNACK_MASK 0x1
#define SQ_WAVE_IB_DBG1__IXNACK__SHIFT 0x0
#define SQ_WAVE_IB_DBG1__XNACK_MASK 0x2
#define SQ_WAVE_IB_DBG1__XNACK__SHIFT 0x1
#define SQ_WAVE_IB_DBG1__TA_NEED_RESET_MASK 0x4
#define SQ_WAVE_IB_DBG1__TA_NEED_RESET__SHIFT 0x2
#define SQ_WAVE_IB_DBG1__XCNT_MASK 0xf0
#define SQ_WAVE_IB_DBG1__XCNT__SHIFT 0x4
#define SQ_WAVE_IB_DBG1__QCNT_MASK 0xf00
#define SQ_WAVE_IB_DBG1__QCNT__SHIFT 0x8
#define SQ_WAVE_EXEC_LO__EXEC_LO_MASK 0xffffffff
#define SQ_WAVE_EXEC_LO__EXEC_LO__SHIFT 0x0
#define SQ_WAVE_EXEC_HI__EXEC_HI_MASK 0xffffffff
#define SQ_WAVE_EXEC_HI__EXEC_HI__SHIFT 0x0
#define SQ_WAVE_STATUS__SCC_MASK 0x1
#define SQ_WAVE_STATUS__SCC__SHIFT 0x0
#define SQ_WAVE_STATUS__SPI_PRIO_MASK 0x6
#define SQ_WAVE_STATUS__SPI_PRIO__SHIFT 0x1
#define SQ_WAVE_STATUS__USER_PRIO_MASK 0x18
#define SQ_WAVE_STATUS__USER_PRIO__SHIFT 0x3
#define SQ_WAVE_STATUS__PRIV_MASK 0x20
#define SQ_WAVE_STATUS__PRIV__SHIFT 0x5
#define SQ_WAVE_STATUS__TRAP_EN_MASK 0x40
#define SQ_WAVE_STATUS__TRAP_EN__SHIFT 0x6
#define SQ_WAVE_STATUS__TTRACE_EN_MASK 0x80
#define SQ_WAVE_STATUS__TTRACE_EN__SHIFT 0x7
#define SQ_WAVE_STATUS__EXPORT_RDY_MASK 0x100
#define SQ_WAVE_STATUS__EXPORT_RDY__SHIFT 0x8
#define SQ_WAVE_STATUS__EXECZ_MASK 0x200
#define SQ_WAVE_STATUS__EXECZ__SHIFT 0x9
#define SQ_WAVE_STATUS__VCCZ_MASK 0x400
#define SQ_WAVE_STATUS__VCCZ__SHIFT 0xa
#define SQ_WAVE_STATUS__IN_TG_MASK 0x800
#define SQ_WAVE_STATUS__IN_TG__SHIFT 0xb
#define SQ_WAVE_STATUS__IN_BARRIER_MASK 0x1000
#define SQ_WAVE_STATUS__IN_BARRIER__SHIFT 0xc
#define SQ_WAVE_STATUS__HALT_MASK 0x2000
#define SQ_WAVE_STATUS__HALT__SHIFT 0xd
#define SQ_WAVE_STATUS__TRAP_MASK 0x4000
#define SQ_WAVE_STATUS__TRAP__SHIFT 0xe
#define SQ_WAVE_STATUS__TTRACE_CU_EN_MASK 0x8000
#define SQ_WAVE_STATUS__TTRACE_CU_EN__SHIFT 0xf
#define SQ_WAVE_STATUS__VALID_MASK 0x10000
#define SQ_WAVE_STATUS__VALID__SHIFT 0x10
#define SQ_WAVE_STATUS__ECC_ERR_MASK 0x20000
#define SQ_WAVE_STATUS__ECC_ERR__SHIFT 0x11
#define SQ_WAVE_STATUS__SKIP_EXPORT_MASK 0x40000
#define SQ_WAVE_STATUS__SKIP_EXPORT__SHIFT 0x12
#define SQ_WAVE_STATUS__PERF_EN_MASK 0x80000
#define SQ_WAVE_STATUS__PERF_EN__SHIFT 0x13
#define SQ_WAVE_STATUS__COND_DBG_USER_MASK 0x100000
#define SQ_WAVE_STATUS__COND_DBG_USER__SHIFT 0x14
#define SQ_WAVE_STATUS__COND_DBG_SYS_MASK 0x200000
#define SQ_WAVE_STATUS__COND_DBG_SYS__SHIFT 0x15
#define SQ_WAVE_STATUS__ALLOW_REPLAY_MASK 0x400000
#define SQ_WAVE_STATUS__ALLOW_REPLAY__SHIFT 0x16
#define SQ_WAVE_STATUS__INST_ATC_MASK 0x800000
#define SQ_WAVE_STATUS__INST_ATC__SHIFT 0x17
#define SQ_WAVE_STATUS__MUST_EXPORT_MASK 0x8000000
#define SQ_WAVE_STATUS__MUST_EXPORT__SHIFT 0x1b
#define SQ_WAVE_MODE__FP_ROUND_MASK 0xf
#define SQ_WAVE_MODE__FP_ROUND__SHIFT 0x0
#define SQ_WAVE_MODE__FP_DENORM_MASK 0xf0
#define SQ_WAVE_MODE__FP_DENORM__SHIFT 0x4
#define SQ_WAVE_MODE__DX10_CLAMP_MASK 0x100
#define SQ_WAVE_MODE__DX10_CLAMP__SHIFT 0x8
#define SQ_WAVE_MODE__IEEE_MASK 0x200
#define SQ_WAVE_MODE__IEEE__SHIFT 0x9
#define SQ_WAVE_MODE__LOD_CLAMPED_MASK 0x400
#define SQ_WAVE_MODE__LOD_CLAMPED__SHIFT 0xa
#define SQ_WAVE_MODE__DEBUG_EN_MASK 0x800
#define SQ_WAVE_MODE__DEBUG_EN__SHIFT 0xb
#define SQ_WAVE_MODE__EXCP_EN_MASK 0x1ff000
#define SQ_WAVE_MODE__EXCP_EN__SHIFT 0xc
#define SQ_WAVE_MODE__GPR_IDX_EN_MASK 0x8000000
#define SQ_WAVE_MODE__GPR_IDX_EN__SHIFT 0x1b
#define SQ_WAVE_MODE__VSKIP_MASK 0x10000000
#define SQ_WAVE_MODE__VSKIP__SHIFT 0x1c
#define SQ_WAVE_MODE__CSP_MASK 0xe0000000
#define SQ_WAVE_MODE__CSP__SHIFT 0x1d
#define SQ_WAVE_TRAPSTS__EXCP_MASK 0x1ff
#define SQ_WAVE_TRAPSTS__EXCP__SHIFT 0x0
#define SQ_WAVE_TRAPSTS__SAVECTX_MASK 0x400
#define SQ_WAVE_TRAPSTS__SAVECTX__SHIFT 0xa
#define SQ_WAVE_TRAPSTS__EXCP_CYCLE_MASK 0x3f0000
#define SQ_WAVE_TRAPSTS__EXCP_CYCLE__SHIFT 0x10
#define SQ_WAVE_TRAPSTS__DP_RATE_MASK 0xe0000000
#define SQ_WAVE_TRAPSTS__DP_RATE__SHIFT 0x1d
#define SQ_WAVE_HW_ID__WAVE_ID_MASK 0xf
#define SQ_WAVE_HW_ID__WAVE_ID__SHIFT 0x0
#define SQ_WAVE_HW_ID__SIMD_ID_MASK 0x30
#define SQ_WAVE_HW_ID__SIMD_ID__SHIFT 0x4
#define SQ_WAVE_HW_ID__PIPE_ID_MASK 0xc0
#define SQ_WAVE_HW_ID__PIPE_ID__SHIFT 0x6
#define SQ_WAVE_HW_ID__CU_ID_MASK 0xf00
#define SQ_WAVE_HW_ID__CU_ID__SHIFT 0x8
#define SQ_WAVE_HW_ID__SH_ID_MASK 0x1000
#define SQ_WAVE_HW_ID__SH_ID__SHIFT 0xc
#define SQ_WAVE_HW_ID__SE_ID_MASK 0x6000
#define SQ_WAVE_HW_ID__SE_ID__SHIFT 0xd
#define SQ_WAVE_HW_ID__TG_ID_MASK 0xf0000
#define SQ_WAVE_HW_ID__TG_ID__SHIFT 0x10
#define SQ_WAVE_HW_ID__VM_ID_MASK 0xf00000
#define SQ_WAVE_HW_ID__VM_ID__SHIFT 0x14
#define SQ_WAVE_HW_ID__QUEUE_ID_MASK 0x7000000
#define SQ_WAVE_HW_ID__QUEUE_ID__SHIFT 0x18
#define SQ_WAVE_HW_ID__STATE_ID_MASK 0x38000000
#define SQ_WAVE_HW_ID__STATE_ID__SHIFT 0x1b
#define SQ_WAVE_HW_ID__ME_ID_MASK 0xc0000000
#define SQ_WAVE_HW_ID__ME_ID__SHIFT 0x1e
#define SQ_WAVE_GPR_ALLOC__VGPR_BASE_MASK 0x3f
#define SQ_WAVE_GPR_ALLOC__VGPR_BASE__SHIFT 0x0
#define SQ_WAVE_GPR_ALLOC__VGPR_SIZE_MASK 0x3f00
#define SQ_WAVE_GPR_ALLOC__VGPR_SIZE__SHIFT 0x8
#define SQ_WAVE_GPR_ALLOC__SGPR_BASE_MASK 0x3f0000
#define SQ_WAVE_GPR_ALLOC__SGPR_BASE__SHIFT 0x10
#define SQ_WAVE_GPR_ALLOC__SGPR_SIZE_MASK 0xf000000
#define SQ_WAVE_GPR_ALLOC__SGPR_SIZE__SHIFT 0x18
#define SQ_WAVE_LDS_ALLOC__LDS_BASE_MASK 0xff
#define SQ_WAVE_LDS_ALLOC__LDS_BASE__SHIFT 0x0
#define SQ_WAVE_LDS_ALLOC__LDS_SIZE_MASK 0x1ff000
#define SQ_WAVE_LDS_ALLOC__LDS_SIZE__SHIFT 0xc
#define SQ_WAVE_IB_STS__VM_CNT_MASK 0xf
#define SQ_WAVE_IB_STS__VM_CNT__SHIFT 0x0
#define SQ_WAVE_IB_STS__EXP_CNT_MASK 0x70
#define SQ_WAVE_IB_STS__EXP_CNT__SHIFT 0x4
#define SQ_WAVE_IB_STS__LGKM_CNT_MASK 0xf00
#define SQ_WAVE_IB_STS__LGKM_CNT__SHIFT 0x8
#define SQ_WAVE_IB_STS__VALU_CNT_MASK 0x7000
#define SQ_WAVE_IB_STS__VALU_CNT__SHIFT 0xc
#define SQ_WAVE_IB_STS__FIRST_REPLAY_MASK 0x8000
#define SQ_WAVE_IB_STS__FIRST_REPLAY__SHIFT 0xf
#define SQ_WAVE_IB_STS__RCNT_MASK 0xf0000
#define SQ_WAVE_IB_STS__RCNT__SHIFT 0x10
#define SQ_WAVE_M0__M0_MASK 0xffffffff
#define SQ_WAVE_M0__M0__SHIFT 0x0
#define SQ_WAVE_TBA_LO__ADDR_LO_MASK 0xffffffff
#define SQ_WAVE_TBA_LO__ADDR_LO__SHIFT 0x0
#define SQ_WAVE_TBA_HI__ADDR_HI_MASK 0xff
#define SQ_WAVE_TBA_HI__ADDR_HI__SHIFT 0x0
#define SQ_WAVE_TMA_LO__ADDR_LO_MASK 0xffffffff
#define SQ_WAVE_TMA_LO__ADDR_LO__SHIFT 0x0
#define SQ_WAVE_TMA_HI__ADDR_HI_MASK 0xff
#define SQ_WAVE_TMA_HI__ADDR_HI__SHIFT 0x0
#define SQ_WAVE_TTMP0__DATA_MASK 0xffffffff
#define SQ_WAVE_TTMP0__DATA__SHIFT 0x0
#define SQ_WAVE_TTMP1__DATA_MASK 0xffffffff
#define SQ_WAVE_TTMP1__DATA__SHIFT 0x0
#define SQ_WAVE_TTMP2__DATA_MASK 0xffffffff
#define SQ_WAVE_TTMP2__DATA__SHIFT 0x0
#define SQ_WAVE_TTMP3__DATA_MASK 0xffffffff
#define SQ_WAVE_TTMP3__DATA__SHIFT 0x0
#define SQ_WAVE_TTMP4__DATA_MASK 0xffffffff
#define SQ_WAVE_TTMP4__DATA__SHIFT 0x0
#define SQ_WAVE_TTMP5__DATA_MASK 0xffffffff
#define SQ_WAVE_TTMP5__DATA__SHIFT 0x0
#define SQ_WAVE_TTMP6__DATA_MASK 0xffffffff
#define SQ_WAVE_TTMP6__DATA__SHIFT 0x0
#define SQ_WAVE_TTMP7__DATA_MASK 0xffffffff
#define SQ_WAVE_TTMP7__DATA__SHIFT 0x0
#define SQ_WAVE_TTMP8__DATA_MASK 0xffffffff
#define SQ_WAVE_TTMP8__DATA__SHIFT 0x0
#define SQ_WAVE_TTMP9__DATA_MASK 0xffffffff
#define SQ_WAVE_TTMP9__DATA__SHIFT 0x0
#define SQ_WAVE_TTMP10__DATA_MASK 0xffffffff
#define SQ_WAVE_TTMP10__DATA__SHIFT 0x0
#define SQ_WAVE_TTMP11__DATA_MASK 0xffffffff
#define SQ_WAVE_TTMP11__DATA__SHIFT 0x0
#define SQ_DEBUG_STS_GLOBAL__BUSY_MASK 0x1
#define SQ_DEBUG_STS_GLOBAL__BUSY__SHIFT 0x0
#define SQ_DEBUG_STS_GLOBAL__INTERRUPT_MSG_BUSY_MASK 0x2
#define SQ_DEBUG_STS_GLOBAL__INTERRUPT_MSG_BUSY__SHIFT 0x1
#define SQ_DEBUG_STS_GLOBAL__WAVE_LEVEL_SH0_MASK 0xfff0
#define SQ_DEBUG_STS_GLOBAL__WAVE_LEVEL_SH0__SHIFT 0x4
#define SQ_DEBUG_STS_GLOBAL__WAVE_LEVEL_SH1_MASK 0xfff0000
#define SQ_DEBUG_STS_GLOBAL__WAVE_LEVEL_SH1__SHIFT 0x10
#define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_GFX0_MASK 0xff
#define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_GFX0__SHIFT 0x0
#define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_GFX1_MASK 0xff00
#define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_GFX1__SHIFT 0x8
#define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_IMMED_MASK 0xff0000
#define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_IMMED__SHIFT 0x10
#define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_HOST_MASK 0xff000000
#define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_HOST__SHIFT 0x18
#define SQ_DEBUG_STS_GLOBAL3__FIFO_LEVEL_HOST_CMD_MASK 0xf
#define SQ_DEBUG_STS_GLOBAL3__FIFO_LEVEL_HOST_CMD__SHIFT 0x0
#define SQ_DEBUG_STS_GLOBAL3__FIFO_LEVEL_HOST_REG_MASK 0x3f0
#define SQ_DEBUG_STS_GLOBAL3__FIFO_LEVEL_HOST_REG__SHIFT 0x4
#define SQ_DEBUG_STS_LOCAL__BUSY_MASK 0x1
#define SQ_DEBUG_STS_LOCAL__BUSY__SHIFT 0x0
#define SQ_DEBUG_STS_LOCAL__WAVE_LEVEL_MASK 0x3f0
#define SQ_DEBUG_STS_LOCAL__WAVE_LEVEL__SHIFT 0x4
#define SQ_DEBUG_CTRL_LOCAL__UNUSED_MASK 0xff
#define SQ_DEBUG_CTRL_LOCAL__UNUSED__SHIFT 0x0
#define SH_MEM_BASES__PRIVATE_BASE_MASK 0xffff
#define SH_MEM_BASES__PRIVATE_BASE__SHIFT 0x0
#define SH_MEM_BASES__SHARED_BASE_MASK 0xffff0000
#define SH_MEM_BASES__SHARED_BASE__SHIFT 0x10
#define SH_MEM_APE1_BASE__BASE_MASK 0xffffffff
#define SH_MEM_APE1_BASE__BASE__SHIFT 0x0
#define SH_MEM_APE1_LIMIT__LIMIT_MASK 0xffffffff
#define SH_MEM_APE1_LIMIT__LIMIT__SHIFT 0x0
#define SH_MEM_CONFIG__ADDRESS_MODE_MASK 0x3
#define SH_MEM_CONFIG__ADDRESS_MODE__SHIFT 0x0
#define SH_MEM_CONFIG__PRIVATE_ATC_MASK 0x4
#define SH_MEM_CONFIG__PRIVATE_ATC__SHIFT 0x2
#define SH_MEM_CONFIG__ALIGNMENT_MODE_MASK 0x18
#define SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT 0x3
#define SH_MEM_CONFIG__DEFAULT_MTYPE_MASK 0xe0
#define SH_MEM_CONFIG__DEFAULT_MTYPE__SHIFT 0x5
#define SH_MEM_CONFIG__APE1_MTYPE_MASK 0x700
#define SH_MEM_CONFIG__APE1_MTYPE__SHIFT 0x8
#define SH_MEM_CONFIG__APE1_ATC_MASK 0x800
#define SH_MEM_CONFIG__APE1_ATC__SHIFT 0xb
#define SQ_THREAD_TRACE_WORD_CMN__TOKEN_TYPE_MASK 0xf
#define SQ_THREAD_TRACE_WORD_CMN__TOKEN_TYPE__SHIFT 0x0
#define SQ_THREAD_TRACE_WORD_CMN__TIME_DELTA_MASK 0x10
#define SQ_THREAD_TRACE_WORD_CMN__TIME_DELTA__SHIFT 0x4
#define SQ_THREAD_TRACE_WORD_INST__TOKEN_TYPE_MASK 0xf
#define SQ_THREAD_TRACE_WORD_INST__TOKEN_TYPE__SHIFT 0x0
#define SQ_THREAD_TRACE_WORD_INST__TIME_DELTA_MASK 0x10
#define SQ_THREAD_TRACE_WORD_INST__TIME_DELTA__SHIFT 0x4
#define SQ_THREAD_TRACE_WORD_INST__WAVE_ID_MASK 0x1e0
#define SQ_THREAD_TRACE_WORD_INST__WAVE_ID__SHIFT 0x5
#define SQ_THREAD_TRACE_WORD_INST__SIMD_ID_MASK 0x600
#define SQ_THREAD_TRACE_WORD_INST__SIMD_ID__SHIFT 0x9
#define SQ_THREAD_TRACE_WORD_INST__INST_TYPE_MASK 0xf800
#define SQ_THREAD_TRACE_WORD_INST__INST_TYPE__SHIFT 0xb
#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__TOKEN_TYPE_MASK 0xf
#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__TOKEN_TYPE__SHIFT 0x0
#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__TIME_DELTA_MASK 0x10
#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__TIME_DELTA__SHIFT 0x4
#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__WAVE_ID_MASK 0x1e0
#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__WAVE_ID__SHIFT 0x5
#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__SIMD_ID_MASK 0x600
#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__SIMD_ID__SHIFT 0x9
#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__PC_LO_MASK 0xffff0000
#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__PC_LO__SHIFT 0x10
#define SQ_THREAD_TRACE_WORD_INST_PC_2_OF_2__PC_HI_MASK 0xffffff
#define SQ_THREAD_TRACE_WORD_INST_PC_2_OF_2__PC_HI__SHIFT 0x0
#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__TOKEN_TYPE_MASK 0xf
#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__TOKEN_TYPE__SHIFT 0x0
#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__TIME_DELTA_MASK 0x10
#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__TIME_DELTA__SHIFT 0x4
#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__SH_ID_MASK 0x20
#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__SH_ID__SHIFT 0x5
#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__CU_ID_MASK 0x3c0
#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__CU_ID__SHIFT 0x6
#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__WAVE_ID_MASK 0x3c00
#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__WAVE_ID__SHIFT 0xa
#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__SIMD_ID_MASK 0xc000
#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__SIMD_ID__SHIFT 0xe
#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__DATA_LO_MASK 0xffff0000
#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__DATA_LO__SHIFT 0x10
#define SQ_THREAD_TRACE_WORD_INST_USERDATA_2_OF_2__DATA_HI_MASK 0xffff
#define SQ_THREAD_TRACE_WORD_INST_USERDATA_2_OF_2__DATA_HI__SHIFT 0x0
#define SQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2__TOKEN_TYPE_MASK 0xf
#define SQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2__TOKEN_TYPE__SHIFT 0x0
#define SQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2__TIME_LO_MASK 0xffff0000
#define SQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2__TIME_LO__SHIFT 0x10
#define SQ_THREAD_TRACE_WORD_TIMESTAMP_2_OF_2__TIME_HI_MASK 0xffffffff
#define SQ_THREAD_TRACE_WORD_TIMESTAMP_2_OF_2__TIME_HI__SHIFT 0x0
#define SQ_THREAD_TRACE_WORD_WAVE__TOKEN_TYPE_MASK 0xf
#define SQ_THREAD_TRACE_WORD_WAVE__TOKEN_TYPE__SHIFT 0x0
#define SQ_THREAD_TRACE_WORD_WAVE__TIME_DELTA_MASK 0x10
#define SQ_THREAD_TRACE_WORD_WAVE__TIME_DELTA__SHIFT 0x4
#define SQ_THREAD_TRACE_WORD_WAVE__SH_ID_MASK 0x20
#define SQ_THREAD_TRACE_WORD_WAVE__SH_ID__SHIFT 0x5
#define SQ_THREAD_TRACE_WORD_WAVE__CU_ID_MASK 0x3c0
#define SQ_THREAD_TRACE_WORD_WAVE__CU_ID__SHIFT 0x6
#define SQ_THREAD_TRACE_WORD_WAVE__WAVE_ID_MASK 0x3c00
#define SQ_THREAD_TRACE_WORD_WAVE__WAVE_ID__SHIFT 0xa
#define SQ_THREAD_TRACE_WORD_WAVE__SIMD_ID_MASK 0xc000
#define SQ_THREAD_TRACE_WORD_WAVE__SIMD_ID__SHIFT 0xe
#define SQ_THREAD_TRACE_WORD_MISC__TOKEN_TYPE_MASK 0xf
#define SQ_THREAD_TRACE_WORD_MISC__TOKEN_TYPE__SHIFT 0x0
#define SQ_THREAD_TRACE_WORD_MISC__TIME_DELTA_MASK 0xff0
#define SQ_THREAD_TRACE_WORD_MISC__TIME_DELTA__SHIFT 0x4
#define SQ_THREAD_TRACE_WORD_MISC__SH_ID_MASK 0x1000
#define SQ_THREAD_TRACE_WORD_MISC__SH_ID__SHIFT 0xc
#define SQ_THREAD_TRACE_WORD_MISC__MISC_TOKEN_TYPE_MASK 0xe000
#define SQ_THREAD_TRACE_WORD_MISC__MISC_TOKEN_TYPE__SHIFT 0xd
#define SQ_THREAD_TRACE_WORD_WAVE_START__TOKEN_TYPE_MASK 0xf
#define SQ_THREAD_TRACE_WORD_WAVE_START__TOKEN_TYPE__SHIFT 0x0
#define SQ_THREAD_TRACE_WORD_WAVE_START__TIME_DELTA_MASK 0x10
#define SQ_THREAD_TRACE_WORD_WAVE_START__TIME_DELTA__SHIFT 0x4
#define SQ_THREAD_TRACE_WORD_WAVE_START__SH_ID_MASK 0x20
#define SQ_THREAD_TRACE_WORD_WAVE_START__SH_ID__SHIFT 0x5
#define SQ_THREAD_TRACE_WORD_WAVE_START__CU_ID_MASK 0x3c0
#define SQ_THREAD_TRACE_WORD_WAVE_START__CU_ID__SHIFT 0x6
#define SQ_THREAD_TRACE_WORD_WAVE_START__WAVE_ID_MASK 0x3c00
#define SQ_THREAD_TRACE_WORD_WAVE_START__WAVE_ID__SHIFT 0xa
#define SQ_THREAD_TRACE_WORD_WAVE_START__SIMD_ID_MASK 0xc000
#define SQ_THREAD_TRACE_WORD_WAVE_START__SIMD_ID__SHIFT 0xe
#define SQ_THREAD_TRACE_WORD_WAVE_START__DISPATCHER_MASK 0x1f0000
#define SQ_THREAD_TRACE_WORD_WAVE_START__DISPATCHER__SHIFT 0x10
#define SQ_THREAD_TRACE_WORD_WAVE_START__VS_NO_ALLOC_OR_GROUPED_MASK 0x200000
#define SQ_THREAD_TRACE_WORD_WAVE_START__VS_NO_ALLOC_OR_GROUPED__SHIFT 0x15
#define SQ_THREAD_TRACE_WORD_WAVE_START__COUNT_MASK 0x1fc00000
#define SQ_THREAD_TRACE_WORD_WAVE_START__COUNT__SHIFT 0x16
#define SQ_THREAD_TRACE_WORD_WAVE_START__TG_ID_MASK 0xe0000000
#define SQ_THREAD_TRACE_WORD_WAVE_START__TG_ID__SHIFT 0x1d
#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__TOKEN_TYPE_MASK 0xf
#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__TOKEN_TYPE__SHIFT 0x0
#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__TIME_DELTA_MASK 0x10
#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__TIME_DELTA__SHIFT 0x4
#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__PIPE_ID_MASK 0x60
#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__PIPE_ID__SHIFT 0x5
#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__ME_ID_MASK 0x180
#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__ME_ID__SHIFT 0x7
#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_DROPPED_PREV_MASK 0x200
#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_DROPPED_PREV__SHIFT 0x9
#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_TYPE_MASK 0x1c00
#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_TYPE__SHIFT 0xa
#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_PRIV_MASK 0x4000
#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_PRIV__SHIFT 0xe
#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_OP_MASK 0x8000
#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_OP__SHIFT 0xf
#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_ADDR_MASK 0xffff0000
#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_ADDR__SHIFT 0x10
#define SQ_THREAD_TRACE_WORD_REG_2_OF_2__DATA_MASK 0xffffffff
#define SQ_THREAD_TRACE_WORD_REG_2_OF_2__DATA__SHIFT 0x0
#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__TOKEN_TYPE_MASK 0xf
#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__TOKEN_TYPE__SHIFT 0x0
#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__TIME_DELTA_MASK 0x10
#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__TIME_DELTA__SHIFT 0x4
#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__PIPE_ID_MASK 0x60
#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__PIPE_ID__SHIFT 0x5
#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__ME_ID_MASK 0x180
#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__ME_ID__SHIFT 0x7
#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__REG_ADDR_MASK 0xfe00
#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__REG_ADDR__SHIFT 0x9
#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__DATA_LO_MASK 0xffff0000
#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__DATA_LO__SHIFT 0x10
#define SQ_THREAD_TRACE_WORD_REG_CS_2_OF_2__DATA_HI_MASK 0xffff
#define SQ_THREAD_TRACE_WORD_REG_CS_2_OF_2__DATA_HI__SHIFT 0x0
#define SQ_THREAD_TRACE_WORD_EVENT__TOKEN_TYPE_MASK 0xf
#define SQ_THREAD_TRACE_WORD_EVENT__TOKEN_TYPE__SHIFT 0x0
#define SQ_THREAD_TRACE_WORD_EVENT__TIME_DELTA_MASK 0x10
#define SQ_THREAD_TRACE_WORD_EVENT__TIME_DELTA__SHIFT 0x4
#define SQ_THREAD_TRACE_WORD_EVENT__SH_ID_MASK 0x20
#define SQ_THREAD_TRACE_WORD_EVENT__SH_ID__SHIFT 0x5
#define SQ_THREAD_TRACE_WORD_EVENT__STAGE_MASK 0x1c0
#define SQ_THREAD_TRACE_WORD_EVENT__STAGE__SHIFT 0x6
#define SQ_THREAD_TRACE_WORD_EVENT__EVENT_TYPE_MASK 0xfc00
#define SQ_THREAD_TRACE_WORD_EVENT__EVENT_TYPE__SHIFT 0xa
#define SQ_THREAD_TRACE_WORD_ISSUE__TOKEN_TYPE_MASK 0xf
#define SQ_THREAD_TRACE_WORD_ISSUE__TOKEN_TYPE__SHIFT 0x0
#define SQ_THREAD_TRACE_WORD_ISSUE__TIME_DELTA_MASK 0x10
#define SQ_THREAD_TRACE_WORD_ISSUE__TIME_DELTA__SHIFT 0x4
#define SQ_THREAD_TRACE_WORD_ISSUE__SIMD_ID_MASK 0x60
#define SQ_THREAD_TRACE_WORD_ISSUE__SIMD_ID__SHIFT 0x5
#define SQ_THREAD_TRACE_WORD_ISSUE__INST0_MASK 0x300
#define SQ_THREAD_TRACE_WORD_ISSUE__INST0__SHIFT 0x8
#define SQ_THREAD_TRACE_WORD_ISSUE__INST1_MASK 0xc00
#define SQ_THREAD_TRACE_WORD_ISSUE__INST1__SHIFT 0xa
#define SQ_THREAD_TRACE_WORD_ISSUE__INST2_MASK 0x3000
#define SQ_THREAD_TRACE_WORD_ISSUE__INST2__SHIFT 0xc
#define SQ_THREAD_TRACE_WORD_ISSUE__INST3_MASK 0xc000
#define SQ_THREAD_TRACE_WORD_ISSUE__INST3__SHIFT 0xe
#define SQ_THREAD_TRACE_WORD_ISSUE__INST4_MASK 0x30000
#define SQ_THREAD_TRACE_WORD_ISSUE__INST4__SHIFT 0x10
#define SQ_THREAD_TRACE_WORD_ISSUE__INST5_MASK 0xc0000
#define SQ_THREAD_TRACE_WORD_ISSUE__INST5__SHIFT 0x12
#define SQ_THREAD_TRACE_WORD_ISSUE__INST6_MASK 0x300000
#define SQ_THREAD_TRACE_WORD_ISSUE__INST6__SHIFT 0x14
#define SQ_THREAD_TRACE_WORD_ISSUE__INST7_MASK 0xc00000
#define SQ_THREAD_TRACE_WORD_ISSUE__INST7__SHIFT 0x16
#define SQ_THREAD_TRACE_WORD_ISSUE__INST8_MASK 0x3000000
#define SQ_THREAD_TRACE_WORD_ISSUE__INST8__SHIFT 0x18
#define SQ_THREAD_TRACE_WORD_ISSUE__INST9_MASK 0xc000000
#define SQ_THREAD_TRACE_WORD_ISSUE__INST9__SHIFT 0x1a
#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__TOKEN_TYPE_MASK 0xf
#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__TOKEN_TYPE__SHIFT 0x0
#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__TIME_DELTA_MASK 0x10
#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__TIME_DELTA__SHIFT 0x4
#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__SH_ID_MASK 0x20
#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__SH_ID__SHIFT 0x5
#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CU_ID_MASK 0x3c0
#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CU_ID__SHIFT 0x6
#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CNTR_BANK_MASK 0xc00
#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CNTR_BANK__SHIFT 0xa
#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CNTR0_MASK 0x1fff000
#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CNTR0__SHIFT 0xc
#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CNTR1_LO_MASK 0xfe000000
#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CNTR1_LO__SHIFT 0x19
#define SQ_THREAD_TRACE_WORD_PERF_2_OF_2__CNTR1_HI_MASK 0x3f
#define SQ_THREAD_TRACE_WORD_PERF_2_OF_2__CNTR1_HI__SHIFT 0x0
#define SQ_THREAD_TRACE_WORD_PERF_2_OF_2__CNTR2_MASK 0x7ffc0
#define SQ_THREAD_TRACE_WORD_PERF_2_OF_2__CNTR2__SHIFT 0x6
#define SQ_THREAD_TRACE_WORD_PERF_2_OF_2__CNTR3_MASK 0xfff80000
#define SQ_THREAD_TRACE_WORD_PERF_2_OF_2__CNTR3__SHIFT 0x13
#define SQ_WREXEC_EXEC_LO__ADDR_LO_MASK 0xffffffff
#define SQ_WREXEC_EXEC_LO__ADDR_LO__SHIFT 0x0
#define SQ_WREXEC_EXEC_HI__ADDR_HI_MASK 0xffff
#define SQ_WREXEC_EXEC_HI__ADDR_HI__SHIFT 0x0
#define SQ_WREXEC_EXEC_HI__FIRST_WAVE_MASK 0x4000000
#define SQ_WREXEC_EXEC_HI__FIRST_WAVE__SHIFT 0x1a
#define SQ_WREXEC_EXEC_HI__ATC_MASK 0x8000000
#define SQ_WREXEC_EXEC_HI__ATC__SHIFT 0x1b
#define SQ_WREXEC_EXEC_HI__MTYPE_MASK 0x70000000
#define SQ_WREXEC_EXEC_HI__MTYPE__SHIFT 0x1c
#define SQ_WREXEC_EXEC_HI__MSB_MASK 0x80000000
#define SQ_WREXEC_EXEC_HI__MSB__SHIFT 0x1f
#define SQC_GATCL1_CNTL__RESERVED_MASK 0x3ffff
#define SQC_GATCL1_CNTL__RESERVED__SHIFT 0x0
#define SQC_GATCL1_CNTL__DCACHE_INVALIDATE_ALL_VMID_MASK 0x40000
#define SQC_GATCL1_CNTL__DCACHE_INVALIDATE_ALL_VMID__SHIFT 0x12
#define SQC_GATCL1_CNTL__DCACHE_FORCE_MISS_MASK 0x80000
#define SQC_GATCL1_CNTL__DCACHE_FORCE_MISS__SHIFT 0x13
#define SQC_GATCL1_CNTL__DCACHE_FORCE_IN_ORDER_MASK 0x100000
#define SQC_GATCL1_CNTL__DCACHE_FORCE_IN_ORDER__SHIFT 0x14
#define SQC_GATCL1_CNTL__DCACHE_REDUCE_FIFO_DEPTH_BY_2_MASK 0x600000
#define SQC_GATCL1_CNTL__DCACHE_REDUCE_FIFO_DEPTH_BY_2__SHIFT 0x15
#define SQC_GATCL1_CNTL__DCACHE_REDUCE_CACHE_SIZE_BY_2_MASK 0x1800000
#define SQC_GATCL1_CNTL__DCACHE_REDUCE_CACHE_SIZE_BY_2__SHIFT 0x17
#define SQC_GATCL1_CNTL__ICACHE_INVALIDATE_ALL_VMID_MASK 0x2000000
#define SQC_GATCL1_CNTL__ICACHE_INVALIDATE_ALL_VMID__SHIFT 0x19
#define SQC_GATCL1_CNTL__ICACHE_FORCE_MISS_MASK 0x4000000
#define SQC_GATCL1_CNTL__ICACHE_FORCE_MISS__SHIFT 0x1a
#define SQC_GATCL1_CNTL__ICACHE_FORCE_IN_ORDER_MASK 0x8000000
#define SQC_GATCL1_CNTL__ICACHE_FORCE_IN_ORDER__SHIFT 0x1b
#define SQC_GATCL1_CNTL__ICACHE_REDUCE_FIFO_DEPTH_BY_2_MASK 0x30000000
#define SQC_GATCL1_CNTL__ICACHE_REDUCE_FIFO_DEPTH_BY_2__SHIFT 0x1c
#define SQC_GATCL1_CNTL__ICACHE_REDUCE_CACHE_SIZE_BY_2_MASK 0xc0000000
#define SQC_GATCL1_CNTL__ICACHE_REDUCE_CACHE_SIZE_BY_2__SHIFT 0x1e
#define SQC_ATC_EDC_GATCL1_CNT__ICACHE_DATA_SEC_MASK 0xff
#define SQC_ATC_EDC_GATCL1_CNT__ICACHE_DATA_SEC__SHIFT 0x0
#define SQC_ATC_EDC_GATCL1_CNT__DCACHE_DATA_SEC_MASK 0xff0000
#define SQC_ATC_EDC_GATCL1_CNT__DCACHE_DATA_SEC__SHIFT 0x10
#define SQ_INTERRUPT_WORD_CMN__SE_ID_MASK 0x3000000
#define SQ_INTERRUPT_WORD_CMN__SE_ID__SHIFT 0x18
#define SQ_INTERRUPT_WORD_CMN__ENCODING_MASK 0xc000000
#define SQ_INTERRUPT_WORD_CMN__ENCODING__SHIFT 0x1a
#define SQ_INTERRUPT_WORD_AUTO__THREAD_TRACE_MASK 0x1
#define SQ_INTERRUPT_WORD_AUTO__THREAD_TRACE__SHIFT 0x0
#define SQ_INTERRUPT_WORD_AUTO__WLT_MASK 0x2
#define SQ_INTERRUPT_WORD_AUTO__WLT__SHIFT 0x1
#define SQ_INTERRUPT_WORD_AUTO__THREAD_TRACE_BUF_FULL_MASK 0x4
#define SQ_INTERRUPT_WORD_AUTO__THREAD_TRACE_BUF_FULL__SHIFT 0x2
#define SQ_INTERRUPT_WORD_AUTO__REG_TIMESTAMP_MASK 0x8
#define SQ_INTERRUPT_WORD_AUTO__REG_TIMESTAMP__SHIFT 0x3
#define SQ_INTERRUPT_WORD_AUTO__CMD_TIMESTAMP_MASK 0x10
#define SQ_INTERRUPT_WORD_AUTO__CMD_TIMESTAMP__SHIFT 0x4
#define SQ_INTERRUPT_WORD_AUTO__HOST_CMD_OVERFLOW_MASK 0x20
#define SQ_INTERRUPT_WORD_AUTO__HOST_CMD_OVERFLOW__SHIFT 0x5
#define SQ_INTERRUPT_WORD_AUTO__HOST_REG_OVERFLOW_MASK 0x40
#define SQ_INTERRUPT_WORD_AUTO__HOST_REG_OVERFLOW__SHIFT 0x6
#define SQ_INTERRUPT_WORD_AUTO__IMMED_OVERFLOW_MASK 0x80
#define SQ_INTERRUPT_WORD_AUTO__IMMED_OVERFLOW__SHIFT 0x7
#define SQ_INTERRUPT_WORD_AUTO__SE_ID_MASK 0x3000000
#define SQ_INTERRUPT_WORD_AUTO__SE_ID__SHIFT 0x18
#define SQ_INTERRUPT_WORD_AUTO__ENCODING_MASK 0xc000000
#define SQ_INTERRUPT_WORD_AUTO__ENCODING__SHIFT 0x1a
#define SQ_INTERRUPT_WORD_WAVE__DATA_MASK 0xff
#define SQ_INTERRUPT_WORD_WAVE__DATA__SHIFT 0x0
#define SQ_INTERRUPT_WORD_WAVE__SH_ID_MASK 0x100
#define SQ_INTERRUPT_WORD_WAVE__SH_ID__SHIFT 0x8
#define SQ_INTERRUPT_WORD_WAVE__PRIV_MASK 0x200
#define SQ_INTERRUPT_WORD_WAVE__PRIV__SHIFT 0x9
#define SQ_INTERRUPT_WORD_WAVE__VM_ID_MASK 0x3c00
#define SQ_INTERRUPT_WORD_WAVE__VM_ID__SHIFT 0xa
#define SQ_INTERRUPT_WORD_WAVE__WAVE_ID_MASK 0x3c000
#define SQ_INTERRUPT_WORD_WAVE__WAVE_ID__SHIFT 0xe
#define SQ_INTERRUPT_WORD_WAVE__SIMD_ID_MASK 0xc0000
#define SQ_INTERRUPT_WORD_WAVE__SIMD_ID__SHIFT 0x12
#define SQ_INTERRUPT_WORD_WAVE__CU_ID_MASK 0xf00000
#define SQ_INTERRUPT_WORD_WAVE__CU_ID__SHIFT 0x14
#define SQ_INTERRUPT_WORD_WAVE__SE_ID_MASK 0x3000000
#define SQ_INTERRUPT_WORD_WAVE__SE_ID__SHIFT 0x18
#define SQ_INTERRUPT_WORD_WAVE__ENCODING_MASK 0xc000000
#define SQ_INTERRUPT_WORD_WAVE__ENCODING__SHIFT 0x1a
#define SQ_SOP2__SSRC0_MASK 0xff
#define SQ_SOP2__SSRC0__SHIFT 0x0
#define SQ_SOP2__SSRC1_MASK 0xff00
#define SQ_SOP2__SSRC1__SHIFT 0x8
#define SQ_SOP2__SDST_MASK 0x7f0000
#define SQ_SOP2__SDST__SHIFT 0x10
#define SQ_SOP2__OP_MASK 0x3f800000
#define SQ_SOP2__OP__SHIFT 0x17
#define SQ_SOP2__ENCODING_MASK 0xc0000000
#define SQ_SOP2__ENCODING__SHIFT 0x1e
#define SQ_VOP1__SRC0_MASK 0x1ff
#define SQ_VOP1__SRC0__SHIFT 0x0
#define SQ_VOP1__OP_MASK 0x1fe00
#define SQ_VOP1__OP__SHIFT 0x9
#define SQ_VOP1__VDST_MASK 0x1fe0000
#define SQ_VOP1__VDST__SHIFT 0x11
#define SQ_VOP1__ENCODING_MASK 0xfe000000
#define SQ_VOP1__ENCODING__SHIFT 0x19
#define SQ_MTBUF_1__VADDR_MASK 0xff
#define SQ_MTBUF_1__VADDR__SHIFT 0x0
#define SQ_MTBUF_1__VDATA_MASK 0xff00
#define SQ_MTBUF_1__VDATA__SHIFT 0x8
#define SQ_MTBUF_1__SRSRC_MASK 0x1f0000
#define SQ_MTBUF_1__SRSRC__SHIFT 0x10
#define SQ_MTBUF_1__SLC_MASK 0x400000
#define SQ_MTBUF_1__SLC__SHIFT 0x16
#define SQ_MTBUF_1__TFE_MASK 0x800000
#define SQ_MTBUF_1__TFE__SHIFT 0x17
#define SQ_MTBUF_1__SOFFSET_MASK 0xff000000
#define SQ_MTBUF_1__SOFFSET__SHIFT 0x18
#define SQ_EXP_1__VSRC0_MASK 0xff
#define SQ_EXP_1__VSRC0__SHIFT 0x0
#define SQ_EXP_1__VSRC1_MASK 0xff00
#define SQ_EXP_1__VSRC1__SHIFT 0x8
#define SQ_EXP_1__VSRC2_MASK 0xff0000
#define SQ_EXP_1__VSRC2__SHIFT 0x10
#define SQ_EXP_1__VSRC3_MASK 0xff000000
#define SQ_EXP_1__VSRC3__SHIFT 0x18
#define SQ_MUBUF_1__VADDR_MASK 0xff
#define SQ_MUBUF_1__VADDR__SHIFT 0x0
#define SQ_MUBUF_1__VDATA_MASK 0xff00
#define SQ_MUBUF_1__VDATA__SHIFT 0x8
#define SQ_MUBUF_1__SRSRC_MASK 0x1f0000
#define SQ_MUBUF_1__SRSRC__SHIFT 0x10
#define SQ_MUBUF_1__TFE_MASK 0x800000
#define SQ_MUBUF_1__TFE__SHIFT 0x17
#define SQ_MUBUF_1__SOFFSET_MASK 0xff000000
#define SQ_MUBUF_1__SOFFSET__SHIFT 0x18
#define SQ_SMEM_1__OFFSET_MASK 0xfffff
#define SQ_SMEM_1__OFFSET__SHIFT 0x0
#define SQ_INST__ENCODING_MASK 0xffffffff
#define SQ_INST__ENCODING__SHIFT 0x0
#define SQ_EXP_0__EN_MASK 0xf
#define SQ_EXP_0__EN__SHIFT 0x0
#define SQ_EXP_0__TGT_MASK 0x3f0
#define SQ_EXP_0__TGT__SHIFT 0x4
#define SQ_EXP_0__COMPR_MASK 0x400
#define SQ_EXP_0__COMPR__SHIFT 0xa
#define SQ_EXP_0__DONE_MASK 0x800
#define SQ_EXP_0__DONE__SHIFT 0xb
#define SQ_EXP_0__VM_MASK 0x1000
#define SQ_EXP_0__VM__SHIFT 0xc
#define SQ_EXP_0__ENCODING_MASK 0xfc000000
#define SQ_EXP_0__ENCODING__SHIFT 0x1a
#define SQ_MUBUF_0__OFFSET_MASK 0xfff
#define SQ_MUBUF_0__OFFSET__SHIFT 0x0
#define SQ_MUBUF_0__OFFEN_MASK 0x1000
#define SQ_MUBUF_0__OFFEN__SHIFT 0xc
#define SQ_MUBUF_0__IDXEN_MASK 0x2000
#define SQ_MUBUF_0__IDXEN__SHIFT 0xd
#define SQ_MUBUF_0__GLC_MASK 0x4000
#define SQ_MUBUF_0__GLC__SHIFT 0xe
#define SQ_MUBUF_0__LDS_MASK 0x10000
#define SQ_MUBUF_0__LDS__SHIFT 0x10
#define SQ_MUBUF_0__SLC_MASK 0x20000
#define SQ_MUBUF_0__SLC__SHIFT 0x11
#define SQ_MUBUF_0__OP_MASK 0x1fc0000
#define SQ_MUBUF_0__OP__SHIFT 0x12
#define SQ_MUBUF_0__ENCODING_MASK 0xfc000000
#define SQ_MUBUF_0__ENCODING__SHIFT 0x1a
#define SQ_VOP_SDWA__SRC0_MASK 0xff
#define SQ_VOP_SDWA__SRC0__SHIFT 0x0
#define SQ_VOP_SDWA__DST_SEL_MASK 0x700
#define SQ_VOP_SDWA__DST_SEL__SHIFT 0x8
#define SQ_VOP_SDWA__DST_UNUSED_MASK 0x1800
#define SQ_VOP_SDWA__DST_UNUSED__SHIFT 0xb
#define SQ_VOP_SDWA__CLAMP_MASK 0x2000
#define SQ_VOP_SDWA__CLAMP__SHIFT 0xd
#define SQ_VOP_SDWA__SRC0_SEL_MASK 0x70000
#define SQ_VOP_SDWA__SRC0_SEL__SHIFT 0x10
#define SQ_VOP_SDWA__SRC0_SEXT_MASK 0x80000
#define SQ_VOP_SDWA__SRC0_SEXT__SHIFT 0x13
#define SQ_VOP_SDWA__SRC0_NEG_MASK 0x100000
#define SQ_VOP_SDWA__SRC0_NEG__SHIFT 0x14
#define SQ_VOP_SDWA__SRC0_ABS_MASK 0x200000
#define SQ_VOP_SDWA__SRC0_ABS__SHIFT 0x15
#define SQ_VOP_SDWA__SRC1_SEL_MASK 0x7000000
#define SQ_VOP_SDWA__SRC1_SEL__SHIFT 0x18
#define SQ_VOP_SDWA__SRC1_SEXT_MASK 0x8000000
#define SQ_VOP_SDWA__SRC1_SEXT__SHIFT 0x1b
#define SQ_VOP_SDWA__SRC1_NEG_MASK 0x10000000
#define SQ_VOP_SDWA__SRC1_NEG__SHIFT 0x1c
#define SQ_VOP_SDWA__SRC1_ABS_MASK 0x20000000
#define SQ_VOP_SDWA__SRC1_ABS__SHIFT 0x1d
#define SQ_VOP3_0__VDST_MASK 0xff
#define SQ_VOP3_0__VDST__SHIFT 0x0
#define SQ_VOP3_0__ABS_MASK 0x700
#define SQ_VOP3_0__ABS__SHIFT 0x8
#define SQ_VOP3_0__CLAMP_MASK 0x8000
#define SQ_VOP3_0__CLAMP__SHIFT 0xf
#define SQ_VOP3_0__OP_MASK 0x3ff0000
#define SQ_VOP3_0__OP__SHIFT 0x10
#define SQ_VOP3_0__ENCODING_MASK 0xfc000000
#define SQ_VOP3_0__ENCODING__SHIFT 0x1a
#define SQ_VOP2__SRC0_MASK 0x1ff
#define SQ_VOP2__SRC0__SHIFT 0x0
#define SQ_VOP2__VSRC1_MASK 0x1fe00
#define SQ_VOP2__VSRC1__SHIFT 0x9
#define SQ_VOP2__VDST_MASK 0x1fe0000
#define SQ_VOP2__VDST__SHIFT 0x11
#define SQ_VOP2__OP_MASK 0x7e000000
#define SQ_VOP2__OP__SHIFT 0x19
#define SQ_VOP2__ENCODING_MASK 0x80000000
#define SQ_VOP2__ENCODING__SHIFT 0x1f
#define SQ_MTBUF_0__OFFSET_MASK 0xfff
#define SQ_MTBUF_0__OFFSET__SHIFT 0x0
#define SQ_MTBUF_0__OFFEN_MASK 0x1000
#define SQ_MTBUF_0__OFFEN__SHIFT 0xc
#define SQ_MTBUF_0__IDXEN_MASK 0x2000
#define SQ_MTBUF_0__IDXEN__SHIFT 0xd
#define SQ_MTBUF_0__GLC_MASK 0x4000
#define SQ_MTBUF_0__GLC__SHIFT 0xe
#define SQ_MTBUF_0__OP_MASK 0x78000
#define SQ_MTBUF_0__OP__SHIFT 0xf
#define SQ_MTBUF_0__DFMT_MASK 0x780000
#define SQ_MTBUF_0__DFMT__SHIFT 0x13
#define SQ_MTBUF_0__NFMT_MASK 0x3800000
#define SQ_MTBUF_0__NFMT__SHIFT 0x17
#define SQ_MTBUF_0__ENCODING_MASK 0xfc000000
#define SQ_MTBUF_0__ENCODING__SHIFT 0x1a
#define SQ_SOPP__SIMM16_MASK 0xffff
#define SQ_SOPP__SIMM16__SHIFT 0x0
#define SQ_SOPP__OP_MASK 0x7f0000
#define SQ_SOPP__OP__SHIFT 0x10
#define SQ_SOPP__ENCODING_MASK 0xff800000
#define SQ_SOPP__ENCODING__SHIFT 0x17
#define SQ_FLAT_0__GLC_MASK 0x10000
#define SQ_FLAT_0__GLC__SHIFT 0x10
#define SQ_FLAT_0__SLC_MASK 0x20000
#define SQ_FLAT_0__SLC__SHIFT 0x11
#define SQ_FLAT_0__OP_MASK 0x1fc0000
#define SQ_FLAT_0__OP__SHIFT 0x12
#define SQ_FLAT_0__ENCODING_MASK 0xfc000000
#define SQ_FLAT_0__ENCODING__SHIFT 0x1a
#define SQ_VOP3_0_SDST_ENC__VDST_MASK 0xff
#define SQ_VOP3_0_SDST_ENC__VDST__SHIFT 0x0
#define SQ_VOP3_0_SDST_ENC__SDST_MASK 0x7f00
#define SQ_VOP3_0_SDST_ENC__SDST__SHIFT 0x8
#define SQ_VOP3_0_SDST_ENC__CLAMP_MASK 0x8000
#define SQ_VOP3_0_SDST_ENC__CLAMP__SHIFT 0xf
#define SQ_VOP3_0_SDST_ENC__OP_MASK 0x3ff0000
#define SQ_VOP3_0_SDST_ENC__OP__SHIFT 0x10
#define SQ_VOP3_0_SDST_ENC__ENCODING_MASK 0xfc000000
#define SQ_VOP3_0_SDST_ENC__ENCODING__SHIFT 0x1a
#define SQ_MIMG_1__VADDR_MASK 0xff
#define SQ_MIMG_1__VADDR__SHIFT 0x0
#define SQ_MIMG_1__VDATA_MASK 0xff00
#define SQ_MIMG_1__VDATA__SHIFT 0x8
#define SQ_MIMG_1__SRSRC_MASK 0x1f0000
#define SQ_MIMG_1__SRSRC__SHIFT 0x10
#define SQ_MIMG_1__SSAMP_MASK 0x3e00000
#define SQ_MIMG_1__SSAMP__SHIFT 0x15
#define SQ_MIMG_1__D16_MASK 0x80000000
#define SQ_MIMG_1__D16__SHIFT 0x1f
#define SQ_SOP1__SSRC0_MASK 0xff
#define SQ_SOP1__SSRC0__SHIFT 0x0
#define SQ_SOP1__OP_MASK 0xff00
#define SQ_SOP1__OP__SHIFT 0x8
#define SQ_SOP1__SDST_MASK 0x7f0000
#define SQ_SOP1__SDST__SHIFT 0x10
#define SQ_SOP1__ENCODING_MASK 0xff800000
#define SQ_SOP1__ENCODING__SHIFT 0x17
#define SQ_SOPC__SSRC0_MASK 0xff
#define SQ_SOPC__SSRC0__SHIFT 0x0
#define SQ_SOPC__SSRC1_MASK 0xff00
#define SQ_SOPC__SSRC1__SHIFT 0x8
#define SQ_SOPC__OP_MASK 0x7f0000
#define SQ_SOPC__OP__SHIFT 0x10
#define SQ_SOPC__ENCODING_MASK 0xff800000
#define SQ_SOPC__ENCODING__SHIFT 0x17
#define SQ_FLAT_1__ADDR_MASK 0xff
#define SQ_FLAT_1__ADDR__SHIFT 0x0
#define SQ_FLAT_1__DATA_MASK 0xff00
#define SQ_FLAT_1__DATA__SHIFT 0x8
#define SQ_FLAT_1__TFE_MASK 0x800000
#define SQ_FLAT_1__TFE__SHIFT 0x17
#define SQ_FLAT_1__VDST_MASK 0xff000000
#define SQ_FLAT_1__VDST__SHIFT 0x18
#define SQ_DS_1__ADDR_MASK 0xff
#define SQ_DS_1__ADDR__SHIFT 0x0
#define SQ_DS_1__DATA0_MASK 0xff00
#define SQ_DS_1__DATA0__SHIFT 0x8
#define SQ_DS_1__DATA1_MASK 0xff0000
#define SQ_DS_1__DATA1__SHIFT 0x10
#define SQ_DS_1__VDST_MASK 0xff000000
#define SQ_DS_1__VDST__SHIFT 0x18
#define SQ_VOP3_1__SRC0_MASK 0x1ff
#define SQ_VOP3_1__SRC0__SHIFT 0x0
#define SQ_VOP3_1__SRC1_MASK 0x3fe00
#define SQ_VOP3_1__SRC1__SHIFT 0x9
#define SQ_VOP3_1__SRC2_MASK 0x7fc0000
#define SQ_VOP3_1__SRC2__SHIFT 0x12
#define SQ_VOP3_1__OMOD_MASK 0x18000000
#define SQ_VOP3_1__OMOD__SHIFT 0x1b
#define SQ_VOP3_1__NEG_MASK 0xe0000000
#define SQ_VOP3_1__NEG__SHIFT 0x1d
#define SQ_SMEM_0__SBASE_MASK 0x3f
#define SQ_SMEM_0__SBASE__SHIFT 0x0
#define SQ_SMEM_0__SDATA_MASK 0x1fc0
#define SQ_SMEM_0__SDATA__SHIFT 0x6
#define SQ_SMEM_0__GLC_MASK 0x10000
#define SQ_SMEM_0__GLC__SHIFT 0x10
#define SQ_SMEM_0__IMM_MASK 0x20000
#define SQ_SMEM_0__IMM__SHIFT 0x11
#define SQ_SMEM_0__OP_MASK 0x3fc0000
#define SQ_SMEM_0__OP__SHIFT 0x12
#define SQ_SMEM_0__ENCODING_MASK 0xfc000000
#define SQ_SMEM_0__ENCODING__SHIFT 0x1a
#define SQ_MIMG_0__DMASK_MASK 0xf00
#define SQ_MIMG_0__DMASK__SHIFT 0x8
#define SQ_MIMG_0__UNORM_MASK 0x1000
#define SQ_MIMG_0__UNORM__SHIFT 0xc
#define SQ_MIMG_0__GLC_MASK 0x2000
#define SQ_MIMG_0__GLC__SHIFT 0xd
#define SQ_MIMG_0__DA_MASK 0x4000
#define SQ_MIMG_0__DA__SHIFT 0xe
#define SQ_MIMG_0__R128_MASK 0x8000
#define SQ_MIMG_0__R128__SHIFT 0xf
#define SQ_MIMG_0__TFE_MASK 0x10000
#define SQ_MIMG_0__TFE__SHIFT 0x10
#define SQ_MIMG_0__LWE_MASK 0x20000
#define SQ_MIMG_0__LWE__SHIFT 0x11
#define SQ_MIMG_0__OP_MASK 0x1fc0000
#define SQ_MIMG_0__OP__SHIFT 0x12
#define SQ_MIMG_0__SLC_MASK 0x2000000
#define SQ_MIMG_0__SLC__SHIFT 0x19
#define SQ_MIMG_0__ENCODING_MASK 0xfc000000
#define SQ_MIMG_0__ENCODING__SHIFT 0x1a
#define SQ_SOPK__SIMM16_MASK 0xffff
#define SQ_SOPK__SIMM16__SHIFT 0x0
#define SQ_SOPK__SDST_MASK 0x7f0000
#define SQ_SOPK__SDST__SHIFT 0x10
#define SQ_SOPK__OP_MASK 0xf800000
#define SQ_SOPK__OP__SHIFT 0x17
#define SQ_SOPK__ENCODING_MASK 0xf0000000
#define SQ_SOPK__ENCODING__SHIFT 0x1c
#define SQ_DS_0__OFFSET0_MASK 0xff
#define SQ_DS_0__OFFSET0__SHIFT 0x0
#define SQ_DS_0__OFFSET1_MASK 0xff00
#define SQ_DS_0__OFFSET1__SHIFT 0x8
#define SQ_DS_0__GDS_MASK 0x10000
#define SQ_DS_0__GDS__SHIFT 0x10
#define SQ_DS_0__OP_MASK 0x1fe0000
#define SQ_DS_0__OP__SHIFT 0x11
#define SQ_DS_0__ENCODING_MASK 0xfc000000
#define SQ_DS_0__ENCODING__SHIFT 0x1a
#define SQ_VOP_DPP__SRC0_MASK 0xff
#define SQ_VOP_DPP__SRC0__SHIFT 0x0
#define SQ_VOP_DPP__DPP_CTRL_MASK 0x1ff00
#define SQ_VOP_DPP__DPP_CTRL__SHIFT 0x8
#define SQ_VOP_DPP__BOUND_CTRL_MASK 0x80000
#define SQ_VOP_DPP__BOUND_CTRL__SHIFT 0x13
#define SQ_VOP_DPP__SRC0_NEG_MASK 0x100000
#define SQ_VOP_DPP__SRC0_NEG__SHIFT 0x14
#define SQ_VOP_DPP__SRC0_ABS_MASK 0x200000
#define SQ_VOP_DPP__SRC0_ABS__SHIFT 0x15
#define SQ_VOP_DPP__SRC1_NEG_MASK 0x400000
#define SQ_VOP_DPP__SRC1_NEG__SHIFT 0x16
#define SQ_VOP_DPP__SRC1_ABS_MASK 0x800000
#define SQ_VOP_DPP__SRC1_ABS__SHIFT 0x17
#define SQ_VOP_DPP__BANK_MASK_MASK 0xf000000
#define SQ_VOP_DPP__BANK_MASK__SHIFT 0x18
#define SQ_VOP_DPP__ROW_MASK_MASK 0xf0000000
#define SQ_VOP_DPP__ROW_MASK__SHIFT 0x1c
#define SQ_VOPC__SRC0_MASK 0x1ff
#define SQ_VOPC__SRC0__SHIFT 0x0
#define SQ_VOPC__VSRC1_MASK 0x1fe00
#define SQ_VOPC__VSRC1__SHIFT 0x9
#define SQ_VOPC__OP_MASK 0x1fe0000
#define SQ_VOPC__OP__SHIFT 0x11
#define SQ_VOPC__ENCODING_MASK 0xfe000000
#define SQ_VOPC__ENCODING__SHIFT 0x19
#define SQ_VINTRP__VSRC_MASK 0xff
#define SQ_VINTRP__VSRC__SHIFT 0x0
#define SQ_VINTRP__ATTRCHAN_MASK 0x300
#define SQ_VINTRP__ATTRCHAN__SHIFT 0x8
#define SQ_VINTRP__ATTR_MASK 0xfc00
#define SQ_VINTRP__ATTR__SHIFT 0xa
#define SQ_VINTRP__OP_MASK 0x30000
#define SQ_VINTRP__OP__SHIFT 0x10
#define SQ_VINTRP__VDST_MASK 0x3fc0000
#define SQ_VINTRP__VDST__SHIFT 0x12
#define SQ_VINTRP__ENCODING_MASK 0xfc000000
#define SQ_VINTRP__ENCODING__SHIFT 0x1a
#define CGTT_SX_CLK_CTRL0__ON_DELAY_MASK 0xf
#define CGTT_SX_CLK_CTRL0__ON_DELAY__SHIFT 0x0
#define CGTT_SX_CLK_CTRL0__OFF_HYSTERESIS_MASK 0xff0
#define CGTT_SX_CLK_CTRL0__OFF_HYSTERESIS__SHIFT 0x4
#define CGTT_SX_CLK_CTRL0__RESERVED_MASK 0xfff000
#define CGTT_SX_CLK_CTRL0__RESERVED__SHIFT 0xc
#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE7_MASK 0x1000000
#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE7__SHIFT 0x18
#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE6_MASK 0x2000000
#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE6__SHIFT 0x19
#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE5_MASK 0x4000000
#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE5__SHIFT 0x1a
#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE4_MASK 0x8000000
#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE4__SHIFT 0x1b
#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE3_MASK 0x10000000
#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE3__SHIFT 0x1c
#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE2_MASK 0x20000000
#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE2__SHIFT 0x1d
#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE1_MASK 0x40000000
#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE1__SHIFT 0x1e
#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE0_MASK 0x80000000
#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE0__SHIFT 0x1f
#define CGTT_SX_CLK_CTRL1__ON_DELAY_MASK 0xf
#define CGTT_SX_CLK_CTRL1__ON_DELAY__SHIFT 0x0
#define CGTT_SX_CLK_CTRL1__OFF_HYSTERESIS_MASK 0xff0
#define CGTT_SX_CLK_CTRL1__OFF_HYSTERESIS__SHIFT 0x4
#define CGTT_SX_CLK_CTRL1__RESERVED_MASK 0xfff000
#define CGTT_SX_CLK_CTRL1__RESERVED__SHIFT 0xc
#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE7_MASK 0x1000000
#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE7__SHIFT 0x18
#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE6_MASK 0x2000000
#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE6__SHIFT 0x19
#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE5_MASK 0x4000000
#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE5__SHIFT 0x1a
#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE4_MASK 0x8000000
#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE4__SHIFT 0x1b
#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE3_MASK 0x10000000
#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE3__SHIFT 0x1c
#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE2_MASK 0x20000000
#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE2__SHIFT 0x1d
#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE1_MASK 0x40000000
#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE1__SHIFT 0x1e
#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE0_MASK 0x80000000
#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE0__SHIFT 0x1f
#define CGTT_SX_CLK_CTRL2__ON_DELAY_MASK 0xf
#define CGTT_SX_CLK_CTRL2__ON_DELAY__SHIFT 0x0
#define CGTT_SX_CLK_CTRL2__OFF_HYSTERESIS_MASK 0xff0
#define CGTT_SX_CLK_CTRL2__OFF_HYSTERESIS__SHIFT 0x4
#define CGTT_SX_CLK_CTRL2__RESERVED_MASK 0xfff000
#define CGTT_SX_CLK_CTRL2__RESERVED__SHIFT 0xc
#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE7_MASK 0x1000000
#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE7__SHIFT 0x18
#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE6_MASK 0x2000000
#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE6__SHIFT 0x19
#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE5_MASK 0x4000000
#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE5__SHIFT 0x1a
#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE4_MASK 0x8000000
#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE4__SHIFT 0x1b
#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE3_MASK 0x10000000
#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE3__SHIFT 0x1c
#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE2_MASK 0x20000000
#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE2__SHIFT 0x1d
#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE1_MASK 0x40000000
#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE1__SHIFT 0x1e
#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE0_MASK 0x80000000
#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE0__SHIFT 0x1f
#define CGTT_SX_CLK_CTRL3__ON_DELAY_MASK 0xf
#define CGTT_SX_CLK_CTRL3__ON_DELAY__SHIFT 0x0
#define CGTT_SX_CLK_CTRL3__OFF_HYSTERESIS_MASK 0xff0
#define CGTT_SX_CLK_CTRL3__OFF_HYSTERESIS__SHIFT 0x4
#define CGTT_SX_CLK_CTRL3__RESERVED_MASK 0xfff000
#define CGTT_SX_CLK_CTRL3__RESERVED__SHIFT 0xc
#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE7_MASK 0x1000000
#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE7__SHIFT 0x18
#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE6_MASK 0x2000000
#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE6__SHIFT 0x19
#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE5_MASK 0x4000000
#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE5__SHIFT 0x1a
#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE4_MASK 0x8000000
#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE4__SHIFT 0x1b
#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE3_MASK 0x10000000
#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE3__SHIFT 0x1c
#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE2_MASK 0x20000000
#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE2__SHIFT 0x1d
#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE1_MASK 0x40000000
#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE1__SHIFT 0x1e
#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE0_MASK 0x80000000
#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE0__SHIFT 0x1f
#define CGTT_SX_CLK_CTRL4__ON_DELAY_MASK 0xf
#define CGTT_SX_CLK_CTRL4__ON_DELAY__SHIFT 0x0
#define CGTT_SX_CLK_CTRL4__OFF_HYSTERESIS_MASK 0xff0
#define CGTT_SX_CLK_CTRL4__OFF_HYSTERESIS__SHIFT 0x4
#define CGTT_SX_CLK_CTRL4__RESERVED_MASK 0xfff000
#define CGTT_SX_CLK_CTRL4__RESERVED__SHIFT 0xc
#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE7_MASK 0x1000000
#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE7__SHIFT 0x18
#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE6_MASK 0x2000000
#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE6__SHIFT 0x19
#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE5_MASK 0x4000000
#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE5__SHIFT 0x1a
#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE4_MASK 0x8000000
#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE4__SHIFT 0x1b
#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE3_MASK 0x10000000
#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE3__SHIFT 0x1c
#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE2_MASK 0x20000000
#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE2__SHIFT 0x1d
#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE1_MASK 0x40000000
#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE1__SHIFT 0x1e
#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE0_MASK 0x80000000
#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE0__SHIFT 0x1f
#define SX_DEBUG_BUSY__POS_FREE_OR_VALIDS_MASK 0x1
#define SX_DEBUG_BUSY__POS_FREE_OR_VALIDS__SHIFT 0x0
#define SX_DEBUG_BUSY__POS_REQUESTER_BUSY_MASK 0x2
#define SX_DEBUG_BUSY__POS_REQUESTER_BUSY__SHIFT 0x1
#define SX_DEBUG_BUSY__PA_SX_BUSY_MASK 0x4
#define SX_DEBUG_BUSY__PA_SX_BUSY__SHIFT 0x2
#define SX_DEBUG_BUSY__POS_SCBD_BUSY_MASK 0x8
#define SX_DEBUG_BUSY__POS_SCBD_BUSY__SHIFT 0x3
#define SX_DEBUG_BUSY__POS_BANK3VAL3_BUSY_MASK 0x10
#define SX_DEBUG_BUSY__POS_BANK3VAL3_BUSY__SHIFT 0x4
#define SX_DEBUG_BUSY__POS_BANK3VAL2_BUSY_MASK 0x20
#define SX_DEBUG_BUSY__POS_BANK3VAL2_BUSY__SHIFT 0x5
#define SX_DEBUG_BUSY__POS_BANK3VAL1_BUSY_MASK 0x40
#define SX_DEBUG_BUSY__POS_BANK3VAL1_BUSY__SHIFT 0x6
#define SX_DEBUG_BUSY__POS_BANK3VAL0_BUSY_MASK 0x80
#define SX_DEBUG_BUSY__POS_BANK3VAL0_BUSY__SHIFT 0x7
#define SX_DEBUG_BUSY__POS_BANK2VAL3_BUSY_MASK 0x100
#define SX_DEBUG_BUSY__POS_BANK2VAL3_BUSY__SHIFT 0x8
#define SX_DEBUG_BUSY__POS_BANK2VAL2_BUSY_MASK 0x200
#define SX_DEBUG_BUSY__POS_BANK2VAL2_BUSY__SHIFT 0x9
#define SX_DEBUG_BUSY__POS_BANK2VAL1_BUSY_MASK 0x400
#define SX_DEBUG_BUSY__POS_BANK2VAL1_BUSY__SHIFT 0xa
#define SX_DEBUG_BUSY__POS_BANK2VAL0_BUSY_MASK 0x800
#define SX_DEBUG_BUSY__POS_BANK2VAL0_BUSY__SHIFT 0xb
#define SX_DEBUG_BUSY__POS_BANK1VAL3_BUSY_MASK 0x1000
#define SX_DEBUG_BUSY__POS_BANK1VAL3_BUSY__SHIFT 0xc
#define SX_DEBUG_BUSY__POS_BANK1VAL2_BUSY_MASK 0x2000
#define SX_DEBUG_BUSY__POS_BANK1VAL2_BUSY__SHIFT 0xd
#define SX_DEBUG_BUSY__POS_BANK1VAL1_BUSY_MASK 0x4000
#define SX_DEBUG_BUSY__POS_BANK1VAL1_BUSY__SHIFT 0xe
#define SX_DEBUG_BUSY__POS_BANK1VAL0_BUSY_MASK 0x8000
#define SX_DEBUG_BUSY__POS_BANK1VAL0_BUSY__SHIFT 0xf
#define SX_DEBUG_BUSY__POS_BANK0VAL3_BUSY_MASK 0x10000
#define SX_DEBUG_BUSY__POS_BANK0VAL3_BUSY__SHIFT 0x10
#define SX_DEBUG_BUSY__POS_BANK0VAL2_BUSY_MASK 0x20000
#define SX_DEBUG_BUSY__POS_BANK0VAL2_BUSY__SHIFT 0x11
#define SX_DEBUG_BUSY__POS_BANK0VAL1_BUSY_MASK 0x40000
#define SX_DEBUG_BUSY__POS_BANK0VAL1_BUSY__SHIFT 0x12
#define SX_DEBUG_BUSY__POS_BANK0VAL0_BUSY_MASK 0x80000
#define SX_DEBUG_BUSY__POS_BANK0VAL0_BUSY__SHIFT 0x13
#define SX_DEBUG_BUSY__POS_INMUX_VALID_MASK 0x100000
#define SX_DEBUG_BUSY__POS_INMUX_VALID__SHIFT 0x14
#define SX_DEBUG_BUSY__WRCTRL1_VALIDQ3_MASK 0x200000
#define SX_DEBUG_BUSY__WRCTRL1_VALIDQ3__SHIFT 0x15
#define SX_DEBUG_BUSY__WRCTRL1_VALIDQ2_MASK 0x400000
#define SX_DEBUG_BUSY__WRCTRL1_VALIDQ2__SHIFT 0x16
#define SX_DEBUG_BUSY__WRCTRL1_VALIDQ1_MASK 0x800000
#define SX_DEBUG_BUSY__WRCTRL1_VALIDQ1__SHIFT 0x17
#define SX_DEBUG_BUSY__WRCTRL0_VALIDQ3_MASK 0x1000000
#define SX_DEBUG_BUSY__WRCTRL0_VALIDQ3__SHIFT 0x18
#define SX_DEBUG_BUSY__WRCTRL0_VALIDQ2_MASK 0x2000000
#define SX_DEBUG_BUSY__WRCTRL0_VALIDQ2__SHIFT 0x19
#define SX_DEBUG_BUSY__WRCTRL0_VALIDQ1_MASK 0x4000000
#define SX_DEBUG_BUSY__WRCTRL0_VALIDQ1__SHIFT 0x1a
#define SX_DEBUG_BUSY__PCCMD_VALID_MASK 0x8000000
#define SX_DEBUG_BUSY__PCCMD_VALID__SHIFT 0x1b
#define SX_DEBUG_BUSY__VDATA1_VALID_MASK 0x10000000
#define SX_DEBUG_BUSY__VDATA1_VALID__SHIFT 0x1c
#define SX_DEBUG_BUSY__VDATA0_VALID_MASK 0x20000000
#define SX_DEBUG_BUSY__VDATA0_VALID__SHIFT 0x1d
#define SX_DEBUG_BUSY__CMD_BUSYORVAL_MASK 0x40000000
#define SX_DEBUG_BUSY__CMD_BUSYORVAL__SHIFT 0x1e
#define SX_DEBUG_BUSY__ADDR_BUSYORVAL_MASK 0x80000000
#define SX_DEBUG_BUSY__ADDR_BUSYORVAL__SHIFT 0x1f
#define SX_DEBUG_BUSY_2__COL_SCBD_BUSY_MASK 0x1
#define SX_DEBUG_BUSY_2__COL_SCBD_BUSY__SHIFT 0x0
#define SX_DEBUG_BUSY_2__COL_REQ3_FREECNT_NE0_MASK 0x2
#define SX_DEBUG_BUSY_2__COL_REQ3_FREECNT_NE0__SHIFT 0x1
#define SX_DEBUG_BUSY_2__COL_REQ3_IDLE_MASK 0x4
#define SX_DEBUG_BUSY_2__COL_REQ3_IDLE__SHIFT 0x2
#define SX_DEBUG_BUSY_2__COL_REQ3_BUSY_MASK 0x8
#define SX_DEBUG_BUSY_2__COL_REQ3_BUSY__SHIFT 0x3
#define SX_DEBUG_BUSY_2__COL_REQ2_FREECNT_NE0_MASK 0x10
#define SX_DEBUG_BUSY_2__COL_REQ2_FREECNT_NE0__SHIFT 0x4
#define SX_DEBUG_BUSY_2__COL_REQ2_IDLE_MASK 0x20
#define SX_DEBUG_BUSY_2__COL_REQ2_IDLE__SHIFT 0x5
#define SX_DEBUG_BUSY_2__COL_REQ2_BUSY_MASK 0x40
#define SX_DEBUG_BUSY_2__COL_REQ2_BUSY__SHIFT 0x6
#define SX_DEBUG_BUSY_2__COL_REQ1_FREECNT_NE0_MASK 0x80
#define SX_DEBUG_BUSY_2__COL_REQ1_FREECNT_NE0__SHIFT 0x7
#define SX_DEBUG_BUSY_2__COL_REQ1_IDLE_MASK 0x100
#define SX_DEBUG_BUSY_2__COL_REQ1_IDLE__SHIFT 0x8
#define SX_DEBUG_BUSY_2__COL_REQ1_BUSY_MASK 0x200
#define SX_DEBUG_BUSY_2__COL_REQ1_BUSY__SHIFT 0x9
#define SX_DEBUG_BUSY_2__COL_REQ0_FREECNT_NE0_MASK 0x400
#define SX_DEBUG_BUSY_2__COL_REQ0_FREECNT_NE0__SHIFT 0xa
#define SX_DEBUG_BUSY_2__COL_REQ0_IDLE_MASK 0x800
#define SX_DEBUG_BUSY_2__COL_REQ0_IDLE__SHIFT 0xb
#define SX_DEBUG_BUSY_2__COL_REQ0_BUSY_MASK 0x1000
#define SX_DEBUG_BUSY_2__COL_REQ0_BUSY__SHIFT 0xc
#define SX_DEBUG_BUSY_2__COL_DBIF3_SENDFREE_BUSY_MASK 0x2000
#define SX_DEBUG_BUSY_2__COL_DBIF3_SENDFREE_BUSY__SHIFT 0xd
#define SX_DEBUG_BUSY_2__COL_DBIF3_FIFO_BUSY_MASK 0x4000
#define SX_DEBUG_BUSY_2__COL_DBIF3_FIFO_BUSY__SHIFT 0xe
#define SX_DEBUG_BUSY_2__COL_DBIF3_READ_VALID_MASK 0x8000
#define SX_DEBUG_BUSY_2__COL_DBIF3_READ_VALID__SHIFT 0xf
#define SX_DEBUG_BUSY_2__COL_DBIF2_SENDFREE_BUSY_MASK 0x10000
#define SX_DEBUG_BUSY_2__COL_DBIF2_SENDFREE_BUSY__SHIFT 0x10
#define SX_DEBUG_BUSY_2__COL_DBIF2_FIFO_BUSY_MASK 0x20000
#define SX_DEBUG_BUSY_2__COL_DBIF2_FIFO_BUSY__SHIFT 0x11
#define SX_DEBUG_BUSY_2__COL_DBIF2_READ_VALID_MASK 0x40000
#define SX_DEBUG_BUSY_2__COL_DBIF2_READ_VALID__SHIFT 0x12
#define SX_DEBUG_BUSY_2__COL_DBIF1_SENDFREE_BUSY_MASK 0x80000
#define SX_DEBUG_BUSY_2__COL_DBIF1_SENDFREE_BUSY__SHIFT 0x13
#define SX_DEBUG_BUSY_2__COL_DBIF1_FIFO_BUSY_MASK 0x100000
#define SX_DEBUG_BUSY_2__COL_DBIF1_FIFO_BUSY__SHIFT 0x14
#define SX_DEBUG_BUSY_2__COL_DBIF1_READ_VALID_MASK 0x200000
#define SX_DEBUG_BUSY_2__COL_DBIF1_READ_VALID__SHIFT 0x15
#define SX_DEBUG_BUSY_2__COL_DBIF0_SENDFREE_BUSY_MASK 0x400000
#define SX_DEBUG_BUSY_2__COL_DBIF0_SENDFREE_BUSY__SHIFT 0x16
#define SX_DEBUG_BUSY_2__COL_DBIF0_FIFO_BUSY_MASK 0x800000
#define SX_DEBUG_BUSY_2__COL_DBIF0_FIFO_BUSY__SHIFT 0x17
#define SX_DEBUG_BUSY_2__COL_DBIF0_READ_VALID_MASK 0x1000000
#define SX_DEBUG_BUSY_2__COL_DBIF0_READ_VALID__SHIFT 0x18
#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK3_VAL3_BUSY_MASK 0x2000000
#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK3_VAL3_BUSY__SHIFT 0x19
#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK3_VAL2_BUSY_MASK 0x4000000
#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK3_VAL2_BUSY__SHIFT 0x1a
#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK3_VAL1_BUSY_MASK 0x8000000
#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK3_VAL1_BUSY__SHIFT 0x1b
#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK3_VAL0_BUSY_MASK 0x10000000
#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK3_VAL0_BUSY__SHIFT 0x1c
#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK2_VAL3_BUSY_MASK 0x20000000
#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK2_VAL3_BUSY__SHIFT 0x1d
#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK2_VAL2_BUSY_MASK 0x40000000
#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK2_VAL2_BUSY__SHIFT 0x1e
#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK2_VAL1_BUSY_MASK 0x80000000
#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK2_VAL1_BUSY__SHIFT 0x1f
#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK2_VAL0_BUSY_MASK 0x1
#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK2_VAL0_BUSY__SHIFT 0x0
#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK1_VAL3_BUSY_MASK 0x2
#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK1_VAL3_BUSY__SHIFT 0x1
#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK1_VAL2_BUSY_MASK 0x4
#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK1_VAL2_BUSY__SHIFT 0x2
#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK1_VAL1_BUSY_MASK 0x8
#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK1_VAL1_BUSY__SHIFT 0x3
#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK1_VAL0_BUSY_MASK 0x10
#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK1_VAL0_BUSY__SHIFT 0x4
#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK0_VAL3_BUSY_MASK 0x20
#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK0_VAL3_BUSY__SHIFT 0x5
#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK0_VAL2_BUSY_MASK 0x40
#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK0_VAL2_BUSY__SHIFT 0x6
#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK0_VAL1_BUSY_MASK 0x80
#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK0_VAL1_BUSY__SHIFT 0x7
#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK0_VAL0_BUSY_MASK 0x100
#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK0_VAL0_BUSY__SHIFT 0x8
#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK3_VAL3_BUSY_MASK 0x200
#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK3_VAL3_BUSY__SHIFT 0x9
#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK3_VAL2_BUSY_MASK 0x400
#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK3_VAL2_BUSY__SHIFT 0xa
#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK3_VAL1_BUSY_MASK 0x800
#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK3_VAL1_BUSY__SHIFT 0xb
#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK3_VAL0_BUSY_MASK 0x1000
#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK3_VAL0_BUSY__SHIFT 0xc
#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK2_VAL3_BUSY_MASK 0x2000
#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK2_VAL3_BUSY__SHIFT 0xd
#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK2_VAL2_BUSY_MASK 0x4000
#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK2_VAL2_BUSY__SHIFT 0xe
#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK2_VAL1_BUSY_MASK 0x8000
#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK2_VAL1_BUSY__SHIFT 0xf
#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK2_VAL0_BUSY_MASK 0x10000
#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK2_VAL0_BUSY__SHIFT 0x10
#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK1_VAL3_BUSY_MASK 0x20000
#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK1_VAL3_BUSY__SHIFT 0x11
#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK1_VAL2_BUSY_MASK 0x40000
#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK1_VAL2_BUSY__SHIFT 0x12
#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK1_VAL1_BUSY_MASK 0x80000
#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK1_VAL1_BUSY__SHIFT 0x13
#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK1_VAL0_BUSY_MASK 0x100000
#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK1_VAL0_BUSY__SHIFT 0x14
#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK0_VAL3_BUSY_MASK 0x200000
#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK0_VAL3_BUSY__SHIFT 0x15
#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK0_VAL2_BUSY_MASK 0x400000
#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK0_VAL2_BUSY__SHIFT 0x16
#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK0_VAL1_BUSY_MASK 0x800000
#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK0_VAL1_BUSY__SHIFT 0x17
#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK0_VAL0_BUSY_MASK 0x1000000
#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK0_VAL0_BUSY__SHIFT 0x18
#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK3_VAL3_BUSY_MASK 0x2000000
#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK3_VAL3_BUSY__SHIFT 0x19
#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK3_VAL2_BUSY_MASK 0x4000000
#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK3_VAL2_BUSY__SHIFT 0x1a
#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK3_VAL1_BUSY_MASK 0x8000000
#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK3_VAL1_BUSY__SHIFT 0x1b
#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK3_VAL0_BUSY_MASK 0x10000000
#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK3_VAL0_BUSY__SHIFT 0x1c
#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK2_VAL3_BUSY_MASK 0x20000000
#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK2_VAL3_BUSY__SHIFT 0x1d
#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK2_VAL2_BUSY_MASK 0x40000000
#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK2_VAL2_BUSY__SHIFT 0x1e
#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK2_VAL1_BUSY_MASK 0x80000000
#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK2_VAL1_BUSY__SHIFT 0x1f
#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK2_VAL0_BUSY_MASK 0x1
#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK2_VAL0_BUSY__SHIFT 0x0
#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK1_VAL3_BUSY_MASK 0x2
#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK1_VAL3_BUSY__SHIFT 0x1
#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK1_VAL2_BUSY_MASK 0x4
#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK1_VAL2_BUSY__SHIFT 0x2
#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK1_VAL1_BUSY_MASK 0x8
#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK1_VAL1_BUSY__SHIFT 0x3
#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK1_VAL0_BUSY_MASK 0x10
#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK1_VAL0_BUSY__SHIFT 0x4
#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK0_VAL3_BUSY_MASK 0x20
#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK0_VAL3_BUSY__SHIFT 0x5
#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK0_VAL2_BUSY_MASK 0x40
#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK0_VAL2_BUSY__SHIFT 0x6
#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK0_VAL1_BUSY_MASK 0x80
#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK0_VAL1_BUSY__SHIFT 0x7
#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK0_VAL0_BUSY_MASK 0x100
#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK0_VAL0_BUSY__SHIFT 0x8
#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK3_VAL3_BUSY_MASK 0x200
#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK3_VAL3_BUSY__SHIFT 0x9
#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK3_VAL2_BUSY_MASK 0x400
#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK3_VAL2_BUSY__SHIFT 0xa
#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK3_VAL1_BUSY_MASK 0x800
#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK3_VAL1_BUSY__SHIFT 0xb
#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK3_VAL0_BUSY_MASK 0x1000
#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK3_VAL0_BUSY__SHIFT 0xc
#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK2_VAL3_BUSY_MASK 0x2000
#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK2_VAL3_BUSY__SHIFT 0xd
#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK2_VAL2_BUSY_MASK 0x4000
#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK2_VAL2_BUSY__SHIFT 0xe
#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK2_VAL1_BUSY_MASK 0x8000
#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK2_VAL1_BUSY__SHIFT 0xf
#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK2_VAL0_BUSY_MASK 0x10000
#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK2_VAL0_BUSY__SHIFT 0x10
#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK1_VAL3_BUSY_MASK 0x20000
#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK1_VAL3_BUSY__SHIFT 0x11
#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK1_VAL2_BUSY_MASK 0x40000
#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK1_VAL2_BUSY__SHIFT 0x12
#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK1_VAL1_BUSY_MASK 0x80000
#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK1_VAL1_BUSY__SHIFT 0x13
#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK1_VAL0_BUSY_MASK 0x100000
#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK1_VAL0_BUSY__SHIFT 0x14
#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK0_VAL3_BUSY_MASK 0x200000
#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK0_VAL3_BUSY__SHIFT 0x15
#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK0_VAL2_BUSY_MASK 0x400000
#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK0_VAL2_BUSY__SHIFT 0x16
#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK0_VAL1_BUSY_MASK 0x800000
#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK0_VAL1_BUSY__SHIFT 0x17
#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK0_VAL0_BUSY_MASK 0x1000000
#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK0_VAL0_BUSY__SHIFT 0x18
#define SX_DEBUG_BUSY_4__RESERVED_MASK 0xfe000000
#define SX_DEBUG_BUSY_4__RESERVED__SHIFT 0x19
#define SX_DEBUG_1__SX_DB_QUAD_CREDIT_MASK 0x7f
#define SX_DEBUG_1__SX_DB_QUAD_CREDIT__SHIFT 0x0
#define SX_DEBUG_1__DEBUG_DATA_MASK 0xffffff80
#define SX_DEBUG_1__DEBUG_DATA__SHIFT 0x7
#define SX_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT_MASK 0x3ff
#define SX_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT__SHIFT 0x0
#define SX_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT1_MASK 0xffc00
#define SX_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT1__SHIFT 0xa
#define SX_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000
#define SX_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
#define SX_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT_MASK 0x3ff
#define SX_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT__SHIFT 0x0
#define SX_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT1_MASK 0xffc00
#define SX_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT1__SHIFT 0xa
#define SX_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0xf00000
#define SX_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14
#define SX_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT_MASK 0x3ff
#define SX_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT__SHIFT 0x0
#define SX_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT1_MASK 0xffc00
#define SX_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT1__SHIFT 0xa
#define SX_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0xf00000
#define SX_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14
#define SX_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT_MASK 0x3ff
#define SX_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT__SHIFT 0x0
#define SX_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT1_MASK 0xffc00
#define SX_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT1__SHIFT 0xa
#define SX_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0xf00000
#define SX_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14
#define SX_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT2_MASK 0x3ff
#define SX_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT2__SHIFT 0x0
#define SX_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT3_MASK 0xffc00
#define SX_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT3__SHIFT 0xa
#define SX_PERFCOUNTER1_SELECT1__PERFCOUNTER_SELECT2_MASK 0x3ff
#define SX_PERFCOUNTER1_SELECT1__PERFCOUNTER_SELECT2__SHIFT 0x0
#define SX_PERFCOUNTER1_SELECT1__PERFCOUNTER_SELECT3_MASK 0xffc00
#define SX_PERFCOUNTER1_SELECT1__PERFCOUNTER_SELECT3__SHIFT 0xa
#define SX_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff
#define SX_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
#define SX_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff
#define SX_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
#define SX_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff
#define SX_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
#define SX_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff
#define SX_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
#define SX_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffff
#define SX_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0
#define SX_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffff
#define SX_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0
#define SX_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffff
#define SX_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0
#define SX_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffff
#define SX_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0
#define TCC_CTRL__CACHE_SIZE_MASK 0x3
#define TCC_CTRL__CACHE_SIZE__SHIFT 0x0
#define TCC_CTRL__RATE_MASK 0xc
#define TCC_CTRL__RATE__SHIFT 0x2
#define TCC_CTRL__WRITEBACK_MARGIN_MASK 0xf0
#define TCC_CTRL__WRITEBACK_MARGIN__SHIFT 0x4
#define TCC_CTRL__METADATA_LATENCY_FIFO_SIZE_MASK 0xf00
#define TCC_CTRL__METADATA_LATENCY_FIFO_SIZE__SHIFT 0x8
#define TCC_CTRL__SRC_FIFO_SIZE_MASK 0xf000
#define TCC_CTRL__SRC_FIFO_SIZE__SHIFT 0xc
#define TCC_CTRL__LATENCY_FIFO_SIZE_MASK 0xf0000
#define TCC_CTRL__LATENCY_FIFO_SIZE__SHIFT 0x10
#define TCC_CTRL__WB_OR_INV_ALL_VMIDS_MASK 0x100000
#define TCC_CTRL__WB_OR_INV_ALL_VMIDS__SHIFT 0x14
#define TCC_CTRL__MDC_SIZE_MASK 0x3000000
#define TCC_CTRL__MDC_SIZE__SHIFT 0x18
#define TCC_CTRL__MDC_SECTOR_SIZE_MASK 0xc000000
#define TCC_CTRL__MDC_SECTOR_SIZE__SHIFT 0x1a
#define TCC_CTRL__MDC_SIDEBAND_FIFO_SIZE_MASK 0xf0000000
#define TCC_CTRL__MDC_SIDEBAND_FIFO_SIZE__SHIFT 0x1c
#define TCC_EDC_CNT__SEC_COUNT_MASK 0xff
#define TCC_EDC_CNT__SEC_COUNT__SHIFT 0x0
#define TCC_EDC_CNT__DED_COUNT_MASK 0xff0000
#define TCC_EDC_CNT__DED_COUNT__SHIFT 0x10
#define TCC_REDUNDANCY__MC_SEL0_MASK 0x1
#define TCC_REDUNDANCY__MC_SEL0__SHIFT 0x0
#define TCC_REDUNDANCY__MC_SEL1_MASK 0x2
#define TCC_REDUNDANCY__MC_SEL1__SHIFT 0x1
#define TCC_EXE_DISABLE__EXE_DISABLE_MASK 0x2
#define TCC_EXE_DISABLE__EXE_DISABLE__SHIFT 0x1
#define TCC_DSM_CNTL__CACHE_RAM_IRRITATOR_DATA_SEL_MASK 0x3
#define TCC_DSM_CNTL__CACHE_RAM_IRRITATOR_DATA_SEL__SHIFT 0x0
#define TCC_DSM_CNTL__CACHE_RAM_IRRITATOR_SINGLE_WRITE_MASK 0x4
#define TCC_DSM_CNTL__CACHE_RAM_IRRITATOR_SINGLE_WRITE__SHIFT 0x2
#define TCC_CGTT_SCLK_CTRL__ON_DELAY_MASK 0xf
#define TCC_CGTT_SCLK_CTRL__ON_DELAY__SHIFT 0x0
#define TCC_CGTT_SCLK_CTRL__OFF_HYSTERESIS_MASK 0xff0
#define TCC_CGTT_SCLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE7_MASK 0x1000000
#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18
#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE6_MASK 0x2000000
#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19
#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE5_MASK 0x4000000
#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a
#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE4_MASK 0x8000000
#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b
#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000
#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c
#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000
#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d
#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000
#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e
#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000
#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f
#define TCA_CGTT_SCLK_CTRL__ON_DELAY_MASK 0xf
#define TCA_CGTT_SCLK_CTRL__ON_DELAY__SHIFT 0x0
#define TCA_CGTT_SCLK_CTRL__OFF_HYSTERESIS_MASK 0xff0
#define TCA_CGTT_SCLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE7_MASK 0x1000000
#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18
#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE6_MASK 0x2000000
#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19
#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE5_MASK 0x4000000
#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a
#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE4_MASK 0x8000000
#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b
#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000
#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c
#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000
#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d
#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000
#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e
#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000
#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f
#define TCC_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x3ff
#define TCC_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
#define TCC_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0xffc00
#define TCC_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
#define TCC_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000
#define TCC_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
#define TCC_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0xf000000
#define TCC_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18
#define TCC_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xf0000000
#define TCC_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c
#define TCC_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x3ff
#define TCC_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
#define TCC_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0xffc00
#define TCC_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa
#define TCC_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0xf00000
#define TCC_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14
#define TCC_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0xf000000
#define TCC_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18
#define TCC_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xf0000000
#define TCC_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c
#define TCC_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x3ff
#define TCC_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0
#define TCC_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0xffc00
#define TCC_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
#define TCC_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xf000000
#define TCC_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x18
#define TCC_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0xf0000000
#define TCC_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x1c
#define TCC_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x3ff
#define TCC_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0
#define TCC_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0xffc00
#define TCC_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa
#define TCC_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0xf000000
#define TCC_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x18
#define TCC_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0xf0000000
#define TCC_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x1c
#define TCC_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x3ff
#define TCC_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0
#define TCC_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0xf00000
#define TCC_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14
#define TCC_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xf0000000
#define TCC_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c
#define TCC_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x3ff
#define TCC_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0
#define TCC_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0xf00000
#define TCC_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14
#define TCC_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xf0000000
#define TCC_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c
#define TCC_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff
#define TCC_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
#define TCC_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff
#define TCC_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
#define TCC_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffff
#define TCC_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0
#define TCC_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffff
#define TCC_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0
#define TCC_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff
#define TCC_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
#define TCC_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff
#define TCC_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
#define TCC_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffff
#define TCC_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0
#define TCC_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffff
#define TCC_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0
#define TCA_CTRL__HOLE_TIMEOUT_MASK 0xf
#define TCA_CTRL__HOLE_TIMEOUT__SHIFT 0x0
#define TCA_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x3ff
#define TCA_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
#define TCA_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0xffc00
#define TCA_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
#define TCA_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000
#define TCA_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
#define TCA_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0xf000000
#define TCA_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18
#define TCA_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xf0000000
#define TCA_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c
#define TCA_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x3ff
#define TCA_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
#define TCA_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0xffc00
#define TCA_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa
#define TCA_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0xf00000
#define TCA_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14
#define TCA_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0xf000000
#define TCA_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18
#define TCA_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xf0000000
#define TCA_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c
#define TCA_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x3ff
#define TCA_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0
#define TCA_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0xffc00
#define TCA_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
#define TCA_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xf000000
#define TCA_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x18
#define TCA_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0xf0000000
#define TCA_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x1c
#define TCA_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x3ff
#define TCA_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0
#define TCA_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0xffc00
#define TCA_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa
#define TCA_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0xf000000
#define TCA_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x18
#define TCA_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0xf0000000
#define TCA_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x1c
#define TCA_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x3ff
#define TCA_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0
#define TCA_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0xf00000
#define TCA_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14
#define TCA_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xf0000000
#define TCA_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c
#define TCA_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x3ff
#define TCA_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0
#define TCA_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0xf00000
#define TCA_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14
#define TCA_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xf0000000
#define TCA_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c
#define TCA_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff
#define TCA_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
#define TCA_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff
#define TCA_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
#define TCA_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffff
#define TCA_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0
#define TCA_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffff
#define TCA_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0
#define TCA_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff
#define TCA_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
#define TCA_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff
#define TCA_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
#define TCA_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffff
#define TCA_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0
#define TCA_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffff
#define TCA_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0
#define TA_BC_BASE_ADDR__ADDRESS_MASK 0xffffffff
#define TA_BC_BASE_ADDR__ADDRESS__SHIFT 0x0
#define TA_BC_BASE_ADDR_HI__ADDRESS_MASK 0xff
#define TA_BC_BASE_ADDR_HI__ADDRESS__SHIFT 0x0
#define TD_CNTL__SYNC_PHASE_SH_MASK 0x3
#define TD_CNTL__SYNC_PHASE_SH__SHIFT 0x0
#define TD_CNTL__SYNC_PHASE_VC_SMX_MASK 0x30
#define TD_CNTL__SYNC_PHASE_VC_SMX__SHIFT 0x4
#define TD_CNTL__PAD_STALL_EN_MASK 0x100
#define TD_CNTL__PAD_STALL_EN__SHIFT 0x8
#define TD_CNTL__EXTEND_LDS_STALL_MASK 0x600
#define TD_CNTL__EXTEND_LDS_STALL__SHIFT 0x9
#define TD_CNTL__LDS_STALL_PHASE_ADJUST_MASK 0x1800
#define TD_CNTL__LDS_STALL_PHASE_ADJUST__SHIFT 0xb
#define TD_CNTL__PRECISION_COMPATIBILITY_MASK 0x8000
#define TD_CNTL__PRECISION_COMPATIBILITY__SHIFT 0xf
#define TD_CNTL__GATHER4_FLOAT_MODE_MASK 0x10000
#define TD_CNTL__GATHER4_FLOAT_MODE__SHIFT 0x10
#define TD_CNTL__LD_FLOAT_MODE_MASK 0x40000
#define TD_CNTL__LD_FLOAT_MODE__SHIFT 0x12
#define TD_CNTL__GATHER4_DX9_MODE_MASK 0x80000
#define TD_CNTL__GATHER4_DX9_MODE__SHIFT 0x13
#define TD_CNTL__DISABLE_POWER_THROTTLE_MASK 0x100000
#define TD_CNTL__DISABLE_POWER_THROTTLE__SHIFT 0x14
#define TD_CNTL__ENABLE_ROUND_TO_ZERO_MASK 0x200000
#define TD_CNTL__ENABLE_ROUND_TO_ZERO__SHIFT 0x15
#define TD_STATUS__BUSY_MASK 0x80000000
#define TD_STATUS__BUSY__SHIFT 0x1f
#define TD_DEBUG_INDEX__INDEX_MASK 0x1f
#define TD_DEBUG_INDEX__INDEX__SHIFT 0x0
#define TD_DEBUG_DATA__DATA_MASK 0xffffffff
#define TD_DEBUG_DATA__DATA__SHIFT 0x0
#define TD_DSM_CNTL__FORCE_SEDB_0_MASK 0x1
#define TD_DSM_CNTL__FORCE_SEDB_0__SHIFT 0x0
#define TD_DSM_CNTL__FORCE_SEDB_1_MASK 0x2
#define TD_DSM_CNTL__FORCE_SEDB_1__SHIFT 0x1
#define TD_DSM_CNTL__EN_SINGLE_WR_SEDB_MASK 0x4
#define TD_DSM_CNTL__EN_SINGLE_WR_SEDB__SHIFT 0x2
#define TD_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0xff
#define TD_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
#define TD_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x3fc00
#define TD_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
#define TD_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000
#define TD_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
#define TD_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0xf000000
#define TD_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18
#define TD_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xf0000000
#define TD_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c
#define TD_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0xff
#define TD_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
#define TD_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x3fc00
#define TD_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa
#define TD_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0xf00000
#define TD_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14
#define TD_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0xf000000
#define TD_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18
#define TD_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xf0000000
#define TD_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c
#define TD_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0xff
#define TD_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0
#define TD_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x3fc00
#define TD_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
#define TD_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0xf000000
#define TD_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18
#define TD_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xf0000000
#define TD_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c
#define TD_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff
#define TD_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
#define TD_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff
#define TD_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
#define TD_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff
#define TD_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
#define TD_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff
#define TD_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
#define TD_SCRATCH__SCRATCH_MASK 0xffffffff
#define TD_SCRATCH__SCRATCH__SHIFT 0x0
#define TA_CNTL__TC_DATA_CREDIT_MASK 0xe000
#define TA_CNTL__TC_DATA_CREDIT__SHIFT 0xd
#define TA_CNTL__ALIGNER_CREDIT_MASK 0x1f0000
#define TA_CNTL__ALIGNER_CREDIT__SHIFT 0x10
#define TA_CNTL__TD_FIFO_CREDIT_MASK 0xffc00000
#define TA_CNTL__TD_FIFO_CREDIT__SHIFT 0x16
#define TA_CNTL_AUX__SCOAL_DSWIZZLE_N_MASK 0x1
#define TA_CNTL_AUX__SCOAL_DSWIZZLE_N__SHIFT 0x0
#define TA_CNTL_AUX__RESERVED_MASK 0xe
#define TA_CNTL_AUX__RESERVED__SHIFT 0x1
#define TA_CNTL_AUX__ANISO_WEIGHT_MODE_MASK 0x10000
#define TA_CNTL_AUX__ANISO_WEIGHT_MODE__SHIFT 0x10
#define TA_CNTL_AUX__ANISO_RATIO_LUT_MASK 0x20000
#define TA_CNTL_AUX__ANISO_RATIO_LUT__SHIFT 0x11
#define TA_CNTL_AUX__ANISO_TAP_MASK 0x40000
#define TA_CNTL_AUX__ANISO_TAP__SHIFT 0x12
#define TA_CNTL_AUX__ANISO_MIP_ADJ_MODE_MASK 0x80000
#define TA_CNTL_AUX__ANISO_MIP_ADJ_MODE__SHIFT 0x13
#define TA_RESERVED_010C__Unused_MASK 0xffffffff
#define TA_RESERVED_010C__Unused__SHIFT 0x0
#define TA_CS_BC_BASE_ADDR__ADDRESS_MASK 0xffffffff
#define TA_CS_BC_BASE_ADDR__ADDRESS__SHIFT 0x0
#define TA_CS_BC_BASE_ADDR_HI__ADDRESS_MASK 0xff
#define TA_CS_BC_BASE_ADDR_HI__ADDRESS__SHIFT 0x0
#define TA_STATUS__FG_PFIFO_EMPTYB_MASK 0x1000
#define TA_STATUS__FG_PFIFO_EMPTYB__SHIFT 0xc
#define TA_STATUS__FG_LFIFO_EMPTYB_MASK 0x2000
#define TA_STATUS__FG_LFIFO_EMPTYB__SHIFT 0xd
#define TA_STATUS__FG_SFIFO_EMPTYB_MASK 0x4000
#define TA_STATUS__FG_SFIFO_EMPTYB__SHIFT 0xe
#define TA_STATUS__FL_PFIFO_EMPTYB_MASK 0x10000
#define TA_STATUS__FL_PFIFO_EMPTYB__SHIFT 0x10
#define TA_STATUS__FL_LFIFO_EMPTYB_MASK 0x20000
#define TA_STATUS__FL_LFIFO_EMPTYB__SHIFT 0x11
#define TA_STATUS__FL_SFIFO_EMPTYB_MASK 0x40000
#define TA_STATUS__FL_SFIFO_EMPTYB__SHIFT 0x12
#define TA_STATUS__FA_PFIFO_EMPTYB_MASK 0x100000
#define TA_STATUS__FA_PFIFO_EMPTYB__SHIFT 0x14
#define TA_STATUS__FA_LFIFO_EMPTYB_MASK 0x200000
#define TA_STATUS__FA_LFIFO_EMPTYB__SHIFT 0x15
#define TA_STATUS__FA_SFIFO_EMPTYB_MASK 0x400000
#define TA_STATUS__FA_SFIFO_EMPTYB__SHIFT 0x16
#define TA_STATUS__IN_BUSY_MASK 0x1000000
#define TA_STATUS__IN_BUSY__SHIFT 0x18
#define TA_STATUS__FG_BUSY_MASK 0x2000000
#define TA_STATUS__FG_BUSY__SHIFT 0x19
#define TA_STATUS__LA_BUSY_MASK 0x4000000
#define TA_STATUS__LA_BUSY__SHIFT 0x1a
#define TA_STATUS__FL_BUSY_MASK 0x8000000
#define TA_STATUS__FL_BUSY__SHIFT 0x1b
#define TA_STATUS__TA_BUSY_MASK 0x10000000
#define TA_STATUS__TA_BUSY__SHIFT 0x1c
#define TA_STATUS__FA_BUSY_MASK 0x20000000
#define TA_STATUS__FA_BUSY__SHIFT 0x1d
#define TA_STATUS__AL_BUSY_MASK 0x40000000
#define TA_STATUS__AL_BUSY__SHIFT 0x1e
#define TA_STATUS__BUSY_MASK 0x80000000
#define TA_STATUS__BUSY__SHIFT 0x1f
#define TA_DEBUG_INDEX__INDEX_MASK 0x1f
#define TA_DEBUG_INDEX__INDEX__SHIFT 0x0
#define TA_DEBUG_DATA__DATA_MASK 0xffffffff
#define TA_DEBUG_DATA__DATA__SHIFT 0x0
#define TA_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0xff
#define TA_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
#define TA_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x3fc00
#define TA_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
#define TA_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000
#define TA_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
#define TA_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0xf000000
#define TA_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18
#define TA_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xf0000000
#define TA_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c
#define TA_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0xff
#define TA_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
#define TA_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x3fc00
#define TA_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa
#define TA_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0xf00000
#define TA_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14
#define TA_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0xf000000
#define TA_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18
#define TA_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xf0000000
#define TA_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c
#define TA_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0xff
#define TA_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0
#define TA_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x3fc00
#define TA_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
#define TA_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0xf000000
#define TA_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18
#define TA_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xf0000000
#define TA_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c
#define TA_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff
#define TA_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
#define TA_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff
#define TA_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
#define TA_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff
#define TA_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
#define TA_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff
#define TA_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
#define TA_SCRATCH__SCRATCH_MASK 0xffffffff
#define TA_SCRATCH__SCRATCH__SHIFT 0x0
#define SH_HIDDEN_PRIVATE_BASE_VMID__ADDRESS_MASK 0xffffffff
#define SH_HIDDEN_PRIVATE_BASE_VMID__ADDRESS__SHIFT 0x0
#define SH_STATIC_MEM_CONFIG__SWIZZLE_ENABLE_MASK 0x1
#define SH_STATIC_MEM_CONFIG__SWIZZLE_ENABLE__SHIFT 0x0
#define SH_STATIC_MEM_CONFIG__ELEMENT_SIZE_MASK 0x6
#define SH_STATIC_MEM_CONFIG__ELEMENT_SIZE__SHIFT 0x1
#define SH_STATIC_MEM_CONFIG__INDEX_STRIDE_MASK 0x18
#define SH_STATIC_MEM_CONFIG__INDEX_STRIDE__SHIFT 0x3
#define SH_STATIC_MEM_CONFIG__PRIVATE_MTYPE_MASK 0xe0
#define SH_STATIC_MEM_CONFIG__PRIVATE_MTYPE__SHIFT 0x5
#define SH_STATIC_MEM_CONFIG__READ_ONLY_CNTL_MASK 0xff00
#define SH_STATIC_MEM_CONFIG__READ_ONLY_CNTL__SHIFT 0x8
#define TCP_INVALIDATE__START_MASK 0x1
#define TCP_INVALIDATE__START__SHIFT 0x0
#define TCP_STATUS__TCP_BUSY_MASK 0x1
#define TCP_STATUS__TCP_BUSY__SHIFT 0x0
#define TCP_STATUS__INPUT_BUSY_MASK 0x2
#define TCP_STATUS__INPUT_BUSY__SHIFT 0x1
#define TCP_STATUS__ADRS_BUSY_MASK 0x4
#define TCP_STATUS__ADRS_BUSY__SHIFT 0x2
#define TCP_STATUS__TAGRAMS_BUSY_MASK 0x8
#define TCP_STATUS__TAGRAMS_BUSY__SHIFT 0x3
#define TCP_STATUS__CNTRL_BUSY_MASK 0x10
#define TCP_STATUS__CNTRL_BUSY__SHIFT 0x4
#define TCP_STATUS__LFIFO_BUSY_MASK 0x20
#define TCP_STATUS__LFIFO_BUSY__SHIFT 0x5
#define TCP_STATUS__READ_BUSY_MASK 0x40
#define TCP_STATUS__READ_BUSY__SHIFT 0x6
#define TCP_STATUS__FORMAT_BUSY_MASK 0x80
#define TCP_STATUS__FORMAT_BUSY__SHIFT 0x7
#define TCP_CNTL__FORCE_HIT_MASK 0x1
#define TCP_CNTL__FORCE_HIT__SHIFT 0x0
#define TCP_CNTL__FORCE_MISS_MASK 0x2
#define TCP_CNTL__FORCE_MISS__SHIFT 0x1
#define TCP_CNTL__L1_SIZE_MASK 0xc
#define TCP_CNTL__L1_SIZE__SHIFT 0x2
#define TCP_CNTL__FLAT_BUF_HASH_ENABLE_MASK 0x10
#define TCP_CNTL__FLAT_BUF_HASH_ENABLE__SHIFT 0x4
#define TCP_CNTL__FLAT_BUF_CACHE_SWIZZLE_MASK 0x20
#define TCP_CNTL__FLAT_BUF_CACHE_SWIZZLE__SHIFT 0x5
#define TCP_CNTL__FORCE_EOW_TOTAL_CNT_MASK 0x1f8000
#define TCP_CNTL__FORCE_EOW_TOTAL_CNT__SHIFT 0xf
#define TCP_CNTL__FORCE_EOW_TAGRAM_CNT_MASK 0xfc00000
#define TCP_CNTL__FORCE_EOW_TAGRAM_CNT__SHIFT 0x16
#define TCP_CNTL__DISABLE_Z_MAP_MASK 0x10000000
#define TCP_CNTL__DISABLE_Z_MAP__SHIFT 0x1c
#define TCP_CNTL__INV_ALL_VMIDS_MASK 0x20000000
#define TCP_CNTL__INV_ALL_VMIDS__SHIFT 0x1d
#define TCP_CHAN_STEER_LO__CHAN0_MASK 0xf
#define TCP_CHAN_STEER_LO__CHAN0__SHIFT 0x0
#define TCP_CHAN_STEER_LO__CHAN1_MASK 0xf0
#define TCP_CHAN_STEER_LO__CHAN1__SHIFT 0x4
#define TCP_CHAN_STEER_LO__CHAN2_MASK 0xf00
#define TCP_CHAN_STEER_LO__CHAN2__SHIFT 0x8
#define TCP_CHAN_STEER_LO__CHAN3_MASK 0xf000
#define TCP_CHAN_STEER_LO__CHAN3__SHIFT 0xc
#define TCP_CHAN_STEER_LO__CHAN4_MASK 0xf0000
#define TCP_CHAN_STEER_LO__CHAN4__SHIFT 0x10
#define TCP_CHAN_STEER_LO__CHAN5_MASK 0xf00000
#define TCP_CHAN_STEER_LO__CHAN5__SHIFT 0x14
#define TCP_CHAN_STEER_LO__CHAN6_MASK 0xf000000
#define TCP_CHAN_STEER_LO__CHAN6__SHIFT 0x18
#define TCP_CHAN_STEER_LO__CHAN7_MASK 0xf0000000
#define TCP_CHAN_STEER_LO__CHAN7__SHIFT 0x1c
#define TCP_CHAN_STEER_HI__CHAN8_MASK 0xf
#define TCP_CHAN_STEER_HI__CHAN8__SHIFT 0x0
#define TCP_CHAN_STEER_HI__CHAN9_MASK 0xf0
#define TCP_CHAN_STEER_HI__CHAN9__SHIFT 0x4
#define TCP_CHAN_STEER_HI__CHANA_MASK 0xf00
#define TCP_CHAN_STEER_HI__CHANA__SHIFT 0x8
#define TCP_CHAN_STEER_HI__CHANB_MASK 0xf000
#define TCP_CHAN_STEER_HI__CHANB__SHIFT 0xc
#define TCP_CHAN_STEER_HI__CHANC_MASK 0xf0000
#define TCP_CHAN_STEER_HI__CHANC__SHIFT 0x10
#define TCP_CHAN_STEER_HI__CHAND_MASK 0xf00000
#define TCP_CHAN_STEER_HI__CHAND__SHIFT 0x14
#define TCP_CHAN_STEER_HI__CHANE_MASK 0xf000000
#define TCP_CHAN_STEER_HI__CHANE__SHIFT 0x18
#define TCP_CHAN_STEER_HI__CHANF_MASK 0xf0000000
#define TCP_CHAN_STEER_HI__CHANF__SHIFT 0x1c
#define TCP_ADDR_CONFIG__NUM_TCC_BANKS_MASK 0xf
#define TCP_ADDR_CONFIG__NUM_TCC_BANKS__SHIFT 0x0
#define TCP_ADDR_CONFIG__NUM_BANKS_MASK 0x30
#define TCP_ADDR_CONFIG__NUM_BANKS__SHIFT 0x4
#define TCP_ADDR_CONFIG__COLHI_WIDTH_MASK 0x1c0
#define TCP_ADDR_CONFIG__COLHI_WIDTH__SHIFT 0x6
#define TCP_ADDR_CONFIG__RB_SPLIT_COLHI_MASK 0x200
#define TCP_ADDR_CONFIG__RB_SPLIT_COLHI__SHIFT 0x9
#define TCP_CREDIT__LFIFO_CREDIT_MASK 0x3ff
#define TCP_CREDIT__LFIFO_CREDIT__SHIFT 0x0
#define TCP_CREDIT__REQ_FIFO_CREDIT_MASK 0x7f0000
#define TCP_CREDIT__REQ_FIFO_CREDIT__SHIFT 0x10
#define TCP_CREDIT__TD_CREDIT_MASK 0xe0000000
#define TCP_CREDIT__TD_CREDIT__SHIFT 0x1d
#define TCP_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x3ff
#define TCP_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
#define TCP_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0xffc00
#define TCP_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
#define TCP_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000
#define TCP_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
#define TCP_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0xf000000
#define TCP_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18
#define TCP_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xf0000000
#define TCP_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c
#define TCP_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x3ff
#define TCP_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
#define TCP_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0xffc00
#define TCP_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa
#define TCP_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0xf00000
#define TCP_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14
#define TCP_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0xf000000
#define TCP_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18
#define TCP_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xf0000000
#define TCP_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c
#define TCP_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x3ff
#define TCP_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0
#define TCP_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0xffc00
#define TCP_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
#define TCP_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0xf000000
#define TCP_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18
#define TCP_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xf0000000
#define TCP_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c
#define TCP_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x3ff
#define TCP_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0
#define TCP_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0xffc00
#define TCP_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa
#define TCP_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0xf000000
#define TCP_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x18
#define TCP_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0xf0000000
#define TCP_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x1c
#define TCP_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x3ff
#define TCP_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0
#define TCP_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0xf00000
#define TCP_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14
#define TCP_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xf0000000
#define TCP_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c
#define TCP_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x3ff
#define TCP_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0
#define TCP_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0xf00000
#define TCP_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14
#define TCP_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xf0000000
#define TCP_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c
#define TCP_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff
#define TCP_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
#define TCP_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff
#define TCP_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
#define TCP_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffff
#define TCP_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0
#define TCP_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffff
#define TCP_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0
#define TCP_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff
#define TCP_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
#define TCP_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff
#define TCP_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
#define TCP_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffff
#define TCP_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0
#define TCP_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffff
#define TCP_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0
#define TCP_BUFFER_ADDR_HASH_CNTL__CHANNEL_BITS_MASK 0x7
#define TCP_BUFFER_ADDR_HASH_CNTL__CHANNEL_BITS__SHIFT 0x0
#define TCP_BUFFER_ADDR_HASH_CNTL__BANK_BITS_MASK 0x700
#define TCP_BUFFER_ADDR_HASH_CNTL__BANK_BITS__SHIFT 0x8
#define TCP_BUFFER_ADDR_HASH_CNTL__CHANNEL_XOR_COUNT_MASK 0x70000
#define TCP_BUFFER_ADDR_HASH_CNTL__CHANNEL_XOR_COUNT__SHIFT 0x10
#define TCP_BUFFER_ADDR_HASH_CNTL__BANK_XOR_COUNT_MASK 0x7000000
#define TCP_BUFFER_ADDR_HASH_CNTL__BANK_XOR_COUNT__SHIFT 0x18
#define TCP_EDC_CNT__SEC_COUNT_MASK 0xff
#define TCP_EDC_CNT__SEC_COUNT__SHIFT 0x0
#define TCP_EDC_CNT__LFIFO_SED_COUNT_MASK 0xff00
#define TCP_EDC_CNT__LFIFO_SED_COUNT__SHIFT 0x8
#define TCP_EDC_CNT__DED_COUNT_MASK 0xff0000
#define TCP_EDC_CNT__DED_COUNT__SHIFT 0x10
#define TCP_EDC_CNT__UNUSED_MASK 0xff000000
#define TCP_EDC_CNT__UNUSED__SHIFT 0x18
#define TC_CFG_L1_LOAD_POLICY0__POLICY_0_MASK 0x3
#define TC_CFG_L1_LOAD_POLICY0__POLICY_0__SHIFT 0x0
#define TC_CFG_L1_LOAD_POLICY0__POLICY_1_MASK 0xc
#define TC_CFG_L1_LOAD_POLICY0__POLICY_1__SHIFT 0x2
#define TC_CFG_L1_LOAD_POLICY0__POLICY_2_MASK 0x30
#define TC_CFG_L1_LOAD_POLICY0__POLICY_2__SHIFT 0x4
#define TC_CFG_L1_LOAD_POLICY0__POLICY_3_MASK 0xc0
#define TC_CFG_L1_LOAD_POLICY0__POLICY_3__SHIFT 0x6
#define TC_CFG_L1_LOAD_POLICY0__POLICY_4_MASK 0x300
#define TC_CFG_L1_LOAD_POLICY0__POLICY_4__SHIFT 0x8
#define TC_CFG_L1_LOAD_POLICY0__POLICY_5_MASK 0xc00
#define TC_CFG_L1_LOAD_POLICY0__POLICY_5__SHIFT 0xa
#define TC_CFG_L1_LOAD_POLICY0__POLICY_6_MASK 0x3000
#define TC_CFG_L1_LOAD_POLICY0__POLICY_6__SHIFT 0xc
#define TC_CFG_L1_LOAD_POLICY0__POLICY_7_MASK 0xc000
#define TC_CFG_L1_LOAD_POLICY0__POLICY_7__SHIFT 0xe
#define TC_CFG_L1_LOAD_POLICY0__POLICY_8_MASK 0x30000
#define TC_CFG_L1_LOAD_POLICY0__POLICY_8__SHIFT 0x10
#define TC_CFG_L1_LOAD_POLICY0__POLICY_9_MASK 0xc0000
#define TC_CFG_L1_LOAD_POLICY0__POLICY_9__SHIFT 0x12
#define TC_CFG_L1_LOAD_POLICY0__POLICY_10_MASK 0x300000
#define TC_CFG_L1_LOAD_POLICY0__POLICY_10__SHIFT 0x14
#define TC_CFG_L1_LOAD_POLICY0__POLICY_11_MASK 0xc00000
#define TC_CFG_L1_LOAD_POLICY0__POLICY_11__SHIFT 0x16
#define TC_CFG_L1_LOAD_POLICY0__POLICY_12_MASK 0x3000000
#define TC_CFG_L1_LOAD_POLICY0__POLICY_12__SHIFT 0x18
#define TC_CFG_L1_LOAD_POLICY0__POLICY_13_MASK 0xc000000
#define TC_CFG_L1_LOAD_POLICY0__POLICY_13__SHIFT 0x1a
#define TC_CFG_L1_LOAD_POLICY0__POLICY_14_MASK 0x30000000
#define TC_CFG_L1_LOAD_POLICY0__POLICY_14__SHIFT 0x1c
#define TC_CFG_L1_LOAD_POLICY0__POLICY_15_MASK 0xc0000000
#define TC_CFG_L1_LOAD_POLICY0__POLICY_15__SHIFT 0x1e
#define TC_CFG_L1_LOAD_POLICY1__POLICY_16_MASK 0x3
#define TC_CFG_L1_LOAD_POLICY1__POLICY_16__SHIFT 0x0
#define TC_CFG_L1_LOAD_POLICY1__POLICY_17_MASK 0xc
#define TC_CFG_L1_LOAD_POLICY1__POLICY_17__SHIFT 0x2
#define TC_CFG_L1_LOAD_POLICY1__POLICY_18_MASK 0x30
#define TC_CFG_L1_LOAD_POLICY1__POLICY_18__SHIFT 0x4
#define TC_CFG_L1_LOAD_POLICY1__POLICY_19_MASK 0xc0
#define TC_CFG_L1_LOAD_POLICY1__POLICY_19__SHIFT 0x6
#define TC_CFG_L1_LOAD_POLICY1__POLICY_20_MASK 0x300
#define TC_CFG_L1_LOAD_POLICY1__POLICY_20__SHIFT 0x8
#define TC_CFG_L1_LOAD_POLICY1__POLICY_21_MASK 0xc00
#define TC_CFG_L1_LOAD_POLICY1__POLICY_21__SHIFT 0xa
#define TC_CFG_L1_LOAD_POLICY1__POLICY_22_MASK 0x3000
#define TC_CFG_L1_LOAD_POLICY1__POLICY_22__SHIFT 0xc
#define TC_CFG_L1_LOAD_POLICY1__POLICY_23_MASK 0xc000
#define TC_CFG_L1_LOAD_POLICY1__POLICY_23__SHIFT 0xe
#define TC_CFG_L1_LOAD_POLICY1__POLICY_24_MASK 0x30000
#define TC_CFG_L1_LOAD_POLICY1__POLICY_24__SHIFT 0x10
#define TC_CFG_L1_LOAD_POLICY1__POLICY_25_MASK 0xc0000
#define TC_CFG_L1_LOAD_POLICY1__POLICY_25__SHIFT 0x12
#define TC_CFG_L1_LOAD_POLICY1__POLICY_26_MASK 0x300000
#define TC_CFG_L1_LOAD_POLICY1__POLICY_26__SHIFT 0x14
#define TC_CFG_L1_LOAD_POLICY1__POLICY_27_MASK 0xc00000
#define TC_CFG_L1_LOAD_POLICY1__POLICY_27__SHIFT 0x16
#define TC_CFG_L1_LOAD_POLICY1__POLICY_28_MASK 0x3000000
#define TC_CFG_L1_LOAD_POLICY1__POLICY_28__SHIFT 0x18
#define TC_CFG_L1_LOAD_POLICY1__POLICY_29_MASK 0xc000000
#define TC_CFG_L1_LOAD_POLICY1__POLICY_29__SHIFT 0x1a
#define TC_CFG_L1_LOAD_POLICY1__POLICY_30_MASK 0x30000000
#define TC_CFG_L1_LOAD_POLICY1__POLICY_30__SHIFT 0x1c
#define TC_CFG_L1_LOAD_POLICY1__POLICY_31_MASK 0xc0000000
#define TC_CFG_L1_LOAD_POLICY1__POLICY_31__SHIFT 0x1e
#define TC_CFG_L1_STORE_POLICY__POLICY_0_MASK 0x1
#define TC_CFG_L1_STORE_POLICY__POLICY_0__SHIFT 0x0
#define TC_CFG_L1_STORE_POLICY__POLICY_1_MASK 0x2
#define TC_CFG_L1_STORE_POLICY__POLICY_1__SHIFT 0x1
#define TC_CFG_L1_STORE_POLICY__POLICY_2_MASK 0x4
#define TC_CFG_L1_STORE_POLICY__POLICY_2__SHIFT 0x2
#define TC_CFG_L1_STORE_POLICY__POLICY_3_MASK 0x8
#define TC_CFG_L1_STORE_POLICY__POLICY_3__SHIFT 0x3
#define TC_CFG_L1_STORE_POLICY__POLICY_4_MASK 0x10
#define TC_CFG_L1_STORE_POLICY__POLICY_4__SHIFT 0x4
#define TC_CFG_L1_STORE_POLICY__POLICY_5_MASK 0x20
#define TC_CFG_L1_STORE_POLICY__POLICY_5__SHIFT 0x5
#define TC_CFG_L1_STORE_POLICY__POLICY_6_MASK 0x40
#define TC_CFG_L1_STORE_POLICY__POLICY_6__SHIFT 0x6
#define TC_CFG_L1_STORE_POLICY__POLICY_7_MASK 0x80
#define TC_CFG_L1_STORE_POLICY__POLICY_7__SHIFT 0x7
#define TC_CFG_L1_STORE_POLICY__POLICY_8_MASK 0x100
#define TC_CFG_L1_STORE_POLICY__POLICY_8__SHIFT 0x8
#define TC_CFG_L1_STORE_POLICY__POLICY_9_MASK 0x200
#define TC_CFG_L1_STORE_POLICY__POLICY_9__SHIFT 0x9
#define TC_CFG_L1_STORE_POLICY__POLICY_10_MASK 0x400
#define TC_CFG_L1_STORE_POLICY__POLICY_10__SHIFT 0xa
#define TC_CFG_L1_STORE_POLICY__POLICY_11_MASK 0x800
#define TC_CFG_L1_STORE_POLICY__POLICY_11__SHIFT 0xb
#define TC_CFG_L1_STORE_POLICY__POLICY_12_MASK 0x1000
#define TC_CFG_L1_STORE_POLICY__POLICY_12__SHIFT 0xc
#define TC_CFG_L1_STORE_POLICY__POLICY_13_MASK 0x2000
#define TC_CFG_L1_STORE_POLICY__POLICY_13__SHIFT 0xd
#define TC_CFG_L1_STORE_POLICY__POLICY_14_MASK 0x4000
#define TC_CFG_L1_STORE_POLICY__POLICY_14__SHIFT 0xe
#define TC_CFG_L1_STORE_POLICY__POLICY_15_MASK 0x8000
#define TC_CFG_L1_STORE_POLICY__POLICY_15__SHIFT 0xf
#define TC_CFG_L1_STORE_POLICY__POLICY_16_MASK 0x10000
#define TC_CFG_L1_STORE_POLICY__POLICY_16__SHIFT 0x10
#define TC_CFG_L1_STORE_POLICY__POLICY_17_MASK 0x20000
#define TC_CFG_L1_STORE_POLICY__POLICY_17__SHIFT 0x11
#define TC_CFG_L1_STORE_POLICY__POLICY_18_MASK 0x40000
#define TC_CFG_L1_STORE_POLICY__POLICY_18__SHIFT 0x12
#define TC_CFG_L1_STORE_POLICY__POLICY_19_MASK 0x80000
#define TC_CFG_L1_STORE_POLICY__POLICY_19__SHIFT 0x13
#define TC_CFG_L1_STORE_POLICY__POLICY_20_MASK 0x100000
#define TC_CFG_L1_STORE_POLICY__POLICY_20__SHIFT 0x14
#define TC_CFG_L1_STORE_POLICY__POLICY_21_MASK 0x200000
#define TC_CFG_L1_STORE_POLICY__POLICY_21__SHIFT 0x15
#define TC_CFG_L1_STORE_POLICY__POLICY_22_MASK 0x400000
#define TC_CFG_L1_STORE_POLICY__POLICY_22__SHIFT 0x16
#define TC_CFG_L1_STORE_POLICY__POLICY_23_MASK 0x800000
#define TC_CFG_L1_STORE_POLICY__POLICY_23__SHIFT 0x17
#define TC_CFG_L1_STORE_POLICY__POLICY_24_MASK 0x1000000
#define TC_CFG_L1_STORE_POLICY__POLICY_24__SHIFT 0x18
#define TC_CFG_L1_STORE_POLICY__POLICY_25_MASK 0x2000000
#define TC_CFG_L1_STORE_POLICY__POLICY_25__SHIFT 0x19
#define TC_CFG_L1_STORE_POLICY__POLICY_26_MASK 0x4000000
#define TC_CFG_L1_STORE_POLICY__POLICY_26__SHIFT 0x1a
#define TC_CFG_L1_STORE_POLICY__POLICY_27_MASK 0x8000000
#define TC_CFG_L1_STORE_POLICY__POLICY_27__SHIFT 0x1b
#define TC_CFG_L1_STORE_POLICY__POLICY_28_MASK 0x10000000
#define TC_CFG_L1_STORE_POLICY__POLICY_28__SHIFT 0x1c
#define TC_CFG_L1_STORE_POLICY__POLICY_29_MASK 0x20000000
#define TC_CFG_L1_STORE_POLICY__POLICY_29__SHIFT 0x1d
#define TC_CFG_L1_STORE_POLICY__POLICY_30_MASK 0x40000000
#define TC_CFG_L1_STORE_POLICY__POLICY_30__SHIFT 0x1e
#define TC_CFG_L1_STORE_POLICY__POLICY_31_MASK 0x80000000
#define TC_CFG_L1_STORE_POLICY__POLICY_31__SHIFT 0x1f
#define TC_CFG_L2_LOAD_POLICY0__POLICY_0_MASK 0x3
#define TC_CFG_L2_LOAD_POLICY0__POLICY_0__SHIFT 0x0
#define TC_CFG_L2_LOAD_POLICY0__POLICY_1_MASK 0xc
#define TC_CFG_L2_LOAD_POLICY0__POLICY_1__SHIFT 0x2
#define TC_CFG_L2_LOAD_POLICY0__POLICY_2_MASK 0x30
#define TC_CFG_L2_LOAD_POLICY0__POLICY_2__SHIFT 0x4
#define TC_CFG_L2_LOAD_POLICY0__POLICY_3_MASK 0xc0
#define TC_CFG_L2_LOAD_POLICY0__POLICY_3__SHIFT 0x6
#define TC_CFG_L2_LOAD_POLICY0__POLICY_4_MASK 0x300
#define TC_CFG_L2_LOAD_POLICY0__POLICY_4__SHIFT 0x8
#define TC_CFG_L2_LOAD_POLICY0__POLICY_5_MASK 0xc00
#define TC_CFG_L2_LOAD_POLICY0__POLICY_5__SHIFT 0xa
#define TC_CFG_L2_LOAD_POLICY0__POLICY_6_MASK 0x3000
#define TC_CFG_L2_LOAD_POLICY0__POLICY_6__SHIFT 0xc
#define TC_CFG_L2_LOAD_POLICY0__POLICY_7_MASK 0xc000
#define TC_CFG_L2_LOAD_POLICY0__POLICY_7__SHIFT 0xe
#define TC_CFG_L2_LOAD_POLICY0__POLICY_8_MASK 0x30000
#define TC_CFG_L2_LOAD_POLICY0__POLICY_8__SHIFT 0x10
#define TC_CFG_L2_LOAD_POLICY0__POLICY_9_MASK 0xc0000
#define TC_CFG_L2_LOAD_POLICY0__POLICY_9__SHIFT 0x12
#define TC_CFG_L2_LOAD_POLICY0__POLICY_10_MASK 0x300000
#define TC_CFG_L2_LOAD_POLICY0__POLICY_10__SHIFT 0x14
#define TC_CFG_L2_LOAD_POLICY0__POLICY_11_MASK 0xc00000
#define TC_CFG_L2_LOAD_POLICY0__POLICY_11__SHIFT 0x16
#define TC_CFG_L2_LOAD_POLICY0__POLICY_12_MASK 0x3000000
#define TC_CFG_L2_LOAD_POLICY0__POLICY_12__SHIFT 0x18
#define TC_CFG_L2_LOAD_POLICY0__POLICY_13_MASK 0xc000000
#define TC_CFG_L2_LOAD_POLICY0__POLICY_13__SHIFT 0x1a
#define TC_CFG_L2_LOAD_POLICY0__POLICY_14_MASK 0x30000000
#define TC_CFG_L2_LOAD_POLICY0__POLICY_14__SHIFT 0x1c
#define TC_CFG_L2_LOAD_POLICY0__POLICY_15_MASK 0xc0000000
#define TC_CFG_L2_LOAD_POLICY0__POLICY_15__SHIFT 0x1e
#define TC_CFG_L2_LOAD_POLICY1__POLICY_16_MASK 0x3
#define TC_CFG_L2_LOAD_POLICY1__POLICY_16__SHIFT 0x0
#define TC_CFG_L2_LOAD_POLICY1__POLICY_17_MASK 0xc
#define TC_CFG_L2_LOAD_POLICY1__POLICY_17__SHIFT 0x2
#define TC_CFG_L2_LOAD_POLICY1__POLICY_18_MASK 0x30
#define TC_CFG_L2_LOAD_POLICY1__POLICY_18__SHIFT 0x4
#define TC_CFG_L2_LOAD_POLICY1__POLICY_19_MASK 0xc0
#define TC_CFG_L2_LOAD_POLICY1__POLICY_19__SHIFT 0x6
#define TC_CFG_L2_LOAD_POLICY1__POLICY_20_MASK 0x300
#define TC_CFG_L2_LOAD_POLICY1__POLICY_20__SHIFT 0x8
#define TC_CFG_L2_LOAD_POLICY1__POLICY_21_MASK 0xc00
#define TC_CFG_L2_LOAD_POLICY1__POLICY_21__SHIFT 0xa
#define TC_CFG_L2_LOAD_POLICY1__POLICY_22_MASK 0x3000
#define TC_CFG_L2_LOAD_POLICY1__POLICY_22__SHIFT 0xc
#define TC_CFG_L2_LOAD_POLICY1__POLICY_23_MASK 0xc000
#define TC_CFG_L2_LOAD_POLICY1__POLICY_23__SHIFT 0xe
#define TC_CFG_L2_LOAD_POLICY1__POLICY_24_MASK 0x30000
#define TC_CFG_L2_LOAD_POLICY1__POLICY_24__SHIFT 0x10
#define TC_CFG_L2_LOAD_POLICY1__POLICY_25_MASK 0xc0000
#define TC_CFG_L2_LOAD_POLICY1__POLICY_25__SHIFT 0x12
#define TC_CFG_L2_LOAD_POLICY1__POLICY_26_MASK 0x300000
#define TC_CFG_L2_LOAD_POLICY1__POLICY_26__SHIFT 0x14
#define TC_CFG_L2_LOAD_POLICY1__POLICY_27_MASK 0xc00000
#define TC_CFG_L2_LOAD_POLICY1__POLICY_27__SHIFT 0x16
#define TC_CFG_L2_LOAD_POLICY1__POLICY_28_MASK 0x3000000
#define TC_CFG_L2_LOAD_POLICY1__POLICY_28__SHIFT 0x18
#define TC_CFG_L2_LOAD_POLICY1__POLICY_29_MASK 0xc000000
#define TC_CFG_L2_LOAD_POLICY1__POLICY_29__SHIFT 0x1a
#define TC_CFG_L2_LOAD_POLICY1__POLICY_30_MASK 0x30000000
#define TC_CFG_L2_LOAD_POLICY1__POLICY_30__SHIFT 0x1c
#define TC_CFG_L2_LOAD_POLICY1__POLICY_31_MASK 0xc0000000
#define TC_CFG_L2_LOAD_POLICY1__POLICY_31__SHIFT 0x1e
#define TC_CFG_L2_STORE_POLICY0__POLICY_0_MASK 0x3
#define TC_CFG_L2_STORE_POLICY0__POLICY_0__SHIFT 0x0
#define TC_CFG_L2_STORE_POLICY0__POLICY_1_MASK 0xc
#define TC_CFG_L2_STORE_POLICY0__POLICY_1__SHIFT 0x2
#define TC_CFG_L2_STORE_POLICY0__POLICY_2_MASK 0x30
#define TC_CFG_L2_STORE_POLICY0__POLICY_2__SHIFT 0x4
#define TC_CFG_L2_STORE_POLICY0__POLICY_3_MASK 0xc0
#define TC_CFG_L2_STORE_POLICY0__POLICY_3__SHIFT 0x6
#define TC_CFG_L2_STORE_POLICY0__POLICY_4_MASK 0x300
#define TC_CFG_L2_STORE_POLICY0__POLICY_4__SHIFT 0x8
#define TC_CFG_L2_STORE_POLICY0__POLICY_5_MASK 0xc00
#define TC_CFG_L2_STORE_POLICY0__POLICY_5__SHIFT 0xa
#define TC_CFG_L2_STORE_POLICY0__POLICY_6_MASK 0x3000
#define TC_CFG_L2_STORE_POLICY0__POLICY_6__SHIFT 0xc
#define TC_CFG_L2_STORE_POLICY0__POLICY_7_MASK 0xc000
#define TC_CFG_L2_STORE_POLICY0__POLICY_7__SHIFT 0xe
#define TC_CFG_L2_STORE_POLICY0__POLICY_8_MASK 0x30000
#define TC_CFG_L2_STORE_POLICY0__POLICY_8__SHIFT 0x10
#define TC_CFG_L2_STORE_POLICY0__POLICY_9_MASK 0xc0000
#define TC_CFG_L2_STORE_POLICY0__POLICY_9__SHIFT 0x12
#define TC_CFG_L2_STORE_POLICY0__POLICY_10_MASK 0x300000
#define TC_CFG_L2_STORE_POLICY0__POLICY_10__SHIFT 0x14
#define TC_CFG_L2_STORE_POLICY0__POLICY_11_MASK 0xc00000
#define TC_CFG_L2_STORE_POLICY0__POLICY_11__SHIFT 0x16
#define TC_CFG_L2_STORE_POLICY0__POLICY_12_MASK 0x3000000
#define TC_CFG_L2_STORE_POLICY0__POLICY_12__SHIFT 0x18
#define TC_CFG_L2_STORE_POLICY0__POLICY_13_MASK 0xc000000
#define TC_CFG_L2_STORE_POLICY0__POLICY_13__SHIFT 0x1a
#define TC_CFG_L2_STORE_POLICY0__POLICY_14_MASK 0x30000000
#define TC_CFG_L2_STORE_POLICY0__POLICY_14__SHIFT 0x1c
#define TC_CFG_L2_STORE_POLICY0__POLICY_15_MASK 0xc0000000
#define TC_CFG_L2_STORE_POLICY0__POLICY_15__SHIFT 0x1e
#define TC_CFG_L2_STORE_POLICY1__POLICY_16_MASK 0x3
#define TC_CFG_L2_STORE_POLICY1__POLICY_16__SHIFT 0x0
#define TC_CFG_L2_STORE_POLICY1__POLICY_17_MASK 0xc
#define TC_CFG_L2_STORE_POLICY1__POLICY_17__SHIFT 0x2
#define TC_CFG_L2_STORE_POLICY1__POLICY_18_MASK 0x30
#define TC_CFG_L2_STORE_POLICY1__POLICY_18__SHIFT 0x4
#define TC_CFG_L2_STORE_POLICY1__POLICY_19_MASK 0xc0
#define TC_CFG_L2_STORE_POLICY1__POLICY_19__SHIFT 0x6
#define TC_CFG_L2_STORE_POLICY1__POLICY_20_MASK 0x300
#define TC_CFG_L2_STORE_POLICY1__POLICY_20__SHIFT 0x8
#define TC_CFG_L2_STORE_POLICY1__POLICY_21_MASK 0xc00
#define TC_CFG_L2_STORE_POLICY1__POLICY_21__SHIFT 0xa
#define TC_CFG_L2_STORE_POLICY1__POLICY_22_MASK 0x3000
#define TC_CFG_L2_STORE_POLICY1__POLICY_22__SHIFT 0xc
#define TC_CFG_L2_STORE_POLICY1__POLICY_23_MASK 0xc000
#define TC_CFG_L2_STORE_POLICY1__POLICY_23__SHIFT 0xe
#define TC_CFG_L2_STORE_POLICY1__POLICY_24_MASK 0x30000
#define TC_CFG_L2_STORE_POLICY1__POLICY_24__SHIFT 0x10
#define TC_CFG_L2_STORE_POLICY1__POLICY_25_MASK 0xc0000
#define TC_CFG_L2_STORE_POLICY1__POLICY_25__SHIFT 0x12
#define TC_CFG_L2_STORE_POLICY1__POLICY_26_MASK 0x300000
#define TC_CFG_L2_STORE_POLICY1__POLICY_26__SHIFT 0x14
#define TC_CFG_L2_STORE_POLICY1__POLICY_27_MASK 0xc00000
#define TC_CFG_L2_STORE_POLICY1__POLICY_27__SHIFT 0x16
#define TC_CFG_L2_STORE_POLICY1__POLICY_28_MASK 0x3000000
#define TC_CFG_L2_STORE_POLICY1__POLICY_28__SHIFT 0x18
#define TC_CFG_L2_STORE_POLICY1__POLICY_29_MASK 0xc000000
#define TC_CFG_L2_STORE_POLICY1__POLICY_29__SHIFT 0x1a
#define TC_CFG_L2_STORE_POLICY1__POLICY_30_MASK 0x30000000
#define TC_CFG_L2_STORE_POLICY1__POLICY_30__SHIFT 0x1c
#define TC_CFG_L2_STORE_POLICY1__POLICY_31_MASK 0xc0000000
#define TC_CFG_L2_STORE_POLICY1__POLICY_31__SHIFT 0x1e
#define TC_CFG_L2_ATOMIC_POLICY__POLICY_0_MASK 0x3
#define TC_CFG_L2_ATOMIC_POLICY__POLICY_0__SHIFT 0x0
#define TC_CFG_L2_ATOMIC_POLICY__POLICY_1_MASK 0xc
#define TC_CFG_L2_ATOMIC_POLICY__POLICY_1__SHIFT 0x2
#define TC_CFG_L2_ATOMIC_POLICY__POLICY_2_MASK 0x30
#define TC_CFG_L2_ATOMIC_POLICY__POLICY_2__SHIFT 0x4
#define TC_CFG_L2_ATOMIC_POLICY__POLICY_3_MASK 0xc0
#define TC_CFG_L2_ATOMIC_POLICY__POLICY_3__SHIFT 0x6
#define TC_CFG_L2_ATOMIC_POLICY__POLICY_4_MASK 0x300
#define TC_CFG_L2_ATOMIC_POLICY__POLICY_4__SHIFT 0x8
#define TC_CFG_L2_ATOMIC_POLICY__POLICY_5_MASK 0xc00
#define TC_CFG_L2_ATOMIC_POLICY__POLICY_5__SHIFT 0xa
#define TC_CFG_L2_ATOMIC_POLICY__POLICY_6_MASK 0x3000
#define TC_CFG_L2_ATOMIC_POLICY__POLICY_6__SHIFT 0xc
#define TC_CFG_L2_ATOMIC_POLICY__POLICY_7_MASK 0xc000
#define TC_CFG_L2_ATOMIC_POLICY__POLICY_7__SHIFT 0xe
#define TC_CFG_L2_ATOMIC_POLICY__POLICY_8_MASK 0x30000
#define TC_CFG_L2_ATOMIC_POLICY__POLICY_8__SHIFT 0x10
#define TC_CFG_L2_ATOMIC_POLICY__POLICY_9_MASK 0xc0000
#define TC_CFG_L2_ATOMIC_POLICY__POLICY_9__SHIFT 0x12
#define TC_CFG_L2_ATOMIC_POLICY__POLICY_10_MASK 0x300000
#define TC_CFG_L2_ATOMIC_POLICY__POLICY_10__SHIFT 0x14
#define TC_CFG_L2_ATOMIC_POLICY__POLICY_11_MASK 0xc00000
#define TC_CFG_L2_ATOMIC_POLICY__POLICY_11__SHIFT 0x16
#define TC_CFG_L2_ATOMIC_POLICY__POLICY_12_MASK 0x3000000
#define TC_CFG_L2_ATOMIC_POLICY__POLICY_12__SHIFT 0x18
#define TC_CFG_L2_ATOMIC_POLICY__POLICY_13_MASK 0xc000000
#define TC_CFG_L2_ATOMIC_POLICY__POLICY_13__SHIFT 0x1a
#define TC_CFG_L2_ATOMIC_POLICY__POLICY_14_MASK 0x30000000
#define TC_CFG_L2_ATOMIC_POLICY__POLICY_14__SHIFT 0x1c
#define TC_CFG_L2_ATOMIC_POLICY__POLICY_15_MASK 0xc0000000
#define TC_CFG_L2_ATOMIC_POLICY__POLICY_15__SHIFT 0x1e
#define TC_CFG_L1_VOLATILE__VOL_MASK 0xf
#define TC_CFG_L1_VOLATILE__VOL__SHIFT 0x0
#define TC_CFG_L2_VOLATILE__VOL_MASK 0xf
#define TC_CFG_L2_VOLATILE__VOL__SHIFT 0x0
#define TCP_WATCH0_ADDR_H__ADDR_MASK 0xffff
#define TCP_WATCH0_ADDR_H__ADDR__SHIFT 0x0
#define TCP_WATCH1_ADDR_H__ADDR_MASK 0xffff
#define TCP_WATCH1_ADDR_H__ADDR__SHIFT 0x0
#define TCP_WATCH2_ADDR_H__ADDR_MASK 0xffff
#define TCP_WATCH2_ADDR_H__ADDR__SHIFT 0x0
#define TCP_WATCH3_ADDR_H__ADDR_MASK 0xffff
#define TCP_WATCH3_ADDR_H__ADDR__SHIFT 0x0
#define TCP_WATCH0_ADDR_L__ADDR_MASK 0xffffffc0
#define TCP_WATCH0_ADDR_L__ADDR__SHIFT 0x6
#define TCP_WATCH1_ADDR_L__ADDR_MASK 0xffffffc0
#define TCP_WATCH1_ADDR_L__ADDR__SHIFT 0x6
#define TCP_WATCH2_ADDR_L__ADDR_MASK 0xffffffc0
#define TCP_WATCH2_ADDR_L__ADDR__SHIFT 0x6
#define TCP_WATCH3_ADDR_L__ADDR_MASK 0xffffffc0
#define TCP_WATCH3_ADDR_L__ADDR__SHIFT 0x6
#define TCP_WATCH0_CNTL__MASK_MASK 0xffffff
#define TCP_WATCH0_CNTL__MASK__SHIFT 0x0
#define TCP_WATCH0_CNTL__VMID_MASK 0xf000000
#define TCP_WATCH0_CNTL__VMID__SHIFT 0x18
#define TCP_WATCH0_CNTL__MODE_MASK 0x60000000
#define TCP_WATCH0_CNTL__MODE__SHIFT 0x1d
#define TCP_WATCH0_CNTL__VALID_MASK 0x80000000
#define TCP_WATCH0_CNTL__VALID__SHIFT 0x1f
#define TCP_WATCH1_CNTL__MASK_MASK 0xffffff
#define TCP_WATCH1_CNTL__MASK__SHIFT 0x0
#define TCP_WATCH1_CNTL__VMID_MASK 0xf000000
#define TCP_WATCH1_CNTL__VMID__SHIFT 0x18
#define TCP_WATCH1_CNTL__MODE_MASK 0x60000000
#define TCP_WATCH1_CNTL__MODE__SHIFT 0x1d
#define TCP_WATCH1_CNTL__VALID_MASK 0x80000000
#define TCP_WATCH1_CNTL__VALID__SHIFT 0x1f
#define TCP_WATCH2_CNTL__MASK_MASK 0xffffff
#define TCP_WATCH2_CNTL__MASK__SHIFT 0x0
#define TCP_WATCH2_CNTL__VMID_MASK 0xf000000
#define TCP_WATCH2_CNTL__VMID__SHIFT 0x18
#define TCP_WATCH2_CNTL__MODE_MASK 0x60000000
#define TCP_WATCH2_CNTL__MODE__SHIFT 0x1d
#define TCP_WATCH2_CNTL__VALID_MASK 0x80000000
#define TCP_WATCH2_CNTL__VALID__SHIFT 0x1f
#define TCP_WATCH3_CNTL__MASK_MASK 0xffffff
#define TCP_WATCH3_CNTL__MASK__SHIFT 0x0
#define TCP_WATCH3_CNTL__VMID_MASK 0xf000000
#define TCP_WATCH3_CNTL__VMID__SHIFT 0x18
#define TCP_WATCH3_CNTL__MODE_MASK 0x60000000
#define TCP_WATCH3_CNTL__MODE__SHIFT 0x1d
#define TCP_WATCH3_CNTL__VALID_MASK 0x80000000
#define TCP_WATCH3_CNTL__VALID__SHIFT 0x1f
#define TCP_GATCL1_CNTL__INVALIDATE_ALL_VMID_MASK 0x2000000
#define TCP_GATCL1_CNTL__INVALIDATE_ALL_VMID__SHIFT 0x19
#define TCP_GATCL1_CNTL__FORCE_MISS_MASK 0x4000000
#define TCP_GATCL1_CNTL__FORCE_MISS__SHIFT 0x1a
#define TCP_GATCL1_CNTL__FORCE_IN_ORDER_MASK 0x8000000
#define TCP_GATCL1_CNTL__FORCE_IN_ORDER__SHIFT 0x1b
#define TCP_GATCL1_CNTL__REDUCE_FIFO_DEPTH_BY_2_MASK 0x30000000
#define TCP_GATCL1_CNTL__REDUCE_FIFO_DEPTH_BY_2__SHIFT 0x1c
#define TCP_GATCL1_CNTL__REDUCE_CACHE_SIZE_BY_2_MASK 0xc0000000
#define TCP_GATCL1_CNTL__REDUCE_CACHE_SIZE_BY_2__SHIFT 0x1e
#define TCP_ATC_EDC_GATCL1_CNT__DATA_SEC_MASK 0xff
#define TCP_ATC_EDC_GATCL1_CNT__DATA_SEC__SHIFT 0x0
#define TCP_GATCL1_DSM_CNTL__SEL_DSM_TCP_GATCL1_IRRITATOR_DATA_A0_MASK 0x1
#define TCP_GATCL1_DSM_CNTL__SEL_DSM_TCP_GATCL1_IRRITATOR_DATA_A0__SHIFT 0x0
#define TCP_GATCL1_DSM_CNTL__SEL_DSM_TCP_GATCL1_IRRITATOR_DATA_A1_MASK 0x2
#define TCP_GATCL1_DSM_CNTL__SEL_DSM_TCP_GATCL1_IRRITATOR_DATA_A1__SHIFT 0x1
#define TCP_GATCL1_DSM_CNTL__TCP_GATCL1_ENABLE_SINGLE_WRITE_A_MASK 0x4
#define TCP_GATCL1_DSM_CNTL__TCP_GATCL1_ENABLE_SINGLE_WRITE_A__SHIFT 0x2
#define TCP_DSM_CNTL__CACHE_RAM_IRRITATOR_DATA_SEL_MASK 0x3
#define TCP_DSM_CNTL__CACHE_RAM_IRRITATOR_DATA_SEL__SHIFT 0x0
#define TCP_DSM_CNTL__CACHE_RAM_IRRITATOR_SINGLE_WRITE_MASK 0x4
#define TCP_DSM_CNTL__CACHE_RAM_IRRITATOR_SINGLE_WRITE__SHIFT 0x2
#define TCP_DSM_CNTL__LFIFO_RAM_IRRITATOR_DATA_SEL_MASK 0x18
#define TCP_DSM_CNTL__LFIFO_RAM_IRRITATOR_DATA_SEL__SHIFT 0x3
#define TCP_DSM_CNTL__LFIFO_RAM_IRRITATOR_SINGLE_WRITE_MASK 0x20
#define TCP_DSM_CNTL__LFIFO_RAM_IRRITATOR_SINGLE_WRITE__SHIFT 0x5
#define TCP_CNTL2__LS_DISABLE_CLOCKS_MASK 0xff
#define TCP_CNTL2__LS_DISABLE_CLOCKS__SHIFT 0x0
#define TD_CGTT_CTRL__ON_DELAY_MASK 0xf
#define TD_CGTT_CTRL__ON_DELAY__SHIFT 0x0
#define TD_CGTT_CTRL__OFF_HYSTERESIS_MASK 0xff0
#define TD_CGTT_CTRL__OFF_HYSTERESIS__SHIFT 0x4
#define TD_CGTT_CTRL__SOFT_OVERRIDE7_MASK 0x1000000
#define TD_CGTT_CTRL__SOFT_OVERRIDE7__SHIFT 0x18
#define TD_CGTT_CTRL__SOFT_OVERRIDE6_MASK 0x2000000
#define TD_CGTT_CTRL__SOFT_OVERRIDE6__SHIFT 0x19
#define TD_CGTT_CTRL__SOFT_OVERRIDE5_MASK 0x4000000
#define TD_CGTT_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a
#define TD_CGTT_CTRL__SOFT_OVERRIDE4_MASK 0x8000000
#define TD_CGTT_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b
#define TD_CGTT_CTRL__SOFT_OVERRIDE3_MASK 0x10000000
#define TD_CGTT_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c
#define TD_CGTT_CTRL__SOFT_OVERRIDE2_MASK 0x20000000
#define TD_CGTT_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d
#define TD_CGTT_CTRL__SOFT_OVERRIDE1_MASK 0x40000000
#define TD_CGTT_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e
#define TD_CGTT_CTRL__SOFT_OVERRIDE0_MASK 0x80000000
#define TD_CGTT_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f
#define TA_CGTT_CTRL__ON_DELAY_MASK 0xf
#define TA_CGTT_CTRL__ON_DELAY__SHIFT 0x0
#define TA_CGTT_CTRL__OFF_HYSTERESIS_MASK 0xff0
#define TA_CGTT_CTRL__OFF_HYSTERESIS__SHIFT 0x4
#define TA_CGTT_CTRL__SOFT_OVERRIDE7_MASK 0x1000000
#define TA_CGTT_CTRL__SOFT_OVERRIDE7__SHIFT 0x18
#define TA_CGTT_CTRL__SOFT_OVERRIDE6_MASK 0x2000000
#define TA_CGTT_CTRL__SOFT_OVERRIDE6__SHIFT 0x19
#define TA_CGTT_CTRL__SOFT_OVERRIDE5_MASK 0x4000000
#define TA_CGTT_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a
#define TA_CGTT_CTRL__SOFT_OVERRIDE4_MASK 0x8000000
#define TA_CGTT_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b
#define TA_CGTT_CTRL__SOFT_OVERRIDE3_MASK 0x10000000
#define TA_CGTT_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c
#define TA_CGTT_CTRL__SOFT_OVERRIDE2_MASK 0x20000000
#define TA_CGTT_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d
#define TA_CGTT_CTRL__SOFT_OVERRIDE1_MASK 0x40000000
#define TA_CGTT_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e
#define TA_CGTT_CTRL__SOFT_OVERRIDE0_MASK 0x80000000
#define TA_CGTT_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f
#define CGTT_TCP_CLK_CTRL__ON_DELAY_MASK 0xf
#define CGTT_TCP_CLK_CTRL__ON_DELAY__SHIFT 0x0
#define CGTT_TCP_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0
#define CGTT_TCP_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x1000000
#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18
#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x2000000
#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19
#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x4000000
#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a
#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x8000000
#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b
#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000
#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c
#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000
#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d
#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000
#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e
#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000
#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f
#define CGTT_TCI_CLK_CTRL__ON_DELAY_MASK 0xf
#define CGTT_TCI_CLK_CTRL__ON_DELAY__SHIFT 0x0
#define CGTT_TCI_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0
#define CGTT_TCI_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x1000000
#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18
#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x2000000
#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19
#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x4000000
#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a
#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x8000000
#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b
#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000
#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c
#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000
#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d
#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000
#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e
#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000
#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f
#define TCI_STATUS__TCI_BUSY_MASK 0x1
#define TCI_STATUS__TCI_BUSY__SHIFT 0x0
#define TCI_CNTL_1__WBINVL1_NUM_CYCLES_MASK 0xffff
#define TCI_CNTL_1__WBINVL1_NUM_CYCLES__SHIFT 0x0
#define TCI_CNTL_1__REQ_FIFO_DEPTH_MASK 0xff0000
#define TCI_CNTL_1__REQ_FIFO_DEPTH__SHIFT 0x10
#define TCI_CNTL_1__WDATA_RAM_DEPTH_MASK 0xff000000
#define TCI_CNTL_1__WDATA_RAM_DEPTH__SHIFT 0x18
#define TCI_CNTL_2__L1_INVAL_ON_WBINVL2_MASK 0x1
#define TCI_CNTL_2__L1_INVAL_ON_WBINVL2__SHIFT 0x0
#define TCI_CNTL_2__TCA_MAX_CREDIT_MASK 0x1fe
#define TCI_CNTL_2__TCA_MAX_CREDIT__SHIFT 0x1
#define GDS_CONFIG__SH0_GPR_PHASE_SEL_MASK 0x6
#define GDS_CONFIG__SH0_GPR_PHASE_SEL__SHIFT 0x1
#define GDS_CONFIG__SH1_GPR_PHASE_SEL_MASK 0x18
#define GDS_CONFIG__SH1_GPR_PHASE_SEL__SHIFT 0x3
#define GDS_CONFIG__SH2_GPR_PHASE_SEL_MASK 0x60
#define GDS_CONFIG__SH2_GPR_PHASE_SEL__SHIFT 0x5
#define GDS_CONFIG__SH3_GPR_PHASE_SEL_MASK 0x180
#define GDS_CONFIG__SH3_GPR_PHASE_SEL__SHIFT 0x7
#define GDS_CNTL_STATUS__GDS_BUSY_MASK 0x1
#define GDS_CNTL_STATUS__GDS_BUSY__SHIFT 0x0
#define GDS_CNTL_STATUS__GRBM_WBUF_BUSY_MASK 0x2
#define GDS_CNTL_STATUS__GRBM_WBUF_BUSY__SHIFT 0x1
#define GDS_CNTL_STATUS__ORD_APP_BUSY_MASK 0x4
#define GDS_CNTL_STATUS__ORD_APP_BUSY__SHIFT 0x2
#define GDS_CNTL_STATUS__DS_BANK_CONFLICT_MASK 0x8
#define GDS_CNTL_STATUS__DS_BANK_CONFLICT__SHIFT 0x3
#define GDS_CNTL_STATUS__DS_ADDR_CONFLICT_MASK 0x10
#define GDS_CNTL_STATUS__DS_ADDR_CONFLICT__SHIFT 0x4
#define GDS_CNTL_STATUS__DS_WR_CLAMP_MASK 0x20
#define GDS_CNTL_STATUS__DS_WR_CLAMP__SHIFT 0x5
#define GDS_CNTL_STATUS__DS_RD_CLAMP_MASK 0x40
#define GDS_CNTL_STATUS__DS_RD_CLAMP__SHIFT 0x6
#define GDS_CNTL_STATUS__GRBM_RBUF_BUSY_MASK 0x80
#define GDS_CNTL_STATUS__GRBM_RBUF_BUSY__SHIFT 0x7
#define GDS_CNTL_STATUS__DS_BUSY_MASK 0x100
#define GDS_CNTL_STATUS__DS_BUSY__SHIFT 0x8
#define GDS_CNTL_STATUS__GWS_BUSY_MASK 0x200
#define GDS_CNTL_STATUS__GWS_BUSY__SHIFT 0x9
#define GDS_CNTL_STATUS__ORD_FIFO_BUSY_MASK 0x400
#define GDS_CNTL_STATUS__ORD_FIFO_BUSY__SHIFT 0xa
#define GDS_CNTL_STATUS__CREDIT_BUSY0_MASK 0x800
#define GDS_CNTL_STATUS__CREDIT_BUSY0__SHIFT 0xb
#define GDS_CNTL_STATUS__CREDIT_BUSY1_MASK 0x1000
#define GDS_CNTL_STATUS__CREDIT_BUSY1__SHIFT 0xc
#define GDS_CNTL_STATUS__CREDIT_BUSY2_MASK 0x2000
#define GDS_CNTL_STATUS__CREDIT_BUSY2__SHIFT 0xd
#define GDS_CNTL_STATUS__CREDIT_BUSY3_MASK 0x4000
#define GDS_CNTL_STATUS__CREDIT_BUSY3__SHIFT 0xe
#define GDS_ENHANCE2__MISC_MASK 0xffff
#define GDS_ENHANCE2__MISC__SHIFT 0x0
#define GDS_ENHANCE2__UNUSED_MASK 0xffff0000
#define GDS_ENHANCE2__UNUSED__SHIFT 0x10
#define GDS_PROTECTION_FAULT__WRITE_DIS_MASK 0x1
#define GDS_PROTECTION_FAULT__WRITE_DIS__SHIFT 0x0
#define GDS_PROTECTION_FAULT__FAULT_DETECTED_MASK 0x2
#define GDS_PROTECTION_FAULT__FAULT_DETECTED__SHIFT 0x1
#define GDS_PROTECTION_FAULT__GRBM_MASK 0x4
#define GDS_PROTECTION_FAULT__GRBM__SHIFT 0x2
#define GDS_PROTECTION_FAULT__SH_ID_MASK 0x38
#define GDS_PROTECTION_FAULT__SH_ID__SHIFT 0x3
#define GDS_PROTECTION_FAULT__CU_ID_MASK 0x3c0
#define GDS_PROTECTION_FAULT__CU_ID__SHIFT 0x6
#define GDS_PROTECTION_FAULT__SIMD_ID_MASK 0xc00
#define GDS_PROTECTION_FAULT__SIMD_ID__SHIFT 0xa
#define GDS_PROTECTION_FAULT__WAVE_ID_MASK 0xf000
#define GDS_PROTECTION_FAULT__WAVE_ID__SHIFT 0xc
#define GDS_PROTECTION_FAULT__ADDRESS_MASK 0xffff0000
#define GDS_PROTECTION_FAULT__ADDRESS__SHIFT 0x10
#define GDS_VM_PROTECTION_FAULT__WRITE_DIS_MASK 0x1
#define GDS_VM_PROTECTION_FAULT__WRITE_DIS__SHIFT 0x0
#define GDS_VM_PROTECTION_FAULT__FAULT_DETECTED_MASK 0x2
#define GDS_VM_PROTECTION_FAULT__FAULT_DETECTED__SHIFT 0x1
#define GDS_VM_PROTECTION_FAULT__GWS_MASK 0x4
#define GDS_VM_PROTECTION_FAULT__GWS__SHIFT 0x2
#define GDS_VM_PROTECTION_FAULT__OA_MASK 0x8
#define GDS_VM_PROTECTION_FAULT__OA__SHIFT 0x3
#define GDS_VM_PROTECTION_FAULT__GRBM_MASK 0x10
#define GDS_VM_PROTECTION_FAULT__GRBM__SHIFT 0x4
#define GDS_VM_PROTECTION_FAULT__VMID_MASK 0xf00
#define GDS_VM_PROTECTION_FAULT__VMID__SHIFT 0x8
#define GDS_VM_PROTECTION_FAULT__ADDRESS_MASK 0xffff0000
#define GDS_VM_PROTECTION_FAULT__ADDRESS__SHIFT 0x10
#define GDS_EDC_CNT__DED_MASK 0xff
#define GDS_EDC_CNT__DED__SHIFT 0x0
#define GDS_EDC_CNT__SED_MASK 0xff00
#define GDS_EDC_CNT__SED__SHIFT 0x8
#define GDS_EDC_CNT__SEC_MASK 0xff0000
#define GDS_EDC_CNT__SEC__SHIFT 0x10
#define GDS_EDC_GRBM_CNT__DED_MASK 0xff
#define GDS_EDC_GRBM_CNT__DED__SHIFT 0x0
#define GDS_EDC_GRBM_CNT__SEC_MASK 0xff0000
#define GDS_EDC_GRBM_CNT__SEC__SHIFT 0x10
#define GDS_EDC_OA_DED__ME0_GFXHP3D_PIX_DED_MASK 0x1
#define GDS_EDC_OA_DED__ME0_GFXHP3D_PIX_DED__SHIFT 0x0
#define GDS_EDC_OA_DED__ME0_GFXHP3D_VTX_DED_MASK 0x2
#define GDS_EDC_OA_DED__ME0_GFXHP3D_VTX_DED__SHIFT 0x1
#define GDS_EDC_OA_DED__ME0_CS_DED_MASK 0x4
#define GDS_EDC_OA_DED__ME0_CS_DED__SHIFT 0x2
#define GDS_EDC_OA_DED__UNUSED0_MASK 0x8
#define GDS_EDC_OA_DED__UNUSED0__SHIFT 0x3
#define GDS_EDC_OA_DED__ME1_PIPE0_DED_MASK 0x10
#define GDS_EDC_OA_DED__ME1_PIPE0_DED__SHIFT 0x4
#define GDS_EDC_OA_DED__ME1_PIPE1_DED_MASK 0x20
#define GDS_EDC_OA_DED__ME1_PIPE1_DED__SHIFT 0x5
#define GDS_EDC_OA_DED__ME1_PIPE2_DED_MASK 0x40
#define GDS_EDC_OA_DED__ME1_PIPE2_DED__SHIFT 0x6
#define GDS_EDC_OA_DED__ME1_PIPE3_DED_MASK 0x80
#define GDS_EDC_OA_DED__ME1_PIPE3_DED__SHIFT 0x7
#define GDS_EDC_OA_DED__ME2_PIPE0_DED_MASK 0x100
#define GDS_EDC_OA_DED__ME2_PIPE0_DED__SHIFT 0x8
#define GDS_EDC_OA_DED__ME2_PIPE1_DED_MASK 0x200
#define GDS_EDC_OA_DED__ME2_PIPE1_DED__SHIFT 0x9
#define GDS_EDC_OA_DED__ME2_PIPE2_DED_MASK 0x400
#define GDS_EDC_OA_DED__ME2_PIPE2_DED__SHIFT 0xa
#define GDS_EDC_OA_DED__ME2_PIPE3_DED_MASK 0x800
#define GDS_EDC_OA_DED__ME2_PIPE3_DED__SHIFT 0xb
#define GDS_EDC_OA_DED__UNUSED1_MASK 0xfffff000
#define GDS_EDC_OA_DED__UNUSED1__SHIFT 0xc
#define GDS_DEBUG_CNTL__GDS_DEBUG_INDX_MASK 0x1f
#define GDS_DEBUG_CNTL__GDS_DEBUG_INDX__SHIFT 0x0
#define GDS_DEBUG_CNTL__UNUSED_MASK 0xffffffe0
#define GDS_DEBUG_CNTL__UNUSED__SHIFT 0x5
#define GDS_DEBUG_DATA__DATA_MASK 0xffffffff
#define GDS_DEBUG_DATA__DATA__SHIFT 0x0
#define GDS_DSM_CNTL__SEL_DSM_GDS_IRRITATOR_DATA_A_0_MASK 0x1
#define GDS_DSM_CNTL__SEL_DSM_GDS_IRRITATOR_DATA_A_0__SHIFT 0x0
#define GDS_DSM_CNTL__SEL_DSM_GDS_IRRITATOR_DATA_A_1_MASK 0x2
#define GDS_DSM_CNTL__SEL_DSM_GDS_IRRITATOR_DATA_A_1__SHIFT 0x1
#define GDS_DSM_CNTL__GDS_ENABLE_SINGLE_WRITE_A_MASK 0x4
#define GDS_DSM_CNTL__GDS_ENABLE_SINGLE_WRITE_A__SHIFT 0x2
#define GDS_DSM_CNTL__SEL_DSM_GDS_IRRITATOR_DATA_B_0_MASK 0x8
#define GDS_DSM_CNTL__SEL_DSM_GDS_IRRITATOR_DATA_B_0__SHIFT 0x3
#define GDS_DSM_CNTL__SEL_DSM_GDS_IRRITATOR_DATA_B_1_MASK 0x10
#define GDS_DSM_CNTL__SEL_DSM_GDS_IRRITATOR_DATA_B_1__SHIFT 0x4
#define GDS_DSM_CNTL__GDS_ENABLE_SINGLE_WRITE_B_MASK 0x20
#define GDS_DSM_CNTL__GDS_ENABLE_SINGLE_WRITE_B__SHIFT 0x5
#define GDS_DSM_CNTL__UNUSED_MASK 0xffffffc0
#define GDS_DSM_CNTL__UNUSED__SHIFT 0x6
#define CGTT_GDS_CLK_CTRL__ON_DELAY_MASK 0xf
#define CGTT_GDS_CLK_CTRL__ON_DELAY__SHIFT 0x0
#define CGTT_GDS_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0
#define CGTT_GDS_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x1000000
#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18
#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x2000000
#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19
#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x4000000
#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a
#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x8000000
#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b
#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000
#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c
#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000
#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d
#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000
#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e
#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000
#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f
#define GDS_RD_ADDR__READ_ADDR_MASK 0xffffffff
#define GDS_RD_ADDR__READ_ADDR__SHIFT 0x0
#define GDS_RD_DATA__READ_DATA_MASK 0xffffffff
#define GDS_RD_DATA__READ_DATA__SHIFT 0x0
#define GDS_RD_BURST_ADDR__BURST_ADDR_MASK 0xffffffff
#define GDS_RD_BURST_ADDR__BURST_ADDR__SHIFT 0x0
#define GDS_RD_BURST_COUNT__BURST_COUNT_MASK 0xffffffff
#define GDS_RD_BURST_COUNT__BURST_COUNT__SHIFT 0x0
#define GDS_RD_BURST_DATA__BURST_DATA_MASK 0xffffffff
#define GDS_RD_BURST_DATA__BURST_DATA__SHIFT 0x0
#define GDS_WR_ADDR__WRITE_ADDR_MASK 0xffffffff
#define GDS_WR_ADDR__WRITE_ADDR__SHIFT 0x0
#define GDS_WR_DATA__WRITE_DATA_MASK 0xffffffff
#define GDS_WR_DATA__WRITE_DATA__SHIFT 0x0
#define GDS_WR_BURST_ADDR__WRITE_ADDR_MASK 0xffffffff
#define GDS_WR_BURST_ADDR__WRITE_ADDR__SHIFT 0x0
#define GDS_WR_BURST_DATA__WRITE_DATA_MASK 0xffffffff
#define GDS_WR_BURST_DATA__WRITE_DATA__SHIFT 0x0
#define GDS_WRITE_COMPLETE__WRITE_COMPLETE_MASK 0xffffffff
#define GDS_WRITE_COMPLETE__WRITE_COMPLETE__SHIFT 0x0
#define GDS_ATOM_CNTL__AINC_MASK 0x3f
#define GDS_ATOM_CNTL__AINC__SHIFT 0x0
#define GDS_ATOM_CNTL__UNUSED1_MASK 0xc0
#define GDS_ATOM_CNTL__UNUSED1__SHIFT 0x6
#define GDS_ATOM_CNTL__DMODE_MASK 0x300
#define GDS_ATOM_CNTL__DMODE__SHIFT 0x8
#define GDS_ATOM_CNTL__UNUSED2_MASK 0xfffffc00
#define GDS_ATOM_CNTL__UNUSED2__SHIFT 0xa
#define GDS_ATOM_COMPLETE__COMPLETE_MASK 0x1
#define GDS_ATOM_COMPLETE__COMPLETE__SHIFT 0x0
#define GDS_ATOM_COMPLETE__UNUSED_MASK 0xfffffffe
#define GDS_ATOM_COMPLETE__UNUSED__SHIFT 0x1
#define GDS_ATOM_BASE__BASE_MASK 0xffff
#define GDS_ATOM_BASE__BASE__SHIFT 0x0
#define GDS_ATOM_BASE__UNUSED_MASK 0xffff0000
#define GDS_ATOM_BASE__UNUSED__SHIFT 0x10
#define GDS_ATOM_SIZE__SIZE_MASK 0xffff
#define GDS_ATOM_SIZE__SIZE__SHIFT 0x0
#define GDS_ATOM_SIZE__UNUSED_MASK 0xffff0000
#define GDS_ATOM_SIZE__UNUSED__SHIFT 0x10
#define GDS_ATOM_OFFSET0__OFFSET0_MASK 0xff
#define GDS_ATOM_OFFSET0__OFFSET0__SHIFT 0x0
#define GDS_ATOM_OFFSET0__UNUSED_MASK 0xffffff00
#define GDS_ATOM_OFFSET0__UNUSED__SHIFT 0x8
#define GDS_ATOM_OFFSET1__OFFSET1_MASK 0xff
#define GDS_ATOM_OFFSET1__OFFSET1__SHIFT 0x0
#define GDS_ATOM_OFFSET1__UNUSED_MASK 0xffffff00
#define GDS_ATOM_OFFSET1__UNUSED__SHIFT 0x8
#define GDS_ATOM_DST__DST_MASK 0xffffffff
#define GDS_ATOM_DST__DST__SHIFT 0x0
#define GDS_ATOM_OP__OP_MASK 0xff
#define GDS_ATOM_OP__OP__SHIFT 0x0
#define GDS_ATOM_OP__UNUSED_MASK 0xffffff00
#define GDS_ATOM_OP__UNUSED__SHIFT 0x8
#define GDS_ATOM_SRC0__DATA_MASK 0xffffffff
#define GDS_ATOM_SRC0__DATA__SHIFT 0x0
#define GDS_ATOM_SRC0_U__DATA_MASK 0xffffffff
#define GDS_ATOM_SRC0_U__DATA__SHIFT 0x0
#define GDS_ATOM_SRC1__DATA_MASK 0xffffffff
#define GDS_ATOM_SRC1__DATA__SHIFT 0x0
#define GDS_ATOM_SRC1_U__DATA_MASK 0xffffffff
#define GDS_ATOM_SRC1_U__DATA__SHIFT 0x0
#define GDS_ATOM_READ0__DATA_MASK 0xffffffff
#define GDS_ATOM_READ0__DATA__SHIFT 0x0
#define GDS_ATOM_READ0_U__DATA_MASK 0xffffffff
#define GDS_ATOM_READ0_U__DATA__SHIFT 0x0
#define GDS_ATOM_READ1__DATA_MASK 0xffffffff
#define GDS_ATOM_READ1__DATA__SHIFT 0x0
#define GDS_ATOM_READ1_U__DATA_MASK 0xffffffff
#define GDS_ATOM_READ1_U__DATA__SHIFT 0x0
#define GDS_GWS_RESOURCE_CNTL__INDEX_MASK 0x3f
#define GDS_GWS_RESOURCE_CNTL__INDEX__SHIFT 0x0
#define GDS_GWS_RESOURCE_CNTL__UNUSED_MASK 0xffffffc0
#define GDS_GWS_RESOURCE_CNTL__UNUSED__SHIFT 0x6
#define GDS_GWS_RESOURCE__FLAG_MASK 0x1
#define GDS_GWS_RESOURCE__FLAG__SHIFT 0x0
#define GDS_GWS_RESOURCE__COUNTER_MASK 0x1ffe
#define GDS_GWS_RESOURCE__COUNTER__SHIFT 0x1
#define GDS_GWS_RESOURCE__TYPE_MASK 0x2000
#define GDS_GWS_RESOURCE__TYPE__SHIFT 0xd
#define GDS_GWS_RESOURCE__DED_MASK 0x4000
#define GDS_GWS_RESOURCE__DED__SHIFT 0xe
#define GDS_GWS_RESOURCE__RELEASE_ALL_MASK 0x8000
#define GDS_GWS_RESOURCE__RELEASE_ALL__SHIFT 0xf
#define GDS_GWS_RESOURCE__HEAD_QUEUE_MASK 0x7ff0000
#define GDS_GWS_RESOURCE__HEAD_QUEUE__SHIFT 0x10
#define GDS_GWS_RESOURCE__HEAD_VALID_MASK 0x8000000
#define GDS_GWS_RESOURCE__HEAD_VALID__SHIFT 0x1b
#define GDS_GWS_RESOURCE__HEAD_FLAG_MASK 0x10000000
#define GDS_GWS_RESOURCE__HEAD_FLAG__SHIFT 0x1c
#define GDS_GWS_RESOURCE__UNUSED1_MASK 0xe0000000
#define GDS_GWS_RESOURCE__UNUSED1__SHIFT 0x1d
#define GDS_GWS_RESOURCE_CNT__RESOURCE_CNT_MASK 0xffff
#define GDS_GWS_RESOURCE_CNT__RESOURCE_CNT__SHIFT 0x0
#define GDS_GWS_RESOURCE_CNT__UNUSED_MASK 0xffff0000
#define GDS_GWS_RESOURCE_CNT__UNUSED__SHIFT 0x10
#define GDS_OA_CNTL__INDEX_MASK 0xf
#define GDS_OA_CNTL__INDEX__SHIFT 0x0
#define GDS_OA_CNTL__UNUSED_MASK 0xfffffff0
#define GDS_OA_CNTL__UNUSED__SHIFT 0x4
#define GDS_OA_COUNTER__SPACE_AVAILABLE_MASK 0xffffffff
#define GDS_OA_COUNTER__SPACE_AVAILABLE__SHIFT 0x0
#define GDS_OA_ADDRESS__DS_ADDRESS_MASK 0xffff
#define GDS_OA_ADDRESS__DS_ADDRESS__SHIFT 0x0
#define GDS_OA_ADDRESS__CRAWLER_MASK 0xf0000
#define GDS_OA_ADDRESS__CRAWLER__SHIFT 0x10
#define GDS_OA_ADDRESS__CRAWLER_TYPE_MASK 0x300000
#define GDS_OA_ADDRESS__CRAWLER_TYPE__SHIFT 0x14
#define GDS_OA_ADDRESS__UNUSED_MASK 0x3fc00000
#define GDS_OA_ADDRESS__UNUSED__SHIFT 0x16
#define GDS_OA_ADDRESS__NO_ALLOC_MASK 0x40000000
#define GDS_OA_ADDRESS__NO_ALLOC__SHIFT 0x1e
#define GDS_OA_ADDRESS__ENABLE_MASK 0x80000000
#define GDS_OA_ADDRESS__ENABLE__SHIFT 0x1f
#define GDS_OA_INCDEC__VALUE_MASK 0x7fffffff
#define GDS_OA_INCDEC__VALUE__SHIFT 0x0
#define GDS_OA_INCDEC__INCDEC_MASK 0x80000000
#define GDS_OA_INCDEC__INCDEC__SHIFT 0x1f
#define GDS_OA_RING_SIZE__RING_SIZE_MASK 0xffffffff
#define GDS_OA_RING_SIZE__RING_SIZE__SHIFT 0x0
#define GDS_DEBUG_REG0__spare1_MASK 0x3f
#define GDS_DEBUG_REG0__spare1__SHIFT 0x0
#define GDS_DEBUG_REG0__write_buff_valid_MASK 0x40
#define GDS_DEBUG_REG0__write_buff_valid__SHIFT 0x6
#define GDS_DEBUG_REG0__wr_pixel_nxt_ptr_MASK 0xf80
#define GDS_DEBUG_REG0__wr_pixel_nxt_ptr__SHIFT 0x7
#define GDS_DEBUG_REG0__last_pixel_ptr_MASK 0x1000
#define GDS_DEBUG_REG0__last_pixel_ptr__SHIFT 0xc
#define GDS_DEBUG_REG0__cstate_MASK 0x1e000
#define GDS_DEBUG_REG0__cstate__SHIFT 0xd
#define GDS_DEBUG_REG0__buff_write_MASK 0x20000
#define GDS_DEBUG_REG0__buff_write__SHIFT 0x11
#define GDS_DEBUG_REG0__flush_request_MASK 0x40000
#define GDS_DEBUG_REG0__flush_request__SHIFT 0x12
#define GDS_DEBUG_REG0__wr_buffer_wr_complete_MASK 0x80000
#define GDS_DEBUG_REG0__wr_buffer_wr_complete__SHIFT 0x13
#define GDS_DEBUG_REG0__wbuf_fifo_empty_MASK 0x100000
#define GDS_DEBUG_REG0__wbuf_fifo_empty__SHIFT 0x14
#define GDS_DEBUG_REG0__wbuf_fifo_full_MASK 0x200000
#define GDS_DEBUG_REG0__wbuf_fifo_full__SHIFT 0x15
#define GDS_DEBUG_REG0__spare_MASK 0xffc00000
#define GDS_DEBUG_REG0__spare__SHIFT 0x16
#define GDS_DEBUG_REG1__tag_hit_MASK 0x1
#define GDS_DEBUG_REG1__tag_hit__SHIFT 0x0
#define GDS_DEBUG_REG1__tag_miss_MASK 0x2
#define GDS_DEBUG_REG1__tag_miss__SHIFT 0x1
#define GDS_DEBUG_REG1__pixel_addr_MASK 0x1fffc
#define GDS_DEBUG_REG1__pixel_addr__SHIFT 0x2
#define GDS_DEBUG_REG1__pixel_vld_MASK 0x20000
#define GDS_DEBUG_REG1__pixel_vld__SHIFT 0x11
#define GDS_DEBUG_REG1__data_ready_MASK 0x40000
#define GDS_DEBUG_REG1__data_ready__SHIFT 0x12
#define GDS_DEBUG_REG1__awaiting_data_MASK 0x80000
#define GDS_DEBUG_REG1__awaiting_data__SHIFT 0x13
#define GDS_DEBUG_REG1__addr_fifo_full_MASK 0x100000
#define GDS_DEBUG_REG1__addr_fifo_full__SHIFT 0x14
#define GDS_DEBUG_REG1__addr_fifo_empty_MASK 0x200000
#define GDS_DEBUG_REG1__addr_fifo_empty__SHIFT 0x15
#define GDS_DEBUG_REG1__buffer_loaded_MASK 0x400000
#define GDS_DEBUG_REG1__buffer_loaded__SHIFT 0x16
#define GDS_DEBUG_REG1__buffer_invalid_MASK 0x800000
#define GDS_DEBUG_REG1__buffer_invalid__SHIFT 0x17
#define GDS_DEBUG_REG1__spare_MASK 0xff000000
#define GDS_DEBUG_REG1__spare__SHIFT 0x18
#define GDS_DEBUG_REG2__ds_full_MASK 0x1
#define GDS_DEBUG_REG2__ds_full__SHIFT 0x0
#define GDS_DEBUG_REG2__ds_credit_avail_MASK 0x2
#define GDS_DEBUG_REG2__ds_credit_avail__SHIFT 0x1
#define GDS_DEBUG_REG2__ord_idx_free_MASK 0x4
#define GDS_DEBUG_REG2__ord_idx_free__SHIFT 0x2
#define GDS_DEBUG_REG2__cmd_write_MASK 0x8
#define GDS_DEBUG_REG2__cmd_write__SHIFT 0x3
#define GDS_DEBUG_REG2__app_sel_MASK 0xf0
#define GDS_DEBUG_REG2__app_sel__SHIFT 0x4
#define GDS_DEBUG_REG2__req_MASK 0x7fff00
#define GDS_DEBUG_REG2__req__SHIFT 0x8
#define GDS_DEBUG_REG2__spare_MASK 0xff800000
#define GDS_DEBUG_REG2__spare__SHIFT 0x17
#define GDS_DEBUG_REG3__pipe_num_busy_MASK 0x7ff
#define GDS_DEBUG_REG3__pipe_num_busy__SHIFT 0x0
#define GDS_DEBUG_REG3__pipe0_busy_num_MASK 0x7800
#define GDS_DEBUG_REG3__pipe0_busy_num__SHIFT 0xb
#define GDS_DEBUG_REG3__spare_MASK 0xffff8000
#define GDS_DEBUG_REG3__spare__SHIFT 0xf
#define GDS_DEBUG_REG4__gws_busy_MASK 0x1
#define GDS_DEBUG_REG4__gws_busy__SHIFT 0x0
#define GDS_DEBUG_REG4__gws_req_MASK 0x2
#define GDS_DEBUG_REG4__gws_req__SHIFT 0x1
#define GDS_DEBUG_REG4__gws_out_stall_MASK 0x4
#define GDS_DEBUG_REG4__gws_out_stall__SHIFT 0x2
#define GDS_DEBUG_REG4__cur_reso_MASK 0x1f8
#define GDS_DEBUG_REG4__cur_reso__SHIFT 0x3
#define GDS_DEBUG_REG4__cur_reso_head_valid_MASK 0x200
#define GDS_DEBUG_REG4__cur_reso_head_valid__SHIFT 0x9
#define GDS_DEBUG_REG4__cur_reso_head_dirty_MASK 0x400
#define GDS_DEBUG_REG4__cur_reso_head_dirty__SHIFT 0xa
#define GDS_DEBUG_REG4__cur_reso_head_flag_MASK 0x800
#define GDS_DEBUG_REG4__cur_reso_head_flag__SHIFT 0xb
#define GDS_DEBUG_REG4__cur_reso_fed_MASK 0x1000
#define GDS_DEBUG_REG4__cur_reso_fed__SHIFT 0xc
#define GDS_DEBUG_REG4__cur_reso_barrier_MASK 0x2000
#define GDS_DEBUG_REG4__cur_reso_barrier__SHIFT 0xd
#define GDS_DEBUG_REG4__cur_reso_flag_MASK 0x4000
#define GDS_DEBUG_REG4__cur_reso_flag__SHIFT 0xe
#define GDS_DEBUG_REG4__cur_reso_cnt_gt0_MASK 0x8000
#define GDS_DEBUG_REG4__cur_reso_cnt_gt0__SHIFT 0xf
#define GDS_DEBUG_REG4__credit_cnt_gt0_MASK 0x10000
#define GDS_DEBUG_REG4__credit_cnt_gt0__SHIFT 0x10
#define GDS_DEBUG_REG4__cmd_write_MASK 0x20000
#define GDS_DEBUG_REG4__cmd_write__SHIFT 0x11
#define GDS_DEBUG_REG4__grbm_gws_reso_wr_MASK 0x40000
#define GDS_DEBUG_REG4__grbm_gws_reso_wr__SHIFT 0x12
#define GDS_DEBUG_REG4__grbm_gws_reso_rd_MASK 0x80000
#define GDS_DEBUG_REG4__grbm_gws_reso_rd__SHIFT 0x13
#define GDS_DEBUG_REG4__ram_read_busy_MASK 0x100000
#define GDS_DEBUG_REG4__ram_read_busy__SHIFT 0x14
#define GDS_DEBUG_REG4__gws_bulkfree_MASK 0x200000
#define GDS_DEBUG_REG4__gws_bulkfree__SHIFT 0x15
#define GDS_DEBUG_REG4__ram_gws_re_MASK 0x400000
#define GDS_DEBUG_REG4__ram_gws_re__SHIFT 0x16
#define GDS_DEBUG_REG4__ram_gws_we_MASK 0x800000
#define GDS_DEBUG_REG4__ram_gws_we__SHIFT 0x17
#define GDS_DEBUG_REG4__spare_MASK 0xff000000
#define GDS_DEBUG_REG4__spare__SHIFT 0x18
#define GDS_DEBUG_REG5__write_dis_MASK 0x1
#define GDS_DEBUG_REG5__write_dis__SHIFT 0x0
#define GDS_DEBUG_REG5__dec_error_MASK 0x2
#define GDS_DEBUG_REG5__dec_error__SHIFT 0x1
#define GDS_DEBUG_REG5__alloc_opco_error_MASK 0x4
#define GDS_DEBUG_REG5__alloc_opco_error__SHIFT 0x2
#define GDS_DEBUG_REG5__dealloc_opco_error_MASK 0x8
#define GDS_DEBUG_REG5__dealloc_opco_error__SHIFT 0x3
#define GDS_DEBUG_REG5__wrap_opco_error_MASK 0x10
#define GDS_DEBUG_REG5__wrap_opco_error__SHIFT 0x4
#define GDS_DEBUG_REG5__spare_MASK 0xe0
#define GDS_DEBUG_REG5__spare__SHIFT 0x5
#define GDS_DEBUG_REG5__error_ds_address_MASK 0x3fff00
#define GDS_DEBUG_REG5__error_ds_address__SHIFT 0x8
#define GDS_DEBUG_REG5__spare1_MASK 0xffc00000
#define GDS_DEBUG_REG5__spare1__SHIFT 0x16
#define GDS_DEBUG_REG6__oa_busy_MASK 0x1
#define GDS_DEBUG_REG6__oa_busy__SHIFT 0x0
#define GDS_DEBUG_REG6__counters_enabled_MASK 0x1e
#define GDS_DEBUG_REG6__counters_enabled__SHIFT 0x1
#define GDS_DEBUG_REG6__counters_busy_MASK 0x1fffe0
#define GDS_DEBUG_REG6__counters_busy__SHIFT 0x5
#define GDS_DEBUG_REG6__spare_MASK 0xffe00000
#define GDS_DEBUG_REG6__spare__SHIFT 0x15
#define GDS_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT_MASK 0x3ff
#define GDS_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT__SHIFT 0x0
#define GDS_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT1_MASK 0xffc00
#define GDS_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT1__SHIFT 0xa
#define GDS_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000
#define GDS_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
#define GDS_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT_MASK 0x3ff
#define GDS_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT__SHIFT 0x0
#define GDS_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT1_MASK 0xffc00
#define GDS_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT1__SHIFT 0xa
#define GDS_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0xf00000
#define GDS_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14
#define GDS_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT_MASK 0x3ff
#define GDS_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT__SHIFT 0x0
#define GDS_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT1_MASK 0xffc00
#define GDS_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT1__SHIFT 0xa
#define GDS_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0xf00000
#define GDS_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14
#define GDS_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT_MASK 0x3ff
#define GDS_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT__SHIFT 0x0
#define GDS_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT1_MASK 0xffc00
#define GDS_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT1__SHIFT 0xa
#define GDS_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0xf00000
#define GDS_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14
#define GDS_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff
#define GDS_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
#define GDS_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff
#define GDS_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
#define GDS_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffff
#define GDS_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0
#define GDS_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffff
#define GDS_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0
#define GDS_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff
#define GDS_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
#define GDS_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff
#define GDS_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
#define GDS_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffff
#define GDS_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0
#define GDS_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffff
#define GDS_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0
#define GDS_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT2_MASK 0x3ff
#define GDS_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT2__SHIFT 0x0
#define GDS_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT3_MASK 0xffc00
#define GDS_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT3__SHIFT 0xa
#define GDS_VMID0_BASE__BASE_MASK 0xffff
#define GDS_VMID0_BASE__BASE__SHIFT 0x0
#define GDS_VMID1_BASE__BASE_MASK 0xffff
#define GDS_VMID1_BASE__BASE__SHIFT 0x0
#define GDS_VMID2_BASE__BASE_MASK 0xffff
#define GDS_VMID2_BASE__BASE__SHIFT 0x0
#define GDS_VMID3_BASE__BASE_MASK 0xffff
#define GDS_VMID3_BASE__BASE__SHIFT 0x0
#define GDS_VMID4_BASE__BASE_MASK 0xffff
#define GDS_VMID4_BASE__BASE__SHIFT 0x0
#define GDS_VMID5_BASE__BASE_MASK 0xffff
#define GDS_VMID5_BASE__BASE__SHIFT 0x0
#define GDS_VMID6_BASE__BASE_MASK 0xffff
#define GDS_VMID6_BASE__BASE__SHIFT 0x0
#define GDS_VMID7_BASE__BASE_MASK 0xffff
#define GDS_VMID7_BASE__BASE__SHIFT 0x0
#define GDS_VMID8_BASE__BASE_MASK 0xffff
#define GDS_VMID8_BASE__BASE__SHIFT 0x0
#define GDS_VMID9_BASE__BASE_MASK 0xffff
#define GDS_VMID9_BASE__BASE__SHIFT 0x0
#define GDS_VMID10_BASE__BASE_MASK 0xffff
#define GDS_VMID10_BASE__BASE__SHIFT 0x0
#define GDS_VMID11_BASE__BASE_MASK 0xffff
#define GDS_VMID11_BASE__BASE__SHIFT 0x0
#define GDS_VMID12_BASE__BASE_MASK 0xffff
#define GDS_VMID12_BASE__BASE__SHIFT 0x0
#define GDS_VMID13_BASE__BASE_MASK 0xffff
#define GDS_VMID13_BASE__BASE__SHIFT 0x0
#define GDS_VMID14_BASE__BASE_MASK 0xffff
#define GDS_VMID14_BASE__BASE__SHIFT 0x0
#define GDS_VMID15_BASE__BASE_MASK 0xffff
#define GDS_VMID15_BASE__BASE__SHIFT 0x0
#define GDS_VMID0_SIZE__SIZE_MASK 0x1ffff
#define GDS_VMID0_SIZE__SIZE__SHIFT 0x0
#define GDS_VMID1_SIZE__SIZE_MASK 0x1ffff
#define GDS_VMID1_SIZE__SIZE__SHIFT 0x0
#define GDS_VMID2_SIZE__SIZE_MASK 0x1ffff
#define GDS_VMID2_SIZE__SIZE__SHIFT 0x0
#define GDS_VMID3_SIZE__SIZE_MASK 0x1ffff
#define GDS_VMID3_SIZE__SIZE__SHIFT 0x0
#define GDS_VMID4_SIZE__SIZE_MASK 0x1ffff
#define GDS_VMID4_SIZE__SIZE__SHIFT 0x0
#define GDS_VMID5_SIZE__SIZE_MASK 0x1ffff
#define GDS_VMID5_SIZE__SIZE__SHIFT 0x0
#define GDS_VMID6_SIZE__SIZE_MASK 0x1ffff
#define GDS_VMID6_SIZE__SIZE__SHIFT 0x0
#define GDS_VMID7_SIZE__SIZE_MASK 0x1ffff
#define GDS_VMID7_SIZE__SIZE__SHIFT 0x0
#define GDS_VMID8_SIZE__SIZE_MASK 0x1ffff
#define GDS_VMID8_SIZE__SIZE__SHIFT 0x0
#define GDS_VMID9_SIZE__SIZE_MASK 0x1ffff
#define GDS_VMID9_SIZE__SIZE__SHIFT 0x0
#define GDS_VMID10_SIZE__SIZE_MASK 0x1ffff
#define GDS_VMID10_SIZE__SIZE__SHIFT 0x0
#define GDS_VMID11_SIZE__SIZE_MASK 0x1ffff
#define GDS_VMID11_SIZE__SIZE__SHIFT 0x0
#define GDS_VMID12_SIZE__SIZE_MASK 0x1ffff
#define GDS_VMID12_SIZE__SIZE__SHIFT 0x0
#define GDS_VMID13_SIZE__SIZE_MASK 0x1ffff
#define GDS_VMID13_SIZE__SIZE__SHIFT 0x0
#define GDS_VMID14_SIZE__SIZE_MASK 0x1ffff
#define GDS_VMID14_SIZE__SIZE__SHIFT 0x0
#define GDS_VMID15_SIZE__SIZE_MASK 0x1ffff
#define GDS_VMID15_SIZE__SIZE__SHIFT 0x0
#define GDS_GWS_VMID0__BASE_MASK 0x3f
#define GDS_GWS_VMID0__BASE__SHIFT 0x0
#define GDS_GWS_VMID0__SIZE_MASK 0x7f0000
#define GDS_GWS_VMID0__SIZE__SHIFT 0x10
#define GDS_GWS_VMID1__BASE_MASK 0x3f
#define GDS_GWS_VMID1__BASE__SHIFT 0x0
#define GDS_GWS_VMID1__SIZE_MASK 0x7f0000
#define GDS_GWS_VMID1__SIZE__SHIFT 0x10
#define GDS_GWS_VMID2__BASE_MASK 0x3f
#define GDS_GWS_VMID2__BASE__SHIFT 0x0
#define GDS_GWS_VMID2__SIZE_MASK 0x7f0000
#define GDS_GWS_VMID2__SIZE__SHIFT 0x10
#define GDS_GWS_VMID3__BASE_MASK 0x3f
#define GDS_GWS_VMID3__BASE__SHIFT 0x0
#define GDS_GWS_VMID3__SIZE_MASK 0x7f0000
#define GDS_GWS_VMID3__SIZE__SHIFT 0x10
#define GDS_GWS_VMID4__BASE_MASK 0x3f
#define GDS_GWS_VMID4__BASE__SHIFT 0x0
#define GDS_GWS_VMID4__SIZE_MASK 0x7f0000
#define GDS_GWS_VMID4__SIZE__SHIFT 0x10
#define GDS_GWS_VMID5__BASE_MASK 0x3f
#define GDS_GWS_VMID5__BASE__SHIFT 0x0
#define GDS_GWS_VMID5__SIZE_MASK 0x7f0000
#define GDS_GWS_VMID5__SIZE__SHIFT 0x10
#define GDS_GWS_VMID6__BASE_MASK 0x3f
#define GDS_GWS_VMID6__BASE__SHIFT 0x0
#define GDS_GWS_VMID6__SIZE_MASK 0x7f0000
#define GDS_GWS_VMID6__SIZE__SHIFT 0x10
#define GDS_GWS_VMID7__BASE_MASK 0x3f
#define GDS_GWS_VMID7__BASE__SHIFT 0x0
#define GDS_GWS_VMID7__SIZE_MASK 0x7f0000
#define GDS_GWS_VMID7__SIZE__SHIFT 0x10
#define GDS_GWS_VMID8__BASE_MASK 0x3f
#define GDS_GWS_VMID8__BASE__SHIFT 0x0
#define GDS_GWS_VMID8__SIZE_MASK 0x7f0000
#define GDS_GWS_VMID8__SIZE__SHIFT 0x10
#define GDS_GWS_VMID9__BASE_MASK 0x3f
#define GDS_GWS_VMID9__BASE__SHIFT 0x0
#define GDS_GWS_VMID9__SIZE_MASK 0x7f0000
#define GDS_GWS_VMID9__SIZE__SHIFT 0x10
#define GDS_GWS_VMID10__BASE_MASK 0x3f
#define GDS_GWS_VMID10__BASE__SHIFT 0x0
#define GDS_GWS_VMID10__SIZE_MASK 0x7f0000
#define GDS_GWS_VMID10__SIZE__SHIFT 0x10
#define GDS_GWS_VMID11__BASE_MASK 0x3f
#define GDS_GWS_VMID11__BASE__SHIFT 0x0
#define GDS_GWS_VMID11__SIZE_MASK 0x7f0000
#define GDS_GWS_VMID11__SIZE__SHIFT 0x10
#define GDS_GWS_VMID12__BASE_MASK 0x3f
#define GDS_GWS_VMID12__BASE__SHIFT 0x0
#define GDS_GWS_VMID12__SIZE_MASK 0x7f0000
#define GDS_GWS_VMID12__SIZE__SHIFT 0x10
#define GDS_GWS_VMID13__BASE_MASK 0x3f
#define GDS_GWS_VMID13__BASE__SHIFT 0x0
#define GDS_GWS_VMID13__SIZE_MASK 0x7f0000
#define GDS_GWS_VMID13__SIZE__SHIFT 0x10
#define GDS_GWS_VMID14__BASE_MASK 0x3f
#define GDS_GWS_VMID14__BASE__SHIFT 0x0
#define GDS_GWS_VMID14__SIZE_MASK 0x7f0000
#define GDS_GWS_VMID14__SIZE__SHIFT 0x10
#define GDS_GWS_VMID15__BASE_MASK 0x3f
#define GDS_GWS_VMID15__BASE__SHIFT 0x0
#define GDS_GWS_VMID15__SIZE_MASK 0x7f0000
#define GDS_GWS_VMID15__SIZE__SHIFT 0x10
#define GDS_OA_VMID0__MASK_MASK 0xffff
#define GDS_OA_VMID0__MASK__SHIFT 0x0
#define GDS_OA_VMID0__UNUSED_MASK 0xffff0000
#define GDS_OA_VMID0__UNUSED__SHIFT 0x10
#define GDS_OA_VMID1__MASK_MASK 0xffff
#define GDS_OA_VMID1__MASK__SHIFT 0x0
#define GDS_OA_VMID1__UNUSED_MASK 0xffff0000
#define GDS_OA_VMID1__UNUSED__SHIFT 0x10
#define GDS_OA_VMID2__MASK_MASK 0xffff
#define GDS_OA_VMID2__MASK__SHIFT 0x0
#define GDS_OA_VMID2__UNUSED_MASK 0xffff0000
#define GDS_OA_VMID2__UNUSED__SHIFT 0x10
#define GDS_OA_VMID3__MASK_MASK 0xffff
#define GDS_OA_VMID3__MASK__SHIFT 0x0
#define GDS_OA_VMID3__UNUSED_MASK 0xffff0000
#define GDS_OA_VMID3__UNUSED__SHIFT 0x10
#define GDS_OA_VMID4__MASK_MASK 0xffff
#define GDS_OA_VMID4__MASK__SHIFT 0x0
#define GDS_OA_VMID4__UNUSED_MASK 0xffff0000
#define GDS_OA_VMID4__UNUSED__SHIFT 0x10
#define GDS_OA_VMID5__MASK_MASK 0xffff
#define GDS_OA_VMID5__MASK__SHIFT 0x0
#define GDS_OA_VMID5__UNUSED_MASK 0xffff0000
#define GDS_OA_VMID5__UNUSED__SHIFT 0x10
#define GDS_OA_VMID6__MASK_MASK 0xffff
#define GDS_OA_VMID6__MASK__SHIFT 0x0
#define GDS_OA_VMID6__UNUSED_MASK 0xffff0000
#define GDS_OA_VMID6__UNUSED__SHIFT 0x10
#define GDS_OA_VMID7__MASK_MASK 0xffff
#define GDS_OA_VMID7__MASK__SHIFT 0x0
#define GDS_OA_VMID7__UNUSED_MASK 0xffff0000
#define GDS_OA_VMID7__UNUSED__SHIFT 0x10
#define GDS_OA_VMID8__MASK_MASK 0xffff
#define GDS_OA_VMID8__MASK__SHIFT 0x0
#define GDS_OA_VMID8__UNUSED_MASK 0xffff0000
#define GDS_OA_VMID8__UNUSED__SHIFT 0x10
#define GDS_OA_VMID9__MASK_MASK 0xffff
#define GDS_OA_VMID9__MASK__SHIFT 0x0
#define GDS_OA_VMID9__UNUSED_MASK 0xffff0000
#define GDS_OA_VMID9__UNUSED__SHIFT 0x10
#define GDS_OA_VMID10__MASK_MASK 0xffff
#define GDS_OA_VMID10__MASK__SHIFT 0x0
#define GDS_OA_VMID10__UNUSED_MASK 0xffff0000
#define GDS_OA_VMID10__UNUSED__SHIFT 0x10
#define GDS_OA_VMID11__MASK_MASK 0xffff
#define GDS_OA_VMID11__MASK__SHIFT 0x0
#define GDS_OA_VMID11__UNUSED_MASK 0xffff0000
#define GDS_OA_VMID11__UNUSED__SHIFT 0x10
#define GDS_OA_VMID12__MASK_MASK 0xffff
#define GDS_OA_VMID12__MASK__SHIFT 0x0
#define GDS_OA_VMID12__UNUSED_MASK 0xffff0000
#define GDS_OA_VMID12__UNUSED__SHIFT 0x10
#define GDS_OA_VMID13__MASK_MASK 0xffff
#define GDS_OA_VMID13__MASK__SHIFT 0x0
#define GDS_OA_VMID13__UNUSED_MASK 0xffff0000
#define GDS_OA_VMID13__UNUSED__SHIFT 0x10
#define GDS_OA_VMID14__MASK_MASK 0xffff
#define GDS_OA_VMID14__MASK__SHIFT 0x0
#define GDS_OA_VMID14__UNUSED_MASK 0xffff0000
#define GDS_OA_VMID14__UNUSED__SHIFT 0x10
#define GDS_OA_VMID15__MASK_MASK 0xffff
#define GDS_OA_VMID15__MASK__SHIFT 0x0
#define GDS_OA_VMID15__UNUSED_MASK 0xffff0000
#define GDS_OA_VMID15__UNUSED__SHIFT 0x10
#define GDS_GWS_RESET0__RESOURCE0_RESET_MASK 0x1
#define GDS_GWS_RESET0__RESOURCE0_RESET__SHIFT 0x0
#define GDS_GWS_RESET0__RESOURCE1_RESET_MASK 0x2
#define GDS_GWS_RESET0__RESOURCE1_RESET__SHIFT 0x1
#define GDS_GWS_RESET0__RESOURCE2_RESET_MASK 0x4
#define GDS_GWS_RESET0__RESOURCE2_RESET__SHIFT 0x2
#define GDS_GWS_RESET0__RESOURCE3_RESET_MASK 0x8
#define GDS_GWS_RESET0__RESOURCE3_RESET__SHIFT 0x3
#define GDS_GWS_RESET0__RESOURCE4_RESET_MASK 0x10
#define GDS_GWS_RESET0__RESOURCE4_RESET__SHIFT 0x4
#define GDS_GWS_RESET0__RESOURCE5_RESET_MASK 0x20
#define GDS_GWS_RESET0__RESOURCE5_RESET__SHIFT 0x5
#define GDS_GWS_RESET0__RESOURCE6_RESET_MASK 0x40
#define GDS_GWS_RESET0__RESOURCE6_RESET__SHIFT 0x6
#define GDS_GWS_RESET0__RESOURCE7_RESET_MASK 0x80
#define GDS_GWS_RESET0__RESOURCE7_RESET__SHIFT 0x7
#define GDS_GWS_RESET0__RESOURCE8_RESET_MASK 0x100
#define GDS_GWS_RESET0__RESOURCE8_RESET__SHIFT 0x8
#define GDS_GWS_RESET0__RESOURCE9_RESET_MASK 0x200
#define GDS_GWS_RESET0__RESOURCE9_RESET__SHIFT 0x9
#define GDS_GWS_RESET0__RESOURCE10_RESET_MASK 0x400
#define GDS_GWS_RESET0__RESOURCE10_RESET__SHIFT 0xa
#define GDS_GWS_RESET0__RESOURCE11_RESET_MASK 0x800
#define GDS_GWS_RESET0__RESOURCE11_RESET__SHIFT 0xb
#define GDS_GWS_RESET0__RESOURCE12_RESET_MASK 0x1000
#define GDS_GWS_RESET0__RESOURCE12_RESET__SHIFT 0xc
#define GDS_GWS_RESET0__RESOURCE13_RESET_MASK 0x2000
#define GDS_GWS_RESET0__RESOURCE13_RESET__SHIFT 0xd
#define GDS_GWS_RESET0__RESOURCE14_RESET_MASK 0x4000
#define GDS_GWS_RESET0__RESOURCE14_RESET__SHIFT 0xe
#define GDS_GWS_RESET0__RESOURCE15_RESET_MASK 0x8000
#define GDS_GWS_RESET0__RESOURCE15_RESET__SHIFT 0xf
#define GDS_GWS_RESET0__RESOURCE16_RESET_MASK 0x10000
#define GDS_GWS_RESET0__RESOURCE16_RESET__SHIFT 0x10
#define GDS_GWS_RESET0__RESOURCE17_RESET_MASK 0x20000
#define GDS_GWS_RESET0__RESOURCE17_RESET__SHIFT 0x11
#define GDS_GWS_RESET0__RESOURCE18_RESET_MASK 0x40000
#define GDS_GWS_RESET0__RESOURCE18_RESET__SHIFT 0x12
#define GDS_GWS_RESET0__RESOURCE19_RESET_MASK 0x80000
#define GDS_GWS_RESET0__RESOURCE19_RESET__SHIFT 0x13
#define GDS_GWS_RESET0__RESOURCE20_RESET_MASK 0x100000
#define GDS_GWS_RESET0__RESOURCE20_RESET__SHIFT 0x14
#define GDS_GWS_RESET0__RESOURCE21_RESET_MASK 0x200000
#define GDS_GWS_RESET0__RESOURCE21_RESET__SHIFT 0x15
#define GDS_GWS_RESET0__RESOURCE22_RESET_MASK 0x400000
#define GDS_GWS_RESET0__RESOURCE22_RESET__SHIFT 0x16
#define GDS_GWS_RESET0__RESOURCE23_RESET_MASK 0x800000
#define GDS_GWS_RESET0__RESOURCE23_RESET__SHIFT 0x17
#define GDS_GWS_RESET0__RESOURCE24_RESET_MASK 0x1000000
#define GDS_GWS_RESET0__RESOURCE24_RESET__SHIFT 0x18
#define GDS_GWS_RESET0__RESOURCE25_RESET_MASK 0x2000000
#define GDS_GWS_RESET0__RESOURCE25_RESET__SHIFT 0x19
#define GDS_GWS_RESET0__RESOURCE26_RESET_MASK 0x4000000
#define GDS_GWS_RESET0__RESOURCE26_RESET__SHIFT 0x1a
#define GDS_GWS_RESET0__RESOURCE27_RESET_MASK 0x8000000
#define GDS_GWS_RESET0__RESOURCE27_RESET__SHIFT 0x1b
#define GDS_GWS_RESET0__RESOURCE28_RESET_MASK 0x10000000
#define GDS_GWS_RESET0__RESOURCE28_RESET__SHIFT 0x1c
#define GDS_GWS_RESET0__RESOURCE29_RESET_MASK 0x20000000
#define GDS_GWS_RESET0__RESOURCE29_RESET__SHIFT 0x1d
#define GDS_GWS_RESET0__RESOURCE30_RESET_MASK 0x40000000
#define GDS_GWS_RESET0__RESOURCE30_RESET__SHIFT 0x1e
#define GDS_GWS_RESET0__RESOURCE31_RESET_MASK 0x80000000
#define GDS_GWS_RESET0__RESOURCE31_RESET__SHIFT 0x1f
#define GDS_GWS_RESET1__RESOURCE32_RESET_MASK 0x1
#define GDS_GWS_RESET1__RESOURCE32_RESET__SHIFT 0x0
#define GDS_GWS_RESET1__RESOURCE33_RESET_MASK 0x2
#define GDS_GWS_RESET1__RESOURCE33_RESET__SHIFT 0x1
#define GDS_GWS_RESET1__RESOURCE34_RESET_MASK 0x4
#define GDS_GWS_RESET1__RESOURCE34_RESET__SHIFT 0x2
#define GDS_GWS_RESET1__RESOURCE35_RESET_MASK 0x8
#define GDS_GWS_RESET1__RESOURCE35_RESET__SHIFT 0x3
#define GDS_GWS_RESET1__RESOURCE36_RESET_MASK 0x10
#define GDS_GWS_RESET1__RESOURCE36_RESET__SHIFT 0x4
#define GDS_GWS_RESET1__RESOURCE37_RESET_MASK 0x20
#define GDS_GWS_RESET1__RESOURCE37_RESET__SHIFT 0x5
#define GDS_GWS_RESET1__RESOURCE38_RESET_MASK 0x40
#define GDS_GWS_RESET1__RESOURCE38_RESET__SHIFT 0x6
#define GDS_GWS_RESET1__RESOURCE39_RESET_MASK 0x80
#define GDS_GWS_RESET1__RESOURCE39_RESET__SHIFT 0x7
#define GDS_GWS_RESET1__RESOURCE40_RESET_MASK 0x100
#define GDS_GWS_RESET1__RESOURCE40_RESET__SHIFT 0x8
#define GDS_GWS_RESET1__RESOURCE41_RESET_MASK 0x200
#define GDS_GWS_RESET1__RESOURCE41_RESET__SHIFT 0x9
#define GDS_GWS_RESET1__RESOURCE42_RESET_MASK 0x400
#define GDS_GWS_RESET1__RESOURCE42_RESET__SHIFT 0xa
#define GDS_GWS_RESET1__RESOURCE43_RESET_MASK 0x800
#define GDS_GWS_RESET1__RESOURCE43_RESET__SHIFT 0xb
#define GDS_GWS_RESET1__RESOURCE44_RESET_MASK 0x1000
#define GDS_GWS_RESET1__RESOURCE44_RESET__SHIFT 0xc
#define GDS_GWS_RESET1__RESOURCE45_RESET_MASK 0x2000
#define GDS_GWS_RESET1__RESOURCE45_RESET__SHIFT 0xd
#define GDS_GWS_RESET1__RESOURCE46_RESET_MASK 0x4000
#define GDS_GWS_RESET1__RESOURCE46_RESET__SHIFT 0xe
#define GDS_GWS_RESET1__RESOURCE47_RESET_MASK 0x8000
#define GDS_GWS_RESET1__RESOURCE47_RESET__SHIFT 0xf
#define GDS_GWS_RESET1__RESOURCE48_RESET_MASK 0x10000
#define GDS_GWS_RESET1__RESOURCE48_RESET__SHIFT 0x10
#define GDS_GWS_RESET1__RESOURCE49_RESET_MASK 0x20000
#define GDS_GWS_RESET1__RESOURCE49_RESET__SHIFT 0x11
#define GDS_GWS_RESET1__RESOURCE50_RESET_MASK 0x40000
#define GDS_GWS_RESET1__RESOURCE50_RESET__SHIFT 0x12
#define GDS_GWS_RESET1__RESOURCE51_RESET_MASK 0x80000
#define GDS_GWS_RESET1__RESOURCE51_RESET__SHIFT 0x13
#define GDS_GWS_RESET1__RESOURCE52_RESET_MASK 0x100000
#define GDS_GWS_RESET1__RESOURCE52_RESET__SHIFT 0x14
#define GDS_GWS_RESET1__RESOURCE53_RESET_MASK 0x200000
#define GDS_GWS_RESET1__RESOURCE53_RESET__SHIFT 0x15
#define GDS_GWS_RESET1__RESOURCE54_RESET_MASK 0x400000
#define GDS_GWS_RESET1__RESOURCE54_RESET__SHIFT 0x16
#define GDS_GWS_RESET1__RESOURCE55_RESET_MASK 0x800000
#define GDS_GWS_RESET1__RESOURCE55_RESET__SHIFT 0x17
#define GDS_GWS_RESET1__RESOURCE56_RESET_MASK 0x1000000
#define GDS_GWS_RESET1__RESOURCE56_RESET__SHIFT 0x18
#define GDS_GWS_RESET1__RESOURCE57_RESET_MASK 0x2000000
#define GDS_GWS_RESET1__RESOURCE57_RESET__SHIFT 0x19
#define GDS_GWS_RESET1__RESOURCE58_RESET_MASK 0x4000000
#define GDS_GWS_RESET1__RESOURCE58_RESET__SHIFT 0x1a
#define GDS_GWS_RESET1__RESOURCE59_RESET_MASK 0x8000000
#define GDS_GWS_RESET1__RESOURCE59_RESET__SHIFT 0x1b
#define GDS_GWS_RESET1__RESOURCE60_RESET_MASK 0x10000000
#define GDS_GWS_RESET1__RESOURCE60_RESET__SHIFT 0x1c
#define GDS_GWS_RESET1__RESOURCE61_RESET_MASK 0x20000000
#define GDS_GWS_RESET1__RESOURCE61_RESET__SHIFT 0x1d
#define GDS_GWS_RESET1__RESOURCE62_RESET_MASK 0x40000000
#define GDS_GWS_RESET1__RESOURCE62_RESET__SHIFT 0x1e
#define GDS_GWS_RESET1__RESOURCE63_RESET_MASK 0x80000000
#define GDS_GWS_RESET1__RESOURCE63_RESET__SHIFT 0x1f
#define GDS_GWS_RESOURCE_RESET__RESET_MASK 0x1
#define GDS_GWS_RESOURCE_RESET__RESET__SHIFT 0x0
#define GDS_GWS_RESOURCE_RESET__RESOURCE_ID_MASK 0xff00
#define GDS_GWS_RESOURCE_RESET__RESOURCE_ID__SHIFT 0x8
#define GDS_COMPUTE_MAX_WAVE_ID__MAX_WAVE_ID_MASK 0xfff
#define GDS_COMPUTE_MAX_WAVE_ID__MAX_WAVE_ID__SHIFT 0x0
#define GDS_OA_RESET_MASK__ME0_GFXHP3D_PIX_RESET_MASK 0x1
#define GDS_OA_RESET_MASK__ME0_GFXHP3D_PIX_RESET__SHIFT 0x0
#define GDS_OA_RESET_MASK__ME0_GFXHP3D_VTX_RESET_MASK 0x2
#define GDS_OA_RESET_MASK__ME0_GFXHP3D_VTX_RESET__SHIFT 0x1
#define GDS_OA_RESET_MASK__ME0_CS_RESET_MASK 0x4
#define GDS_OA_RESET_MASK__ME0_CS_RESET__SHIFT 0x2
#define GDS_OA_RESET_MASK__UNUSED0_MASK 0x8
#define GDS_OA_RESET_MASK__UNUSED0__SHIFT 0x3
#define GDS_OA_RESET_MASK__ME1_PIPE0_RESET_MASK 0x10
#define GDS_OA_RESET_MASK__ME1_PIPE0_RESET__SHIFT 0x4
#define GDS_OA_RESET_MASK__ME1_PIPE1_RESET_MASK 0x20
#define GDS_OA_RESET_MASK__ME1_PIPE1_RESET__SHIFT 0x5
#define GDS_OA_RESET_MASK__ME1_PIPE2_RESET_MASK 0x40
#define GDS_OA_RESET_MASK__ME1_PIPE2_RESET__SHIFT 0x6
#define GDS_OA_RESET_MASK__ME1_PIPE3_RESET_MASK 0x80
#define GDS_OA_RESET_MASK__ME1_PIPE3_RESET__SHIFT 0x7
#define GDS_OA_RESET_MASK__ME2_PIPE0_RESET_MASK 0x100
#define GDS_OA_RESET_MASK__ME2_PIPE0_RESET__SHIFT 0x8
#define GDS_OA_RESET_MASK__ME2_PIPE1_RESET_MASK 0x200
#define GDS_OA_RESET_MASK__ME2_PIPE1_RESET__SHIFT 0x9
#define GDS_OA_RESET_MASK__ME2_PIPE2_RESET_MASK 0x400
#define GDS_OA_RESET_MASK__ME2_PIPE2_RESET__SHIFT 0xa
#define GDS_OA_RESET_MASK__ME2_PIPE3_RESET_MASK 0x800
#define GDS_OA_RESET_MASK__ME2_PIPE3_RESET__SHIFT 0xb
#define GDS_OA_RESET_MASK__UNUSED1_MASK 0xfffff000
#define GDS_OA_RESET_MASK__UNUSED1__SHIFT 0xc
#define GDS_OA_RESET__RESET_MASK 0x1
#define GDS_OA_RESET__RESET__SHIFT 0x0
#define GDS_OA_RESET__PIPE_ID_MASK 0xff00
#define GDS_OA_RESET__PIPE_ID__SHIFT 0x8
#define GDS_ENHANCE__MISC_MASK 0xffff
#define GDS_ENHANCE__MISC__SHIFT 0x0
#define GDS_ENHANCE__AUTO_INC_INDEX_MASK 0x10000
#define GDS_ENHANCE__AUTO_INC_INDEX__SHIFT 0x10
#define GDS_ENHANCE__CGPG_RESTORE_MASK 0x20000
#define GDS_ENHANCE__CGPG_RESTORE__SHIFT 0x11
#define GDS_ENHANCE__UNUSED_MASK 0xfffc0000
#define GDS_ENHANCE__UNUSED__SHIFT 0x12
#define GDS_OA_CGPG_RESTORE__VMID_MASK 0xff
#define GDS_OA_CGPG_RESTORE__VMID__SHIFT 0x0
#define GDS_OA_CGPG_RESTORE__MEID_MASK 0xf00
#define GDS_OA_CGPG_RESTORE__MEID__SHIFT 0x8
#define GDS_OA_CGPG_RESTORE__PIPEID_MASK 0xf000
#define GDS_OA_CGPG_RESTORE__PIPEID__SHIFT 0xc
#define GDS_OA_CGPG_RESTORE__QUEUEID_MASK 0xf0000
#define GDS_OA_CGPG_RESTORE__QUEUEID__SHIFT 0x10
#define GDS_OA_CGPG_RESTORE__UNUSED_MASK 0xfff00000
#define GDS_OA_CGPG_RESTORE__UNUSED__SHIFT 0x14
#define GDS_CS_CTXSW_STATUS__R_MASK 0x1
#define GDS_CS_CTXSW_STATUS__R__SHIFT 0x0
#define GDS_CS_CTXSW_STATUS__W_MASK 0x2
#define GDS_CS_CTXSW_STATUS__W__SHIFT 0x1
#define GDS_CS_CTXSW_STATUS__UNUSED_MASK 0xfffffffc
#define GDS_CS_CTXSW_STATUS__UNUSED__SHIFT 0x2
#define GDS_CS_CTXSW_CNT0__UPDN_MASK 0xffff
#define GDS_CS_CTXSW_CNT0__UPDN__SHIFT 0x0
#define GDS_CS_CTXSW_CNT0__PTR_MASK 0xffff0000
#define GDS_CS_CTXSW_CNT0__PTR__SHIFT 0x10
#define GDS_CS_CTXSW_CNT1__UPDN_MASK 0xffff
#define GDS_CS_CTXSW_CNT1__UPDN__SHIFT 0x0
#define GDS_CS_CTXSW_CNT1__PTR_MASK 0xffff0000
#define GDS_CS_CTXSW_CNT1__PTR__SHIFT 0x10
#define GDS_CS_CTXSW_CNT2__UPDN_MASK 0xffff
#define GDS_CS_CTXSW_CNT2__UPDN__SHIFT 0x0
#define GDS_CS_CTXSW_CNT2__PTR_MASK 0xffff0000
#define GDS_CS_CTXSW_CNT2__PTR__SHIFT 0x10
#define GDS_CS_CTXSW_CNT3__UPDN_MASK 0xffff
#define GDS_CS_CTXSW_CNT3__UPDN__SHIFT 0x0
#define GDS_CS_CTXSW_CNT3__PTR_MASK 0xffff0000
#define GDS_CS_CTXSW_CNT3__PTR__SHIFT 0x10
#define GDS_GFX_CTXSW_STATUS__R_MASK 0x1
#define GDS_GFX_CTXSW_STATUS__R__SHIFT 0x0
#define GDS_GFX_CTXSW_STATUS__W_MASK 0x2
#define GDS_GFX_CTXSW_STATUS__W__SHIFT 0x1
#define GDS_GFX_CTXSW_STATUS__UNUSED_MASK 0xfffffffc
#define GDS_GFX_CTXSW_STATUS__UNUSED__SHIFT 0x2
#define GDS_VS_CTXSW_CNT0__UPDN_MASK 0xffff
#define GDS_VS_CTXSW_CNT0__UPDN__SHIFT 0x0
#define GDS_VS_CTXSW_CNT0__PTR_MASK 0xffff0000
#define GDS_VS_CTXSW_CNT0__PTR__SHIFT 0x10
#define GDS_VS_CTXSW_CNT1__UPDN_MASK 0xffff
#define GDS_VS_CTXSW_CNT1__UPDN__SHIFT 0x0
#define GDS_VS_CTXSW_CNT1__PTR_MASK 0xffff0000
#define GDS_VS_CTXSW_CNT1__PTR__SHIFT 0x10
#define GDS_VS_CTXSW_CNT2__UPDN_MASK 0xffff
#define GDS_VS_CTXSW_CNT2__UPDN__SHIFT 0x0
#define GDS_VS_CTXSW_CNT2__PTR_MASK 0xffff0000
#define GDS_VS_CTXSW_CNT2__PTR__SHIFT 0x10
#define GDS_VS_CTXSW_CNT3__UPDN_MASK 0xffff
#define GDS_VS_CTXSW_CNT3__UPDN__SHIFT 0x0
#define GDS_VS_CTXSW_CNT3__PTR_MASK 0xffff0000
#define GDS_VS_CTXSW_CNT3__PTR__SHIFT 0x10
#define GDS_PS0_CTXSW_CNT0__UPDN_MASK 0xffff
#define GDS_PS0_CTXSW_CNT0__UPDN__SHIFT 0x0
#define GDS_PS0_CTXSW_CNT0__PTR_MASK 0xffff0000
#define GDS_PS0_CTXSW_CNT0__PTR__SHIFT 0x10
#define GDS_PS1_CTXSW_CNT0__UPDN_MASK 0xffff
#define GDS_PS1_CTXSW_CNT0__UPDN__SHIFT 0x0
#define GDS_PS1_CTXSW_CNT0__PTR_MASK 0xffff0000
#define GDS_PS1_CTXSW_CNT0__PTR__SHIFT 0x10
#define GDS_PS2_CTXSW_CNT0__UPDN_MASK 0xffff
#define GDS_PS2_CTXSW_CNT0__UPDN__SHIFT 0x0
#define GDS_PS2_CTXSW_CNT0__PTR_MASK 0xffff0000
#define GDS_PS2_CTXSW_CNT0__PTR__SHIFT 0x10
#define GDS_PS3_CTXSW_CNT0__UPDN_MASK 0xffff
#define GDS_PS3_CTXSW_CNT0__UPDN__SHIFT 0x0
#define GDS_PS3_CTXSW_CNT0__PTR_MASK 0xffff0000
#define GDS_PS3_CTXSW_CNT0__PTR__SHIFT 0x10
#define GDS_PS4_CTXSW_CNT0__UPDN_MASK 0xffff
#define GDS_PS4_CTXSW_CNT0__UPDN__SHIFT 0x0
#define GDS_PS4_CTXSW_CNT0__PTR_MASK 0xffff0000
#define GDS_PS4_CTXSW_CNT0__PTR__SHIFT 0x10
#define GDS_PS5_CTXSW_CNT0__UPDN_MASK 0xffff
#define GDS_PS5_CTXSW_CNT0__UPDN__SHIFT 0x0
#define GDS_PS5_CTXSW_CNT0__PTR_MASK 0xffff0000
#define GDS_PS5_CTXSW_CNT0__PTR__SHIFT 0x10
#define GDS_PS6_CTXSW_CNT0__UPDN_MASK 0xffff
#define GDS_PS6_CTXSW_CNT0__UPDN__SHIFT 0x0
#define GDS_PS6_CTXSW_CNT0__PTR_MASK 0xffff0000
#define GDS_PS6_CTXSW_CNT0__PTR__SHIFT 0x10
#define GDS_PS7_CTXSW_CNT0__UPDN_MASK 0xffff
#define GDS_PS7_CTXSW_CNT0__UPDN__SHIFT 0x0
#define GDS_PS7_CTXSW_CNT0__PTR_MASK 0xffff0000
#define GDS_PS7_CTXSW_CNT0__PTR__SHIFT 0x10
#define GDS_PS0_CTXSW_CNT1__UPDN_MASK 0xffff
#define GDS_PS0_CTXSW_CNT1__UPDN__SHIFT 0x0
#define GDS_PS0_CTXSW_CNT1__PTR_MASK 0xffff0000
#define GDS_PS0_CTXSW_CNT1__PTR__SHIFT 0x10
#define GDS_PS1_CTXSW_CNT1__UPDN_MASK 0xffff
#define GDS_PS1_CTXSW_CNT1__UPDN__SHIFT 0x0
#define GDS_PS1_CTXSW_CNT1__PTR_MASK 0xffff0000
#define GDS_PS1_CTXSW_CNT1__PTR__SHIFT 0x10
#define GDS_PS2_CTXSW_CNT1__UPDN_MASK 0xffff
#define GDS_PS2_CTXSW_CNT1__UPDN__SHIFT 0x0
#define GDS_PS2_CTXSW_CNT1__PTR_MASK 0xffff0000
#define GDS_PS2_CTXSW_CNT1__PTR__SHIFT 0x10
#define GDS_PS3_CTXSW_CNT1__UPDN_MASK 0xffff
#define GDS_PS3_CTXSW_CNT1__UPDN__SHIFT 0x0
#define GDS_PS3_CTXSW_CNT1__PTR_MASK 0xffff0000
#define GDS_PS3_CTXSW_CNT1__PTR__SHIFT 0x10
#define GDS_PS4_CTXSW_CNT1__UPDN_MASK 0xffff
#define GDS_PS4_CTXSW_CNT1__UPDN__SHIFT 0x0
#define GDS_PS4_CTXSW_CNT1__PTR_MASK 0xffff0000
#define GDS_PS4_CTXSW_CNT1__PTR__SHIFT 0x10
#define GDS_PS5_CTXSW_CNT1__UPDN_MASK 0xffff
#define GDS_PS5_CTXSW_CNT1__UPDN__SHIFT 0x0
#define GDS_PS5_CTXSW_CNT1__PTR_MASK 0xffff0000
#define GDS_PS5_CTXSW_CNT1__PTR__SHIFT 0x10
#define GDS_PS6_CTXSW_CNT1__UPDN_MASK 0xffff
#define GDS_PS6_CTXSW_CNT1__UPDN__SHIFT 0x0
#define GDS_PS6_CTXSW_CNT1__PTR_MASK 0xffff0000
#define GDS_PS6_CTXSW_CNT1__PTR__SHIFT 0x10
#define GDS_PS7_CTXSW_CNT1__UPDN_MASK 0xffff
#define GDS_PS7_CTXSW_CNT1__UPDN__SHIFT 0x0
#define GDS_PS7_CTXSW_CNT1__PTR_MASK 0xffff0000
#define GDS_PS7_CTXSW_CNT1__PTR__SHIFT 0x10
#define GDS_PS0_CTXSW_CNT2__UPDN_MASK 0xffff
#define GDS_PS0_CTXSW_CNT2__UPDN__SHIFT 0x0
#define GDS_PS0_CTXSW_CNT2__PTR_MASK 0xffff0000
#define GDS_PS0_CTXSW_CNT2__PTR__SHIFT 0x10
#define GDS_PS1_CTXSW_CNT2__UPDN_MASK 0xffff
#define GDS_PS1_CTXSW_CNT2__UPDN__SHIFT 0x0
#define GDS_PS1_CTXSW_CNT2__PTR_MASK 0xffff0000
#define GDS_PS1_CTXSW_CNT2__PTR__SHIFT 0x10
#define GDS_PS2_CTXSW_CNT2__UPDN_MASK 0xffff
#define GDS_PS2_CTXSW_CNT2__UPDN__SHIFT 0x0
#define GDS_PS2_CTXSW_CNT2__PTR_MASK 0xffff0000
#define GDS_PS2_CTXSW_CNT2__PTR__SHIFT 0x10
#define GDS_PS3_CTXSW_CNT2__UPDN_MASK 0xffff
#define GDS_PS3_CTXSW_CNT2__UPDN__SHIFT 0x0
#define GDS_PS3_CTXSW_CNT2__PTR_MASK 0xffff0000
#define GDS_PS3_CTXSW_CNT2__PTR__SHIFT 0x10
#define GDS_PS4_CTXSW_CNT2__UPDN_MASK 0xffff
#define GDS_PS4_CTXSW_CNT2__UPDN__SHIFT 0x0
#define GDS_PS4_CTXSW_CNT2__PTR_MASK 0xffff0000
#define GDS_PS4_CTXSW_CNT2__PTR__SHIFT 0x10
#define GDS_PS5_CTXSW_CNT2__UPDN_MASK 0xffff
#define GDS_PS5_CTXSW_CNT2__UPDN__SHIFT 0x0
#define GDS_PS5_CTXSW_CNT2__PTR_MASK 0xffff0000
#define GDS_PS5_CTXSW_CNT2__PTR__SHIFT 0x10
#define GDS_PS6_CTXSW_CNT2__UPDN_MASK 0xffff
#define GDS_PS6_CTXSW_CNT2__UPDN__SHIFT 0x0
#define GDS_PS6_CTXSW_CNT2__PTR_MASK 0xffff0000
#define GDS_PS6_CTXSW_CNT2__PTR__SHIFT 0x10
#define GDS_PS7_CTXSW_CNT2__UPDN_MASK 0xffff
#define GDS_PS7_CTXSW_CNT2__UPDN__SHIFT 0x0
#define GDS_PS7_CTXSW_CNT2__PTR_MASK 0xffff0000
#define GDS_PS7_CTXSW_CNT2__PTR__SHIFT 0x10
#define GDS_PS0_CTXSW_CNT3__UPDN_MASK 0xffff
#define GDS_PS0_CTXSW_CNT3__UPDN__SHIFT 0x0
#define GDS_PS0_CTXSW_CNT3__PTR_MASK 0xffff0000
#define GDS_PS0_CTXSW_CNT3__PTR__SHIFT 0x10
#define GDS_PS1_CTXSW_CNT3__UPDN_MASK 0xffff
#define GDS_PS1_CTXSW_CNT3__UPDN__SHIFT 0x0
#define GDS_PS1_CTXSW_CNT3__PTR_MASK 0xffff0000
#define GDS_PS1_CTXSW_CNT3__PTR__SHIFT 0x10
#define GDS_PS2_CTXSW_CNT3__UPDN_MASK 0xffff
#define GDS_PS2_CTXSW_CNT3__UPDN__SHIFT 0x0
#define GDS_PS2_CTXSW_CNT3__PTR_MASK 0xffff0000
#define GDS_PS2_CTXSW_CNT3__PTR__SHIFT 0x10
#define GDS_PS3_CTXSW_CNT3__UPDN_MASK 0xffff
#define GDS_PS3_CTXSW_CNT3__UPDN__SHIFT 0x0
#define GDS_PS3_CTXSW_CNT3__PTR_MASK 0xffff0000
#define GDS_PS3_CTXSW_CNT3__PTR__SHIFT 0x10
#define GDS_PS4_CTXSW_CNT3__UPDN_MASK 0xffff
#define GDS_PS4_CTXSW_CNT3__UPDN__SHIFT 0x0
#define GDS_PS4_CTXSW_CNT3__PTR_MASK 0xffff0000
#define GDS_PS4_CTXSW_CNT3__PTR__SHIFT 0x10
#define GDS_PS5_CTXSW_CNT3__UPDN_MASK 0xffff
#define GDS_PS5_CTXSW_CNT3__UPDN__SHIFT 0x0
#define GDS_PS5_CTXSW_CNT3__PTR_MASK 0xffff0000
#define GDS_PS5_CTXSW_CNT3__PTR__SHIFT 0x10
#define GDS_PS6_CTXSW_CNT3__UPDN_MASK 0xffff
#define GDS_PS6_CTXSW_CNT3__UPDN__SHIFT 0x0
#define GDS_PS6_CTXSW_CNT3__PTR_MASK 0xffff0000
#define GDS_PS6_CTXSW_CNT3__PTR__SHIFT 0x10
#define GDS_PS7_CTXSW_CNT3__UPDN_MASK 0xffff
#define GDS_PS7_CTXSW_CNT3__UPDN__SHIFT 0x0
#define GDS_PS7_CTXSW_CNT3__PTR_MASK 0xffff0000
#define GDS_PS7_CTXSW_CNT3__PTR__SHIFT 0x10
#define CS_COPY_STATE__SRC_STATE_ID_MASK 0x7
#define CS_COPY_STATE__SRC_STATE_ID__SHIFT 0x0
#define GFX_COPY_STATE__SRC_STATE_ID_MASK 0x7
#define GFX_COPY_STATE__SRC_STATE_ID__SHIFT 0x0
#define VGT_DRAW_INITIATOR__SOURCE_SELECT_MASK 0x3
#define VGT_DRAW_INITIATOR__SOURCE_SELECT__SHIFT 0x0
#define VGT_DRAW_INITIATOR__MAJOR_MODE_MASK 0xc
#define VGT_DRAW_INITIATOR__MAJOR_MODE__SHIFT 0x2
#define VGT_DRAW_INITIATOR__SPRITE_EN_R6XX_MASK 0x10
#define VGT_DRAW_INITIATOR__SPRITE_EN_R6XX__SHIFT 0x4
#define VGT_DRAW_INITIATOR__NOT_EOP_MASK 0x20
#define VGT_DRAW_INITIATOR__NOT_EOP__SHIFT 0x5
#define VGT_DRAW_INITIATOR__USE_OPAQUE_MASK 0x40
#define VGT_DRAW_INITIATOR__USE_OPAQUE__SHIFT 0x6
#define VGT_EVENT_INITIATOR__EVENT_TYPE_MASK 0x3f
#define VGT_EVENT_INITIATOR__EVENT_TYPE__SHIFT 0x0
#define VGT_EVENT_INITIATOR__ADDRESS_HI_MASK 0x7fc0000
#define VGT_EVENT_INITIATOR__ADDRESS_HI__SHIFT 0x12
#define VGT_EVENT_INITIATOR__EXTENDED_EVENT_MASK 0x8000000
#define VGT_EVENT_INITIATOR__EXTENDED_EVENT__SHIFT 0x1b
#define VGT_EVENT_ADDRESS_REG__ADDRESS_LOW_MASK 0xfffffff
#define VGT_EVENT_ADDRESS_REG__ADDRESS_LOW__SHIFT 0x0
#define VGT_DMA_BASE_HI__BASE_ADDR_MASK 0xff
#define VGT_DMA_BASE_HI__BASE_ADDR__SHIFT 0x0
#define VGT_DMA_BASE__BASE_ADDR_MASK 0xffffffff
#define VGT_DMA_BASE__BASE_ADDR__SHIFT 0x0
#define VGT_DMA_INDEX_TYPE__INDEX_TYPE_MASK 0x3
#define VGT_DMA_INDEX_TYPE__INDEX_TYPE__SHIFT 0x0
#define VGT_DMA_INDEX_TYPE__SWAP_MODE_MASK 0xc
#define VGT_DMA_INDEX_TYPE__SWAP_MODE__SHIFT 0x2
#define VGT_DMA_INDEX_TYPE__BUF_TYPE_MASK 0x30
#define VGT_DMA_INDEX_TYPE__BUF_TYPE__SHIFT 0x4
#define VGT_DMA_INDEX_TYPE__RDREQ_POLICY_MASK 0x40
#define VGT_DMA_INDEX_TYPE__RDREQ_POLICY__SHIFT 0x6
#define VGT_DMA_INDEX_TYPE__NOT_EOP_MASK 0x200
#define VGT_DMA_INDEX_TYPE__NOT_EOP__SHIFT 0x9
#define VGT_DMA_INDEX_TYPE__REQ_PATH_MASK 0x400
#define VGT_DMA_INDEX_TYPE__REQ_PATH__SHIFT 0xa
#define VGT_DMA_INDEX_TYPE__MTYPE_MASK 0x1800
#define VGT_DMA_INDEX_TYPE__MTYPE__SHIFT 0xb
#define VGT_DMA_NUM_INSTANCES__NUM_INSTANCES_MASK 0xffffffff
#define VGT_DMA_NUM_INSTANCES__NUM_INSTANCES__SHIFT 0x0
#define IA_ENHANCE__MISC_MASK 0xffffffff
#define IA_ENHANCE__MISC__SHIFT 0x0
#define VGT_DMA_SIZE__NUM_INDICES_MASK 0xffffffff
#define VGT_DMA_SIZE__NUM_INDICES__SHIFT 0x0
#define VGT_DMA_MAX_SIZE__MAX_SIZE_MASK 0xffffffff
#define VGT_DMA_MAX_SIZE__MAX_SIZE__SHIFT 0x0
#define VGT_DMA_PRIMITIVE_TYPE__PRIM_TYPE_MASK 0x3f
#define VGT_DMA_PRIMITIVE_TYPE__PRIM_TYPE__SHIFT 0x0
#define VGT_DMA_CONTROL__PRIMGROUP_SIZE_MASK 0xffff
#define VGT_DMA_CONTROL__PRIMGROUP_SIZE__SHIFT 0x0
#define VGT_DMA_CONTROL__IA_SWITCH_ON_EOP_MASK 0x20000
#define VGT_DMA_CONTROL__IA_SWITCH_ON_EOP__SHIFT 0x11
#define VGT_DMA_CONTROL__WD_SWITCH_ON_EOP_MASK 0x100000
#define VGT_DMA_CONTROL__WD_SWITCH_ON_EOP__SHIFT 0x14
#define VGT_IMMED_DATA__DATA_MASK 0xffffffff
#define VGT_IMMED_DATA__DATA__SHIFT 0x0
#define VGT_INDEX_TYPE__INDEX_TYPE_MASK 0x3
#define VGT_INDEX_TYPE__INDEX_TYPE__SHIFT 0x0
#define VGT_NUM_INDICES__NUM_INDICES_MASK 0xffffffff
#define VGT_NUM_INDICES__NUM_INDICES__SHIFT 0x0
#define VGT_NUM_INSTANCES__NUM_INSTANCES_MASK 0xffffffff
#define VGT_NUM_INSTANCES__NUM_INSTANCES__SHIFT 0x0
#define VGT_PRIMITIVE_TYPE__PRIM_TYPE_MASK 0x3f
#define VGT_PRIMITIVE_TYPE__PRIM_TYPE__SHIFT 0x0
#define VGT_PRIMITIVEID_EN__PRIMITIVEID_EN_MASK 0x1
#define VGT_PRIMITIVEID_EN__PRIMITIVEID_EN__SHIFT 0x0
#define VGT_PRIMITIVEID_EN__DISABLE_RESET_ON_EOI_MASK 0x2
#define VGT_PRIMITIVEID_EN__DISABLE_RESET_ON_EOI__SHIFT 0x1
#define VGT_PRIMITIVEID_RESET__VALUE_MASK 0xffffffff
#define VGT_PRIMITIVEID_RESET__VALUE__SHIFT 0x0
#define VGT_VTX_CNT_EN__VTX_CNT_EN_MASK 0x1
#define VGT_VTX_CNT_EN__VTX_CNT_EN__SHIFT 0x0
#define VGT_REUSE_OFF__REUSE_OFF_MASK 0x1
#define VGT_REUSE_OFF__REUSE_OFF__SHIFT 0x0
#define VGT_INSTANCE_STEP_RATE_0__STEP_RATE_MASK 0xffffffff
#define VGT_INSTANCE_STEP_RATE_0__STEP_RATE__SHIFT 0x0
#define VGT_INSTANCE_STEP_RATE_1__STEP_RATE_MASK 0xffffffff
#define VGT_INSTANCE_STEP_RATE_1__STEP_RATE__SHIFT 0x0
#define VGT_MAX_VTX_INDX__MAX_INDX_MASK 0xffffffff
#define VGT_MAX_VTX_INDX__MAX_INDX__SHIFT 0x0
#define VGT_MIN_VTX_INDX__MIN_INDX_MASK 0xffffffff
#define VGT_MIN_VTX_INDX__MIN_INDX__SHIFT 0x0
#define VGT_INDX_OFFSET__INDX_OFFSET_MASK 0xffffffff
#define VGT_INDX_OFFSET__INDX_OFFSET__SHIFT 0x0
#define VGT_VERTEX_REUSE_BLOCK_CNTL__VTX_REUSE_DEPTH_MASK 0xff
#define VGT_VERTEX_REUSE_BLOCK_CNTL__VTX_REUSE_DEPTH__SHIFT 0x0
#define VGT_OUT_DEALLOC_CNTL__DEALLOC_DIST_MASK 0x7f
#define VGT_OUT_DEALLOC_CNTL__DEALLOC_DIST__SHIFT 0x0
#define VGT_MULTI_PRIM_IB_RESET_INDX__RESET_INDX_MASK 0xffffffff
#define VGT_MULTI_PRIM_IB_RESET_INDX__RESET_INDX__SHIFT 0x0
#define VGT_MULTI_PRIM_IB_RESET_EN__RESET_EN_MASK 0x1
#define VGT_MULTI_PRIM_IB_RESET_EN__RESET_EN__SHIFT 0x0
#define VGT_ENHANCE__MISC_MASK 0xffffffff
#define VGT_ENHANCE__MISC__SHIFT 0x0
#define VGT_OUTPUT_PATH_CNTL__PATH_SELECT_MASK 0x7
#define VGT_OUTPUT_PATH_CNTL__PATH_SELECT__SHIFT 0x0
#define VGT_HOS_CNTL__TESS_MODE_MASK 0x3
#define VGT_HOS_CNTL__TESS_MODE__SHIFT 0x0
#define VGT_HOS_MAX_TESS_LEVEL__MAX_TESS_MASK 0xffffffff
#define VGT_HOS_MAX_TESS_LEVEL__MAX_TESS__SHIFT 0x0
#define VGT_HOS_MIN_TESS_LEVEL__MIN_TESS_MASK 0xffffffff
#define VGT_HOS_MIN_TESS_LEVEL__MIN_TESS__SHIFT 0x0
#define VGT_HOS_REUSE_DEPTH__REUSE_DEPTH_MASK 0xff
#define VGT_HOS_REUSE_DEPTH__REUSE_DEPTH__SHIFT 0x0
#define VGT_GROUP_PRIM_TYPE__PRIM_TYPE_MASK 0x1f
#define VGT_GROUP_PRIM_TYPE__PRIM_TYPE__SHIFT 0x0
#define VGT_GROUP_PRIM_TYPE__RETAIN_ORDER_MASK 0x4000
#define VGT_GROUP_PRIM_TYPE__RETAIN_ORDER__SHIFT 0xe
#define VGT_GROUP_PRIM_TYPE__RETAIN_QUADS_MASK 0x8000
#define VGT_GROUP_PRIM_TYPE__RETAIN_QUADS__SHIFT 0xf
#define VGT_GROUP_PRIM_TYPE__PRIM_ORDER_MASK 0x70000
#define VGT_GROUP_PRIM_TYPE__PRIM_ORDER__SHIFT 0x10
#define VGT_GROUP_FIRST_DECR__FIRST_DECR_MASK 0xf
#define VGT_GROUP_FIRST_DECR__FIRST_DECR__SHIFT 0x0
#define VGT_GROUP_DECR__DECR_MASK 0xf
#define VGT_GROUP_DECR__DECR__SHIFT 0x0
#define VGT_GROUP_VECT_0_CNTL__COMP_X_EN_MASK 0x1
#define VGT_GROUP_VECT_0_CNTL__COMP_X_EN__SHIFT 0x0
#define VGT_GROUP_VECT_0_CNTL__COMP_Y_EN_MASK 0x2
#define VGT_GROUP_VECT_0_CNTL__COMP_Y_EN__SHIFT 0x1
#define VGT_GROUP_VECT_0_CNTL__COMP_Z_EN_MASK 0x4
#define VGT_GROUP_VECT_0_CNTL__COMP_Z_EN__SHIFT 0x2
#define VGT_GROUP_VECT_0_CNTL__COMP_W_EN_MASK 0x8
#define VGT_GROUP_VECT_0_CNTL__COMP_W_EN__SHIFT 0x3
#define VGT_GROUP_VECT_0_CNTL__STRIDE_MASK 0xff00
#define VGT_GROUP_VECT_0_CNTL__STRIDE__SHIFT 0x8
#define VGT_GROUP_VECT_0_CNTL__SHIFT_MASK 0xff0000
#define VGT_GROUP_VECT_0_CNTL__SHIFT__SHIFT 0x10
#define VGT_GROUP_VECT_1_CNTL__COMP_X_EN_MASK 0x1
#define VGT_GROUP_VECT_1_CNTL__COMP_X_EN__SHIFT 0x0
#define VGT_GROUP_VECT_1_CNTL__COMP_Y_EN_MASK 0x2
#define VGT_GROUP_VECT_1_CNTL__COMP_Y_EN__SHIFT 0x1
#define VGT_GROUP_VECT_1_CNTL__COMP_Z_EN_MASK 0x4
#define VGT_GROUP_VECT_1_CNTL__COMP_Z_EN__SHIFT 0x2
#define VGT_GROUP_VECT_1_CNTL__COMP_W_EN_MASK 0x8
#define VGT_GROUP_VECT_1_CNTL__COMP_W_EN__SHIFT 0x3
#define VGT_GROUP_VECT_1_CNTL__STRIDE_MASK 0xff00
#define VGT_GROUP_VECT_1_CNTL__STRIDE__SHIFT 0x8
#define VGT_GROUP_VECT_1_CNTL__SHIFT_MASK 0xff0000
#define VGT_GROUP_VECT_1_CNTL__SHIFT__SHIFT 0x10
#define VGT_GROUP_VECT_0_FMT_CNTL__X_CONV_MASK 0xf
#define VGT_GROUP_VECT_0_FMT_CNTL__X_CONV__SHIFT 0x0
#define VGT_GROUP_VECT_0_FMT_CNTL__X_OFFSET_MASK 0xf0
#define VGT_GROUP_VECT_0_FMT_CNTL__X_OFFSET__SHIFT 0x4
#define VGT_GROUP_VECT_0_FMT_CNTL__Y_CONV_MASK 0xf00
#define VGT_GROUP_VECT_0_FMT_CNTL__Y_CONV__SHIFT 0x8
#define VGT_GROUP_VECT_0_FMT_CNTL__Y_OFFSET_MASK 0xf000
#define VGT_GROUP_VECT_0_FMT_CNTL__Y_OFFSET__SHIFT 0xc
#define VGT_GROUP_VECT_0_FMT_CNTL__Z_CONV_MASK 0xf0000
#define VGT_GROUP_VECT_0_FMT_CNTL__Z_CONV__SHIFT 0x10
#define VGT_GROUP_VECT_0_FMT_CNTL__Z_OFFSET_MASK 0xf00000
#define VGT_GROUP_VECT_0_FMT_CNTL__Z_OFFSET__SHIFT 0x14
#define VGT_GROUP_VECT_0_FMT_CNTL__W_CONV_MASK 0xf000000
#define VGT_GROUP_VECT_0_FMT_CNTL__W_CONV__SHIFT 0x18
#define VGT_GROUP_VECT_0_FMT_CNTL__W_OFFSET_MASK 0xf0000000
#define VGT_GROUP_VECT_0_FMT_CNTL__W_OFFSET__SHIFT 0x1c
#define VGT_GROUP_VECT_1_FMT_CNTL__X_CONV_MASK 0xf
#define VGT_GROUP_VECT_1_FMT_CNTL__X_CONV__SHIFT 0x0
#define VGT_GROUP_VECT_1_FMT_CNTL__X_OFFSET_MASK 0xf0
#define VGT_GROUP_VECT_1_FMT_CNTL__X_OFFSET__SHIFT 0x4
#define VGT_GROUP_VECT_1_FMT_CNTL__Y_CONV_MASK 0xf00
#define VGT_GROUP_VECT_1_FMT_CNTL__Y_CONV__SHIFT 0x8
#define VGT_GROUP_VECT_1_FMT_CNTL__Y_OFFSET_MASK 0xf000
#define VGT_GROUP_VECT_1_FMT_CNTL__Y_OFFSET__SHIFT 0xc
#define VGT_GROUP_VECT_1_FMT_CNTL__Z_CONV_MASK 0xf0000
#define VGT_GROUP_VECT_1_FMT_CNTL__Z_CONV__SHIFT 0x10
#define VGT_GROUP_VECT_1_FMT_CNTL__Z_OFFSET_MASK 0xf00000
#define VGT_GROUP_VECT_1_FMT_CNTL__Z_OFFSET__SHIFT 0x14
#define VGT_GROUP_VECT_1_FMT_CNTL__W_CONV_MASK 0xf000000
#define VGT_GROUP_VECT_1_FMT_CNTL__W_CONV__SHIFT 0x18
#define VGT_GROUP_VECT_1_FMT_CNTL__W_OFFSET_MASK 0xf0000000
#define VGT_GROUP_VECT_1_FMT_CNTL__W_OFFSET__SHIFT 0x1c
#define VGT_VTX_VECT_EJECT_REG__PRIM_COUNT_MASK 0x3ff
#define VGT_VTX_VECT_EJECT_REG__PRIM_COUNT__SHIFT 0x0
#define VGT_DMA_DATA_FIFO_DEPTH__DMA_DATA_FIFO_DEPTH_MASK 0x1ff
#define VGT_DMA_DATA_FIFO_DEPTH__DMA_DATA_FIFO_DEPTH__SHIFT 0x0
#define VGT_DMA_REQ_FIFO_DEPTH__DMA_REQ_FIFO_DEPTH_MASK 0x3f
#define VGT_DMA_REQ_FIFO_DEPTH__DMA_REQ_FIFO_DEPTH__SHIFT 0x0
#define VGT_DRAW_INIT_FIFO_DEPTH__DRAW_INIT_FIFO_DEPTH_MASK 0x3f
#define VGT_DRAW_INIT_FIFO_DEPTH__DRAW_INIT_FIFO_DEPTH__SHIFT 0x0
#define VGT_LAST_COPY_STATE__SRC_STATE_ID_MASK 0x7
#define VGT_LAST_COPY_STATE__SRC_STATE_ID__SHIFT 0x0
#define VGT_LAST_COPY_STATE__DST_STATE_ID_MASK 0x70000
#define VGT_LAST_COPY_STATE__DST_STATE_ID__SHIFT 0x10
#define CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK 0xffff0000
#define CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT 0x10
#define GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK 0xffff0000
#define GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT 0x10
#define VGT_GS_MODE__MODE_MASK 0x7
#define VGT_GS_MODE__MODE__SHIFT 0x0
#define VGT_GS_MODE__RESERVED_0_MASK 0x8
#define VGT_GS_MODE__RESERVED_0__SHIFT 0x3
#define VGT_GS_MODE__CUT_MODE_MASK 0x30
#define VGT_GS_MODE__CUT_MODE__SHIFT 0x4
#define VGT_GS_MODE__RESERVED_1_MASK 0x7c0
#define VGT_GS_MODE__RESERVED_1__SHIFT 0x6
#define VGT_GS_MODE__GS_C_PACK_EN_MASK 0x800
#define VGT_GS_MODE__GS_C_PACK_EN__SHIFT 0xb
#define VGT_GS_MODE__RESERVED_2_MASK 0x1000
#define VGT_GS_MODE__RESERVED_2__SHIFT 0xc
#define VGT_GS_MODE__ES_PASSTHRU_MASK 0x2000
#define VGT_GS_MODE__ES_PASSTHRU__SHIFT 0xd
#define VGT_GS_MODE__RESERVED_3_MASK 0x4000
#define VGT_GS_MODE__RESERVED_3__SHIFT 0xe
#define VGT_GS_MODE__RESERVED_4_MASK 0x8000
#define VGT_GS_MODE__RESERVED_4__SHIFT 0xf
#define VGT_GS_MODE__RESERVED_5_MASK 0x10000
#define VGT_GS_MODE__RESERVED_5__SHIFT 0x10
#define VGT_GS_MODE__PARTIAL_THD_AT_EOI_MASK 0x20000
#define VGT_GS_MODE__PARTIAL_THD_AT_EOI__SHIFT 0x11
#define VGT_GS_MODE__SUPPRESS_CUTS_MASK 0x40000
#define VGT_GS_MODE__SUPPRESS_CUTS__SHIFT 0x12
#define VGT_GS_MODE__ES_WRITE_OPTIMIZE_MASK 0x80000
#define VGT_GS_MODE__ES_WRITE_OPTIMIZE__SHIFT 0x13
#define VGT_GS_MODE__GS_WRITE_OPTIMIZE_MASK 0x100000
#define VGT_GS_MODE__GS_WRITE_OPTIMIZE__SHIFT 0x14
#define VGT_GS_MODE__ONCHIP_MASK 0x600000
#define VGT_GS_MODE__ONCHIP__SHIFT 0x15
#define VGT_GS_ONCHIP_CNTL__ES_VERTS_PER_SUBGRP_MASK 0x7ff
#define VGT_GS_ONCHIP_CNTL__ES_VERTS_PER_SUBGRP__SHIFT 0x0
#define VGT_GS_ONCHIP_CNTL__GS_PRIMS_PER_SUBGRP_MASK 0x3ff800
#define VGT_GS_ONCHIP_CNTL__GS_PRIMS_PER_SUBGRP__SHIFT 0xb
#define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_MASK 0x3f
#define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE__SHIFT 0x0
#define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_1_MASK 0x3f00
#define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_1__SHIFT 0x8
#define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_2_MASK 0x3f0000
#define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_2__SHIFT 0x10
#define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_3_MASK 0xfc00000
#define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_3__SHIFT 0x16
#define VGT_GS_OUT_PRIM_TYPE__UNIQUE_TYPE_PER_STREAM_MASK 0x80000000
#define VGT_GS_OUT_PRIM_TYPE__UNIQUE_TYPE_PER_STREAM__SHIFT 0x1f
#define VGT_CACHE_INVALIDATION__CACHE_INVALIDATION_MASK 0x3
#define VGT_CACHE_INVALIDATION__CACHE_INVALIDATION__SHIFT 0x0
#define VGT_CACHE_INVALIDATION__DIS_INSTANCING_OPT_MASK 0x10
#define VGT_CACHE_INVALIDATION__DIS_INSTANCING_OPT__SHIFT 0x4
#define VGT_CACHE_INVALIDATION__VS_NO_EXTRA_BUFFER_MASK 0x20
#define VGT_CACHE_INVALIDATION__VS_NO_EXTRA_BUFFER__SHIFT 0x5
#define VGT_CACHE_INVALIDATION__AUTO_INVLD_EN_MASK 0xc0
#define VGT_CACHE_INVALIDATION__AUTO_INVLD_EN__SHIFT 0x6
#define VGT_CACHE_INVALIDATION__USE_GS_DONE_MASK 0x200
#define VGT_CACHE_INVALIDATION__USE_GS_DONE__SHIFT 0x9
#define VGT_CACHE_INVALIDATION__DIS_RANGE_FULL_INVLD_MASK 0x800
#define VGT_CACHE_INVALIDATION__DIS_RANGE_FULL_INVLD__SHIFT 0xb
#define VGT_CACHE_INVALIDATION__GS_LATE_ALLOC_EN_MASK 0x1000
#define VGT_CACHE_INVALIDATION__GS_LATE_ALLOC_EN__SHIFT 0xc
#define VGT_CACHE_INVALIDATION__STREAMOUT_FULL_FLUSH_MASK 0x2000
#define VGT_CACHE_INVALIDATION__STREAMOUT_FULL_FLUSH__SHIFT 0xd
#define VGT_CACHE_INVALIDATION__ES_LIMIT_MASK 0x1f0000
#define VGT_CACHE_INVALIDATION__ES_LIMIT__SHIFT 0x10
#define VGT_RESET_DEBUG__GS_DISABLE_MASK 0x1
#define VGT_RESET_DEBUG__GS_DISABLE__SHIFT 0x0
#define VGT_RESET_DEBUG__TESS_DISABLE_MASK 0x2
#define VGT_RESET_DEBUG__TESS_DISABLE__SHIFT 0x1
#define VGT_RESET_DEBUG__WD_DISABLE_MASK 0x4
#define VGT_RESET_DEBUG__WD_DISABLE__SHIFT 0x2
#define VGT_STRMOUT_DELAY__SKIP_DELAY_MASK 0xff
#define VGT_STRMOUT_DELAY__SKIP_DELAY__SHIFT 0x0
#define VGT_STRMOUT_DELAY__SE0_WD_DELAY_MASK 0x700
#define VGT_STRMOUT_DELAY__SE0_WD_DELAY__SHIFT 0x8
#define VGT_STRMOUT_DELAY__SE1_WD_DELAY_MASK 0x3800
#define VGT_STRMOUT_DELAY__SE1_WD_DELAY__SHIFT 0xb
#define VGT_STRMOUT_DELAY__SE2_WD_DELAY_MASK 0x1c000
#define VGT_STRMOUT_DELAY__SE2_WD_DELAY__SHIFT 0xe
#define VGT_STRMOUT_DELAY__SE3_WD_DELAY_MASK 0xe0000
#define VGT_STRMOUT_DELAY__SE3_WD_DELAY__SHIFT 0x11
#define VGT_FIFO_DEPTHS__VS_DEALLOC_TBL_DEPTH_MASK 0x7f
#define VGT_FIFO_DEPTHS__VS_DEALLOC_TBL_DEPTH__SHIFT 0x0
#define VGT_FIFO_DEPTHS__RESERVED_0_MASK 0x80
#define VGT_FIFO_DEPTHS__RESERVED_0__SHIFT 0x7
#define VGT_FIFO_DEPTHS__CLIPP_FIFO_DEPTH_MASK 0x3fff00
#define VGT_FIFO_DEPTHS__CLIPP_FIFO_DEPTH__SHIFT 0x8
#define VGT_FIFO_DEPTHS__HSINPUT_FIFO_DEPTH_MASK 0xfc00000
#define VGT_FIFO_DEPTHS__HSINPUT_FIFO_DEPTH__SHIFT 0x16
#define VGT_GS_PER_ES__GS_PER_ES_MASK 0x7ff
#define VGT_GS_PER_ES__GS_PER_ES__SHIFT 0x0
#define VGT_ES_PER_GS__ES_PER_GS_MASK 0x7ff
#define VGT_ES_PER_GS__ES_PER_GS__SHIFT 0x0
#define VGT_GS_PER_VS__GS_PER_VS_MASK 0xf
#define VGT_GS_PER_VS__GS_PER_VS__SHIFT 0x0
#define VGT_GS_VERTEX_REUSE__VERT_REUSE_MASK 0x1f
#define VGT_GS_VERTEX_REUSE__VERT_REUSE__SHIFT 0x0
#define VGT_MC_LAT_CNTL__MC_TIME_STAMP_RES_MASK 0x3
#define VGT_MC_LAT_CNTL__MC_TIME_STAMP_RES__SHIFT 0x0
#define IA_CNTL_STATUS__IA_BUSY_MASK 0x1
#define IA_CNTL_STATUS__IA_BUSY__SHIFT 0x0
#define IA_CNTL_STATUS__IA_DMA_BUSY_MASK 0x2
#define IA_CNTL_STATUS__IA_DMA_BUSY__SHIFT 0x1
#define IA_CNTL_STATUS__IA_DMA_REQ_BUSY_MASK 0x4
#define IA_CNTL_STATUS__IA_DMA_REQ_BUSY__SHIFT 0x2
#define IA_CNTL_STATUS__IA_GRP_BUSY_MASK 0x8
#define IA_CNTL_STATUS__IA_GRP_BUSY__SHIFT 0x3
#define IA_CNTL_STATUS__IA_ADC_BUSY_MASK 0x10
#define IA_CNTL_STATUS__IA_ADC_BUSY__SHIFT 0x4
#define VGT_STRMOUT_CONFIG__STREAMOUT_0_EN_MASK 0x1
#define VGT_STRMOUT_CONFIG__STREAMOUT_0_EN__SHIFT 0x0
#define VGT_STRMOUT_CONFIG__STREAMOUT_1_EN_MASK 0x2
#define VGT_STRMOUT_CONFIG__STREAMOUT_1_EN__SHIFT 0x1
#define VGT_STRMOUT_CONFIG__STREAMOUT_2_EN_MASK 0x4
#define VGT_STRMOUT_CONFIG__STREAMOUT_2_EN__SHIFT 0x2
#define VGT_STRMOUT_CONFIG__STREAMOUT_3_EN_MASK 0x8
#define VGT_STRMOUT_CONFIG__STREAMOUT_3_EN__SHIFT 0x3
#define VGT_STRMOUT_CONFIG__RAST_STREAM_MASK 0x70
#define VGT_STRMOUT_CONFIG__RAST_STREAM__SHIFT 0x4
#define VGT_STRMOUT_CONFIG__RAST_STREAM_MASK_MASK 0xf00
#define VGT_STRMOUT_CONFIG__RAST_STREAM_MASK__SHIFT 0x8
#define VGT_STRMOUT_CONFIG__USE_RAST_STREAM_MASK_MASK 0x80000000
#define VGT_STRMOUT_CONFIG__USE_RAST_STREAM_MASK__SHIFT 0x1f
#define VGT_STRMOUT_BUFFER_SIZE_0__SIZE_MASK 0xffffffff
#define VGT_STRMOUT_BUFFER_SIZE_0__SIZE__SHIFT 0x0
#define VGT_STRMOUT_BUFFER_SIZE_1__SIZE_MASK 0xffffffff
#define VGT_STRMOUT_BUFFER_SIZE_1__SIZE__SHIFT 0x0
#define VGT_STRMOUT_BUFFER_SIZE_2__SIZE_MASK 0xffffffff
#define VGT_STRMOUT_BUFFER_SIZE_2__SIZE__SHIFT 0x0
#define VGT_STRMOUT_BUFFER_SIZE_3__SIZE_MASK 0xffffffff
#define VGT_STRMOUT_BUFFER_SIZE_3__SIZE__SHIFT 0x0
#define VGT_STRMOUT_BUFFER_OFFSET_0__OFFSET_MASK 0xffffffff
#define VGT_STRMOUT_BUFFER_OFFSET_0__OFFSET__SHIFT 0x0
#define VGT_STRMOUT_BUFFER_OFFSET_1__OFFSET_MASK 0xffffffff
#define VGT_STRMOUT_BUFFER_OFFSET_1__OFFSET__SHIFT 0x0
#define VGT_STRMOUT_BUFFER_OFFSET_2__OFFSET_MASK 0xffffffff
#define VGT_STRMOUT_BUFFER_OFFSET_2__OFFSET__SHIFT 0x0
#define VGT_STRMOUT_BUFFER_OFFSET_3__OFFSET_MASK 0xffffffff
#define VGT_STRMOUT_BUFFER_OFFSET_3__OFFSET__SHIFT 0x0
#define VGT_STRMOUT_VTX_STRIDE_0__STRIDE_MASK 0x3ff
#define VGT_STRMOUT_VTX_STRIDE_0__STRIDE__SHIFT 0x0
#define VGT_STRMOUT_VTX_STRIDE_1__STRIDE_MASK 0x3ff
#define VGT_STRMOUT_VTX_STRIDE_1__STRIDE__SHIFT 0x0
#define VGT_STRMOUT_VTX_STRIDE_2__STRIDE_MASK 0x3ff
#define VGT_STRMOUT_VTX_STRIDE_2__STRIDE__SHIFT 0x0
#define VGT_STRMOUT_VTX_STRIDE_3__STRIDE_MASK 0x3ff
#define VGT_STRMOUT_VTX_STRIDE_3__STRIDE__SHIFT 0x0
#define VGT_STRMOUT_BUFFER_CONFIG__STREAM_0_BUFFER_EN_MASK 0xf
#define VGT_STRMOUT_BUFFER_CONFIG__STREAM_0_BUFFER_EN__SHIFT 0x0
#define VGT_STRMOUT_BUFFER_CONFIG__STREAM_1_BUFFER_EN_MASK 0xf0
#define VGT_STRMOUT_BUFFER_CONFIG__STREAM_1_BUFFER_EN__SHIFT 0x4
#define VGT_STRMOUT_BUFFER_CONFIG__STREAM_2_BUFFER_EN_MASK 0xf00
#define VGT_STRMOUT_BUFFER_CONFIG__STREAM_2_BUFFER_EN__SHIFT 0x8
#define VGT_STRMOUT_BUFFER_CONFIG__STREAM_3_BUFFER_EN_MASK 0xf000
#define VGT_STRMOUT_BUFFER_CONFIG__STREAM_3_BUFFER_EN__SHIFT 0xc
#define VGT_STRMOUT_BUFFER_FILLED_SIZE_0__SIZE_MASK 0xffffffff
#define VGT_STRMOUT_BUFFER_FILLED_SIZE_0__SIZE__SHIFT 0x0
#define VGT_STRMOUT_BUFFER_FILLED_SIZE_1__SIZE_MASK 0xffffffff
#define VGT_STRMOUT_BUFFER_FILLED_SIZE_1__SIZE__SHIFT 0x0
#define VGT_STRMOUT_BUFFER_FILLED_SIZE_2__SIZE_MASK 0xffffffff
#define VGT_STRMOUT_BUFFER_FILLED_SIZE_2__SIZE__SHIFT 0x0
#define VGT_STRMOUT_BUFFER_FILLED_SIZE_3__SIZE_MASK 0xffffffff
#define VGT_STRMOUT_BUFFER_FILLED_SIZE_3__SIZE__SHIFT 0x0
#define VGT_STRMOUT_DRAW_OPAQUE_OFFSET__OFFSET_MASK 0xffffffff
#define VGT_STRMOUT_DRAW_OPAQUE_OFFSET__OFFSET__SHIFT 0x0
#define VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE__SIZE_MASK 0xffffffff
#define VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE__SIZE__SHIFT 0x0
#define VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE__VERTEX_STRIDE_MASK 0x1ff
#define VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE__VERTEX_STRIDE__SHIFT 0x0
#define VGT_GS_MAX_VERT_OUT__MAX_VERT_OUT_MASK 0x7ff
#define VGT_GS_MAX_VERT_OUT__MAX_VERT_OUT__SHIFT 0x0
#define VGT_SHADER_STAGES_EN__LS_EN_MASK 0x3
#define VGT_SHADER_STAGES_EN__LS_EN__SHIFT 0x0
#define VGT_SHADER_STAGES_EN__HS_EN_MASK 0x4
#define VGT_SHADER_STAGES_EN__HS_EN__SHIFT 0x2
#define VGT_SHADER_STAGES_EN__ES_EN_MASK 0x18
#define VGT_SHADER_STAGES_EN__ES_EN__SHIFT 0x3
#define VGT_SHADER_STAGES_EN__GS_EN_MASK 0x20
#define VGT_SHADER_STAGES_EN__GS_EN__SHIFT 0x5
#define VGT_SHADER_STAGES_EN__VS_EN_MASK 0xc0
#define VGT_SHADER_STAGES_EN__VS_EN__SHIFT 0x6
#define VGT_SHADER_STAGES_EN__DYNAMIC_HS_MASK 0x100
#define VGT_SHADER_STAGES_EN__DYNAMIC_HS__SHIFT 0x8
#define VGT_SHADER_STAGES_EN__DISPATCH_DRAW_EN_MASK 0x200
#define VGT_SHADER_STAGES_EN__DISPATCH_DRAW_EN__SHIFT 0x9
#define VGT_SHADER_STAGES_EN__DIS_DEALLOC_ACCUM_0_MASK 0x400
#define VGT_SHADER_STAGES_EN__DIS_DEALLOC_ACCUM_0__SHIFT 0xa
#define VGT_SHADER_STAGES_EN__DIS_DEALLOC_ACCUM_1_MASK 0x800
#define VGT_SHADER_STAGES_EN__DIS_DEALLOC_ACCUM_1__SHIFT 0xb
#define VGT_SHADER_STAGES_EN__VS_WAVE_ID_EN_MASK 0x1000
#define VGT_SHADER_STAGES_EN__VS_WAVE_ID_EN__SHIFT 0xc
#define VGT_DISPATCH_DRAW_INDEX__MATCH_INDEX_MASK 0xffffffff
#define VGT_DISPATCH_DRAW_INDEX__MATCH_INDEX__SHIFT 0x0
#define VGT_LS_HS_CONFIG__NUM_PATCHES_MASK 0xff
#define VGT_LS_HS_CONFIG__NUM_PATCHES__SHIFT 0x0
#define VGT_LS_HS_CONFIG__HS_NUM_INPUT_CP_MASK 0x3f00
#define VGT_LS_HS_CONFIG__HS_NUM_INPUT_CP__SHIFT 0x8
#define VGT_LS_HS_CONFIG__HS_NUM_OUTPUT_CP_MASK 0xfc000
#define VGT_LS_HS_CONFIG__HS_NUM_OUTPUT_CP__SHIFT 0xe
#define VGT_DMA_LS_HS_CONFIG__HS_NUM_INPUT_CP_MASK 0x3f00
#define VGT_DMA_LS_HS_CONFIG__HS_NUM_INPUT_CP__SHIFT 0x8
#define VGT_TF_PARAM__TYPE_MASK 0x3
#define VGT_TF_PARAM__TYPE__SHIFT 0x0
#define VGT_TF_PARAM__PARTITIONING_MASK 0x1c
#define VGT_TF_PARAM__PARTITIONING__SHIFT 0x2
#define VGT_TF_PARAM__TOPOLOGY_MASK 0xe0
#define VGT_TF_PARAM__TOPOLOGY__SHIFT 0x5
#define VGT_TF_PARAM__RESERVED_REDUC_AXIS_MASK 0x100
#define VGT_TF_PARAM__RESERVED_REDUC_AXIS__SHIFT 0x8
#define VGT_TF_PARAM__DEPRECATED_MASK 0x200
#define VGT_TF_PARAM__DEPRECATED__SHIFT 0x9
#define VGT_TF_PARAM__NUM_DS_WAVES_PER_SIMD_MASK 0x3c00
#define VGT_TF_PARAM__NUM_DS_WAVES_PER_SIMD__SHIFT 0xa
#define VGT_TF_PARAM__DISABLE_DONUTS_MASK 0x4000
#define VGT_TF_PARAM__DISABLE_DONUTS__SHIFT 0xe
#define VGT_TF_PARAM__RDREQ_POLICY_MASK 0x8000
#define VGT_TF_PARAM__RDREQ_POLICY__SHIFT 0xf
#define VGT_TF_PARAM__DISTRIBUTION_MODE_MASK 0x60000
#define VGT_TF_PARAM__DISTRIBUTION_MODE__SHIFT 0x11
#define VGT_TF_PARAM__MTYPE_MASK 0x180000
#define VGT_TF_PARAM__MTYPE__SHIFT 0x13
#define VGT_TESS_DISTRIBUTION__ACCUM_ISOLINE_MASK 0xff
#define VGT_TESS_DISTRIBUTION__ACCUM_ISOLINE__SHIFT 0x0
#define VGT_TESS_DISTRIBUTION__ACCUM_TRI_MASK 0xff00
#define VGT_TESS_DISTRIBUTION__ACCUM_TRI__SHIFT 0x8
#define VGT_TESS_DISTRIBUTION__ACCUM_QUAD_MASK 0xff0000
#define VGT_TESS_DISTRIBUTION__ACCUM_QUAD__SHIFT 0x10
#define VGT_TF_RING_SIZE__SIZE_MASK 0xffff
#define VGT_TF_RING_SIZE__SIZE__SHIFT 0x0
#define VGT_SYS_CONFIG__DUAL_CORE_EN_MASK 0x1
#define VGT_SYS_CONFIG__DUAL_CORE_EN__SHIFT 0x0
#define VGT_SYS_CONFIG__MAX_LS_HS_THDGRP_MASK 0x7e
#define VGT_SYS_CONFIG__MAX_LS_HS_THDGRP__SHIFT 0x1
#define VGT_SYS_CONFIG__ADC_EVENT_FILTER_DISABLE_MASK 0x80
#define VGT_SYS_CONFIG__ADC_EVENT_FILTER_DISABLE__SHIFT 0x7
#define VGT_HS_OFFCHIP_PARAM__OFFCHIP_BUFFERING_MASK 0x1ff
#define VGT_HS_OFFCHIP_PARAM__OFFCHIP_BUFFERING__SHIFT 0x0
#define VGT_HS_OFFCHIP_PARAM__OFFCHIP_GRANULARITY_MASK 0x600
#define VGT_HS_OFFCHIP_PARAM__OFFCHIP_GRANULARITY__SHIFT 0x9
#define VGT_TF_MEMORY_BASE__BASE_MASK 0xffffffff
#define VGT_TF_MEMORY_BASE__BASE__SHIFT 0x0
#define VGT_GS_INSTANCE_CNT__ENABLE_MASK 0x1
#define VGT_GS_INSTANCE_CNT__ENABLE__SHIFT 0x0
#define VGT_GS_INSTANCE_CNT__CNT_MASK 0x1fc
#define VGT_GS_INSTANCE_CNT__CNT__SHIFT 0x2
#define IA_MULTI_VGT_PARAM__PRIMGROUP_SIZE_MASK 0xffff
#define IA_MULTI_VGT_PARAM__PRIMGROUP_SIZE__SHIFT 0x0
#define IA_MULTI_VGT_PARAM__PARTIAL_VS_WAVE_ON_MASK 0x10000
#define IA_MULTI_VGT_PARAM__PARTIAL_VS_WAVE_ON__SHIFT 0x10
#define IA_MULTI_VGT_PARAM__SWITCH_ON_EOP_MASK 0x20000
#define IA_MULTI_VGT_PARAM__SWITCH_ON_EOP__SHIFT 0x11
#define IA_MULTI_VGT_PARAM__PARTIAL_ES_WAVE_ON_MASK 0x40000
#define IA_MULTI_VGT_PARAM__PARTIAL_ES_WAVE_ON__SHIFT 0x12
#define IA_MULTI_VGT_PARAM__SWITCH_ON_EOI_MASK 0x80000
#define IA_MULTI_VGT_PARAM__SWITCH_ON_EOI__SHIFT 0x13
#define IA_MULTI_VGT_PARAM__WD_SWITCH_ON_EOP_MASK 0x100000
#define IA_MULTI_VGT_PARAM__WD_SWITCH_ON_EOP__SHIFT 0x14
#define IA_MULTI_VGT_PARAM__MAX_PRIMGRP_IN_WAVE_MASK 0xf0000000
#define IA_MULTI_VGT_PARAM__MAX_PRIMGRP_IN_WAVE__SHIFT 0x1c
#define VGT_VS_MAX_WAVE_ID__MAX_WAVE_ID_MASK 0xfff
#define VGT_VS_MAX_WAVE_ID__MAX_WAVE_ID__SHIFT 0x0
#define VGT_ESGS_RING_SIZE__MEM_SIZE_MASK 0xffffffff
#define VGT_ESGS_RING_SIZE__MEM_SIZE__SHIFT 0x0
#define VGT_GSVS_RING_SIZE__MEM_SIZE_MASK 0xffffffff
#define VGT_GSVS_RING_SIZE__MEM_SIZE__SHIFT 0x0
#define VGT_GSVS_RING_OFFSET_1__OFFSET_MASK 0x7fff
#define VGT_GSVS_RING_OFFSET_1__OFFSET__SHIFT 0x0
#define VGT_GSVS_RING_OFFSET_2__OFFSET_MASK 0x7fff
#define VGT_GSVS_RING_OFFSET_2__OFFSET__SHIFT 0x0
#define VGT_GSVS_RING_OFFSET_3__OFFSET_MASK 0x7fff
#define VGT_GSVS_RING_OFFSET_3__OFFSET__SHIFT 0x0
#define VGT_ESGS_RING_ITEMSIZE__ITEMSIZE_MASK 0x7fff
#define VGT_ESGS_RING_ITEMSIZE__ITEMSIZE__SHIFT 0x0
#define VGT_GSVS_RING_ITEMSIZE__ITEMSIZE_MASK 0x7fff
#define VGT_GSVS_RING_ITEMSIZE__ITEMSIZE__SHIFT 0x0
#define VGT_GS_VERT_ITEMSIZE__ITEMSIZE_MASK 0x7fff
#define VGT_GS_VERT_ITEMSIZE__ITEMSIZE__SHIFT 0x0
#define VGT_GS_VERT_ITEMSIZE_1__ITEMSIZE_MASK 0x7fff
#define VGT_GS_VERT_ITEMSIZE_1__ITEMSIZE__SHIFT 0x0
#define VGT_GS_VERT_ITEMSIZE_2__ITEMSIZE_MASK 0x7fff
#define VGT_GS_VERT_ITEMSIZE_2__ITEMSIZE__SHIFT 0x0
#define VGT_GS_VERT_ITEMSIZE_3__ITEMSIZE_MASK 0x7fff
#define VGT_GS_VERT_ITEMSIZE_3__ITEMSIZE__SHIFT 0x0
#define WD_CNTL_STATUS__WD_BUSY_MASK 0x1
#define WD_CNTL_STATUS__WD_BUSY__SHIFT 0x0
#define WD_CNTL_STATUS__WD_SPL_DMA_BUSY_MASK 0x2
#define WD_CNTL_STATUS__WD_SPL_DMA_BUSY__SHIFT 0x1
#define WD_CNTL_STATUS__WD_SPL_DI_BUSY_MASK 0x4
#define WD_CNTL_STATUS__WD_SPL_DI_BUSY__SHIFT 0x2
#define WD_CNTL_STATUS__WD_ADC_BUSY_MASK 0x8
#define WD_CNTL_STATUS__WD_ADC_BUSY__SHIFT 0x3
#define WD_ENHANCE__MISC_MASK 0xffffffff
#define WD_ENHANCE__MISC__SHIFT 0x0
#define GFX_PIPE_CONTROL__HYSTERESIS_CNT_MASK 0x1fff
#define GFX_PIPE_CONTROL__HYSTERESIS_CNT__SHIFT 0x0
#define GFX_PIPE_CONTROL__RESERVED_MASK 0xe000
#define GFX_PIPE_CONTROL__RESERVED__SHIFT 0xd
#define GFX_PIPE_CONTROL__CONTEXT_SUSPEND_EN_MASK 0x10000
#define GFX_PIPE_CONTROL__CONTEXT_SUSPEND_EN__SHIFT 0x10
#define GFX_PIPE_PRIORITY__HP_PIPE_SELECT_MASK 0x1
#define GFX_PIPE_PRIORITY__HP_PIPE_SELECT__SHIFT 0x0
#define CGTT_VGT_CLK_CTRL__ON_DELAY_MASK 0xf
#define CGTT_VGT_CLK_CTRL__ON_DELAY__SHIFT 0x0
#define CGTT_VGT_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0
#define CGTT_VGT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
#define CGTT_VGT_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x1000000
#define CGTT_VGT_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18
#define CGTT_VGT_CLK_CTRL__PERF_ENABLE_MASK 0x2000000
#define CGTT_VGT_CLK_CTRL__PERF_ENABLE__SHIFT 0x19
#define CGTT_VGT_CLK_CTRL__DBG_ENABLE_MASK 0x4000000
#define CGTT_VGT_CLK_CTRL__DBG_ENABLE__SHIFT 0x1a
#define CGTT_VGT_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x8000000
#define CGTT_VGT_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b
#define CGTT_VGT_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000
#define CGTT_VGT_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c
#define CGTT_VGT_CLK_CTRL__GS_OVERRIDE_MASK 0x20000000
#define CGTT_VGT_CLK_CTRL__GS_OVERRIDE__SHIFT 0x1d
#define CGTT_VGT_CLK_CTRL__CORE_OVERRIDE_MASK 0x40000000
#define CGTT_VGT_CLK_CTRL__CORE_OVERRIDE__SHIFT 0x1e
#define CGTT_VGT_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000
#define CGTT_VGT_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f
#define CGTT_IA_CLK_CTRL__ON_DELAY_MASK 0xf
#define CGTT_IA_CLK_CTRL__ON_DELAY__SHIFT 0x0
#define CGTT_IA_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0
#define CGTT_IA_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
#define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x1000000
#define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18
#define CGTT_IA_CLK_CTRL__PERF_ENABLE_MASK 0x2000000
#define CGTT_IA_CLK_CTRL__PERF_ENABLE__SHIFT 0x19
#define CGTT_IA_CLK_CTRL__DBG_ENABLE_MASK 0x4000000
#define CGTT_IA_CLK_CTRL__DBG_ENABLE__SHIFT 0x1a
#define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x8000000
#define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b
#define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000
#define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c
#define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000
#define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d
#define CGTT_IA_CLK_CTRL__CORE_OVERRIDE_MASK 0x40000000
#define CGTT_IA_CLK_CTRL__CORE_OVERRIDE__SHIFT 0x1e
#define CGTT_IA_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000
#define CGTT_IA_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f
#define CGTT_WD_CLK_CTRL__ON_DELAY_MASK 0xf
#define CGTT_WD_CLK_CTRL__ON_DELAY__SHIFT 0x0
#define CGTT_WD_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0
#define CGTT_WD_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
#define CGTT_WD_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x1000000
#define CGTT_WD_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18
#define CGTT_WD_CLK_CTRL__PERF_ENABLE_MASK 0x2000000
#define CGTT_WD_CLK_CTRL__PERF_ENABLE__SHIFT 0x19
#define CGTT_WD_CLK_CTRL__DBG_ENABLE_MASK 0x4000000
#define CGTT_WD_CLK_CTRL__DBG_ENABLE__SHIFT 0x1a
#define CGTT_WD_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x8000000
#define CGTT_WD_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b
#define CGTT_WD_CLK_CTRL__ADC_OVERRIDE_MASK 0x10000000
#define CGTT_WD_CLK_CTRL__ADC_OVERRIDE__SHIFT 0x1c
#define CGTT_WD_CLK_CTRL__CORE_OVERRIDE_MASK 0x20000000
#define CGTT_WD_CLK_CTRL__CORE_OVERRIDE__SHIFT 0x1d
#define CGTT_WD_CLK_CTRL__RBIU_INPUT_OVERRIDE_MASK 0x40000000
#define CGTT_WD_CLK_CTRL__RBIU_INPUT_OVERRIDE__SHIFT 0x1e
#define CGTT_WD_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000
#define CGTT_WD_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f
#define VGT_DEBUG_CNTL__VGT_DEBUG_INDX_MASK 0x3f
#define VGT_DEBUG_CNTL__VGT_DEBUG_INDX__SHIFT 0x0
#define VGT_DEBUG_CNTL__VGT_DEBUG_SEL_BUS_B_MASK 0x40
#define VGT_DEBUG_CNTL__VGT_DEBUG_SEL_BUS_B__SHIFT 0x6
#define VGT_DEBUG_DATA__DATA_MASK 0xffffffff
#define VGT_DEBUG_DATA__DATA__SHIFT 0x0
#define IA_DEBUG_CNTL__IA_DEBUG_INDX_MASK 0x3f
#define IA_DEBUG_CNTL__IA_DEBUG_INDX__SHIFT 0x0
#define IA_DEBUG_CNTL__IA_DEBUG_SEL_BUS_B_MASK 0x40
#define IA_DEBUG_CNTL__IA_DEBUG_SEL_BUS_B__SHIFT 0x6
#define IA_DEBUG_DATA__DATA_MASK 0xffffffff
#define IA_DEBUG_DATA__DATA__SHIFT 0x0
#define VGT_CNTL_STATUS__VGT_BUSY_MASK 0x1
#define VGT_CNTL_STATUS__VGT_BUSY__SHIFT 0x0
#define VGT_CNTL_STATUS__VGT_OUT_INDX_BUSY_MASK 0x2
#define VGT_CNTL_STATUS__VGT_OUT_INDX_BUSY__SHIFT 0x1
#define VGT_CNTL_STATUS__VGT_OUT_BUSY_MASK 0x4
#define VGT_CNTL_STATUS__VGT_OUT_BUSY__SHIFT 0x2
#define VGT_CNTL_STATUS__VGT_PT_BUSY_MASK 0x8
#define VGT_CNTL_STATUS__VGT_PT_BUSY__SHIFT 0x3
#define VGT_CNTL_STATUS__VGT_TE_BUSY_MASK 0x10
#define VGT_CNTL_STATUS__VGT_TE_BUSY__SHIFT 0x4
#define VGT_CNTL_STATUS__VGT_VR_BUSY_MASK 0x20
#define VGT_CNTL_STATUS__VGT_VR_BUSY__SHIFT 0x5
#define VGT_CNTL_STATUS__VGT_PI_BUSY_MASK 0x40
#define VGT_CNTL_STATUS__VGT_PI_BUSY__SHIFT 0x6
#define VGT_CNTL_STATUS__VGT_GS_BUSY_MASK 0x80
#define VGT_CNTL_STATUS__VGT_GS_BUSY__SHIFT 0x7
#define VGT_CNTL_STATUS__VGT_HS_BUSY_MASK 0x100
#define VGT_CNTL_STATUS__VGT_HS_BUSY__SHIFT 0x8
#define VGT_CNTL_STATUS__VGT_TE11_BUSY_MASK 0x200
#define VGT_CNTL_STATUS__VGT_TE11_BUSY__SHIFT 0x9
#define WD_DEBUG_CNTL__WD_DEBUG_INDX_MASK 0x3f
#define WD_DEBUG_CNTL__WD_DEBUG_INDX__SHIFT 0x0
#define WD_DEBUG_CNTL__WD_DEBUG_SEL_BUS_B_MASK 0x40
#define WD_DEBUG_CNTL__WD_DEBUG_SEL_BUS_B__SHIFT 0x6
#define WD_DEBUG_DATA__DATA_MASK 0xffffffff
#define WD_DEBUG_DATA__DATA__SHIFT 0x0
#define WD_QOS__DRAW_STALL_MASK 0x1
#define WD_QOS__DRAW_STALL__SHIFT 0x0
#define CC_GC_PRIM_CONFIG__INACTIVE_IA_MASK 0x30000
#define CC_GC_PRIM_CONFIG__INACTIVE_IA__SHIFT 0x10
#define CC_GC_PRIM_CONFIG__INACTIVE_VGT_PA_MASK 0xf000000
#define CC_GC_PRIM_CONFIG__INACTIVE_VGT_PA__SHIFT 0x18
#define GC_USER_PRIM_CONFIG__INACTIVE_IA_MASK 0x30000
#define GC_USER_PRIM_CONFIG__INACTIVE_IA__SHIFT 0x10
#define GC_USER_PRIM_CONFIG__INACTIVE_VGT_PA_MASK 0xf000000
#define GC_USER_PRIM_CONFIG__INACTIVE_VGT_PA__SHIFT 0x18
#define WD_DEBUG_REG0__wd_busy_extended_MASK 0x1
#define WD_DEBUG_REG0__wd_busy_extended__SHIFT 0x0
#define WD_DEBUG_REG0__wd_nodma_busy_extended_MASK 0x2
#define WD_DEBUG_REG0__wd_nodma_busy_extended__SHIFT 0x1
#define WD_DEBUG_REG0__wd_busy_MASK 0x4
#define WD_DEBUG_REG0__wd_busy__SHIFT 0x2
#define WD_DEBUG_REG0__wd_nodma_busy_MASK 0x8
#define WD_DEBUG_REG0__wd_nodma_busy__SHIFT 0x3
#define WD_DEBUG_REG0__rbiu_busy_MASK 0x10
#define WD_DEBUG_REG0__rbiu_busy__SHIFT 0x4
#define WD_DEBUG_REG0__spl_dma_busy_MASK 0x20
#define WD_DEBUG_REG0__spl_dma_busy__SHIFT 0x5
#define WD_DEBUG_REG0__spl_di_busy_MASK 0x40
#define WD_DEBUG_REG0__spl_di_busy__SHIFT 0x6
#define WD_DEBUG_REG0__vgt0_active_q_MASK 0x80
#define WD_DEBUG_REG0__vgt0_active_q__SHIFT 0x7
#define WD_DEBUG_REG0__vgt1_active_q_MASK 0x100
#define WD_DEBUG_REG0__vgt1_active_q__SHIFT 0x8
#define WD_DEBUG_REG0__spl_dma_p1_busy_MASK 0x200
#define WD_DEBUG_REG0__spl_dma_p1_busy__SHIFT 0x9
#define WD_DEBUG_REG0__rbiu_dr_p1_fifo_busy_MASK 0x400
#define WD_DEBUG_REG0__rbiu_dr_p1_fifo_busy__SHIFT 0xa
#define WD_DEBUG_REG0__rbiu_di_p1_fifo_busy_MASK 0x800
#define WD_DEBUG_REG0__rbiu_di_p1_fifo_busy__SHIFT 0xb
#define WD_DEBUG_REG0__SPARE2_MASK 0x1000
#define WD_DEBUG_REG0__SPARE2__SHIFT 0xc
#define WD_DEBUG_REG0__rbiu_dr_fifo_busy_MASK 0x2000
#define WD_DEBUG_REG0__rbiu_dr_fifo_busy__SHIFT 0xd
#define WD_DEBUG_REG0__rbiu_spl_dr_valid_MASK 0x4000
#define WD_DEBUG_REG0__rbiu_spl_dr_valid__SHIFT 0xe
#define WD_DEBUG_REG0__spl_rbiu_dr_read_MASK 0x8000
#define WD_DEBUG_REG0__spl_rbiu_dr_read__SHIFT 0xf
#define WD_DEBUG_REG0__SPARE3_MASK 0x10000
#define WD_DEBUG_REG0__SPARE3__SHIFT 0x10
#define WD_DEBUG_REG0__rbiu_di_fifo_busy_MASK 0x20000
#define WD_DEBUG_REG0__rbiu_di_fifo_busy__SHIFT 0x11
#define WD_DEBUG_REG0__rbiu_spl_di_valid_MASK 0x40000
#define WD_DEBUG_REG0__rbiu_spl_di_valid__SHIFT 0x12
#define WD_DEBUG_REG0__spl_rbiu_di_read_MASK 0x80000
#define WD_DEBUG_REG0__spl_rbiu_di_read__SHIFT 0x13
#define WD_DEBUG_REG0__se0_synced_q_MASK 0x100000
#define WD_DEBUG_REG0__se0_synced_q__SHIFT 0x14
#define WD_DEBUG_REG0__se1_synced_q_MASK 0x200000
#define WD_DEBUG_REG0__se1_synced_q__SHIFT 0x15
#define WD_DEBUG_REG0__se2_synced_q_MASK 0x400000
#define WD_DEBUG_REG0__se2_synced_q__SHIFT 0x16
#define WD_DEBUG_REG0__se3_synced_q_MASK 0x800000
#define WD_DEBUG_REG0__se3_synced_q__SHIFT 0x17
#define WD_DEBUG_REG0__reg_clk_busy_MASK 0x1000000
#define WD_DEBUG_REG0__reg_clk_busy__SHIFT 0x18
#define WD_DEBUG_REG0__input_clk_busy_MASK 0x2000000
#define WD_DEBUG_REG0__input_clk_busy__SHIFT 0x19
#define WD_DEBUG_REG0__core_clk_busy_MASK 0x4000000
#define WD_DEBUG_REG0__core_clk_busy__SHIFT 0x1a
#define WD_DEBUG_REG0__vgt2_active_q_MASK 0x8000000
#define WD_DEBUG_REG0__vgt2_active_q__SHIFT 0x1b
#define WD_DEBUG_REG0__sclk_reg_vld_MASK 0x10000000
#define WD_DEBUG_REG0__sclk_reg_vld__SHIFT 0x1c
#define WD_DEBUG_REG0__sclk_input_vld_MASK 0x20000000
#define WD_DEBUG_REG0__sclk_input_vld__SHIFT 0x1d
#define WD_DEBUG_REG0__sclk_core_vld_MASK 0x40000000
#define WD_DEBUG_REG0__sclk_core_vld__SHIFT 0x1e
#define WD_DEBUG_REG0__vgt3_active_q_MASK 0x80000000
#define WD_DEBUG_REG0__vgt3_active_q__SHIFT 0x1f
#define WD_DEBUG_REG1__grbm_fifo_empty_MASK 0x1
#define WD_DEBUG_REG1__grbm_fifo_empty__SHIFT 0x0
#define WD_DEBUG_REG1__grbm_fifo_full_MASK 0x2
#define WD_DEBUG_REG1__grbm_fifo_full__SHIFT 0x1
#define WD_DEBUG_REG1__grbm_fifo_we_MASK 0x4
#define WD_DEBUG_REG1__grbm_fifo_we__SHIFT 0x2
#define WD_DEBUG_REG1__grbm_fifo_re_MASK 0x8
#define WD_DEBUG_REG1__grbm_fifo_re__SHIFT 0x3
#define WD_DEBUG_REG1__draw_initiator_valid_q_MASK 0x10
#define WD_DEBUG_REG1__draw_initiator_valid_q__SHIFT 0x4
#define WD_DEBUG_REG1__event_initiator_valid_q_MASK 0x20
#define WD_DEBUG_REG1__event_initiator_valid_q__SHIFT 0x5
#define WD_DEBUG_REG1__event_addr_valid_q_MASK 0x40
#define WD_DEBUG_REG1__event_addr_valid_q__SHIFT 0x6
#define WD_DEBUG_REG1__dma_request_valid_q_MASK 0x80
#define WD_DEBUG_REG1__dma_request_valid_q__SHIFT 0x7
#define WD_DEBUG_REG1__SPARE0_MASK 0x100
#define WD_DEBUG_REG1__SPARE0__SHIFT 0x8
#define WD_DEBUG_REG1__min_indx_valid_q_MASK 0x200
#define WD_DEBUG_REG1__min_indx_valid_q__SHIFT 0x9
#define WD_DEBUG_REG1__max_indx_valid_q_MASK 0x400
#define WD_DEBUG_REG1__max_indx_valid_q__SHIFT 0xa
#define WD_DEBUG_REG1__indx_offset_valid_q_MASK 0x800
#define WD_DEBUG_REG1__indx_offset_valid_q__SHIFT 0xb
#define WD_DEBUG_REG1__grbm_fifo_rdata_reg_id_MASK 0x1f000
#define WD_DEBUG_REG1__grbm_fifo_rdata_reg_id__SHIFT 0xc
#define WD_DEBUG_REG1__grbm_fifo_rdata_state_MASK 0xe0000
#define WD_DEBUG_REG1__grbm_fifo_rdata_state__SHIFT 0x11
#define WD_DEBUG_REG1__free_cnt_q_MASK 0x3f00000
#define WD_DEBUG_REG1__free_cnt_q__SHIFT 0x14
#define WD_DEBUG_REG1__rbiu_di_fifo_we_MASK 0x4000000
#define WD_DEBUG_REG1__rbiu_di_fifo_we__SHIFT 0x1a
#define WD_DEBUG_REG1__rbiu_dr_fifo_we_MASK 0x8000000
#define WD_DEBUG_REG1__rbiu_dr_fifo_we__SHIFT 0x1b
#define WD_DEBUG_REG1__rbiu_di_fifo_empty_MASK 0x10000000
#define WD_DEBUG_REG1__rbiu_di_fifo_empty__SHIFT 0x1c
#define WD_DEBUG_REG1__rbiu_di_fifo_full_MASK 0x20000000
#define WD_DEBUG_REG1__rbiu_di_fifo_full__SHIFT 0x1d
#define WD_DEBUG_REG1__rbiu_dr_fifo_empty_MASK 0x40000000
#define WD_DEBUG_REG1__rbiu_dr_fifo_empty__SHIFT 0x1e
#define WD_DEBUG_REG1__rbiu_dr_fifo_full_MASK 0x80000000
#define WD_DEBUG_REG1__rbiu_dr_fifo_full__SHIFT 0x1f
#define WD_DEBUG_REG2__p1_grbm_fifo_empty_MASK 0x1
#define WD_DEBUG_REG2__p1_grbm_fifo_empty__SHIFT 0x0
#define WD_DEBUG_REG2__p1_grbm_fifo_full_MASK 0x2
#define WD_DEBUG_REG2__p1_grbm_fifo_full__SHIFT 0x1
#define WD_DEBUG_REG2__p1_grbm_fifo_we_MASK 0x4
#define WD_DEBUG_REG2__p1_grbm_fifo_we__SHIFT 0x2
#define WD_DEBUG_REG2__p1_grbm_fifo_re_MASK 0x8
#define WD_DEBUG_REG2__p1_grbm_fifo_re__SHIFT 0x3
#define WD_DEBUG_REG2__p1_draw_initiator_valid_q_MASK 0x10
#define WD_DEBUG_REG2__p1_draw_initiator_valid_q__SHIFT 0x4
#define WD_DEBUG_REG2__p1_event_initiator_valid_q_MASK 0x20
#define WD_DEBUG_REG2__p1_event_initiator_valid_q__SHIFT 0x5
#define WD_DEBUG_REG2__p1_event_addr_valid_q_MASK 0x40
#define WD_DEBUG_REG2__p1_event_addr_valid_q__SHIFT 0x6
#define WD_DEBUG_REG2__p1_dma_request_valid_q_MASK 0x80
#define WD_DEBUG_REG2__p1_dma_request_valid_q__SHIFT 0x7
#define WD_DEBUG_REG2__SPARE0_MASK 0x100
#define WD_DEBUG_REG2__SPARE0__SHIFT 0x8
#define WD_DEBUG_REG2__p1_min_indx_valid_q_MASK 0x200
#define WD_DEBUG_REG2__p1_min_indx_valid_q__SHIFT 0x9
#define WD_DEBUG_REG2__p1_max_indx_valid_q_MASK 0x400
#define WD_DEBUG_REG2__p1_max_indx_valid_q__SHIFT 0xa
#define WD_DEBUG_REG2__p1_indx_offset_valid_q_MASK 0x800
#define WD_DEBUG_REG2__p1_indx_offset_valid_q__SHIFT 0xb
#define WD_DEBUG_REG2__p1_grbm_fifo_rdata_reg_id_MASK 0x1f000
#define WD_DEBUG_REG2__p1_grbm_fifo_rdata_reg_id__SHIFT 0xc
#define WD_DEBUG_REG2__p1_grbm_fifo_rdata_state_MASK 0xe0000
#define WD_DEBUG_REG2__p1_grbm_fifo_rdata_state__SHIFT 0x11
#define WD_DEBUG_REG2__p1_free_cnt_q_MASK 0x3f00000
#define WD_DEBUG_REG2__p1_free_cnt_q__SHIFT 0x14
#define WD_DEBUG_REG2__p1_rbiu_di_fifo_we_MASK 0x4000000
#define WD_DEBUG_REG2__p1_rbiu_di_fifo_we__SHIFT 0x1a
#define WD_DEBUG_REG2__p1_rbiu_dr_fifo_we_MASK 0x8000000
#define WD_DEBUG_REG2__p1_rbiu_dr_fifo_we__SHIFT 0x1b
#define WD_DEBUG_REG2__p1_rbiu_di_fifo_empty_MASK 0x10000000
#define WD_DEBUG_REG2__p1_rbiu_di_fifo_empty__SHIFT 0x1c
#define WD_DEBUG_REG2__p1_rbiu_di_fifo_full_MASK 0x20000000
#define WD_DEBUG_REG2__p1_rbiu_di_fifo_full__SHIFT 0x1d
#define WD_DEBUG_REG2__p1_rbiu_dr_fifo_empty_MASK 0x40000000
#define WD_DEBUG_REG2__p1_rbiu_dr_fifo_empty__SHIFT 0x1e
#define WD_DEBUG_REG2__p1_rbiu_dr_fifo_full_MASK 0x80000000
#define WD_DEBUG_REG2__p1_rbiu_dr_fifo_full__SHIFT 0x1f
#define WD_DEBUG_REG3__rbiu_spl_dr_valid_MASK 0x1
#define WD_DEBUG_REG3__rbiu_spl_dr_valid__SHIFT 0x0
#define WD_DEBUG_REG3__SPARE0_MASK 0x2
#define WD_DEBUG_REG3__SPARE0__SHIFT 0x1
#define WD_DEBUG_REG3__pipe0_dr_MASK 0x4
#define WD_DEBUG_REG3__pipe0_dr__SHIFT 0x2
#define WD_DEBUG_REG3__pipe0_rtr_MASK 0x8
#define WD_DEBUG_REG3__pipe0_rtr__SHIFT 0x3
#define WD_DEBUG_REG3__pipe1_dr_MASK 0x10
#define WD_DEBUG_REG3__pipe1_dr__SHIFT 0x4
#define WD_DEBUG_REG3__pipe1_rtr_MASK 0x20
#define WD_DEBUG_REG3__pipe1_rtr__SHIFT 0x5
#define WD_DEBUG_REG3__wd_subdma_fifo_empty_MASK 0x40
#define WD_DEBUG_REG3__wd_subdma_fifo_empty__SHIFT 0x6
#define WD_DEBUG_REG3__wd_subdma_fifo_full_MASK 0x80
#define WD_DEBUG_REG3__wd_subdma_fifo_full__SHIFT 0x7
#define WD_DEBUG_REG3__dma_buf_type_p0_q_MASK 0x300
#define WD_DEBUG_REG3__dma_buf_type_p0_q__SHIFT 0x8
#define WD_DEBUG_REG3__dma_zero_indices_p0_q_MASK 0x400
#define WD_DEBUG_REG3__dma_zero_indices_p0_q__SHIFT 0xa
#define WD_DEBUG_REG3__dma_req_path_p3_q_MASK 0x800
#define WD_DEBUG_REG3__dma_req_path_p3_q__SHIFT 0xb
#define WD_DEBUG_REG3__dma_not_eop_p1_q_MASK 0x1000
#define WD_DEBUG_REG3__dma_not_eop_p1_q__SHIFT 0xc
#define WD_DEBUG_REG3__out_of_range_p4_MASK 0x2000
#define WD_DEBUG_REG3__out_of_range_p4__SHIFT 0xd
#define WD_DEBUG_REG3__last_sub_dma_p3_q_MASK 0x4000
#define WD_DEBUG_REG3__last_sub_dma_p3_q__SHIFT 0xe
#define WD_DEBUG_REG3__last_rdreq_of_sub_dma_p4_MASK 0x8000
#define WD_DEBUG_REG3__last_rdreq_of_sub_dma_p4__SHIFT 0xf
#define WD_DEBUG_REG3__WD_IA_dma_send_d_MASK 0x10000
#define WD_DEBUG_REG3__WD_IA_dma_send_d__SHIFT 0x10
#define WD_DEBUG_REG3__WD_IA_dma_rtr_MASK 0x20000
#define WD_DEBUG_REG3__WD_IA_dma_rtr__SHIFT 0x11
#define WD_DEBUG_REG3__WD_IA1_dma_send_d_MASK 0x40000
#define WD_DEBUG_REG3__WD_IA1_dma_send_d__SHIFT 0x12
#define WD_DEBUG_REG3__WD_IA1_dma_rtr_MASK 0x80000
#define WD_DEBUG_REG3__WD_IA1_dma_rtr__SHIFT 0x13
#define WD_DEBUG_REG3__last_inst_of_dma_p2_MASK 0x100000
#define WD_DEBUG_REG3__last_inst_of_dma_p2__SHIFT 0x14
#define WD_DEBUG_REG3__last_sd_of_inst_p2_MASK 0x200000
#define WD_DEBUG_REG3__last_sd_of_inst_p2__SHIFT 0x15
#define WD_DEBUG_REG3__last_sd_of_dma_p2_MASK 0x400000
#define WD_DEBUG_REG3__last_sd_of_dma_p2__SHIFT 0x16
#define WD_DEBUG_REG3__SPARE1_MASK 0x800000
#define WD_DEBUG_REG3__SPARE1__SHIFT 0x17
#define WD_DEBUG_REG3__WD_IA_dma_busy_MASK 0x1000000
#define WD_DEBUG_REG3__WD_IA_dma_busy__SHIFT 0x18
#define WD_DEBUG_REG3__WD_IA1_dma_busy_MASK 0x2000000
#define WD_DEBUG_REG3__WD_IA1_dma_busy__SHIFT 0x19
#define WD_DEBUG_REG3__send_to_ia1_p3_q_MASK 0x4000000
#define WD_DEBUG_REG3__send_to_ia1_p3_q__SHIFT 0x1a
#define WD_DEBUG_REG3__dma_wd_switch_on_eop_p3_q_MASK 0x8000000
#define WD_DEBUG_REG3__dma_wd_switch_on_eop_p3_q__SHIFT 0x1b
#define WD_DEBUG_REG3__pipe3_dr_MASK 0x10000000
#define WD_DEBUG_REG3__pipe3_dr__SHIFT 0x1c
#define WD_DEBUG_REG3__pipe3_rtr_MASK 0x20000000
#define WD_DEBUG_REG3__pipe3_rtr__SHIFT 0x1d
#define WD_DEBUG_REG3__wd_dma2draw_fifo_empty_MASK 0x40000000
#define WD_DEBUG_REG3__wd_dma2draw_fifo_empty__SHIFT 0x1e
#define WD_DEBUG_REG3__wd_dma2draw_fifo_full_MASK 0x80000000
#define WD_DEBUG_REG3__wd_dma2draw_fifo_full__SHIFT 0x1f
#define WD_DEBUG_REG4__rbiu_spl_di_valid_MASK 0x1
#define WD_DEBUG_REG4__rbiu_spl_di_valid__SHIFT 0x0
#define WD_DEBUG_REG4__spl_rbiu_di_read_MASK 0x2
#define WD_DEBUG_REG4__spl_rbiu_di_read__SHIFT 0x1
#define WD_DEBUG_REG4__rbiu_spl_p1_di_valid_MASK 0x4
#define WD_DEBUG_REG4__rbiu_spl_p1_di_valid__SHIFT 0x2
#define WD_DEBUG_REG4__spl_rbiu_p1_di_read_MASK 0x8
#define WD_DEBUG_REG4__spl_rbiu_p1_di_read__SHIFT 0x3
#define WD_DEBUG_REG4__pipe0_dr_MASK 0x10
#define WD_DEBUG_REG4__pipe0_dr__SHIFT 0x4
#define WD_DEBUG_REG4__pipe0_rtr_MASK 0x20
#define WD_DEBUG_REG4__pipe0_rtr__SHIFT 0x5
#define WD_DEBUG_REG4__pipe1_dr_MASK 0x40
#define WD_DEBUG_REG4__pipe1_dr__SHIFT 0x6
#define WD_DEBUG_REG4__pipe1_rtr_MASK 0x80
#define WD_DEBUG_REG4__pipe1_rtr__SHIFT 0x7
#define WD_DEBUG_REG4__pipe2_dr_MASK 0x100
#define WD_DEBUG_REG4__pipe2_dr__SHIFT 0x8
#define WD_DEBUG_REG4__pipe2_rtr_MASK 0x200
#define WD_DEBUG_REG4__pipe2_rtr__SHIFT 0x9
#define WD_DEBUG_REG4__pipe3_ld_MASK 0x400
#define WD_DEBUG_REG4__pipe3_ld__SHIFT 0xa
#define WD_DEBUG_REG4__pipe3_rtr_MASK 0x800
#define WD_DEBUG_REG4__pipe3_rtr__SHIFT 0xb
#define WD_DEBUG_REG4__WD_IA_draw_send_d_MASK 0x1000
#define WD_DEBUG_REG4__WD_IA_draw_send_d__SHIFT 0xc
#define WD_DEBUG_REG4__WD_IA_draw_rtr_MASK 0x2000
#define WD_DEBUG_REG4__WD_IA_draw_rtr__SHIFT 0xd
#define WD_DEBUG_REG4__di_type_p0_MASK 0xc000
#define WD_DEBUG_REG4__di_type_p0__SHIFT 0xe
#define WD_DEBUG_REG4__di_state_sel_p1_q_MASK 0x70000
#define WD_DEBUG_REG4__di_state_sel_p1_q__SHIFT 0x10
#define WD_DEBUG_REG4__di_wd_switch_on_eop_p1_q_MASK 0x80000
#define WD_DEBUG_REG4__di_wd_switch_on_eop_p1_q__SHIFT 0x13
#define WD_DEBUG_REG4__rbiu_spl_pipe0_lockout_MASK 0x100000
#define WD_DEBUG_REG4__rbiu_spl_pipe0_lockout__SHIFT 0x14
#define WD_DEBUG_REG4__last_inst_of_di_p2_MASK 0x200000
#define WD_DEBUG_REG4__last_inst_of_di_p2__SHIFT 0x15
#define WD_DEBUG_REG4__last_sd_of_inst_p2_MASK 0x400000
#define WD_DEBUG_REG4__last_sd_of_inst_p2__SHIFT 0x16
#define WD_DEBUG_REG4__last_sd_of_di_p2_MASK 0x800000
#define WD_DEBUG_REG4__last_sd_of_di_p2__SHIFT 0x17
#define WD_DEBUG_REG4__not_eop_wait_p1_q_MASK 0x1000000
#define WD_DEBUG_REG4__not_eop_wait_p1_q__SHIFT 0x18
#define WD_DEBUG_REG4__not_eop_wait_q_MASK 0x2000000
#define WD_DEBUG_REG4__not_eop_wait_q__SHIFT 0x19
#define WD_DEBUG_REG4__ext_event_wait_p1_q_MASK 0x4000000
#define WD_DEBUG_REG4__ext_event_wait_p1_q__SHIFT 0x1a
#define WD_DEBUG_REG4__ext_event_wait_q_MASK 0x8000000
#define WD_DEBUG_REG4__ext_event_wait_q__SHIFT 0x1b
#define WD_DEBUG_REG4__WD_IA1_draw_send_d_MASK 0x10000000
#define WD_DEBUG_REG4__WD_IA1_draw_send_d__SHIFT 0x1c
#define WD_DEBUG_REG4__WD_IA1_draw_rtr_MASK 0x20000000
#define WD_DEBUG_REG4__WD_IA1_draw_rtr__SHIFT 0x1d
#define WD_DEBUG_REG4__send_to_ia1_q_MASK 0x40000000
#define WD_DEBUG_REG4__send_to_ia1_q__SHIFT 0x1e
#define WD_DEBUG_REG4__dual_ia_mode_MASK 0x80000000
#define WD_DEBUG_REG4__dual_ia_mode__SHIFT 0x1f
#define WD_DEBUG_REG5__p1_rbiu_spl_dr_valid_MASK 0x1
#define WD_DEBUG_REG5__p1_rbiu_spl_dr_valid__SHIFT 0x0
#define WD_DEBUG_REG5__SPARE0_MASK 0x2
#define WD_DEBUG_REG5__SPARE0__SHIFT 0x1
#define WD_DEBUG_REG5__p1_pipe0_dr_MASK 0x4
#define WD_DEBUG_REG5__p1_pipe0_dr__SHIFT 0x2
#define WD_DEBUG_REG5__p1_pipe0_rtr_MASK 0x8
#define WD_DEBUG_REG5__p1_pipe0_rtr__SHIFT 0x3
#define WD_DEBUG_REG5__p1_pipe1_dr_MASK 0x10
#define WD_DEBUG_REG5__p1_pipe1_dr__SHIFT 0x4
#define WD_DEBUG_REG5__p1_pipe1_rtr_MASK 0x20
#define WD_DEBUG_REG5__p1_pipe1_rtr__SHIFT 0x5
#define WD_DEBUG_REG5__p1_wd_subdma_fifo_empty_MASK 0x40
#define WD_DEBUG_REG5__p1_wd_subdma_fifo_empty__SHIFT 0x6
#define WD_DEBUG_REG5__p1_wd_subdma_fifo_full_MASK 0x80
#define WD_DEBUG_REG5__p1_wd_subdma_fifo_full__SHIFT 0x7
#define WD_DEBUG_REG5__p1_dma_buf_type_p0_q_MASK 0x300
#define WD_DEBUG_REG5__p1_dma_buf_type_p0_q__SHIFT 0x8
#define WD_DEBUG_REG5__p1_dma_zero_indices_p0_q_MASK 0x400
#define WD_DEBUG_REG5__p1_dma_zero_indices_p0_q__SHIFT 0xa
#define WD_DEBUG_REG5__p1_dma_req_path_p3_q_MASK 0x800
#define WD_DEBUG_REG5__p1_dma_req_path_p3_q__SHIFT 0xb
#define WD_DEBUG_REG5__p1_dma_not_eop_p1_q_MASK 0x1000
#define WD_DEBUG_REG5__p1_dma_not_eop_p1_q__SHIFT 0xc
#define WD_DEBUG_REG5__p1_out_of_range_p4_MASK 0x2000
#define WD_DEBUG_REG5__p1_out_of_range_p4__SHIFT 0xd
#define WD_DEBUG_REG5__p1_last_sub_dma_p3_q_MASK 0x4000
#define WD_DEBUG_REG5__p1_last_sub_dma_p3_q__SHIFT 0xe
#define WD_DEBUG_REG5__p1_last_rdreq_of_sub_dma_p4_MASK 0x8000
#define WD_DEBUG_REG5__p1_last_rdreq_of_sub_dma_p4__SHIFT 0xf
#define WD_DEBUG_REG5__p1_WD_IA_dma_send_d_MASK 0x10000
#define WD_DEBUG_REG5__p1_WD_IA_dma_send_d__SHIFT 0x10
#define WD_DEBUG_REG5__p1_WD_IA_dma_rtr_MASK 0x20000
#define WD_DEBUG_REG5__p1_WD_IA_dma_rtr__SHIFT 0x11
#define WD_DEBUG_REG5__p1_WD_IA1_dma_send_d_MASK 0x40000
#define WD_DEBUG_REG5__p1_WD_IA1_dma_send_d__SHIFT 0x12
#define WD_DEBUG_REG5__p1_WD_IA1_dma_rtr_MASK 0x80000
#define WD_DEBUG_REG5__p1_WD_IA1_dma_rtr__SHIFT 0x13
#define WD_DEBUG_REG5__p1_last_inst_of_dma_p2_MASK 0x100000
#define WD_DEBUG_REG5__p1_last_inst_of_dma_p2__SHIFT 0x14
#define WD_DEBUG_REG5__p1_last_sd_of_inst_p2_MASK 0x200000
#define WD_DEBUG_REG5__p1_last_sd_of_inst_p2__SHIFT 0x15
#define WD_DEBUG_REG5__p1_last_sd_of_dma_p2_MASK 0x400000
#define WD_DEBUG_REG5__p1_last_sd_of_dma_p2__SHIFT 0x16
#define WD_DEBUG_REG5__SPARE1_MASK 0x800000
#define WD_DEBUG_REG5__SPARE1__SHIFT 0x17
#define WD_DEBUG_REG5__p1_WD_IA_dma_busy_MASK 0x1000000
#define WD_DEBUG_REG5__p1_WD_IA_dma_busy__SHIFT 0x18
#define WD_DEBUG_REG5__p1_WD_IA1_dma_busy_MASK 0x2000000
#define WD_DEBUG_REG5__p1_WD_IA1_dma_busy__SHIFT 0x19
#define WD_DEBUG_REG5__p1_send_to_ia1_p3_q_MASK 0x4000000
#define WD_DEBUG_REG5__p1_send_to_ia1_p3_q__SHIFT 0x1a
#define WD_DEBUG_REG5__p1_dma_wd_switch_on_eop_p3_q_MASK 0x8000000
#define WD_DEBUG_REG5__p1_dma_wd_switch_on_eop_p3_q__SHIFT 0x1b
#define WD_DEBUG_REG5__p1_pipe3_dr_MASK 0x10000000
#define WD_DEBUG_REG5__p1_pipe3_dr__SHIFT 0x1c
#define WD_DEBUG_REG5__p1_pipe3_rtr_MASK 0x20000000
#define WD_DEBUG_REG5__p1_pipe3_rtr__SHIFT 0x1d
#define WD_DEBUG_REG5__p1_wd_dma2draw_fifo_empty_MASK 0x40000000
#define WD_DEBUG_REG5__p1_wd_dma2draw_fifo_empty__SHIFT 0x1e
#define WD_DEBUG_REG5__p1_wd_dma2draw_fifo_full_MASK 0x80000000
#define WD_DEBUG_REG5__p1_wd_dma2draw_fifo_full__SHIFT 0x1f
#define WD_DEBUG_REG6__WD_IA_draw_eop_MASK 0xffffffff
#define WD_DEBUG_REG6__WD_IA_draw_eop__SHIFT 0x0
#define WD_DEBUG_REG7__SE0VGT_WD_thdgrp_send_in_MASK 0x1
#define WD_DEBUG_REG7__SE0VGT_WD_thdgrp_send_in__SHIFT 0x0
#define WD_DEBUG_REG7__wd_arb_se0_input_fifo_re_MASK 0x2
#define WD_DEBUG_REG7__wd_arb_se0_input_fifo_re__SHIFT 0x1
#define WD_DEBUG_REG7__wd_arb_se0_input_fifo_empty_MASK 0x4
#define WD_DEBUG_REG7__wd_arb_se0_input_fifo_empty__SHIFT 0x2
#define WD_DEBUG_REG7__wd_arb_se0_input_fifo_full_MASK 0x8
#define WD_DEBUG_REG7__wd_arb_se0_input_fifo_full__SHIFT 0x3
#define WD_DEBUG_REG7__SPARE0_MASK 0xf0
#define WD_DEBUG_REG7__SPARE0__SHIFT 0x4
#define WD_DEBUG_REG7__SPARE1_MASK 0xf00
#define WD_DEBUG_REG7__SPARE1__SHIFT 0x8
#define WD_DEBUG_REG7__SPARE2_MASK 0xf000
#define WD_DEBUG_REG7__SPARE2__SHIFT 0xc
#define WD_DEBUG_REG7__SPARE3_MASK 0xf0000
#define WD_DEBUG_REG7__SPARE3__SHIFT 0x10
#define WD_DEBUG_REG7__se0_thdgrp_is_event_MASK 0x100000
#define WD_DEBUG_REG7__se0_thdgrp_is_event__SHIFT 0x14
#define WD_DEBUG_REG7__se0_thdgrp_eop_MASK 0x200000
#define WD_DEBUG_REG7__se0_thdgrp_eop__SHIFT 0x15
#define WD_DEBUG_REG7__SPARE4_MASK 0xfc00000
#define WD_DEBUG_REG7__SPARE4__SHIFT 0x16
#define WD_DEBUG_REG7__tfreq_arb_tgroup_rtr_MASK 0x10000000
#define WD_DEBUG_REG7__tfreq_arb_tgroup_rtr__SHIFT 0x1c
#define WD_DEBUG_REG7__arb_tfreq_tgroup_rts_MASK 0x20000000
#define WD_DEBUG_REG7__arb_tfreq_tgroup_rts__SHIFT 0x1d
#define WD_DEBUG_REG7__arb_tfreq_tgroup_event_MASK 0x40000000
#define WD_DEBUG_REG7__arb_tfreq_tgroup_event__SHIFT 0x1e
#define WD_DEBUG_REG7__te11_arb_busy_MASK 0x80000000
#define WD_DEBUG_REG7__te11_arb_busy__SHIFT 0x1f
#define WD_DEBUG_REG8__pipe0_dr_MASK 0x1
#define WD_DEBUG_REG8__pipe0_dr__SHIFT 0x0
#define WD_DEBUG_REG8__pipe1_dr_MASK 0x2
#define WD_DEBUG_REG8__pipe1_dr__SHIFT 0x1
#define WD_DEBUG_REG8__pipe0_rtr_MASK 0x4
#define WD_DEBUG_REG8__pipe0_rtr__SHIFT 0x2
#define WD_DEBUG_REG8__pipe1_rtr_MASK 0x8
#define WD_DEBUG_REG8__pipe1_rtr__SHIFT 0x3
#define WD_DEBUG_REG8__tfreq_tg_fifo_empty_MASK 0x10
#define WD_DEBUG_REG8__tfreq_tg_fifo_empty__SHIFT 0x4
#define WD_DEBUG_REG8__tfreq_tg_fifo_full_MASK 0x20
#define WD_DEBUG_REG8__tfreq_tg_fifo_full__SHIFT 0x5
#define WD_DEBUG_REG8__tf_data_fifo_busy_q_MASK 0x40
#define WD_DEBUG_REG8__tf_data_fifo_busy_q__SHIFT 0x6
#define WD_DEBUG_REG8__tf_data_fifo_rtr_q_MASK 0x80
#define WD_DEBUG_REG8__tf_data_fifo_rtr_q__SHIFT 0x7
#define WD_DEBUG_REG8__tf_skid_fifo_empty_MASK 0x100
#define WD_DEBUG_REG8__tf_skid_fifo_empty__SHIFT 0x8
#define WD_DEBUG_REG8__tf_skid_fifo_full_MASK 0x200
#define WD_DEBUG_REG8__tf_skid_fifo_full__SHIFT 0x9
#define WD_DEBUG_REG8__wd_tc_rdreq_rtr_q_MASK 0x400
#define WD_DEBUG_REG8__wd_tc_rdreq_rtr_q__SHIFT 0xa
#define WD_DEBUG_REG8__last_req_of_tg_p2_MASK 0x800
#define WD_DEBUG_REG8__last_req_of_tg_p2__SHIFT 0xb
#define WD_DEBUG_REG8__se0spi_wd_hs_done_cnt_q_MASK 0x3f000
#define WD_DEBUG_REG8__se0spi_wd_hs_done_cnt_q__SHIFT 0xc
#define WD_DEBUG_REG8__event_flag_p1_q_MASK 0x40000
#define WD_DEBUG_REG8__event_flag_p1_q__SHIFT 0x12
#define WD_DEBUG_REG8__null_flag_p1_q_MASK 0x80000
#define WD_DEBUG_REG8__null_flag_p1_q__SHIFT 0x13
#define WD_DEBUG_REG8__tf_data_fifo_cnt_q_MASK 0x7f00000
#define WD_DEBUG_REG8__tf_data_fifo_cnt_q__SHIFT 0x14
#define WD_DEBUG_REG8__second_tf_ret_data_q_MASK 0x8000000
#define WD_DEBUG_REG8__second_tf_ret_data_q__SHIFT 0x1b
#define WD_DEBUG_REG8__first_req_of_tg_p1_q_MASK 0x10000000
#define WD_DEBUG_REG8__first_req_of_tg_p1_q__SHIFT 0x1c
#define WD_DEBUG_REG8__WD_TC_rdreq_send_out_MASK 0x20000000
#define WD_DEBUG_REG8__WD_TC_rdreq_send_out__SHIFT 0x1d
#define WD_DEBUG_REG8__WD_TC_rdnfo_stall_out_MASK 0x40000000
#define WD_DEBUG_REG8__WD_TC_rdnfo_stall_out__SHIFT 0x1e
#define WD_DEBUG_REG8__TC_WD_rdret_valid_in_MASK 0x80000000
#define WD_DEBUG_REG8__TC_WD_rdret_valid_in__SHIFT 0x1f
#define WD_DEBUG_REG9__pipe0_dr_MASK 0x1
#define WD_DEBUG_REG9__pipe0_dr__SHIFT 0x0
#define WD_DEBUG_REG9__pipec_tf_dr_MASK 0x2
#define WD_DEBUG_REG9__pipec_tf_dr__SHIFT 0x1
#define WD_DEBUG_REG9__pipe2_dr_MASK 0x4
#define WD_DEBUG_REG9__pipe2_dr__SHIFT 0x2
#define WD_DEBUG_REG9__event_or_null_flags_p0_q_MASK 0x8
#define WD_DEBUG_REG9__event_or_null_flags_p0_q__SHIFT 0x3
#define WD_DEBUG_REG9__pipe0_rtr_MASK 0x10
#define WD_DEBUG_REG9__pipe0_rtr__SHIFT 0x4
#define WD_DEBUG_REG9__pipe1_rtr_MASK 0x20
#define WD_DEBUG_REG9__pipe1_rtr__SHIFT 0x5
#define WD_DEBUG_REG9__pipec_tf_rtr_MASK 0x40
#define WD_DEBUG_REG9__pipec_tf_rtr__SHIFT 0x6
#define WD_DEBUG_REG9__pipe2_rtr_MASK 0x80
#define WD_DEBUG_REG9__pipe2_rtr__SHIFT 0x7
#define WD_DEBUG_REG9__ttp_patch_fifo_full_MASK 0x100
#define WD_DEBUG_REG9__ttp_patch_fifo_full__SHIFT 0x8
#define WD_DEBUG_REG9__ttp_patch_fifo_empty_MASK 0x200
#define WD_DEBUG_REG9__ttp_patch_fifo_empty__SHIFT 0x9
#define WD_DEBUG_REG9__ttp_tf_fifo_empty_MASK 0x400
#define WD_DEBUG_REG9__ttp_tf_fifo_empty__SHIFT 0xa
#define WD_DEBUG_REG9__SPARE0_MASK 0xf800
#define WD_DEBUG_REG9__SPARE0__SHIFT 0xb
#define WD_DEBUG_REG9__tf_fetch_state_q_MASK 0x70000
#define WD_DEBUG_REG9__tf_fetch_state_q__SHIFT 0x10
#define WD_DEBUG_REG9__last_patch_of_tg_MASK 0x80000
#define WD_DEBUG_REG9__last_patch_of_tg__SHIFT 0x13
#define WD_DEBUG_REG9__tf_pointer_p0_q_MASK 0xf00000
#define WD_DEBUG_REG9__tf_pointer_p0_q__SHIFT 0x14
#define WD_DEBUG_REG9__dynamic_hs_p0_q_MASK 0x1000000
#define WD_DEBUG_REG9__dynamic_hs_p0_q__SHIFT 0x18
#define WD_DEBUG_REG9__first_fetch_of_tg_p0_q_MASK 0x2000000
#define WD_DEBUG_REG9__first_fetch_of_tg_p0_q__SHIFT 0x19
#define WD_DEBUG_REG9__mem_is_even_MASK 0x4000000
#define WD_DEBUG_REG9__mem_is_even__SHIFT 0x1a
#define WD_DEBUG_REG9__SPARE1_MASK 0x8000000
#define WD_DEBUG_REG9__SPARE1__SHIFT 0x1b
#define WD_DEBUG_REG9__SPARE2_MASK 0x30000000
#define WD_DEBUG_REG9__SPARE2__SHIFT 0x1c
#define WD_DEBUG_REG9__pipe4_dr_MASK 0x40000000
#define WD_DEBUG_REG9__pipe4_dr__SHIFT 0x1e
#define WD_DEBUG_REG9__pipe4_rtr_MASK 0x80000000
#define WD_DEBUG_REG9__pipe4_rtr__SHIFT 0x1f
#define WD_DEBUG_REG10__ttp_pd_patch_rts_MASK 0x1
#define WD_DEBUG_REG10__ttp_pd_patch_rts__SHIFT 0x0
#define WD_DEBUG_REG10__ttp_pd_is_event_MASK 0x2
#define WD_DEBUG_REG10__ttp_pd_is_event__SHIFT 0x1
#define WD_DEBUG_REG10__ttp_pd_eopg_MASK 0x4
#define WD_DEBUG_REG10__ttp_pd_eopg__SHIFT 0x2
#define WD_DEBUG_REG10__ttp_pd_eop_MASK 0x8
#define WD_DEBUG_REG10__ttp_pd_eop__SHIFT 0x3
#define WD_DEBUG_REG10__pipe0_dr_MASK 0x10
#define WD_DEBUG_REG10__pipe0_dr__SHIFT 0x4
#define WD_DEBUG_REG10__pipe1_dr_MASK 0x20
#define WD_DEBUG_REG10__pipe1_dr__SHIFT 0x5
#define WD_DEBUG_REG10__pipe0_rtr_MASK 0x40
#define WD_DEBUG_REG10__pipe0_rtr__SHIFT 0x6
#define WD_DEBUG_REG10__pipe1_rtr_MASK 0x80
#define WD_DEBUG_REG10__pipe1_rtr__SHIFT 0x7
#define WD_DEBUG_REG10__donut_en_p1_q_MASK 0x100
#define WD_DEBUG_REG10__donut_en_p1_q__SHIFT 0x8
#define WD_DEBUG_REG10__donut_se_switch_p2_MASK 0x200
#define WD_DEBUG_REG10__donut_se_switch_p2__SHIFT 0x9
#define WD_DEBUG_REG10__patch_se_switch_p2_MASK 0x400
#define WD_DEBUG_REG10__patch_se_switch_p2__SHIFT 0xa
#define WD_DEBUG_REG10__last_donut_switch_p2_MASK 0x800
#define WD_DEBUG_REG10__last_donut_switch_p2__SHIFT 0xb
#define WD_DEBUG_REG10__last_donut_of_patch_p2_MASK 0x1000
#define WD_DEBUG_REG10__last_donut_of_patch_p2__SHIFT 0xc
#define WD_DEBUG_REG10__is_event_p1_q_MASK 0x2000
#define WD_DEBUG_REG10__is_event_p1_q__SHIFT 0xd
#define WD_DEBUG_REG10__eopg_p1_q_MASK 0x4000
#define WD_DEBUG_REG10__eopg_p1_q__SHIFT 0xe
#define WD_DEBUG_REG10__eop_p1_q_MASK 0x8000
#define WD_DEBUG_REG10__eop_p1_q__SHIFT 0xf
#define WD_DEBUG_REG10__patch_accum_q_MASK 0xff0000
#define WD_DEBUG_REG10__patch_accum_q__SHIFT 0x10
#define WD_DEBUG_REG10__wd_te11_out_se0_fifo_full_MASK 0x1000000
#define WD_DEBUG_REG10__wd_te11_out_se0_fifo_full__SHIFT 0x18
#define WD_DEBUG_REG10__wd_te11_out_se0_fifo_empty_MASK 0x2000000
#define WD_DEBUG_REG10__wd_te11_out_se0_fifo_empty__SHIFT 0x19
#define WD_DEBUG_REG10__wd_te11_out_se1_fifo_full_MASK 0x4000000
#define WD_DEBUG_REG10__wd_te11_out_se1_fifo_full__SHIFT 0x1a
#define WD_DEBUG_REG10__wd_te11_out_se1_fifo_empty_MASK 0x8000000
#define WD_DEBUG_REG10__wd_te11_out_se1_fifo_empty__SHIFT 0x1b
#define WD_DEBUG_REG10__wd_te11_out_se2_fifo_full_MASK 0x10000000
#define WD_DEBUG_REG10__wd_te11_out_se2_fifo_full__SHIFT 0x1c
#define WD_DEBUG_REG10__wd_te11_out_se2_fifo_empty_MASK 0x20000000
#define WD_DEBUG_REG10__wd_te11_out_se2_fifo_empty__SHIFT 0x1d
#define WD_DEBUG_REG10__wd_te11_out_se3_fifo_full_MASK 0x40000000
#define WD_DEBUG_REG10__wd_te11_out_se3_fifo_full__SHIFT 0x1e
#define WD_DEBUG_REG10__wd_te11_out_se3_fifo_empty_MASK 0x80000000
#define WD_DEBUG_REG10__wd_te11_out_se3_fifo_empty__SHIFT 0x1f
#define IA_DEBUG_REG0__ia_busy_extended_MASK 0x1
#define IA_DEBUG_REG0__ia_busy_extended__SHIFT 0x0
#define IA_DEBUG_REG0__ia_nodma_busy_extended_MASK 0x2
#define IA_DEBUG_REG0__ia_nodma_busy_extended__SHIFT 0x1
#define IA_DEBUG_REG0__ia_busy_MASK 0x4
#define IA_DEBUG_REG0__ia_busy__SHIFT 0x2
#define IA_DEBUG_REG0__ia_nodma_busy_MASK 0x8
#define IA_DEBUG_REG0__ia_nodma_busy__SHIFT 0x3
#define IA_DEBUG_REG0__SPARE0_MASK 0x10
#define IA_DEBUG_REG0__SPARE0__SHIFT 0x4
#define IA_DEBUG_REG0__dma_req_busy_MASK 0x20
#define IA_DEBUG_REG0__dma_req_busy__SHIFT 0x5
#define IA_DEBUG_REG0__dma_busy_MASK 0x40
#define IA_DEBUG_REG0__dma_busy__SHIFT 0x6
#define IA_DEBUG_REG0__mc_xl8r_busy_MASK 0x80
#define IA_DEBUG_REG0__mc_xl8r_busy__SHIFT 0x7
#define IA_DEBUG_REG0__grp_busy_MASK 0x100
#define IA_DEBUG_REG0__grp_busy__SHIFT 0x8
#define IA_DEBUG_REG0__SPARE1_MASK 0x200
#define IA_DEBUG_REG0__SPARE1__SHIFT 0x9
#define IA_DEBUG_REG0__dma_grp_valid_MASK 0x400
#define IA_DEBUG_REG0__dma_grp_valid__SHIFT 0xa
#define IA_DEBUG_REG0__grp_dma_read_MASK 0x800
#define IA_DEBUG_REG0__grp_dma_read__SHIFT 0xb
#define IA_DEBUG_REG0__dma_grp_hp_valid_MASK 0x1000
#define IA_DEBUG_REG0__dma_grp_hp_valid__SHIFT 0xc
#define IA_DEBUG_REG0__grp_dma_hp_read_MASK 0x2000
#define IA_DEBUG_REG0__grp_dma_hp_read__SHIFT 0xd
#define IA_DEBUG_REG0__SPARE2_MASK 0xffc000
#define IA_DEBUG_REG0__SPARE2__SHIFT 0xe
#define IA_DEBUG_REG0__reg_clk_busy_MASK 0x1000000
#define IA_DEBUG_REG0__reg_clk_busy__SHIFT 0x18
#define IA_DEBUG_REG0__core_clk_busy_MASK 0x2000000
#define IA_DEBUG_REG0__core_clk_busy__SHIFT 0x19
#define IA_DEBUG_REG0__SPARE3_MASK 0x4000000
#define IA_DEBUG_REG0__SPARE3__SHIFT 0x1a
#define IA_DEBUG_REG0__SPARE4_MASK 0x8000000
#define IA_DEBUG_REG0__SPARE4__SHIFT 0x1b
#define IA_DEBUG_REG0__sclk_reg_vld_MASK 0x10000000
#define IA_DEBUG_REG0__sclk_reg_vld__SHIFT 0x1c
#define IA_DEBUG_REG0__sclk_core_vld_MASK 0x20000000
#define IA_DEBUG_REG0__sclk_core_vld__SHIFT 0x1d
#define IA_DEBUG_REG0__SPARE5_MASK 0x40000000
#define IA_DEBUG_REG0__SPARE5__SHIFT 0x1e
#define IA_DEBUG_REG0__SPARE6_MASK 0x80000000
#define IA_DEBUG_REG0__SPARE6__SHIFT 0x1f
#define IA_DEBUG_REG1__dma_input_fifo_empty_MASK 0x1
#define IA_DEBUG_REG1__dma_input_fifo_empty__SHIFT 0x0
#define IA_DEBUG_REG1__dma_input_fifo_full_MASK 0x2
#define IA_DEBUG_REG1__dma_input_fifo_full__SHIFT 0x1
#define IA_DEBUG_REG1__start_new_packet_MASK 0x4
#define IA_DEBUG_REG1__start_new_packet__SHIFT 0x2
#define IA_DEBUG_REG1__dma_rdreq_dr_q_MASK 0x8
#define IA_DEBUG_REG1__dma_rdreq_dr_q__SHIFT 0x3
#define IA_DEBUG_REG1__dma_zero_indices_q_MASK 0x10
#define IA_DEBUG_REG1__dma_zero_indices_q__SHIFT 0x4
#define IA_DEBUG_REG1__dma_buf_type_q_MASK 0x60
#define IA_DEBUG_REG1__dma_buf_type_q__SHIFT 0x5
#define IA_DEBUG_REG1__dma_req_path_q_MASK 0x80
#define IA_DEBUG_REG1__dma_req_path_q__SHIFT 0x7
#define IA_DEBUG_REG1__discard_1st_chunk_MASK 0x100
#define IA_DEBUG_REG1__discard_1st_chunk__SHIFT 0x8
#define IA_DEBUG_REG1__discard_2nd_chunk_MASK 0x200
#define IA_DEBUG_REG1__discard_2nd_chunk__SHIFT 0x9
#define IA_DEBUG_REG1__second_tc_ret_data_q_MASK 0x400
#define IA_DEBUG_REG1__second_tc_ret_data_q__SHIFT 0xa
#define IA_DEBUG_REG1__dma_tc_ret_sel_q_MASK 0x800
#define IA_DEBUG_REG1__dma_tc_ret_sel_q__SHIFT 0xb
#define IA_DEBUG_REG1__last_rdreq_in_dma_op_MASK 0x1000
#define IA_DEBUG_REG1__last_rdreq_in_dma_op__SHIFT 0xc
#define IA_DEBUG_REG1__dma_mask_fifo_empty_MASK 0x2000
#define IA_DEBUG_REG1__dma_mask_fifo_empty__SHIFT 0xd
#define IA_DEBUG_REG1__dma_data_fifo_empty_q_MASK 0x4000
#define IA_DEBUG_REG1__dma_data_fifo_empty_q__SHIFT 0xe
#define IA_DEBUG_REG1__dma_data_fifo_full_MASK 0x8000
#define IA_DEBUG_REG1__dma_data_fifo_full__SHIFT 0xf
#define IA_DEBUG_REG1__dma_req_fifo_empty_MASK 0x10000
#define IA_DEBUG_REG1__dma_req_fifo_empty__SHIFT 0x10
#define IA_DEBUG_REG1__dma_req_fifo_full_MASK 0x20000
#define IA_DEBUG_REG1__dma_req_fifo_full__SHIFT 0x11
#define IA_DEBUG_REG1__stage2_dr_MASK 0x40000
#define IA_DEBUG_REG1__stage2_dr__SHIFT 0x12
#define IA_DEBUG_REG1__stage2_rtr_MASK 0x80000
#define IA_DEBUG_REG1__stage2_rtr__SHIFT 0x13
#define IA_DEBUG_REG1__stage3_dr_MASK 0x100000
#define IA_DEBUG_REG1__stage3_dr__SHIFT 0x14
#define IA_DEBUG_REG1__stage3_rtr_MASK 0x200000
#define IA_DEBUG_REG1__stage3_rtr__SHIFT 0x15
#define IA_DEBUG_REG1__stage4_dr_MASK 0x400000
#define IA_DEBUG_REG1__stage4_dr__SHIFT 0x16
#define IA_DEBUG_REG1__stage4_rtr_MASK 0x800000
#define IA_DEBUG_REG1__stage4_rtr__SHIFT 0x17
#define IA_DEBUG_REG1__dma_skid_fifo_empty_MASK 0x1000000
#define IA_DEBUG_REG1__dma_skid_fifo_empty__SHIFT 0x18
#define IA_DEBUG_REG1__dma_skid_fifo_full_MASK 0x2000000
#define IA_DEBUG_REG1__dma_skid_fifo_full__SHIFT 0x19
#define IA_DEBUG_REG1__dma_grp_valid_MASK 0x4000000
#define IA_DEBUG_REG1__dma_grp_valid__SHIFT 0x1a
#define IA_DEBUG_REG1__grp_dma_read_MASK 0x8000000
#define IA_DEBUG_REG1__grp_dma_read__SHIFT 0x1b
#define IA_DEBUG_REG1__current_data_valid_MASK 0x10000000
#define IA_DEBUG_REG1__current_data_valid__SHIFT 0x1c
#define IA_DEBUG_REG1__out_of_range_r2_q_MASK 0x20000000
#define IA_DEBUG_REG1__out_of_range_r2_q__SHIFT 0x1d
#define IA_DEBUG_REG1__dma_mask_fifo_we_MASK 0x40000000
#define IA_DEBUG_REG1__dma_mask_fifo_we__SHIFT 0x1e
#define IA_DEBUG_REG1__dma_ret_data_we_q_MASK 0x80000000
#define IA_DEBUG_REG1__dma_ret_data_we_q__SHIFT 0x1f
#define IA_DEBUG_REG2__hp_dma_input_fifo_empty_MASK 0x1
#define IA_DEBUG_REG2__hp_dma_input_fifo_empty__SHIFT 0x0
#define IA_DEBUG_REG2__hp_dma_input_fifo_full_MASK 0x2
#define IA_DEBUG_REG2__hp_dma_input_fifo_full__SHIFT 0x1
#define IA_DEBUG_REG2__hp_start_new_packet_MASK 0x4
#define IA_DEBUG_REG2__hp_start_new_packet__SHIFT 0x2
#define IA_DEBUG_REG2__hp_dma_rdreq_dr_q_MASK 0x8
#define IA_DEBUG_REG2__hp_dma_rdreq_dr_q__SHIFT 0x3
#define IA_DEBUG_REG2__hp_dma_zero_indices_q_MASK 0x10
#define IA_DEBUG_REG2__hp_dma_zero_indices_q__SHIFT 0x4
#define IA_DEBUG_REG2__hp_dma_buf_type_q_MASK 0x60
#define IA_DEBUG_REG2__hp_dma_buf_type_q__SHIFT 0x5
#define IA_DEBUG_REG2__hp_dma_req_path_q_MASK 0x80
#define IA_DEBUG_REG2__hp_dma_req_path_q__SHIFT 0x7
#define IA_DEBUG_REG2__hp_discard_1st_chunk_MASK 0x100
#define IA_DEBUG_REG2__hp_discard_1st_chunk__SHIFT 0x8
#define IA_DEBUG_REG2__hp_discard_2nd_chunk_MASK 0x200
#define IA_DEBUG_REG2__hp_discard_2nd_chunk__SHIFT 0x9
#define IA_DEBUG_REG2__hp_second_tc_ret_data_q_MASK 0x400
#define IA_DEBUG_REG2__hp_second_tc_ret_data_q__SHIFT 0xa
#define IA_DEBUG_REG2__hp_dma_tc_ret_sel_q_MASK 0x800
#define IA_DEBUG_REG2__hp_dma_tc_ret_sel_q__SHIFT 0xb
#define IA_DEBUG_REG2__hp_last_rdreq_in_dma_op_MASK 0x1000
#define IA_DEBUG_REG2__hp_last_rdreq_in_dma_op__SHIFT 0xc
#define IA_DEBUG_REG2__hp_dma_mask_fifo_empty_MASK 0x2000
#define IA_DEBUG_REG2__hp_dma_mask_fifo_empty__SHIFT 0xd
#define IA_DEBUG_REG2__hp_dma_data_fifo_empty_q_MASK 0x4000
#define IA_DEBUG_REG2__hp_dma_data_fifo_empty_q__SHIFT 0xe
#define IA_DEBUG_REG2__hp_dma_data_fifo_full_MASK 0x8000
#define IA_DEBUG_REG2__hp_dma_data_fifo_full__SHIFT 0xf
#define IA_DEBUG_REG2__hp_dma_req_fifo_empty_MASK 0x10000
#define IA_DEBUG_REG2__hp_dma_req_fifo_empty__SHIFT 0x10
#define IA_DEBUG_REG2__hp_dma_req_fifo_full_MASK 0x20000
#define IA_DEBUG_REG2__hp_dma_req_fifo_full__SHIFT 0x11
#define IA_DEBUG_REG2__hp_stage2_dr_MASK 0x40000
#define IA_DEBUG_REG2__hp_stage2_dr__SHIFT 0x12
#define IA_DEBUG_REG2__hp_stage2_rtr_MASK 0x80000
#define IA_DEBUG_REG2__hp_stage2_rtr__SHIFT 0x13
#define IA_DEBUG_REG2__hp_stage3_dr_MASK 0x100000
#define IA_DEBUG_REG2__hp_stage3_dr__SHIFT 0x14
#define IA_DEBUG_REG2__hp_stage3_rtr_MASK 0x200000
#define IA_DEBUG_REG2__hp_stage3_rtr__SHIFT 0x15
#define IA_DEBUG_REG2__hp_stage4_dr_MASK 0x400000
#define IA_DEBUG_REG2__hp_stage4_dr__SHIFT 0x16
#define IA_DEBUG_REG2__hp_stage4_rtr_MASK 0x800000
#define IA_DEBUG_REG2__hp_stage4_rtr__SHIFT 0x17
#define IA_DEBUG_REG2__hp_dma_skid_fifo_empty_MASK 0x1000000
#define IA_DEBUG_REG2__hp_dma_skid_fifo_empty__SHIFT 0x18
#define IA_DEBUG_REG2__hp_dma_skid_fifo_full_MASK 0x2000000
#define IA_DEBUG_REG2__hp_dma_skid_fifo_full__SHIFT 0x19
#define IA_DEBUG_REG2__hp_dma_grp_valid_MASK 0x4000000
#define IA_DEBUG_REG2__hp_dma_grp_valid__SHIFT 0x1a
#define IA_DEBUG_REG2__hp_grp_dma_read_MASK 0x8000000
#define IA_DEBUG_REG2__hp_grp_dma_read__SHIFT 0x1b
#define IA_DEBUG_REG2__hp_current_data_valid_MASK 0x10000000
#define IA_DEBUG_REG2__hp_current_data_valid__SHIFT 0x1c
#define IA_DEBUG_REG2__hp_out_of_range_r2_q_MASK 0x20000000
#define IA_DEBUG_REG2__hp_out_of_range_r2_q__SHIFT 0x1d
#define IA_DEBUG_REG2__hp_dma_mask_fifo_we_MASK 0x40000000
#define IA_DEBUG_REG2__hp_dma_mask_fifo_we__SHIFT 0x1e
#define IA_DEBUG_REG2__hp_dma_ret_data_we_q_MASK 0x80000000
#define IA_DEBUG_REG2__hp_dma_ret_data_we_q__SHIFT 0x1f
#define IA_DEBUG_REG3__dma_pipe0_rdreq_valid_MASK 0x1
#define IA_DEBUG_REG3__dma_pipe0_rdreq_valid__SHIFT 0x0
#define IA_DEBUG_REG3__dma_pipe0_rdreq_read_MASK 0x2
#define IA_DEBUG_REG3__dma_pipe0_rdreq_read__SHIFT 0x1
#define IA_DEBUG_REG3__dma_pipe0_rdreq_null_out_MASK 0x4
#define IA_DEBUG_REG3__dma_pipe0_rdreq_null_out__SHIFT 0x2
#define IA_DEBUG_REG3__dma_pipe0_rdreq_eop_out_MASK 0x8
#define IA_DEBUG_REG3__dma_pipe0_rdreq_eop_out__SHIFT 0x3
#define IA_DEBUG_REG3__dma_pipe0_rdreq_use_tc_out_MASK 0x10
#define IA_DEBUG_REG3__dma_pipe0_rdreq_use_tc_out__SHIFT 0x4
#define IA_DEBUG_REG3__grp_dma_draw_is_pipe0_MASK 0x20
#define IA_DEBUG_REG3__grp_dma_draw_is_pipe0__SHIFT 0x5
#define IA_DEBUG_REG3__must_service_pipe0_req_MASK 0x40
#define IA_DEBUG_REG3__must_service_pipe0_req__SHIFT 0x6
#define IA_DEBUG_REG3__send_pipe1_req_MASK 0x80
#define IA_DEBUG_REG3__send_pipe1_req__SHIFT 0x7
#define IA_DEBUG_REG3__dma_pipe1_rdreq_valid_MASK 0x100
#define IA_DEBUG_REG3__dma_pipe1_rdreq_valid__SHIFT 0x8
#define IA_DEBUG_REG3__dma_pipe1_rdreq_read_MASK 0x200
#define IA_DEBUG_REG3__dma_pipe1_rdreq_read__SHIFT 0x9
#define IA_DEBUG_REG3__dma_pipe1_rdreq_null_out_MASK 0x400
#define IA_DEBUG_REG3__dma_pipe1_rdreq_null_out__SHIFT 0xa
#define IA_DEBUG_REG3__dma_pipe1_rdreq_eop_out_MASK 0x800
#define IA_DEBUG_REG3__dma_pipe1_rdreq_eop_out__SHIFT 0xb
#define IA_DEBUG_REG3__dma_pipe1_rdreq_use_tc_out_MASK 0x1000
#define IA_DEBUG_REG3__dma_pipe1_rdreq_use_tc_out__SHIFT 0xc
#define IA_DEBUG_REG3__ia_mc_rdreq_rtr_q_MASK 0x2000
#define IA_DEBUG_REG3__ia_mc_rdreq_rtr_q__SHIFT 0xd
#define IA_DEBUG_REG3__mc_out_rtr_MASK 0x4000
#define IA_DEBUG_REG3__mc_out_rtr__SHIFT 0xe
#define IA_DEBUG_REG3__dma_rdreq_send_out_MASK 0x8000
#define IA_DEBUG_REG3__dma_rdreq_send_out__SHIFT 0xf
#define IA_DEBUG_REG3__pipe0_dr_MASK 0x10000
#define IA_DEBUG_REG3__pipe0_dr__SHIFT 0x10
#define IA_DEBUG_REG3__pipe0_rtr_MASK 0x20000
#define IA_DEBUG_REG3__pipe0_rtr__SHIFT 0x11
#define IA_DEBUG_REG3__ia_tc_rdreq_rtr_q_MASK 0x40000
#define IA_DEBUG_REG3__ia_tc_rdreq_rtr_q__SHIFT 0x12
#define IA_DEBUG_REG3__tc_out_rtr_MASK 0x80000
#define IA_DEBUG_REG3__tc_out_rtr__SHIFT 0x13
#define IA_DEBUG_REG3__pair0_valid_p1_MASK 0x100000
#define IA_DEBUG_REG3__pair0_valid_p1__SHIFT 0x14
#define IA_DEBUG_REG3__pair1_valid_p1_MASK 0x200000
#define IA_DEBUG_REG3__pair1_valid_p1__SHIFT 0x15
#define IA_DEBUG_REG3__pair2_valid_p1_MASK 0x400000
#define IA_DEBUG_REG3__pair2_valid_p1__SHIFT 0x16
#define IA_DEBUG_REG3__pair3_valid_p1_MASK 0x800000
#define IA_DEBUG_REG3__pair3_valid_p1__SHIFT 0x17
#define IA_DEBUG_REG3__tc_req_count_q_MASK 0x3000000
#define IA_DEBUG_REG3__tc_req_count_q__SHIFT 0x18
#define IA_DEBUG_REG3__discard_1st_chunk_MASK 0x4000000
#define IA_DEBUG_REG3__discard_1st_chunk__SHIFT 0x1a
#define IA_DEBUG_REG3__discard_2nd_chunk_MASK 0x8000000
#define IA_DEBUG_REG3__discard_2nd_chunk__SHIFT 0x1b
#define IA_DEBUG_REG3__last_tc_req_p1_MASK 0x10000000
#define IA_DEBUG_REG3__last_tc_req_p1__SHIFT 0x1c
#define IA_DEBUG_REG3__IA_TC_rdreq_send_out_MASK 0x20000000
#define IA_DEBUG_REG3__IA_TC_rdreq_send_out__SHIFT 0x1d
#define IA_DEBUG_REG3__TC_IA_rdret_valid_in_MASK 0x40000000
#define IA_DEBUG_REG3__TC_IA_rdret_valid_in__SHIFT 0x1e
#define IA_DEBUG_REG3__TAP_IA_rdret_vld_in_MASK 0x80000000
#define IA_DEBUG_REG3__TAP_IA_rdret_vld_in__SHIFT 0x1f
#define IA_DEBUG_REG4__pipe0_dr_MASK 0x1
#define IA_DEBUG_REG4__pipe0_dr__SHIFT 0x0
#define IA_DEBUG_REG4__pipe1_dr_MASK 0x2
#define IA_DEBUG_REG4__pipe1_dr__SHIFT 0x1
#define IA_DEBUG_REG4__pipe2_dr_MASK 0x4
#define IA_DEBUG_REG4__pipe2_dr__SHIFT 0x2
#define IA_DEBUG_REG4__pipe3_dr_MASK 0x8
#define IA_DEBUG_REG4__pipe3_dr__SHIFT 0x3
#define IA_DEBUG_REG4__pipe4_dr_MASK 0x10
#define IA_DEBUG_REG4__pipe4_dr__SHIFT 0x4
#define IA_DEBUG_REG4__pipe5_dr_MASK 0x20
#define IA_DEBUG_REG4__pipe5_dr__SHIFT 0x5
#define IA_DEBUG_REG4__grp_se0_fifo_empty_MASK 0x40
#define IA_DEBUG_REG4__grp_se0_fifo_empty__SHIFT 0x6
#define IA_DEBUG_REG4__grp_se0_fifo_full_MASK 0x80
#define IA_DEBUG_REG4__grp_se0_fifo_full__SHIFT 0x7
#define IA_DEBUG_REG4__pipe0_rtr_MASK 0x100
#define IA_DEBUG_REG4__pipe0_rtr__SHIFT 0x8
#define IA_DEBUG_REG4__pipe1_rtr_MASK 0x200
#define IA_DEBUG_REG4__pipe1_rtr__SHIFT 0x9
#define IA_DEBUG_REG4__pipe2_rtr_MASK 0x400
#define IA_DEBUG_REG4__pipe2_rtr__SHIFT 0xa
#define IA_DEBUG_REG4__pipe3_rtr_MASK 0x800
#define IA_DEBUG_REG4__pipe3_rtr__SHIFT 0xb
#define IA_DEBUG_REG4__pipe4_rtr_MASK 0x1000
#define IA_DEBUG_REG4__pipe4_rtr__SHIFT 0xc
#define IA_DEBUG_REG4__pipe5_rtr_MASK 0x2000
#define IA_DEBUG_REG4__pipe5_rtr__SHIFT 0xd
#define IA_DEBUG_REG4__ia_vgt_prim_rtr_q_MASK 0x4000
#define IA_DEBUG_REG4__ia_vgt_prim_rtr_q__SHIFT 0xe
#define IA_DEBUG_REG4__ia_se1vgt_prim_rtr_q_MASK 0x8000
#define IA_DEBUG_REG4__ia_se1vgt_prim_rtr_q__SHIFT 0xf
#define IA_DEBUG_REG4__di_major_mode_p1_q_MASK 0x10000
#define IA_DEBUG_REG4__di_major_mode_p1_q__SHIFT 0x10
#define IA_DEBUG_REG4__gs_mode_p1_q_MASK 0xe0000
#define IA_DEBUG_REG4__gs_mode_p1_q__SHIFT 0x11
#define IA_DEBUG_REG4__di_event_flag_p1_q_MASK 0x100000
#define IA_DEBUG_REG4__di_event_flag_p1_q__SHIFT 0x14
#define IA_DEBUG_REG4__di_state_sel_p1_q_MASK 0xe00000
#define IA_DEBUG_REG4__di_state_sel_p1_q__SHIFT 0x15
#define IA_DEBUG_REG4__draw_opaq_en_p1_q_MASK 0x1000000
#define IA_DEBUG_REG4__draw_opaq_en_p1_q__SHIFT 0x18
#define IA_DEBUG_REG4__draw_opaq_active_q_MASK 0x2000000
#define IA_DEBUG_REG4__draw_opaq_active_q__SHIFT 0x19
#define IA_DEBUG_REG4__di_source_select_p1_q_MASK 0xc000000
#define IA_DEBUG_REG4__di_source_select_p1_q__SHIFT 0x1a
#define IA_DEBUG_REG4__ready_to_read_di_MASK 0x10000000
#define IA_DEBUG_REG4__ready_to_read_di__SHIFT 0x1c
#define IA_DEBUG_REG4__di_first_group_of_draw_q_MASK 0x20000000
#define IA_DEBUG_REG4__di_first_group_of_draw_q__SHIFT 0x1d
#define IA_DEBUG_REG4__last_shift_of_draw_MASK 0x40000000
#define IA_DEBUG_REG4__last_shift_of_draw__SHIFT 0x1e
#define IA_DEBUG_REG4__current_shift_is_vect1_q_MASK 0x80000000
#define IA_DEBUG_REG4__current_shift_is_vect1_q__SHIFT 0x1f
#define IA_DEBUG_REG5__di_index_counter_q_15_0_MASK 0xffff
#define IA_DEBUG_REG5__di_index_counter_q_15_0__SHIFT 0x0
#define IA_DEBUG_REG5__instanceid_13_0_MASK 0x3fff0000
#define IA_DEBUG_REG5__instanceid_13_0__SHIFT 0x10
#define IA_DEBUG_REG5__draw_input_fifo_full_MASK 0x40000000
#define IA_DEBUG_REG5__draw_input_fifo_full__SHIFT 0x1e
#define IA_DEBUG_REG5__draw_input_fifo_empty_MASK 0x80000000
#define IA_DEBUG_REG5__draw_input_fifo_empty__SHIFT 0x1f
#define IA_DEBUG_REG6__current_shift_q_MASK 0xf
#define IA_DEBUG_REG6__current_shift_q__SHIFT 0x0
#define IA_DEBUG_REG6__current_stride_pre_MASK 0xf0
#define IA_DEBUG_REG6__current_stride_pre__SHIFT 0x4
#define IA_DEBUG_REG6__current_stride_q_MASK 0x1f00
#define IA_DEBUG_REG6__current_stride_q__SHIFT 0x8
#define IA_DEBUG_REG6__first_group_partial_MASK 0x2000
#define IA_DEBUG_REG6__first_group_partial__SHIFT 0xd
#define IA_DEBUG_REG6__second_group_partial_MASK 0x4000
#define IA_DEBUG_REG6__second_group_partial__SHIFT 0xe
#define IA_DEBUG_REG6__curr_prim_partial_MASK 0x8000
#define IA_DEBUG_REG6__curr_prim_partial__SHIFT 0xf
#define IA_DEBUG_REG6__next_stride_q_MASK 0x1f0000
#define IA_DEBUG_REG6__next_stride_q__SHIFT 0x10
#define IA_DEBUG_REG6__next_group_partial_MASK 0x200000
#define IA_DEBUG_REG6__next_group_partial__SHIFT 0x15
#define IA_DEBUG_REG6__after_group_partial_MASK 0x400000
#define IA_DEBUG_REG6__after_group_partial__SHIFT 0x16
#define IA_DEBUG_REG6__extract_group_MASK 0x800000
#define IA_DEBUG_REG6__extract_group__SHIFT 0x17
#define IA_DEBUG_REG6__grp_shift_debug_data_MASK 0xff000000
#define IA_DEBUG_REG6__grp_shift_debug_data__SHIFT 0x18
#define IA_DEBUG_REG7__reset_indx_state_q_MASK 0xf
#define IA_DEBUG_REG7__reset_indx_state_q__SHIFT 0x0
#define IA_DEBUG_REG7__shift_vect_valid_p2_q_MASK 0xf0
#define IA_DEBUG_REG7__shift_vect_valid_p2_q__SHIFT 0x4
#define IA_DEBUG_REG7__shift_vect1_valid_p2_q_MASK 0xf00
#define IA_DEBUG_REG7__shift_vect1_valid_p2_q__SHIFT 0x8
#define IA_DEBUG_REG7__shift_vect0_reset_match_p2_q_MASK 0xf000
#define IA_DEBUG_REG7__shift_vect0_reset_match_p2_q__SHIFT 0xc
#define IA_DEBUG_REG7__shift_vect1_reset_match_p2_q_MASK 0xf0000
#define IA_DEBUG_REG7__shift_vect1_reset_match_p2_q__SHIFT 0x10
#define IA_DEBUG_REG7__num_indx_in_group_p2_q_MASK 0x700000
#define IA_DEBUG_REG7__num_indx_in_group_p2_q__SHIFT 0x14
#define IA_DEBUG_REG7__last_group_of_draw_p2_q_MASK 0x800000
#define IA_DEBUG_REG7__last_group_of_draw_p2_q__SHIFT 0x17
#define IA_DEBUG_REG7__shift_event_flag_p2_q_MASK 0x1000000
#define IA_DEBUG_REG7__shift_event_flag_p2_q__SHIFT 0x18
#define IA_DEBUG_REG7__indx_shift_is_one_p2_q_MASK 0x2000000
#define IA_DEBUG_REG7__indx_shift_is_one_p2_q__SHIFT 0x19
#define IA_DEBUG_REG7__indx_shift_is_two_p2_q_MASK 0x4000000
#define IA_DEBUG_REG7__indx_shift_is_two_p2_q__SHIFT 0x1a
#define IA_DEBUG_REG7__indx_stride_is_four_p2_q_MASK 0x8000000
#define IA_DEBUG_REG7__indx_stride_is_four_p2_q__SHIFT 0x1b
#define IA_DEBUG_REG7__shift_prim1_reset_p3_q_MASK 0x10000000
#define IA_DEBUG_REG7__shift_prim1_reset_p3_q__SHIFT 0x1c
#define IA_DEBUG_REG7__shift_prim1_partial_p3_q_MASK 0x20000000
#define IA_DEBUG_REG7__shift_prim1_partial_p3_q__SHIFT 0x1d
#define IA_DEBUG_REG7__shift_prim0_reset_p3_q_MASK 0x40000000
#define IA_DEBUG_REG7__shift_prim0_reset_p3_q__SHIFT 0x1e
#define IA_DEBUG_REG7__shift_prim0_partial_p3_q_MASK 0x80000000
#define IA_DEBUG_REG7__shift_prim0_partial_p3_q__SHIFT 0x1f
#define IA_DEBUG_REG8__di_prim_type_p1_q_MASK 0x1f
#define IA_DEBUG_REG8__di_prim_type_p1_q__SHIFT 0x0
#define IA_DEBUG_REG8__two_cycle_xfer_p1_q_MASK 0x20
#define IA_DEBUG_REG8__two_cycle_xfer_p1_q__SHIFT 0x5
#define IA_DEBUG_REG8__two_prim_input_p1_q_MASK 0x40
#define IA_DEBUG_REG8__two_prim_input_p1_q__SHIFT 0x6
#define IA_DEBUG_REG8__shift_vect_end_of_packet_p5_q_MASK 0x80
#define IA_DEBUG_REG8__shift_vect_end_of_packet_p5_q__SHIFT 0x7
#define IA_DEBUG_REG8__last_group_of_inst_p5_q_MASK 0x100
#define IA_DEBUG_REG8__last_group_of_inst_p5_q__SHIFT 0x8
#define IA_DEBUG_REG8__shift_prim1_null_flag_p5_q_MASK 0x200
#define IA_DEBUG_REG8__shift_prim1_null_flag_p5_q__SHIFT 0x9
#define IA_DEBUG_REG8__shift_prim0_null_flag_p5_q_MASK 0x400
#define IA_DEBUG_REG8__shift_prim0_null_flag_p5_q__SHIFT 0xa
#define IA_DEBUG_REG8__grp_continued_MASK 0x800
#define IA_DEBUG_REG8__grp_continued__SHIFT 0xb
#define IA_DEBUG_REG8__grp_state_sel_MASK 0x7000
#define IA_DEBUG_REG8__grp_state_sel__SHIFT 0xc
#define IA_DEBUG_REG8__grp_sub_prim_type_MASK 0x1f8000
#define IA_DEBUG_REG8__grp_sub_prim_type__SHIFT 0xf
#define IA_DEBUG_REG8__grp_output_path_MASK 0xe00000
#define IA_DEBUG_REG8__grp_output_path__SHIFT 0x15
#define IA_DEBUG_REG8__grp_null_primitive_MASK 0x1000000
#define IA_DEBUG_REG8__grp_null_primitive__SHIFT 0x18
#define IA_DEBUG_REG8__grp_eop_MASK 0x2000000
#define IA_DEBUG_REG8__grp_eop__SHIFT 0x19
#define IA_DEBUG_REG8__grp_eopg_MASK 0x4000000
#define IA_DEBUG_REG8__grp_eopg__SHIFT 0x1a
#define IA_DEBUG_REG8__grp_event_flag_MASK 0x8000000
#define IA_DEBUG_REG8__grp_event_flag__SHIFT 0x1b
#define IA_DEBUG_REG8__grp_components_valid_MASK 0xf0000000
#define IA_DEBUG_REG8__grp_components_valid__SHIFT 0x1c
#define IA_DEBUG_REG9__send_to_se1_p6_MASK 0x1
#define IA_DEBUG_REG9__send_to_se1_p6__SHIFT 0x0
#define IA_DEBUG_REG9__gfx_se_switch_p6_MASK 0x2
#define IA_DEBUG_REG9__gfx_se_switch_p6__SHIFT 0x1
#define IA_DEBUG_REG9__null_eoi_xfer_prim1_p6_MASK 0x4
#define IA_DEBUG_REG9__null_eoi_xfer_prim1_p6__SHIFT 0x2
#define IA_DEBUG_REG9__null_eoi_xfer_prim0_p6_MASK 0x8
#define IA_DEBUG_REG9__null_eoi_xfer_prim0_p6__SHIFT 0x3
#define IA_DEBUG_REG9__prim1_eoi_p6_MASK 0x10
#define IA_DEBUG_REG9__prim1_eoi_p6__SHIFT 0x4
#define IA_DEBUG_REG9__prim0_eoi_p6_MASK 0x20
#define IA_DEBUG_REG9__prim0_eoi_p6__SHIFT 0x5
#define IA_DEBUG_REG9__prim1_valid_eopg_p6_MASK 0x40
#define IA_DEBUG_REG9__prim1_valid_eopg_p6__SHIFT 0x6
#define IA_DEBUG_REG9__prim0_valid_eopg_p6_MASK 0x80
#define IA_DEBUG_REG9__prim0_valid_eopg_p6__SHIFT 0x7
#define IA_DEBUG_REG9__prim1_to_other_se_p6_MASK 0x100
#define IA_DEBUG_REG9__prim1_to_other_se_p6__SHIFT 0x8
#define IA_DEBUG_REG9__eopg_on_last_prim_p6_MASK 0x200
#define IA_DEBUG_REG9__eopg_on_last_prim_p6__SHIFT 0x9
#define IA_DEBUG_REG9__eopg_between_prims_p6_MASK 0x400
#define IA_DEBUG_REG9__eopg_between_prims_p6__SHIFT 0xa
#define IA_DEBUG_REG9__prim_count_eq_group_size_p6_MASK 0x800
#define IA_DEBUG_REG9__prim_count_eq_group_size_p6__SHIFT 0xb
#define IA_DEBUG_REG9__prim_count_gt_group_size_p6_MASK 0x1000
#define IA_DEBUG_REG9__prim_count_gt_group_size_p6__SHIFT 0xc
#define IA_DEBUG_REG9__two_prim_output_p5_q_MASK 0x2000
#define IA_DEBUG_REG9__two_prim_output_p5_q__SHIFT 0xd
#define IA_DEBUG_REG9__SPARE0_MASK 0x4000
#define IA_DEBUG_REG9__SPARE0__SHIFT 0xe
#define IA_DEBUG_REG9__SPARE1_MASK 0x8000
#define IA_DEBUG_REG9__SPARE1__SHIFT 0xf
#define IA_DEBUG_REG9__shift_vect_end_of_packet_p5_q_MASK 0x10000
#define IA_DEBUG_REG9__shift_vect_end_of_packet_p5_q__SHIFT 0x10
#define IA_DEBUG_REG9__prim1_xfer_p6_MASK 0x20000
#define IA_DEBUG_REG9__prim1_xfer_p6__SHIFT 0x11
#define IA_DEBUG_REG9__grp_se1_fifo_empty_MASK 0x40000
#define IA_DEBUG_REG9__grp_se1_fifo_empty__SHIFT 0x12
#define IA_DEBUG_REG9__grp_se1_fifo_full_MASK 0x80000
#define IA_DEBUG_REG9__grp_se1_fifo_full__SHIFT 0x13
#define IA_DEBUG_REG9__prim_counter_q_MASK 0xfff00000
#define IA_DEBUG_REG9__prim_counter_q__SHIFT 0x14
#define VGT_DEBUG_REG0__vgt_busy_extended_MASK 0x1
#define VGT_DEBUG_REG0__vgt_busy_extended__SHIFT 0x0
#define VGT_DEBUG_REG0__SPARE9_MASK 0x2
#define VGT_DEBUG_REG0__SPARE9__SHIFT 0x1
#define VGT_DEBUG_REG0__vgt_busy_MASK 0x4
#define VGT_DEBUG_REG0__vgt_busy__SHIFT 0x2
#define VGT_DEBUG_REG0__SPARE8_MASK 0x8
#define VGT_DEBUG_REG0__SPARE8__SHIFT 0x3
#define VGT_DEBUG_REG0__SPARE7_MASK 0x10
#define VGT_DEBUG_REG0__SPARE7__SHIFT 0x4
#define VGT_DEBUG_REG0__SPARE6_MASK 0x20
#define VGT_DEBUG_REG0__SPARE6__SHIFT 0x5
#define VGT_DEBUG_REG0__SPARE5_MASK 0x40
#define VGT_DEBUG_REG0__SPARE5__SHIFT 0x6
#define VGT_DEBUG_REG0__SPARE4_MASK 0x80
#define VGT_DEBUG_REG0__SPARE4__SHIFT 0x7
#define VGT_DEBUG_REG0__pi_busy_MASK 0x100
#define VGT_DEBUG_REG0__pi_busy__SHIFT 0x8
#define VGT_DEBUG_REG0__vr_pi_busy_MASK 0x200
#define VGT_DEBUG_REG0__vr_pi_busy__SHIFT 0x9
#define VGT_DEBUG_REG0__pt_pi_busy_MASK 0x400
#define VGT_DEBUG_REG0__pt_pi_busy__SHIFT 0xa
#define VGT_DEBUG_REG0__te_pi_busy_MASK 0x800
#define VGT_DEBUG_REG0__te_pi_busy__SHIFT 0xb
#define VGT_DEBUG_REG0__gs_busy_MASK 0x1000
#define VGT_DEBUG_REG0__gs_busy__SHIFT 0xc
#define VGT_DEBUG_REG0__rcm_busy_MASK 0x2000
#define VGT_DEBUG_REG0__rcm_busy__SHIFT 0xd
#define VGT_DEBUG_REG0__tm_busy_MASK 0x4000
#define VGT_DEBUG_REG0__tm_busy__SHIFT 0xe
#define VGT_DEBUG_REG0__cm_busy_MASK 0x8000
#define VGT_DEBUG_REG0__cm_busy__SHIFT 0xf
#define VGT_DEBUG_REG0__gog_busy_MASK 0x10000
#define VGT_DEBUG_REG0__gog_busy__SHIFT 0x10
#define VGT_DEBUG_REG0__frmt_busy_MASK 0x20000
#define VGT_DEBUG_REG0__frmt_busy__SHIFT 0x11
#define VGT_DEBUG_REG0__SPARE10_MASK 0x40000
#define VGT_DEBUG_REG0__SPARE10__SHIFT 0x12
#define VGT_DEBUG_REG0__te11_pi_busy_MASK 0x80000
#define VGT_DEBUG_REG0__te11_pi_busy__SHIFT 0x13
#define VGT_DEBUG_REG0__SPARE3_MASK 0x100000
#define VGT_DEBUG_REG0__SPARE3__SHIFT 0x14
#define VGT_DEBUG_REG0__combined_out_busy_MASK 0x200000
#define VGT_DEBUG_REG0__combined_out_busy__SHIFT 0x15
#define VGT_DEBUG_REG0__spi_vs_interfaces_busy_MASK 0x400000
#define VGT_DEBUG_REG0__spi_vs_interfaces_busy__SHIFT 0x16
#define VGT_DEBUG_REG0__pa_interfaces_busy_MASK 0x800000
#define VGT_DEBUG_REG0__pa_interfaces_busy__SHIFT 0x17
#define VGT_DEBUG_REG0__reg_clk_busy_MASK 0x1000000
#define VGT_DEBUG_REG0__reg_clk_busy__SHIFT 0x18
#define VGT_DEBUG_REG0__SPARE2_MASK 0x2000000
#define VGT_DEBUG_REG0__SPARE2__SHIFT 0x19
#define VGT_DEBUG_REG0__core_clk_busy_MASK 0x4000000
#define VGT_DEBUG_REG0__core_clk_busy__SHIFT 0x1a
#define VGT_DEBUG_REG0__gs_clk_busy_MASK 0x8000000
#define VGT_DEBUG_REG0__gs_clk_busy__SHIFT 0x1b
#define VGT_DEBUG_REG0__SPARE1_MASK 0x10000000
#define VGT_DEBUG_REG0__SPARE1__SHIFT 0x1c
#define VGT_DEBUG_REG0__sclk_core_vld_MASK 0x20000000
#define VGT_DEBUG_REG0__sclk_core_vld__SHIFT 0x1d
#define VGT_DEBUG_REG0__sclk_gs_vld_MASK 0x40000000
#define VGT_DEBUG_REG0__sclk_gs_vld__SHIFT 0x1e
#define VGT_DEBUG_REG0__SPARE0_MASK 0x80000000
#define VGT_DEBUG_REG0__SPARE0__SHIFT 0x1f
#define VGT_DEBUG_REG1__SPARE9_MASK 0x1
#define VGT_DEBUG_REG1__SPARE9__SHIFT 0x0
#define VGT_DEBUG_REG1__SPARE8_MASK 0x2
#define VGT_DEBUG_REG1__SPARE8__SHIFT 0x1
#define VGT_DEBUG_REG1__SPARE7_MASK 0x4
#define VGT_DEBUG_REG1__SPARE7__SHIFT 0x2
#define VGT_DEBUG_REG1__SPARE6_MASK 0x8
#define VGT_DEBUG_REG1__SPARE6__SHIFT 0x3
#define VGT_DEBUG_REG1__SPARE5_MASK 0x10
#define VGT_DEBUG_REG1__SPARE5__SHIFT 0x4
#define VGT_DEBUG_REG1__SPARE4_MASK 0x20
#define VGT_DEBUG_REG1__SPARE4__SHIFT 0x5
#define VGT_DEBUG_REG1__SPARE3_MASK 0x40
#define VGT_DEBUG_REG1__SPARE3__SHIFT 0x6
#define VGT_DEBUG_REG1__SPARE2_MASK 0x80
#define VGT_DEBUG_REG1__SPARE2__SHIFT 0x7
#define VGT_DEBUG_REG1__SPARE1_MASK 0x100
#define VGT_DEBUG_REG1__SPARE1__SHIFT 0x8
#define VGT_DEBUG_REG1__SPARE0_MASK 0x200
#define VGT_DEBUG_REG1__SPARE0__SHIFT 0x9
#define VGT_DEBUG_REG1__pi_vr_valid_MASK 0x400
#define VGT_DEBUG_REG1__pi_vr_valid__SHIFT 0xa
#define VGT_DEBUG_REG1__vr_pi_read_MASK 0x800
#define VGT_DEBUG_REG1__vr_pi_read__SHIFT 0xb
#define VGT_DEBUG_REG1__pi_pt_valid_MASK 0x1000
#define VGT_DEBUG_REG1__pi_pt_valid__SHIFT 0xc
#define VGT_DEBUG_REG1__pt_pi_read_MASK 0x2000
#define VGT_DEBUG_REG1__pt_pi_read__SHIFT 0xd
#define VGT_DEBUG_REG1__pi_te_valid_MASK 0x4000
#define VGT_DEBUG_REG1__pi_te_valid__SHIFT 0xe
#define VGT_DEBUG_REG1__te_grp_read_MASK 0x8000
#define VGT_DEBUG_REG1__te_grp_read__SHIFT 0xf
#define VGT_DEBUG_REG1__vr_out_indx_valid_MASK 0x10000
#define VGT_DEBUG_REG1__vr_out_indx_valid__SHIFT 0x10
#define VGT_DEBUG_REG1__SPARE12_MASK 0x20000
#define VGT_DEBUG_REG1__SPARE12__SHIFT 0x11
#define VGT_DEBUG_REG1__vr_out_prim_valid_MASK 0x40000
#define VGT_DEBUG_REG1__vr_out_prim_valid__SHIFT 0x12
#define VGT_DEBUG_REG1__SPARE11_MASK 0x80000
#define VGT_DEBUG_REG1__SPARE11__SHIFT 0x13
#define VGT_DEBUG_REG1__pt_out_indx_valid_MASK 0x100000
#define VGT_DEBUG_REG1__pt_out_indx_valid__SHIFT 0x14
#define VGT_DEBUG_REG1__SPARE10_MASK 0x200000
#define VGT_DEBUG_REG1__SPARE10__SHIFT 0x15
#define VGT_DEBUG_REG1__pt_out_prim_valid_MASK 0x400000
#define VGT_DEBUG_REG1__pt_out_prim_valid__SHIFT 0x16
#define VGT_DEBUG_REG1__SPARE23_MASK 0x800000
#define VGT_DEBUG_REG1__SPARE23__SHIFT 0x17
#define VGT_DEBUG_REG1__te_out_data_valid_MASK 0x1000000
#define VGT_DEBUG_REG1__te_out_data_valid__SHIFT 0x18
#define VGT_DEBUG_REG1__SPARE25_MASK 0x2000000
#define VGT_DEBUG_REG1__SPARE25__SHIFT 0x19
#define VGT_DEBUG_REG1__pi_gs_valid_MASK 0x4000000
#define VGT_DEBUG_REG1__pi_gs_valid__SHIFT 0x1a
#define VGT_DEBUG_REG1__gs_pi_read_MASK 0x8000000
#define VGT_DEBUG_REG1__gs_pi_read__SHIFT 0x1b
#define VGT_DEBUG_REG1__gog_out_indx_valid_MASK 0x10000000
#define VGT_DEBUG_REG1__gog_out_indx_valid__SHIFT 0x1c
#define VGT_DEBUG_REG1__out_indx_read_MASK 0x20000000
#define VGT_DEBUG_REG1__out_indx_read__SHIFT 0x1d
#define VGT_DEBUG_REG1__gog_out_prim_valid_MASK 0x40000000
#define VGT_DEBUG_REG1__gog_out_prim_valid__SHIFT 0x1e
#define VGT_DEBUG_REG1__out_prim_read_MASK 0x80000000
#define VGT_DEBUG_REG1__out_prim_read__SHIFT 0x1f
#define VGT_DEBUG_REG2__hs_grp_busy_MASK 0x1
#define VGT_DEBUG_REG2__hs_grp_busy__SHIFT 0x0
#define VGT_DEBUG_REG2__hs_noif_busy_MASK 0x2
#define VGT_DEBUG_REG2__hs_noif_busy__SHIFT 0x1
#define VGT_DEBUG_REG2__tfmmIsBusy_MASK 0x4
#define VGT_DEBUG_REG2__tfmmIsBusy__SHIFT 0x2
#define VGT_DEBUG_REG2__lsVertIfBusy_0_MASK 0x8
#define VGT_DEBUG_REG2__lsVertIfBusy_0__SHIFT 0x3
#define VGT_DEBUG_REG2__te11_hs_tess_input_rtr_MASK 0x10
#define VGT_DEBUG_REG2__te11_hs_tess_input_rtr__SHIFT 0x4
#define VGT_DEBUG_REG2__lsWaveIfBusy_0_MASK 0x20
#define VGT_DEBUG_REG2__lsWaveIfBusy_0__SHIFT 0x5
#define VGT_DEBUG_REG2__hs_te11_tess_input_rts_MASK 0x40
#define VGT_DEBUG_REG2__hs_te11_tess_input_rts__SHIFT 0x6
#define VGT_DEBUG_REG2__grpModBusy_MASK 0x80
#define VGT_DEBUG_REG2__grpModBusy__SHIFT 0x7
#define VGT_DEBUG_REG2__lsVertFifoEmpty_MASK 0x100
#define VGT_DEBUG_REG2__lsVertFifoEmpty__SHIFT 0x8
#define VGT_DEBUG_REG2__lsWaveFifoEmpty_MASK 0x200
#define VGT_DEBUG_REG2__lsWaveFifoEmpty__SHIFT 0x9
#define VGT_DEBUG_REG2__hsVertFifoEmpty_MASK 0x400
#define VGT_DEBUG_REG2__hsVertFifoEmpty__SHIFT 0xa
#define VGT_DEBUG_REG2__hsWaveFifoEmpty_MASK 0x800
#define VGT_DEBUG_REG2__hsWaveFifoEmpty__SHIFT 0xb
#define VGT_DEBUG_REG2__hsInputFifoEmpty_MASK 0x1000
#define VGT_DEBUG_REG2__hsInputFifoEmpty__SHIFT 0xc
#define VGT_DEBUG_REG2__hsTifFifoEmpty_MASK 0x2000
#define VGT_DEBUG_REG2__hsTifFifoEmpty__SHIFT 0xd
#define VGT_DEBUG_REG2__lsVertFifoFull_MASK 0x4000
#define VGT_DEBUG_REG2__lsVertFifoFull__SHIFT 0xe
#define VGT_DEBUG_REG2__lsWaveFifoFull_MASK 0x8000
#define VGT_DEBUG_REG2__lsWaveFifoFull__SHIFT 0xf
#define VGT_DEBUG_REG2__hsVertFifoFull_MASK 0x10000
#define VGT_DEBUG_REG2__hsVertFifoFull__SHIFT 0x10
#define VGT_DEBUG_REG2__hsWaveFifoFull_MASK 0x20000
#define VGT_DEBUG_REG2__hsWaveFifoFull__SHIFT 0x11
#define VGT_DEBUG_REG2__hsInputFifoFull_MASK 0x40000
#define VGT_DEBUG_REG2__hsInputFifoFull__SHIFT 0x12
#define VGT_DEBUG_REG2__hsTifFifoFull_MASK 0x80000
#define VGT_DEBUG_REG2__hsTifFifoFull__SHIFT 0x13
#define VGT_DEBUG_REG2__p0_rtr_MASK 0x100000
#define VGT_DEBUG_REG2__p0_rtr__SHIFT 0x14
#define VGT_DEBUG_REG2__p1_rtr_MASK 0x200000
#define VGT_DEBUG_REG2__p1_rtr__SHIFT 0x15
#define VGT_DEBUG_REG2__p0_dr_MASK 0x400000
#define VGT_DEBUG_REG2__p0_dr__SHIFT 0x16
#define VGT_DEBUG_REG2__p1_dr_MASK 0x800000
#define VGT_DEBUG_REG2__p1_dr__SHIFT 0x17
#define VGT_DEBUG_REG2__p0_rts_MASK 0x1000000
#define VGT_DEBUG_REG2__p0_rts__SHIFT 0x18
#define VGT_DEBUG_REG2__p1_rts_MASK 0x2000000
#define VGT_DEBUG_REG2__p1_rts__SHIFT 0x19
#define VGT_DEBUG_REG2__ls_sh_id_MASK 0x4000000
#define VGT_DEBUG_REG2__ls_sh_id__SHIFT 0x1a
#define VGT_DEBUG_REG2__lsFwaveFlag_MASK 0x8000000
#define VGT_DEBUG_REG2__lsFwaveFlag__SHIFT 0x1b
#define VGT_DEBUG_REG2__lsWaveSendFlush_MASK 0x10000000
#define VGT_DEBUG_REG2__lsWaveSendFlush__SHIFT 0x1c
#define VGT_DEBUG_REG2__SPARE_MASK 0xe0000000
#define VGT_DEBUG_REG2__SPARE__SHIFT 0x1d
#define VGT_DEBUG_REG3__lsTgRelInd_MASK 0xfff
#define VGT_DEBUG_REG3__lsTgRelInd__SHIFT 0x0
#define VGT_DEBUG_REG3__lsWaveRelInd_MASK 0x3f000
#define VGT_DEBUG_REG3__lsWaveRelInd__SHIFT 0xc
#define VGT_DEBUG_REG3__lsPatchCnt_MASK 0x3fc0000
#define VGT_DEBUG_REG3__lsPatchCnt__SHIFT 0x12
#define VGT_DEBUG_REG3__hsWaveRelInd_MASK 0xfc000000
#define VGT_DEBUG_REG3__hsWaveRelInd__SHIFT 0x1a
#define VGT_DEBUG_REG4__hsPatchCnt_MASK 0xff
#define VGT_DEBUG_REG4__hsPatchCnt__SHIFT 0x0
#define VGT_DEBUG_REG4__hsPrimId_15_0_MASK 0xffff00
#define VGT_DEBUG_REG4__hsPrimId_15_0__SHIFT 0x8
#define VGT_DEBUG_REG4__hsCpCnt_MASK 0x1f000000
#define VGT_DEBUG_REG4__hsCpCnt__SHIFT 0x18
#define VGT_DEBUG_REG4__hsWaveSendFlush_MASK 0x20000000
#define VGT_DEBUG_REG4__hsWaveSendFlush__SHIFT 0x1d
#define VGT_DEBUG_REG4__hsFwaveFlag_MASK 0x40000000
#define VGT_DEBUG_REG4__hsFwaveFlag__SHIFT 0x1e
#define VGT_DEBUG_REG4__SPARE_MASK 0x80000000
#define VGT_DEBUG_REG4__SPARE__SHIFT 0x1f
#define VGT_DEBUG_REG5__SPARE4_MASK 0x7
#define VGT_DEBUG_REG5__SPARE4__SHIFT 0x0
#define VGT_DEBUG_REG5__hsWaveCreditCnt_0_MASK 0xf8
#define VGT_DEBUG_REG5__hsWaveCreditCnt_0__SHIFT 0x3
#define VGT_DEBUG_REG5__SPARE3_MASK 0x700
#define VGT_DEBUG_REG5__SPARE3__SHIFT 0x8
#define VGT_DEBUG_REG5__hsVertCreditCnt_0_MASK 0xf800
#define VGT_DEBUG_REG5__hsVertCreditCnt_0__SHIFT 0xb
#define VGT_DEBUG_REG5__SPARE2_MASK 0x70000
#define VGT_DEBUG_REG5__SPARE2__SHIFT 0x10
#define VGT_DEBUG_REG5__lsWaveCreditCnt_0_MASK 0xf80000
#define VGT_DEBUG_REG5__lsWaveCreditCnt_0__SHIFT 0x13
#define VGT_DEBUG_REG5__SPARE1_MASK 0x7000000
#define VGT_DEBUG_REG5__SPARE1__SHIFT 0x18
#define VGT_DEBUG_REG5__lsVertCreditCnt_0_MASK 0xf8000000
#define VGT_DEBUG_REG5__lsVertCreditCnt_0__SHIFT 0x1b
#define VGT_DEBUG_REG6__debug_BASE_MASK 0xffff
#define VGT_DEBUG_REG6__debug_BASE__SHIFT 0x0
#define VGT_DEBUG_REG6__debug_SIZE_MASK 0xffff0000
#define VGT_DEBUG_REG6__debug_SIZE__SHIFT 0x10
#define VGT_DEBUG_REG7__debug_tfmmFifoEmpty_MASK 0x1
#define VGT_DEBUG_REG7__debug_tfmmFifoEmpty__SHIFT 0x0
#define VGT_DEBUG_REG7__debug_tfmmFifoFull_MASK 0x2
#define VGT_DEBUG_REG7__debug_tfmmFifoFull__SHIFT 0x1
#define VGT_DEBUG_REG7__hs_pipe0_dr_MASK 0x4
#define VGT_DEBUG_REG7__hs_pipe0_dr__SHIFT 0x2
#define VGT_DEBUG_REG7__hs_pipe0_rtr_MASK 0x8
#define VGT_DEBUG_REG7__hs_pipe0_rtr__SHIFT 0x3
#define VGT_DEBUG_REG7__hs_pipe1_rtr_MASK 0x10
#define VGT_DEBUG_REG7__hs_pipe1_rtr__SHIFT 0x4
#define VGT_DEBUG_REG7__SPARE_MASK 0xffe0
#define VGT_DEBUG_REG7__SPARE__SHIFT 0x5
#define VGT_DEBUG_REG7__TF_addr_MASK 0xffff0000
#define VGT_DEBUG_REG7__TF_addr__SHIFT 0x10
#define VGT_DEBUG_REG8__rcm_busy_q_MASK 0x1
#define VGT_DEBUG_REG8__rcm_busy_q__SHIFT 0x0
#define VGT_DEBUG_REG8__rcm_noif_busy_q_MASK 0x2
#define VGT_DEBUG_REG8__rcm_noif_busy_q__SHIFT 0x1
#define VGT_DEBUG_REG8__r1_inst_rtr_MASK 0x4
#define VGT_DEBUG_REG8__r1_inst_rtr__SHIFT 0x2
#define VGT_DEBUG_REG8__spi_gsprim_fifo_busy_q_MASK 0x8
#define VGT_DEBUG_REG8__spi_gsprim_fifo_busy_q__SHIFT 0x3
#define VGT_DEBUG_REG8__spi_esvert_fifo_busy_q_MASK 0x10
#define VGT_DEBUG_REG8__spi_esvert_fifo_busy_q__SHIFT 0x4
#define VGT_DEBUG_REG8__gs_tbl_valid_r3_q_MASK 0x20
#define VGT_DEBUG_REG8__gs_tbl_valid_r3_q__SHIFT 0x5
#define VGT_DEBUG_REG8__valid_r0_q_MASK 0x40
#define VGT_DEBUG_REG8__valid_r0_q__SHIFT 0x6
#define VGT_DEBUG_REG8__valid_r1_q_MASK 0x80
#define VGT_DEBUG_REG8__valid_r1_q__SHIFT 0x7
#define VGT_DEBUG_REG8__valid_r2_MASK 0x100
#define VGT_DEBUG_REG8__valid_r2__SHIFT 0x8
#define VGT_DEBUG_REG8__valid_r2_q_MASK 0x200
#define VGT_DEBUG_REG8__valid_r2_q__SHIFT 0x9
#define VGT_DEBUG_REG8__r0_rtr_MASK 0x400
#define VGT_DEBUG_REG8__r0_rtr__SHIFT 0xa
#define VGT_DEBUG_REG8__r1_rtr_MASK 0x800
#define VGT_DEBUG_REG8__r1_rtr__SHIFT 0xb
#define VGT_DEBUG_REG8__r2_indx_rtr_MASK 0x1000
#define VGT_DEBUG_REG8__r2_indx_rtr__SHIFT 0xc
#define VGT_DEBUG_REG8__r2_rtr_MASK 0x2000
#define VGT_DEBUG_REG8__r2_rtr__SHIFT 0xd
#define VGT_DEBUG_REG8__es_gs_rtr_MASK 0x4000
#define VGT_DEBUG_REG8__es_gs_rtr__SHIFT 0xe
#define VGT_DEBUG_REG8__gs_event_fifo_rtr_MASK 0x8000
#define VGT_DEBUG_REG8__gs_event_fifo_rtr__SHIFT 0xf
#define VGT_DEBUG_REG8__tm_rcm_gs_event_rtr_MASK 0x10000
#define VGT_DEBUG_REG8__tm_rcm_gs_event_rtr__SHIFT 0x10
#define VGT_DEBUG_REG8__gs_tbl_r3_rtr_MASK 0x20000
#define VGT_DEBUG_REG8__gs_tbl_r3_rtr__SHIFT 0x11
#define VGT_DEBUG_REG8__prim_skid_fifo_empty_MASK 0x40000
#define VGT_DEBUG_REG8__prim_skid_fifo_empty__SHIFT 0x12
#define VGT_DEBUG_REG8__VGT_SPI_gsprim_rtr_q_MASK 0x80000
#define VGT_DEBUG_REG8__VGT_SPI_gsprim_rtr_q__SHIFT 0x13
#define VGT_DEBUG_REG8__tm_rcm_gs_tbl_rtr_MASK 0x100000
#define VGT_DEBUG_REG8__tm_rcm_gs_tbl_rtr__SHIFT 0x14
#define VGT_DEBUG_REG8__tm_rcm_es_tbl_rtr_MASK 0x200000
#define VGT_DEBUG_REG8__tm_rcm_es_tbl_rtr__SHIFT 0x15
#define VGT_DEBUG_REG8__VGT_SPI_esvert_rtr_q_MASK 0x400000
#define VGT_DEBUG_REG8__VGT_SPI_esvert_rtr_q__SHIFT 0x16
#define VGT_DEBUG_REG8__r2_no_bp_rtr_MASK 0x800000
#define VGT_DEBUG_REG8__r2_no_bp_rtr__SHIFT 0x17
#define VGT_DEBUG_REG8__hold_for_es_flush_MASK 0x1000000
#define VGT_DEBUG_REG8__hold_for_es_flush__SHIFT 0x18
#define VGT_DEBUG_REG8__gs_event_fifo_empty_MASK 0x2000000
#define VGT_DEBUG_REG8__gs_event_fifo_empty__SHIFT 0x19
#define VGT_DEBUG_REG8__gsprim_buff_empty_q_MASK 0x4000000
#define VGT_DEBUG_REG8__gsprim_buff_empty_q__SHIFT 0x1a
#define VGT_DEBUG_REG8__gsprim_buff_full_q_MASK 0x8000000
#define VGT_DEBUG_REG8__gsprim_buff_full_q__SHIFT 0x1b
#define VGT_DEBUG_REG8__te_prim_fifo_empty_MASK 0x10000000
#define VGT_DEBUG_REG8__te_prim_fifo_empty__SHIFT 0x1c
#define VGT_DEBUG_REG8__te_prim_fifo_full_MASK 0x20000000
#define VGT_DEBUG_REG8__te_prim_fifo_full__SHIFT 0x1d
#define VGT_DEBUG_REG8__te_vert_fifo_empty_MASK 0x40000000
#define VGT_DEBUG_REG8__te_vert_fifo_empty__SHIFT 0x1e
#define VGT_DEBUG_REG8__te_vert_fifo_full_MASK 0x80000000
#define VGT_DEBUG_REG8__te_vert_fifo_full__SHIFT 0x1f
#define VGT_DEBUG_REG9__indices_to_send_r2_q_MASK 0x3
#define VGT_DEBUG_REG9__indices_to_send_r2_q__SHIFT 0x0
#define VGT_DEBUG_REG9__valid_indices_r3_MASK 0x4
#define VGT_DEBUG_REG9__valid_indices_r3__SHIFT 0x2
#define VGT_DEBUG_REG9__gs_eov_r3_MASK 0x8
#define VGT_DEBUG_REG9__gs_eov_r3__SHIFT 0x3
#define VGT_DEBUG_REG9__eop_indx_r3_MASK 0x10
#define VGT_DEBUG_REG9__eop_indx_r3__SHIFT 0x4
#define VGT_DEBUG_REG9__eop_prim_r3_MASK 0x20
#define VGT_DEBUG_REG9__eop_prim_r3__SHIFT 0x5
#define VGT_DEBUG_REG9__es_eov_r3_MASK 0x40
#define VGT_DEBUG_REG9__es_eov_r3__SHIFT 0x6
#define VGT_DEBUG_REG9__es_tbl_state_r3_q_0_MASK 0x80
#define VGT_DEBUG_REG9__es_tbl_state_r3_q_0__SHIFT 0x7
#define VGT_DEBUG_REG9__pending_es_send_r3_q_MASK 0x100
#define VGT_DEBUG_REG9__pending_es_send_r3_q__SHIFT 0x8
#define VGT_DEBUG_REG9__pending_es_flush_r3_MASK 0x200
#define VGT_DEBUG_REG9__pending_es_flush_r3__SHIFT 0x9
#define VGT_DEBUG_REG9__gs_tbl_num_es_per_gs_r3_q_not_0_MASK 0x400
#define VGT_DEBUG_REG9__gs_tbl_num_es_per_gs_r3_q_not_0__SHIFT 0xa
#define VGT_DEBUG_REG9__gs_tbl_prim_cnt_r3_q_MASK 0x3f800
#define VGT_DEBUG_REG9__gs_tbl_prim_cnt_r3_q__SHIFT 0xb
#define VGT_DEBUG_REG9__gs_tbl_eop_r3_q_MASK 0x40000
#define VGT_DEBUG_REG9__gs_tbl_eop_r3_q__SHIFT 0x12
#define VGT_DEBUG_REG9__gs_tbl_state_r3_q_MASK 0x380000
#define VGT_DEBUG_REG9__gs_tbl_state_r3_q__SHIFT 0x13
#define VGT_DEBUG_REG9__gs_pending_state_r3_q_MASK 0x400000
#define VGT_DEBUG_REG9__gs_pending_state_r3_q__SHIFT 0x16
#define VGT_DEBUG_REG9__invalidate_rb_roll_over_q_MASK 0x800000
#define VGT_DEBUG_REG9__invalidate_rb_roll_over_q__SHIFT 0x17
#define VGT_DEBUG_REG9__gs_instancing_state_q_MASK 0x1000000
#define VGT_DEBUG_REG9__gs_instancing_state_q__SHIFT 0x18
#define VGT_DEBUG_REG9__es_per_gs_vert_cnt_r3_q_not_0_MASK 0x2000000
#define VGT_DEBUG_REG9__es_per_gs_vert_cnt_r3_q_not_0__SHIFT 0x19
#define VGT_DEBUG_REG9__gs_prim_per_es_ctr_r3_q_not_0_MASK 0x4000000
#define VGT_DEBUG_REG9__gs_prim_per_es_ctr_r3_q_not_0__SHIFT 0x1a
#define VGT_DEBUG_REG9__pre_r0_rtr_MASK 0x8000000
#define VGT_DEBUG_REG9__pre_r0_rtr__SHIFT 0x1b
#define VGT_DEBUG_REG9__valid_r3_q_MASK 0x10000000
#define VGT_DEBUG_REG9__valid_r3_q__SHIFT 0x1c
#define VGT_DEBUG_REG9__valid_pre_r0_q_MASK 0x20000000
#define VGT_DEBUG_REG9__valid_pre_r0_q__SHIFT 0x1d
#define VGT_DEBUG_REG9__SPARE0_MASK 0x40000000
#define VGT_DEBUG_REG9__SPARE0__SHIFT 0x1e
#define VGT_DEBUG_REG9__off_chip_hs_r2_q_MASK 0x80000000
#define VGT_DEBUG_REG9__off_chip_hs_r2_q__SHIFT 0x1f
#define VGT_DEBUG_REG10__index_buffer_depth_r1_q_MASK 0x1f
#define VGT_DEBUG_REG10__index_buffer_depth_r1_q__SHIFT 0x0
#define VGT_DEBUG_REG10__eopg_r2_q_MASK 0x20
#define VGT_DEBUG_REG10__eopg_r2_q__SHIFT 0x5
#define VGT_DEBUG_REG10__eotg_r2_q_MASK 0x40
#define VGT_DEBUG_REG10__eotg_r2_q__SHIFT 0x6
#define VGT_DEBUG_REG10__onchip_gs_en_r0_q_MASK 0x180
#define VGT_DEBUG_REG10__onchip_gs_en_r0_q__SHIFT 0x7
#define VGT_DEBUG_REG10__SPARE2_MASK 0x600
#define VGT_DEBUG_REG10__SPARE2__SHIFT 0x9
#define VGT_DEBUG_REG10__rcm_mem_gsprim_re_qq_MASK 0x800
#define VGT_DEBUG_REG10__rcm_mem_gsprim_re_qq__SHIFT 0xb
#define VGT_DEBUG_REG10__rcm_mem_gsprim_re_q_MASK 0x1000
#define VGT_DEBUG_REG10__rcm_mem_gsprim_re_q__SHIFT 0xc
#define VGT_DEBUG_REG10__gs_rb_space_avail_r3_q_9_0_MASK 0x7fe000
#define VGT_DEBUG_REG10__gs_rb_space_avail_r3_q_9_0__SHIFT 0xd
#define VGT_DEBUG_REG10__es_rb_space_avail_r2_q_8_0_MASK 0xff800000
#define VGT_DEBUG_REG10__es_rb_space_avail_r2_q_8_0__SHIFT 0x17
#define VGT_DEBUG_REG11__tm_busy_q_MASK 0x1
#define VGT_DEBUG_REG11__tm_busy_q__SHIFT 0x0
#define VGT_DEBUG_REG11__tm_noif_busy_q_MASK 0x2
#define VGT_DEBUG_REG11__tm_noif_busy_q__SHIFT 0x1
#define VGT_DEBUG_REG11__tm_out_busy_q_MASK 0x4
#define VGT_DEBUG_REG11__tm_out_busy_q__SHIFT 0x2
#define VGT_DEBUG_REG11__es_rb_dealloc_fifo_busy_MASK 0x8
#define VGT_DEBUG_REG11__es_rb_dealloc_fifo_busy__SHIFT 0x3
#define VGT_DEBUG_REG11__vs_dealloc_tbl_busy_MASK 0x10
#define VGT_DEBUG_REG11__vs_dealloc_tbl_busy__SHIFT 0x4
#define VGT_DEBUG_REG11__SPARE1_MASK 0x20
#define VGT_DEBUG_REG11__SPARE1__SHIFT 0x5
#define VGT_DEBUG_REG11__spi_gsthread_fifo_busy_MASK 0x40
#define VGT_DEBUG_REG11__spi_gsthread_fifo_busy__SHIFT 0x6
#define VGT_DEBUG_REG11__spi_esthread_fifo_busy_MASK 0x80
#define VGT_DEBUG_REG11__spi_esthread_fifo_busy__SHIFT 0x7
#define VGT_DEBUG_REG11__hold_eswave_MASK 0x100
#define VGT_DEBUG_REG11__hold_eswave__SHIFT 0x8
#define VGT_DEBUG_REG11__es_rb_roll_over_r3_MASK 0x200
#define VGT_DEBUG_REG11__es_rb_roll_over_r3__SHIFT 0x9
#define VGT_DEBUG_REG11__counters_busy_r0_MASK 0x400
#define VGT_DEBUG_REG11__counters_busy_r0__SHIFT 0xa
#define VGT_DEBUG_REG11__counters_avail_r0_MASK 0x800
#define VGT_DEBUG_REG11__counters_avail_r0__SHIFT 0xb
#define VGT_DEBUG_REG11__counters_available_r0_MASK 0x1000
#define VGT_DEBUG_REG11__counters_available_r0__SHIFT 0xc
#define VGT_DEBUG_REG11__vs_event_fifo_rtr_MASK 0x2000
#define VGT_DEBUG_REG11__vs_event_fifo_rtr__SHIFT 0xd
#define VGT_DEBUG_REG11__VGT_SPI_gsthread_rtr_q_MASK 0x4000
#define VGT_DEBUG_REG11__VGT_SPI_gsthread_rtr_q__SHIFT 0xe
#define VGT_DEBUG_REG11__VGT_SPI_esthread_rtr_q_MASK 0x8000
#define VGT_DEBUG_REG11__VGT_SPI_esthread_rtr_q__SHIFT 0xf
#define VGT_DEBUG_REG11__gs_issue_rtr_MASK 0x10000
#define VGT_DEBUG_REG11__gs_issue_rtr__SHIFT 0x10
#define VGT_DEBUG_REG11__tm_pt_event_rtr_MASK 0x20000
#define VGT_DEBUG_REG11__tm_pt_event_rtr__SHIFT 0x11
#define VGT_DEBUG_REG11__SPARE0_MASK 0x40000
#define VGT_DEBUG_REG11__SPARE0__SHIFT 0x12
#define VGT_DEBUG_REG11__gs_r0_rtr_MASK 0x80000
#define VGT_DEBUG_REG11__gs_r0_rtr__SHIFT 0x13
#define VGT_DEBUG_REG11__es_r0_rtr_MASK 0x100000
#define VGT_DEBUG_REG11__es_r0_rtr__SHIFT 0x14
#define VGT_DEBUG_REG11__gog_tm_vs_event_rtr_MASK 0x200000
#define VGT_DEBUG_REG11__gog_tm_vs_event_rtr__SHIFT 0x15
#define VGT_DEBUG_REG11__tm_rcm_gs_event_rtr_MASK 0x400000
#define VGT_DEBUG_REG11__tm_rcm_gs_event_rtr__SHIFT 0x16
#define VGT_DEBUG_REG11__tm_rcm_gs_tbl_rtr_MASK 0x800000
#define VGT_DEBUG_REG11__tm_rcm_gs_tbl_rtr__SHIFT 0x17
#define VGT_DEBUG_REG11__tm_rcm_es_tbl_rtr_MASK 0x1000000
#define VGT_DEBUG_REG11__tm_rcm_es_tbl_rtr__SHIFT 0x18
#define VGT_DEBUG_REG11__vs_event_fifo_empty_MASK 0x2000000
#define VGT_DEBUG_REG11__vs_event_fifo_empty__SHIFT 0x19
#define VGT_DEBUG_REG11__vs_event_fifo_full_MASK 0x4000000
#define VGT_DEBUG_REG11__vs_event_fifo_full__SHIFT 0x1a
#define VGT_DEBUG_REG11__es_rb_dealloc_fifo_full_MASK 0x8000000
#define VGT_DEBUG_REG11__es_rb_dealloc_fifo_full__SHIFT 0x1b
#define VGT_DEBUG_REG11__vs_dealloc_tbl_full_MASK 0x10000000
#define VGT_DEBUG_REG11__vs_dealloc_tbl_full__SHIFT 0x1c
#define VGT_DEBUG_REG11__send_event_q_MASK 0x20000000
#define VGT_DEBUG_REG11__send_event_q__SHIFT 0x1d
#define VGT_DEBUG_REG11__es_tbl_empty_MASK 0x40000000
#define VGT_DEBUG_REG11__es_tbl_empty__SHIFT 0x1e
#define VGT_DEBUG_REG11__no_active_states_r0_MASK 0x80000000
#define VGT_DEBUG_REG11__no_active_states_r0__SHIFT 0x1f
#define VGT_DEBUG_REG12__gs_state0_r0_q_MASK 0x7
#define VGT_DEBUG_REG12__gs_state0_r0_q__SHIFT 0x0
#define VGT_DEBUG_REG12__gs_state1_r0_q_MASK 0x38
#define VGT_DEBUG_REG12__gs_state1_r0_q__SHIFT 0x3
#define VGT_DEBUG_REG12__gs_state2_r0_q_MASK 0x1c0
#define VGT_DEBUG_REG12__gs_state2_r0_q__SHIFT 0x6
#define VGT_DEBUG_REG12__gs_state3_r0_q_MASK 0xe00
#define VGT_DEBUG_REG12__gs_state3_r0_q__SHIFT 0x9
#define VGT_DEBUG_REG12__gs_state4_r0_q_MASK 0x7000
#define VGT_DEBUG_REG12__gs_state4_r0_q__SHIFT 0xc
#define VGT_DEBUG_REG12__gs_state5_r0_q_MASK 0x38000
#define VGT_DEBUG_REG12__gs_state5_r0_q__SHIFT 0xf
#define VGT_DEBUG_REG12__gs_state6_r0_q_MASK 0x1c0000
#define VGT_DEBUG_REG12__gs_state6_r0_q__SHIFT 0x12
#define VGT_DEBUG_REG12__gs_state7_r0_q_MASK 0xe00000
#define VGT_DEBUG_REG12__gs_state7_r0_q__SHIFT 0x15
#define VGT_DEBUG_REG12__gs_state8_r0_q_MASK 0x7000000
#define VGT_DEBUG_REG12__gs_state8_r0_q__SHIFT 0x18
#define VGT_DEBUG_REG12__gs_state9_r0_q_MASK 0x38000000
#define VGT_DEBUG_REG12__gs_state9_r0_q__SHIFT 0x1b
#define VGT_DEBUG_REG12__hold_eswave_eop_MASK 0x40000000
#define VGT_DEBUG_REG12__hold_eswave_eop__SHIFT 0x1e
#define VGT_DEBUG_REG12__SPARE0_MASK 0x80000000
#define VGT_DEBUG_REG12__SPARE0__SHIFT 0x1f
#define VGT_DEBUG_REG13__gs_state10_r0_q_MASK 0x7
#define VGT_DEBUG_REG13__gs_state10_r0_q__SHIFT 0x0
#define VGT_DEBUG_REG13__gs_state11_r0_q_MASK 0x38
#define VGT_DEBUG_REG13__gs_state11_r0_q__SHIFT 0x3
#define VGT_DEBUG_REG13__gs_state12_r0_q_MASK 0x1c0
#define VGT_DEBUG_REG13__gs_state12_r0_q__SHIFT 0x6
#define VGT_DEBUG_REG13__gs_state13_r0_q_MASK 0xe00
#define VGT_DEBUG_REG13__gs_state13_r0_q__SHIFT 0x9
#define VGT_DEBUG_REG13__gs_state14_r0_q_MASK 0x7000
#define VGT_DEBUG_REG13__gs_state14_r0_q__SHIFT 0xc
#define VGT_DEBUG_REG13__gs_state15_r0_q_MASK 0x38000
#define VGT_DEBUG_REG13__gs_state15_r0_q__SHIFT 0xf
#define VGT_DEBUG_REG13__gs_tbl_wrptr_r0_q_3_0_MASK 0x3c0000
#define VGT_DEBUG_REG13__gs_tbl_wrptr_r0_q_3_0__SHIFT 0x12
#define VGT_DEBUG_REG13__gsfetch_done_fifo_cnt_q_not_0_MASK 0x400000
#define VGT_DEBUG_REG13__gsfetch_done_fifo_cnt_q_not_0__SHIFT 0x16
#define VGT_DEBUG_REG13__gsfetch_done_cnt_q_not_0_MASK 0x800000
#define VGT_DEBUG_REG13__gsfetch_done_cnt_q_not_0__SHIFT 0x17
#define VGT_DEBUG_REG13__es_tbl_full_MASK 0x1000000
#define VGT_DEBUG_REG13__es_tbl_full__SHIFT 0x18
#define VGT_DEBUG_REG13__SPARE1_MASK 0x2000000
#define VGT_DEBUG_REG13__SPARE1__SHIFT 0x19
#define VGT_DEBUG_REG13__SPARE0_MASK 0x4000000
#define VGT_DEBUG_REG13__SPARE0__SHIFT 0x1a
#define VGT_DEBUG_REG13__active_cm_sm_r0_q_MASK 0xf8000000
#define VGT_DEBUG_REG13__active_cm_sm_r0_q__SHIFT 0x1b
#define VGT_DEBUG_REG14__SPARE3_MASK 0xf
#define VGT_DEBUG_REG14__SPARE3__SHIFT 0x0
#define VGT_DEBUG_REG14__gsfetch_done_fifo_full_MASK 0x10
#define VGT_DEBUG_REG14__gsfetch_done_fifo_full__SHIFT 0x4
#define VGT_DEBUG_REG14__gs_rb_space_avail_r0_MASK 0x20
#define VGT_DEBUG_REG14__gs_rb_space_avail_r0__SHIFT 0x5
#define VGT_DEBUG_REG14__smx_es_done_cnt_r0_q_not_0_MASK 0x40
#define VGT_DEBUG_REG14__smx_es_done_cnt_r0_q_not_0__SHIFT 0x6
#define VGT_DEBUG_REG14__SPARE8_MASK 0x180
#define VGT_DEBUG_REG14__SPARE8__SHIFT 0x7
#define VGT_DEBUG_REG14__vs_done_cnt_q_not_0_MASK 0x200
#define VGT_DEBUG_REG14__vs_done_cnt_q_not_0__SHIFT 0x9
#define VGT_DEBUG_REG14__es_flush_cnt_busy_q_MASK 0x400
#define VGT_DEBUG_REG14__es_flush_cnt_busy_q__SHIFT 0xa
#define VGT_DEBUG_REG14__gs_tbl_full_r0_MASK 0x800
#define VGT_DEBUG_REG14__gs_tbl_full_r0__SHIFT 0xb
#define VGT_DEBUG_REG14__SPARE2_MASK 0x1ff000
#define VGT_DEBUG_REG14__SPARE2__SHIFT 0xc
#define VGT_DEBUG_REG14__se1spi_gsthread_fifo_busy_MASK 0x200000
#define VGT_DEBUG_REG14__se1spi_gsthread_fifo_busy__SHIFT 0x15
#define VGT_DEBUG_REG14__SPARE_MASK 0x1c00000
#define VGT_DEBUG_REG14__SPARE__SHIFT 0x16
#define VGT_DEBUG_REG14__VGT_SE1SPI_gsthread_rtr_q_MASK 0x2000000
#define VGT_DEBUG_REG14__VGT_SE1SPI_gsthread_rtr_q__SHIFT 0x19
#define VGT_DEBUG_REG14__smx1_es_done_cnt_r0_q_not_0_MASK 0x4000000
#define VGT_DEBUG_REG14__smx1_es_done_cnt_r0_q_not_0__SHIFT 0x1a
#define VGT_DEBUG_REG14__se1spi_esthread_fifo_busy_MASK 0x8000000
#define VGT_DEBUG_REG14__se1spi_esthread_fifo_busy__SHIFT 0x1b
#define VGT_DEBUG_REG14__SPARE1_MASK 0x10000000
#define VGT_DEBUG_REG14__SPARE1__SHIFT 0x1c
#define VGT_DEBUG_REG14__gsfetch_done_se1_cnt_q_not_0_MASK 0x20000000
#define VGT_DEBUG_REG14__gsfetch_done_se1_cnt_q_not_0__SHIFT 0x1d
#define VGT_DEBUG_REG14__SPARE0_MASK 0x40000000
#define VGT_DEBUG_REG14__SPARE0__SHIFT 0x1e
#define VGT_DEBUG_REG14__VGT_SE1SPI_esthread_rtr_q_MASK 0x80000000
#define VGT_DEBUG_REG14__VGT_SE1SPI_esthread_rtr_q__SHIFT 0x1f
#define VGT_DEBUG_REG15__cm_busy_q_MASK 0x1
#define VGT_DEBUG_REG15__cm_busy_q__SHIFT 0x0
#define VGT_DEBUG_REG15__counters_busy_q_MASK 0x2
#define VGT_DEBUG_REG15__counters_busy_q__SHIFT 0x1
#define VGT_DEBUG_REG15__output_fifo_empty_MASK 0x4
#define VGT_DEBUG_REG15__output_fifo_empty__SHIFT 0x2
#define VGT_DEBUG_REG15__output_fifo_full_MASK 0x8
#define VGT_DEBUG_REG15__output_fifo_full__SHIFT 0x3
#define VGT_DEBUG_REG15__counters_full_MASK 0x10
#define VGT_DEBUG_REG15__counters_full__SHIFT 0x4
#define VGT_DEBUG_REG15__active_sm_q_MASK 0x3e0
#define VGT_DEBUG_REG15__active_sm_q__SHIFT 0x5
#define VGT_DEBUG_REG15__entry_rdptr_q_MASK 0x7c00
#define VGT_DEBUG_REG15__entry_rdptr_q__SHIFT 0xa
#define VGT_DEBUG_REG15__cntr_tbl_wrptr_q_MASK 0xf8000
#define VGT_DEBUG_REG15__cntr_tbl_wrptr_q__SHIFT 0xf
#define VGT_DEBUG_REG15__SPARE25_MASK 0x3f00000
#define VGT_DEBUG_REG15__SPARE25__SHIFT 0x14
#define VGT_DEBUG_REG15__st_cut_mode_q_MASK 0xc000000
#define VGT_DEBUG_REG15__st_cut_mode_q__SHIFT 0x1a
#define VGT_DEBUG_REG15__gs_done_array_q_not_0_MASK 0x10000000
#define VGT_DEBUG_REG15__gs_done_array_q_not_0__SHIFT 0x1c
#define VGT_DEBUG_REG15__SPARE31_MASK 0xe0000000
#define VGT_DEBUG_REG15__SPARE31__SHIFT 0x1d
#define VGT_DEBUG_REG16__gog_busy_MASK 0x1
#define VGT_DEBUG_REG16__gog_busy__SHIFT 0x0
#define VGT_DEBUG_REG16__gog_state_q_MASK 0xe
#define VGT_DEBUG_REG16__gog_state_q__SHIFT 0x1
#define VGT_DEBUG_REG16__r0_rtr_MASK 0x10
#define VGT_DEBUG_REG16__r0_rtr__SHIFT 0x4
#define VGT_DEBUG_REG16__r1_rtr_MASK 0x20
#define VGT_DEBUG_REG16__r1_rtr__SHIFT 0x5
#define VGT_DEBUG_REG16__r1_upstream_rtr_MASK 0x40
#define VGT_DEBUG_REG16__r1_upstream_rtr__SHIFT 0x6
#define VGT_DEBUG_REG16__r2_vs_tbl_rtr_MASK 0x80
#define VGT_DEBUG_REG16__r2_vs_tbl_rtr__SHIFT 0x7
#define VGT_DEBUG_REG16__r2_prim_rtr_MASK 0x100
#define VGT_DEBUG_REG16__r2_prim_rtr__SHIFT 0x8
#define VGT_DEBUG_REG16__r2_indx_rtr_MASK 0x200
#define VGT_DEBUG_REG16__r2_indx_rtr__SHIFT 0x9
#define VGT_DEBUG_REG16__r2_rtr_MASK 0x400
#define VGT_DEBUG_REG16__r2_rtr__SHIFT 0xa
#define VGT_DEBUG_REG16__gog_tm_vs_event_rtr_MASK 0x800
#define VGT_DEBUG_REG16__gog_tm_vs_event_rtr__SHIFT 0xb
#define VGT_DEBUG_REG16__r3_force_vs_tbl_we_rtr_MASK 0x1000
#define VGT_DEBUG_REG16__r3_force_vs_tbl_we_rtr__SHIFT 0xc
#define VGT_DEBUG_REG16__indx_valid_r2_q_MASK 0x2000
#define VGT_DEBUG_REG16__indx_valid_r2_q__SHIFT 0xd
#define VGT_DEBUG_REG16__prim_valid_r2_q_MASK 0x4000
#define VGT_DEBUG_REG16__prim_valid_r2_q__SHIFT 0xe
#define VGT_DEBUG_REG16__valid_r2_q_MASK 0x8000
#define VGT_DEBUG_REG16__valid_r2_q__SHIFT 0xf
#define VGT_DEBUG_REG16__prim_valid_r1_q_MASK 0x10000
#define VGT_DEBUG_REG16__prim_valid_r1_q__SHIFT 0x10
#define VGT_DEBUG_REG16__indx_valid_r1_q_MASK 0x20000
#define VGT_DEBUG_REG16__indx_valid_r1_q__SHIFT 0x11
#define VGT_DEBUG_REG16__valid_r1_q_MASK 0x40000
#define VGT_DEBUG_REG16__valid_r1_q__SHIFT 0x12
#define VGT_DEBUG_REG16__indx_valid_r0_q_MASK 0x80000
#define VGT_DEBUG_REG16__indx_valid_r0_q__SHIFT 0x13
#define VGT_DEBUG_REG16__prim_valid_r0_q_MASK 0x100000
#define VGT_DEBUG_REG16__prim_valid_r0_q__SHIFT 0x14
#define VGT_DEBUG_REG16__valid_r0_q_MASK 0x200000
#define VGT_DEBUG_REG16__valid_r0_q__SHIFT 0x15
#define VGT_DEBUG_REG16__send_event_q_MASK 0x400000
#define VGT_DEBUG_REG16__send_event_q__SHIFT 0x16
#define VGT_DEBUG_REG16__SPARE24_MASK 0x800000
#define VGT_DEBUG_REG16__SPARE24__SHIFT 0x17
#define VGT_DEBUG_REG16__vert_seen_since_sopg_r2_q_MASK 0x1000000
#define VGT_DEBUG_REG16__vert_seen_since_sopg_r2_q__SHIFT 0x18
#define VGT_DEBUG_REG16__gog_out_prim_state_sel_MASK 0xe000000
#define VGT_DEBUG_REG16__gog_out_prim_state_sel__SHIFT 0x19
#define VGT_DEBUG_REG16__multiple_streams_en_r1_q_MASK 0x10000000
#define VGT_DEBUG_REG16__multiple_streams_en_r1_q__SHIFT 0x1c
#define VGT_DEBUG_REG16__vs_vert_count_r2_q_not_0_MASK 0x20000000
#define VGT_DEBUG_REG16__vs_vert_count_r2_q_not_0__SHIFT 0x1d
#define VGT_DEBUG_REG16__num_gs_r2_q_not_0_MASK 0x40000000
#define VGT_DEBUG_REG16__num_gs_r2_q_not_0__SHIFT 0x1e
#define VGT_DEBUG_REG16__new_vs_thread_r2_MASK 0x80000000
#define VGT_DEBUG_REG16__new_vs_thread_r2__SHIFT 0x1f
#define VGT_DEBUG_REG17__gog_out_prim_rel_indx2_5_0_MASK 0x3f
#define VGT_DEBUG_REG17__gog_out_prim_rel_indx2_5_0__SHIFT 0x0
#define VGT_DEBUG_REG17__gog_out_prim_rel_indx1_5_0_MASK 0xfc0
#define VGT_DEBUG_REG17__gog_out_prim_rel_indx1_5_0__SHIFT 0x6
#define VGT_DEBUG_REG17__gog_out_prim_rel_indx0_5_0_MASK 0x3f000
#define VGT_DEBUG_REG17__gog_out_prim_rel_indx0_5_0__SHIFT 0xc
#define VGT_DEBUG_REG17__gog_out_indx_13_0_MASK 0xfffc0000
#define VGT_DEBUG_REG17__gog_out_indx_13_0__SHIFT 0x12
#define VGT_DEBUG_REG18__grp_vr_valid_MASK 0x1
#define VGT_DEBUG_REG18__grp_vr_valid__SHIFT 0x0
#define VGT_DEBUG_REG18__pipe0_dr_MASK 0x2
#define VGT_DEBUG_REG18__pipe0_dr__SHIFT 0x1
#define VGT_DEBUG_REG18__pipe1_dr_MASK 0x4
#define VGT_DEBUG_REG18__pipe1_dr__SHIFT 0x2
#define VGT_DEBUG_REG18__vr_grp_read_MASK 0x8
#define VGT_DEBUG_REG18__vr_grp_read__SHIFT 0x3
#define VGT_DEBUG_REG18__pipe0_rtr_MASK 0x10
#define VGT_DEBUG_REG18__pipe0_rtr__SHIFT 0x4
#define VGT_DEBUG_REG18__pipe1_rtr_MASK 0x20
#define VGT_DEBUG_REG18__pipe1_rtr__SHIFT 0x5
#define VGT_DEBUG_REG18__out_vr_indx_read_MASK 0x40
#define VGT_DEBUG_REG18__out_vr_indx_read__SHIFT 0x6
#define VGT_DEBUG_REG18__out_vr_prim_read_MASK 0x80
#define VGT_DEBUG_REG18__out_vr_prim_read__SHIFT 0x7
#define VGT_DEBUG_REG18__indices_to_send_q_MASK 0x700
#define VGT_DEBUG_REG18__indices_to_send_q__SHIFT 0x8
#define VGT_DEBUG_REG18__valid_indices_MASK 0x800
#define VGT_DEBUG_REG18__valid_indices__SHIFT 0xb
#define VGT_DEBUG_REG18__last_indx_of_prim_MASK 0x1000
#define VGT_DEBUG_REG18__last_indx_of_prim__SHIFT 0xc
#define VGT_DEBUG_REG18__indx0_new_d_MASK 0x2000
#define VGT_DEBUG_REG18__indx0_new_d__SHIFT 0xd
#define VGT_DEBUG_REG18__indx1_new_d_MASK 0x4000
#define VGT_DEBUG_REG18__indx1_new_d__SHIFT 0xe
#define VGT_DEBUG_REG18__indx2_new_d_MASK 0x8000
#define VGT_DEBUG_REG18__indx2_new_d__SHIFT 0xf
#define VGT_DEBUG_REG18__indx2_hit_d_MASK 0x10000
#define VGT_DEBUG_REG18__indx2_hit_d__SHIFT 0x10
#define VGT_DEBUG_REG18__indx1_hit_d_MASK 0x20000
#define VGT_DEBUG_REG18__indx1_hit_d__SHIFT 0x11
#define VGT_DEBUG_REG18__indx0_hit_d_MASK 0x40000
#define VGT_DEBUG_REG18__indx0_hit_d__SHIFT 0x12
#define VGT_DEBUG_REG18__st_vertex_reuse_off_r0_q_MASK 0x80000
#define VGT_DEBUG_REG18__st_vertex_reuse_off_r0_q__SHIFT 0x13
#define VGT_DEBUG_REG18__last_group_of_instance_r0_q_MASK 0x100000
#define VGT_DEBUG_REG18__last_group_of_instance_r0_q__SHIFT 0x14
#define VGT_DEBUG_REG18__null_primitive_r0_q_MASK 0x200000
#define VGT_DEBUG_REG18__null_primitive_r0_q__SHIFT 0x15
#define VGT_DEBUG_REG18__eop_r0_q_MASK 0x400000
#define VGT_DEBUG_REG18__eop_r0_q__SHIFT 0x16
#define VGT_DEBUG_REG18__eject_vtx_vect_r1_d_MASK 0x800000
#define VGT_DEBUG_REG18__eject_vtx_vect_r1_d__SHIFT 0x17
#define VGT_DEBUG_REG18__sub_prim_type_r0_q_MASK 0x7000000
#define VGT_DEBUG_REG18__sub_prim_type_r0_q__SHIFT 0x18
#define VGT_DEBUG_REG18__gs_scenario_a_r0_q_MASK 0x8000000
#define VGT_DEBUG_REG18__gs_scenario_a_r0_q__SHIFT 0x1b
#define VGT_DEBUG_REG18__gs_scenario_b_r0_q_MASK 0x10000000
#define VGT_DEBUG_REG18__gs_scenario_b_r0_q__SHIFT 0x1c
#define VGT_DEBUG_REG18__components_valid_r0_q_MASK 0xe0000000
#define VGT_DEBUG_REG18__components_valid_r0_q__SHIFT 0x1d
#define VGT_DEBUG_REG19__separate_out_busy_q_MASK 0x1
#define VGT_DEBUG_REG19__separate_out_busy_q__SHIFT 0x0
#define VGT_DEBUG_REG19__separate_out_indx_busy_q_MASK 0x2
#define VGT_DEBUG_REG19__separate_out_indx_busy_q__SHIFT 0x1
#define VGT_DEBUG_REG19__prim_buffer_empty_MASK 0x4
#define VGT_DEBUG_REG19__prim_buffer_empty__SHIFT 0x2
#define VGT_DEBUG_REG19__prim_buffer_full_MASK 0x8
#define VGT_DEBUG_REG19__prim_buffer_full__SHIFT 0x3
#define VGT_DEBUG_REG19__pa_clips_fifo_busy_q_MASK 0x10
#define VGT_DEBUG_REG19__pa_clips_fifo_busy_q__SHIFT 0x4
#define VGT_DEBUG_REG19__pa_clipp_fifo_busy_q_MASK 0x20
#define VGT_DEBUG_REG19__pa_clipp_fifo_busy_q__SHIFT 0x5
#define VGT_DEBUG_REG19__VGT_PA_clips_rtr_q_MASK 0x40
#define VGT_DEBUG_REG19__VGT_PA_clips_rtr_q__SHIFT 0x6
#define VGT_DEBUG_REG19__VGT_PA_clipp_rtr_q_MASK 0x80
#define VGT_DEBUG_REG19__VGT_PA_clipp_rtr_q__SHIFT 0x7
#define VGT_DEBUG_REG19__spi_vsthread_fifo_busy_q_MASK 0x100
#define VGT_DEBUG_REG19__spi_vsthread_fifo_busy_q__SHIFT 0x8
#define VGT_DEBUG_REG19__spi_vsvert_fifo_busy_q_MASK 0x200
#define VGT_DEBUG_REG19__spi_vsvert_fifo_busy_q__SHIFT 0x9
#define VGT_DEBUG_REG19__pa_clipv_fifo_busy_q_MASK 0x400
#define VGT_DEBUG_REG19__pa_clipv_fifo_busy_q__SHIFT 0xa
#define VGT_DEBUG_REG19__hold_prim_MASK 0x800
#define VGT_DEBUG_REG19__hold_prim__SHIFT 0xb
#define VGT_DEBUG_REG19__VGT_SPI_vsthread_rtr_q_MASK 0x1000
#define VGT_DEBUG_REG19__VGT_SPI_vsthread_rtr_q__SHIFT 0xc
#define VGT_DEBUG_REG19__VGT_SPI_vsvert_rtr_q_MASK 0x2000
#define VGT_DEBUG_REG19__VGT_SPI_vsvert_rtr_q__SHIFT 0xd
#define VGT_DEBUG_REG19__VGT_PA_clipv_rtr_q_MASK 0x4000
#define VGT_DEBUG_REG19__VGT_PA_clipv_rtr_q__SHIFT 0xe
#define VGT_DEBUG_REG19__new_packet_q_MASK 0x8000
#define VGT_DEBUG_REG19__new_packet_q__SHIFT 0xf
#define VGT_DEBUG_REG19__buffered_prim_event_MASK 0x10000
#define VGT_DEBUG_REG19__buffered_prim_event__SHIFT 0x10
#define VGT_DEBUG_REG19__buffered_prim_null_primitive_MASK 0x20000
#define VGT_DEBUG_REG19__buffered_prim_null_primitive__SHIFT 0x11
#define VGT_DEBUG_REG19__buffered_prim_eop_MASK 0x40000
#define VGT_DEBUG_REG19__buffered_prim_eop__SHIFT 0x12
#define VGT_DEBUG_REG19__buffered_prim_eject_vtx_vect_MASK 0x80000
#define VGT_DEBUG_REG19__buffered_prim_eject_vtx_vect__SHIFT 0x13
#define VGT_DEBUG_REG19__buffered_prim_type_event_MASK 0x3f00000
#define VGT_DEBUG_REG19__buffered_prim_type_event__SHIFT 0x14
#define VGT_DEBUG_REG19__VGT_SE1SPI_vswave_rtr_q_MASK 0x4000000
#define VGT_DEBUG_REG19__VGT_SE1SPI_vswave_rtr_q__SHIFT 0x1a
#define VGT_DEBUG_REG19__VGT_SE1SPI_vsvert_rtr_q_MASK 0x8000000
#define VGT_DEBUG_REG19__VGT_SE1SPI_vsvert_rtr_q__SHIFT 0x1b
#define VGT_DEBUG_REG19__num_new_unique_rel_indx_MASK 0x30000000
#define VGT_DEBUG_REG19__num_new_unique_rel_indx__SHIFT 0x1c
#define VGT_DEBUG_REG19__null_terminate_vtx_vector_MASK 0x40000000
#define VGT_DEBUG_REG19__null_terminate_vtx_vector__SHIFT 0x1e
#define VGT_DEBUG_REG19__filter_event_MASK 0x80000000
#define VGT_DEBUG_REG19__filter_event__SHIFT 0x1f
#define VGT_DEBUG_REG20__dbg_VGT_SPI_vsthread_sovertexindex_MASK 0xffff
#define VGT_DEBUG_REG20__dbg_VGT_SPI_vsthread_sovertexindex__SHIFT 0x0
#define VGT_DEBUG_REG20__dbg_VGT_SPI_vsthread_sovertexcount_not_0_MASK 0x10000
#define VGT_DEBUG_REG20__dbg_VGT_SPI_vsthread_sovertexcount_not_0__SHIFT 0x10
#define VGT_DEBUG_REG20__SPARE17_MASK 0x20000
#define VGT_DEBUG_REG20__SPARE17__SHIFT 0x11
#define VGT_DEBUG_REG20__alloc_counter_q_MASK 0x3c0000
#define VGT_DEBUG_REG20__alloc_counter_q__SHIFT 0x12
#define VGT_DEBUG_REG20__curr_dealloc_distance_q_MASK 0x1fc00000
#define VGT_DEBUG_REG20__curr_dealloc_distance_q__SHIFT 0x16
#define VGT_DEBUG_REG20__new_allocate_q_MASK 0x20000000
#define VGT_DEBUG_REG20__new_allocate_q__SHIFT 0x1d
#define VGT_DEBUG_REG20__curr_slot_in_vtx_vect_q_not_0_MASK 0x40000000
#define VGT_DEBUG_REG20__curr_slot_in_vtx_vect_q_not_0__SHIFT 0x1e
#define VGT_DEBUG_REG20__int_vtx_counter_q_not_0_MASK 0x80000000
#define VGT_DEBUG_REG20__int_vtx_counter_q_not_0__SHIFT 0x1f
#define VGT_DEBUG_REG21__out_indx_fifo_empty_MASK 0x1
#define VGT_DEBUG_REG21__out_indx_fifo_empty__SHIFT 0x0
#define VGT_DEBUG_REG21__indx_side_fifo_empty_MASK 0x2
#define VGT_DEBUG_REG21__indx_side_fifo_empty__SHIFT 0x1
#define VGT_DEBUG_REG21__pipe0_dr_MASK 0x4
#define VGT_DEBUG_REG21__pipe0_dr__SHIFT 0x2
#define VGT_DEBUG_REG21__pipe1_dr_MASK 0x8
#define VGT_DEBUG_REG21__pipe1_dr__SHIFT 0x3
#define VGT_DEBUG_REG21__pipe2_dr_MASK 0x10
#define VGT_DEBUG_REG21__pipe2_dr__SHIFT 0x4
#define VGT_DEBUG_REG21__vsthread_buff_empty_MASK 0x20
#define VGT_DEBUG_REG21__vsthread_buff_empty__SHIFT 0x5
#define VGT_DEBUG_REG21__out_indx_fifo_full_MASK 0x40
#define VGT_DEBUG_REG21__out_indx_fifo_full__SHIFT 0x6
#define VGT_DEBUG_REG21__indx_side_fifo_full_MASK 0x80
#define VGT_DEBUG_REG21__indx_side_fifo_full__SHIFT 0x7
#define VGT_DEBUG_REG21__pipe0_rtr_MASK 0x100
#define VGT_DEBUG_REG21__pipe0_rtr__SHIFT 0x8
#define VGT_DEBUG_REG21__pipe1_rtr_MASK 0x200
#define VGT_DEBUG_REG21__pipe1_rtr__SHIFT 0x9
#define VGT_DEBUG_REG21__pipe2_rtr_MASK 0x400
#define VGT_DEBUG_REG21__pipe2_rtr__SHIFT 0xa
#define VGT_DEBUG_REG21__vsthread_buff_full_MASK 0x800
#define VGT_DEBUG_REG21__vsthread_buff_full__SHIFT 0xb
#define VGT_DEBUG_REG21__interfaces_rtr_MASK 0x1000
#define VGT_DEBUG_REG21__interfaces_rtr__SHIFT 0xc
#define VGT_DEBUG_REG21__indx_count_q_not_0_MASK 0x2000
#define VGT_DEBUG_REG21__indx_count_q_not_0__SHIFT 0xd
#define VGT_DEBUG_REG21__wait_for_external_eopg_q_MASK 0x4000
#define VGT_DEBUG_REG21__wait_for_external_eopg_q__SHIFT 0xe
#define VGT_DEBUG_REG21__full_state_p1_q_MASK 0x8000
#define VGT_DEBUG_REG21__full_state_p1_q__SHIFT 0xf
#define VGT_DEBUG_REG21__indx_side_indx_valid_MASK 0x10000
#define VGT_DEBUG_REG21__indx_side_indx_valid__SHIFT 0x10
#define VGT_DEBUG_REG21__stateid_p0_q_MASK 0xe0000
#define VGT_DEBUG_REG21__stateid_p0_q__SHIFT 0x11
#define VGT_DEBUG_REG21__is_event_p0_q_MASK 0x100000
#define VGT_DEBUG_REG21__is_event_p0_q__SHIFT 0x14
#define VGT_DEBUG_REG21__lshs_dealloc_p1_MASK 0x200000
#define VGT_DEBUG_REG21__lshs_dealloc_p1__SHIFT 0x15
#define VGT_DEBUG_REG21__stream_id_r2_q_MASK 0x400000
#define VGT_DEBUG_REG21__stream_id_r2_q__SHIFT 0x16
#define VGT_DEBUG_REG21__vtx_vect_counter_q_not_0_MASK 0x800000
#define VGT_DEBUG_REG21__vtx_vect_counter_q_not_0__SHIFT 0x17
#define VGT_DEBUG_REG21__buff_full_p1_MASK 0x1000000
#define VGT_DEBUG_REG21__buff_full_p1__SHIFT 0x18
#define VGT_DEBUG_REG21__strmout_valid_p1_MASK 0x2000000
#define VGT_DEBUG_REG21__strmout_valid_p1__SHIFT 0x19
#define VGT_DEBUG_REG21__eotg_r2_q_MASK 0x4000000
#define VGT_DEBUG_REG21__eotg_r2_q__SHIFT 0x1a
#define VGT_DEBUG_REG21__null_r2_q_MASK 0x8000000
#define VGT_DEBUG_REG21__null_r2_q__SHIFT 0x1b
#define VGT_DEBUG_REG21__p0_dr_MASK 0x10000000
#define VGT_DEBUG_REG21__p0_dr__SHIFT 0x1c
#define VGT_DEBUG_REG21__p0_rtr_MASK 0x20000000
#define VGT_DEBUG_REG21__p0_rtr__SHIFT 0x1d
#define VGT_DEBUG_REG21__eopg_p0_q_MASK 0x40000000
#define VGT_DEBUG_REG21__eopg_p0_q__SHIFT 0x1e
#define VGT_DEBUG_REG21__p0_nobp_MASK 0x80000000
#define VGT_DEBUG_REG21__p0_nobp__SHIFT 0x1f
#define VGT_DEBUG_REG22__cm_state16_MASK 0x3
#define VGT_DEBUG_REG22__cm_state16__SHIFT 0x0
#define VGT_DEBUG_REG22__cm_state17_MASK 0xc
#define VGT_DEBUG_REG22__cm_state17__SHIFT 0x2
#define VGT_DEBUG_REG22__cm_state18_MASK 0x30
#define VGT_DEBUG_REG22__cm_state18__SHIFT 0x4
#define VGT_DEBUG_REG22__cm_state19_MASK 0xc0
#define VGT_DEBUG_REG22__cm_state19__SHIFT 0x6
#define VGT_DEBUG_REG22__cm_state20_MASK 0x300
#define VGT_DEBUG_REG22__cm_state20__SHIFT 0x8
#define VGT_DEBUG_REG22__cm_state21_MASK 0xc00
#define VGT_DEBUG_REG22__cm_state21__SHIFT 0xa
#define VGT_DEBUG_REG22__cm_state22_MASK 0x3000
#define VGT_DEBUG_REG22__cm_state22__SHIFT 0xc
#define VGT_DEBUG_REG22__cm_state23_MASK 0xc000
#define VGT_DEBUG_REG22__cm_state23__SHIFT 0xe
#define VGT_DEBUG_REG22__cm_state24_MASK 0x30000
#define VGT_DEBUG_REG22__cm_state24__SHIFT 0x10
#define VGT_DEBUG_REG22__cm_state25_MASK 0xc0000
#define VGT_DEBUG_REG22__cm_state25__SHIFT 0x12
#define VGT_DEBUG_REG22__cm_state26_MASK 0x300000
#define VGT_DEBUG_REG22__cm_state26__SHIFT 0x14
#define VGT_DEBUG_REG22__cm_state27_MASK 0xc00000
#define VGT_DEBUG_REG22__cm_state27__SHIFT 0x16
#define VGT_DEBUG_REG22__cm_state28_MASK 0x3000000
#define VGT_DEBUG_REG22__cm_state28__SHIFT 0x18
#define VGT_DEBUG_REG22__cm_state29_MASK 0xc000000
#define VGT_DEBUG_REG22__cm_state29__SHIFT 0x1a
#define VGT_DEBUG_REG22__cm_state30_MASK 0x30000000
#define VGT_DEBUG_REG22__cm_state30__SHIFT 0x1c
#define VGT_DEBUG_REG22__cm_state31_MASK 0xc0000000
#define VGT_DEBUG_REG22__cm_state31__SHIFT 0x1e
#define VGT_DEBUG_REG23__frmt_busy_MASK 0x1
#define VGT_DEBUG_REG23__frmt_busy__SHIFT 0x0
#define VGT_DEBUG_REG23__rcm_frmt_vert_rtr_MASK 0x2
#define VGT_DEBUG_REG23__rcm_frmt_vert_rtr__SHIFT 0x1
#define VGT_DEBUG_REG23__rcm_frmt_prim_rtr_MASK 0x4
#define VGT_DEBUG_REG23__rcm_frmt_prim_rtr__SHIFT 0x2
#define VGT_DEBUG_REG23__prim_r3_rtr_MASK 0x8
#define VGT_DEBUG_REG23__prim_r3_rtr__SHIFT 0x3
#define VGT_DEBUG_REG23__prim_r2_rtr_MASK 0x10
#define VGT_DEBUG_REG23__prim_r2_rtr__SHIFT 0x4
#define VGT_DEBUG_REG23__vert_r3_rtr_MASK 0x20
#define VGT_DEBUG_REG23__vert_r3_rtr__SHIFT 0x5
#define VGT_DEBUG_REG23__vert_r2_rtr_MASK 0x40
#define VGT_DEBUG_REG23__vert_r2_rtr__SHIFT 0x6
#define VGT_DEBUG_REG23__vert_r1_rtr_MASK 0x80
#define VGT_DEBUG_REG23__vert_r1_rtr__SHIFT 0x7
#define VGT_DEBUG_REG23__vert_r0_rtr_MASK 0x100
#define VGT_DEBUG_REG23__vert_r0_rtr__SHIFT 0x8
#define VGT_DEBUG_REG23__prim_fifo_empty_MASK 0x200
#define VGT_DEBUG_REG23__prim_fifo_empty__SHIFT 0x9
#define VGT_DEBUG_REG23__prim_fifo_full_MASK 0x400
#define VGT_DEBUG_REG23__prim_fifo_full__SHIFT 0xa
#define VGT_DEBUG_REG23__vert_dr_r2_q_MASK 0x800
#define VGT_DEBUG_REG23__vert_dr_r2_q__SHIFT 0xb
#define VGT_DEBUG_REG23__prim_dr_r2_q_MASK 0x1000
#define VGT_DEBUG_REG23__prim_dr_r2_q__SHIFT 0xc
#define VGT_DEBUG_REG23__vert_dr_r1_q_MASK 0x2000
#define VGT_DEBUG_REG23__vert_dr_r1_q__SHIFT 0xd
#define VGT_DEBUG_REG23__vert_dr_r0_q_MASK 0x4000
#define VGT_DEBUG_REG23__vert_dr_r0_q__SHIFT 0xe
#define VGT_DEBUG_REG23__new_verts_r2_q_MASK 0x18000
#define VGT_DEBUG_REG23__new_verts_r2_q__SHIFT 0xf
#define VGT_DEBUG_REG23__verts_sent_r2_q_MASK 0x1e0000
#define VGT_DEBUG_REG23__verts_sent_r2_q__SHIFT 0x11
#define VGT_DEBUG_REG23__prim_state_sel_r2_q_MASK 0xe00000
#define VGT_DEBUG_REG23__prim_state_sel_r2_q__SHIFT 0x15
#define VGT_DEBUG_REG23__SPARE_MASK 0xff000000
#define VGT_DEBUG_REG23__SPARE__SHIFT 0x18
#define VGT_DEBUG_REG24__avail_es_rb_space_r0_q_23_0_MASK 0xffffff
#define VGT_DEBUG_REG24__avail_es_rb_space_r0_q_23_0__SHIFT 0x0
#define VGT_DEBUG_REG24__dependent_st_cut_mode_q_MASK 0x3000000
#define VGT_DEBUG_REG24__dependent_st_cut_mode_q__SHIFT 0x18
#define VGT_DEBUG_REG24__SPARE31_MASK 0xfc000000
#define VGT_DEBUG_REG24__SPARE31__SHIFT 0x1a
#define VGT_DEBUG_REG25__avail_gs_rb_space_r0_q_25_0_MASK 0x3ffffff
#define VGT_DEBUG_REG25__avail_gs_rb_space_r0_q_25_0__SHIFT 0x0
#define VGT_DEBUG_REG25__active_sm_r0_q_MASK 0x3c000000
#define VGT_DEBUG_REG25__active_sm_r0_q__SHIFT 0x1a
#define VGT_DEBUG_REG25__add_gs_rb_space_r1_q_MASK 0x40000000
#define VGT_DEBUG_REG25__add_gs_rb_space_r1_q__SHIFT 0x1e
#define VGT_DEBUG_REG25__add_gs_rb_space_r0_q_MASK 0x80000000
#define VGT_DEBUG_REG25__add_gs_rb_space_r0_q__SHIFT 0x1f
#define VGT_DEBUG_REG26__cm_state0_MASK 0x3
#define VGT_DEBUG_REG26__cm_state0__SHIFT 0x0
#define VGT_DEBUG_REG26__cm_state1_MASK 0xc
#define VGT_DEBUG_REG26__cm_state1__SHIFT 0x2
#define VGT_DEBUG_REG26__cm_state2_MASK 0x30
#define VGT_DEBUG_REG26__cm_state2__SHIFT 0x4
#define VGT_DEBUG_REG26__cm_state3_MASK 0xc0
#define VGT_DEBUG_REG26__cm_state3__SHIFT 0x6
#define VGT_DEBUG_REG26__cm_state4_MASK 0x300
#define VGT_DEBUG_REG26__cm_state4__SHIFT 0x8
#define VGT_DEBUG_REG26__cm_state5_MASK 0xc00
#define VGT_DEBUG_REG26__cm_state5__SHIFT 0xa
#define VGT_DEBUG_REG26__cm_state6_MASK 0x3000
#define VGT_DEBUG_REG26__cm_state6__SHIFT 0xc
#define VGT_DEBUG_REG26__cm_state7_MASK 0xc000
#define VGT_DEBUG_REG26__cm_state7__SHIFT 0xe
#define VGT_DEBUG_REG26__cm_state8_MASK 0x30000
#define VGT_DEBUG_REG26__cm_state8__SHIFT 0x10
#define VGT_DEBUG_REG26__cm_state9_MASK 0xc0000
#define VGT_DEBUG_REG26__cm_state9__SHIFT 0x12
#define VGT_DEBUG_REG26__cm_state10_MASK 0x300000
#define VGT_DEBUG_REG26__cm_state10__SHIFT 0x14
#define VGT_DEBUG_REG26__cm_state11_MASK 0xc00000
#define VGT_DEBUG_REG26__cm_state11__SHIFT 0x16
#define VGT_DEBUG_REG26__cm_state12_MASK 0x3000000
#define VGT_DEBUG_REG26__cm_state12__SHIFT 0x18
#define VGT_DEBUG_REG26__cm_state13_MASK 0xc000000
#define VGT_DEBUG_REG26__cm_state13__SHIFT 0x1a
#define VGT_DEBUG_REG26__cm_state14_MASK 0x30000000
#define VGT_DEBUG_REG26__cm_state14__SHIFT 0x1c
#define VGT_DEBUG_REG26__cm_state15_MASK 0xc0000000
#define VGT_DEBUG_REG26__cm_state15__SHIFT 0x1e
#define VGT_DEBUG_REG27__pipe0_dr_MASK 0x1
#define VGT_DEBUG_REG27__pipe0_dr__SHIFT 0x0
#define VGT_DEBUG_REG27__gsc0_dr_MASK 0x2
#define VGT_DEBUG_REG27__gsc0_dr__SHIFT 0x1
#define VGT_DEBUG_REG27__pipe1_dr_MASK 0x4
#define VGT_DEBUG_REG27__pipe1_dr__SHIFT 0x2
#define VGT_DEBUG_REG27__tm_pt_event_rtr_MASK 0x8
#define VGT_DEBUG_REG27__tm_pt_event_rtr__SHIFT 0x3
#define VGT_DEBUG_REG27__pipe0_rtr_MASK 0x10
#define VGT_DEBUG_REG27__pipe0_rtr__SHIFT 0x4
#define VGT_DEBUG_REG27__gsc0_rtr_MASK 0x20
#define VGT_DEBUG_REG27__gsc0_rtr__SHIFT 0x5
#define VGT_DEBUG_REG27__pipe1_rtr_MASK 0x40
#define VGT_DEBUG_REG27__pipe1_rtr__SHIFT 0x6
#define VGT_DEBUG_REG27__last_indx_of_prim_p1_q_MASK 0x80
#define VGT_DEBUG_REG27__last_indx_of_prim_p1_q__SHIFT 0x7
#define VGT_DEBUG_REG27__indices_to_send_p0_q_MASK 0x300
#define VGT_DEBUG_REG27__indices_to_send_p0_q__SHIFT 0x8
#define VGT_DEBUG_REG27__event_flag_p1_q_MASK 0x400
#define VGT_DEBUG_REG27__event_flag_p1_q__SHIFT 0xa
#define VGT_DEBUG_REG27__eop_p1_q_MASK 0x800
#define VGT_DEBUG_REG27__eop_p1_q__SHIFT 0xb
#define VGT_DEBUG_REG27__gs_out_prim_type_p0_q_MASK 0x3000
#define VGT_DEBUG_REG27__gs_out_prim_type_p0_q__SHIFT 0xc
#define VGT_DEBUG_REG27__gsc_null_primitive_p0_q_MASK 0x4000
#define VGT_DEBUG_REG27__gsc_null_primitive_p0_q__SHIFT 0xe
#define VGT_DEBUG_REG27__gsc_eop_p0_q_MASK 0x8000
#define VGT_DEBUG_REG27__gsc_eop_p0_q__SHIFT 0xf
#define VGT_DEBUG_REG27__gsc_2cycle_output_MASK 0x10000
#define VGT_DEBUG_REG27__gsc_2cycle_output__SHIFT 0x10
#define VGT_DEBUG_REG27__gsc_2nd_cycle_p0_q_MASK 0x20000
#define VGT_DEBUG_REG27__gsc_2nd_cycle_p0_q__SHIFT 0x11
#define VGT_DEBUG_REG27__last_indx_of_vsprim_MASK 0x40000
#define VGT_DEBUG_REG27__last_indx_of_vsprim__SHIFT 0x12
#define VGT_DEBUG_REG27__first_vsprim_of_gsprim_p0_q_MASK 0x80000
#define VGT_DEBUG_REG27__first_vsprim_of_gsprim_p0_q__SHIFT 0x13
#define VGT_DEBUG_REG27__gsc_indx_count_p0_q_MASK 0x7ff00000
#define VGT_DEBUG_REG27__gsc_indx_count_p0_q__SHIFT 0x14
#define VGT_DEBUG_REG27__last_vsprim_of_gsprim_MASK 0x80000000
#define VGT_DEBUG_REG27__last_vsprim_of_gsprim__SHIFT 0x1f
#define VGT_DEBUG_REG28__con_state_q_MASK 0xf
#define VGT_DEBUG_REG28__con_state_q__SHIFT 0x0
#define VGT_DEBUG_REG28__second_cycle_q_MASK 0x10
#define VGT_DEBUG_REG28__second_cycle_q__SHIFT 0x4
#define VGT_DEBUG_REG28__process_tri_middle_p0_q_MASK 0x20
#define VGT_DEBUG_REG28__process_tri_middle_p0_q__SHIFT 0x5
#define VGT_DEBUG_REG28__process_tri_1st_2nd_half_p0_q_MASK 0x40
#define VGT_DEBUG_REG28__process_tri_1st_2nd_half_p0_q__SHIFT 0x6
#define VGT_DEBUG_REG28__process_tri_center_poly_p0_q_MASK 0x80
#define VGT_DEBUG_REG28__process_tri_center_poly_p0_q__SHIFT 0x7
#define VGT_DEBUG_REG28__pipe0_patch_dr_MASK 0x100
#define VGT_DEBUG_REG28__pipe0_patch_dr__SHIFT 0x8
#define VGT_DEBUG_REG28__pipe0_edge_dr_MASK 0x200
#define VGT_DEBUG_REG28__pipe0_edge_dr__SHIFT 0x9
#define VGT_DEBUG_REG28__pipe1_dr_MASK 0x400
#define VGT_DEBUG_REG28__pipe1_dr__SHIFT 0xa
#define VGT_DEBUG_REG28__pipe0_patch_rtr_MASK 0x800
#define VGT_DEBUG_REG28__pipe0_patch_rtr__SHIFT 0xb
#define VGT_DEBUG_REG28__pipe0_edge_rtr_MASK 0x1000
#define VGT_DEBUG_REG28__pipe0_edge_rtr__SHIFT 0xc
#define VGT_DEBUG_REG28__pipe1_rtr_MASK 0x2000
#define VGT_DEBUG_REG28__pipe1_rtr__SHIFT 0xd
#define VGT_DEBUG_REG28__outer_parity_p0_q_MASK 0x4000
#define VGT_DEBUG_REG28__outer_parity_p0_q__SHIFT 0xe
#define VGT_DEBUG_REG28__parallel_parity_p0_q_MASK 0x8000
#define VGT_DEBUG_REG28__parallel_parity_p0_q__SHIFT 0xf
#define VGT_DEBUG_REG28__first_ring_of_patch_p0_q_MASK 0x10000
#define VGT_DEBUG_REG28__first_ring_of_patch_p0_q__SHIFT 0x10
#define VGT_DEBUG_REG28__last_ring_of_patch_p0_q_MASK 0x20000
#define VGT_DEBUG_REG28__last_ring_of_patch_p0_q__SHIFT 0x11
#define VGT_DEBUG_REG28__last_edge_of_outer_ring_p0_q_MASK 0x40000
#define VGT_DEBUG_REG28__last_edge_of_outer_ring_p0_q__SHIFT 0x12
#define VGT_DEBUG_REG28__last_point_of_outer_ring_p1_MASK 0x80000
#define VGT_DEBUG_REG28__last_point_of_outer_ring_p1__SHIFT 0x13
#define VGT_DEBUG_REG28__last_point_of_inner_ring_p1_MASK 0x100000
#define VGT_DEBUG_REG28__last_point_of_inner_ring_p1__SHIFT 0x14
#define VGT_DEBUG_REG28__outer_edge_tf_eq_one_p0_q_MASK 0x200000
#define VGT_DEBUG_REG28__outer_edge_tf_eq_one_p0_q__SHIFT 0x15
#define VGT_DEBUG_REG28__advance_outer_point_p1_MASK 0x400000
#define VGT_DEBUG_REG28__advance_outer_point_p1__SHIFT 0x16
#define VGT_DEBUG_REG28__advance_inner_point_p1_MASK 0x800000
#define VGT_DEBUG_REG28__advance_inner_point_p1__SHIFT 0x17
#define VGT_DEBUG_REG28__next_ring_is_rect_p0_q_MASK 0x1000000
#define VGT_DEBUG_REG28__next_ring_is_rect_p0_q__SHIFT 0x18
#define VGT_DEBUG_REG28__pipe1_outer1_rtr_MASK 0x2000000
#define VGT_DEBUG_REG28__pipe1_outer1_rtr__SHIFT 0x19
#define VGT_DEBUG_REG28__pipe1_outer2_rtr_MASK 0x4000000
#define VGT_DEBUG_REG28__pipe1_outer2_rtr__SHIFT 0x1a
#define VGT_DEBUG_REG28__pipe1_inner1_rtr_MASK 0x8000000
#define VGT_DEBUG_REG28__pipe1_inner1_rtr__SHIFT 0x1b
#define VGT_DEBUG_REG28__pipe1_inner2_rtr_MASK 0x10000000
#define VGT_DEBUG_REG28__pipe1_inner2_rtr__SHIFT 0x1c
#define VGT_DEBUG_REG28__pipe1_patch_rtr_MASK 0x20000000
#define VGT_DEBUG_REG28__pipe1_patch_rtr__SHIFT 0x1d
#define VGT_DEBUG_REG28__pipe1_edge_rtr_MASK 0x40000000
#define VGT_DEBUG_REG28__pipe1_edge_rtr__SHIFT 0x1e
#define VGT_DEBUG_REG28__use_stored_inner_q_ring2_MASK 0x80000000
#define VGT_DEBUG_REG28__use_stored_inner_q_ring2__SHIFT 0x1f
#define VGT_DEBUG_REG29__con_state_q_MASK 0xf
#define VGT_DEBUG_REG29__con_state_q__SHIFT 0x0
#define VGT_DEBUG_REG29__second_cycle_q_MASK 0x10
#define VGT_DEBUG_REG29__second_cycle_q__SHIFT 0x4
#define VGT_DEBUG_REG29__process_tri_middle_p0_q_MASK 0x20
#define VGT_DEBUG_REG29__process_tri_middle_p0_q__SHIFT 0x5
#define VGT_DEBUG_REG29__process_tri_1st_2nd_half_p0_q_MASK 0x40
#define VGT_DEBUG_REG29__process_tri_1st_2nd_half_p0_q__SHIFT 0x6
#define VGT_DEBUG_REG29__process_tri_center_poly_p0_q_MASK 0x80
#define VGT_DEBUG_REG29__process_tri_center_poly_p0_q__SHIFT 0x7
#define VGT_DEBUG_REG29__pipe0_patch_dr_MASK 0x100
#define VGT_DEBUG_REG29__pipe0_patch_dr__SHIFT 0x8
#define VGT_DEBUG_REG29__pipe0_edge_dr_MASK 0x200
#define VGT_DEBUG_REG29__pipe0_edge_dr__SHIFT 0x9
#define VGT_DEBUG_REG29__pipe1_dr_MASK 0x400
#define VGT_DEBUG_REG29__pipe1_dr__SHIFT 0xa
#define VGT_DEBUG_REG29__pipe0_patch_rtr_MASK 0x800
#define VGT_DEBUG_REG29__pipe0_patch_rtr__SHIFT 0xb
#define VGT_DEBUG_REG29__pipe0_edge_rtr_MASK 0x1000
#define VGT_DEBUG_REG29__pipe0_edge_rtr__SHIFT 0xc
#define VGT_DEBUG_REG29__pipe1_rtr_MASK 0x2000
#define VGT_DEBUG_REG29__pipe1_rtr__SHIFT 0xd
#define VGT_DEBUG_REG29__outer_parity_p0_q_MASK 0x4000
#define VGT_DEBUG_REG29__outer_parity_p0_q__SHIFT 0xe
#define VGT_DEBUG_REG29__parallel_parity_p0_q_MASK 0x8000
#define VGT_DEBUG_REG29__parallel_parity_p0_q__SHIFT 0xf
#define VGT_DEBUG_REG29__first_ring_of_patch_p0_q_MASK 0x10000
#define VGT_DEBUG_REG29__first_ring_of_patch_p0_q__SHIFT 0x10
#define VGT_DEBUG_REG29__last_ring_of_patch_p0_q_MASK 0x20000
#define VGT_DEBUG_REG29__last_ring_of_patch_p0_q__SHIFT 0x11
#define VGT_DEBUG_REG29__last_edge_of_outer_ring_p0_q_MASK 0x40000
#define VGT_DEBUG_REG29__last_edge_of_outer_ring_p0_q__SHIFT 0x12
#define VGT_DEBUG_REG29__last_point_of_outer_ring_p1_MASK 0x80000
#define VGT_DEBUG_REG29__last_point_of_outer_ring_p1__SHIFT 0x13
#define VGT_DEBUG_REG29__last_point_of_inner_ring_p1_MASK 0x100000
#define VGT_DEBUG_REG29__last_point_of_inner_ring_p1__SHIFT 0x14
#define VGT_DEBUG_REG29__outer_edge_tf_eq_one_p0_q_MASK 0x200000
#define VGT_DEBUG_REG29__outer_edge_tf_eq_one_p0_q__SHIFT 0x15
#define VGT_DEBUG_REG29__advance_outer_point_p1_MASK 0x400000
#define VGT_DEBUG_REG29__advance_outer_point_p1__SHIFT 0x16
#define VGT_DEBUG_REG29__advance_inner_point_p1_MASK 0x800000
#define VGT_DEBUG_REG29__advance_inner_point_p1__SHIFT 0x17
#define VGT_DEBUG_REG29__next_ring_is_rect_p0_q_MASK 0x1000000
#define VGT_DEBUG_REG29__next_ring_is_rect_p0_q__SHIFT 0x18
#define VGT_DEBUG_REG29__pipe1_outer1_rtr_MASK 0x2000000
#define VGT_DEBUG_REG29__pipe1_outer1_rtr__SHIFT 0x19
#define VGT_DEBUG_REG29__pipe1_outer2_rtr_MASK 0x4000000
#define VGT_DEBUG_REG29__pipe1_outer2_rtr__SHIFT 0x1a
#define VGT_DEBUG_REG29__pipe1_inner1_rtr_MASK 0x8000000
#define VGT_DEBUG_REG29__pipe1_inner1_rtr__SHIFT 0x1b
#define VGT_DEBUG_REG29__pipe1_inner2_rtr_MASK 0x10000000
#define VGT_DEBUG_REG29__pipe1_inner2_rtr__SHIFT 0x1c
#define VGT_DEBUG_REG29__pipe1_patch_rtr_MASK 0x20000000
#define VGT_DEBUG_REG29__pipe1_patch_rtr__SHIFT 0x1d
#define VGT_DEBUG_REG29__pipe1_edge_rtr_MASK 0x40000000
#define VGT_DEBUG_REG29__pipe1_edge_rtr__SHIFT 0x1e
#define VGT_DEBUG_REG29__use_stored_inner_q_ring3_MASK 0x80000000
#define VGT_DEBUG_REG29__use_stored_inner_q_ring3__SHIFT 0x1f
#define VGT_DEBUG_REG31__pipe0_dr_MASK 0x1
#define VGT_DEBUG_REG31__pipe0_dr__SHIFT 0x0
#define VGT_DEBUG_REG31__pipe0_rtr_MASK 0x2
#define VGT_DEBUG_REG31__pipe0_rtr__SHIFT 0x1
#define VGT_DEBUG_REG31__pipe1_outer_dr_MASK 0x4
#define VGT_DEBUG_REG31__pipe1_outer_dr__SHIFT 0x2
#define VGT_DEBUG_REG31__pipe1_inner_dr_MASK 0x8
#define VGT_DEBUG_REG31__pipe1_inner_dr__SHIFT 0x3
#define VGT_DEBUG_REG31__pipe2_outer_dr_MASK 0x10
#define VGT_DEBUG_REG31__pipe2_outer_dr__SHIFT 0x4
#define VGT_DEBUG_REG31__pipe2_inner_dr_MASK 0x20
#define VGT_DEBUG_REG31__pipe2_inner_dr__SHIFT 0x5
#define VGT_DEBUG_REG31__pipe3_outer_dr_MASK 0x40
#define VGT_DEBUG_REG31__pipe3_outer_dr__SHIFT 0x6
#define VGT_DEBUG_REG31__pipe3_inner_dr_MASK 0x80
#define VGT_DEBUG_REG31__pipe3_inner_dr__SHIFT 0x7
#define VGT_DEBUG_REG31__pipe4_outer_dr_MASK 0x100
#define VGT_DEBUG_REG31__pipe4_outer_dr__SHIFT 0x8
#define VGT_DEBUG_REG31__pipe4_inner_dr_MASK 0x200
#define VGT_DEBUG_REG31__pipe4_inner_dr__SHIFT 0x9
#define VGT_DEBUG_REG31__pipe5_outer_dr_MASK 0x400
#define VGT_DEBUG_REG31__pipe5_outer_dr__SHIFT 0xa
#define VGT_DEBUG_REG31__pipe5_inner_dr_MASK 0x800
#define VGT_DEBUG_REG31__pipe5_inner_dr__SHIFT 0xb
#define VGT_DEBUG_REG31__pipe2_outer_rtr_MASK 0x1000
#define VGT_DEBUG_REG31__pipe2_outer_rtr__SHIFT 0xc
#define VGT_DEBUG_REG31__pipe2_inner_rtr_MASK 0x2000
#define VGT_DEBUG_REG31__pipe2_inner_rtr__SHIFT 0xd
#define VGT_DEBUG_REG31__pipe3_outer_rtr_MASK 0x4000
#define VGT_DEBUG_REG31__pipe3_outer_rtr__SHIFT 0xe
#define VGT_DEBUG_REG31__pipe3_inner_rtr_MASK 0x8000
#define VGT_DEBUG_REG31__pipe3_inner_rtr__SHIFT 0xf
#define VGT_DEBUG_REG31__pipe4_outer_rtr_MASK 0x10000
#define VGT_DEBUG_REG31__pipe4_outer_rtr__SHIFT 0x10
#define VGT_DEBUG_REG31__pipe4_inner_rtr_MASK 0x20000
#define VGT_DEBUG_REG31__pipe4_inner_rtr__SHIFT 0x11
#define VGT_DEBUG_REG31__pipe5_outer_rtr_MASK 0x40000
#define VGT_DEBUG_REG31__pipe5_outer_rtr__SHIFT 0x12
#define VGT_DEBUG_REG31__pipe5_inner_rtr_MASK 0x80000
#define VGT_DEBUG_REG31__pipe5_inner_rtr__SHIFT 0x13
#define VGT_DEBUG_REG31__pg_con_outer_point1_rts_MASK 0x100000
#define VGT_DEBUG_REG31__pg_con_outer_point1_rts__SHIFT 0x14
#define VGT_DEBUG_REG31__pg_con_outer_point2_rts_MASK 0x200000
#define VGT_DEBUG_REG31__pg_con_outer_point2_rts__SHIFT 0x15
#define VGT_DEBUG_REG31__pg_con_inner_point1_rts_MASK 0x400000
#define VGT_DEBUG_REG31__pg_con_inner_point1_rts__SHIFT 0x16
#define VGT_DEBUG_REG31__pg_con_inner_point2_rts_MASK 0x800000
#define VGT_DEBUG_REG31__pg_con_inner_point2_rts__SHIFT 0x17
#define VGT_DEBUG_REG31__pg_patch_fifo_empty_MASK 0x1000000
#define VGT_DEBUG_REG31__pg_patch_fifo_empty__SHIFT 0x18
#define VGT_DEBUG_REG31__pg_edge_fifo_empty_MASK 0x2000000
#define VGT_DEBUG_REG31__pg_edge_fifo_empty__SHIFT 0x19
#define VGT_DEBUG_REG31__pg_inner3_perp_fifo_empty_MASK 0x4000000
#define VGT_DEBUG_REG31__pg_inner3_perp_fifo_empty__SHIFT 0x1a
#define VGT_DEBUG_REG31__pg_patch_fifo_full_MASK 0x8000000
#define VGT_DEBUG_REG31__pg_patch_fifo_full__SHIFT 0x1b
#define VGT_DEBUG_REG31__pg_edge_fifo_full_MASK 0x10000000
#define VGT_DEBUG_REG31__pg_edge_fifo_full__SHIFT 0x1c
#define VGT_DEBUG_REG31__pg_inner_perp_fifo_full_MASK 0x20000000
#define VGT_DEBUG_REG31__pg_inner_perp_fifo_full__SHIFT 0x1d
#define VGT_DEBUG_REG31__outer_ring_done_q_MASK 0x40000000
#define VGT_DEBUG_REG31__outer_ring_done_q__SHIFT 0x1e
#define VGT_DEBUG_REG31__inner_ring_done_q_MASK 0x80000000
#define VGT_DEBUG_REG31__inner_ring_done_q__SHIFT 0x1f
#define VGT_DEBUG_REG32__first_ring_of_patch_MASK 0x1
#define VGT_DEBUG_REG32__first_ring_of_patch__SHIFT 0x0
#define VGT_DEBUG_REG32__last_ring_of_patch_MASK 0x2
#define VGT_DEBUG_REG32__last_ring_of_patch__SHIFT 0x1
#define VGT_DEBUG_REG32__last_edge_of_outer_ring_MASK 0x4
#define VGT_DEBUG_REG32__last_edge_of_outer_ring__SHIFT 0x2
#define VGT_DEBUG_REG32__last_point_of_outer_edge_MASK 0x8
#define VGT_DEBUG_REG32__last_point_of_outer_edge__SHIFT 0x3
#define VGT_DEBUG_REG32__last_edge_of_inner_ring_MASK 0x10
#define VGT_DEBUG_REG32__last_edge_of_inner_ring__SHIFT 0x4
#define VGT_DEBUG_REG32__last_point_of_inner_edge_MASK 0x20
#define VGT_DEBUG_REG32__last_point_of_inner_edge__SHIFT 0x5
#define VGT_DEBUG_REG32__last_patch_of_tg_p0_q_MASK 0x40
#define VGT_DEBUG_REG32__last_patch_of_tg_p0_q__SHIFT 0x6
#define VGT_DEBUG_REG32__event_null_special_p0_q_MASK 0x80
#define VGT_DEBUG_REG32__event_null_special_p0_q__SHIFT 0x7
#define VGT_DEBUG_REG32__event_flag_p5_q_MASK 0x100
#define VGT_DEBUG_REG32__event_flag_p5_q__SHIFT 0x8
#define VGT_DEBUG_REG32__first_point_of_patch_p5_q_MASK 0x200
#define VGT_DEBUG_REG32__first_point_of_patch_p5_q__SHIFT 0x9
#define VGT_DEBUG_REG32__first_point_of_edge_p5_q_MASK 0x400
#define VGT_DEBUG_REG32__first_point_of_edge_p5_q__SHIFT 0xa
#define VGT_DEBUG_REG32__last_patch_of_tg_p5_q_MASK 0x800
#define VGT_DEBUG_REG32__last_patch_of_tg_p5_q__SHIFT 0xb
#define VGT_DEBUG_REG32__tess_topology_p5_q_MASK 0x3000
#define VGT_DEBUG_REG32__tess_topology_p5_q__SHIFT 0xc
#define VGT_DEBUG_REG32__pipe5_inner3_rtr_MASK 0x4000
#define VGT_DEBUG_REG32__pipe5_inner3_rtr__SHIFT 0xe
#define VGT_DEBUG_REG32__pipe5_inner2_rtr_MASK 0x8000
#define VGT_DEBUG_REG32__pipe5_inner2_rtr__SHIFT 0xf
#define VGT_DEBUG_REG32__pg_edge_fifo3_full_MASK 0x10000
#define VGT_DEBUG_REG32__pg_edge_fifo3_full__SHIFT 0x10
#define VGT_DEBUG_REG32__pg_edge_fifo2_full_MASK 0x20000
#define VGT_DEBUG_REG32__pg_edge_fifo2_full__SHIFT 0x11
#define VGT_DEBUG_REG32__pg_inner3_point_fifo_full_MASK 0x40000
#define VGT_DEBUG_REG32__pg_inner3_point_fifo_full__SHIFT 0x12
#define VGT_DEBUG_REG32__pg_outer3_point_fifo_full_MASK 0x80000
#define VGT_DEBUG_REG32__pg_outer3_point_fifo_full__SHIFT 0x13
#define VGT_DEBUG_REG32__pg_inner2_point_fifo_full_MASK 0x100000
#define VGT_DEBUG_REG32__pg_inner2_point_fifo_full__SHIFT 0x14
#define VGT_DEBUG_REG32__pg_outer2_point_fifo_full_MASK 0x200000
#define VGT_DEBUG_REG32__pg_outer2_point_fifo_full__SHIFT 0x15
#define VGT_DEBUG_REG32__pg_inner_point_fifo_full_MASK 0x400000
#define VGT_DEBUG_REG32__pg_inner_point_fifo_full__SHIFT 0x16
#define VGT_DEBUG_REG32__pg_outer_point_fifo_full_MASK 0x800000
#define VGT_DEBUG_REG32__pg_outer_point_fifo_full__SHIFT 0x17
#define VGT_DEBUG_REG32__inner2_fifos_rtr_MASK 0x1000000
#define VGT_DEBUG_REG32__inner2_fifos_rtr__SHIFT 0x18
#define VGT_DEBUG_REG32__inner_fifos_rtr_MASK 0x2000000
#define VGT_DEBUG_REG32__inner_fifos_rtr__SHIFT 0x19
#define VGT_DEBUG_REG32__outer_fifos_rtr_MASK 0x4000000
#define VGT_DEBUG_REG32__outer_fifos_rtr__SHIFT 0x1a
#define VGT_DEBUG_REG32__fifos_rtr_MASK 0x8000000
#define VGT_DEBUG_REG32__fifos_rtr__SHIFT 0x1b
#define VGT_DEBUG_REG32__SPARE_MASK 0xf0000000
#define VGT_DEBUG_REG32__SPARE__SHIFT 0x1c
#define VGT_DEBUG_REG33__pipe0_patch_dr_MASK 0x1
#define VGT_DEBUG_REG33__pipe0_patch_dr__SHIFT 0x0
#define VGT_DEBUG_REG33__ring3_pipe1_dr_MASK 0x2
#define VGT_DEBUG_REG33__ring3_pipe1_dr__SHIFT 0x1
#define VGT_DEBUG_REG33__pipe1_dr_MASK 0x4
#define VGT_DEBUG_REG33__pipe1_dr__SHIFT 0x2
#define VGT_DEBUG_REG33__pipe2_dr_MASK 0x8
#define VGT_DEBUG_REG33__pipe2_dr__SHIFT 0x3
#define VGT_DEBUG_REG33__pipe0_patch_rtr_MASK 0x10
#define VGT_DEBUG_REG33__pipe0_patch_rtr__SHIFT 0x4
#define VGT_DEBUG_REG33__ring2_pipe1_dr_MASK 0x20
#define VGT_DEBUG_REG33__ring2_pipe1_dr__SHIFT 0x5
#define VGT_DEBUG_REG33__ring1_pipe1_dr_MASK 0x40
#define VGT_DEBUG_REG33__ring1_pipe1_dr__SHIFT 0x6
#define VGT_DEBUG_REG33__pipe2_rtr_MASK 0x80
#define VGT_DEBUG_REG33__pipe2_rtr__SHIFT 0x7
#define VGT_DEBUG_REG33__pipe3_dr_MASK 0x100
#define VGT_DEBUG_REG33__pipe3_dr__SHIFT 0x8
#define VGT_DEBUG_REG33__pipe3_rtr_MASK 0x200
#define VGT_DEBUG_REG33__pipe3_rtr__SHIFT 0x9
#define VGT_DEBUG_REG33__ring2_in_sync_q_MASK 0x400
#define VGT_DEBUG_REG33__ring2_in_sync_q__SHIFT 0xa
#define VGT_DEBUG_REG33__ring1_in_sync_q_MASK 0x800
#define VGT_DEBUG_REG33__ring1_in_sync_q__SHIFT 0xb
#define VGT_DEBUG_REG33__pipe1_patch_rtr_MASK 0x1000
#define VGT_DEBUG_REG33__pipe1_patch_rtr__SHIFT 0xc
#define VGT_DEBUG_REG33__ring3_in_sync_q_MASK 0x2000
#define VGT_DEBUG_REG33__ring3_in_sync_q__SHIFT 0xd
#define VGT_DEBUG_REG33__tm_te11_event_rtr_MASK 0x4000
#define VGT_DEBUG_REG33__tm_te11_event_rtr__SHIFT 0xe
#define VGT_DEBUG_REG33__first_prim_of_patch_q_MASK 0x8000
#define VGT_DEBUG_REG33__first_prim_of_patch_q__SHIFT 0xf
#define VGT_DEBUG_REG33__con_prim_fifo_full_MASK 0x10000
#define VGT_DEBUG_REG33__con_prim_fifo_full__SHIFT 0x10
#define VGT_DEBUG_REG33__con_vert_fifo_full_MASK 0x20000
#define VGT_DEBUG_REG33__con_vert_fifo_full__SHIFT 0x11
#define VGT_DEBUG_REG33__con_prim_fifo_empty_MASK 0x40000
#define VGT_DEBUG_REG33__con_prim_fifo_empty__SHIFT 0x12
#define VGT_DEBUG_REG33__con_vert_fifo_empty_MASK 0x80000
#define VGT_DEBUG_REG33__con_vert_fifo_empty__SHIFT 0x13
#define VGT_DEBUG_REG33__last_patch_of_tg_p0_q_MASK 0x100000
#define VGT_DEBUG_REG33__last_patch_of_tg_p0_q__SHIFT 0x14
#define VGT_DEBUG_REG33__ring3_valid_p2_MASK 0x200000
#define VGT_DEBUG_REG33__ring3_valid_p2__SHIFT 0x15
#define VGT_DEBUG_REG33__ring2_valid_p2_MASK 0x400000
#define VGT_DEBUG_REG33__ring2_valid_p2__SHIFT 0x16
#define VGT_DEBUG_REG33__ring1_valid_p2_MASK 0x800000
#define VGT_DEBUG_REG33__ring1_valid_p2__SHIFT 0x17
#define VGT_DEBUG_REG33__tess_type_p0_q_MASK 0x3000000
#define VGT_DEBUG_REG33__tess_type_p0_q__SHIFT 0x18
#define VGT_DEBUG_REG33__tess_topology_p0_q_MASK 0xc000000
#define VGT_DEBUG_REG33__tess_topology_p0_q__SHIFT 0x1a
#define VGT_DEBUG_REG33__te11_out_vert_gs_en_MASK 0x10000000
#define VGT_DEBUG_REG33__te11_out_vert_gs_en__SHIFT 0x1c
#define VGT_DEBUG_REG33__con_ring3_busy_MASK 0x20000000
#define VGT_DEBUG_REG33__con_ring3_busy__SHIFT 0x1d
#define VGT_DEBUG_REG33__con_ring2_busy_MASK 0x40000000
#define VGT_DEBUG_REG33__con_ring2_busy__SHIFT 0x1e
#define VGT_DEBUG_REG33__con_ring1_busy_MASK 0x80000000
#define VGT_DEBUG_REG33__con_ring1_busy__SHIFT 0x1f
#define VGT_DEBUG_REG34__con_state_q_MASK 0xf
#define VGT_DEBUG_REG34__con_state_q__SHIFT 0x0
#define VGT_DEBUG_REG34__second_cycle_q_MASK 0x10
#define VGT_DEBUG_REG34__second_cycle_q__SHIFT 0x4
#define VGT_DEBUG_REG34__process_tri_middle_p0_q_MASK 0x20
#define VGT_DEBUG_REG34__process_tri_middle_p0_q__SHIFT 0x5
#define VGT_DEBUG_REG34__process_tri_1st_2nd_half_p0_q_MASK 0x40
#define VGT_DEBUG_REG34__process_tri_1st_2nd_half_p0_q__SHIFT 0x6
#define VGT_DEBUG_REG34__process_tri_center_poly_p0_q_MASK 0x80
#define VGT_DEBUG_REG34__process_tri_center_poly_p0_q__SHIFT 0x7
#define VGT_DEBUG_REG34__pipe0_patch_dr_MASK 0x100
#define VGT_DEBUG_REG34__pipe0_patch_dr__SHIFT 0x8
#define VGT_DEBUG_REG34__pipe0_edge_dr_MASK 0x200
#define VGT_DEBUG_REG34__pipe0_edge_dr__SHIFT 0x9
#define VGT_DEBUG_REG34__pipe1_dr_MASK 0x400
#define VGT_DEBUG_REG34__pipe1_dr__SHIFT 0xa
#define VGT_DEBUG_REG34__pipe0_patch_rtr_MASK 0x800
#define VGT_DEBUG_REG34__pipe0_patch_rtr__SHIFT 0xb
#define VGT_DEBUG_REG34__pipe0_edge_rtr_MASK 0x1000
#define VGT_DEBUG_REG34__pipe0_edge_rtr__SHIFT 0xc
#define VGT_DEBUG_REG34__pipe1_rtr_MASK 0x2000
#define VGT_DEBUG_REG34__pipe1_rtr__SHIFT 0xd
#define VGT_DEBUG_REG34__outer_parity_p0_q_MASK 0x4000
#define VGT_DEBUG_REG34__outer_parity_p0_q__SHIFT 0xe
#define VGT_DEBUG_REG34__parallel_parity_p0_q_MASK 0x8000
#define VGT_DEBUG_REG34__parallel_parity_p0_q__SHIFT 0xf
#define VGT_DEBUG_REG34__first_ring_of_patch_p0_q_MASK 0x10000
#define VGT_DEBUG_REG34__first_ring_of_patch_p0_q__SHIFT 0x10
#define VGT_DEBUG_REG34__last_ring_of_patch_p0_q_MASK 0x20000
#define VGT_DEBUG_REG34__last_ring_of_patch_p0_q__SHIFT 0x11
#define VGT_DEBUG_REG34__last_edge_of_outer_ring_p0_q_MASK 0x40000
#define VGT_DEBUG_REG34__last_edge_of_outer_ring_p0_q__SHIFT 0x12
#define VGT_DEBUG_REG34__last_point_of_outer_ring_p1_MASK 0x80000
#define VGT_DEBUG_REG34__last_point_of_outer_ring_p1__SHIFT 0x13
#define VGT_DEBUG_REG34__last_point_of_inner_ring_p1_MASK 0x100000
#define VGT_DEBUG_REG34__last_point_of_inner_ring_p1__SHIFT 0x14
#define VGT_DEBUG_REG34__outer_edge_tf_eq_one_p0_q_MASK 0x200000
#define VGT_DEBUG_REG34__outer_edge_tf_eq_one_p0_q__SHIFT 0x15
#define VGT_DEBUG_REG34__advance_outer_point_p1_MASK 0x400000
#define VGT_DEBUG_REG34__advance_outer_point_p1__SHIFT 0x16
#define VGT_DEBUG_REG34__advance_inner_point_p1_MASK 0x800000
#define VGT_DEBUG_REG34__advance_inner_point_p1__SHIFT 0x17
#define VGT_DEBUG_REG34__next_ring_is_rect_p0_q_MASK 0x1000000
#define VGT_DEBUG_REG34__next_ring_is_rect_p0_q__SHIFT 0x18
#define VGT_DEBUG_REG34__pipe1_outer1_rtr_MASK 0x2000000
#define VGT_DEBUG_REG34__pipe1_outer1_rtr__SHIFT 0x19
#define VGT_DEBUG_REG34__pipe1_outer2_rtr_MASK 0x4000000
#define VGT_DEBUG_REG34__pipe1_outer2_rtr__SHIFT 0x1a
#define VGT_DEBUG_REG34__pipe1_inner1_rtr_MASK 0x8000000
#define VGT_DEBUG_REG34__pipe1_inner1_rtr__SHIFT 0x1b
#define VGT_DEBUG_REG34__pipe1_inner2_rtr_MASK 0x10000000
#define VGT_DEBUG_REG34__pipe1_inner2_rtr__SHIFT 0x1c
#define VGT_DEBUG_REG34__pipe1_patch_rtr_MASK 0x20000000
#define VGT_DEBUG_REG34__pipe1_patch_rtr__SHIFT 0x1d
#define VGT_DEBUG_REG34__pipe1_edge_rtr_MASK 0x40000000
#define VGT_DEBUG_REG34__pipe1_edge_rtr__SHIFT 0x1e
#define VGT_DEBUG_REG34__use_stored_inner_q_ring1_MASK 0x80000000
#define VGT_DEBUG_REG34__use_stored_inner_q_ring1__SHIFT 0x1f
#define VGT_DEBUG_REG36__VGT_PA_clipp_eop_MASK 0xffffffff
#define VGT_DEBUG_REG36__VGT_PA_clipp_eop__SHIFT 0x0
#define VGT_PERFCOUNTER_SEID_MASK__PERF_SEID_IGNORE_MASK_MASK 0xff
#define VGT_PERFCOUNTER_SEID_MASK__PERF_SEID_IGNORE_MASK__SHIFT 0x0
#define VGT_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x3ff
#define VGT_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
#define VGT_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0xffc00
#define VGT_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
#define VGT_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000
#define VGT_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
#define VGT_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0xf000000
#define VGT_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18
#define VGT_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xf0000000
#define VGT_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c
#define VGT_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x3ff
#define VGT_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
#define VGT_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0xffc00
#define VGT_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa
#define VGT_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0xf00000
#define VGT_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14
#define VGT_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0xf000000
#define VGT_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18
#define VGT_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xf0000000
#define VGT_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c
#define VGT_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0xff
#define VGT_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0
#define VGT_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xf0000000
#define VGT_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c
#define VGT_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0xff
#define VGT_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0
#define VGT_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xf0000000
#define VGT_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c
#define VGT_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x3ff
#define VGT_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0
#define VGT_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0xffc00
#define VGT_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
#define VGT_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0xf000000
#define VGT_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18
#define VGT_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xf0000000
#define VGT_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c
#define VGT_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x3ff
#define VGT_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0
#define VGT_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0xffc00
#define VGT_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa
#define VGT_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0xf000000
#define VGT_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x18
#define VGT_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0xf0000000
#define VGT_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x1c
#define VGT_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff
#define VGT_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
#define VGT_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff
#define VGT_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
#define VGT_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffff
#define VGT_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0
#define VGT_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffff
#define VGT_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0
#define VGT_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff
#define VGT_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
#define VGT_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff
#define VGT_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
#define VGT_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffff
#define VGT_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0
#define VGT_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffff
#define VGT_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0
#define IA_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x3ff
#define IA_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
#define IA_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0xffc00
#define IA_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
#define IA_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000
#define IA_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
#define IA_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0xf000000
#define IA_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18
#define IA_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xf0000000
#define IA_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c
#define IA_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0xff
#define IA_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
#define IA_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xf0000000
#define IA_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c
#define IA_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0xff
#define IA_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0
#define IA_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xf0000000
#define IA_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c
#define IA_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0xff
#define IA_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0
#define IA_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xf0000000
#define IA_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c
#define IA_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x3ff
#define IA_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0
#define IA_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0xffc00
#define IA_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
#define IA_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0xf000000
#define IA_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18
#define IA_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xf0000000
#define IA_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c
#define IA_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff
#define IA_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
#define IA_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff
#define IA_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
#define IA_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffff
#define IA_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0
#define IA_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffff
#define IA_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0
#define IA_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff
#define IA_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
#define IA_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff
#define IA_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
#define IA_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffff
#define IA_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0
#define IA_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffff
#define IA_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0
#define WD_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0xff
#define WD_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
#define WD_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xf0000000
#define WD_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c
#define WD_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0xff
#define WD_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
#define WD_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xf0000000
#define WD_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c
#define WD_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0xff
#define WD_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0
#define WD_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xf0000000
#define WD_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c
#define WD_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0xff
#define WD_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0
#define WD_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xf0000000
#define WD_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c
#define WD_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff
#define WD_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
#define WD_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff
#define WD_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
#define WD_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffff
#define WD_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0
#define WD_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffff
#define WD_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0
#define WD_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff
#define WD_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
#define WD_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff
#define WD_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
#define WD_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffff
#define WD_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0
#define WD_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffff
#define WD_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0
#define DIDT_IND_INDEX__DIDT_IND_INDEX_MASK 0xffffffff
#define DIDT_IND_INDEX__DIDT_IND_INDEX__SHIFT 0x0
#define DIDT_IND_DATA__DIDT_IND_DATA_MASK 0xffffffff
#define DIDT_IND_DATA__DIDT_IND_DATA__SHIFT 0x0
#define DIDT_SQ_CTRL0__DIDT_CTRL_EN_MASK 0x1
#define DIDT_SQ_CTRL0__DIDT_CTRL_EN__SHIFT 0x0
#define DIDT_SQ_CTRL0__USE_REF_CLOCK_MASK 0x2
#define DIDT_SQ_CTRL0__USE_REF_CLOCK__SHIFT 0x1
#define DIDT_SQ_CTRL0__PHASE_OFFSET_MASK 0xc
#define DIDT_SQ_CTRL0__PHASE_OFFSET__SHIFT 0x2
#define DIDT_SQ_CTRL0__DIDT_CTRL_RST_MASK 0x10
#define DIDT_SQ_CTRL0__DIDT_CTRL_RST__SHIFT 0x4
#define DIDT_SQ_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK 0x20
#define DIDT_SQ_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT 0x5
#define DIDT_SQ_CTRL1__MIN_POWER_MASK 0xffff
#define DIDT_SQ_CTRL1__MIN_POWER__SHIFT 0x0
#define DIDT_SQ_CTRL1__MAX_POWER_MASK 0xffff0000
#define DIDT_SQ_CTRL1__MAX_POWER__SHIFT 0x10
#define DIDT_SQ_CTRL2__MAX_POWER_DELTA_MASK 0x3fff
#define DIDT_SQ_CTRL2__MAX_POWER_DELTA__SHIFT 0x0
#define DIDT_SQ_CTRL2__UNUSED_0_MASK 0xc000
#define DIDT_SQ_CTRL2__UNUSED_0__SHIFT 0xe
#define DIDT_SQ_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK 0x3ff0000
#define DIDT_SQ_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT 0x10
#define DIDT_SQ_CTRL2__UNUSED_1_MASK 0x4000000
#define DIDT_SQ_CTRL2__UNUSED_1__SHIFT 0x1a
#define DIDT_SQ_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK 0x78000000
#define DIDT_SQ_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT 0x1b
#define DIDT_SQ_CTRL2__UNUSED_2_MASK 0x80000000
#define DIDT_SQ_CTRL2__UNUSED_2__SHIFT 0x1f
#define DIDT_SQ_CTRL_OCP__UNUSED_0_MASK 0xffff
#define DIDT_SQ_CTRL_OCP__UNUSED_0__SHIFT 0x0
#define DIDT_SQ_CTRL_OCP__OCP_MAX_POWER_MASK 0xffff0000
#define DIDT_SQ_CTRL_OCP__OCP_MAX_POWER__SHIFT 0x10
#define DIDT_SQ_WEIGHT0_3__WEIGHT0_MASK 0xff
#define DIDT_SQ_WEIGHT0_3__WEIGHT0__SHIFT 0x0
#define DIDT_SQ_WEIGHT0_3__WEIGHT1_MASK 0xff00
#define DIDT_SQ_WEIGHT0_3__WEIGHT1__SHIFT 0x8
#define DIDT_SQ_WEIGHT0_3__WEIGHT2_MASK 0xff0000
#define DIDT_SQ_WEIGHT0_3__WEIGHT2__SHIFT 0x10
#define DIDT_SQ_WEIGHT0_3__WEIGHT3_MASK 0xff000000
#define DIDT_SQ_WEIGHT0_3__WEIGHT3__SHIFT 0x18
#define DIDT_SQ_WEIGHT4_7__WEIGHT4_MASK 0xff
#define DIDT_SQ_WEIGHT4_7__WEIGHT4__SHIFT 0x0
#define DIDT_SQ_WEIGHT4_7__WEIGHT5_MASK 0xff00
#define DIDT_SQ_WEIGHT4_7__WEIGHT5__SHIFT 0x8
#define DIDT_SQ_WEIGHT4_7__WEIGHT6_MASK 0xff0000
#define DIDT_SQ_WEIGHT4_7__WEIGHT6__SHIFT 0x10
#define DIDT_SQ_WEIGHT4_7__WEIGHT7_MASK 0xff000000
#define DIDT_SQ_WEIGHT4_7__WEIGHT7__SHIFT 0x18
#define DIDT_SQ_WEIGHT8_11__WEIGHT8_MASK 0xff
#define DIDT_SQ_WEIGHT8_11__WEIGHT8__SHIFT 0x0
#define DIDT_SQ_WEIGHT8_11__WEIGHT9_MASK 0xff00
#define DIDT_SQ_WEIGHT8_11__WEIGHT9__SHIFT 0x8
#define DIDT_SQ_WEIGHT8_11__WEIGHT10_MASK 0xff0000
#define DIDT_SQ_WEIGHT8_11__WEIGHT10__SHIFT 0x10
#define DIDT_SQ_WEIGHT8_11__WEIGHT11_MASK 0xff000000
#define DIDT_SQ_WEIGHT8_11__WEIGHT11__SHIFT 0x18
#define DIDT_DB_CTRL0__DIDT_CTRL_EN_MASK 0x1
#define DIDT_DB_CTRL0__DIDT_CTRL_EN__SHIFT 0x0
#define DIDT_DB_CTRL0__USE_REF_CLOCK_MASK 0x2
#define DIDT_DB_CTRL0__USE_REF_CLOCK__SHIFT 0x1
#define DIDT_DB_CTRL0__PHASE_OFFSET_MASK 0xc
#define DIDT_DB_CTRL0__PHASE_OFFSET__SHIFT 0x2
#define DIDT_DB_CTRL0__DIDT_CTRL_RST_MASK 0x10
#define DIDT_DB_CTRL0__DIDT_CTRL_RST__SHIFT 0x4
#define DIDT_DB_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK 0x20
#define DIDT_DB_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT 0x5
#define DIDT_DB_CTRL1__MIN_POWER_MASK 0xffff
#define DIDT_DB_CTRL1__MIN_POWER__SHIFT 0x0
#define DIDT_DB_CTRL1__MAX_POWER_MASK 0xffff0000
#define DIDT_DB_CTRL1__MAX_POWER__SHIFT 0x10
#define DIDT_DB_CTRL2__MAX_POWER_DELTA_MASK 0x3fff
#define DIDT_DB_CTRL2__MAX_POWER_DELTA__SHIFT 0x0
#define DIDT_DB_CTRL2__UNUSED_0_MASK 0xc000
#define DIDT_DB_CTRL2__UNUSED_0__SHIFT 0xe
#define DIDT_DB_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK 0x3ff0000
#define DIDT_DB_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT 0x10
#define DIDT_DB_CTRL2__UNUSED_1_MASK 0x4000000
#define DIDT_DB_CTRL2__UNUSED_1__SHIFT 0x1a
#define DIDT_DB_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK 0x78000000
#define DIDT_DB_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT 0x1b
#define DIDT_DB_CTRL2__UNUSED_2_MASK 0x80000000
#define DIDT_DB_CTRL2__UNUSED_2__SHIFT 0x1f
#define DIDT_DB_CTRL_OCP__UNUSED_0_MASK 0xffff
#define DIDT_DB_CTRL_OCP__UNUSED_0__SHIFT 0x0
#define DIDT_DB_CTRL_OCP__OCP_MAX_POWER_MASK 0xffff0000
#define DIDT_DB_CTRL_OCP__OCP_MAX_POWER__SHIFT 0x10
#define DIDT_DB_WEIGHT0_3__WEIGHT0_MASK 0xff
#define DIDT_DB_WEIGHT0_3__WEIGHT0__SHIFT 0x0
#define DIDT_DB_WEIGHT0_3__WEIGHT1_MASK 0xff00
#define DIDT_DB_WEIGHT0_3__WEIGHT1__SHIFT 0x8
#define DIDT_DB_WEIGHT0_3__WEIGHT2_MASK 0xff0000
#define DIDT_DB_WEIGHT0_3__WEIGHT2__SHIFT 0x10
#define DIDT_DB_WEIGHT0_3__WEIGHT3_MASK 0xff000000
#define DIDT_DB_WEIGHT0_3__WEIGHT3__SHIFT 0x18
#define DIDT_DB_WEIGHT4_7__WEIGHT4_MASK 0xff
#define DIDT_DB_WEIGHT4_7__WEIGHT4__SHIFT 0x0
#define DIDT_DB_WEIGHT4_7__WEIGHT5_MASK 0xff00
#define DIDT_DB_WEIGHT4_7__WEIGHT5__SHIFT 0x8
#define DIDT_DB_WEIGHT4_7__WEIGHT6_MASK 0xff0000
#define DIDT_DB_WEIGHT4_7__WEIGHT6__SHIFT 0x10
#define DIDT_DB_WEIGHT4_7__WEIGHT7_MASK 0xff000000
#define DIDT_DB_WEIGHT4_7__WEIGHT7__SHIFT 0x18
#define DIDT_DB_WEIGHT8_11__WEIGHT8_MASK 0xff
#define DIDT_DB_WEIGHT8_11__WEIGHT8__SHIFT 0x0
#define DIDT_DB_WEIGHT8_11__WEIGHT9_MASK 0xff00
#define DIDT_DB_WEIGHT8_11__WEIGHT9__SHIFT 0x8
#define DIDT_DB_WEIGHT8_11__WEIGHT10_MASK 0xff0000
#define DIDT_DB_WEIGHT8_11__WEIGHT10__SHIFT 0x10
#define DIDT_DB_WEIGHT8_11__WEIGHT11_MASK 0xff000000
#define DIDT_DB_WEIGHT8_11__WEIGHT11__SHIFT 0x18
#define DIDT_TD_CTRL0__DIDT_CTRL_EN_MASK 0x1
#define DIDT_TD_CTRL0__DIDT_CTRL_EN__SHIFT 0x0
#define DIDT_TD_CTRL0__USE_REF_CLOCK_MASK 0x2
#define DIDT_TD_CTRL0__USE_REF_CLOCK__SHIFT 0x1
#define DIDT_TD_CTRL0__PHASE_OFFSET_MASK 0xc
#define DIDT_TD_CTRL0__PHASE_OFFSET__SHIFT 0x2
#define DIDT_TD_CTRL0__DIDT_CTRL_RST_MASK 0x10
#define DIDT_TD_CTRL0__DIDT_CTRL_RST__SHIFT 0x4
#define DIDT_TD_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK 0x20
#define DIDT_TD_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT 0x5
#define DIDT_TD_CTRL1__MIN_POWER_MASK 0xffff
#define DIDT_TD_CTRL1__MIN_POWER__SHIFT 0x0
#define DIDT_TD_CTRL1__MAX_POWER_MASK 0xffff0000
#define DIDT_TD_CTRL1__MAX_POWER__SHIFT 0x10
#define DIDT_TD_CTRL2__MAX_POWER_DELTA_MASK 0x3fff
#define DIDT_TD_CTRL2__MAX_POWER_DELTA__SHIFT 0x0
#define DIDT_TD_CTRL2__UNUSED_0_MASK 0xc000
#define DIDT_TD_CTRL2__UNUSED_0__SHIFT 0xe
#define DIDT_TD_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK 0x3ff0000
#define DIDT_TD_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT 0x10
#define DIDT_TD_CTRL2__UNUSED_1_MASK 0x4000000
#define DIDT_TD_CTRL2__UNUSED_1__SHIFT 0x1a
#define DIDT_TD_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK 0x78000000
#define DIDT_TD_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT 0x1b
#define DIDT_TD_CTRL2__UNUSED_2_MASK 0x80000000
#define DIDT_TD_CTRL2__UNUSED_2__SHIFT 0x1f
#define DIDT_TD_CTRL_OCP__UNUSED_0_MASK 0xffff
#define DIDT_TD_CTRL_OCP__UNUSED_0__SHIFT 0x0
#define DIDT_TD_CTRL_OCP__OCP_MAX_POWER_MASK 0xffff0000
#define DIDT_TD_CTRL_OCP__OCP_MAX_POWER__SHIFT 0x10
#define DIDT_TD_WEIGHT0_3__WEIGHT0_MASK 0xff
#define DIDT_TD_WEIGHT0_3__WEIGHT0__SHIFT 0x0
#define DIDT_TD_WEIGHT0_3__WEIGHT1_MASK 0xff00
#define DIDT_TD_WEIGHT0_3__WEIGHT1__SHIFT 0x8
#define DIDT_TD_WEIGHT0_3__WEIGHT2_MASK 0xff0000
#define DIDT_TD_WEIGHT0_3__WEIGHT2__SHIFT 0x10
#define DIDT_TD_WEIGHT0_3__WEIGHT3_MASK 0xff000000
#define DIDT_TD_WEIGHT0_3__WEIGHT3__SHIFT 0x18
#define DIDT_TD_WEIGHT4_7__WEIGHT4_MASK 0xff
#define DIDT_TD_WEIGHT4_7__WEIGHT4__SHIFT 0x0
#define DIDT_TD_WEIGHT4_7__WEIGHT5_MASK 0xff00
#define DIDT_TD_WEIGHT4_7__WEIGHT5__SHIFT 0x8
#define DIDT_TD_WEIGHT4_7__WEIGHT6_MASK 0xff0000
#define DIDT_TD_WEIGHT4_7__WEIGHT6__SHIFT 0x10
#define DIDT_TD_WEIGHT4_7__WEIGHT7_MASK 0xff000000
#define DIDT_TD_WEIGHT4_7__WEIGHT7__SHIFT 0x18
#define DIDT_TD_WEIGHT8_11__WEIGHT8_MASK 0xff
#define DIDT_TD_WEIGHT8_11__WEIGHT8__SHIFT 0x0
#define DIDT_TD_WEIGHT8_11__WEIGHT9_MASK 0xff00
#define DIDT_TD_WEIGHT8_11__WEIGHT9__SHIFT 0x8
#define DIDT_TD_WEIGHT8_11__WEIGHT10_MASK 0xff0000
#define DIDT_TD_WEIGHT8_11__WEIGHT10__SHIFT 0x10
#define DIDT_TD_WEIGHT8_11__WEIGHT11_MASK 0xff000000
#define DIDT_TD_WEIGHT8_11__WEIGHT11__SHIFT 0x18
#define DIDT_TCP_CTRL0__DIDT_CTRL_EN_MASK 0x1
#define DIDT_TCP_CTRL0__DIDT_CTRL_EN__SHIFT 0x0
#define DIDT_TCP_CTRL0__USE_REF_CLOCK_MASK 0x2
#define DIDT_TCP_CTRL0__USE_REF_CLOCK__SHIFT 0x1
#define DIDT_TCP_CTRL0__PHASE_OFFSET_MASK 0xc
#define DIDT_TCP_CTRL0__PHASE_OFFSET__SHIFT 0x2
#define DIDT_TCP_CTRL0__DIDT_CTRL_RST_MASK 0x10
#define DIDT_TCP_CTRL0__DIDT_CTRL_RST__SHIFT 0x4
#define DIDT_TCP_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK 0x20
#define DIDT_TCP_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT 0x5
#define DIDT_TCP_CTRL1__MIN_POWER_MASK 0xffff
#define DIDT_TCP_CTRL1__MIN_POWER__SHIFT 0x0
#define DIDT_TCP_CTRL1__MAX_POWER_MASK 0xffff0000
#define DIDT_TCP_CTRL1__MAX_POWER__SHIFT 0x10
#define DIDT_TCP_CTRL2__MAX_POWER_DELTA_MASK 0x3fff
#define DIDT_TCP_CTRL2__MAX_POWER_DELTA__SHIFT 0x0
#define DIDT_TCP_CTRL2__UNUSED_0_MASK 0xc000
#define DIDT_TCP_CTRL2__UNUSED_0__SHIFT 0xe
#define DIDT_TCP_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK 0x3ff0000
#define DIDT_TCP_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT 0x10
#define DIDT_TCP_CTRL2__UNUSED_1_MASK 0x4000000
#define DIDT_TCP_CTRL2__UNUSED_1__SHIFT 0x1a
#define DIDT_TCP_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK 0x78000000
#define DIDT_TCP_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT 0x1b
#define DIDT_TCP_CTRL2__UNUSED_2_MASK 0x80000000
#define DIDT_TCP_CTRL2__UNUSED_2__SHIFT 0x1f
#define DIDT_TCP_CTRL_OCP__UNUSED_0_MASK 0xffff
#define DIDT_TCP_CTRL_OCP__UNUSED_0__SHIFT 0x0
#define DIDT_TCP_CTRL_OCP__OCP_MAX_POWER_MASK 0xffff0000
#define DIDT_TCP_CTRL_OCP__OCP_MAX_POWER__SHIFT 0x10
#define DIDT_TCP_WEIGHT0_3__WEIGHT0_MASK 0xff
#define DIDT_TCP_WEIGHT0_3__WEIGHT0__SHIFT 0x0
#define DIDT_TCP_WEIGHT0_3__WEIGHT1_MASK 0xff00
#define DIDT_TCP_WEIGHT0_3__WEIGHT1__SHIFT 0x8
#define DIDT_TCP_WEIGHT0_3__WEIGHT2_MASK 0xff0000
#define DIDT_TCP_WEIGHT0_3__WEIGHT2__SHIFT 0x10
#define DIDT_TCP_WEIGHT0_3__WEIGHT3_MASK 0xff000000
#define DIDT_TCP_WEIGHT0_3__WEIGHT3__SHIFT 0x18
#define DIDT_TCP_WEIGHT4_7__WEIGHT4_MASK 0xff
#define DIDT_TCP_WEIGHT4_7__WEIGHT4__SHIFT 0x0
#define DIDT_TCP_WEIGHT4_7__WEIGHT5_MASK 0xff00
#define DIDT_TCP_WEIGHT4_7__WEIGHT5__SHIFT 0x8
#define DIDT_TCP_WEIGHT4_7__WEIGHT6_MASK 0xff0000
#define DIDT_TCP_WEIGHT4_7__WEIGHT6__SHIFT 0x10
#define DIDT_TCP_WEIGHT4_7__WEIGHT7_MASK 0xff000000
#define DIDT_TCP_WEIGHT4_7__WEIGHT7__SHIFT 0x18
#define DIDT_TCP_WEIGHT8_11__WEIGHT8_MASK 0xff
#define DIDT_TCP_WEIGHT8_11__WEIGHT8__SHIFT 0x0
#define DIDT_TCP_WEIGHT8_11__WEIGHT9_MASK 0xff00
#define DIDT_TCP_WEIGHT8_11__WEIGHT9__SHIFT 0x8
#define DIDT_TCP_WEIGHT8_11__WEIGHT10_MASK 0xff0000
#define DIDT_TCP_WEIGHT8_11__WEIGHT10__SHIFT 0x10
#define DIDT_TCP_WEIGHT8_11__WEIGHT11_MASK 0xff000000
#define DIDT_TCP_WEIGHT8_11__WEIGHT11__SHIFT 0x18
#define DIDT_DBR_CTRL0__DIDT_CTRL_EN_MASK 0x1
#define DIDT_DBR_CTRL0__DIDT_CTRL_EN__SHIFT 0x0
#define DIDT_DBR_CTRL0__USE_REF_CLOCK_MASK 0x2
#define DIDT_DBR_CTRL0__USE_REF_CLOCK__SHIFT 0x1
#define DIDT_DBR_CTRL0__PHASE_OFFSET_MASK 0xc
#define DIDT_DBR_CTRL0__PHASE_OFFSET__SHIFT 0x2
#define DIDT_DBR_CTRL0__DIDT_CTRL_RST_MASK 0x10
#define DIDT_DBR_CTRL0__DIDT_CTRL_RST__SHIFT 0x4
#define DIDT_DBR_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK 0x20
#define DIDT_DBR_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT 0x5
#define DIDT_DBR_CTRL1__MIN_POWER_MASK 0xffff
#define DIDT_DBR_CTRL1__MIN_POWER__SHIFT 0x0
#define DIDT_DBR_CTRL1__MAX_POWER_MASK 0xffff0000
#define DIDT_DBR_CTRL1__MAX_POWER__SHIFT 0x10
#define DIDT_DBR_CTRL2__MAX_POWER_DELTA_MASK 0x3fff
#define DIDT_DBR_CTRL2__MAX_POWER_DELTA__SHIFT 0x0
#define DIDT_DBR_CTRL2__UNUSED_0_MASK 0xc000
#define DIDT_DBR_CTRL2__UNUSED_0__SHIFT 0xe
#define DIDT_DBR_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK 0x3ff0000
#define DIDT_DBR_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT 0x10
#define DIDT_DBR_CTRL2__UNUSED_1_MASK 0x4000000
#define DIDT_DBR_CTRL2__UNUSED_1__SHIFT 0x1a
#define DIDT_DBR_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK 0x78000000
#define DIDT_DBR_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT 0x1b
#define DIDT_DBR_CTRL2__UNUSED_2_MASK 0x80000000
#define DIDT_DBR_CTRL2__UNUSED_2__SHIFT 0x1f
#define DIDT_DBR_CTRL_OCP__UNUSED_0_MASK 0xffff
#define DIDT_DBR_CTRL_OCP__UNUSED_0__SHIFT 0x0
#define DIDT_DBR_CTRL_OCP__OCP_MAX_POWER_MASK 0xffff0000
#define DIDT_DBR_CTRL_OCP__OCP_MAX_POWER__SHIFT 0x10
#define DIDT_DBR_WEIGHT0_3__WEIGHT0_MASK 0xff
#define DIDT_DBR_WEIGHT0_3__WEIGHT0__SHIFT 0x0
#define DIDT_DBR_WEIGHT0_3__WEIGHT1_MASK 0xff00
#define DIDT_DBR_WEIGHT0_3__WEIGHT1__SHIFT 0x8
#define DIDT_DBR_WEIGHT0_3__WEIGHT2_MASK 0xff0000
#define DIDT_DBR_WEIGHT0_3__WEIGHT2__SHIFT 0x10
#define DIDT_DBR_WEIGHT0_3__WEIGHT3_MASK 0xff000000
#define DIDT_DBR_WEIGHT0_3__WEIGHT3__SHIFT 0x18
#define DIDT_DBR_WEIGHT4_7__WEIGHT4_MASK 0xff
#define DIDT_DBR_WEIGHT4_7__WEIGHT4__SHIFT 0x0
#define DIDT_DBR_WEIGHT4_7__WEIGHT5_MASK 0xff00
#define DIDT_DBR_WEIGHT4_7__WEIGHT5__SHIFT 0x8
#define DIDT_DBR_WEIGHT4_7__WEIGHT6_MASK 0xff0000
#define DIDT_DBR_WEIGHT4_7__WEIGHT6__SHIFT 0x10
#define DIDT_DBR_WEIGHT4_7__WEIGHT7_MASK 0xff000000
#define DIDT_DBR_WEIGHT4_7__WEIGHT7__SHIFT 0x18
#define DIDT_DBR_WEIGHT8_11__WEIGHT8_MASK 0xff
#define DIDT_DBR_WEIGHT8_11__WEIGHT8__SHIFT 0x0
#define DIDT_DBR_WEIGHT8_11__WEIGHT9_MASK 0xff00
#define DIDT_DBR_WEIGHT8_11__WEIGHT9__SHIFT 0x8
#define DIDT_DBR_WEIGHT8_11__WEIGHT10_MASK 0xff0000
#define DIDT_DBR_WEIGHT8_11__WEIGHT10__SHIFT 0x10
#define DIDT_DBR_WEIGHT8_11__WEIGHT11_MASK 0xff000000
#define DIDT_DBR_WEIGHT8_11__WEIGHT11__SHIFT 0x18
#define DIDT_SQ_STALL_CTRL__DIDT_STALL_CTRL_ENABLE_MASK 0x00000001
#define DIDT_SQ_STALL_CTRL__DIDT_STALL_CTRL_ENABLE__SHIFT 0x00000000
#define DIDT_SQ_STALL_CTRL__DIDT_STALL_DELAY_HI_MASK 0x0000007e
#define DIDT_SQ_STALL_CTRL__DIDT_STALL_DELAY_LO_MASK 0x00001f80L
#define DIDT_SQ_STALL_CTRL__DIDT_STALL_DELAY_HI__SHIFT 0x00000001
#define DIDT_SQ_STALL_CTRL__DIDT_STALL_DELAY_LO__SHIFT 0x00000007
#define DIDT_SQ_STALL_CTRL__DIDT_HI_POWER_THRESHOLD_MASK 0x1fffe000L
#define DIDT_SQ_STALL_CTRL__DIDT_HI_POWER_THRESHOLD__SHIFT 0x0000000d
#define DIDT_SQ_STALL_CTRL__UNUSED_0_MASK 0xe0000000L
#define DIDT_SQ_STALL_CTRL__UNUSED_0__SHIFT 0x0000001d
#define DIDT_SQ_TUNING_CTRL__DIDT_TUNING_ENABLE_MASK 0x00000001L
#define DIDT_SQ_TUNING_CTRL__DIDT_TUNING_ENABLE__SHIFT 0x00000000
#define DIDT_SQ_TUNING_CTRL__MAX_POWER_DELTA_HI_MASK 0x00007ffeL
#define DIDT_SQ_TUNING_CTRL__MAX_POWER_DELTA_HI__SHIFT 0x00000001
#define DIDT_SQ_TUNING_CTRL__MAX_POWER_DELTA_LO_MASK 0x1fff8000L
#define DIDT_SQ_TUNING_CTRL__MAX_POWER_DELTA_LO__SHIFT 0x0000000f
#define DIDT_TD_STALL_CTRL__DIDT_STALL_CTRL_ENABLE_MASK 0x00000001L
#define DIDT_TD_STALL_CTRL__DIDT_STALL_CTRL_ENABLE__SHIFT 0x00000000
#define DIDT_TD_STALL_CTRL__DIDT_STALL_DELAY_HI_MASK 0x0000007eL
#define DIDT_TD_STALL_CTRL__DIDT_STALL_DELAY_LO_MASK 0x00001f80L
#define DIDT_TD_STALL_CTRL__DIDT_STALL_DELAY_HI__SHIFT 0x00000001
#define DIDT_TD_STALL_CTRL__DIDT_STALL_DELAY_LO__SHIFT 0x00000007
#define DIDT_TD_STALL_CTRL__DIDT_HI_POWER_THRESHOLD_MASK 0x1fffe000L
#define DIDT_TD_STALL_CTRL__DIDT_HI_POWER_THRESHOLD__SHIFT 0x0000000d
#define DIDT_SQ_CTRL0__DIDT_MAX_STALLS_ALLOWED_HI_MASK 0x00000fc0L
#define DIDT_SQ_CTRL0__DIDT_MAX_STALLS_ALLOWED_LO_MASK 0x0003f000L
#define DIDT_SQ_CTRL0__DIDT_MAX_STALLS_ALLOWED_HI__SHIFT 0x00000006
#define DIDT_SQ_CTRL0__DIDT_MAX_STALLS_ALLOWED_LO__SHIFT 0x0000000c
#define DIDT_TD_TUNING_CTRL__DIDT_TUNING_ENABLE_MASK 0x00000001L
#define DIDT_TD_TUNING_CTRL__MAX_POWER_DELTA_HI_MASK 0x00007ffeL
#define DIDT_TD_TUNING_CTRL__MAX_POWER_DELTA_LO_MASK 0x1fff8000L
#define DIDT_TD_TUNING_CTRL__DIDT_TUNING_ENABLE__SHIFT 0x00000000
#define DIDT_TD_TUNING_CTRL__MAX_POWER_DELTA_HI__SHIFT 0x00000001
#define DIDT_TD_TUNING_CTRL__MAX_POWER_DELTA_LO__SHIFT 0x0000000f
#define DIDT_TD_STALL_CTRL__UNUSED_0_MASK 0xe0000000L
#define DIDT_TD_STALL_CTRL__UNUSED_0__SHIFT 0x0000001d
#define DIDT_TD_CTRL0__DIDT_MAX_STALLS_ALLOWED_HI_MASK 0x00000fc0L
#define DIDT_TD_CTRL0__DIDT_MAX_STALLS_ALLOWED_LO_MASK 0x0003f000L
#define DIDT_TD_CTRL0__DIDT_MAX_STALLS_ALLOWED_HI__SHIFT 0x00000006
#define DIDT_TD_CTRL0__DIDT_MAX_STALLS_ALLOWED_LO__SHIFT 0x0000000c
#define DIDT_TCP_STALL_CTRL__DIDT_STALL_CTRL_ENABLE_MASK 0x00000001L
#define DIDT_TCP_STALL_CTRL__DIDT_STALL_CTRL_ENABLE__SHIFT 0x00000000
#define DIDT_TCP_STALL_CTRL__DIDT_STALL_DELAY_HI_MASK 0x0000007eL
#define DIDT_TCP_STALL_CTRL__DIDT_STALL_DELAY_LO_MASK 0x00001f80L
#define DIDT_TCP_STALL_CTRL__DIDT_STALL_DELAY_HI__SHIFT 0x00000001
#define DIDT_TCP_STALL_CTRL__DIDT_STALL_DELAY_LO__SHIFT 0x00000007
#define DIDT_TCP_STALL_CTRL__DIDT_HI_POWER_THRESHOLD_MASK 0x1fffe000L
#define DIDT_TCP_STALL_CTRL__DIDT_HI_POWER_THRESHOLD__SHIFT 0x0000000d
#define DIDT_TCP_STALL_CTRL__UNUSED_0_MASK 0xe0000000L
#define DIDT_TCP_STALL_CTRL__UNUSED_0__SHIFT 0x0000001d
#define DIDT_TCP_TUNING_CTRL__DIDT_TUNING_ENABLE_MASK 0x00000001L
#define DIDT_TCP_TUNING_CTRL__MAX_POWER_DELTA_HI_MASK 0x00007ffeL
#define DIDT_TCP_TUNING_CTRL__MAX_POWER_DELTA_LO_MASK 0x1fff8000L
#define DIDT_TCP_TUNING_CTRL__DIDT_TUNING_ENABLE__SHIFT 0x00000000
#define DIDT_TCP_TUNING_CTRL__MAX_POWER_DELTA_HI__SHIFT 0x00000001
#define DIDT_TCP_TUNING_CTRL__MAX_POWER_DELTA_LO__SHIFT 0x0000000f
#define DIDT_TCP_CTRL0__DIDT_MAX_STALLS_ALLOWED_HI_MASK 0x00000fc0L
#define DIDT_TCP_CTRL0__DIDT_MAX_STALLS_ALLOWED_LO_MASK 0x0003f000L
#define DIDT_TCP_CTRL0__DIDT_MAX_STALLS_ALLOWED_HI__SHIFT 0x00000006
#define DIDT_TCP_CTRL0__DIDT_MAX_STALLS_ALLOWED_LO__SHIFT 0x0000000c
#endif /* GFX_8_0_SH_MASK_H */
|
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* pv88080-regulator.h - Regulator definitions for PV88080
* Copyright (C) 2016 Powerventure Semiconductor Ltd.
*/
#ifndef __PV88080_REGISTERS_H__
#define __PV88080_REGISTERS_H__
/* System Control and Event Registers */
#define PV88080_REG_EVENT_A 0x04
#define PV88080_REG_MASK_A 0x09
#define PV88080_REG_MASK_B 0x0A
#define PV88080_REG_MASK_C 0x0B
/* Regulator Registers - rev. AA */
#define PV88080AA_REG_HVBUCK_CONF1 0x2D
#define PV88080AA_REG_HVBUCK_CONF2 0x2E
#define PV88080AA_REG_BUCK1_CONF0 0x27
#define PV88080AA_REG_BUCK1_CONF1 0x28
#define PV88080AA_REG_BUCK1_CONF2 0x59
#define PV88080AA_REG_BUCK1_CONF5 0x5C
#define PV88080AA_REG_BUCK2_CONF0 0x29
#define PV88080AA_REG_BUCK2_CONF1 0x2A
#define PV88080AA_REG_BUCK2_CONF2 0x61
#define PV88080AA_REG_BUCK2_CONF5 0x64
#define PV88080AA_REG_BUCK3_CONF0 0x2B
#define PV88080AA_REG_BUCK3_CONF1 0x2C
#define PV88080AA_REG_BUCK3_CONF2 0x69
#define PV88080AA_REG_BUCK3_CONF5 0x6C
/* Regulator Registers - rev. BA */
#define PV88080BA_REG_HVBUCK_CONF1 0x33
#define PV88080BA_REG_HVBUCK_CONF2 0x34
#define PV88080BA_REG_BUCK1_CONF0 0x2A
#define PV88080BA_REG_BUCK1_CONF1 0x2C
#define PV88080BA_REG_BUCK1_CONF2 0x5A
#define PV88080BA_REG_BUCK1_CONF5 0x5D
#define PV88080BA_REG_BUCK2_CONF0 0x2D
#define PV88080BA_REG_BUCK2_CONF1 0x2F
#define PV88080BA_REG_BUCK2_CONF2 0x63
#define PV88080BA_REG_BUCK2_CONF5 0x66
#define PV88080BA_REG_BUCK3_CONF0 0x30
#define PV88080BA_REG_BUCK3_CONF1 0x32
#define PV88080BA_REG_BUCK3_CONF2 0x6C
#define PV88080BA_REG_BUCK3_CONF5 0x6F
/* PV88080_REG_EVENT_A (addr=0x04) */
#define PV88080_E_VDD_FLT 0x01
#define PV88080_E_OVER_TEMP 0x02
/* PV88080_REG_MASK_A (addr=0x09) */
#define PV88080_M_VDD_FLT 0x01
#define PV88080_M_OVER_TEMP 0x02
/* PV88080_REG_BUCK1_CONF0 (addr=0x27|0x2A) */
#define PV88080_BUCK1_EN 0x80
#define PV88080_VBUCK1_MASK 0x7F
/* PV88080_REG_BUCK2_CONF0 (addr=0x29|0x2D) */
#define PV88080_BUCK2_EN 0x80
#define PV88080_VBUCK2_MASK 0x7F
/* PV88080_REG_BUCK3_CONF0 (addr=0x2B|0x30) */
#define PV88080_BUCK3_EN 0x80
#define PV88080_VBUCK3_MASK 0x7F
/* PV88080_REG_BUCK1_CONF1 (addr=0x28|0x2C) */
#define PV88080_BUCK1_ILIM_SHIFT 2
#define PV88080_BUCK1_ILIM_MASK 0x0C
#define PV88080_BUCK1_MODE_MASK 0x03
/* PV88080_REG_BUCK2_CONF1 (addr=0x2A|0x2F) */
#define PV88080_BUCK2_ILIM_SHIFT 2
#define PV88080_BUCK2_ILIM_MASK 0x0C
#define PV88080_BUCK2_MODE_MASK 0x03
/* PV88080_REG_BUCK3_CONF1 (addr=0x2C|0x32) */
#define PV88080_BUCK3_ILIM_SHIFT 2
#define PV88080_BUCK3_ILIM_MASK 0x0C
#define PV88080_BUCK3_MODE_MASK 0x03
#define PV88080_BUCK_MODE_SLEEP 0x00
#define PV88080_BUCK_MODE_AUTO 0x01
#define PV88080_BUCK_MODE_SYNC 0x02
/* PV88080_REG_HVBUCK_CONF1 (addr=0x2D|0x33) */
#define PV88080_VHVBUCK_MASK 0xFF
/* PV88080_REG_HVBUCK_CONF1 (addr=0x2E|0x34) */
#define PV88080_HVBUCK_EN 0x01
/* PV88080_REG_BUCK2_CONF2 (addr=0x61|0x63) */
/* PV88080_REG_BUCK3_CONF2 (addr=0x69|0x6C) */
#define PV88080_BUCK_VDAC_RANGE_SHIFT 7
#define PV88080_BUCK_VDAC_RANGE_MASK 0x01
#define PV88080_BUCK_VDAC_RANGE_1 0x00
#define PV88080_BUCK_VDAC_RANGE_2 0x01
/* PV88080_REG_BUCK2_CONF5 (addr=0x64|0x66) */
/* PV88080_REG_BUCK3_CONF5 (addr=0x6C|0x6F) */
#define PV88080_BUCK_VRANGE_GAIN_SHIFT 0
#define PV88080_BUCK_VRANGE_GAIN_MASK 0x01
#define PV88080_BUCK_VRANGE_GAIN_1 0x00
#define PV88080_BUCK_VRANGE_GAIN_2 0x01
#endif /* __PV88080_REGISTERS_H__ */
|
/* SPDX-License-Identifier: MIT */
/*
* Copyright © 2014-2018 Broadcom
* Copyright © 2019 Collabora ltd.
*/
#ifndef _PANFROST_DRM_H_
#define _PANFROST_DRM_H_
#include "drm.h"
#if defined(__cplusplus)
extern "C" {
#endif
#define DRM_PANFROST_SUBMIT 0x00
#define DRM_PANFROST_WAIT_BO 0x01
#define DRM_PANFROST_CREATE_BO 0x02
#define DRM_PANFROST_MMAP_BO 0x03
#define DRM_PANFROST_GET_PARAM 0x04
#define DRM_PANFROST_GET_BO_OFFSET 0x05
#define DRM_PANFROST_PERFCNT_ENABLE 0x06
#define DRM_PANFROST_PERFCNT_DUMP 0x07
#define DRM_PANFROST_MADVISE 0x08
#define DRM_IOCTL_PANFROST_SUBMIT DRM_IOW(DRM_COMMAND_BASE + DRM_PANFROST_SUBMIT, struct drm_panfrost_submit)
#define DRM_IOCTL_PANFROST_WAIT_BO DRM_IOW(DRM_COMMAND_BASE + DRM_PANFROST_WAIT_BO, struct drm_panfrost_wait_bo)
#define DRM_IOCTL_PANFROST_CREATE_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_PANFROST_CREATE_BO, struct drm_panfrost_create_bo)
#define DRM_IOCTL_PANFROST_MMAP_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_PANFROST_MMAP_BO, struct drm_panfrost_mmap_bo)
#define DRM_IOCTL_PANFROST_GET_PARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_PANFROST_GET_PARAM, struct drm_panfrost_get_param)
#define DRM_IOCTL_PANFROST_GET_BO_OFFSET DRM_IOWR(DRM_COMMAND_BASE + DRM_PANFROST_GET_BO_OFFSET, struct drm_panfrost_get_bo_offset)
#define DRM_IOCTL_PANFROST_MADVISE DRM_IOWR(DRM_COMMAND_BASE + DRM_PANFROST_MADVISE, struct drm_panfrost_madvise)
/*
* Unstable ioctl(s): only exposed when the unsafe unstable_ioctls module
* param is set to true.
* All these ioctl(s) are subject to deprecation, so please don't rely on
* them for anything but debugging purpose.
*/
#define DRM_IOCTL_PANFROST_PERFCNT_ENABLE DRM_IOW(DRM_COMMAND_BASE + DRM_PANFROST_PERFCNT_ENABLE, struct drm_panfrost_perfcnt_enable)
#define DRM_IOCTL_PANFROST_PERFCNT_DUMP DRM_IOW(DRM_COMMAND_BASE + DRM_PANFROST_PERFCNT_DUMP, struct drm_panfrost_perfcnt_dump)
#define PANFROST_JD_REQ_FS (1 << 0)
#define PANFROST_JD_REQ_CYCLE_COUNT (1 << 1)
/**
* struct drm_panfrost_submit - ioctl argument for submitting commands to the 3D
* engine.
*
* This asks the kernel to have the GPU execute a render command list.
*/
struct drm_panfrost_submit {
/** Address to GPU mapping of job descriptor */
__u64 jc;
/** An optional array of sync objects to wait on before starting this job. */
__u64 in_syncs;
/** Number of sync objects to wait on before starting this job. */
__u32 in_sync_count;
/** An optional sync object to place the completion fence in. */
__u32 out_sync;
/** Pointer to a u32 array of the BOs that are referenced by the job. */
__u64 bo_handles;
/** Number of BO handles passed in (size is that times 4). */
__u32 bo_handle_count;
/** A combination of PANFROST_JD_REQ_* */
__u32 requirements;
};
/**
* struct drm_panfrost_wait_bo - ioctl argument for waiting for
* completion of the last DRM_PANFROST_SUBMIT on a BO.
*
* This is useful for cases where multiple processes might be
* rendering to a BO and you want to wait for all rendering to be
* completed.
*/
struct drm_panfrost_wait_bo {
__u32 handle;
__u32 pad;
__s64 timeout_ns; /* absolute */
};
/* Valid flags to pass to drm_panfrost_create_bo */
#define PANFROST_BO_NOEXEC 1
#define PANFROST_BO_HEAP 2
/**
* struct drm_panfrost_create_bo - ioctl argument for creating Panfrost BOs.
*
* The flags argument is a bit mask of PANFROST_BO_* flags.
*/
struct drm_panfrost_create_bo {
__u32 size;
__u32 flags;
/** Returned GEM handle for the BO. */
__u32 handle;
/* Pad, must be zero-filled. */
__u32 pad;
/**
* Returned offset for the BO in the GPU address space. This offset
* is private to the DRM fd and is valid for the lifetime of the GEM
* handle.
*
* This offset value will always be nonzero, since various HW
* units treat 0 specially.
*/
__u64 offset;
};
/**
* struct drm_panfrost_mmap_bo - ioctl argument for mapping Panfrost BOs.
*
* This doesn't actually perform an mmap. Instead, it returns the
* offset you need to use in an mmap on the DRM device node. This
* means that tools like valgrind end up knowing about the mapped
* memory.
*
* There are currently no values for the flags argument, but it may be
* used in a future extension.
*/
struct drm_panfrost_mmap_bo {
/** Handle for the object being mapped. */
__u32 handle;
__u32 flags;
/** offset into the drm node to use for subsequent mmap call. */
__u64 offset;
};
enum drm_panfrost_param {
DRM_PANFROST_PARAM_GPU_PROD_ID,
DRM_PANFROST_PARAM_GPU_REVISION,
DRM_PANFROST_PARAM_SHADER_PRESENT,
DRM_PANFROST_PARAM_TILER_PRESENT,
DRM_PANFROST_PARAM_L2_PRESENT,
DRM_PANFROST_PARAM_STACK_PRESENT,
DRM_PANFROST_PARAM_AS_PRESENT,
DRM_PANFROST_PARAM_JS_PRESENT,
DRM_PANFROST_PARAM_L2_FEATURES,
DRM_PANFROST_PARAM_CORE_FEATURES,
DRM_PANFROST_PARAM_TILER_FEATURES,
DRM_PANFROST_PARAM_MEM_FEATURES,
DRM_PANFROST_PARAM_MMU_FEATURES,
DRM_PANFROST_PARAM_THREAD_FEATURES,
DRM_PANFROST_PARAM_MAX_THREADS,
DRM_PANFROST_PARAM_THREAD_MAX_WORKGROUP_SZ,
DRM_PANFROST_PARAM_THREAD_MAX_BARRIER_SZ,
DRM_PANFROST_PARAM_COHERENCY_FEATURES,
DRM_PANFROST_PARAM_TEXTURE_FEATURES0,
DRM_PANFROST_PARAM_TEXTURE_FEATURES1,
DRM_PANFROST_PARAM_TEXTURE_FEATURES2,
DRM_PANFROST_PARAM_TEXTURE_FEATURES3,
DRM_PANFROST_PARAM_JS_FEATURES0,
DRM_PANFROST_PARAM_JS_FEATURES1,
DRM_PANFROST_PARAM_JS_FEATURES2,
DRM_PANFROST_PARAM_JS_FEATURES3,
DRM_PANFROST_PARAM_JS_FEATURES4,
DRM_PANFROST_PARAM_JS_FEATURES5,
DRM_PANFROST_PARAM_JS_FEATURES6,
DRM_PANFROST_PARAM_JS_FEATURES7,
DRM_PANFROST_PARAM_JS_FEATURES8,
DRM_PANFROST_PARAM_JS_FEATURES9,
DRM_PANFROST_PARAM_JS_FEATURES10,
DRM_PANFROST_PARAM_JS_FEATURES11,
DRM_PANFROST_PARAM_JS_FEATURES12,
DRM_PANFROST_PARAM_JS_FEATURES13,
DRM_PANFROST_PARAM_JS_FEATURES14,
DRM_PANFROST_PARAM_JS_FEATURES15,
DRM_PANFROST_PARAM_NR_CORE_GROUPS,
DRM_PANFROST_PARAM_THREAD_TLS_ALLOC,
DRM_PANFROST_PARAM_AFBC_FEATURES,
DRM_PANFROST_PARAM_SYSTEM_TIMESTAMP,
DRM_PANFROST_PARAM_SYSTEM_TIMESTAMP_FREQUENCY,
};
struct drm_panfrost_get_param {
__u32 param;
__u32 pad;
__u64 value;
};
/**
* Returns the offset for the BO in the GPU address space for this DRM fd.
* This is the same value returned by drm_panfrost_create_bo, if that was called
* from this DRM fd.
*/
struct drm_panfrost_get_bo_offset {
__u32 handle;
__u32 pad;
__u64 offset;
};
struct drm_panfrost_perfcnt_enable {
__u32 enable;
/*
* On bifrost we have 2 sets of counters, this parameter defines the
* one to track.
*/
__u32 counterset;
};
struct drm_panfrost_perfcnt_dump {
__u64 buf_ptr;
};
/* madvise provides a way to tell the kernel in case a buffers contents
* can be discarded under memory pressure, which is useful for userspace
* bo cache where we want to optimistically hold on to buffer allocate
* and potential mmap, but allow the pages to be discarded under memory
* pressure.
*
* Typical usage would involve madvise(DONTNEED) when buffer enters BO
* cache, and madvise(WILLNEED) if trying to recycle buffer from BO cache.
* In the WILLNEED case, 'retained' indicates to userspace whether the
* backing pages still exist.
*/
#define PANFROST_MADV_WILLNEED 0 /* backing pages are needed, status returned in 'retained' */
#define PANFROST_MADV_DONTNEED 1 /* backing pages not needed */
struct drm_panfrost_madvise {
__u32 handle; /* in, GEM handle */
__u32 madv; /* in, PANFROST_MADV_x */
__u32 retained; /* out, whether backing store still exists */
};
/* Definitions for coredump decoding in user space */
#define PANFROSTDUMP_MAJOR 1
#define PANFROSTDUMP_MINOR 0
#define PANFROSTDUMP_MAGIC 0x464E4150 /* PANF */
#define PANFROSTDUMP_BUF_REG 0
#define PANFROSTDUMP_BUF_BOMAP (PANFROSTDUMP_BUF_REG + 1)
#define PANFROSTDUMP_BUF_BO (PANFROSTDUMP_BUF_BOMAP + 1)
#define PANFROSTDUMP_BUF_TRAILER (PANFROSTDUMP_BUF_BO + 1)
/*
* This structure is the native endianness of the dumping machine, tools can
* detect the endianness by looking at the value in 'magic'.
*/
struct panfrost_dump_object_header {
__u32 magic;
__u32 type;
__u32 file_size;
__u32 file_offset;
union {
struct {
__u64 jc;
__u32 gpu_id;
__u32 major;
__u32 minor;
__u64 nbos;
} reghdr;
struct {
__u32 valid;
__u64 iova;
__u32 data[2];
} bomap;
/*
* Force same size in case we want to expand the header
* with new fields and also keep it 512-byte aligned
*/
__u32 sizer[496];
};
};
/* Registers object, an array of these */
struct panfrost_dump_registers {
__u32 reg;
__u32 value;
};
#if defined(__cplusplus)
}
#endif
#endif /* _PANFROST_DRM_H_ */
|
// SPDX-License-Identifier: GPL-2.0-only
//
// rt715-sdca-sdw.c -- rt715 ALSA SoC audio driver
//
// Copyright(c) 2020 Realtek Semiconductor Corp.
//
//
#include <linux/delay.h>
#include <linux/device.h>
#include <linux/mod_devicetable.h>
#include <linux/soundwire/sdw.h>
#include <linux/soundwire/sdw_type.h>
#include <linux/soundwire/sdw_registers.h>
#include <linux/module.h>
#include <linux/pm_runtime.h>
#include <linux/regmap.h>
#include <sound/soc.h>
#include "rt715-sdca.h"
#include "rt715-sdca-sdw.h"
static bool rt715_sdca_readable_register(struct device *dev, unsigned int reg)
{
switch (reg) {
case 0x201a ... 0x2027:
case 0x2029 ... 0x202a:
case 0x202d ... 0x2034:
case 0x2200 ... 0x2204:
case 0x2206 ... 0x2212:
case 0x2230 ... 0x2239:
case 0x2f5b:
case SDW_SDCA_CTL(FUN_MIC_ARRAY, RT715_SDCA_SMPU_TRIG_ST_EN,
RT715_SDCA_SMPU_TRIG_ST_CTRL, CH_00):
return true;
default:
return false;
}
}
static bool rt715_sdca_volatile_register(struct device *dev, unsigned int reg)
{
switch (reg) {
case 0x201b:
case 0x201c:
case 0x201d:
case 0x201f:
case 0x2021:
case 0x2023:
case 0x2230:
case 0x202d ... 0x202f: /* BRA */
case 0x2200 ... 0x2212: /* i2c debug */
case 0x2f07:
case 0x2f1b ... 0x2f1e:
case 0x2f30 ... 0x2f34:
case 0x2f50 ... 0x2f51:
case 0x2f53 ... 0x2f59:
case 0x2f5c ... 0x2f5f:
case SDW_SDCA_CTL(FUN_MIC_ARRAY, RT715_SDCA_SMPU_TRIG_ST_EN,
RT715_SDCA_SMPU_TRIG_ST_CTRL, CH_00): /* VAD Searching status */
return true;
default:
return false;
}
}
static bool rt715_sdca_mbq_readable_register(struct device *dev, unsigned int reg)
{
switch (reg) {
case 0x2000000:
case 0x200002b:
case 0x2000036:
case 0x2000037:
case 0x2000039:
case 0x2000044:
case 0x6100000:
return true;
default:
return false;
}
}
static bool rt715_sdca_mbq_volatile_register(struct device *dev, unsigned int reg)
{
switch (reg) {
case 0x2000000:
return true;
default:
return false;
}
}
static const struct regmap_config rt715_sdca_regmap = {
.reg_bits = 32,
.val_bits = 8,
.readable_reg = rt715_sdca_readable_register,
.volatile_reg = rt715_sdca_volatile_register,
.max_register = 0x43ffffff,
.reg_defaults = rt715_reg_defaults_sdca,
.num_reg_defaults = ARRAY_SIZE(rt715_reg_defaults_sdca),
.cache_type = REGCACHE_MAPLE,
.use_single_read = true,
.use_single_write = true,
};
static const struct regmap_config rt715_sdca_mbq_regmap = {
.name = "sdw-mbq",
.reg_bits = 32,
.val_bits = 16,
.readable_reg = rt715_sdca_mbq_readable_register,
.volatile_reg = rt715_sdca_mbq_volatile_register,
.max_register = 0x43ffffff,
.reg_defaults = rt715_mbq_reg_defaults_sdca,
.num_reg_defaults = ARRAY_SIZE(rt715_mbq_reg_defaults_sdca),
.cache_type = REGCACHE_MAPLE,
.use_single_read = true,
.use_single_write = true,
};
static int rt715_sdca_update_status(struct sdw_slave *slave,
enum sdw_slave_status status)
{
struct rt715_sdca_priv *rt715 = dev_get_drvdata(&slave->dev);
/*
* Perform initialization only if slave status is present and
* hw_init flag is false
*/
if (rt715->hw_init || status != SDW_SLAVE_ATTACHED)
return 0;
/* perform I/O transfers required for Slave initialization */
return rt715_sdca_io_init(&slave->dev, slave);
}
static int rt715_sdca_read_prop(struct sdw_slave *slave)
{
struct sdw_slave_prop *prop = &slave->prop;
int nval, i;
u32 bit;
unsigned long addr;
struct sdw_dpn_prop *dpn;
prop->paging_support = true;
/* first we need to allocate memory for set bits in port lists */
prop->source_ports = 0x50;/* BITMAP: 01010000 */
prop->sink_ports = 0x0; /* BITMAP: 00000000 */
nval = hweight32(prop->source_ports);
prop->src_dpn_prop = devm_kcalloc(&slave->dev, nval,
sizeof(*prop->src_dpn_prop),
GFP_KERNEL);
if (!prop->src_dpn_prop)
return -ENOMEM;
dpn = prop->src_dpn_prop;
i = 0;
addr = prop->source_ports;
for_each_set_bit(bit, &addr, 32) {
dpn[i].num = bit;
dpn[i].simple_ch_prep_sm = true;
dpn[i].ch_prep_timeout = 10;
i++;
}
/* set the timeout values */
prop->clk_stop_timeout = 200;
return 0;
}
static const struct sdw_slave_ops rt715_sdca_slave_ops = {
.read_prop = rt715_sdca_read_prop,
.update_status = rt715_sdca_update_status,
};
static int rt715_sdca_sdw_probe(struct sdw_slave *slave,
const struct sdw_device_id *id)
{
struct regmap *mbq_regmap, *regmap;
/* Regmap Initialization */
mbq_regmap = devm_regmap_init_sdw_mbq(slave, &rt715_sdca_mbq_regmap);
if (IS_ERR(mbq_regmap))
return PTR_ERR(mbq_regmap);
regmap = devm_regmap_init_sdw(slave, &rt715_sdca_regmap);
if (IS_ERR(regmap))
return PTR_ERR(regmap);
return rt715_sdca_init(&slave->dev, mbq_regmap, regmap, slave);
}
static int rt715_sdca_sdw_remove(struct sdw_slave *slave)
{
pm_runtime_disable(&slave->dev);
return 0;
}
static const struct sdw_device_id rt715_sdca_id[] = {
SDW_SLAVE_ENTRY_EXT(0x025d, 0x715, 0x3, 0x1, 0),
SDW_SLAVE_ENTRY_EXT(0x025d, 0x714, 0x3, 0x1, 0),
{},
};
MODULE_DEVICE_TABLE(sdw, rt715_sdca_id);
static int __maybe_unused rt715_dev_suspend(struct device *dev)
{
struct rt715_sdca_priv *rt715 = dev_get_drvdata(dev);
if (!rt715->hw_init)
return 0;
regcache_cache_only(rt715->regmap, true);
regcache_mark_dirty(rt715->regmap);
regcache_cache_only(rt715->mbq_regmap, true);
regcache_mark_dirty(rt715->mbq_regmap);
return 0;
}
#define RT715_PROBE_TIMEOUT 5000
static int __maybe_unused rt715_dev_resume(struct device *dev)
{
struct sdw_slave *slave = dev_to_sdw_dev(dev);
struct rt715_sdca_priv *rt715 = dev_get_drvdata(dev);
unsigned long time;
if (!rt715->first_hw_init)
return 0;
if (!slave->unattach_request)
goto regmap_sync;
time = wait_for_completion_timeout(&slave->initialization_complete,
msecs_to_jiffies(RT715_PROBE_TIMEOUT));
if (!time) {
dev_err(&slave->dev, "%s: Initialization not complete, timed out\n", __func__);
sdw_show_ping_status(slave->bus, true);
return -ETIMEDOUT;
}
regmap_sync:
slave->unattach_request = 0;
regcache_cache_only(rt715->regmap, false);
regcache_sync_region(rt715->regmap,
SDW_SDCA_CTL(FUN_JACK_CODEC, RT715_SDCA_ST_EN, RT715_SDCA_ST_CTRL,
CH_00),
SDW_SDCA_CTL(FUN_MIC_ARRAY, RT715_SDCA_SMPU_TRIG_ST_EN,
RT715_SDCA_SMPU_TRIG_ST_CTRL, CH_00));
regcache_cache_only(rt715->mbq_regmap, false);
regcache_sync_region(rt715->mbq_regmap, 0x2000000, 0x61020ff);
regcache_sync_region(rt715->mbq_regmap,
SDW_SDCA_CTL(FUN_JACK_CODEC, RT715_SDCA_ST_EN, RT715_SDCA_ST_CTRL,
CH_00),
SDW_SDCA_CTL(FUN_MIC_ARRAY, RT715_SDCA_SMPU_TRIG_ST_EN,
RT715_SDCA_SMPU_TRIG_ST_CTRL, CH_00));
return 0;
}
static const struct dev_pm_ops rt715_pm = {
SET_SYSTEM_SLEEP_PM_OPS(rt715_dev_suspend, rt715_dev_resume)
SET_RUNTIME_PM_OPS(rt715_dev_suspend, rt715_dev_resume, NULL)
};
static struct sdw_driver rt715_sdw_driver = {
.driver = {
.name = "rt715-sdca",
.pm = &rt715_pm,
},
.probe = rt715_sdca_sdw_probe,
.remove = rt715_sdca_sdw_remove,
.ops = &rt715_sdca_slave_ops,
.id_table = rt715_sdca_id,
};
module_sdw_driver(rt715_sdw_driver);
MODULE_DESCRIPTION("ASoC RT715 driver SDW SDCA");
MODULE_AUTHOR("Jack Yu <[email protected]>");
MODULE_LICENSE("GPL v2");
|
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2013 Fusion IO. All rights reserved.
*/
#include <linux/types.h>
#include "btrfs-tests.h"
#include "../ctree.h"
#include "../btrfs_inode.h"
#include "../disk-io.h"
#include "../extent_io.h"
#include "../volumes.h"
#include "../compression.h"
#include "../accessors.h"
static void insert_extent(struct btrfs_root *root, u64 start, u64 len,
u64 ram_bytes, u64 offset, u64 disk_bytenr,
u64 disk_len, u32 type, u8 compression, int slot)
{
struct btrfs_path path;
struct btrfs_file_extent_item *fi;
struct extent_buffer *leaf = root->node;
struct btrfs_key key;
u32 value_len = sizeof(struct btrfs_file_extent_item);
if (type == BTRFS_FILE_EXTENT_INLINE)
value_len += len;
memset(&path, 0, sizeof(path));
path.nodes[0] = leaf;
path.slots[0] = slot;
key.objectid = BTRFS_FIRST_FREE_OBJECTID;
key.type = BTRFS_EXTENT_DATA_KEY;
key.offset = start;
/*
* Passing a NULL trans handle is fine here, we have a dummy root eb
* and the tree is a single node (level 0).
*/
btrfs_setup_item_for_insert(NULL, root, &path, &key, value_len);
fi = btrfs_item_ptr(leaf, slot, struct btrfs_file_extent_item);
btrfs_set_file_extent_generation(leaf, fi, 1);
btrfs_set_file_extent_type(leaf, fi, type);
btrfs_set_file_extent_disk_bytenr(leaf, fi, disk_bytenr);
btrfs_set_file_extent_disk_num_bytes(leaf, fi, disk_len);
btrfs_set_file_extent_offset(leaf, fi, offset);
btrfs_set_file_extent_num_bytes(leaf, fi, len);
btrfs_set_file_extent_ram_bytes(leaf, fi, ram_bytes);
btrfs_set_file_extent_compression(leaf, fi, compression);
btrfs_set_file_extent_encryption(leaf, fi, 0);
btrfs_set_file_extent_other_encoding(leaf, fi, 0);
}
static void insert_inode_item_key(struct btrfs_root *root)
{
struct btrfs_path path;
struct extent_buffer *leaf = root->node;
struct btrfs_key key;
u32 value_len = 0;
memset(&path, 0, sizeof(path));
path.nodes[0] = leaf;
path.slots[0] = 0;
key.objectid = BTRFS_INODE_ITEM_KEY;
key.type = BTRFS_INODE_ITEM_KEY;
key.offset = 0;
/*
* Passing a NULL trans handle is fine here, we have a dummy root eb
* and the tree is a single node (level 0).
*/
btrfs_setup_item_for_insert(NULL, root, &path, &key, value_len);
}
/*
* Build the most complicated map of extents the earth has ever seen. We want
* this so we can test all of the corner cases of btrfs_get_extent. Here is a
* diagram of how the extents will look though this may not be possible we still
* want to make sure everything acts normally (the last number is not inclusive)
*
* [0 - 6][ 6 - 4096 ][ 4096 - 4100][4100 - 8195][8195 - 12291]
* [inline][hole but no extent][ hole ][ regular ][regular1 split]
*
* [12291 - 16387][16387 - 24579][24579 - 28675][ 28675 - 32771][32771 - 36867 ]
* [ hole ][regular1 split][ prealloc ][ prealloc1 ][prealloc1 written]
*
* [36867 - 45059][45059 - 53251][53251 - 57347][57347 - 61443][61443- 69635]
* [ prealloc1 ][ compressed ][ compressed1 ][ regular ][ compressed1]
*
* [69635-73731][ 73731 - 86019 ][86019-90115]
* [ regular ][ hole but no extent][ regular ]
*/
static void setup_file_extents(struct btrfs_root *root, u32 sectorsize)
{
int slot = 0;
u64 disk_bytenr = SZ_1M;
u64 offset = 0;
/*
* Tree-checker has strict limits on inline extents that they can only
* exist at file offset 0, thus we can only have one inline file extent
* at most.
*/
insert_extent(root, offset, 6, 6, 0, 0, 0, BTRFS_FILE_EXTENT_INLINE, 0,
slot);
slot++;
offset = sectorsize;
/* Now another hole */
insert_extent(root, offset, 4, 4, 0, 0, 0, BTRFS_FILE_EXTENT_REG, 0,
slot);
slot++;
offset += 4;
/* Now for a regular extent */
insert_extent(root, offset, sectorsize - 1, sectorsize - 1, 0,
disk_bytenr, sectorsize - 1, BTRFS_FILE_EXTENT_REG, 0, slot);
slot++;
disk_bytenr += sectorsize;
offset += sectorsize - 1;
/*
* Now for 3 extents that were split from a hole punch so we test
* offsets properly.
*/
insert_extent(root, offset, sectorsize, 4 * sectorsize, 0, disk_bytenr,
4 * sectorsize, BTRFS_FILE_EXTENT_REG, 0, slot);
slot++;
offset += sectorsize;
insert_extent(root, offset, sectorsize, sectorsize, 0, 0, 0,
BTRFS_FILE_EXTENT_REG, 0, slot);
slot++;
offset += sectorsize;
insert_extent(root, offset, 2 * sectorsize, 4 * sectorsize,
2 * sectorsize, disk_bytenr, 4 * sectorsize,
BTRFS_FILE_EXTENT_REG, 0, slot);
slot++;
offset += 2 * sectorsize;
disk_bytenr += 4 * sectorsize;
/* Now for a unwritten prealloc extent */
insert_extent(root, offset, sectorsize, sectorsize, 0, disk_bytenr,
sectorsize, BTRFS_FILE_EXTENT_PREALLOC, 0, slot);
slot++;
offset += sectorsize;
/*
* We want to jack up disk_bytenr a little more so the em stuff doesn't
* merge our records.
*/
disk_bytenr += 2 * sectorsize;
/*
* Now for a partially written prealloc extent, basically the same as
* the hole punch example above. Ram_bytes never changes when you mark
* extents written btw.
*/
insert_extent(root, offset, sectorsize, 4 * sectorsize, 0, disk_bytenr,
4 * sectorsize, BTRFS_FILE_EXTENT_PREALLOC, 0, slot);
slot++;
offset += sectorsize;
insert_extent(root, offset, sectorsize, 4 * sectorsize, sectorsize,
disk_bytenr, 4 * sectorsize, BTRFS_FILE_EXTENT_REG, 0,
slot);
slot++;
offset += sectorsize;
insert_extent(root, offset, 2 * sectorsize, 4 * sectorsize,
2 * sectorsize, disk_bytenr, 4 * sectorsize,
BTRFS_FILE_EXTENT_PREALLOC, 0, slot);
slot++;
offset += 2 * sectorsize;
disk_bytenr += 4 * sectorsize;
/* Now a normal compressed extent */
insert_extent(root, offset, 2 * sectorsize, 2 * sectorsize, 0,
disk_bytenr, sectorsize, BTRFS_FILE_EXTENT_REG,
BTRFS_COMPRESS_ZLIB, slot);
slot++;
offset += 2 * sectorsize;
/* No merges */
disk_bytenr += 2 * sectorsize;
/* Now a split compressed extent */
insert_extent(root, offset, sectorsize, 4 * sectorsize, 0, disk_bytenr,
sectorsize, BTRFS_FILE_EXTENT_REG,
BTRFS_COMPRESS_ZLIB, slot);
slot++;
offset += sectorsize;
insert_extent(root, offset, sectorsize, sectorsize, 0,
disk_bytenr + sectorsize, sectorsize,
BTRFS_FILE_EXTENT_REG, 0, slot);
slot++;
offset += sectorsize;
insert_extent(root, offset, 2 * sectorsize, 4 * sectorsize,
2 * sectorsize, disk_bytenr, sectorsize,
BTRFS_FILE_EXTENT_REG, BTRFS_COMPRESS_ZLIB, slot);
slot++;
offset += 2 * sectorsize;
disk_bytenr += 2 * sectorsize;
/* Now extents that have a hole but no hole extent */
insert_extent(root, offset, sectorsize, sectorsize, 0, disk_bytenr,
sectorsize, BTRFS_FILE_EXTENT_REG, 0, slot);
slot++;
offset += 4 * sectorsize;
disk_bytenr += sectorsize;
insert_extent(root, offset, sectorsize, sectorsize, 0, disk_bytenr,
sectorsize, BTRFS_FILE_EXTENT_REG, 0, slot);
}
static u32 prealloc_only = 0;
static u32 compressed_only = 0;
static u32 vacancy_only = 0;
static noinline int test_btrfs_get_extent(u32 sectorsize, u32 nodesize)
{
struct btrfs_fs_info *fs_info = NULL;
struct inode *inode = NULL;
struct btrfs_root *root = NULL;
struct extent_map *em = NULL;
u64 orig_start;
u64 disk_bytenr;
u64 offset;
int ret = -ENOMEM;
test_msg("running btrfs_get_extent tests");
inode = btrfs_new_test_inode();
if (!inode) {
test_std_err(TEST_ALLOC_INODE);
return ret;
}
fs_info = btrfs_alloc_dummy_fs_info(nodesize, sectorsize);
if (!fs_info) {
test_std_err(TEST_ALLOC_FS_INFO);
goto out;
}
root = btrfs_alloc_dummy_root(fs_info);
if (IS_ERR(root)) {
test_std_err(TEST_ALLOC_ROOT);
goto out;
}
root->node = alloc_dummy_extent_buffer(fs_info, nodesize);
if (!root->node) {
test_std_err(TEST_ALLOC_ROOT);
goto out;
}
btrfs_set_header_nritems(root->node, 0);
btrfs_set_header_level(root->node, 0);
ret = -EINVAL;
/* First with no extents */
BTRFS_I(inode)->root = root;
em = btrfs_get_extent(BTRFS_I(inode), NULL, 0, sectorsize);
if (IS_ERR(em)) {
em = NULL;
test_err("got an error when we shouldn't have");
goto out;
}
if (em->disk_bytenr != EXTENT_MAP_HOLE) {
test_err("expected a hole, got %llu", em->disk_bytenr);
goto out;
}
free_extent_map(em);
btrfs_drop_extent_map_range(BTRFS_I(inode), 0, (u64)-1, false);
/*
* All of the magic numbers are based on the mapping setup in
* setup_file_extents, so if you change anything there you need to
* update the comment and update the expected values below.
*/
setup_file_extents(root, sectorsize);
em = btrfs_get_extent(BTRFS_I(inode), NULL, 0, (u64)-1);
if (IS_ERR(em)) {
test_err("got an error when we shouldn't have");
goto out;
}
if (em->disk_bytenr != EXTENT_MAP_INLINE) {
test_err("expected an inline, got %llu", em->disk_bytenr);
goto out;
}
/*
* For inline extent, we always round up the em to sectorsize, as
* they are either:
*
* a) a hidden hole
* The range will be zeroed at inline extent read time.
*
* b) a file extent with unaligned bytenr
* Tree checker will reject it.
*/
if (em->start != 0 || em->len != sectorsize) {
test_err(
"unexpected extent wanted start 0 len %u, got start %llu len %llu",
sectorsize, em->start, em->len);
goto out;
}
if (em->flags != 0) {
test_err("unexpected flags set, want 0 have %u", em->flags);
goto out;
}
/*
* We don't test anything else for inline since it doesn't get set
* unless we have a page for it to write into. Maybe we should change
* this?
*/
offset = em->start + em->len;
free_extent_map(em);
em = btrfs_get_extent(BTRFS_I(inode), NULL, offset, sectorsize);
if (IS_ERR(em)) {
test_err("got an error when we shouldn't have");
goto out;
}
if (em->disk_bytenr != EXTENT_MAP_HOLE) {
test_err("expected a hole, got %llu", em->disk_bytenr);
goto out;
}
if (em->start != offset || em->len != 4) {
test_err(
"unexpected extent wanted start %llu len 4, got start %llu len %llu",
offset, em->start, em->len);
goto out;
}
if (em->flags != 0) {
test_err("unexpected flags set, want 0 have %u", em->flags);
goto out;
}
offset = em->start + em->len;
free_extent_map(em);
/* Regular extent */
em = btrfs_get_extent(BTRFS_I(inode), NULL, offset, sectorsize);
if (IS_ERR(em)) {
test_err("got an error when we shouldn't have");
goto out;
}
if (em->disk_bytenr >= EXTENT_MAP_LAST_BYTE) {
test_err("expected a real extent, got %llu", em->disk_bytenr);
goto out;
}
if (em->start != offset || em->len != sectorsize - 1) {
test_err(
"unexpected extent wanted start %llu len 4095, got start %llu len %llu",
offset, em->start, em->len);
goto out;
}
if (em->flags != 0) {
test_err("unexpected flags set, want 0 have %u", em->flags);
goto out;
}
if (em->offset != 0) {
test_err("wrong offset, want 0, have %llu", em->offset);
goto out;
}
offset = em->start + em->len;
free_extent_map(em);
/* The next 3 are split extents */
em = btrfs_get_extent(BTRFS_I(inode), NULL, offset, sectorsize);
if (IS_ERR(em)) {
test_err("got an error when we shouldn't have");
goto out;
}
if (em->disk_bytenr >= EXTENT_MAP_LAST_BYTE) {
test_err("expected a real extent, got %llu", em->disk_bytenr);
goto out;
}
if (em->start != offset || em->len != sectorsize) {
test_err(
"unexpected extent start %llu len %u, got start %llu len %llu",
offset, sectorsize, em->start, em->len);
goto out;
}
if (em->flags != 0) {
test_err("unexpected flags set, want 0 have %u", em->flags);
goto out;
}
if (em->offset != 0) {
test_err("wrong offset, want 0, have %llu", em->offset);
goto out;
}
disk_bytenr = extent_map_block_start(em);
orig_start = em->start;
offset = em->start + em->len;
free_extent_map(em);
em = btrfs_get_extent(BTRFS_I(inode), NULL, offset, sectorsize);
if (IS_ERR(em)) {
test_err("got an error when we shouldn't have");
goto out;
}
if (em->disk_bytenr != EXTENT_MAP_HOLE) {
test_err("expected a hole, got %llu", em->disk_bytenr);
goto out;
}
if (em->start != offset || em->len != sectorsize) {
test_err(
"unexpected extent wanted start %llu len %u, got start %llu len %llu",
offset, sectorsize, em->start, em->len);
goto out;
}
if (em->flags != 0) {
test_err("unexpected flags set, want 0 have %u", em->flags);
goto out;
}
offset = em->start + em->len;
free_extent_map(em);
em = btrfs_get_extent(BTRFS_I(inode), NULL, offset, sectorsize);
if (IS_ERR(em)) {
test_err("got an error when we shouldn't have");
goto out;
}
if (em->disk_bytenr >= EXTENT_MAP_LAST_BYTE) {
test_err("expected a real extent, got %llu", em->disk_bytenr);
goto out;
}
if (em->start != offset || em->len != 2 * sectorsize) {
test_err(
"unexpected extent wanted start %llu len %u, got start %llu len %llu",
offset, 2 * sectorsize, em->start, em->len);
goto out;
}
if (em->flags != 0) {
test_err("unexpected flags set, want 0 have %u", em->flags);
goto out;
}
if (em->start - em->offset != orig_start) {
test_err("wrong offset, em->start=%llu em->offset=%llu orig_start=%llu",
em->start, em->offset, orig_start);
goto out;
}
disk_bytenr += (em->start - orig_start);
if (extent_map_block_start(em) != disk_bytenr) {
test_err("wrong block start, want %llu, have %llu",
disk_bytenr, extent_map_block_start(em));
goto out;
}
offset = em->start + em->len;
free_extent_map(em);
/* Prealloc extent */
em = btrfs_get_extent(BTRFS_I(inode), NULL, offset, sectorsize);
if (IS_ERR(em)) {
test_err("got an error when we shouldn't have");
goto out;
}
if (em->disk_bytenr >= EXTENT_MAP_LAST_BYTE) {
test_err("expected a real extent, got %llu", em->disk_bytenr);
goto out;
}
if (em->start != offset || em->len != sectorsize) {
test_err(
"unexpected extent wanted start %llu len %u, got start %llu len %llu",
offset, sectorsize, em->start, em->len);
goto out;
}
if (em->flags != prealloc_only) {
test_err("unexpected flags set, want %u have %u",
prealloc_only, em->flags);
goto out;
}
if (em->offset != 0) {
test_err("wrong offset, want 0, have %llu", em->offset);
goto out;
}
offset = em->start + em->len;
free_extent_map(em);
/* The next 3 are a half written prealloc extent */
em = btrfs_get_extent(BTRFS_I(inode), NULL, offset, sectorsize);
if (IS_ERR(em)) {
test_err("got an error when we shouldn't have");
goto out;
}
if (em->disk_bytenr >= EXTENT_MAP_LAST_BYTE) {
test_err("expected a real extent, got %llu", em->disk_bytenr);
goto out;
}
if (em->start != offset || em->len != sectorsize) {
test_err(
"unexpected extent wanted start %llu len %u, got start %llu len %llu",
offset, sectorsize, em->start, em->len);
goto out;
}
if (em->flags != prealloc_only) {
test_err("unexpected flags set, want %u have %u",
prealloc_only, em->flags);
goto out;
}
if (em->offset != 0) {
test_err("wrong offset, want 0, have %llu", em->offset);
goto out;
}
disk_bytenr = extent_map_block_start(em);
orig_start = em->start;
offset = em->start + em->len;
free_extent_map(em);
em = btrfs_get_extent(BTRFS_I(inode), NULL, offset, sectorsize);
if (IS_ERR(em)) {
test_err("got an error when we shouldn't have");
goto out;
}
if (em->disk_bytenr >= EXTENT_MAP_HOLE) {
test_err("expected a real extent, got %llu", em->disk_bytenr);
goto out;
}
if (em->start != offset || em->len != sectorsize) {
test_err(
"unexpected extent wanted start %llu len %u, got start %llu len %llu",
offset, sectorsize, em->start, em->len);
goto out;
}
if (em->flags != 0) {
test_err("unexpected flags set, want 0 have %u", em->flags);
goto out;
}
if (em->start - em->offset != orig_start) {
test_err("unexpected offset, wanted %llu, have %llu",
em->start - orig_start, em->offset);
goto out;
}
if (extent_map_block_start(em) != disk_bytenr + em->offset) {
test_err("unexpected block start, wanted %llu, have %llu",
disk_bytenr + em->offset, extent_map_block_start(em));
goto out;
}
offset = em->start + em->len;
free_extent_map(em);
em = btrfs_get_extent(BTRFS_I(inode), NULL, offset, sectorsize);
if (IS_ERR(em)) {
test_err("got an error when we shouldn't have");
goto out;
}
if (em->disk_bytenr >= EXTENT_MAP_LAST_BYTE) {
test_err("expected a real extent, got %llu", em->disk_bytenr);
goto out;
}
if (em->start != offset || em->len != 2 * sectorsize) {
test_err(
"unexpected extent wanted start %llu len %u, got start %llu len %llu",
offset, 2 * sectorsize, em->start, em->len);
goto out;
}
if (em->flags != prealloc_only) {
test_err("unexpected flags set, want %u have %u",
prealloc_only, em->flags);
goto out;
}
if (em->start - em->offset != orig_start) {
test_err("wrong offset, em->start=%llu em->offset=%llu orig_start=%llu",
em->start, em->offset, orig_start);
goto out;
}
if (extent_map_block_start(em) != disk_bytenr + em->offset) {
test_err("unexpected block start, wanted %llu, have %llu",
disk_bytenr + em->offset, extent_map_block_start(em));
goto out;
}
offset = em->start + em->len;
free_extent_map(em);
/* Now for the compressed extent */
em = btrfs_get_extent(BTRFS_I(inode), NULL, offset, sectorsize);
if (IS_ERR(em)) {
test_err("got an error when we shouldn't have");
goto out;
}
if (em->disk_bytenr >= EXTENT_MAP_LAST_BYTE) {
test_err("expected a real extent, got %llu", em->disk_bytenr);
goto out;
}
if (em->start != offset || em->len != 2 * sectorsize) {
test_err(
"unexpected extent wanted start %llu len %u, got start %llu len %llu",
offset, 2 * sectorsize, em->start, em->len);
goto out;
}
if (em->flags != compressed_only) {
test_err("unexpected flags set, want %u have %u",
compressed_only, em->flags);
goto out;
}
if (em->offset != 0) {
test_err("wrong offset, want 0, have %llu", em->offset);
goto out;
}
if (extent_map_compression(em) != BTRFS_COMPRESS_ZLIB) {
test_err("unexpected compress type, wanted %d, got %d",
BTRFS_COMPRESS_ZLIB, extent_map_compression(em));
goto out;
}
offset = em->start + em->len;
free_extent_map(em);
/* Split compressed extent */
em = btrfs_get_extent(BTRFS_I(inode), NULL, offset, sectorsize);
if (IS_ERR(em)) {
test_err("got an error when we shouldn't have");
goto out;
}
if (em->disk_bytenr >= EXTENT_MAP_LAST_BYTE) {
test_err("expected a real extent, got %llu", em->disk_bytenr);
goto out;
}
if (em->start != offset || em->len != sectorsize) {
test_err(
"unexpected extent wanted start %llu len %u, got start %llu len %llu",
offset, sectorsize, em->start, em->len);
goto out;
}
if (em->flags != compressed_only) {
test_err("unexpected flags set, want %u have %u",
compressed_only, em->flags);
goto out;
}
if (em->offset != 0) {
test_err("wrong offset, want 0, have %llu", em->offset);
goto out;
}
if (extent_map_compression(em) != BTRFS_COMPRESS_ZLIB) {
test_err("unexpected compress type, wanted %d, got %d",
BTRFS_COMPRESS_ZLIB, extent_map_compression(em));
goto out;
}
disk_bytenr = extent_map_block_start(em);
orig_start = em->start;
offset = em->start + em->len;
free_extent_map(em);
em = btrfs_get_extent(BTRFS_I(inode), NULL, offset, sectorsize);
if (IS_ERR(em)) {
test_err("got an error when we shouldn't have");
goto out;
}
if (em->disk_bytenr >= EXTENT_MAP_LAST_BYTE) {
test_err("expected a real extent, got %llu", em->disk_bytenr);
goto out;
}
if (em->start != offset || em->len != sectorsize) {
test_err(
"unexpected extent wanted start %llu len %u, got start %llu len %llu",
offset, sectorsize, em->start, em->len);
goto out;
}
if (em->flags != 0) {
test_err("unexpected flags set, want 0 have %u", em->flags);
goto out;
}
if (em->offset != 0) {
test_err("wrong offset, want 0, have %llu", em->offset);
goto out;
}
offset = em->start + em->len;
free_extent_map(em);
em = btrfs_get_extent(BTRFS_I(inode), NULL, offset, sectorsize);
if (IS_ERR(em)) {
test_err("got an error when we shouldn't have");
goto out;
}
if (extent_map_block_start(em) != disk_bytenr) {
test_err("block start does not match, want %llu got %llu",
disk_bytenr, extent_map_block_start(em));
goto out;
}
if (em->start != offset || em->len != 2 * sectorsize) {
test_err(
"unexpected extent wanted start %llu len %u, got start %llu len %llu",
offset, 2 * sectorsize, em->start, em->len);
goto out;
}
if (em->flags != compressed_only) {
test_err("unexpected flags set, want %u have %u",
compressed_only, em->flags);
goto out;
}
if (em->start - em->offset != orig_start) {
test_err("wrong offset, em->start=%llu em->offset=%llu orig_start=%llu",
em->start, em->offset, orig_start);
goto out;
}
if (extent_map_compression(em) != BTRFS_COMPRESS_ZLIB) {
test_err("unexpected compress type, wanted %d, got %d",
BTRFS_COMPRESS_ZLIB, extent_map_compression(em));
goto out;
}
offset = em->start + em->len;
free_extent_map(em);
/* A hole between regular extents but no hole extent */
em = btrfs_get_extent(BTRFS_I(inode), NULL, offset + 6, sectorsize);
if (IS_ERR(em)) {
test_err("got an error when we shouldn't have");
goto out;
}
if (em->disk_bytenr >= EXTENT_MAP_LAST_BYTE) {
test_err("expected a real extent, got %llu", em->disk_bytenr);
goto out;
}
if (em->start != offset || em->len != sectorsize) {
test_err(
"unexpected extent wanted start %llu len %u, got start %llu len %llu",
offset, sectorsize, em->start, em->len);
goto out;
}
if (em->flags != 0) {
test_err("unexpected flags set, want 0 have %u", em->flags);
goto out;
}
if (em->offset != 0) {
test_err("wrong offset, want 0, have %llu", em->offset);
goto out;
}
offset = em->start + em->len;
free_extent_map(em);
em = btrfs_get_extent(BTRFS_I(inode), NULL, offset, SZ_4M);
if (IS_ERR(em)) {
test_err("got an error when we shouldn't have");
goto out;
}
if (em->disk_bytenr != EXTENT_MAP_HOLE) {
test_err("expected a hole extent, got %llu", em->disk_bytenr);
goto out;
}
/*
* Currently we just return a length that we requested rather than the
* length of the actual hole, if this changes we'll have to change this
* test.
*/
if (em->start != offset || em->len != 3 * sectorsize) {
test_err(
"unexpected extent wanted start %llu len %u, got start %llu len %llu",
offset, 3 * sectorsize, em->start, em->len);
goto out;
}
if (em->flags != vacancy_only) {
test_err("unexpected flags set, want %u have %u",
vacancy_only, em->flags);
goto out;
}
if (em->offset != 0) {
test_err("wrong offset, want 0, have %llu", em->offset);
goto out;
}
offset = em->start + em->len;
free_extent_map(em);
em = btrfs_get_extent(BTRFS_I(inode), NULL, offset, sectorsize);
if (IS_ERR(em)) {
test_err("got an error when we shouldn't have");
goto out;
}
if (em->disk_bytenr >= EXTENT_MAP_LAST_BYTE) {
test_err("expected a real extent, got %llu", em->disk_bytenr);
goto out;
}
if (em->start != offset || em->len != sectorsize) {
test_err(
"unexpected extent wanted start %llu len %u, got start %llu len %llu",
offset, sectorsize, em->start, em->len);
goto out;
}
if (em->flags != 0) {
test_err("unexpected flags set, want 0 have %u", em->flags);
goto out;
}
if (em->offset != 0) {
test_err("wrong orig offset, want 0, have %llu", em->offset);
goto out;
}
ret = 0;
out:
if (!IS_ERR(em))
free_extent_map(em);
iput(inode);
btrfs_free_dummy_root(root);
btrfs_free_dummy_fs_info(fs_info);
return ret;
}
static int test_hole_first(u32 sectorsize, u32 nodesize)
{
struct btrfs_fs_info *fs_info = NULL;
struct inode *inode = NULL;
struct btrfs_root *root = NULL;
struct extent_map *em = NULL;
int ret = -ENOMEM;
test_msg("running hole first btrfs_get_extent test");
inode = btrfs_new_test_inode();
if (!inode) {
test_std_err(TEST_ALLOC_INODE);
return ret;
}
fs_info = btrfs_alloc_dummy_fs_info(nodesize, sectorsize);
if (!fs_info) {
test_std_err(TEST_ALLOC_FS_INFO);
goto out;
}
root = btrfs_alloc_dummy_root(fs_info);
if (IS_ERR(root)) {
test_std_err(TEST_ALLOC_ROOT);
goto out;
}
root->node = alloc_dummy_extent_buffer(fs_info, nodesize);
if (!root->node) {
test_std_err(TEST_ALLOC_ROOT);
goto out;
}
btrfs_set_header_nritems(root->node, 0);
btrfs_set_header_level(root->node, 0);
BTRFS_I(inode)->root = root;
ret = -EINVAL;
/*
* Need a blank inode item here just so we don't confuse
* btrfs_get_extent.
*/
insert_inode_item_key(root);
insert_extent(root, sectorsize, sectorsize, sectorsize, 0, sectorsize,
sectorsize, BTRFS_FILE_EXTENT_REG, 0, 1);
em = btrfs_get_extent(BTRFS_I(inode), NULL, 0, 2 * sectorsize);
if (IS_ERR(em)) {
test_err("got an error when we shouldn't have");
goto out;
}
if (em->disk_bytenr != EXTENT_MAP_HOLE) {
test_err("expected a hole, got %llu", em->disk_bytenr);
goto out;
}
if (em->start != 0 || em->len != sectorsize) {
test_err(
"unexpected extent wanted start 0 len %u, got start %llu len %llu",
sectorsize, em->start, em->len);
goto out;
}
if (em->flags != vacancy_only) {
test_err("wrong flags, wanted %u, have %u", vacancy_only,
em->flags);
goto out;
}
free_extent_map(em);
em = btrfs_get_extent(BTRFS_I(inode), NULL, sectorsize, 2 * sectorsize);
if (IS_ERR(em)) {
test_err("got an error when we shouldn't have");
goto out;
}
if (extent_map_block_start(em) != sectorsize) {
test_err("expected a real extent, got %llu", extent_map_block_start(em));
goto out;
}
if (em->start != sectorsize || em->len != sectorsize) {
test_err(
"unexpected extent wanted start %u len %u, got start %llu len %llu",
sectorsize, sectorsize, em->start, em->len);
goto out;
}
if (em->flags != 0) {
test_err("unexpected flags set, wanted 0 got %u",
em->flags);
goto out;
}
ret = 0;
out:
if (!IS_ERR(em))
free_extent_map(em);
iput(inode);
btrfs_free_dummy_root(root);
btrfs_free_dummy_fs_info(fs_info);
return ret;
}
static int test_extent_accounting(u32 sectorsize, u32 nodesize)
{
struct btrfs_fs_info *fs_info = NULL;
struct inode *inode = NULL;
struct btrfs_root *root = NULL;
int ret = -ENOMEM;
test_msg("running outstanding_extents tests");
inode = btrfs_new_test_inode();
if (!inode) {
test_std_err(TEST_ALLOC_INODE);
return ret;
}
fs_info = btrfs_alloc_dummy_fs_info(nodesize, sectorsize);
if (!fs_info) {
test_std_err(TEST_ALLOC_FS_INFO);
goto out;
}
root = btrfs_alloc_dummy_root(fs_info);
if (IS_ERR(root)) {
test_std_err(TEST_ALLOC_ROOT);
goto out;
}
BTRFS_I(inode)->root = root;
/* [BTRFS_MAX_EXTENT_SIZE] */
ret = btrfs_set_extent_delalloc(BTRFS_I(inode), 0,
BTRFS_MAX_EXTENT_SIZE - 1, 0, NULL);
if (ret) {
test_err("btrfs_set_extent_delalloc returned %d", ret);
goto out;
}
if (BTRFS_I(inode)->outstanding_extents != 1) {
ret = -EINVAL;
test_err("miscount, wanted 1, got %u",
BTRFS_I(inode)->outstanding_extents);
goto out;
}
/* [BTRFS_MAX_EXTENT_SIZE][sectorsize] */
ret = btrfs_set_extent_delalloc(BTRFS_I(inode), BTRFS_MAX_EXTENT_SIZE,
BTRFS_MAX_EXTENT_SIZE + sectorsize - 1,
0, NULL);
if (ret) {
test_err("btrfs_set_extent_delalloc returned %d", ret);
goto out;
}
if (BTRFS_I(inode)->outstanding_extents != 2) {
ret = -EINVAL;
test_err("miscount, wanted 2, got %u",
BTRFS_I(inode)->outstanding_extents);
goto out;
}
/* [BTRFS_MAX_EXTENT_SIZE/2][sectorsize HOLE][the rest] */
ret = clear_extent_bit(&BTRFS_I(inode)->io_tree,
BTRFS_MAX_EXTENT_SIZE >> 1,
(BTRFS_MAX_EXTENT_SIZE >> 1) + sectorsize - 1,
EXTENT_DELALLOC | EXTENT_DELALLOC_NEW |
EXTENT_UPTODATE, NULL);
if (ret) {
test_err("clear_extent_bit returned %d", ret);
goto out;
}
if (BTRFS_I(inode)->outstanding_extents != 2) {
ret = -EINVAL;
test_err("miscount, wanted 2, got %u",
BTRFS_I(inode)->outstanding_extents);
goto out;
}
/* [BTRFS_MAX_EXTENT_SIZE][sectorsize] */
ret = btrfs_set_extent_delalloc(BTRFS_I(inode), BTRFS_MAX_EXTENT_SIZE >> 1,
(BTRFS_MAX_EXTENT_SIZE >> 1)
+ sectorsize - 1,
0, NULL);
if (ret) {
test_err("btrfs_set_extent_delalloc returned %d", ret);
goto out;
}
if (BTRFS_I(inode)->outstanding_extents != 2) {
ret = -EINVAL;
test_err("miscount, wanted 2, got %u",
BTRFS_I(inode)->outstanding_extents);
goto out;
}
/*
* [BTRFS_MAX_EXTENT_SIZE+sectorsize][sectorsize HOLE][BTRFS_MAX_EXTENT_SIZE+sectorsize]
*/
ret = btrfs_set_extent_delalloc(BTRFS_I(inode),
BTRFS_MAX_EXTENT_SIZE + 2 * sectorsize,
(BTRFS_MAX_EXTENT_SIZE << 1) + 3 * sectorsize - 1,
0, NULL);
if (ret) {
test_err("btrfs_set_extent_delalloc returned %d", ret);
goto out;
}
if (BTRFS_I(inode)->outstanding_extents != 4) {
ret = -EINVAL;
test_err("miscount, wanted 4, got %u",
BTRFS_I(inode)->outstanding_extents);
goto out;
}
/*
* [BTRFS_MAX_EXTENT_SIZE+sectorsize][sectorsize][BTRFS_MAX_EXTENT_SIZE+sectorsize]
*/
ret = btrfs_set_extent_delalloc(BTRFS_I(inode),
BTRFS_MAX_EXTENT_SIZE + sectorsize,
BTRFS_MAX_EXTENT_SIZE + 2 * sectorsize - 1, 0, NULL);
if (ret) {
test_err("btrfs_set_extent_delalloc returned %d", ret);
goto out;
}
if (BTRFS_I(inode)->outstanding_extents != 3) {
ret = -EINVAL;
test_err("miscount, wanted 3, got %u",
BTRFS_I(inode)->outstanding_extents);
goto out;
}
/* [BTRFS_MAX_EXTENT_SIZE+4k][4K HOLE][BTRFS_MAX_EXTENT_SIZE+4k] */
ret = clear_extent_bit(&BTRFS_I(inode)->io_tree,
BTRFS_MAX_EXTENT_SIZE + sectorsize,
BTRFS_MAX_EXTENT_SIZE + 2 * sectorsize - 1,
EXTENT_DELALLOC | EXTENT_DELALLOC_NEW |
EXTENT_UPTODATE, NULL);
if (ret) {
test_err("clear_extent_bit returned %d", ret);
goto out;
}
if (BTRFS_I(inode)->outstanding_extents != 4) {
ret = -EINVAL;
test_err("miscount, wanted 4, got %u",
BTRFS_I(inode)->outstanding_extents);
goto out;
}
/*
* Refill the hole again just for good measure, because I thought it
* might fail and I'd rather satisfy my paranoia at this point.
*/
ret = btrfs_set_extent_delalloc(BTRFS_I(inode),
BTRFS_MAX_EXTENT_SIZE + sectorsize,
BTRFS_MAX_EXTENT_SIZE + 2 * sectorsize - 1, 0, NULL);
if (ret) {
test_err("btrfs_set_extent_delalloc returned %d", ret);
goto out;
}
if (BTRFS_I(inode)->outstanding_extents != 3) {
ret = -EINVAL;
test_err("miscount, wanted 3, got %u",
BTRFS_I(inode)->outstanding_extents);
goto out;
}
/* Empty */
ret = clear_extent_bit(&BTRFS_I(inode)->io_tree, 0, (u64)-1,
EXTENT_DELALLOC | EXTENT_DELALLOC_NEW |
EXTENT_UPTODATE, NULL);
if (ret) {
test_err("clear_extent_bit returned %d", ret);
goto out;
}
if (BTRFS_I(inode)->outstanding_extents) {
ret = -EINVAL;
test_err("miscount, wanted 0, got %u",
BTRFS_I(inode)->outstanding_extents);
goto out;
}
ret = 0;
out:
if (ret)
clear_extent_bit(&BTRFS_I(inode)->io_tree, 0, (u64)-1,
EXTENT_DELALLOC | EXTENT_DELALLOC_NEW |
EXTENT_UPTODATE, NULL);
iput(inode);
btrfs_free_dummy_root(root);
btrfs_free_dummy_fs_info(fs_info);
return ret;
}
int btrfs_test_inodes(u32 sectorsize, u32 nodesize)
{
int ret;
test_msg("running inode tests");
compressed_only |= EXTENT_FLAG_COMPRESS_ZLIB;
prealloc_only |= EXTENT_FLAG_PREALLOC;
ret = test_btrfs_get_extent(sectorsize, nodesize);
if (ret)
return ret;
ret = test_hole_first(sectorsize, nodesize);
if (ret)
return ret;
return test_extent_accounting(sectorsize, nodesize);
}
|
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright 2011 Freescale Semiconductor, Inc.
* Copyright 2011 Linaro Ltd.
*/
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include "imx6q.dtsi"
/ {
model = "Freescale i.MX6 Quad Armadillo2 Board";
compatible = "fsl,imx6q-arm2", "fsl,imx6q";
memory@10000000 {
device_type = "memory";
reg = <0x10000000 0x80000000>;
};
reg_3p3v: regulator-3p3v {
compatible = "regulator-fixed";
regulator-name = "3P3V";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
reg_usb_otg_vbus: regulator-usb-otg-vbus {
compatible = "regulator-fixed";
regulator-name = "usb_otg_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&gpio3 22 0>;
enable-active-high;
};
leds {
compatible = "gpio-leds";
debug-led {
label = "Heartbeat";
gpios = <&gpio3 25 0>;
linux,default-trigger = "heartbeat";
};
};
};
&gpmi {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpmi_nand>;
status = "disabled"; /* gpmi nand conflicts with SD */
};
&iomuxc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hog>;
pinctrl_hog: hoggrp {
fsl,pins = <
MX6QDL_PAD_EIM_D25__GPIO3_IO25 0x80000000
>;
};
pinctrl_enet: enetgrp {
fsl,pins = <
MX6QDL_PAD_KEY_COL1__ENET_MDIO 0x1b0b0
MX6QDL_PAD_KEY_COL2__ENET_MDC 0x1b0b0
MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030
MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1
>;
};
pinctrl_gpmi_nand: gpminandgrp {
fsl,pins = <
MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1
MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
MX6QDL_PAD_SD4_DAT0__NAND_DQS 0x00b1
>;
};
pinctrl_uart2: uart2grp {
fsl,pins = <
MX6QDL_PAD_EIM_D26__UART2_RX_DATA 0x1b0b1
MX6QDL_PAD_EIM_D27__UART2_TX_DATA 0x1b0b1
MX6QDL_PAD_EIM_D28__UART2_DTE_CTS_B 0x1b0b1
MX6QDL_PAD_EIM_D29__UART2_DTE_RTS_B 0x1b0b1
>;
};
pinctrl_uart4: uart4grp {
fsl,pins = <
MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1
MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1
>;
};
pinctrl_usbotg: usbotggrp {
fsl,pins = <
MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
>;
};
pinctrl_usdhc3: usdhc3grp {
fsl,pins = <
MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059
MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059
MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059
MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059
>;
};
pinctrl_usdhc3_cdwp: usdhc3cdwpgrp {
fsl,pins = <
MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x80000000
MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x80000000
>;
};
pinctrl_usdhc4: usdhc4grp {
fsl,pins = <
MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059
MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059
MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059
MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059
MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059
MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059
MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059
MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059
MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059
MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059
>;
};
};
&fec {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet>;
phy-mode = "rgmii";
/delete-property/ interrupts;
interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>,
<&intc 0 119 IRQ_TYPE_LEVEL_HIGH>;
fsl,err006687-workaround-present;
status = "okay";
};
&usbotg {
vbus-supply = <®_usb_otg_vbus>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbotg>;
disable-over-current;
status = "okay";
};
&usdhc3 {
cd-gpios = <&gpio6 11 GPIO_ACTIVE_LOW>;
wp-gpios = <&gpio6 14 GPIO_ACTIVE_HIGH>;
vmmc-supply = <®_3p3v>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc3
&pinctrl_usdhc3_cdwp>;
status = "okay";
};
&usdhc4 {
non-removable;
vmmc-supply = <®_3p3v>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc4>;
status = "okay";
};
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
fsl,dte-mode;
uart-has-rtscts;
status = "okay";
};
&uart4 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart4>;
status = "okay";
};
|
/* SPDX-License-Identifier: ((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause) */
/*
* Copyright (C) 2020-2021 OpenSynergy GmbH
* Copyright (C) 2021 ARM Ltd.
*/
#ifndef _UAPI_LINUX_VIRTIO_SCMI_H
#define _UAPI_LINUX_VIRTIO_SCMI_H
#include <linux/virtio_types.h>
/* Device implements some SCMI notifications, or delayed responses. */
#define VIRTIO_SCMI_F_P2A_CHANNELS 0
/* Device implements any SCMI statistics shared memory region */
#define VIRTIO_SCMI_F_SHARED_MEMORY 1
/* Virtqueues */
#define VIRTIO_SCMI_VQ_TX 0 /* cmdq */
#define VIRTIO_SCMI_VQ_RX 1 /* eventq */
#define VIRTIO_SCMI_VQ_MAX_CNT 2
#endif /* _UAPI_LINUX_VIRTIO_SCMI_H */
|
// SPDX-License-Identifier: GPL-2.0-only
/* (C) 1999-2001 Paul `Rusty' Russell
* (C) 2002-2004 Netfilter Core Team <[email protected]>
*/
#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/spinlock.h>
#include <linux/skbuff.h>
#include <linux/if_arp.h>
#include <linux/ip.h>
#include <net/ipv6.h>
#include <net/icmp.h>
#include <net/udp.h>
#include <net/tcp.h>
#include <net/route.h>
#include <linux/netfilter.h>
#include <linux/netfilter_bridge.h>
#include <linux/netfilter_ipv6.h>
#include <linux/netfilter/xt_LOG.h>
#include <net/netfilter/nf_log.h>
static const struct nf_loginfo default_loginfo = {
.type = NF_LOG_TYPE_LOG,
.u = {
.log = {
.level = LOGLEVEL_NOTICE,
.logflags = NF_LOG_DEFAULT_MASK,
},
},
};
struct arppayload {
unsigned char mac_src[ETH_ALEN];
unsigned char ip_src[4];
unsigned char mac_dst[ETH_ALEN];
unsigned char ip_dst[4];
};
/* Guard against containers flooding syslog. */
static bool nf_log_allowed(const struct net *net)
{
return net_eq(net, &init_net) || sysctl_nf_log_all_netns;
}
static void nf_log_dump_vlan(struct nf_log_buf *m, const struct sk_buff *skb)
{
u16 vid;
if (!skb_vlan_tag_present(skb))
return;
vid = skb_vlan_tag_get(skb);
nf_log_buf_add(m, "VPROTO=%04x VID=%u ", ntohs(skb->vlan_proto), vid);
}
static void noinline_for_stack
dump_arp_packet(struct nf_log_buf *m,
const struct nf_loginfo *info,
const struct sk_buff *skb, unsigned int nhoff)
{
const struct arppayload *ap;
struct arppayload _arpp;
const struct arphdr *ah;
unsigned int logflags;
struct arphdr _arph;
ah = skb_header_pointer(skb, nhoff, sizeof(_arph), &_arph);
if (!ah) {
nf_log_buf_add(m, "TRUNCATED");
return;
}
if (info->type == NF_LOG_TYPE_LOG)
logflags = info->u.log.logflags;
else
logflags = NF_LOG_DEFAULT_MASK;
if (logflags & NF_LOG_MACDECODE) {
nf_log_buf_add(m, "MACSRC=%pM MACDST=%pM ",
eth_hdr(skb)->h_source, eth_hdr(skb)->h_dest);
nf_log_dump_vlan(m, skb);
nf_log_buf_add(m, "MACPROTO=%04x ",
ntohs(eth_hdr(skb)->h_proto));
}
nf_log_buf_add(m, "ARP HTYPE=%d PTYPE=0x%04x OPCODE=%d",
ntohs(ah->ar_hrd), ntohs(ah->ar_pro), ntohs(ah->ar_op));
/* If it's for Ethernet and the lengths are OK, then log the ARP
* payload.
*/
if (ah->ar_hrd != htons(ARPHRD_ETHER) ||
ah->ar_hln != ETH_ALEN ||
ah->ar_pln != sizeof(__be32))
return;
ap = skb_header_pointer(skb, nhoff + sizeof(_arph), sizeof(_arpp), &_arpp);
if (!ap) {
nf_log_buf_add(m, " INCOMPLETE [%zu bytes]",
skb->len - sizeof(_arph));
return;
}
nf_log_buf_add(m, " MACSRC=%pM IPSRC=%pI4 MACDST=%pM IPDST=%pI4",
ap->mac_src, ap->ip_src, ap->mac_dst, ap->ip_dst);
}
static void
nf_log_dump_packet_common(struct nf_log_buf *m, u8 pf,
unsigned int hooknum, const struct sk_buff *skb,
const struct net_device *in,
const struct net_device *out,
const struct nf_loginfo *loginfo, const char *prefix,
struct net *net)
{
const struct net_device *physoutdev __maybe_unused;
const struct net_device *physindev __maybe_unused;
nf_log_buf_add(m, KERN_SOH "%c%sIN=%s OUT=%s ",
'0' + loginfo->u.log.level, prefix,
in ? in->name : "",
out ? out->name : "");
#if IS_ENABLED(CONFIG_BRIDGE_NETFILTER)
physindev = nf_bridge_get_physindev(skb, net);
if (physindev && in != physindev)
nf_log_buf_add(m, "PHYSIN=%s ", physindev->name);
physoutdev = nf_bridge_get_physoutdev(skb);
if (physoutdev && out != physoutdev)
nf_log_buf_add(m, "PHYSOUT=%s ", physoutdev->name);
#endif
}
static void nf_log_arp_packet(struct net *net, u_int8_t pf,
unsigned int hooknum, const struct sk_buff *skb,
const struct net_device *in,
const struct net_device *out,
const struct nf_loginfo *loginfo,
const char *prefix)
{
struct nf_log_buf *m;
if (!nf_log_allowed(net))
return;
m = nf_log_buf_open();
if (!loginfo)
loginfo = &default_loginfo;
nf_log_dump_packet_common(m, pf, hooknum, skb, in, out, loginfo,
prefix, net);
dump_arp_packet(m, loginfo, skb, skb_network_offset(skb));
nf_log_buf_close(m);
}
static struct nf_logger nf_arp_logger __read_mostly = {
.name = "nf_log_arp",
.type = NF_LOG_TYPE_LOG,
.logfn = nf_log_arp_packet,
.me = THIS_MODULE,
};
static void nf_log_dump_sk_uid_gid(struct net *net, struct nf_log_buf *m,
struct sock *sk)
{
if (!sk || !sk_fullsock(sk) || !net_eq(net, sock_net(sk)))
return;
read_lock_bh(&sk->sk_callback_lock);
if (sk->sk_socket && sk->sk_socket->file) {
const struct cred *cred = sk->sk_socket->file->f_cred;
nf_log_buf_add(m, "UID=%u GID=%u ",
from_kuid_munged(&init_user_ns, cred->fsuid),
from_kgid_munged(&init_user_ns, cred->fsgid));
}
read_unlock_bh(&sk->sk_callback_lock);
}
static noinline_for_stack int
nf_log_dump_tcp_header(struct nf_log_buf *m,
const struct sk_buff *skb,
u8 proto, int fragment,
unsigned int offset,
unsigned int logflags)
{
struct tcphdr _tcph;
const struct tcphdr *th;
/* Max length: 10 "PROTO=TCP " */
nf_log_buf_add(m, "PROTO=TCP ");
if (fragment)
return 0;
/* Max length: 25 "INCOMPLETE [65535 bytes] " */
th = skb_header_pointer(skb, offset, sizeof(_tcph), &_tcph);
if (!th) {
nf_log_buf_add(m, "INCOMPLETE [%u bytes] ", skb->len - offset);
return 1;
}
/* Max length: 20 "SPT=65535 DPT=65535 " */
nf_log_buf_add(m, "SPT=%u DPT=%u ",
ntohs(th->source), ntohs(th->dest));
/* Max length: 30 "SEQ=4294967295 ACK=4294967295 " */
if (logflags & NF_LOG_TCPSEQ) {
nf_log_buf_add(m, "SEQ=%u ACK=%u ",
ntohl(th->seq), ntohl(th->ack_seq));
}
/* Max length: 13 "WINDOW=65535 " */
nf_log_buf_add(m, "WINDOW=%u ", ntohs(th->window));
/* Max length: 9 "RES=0x3C " */
nf_log_buf_add(m, "RES=0x%02x ", (u_int8_t)(ntohl(tcp_flag_word(th) &
TCP_RESERVED_BITS) >> 22));
/* Max length: 32 "CWR ECE URG ACK PSH RST SYN FIN " */
if (th->cwr)
nf_log_buf_add(m, "CWR ");
if (th->ece)
nf_log_buf_add(m, "ECE ");
if (th->urg)
nf_log_buf_add(m, "URG ");
if (th->ack)
nf_log_buf_add(m, "ACK ");
if (th->psh)
nf_log_buf_add(m, "PSH ");
if (th->rst)
nf_log_buf_add(m, "RST ");
if (th->syn)
nf_log_buf_add(m, "SYN ");
if (th->fin)
nf_log_buf_add(m, "FIN ");
/* Max length: 11 "URGP=65535 " */
nf_log_buf_add(m, "URGP=%u ", ntohs(th->urg_ptr));
if ((logflags & NF_LOG_TCPOPT) && th->doff * 4 > sizeof(struct tcphdr)) {
unsigned int optsize = th->doff * 4 - sizeof(struct tcphdr);
u8 _opt[60 - sizeof(struct tcphdr)];
unsigned int i;
const u8 *op;
op = skb_header_pointer(skb, offset + sizeof(struct tcphdr),
optsize, _opt);
if (!op) {
nf_log_buf_add(m, "OPT (TRUNCATED)");
return 1;
}
/* Max length: 127 "OPT (" 15*4*2chars ") " */
nf_log_buf_add(m, "OPT (");
for (i = 0; i < optsize; i++)
nf_log_buf_add(m, "%02X", op[i]);
nf_log_buf_add(m, ") ");
}
return 0;
}
static noinline_for_stack int
nf_log_dump_udp_header(struct nf_log_buf *m,
const struct sk_buff *skb,
u8 proto, int fragment,
unsigned int offset)
{
struct udphdr _udph;
const struct udphdr *uh;
if (proto == IPPROTO_UDP)
/* Max length: 10 "PROTO=UDP " */
nf_log_buf_add(m, "PROTO=UDP ");
else /* Max length: 14 "PROTO=UDPLITE " */
nf_log_buf_add(m, "PROTO=UDPLITE ");
if (fragment)
goto out;
/* Max length: 25 "INCOMPLETE [65535 bytes] " */
uh = skb_header_pointer(skb, offset, sizeof(_udph), &_udph);
if (!uh) {
nf_log_buf_add(m, "INCOMPLETE [%u bytes] ", skb->len - offset);
return 1;
}
/* Max length: 20 "SPT=65535 DPT=65535 " */
nf_log_buf_add(m, "SPT=%u DPT=%u LEN=%u ",
ntohs(uh->source), ntohs(uh->dest), ntohs(uh->len));
out:
return 0;
}
/* One level of recursion won't kill us */
static noinline_for_stack void
dump_ipv4_packet(struct net *net, struct nf_log_buf *m,
const struct nf_loginfo *info,
const struct sk_buff *skb, unsigned int iphoff)
{
const struct iphdr *ih;
unsigned int logflags;
struct iphdr _iph;
if (info->type == NF_LOG_TYPE_LOG)
logflags = info->u.log.logflags;
else
logflags = NF_LOG_DEFAULT_MASK;
ih = skb_header_pointer(skb, iphoff, sizeof(_iph), &_iph);
if (!ih) {
nf_log_buf_add(m, "TRUNCATED");
return;
}
/* Important fields:
* TOS, len, DF/MF, fragment offset, TTL, src, dst, options.
* Max length: 40 "SRC=255.255.255.255 DST=255.255.255.255 "
*/
nf_log_buf_add(m, "SRC=%pI4 DST=%pI4 ", &ih->saddr, &ih->daddr);
/* Max length: 46 "LEN=65535 TOS=0xFF PREC=0xFF TTL=255 ID=65535 " */
nf_log_buf_add(m, "LEN=%u TOS=0x%02X PREC=0x%02X TTL=%u ID=%u ",
iph_totlen(skb, ih), ih->tos & IPTOS_TOS_MASK,
ih->tos & IPTOS_PREC_MASK, ih->ttl, ntohs(ih->id));
/* Max length: 6 "CE DF MF " */
if (ntohs(ih->frag_off) & IP_CE)
nf_log_buf_add(m, "CE ");
if (ntohs(ih->frag_off) & IP_DF)
nf_log_buf_add(m, "DF ");
if (ntohs(ih->frag_off) & IP_MF)
nf_log_buf_add(m, "MF ");
/* Max length: 11 "FRAG:65535 " */
if (ntohs(ih->frag_off) & IP_OFFSET)
nf_log_buf_add(m, "FRAG:%u ", ntohs(ih->frag_off) & IP_OFFSET);
if ((logflags & NF_LOG_IPOPT) &&
ih->ihl * 4 > sizeof(struct iphdr)) {
unsigned char _opt[4 * 15 - sizeof(struct iphdr)];
const unsigned char *op;
unsigned int i, optsize;
optsize = ih->ihl * 4 - sizeof(struct iphdr);
op = skb_header_pointer(skb, iphoff + sizeof(_iph),
optsize, _opt);
if (!op) {
nf_log_buf_add(m, "TRUNCATED");
return;
}
/* Max length: 127 "OPT (" 15*4*2chars ") " */
nf_log_buf_add(m, "OPT (");
for (i = 0; i < optsize; i++)
nf_log_buf_add(m, "%02X", op[i]);
nf_log_buf_add(m, ") ");
}
switch (ih->protocol) {
case IPPROTO_TCP:
if (nf_log_dump_tcp_header(m, skb, ih->protocol,
ntohs(ih->frag_off) & IP_OFFSET,
iphoff + ih->ihl * 4, logflags))
return;
break;
case IPPROTO_UDP:
case IPPROTO_UDPLITE:
if (nf_log_dump_udp_header(m, skb, ih->protocol,
ntohs(ih->frag_off) & IP_OFFSET,
iphoff + ih->ihl * 4))
return;
break;
case IPPROTO_ICMP: {
static const size_t required_len[NR_ICMP_TYPES + 1] = {
[ICMP_ECHOREPLY] = 4,
[ICMP_DEST_UNREACH] = 8 + sizeof(struct iphdr),
[ICMP_SOURCE_QUENCH] = 8 + sizeof(struct iphdr),
[ICMP_REDIRECT] = 8 + sizeof(struct iphdr),
[ICMP_ECHO] = 4,
[ICMP_TIME_EXCEEDED] = 8 + sizeof(struct iphdr),
[ICMP_PARAMETERPROB] = 8 + sizeof(struct iphdr),
[ICMP_TIMESTAMP] = 20,
[ICMP_TIMESTAMPREPLY] = 20,
[ICMP_ADDRESS] = 12,
[ICMP_ADDRESSREPLY] = 12 };
const struct icmphdr *ich;
struct icmphdr _icmph;
/* Max length: 11 "PROTO=ICMP " */
nf_log_buf_add(m, "PROTO=ICMP ");
if (ntohs(ih->frag_off) & IP_OFFSET)
break;
/* Max length: 25 "INCOMPLETE [65535 bytes] " */
ich = skb_header_pointer(skb, iphoff + ih->ihl * 4,
sizeof(_icmph), &_icmph);
if (!ich) {
nf_log_buf_add(m, "INCOMPLETE [%u bytes] ",
skb->len - iphoff - ih->ihl * 4);
break;
}
/* Max length: 18 "TYPE=255 CODE=255 " */
nf_log_buf_add(m, "TYPE=%u CODE=%u ", ich->type, ich->code);
/* Max length: 25 "INCOMPLETE [65535 bytes] " */
if (ich->type <= NR_ICMP_TYPES &&
required_len[ich->type] &&
skb->len - iphoff - ih->ihl * 4 < required_len[ich->type]) {
nf_log_buf_add(m, "INCOMPLETE [%u bytes] ",
skb->len - iphoff - ih->ihl * 4);
break;
}
switch (ich->type) {
case ICMP_ECHOREPLY:
case ICMP_ECHO:
/* Max length: 19 "ID=65535 SEQ=65535 " */
nf_log_buf_add(m, "ID=%u SEQ=%u ",
ntohs(ich->un.echo.id),
ntohs(ich->un.echo.sequence));
break;
case ICMP_PARAMETERPROB:
/* Max length: 14 "PARAMETER=255 " */
nf_log_buf_add(m, "PARAMETER=%u ",
ntohl(ich->un.gateway) >> 24);
break;
case ICMP_REDIRECT:
/* Max length: 24 "GATEWAY=255.255.255.255 " */
nf_log_buf_add(m, "GATEWAY=%pI4 ", &ich->un.gateway);
fallthrough;
case ICMP_DEST_UNREACH:
case ICMP_SOURCE_QUENCH:
case ICMP_TIME_EXCEEDED:
/* Max length: 3+maxlen */
if (!iphoff) { /* Only recurse once. */
nf_log_buf_add(m, "[");
dump_ipv4_packet(net, m, info, skb,
iphoff + ih->ihl * 4 + sizeof(_icmph));
nf_log_buf_add(m, "] ");
}
/* Max length: 10 "MTU=65535 " */
if (ich->type == ICMP_DEST_UNREACH &&
ich->code == ICMP_FRAG_NEEDED) {
nf_log_buf_add(m, "MTU=%u ",
ntohs(ich->un.frag.mtu));
}
}
break;
}
/* Max Length */
case IPPROTO_AH: {
const struct ip_auth_hdr *ah;
struct ip_auth_hdr _ahdr;
if (ntohs(ih->frag_off) & IP_OFFSET)
break;
/* Max length: 9 "PROTO=AH " */
nf_log_buf_add(m, "PROTO=AH ");
/* Max length: 25 "INCOMPLETE [65535 bytes] " */
ah = skb_header_pointer(skb, iphoff + ih->ihl * 4,
sizeof(_ahdr), &_ahdr);
if (!ah) {
nf_log_buf_add(m, "INCOMPLETE [%u bytes] ",
skb->len - iphoff - ih->ihl * 4);
break;
}
/* Length: 15 "SPI=0xF1234567 " */
nf_log_buf_add(m, "SPI=0x%x ", ntohl(ah->spi));
break;
}
case IPPROTO_ESP: {
const struct ip_esp_hdr *eh;
struct ip_esp_hdr _esph;
/* Max length: 10 "PROTO=ESP " */
nf_log_buf_add(m, "PROTO=ESP ");
if (ntohs(ih->frag_off) & IP_OFFSET)
break;
/* Max length: 25 "INCOMPLETE [65535 bytes] " */
eh = skb_header_pointer(skb, iphoff + ih->ihl * 4,
sizeof(_esph), &_esph);
if (!eh) {
nf_log_buf_add(m, "INCOMPLETE [%u bytes] ",
skb->len - iphoff - ih->ihl * 4);
break;
}
/* Length: 15 "SPI=0xF1234567 " */
nf_log_buf_add(m, "SPI=0x%x ", ntohl(eh->spi));
break;
}
/* Max length: 10 "PROTO 255 " */
default:
nf_log_buf_add(m, "PROTO=%u ", ih->protocol);
}
/* Max length: 15 "UID=4294967295 " */
if ((logflags & NF_LOG_UID) && !iphoff)
nf_log_dump_sk_uid_gid(net, m, skb->sk);
/* Max length: 16 "MARK=0xFFFFFFFF " */
if (!iphoff && skb->mark)
nf_log_buf_add(m, "MARK=0x%x ", skb->mark);
/* Proto Max log string length */
/* IP: 40+46+6+11+127 = 230 */
/* TCP: 10+max(25,20+30+13+9+32+11+127) = 252 */
/* UDP: 10+max(25,20) = 35 */
/* UDPLITE: 14+max(25,20) = 39 */
/* ICMP: 11+max(25, 18+25+max(19,14,24+3+n+10,3+n+10)) = 91+n */
/* ESP: 10+max(25)+15 = 50 */
/* AH: 9+max(25)+15 = 49 */
/* unknown: 10 */
/* (ICMP allows recursion one level deep) */
/* maxlen = IP + ICMP + IP + max(TCP,UDP,ICMP,unknown) */
/* maxlen = 230+ 91 + 230 + 252 = 803 */
}
static noinline_for_stack void
dump_ipv6_packet(struct net *net, struct nf_log_buf *m,
const struct nf_loginfo *info,
const struct sk_buff *skb, unsigned int ip6hoff,
int recurse)
{
const struct ipv6hdr *ih;
unsigned int hdrlen = 0;
unsigned int logflags;
struct ipv6hdr _ip6h;
unsigned int ptr;
u8 currenthdr;
int fragment;
if (info->type == NF_LOG_TYPE_LOG)
logflags = info->u.log.logflags;
else
logflags = NF_LOG_DEFAULT_MASK;
ih = skb_header_pointer(skb, ip6hoff, sizeof(_ip6h), &_ip6h);
if (!ih) {
nf_log_buf_add(m, "TRUNCATED");
return;
}
/* Max length: 88 "SRC=0000.0000.0000.0000.0000.0000.0000.0000 DST=0000.0000.0000.0000.0000.0000.0000.0000 " */
nf_log_buf_add(m, "SRC=%pI6 DST=%pI6 ", &ih->saddr, &ih->daddr);
/* Max length: 44 "LEN=65535 TC=255 HOPLIMIT=255 FLOWLBL=FFFFF " */
nf_log_buf_add(m, "LEN=%zu TC=%u HOPLIMIT=%u FLOWLBL=%u ",
ntohs(ih->payload_len) + sizeof(struct ipv6hdr),
(ntohl(*(__be32 *)ih) & 0x0ff00000) >> 20,
ih->hop_limit,
(ntohl(*(__be32 *)ih) & 0x000fffff));
fragment = 0;
ptr = ip6hoff + sizeof(struct ipv6hdr);
currenthdr = ih->nexthdr;
while (currenthdr != NEXTHDR_NONE && nf_ip6_ext_hdr(currenthdr)) {
struct ipv6_opt_hdr _hdr;
const struct ipv6_opt_hdr *hp;
hp = skb_header_pointer(skb, ptr, sizeof(_hdr), &_hdr);
if (!hp) {
nf_log_buf_add(m, "TRUNCATED");
return;
}
/* Max length: 48 "OPT (...) " */
if (logflags & NF_LOG_IPOPT)
nf_log_buf_add(m, "OPT ( ");
switch (currenthdr) {
case IPPROTO_FRAGMENT: {
struct frag_hdr _fhdr;
const struct frag_hdr *fh;
nf_log_buf_add(m, "FRAG:");
fh = skb_header_pointer(skb, ptr, sizeof(_fhdr),
&_fhdr);
if (!fh) {
nf_log_buf_add(m, "TRUNCATED ");
return;
}
/* Max length: 6 "65535 " */
nf_log_buf_add(m, "%u ", ntohs(fh->frag_off) & 0xFFF8);
/* Max length: 11 "INCOMPLETE " */
if (fh->frag_off & htons(0x0001))
nf_log_buf_add(m, "INCOMPLETE ");
nf_log_buf_add(m, "ID:%08x ",
ntohl(fh->identification));
if (ntohs(fh->frag_off) & 0xFFF8)
fragment = 1;
hdrlen = 8;
break;
}
case IPPROTO_DSTOPTS:
case IPPROTO_ROUTING:
case IPPROTO_HOPOPTS:
if (fragment) {
if (logflags & NF_LOG_IPOPT)
nf_log_buf_add(m, ")");
return;
}
hdrlen = ipv6_optlen(hp);
break;
/* Max Length */
case IPPROTO_AH:
if (logflags & NF_LOG_IPOPT) {
struct ip_auth_hdr _ahdr;
const struct ip_auth_hdr *ah;
/* Max length: 3 "AH " */
nf_log_buf_add(m, "AH ");
if (fragment) {
nf_log_buf_add(m, ")");
return;
}
ah = skb_header_pointer(skb, ptr, sizeof(_ahdr),
&_ahdr);
if (!ah) {
/* Max length: 26 "INCOMPLETE [65535 bytes] )" */
nf_log_buf_add(m, "INCOMPLETE [%u bytes] )",
skb->len - ptr);
return;
}
/* Length: 15 "SPI=0xF1234567 */
nf_log_buf_add(m, "SPI=0x%x ", ntohl(ah->spi));
}
hdrlen = ipv6_authlen(hp);
break;
case IPPROTO_ESP:
if (logflags & NF_LOG_IPOPT) {
struct ip_esp_hdr _esph;
const struct ip_esp_hdr *eh;
/* Max length: 4 "ESP " */
nf_log_buf_add(m, "ESP ");
if (fragment) {
nf_log_buf_add(m, ")");
return;
}
/* Max length: 26 "INCOMPLETE [65535 bytes] )" */
eh = skb_header_pointer(skb, ptr, sizeof(_esph),
&_esph);
if (!eh) {
nf_log_buf_add(m, "INCOMPLETE [%u bytes] )",
skb->len - ptr);
return;
}
/* Length: 16 "SPI=0xF1234567 )" */
nf_log_buf_add(m, "SPI=0x%x )",
ntohl(eh->spi));
}
return;
default:
/* Max length: 20 "Unknown Ext Hdr 255" */
nf_log_buf_add(m, "Unknown Ext Hdr %u", currenthdr);
return;
}
if (logflags & NF_LOG_IPOPT)
nf_log_buf_add(m, ") ");
currenthdr = hp->nexthdr;
ptr += hdrlen;
}
switch (currenthdr) {
case IPPROTO_TCP:
if (nf_log_dump_tcp_header(m, skb, currenthdr, fragment,
ptr, logflags))
return;
break;
case IPPROTO_UDP:
case IPPROTO_UDPLITE:
if (nf_log_dump_udp_header(m, skb, currenthdr, fragment, ptr))
return;
break;
case IPPROTO_ICMPV6: {
struct icmp6hdr _icmp6h;
const struct icmp6hdr *ic;
/* Max length: 13 "PROTO=ICMPv6 " */
nf_log_buf_add(m, "PROTO=ICMPv6 ");
if (fragment)
break;
/* Max length: 25 "INCOMPLETE [65535 bytes] " */
ic = skb_header_pointer(skb, ptr, sizeof(_icmp6h), &_icmp6h);
if (!ic) {
nf_log_buf_add(m, "INCOMPLETE [%u bytes] ",
skb->len - ptr);
return;
}
/* Max length: 18 "TYPE=255 CODE=255 " */
nf_log_buf_add(m, "TYPE=%u CODE=%u ",
ic->icmp6_type, ic->icmp6_code);
switch (ic->icmp6_type) {
case ICMPV6_ECHO_REQUEST:
case ICMPV6_ECHO_REPLY:
/* Max length: 19 "ID=65535 SEQ=65535 " */
nf_log_buf_add(m, "ID=%u SEQ=%u ",
ntohs(ic->icmp6_identifier),
ntohs(ic->icmp6_sequence));
break;
case ICMPV6_MGM_QUERY:
case ICMPV6_MGM_REPORT:
case ICMPV6_MGM_REDUCTION:
break;
case ICMPV6_PARAMPROB:
/* Max length: 17 "POINTER=ffffffff " */
nf_log_buf_add(m, "POINTER=%08x ",
ntohl(ic->icmp6_pointer));
fallthrough;
case ICMPV6_DEST_UNREACH:
case ICMPV6_PKT_TOOBIG:
case ICMPV6_TIME_EXCEED:
/* Max length: 3+maxlen */
if (recurse) {
nf_log_buf_add(m, "[");
dump_ipv6_packet(net, m, info, skb,
ptr + sizeof(_icmp6h), 0);
nf_log_buf_add(m, "] ");
}
/* Max length: 10 "MTU=65535 " */
if (ic->icmp6_type == ICMPV6_PKT_TOOBIG) {
nf_log_buf_add(m, "MTU=%u ",
ntohl(ic->icmp6_mtu));
}
}
break;
}
/* Max length: 10 "PROTO=255 " */
default:
nf_log_buf_add(m, "PROTO=%u ", currenthdr);
}
/* Max length: 15 "UID=4294967295 " */
if ((logflags & NF_LOG_UID) && recurse)
nf_log_dump_sk_uid_gid(net, m, skb->sk);
/* Max length: 16 "MARK=0xFFFFFFFF " */
if (recurse && skb->mark)
nf_log_buf_add(m, "MARK=0x%x ", skb->mark);
}
static void dump_mac_header(struct nf_log_buf *m,
const struct nf_loginfo *info,
const struct sk_buff *skb)
{
struct net_device *dev = skb->dev;
unsigned int logflags = 0;
if (info->type == NF_LOG_TYPE_LOG)
logflags = info->u.log.logflags;
if (!(logflags & NF_LOG_MACDECODE))
goto fallback;
switch (dev->type) {
case ARPHRD_ETHER:
nf_log_buf_add(m, "MACSRC=%pM MACDST=%pM ",
eth_hdr(skb)->h_source, eth_hdr(skb)->h_dest);
nf_log_dump_vlan(m, skb);
nf_log_buf_add(m, "MACPROTO=%04x ",
ntohs(eth_hdr(skb)->h_proto));
return;
default:
break;
}
fallback:
nf_log_buf_add(m, "MAC=");
if (dev->hard_header_len &&
skb->mac_header != skb->network_header) {
const unsigned char *p = skb_mac_header(skb);
unsigned int i;
if (dev->type == ARPHRD_SIT) {
p -= ETH_HLEN;
if (p < skb->head)
p = NULL;
}
if (p) {
nf_log_buf_add(m, "%02x", *p++);
for (i = 1; i < dev->hard_header_len; i++)
nf_log_buf_add(m, ":%02x", *p++);
}
if (dev->type == ARPHRD_SIT) {
const struct iphdr *iph =
(struct iphdr *)skb_mac_header(skb);
nf_log_buf_add(m, " TUNNEL=%pI4->%pI4", &iph->saddr,
&iph->daddr);
}
}
nf_log_buf_add(m, " ");
}
static void nf_log_ip_packet(struct net *net, u_int8_t pf,
unsigned int hooknum, const struct sk_buff *skb,
const struct net_device *in,
const struct net_device *out,
const struct nf_loginfo *loginfo,
const char *prefix)
{
struct nf_log_buf *m;
if (!nf_log_allowed(net))
return;
m = nf_log_buf_open();
if (!loginfo)
loginfo = &default_loginfo;
nf_log_dump_packet_common(m, pf, hooknum, skb, in,
out, loginfo, prefix, net);
if (in)
dump_mac_header(m, loginfo, skb);
dump_ipv4_packet(net, m, loginfo, skb, skb_network_offset(skb));
nf_log_buf_close(m);
}
static struct nf_logger nf_ip_logger __read_mostly = {
.name = "nf_log_ipv4",
.type = NF_LOG_TYPE_LOG,
.logfn = nf_log_ip_packet,
.me = THIS_MODULE,
};
static void nf_log_ip6_packet(struct net *net, u_int8_t pf,
unsigned int hooknum, const struct sk_buff *skb,
const struct net_device *in,
const struct net_device *out,
const struct nf_loginfo *loginfo,
const char *prefix)
{
struct nf_log_buf *m;
if (!nf_log_allowed(net))
return;
m = nf_log_buf_open();
if (!loginfo)
loginfo = &default_loginfo;
nf_log_dump_packet_common(m, pf, hooknum, skb, in, out,
loginfo, prefix, net);
if (in)
dump_mac_header(m, loginfo, skb);
dump_ipv6_packet(net, m, loginfo, skb, skb_network_offset(skb), 1);
nf_log_buf_close(m);
}
static struct nf_logger nf_ip6_logger __read_mostly = {
.name = "nf_log_ipv6",
.type = NF_LOG_TYPE_LOG,
.logfn = nf_log_ip6_packet,
.me = THIS_MODULE,
};
static void nf_log_unknown_packet(struct net *net, u_int8_t pf,
unsigned int hooknum,
const struct sk_buff *skb,
const struct net_device *in,
const struct net_device *out,
const struct nf_loginfo *loginfo,
const char *prefix)
{
struct nf_log_buf *m;
if (!nf_log_allowed(net))
return;
m = nf_log_buf_open();
if (!loginfo)
loginfo = &default_loginfo;
nf_log_dump_packet_common(m, pf, hooknum, skb, in, out, loginfo,
prefix, net);
dump_mac_header(m, loginfo, skb);
nf_log_buf_close(m);
}
static void nf_log_netdev_packet(struct net *net, u_int8_t pf,
unsigned int hooknum,
const struct sk_buff *skb,
const struct net_device *in,
const struct net_device *out,
const struct nf_loginfo *loginfo,
const char *prefix)
{
switch (skb->protocol) {
case htons(ETH_P_IP):
nf_log_ip_packet(net, pf, hooknum, skb, in, out, loginfo, prefix);
break;
case htons(ETH_P_IPV6):
nf_log_ip6_packet(net, pf, hooknum, skb, in, out, loginfo, prefix);
break;
case htons(ETH_P_ARP):
case htons(ETH_P_RARP):
nf_log_arp_packet(net, pf, hooknum, skb, in, out, loginfo, prefix);
break;
default:
nf_log_unknown_packet(net, pf, hooknum, skb,
in, out, loginfo, prefix);
break;
}
}
static struct nf_logger nf_netdev_logger __read_mostly = {
.name = "nf_log_netdev",
.type = NF_LOG_TYPE_LOG,
.logfn = nf_log_netdev_packet,
.me = THIS_MODULE,
};
static struct nf_logger nf_bridge_logger __read_mostly = {
.name = "nf_log_bridge",
.type = NF_LOG_TYPE_LOG,
.logfn = nf_log_netdev_packet,
.me = THIS_MODULE,
};
static int __net_init nf_log_syslog_net_init(struct net *net)
{
int ret = nf_log_set(net, NFPROTO_IPV4, &nf_ip_logger);
if (ret)
return ret;
ret = nf_log_set(net, NFPROTO_ARP, &nf_arp_logger);
if (ret)
goto err1;
ret = nf_log_set(net, NFPROTO_IPV6, &nf_ip6_logger);
if (ret)
goto err2;
ret = nf_log_set(net, NFPROTO_NETDEV, &nf_netdev_logger);
if (ret)
goto err3;
ret = nf_log_set(net, NFPROTO_BRIDGE, &nf_bridge_logger);
if (ret)
goto err4;
return 0;
err4:
nf_log_unset(net, &nf_netdev_logger);
err3:
nf_log_unset(net, &nf_ip6_logger);
err2:
nf_log_unset(net, &nf_arp_logger);
err1:
nf_log_unset(net, &nf_ip_logger);
return ret;
}
static void __net_exit nf_log_syslog_net_exit(struct net *net)
{
nf_log_unset(net, &nf_ip_logger);
nf_log_unset(net, &nf_arp_logger);
nf_log_unset(net, &nf_ip6_logger);
nf_log_unset(net, &nf_netdev_logger);
nf_log_unset(net, &nf_bridge_logger);
}
static struct pernet_operations nf_log_syslog_net_ops = {
.init = nf_log_syslog_net_init,
.exit = nf_log_syslog_net_exit,
};
static int __init nf_log_syslog_init(void)
{
int ret;
ret = register_pernet_subsys(&nf_log_syslog_net_ops);
if (ret < 0)
return ret;
ret = nf_log_register(NFPROTO_IPV4, &nf_ip_logger);
if (ret < 0)
goto err1;
ret = nf_log_register(NFPROTO_ARP, &nf_arp_logger);
if (ret < 0)
goto err2;
ret = nf_log_register(NFPROTO_IPV6, &nf_ip6_logger);
if (ret < 0)
goto err3;
ret = nf_log_register(NFPROTO_NETDEV, &nf_netdev_logger);
if (ret < 0)
goto err4;
ret = nf_log_register(NFPROTO_BRIDGE, &nf_bridge_logger);
if (ret < 0)
goto err5;
return 0;
err5:
nf_log_unregister(&nf_netdev_logger);
err4:
nf_log_unregister(&nf_ip6_logger);
err3:
nf_log_unregister(&nf_arp_logger);
err2:
nf_log_unregister(&nf_ip_logger);
err1:
pr_err("failed to register logger\n");
unregister_pernet_subsys(&nf_log_syslog_net_ops);
return ret;
}
static void __exit nf_log_syslog_exit(void)
{
unregister_pernet_subsys(&nf_log_syslog_net_ops);
nf_log_unregister(&nf_ip_logger);
nf_log_unregister(&nf_arp_logger);
nf_log_unregister(&nf_ip6_logger);
nf_log_unregister(&nf_netdev_logger);
nf_log_unregister(&nf_bridge_logger);
}
module_init(nf_log_syslog_init);
module_exit(nf_log_syslog_exit);
MODULE_AUTHOR("Netfilter Core Team <[email protected]>");
MODULE_DESCRIPTION("Netfilter syslog packet logging");
MODULE_LICENSE("GPL");
MODULE_ALIAS("nf_log_arp");
MODULE_ALIAS("nf_log_bridge");
MODULE_ALIAS("nf_log_ipv4");
MODULE_ALIAS("nf_log_ipv6");
MODULE_ALIAS("nf_log_netdev");
MODULE_ALIAS_NF_LOGGER(AF_BRIDGE, 0);
MODULE_ALIAS_NF_LOGGER(AF_INET, 0);
MODULE_ALIAS_NF_LOGGER(3, 0);
MODULE_ALIAS_NF_LOGGER(5, 0); /* NFPROTO_NETDEV */
MODULE_ALIAS_NF_LOGGER(AF_INET6, 0);
|
// SPDX-License-Identifier: GPL-2.0+
/*
* Driver for SMSC USB3503 USB 2.0 hub controller driver
*
* Copyright (c) 2012-2013 Dongjin Kim ([email protected])
*/
#include <linux/clk.h>
#include <linux/i2c.h>
#include <linux/gpio/consumer.h>
#include <linux/delay.h>
#include <linux/slab.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/platform_data/usb3503.h>
#include <linux/regmap.h>
#define USB3503_VIDL 0x00
#define USB3503_VIDM 0x01
#define USB3503_PIDL 0x02
#define USB3503_PIDM 0x03
#define USB3503_DIDL 0x04
#define USB3503_DIDM 0x05
#define USB3503_CFG1 0x06
#define USB3503_SELF_BUS_PWR (1 << 7)
#define USB3503_CFG2 0x07
#define USB3503_CFG3 0x08
#define USB3503_NRD 0x09
#define USB3503_PDS 0x0a
#define USB3503_SP_ILOCK 0xe7
#define USB3503_SPILOCK_CONNECT (1 << 1)
#define USB3503_SPILOCK_CONFIG (1 << 0)
#define USB3503_CFGP 0xee
#define USB3503_CLKSUSP (1 << 7)
#define USB3503_RESET 0xff
struct usb3503 {
enum usb3503_mode mode;
struct regmap *regmap;
struct device *dev;
struct clk *clk;
u8 port_off_mask;
struct gpio_desc *bypass;
struct gpio_desc *intn;
struct gpio_desc *reset;
struct gpio_desc *connect;
bool secondary_ref_clk;
};
static int usb3503_connect(struct usb3503 *hub)
{
struct device *dev = hub->dev;
int err;
if (hub->regmap) {
/* SP_ILOCK: set connect_n, config_n for config */
err = regmap_write(hub->regmap, USB3503_SP_ILOCK,
(USB3503_SPILOCK_CONNECT
| USB3503_SPILOCK_CONFIG));
if (err < 0) {
dev_err(dev, "SP_ILOCK failed (%d)\n", err);
return err;
}
/* PDS : Set the ports which are disabled in self-powered mode. */
if (hub->port_off_mask) {
err = regmap_update_bits(hub->regmap, USB3503_PDS,
hub->port_off_mask,
hub->port_off_mask);
if (err < 0) {
dev_err(dev, "PDS failed (%d)\n", err);
return err;
}
}
/* CFG1 : Set SELF_BUS_PWR, this enables self-powered operation. */
err = regmap_update_bits(hub->regmap, USB3503_CFG1,
USB3503_SELF_BUS_PWR,
USB3503_SELF_BUS_PWR);
if (err < 0) {
dev_err(dev, "CFG1 failed (%d)\n", err);
return err;
}
/* SP_LOCK: clear connect_n, config_n for hub connect */
err = regmap_update_bits(hub->regmap, USB3503_SP_ILOCK,
(USB3503_SPILOCK_CONNECT
| USB3503_SPILOCK_CONFIG), 0);
if (err < 0) {
dev_err(dev, "SP_ILOCK failed (%d)\n", err);
return err;
}
}
if (hub->connect)
gpiod_set_value_cansleep(hub->connect, 1);
hub->mode = USB3503_MODE_HUB;
dev_info(dev, "switched to HUB mode\n");
return 0;
}
static int usb3503_switch_mode(struct usb3503 *hub, enum usb3503_mode mode)
{
struct device *dev = hub->dev;
int rst, bypass, conn;
switch (mode) {
case USB3503_MODE_HUB:
conn = 1;
rst = 0;
bypass = 0;
break;
case USB3503_MODE_STANDBY:
conn = 0;
rst = 1;
bypass = 1;
dev_info(dev, "switched to STANDBY mode\n");
break;
case USB3503_MODE_BYPASS:
conn = 0;
rst = 0;
bypass = 1;
break;
default:
dev_err(dev, "unknown mode is requested\n");
return -EINVAL;
}
if (!conn && hub->connect)
gpiod_set_value_cansleep(hub->connect, 0);
if (hub->reset)
gpiod_set_value_cansleep(hub->reset, rst);
if (hub->bypass)
gpiod_set_value_cansleep(hub->bypass, bypass);
if (conn) {
/* Wait T_HUBINIT == 4ms for hub logic to stabilize */
usleep_range(4000, 10000);
return usb3503_connect(hub);
}
return 0;
}
static const struct regmap_config usb3503_regmap_config = {
.reg_bits = 8,
.val_bits = 8,
.max_register = USB3503_RESET,
};
static int usb3503_probe(struct usb3503 *hub)
{
struct device *dev = hub->dev;
struct usb3503_platform_data *pdata = dev_get_platdata(dev);
struct device_node *np = dev->of_node;
int err;
bool is_clk_enabled = false;
u32 mode = USB3503_MODE_HUB;
const u32 *property;
enum gpiod_flags flags;
int len;
if (pdata) {
hub->port_off_mask = pdata->port_off_mask;
hub->mode = pdata->initial_mode;
} else if (np) {
u32 rate = 0;
hub->port_off_mask = 0;
if (!of_property_read_u32(np, "refclk-frequency", &rate)) {
switch (rate) {
case 38400000:
case 26000000:
case 19200000:
case 12000000:
hub->secondary_ref_clk = 0;
break;
case 24000000:
case 27000000:
case 25000000:
case 50000000:
hub->secondary_ref_clk = 1;
break;
default:
dev_err(dev,
"unsupported reference clock rate (%d)\n",
(int) rate);
return -EINVAL;
}
}
hub->clk = devm_clk_get_optional(dev, "refclk");
if (IS_ERR(hub->clk)) {
dev_err(dev, "unable to request refclk (%ld)\n",
PTR_ERR(hub->clk));
return PTR_ERR(hub->clk);
}
if (rate != 0) {
err = clk_set_rate(hub->clk, rate);
if (err) {
dev_err(dev,
"unable to set reference clock rate to %d\n",
(int)rate);
return err;
}
}
err = clk_prepare_enable(hub->clk);
if (err) {
dev_err(dev, "unable to enable reference clock\n");
return err;
}
is_clk_enabled = true;
property = of_get_property(np, "disabled-ports", &len);
if (property && (len / sizeof(u32)) > 0) {
int i;
for (i = 0; i < len / sizeof(u32); i++) {
u32 port = be32_to_cpu(property[i]);
if ((1 <= port) && (port <= 3))
hub->port_off_mask |= (1 << port);
}
}
of_property_read_u32(np, "initial-mode", &mode);
hub->mode = mode;
}
if (hub->secondary_ref_clk)
flags = GPIOD_OUT_LOW;
else
flags = GPIOD_OUT_HIGH;
hub->intn = devm_gpiod_get_optional(dev, "intn", flags);
if (IS_ERR(hub->intn)) {
err = PTR_ERR(hub->intn);
goto err_clk;
}
if (hub->intn)
gpiod_set_consumer_name(hub->intn, "usb3503 intn");
hub->connect = devm_gpiod_get_optional(dev, "connect", GPIOD_OUT_LOW);
if (IS_ERR(hub->connect)) {
err = PTR_ERR(hub->connect);
goto err_clk;
}
if (hub->connect)
gpiod_set_consumer_name(hub->connect, "usb3503 connect");
hub->bypass = devm_gpiod_get_optional(dev, "bypass", GPIOD_OUT_HIGH);
if (IS_ERR(hub->bypass)) {
err = PTR_ERR(hub->bypass);
goto err_clk;
}
if (hub->bypass)
gpiod_set_consumer_name(hub->bypass, "usb3503 bypass");
hub->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_HIGH);
if (IS_ERR(hub->reset)) {
err = PTR_ERR(hub->reset);
goto err_clk;
}
if (hub->reset) {
/* Datasheet defines a hardware reset to be at least 100us */
usleep_range(100, 10000);
gpiod_set_consumer_name(hub->reset, "usb3503 reset");
}
if (hub->port_off_mask && !hub->regmap)
dev_err(dev, "Ports disabled with no control interface\n");
usb3503_switch_mode(hub, hub->mode);
dev_info(dev, "%s: probed in %s mode\n", __func__,
(hub->mode == USB3503_MODE_HUB) ? "hub" : "standby");
return 0;
err_clk:
if (is_clk_enabled)
clk_disable_unprepare(hub->clk);
return err;
}
static int usb3503_i2c_probe(struct i2c_client *i2c)
{
struct usb3503 *hub;
int err;
hub = devm_kzalloc(&i2c->dev, sizeof(struct usb3503), GFP_KERNEL);
if (!hub)
return -ENOMEM;
i2c_set_clientdata(i2c, hub);
hub->regmap = devm_regmap_init_i2c(i2c, &usb3503_regmap_config);
if (IS_ERR(hub->regmap)) {
err = PTR_ERR(hub->regmap);
dev_err(&i2c->dev, "Failed to initialise regmap: %d\n", err);
return err;
}
hub->dev = &i2c->dev;
return usb3503_probe(hub);
}
static void usb3503_i2c_remove(struct i2c_client *i2c)
{
struct usb3503 *hub;
hub = i2c_get_clientdata(i2c);
clk_disable_unprepare(hub->clk);
}
static int usb3503_platform_probe(struct platform_device *pdev)
{
struct usb3503 *hub;
hub = devm_kzalloc(&pdev->dev, sizeof(struct usb3503), GFP_KERNEL);
if (!hub)
return -ENOMEM;
hub->dev = &pdev->dev;
platform_set_drvdata(pdev, hub);
return usb3503_probe(hub);
}
static void usb3503_platform_remove(struct platform_device *pdev)
{
struct usb3503 *hub;
hub = platform_get_drvdata(pdev);
clk_disable_unprepare(hub->clk);
}
static int __maybe_unused usb3503_suspend(struct usb3503 *hub)
{
usb3503_switch_mode(hub, USB3503_MODE_STANDBY);
clk_disable_unprepare(hub->clk);
return 0;
}
static int __maybe_unused usb3503_resume(struct usb3503 *hub)
{
clk_prepare_enable(hub->clk);
usb3503_switch_mode(hub, hub->mode);
return 0;
}
static int __maybe_unused usb3503_i2c_suspend(struct device *dev)
{
struct i2c_client *client = to_i2c_client(dev);
return usb3503_suspend(i2c_get_clientdata(client));
}
static int __maybe_unused usb3503_i2c_resume(struct device *dev)
{
struct i2c_client *client = to_i2c_client(dev);
return usb3503_resume(i2c_get_clientdata(client));
}
static int __maybe_unused usb3503_platform_suspend(struct device *dev)
{
return usb3503_suspend(dev_get_drvdata(dev));
}
static int __maybe_unused usb3503_platform_resume(struct device *dev)
{
return usb3503_resume(dev_get_drvdata(dev));
}
static SIMPLE_DEV_PM_OPS(usb3503_i2c_pm_ops, usb3503_i2c_suspend,
usb3503_i2c_resume);
static SIMPLE_DEV_PM_OPS(usb3503_platform_pm_ops, usb3503_platform_suspend,
usb3503_platform_resume);
static const struct i2c_device_id usb3503_id[] = {
{ USB3503_I2C_NAME },
{ }
};
MODULE_DEVICE_TABLE(i2c, usb3503_id);
#ifdef CONFIG_OF
static const struct of_device_id usb3503_of_match[] = {
{ .compatible = "smsc,usb3503", },
{ .compatible = "smsc,usb3503a", },
{ .compatible = "smsc,usb3803", },
{},
};
MODULE_DEVICE_TABLE(of, usb3503_of_match);
#endif
static struct i2c_driver usb3503_i2c_driver = {
.driver = {
.name = USB3503_I2C_NAME,
.pm = pm_ptr(&usb3503_i2c_pm_ops),
.of_match_table = of_match_ptr(usb3503_of_match),
},
.probe = usb3503_i2c_probe,
.remove = usb3503_i2c_remove,
.id_table = usb3503_id,
};
static struct platform_driver usb3503_platform_driver = {
.driver = {
.name = USB3503_I2C_NAME,
.of_match_table = of_match_ptr(usb3503_of_match),
.pm = pm_ptr(&usb3503_platform_pm_ops),
},
.probe = usb3503_platform_probe,
.remove = usb3503_platform_remove,
};
static int __init usb3503_init(void)
{
int err;
err = i2c_add_driver(&usb3503_i2c_driver);
if (err) {
pr_err("usb3503: Failed to register I2C driver: %d\n", err);
return err;
}
err = platform_driver_register(&usb3503_platform_driver);
if (err) {
pr_err("usb3503: Failed to register platform driver: %d\n",
err);
i2c_del_driver(&usb3503_i2c_driver);
return err;
}
return 0;
}
module_init(usb3503_init);
static void __exit usb3503_exit(void)
{
platform_driver_unregister(&usb3503_platform_driver);
i2c_del_driver(&usb3503_i2c_driver);
}
module_exit(usb3503_exit);
MODULE_AUTHOR("Dongjin Kim <[email protected]>");
MODULE_DESCRIPTION("USB3503 USB HUB driver");
MODULE_LICENSE("GPL");
|
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* STX GP3 - 8560 ADS Device Tree Source
*
* Copyright 2008 Freescale Semiconductor Inc.
*/
/dts-v1/;
/include/ "fsl/e500v1_power_isa.dtsi"
/ {
model = "stx,gp3";
compatible = "stx,gp3-8560", "stx,gp3";
#address-cells = <1>;
#size-cells = <1>;
aliases {
ethernet0 = &enet0;
ethernet1 = &enet1;
serial0 = &serial0;
pci0 = &pci0;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
PowerPC,8560@0 {
device_type = "cpu";
reg = <0>;
d-cache-line-size = <32>;
i-cache-line-size = <32>;
d-cache-size = <32768>;
i-cache-size = <32768>;
timebase-frequency = <0>;
bus-frequency = <0>;
clock-frequency = <0>;
next-level-cache = <&L2>;
};
};
memory {
device_type = "memory";
reg = <0x00000000 0x10000000>;
};
soc@fdf00000 {
#address-cells = <1>;
#size-cells = <1>;
device_type = "soc";
ranges = <0 0xfdf00000 0x100000>;
bus-frequency = <0>;
compatible = "fsl,mpc8560-immr", "simple-bus";
ecm-law@0 {
compatible = "fsl,ecm-law";
reg = <0x0 0x1000>;
fsl,num-laws = <8>;
};
ecm@1000 {
compatible = "fsl,mpc8560-ecm", "fsl,ecm";
reg = <0x1000 0x1000>;
interrupts = <17 2>;
interrupt-parent = <&mpic>;
};
memory-controller@2000 {
compatible = "fsl,mpc8540-memory-controller";
reg = <0x2000 0x1000>;
interrupt-parent = <&mpic>;
interrupts = <18 2>;
};
L2: l2-cache-controller@20000 {
compatible = "fsl,mpc8540-l2-cache-controller";
reg = <0x20000 0x1000>;
cache-line-size = <32>;
cache-size = <0x40000>; // L2, 256K
interrupt-parent = <&mpic>;
interrupts = <16 2>;
};
i2c@3000 {
#address-cells = <1>;
#size-cells = <0>;
cell-index = <0>;
compatible = "fsl-i2c";
reg = <0x3000 0x100>;
interrupts = <43 2>;
interrupt-parent = <&mpic>;
dfsrr;
};
dma@21300 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "fsl,mpc8560-dma", "fsl,eloplus-dma";
reg = <0x21300 0x4>;
ranges = <0x0 0x21100 0x200>;
cell-index = <0>;
dma-channel@0 {
compatible = "fsl,mpc8560-dma-channel",
"fsl,eloplus-dma-channel";
reg = <0x0 0x80>;
cell-index = <0>;
interrupt-parent = <&mpic>;
interrupts = <20 2>;
};
dma-channel@80 {
compatible = "fsl,mpc8560-dma-channel",
"fsl,eloplus-dma-channel";
reg = <0x80 0x80>;
cell-index = <1>;
interrupt-parent = <&mpic>;
interrupts = <21 2>;
};
dma-channel@100 {
compatible = "fsl,mpc8560-dma-channel",
"fsl,eloplus-dma-channel";
reg = <0x100 0x80>;
cell-index = <2>;
interrupt-parent = <&mpic>;
interrupts = <22 2>;
};
dma-channel@180 {
compatible = "fsl,mpc8560-dma-channel",
"fsl,eloplus-dma-channel";
reg = <0x180 0x80>;
cell-index = <3>;
interrupt-parent = <&mpic>;
interrupts = <23 2>;
};
};
enet0: ethernet@24000 {
#address-cells = <1>;
#size-cells = <1>;
cell-index = <0>;
device_type = "network";
model = "TSEC";
compatible = "gianfar";
reg = <0x24000 0x1000>;
ranges = <0x0 0x24000 0x1000>;
local-mac-address = [ 00 00 00 00 00 00 ];
interrupts = <29 2 30 2 34 2>;
interrupt-parent = <&mpic>;
tbi-handle = <&tbi0>;
phy-handle = <&phy2>;
mdio@520 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,gianfar-mdio";
reg = <0x520 0x20>;
phy2: ethernet-phy@2 {
interrupt-parent = <&mpic>;
interrupts = <5 4>;
reg = <2>;
};
phy4: ethernet-phy@4 {
interrupt-parent = <&mpic>;
interrupts = <5 4>;
reg = <4>;
};
tbi0: tbi-phy@11 {
reg = <0x11>;
device_type = "tbi-phy";
};
};
};
enet1: ethernet@25000 {
#address-cells = <1>;
#size-cells = <1>;
cell-index = <1>;
device_type = "network";
model = "TSEC";
compatible = "gianfar";
reg = <0x25000 0x1000>;
ranges = <0x0 0x25000 0x1000>;
local-mac-address = [ 00 00 00 00 00 00 ];
interrupts = <35 2 36 2 40 2>;
interrupt-parent = <&mpic>;
tbi-handle = <&tbi1>;
phy-handle = <&phy4>;
mdio@520 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,gianfar-tbi";
reg = <0x520 0x20>;
tbi1: tbi-phy@11 {
reg = <0x11>;
device_type = "tbi-phy";
};
};
};
mpic: pic@40000 {
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <2>;
reg = <0x40000 0x40000>;
compatible = "chrp,open-pic";
device_type = "open-pic";
};
cpm@919c0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "fsl,mpc8560-cpm", "fsl,cpm2", "simple-bus";
reg = <0x919c0 0x30>;
ranges;
muram@80000 {
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x80000 0x10000>;
data@0 {
compatible = "fsl,cpm-muram-data";
reg = <0 0x4000 0x9000 0x2000>;
};
};
brg@919f0 {
compatible = "fsl,mpc8560-brg",
"fsl,cpm2-brg",
"fsl,cpm-brg";
reg = <0x919f0 0x10 0x915f0 0x10>;
clock-frequency = <0>;
};
cpmpic: pic@90c00 {
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <2>;
interrupts = <46 2>;
interrupt-parent = <&mpic>;
reg = <0x90c00 0x80>;
compatible = "fsl,mpc8560-cpm-pic", "fsl,cpm2-pic";
};
serial0: serial@91a20 {
device_type = "serial";
compatible = "fsl,mpc8560-scc-uart",
"fsl,cpm2-scc-uart";
reg = <0x91a20 0x20 0x88100 0x100>;
fsl,cpm-brg = <2>;
fsl,cpm-command = <0x4a00000>;
interrupts = <41 8>;
interrupt-parent = <&cpmpic>;
};
};
};
pci0: pci@fdf08000 {
interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
interrupt-map = <
/* IDSEL 0x0c */
0x6000 0 0 1 &mpic 1 1
0x6000 0 0 2 &mpic 2 1
0x6000 0 0 3 &mpic 3 1
0x6000 0 0 4 &mpic 4 1
/* IDSEL 0x0d */
0x6800 0 0 1 &mpic 4 1
0x6800 0 0 2 &mpic 1 1
0x6800 0 0 3 &mpic 2 1
0x6800 0 0 4 &mpic 3 1
/* IDSEL 0x0e */
0x7000 0 0 1 &mpic 3 1
0x7000 0 0 2 &mpic 4 1
0x7000 0 0 3 &mpic 1 1
0x7000 0 0 4 &mpic 2 1
/* IDSEL 0x0f */
0x7800 0 0 1 &mpic 2 1
0x7800 0 0 2 &mpic 3 1
0x7800 0 0 3 &mpic 4 1
0x7800 0 0 4 &mpic 1 1>;
interrupt-parent = <&mpic>;
interrupts = <24 2>;
bus-range = <0 0>;
ranges = <0x02000000 0 0x80000000 0x80000000 0 0x20000000
0x01000000 0 0x00000000 0xe2000000 0 0x00100000>;
clock-frequency = <66666666>;
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
reg = <0xfdf08000 0x1000>;
compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
device_type = "pci";
};
};
|
// SPDX-License-Identifier: GPL-2.0-only
#define pr_fmt(fmt) "efi: " fmt
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/string.h>
#include <linux/time.h>
#include <linux/types.h>
#include <linux/efi.h>
#include <linux/slab.h>
#include <linux/memblock.h>
#include <linux/acpi.h>
#include <linux/dmi.h>
#include <asm/e820/api.h>
#include <asm/efi.h>
#include <asm/uv/uv.h>
#include <asm/cpu_device_id.h>
#include <asm/realmode.h>
#include <asm/reboot.h>
#define EFI_MIN_RESERVE 5120
#define EFI_DUMMY_GUID \
EFI_GUID(0x4424ac57, 0xbe4b, 0x47dd, 0x9e, 0x97, 0xed, 0x50, 0xf0, 0x9f, 0x92, 0xa9)
#define QUARK_CSH_SIGNATURE 0x5f435348 /* _CSH */
#define QUARK_SECURITY_HEADER_SIZE 0x400
/*
* Header prepended to the standard EFI capsule on Quark systems the are based
* on Intel firmware BSP.
* @csh_signature: Unique identifier to sanity check signed module
* presence ("_CSH").
* @version: Current version of CSH used. Should be one for Quark A0.
* @modulesize: Size of the entire module including the module header
* and payload.
* @security_version_number_index: Index of SVN to use for validation of signed
* module.
* @security_version_number: Used to prevent against roll back of modules.
* @rsvd_module_id: Currently unused for Clanton (Quark).
* @rsvd_module_vendor: Vendor Identifier. For Intel products value is
* 0x00008086.
* @rsvd_date: BCD representation of build date as yyyymmdd, where
* yyyy=4 digit year, mm=1-12, dd=1-31.
* @headersize: Total length of the header including including any
* padding optionally added by the signing tool.
* @hash_algo: What Hash is used in the module signing.
* @cryp_algo: What Crypto is used in the module signing.
* @keysize: Total length of the key data including including any
* padding optionally added by the signing tool.
* @signaturesize: Total length of the signature including including any
* padding optionally added by the signing tool.
* @rsvd_next_header: 32-bit pointer to the next Secure Boot Module in the
* chain, if there is a next header.
* @rsvd: Reserved, padding structure to required size.
*
* See also QuartSecurityHeader_t in
* Quark_EDKII_v1.2.1.1/QuarkPlatformPkg/Include/QuarkBootRom.h
* from https://downloadcenter.intel.com/download/23197/Intel-Quark-SoC-X1000-Board-Support-Package-BSP
*/
struct quark_security_header {
u32 csh_signature;
u32 version;
u32 modulesize;
u32 security_version_number_index;
u32 security_version_number;
u32 rsvd_module_id;
u32 rsvd_module_vendor;
u32 rsvd_date;
u32 headersize;
u32 hash_algo;
u32 cryp_algo;
u32 keysize;
u32 signaturesize;
u32 rsvd_next_header;
u32 rsvd[2];
};
static const efi_char16_t efi_dummy_name[] = L"DUMMY";
static bool efi_no_storage_paranoia;
/*
* Some firmware implementations refuse to boot if there's insufficient
* space in the variable store. The implementation of garbage collection
* in some FW versions causes stale (deleted) variables to take up space
* longer than intended and space is only freed once the store becomes
* almost completely full.
*
* Enabling this option disables the space checks in
* efi_query_variable_store() and forces garbage collection.
*
* Only enable this option if deleting EFI variables does not free up
* space in your variable store, e.g. if despite deleting variables
* you're unable to create new ones.
*/
static int __init setup_storage_paranoia(char *arg)
{
efi_no_storage_paranoia = true;
return 0;
}
early_param("efi_no_storage_paranoia", setup_storage_paranoia);
/*
* Deleting the dummy variable which kicks off garbage collection
*/
void efi_delete_dummy_variable(void)
{
efi.set_variable_nonblocking((efi_char16_t *)efi_dummy_name,
&EFI_DUMMY_GUID,
EFI_VARIABLE_NON_VOLATILE |
EFI_VARIABLE_BOOTSERVICE_ACCESS |
EFI_VARIABLE_RUNTIME_ACCESS, 0, NULL);
}
u64 efivar_reserved_space(void)
{
if (efi_no_storage_paranoia)
return 0;
return EFI_MIN_RESERVE;
}
EXPORT_SYMBOL_GPL(efivar_reserved_space);
/*
* In the nonblocking case we do not attempt to perform garbage
* collection if we do not have enough free space. Rather, we do the
* bare minimum check and give up immediately if the available space
* is below EFI_MIN_RESERVE.
*
* This function is intended to be small and simple because it is
* invoked from crash handler paths.
*/
static efi_status_t
query_variable_store_nonblocking(u32 attributes, unsigned long size)
{
efi_status_t status;
u64 storage_size, remaining_size, max_size;
status = efi.query_variable_info_nonblocking(attributes, &storage_size,
&remaining_size,
&max_size);
if (status != EFI_SUCCESS)
return status;
if (remaining_size - size < EFI_MIN_RESERVE)
return EFI_OUT_OF_RESOURCES;
return EFI_SUCCESS;
}
/*
* Some firmware implementations refuse to boot if there's insufficient space
* in the variable store. Ensure that we never use more than a safe limit.
*
* Return EFI_SUCCESS if it is safe to write 'size' bytes to the variable
* store.
*/
efi_status_t efi_query_variable_store(u32 attributes, unsigned long size,
bool nonblocking)
{
efi_status_t status;
u64 storage_size, remaining_size, max_size;
if (!(attributes & EFI_VARIABLE_NON_VOLATILE))
return 0;
if (nonblocking)
return query_variable_store_nonblocking(attributes, size);
status = efi.query_variable_info(attributes, &storage_size,
&remaining_size, &max_size);
if (status != EFI_SUCCESS)
return status;
/*
* We account for that by refusing the write if permitting it would
* reduce the available space to under 5KB. This figure was provided by
* Samsung, so should be safe.
*/
if ((remaining_size - size < EFI_MIN_RESERVE) &&
!efi_no_storage_paranoia) {
/*
* Triggering garbage collection may require that the firmware
* generate a real EFI_OUT_OF_RESOURCES error. We can force
* that by attempting to use more space than is available.
*/
unsigned long dummy_size = remaining_size + 1024;
void *dummy = kzalloc(dummy_size, GFP_KERNEL);
if (!dummy)
return EFI_OUT_OF_RESOURCES;
status = efi.set_variable((efi_char16_t *)efi_dummy_name,
&EFI_DUMMY_GUID,
EFI_VARIABLE_NON_VOLATILE |
EFI_VARIABLE_BOOTSERVICE_ACCESS |
EFI_VARIABLE_RUNTIME_ACCESS,
dummy_size, dummy);
if (status == EFI_SUCCESS) {
/*
* This should have failed, so if it didn't make sure
* that we delete it...
*/
efi_delete_dummy_variable();
}
kfree(dummy);
/*
* The runtime code may now have triggered a garbage collection
* run, so check the variable info again
*/
status = efi.query_variable_info(attributes, &storage_size,
&remaining_size, &max_size);
if (status != EFI_SUCCESS)
return status;
/*
* There still isn't enough room, so return an error
*/
if (remaining_size - size < EFI_MIN_RESERVE)
return EFI_OUT_OF_RESOURCES;
}
return EFI_SUCCESS;
}
EXPORT_SYMBOL_GPL(efi_query_variable_store);
/*
* The UEFI specification makes it clear that the operating system is
* free to do whatever it wants with boot services code after
* ExitBootServices() has been called. Ignoring this recommendation a
* significant bunch of EFI implementations continue calling into boot
* services code (SetVirtualAddressMap). In order to work around such
* buggy implementations we reserve boot services region during EFI
* init and make sure it stays executable. Then, after
* SetVirtualAddressMap(), it is discarded.
*
* However, some boot services regions contain data that is required
* by drivers, so we need to track which memory ranges can never be
* freed. This is done by tagging those regions with the
* EFI_MEMORY_RUNTIME attribute.
*
* Any driver that wants to mark a region as reserved must use
* efi_mem_reserve() which will insert a new EFI memory descriptor
* into efi.memmap (splitting existing regions if necessary) and tag
* it with EFI_MEMORY_RUNTIME.
*/
void __init efi_arch_mem_reserve(phys_addr_t addr, u64 size)
{
struct efi_memory_map_data data = { 0 };
struct efi_mem_range mr;
efi_memory_desc_t md;
int num_entries;
void *new;
if (efi_mem_desc_lookup(addr, &md) ||
md.type != EFI_BOOT_SERVICES_DATA) {
pr_err("Failed to lookup EFI memory descriptor for %pa\n", &addr);
return;
}
if (addr + size > md.phys_addr + (md.num_pages << EFI_PAGE_SHIFT)) {
pr_err("Region spans EFI memory descriptors, %pa\n", &addr);
return;
}
size += addr % EFI_PAGE_SIZE;
size = round_up(size, EFI_PAGE_SIZE);
addr = round_down(addr, EFI_PAGE_SIZE);
mr.range.start = addr;
mr.range.end = addr + size - 1;
mr.attribute = md.attribute | EFI_MEMORY_RUNTIME;
num_entries = efi_memmap_split_count(&md, &mr.range);
num_entries += efi.memmap.nr_map;
if (efi_memmap_alloc(num_entries, &data) != 0) {
pr_err("Could not allocate boot services memmap\n");
return;
}
new = early_memremap_prot(data.phys_map, data.size,
pgprot_val(pgprot_encrypted(FIXMAP_PAGE_NORMAL)));
if (!new) {
pr_err("Failed to map new boot services memmap\n");
return;
}
efi_memmap_insert(&efi.memmap, new, &mr);
early_memunmap(new, data.size);
efi_memmap_install(&data);
e820__range_update(addr, size, E820_TYPE_RAM, E820_TYPE_RESERVED);
e820__update_table(e820_table);
}
/*
* Helper function for efi_reserve_boot_services() to figure out if we
* can free regions in efi_free_boot_services().
*
* Use this function to ensure we do not free regions owned by somebody
* else. We must only reserve (and then free) regions:
*
* - Not within any part of the kernel
* - Not the BIOS reserved area (E820_TYPE_RESERVED, E820_TYPE_NVS, etc)
*/
static __init bool can_free_region(u64 start, u64 size)
{
if (start + size > __pa_symbol(_text) && start <= __pa_symbol(_end))
return false;
if (!e820__mapped_all(start, start+size, E820_TYPE_RAM))
return false;
return true;
}
void __init efi_reserve_boot_services(void)
{
efi_memory_desc_t *md;
if (!efi_enabled(EFI_MEMMAP))
return;
for_each_efi_memory_desc(md) {
u64 start = md->phys_addr;
u64 size = md->num_pages << EFI_PAGE_SHIFT;
bool already_reserved;
if (md->type != EFI_BOOT_SERVICES_CODE &&
md->type != EFI_BOOT_SERVICES_DATA)
continue;
already_reserved = memblock_is_region_reserved(start, size);
/*
* Because the following memblock_reserve() is paired
* with memblock_free_late() for this region in
* efi_free_boot_services(), we must be extremely
* careful not to reserve, and subsequently free,
* critical regions of memory (like the kernel image) or
* those regions that somebody else has already
* reserved.
*
* A good example of a critical region that must not be
* freed is page zero (first 4Kb of memory), which may
* contain boot services code/data but is marked
* E820_TYPE_RESERVED by trim_bios_range().
*/
if (!already_reserved) {
memblock_reserve(start, size);
/*
* If we are the first to reserve the region, no
* one else cares about it. We own it and can
* free it later.
*/
if (can_free_region(start, size))
continue;
}
/*
* We don't own the region. We must not free it.
*
* Setting this bit for a boot services region really
* doesn't make sense as far as the firmware is
* concerned, but it does provide us with a way to tag
* those regions that must not be paired with
* memblock_free_late().
*/
md->attribute |= EFI_MEMORY_RUNTIME;
}
}
/*
* Apart from having VA mappings for EFI boot services code/data regions,
* (duplicate) 1:1 mappings were also created as a quirk for buggy firmware. So,
* unmap both 1:1 and VA mappings.
*/
static void __init efi_unmap_pages(efi_memory_desc_t *md)
{
pgd_t *pgd = efi_mm.pgd;
u64 pa = md->phys_addr;
u64 va = md->virt_addr;
/*
* EFI mixed mode has all RAM mapped to access arguments while making
* EFI runtime calls, hence don't unmap EFI boot services code/data
* regions.
*/
if (efi_is_mixed())
return;
if (kernel_unmap_pages_in_pgd(pgd, pa, md->num_pages))
pr_err("Failed to unmap 1:1 mapping for 0x%llx\n", pa);
if (kernel_unmap_pages_in_pgd(pgd, va, md->num_pages))
pr_err("Failed to unmap VA mapping for 0x%llx\n", va);
}
void __init efi_free_boot_services(void)
{
struct efi_memory_map_data data = { 0 };
efi_memory_desc_t *md;
int num_entries = 0;
void *new, *new_md;
/* Keep all regions for /sys/kernel/debug/efi */
if (efi_enabled(EFI_DBG))
return;
for_each_efi_memory_desc(md) {
unsigned long long start = md->phys_addr;
unsigned long long size = md->num_pages << EFI_PAGE_SHIFT;
size_t rm_size;
if (md->type != EFI_BOOT_SERVICES_CODE &&
md->type != EFI_BOOT_SERVICES_DATA) {
num_entries++;
continue;
}
/* Do not free, someone else owns it: */
if (md->attribute & EFI_MEMORY_RUNTIME) {
num_entries++;
continue;
}
/*
* Before calling set_virtual_address_map(), EFI boot services
* code/data regions were mapped as a quirk for buggy firmware.
* Unmap them from efi_pgd before freeing them up.
*/
efi_unmap_pages(md);
/*
* Nasty quirk: if all sub-1MB memory is used for boot
* services, we can get here without having allocated the
* real mode trampoline. It's too late to hand boot services
* memory back to the memblock allocator, so instead
* try to manually allocate the trampoline if needed.
*
* I've seen this on a Dell XPS 13 9350 with firmware
* 1.4.4 with SGX enabled booting Linux via Fedora 24's
* grub2-efi on a hard disk. (And no, I don't know why
* this happened, but Linux should still try to boot rather
* panicking early.)
*/
rm_size = real_mode_size_needed();
if (rm_size && (start + rm_size) < (1<<20) && size >= rm_size) {
set_real_mode_mem(start);
start += rm_size;
size -= rm_size;
}
/*
* Don't free memory under 1M for two reasons:
* - BIOS might clobber it
* - Crash kernel needs it to be reserved
*/
if (start + size < SZ_1M)
continue;
if (start < SZ_1M) {
size -= (SZ_1M - start);
start = SZ_1M;
}
memblock_free_late(start, size);
}
if (!num_entries)
return;
if (efi_memmap_alloc(num_entries, &data) != 0) {
pr_err("Failed to allocate new EFI memmap\n");
return;
}
new = memremap(data.phys_map, data.size, MEMREMAP_WB);
if (!new) {
pr_err("Failed to map new EFI memmap\n");
return;
}
/*
* Build a new EFI memmap that excludes any boot services
* regions that are not tagged EFI_MEMORY_RUNTIME, since those
* regions have now been freed.
*/
new_md = new;
for_each_efi_memory_desc(md) {
if (!(md->attribute & EFI_MEMORY_RUNTIME) &&
(md->type == EFI_BOOT_SERVICES_CODE ||
md->type == EFI_BOOT_SERVICES_DATA))
continue;
memcpy(new_md, md, efi.memmap.desc_size);
new_md += efi.memmap.desc_size;
}
memunmap(new);
if (efi_memmap_install(&data) != 0) {
pr_err("Could not install new EFI memmap\n");
return;
}
}
/*
* A number of config table entries get remapped to virtual addresses
* after entering EFI virtual mode. However, the kexec kernel requires
* their physical addresses therefore we pass them via setup_data and
* correct those entries to their respective physical addresses here.
*
* Currently only handles smbios which is necessary for some firmware
* implementation.
*/
int __init efi_reuse_config(u64 tables, int nr_tables)
{
int i, sz, ret = 0;
void *p, *tablep;
struct efi_setup_data *data;
if (nr_tables == 0)
return 0;
if (!efi_setup)
return 0;
if (!efi_enabled(EFI_64BIT))
return 0;
data = early_memremap(efi_setup, sizeof(*data));
if (!data) {
ret = -ENOMEM;
goto out;
}
if (!data->smbios)
goto out_memremap;
sz = sizeof(efi_config_table_64_t);
p = tablep = early_memremap(tables, nr_tables * sz);
if (!p) {
pr_err("Could not map Configuration table!\n");
ret = -ENOMEM;
goto out_memremap;
}
for (i = 0; i < nr_tables; i++) {
efi_guid_t guid;
guid = ((efi_config_table_64_t *)p)->guid;
if (!efi_guidcmp(guid, SMBIOS_TABLE_GUID))
((efi_config_table_64_t *)p)->table = data->smbios;
p += sz;
}
early_memunmap(tablep, nr_tables * sz);
out_memremap:
early_memunmap(data, sizeof(*data));
out:
return ret;
}
void __init efi_apply_memmap_quirks(void)
{
/*
* Once setup is done earlier, unmap the EFI memory map on mismatched
* firmware/kernel architectures since there is no support for runtime
* services.
*/
if (!efi_runtime_supported()) {
pr_info("Setup done, disabling due to 32/64-bit mismatch\n");
efi_memmap_unmap();
}
}
/*
* For most modern platforms the preferred method of powering off is via
* ACPI. However, there are some that are known to require the use of
* EFI runtime services and for which ACPI does not work at all.
*
* Using EFI is a last resort, to be used only if no other option
* exists.
*/
bool efi_reboot_required(void)
{
if (!acpi_gbl_reduced_hardware)
return false;
efi_reboot_quirk_mode = EFI_RESET_WARM;
return true;
}
bool efi_poweroff_required(void)
{
return acpi_gbl_reduced_hardware || acpi_no_s5;
}
#ifdef CONFIG_EFI_CAPSULE_QUIRK_QUARK_CSH
static int qrk_capsule_setup_info(struct capsule_info *cap_info, void **pkbuff,
size_t hdr_bytes)
{
struct quark_security_header *csh = *pkbuff;
/* Only process data block that is larger than the security header */
if (hdr_bytes < sizeof(struct quark_security_header))
return 0;
if (csh->csh_signature != QUARK_CSH_SIGNATURE ||
csh->headersize != QUARK_SECURITY_HEADER_SIZE)
return 1;
/* Only process data block if EFI header is included */
if (hdr_bytes < QUARK_SECURITY_HEADER_SIZE +
sizeof(efi_capsule_header_t))
return 0;
pr_debug("Quark security header detected\n");
if (csh->rsvd_next_header != 0) {
pr_err("multiple Quark security headers not supported\n");
return -EINVAL;
}
*pkbuff += csh->headersize;
cap_info->total_size = csh->headersize;
/*
* Update the first page pointer to skip over the CSH header.
*/
cap_info->phys[0] += csh->headersize;
/*
* cap_info->capsule should point at a virtual mapping of the entire
* capsule, starting at the capsule header. Our image has the Quark
* security header prepended, so we cannot rely on the default vmap()
* mapping created by the generic capsule code.
* Given that the Quark firmware does not appear to care about the
* virtual mapping, let's just point cap_info->capsule at our copy
* of the capsule header.
*/
cap_info->capsule = &cap_info->header;
return 1;
}
static const struct x86_cpu_id efi_capsule_quirk_ids[] = {
X86_MATCH_VFM(INTEL_QUARK_X1000, &qrk_capsule_setup_info),
{ }
};
int efi_capsule_setup_info(struct capsule_info *cap_info, void *kbuff,
size_t hdr_bytes)
{
int (*quirk_handler)(struct capsule_info *, void **, size_t);
const struct x86_cpu_id *id;
int ret;
if (hdr_bytes < sizeof(efi_capsule_header_t))
return 0;
cap_info->total_size = 0;
id = x86_match_cpu(efi_capsule_quirk_ids);
if (id) {
/*
* The quirk handler is supposed to return
* - a value > 0 if the setup should continue, after advancing
* kbuff as needed
* - 0 if not enough hdr_bytes are available yet
* - a negative error code otherwise
*/
quirk_handler = (typeof(quirk_handler))id->driver_data;
ret = quirk_handler(cap_info, &kbuff, hdr_bytes);
if (ret <= 0)
return ret;
}
memcpy(&cap_info->header, kbuff, sizeof(cap_info->header));
cap_info->total_size += cap_info->header.imagesize;
return __efi_capsule_setup_info(cap_info);
}
#endif
/*
* If any access by any efi runtime service causes a page fault, then,
* 1. If it's efi_reset_system(), reboot through BIOS.
* 2. If any other efi runtime service, then
* a. Return error status to the efi caller process.
* b. Disable EFI Runtime Services forever and
* c. Freeze efi_rts_wq and schedule new process.
*
* @return: Returns, if the page fault is not handled. This function
* will never return if the page fault is handled successfully.
*/
void efi_crash_gracefully_on_page_fault(unsigned long phys_addr)
{
if (!IS_ENABLED(CONFIG_X86_64))
return;
/*
* If we get an interrupt/NMI while processing an EFI runtime service
* then this is a regular OOPS, not an EFI failure.
*/
if (in_interrupt())
return;
/*
* Make sure that an efi runtime service caused the page fault.
* READ_ONCE() because we might be OOPSing in a different thread,
* and we don't want to trip KTSAN while trying to OOPS.
*/
if (READ_ONCE(efi_rts_work.efi_rts_id) == EFI_NONE ||
current_work() != &efi_rts_work.work)
return;
/*
* Address range 0x0000 - 0x0fff is always mapped in the efi_pgd, so
* page faulting on these addresses isn't expected.
*/
if (phys_addr <= 0x0fff)
return;
/*
* Print stack trace as it might be useful to know which EFI Runtime
* Service is buggy.
*/
WARN(1, FW_BUG "Page fault caused by firmware at PA: 0x%lx\n",
phys_addr);
/*
* Buggy efi_reset_system() is handled differently from other EFI
* Runtime Services as it doesn't use efi_rts_wq. Although,
* native_machine_emergency_restart() says that machine_real_restart()
* could fail, it's better not to complicate this fault handler
* because this case occurs *very* rarely and hence could be improved
* on a need by basis.
*/
if (efi_rts_work.efi_rts_id == EFI_RESET_SYSTEM) {
pr_info("efi_reset_system() buggy! Reboot through BIOS\n");
machine_real_restart(MRR_BIOS);
return;
}
/*
* Before calling EFI Runtime Service, the kernel has switched the
* calling process to efi_mm. Hence, switch back to task_mm.
*/
arch_efi_call_virt_teardown();
/* Signal error status to the efi caller process */
efi_rts_work.status = EFI_ABORTED;
complete(&efi_rts_work.efi_rts_comp);
clear_bit(EFI_RUNTIME_SERVICES, &efi.flags);
pr_info("Froze efi_rts_wq and disabled EFI Runtime Services\n");
/*
* Call schedule() in an infinite loop, so that any spurious wake ups
* will never run efi_rts_wq again.
*/
for (;;) {
set_current_state(TASK_IDLE);
schedule();
}
}
|
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Support for Intel Camera Imaging ISP subsystem.
* Copyright (c) 2015, Intel Corporation.
*/
#ifndef _SH_CSS_SP_H_
#define _SH_CSS_SP_H_
#include <system_global.h>
#include <type_support.h>
#include "input_formatter.h"
#include "ia_css_binary.h"
#include "ia_css_types.h"
#include "ia_css_pipeline.h"
/* Function to initialize the data and bss section descr of the binary */
void
sh_css_sp_store_init_dmem(const struct ia_css_fw_info *fw);
void
store_sp_stage_data(enum ia_css_pipe_id id, unsigned int pipe_num,
unsigned int stage);
void
sh_css_stage_write_binary_info(struct ia_css_binary_info *info);
void
store_sp_group_data(void);
/* Start binary (jpeg) copy on the SP */
void
sh_css_sp_start_binary_copy(unsigned int pipe_num,
struct ia_css_frame *out_frame,
unsigned int two_ppc);
unsigned int
sh_css_sp_get_binary_copy_size(void);
/* Return the value of a SW interrupt */
unsigned int
sh_css_sp_get_sw_interrupt_value(unsigned int irq);
void
sh_css_sp_init_pipeline(struct ia_css_pipeline *me,
enum ia_css_pipe_id id,
u8 pipe_num,
bool xnr,
bool two_ppc,
bool continuous,
bool offline,
unsigned int required_bds_factor,
enum sh_css_pipe_config_override copy_ovrd,
enum ia_css_input_mode input_mode,
const struct ia_css_metadata_config *md_config,
const struct ia_css_metadata_info *md_info,
const enum mipi_port_id port_id);
void
sh_css_sp_uninit_pipeline(unsigned int pipe_num);
bool sh_css_write_host2sp_command(enum host2sp_commands host2sp_command);
enum host2sp_commands
sh_css_read_host2sp_command(void);
void
sh_css_init_host2sp_frame_data(void);
/**
* @brief Update the offline frame information in host_sp_communication.
*
* @param[in] frame_num The offline frame number.
* @param[in] frame The pointer to the offline frame.
*/
void
sh_css_update_host2sp_offline_frame(
unsigned int frame_num,
struct ia_css_frame *frame,
struct ia_css_metadata *metadata);
/**
* @brief Update the mipi frame information in host_sp_communication.
*
* @param[in] frame_num The mipi frame number.
* @param[in] frame The pointer to the mipi frame.
*/
void
sh_css_update_host2sp_mipi_frame(
unsigned int frame_num,
struct ia_css_frame *frame);
/**
* @brief Update the mipi metadata information in host_sp_communication.
*
* @param[in] frame_num The mipi frame number.
* @param[in] metadata The pointer to the mipi metadata.
*/
void
sh_css_update_host2sp_mipi_metadata(
unsigned int frame_num,
struct ia_css_metadata *metadata);
/**
* @brief Update the nr of mipi frames to use in host_sp_communication.
*
* @param[in] num_frames The number of mipi frames to use.
*/
void
sh_css_update_host2sp_num_mipi_frames(unsigned int num_frames);
/**
* @brief Update the nr of offline frames to use in host_sp_communication.
*
* @param[in] num_frames The number of raw frames to use.
*/
void
sh_css_update_host2sp_cont_num_raw_frames(unsigned int num_frames,
bool set_avail);
void
sh_css_event_init_irq_mask(void);
void
sh_css_sp_start_isp(void);
void
sh_css_sp_set_sp_running(bool flag);
bool
sh_css_sp_is_running(void);
#if SP_DEBUG != SP_DEBUG_NONE
void
sh_css_sp_get_debug_state(struct sh_css_sp_debug_state *state);
#endif
void
sh_css_sp_set_if_configs(
const input_formatter_cfg_t *config_a,
const input_formatter_cfg_t *config_b,
const uint8_t if_config_index);
void
sh_css_sp_program_input_circuit(int fmt_type,
int ch_id,
enum ia_css_input_mode input_mode);
void
sh_css_sp_configure_sync_gen(int width,
int height,
int hblank_cycles,
int vblank_cycles);
void
sh_css_sp_configure_prbs(int seed);
void
sh_css_sp_configure_enable_raw_pool_locking(bool lock_all);
void
sh_css_sp_enable_isys_event_queue(bool enable);
void
sh_css_sp_set_disable_continuous_viewfinder(bool flag);
void
sh_css_sp_reset_global_vars(void);
/**
* @brief Initialize the DMA software-mask in the debug mode.
* This API should be ONLY called in the debugging mode.
* And it should be always called before the first call of
* "sh_css_set_dma_sw_reg(...)".
*
* @param[in] dma_id The ID of the target DMA.
*
* @return
* - true, if it is successful.
* - false, otherwise.
*/
bool
sh_css_sp_init_dma_sw_reg(int dma_id);
/**
* @brief Set the DMA software-mask in the debug mode.
* This API should be ONLYL called in the debugging mode. Must
* call "sh_css_set_dma_sw_reg(...)" before this
* API is called for the first time.
*
* @param[in] dma_id The ID of the target DMA.
* @param[in] channel_id The ID of the target DMA channel.
* @param[in] request_type The type of the DMA request.
* For example:
* - "0" indicates the writing request.
* - "1" indicates the reading request.
*
* @param[in] enable If it is "true", the target DMA
* channel is enabled in the software.
* Otherwise, the target DMA channel
* is disabled in the software.
*
* @return
* - true, if it is successful.
* - false, otherwise.
*/
bool
sh_css_sp_set_dma_sw_reg(int dma_id,
int channel_id,
int request_type,
bool enable);
extern struct sh_css_sp_group sh_css_sp_group;
extern struct sh_css_sp_stage sh_css_sp_stage;
extern struct sh_css_isp_stage sh_css_isp_stage;
#endif /* _SH_CSS_SP_H_ */
|
// SPDX-License-Identifier: GPL-2.0-only
/* Copyright(c) 2023 Intel Corporation */
#include "adf_accel_devices.h"
#include "adf_cfg.h"
#include "adf_cfg_services.h"
#include "adf_cfg_strings.h"
#include "adf_common_drv.h"
#include "adf_gen4_config.h"
#include "adf_heartbeat.h"
#include "adf_transport_access_macros.h"
#include "qat_compression.h"
#include "qat_crypto.h"
static int adf_crypto_dev_config(struct adf_accel_dev *accel_dev)
{
char key[ADF_CFG_MAX_KEY_LEN_IN_BYTES];
int banks = GET_MAX_BANKS(accel_dev);
int cpus = num_online_cpus();
unsigned long bank, val;
int instances;
int ret;
int i;
if (adf_hw_dev_has_crypto(accel_dev))
instances = min(cpus, banks / 2);
else
instances = 0;
for (i = 0; i < instances; i++) {
val = i;
bank = i * 2;
snprintf(key, sizeof(key), ADF_CY "%d" ADF_RING_ASYM_BANK_NUM, i);
ret = adf_cfg_add_key_value_param(accel_dev, ADF_KERNEL_SEC,
key, &bank, ADF_DEC);
if (ret)
goto err;
bank += 1;
snprintf(key, sizeof(key), ADF_CY "%d" ADF_RING_SYM_BANK_NUM, i);
ret = adf_cfg_add_key_value_param(accel_dev, ADF_KERNEL_SEC,
key, &bank, ADF_DEC);
if (ret)
goto err;
snprintf(key, sizeof(key), ADF_CY "%d" ADF_ETRMGR_CORE_AFFINITY,
i);
ret = adf_cfg_add_key_value_param(accel_dev, ADF_KERNEL_SEC,
key, &val, ADF_DEC);
if (ret)
goto err;
snprintf(key, sizeof(key), ADF_CY "%d" ADF_RING_ASYM_SIZE, i);
val = 128;
ret = adf_cfg_add_key_value_param(accel_dev, ADF_KERNEL_SEC,
key, &val, ADF_DEC);
if (ret)
goto err;
val = 512;
snprintf(key, sizeof(key), ADF_CY "%d" ADF_RING_SYM_SIZE, i);
ret = adf_cfg_add_key_value_param(accel_dev, ADF_KERNEL_SEC,
key, &val, ADF_DEC);
if (ret)
goto err;
val = 0;
snprintf(key, sizeof(key), ADF_CY "%d" ADF_RING_ASYM_TX, i);
ret = adf_cfg_add_key_value_param(accel_dev, ADF_KERNEL_SEC,
key, &val, ADF_DEC);
if (ret)
goto err;
val = 0;
snprintf(key, sizeof(key), ADF_CY "%d" ADF_RING_SYM_TX, i);
ret = adf_cfg_add_key_value_param(accel_dev, ADF_KERNEL_SEC,
key, &val, ADF_DEC);
if (ret)
goto err;
val = 1;
snprintf(key, sizeof(key), ADF_CY "%d" ADF_RING_ASYM_RX, i);
ret = adf_cfg_add_key_value_param(accel_dev, ADF_KERNEL_SEC,
key, &val, ADF_DEC);
if (ret)
goto err;
val = 1;
snprintf(key, sizeof(key), ADF_CY "%d" ADF_RING_SYM_RX, i);
ret = adf_cfg_add_key_value_param(accel_dev, ADF_KERNEL_SEC,
key, &val, ADF_DEC);
if (ret)
goto err;
val = ADF_COALESCING_DEF_TIME;
snprintf(key, sizeof(key), ADF_ETRMGR_COALESCE_TIMER_FORMAT, i);
ret = adf_cfg_add_key_value_param(accel_dev, "Accelerator0",
key, &val, ADF_DEC);
if (ret)
goto err;
}
val = i;
ret = adf_cfg_add_key_value_param(accel_dev, ADF_KERNEL_SEC, ADF_NUM_CY,
&val, ADF_DEC);
if (ret)
goto err;
val = 0;
ret = adf_cfg_add_key_value_param(accel_dev, ADF_KERNEL_SEC, ADF_NUM_DC,
&val, ADF_DEC);
if (ret)
goto err;
return 0;
err:
dev_err(&GET_DEV(accel_dev), "Failed to add configuration for crypto\n");
return ret;
}
static int adf_comp_dev_config(struct adf_accel_dev *accel_dev)
{
char key[ADF_CFG_MAX_KEY_LEN_IN_BYTES];
int banks = GET_MAX_BANKS(accel_dev);
int cpus = num_online_cpus();
unsigned long val;
int instances;
int ret;
int i;
if (adf_hw_dev_has_compression(accel_dev))
instances = min(cpus, banks);
else
instances = 0;
for (i = 0; i < instances; i++) {
val = i;
snprintf(key, sizeof(key), ADF_DC "%d" ADF_RING_DC_BANK_NUM, i);
ret = adf_cfg_add_key_value_param(accel_dev, ADF_KERNEL_SEC,
key, &val, ADF_DEC);
if (ret)
goto err;
val = 512;
snprintf(key, sizeof(key), ADF_DC "%d" ADF_RING_DC_SIZE, i);
ret = adf_cfg_add_key_value_param(accel_dev, ADF_KERNEL_SEC,
key, &val, ADF_DEC);
if (ret)
goto err;
val = 0;
snprintf(key, sizeof(key), ADF_DC "%d" ADF_RING_DC_TX, i);
ret = adf_cfg_add_key_value_param(accel_dev, ADF_KERNEL_SEC,
key, &val, ADF_DEC);
if (ret)
goto err;
val = 1;
snprintf(key, sizeof(key), ADF_DC "%d" ADF_RING_DC_RX, i);
ret = adf_cfg_add_key_value_param(accel_dev, ADF_KERNEL_SEC,
key, &val, ADF_DEC);
if (ret)
goto err;
val = ADF_COALESCING_DEF_TIME;
snprintf(key, sizeof(key), ADF_ETRMGR_COALESCE_TIMER_FORMAT, i);
ret = adf_cfg_add_key_value_param(accel_dev, "Accelerator0",
key, &val, ADF_DEC);
if (ret)
goto err;
}
val = i;
ret = adf_cfg_add_key_value_param(accel_dev, ADF_KERNEL_SEC, ADF_NUM_DC,
&val, ADF_DEC);
if (ret)
goto err;
val = 0;
ret = adf_cfg_add_key_value_param(accel_dev, ADF_KERNEL_SEC, ADF_NUM_CY,
&val, ADF_DEC);
if (ret)
goto err;
return 0;
err:
dev_err(&GET_DEV(accel_dev), "Failed to add configuration for compression\n");
return ret;
}
static int adf_no_dev_config(struct adf_accel_dev *accel_dev)
{
unsigned long val;
int ret;
val = 0;
ret = adf_cfg_add_key_value_param(accel_dev, ADF_KERNEL_SEC, ADF_NUM_DC,
&val, ADF_DEC);
if (ret)
return ret;
return adf_cfg_add_key_value_param(accel_dev, ADF_KERNEL_SEC, ADF_NUM_CY,
&val, ADF_DEC);
}
/**
* adf_gen4_dev_config() - create dev config required to create instances
*
* @accel_dev: Pointer to acceleration device.
*
* Function creates device configuration required to create instances
*
* Return: 0 on success, error code otherwise.
*/
int adf_gen4_dev_config(struct adf_accel_dev *accel_dev)
{
char services[ADF_CFG_MAX_VAL_LEN_IN_BYTES] = {0};
int ret;
ret = adf_cfg_section_add(accel_dev, ADF_KERNEL_SEC);
if (ret)
goto err;
ret = adf_cfg_section_add(accel_dev, "Accelerator0");
if (ret)
goto err;
ret = adf_cfg_get_param_value(accel_dev, ADF_GENERAL_SEC,
ADF_SERVICES_ENABLED, services);
if (ret)
goto err;
ret = sysfs_match_string(adf_cfg_services, services);
if (ret < 0)
goto err;
switch (ret) {
case SVC_CY:
case SVC_CY2:
ret = adf_crypto_dev_config(accel_dev);
break;
case SVC_DC:
case SVC_DCC:
ret = adf_comp_dev_config(accel_dev);
break;
default:
ret = adf_no_dev_config(accel_dev);
break;
}
if (ret)
goto err;
set_bit(ADF_STATUS_CONFIGURED, &accel_dev->status);
return ret;
err:
dev_err(&GET_DEV(accel_dev), "Failed to configure QAT driver\n");
return ret;
}
EXPORT_SYMBOL_GPL(adf_gen4_dev_config);
int adf_gen4_cfg_dev_init(struct adf_accel_dev *accel_dev)
{
const char *config;
int ret;
config = accel_dev->accel_id % 2 ? ADF_CFG_DC : ADF_CFG_CY;
ret = adf_cfg_section_add(accel_dev, ADF_GENERAL_SEC);
if (ret)
return ret;
/* Default configuration is crypto only for even devices
* and compression for odd devices
*/
ret = adf_cfg_add_key_value_param(accel_dev, ADF_GENERAL_SEC,
ADF_SERVICES_ENABLED, config,
ADF_STR);
if (ret)
return ret;
adf_heartbeat_save_cfg_param(accel_dev, ADF_CFG_HB_TIMER_MIN_MS);
return 0;
}
EXPORT_SYMBOL_GPL(adf_gen4_cfg_dev_init);
|
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include <linux/clk-provider.h>
#include <linux/mod_devicetable.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <dt-bindings/clock/qcom,sm8550-gpucc.h>
#include "clk-alpha-pll.h"
#include "clk-branch.h"
#include "clk-rcg.h"
#include "clk-regmap.h"
#include "clk-regmap-divider.h"
#include "common.h"
#include "gdsc.h"
#include "reset.h"
enum {
DT_BI_TCXO,
DT_GPLL0_OUT_MAIN,
DT_GPLL0_OUT_MAIN_DIV,
};
enum {
P_BI_TCXO,
P_GPLL0_OUT_MAIN,
P_GPLL0_OUT_MAIN_DIV,
P_GPU_CC_PLL0_OUT_MAIN,
P_GPU_CC_PLL1_OUT_MAIN,
};
static const struct pll_vco lucid_ole_vco[] = {
{ 249600000, 2000000000, 0 },
};
static const struct alpha_pll_config gpu_cc_pll0_config = {
.l = 0x1e,
.alpha = 0xbaaa,
.config_ctl_val = 0x20485699,
.config_ctl_hi_val = 0x00182261,
.config_ctl_hi1_val = 0x82aa299c,
.test_ctl_val = 0x00000000,
.test_ctl_hi_val = 0x00000003,
.test_ctl_hi1_val = 0x00009000,
.test_ctl_hi2_val = 0x00000034,
.user_ctl_val = 0x00000000,
.user_ctl_hi_val = 0x00000005,
};
static struct clk_alpha_pll gpu_cc_pll0 = {
.offset = 0x0,
.vco_table = lucid_ole_vco,
.num_vco = ARRAY_SIZE(lucid_ole_vco),
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
.clkr = {
.hw.init = &(const struct clk_init_data) {
.name = "gpu_cc_pll0",
.parent_data = &(const struct clk_parent_data) {
.index = DT_BI_TCXO,
},
.num_parents = 1,
.ops = &clk_alpha_pll_lucid_evo_ops,
},
},
};
static const struct alpha_pll_config gpu_cc_pll1_config = {
.l = 0x16,
.alpha = 0xeaaa,
.config_ctl_val = 0x20485699,
.config_ctl_hi_val = 0x00182261,
.config_ctl_hi1_val = 0x82aa299c,
.test_ctl_val = 0x00000000,
.test_ctl_hi_val = 0x00000003,
.test_ctl_hi1_val = 0x00009000,
.test_ctl_hi2_val = 0x00000034,
.user_ctl_val = 0x00000000,
.user_ctl_hi_val = 0x00000005,
};
static struct clk_alpha_pll gpu_cc_pll1 = {
.offset = 0x1000,
.vco_table = lucid_ole_vco,
.num_vco = ARRAY_SIZE(lucid_ole_vco),
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
.clkr = {
.hw.init = &(const struct clk_init_data) {
.name = "gpu_cc_pll1",
.parent_data = &(const struct clk_parent_data) {
.index = DT_BI_TCXO,
},
.num_parents = 1,
.ops = &clk_alpha_pll_lucid_evo_ops,
},
},
};
static const struct parent_map gpu_cc_parent_map_0[] = {
{ P_BI_TCXO, 0 },
{ P_GPLL0_OUT_MAIN, 5 },
{ P_GPLL0_OUT_MAIN_DIV, 6 },
};
static const struct clk_parent_data gpu_cc_parent_data_0[] = {
{ .index = DT_BI_TCXO },
{ .index = DT_GPLL0_OUT_MAIN },
{ .index = DT_GPLL0_OUT_MAIN_DIV },
};
static const struct parent_map gpu_cc_parent_map_1[] = {
{ P_BI_TCXO, 0 },
{ P_GPU_CC_PLL0_OUT_MAIN, 1 },
{ P_GPU_CC_PLL1_OUT_MAIN, 3 },
{ P_GPLL0_OUT_MAIN, 5 },
{ P_GPLL0_OUT_MAIN_DIV, 6 },
};
static const struct clk_parent_data gpu_cc_parent_data_1[] = {
{ .index = DT_BI_TCXO },
{ .hw = &gpu_cc_pll0.clkr.hw },
{ .hw = &gpu_cc_pll1.clkr.hw },
{ .index = DT_GPLL0_OUT_MAIN },
{ .index = DT_GPLL0_OUT_MAIN_DIV },
};
static const struct parent_map gpu_cc_parent_map_2[] = {
{ P_BI_TCXO, 0 },
{ P_GPU_CC_PLL1_OUT_MAIN, 3 },
{ P_GPLL0_OUT_MAIN, 5 },
{ P_GPLL0_OUT_MAIN_DIV, 6 },
};
static const struct clk_parent_data gpu_cc_parent_data_2[] = {
{ .index = DT_BI_TCXO },
{ .hw = &gpu_cc_pll1.clkr.hw },
{ .index = DT_GPLL0_OUT_MAIN },
{ .index = DT_GPLL0_OUT_MAIN_DIV },
};
static const struct parent_map gpu_cc_parent_map_3[] = {
{ P_BI_TCXO, 0 },
};
static const struct clk_parent_data gpu_cc_parent_data_3[] = {
{ .index = DT_BI_TCXO },
};
static const struct freq_tbl ftbl_gpu_cc_ff_clk_src[] = {
F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
{ }
};
static struct clk_rcg2 gpu_cc_ff_clk_src = {
.cmd_rcgr = 0x9474,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gpu_cc_parent_map_0,
.freq_tbl = ftbl_gpu_cc_ff_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gpu_cc_ff_clk_src",
.parent_data = gpu_cc_parent_data_0,
.num_parents = ARRAY_SIZE(gpu_cc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
};
static const struct freq_tbl ftbl_gpu_cc_gmu_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
F(220000000, P_GPU_CC_PLL1_OUT_MAIN, 2, 0, 0),
F(550000000, P_GPU_CC_PLL1_OUT_MAIN, 2, 0, 0),
{ }
};
static struct clk_rcg2 gpu_cc_gmu_clk_src = {
.cmd_rcgr = 0x9318,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gpu_cc_parent_map_1,
.freq_tbl = ftbl_gpu_cc_gmu_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gpu_cc_gmu_clk_src",
.parent_data = gpu_cc_parent_data_1,
.num_parents = ARRAY_SIZE(gpu_cc_parent_data_1),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
};
static const struct freq_tbl ftbl_gpu_cc_hub_clk_src[] = {
F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0),
F(400000000, P_GPLL0_OUT_MAIN, 1.5, 0, 0),
{ }
};
static struct clk_rcg2 gpu_cc_hub_clk_src = {
.cmd_rcgr = 0x93ec,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gpu_cc_parent_map_2,
.freq_tbl = ftbl_gpu_cc_hub_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gpu_cc_hub_clk_src",
.parent_data = gpu_cc_parent_data_2,
.num_parents = ARRAY_SIZE(gpu_cc_parent_data_2),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
};
static const struct freq_tbl ftbl_gpu_cc_xo_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
{ }
};
static struct clk_rcg2 gpu_cc_xo_clk_src = {
.cmd_rcgr = 0x9010,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gpu_cc_parent_map_3,
.freq_tbl = ftbl_gpu_cc_xo_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gpu_cc_xo_clk_src",
.parent_data = gpu_cc_parent_data_3,
.num_parents = ARRAY_SIZE(gpu_cc_parent_data_3),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_regmap_div gpu_cc_demet_div_clk_src = {
.reg = 0x9054,
.shift = 0,
.width = 4,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gpu_cc_demet_div_clk_src",
.parent_hws = (const struct clk_hw*[]) {
&gpu_cc_xo_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_regmap_div_ro_ops,
},
};
static struct clk_regmap_div gpu_cc_xo_div_clk_src = {
.reg = 0x9050,
.shift = 0,
.width = 4,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gpu_cc_xo_div_clk_src",
.parent_hws = (const struct clk_hw*[]) {
&gpu_cc_xo_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_regmap_div_ro_ops,
},
};
static struct clk_branch gpu_cc_ahb_clk = {
.halt_reg = 0x911c,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x911c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gpu_cc_ahb_clk",
.parent_hws = (const struct clk_hw*[]) {
&gpu_cc_hub_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpu_cc_crc_ahb_clk = {
.halt_reg = 0x9120,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x9120,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gpu_cc_crc_ahb_clk",
.parent_hws = (const struct clk_hw*[]) {
&gpu_cc_hub_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpu_cc_cx_ff_clk = {
.halt_reg = 0x914c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x914c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gpu_cc_cx_ff_clk",
.parent_hws = (const struct clk_hw*[]) {
&gpu_cc_ff_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpu_cc_cx_gmu_clk = {
.halt_reg = 0x913c,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x913c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gpu_cc_cx_gmu_clk",
.parent_hws = (const struct clk_hw*[]) {
&gpu_cc_gmu_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_aon_ops,
},
},
};
static struct clk_branch gpu_cc_cxo_clk = {
.halt_reg = 0x9144,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x9144,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gpu_cc_cxo_clk",
.parent_hws = (const struct clk_hw*[]) {
&gpu_cc_xo_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpu_cc_freq_measure_clk = {
.halt_reg = 0x9008,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x9008,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gpu_cc_freq_measure_clk",
.parent_hws = (const struct clk_hw*[]) {
&gpu_cc_xo_div_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpu_cc_hlos1_vote_gpu_smmu_clk = {
.halt_reg = 0x7000,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x7000,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gpu_cc_hlos1_vote_gpu_smmu_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpu_cc_hub_aon_clk = {
.halt_reg = 0x93e8,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x93e8,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gpu_cc_hub_aon_clk",
.parent_hws = (const struct clk_hw*[]) {
&gpu_cc_hub_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_aon_ops,
},
},
};
static struct clk_branch gpu_cc_hub_cx_int_clk = {
.halt_reg = 0x9148,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x9148,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gpu_cc_hub_cx_int_clk",
.parent_hws = (const struct clk_hw*[]) {
&gpu_cc_hub_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_aon_ops,
},
},
};
static struct clk_branch gpu_cc_memnoc_gfx_clk = {
.halt_reg = 0x9150,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x9150,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gpu_cc_memnoc_gfx_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpu_cc_mnd1x_0_gfx3d_clk = {
.halt_reg = 0x9288,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x9288,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gpu_cc_mnd1x_0_gfx3d_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpu_cc_mnd1x_1_gfx3d_clk = {
.halt_reg = 0x928c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x928c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gpu_cc_mnd1x_1_gfx3d_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpu_cc_sleep_clk = {
.halt_reg = 0x9134,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x9134,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gpu_cc_sleep_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct gdsc gpu_cc_cx_gdsc = {
.gdscr = 0x9108,
.gds_hw_ctrl = 0x953c,
.en_rest_wait_val = 0x2,
.en_few_wait_val = 0x2,
.clk_dis_wait_val = 0xf,
.pd = {
.name = "gpu_cc_cx_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = RETAIN_FF_ENABLE | VOTABLE,
};
static struct gdsc gpu_cc_gx_gdsc = {
.gdscr = 0x905c,
.clamp_io_ctrl = 0x9504,
.en_rest_wait_val = 0x2,
.en_few_wait_val = 0x2,
.clk_dis_wait_val = 0xf,
.pd = {
.name = "gpu_cc_gx_gdsc",
.power_on = gdsc_gx_do_nothing_enable,
},
.pwrsts = PWRSTS_OFF_ON,
.flags = CLAMP_IO | POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
};
static struct clk_regmap *gpu_cc_sm8550_clocks[] = {
[GPU_CC_AHB_CLK] = &gpu_cc_ahb_clk.clkr,
[GPU_CC_CRC_AHB_CLK] = &gpu_cc_crc_ahb_clk.clkr,
[GPU_CC_CX_FF_CLK] = &gpu_cc_cx_ff_clk.clkr,
[GPU_CC_CX_GMU_CLK] = &gpu_cc_cx_gmu_clk.clkr,
[GPU_CC_CXO_CLK] = &gpu_cc_cxo_clk.clkr,
[GPU_CC_DEMET_DIV_CLK_SRC] = &gpu_cc_demet_div_clk_src.clkr,
[GPU_CC_FF_CLK_SRC] = &gpu_cc_ff_clk_src.clkr,
[GPU_CC_FREQ_MEASURE_CLK] = &gpu_cc_freq_measure_clk.clkr,
[GPU_CC_GMU_CLK_SRC] = &gpu_cc_gmu_clk_src.clkr,
[GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK] = &gpu_cc_hlos1_vote_gpu_smmu_clk.clkr,
[GPU_CC_HUB_AON_CLK] = &gpu_cc_hub_aon_clk.clkr,
[GPU_CC_HUB_CLK_SRC] = &gpu_cc_hub_clk_src.clkr,
[GPU_CC_HUB_CX_INT_CLK] = &gpu_cc_hub_cx_int_clk.clkr,
[GPU_CC_MEMNOC_GFX_CLK] = &gpu_cc_memnoc_gfx_clk.clkr,
[GPU_CC_MND1X_0_GFX3D_CLK] = &gpu_cc_mnd1x_0_gfx3d_clk.clkr,
[GPU_CC_MND1X_1_GFX3D_CLK] = &gpu_cc_mnd1x_1_gfx3d_clk.clkr,
[GPU_CC_PLL0] = &gpu_cc_pll0.clkr,
[GPU_CC_PLL1] = &gpu_cc_pll1.clkr,
[GPU_CC_SLEEP_CLK] = &gpu_cc_sleep_clk.clkr,
[GPU_CC_XO_CLK_SRC] = &gpu_cc_xo_clk_src.clkr,
[GPU_CC_XO_DIV_CLK_SRC] = &gpu_cc_xo_div_clk_src.clkr,
};
static struct gdsc *gpu_cc_sm8550_gdscs[] = {
[GPU_CC_CX_GDSC] = &gpu_cc_cx_gdsc,
[GPU_CC_GX_GDSC] = &gpu_cc_gx_gdsc,
};
static const struct qcom_reset_map gpu_cc_sm8550_resets[] = {
[GPUCC_GPU_CC_ACD_BCR] = { 0x9358 },
[GPUCC_GPU_CC_CX_BCR] = { 0x9104 },
[GPUCC_GPU_CC_FAST_HUB_BCR] = { 0x93e4 },
[GPUCC_GPU_CC_FF_BCR] = { 0x9470 },
[GPUCC_GPU_CC_GFX3D_AON_BCR] = { 0x9198 },
[GPUCC_GPU_CC_GMU_BCR] = { 0x9314 },
[GPUCC_GPU_CC_GX_BCR] = { 0x9058 },
[GPUCC_GPU_CC_XO_BCR] = { 0x9000 },
};
static const struct regmap_config gpu_cc_sm8550_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.max_register = 0x9988,
.fast_io = true,
};
static const struct qcom_cc_desc gpu_cc_sm8550_desc = {
.config = &gpu_cc_sm8550_regmap_config,
.clks = gpu_cc_sm8550_clocks,
.num_clks = ARRAY_SIZE(gpu_cc_sm8550_clocks),
.resets = gpu_cc_sm8550_resets,
.num_resets = ARRAY_SIZE(gpu_cc_sm8550_resets),
.gdscs = gpu_cc_sm8550_gdscs,
.num_gdscs = ARRAY_SIZE(gpu_cc_sm8550_gdscs),
};
static const struct of_device_id gpu_cc_sm8550_match_table[] = {
{ .compatible = "qcom,sm8550-gpucc" },
{ }
};
MODULE_DEVICE_TABLE(of, gpu_cc_sm8550_match_table);
static int gpu_cc_sm8550_probe(struct platform_device *pdev)
{
struct regmap *regmap;
regmap = qcom_cc_map(pdev, &gpu_cc_sm8550_desc);
if (IS_ERR(regmap))
return PTR_ERR(regmap);
clk_lucid_ole_pll_configure(&gpu_cc_pll0, regmap, &gpu_cc_pll0_config);
clk_lucid_ole_pll_configure(&gpu_cc_pll1, regmap, &gpu_cc_pll1_config);
/* Keep some clocks always-on */
qcom_branch_set_clk_en(regmap, 0x9004); /* GPU_CC_CXO_AON_CLK */
qcom_branch_set_clk_en(regmap, 0x900c); /* GPU_CC_DEMET_CLK */
return qcom_cc_really_probe(&pdev->dev, &gpu_cc_sm8550_desc, regmap);
}
static struct platform_driver gpu_cc_sm8550_driver = {
.probe = gpu_cc_sm8550_probe,
.driver = {
.name = "gpu_cc-sm8550",
.of_match_table = gpu_cc_sm8550_match_table,
},
};
module_platform_driver(gpu_cc_sm8550_driver);
MODULE_DESCRIPTION("QTI GPUCC SM8550 Driver");
MODULE_LICENSE("GPL");
|
// SPDX-License-Identifier: GPL-2.0-only
/*
* WonderMedia WM8505 Frame Buffer device driver
*
* Copyright (C) 2010 Ed Spiridonov <[email protected]>
* Based on vt8500lcdfb.c
*/
#include <linux/delay.h>
#include <linux/dma-mapping.h>
#include <linux/fb.h>
#include <linux/errno.h>
#include <linux/err.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/memblock.h>
#include <linux/mm.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_fdt.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include <linux/string.h>
#include <linux/wait.h>
#include <video/of_display_timing.h>
#include "wm8505fb_regs.h"
#include "wmt_ge_rops.h"
#define DRIVER_NAME "wm8505-fb"
#define to_wm8505fb_info(__info) container_of(__info, \
struct wm8505fb_info, fb)
struct wm8505fb_info {
struct fb_info fb;
void __iomem *regbase;
unsigned int contrast;
};
static int wm8505fb_init_hw(struct fb_info *info)
{
struct wm8505fb_info *fbi = to_wm8505fb_info(info);
int i;
/* I know the purpose only of few registers, so clear unknown */
for (i = 0; i < 0x200; i += 4)
writel(0, fbi->regbase + i);
/* Set frame buffer address */
writel(fbi->fb.fix.smem_start, fbi->regbase + WMT_GOVR_FBADDR);
writel(fbi->fb.fix.smem_start, fbi->regbase + WMT_GOVR_FBADDR1);
/*
* Set in-memory picture format to RGB
* 0x31C sets the correct color mode (RGB565) for WM8650
* Bit 8+9 (0x300) are ignored on WM8505 as reserved
*/
writel(0x31c, fbi->regbase + WMT_GOVR_COLORSPACE);
writel(1, fbi->regbase + WMT_GOVR_COLORSPACE1);
/* Virtual buffer size */
writel(info->var.xres, fbi->regbase + WMT_GOVR_XRES);
writel(info->var.xres_virtual, fbi->regbase + WMT_GOVR_XRES_VIRTUAL);
/* black magic ;) */
writel(0xf, fbi->regbase + WMT_GOVR_FHI);
writel(4, fbi->regbase + WMT_GOVR_DVO_SET);
writel(1, fbi->regbase + WMT_GOVR_MIF_ENABLE);
writel(1, fbi->regbase + WMT_GOVR_REG_UPDATE);
return 0;
}
static int wm8505fb_set_timing(struct fb_info *info)
{
struct wm8505fb_info *fbi = to_wm8505fb_info(info);
int h_start = info->var.left_margin;
int h_end = h_start + info->var.xres;
int h_all = h_end + info->var.right_margin;
int h_sync = info->var.hsync_len;
int v_start = info->var.upper_margin;
int v_end = v_start + info->var.yres;
int v_all = v_end + info->var.lower_margin;
int v_sync = info->var.vsync_len;
writel(0, fbi->regbase + WMT_GOVR_TG);
writel(h_start, fbi->regbase + WMT_GOVR_TIMING_H_START);
writel(h_end, fbi->regbase + WMT_GOVR_TIMING_H_END);
writel(h_all, fbi->regbase + WMT_GOVR_TIMING_H_ALL);
writel(h_sync, fbi->regbase + WMT_GOVR_TIMING_H_SYNC);
writel(v_start, fbi->regbase + WMT_GOVR_TIMING_V_START);
writel(v_end, fbi->regbase + WMT_GOVR_TIMING_V_END);
writel(v_all, fbi->regbase + WMT_GOVR_TIMING_V_ALL);
writel(v_sync, fbi->regbase + WMT_GOVR_TIMING_V_SYNC);
writel(1, fbi->regbase + WMT_GOVR_TG);
return 0;
}
static int wm8505fb_set_par(struct fb_info *info)
{
struct wm8505fb_info *fbi = to_wm8505fb_info(info);
if (!fbi)
return -EINVAL;
if (info->var.bits_per_pixel == 32) {
info->var.red.offset = 16;
info->var.red.length = 8;
info->var.red.msb_right = 0;
info->var.green.offset = 8;
info->var.green.length = 8;
info->var.green.msb_right = 0;
info->var.blue.offset = 0;
info->var.blue.length = 8;
info->var.blue.msb_right = 0;
info->fix.visual = FB_VISUAL_TRUECOLOR;
info->fix.line_length = info->var.xres_virtual << 2;
} else if (info->var.bits_per_pixel == 16) {
info->var.red.offset = 11;
info->var.red.length = 5;
info->var.red.msb_right = 0;
info->var.green.offset = 5;
info->var.green.length = 6;
info->var.green.msb_right = 0;
info->var.blue.offset = 0;
info->var.blue.length = 5;
info->var.blue.msb_right = 0;
info->fix.visual = FB_VISUAL_TRUECOLOR;
info->fix.line_length = info->var.xres_virtual << 1;
}
wm8505fb_set_timing(info);
writel(fbi->contrast<<16 | fbi->contrast<<8 | fbi->contrast,
fbi->regbase + WMT_GOVR_CONTRAST);
return 0;
}
static ssize_t contrast_show(struct device *dev,
struct device_attribute *attr, char *buf)
{
struct fb_info *info = dev_get_drvdata(dev);
struct wm8505fb_info *fbi = to_wm8505fb_info(info);
return sprintf(buf, "%u\n", fbi->contrast);
}
static ssize_t contrast_store(struct device *dev,
struct device_attribute *attr,
const char *buf, size_t count)
{
struct fb_info *info = dev_get_drvdata(dev);
struct wm8505fb_info *fbi = to_wm8505fb_info(info);
unsigned long tmp;
if (kstrtoul(buf, 10, &tmp) || (tmp > 0xff))
return -EINVAL;
fbi->contrast = tmp;
wm8505fb_set_par(info);
return count;
}
static DEVICE_ATTR_RW(contrast);
static struct attribute *wm8505fb_attrs[] = {
&dev_attr_contrast.attr,
NULL,
};
ATTRIBUTE_GROUPS(wm8505fb);
static inline u_int chan_to_field(u_int chan, struct fb_bitfield *bf)
{
chan &= 0xffff;
chan >>= 16 - bf->length;
return chan << bf->offset;
}
static int wm8505fb_setcolreg(unsigned regno, unsigned red, unsigned green,
unsigned blue, unsigned transp,
struct fb_info *info) {
struct wm8505fb_info *fbi = to_wm8505fb_info(info);
int ret = 1;
unsigned int val;
if (regno >= 256)
return -EINVAL;
if (info->var.grayscale)
red = green = blue =
(19595 * red + 38470 * green + 7471 * blue) >> 16;
switch (fbi->fb.fix.visual) {
case FB_VISUAL_TRUECOLOR:
if (regno < 16) {
u32 *pal = info->pseudo_palette;
val = chan_to_field(red, &fbi->fb.var.red);
val |= chan_to_field(green, &fbi->fb.var.green);
val |= chan_to_field(blue, &fbi->fb.var.blue);
pal[regno] = val;
ret = 0;
}
break;
}
return ret;
}
static int wm8505fb_pan_display(struct fb_var_screeninfo *var,
struct fb_info *info)
{
struct wm8505fb_info *fbi = to_wm8505fb_info(info);
writel(var->xoffset, fbi->regbase + WMT_GOVR_XPAN);
writel(var->yoffset, fbi->regbase + WMT_GOVR_YPAN);
return 0;
}
static int wm8505fb_blank(int blank, struct fb_info *info)
{
struct wm8505fb_info *fbi = to_wm8505fb_info(info);
switch (blank) {
case FB_BLANK_UNBLANK:
wm8505fb_set_timing(info);
break;
default:
writel(0, fbi->regbase + WMT_GOVR_TIMING_V_SYNC);
break;
}
return 0;
}
static const struct fb_ops wm8505fb_ops = {
.owner = THIS_MODULE,
__FB_DEFAULT_DMAMEM_OPS_RDWR,
.fb_set_par = wm8505fb_set_par,
.fb_setcolreg = wm8505fb_setcolreg,
.fb_fillrect = wmt_ge_fillrect,
.fb_copyarea = wmt_ge_copyarea,
.fb_imageblit = sys_imageblit,
.fb_sync = wmt_ge_sync,
.fb_pan_display = wm8505fb_pan_display,
.fb_blank = wm8505fb_blank,
__FB_DEFAULT_IOMEM_OPS_MMAP,
};
static int wm8505fb_probe(struct platform_device *pdev)
{
struct wm8505fb_info *fbi;
struct display_timings *disp_timing;
void *addr;
int ret;
struct fb_videomode mode;
u32 bpp;
dma_addr_t fb_mem_phys;
unsigned long fb_mem_len;
void *fb_mem_virt;
fbi = devm_kzalloc(&pdev->dev, sizeof(struct wm8505fb_info) +
sizeof(u32) * 16, GFP_KERNEL);
if (!fbi)
return -ENOMEM;
strcpy(fbi->fb.fix.id, DRIVER_NAME);
fbi->fb.fix.type = FB_TYPE_PACKED_PIXELS;
fbi->fb.fix.xpanstep = 1;
fbi->fb.fix.ypanstep = 1;
fbi->fb.fix.ywrapstep = 0;
fbi->fb.fix.accel = FB_ACCEL_NONE;
fbi->fb.fbops = &wm8505fb_ops;
fbi->fb.flags = FBINFO_HWACCEL_COPYAREA
| FBINFO_HWACCEL_FILLRECT
| FBINFO_HWACCEL_XPAN
| FBINFO_HWACCEL_YPAN
| FBINFO_VIRTFB
| FBINFO_PARTIAL_PAN_OK;
fbi->fb.node = -1;
addr = fbi;
addr = addr + sizeof(struct wm8505fb_info);
fbi->fb.pseudo_palette = addr;
fbi->regbase = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(fbi->regbase))
return PTR_ERR(fbi->regbase);
disp_timing = of_get_display_timings(pdev->dev.of_node);
if (!disp_timing)
return -EINVAL;
ret = of_get_fb_videomode(pdev->dev.of_node, &mode, OF_USE_NATIVE_MODE);
if (ret)
return ret;
ret = of_property_read_u32(pdev->dev.of_node, "bits-per-pixel", &bpp);
if (ret)
return ret;
fb_videomode_to_var(&fbi->fb.var, &mode);
fbi->fb.var.nonstd = 0;
fbi->fb.var.activate = FB_ACTIVATE_NOW;
fbi->fb.var.height = -1;
fbi->fb.var.width = -1;
/* try allocating the framebuffer */
fb_mem_len = mode.xres * mode.yres * 2 * (bpp / 8);
fb_mem_virt = dmam_alloc_coherent(&pdev->dev, fb_mem_len, &fb_mem_phys,
GFP_KERNEL);
if (!fb_mem_virt) {
pr_err("%s: Failed to allocate framebuffer\n", __func__);
return -ENOMEM;
}
fbi->fb.var.xres_virtual = mode.xres;
fbi->fb.var.yres_virtual = mode.yres * 2;
fbi->fb.var.bits_per_pixel = bpp;
fbi->fb.fix.smem_start = fb_mem_phys;
fbi->fb.fix.smem_len = fb_mem_len;
fbi->fb.screen_buffer = fb_mem_virt;
fbi->fb.screen_size = fb_mem_len;
fbi->contrast = 0x10;
ret = wm8505fb_set_par(&fbi->fb);
if (ret) {
dev_err(&pdev->dev, "Failed to set parameters\n");
return ret;
}
if (fb_alloc_cmap(&fbi->fb.cmap, 256, 0) < 0) {
dev_err(&pdev->dev, "Failed to allocate color map\n");
return -ENOMEM;
}
wm8505fb_init_hw(&fbi->fb);
platform_set_drvdata(pdev, fbi);
ret = register_framebuffer(&fbi->fb);
if (ret < 0) {
dev_err(&pdev->dev,
"Failed to register framebuffer device: %d\n", ret);
if (fbi->fb.cmap.len)
fb_dealloc_cmap(&fbi->fb.cmap);
return ret;
}
fb_info(&fbi->fb, "%s frame buffer at 0x%lx-0x%lx\n",
fbi->fb.fix.id, fbi->fb.fix.smem_start,
fbi->fb.fix.smem_start + fbi->fb.fix.smem_len - 1);
return 0;
}
static void wm8505fb_remove(struct platform_device *pdev)
{
struct wm8505fb_info *fbi = platform_get_drvdata(pdev);
unregister_framebuffer(&fbi->fb);
writel(0, fbi->regbase);
if (fbi->fb.cmap.len)
fb_dealloc_cmap(&fbi->fb.cmap);
}
static const struct of_device_id wmt_dt_ids[] = {
{ .compatible = "wm,wm8505-fb", },
{}
};
static struct platform_driver wm8505fb_driver = {
.probe = wm8505fb_probe,
.remove = wm8505fb_remove,
.driver = {
.name = DRIVER_NAME,
.of_match_table = wmt_dt_ids,
.dev_groups = wm8505fb_groups,
},
};
module_platform_driver(wm8505fb_driver);
MODULE_AUTHOR("Ed Spiridonov <[email protected]>");
MODULE_DESCRIPTION("Framebuffer driver for WMT WM8505");
MODULE_DEVICE_TABLE(of, wmt_dt_ids);
|
/*
* Copyright (c) 1993-2014, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _cl917d_h_
#define _cl917d_h_
// class methods
#define NV917D_SOR_SET_CONTROL(a) (0x00000200 + (a)*0x00000020)
#define NV917D_SOR_SET_CONTROL_OWNER_MASK 3:0
#define NV917D_SOR_SET_CONTROL_OWNER_MASK_NONE (0x00000000)
#define NV917D_SOR_SET_CONTROL_OWNER_MASK_HEAD0 (0x00000001)
#define NV917D_SOR_SET_CONTROL_OWNER_MASK_HEAD1 (0x00000002)
#define NV917D_SOR_SET_CONTROL_OWNER_MASK_HEAD2 (0x00000004)
#define NV917D_SOR_SET_CONTROL_OWNER_MASK_HEAD3 (0x00000008)
#define NV917D_SOR_SET_CONTROL_PROTOCOL 11:8
#define NV917D_SOR_SET_CONTROL_PROTOCOL_LVDS_CUSTOM (0x00000000)
#define NV917D_SOR_SET_CONTROL_PROTOCOL_SINGLE_TMDS_A (0x00000001)
#define NV917D_SOR_SET_CONTROL_PROTOCOL_SINGLE_TMDS_B (0x00000002)
#define NV917D_SOR_SET_CONTROL_PROTOCOL_DUAL_TMDS (0x00000005)
#define NV917D_SOR_SET_CONTROL_PROTOCOL_DP_A (0x00000008)
#define NV917D_SOR_SET_CONTROL_PROTOCOL_DP_B (0x00000009)
#define NV917D_SOR_SET_CONTROL_PROTOCOL_CUSTOM (0x0000000F)
#define NV917D_SOR_SET_CONTROL_DE_SYNC_POLARITY 14:14
#define NV917D_SOR_SET_CONTROL_DE_SYNC_POLARITY_POSITIVE_TRUE (0x00000000)
#define NV917D_SOR_SET_CONTROL_DE_SYNC_POLARITY_NEGATIVE_TRUE (0x00000001)
#define NV917D_SOR_SET_CONTROL_PIXEL_REPLICATE_MODE 21:20
#define NV917D_SOR_SET_CONTROL_PIXEL_REPLICATE_MODE_OFF (0x00000000)
#define NV917D_SOR_SET_CONTROL_PIXEL_REPLICATE_MODE_X2 (0x00000001)
#define NV917D_SOR_SET_CONTROL_PIXEL_REPLICATE_MODE_X4 (0x00000002)
#define NV917D_HEAD_SET_CONTROL_CURSOR(a) (0x00000480 + (a)*0x00000300)
#define NV917D_HEAD_SET_CONTROL_CURSOR_ENABLE 31:31
#define NV917D_HEAD_SET_CONTROL_CURSOR_ENABLE_DISABLE (0x00000000)
#define NV917D_HEAD_SET_CONTROL_CURSOR_ENABLE_ENABLE (0x00000001)
#define NV917D_HEAD_SET_CONTROL_CURSOR_FORMAT 25:24
#define NV917D_HEAD_SET_CONTROL_CURSOR_FORMAT_A1R5G5B5 (0x00000000)
#define NV917D_HEAD_SET_CONTROL_CURSOR_FORMAT_A8R8G8B8 (0x00000001)
#define NV917D_HEAD_SET_CONTROL_CURSOR_SIZE 27:26
#define NV917D_HEAD_SET_CONTROL_CURSOR_SIZE_W32_H32 (0x00000000)
#define NV917D_HEAD_SET_CONTROL_CURSOR_SIZE_W64_H64 (0x00000001)
#define NV917D_HEAD_SET_CONTROL_CURSOR_SIZE_W128_H128 (0x00000002)
#define NV917D_HEAD_SET_CONTROL_CURSOR_SIZE_W256_H256 (0x00000003)
#define NV917D_HEAD_SET_CONTROL_CURSOR_HOT_SPOT_X 15:8
#define NV917D_HEAD_SET_CONTROL_CURSOR_HOT_SPOT_Y 23:16
#define NV917D_HEAD_SET_CONTROL_CURSOR_COMPOSITION 29:28
#define NV917D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_ALPHA_BLEND (0x00000000)
#define NV917D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_PREMULT_ALPHA_BLEND (0x00000001)
#define NV917D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_XOR (0x00000002)
#define NV917D_HEAD_SET_OFFSET_CURSOR(a) (0x00000484 + (a)*0x00000300)
#define NV917D_HEAD_SET_OFFSET_CURSOR_ORIGIN 31:0
#define NV917D_HEAD_SET_CONTEXT_DMA_CURSOR(a) (0x0000048C + (a)*0x00000300)
#define NV917D_HEAD_SET_CONTEXT_DMA_CURSOR_HANDLE 31:0
#define NV917D_HEAD_SET_DITHER_CONTROL(a) (0x000004A0 + (a)*0x00000300)
#define NV917D_HEAD_SET_DITHER_CONTROL_ENABLE 0:0
#define NV917D_HEAD_SET_DITHER_CONTROL_ENABLE_DISABLE (0x00000000)
#define NV917D_HEAD_SET_DITHER_CONTROL_ENABLE_ENABLE (0x00000001)
#define NV917D_HEAD_SET_DITHER_CONTROL_BITS 2:1
#define NV917D_HEAD_SET_DITHER_CONTROL_BITS_DITHER_TO_6_BITS (0x00000000)
#define NV917D_HEAD_SET_DITHER_CONTROL_BITS_DITHER_TO_8_BITS (0x00000001)
#define NV917D_HEAD_SET_DITHER_CONTROL_BITS_DITHER_TO_10_BITS (0x00000002)
#define NV917D_HEAD_SET_DITHER_CONTROL_MODE 6:3
#define NV917D_HEAD_SET_DITHER_CONTROL_MODE_DYNAMIC_ERR_ACC (0x00000000)
#define NV917D_HEAD_SET_DITHER_CONTROL_MODE_STATIC_ERR_ACC (0x00000001)
#define NV917D_HEAD_SET_DITHER_CONTROL_MODE_DYNAMIC_2X2 (0x00000002)
#define NV917D_HEAD_SET_DITHER_CONTROL_MODE_STATIC_2X2 (0x00000003)
#define NV917D_HEAD_SET_DITHER_CONTROL_MODE_TEMPORAL (0x00000004)
#define NV917D_HEAD_SET_DITHER_CONTROL_PHASE 8:7
#define NV917D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS(a) (0x000004D0 + (a)*0x00000300)
#define NV917D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_USABLE 0:0
#define NV917D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_USABLE_FALSE (0x00000000)
#define NV917D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_USABLE_TRUE (0x00000001)
#define NV917D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH 11:8
#define NV917D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH_BPP_8 (0x00000000)
#define NV917D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH_BPP_16 (0x00000001)
#define NV917D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH_BPP_32 (0x00000003)
#define NV917D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH_BPP_64 (0x00000005)
#define NV917D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_SUPER_SAMPLE 13:12
#define NV917D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_SUPER_SAMPLE_X1_AA (0x00000000)
#define NV917D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_SUPER_SAMPLE_X4_AA (0x00000002)
#define NV917D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_BASE_LUT 17:16
#define NV917D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_BASE_LUT_USAGE_NONE (0x00000000)
#define NV917D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_BASE_LUT_USAGE_257 (0x00000001)
#define NV917D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_BASE_LUT_USAGE_1025 (0x00000002)
#define NV917D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_OUTPUT_LUT 21:20
#define NV917D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_OUTPUT_LUT_USAGE_NONE (0x00000000)
#define NV917D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_OUTPUT_LUT_USAGE_257 (0x00000001)
#define NV917D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_OUTPUT_LUT_USAGE_1025 (0x00000002)
#endif // _cl917d_h
|
// SPDX-License-Identifier: GPL-2.0
/dts-v1/;
#include <dt-bindings/input/input.h>
#include "tegra30-colibri.dtsi"
/ {
model = "Toradex Colibri T30 on Colibri Evaluation Board";
compatible = "toradex,colibri_t30-eval-v3", "toradex,colibri_t30",
"nvidia,tegra30";
aliases {
rtc0 = "/i2c@7000c000/rtc@68";
rtc1 = "/i2c@7000d000/pmic@2d";
rtc2 = "/rtc@7000e000";
serial0 = &uarta;
serial1 = &uartb;
serial2 = &uartd;
};
chosen {
stdout-path = "serial0:115200n8";
};
host1x@50000000 {
dc@54200000 {
rgb {
status = "okay";
nvidia,panel = <&panel>;
};
};
hdmi@54280000 {
status = "okay";
hdmi-supply = <®_5v0>;
};
};
/* Colibri UART-A */
serial@70006000 {
/delete-property/ dmas;
/delete-property/ dma-names;
status = "okay";
};
/* Colibri UART-C */
serial@70006040 {
status = "okay";
};
/* Colibri UART-B */
serial@70006300 {
status = "okay";
};
pwm@7000a000 {
status = "okay";
};
/*
* GEN1_I2C: I2C_SDA/SCL on SODIMM pin 194/196 (e.g. RTC on carrier
* board)
*/
i2c@7000c000 {
status = "okay";
clock-frequency = <400000>;
/* M41T0M6 real time clock on carrier board */
rtc@68 {
compatible = "st,m41t0";
reg = <0x68>;
};
};
/* GEN2_I2C: unused */
/* CAM_I2C (I2C3): unused */
/* DDC_CLOCK/DATA on X3 pin 15/16 (e.g. display EDID) */
i2c@7000c700 {
status = "okay";
};
/* SPI1: Colibri SSP */
spi@7000d400 {
status = "okay";
spi-max-frequency = <25000000>;
can@0 {
compatible = "microchip,mcp2515";
reg = <0>;
clocks = <&clk16m>;
interrupt-parent = <&gpio>;
/* CAN_INT */
interrupts = <TEGRA_GPIO(S, 0) IRQ_TYPE_EDGE_FALLING>;
spi-max-frequency = <10000000>;
vdd-supply = <®_3v3>;
xceiver-supply = <®_5v0>;
};
};
/* SD/MMC */
mmc@78000200 {
status = "okay";
bus-width = <4>;
cd-gpios = <&gpio TEGRA_GPIO(C, 7) GPIO_ACTIVE_LOW>; /* MMCD */
no-1-8-v;
};
/* EHCI instance 0: USB1_DP/N -> USBC_P/N */
usb@7d000000 {
status = "okay";
dr_mode = "otg";
};
usb-phy@7d000000 {
status = "okay";
vbus-supply = <®_usbc_vbus>;
};
/* EHCI instance 2: USB3_DP/N -> USBH_P/N */
usb@7d008000 {
status = "okay";
};
usb-phy@7d008000 {
status = "okay";
vbus-supply = <®_usbh_vbus>;
};
backlight: backlight {
compatible = "pwm-backlight";
brightness-levels = <255 128 64 32 16 8 4 0>;
default-brightness-level = <6>;
/* BL_ON */
enable-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_HIGH>;
power-supply = <®_3v3>;
pwms = <&pwm 0 5000000>; /* PWM<A> */
};
clk16m: clock-osc3 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <16000000>;
};
gpio-keys {
compatible = "gpio-keys";
key-wakeup {
label = "SODIMM pin 45 wakeup";
gpios = <&gpio TEGRA_GPIO(V, 1) GPIO_ACTIVE_HIGH>;
linux,code = <KEY_WAKEUP>;
debounce-interval = <10>;
wakeup-source;
};
};
panel: panel {
/*
* edt,et057090dhu: EDT 5.7" LCD TFT
* edt,et070080dh6: EDT 7.0" LCD TFT
*/
compatible = "edt,et057090dhu";
backlight = <&backlight>;
power-supply = <®_3v3>;
};
reg_3v3: regulator-3v3 {
compatible = "regulator-fixed";
regulator-name = "3.3V_SW";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
reg_5v0: regulator-5v0 {
compatible = "regulator-fixed";
regulator-name = "5V_SW";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
};
reg_usbc_vbus: regulator-usbc-vbus {
compatible = "regulator-fixed";
regulator-name = "VCC_USB5";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
vin-supply = <®_5v0>;
};
/* USBH_PEN resp. USB_P_EN */
reg_usbh_vbus: regulator-usbh-vbus {
compatible = "regulator-fixed";
regulator-name = "VCC_USB[1-4]";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_LOW>;
vin-supply = <®_5v0>;
};
};
|
/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* CLPS711X system register bits definitions
*
* Copyright (C) 2013 Alexander Shiyan <[email protected]>
*/
#ifndef _LINUX_MFD_SYSCON_CLPS711X_H_
#define _LINUX_MFD_SYSCON_CLPS711X_H_
#define SYSCON_OFFSET (0x00)
#define SYSFLG_OFFSET (0x40)
#define SYSCON1_KBDSCAN(x) ((x) & 15)
#define SYSCON1_KBDSCAN_MASK (15)
#define SYSCON1_TC1M (1 << 4)
#define SYSCON1_TC1S (1 << 5)
#define SYSCON1_TC2M (1 << 6)
#define SYSCON1_TC2S (1 << 7)
#define SYSCON1_BZTOG (1 << 9)
#define SYSCON1_BZMOD (1 << 10)
#define SYSCON1_DBGEN (1 << 11)
#define SYSCON1_LCDEN (1 << 12)
#define SYSCON1_CDENTX (1 << 13)
#define SYSCON1_CDENRX (1 << 14)
#define SYSCON1_SIREN (1 << 15)
#define SYSCON1_ADCKSEL(x) (((x) & 3) << 16)
#define SYSCON1_ADCKSEL_MASK (3 << 16)
#define SYSCON1_EXCKEN (1 << 18)
#define SYSCON1_WAKEDIS (1 << 19)
#define SYSCON1_IRTXM (1 << 20)
#define SYSCON2_SERSEL (1 << 0)
#define SYSCON2_KBD6 (1 << 1)
#define SYSCON2_DRAMZ (1 << 2)
#define SYSCON2_KBWEN (1 << 3)
#define SYSCON2_SS2TXEN (1 << 4)
#define SYSCON2_PCCARD1 (1 << 5)
#define SYSCON2_PCCARD2 (1 << 6)
#define SYSCON2_SS2RXEN (1 << 7)
#define SYSCON2_SS2MAEN (1 << 9)
#define SYSCON2_OSTB (1 << 12)
#define SYSCON2_CLKENSL (1 << 13)
#define SYSCON2_BUZFREQ (1 << 14)
#define SYSCON3_ADCCON (1 << 0)
#define SYSCON3_CLKCTL0 (1 << 1)
#define SYSCON3_CLKCTL1 (1 << 2)
#define SYSCON3_DAISEL (1 << 3)
#define SYSCON3_ADCCKNSEN (1 << 4)
#define SYSCON3_VERSN(x) (((x) >> 5) & 7)
#define SYSCON3_VERSN_MASK (7 << 5)
#define SYSCON3_FASTWAKE (1 << 8)
#define SYSCON3_DAIEN (1 << 9)
#define SYSCON3_128FS SYSCON3_DAIEN
#define SYSCON3_ENPD67 (1 << 10)
#define SYSCON_UARTEN (1 << 8)
#define SYSFLG1_MCDR (1 << 0)
#define SYSFLG1_DCDET (1 << 1)
#define SYSFLG1_WUDR (1 << 2)
#define SYSFLG1_WUON (1 << 3)
#define SYSFLG1_CTS (1 << 8)
#define SYSFLG1_DSR (1 << 9)
#define SYSFLG1_DCD (1 << 10)
#define SYSFLG1_NBFLG (1 << 12)
#define SYSFLG1_RSTFLG (1 << 13)
#define SYSFLG1_PFFLG (1 << 14)
#define SYSFLG1_CLDFLG (1 << 15)
#define SYSFLG1_CRXFE (1 << 24)
#define SYSFLG1_CTXFF (1 << 25)
#define SYSFLG1_SSIBUSY (1 << 26)
#define SYSFLG1_ID (1 << 29)
#define SYSFLG1_VERID(x) (((x) >> 30) & 3)
#define SYSFLG1_VERID_MASK (3 << 30)
#define SYSFLG2_SSRXOF (1 << 0)
#define SYSFLG2_RESVAL (1 << 1)
#define SYSFLG2_RESFRM (1 << 2)
#define SYSFLG2_SS2RXFE (1 << 3)
#define SYSFLG2_SS2TXFF (1 << 4)
#define SYSFLG2_SS2TXUF (1 << 5)
#define SYSFLG2_CKMODE (1 << 6)
#define SYSFLG_UBUSY (1 << 11)
#define SYSFLG_URXFE (1 << 22)
#define SYSFLG_UTXFF (1 << 23)
#endif
|
// SPDX-License-Identifier: GPL-2.0+
// rc-pixelview-mk12.h - Keytable for pixelview Remote Controller
//
// keymap imported from ir-keymaps.c
//
// Copyright (c) 2010 by Mauro Carvalho Chehab
#include <media/rc-map.h>
#include <linux/module.h>
/*
* Keytable for 002-T IR remote provided together with Pixelview
* SBTVD Hybrid Remote Controller. Uses NEC extended format.
*/
static struct rc_map_table pixelview_002t[] = {
{ 0x866b13, KEY_MUTE },
{ 0x866b12, KEY_POWER2 }, /* power */
{ 0x866b01, KEY_NUMERIC_1 },
{ 0x866b02, KEY_NUMERIC_2 },
{ 0x866b03, KEY_NUMERIC_3 },
{ 0x866b04, KEY_NUMERIC_4 },
{ 0x866b05, KEY_NUMERIC_5 },
{ 0x866b06, KEY_NUMERIC_6 },
{ 0x866b07, KEY_NUMERIC_7 },
{ 0x866b08, KEY_NUMERIC_8 },
{ 0x866b09, KEY_NUMERIC_9 },
{ 0x866b00, KEY_NUMERIC_0 },
{ 0x866b0d, KEY_CHANNELUP },
{ 0x866b19, KEY_CHANNELDOWN },
{ 0x866b10, KEY_VOLUMEUP }, /* vol + */
{ 0x866b0c, KEY_VOLUMEDOWN }, /* vol - */
{ 0x866b0a, KEY_CAMERA }, /* snapshot */
{ 0x866b0b, KEY_ZOOM }, /* zoom */
{ 0x866b1b, KEY_BACKSPACE },
{ 0x866b15, KEY_ENTER },
{ 0x866b1d, KEY_UP },
{ 0x866b1e, KEY_DOWN },
{ 0x866b0e, KEY_LEFT },
{ 0x866b0f, KEY_RIGHT },
{ 0x866b18, KEY_RECORD },
{ 0x866b1a, KEY_STOP },
};
static struct rc_map_list pixelview_map = {
.map = {
.scan = pixelview_002t,
.size = ARRAY_SIZE(pixelview_002t),
.rc_proto = RC_PROTO_NECX,
.name = RC_MAP_PIXELVIEW_002T,
}
};
static int __init init_rc_map_pixelview(void)
{
return rc_map_register(&pixelview_map);
}
static void __exit exit_rc_map_pixelview(void)
{
rc_map_unregister(&pixelview_map);
}
module_init(init_rc_map_pixelview)
module_exit(exit_rc_map_pixelview)
MODULE_LICENSE("GPL");
MODULE_AUTHOR("Mauro Carvalho Chehab");
MODULE_DESCRIPTION("002-T IR remote keytable");
|
/* SPDX-License-Identifier: GPL-2.0 */
#ifndef _NF_DUP_NETDEV_H_
#define _NF_DUP_NETDEV_H_
#include <net/netfilter/nf_tables.h>
void nf_dup_netdev_egress(const struct nft_pktinfo *pkt, int oif);
void nf_fwd_netdev_egress(const struct nft_pktinfo *pkt, int oif);
struct nft_offload_ctx;
struct nft_flow_rule;
int nft_fwd_dup_netdev_offload(struct nft_offload_ctx *ctx,
struct nft_flow_rule *flow,
enum flow_action_id id, int oif);
#endif
|
// SPDX-License-Identifier: GPL-2.0
/*
* PowerNV code for secure variables
*
* Copyright (C) 2019 IBM Corporation
* Author: Claudio Carvalho
* Nayna Jain
*
* APIs to access secure variables managed by OPAL.
*/
#define pr_fmt(fmt) "secvar: "fmt
#include <linux/types.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <asm/opal.h>
#include <asm/secvar.h>
#include <asm/secure_boot.h>
static int opal_status_to_err(int rc)
{
int err;
switch (rc) {
case OPAL_SUCCESS:
err = 0;
break;
case OPAL_UNSUPPORTED:
err = -ENXIO;
break;
case OPAL_PARAMETER:
err = -EINVAL;
break;
case OPAL_RESOURCE:
err = -ENOSPC;
break;
case OPAL_HARDWARE:
err = -EIO;
break;
case OPAL_NO_MEM:
err = -ENOMEM;
break;
case OPAL_EMPTY:
err = -ENOENT;
break;
case OPAL_PARTIAL:
err = -EFBIG;
break;
default:
err = -EINVAL;
}
return err;
}
static int opal_get_variable(const char *key, u64 ksize, u8 *data, u64 *dsize)
{
int rc;
if (!key || !dsize)
return -EINVAL;
*dsize = cpu_to_be64(*dsize);
rc = opal_secvar_get(key, ksize, data, dsize);
*dsize = be64_to_cpu(*dsize);
return opal_status_to_err(rc);
}
static int opal_get_next_variable(const char *key, u64 *keylen, u64 keybufsize)
{
int rc;
if (!key || !keylen)
return -EINVAL;
*keylen = cpu_to_be64(*keylen);
rc = opal_secvar_get_next(key, keylen, keybufsize);
*keylen = be64_to_cpu(*keylen);
return opal_status_to_err(rc);
}
static int opal_set_variable(const char *key, u64 ksize, u8 *data, u64 dsize)
{
int rc;
if (!key || !data)
return -EINVAL;
rc = opal_secvar_enqueue_update(key, ksize, data, dsize);
return opal_status_to_err(rc);
}
static ssize_t opal_secvar_format(char *buf, size_t bufsize)
{
ssize_t rc = 0;
struct device_node *node;
const char *format;
node = of_find_compatible_node(NULL, NULL, "ibm,secvar-backend");
if (!of_device_is_available(node)) {
rc = -ENODEV;
goto out;
}
rc = of_property_read_string(node, "format", &format);
if (rc)
goto out;
rc = snprintf(buf, bufsize, "%s", format);
out:
of_node_put(node);
return rc;
}
static int opal_secvar_max_size(u64 *max_size)
{
int rc;
struct device_node *node;
node = of_find_compatible_node(NULL, NULL, "ibm,secvar-backend");
if (!node)
return -ENODEV;
if (!of_device_is_available(node)) {
rc = -ENODEV;
goto out;
}
rc = of_property_read_u64(node, "max-var-size", max_size);
out:
of_node_put(node);
return rc;
}
static const struct secvar_operations opal_secvar_ops = {
.get = opal_get_variable,
.get_next = opal_get_next_variable,
.set = opal_set_variable,
.format = opal_secvar_format,
.max_size = opal_secvar_max_size,
};
static int opal_secvar_probe(struct platform_device *pdev)
{
if (!opal_check_token(OPAL_SECVAR_GET)
|| !opal_check_token(OPAL_SECVAR_GET_NEXT)
|| !opal_check_token(OPAL_SECVAR_ENQUEUE_UPDATE)) {
pr_err("OPAL doesn't support secure variables\n");
return -ENODEV;
}
return set_secvar_ops(&opal_secvar_ops);
}
static const struct of_device_id opal_secvar_match[] = {
{ .compatible = "ibm,secvar-backend",},
{},
};
static struct platform_driver opal_secvar_driver = {
.driver = {
.name = "secvar",
.of_match_table = opal_secvar_match,
},
};
static int __init opal_secvar_init(void)
{
return platform_driver_probe(&opal_secvar_driver, opal_secvar_probe);
}
device_initcall(opal_secvar_init);
|
/*
* Copyright 2021 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
*
*/
#include <linux/debugfs.h>
#include <linux/pm_runtime.h>
#include "amdgpu.h"
#include "amdgpu_securedisplay.h"
/**
* DOC: AMDGPU SECUREDISPLAY debugfs test interface
*
* how to use?
* echo opcode <value> > <debugfs_dir>/dri/xxx/securedisplay_test
* eg. echo 1 > <debugfs_dir>/dri/xxx/securedisplay_test
* eg. echo 2 phy_id > <debugfs_dir>/dri/xxx/securedisplay_test
*
* opcode:
* 1：Query whether TA is responding used only for validation pupose
* 2: Send region of Interest and CRC value to I2C. (uint32)phy_id is
* send to determine which DIO scratch register should be used to get
* ROI and receive i2c_buf as the output.
*
* You can refer more detail from header file ta_securedisplay_if.h
*
*/
void psp_securedisplay_parse_resp_status(struct psp_context *psp,
enum ta_securedisplay_status status)
{
switch (status) {
case TA_SECUREDISPLAY_STATUS__SUCCESS:
break;
case TA_SECUREDISPLAY_STATUS__GENERIC_FAILURE:
dev_err(psp->adev->dev, "Secure display: Generic Failure.");
break;
case TA_SECUREDISPLAY_STATUS__INVALID_PARAMETER:
dev_err(psp->adev->dev, "Secure display: Invalid Parameter.");
break;
case TA_SECUREDISPLAY_STATUS__NULL_POINTER:
dev_err(psp->adev->dev, "Secure display: Null Pointer.");
break;
case TA_SECUREDISPLAY_STATUS__I2C_WRITE_ERROR:
dev_err(psp->adev->dev, "Secure display: Failed to write to I2C.");
break;
case TA_SECUREDISPLAY_STATUS__READ_DIO_SCRATCH_ERROR:
dev_err(psp->adev->dev, "Secure display: Failed to Read DIO Scratch Register.");
break;
case TA_SECUREDISPLAY_STATUS__READ_CRC_ERROR:
dev_err(psp->adev->dev, "Secure display: Failed to Read CRC");
break;
case TA_SECUREDISPLAY_STATUS__I2C_INIT_ERROR:
dev_err(psp->adev->dev, "Secure display: Failed to initialize I2C.");
break;
default:
dev_err(psp->adev->dev, "Secure display: Failed to parse status: %d\n", status);
}
}
void psp_prep_securedisplay_cmd_buf(struct psp_context *psp, struct ta_securedisplay_cmd **cmd,
enum ta_securedisplay_command command_id)
{
*cmd = (struct ta_securedisplay_cmd *)psp->securedisplay_context.context.mem_context.shared_buf;
memset(*cmd, 0, sizeof(struct ta_securedisplay_cmd));
(*cmd)->status = TA_SECUREDISPLAY_STATUS__GENERIC_FAILURE;
(*cmd)->cmd_id = command_id;
}
#if defined(CONFIG_DEBUG_FS)
static ssize_t amdgpu_securedisplay_debugfs_write(struct file *f, const char __user *buf,
size_t size, loff_t *pos)
{
struct amdgpu_device *adev = (struct amdgpu_device *)file_inode(f)->i_private;
struct psp_context *psp = &adev->psp;
struct ta_securedisplay_cmd *securedisplay_cmd;
struct drm_device *dev = adev_to_drm(adev);
uint32_t phy_id;
uint32_t op;
char str[64];
int ret;
if (*pos || size > sizeof(str) - 1)
return -EINVAL;
memset(str, 0, sizeof(str));
ret = copy_from_user(str, buf, size);
if (ret)
return -EFAULT;
ret = pm_runtime_get_sync(dev->dev);
if (ret < 0) {
pm_runtime_put_autosuspend(dev->dev);
return ret;
}
if (size < 3)
sscanf(str, "%u ", &op);
else
sscanf(str, "%u %u", &op, &phy_id);
switch (op) {
case 1:
mutex_lock(&psp->securedisplay_context.mutex);
psp_prep_securedisplay_cmd_buf(psp, &securedisplay_cmd,
TA_SECUREDISPLAY_COMMAND__QUERY_TA);
ret = psp_securedisplay_invoke(psp, TA_SECUREDISPLAY_COMMAND__QUERY_TA);
if (!ret) {
if (securedisplay_cmd->status == TA_SECUREDISPLAY_STATUS__SUCCESS)
dev_info(adev->dev, "SECUREDISPLAY: query securedisplay TA ret is 0x%X\n",
securedisplay_cmd->securedisplay_out_message.query_ta.query_cmd_ret);
else
psp_securedisplay_parse_resp_status(psp, securedisplay_cmd->status);
}
mutex_unlock(&psp->securedisplay_context.mutex);
break;
case 2:
if (size < 3 || phy_id >= TA_SECUREDISPLAY_MAX_PHY) {
dev_err(adev->dev, "Invalid input: %s\n", str);
return -EINVAL;
}
mutex_lock(&psp->securedisplay_context.mutex);
psp_prep_securedisplay_cmd_buf(psp, &securedisplay_cmd,
TA_SECUREDISPLAY_COMMAND__SEND_ROI_CRC);
securedisplay_cmd->securedisplay_in_message.send_roi_crc.phy_id = phy_id;
ret = psp_securedisplay_invoke(psp, TA_SECUREDISPLAY_COMMAND__SEND_ROI_CRC);
if (!ret) {
if (securedisplay_cmd->status == TA_SECUREDISPLAY_STATUS__SUCCESS) {
dev_info(adev->dev, "SECUREDISPLAY: I2C buffer out put is: %*ph\n",
TA_SECUREDISPLAY_I2C_BUFFER_SIZE,
securedisplay_cmd->securedisplay_out_message.send_roi_crc.i2c_buf);
} else {
psp_securedisplay_parse_resp_status(psp, securedisplay_cmd->status);
}
}
mutex_unlock(&psp->securedisplay_context.mutex);
break;
default:
dev_err(adev->dev, "Invalid input: %s\n", str);
}
pm_runtime_mark_last_busy(dev->dev);
pm_runtime_put_autosuspend(dev->dev);
return size;
}
static const struct file_operations amdgpu_securedisplay_debugfs_ops = {
.owner = THIS_MODULE,
.read = NULL,
.write = amdgpu_securedisplay_debugfs_write,
.llseek = default_llseek
};
#endif
void amdgpu_securedisplay_debugfs_init(struct amdgpu_device *adev)
{
#if defined(CONFIG_DEBUG_FS)
if (!adev->psp.securedisplay_context.context.initialized)
return;
debugfs_create_file("securedisplay_test", S_IWUSR, adev_to_drm(adev)->primary->debugfs_root,
adev, &amdgpu_securedisplay_debugfs_ops);
#endif
}
|
/*
* Copyright 2015 Jelle de Jong <[email protected]>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
/dts-v1/;
#include "sun7i-a20.dtsi"
#include "sunxi-common-regulators.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
/ {
model = "Lamobo R1";
compatible = "lamobo,lamobo-r1", "allwinner,sun7i-a20";
aliases {
serial0 = &uart0;
serial1 = &uart3;
serial2 = &uart7;
};
chosen {
stdout-path = "serial0:115200n8";
};
hdmi-connector {
compatible = "hdmi-connector";
type = "a";
port {
hdmi_con_in: endpoint {
remote-endpoint = <&hdmi_out_con>;
};
};
};
leds {
compatible = "gpio-leds";
led {
label = "lamobo_r1:green:usr";
gpios = <&pio 7 24 GPIO_ACTIVE_HIGH>;
};
};
reg_gmac_3v3: gmac-3v3 {
compatible = "regulator-fixed";
regulator-name = "gmac-3v3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
startup-delay-us = <100000>;
enable-active-high;
gpio = <&pio 7 23 GPIO_ACTIVE_HIGH>; /* PH23 */
};
};
&ahci {
target-supply = <®_ahci_5v>;
status = "okay";
};
&codec {
status = "okay";
};
&cpu0 {
cpu-supply = <®_dcdc2>;
};
&de {
status = "okay";
};
&ehci0 {
status = "okay";
};
&ehci1 {
status = "okay";
};
&gmac {
pinctrl-names = "default";
pinctrl-0 = <&gmac_rgmii_pins>;
phy-mode = "rgmii";
phy-supply = <®_gmac_3v3>;
status = "okay";
fixed-link {
speed = <1000>;
full-duplex;
};
mdio {
compatible = "snps,dwmac-mdio";
#address-cells = <1>;
#size-cells = <0>;
switch: ethernet-switch@1e {
compatible = "brcm,bcm53125";
reg = <30>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port0: port@0 {
reg = <0>;
label = "lan2";
};
port1: port@1 {
reg = <1>;
label = "lan3";
};
port2: port@2 {
reg = <2>;
label = "lan4";
};
port3: port@3 {
reg = <3>;
label = "wan";
};
port4: port@4 {
reg = <4>;
label = "lan1";
};
port8: port@8 {
reg = <8>;
label = "cpu";
ethernet = <&gmac>;
phy-mode = "rgmii-txid";
fixed-link {
speed = <1000>;
full-duplex;
};
};
};
};
};
};
&hdmi {
status = "okay";
};
&hdmi_out {
hdmi_out_con: endpoint {
remote-endpoint = <&hdmi_con_in>;
};
};
&i2c0 {
status = "okay";
axp209: pmic@34 {
reg = <0x34>;
interrupt-parent = <&nmi_intc>;
interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
};
};
&i2c2 {
status = "okay";
};
&ir0 {
pinctrl-names = "default";
pinctrl-0 = <&ir0_rx_pin>;
status = "okay";
};
&mmc0 {
vmmc-supply = <®_vcc3v3>;
bus-width = <4>;
cd-gpios = <&pio 7 10 GPIO_ACTIVE_LOW>; /* PH10 */
status = "okay";
};
&ohci0 {
status = "okay";
};
&otg_sram {
status = "okay";
};
#include "axp209.dtsi"
&ac_power_supply {
status = "okay";
};
&battery_power_supply {
status = "okay";
};
®_ahci_5v {
gpio = <&pio 1 3 GPIO_ACTIVE_HIGH>; /* PB3 */
status = "okay";
};
®_dcdc2 {
regulator-always-on;
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1400000>;
regulator-name = "vdd-cpu";
};
®_dcdc3 {
regulator-always-on;
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1400000>;
regulator-name = "vdd-int-dll";
};
®_ldo1 {
regulator-name = "vdd-rtc";
};
®_ldo2 {
regulator-always-on;
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3000000>;
regulator-name = "avcc";
};
®_usb0_vbus {
status = "okay";
};
®_usb2_vbus {
gpio = <&pio 7 12 GPIO_ACTIVE_HIGH>; /* PH12 */
status = "okay";
};
&spi0 {
pinctrl-names = "default";
pinctrl-0 = <&spi0_pi_pins>,
<&spi0_cs0_pi_pin>,
<&spi0_cs1_pi_pin>;
status = "okay";
};
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pb_pins>;
status = "okay";
};
&uart3 {
pinctrl-names = "default";
pinctrl-0 = <&uart3_ph_pins>;
status = "okay";
};
&uart7 {
pinctrl-names = "default";
pinctrl-0 = <&uart7_pi_pins>;
status = "okay";
};
&usb_otg {
dr_mode = "otg";
status = "okay";
};
&usb_power_supply {
status = "okay";
};
&usbphy {
usb0_id_det-gpios = <&pio 7 4 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PH4 */
usb0_vbus_power-supply = <&usb_power_supply>;
usb0_vbus-supply = <®_usb0_vbus>;
usb2_vbus-supply = <®_usb2_vbus>;
status = "okay";
};
|
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2013
* Phillip Lougher <[email protected]>
*/
#include <linux/types.h>
#include <linux/slab.h>
#include <linux/percpu.h>
#include <linux/local_lock.h>
#include "squashfs_fs.h"
#include "squashfs_fs_sb.h"
#include "decompressor.h"
#include "squashfs.h"
/*
* This file implements multi-threaded decompression using percpu
* variables, one thread per cpu core.
*/
struct squashfs_stream {
void *stream;
local_lock_t lock;
};
static void *squashfs_decompressor_create(struct squashfs_sb_info *msblk,
void *comp_opts)
{
struct squashfs_stream *stream;
struct squashfs_stream __percpu *percpu;
int err, cpu;
percpu = alloc_percpu(struct squashfs_stream);
if (percpu == NULL)
return ERR_PTR(-ENOMEM);
for_each_possible_cpu(cpu) {
stream = per_cpu_ptr(percpu, cpu);
stream->stream = msblk->decompressor->init(msblk, comp_opts);
if (IS_ERR(stream->stream)) {
err = PTR_ERR(stream->stream);
goto out;
}
local_lock_init(&stream->lock);
}
kfree(comp_opts);
return (void *)(__force unsigned long) percpu;
out:
for_each_possible_cpu(cpu) {
stream = per_cpu_ptr(percpu, cpu);
if (!IS_ERR_OR_NULL(stream->stream))
msblk->decompressor->free(stream->stream);
}
free_percpu(percpu);
return ERR_PTR(err);
}
static void squashfs_decompressor_destroy(struct squashfs_sb_info *msblk)
{
struct squashfs_stream __percpu *percpu =
(void __percpu *)(unsigned long) msblk->stream;
struct squashfs_stream *stream;
int cpu;
if (msblk->stream) {
for_each_possible_cpu(cpu) {
stream = per_cpu_ptr(percpu, cpu);
msblk->decompressor->free(stream->stream);
}
free_percpu(percpu);
}
}
static int squashfs_decompress(struct squashfs_sb_info *msblk, struct bio *bio,
int offset, int length, struct squashfs_page_actor *output)
{
struct squashfs_stream *stream;
struct squashfs_stream __percpu *percpu =
(void __percpu *)(unsigned long) msblk->stream;
int res;
local_lock(&percpu->lock);
stream = this_cpu_ptr(percpu);
res = msblk->decompressor->decompress(msblk, stream->stream, bio,
offset, length, output);
local_unlock(&percpu->lock);
if (res < 0)
ERROR("%s decompression failed, data probably corrupt\n",
msblk->decompressor->name);
return res;
}
static int squashfs_max_decompressors(void)
{
return num_possible_cpus();
}
const struct squashfs_decompressor_thread_ops squashfs_decompressor_percpu = {
.create = squashfs_decompressor_create,
.destroy = squashfs_decompressor_destroy,
.decompress = squashfs_decompress,
.max_decompressors = squashfs_max_decompressors,
};
|
/* SPDX-License-Identifier: GPL-2.0 */
#ifndef _ASM_X86_CPU_ENTRY_AREA_H
#define _ASM_X86_CPU_ENTRY_AREA_H
#include <linux/percpu-defs.h>
#include <asm/processor.h>
#include <asm/intel_ds.h>
#include <asm/pgtable_areas.h>
#ifdef CONFIG_X86_64
#ifdef CONFIG_AMD_MEM_ENCRYPT
#define VC_EXCEPTION_STKSZ EXCEPTION_STKSZ
#else
#define VC_EXCEPTION_STKSZ 0
#endif
/* Macro to enforce the same ordering and stack sizes */
#define ESTACKS_MEMBERS(guardsize, optional_stack_size) \
char DF_stack_guard[guardsize]; \
char DF_stack[EXCEPTION_STKSZ]; \
char NMI_stack_guard[guardsize]; \
char NMI_stack[EXCEPTION_STKSZ]; \
char DB_stack_guard[guardsize]; \
char DB_stack[EXCEPTION_STKSZ]; \
char MCE_stack_guard[guardsize]; \
char MCE_stack[EXCEPTION_STKSZ]; \
char VC_stack_guard[guardsize]; \
char VC_stack[optional_stack_size]; \
char VC2_stack_guard[guardsize]; \
char VC2_stack[optional_stack_size]; \
char IST_top_guard[guardsize]; \
/* The exception stacks' physical storage. No guard pages required */
struct exception_stacks {
ESTACKS_MEMBERS(0, VC_EXCEPTION_STKSZ)
};
/* The effective cpu entry area mapping with guard pages. */
struct cea_exception_stacks {
ESTACKS_MEMBERS(PAGE_SIZE, EXCEPTION_STKSZ)
};
/*
* The exception stack ordering in [cea_]exception_stacks
*/
enum exception_stack_ordering {
ESTACK_DF,
ESTACK_NMI,
ESTACK_DB,
ESTACK_MCE,
ESTACK_VC,
ESTACK_VC2,
N_EXCEPTION_STACKS
};
#define CEA_ESTACK_SIZE(st) \
sizeof(((struct cea_exception_stacks *)0)->st## _stack)
#define CEA_ESTACK_BOT(ceastp, st) \
((unsigned long)&(ceastp)->st## _stack)
#define CEA_ESTACK_TOP(ceastp, st) \
(CEA_ESTACK_BOT(ceastp, st) + CEA_ESTACK_SIZE(st))
#define CEA_ESTACK_OFFS(st) \
offsetof(struct cea_exception_stacks, st## _stack)
#define CEA_ESTACK_PAGES \
(sizeof(struct cea_exception_stacks) / PAGE_SIZE)
#endif
#ifdef CONFIG_X86_32
struct doublefault_stack {
unsigned long stack[(PAGE_SIZE - sizeof(struct x86_hw_tss)) / sizeof(unsigned long)];
struct x86_hw_tss tss;
} __aligned(PAGE_SIZE);
#endif
/*
* cpu_entry_area is a percpu region that contains things needed by the CPU
* and early entry/exit code. Real types aren't used for all fields here
* to avoid circular header dependencies.
*
* Every field is a virtual alias of some other allocated backing store.
* There is no direct allocation of a struct cpu_entry_area.
*/
struct cpu_entry_area {
char gdt[PAGE_SIZE];
/*
* The GDT is just below entry_stack and thus serves (on x86_64) as
* a read-only guard page. On 32-bit the GDT must be writeable, so
* it needs an extra guard page.
*/
#ifdef CONFIG_X86_32
char guard_entry_stack[PAGE_SIZE];
#endif
struct entry_stack_page entry_stack_page;
#ifdef CONFIG_X86_32
char guard_doublefault_stack[PAGE_SIZE];
struct doublefault_stack doublefault_stack;
#endif
/*
* On x86_64, the TSS is mapped RO. On x86_32, it's mapped RW because
* we need task switches to work, and task switches write to the TSS.
*/
struct tss_struct tss;
#ifdef CONFIG_X86_64
/*
* Exception stacks used for IST entries with guard pages.
*/
struct cea_exception_stacks estacks;
#endif
/*
* Per CPU debug store for Intel performance monitoring. Wastes a
* full page at the moment.
*/
struct debug_store cpu_debug_store;
/*
* The actual PEBS/BTS buffers must be mapped to user space
* Reserve enough fixmap PTEs.
*/
struct debug_store_buffers cpu_debug_buffers;
};
#define CPU_ENTRY_AREA_SIZE (sizeof(struct cpu_entry_area))
DECLARE_PER_CPU(struct cpu_entry_area *, cpu_entry_area);
DECLARE_PER_CPU(struct cea_exception_stacks *, cea_exception_stacks);
extern void setup_cpu_entry_areas(void);
extern void cea_set_pte(void *cea_vaddr, phys_addr_t pa, pgprot_t flags);
extern struct cpu_entry_area *get_cpu_entry_area(int cpu);
static __always_inline struct entry_stack *cpu_entry_stack(int cpu)
{
return &get_cpu_entry_area(cpu)->entry_stack_page.stack;
}
#define __this_cpu_ist_top_va(name) \
CEA_ESTACK_TOP(__this_cpu_read(cea_exception_stacks), name)
#define __this_cpu_ist_bottom_va(name) \
CEA_ESTACK_BOT(__this_cpu_read(cea_exception_stacks), name)
#endif
|
// SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB
/*
* Copyright (c) 2022 Hewlett Packard Enterprise, Inc. All rights reserved.
* Copyright (c) 2016 Mellanox Technologies Ltd. All rights reserved.
* Copyright (c) 2015 System Fabric Works, Inc. All rights reserved.
*/
/*
* rxe_mcast.c implements driver support for multicast transport.
* It is based on two data structures struct rxe_mcg ('mcg') and
* struct rxe_mca ('mca'). An mcg is allocated each time a qp is
* attached to a new mgid for the first time. These are indexed by
* a red-black tree using the mgid. This data structure is searched
* for the mcg when a multicast packet is received and when another
* qp is attached to the same mgid. It is cleaned up when the last qp
* is detached from the mcg. Each time a qp is attached to an mcg an
* mca is created. It holds a pointer to the qp and is added to a list
* of qp's that are attached to the mcg. The qp_list is used to replicate
* mcast packets in the rxe receive path.
*/
#include "rxe.h"
/**
* rxe_mcast_add - add multicast address to rxe device
* @rxe: rxe device object
* @mgid: multicast address as a gid
*
* Returns 0 on success else an error
*/
static int rxe_mcast_add(struct rxe_dev *rxe, union ib_gid *mgid)
{
unsigned char ll_addr[ETH_ALEN];
ipv6_eth_mc_map((struct in6_addr *)mgid->raw, ll_addr);
return dev_mc_add(rxe->ndev, ll_addr);
}
/**
* rxe_mcast_del - delete multicast address from rxe device
* @rxe: rxe device object
* @mgid: multicast address as a gid
*
* Returns 0 on success else an error
*/
static int rxe_mcast_del(struct rxe_dev *rxe, union ib_gid *mgid)
{
unsigned char ll_addr[ETH_ALEN];
ipv6_eth_mc_map((struct in6_addr *)mgid->raw, ll_addr);
return dev_mc_del(rxe->ndev, ll_addr);
}
/**
* __rxe_insert_mcg - insert an mcg into red-black tree (rxe->mcg_tree)
* @mcg: mcg object with an embedded red-black tree node
*
* Context: caller must hold a reference to mcg and rxe->mcg_lock and
* is responsible to avoid adding the same mcg twice to the tree.
*/
static void __rxe_insert_mcg(struct rxe_mcg *mcg)
{
struct rb_root *tree = &mcg->rxe->mcg_tree;
struct rb_node **link = &tree->rb_node;
struct rb_node *node = NULL;
struct rxe_mcg *tmp;
int cmp;
while (*link) {
node = *link;
tmp = rb_entry(node, struct rxe_mcg, node);
cmp = memcmp(&tmp->mgid, &mcg->mgid, sizeof(mcg->mgid));
if (cmp > 0)
link = &(*link)->rb_left;
else
link = &(*link)->rb_right;
}
rb_link_node(&mcg->node, node, link);
rb_insert_color(&mcg->node, tree);
}
/**
* __rxe_remove_mcg - remove an mcg from red-black tree holding lock
* @mcg: mcast group object with an embedded red-black tree node
*
* Context: caller must hold a reference to mcg and rxe->mcg_lock
*/
static void __rxe_remove_mcg(struct rxe_mcg *mcg)
{
rb_erase(&mcg->node, &mcg->rxe->mcg_tree);
}
/**
* __rxe_lookup_mcg - lookup mcg in rxe->mcg_tree while holding lock
* @rxe: rxe device object
* @mgid: multicast IP address
*
* Context: caller must hold rxe->mcg_lock
* Returns: mcg on success and takes a ref to mcg else NULL
*/
static struct rxe_mcg *__rxe_lookup_mcg(struct rxe_dev *rxe,
union ib_gid *mgid)
{
struct rb_root *tree = &rxe->mcg_tree;
struct rxe_mcg *mcg;
struct rb_node *node;
int cmp;
node = tree->rb_node;
while (node) {
mcg = rb_entry(node, struct rxe_mcg, node);
cmp = memcmp(&mcg->mgid, mgid, sizeof(*mgid));
if (cmp > 0)
node = node->rb_left;
else if (cmp < 0)
node = node->rb_right;
else
break;
}
if (node) {
kref_get(&mcg->ref_cnt);
return mcg;
}
return NULL;
}
/**
* rxe_lookup_mcg - lookup up mcg in red-back tree
* @rxe: rxe device object
* @mgid: multicast IP address
*
* Returns: mcg if found else NULL
*/
struct rxe_mcg *rxe_lookup_mcg(struct rxe_dev *rxe, union ib_gid *mgid)
{
struct rxe_mcg *mcg;
spin_lock_bh(&rxe->mcg_lock);
mcg = __rxe_lookup_mcg(rxe, mgid);
spin_unlock_bh(&rxe->mcg_lock);
return mcg;
}
/**
* __rxe_init_mcg - initialize a new mcg
* @rxe: rxe device
* @mgid: multicast address as a gid
* @mcg: new mcg object
*
* Context: caller should hold rxe->mcg lock
*/
static void __rxe_init_mcg(struct rxe_dev *rxe, union ib_gid *mgid,
struct rxe_mcg *mcg)
{
kref_init(&mcg->ref_cnt);
memcpy(&mcg->mgid, mgid, sizeof(mcg->mgid));
INIT_LIST_HEAD(&mcg->qp_list);
mcg->rxe = rxe;
/* caller holds a ref on mcg but that will be
* dropped when mcg goes out of scope. We need to take a ref
* on the pointer that will be saved in the red-black tree
* by __rxe_insert_mcg and used to lookup mcg from mgid later.
* Inserting mcg makes it visible to outside so this should
* be done last after the object is ready.
*/
kref_get(&mcg->ref_cnt);
__rxe_insert_mcg(mcg);
}
/**
* rxe_get_mcg - lookup or allocate a mcg
* @rxe: rxe device object
* @mgid: multicast IP address as a gid
*
* Returns: mcg on success else ERR_PTR(error)
*/
static struct rxe_mcg *rxe_get_mcg(struct rxe_dev *rxe, union ib_gid *mgid)
{
struct rxe_mcg *mcg, *tmp;
int err;
if (rxe->attr.max_mcast_grp == 0)
return ERR_PTR(-EINVAL);
/* check to see if mcg already exists */
mcg = rxe_lookup_mcg(rxe, mgid);
if (mcg)
return mcg;
/* check to see if we have reached limit */
if (atomic_inc_return(&rxe->mcg_num) > rxe->attr.max_mcast_grp) {
err = -ENOMEM;
goto err_dec;
}
/* speculative alloc of new mcg */
mcg = kzalloc(sizeof(*mcg), GFP_KERNEL);
if (!mcg) {
err = -ENOMEM;
goto err_dec;
}
spin_lock_bh(&rxe->mcg_lock);
/* re-check to see if someone else just added it */
tmp = __rxe_lookup_mcg(rxe, mgid);
if (tmp) {
spin_unlock_bh(&rxe->mcg_lock);
atomic_dec(&rxe->mcg_num);
kfree(mcg);
return tmp;
}
__rxe_init_mcg(rxe, mgid, mcg);
spin_unlock_bh(&rxe->mcg_lock);
/* add mcast address outside of lock */
err = rxe_mcast_add(rxe, mgid);
if (!err)
return mcg;
kfree(mcg);
err_dec:
atomic_dec(&rxe->mcg_num);
return ERR_PTR(err);
}
/**
* rxe_cleanup_mcg - cleanup mcg for kref_put
* @kref: struct kref embnedded in mcg
*/
void rxe_cleanup_mcg(struct kref *kref)
{
struct rxe_mcg *mcg = container_of(kref, typeof(*mcg), ref_cnt);
kfree(mcg);
}
/**
* __rxe_destroy_mcg - destroy mcg object holding rxe->mcg_lock
* @mcg: the mcg object
*
* Context: caller is holding rxe->mcg_lock
* no qp's are attached to mcg
*/
static void __rxe_destroy_mcg(struct rxe_mcg *mcg)
{
struct rxe_dev *rxe = mcg->rxe;
/* remove mcg from red-black tree then drop ref */
__rxe_remove_mcg(mcg);
kref_put(&mcg->ref_cnt, rxe_cleanup_mcg);
atomic_dec(&rxe->mcg_num);
}
/**
* rxe_destroy_mcg - destroy mcg object
* @mcg: the mcg object
*
* Context: no qp's are attached to mcg
*/
static void rxe_destroy_mcg(struct rxe_mcg *mcg)
{
/* delete mcast address outside of lock */
rxe_mcast_del(mcg->rxe, &mcg->mgid);
spin_lock_bh(&mcg->rxe->mcg_lock);
__rxe_destroy_mcg(mcg);
spin_unlock_bh(&mcg->rxe->mcg_lock);
}
/**
* __rxe_init_mca - initialize a new mca holding lock
* @qp: qp object
* @mcg: mcg object
* @mca: empty space for new mca
*
* Context: caller must hold references on qp and mcg, rxe->mcg_lock
* and pass memory for new mca
*
* Returns: 0 on success else an error
*/
static int __rxe_init_mca(struct rxe_qp *qp, struct rxe_mcg *mcg,
struct rxe_mca *mca)
{
struct rxe_dev *rxe = to_rdev(qp->ibqp.device);
int n;
n = atomic_inc_return(&rxe->mcg_attach);
if (n > rxe->attr.max_total_mcast_qp_attach) {
atomic_dec(&rxe->mcg_attach);
return -ENOMEM;
}
n = atomic_inc_return(&mcg->qp_num);
if (n > rxe->attr.max_mcast_qp_attach) {
atomic_dec(&mcg->qp_num);
atomic_dec(&rxe->mcg_attach);
return -ENOMEM;
}
atomic_inc(&qp->mcg_num);
rxe_get(qp);
mca->qp = qp;
list_add_tail(&mca->qp_list, &mcg->qp_list);
return 0;
}
/**
* rxe_attach_mcg - attach qp to mcg if not already attached
* @qp: qp object
* @mcg: mcg object
*
* Context: caller must hold reference on qp and mcg.
* Returns: 0 on success else an error
*/
static int rxe_attach_mcg(struct rxe_mcg *mcg, struct rxe_qp *qp)
{
struct rxe_dev *rxe = mcg->rxe;
struct rxe_mca *mca, *tmp;
int err;
/* check to see if the qp is already a member of the group */
spin_lock_bh(&rxe->mcg_lock);
list_for_each_entry(mca, &mcg->qp_list, qp_list) {
if (mca->qp == qp) {
spin_unlock_bh(&rxe->mcg_lock);
return 0;
}
}
spin_unlock_bh(&rxe->mcg_lock);
/* speculative alloc new mca without using GFP_ATOMIC */
mca = kzalloc(sizeof(*mca), GFP_KERNEL);
if (!mca)
return -ENOMEM;
spin_lock_bh(&rxe->mcg_lock);
/* re-check to see if someone else just attached qp */
list_for_each_entry(tmp, &mcg->qp_list, qp_list) {
if (tmp->qp == qp) {
kfree(mca);
err = 0;
goto out;
}
}
err = __rxe_init_mca(qp, mcg, mca);
if (err)
kfree(mca);
out:
spin_unlock_bh(&rxe->mcg_lock);
return err;
}
/**
* __rxe_cleanup_mca - cleanup mca object holding lock
* @mca: mca object
* @mcg: mcg object
*
* Context: caller must hold a reference to mcg and rxe->mcg_lock
*/
static void __rxe_cleanup_mca(struct rxe_mca *mca, struct rxe_mcg *mcg)
{
list_del(&mca->qp_list);
atomic_dec(&mcg->qp_num);
atomic_dec(&mcg->rxe->mcg_attach);
atomic_dec(&mca->qp->mcg_num);
rxe_put(mca->qp);
kfree(mca);
}
/**
* rxe_detach_mcg - detach qp from mcg
* @mcg: mcg object
* @qp: qp object
*
* Returns: 0 on success else an error if qp is not attached.
*/
static int rxe_detach_mcg(struct rxe_mcg *mcg, struct rxe_qp *qp)
{
struct rxe_dev *rxe = mcg->rxe;
struct rxe_mca *mca, *tmp;
spin_lock_bh(&rxe->mcg_lock);
list_for_each_entry_safe(mca, tmp, &mcg->qp_list, qp_list) {
if (mca->qp == qp) {
__rxe_cleanup_mca(mca, mcg);
/* if the number of qp's attached to the
* mcast group falls to zero go ahead and
* tear it down. This will not free the
* object since we are still holding a ref
* from the caller
*/
if (atomic_read(&mcg->qp_num) <= 0)
__rxe_destroy_mcg(mcg);
spin_unlock_bh(&rxe->mcg_lock);
return 0;
}
}
/* we didn't find the qp on the list */
spin_unlock_bh(&rxe->mcg_lock);
return -EINVAL;
}
/**
* rxe_attach_mcast - attach qp to multicast group (see IBA-11.3.1)
* @ibqp: (IB) qp object
* @mgid: multicast IP address
* @mlid: multicast LID, ignored for RoCEv2 (see IBA-A17.5.6)
*
* Returns: 0 on success else an errno
*/
int rxe_attach_mcast(struct ib_qp *ibqp, union ib_gid *mgid, u16 mlid)
{
int err;
struct rxe_dev *rxe = to_rdev(ibqp->device);
struct rxe_qp *qp = to_rqp(ibqp);
struct rxe_mcg *mcg;
/* takes a ref on mcg if successful */
mcg = rxe_get_mcg(rxe, mgid);
if (IS_ERR(mcg))
return PTR_ERR(mcg);
err = rxe_attach_mcg(mcg, qp);
/* if we failed to attach the first qp to mcg tear it down */
if (atomic_read(&mcg->qp_num) == 0)
rxe_destroy_mcg(mcg);
kref_put(&mcg->ref_cnt, rxe_cleanup_mcg);
return err;
}
/**
* rxe_detach_mcast - detach qp from multicast group (see IBA-11.3.2)
* @ibqp: address of (IB) qp object
* @mgid: multicast IP address
* @mlid: multicast LID, ignored for RoCEv2 (see IBA-A17.5.6)
*
* Returns: 0 on success else an errno
*/
int rxe_detach_mcast(struct ib_qp *ibqp, union ib_gid *mgid, u16 mlid)
{
struct rxe_dev *rxe = to_rdev(ibqp->device);
struct rxe_qp *qp = to_rqp(ibqp);
struct rxe_mcg *mcg;
int err;
mcg = rxe_lookup_mcg(rxe, mgid);
if (!mcg)
return -EINVAL;
err = rxe_detach_mcg(mcg, qp);
kref_put(&mcg->ref_cnt, rxe_cleanup_mcg);
return err;
}
|
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
* Keerthy <[email protected]>
*
* Based on the LP873X driver
*/
#include <linux/gpio/driver.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <linux/mfd/lp87565.h>
struct lp87565_gpio {
struct gpio_chip chip;
struct regmap *map;
};
static int lp87565_gpio_get(struct gpio_chip *chip, unsigned int offset)
{
struct lp87565_gpio *gpio = gpiochip_get_data(chip);
int ret, val;
ret = regmap_read(gpio->map, LP87565_REG_GPIO_IN, &val);
if (ret < 0)
return ret;
return !!(val & BIT(offset));
}
static void lp87565_gpio_set(struct gpio_chip *chip, unsigned int offset,
int value)
{
struct lp87565_gpio *gpio = gpiochip_get_data(chip);
regmap_update_bits(gpio->map, LP87565_REG_GPIO_OUT,
BIT(offset), value ? BIT(offset) : 0);
}
static int lp87565_gpio_get_direction(struct gpio_chip *chip,
unsigned int offset)
{
struct lp87565_gpio *gpio = gpiochip_get_data(chip);
int ret, val;
ret = regmap_read(gpio->map, LP87565_REG_GPIO_CONFIG, &val);
if (ret < 0)
return ret;
if (val & BIT(offset))
return GPIO_LINE_DIRECTION_OUT;
return GPIO_LINE_DIRECTION_IN;
}
static int lp87565_gpio_direction_input(struct gpio_chip *chip,
unsigned int offset)
{
struct lp87565_gpio *gpio = gpiochip_get_data(chip);
return regmap_update_bits(gpio->map,
LP87565_REG_GPIO_CONFIG,
BIT(offset), 0);
}
static int lp87565_gpio_direction_output(struct gpio_chip *chip,
unsigned int offset, int value)
{
struct lp87565_gpio *gpio = gpiochip_get_data(chip);
lp87565_gpio_set(chip, offset, value);
return regmap_update_bits(gpio->map,
LP87565_REG_GPIO_CONFIG,
BIT(offset), BIT(offset));
}
static int lp87565_gpio_request(struct gpio_chip *gc, unsigned int offset)
{
struct lp87565_gpio *gpio = gpiochip_get_data(gc);
int ret;
switch (offset) {
case 0:
case 1:
case 2:
/*
* MUX can program the pin to be in EN1/2/3 pin mode
* Or GPIO1/2/3 mode.
* Setup the GPIO*_SEL MUX to GPIO mode
*/
ret = regmap_update_bits(gpio->map,
LP87565_REG_PIN_FUNCTION,
BIT(offset), BIT(offset));
if (ret)
return ret;
break;
default:
return -EINVAL;
}
return 0;
}
static int lp87565_gpio_set_config(struct gpio_chip *gc, unsigned int offset,
unsigned long config)
{
struct lp87565_gpio *gpio = gpiochip_get_data(gc);
switch (pinconf_to_config_param(config)) {
case PIN_CONFIG_DRIVE_OPEN_DRAIN:
return regmap_update_bits(gpio->map,
LP87565_REG_GPIO_CONFIG,
BIT(offset +
__ffs(LP87565_GPIO1_OD)),
BIT(offset +
__ffs(LP87565_GPIO1_OD)));
case PIN_CONFIG_DRIVE_PUSH_PULL:
return regmap_update_bits(gpio->map,
LP87565_REG_GPIO_CONFIG,
BIT(offset +
__ffs(LP87565_GPIO1_OD)), 0);
default:
return -ENOTSUPP;
}
}
static const struct gpio_chip template_chip = {
.label = "lp87565-gpio",
.owner = THIS_MODULE,
.request = lp87565_gpio_request,
.get_direction = lp87565_gpio_get_direction,
.direction_input = lp87565_gpio_direction_input,
.direction_output = lp87565_gpio_direction_output,
.get = lp87565_gpio_get,
.set = lp87565_gpio_set,
.set_config = lp87565_gpio_set_config,
.base = -1,
.ngpio = 3,
.can_sleep = true,
};
static int lp87565_gpio_probe(struct platform_device *pdev)
{
struct lp87565_gpio *gpio;
struct lp87565 *lp87565;
int ret;
gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL);
if (!gpio)
return -ENOMEM;
lp87565 = dev_get_drvdata(pdev->dev.parent);
gpio->chip = template_chip;
gpio->chip.parent = lp87565->dev;
gpio->map = lp87565->regmap;
ret = devm_gpiochip_add_data(&pdev->dev, &gpio->chip, gpio);
if (ret < 0) {
dev_err(&pdev->dev, "Could not register gpiochip, %d\n", ret);
return ret;
}
return 0;
}
static const struct platform_device_id lp87565_gpio_id_table[] = {
{ "lp87565-q1-gpio", },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(platform, lp87565_gpio_id_table);
static struct platform_driver lp87565_gpio_driver = {
.driver = {
.name = "lp87565-gpio",
},
.probe = lp87565_gpio_probe,
.id_table = lp87565_gpio_id_table,
};
module_platform_driver(lp87565_gpio_driver);
MODULE_AUTHOR("Keerthy <[email protected]>");
MODULE_DESCRIPTION("LP87565 GPIO driver");
MODULE_LICENSE("GPL v2");
|
// SPDX-License-Identifier: GPL-2.0
#include "qcom-msm8974pro.dtsi"
#include "pma8084.dtsi"
#include <dt-bindings/input/input.h>
#include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
#include <dt-bindings/leds/common.h>
/ {
chassis-type = "handset";
aliases {
serial0 = &blsp1_uart1;
mmc0 = &sdhc_1; /* SDC1 eMMC slot */
mmc1 = &sdhc_3; /* SDC2 SD card slot */
};
chosen {
stdout-path = "serial0:115200n8";
};
gpio-keys {
compatible = "gpio-keys";
pinctrl-names = "default";
pinctrl-0 = <&gpio_keys_pin_a>;
key-volume-down {
label = "volume_down";
gpios = <&pma8084_gpios 2 GPIO_ACTIVE_LOW>;
linux,input-type = <1>;
linux,code = <KEY_VOLUMEDOWN>;
debounce-interval = <15>;
};
key-home {
label = "home_key";
gpios = <&pma8084_gpios 3 GPIO_ACTIVE_LOW>;
linux,input-type = <1>;
linux,code = <KEY_HOMEPAGE>;
wakeup-source;
debounce-interval = <15>;
};
key-volume-up {
label = "volume_up";
gpios = <&pma8084_gpios 5 GPIO_ACTIVE_LOW>;
linux,input-type = <1>;
linux,code = <KEY_VOLUMEUP>;
debounce-interval = <15>;
};
};
i2c-gpio-touchkey {
compatible = "i2c-gpio";
#address-cells = <1>;
#size-cells = <0>;
sda-gpios = <&tlmm 95 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
scl-gpios = <&tlmm 96 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
pinctrl-names = "default";
pinctrl-0 = <&i2c_touchkey_pins>;
touchkey@20 {
compatible = "cypress,tm2-touchkey";
reg = <0x20>;
interrupt-parent = <&pma8084_gpios>;
interrupts = <6 IRQ_TYPE_EDGE_FALLING>;
pinctrl-names = "default";
pinctrl-0 = <&touchkey_pin>;
vcc-supply = <&max77826_ldo15>;
vdd-supply = <&pma8084_l19>;
linux,keycodes = <KEY_APPSELECT KEY_BACK>;
};
};
i2c_led_gpio: i2c-gpio-led {
compatible = "i2c-gpio";
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&i2c_led_gpioex_pins>;
i2c-gpio,delay-us = <2>;
gpio_expander: gpio@20 {
compatible = "nxp,pcal6416";
reg = <0x20>;
gpio-controller;
#gpio-cells = <2>;
vcc-supply = <&pma8084_s4>;
pinctrl-names = "default";
pinctrl-0 = <&gpioex_pin>;
reset-gpios = <&tlmm 145 GPIO_ACTIVE_LOW>;
};
led-controller@30 {
compatible = "panasonic,an30259a";
reg = <0x30>;
#address-cells = <1>;
#size-cells = <0>;
led@1 {
reg = <1>;
function = LED_FUNCTION_STATUS;
color = <LED_COLOR_ID_RED>;
};
led@2 {
reg = <2>;
function = LED_FUNCTION_STATUS;
color = <LED_COLOR_ID_GREEN>;
};
led@3 {
reg = <3>;
function = LED_FUNCTION_STATUS;
color = <LED_COLOR_ID_BLUE>;
};
};
};
vreg_wlan: wlan-regulator {
compatible = "regulator-fixed";
regulator-name = "wl-reg";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio_expander 8 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
vreg_panel: panel-regulator {
compatible = "regulator-fixed";
pinctrl-names = "default";
pinctrl-0 = <&panel_en_pin>;
regulator-name = "panel-vddr-reg";
regulator-min-microvolt = <1500000>;
regulator-max-microvolt = <1500000>;
gpio = <&pma8084_gpios 14 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
vreg_vph_pwr: vreg-vph-pwr {
compatible = "regulator-fixed";
regulator-name = "vph-pwr";
regulator-min-microvolt = <3600000>;
regulator-max-microvolt = <3600000>;
regulator-always-on;
};
};
&blsp1_i2c2 {
status = "okay";
touchscreen@20 {
compatible = "syna,rmi4-i2c";
reg = <0x20>;
interrupt-parent = <&pma8084_gpios>;
interrupts = <8 IRQ_TYPE_EDGE_FALLING>;
vdd-supply = <&max77826_ldo13>;
vio-supply = <&pma8084_lvs2>;
pinctrl-names = "default";
pinctrl-0 = <&touch_pin>;
syna,startup-delay-ms = <100>;
#address-cells = <1>;
#size-cells = <0>;
rmi4-f01@1 {
reg = <0x1>;
syna,nosleep-mode = <1>;
};
rmi4-f12@12 {
reg = <0x12>;
syna,sensor-type = <1>;
};
};
};
&blsp1_i2c6 {
status = "okay";
pmic@60 {
reg = <0x60>;
compatible = "maxim,max77826";
regulators {
max77826_ldo1: LDO1 {
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
};
max77826_ldo2: LDO2 {
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1000000>;
};
max77826_ldo3: LDO3 {
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
};
max77826_ldo4: LDO4 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
max77826_ldo5: LDO5 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
max77826_ldo6: LDO6 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
};
max77826_ldo7: LDO7 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
max77826_ldo8: LDO8 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
};
max77826_ldo9: LDO9 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
max77826_ldo10: LDO10 {
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2950000>;
};
max77826_ldo11: LDO11 {
regulator-min-microvolt = <2700000>;
regulator-max-microvolt = <2950000>;
};
max77826_ldo12: LDO12 {
regulator-min-microvolt = <2500000>;
regulator-max-microvolt = <3300000>;
};
max77826_ldo13: LDO13 {
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
max77826_ldo14: LDO14 {
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
max77826_ldo15: LDO15 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
max77826_buck: BUCK {
regulator-min-microvolt = <1225000>;
regulator-max-microvolt = <1225000>;
};
max77826_buckboost: BUCKBOOST {
regulator-min-microvolt = <3400000>;
regulator-max-microvolt = <3400000>;
};
};
};
};
&blsp1_uart2 {
status = "okay";
};
&blsp2_i2c6 {
status = "okay";
fuelgauge@36 {
compatible = "maxim,max17048";
reg = <0x36>;
maxim,double-soc;
maxim,rcomp = /bits/ 8 <0x56>;
interrupt-parent = <&pma8084_gpios>;
interrupts = <21 IRQ_TYPE_LEVEL_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&fuelgauge_pin>;
};
};
&blsp2_uart2 {
status = "okay";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&blsp2_uart2_pins_active>;
pinctrl-1 = <&blsp2_uart2_pins_sleep>;
bluetooth {
compatible = "brcm,bcm43540-bt";
max-speed = <3000000>;
pinctrl-names = "default";
pinctrl-0 = <&bt_pins>;
device-wakeup-gpios = <&tlmm 91 GPIO_ACTIVE_HIGH>;
shutdown-gpios = <&gpio_expander 9 GPIO_ACTIVE_HIGH>;
interrupt-parent = <&tlmm>;
interrupts = <75 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "host-wakeup";
};
};
&gpu {
status = "okay";
};
&mdss {
status = "okay";
};
&mdss_dsi0 {
status = "okay";
vdda-supply = <&pma8084_l2>;
vdd-supply = <&pma8084_l22>;
vddio-supply = <&pma8084_l12>;
panel: panel@0 {
reg = <0>;
compatible = "samsung,s6e3fa2";
pinctrl-names = "default";
pinctrl-0 = <&panel_te_pin &panel_rst_pin>;
iovdd-supply = <&pma8084_lvs4>;
vddr-supply = <&vreg_panel>;
reset-gpios = <&pma8084_gpios 17 GPIO_ACTIVE_LOW>;
port {
panel_in: endpoint {
remote-endpoint = <&mdss_dsi0_out>;
};
};
};
};
&mdss_dsi0_out {
remote-endpoint = <&panel_in>;
data-lanes = <0 1 2 3>;
};
&mdss_dsi0_phy {
status = "okay";
vddio-supply = <&pma8084_l12>;
};
&pma8084_gpios {
gpio_keys_pin_a: gpio-keys-active-state {
pins = "gpio2", "gpio3", "gpio5";
function = "normal";
bias-pull-up;
power-source = <PMA8084_GPIO_S4>;
};
touchkey_pin: touchkey-int-state {
pins = "gpio6";
function = "normal";
bias-disable;
input-enable;
power-source = <PMA8084_GPIO_S4>;
};
touch_pin: touchscreen-int-state {
pins = "gpio8";
function = "normal";
bias-disable;
input-enable;
power-source = <PMA8084_GPIO_S4>;
};
panel_en_pin: panel-en-state {
pins = "gpio14";
function = "normal";
bias-pull-up;
power-source = <PMA8084_GPIO_S4>;
qcom,drive-strength = <PMIC_GPIO_STRENGTH_LOW>;
};
wlan_sleep_clk_pin: wlan-sleep-clk-state {
pins = "gpio16";
function = "func2";
output-high;
power-source = <PMA8084_GPIO_S4>;
qcom,drive-strength = <PMIC_GPIO_STRENGTH_HIGH>;
};
panel_rst_pin: panel-rst-state {
pins = "gpio17";
function = "normal";
bias-disable;
power-source = <PMA8084_GPIO_S4>;
qcom,drive-strength = <PMIC_GPIO_STRENGTH_LOW>;
};
fuelgauge_pin: fuelgauge-int-state {
pins = "gpio21";
function = "normal";
bias-disable;
input-enable;
power-source = <PMA8084_GPIO_S4>;
};
};
&reserved_memory {
ramoops@3e8e0000 {
compatible = "ramoops";
reg = <0x3e8e0000 0x200000>;
console-size = <0x100000>;
record-size = <0x10000>;
ftrace-size = <0x10000>;
pmsg-size = <0x80000>;
ecc-size = <8>;
};
};
&remoteproc_adsp {
status = "okay";
cx-supply = <&pma8084_s2>;
};
&remoteproc_mss {
status = "okay";
cx-supply = <&pma8084_s2>;
mss-supply = <&pma8084_s6>;
mx-supply = <&pma8084_s1>;
pll-supply = <&pma8084_l12>;
};
&rpm_requests {
regulators-0 {
compatible = "qcom,rpm-pma8084-regulators";
pma8084_s1: s1 {
regulator-min-microvolt = <675000>;
regulator-max-microvolt = <1050000>;
regulator-always-on;
};
pma8084_s2: s2 {
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <1050000>;
};
pma8084_s3: s3 {
regulator-min-microvolt = <1300000>;
regulator-max-microvolt = <1300000>;
};
pma8084_s4: s4 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
pma8084_s5: s5 {
regulator-min-microvolt = <2150000>;
regulator-max-microvolt = <2150000>;
};
pma8084_s6: s6 {
regulator-min-microvolt = <1050000>;
regulator-max-microvolt = <1050000>;
};
pma8084_l1: l1 {
regulator-min-microvolt = <1225000>;
regulator-max-microvolt = <1225000>;
};
pma8084_l2: l2 {
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
};
pma8084_l3: l3 {
regulator-min-microvolt = <1050000>;
regulator-max-microvolt = <1200000>;
};
pma8084_l4: l4 {
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1225000>;
};
pma8084_l5: l5 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
pma8084_l6: l6 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
pma8084_l7: l7 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
pma8084_l8: l8 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
pma8084_l9: l9 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <2950000>;
};
pma8084_l10: l10 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <2950000>;
};
pma8084_l11: l11 {
regulator-min-microvolt = <1300000>;
regulator-max-microvolt = <1300000>;
};
pma8084_l12: l12 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
};
pma8084_l13: l13 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <2950000>;
};
pma8084_l14: l14 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
pma8084_l15: l15 {
regulator-min-microvolt = <2050000>;
regulator-max-microvolt = <2050000>;
};
pma8084_l16: l16 {
regulator-min-microvolt = <2700000>;
regulator-max-microvolt = <2700000>;
};
pma8084_l17: l17 {
regulator-min-microvolt = <2850000>;
regulator-max-microvolt = <2850000>;
};
pma8084_l18: l18 {
regulator-min-microvolt = <2850000>;
regulator-max-microvolt = <2850000>;
};
pma8084_l19: l19 {
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
pma8084_l20: l20 {
regulator-min-microvolt = <2950000>;
regulator-max-microvolt = <2950000>;
regulator-system-load = <200000>;
regulator-allow-set-load;
};
pma8084_l21: l21 {
regulator-min-microvolt = <2950000>;
regulator-max-microvolt = <2950000>;
regulator-system-load = <200000>;
regulator-allow-set-load;
};
pma8084_l22: l22 {
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3300000>;
};
pma8084_l23: l23 {
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3000000>;
};
pma8084_l24: l24 {
regulator-min-microvolt = <3075000>;
regulator-max-microvolt = <3075000>;
};
pma8084_l25: l25 {
regulator-min-microvolt = <2100000>;
regulator-max-microvolt = <2100000>;
};
pma8084_l26: l26 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <2050000>;
};
pma8084_l27: l27 {
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1225000>;
};
pma8084_lvs1: lvs1 {};
pma8084_lvs2: lvs2 {};
pma8084_lvs3: lvs3 {};
pma8084_lvs4: lvs4 {};
pma8084_5vs1: 5vs1 {};
};
};
&sdhc_1 {
status = "okay";
vmmc-supply = <&pma8084_l20>;
vqmmc-supply = <&pma8084_s4>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&sdc1_on>;
pinctrl-1 = <&sdc1_off>;
};
&sdhc_2 {
status = "okay";
max-frequency = <100000000>;
vmmc-supply = <&vreg_wlan>;
vqmmc-supply = <&pma8084_s4>;
non-removable;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&sdc2_on>;
pinctrl-1 = <&sdc2_off>;
wifi@1 {
reg = <1>;
compatible = "brcm,bcm4329-fmac";
/*
* Allow all klte* variants to load the same NVRAM file,
* as they have little difference in the WiFi part.
*/
brcm,board-type = "samsung,klte";
interrupt-parent = <&tlmm>;
interrupts = <92 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "host-wake";
pinctrl-names = "default";
pinctrl-0 = <&wlan_sleep_clk_pin &wifi_pin>;
};
};
&sdhc_3 {
status = "okay";
max-frequency = <100000000>;
vmmc-supply = <&pma8084_l21>;
vqmmc-supply = <&pma8084_l13>;
/*
* cd-gpio is intentionally disabled. If enabled, an SD card
* present during boot is not initialized correctly. Without
* cd-gpios the driver resorts to polling, so hotplug works.
*/
pinctrl-names = "default";
pinctrl-0 = <&sdc3_on /* &sdhc3_cd_pin */>;
/* cd-gpios = <&tlmm 62 GPIO_ACTIVE_LOW>; */
};
&tlmm {
/* This seems suspicious, but somebody with this device should look into it. */
blsp2_uart2_pins_active: blsp2-uart2-pins-active-state {
pins = "gpio45", "gpio46", "gpio47", "gpio48";
function = "blsp_uart8";
drive-strength = <8>;
bias-disable;
};
blsp2_uart2_pins_sleep: blsp2-uart2-pins-sleep-state {
pins = "gpio45", "gpio46", "gpio47", "gpio48";
function = "gpio";
drive-strength = <2>;
bias-pull-down;
};
bt_pins: bt-pins-state {
hostwake-pins {
pins = "gpio75";
function = "gpio";
drive-strength = <16>;
};
devwake-pins {
pins = "gpio91";
function = "gpio";
drive-strength = <2>;
};
};
sdc1_on: sdhc1-on-state {
clk-pins {
pins = "sdc1_clk";
drive-strength = <4>;
bias-disable;
};
cmd-data-pins {
pins = "sdc1_cmd", "sdc1_data";
drive-strength = <4>;
bias-pull-up;
};
};
sdc3_on: sdc3-on-state {
pins = "gpio35", "gpio36", "gpio37", "gpio38", "gpio39", "gpio40";
function = "sdc3";
drive-strength = <8>;
bias-disable;
};
sdhc3_cd_pin: sdc3-cd-on-state {
pins = "gpio62";
function = "gpio";
drive-strength = <2>;
bias-disable;
};
sdc2_on: sdhc2-on-state {
clk-pins {
pins = "sdc2_clk";
drive-strength = <6>;
bias-disable;
};
cmd-data-pins {
pins = "sdc2_cmd", "sdc2_data";
drive-strength = <6>;
bias-pull-up;
};
};
i2c_touchkey_pins: i2c-touchkey-state {
pins = "gpio95", "gpio96";
function = "gpio";
bias-pull-up;
};
i2c_led_gpioex_pins: i2c-led-gpioex-state {
function = "gpio";
bias-pull-down;
};
gpioex_pin: gpioex-state {
pins = "gpio145";
function = "gpio";
bias-pull-up;
drive-strength = <2>;
};
wifi_pin: wifi-state {
pins = "gpio92";
function = "gpio";
bias-pull-down;
};
panel_te_pin: panel-state {
pins = "gpio12";
function = "mdp_vsync";
drive-strength = <2>;
bias-disable;
};
};
&usb {
status = "okay";
phys = <&usb_hs1_phy>;
phy-select = <&tcsr 0xb000 0>;
hnp-disable;
srp-disable;
adp-disable;
};
&usb_hs1_phy {
status = "okay";
v1p8-supply = <&pma8084_l6>;
v3p3-supply = <&pma8084_l24>;
qcom,init-seq = /bits/ 8 <0x1 0x64>;
};
|
// SPDX-License-Identifier: GPL-2.0-only
/*
* Windfarm PowerMac thermal control.
* Control loops for machines with SMU and PPC970MP processors.
*
* Copyright (C) 2005 Paul Mackerras, IBM Corp. <[email protected]>
* Copyright (C) 2006 Benjamin Herrenschmidt, IBM Corp.
*/
#include <linux/types.h>
#include <linux/errno.h>
#include <linux/kernel.h>
#include <linux/device.h>
#include <linux/platform_device.h>
#include <linux/reboot.h>
#include <linux/of.h>
#include <linux/slab.h>
#include <asm/smu.h>
#include "windfarm.h"
#include "windfarm_pid.h"
#define VERSION "0.2"
#define DEBUG
#undef LOTSA_DEBUG
#ifdef DEBUG
#define DBG(args...) printk(args)
#else
#define DBG(args...) do { } while(0)
#endif
#ifdef LOTSA_DEBUG
#define DBG_LOTS(args...) printk(args)
#else
#define DBG_LOTS(args...) do { } while(0)
#endif
/* define this to force CPU overtemp to 60 degree, useful for testing
* the overtemp code
*/
#undef HACKED_OVERTEMP
/* We currently only handle 2 chips, 4 cores... */
#define NR_CHIPS 2
#define NR_CORES 4
#define NR_CPU_FANS 3 * NR_CHIPS
/* Controls and sensors */
static struct wf_sensor *sens_cpu_temp[NR_CORES];
static struct wf_sensor *sens_cpu_power[NR_CORES];
static struct wf_sensor *hd_temp;
static struct wf_sensor *slots_power;
static struct wf_sensor *u4_temp;
static struct wf_control *cpu_fans[NR_CPU_FANS];
static char *cpu_fan_names[NR_CPU_FANS] = {
"cpu-rear-fan-0",
"cpu-rear-fan-1",
"cpu-front-fan-0",
"cpu-front-fan-1",
"cpu-pump-0",
"cpu-pump-1",
};
static struct wf_control *cpufreq_clamp;
/* Second pump isn't required (and isn't actually present) */
#define CPU_FANS_REQD (NR_CPU_FANS - 2)
#define FIRST_PUMP 4
#define LAST_PUMP 5
/* We keep a temperature history for average calculation of 180s */
#define CPU_TEMP_HIST_SIZE 180
/* Scale factor for fan speed, *100 */
static int cpu_fan_scale[NR_CPU_FANS] = {
100,
100,
97, /* inlet fans run at 97% of exhaust fan */
97,
100, /* updated later */
100, /* updated later */
};
static struct wf_control *backside_fan;
static struct wf_control *slots_fan;
static struct wf_control *drive_bay_fan;
/* PID loop state */
static struct wf_cpu_pid_state cpu_pid[NR_CORES];
static u32 cpu_thist[CPU_TEMP_HIST_SIZE];
static int cpu_thist_pt;
static s64 cpu_thist_total;
static s32 cpu_all_tmax = 100 << 16;
static int cpu_last_target;
static struct wf_pid_state backside_pid;
static int backside_tick;
static struct wf_pid_state slots_pid;
static bool slots_started;
static struct wf_pid_state drive_bay_pid;
static int drive_bay_tick;
static int nr_cores;
static int have_all_controls;
static int have_all_sensors;
static bool started;
static int failure_state;
#define FAILURE_SENSOR 1
#define FAILURE_FAN 2
#define FAILURE_PERM 4
#define FAILURE_LOW_OVERTEMP 8
#define FAILURE_HIGH_OVERTEMP 16
/* Overtemp values */
#define LOW_OVER_AVERAGE 0
#define LOW_OVER_IMMEDIATE (10 << 16)
#define LOW_OVER_CLEAR ((-10) << 16)
#define HIGH_OVER_IMMEDIATE (14 << 16)
#define HIGH_OVER_AVERAGE (10 << 16)
#define HIGH_OVER_IMMEDIATE (14 << 16)
/* Implementation... */
static int create_cpu_loop(int cpu)
{
int chip = cpu / 2;
int core = cpu & 1;
struct smu_sdbp_header *hdr;
struct smu_sdbp_cpupiddata *piddata;
struct wf_cpu_pid_param pid;
struct wf_control *main_fan = cpu_fans[0];
s32 tmax;
int fmin;
/* Get FVT params to get Tmax; if not found, assume default */
hdr = smu_sat_get_sdb_partition(chip, 0xC4 + core, NULL);
if (hdr) {
struct smu_sdbp_fvt *fvt = (struct smu_sdbp_fvt *)&hdr[1];
tmax = fvt->maxtemp << 16;
} else
tmax = 95 << 16; /* default to 95 degrees C */
/* We keep a global tmax for overtemp calculations */
if (tmax < cpu_all_tmax)
cpu_all_tmax = tmax;
kfree(hdr);
/* Get PID params from the appropriate SAT */
hdr = smu_sat_get_sdb_partition(chip, 0xC8 + core, NULL);
if (hdr == NULL) {
printk(KERN_WARNING"windfarm: can't get CPU PID fan config\n");
return -EINVAL;
}
piddata = (struct smu_sdbp_cpupiddata *)&hdr[1];
/*
* Darwin has a minimum fan speed of 1000 rpm for the 4-way and
* 515 for the 2-way. That appears to be overkill, so for now,
* impose a minimum of 750 or 515.
*/
fmin = (nr_cores > 2) ? 750 : 515;
/* Initialize PID loop */
pid.interval = 1; /* seconds */
pid.history_len = piddata->history_len;
pid.gd = piddata->gd;
pid.gp = piddata->gp;
pid.gr = piddata->gr / piddata->history_len;
pid.pmaxadj = (piddata->max_power << 16) - (piddata->power_adj << 8);
pid.ttarget = tmax - (piddata->target_temp_delta << 16);
pid.tmax = tmax;
pid.min = main_fan->ops->get_min(main_fan);
pid.max = main_fan->ops->get_max(main_fan);
if (pid.min < fmin)
pid.min = fmin;
wf_cpu_pid_init(&cpu_pid[cpu], &pid);
kfree(hdr);
return 0;
}
static void cpu_max_all_fans(void)
{
int i;
/* We max all CPU fans in case of a sensor error. We also do the
* cpufreq clamping now, even if it's supposedly done later by the
* generic code anyway, we do it earlier here to react faster
*/
if (cpufreq_clamp)
wf_control_set_max(cpufreq_clamp);
for (i = 0; i < NR_CPU_FANS; ++i)
if (cpu_fans[i])
wf_control_set_max(cpu_fans[i]);
}
static int cpu_check_overtemp(s32 temp)
{
int new_state = 0;
s32 t_avg, t_old;
/* First check for immediate overtemps */
if (temp >= (cpu_all_tmax + LOW_OVER_IMMEDIATE)) {
new_state |= FAILURE_LOW_OVERTEMP;
if ((failure_state & FAILURE_LOW_OVERTEMP) == 0)
printk(KERN_ERR "windfarm: Overtemp due to immediate CPU"
" temperature !\n");
}
if (temp >= (cpu_all_tmax + HIGH_OVER_IMMEDIATE)) {
new_state |= FAILURE_HIGH_OVERTEMP;
if ((failure_state & FAILURE_HIGH_OVERTEMP) == 0)
printk(KERN_ERR "windfarm: Critical overtemp due to"
" immediate CPU temperature !\n");
}
/* We calculate a history of max temperatures and use that for the
* overtemp management
*/
t_old = cpu_thist[cpu_thist_pt];
cpu_thist[cpu_thist_pt] = temp;
cpu_thist_pt = (cpu_thist_pt + 1) % CPU_TEMP_HIST_SIZE;
cpu_thist_total -= t_old;
cpu_thist_total += temp;
t_avg = cpu_thist_total / CPU_TEMP_HIST_SIZE;
DBG_LOTS("t_avg = %d.%03d (out: %d.%03d, in: %d.%03d)\n",
FIX32TOPRINT(t_avg), FIX32TOPRINT(t_old), FIX32TOPRINT(temp));
/* Now check for average overtemps */
if (t_avg >= (cpu_all_tmax + LOW_OVER_AVERAGE)) {
new_state |= FAILURE_LOW_OVERTEMP;
if ((failure_state & FAILURE_LOW_OVERTEMP) == 0)
printk(KERN_ERR "windfarm: Overtemp due to average CPU"
" temperature !\n");
}
if (t_avg >= (cpu_all_tmax + HIGH_OVER_AVERAGE)) {
new_state |= FAILURE_HIGH_OVERTEMP;
if ((failure_state & FAILURE_HIGH_OVERTEMP) == 0)
printk(KERN_ERR "windfarm: Critical overtemp due to"
" average CPU temperature !\n");
}
/* Now handle overtemp conditions. We don't currently use the windfarm
* overtemp handling core as it's not fully suited to the needs of those
* new machine. This will be fixed later.
*/
if (new_state) {
/* High overtemp -> immediate shutdown */
if (new_state & FAILURE_HIGH_OVERTEMP)
machine_power_off();
if ((failure_state & new_state) != new_state)
cpu_max_all_fans();
failure_state |= new_state;
} else if ((failure_state & FAILURE_LOW_OVERTEMP) &&
(temp < (cpu_all_tmax + LOW_OVER_CLEAR))) {
printk(KERN_ERR "windfarm: Overtemp condition cleared !\n");
failure_state &= ~FAILURE_LOW_OVERTEMP;
}
return failure_state & (FAILURE_LOW_OVERTEMP | FAILURE_HIGH_OVERTEMP);
}
static void cpu_fans_tick(void)
{
int err, cpu;
s32 greatest_delta = 0;
s32 temp, power, t_max = 0;
int i, t, target = 0;
struct wf_sensor *sr;
struct wf_control *ct;
struct wf_cpu_pid_state *sp;
DBG_LOTS(KERN_DEBUG);
for (cpu = 0; cpu < nr_cores; ++cpu) {
/* Get CPU core temperature */
sr = sens_cpu_temp[cpu];
err = sr->ops->get_value(sr, &temp);
if (err) {
DBG("\n");
printk(KERN_WARNING "windfarm: CPU %d temperature "
"sensor error %d\n", cpu, err);
failure_state |= FAILURE_SENSOR;
cpu_max_all_fans();
return;
}
/* Keep track of highest temp */
t_max = max(t_max, temp);
/* Get CPU power */
sr = sens_cpu_power[cpu];
err = sr->ops->get_value(sr, &power);
if (err) {
DBG("\n");
printk(KERN_WARNING "windfarm: CPU %d power "
"sensor error %d\n", cpu, err);
failure_state |= FAILURE_SENSOR;
cpu_max_all_fans();
return;
}
/* Run PID */
sp = &cpu_pid[cpu];
t = wf_cpu_pid_run(sp, power, temp);
if (cpu == 0 || sp->last_delta > greatest_delta) {
greatest_delta = sp->last_delta;
target = t;
}
DBG_LOTS("[%d] P=%d.%.3d T=%d.%.3d ",
cpu, FIX32TOPRINT(power), FIX32TOPRINT(temp));
}
DBG_LOTS("fans = %d, t_max = %d.%03d\n", target, FIX32TOPRINT(t_max));
/* Darwin limits decrease to 20 per iteration */
if (target < (cpu_last_target - 20))
target = cpu_last_target - 20;
cpu_last_target = target;
for (cpu = 0; cpu < nr_cores; ++cpu)
cpu_pid[cpu].target = target;
/* Handle possible overtemps */
if (cpu_check_overtemp(t_max))
return;
/* Set fans */
for (i = 0; i < NR_CPU_FANS; ++i) {
ct = cpu_fans[i];
if (ct == NULL)
continue;
err = ct->ops->set_value(ct, target * cpu_fan_scale[i] / 100);
if (err) {
printk(KERN_WARNING "windfarm: fan %s reports "
"error %d\n", ct->name, err);
failure_state |= FAILURE_FAN;
break;
}
}
}
/* Backside/U4 fan */
static struct wf_pid_param backside_param = {
.interval = 5,
.history_len = 2,
.gd = 48 << 20,
.gp = 5 << 20,
.gr = 0,
.itarget = 64 << 16,
.additive = 1,
};
static void backside_fan_tick(void)
{
s32 temp;
int speed;
int err;
if (!backside_fan || !u4_temp)
return;
if (!backside_tick) {
/* first time; initialize things */
printk(KERN_INFO "windfarm: Backside control loop started.\n");
backside_param.min = backside_fan->ops->get_min(backside_fan);
backside_param.max = backside_fan->ops->get_max(backside_fan);
wf_pid_init(&backside_pid, &backside_param);
backside_tick = 1;
}
if (--backside_tick > 0)
return;
backside_tick = backside_pid.param.interval;
err = u4_temp->ops->get_value(u4_temp, &temp);
if (err) {
printk(KERN_WARNING "windfarm: U4 temp sensor error %d\n",
err);
failure_state |= FAILURE_SENSOR;
wf_control_set_max(backside_fan);
return;
}
speed = wf_pid_run(&backside_pid, temp);
DBG_LOTS("backside PID temp=%d.%.3d speed=%d\n",
FIX32TOPRINT(temp), speed);
err = backside_fan->ops->set_value(backside_fan, speed);
if (err) {
printk(KERN_WARNING "windfarm: backside fan error %d\n", err);
failure_state |= FAILURE_FAN;
}
}
/* Drive bay fan */
static struct wf_pid_param drive_bay_prm = {
.interval = 5,
.history_len = 2,
.gd = 30 << 20,
.gp = 5 << 20,
.gr = 0,
.itarget = 40 << 16,
.additive = 1,
};
static void drive_bay_fan_tick(void)
{
s32 temp;
int speed;
int err;
if (!drive_bay_fan || !hd_temp)
return;
if (!drive_bay_tick) {
/* first time; initialize things */
printk(KERN_INFO "windfarm: Drive bay control loop started.\n");
drive_bay_prm.min = drive_bay_fan->ops->get_min(drive_bay_fan);
drive_bay_prm.max = drive_bay_fan->ops->get_max(drive_bay_fan);
wf_pid_init(&drive_bay_pid, &drive_bay_prm);
drive_bay_tick = 1;
}
if (--drive_bay_tick > 0)
return;
drive_bay_tick = drive_bay_pid.param.interval;
err = hd_temp->ops->get_value(hd_temp, &temp);
if (err) {
printk(KERN_WARNING "windfarm: drive bay temp sensor "
"error %d\n", err);
failure_state |= FAILURE_SENSOR;
wf_control_set_max(drive_bay_fan);
return;
}
speed = wf_pid_run(&drive_bay_pid, temp);
DBG_LOTS("drive_bay PID temp=%d.%.3d speed=%d\n",
FIX32TOPRINT(temp), speed);
err = drive_bay_fan->ops->set_value(drive_bay_fan, speed);
if (err) {
printk(KERN_WARNING "windfarm: drive bay fan error %d\n", err);
failure_state |= FAILURE_FAN;
}
}
/* PCI slots area fan */
/* This makes the fan speed proportional to the power consumed */
static struct wf_pid_param slots_param = {
.interval = 1,
.history_len = 2,
.gd = 0,
.gp = 0,
.gr = 0x1277952,
.itarget = 0,
.min = 1560,
.max = 3510,
};
static void slots_fan_tick(void)
{
s32 power;
int speed;
int err;
if (!slots_fan || !slots_power)
return;
if (!slots_started) {
/* first time; initialize things */
printk(KERN_INFO "windfarm: Slots control loop started.\n");
wf_pid_init(&slots_pid, &slots_param);
slots_started = true;
}
err = slots_power->ops->get_value(slots_power, &power);
if (err) {
printk(KERN_WARNING "windfarm: slots power sensor error %d\n",
err);
failure_state |= FAILURE_SENSOR;
wf_control_set_max(slots_fan);
return;
}
speed = wf_pid_run(&slots_pid, power);
DBG_LOTS("slots PID power=%d.%.3d speed=%d\n",
FIX32TOPRINT(power), speed);
err = slots_fan->ops->set_value(slots_fan, speed);
if (err) {
printk(KERN_WARNING "windfarm: slots fan error %d\n", err);
failure_state |= FAILURE_FAN;
}
}
static void set_fail_state(void)
{
int i;
if (cpufreq_clamp)
wf_control_set_max(cpufreq_clamp);
for (i = 0; i < NR_CPU_FANS; ++i)
if (cpu_fans[i])
wf_control_set_max(cpu_fans[i]);
if (backside_fan)
wf_control_set_max(backside_fan);
if (slots_fan)
wf_control_set_max(slots_fan);
if (drive_bay_fan)
wf_control_set_max(drive_bay_fan);
}
static void pm112_tick(void)
{
int i, last_failure;
if (!started) {
started = true;
printk(KERN_INFO "windfarm: CPUs control loops started.\n");
for (i = 0; i < nr_cores; ++i) {
if (create_cpu_loop(i) < 0) {
failure_state = FAILURE_PERM;
set_fail_state();
break;
}
}
DBG_LOTS("cpu_all_tmax=%d.%03d\n", FIX32TOPRINT(cpu_all_tmax));
#ifdef HACKED_OVERTEMP
cpu_all_tmax = 60 << 16;
#endif
}
/* Permanent failure, bail out */
if (failure_state & FAILURE_PERM)
return;
/* Clear all failure bits except low overtemp which will be eventually
* cleared by the control loop itself
*/
last_failure = failure_state;
failure_state &= FAILURE_LOW_OVERTEMP;
cpu_fans_tick();
backside_fan_tick();
slots_fan_tick();
drive_bay_fan_tick();
DBG_LOTS("last_failure: 0x%x, failure_state: %x\n",
last_failure, failure_state);
/* Check for failures. Any failure causes cpufreq clamping */
if (failure_state && last_failure == 0 && cpufreq_clamp)
wf_control_set_max(cpufreq_clamp);
if (failure_state == 0 && last_failure && cpufreq_clamp)
wf_control_set_min(cpufreq_clamp);
/* That's it for now, we might want to deal with other failures
* differently in the future though
*/
}
static void pm112_new_control(struct wf_control *ct)
{
int i, max_exhaust;
if (cpufreq_clamp == NULL && !strcmp(ct->name, "cpufreq-clamp")) {
if (wf_get_control(ct) == 0)
cpufreq_clamp = ct;
}
for (i = 0; i < NR_CPU_FANS; ++i) {
if (!strcmp(ct->name, cpu_fan_names[i])) {
if (cpu_fans[i] == NULL && wf_get_control(ct) == 0)
cpu_fans[i] = ct;
break;
}
}
if (i >= NR_CPU_FANS) {
/* not a CPU fan, try the others */
if (!strcmp(ct->name, "backside-fan")) {
if (backside_fan == NULL && wf_get_control(ct) == 0)
backside_fan = ct;
} else if (!strcmp(ct->name, "slots-fan")) {
if (slots_fan == NULL && wf_get_control(ct) == 0)
slots_fan = ct;
} else if (!strcmp(ct->name, "drive-bay-fan")) {
if (drive_bay_fan == NULL && wf_get_control(ct) == 0)
drive_bay_fan = ct;
}
return;
}
for (i = 0; i < CPU_FANS_REQD; ++i)
if (cpu_fans[i] == NULL)
return;
/* work out pump scaling factors */
max_exhaust = cpu_fans[0]->ops->get_max(cpu_fans[0]);
for (i = FIRST_PUMP; i <= LAST_PUMP; ++i)
if ((ct = cpu_fans[i]) != NULL)
cpu_fan_scale[i] =
ct->ops->get_max(ct) * 100 / max_exhaust;
have_all_controls = 1;
}
static void pm112_new_sensor(struct wf_sensor *sr)
{
unsigned int i;
if (!strncmp(sr->name, "cpu-temp-", 9)) {
i = sr->name[9] - '0';
if (sr->name[10] == 0 && i < NR_CORES &&
sens_cpu_temp[i] == NULL && wf_get_sensor(sr) == 0)
sens_cpu_temp[i] = sr;
} else if (!strncmp(sr->name, "cpu-power-", 10)) {
i = sr->name[10] - '0';
if (sr->name[11] == 0 && i < NR_CORES &&
sens_cpu_power[i] == NULL && wf_get_sensor(sr) == 0)
sens_cpu_power[i] = sr;
} else if (!strcmp(sr->name, "hd-temp")) {
if (hd_temp == NULL && wf_get_sensor(sr) == 0)
hd_temp = sr;
} else if (!strcmp(sr->name, "slots-power")) {
if (slots_power == NULL && wf_get_sensor(sr) == 0)
slots_power = sr;
} else if (!strcmp(sr->name, "backside-temp")) {
if (u4_temp == NULL && wf_get_sensor(sr) == 0)
u4_temp = sr;
} else
return;
/* check if we have all the sensors we need */
for (i = 0; i < nr_cores; ++i)
if (sens_cpu_temp[i] == NULL || sens_cpu_power[i] == NULL)
return;
have_all_sensors = 1;
}
static int pm112_wf_notify(struct notifier_block *self,
unsigned long event, void *data)
{
switch (event) {
case WF_EVENT_NEW_SENSOR:
pm112_new_sensor(data);
break;
case WF_EVENT_NEW_CONTROL:
pm112_new_control(data);
break;
case WF_EVENT_TICK:
if (have_all_controls && have_all_sensors)
pm112_tick();
}
return 0;
}
static struct notifier_block pm112_events = {
.notifier_call = pm112_wf_notify,
};
static int wf_pm112_probe(struct platform_device *dev)
{
wf_register_client(&pm112_events);
return 0;
}
static void wf_pm112_remove(struct platform_device *dev)
{
wf_unregister_client(&pm112_events);
}
static struct platform_driver wf_pm112_driver = {
.probe = wf_pm112_probe,
.remove = wf_pm112_remove,
.driver = {
.name = "windfarm",
},
};
static int __init wf_pm112_init(void)
{
struct device_node *cpu;
if (!of_machine_is_compatible("PowerMac11,2"))
return -ENODEV;
/* Count the number of CPU cores */
nr_cores = 0;
for_each_node_by_type(cpu, "cpu")
++nr_cores;
printk(KERN_INFO "windfarm: initializing for dual-core desktop G5\n");
#ifdef MODULE
request_module("windfarm_smu_controls");
request_module("windfarm_smu_sensors");
request_module("windfarm_smu_sat");
request_module("windfarm_lm75_sensor");
request_module("windfarm_max6690_sensor");
request_module("windfarm_cpufreq_clamp");
#endif /* MODULE */
platform_driver_register(&wf_pm112_driver);
return 0;
}
static void __exit wf_pm112_exit(void)
{
platform_driver_unregister(&wf_pm112_driver);
}
module_init(wf_pm112_init);
module_exit(wf_pm112_exit);
MODULE_AUTHOR("Paul Mackerras <[email protected]>");
MODULE_DESCRIPTION("Thermal control for PowerMac11,2");
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:windfarm");
|
// SPDX-License-Identifier: GPL-2.0-only
/*
* Userfaultfd tests util functions
*
* Copyright (C) 2015-2023 Red Hat, Inc.
*/
#include "uffd-common.h"
#define BASE_PMD_ADDR ((void *)(1UL << 30))
volatile bool test_uffdio_copy_eexist = true;
unsigned long nr_cpus, nr_pages, nr_pages_per_cpu, page_size;
char *area_src, *area_src_alias, *area_dst, *area_dst_alias, *area_remap;
int uffd = -1, uffd_flags, finished, *pipefd, test_type;
bool map_shared;
bool test_uffdio_wp = true;
unsigned long long *count_verify;
uffd_test_ops_t *uffd_test_ops;
uffd_test_case_ops_t *uffd_test_case_ops;
atomic_bool ready_for_fork;
static int uffd_mem_fd_create(off_t mem_size, bool hugetlb)
{
unsigned int memfd_flags = 0;
int mem_fd;
if (hugetlb)
memfd_flags = MFD_HUGETLB;
mem_fd = memfd_create("uffd-test", memfd_flags);
if (mem_fd < 0)
err("memfd_create");
if (ftruncate(mem_fd, mem_size))
err("ftruncate");
if (fallocate(mem_fd,
FALLOC_FL_PUNCH_HOLE | FALLOC_FL_KEEP_SIZE, 0,
mem_size))
err("fallocate");
return mem_fd;
}
static void anon_release_pages(char *rel_area)
{
if (madvise(rel_area, nr_pages * page_size, MADV_DONTNEED))
err("madvise(MADV_DONTNEED) failed");
}
static int anon_allocate_area(void **alloc_area, bool is_src)
{
*alloc_area = mmap(NULL, nr_pages * page_size, PROT_READ | PROT_WRITE,
MAP_ANONYMOUS | MAP_PRIVATE, -1, 0);
if (*alloc_area == MAP_FAILED) {
*alloc_area = NULL;
return -errno;
}
return 0;
}
static void noop_alias_mapping(__u64 *start, size_t len, unsigned long offset)
{
}
static void hugetlb_release_pages(char *rel_area)
{
if (!map_shared) {
if (madvise(rel_area, nr_pages * page_size, MADV_DONTNEED))
err("madvise(MADV_DONTNEED) failed");
} else {
if (madvise(rel_area, nr_pages * page_size, MADV_REMOVE))
err("madvise(MADV_REMOVE) failed");
}
}
static int hugetlb_allocate_area(void **alloc_area, bool is_src)
{
off_t size = nr_pages * page_size;
off_t offset = is_src ? 0 : size;
void *area_alias = NULL;
char **alloc_area_alias;
int mem_fd = uffd_mem_fd_create(size * 2, true);
*alloc_area = mmap(NULL, size, PROT_READ | PROT_WRITE,
(map_shared ? MAP_SHARED : MAP_PRIVATE) |
(is_src ? 0 : MAP_NORESERVE),
mem_fd, offset);
if (*alloc_area == MAP_FAILED) {
*alloc_area = NULL;
return -errno;
}
if (map_shared) {
area_alias = mmap(NULL, size, PROT_READ | PROT_WRITE,
MAP_SHARED, mem_fd, offset);
if (area_alias == MAP_FAILED)
return -errno;
}
if (is_src) {
alloc_area_alias = &area_src_alias;
} else {
alloc_area_alias = &area_dst_alias;
}
if (area_alias)
*alloc_area_alias = area_alias;
close(mem_fd);
return 0;
}
static void hugetlb_alias_mapping(__u64 *start, size_t len, unsigned long offset)
{
if (!map_shared)
return;
*start = (unsigned long) area_dst_alias + offset;
}
static void shmem_release_pages(char *rel_area)
{
if (madvise(rel_area, nr_pages * page_size, MADV_REMOVE))
err("madvise(MADV_REMOVE) failed");
}
static int shmem_allocate_area(void **alloc_area, bool is_src)
{
void *area_alias = NULL;
size_t bytes = nr_pages * page_size, hpage_size = read_pmd_pagesize();
unsigned long offset = is_src ? 0 : bytes;
char *p = NULL, *p_alias = NULL;
int mem_fd = uffd_mem_fd_create(bytes * 2, false);
/* TODO: clean this up. Use a static addr is ugly */
p = BASE_PMD_ADDR;
if (!is_src)
/* src map + alias + interleaved hpages */
p += 2 * (bytes + hpage_size);
p_alias = p;
p_alias += bytes;
p_alias += hpage_size; /* Prevent src/dst VMA merge */
*alloc_area = mmap(p, bytes, PROT_READ | PROT_WRITE, MAP_SHARED,
mem_fd, offset);
if (*alloc_area == MAP_FAILED) {
*alloc_area = NULL;
return -errno;
}
if (*alloc_area != p)
err("mmap of memfd failed at %p", p);
area_alias = mmap(p_alias, bytes, PROT_READ | PROT_WRITE, MAP_SHARED,
mem_fd, offset);
if (area_alias == MAP_FAILED) {
munmap(*alloc_area, bytes);
*alloc_area = NULL;
return -errno;
}
if (area_alias != p_alias)
err("mmap of anonymous memory failed at %p", p_alias);
if (is_src)
area_src_alias = area_alias;
else
area_dst_alias = area_alias;
close(mem_fd);
return 0;
}
static void shmem_alias_mapping(__u64 *start, size_t len, unsigned long offset)
{
*start = (unsigned long)area_dst_alias + offset;
}
static void shmem_check_pmd_mapping(void *p, int expect_nr_hpages)
{
if (!check_huge_shmem(area_dst_alias, expect_nr_hpages,
read_pmd_pagesize()))
err("Did not find expected %d number of hugepages",
expect_nr_hpages);
}
struct uffd_test_ops anon_uffd_test_ops = {
.allocate_area = anon_allocate_area,
.release_pages = anon_release_pages,
.alias_mapping = noop_alias_mapping,
.check_pmd_mapping = NULL,
};
struct uffd_test_ops shmem_uffd_test_ops = {
.allocate_area = shmem_allocate_area,
.release_pages = shmem_release_pages,
.alias_mapping = shmem_alias_mapping,
.check_pmd_mapping = shmem_check_pmd_mapping,
};
struct uffd_test_ops hugetlb_uffd_test_ops = {
.allocate_area = hugetlb_allocate_area,
.release_pages = hugetlb_release_pages,
.alias_mapping = hugetlb_alias_mapping,
.check_pmd_mapping = NULL,
};
void uffd_stats_report(struct uffd_args *args, int n_cpus)
{
int i;
unsigned long long miss_total = 0, wp_total = 0, minor_total = 0;
for (i = 0; i < n_cpus; i++) {
miss_total += args[i].missing_faults;
wp_total += args[i].wp_faults;
minor_total += args[i].minor_faults;
}
printf("userfaults: ");
if (miss_total) {
printf("%llu missing (", miss_total);
for (i = 0; i < n_cpus; i++)
printf("%lu+", args[i].missing_faults);
printf("\b) ");
}
if (wp_total) {
printf("%llu wp (", wp_total);
for (i = 0; i < n_cpus; i++)
printf("%lu+", args[i].wp_faults);
printf("\b) ");
}
if (minor_total) {
printf("%llu minor (", minor_total);
for (i = 0; i < n_cpus; i++)
printf("%lu+", args[i].minor_faults);
printf("\b)");
}
printf("\n");
}
int userfaultfd_open(uint64_t *features)
{
struct uffdio_api uffdio_api;
uffd = uffd_open(UFFD_FLAGS);
if (uffd < 0)
return -1;
uffd_flags = fcntl(uffd, F_GETFD, NULL);
uffdio_api.api = UFFD_API;
uffdio_api.features = *features;
if (ioctl(uffd, UFFDIO_API, &uffdio_api))
/* Probably lack of CAP_PTRACE? */
return -1;
if (uffdio_api.api != UFFD_API)
err("UFFDIO_API error: %" PRIu64, (uint64_t)uffdio_api.api);
*features = uffdio_api.features;
return 0;
}
static inline void munmap_area(void **area)
{
if (*area)
if (munmap(*area, nr_pages * page_size))
err("munmap");
*area = NULL;
}
void uffd_test_ctx_clear(void)
{
size_t i;
if (pipefd) {
for (i = 0; i < nr_cpus * 2; ++i) {
if (close(pipefd[i]))
err("close pipefd");
}
free(pipefd);
pipefd = NULL;
}
if (count_verify) {
free(count_verify);
count_verify = NULL;
}
if (uffd != -1) {
if (close(uffd))
err("close uffd");
uffd = -1;
}
munmap_area((void **)&area_src);
munmap_area((void **)&area_src_alias);
munmap_area((void **)&area_dst);
munmap_area((void **)&area_dst_alias);
munmap_area((void **)&area_remap);
}
int uffd_test_ctx_init(uint64_t features, const char **errmsg)
{
unsigned long nr, cpu;
int ret;
if (uffd_test_case_ops && uffd_test_case_ops->pre_alloc) {
ret = uffd_test_case_ops->pre_alloc(errmsg);
if (ret)
return ret;
}
ret = uffd_test_ops->allocate_area((void **)&area_src, true);
ret |= uffd_test_ops->allocate_area((void **)&area_dst, false);
if (ret) {
if (errmsg)
*errmsg = "memory allocation failed";
return ret;
}
if (uffd_test_case_ops && uffd_test_case_ops->post_alloc) {
ret = uffd_test_case_ops->post_alloc(errmsg);
if (ret)
return ret;
}
ret = userfaultfd_open(&features);
if (ret) {
if (errmsg)
*errmsg = "possible lack of priviledge";
return ret;
}
count_verify = malloc(nr_pages * sizeof(unsigned long long));
if (!count_verify)
err("count_verify");
for (nr = 0; nr < nr_pages; nr++) {
*area_mutex(area_src, nr) =
(pthread_mutex_t)PTHREAD_MUTEX_INITIALIZER;
count_verify[nr] = *area_count(area_src, nr) = 1;
/*
* In the transition between 255 to 256, powerpc will
* read out of order in my_bcmp and see both bytes as
* zero, so leave a placeholder below always non-zero
* after the count, to avoid my_bcmp to trigger false
* positives.
*/
*(area_count(area_src, nr) + 1) = 1;
}
/*
* After initialization of area_src, we must explicitly release pages
* for area_dst to make sure it's fully empty. Otherwise we could have
* some area_dst pages be errornously initialized with zero pages,
* hence we could hit memory corruption later in the test.
*
* One example is when THP is globally enabled, above allocate_area()
* calls could have the two areas merged into a single VMA (as they
* will have the same VMA flags so they're mergeable). When we
* initialize the area_src above, it's possible that some part of
* area_dst could have been faulted in via one huge THP that will be
* shared between area_src and area_dst. It could cause some of the
* area_dst won't be trapped by missing userfaults.
*
* This release_pages() will guarantee even if that happened, we'll
* proactively split the thp and drop any accidentally initialized
* pages within area_dst.
*/
uffd_test_ops->release_pages(area_dst);
pipefd = malloc(sizeof(int) * nr_cpus * 2);
if (!pipefd)
err("pipefd");
for (cpu = 0; cpu < nr_cpus; cpu++)
if (pipe2(&pipefd[cpu * 2], O_CLOEXEC | O_NONBLOCK))
err("pipe");
return 0;
}
void wp_range(int ufd, __u64 start, __u64 len, bool wp)
{
struct uffdio_writeprotect prms;
/* Write protection page faults */
prms.range.start = start;
prms.range.len = len;
/* Undo write-protect, do wakeup after that */
prms.mode = wp ? UFFDIO_WRITEPROTECT_MODE_WP : 0;
if (ioctl(ufd, UFFDIO_WRITEPROTECT, &prms))
err("clear WP failed: address=0x%"PRIx64, (uint64_t)start);
}
static void continue_range(int ufd, __u64 start, __u64 len, bool wp)
{
struct uffdio_continue req;
int ret;
req.range.start = start;
req.range.len = len;
req.mode = 0;
if (wp)
req.mode |= UFFDIO_CONTINUE_MODE_WP;
if (ioctl(ufd, UFFDIO_CONTINUE, &req))
err("UFFDIO_CONTINUE failed for address 0x%" PRIx64,
(uint64_t)start);
/*
* Error handling within the kernel for continue is subtly different
* from copy or zeropage, so it may be a source of bugs. Trigger an
* error (-EEXIST) on purpose, to verify doing so doesn't cause a BUG.
*/
req.mapped = 0;
ret = ioctl(ufd, UFFDIO_CONTINUE, &req);
if (ret >= 0 || req.mapped != -EEXIST)
err("failed to exercise UFFDIO_CONTINUE error handling, ret=%d, mapped=%" PRId64,
ret, (int64_t) req.mapped);
}
int uffd_read_msg(int ufd, struct uffd_msg *msg)
{
int ret = read(uffd, msg, sizeof(*msg));
if (ret != sizeof(*msg)) {
if (ret < 0) {
if (errno == EAGAIN || errno == EINTR)
return 1;
err("blocking read error");
} else {
err("short read");
}
}
return 0;
}
void uffd_handle_page_fault(struct uffd_msg *msg, struct uffd_args *args)
{
unsigned long offset;
if (msg->event != UFFD_EVENT_PAGEFAULT)
err("unexpected msg event %u", msg->event);
if (msg->arg.pagefault.flags & UFFD_PAGEFAULT_FLAG_WP) {
/* Write protect page faults */
wp_range(uffd, msg->arg.pagefault.address, page_size, false);
args->wp_faults++;
} else if (msg->arg.pagefault.flags & UFFD_PAGEFAULT_FLAG_MINOR) {
uint8_t *area;
int b;
/*
* Minor page faults
*
* To prove we can modify the original range for testing
* purposes, we're going to bit flip this range before
* continuing.
*
* Note that this requires all minor page fault tests operate on
* area_dst (non-UFFD-registered) and area_dst_alias
* (UFFD-registered).
*/
area = (uint8_t *)(area_dst +
((char *)msg->arg.pagefault.address -
area_dst_alias));
for (b = 0; b < page_size; ++b)
area[b] = ~area[b];
continue_range(uffd, msg->arg.pagefault.address, page_size,
args->apply_wp);
args->minor_faults++;
} else {
/*
* Missing page faults.
*
* Here we force a write check for each of the missing mode
* faults. It's guaranteed because the only threads that
* will trigger uffd faults are the locking threads, and
* their first instruction to touch the missing page will
* always be pthread_mutex_lock().
*
* Note that here we relied on an NPTL glibc impl detail to
* always read the lock type at the entry of the lock op
* (pthread_mutex_t.__data.__type, offset 0x10) before
* doing any locking operations to guarantee that. It's
* actually not good to rely on this impl detail because
* logically a pthread-compatible lib can implement the
* locks without types and we can fail when linking with
* them. However since we used to find bugs with this
* strict check we still keep it around. Hopefully this
* could be a good hint when it fails again. If one day
* it'll break on some other impl of glibc we'll revisit.
*/
if (msg->arg.pagefault.flags & UFFD_PAGEFAULT_FLAG_WRITE)
err("unexpected write fault");
offset = (char *)(unsigned long)msg->arg.pagefault.address - area_dst;
offset &= ~(page_size-1);
if (copy_page(uffd, offset, args->apply_wp))
args->missing_faults++;
}
}
void *uffd_poll_thread(void *arg)
{
struct uffd_args *args = (struct uffd_args *)arg;
unsigned long cpu = args->cpu;
struct pollfd pollfd[2];
struct uffd_msg msg;
struct uffdio_register uffd_reg;
int ret;
char tmp_chr;
if (!args->handle_fault)
args->handle_fault = uffd_handle_page_fault;
pollfd[0].fd = uffd;
pollfd[0].events = POLLIN;
pollfd[1].fd = pipefd[cpu*2];
pollfd[1].events = POLLIN;
ready_for_fork = true;
for (;;) {
ret = poll(pollfd, 2, -1);
if (ret <= 0) {
if (errno == EINTR || errno == EAGAIN)
continue;
err("poll error: %d", ret);
}
if (pollfd[1].revents) {
if (!(pollfd[1].revents & POLLIN))
err("pollfd[1].revents %d", pollfd[1].revents);
if (read(pollfd[1].fd, &tmp_chr, 1) != 1)
err("read pipefd error");
break;
}
if (!(pollfd[0].revents & POLLIN))
err("pollfd[0].revents %d", pollfd[0].revents);
if (uffd_read_msg(uffd, &msg))
continue;
switch (msg.event) {
default:
err("unexpected msg event %u\n", msg.event);
break;
case UFFD_EVENT_PAGEFAULT:
args->handle_fault(&msg, args);
break;
case UFFD_EVENT_FORK:
close(uffd);
uffd = msg.arg.fork.ufd;
pollfd[0].fd = uffd;
break;
case UFFD_EVENT_REMOVE:
uffd_reg.range.start = msg.arg.remove.start;
uffd_reg.range.len = msg.arg.remove.end -
msg.arg.remove.start;
if (ioctl(uffd, UFFDIO_UNREGISTER, &uffd_reg.range))
err("remove failure");
break;
case UFFD_EVENT_REMAP:
area_remap = area_dst; /* save for later unmap */
area_dst = (char *)(unsigned long)msg.arg.remap.to;
break;
}
}
return NULL;
}
static void retry_copy_page(int ufd, struct uffdio_copy *uffdio_copy,
unsigned long offset)
{
uffd_test_ops->alias_mapping(&uffdio_copy->dst,
uffdio_copy->len,
offset);
if (ioctl(ufd, UFFDIO_COPY, uffdio_copy)) {
/* real retval in ufdio_copy.copy */
if (uffdio_copy->copy != -EEXIST)
err("UFFDIO_COPY retry error: %"PRId64,
(int64_t)uffdio_copy->copy);
} else {
err("UFFDIO_COPY retry unexpected: %"PRId64,
(int64_t)uffdio_copy->copy);
}
}
static void wake_range(int ufd, unsigned long addr, unsigned long len)
{
struct uffdio_range uffdio_wake;
uffdio_wake.start = addr;
uffdio_wake.len = len;
if (ioctl(ufd, UFFDIO_WAKE, &uffdio_wake))
fprintf(stderr, "error waking %lu\n",
addr), exit(1);
}
int __copy_page(int ufd, unsigned long offset, bool retry, bool wp)
{
struct uffdio_copy uffdio_copy;
if (offset >= nr_pages * page_size)
err("unexpected offset %lu\n", offset);
uffdio_copy.dst = (unsigned long) area_dst + offset;
uffdio_copy.src = (unsigned long) area_src + offset;
uffdio_copy.len = page_size;
if (wp)
uffdio_copy.mode = UFFDIO_COPY_MODE_WP;
else
uffdio_copy.mode = 0;
uffdio_copy.copy = 0;
if (ioctl(ufd, UFFDIO_COPY, &uffdio_copy)) {
/* real retval in ufdio_copy.copy */
if (uffdio_copy.copy != -EEXIST)
err("UFFDIO_COPY error: %"PRId64,
(int64_t)uffdio_copy.copy);
wake_range(ufd, uffdio_copy.dst, page_size);
} else if (uffdio_copy.copy != page_size) {
err("UFFDIO_COPY error: %"PRId64, (int64_t)uffdio_copy.copy);
} else {
if (test_uffdio_copy_eexist && retry) {
test_uffdio_copy_eexist = false;
retry_copy_page(ufd, &uffdio_copy, offset);
}
return 1;
}
return 0;
}
int copy_page(int ufd, unsigned long offset, bool wp)
{
return __copy_page(ufd, offset, false, wp);
}
int move_page(int ufd, unsigned long offset, unsigned long len)
{
struct uffdio_move uffdio_move;
if (offset + len > nr_pages * page_size)
err("unexpected offset %lu and length %lu\n", offset, len);
uffdio_move.dst = (unsigned long) area_dst + offset;
uffdio_move.src = (unsigned long) area_src + offset;
uffdio_move.len = len;
uffdio_move.mode = UFFDIO_MOVE_MODE_ALLOW_SRC_HOLES;
uffdio_move.move = 0;
if (ioctl(ufd, UFFDIO_MOVE, &uffdio_move)) {
/* real retval in uffdio_move.move */
if (uffdio_move.move != -EEXIST)
err("UFFDIO_MOVE error: %"PRId64,
(int64_t)uffdio_move.move);
wake_range(ufd, uffdio_move.dst, len);
} else if (uffdio_move.move != len) {
err("UFFDIO_MOVE error: %"PRId64, (int64_t)uffdio_move.move);
} else
return 1;
return 0;
}
int uffd_open_dev(unsigned int flags)
{
int fd, uffd;
fd = open("/dev/userfaultfd", O_RDWR | O_CLOEXEC);
if (fd < 0)
return fd;
uffd = ioctl(fd, USERFAULTFD_IOC_NEW, flags);
close(fd);
return uffd;
}
int uffd_open_sys(unsigned int flags)
{
return syscall(__NR_userfaultfd, flags);
}
int uffd_open(unsigned int flags)
{
int uffd = uffd_open_sys(flags);
if (uffd < 0)
uffd = uffd_open_dev(flags);
return uffd;
}
int uffd_get_features(uint64_t *features)
{
struct uffdio_api uffdio_api = { .api = UFFD_API, .features = 0 };
/*
* This should by default work in most kernels; the feature list
* will be the same no matter what we pass in here.
*/
int fd = uffd_open(UFFD_USER_MODE_ONLY);
if (fd < 0)
/* Maybe the kernel is older than user-only mode? */
fd = uffd_open(0);
if (fd < 0)
return fd;
if (ioctl(fd, UFFDIO_API, &uffdio_api)) {
close(fd);
return -errno;
}
*features = uffdio_api.features;
close(fd);
return 0;
}
|
/* SPDX-License-Identifier: GPL-2.0 */
/* Copyright (c) 2019, Vladimir Oltean <[email protected]>
*/
#ifndef _SJA1105_DYNAMIC_CONFIG_H
#define _SJA1105_DYNAMIC_CONFIG_H
#include "sja1105.h"
#include <linux/packing.h>
/* Special index that can be used for sja1105_dynamic_config_read */
#define SJA1105_SEARCH -1
struct sja1105_dyn_cmd;
struct sja1105_dynamic_table_ops {
/* This returns size_t just to keep same prototype as the
* static config ops, of which we are reusing some functions.
*/
size_t (*entry_packing)(void *buf, void *entry_ptr, enum packing_op op);
void (*cmd_packing)(void *buf, struct sja1105_dyn_cmd *cmd,
enum packing_op op);
size_t max_entry_count;
size_t packed_size;
u64 addr;
u8 access;
};
struct sja1105_mgmt_entry {
u64 tsreg;
u64 takets;
u64 macaddr;
u64 destports;
u64 enfport;
u64 index;
};
extern const struct sja1105_dynamic_table_ops sja1105et_dyn_ops[BLK_IDX_MAX_DYN];
extern const struct sja1105_dynamic_table_ops sja1105pqrs_dyn_ops[BLK_IDX_MAX_DYN];
extern const struct sja1105_dynamic_table_ops sja1110_dyn_ops[BLK_IDX_MAX_DYN];
#endif
|
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* (c) Copyright 2002-2010, Ralink Technology, Inc.
* Copyright (C) 2015 Jakub Kicinski <[email protected]>
* Copyright (C) 2018 Stanislaw Gruszka <[email protected]>
* Copyright (C) 2018 Lorenzo Bianconi <[email protected]>
*/
#ifndef __MT76X0U_INITVALS_INIT_H
#define __MT76X0U_INITVALS_INIT_H
#include "phy.h"
static const struct mt76_reg_pair common_mac_reg_table[] = {
{ MT_BCN_OFFSET(0), 0xf8f0e8e0 },
{ MT_BCN_OFFSET(1), 0x6f77d0c8 },
{ MT_LEGACY_BASIC_RATE, 0x0000013f },
{ MT_HT_BASIC_RATE, 0x00008003 },
{ MT_MAC_SYS_CTRL, 0x00000000 },
{ MT_RX_FILTR_CFG, 0x00017f97 },
{ MT_BKOFF_SLOT_CFG, 0x00000209 },
{ MT_TX_SW_CFG0, 0x00000000 },
{ MT_TX_SW_CFG1, 0x00080606 },
{ MT_TX_LINK_CFG, 0x00001020 },
{ MT_TX_TIMEOUT_CFG, 0x000a2090 },
{ MT_MAX_LEN_CFG, 0xa0fff | 0x00001000 },
{ MT_LED_CFG, 0x7f031e46 },
{ MT_PBF_TX_MAX_PCNT, 0x1fbf1f1f },
{ MT_PBF_RX_MAX_PCNT, 0x0000fe9f },
{ MT_TX_RETRY_CFG, 0x47d01f0f },
{ MT_AUTO_RSP_CFG, 0x00000013 },
{ MT_CCK_PROT_CFG, 0x07f40003 },
{ MT_OFDM_PROT_CFG, 0x07f42004 },
{ MT_PBF_CFG, 0x00f40006 },
{ MT_WPDMA_GLO_CFG, 0x00000030 },
{ MT_GF20_PROT_CFG, 0x01742004 },
{ MT_GF40_PROT_CFG, 0x03f42084 },
{ MT_MM20_PROT_CFG, 0x01742004 },
{ MT_MM40_PROT_CFG, 0x03f42084 },
{ MT_TXOP_CTRL_CFG, 0x0000583f },
{ MT_TX_RTS_CFG, 0x00ffff20 },
{ MT_EXP_ACK_TIME, 0x002400ca },
{ MT_TXOP_HLDR_ET, 0x00000002 },
{ MT_XIFS_TIME_CFG, 0x33a41010 },
{ MT_PWR_PIN_CFG, 0x00000000 },
};
static const struct mt76_reg_pair mt76x0_mac_reg_table[] = {
{ MT_IOCFG_6, 0xa0040080 },
{ MT_PBF_SYS_CTRL, 0x00080c00 },
{ MT_PBF_CFG, 0x77723c1f },
{ MT_FCE_PSE_CTRL, 0x00000001 },
{ MT_AMPDU_MAX_LEN_20M1S, 0xAAA99887 },
{ MT_TX_SW_CFG0, 0x00000601 },
{ MT_TX_SW_CFG1, 0x00040000 },
{ MT_TX_SW_CFG2, 0x00000000 },
{ 0xa44, 0x00000000 },
{ MT_HEADER_TRANS_CTRL_REG, 0x00000000 },
{ MT_TSO_CTRL, 0x00000000 },
{ MT_BB_PA_MODE_CFG1, 0x00500055 },
{ MT_RF_PA_MODE_CFG1, 0x00500055 },
{ MT_TX_ALC_CFG_0, 0x2F2F000C },
{ MT_TX0_BB_GAIN_ATTEN, 0x00000000 },
{ MT_TX_PWR_CFG_0, 0x3A3A3A3A },
{ MT_TX_PWR_CFG_1, 0x3A3A3A3A },
{ MT_TX_PWR_CFG_2, 0x3A3A3A3A },
{ MT_TX_PWR_CFG_3, 0x3A3A3A3A },
{ MT_TX_PWR_CFG_4, 0x3A3A3A3A },
{ MT_TX_PWR_CFG_7, 0x3A3A3A3A },
{ MT_TX_PWR_CFG_8, 0x0000003A },
{ MT_TX_PWR_CFG_9, 0x0000003A },
{ 0x150C, 0x00000002 },
{ 0x1238, 0x001700C8 },
{ MT_LDO_CTRL_0, 0x00A647B6 },
{ MT_LDO_CTRL_1, 0x6B006464 },
{ MT_HT_BASIC_RATE, 0x00004003 },
{ MT_HT_CTRL_CFG, 0x000001FF },
{ MT_TXOP_HLDR_ET, 0x00000000 },
{ MT_PN_PAD_MODE, 0x00000003 },
{ MT_TX_PROT_CFG6, 0xe3f42004 },
{ MT_TX_PROT_CFG7, 0xe3f42084 },
{ MT_TX_PROT_CFG8, 0xe3f42104 },
{ MT_VHT_HT_FBK_CFG1, 0xedcba980 },
};
static const struct mt76_reg_pair mt76x0_bbp_init_tab[] = {
{ MT_BBP(CORE, 1), 0x00000002 },
{ MT_BBP(CORE, 4), 0x00000000 },
{ MT_BBP(CORE, 24), 0x00000000 },
{ MT_BBP(CORE, 32), 0x4003000a },
{ MT_BBP(CORE, 42), 0x00000000 },
{ MT_BBP(CORE, 44), 0x00000000 },
{ MT_BBP(IBI, 11), 0x0FDE8081 },
{ MT_BBP(AGC, 0), 0x00021400 },
{ MT_BBP(AGC, 1), 0x00000003 },
{ MT_BBP(AGC, 2), 0x003A6464 },
{ MT_BBP(AGC, 15), 0x88A28CB8 },
{ MT_BBP(AGC, 22), 0x00001E21 },
{ MT_BBP(AGC, 23), 0x0000272C },
{ MT_BBP(AGC, 24), 0x00002F3A },
{ MT_BBP(AGC, 25), 0x8000005A },
{ MT_BBP(AGC, 26), 0x007C2005 },
{ MT_BBP(AGC, 33), 0x00003238 },
{ MT_BBP(AGC, 34), 0x000A0C0C },
{ MT_BBP(AGC, 37), 0x2121262C },
{ MT_BBP(AGC, 41), 0x38383E45 },
{ MT_BBP(AGC, 57), 0x00001010 },
{ MT_BBP(AGC, 59), 0xBAA20E96 },
{ MT_BBP(AGC, 63), 0x00000001 },
{ MT_BBP(TXC, 0), 0x00280403 },
{ MT_BBP(TXC, 1), 0x00000000 },
{ MT_BBP(RXC, 1), 0x00000012 },
{ MT_BBP(RXC, 2), 0x00000011 },
{ MT_BBP(RXC, 3), 0x00000005 },
{ MT_BBP(RXC, 4), 0x00000000 },
{ MT_BBP(RXC, 5), 0xF977C4EC },
{ MT_BBP(RXC, 7), 0x00000090 },
{ MT_BBP(TXO, 8), 0x00000000 },
{ MT_BBP(TXBE, 0), 0x00000000 },
{ MT_BBP(TXBE, 4), 0x00000004 },
{ MT_BBP(TXBE, 6), 0x00000000 },
{ MT_BBP(TXBE, 8), 0x00000014 },
{ MT_BBP(TXBE, 9), 0x20000000 },
{ MT_BBP(TXBE, 10), 0x00000000 },
{ MT_BBP(TXBE, 12), 0x00000000 },
{ MT_BBP(TXBE, 13), 0x00000000 },
{ MT_BBP(TXBE, 14), 0x00000000 },
{ MT_BBP(TXBE, 15), 0x00000000 },
{ MT_BBP(TXBE, 16), 0x00000000 },
{ MT_BBP(TXBE, 17), 0x00000000 },
{ MT_BBP(RXFE, 1), 0x00008800 },
{ MT_BBP(RXFE, 3), 0x00000000 },
{ MT_BBP(RXFE, 4), 0x00000000 },
{ MT_BBP(RXO, 13), 0x00000192 },
{ MT_BBP(RXO, 14), 0x00060612 },
{ MT_BBP(RXO, 15), 0xC8321B18 },
{ MT_BBP(RXO, 16), 0x0000001E },
{ MT_BBP(RXO, 17), 0x00000000 },
{ MT_BBP(RXO, 18), 0xCC00A993 },
{ MT_BBP(RXO, 19), 0xB9CB9CB9 },
{ MT_BBP(RXO, 20), 0x26c00057 },
{ MT_BBP(RXO, 21), 0x00000001 },
{ MT_BBP(RXO, 24), 0x00000006 },
{ MT_BBP(RXO, 28), 0x0000003F },
};
static const struct mt76_reg_pair mt76x0_dcoc_tab[] = {
{ MT_BBP(CAL, 47), 0x000010F0 },
{ MT_BBP(CAL, 48), 0x00008080 },
{ MT_BBP(CAL, 49), 0x00000F07 },
{ MT_BBP(CAL, 50), 0x00000040 },
{ MT_BBP(CAL, 51), 0x00000404 },
{ MT_BBP(CAL, 52), 0x00080803 },
{ MT_BBP(CAL, 53), 0x00000704 },
{ MT_BBP(CAL, 54), 0x00002828 },
{ MT_BBP(CAL, 55), 0x00005050 },
};
#endif
|
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Broadcom BCM63xx SPI controller support
*
* Copyright (C) 2009-2012 Florian Fainelli <[email protected]>
* Copyright (C) 2010 Tanguy Bouzeloc <[email protected]>
*/
#include <linux/kernel.h>
#include <linux/clk.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/delay.h>
#include <linux/interrupt.h>
#include <linux/spi/spi.h>
#include <linux/completion.h>
#include <linux/err.h>
#include <linux/pm_runtime.h>
#include <linux/of.h>
#include <linux/reset.h>
/* BCM 6338/6348 SPI core */
#define SPI_6348_RSET_SIZE 64
#define SPI_6348_CMD 0x00 /* 16-bits register */
#define SPI_6348_INT_STATUS 0x02
#define SPI_6348_INT_MASK_ST 0x03
#define SPI_6348_INT_MASK 0x04
#define SPI_6348_ST 0x05
#define SPI_6348_CLK_CFG 0x06
#define SPI_6348_FILL_BYTE 0x07
#define SPI_6348_MSG_TAIL 0x09
#define SPI_6348_RX_TAIL 0x0b
#define SPI_6348_MSG_CTL 0x40 /* 8-bits register */
#define SPI_6348_MSG_CTL_WIDTH 8
#define SPI_6348_MSG_DATA 0x41
#define SPI_6348_MSG_DATA_SIZE 0x3f
#define SPI_6348_RX_DATA 0x80
#define SPI_6348_RX_DATA_SIZE 0x3f
/* BCM 3368/6358/6262/6368 SPI core */
#define SPI_6358_RSET_SIZE 1804
#define SPI_6358_MSG_CTL 0x00 /* 16-bits register */
#define SPI_6358_MSG_CTL_WIDTH 16
#define SPI_6358_MSG_DATA 0x02
#define SPI_6358_MSG_DATA_SIZE 0x21e
#define SPI_6358_RX_DATA 0x400
#define SPI_6358_RX_DATA_SIZE 0x220
#define SPI_6358_CMD 0x700 /* 16-bits register */
#define SPI_6358_INT_STATUS 0x702
#define SPI_6358_INT_MASK_ST 0x703
#define SPI_6358_INT_MASK 0x704
#define SPI_6358_ST 0x705
#define SPI_6358_CLK_CFG 0x706
#define SPI_6358_FILL_BYTE 0x707
#define SPI_6358_MSG_TAIL 0x709
#define SPI_6358_RX_TAIL 0x70B
/* Shared SPI definitions */
/* Message configuration */
#define SPI_FD_RW 0x00
#define SPI_HD_W 0x01
#define SPI_HD_R 0x02
#define SPI_BYTE_CNT_SHIFT 0
#define SPI_6348_MSG_TYPE_SHIFT 6
#define SPI_6358_MSG_TYPE_SHIFT 14
/* Command */
#define SPI_CMD_NOOP 0x00
#define SPI_CMD_SOFT_RESET 0x01
#define SPI_CMD_HARD_RESET 0x02
#define SPI_CMD_START_IMMEDIATE 0x03
#define SPI_CMD_COMMAND_SHIFT 0
#define SPI_CMD_COMMAND_MASK 0x000f
#define SPI_CMD_DEVICE_ID_SHIFT 4
#define SPI_CMD_PREPEND_BYTE_CNT_SHIFT 8
#define SPI_CMD_ONE_BYTE_SHIFT 11
#define SPI_CMD_ONE_WIRE_SHIFT 12
#define SPI_DEV_ID_0 0
#define SPI_DEV_ID_1 1
#define SPI_DEV_ID_2 2
#define SPI_DEV_ID_3 3
/* Interrupt mask */
#define SPI_INTR_CMD_DONE 0x01
#define SPI_INTR_RX_OVERFLOW 0x02
#define SPI_INTR_TX_UNDERFLOW 0x04
#define SPI_INTR_TX_OVERFLOW 0x08
#define SPI_INTR_RX_UNDERFLOW 0x10
#define SPI_INTR_CLEAR_ALL 0x1f
/* Status */
#define SPI_RX_EMPTY 0x02
#define SPI_CMD_BUSY 0x04
#define SPI_SERIAL_BUSY 0x08
/* Clock configuration */
#define SPI_CLK_20MHZ 0x00
#define SPI_CLK_0_391MHZ 0x01
#define SPI_CLK_0_781MHZ 0x02 /* default */
#define SPI_CLK_1_563MHZ 0x03
#define SPI_CLK_3_125MHZ 0x04
#define SPI_CLK_6_250MHZ 0x05
#define SPI_CLK_12_50MHZ 0x06
#define SPI_CLK_MASK 0x07
#define SPI_SSOFFTIME_MASK 0x38
#define SPI_SSOFFTIME_SHIFT 3
#define SPI_BYTE_SWAP 0x80
enum bcm63xx_regs_spi {
SPI_CMD,
SPI_INT_STATUS,
SPI_INT_MASK_ST,
SPI_INT_MASK,
SPI_ST,
SPI_CLK_CFG,
SPI_FILL_BYTE,
SPI_MSG_TAIL,
SPI_RX_TAIL,
SPI_MSG_CTL,
SPI_MSG_DATA,
SPI_RX_DATA,
SPI_MSG_TYPE_SHIFT,
SPI_MSG_CTL_WIDTH,
SPI_MSG_DATA_SIZE,
};
#define BCM63XX_SPI_MAX_PREPEND 7
#define BCM63XX_SPI_MAX_CS 8
#define BCM63XX_SPI_BUS_NUM 0
struct bcm63xx_spi {
struct completion done;
void __iomem *regs;
int irq;
/* Platform data */
const unsigned long *reg_offsets;
unsigned int fifo_size;
unsigned int msg_type_shift;
unsigned int msg_ctl_width;
/* data iomem */
u8 __iomem *tx_io;
const u8 __iomem *rx_io;
struct clk *clk;
struct platform_device *pdev;
};
static inline u8 bcm_spi_readb(struct bcm63xx_spi *bs,
unsigned int offset)
{
return readb(bs->regs + bs->reg_offsets[offset]);
}
static inline void bcm_spi_writeb(struct bcm63xx_spi *bs,
u8 value, unsigned int offset)
{
writeb(value, bs->regs + bs->reg_offsets[offset]);
}
static inline void bcm_spi_writew(struct bcm63xx_spi *bs,
u16 value, unsigned int offset)
{
#ifdef CONFIG_CPU_BIG_ENDIAN
iowrite16be(value, bs->regs + bs->reg_offsets[offset]);
#else
writew(value, bs->regs + bs->reg_offsets[offset]);
#endif
}
static const unsigned int bcm63xx_spi_freq_table[SPI_CLK_MASK][2] = {
{ 20000000, SPI_CLK_20MHZ },
{ 12500000, SPI_CLK_12_50MHZ },
{ 6250000, SPI_CLK_6_250MHZ },
{ 3125000, SPI_CLK_3_125MHZ },
{ 1563000, SPI_CLK_1_563MHZ },
{ 781000, SPI_CLK_0_781MHZ },
{ 391000, SPI_CLK_0_391MHZ }
};
static void bcm63xx_spi_setup_transfer(struct spi_device *spi,
struct spi_transfer *t)
{
struct bcm63xx_spi *bs = spi_controller_get_devdata(spi->controller);
u8 clk_cfg, reg;
int i;
/* Default to lowest clock configuration */
clk_cfg = SPI_CLK_0_391MHZ;
/* Find the closest clock configuration */
for (i = 0; i < SPI_CLK_MASK; i++) {
if (t->speed_hz >= bcm63xx_spi_freq_table[i][0]) {
clk_cfg = bcm63xx_spi_freq_table[i][1];
break;
}
}
/* clear existing clock configuration bits of the register */
reg = bcm_spi_readb(bs, SPI_CLK_CFG);
reg &= ~SPI_CLK_MASK;
reg |= clk_cfg;
bcm_spi_writeb(bs, reg, SPI_CLK_CFG);
dev_dbg(&spi->dev, "Setting clock register to %02x (hz %d)\n",
clk_cfg, t->speed_hz);
}
/* the spi->mode bits understood by this driver: */
#define MODEBITS (SPI_CPOL | SPI_CPHA)
static int bcm63xx_txrx_bufs(struct spi_device *spi, struct spi_transfer *first,
unsigned int num_transfers)
{
struct bcm63xx_spi *bs = spi_controller_get_devdata(spi->controller);
u16 msg_ctl;
u16 cmd;
unsigned int i, timeout = 0, prepend_len = 0, len = 0;
struct spi_transfer *t = first;
bool do_rx = false;
bool do_tx = false;
/* Disable the CMD_DONE interrupt */
bcm_spi_writeb(bs, 0, SPI_INT_MASK);
dev_dbg(&spi->dev, "txrx: tx %p, rx %p, len %d\n",
t->tx_buf, t->rx_buf, t->len);
if (num_transfers > 1 && t->tx_buf && t->len <= BCM63XX_SPI_MAX_PREPEND)
prepend_len = t->len;
/* prepare the buffer */
for (i = 0; i < num_transfers; i++) {
if (t->tx_buf) {
do_tx = true;
memcpy_toio(bs->tx_io + len, t->tx_buf, t->len);
/* don't prepend more than one tx */
if (t != first)
prepend_len = 0;
}
if (t->rx_buf) {
do_rx = true;
/* prepend is half-duplex write only */
if (t == first)
prepend_len = 0;
}
len += t->len;
t = list_entry(t->transfer_list.next, struct spi_transfer,
transfer_list);
}
reinit_completion(&bs->done);
/* Fill in the Message control register */
msg_ctl = (len << SPI_BYTE_CNT_SHIFT);
if (do_rx && do_tx && prepend_len == 0)
msg_ctl |= (SPI_FD_RW << bs->msg_type_shift);
else if (do_rx)
msg_ctl |= (SPI_HD_R << bs->msg_type_shift);
else if (do_tx)
msg_ctl |= (SPI_HD_W << bs->msg_type_shift);
switch (bs->msg_ctl_width) {
case 8:
bcm_spi_writeb(bs, msg_ctl, SPI_MSG_CTL);
break;
case 16:
bcm_spi_writew(bs, msg_ctl, SPI_MSG_CTL);
break;
}
/* Issue the transfer */
cmd = SPI_CMD_START_IMMEDIATE;
cmd |= (prepend_len << SPI_CMD_PREPEND_BYTE_CNT_SHIFT);
cmd |= (spi_get_chipselect(spi, 0) << SPI_CMD_DEVICE_ID_SHIFT);
bcm_spi_writew(bs, cmd, SPI_CMD);
/* Enable the CMD_DONE interrupt */
bcm_spi_writeb(bs, SPI_INTR_CMD_DONE, SPI_INT_MASK);
timeout = wait_for_completion_timeout(&bs->done, HZ);
if (!timeout)
return -ETIMEDOUT;
if (!do_rx)
return 0;
len = 0;
t = first;
/* Read out all the data */
for (i = 0; i < num_transfers; i++) {
if (t->rx_buf)
memcpy_fromio(t->rx_buf, bs->rx_io + len, t->len);
if (t != first || prepend_len == 0)
len += t->len;
t = list_entry(t->transfer_list.next, struct spi_transfer,
transfer_list);
}
return 0;
}
static int bcm63xx_spi_transfer_one(struct spi_controller *host,
struct spi_message *m)
{
struct bcm63xx_spi *bs = spi_controller_get_devdata(host);
struct spi_transfer *t, *first = NULL;
struct spi_device *spi = m->spi;
int status = 0;
unsigned int n_transfers = 0, total_len = 0;
bool can_use_prepend = false;
/*
* This SPI controller does not support keeping CS active after a
* transfer.
* Work around this by merging as many transfers we can into one big
* full-duplex transfers.
*/
list_for_each_entry(t, &m->transfers, transfer_list) {
if (!first)
first = t;
n_transfers++;
total_len += t->len;
if (n_transfers == 2 && !first->rx_buf && !t->tx_buf &&
first->len <= BCM63XX_SPI_MAX_PREPEND)
can_use_prepend = true;
else if (can_use_prepend && t->tx_buf)
can_use_prepend = false;
/* we can only transfer one fifo worth of data */
if ((can_use_prepend &&
total_len > (bs->fifo_size + BCM63XX_SPI_MAX_PREPEND)) ||
(!can_use_prepend && total_len > bs->fifo_size)) {
dev_err(&spi->dev, "unable to do transfers larger than FIFO size (%i > %i)\n",
total_len, bs->fifo_size);
status = -EINVAL;
goto exit;
}
/* all combined transfers have to have the same speed */
if (t->speed_hz != first->speed_hz) {
dev_err(&spi->dev, "unable to change speed between transfers\n");
status = -EINVAL;
goto exit;
}
/* CS will be deasserted directly after transfer */
if (t->delay.value) {
dev_err(&spi->dev, "unable to keep CS asserted after transfer\n");
status = -EINVAL;
goto exit;
}
if (t->cs_change ||
list_is_last(&t->transfer_list, &m->transfers)) {
/* configure adapter for a new transfer */
bcm63xx_spi_setup_transfer(spi, first);
/* send the data */
status = bcm63xx_txrx_bufs(spi, first, n_transfers);
if (status)
goto exit;
m->actual_length += total_len;
first = NULL;
n_transfers = 0;
total_len = 0;
can_use_prepend = false;
}
}
exit:
m->status = status;
spi_finalize_current_message(host);
return 0;
}
/* This driver supports single host mode only. Hence
* CMD_DONE is the only interrupt we care about
*/
static irqreturn_t bcm63xx_spi_interrupt(int irq, void *dev_id)
{
struct spi_controller *host = (struct spi_controller *)dev_id;
struct bcm63xx_spi *bs = spi_controller_get_devdata(host);
u8 intr;
/* Read interupts and clear them immediately */
intr = bcm_spi_readb(bs, SPI_INT_STATUS);
bcm_spi_writeb(bs, SPI_INTR_CLEAR_ALL, SPI_INT_STATUS);
bcm_spi_writeb(bs, 0, SPI_INT_MASK);
/* A transfer completed */
if (intr & SPI_INTR_CMD_DONE)
complete(&bs->done);
return IRQ_HANDLED;
}
static size_t bcm63xx_spi_max_length(struct spi_device *spi)
{
struct bcm63xx_spi *bs = spi_controller_get_devdata(spi->controller);
return bs->fifo_size;
}
static const unsigned long bcm6348_spi_reg_offsets[] = {
[SPI_CMD] = SPI_6348_CMD,
[SPI_INT_STATUS] = SPI_6348_INT_STATUS,
[SPI_INT_MASK_ST] = SPI_6348_INT_MASK_ST,
[SPI_INT_MASK] = SPI_6348_INT_MASK,
[SPI_ST] = SPI_6348_ST,
[SPI_CLK_CFG] = SPI_6348_CLK_CFG,
[SPI_FILL_BYTE] = SPI_6348_FILL_BYTE,
[SPI_MSG_TAIL] = SPI_6348_MSG_TAIL,
[SPI_RX_TAIL] = SPI_6348_RX_TAIL,
[SPI_MSG_CTL] = SPI_6348_MSG_CTL,
[SPI_MSG_DATA] = SPI_6348_MSG_DATA,
[SPI_RX_DATA] = SPI_6348_RX_DATA,
[SPI_MSG_TYPE_SHIFT] = SPI_6348_MSG_TYPE_SHIFT,
[SPI_MSG_CTL_WIDTH] = SPI_6348_MSG_CTL_WIDTH,
[SPI_MSG_DATA_SIZE] = SPI_6348_MSG_DATA_SIZE,
};
static const unsigned long bcm6358_spi_reg_offsets[] = {
[SPI_CMD] = SPI_6358_CMD,
[SPI_INT_STATUS] = SPI_6358_INT_STATUS,
[SPI_INT_MASK_ST] = SPI_6358_INT_MASK_ST,
[SPI_INT_MASK] = SPI_6358_INT_MASK,
[SPI_ST] = SPI_6358_ST,
[SPI_CLK_CFG] = SPI_6358_CLK_CFG,
[SPI_FILL_BYTE] = SPI_6358_FILL_BYTE,
[SPI_MSG_TAIL] = SPI_6358_MSG_TAIL,
[SPI_RX_TAIL] = SPI_6358_RX_TAIL,
[SPI_MSG_CTL] = SPI_6358_MSG_CTL,
[SPI_MSG_DATA] = SPI_6358_MSG_DATA,
[SPI_RX_DATA] = SPI_6358_RX_DATA,
[SPI_MSG_TYPE_SHIFT] = SPI_6358_MSG_TYPE_SHIFT,
[SPI_MSG_CTL_WIDTH] = SPI_6358_MSG_CTL_WIDTH,
[SPI_MSG_DATA_SIZE] = SPI_6358_MSG_DATA_SIZE,
};
static const struct platform_device_id bcm63xx_spi_dev_match[] = {
{
.name = "bcm6348-spi",
.driver_data = (unsigned long)bcm6348_spi_reg_offsets,
},
{
.name = "bcm6358-spi",
.driver_data = (unsigned long)bcm6358_spi_reg_offsets,
},
{
},
};
MODULE_DEVICE_TABLE(platform, bcm63xx_spi_dev_match);
static const struct of_device_id bcm63xx_spi_of_match[] = {
{ .compatible = "brcm,bcm6348-spi", .data = &bcm6348_spi_reg_offsets },
{ .compatible = "brcm,bcm6358-spi", .data = &bcm6358_spi_reg_offsets },
{ },
};
MODULE_DEVICE_TABLE(of, bcm63xx_spi_of_match);
static int bcm63xx_spi_probe(struct platform_device *pdev)
{
struct resource *r;
const unsigned long *bcm63xx_spireg;
struct device *dev = &pdev->dev;
int irq, bus_num;
struct spi_controller *host;
struct clk *clk;
struct bcm63xx_spi *bs;
int ret;
u32 num_cs = BCM63XX_SPI_MAX_CS;
struct reset_control *reset;
if (dev->of_node) {
const struct of_device_id *match;
match = of_match_node(bcm63xx_spi_of_match, dev->of_node);
if (!match)
return -EINVAL;
bcm63xx_spireg = match->data;
of_property_read_u32(dev->of_node, "num-cs", &num_cs);
if (num_cs > BCM63XX_SPI_MAX_CS) {
dev_warn(dev, "unsupported number of cs (%i), reducing to 8\n",
num_cs);
num_cs = BCM63XX_SPI_MAX_CS;
}
bus_num = -1;
} else if (pdev->id_entry->driver_data) {
const struct platform_device_id *match = pdev->id_entry;
bcm63xx_spireg = (const unsigned long *)match->driver_data;
bus_num = BCM63XX_SPI_BUS_NUM;
} else {
return -EINVAL;
}
irq = platform_get_irq(pdev, 0);
if (irq < 0)
return irq;
clk = devm_clk_get(dev, "spi");
if (IS_ERR(clk)) {
dev_err(dev, "no clock for device\n");
return PTR_ERR(clk);
}
reset = devm_reset_control_get_optional_exclusive(dev, NULL);
if (IS_ERR(reset))
return PTR_ERR(reset);
host = spi_alloc_host(dev, sizeof(*bs));
if (!host) {
dev_err(dev, "out of memory\n");
return -ENOMEM;
}
bs = spi_controller_get_devdata(host);
init_completion(&bs->done);
platform_set_drvdata(pdev, host);
bs->pdev = pdev;
bs->regs = devm_platform_get_and_ioremap_resource(pdev, 0, &r);
if (IS_ERR(bs->regs)) {
ret = PTR_ERR(bs->regs);
goto out_err;
}
bs->irq = irq;
bs->clk = clk;
bs->reg_offsets = bcm63xx_spireg;
bs->fifo_size = bs->reg_offsets[SPI_MSG_DATA_SIZE];
ret = devm_request_irq(&pdev->dev, irq, bcm63xx_spi_interrupt, 0,
pdev->name, host);
if (ret) {
dev_err(dev, "unable to request irq\n");
goto out_err;
}
host->dev.of_node = dev->of_node;
host->bus_num = bus_num;
host->num_chipselect = num_cs;
host->transfer_one_message = bcm63xx_spi_transfer_one;
host->mode_bits = MODEBITS;
host->bits_per_word_mask = SPI_BPW_MASK(8);
host->max_transfer_size = bcm63xx_spi_max_length;
host->max_message_size = bcm63xx_spi_max_length;
host->auto_runtime_pm = true;
bs->msg_type_shift = bs->reg_offsets[SPI_MSG_TYPE_SHIFT];
bs->msg_ctl_width = bs->reg_offsets[SPI_MSG_CTL_WIDTH];
bs->tx_io = (u8 *)(bs->regs + bs->reg_offsets[SPI_MSG_DATA]);
bs->rx_io = (const u8 *)(bs->regs + bs->reg_offsets[SPI_RX_DATA]);
/* Initialize hardware */
ret = clk_prepare_enable(bs->clk);
if (ret)
goto out_err;
ret = reset_control_reset(reset);
if (ret) {
dev_err(dev, "unable to reset device: %d\n", ret);
goto out_clk_disable;
}
bcm_spi_writeb(bs, SPI_INTR_CLEAR_ALL, SPI_INT_STATUS);
ret = devm_pm_runtime_enable(&pdev->dev);
if (ret)
goto out_clk_disable;
/* register and we are done */
ret = devm_spi_register_controller(dev, host);
if (ret) {
dev_err(dev, "spi register failed\n");
goto out_clk_disable;
}
dev_info(dev, "at %pr (irq %d, FIFOs size %d)\n",
r, irq, bs->fifo_size);
return 0;
out_clk_disable:
clk_disable_unprepare(clk);
out_err:
spi_controller_put(host);
return ret;
}
static void bcm63xx_spi_remove(struct platform_device *pdev)
{
struct spi_controller *host = platform_get_drvdata(pdev);
struct bcm63xx_spi *bs = spi_controller_get_devdata(host);
/* reset spi block */
bcm_spi_writeb(bs, 0, SPI_INT_MASK);
/* HW shutdown */
clk_disable_unprepare(bs->clk);
}
static int bcm63xx_spi_suspend(struct device *dev)
{
struct spi_controller *host = dev_get_drvdata(dev);
struct bcm63xx_spi *bs = spi_controller_get_devdata(host);
spi_controller_suspend(host);
clk_disable_unprepare(bs->clk);
return 0;
}
static int bcm63xx_spi_resume(struct device *dev)
{
struct spi_controller *host = dev_get_drvdata(dev);
struct bcm63xx_spi *bs = spi_controller_get_devdata(host);
int ret;
ret = clk_prepare_enable(bs->clk);
if (ret)
return ret;
spi_controller_resume(host);
return 0;
}
static DEFINE_SIMPLE_DEV_PM_OPS(bcm63xx_spi_pm_ops, bcm63xx_spi_suspend, bcm63xx_spi_resume);
static struct platform_driver bcm63xx_spi_driver = {
.driver = {
.name = "bcm63xx-spi",
.pm = &bcm63xx_spi_pm_ops,
.of_match_table = bcm63xx_spi_of_match,
},
.id_table = bcm63xx_spi_dev_match,
.probe = bcm63xx_spi_probe,
.remove = bcm63xx_spi_remove,
};
module_platform_driver(bcm63xx_spi_driver);
MODULE_ALIAS("platform:bcm63xx_spi");
MODULE_AUTHOR("Florian Fainelli <[email protected]>");
MODULE_AUTHOR("Tanguy Bouzeloc <[email protected]>");
MODULE_DESCRIPTION("Broadcom BCM63xx SPI Controller driver");
MODULE_LICENSE("GPL");
|
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (C) 2020 BAIKAL ELECTRONICS, JSC
*
* Baikal-T1 CCU Dividers interface driver
*/
#ifndef __CLK_BT1_CCU_DIV_H__
#define __CLK_BT1_CCU_DIV_H__
#include <linux/clk-provider.h>
#include <linux/spinlock.h>
#include <linux/regmap.h>
#include <linux/bits.h>
#include <linux/of.h>
/*
* CCU Divider private clock IDs
* @CCU_SYS_SATA_CLK: CCU SATA internal clock
* @CCU_SYS_XGMAC_CLK: CCU XGMAC internal clock
*/
#define CCU_SYS_SATA_CLK -1
#define CCU_SYS_XGMAC_CLK -2
/*
* CCU Divider private flags
* @CCU_DIV_BASIC: Basic divider clock required by the kernel as early as
* possible.
* @CCU_DIV_SKIP_ONE: Due to some reason divider can't be set to 1.
* It can be 0 though, which is functionally the same.
* @CCU_DIV_SKIP_ONE_TO_THREE: For some reason divider can't be within [1,3].
* It can be either 0 or greater than 3.
* @CCU_DIV_LOCK_SHIFTED: Find lock-bit at non-standard position.
* @CCU_DIV_RESET_DOMAIN: There is a clock domain reset handle.
*/
#define CCU_DIV_BASIC BIT(0)
#define CCU_DIV_SKIP_ONE BIT(1)
#define CCU_DIV_SKIP_ONE_TO_THREE BIT(2)
#define CCU_DIV_LOCK_SHIFTED BIT(3)
#define CCU_DIV_RESET_DOMAIN BIT(4)
/*
* enum ccu_div_type - CCU Divider types
* @CCU_DIV_VAR: Clocks gate with variable divider.
* @CCU_DIV_GATE: Clocks gate with fixed divider.
* @CCU_DIV_BUF: Clock gate with no divider.
* @CCU_DIV_FIXED: Ungateable clock with fixed divider.
*/
enum ccu_div_type {
CCU_DIV_VAR,
CCU_DIV_GATE,
CCU_DIV_BUF,
CCU_DIV_FIXED
};
/*
* struct ccu_div_init_data - CCU Divider initialization data
* @id: Clocks private identifier.
* @name: Clocks name.
* @parent_name: Parent clocks name in a fw node.
* @base: Divider register base address with respect to the sys_regs base.
* @sys_regs: Baikal-T1 System Controller registers map.
* @np: Pointer to the node describing the CCU Dividers.
* @type: CCU divider type (variable, fixed with and without gate).
* @width: Divider width if it's variable.
* @divider: Divider fixed value.
* @flags: CCU Divider clock flags.
* @features: CCU Divider private features.
*/
struct ccu_div_init_data {
unsigned int id;
const char *name;
const char *parent_name;
unsigned int base;
struct regmap *sys_regs;
struct device_node *np;
enum ccu_div_type type;
union {
unsigned int width;
unsigned int divider;
};
unsigned long flags;
unsigned long features;
};
/*
* struct ccu_div - CCU Divider descriptor
* @hw: clk_hw of the divider.
* @id: Clock private identifier.
* @reg_ctl: Divider control register base address.
* @sys_regs: Baikal-T1 System Controller registers map.
* @lock: Divider state change spin-lock.
* @mask: Divider field mask.
* @divider: Divider fixed value.
* @flags: Divider clock flags.
* @features: CCU Divider private features.
*/
struct ccu_div {
struct clk_hw hw;
unsigned int id;
unsigned int reg_ctl;
struct regmap *sys_regs;
spinlock_t lock;
union {
u32 mask;
unsigned int divider;
};
unsigned long flags;
unsigned long features;
};
#define to_ccu_div(_hw) container_of(_hw, struct ccu_div, hw)
static inline struct clk_hw *ccu_div_get_clk_hw(struct ccu_div *div)
{
return div ? &div->hw : NULL;
}
struct ccu_div *ccu_div_hw_register(const struct ccu_div_init_data *init);
void ccu_div_hw_unregister(struct ccu_div *div);
#endif /* __CLK_BT1_CCU_DIV_H__ */
|
// SPDX-License-Identifier: GPL-2.0-only
/*
* wm8523.c -- WM8523 ALSA SoC Audio driver
*
* Copyright 2009 Wolfson Microelectronics plc
*
* Author: Mark Brown <[email protected]>
*/
#include <linux/mod_devicetable.h>
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/pm.h>
#include <linux/i2c.h>
#include <linux/regmap.h>
#include <linux/regulator/consumer.h>
#include <linux/slab.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/initval.h>
#include <sound/tlv.h>
#include "wm8523.h"
#define WM8523_NUM_SUPPLIES 2
static const char *wm8523_supply_names[WM8523_NUM_SUPPLIES] = {
"AVDD",
"LINEVDD",
};
#define WM8523_NUM_RATES 7
/* codec private data */
struct wm8523_priv {
struct regmap *regmap;
struct regulator_bulk_data supplies[WM8523_NUM_SUPPLIES];
unsigned int sysclk;
unsigned int rate_constraint_list[WM8523_NUM_RATES];
struct snd_pcm_hw_constraint_list rate_constraint;
};
static const struct reg_default wm8523_reg_defaults[] = {
{ 2, 0x0000 }, /* R2 - PSCTRL1 */
{ 3, 0x1812 }, /* R3 - AIF_CTRL1 */
{ 4, 0x0000 }, /* R4 - AIF_CTRL2 */
{ 5, 0x0001 }, /* R5 - DAC_CTRL3 */
{ 6, 0x0190 }, /* R6 - DAC_GAINL */
{ 7, 0x0190 }, /* R7 - DAC_GAINR */
{ 8, 0x0000 }, /* R8 - ZERO_DETECT */
};
static bool wm8523_volatile_register(struct device *dev, unsigned int reg)
{
switch (reg) {
case WM8523_DEVICE_ID:
case WM8523_REVISION:
return true;
default:
return false;
}
}
static const DECLARE_TLV_DB_SCALE(dac_tlv, -10000, 25, 0);
static const char *wm8523_zd_count_text[] = {
"1024",
"2048",
};
static SOC_ENUM_SINGLE_DECL(wm8523_zc_count, WM8523_ZERO_DETECT, 0,
wm8523_zd_count_text);
static const struct snd_kcontrol_new wm8523_controls[] = {
SOC_DOUBLE_R_TLV("Playback Volume", WM8523_DAC_GAINL, WM8523_DAC_GAINR,
0, 448, 0, dac_tlv),
SOC_SINGLE("ZC Switch", WM8523_DAC_CTRL3, 4, 1, 0),
SOC_SINGLE("Playback Deemphasis Switch", WM8523_AIF_CTRL1, 8, 1, 0),
SOC_DOUBLE("Playback Switch", WM8523_DAC_CTRL3, 2, 3, 1, 1),
SOC_SINGLE("Volume Ramp Up Switch", WM8523_DAC_CTRL3, 1, 1, 0),
SOC_SINGLE("Volume Ramp Down Switch", WM8523_DAC_CTRL3, 0, 1, 0),
SOC_ENUM("Zero Detect Count", wm8523_zc_count),
};
static const struct snd_soc_dapm_widget wm8523_dapm_widgets[] = {
SND_SOC_DAPM_DAC("DAC", "Playback", SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_OUTPUT("LINEVOUTL"),
SND_SOC_DAPM_OUTPUT("LINEVOUTR"),
};
static const struct snd_soc_dapm_route wm8523_dapm_routes[] = {
{ "LINEVOUTL", NULL, "DAC" },
{ "LINEVOUTR", NULL, "DAC" },
};
static const struct {
int value;
int ratio;
} lrclk_ratios[WM8523_NUM_RATES] = {
{ 1, 128 },
{ 2, 192 },
{ 3, 256 },
{ 4, 384 },
{ 5, 512 },
{ 6, 768 },
{ 7, 1152 },
};
static const struct {
int value;
int ratio;
} bclk_ratios[] = {
{ 2, 32 },
{ 3, 64 },
{ 4, 128 },
};
static int wm8523_startup(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
struct wm8523_priv *wm8523 = snd_soc_component_get_drvdata(component);
/* The set of sample rates that can be supported depends on the
* MCLK supplied to the CODEC - enforce this.
*/
if (!wm8523->sysclk) {
dev_err(component->dev,
"No MCLK configured, call set_sysclk() on init\n");
return -EINVAL;
}
snd_pcm_hw_constraint_list(substream->runtime, 0,
SNDRV_PCM_HW_PARAM_RATE,
&wm8523->rate_constraint);
return 0;
}
static int wm8523_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
struct wm8523_priv *wm8523 = snd_soc_component_get_drvdata(component);
int i;
u16 aifctrl1 = snd_soc_component_read(component, WM8523_AIF_CTRL1);
u16 aifctrl2 = snd_soc_component_read(component, WM8523_AIF_CTRL2);
/* Find a supported LRCLK ratio */
for (i = 0; i < ARRAY_SIZE(lrclk_ratios); i++) {
if (wm8523->sysclk / params_rate(params) ==
lrclk_ratios[i].ratio)
break;
}
/* Should never happen, should be handled by constraints */
if (i == ARRAY_SIZE(lrclk_ratios)) {
dev_err(component->dev, "MCLK/fs ratio %d unsupported\n",
wm8523->sysclk / params_rate(params));
return -EINVAL;
}
aifctrl2 &= ~WM8523_SR_MASK;
aifctrl2 |= lrclk_ratios[i].value;
if (aifctrl1 & WM8523_AIF_MSTR) {
/* Find a fs->bclk ratio */
for (i = 0; i < ARRAY_SIZE(bclk_ratios); i++)
if (params_width(params) * 2 <= bclk_ratios[i].ratio)
break;
if (i == ARRAY_SIZE(bclk_ratios)) {
dev_err(component->dev,
"No matching BCLK/fs ratio for word length %d\n",
params_width(params));
return -EINVAL;
}
aifctrl2 &= ~WM8523_BCLKDIV_MASK;
aifctrl2 |= bclk_ratios[i].value << WM8523_BCLKDIV_SHIFT;
}
aifctrl1 &= ~WM8523_WL_MASK;
switch (params_width(params)) {
case 16:
break;
case 20:
aifctrl1 |= 0x8;
break;
case 24:
aifctrl1 |= 0x10;
break;
case 32:
aifctrl1 |= 0x18;
break;
}
snd_soc_component_write(component, WM8523_AIF_CTRL1, aifctrl1);
snd_soc_component_write(component, WM8523_AIF_CTRL2, aifctrl2);
return 0;
}
static int wm8523_set_dai_sysclk(struct snd_soc_dai *codec_dai,
int clk_id, unsigned int freq, int dir)
{
struct snd_soc_component *component = codec_dai->component;
struct wm8523_priv *wm8523 = snd_soc_component_get_drvdata(component);
unsigned int val;
int i;
wm8523->sysclk = freq;
wm8523->rate_constraint.count = 0;
for (i = 0; i < ARRAY_SIZE(lrclk_ratios); i++) {
val = freq / lrclk_ratios[i].ratio;
/* Check that it's a standard rate since core can't
* cope with others and having the odd rates confuses
* constraint matching.
*/
switch (val) {
case 8000:
case 11025:
case 16000:
case 22050:
case 32000:
case 44100:
case 48000:
case 64000:
case 88200:
case 96000:
case 176400:
case 192000:
dev_dbg(component->dev, "Supported sample rate: %dHz\n",
val);
wm8523->rate_constraint_list[i] = val;
wm8523->rate_constraint.count++;
break;
default:
dev_dbg(component->dev, "Skipping sample rate: %dHz\n",
val);
}
}
/* Need at least one supported rate... */
if (wm8523->rate_constraint.count == 0)
return -EINVAL;
return 0;
}
static int wm8523_set_dai_fmt(struct snd_soc_dai *codec_dai,
unsigned int fmt)
{
struct snd_soc_component *component = codec_dai->component;
u16 aifctrl1 = snd_soc_component_read(component, WM8523_AIF_CTRL1);
aifctrl1 &= ~(WM8523_BCLK_INV_MASK | WM8523_LRCLK_INV_MASK |
WM8523_FMT_MASK | WM8523_AIF_MSTR_MASK);
switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
case SND_SOC_DAIFMT_CBM_CFM:
aifctrl1 |= WM8523_AIF_MSTR;
break;
case SND_SOC_DAIFMT_CBS_CFS:
break;
default:
return -EINVAL;
}
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_I2S:
aifctrl1 |= 0x0002;
break;
case SND_SOC_DAIFMT_RIGHT_J:
break;
case SND_SOC_DAIFMT_LEFT_J:
aifctrl1 |= 0x0001;
break;
case SND_SOC_DAIFMT_DSP_A:
aifctrl1 |= 0x0003;
break;
case SND_SOC_DAIFMT_DSP_B:
aifctrl1 |= 0x0023;
break;
default:
return -EINVAL;
}
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
case SND_SOC_DAIFMT_NB_NF:
break;
case SND_SOC_DAIFMT_IB_IF:
aifctrl1 |= WM8523_BCLK_INV | WM8523_LRCLK_INV;
break;
case SND_SOC_DAIFMT_IB_NF:
aifctrl1 |= WM8523_BCLK_INV;
break;
case SND_SOC_DAIFMT_NB_IF:
aifctrl1 |= WM8523_LRCLK_INV;
break;
default:
return -EINVAL;
}
snd_soc_component_write(component, WM8523_AIF_CTRL1, aifctrl1);
return 0;
}
static int wm8523_set_bias_level(struct snd_soc_component *component,
enum snd_soc_bias_level level)
{
struct wm8523_priv *wm8523 = snd_soc_component_get_drvdata(component);
int ret;
switch (level) {
case SND_SOC_BIAS_ON:
break;
case SND_SOC_BIAS_PREPARE:
/* Full power on */
snd_soc_component_update_bits(component, WM8523_PSCTRL1,
WM8523_SYS_ENA_MASK, 3);
break;
case SND_SOC_BIAS_STANDBY:
if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) {
ret = regulator_bulk_enable(ARRAY_SIZE(wm8523->supplies),
wm8523->supplies);
if (ret != 0) {
dev_err(component->dev,
"Failed to enable supplies: %d\n",
ret);
return ret;
}
/* Sync back default/cached values */
regcache_sync(wm8523->regmap);
/* Initial power up */
snd_soc_component_update_bits(component, WM8523_PSCTRL1,
WM8523_SYS_ENA_MASK, 1);
msleep(100);
}
/* Power up to mute */
snd_soc_component_update_bits(component, WM8523_PSCTRL1,
WM8523_SYS_ENA_MASK, 2);
break;
case SND_SOC_BIAS_OFF:
/* The chip runs through the power down sequence for us. */
snd_soc_component_update_bits(component, WM8523_PSCTRL1,
WM8523_SYS_ENA_MASK, 0);
msleep(100);
regulator_bulk_disable(ARRAY_SIZE(wm8523->supplies),
wm8523->supplies);
break;
}
return 0;
}
#define WM8523_RATES SNDRV_PCM_RATE_8000_192000
#define WM8523_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
static const struct snd_soc_dai_ops wm8523_dai_ops = {
.startup = wm8523_startup,
.hw_params = wm8523_hw_params,
.set_sysclk = wm8523_set_dai_sysclk,
.set_fmt = wm8523_set_dai_fmt,
};
static struct snd_soc_dai_driver wm8523_dai = {
.name = "wm8523-hifi",
.playback = {
.stream_name = "Playback",
.channels_min = 2, /* Mono modes not yet supported */
.channels_max = 2,
.rates = WM8523_RATES,
.formats = WM8523_FORMATS,
},
.ops = &wm8523_dai_ops,
};
static int wm8523_probe(struct snd_soc_component *component)
{
struct wm8523_priv *wm8523 = snd_soc_component_get_drvdata(component);
wm8523->rate_constraint.list = &wm8523->rate_constraint_list[0];
wm8523->rate_constraint.count =
ARRAY_SIZE(wm8523->rate_constraint_list);
/* Change some default settings - latch VU and enable ZC */
snd_soc_component_update_bits(component, WM8523_DAC_GAINR,
WM8523_DACR_VU, WM8523_DACR_VU);
snd_soc_component_update_bits(component, WM8523_DAC_CTRL3, WM8523_ZC, WM8523_ZC);
return 0;
}
static const struct snd_soc_component_driver soc_component_dev_wm8523 = {
.probe = wm8523_probe,
.set_bias_level = wm8523_set_bias_level,
.controls = wm8523_controls,
.num_controls = ARRAY_SIZE(wm8523_controls),
.dapm_widgets = wm8523_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(wm8523_dapm_widgets),
.dapm_routes = wm8523_dapm_routes,
.num_dapm_routes = ARRAY_SIZE(wm8523_dapm_routes),
.suspend_bias_off = 1,
.idle_bias_on = 1,
.use_pmdown_time = 1,
.endianness = 1,
};
static const struct of_device_id wm8523_of_match[] = {
{ .compatible = "wlf,wm8523" },
{ },
};
MODULE_DEVICE_TABLE(of, wm8523_of_match);
static const struct regmap_config wm8523_regmap = {
.reg_bits = 8,
.val_bits = 16,
.max_register = WM8523_ZERO_DETECT,
.reg_defaults = wm8523_reg_defaults,
.num_reg_defaults = ARRAY_SIZE(wm8523_reg_defaults),
.cache_type = REGCACHE_MAPLE,
.volatile_reg = wm8523_volatile_register,
};
static int wm8523_i2c_probe(struct i2c_client *i2c)
{
struct wm8523_priv *wm8523;
unsigned int val;
int ret, i;
wm8523 = devm_kzalloc(&i2c->dev, sizeof(struct wm8523_priv),
GFP_KERNEL);
if (wm8523 == NULL)
return -ENOMEM;
wm8523->regmap = devm_regmap_init_i2c(i2c, &wm8523_regmap);
if (IS_ERR(wm8523->regmap)) {
ret = PTR_ERR(wm8523->regmap);
dev_err(&i2c->dev, "Failed to create regmap: %d\n", ret);
return ret;
}
for (i = 0; i < ARRAY_SIZE(wm8523->supplies); i++)
wm8523->supplies[i].supply = wm8523_supply_names[i];
ret = devm_regulator_bulk_get(&i2c->dev, ARRAY_SIZE(wm8523->supplies),
wm8523->supplies);
if (ret != 0) {
dev_err(&i2c->dev, "Failed to request supplies: %d\n", ret);
return ret;
}
ret = regulator_bulk_enable(ARRAY_SIZE(wm8523->supplies),
wm8523->supplies);
if (ret != 0) {
dev_err(&i2c->dev, "Failed to enable supplies: %d\n", ret);
return ret;
}
ret = regmap_read(wm8523->regmap, WM8523_DEVICE_ID, &val);
if (ret < 0) {
dev_err(&i2c->dev, "Failed to read ID register\n");
goto err_enable;
}
if (val != 0x8523) {
dev_err(&i2c->dev, "Device is not a WM8523, ID is %x\n", ret);
ret = -EINVAL;
goto err_enable;
}
ret = regmap_read(wm8523->regmap, WM8523_REVISION, &val);
if (ret < 0) {
dev_err(&i2c->dev, "Failed to read revision register\n");
goto err_enable;
}
dev_info(&i2c->dev, "revision %c\n",
(val & WM8523_CHIP_REV_MASK) + 'A');
ret = regmap_write(wm8523->regmap, WM8523_DEVICE_ID, 0x8523);
if (ret != 0) {
dev_err(&i2c->dev, "Failed to reset device: %d\n", ret);
goto err_enable;
}
regulator_bulk_disable(ARRAY_SIZE(wm8523->supplies), wm8523->supplies);
i2c_set_clientdata(i2c, wm8523);
ret = devm_snd_soc_register_component(&i2c->dev,
&soc_component_dev_wm8523, &wm8523_dai, 1);
return ret;
err_enable:
regulator_bulk_disable(ARRAY_SIZE(wm8523->supplies), wm8523->supplies);
return ret;
}
static const struct i2c_device_id wm8523_i2c_id[] = {
{ "wm8523" },
{ }
};
MODULE_DEVICE_TABLE(i2c, wm8523_i2c_id);
static struct i2c_driver wm8523_i2c_driver = {
.driver = {
.name = "wm8523",
.of_match_table = wm8523_of_match,
},
.probe = wm8523_i2c_probe,
.id_table = wm8523_i2c_id,
};
module_i2c_driver(wm8523_i2c_driver);
MODULE_DESCRIPTION("ASoC WM8523 driver");
MODULE_AUTHOR("Mark Brown <[email protected]>");
MODULE_LICENSE("GPL");
|
/* SPDX-License-Identifier: GPL-2.0-only */
/****************************************************************************
* Driver for Solarflare network controllers and boards
* Copyright 2019 Solarflare Communications Inc.
* Copyright 2020-2022 Xilinx Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 as published
* by the Free Software Foundation, incorporated herein by reference.
*/
/* Handling for ef100 representor netdevs */
#ifndef EF100_REP_H
#define EF100_REP_H
#include "net_driver.h"
#include "tc.h"
struct efx_rep_sw_stats {
atomic64_t rx_packets, tx_packets;
atomic64_t rx_bytes, tx_bytes;
atomic64_t rx_dropped, tx_errors;
};
struct devlink_port;
/**
* struct efx_rep - Private data for an Efx representor
*
* @parent: the efx PF which manages this representor
* @net_dev: representor netdevice
* @msg_enable: log message enable flags
* @mport: m-port ID of corresponding VF
* @idx: VF index
* @write_index: number of packets enqueued to @rx_list
* @read_index: number of packets consumed from @rx_list
* @rx_pring_size: max length of RX list
* @dflt: default-rule for MAE switching
* @list: entry on efx->vf_reps
* @rx_list: list of SKBs queued for receive in NAPI poll
* @rx_lock: protects @rx_list
* @napi: NAPI control structure
* @stats: software traffic counters for netdev stats
* @dl_port: devlink port associated to this netdev representor
*/
struct efx_rep {
struct efx_nic *parent;
struct net_device *net_dev;
u32 msg_enable;
u32 mport;
unsigned int idx;
unsigned int write_index, read_index;
unsigned int rx_pring_size;
struct efx_tc_flow_rule dflt;
struct list_head list;
struct list_head rx_list;
spinlock_t rx_lock;
struct napi_struct napi;
struct efx_rep_sw_stats stats;
struct devlink_port *dl_port;
};
int efx_ef100_vfrep_create(struct efx_nic *efx, unsigned int i);
void efx_ef100_vfrep_destroy(struct efx_nic *efx, struct efx_rep *efv);
void efx_ef100_fini_vfreps(struct efx_nic *efx);
void efx_ef100_rep_rx_packet(struct efx_rep *efv, struct efx_rx_buffer *rx_buf);
/* Returns the representor corresponding to a VF m-port, or NULL
* @mport is an m-port label, *not* an m-port ID!
* Caller must hold rcu_read_lock().
*/
struct efx_rep *efx_ef100_find_rep_by_mport(struct efx_nic *efx, u16 mport);
extern const struct net_device_ops efx_ef100_rep_netdev_ops;
void efx_ef100_init_reps(struct efx_nic *efx);
void efx_ef100_fini_reps(struct efx_nic *efx);
struct mae_mport_desc;
bool ef100_mport_on_local_intf(struct efx_nic *efx,
struct mae_mport_desc *mport_desc);
bool ef100_mport_is_vf(struct mae_mport_desc *mport_desc);
#endif /* EF100_REP_H */
|
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2021 Google LLC
* Author: Fuad Tabba <[email protected]>
*/
#include <linux/kvm_host.h>
#include <linux/mm.h>
#include <asm/kvm_emulate.h>
#include <nvhe/fixed_config.h>
#include <nvhe/mem_protect.h>
#include <nvhe/memory.h>
#include <nvhe/pkvm.h>
#include <nvhe/trap_handler.h>
/* Used by icache_is_aliasing(). */
unsigned long __icache_flags;
/* Used by kvm_get_vttbr(). */
unsigned int kvm_arm_vmid_bits;
unsigned int kvm_host_sve_max_vl;
/*
* Set trap register values based on features in ID_AA64PFR0.
*/
static void pvm_init_traps_aa64pfr0(struct kvm_vcpu *vcpu)
{
const u64 feature_ids = pvm_read_id_reg(vcpu, SYS_ID_AA64PFR0_EL1);
u64 hcr_set = HCR_RW;
u64 hcr_clear = 0;
u64 cptr_set = 0;
u64 cptr_clear = 0;
/* Protected KVM does not support AArch32 guests. */
BUILD_BUG_ON(FIELD_GET(ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_EL0),
PVM_ID_AA64PFR0_RESTRICT_UNSIGNED) != ID_AA64PFR0_EL1_EL0_IMP);
BUILD_BUG_ON(FIELD_GET(ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_EL1),
PVM_ID_AA64PFR0_RESTRICT_UNSIGNED) != ID_AA64PFR0_EL1_EL1_IMP);
/*
* Linux guests assume support for floating-point and Advanced SIMD. Do
* not change the trapping behavior for these from the KVM default.
*/
BUILD_BUG_ON(!FIELD_GET(ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_FP),
PVM_ID_AA64PFR0_ALLOW));
BUILD_BUG_ON(!FIELD_GET(ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_AdvSIMD),
PVM_ID_AA64PFR0_ALLOW));
if (has_hvhe())
hcr_set |= HCR_E2H;
/* Trap RAS unless all current versions are supported */
if (FIELD_GET(ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_RAS), feature_ids) <
ID_AA64PFR0_EL1_RAS_V1P1) {
hcr_set |= HCR_TERR | HCR_TEA;
hcr_clear |= HCR_FIEN;
}
/* Trap AMU */
if (!FIELD_GET(ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_AMU), feature_ids)) {
hcr_clear |= HCR_AMVOFFEN;
cptr_set |= CPTR_EL2_TAM;
}
/* Trap SVE */
if (!FIELD_GET(ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_SVE), feature_ids)) {
if (has_hvhe())
cptr_clear |= CPACR_ELx_ZEN;
else
cptr_set |= CPTR_EL2_TZ;
}
vcpu->arch.hcr_el2 |= hcr_set;
vcpu->arch.hcr_el2 &= ~hcr_clear;
vcpu->arch.cptr_el2 |= cptr_set;
vcpu->arch.cptr_el2 &= ~cptr_clear;
}
/*
* Set trap register values based on features in ID_AA64PFR1.
*/
static void pvm_init_traps_aa64pfr1(struct kvm_vcpu *vcpu)
{
const u64 feature_ids = pvm_read_id_reg(vcpu, SYS_ID_AA64PFR1_EL1);
u64 hcr_set = 0;
u64 hcr_clear = 0;
/* Memory Tagging: Trap and Treat as Untagged if not supported. */
if (!FIELD_GET(ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_MTE), feature_ids)) {
hcr_set |= HCR_TID5;
hcr_clear |= HCR_DCT | HCR_ATA;
}
vcpu->arch.hcr_el2 |= hcr_set;
vcpu->arch.hcr_el2 &= ~hcr_clear;
}
/*
* Set trap register values based on features in ID_AA64DFR0.
*/
static void pvm_init_traps_aa64dfr0(struct kvm_vcpu *vcpu)
{
const u64 feature_ids = pvm_read_id_reg(vcpu, SYS_ID_AA64DFR0_EL1);
u64 mdcr_set = 0;
u64 mdcr_clear = 0;
u64 cptr_set = 0;
/* Trap/constrain PMU */
if (!FIELD_GET(ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_PMUVer), feature_ids)) {
mdcr_set |= MDCR_EL2_TPM | MDCR_EL2_TPMCR;
mdcr_clear |= MDCR_EL2_HPME | MDCR_EL2_MTPME |
MDCR_EL2_HPMN_MASK;
}
/* Trap Debug */
if (!FIELD_GET(ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_DebugVer), feature_ids))
mdcr_set |= MDCR_EL2_TDRA | MDCR_EL2_TDA | MDCR_EL2_TDE;
/* Trap OS Double Lock */
if (!FIELD_GET(ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_DoubleLock), feature_ids))
mdcr_set |= MDCR_EL2_TDOSA;
/* Trap SPE */
if (!FIELD_GET(ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_PMSVer), feature_ids)) {
mdcr_set |= MDCR_EL2_TPMS;
mdcr_clear |= MDCR_EL2_E2PB_MASK << MDCR_EL2_E2PB_SHIFT;
}
/* Trap Trace Filter */
if (!FIELD_GET(ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_TraceFilt), feature_ids))
mdcr_set |= MDCR_EL2_TTRF;
/* Trap Trace */
if (!FIELD_GET(ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_TraceVer), feature_ids)) {
if (has_hvhe())
cptr_set |= CPACR_EL1_TTA;
else
cptr_set |= CPTR_EL2_TTA;
}
/* Trap External Trace */
if (!FIELD_GET(ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_ExtTrcBuff), feature_ids))
mdcr_clear |= MDCR_EL2_E2TB_MASK << MDCR_EL2_E2TB_SHIFT;
vcpu->arch.mdcr_el2 |= mdcr_set;
vcpu->arch.mdcr_el2 &= ~mdcr_clear;
vcpu->arch.cptr_el2 |= cptr_set;
}
/*
* Set trap register values based on features in ID_AA64MMFR0.
*/
static void pvm_init_traps_aa64mmfr0(struct kvm_vcpu *vcpu)
{
const u64 feature_ids = pvm_read_id_reg(vcpu, SYS_ID_AA64MMFR0_EL1);
u64 mdcr_set = 0;
/* Trap Debug Communications Channel registers */
if (!FIELD_GET(ARM64_FEATURE_MASK(ID_AA64MMFR0_EL1_FGT), feature_ids))
mdcr_set |= MDCR_EL2_TDCC;
vcpu->arch.mdcr_el2 |= mdcr_set;
}
/*
* Set trap register values based on features in ID_AA64MMFR1.
*/
static void pvm_init_traps_aa64mmfr1(struct kvm_vcpu *vcpu)
{
const u64 feature_ids = pvm_read_id_reg(vcpu, SYS_ID_AA64MMFR1_EL1);
u64 hcr_set = 0;
/* Trap LOR */
if (!FIELD_GET(ARM64_FEATURE_MASK(ID_AA64MMFR1_EL1_LO), feature_ids))
hcr_set |= HCR_TLOR;
vcpu->arch.hcr_el2 |= hcr_set;
}
/*
* Set baseline trap register values.
*/
static void pvm_init_trap_regs(struct kvm_vcpu *vcpu)
{
const u64 hcr_trap_feat_regs = HCR_TID3;
const u64 hcr_trap_impdef = HCR_TACR | HCR_TIDCP | HCR_TID1;
/*
* Always trap:
* - Feature id registers: to control features exposed to guests
* - Implementation-defined features
*/
vcpu->arch.hcr_el2 |= hcr_trap_feat_regs | hcr_trap_impdef;
/* Clear res0 and set res1 bits to trap potential new features. */
vcpu->arch.hcr_el2 &= ~(HCR_RES0);
vcpu->arch.mdcr_el2 &= ~(MDCR_EL2_RES0);
if (!has_hvhe()) {
vcpu->arch.cptr_el2 |= CPTR_NVHE_EL2_RES1;
vcpu->arch.cptr_el2 &= ~(CPTR_NVHE_EL2_RES0);
}
}
static void pkvm_vcpu_reset_hcr(struct kvm_vcpu *vcpu)
{
vcpu->arch.hcr_el2 = HCR_GUEST_FLAGS;
if (has_hvhe())
vcpu->arch.hcr_el2 |= HCR_E2H;
if (cpus_have_final_cap(ARM64_HAS_RAS_EXTN)) {
/* route synchronous external abort exceptions to EL2 */
vcpu->arch.hcr_el2 |= HCR_TEA;
/* trap error record accesses */
vcpu->arch.hcr_el2 |= HCR_TERR;
}
if (cpus_have_final_cap(ARM64_HAS_STAGE2_FWB))
vcpu->arch.hcr_el2 |= HCR_FWB;
if (cpus_have_final_cap(ARM64_HAS_EVT) &&
!cpus_have_final_cap(ARM64_MISMATCHED_CACHE_TYPE))
vcpu->arch.hcr_el2 |= HCR_TID4;
else
vcpu->arch.hcr_el2 |= HCR_TID2;
if (vcpu_has_ptrauth(vcpu))
vcpu->arch.hcr_el2 |= (HCR_API | HCR_APK);
}
/*
* Initialize trap register values in protected mode.
*/
static void pkvm_vcpu_init_traps(struct kvm_vcpu *vcpu)
{
vcpu->arch.cptr_el2 = kvm_get_reset_cptr_el2(vcpu);
vcpu->arch.mdcr_el2 = 0;
pkvm_vcpu_reset_hcr(vcpu);
if ((!vcpu_is_protected(vcpu)))
return;
pvm_init_trap_regs(vcpu);
pvm_init_traps_aa64pfr0(vcpu);
pvm_init_traps_aa64pfr1(vcpu);
pvm_init_traps_aa64dfr0(vcpu);
pvm_init_traps_aa64mmfr0(vcpu);
pvm_init_traps_aa64mmfr1(vcpu);
}
/*
* Start the VM table handle at the offset defined instead of at 0.
* Mainly for sanity checking and debugging.
*/
#define HANDLE_OFFSET 0x1000
static unsigned int vm_handle_to_idx(pkvm_handle_t handle)
{
return handle - HANDLE_OFFSET;
}
static pkvm_handle_t idx_to_vm_handle(unsigned int idx)
{
return idx + HANDLE_OFFSET;
}
/*
* Spinlock for protecting state related to the VM table. Protects writes
* to 'vm_table' and 'nr_table_entries' as well as reads and writes to
* 'last_hyp_vcpu_lookup'.
*/
static DEFINE_HYP_SPINLOCK(vm_table_lock);
/*
* The table of VM entries for protected VMs in hyp.
* Allocated at hyp initialization and setup.
*/
static struct pkvm_hyp_vm **vm_table;
void pkvm_hyp_vm_table_init(void *tbl)
{
WARN_ON(vm_table);
vm_table = tbl;
}
/*
* Return the hyp vm structure corresponding to the handle.
*/
static struct pkvm_hyp_vm *get_vm_by_handle(pkvm_handle_t handle)
{
unsigned int idx = vm_handle_to_idx(handle);
if (unlikely(idx >= KVM_MAX_PVMS))
return NULL;
return vm_table[idx];
}
struct pkvm_hyp_vcpu *pkvm_load_hyp_vcpu(pkvm_handle_t handle,
unsigned int vcpu_idx)
{
struct pkvm_hyp_vcpu *hyp_vcpu = NULL;
struct pkvm_hyp_vm *hyp_vm;
hyp_spin_lock(&vm_table_lock);
hyp_vm = get_vm_by_handle(handle);
if (!hyp_vm || hyp_vm->nr_vcpus <= vcpu_idx)
goto unlock;
hyp_vcpu = hyp_vm->vcpus[vcpu_idx];
hyp_page_ref_inc(hyp_virt_to_page(hyp_vm));
unlock:
hyp_spin_unlock(&vm_table_lock);
return hyp_vcpu;
}
void pkvm_put_hyp_vcpu(struct pkvm_hyp_vcpu *hyp_vcpu)
{
struct pkvm_hyp_vm *hyp_vm = pkvm_hyp_vcpu_to_hyp_vm(hyp_vcpu);
hyp_spin_lock(&vm_table_lock);
hyp_page_ref_dec(hyp_virt_to_page(hyp_vm));
hyp_spin_unlock(&vm_table_lock);
}
static void pkvm_init_features_from_host(struct pkvm_hyp_vm *hyp_vm, const struct kvm *host_kvm)
{
struct kvm *kvm = &hyp_vm->kvm;
DECLARE_BITMAP(allowed_features, KVM_VCPU_MAX_FEATURES);
/* No restrictions for non-protected VMs. */
if (!kvm_vm_is_protected(kvm)) {
bitmap_copy(kvm->arch.vcpu_features,
host_kvm->arch.vcpu_features,
KVM_VCPU_MAX_FEATURES);
return;
}
bitmap_zero(allowed_features, KVM_VCPU_MAX_FEATURES);
/*
* For protected VMs, always allow:
* - CPU starting in poweroff state
* - PSCI v0.2
*/
set_bit(KVM_ARM_VCPU_POWER_OFF, allowed_features);
set_bit(KVM_ARM_VCPU_PSCI_0_2, allowed_features);
/*
* Check if remaining features are allowed:
* - Performance Monitoring
* - Scalable Vectors
* - Pointer Authentication
*/
if (FIELD_GET(ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_PMUVer), PVM_ID_AA64DFR0_ALLOW))
set_bit(KVM_ARM_VCPU_PMU_V3, allowed_features);
if (FIELD_GET(ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_SVE), PVM_ID_AA64PFR0_ALLOW))
set_bit(KVM_ARM_VCPU_SVE, allowed_features);
if (FIELD_GET(ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_API), PVM_ID_AA64ISAR1_RESTRICT_UNSIGNED) &&
FIELD_GET(ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_APA), PVM_ID_AA64ISAR1_RESTRICT_UNSIGNED))
set_bit(KVM_ARM_VCPU_PTRAUTH_ADDRESS, allowed_features);
if (FIELD_GET(ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_GPI), PVM_ID_AA64ISAR1_ALLOW) &&
FIELD_GET(ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_GPA), PVM_ID_AA64ISAR1_ALLOW))
set_bit(KVM_ARM_VCPU_PTRAUTH_GENERIC, allowed_features);
bitmap_and(kvm->arch.vcpu_features, host_kvm->arch.vcpu_features,
allowed_features, KVM_VCPU_MAX_FEATURES);
}
static void pkvm_vcpu_init_ptrauth(struct pkvm_hyp_vcpu *hyp_vcpu)
{
struct kvm_vcpu *vcpu = &hyp_vcpu->vcpu;
if (vcpu_has_feature(vcpu, KVM_ARM_VCPU_PTRAUTH_ADDRESS) ||
vcpu_has_feature(vcpu, KVM_ARM_VCPU_PTRAUTH_GENERIC)) {
kvm_vcpu_enable_ptrauth(vcpu);
} else {
vcpu_clear_flag(&hyp_vcpu->vcpu, GUEST_HAS_PTRAUTH);
}
}
static void unpin_host_vcpu(struct kvm_vcpu *host_vcpu)
{
if (host_vcpu)
hyp_unpin_shared_mem(host_vcpu, host_vcpu + 1);
}
static void unpin_host_vcpus(struct pkvm_hyp_vcpu *hyp_vcpus[],
unsigned int nr_vcpus)
{
int i;
for (i = 0; i < nr_vcpus; i++)
unpin_host_vcpu(hyp_vcpus[i]->host_vcpu);
}
static void init_pkvm_hyp_vm(struct kvm *host_kvm, struct pkvm_hyp_vm *hyp_vm,
unsigned int nr_vcpus)
{
hyp_vm->host_kvm = host_kvm;
hyp_vm->kvm.created_vcpus = nr_vcpus;
hyp_vm->kvm.arch.mmu.vtcr = host_mmu.arch.mmu.vtcr;
hyp_vm->kvm.arch.pkvm.enabled = READ_ONCE(host_kvm->arch.pkvm.enabled);
pkvm_init_features_from_host(hyp_vm, host_kvm);
}
static void pkvm_vcpu_init_sve(struct pkvm_hyp_vcpu *hyp_vcpu, struct kvm_vcpu *host_vcpu)
{
struct kvm_vcpu *vcpu = &hyp_vcpu->vcpu;
if (!vcpu_has_feature(vcpu, KVM_ARM_VCPU_SVE)) {
vcpu_clear_flag(vcpu, GUEST_HAS_SVE);
vcpu_clear_flag(vcpu, VCPU_SVE_FINALIZED);
}
}
static int init_pkvm_hyp_vcpu(struct pkvm_hyp_vcpu *hyp_vcpu,
struct pkvm_hyp_vm *hyp_vm,
struct kvm_vcpu *host_vcpu,
unsigned int vcpu_idx)
{
int ret = 0;
if (hyp_pin_shared_mem(host_vcpu, host_vcpu + 1))
return -EBUSY;
if (host_vcpu->vcpu_idx != vcpu_idx) {
ret = -EINVAL;
goto done;
}
hyp_vcpu->host_vcpu = host_vcpu;
hyp_vcpu->vcpu.kvm = &hyp_vm->kvm;
hyp_vcpu->vcpu.vcpu_id = READ_ONCE(host_vcpu->vcpu_id);
hyp_vcpu->vcpu.vcpu_idx = vcpu_idx;
hyp_vcpu->vcpu.arch.hw_mmu = &hyp_vm->kvm.arch.mmu;
hyp_vcpu->vcpu.arch.cflags = READ_ONCE(host_vcpu->arch.cflags);
hyp_vcpu->vcpu.arch.mp_state.mp_state = KVM_MP_STATE_STOPPED;
pkvm_vcpu_init_sve(hyp_vcpu, host_vcpu);
pkvm_vcpu_init_ptrauth(hyp_vcpu);
pkvm_vcpu_init_traps(&hyp_vcpu->vcpu);
done:
if (ret)
unpin_host_vcpu(host_vcpu);
return ret;
}
static int find_free_vm_table_entry(struct kvm *host_kvm)
{
int i;
for (i = 0; i < KVM_MAX_PVMS; ++i) {
if (!vm_table[i])
return i;
}
return -ENOMEM;
}
/*
* Allocate a VM table entry and insert a pointer to the new vm.
*
* Return a unique handle to the protected VM on success,
* negative error code on failure.
*/
static pkvm_handle_t insert_vm_table_entry(struct kvm *host_kvm,
struct pkvm_hyp_vm *hyp_vm)
{
struct kvm_s2_mmu *mmu = &hyp_vm->kvm.arch.mmu;
int idx;
hyp_assert_lock_held(&vm_table_lock);
/*
* Initializing protected state might have failed, yet a malicious
* host could trigger this function. Thus, ensure that 'vm_table'
* exists.
*/
if (unlikely(!vm_table))
return -EINVAL;
idx = find_free_vm_table_entry(host_kvm);
if (idx < 0)
return idx;
hyp_vm->kvm.arch.pkvm.handle = idx_to_vm_handle(idx);
/* VMID 0 is reserved for the host */
atomic64_set(&mmu->vmid.id, idx + 1);
mmu->arch = &hyp_vm->kvm.arch;
mmu->pgt = &hyp_vm->pgt;
vm_table[idx] = hyp_vm;
return hyp_vm->kvm.arch.pkvm.handle;
}
/*
* Deallocate and remove the VM table entry corresponding to the handle.
*/
static void remove_vm_table_entry(pkvm_handle_t handle)
{
hyp_assert_lock_held(&vm_table_lock);
vm_table[vm_handle_to_idx(handle)] = NULL;
}
static size_t pkvm_get_hyp_vm_size(unsigned int nr_vcpus)
{
return size_add(sizeof(struct pkvm_hyp_vm),
size_mul(sizeof(struct pkvm_hyp_vcpu *), nr_vcpus));
}
static void *map_donated_memory_noclear(unsigned long host_va, size_t size)
{
void *va = (void *)kern_hyp_va(host_va);
if (!PAGE_ALIGNED(va))
return NULL;
if (__pkvm_host_donate_hyp(hyp_virt_to_pfn(va),
PAGE_ALIGN(size) >> PAGE_SHIFT))
return NULL;
return va;
}
static void *map_donated_memory(unsigned long host_va, size_t size)
{
void *va = map_donated_memory_noclear(host_va, size);
if (va)
memset(va, 0, size);
return va;
}
static void __unmap_donated_memory(void *va, size_t size)
{
kvm_flush_dcache_to_poc(va, size);
WARN_ON(__pkvm_hyp_donate_host(hyp_virt_to_pfn(va),
PAGE_ALIGN(size) >> PAGE_SHIFT));
}
static void unmap_donated_memory(void *va, size_t size)
{
if (!va)
return;
memset(va, 0, size);
__unmap_donated_memory(va, size);
}
static void unmap_donated_memory_noclear(void *va, size_t size)
{
if (!va)
return;
__unmap_donated_memory(va, size);
}
/*
* Initialize the hypervisor copy of the protected VM state using the
* memory donated by the host.
*
* Unmaps the donated memory from the host at stage 2.
*
* host_kvm: A pointer to the host's struct kvm.
* vm_hva: The host va of the area being donated for the VM state.
* Must be page aligned.
* pgd_hva: The host va of the area being donated for the stage-2 PGD for
* the VM. Must be page aligned. Its size is implied by the VM's
* VTCR.
*
* Return a unique handle to the protected VM on success,
* negative error code on failure.
*/
int __pkvm_init_vm(struct kvm *host_kvm, unsigned long vm_hva,
unsigned long pgd_hva)
{
struct pkvm_hyp_vm *hyp_vm = NULL;
size_t vm_size, pgd_size;
unsigned int nr_vcpus;
void *pgd = NULL;
int ret;
ret = hyp_pin_shared_mem(host_kvm, host_kvm + 1);
if (ret)
return ret;
nr_vcpus = READ_ONCE(host_kvm->created_vcpus);
if (nr_vcpus < 1) {
ret = -EINVAL;
goto err_unpin_kvm;
}
vm_size = pkvm_get_hyp_vm_size(nr_vcpus);
pgd_size = kvm_pgtable_stage2_pgd_size(host_mmu.arch.mmu.vtcr);
ret = -ENOMEM;
hyp_vm = map_donated_memory(vm_hva, vm_size);
if (!hyp_vm)
goto err_remove_mappings;
pgd = map_donated_memory_noclear(pgd_hva, pgd_size);
if (!pgd)
goto err_remove_mappings;
init_pkvm_hyp_vm(host_kvm, hyp_vm, nr_vcpus);
hyp_spin_lock(&vm_table_lock);
ret = insert_vm_table_entry(host_kvm, hyp_vm);
if (ret < 0)
goto err_unlock;
ret = kvm_guest_prepare_stage2(hyp_vm, pgd);
if (ret)
goto err_remove_vm_table_entry;
hyp_spin_unlock(&vm_table_lock);
return hyp_vm->kvm.arch.pkvm.handle;
err_remove_vm_table_entry:
remove_vm_table_entry(hyp_vm->kvm.arch.pkvm.handle);
err_unlock:
hyp_spin_unlock(&vm_table_lock);
err_remove_mappings:
unmap_donated_memory(hyp_vm, vm_size);
unmap_donated_memory(pgd, pgd_size);
err_unpin_kvm:
hyp_unpin_shared_mem(host_kvm, host_kvm + 1);
return ret;
}
/*
* Initialize the hypervisor copy of the protected vCPU state using the
* memory donated by the host.
*
* handle: The handle for the protected vm.
* host_vcpu: A pointer to the corresponding host vcpu.
* vcpu_hva: The host va of the area being donated for the vcpu state.
* Must be page aligned. The size of the area must be equal to
* the page-aligned size of 'struct pkvm_hyp_vcpu'.
* Return 0 on success, negative error code on failure.
*/
int __pkvm_init_vcpu(pkvm_handle_t handle, struct kvm_vcpu *host_vcpu,
unsigned long vcpu_hva)
{
struct pkvm_hyp_vcpu *hyp_vcpu;
struct pkvm_hyp_vm *hyp_vm;
unsigned int idx;
int ret;
hyp_vcpu = map_donated_memory(vcpu_hva, sizeof(*hyp_vcpu));
if (!hyp_vcpu)
return -ENOMEM;
hyp_spin_lock(&vm_table_lock);
hyp_vm = get_vm_by_handle(handle);
if (!hyp_vm) {
ret = -ENOENT;
goto unlock;
}
idx = hyp_vm->nr_vcpus;
if (idx >= hyp_vm->kvm.created_vcpus) {
ret = -EINVAL;
goto unlock;
}
ret = init_pkvm_hyp_vcpu(hyp_vcpu, hyp_vm, host_vcpu, idx);
if (ret)
goto unlock;
hyp_vm->vcpus[idx] = hyp_vcpu;
hyp_vm->nr_vcpus++;
unlock:
hyp_spin_unlock(&vm_table_lock);
if (ret) {
unmap_donated_memory(hyp_vcpu, sizeof(*hyp_vcpu));
return ret;
}
hyp_vcpu->vcpu.arch.cptr_el2 = kvm_get_reset_cptr_el2(&hyp_vcpu->vcpu);
return 0;
}
static void
teardown_donated_memory(struct kvm_hyp_memcache *mc, void *addr, size_t size)
{
size = PAGE_ALIGN(size);
memset(addr, 0, size);
for (void *start = addr; start < addr + size; start += PAGE_SIZE)
push_hyp_memcache(mc, start, hyp_virt_to_phys);
unmap_donated_memory_noclear(addr, size);
}
int __pkvm_teardown_vm(pkvm_handle_t handle)
{
struct kvm_hyp_memcache *mc;
struct pkvm_hyp_vm *hyp_vm;
struct kvm *host_kvm;
unsigned int idx;
size_t vm_size;
int err;
hyp_spin_lock(&vm_table_lock);
hyp_vm = get_vm_by_handle(handle);
if (!hyp_vm) {
err = -ENOENT;
goto err_unlock;
}
if (WARN_ON(hyp_page_count(hyp_vm))) {
err = -EBUSY;
goto err_unlock;
}
host_kvm = hyp_vm->host_kvm;
/* Ensure the VMID is clean before it can be reallocated */
__kvm_tlb_flush_vmid(&hyp_vm->kvm.arch.mmu);
remove_vm_table_entry(handle);
hyp_spin_unlock(&vm_table_lock);
/* Reclaim guest pages (including page-table pages) */
mc = &host_kvm->arch.pkvm.teardown_mc;
reclaim_guest_pages(hyp_vm, mc);
unpin_host_vcpus(hyp_vm->vcpus, hyp_vm->nr_vcpus);
/* Push the metadata pages to the teardown memcache */
for (idx = 0; idx < hyp_vm->nr_vcpus; ++idx) {
struct pkvm_hyp_vcpu *hyp_vcpu = hyp_vm->vcpus[idx];
teardown_donated_memory(mc, hyp_vcpu, sizeof(*hyp_vcpu));
}
vm_size = pkvm_get_hyp_vm_size(hyp_vm->kvm.created_vcpus);
teardown_donated_memory(mc, hyp_vm, vm_size);
hyp_unpin_shared_mem(host_kvm, host_kvm + 1);
return 0;
err_unlock:
hyp_spin_unlock(&vm_table_lock);
return err;
}
|
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* w1_therm.c
*
* Copyright (c) 2004 Evgeniy Polyakov <[email protected]>
*/
#include <asm/types.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/sched.h>
#include <linux/device.h>
#include <linux/types.h>
#include <linux/slab.h>
#include <linux/delay.h>
#include <linux/hwmon.h>
#include <linux/string.h>
#include <linux/jiffies.h>
#include <linux/w1.h>
#define W1_THERM_DS18S20 0x10
#define W1_THERM_DS1822 0x22
#define W1_THERM_DS18B20 0x28
#define W1_THERM_DS1825 0x3B
#define W1_THERM_DS28EA00 0x42
/*
* Allow the strong pullup to be disabled, but default to enabled.
* If it was disabled a parasite powered device might not get the require
* current to do a temperature conversion. If it is enabled parasite powered
* devices have a better chance of getting the current required.
* In case the parasite power-detection is not working (seems to be the case
* for some DS18S20) the strong pullup can also be forced, regardless of the
* power state of the devices.
*
* Summary of options:
* - strong_pullup = 0 Disable strong pullup completely
* - strong_pullup = 1 Enable automatic strong pullup detection
* - strong_pullup = 2 Force strong pullup
*/
static int w1_strong_pullup = 1;
module_param_named(strong_pullup, w1_strong_pullup, int, 0);
/* Counter for devices supporting bulk reading */
static u16 bulk_read_device_counter; /* =0 as per C standard */
/* This command should be in public header w1.h but is not */
#define W1_RECALL_EEPROM 0xB8
/* Nb of try for an operation */
#define W1_THERM_MAX_TRY 5
/* ms delay to retry bus mutex */
#define W1_THERM_RETRY_DELAY 20
/* delay in ms to write in EEPROM */
#define W1_THERM_EEPROM_WRITE_DELAY 10
#define EEPROM_CMD_WRITE "save" /* cmd for write eeprom sysfs */
#define EEPROM_CMD_READ "restore" /* cmd for read eeprom sysfs */
#define BULK_TRIGGER_CMD "trigger" /* cmd to trigger a bulk read */
#define MIN_TEMP -55 /* min temperature that can be measured */
#define MAX_TEMP 125 /* max temperature that can be measured */
/* Allowed values for sysfs conv_time attribute */
#define CONV_TIME_DEFAULT 0
#define CONV_TIME_MEASURE 1
/* Bits in sysfs "features" value */
#define W1_THERM_CHECK_RESULT 1 /* Enable conversion success check */
#define W1_THERM_POLL_COMPLETION 2 /* Poll for conversion completion */
#define W1_THERM_FEATURES_MASK 3 /* All values mask */
/* Poll period in milliseconds. Should be less then a shortest operation on the device */
#define W1_POLL_PERIOD 32
#define W1_POLL_CONVERT_TEMP 2000 /* Timeout for W1_CONVERT_TEMP, ms */
#define W1_POLL_RECALL_EEPROM 500 /* Timeout for W1_RECALL_EEPROM, ms*/
/* Masks for resolution functions, work with all devices */
/* Bit mask for config register for all devices, bits 7,6,5 */
#define W1_THERM_RESOLUTION_MASK 0xE0
/* Bit offset of resolution in config register for all devices */
#define W1_THERM_RESOLUTION_SHIFT 5
/* Bit offset of resolution in config register for all devices */
#define W1_THERM_RESOLUTION_SHIFT 5
/* Add this to bit value to get resolution */
#define W1_THERM_RESOLUTION_MIN 9
/* Maximum allowed value */
#define W1_THERM_RESOLUTION_MAX 14
/* Helpers Macros */
/*
* return a pointer on the slave w1_therm_family_converter struct:
* always test family data existence before using this macro
*/
#define SLAVE_SPECIFIC_FUNC(sl) \
(((struct w1_therm_family_data *)(sl->family_data))->specific_functions)
/*
* return the power mode of the sl slave : 1-ext, 0-parasite, <0 unknown
* always test family data existence before using this macro
*/
#define SLAVE_POWERMODE(sl) \
(((struct w1_therm_family_data *)(sl->family_data))->external_powered)
/*
* return the resolution in bit of the sl slave : <0 unknown
* always test family data existence before using this macro
*/
#define SLAVE_RESOLUTION(sl) \
(((struct w1_therm_family_data *)(sl->family_data))->resolution)
/*
* return the conv_time_override of the sl slave
* always test family data existence before using this macro
*/
#define SLAVE_CONV_TIME_OVERRIDE(sl) \
(((struct w1_therm_family_data *)(sl->family_data))->conv_time_override)
/*
* return the features of the sl slave
* always test family data existence before using this macro
*/
#define SLAVE_FEATURES(sl) \
(((struct w1_therm_family_data *)(sl->family_data))->features)
/*
* return whether or not a converT command has been issued to the slave
* * 0: no bulk read is pending
* * -1: conversion is in progress
* * 1: conversion done, result to be read
*/
#define SLAVE_CONVERT_TRIGGERED(sl) \
(((struct w1_therm_family_data *)(sl->family_data))->convert_triggered)
/* return the address of the refcnt in the family data */
#define THERM_REFCNT(family_data) \
(&((struct w1_therm_family_data *)family_data)->refcnt)
/* Structs definition */
/**
* struct w1_therm_family_converter - bind device specific functions
* @broken: flag for non-registred families
* @reserved: not used here
* @f: pointer to the device binding structure
* @convert: pointer to the device conversion function
* @get_conversion_time: pointer to the device conversion time function
* @set_resolution: pointer to the device set_resolution function
* @get_resolution: pointer to the device get_resolution function
* @write_data: pointer to the device writing function (2 or 3 bytes)
* @bulk_read: true if device family support bulk read, false otherwise
*/
struct w1_therm_family_converter {
u8 broken;
u16 reserved;
struct w1_family *f;
int (*convert)(u8 rom[9]);
int (*get_conversion_time)(struct w1_slave *sl);
int (*set_resolution)(struct w1_slave *sl, int val);
int (*get_resolution)(struct w1_slave *sl);
int (*write_data)(struct w1_slave *sl, const u8 *data);
bool bulk_read;
};
/**
* struct w1_therm_family_data - device data
* @rom: ROM device id (64bit Lasered ROM code + 1 CRC byte)
* @refcnt: ref count
* @external_powered: 1 device powered externally,
* 0 device parasite powered,
* -x error or undefined
* @resolution: current device resolution
* @convert_triggered: conversion state of the device
* @conv_time_override: user selected conversion time or CONV_TIME_DEFAULT
* @features: bit mask - enable temperature validity check, poll for completion
* @specific_functions: pointer to struct of device specific function
*/
struct w1_therm_family_data {
uint8_t rom[9];
atomic_t refcnt;
int external_powered;
int resolution;
int convert_triggered;
int conv_time_override;
unsigned int features;
struct w1_therm_family_converter *specific_functions;
};
/**
* struct therm_info - store temperature reading
* @rom: read device data (8 data bytes + 1 CRC byte)
* @crc: computed crc from rom
* @verdict: 1 crc checked, 0 crc not matching
*/
struct therm_info {
u8 rom[9];
u8 crc;
u8 verdict;
};
/* Hardware Functions declaration */
/**
* reset_select_slave() - reset and select a slave
* @sl: the slave to select
*
* Resets the bus and select the slave by sending a ROM MATCH cmd
* w1_reset_select_slave() from w1_io.c could not be used here because
* it sent a SKIP ROM command if only one device is on the line.
* At the beginning of the such process, sl->master->slave_count is 1 even if
* more devices are on the line, causing collision on the line.
*
* Context: The w1 master lock must be held.
*
* Return: 0 if success, negative kernel error code otherwise.
*/
static int reset_select_slave(struct w1_slave *sl);
/**
* convert_t() - Query the device for temperature conversion and read
* @sl: pointer to the slave to read
* @info: pointer to a structure to store the read results
*
* Return: 0 if success, -kernel error code otherwise
*/
static int convert_t(struct w1_slave *sl, struct therm_info *info);
/**
* read_scratchpad() - read the data in device RAM
* @sl: pointer to the slave to read
* @info: pointer to a structure to store the read results
*
* Return: 0 if success, -kernel error code otherwise
*/
static int read_scratchpad(struct w1_slave *sl, struct therm_info *info);
/**
* write_scratchpad() - write nb_bytes in the device RAM
* @sl: pointer to the slave to write in
* @data: pointer to an array of 3 bytes, as 3 bytes MUST be written
* @nb_bytes: number of bytes to be written (2 for DS18S20, 3 otherwise)
*
* Return: 0 if success, -kernel error code otherwise
*/
static int write_scratchpad(struct w1_slave *sl, const u8 *data, u8 nb_bytes);
/**
* copy_scratchpad() - Copy the content of scratchpad in device EEPROM
* @sl: slave involved
*
* Return: 0 if success, -kernel error code otherwise
*/
static int copy_scratchpad(struct w1_slave *sl);
/**
* recall_eeprom() - Restore EEPROM data to device RAM
* @sl: slave involved
*
* Return: 0 if success, -kernel error code otherwise
*/
static int recall_eeprom(struct w1_slave *sl);
/**
* read_powermode() - Query the power mode of the slave
* @sl: slave to retrieve the power mode
*
* Ask the device to get its power mode (external or parasite)
* and store the power status in the &struct w1_therm_family_data.
*
* Return:
* * 0 parasite powered device
* * 1 externally powered device
* * <0 kernel error code
*/
static int read_powermode(struct w1_slave *sl);
/**
* trigger_bulk_read() - function to trigger a bulk read on the bus
* @dev_master: the device master of the bus
*
* Send a SKIP ROM follow by a CONVERT T command on the bus.
* It also set the status flag in each slave &struct w1_therm_family_data
* to signal that a conversion is in progress.
*
* Return: 0 if success, -kernel error code otherwise
*/
static int trigger_bulk_read(struct w1_master *dev_master);
/* Sysfs interface declaration */
static ssize_t w1_slave_show(struct device *device,
struct device_attribute *attr, char *buf);
static ssize_t w1_slave_store(struct device *device,
struct device_attribute *attr, const char *buf, size_t size);
static ssize_t w1_seq_show(struct device *device,
struct device_attribute *attr, char *buf);
static ssize_t temperature_show(struct device *device,
struct device_attribute *attr, char *buf);
static ssize_t ext_power_show(struct device *device,
struct device_attribute *attr, char *buf);
static ssize_t resolution_show(struct device *device,
struct device_attribute *attr, char *buf);
static ssize_t resolution_store(struct device *device,
struct device_attribute *attr, const char *buf, size_t size);
static ssize_t eeprom_cmd_store(struct device *device,
struct device_attribute *attr, const char *buf, size_t size);
static ssize_t alarms_store(struct device *device,
struct device_attribute *attr, const char *buf, size_t size);
static ssize_t alarms_show(struct device *device,
struct device_attribute *attr, char *buf);
static ssize_t therm_bulk_read_store(struct device *device,
struct device_attribute *attr, const char *buf, size_t size);
static ssize_t therm_bulk_read_show(struct device *device,
struct device_attribute *attr, char *buf);
static ssize_t conv_time_show(struct device *device,
struct device_attribute *attr, char *buf);
static ssize_t conv_time_store(struct device *device,
struct device_attribute *attr, const char *buf,
size_t size);
static ssize_t features_show(struct device *device,
struct device_attribute *attr, char *buf);
static ssize_t features_store(struct device *device,
struct device_attribute *attr, const char *buf,
size_t size);
/* Attributes declarations */
static DEVICE_ATTR_RW(w1_slave);
static DEVICE_ATTR_RO(w1_seq);
static DEVICE_ATTR_RO(temperature);
static DEVICE_ATTR_RO(ext_power);
static DEVICE_ATTR_RW(resolution);
static DEVICE_ATTR_WO(eeprom_cmd);
static DEVICE_ATTR_RW(alarms);
static DEVICE_ATTR_RW(conv_time);
static DEVICE_ATTR_RW(features);
static DEVICE_ATTR_RW(therm_bulk_read); /* attribut at master level */
/* Interface Functions declaration */
/**
* w1_therm_add_slave() - Called when a new slave is discovered
* @sl: slave just discovered by the master.
*
* Called by the master when the slave is discovered on the bus. Used to
* initialize slave state before the beginning of any communication.
*
* Return: 0 - If success, negative kernel code otherwise
*/
static int w1_therm_add_slave(struct w1_slave *sl);
/**
* w1_therm_remove_slave() - Called when a slave is removed
* @sl: slave to be removed.
*
* Called by the master when the slave is considered not to be on the bus
* anymore. Used to free memory.
*/
static void w1_therm_remove_slave(struct w1_slave *sl);
/* Family attributes */
static struct attribute *w1_therm_attrs[] = {
&dev_attr_w1_slave.attr,
&dev_attr_temperature.attr,
&dev_attr_ext_power.attr,
&dev_attr_resolution.attr,
&dev_attr_eeprom_cmd.attr,
&dev_attr_alarms.attr,
&dev_attr_conv_time.attr,
&dev_attr_features.attr,
NULL,
};
static struct attribute *w1_ds18s20_attrs[] = {
&dev_attr_w1_slave.attr,
&dev_attr_temperature.attr,
&dev_attr_ext_power.attr,
&dev_attr_eeprom_cmd.attr,
&dev_attr_alarms.attr,
&dev_attr_conv_time.attr,
&dev_attr_features.attr,
NULL,
};
static struct attribute *w1_ds28ea00_attrs[] = {
&dev_attr_w1_slave.attr,
&dev_attr_w1_seq.attr,
&dev_attr_temperature.attr,
&dev_attr_ext_power.attr,
&dev_attr_resolution.attr,
&dev_attr_eeprom_cmd.attr,
&dev_attr_alarms.attr,
&dev_attr_conv_time.attr,
&dev_attr_features.attr,
NULL,
};
/* Attribute groups */
ATTRIBUTE_GROUPS(w1_therm);
ATTRIBUTE_GROUPS(w1_ds18s20);
ATTRIBUTE_GROUPS(w1_ds28ea00);
#if IS_REACHABLE(CONFIG_HWMON)
static int w1_read_temp(struct device *dev, u32 attr, int channel,
long *val);
static umode_t w1_is_visible(const void *_data, enum hwmon_sensor_types type,
u32 attr, int channel)
{
return attr == hwmon_temp_input ? 0444 : 0;
}
static int w1_read(struct device *dev, enum hwmon_sensor_types type,
u32 attr, int channel, long *val)
{
switch (type) {
case hwmon_temp:
return w1_read_temp(dev, attr, channel, val);
default:
return -EOPNOTSUPP;
}
}
static const u32 w1_temp_config[] = {
HWMON_T_INPUT,
0
};
static const struct hwmon_channel_info w1_temp = {
.type = hwmon_temp,
.config = w1_temp_config,
};
static const struct hwmon_channel_info * const w1_info[] = {
&w1_temp,
NULL
};
static const struct hwmon_ops w1_hwmon_ops = {
.is_visible = w1_is_visible,
.read = w1_read,
};
static const struct hwmon_chip_info w1_chip_info = {
.ops = &w1_hwmon_ops,
.info = w1_info,
};
#define W1_CHIPINFO (&w1_chip_info)
#else
#define W1_CHIPINFO NULL
#endif
/* Family operations */
static const struct w1_family_ops w1_therm_fops = {
.add_slave = w1_therm_add_slave,
.remove_slave = w1_therm_remove_slave,
.groups = w1_therm_groups,
.chip_info = W1_CHIPINFO,
};
static const struct w1_family_ops w1_ds18s20_fops = {
.add_slave = w1_therm_add_slave,
.remove_slave = w1_therm_remove_slave,
.groups = w1_ds18s20_groups,
.chip_info = W1_CHIPINFO,
};
static const struct w1_family_ops w1_ds28ea00_fops = {
.add_slave = w1_therm_add_slave,
.remove_slave = w1_therm_remove_slave,
.groups = w1_ds28ea00_groups,
.chip_info = W1_CHIPINFO,
};
/* Family binding operations struct */
static struct w1_family w1_therm_family_DS18S20 = {
.fid = W1_THERM_DS18S20,
.fops = &w1_ds18s20_fops,
};
static struct w1_family w1_therm_family_DS18B20 = {
.fid = W1_THERM_DS18B20,
.fops = &w1_therm_fops,
};
static struct w1_family w1_therm_family_DS1822 = {
.fid = W1_THERM_DS1822,
.fops = &w1_therm_fops,
};
static struct w1_family w1_therm_family_DS28EA00 = {
.fid = W1_THERM_DS28EA00,
.fops = &w1_ds28ea00_fops,
};
static struct w1_family w1_therm_family_DS1825 = {
.fid = W1_THERM_DS1825,
.fops = &w1_therm_fops,
};
/* Device dependent func */
static inline int w1_DS18B20_convert_time(struct w1_slave *sl)
{
int ret;
if (!sl->family_data)
return -ENODEV; /* device unknown */
if (SLAVE_CONV_TIME_OVERRIDE(sl) != CONV_TIME_DEFAULT)
return SLAVE_CONV_TIME_OVERRIDE(sl);
/* Return the conversion time, depending on resolution,
* select maximum conversion time among all compatible devices
*/
switch (SLAVE_RESOLUTION(sl)) {
case 9:
ret = 95;
break;
case 10:
ret = 190;
break;
case 11:
ret = 375;
break;
case 12:
ret = 750;
break;
case 13:
ret = 850; /* GX20MH01 only. Datasheet says 500ms, but that's not enough. */
break;
case 14:
ret = 1600; /* GX20MH01 only. Datasheet says 1000ms - not enough */
break;
default:
ret = 750;
}
return ret;
}
static inline int w1_DS18S20_convert_time(struct w1_slave *sl)
{
if (!sl->family_data)
return -ENODEV; /* device unknown */
if (SLAVE_CONV_TIME_OVERRIDE(sl) == CONV_TIME_DEFAULT)
return 750; /* default for DS18S20 */
else
return SLAVE_CONV_TIME_OVERRIDE(sl);
}
static inline int w1_DS1825_convert_time(struct w1_slave *sl)
{
int ret;
if (!sl->family_data)
return -ENODEV; /* device unknown */
if (SLAVE_CONV_TIME_OVERRIDE(sl) != CONV_TIME_DEFAULT)
return SLAVE_CONV_TIME_OVERRIDE(sl);
/* Return the conversion time, depending on resolution,
* select maximum conversion time among all compatible devices
*/
switch (SLAVE_RESOLUTION(sl)) {
case 9:
ret = 95;
break;
case 10:
ret = 190;
break;
case 11:
ret = 375;
break;
case 12:
ret = 750;
break;
case 14:
ret = 100; /* MAX31850 only. Datasheet says 100ms */
break;
default:
ret = 750;
}
return ret;
}
static inline int w1_DS18B20_write_data(struct w1_slave *sl,
const u8 *data)
{
return write_scratchpad(sl, data, 3);
}
static inline int w1_DS18S20_write_data(struct w1_slave *sl,
const u8 *data)
{
/* No config register */
return write_scratchpad(sl, data, 2);
}
static inline int w1_DS18B20_set_resolution(struct w1_slave *sl, int val)
{
int ret;
struct therm_info info, info2;
/* DS18B20 resolution is 9 to 12 bits */
/* GX20MH01 resolution is 9 to 14 bits */
/* MAX31850 resolution is fixed 14 bits */
if (val < W1_THERM_RESOLUTION_MIN || val > W1_THERM_RESOLUTION_MAX)
return -EINVAL;
/* Calc bit value from resolution */
val = (val - W1_THERM_RESOLUTION_MIN) << W1_THERM_RESOLUTION_SHIFT;
/*
* Read the scratchpad to change only the required bits
* (bit5 & bit 6 from byte 4)
*/
ret = read_scratchpad(sl, &info);
if (ret)
return ret;
info.rom[4] &= ~W1_THERM_RESOLUTION_MASK;
info.rom[4] |= val;
/* Write data in the device RAM */
ret = w1_DS18B20_write_data(sl, info.rom + 2);
if (ret)
return ret;
/* Have to read back the resolution to verify an actual value
* GX20MH01 and DS18B20 are indistinguishable by family number, but resolutions differ
* Some DS18B20 clones don't support resolution change
*/
ret = read_scratchpad(sl, &info2);
if (ret)
/* Scratchpad read fail */
return ret;
if ((info2.rom[4] & W1_THERM_RESOLUTION_MASK) == (info.rom[4] & W1_THERM_RESOLUTION_MASK))
return 0;
/* Resolution verify error */
return -EIO;
}
static inline int w1_DS18B20_get_resolution(struct w1_slave *sl)
{
int ret;
int resolution;
struct therm_info info;
ret = read_scratchpad(sl, &info);
if (ret)
return ret;
resolution = ((info.rom[4] & W1_THERM_RESOLUTION_MASK) >> W1_THERM_RESOLUTION_SHIFT)
+ W1_THERM_RESOLUTION_MIN;
/* GX20MH01 has one special case:
* >=14 means 14 bits when getting resolution from bit value.
* MAX31850 delivers fixed 15 and has 14 bits.
* Other devices have no more then 12 bits.
*/
if (resolution > W1_THERM_RESOLUTION_MAX)
resolution = W1_THERM_RESOLUTION_MAX;
return resolution;
}
/**
* w1_DS18B20_convert_temp() - temperature computation for DS18B20
* @rom: data read from device RAM (8 data bytes + 1 CRC byte)
*
* Can be called for any DS18B20 compliant device.
*
* Return: value in millidegrees Celsius.
*/
static inline int w1_DS18B20_convert_temp(u8 rom[9])
{
u16 bv;
s16 t;
/* Signed 16-bit value to unsigned, cpu order */
bv = le16_to_cpup((__le16 *)rom);
/* Config register bit R2 = 1 - GX20MH01 in 13 or 14 bit resolution mode */
if (rom[4] & 0x80) {
/* Insert two temperature bits from config register */
/* Avoid arithmetic shift of signed value */
bv = (bv << 2) | (rom[4] & 3);
t = (s16) bv; /* Degrees, lowest bit is 2^-6 */
return (int)t * 1000 / 64; /* Sign-extend to int; millidegrees */
}
t = (s16)bv; /* Degrees, lowest bit is 2^-4 */
return (int)t * 1000 / 16; /* Sign-extend to int; millidegrees */
}
/**
* w1_DS18S20_convert_temp() - temperature computation for DS18S20
* @rom: data read from device RAM (8 data bytes + 1 CRC byte)
*
* Can be called for any DS18S20 compliant device.
*
* Return: value in millidegrees Celsius.
*/
static inline int w1_DS18S20_convert_temp(u8 rom[9])
{
int t, h;
if (!rom[7]) {
pr_debug("%s: Invalid argument for conversion\n", __func__);
return 0;
}
if (rom[1] == 0)
t = ((s32)rom[0] >> 1)*1000;
else
t = 1000*(-1*(s32)(0x100-rom[0]) >> 1);
t -= 250;
h = 1000*((s32)rom[7] - (s32)rom[6]);
h /= (s32)rom[7];
t += h;
return t;
}
/**
* w1_DS1825_convert_temp() - temperature computation for DS1825
* @rom: data read from device RAM (8 data bytes + 1 CRC byte)
*
* Can be called for any DS1825 compliant device.
* Is used by MAX31850, too
*
* Return: value in millidegrees Celsius.
*/
static inline int w1_DS1825_convert_temp(u8 rom[9])
{
u16 bv;
s16 t;
/* Signed 16-bit value to unsigned, cpu order */
bv = le16_to_cpup((__le16 *)rom);
/* Config register bit 7 = 1 - MA31850 found, 14 bit resolution */
if (rom[4] & 0x80) {
/* Mask out bits 0 (Fault) and 1 (Reserved) */
/* Avoid arithmetic shift of signed value */
bv = (bv & 0xFFFC); /* Degrees, lowest 4 bits are 2^-1, 2^-2 and 2 zero bits */
}
t = (s16)bv; /* Degrees, lowest bit is 2^-4 */
return (int)t * 1000 / 16; /* Sign-extend to int; millidegrees */
}
/* Device capability description */
/* GX20MH01 device shares family number and structure with DS18B20 */
static struct w1_therm_family_converter w1_therm_families[] = {
{
.f = &w1_therm_family_DS18S20,
.convert = w1_DS18S20_convert_temp,
.get_conversion_time = w1_DS18S20_convert_time,
.set_resolution = NULL, /* no config register */
.get_resolution = NULL, /* no config register */
.write_data = w1_DS18S20_write_data,
.bulk_read = true
},
{
.f = &w1_therm_family_DS1822,
.convert = w1_DS18B20_convert_temp,
.get_conversion_time = w1_DS18B20_convert_time,
.set_resolution = w1_DS18B20_set_resolution,
.get_resolution = w1_DS18B20_get_resolution,
.write_data = w1_DS18B20_write_data,
.bulk_read = true
},
{
/* Also used for GX20MH01 */
.f = &w1_therm_family_DS18B20,
.convert = w1_DS18B20_convert_temp,
.get_conversion_time = w1_DS18B20_convert_time,
.set_resolution = w1_DS18B20_set_resolution,
.get_resolution = w1_DS18B20_get_resolution,
.write_data = w1_DS18B20_write_data,
.bulk_read = true
},
{
.f = &w1_therm_family_DS28EA00,
.convert = w1_DS18B20_convert_temp,
.get_conversion_time = w1_DS18B20_convert_time,
.set_resolution = w1_DS18B20_set_resolution,
.get_resolution = w1_DS18B20_get_resolution,
.write_data = w1_DS18B20_write_data,
.bulk_read = false
},
{
/* Also used for MAX31850 */
.f = &w1_therm_family_DS1825,
.convert = w1_DS1825_convert_temp,
.get_conversion_time = w1_DS1825_convert_time,
.set_resolution = w1_DS18B20_set_resolution,
.get_resolution = w1_DS18B20_get_resolution,
.write_data = w1_DS18B20_write_data,
.bulk_read = true
}
};
/* Helpers Functions */
/**
* device_family() - Retrieve a pointer on &struct w1_therm_family_converter
* @sl: slave to retrieve the device specific structure
*
* Return: pointer to the slaves's family converter, NULL if not known
*/
static struct w1_therm_family_converter *device_family(struct w1_slave *sl)
{
struct w1_therm_family_converter *ret = NULL;
int i;
for (i = 0; i < ARRAY_SIZE(w1_therm_families); ++i) {
if (w1_therm_families[i].f->fid == sl->family->fid) {
ret = &w1_therm_families[i];
break;
}
}
return ret;
}
/**
* bus_mutex_lock() - Acquire the mutex
* @lock: w1 bus mutex to acquire
*
* It try to acquire the mutex W1_THERM_MAX_TRY times and wait
* W1_THERM_RETRY_DELAY between 2 attempts.
*
* Return: true is mutex is acquired and lock, false otherwise
*/
static inline bool bus_mutex_lock(struct mutex *lock)
{
int max_trying = W1_THERM_MAX_TRY;
/* try to acquire the mutex, if not, sleep retry_delay before retry) */
while (mutex_lock_interruptible(lock) != 0 && max_trying > 0) {
unsigned long sleep_rem;
sleep_rem = msleep_interruptible(W1_THERM_RETRY_DELAY);
if (!sleep_rem)
max_trying--;
}
if (!max_trying)
return false; /* Didn't acquire the bus mutex */
return true;
}
/**
* check_family_data() - Check if family data and specific functions are present
* @sl: W1 device data
*
* Return: 0 - OK, negative value - error
*/
static int check_family_data(struct w1_slave *sl)
{
if ((!sl->family_data) || (!SLAVE_SPECIFIC_FUNC(sl))) {
dev_info(&sl->dev,
"%s: Device is not supported by the driver\n", __func__);
return -EINVAL; /* No device family */
}
return 0;
}
/**
* bulk_read_support() - check if slave support bulk read
* @sl: device to check the ability
*
* Return: true if bulk read is supported, false if not or error
*/
static inline bool bulk_read_support(struct w1_slave *sl)
{
if (SLAVE_SPECIFIC_FUNC(sl))
return SLAVE_SPECIFIC_FUNC(sl)->bulk_read;
dev_info(&sl->dev,
"%s: Device not supported by the driver\n", __func__);
return false; /* No device family */
}
/**
* conversion_time() - get the Tconv for the slave
* @sl: device to get the conversion time
*
* On device supporting resolution settings, conversion time depend
* on the resolution setting. This helper function get the slave timing,
* depending on its current setting.
*
* Return: conversion time in ms, negative values are kernel error code
*/
static inline int conversion_time(struct w1_slave *sl)
{
if (SLAVE_SPECIFIC_FUNC(sl))
return SLAVE_SPECIFIC_FUNC(sl)->get_conversion_time(sl);
dev_info(&sl->dev,
"%s: Device not supported by the driver\n", __func__);
return -ENODEV; /* No device family */
}
/**
* temperature_from_RAM() - Convert the read info to temperature
* @sl: device that sent the RAM data
* @rom: read value on the slave device RAM
*
* Device dependent, the function bind the correct computation method.
*
* Return: temperature in 1/1000degC, 0 on error.
*/
static inline int temperature_from_RAM(struct w1_slave *sl, u8 rom[9])
{
if (SLAVE_SPECIFIC_FUNC(sl))
return SLAVE_SPECIFIC_FUNC(sl)->convert(rom);
dev_info(&sl->dev,
"%s: Device not supported by the driver\n", __func__);
return 0; /* No device family */
}
/**
* int_to_short() - Safe casting of int to short
*
* @i: integer to be converted to short
*
* Device register use 1 byte to store signed integer.
* This helper function convert the int in a signed short,
* using the min/max values that device can measure as limits.
* min/max values are defined by macro.
*
* Return: a short in the range of min/max value
*/
static inline s8 int_to_short(int i)
{
/* Prepare to cast to short by eliminating out of range values */
i = clamp(i, MIN_TEMP, MAX_TEMP);
return (s8) i;
}
/* Interface Functions */
static int w1_therm_add_slave(struct w1_slave *sl)
{
struct w1_therm_family_converter *sl_family_conv;
/* Allocate memory */
sl->family_data = kzalloc(sizeof(struct w1_therm_family_data),
GFP_KERNEL);
if (!sl->family_data)
return -ENOMEM;
atomic_set(THERM_REFCNT(sl->family_data), 1);
/* Get a pointer to the device specific function struct */
sl_family_conv = device_family(sl);
if (!sl_family_conv) {
kfree(sl->family_data);
return -ENODEV;
}
/* save this pointer to the device structure */
SLAVE_SPECIFIC_FUNC(sl) = sl_family_conv;
if (bulk_read_support(sl)) {
/*
* add the sys entry to trigger bulk_read
* at master level only the 1st time
*/
if (!bulk_read_device_counter) {
int err = device_create_file(&sl->master->dev,
&dev_attr_therm_bulk_read);
if (err)
dev_warn(&sl->dev,
"%s: Device has been added, but bulk read is unavailable. err=%d\n",
__func__, err);
}
/* Increment the counter */
bulk_read_device_counter++;
}
/* Getting the power mode of the device {external, parasite} */
SLAVE_POWERMODE(sl) = read_powermode(sl);
if (SLAVE_POWERMODE(sl) < 0) {
/* no error returned as device has been added */
dev_warn(&sl->dev,
"%s: Device has been added, but power_mode may be corrupted. err=%d\n",
__func__, SLAVE_POWERMODE(sl));
}
/* Getting the resolution of the device */
if (SLAVE_SPECIFIC_FUNC(sl)->get_resolution) {
SLAVE_RESOLUTION(sl) =
SLAVE_SPECIFIC_FUNC(sl)->get_resolution(sl);
if (SLAVE_RESOLUTION(sl) < 0) {
/* no error returned as device has been added */
dev_warn(&sl->dev,
"%s:Device has been added, but resolution may be corrupted. err=%d\n",
__func__, SLAVE_RESOLUTION(sl));
}
}
/* Finally initialize convert_triggered flag */
SLAVE_CONVERT_TRIGGERED(sl) = 0;
return 0;
}
static void w1_therm_remove_slave(struct w1_slave *sl)
{
int refcnt = atomic_sub_return(1, THERM_REFCNT(sl->family_data));
if (bulk_read_support(sl)) {
bulk_read_device_counter--;
/* Delete the entry if no more device support the feature */
if (!bulk_read_device_counter)
device_remove_file(&sl->master->dev,
&dev_attr_therm_bulk_read);
}
while (refcnt) {
msleep(1000);
refcnt = atomic_read(THERM_REFCNT(sl->family_data));
}
kfree(sl->family_data);
sl->family_data = NULL;
}
/* Hardware Functions */
/* Safe version of reset_select_slave - avoid using the one in w_io.c */
static int reset_select_slave(struct w1_slave *sl)
{
u8 match[9] = { W1_MATCH_ROM, };
u64 rn = le64_to_cpu(*((u64 *)&sl->reg_num));
if (w1_reset_bus(sl->master))
return -ENODEV;
memcpy(&match[1], &rn, 8);
w1_write_block(sl->master, match, 9);
return 0;
}
/**
* w1_poll_completion - Poll for operation completion, with timeout
* @dev_master: the device master of the bus
* @tout_ms: timeout in milliseconds
*
* The device is answering 0's while an operation is in progress and 1's after it completes
* Timeout may happen if the previous command was not recognised due to a line noise
*
* Return: 0 - OK, negative error - timeout
*/
static int w1_poll_completion(struct w1_master *dev_master, int tout_ms)
{
int i;
for (i = 0; i < tout_ms/W1_POLL_PERIOD; i++) {
/* Delay is before poll, for device to recognize a command */
msleep(W1_POLL_PERIOD);
/* Compare all 8 bits to mitigate a noise on the bus */
if (w1_read_8(dev_master) == 0xFF)
break;
}
if (i == tout_ms/W1_POLL_PERIOD)
return -EIO;
return 0;
}
static int convert_t(struct w1_slave *sl, struct therm_info *info)
{
struct w1_master *dev_master = sl->master;
int max_trying = W1_THERM_MAX_TRY;
int t_conv;
int ret = -ENODEV;
bool strong_pullup;
if (!sl->family_data)
goto error;
strong_pullup = (w1_strong_pullup == 2 ||
(!SLAVE_POWERMODE(sl) &&
w1_strong_pullup));
if (strong_pullup && SLAVE_FEATURES(sl) & W1_THERM_POLL_COMPLETION) {
dev_warn(&sl->dev,
"%s: Disabling W1_THERM_POLL_COMPLETION in parasite power mode.\n",
__func__);
SLAVE_FEATURES(sl) &= ~W1_THERM_POLL_COMPLETION;
}
/* get conversion duration device and id dependent */
t_conv = conversion_time(sl);
memset(info->rom, 0, sizeof(info->rom));
/* prevent the slave from going away in sleep */
atomic_inc(THERM_REFCNT(sl->family_data));
if (!bus_mutex_lock(&dev_master->bus_mutex)) {
ret = -EAGAIN; /* Didn't acquire the mutex */
goto dec_refcnt;
}
while (max_trying-- && ret) { /* ret should be 0 */
info->verdict = 0;
info->crc = 0;
/* safe version to select slave */
if (!reset_select_slave(sl)) {
unsigned long sleep_rem;
/* 750ms strong pullup (or delay) after the convert */
if (strong_pullup)
w1_next_pullup(dev_master, t_conv);
w1_write_8(dev_master, W1_CONVERT_TEMP);
if (SLAVE_FEATURES(sl) & W1_THERM_POLL_COMPLETION) {
ret = w1_poll_completion(dev_master, W1_POLL_CONVERT_TEMP);
if (ret) {
dev_dbg(&sl->dev, "%s: Timeout\n", __func__);
goto mt_unlock;
}
mutex_unlock(&dev_master->bus_mutex);
} else if (!strong_pullup) { /*no device need pullup */
sleep_rem = msleep_interruptible(t_conv);
if (sleep_rem != 0) {
ret = -EINTR;
goto mt_unlock;
}
mutex_unlock(&dev_master->bus_mutex);
} else { /*some device need pullup */
mutex_unlock(&dev_master->bus_mutex);
sleep_rem = msleep_interruptible(t_conv);
if (sleep_rem != 0) {
ret = -EINTR;
goto dec_refcnt;
}
}
ret = read_scratchpad(sl, info);
/* If enabled, check for conversion success */
if ((SLAVE_FEATURES(sl) & W1_THERM_CHECK_RESULT) &&
(info->rom[6] == 0xC) &&
((info->rom[1] == 0x5 && info->rom[0] == 0x50) ||
(info->rom[1] == 0x7 && info->rom[0] == 0xFF))
) {
/* Invalid reading (scratchpad byte 6 = 0xC)
* due to insufficient conversion time
* or power failure.
*/
ret = -EIO;
}
goto dec_refcnt;
}
}
mt_unlock:
mutex_unlock(&dev_master->bus_mutex);
dec_refcnt:
atomic_dec(THERM_REFCNT(sl->family_data));
error:
return ret;
}
static int conv_time_measure(struct w1_slave *sl, int *conv_time)
{
struct therm_info inf,
*info = &inf;
struct w1_master *dev_master = sl->master;
int max_trying = W1_THERM_MAX_TRY;
int ret = -ENODEV;
bool strong_pullup;
if (!sl->family_data)
goto error;
strong_pullup = (w1_strong_pullup == 2 ||
(!SLAVE_POWERMODE(sl) &&
w1_strong_pullup));
if (strong_pullup) {
pr_info("%s: Measure with strong_pullup is not supported.\n", __func__);
return -EINVAL;
}
memset(info->rom, 0, sizeof(info->rom));
/* prevent the slave from going away in sleep */
atomic_inc(THERM_REFCNT(sl->family_data));
if (!bus_mutex_lock(&dev_master->bus_mutex)) {
ret = -EAGAIN; /* Didn't acquire the mutex */
goto dec_refcnt;
}
while (max_trying-- && ret) { /* ret should be 0 */
info->verdict = 0;
info->crc = 0;
/* safe version to select slave */
if (!reset_select_slave(sl)) {
int j_start, j_end;
/*no device need pullup */
w1_write_8(dev_master, W1_CONVERT_TEMP);
j_start = jiffies;
ret = w1_poll_completion(dev_master, W1_POLL_CONVERT_TEMP);
if (ret) {
dev_dbg(&sl->dev, "%s: Timeout\n", __func__);
goto mt_unlock;
}
j_end = jiffies;
/* 1.2x increase for variation and changes over temperature range */
*conv_time = jiffies_to_msecs(j_end-j_start)*12/10;
pr_debug("W1 Measure complete, conv_time = %d, HZ=%d.\n",
*conv_time, HZ);
if (*conv_time <= CONV_TIME_MEASURE) {
ret = -EIO;
goto mt_unlock;
}
mutex_unlock(&dev_master->bus_mutex);
ret = read_scratchpad(sl, info);
goto dec_refcnt;
}
}
mt_unlock:
mutex_unlock(&dev_master->bus_mutex);
dec_refcnt:
atomic_dec(THERM_REFCNT(sl->family_data));
error:
return ret;
}
static int read_scratchpad(struct w1_slave *sl, struct therm_info *info)
{
struct w1_master *dev_master = sl->master;
int max_trying = W1_THERM_MAX_TRY;
int ret = -ENODEV;
info->verdict = 0;
if (!sl->family_data)
goto error;
memset(info->rom, 0, sizeof(info->rom));
/* prevent the slave from going away in sleep */
atomic_inc(THERM_REFCNT(sl->family_data));
if (!bus_mutex_lock(&dev_master->bus_mutex)) {
ret = -EAGAIN; /* Didn't acquire the mutex */
goto dec_refcnt;
}
while (max_trying-- && ret) { /* ret should be 0 */
/* safe version to select slave */
if (!reset_select_slave(sl)) {
u8 nb_bytes_read;
w1_write_8(dev_master, W1_READ_SCRATCHPAD);
nb_bytes_read = w1_read_block(dev_master, info->rom, 9);
if (nb_bytes_read != 9) {
dev_warn(&sl->dev,
"w1_read_block(): returned %u instead of 9.\n",
nb_bytes_read);
ret = -EIO;
}
info->crc = w1_calc_crc8(info->rom, 8);
if (info->rom[8] == info->crc) {
info->verdict = 1;
ret = 0;
} else
ret = -EIO; /* CRC not checked */
}
}
mutex_unlock(&dev_master->bus_mutex);
dec_refcnt:
atomic_dec(THERM_REFCNT(sl->family_data));
error:
return ret;
}
static int write_scratchpad(struct w1_slave *sl, const u8 *data, u8 nb_bytes)
{
struct w1_master *dev_master = sl->master;
int max_trying = W1_THERM_MAX_TRY;
int ret = -ENODEV;
if (!sl->family_data)
goto error;
/* prevent the slave from going away in sleep */
atomic_inc(THERM_REFCNT(sl->family_data));
if (!bus_mutex_lock(&dev_master->bus_mutex)) {
ret = -EAGAIN; /* Didn't acquire the mutex */
goto dec_refcnt;
}
while (max_trying-- && ret) { /* ret should be 0 */
/* safe version to select slave */
if (!reset_select_slave(sl)) {
w1_write_8(dev_master, W1_WRITE_SCRATCHPAD);
w1_write_block(dev_master, data, nb_bytes);
ret = 0;
}
}
mutex_unlock(&dev_master->bus_mutex);
dec_refcnt:
atomic_dec(THERM_REFCNT(sl->family_data));
error:
return ret;
}
static int copy_scratchpad(struct w1_slave *sl)
{
struct w1_master *dev_master = sl->master;
int max_trying = W1_THERM_MAX_TRY;
int t_write, ret = -ENODEV;
bool strong_pullup;
if (!sl->family_data)
goto error;
t_write = W1_THERM_EEPROM_WRITE_DELAY;
strong_pullup = (w1_strong_pullup == 2 ||
(!SLAVE_POWERMODE(sl) &&
w1_strong_pullup));
/* prevent the slave from going away in sleep */
atomic_inc(THERM_REFCNT(sl->family_data));
if (!bus_mutex_lock(&dev_master->bus_mutex)) {
ret = -EAGAIN; /* Didn't acquire the mutex */
goto dec_refcnt;
}
while (max_trying-- && ret) { /* ret should be 0 */
/* safe version to select slave */
if (!reset_select_slave(sl)) {
unsigned long sleep_rem;
/* 10ms strong pullup (or delay) after the convert */
if (strong_pullup)
w1_next_pullup(dev_master, t_write);
w1_write_8(dev_master, W1_COPY_SCRATCHPAD);
if (strong_pullup) {
sleep_rem = msleep_interruptible(t_write);
if (sleep_rem != 0) {
ret = -EINTR;
goto mt_unlock;
}
}
ret = 0;
}
}
mt_unlock:
mutex_unlock(&dev_master->bus_mutex);
dec_refcnt:
atomic_dec(THERM_REFCNT(sl->family_data));
error:
return ret;
}
static int recall_eeprom(struct w1_slave *sl)
{
struct w1_master *dev_master = sl->master;
int max_trying = W1_THERM_MAX_TRY;
int ret = -ENODEV;
if (!sl->family_data)
goto error;
/* prevent the slave from going away in sleep */
atomic_inc(THERM_REFCNT(sl->family_data));
if (!bus_mutex_lock(&dev_master->bus_mutex)) {
ret = -EAGAIN; /* Didn't acquire the mutex */
goto dec_refcnt;
}
while (max_trying-- && ret) { /* ret should be 0 */
/* safe version to select slave */
if (!reset_select_slave(sl)) {
w1_write_8(dev_master, W1_RECALL_EEPROM);
ret = w1_poll_completion(dev_master, W1_POLL_RECALL_EEPROM);
}
}
mutex_unlock(&dev_master->bus_mutex);
dec_refcnt:
atomic_dec(THERM_REFCNT(sl->family_data));
error:
return ret;
}
static int read_powermode(struct w1_slave *sl)
{
struct w1_master *dev_master = sl->master;
int max_trying = W1_THERM_MAX_TRY;
int ret = -ENODEV;
if (!sl->family_data)
goto error;
/* prevent the slave from going away in sleep */
atomic_inc(THERM_REFCNT(sl->family_data));
if (!bus_mutex_lock(&dev_master->bus_mutex)) {
ret = -EAGAIN; /* Didn't acquire the mutex */
goto dec_refcnt;
}
while ((max_trying--) && (ret < 0)) {
/* safe version to select slave */
if (!reset_select_slave(sl)) {
w1_write_8(dev_master, W1_READ_PSUPPLY);
/*
* Emit a read time slot and read only one bit,
* 1 is externally powered,
* 0 is parasite powered
*/
ret = w1_touch_bit(dev_master, 1);
/* ret should be either 1 either 0 */
}
}
mutex_unlock(&dev_master->bus_mutex);
dec_refcnt:
atomic_dec(THERM_REFCNT(sl->family_data));
error:
return ret;
}
static int trigger_bulk_read(struct w1_master *dev_master)
{
struct w1_slave *sl = NULL; /* used to iterate through slaves */
int max_trying = W1_THERM_MAX_TRY;
int t_conv = 0;
int ret = -ENODEV;
bool strong_pullup = false;
/*
* Check whether there are parasite powered device on the bus,
* and compute duration of conversion for these devices
* so we can apply a strong pullup if required
*/
list_for_each_entry(sl, &dev_master->slist, w1_slave_entry) {
if (!sl->family_data)
goto error;
if (bulk_read_support(sl)) {
int t_cur = conversion_time(sl);
t_conv = max(t_cur, t_conv);
strong_pullup = strong_pullup ||
(w1_strong_pullup == 2 ||
(!SLAVE_POWERMODE(sl) &&
w1_strong_pullup));
}
}
/*
* t_conv is the max conversion time required on the bus
* If its 0, no device support the bulk read feature
*/
if (!t_conv)
goto error;
if (!bus_mutex_lock(&dev_master->bus_mutex)) {
ret = -EAGAIN; /* Didn't acquire the mutex */
goto error;
}
while ((max_trying--) && (ret < 0)) { /* ret should be either 0 */
if (!w1_reset_bus(dev_master)) { /* Just reset the bus */
unsigned long sleep_rem;
w1_write_8(dev_master, W1_SKIP_ROM);
if (strong_pullup) /* Apply pullup if required */
w1_next_pullup(dev_master, t_conv);
w1_write_8(dev_master, W1_CONVERT_TEMP);
/* set a flag to instruct that converT pending */
list_for_each_entry(sl,
&dev_master->slist, w1_slave_entry) {
if (bulk_read_support(sl))
SLAVE_CONVERT_TRIGGERED(sl) = -1;
}
if (strong_pullup) { /* some device need pullup */
sleep_rem = msleep_interruptible(t_conv);
if (sleep_rem != 0) {
ret = -EINTR;
goto mt_unlock;
}
mutex_unlock(&dev_master->bus_mutex);
} else {
mutex_unlock(&dev_master->bus_mutex);
sleep_rem = msleep_interruptible(t_conv);
if (sleep_rem != 0) {
ret = -EINTR;
goto set_flag;
}
}
ret = 0;
goto set_flag;
}
}
mt_unlock:
mutex_unlock(&dev_master->bus_mutex);
set_flag:
/* set a flag to register convsersion is done */
list_for_each_entry(sl, &dev_master->slist, w1_slave_entry) {
if (bulk_read_support(sl))
SLAVE_CONVERT_TRIGGERED(sl) = 1;
}
error:
return ret;
}
/* Sysfs Interface definition */
static ssize_t w1_slave_show(struct device *device,
struct device_attribute *attr, char *buf)
{
struct w1_slave *sl = dev_to_w1_slave(device);
struct therm_info info;
u8 *family_data = sl->family_data;
int ret, i;
ssize_t c = PAGE_SIZE;
if (bulk_read_support(sl)) {
if (SLAVE_CONVERT_TRIGGERED(sl) < 0) {
dev_dbg(device,
"%s: Conversion in progress, retry later\n",
__func__);
return 0;
} else if (SLAVE_CONVERT_TRIGGERED(sl) > 0) {
/* A bulk read has been issued, read the device RAM */
ret = read_scratchpad(sl, &info);
SLAVE_CONVERT_TRIGGERED(sl) = 0;
} else
ret = convert_t(sl, &info);
} else
ret = convert_t(sl, &info);
if (ret < 0) {
dev_dbg(device,
"%s: Temperature data may be corrupted. err=%d\n",
__func__, ret);
return 0;
}
for (i = 0; i < 9; ++i)
c -= snprintf(buf + PAGE_SIZE - c, c, "%02x ", info.rom[i]);
c -= snprintf(buf + PAGE_SIZE - c, c, ": crc=%02x %s\n",
info.crc, (info.verdict) ? "YES" : "NO");
if (info.verdict)
memcpy(family_data, info.rom, sizeof(info.rom));
else
dev_warn(device, "%s:Read failed CRC check\n", __func__);
for (i = 0; i < 9; ++i)
c -= snprintf(buf + PAGE_SIZE - c, c, "%02x ",
((u8 *)family_data)[i]);
c -= snprintf(buf + PAGE_SIZE - c, c, "t=%d\n",
temperature_from_RAM(sl, info.rom));
ret = PAGE_SIZE - c;
return ret;
}
static ssize_t w1_slave_store(struct device *device,
struct device_attribute *attr, const char *buf,
size_t size)
{
int val, ret = 0;
struct w1_slave *sl = dev_to_w1_slave(device);
ret = kstrtoint(buf, 10, &val); /* converting user entry to int */
if (ret) { /* conversion error */
dev_info(device,
"%s: conversion error. err= %d\n", __func__, ret);
return size; /* return size to avoid call back again */
}
if ((!sl->family_data) || (!SLAVE_SPECIFIC_FUNC(sl))) {
dev_info(device,
"%s: Device not supported by the driver\n", __func__);
return size; /* No device family */
}
if (val == 0) /* val=0 : trigger a EEPROM save */
ret = copy_scratchpad(sl);
else {
if (SLAVE_SPECIFIC_FUNC(sl)->set_resolution)
ret = SLAVE_SPECIFIC_FUNC(sl)->set_resolution(sl, val);
}
if (ret) {
dev_warn(device, "%s: Set resolution - error %d\n", __func__, ret);
/* Propagate error to userspace */
return ret;
}
SLAVE_RESOLUTION(sl) = val;
/* Reset the conversion time to default - it depends on resolution */
SLAVE_CONV_TIME_OVERRIDE(sl) = CONV_TIME_DEFAULT;
return size; /* always return size to avoid infinite calling */
}
static ssize_t temperature_show(struct device *device,
struct device_attribute *attr, char *buf)
{
struct w1_slave *sl = dev_to_w1_slave(device);
struct therm_info info;
int ret = 0;
if ((!sl->family_data) || (!SLAVE_SPECIFIC_FUNC(sl))) {
dev_info(device,
"%s: Device not supported by the driver\n", __func__);
return 0; /* No device family */
}
if (bulk_read_support(sl)) {
if (SLAVE_CONVERT_TRIGGERED(sl) < 0) {
dev_dbg(device,
"%s: Conversion in progress, retry later\n",
__func__);
return 0;
} else if (SLAVE_CONVERT_TRIGGERED(sl) > 0) {
/* A bulk read has been issued, read the device RAM */
ret = read_scratchpad(sl, &info);
SLAVE_CONVERT_TRIGGERED(sl) = 0;
} else
ret = convert_t(sl, &info);
} else
ret = convert_t(sl, &info);
if (ret < 0) {
dev_dbg(device,
"%s: Temperature data may be corrupted. err=%d\n",
__func__, ret);
return 0;
}
return sprintf(buf, "%d\n", temperature_from_RAM(sl, info.rom));
}
static ssize_t ext_power_show(struct device *device,
struct device_attribute *attr, char *buf)
{
struct w1_slave *sl = dev_to_w1_slave(device);
if (!sl->family_data) {
dev_info(device,
"%s: Device not supported by the driver\n", __func__);
return 0; /* No device family */
}
/* Getting the power mode of the device {external, parasite} */
SLAVE_POWERMODE(sl) = read_powermode(sl);
if (SLAVE_POWERMODE(sl) < 0) {
dev_dbg(device,
"%s: Power_mode may be corrupted. err=%d\n",
__func__, SLAVE_POWERMODE(sl));
}
return sprintf(buf, "%d\n", SLAVE_POWERMODE(sl));
}
static ssize_t resolution_show(struct device *device,
struct device_attribute *attr, char *buf)
{
struct w1_slave *sl = dev_to_w1_slave(device);
if ((!sl->family_data) || (!SLAVE_SPECIFIC_FUNC(sl))) {
dev_info(device,
"%s: Device not supported by the driver\n", __func__);
return 0; /* No device family */
}
/* get the correct function depending on the device */
SLAVE_RESOLUTION(sl) = SLAVE_SPECIFIC_FUNC(sl)->get_resolution(sl);
if (SLAVE_RESOLUTION(sl) < 0) {
dev_dbg(device,
"%s: Resolution may be corrupted. err=%d\n",
__func__, SLAVE_RESOLUTION(sl));
}
return sprintf(buf, "%d\n", SLAVE_RESOLUTION(sl));
}
static ssize_t resolution_store(struct device *device,
struct device_attribute *attr, const char *buf, size_t size)
{
struct w1_slave *sl = dev_to_w1_slave(device);
int val;
int ret = 0;
ret = kstrtoint(buf, 10, &val); /* converting user entry to int */
if (ret) { /* conversion error */
dev_info(device,
"%s: conversion error. err= %d\n", __func__, ret);
return size; /* return size to avoid call back again */
}
if ((!sl->family_data) || (!SLAVE_SPECIFIC_FUNC(sl))) {
dev_info(device,
"%s: Device not supported by the driver\n", __func__);
return size; /* No device family */
}
/*
* Don't deal with the val enterd by user,
* only device knows what is correct or not
*/
/* get the correct function depending on the device */
ret = SLAVE_SPECIFIC_FUNC(sl)->set_resolution(sl, val);
if (ret)
return ret;
SLAVE_RESOLUTION(sl) = val;
/* Reset the conversion time to default because it depends on resolution */
SLAVE_CONV_TIME_OVERRIDE(sl) = CONV_TIME_DEFAULT;
return size;
}
static ssize_t eeprom_cmd_store(struct device *device,
struct device_attribute *attr, const char *buf, size_t size)
{
struct w1_slave *sl = dev_to_w1_slave(device);
int ret = -EINVAL; /* Invalid argument */
if (size == sizeof(EEPROM_CMD_WRITE)) {
if (!strncmp(buf, EEPROM_CMD_WRITE, sizeof(EEPROM_CMD_WRITE)-1))
ret = copy_scratchpad(sl);
} else if (size == sizeof(EEPROM_CMD_READ)) {
if (!strncmp(buf, EEPROM_CMD_READ, sizeof(EEPROM_CMD_READ)-1))
ret = recall_eeprom(sl);
}
if (ret)
dev_info(device, "%s: error in process %d\n", __func__, ret);
return size;
}
static ssize_t alarms_show(struct device *device,
struct device_attribute *attr, char *buf)
{
struct w1_slave *sl = dev_to_w1_slave(device);
int ret;
s8 th = 0, tl = 0;
struct therm_info scratchpad;
ret = read_scratchpad(sl, &scratchpad);
if (!ret) {
th = scratchpad.rom[2]; /* TH is byte 2 */
tl = scratchpad.rom[3]; /* TL is byte 3 */
} else {
dev_info(device,
"%s: error reading alarms register %d\n",
__func__, ret);
}
return sprintf(buf, "%hd %hd\n", tl, th);
}
static ssize_t alarms_store(struct device *device,
struct device_attribute *attr, const char *buf, size_t size)
{
struct w1_slave *sl = dev_to_w1_slave(device);
struct therm_info info;
u8 new_config_register[3]; /* array of data to be written */
int temp, ret;
char *token = NULL;
s8 tl, th; /* 1 byte per value + temp ring order */
char *p_args, *orig;
p_args = orig = kmalloc(size, GFP_KERNEL);
/* Safe string copys as buf is const */
if (!p_args) {
dev_warn(device,
"%s: error unable to allocate memory %d\n",
__func__, -ENOMEM);
return size;
}
strcpy(p_args, buf);
/* Split string using space char */
token = strsep(&p_args, " ");
if (!token) {
dev_info(device,
"%s: error parsing args %d\n", __func__, -EINVAL);
goto free_m;
}
/* Convert 1st entry to int */
ret = kstrtoint (token, 10, &temp);
if (ret) {
dev_info(device,
"%s: error parsing args %d\n", __func__, ret);
goto free_m;
}
tl = int_to_short(temp);
/* Split string using space char */
token = strsep(&p_args, " ");
if (!token) {
dev_info(device,
"%s: error parsing args %d\n", __func__, -EINVAL);
goto free_m;
}
/* Convert 2nd entry to int */
ret = kstrtoint (token, 10, &temp);
if (ret) {
dev_info(device,
"%s: error parsing args %d\n", __func__, ret);
goto free_m;
}
/* Prepare to cast to short by eliminating out of range values */
th = int_to_short(temp);
/* Reorder if required th and tl */
if (tl > th)
swap(tl, th);
/*
* Read the scratchpad to change only the required bits
* (th : byte 2 - tl: byte 3)
*/
ret = read_scratchpad(sl, &info);
if (!ret) {
new_config_register[0] = th; /* Byte 2 */
new_config_register[1] = tl; /* Byte 3 */
new_config_register[2] = info.rom[4];/* Byte 4 */
} else {
dev_info(device,
"%s: error reading from the slave device %d\n",
__func__, ret);
goto free_m;
}
/* Write data in the device RAM */
if (!SLAVE_SPECIFIC_FUNC(sl)) {
dev_info(device,
"%s: Device not supported by the driver %d\n",
__func__, -ENODEV);
goto free_m;
}
ret = SLAVE_SPECIFIC_FUNC(sl)->write_data(sl, new_config_register);
if (ret)
dev_info(device,
"%s: error writing to the slave device %d\n",
__func__, ret);
free_m:
/* free allocated memory */
kfree(orig);
return size;
}
static ssize_t therm_bulk_read_store(struct device *device,
struct device_attribute *attr, const char *buf, size_t size)
{
struct w1_master *dev_master = dev_to_w1_master(device);
int ret = -EINVAL; /* Invalid argument */
if (size == sizeof(BULK_TRIGGER_CMD))
if (!strncmp(buf, BULK_TRIGGER_CMD,
sizeof(BULK_TRIGGER_CMD)-1))
ret = trigger_bulk_read(dev_master);
if (ret)
dev_info(device,
"%s: unable to trigger a bulk read on the bus. err=%d\n",
__func__, ret);
return size;
}
static ssize_t therm_bulk_read_show(struct device *device,
struct device_attribute *attr, char *buf)
{
struct w1_master *dev_master = dev_to_w1_master(device);
struct w1_slave *sl = NULL;
int ret = 0;
list_for_each_entry(sl, &dev_master->slist, w1_slave_entry) {
if (sl->family_data) {
if (bulk_read_support(sl)) {
if (SLAVE_CONVERT_TRIGGERED(sl) == -1) {
ret = -1;
goto show_result;
}
if (SLAVE_CONVERT_TRIGGERED(sl) == 1)
/* continue to check other slaves */
ret = 1;
}
}
}
show_result:
return sprintf(buf, "%d\n", ret);
}
static ssize_t conv_time_show(struct device *device,
struct device_attribute *attr, char *buf)
{
struct w1_slave *sl = dev_to_w1_slave(device);
if ((!sl->family_data) || (!SLAVE_SPECIFIC_FUNC(sl))) {
dev_info(device,
"%s: Device is not supported by the driver\n", __func__);
return 0; /* No device family */
}
return sprintf(buf, "%d\n", conversion_time(sl));
}
static ssize_t conv_time_store(struct device *device,
struct device_attribute *attr, const char *buf, size_t size)
{
int val, ret = 0;
struct w1_slave *sl = dev_to_w1_slave(device);
if (kstrtoint(buf, 10, &val)) /* converting user entry to int */
return -EINVAL;
if (check_family_data(sl))
return -ENODEV;
if (val != CONV_TIME_MEASURE) {
if (val >= CONV_TIME_DEFAULT)
SLAVE_CONV_TIME_OVERRIDE(sl) = val;
else
return -EINVAL;
} else {
int conv_time;
ret = conv_time_measure(sl, &conv_time);
if (ret)
return -EIO;
SLAVE_CONV_TIME_OVERRIDE(sl) = conv_time;
}
return size;
}
static ssize_t features_show(struct device *device,
struct device_attribute *attr, char *buf)
{
struct w1_slave *sl = dev_to_w1_slave(device);
if ((!sl->family_data) || (!SLAVE_SPECIFIC_FUNC(sl))) {
dev_info(device,
"%s: Device not supported by the driver\n", __func__);
return 0; /* No device family */
}
return sprintf(buf, "%u\n", SLAVE_FEATURES(sl));
}
static ssize_t features_store(struct device *device,
struct device_attribute *attr, const char *buf, size_t size)
{
int val, ret = 0;
bool strong_pullup;
struct w1_slave *sl = dev_to_w1_slave(device);
ret = kstrtouint(buf, 10, &val); /* converting user entry to int */
if (ret)
return -EINVAL; /* invalid number */
if ((!sl->family_data) || (!SLAVE_SPECIFIC_FUNC(sl))) {
dev_info(device, "%s: Device not supported by the driver\n", __func__);
return -ENODEV;
}
if ((val & W1_THERM_FEATURES_MASK) != val)
return -EINVAL;
SLAVE_FEATURES(sl) = val;
strong_pullup = (w1_strong_pullup == 2 ||
(!SLAVE_POWERMODE(sl) &&
w1_strong_pullup));
if (strong_pullup && SLAVE_FEATURES(sl) & W1_THERM_POLL_COMPLETION) {
dev_warn(&sl->dev,
"%s: W1_THERM_POLL_COMPLETION disabled in parasite power mode.\n",
__func__);
SLAVE_FEATURES(sl) &= ~W1_THERM_POLL_COMPLETION;
}
return size;
}
#if IS_REACHABLE(CONFIG_HWMON)
static int w1_read_temp(struct device *device, u32 attr, int channel,
long *val)
{
struct w1_slave *sl = dev_get_drvdata(device);
struct therm_info info;
int ret;
switch (attr) {
case hwmon_temp_input:
ret = convert_t(sl, &info);
if (ret)
return ret;
if (!info.verdict) {
ret = -EIO;
return ret;
}
*val = temperature_from_RAM(sl, info.rom);
ret = 0;
break;
default:
ret = -EOPNOTSUPP;
break;
}
return ret;
}
#endif
#define W1_42_CHAIN 0x99
#define W1_42_CHAIN_OFF 0x3C
#define W1_42_CHAIN_OFF_INV 0xC3
#define W1_42_CHAIN_ON 0x5A
#define W1_42_CHAIN_ON_INV 0xA5
#define W1_42_CHAIN_DONE 0x96
#define W1_42_CHAIN_DONE_INV 0x69
#define W1_42_COND_READ 0x0F
#define W1_42_SUCCESS_CONFIRM_BYTE 0xAA
#define W1_42_FINISHED_BYTE 0xFF
static ssize_t w1_seq_show(struct device *device,
struct device_attribute *attr, char *buf)
{
struct w1_slave *sl = dev_to_w1_slave(device);
ssize_t c = PAGE_SIZE;
int i;
u8 ack;
u64 rn;
struct w1_reg_num *reg_num;
int seq = 0;
mutex_lock(&sl->master->bus_mutex);
/* Place all devices in CHAIN state */
if (w1_reset_bus(sl->master))
goto error;
w1_write_8(sl->master, W1_SKIP_ROM);
w1_write_8(sl->master, W1_42_CHAIN);
w1_write_8(sl->master, W1_42_CHAIN_ON);
w1_write_8(sl->master, W1_42_CHAIN_ON_INV);
msleep(sl->master->pullup_duration);
/* check for acknowledgment */
ack = w1_read_8(sl->master);
if (ack != W1_42_SUCCESS_CONFIRM_BYTE)
goto error;
/* In case the bus fails to send 0xFF, limit */
for (i = 0; i <= 64; i++) {
if (w1_reset_bus(sl->master))
goto error;
w1_write_8(sl->master, W1_42_COND_READ);
w1_read_block(sl->master, (u8 *)&rn, 8);
reg_num = (struct w1_reg_num *) &rn;
if (reg_num->family == W1_42_FINISHED_BYTE)
break;
if (sl->reg_num.id == reg_num->id)
seq = i;
if (w1_reset_bus(sl->master))
goto error;
/* Put the device into chain DONE state */
w1_write_8(sl->master, W1_MATCH_ROM);
w1_write_block(sl->master, (u8 *)&rn, 8);
w1_write_8(sl->master, W1_42_CHAIN);
w1_write_8(sl->master, W1_42_CHAIN_DONE);
w1_write_8(sl->master, W1_42_CHAIN_DONE_INV);
/* check for acknowledgment */
ack = w1_read_8(sl->master);
if (ack != W1_42_SUCCESS_CONFIRM_BYTE)
goto error;
}
/* Exit from CHAIN state */
if (w1_reset_bus(sl->master))
goto error;
w1_write_8(sl->master, W1_SKIP_ROM);
w1_write_8(sl->master, W1_42_CHAIN);
w1_write_8(sl->master, W1_42_CHAIN_OFF);
w1_write_8(sl->master, W1_42_CHAIN_OFF_INV);
/* check for acknowledgment */
ack = w1_read_8(sl->master);
if (ack != W1_42_SUCCESS_CONFIRM_BYTE)
goto error;
mutex_unlock(&sl->master->bus_mutex);
c -= snprintf(buf + PAGE_SIZE - c, c, "%d\n", seq);
return PAGE_SIZE - c;
error:
mutex_unlock(&sl->master->bus_mutex);
return -EIO;
}
static int __init w1_therm_init(void)
{
int err, i;
for (i = 0; i < ARRAY_SIZE(w1_therm_families); ++i) {
err = w1_register_family(w1_therm_families[i].f);
if (err)
w1_therm_families[i].broken = 1;
}
return 0;
}
static void __exit w1_therm_fini(void)
{
int i;
for (i = 0; i < ARRAY_SIZE(w1_therm_families); ++i)
if (!w1_therm_families[i].broken)
w1_unregister_family(w1_therm_families[i].f);
}
module_init(w1_therm_init);
module_exit(w1_therm_fini);
MODULE_AUTHOR("Evgeniy Polyakov <[email protected]>");
MODULE_DESCRIPTION("Driver for 1-wire Dallas network protocol, temperature family.");
MODULE_LICENSE("GPL");
MODULE_ALIAS("w1-family-" __stringify(W1_THERM_DS18S20));
MODULE_ALIAS("w1-family-" __stringify(W1_THERM_DS1822));
MODULE_ALIAS("w1-family-" __stringify(W1_THERM_DS18B20));
MODULE_ALIAS("w1-family-" __stringify(W1_THERM_DS1825));
MODULE_ALIAS("w1-family-" __stringify(W1_THERM_DS28EA00));
|
// SPDX-License-Identifier: GPL-2.0
/*
* NXP FXLS8962AF/FXLS8964AF Accelerometer SPI Driver
*
* Copyright 2021 Connected Cars A/S
*/
#include <linux/dev_printk.h>
#include <linux/err.h>
#include <linux/module.h>
#include <linux/mod_devicetable.h>
#include <linux/spi/spi.h>
#include <linux/regmap.h>
#include "fxls8962af.h"
static int fxls8962af_probe(struct spi_device *spi)
{
struct regmap *regmap;
regmap = devm_regmap_init_spi(spi, &fxls8962af_spi_regmap_conf);
if (IS_ERR(regmap)) {
dev_err(&spi->dev, "Failed to initialize spi regmap\n");
return PTR_ERR(regmap);
}
return fxls8962af_core_probe(&spi->dev, regmap, spi->irq);
}
static const struct of_device_id fxls8962af_spi_of_match[] = {
{ .compatible = "nxp,fxls8962af" },
{ .compatible = "nxp,fxls8964af" },
{}
};
MODULE_DEVICE_TABLE(of, fxls8962af_spi_of_match);
static const struct spi_device_id fxls8962af_spi_id_table[] = {
{ "fxls8962af", fxls8962af },
{ "fxls8964af", fxls8964af },
{}
};
MODULE_DEVICE_TABLE(spi, fxls8962af_spi_id_table);
static struct spi_driver fxls8962af_driver = {
.driver = {
.name = "fxls8962af_spi",
.pm = pm_ptr(&fxls8962af_pm_ops),
.of_match_table = fxls8962af_spi_of_match,
},
.probe = fxls8962af_probe,
.id_table = fxls8962af_spi_id_table,
};
module_spi_driver(fxls8962af_driver);
MODULE_AUTHOR("Sean Nyekjaer <[email protected]>");
MODULE_DESCRIPTION("NXP FXLS8962AF/FXLS8964AF accelerometer spi driver");
MODULE_LICENSE("GPL v2");
MODULE_IMPORT_NS("IIO_FXLS8962AF");
|
// SPDX-License-Identifier: GPL-2.0-only
/*
* pata_sis.c - SiS ATA driver
*
* (C) 2005 Red Hat
* (C) 2007,2009 Bartlomiej Zolnierkiewicz
*
* Based upon linux/drivers/ide/pci/sis5513.c
* Copyright (C) 1999-2000 Andre Hedrick <[email protected]>
* Copyright (C) 2002 Lionel Bouton <[email protected]>, Maintainer
* Copyright (C) 2003 Vojtech Pavlik <[email protected]>
* SiS Taiwan : for direct support and hardware.
* Daniela Engert : for initial ATA100 advices and numerous others.
* John Fremlin, Manfred Spraul, Dave Morgan, Peter Kjellerstedt :
* for checking code correctness, providing patches.
* Original tests and design on the SiS620 chipset.
* ATA100 tests and design on the SiS735 chipset.
* ATA16/33 support from specs
* ATA133 support for SiS961/962 by L.C. Chang <[email protected]>
*
*
* TODO
* Check MWDMA on drives that don't support MWDMA speed pio cycles ?
* More Testing
*/
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/pci.h>
#include <linux/blkdev.h>
#include <linux/delay.h>
#include <linux/device.h>
#include <scsi/scsi_host.h>
#include <linux/libata.h>
#include <linux/ata.h>
#include "sis.h"
#define DRV_NAME "pata_sis"
#define DRV_VERSION "0.5.2"
struct sis_chipset {
u16 device; /* PCI host ID */
const struct ata_port_info *info; /* Info block */
/* Probably add family, cable detect type etc here to clean
up code later */
};
struct sis_laptop {
u16 device;
u16 subvendor;
u16 subdevice;
};
static const struct sis_laptop sis_laptop[] = {
/* devid, subvendor, subdev */
{ 0x5513, 0x1043, 0x1107 }, /* ASUS A6K */
{ 0x5513, 0x1734, 0x105F }, /* FSC Amilo A1630 */
{ 0x5513, 0x1071, 0x8640 }, /* EasyNote K5305 */
/* end marker */
{ 0, }
};
static int sis_short_ata40(struct pci_dev *dev)
{
const struct sis_laptop *lap = &sis_laptop[0];
while (lap->device) {
if (lap->device == dev->device &&
lap->subvendor == dev->subsystem_vendor &&
lap->subdevice == dev->subsystem_device)
return 1;
lap++;
}
return 0;
}
/**
* sis_old_port_base - return PCI configuration base for dev
* @adev: device
*
* Returns the base of the PCI configuration registers for this port
* number.
*/
static int sis_old_port_base(struct ata_device *adev)
{
return 0x40 + (4 * adev->link->ap->port_no) + (2 * adev->devno);
}
/**
* sis_port_base - return PCI configuration base for dev
* @adev: device
*
* Returns the base of the PCI configuration registers for this port
* number.
*/
static int sis_port_base(struct ata_device *adev)
{
struct ata_port *ap = adev->link->ap;
struct pci_dev *pdev = to_pci_dev(ap->host->dev);
int port = 0x40;
u32 reg54;
/* If bit 30 is set then the registers are mapped at 0x70 not 0x40 */
pci_read_config_dword(pdev, 0x54, ®54);
if (reg54 & 0x40000000)
port = 0x70;
return port + (8 * ap->port_no) + (4 * adev->devno);
}
/**
* sis_133_cable_detect - check for 40/80 pin
* @ap: Port
*
* Perform cable detection for the later UDMA133 capable
* SiS chipset.
*/
static int sis_133_cable_detect(struct ata_port *ap)
{
struct pci_dev *pdev = to_pci_dev(ap->host->dev);
u16 tmp;
/* The top bit of this register is the cable detect bit */
pci_read_config_word(pdev, 0x50 + 2 * ap->port_no, &tmp);
if ((tmp & 0x8000) && !sis_short_ata40(pdev))
return ATA_CBL_PATA40;
return ATA_CBL_PATA80;
}
/**
* sis_66_cable_detect - check for 40/80 pin
* @ap: Port
*
* Perform cable detection on the UDMA66, UDMA100 and early UDMA133
* SiS IDE controllers.
*/
static int sis_66_cable_detect(struct ata_port *ap)
{
struct pci_dev *pdev = to_pci_dev(ap->host->dev);
u8 tmp;
/* Older chips keep cable detect in bits 4/5 of reg 0x48 */
pci_read_config_byte(pdev, 0x48, &tmp);
tmp >>= ap->port_no;
if ((tmp & 0x10) && !sis_short_ata40(pdev))
return ATA_CBL_PATA40;
return ATA_CBL_PATA80;
}
/**
* sis_pre_reset - probe begin
* @link: ATA link
* @deadline: deadline jiffies for the operation
*
* Set up cable type and use generic probe init
*/
static int sis_pre_reset(struct ata_link *link, unsigned long deadline)
{
static const struct pci_bits sis_enable_bits[] = {
{ 0x4aU, 1U, 0x02UL, 0x02UL }, /* port 0 */
{ 0x4aU, 1U, 0x04UL, 0x04UL }, /* port 1 */
};
struct ata_port *ap = link->ap;
struct pci_dev *pdev = to_pci_dev(ap->host->dev);
if (!pci_test_config_bits(pdev, &sis_enable_bits[ap->port_no]))
return -ENOENT;
/* Clear the FIFO settings. We can't enable the FIFO until
we know we are poking at a disk */
pci_write_config_byte(pdev, 0x4B, 0);
return ata_sff_prereset(link, deadline);
}
/**
* sis_set_fifo - Set RWP fifo bits for this device
* @ap: Port
* @adev: Device
*
* SIS chipsets implement prefetch/postwrite bits for each device
* on both channels. This functionality is not ATAPI compatible and
* must be configured according to the class of device present
*/
static void sis_set_fifo(struct ata_port *ap, struct ata_device *adev)
{
struct pci_dev *pdev = to_pci_dev(ap->host->dev);
u8 fifoctrl;
u8 mask = 0x11;
mask <<= (2 * ap->port_no);
mask <<= adev->devno;
/* This holds various bits including the FIFO control */
pci_read_config_byte(pdev, 0x4B, &fifoctrl);
fifoctrl &= ~mask;
/* Enable for ATA (disk) only */
if (adev->class == ATA_DEV_ATA)
fifoctrl |= mask;
pci_write_config_byte(pdev, 0x4B, fifoctrl);
}
/**
* sis_old_set_piomode - Initialize host controller PATA PIO timings
* @ap: Port whose timings we are configuring
* @adev: Device we are configuring for.
*
* Set PIO mode for device, in host controller PCI config space. This
* function handles PIO set up for all chips that are pre ATA100 and
* also early ATA100 devices.
*
* LOCKING:
* None (inherited from caller).
*/
static void sis_old_set_piomode (struct ata_port *ap, struct ata_device *adev)
{
struct pci_dev *pdev = to_pci_dev(ap->host->dev);
int port = sis_old_port_base(adev);
u8 t1, t2;
int speed = adev->pio_mode - XFER_PIO_0;
static const u8 active[] = { 0x00, 0x07, 0x04, 0x03, 0x01 };
static const u8 recovery[] = { 0x00, 0x06, 0x04, 0x03, 0x03 };
sis_set_fifo(ap, adev);
pci_read_config_byte(pdev, port, &t1);
pci_read_config_byte(pdev, port + 1, &t2);
t1 &= ~0x0F; /* Clear active/recovery timings */
t2 &= ~0x07;
t1 |= active[speed];
t2 |= recovery[speed];
pci_write_config_byte(pdev, port, t1);
pci_write_config_byte(pdev, port + 1, t2);
}
/**
* sis_100_set_piomode - Initialize host controller PATA PIO timings
* @ap: Port whose timings we are configuring
* @adev: Device we are configuring for.
*
* Set PIO mode for device, in host controller PCI config space. This
* function handles PIO set up for ATA100 devices and early ATA133.
*
* LOCKING:
* None (inherited from caller).
*/
static void sis_100_set_piomode (struct ata_port *ap, struct ata_device *adev)
{
struct pci_dev *pdev = to_pci_dev(ap->host->dev);
int port = sis_old_port_base(adev);
int speed = adev->pio_mode - XFER_PIO_0;
static const u8 actrec[] = { 0x00, 0x67, 0x44, 0x33, 0x31 };
sis_set_fifo(ap, adev);
pci_write_config_byte(pdev, port, actrec[speed]);
}
/**
* sis_133_set_piomode - Initialize host controller PATA PIO timings
* @ap: Port whose timings we are configuring
* @adev: Device we are configuring for.
*
* Set PIO mode for device, in host controller PCI config space. This
* function handles PIO set up for the later ATA133 devices.
*
* LOCKING:
* None (inherited from caller).
*/
static void sis_133_set_piomode (struct ata_port *ap, struct ata_device *adev)
{
struct pci_dev *pdev = to_pci_dev(ap->host->dev);
int port;
u32 t1;
int speed = adev->pio_mode - XFER_PIO_0;
static const u32 timing133[] = {
0x28269000, /* Recovery << 24 | Act << 16 | Ini << 12 */
0x0C266000,
0x04263000,
0x0C0A3000,
0x05093000
};
static const u32 timing100[] = {
0x1E1C6000, /* Recovery << 24 | Act << 16 | Ini << 12 */
0x091C4000,
0x031C2000,
0x09072000,
0x04062000
};
sis_set_fifo(ap, adev);
port = sis_port_base(adev);
pci_read_config_dword(pdev, port, &t1);
t1 &= 0xC0C00FFF; /* Mask out timing */
if (t1 & 0x08) /* 100 or 133 ? */
t1 |= timing133[speed];
else
t1 |= timing100[speed];
pci_write_config_byte(pdev, port, t1);
}
/**
* sis_old_set_dmamode - Initialize host controller PATA DMA timings
* @ap: Port whose timings we are configuring
* @adev: Device to program
*
* Set UDMA/MWDMA mode for device, in host controller PCI config space.
* Handles pre UDMA and UDMA33 devices. Supports MWDMA as well unlike
* the old ide/pci driver.
*
* LOCKING:
* None (inherited from caller).
*/
static void sis_old_set_dmamode (struct ata_port *ap, struct ata_device *adev)
{
struct pci_dev *pdev = to_pci_dev(ap->host->dev);
int speed = adev->dma_mode - XFER_MW_DMA_0;
int drive_pci = sis_old_port_base(adev);
u16 timing;
static const u16 mwdma_bits[] = { 0x008, 0x302, 0x301 };
static const u16 udma_bits[] = { 0xE000, 0xC000, 0xA000 };
pci_read_config_word(pdev, drive_pci, &timing);
if (adev->dma_mode < XFER_UDMA_0) {
/* bits 3-0 hold recovery timing bits 8-10 active timing and
the higher bits are dependent on the device */
timing &= ~0x870F;
timing |= mwdma_bits[speed];
} else {
/* Bit 15 is UDMA on/off, bit 13-14 are cycle time */
speed = adev->dma_mode - XFER_UDMA_0;
timing &= ~0x6000;
timing |= udma_bits[speed];
}
pci_write_config_word(pdev, drive_pci, timing);
}
/**
* sis_66_set_dmamode - Initialize host controller PATA DMA timings
* @ap: Port whose timings we are configuring
* @adev: Device to program
*
* Set UDMA/MWDMA mode for device, in host controller PCI config space.
* Handles UDMA66 and early UDMA100 devices. Supports MWDMA as well unlike
* the old ide/pci driver.
*
* LOCKING:
* None (inherited from caller).
*/
static void sis_66_set_dmamode (struct ata_port *ap, struct ata_device *adev)
{
struct pci_dev *pdev = to_pci_dev(ap->host->dev);
int speed = adev->dma_mode - XFER_MW_DMA_0;
int drive_pci = sis_old_port_base(adev);
u16 timing;
/* MWDMA 0-2 and UDMA 0-5 */
static const u16 mwdma_bits[] = { 0x008, 0x302, 0x301 };
static const u16 udma_bits[] = { 0xF000, 0xD000, 0xB000, 0xA000, 0x9000, 0x8000 };
pci_read_config_word(pdev, drive_pci, &timing);
if (adev->dma_mode < XFER_UDMA_0) {
/* bits 3-0 hold recovery timing bits 8-10 active timing and
the higher bits are dependent on the device, bit 15 udma */
timing &= ~0x870F;
timing |= mwdma_bits[speed];
} else {
/* Bit 15 is UDMA on/off, bit 12-14 are cycle time */
speed = adev->dma_mode - XFER_UDMA_0;
timing &= ~0xF000;
timing |= udma_bits[speed];
}
pci_write_config_word(pdev, drive_pci, timing);
}
/**
* sis_100_set_dmamode - Initialize host controller PATA DMA timings
* @ap: Port whose timings we are configuring
* @adev: Device to program
*
* Set UDMA/MWDMA mode for device, in host controller PCI config space.
* Handles UDMA66 and early UDMA100 devices.
*
* LOCKING:
* None (inherited from caller).
*/
static void sis_100_set_dmamode (struct ata_port *ap, struct ata_device *adev)
{
struct pci_dev *pdev = to_pci_dev(ap->host->dev);
int speed = adev->dma_mode - XFER_MW_DMA_0;
int drive_pci = sis_old_port_base(adev);
u8 timing;
static const u8 udma_bits[] = { 0x8B, 0x87, 0x85, 0x83, 0x82, 0x81};
pci_read_config_byte(pdev, drive_pci + 1, &timing);
if (adev->dma_mode < XFER_UDMA_0) {
/* NOT SUPPORTED YET: NEED DATA SHEET. DITTO IN OLD DRIVER */
} else {
/* Bit 7 is UDMA on/off, bit 0-3 are cycle time */
speed = adev->dma_mode - XFER_UDMA_0;
timing &= ~0x8F;
timing |= udma_bits[speed];
}
pci_write_config_byte(pdev, drive_pci + 1, timing);
}
/**
* sis_133_early_set_dmamode - Initialize host controller PATA DMA timings
* @ap: Port whose timings we are configuring
* @adev: Device to program
*
* Set UDMA/MWDMA mode for device, in host controller PCI config space.
* Handles early SiS 961 bridges.
*
* LOCKING:
* None (inherited from caller).
*/
static void sis_133_early_set_dmamode (struct ata_port *ap, struct ata_device *adev)
{
struct pci_dev *pdev = to_pci_dev(ap->host->dev);
int speed = adev->dma_mode - XFER_MW_DMA_0;
int drive_pci = sis_old_port_base(adev);
u8 timing;
/* Low 4 bits are timing */
static const u8 udma_bits[] = { 0x8F, 0x8A, 0x87, 0x85, 0x83, 0x82, 0x81};
pci_read_config_byte(pdev, drive_pci + 1, &timing);
if (adev->dma_mode < XFER_UDMA_0) {
/* NOT SUPPORTED YET: NEED DATA SHEET. DITTO IN OLD DRIVER */
} else {
/* Bit 7 is UDMA on/off, bit 0-3 are cycle time */
speed = adev->dma_mode - XFER_UDMA_0;
timing &= ~0x8F;
timing |= udma_bits[speed];
}
pci_write_config_byte(pdev, drive_pci + 1, timing);
}
/**
* sis_133_set_dmamode - Initialize host controller PATA DMA timings
* @ap: Port whose timings we are configuring
* @adev: Device to program
*
* Set UDMA/MWDMA mode for device, in host controller PCI config space.
*
* LOCKING:
* None (inherited from caller).
*/
static void sis_133_set_dmamode (struct ata_port *ap, struct ata_device *adev)
{
struct pci_dev *pdev = to_pci_dev(ap->host->dev);
int port;
u32 t1;
port = sis_port_base(adev);
pci_read_config_dword(pdev, port, &t1);
if (adev->dma_mode < XFER_UDMA_0) {
/* Recovery << 24 | Act << 16 | Ini << 12, like PIO modes */
static const u32 timing_u100[] = { 0x19154000, 0x06072000, 0x04062000 };
static const u32 timing_u133[] = { 0x221C6000, 0x0C0A3000, 0x05093000 };
int speed = adev->dma_mode - XFER_MW_DMA_0;
t1 &= 0xC0C00FFF;
/* disable UDMA */
t1 &= ~0x00000004;
if (t1 & 0x08)
t1 |= timing_u133[speed];
else
t1 |= timing_u100[speed];
} else {
/* bits 4- cycle time 8 - cvs time */
static const u32 timing_u100[] = { 0x6B0, 0x470, 0x350, 0x140, 0x120, 0x110, 0x000 };
static const u32 timing_u133[] = { 0x9F0, 0x6A0, 0x470, 0x250, 0x230, 0x220, 0x210 };
int speed = adev->dma_mode - XFER_UDMA_0;
t1 &= ~0x00000FF0;
/* enable UDMA */
t1 |= 0x00000004;
if (t1 & 0x08)
t1 |= timing_u133[speed];
else
t1 |= timing_u100[speed];
}
pci_write_config_dword(pdev, port, t1);
}
/**
* sis_133_mode_filter - mode selection filter
* @adev: ATA device
* @mask: received mask to manipulate and pass back
*
* Block UDMA6 on devices that do not support it.
*/
static unsigned int sis_133_mode_filter(struct ata_device *adev, unsigned int mask)
{
struct ata_port *ap = adev->link->ap;
struct pci_dev *pdev = to_pci_dev(ap->host->dev);
int port = sis_port_base(adev);
u32 t1;
pci_read_config_dword(pdev, port, &t1);
/* if ATA133 is disabled, mask it out */
if (!(t1 & 0x08))
mask &= ~(0xC0 << ATA_SHIFT_UDMA);
return mask;
}
static const struct scsi_host_template sis_sht = {
ATA_BMDMA_SHT(DRV_NAME),
};
static struct ata_port_operations sis_133_for_sata_ops = {
.inherits = &ata_bmdma_port_ops,
.set_piomode = sis_133_set_piomode,
.set_dmamode = sis_133_set_dmamode,
.cable_detect = sis_133_cable_detect,
};
static struct ata_port_operations sis_base_ops = {
.inherits = &ata_bmdma_port_ops,
.prereset = sis_pre_reset,
};
static struct ata_port_operations sis_133_ops = {
.inherits = &sis_base_ops,
.set_piomode = sis_133_set_piomode,
.set_dmamode = sis_133_set_dmamode,
.cable_detect = sis_133_cable_detect,
.mode_filter = sis_133_mode_filter,
};
static struct ata_port_operations sis_133_early_ops = {
.inherits = &sis_base_ops,
.set_piomode = sis_100_set_piomode,
.set_dmamode = sis_133_early_set_dmamode,
.cable_detect = sis_66_cable_detect,
};
static struct ata_port_operations sis_100_ops = {
.inherits = &sis_base_ops,
.set_piomode = sis_100_set_piomode,
.set_dmamode = sis_100_set_dmamode,
.cable_detect = sis_66_cable_detect,
};
static struct ata_port_operations sis_66_ops = {
.inherits = &sis_base_ops,
.set_piomode = sis_old_set_piomode,
.set_dmamode = sis_66_set_dmamode,
.cable_detect = sis_66_cable_detect,
};
static struct ata_port_operations sis_old_ops = {
.inherits = &sis_base_ops,
.set_piomode = sis_old_set_piomode,
.set_dmamode = sis_old_set_dmamode,
.cable_detect = ata_cable_40wire,
};
static const struct ata_port_info sis_info = {
.flags = ATA_FLAG_SLAVE_POSS,
.pio_mask = ATA_PIO4,
.mwdma_mask = ATA_MWDMA2,
/* No UDMA */
.port_ops = &sis_old_ops,
};
static const struct ata_port_info sis_info33 = {
.flags = ATA_FLAG_SLAVE_POSS,
.pio_mask = ATA_PIO4,
.mwdma_mask = ATA_MWDMA2,
.udma_mask = ATA_UDMA2,
.port_ops = &sis_old_ops,
};
static const struct ata_port_info sis_info66 = {
.flags = ATA_FLAG_SLAVE_POSS,
.pio_mask = ATA_PIO4,
/* No MWDMA */
.udma_mask = ATA_UDMA4,
.port_ops = &sis_66_ops,
};
static const struct ata_port_info sis_info100 = {
.flags = ATA_FLAG_SLAVE_POSS,
.pio_mask = ATA_PIO4,
/* No MWDMA */
.udma_mask = ATA_UDMA5,
.port_ops = &sis_100_ops,
};
static const struct ata_port_info sis_info100_early = {
.flags = ATA_FLAG_SLAVE_POSS,
.pio_mask = ATA_PIO4,
/* No MWDMA */
.udma_mask = ATA_UDMA5,
.port_ops = &sis_66_ops,
};
static const struct ata_port_info sis_info133 = {
.flags = ATA_FLAG_SLAVE_POSS,
.pio_mask = ATA_PIO4,
.mwdma_mask = ATA_MWDMA2,
.udma_mask = ATA_UDMA6,
.port_ops = &sis_133_ops,
};
const struct ata_port_info sis_info133_for_sata = {
.flags = ATA_FLAG_SLAVE_POSS,
.pio_mask = ATA_PIO4,
/* No MWDMA */
.udma_mask = ATA_UDMA6,
.port_ops = &sis_133_for_sata_ops,
};
static const struct ata_port_info sis_info133_early = {
.flags = ATA_FLAG_SLAVE_POSS,
.pio_mask = ATA_PIO4,
/* No MWDMA */
.udma_mask = ATA_UDMA6,
.port_ops = &sis_133_early_ops,
};
/* Privately shared with the SiS180 SATA driver, not for use elsewhere */
EXPORT_SYMBOL_GPL(sis_info133_for_sata);
static void sis_fixup(struct pci_dev *pdev, struct sis_chipset *sis)
{
u16 regw;
u8 reg;
if (sis->info == &sis_info133) {
pci_read_config_word(pdev, 0x50, ®w);
if (regw & 0x08)
pci_write_config_word(pdev, 0x50, regw & ~0x08);
pci_read_config_word(pdev, 0x52, ®w);
if (regw & 0x08)
pci_write_config_word(pdev, 0x52, regw & ~0x08);
return;
}
if (sis->info == &sis_info133_early || sis->info == &sis_info100) {
/* Fix up latency */
pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0x80);
/* Set compatibility bit */
pci_read_config_byte(pdev, 0x49, ®);
if (!(reg & 0x01))
pci_write_config_byte(pdev, 0x49, reg | 0x01);
return;
}
if (sis->info == &sis_info66 || sis->info == &sis_info100_early) {
/* Fix up latency */
pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0x80);
/* Set compatibility bit */
pci_read_config_byte(pdev, 0x52, ®);
if (!(reg & 0x04))
pci_write_config_byte(pdev, 0x52, reg | 0x04);
return;
}
if (sis->info == &sis_info33) {
pci_read_config_byte(pdev, PCI_CLASS_PROG, ®);
if (( reg & 0x0F ) != 0x00)
pci_write_config_byte(pdev, PCI_CLASS_PROG, reg & 0xF0);
/* Fall through to ATA16 fixup below */
}
if (sis->info == &sis_info || sis->info == &sis_info33) {
/* force per drive recovery and active timings
needed on ATA_33 and below chips */
pci_read_config_byte(pdev, 0x52, ®);
if (!(reg & 0x08))
pci_write_config_byte(pdev, 0x52, reg|0x08);
return;
}
BUG();
}
/**
* sis_init_one - Register SiS ATA PCI device with kernel services
* @pdev: PCI device to register
* @ent: Entry in sis_pci_tbl matching with @pdev
*
* Called from kernel PCI layer. We probe for combined mode (sigh),
* and then hand over control to libata, for it to do the rest.
*
* LOCKING:
* Inherited from PCI layer (may sleep).
*
* RETURNS:
* Zero on success, or -ERRNO value.
*/
static int sis_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
{
const struct ata_port_info *ppi[] = { NULL, NULL };
struct pci_dev *host = NULL;
struct sis_chipset *chipset = NULL;
struct sis_chipset *sets;
int rc;
static struct sis_chipset sis_chipsets[] = {
{ 0x0968, &sis_info133 },
{ 0x0966, &sis_info133 },
{ 0x0965, &sis_info133 },
{ 0x0745, &sis_info100 },
{ 0x0735, &sis_info100 },
{ 0x0733, &sis_info100 },
{ 0x0635, &sis_info100 },
{ 0x0633, &sis_info100 },
{ 0x0730, &sis_info100_early }, /* 100 with ATA 66 layout */
{ 0x0550, &sis_info100_early }, /* 100 with ATA 66 layout */
{ 0x0640, &sis_info66 },
{ 0x0630, &sis_info66 },
{ 0x0620, &sis_info66 },
{ 0x0540, &sis_info66 },
{ 0x0530, &sis_info66 },
{ 0x5600, &sis_info33 },
{ 0x5598, &sis_info33 },
{ 0x5597, &sis_info33 },
{ 0x5591, &sis_info33 },
{ 0x5582, &sis_info33 },
{ 0x5581, &sis_info33 },
{ 0x5596, &sis_info },
{ 0x5571, &sis_info },
{ 0x5517, &sis_info },
{ 0x5511, &sis_info },
{0}
};
static struct sis_chipset sis133_early = {
0x0, &sis_info133_early
};
static struct sis_chipset sis133 = {
0x0, &sis_info133
};
static struct sis_chipset sis100_early = {
0x0, &sis_info100_early
};
static struct sis_chipset sis100 = {
0x0, &sis_info100
};
ata_print_version_once(&pdev->dev, DRV_VERSION);
rc = pcim_enable_device(pdev);
if (rc)
return rc;
/* We have to find the bridge first */
for (sets = &sis_chipsets[0]; sets->device; sets++) {
host = pci_get_device(PCI_VENDOR_ID_SI, sets->device, NULL);
if (host != NULL) {
chipset = sets; /* Match found */
if (sets->device == 0x630) { /* SIS630 */
if (host->revision >= 0x30) /* 630 ET */
chipset = &sis100_early;
}
break;
}
}
/* Look for concealed bridges */
if (chipset == NULL) {
/* Second check */
u32 idemisc;
u16 trueid;
/* Disable ID masking and register remapping then
see what the real ID is */
pci_read_config_dword(pdev, 0x54, &idemisc);
pci_write_config_dword(pdev, 0x54, idemisc & 0x7fffffff);
pci_read_config_word(pdev, PCI_DEVICE_ID, &trueid);
pci_write_config_dword(pdev, 0x54, idemisc);
switch(trueid) {
case 0x5518: /* SIS 962/963 */
dev_info(&pdev->dev,
"SiS 962/963 MuTIOL IDE UDMA133 controller\n");
chipset = &sis133;
if ((idemisc & 0x40000000) == 0) {
pci_write_config_dword(pdev, 0x54, idemisc | 0x40000000);
dev_info(&pdev->dev,
"Switching to 5513 register mapping\n");
}
break;
case 0x0180: /* SIS 965/965L */
chipset = &sis133;
break;
case 0x1180: /* SIS 966/966L */
chipset = &sis133;
break;
}
}
/* Further check */
if (chipset == NULL) {
struct pci_dev *lpc_bridge;
u16 trueid;
u8 prefctl;
u8 idecfg;
/* Try the second unmasking technique */
pci_read_config_byte(pdev, 0x4a, &idecfg);
pci_write_config_byte(pdev, 0x4a, idecfg | 0x10);
pci_read_config_word(pdev, PCI_DEVICE_ID, &trueid);
pci_write_config_byte(pdev, 0x4a, idecfg);
switch(trueid) {
case 0x5517:
lpc_bridge = pci_get_slot(pdev->bus, 0x10); /* Bus 0 Dev 2 Fn 0 */
if (lpc_bridge == NULL)
break;
pci_read_config_byte(pdev, 0x49, &prefctl);
pci_dev_put(lpc_bridge);
if (lpc_bridge->revision == 0x10 && (prefctl & 0x80)) {
chipset = &sis133_early;
break;
}
chipset = &sis100;
break;
}
}
pci_dev_put(host);
/* No chipset info, no support */
if (chipset == NULL)
return -ENODEV;
ppi[0] = chipset->info;
sis_fixup(pdev, chipset);
return ata_pci_bmdma_init_one(pdev, ppi, &sis_sht, chipset, 0);
}
#ifdef CONFIG_PM_SLEEP
static int sis_reinit_one(struct pci_dev *pdev)
{
struct ata_host *host = pci_get_drvdata(pdev);
int rc;
rc = ata_pci_device_do_resume(pdev);
if (rc)
return rc;
sis_fixup(pdev, host->private_data);
ata_host_resume(host);
return 0;
}
#endif
static const struct pci_device_id sis_pci_tbl[] = {
{ PCI_VDEVICE(SI, 0x5513), }, /* SiS 5513 */
{ PCI_VDEVICE(SI, 0x5518), }, /* SiS 5518 */
{ PCI_VDEVICE(SI, 0x1180), }, /* SiS 1180 */
{ }
};
static struct pci_driver sis_pci_driver = {
.name = DRV_NAME,
.id_table = sis_pci_tbl,
.probe = sis_init_one,
.remove = ata_pci_remove_one,
#ifdef CONFIG_PM_SLEEP
.suspend = ata_pci_device_suspend,
.resume = sis_reinit_one,
#endif
};
module_pci_driver(sis_pci_driver);
MODULE_AUTHOR("Alan Cox");
MODULE_DESCRIPTION("SCSI low-level driver for SiS ATA");
MODULE_LICENSE("GPL");
MODULE_DEVICE_TABLE(pci, sis_pci_tbl);
MODULE_VERSION(DRV_VERSION);
|
/* SPDX-License-Identifier: GPL-2.0 */
#ifndef __ASM_SH7757_H__
#define __ASM_SH7757_H__
enum {
/* PTA */
GPIO_PTA0, GPIO_PTA1, GPIO_PTA2, GPIO_PTA3,
GPIO_PTA4, GPIO_PTA5, GPIO_PTA6, GPIO_PTA7,
/* PTB */
GPIO_PTB0, GPIO_PTB1, GPIO_PTB2, GPIO_PTB3,
GPIO_PTB4, GPIO_PTB5, GPIO_PTB6, GPIO_PTB7,
/* PTC */
GPIO_PTC0, GPIO_PTC1, GPIO_PTC2, GPIO_PTC3,
GPIO_PTC4, GPIO_PTC5, GPIO_PTC6, GPIO_PTC7,
/* PTD */
GPIO_PTD0, GPIO_PTD1, GPIO_PTD2, GPIO_PTD3,
GPIO_PTD4, GPIO_PTD5, GPIO_PTD6, GPIO_PTD7,
/* PTE */
GPIO_PTE0, GPIO_PTE1, GPIO_PTE2, GPIO_PTE3,
GPIO_PTE4, GPIO_PTE5, GPIO_PTE6, GPIO_PTE7,
/* PTF */
GPIO_PTF0, GPIO_PTF1, GPIO_PTF2, GPIO_PTF3,
GPIO_PTF4, GPIO_PTF5, GPIO_PTF6, GPIO_PTF7,
/* PTG */
GPIO_PTG0, GPIO_PTG1, GPIO_PTG2, GPIO_PTG3,
GPIO_PTG4, GPIO_PTG5, GPIO_PTG6, GPIO_PTG7,
/* PTH */
GPIO_PTH0, GPIO_PTH1, GPIO_PTH2, GPIO_PTH3,
GPIO_PTH4, GPIO_PTH5, GPIO_PTH6, GPIO_PTH7,
/* PTI */
GPIO_PTI0, GPIO_PTI1, GPIO_PTI2, GPIO_PTI3,
GPIO_PTI4, GPIO_PTI5, GPIO_PTI6, GPIO_PTI7,
/* PTJ */
GPIO_PTJ0, GPIO_PTJ1, GPIO_PTJ2, GPIO_PTJ3,
GPIO_PTJ4, GPIO_PTJ5, GPIO_PTJ6,
/* PTK */
GPIO_PTK0, GPIO_PTK1, GPIO_PTK2, GPIO_PTK3,
GPIO_PTK4, GPIO_PTK5, GPIO_PTK6, GPIO_PTK7,
/* PTL */
GPIO_PTL0, GPIO_PTL1, GPIO_PTL2, GPIO_PTL3,
GPIO_PTL4, GPIO_PTL5, GPIO_PTL6,
/* PTM */
GPIO_PTM0, GPIO_PTM1, GPIO_PTM2, GPIO_PTM3,
GPIO_PTM4, GPIO_PTM5, GPIO_PTM6, GPIO_PTM7,
/* PTN */
GPIO_PTN0, GPIO_PTN1, GPIO_PTN2, GPIO_PTN3,
GPIO_PTN4, GPIO_PTN5, GPIO_PTN6,
/* PTO */
GPIO_PTO0, GPIO_PTO1, GPIO_PTO2, GPIO_PTO3,
GPIO_PTO4, GPIO_PTO5, GPIO_PTO6, GPIO_PTO7,
/* PTP */
GPIO_PTP0, GPIO_PTP1, GPIO_PTP2, GPIO_PTP3,
GPIO_PTP4, GPIO_PTP5, GPIO_PTP6, GPIO_PTP7,
/* PTQ */
GPIO_PTQ0, GPIO_PTQ1, GPIO_PTQ2, GPIO_PTQ3,
GPIO_PTQ4, GPIO_PTQ5, GPIO_PTQ6,
/* PTR */
GPIO_PTR0, GPIO_PTR1, GPIO_PTR2, GPIO_PTR3,
GPIO_PTR4, GPIO_PTR5, GPIO_PTR6, GPIO_PTR7,
/* PTS */
GPIO_PTS0, GPIO_PTS1, GPIO_PTS2, GPIO_PTS3,
GPIO_PTS4, GPIO_PTS5, GPIO_PTS6, GPIO_PTS7,
/* PTT */
GPIO_PTT0, GPIO_PTT1, GPIO_PTT2, GPIO_PTT3,
GPIO_PTT4, GPIO_PTT5, GPIO_PTT6, GPIO_PTT7,
/* PTU */
GPIO_PTU0, GPIO_PTU1, GPIO_PTU2, GPIO_PTU3,
GPIO_PTU4, GPIO_PTU5, GPIO_PTU6, GPIO_PTU7,
/* PTV */
GPIO_PTV0, GPIO_PTV1, GPIO_PTV2, GPIO_PTV3,
GPIO_PTV4, GPIO_PTV5, GPIO_PTV6, GPIO_PTV7,
/* PTW */
GPIO_PTW0, GPIO_PTW1, GPIO_PTW2, GPIO_PTW3,
GPIO_PTW4, GPIO_PTW5, GPIO_PTW6, GPIO_PTW7,
/* PTX */
GPIO_PTX0, GPIO_PTX1, GPIO_PTX2, GPIO_PTX3,
GPIO_PTX4, GPIO_PTX5, GPIO_PTX6, GPIO_PTX7,
/* PTY */
GPIO_PTY0, GPIO_PTY1, GPIO_PTY2, GPIO_PTY3,
GPIO_PTY4, GPIO_PTY5, GPIO_PTY6, GPIO_PTY7,
/* PTZ */
GPIO_PTZ0, GPIO_PTZ1, GPIO_PTZ2, GPIO_PTZ3,
GPIO_PTZ4, GPIO_PTZ5, GPIO_PTZ6, GPIO_PTZ7,
/* PTA (mobule: LBSC, RGMII) */
GPIO_FN_BS, GPIO_FN_RDWR, GPIO_FN_WE1, GPIO_FN_RDY,
GPIO_FN_ET0_MDC, GPIO_FN_ET0_MDIO,
GPIO_FN_ET1_MDC, GPIO_FN_ET1_MDIO,
/* PTB (mobule: INTC, ONFI, TMU) */
GPIO_FN_IRQ15, GPIO_FN_IRQ14, GPIO_FN_IRQ13, GPIO_FN_IRQ12,
GPIO_FN_IRQ11, GPIO_FN_IRQ10, GPIO_FN_IRQ9, GPIO_FN_IRQ8,
GPIO_FN_ON_NRE, GPIO_FN_ON_NWE, GPIO_FN_ON_NWP, GPIO_FN_ON_NCE0,
GPIO_FN_ON_R_B0, GPIO_FN_ON_ALE, GPIO_FN_ON_CLE,
GPIO_FN_TCLK,
/* PTC (mobule: IRQ, PWMU) */
GPIO_FN_IRQ7, GPIO_FN_IRQ6, GPIO_FN_IRQ5, GPIO_FN_IRQ4,
GPIO_FN_IRQ3, GPIO_FN_IRQ2, GPIO_FN_IRQ1, GPIO_FN_IRQ0,
GPIO_FN_PWMU0, GPIO_FN_PWMU1, GPIO_FN_PWMU2, GPIO_FN_PWMU3,
GPIO_FN_PWMU4, GPIO_FN_PWMU5,
/* PTD (mobule: SPI0, DMAC) */
GPIO_FN_SP0_MOSI, GPIO_FN_SP0_MISO, GPIO_FN_SP0_SCK,
GPIO_FN_SP0_SCK_FB, GPIO_FN_SP0_SS0, GPIO_FN_SP0_SS1,
GPIO_FN_SP0_SS2, GPIO_FN_SP0_SS3, GPIO_FN_DREQ0,
GPIO_FN_DACK0, GPIO_FN_TEND0,
/* PTE (mobule: RMII) */
GPIO_FN_RMII0_CRS_DV, GPIO_FN_RMII0_TXD1, GPIO_FN_RMII0_TXD0,
GPIO_FN_RMII0_TXEN, GPIO_FN_RMII0_REFCLK, GPIO_FN_RMII0_RXD1,
GPIO_FN_RMII0_RXD0, GPIO_FN_RMII0_RX_ER,
/* PTF (mobule: RMII, SerMux) */
GPIO_FN_RMII1_CRS_DV, GPIO_FN_RMII1_TXD1, GPIO_FN_RMII1_TXD0,
GPIO_FN_RMII1_TXEN, GPIO_FN_RMII1_REFCLK, GPIO_FN_RMII1_RXD1,
GPIO_FN_RMII1_RXD0, GPIO_FN_RMII1_RX_ER, GPIO_FN_RAC_RI,
/* PTG (mobule: system, LBSC, LPC, WDT, LPC, eMMC) */
GPIO_FN_BOOTFMS, GPIO_FN_BOOTWP,
GPIO_FN_A25, GPIO_FN_A24, GPIO_FN_SERIRQ, GPIO_FN_WDTOVF,
GPIO_FN_LPCPD, GPIO_FN_LDRQ, GPIO_FN_MMCCLK, GPIO_FN_MMCCMD,
/* PTH (mobule: SPI1, LPC, DMAC, ADC) */
GPIO_FN_SP1_MOSI, GPIO_FN_SP1_MISO,
GPIO_FN_SP1_SCK, GPIO_FN_SP1_SCK_FB,
GPIO_FN_SP1_SS0, GPIO_FN_SP1_SS1,
GPIO_FN_WP, GPIO_FN_FMS0, GPIO_FN_TEND1, GPIO_FN_DREQ1,
GPIO_FN_DACK1, GPIO_FN_ADTRG1, GPIO_FN_ADTRG0,
/* PTI (mobule: LBSC, SDHI) */
GPIO_FN_D15, GPIO_FN_D14, GPIO_FN_D13, GPIO_FN_D12,
GPIO_FN_D11, GPIO_FN_D10, GPIO_FN_D9, GPIO_FN_D8,
GPIO_FN_SD_WP, GPIO_FN_SD_CD, GPIO_FN_SD_CLK, GPIO_FN_SD_CMD,
GPIO_FN_SD_D3, GPIO_FN_SD_D2, GPIO_FN_SD_D1, GPIO_FN_SD_D0,
/* PTJ (mobule: SCIF234) */
GPIO_FN_RTS3, GPIO_FN_CTS3, GPIO_FN_TXD3, GPIO_FN_RXD3,
GPIO_FN_RTS4, GPIO_FN_RXD4, GPIO_FN_TXD4,
/* PTK (mobule: SERMUX, LBSC, SCIF) */
GPIO_FN_COM2_TXD, GPIO_FN_COM2_RXD, GPIO_FN_COM2_RTS,
GPIO_FN_COM2_CTS, GPIO_FN_COM2_DTR, GPIO_FN_COM2_DSR,
GPIO_FN_COM2_DCD, GPIO_FN_CLKOUT,
GPIO_FN_SCK2, GPIO_FN_SCK4, GPIO_FN_SCK3,
/* PTL (mobule: SERMUX, SCIF, LBSC, AUD) */
GPIO_FN_RAC_RXD, GPIO_FN_RAC_RTS, GPIO_FN_RAC_CTS,
GPIO_FN_RAC_DTR, GPIO_FN_RAC_DSR, GPIO_FN_RAC_DCD,
GPIO_FN_RAC_TXD, GPIO_FN_RXD2, GPIO_FN_CS5,
GPIO_FN_CS6, GPIO_FN_AUDSYNC, GPIO_FN_AUDCK,
GPIO_FN_TXD2,
/* PTM (mobule: LBSC, IIC) */
GPIO_FN_CS4, GPIO_FN_RD, GPIO_FN_WE0, GPIO_FN_CS0,
GPIO_FN_SDA6, GPIO_FN_SCL6, GPIO_FN_SDA7, GPIO_FN_SCL7,
/* PTN (mobule: USB, JMC, SGPIO, WDT) */
GPIO_FN_VBUS_EN, GPIO_FN_VBUS_OC, GPIO_FN_JMCTCK,
GPIO_FN_JMCTMS, GPIO_FN_JMCTDO, GPIO_FN_JMCTDI,
GPIO_FN_JMCTRST,
GPIO_FN_SGPIO1_CLK, GPIO_FN_SGPIO1_LOAD, GPIO_FN_SGPIO1_DI,
GPIO_FN_SGPIO1_DO, GPIO_FN_SUB_CLKIN,
/* PTO (mobule: SGPIO, SerMux) */
GPIO_FN_SGPIO0_CLK, GPIO_FN_SGPIO0_LOAD, GPIO_FN_SGPIO0_DI,
GPIO_FN_SGPIO0_DO, GPIO_FN_SGPIO2_CLK, GPIO_FN_SGPIO2_LOAD,
GPIO_FN_SGPIO2_DI, GPIO_FN_SGPIO2_DO, GPIO_FN_COM1_TXD,
GPIO_FN_COM1_RXD, GPIO_FN_COM1_RTS, GPIO_FN_COM1_CTS,
/* PTQ (mobule: LPC) */
GPIO_FN_LAD3, GPIO_FN_LAD2, GPIO_FN_LAD1, GPIO_FN_LAD0,
GPIO_FN_LFRAME, GPIO_FN_LRESET, GPIO_FN_LCLK,
/* PTR (mobule: GRA, IIC) */
GPIO_FN_DDC3, GPIO_FN_DDC2, GPIO_FN_SDA2, GPIO_FN_SCL2,
GPIO_FN_SDA1, GPIO_FN_SCL1, GPIO_FN_SDA0, GPIO_FN_SCL0,
GPIO_FN_SDA8, GPIO_FN_SCL8,
/* PTS (mobule: GRA, IIC) */
GPIO_FN_DDC1, GPIO_FN_DDC0, GPIO_FN_SDA5, GPIO_FN_SCL5,
GPIO_FN_SDA4, GPIO_FN_SCL4, GPIO_FN_SDA3, GPIO_FN_SCL3,
GPIO_FN_SDA9, GPIO_FN_SCL9,
/* PTT (mobule: PWMX, AUD) */
GPIO_FN_PWMX7, GPIO_FN_PWMX6, GPIO_FN_PWMX5, GPIO_FN_PWMX4,
GPIO_FN_PWMX3, GPIO_FN_PWMX2, GPIO_FN_PWMX1, GPIO_FN_PWMX0,
GPIO_FN_AUDATA3, GPIO_FN_AUDATA2, GPIO_FN_AUDATA1,
GPIO_FN_AUDATA0, GPIO_FN_STATUS1, GPIO_FN_STATUS0,
/* PTU (mobule: LPC, APM) */
GPIO_FN_LGPIO7, GPIO_FN_LGPIO6, GPIO_FN_LGPIO5, GPIO_FN_LGPIO4,
GPIO_FN_LGPIO3, GPIO_FN_LGPIO2, GPIO_FN_LGPIO1, GPIO_FN_LGPIO0,
GPIO_FN_APMONCTL_O, GPIO_FN_APMPWBTOUT_O, GPIO_FN_APMSCI_O,
GPIO_FN_APMVDDON, GPIO_FN_APMSLPBTN, GPIO_FN_APMPWRBTN,
GPIO_FN_APMS5N, GPIO_FN_APMS3N,
/* PTV (mobule: LBSC, SerMux, R-SPI, EVC, GRA) */
GPIO_FN_A23, GPIO_FN_A22, GPIO_FN_A21, GPIO_FN_A20,
GPIO_FN_A19, GPIO_FN_A18, GPIO_FN_A17, GPIO_FN_A16,
GPIO_FN_COM2_RI, GPIO_FN_R_SPI_MOSI, GPIO_FN_R_SPI_MISO,
GPIO_FN_R_SPI_RSPCK, GPIO_FN_R_SPI_SSL0, GPIO_FN_R_SPI_SSL1,
GPIO_FN_EVENT7, GPIO_FN_EVENT6, GPIO_FN_VBIOS_DI,
GPIO_FN_VBIOS_DO, GPIO_FN_VBIOS_CLK, GPIO_FN_VBIOS_CS,
/* PTW (mobule: LBSC, EVC, SCIF) */
GPIO_FN_A15, GPIO_FN_A14, GPIO_FN_A13, GPIO_FN_A12,
GPIO_FN_A11, GPIO_FN_A10, GPIO_FN_A9, GPIO_FN_A8,
GPIO_FN_EVENT5, GPIO_FN_EVENT4, GPIO_FN_EVENT3, GPIO_FN_EVENT2,
GPIO_FN_EVENT1, GPIO_FN_EVENT0, GPIO_FN_CTS4, GPIO_FN_CTS2,
/* PTX (mobule: LBSC, SCIF, SIM) */
GPIO_FN_A7, GPIO_FN_A6, GPIO_FN_A5, GPIO_FN_A4,
GPIO_FN_A3, GPIO_FN_A2, GPIO_FN_A1, GPIO_FN_A0,
GPIO_FN_RTS2, GPIO_FN_SIM_D, GPIO_FN_SIM_CLK, GPIO_FN_SIM_RST,
/* PTY (mobule: LBSC) */
GPIO_FN_D7, GPIO_FN_D6, GPIO_FN_D5, GPIO_FN_D4,
GPIO_FN_D3, GPIO_FN_D2, GPIO_FN_D1, GPIO_FN_D0,
/* PTZ (mobule: eMMC, ONFI) */
GPIO_FN_MMCDAT7, GPIO_FN_MMCDAT6, GPIO_FN_MMCDAT5,
GPIO_FN_MMCDAT4, GPIO_FN_MMCDAT3, GPIO_FN_MMCDAT2,
GPIO_FN_MMCDAT1, GPIO_FN_MMCDAT0,
GPIO_FN_ON_DQ7, GPIO_FN_ON_DQ6, GPIO_FN_ON_DQ5, GPIO_FN_ON_DQ4,
GPIO_FN_ON_DQ3, GPIO_FN_ON_DQ2, GPIO_FN_ON_DQ1, GPIO_FN_ON_DQ0,
};
enum {
SHDMA_SLAVE_INVALID,
SHDMA_SLAVE_SDHI_TX,
SHDMA_SLAVE_SDHI_RX,
SHDMA_SLAVE_MMCIF_TX,
SHDMA_SLAVE_MMCIF_RX,
SHDMA_SLAVE_SCIF2_TX,
SHDMA_SLAVE_SCIF2_RX,
SHDMA_SLAVE_SCIF3_TX,
SHDMA_SLAVE_SCIF3_RX,
SHDMA_SLAVE_SCIF4_TX,
SHDMA_SLAVE_SCIF4_RX,
SHDMA_SLAVE_RIIC0_TX,
SHDMA_SLAVE_RIIC0_RX,
SHDMA_SLAVE_RIIC1_TX,
SHDMA_SLAVE_RIIC1_RX,
SHDMA_SLAVE_RIIC2_TX,
SHDMA_SLAVE_RIIC2_RX,
SHDMA_SLAVE_RIIC3_TX,
SHDMA_SLAVE_RIIC3_RX,
SHDMA_SLAVE_RIIC4_TX,
SHDMA_SLAVE_RIIC4_RX,
SHDMA_SLAVE_RIIC5_TX,
SHDMA_SLAVE_RIIC5_RX,
SHDMA_SLAVE_RIIC6_TX,
SHDMA_SLAVE_RIIC6_RX,
SHDMA_SLAVE_RIIC7_TX,
SHDMA_SLAVE_RIIC7_RX,
SHDMA_SLAVE_RIIC8_TX,
SHDMA_SLAVE_RIIC8_RX,
SHDMA_SLAVE_RIIC9_TX,
SHDMA_SLAVE_RIIC9_RX,
SHDMA_SLAVE_RSPI_TX,
SHDMA_SLAVE_RSPI_RX,
};
#endif /* __ASM_SH7757_H__ */
|
// SPDX-License-Identifier: GPL-2.0
/*
* MediaTek Pinctrl Moore Driver, which implement the generic dt-binding
* pinctrl-bindings.txt for MediaTek SoC.
*
* Copyright (C) 2017-2018 MediaTek Inc.
* Author: Sean Wang <[email protected]>
*
*/
#include <dt-bindings/pinctrl/mt65xx.h>
#include <linux/gpio/driver.h>
#include <linux/pinctrl/consumer.h>
#include "pinctrl-moore.h"
#define PINCTRL_PINCTRL_DEV KBUILD_MODNAME
/* Custom pinconf parameters */
#define MTK_PIN_CONFIG_TDSEL (PIN_CONFIG_END + 1)
#define MTK_PIN_CONFIG_RDSEL (PIN_CONFIG_END + 2)
#define MTK_PIN_CONFIG_PU_ADV (PIN_CONFIG_END + 3)
#define MTK_PIN_CONFIG_PD_ADV (PIN_CONFIG_END + 4)
static const struct pinconf_generic_params mtk_custom_bindings[] = {
{"mediatek,tdsel", MTK_PIN_CONFIG_TDSEL, 0},
{"mediatek,rdsel", MTK_PIN_CONFIG_RDSEL, 0},
{"mediatek,pull-up-adv", MTK_PIN_CONFIG_PU_ADV, 1},
{"mediatek,pull-down-adv", MTK_PIN_CONFIG_PD_ADV, 1},
};
#ifdef CONFIG_DEBUG_FS
static const struct pin_config_item mtk_conf_items[] = {
PCONFDUMP(MTK_PIN_CONFIG_TDSEL, "tdsel", NULL, true),
PCONFDUMP(MTK_PIN_CONFIG_RDSEL, "rdsel", NULL, true),
PCONFDUMP(MTK_PIN_CONFIG_PU_ADV, "pu-adv", NULL, true),
PCONFDUMP(MTK_PIN_CONFIG_PD_ADV, "pd-adv", NULL, true),
};
#endif
static int mtk_pinmux_set_mux(struct pinctrl_dev *pctldev,
unsigned int selector, unsigned int group)
{
struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
struct function_desc *func;
struct group_desc *grp;
int i, err;
func = pinmux_generic_get_function(pctldev, selector);
if (!func)
return -EINVAL;
grp = pinctrl_generic_get_group(pctldev, group);
if (!grp)
return -EINVAL;
dev_dbg(pctldev->dev, "enable function %s group %s\n",
func->func.name, grp->grp.name);
for (i = 0; i < grp->grp.npins; i++) {
const struct mtk_pin_desc *desc;
int *pin_modes = grp->data;
int pin = grp->grp.pins[i];
desc = (const struct mtk_pin_desc *)&hw->soc->pins[pin];
if (!desc->name)
return -ENOTSUPP;
err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_MODE,
pin_modes[i]);
if (err)
return err;
}
return 0;
}
static int mtk_pinmux_gpio_request_enable(struct pinctrl_dev *pctldev,
struct pinctrl_gpio_range *range,
unsigned int pin)
{
struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
const struct mtk_pin_desc *desc;
desc = (const struct mtk_pin_desc *)&hw->soc->pins[pin];
if (!desc->name)
return -ENOTSUPP;
return mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_MODE,
hw->soc->gpio_m);
}
static int mtk_pinmux_gpio_set_direction(struct pinctrl_dev *pctldev,
struct pinctrl_gpio_range *range,
unsigned int pin, bool input)
{
struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
const struct mtk_pin_desc *desc;
desc = (const struct mtk_pin_desc *)&hw->soc->pins[pin];
if (!desc->name)
return -ENOTSUPP;
/* hardware would take 0 as input direction */
return mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DIR, !input);
}
static int mtk_pinconf_get(struct pinctrl_dev *pctldev,
unsigned int pin, unsigned long *config)
{
struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
u32 param = pinconf_to_config_param(*config);
int val, val2, err, pullup, reg, ret = 1;
const struct mtk_pin_desc *desc;
desc = (const struct mtk_pin_desc *)&hw->soc->pins[pin];
if (!desc->name)
return -ENOTSUPP;
switch (param) {
case PIN_CONFIG_BIAS_DISABLE:
if (hw->soc->bias_get_combo) {
err = hw->soc->bias_get_combo(hw, desc, &pullup, &ret);
if (err)
return err;
if (ret != MTK_PUPD_SET_R1R0_00 && ret != MTK_DISABLE)
return -EINVAL;
} else if (hw->soc->bias_disable_get) {
err = hw->soc->bias_disable_get(hw, desc, &ret);
if (err)
return err;
} else {
return -ENOTSUPP;
}
break;
case PIN_CONFIG_BIAS_PULL_UP:
if (hw->soc->bias_get_combo) {
err = hw->soc->bias_get_combo(hw, desc, &pullup, &ret);
if (err)
return err;
if (ret == MTK_PUPD_SET_R1R0_00 || ret == MTK_DISABLE)
return -EINVAL;
if (!pullup)
return -EINVAL;
} else if (hw->soc->bias_get) {
err = hw->soc->bias_get(hw, desc, 1, &ret);
if (err)
return err;
} else {
return -ENOTSUPP;
}
break;
case PIN_CONFIG_BIAS_PULL_DOWN:
if (hw->soc->bias_get_combo) {
err = hw->soc->bias_get_combo(hw, desc, &pullup, &ret);
if (err)
return err;
if (ret == MTK_PUPD_SET_R1R0_00 || ret == MTK_DISABLE)
return -EINVAL;
if (pullup)
return -EINVAL;
} else if (hw->soc->bias_get) {
err = hw->soc->bias_get(hw, desc, 0, &ret);
if (err)
return err;
} else {
return -ENOTSUPP;
}
break;
case PIN_CONFIG_SLEW_RATE:
err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_SR, &val);
if (err)
return err;
if (!val)
return -EINVAL;
break;
case PIN_CONFIG_INPUT_ENABLE:
case PIN_CONFIG_OUTPUT_ENABLE:
err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_DIR, &val);
if (err)
return err;
/* HW takes input mode as zero; output mode as non-zero */
if ((val && param == PIN_CONFIG_INPUT_ENABLE) ||
(!val && param == PIN_CONFIG_OUTPUT_ENABLE))
return -EINVAL;
break;
case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_DIR, &val);
if (err)
return err;
err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_SMT, &val2);
if (err)
return err;
if (val || !val2)
return -EINVAL;
break;
case PIN_CONFIG_DRIVE_STRENGTH:
if (hw->soc->drive_get) {
err = hw->soc->drive_get(hw, desc, &ret);
if (err)
return err;
} else {
err = -ENOTSUPP;
}
break;
case MTK_PIN_CONFIG_TDSEL:
case MTK_PIN_CONFIG_RDSEL:
reg = (param == MTK_PIN_CONFIG_TDSEL) ?
PINCTRL_PIN_REG_TDSEL : PINCTRL_PIN_REG_RDSEL;
err = mtk_hw_get_value(hw, desc, reg, &val);
if (err)
return err;
ret = val;
break;
case MTK_PIN_CONFIG_PU_ADV:
case MTK_PIN_CONFIG_PD_ADV:
if (hw->soc->adv_pull_get) {
bool pullup;
pullup = param == MTK_PIN_CONFIG_PU_ADV;
err = hw->soc->adv_pull_get(hw, desc, pullup, &ret);
if (err)
return err;
} else {
return -ENOTSUPP;
}
break;
default:
return -ENOTSUPP;
}
*config = pinconf_to_config_packed(param, ret);
return 0;
}
static int mtk_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
unsigned long *configs, unsigned int num_configs)
{
struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
const struct mtk_pin_desc *desc;
u32 reg, param, arg;
int cfg, err = 0;
desc = (const struct mtk_pin_desc *)&hw->soc->pins[pin];
if (!desc->name)
return -ENOTSUPP;
for (cfg = 0; cfg < num_configs; cfg++) {
param = pinconf_to_config_param(configs[cfg]);
arg = pinconf_to_config_argument(configs[cfg]);
switch (param) {
case PIN_CONFIG_BIAS_DISABLE:
if (hw->soc->bias_set_combo) {
err = hw->soc->bias_set_combo(hw, desc, 0, MTK_DISABLE);
if (err)
return err;
} else if (hw->soc->bias_disable_set) {
err = hw->soc->bias_disable_set(hw, desc);
if (err)
return err;
} else {
return -ENOTSUPP;
}
break;
case PIN_CONFIG_BIAS_PULL_UP:
if (hw->soc->bias_set_combo) {
err = hw->soc->bias_set_combo(hw, desc, 1, arg);
if (err)
return err;
} else if (hw->soc->bias_set) {
err = hw->soc->bias_set(hw, desc, 1);
if (err)
return err;
} else {
return -ENOTSUPP;
}
break;
case PIN_CONFIG_BIAS_PULL_DOWN:
if (hw->soc->bias_set_combo) {
err = hw->soc->bias_set_combo(hw, desc, 0, arg);
if (err)
return err;
} else if (hw->soc->bias_set) {
err = hw->soc->bias_set(hw, desc, 0);
if (err)
return err;
} else {
return -ENOTSUPP;
}
break;
case PIN_CONFIG_OUTPUT_ENABLE:
err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_SMT,
MTK_DISABLE);
if (err)
goto err;
err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DIR,
MTK_OUTPUT);
if (err)
goto err;
break;
case PIN_CONFIG_INPUT_ENABLE:
if (hw->soc->ies_present) {
mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_IES,
MTK_ENABLE);
}
err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DIR,
MTK_INPUT);
if (err)
goto err;
break;
case PIN_CONFIG_SLEW_RATE:
err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_SR,
arg);
if (err)
goto err;
break;
case PIN_CONFIG_OUTPUT:
err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DIR,
MTK_OUTPUT);
if (err)
goto err;
err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DO,
arg);
if (err)
goto err;
break;
case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
/* arg = 1: Input mode & SMT enable ;
* arg = 0: Output mode & SMT disable
*/
arg = arg ? 2 : 1;
err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DIR,
arg & 1);
if (err)
goto err;
err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_SMT,
!!(arg & 2));
if (err)
goto err;
break;
case PIN_CONFIG_DRIVE_STRENGTH:
if (hw->soc->drive_set) {
err = hw->soc->drive_set(hw, desc, arg);
if (err)
return err;
} else {
err = -ENOTSUPP;
}
break;
case MTK_PIN_CONFIG_TDSEL:
case MTK_PIN_CONFIG_RDSEL:
reg = (param == MTK_PIN_CONFIG_TDSEL) ?
PINCTRL_PIN_REG_TDSEL : PINCTRL_PIN_REG_RDSEL;
err = mtk_hw_set_value(hw, desc, reg, arg);
if (err)
goto err;
break;
case MTK_PIN_CONFIG_PU_ADV:
case MTK_PIN_CONFIG_PD_ADV:
if (hw->soc->adv_pull_set) {
bool pullup;
pullup = param == MTK_PIN_CONFIG_PU_ADV;
err = hw->soc->adv_pull_set(hw, desc, pullup,
arg);
if (err)
return err;
} else {
return -ENOTSUPP;
}
break;
default:
err = -ENOTSUPP;
}
}
err:
return err;
}
static int mtk_pinconf_group_get(struct pinctrl_dev *pctldev,
unsigned int group, unsigned long *config)
{
const unsigned int *pins;
unsigned int i, npins, old = 0;
int ret;
ret = pinctrl_generic_get_group_pins(pctldev, group, &pins, &npins);
if (ret)
return ret;
for (i = 0; i < npins; i++) {
if (mtk_pinconf_get(pctldev, pins[i], config))
return -ENOTSUPP;
/* configs do not match between two pins */
if (i && old != *config)
return -ENOTSUPP;
old = *config;
}
return 0;
}
static int mtk_pinconf_group_set(struct pinctrl_dev *pctldev,
unsigned int group, unsigned long *configs,
unsigned int num_configs)
{
const unsigned int *pins;
unsigned int i, npins;
int ret;
ret = pinctrl_generic_get_group_pins(pctldev, group, &pins, &npins);
if (ret)
return ret;
for (i = 0; i < npins; i++) {
ret = mtk_pinconf_set(pctldev, pins[i], configs, num_configs);
if (ret)
return ret;
}
return 0;
}
static const struct pinctrl_ops mtk_pctlops = {
.get_groups_count = pinctrl_generic_get_group_count,
.get_group_name = pinctrl_generic_get_group_name,
.get_group_pins = pinctrl_generic_get_group_pins,
.dt_node_to_map = pinconf_generic_dt_node_to_map_all,
.dt_free_map = pinconf_generic_dt_free_map,
};
static const struct pinmux_ops mtk_pmxops = {
.get_functions_count = pinmux_generic_get_function_count,
.get_function_name = pinmux_generic_get_function_name,
.get_function_groups = pinmux_generic_get_function_groups,
.set_mux = mtk_pinmux_set_mux,
.gpio_request_enable = mtk_pinmux_gpio_request_enable,
.gpio_set_direction = mtk_pinmux_gpio_set_direction,
.strict = true,
};
static const struct pinconf_ops mtk_confops = {
.is_generic = true,
.pin_config_get = mtk_pinconf_get,
.pin_config_set = mtk_pinconf_set,
.pin_config_group_get = mtk_pinconf_group_get,
.pin_config_group_set = mtk_pinconf_group_set,
.pin_config_config_dbg_show = pinconf_generic_dump_config,
};
static struct pinctrl_desc mtk_desc = {
.name = PINCTRL_PINCTRL_DEV,
.pctlops = &mtk_pctlops,
.pmxops = &mtk_pmxops,
.confops = &mtk_confops,
.owner = THIS_MODULE,
};
static int mtk_gpio_get(struct gpio_chip *chip, unsigned int gpio)
{
struct mtk_pinctrl *hw = gpiochip_get_data(chip);
const struct mtk_pin_desc *desc;
int value, err;
desc = (const struct mtk_pin_desc *)&hw->soc->pins[gpio];
if (!desc->name)
return -ENOTSUPP;
err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_DI, &value);
if (err)
return err;
return !!value;
}
static void mtk_gpio_set(struct gpio_chip *chip, unsigned int gpio, int value)
{
struct mtk_pinctrl *hw = gpiochip_get_data(chip);
const struct mtk_pin_desc *desc;
desc = (const struct mtk_pin_desc *)&hw->soc->pins[gpio];
if (!desc->name) {
dev_err(hw->dev, "Failed to set gpio %d\n", gpio);
return;
}
mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DO, !!value);
}
static int mtk_gpio_direction_output(struct gpio_chip *chip, unsigned int gpio,
int value)
{
mtk_gpio_set(chip, gpio, value);
return pinctrl_gpio_direction_output(chip, gpio);
}
static int mtk_gpio_to_irq(struct gpio_chip *chip, unsigned int offset)
{
struct mtk_pinctrl *hw = gpiochip_get_data(chip);
const struct mtk_pin_desc *desc;
if (!hw->eint)
return -ENOTSUPP;
desc = (const struct mtk_pin_desc *)&hw->soc->pins[offset];
if (desc->eint.eint_n == (u16)EINT_NA)
return -ENOTSUPP;
return mtk_eint_find_irq(hw->eint, desc->eint.eint_n);
}
static int mtk_gpio_set_config(struct gpio_chip *chip, unsigned int offset,
unsigned long config)
{
struct mtk_pinctrl *hw = gpiochip_get_data(chip);
const struct mtk_pin_desc *desc;
u32 debounce;
desc = (const struct mtk_pin_desc *)&hw->soc->pins[offset];
if (!desc->name)
return -ENOTSUPP;
if (!hw->eint ||
pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE ||
desc->eint.eint_n == (u16)EINT_NA)
return -ENOTSUPP;
debounce = pinconf_to_config_argument(config);
return mtk_eint_set_debounce(hw->eint, desc->eint.eint_n, debounce);
}
static int mtk_build_gpiochip(struct mtk_pinctrl *hw)
{
struct gpio_chip *chip = &hw->chip;
int ret;
chip->label = PINCTRL_PINCTRL_DEV;
chip->parent = hw->dev;
chip->request = gpiochip_generic_request;
chip->free = gpiochip_generic_free;
chip->direction_input = pinctrl_gpio_direction_input;
chip->direction_output = mtk_gpio_direction_output;
chip->get = mtk_gpio_get;
chip->set = mtk_gpio_set;
chip->to_irq = mtk_gpio_to_irq;
chip->set_config = mtk_gpio_set_config;
chip->base = -1;
chip->ngpio = hw->soc->npins;
ret = gpiochip_add_data(chip, hw);
if (ret < 0)
return ret;
/* Just for backward compatible for these old pinctrl nodes without
* "gpio-ranges" property. Otherwise, called directly from a
* DeviceTree-supported pinctrl driver is DEPRECATED.
* Please see Section 2.1 of
* Documentation/devicetree/bindings/gpio/gpio.txt on how to
* bind pinctrl and gpio drivers via the "gpio-ranges" property.
*/
if (!of_property_present(hw->dev->of_node, "gpio-ranges")) {
ret = gpiochip_add_pin_range(chip, dev_name(hw->dev), 0, 0,
chip->ngpio);
if (ret < 0) {
gpiochip_remove(chip);
return ret;
}
}
return 0;
}
static int mtk_build_groups(struct mtk_pinctrl *hw)
{
int err, i;
for (i = 0; i < hw->soc->ngrps; i++) {
const struct group_desc *group = hw->soc->grps + i;
const struct pingroup *grp = &group->grp;
err = pinctrl_generic_add_group(hw->pctrl, grp->name, grp->pins, grp->npins,
group->data);
if (err < 0) {
dev_err(hw->dev, "Failed to register group %s\n", grp->name);
return err;
}
}
return 0;
}
static int mtk_build_functions(struct mtk_pinctrl *hw)
{
int i, err;
for (i = 0; i < hw->soc->nfuncs ; i++) {
const struct function_desc *function = hw->soc->funcs + i;
const struct pinfunction *func = &function->func;
err = pinmux_generic_add_function(hw->pctrl, func->name,
func->groups, func->ngroups,
function->data);
if (err < 0) {
dev_err(hw->dev, "Failed to register function %s\n",
func->name);
return err;
}
}
return 0;
}
int mtk_moore_pinctrl_probe(struct platform_device *pdev,
const struct mtk_pin_soc *soc)
{
struct device *dev = &pdev->dev;
struct pinctrl_pin_desc *pins;
struct mtk_pinctrl *hw;
int err, i;
hw = devm_kzalloc(&pdev->dev, sizeof(*hw), GFP_KERNEL);
if (!hw)
return -ENOMEM;
hw->soc = soc;
hw->dev = &pdev->dev;
if (!hw->soc->nbase_names)
return dev_err_probe(dev, -EINVAL,
"SoC should be assigned at least one register base\n");
hw->base = devm_kmalloc_array(&pdev->dev, hw->soc->nbase_names,
sizeof(*hw->base), GFP_KERNEL);
if (!hw->base)
return -ENOMEM;
for (i = 0; i < hw->soc->nbase_names; i++) {
hw->base[i] = devm_platform_ioremap_resource_byname(pdev,
hw->soc->base_names[i]);
if (IS_ERR(hw->base[i]))
return PTR_ERR(hw->base[i]);
}
hw->nbase = hw->soc->nbase_names;
spin_lock_init(&hw->lock);
/* Copy from internal struct mtk_pin_desc to register to the core */
pins = devm_kmalloc_array(&pdev->dev, hw->soc->npins, sizeof(*pins),
GFP_KERNEL);
if (!pins)
return -ENOMEM;
for (i = 0; i < hw->soc->npins; i++) {
pins[i].number = hw->soc->pins[i].number;
pins[i].name = hw->soc->pins[i].name;
}
/* Setup pins descriptions per SoC types */
mtk_desc.pins = (const struct pinctrl_pin_desc *)pins;
mtk_desc.npins = hw->soc->npins;
mtk_desc.num_custom_params = ARRAY_SIZE(mtk_custom_bindings);
mtk_desc.custom_params = mtk_custom_bindings;
#ifdef CONFIG_DEBUG_FS
mtk_desc.custom_conf_items = mtk_conf_items;
#endif
err = devm_pinctrl_register_and_init(&pdev->dev, &mtk_desc, hw,
&hw->pctrl);
if (err)
return err;
/* Setup groups descriptions per SoC types */
err = mtk_build_groups(hw);
if (err)
return dev_err_probe(dev, err, "Failed to build groups\n");
/* Setup functions descriptions per SoC types */
err = mtk_build_functions(hw);
if (err)
return dev_err_probe(dev, err, "Failed to build functions\n");
/* For able to make pinctrl_claim_hogs, we must not enable pinctrl
* until all groups and functions are being added one.
*/
err = pinctrl_enable(hw->pctrl);
if (err)
return err;
err = mtk_build_eint(hw, pdev);
if (err)
dev_warn(&pdev->dev,
"Failed to add EINT, but pinctrl still can work\n");
/* Build gpiochip should be after pinctrl_enable is done */
err = mtk_build_gpiochip(hw);
if (err)
return dev_err_probe(dev, err, "Failed to add gpio_chip\n");
platform_set_drvdata(pdev, hw);
return 0;
}
|
/*
* Copyright 2023 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
*/
#ifndef __SMU_V13_0_10_H__
#define __SMU_V13_0_10_H__
#include "amdgpu.h"
int smu_v13_0_10_reset_init(struct amdgpu_device *adev);
int smu_v13_0_10_reset_fini(struct amdgpu_device *adev);
#endif
|
/*
* Copyright 2024 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
*/
#ifndef __IRQSRCS_ISP_4_1_H__
#define __IRQSRCS_ISP_4_1_H__
#define ISP_4_1__SRCID__ISP_SEMA_WAIT_FAIL_TIMEOUT 0x12 // Semaphore wait fail timeout
#define ISP_4_1__SRCID__ISP_SEMA_WAIT_INCOMPLETE_TIMEOUT 0x13 // Semaphore wait incomplete timeout
#define ISP_4_1__SRCID__ISP_SEMA_SIGNAL_INCOMPLETE_TIMEOUT 0x14 // Semaphore signal incomplete timeout
#define ISP_4_1__SRCID__ISP_RINGBUFFER_BASE5_CHANGED 0x15 // Ringbuffer base5 address changed
#define ISP_4_1__SRCID__ISP_RINGBUFFER_WPT5 0x16 // Ringbuffer write point 5 changed
#define ISP_4_1__SRCID__ISP_RINGBUFFER_BASE6_CHANGED 0x17 // Ringbuffer base6 address changed
#define ISP_4_1__SRCID__ISP_RINGBUFFER_WPT6 0x18 // Ringbuffer write point 6 changed
#define ISP_4_1__SRCID__ISP_RINGBUFFER_BASE7_CHANGED 0x19 // Ringbuffer base7 address changed
#define ISP_4_1__SRCID__ISP_RINGBUFFER_WPT7 0x1A // Ringbuffer write point 7 changed
#define ISP_4_1__SRCID__ISP_RINGBUFFER_BASE8_CHANGED 0x1B // Ringbuffer base8 address changed
#define ISP_4_1__SRCID__ISP_RINGBUFFER_WPT8 0x1C // Ringbuffer write point 8 changed
#define ISP_4_1__SRCID__ISP_RINGBUFFER_BASE9_CHANGED 0x00 // Ringbuffer base9 address changed
#define ISP_4_1__SRCID__ISP_RINGBUFFER_WPT9 0x01 // Ringbuffer write point 9 changed
#define ISP_4_1__SRCID__ISP_RINGBUFFER_BASE10_CHANGED 0x02 // Ringbuffer base10 address changed
#define ISP_4_1__SRCID__ISP_RINGBUFFER_WPT10 0x03 // Ringbuffer write point 10 changed
#define ISP_4_1__SRCID__ISP_RINGBUFFER_BASE11_CHANGED 0x04 // Ringbuffer base11 address changed
#define ISP_4_1__SRCID__ISP_RINGBUFFER_WPT11 0x05 // Ringbuffer write point 11 changed
#define ISP_4_1__SRCID__ISP_RINGBUFFER_BASE12_CHANGED 0x06 // Ringbuffer base12 address changed
#define ISP_4_1__SRCID__ISP_RINGBUFFER_WPT12 0x07 // Ringbuffer write point 12 changed
#define ISP_4_1__SRCID__ISP_RINGBUFFER_BASE13_CHANGED 0x08 // Ringbuffer base13 address changed
#define ISP_4_1__SRCID__ISP_RINGBUFFER_WPT13 0x09 // Ringbuffer write point 13 changed
#define ISP_4_1__SRCID__ISP_RINGBUFFER_BASE14_CHANGED 0x0A // Ringbuffer base14 address changed
#define ISP_4_1__SRCID__ISP_RINGBUFFER_WPT14 0x0B // Ringbuffer write point 14 changed
#define ISP_4_1__SRCID__ISP_RINGBUFFER_BASE15_CHANGED 0x0C // Ringbuffer base15 address changed
#define ISP_4_1__SRCID__ISP_RINGBUFFER_WPT15 0x0D // Ringbuffer write point 15 changed
#define ISP_4_1__SRCID__ISP_RINGBUFFER_BASE16_CHANGED 0x0E // Ringbuffer base16 address changed
#define ISP_4_1__SRCID__ISP_RINGBUFFER_WPT16 0x0F // Ringbuffer write point 16 changed
#define ISP_4_1__SRCID__ISP_MIPI0 0x29 // MIPI0 interrupt
#define ISP_4_1__SRCID__ISP_MIPI1 0x2A // MIPI1 interrupt
#define ISP_4_1__SRCID__ISP_I2C0 0x2B // I2C0 PAD interrupt
#define ISP_4_1__SRCID__ISP_I2C1 0x2C // I2C1 PAD interrupt
#define ISP_4_1__SRCID__ISP_FLASH0 0x2D // Flash0 interrupt
#define ISP_4_1__SRCID__ISP_FLASH1 0x2E // Flash1 interrupt
#define ISP_4_1__SRCID__ISP_DEBUG 0x2F // Debug information
#endif
|
/* SPDX-License-Identifier: GPL-2.0-only */
/******************************************************************************
*******************************************************************************
**
** Copyright (C) 2005-2010 Red Hat, Inc. All rights reserved.
**
**
*******************************************************************************
******************************************************************************/
#ifndef __ASTD_DOT_H__
#define __ASTD_DOT_H__
bool dlm_may_skip_callback(struct dlm_lkb *lkb, uint32_t flags, int mode,
int status, uint32_t sbflags, int *copy_lvb);
int dlm_get_cb(struct dlm_lkb *lkb, uint32_t flags, int mode,
int status, uint32_t sbflags,
struct dlm_callback **cb);
void dlm_add_cb(struct dlm_lkb *lkb, uint32_t flags, int mode, int status,
uint32_t sbflags);
int dlm_callback_start(struct dlm_ls *ls);
void dlm_callback_stop(struct dlm_ls *ls);
void dlm_callback_suspend(struct dlm_ls *ls);
void dlm_callback_resume(struct dlm_ls *ls);
#endif
|
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2019-20 Sean Anderson <[email protected]>
* Copyright (C) 2020 Western Digital Corporation or its affiliates.
*/
/dts-v1/;
#include "k210.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/leds/common.h>
/ {
model = "SiPeed MAIX GO";
compatible = "sipeed,maix-go", "canaan,kendryte-k210";
aliases {
serial0 = &uarths0;
};
chosen {
bootargs = "earlycon console=ttySIF0";
stdout-path = "serial0:115200n8";
};
gpio-leds {
compatible = "gpio-leds";
led0 {
color = <LED_COLOR_ID_GREEN>;
label = "green";
gpios = <&gpio1_0 4 GPIO_ACTIVE_LOW>;
};
led1 {
color = <LED_COLOR_ID_RED>;
label = "red";
gpios = <&gpio1_0 5 GPIO_ACTIVE_LOW>;
};
led2 {
color = <LED_COLOR_ID_BLUE>;
label = "blue";
gpios = <&gpio1_0 6 GPIO_ACTIVE_LOW>;
};
};
gpio-keys {
compatible = "gpio-keys";
key-up {
label = "UP";
linux,code = <BTN_1>;
gpios = <&gpio1_0 7 GPIO_ACTIVE_LOW>;
};
key-press {
label = "PRESS";
linux,code = <BTN_0>;
gpios = <&gpio0 0 GPIO_ACTIVE_LOW>;
};
key-down {
label = "DOWN";
linux,code = <BTN_2>;
gpios = <&gpio0 1 GPIO_ACTIVE_LOW>;
};
};
};
&fpioa {
pinctrl-0 = <&jtag_pinctrl>;
pinctrl-names = "default";
jtag_pinctrl: jtag-pinmux {
pinmux = <K210_FPIOA(0, K210_PCF_JTAG_TCLK)>,
<K210_FPIOA(1, K210_PCF_JTAG_TDI)>,
<K210_FPIOA(2, K210_PCF_JTAG_TMS)>,
<K210_FPIOA(3, K210_PCF_JTAG_TDO)>;
};
uarths_pinctrl: uarths-pinmux {
pinmux = <K210_FPIOA(4, K210_PCF_UARTHS_RX)>,
<K210_FPIOA(5, K210_PCF_UARTHS_TX)>;
};
gpio_pinctrl: gpio-pinmux {
pinmux = <K210_FPIOA(8, K210_PCF_GPIO0)>,
<K210_FPIOA(9, K210_PCF_GPIO1)>,
<K210_FPIOA(10, K210_PCF_GPIO2)>,
<K210_FPIOA(11, K210_PCF_GPIO3)>,
<K210_FPIOA(12, K210_PCF_GPIO4)>,
<K210_FPIOA(13, K210_PCF_GPIO5)>,
<K210_FPIOA(14, K210_PCF_GPIO6)>,
<K210_FPIOA(15, K210_PCF_GPIO7)>;
};
gpiohs_pinctrl: gpiohs-pinmux {
pinmux = <K210_FPIOA(16, K210_PCF_GPIOHS0)>,
<K210_FPIOA(17, K210_PCF_GPIOHS1)>,
<K210_FPIOA(21, K210_PCF_GPIOHS5)>,
<K210_FPIOA(22, K210_PCF_GPIOHS6)>,
<K210_FPIOA(23, K210_PCF_GPIOHS7)>,
<K210_FPIOA(24, K210_PCF_GPIOHS8)>,
<K210_FPIOA(25, K210_PCF_GPIOHS9)>,
<K210_FPIOA(32, K210_PCF_GPIOHS16)>,
<K210_FPIOA(33, K210_PCF_GPIOHS17)>,
<K210_FPIOA(34, K210_PCF_GPIOHS18)>,
<K210_FPIOA(35, K210_PCF_GPIOHS19)>;
};
i2s0_pinctrl: i2s0-pinmux {
pinmux = <K210_FPIOA(18, K210_PCF_I2S0_SCLK)>,
<K210_FPIOA(19, K210_PCF_I2S0_WS)>,
<K210_FPIOA(20, K210_PCF_I2S0_IN_D0)>;
};
dvp_pinctrl: dvp-pinmux {
pinmux = <K210_FPIOA(40, K210_PCF_SCCB_SDA)>,
<K210_FPIOA(41, K210_PCF_SCCB_SCLK)>,
<K210_FPIOA(42, K210_PCF_DVP_RST)>,
<K210_FPIOA(43, K210_PCF_DVP_VSYNC)>,
<K210_FPIOA(44, K210_PCF_DVP_PWDN)>,
<K210_FPIOA(45, K210_PCF_DVP_HSYNC)>,
<K210_FPIOA(46, K210_PCF_DVP_XCLK)>,
<K210_FPIOA(47, K210_PCF_DVP_PCLK)>;
};
spi0_pinctrl: spi0-pinmux {
pinmux = <K210_FPIOA(36, K210_PCF_GPIOHS20)>, /* cs */
<K210_FPIOA(37, K210_PCF_GPIOHS21)>, /* rst */
<K210_FPIOA(38, K210_PCF_GPIOHS22)>, /* dc */
<K210_FPIOA(39, K210_PCF_SPI0_SCLK)>; /* wr */
};
spi1_pinctrl: spi1-pinmux {
pinmux = <K210_FPIOA(26, K210_PCF_SPI1_D1)>,
<K210_FPIOA(27, K210_PCF_SPI1_SCLK)>,
<K210_FPIOA(28, K210_PCF_SPI1_D0)>,
<K210_FPIOA(29, K210_PCF_GPIOHS13)>; /* cs */
};
i2c1_pinctrl: i2c1-pinmux {
pinmux = <K210_FPIOA(30, K210_PCF_I2C1_SCLK)>,
<K210_FPIOA(31, K210_PCF_I2C1_SDA)>;
};
};
&uarths0 {
pinctrl-0 = <&uarths_pinctrl>;
pinctrl-names = "default";
status = "okay";
};
&gpio0 {
pinctrl-0 = <&gpiohs_pinctrl>;
pinctrl-names = "default";
status = "okay";
};
&gpio1 {
pinctrl-0 = <&gpio_pinctrl>;
pinctrl-names = "default";
status = "okay";
};
&i2s0 {
#sound-dai-cells = <1>;
pinctrl-0 = <&i2s0_pinctrl>;
pinctrl-names = "default";
status = "okay";
};
&i2c1 {
pinctrl-0 = <&i2c1_pinctrl>;
pinctrl-names = "default";
clock-frequency = <400000>;
status = "okay";
};
&spi0 {
pinctrl-0 = <&spi0_pinctrl>;
pinctrl-names = "default";
num-cs = <1>;
cs-gpios = <&gpio0 20 GPIO_ACTIVE_HIGH>;
status = "okay";
panel@0 {
compatible = "sitronix,st7789v";
reg = <0>;
reset-gpios = <&gpio0 21 GPIO_ACTIVE_LOW>;
dc-gpios = <&gpio0 22 GPIO_ACTIVE_HIGH>;
spi-max-frequency = <15000000>;
status = "disabled";
};
};
&spi1 {
pinctrl-0 = <&spi1_pinctrl>;
pinctrl-names = "default";
num-cs = <1>;
cs-gpios = <&gpio0 13 GPIO_ACTIVE_LOW>;
status = "okay";
mmc@0 {
compatible = "mmc-spi-slot";
reg = <0>;
voltage-ranges = <3300 3300>;
spi-max-frequency = <25000000>;
broken-cd;
};
};
&spi3 {
status = "okay";
flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <50000000>;
spi-tx-bus-width = <4>;
spi-rx-bus-width = <4>;
m25p,fast-read;
broken-flash-reset;
};
};
|
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2014 MediaTek Inc.
* Author: Shunli Wang <[email protected]>
*/
#include <linux/clk-provider.h>
#include <linux/mod_devicetable.h>
#include <linux/platform_device.h>
#include "clk-cpumux.h"
#include "clk-gate.h"
#include "clk-mtk.h"
#include "clk-pll.h"
#include <dt-bindings/clock/mt2701-clk.h>
/*
* For some clocks, we don't care what their actual rates are. And these
* clocks may change their rate on different products or different scenarios.
* So we model these clocks' rate as 0, to denote it's not an actual rate.
*/
#define DUMMY_RATE 0
static DEFINE_SPINLOCK(mt2701_clk_lock);
static const struct mtk_fixed_clk top_fixed_clks[] = {
FIXED_CLK(CLK_TOP_DPI, "dpi_ck", "clk26m",
108 * MHZ),
FIXED_CLK(CLK_TOP_DMPLL, "dmpll_ck", "clk26m",
400 * MHZ),
FIXED_CLK(CLK_TOP_VENCPLL, "vencpll_ck", "clk26m",
295750000),
FIXED_CLK(CLK_TOP_HDMI_0_PIX340M, "hdmi_0_pix340m", "clk26m",
340 * MHZ),
FIXED_CLK(CLK_TOP_HDMI_0_DEEP340M, "hdmi_0_deep340m", "clk26m",
340 * MHZ),
FIXED_CLK(CLK_TOP_HDMI_0_PLL340M, "hdmi_0_pll340m", "clk26m",
340 * MHZ),
FIXED_CLK(CLK_TOP_HADDS2_FB, "hadds2_fbclk", "clk26m",
27 * MHZ),
FIXED_CLK(CLK_TOP_WBG_DIG_416M, "wbg_dig_ck_416m", "clk26m",
416 * MHZ),
FIXED_CLK(CLK_TOP_DSI0_LNTC_DSI, "dsi0_lntc_dsi", "clk26m",
143 * MHZ),
FIXED_CLK(CLK_TOP_HDMI_SCL_RX, "hdmi_scl_rx", "clk26m",
27 * MHZ),
FIXED_CLK(CLK_TOP_AUD_EXT1, "aud_ext1", "clk26m",
DUMMY_RATE),
FIXED_CLK(CLK_TOP_AUD_EXT2, "aud_ext2", "clk26m",
DUMMY_RATE),
FIXED_CLK(CLK_TOP_NFI1X_PAD, "nfi1x_pad", "clk26m",
DUMMY_RATE),
};
static const struct mtk_fixed_factor top_fixed_divs[] = {
FACTOR(CLK_TOP_SYSPLL, "syspll_ck", "mainpll", 1, 1),
FACTOR(CLK_TOP_SYSPLL_D2, "syspll_d2", "mainpll", 1, 2),
FACTOR(CLK_TOP_SYSPLL_D3, "syspll_d3", "mainpll", 1, 3),
FACTOR(CLK_TOP_SYSPLL_D5, "syspll_d5", "mainpll", 1, 5),
FACTOR(CLK_TOP_SYSPLL_D7, "syspll_d7", "mainpll", 1, 7),
FACTOR(CLK_TOP_SYSPLL1_D2, "syspll1_d2", "syspll_d2", 1, 2),
FACTOR(CLK_TOP_SYSPLL1_D4, "syspll1_d4", "syspll_d2", 1, 4),
FACTOR(CLK_TOP_SYSPLL1_D8, "syspll1_d8", "syspll_d2", 1, 8),
FACTOR(CLK_TOP_SYSPLL1_D16, "syspll1_d16", "syspll_d2", 1, 16),
FACTOR(CLK_TOP_SYSPLL2_D2, "syspll2_d2", "syspll_d3", 1, 2),
FACTOR(CLK_TOP_SYSPLL2_D4, "syspll2_d4", "syspll_d3", 1, 4),
FACTOR(CLK_TOP_SYSPLL2_D8, "syspll2_d8", "syspll_d3", 1, 8),
FACTOR(CLK_TOP_SYSPLL3_D2, "syspll3_d2", "syspll_d5", 1, 2),
FACTOR(CLK_TOP_SYSPLL3_D4, "syspll3_d4", "syspll_d5", 1, 4),
FACTOR(CLK_TOP_SYSPLL4_D2, "syspll4_d2", "syspll_d7", 1, 2),
FACTOR(CLK_TOP_SYSPLL4_D4, "syspll4_d4", "syspll_d7", 1, 4),
FACTOR(CLK_TOP_UNIVPLL, "univpll_ck", "univpll", 1, 1),
FACTOR(CLK_TOP_UNIVPLL_D2, "univpll_d2", "univpll", 1, 2),
FACTOR(CLK_TOP_UNIVPLL_D3, "univpll_d3", "univpll", 1, 3),
FACTOR(CLK_TOP_UNIVPLL_D5, "univpll_d5", "univpll", 1, 5),
FACTOR(CLK_TOP_UNIVPLL_D7, "univpll_d7", "univpll", 1, 7),
FACTOR(CLK_TOP_UNIVPLL_D26, "univpll_d26", "univpll", 1, 26),
FACTOR(CLK_TOP_UNIVPLL_D52, "univpll_d52", "univpll", 1, 52),
FACTOR(CLK_TOP_UNIVPLL_D108, "univpll_d108", "univpll", 1, 108),
FACTOR(CLK_TOP_USB_PHY48M, "usb_phy48m_ck", "univpll", 1, 26),
FACTOR(CLK_TOP_UNIVPLL1_D2, "univpll1_d2", "univpll_d2", 1, 2),
FACTOR(CLK_TOP_UNIVPLL1_D4, "univpll1_d4", "univpll_d2", 1, 4),
FACTOR(CLK_TOP_UNIVPLL1_D8, "univpll1_d8", "univpll_d2", 1, 8),
FACTOR(CLK_TOP_8BDAC, "8bdac_ck", "univpll_d2", 1, 1),
FACTOR(CLK_TOP_UNIVPLL2_D2, "univpll2_d2", "univpll_d3", 1, 2),
FACTOR(CLK_TOP_UNIVPLL2_D4, "univpll2_d4", "univpll_d3", 1, 4),
FACTOR(CLK_TOP_UNIVPLL2_D8, "univpll2_d8", "univpll_d3", 1, 8),
FACTOR(CLK_TOP_UNIVPLL2_D16, "univpll2_d16", "univpll_d3", 1, 16),
FACTOR(CLK_TOP_UNIVPLL2_D32, "univpll2_d32", "univpll_d3", 1, 32),
FACTOR(CLK_TOP_UNIVPLL3_D2, "univpll3_d2", "univpll_d5", 1, 2),
FACTOR(CLK_TOP_UNIVPLL3_D4, "univpll3_d4", "univpll_d5", 1, 4),
FACTOR(CLK_TOP_UNIVPLL3_D8, "univpll3_d8", "univpll_d5", 1, 8),
FACTOR(CLK_TOP_MSDCPLL, "msdcpll_ck", "msdcpll", 1, 1),
FACTOR(CLK_TOP_MSDCPLL_D2, "msdcpll_d2", "msdcpll", 1, 2),
FACTOR(CLK_TOP_MSDCPLL_D4, "msdcpll_d4", "msdcpll", 1, 4),
FACTOR(CLK_TOP_MSDCPLL_D8, "msdcpll_d8", "msdcpll", 1, 8),
FACTOR(CLK_TOP_MMPLL, "mmpll_ck", "mmpll", 1, 1),
FACTOR(CLK_TOP_MMPLL_D2, "mmpll_d2", "mmpll", 1, 2),
FACTOR(CLK_TOP_DMPLL_D2, "dmpll_d2", "dmpll_ck", 1, 2),
FACTOR(CLK_TOP_DMPLL_D4, "dmpll_d4", "dmpll_ck", 1, 4),
FACTOR(CLK_TOP_DMPLL_X2, "dmpll_x2", "dmpll_ck", 1, 1),
FACTOR(CLK_TOP_TVDPLL, "tvdpll_ck", "tvdpll", 1, 1),
FACTOR(CLK_TOP_TVDPLL_D2, "tvdpll_d2", "tvdpll", 1, 2),
FACTOR(CLK_TOP_TVDPLL_D4, "tvdpll_d4", "tvdpll", 1, 4),
FACTOR(CLK_TOP_VDECPLL, "vdecpll_ck", "vdecpll", 1, 1),
FACTOR(CLK_TOP_TVD2PLL, "tvd2pll_ck", "tvd2pll", 1, 1),
FACTOR(CLK_TOP_TVD2PLL_D2, "tvd2pll_d2", "tvd2pll", 1, 2),
FACTOR(CLK_TOP_MIPIPLL, "mipipll", "dpi_ck", 1, 1),
FACTOR(CLK_TOP_MIPIPLL_D2, "mipipll_d2", "dpi_ck", 1, 2),
FACTOR(CLK_TOP_MIPIPLL_D4, "mipipll_d4", "dpi_ck", 1, 4),
FACTOR(CLK_TOP_HDMIPLL, "hdmipll_ck", "hdmitx_dig_cts", 1, 1),
FACTOR(CLK_TOP_HDMIPLL_D2, "hdmipll_d2", "hdmitx_dig_cts", 1, 2),
FACTOR(CLK_TOP_HDMIPLL_D3, "hdmipll_d3", "hdmitx_dig_cts", 1, 3),
FACTOR(CLK_TOP_ARMPLL_1P3G, "armpll_1p3g_ck", "armpll", 1, 1),
FACTOR(CLK_TOP_AUDPLL, "audpll", "audpll_sel", 1, 1),
FACTOR(CLK_TOP_AUDPLL_D4, "audpll_d4", "audpll_sel", 1, 4),
FACTOR(CLK_TOP_AUDPLL_D8, "audpll_d8", "audpll_sel", 1, 8),
FACTOR(CLK_TOP_AUDPLL_D16, "audpll_d16", "audpll_sel", 1, 16),
FACTOR(CLK_TOP_AUDPLL_D24, "audpll_d24", "audpll_sel", 1, 24),
FACTOR(CLK_TOP_AUD1PLL_98M, "aud1pll_98m_ck", "aud1pll", 1, 3),
FACTOR(CLK_TOP_AUD2PLL_90M, "aud2pll_90m_ck", "aud2pll", 1, 3),
FACTOR(CLK_TOP_HADDS2PLL_98M, "hadds2pll_98m", "hadds2pll", 1, 3),
FACTOR(CLK_TOP_HADDS2PLL_294M, "hadds2pll_294m", "hadds2pll", 1, 1),
FACTOR(CLK_TOP_ETHPLL_500M, "ethpll_500m_ck", "ethpll", 1, 1),
FACTOR(CLK_TOP_CLK26M_D8, "clk26m_d8", "clk26m", 1, 8),
FACTOR(CLK_TOP_32K_INTERNAL, "32k_internal", "clk26m", 1, 793),
FACTOR(CLK_TOP_32K_EXTERNAL, "32k_external", "rtc32k", 1, 1),
FACTOR(CLK_TOP_AXISEL_D4, "axisel_d4", "axi_sel", 1, 4),
};
static const char * const axi_parents[] = {
"clk26m",
"syspll1_d2",
"syspll_d5",
"syspll1_d4",
"univpll_d5",
"univpll2_d2",
"mmpll_d2",
"dmpll_d2"
};
static const char * const mem_parents[] = {
"clk26m",
"dmpll_ck"
};
static const char * const ddrphycfg_parents[] = {
"clk26m",
"syspll1_d8"
};
static const char * const mm_parents[] = {
"clk26m",
"vencpll_ck",
"syspll1_d2",
"syspll1_d4",
"univpll_d5",
"univpll1_d2",
"univpll2_d2",
"dmpll_ck"
};
static const char * const pwm_parents[] = {
"clk26m",
"univpll2_d4",
"univpll3_d2",
"univpll1_d4",
};
static const char * const vdec_parents[] = {
"clk26m",
"vdecpll_ck",
"syspll_d5",
"syspll1_d4",
"univpll_d5",
"univpll2_d2",
"vencpll_ck",
"msdcpll_d2",
"mmpll_d2"
};
static const char * const mfg_parents[] = {
"clk26m",
"mmpll_ck",
"dmpll_x2_ck",
"msdcpll_ck",
"clk26m",
"syspll_d3",
"univpll_d3",
"univpll1_d2"
};
static const char * const camtg_parents[] = {
"clk26m",
"univpll_d26",
"univpll2_d2",
"syspll3_d2",
"syspll3_d4",
"msdcpll_d2",
"mmpll_d2"
};
static const char * const uart_parents[] = {
"clk26m",
"univpll2_d8"
};
static const char * const spi_parents[] = {
"clk26m",
"syspll3_d2",
"syspll4_d2",
"univpll2_d4",
"univpll1_d8"
};
static const char * const usb20_parents[] = {
"clk26m",
"univpll1_d8",
"univpll3_d4"
};
static const char * const msdc30_parents[] = {
"clk26m",
"msdcpll_d2",
"syspll2_d2",
"syspll1_d4",
"univpll1_d4",
"univpll2_d4"
};
static const char * const aud_intbus_parents[] = {
"clk26m",
"syspll1_d4",
"syspll3_d2",
"syspll4_d2",
"univpll3_d2",
"univpll2_d4"
};
static const char * const pmicspi_parents[] = {
"clk26m",
"syspll1_d8",
"syspll2_d4",
"syspll4_d2",
"syspll3_d4",
"syspll2_d8",
"syspll1_d16",
"univpll3_d4",
"univpll_d26",
"dmpll_d2",
"dmpll_d4"
};
static const char * const scp_parents[] = {
"clk26m",
"syspll1_d8",
"dmpll_d2",
"dmpll_d4"
};
static const char * const dpi0_parents[] = {
"clk26m",
"mipipll",
"mipipll_d2",
"mipipll_d4",
"clk26m",
"tvdpll_ck",
"tvdpll_d2",
"tvdpll_d4"
};
static const char * const dpi1_parents[] = {
"clk26m",
"tvdpll_ck",
"tvdpll_d2",
"tvdpll_d4"
};
static const char * const tve_parents[] = {
"clk26m",
"mipipll",
"mipipll_d2",
"mipipll_d4",
"clk26m",
"tvdpll_ck",
"tvdpll_d2",
"tvdpll_d4"
};
static const char * const hdmi_parents[] = {
"clk26m",
"hdmipll_ck",
"hdmipll_d2",
"hdmipll_d3"
};
static const char * const apll_parents[] = {
"clk26m",
"audpll",
"audpll_d4",
"audpll_d8",
"audpll_d16",
"audpll_d24",
"clk26m",
"clk26m"
};
static const char * const rtc_parents[] = {
"32k_internal",
"32k_external",
"clk26m",
"univpll3_d8"
};
static const char * const nfi2x_parents[] = {
"clk26m",
"syspll2_d2",
"syspll_d7",
"univpll3_d2",
"syspll2_d4",
"univpll3_d4",
"syspll4_d4",
"clk26m"
};
static const char * const emmc_hclk_parents[] = {
"clk26m",
"syspll1_d2",
"syspll1_d4",
"syspll2_d2"
};
static const char * const flash_parents[] = {
"clk26m_d8",
"clk26m",
"syspll2_d8",
"syspll3_d4",
"univpll3_d4",
"syspll4_d2",
"syspll2_d4",
"univpll2_d4"
};
static const char * const di_parents[] = {
"clk26m",
"tvd2pll_ck",
"tvd2pll_d2",
"clk26m"
};
static const char * const nr_osd_parents[] = {
"clk26m",
"vencpll_ck",
"syspll1_d2",
"syspll1_d4",
"univpll_d5",
"univpll1_d2",
"univpll2_d2",
"dmpll_ck"
};
static const char * const hdmirx_bist_parents[] = {
"clk26m",
"syspll_d3",
"clk26m",
"syspll1_d16",
"syspll4_d2",
"syspll1_d4",
"vencpll_ck",
"clk26m"
};
static const char * const intdir_parents[] = {
"clk26m",
"mmpll_ck",
"syspll_d2",
"univpll_d2"
};
static const char * const asm_parents[] = {
"clk26m",
"univpll2_d4",
"univpll2_d2",
"syspll_d5"
};
static const char * const ms_card_parents[] = {
"clk26m",
"univpll3_d8",
"syspll4_d4"
};
static const char * const ethif_parents[] = {
"clk26m",
"syspll1_d2",
"syspll_d5",
"syspll1_d4",
"univpll_d5",
"univpll1_d2",
"dmpll_ck",
"dmpll_d2"
};
static const char * const hdmirx_parents[] = {
"clk26m",
"univpll_d52"
};
static const char * const cmsys_parents[] = {
"clk26m",
"syspll1_d2",
"univpll1_d2",
"univpll_d5",
"syspll_d5",
"syspll2_d2",
"syspll1_d4",
"syspll3_d2",
"syspll2_d4",
"syspll1_d8",
"clk26m",
"clk26m",
"clk26m",
"clk26m",
"clk26m"
};
static const char * const clk_8bdac_parents[] = {
"32k_internal",
"8bdac_ck",
"clk26m",
"clk26m"
};
static const char * const aud2dvd_parents[] = {
"a1sys_hp_ck",
"a2sys_hp_ck"
};
static const char * const padmclk_parents[] = {
"clk26m",
"univpll_d26",
"univpll_d52",
"univpll_d108",
"univpll2_d8",
"univpll2_d16",
"univpll2_d32"
};
static const char * const aud_mux_parents[] = {
"clk26m",
"aud1pll_98m_ck",
"aud2pll_90m_ck",
"hadds2pll_98m",
"audio_ext1_ck",
"audio_ext2_ck"
};
static const char * const aud_src_parents[] = {
"aud_mux1_sel",
"aud_mux2_sel"
};
static const char * const cpu_parents[] = {
"clk26m",
"armpll",
"mainpll",
"mmpll"
};
static const struct mtk_composite cpu_muxes[] __initconst = {
MUX(CLK_INFRA_CPUSEL, "infra_cpu_sel", cpu_parents, 0x0000, 2, 2),
};
static const struct mtk_composite top_muxes[] = {
MUX_GATE_FLAGS(CLK_TOP_AXI_SEL, "axi_sel", axi_parents,
0x0040, 0, 3, 7, CLK_IS_CRITICAL),
MUX_GATE_FLAGS(CLK_TOP_MEM_SEL, "mem_sel", mem_parents,
0x0040, 8, 1, 15, CLK_IS_CRITICAL),
MUX_GATE_FLAGS(CLK_TOP_DDRPHYCFG_SEL, "ddrphycfg_sel",
ddrphycfg_parents, 0x0040, 16, 1, 23, CLK_IS_CRITICAL),
MUX_GATE(CLK_TOP_MM_SEL, "mm_sel", mm_parents,
0x0040, 24, 3, 31),
MUX_GATE(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents,
0x0050, 0, 2, 7),
MUX_GATE(CLK_TOP_VDEC_SEL, "vdec_sel", vdec_parents,
0x0050, 8, 4, 15),
MUX_GATE(CLK_TOP_MFG_SEL, "mfg_sel", mfg_parents,
0x0050, 16, 3, 23),
MUX_GATE(CLK_TOP_CAMTG_SEL, "camtg_sel", camtg_parents,
0x0050, 24, 3, 31),
MUX_GATE(CLK_TOP_UART_SEL, "uart_sel", uart_parents,
0x0060, 0, 1, 7),
MUX_GATE(CLK_TOP_SPI0_SEL, "spi0_sel", spi_parents,
0x0060, 8, 3, 15),
MUX_GATE(CLK_TOP_USB20_SEL, "usb20_sel", usb20_parents,
0x0060, 16, 2, 23),
MUX_GATE(CLK_TOP_MSDC30_0_SEL, "msdc30_0_sel", msdc30_parents,
0x0060, 24, 3, 31),
MUX_GATE(CLK_TOP_MSDC30_1_SEL, "msdc30_1_sel", msdc30_parents,
0x0070, 0, 3, 7),
MUX_GATE(CLK_TOP_MSDC30_2_SEL, "msdc30_2_sel", msdc30_parents,
0x0070, 8, 3, 15),
MUX_GATE(CLK_TOP_AUDIO_SEL, "audio_sel", msdc30_parents,
0x0070, 16, 1, 23),
MUX_GATE(CLK_TOP_AUDINTBUS_SEL, "aud_intbus_sel", aud_intbus_parents,
0x0070, 24, 3, 31),
MUX_GATE(CLK_TOP_PMICSPI_SEL, "pmicspi_sel", pmicspi_parents,
0x0080, 0, 4, 7),
MUX_GATE(CLK_TOP_SCP_SEL, "scp_sel", scp_parents,
0x0080, 8, 2, 15),
MUX_GATE(CLK_TOP_DPI0_SEL, "dpi0_sel", dpi0_parents,
0x0080, 16, 3, 23),
MUX_GATE_FLAGS_2(CLK_TOP_DPI1_SEL, "dpi1_sel", dpi1_parents,
0x0080, 24, 2, 31, 0, CLK_MUX_ROUND_CLOSEST),
MUX_GATE(CLK_TOP_TVE_SEL, "tve_sel", tve_parents,
0x0090, 0, 3, 7),
MUX_GATE(CLK_TOP_HDMI_SEL, "hdmi_sel", hdmi_parents,
0x0090, 8, 2, 15),
MUX_GATE(CLK_TOP_APLL_SEL, "apll_sel", apll_parents,
0x0090, 16, 3, 23),
MUX_GATE_FLAGS(CLK_TOP_RTC_SEL, "rtc_sel", rtc_parents,
0x00A0, 0, 2, 7, CLK_IS_CRITICAL),
MUX_GATE(CLK_TOP_NFI2X_SEL, "nfi2x_sel", nfi2x_parents,
0x00A0, 8, 3, 15),
MUX_GATE(CLK_TOP_EMMC_HCLK_SEL, "emmc_hclk_sel", emmc_hclk_parents,
0x00A0, 24, 2, 31),
MUX_GATE(CLK_TOP_FLASH_SEL, "flash_sel", flash_parents,
0x00B0, 0, 3, 7),
MUX_GATE(CLK_TOP_DI_SEL, "di_sel", di_parents,
0x00B0, 8, 2, 15),
MUX_GATE(CLK_TOP_NR_SEL, "nr_sel", nr_osd_parents,
0x00B0, 16, 3, 23),
MUX_GATE(CLK_TOP_OSD_SEL, "osd_sel", nr_osd_parents,
0x00B0, 24, 3, 31),
MUX_GATE(CLK_TOP_HDMIRX_BIST_SEL, "hdmirx_bist_sel",
hdmirx_bist_parents, 0x00C0, 0, 3, 7),
MUX_GATE(CLK_TOP_INTDIR_SEL, "intdir_sel", intdir_parents,
0x00C0, 8, 2, 15),
MUX_GATE(CLK_TOP_ASM_I_SEL, "asm_i_sel", asm_parents,
0x00C0, 16, 2, 23),
MUX_GATE(CLK_TOP_ASM_M_SEL, "asm_m_sel", asm_parents,
0x00C0, 24, 3, 31),
MUX_GATE(CLK_TOP_ASM_H_SEL, "asm_h_sel", asm_parents,
0x00D0, 0, 2, 7),
MUX_GATE(CLK_TOP_MS_CARD_SEL, "ms_card_sel", ms_card_parents,
0x00D0, 16, 2, 23),
MUX_GATE(CLK_TOP_ETHIF_SEL, "ethif_sel", ethif_parents,
0x00D0, 24, 3, 31),
MUX_GATE(CLK_TOP_HDMIRX26_24_SEL, "hdmirx26_24_sel", hdmirx_parents,
0x00E0, 0, 1, 7),
MUX_GATE(CLK_TOP_MSDC30_3_SEL, "msdc30_3_sel", msdc30_parents,
0x00E0, 8, 3, 15),
MUX_GATE(CLK_TOP_CMSYS_SEL, "cmsys_sel", cmsys_parents,
0x00E0, 16, 4, 23),
MUX_GATE(CLK_TOP_SPI1_SEL, "spi2_sel", spi_parents,
0x00E0, 24, 3, 31),
MUX_GATE(CLK_TOP_SPI2_SEL, "spi1_sel", spi_parents,
0x00F0, 0, 3, 7),
MUX_GATE(CLK_TOP_8BDAC_SEL, "8bdac_sel", clk_8bdac_parents,
0x00F0, 8, 2, 15),
MUX_GATE(CLK_TOP_AUD2DVD_SEL, "aud2dvd_sel", aud2dvd_parents,
0x00F0, 16, 1, 23),
MUX(CLK_TOP_PADMCLK_SEL, "padmclk_sel", padmclk_parents,
0x0100, 0, 3),
MUX(CLK_TOP_AUD_MUX1_SEL, "aud_mux1_sel", aud_mux_parents,
0x012c, 0, 3),
MUX(CLK_TOP_AUD_MUX2_SEL, "aud_mux2_sel", aud_mux_parents,
0x012c, 3, 3),
MUX(CLK_TOP_AUDPLL_MUX_SEL, "audpll_sel", aud_mux_parents,
0x012c, 6, 3),
MUX_GATE(CLK_TOP_AUD_K1_SRC_SEL, "aud_k1_src_sel", aud_src_parents,
0x012c, 15, 1, 23),
MUX_GATE(CLK_TOP_AUD_K2_SRC_SEL, "aud_k2_src_sel", aud_src_parents,
0x012c, 16, 1, 24),
MUX_GATE(CLK_TOP_AUD_K3_SRC_SEL, "aud_k3_src_sel", aud_src_parents,
0x012c, 17, 1, 25),
MUX_GATE(CLK_TOP_AUD_K4_SRC_SEL, "aud_k4_src_sel", aud_src_parents,
0x012c, 18, 1, 26),
MUX_GATE(CLK_TOP_AUD_K5_SRC_SEL, "aud_k5_src_sel", aud_src_parents,
0x012c, 19, 1, 27),
MUX_GATE(CLK_TOP_AUD_K6_SRC_SEL, "aud_k6_src_sel", aud_src_parents,
0x012c, 20, 1, 28),
};
static const struct mtk_clk_divider top_adj_divs[] = {
DIV_ADJ(CLK_TOP_AUD_EXTCK1_DIV, "audio_ext1_ck", "aud_ext1",
0x0120, 0, 8),
DIV_ADJ(CLK_TOP_AUD_EXTCK2_DIV, "audio_ext2_ck", "aud_ext2",
0x0120, 8, 8),
DIV_ADJ(CLK_TOP_AUD_MUX1_DIV, "aud_mux1_div", "aud_mux1_sel",
0x0120, 16, 8),
DIV_ADJ(CLK_TOP_AUD_MUX2_DIV, "aud_mux2_div", "aud_mux2_sel",
0x0120, 24, 8),
DIV_ADJ(CLK_TOP_AUD_K1_SRC_DIV, "aud_k1_src_div", "aud_k1_src_sel",
0x0124, 0, 8),
DIV_ADJ(CLK_TOP_AUD_K2_SRC_DIV, "aud_k2_src_div", "aud_k2_src_sel",
0x0124, 8, 8),
DIV_ADJ(CLK_TOP_AUD_K3_SRC_DIV, "aud_k3_src_div", "aud_k3_src_sel",
0x0124, 16, 8),
DIV_ADJ(CLK_TOP_AUD_K4_SRC_DIV, "aud_k4_src_div", "aud_k4_src_sel",
0x0124, 24, 8),
DIV_ADJ(CLK_TOP_AUD_K5_SRC_DIV, "aud_k5_src_div", "aud_k5_src_sel",
0x0128, 0, 8),
DIV_ADJ(CLK_TOP_AUD_K6_SRC_DIV, "aud_k6_src_div", "aud_k6_src_sel",
0x0128, 8, 8),
};
static const struct mtk_gate_regs top_aud_cg_regs = {
.sta_ofs = 0x012C,
};
#define GATE_TOP_AUD(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &top_aud_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr)
static const struct mtk_gate top_clks[] = {
GATE_TOP_AUD(CLK_TOP_AUD_48K_TIMING, "a1sys_hp_ck", "aud_mux1_div",
21),
GATE_TOP_AUD(CLK_TOP_AUD_44K_TIMING, "a2sys_hp_ck", "aud_mux2_div",
22),
GATE_TOP_AUD(CLK_TOP_AUD_I2S1_MCLK, "aud_i2s1_mclk", "aud_k1_src_div",
23),
GATE_TOP_AUD(CLK_TOP_AUD_I2S2_MCLK, "aud_i2s2_mclk", "aud_k2_src_div",
24),
GATE_TOP_AUD(CLK_TOP_AUD_I2S3_MCLK, "aud_i2s3_mclk", "aud_k3_src_div",
25),
GATE_TOP_AUD(CLK_TOP_AUD_I2S4_MCLK, "aud_i2s4_mclk", "aud_k4_src_div",
26),
GATE_TOP_AUD(CLK_TOP_AUD_I2S5_MCLK, "aud_i2s5_mclk", "aud_k5_src_div",
27),
GATE_TOP_AUD(CLK_TOP_AUD_I2S6_MCLK, "aud_i2s6_mclk", "aud_k6_src_div",
28),
};
static int mtk_topckgen_init(struct platform_device *pdev)
{
struct clk_hw_onecell_data *clk_data;
void __iomem *base;
struct device_node *node = pdev->dev.of_node;
base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(base))
return PTR_ERR(base);
clk_data = mtk_alloc_clk_data(CLK_TOP_NR);
if (!clk_data)
return -ENOMEM;
mtk_clk_register_fixed_clks(top_fixed_clks, ARRAY_SIZE(top_fixed_clks),
clk_data);
mtk_clk_register_factors(top_fixed_divs, ARRAY_SIZE(top_fixed_divs),
clk_data);
mtk_clk_register_composites(&pdev->dev, top_muxes,
ARRAY_SIZE(top_muxes), base,
&mt2701_clk_lock, clk_data);
mtk_clk_register_dividers(&pdev->dev, top_adj_divs, ARRAY_SIZE(top_adj_divs),
base, &mt2701_clk_lock, clk_data);
mtk_clk_register_gates(&pdev->dev, node, top_clks,
ARRAY_SIZE(top_clks), clk_data);
return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
}
static const struct mtk_gate_regs infra_cg_regs = {
.set_ofs = 0x0040,
.clr_ofs = 0x0044,
.sta_ofs = 0x0048,
};
#define GATE_ICG(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &infra_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
static const struct mtk_gate infra_clks[] = {
GATE_ICG(CLK_INFRA_DBG, "dbgclk", "axi_sel", 0),
GATE_ICG(CLK_INFRA_SMI, "smi_ck", "mm_sel", 1),
GATE_ICG(CLK_INFRA_QAXI_CM4, "cm4_ck", "axi_sel", 2),
GATE_ICG(CLK_INFRA_AUD_SPLIN_B, "audio_splin_bck", "hadds2pll_294m", 4),
GATE_ICG(CLK_INFRA_AUDIO, "audio_ck", "clk26m", 5),
GATE_ICG(CLK_INFRA_EFUSE, "efuse_ck", "clk26m", 6),
GATE_ICG(CLK_INFRA_L2C_SRAM, "l2c_sram_ck", "mm_sel", 7),
GATE_ICG(CLK_INFRA_M4U, "m4u_ck", "mem_sel", 8),
GATE_ICG(CLK_INFRA_CONNMCU, "connsys_bus", "wbg_dig_ck_416m", 12),
GATE_ICG(CLK_INFRA_TRNG, "trng_ck", "axi_sel", 13),
GATE_ICG(CLK_INFRA_RAMBUFIF, "rambufif_ck", "mem_sel", 14),
GATE_ICG(CLK_INFRA_CPUM, "cpum_ck", "mem_sel", 15),
GATE_ICG(CLK_INFRA_KP, "kp_ck", "axi_sel", 16),
GATE_ICG(CLK_INFRA_CEC, "cec_ck", "rtc_sel", 18),
GATE_ICG(CLK_INFRA_IRRX, "irrx_ck", "axi_sel", 19),
GATE_ICG(CLK_INFRA_PMICSPI, "pmicspi_ck", "pmicspi_sel", 22),
GATE_ICG(CLK_INFRA_PMICWRAP, "pmicwrap_ck", "axi_sel", 23),
GATE_ICG(CLK_INFRA_DDCCI, "ddcci_ck", "axi_sel", 24),
};
static const struct mtk_fixed_factor infra_fixed_divs[] = {
FACTOR(CLK_INFRA_CLK_13M, "clk13m", "clk26m", 1, 2),
};
static u16 infrasys_rst_ofs[] = { 0x30, 0x34, };
static u16 pericfg_rst_ofs[] = { 0x0, 0x4, };
static const struct mtk_clk_rst_desc clk_rst_desc[] = {
/* infrasys */
{
.version = MTK_RST_SIMPLE,
.rst_bank_ofs = infrasys_rst_ofs,
.rst_bank_nr = ARRAY_SIZE(infrasys_rst_ofs),
},
/* pericfg */
{
.version = MTK_RST_SIMPLE,
.rst_bank_ofs = pericfg_rst_ofs,
.rst_bank_nr = ARRAY_SIZE(pericfg_rst_ofs),
},
};
static struct clk_hw_onecell_data *infra_clk_data;
static void __init mtk_infrasys_init_early(struct device_node *node)
{
int r, i;
if (!infra_clk_data) {
infra_clk_data = mtk_alloc_clk_data(CLK_INFRA_NR);
if (!infra_clk_data)
return;
for (i = 0; i < CLK_INFRA_NR; i++)
infra_clk_data->hws[i] = ERR_PTR(-EPROBE_DEFER);
}
mtk_clk_register_factors(infra_fixed_divs, ARRAY_SIZE(infra_fixed_divs),
infra_clk_data);
mtk_clk_register_cpumuxes(NULL, node, cpu_muxes, ARRAY_SIZE(cpu_muxes),
infra_clk_data);
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get,
infra_clk_data);
if (r)
pr_err("%s(): could not register clock provider: %d\n",
__func__, r);
}
CLK_OF_DECLARE_DRIVER(mtk_infra, "mediatek,mt2701-infracfg",
mtk_infrasys_init_early);
static int mtk_infrasys_init(struct platform_device *pdev)
{
int r, i;
struct device_node *node = pdev->dev.of_node;
if (!infra_clk_data) {
infra_clk_data = mtk_alloc_clk_data(CLK_INFRA_NR);
if (!infra_clk_data)
return -ENOMEM;
} else {
for (i = 0; i < CLK_INFRA_NR; i++) {
if (infra_clk_data->hws[i] == ERR_PTR(-EPROBE_DEFER))
infra_clk_data->hws[i] = ERR_PTR(-ENOENT);
}
}
mtk_clk_register_gates(&pdev->dev, node, infra_clks,
ARRAY_SIZE(infra_clks), infra_clk_data);
mtk_clk_register_factors(infra_fixed_divs, ARRAY_SIZE(infra_fixed_divs),
infra_clk_data);
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get,
infra_clk_data);
if (r)
return r;
mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc[0]);
return 0;
}
static const struct mtk_gate_regs peri0_cg_regs = {
.set_ofs = 0x0008,
.clr_ofs = 0x0010,
.sta_ofs = 0x0018,
};
static const struct mtk_gate_regs peri1_cg_regs = {
.set_ofs = 0x000c,
.clr_ofs = 0x0014,
.sta_ofs = 0x001c,
};
#define GATE_PERI0(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &peri0_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
#define GATE_PERI1(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &peri1_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
static const struct mtk_gate peri_clks[] = {
GATE_PERI0(CLK_PERI_USB0_MCU, "usb0_mcu_ck", "axi_sel", 31),
GATE_PERI0(CLK_PERI_ETH, "eth_ck", "clk26m", 30),
GATE_PERI0(CLK_PERI_SPI0, "spi0_ck", "spi0_sel", 29),
GATE_PERI0(CLK_PERI_AUXADC, "auxadc_ck", "clk26m", 28),
GATE_PERI0(CLK_PERI_I2C3, "i2c3_ck", "clk26m", 27),
GATE_PERI0(CLK_PERI_I2C2, "i2c2_ck", "axi_sel", 26),
GATE_PERI0(CLK_PERI_I2C1, "i2c1_ck", "axi_sel", 25),
GATE_PERI0(CLK_PERI_I2C0, "i2c0_ck", "axi_sel", 24),
GATE_PERI0(CLK_PERI_BTIF, "bitif_ck", "axi_sel", 23),
GATE_PERI0(CLK_PERI_UART3, "uart3_ck", "axi_sel", 22),
GATE_PERI0(CLK_PERI_UART2, "uart2_ck", "axi_sel", 21),
GATE_PERI0(CLK_PERI_UART1, "uart1_ck", "axi_sel", 20),
GATE_PERI0(CLK_PERI_UART0, "uart0_ck", "axi_sel", 19),
GATE_PERI0(CLK_PERI_NLI, "nli_ck", "axi_sel", 18),
GATE_PERI0(CLK_PERI_MSDC50_3, "msdc50_3_ck", "emmc_hclk_sel", 17),
GATE_PERI0(CLK_PERI_MSDC30_3, "msdc30_3_ck", "msdc30_3_sel", 16),
GATE_PERI0(CLK_PERI_MSDC30_2, "msdc30_2_ck", "msdc30_2_sel", 15),
GATE_PERI0(CLK_PERI_MSDC30_1, "msdc30_1_ck", "msdc30_1_sel", 14),
GATE_PERI0(CLK_PERI_MSDC30_0, "msdc30_0_ck", "msdc30_0_sel", 13),
GATE_PERI0(CLK_PERI_AP_DMA, "ap_dma_ck", "axi_sel", 12),
GATE_PERI0(CLK_PERI_USB1, "usb1_ck", "usb20_sel", 11),
GATE_PERI0(CLK_PERI_USB0, "usb0_ck", "usb20_sel", 10),
GATE_PERI0(CLK_PERI_PWM, "pwm_ck", "axi_sel", 9),
GATE_PERI0(CLK_PERI_PWM7, "pwm7_ck", "axisel_d4", 8),
GATE_PERI0(CLK_PERI_PWM6, "pwm6_ck", "axisel_d4", 7),
GATE_PERI0(CLK_PERI_PWM5, "pwm5_ck", "axisel_d4", 6),
GATE_PERI0(CLK_PERI_PWM4, "pwm4_ck", "axisel_d4", 5),
GATE_PERI0(CLK_PERI_PWM3, "pwm3_ck", "axisel_d4", 4),
GATE_PERI0(CLK_PERI_PWM2, "pwm2_ck", "axisel_d4", 3),
GATE_PERI0(CLK_PERI_PWM1, "pwm1_ck", "axisel_d4", 2),
GATE_PERI0(CLK_PERI_THERM, "therm_ck", "axi_sel", 1),
GATE_PERI0(CLK_PERI_NFI, "nfi_ck", "nfi2x_sel", 0),
GATE_PERI1(CLK_PERI_FCI, "fci_ck", "ms_card_sel", 11),
GATE_PERI1(CLK_PERI_SPI2, "spi2_ck", "spi2_sel", 10),
GATE_PERI1(CLK_PERI_SPI1, "spi1_ck", "spi1_sel", 9),
GATE_PERI1(CLK_PERI_HOST89_DVD, "host89_dvd_ck", "aud2dvd_sel", 8),
GATE_PERI1(CLK_PERI_HOST89_SPI, "host89_spi_ck", "spi0_sel", 7),
GATE_PERI1(CLK_PERI_HOST89_INT, "host89_int_ck", "axi_sel", 6),
GATE_PERI1(CLK_PERI_FLASH, "flash_ck", "nfi2x_sel", 5),
GATE_PERI1(CLK_PERI_NFI_PAD, "nfi_pad_ck", "nfi1x_pad", 4),
GATE_PERI1(CLK_PERI_NFI_ECC, "nfi_ecc_ck", "nfi1x_pad", 3),
GATE_PERI1(CLK_PERI_GCPU, "gcpu_ck", "axi_sel", 2),
GATE_PERI1(CLK_PERI_USB_SLV, "usbslv_ck", "axi_sel", 1),
GATE_PERI1(CLK_PERI_USB1_MCU, "usb1_mcu_ck", "axi_sel", 0),
};
static const char * const uart_ck_sel_parents[] = {
"clk26m",
"uart_sel",
};
static const struct mtk_composite peri_muxs[] = {
MUX(CLK_PERI_UART0_SEL, "uart0_ck_sel", uart_ck_sel_parents,
0x40c, 0, 1),
MUX(CLK_PERI_UART1_SEL, "uart1_ck_sel", uart_ck_sel_parents,
0x40c, 1, 1),
MUX(CLK_PERI_UART2_SEL, "uart2_ck_sel", uart_ck_sel_parents,
0x40c, 2, 1),
MUX(CLK_PERI_UART3_SEL, "uart3_ck_sel", uart_ck_sel_parents,
0x40c, 3, 1),
};
static int mtk_pericfg_init(struct platform_device *pdev)
{
struct clk_hw_onecell_data *clk_data;
void __iomem *base;
int r;
struct device_node *node = pdev->dev.of_node;
base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(base))
return PTR_ERR(base);
clk_data = mtk_alloc_clk_data(CLK_PERI_NR);
if (!clk_data)
return -ENOMEM;
mtk_clk_register_gates(&pdev->dev, node, peri_clks,
ARRAY_SIZE(peri_clks), clk_data);
mtk_clk_register_composites(&pdev->dev, peri_muxs,
ARRAY_SIZE(peri_muxs), base,
&mt2701_clk_lock, clk_data);
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
if (r)
return r;
mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc[1]);
return 0;
}
#define MT8590_PLL_FMAX (2000 * MHZ)
#define CON0_MT8590_RST_BAR BIT(27)
#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, \
_pd_shift, _tuner_reg, _pcw_reg, _pcw_shift) { \
.id = _id, \
.name = _name, \
.reg = _reg, \
.pwr_reg = _pwr_reg, \
.en_mask = _en_mask, \
.flags = _flags, \
.rst_bar_mask = CON0_MT8590_RST_BAR, \
.fmax = MT8590_PLL_FMAX, \
.pcwbits = _pcwbits, \
.pd_reg = _pd_reg, \
.pd_shift = _pd_shift, \
.tuner_reg = _tuner_reg, \
.pcw_reg = _pcw_reg, \
.pcw_shift = _pcw_shift, \
}
static const struct mtk_pll_data apmixed_plls[] = {
PLL(CLK_APMIXED_ARMPLL, "armpll", 0x200, 0x20c, 0x80000000,
PLL_AO, 21, 0x204, 24, 0x0, 0x204, 0),
PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x210, 0x21c, 0xf0000000,
HAVE_RST_BAR, 21, 0x210, 4, 0x0, 0x214, 0),
PLL(CLK_APMIXED_UNIVPLL, "univpll", 0x220, 0x22c, 0xf3000000,
HAVE_RST_BAR, 7, 0x220, 4, 0x0, 0x224, 14),
PLL(CLK_APMIXED_MMPLL, "mmpll", 0x230, 0x23c, 0, 0,
21, 0x230, 4, 0x0, 0x234, 0),
PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x240, 0x24c, 0x00000001, 0,
21, 0x240, 4, 0x0, 0x244, 0),
PLL(CLK_APMIXED_TVDPLL, "tvdpll", 0x250, 0x25c, 0x00000001, 0,
21, 0x250, 4, 0x0, 0x254, 0),
PLL(CLK_APMIXED_AUD1PLL, "aud1pll", 0x270, 0x27c, 0x00000001, 0,
31, 0x270, 4, 0x0, 0x274, 0),
PLL(CLK_APMIXED_TRGPLL, "trgpll", 0x280, 0x28c, 0x00000001, 0,
31, 0x280, 4, 0x0, 0x284, 0),
PLL(CLK_APMIXED_ETHPLL, "ethpll", 0x290, 0x29c, 0x00000001, 0,
31, 0x290, 4, 0x0, 0x294, 0),
PLL(CLK_APMIXED_VDECPLL, "vdecpll", 0x2a0, 0x2ac, 0x00000001, 0,
31, 0x2a0, 4, 0x0, 0x2a4, 0),
PLL(CLK_APMIXED_HADDS2PLL, "hadds2pll", 0x2b0, 0x2bc, 0x00000001, 0,
31, 0x2b0, 4, 0x0, 0x2b4, 0),
PLL(CLK_APMIXED_AUD2PLL, "aud2pll", 0x2c0, 0x2cc, 0x00000001, 0,
31, 0x2c0, 4, 0x0, 0x2c4, 0),
PLL(CLK_APMIXED_TVD2PLL, "tvd2pll", 0x2d0, 0x2dc, 0x00000001, 0,
21, 0x2d0, 4, 0x0, 0x2d4, 0),
};
static const struct mtk_fixed_factor apmixed_fixed_divs[] = {
FACTOR(CLK_APMIXED_HDMI_REF, "hdmi_ref", "tvdpll", 1, 1),
};
static int mtk_apmixedsys_init(struct platform_device *pdev)
{
struct clk_hw_onecell_data *clk_data;
struct device_node *node = pdev->dev.of_node;
clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR);
if (!clk_data)
return -ENOMEM;
mtk_clk_register_plls(node, apmixed_plls, ARRAY_SIZE(apmixed_plls),
clk_data);
mtk_clk_register_factors(apmixed_fixed_divs, ARRAY_SIZE(apmixed_fixed_divs),
clk_data);
return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
}
static const struct of_device_id of_match_clk_mt2701[] = {
{
.compatible = "mediatek,mt2701-topckgen",
.data = mtk_topckgen_init,
}, {
.compatible = "mediatek,mt2701-infracfg",
.data = mtk_infrasys_init,
}, {
.compatible = "mediatek,mt2701-pericfg",
.data = mtk_pericfg_init,
}, {
.compatible = "mediatek,mt2701-apmixedsys",
.data = mtk_apmixedsys_init,
}, {
/* sentinel */
}
};
MODULE_DEVICE_TABLE(of, of_match_clk_mt2701);
static int clk_mt2701_probe(struct platform_device *pdev)
{
int (*clk_init)(struct platform_device *);
int r;
clk_init = of_device_get_match_data(&pdev->dev);
if (!clk_init)
return -EINVAL;
r = clk_init(pdev);
if (r)
dev_err(&pdev->dev,
"could not register clock provider: %s: %d\n",
pdev->name, r);
return r;
}
static struct platform_driver clk_mt2701_drv = {
.probe = clk_mt2701_probe,
.driver = {
.name = "clk-mt2701",
.of_match_table = of_match_clk_mt2701,
},
};
static int __init clk_mt2701_init(void)
{
return platform_driver_register(&clk_mt2701_drv);
}
arch_initcall(clk_mt2701_init);
MODULE_DESCRIPTION("MediaTek MT2701 main clocks driver");
MODULE_LICENSE("GPL");
|
/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
/*
* Copyright (c) 2016 Amlogic, Inc.
* Author: Michael Turquette <[email protected]>
*
* Copyright (c) 2018 Amlogic, inc.
* Author: Qiufang Dai <[email protected]>
* Author: Jian Hu <[email protected]>
*
*/
#ifndef __G12A_H
#define __G12A_H
/*
* Clock controller register offsets
*
* Register offsets from the data sheet must be multiplied by 4 before
* adding them to the base address to get the right value.
*/
#define HHI_MIPI_CNTL0 0x000
#define HHI_MIPI_CNTL1 0x004
#define HHI_MIPI_CNTL2 0x008
#define HHI_MIPI_STS 0x00C
#define HHI_GP0_PLL_CNTL0 0x040
#define HHI_GP0_PLL_CNTL1 0x044
#define HHI_GP0_PLL_CNTL2 0x048
#define HHI_GP0_PLL_CNTL3 0x04C
#define HHI_GP0_PLL_CNTL4 0x050
#define HHI_GP0_PLL_CNTL5 0x054
#define HHI_GP0_PLL_CNTL6 0x058
#define HHI_GP0_PLL_STS 0x05C
#define HHI_GP1_PLL_CNTL0 0x060
#define HHI_GP1_PLL_CNTL1 0x064
#define HHI_GP1_PLL_CNTL2 0x068
#define HHI_GP1_PLL_CNTL3 0x06C
#define HHI_GP1_PLL_CNTL4 0x070
#define HHI_GP1_PLL_CNTL5 0x074
#define HHI_GP1_PLL_CNTL6 0x078
#define HHI_GP1_PLL_STS 0x07C
#define HHI_PCIE_PLL_CNTL0 0x098
#define HHI_PCIE_PLL_CNTL1 0x09C
#define HHI_PCIE_PLL_CNTL2 0x0A0
#define HHI_PCIE_PLL_CNTL3 0x0A4
#define HHI_PCIE_PLL_CNTL4 0x0A8
#define HHI_PCIE_PLL_CNTL5 0x0AC
#define HHI_PCIE_PLL_STS 0x0B8
#define HHI_HIFI_PLL_CNTL0 0x0D8
#define HHI_HIFI_PLL_CNTL1 0x0DC
#define HHI_HIFI_PLL_CNTL2 0x0E0
#define HHI_HIFI_PLL_CNTL3 0x0E4
#define HHI_HIFI_PLL_CNTL4 0x0E8
#define HHI_HIFI_PLL_CNTL5 0x0EC
#define HHI_HIFI_PLL_CNTL6 0x0F0
#define HHI_VIID_CLK_DIV 0x128
#define HHI_VIID_CLK_CNTL 0x12C
#define HHI_GCLK_MPEG0 0x140
#define HHI_GCLK_MPEG1 0x144
#define HHI_GCLK_MPEG2 0x148
#define HHI_GCLK_OTHER 0x150
#define HHI_GCLK_OTHER2 0x154
#define HHI_SYS_CPU_CLK_CNTL1 0x15c
#define HHI_VID_CLK_DIV 0x164
#define HHI_MPEG_CLK_CNTL 0x174
#define HHI_AUD_CLK_CNTL 0x178
#define HHI_VID_CLK_CNTL 0x17c
#define HHI_TS_CLK_CNTL 0x190
#define HHI_VID_CLK_CNTL2 0x194
#define HHI_SYS_CPU_CLK_CNTL0 0x19c
#define HHI_VID_PLL_CLK_DIV 0x1A0
#define HHI_MALI_CLK_CNTL 0x1b0
#define HHI_VPU_CLKC_CNTL 0x1b4
#define HHI_VPU_CLK_CNTL 0x1bC
#define HHI_ISP_CLK_CNTL 0x1C0
#define HHI_NNA_CLK_CNTL 0x1C8
#define HHI_HDMI_CLK_CNTL 0x1CC
#define HHI_VDEC_CLK_CNTL 0x1E0
#define HHI_VDEC2_CLK_CNTL 0x1E4
#define HHI_VDEC3_CLK_CNTL 0x1E8
#define HHI_VDEC4_CLK_CNTL 0x1EC
#define HHI_HDCP22_CLK_CNTL 0x1F0
#define HHI_VAPBCLK_CNTL 0x1F4
#define HHI_SYS_CPUB_CLK_CNTL1 0x200
#define HHI_SYS_CPUB_CLK_CNTL 0x208
#define HHI_VPU_CLKB_CNTL 0x20C
#define HHI_SYS_CPU_CLK_CNTL2 0x210
#define HHI_SYS_CPU_CLK_CNTL3 0x214
#define HHI_SYS_CPU_CLK_CNTL4 0x218
#define HHI_SYS_CPU_CLK_CNTL5 0x21c
#define HHI_SYS_CPU_CLK_CNTL6 0x220
#define HHI_GEN_CLK_CNTL 0x228
#define HHI_VDIN_MEAS_CLK_CNTL 0x250
#define HHI_MIPIDSI_PHY_CLK_CNTL 0x254
#define HHI_NAND_CLK_CNTL 0x25C
#define HHI_SD_EMMC_CLK_CNTL 0x264
#define HHI_MPLL_CNTL0 0x278
#define HHI_MPLL_CNTL1 0x27C
#define HHI_MPLL_CNTL2 0x280
#define HHI_MPLL_CNTL3 0x284
#define HHI_MPLL_CNTL4 0x288
#define HHI_MPLL_CNTL5 0x28c
#define HHI_MPLL_CNTL6 0x290
#define HHI_MPLL_CNTL7 0x294
#define HHI_MPLL_CNTL8 0x298
#define HHI_FIX_PLL_CNTL0 0x2A0
#define HHI_FIX_PLL_CNTL1 0x2A4
#define HHI_FIX_PLL_CNTL3 0x2AC
#define HHI_SYS_PLL_CNTL0 0x2f4
#define HHI_SYS_PLL_CNTL1 0x2f8
#define HHI_SYS_PLL_CNTL2 0x2fc
#define HHI_SYS_PLL_CNTL3 0x300
#define HHI_SYS_PLL_CNTL4 0x304
#define HHI_SYS_PLL_CNTL5 0x308
#define HHI_SYS_PLL_CNTL6 0x30c
#define HHI_HDMI_PLL_CNTL0 0x320
#define HHI_HDMI_PLL_CNTL1 0x324
#define HHI_HDMI_PLL_CNTL2 0x328
#define HHI_HDMI_PLL_CNTL3 0x32c
#define HHI_HDMI_PLL_CNTL4 0x330
#define HHI_HDMI_PLL_CNTL5 0x334
#define HHI_HDMI_PLL_CNTL6 0x338
#define HHI_SPICC_CLK_CNTL 0x3dc
#define HHI_SYS1_PLL_CNTL0 0x380
#define HHI_SYS1_PLL_CNTL1 0x384
#define HHI_SYS1_PLL_CNTL2 0x388
#define HHI_SYS1_PLL_CNTL3 0x38c
#define HHI_SYS1_PLL_CNTL4 0x390
#define HHI_SYS1_PLL_CNTL5 0x394
#define HHI_SYS1_PLL_CNTL6 0x398
#endif /* __G12A_H */
|
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) STMicroelectronics SA 2014
* Author: Vincent Abriou <[email protected]> for STMicroelectronics.
*/
#ifndef _STI_HDMI_H_
#define _STI_HDMI_H_
#include <linux/hdmi.h>
#include <linux/platform_device.h>
#include <media/cec-notifier.h>
#include <drm/drm_modes.h>
#include <drm/drm_property.h>
#define HDMI_STA 0x0010
#define HDMI_STA_DLL_LCK BIT(5)
#define HDMI_STA_HOT_PLUG BIT(4)
struct sti_hdmi;
struct hdmi_phy_ops {
bool (*start)(struct sti_hdmi *hdmi);
void (*stop)(struct sti_hdmi *hdmi);
};
struct hdmi_audio_params {
bool enabled;
unsigned int sample_width;
unsigned int sample_rate;
struct hdmi_audio_infoframe cea;
};
#define DEFAULT_COLORSPACE_MODE HDMI_COLORSPACE_RGB
/**
* STI hdmi structure
*
* @dev: driver device
* @drm_dev: pointer to drm device
* @mode: current display mode selected
* @regs: hdmi register
* @syscfg: syscfg register for pll rejection configuration
* @clk_pix: hdmi pixel clock
* @clk_tmds: hdmi tmds clock
* @clk_phy: hdmi phy clock
* @clk_audio: hdmi audio clock
* @irq: hdmi interrupt number
* @irq_status: interrupt status register
* @phy_ops: phy start/stop operations
* @enabled: true if hdmi is enabled else false
* @hpd: hot plug detect status
* @wait_event: wait event
* @event_received: wait event status
* @reset: reset control of the hdmi phy
* @ddc_adapt: i2c ddc adapter
* @colorspace: current colorspace selected
* @audio_pdev: ASoC hdmi-codec platform device
* @audio: hdmi audio parameters.
* @drm_connector: hdmi connector
* @notifier: hotplug detect notifier
*/
struct sti_hdmi {
struct device dev;
struct drm_device *drm_dev;
struct drm_display_mode mode;
void __iomem *regs;
void __iomem *syscfg;
struct clk *clk_pix;
struct clk *clk_tmds;
struct clk *clk_phy;
struct clk *clk_audio;
int irq;
u32 irq_status;
struct hdmi_phy_ops *phy_ops;
bool enabled;
bool hpd;
wait_queue_head_t wait_event;
bool event_received;
struct reset_control *reset;
struct i2c_adapter *ddc_adapt;
enum hdmi_colorspace colorspace;
struct platform_device *audio_pdev;
struct hdmi_audio_params audio;
struct drm_connector *drm_connector;
struct cec_notifier *notifier;
};
u32 hdmi_read(struct sti_hdmi *hdmi, int offset);
void hdmi_write(struct sti_hdmi *hdmi, u32 val, int offset);
/**
* hdmi phy config structure
*
* A pointer to an array of these structures is passed to a TMDS (HDMI) output
* via the control interface to provide board and SoC specific
* configurations of the HDMI PHY. Each entry in the array specifies a hardware
* specific configuration for a given TMDS clock frequency range.
*
* @min_tmds_freq: Lower bound of TMDS clock frequency this entry applies to
* @max_tmds_freq: Upper bound of TMDS clock frequency this entry applies to
* @config: SoC specific register configuration
*/
struct hdmi_phy_config {
u32 min_tmds_freq;
u32 max_tmds_freq;
u32 config[4];
};
#endif
|
/* SPDX-License-Identifier: GPL-2.0 */
#ifndef __DTS_MT6397_PINFUNC_H
#define __DTS_MT6397_PINFUNC_H
#include <dt-bindings/pinctrl/mt65xx.h>
#define MT6397_PIN_0_INT__FUNC_GPIO0 (MTK_PIN_NO(0) | 0)
#define MT6397_PIN_0_INT__FUNC_INT (MTK_PIN_NO(0) | 1)
#define MT6397_PIN_1_SRCVOLTEN__FUNC_GPIO1 (MTK_PIN_NO(1) | 0)
#define MT6397_PIN_1_SRCVOLTEN__FUNC_SRCVOLTEN (MTK_PIN_NO(1) | 1)
#define MT6397_PIN_1_SRCVOLTEN__FUNC_TEST_CK1 (MTK_PIN_NO(1) | 6)
#define MT6397_PIN_2_SRCLKEN_PERI__FUNC_GPIO2 (MTK_PIN_NO(2) | 0)
#define MT6397_PIN_2_SRCLKEN_PERI__FUNC_SRCLKEN_PERI (MTK_PIN_NO(2) | 1)
#define MT6397_PIN_2_SRCLKEN_PERI__FUNC_TEST_CK2 (MTK_PIN_NO(2) | 6)
#define MT6397_PIN_3_RTC_32K1V8__FUNC_GPIO3 (MTK_PIN_NO(3) | 0)
#define MT6397_PIN_3_RTC_32K1V8__FUNC_RTC_32K1V8 (MTK_PIN_NO(3) | 1)
#define MT6397_PIN_3_RTC_32K1V8__FUNC_TEST_CK3 (MTK_PIN_NO(3) | 6)
#define MT6397_PIN_4_WRAP_EVENT__FUNC_GPIO4 (MTK_PIN_NO(4) | 0)
#define MT6397_PIN_4_WRAP_EVENT__FUNC_WRAP_EVENT (MTK_PIN_NO(4) | 1)
#define MT6397_PIN_5_SPI_CLK__FUNC_GPIO5 (MTK_PIN_NO(5) | 0)
#define MT6397_PIN_5_SPI_CLK__FUNC_SPI_CLK (MTK_PIN_NO(5) | 1)
#define MT6397_PIN_6_SPI_CSN__FUNC_GPIO6 (MTK_PIN_NO(6) | 0)
#define MT6397_PIN_6_SPI_CSN__FUNC_SPI_CSN (MTK_PIN_NO(6) | 1)
#define MT6397_PIN_7_SPI_MOSI__FUNC_GPIO7 (MTK_PIN_NO(7) | 0)
#define MT6397_PIN_7_SPI_MOSI__FUNC_SPI_MOSI (MTK_PIN_NO(7) | 1)
#define MT6397_PIN_8_SPI_MISO__FUNC_GPIO8 (MTK_PIN_NO(8) | 0)
#define MT6397_PIN_8_SPI_MISO__FUNC_SPI_MISO (MTK_PIN_NO(8) | 1)
#define MT6397_PIN_9_AUD_CLK_MOSI__FUNC_GPIO9 (MTK_PIN_NO(9) | 0)
#define MT6397_PIN_9_AUD_CLK_MOSI__FUNC_AUD_CLK (MTK_PIN_NO(9) | 1)
#define MT6397_PIN_9_AUD_CLK_MOSI__FUNC_TEST_IN0 (MTK_PIN_NO(9) | 6)
#define MT6397_PIN_9_AUD_CLK_MOSI__FUNC_TEST_OUT0 (MTK_PIN_NO(9) | 7)
#define MT6397_PIN_10_AUD_DAT_MISO__FUNC_GPIO10 (MTK_PIN_NO(10) | 0)
#define MT6397_PIN_10_AUD_DAT_MISO__FUNC_AUD_MISO (MTK_PIN_NO(10) | 1)
#define MT6397_PIN_10_AUD_DAT_MISO__FUNC_TEST_IN1 (MTK_PIN_NO(10) | 6)
#define MT6397_PIN_10_AUD_DAT_MISO__FUNC_TEST_OUT1 (MTK_PIN_NO(10) | 7)
#define MT6397_PIN_11_AUD_DAT_MOSI__FUNC_GPIO11 (MTK_PIN_NO(11) | 0)
#define MT6397_PIN_11_AUD_DAT_MOSI__FUNC_AUD_MOSI (MTK_PIN_NO(11) | 1)
#define MT6397_PIN_11_AUD_DAT_MOSI__FUNC_TEST_IN2 (MTK_PIN_NO(11) | 6)
#define MT6397_PIN_11_AUD_DAT_MOSI__FUNC_TEST_OUT2 (MTK_PIN_NO(11) | 7)
#define MT6397_PIN_12_COL0__FUNC_GPIO12 (MTK_PIN_NO(12) | 0)
#define MT6397_PIN_12_COL0__FUNC_COL0_USBDL (MTK_PIN_NO(12) | 1)
#define MT6397_PIN_12_COL0__FUNC_EINT10_1X (MTK_PIN_NO(12) | 2)
#define MT6397_PIN_12_COL0__FUNC_PWM1_3X (MTK_PIN_NO(12) | 3)
#define MT6397_PIN_12_COL0__FUNC_TEST_IN3 (MTK_PIN_NO(12) | 6)
#define MT6397_PIN_12_COL0__FUNC_TEST_OUT3 (MTK_PIN_NO(12) | 7)
#define MT6397_PIN_13_COL1__FUNC_GPIO13 (MTK_PIN_NO(13) | 0)
#define MT6397_PIN_13_COL1__FUNC_COL1 (MTK_PIN_NO(13) | 1)
#define MT6397_PIN_13_COL1__FUNC_EINT11_1X (MTK_PIN_NO(13) | 2)
#define MT6397_PIN_13_COL1__FUNC_SCL0_2X (MTK_PIN_NO(13) | 3)
#define MT6397_PIN_13_COL1__FUNC_TEST_IN4 (MTK_PIN_NO(13) | 6)
#define MT6397_PIN_13_COL1__FUNC_TEST_OUT4 (MTK_PIN_NO(13) | 7)
#define MT6397_PIN_14_COL2__FUNC_GPIO14 (MTK_PIN_NO(14) | 0)
#define MT6397_PIN_14_COL2__FUNC_COL2 (MTK_PIN_NO(14) | 1)
#define MT6397_PIN_14_COL2__FUNC_EINT12_1X (MTK_PIN_NO(14) | 2)
#define MT6397_PIN_14_COL2__FUNC_SDA0_2X (MTK_PIN_NO(14) | 3)
#define MT6397_PIN_14_COL2__FUNC_TEST_IN5 (MTK_PIN_NO(14) | 6)
#define MT6397_PIN_14_COL2__FUNC_TEST_OUT5 (MTK_PIN_NO(14) | 7)
#define MT6397_PIN_15_COL3__FUNC_GPIO15 (MTK_PIN_NO(15) | 0)
#define MT6397_PIN_15_COL3__FUNC_COL3 (MTK_PIN_NO(15) | 1)
#define MT6397_PIN_15_COL3__FUNC_EINT13_1X (MTK_PIN_NO(15) | 2)
#define MT6397_PIN_15_COL3__FUNC_SCL1_2X (MTK_PIN_NO(15) | 3)
#define MT6397_PIN_15_COL3__FUNC_TEST_IN6 (MTK_PIN_NO(15) | 6)
#define MT6397_PIN_15_COL3__FUNC_TEST_OUT6 (MTK_PIN_NO(15) | 7)
#define MT6397_PIN_16_COL4__FUNC_GPIO16 (MTK_PIN_NO(16) | 0)
#define MT6397_PIN_16_COL4__FUNC_COL4 (MTK_PIN_NO(16) | 1)
#define MT6397_PIN_16_COL4__FUNC_EINT14_1X (MTK_PIN_NO(16) | 2)
#define MT6397_PIN_16_COL4__FUNC_SDA1_2X (MTK_PIN_NO(16) | 3)
#define MT6397_PIN_16_COL4__FUNC_TEST_IN7 (MTK_PIN_NO(16) | 6)
#define MT6397_PIN_16_COL4__FUNC_TEST_OUT7 (MTK_PIN_NO(16) | 7)
#define MT6397_PIN_17_COL5__FUNC_GPIO17 (MTK_PIN_NO(17) | 0)
#define MT6397_PIN_17_COL5__FUNC_COL5 (MTK_PIN_NO(17) | 1)
#define MT6397_PIN_17_COL5__FUNC_EINT15_1X (MTK_PIN_NO(17) | 2)
#define MT6397_PIN_17_COL5__FUNC_SCL2_2X (MTK_PIN_NO(17) | 3)
#define MT6397_PIN_17_COL5__FUNC_TEST_IN8 (MTK_PIN_NO(17) | 6)
#define MT6397_PIN_17_COL5__FUNC_TEST_OUT8 (MTK_PIN_NO(17) | 7)
#define MT6397_PIN_18_COL6__FUNC_GPIO18 (MTK_PIN_NO(18) | 0)
#define MT6397_PIN_18_COL6__FUNC_COL6 (MTK_PIN_NO(18) | 1)
#define MT6397_PIN_18_COL6__FUNC_EINT16_1X (MTK_PIN_NO(18) | 2)
#define MT6397_PIN_18_COL6__FUNC_SDA2_2X (MTK_PIN_NO(18) | 3)
#define MT6397_PIN_18_COL6__FUNC_GPIO32K_0 (MTK_PIN_NO(18) | 4)
#define MT6397_PIN_18_COL6__FUNC_GPIO26M_0 (MTK_PIN_NO(18) | 5)
#define MT6397_PIN_18_COL6__FUNC_TEST_IN9 (MTK_PIN_NO(18) | 6)
#define MT6397_PIN_18_COL6__FUNC_TEST_OUT9 (MTK_PIN_NO(18) | 7)
#define MT6397_PIN_19_COL7__FUNC_GPIO19 (MTK_PIN_NO(19) | 0)
#define MT6397_PIN_19_COL7__FUNC_COL7 (MTK_PIN_NO(19) | 1)
#define MT6397_PIN_19_COL7__FUNC_EINT17_1X (MTK_PIN_NO(19) | 2)
#define MT6397_PIN_19_COL7__FUNC_PWM2_3X (MTK_PIN_NO(19) | 3)
#define MT6397_PIN_19_COL7__FUNC_GPIO32K_1 (MTK_PIN_NO(19) | 4)
#define MT6397_PIN_19_COL7__FUNC_GPIO26M_1 (MTK_PIN_NO(19) | 5)
#define MT6397_PIN_19_COL7__FUNC_TEST_IN10 (MTK_PIN_NO(19) | 6)
#define MT6397_PIN_19_COL7__FUNC_TEST_OUT10 (MTK_PIN_NO(19) | 7)
#define MT6397_PIN_20_ROW0__FUNC_GPIO20 (MTK_PIN_NO(20) | 0)
#define MT6397_PIN_20_ROW0__FUNC_ROW0 (MTK_PIN_NO(20) | 1)
#define MT6397_PIN_20_ROW0__FUNC_EINT18_1X (MTK_PIN_NO(20) | 2)
#define MT6397_PIN_20_ROW0__FUNC_SCL0_3X (MTK_PIN_NO(20) | 3)
#define MT6397_PIN_20_ROW0__FUNC_TEST_IN11 (MTK_PIN_NO(20) | 6)
#define MT6397_PIN_20_ROW0__FUNC_TEST_OUT11 (MTK_PIN_NO(20) | 7)
#define MT6397_PIN_21_ROW1__FUNC_GPIO21 (MTK_PIN_NO(21) | 0)
#define MT6397_PIN_21_ROW1__FUNC_ROW1 (MTK_PIN_NO(21) | 1)
#define MT6397_PIN_21_ROW1__FUNC_EINT19_1X (MTK_PIN_NO(21) | 2)
#define MT6397_PIN_21_ROW1__FUNC_SDA0_3X (MTK_PIN_NO(21) | 3)
#define MT6397_PIN_21_ROW1__FUNC_AUD_TSTCK (MTK_PIN_NO(21) | 4)
#define MT6397_PIN_21_ROW1__FUNC_TEST_IN12 (MTK_PIN_NO(21) | 6)
#define MT6397_PIN_21_ROW1__FUNC_TEST_OUT12 (MTK_PIN_NO(21) | 7)
#define MT6397_PIN_22_ROW2__FUNC_GPIO22 (MTK_PIN_NO(22) | 0)
#define MT6397_PIN_22_ROW2__FUNC_ROW2 (MTK_PIN_NO(22) | 1)
#define MT6397_PIN_22_ROW2__FUNC_EINT20_1X (MTK_PIN_NO(22) | 2)
#define MT6397_PIN_22_ROW2__FUNC_SCL1_3X (MTK_PIN_NO(22) | 3)
#define MT6397_PIN_22_ROW2__FUNC_TEST_IN13 (MTK_PIN_NO(22) | 6)
#define MT6397_PIN_22_ROW2__FUNC_TEST_OUT13 (MTK_PIN_NO(22) | 7)
#define MT6397_PIN_23_ROW3__FUNC_GPIO23 (MTK_PIN_NO(23) | 0)
#define MT6397_PIN_23_ROW3__FUNC_ROW3 (MTK_PIN_NO(23) | 1)
#define MT6397_PIN_23_ROW3__FUNC_EINT21_1X (MTK_PIN_NO(23) | 2)
#define MT6397_PIN_23_ROW3__FUNC_SDA1_3X (MTK_PIN_NO(23) | 3)
#define MT6397_PIN_23_ROW3__FUNC_TEST_IN14 (MTK_PIN_NO(23) | 6)
#define MT6397_PIN_23_ROW3__FUNC_TEST_OUT14 (MTK_PIN_NO(23) | 7)
#define MT6397_PIN_24_ROW4__FUNC_GPIO24 (MTK_PIN_NO(24) | 0)
#define MT6397_PIN_24_ROW4__FUNC_ROW4 (MTK_PIN_NO(24) | 1)
#define MT6397_PIN_24_ROW4__FUNC_EINT22_1X (MTK_PIN_NO(24) | 2)
#define MT6397_PIN_24_ROW4__FUNC_SCL2_3X (MTK_PIN_NO(24) | 3)
#define MT6397_PIN_24_ROW4__FUNC_TEST_IN15 (MTK_PIN_NO(24) | 6)
#define MT6397_PIN_24_ROW4__FUNC_TEST_OUT15 (MTK_PIN_NO(24) | 7)
#define MT6397_PIN_25_ROW5__FUNC_GPIO25 (MTK_PIN_NO(25) | 0)
#define MT6397_PIN_25_ROW5__FUNC_ROW5 (MTK_PIN_NO(25) | 1)
#define MT6397_PIN_25_ROW5__FUNC_EINT23_1X (MTK_PIN_NO(25) | 2)
#define MT6397_PIN_25_ROW5__FUNC_SDA2_3X (MTK_PIN_NO(25) | 3)
#define MT6397_PIN_25_ROW5__FUNC_TEST_IN16 (MTK_PIN_NO(25) | 6)
#define MT6397_PIN_25_ROW5__FUNC_TEST_OUT16 (MTK_PIN_NO(25) | 7)
#define MT6397_PIN_26_ROW6__FUNC_GPIO26 (MTK_PIN_NO(26) | 0)
#define MT6397_PIN_26_ROW6__FUNC_ROW6 (MTK_PIN_NO(26) | 1)
#define MT6397_PIN_26_ROW6__FUNC_EINT24_1X (MTK_PIN_NO(26) | 2)
#define MT6397_PIN_26_ROW6__FUNC_PWM3_3X (MTK_PIN_NO(26) | 3)
#define MT6397_PIN_26_ROW6__FUNC_GPIO32K_2 (MTK_PIN_NO(26) | 4)
#define MT6397_PIN_26_ROW6__FUNC_GPIO26M_2 (MTK_PIN_NO(26) | 5)
#define MT6397_PIN_26_ROW6__FUNC_TEST_IN17 (MTK_PIN_NO(26) | 6)
#define MT6397_PIN_26_ROW6__FUNC_TEST_OUT17 (MTK_PIN_NO(26) | 7)
#define MT6397_PIN_27_ROW7__FUNC_GPIO27 (MTK_PIN_NO(27) | 0)
#define MT6397_PIN_27_ROW7__FUNC_ROW7 (MTK_PIN_NO(27) | 1)
#define MT6397_PIN_27_ROW7__FUNC_EINT3_1X (MTK_PIN_NO(27) | 2)
#define MT6397_PIN_27_ROW7__FUNC_CBUS (MTK_PIN_NO(27) | 3)
#define MT6397_PIN_27_ROW7__FUNC_GPIO32K_3 (MTK_PIN_NO(27) | 4)
#define MT6397_PIN_27_ROW7__FUNC_GPIO26M_3 (MTK_PIN_NO(27) | 5)
#define MT6397_PIN_27_ROW7__FUNC_TEST_IN18 (MTK_PIN_NO(27) | 6)
#define MT6397_PIN_27_ROW7__FUNC_TEST_OUT18 (MTK_PIN_NO(27) | 7)
#define MT6397_PIN_28_PWM1__FUNC_GPIO28 (MTK_PIN_NO(28) | 0)
#define MT6397_PIN_28_PWM1__FUNC_PWM1 (MTK_PIN_NO(28) | 1)
#define MT6397_PIN_28_PWM1__FUNC_EINT4_1X (MTK_PIN_NO(28) | 2)
#define MT6397_PIN_28_PWM1__FUNC_GPIO32K_4 (MTK_PIN_NO(28) | 4)
#define MT6397_PIN_28_PWM1__FUNC_GPIO26M_4 (MTK_PIN_NO(28) | 5)
#define MT6397_PIN_28_PWM1__FUNC_TEST_IN19 (MTK_PIN_NO(28) | 6)
#define MT6397_PIN_28_PWM1__FUNC_TEST_OUT19 (MTK_PIN_NO(28) | 7)
#define MT6397_PIN_29_PWM2__FUNC_GPIO29 (MTK_PIN_NO(29) | 0)
#define MT6397_PIN_29_PWM2__FUNC_PWM2 (MTK_PIN_NO(29) | 1)
#define MT6397_PIN_29_PWM2__FUNC_EINT5_1X (MTK_PIN_NO(29) | 2)
#define MT6397_PIN_29_PWM2__FUNC_GPIO32K_5 (MTK_PIN_NO(29) | 4)
#define MT6397_PIN_29_PWM2__FUNC_GPIO26M_5 (MTK_PIN_NO(29) | 5)
#define MT6397_PIN_29_PWM2__FUNC_TEST_IN20 (MTK_PIN_NO(29) | 6)
#define MT6397_PIN_29_PWM2__FUNC_TEST_OUT20 (MTK_PIN_NO(29) | 7)
#define MT6397_PIN_30_PWM3__FUNC_GPIO30 (MTK_PIN_NO(30) | 0)
#define MT6397_PIN_30_PWM3__FUNC_PWM3 (MTK_PIN_NO(30) | 1)
#define MT6397_PIN_30_PWM3__FUNC_EINT6_1X (MTK_PIN_NO(30) | 2)
#define MT6397_PIN_30_PWM3__FUNC_COL0 (MTK_PIN_NO(30) | 3)
#define MT6397_PIN_30_PWM3__FUNC_GPIO32K_6 (MTK_PIN_NO(30) | 4)
#define MT6397_PIN_30_PWM3__FUNC_GPIO26M_6 (MTK_PIN_NO(30) | 5)
#define MT6397_PIN_30_PWM3__FUNC_TEST_IN21 (MTK_PIN_NO(30) | 6)
#define MT6397_PIN_30_PWM3__FUNC_TEST_OUT21 (MTK_PIN_NO(30) | 7)
#define MT6397_PIN_31_SCL0__FUNC_GPIO31 (MTK_PIN_NO(31) | 0)
#define MT6397_PIN_31_SCL0__FUNC_SCL0 (MTK_PIN_NO(31) | 1)
#define MT6397_PIN_31_SCL0__FUNC_EINT7_1X (MTK_PIN_NO(31) | 2)
#define MT6397_PIN_31_SCL0__FUNC_PWM1_2X (MTK_PIN_NO(31) | 3)
#define MT6397_PIN_31_SCL0__FUNC_TEST_IN22 (MTK_PIN_NO(31) | 6)
#define MT6397_PIN_31_SCL0__FUNC_TEST_OUT22 (MTK_PIN_NO(31) | 7)
#define MT6397_PIN_32_SDA0__FUNC_GPIO32 (MTK_PIN_NO(32) | 0)
#define MT6397_PIN_32_SDA0__FUNC_SDA0 (MTK_PIN_NO(32) | 1)
#define MT6397_PIN_32_SDA0__FUNC_EINT8_1X (MTK_PIN_NO(32) | 2)
#define MT6397_PIN_32_SDA0__FUNC_TEST_IN23 (MTK_PIN_NO(32) | 6)
#define MT6397_PIN_32_SDA0__FUNC_TEST_OUT23 (MTK_PIN_NO(32) | 7)
#define MT6397_PIN_33_SCL1__FUNC_GPIO33 (MTK_PIN_NO(33) | 0)
#define MT6397_PIN_33_SCL1__FUNC_SCL1 (MTK_PIN_NO(33) | 1)
#define MT6397_PIN_33_SCL1__FUNC_EINT9_1X (MTK_PIN_NO(33) | 2)
#define MT6397_PIN_33_SCL1__FUNC_PWM2_2X (MTK_PIN_NO(33) | 3)
#define MT6397_PIN_33_SCL1__FUNC_TEST_IN24 (MTK_PIN_NO(33) | 6)
#define MT6397_PIN_33_SCL1__FUNC_TEST_OUT24 (MTK_PIN_NO(33) | 7)
#define MT6397_PIN_34_SDA1__FUNC_GPIO34 (MTK_PIN_NO(34) | 0)
#define MT6397_PIN_34_SDA1__FUNC_SDA1 (MTK_PIN_NO(34) | 1)
#define MT6397_PIN_34_SDA1__FUNC_EINT0_1X (MTK_PIN_NO(34) | 2)
#define MT6397_PIN_34_SDA1__FUNC_TEST_IN25 (MTK_PIN_NO(34) | 6)
#define MT6397_PIN_34_SDA1__FUNC_TEST_OUT25 (MTK_PIN_NO(34) | 7)
#define MT6397_PIN_35_SCL2__FUNC_GPIO35 (MTK_PIN_NO(35) | 0)
#define MT6397_PIN_35_SCL2__FUNC_SCL2 (MTK_PIN_NO(35) | 1)
#define MT6397_PIN_35_SCL2__FUNC_EINT1_1X (MTK_PIN_NO(35) | 2)
#define MT6397_PIN_35_SCL2__FUNC_PWM3_2X (MTK_PIN_NO(35) | 3)
#define MT6397_PIN_35_SCL2__FUNC_TEST_IN26 (MTK_PIN_NO(35) | 6)
#define MT6397_PIN_35_SCL2__FUNC_TEST_OUT26 (MTK_PIN_NO(35) | 7)
#define MT6397_PIN_36_SDA2__FUNC_GPIO36 (MTK_PIN_NO(36) | 0)
#define MT6397_PIN_36_SDA2__FUNC_SDA2 (MTK_PIN_NO(36) | 1)
#define MT6397_PIN_36_SDA2__FUNC_EINT2_1X (MTK_PIN_NO(36) | 2)
#define MT6397_PIN_36_SDA2__FUNC_TEST_IN27 (MTK_PIN_NO(36) | 6)
#define MT6397_PIN_36_SDA2__FUNC_TEST_OUT27 (MTK_PIN_NO(36) | 7)
#define MT6397_PIN_37_HDMISD__FUNC_GPIO37 (MTK_PIN_NO(37) | 0)
#define MT6397_PIN_37_HDMISD__FUNC_HDMISD (MTK_PIN_NO(37) | 1)
#define MT6397_PIN_37_HDMISD__FUNC_TEST_IN28 (MTK_PIN_NO(37) | 6)
#define MT6397_PIN_37_HDMISD__FUNC_TEST_OUT28 (MTK_PIN_NO(37) | 7)
#define MT6397_PIN_38_HDMISCK__FUNC_GPIO38 (MTK_PIN_NO(38) | 0)
#define MT6397_PIN_38_HDMISCK__FUNC_HDMISCK (MTK_PIN_NO(38) | 1)
#define MT6397_PIN_38_HDMISCK__FUNC_TEST_IN29 (MTK_PIN_NO(38) | 6)
#define MT6397_PIN_38_HDMISCK__FUNC_TEST_OUT29 (MTK_PIN_NO(38) | 7)
#define MT6397_PIN_39_HTPLG__FUNC_GPIO39 (MTK_PIN_NO(39) | 0)
#define MT6397_PIN_39_HTPLG__FUNC_HTPLG (MTK_PIN_NO(39) | 1)
#define MT6397_PIN_39_HTPLG__FUNC_TEST_IN30 (MTK_PIN_NO(39) | 6)
#define MT6397_PIN_39_HTPLG__FUNC_TEST_OUT30 (MTK_PIN_NO(39) | 7)
#define MT6397_PIN_40_CEC__FUNC_GPIO40 (MTK_PIN_NO(40) | 0)
#define MT6397_PIN_40_CEC__FUNC_CEC (MTK_PIN_NO(40) | 1)
#define MT6397_PIN_40_CEC__FUNC_TEST_IN31 (MTK_PIN_NO(40) | 6)
#define MT6397_PIN_40_CEC__FUNC_TEST_OUT31 (MTK_PIN_NO(40) | 7)
#endif /* __DTS_MT6397_PINFUNC_H */
|
/*
* Device Tree Source for IBM Embedded PPC 476 Platform
*
* Copyright © 2011 Tony Breeds IBM Corporation
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without
* any warranty of any kind, whether express or implied.
*/
/dts-v1/;
/memreserve/ 0x01f00000 0x00100000; // spin table
/ {
#address-cells = <2>;
#size-cells = <2>;
model = "ibm,currituck";
compatible = "ibm,currituck";
dcr-parent = <&{/cpus/cpu@0}>;
aliases {
serial0 = &UART0;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
device_type = "cpu";
model = "PowerPC,476";
reg = <0>;
clock-frequency = <1600000000>; // 1.6 GHz
timebase-frequency = <100000000>; // 100Mhz
i-cache-line-size = <32>;
d-cache-line-size = <32>;
i-cache-size = <32768>;
d-cache-size = <32768>;
dcr-controller;
dcr-access-method = "native";
status = "okay";
};
cpu@1 {
device_type = "cpu";
model = "PowerPC,476";
reg = <1>;
clock-frequency = <1600000000>; // 1.6 GHz
timebase-frequency = <100000000>; // 100Mhz
i-cache-line-size = <32>;
d-cache-line-size = <32>;
i-cache-size = <32768>;
d-cache-size = <32768>;
dcr-controller;
dcr-access-method = "native";
status = "disabled";
enable-method = "spin-table";
cpu-release-addr = <0x0 0x01f00000>;
};
};
memory {
device_type = "memory";
reg = <0x0 0x0 0x0 0x0>; // filled in by zImage
};
MPIC: interrupt-controller {
compatible = "chrp,open-pic";
interrupt-controller;
dcr-reg = <0xffc00000 0x00040000>;
#address-cells = <0>;
#size-cells = <0>;
#interrupt-cells = <2>;
};
plb {
compatible = "ibm,plb6";
#address-cells = <2>;
#size-cells = <2>;
ranges;
clock-frequency = <200000000>; // 200Mhz
POB0: opb {
compatible = "ibm,opb-4xx", "ibm,opb";
#address-cells = <1>;
#size-cells = <1>;
/* Wish there was a nicer way of specifying a full
* 32-bit range
*/
ranges = <0x00000000 0x00000200 0x00000000 0x80000000
0x80000000 0x00000200 0x80000000 0x80000000>;
clock-frequency = <100000000>;
UART0: serial@10000000 {
device_type = "serial";
compatible = "ns16750", "ns16550";
reg = <0x10000000 0x00000008>;
virtual-reg = <0xe1000000>;
clock-frequency = <1851851>; // PCIe refclk/MCGC0_CTL[UART]
current-speed = <115200>;
interrupt-parent = <&MPIC>;
interrupts = <34 2>;
};
FPGA0: fpga@50000000 {
compatible = "ibm,currituck-fpga";
reg = <0x50000000 0x4>;
};
IIC0: i2c@0 {
compatible = "ibm,iic-currituck", "ibm,iic";
reg = <0x0 0x00000014>;
interrupt-parent = <&MPIC>;
interrupts = <79 2>;
#address-cells = <1>;
#size-cells = <0>;
rtc@68 {
compatible = "st,m41t80", "m41st85";
reg = <0x68>;
};
};
};
PCIE0: pcie@10100000000 { // 4xGBIF1
device_type = "pci";
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
compatible = "ibm,plb-pciex-476fpe", "ibm,plb-pciex";
primary;
port = <0x0>; /* port number */
reg = <0x00000101 0x00000000 0x0 0x10000000 /* Config space access */
0x00000100 0x00000000 0x0 0x00001000>; /* UTL Registers space access */
dcr-reg = <0x80 0x20>;
// pci_space < pci_addr > < cpu_addr > < size >
ranges = <0x02000000 0x00000000 0x80000000 0x00000110 0x80000000 0x0 0x80000000
0x01000000 0x0 0x0 0x00000140 0x0 0x0 0x00010000>;
/* Inbound starting at 0 to memsize filled in by zImage */
dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x0>;
/* This drives busses 0 to 0xf */
bus-range = <0x0 0xf>;
/* Legacy interrupts (note the weird polarity, the bridge seems
* to invert PCIe legacy interrupts).
* We are de-swizzling here because the numbers are actually for
* port of the root complex virtual P2P bridge. But I want
* to avoid putting a node for it in the tree, so the numbers
* below are basically de-swizzled numbers.
* The real slot is on idsel 0, so the swizzling is 1:1
*/
interrupt-map-mask = <0x0 0x0 0x0 0x7>;
interrupt-map = <
0x0 0x0 0x0 0x1 &MPIC 46 0x2 /* int A */
0x0 0x0 0x0 0x2 &MPIC 47 0x2 /* int B */
0x0 0x0 0x0 0x3 &MPIC 48 0x2 /* int C */
0x0 0x0 0x0 0x4 &MPIC 49 0x2 /* int D */>;
};
PCIE1: pcie@30100000000 { // 4xGBIF0
device_type = "pci";
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
compatible = "ibm,plb-pciex-476fpe", "ibm,plb-pciex";
primary;
port = <0x1>; /* port number */
reg = <0x00000301 0x00000000 0x0 0x10000000 /* Config space access */
0x00000300 0x00000000 0x0 0x00001000>; /* UTL Registers space access */
dcr-reg = <0x60 0x20>;
ranges = <0x02000000 0x00000000 0x80000000 0x00000310 0x80000000 0x0 0x80000000
0x01000000 0x0 0x0 0x00000340 0x0 0x0 0x00010000>;
/* Inbound starting at 0 to memsize filled in by zImage */
dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x0>;
/* This drives busses 0 to 0xf */
bus-range = <0x0 0xf>;
/* Legacy interrupts (note the weird polarity, the bridge seems
* to invert PCIe legacy interrupts).
* We are de-swizzling here because the numbers are actually for
* port of the root complex virtual P2P bridge. But I want
* to avoid putting a node for it in the tree, so the numbers
* below are basically de-swizzled numbers.
* The real slot is on idsel 0, so the swizzling is 1:1
*/
interrupt-map-mask = <0x0 0x0 0x0 0x7>;
interrupt-map = <
0x0 0x0 0x0 0x1 &MPIC 38 0x2 /* int A */
0x0 0x0 0x0 0x2 &MPIC 39 0x2 /* int B */
0x0 0x0 0x0 0x3 &MPIC 40 0x2 /* int C */
0x0 0x0 0x0 0x4 &MPIC 41 0x2 /* int D */>;
};
PCIE2: pcie@38100000000 { // 2xGBIF0
device_type = "pci";
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
compatible = "ibm,plb-pciex-476fpe", "ibm,plb-pciex";
primary;
port = <0x2>; /* port number */
reg = <0x00000381 0x00000000 0x0 0x10000000 /* Config space access */
0x00000380 0x00000000 0x0 0x00001000>; /* UTL Registers space access */
dcr-reg = <0xA0 0x20>;
ranges = <0x02000000 0x00000000 0x80000000 0x00000390 0x80000000 0x0 0x80000000
0x01000000 0x0 0x0 0x000003C0 0x0 0x0 0x00010000>;
/* Inbound starting at 0 to memsize filled in by zImage */
dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x0>;
/* This drives busses 0 to 0xf */
bus-range = <0x0 0xf>;
/* Legacy interrupts (note the weird polarity, the bridge seems
* to invert PCIe legacy interrupts).
* We are de-swizzling here because the numbers are actually for
* port of the root complex virtual P2P bridge. But I want
* to avoid putting a node for it in the tree, so the numbers
* below are basically de-swizzled numbers.
* The real slot is on idsel 0, so the swizzling is 1:1
*/
interrupt-map-mask = <0x0 0x0 0x0 0x7>;
interrupt-map = <
0x0 0x0 0x0 0x1 &MPIC 54 0x2 /* int A */
0x0 0x0 0x0 0x2 &MPIC 55 0x2 /* int B */
0x0 0x0 0x0 0x3 &MPIC 56 0x2 /* int C */
0x0 0x0 0x0 0x4 &MPIC 57 0x2 /* int D */>;
};
};
chosen {
stdout-path = &UART0;
};
};
|
/* SPDX-License-Identifier: GPL-2.0-only */
/*
*
* Copyright SUSE Linux Products GmbH 2009
*
* Authors: Alexander Graf <[email protected]>
*/
#ifndef __ASM_KVM_BOOK3S_ASM_H__
#define __ASM_KVM_BOOK3S_ASM_H__
/* XICS ICP register offsets */
#define XICS_XIRR 4
#define XICS_MFRR 0xc
#define XICS_IPI 2 /* interrupt source # for IPIs */
/* Maximum number of threads per physical core */
#define MAX_SMT_THREADS 8
/* Maximum number of subcores per physical core */
#define MAX_SUBCORES 4
#ifdef __ASSEMBLY__
#ifdef CONFIG_KVM_BOOK3S_HANDLER
#include <asm/kvm_asm.h>
.macro DO_KVM intno
.if (\intno == BOOK3S_INTERRUPT_SYSTEM_RESET) || \
(\intno == BOOK3S_INTERRUPT_MACHINE_CHECK) || \
(\intno == BOOK3S_INTERRUPT_DATA_STORAGE) || \
(\intno == BOOK3S_INTERRUPT_INST_STORAGE) || \
(\intno == BOOK3S_INTERRUPT_DATA_SEGMENT) || \
(\intno == BOOK3S_INTERRUPT_INST_SEGMENT) || \
(\intno == BOOK3S_INTERRUPT_EXTERNAL) || \
(\intno == BOOK3S_INTERRUPT_EXTERNAL_HV) || \
(\intno == BOOK3S_INTERRUPT_ALIGNMENT) || \
(\intno == BOOK3S_INTERRUPT_PROGRAM) || \
(\intno == BOOK3S_INTERRUPT_FP_UNAVAIL) || \
(\intno == BOOK3S_INTERRUPT_DECREMENTER) || \
(\intno == BOOK3S_INTERRUPT_SYSCALL) || \
(\intno == BOOK3S_INTERRUPT_TRACE) || \
(\intno == BOOK3S_INTERRUPT_PERFMON) || \
(\intno == BOOK3S_INTERRUPT_ALTIVEC) || \
(\intno == BOOK3S_INTERRUPT_VSX)
b kvmppc_trampoline_\intno
kvmppc_resume_\intno:
.endif
.endm
#else
.macro DO_KVM intno
.endm
#endif /* CONFIG_KVM_BOOK3S_HANDLER */
#else /*__ASSEMBLY__ */
struct kvmppc_vcore;
/* Struct used for coordinating micro-threading (split-core) mode changes */
struct kvm_split_mode {
unsigned long rpr;
unsigned long pmmar;
unsigned long ldbar;
u8 subcore_size;
u8 do_nap;
u8 napped[MAX_SMT_THREADS];
struct kvmppc_vcore *vc[MAX_SUBCORES];
};
/*
* This struct goes in the PACA on 64-bit processors. It is used
* to store host state that needs to be saved when we enter a guest
* and restored when we exit, but isn't specific to any particular
* guest or vcpu. It also has some scratch fields used by the guest
* exit code.
*/
struct kvmppc_host_state {
ulong host_r1;
ulong host_r2;
ulong host_msr;
ulong vmhandler;
ulong scratch0;
ulong scratch1;
ulong scratch2;
u8 in_guest;
u8 restore_hid5;
u8 napping;
#ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
u8 hwthread_req;
u8 hwthread_state;
u8 host_ipi;
u8 ptid; /* thread number within subcore when split */
u8 fake_suspend;
struct kvm_vcpu *kvm_vcpu;
struct kvmppc_vcore *kvm_vcore;
void __iomem *xics_phys;
void __iomem *xive_tima_phys;
void __iomem *xive_tima_virt;
u32 saved_xirr;
u64 dabr;
u64 host_mmcr[7]; /* MMCR 0,1,A, SIAR, SDAR, MMCR2, SIER */
u32 host_pmc[8];
u64 host_purr;
u64 host_spurr;
u64 host_dscr;
u64 dec_expires;
struct kvm_split_mode *kvm_split_mode;
#endif
#ifdef CONFIG_PPC_BOOK3S_64
u64 cfar;
u64 ppr;
u64 host_fscr;
#endif
};
struct kvmppc_book3s_shadow_vcpu {
bool in_use;
ulong gpr[14];
u32 cr;
ulong xer;
ulong ctr;
ulong lr;
ulong pc;
ulong shadow_srr1;
ulong fault_dar;
u32 fault_dsisr;
u32 last_inst;
#ifdef CONFIG_PPC_BOOK3S_32
u32 sr[16]; /* Guest SRs */
struct kvmppc_host_state hstate;
#endif
#ifdef CONFIG_PPC_BOOK3S_64
u8 slb_max; /* highest used guest slb entry */
struct {
u64 esid;
u64 vsid;
} slb[64]; /* guest SLB */
u64 shadow_fscr;
#endif
};
#endif /*__ASSEMBLY__ */
/* Values for kvm_state */
#define KVM_HWTHREAD_IN_KERNEL 0
#define KVM_HWTHREAD_IN_IDLE 1
#define KVM_HWTHREAD_IN_KVM 2
#endif /* __ASM_KVM_BOOK3S_ASM_H__ */
|
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Copyright 2022 Google LLC
*/
/dts-v1/;
#include "mt8192-asurada.dtsi"
#include <dt-bindings/leds/common.h>
/ {
model = "Google Spherion (rev4)";
chassis-type = "laptop";
compatible = "google,spherion-rev4", "google,spherion",
"mediatek,mt8192";
pwmleds {
compatible = "pwm-leds";
led {
function = LED_FUNCTION_KBD_BACKLIGHT;
color = <LED_COLOR_ID_WHITE>;
pwms = <&cros_ec_pwm 0>;
max-brightness = <1023>;
};
};
};
&cros_ec_pwm {
status = "okay";
};
&keyboard_controller {
function-row-physmap = <
MATRIX_KEY(0x00, 0x02, 0) /* T1 */
MATRIX_KEY(0x03, 0x02, 0) /* T2 */
MATRIX_KEY(0x02, 0x02, 0) /* T3 */
MATRIX_KEY(0x01, 0x02, 0) /* T4 */
MATRIX_KEY(0x03, 0x04, 0) /* T5 */
MATRIX_KEY(0x02, 0x04, 0) /* T6 */
MATRIX_KEY(0x01, 0x04, 0) /* T7 */
MATRIX_KEY(0x02, 0x09, 0) /* T8 */
MATRIX_KEY(0x01, 0x09, 0) /* T9 */
MATRIX_KEY(0x00, 0x04, 0) /* T10 */
>;
linux,keymap = <
MATRIX_KEY(0x00, 0x02, KEY_BACK)
MATRIX_KEY(0x03, 0x02, KEY_REFRESH)
MATRIX_KEY(0x02, 0x02, KEY_FULL_SCREEN)
MATRIX_KEY(0x01, 0x02, KEY_SCALE)
MATRIX_KEY(0x03, 0x04, KEY_SYSRQ)
MATRIX_KEY(0x02, 0x04, KEY_BRIGHTNESSDOWN)
MATRIX_KEY(0x01, 0x04, KEY_BRIGHTNESSUP)
MATRIX_KEY(0x02, 0x09, KEY_MUTE)
MATRIX_KEY(0x01, 0x09, KEY_VOLUMEDOWN)
MATRIX_KEY(0x00, 0x04, KEY_VOLUMEUP)
CROS_STD_MAIN_KEYMAP
>;
};
&rt5682 {
compatible = "realtek,rt5682s";
};
&sound {
compatible = "mediatek,mt8192_mt6359_rt1015p_rt5682s";
speaker-codecs {
sound-dai = <&rt1015p>;
};
headset-codec {
sound-dai = <&rt5682 0>;
};
};
&touchscreen {
compatible = "elan,ekth3500";
};
|
// SPDX-License-Identifier: GPL-2.0
/*
* security/tomoyo/securityfs_if.c
*
* Copyright (C) 2005-2011 NTT DATA CORPORATION
*/
#include <linux/security.h>
#include "common.h"
/**
* tomoyo_check_task_acl - Check permission for task operation.
*
* @r: Pointer to "struct tomoyo_request_info".
* @ptr: Pointer to "struct tomoyo_acl_info".
*
* Returns true if granted, false otherwise.
*/
static bool tomoyo_check_task_acl(struct tomoyo_request_info *r,
const struct tomoyo_acl_info *ptr)
{
const struct tomoyo_task_acl *acl = container_of(ptr, typeof(*acl),
head);
return !tomoyo_pathcmp(r->param.task.domainname, acl->domainname);
}
/**
* tomoyo_write_self - write() for /sys/kernel/security/tomoyo/self_domain interface.
*
* @file: Pointer to "struct file".
* @buf: Domainname to transit to.
* @count: Size of @buf.
* @ppos: Unused.
*
* Returns @count on success, negative value otherwise.
*
* If domain transition was permitted but the domain transition failed, this
* function returns error rather than terminating current thread with SIGKILL.
*/
static ssize_t tomoyo_write_self(struct file *file, const char __user *buf,
size_t count, loff_t *ppos)
{
char *data;
int error;
if (!count || count >= TOMOYO_EXEC_TMPSIZE - 10)
return -ENOMEM;
data = memdup_user_nul(buf, count);
if (IS_ERR(data))
return PTR_ERR(data);
tomoyo_normalize_line(data);
if (tomoyo_correct_domain(data)) {
const int idx = tomoyo_read_lock();
struct tomoyo_path_info name;
struct tomoyo_request_info r;
name.name = data;
tomoyo_fill_path_info(&name);
/* Check "task manual_domain_transition" permission. */
tomoyo_init_request_info(&r, NULL, TOMOYO_MAC_FILE_EXECUTE);
r.param_type = TOMOYO_TYPE_MANUAL_TASK_ACL;
r.param.task.domainname = &name;
tomoyo_check_acl(&r, tomoyo_check_task_acl);
if (!r.granted)
error = -EPERM;
else {
struct tomoyo_domain_info *new_domain =
tomoyo_assign_domain(data, true);
if (!new_domain) {
error = -ENOENT;
} else {
struct tomoyo_task *s = tomoyo_task(current);
struct tomoyo_domain_info *old_domain =
s->domain_info;
s->domain_info = new_domain;
atomic_inc(&new_domain->users);
atomic_dec(&old_domain->users);
error = 0;
}
}
tomoyo_read_unlock(idx);
} else
error = -EINVAL;
kfree(data);
return error ? error : count;
}
/**
* tomoyo_read_self - read() for /sys/kernel/security/tomoyo/self_domain interface.
*
* @file: Pointer to "struct file".
* @buf: Domainname which current thread belongs to.
* @count: Size of @buf.
* @ppos: Bytes read by now.
*
* Returns read size on success, negative value otherwise.
*/
static ssize_t tomoyo_read_self(struct file *file, char __user *buf,
size_t count, loff_t *ppos)
{
const char *domain = tomoyo_domain()->domainname->name;
loff_t len = strlen(domain);
loff_t pos = *ppos;
if (pos >= len || !count)
return 0;
len -= pos;
if (count < len)
len = count;
if (copy_to_user(buf, domain + pos, len))
return -EFAULT;
*ppos += len;
return len;
}
/* Operations for /sys/kernel/security/tomoyo/self_domain interface. */
static const struct file_operations tomoyo_self_operations = {
.write = tomoyo_write_self,
.read = tomoyo_read_self,
};
/**
* tomoyo_open - open() for /sys/kernel/security/tomoyo/ interface.
*
* @inode: Pointer to "struct inode".
* @file: Pointer to "struct file".
*
* Returns 0 on success, negative value otherwise.
*/
static int tomoyo_open(struct inode *inode, struct file *file)
{
const u8 key = (uintptr_t) file_inode(file)->i_private;
return tomoyo_open_control(key, file);
}
/**
* tomoyo_release - close() for /sys/kernel/security/tomoyo/ interface.
*
* @inode: Pointer to "struct inode".
* @file: Pointer to "struct file".
*
*/
static int tomoyo_release(struct inode *inode, struct file *file)
{
tomoyo_close_control(file->private_data);
return 0;
}
/**
* tomoyo_poll - poll() for /sys/kernel/security/tomoyo/ interface.
*
* @file: Pointer to "struct file".
* @wait: Pointer to "poll_table". Maybe NULL.
*
* Returns EPOLLIN | EPOLLRDNORM | EPOLLOUT | EPOLLWRNORM if ready to read/write,
* EPOLLOUT | EPOLLWRNORM otherwise.
*/
static __poll_t tomoyo_poll(struct file *file, poll_table *wait)
{
return tomoyo_poll_control(file, wait);
}
/**
* tomoyo_read - read() for /sys/kernel/security/tomoyo/ interface.
*
* @file: Pointer to "struct file".
* @buf: Pointer to buffer.
* @count: Size of @buf.
* @ppos: Unused.
*
* Returns bytes read on success, negative value otherwise.
*/
static ssize_t tomoyo_read(struct file *file, char __user *buf, size_t count,
loff_t *ppos)
{
return tomoyo_read_control(file->private_data, buf, count);
}
/**
* tomoyo_write - write() for /sys/kernel/security/tomoyo/ interface.
*
* @file: Pointer to "struct file".
* @buf: Pointer to buffer.
* @count: Size of @buf.
* @ppos: Unused.
*
* Returns @count on success, negative value otherwise.
*/
static ssize_t tomoyo_write(struct file *file, const char __user *buf,
size_t count, loff_t *ppos)
{
return tomoyo_write_control(file->private_data, buf, count);
}
/*
* tomoyo_operations is a "struct file_operations" which is used for handling
* /sys/kernel/security/tomoyo/ interface.
*
* Some files under /sys/kernel/security/tomoyo/ directory accept open(O_RDWR).
* See tomoyo_io_buffer for internals.
*/
static const struct file_operations tomoyo_operations = {
.open = tomoyo_open,
.release = tomoyo_release,
.poll = tomoyo_poll,
.read = tomoyo_read,
.write = tomoyo_write,
.llseek = noop_llseek,
};
/**
* tomoyo_create_entry - Create interface files under /sys/kernel/security/tomoyo/ directory.
*
* @name: The name of the interface file.
* @mode: The permission of the interface file.
* @parent: The parent directory.
* @key: Type of interface.
*
* Returns nothing.
*/
static void __init tomoyo_create_entry(const char *name, const umode_t mode,
struct dentry *parent, const u8 key)
{
securityfs_create_file(name, mode, parent, (void *) (uintptr_t) key,
&tomoyo_operations);
}
/**
* tomoyo_initerface_init - Initialize /sys/kernel/security/tomoyo/ interface.
*
* Returns 0.
*/
static int __init tomoyo_initerface_init(void)
{
struct tomoyo_domain_info *domain;
struct dentry *tomoyo_dir;
if (!tomoyo_enabled)
return 0;
domain = tomoyo_domain();
/* Don't create securityfs entries unless registered. */
if (domain != &tomoyo_kernel_domain)
return 0;
tomoyo_dir = securityfs_create_dir("tomoyo", NULL);
tomoyo_create_entry("query", 0600, tomoyo_dir,
TOMOYO_QUERY);
tomoyo_create_entry("domain_policy", 0600, tomoyo_dir,
TOMOYO_DOMAINPOLICY);
tomoyo_create_entry("exception_policy", 0600, tomoyo_dir,
TOMOYO_EXCEPTIONPOLICY);
tomoyo_create_entry("audit", 0400, tomoyo_dir,
TOMOYO_AUDIT);
tomoyo_create_entry(".process_status", 0600, tomoyo_dir,
TOMOYO_PROCESS_STATUS);
tomoyo_create_entry("stat", 0644, tomoyo_dir,
TOMOYO_STAT);
tomoyo_create_entry("profile", 0600, tomoyo_dir,
TOMOYO_PROFILE);
tomoyo_create_entry("manager", 0600, tomoyo_dir,
TOMOYO_MANAGER);
tomoyo_create_entry("version", 0400, tomoyo_dir,
TOMOYO_VERSION);
securityfs_create_file("self_domain", 0666, tomoyo_dir, NULL,
&tomoyo_self_operations);
tomoyo_load_builtin_policy();
return 0;
}
fs_initcall(tomoyo_initerface_init);
|
// SPDX-License-Identifier: GPL-2.0-only
// Copyright (C) 2014 Broadcom Corporation
#include <linux/kernel.h>
#include <linux/err.h>
#include <linux/clk-provider.h>
#include <linux/io.h>
#include <linux/of.h>
#include <linux/clkdev.h>
#include <linux/of_address.h>
#include <linux/delay.h>
#include "clk-iproc.h"
struct iproc_asiu;
struct iproc_asiu_clk {
struct clk_hw hw;
const char *name;
struct iproc_asiu *asiu;
unsigned long rate;
struct iproc_asiu_div div;
struct iproc_asiu_gate gate;
};
struct iproc_asiu {
void __iomem *div_base;
void __iomem *gate_base;
struct clk_hw_onecell_data *clk_data;
struct iproc_asiu_clk *clks;
};
#define to_asiu_clk(hw) container_of(hw, struct iproc_asiu_clk, hw)
static int iproc_asiu_clk_enable(struct clk_hw *hw)
{
struct iproc_asiu_clk *clk = to_asiu_clk(hw);
struct iproc_asiu *asiu = clk->asiu;
u32 val;
/* some clocks at the ASIU level are always enabled */
if (clk->gate.offset == IPROC_CLK_INVALID_OFFSET)
return 0;
val = readl(asiu->gate_base + clk->gate.offset);
val |= (1 << clk->gate.en_shift);
writel(val, asiu->gate_base + clk->gate.offset);
return 0;
}
static void iproc_asiu_clk_disable(struct clk_hw *hw)
{
struct iproc_asiu_clk *clk = to_asiu_clk(hw);
struct iproc_asiu *asiu = clk->asiu;
u32 val;
/* some clocks at the ASIU level are always enabled */
if (clk->gate.offset == IPROC_CLK_INVALID_OFFSET)
return;
val = readl(asiu->gate_base + clk->gate.offset);
val &= ~(1 << clk->gate.en_shift);
writel(val, asiu->gate_base + clk->gate.offset);
}
static unsigned long iproc_asiu_clk_recalc_rate(struct clk_hw *hw,
unsigned long parent_rate)
{
struct iproc_asiu_clk *clk = to_asiu_clk(hw);
struct iproc_asiu *asiu = clk->asiu;
u32 val;
unsigned int div_h, div_l;
if (parent_rate == 0) {
clk->rate = 0;
return 0;
}
/* if clock divisor is not enabled, simply return parent rate */
val = readl(asiu->div_base + clk->div.offset);
if ((val & (1 << clk->div.en_shift)) == 0) {
clk->rate = parent_rate;
return parent_rate;
}
/* clock rate = parent rate / (high_div + 1) + (low_div + 1) */
div_h = (val >> clk->div.high_shift) & bit_mask(clk->div.high_width);
div_h++;
div_l = (val >> clk->div.low_shift) & bit_mask(clk->div.low_width);
div_l++;
clk->rate = parent_rate / (div_h + div_l);
pr_debug("%s: rate: %lu. parent rate: %lu div_h: %u div_l: %u\n",
__func__, clk->rate, parent_rate, div_h, div_l);
return clk->rate;
}
static long iproc_asiu_clk_round_rate(struct clk_hw *hw, unsigned long rate,
unsigned long *parent_rate)
{
unsigned int div;
if (rate == 0 || *parent_rate == 0)
return -EINVAL;
if (rate == *parent_rate)
return *parent_rate;
div = DIV_ROUND_CLOSEST(*parent_rate, rate);
if (div < 2)
return *parent_rate;
return *parent_rate / div;
}
static int iproc_asiu_clk_set_rate(struct clk_hw *hw, unsigned long rate,
unsigned long parent_rate)
{
struct iproc_asiu_clk *clk = to_asiu_clk(hw);
struct iproc_asiu *asiu = clk->asiu;
unsigned int div, div_h, div_l;
u32 val;
if (rate == 0 || parent_rate == 0)
return -EINVAL;
/* simply disable the divisor if one wants the same rate as parent */
if (rate == parent_rate) {
val = readl(asiu->div_base + clk->div.offset);
val &= ~(1 << clk->div.en_shift);
writel(val, asiu->div_base + clk->div.offset);
return 0;
}
div = DIV_ROUND_CLOSEST(parent_rate, rate);
if (div < 2)
return -EINVAL;
div_h = div_l = div >> 1;
div_h--;
div_l--;
val = readl(asiu->div_base + clk->div.offset);
val |= 1 << clk->div.en_shift;
if (div_h) {
val &= ~(bit_mask(clk->div.high_width)
<< clk->div.high_shift);
val |= div_h << clk->div.high_shift;
} else {
val &= ~(bit_mask(clk->div.high_width)
<< clk->div.high_shift);
}
if (div_l) {
val &= ~(bit_mask(clk->div.low_width) << clk->div.low_shift);
val |= div_l << clk->div.low_shift;
} else {
val &= ~(bit_mask(clk->div.low_width) << clk->div.low_shift);
}
writel(val, asiu->div_base + clk->div.offset);
return 0;
}
static const struct clk_ops iproc_asiu_ops = {
.enable = iproc_asiu_clk_enable,
.disable = iproc_asiu_clk_disable,
.recalc_rate = iproc_asiu_clk_recalc_rate,
.round_rate = iproc_asiu_clk_round_rate,
.set_rate = iproc_asiu_clk_set_rate,
};
void __init iproc_asiu_setup(struct device_node *node,
const struct iproc_asiu_div *div,
const struct iproc_asiu_gate *gate,
unsigned int num_clks)
{
int i, ret;
struct iproc_asiu *asiu;
if (WARN_ON(!gate || !div))
return;
asiu = kzalloc(sizeof(*asiu), GFP_KERNEL);
if (WARN_ON(!asiu))
return;
asiu->clk_data = kzalloc(struct_size(asiu->clk_data, hws, num_clks),
GFP_KERNEL);
if (WARN_ON(!asiu->clk_data))
goto err_clks;
asiu->clk_data->num = num_clks;
asiu->clks = kcalloc(num_clks, sizeof(*asiu->clks), GFP_KERNEL);
if (WARN_ON(!asiu->clks))
goto err_asiu_clks;
asiu->div_base = of_iomap(node, 0);
if (WARN_ON(!asiu->div_base))
goto err_iomap_div;
asiu->gate_base = of_iomap(node, 1);
if (WARN_ON(!asiu->gate_base))
goto err_iomap_gate;
for (i = 0; i < num_clks; i++) {
struct clk_init_data init;
const char *parent_name;
struct iproc_asiu_clk *asiu_clk;
const char *clk_name;
ret = of_property_read_string_index(node, "clock-output-names",
i, &clk_name);
if (WARN_ON(ret))
goto err_clk_register;
asiu_clk = &asiu->clks[i];
asiu_clk->name = clk_name;
asiu_clk->asiu = asiu;
asiu_clk->div = div[i];
asiu_clk->gate = gate[i];
init.name = clk_name;
init.ops = &iproc_asiu_ops;
init.flags = 0;
parent_name = of_clk_get_parent_name(node, 0);
init.parent_names = (parent_name ? &parent_name : NULL);
init.num_parents = (parent_name ? 1 : 0);
asiu_clk->hw.init = &init;
ret = clk_hw_register(NULL, &asiu_clk->hw);
if (WARN_ON(ret))
goto err_clk_register;
asiu->clk_data->hws[i] = &asiu_clk->hw;
}
ret = of_clk_add_hw_provider(node, of_clk_hw_onecell_get,
asiu->clk_data);
if (WARN_ON(ret))
goto err_clk_register;
return;
err_clk_register:
while (--i >= 0)
clk_hw_unregister(asiu->clk_data->hws[i]);
iounmap(asiu->gate_base);
err_iomap_gate:
iounmap(asiu->div_base);
err_iomap_div:
kfree(asiu->clks);
err_asiu_clks:
kfree(asiu->clk_data);
err_clks:
kfree(asiu);
}
|
// SPDX-License-Identifier: GPL-2.0-or-later
/*
On Screen Display cx23415 Framebuffer driver
This module presents the cx23415 OSD (onscreen display) framebuffer memory
as a standard Linux /dev/fb style framebuffer device. The framebuffer has
support for 8, 16 & 32 bpp packed pixel formats with alpha channel. In 16bpp
mode, there is a choice of a three color depths (12, 15 or 16 bits), but no
local alpha. The colorspace is selectable between rgb & yuv.
Depending on the TV standard configured in the ivtv module at load time,
the initial resolution is either 640x400 (NTSC) or 640x480 (PAL) at 8bpp.
Video timings are locked to ensure a vertical refresh rate of 50Hz (PAL)
or 59.94 (NTSC)
Copyright (c) 2003 Matt T. Yourst <[email protected]>
Derived from drivers/video/vesafb.c
Portions (c) 1998 Gerd Knorr <[email protected]>
2.6 kernel port:
Copyright (C) 2004 Matthias Badaire
Copyright (C) 2004 Chris Kennedy <[email protected]>
Copyright (C) 2006 Ian Armstrong <[email protected]>
*/
#include "ivtv-driver.h"
#include "ivtv-cards.h"
#include "ivtv-i2c.h"
#include "ivtv-udma.h"
#include "ivtv-mailbox.h"
#include "ivtv-firmware.h"
#include <linux/fb.h>
#include <linux/ivtvfb.h>
#if defined(CONFIG_X86_64) && !defined(CONFIG_UML)
#include <asm/memtype.h>
#endif
/* card parameters */
static int ivtvfb_card_id = -1;
static int ivtvfb_debug;
static bool ivtvfb_force_pat = IS_ENABLED(CONFIG_VIDEO_FB_IVTV_FORCE_PAT);
static bool osd_laced;
static int osd_depth;
static int osd_upper;
static int osd_left;
static unsigned int osd_yres;
static unsigned int osd_xres;
module_param(ivtvfb_card_id, int, 0444);
module_param_named(debug,ivtvfb_debug, int, 0644);
module_param_named(force_pat, ivtvfb_force_pat, bool, 0644);
module_param(osd_laced, bool, 0444);
module_param(osd_depth, int, 0444);
module_param(osd_upper, int, 0444);
module_param(osd_left, int, 0444);
module_param(osd_yres, uint, 0444);
module_param(osd_xres, uint, 0444);
MODULE_PARM_DESC(ivtvfb_card_id,
"Only use framebuffer of the specified ivtv card (0-31)\n"
"\t\t\tdefault -1: initialize all available framebuffers");
MODULE_PARM_DESC(debug,
"Debug level (bitmask). Default: errors only\n"
"\t\t\t(debug = 3 gives full debugging)");
MODULE_PARM_DESC(force_pat,
"Force initialization on x86 PAT-enabled systems (bool).\n");
/* Why upper, left, xres, yres, depth, laced ? To match terminology used
by fbset.
Why start at 1 for left & upper coordinate ? Because X doesn't allow 0 */
MODULE_PARM_DESC(osd_laced,
"Interlaced mode\n"
"\t\t\t0=off\n"
"\t\t\t1=on\n"
"\t\t\tdefault off");
MODULE_PARM_DESC(osd_depth,
"Bits per pixel - 8, 16, 32\n"
"\t\t\tdefault 8");
MODULE_PARM_DESC(osd_upper,
"Vertical start position\n"
"\t\t\tdefault 0 (Centered)");
MODULE_PARM_DESC(osd_left,
"Horizontal start position\n"
"\t\t\tdefault 0 (Centered)");
MODULE_PARM_DESC(osd_yres,
"Display height\n"
"\t\t\tdefault 480 (PAL)\n"
"\t\t\t 400 (NTSC)");
MODULE_PARM_DESC(osd_xres,
"Display width\n"
"\t\t\tdefault 640");
MODULE_AUTHOR("Kevin Thayer, Chris Kennedy, Hans Verkuil, John Harvey, Ian Armstrong");
MODULE_DESCRIPTION("Conexant cx23415 framebuffer support");
MODULE_LICENSE("GPL");
/* --------------------------------------------------------------------- */
#define IVTVFB_DBGFLG_WARN (1 << 0)
#define IVTVFB_DBGFLG_INFO (1 << 1)
#define IVTVFB_DEBUG(x, type, fmt, args...) \
do { \
if ((x) & ivtvfb_debug) \
printk(KERN_INFO "ivtvfb%d " type ": " fmt, itv->instance , ## args); \
} while (0)
#define IVTVFB_DEBUG_WARN(fmt, args...) IVTVFB_DEBUG(IVTVFB_DBGFLG_WARN, "warning", fmt , ## args)
#define IVTVFB_DEBUG_INFO(fmt, args...) IVTVFB_DEBUG(IVTVFB_DBGFLG_INFO, "info", fmt , ## args)
/* Standard kernel messages */
#define IVTVFB_ERR(fmt, args...) printk(KERN_ERR "ivtvfb%d: " fmt, itv->instance , ## args)
#define IVTVFB_WARN(fmt, args...) printk(KERN_WARNING "ivtvfb%d: " fmt, itv->instance , ## args)
#define IVTVFB_INFO(fmt, args...) printk(KERN_INFO "ivtvfb%d: " fmt, itv->instance , ## args)
/* --------------------------------------------------------------------- */
#define IVTV_OSD_MAX_WIDTH 720
#define IVTV_OSD_MAX_HEIGHT 576
#define IVTV_OSD_BPP_8 0x00
#define IVTV_OSD_BPP_16_444 0x03
#define IVTV_OSD_BPP_16_555 0x02
#define IVTV_OSD_BPP_16_565 0x01
#define IVTV_OSD_BPP_32 0x04
struct osd_info {
/* Physical base address */
unsigned long video_pbase;
/* Relative base address (relative to start of decoder memory) */
u32 video_rbase;
/* Mapped base address */
volatile char __iomem *video_vbase;
/* Buffer size */
u32 video_buffer_size;
/* video_base rounded down as required by hardware MTRRs */
unsigned long fb_start_aligned_physaddr;
/* video_base rounded up as required by hardware MTRRs */
unsigned long fb_end_aligned_physaddr;
int wc_cookie;
/* Store the buffer offset */
int set_osd_coords_x;
int set_osd_coords_y;
/* Current dimensions (NOT VISIBLE SIZE!) */
int display_width;
int display_height;
int display_byte_stride;
/* Current bits per pixel */
int bits_per_pixel;
int bytes_per_pixel;
/* Frame buffer stuff */
struct fb_info ivtvfb_info;
struct fb_var_screeninfo ivtvfb_defined;
struct fb_fix_screeninfo ivtvfb_fix;
/* Used for a warm start */
struct fb_var_screeninfo fbvar_cur;
int blank_cur;
u32 palette_cur[256];
u32 pan_cur;
};
struct ivtv_osd_coords {
unsigned long offset;
unsigned long max_offset;
int pixel_stride;
int lines;
int x;
int y;
};
/* --------------------------------------------------------------------- */
/* ivtv API calls for framebuffer related support */
static int ivtvfb_get_framebuffer(struct ivtv *itv, u32 *fbbase,
u32 *fblength)
{
u32 data[CX2341X_MBOX_MAX_DATA];
int rc;
ivtv_firmware_check(itv, "ivtvfb_get_framebuffer");
rc = ivtv_vapi_result(itv, data, CX2341X_OSD_GET_FRAMEBUFFER, 0);
*fbbase = data[0];
*fblength = data[1];
return rc;
}
static int ivtvfb_get_osd_coords(struct ivtv *itv,
struct ivtv_osd_coords *osd)
{
struct osd_info *oi = itv->osd_info;
u32 data[CX2341X_MBOX_MAX_DATA];
ivtv_vapi_result(itv, data, CX2341X_OSD_GET_OSD_COORDS, 0);
osd->offset = data[0] - oi->video_rbase;
osd->max_offset = oi->display_width * oi->display_height * 4;
osd->pixel_stride = data[1];
osd->lines = data[2];
osd->x = data[3];
osd->y = data[4];
return 0;
}
static int ivtvfb_set_osd_coords(struct ivtv *itv, const struct ivtv_osd_coords *osd)
{
struct osd_info *oi = itv->osd_info;
oi->display_width = osd->pixel_stride;
oi->display_byte_stride = osd->pixel_stride * oi->bytes_per_pixel;
oi->set_osd_coords_x += osd->x;
oi->set_osd_coords_y = osd->y;
return ivtv_vapi(itv, CX2341X_OSD_SET_OSD_COORDS, 5,
osd->offset + oi->video_rbase,
osd->pixel_stride,
osd->lines, osd->x, osd->y);
}
static int ivtvfb_set_display_window(struct ivtv *itv, struct v4l2_rect *ivtv_window)
{
int osd_height_limit = itv->is_out_50hz ? 576 : 480;
/* Only fail if resolution too high, otherwise fudge the start coords. */
if ((ivtv_window->height > osd_height_limit) || (ivtv_window->width > IVTV_OSD_MAX_WIDTH))
return -EINVAL;
/* Ensure we don't exceed display limits */
if (ivtv_window->top + ivtv_window->height > osd_height_limit) {
IVTVFB_DEBUG_WARN("ivtv_ioctl_fb_set_display_window - Invalid height setting (%d, %d)\n",
ivtv_window->top, ivtv_window->height);
ivtv_window->top = osd_height_limit - ivtv_window->height;
}
if (ivtv_window->left + ivtv_window->width > IVTV_OSD_MAX_WIDTH) {
IVTVFB_DEBUG_WARN("ivtv_ioctl_fb_set_display_window - Invalid width setting (%d, %d)\n",
ivtv_window->left, ivtv_window->width);
ivtv_window->left = IVTV_OSD_MAX_WIDTH - ivtv_window->width;
}
/* Set the OSD origin */
write_reg((ivtv_window->top << 16) | ivtv_window->left, 0x02a04);
/* How much to display */
write_reg(((ivtv_window->top+ivtv_window->height) << 16) | (ivtv_window->left+ivtv_window->width), 0x02a08);
/* Pass this info back the yuv handler */
itv->yuv_info.osd_vis_w = ivtv_window->width;
itv->yuv_info.osd_vis_h = ivtv_window->height;
itv->yuv_info.osd_x_offset = ivtv_window->left;
itv->yuv_info.osd_y_offset = ivtv_window->top;
return 0;
}
static int ivtvfb_prep_dec_dma_to_device(struct ivtv *itv,
unsigned long ivtv_dest_addr, void __user *userbuf,
int size_in_bytes)
{
DEFINE_WAIT(wait);
int got_sig = 0;
mutex_lock(&itv->udma.lock);
/* Map User DMA */
if (ivtv_udma_setup(itv, ivtv_dest_addr, userbuf, size_in_bytes) <= 0) {
mutex_unlock(&itv->udma.lock);
IVTVFB_WARN("%s, Error in ivtv_udma_setup: %d bytes, %d pages returned\n",
__func__, size_in_bytes, itv->udma.page_count);
/* pin_user_pages or DMA must have failed completely */
return -EIO;
}
IVTVFB_DEBUG_INFO("ivtvfb_prep_dec_dma_to_device, %d bytes, %d pages\n",
size_in_bytes, itv->udma.page_count);
ivtv_udma_prepare(itv);
prepare_to_wait(&itv->dma_waitq, &wait, TASK_INTERRUPTIBLE);
/* if no UDMA is pending and no UDMA is in progress, then the DMA
is finished */
while (test_bit(IVTV_F_I_UDMA_PENDING, &itv->i_flags) ||
test_bit(IVTV_F_I_UDMA, &itv->i_flags)) {
/* don't interrupt if the DMA is in progress but break off
a still pending DMA. */
got_sig = signal_pending(current);
if (got_sig && test_and_clear_bit(IVTV_F_I_UDMA_PENDING, &itv->i_flags))
break;
got_sig = 0;
schedule();
}
finish_wait(&itv->dma_waitq, &wait);
/* Unmap Last DMA Xfer */
ivtv_udma_unmap(itv);
mutex_unlock(&itv->udma.lock);
if (got_sig) {
IVTV_DEBUG_INFO("User stopped OSD\n");
return -EINTR;
}
return 0;
}
static int ivtvfb_prep_frame(struct ivtv *itv, int cmd, void __user *source,
unsigned long dest_offset, int count)
{
DEFINE_WAIT(wait);
struct osd_info *oi = itv->osd_info;
/* Nothing to do */
if (count == 0) {
IVTVFB_DEBUG_WARN("ivtvfb_prep_frame: Nothing to do. count = 0\n");
return -EINVAL;
}
/* Check Total FB Size */
if ((dest_offset + count) > oi->video_buffer_size) {
IVTVFB_WARN("ivtvfb_prep_frame: Overflowing the framebuffer %ld, only %d available\n",
dest_offset + count, oi->video_buffer_size);
return -E2BIG;
}
/* Not fatal, but will have undesirable results */
if ((unsigned long)source & 3)
IVTVFB_WARN("ivtvfb_prep_frame: Source address not 32 bit aligned (%p)\n",
source);
if (dest_offset & 3)
IVTVFB_WARN("ivtvfb_prep_frame: Dest offset not 32 bit aligned (%ld)\n", dest_offset);
if (count & 3)
IVTVFB_WARN("ivtvfb_prep_frame: Count not a multiple of 4 (%d)\n", count);
/* Check Source */
if (!access_ok(source + dest_offset, count)) {
IVTVFB_WARN("Invalid userspace pointer %p\n", source);
IVTVFB_DEBUG_WARN("access_ok() failed for offset 0x%08lx source %p count %d\n",
dest_offset, source, count);
return -EINVAL;
}
/* OSD Address to send DMA to */
dest_offset += IVTV_DECODER_OFFSET + oi->video_rbase;
/* Fill Buffers */
return ivtvfb_prep_dec_dma_to_device(itv, dest_offset, source, count);
}
static ssize_t ivtvfb_write(struct fb_info *info, const char __user *buf,
size_t count, loff_t *ppos)
{
unsigned long p = *ppos;
void *dst;
int err = 0;
int dma_err;
unsigned long total_size;
struct ivtv *itv = (struct ivtv *) info->par;
unsigned long dma_offset =
IVTV_DECODER_OFFSET + itv->osd_info->video_rbase;
unsigned long dma_size;
u16 lead = 0, tail = 0;
if (!info->screen_base)
return -ENODEV;
total_size = info->screen_size;
if (total_size == 0)
total_size = info->fix.smem_len;
if (p > total_size)
return -EFBIG;
if (count > total_size) {
err = -EFBIG;
count = total_size;
}
if (count + p > total_size) {
if (!err)
err = -ENOSPC;
count = total_size - p;
}
dst = (void __force *) (info->screen_base + p);
if (info->fbops->fb_sync)
info->fbops->fb_sync(info);
/* If transfer size > threshold and both src/dst
addresses are aligned, use DMA */
if (count >= 4096 &&
((unsigned long)buf & 3) == ((unsigned long)dst & 3)) {
/* Odd address = can't DMA. Align */
if ((unsigned long)dst & 3) {
lead = 4 - ((unsigned long)dst & 3);
if (copy_from_user(dst, buf, lead))
return -EFAULT;
buf += lead;
dst += lead;
}
/* DMA resolution is 32 bits */
if ((count - lead) & 3)
tail = (count - lead) & 3;
/* DMA the data */
dma_size = count - lead - tail;
dma_err = ivtvfb_prep_dec_dma_to_device(itv,
p + lead + dma_offset, (void __user *)buf, dma_size);
if (dma_err)
return dma_err;
dst += dma_size;
buf += dma_size;
/* Copy any leftover data */
if (tail && copy_from_user(dst, buf, tail))
return -EFAULT;
} else if (copy_from_user(dst, buf, count)) {
return -EFAULT;
}
if (!err)
*ppos += count;
return (err) ? err : count;
}
static int ivtvfb_ioctl(struct fb_info *info, unsigned int cmd, unsigned long arg)
{
DEFINE_WAIT(wait);
struct ivtv *itv = (struct ivtv *)info->par;
int rc = 0;
switch (cmd) {
case FBIOGET_VBLANK: {
struct fb_vblank vblank;
u32 trace;
memset(&vblank, 0, sizeof(struct fb_vblank));
vblank.flags = FB_VBLANK_HAVE_COUNT |FB_VBLANK_HAVE_VCOUNT |
FB_VBLANK_HAVE_VSYNC;
trace = read_reg(IVTV_REG_DEC_LINE_FIELD) >> 16;
if (itv->is_out_50hz && trace > 312)
trace -= 312;
else if (itv->is_out_60hz && trace > 262)
trace -= 262;
if (trace == 1)
vblank.flags |= FB_VBLANK_VSYNCING;
vblank.count = itv->last_vsync_field;
vblank.vcount = trace;
vblank.hcount = 0;
if (copy_to_user((void __user *)arg, &vblank, sizeof(vblank)))
return -EFAULT;
return 0;
}
case FBIO_WAITFORVSYNC:
prepare_to_wait(&itv->vsync_waitq, &wait, TASK_INTERRUPTIBLE);
if (!schedule_timeout(msecs_to_jiffies(50)))
rc = -ETIMEDOUT;
finish_wait(&itv->vsync_waitq, &wait);
return rc;
case IVTVFB_IOC_DMA_FRAME: {
struct ivtvfb_dma_frame args;
IVTVFB_DEBUG_INFO("IVTVFB_IOC_DMA_FRAME\n");
if (copy_from_user(&args, (void __user *)arg, sizeof(args)))
return -EFAULT;
return ivtvfb_prep_frame(itv, cmd, args.source, args.dest_offset, args.count);
}
default:
IVTVFB_DEBUG_INFO("Unknown ioctl %08x\n", cmd);
return -EINVAL;
}
return 0;
}
/* Framebuffer device handling */
static int ivtvfb_set_var(struct ivtv *itv, struct fb_var_screeninfo *var)
{
struct osd_info *oi = itv->osd_info;
struct ivtv_osd_coords ivtv_osd;
struct v4l2_rect ivtv_window;
int osd_mode = -1;
IVTVFB_DEBUG_INFO("ivtvfb_set_var\n");
/* Select color space */
if (var->nonstd) /* YUV */
write_reg(read_reg(0x02a00) | 0x0002000, 0x02a00);
else /* RGB */
write_reg(read_reg(0x02a00) & ~0x0002000, 0x02a00);
/* Set the color mode */
switch (var->bits_per_pixel) {
case 8:
osd_mode = IVTV_OSD_BPP_8;
break;
case 32:
osd_mode = IVTV_OSD_BPP_32;
break;
case 16:
switch (var->green.length) {
case 4:
osd_mode = IVTV_OSD_BPP_16_444;
break;
case 5:
osd_mode = IVTV_OSD_BPP_16_555;
break;
case 6:
osd_mode = IVTV_OSD_BPP_16_565;
break;
default:
IVTVFB_DEBUG_WARN("ivtvfb_set_var - Invalid bpp\n");
}
break;
default:
IVTVFB_DEBUG_WARN("ivtvfb_set_var - Invalid bpp\n");
}
/* Set video mode. Although rare, the display can become scrambled even
if we don't change mode. Always 'bounce' to osd_mode via mode 0 */
if (osd_mode != -1) {
ivtv_vapi(itv, CX2341X_OSD_SET_PIXEL_FORMAT, 1, 0);
ivtv_vapi(itv, CX2341X_OSD_SET_PIXEL_FORMAT, 1, osd_mode);
}
oi->bits_per_pixel = var->bits_per_pixel;
oi->bytes_per_pixel = var->bits_per_pixel / 8;
/* Set the flicker filter */
switch (var->vmode & FB_VMODE_MASK) {
case FB_VMODE_NONINTERLACED: /* Filter on */
ivtv_vapi(itv, CX2341X_OSD_SET_FLICKER_STATE, 1, 1);
break;
case FB_VMODE_INTERLACED: /* Filter off */
ivtv_vapi(itv, CX2341X_OSD_SET_FLICKER_STATE, 1, 0);
break;
default:
IVTVFB_DEBUG_WARN("ivtvfb_set_var - Invalid video mode\n");
}
/* Read the current osd info */
ivtvfb_get_osd_coords(itv, &ivtv_osd);
/* Now set the OSD to the size we want */
ivtv_osd.pixel_stride = var->xres_virtual;
ivtv_osd.lines = var->yres_virtual;
ivtv_osd.x = 0;
ivtv_osd.y = 0;
ivtvfb_set_osd_coords(itv, &ivtv_osd);
/* Can't seem to find the right API combo for this.
Use another function which does what we need through direct register access. */
ivtv_window.width = var->xres;
ivtv_window.height = var->yres;
/* Minimum margin cannot be 0, as X won't allow such a mode */
if (!var->upper_margin)
var->upper_margin++;
if (!var->left_margin)
var->left_margin++;
ivtv_window.top = var->upper_margin - 1;
ivtv_window.left = var->left_margin - 1;
ivtvfb_set_display_window(itv, &ivtv_window);
/* Pass screen size back to yuv handler */
itv->yuv_info.osd_full_w = ivtv_osd.pixel_stride;
itv->yuv_info.osd_full_h = ivtv_osd.lines;
/* Force update of yuv registers */
itv->yuv_info.yuv_forced_update = 1;
/* Keep a copy of these settings */
memcpy(&oi->fbvar_cur, var, sizeof(oi->fbvar_cur));
IVTVFB_DEBUG_INFO("Display size: %dx%d (virtual %dx%d) @ %dbpp\n",
var->xres, var->yres,
var->xres_virtual, var->yres_virtual,
var->bits_per_pixel);
IVTVFB_DEBUG_INFO("Display position: %d, %d\n",
var->left_margin, var->upper_margin);
IVTVFB_DEBUG_INFO("Display filter: %s\n",
(var->vmode & FB_VMODE_MASK) == FB_VMODE_NONINTERLACED ? "on" : "off");
IVTVFB_DEBUG_INFO("Color space: %s\n", var->nonstd ? "YUV" : "RGB");
return 0;
}
static int ivtvfb_get_fix(struct ivtv *itv, struct fb_fix_screeninfo *fix)
{
struct osd_info *oi = itv->osd_info;
IVTVFB_DEBUG_INFO("ivtvfb_get_fix\n");
memset(fix, 0, sizeof(struct fb_fix_screeninfo));
strscpy(fix->id, "cx23415 TV out", sizeof(fix->id));
fix->smem_start = oi->video_pbase;
fix->smem_len = oi->video_buffer_size;
fix->type = FB_TYPE_PACKED_PIXELS;
fix->visual = (oi->bits_per_pixel == 8) ? FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_TRUECOLOR;
fix->xpanstep = 1;
fix->ypanstep = 1;
fix->ywrapstep = 0;
fix->line_length = oi->display_byte_stride;
fix->accel = FB_ACCEL_NONE;
return 0;
}
/* Check the requested display mode, returning -EINVAL if we can't
handle it. */
static int _ivtvfb_check_var(struct fb_var_screeninfo *var, struct ivtv *itv)
{
struct osd_info *oi = itv->osd_info;
int osd_height_limit;
u32 pixclock, hlimit, vlimit;
IVTVFB_DEBUG_INFO("ivtvfb_check_var\n");
/* Set base references for mode calcs. */
if (itv->is_out_50hz) {
pixclock = 84316;
hlimit = 776;
vlimit = 591;
osd_height_limit = 576;
}
else {
pixclock = 83926;
hlimit = 776;
vlimit = 495;
osd_height_limit = 480;
}
if (var->bits_per_pixel == 8 || var->bits_per_pixel == 32) {
var->transp.offset = 24;
var->transp.length = 8;
var->red.offset = 16;
var->red.length = 8;
var->green.offset = 8;
var->green.length = 8;
var->blue.offset = 0;
var->blue.length = 8;
}
else if (var->bits_per_pixel == 16) {
/* To find out the true mode, check green length */
switch (var->green.length) {
case 4:
var->red.offset = 8;
var->red.length = 4;
var->green.offset = 4;
var->green.length = 4;
var->blue.offset = 0;
var->blue.length = 4;
var->transp.offset = 12;
var->transp.length = 1;
break;
case 5:
var->red.offset = 10;
var->red.length = 5;
var->green.offset = 5;
var->green.length = 5;
var->blue.offset = 0;
var->blue.length = 5;
var->transp.offset = 15;
var->transp.length = 1;
break;
default:
var->red.offset = 11;
var->red.length = 5;
var->green.offset = 5;
var->green.length = 6;
var->blue.offset = 0;
var->blue.length = 5;
var->transp.offset = 0;
var->transp.length = 0;
break;
}
}
else {
IVTVFB_DEBUG_WARN("Invalid colour mode: %d\n", var->bits_per_pixel);
return -EINVAL;
}
/* Check the resolution */
if (var->xres > IVTV_OSD_MAX_WIDTH || var->yres > osd_height_limit) {
IVTVFB_DEBUG_WARN("Invalid resolution: %dx%d\n",
var->xres, var->yres);
return -EINVAL;
}
/* Max horizontal size is 1023 @ 32bpp, 2046 & 16bpp, 4092 @ 8bpp */
if (var->xres_virtual > 4095 / (var->bits_per_pixel / 8) ||
var->xres_virtual * var->yres_virtual * (var->bits_per_pixel / 8) > oi->video_buffer_size ||
var->xres_virtual < var->xres ||
var->yres_virtual < var->yres) {
IVTVFB_DEBUG_WARN("Invalid virtual resolution: %dx%d\n",
var->xres_virtual, var->yres_virtual);
return -EINVAL;
}
/* Some extra checks if in 8 bit mode */
if (var->bits_per_pixel == 8) {
/* Width must be a multiple of 4 */
if (var->xres & 3) {
IVTVFB_DEBUG_WARN("Invalid resolution for 8bpp: %d\n", var->xres);
return -EINVAL;
}
if (var->xres_virtual & 3) {
IVTVFB_DEBUG_WARN("Invalid virtual resolution for 8bpp: %d)\n", var->xres_virtual);
return -EINVAL;
}
}
else if (var->bits_per_pixel == 16) {
/* Width must be a multiple of 2 */
if (var->xres & 1) {
IVTVFB_DEBUG_WARN("Invalid resolution for 16bpp: %d\n", var->xres);
return -EINVAL;
}
if (var->xres_virtual & 1) {
IVTVFB_DEBUG_WARN("Invalid virtual resolution for 16bpp: %d)\n", var->xres_virtual);
return -EINVAL;
}
}
/* Now check the offsets */
if (var->xoffset >= var->xres_virtual || var->yoffset >= var->yres_virtual) {
IVTVFB_DEBUG_WARN("Invalid offset: %d (%d) %d (%d)\n",
var->xoffset, var->xres_virtual, var->yoffset, var->yres_virtual);
return -EINVAL;
}
/* Check pixel format */
if (var->nonstd > 1) {
IVTVFB_DEBUG_WARN("Invalid nonstd % d\n", var->nonstd);
return -EINVAL;
}
/* Check video mode */
if (((var->vmode & FB_VMODE_MASK) != FB_VMODE_NONINTERLACED) &&
((var->vmode & FB_VMODE_MASK) != FB_VMODE_INTERLACED)) {
IVTVFB_DEBUG_WARN("Invalid video mode: %d\n", var->vmode & FB_VMODE_MASK);
return -EINVAL;
}
/* Check the left & upper margins
If the margins are too large, just center the screen
(enforcing margins causes too many problems) */
if (var->left_margin + var->xres > IVTV_OSD_MAX_WIDTH + 1)
var->left_margin = 1 + ((IVTV_OSD_MAX_WIDTH - var->xres) / 2);
if (var->upper_margin + var->yres > (itv->is_out_50hz ? 577 : 481))
var->upper_margin = 1 + (((itv->is_out_50hz ? 576 : 480) -
var->yres) / 2);
/* Maintain overall 'size' for a constant refresh rate */
var->right_margin = hlimit - var->left_margin - var->xres;
var->lower_margin = vlimit - var->upper_margin - var->yres;
/* Fixed sync times */
var->hsync_len = 24;
var->vsync_len = 2;
/* Non-interlaced / interlaced mode is used to switch the OSD filter
on or off. Adjust the clock timings to maintain a constant
vertical refresh rate. */
if ((var->vmode & FB_VMODE_MASK) == FB_VMODE_NONINTERLACED)
var->pixclock = pixclock / 2;
else
var->pixclock = pixclock;
itv->osd_rect.width = var->xres;
itv->osd_rect.height = var->yres;
IVTVFB_DEBUG_INFO("Display size: %dx%d (virtual %dx%d) @ %dbpp\n",
var->xres, var->yres,
var->xres_virtual, var->yres_virtual,
var->bits_per_pixel);
IVTVFB_DEBUG_INFO("Display position: %d, %d\n",
var->left_margin, var->upper_margin);
IVTVFB_DEBUG_INFO("Display filter: %s\n",
(var->vmode & FB_VMODE_MASK) == FB_VMODE_NONINTERLACED ? "on" : "off");
IVTVFB_DEBUG_INFO("Color space: %s\n", var->nonstd ? "YUV" : "RGB");
return 0;
}
static int ivtvfb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
{
struct ivtv *itv = (struct ivtv *) info->par;
IVTVFB_DEBUG_INFO("ivtvfb_check_var\n");
return _ivtvfb_check_var(var, itv);
}
static int ivtvfb_pan_display(struct fb_var_screeninfo *var, struct fb_info *info)
{
u32 osd_pan_index;
struct ivtv *itv = (struct ivtv *) info->par;
if (var->yoffset + info->var.yres > info->var.yres_virtual ||
var->xoffset + info->var.xres > info->var.xres_virtual)
return -EINVAL;
osd_pan_index = var->yoffset * info->fix.line_length
+ var->xoffset * info->var.bits_per_pixel / 8;
write_reg(osd_pan_index, 0x02A0C);
/* Pass this info back the yuv handler */
itv->yuv_info.osd_x_pan = var->xoffset;
itv->yuv_info.osd_y_pan = var->yoffset;
/* Force update of yuv registers */
itv->yuv_info.yuv_forced_update = 1;
/* Remember this value */
itv->osd_info->pan_cur = osd_pan_index;
return 0;
}
static int ivtvfb_set_par(struct fb_info *info)
{
int rc = 0;
struct ivtv *itv = (struct ivtv *) info->par;
IVTVFB_DEBUG_INFO("ivtvfb_set_par\n");
rc = ivtvfb_set_var(itv, &info->var);
ivtvfb_pan_display(&info->var, info);
ivtvfb_get_fix(itv, &info->fix);
ivtv_firmware_check(itv, "ivtvfb_set_par");
return rc;
}
static int ivtvfb_setcolreg(unsigned regno, unsigned red, unsigned green,
unsigned blue, unsigned transp,
struct fb_info *info)
{
u32 color, *palette;
struct ivtv *itv = (struct ivtv *)info->par;
if (regno >= info->cmap.len)
return -EINVAL;
color = ((transp & 0xFF00) << 16) |((red & 0xFF00) << 8) | (green & 0xFF00) | ((blue & 0xFF00) >> 8);
if (info->var.bits_per_pixel <= 8) {
write_reg(regno, 0x02a30);
write_reg(color, 0x02a34);
itv->osd_info->palette_cur[regno] = color;
return 0;
}
if (regno >= 16)
return -EINVAL;
palette = info->pseudo_palette;
if (info->var.bits_per_pixel == 16) {
switch (info->var.green.length) {
case 4:
color = ((red & 0xf000) >> 4) |
((green & 0xf000) >> 8) |
((blue & 0xf000) >> 12);
break;
case 5:
color = ((red & 0xf800) >> 1) |
((green & 0xf800) >> 6) |
((blue & 0xf800) >> 11);
break;
case 6:
color = (red & 0xf800 ) |
((green & 0xfc00) >> 5) |
((blue & 0xf800) >> 11);
break;
}
}
palette[regno] = color;
return 0;
}
/* We don't really support blanking. All this does is enable or
disable the OSD. */
static int ivtvfb_blank(int blank_mode, struct fb_info *info)
{
struct ivtv *itv = (struct ivtv *)info->par;
IVTVFB_DEBUG_INFO("Set blanking mode : %d\n", blank_mode);
switch (blank_mode) {
case FB_BLANK_UNBLANK:
ivtv_vapi(itv, CX2341X_OSD_SET_STATE, 1, 1);
ivtv_call_hw(itv, IVTV_HW_SAA7127, video, s_stream, 1);
break;
case FB_BLANK_NORMAL:
case FB_BLANK_HSYNC_SUSPEND:
case FB_BLANK_VSYNC_SUSPEND:
ivtv_vapi(itv, CX2341X_OSD_SET_STATE, 1, 0);
ivtv_call_hw(itv, IVTV_HW_SAA7127, video, s_stream, 1);
break;
case FB_BLANK_POWERDOWN:
ivtv_call_hw(itv, IVTV_HW_SAA7127, video, s_stream, 0);
ivtv_vapi(itv, CX2341X_OSD_SET_STATE, 1, 0);
break;
}
itv->osd_info->blank_cur = blank_mode;
return 0;
}
static const struct fb_ops ivtvfb_ops = {
.owner = THIS_MODULE,
.fb_read = fb_io_read,
.fb_write = ivtvfb_write,
.fb_check_var = ivtvfb_check_var,
.fb_set_par = ivtvfb_set_par,
.fb_setcolreg = ivtvfb_setcolreg,
__FB_DEFAULT_IOMEM_OPS_DRAW,
.fb_cursor = NULL,
.fb_ioctl = ivtvfb_ioctl,
.fb_pan_display = ivtvfb_pan_display,
.fb_blank = ivtvfb_blank,
__FB_DEFAULT_IOMEM_OPS_MMAP,
};
/* Restore hardware after firmware restart */
static void ivtvfb_restore(struct ivtv *itv)
{
struct osd_info *oi = itv->osd_info;
int i;
ivtvfb_set_var(itv, &oi->fbvar_cur);
ivtvfb_blank(oi->blank_cur, &oi->ivtvfb_info);
for (i = 0; i < 256; i++) {
write_reg(i, 0x02a30);
write_reg(oi->palette_cur[i], 0x02a34);
}
write_reg(oi->pan_cur, 0x02a0c);
}
/* Initialization */
/* Setup our initial video mode */
static int ivtvfb_init_vidmode(struct ivtv *itv)
{
struct osd_info *oi = itv->osd_info;
struct v4l2_rect start_window;
int max_height;
/* Color mode */
if (osd_depth != 8 && osd_depth != 16 && osd_depth != 32)
osd_depth = 8;
oi->bits_per_pixel = osd_depth;
oi->bytes_per_pixel = oi->bits_per_pixel / 8;
/* Horizontal size & position */
if (osd_xres > 720)
osd_xres = 720;
/* Must be a multiple of 4 for 8bpp & 2 for 16bpp */
if (osd_depth == 8)
osd_xres &= ~3;
else if (osd_depth == 16)
osd_xres &= ~1;
start_window.width = osd_xres ? osd_xres : 640;
/* Check horizontal start (osd_left). */
if (osd_left && osd_left + start_window.width > 721) {
IVTVFB_ERR("Invalid osd_left - assuming default\n");
osd_left = 0;
}
/* Hardware coords start at 0, user coords start at 1. */
osd_left--;
start_window.left = osd_left >= 0 ?
osd_left : ((IVTV_OSD_MAX_WIDTH - start_window.width) / 2);
oi->display_byte_stride =
start_window.width * oi->bytes_per_pixel;
/* Vertical size & position */
max_height = itv->is_out_50hz ? 576 : 480;
if (osd_yres > max_height)
osd_yres = max_height;
start_window.height = osd_yres ?
osd_yres : itv->is_out_50hz ? 480 : 400;
/* Check vertical start (osd_upper). */
if (osd_upper + start_window.height > max_height + 1) {
IVTVFB_ERR("Invalid osd_upper - assuming default\n");
osd_upper = 0;
}
/* Hardware coords start at 0, user coords start at 1. */
osd_upper--;
start_window.top = osd_upper >= 0 ? osd_upper : ((max_height - start_window.height) / 2);
oi->display_width = start_window.width;
oi->display_height = start_window.height;
/* Generate a valid fb_var_screeninfo */
oi->ivtvfb_defined.xres = oi->display_width;
oi->ivtvfb_defined.yres = oi->display_height;
oi->ivtvfb_defined.xres_virtual = oi->display_width;
oi->ivtvfb_defined.yres_virtual = oi->display_height;
oi->ivtvfb_defined.bits_per_pixel = oi->bits_per_pixel;
oi->ivtvfb_defined.vmode = (osd_laced ? FB_VMODE_INTERLACED : FB_VMODE_NONINTERLACED);
oi->ivtvfb_defined.left_margin = start_window.left + 1;
oi->ivtvfb_defined.upper_margin = start_window.top + 1;
oi->ivtvfb_defined.accel_flags = FB_ACCEL_NONE;
oi->ivtvfb_defined.nonstd = 0;
/* We've filled in the most data, let the usual mode check
routine fill in the rest. */
_ivtvfb_check_var(&oi->ivtvfb_defined, itv);
/* Generate valid fb_fix_screeninfo */
ivtvfb_get_fix(itv, &oi->ivtvfb_fix);
/* Generate valid fb_info */
oi->ivtvfb_info.node = -1;
oi->ivtvfb_info.par = itv;
oi->ivtvfb_info.var = oi->ivtvfb_defined;
oi->ivtvfb_info.fix = oi->ivtvfb_fix;
oi->ivtvfb_info.screen_base = (u8 __iomem *)oi->video_vbase;
oi->ivtvfb_info.fbops = &ivtvfb_ops;
/* Supply some monitor specs. Bogus values will do for now */
oi->ivtvfb_info.monspecs.hfmin = 8000;
oi->ivtvfb_info.monspecs.hfmax = 70000;
oi->ivtvfb_info.monspecs.vfmin = 10;
oi->ivtvfb_info.monspecs.vfmax = 100;
/* Allocate color map */
if (fb_alloc_cmap(&oi->ivtvfb_info.cmap, 256, 1)) {
IVTVFB_ERR("abort, unable to alloc cmap\n");
return -ENOMEM;
}
/* Allocate the pseudo palette */
oi->ivtvfb_info.pseudo_palette =
kmalloc_array(16, sizeof(u32), GFP_KERNEL|__GFP_NOWARN);
if (!oi->ivtvfb_info.pseudo_palette) {
IVTVFB_ERR("abort, unable to alloc pseudo palette\n");
return -ENOMEM;
}
return 0;
}
/* Find OSD buffer base & size. Add to mtrr. Zero osd buffer. */
static int ivtvfb_init_io(struct ivtv *itv)
{
struct osd_info *oi = itv->osd_info;
/* Find the largest power of two that maps the whole buffer */
int size_shift = 31;
mutex_lock(&itv->serialize_lock);
if (ivtv_init_on_first_open(itv)) {
mutex_unlock(&itv->serialize_lock);
IVTVFB_ERR("Failed to initialize ivtv\n");
return -ENXIO;
}
mutex_unlock(&itv->serialize_lock);
if (ivtvfb_get_framebuffer(itv, &oi->video_rbase,
&oi->video_buffer_size) < 0) {
IVTVFB_ERR("Firmware failed to respond\n");
return -EIO;
}
/* The osd buffer size depends on the number of video buffers allocated
on the PVR350 itself. For now we'll hardcode the smallest osd buffer
size to prevent any overlap. */
oi->video_buffer_size = 1704960;
oi->video_pbase = itv->base_addr + IVTV_DECODER_OFFSET + oi->video_rbase;
oi->video_vbase = itv->dec_mem + oi->video_rbase;
if (!oi->video_vbase) {
IVTVFB_ERR("abort, video memory 0x%x @ 0x%lx isn't mapped!\n",
oi->video_buffer_size, oi->video_pbase);
return -EIO;
}
IVTVFB_INFO("Framebuffer at 0x%lx, mapped to 0x%p, size %dk\n",
oi->video_pbase, oi->video_vbase,
oi->video_buffer_size / 1024);
while (!(oi->video_buffer_size & (1 << size_shift)))
size_shift--;
size_shift++;
oi->fb_start_aligned_physaddr = oi->video_pbase & ~((1 << size_shift) - 1);
oi->fb_end_aligned_physaddr = oi->video_pbase + oi->video_buffer_size;
oi->fb_end_aligned_physaddr += (1 << size_shift) - 1;
oi->fb_end_aligned_physaddr &= ~((1 << size_shift) - 1);
oi->wc_cookie = arch_phys_wc_add(oi->fb_start_aligned_physaddr,
oi->fb_end_aligned_physaddr -
oi->fb_start_aligned_physaddr);
/* Blank the entire osd. */
memset_io(oi->video_vbase, 0, oi->video_buffer_size);
return 0;
}
/* Release any memory we've grabbed & remove mtrr entry */
static void ivtvfb_release_buffers (struct ivtv *itv)
{
struct osd_info *oi = itv->osd_info;
/* Release cmap */
if (oi->ivtvfb_info.cmap.len)
fb_dealloc_cmap(&oi->ivtvfb_info.cmap);
/* Release pseudo palette */
kfree(oi->ivtvfb_info.pseudo_palette);
arch_phys_wc_del(oi->wc_cookie);
kfree(oi);
itv->osd_info = NULL;
}
/* Initialize the specified card */
static int ivtvfb_init_card(struct ivtv *itv)
{
int rc;
#if defined(CONFIG_X86_64) && !defined(CONFIG_UML)
if (pat_enabled()) {
if (ivtvfb_force_pat) {
pr_info("PAT is enabled. Write-combined framebuffer caching will be disabled.\n");
pr_info("To enable caching, boot with nopat kernel parameter\n");
} else {
pr_warn("ivtvfb needs PAT disabled for write-combined framebuffer caching.\n");
pr_warn("Boot with nopat kernel parameter to use caching, or use the\n");
pr_warn("force_pat module parameter to run with caching disabled\n");
return -ENODEV;
}
}
#endif
if (itv->osd_info) {
IVTVFB_ERR("Card %d already initialised\n", ivtvfb_card_id);
return -EBUSY;
}
itv->osd_info = kzalloc(sizeof(struct osd_info),
GFP_KERNEL|__GFP_NOWARN);
if (itv->osd_info == NULL) {
IVTVFB_ERR("Failed to allocate memory for osd_info\n");
return -ENOMEM;
}
/* Find & setup the OSD buffer */
rc = ivtvfb_init_io(itv);
if (rc) {
ivtvfb_release_buffers(itv);
return rc;
}
/* Set the startup video mode information */
if ((rc = ivtvfb_init_vidmode(itv))) {
ivtvfb_release_buffers(itv);
return rc;
}
/* Register the framebuffer */
if (register_framebuffer(&itv->osd_info->ivtvfb_info) < 0) {
ivtvfb_release_buffers(itv);
return -EINVAL;
}
itv->osd_video_pbase = itv->osd_info->video_pbase;
/* Set the card to the requested mode */
ivtvfb_set_par(&itv->osd_info->ivtvfb_info);
/* Set color 0 to black */
write_reg(0, 0x02a30);
write_reg(0, 0x02a34);
/* Enable the osd */
ivtvfb_blank(FB_BLANK_UNBLANK, &itv->osd_info->ivtvfb_info);
/* Enable restart */
itv->ivtvfb_restore = ivtvfb_restore;
/* Allocate DMA */
ivtv_udma_alloc(itv);
itv->streams[IVTV_DEC_STREAM_TYPE_YUV].vdev.device_caps |=
V4L2_CAP_VIDEO_OUTPUT_OVERLAY;
itv->streams[IVTV_DEC_STREAM_TYPE_MPG].vdev.device_caps |=
V4L2_CAP_VIDEO_OUTPUT_OVERLAY;
itv->v4l2_cap |= V4L2_CAP_VIDEO_OUTPUT_OVERLAY;
return 0;
}
static int __init ivtvfb_callback_init(struct device *dev, void *p)
{
struct v4l2_device *v4l2_dev = dev_get_drvdata(dev);
struct ivtv *itv = container_of(v4l2_dev, struct ivtv, v4l2_dev);
if (itv->v4l2_cap & V4L2_CAP_VIDEO_OUTPUT) {
if (ivtvfb_init_card(itv) == 0) {
IVTVFB_INFO("Framebuffer registered on %s\n",
itv->v4l2_dev.name);
(*(int *)p)++;
}
}
return 0;
}
static int ivtvfb_callback_cleanup(struct device *dev, void *p)
{
struct v4l2_device *v4l2_dev = dev_get_drvdata(dev);
struct ivtv *itv = container_of(v4l2_dev, struct ivtv, v4l2_dev);
struct osd_info *oi = itv->osd_info;
if (itv->v4l2_cap & V4L2_CAP_VIDEO_OUTPUT) {
itv->streams[IVTV_DEC_STREAM_TYPE_YUV].vdev.device_caps &=
~V4L2_CAP_VIDEO_OUTPUT_OVERLAY;
itv->streams[IVTV_DEC_STREAM_TYPE_MPG].vdev.device_caps &=
~V4L2_CAP_VIDEO_OUTPUT_OVERLAY;
itv->v4l2_cap &= ~V4L2_CAP_VIDEO_OUTPUT_OVERLAY;
unregister_framebuffer(&itv->osd_info->ivtvfb_info);
IVTVFB_INFO("Unregister framebuffer %d\n", itv->instance);
itv->ivtvfb_restore = NULL;
ivtvfb_blank(FB_BLANK_VSYNC_SUSPEND, &oi->ivtvfb_info);
ivtvfb_release_buffers(itv);
itv->osd_video_pbase = 0;
}
return 0;
}
static int __init ivtvfb_init(void)
{
struct device_driver *drv;
int registered = 0;
int err;
if (ivtvfb_card_id < -1 || ivtvfb_card_id >= IVTV_MAX_CARDS) {
pr_err("ivtvfb_card_id parameter is out of range (valid range: -1 - %d)\n",
IVTV_MAX_CARDS - 1);
return -EINVAL;
}
drv = driver_find("ivtv", &pci_bus_type);
err = driver_for_each_device(drv, NULL, ®istered, ivtvfb_callback_init);
(void)err; /* suppress compiler warning */
if (!registered) {
pr_err("no cards found\n");
return -ENODEV;
}
return 0;
}
static void ivtvfb_cleanup(void)
{
struct device_driver *drv;
int err;
pr_info("Unloading framebuffer module\n");
drv = driver_find("ivtv", &pci_bus_type);
err = driver_for_each_device(drv, NULL, NULL, ivtvfb_callback_cleanup);
(void)err; /* suppress compiler warning */
}
module_init(ivtvfb_init);
module_exit(ivtvfb_cleanup);
|
// SPDX-License-Identifier: GPL-2.0
/******************************************************************************
*
* Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved.
*
******************************************************************************/
#include <drv_types.h>
u8 rtw_validate_bssid(u8 *bssid)
{
u8 ret = true;
if (is_zero_mac_addr(bssid)
|| is_broadcast_mac_addr(bssid)
|| is_multicast_mac_addr(bssid)
) {
ret = false;
}
return ret;
}
u8 rtw_validate_ssid(struct ndis_802_11_ssid *ssid)
{
u8 ret = true;
if (ssid->ssid_length > 32) {
ret = false;
goto exit;
}
exit:
return ret;
}
u8 rtw_do_join(struct adapter *padapter)
{
struct list_head *plist, *phead;
u8 *pibss = NULL;
struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
struct __queue *queue = &(pmlmepriv->scanned_queue);
u8 ret = _SUCCESS;
spin_lock_bh(&(pmlmepriv->scanned_queue.lock));
phead = get_list_head(queue);
plist = get_next(phead);
pmlmepriv->cur_network.join_res = -2;
set_fwstate(pmlmepriv, _FW_UNDER_LINKING);
pmlmepriv->pscanned = plist;
pmlmepriv->to_join = true;
if (list_empty(&queue->queue)) {
spin_unlock_bh(&(pmlmepriv->scanned_queue.lock));
_clr_fwstate_(pmlmepriv, _FW_UNDER_LINKING);
/* when set_ssid/set_bssid for rtw_do_join(), but scanning queue is empty */
/* we try to issue sitesurvey firstly */
if (pmlmepriv->LinkDetectInfo.bBusyTraffic == false
|| rtw_to_roam(padapter) > 0
) {
/* submit site_survey_cmd */
ret = rtw_sitesurvey_cmd(padapter, &pmlmepriv->assoc_ssid, 1, NULL, 0);
if (ret != _SUCCESS)
pmlmepriv->to_join = false;
} else {
pmlmepriv->to_join = false;
ret = _FAIL;
}
goto exit;
} else {
int select_ret;
spin_unlock_bh(&(pmlmepriv->scanned_queue.lock));
select_ret = rtw_select_and_join_from_scanned_queue(pmlmepriv);
if (select_ret == _SUCCESS) {
pmlmepriv->to_join = false;
_set_timer(&pmlmepriv->assoc_timer, MAX_JOIN_TIMEOUT);
} else {
if (check_fwstate(pmlmepriv, WIFI_ADHOC_STATE) == true) {
/* submit createbss_cmd to change to a ADHOC_MASTER */
/* pmlmepriv->lock has been acquired by caller... */
struct wlan_bssid_ex *pdev_network = &(padapter->registrypriv.dev_network);
pmlmepriv->fw_state = WIFI_ADHOC_MASTER_STATE;
pibss = padapter->registrypriv.dev_network.mac_address;
memcpy(&pdev_network->ssid, &pmlmepriv->assoc_ssid, sizeof(struct ndis_802_11_ssid));
rtw_update_registrypriv_dev_network(padapter);
rtw_generate_random_ibss(pibss);
if (rtw_createbss_cmd(padapter) != _SUCCESS) {
ret = false;
goto exit;
}
pmlmepriv->to_join = false;
} else {
/* can't associate ; reset under-linking */
_clr_fwstate_(pmlmepriv, _FW_UNDER_LINKING);
/* when set_ssid/set_bssid for rtw_do_join(), but there are no desired bss in scanning queue */
/* we try to issue sitesurvey firstly */
if (pmlmepriv->LinkDetectInfo.bBusyTraffic == false
|| rtw_to_roam(padapter) > 0
) {
ret = rtw_sitesurvey_cmd(padapter, &pmlmepriv->assoc_ssid, 1, NULL, 0);
if (ret != _SUCCESS)
pmlmepriv->to_join = false;
} else {
ret = _FAIL;
pmlmepriv->to_join = false;
}
}
}
}
exit:
return ret;
}
u8 rtw_set_802_11_ssid(struct adapter *padapter, struct ndis_802_11_ssid *ssid)
{
u8 status = _SUCCESS;
struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
struct wlan_network *pnetwork = &pmlmepriv->cur_network;
netdev_dbg(padapter->pnetdev, "set ssid [%s] fw_state = 0x%08x\n",
ssid->ssid, get_fwstate(pmlmepriv));
if (padapter->hw_init_completed == false) {
status = _FAIL;
goto exit;
}
spin_lock_bh(&pmlmepriv->lock);
if (check_fwstate(pmlmepriv, _FW_UNDER_SURVEY) == true)
goto handle_tkip_countermeasure;
else if (check_fwstate(pmlmepriv, _FW_UNDER_LINKING) == true)
goto release_mlme_lock;
if (check_fwstate(pmlmepriv, _FW_LINKED|WIFI_ADHOC_MASTER_STATE) == true) {
if ((pmlmepriv->assoc_ssid.ssid_length == ssid->ssid_length) &&
(!memcmp(&pmlmepriv->assoc_ssid.ssid, ssid->ssid, ssid->ssid_length))) {
if (check_fwstate(pmlmepriv, WIFI_STATION_STATE) == false) {
if (rtw_is_same_ibss(padapter, pnetwork) == false) {
/* if in WIFI_ADHOC_MASTER_STATE | WIFI_ADHOC_STATE, create bss or rejoin again */
rtw_disassoc_cmd(padapter, 0, true);
if (check_fwstate(pmlmepriv, _FW_LINKED) == true)
rtw_indicate_disconnect(padapter);
rtw_free_assoc_resources(padapter, 1);
if (check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE) == true) {
_clr_fwstate_(pmlmepriv, WIFI_ADHOC_MASTER_STATE);
set_fwstate(pmlmepriv, WIFI_ADHOC_STATE);
}
} else {
goto release_mlme_lock;/* it means driver is in WIFI_ADHOC_MASTER_STATE, we needn't create bss again. */
}
} else {
rtw_lps_ctrl_wk_cmd(padapter, LPS_CTRL_JOINBSS, 1);
}
} else {
rtw_disassoc_cmd(padapter, 0, true);
if (check_fwstate(pmlmepriv, _FW_LINKED) == true)
rtw_indicate_disconnect(padapter);
rtw_free_assoc_resources(padapter, 1);
if (check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE) == true) {
_clr_fwstate_(pmlmepriv, WIFI_ADHOC_MASTER_STATE);
set_fwstate(pmlmepriv, WIFI_ADHOC_STATE);
}
}
}
handle_tkip_countermeasure:
if (rtw_handle_tkip_countermeasure(padapter, __func__) == _FAIL) {
status = _FAIL;
goto release_mlme_lock;
}
if (rtw_validate_ssid(ssid) == false) {
status = _FAIL;
goto release_mlme_lock;
}
memcpy(&pmlmepriv->assoc_ssid, ssid, sizeof(struct ndis_802_11_ssid));
pmlmepriv->assoc_by_bssid = false;
if (check_fwstate(pmlmepriv, _FW_UNDER_SURVEY) == true)
pmlmepriv->to_join = true;
else
status = rtw_do_join(padapter);
release_mlme_lock:
spin_unlock_bh(&pmlmepriv->lock);
exit:
return status;
}
u8 rtw_set_802_11_connect(struct adapter *padapter, u8 *bssid, struct ndis_802_11_ssid *ssid)
{
u8 status = _SUCCESS;
bool bssid_valid = true;
bool ssid_valid = true;
struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
if (!ssid || rtw_validate_ssid(ssid) == false)
ssid_valid = false;
if (!bssid || rtw_validate_bssid(bssid) == false)
bssid_valid = false;
if (!ssid_valid && !bssid_valid) {
status = _FAIL;
goto exit;
}
if (padapter->hw_init_completed == false) {
status = _FAIL;
goto exit;
}
spin_lock_bh(&pmlmepriv->lock);
netdev_dbg(padapter->pnetdev, FUNC_ADPT_FMT " fw_state = 0x%08x\n",
FUNC_ADPT_ARG(padapter), get_fwstate(pmlmepriv));
if (check_fwstate(pmlmepriv, _FW_UNDER_SURVEY) == true)
goto handle_tkip_countermeasure;
else if (check_fwstate(pmlmepriv, _FW_UNDER_LINKING) == true)
goto release_mlme_lock;
handle_tkip_countermeasure:
if (rtw_handle_tkip_countermeasure(padapter, __func__) == _FAIL) {
status = _FAIL;
goto release_mlme_lock;
}
if (ssid && ssid_valid)
memcpy(&pmlmepriv->assoc_ssid, ssid, sizeof(struct ndis_802_11_ssid));
else
memset(&pmlmepriv->assoc_ssid, 0, sizeof(struct ndis_802_11_ssid));
if (bssid && bssid_valid) {
memcpy(&pmlmepriv->assoc_bssid, bssid, ETH_ALEN);
pmlmepriv->assoc_by_bssid = true;
} else {
pmlmepriv->assoc_by_bssid = false;
}
if (check_fwstate(pmlmepriv, _FW_UNDER_SURVEY) == true)
pmlmepriv->to_join = true;
else
status = rtw_do_join(padapter);
release_mlme_lock:
spin_unlock_bh(&pmlmepriv->lock);
exit:
return status;
}
u8 rtw_set_802_11_infrastructure_mode(struct adapter *padapter,
enum ndis_802_11_network_infrastructure networktype)
{
struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
struct wlan_network *cur_network = &pmlmepriv->cur_network;
enum ndis_802_11_network_infrastructure *pold_state = &(cur_network->network.infrastructure_mode);
if (*pold_state != networktype) {
if (*pold_state == Ndis802_11APMode) {
/* change to other mode from Ndis802_11APMode */
cur_network->join_res = -1;
stop_ap_mode(padapter);
}
spin_lock_bh(&pmlmepriv->lock);
if ((check_fwstate(pmlmepriv, _FW_LINKED) == true) || (*pold_state == Ndis802_11IBSS))
rtw_disassoc_cmd(padapter, 0, true);
if ((check_fwstate(pmlmepriv, _FW_LINKED) == true) ||
(check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE) == true))
rtw_free_assoc_resources(padapter, 1);
if ((*pold_state == Ndis802_11Infrastructure) || (*pold_state == Ndis802_11IBSS)) {
if (check_fwstate(pmlmepriv, _FW_LINKED) == true)
rtw_indicate_disconnect(padapter); /* will clr Linked_state; before this function, we must have checked whether issue dis-assoc_cmd or not */
}
*pold_state = networktype;
_clr_fwstate_(pmlmepriv, ~WIFI_NULL_STATE);
switch (networktype) {
case Ndis802_11IBSS:
set_fwstate(pmlmepriv, WIFI_ADHOC_STATE);
break;
case Ndis802_11Infrastructure:
set_fwstate(pmlmepriv, WIFI_STATION_STATE);
break;
case Ndis802_11APMode:
set_fwstate(pmlmepriv, WIFI_AP_STATE);
start_ap_mode(padapter);
/* rtw_indicate_connect(padapter); */
break;
case Ndis802_11AutoUnknown:
case Ndis802_11InfrastructureMax:
break;
}
/* SecClearAllKeys(adapter); */
spin_unlock_bh(&pmlmepriv->lock);
}
return true;
}
u8 rtw_set_802_11_disassociate(struct adapter *padapter)
{
struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
spin_lock_bh(&pmlmepriv->lock);
if (check_fwstate(pmlmepriv, _FW_LINKED) == true) {
rtw_disassoc_cmd(padapter, 0, true);
rtw_indicate_disconnect(padapter);
/* modify for CONFIG_IEEE80211W, none 11w can use it */
rtw_free_assoc_resources_cmd(padapter);
rtw_pwr_wakeup(padapter);
}
spin_unlock_bh(&pmlmepriv->lock);
return true;
}
u8 rtw_set_802_11_bssid_list_scan(struct adapter *padapter, struct ndis_802_11_ssid *pssid, int ssid_max_num)
{
struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
u8 res = true;
if (!padapter) {
res = false;
goto exit;
}
if (padapter->hw_init_completed == false) {
res = false;
goto exit;
}
if ((check_fwstate(pmlmepriv, _FW_UNDER_SURVEY|_FW_UNDER_LINKING) == true) ||
(pmlmepriv->LinkDetectInfo.bBusyTraffic == true)) {
/* Scan or linking is in progress, do nothing. */
res = true;
} else {
if (rtw_is_scan_deny(padapter))
return _SUCCESS;
spin_lock_bh(&pmlmepriv->lock);
res = rtw_sitesurvey_cmd(padapter, pssid, ssid_max_num, NULL, 0);
spin_unlock_bh(&pmlmepriv->lock);
}
exit:
return res;
}
u8 rtw_set_802_11_authentication_mode(struct adapter *padapter, enum ndis_802_11_authentication_mode authmode)
{
struct security_priv *psecuritypriv = &padapter->securitypriv;
int res;
u8 ret;
psecuritypriv->ndisauthtype = authmode;
if (psecuritypriv->ndisauthtype > 3)
psecuritypriv->dot11AuthAlgrthm = dot11AuthAlgrthm_8021X;
res = rtw_set_auth(padapter, psecuritypriv);
if (res == _SUCCESS)
ret = true;
else
ret = false;
return ret;
}
u8 rtw_set_802_11_add_wep(struct adapter *padapter, struct ndis_802_11_wep *wep)
{
signed int keyid, res;
struct security_priv *psecuritypriv = &(padapter->securitypriv);
u8 ret = _SUCCESS;
keyid = wep->key_index & 0x3fffffff;
if (keyid >= 4) {
ret = false;
goto exit;
}
switch (wep->key_length) {
case 5:
psecuritypriv->dot11PrivacyAlgrthm = _WEP40_;
break;
case 13:
psecuritypriv->dot11PrivacyAlgrthm = _WEP104_;
break;
default:
psecuritypriv->dot11PrivacyAlgrthm = _NO_PRIVACY_;
break;
}
memcpy(&(psecuritypriv->dot11DefKey[keyid].skey[0]), &(wep->key_material), wep->key_length);
psecuritypriv->dot11DefKeylen[keyid] = wep->key_length;
psecuritypriv->dot11PrivacyKeyIndex = keyid;
res = rtw_set_key(padapter, psecuritypriv, keyid, 1, true);
if (res == _FAIL)
ret = false;
exit:
return ret;
}
/*
* rtw_get_cur_max_rate -
* @adapter: pointer to struct adapter structure
*
* Return 0 or 100Kbps
*/
u16 rtw_get_cur_max_rate(struct adapter *adapter)
{
int i = 0;
u16 rate = 0, max_rate = 0;
struct mlme_priv *pmlmepriv = &adapter->mlmepriv;
struct wlan_bssid_ex *pcur_bss = &pmlmepriv->cur_network.network;
struct sta_info *psta = NULL;
u8 short_GI = 0;
if ((check_fwstate(pmlmepriv, _FW_LINKED) != true)
&& (check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE) != true))
return 0;
psta = rtw_get_stainfo(&adapter->stapriv, get_bssid(pmlmepriv));
if (!psta)
return 0;
short_GI = query_ra_short_GI(psta);
if (is_supported_ht(psta->wireless_mode)) {
max_rate = rtw_mcs_rate(psta->bw_mode == CHANNEL_WIDTH_40 ? 1 : 0,
short_GI,
psta->htpriv.ht_cap.mcs.rx_mask);
} else {
while ((pcur_bss->supported_rates[i] != 0) && (pcur_bss->supported_rates[i] != 0xFF)) {
rate = pcur_bss->supported_rates[i]&0x7F;
if (rate > max_rate)
max_rate = rate;
i++;
}
max_rate = max_rate*10/2;
}
return max_rate;
}
|
/*
* Allwinner new F-series F1C100s SoC (suniv) pinctrl driver.
*
* Copyright (C) 2018 Icenowy Zheng
*
* Icenowy Zheng <[email protected]>
*
* Copyright (C) 2014 Jackie Hwang
*
* Jackie Hwang <[email protected]>
*
* Copyright (C) 2014 Chen-Yu Tsai
*
* Chen-Yu Tsai <[email protected]>
*
* Copyright (C) 2014 Maxime Ripard
*
* Maxime Ripard <[email protected]>
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/of.h>
#include <linux/pinctrl/pinctrl.h>
#include "pinctrl-sunxi.h"
static const struct sunxi_desc_pin suniv_f1c100s_pins[] = {
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 0),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "rtp"), /* X1 */
SUNXI_FUNCTION(0x4, "i2s"), /* BCLK */
SUNXI_FUNCTION(0x5, "uart1"), /* RTS */
SUNXI_FUNCTION(0x6, "spi1")), /* CS */
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 1),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "rtp"), /* X2 */
SUNXI_FUNCTION(0x4, "i2s"), /* LRCK */
SUNXI_FUNCTION(0x5, "uart1"), /* CTS */
SUNXI_FUNCTION(0x6, "spi1")), /* MOSI */
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 2),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "rtp"), /* Y1 */
SUNXI_FUNCTION(0x3, "pwm0"), /* PWM0 */
SUNXI_FUNCTION(0x4, "i2s"), /* IN */
SUNXI_FUNCTION(0x5, "uart1"), /* RX */
SUNXI_FUNCTION(0x6, "spi1")), /* CLK */
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 3),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "rtp"), /* Y2 */
SUNXI_FUNCTION(0x3, "ir0"), /* RX */
SUNXI_FUNCTION(0x4, "i2s"), /* OUT */
SUNXI_FUNCTION(0x5, "uart1"), /* TX */
SUNXI_FUNCTION(0x6, "spi1")), /* MISO */
/* Hole */
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 0),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "dram"), /* DQS0 */
SUNXI_FUNCTION(0x3, "i2c1"), /* SCK */
SUNXI_FUNCTION(0x4, "i2s"), /* BCLK */
SUNXI_FUNCTION(0x5, "uart1"), /* RTS */
SUNXI_FUNCTION(0x6, "spi1")), /* CS */
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 1),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "dram"), /* DQS1 */
SUNXI_FUNCTION(0x3, "i2c1"), /* SDA */
SUNXI_FUNCTION(0x4, "i2s"), /* LRCK */
SUNXI_FUNCTION(0x5, "uart1"), /* CTS */
SUNXI_FUNCTION(0x6, "spi1")), /* MOSI */
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 2),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "dram"), /* CKE */
SUNXI_FUNCTION(0x3, "pwm0"), /* PWM0 */
SUNXI_FUNCTION(0x4, "i2s"), /* IN */
SUNXI_FUNCTION(0x5, "uart1"), /* RX */
SUNXI_FUNCTION(0x6, "spi1")), /* CLK */
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 3),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "dram"), /* DDR_REF_D */
SUNXI_FUNCTION(0x3, "ir0"), /* RX */
SUNXI_FUNCTION(0x4, "i2s"), /* OUT */
SUNXI_FUNCTION(0x5, "uart1"), /* TX */
SUNXI_FUNCTION(0x6, "spi1")), /* MISO */
/* Hole */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 0),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "spi0"), /* CLK */
SUNXI_FUNCTION(0x3, "mmc1")), /* CLK */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 1),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "spi0"), /* CS */
SUNXI_FUNCTION(0x3, "mmc1")), /* CMD */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 2),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "spi0"), /* MISO */
SUNXI_FUNCTION(0x3, "mmc1")), /* D0 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 3),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "spi0"), /* MOSI */
SUNXI_FUNCTION(0x3, "uart0")), /* TX */
/* Hole */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 0),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd"), /* D2 */
SUNXI_FUNCTION(0x3, "i2c0"), /* SDA */
SUNXI_FUNCTION(0x4, "rsb"), /* SDA */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 0)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 1),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd"), /* D3 */
SUNXI_FUNCTION(0x3, "uart1"), /* RTS */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 1)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 2),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd"), /* D4*/
SUNXI_FUNCTION(0x3, "uart1"), /* CTS */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 2)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 3),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd"), /* D5 */
SUNXI_FUNCTION(0x3, "uart1"), /* RX */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 3)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 4),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd"), /* D6 */
SUNXI_FUNCTION(0x3, "uart1"), /* TX */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 4)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 5),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd"), /* D7 */
SUNXI_FUNCTION(0x3, "i2c1"), /* SCK */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 5)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 6),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd"), /* D10 */
SUNXI_FUNCTION(0x3, "i2c1"), /* SDA */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 6)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 7),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd"), /* D11 */
SUNXI_FUNCTION(0x3, "i2s"), /* MCLK */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 7)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 8),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd"), /* D12 */
SUNXI_FUNCTION(0x3, "i2s"), /* BCLK */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 8)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 9),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd"), /* D13 */
SUNXI_FUNCTION(0x3, "i2s"), /* LRCK */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 9)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 10),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd"), /* D14 */
SUNXI_FUNCTION(0x3, "i2s"), /* IN */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 10)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 11),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd"), /* D15 */
SUNXI_FUNCTION(0x3, "i2s"), /* OUT */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 11)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 12),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd"), /* D18 */
SUNXI_FUNCTION(0x3, "i2c0"), /* SCK */
SUNXI_FUNCTION(0x4, "rsb"), /* SCK */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 12)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 13),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd"), /* D19 */
SUNXI_FUNCTION(0x3, "uart2"), /* TX */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 13)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 14),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd"), /* D20 */
SUNXI_FUNCTION(0x3, "uart2"), /* RX */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 14)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 15),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd"), /* D21 */
SUNXI_FUNCTION(0x3, "uart2"), /* RTS */
SUNXI_FUNCTION(0x4, "i2c2"), /* SCK */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 15)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 16),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd"), /* D22 */
SUNXI_FUNCTION(0x3, "uart2"), /* CTS */
SUNXI_FUNCTION(0x4, "i2c2"), /* SDA */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 16)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 17),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd"), /* D23 */
SUNXI_FUNCTION(0x3, "spdif"), /* OUT */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 17)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 18),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd"), /* CLK */
SUNXI_FUNCTION(0x3, "spi0"), /* CS */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 18)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 19),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd"), /* DE */
SUNXI_FUNCTION(0x3, "spi0"), /* MOSI */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 19)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 20),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd"), /* HYSNC */
SUNXI_FUNCTION(0x3, "spi0"), /* CLK */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 20)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 21),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd"), /* VSYNC */
SUNXI_FUNCTION(0x3, "spi0"), /* MISO */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 21)),
/* Hole */
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 0),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "csi"), /* HSYNC */
SUNXI_FUNCTION(0x3, "lcd"), /* D0 */
SUNXI_FUNCTION(0x4, "i2c2"), /* SCK */
SUNXI_FUNCTION(0x5, "uart0"), /* RX */
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 0)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 1),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "csi"), /* VSYNC */
SUNXI_FUNCTION(0x3, "lcd"), /* D1 */
SUNXI_FUNCTION(0x4, "i2c2"), /* SDA */
SUNXI_FUNCTION(0x5, "uart0"), /* TX */
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 1)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 2),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "csi"), /* PCLK */
SUNXI_FUNCTION(0x3, "lcd"), /* D8 */
SUNXI_FUNCTION(0x4, "clk"), /* OUT */
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 2)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 3),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "csi"), /* D0 */
SUNXI_FUNCTION(0x3, "lcd"), /* D9 */
SUNXI_FUNCTION(0x4, "i2s"), /* BCLK */
SUNXI_FUNCTION(0x5, "rsb"), /* SCK */
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 3)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 4),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "csi"), /* D1 */
SUNXI_FUNCTION(0x3, "lcd"), /* D16 */
SUNXI_FUNCTION(0x4, "i2s"), /* LRCK */
SUNXI_FUNCTION(0x5, "rsb"), /* SDA */
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 4)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 5),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "csi"), /* D2 */
SUNXI_FUNCTION(0x3, "lcd"), /* D17 */
SUNXI_FUNCTION(0x4, "i2s"), /* IN */
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 5)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 6),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "csi"), /* D3 */
SUNXI_FUNCTION(0x3, "pwm1"), /* PWM1 */
SUNXI_FUNCTION(0x4, "i2s"), /* OUT */
SUNXI_FUNCTION(0x5, "spdif"), /* OUT */
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 6)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 7),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "csi"), /* D4 */
SUNXI_FUNCTION(0x3, "uart2"), /* TX */
SUNXI_FUNCTION(0x4, "spi1"), /* CS */
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 7)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 8),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "csi"), /* D5 */
SUNXI_FUNCTION(0x3, "uart2"), /* RX */
SUNXI_FUNCTION(0x4, "spi1"), /* MOSI */
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 8)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 9),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "csi"), /* D6 */
SUNXI_FUNCTION(0x3, "uart2"), /* RTS */
SUNXI_FUNCTION(0x4, "spi1"), /* CLK */
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 9)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 10),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "csi"), /* D7 */
SUNXI_FUNCTION(0x3, "uart2"), /* CTS */
SUNXI_FUNCTION(0x4, "spi1"), /* MISO */
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 10)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 11),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "clk0"), /* OUT */
SUNXI_FUNCTION(0x3, "i2c0"), /* SCK */
SUNXI_FUNCTION(0x4, "ir"), /* RX */
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 11)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 12),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "i2s"), /* MCLK */
SUNXI_FUNCTION(0x3, "i2c0"), /* SDA */
SUNXI_FUNCTION(0x4, "pwm0"), /* PWM0 */
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 12)),
/* Hole */
SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 0),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc0"), /* D1 */
SUNXI_FUNCTION(0x3, "jtag"), /* MS */
SUNXI_FUNCTION(0x4, "ir0"), /* MS */
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 0)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 1),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc0"), /* D0 */
SUNXI_FUNCTION(0x3, "dgb0"), /* DI */
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 1)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 2),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc0"), /* CLK */
SUNXI_FUNCTION(0x3, "uart0"), /* TX */
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 2)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 3),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc0"), /* CMD */
SUNXI_FUNCTION(0x3, "jtag"), /* DO */
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 3)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 4),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc0"), /* D3 */
SUNXI_FUNCTION(0x3, "uart0"), /* TX */
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 4)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 5),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc0"), /* D2 */
SUNXI_FUNCTION(0x3, "jtag"), /* CK */
SUNXI_FUNCTION(0x4, "pwm1"), /* PWM1 */
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 5)),
};
static const struct sunxi_pinctrl_desc suniv_f1c100s_pinctrl_data = {
.pins = suniv_f1c100s_pins,
.npins = ARRAY_SIZE(suniv_f1c100s_pins),
.irq_banks = 3,
};
static int suniv_pinctrl_probe(struct platform_device *pdev)
{
return sunxi_pinctrl_init(pdev,
&suniv_f1c100s_pinctrl_data);
}
static const struct of_device_id suniv_f1c100s_pinctrl_match[] = {
{ .compatible = "allwinner,suniv-f1c100s-pinctrl", },
{}
};
static struct platform_driver suniv_f1c100s_pinctrl_driver = {
.probe = suniv_pinctrl_probe,
.driver = {
.name = "suniv-f1c100s-pinctrl",
.of_match_table = suniv_f1c100s_pinctrl_match,
},
};
builtin_platform_driver(suniv_f1c100s_pinctrl_driver);
|
// SPDX-License-Identifier: MIT
/*
* Copyright © 2023 Intel Corporation
*/
#include "intel_display_types.h"
struct pci_dev;
unsigned int intel_gmch_vga_set_decode(struct pci_dev *pdev, bool enable_decode);
unsigned int intel_gmch_vga_set_decode(struct pci_dev *pdev, bool enable_decode)
{
/* ToDo: Implement the actual handling of vga decode */
return 0;
}
|
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/dts-v1/;
#include "rk322x.dtsi"
/ {
model = "Rockchip RK3228 Evaluation board";
compatible = "rockchip,rk3228-evb", "rockchip,rk3228";
aliases {
mmc0 = &emmc;
};
memory@60000000 {
device_type = "memory";
reg = <0x60000000 0x40000000>;
};
vcc_phy: regulator-vcc-phy {
compatible = "regulator-fixed";
enable-active-high;
regulator-name = "vcc_phy";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
regulator-boot-on;
};
};
&emmc {
cap-mmc-highspeed;
mmc-ddr-1_8v;
disable-wp;
non-removable;
status = "okay";
};
&gmac {
assigned-clocks = <&cru SCLK_MAC_SRC>;
assigned-clock-rates = <50000000>;
clock_in_out = "output";
phy-supply = <&vcc_phy>;
phy-mode = "rmii";
phy-handle = <&phy>;
status = "okay";
mdio {
compatible = "snps,dwmac-mdio";
#address-cells = <1>;
#size-cells = <0>;
phy: ethernet-phy@0 {
compatible = "ethernet-phy-id1234.d400", "ethernet-phy-ieee802.3-c22";
reg = <0>;
clocks = <&cru SCLK_MAC_PHY>;
resets = <&cru SRST_MACPHY>;
phy-is-integrated;
};
};
};
&tsadc {
status = "okay";
rockchip,hw-tshut-mode = <0>; /* tshut mode 0:CRU 1:GPIO */
rockchip,hw-tshut-polarity = <1>; /* tshut polarity 0:LOW 1:HIGH */
};
&uart2 {
status = "okay";
};
|
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