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module note2dds_5st_gen(clk, note, adder);
input wire clk;
input wire [6:0] note;
output [31:0] adder;
(* romstyle = "logic" *) reg [31:0] table_values;
reg [4:0] addr_reg;
wire [3:0] diap = (note < 12) ? 4'd00 :
(note < 24) ? 4'd01 :
(note < 36) ? 4'd02 :
(note < 48) ? 4'd03 :
(note < 60) ? 4'd04 :
(note < 72) ? 4'd05 :
(note < 84) ? 4'd06 :
(note < 96) ? 4'd07 :
(note < 108) ? 4'd08 :
(note < 120) ? 4'd09 : 4'd010 ;
wire [6:0] c_addr = note - (diap * 4'd012);
wire [3:0] divider = 4'd010 - diap;
always@(posedge clk) begin
addr_reg <= c_addr[3:0];
case(addr_reg)
4'd00: table_values <= 32'd0359575;
4'd01: table_values <= 32'd0380957;
4'd02: table_values <= 32'd0403610;
4'd03: table_values <= 32'd0427610;
4'd04: table_values <= 32'd0453037;
4'd05: table_values <= 32'd0479976;
4'd06: table_values <= 32'd0508516;
4'd07: table_values <= 32'd0538754;
4'd08: table_values <= 32'd0570790;
4'd09: table_values <= 32'd0604731;
4'd10: table_values <= 32'd0640691;
4'd11: table_values <= 32'd0678788;
4'd12: table_values <= 32'd0;
4'd13: table_values <= 32'd0;
4'd14: table_values <= 32'd0;
4'd15: table_values <= 32'd0;
endcase
end
assign adder = table_values >> divider;
endmodule
|
module flash_top (
wb_clk_i, wb_rst_i,
wb_dat_i, wb_dat_o, wb_adr_i, wb_sel_i, wb_we_i, wb_cyc_i,
wb_stb_i, wb_ack_o, wb_err_o,
flash_rstn, cen, oen, wen, rdy, d, a, a_oe
);
//
// I/O Ports
//
//
// Common WB signals
//
input wb_clk_i;
input wb_rst_i;
//
// WB slave i/f
//
input [31:0] wb_dat_i;
output [31:0] wb_dat_o;
input [31:0] wb_adr_i;
input [3:0] wb_sel_i;
input wb_we_i;
input wb_cyc_i;
input wb_stb_i;
output wb_ack_o;
output wb_err_o;
//
// Flash i/f
//
output flash_rstn;
output oen;
output cen;
output wen;
input rdy;
inout [7:0] d;
output [20:0] a;
output a_oe;
//
// Internal wires and regs
//
reg [7:0] mem [2097151:0];
wire [31:0] adr;
`ifdef FLASH_GENERIC_REGISTERED
reg wb_err_o;
reg [31:0] prev_adr;
reg [1:0] delay;
`else
wire [1:0] delay;
`endif
wire wb_err;
//
// Aliases and simple assignments
//
assign flash_rstn = 1'b1;
assign oen = 1'b1;
assign cen = 1'b1;
assign wen = 1'b1;
assign a = 21'b0;
assign a_oe = 1'b1;
assign wb_err = wb_cyc_i & wb_stb_i & (delay == 2'd0) & (|wb_adr_i[23:21]); // If Access to > 2MB (8-bit leading prefix ignored)
assign adr = {8'h00, wb_adr_i[23:2], 2'b00};
//
// For simulation only
//
initial $readmemh("../src/flash.in", mem, 0);
//
// Reading from flash model
//
assign wb_dat_o[7:0] = wb_adr_i[23:0] < 65535 ? mem[adr+3] : 8'h00;
assign wb_dat_o[15:8] = wb_adr_i[23:0] < 65535 ? mem[adr+2] : 8'h00;
assign wb_dat_o[23:16] = wb_adr_i[23:0] < 65535 ? mem[adr+1] : 8'h00;
assign wb_dat_o[31:24] = wb_adr_i[23:0] < 65535 ? mem[adr+0] : 8'h00;
`ifdef FLASH_GENERIC_REGISTERED
//
// WB Acknowledge
//
always @(posedge wb_clk_i or posedge wb_rst_i)
if (wb_rst_i) begin
delay <= #1 2'd3;
prev_adr <= #1 32'h0000_0000;
end
else if (delay && (wb_adr_i == prev_adr) && wb_cyc_i && wb_stb_i)
delay <= #1 delay - 2'd1;
else if (wb_ack_o || wb_err_o || (wb_adr_i != prev_adr) || ~wb_stb_i) begin
delay <= #1 2'd0; // delay ... can range from 3 to 0
prev_adr <= #1 wb_adr_i;
end
`else
assign delay = 2'd0;
`endif
assign wb_ack_o = wb_cyc_i & wb_stb_i & ~wb_err & (delay == 2'd0)
`ifdef FLASH_GENERIC_REGISTERED
& (wb_adr_i == prev_adr)
`endif
;
`ifdef FLASH_GENERIC_REGISTERED
//
// WB Error
//
always @(posedge wb_clk_i or posedge wb_rst_i)
if (wb_rst_i)
wb_err_o <= #1 1'b0;
else
wb_err_o <= #1 wb_err & !wb_err_o;
`else
assign wb_err_o = wb_err;
`endif
//
// Flash i/f monitor
//
// synopsys translate_off
integer fflash;
initial fflash = $fopen("flash.log");
always @(posedge wb_clk_i)
if (wb_cyc_i)
if (wb_stb_i & wb_we_i) begin
// $fdisplay(fflash, "%t Trying to write into flash at %h (%b)", $time, wb_adr_i, wb_we_i);
// #100 $finish;
if (wb_sel_i[3])
mem[{wb_adr_i[23:2], 2'b00}+0] = wb_dat_i[31:24];
if (wb_sel_i[2])
mem[{wb_adr_i[23:2], 2'b00}+1] = wb_dat_i[23:16];
if (wb_sel_i[1])
mem[{wb_adr_i[23:2], 2'b00}+2] = wb_dat_i[15:8];
if (wb_sel_i[0])
mem[{wb_adr_i[23:2], 2'b00}+3] = wb_dat_i[7:0];
$fdisplay(fflash, "%t [%h] <- write %h, byte sel %b", $time, wb_adr_i, wb_dat_i, wb_sel_i);
end else if (wb_ack_o)
$fdisplay(fflash, "%t [%h] -> read %h", $time, wb_adr_i, wb_dat_o);
// synopsys translate_on
endmodule
|
module flash_top (
wb_clk_i, wb_rst_i,
wb_dat_i, wb_dat_o, wb_adr_i, wb_sel_i, wb_we_i, wb_cyc_i,
wb_stb_i, wb_ack_o, wb_err_o,
flash_rstn, cen, oen, wen, rdy, d, a, a_oe
);
//
// I/O Ports
//
//
// Common WB signals
//
input wb_clk_i;
input wb_rst_i;
//
// WB slave i/f
//
input [31:0] wb_dat_i;
output [31:0] wb_dat_o;
input [31:0] wb_adr_i;
input [3:0] wb_sel_i;
input wb_we_i;
input wb_cyc_i;
input wb_stb_i;
output wb_ack_o;
output wb_err_o;
//
// Flash i/f
//
output flash_rstn;
output oen;
output cen;
output wen;
input rdy;
inout [7:0] d;
output [20:0] a;
output a_oe;
//
// Internal wires and regs
//
reg ack;
reg [3:0] middle_tphqv;
reg [31:0] wb_dat_o;
reg [4:0] counter;
//
// Aliases and simple assignments
//
assign wb_ack_o = ~wb_err_o & ack;
assign wb_err_o = 1'b0;
assign flash_rstn = ~wb_rst_i;
assign a = { ~wb_adr_i[20], wb_adr_i[19:2], counter[3:2] }; // Lower 1MB is used by FPGA design conf.
assign a_oe = (wb_cyc_i &! (|middle_tphqv));
assign oen = |middle_tphqv;
assign wen = 1'b1;
assign cen = ~wb_cyc_i | ~wb_stb_i | (|middle_tphqv) | (counter[1:0] == 2'b00);
//
// Flash access time counter
//
always @(posedge wb_clk_i or posedge wb_rst_i)
begin
if (wb_rst_i)
counter <= #1 5'h0;
else
if (!wb_cyc_i | (counter == 5'h10) | (|middle_tphqv))
counter <= #1 5'h0;
else
counter <= #1 counter + 1;
end
//
// Acknowledge
//
always @(posedge wb_clk_i or posedge wb_rst_i)
begin
if (wb_rst_i)
ack <= #1 1'h0;
else
if (counter == 5'h0f && !(|middle_tphqv))
ack <= #1 1'h1;
else
ack <= #1 1'h0;
end
//
// Flash i/f monitor
//
// synopsys translate_off
integer fflash;
initial fflash = $fopen("flash.log");
always @(posedge wb_clk_i)
begin
if (wb_cyc_i & !(|middle_tphqv)) begin
if (wb_stb_i & wb_we_i) begin
$fdisplay(fflash, "%t Trying to write into flash at %h", $time, wb_adr_i);
// #100 $finish;
end
else if (ack)
$fdisplay(fflash, "%t [%h] -> read %h", $time, wb_adr_i, wb_dat_o);
end
end
// synopsys translate_on
always @(posedge wb_clk_i or posedge wb_rst_i)
if (wb_rst_i)
middle_tphqv <= #1 4'hf;
else if (middle_tphqv)
middle_tphqv <= #1 middle_tphqv - 1;
//
// Flash 8-bit data expand into 32-bit WB data
//
always @(posedge wb_clk_i or posedge wb_rst_i)
begin
if (wb_rst_i)
wb_dat_o <= #1 32'h0000_0000;
else
if (counter[1:0] == 2'h3)
begin
case (counter[3:2])
2'h0 : wb_dat_o[31:24] <= #1 d;
2'h1 : wb_dat_o[23:16] <= #1 d;
2'h2 : wb_dat_o[15:8] <= #1 d;
2'h3 : wb_dat_o[7:0] <= #1 d;
endcase
end
end
endmodule
|
module ADT7310 (
(* intersynth_port = "Reset_n_i", src = "../../verilog/adt7310.v:3" *)
input Reset_n_i,
(* intersynth_port = "Clk_i", src = "../../verilog/adt7310.v:5" *)
input Clk_i,
(* intersynth_conntype = "Bit", intersynth_port = "ReconfModuleIn_s", src = "../../verilog/adt7310.v:7" *)
input Enable_i,
(* intersynth_conntype = "Bit", intersynth_port = "ReconfModuleIRQs_s", src = "../../verilog/adt7310.v:9" *)
output CpuIntr_o,
(* intersynth_conntype = "Bit", intersynth_port = "Outputs_o", src = "../../verilog/adt7310.v:11" *)
output ADT7310CS_n_o,
(* intersynth_conntype = "Byte", intersynth_port = "SPI_DataOut", src = "../../verilog/adt7310.v:13" *)
input[7:0] SPI_Data_i,
(* intersynth_conntype = "Bit", intersynth_port = "SPI_Write", src = "../../verilog/adt7310.v:15" *)
output SPI_Write_o,
(* intersynth_conntype = "Bit", intersynth_port = "SPI_ReadNext", src = "../../verilog/adt7310.v:17" *)
output SPI_ReadNext_o,
(* intersynth_conntype = "Byte", intersynth_port = "SPI_DataIn", src = "../../verilog/adt7310.v:19" *)
output[7:0] SPI_Data_o,
(* intersynth_conntype = "Bit", intersynth_port = "SPI_FIFOFull", src = "../../verilog/adt7310.v:21" *)
input SPI_FIFOFull_i,
(* intersynth_conntype = "Bit", intersynth_port = "SPI_FIFOEmpty", src = "../../verilog/adt7310.v:23" *)
input SPI_FIFOEmpty_i,
(* intersynth_conntype = "Bit", intersynth_port = "SPI_Transmission", src = "../../verilog/adt7310.v:25" *)
input SPI_Transmission_i,
(* intersynth_conntype = "Word", intersynth_param = "SPICounterPresetH_i", src = "../../verilog/adt7310.v:27" *)
input[15:0] SPICounterPresetH_i,
(* intersynth_conntype = "Word", intersynth_param = "SPICounterPresetL_i", src = "../../verilog/adt7310.v:29" *)
input[15:0] SPICounterPresetL_i,
(* intersynth_conntype = "Word", intersynth_param = "Threshold_i", src = "../../verilog/adt7310.v:31" *)
input[15:0] Threshold_i,
(* intersynth_conntype = "Word", intersynth_param = "PeriodCounterPreset_i", src = "../../verilog/adt7310.v:33" *)
input[15:0] PeriodCounterPreset_i,
(* intersynth_conntype = "Word", intersynth_param = "SensorValue_o", src = "../../verilog/adt7310.v:35" *)
output[15:0] SensorValue_o,
(* intersynth_conntype = "Bit", intersynth_port = "SPI_CPOL", src = "../../verilog/adt7310.v:37" *)
output SPI_CPOL_o,
(* intersynth_conntype = "Bit", intersynth_port = "SPI_CPHA", src = "../../verilog/adt7310.v:39" *)
output SPI_CPHA_o,
(* intersynth_conntype = "Bit", intersynth_port = "SPI_LSBFE", src = "../../verilog/adt7310.v:41" *)
output SPI_LSBFE_o
);
(* src = "../../verilog/spifsm.v:187" *)
wire [7:0] \$techmap\SPIFSM_1.$0\Byte0_o[7:0] ;
(* src = "../../verilog/spifsm.v:187" *)
wire [7:0] \$techmap\SPIFSM_1.$0\Byte1_o[7:0] ;
(* src = "../../verilog/spifsm.v:217" *)
wire [31:0] \$techmap\SPIFSM_1.$0\SPI_FSM_Timer[31:0] ;
(* src = "../../verilog/spifsm.v:65" *)
wire \$techmap\SPIFSM_1.$2\ADT7310CS_n_o[0:0] ;
(* src = "../../verilog/spifsm.v:65" *)
wire \$techmap\SPIFSM_1.$2\SPI_FSM_TimerEnable[0:0] ;
(* src = "../../verilog/spifsm.v:65" *)
wire \$techmap\SPIFSM_1.$2\SPI_ReadNext_o[0:0] ;
wire \$techmap\SPIFSM_1.$auto$opt_reduce.cc:126:opt_mux$2453 ;
wire \$techmap\SPIFSM_1.$auto$opt_reduce.cc:126:opt_mux$2455 ;
wire \$techmap\SPIFSM_1.$auto$opt_reduce.cc:126:opt_mux$2457 ;
wire \$techmap\SPIFSM_1.$auto$opt_reduce.cc:126:opt_mux$2459 ;
wire \$techmap\SPIFSM_1.$auto$opt_reduce.cc:126:opt_mux$2461 ;
wire \$techmap\SPIFSM_1.$auto$opt_reduce.cc:126:opt_mux$2477 ;
wire \$techmap\SPIFSM_1.$procmux$297_CMP ;
wire \$techmap\SPIFSM_1.$procmux$298_CMP ;
wire \$techmap\SPIFSM_1.$procmux$301_CMP ;
wire \$techmap\SPIFSM_1.$procmux$302_CMP ;
wire \$techmap\SPIFSM_1.$procmux$305_CMP ;
wire \$techmap\SPIFSM_1.$procmux$334_CMP ;
wire \$techmap\SPIFSM_1.$procmux$335_CMP ;
wire \$techmap\SPIFSM_1.$procmux$336_CMP ;
wire [31:0] \$techmap\SPIFSM_1.$procmux$80_Y ;
(* src = "../../verilog/spifsm.v:231" *)
wire [31:0] \$techmap\SPIFSM_1.$sub$../../verilog/spifsm.v:231$46_Y ;
(* src = "../../verilog/sensorfsm.v:130" *)
wire [15:0] \$techmap\SensorFSM_1.$0\SensorFSM_Timer[15:0] ;
(* src = "../../verilog/sensorfsm.v:153" *)
wire [15:0] \$techmap\SensorFSM_1.$0\Word0[15:0] ;
(* src = "../../verilog/sensorfsm.v:57" *)
wire \$techmap\SensorFSM_1.$2\MeasureFSM_Start_o[0:0] ;
(* src = "../../verilog/sensorfsm.v:57" *)
wire \$techmap\SensorFSM_1.$2\SensorFSM_StoreNewValue[0:0] ;
(* src = "../../verilog/sensorfsm.v:57" *)
wire \$techmap\SensorFSM_1.$2\SensorFSM_TimerPreset[0:0] ;
(* src = "../../verilog/sensorfsm.v:57" *)
wire \$techmap\SensorFSM_1.$3\SensorFSM_TimerPreset[0:0] ;
(* src = "../../verilog/sensorfsm.v:57" *)
wire \$techmap\SensorFSM_1.$4\SensorFSM_TimerPreset[0:0] ;
wire \$techmap\SensorFSM_1.$auto$opt_reduce.cc:126:opt_mux$2463 ;
wire \$techmap\SensorFSM_1.$procmux$1004_CMP ;
wire \$techmap\SensorFSM_1.$procmux$1007_CMP ;
wire \$techmap\SensorFSM_1.$procmux$1129_CMP ;
wire [15:0] \$techmap\SensorFSM_1.$procmux$826_Y ;
(* src = "../../verilog/sensorfsm.v:144" *)
wire [15:0] \$techmap\SensorFSM_1.$sub$../../verilog/sensorfsm.v:144$59_Y ;
(* src = "../../verilog/spifsm.v:24" *)
wire \SPIFSM_1.ADT7310CS_n_o ;
(* src = "../../verilog/spifsm.v:13" *)
wire [7:0] \SPIFSM_1.Byte0_o ;
(* src = "../../verilog/spifsm.v:14" *)
wire [7:0] \SPIFSM_1.Byte1_o ;
(* src = "../../verilog/spifsm.v:9" *)
wire \SPIFSM_1.Clk_i ;
(* src = "../../verilog/spifsm.v:12" *)
wire \SPIFSM_1.Done_o ;
(* src = "../../verilog/spifsm.v:26" *)
wire [31:0] \SPIFSM_1.ParamCounterPreset_i ;
(* src = "../../verilog/spifsm.v:8" *)
wire \SPIFSM_1.Reset_n_i ;
(* src = "../../verilog/spifsm.v:20" *)
wire [7:0] \SPIFSM_1.SPI_Data_i ;
(* src = "../../verilog/spifsm.v:19" *)
wire [7:0] \SPIFSM_1.SPI_Data_o ;
(* src = "../../verilog/spifsm.v:22" *)
wire \SPIFSM_1.SPI_FIFOEmpty_i ;
(* src = "../../verilog/spifsm.v:21" *)
wire \SPIFSM_1.SPI_FIFOFull_i ;
(* src = "../../verilog/spifsm.v:215" *)
wire [31:0] \SPIFSM_1.SPI_FSM_Timer ;
(* src = "../../verilog/spifsm.v:45" *)
wire \SPIFSM_1.SPI_FSM_TimerEnable ;
(* src = "../../verilog/spifsm.v:43" *)
wire \SPIFSM_1.SPI_FSM_TimerOvfl ;
(* src = "../../verilog/spifsm.v:44" *)
wire \SPIFSM_1.SPI_FSM_TimerPreset ;
(* src = "../../verilog/spifsm.v:47" *)
wire \SPIFSM_1.SPI_FSM_Wr0 ;
(* src = "../../verilog/spifsm.v:46" *)
wire \SPIFSM_1.SPI_FSM_Wr1 ;
(* src = "../../verilog/spifsm.v:18" *)
wire \SPIFSM_1.SPI_ReadNext_o ;
(* src = "../../verilog/spifsm.v:16" *)
wire \SPIFSM_1.SPI_Transmission_i ;
(* src = "../../verilog/spifsm.v:17" *)
wire \SPIFSM_1.SPI_Write_o ;
(* src = "../../verilog/spifsm.v:11" *)
wire \SPIFSM_1.Start_i ;
(* keep = 1, src = "../../verilog/adt7310.v:56" *)
wire [7:0] SPIFSM_Byte0_s;
(* keep = 1, src = "../../verilog/adt7310.v:58" *)
wire [7:0] SPIFSM_Byte1_s;
(* keep = 1, src = "../../verilog/adt7310.v:54" *)
wire SPIFSM_Done_s;
(* keep = 1, src = "../../verilog/adt7310.v:52" *)
wire SPIFSM_Start_s;
(* src = "../../verilog/sensorfsm.v:39" *)
wire [15:0] \SensorFSM_1.AbsDiffResult ;
(* src = "../../verilog/sensorfsm.v:7" *)
wire \SensorFSM_1.Clk_i ;
(* src = "../../verilog/sensorfsm.v:10" *)
wire \SensorFSM_1.CpuIntr_o ;
(* src = "../../verilog/sensorfsm.v:168" *)
wire [16:0] \SensorFSM_1.DiffAB ;
(* src = "../../verilog/sensorfsm.v:169" *)
wire [15:0] \SensorFSM_1.DiffBA ;
(* src = "../../verilog/sensorfsm.v:9" *)
wire \SensorFSM_1.Enable_i ;
(* src = "../../verilog/sensorfsm.v:15" *)
wire [7:0] \SensorFSM_1.MeasureFSM_Byte0_i ;
(* src = "../../verilog/sensorfsm.v:16" *)
wire [7:0] \SensorFSM_1.MeasureFSM_Byte1_i ;
(* src = "../../verilog/sensorfsm.v:14" *)
wire \SensorFSM_1.MeasureFSM_Done_i ;
(* src = "../../verilog/sensorfsm.v:13" *)
wire \SensorFSM_1.MeasureFSM_Start_o ;
(* src = "../../verilog/sensorfsm.v:19" *)
wire [15:0] \SensorFSM_1.ParamCounterPreset_i ;
(* src = "../../verilog/sensorfsm.v:18" *)
wire [15:0] \SensorFSM_1.ParamThreshold_i ;
(* src = "../../verilog/sensorfsm.v:6" *)
wire \SensorFSM_1.Reset_n_i ;
(* src = "../../verilog/sensorfsm.v:32" *)
wire \SensorFSM_1.SensorFSM_DiffTooLarge ;
(* src = "../../verilog/sensorfsm.v:33" *)
wire \SensorFSM_1.SensorFSM_StoreNewValue ;
(* src = "../../verilog/sensorfsm.v:128" *)
wire [15:0] \SensorFSM_1.SensorFSM_Timer ;
(* src = "../../verilog/sensorfsm.v:31" *)
wire \SensorFSM_1.SensorFSM_TimerEnable ;
(* src = "../../verilog/sensorfsm.v:29" *)
wire \SensorFSM_1.SensorFSM_TimerOvfl ;
(* src = "../../verilog/sensorfsm.v:30" *)
wire \SensorFSM_1.SensorFSM_TimerPreset ;
(* src = "../../verilog/sensorfsm.v:37" *)
wire [15:0] \SensorFSM_1.SensorValue ;
(* src = "../../verilog/sensorfsm.v:11" *)
wire [15:0] \SensorFSM_1.SensorValue_o ;
(* src = "../../verilog/sensorfsm.v:38" *)
wire [15:0] \SensorFSM_1.Word0 ;
wire SPIFSM_1_Out10_s;
wire SPIFSM_1_Out11_s;
wire SPIFSM_1_Out12_s;
wire SPIFSM_1_Out13_s;
wire SPIFSM_1_Out14_s;
wire SPIFSM_1_CfgMode_s;
wire SPIFSM_1_CfgClk_s;
wire SPIFSM_1_CfgShift_s;
wire SPIFSM_1_CfgDataIn_s;
wire SPIFSM_1_CfgDataOut_s;
wire SensorFSM_1_Out3_s;
wire SensorFSM_1_Out4_s;
wire SensorFSM_1_Out5_s;
wire SensorFSM_1_Out6_s;
wire SensorFSM_1_Out7_s;
wire SensorFSM_1_Out8_s;
wire SensorFSM_1_Out9_s;
wire SensorFSM_1_CfgMode_s;
wire SensorFSM_1_CfgClk_s;
wire SensorFSM_1_CfgShift_s;
wire SensorFSM_1_CfgDataIn_s;
wire SensorFSM_1_CfgDataOut_s;
\$reduce_or #(
.A_SIGNED(0),
.A_WIDTH(3),
.Y_WIDTH(1)
) \$techmap\SPIFSM_1.$auto$opt_reduce.cc:130:opt_mux$2454 (
.A({ \SPIFSM_1.SPI_FSM_Wr1 , \SPIFSM_1.SPI_FSM_Wr0 , \$techmap\SPIFSM_1.$procmux$298_CMP }),
.Y(\$techmap\SPIFSM_1.$auto$opt_reduce.cc:126:opt_mux$2453 )
);
\$reduce_or #(
.A_SIGNED(0),
.A_WIDTH(6),
.Y_WIDTH(1)
) \$techmap\SPIFSM_1.$auto$opt_reduce.cc:130:opt_mux$2456 (
.A({ \$techmap\SPIFSM_1.$procmux$336_CMP , \$techmap\SPIFSM_1.$procmux$335_CMP , \$techmap\SPIFSM_1.$procmux$334_CMP , \$techmap\SPIFSM_1.$procmux$302_CMP , \$techmap\SPIFSM_1.$procmux$301_CMP , \$techmap\SPIFSM_1.$procmux$298_CMP }),
.Y(\$techmap\SPIFSM_1.$auto$opt_reduce.cc:126:opt_mux$2455 )
);
\$reduce_or #(
.A_SIGNED(0),
.A_WIDTH(9),
.Y_WIDTH(1)
) \$techmap\SPIFSM_1.$auto$opt_reduce.cc:130:opt_mux$2458 (
.A({ \SPIFSM_1.SPI_FSM_Wr1 , \SPIFSM_1.SPI_FSM_Wr0 , \$techmap\SPIFSM_1.$procmux$336_CMP , \$techmap\SPIFSM_1.$procmux$335_CMP , \$techmap\SPIFSM_1.$procmux$334_CMP , \$techmap\SPIFSM_1.$procmux$302_CMP , \$techmap\SPIFSM_1.$procmux$301_CMP , \$techmap\SPIFSM_1.$procmux$298_CMP , \$techmap\SPIFSM_1.$procmux$297_CMP }),
.Y(\$techmap\SPIFSM_1.$auto$opt_reduce.cc:126:opt_mux$2457 )
);
\$reduce_or #(
.A_SIGNED(0),
.A_WIDTH(2),
.Y_WIDTH(1)
) \$techmap\SPIFSM_1.$auto$opt_reduce.cc:130:opt_mux$2460 (
.A({ \$techmap\SPIFSM_1.$procmux$336_CMP , \$techmap\SPIFSM_1.$procmux$335_CMP }),
.Y(\$techmap\SPIFSM_1.$auto$opt_reduce.cc:126:opt_mux$2459 )
);
\$reduce_or #(
.A_SIGNED(0),
.A_WIDTH(3),
.Y_WIDTH(1)
) \$techmap\SPIFSM_1.$auto$opt_reduce.cc:130:opt_mux$2462 (
.A({ \$techmap\SPIFSM_1.$procmux$336_CMP , \$techmap\SPIFSM_1.$procmux$335_CMP , \$techmap\SPIFSM_1.$procmux$302_CMP }),
.Y(\$techmap\SPIFSM_1.$auto$opt_reduce.cc:126:opt_mux$2461 )
);
\$reduce_or #(
.A_SIGNED(0),
.A_WIDTH(2),
.Y_WIDTH(1)
) \$techmap\SPIFSM_1.$auto$opt_reduce.cc:130:opt_mux$2478 (
.A({ \$techmap\SPIFSM_1.$procmux$334_CMP , \$techmap\SPIFSM_1.$procmux$301_CMP }),
.Y(\$techmap\SPIFSM_1.$auto$opt_reduce.cc:126:opt_mux$2477 )
);
(* src = "../../verilog/spifsm.v:236" *)
\$eq #(
.A_SIGNED(0),
.A_WIDTH(32),
.B_SIGNED(0),
.B_WIDTH(32),
.Y_WIDTH(1)
) \$techmap\SPIFSM_1.$eq$../../verilog/spifsm.v:236$47 (
.A(\SPIFSM_1.SPI_FSM_Timer ),
.B(0),
.Y(\SPIFSM_1.SPI_FSM_TimerOvfl )
);
SPIFSM SPIFSM_1 (
.Reset_n_i(\SPIFSM_1.Reset_n_i ),
.Clk_i(\SPIFSM_1.Clk_i ),
.In0_i(\SPIFSM_1.SPI_FSM_TimerOvfl ),
.In1_i(\SPIFSM_1.SPI_Transmission_i ),
.In2_i(\SPIFSM_1.Start_i ),
.In3_i(1'b0),
.In4_i(1'b0),
.In5_i(1'b0),
.In6_i(1'b0),
.In7_i(1'b0),
.Out0_o(\$techmap\SPIFSM_1.$procmux$297_CMP ),
.Out1_o(\$techmap\SPIFSM_1.$procmux$298_CMP ),
.Out2_o(\$techmap\SPIFSM_1.$procmux$301_CMP ),
.Out3_o(\$techmap\SPIFSM_1.$procmux$302_CMP ),
.Out4_o(\$techmap\SPIFSM_1.$procmux$305_CMP ),
.Out5_o(\$techmap\SPIFSM_1.$procmux$334_CMP ),
.Out6_o(\$techmap\SPIFSM_1.$procmux$335_CMP ),
.Out7_o(\$techmap\SPIFSM_1.$procmux$336_CMP ),
.Out8_o(\SPIFSM_1.SPI_FSM_Wr0 ),
.Out9_o(\SPIFSM_1.SPI_FSM_Wr1 ),
.Out10_o(SPIFSM_1_Out10_s),
.Out11_o(SPIFSM_1_Out11_s),
.Out12_o(SPIFSM_1_Out12_s),
.Out13_o(SPIFSM_1_Out13_s),
.Out14_o(SPIFSM_1_Out14_s),
.CfgMode_i(SPIFSM_1_CfgMode_s),
.CfgClk_i(SPIFSM_1_CfgClk_s),
.CfgShift_i(SPIFSM_1_CfgShift_s),
.CfgDataIn_i(SPIFSM_1_CfgDataIn_s),
.CfgDataOut_o(SPIFSM_1_CfgDataOut_s)
);
(* src = "../../verilog/spifsm.v:187" *)
\$adff #(
.ARST_POLARITY(1'b0),
.ARST_VALUE(8'b00000000),
.CLK_POLARITY(1'b1),
.WIDTH(8)
) \$techmap\SPIFSM_1.$procdff$2439 (
.ARST(\SPIFSM_1.Reset_n_i ),
.CLK(\SPIFSM_1.Clk_i ),
.D(\$techmap\SPIFSM_1.$0\Byte0_o[7:0] ),
.Q(\SPIFSM_1.Byte0_o )
);
(* src = "../../verilog/spifsm.v:187" *)
\$adff #(
.ARST_POLARITY(1'b0),
.ARST_VALUE(8'b00000000),
.CLK_POLARITY(1'b1),
.WIDTH(8)
) \$techmap\SPIFSM_1.$procdff$2440 (
.ARST(\SPIFSM_1.Reset_n_i ),
.CLK(\SPIFSM_1.Clk_i ),
.D(\$techmap\SPIFSM_1.$0\Byte1_o[7:0] ),
.Q(\SPIFSM_1.Byte1_o )
);
(* src = "../../verilog/spifsm.v:217" *)
\$adff #(
.ARST_POLARITY(1'b0),
.ARST_VALUE(0),
.CLK_POLARITY(1'b1),
.WIDTH(32)
) \$techmap\SPIFSM_1.$procdff$2441 (
.ARST(\SPIFSM_1.Reset_n_i ),
.CLK(\SPIFSM_1.Clk_i ),
.D(\$techmap\SPIFSM_1.$0\SPI_FSM_Timer[31:0] ),
.Q(\SPIFSM_1.SPI_FSM_Timer )
);
\$pmux #(
.S_WIDTH(2),
.WIDTH(1)
) \$techmap\SPIFSM_1.$procmux$296 (
.A(1'b0),
.B({ 1'b1, \$techmap\SPIFSM_1.$2\SPI_FSM_TimerEnable[0:0] }),
.S({ \$techmap\SPIFSM_1.$procmux$298_CMP , \$techmap\SPIFSM_1.$procmux$297_CMP }),
.Y(\SPIFSM_1.SPI_FSM_TimerEnable )
);
\$pmux #(
.S_WIDTH(2),
.WIDTH(1)
) \$techmap\SPIFSM_1.$procmux$317 (
.A(1'b1),
.B({ 1'b0, \SPIFSM_1.SPI_FSM_TimerOvfl }),
.S({ \$techmap\SPIFSM_1.$procmux$298_CMP , \$techmap\SPIFSM_1.$procmux$297_CMP }),
.Y(\SPIFSM_1.SPI_FSM_TimerPreset )
);
\$pmux #(
.S_WIDTH(2),
.WIDTH(1)
) \$techmap\SPIFSM_1.$procmux$371 (
.A(1'b0),
.B({ \$techmap\SPIFSM_1.$2\SPI_ReadNext_o[0:0] , 1'b1 }),
.S({ \$techmap\SPIFSM_1.$auto$opt_reduce.cc:126:opt_mux$2477 , \$techmap\SPIFSM_1.$auto$opt_reduce.cc:126:opt_mux$2453 }),
.Y(\SPIFSM_1.SPI_ReadNext_o )
);
\$pmux #(
.S_WIDTH(3),
.WIDTH(1)
) \$techmap\SPIFSM_1.$procmux$396 (
.A(1'b1),
.B({ \$techmap\SPIFSM_1.$2\ADT7310CS_n_o[0:0] , \$techmap\SPIFSM_1.$2\SPI_FSM_TimerEnable[0:0] , 1'b0 }),
.S({ \$techmap\SPIFSM_1.$procmux$305_CMP , \$techmap\SPIFSM_1.$procmux$297_CMP , \$techmap\SPIFSM_1.$auto$opt_reduce.cc:126:opt_mux$2455 }),
.Y(\SPIFSM_1.ADT7310CS_n_o )
);
\$pmux #(
.S_WIDTH(2),
.WIDTH(1)
) \$techmap\SPIFSM_1.$procmux$413 (
.A(1'b1),
.B({ \$techmap\SPIFSM_1.$2\ADT7310CS_n_o[0:0] , 1'b0 }),
.S({ \$techmap\SPIFSM_1.$procmux$305_CMP , \$techmap\SPIFSM_1.$auto$opt_reduce.cc:126:opt_mux$2457 }),
.Y(\SPIFSM_1.Done_o )
);
\$pmux #(
.S_WIDTH(3),
.WIDTH(8)
) \$techmap\SPIFSM_1.$procmux$439 (
.A(8'b00001000),
.B(24'b001000000101000011111111),
.S({ \$techmap\SPIFSM_1.$procmux$302_CMP , \$techmap\SPIFSM_1.$procmux$297_CMP , \$techmap\SPIFSM_1.$auto$opt_reduce.cc:126:opt_mux$2459 }),
.Y(\SPIFSM_1.SPI_Data_o )
);
\$pmux #(
.S_WIDTH(3),
.WIDTH(1)
) \$techmap\SPIFSM_1.$procmux$481 (
.A(1'b0),
.B({ \SPIFSM_1.Start_i , \SPIFSM_1.SPI_FSM_TimerOvfl , 1'b1 }),
.S({ \$techmap\SPIFSM_1.$procmux$305_CMP , \$techmap\SPIFSM_1.$procmux$297_CMP , \$techmap\SPIFSM_1.$auto$opt_reduce.cc:126:opt_mux$2461 }),
.Y(\SPIFSM_1.SPI_Write_o )
);
\$not #(
.A_SIGNED(0),
.A_WIDTH(1),
.Y_WIDTH(1)
) \$techmap\SPIFSM_1.$procmux$535 (
.A(\SPIFSM_1.Start_i ),
.Y(\$techmap\SPIFSM_1.$2\ADT7310CS_n_o[0:0] )
);
\$not #(
.A_SIGNED(0),
.A_WIDTH(1),
.Y_WIDTH(1)
) \$techmap\SPIFSM_1.$procmux$641 (
.A(\SPIFSM_1.SPI_Transmission_i ),
.Y(\$techmap\SPIFSM_1.$2\SPI_ReadNext_o[0:0] )
);
\$not #(
.A_SIGNED(0),
.A_WIDTH(1),
.Y_WIDTH(1)
) \$techmap\SPIFSM_1.$procmux$659 (
.A(\SPIFSM_1.SPI_FSM_TimerOvfl ),
.Y(\$techmap\SPIFSM_1.$2\SPI_FSM_TimerEnable[0:0] )
);
\$mux #(
.WIDTH(8)
) \$techmap\SPIFSM_1.$procmux$70 (
.A(\SPIFSM_1.Byte0_o ),
.B(\SPIFSM_1.SPI_Data_i ),
.S(\SPIFSM_1.SPI_FSM_Wr0 ),
.Y(\$techmap\SPIFSM_1.$0\Byte0_o[7:0] )
);
\$mux #(
.WIDTH(8)
) \$techmap\SPIFSM_1.$procmux$77 (
.A(\SPIFSM_1.Byte1_o ),
.B(\SPIFSM_1.SPI_Data_i ),
.S(\SPIFSM_1.SPI_FSM_Wr1 ),
.Y(\$techmap\SPIFSM_1.$0\Byte1_o[7:0] )
);
\$mux #(
.WIDTH(32)
) \$techmap\SPIFSM_1.$procmux$80 (
.A(\SPIFSM_1.SPI_FSM_Timer ),
.B(\$techmap\SPIFSM_1.$sub$../../verilog/spifsm.v:231$46_Y ),
.S(\SPIFSM_1.SPI_FSM_TimerEnable ),
.Y(\$techmap\SPIFSM_1.$procmux$80_Y )
);
\$mux #(
.WIDTH(32)
) \$techmap\SPIFSM_1.$procmux$83 (
.A(\$techmap\SPIFSM_1.$procmux$80_Y ),
.B(\SPIFSM_1.ParamCounterPreset_i ),
.S(\SPIFSM_1.SPI_FSM_TimerPreset ),
.Y(\$techmap\SPIFSM_1.$0\SPI_FSM_Timer[31:0] )
);
(* src = "../../verilog/spifsm.v:231" *)
\$sub #(
.A_SIGNED(0),
.A_WIDTH(32),
.B_SIGNED(0),
.B_WIDTH(1),
.Y_WIDTH(32)
) \$techmap\SPIFSM_1.$sub$../../verilog/spifsm.v:231$46 (
.A(\SPIFSM_1.SPI_FSM_Timer ),
.B(1'b1),
.Y(\$techmap\SPIFSM_1.$sub$../../verilog/spifsm.v:231$46_Y )
);
\$reduce_or #(
.A_SIGNED(0),
.A_WIDTH(3),
.Y_WIDTH(1)
) \$techmap\SensorFSM_1.$auto$opt_reduce.cc:130:opt_mux$2464 (
.A({ \$techmap\SensorFSM_1.$procmux$1129_CMP , \$techmap\SensorFSM_1.$procmux$1007_CMP , \$techmap\SensorFSM_1.$procmux$1004_CMP }),
.Y(\$techmap\SensorFSM_1.$auto$opt_reduce.cc:126:opt_mux$2463 )
);
(* src = "../../verilog/sensorfsm.v:149" *)
\$eq #(
.A_SIGNED(0),
.A_WIDTH(16),
.B_SIGNED(0),
.B_WIDTH(16),
.Y_WIDTH(1)
) \$techmap\SensorFSM_1.$eq$../../verilog/sensorfsm.v:149$60 (
.A(\SensorFSM_1.SensorFSM_Timer ),
.B(16'b0000000000000000),
.Y(\SensorFSM_1.SensorFSM_TimerOvfl )
);
SensorFSM SensorFSM_1 (
.Reset_n_i(\SensorFSM_1.Reset_n_i ),
.Clk_i(\SensorFSM_1.Clk_i ),
.In0_i(\SensorFSM_1.Enable_i ),
.In1_i(\SensorFSM_1.MeasureFSM_Done_i ),
.In2_i(\SensorFSM_1.SensorFSM_DiffTooLarge ),
.In3_i(\SensorFSM_1.SensorFSM_TimerOvfl ),
.In4_i(1'b0),
.In5_i(1'b0),
.In6_i(1'b0),
.In7_i(1'b0),
.In8_i(1'b0),
.In9_i(1'b0),
.Out0_o(\$techmap\SensorFSM_1.$procmux$1004_CMP ),
.Out1_o(\$techmap\SensorFSM_1.$procmux$1007_CMP ),
.Out2_o(\$techmap\SensorFSM_1.$procmux$1129_CMP ),
.Out3_o(SensorFSM_1_Out3_s),
.Out4_o(SensorFSM_1_Out4_s),
.Out5_o(SensorFSM_1_Out5_s),
.Out6_o(SensorFSM_1_Out6_s),
.Out7_o(SensorFSM_1_Out7_s),
.Out8_o(SensorFSM_1_Out8_s),
.Out9_o(SensorFSM_1_Out9_s),
.CfgMode_i(SensorFSM_1_CfgMode_s),
.CfgClk_i(SensorFSM_1_CfgClk_s),
.CfgShift_i(SensorFSM_1_CfgShift_s),
.CfgDataIn_i(SensorFSM_1_CfgDataIn_s),
.CfgDataOut_o(SensorFSM_1_CfgDataOut_s)
);
(* src = "../../verilog/sensorfsm.v:174" *)
\$gt #(
.A_SIGNED(0),
.A_WIDTH(16),
.B_SIGNED(0),
.B_WIDTH(16),
.Y_WIDTH(1)
) \$techmap\SensorFSM_1.$gt$../../verilog/sensorfsm.v:174$67 (
.A(\SensorFSM_1.AbsDiffResult ),
.B(\SensorFSM_1.ParamThreshold_i ),
.Y(\SensorFSM_1.SensorFSM_DiffTooLarge )
);
(* src = "../../verilog/sensorfsm.v:130" *)
\$adff #(
.ARST_POLARITY(1'b0),
.ARST_VALUE(16'b0000000000000000),
.CLK_POLARITY(1'b1),
.WIDTH(16)
) \$techmap\SensorFSM_1.$procdff$2443 (
.ARST(\SensorFSM_1.Reset_n_i ),
.CLK(\SensorFSM_1.Clk_i ),
.D(\$techmap\SensorFSM_1.$0\SensorFSM_Timer[15:0] ),
.Q(\SensorFSM_1.SensorFSM_Timer )
);
(* src = "../../verilog/sensorfsm.v:153" *)
\$adff #(
.ARST_POLARITY(1'b0),
.ARST_VALUE(16'b0000000000000000),
.CLK_POLARITY(1'b1),
.WIDTH(16)
) \$techmap\SensorFSM_1.$procdff$2444 (
.ARST(\SensorFSM_1.Reset_n_i ),
.CLK(\SensorFSM_1.Clk_i ),
.D(\$techmap\SensorFSM_1.$0\Word0[15:0] ),
.Q(\SensorFSM_1.Word0 )
);
\$not #(
.A_SIGNED(0),
.A_WIDTH(1),
.Y_WIDTH(1)
) \$techmap\SensorFSM_1.$procmux$1036 (
.A(\SensorFSM_1.Enable_i ),
.Y(\$techmap\SensorFSM_1.$2\SensorFSM_TimerPreset[0:0] )
);
\$and #(
.A_SIGNED(0),
.A_WIDTH(1),
.B_SIGNED(0),
.B_WIDTH(1),
.Y_WIDTH(1)
) \$techmap\SensorFSM_1.$procmux$1065 (
.A(\SensorFSM_1.Enable_i ),
.B(\SensorFSM_1.SensorFSM_TimerOvfl ),
.Y(\$techmap\SensorFSM_1.$2\MeasureFSM_Start_o[0:0] )
);
\$and #(
.A_SIGNED(0),
.A_WIDTH(1),
.B_SIGNED(0),
.B_WIDTH(1),
.Y_WIDTH(1)
) \$techmap\SensorFSM_1.$procmux$1142 (
.A(\SensorFSM_1.MeasureFSM_Done_i ),
.B(\SensorFSM_1.SensorFSM_DiffTooLarge ),
.Y(\$techmap\SensorFSM_1.$2\SensorFSM_StoreNewValue[0:0] )
);
\$mux #(
.WIDTH(1)
) \$techmap\SensorFSM_1.$procmux$1174 (
.A(1'b1),
.B(\$techmap\SensorFSM_1.$4\SensorFSM_TimerPreset[0:0] ),
.S(\SensorFSM_1.MeasureFSM_Done_i ),
.Y(\$techmap\SensorFSM_1.$3\SensorFSM_TimerPreset[0:0] )
);
\$not #(
.A_SIGNED(0),
.A_WIDTH(1),
.Y_WIDTH(1)
) \$techmap\SensorFSM_1.$procmux$1206 (
.A(\SensorFSM_1.SensorFSM_DiffTooLarge ),
.Y(\$techmap\SensorFSM_1.$4\SensorFSM_TimerPreset[0:0] )
);
\$mux #(
.WIDTH(16)
) \$techmap\SensorFSM_1.$procmux$826 (
.A(\SensorFSM_1.SensorFSM_Timer ),
.B(\$techmap\SensorFSM_1.$sub$../../verilog/sensorfsm.v:144$59_Y ),
.S(\SensorFSM_1.SensorFSM_TimerEnable ),
.Y(\$techmap\SensorFSM_1.$procmux$826_Y )
);
\$mux #(
.WIDTH(16)
) \$techmap\SensorFSM_1.$procmux$829 (
.A(\$techmap\SensorFSM_1.$procmux$826_Y ),
.B(\SensorFSM_1.ParamCounterPreset_i ),
.S(\SensorFSM_1.SensorFSM_TimerPreset ),
.Y(\$techmap\SensorFSM_1.$0\SensorFSM_Timer[15:0] )
);
\$mux #(
.WIDTH(16)
) \$techmap\SensorFSM_1.$procmux$832 (
.A(\SensorFSM_1.Word0 ),
.B({ \SensorFSM_1.MeasureFSM_Byte1_i , \SensorFSM_1.MeasureFSM_Byte0_i }),
.S(\SensorFSM_1.SensorFSM_StoreNewValue ),
.Y(\$techmap\SensorFSM_1.$0\Word0[15:0] )
);
\$not #(
.A_SIGNED(0),
.A_WIDTH(1),
.Y_WIDTH(1)
) \$techmap\SensorFSM_1.$procmux$923 (
.A(\$techmap\SensorFSM_1.$auto$opt_reduce.cc:126:opt_mux$2463 ),
.Y(\SensorFSM_1.CpuIntr_o )
);
\$and #(
.A_SIGNED(0),
.A_WIDTH(1),
.B_SIGNED(0),
.B_WIDTH(1),
.Y_WIDTH(1)
) \$techmap\SensorFSM_1.$procmux$943 (
.A(\$techmap\SensorFSM_1.$procmux$1004_CMP ),
.B(\$techmap\SensorFSM_1.$2\MeasureFSM_Start_o[0:0] ),
.Y(\SensorFSM_1.MeasureFSM_Start_o )
);
\$and #(
.A_SIGNED(0),
.A_WIDTH(1),
.B_SIGNED(0),
.B_WIDTH(1),
.Y_WIDTH(1)
) \$techmap\SensorFSM_1.$procmux$953 (
.A(\$techmap\SensorFSM_1.$procmux$1129_CMP ),
.B(\$techmap\SensorFSM_1.$2\SensorFSM_StoreNewValue[0:0] ),
.Y(\SensorFSM_1.SensorFSM_StoreNewValue )
);
\$pmux #(
.S_WIDTH(3),
.WIDTH(1)
) \$techmap\SensorFSM_1.$procmux$983 (
.A(1'b0),
.B({ \SensorFSM_1.Enable_i , 1'b1, \$techmap\SensorFSM_1.$2\SensorFSM_StoreNewValue[0:0] }),
.S({ \$techmap\SensorFSM_1.$procmux$1007_CMP , \$techmap\SensorFSM_1.$procmux$1004_CMP , \$techmap\SensorFSM_1.$procmux$1129_CMP }),
.Y(\SensorFSM_1.SensorFSM_TimerEnable )
);
\$pmux #(
.S_WIDTH(3),
.WIDTH(1)
) \$techmap\SensorFSM_1.$procmux$998 (
.A(1'b1),
.B({ \$techmap\SensorFSM_1.$2\SensorFSM_TimerPreset[0:0] , 1'b0, \$techmap\SensorFSM_1.$3\SensorFSM_TimerPreset[0:0] }),
.S({ \$techmap\SensorFSM_1.$procmux$1007_CMP , \$techmap\SensorFSM_1.$procmux$1004_CMP , \$techmap\SensorFSM_1.$procmux$1129_CMP }),
.Y(\SensorFSM_1.SensorFSM_TimerPreset )
);
(* src = "../../verilog/sensorfsm.v:144" *)
\$sub #(
.A_SIGNED(0),
.A_WIDTH(16),
.B_SIGNED(0),
.B_WIDTH(1),
.Y_WIDTH(16)
) \$techmap\SensorFSM_1.$sub$../../verilog/sensorfsm.v:144$59 (
.A(\SensorFSM_1.SensorFSM_Timer ),
.B(1'b1),
.Y(\$techmap\SensorFSM_1.$sub$../../verilog/sensorfsm.v:144$59_Y )
);
(* src = "../../verilog/sensorfsm.v:170" *)
\$sub #(
.A_SIGNED(0),
.A_WIDTH(17),
.B_SIGNED(0),
.B_WIDTH(17),
.Y_WIDTH(17)
) \$techmap\SensorFSM_1.$sub$../../verilog/sensorfsm.v:170$64 (
.A({ 1'b0, \SensorFSM_1.MeasureFSM_Byte1_i , \SensorFSM_1.MeasureFSM_Byte0_i }),
.B({ 1'b0, \SensorFSM_1.Word0 }),
.Y(\SensorFSM_1.DiffAB )
);
(* src = "../../verilog/sensorfsm.v:171" *)
\$sub #(
.A_SIGNED(0),
.A_WIDTH(16),
.B_SIGNED(0),
.B_WIDTH(16),
.Y_WIDTH(16)
) \$techmap\SensorFSM_1.$sub$../../verilog/sensorfsm.v:171$65 (
.A(\SensorFSM_1.Word0 ),
.B({ \SensorFSM_1.MeasureFSM_Byte1_i , \SensorFSM_1.MeasureFSM_Byte0_i }),
.Y(\SensorFSM_1.DiffBA )
);
(* src = "../../verilog/sensorfsm.v:172" *)
\$mux #(
.WIDTH(16)
) \$techmap\SensorFSM_1.$ternary$../../verilog/sensorfsm.v:172$66 (
.A(\SensorFSM_1.DiffAB [15:0]),
.B(\SensorFSM_1.DiffBA ),
.S(\SensorFSM_1.DiffAB [16]),
.Y(\SensorFSM_1.AbsDiffResult )
);
assign SPI_CPHA_o = 1'b1;
assign SPI_CPOL_o = 1'b1;
assign SPI_LSBFE_o = 1'b0;
assign ADT7310CS_n_o = \SPIFSM_1.ADT7310CS_n_o ;
assign SPIFSM_Byte0_s = \SPIFSM_1.Byte0_o ;
assign SPIFSM_Byte1_s = \SPIFSM_1.Byte1_o ;
assign \SPIFSM_1.Clk_i = Clk_i;
assign SPIFSM_Done_s = \SPIFSM_1.Done_o ;
assign \SPIFSM_1.ParamCounterPreset_i = { SPICounterPresetH_i, SPICounterPresetL_i };
assign \SPIFSM_1.Reset_n_i = Reset_n_i;
assign \SPIFSM_1.SPI_Data_i = SPI_Data_i;
assign SPI_Data_o = \SPIFSM_1.SPI_Data_o ;
assign \SPIFSM_1.SPI_FIFOEmpty_i = SPI_FIFOEmpty_i;
assign \SPIFSM_1.SPI_FIFOFull_i = SPI_FIFOFull_i;
assign SPI_ReadNext_o = \SPIFSM_1.SPI_ReadNext_o ;
assign \SPIFSM_1.SPI_Transmission_i = SPI_Transmission_i;
assign SPI_Write_o = \SPIFSM_1.SPI_Write_o ;
assign \SPIFSM_1.Start_i = SPIFSM_Start_s;
assign \SensorFSM_1.Clk_i = Clk_i;
assign CpuIntr_o = \SensorFSM_1.CpuIntr_o ;
assign \SensorFSM_1.Enable_i = Enable_i;
assign \SensorFSM_1.MeasureFSM_Byte0_i = SPIFSM_Byte0_s;
assign \SensorFSM_1.MeasureFSM_Byte1_i = SPIFSM_Byte1_s;
assign \SensorFSM_1.MeasureFSM_Done_i = SPIFSM_Done_s;
assign SPIFSM_Start_s = \SensorFSM_1.MeasureFSM_Start_o ;
assign \SensorFSM_1.ParamCounterPreset_i = PeriodCounterPreset_i;
assign \SensorFSM_1.ParamThreshold_i = Threshold_i;
assign \SensorFSM_1.Reset_n_i = Reset_n_i;
assign SensorValue_o = \SensorFSM_1.SensorValue_o ;
assign \SensorFSM_1.SensorValue = { \SensorFSM_1.MeasureFSM_Byte1_i , \SensorFSM_1.MeasureFSM_Byte0_i };
assign \SensorFSM_1.SensorValue_o = \SensorFSM_1.Word0 ;
assign SPIFSM_1_CfgMode_s = 1'b0;
assign SPIFSM_1_CfgClk_s = 1'b0;
assign SPIFSM_1_CfgShift_s = 1'b0;
assign SPIFSM_1_CfgDataIn_s = 1'b0;
assign SensorFSM_1_CfgMode_s = 1'b0;
assign SensorFSM_1_CfgClk_s = 1'b0;
assign SensorFSM_1_CfgShift_s = 1'b0;
assign SensorFSM_1_CfgDataIn_s = 1'b0;
endmodule
|
module coordinate_cordic
(
realIn,
imagIn,
clk,
amplitude,
angle,
test1,
test2
);
//==================================================
// Input/Output Ports
//==================================================
input signed [INWIDTH-1:0]realIn,imagIn;
input clk;
output signed [OUTWIDTH-1:0]amplitude;
output signed [ANGLEWIDTH-1:0]angle;
input [9:0] test1;
output [9:0] test2;
assign test2 = {11{test1}};
//==================================================
// Parameter Declaration
//==================================================
parameter INWIDTH = 18, //input data width
OUTWIDTH = 20, //output data width
MIDWIDTH = 21, //the temporary data width
ANGLEWIDTH =15;//the angle width,use degree unit and four bits precision
//in fraction part,highest is sign bit
///180degree respect to 10000 for angle
// amplititude with a factor of 1.647 for iteration >10 times
parameter ARCTANG_0 = 12'b10_01110_00100,//0.7854 expand with 10000*/PI times is +7854 = +2500
ARCTANG_1 = 11'b1_01110_00100,//0.4636 expand with 10000*/PI times is +4636 = +1476
ARCTANG_2 = 10'b11000_01100,//0.2450 expand with 10000*/PI times is +2450 = +780
ARCTANG_3 = 9'b1100_01100,//0.1244 expand with 10000*/PI times is +1244 = +396
ARCTANG_4 = 8'b110_00111,//0.0624 expand with 10000*/PI times is +624 = +199
ARCTANG_5 = 7'b11_00011,//0.0312 expand with 10000*/PI times is +312 = +99
ARCTANG_6 = 6'b1_10010,//0.0156 expand with 10000*/PI times is +156 = +50
ARCTANG_7 = 5'b11001,//0.0078 expand with 10000*/PI times is +78 = +25
ARCTANG_8 = 4'b1100,//0.0039 expand with 10000*/PI times is +39 = +12
ARCTANG_9 = 3'b110,//0.0020 expand with 10000*/PI times is +20 = +6
ARCTANG_10 = 2'b11,//0.0010 expand with 10000*/PI times is +10 = +3
ARCTANG_11 = 2'b10;//0.0005 expand with 10000*/PI times is +5 = +2
parameter HALFPI = 13'b100_11100_01000;//+15708/PI = +5000
//==================================================
// Register Declaration
//==================================================
reg signed [MIDWIDTH-1:0]xData1,xData2,xData3,xData4,xData5,xData6,
xData7,xData8,xData9,xData10,xData11,xData12,
xData13,xData14,xData15,xData16,
yData1,yData2,yData3,yData4,yData5,yData6,
yData7,yData8,yData9,yData10,yData11,yData12,
yData13,yData14,yData15,yData16;
reg signed [ANGLEWIDTH-1:0]angle1,angle2,angle3,angle4,angle5,angle6,
angle7,angle8,angle9,angle10,angle11,angle12,
angle13,angle14,angle15,angle16;
//==================================================
// Wire Declaration
//==================================================
wire signed [MIDWIDTH-1:0]reIn,imIn;
wire signed [ANGLEWIDTH-1:0]ang;
//==================================================
// Integer Declaration
//==================================================
//==================================================
// Concurrent Assignment
//==================================================
assign reIn = realIn[INWIDTH-1]?(imagIn[INWIDTH-1]?-imagIn:imagIn):realIn;
assign imIn = realIn[INWIDTH-1]?(imagIn[INWIDTH-1]?realIn:-realIn):imagIn;
assign ang = realIn[INWIDTH-1]?(imagIn[INWIDTH-1]?-HALFPI:HALFPI):1'b0;
/*
//change 23 bits to 22 bits
assign amplitude = {xData13[MIDWIDTH-1],xData13[MIDWIDTH-3:0]};
//angle have expand with 10000 times
assign angle = angle13;
*/
assign amplitude = {xData12[MIDWIDTH-1],xData12[MIDWIDTH-3:0]};
assign angle = angle12;
//==================================================
// Always Construct
//==================================================
always@(posedge clk)
begin
// if y < 0 then d = 1;
// x = x - y.d.2^-i;
// y = y + x.d.2^-i;
// z = z - d.arctan(2^-i);
// i = 0
xData1 <= imIn[MIDWIDTH-1]?(reIn - imIn):(reIn + imIn);
yData1 <= imIn[MIDWIDTH-1]?(imIn + reIn):(imIn - reIn);
angle1 <= imIn[MIDWIDTH-1]?(ang - ARCTANG_0):(ang + ARCTANG_0);
// i = 1
xData2 <= yData1[MIDWIDTH-1]?(xData1 - {{2{yData1[MIDWIDTH-1]}},yData1[MIDWIDTH-2:1]}):(xData1 + {{2{yData1[MIDWIDTH-1]}},yData1[MIDWIDTH-2:1]});
yData2 <= yData1[MIDWIDTH-1]?(yData1 + {{2{xData1[MIDWIDTH-1]}},xData1[MIDWIDTH-2:1]}):(yData1 - {{2{xData1[MIDWIDTH-1]}},xData1[MIDWIDTH-2:1]});
angle2 <= yData1[MIDWIDTH-1]?(angle1 - ARCTANG_1):(angle1 + ARCTANG_1);
// i = 2
xData3 <= yData2[MIDWIDTH-1]?(xData2 - {{3{yData2[MIDWIDTH-1]}},yData2[MIDWIDTH-2:2]}):(xData2 + {{3{yData2[MIDWIDTH-1]}},yData2[MIDWIDTH-2:2]});
yData3 <= yData2[MIDWIDTH-1]?(yData2 + {{3{xData2[MIDWIDTH-1]}},xData2[MIDWIDTH-2:2]}):(yData2 - {{3{xData2[MIDWIDTH-1]}},xData2[MIDWIDTH-2:2]});
angle3 <= yData2[MIDWIDTH-1]?(angle2 - ARCTANG_2):(angle2 + ARCTANG_2);
// i = 3
xData4 <= yData3[MIDWIDTH-1]?(xData3 - {{4{yData3[MIDWIDTH-1]}},yData3[MIDWIDTH-2:3]}):(xData3 + {{4{yData3[MIDWIDTH-1]}},yData3[MIDWIDTH-2:3]});
yData4 <= yData3[MIDWIDTH-1]?(yData3 + {{4{xData3[MIDWIDTH-1]}},xData3[MIDWIDTH-2:3]}):(yData3 - {{4{xData3[MIDWIDTH-1]}},xData3[MIDWIDTH-2:3]});
angle4 <= yData3[MIDWIDTH-1]?(angle3 - ARCTANG_3):(angle3 + ARCTANG_3);
// i = 4
xData5 <= yData4[MIDWIDTH-1]?(xData4 - {{5{yData4[MIDWIDTH-1]}},yData4[MIDWIDTH-2:4]}):(xData4 + {{5{yData4[MIDWIDTH-1]}},yData4[MIDWIDTH-2:4]});
yData5 <= yData4[MIDWIDTH-1]?(yData4 + {{5{xData4[MIDWIDTH-1]}},xData4[MIDWIDTH-2:4]}):(yData4 - {{5{xData4[MIDWIDTH-1]}},xData4[MIDWIDTH-2:4]});
angle5 <= yData4[MIDWIDTH-1]?(angle4 - ARCTANG_4):(angle4 + ARCTANG_4);
// i = 5
xData6 <= yData5[MIDWIDTH-1]?(xData5 - {{6{yData5[MIDWIDTH-1]}},yData5[MIDWIDTH-2:5]}):(xData5 + {{6{yData5[MIDWIDTH-1]}},yData5[MIDWIDTH-2:5]});
yData6 <= yData5[MIDWIDTH-1]?(yData5 + {{6{xData5[MIDWIDTH-1]}},xData5[MIDWIDTH-2:5]}):(yData5 - {{6{xData5[MIDWIDTH-1]}},xData5[MIDWIDTH-2:5]});
angle6 <= yData5[MIDWIDTH-1]?(angle5 - ARCTANG_5):(angle5 + ARCTANG_5);
// i = 6
xData7 <= yData6[MIDWIDTH-1]?(xData6 - {{7{yData6[MIDWIDTH-1]}},yData6[MIDWIDTH-2:6]}):(xData6 + {{7{yData6[MIDWIDTH-1]}},yData6[MIDWIDTH-2:6]});
yData7 <= yData6[MIDWIDTH-1]?(yData6 + {{7{xData6[MIDWIDTH-1]}},xData6[MIDWIDTH-2:6]}):(yData6 - {{7{xData6[MIDWIDTH-1]}},xData6[MIDWIDTH-2:6]});
angle7 <= yData6[MIDWIDTH-1]?(angle6 - ARCTANG_6):(angle6 + ARCTANG_6);
// i = 7
xData8 <= yData7[MIDWIDTH-1]?(xData7 - {{8{yData7[MIDWIDTH-1]}},yData7[MIDWIDTH-2:7]}):(xData7 + {{8{yData7[MIDWIDTH-1]}},yData7[MIDWIDTH-2:7]});
yData8 <= yData7[MIDWIDTH-1]?(yData7 + {{8{xData7[MIDWIDTH-1]}},xData7[MIDWIDTH-2:7]}):(yData7 - {{8{xData7[MIDWIDTH-1]}},xData7[MIDWIDTH-2:7]});
angle8 <= yData7[MIDWIDTH-1]?(angle7 - ARCTANG_7):(angle7 + ARCTANG_7);
// i = 8
xData9 <= yData8[MIDWIDTH-1]?(xData8 - {{9{yData8[MIDWIDTH-1]}},yData8[MIDWIDTH-2:8]}):(xData8 + {{9{yData8[MIDWIDTH-1]}},yData8[MIDWIDTH-2:8]});
yData9 <= yData8[MIDWIDTH-1]?(yData8 + {{9{xData8[MIDWIDTH-1]}},xData8[MIDWIDTH-2:8]}):(yData8 - {{9{xData8[MIDWIDTH-1]}},xData8[MIDWIDTH-2:8]});
angle9 <= yData8[MIDWIDTH-1]?(angle8 - ARCTANG_8):(angle8 + ARCTANG_8);
// i = 9
xData10 <= yData9[MIDWIDTH-1]?(xData9 - {{10{yData9[MIDWIDTH-1]}},yData9[MIDWIDTH-2:9]}):(xData9 + {{10{yData9[MIDWIDTH-1]}},yData9[MIDWIDTH-2:9]});
yData10 <= yData9[MIDWIDTH-1]?(yData9 + {{10{xData9[MIDWIDTH-1]}},xData9[MIDWIDTH-2:9]}):(yData9 - {{10{xData9[MIDWIDTH-1]}},xData9[MIDWIDTH-2:9]});
angle10 <= yData9[MIDWIDTH-1]?(angle9 - ARCTANG_9):(angle9 + ARCTANG_9);
// i = 10
xData11 <= yData10[MIDWIDTH-1]?(xData10 - {{11{yData10[MIDWIDTH-1]}},yData10[MIDWIDTH-2:10]}):(xData10 + {{11{yData10[MIDWIDTH-1]}},yData10[MIDWIDTH-2:10]});
yData11 <= yData10[MIDWIDTH-1]?(yData10 + {{11{xData10[MIDWIDTH-1]}},xData10[MIDWIDTH-2:10]}):(yData10 - {{11{xData10[MIDWIDTH-1]}},xData10[MIDWIDTH-2:10]});
angle11 <= yData10[MIDWIDTH-1]?(angle10 - ARCTANG_10):(angle10 + ARCTANG_10);
// i = 11
xData12 <= yData11[MIDWIDTH-1]?(xData11 - {{12{yData11[MIDWIDTH-1]}},yData11[MIDWIDTH-2:11]}):(xData11 + {{12{yData11[MIDWIDTH-1]}},yData11[MIDWIDTH-2:11]});
yData12 <= yData11[MIDWIDTH-1]?(yData11 + {{12{xData11[MIDWIDTH-1]}},xData11[MIDWIDTH-2:11]}):(yData11 - {{12{xData11[MIDWIDTH-1]}},xData11[MIDWIDTH-2:11]});
angle12 <= yData11[MIDWIDTH-1]?(angle11 - ARCTANG_11):(angle11 + ARCTANG_11);
end
//==================================================
// Module Instantiation
//==================================================
//==================================================
// Task Declaration
//==================================================
//==================================================
// Function Declaration
//==================================================
endmodule
|
module sky130_fd_sc_hvl__and3 (
X ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
|
module vga_timing(
clk25mhz,
hindex,
vindex,
hsync,
vsync
);
// Input
input wire clk25mhz;
// Output
output reg[9:0] hindex = 0;
output reg[9:0] vindex = 0;
output reg hsync;
output reg vsync;
// Process
always @ (posedge clk25mhz) begin: indexes
if(hindex == 799) begin
hindex <= 0;
if(vindex == 524) begin
vindex <= 0;
end else begin
vindex <= vindex + 1;
end
end else begin
hindex <= hindex + 1;
end
end
always @ (posedge clk25mhz) begin: vsync_output
if(vindex >= 490 && vindex <= 491) begin
vsync <= 0;
end else begin
vsync <= 1;
end
end
always @ (posedge clk25mhz) begin: hsync_output
// Both hsync and color output are delayed by one pixel
if(hindex >= 657 && hindex <= 752) begin
hsync <= 0;
end else begin
hsync <= 1;
end
end
endmodule
|
module top();
// Inputs are registered
reg A1;
reg A2;
reg B1;
reg B2;
reg C1;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A1 = 1'bX;
A2 = 1'bX;
B1 = 1'bX;
B2 = 1'bX;
C1 = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A1 = 1'b0;
#40 A2 = 1'b0;
#60 B1 = 1'b0;
#80 B2 = 1'b0;
#100 C1 = 1'b0;
#120 VGND = 1'b0;
#140 VNB = 1'b0;
#160 VPB = 1'b0;
#180 VPWR = 1'b0;
#200 A1 = 1'b1;
#220 A2 = 1'b1;
#240 B1 = 1'b1;
#260 B2 = 1'b1;
#280 C1 = 1'b1;
#300 VGND = 1'b1;
#320 VNB = 1'b1;
#340 VPB = 1'b1;
#360 VPWR = 1'b1;
#380 A1 = 1'b0;
#400 A2 = 1'b0;
#420 B1 = 1'b0;
#440 B2 = 1'b0;
#460 C1 = 1'b0;
#480 VGND = 1'b0;
#500 VNB = 1'b0;
#520 VPB = 1'b0;
#540 VPWR = 1'b0;
#560 VPWR = 1'b1;
#580 VPB = 1'b1;
#600 VNB = 1'b1;
#620 VGND = 1'b1;
#640 C1 = 1'b1;
#660 B2 = 1'b1;
#680 B1 = 1'b1;
#700 A2 = 1'b1;
#720 A1 = 1'b1;
#740 VPWR = 1'bx;
#760 VPB = 1'bx;
#780 VNB = 1'bx;
#800 VGND = 1'bx;
#820 C1 = 1'bx;
#840 B2 = 1'bx;
#860 B1 = 1'bx;
#880 A2 = 1'bx;
#900 A1 = 1'bx;
end
sky130_fd_sc_ls__a221o dut (.A1(A1), .A2(A2), .B1(B1), .B2(B2), .C1(C1), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
|
module GTYE3_COMMON #(
`ifdef XIL_TIMING
parameter LOC = "UNPLACED",
`endif
parameter [15:0] A_SDM1DATA1_0 = 16'b0000000000000000,
parameter [8:0] A_SDM1DATA1_1 = 9'b000000000,
parameter [15:0] BIAS_CFG0 = 16'h0000,
parameter [15:0] BIAS_CFG1 = 16'h0000,
parameter [15:0] BIAS_CFG2 = 16'h0000,
parameter [15:0] BIAS_CFG3 = 16'h0000,
parameter [15:0] BIAS_CFG4 = 16'h0000,
parameter [9:0] BIAS_CFG_RSVD = 10'b0000000000,
parameter [15:0] COMMON_CFG0 = 16'h0000,
parameter [15:0] COMMON_CFG1 = 16'h0000,
parameter [15:0] POR_CFG = 16'h0004,
parameter [15:0] PPF0_CFG = 16'h0FFF,
parameter [15:0] PPF1_CFG = 16'h0FFF,
parameter QPLL0CLKOUT_RATE = "FULL",
parameter [15:0] QPLL0_CFG0 = 16'h301C,
parameter [15:0] QPLL0_CFG1 = 16'h0000,
parameter [15:0] QPLL0_CFG1_G3 = 16'h0020,
parameter [15:0] QPLL0_CFG2 = 16'h0780,
parameter [15:0] QPLL0_CFG2_G3 = 16'h0780,
parameter [15:0] QPLL0_CFG3 = 16'h0120,
parameter [15:0] QPLL0_CFG4 = 16'h0021,
parameter [9:0] QPLL0_CP = 10'b0000011111,
parameter [9:0] QPLL0_CP_G3 = 10'b0000011111,
parameter integer QPLL0_FBDIV = 66,
parameter integer QPLL0_FBDIV_G3 = 80,
parameter [15:0] QPLL0_INIT_CFG0 = 16'h0000,
parameter [7:0] QPLL0_INIT_CFG1 = 8'h00,
parameter [15:0] QPLL0_LOCK_CFG = 16'h01E8,
parameter [15:0] QPLL0_LOCK_CFG_G3 = 16'h21E8,
parameter [9:0] QPLL0_LPF = 10'b1011111111,
parameter [9:0] QPLL0_LPF_G3 = 10'b1111111111,
parameter integer QPLL0_REFCLK_DIV = 2,
parameter [15:0] QPLL0_SDM_CFG0 = 16'h0000,
parameter [15:0] QPLL0_SDM_CFG1 = 16'h0000,
parameter [15:0] QPLL0_SDM_CFG2 = 16'h0000,
parameter QPLL1CLKOUT_RATE = "FULL",
parameter [15:0] QPLL1_CFG0 = 16'h301C,
parameter [15:0] QPLL1_CFG1 = 16'h0000,
parameter [15:0] QPLL1_CFG1_G3 = 16'h0020,
parameter [15:0] QPLL1_CFG2 = 16'h0780,
parameter [15:0] QPLL1_CFG2_G3 = 16'h0780,
parameter [15:0] QPLL1_CFG3 = 16'h0120,
parameter [15:0] QPLL1_CFG4 = 16'h0021,
parameter [9:0] QPLL1_CP = 10'b0000011111,
parameter [9:0] QPLL1_CP_G3 = 10'b0000011111,
parameter integer QPLL1_FBDIV = 66,
parameter integer QPLL1_FBDIV_G3 = 80,
parameter [15:0] QPLL1_INIT_CFG0 = 16'h0000,
parameter [7:0] QPLL1_INIT_CFG1 = 8'h00,
parameter [15:0] QPLL1_LOCK_CFG = 16'h01E8,
parameter [15:0] QPLL1_LOCK_CFG_G3 = 16'h21E8,
parameter [9:0] QPLL1_LPF = 10'b1011111111,
parameter [9:0] QPLL1_LPF_G3 = 10'b1111111111,
parameter integer QPLL1_REFCLK_DIV = 2,
parameter [15:0] QPLL1_SDM_CFG0 = 16'h0000,
parameter [15:0] QPLL1_SDM_CFG1 = 16'h0000,
parameter [15:0] QPLL1_SDM_CFG2 = 16'h0000,
parameter [15:0] RSVD_ATTR0 = 16'h0000,
parameter [15:0] RSVD_ATTR1 = 16'h0000,
parameter [15:0] RSVD_ATTR2 = 16'h0000,
parameter [15:0] RSVD_ATTR3 = 16'h0000,
parameter [1:0] RXRECCLKOUT0_SEL = 2'b00,
parameter [1:0] RXRECCLKOUT1_SEL = 2'b00,
parameter [0:0] SARC_EN = 1'b1,
parameter [0:0] SARC_SEL = 1'b0,
parameter [15:0] SDM0INITSEED0_0 = 16'b0000000000000000,
parameter [8:0] SDM0INITSEED0_1 = 9'b000000000,
parameter [15:0] SDM1INITSEED0_0 = 16'b0000000000000000,
parameter [8:0] SDM1INITSEED0_1 = 9'b000000000,
parameter SIM_MODE = "FAST",
parameter SIM_RESET_SPEEDUP = "TRUE",
parameter integer SIM_VERSION = 2
)(
output [15:0] DRPDO,
output DRPRDY,
output [7:0] PMARSVDOUT0,
output [7:0] PMARSVDOUT1,
output QPLL0FBCLKLOST,
output QPLL0LOCK,
output QPLL0OUTCLK,
output QPLL0OUTREFCLK,
output QPLL0REFCLKLOST,
output QPLL1FBCLKLOST,
output QPLL1LOCK,
output QPLL1OUTCLK,
output QPLL1OUTREFCLK,
output QPLL1REFCLKLOST,
output [7:0] QPLLDMONITOR0,
output [7:0] QPLLDMONITOR1,
output REFCLKOUTMONITOR0,
output REFCLKOUTMONITOR1,
output [1:0] RXRECCLK0_SEL,
output [1:0] RXRECCLK1_SEL,
output [3:0] SDM0FINALOUT,
output [14:0] SDM0TESTDATA,
output [3:0] SDM1FINALOUT,
output [14:0] SDM1TESTDATA,
input BGBYPASSB,
input BGMONITORENB,
input BGPDB,
input [4:0] BGRCALOVRD,
input BGRCALOVRDENB,
input [9:0] DRPADDR,
input DRPCLK,
input [15:0] DRPDI,
input DRPEN,
input DRPWE,
input GTGREFCLK0,
input GTGREFCLK1,
input GTNORTHREFCLK00,
input GTNORTHREFCLK01,
input GTNORTHREFCLK10,
input GTNORTHREFCLK11,
input GTREFCLK00,
input GTREFCLK01,
input GTREFCLK10,
input GTREFCLK11,
input GTSOUTHREFCLK00,
input GTSOUTHREFCLK01,
input GTSOUTHREFCLK10,
input GTSOUTHREFCLK11,
input [7:0] PMARSVD0,
input [7:0] PMARSVD1,
input QPLL0CLKRSVD0,
input QPLL0LOCKDETCLK,
input QPLL0LOCKEN,
input QPLL0PD,
input [2:0] QPLL0REFCLKSEL,
input QPLL0RESET,
input QPLL1CLKRSVD0,
input QPLL1LOCKDETCLK,
input QPLL1LOCKEN,
input QPLL1PD,
input [2:0] QPLL1REFCLKSEL,
input QPLL1RESET,
input [7:0] QPLLRSVD1,
input [4:0] QPLLRSVD2,
input [4:0] QPLLRSVD3,
input [7:0] QPLLRSVD4,
input RCALENB,
input [24:0] SDM0DATA,
input SDM0RESET,
input [1:0] SDM0WIDTH,
input [24:0] SDM1DATA,
input SDM1RESET,
input [1:0] SDM1WIDTH
);
// define constants
localparam MODULE_NAME = "GTYE3_COMMON";
localparam in_delay = 0;
localparam out_delay = 0;
localparam inclk_delay = 0;
localparam outclk_delay = 0;
// include dynamic registers - XILINX test only
reg trig_attr = 1'b0;
`ifdef XIL_DR
`include "GTYE3_COMMON_dr.v"
`else
localparam [15:0] A_SDM1DATA1_0_REG = A_SDM1DATA1_0;
localparam [8:0] A_SDM1DATA1_1_REG = A_SDM1DATA1_1;
localparam [15:0] BIAS_CFG0_REG = BIAS_CFG0;
localparam [15:0] BIAS_CFG1_REG = BIAS_CFG1;
localparam [15:0] BIAS_CFG2_REG = BIAS_CFG2;
localparam [15:0] BIAS_CFG3_REG = BIAS_CFG3;
localparam [15:0] BIAS_CFG4_REG = BIAS_CFG4;
localparam [9:0] BIAS_CFG_RSVD_REG = BIAS_CFG_RSVD;
localparam [15:0] COMMON_CFG0_REG = COMMON_CFG0;
localparam [15:0] COMMON_CFG1_REG = COMMON_CFG1;
localparam [15:0] POR_CFG_REG = POR_CFG;
localparam [15:0] PPF0_CFG_REG = PPF0_CFG;
localparam [15:0] PPF1_CFG_REG = PPF1_CFG;
localparam [32:1] QPLL0CLKOUT_RATE_REG = QPLL0CLKOUT_RATE;
localparam [15:0] QPLL0_CFG0_REG = QPLL0_CFG0;
localparam [15:0] QPLL0_CFG1_REG = QPLL0_CFG1;
localparam [15:0] QPLL0_CFG1_G3_REG = QPLL0_CFG1_G3;
localparam [15:0] QPLL0_CFG2_REG = QPLL0_CFG2;
localparam [15:0] QPLL0_CFG2_G3_REG = QPLL0_CFG2_G3;
localparam [15:0] QPLL0_CFG3_REG = QPLL0_CFG3;
localparam [15:0] QPLL0_CFG4_REG = QPLL0_CFG4;
localparam [9:0] QPLL0_CP_REG = QPLL0_CP;
localparam [9:0] QPLL0_CP_G3_REG = QPLL0_CP_G3;
localparam [7:0] QPLL0_FBDIV_REG = QPLL0_FBDIV;
localparam [7:0] QPLL0_FBDIV_G3_REG = QPLL0_FBDIV_G3;
localparam [15:0] QPLL0_INIT_CFG0_REG = QPLL0_INIT_CFG0;
localparam [7:0] QPLL0_INIT_CFG1_REG = QPLL0_INIT_CFG1;
localparam [15:0] QPLL0_LOCK_CFG_REG = QPLL0_LOCK_CFG;
localparam [15:0] QPLL0_LOCK_CFG_G3_REG = QPLL0_LOCK_CFG_G3;
localparam [9:0] QPLL0_LPF_REG = QPLL0_LPF;
localparam [9:0] QPLL0_LPF_G3_REG = QPLL0_LPF_G3;
localparam [4:0] QPLL0_REFCLK_DIV_REG = QPLL0_REFCLK_DIV;
localparam [15:0] QPLL0_SDM_CFG0_REG = QPLL0_SDM_CFG0;
localparam [15:0] QPLL0_SDM_CFG1_REG = QPLL0_SDM_CFG1;
localparam [15:0] QPLL0_SDM_CFG2_REG = QPLL0_SDM_CFG2;
localparam [32:1] QPLL1CLKOUT_RATE_REG = QPLL1CLKOUT_RATE;
localparam [15:0] QPLL1_CFG0_REG = QPLL1_CFG0;
localparam [15:0] QPLL1_CFG1_REG = QPLL1_CFG1;
localparam [15:0] QPLL1_CFG1_G3_REG = QPLL1_CFG1_G3;
localparam [15:0] QPLL1_CFG2_REG = QPLL1_CFG2;
localparam [15:0] QPLL1_CFG2_G3_REG = QPLL1_CFG2_G3;
localparam [15:0] QPLL1_CFG3_REG = QPLL1_CFG3;
localparam [15:0] QPLL1_CFG4_REG = QPLL1_CFG4;
localparam [9:0] QPLL1_CP_REG = QPLL1_CP;
localparam [9:0] QPLL1_CP_G3_REG = QPLL1_CP_G3;
localparam [7:0] QPLL1_FBDIV_REG = QPLL1_FBDIV;
localparam [7:0] QPLL1_FBDIV_G3_REG = QPLL1_FBDIV_G3;
localparam [15:0] QPLL1_INIT_CFG0_REG = QPLL1_INIT_CFG0;
localparam [7:0] QPLL1_INIT_CFG1_REG = QPLL1_INIT_CFG1;
localparam [15:0] QPLL1_LOCK_CFG_REG = QPLL1_LOCK_CFG;
localparam [15:0] QPLL1_LOCK_CFG_G3_REG = QPLL1_LOCK_CFG_G3;
localparam [9:0] QPLL1_LPF_REG = QPLL1_LPF;
localparam [9:0] QPLL1_LPF_G3_REG = QPLL1_LPF_G3;
localparam [4:0] QPLL1_REFCLK_DIV_REG = QPLL1_REFCLK_DIV;
localparam [15:0] QPLL1_SDM_CFG0_REG = QPLL1_SDM_CFG0;
localparam [15:0] QPLL1_SDM_CFG1_REG = QPLL1_SDM_CFG1;
localparam [15:0] QPLL1_SDM_CFG2_REG = QPLL1_SDM_CFG2;
localparam [15:0] RSVD_ATTR0_REG = RSVD_ATTR0;
localparam [15:0] RSVD_ATTR1_REG = RSVD_ATTR1;
localparam [15:0] RSVD_ATTR2_REG = RSVD_ATTR2;
localparam [15:0] RSVD_ATTR3_REG = RSVD_ATTR3;
localparam [1:0] RXRECCLKOUT0_SEL_REG = RXRECCLKOUT0_SEL;
localparam [1:0] RXRECCLKOUT1_SEL_REG = RXRECCLKOUT1_SEL;
localparam [0:0] SARC_EN_REG = SARC_EN;
localparam [0:0] SARC_SEL_REG = SARC_SEL;
localparam [15:0] SDM0INITSEED0_0_REG = SDM0INITSEED0_0;
localparam [8:0] SDM0INITSEED0_1_REG = SDM0INITSEED0_1;
localparam [15:0] SDM1INITSEED0_0_REG = SDM1INITSEED0_0;
localparam [8:0] SDM1INITSEED0_1_REG = SDM1INITSEED0_1;
// localparam [80:1] SIM_MODE_REG = SIM_MODE;
// localparam [40:1] SIM_RESET_SPEEDUP_REG = SIM_RESET_SPEEDUP;
// localparam [1:0] SIM_VERSION_REG = SIM_VERSION;
`endif
localparam [0:0] AEN_BGBS0_REG = 1'b0;
localparam [0:0] AEN_BGBS1_REG = 1'b0;
localparam [0:0] AEN_MASTER0_REG = 1'b0;
localparam [0:0] AEN_MASTER1_REG = 1'b0;
localparam [0:0] AEN_PD0_REG = 1'b0;
localparam [0:0] AEN_PD1_REG = 1'b0;
localparam [0:0] AEN_QPLL0_REG = 1'b0;
localparam [0:0] AEN_QPLL1_REG = 1'b0;
localparam [0:0] AEN_REFCLK0_REG = 1'b0;
localparam [0:0] AEN_REFCLK1_REG = 1'b0;
localparam [0:0] AEN_RESET0_REG = 1'b0;
localparam [0:0] AEN_RESET1_REG = 1'b0;
localparam [0:0] AEN_SDMDATA0_REG = 1'b0;
localparam [0:0] AEN_SDMDATA1_REG = 1'b0;
localparam [0:0] AEN_SDMRESET0_REG = 1'b0;
localparam [0:0] AEN_SDMRESET1_REG = 1'b0;
localparam [0:0] AEN_SDMWIDTH0_REG = 1'b0;
localparam [0:0] AEN_SDMWIDTH1_REG = 1'b0;
localparam [3:0] AQDMUXSEL1_REG = 4'b0000;
localparam [3:0] AVCC_SENSE_SEL_REG = 4'b0000;
localparam [3:0] AVTT_SENSE_SEL_REG = 4'b0000;
localparam [0:0] A_BGMONITOREN_REG = 1'b0;
localparam [0:0] A_BGPD_REG = 1'b0;
localparam [0:0] A_GTREFCLKPD0_REG = 1'b0;
localparam [0:0] A_GTREFCLKPD1_REG = 1'b0;
localparam [0:0] A_QPLL0LOCKEN_REG = 1'b0;
localparam [0:0] A_QPLL0PD_REG = 1'b0;
localparam [0:0] A_QPLL0RESET_REG = 1'b0;
localparam [0:0] A_QPLL1LOCKEN_REG = 1'b0;
localparam [0:0] A_QPLL1PD_REG = 1'b0;
localparam [0:0] A_QPLL1RESET_REG = 1'b0;
localparam [15:0] A_SDM0DATA1_0_REG = 16'b0000000000000000;
localparam [8:0] A_SDM0DATA1_1_REG = 9'b000000000;
localparam [0:0] A_SDMRESET0_REG = 1'b0;
localparam [0:0] A_SDMRESET1_REG = 1'b0;
localparam [1:0] COMMON_AMUX_SEL0_REG = 2'b00;
localparam [1:0] COMMON_AMUX_SEL1_REG = 2'b00;
localparam [0:0] COMMON_INSTANTIATED_REG = 1'b1;
localparam [2:0] QPLL0_AMONITOR_SEL_REG = 3'b000;
localparam [2:0] QPLL1_AMONITOR_SEL_REG = 3'b000;
localparam [0:0] RCALSAP_TESTEN_REG = 1'b0;
localparam [0:0] RCAL_APROBE_REG = 1'b0;
localparam [0:0] REFCLK0_EN_DC_COUP_REG = 1'b0;
localparam [0:0] REFCLK0_VCM_HIGH_REG = 1'b0;
localparam [0:0] REFCLK0_VCM_LOW_REG = 1'b0;
localparam [0:0] REFCLK1_EN_DC_COUP_REG = 1'b0;
localparam [0:0] REFCLK1_VCM_HIGH_REG = 1'b0;
localparam [0:0] REFCLK1_VCM_LOW_REG = 1'b0;
localparam [1:0] VCCAUX_SENSE_SEL_REG = 2'b00;
`ifdef XIL_ATTR_TEST
reg attr_test = 1'b1;
`else
reg attr_test = 1'b0;
`endif
reg attr_err = 1'b0;
tri0 glblGSR = glbl.GSR;
wire DRPRDY_out;
wire QPLL0FBCLKLOST_out;
wire QPLL0LOCK_out;
wire QPLL0OUTCLK_out;
wire QPLL0OUTREFCLK_out;
wire QPLL0REFCLKLOST_out;
wire QPLL1FBCLKLOST_out;
wire QPLL1LOCK_out;
wire QPLL1OUTCLK_out;
wire QPLL1OUTREFCLK_out;
wire QPLL1REFCLKLOST_out;
wire REFCLKOUTMONITOR0_out;
wire REFCLKOUTMONITOR1_out;
wire [14:0] SDM0TESTDATA_out;
wire [14:0] SDM1TESTDATA_out;
wire [15:0] DRPDO_out;
wire [1:0] RXRECCLK0_SEL_out;
wire [1:0] RXRECCLK1_SEL_out;
wire [3:0] SARCCLK_out;
wire [3:0] SDM0FINALOUT_out;
wire [3:0] SDM1FINALOUT_out;
wire [7:0] PMARSVDOUT0_out;
wire [7:0] PMARSVDOUT1_out;
wire [7:0] PMASCANOUT_out;
wire [7:0] QPLLDMONITOR0_out;
wire [7:0] QPLLDMONITOR1_out;
wire DRPRDY_delay;
wire QPLL0FBCLKLOST_delay;
wire QPLL0LOCK_delay;
wire QPLL0OUTCLK_delay;
wire QPLL0OUTREFCLK_delay;
wire QPLL0REFCLKLOST_delay;
wire QPLL1FBCLKLOST_delay;
wire QPLL1LOCK_delay;
wire QPLL1OUTCLK_delay;
wire QPLL1OUTREFCLK_delay;
wire QPLL1REFCLKLOST_delay;
wire REFCLKOUTMONITOR0_delay;
wire REFCLKOUTMONITOR1_delay;
wire [14:0] SDM0TESTDATA_delay;
wire [14:0] SDM1TESTDATA_delay;
wire [15:0] DRPDO_delay;
wire [1:0] RXRECCLK0_SEL_delay;
wire [1:0] RXRECCLK1_SEL_delay;
wire [3:0] SDM0FINALOUT_delay;
wire [3:0] SDM1FINALOUT_delay;
wire [7:0] PMARSVDOUT0_delay;
wire [7:0] PMARSVDOUT1_delay;
wire [7:0] QPLLDMONITOR0_delay;
wire [7:0] QPLLDMONITOR1_delay;
wire BGBYPASSB_in;
wire BGMONITORENB_in;
wire BGPDB_in;
wire BGRCALOVRDENB_in;
wire DRPCLK_in;
wire DRPEN_in;
wire DRPWE_in;
wire GTGREFCLK0_in;
wire GTGREFCLK1_in;
wire GTNORTHREFCLK00_in;
wire GTNORTHREFCLK01_in;
wire GTNORTHREFCLK10_in;
wire GTNORTHREFCLK11_in;
wire GTREFCLK00_in;
wire GTREFCLK01_in;
wire GTREFCLK10_in;
wire GTREFCLK11_in;
wire GTSOUTHREFCLK00_in;
wire GTSOUTHREFCLK01_in;
wire GTSOUTHREFCLK10_in;
wire GTSOUTHREFCLK11_in;
wire PMASCANENB_in;
wire QDPMASCANMODEB_in;
wire QDPMASCANRSTEN_in;
wire QPLL0CLKRSVD0_in;
wire QPLL0LOCKDETCLK_in;
wire QPLL0LOCKEN_in;
wire QPLL0PD_in;
wire QPLL0RESET_in;
wire QPLL1CLKRSVD0_in;
wire QPLL1LOCKDETCLK_in;
wire QPLL1LOCKEN_in;
wire QPLL1PD_in;
wire QPLL1RESET_in;
wire RCALENB_in;
wire SDM0RESET_in;
wire SDM1RESET_in;
wire [15:0] DRPDI_in;
wire [1:0] SDM0WIDTH_in;
wire [1:0] SDM1WIDTH_in;
wire [24:0] SDM0DATA_in;
wire [24:0] SDM1DATA_in;
wire [2:0] QPLL0REFCLKSEL_in;
wire [2:0] QPLL1REFCLKSEL_in;
wire [3:0] RXRECCLK_in;
wire [4:0] BGRCALOVRD_in;
wire [4:0] QPLLRSVD2_in;
wire [4:0] QPLLRSVD3_in;
wire [7:0] PMARSVD0_in;
wire [7:0] PMARSVD1_in;
wire [7:0] PMASCANCLK_in;
wire [7:0] PMASCANIN_in;
wire [7:0] QPLLRSVD1_in;
wire [7:0] QPLLRSVD4_in;
wire [9:0] DRPADDR_in;
wire BGBYPASSB_delay;
wire BGMONITORENB_delay;
wire BGPDB_delay;
wire BGRCALOVRDENB_delay;
wire DRPCLK_delay;
wire DRPEN_delay;
wire DRPWE_delay;
wire GTGREFCLK0_delay;
wire GTGREFCLK1_delay;
wire GTNORTHREFCLK00_delay;
wire GTNORTHREFCLK01_delay;
wire GTNORTHREFCLK10_delay;
wire GTNORTHREFCLK11_delay;
wire GTREFCLK00_delay;
wire GTREFCLK01_delay;
wire GTREFCLK10_delay;
wire GTREFCLK11_delay;
wire GTSOUTHREFCLK00_delay;
wire GTSOUTHREFCLK01_delay;
wire GTSOUTHREFCLK10_delay;
wire GTSOUTHREFCLK11_delay;
wire QPLL0CLKRSVD0_delay;
wire QPLL0LOCKDETCLK_delay;
wire QPLL0LOCKEN_delay;
wire QPLL0PD_delay;
wire QPLL0RESET_delay;
wire QPLL1CLKRSVD0_delay;
wire QPLL1LOCKDETCLK_delay;
wire QPLL1LOCKEN_delay;
wire QPLL1PD_delay;
wire QPLL1RESET_delay;
wire RCALENB_delay;
wire SDM0RESET_delay;
wire SDM1RESET_delay;
wire [15:0] DRPDI_delay;
wire [1:0] SDM0WIDTH_delay;
wire [1:0] SDM1WIDTH_delay;
wire [24:0] SDM0DATA_delay;
wire [24:0] SDM1DATA_delay;
wire [2:0] QPLL0REFCLKSEL_delay;
wire [2:0] QPLL1REFCLKSEL_delay;
wire [4:0] BGRCALOVRD_delay;
wire [4:0] QPLLRSVD2_delay;
wire [4:0] QPLLRSVD3_delay;
wire [7:0] PMARSVD0_delay;
wire [7:0] PMARSVD1_delay;
wire [7:0] QPLLRSVD1_delay;
wire [7:0] QPLLRSVD4_delay;
wire [9:0] DRPADDR_delay;
assign #(out_delay) DRPDO = DRPDO_delay;
assign #(out_delay) DRPRDY = DRPRDY_delay;
assign #(out_delay) PMARSVDOUT0 = PMARSVDOUT0_delay;
assign #(out_delay) PMARSVDOUT1 = PMARSVDOUT1_delay;
assign #(out_delay) QPLL0FBCLKLOST = QPLL0FBCLKLOST_delay;
assign #(out_delay) QPLL0LOCK = QPLL0LOCK_delay;
assign #(out_delay) QPLL0OUTCLK = QPLL0OUTCLK_delay;
assign #(out_delay) QPLL0OUTREFCLK = QPLL0OUTREFCLK_delay;
assign #(out_delay) QPLL0REFCLKLOST = QPLL0REFCLKLOST_delay;
assign #(out_delay) QPLL1FBCLKLOST = QPLL1FBCLKLOST_delay;
assign #(out_delay) QPLL1LOCK = QPLL1LOCK_delay;
assign #(out_delay) QPLL1OUTCLK = QPLL1OUTCLK_delay;
assign #(out_delay) QPLL1OUTREFCLK = QPLL1OUTREFCLK_delay;
assign #(out_delay) QPLL1REFCLKLOST = QPLL1REFCLKLOST_delay;
assign #(out_delay) QPLLDMONITOR0 = QPLLDMONITOR0_delay;
assign #(out_delay) QPLLDMONITOR1 = QPLLDMONITOR1_delay;
assign #(out_delay) REFCLKOUTMONITOR0 = REFCLKOUTMONITOR0_delay;
assign #(out_delay) REFCLKOUTMONITOR1 = REFCLKOUTMONITOR1_delay;
assign #(out_delay) RXRECCLK0_SEL = RXRECCLK0_SEL_delay;
assign #(out_delay) RXRECCLK1_SEL = RXRECCLK1_SEL_delay;
assign #(out_delay) SDM0FINALOUT = SDM0FINALOUT_delay;
assign #(out_delay) SDM0TESTDATA = SDM0TESTDATA_delay;
assign #(out_delay) SDM1FINALOUT = SDM1FINALOUT_delay;
assign #(out_delay) SDM1TESTDATA = SDM1TESTDATA_delay;
`ifdef XIL_TIMING
reg notifier;
`endif
`ifndef XIL_TIMING // inputs with timing checks
assign #(inclk_delay) DRPCLK_delay = DRPCLK;
assign #(in_delay) DRPADDR_delay = DRPADDR;
assign #(in_delay) DRPDI_delay = DRPDI;
assign #(in_delay) DRPEN_delay = DRPEN;
assign #(in_delay) DRPWE_delay = DRPWE;
`endif
// inputs with no timing checks
assign #(inclk_delay) GTGREFCLK0_delay = GTGREFCLK0;
assign #(inclk_delay) GTGREFCLK1_delay = GTGREFCLK1;
assign #(inclk_delay) GTNORTHREFCLK00_delay = GTNORTHREFCLK00;
assign #(inclk_delay) GTNORTHREFCLK01_delay = GTNORTHREFCLK01;
assign #(inclk_delay) GTNORTHREFCLK10_delay = GTNORTHREFCLK10;
assign #(inclk_delay) GTNORTHREFCLK11_delay = GTNORTHREFCLK11;
assign #(inclk_delay) GTREFCLK00_delay = GTREFCLK00;
assign #(inclk_delay) GTREFCLK01_delay = GTREFCLK01;
assign #(inclk_delay) GTREFCLK10_delay = GTREFCLK10;
assign #(inclk_delay) GTREFCLK11_delay = GTREFCLK11;
assign #(inclk_delay) GTSOUTHREFCLK00_delay = GTSOUTHREFCLK00;
assign #(inclk_delay) GTSOUTHREFCLK01_delay = GTSOUTHREFCLK01;
assign #(inclk_delay) GTSOUTHREFCLK10_delay = GTSOUTHREFCLK10;
assign #(inclk_delay) GTSOUTHREFCLK11_delay = GTSOUTHREFCLK11;
assign #(inclk_delay) QPLL0CLKRSVD0_delay = QPLL0CLKRSVD0;
assign #(inclk_delay) QPLL0LOCKDETCLK_delay = QPLL0LOCKDETCLK;
assign #(inclk_delay) QPLL1CLKRSVD0_delay = QPLL1CLKRSVD0;
assign #(inclk_delay) QPLL1LOCKDETCLK_delay = QPLL1LOCKDETCLK;
assign #(in_delay) BGBYPASSB_delay = BGBYPASSB;
assign #(in_delay) BGMONITORENB_delay = BGMONITORENB;
assign #(in_delay) BGPDB_delay = BGPDB;
assign #(in_delay) BGRCALOVRDENB_delay = BGRCALOVRDENB;
assign #(in_delay) BGRCALOVRD_delay = BGRCALOVRD;
assign #(in_delay) PMARSVD0_delay = PMARSVD0;
assign #(in_delay) PMARSVD1_delay = PMARSVD1;
assign #(in_delay) QPLL0LOCKEN_delay = QPLL0LOCKEN;
assign #(in_delay) QPLL0PD_delay = QPLL0PD;
assign #(in_delay) QPLL0REFCLKSEL_delay = QPLL0REFCLKSEL;
assign #(in_delay) QPLL0RESET_delay = QPLL0RESET;
assign #(in_delay) QPLL1LOCKEN_delay = QPLL1LOCKEN;
assign #(in_delay) QPLL1PD_delay = QPLL1PD;
assign #(in_delay) QPLL1REFCLKSEL_delay = QPLL1REFCLKSEL;
assign #(in_delay) QPLL1RESET_delay = QPLL1RESET;
assign #(in_delay) QPLLRSVD1_delay = QPLLRSVD1;
assign #(in_delay) QPLLRSVD2_delay = QPLLRSVD2;
assign #(in_delay) QPLLRSVD3_delay = QPLLRSVD3;
assign #(in_delay) QPLLRSVD4_delay = QPLLRSVD4;
assign #(in_delay) RCALENB_delay = RCALENB;
assign #(in_delay) SDM0DATA_delay = SDM0DATA;
assign #(in_delay) SDM0RESET_delay = SDM0RESET;
assign #(in_delay) SDM0WIDTH_delay = SDM0WIDTH;
assign #(in_delay) SDM1DATA_delay = SDM1DATA;
assign #(in_delay) SDM1RESET_delay = SDM1RESET;
assign #(in_delay) SDM1WIDTH_delay = SDM1WIDTH;
assign DRPDO_delay = DRPDO_out;
assign DRPRDY_delay = DRPRDY_out;
assign PMARSVDOUT0_delay = PMARSVDOUT0_out;
assign PMARSVDOUT1_delay = PMARSVDOUT1_out;
assign QPLL0FBCLKLOST_delay = QPLL0FBCLKLOST_out;
assign QPLL0LOCK_delay = QPLL0LOCK_out;
assign QPLL0OUTCLK_delay = QPLL0OUTCLK_out;
assign QPLL0OUTREFCLK_delay = QPLL0OUTREFCLK_out;
assign QPLL0REFCLKLOST_delay = QPLL0REFCLKLOST_out;
assign QPLL1FBCLKLOST_delay = QPLL1FBCLKLOST_out;
assign QPLL1LOCK_delay = QPLL1LOCK_out;
assign QPLL1OUTCLK_delay = QPLL1OUTCLK_out;
assign QPLL1OUTREFCLK_delay = QPLL1OUTREFCLK_out;
assign QPLL1REFCLKLOST_delay = QPLL1REFCLKLOST_out;
assign QPLLDMONITOR0_delay = QPLLDMONITOR0_out;
assign QPLLDMONITOR1_delay = QPLLDMONITOR1_out;
assign REFCLKOUTMONITOR0_delay = REFCLKOUTMONITOR0_out;
assign REFCLKOUTMONITOR1_delay = REFCLKOUTMONITOR1_out;
assign RXRECCLK0_SEL_delay = RXRECCLK0_SEL_out;
assign RXRECCLK1_SEL_delay = RXRECCLK1_SEL_out;
assign SDM0FINALOUT_delay = SDM0FINALOUT_out;
assign SDM0TESTDATA_delay = SDM0TESTDATA_out;
assign SDM1FINALOUT_delay = SDM1FINALOUT_out;
assign SDM1TESTDATA_delay = SDM1TESTDATA_out;
assign BGBYPASSB_in = BGBYPASSB_delay;
assign BGMONITORENB_in = BGMONITORENB_delay;
assign BGPDB_in = BGPDB_delay;
assign BGRCALOVRDENB_in = BGRCALOVRDENB_delay;
assign BGRCALOVRD_in = BGRCALOVRD_delay;
assign DRPADDR_in[0] = (DRPADDR[0] !== 1'bz) && DRPADDR_delay[0]; // rv 0
assign DRPADDR_in[1] = (DRPADDR[1] !== 1'bz) && DRPADDR_delay[1]; // rv 0
assign DRPADDR_in[2] = (DRPADDR[2] !== 1'bz) && DRPADDR_delay[2]; // rv 0
assign DRPADDR_in[3] = (DRPADDR[3] !== 1'bz) && DRPADDR_delay[3]; // rv 0
assign DRPADDR_in[4] = (DRPADDR[4] !== 1'bz) && DRPADDR_delay[4]; // rv 0
assign DRPADDR_in[5] = (DRPADDR[5] !== 1'bz) && DRPADDR_delay[5]; // rv 0
assign DRPADDR_in[6] = (DRPADDR[6] !== 1'bz) && DRPADDR_delay[6]; // rv 0
assign DRPADDR_in[7] = (DRPADDR[7] !== 1'bz) && DRPADDR_delay[7]; // rv 0
assign DRPADDR_in[8] = (DRPADDR[8] !== 1'bz) && DRPADDR_delay[8]; // rv 0
assign DRPADDR_in[9] = (DRPADDR[9] !== 1'bz) && DRPADDR_delay[9]; // rv 0
assign DRPCLK_in = (DRPCLK !== 1'bz) && DRPCLK_delay; // rv 0
assign DRPDI_in[0] = (DRPDI[0] !== 1'bz) && DRPDI_delay[0]; // rv 0
assign DRPDI_in[10] = (DRPDI[10] !== 1'bz) && DRPDI_delay[10]; // rv 0
assign DRPDI_in[11] = (DRPDI[11] !== 1'bz) && DRPDI_delay[11]; // rv 0
assign DRPDI_in[12] = (DRPDI[12] !== 1'bz) && DRPDI_delay[12]; // rv 0
assign DRPDI_in[13] = (DRPDI[13] !== 1'bz) && DRPDI_delay[13]; // rv 0
assign DRPDI_in[14] = (DRPDI[14] !== 1'bz) && DRPDI_delay[14]; // rv 0
assign DRPDI_in[15] = (DRPDI[15] !== 1'bz) && DRPDI_delay[15]; // rv 0
assign DRPDI_in[1] = (DRPDI[1] !== 1'bz) && DRPDI_delay[1]; // rv 0
assign DRPDI_in[2] = (DRPDI[2] !== 1'bz) && DRPDI_delay[2]; // rv 0
assign DRPDI_in[3] = (DRPDI[3] !== 1'bz) && DRPDI_delay[3]; // rv 0
assign DRPDI_in[4] = (DRPDI[4] !== 1'bz) && DRPDI_delay[4]; // rv 0
assign DRPDI_in[5] = (DRPDI[5] !== 1'bz) && DRPDI_delay[5]; // rv 0
assign DRPDI_in[6] = (DRPDI[6] !== 1'bz) && DRPDI_delay[6]; // rv 0
assign DRPDI_in[7] = (DRPDI[7] !== 1'bz) && DRPDI_delay[7]; // rv 0
assign DRPDI_in[8] = (DRPDI[8] !== 1'bz) && DRPDI_delay[8]; // rv 0
assign DRPDI_in[9] = (DRPDI[9] !== 1'bz) && DRPDI_delay[9]; // rv 0
assign DRPEN_in = (DRPEN !== 1'bz) && DRPEN_delay; // rv 0
assign DRPWE_in = (DRPWE !== 1'bz) && DRPWE_delay; // rv 0
assign GTGREFCLK0_in = GTGREFCLK0_delay;
assign GTGREFCLK1_in = GTGREFCLK1_delay;
assign GTNORTHREFCLK00_in = GTNORTHREFCLK00_delay;
assign GTNORTHREFCLK01_in = GTNORTHREFCLK01_delay;
assign GTNORTHREFCLK10_in = GTNORTHREFCLK10_delay;
assign GTNORTHREFCLK11_in = GTNORTHREFCLK11_delay;
assign GTREFCLK00_in = GTREFCLK00_delay;
assign GTREFCLK01_in = GTREFCLK01_delay;
assign GTREFCLK10_in = GTREFCLK10_delay;
assign GTREFCLK11_in = GTREFCLK11_delay;
assign GTSOUTHREFCLK00_in = GTSOUTHREFCLK00_delay;
assign GTSOUTHREFCLK01_in = GTSOUTHREFCLK01_delay;
assign GTSOUTHREFCLK10_in = GTSOUTHREFCLK10_delay;
assign GTSOUTHREFCLK11_in = GTSOUTHREFCLK11_delay;
assign PMARSVD0_in[0] = (PMARSVD0[0] !== 1'bz) && PMARSVD0_delay[0]; // rv 0
assign PMARSVD0_in[1] = (PMARSVD0[1] !== 1'bz) && PMARSVD0_delay[1]; // rv 0
assign PMARSVD0_in[2] = (PMARSVD0[2] !== 1'bz) && PMARSVD0_delay[2]; // rv 0
assign PMARSVD0_in[3] = (PMARSVD0[3] !== 1'bz) && PMARSVD0_delay[3]; // rv 0
assign PMARSVD0_in[4] = (PMARSVD0[4] !== 1'bz) && PMARSVD0_delay[4]; // rv 0
assign PMARSVD0_in[5] = (PMARSVD0[5] !== 1'bz) && PMARSVD0_delay[5]; // rv 0
assign PMARSVD0_in[6] = (PMARSVD0[6] !== 1'bz) && PMARSVD0_delay[6]; // rv 0
assign PMARSVD0_in[7] = (PMARSVD0[7] !== 1'bz) && PMARSVD0_delay[7]; // rv 0
assign PMARSVD1_in[0] = (PMARSVD1[0] !== 1'bz) && PMARSVD1_delay[0]; // rv 0
assign PMARSVD1_in[1] = (PMARSVD1[1] !== 1'bz) && PMARSVD1_delay[1]; // rv 0
assign PMARSVD1_in[2] = (PMARSVD1[2] !== 1'bz) && PMARSVD1_delay[2]; // rv 0
assign PMARSVD1_in[3] = (PMARSVD1[3] !== 1'bz) && PMARSVD1_delay[3]; // rv 0
assign PMARSVD1_in[4] = (PMARSVD1[4] !== 1'bz) && PMARSVD1_delay[4]; // rv 0
assign PMARSVD1_in[5] = (PMARSVD1[5] !== 1'bz) && PMARSVD1_delay[5]; // rv 0
assign PMARSVD1_in[6] = (PMARSVD1[6] !== 1'bz) && PMARSVD1_delay[6]; // rv 0
assign PMARSVD1_in[7] = (PMARSVD1[7] !== 1'bz) && PMARSVD1_delay[7]; // rv 0
assign QPLL0CLKRSVD0_in = (QPLL0CLKRSVD0 === 1'bz) || QPLL0CLKRSVD0_delay; // rv 1
assign QPLL0LOCKDETCLK_in = (QPLL0LOCKDETCLK === 1'bz) || QPLL0LOCKDETCLK_delay; // rv 1
assign QPLL0LOCKEN_in = (QPLL0LOCKEN !== 1'bz) && QPLL0LOCKEN_delay; // rv 0
assign QPLL0PD_in = (QPLL0PD !== 1'bz) && QPLL0PD_delay; // rv 0
assign QPLL0REFCLKSEL_in[0] = (QPLL0REFCLKSEL[0] === 1'bz) || QPLL0REFCLKSEL_delay[0]; // rv 1
assign QPLL0REFCLKSEL_in[1] = (QPLL0REFCLKSEL[1] !== 1'bz) && QPLL0REFCLKSEL_delay[1]; // rv 0
assign QPLL0REFCLKSEL_in[2] = (QPLL0REFCLKSEL[2] !== 1'bz) && QPLL0REFCLKSEL_delay[2]; // rv 0
assign QPLL0RESET_in = (QPLL0RESET !== 1'bz) && QPLL0RESET_delay; // rv 0
assign QPLL1CLKRSVD0_in = (QPLL1CLKRSVD0 === 1'bz) || QPLL1CLKRSVD0_delay; // rv 1
assign QPLL1LOCKDETCLK_in = (QPLL1LOCKDETCLK === 1'bz) || QPLL1LOCKDETCLK_delay; // rv 1
assign QPLL1LOCKEN_in = (QPLL1LOCKEN !== 1'bz) && QPLL1LOCKEN_delay; // rv 0
assign QPLL1PD_in = (QPLL1PD !== 1'bz) && QPLL1PD_delay; // rv 0
assign QPLL1REFCLKSEL_in[0] = (QPLL1REFCLKSEL[0] === 1'bz) || QPLL1REFCLKSEL_delay[0]; // rv 1
assign QPLL1REFCLKSEL_in[1] = (QPLL1REFCLKSEL[1] !== 1'bz) && QPLL1REFCLKSEL_delay[1]; // rv 0
assign QPLL1REFCLKSEL_in[2] = (QPLL1REFCLKSEL[2] !== 1'bz) && QPLL1REFCLKSEL_delay[2]; // rv 0
assign QPLL1RESET_in = (QPLL1RESET !== 1'bz) && QPLL1RESET_delay; // rv 0
assign QPLLRSVD1_in[0] = (QPLLRSVD1[0] !== 1'bz) && QPLLRSVD1_delay[0]; // rv 0
assign QPLLRSVD1_in[1] = (QPLLRSVD1[1] !== 1'bz) && QPLLRSVD1_delay[1]; // rv 0
assign QPLLRSVD1_in[2] = (QPLLRSVD1[2] !== 1'bz) && QPLLRSVD1_delay[2]; // rv 0
assign QPLLRSVD1_in[3] = (QPLLRSVD1[3] !== 1'bz) && QPLLRSVD1_delay[3]; // rv 0
assign QPLLRSVD1_in[4] = (QPLLRSVD1[4] !== 1'bz) && QPLLRSVD1_delay[4]; // rv 0
assign QPLLRSVD1_in[5] = (QPLLRSVD1[5] !== 1'bz) && QPLLRSVD1_delay[5]; // rv 0
assign QPLLRSVD1_in[6] = (QPLLRSVD1[6] !== 1'bz) && QPLLRSVD1_delay[6]; // rv 0
assign QPLLRSVD1_in[7] = (QPLLRSVD1[7] !== 1'bz) && QPLLRSVD1_delay[7]; // rv 0
assign QPLLRSVD2_in[0] = (QPLLRSVD2[0] !== 1'bz) && QPLLRSVD2_delay[0]; // rv 0
assign QPLLRSVD2_in[1] = (QPLLRSVD2[1] !== 1'bz) && QPLLRSVD2_delay[1]; // rv 0
assign QPLLRSVD2_in[2] = (QPLLRSVD2[2] !== 1'bz) && QPLLRSVD2_delay[2]; // rv 0
assign QPLLRSVD2_in[3] = (QPLLRSVD2[3] !== 1'bz) && QPLLRSVD2_delay[3]; // rv 0
assign QPLLRSVD2_in[4] = (QPLLRSVD2[4] !== 1'bz) && QPLLRSVD2_delay[4]; // rv 0
assign QPLLRSVD3_in[0] = (QPLLRSVD3[0] !== 1'bz) && QPLLRSVD3_delay[0]; // rv 0
assign QPLLRSVD3_in[1] = (QPLLRSVD3[1] !== 1'bz) && QPLLRSVD3_delay[1]; // rv 0
assign QPLLRSVD3_in[2] = (QPLLRSVD3[2] !== 1'bz) && QPLLRSVD3_delay[2]; // rv 0
assign QPLLRSVD3_in[3] = (QPLLRSVD3[3] !== 1'bz) && QPLLRSVD3_delay[3]; // rv 0
assign QPLLRSVD3_in[4] = (QPLLRSVD3[4] !== 1'bz) && QPLLRSVD3_delay[4]; // rv 0
assign QPLLRSVD4_in[0] = (QPLLRSVD4[0] !== 1'bz) && QPLLRSVD4_delay[0]; // rv 0
assign QPLLRSVD4_in[1] = (QPLLRSVD4[1] !== 1'bz) && QPLLRSVD4_delay[1]; // rv 0
assign QPLLRSVD4_in[2] = (QPLLRSVD4[2] !== 1'bz) && QPLLRSVD4_delay[2]; // rv 0
assign QPLLRSVD4_in[3] = (QPLLRSVD4[3] !== 1'bz) && QPLLRSVD4_delay[3]; // rv 0
assign QPLLRSVD4_in[4] = (QPLLRSVD4[4] !== 1'bz) && QPLLRSVD4_delay[4]; // rv 0
assign QPLLRSVD4_in[5] = (QPLLRSVD4[5] !== 1'bz) && QPLLRSVD4_delay[5]; // rv 0
assign QPLLRSVD4_in[6] = (QPLLRSVD4[6] !== 1'bz) && QPLLRSVD4_delay[6]; // rv 0
assign QPLLRSVD4_in[7] = (QPLLRSVD4[7] !== 1'bz) && QPLLRSVD4_delay[7]; // rv 0
assign RCALENB_in = RCALENB_delay;
assign SDM0DATA_in[0] = (SDM0DATA[0] !== 1'bz) && SDM0DATA_delay[0]; // rv 0
assign SDM0DATA_in[10] = (SDM0DATA[10] !== 1'bz) && SDM0DATA_delay[10]; // rv 0
assign SDM0DATA_in[11] = (SDM0DATA[11] !== 1'bz) && SDM0DATA_delay[11]; // rv 0
assign SDM0DATA_in[12] = (SDM0DATA[12] !== 1'bz) && SDM0DATA_delay[12]; // rv 0
assign SDM0DATA_in[13] = (SDM0DATA[13] !== 1'bz) && SDM0DATA_delay[13]; // rv 0
assign SDM0DATA_in[14] = (SDM0DATA[14] !== 1'bz) && SDM0DATA_delay[14]; // rv 0
assign SDM0DATA_in[15] = (SDM0DATA[15] !== 1'bz) && SDM0DATA_delay[15]; // rv 0
assign SDM0DATA_in[16] = (SDM0DATA[16] !== 1'bz) && SDM0DATA_delay[16]; // rv 0
assign SDM0DATA_in[17] = (SDM0DATA[17] !== 1'bz) && SDM0DATA_delay[17]; // rv 0
assign SDM0DATA_in[18] = (SDM0DATA[18] !== 1'bz) && SDM0DATA_delay[18]; // rv 0
assign SDM0DATA_in[19] = (SDM0DATA[19] !== 1'bz) && SDM0DATA_delay[19]; // rv 0
assign SDM0DATA_in[1] = (SDM0DATA[1] !== 1'bz) && SDM0DATA_delay[1]; // rv 0
assign SDM0DATA_in[20] = (SDM0DATA[20] !== 1'bz) && SDM0DATA_delay[20]; // rv 0
assign SDM0DATA_in[21] = (SDM0DATA[21] !== 1'bz) && SDM0DATA_delay[21]; // rv 0
assign SDM0DATA_in[22] = (SDM0DATA[22] !== 1'bz) && SDM0DATA_delay[22]; // rv 0
assign SDM0DATA_in[23] = (SDM0DATA[23] !== 1'bz) && SDM0DATA_delay[23]; // rv 0
assign SDM0DATA_in[24] = (SDM0DATA[24] !== 1'bz) && SDM0DATA_delay[24]; // rv 0
assign SDM0DATA_in[2] = (SDM0DATA[2] !== 1'bz) && SDM0DATA_delay[2]; // rv 0
assign SDM0DATA_in[3] = (SDM0DATA[3] !== 1'bz) && SDM0DATA_delay[3]; // rv 0
assign SDM0DATA_in[4] = (SDM0DATA[4] !== 1'bz) && SDM0DATA_delay[4]; // rv 0
assign SDM0DATA_in[5] = (SDM0DATA[5] !== 1'bz) && SDM0DATA_delay[5]; // rv 0
assign SDM0DATA_in[6] = (SDM0DATA[6] !== 1'bz) && SDM0DATA_delay[6]; // rv 0
assign SDM0DATA_in[7] = (SDM0DATA[7] !== 1'bz) && SDM0DATA_delay[7]; // rv 0
assign SDM0DATA_in[8] = (SDM0DATA[8] !== 1'bz) && SDM0DATA_delay[8]; // rv 0
assign SDM0DATA_in[9] = (SDM0DATA[9] !== 1'bz) && SDM0DATA_delay[9]; // rv 0
assign SDM0RESET_in = (SDM0RESET !== 1'bz) && SDM0RESET_delay; // rv 0
assign SDM0WIDTH_in[0] = (SDM0WIDTH[0] !== 1'bz) && SDM0WIDTH_delay[0]; // rv 0
assign SDM0WIDTH_in[1] = (SDM0WIDTH[1] !== 1'bz) && SDM0WIDTH_delay[1]; // rv 0
assign SDM1DATA_in[0] = (SDM1DATA[0] !== 1'bz) && SDM1DATA_delay[0]; // rv 0
assign SDM1DATA_in[10] = (SDM1DATA[10] !== 1'bz) && SDM1DATA_delay[10]; // rv 0
assign SDM1DATA_in[11] = (SDM1DATA[11] !== 1'bz) && SDM1DATA_delay[11]; // rv 0
assign SDM1DATA_in[12] = (SDM1DATA[12] !== 1'bz) && SDM1DATA_delay[12]; // rv 0
assign SDM1DATA_in[13] = (SDM1DATA[13] !== 1'bz) && SDM1DATA_delay[13]; // rv 0
assign SDM1DATA_in[14] = (SDM1DATA[14] !== 1'bz) && SDM1DATA_delay[14]; // rv 0
assign SDM1DATA_in[15] = (SDM1DATA[15] !== 1'bz) && SDM1DATA_delay[15]; // rv 0
assign SDM1DATA_in[16] = (SDM1DATA[16] !== 1'bz) && SDM1DATA_delay[16]; // rv 0
assign SDM1DATA_in[17] = (SDM1DATA[17] !== 1'bz) && SDM1DATA_delay[17]; // rv 0
assign SDM1DATA_in[18] = (SDM1DATA[18] !== 1'bz) && SDM1DATA_delay[18]; // rv 0
assign SDM1DATA_in[19] = (SDM1DATA[19] !== 1'bz) && SDM1DATA_delay[19]; // rv 0
assign SDM1DATA_in[1] = (SDM1DATA[1] !== 1'bz) && SDM1DATA_delay[1]; // rv 0
assign SDM1DATA_in[20] = (SDM1DATA[20] !== 1'bz) && SDM1DATA_delay[20]; // rv 0
assign SDM1DATA_in[21] = (SDM1DATA[21] !== 1'bz) && SDM1DATA_delay[21]; // rv 0
assign SDM1DATA_in[22] = (SDM1DATA[22] !== 1'bz) && SDM1DATA_delay[22]; // rv 0
assign SDM1DATA_in[23] = (SDM1DATA[23] !== 1'bz) && SDM1DATA_delay[23]; // rv 0
assign SDM1DATA_in[24] = (SDM1DATA[24] !== 1'bz) && SDM1DATA_delay[24]; // rv 0
assign SDM1DATA_in[2] = (SDM1DATA[2] !== 1'bz) && SDM1DATA_delay[2]; // rv 0
assign SDM1DATA_in[3] = (SDM1DATA[3] !== 1'bz) && SDM1DATA_delay[3]; // rv 0
assign SDM1DATA_in[4] = (SDM1DATA[4] !== 1'bz) && SDM1DATA_delay[4]; // rv 0
assign SDM1DATA_in[5] = (SDM1DATA[5] !== 1'bz) && SDM1DATA_delay[5]; // rv 0
assign SDM1DATA_in[6] = (SDM1DATA[6] !== 1'bz) && SDM1DATA_delay[6]; // rv 0
assign SDM1DATA_in[7] = (SDM1DATA[7] !== 1'bz) && SDM1DATA_delay[7]; // rv 0
assign SDM1DATA_in[8] = (SDM1DATA[8] !== 1'bz) && SDM1DATA_delay[8]; // rv 0
assign SDM1DATA_in[9] = (SDM1DATA[9] !== 1'bz) && SDM1DATA_delay[9]; // rv 0
assign SDM1RESET_in = (SDM1RESET !== 1'bz) && SDM1RESET_delay; // rv 0
assign SDM1WIDTH_in[0] = (SDM1WIDTH[0] !== 1'bz) && SDM1WIDTH_delay[0]; // rv 0
assign SDM1WIDTH_in[1] = (SDM1WIDTH[1] !== 1'bz) && SDM1WIDTH_delay[1]; // rv 0
initial begin
#1;
trig_attr = ~trig_attr;
end
always @ (trig_attr) begin
#1;
if ((attr_test == 1'b1) ||
((QPLL0CLKOUT_RATE_REG != "FULL") &&
(QPLL0CLKOUT_RATE_REG != "HALF"))) begin
$display("Error: [Unisim %s-152] QPLL0CLKOUT_RATE attribute is set to %s. Legal values for this attribute are FULL or HALF. Instance: %m", MODULE_NAME, QPLL0CLKOUT_RATE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((QPLL0_FBDIV_REG < 16) || (QPLL0_FBDIV_REG > 160))) begin
$display("Error: [Unisim %s-163] QPLL0_FBDIV attribute is set to %d. Legal values for this attribute are 16 to 160. Instance: %m", MODULE_NAME, QPLL0_FBDIV_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((QPLL0_FBDIV_G3_REG < 16) || (QPLL0_FBDIV_G3_REG > 160))) begin
$display("Error: [Unisim %s-164] QPLL0_FBDIV_G3 attribute is set to %d. Legal values for this attribute are 16 to 160. Instance: %m", MODULE_NAME, QPLL0_FBDIV_G3_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((QPLL0_REFCLK_DIV_REG != 2) &&
(QPLL0_REFCLK_DIV_REG != 1) &&
(QPLL0_REFCLK_DIV_REG != 3) &&
(QPLL0_REFCLK_DIV_REG != 4) &&
(QPLL0_REFCLK_DIV_REG != 5) &&
(QPLL0_REFCLK_DIV_REG != 6) &&
(QPLL0_REFCLK_DIV_REG != 8) &&
(QPLL0_REFCLK_DIV_REG != 10) &&
(QPLL0_REFCLK_DIV_REG != 12) &&
(QPLL0_REFCLK_DIV_REG != 16) &&
(QPLL0_REFCLK_DIV_REG != 20))) begin
$display("Error: [Unisim %s-171] QPLL0_REFCLK_DIV attribute is set to %d. Legal values for this attribute are 2, 1, 3, 4, 5, 6, 8, 10, 12, 16 or 20. Instance: %m", MODULE_NAME, QPLL0_REFCLK_DIV_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((QPLL1CLKOUT_RATE_REG != "FULL") &&
(QPLL1CLKOUT_RATE_REG != "HALF"))) begin
$display("Error: [Unisim %s-175] QPLL1CLKOUT_RATE attribute is set to %s. Legal values for this attribute are FULL or HALF. Instance: %m", MODULE_NAME, QPLL1CLKOUT_RATE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((QPLL1_FBDIV_REG < 16) || (QPLL1_FBDIV_REG > 160))) begin
$display("Error: [Unisim %s-186] QPLL1_FBDIV attribute is set to %d. Legal values for this attribute are 16 to 160. Instance: %m", MODULE_NAME, QPLL1_FBDIV_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((QPLL1_FBDIV_G3_REG < 16) || (QPLL1_FBDIV_G3_REG > 160))) begin
$display("Error: [Unisim %s-187] QPLL1_FBDIV_G3 attribute is set to %d. Legal values for this attribute are 16 to 160. Instance: %m", MODULE_NAME, QPLL1_FBDIV_G3_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((QPLL1_REFCLK_DIV_REG != 2) &&
(QPLL1_REFCLK_DIV_REG != 1) &&
(QPLL1_REFCLK_DIV_REG != 3) &&
(QPLL1_REFCLK_DIV_REG != 4) &&
(QPLL1_REFCLK_DIV_REG != 5) &&
(QPLL1_REFCLK_DIV_REG != 6) &&
(QPLL1_REFCLK_DIV_REG != 8) &&
(QPLL1_REFCLK_DIV_REG != 10) &&
(QPLL1_REFCLK_DIV_REG != 12) &&
(QPLL1_REFCLK_DIV_REG != 16) &&
(QPLL1_REFCLK_DIV_REG != 20))) begin
$display("Error: [Unisim %s-194] QPLL1_REFCLK_DIV attribute is set to %d. Legal values for this attribute are 2, 1, 3, 4, 5, 6, 8, 10, 12, 16 or 20. Instance: %m", MODULE_NAME, QPLL1_REFCLK_DIV_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
(SIM_MODE != "FAST")) begin
$display("Error: [Unisim %s-218] SIM_MODE attribute is set to %s. Legal values for this attribute are FAST. Instance: %m", MODULE_NAME, SIM_MODE);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((SIM_RESET_SPEEDUP != "TRUE") &&
(SIM_RESET_SPEEDUP != "FALSE"))) begin
$display("Error: [Unisim %s-219] SIM_RESET_SPEEDUP attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, SIM_RESET_SPEEDUP);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((SIM_VERSION != 2) &&
(SIM_VERSION != 1) &&
(SIM_VERSION != 3))) begin
$display("Error: [Unisim %s-220] SIM_VERSION attribute is set to %d. Legal values for this attribute are 2, 1 or 3. Instance: %m", MODULE_NAME, SIM_VERSION);
attr_err = 1'b1;
end
if (attr_err == 1'b1) #1 $finish;
end
assign PMASCANCLK_in = 8'b11111111; // tie off
assign PMASCANENB_in = 1'b1; // tie off
assign PMASCANIN_in = 8'b11111111; // tie off
assign QDPMASCANMODEB_in = 1'b1; // tie off
assign QDPMASCANRSTEN_in = 1'b1; // tie off
assign RXRECCLK_in = 4'b1111; // tie off
SIP_GTYE3_COMMON #(
.SIM_MODE (SIM_MODE),
.SIM_RESET_SPEEDUP (SIM_RESET_SPEEDUP),
.SIM_VERSION (SIM_VERSION)
) SIP_GTYE3_COMMON_INST (
.AEN_BGBS0 (AEN_BGBS0_REG),
.AEN_BGBS1 (AEN_BGBS1_REG),
.AEN_MASTER0 (AEN_MASTER0_REG),
.AEN_MASTER1 (AEN_MASTER1_REG),
.AEN_PD0 (AEN_PD0_REG),
.AEN_PD1 (AEN_PD1_REG),
.AEN_QPLL0 (AEN_QPLL0_REG),
.AEN_QPLL1 (AEN_QPLL1_REG),
.AEN_REFCLK0 (AEN_REFCLK0_REG),
.AEN_REFCLK1 (AEN_REFCLK1_REG),
.AEN_RESET0 (AEN_RESET0_REG),
.AEN_RESET1 (AEN_RESET1_REG),
.AEN_SDMDATA0 (AEN_SDMDATA0_REG),
.AEN_SDMDATA1 (AEN_SDMDATA1_REG),
.AEN_SDMRESET0 (AEN_SDMRESET0_REG),
.AEN_SDMRESET1 (AEN_SDMRESET1_REG),
.AEN_SDMWIDTH0 (AEN_SDMWIDTH0_REG),
.AEN_SDMWIDTH1 (AEN_SDMWIDTH1_REG),
.AQDMUXSEL1 (AQDMUXSEL1_REG),
.AVCC_SENSE_SEL (AVCC_SENSE_SEL_REG),
.AVTT_SENSE_SEL (AVTT_SENSE_SEL_REG),
.A_BGMONITOREN (A_BGMONITOREN_REG),
.A_BGPD (A_BGPD_REG),
.A_GTREFCLKPD0 (A_GTREFCLKPD0_REG),
.A_GTREFCLKPD1 (A_GTREFCLKPD1_REG),
.A_QPLL0LOCKEN (A_QPLL0LOCKEN_REG),
.A_QPLL0PD (A_QPLL0PD_REG),
.A_QPLL0RESET (A_QPLL0RESET_REG),
.A_QPLL1LOCKEN (A_QPLL1LOCKEN_REG),
.A_QPLL1PD (A_QPLL1PD_REG),
.A_QPLL1RESET (A_QPLL1RESET_REG),
.A_SDM0DATA1_0 (A_SDM0DATA1_0_REG),
.A_SDM0DATA1_1 (A_SDM0DATA1_1_REG),
.A_SDM1DATA1_0 (A_SDM1DATA1_0_REG),
.A_SDM1DATA1_1 (A_SDM1DATA1_1_REG),
.A_SDMRESET0 (A_SDMRESET0_REG),
.A_SDMRESET1 (A_SDMRESET1_REG),
.BIAS_CFG0 (BIAS_CFG0_REG),
.BIAS_CFG1 (BIAS_CFG1_REG),
.BIAS_CFG2 (BIAS_CFG2_REG),
.BIAS_CFG3 (BIAS_CFG3_REG),
.BIAS_CFG4 (BIAS_CFG4_REG),
.BIAS_CFG_RSVD (BIAS_CFG_RSVD_REG),
.COMMON_AMUX_SEL0 (COMMON_AMUX_SEL0_REG),
.COMMON_AMUX_SEL1 (COMMON_AMUX_SEL1_REG),
.COMMON_CFG0 (COMMON_CFG0_REG),
.COMMON_CFG1 (COMMON_CFG1_REG),
.COMMON_INSTANTIATED (COMMON_INSTANTIATED_REG),
.POR_CFG (POR_CFG_REG),
.PPF0_CFG (PPF0_CFG_REG),
.PPF1_CFG (PPF1_CFG_REG),
.QPLL0CLKOUT_RATE (QPLL0CLKOUT_RATE_REG),
.QPLL0_AMONITOR_SEL (QPLL0_AMONITOR_SEL_REG),
.QPLL0_CFG0 (QPLL0_CFG0_REG),
.QPLL0_CFG1 (QPLL0_CFG1_REG),
.QPLL0_CFG1_G3 (QPLL0_CFG1_G3_REG),
.QPLL0_CFG2 (QPLL0_CFG2_REG),
.QPLL0_CFG2_G3 (QPLL0_CFG2_G3_REG),
.QPLL0_CFG3 (QPLL0_CFG3_REG),
.QPLL0_CFG4 (QPLL0_CFG4_REG),
.QPLL0_CP (QPLL0_CP_REG),
.QPLL0_CP_G3 (QPLL0_CP_G3_REG),
.QPLL0_FBDIV (QPLL0_FBDIV_REG),
.QPLL0_FBDIV_G3 (QPLL0_FBDIV_G3_REG),
.QPLL0_INIT_CFG0 (QPLL0_INIT_CFG0_REG),
.QPLL0_INIT_CFG1 (QPLL0_INIT_CFG1_REG),
.QPLL0_LOCK_CFG (QPLL0_LOCK_CFG_REG),
.QPLL0_LOCK_CFG_G3 (QPLL0_LOCK_CFG_G3_REG),
.QPLL0_LPF (QPLL0_LPF_REG),
.QPLL0_LPF_G3 (QPLL0_LPF_G3_REG),
.QPLL0_REFCLK_DIV (QPLL0_REFCLK_DIV_REG),
.QPLL0_SDM_CFG0 (QPLL0_SDM_CFG0_REG),
.QPLL0_SDM_CFG1 (QPLL0_SDM_CFG1_REG),
.QPLL0_SDM_CFG2 (QPLL0_SDM_CFG2_REG),
.QPLL1CLKOUT_RATE (QPLL1CLKOUT_RATE_REG),
.QPLL1_AMONITOR_SEL (QPLL1_AMONITOR_SEL_REG),
.QPLL1_CFG0 (QPLL1_CFG0_REG),
.QPLL1_CFG1 (QPLL1_CFG1_REG),
.QPLL1_CFG1_G3 (QPLL1_CFG1_G3_REG),
.QPLL1_CFG2 (QPLL1_CFG2_REG),
.QPLL1_CFG2_G3 (QPLL1_CFG2_G3_REG),
.QPLL1_CFG3 (QPLL1_CFG3_REG),
.QPLL1_CFG4 (QPLL1_CFG4_REG),
.QPLL1_CP (QPLL1_CP_REG),
.QPLL1_CP_G3 (QPLL1_CP_G3_REG),
.QPLL1_FBDIV (QPLL1_FBDIV_REG),
.QPLL1_FBDIV_G3 (QPLL1_FBDIV_G3_REG),
.QPLL1_INIT_CFG0 (QPLL1_INIT_CFG0_REG),
.QPLL1_INIT_CFG1 (QPLL1_INIT_CFG1_REG),
.QPLL1_LOCK_CFG (QPLL1_LOCK_CFG_REG),
.QPLL1_LOCK_CFG_G3 (QPLL1_LOCK_CFG_G3_REG),
.QPLL1_LPF (QPLL1_LPF_REG),
.QPLL1_LPF_G3 (QPLL1_LPF_G3_REG),
.QPLL1_REFCLK_DIV (QPLL1_REFCLK_DIV_REG),
.QPLL1_SDM_CFG0 (QPLL1_SDM_CFG0_REG),
.QPLL1_SDM_CFG1 (QPLL1_SDM_CFG1_REG),
.QPLL1_SDM_CFG2 (QPLL1_SDM_CFG2_REG),
.RCALSAP_TESTEN (RCALSAP_TESTEN_REG),
.RCAL_APROBE (RCAL_APROBE_REG),
.REFCLK0_EN_DC_COUP (REFCLK0_EN_DC_COUP_REG),
.REFCLK0_VCM_HIGH (REFCLK0_VCM_HIGH_REG),
.REFCLK0_VCM_LOW (REFCLK0_VCM_LOW_REG),
.REFCLK1_EN_DC_COUP (REFCLK1_EN_DC_COUP_REG),
.REFCLK1_VCM_HIGH (REFCLK1_VCM_HIGH_REG),
.REFCLK1_VCM_LOW (REFCLK1_VCM_LOW_REG),
.RSVD_ATTR0 (RSVD_ATTR0_REG),
.RSVD_ATTR1 (RSVD_ATTR1_REG),
.RSVD_ATTR2 (RSVD_ATTR2_REG),
.RSVD_ATTR3 (RSVD_ATTR3_REG),
.RXRECCLKOUT0_SEL (RXRECCLKOUT0_SEL_REG),
.RXRECCLKOUT1_SEL (RXRECCLKOUT1_SEL_REG),
.SARC_EN (SARC_EN_REG),
.SARC_SEL (SARC_SEL_REG),
.SDM0INITSEED0_0 (SDM0INITSEED0_0_REG),
.SDM0INITSEED0_1 (SDM0INITSEED0_1_REG),
.SDM1INITSEED0_0 (SDM1INITSEED0_0_REG),
.SDM1INITSEED0_1 (SDM1INITSEED0_1_REG),
.VCCAUX_SENSE_SEL (VCCAUX_SENSE_SEL_REG),
.DRPDO (DRPDO_out),
.DRPRDY (DRPRDY_out),
.PMARSVDOUT0 (PMARSVDOUT0_out),
.PMARSVDOUT1 (PMARSVDOUT1_out),
.PMASCANOUT (PMASCANOUT_out),
.QPLL0FBCLKLOST (QPLL0FBCLKLOST_out),
.QPLL0LOCK (QPLL0LOCK_out),
.QPLL0OUTCLK (QPLL0OUTCLK_out),
.QPLL0OUTREFCLK (QPLL0OUTREFCLK_out),
.QPLL0REFCLKLOST (QPLL0REFCLKLOST_out),
.QPLL1FBCLKLOST (QPLL1FBCLKLOST_out),
.QPLL1LOCK (QPLL1LOCK_out),
.QPLL1OUTCLK (QPLL1OUTCLK_out),
.QPLL1OUTREFCLK (QPLL1OUTREFCLK_out),
.QPLL1REFCLKLOST (QPLL1REFCLKLOST_out),
.QPLLDMONITOR0 (QPLLDMONITOR0_out),
.QPLLDMONITOR1 (QPLLDMONITOR1_out),
.REFCLKOUTMONITOR0 (REFCLKOUTMONITOR0_out),
.REFCLKOUTMONITOR1 (REFCLKOUTMONITOR1_out),
.RXRECCLK0_SEL (RXRECCLK0_SEL_out),
.RXRECCLK1_SEL (RXRECCLK1_SEL_out),
.SARCCLK (SARCCLK_out),
.SDM0FINALOUT (SDM0FINALOUT_out),
.SDM0TESTDATA (SDM0TESTDATA_out),
.SDM1FINALOUT (SDM1FINALOUT_out),
.SDM1TESTDATA (SDM1TESTDATA_out),
.BGBYPASSB (BGBYPASSB_in),
.BGMONITORENB (BGMONITORENB_in),
.BGPDB (BGPDB_in),
.BGRCALOVRD (BGRCALOVRD_in),
.BGRCALOVRDENB (BGRCALOVRDENB_in),
.DRPADDR (DRPADDR_in),
.DRPCLK (DRPCLK_in),
.DRPDI (DRPDI_in),
.DRPEN (DRPEN_in),
.DRPWE (DRPWE_in),
.GTGREFCLK0 (GTGREFCLK0_in),
.GTGREFCLK1 (GTGREFCLK1_in),
.GTNORTHREFCLK00 (GTNORTHREFCLK00_in),
.GTNORTHREFCLK01 (GTNORTHREFCLK01_in),
.GTNORTHREFCLK10 (GTNORTHREFCLK10_in),
.GTNORTHREFCLK11 (GTNORTHREFCLK11_in),
.GTREFCLK00 (GTREFCLK00_in),
.GTREFCLK01 (GTREFCLK01_in),
.GTREFCLK10 (GTREFCLK10_in),
.GTREFCLK11 (GTREFCLK11_in),
.GTSOUTHREFCLK00 (GTSOUTHREFCLK00_in),
.GTSOUTHREFCLK01 (GTSOUTHREFCLK01_in),
.GTSOUTHREFCLK10 (GTSOUTHREFCLK10_in),
.GTSOUTHREFCLK11 (GTSOUTHREFCLK11_in),
.PMARSVD0 (PMARSVD0_in),
.PMARSVD1 (PMARSVD1_in),
.PMASCANCLK (PMASCANCLK_in),
.PMASCANENB (PMASCANENB_in),
.PMASCANIN (PMASCANIN_in),
.QDPMASCANMODEB (QDPMASCANMODEB_in),
.QDPMASCANRSTEN (QDPMASCANRSTEN_in),
.QPLL0CLKRSVD0 (QPLL0CLKRSVD0_in),
.QPLL0LOCKDETCLK (QPLL0LOCKDETCLK_in),
.QPLL0LOCKEN (QPLL0LOCKEN_in),
.QPLL0PD (QPLL0PD_in),
.QPLL0REFCLKSEL (QPLL0REFCLKSEL_in),
.QPLL0RESET (QPLL0RESET_in),
.QPLL1CLKRSVD0 (QPLL1CLKRSVD0_in),
.QPLL1LOCKDETCLK (QPLL1LOCKDETCLK_in),
.QPLL1LOCKEN (QPLL1LOCKEN_in),
.QPLL1PD (QPLL1PD_in),
.QPLL1REFCLKSEL (QPLL1REFCLKSEL_in),
.QPLL1RESET (QPLL1RESET_in),
.QPLLRSVD1 (QPLLRSVD1_in),
.QPLLRSVD2 (QPLLRSVD2_in),
.QPLLRSVD3 (QPLLRSVD3_in),
.QPLLRSVD4 (QPLLRSVD4_in),
.RCALENB (RCALENB_in),
.RXRECCLK (RXRECCLK_in),
.SDM0DATA (SDM0DATA_in),
.SDM0RESET (SDM0RESET_in),
.SDM0WIDTH (SDM0WIDTH_in),
.SDM1DATA (SDM1DATA_in),
.SDM1RESET (SDM1RESET_in),
.SDM1WIDTH (SDM1WIDTH_in),
.GSR (glblGSR)
);
specify
(DRPCLK => DRPDO[0]) = (100:100:100, 100:100:100);
(DRPCLK => DRPDO[10]) = (100:100:100, 100:100:100);
(DRPCLK => DRPDO[11]) = (100:100:100, 100:100:100);
(DRPCLK => DRPDO[12]) = (100:100:100, 100:100:100);
(DRPCLK => DRPDO[13]) = (100:100:100, 100:100:100);
(DRPCLK => DRPDO[14]) = (100:100:100, 100:100:100);
(DRPCLK => DRPDO[15]) = (100:100:100, 100:100:100);
(DRPCLK => DRPDO[1]) = (100:100:100, 100:100:100);
(DRPCLK => DRPDO[2]) = (100:100:100, 100:100:100);
(DRPCLK => DRPDO[3]) = (100:100:100, 100:100:100);
(DRPCLK => DRPDO[4]) = (100:100:100, 100:100:100);
(DRPCLK => DRPDO[5]) = (100:100:100, 100:100:100);
(DRPCLK => DRPDO[6]) = (100:100:100, 100:100:100);
(DRPCLK => DRPDO[7]) = (100:100:100, 100:100:100);
(DRPCLK => DRPDO[8]) = (100:100:100, 100:100:100);
(DRPCLK => DRPDO[9]) = (100:100:100, 100:100:100);
(DRPCLK => DRPRDY) = (100:100:100, 100:100:100);
(DRPCLK => RXRECCLK0_SEL[0]) = (100:100:100, 100:100:100);
(DRPCLK => RXRECCLK0_SEL[1]) = (100:100:100, 100:100:100);
(GTGREFCLK0 => QPLL0OUTREFCLK) = (0:0:0, 0:0:0);
(GTGREFCLK1 => QPLL1OUTREFCLK) = (0:0:0, 0:0:0);
(GTNORTHREFCLK00 => QPLL0OUTREFCLK) = (0:0:0, 0:0:0);
(GTNORTHREFCLK01 => QPLL1OUTREFCLK) = (0:0:0, 0:0:0);
(GTNORTHREFCLK10 => QPLL0OUTREFCLK) = (0:0:0, 0:0:0);
(GTNORTHREFCLK11 => QPLL1OUTREFCLK) = (0:0:0, 0:0:0);
(GTREFCLK00 => QPLL0OUTREFCLK) = (0:0:0, 0:0:0);
(GTREFCLK01 => QPLL1OUTREFCLK) = (0:0:0, 0:0:0);
(GTREFCLK10 => QPLL0OUTREFCLK) = (0:0:0, 0:0:0);
(GTREFCLK11 => QPLL1OUTREFCLK) = (0:0:0, 0:0:0);
(GTSOUTHREFCLK00 => QPLL0OUTREFCLK) = (0:0:0, 0:0:0);
(GTSOUTHREFCLK01 => QPLL1OUTREFCLK) = (0:0:0, 0:0:0);
(GTSOUTHREFCLK10 => QPLL0OUTREFCLK) = (0:0:0, 0:0:0);
(GTSOUTHREFCLK11 => QPLL1OUTREFCLK) = (0:0:0, 0:0:0);
// (QPLL0OUTREFCLK => REFCLKOUTMONITOR0) = (0:0:0, 0:0:0); // error prop output to output
// (QPLL1OUTREFCLK => REFCLKOUTMONITOR1) = (0:0:0, 0:0:0); // error prop output to output
`ifdef XIL_TIMING
$period (negedge DRPCLK, 0:0:0, notifier);
$period (posedge DRPCLK, 0:0:0, notifier);
$setuphold (posedge DRPCLK, negedge DRPADDR[0], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[0]);
$setuphold (posedge DRPCLK, negedge DRPADDR[1], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[1]);
$setuphold (posedge DRPCLK, negedge DRPADDR[2], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[2]);
$setuphold (posedge DRPCLK, negedge DRPADDR[3], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[3]);
$setuphold (posedge DRPCLK, negedge DRPADDR[4], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[4]);
$setuphold (posedge DRPCLK, negedge DRPADDR[5], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[5]);
$setuphold (posedge DRPCLK, negedge DRPADDR[6], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[6]);
$setuphold (posedge DRPCLK, negedge DRPADDR[7], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[7]);
$setuphold (posedge DRPCLK, negedge DRPADDR[8], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[8]);
$setuphold (posedge DRPCLK, negedge DRPADDR[9], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[9]);
$setuphold (posedge DRPCLK, negedge DRPDI[0], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[0]);
$setuphold (posedge DRPCLK, negedge DRPDI[10], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[10]);
$setuphold (posedge DRPCLK, negedge DRPDI[11], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[11]);
$setuphold (posedge DRPCLK, negedge DRPDI[12], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[12]);
$setuphold (posedge DRPCLK, negedge DRPDI[13], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[13]);
$setuphold (posedge DRPCLK, negedge DRPDI[14], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[14]);
$setuphold (posedge DRPCLK, negedge DRPDI[15], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[15]);
$setuphold (posedge DRPCLK, negedge DRPDI[1], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[1]);
$setuphold (posedge DRPCLK, negedge DRPDI[2], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[2]);
$setuphold (posedge DRPCLK, negedge DRPDI[3], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[3]);
$setuphold (posedge DRPCLK, negedge DRPDI[4], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[4]);
$setuphold (posedge DRPCLK, negedge DRPDI[5], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[5]);
$setuphold (posedge DRPCLK, negedge DRPDI[6], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[6]);
$setuphold (posedge DRPCLK, negedge DRPDI[7], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[7]);
$setuphold (posedge DRPCLK, negedge DRPDI[8], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[8]);
$setuphold (posedge DRPCLK, negedge DRPDI[9], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[9]);
$setuphold (posedge DRPCLK, negedge DRPEN, 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPEN_delay);
$setuphold (posedge DRPCLK, negedge DRPWE, 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPWE_delay);
$setuphold (posedge DRPCLK, posedge DRPADDR[0], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[0]);
$setuphold (posedge DRPCLK, posedge DRPADDR[1], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[1]);
$setuphold (posedge DRPCLK, posedge DRPADDR[2], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[2]);
$setuphold (posedge DRPCLK, posedge DRPADDR[3], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[3]);
$setuphold (posedge DRPCLK, posedge DRPADDR[4], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[4]);
$setuphold (posedge DRPCLK, posedge DRPADDR[5], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[5]);
$setuphold (posedge DRPCLK, posedge DRPADDR[6], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[6]);
$setuphold (posedge DRPCLK, posedge DRPADDR[7], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[7]);
$setuphold (posedge DRPCLK, posedge DRPADDR[8], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[8]);
$setuphold (posedge DRPCLK, posedge DRPADDR[9], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[9]);
$setuphold (posedge DRPCLK, posedge DRPDI[0], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[0]);
$setuphold (posedge DRPCLK, posedge DRPDI[10], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[10]);
$setuphold (posedge DRPCLK, posedge DRPDI[11], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[11]);
$setuphold (posedge DRPCLK, posedge DRPDI[12], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[12]);
$setuphold (posedge DRPCLK, posedge DRPDI[13], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[13]);
$setuphold (posedge DRPCLK, posedge DRPDI[14], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[14]);
$setuphold (posedge DRPCLK, posedge DRPDI[15], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[15]);
$setuphold (posedge DRPCLK, posedge DRPDI[1], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[1]);
$setuphold (posedge DRPCLK, posedge DRPDI[2], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[2]);
$setuphold (posedge DRPCLK, posedge DRPDI[3], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[3]);
$setuphold (posedge DRPCLK, posedge DRPDI[4], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[4]);
$setuphold (posedge DRPCLK, posedge DRPDI[5], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[5]);
$setuphold (posedge DRPCLK, posedge DRPDI[6], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[6]);
$setuphold (posedge DRPCLK, posedge DRPDI[7], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[7]);
$setuphold (posedge DRPCLK, posedge DRPDI[8], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[8]);
$setuphold (posedge DRPCLK, posedge DRPDI[9], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[9]);
$setuphold (posedge DRPCLK, posedge DRPEN, 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPEN_delay);
$setuphold (posedge DRPCLK, posedge DRPWE, 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPWE_delay);
$width (negedge DRPCLK, 0:0:0, 0, notifier);
$width (posedge DRPCLK, 0:0:0, 0, notifier);
`endif
specparam PATHPULSE$ = 0;
endspecify
endmodule
|
module Gpio(clk, strobe, rw, reset, addr, data_i, data_o, gpio);
// four registers
// 0 : enable (1 for enable)
// 1 : read-write (1 for write)
// 2 : read state (1 for high)
// 3 : write state (1 for high)
parameter COUNT = 32;
localparam SIZE = 4;
input wire clk, strobe, rw, reset;
input wire[31:0] addr, data_i;
output reg [31:0] data_o;
inout wire[COUNT-1:0] gpio;
localparam EN = 0, RW = 1, RS = 2, WS = 3;
reg [COUNT-1:0] state[SIZE-1:0];
integer k;
initial for (k = 0; k < SIZE; k = k + 1) state[k] = 0;
genvar i;
generate for (i = 0; i < COUNT; i = i + 1)
assign gpio[i] = (state[EN][i] & state[RW][i]) ? state[WS][i] : 1'bz;
endgenerate
always @(posedge clk) begin
state[RS] <= state[EN] & ~state[RW] & gpio;
if (reset) begin
for (k = 0; k < SIZE; k = k + 1)
state[k] <= 0;
end else if (strobe) begin
if (rw)
state[addr] <= data_i[COUNT-1:0];
else
data_o <= {{32-COUNT{1'b0}},state[addr]};
end
end
endmodule
|
module clk_wiz_0
(clk_in1,
clk_out1,
clk_out2);
input clk_in1;
output clk_out1;
output clk_out2;
(* IBUF_LOW_PWR *) wire clk_in1;
wire clk_out1;
wire clk_out2;
clk_wiz_0clk_wiz_0_clk_wiz inst
(.clk_in1(clk_in1),
.clk_out1(clk_out1),
.clk_out2(clk_out2));
endmodule
|
module clk_wiz_0clk_wiz_0_clk_wiz
(clk_in1,
clk_out1,
clk_out2);
input clk_in1;
output clk_out1;
output clk_out2;
(* IBUF_LOW_PWR *) wire clk_in1;
wire clk_in1_clk_wiz_0;
wire clk_out1;
wire clk_out1_clk_wiz_0;
wire clk_out2;
wire clk_out2_clk_wiz_0;
wire clkfbout_buf_clk_wiz_0;
wire clkfbout_clk_wiz_0;
wire NLW_plle2_adv_inst_CLKOUT2_UNCONNECTED;
wire NLW_plle2_adv_inst_CLKOUT3_UNCONNECTED;
wire NLW_plle2_adv_inst_CLKOUT4_UNCONNECTED;
wire NLW_plle2_adv_inst_CLKOUT5_UNCONNECTED;
wire NLW_plle2_adv_inst_DRDY_UNCONNECTED;
wire NLW_plle2_adv_inst_LOCKED_UNCONNECTED;
wire [15:0]NLW_plle2_adv_inst_DO_UNCONNECTED;
(* BOX_TYPE = "PRIMITIVE" *)
BUFG clkf_buf
(.I(clkfbout_clk_wiz_0),
.O(clkfbout_buf_clk_wiz_0));
(* BOX_TYPE = "PRIMITIVE" *)
(* CAPACITANCE = "DONT_CARE" *)
(* IBUF_DELAY_VALUE = "0" *)
(* IFD_DELAY_VALUE = "AUTO" *)
IBUF #(
.IOSTANDARD("DEFAULT"))
clkin1_ibufg
(.I(clk_in1),
.O(clk_in1_clk_wiz_0));
(* BOX_TYPE = "PRIMITIVE" *)
BUFG clkout1_buf
(.I(clk_out1_clk_wiz_0),
.O(clk_out1));
(* BOX_TYPE = "PRIMITIVE" *)
BUFG clkout2_buf
(.I(clk_out2_clk_wiz_0),
.O(clk_out2));
(* BOX_TYPE = "PRIMITIVE" *)
PLLE2_ADV #(
.BANDWIDTH("OPTIMIZED"),
.CLKFBOUT_MULT(8),
.CLKFBOUT_PHASE(0.000000),
.CLKIN1_PERIOD(10.000000),
.CLKIN2_PERIOD(0.000000),
.CLKOUT0_DIVIDE(16),
.CLKOUT0_DUTY_CYCLE(0.500000),
.CLKOUT0_PHASE(0.000000),
.CLKOUT1_DIVIDE(32),
.CLKOUT1_DUTY_CYCLE(0.500000),
.CLKOUT1_PHASE(0.000000),
.CLKOUT2_DIVIDE(1),
.CLKOUT2_DUTY_CYCLE(0.500000),
.CLKOUT2_PHASE(0.000000),
.CLKOUT3_DIVIDE(1),
.CLKOUT3_DUTY_CYCLE(0.500000),
.CLKOUT3_PHASE(0.000000),
.CLKOUT4_DIVIDE(1),
.CLKOUT4_DUTY_CYCLE(0.500000),
.CLKOUT4_PHASE(0.000000),
.CLKOUT5_DIVIDE(1),
.CLKOUT5_DUTY_CYCLE(0.500000),
.CLKOUT5_PHASE(0.000000),
.COMPENSATION("ZHOLD"),
.DIVCLK_DIVIDE(1),
.IS_CLKINSEL_INVERTED(1'b0),
.IS_PWRDWN_INVERTED(1'b0),
.IS_RST_INVERTED(1'b0),
.REF_JITTER1(0.010000),
.REF_JITTER2(0.010000),
.STARTUP_WAIT("FALSE"))
plle2_adv_inst
(.CLKFBIN(clkfbout_buf_clk_wiz_0),
.CLKFBOUT(clkfbout_clk_wiz_0),
.CLKIN1(clk_in1_clk_wiz_0),
.CLKIN2(1'b0),
.CLKINSEL(1'b1),
.CLKOUT0(clk_out1_clk_wiz_0),
.CLKOUT1(clk_out2_clk_wiz_0),
.CLKOUT2(NLW_plle2_adv_inst_CLKOUT2_UNCONNECTED),
.CLKOUT3(NLW_plle2_adv_inst_CLKOUT3_UNCONNECTED),
.CLKOUT4(NLW_plle2_adv_inst_CLKOUT4_UNCONNECTED),
.CLKOUT5(NLW_plle2_adv_inst_CLKOUT5_UNCONNECTED),
.DADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DCLK(1'b0),
.DEN(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DO(NLW_plle2_adv_inst_DO_UNCONNECTED[15:0]),
.DRDY(NLW_plle2_adv_inst_DRDY_UNCONNECTED),
.DWE(1'b0),
.LOCKED(NLW_plle2_adv_inst_LOCKED_UNCONNECTED),
.PWRDWN(1'b0),
.RST(1'b0));
endmodule
|
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
|
module tlu_controller_fsm #(
parameter DIVISOR = 8,
parameter TLU_TRIGGER_MAX_CLOCK_CYCLES = 17,
parameter TIMESTAMP_N_OF_BIT = 32
) (
input wire RESET,
input wire TRIGGER_CLK,
output reg TRIGGER_DATA_WRITE,
output reg [31:0] TRIGGER_DATA,
output reg FIFO_PREEMPT_REQ,
input wire FIFO_ACKNOWLEDGE,
output reg [TIMESTAMP_N_OF_BIT-1:0] TIMESTAMP,
output reg [31:0] TIMESTAMP_DATA,
output reg [31:0] TLU_TRIGGER_NUMBER_DATA,
output reg [31:0] TRIGGER_COUNTER_DATA,
input wire [31:0] TRIGGER_COUNTER,
input wire CONF_EXT_TIMESTAMP,
input wire [TIMESTAMP_N_OF_BIT-1:0] EXT_TIMESTAMP,
input wire [1:0] TRIGGER_MODE,
input wire [7:0] TRIGGER_THRESHOLD,
input wire TRIGGER,
input wire TRIGGER_VETO,
input wire TRIGGER_ENABLE,
input wire TRIGGER_ACKNOWLEDGE,
output reg TRIGGER_ACCEPTED_FLAG,
input wire TIMESTAMP_RESET_FLAG,
input wire [7:0] TLU_TRIGGER_LOW_TIME_OUT,
// input wire [4:0] TLU_TRIGGER_CLOCK_CYCLES,
input wire [7:0] TLU_TRIGGER_DATA_DELAY,
input wire TLU_TRIGGER_DATA_MSB_FIRST,
input wire TLU_ENABLE_VETO,
input wire TLU_RESET_FLAG,
input wire [1:0] CONF_DATA_FORMAT,
output reg TLU_BUSY,
output reg TLU_CLOCK_ENABLE,
output reg TLU_ASSERT_VETO,
input wire [7:0] TLU_TRIGGER_HANDSHAKE_ACCEPT_WAIT_CYCLES,
input wire [7:0] TLU_HANDSHAKE_BUSY_VETO_WAIT_CYCLES,
output wire TLU_TRIGGER_LOW_TIMEOUT_ERROR_FLAG, // error flag
output wire TLU_TRIGGER_ACCEPT_ERROR_FLAG // error flag
);
//assign TRIGGER_DATA[31:0] = (WRITE_TIMESTAMP==1'b1) ? {1'b1, TIMESTAMP_DATA[30:0]} : ((TRIGGER_MODE==2'b11) ? {1'b1, TLU_TRIGGER_NUMBER_DATA[30:0]} : ({1'b1, TRIGGER_COUNTER_DATA[30:0]}));
always @(*)
begin
if(TRIGGER_MODE == 2'b11) // TLU trigger number
begin
if(CONF_DATA_FORMAT == 2'b01) // time stamp only
TRIGGER_DATA[31:0] = {1'b1, TIMESTAMP_DATA[30:0]};
else if(CONF_DATA_FORMAT == 2'b10) // combined
TRIGGER_DATA[31:0] = {1'b1, TIMESTAMP_DATA[14:0], TLU_TRIGGER_NUMBER_DATA[15:0]};
else
TRIGGER_DATA[31:0] = {1'b1, TLU_TRIGGER_NUMBER_DATA[30:0]};
end
else // internally generated trigger number
begin
if(CONF_DATA_FORMAT == 2'b01) // time stamp only
TRIGGER_DATA[31:0] = {1'b1, TIMESTAMP_DATA[30:0]};
else if(CONF_DATA_FORMAT == 2'b10) // combined
TRIGGER_DATA[31:0] = {1'b1, TIMESTAMP_DATA[14:0], TRIGGER_COUNTER_DATA[15:0]};
else
TRIGGER_DATA[31:0] = {1'b1, TRIGGER_COUNTER_DATA[30:0]};
end
end
// shift register, serial to parallel, length of TLU_TRIGGER_MAX_CLOCK_CYCLES
reg [((TLU_TRIGGER_MAX_CLOCK_CYCLES+1)*DIVISOR)-1:0] tlu_data_sr;
always @(posedge TRIGGER_CLK)
begin
if (RESET | TRIGGER_ACCEPTED_FLAG)
tlu_data_sr <= 0;
else
tlu_data_sr[((TLU_TRIGGER_MAX_CLOCK_CYCLES)*DIVISOR)-1:0] <= {tlu_data_sr[((TLU_TRIGGER_MAX_CLOCK_CYCLES)*DIVISOR)-2:0], TRIGGER};
end
// Trigger flag
reg TRIGGER_FF;
always @(posedge TRIGGER_CLK)
TRIGGER_FF <= TRIGGER;
wire TRIGGER_FLAG;
assign TRIGGER_FLAG = ~TRIGGER_FF & TRIGGER;
// Trigger enable flag
reg TRIGGER_ENABLE_FF;
always @(posedge TRIGGER_CLK)
TRIGGER_ENABLE_FF <= TRIGGER_ENABLE;
wire TRIGGER_ENABLE_FLAG;
assign TRIGGER_ENABLE_FLAG = ~TRIGGER_ENABLE_FF & TRIGGER_ENABLE;
// FSM
// workaround for TLU bug where short szintillator pulses lead to glitches on TLU trigger
reg TRIGGER_ACCEPT;
reg TLU_TRIGGER_HANDSHAKE_ACCEPT;
reg [7:0] counter_trigger_high;
// additional wait cycles for TLU veto after TLU handshake
reg [7:0] counter_tlu_handshake_veto;
// other
reg [7:0] counter_trigger_low_time_out;
integer counter_tlu_clock;
integer counter_sr_wait_cycles;
integer n; // for for-loop
reg TRIGGER_ACKNOWLEDGED, FIFO_ACKNOWLEDGED;
reg TLU_TRIGGER_LOW_TIMEOUT_ERROR;
reg TLU_TRIGGER_ACCEPT_ERROR;
reg TLU_TRIGGER_LOW_TIMEOUT_ERROR_FF;
always @(posedge TRIGGER_CLK)
TLU_TRIGGER_LOW_TIMEOUT_ERROR_FF <= TLU_TRIGGER_LOW_TIMEOUT_ERROR;
assign TLU_TRIGGER_LOW_TIMEOUT_ERROR_FLAG = ~TLU_TRIGGER_LOW_TIMEOUT_ERROR_FF & TLU_TRIGGER_LOW_TIMEOUT_ERROR;
reg TLU_TRIGGER_ACCEPT_ERROR_FF;
always @(posedge TRIGGER_CLK)
TLU_TRIGGER_ACCEPT_ERROR_FF <= TLU_TRIGGER_ACCEPT_ERROR;
assign TLU_TRIGGER_ACCEPT_ERROR_FLAG = ~TLU_TRIGGER_ACCEPT_ERROR_FF & TLU_TRIGGER_ACCEPT_ERROR;
// standard state encoding
reg [2:0] state;
reg [2:0] next;
localparam [2:0]
IDLE = 3'b000,
SEND_COMMAND = 3'b001,
SEND_COMMAND_WAIT_FOR_TRIGGER_LOW = 3'b010,
SEND_TLU_CLOCK = 3'b011,
WAIT_BEFORE_LATCH = 3'b100,
LATCH_DATA = 3'b101,
WAIT_FOR_TLU_DATA_SAVED_CMD_READY = 3'b110;
// sequential always block, non-blocking assignments
always @(posedge TRIGGER_CLK)
begin
if (RESET) state <= IDLE; // get D-FF for state
else state <= next;
end
// combinational always block, blocking assignments
always @(state or TRIGGER_ACKNOWLEDGE or TRIGGER_ACKNOWLEDGED or FIFO_ACKNOWLEDGE or FIFO_ACKNOWLEDGED or TRIGGER_ENABLE or TRIGGER_ENABLE_FLAG or TRIGGER_FLAG or TRIGGER or TRIGGER_MODE or TLU_TRIGGER_LOW_TIMEOUT_ERROR or counter_tlu_clock /*or TLU_TRIGGER_CLOCK_CYCLES*/ or counter_sr_wait_cycles or counter_trigger_high or counter_tlu_handshake_veto or counter_trigger_low_time_out or TLU_TRIGGER_DATA_DELAY or TRIGGER_VETO or TRIGGER_ACCEPT or TLU_TRIGGER_HANDSHAKE_ACCEPT or TRIGGER_THRESHOLD or TLU_TRIGGER_HANDSHAKE_ACCEPT_WAIT_CYCLES or TLU_TRIGGER_MAX_CLOCK_CYCLES or DIVISOR)
begin
case (state)
IDLE:
begin
if ((TRIGGER_MODE == 2'b00 || TRIGGER_MODE == 2'b01)
&& (TRIGGER_ACKNOWLEDGE == 1'b0)
&& (FIFO_ACKNOWLEDGE == 1'b0)
&& (TRIGGER_ENABLE == 1'b1)
&& (TRIGGER_VETO == 1'b0)
&& ((TRIGGER_FLAG == 1'b1 && TRIGGER_THRESHOLD == 0) // trigger threshold disabled
|| (TRIGGER_ACCEPT == 1'b1 && TRIGGER_THRESHOLD != 0) // trigger threshold enabled
)
)
next = SEND_COMMAND;
else if ((TRIGGER_MODE == 2'b10 || TRIGGER_MODE == 2'b11)
&& (TRIGGER_ACKNOWLEDGE == 1'b0)
&& (FIFO_ACKNOWLEDGE == 1'b0)
&& (TRIGGER_ENABLE == 1'b1)
&& ((TRIGGER == 1'b1 && TRIGGER_ENABLE_FLAG == 1'b1) // workaround TLU trigger high when FSM enabled
|| (TRIGGER_FLAG == 1'b1 && TLU_TRIGGER_HANDSHAKE_ACCEPT_WAIT_CYCLES == 0) // trigger accept counter disabled
|| (TLU_TRIGGER_HANDSHAKE_ACCEPT == 1'b1 && TLU_TRIGGER_HANDSHAKE_ACCEPT_WAIT_CYCLES != 0) // trigger accept counter enabled
)
)
next = SEND_COMMAND_WAIT_FOR_TRIGGER_LOW;
else
next = IDLE;
end
SEND_COMMAND:
begin
next = LATCH_DATA; // do not wait for trigger becoming low
end
SEND_COMMAND_WAIT_FOR_TRIGGER_LOW:
begin
if (TRIGGER_MODE == 2'b10 && (TRIGGER == 1'b0 || TLU_TRIGGER_LOW_TIMEOUT_ERROR == 1'b1))
next = LATCH_DATA; // wait for trigger low
else if (TRIGGER_MODE == 2'b11 && (TRIGGER == 1'b0 || TLU_TRIGGER_LOW_TIMEOUT_ERROR == 1'b1))
next = SEND_TLU_CLOCK; // wait for trigger low
else
next = SEND_COMMAND_WAIT_FOR_TRIGGER_LOW;
end
SEND_TLU_CLOCK:
begin
//if (TLU_TRIGGER_CLOCK_CYCLES == 5'b0) // send 32 clock cycles
if (counter_tlu_clock >= TLU_TRIGGER_MAX_CLOCK_CYCLES * DIVISOR)
next = WAIT_BEFORE_LATCH;
else
next = SEND_TLU_CLOCK;
/*
else
if (counter_tlu_clock == TLU_TRIGGER_CLOCK_CYCLES * DIVISOR)
next = WAIT_BEFORE_LATCH;
else
next = SEND_TLU_CLOCK;
*/
end
WAIT_BEFORE_LATCH:
begin
if (counter_sr_wait_cycles == TLU_TRIGGER_DATA_DELAY + 5) // wait at least 3 (2 + next state) clock cycles for sync of the signal
next = LATCH_DATA;
else
next = WAIT_BEFORE_LATCH;
end
LATCH_DATA:
begin
next = WAIT_FOR_TLU_DATA_SAVED_CMD_READY;
end
WAIT_FOR_TLU_DATA_SAVED_CMD_READY:
begin
if (TRIGGER_ACKNOWLEDGED == 1'b1 && FIFO_ACKNOWLEDGED == 1'b1)
next = IDLE;
else
next = WAIT_FOR_TLU_DATA_SAVED_CMD_READY;
end
// inferring FF
default:
begin
next = IDLE;
end
endcase
end
// sequential always block, non-blocking assignments, registered outputs
always @(posedge TRIGGER_CLK)
begin
if (RESET) // get D-FF
begin
FIFO_PREEMPT_REQ <= 1'b0;
TRIGGER_DATA_WRITE <= 1'b0;
TLU_TRIGGER_NUMBER_DATA <= 32'b0;
TIMESTAMP_DATA <= 32'b0;
TRIGGER_COUNTER_DATA <= 32'b0;
TLU_ASSERT_VETO <= 1'b0;
TLU_BUSY <= 1'b0;
TLU_CLOCK_ENABLE <= 1'b0;
counter_trigger_high <= 8'b0;
counter_tlu_handshake_veto <= TLU_HANDSHAKE_BUSY_VETO_WAIT_CYCLES;
TRIGGER_ACCEPT <= 1'b0;
TLU_TRIGGER_HANDSHAKE_ACCEPT <= 1'b0;
counter_trigger_low_time_out <= 8'b0;
counter_tlu_clock <= 0;
counter_sr_wait_cycles <= 0;
TLU_TRIGGER_LOW_TIMEOUT_ERROR <= 1'b0;
TLU_TRIGGER_ACCEPT_ERROR <= 1'b0;
TRIGGER_ACCEPTED_FLAG <= 1'b0;
TRIGGER_ACKNOWLEDGED <= 1'b0;
FIFO_ACKNOWLEDGED <= 1'b0;
end
else
begin
FIFO_PREEMPT_REQ <= 1'b0;
TRIGGER_DATA_WRITE <= 1'b0;
TLU_TRIGGER_NUMBER_DATA <= TLU_TRIGGER_NUMBER_DATA;
TIMESTAMP_DATA <= TIMESTAMP_DATA;
TRIGGER_COUNTER_DATA <= TRIGGER_COUNTER_DATA;
TLU_ASSERT_VETO <= 1'b0;
TLU_BUSY <= 1'b0;
TLU_CLOCK_ENABLE <= 1'b0;
counter_trigger_high <= 8'b0;
counter_tlu_handshake_veto <= TLU_HANDSHAKE_BUSY_VETO_WAIT_CYCLES;
TRIGGER_ACCEPT <= 1'b0;
TLU_TRIGGER_HANDSHAKE_ACCEPT <= 1'b0;
counter_trigger_low_time_out <= 8'b0;
counter_tlu_clock <= 0;
counter_sr_wait_cycles <= 0;
TLU_TRIGGER_LOW_TIMEOUT_ERROR <= 1'b0;
TLU_TRIGGER_ACCEPT_ERROR <= 1'b0;
TRIGGER_ACCEPTED_FLAG <= 1'b0;
TRIGGER_ACKNOWLEDGED <= TRIGGER_ACKNOWLEDGED;
FIFO_ACKNOWLEDGED <= FIFO_ACKNOWLEDGED;
case (next)
IDLE:
begin
if (TRIGGER_FLAG && TRIGGER_THRESHOLD != 0)
if (CONF_EXT_TIMESTAMP == 1'b1)
TIMESTAMP_DATA <= EXT_TIMESTAMP[31:0]; // timestamp from external source
else
TIMESTAMP_DATA <= TIMESTAMP[31:0];
if (TRIGGER_ENABLE == 1'b1
&& TRIGGER == 1'b1
&& (((TRIGGER_MODE == 2'b10 || TRIGGER_MODE == 2'b11) && (counter_trigger_high != 0 && TLU_TRIGGER_HANDSHAKE_ACCEPT_WAIT_CYCLES != 0))
|| ((TRIGGER_MODE == 2'b00 || TRIGGER_MODE == 2'b01) && (counter_trigger_high != 0 && TRIGGER_THRESHOLD != 0))
)
)
FIFO_PREEMPT_REQ <= 1'b1;
else
FIFO_PREEMPT_REQ <= 1'b0;
TRIGGER_DATA_WRITE <= 1'b0;
if ((TRIGGER_ENABLE == 1'b0 || (TRIGGER_ENABLE == 1'b1 && TRIGGER_VETO == 1'b1 && counter_tlu_handshake_veto == 0)) && TLU_ENABLE_VETO == 1'b1 && (TRIGGER_MODE == 2'b10 || TRIGGER_MODE == 2'b11))
TLU_ASSERT_VETO <= 1'b1; // assert only outside Trigger/Busy handshake
else
TLU_ASSERT_VETO <= 1'b0;
// if (TRIGGER_ENABLE == 1'b0)
// TLU_BUSY <= 1'b1; // FIXME: temporary fix for accepting first TLU trigger
// else
// TLU_BUSY <= 1'b0;
TLU_BUSY <= 1'b0;
TLU_CLOCK_ENABLE <= 1'b0;
if (TRIGGER_ENABLE == 1'b1 && counter_trigger_high != 8'b1111_1111 && ((counter_trigger_high > 0 && TRIGGER == 1'b1) || (counter_trigger_high == 0 && TRIGGER_FLAG == 1'b1)))
counter_trigger_high <= counter_trigger_high + 1;
else if (TRIGGER_ENABLE == 1'b1 && counter_trigger_high == 8'b1111_1111 && TRIGGER == 1'b1)
counter_trigger_high <= counter_trigger_high;
else
counter_trigger_high <= 8'b0;
if (TRIGGER_ENABLE == 1'b0)
counter_tlu_handshake_veto <= 8'b0;
else if (counter_tlu_handshake_veto == 8'b0)
counter_tlu_handshake_veto <= counter_tlu_handshake_veto;
else
counter_tlu_handshake_veto <= counter_tlu_handshake_veto - 1;
if (counter_trigger_high >= TRIGGER_THRESHOLD && TRIGGER_THRESHOLD != 0)
TRIGGER_ACCEPT <= 1'b1;
else
TRIGGER_ACCEPT <= 1'b0;
if (counter_trigger_high >= TLU_TRIGGER_HANDSHAKE_ACCEPT_WAIT_CYCLES && TLU_TRIGGER_HANDSHAKE_ACCEPT_WAIT_CYCLES != 0)
TLU_TRIGGER_HANDSHAKE_ACCEPT <= 1'b1;
else
TLU_TRIGGER_HANDSHAKE_ACCEPT <= 1'b0;
counter_tlu_clock <= 0;
counter_sr_wait_cycles <= 0;
TRIGGER_ACCEPTED_FLAG <= 1'b0;
TRIGGER_ACKNOWLEDGED <= 1'b0;
FIFO_ACKNOWLEDGED <= 1'b0;
end
SEND_COMMAND:
begin
// send flag at beginning of state
FIFO_PREEMPT_REQ <= 1'b1;
TRIGGER_DATA_WRITE <= 1'b0;
// get timestamp closest to the trigger
if (state != next && TRIGGER_THRESHOLD == 0) begin
if (CONF_EXT_TIMESTAMP == 1'b1)
TIMESTAMP_DATA <= EXT_TIMESTAMP[31:0]; // timestamp from external source
else
TIMESTAMP_DATA <= TIMESTAMP[31:0];
end
if (state != next) begin
TRIGGER_COUNTER_DATA <= TRIGGER_COUNTER;
end
TLU_BUSY <= 1'b1;
TLU_CLOCK_ENABLE <= 1'b0;
counter_tlu_clock <= 0;
counter_sr_wait_cycles <= 0;
// send flag at beginning of state
if (state != next)
TRIGGER_ACCEPTED_FLAG <= 1'b1;
if (TRIGGER_ACKNOWLEDGE == 1'b1)
TRIGGER_ACKNOWLEDGED <= 1'b1;
if (FIFO_ACKNOWLEDGE == 1'b1)
FIFO_ACKNOWLEDGED <= 1'b1;
end
SEND_COMMAND_WAIT_FOR_TRIGGER_LOW:
begin
// send flag at beginning of state
FIFO_PREEMPT_REQ <= 1'b1;
TRIGGER_DATA_WRITE <= 1'b0;
// get timestamp closest to the trigger
if (state != next && TRIGGER_THRESHOLD == 0) begin
if (CONF_EXT_TIMESTAMP == 1'b1)
TIMESTAMP_DATA <= EXT_TIMESTAMP[31:0]; // timestamp from external source
else
TIMESTAMP_DATA <= TIMESTAMP[31:0];
end
if (state != next) begin
TRIGGER_COUNTER_DATA <= TRIGGER_COUNTER;
end
TLU_BUSY <= 1'b1;
TLU_CLOCK_ENABLE <= 1'b0;
counter_trigger_low_time_out <= counter_trigger_low_time_out + 1;
counter_tlu_clock <= 0;
counter_sr_wait_cycles <= 0;
if ((counter_trigger_low_time_out >= TLU_TRIGGER_LOW_TIME_OUT) && (TLU_TRIGGER_LOW_TIME_OUT != 8'b0))
TLU_TRIGGER_LOW_TIMEOUT_ERROR <= 1'b1;
else
TLU_TRIGGER_LOW_TIMEOUT_ERROR <= 1'b0;
if (state != next)
TRIGGER_ACCEPTED_FLAG <= 1'b1;
else
TRIGGER_ACCEPTED_FLAG <= 1'b0;
if (TRIGGER_ACKNOWLEDGE == 1'b1)
TRIGGER_ACKNOWLEDGED <= 1'b1;
if (FIFO_ACKNOWLEDGE == 1'b1)
FIFO_ACKNOWLEDGED <= 1'b1;
end
SEND_TLU_CLOCK:
begin
FIFO_PREEMPT_REQ <= 1'b1;
TRIGGER_DATA_WRITE <= 1'b0;
TLU_BUSY <= 1'b1;
TLU_CLOCK_ENABLE <= 1'b1;
counter_tlu_clock <= counter_tlu_clock + 1;
counter_sr_wait_cycles <= 0;
TRIGGER_ACCEPTED_FLAG <= 1'b0;
if (TRIGGER_ACKNOWLEDGE == 1'b1)
TRIGGER_ACKNOWLEDGED <= 1'b1;
if (FIFO_ACKNOWLEDGE == 1'b1)
FIFO_ACKNOWLEDGED <= 1'b1;
if (state != next && TRIGGER == 1'b0 && counter_trigger_low_time_out < 4) // 4 clocks cycles = 1 for output + 3 for sync
TLU_TRIGGER_ACCEPT_ERROR <= 1'b1;
end
WAIT_BEFORE_LATCH:
begin
FIFO_PREEMPT_REQ <= 1'b1;
TRIGGER_DATA_WRITE <= 1'b0;
TLU_BUSY <= 1'b1;
TLU_CLOCK_ENABLE <= 1'b0;
counter_tlu_clock <= 0;
counter_sr_wait_cycles <= counter_sr_wait_cycles + 1;
TRIGGER_ACCEPTED_FLAG <= 1'b0;
if (TRIGGER_ACKNOWLEDGE == 1'b1)
TRIGGER_ACKNOWLEDGED <= 1'b1;
if (FIFO_ACKNOWLEDGE == 1'b1)
FIFO_ACKNOWLEDGED <= 1'b1;
end
LATCH_DATA:
begin
FIFO_PREEMPT_REQ <= 1'b1;
TRIGGER_DATA_WRITE <= 1'b1;
if (TLU_TRIGGER_DATA_MSB_FIRST == 1'b0) begin // reverse bit order
for ( n=0 ; n < TLU_TRIGGER_MAX_CLOCK_CYCLES ; n = n+1 ) begin
if (n > 31-1)
TLU_TRIGGER_NUMBER_DATA[n] <= 1'b0;
else
TLU_TRIGGER_NUMBER_DATA[n] <= tlu_data_sr[((TLU_TRIGGER_MAX_CLOCK_CYCLES-n)*DIVISOR)-1];
end
end
else begin // do not reverse
for ( n=0 ; n < TLU_TRIGGER_MAX_CLOCK_CYCLES ; n = n+1 ) begin
if (n > 31-1)
TLU_TRIGGER_NUMBER_DATA[n] <= 1'b0;
else
TLU_TRIGGER_NUMBER_DATA[n] <= tlu_data_sr[((n+2)*DIVISOR)-1];
end
end
/*
if (TLU_TRIGGER_CLOCK_CYCLES == 5'b0_0000) begin // 0 results in 32 clock cycles -> 31bit trigger number
if (TLU_TRIGGER_DATA_MSB_FIRST == 1'b0) begin // reverse bit order
for ( n=0 ; n < 32 ; n = n+1 ) begin
if (n > 31-1)
TLU_TRIGGER_NUMBER_DATA[n] <= 1'b0;
else
TLU_TRIGGER_NUMBER_DATA[n] <= tlu_data_sr[((32-n)*DIVISOR)-1];
end
end
else begin // do not reverse
for ( n=0 ; n < 32 ; n = n+1 ) begin
if (n > 31-1)
TLU_TRIGGER_NUMBER_DATA[n] <= 1'b0;
else
TLU_TRIGGER_NUMBER_DATA[n] <= tlu_data_sr[((n+2)*DIVISOR)-1];
end
end
end
else begin // specific number of clock cycles
if (TLU_TRIGGER_DATA_MSB_FIRST == 1'b0) begin // reverse bit order
for ( n=31 ; n >= 0 ; n = n-1 ) begin
if (n + 1 > TLU_TRIGGER_CLOCK_CYCLES - 1)
TLU_TRIGGER_NUMBER_DATA[n] = 1'b0;
else if (n + 1 == TLU_TRIGGER_CLOCK_CYCLES - 1) begin
for ( i=0 ; i < 32 ; i = i+1 ) begin
if (i < TLU_TRIGGER_CLOCK_CYCLES-1)
TLU_TRIGGER_NUMBER_DATA[n-i] = tlu_data_sr[((i+2)*DIVISOR)-1];
end
end
end
end
else begin // do not reverse
for ( n=0 ; n < 32 ; n = n+1 ) begin
if (n + 1 > TLU_TRIGGER_CLOCK_CYCLES - 1)
TLU_TRIGGER_NUMBER_DATA[n] <= 1'b0;
else
TLU_TRIGGER_NUMBER_DATA[n] <= tlu_data_sr[((n+2)*DIVISOR)-1];
end
end
end
*/
TLU_BUSY <= 1'b1;
TLU_CLOCK_ENABLE <= 1'b0;
counter_tlu_clock <= 0;
counter_sr_wait_cycles <= 0;
TRIGGER_ACCEPTED_FLAG <= 1'b0;
if (TRIGGER_ACKNOWLEDGE == 1'b1)
TRIGGER_ACKNOWLEDGED <= 1'b1;
if (FIFO_ACKNOWLEDGE == 1'b1)
FIFO_ACKNOWLEDGED <= 1'b1;
if (state != next && TRIGGER == 1'b0 && counter_trigger_low_time_out < 4 && TRIGGER_MODE == 2'b10) // 4 clocks cycles = 1 for output + 3 for sync
TLU_TRIGGER_ACCEPT_ERROR <= 1'b1;
end
WAIT_FOR_TLU_DATA_SAVED_CMD_READY:
begin
//if ()
// FIFO_PREEMPT_REQ <= 1'b0;
//else
// FIFO_PREEMPT_REQ <= FIFO_PREEMPT_REQ;
FIFO_PREEMPT_REQ <= 1'b1;
TRIGGER_DATA_WRITE <= 1'b0;
// de-assert TLU busy as soon as possible
//if (TRIGGER_ACKNOWLEDGED == 1'b1 && FIFO_ACKNOWLEDGED == 1'b1)
// TLU_BUSY <= 1'b0;
//else
TLU_BUSY <= TLU_BUSY;
TLU_CLOCK_ENABLE <= 1'b0;
counter_tlu_clock <= 0;
counter_sr_wait_cycles <= 0;
TRIGGER_ACCEPTED_FLAG <= 1'b0;
if (TRIGGER_ACKNOWLEDGE == 1'b1)
TRIGGER_ACKNOWLEDGED <= 1'b1;
if (FIFO_ACKNOWLEDGE == 1'b1)
FIFO_ACKNOWLEDGED <= 1'b1;
end
endcase
end
end
// time stamp
always @(posedge TRIGGER_CLK)
begin
if (RESET || (TLU_RESET_FLAG && (TRIGGER_MODE == 2'b10 || TRIGGER_MODE == 2'b11)) || TIMESTAMP_RESET_FLAG)
TIMESTAMP <= 0;
else
TIMESTAMP <= TIMESTAMP + 1;
end
// Chipscope
`ifdef SYNTHESIS_NOT
//`ifdef SYNTHESIS
wire [35:0] control_bus;
chipscope_icon ichipscope_icon
(
.CONTROL0(control_bus)
);
chipscope_ila ichipscope_ila
(
.CONTROL(control_bus),
.TRIGGER_CLK(TRIGGER_CLK),
.TRIG0({TRIGGER_ENABLE, TRIGGER_DATA_WRITE, TRIGGER_ACCEPTED_FLAG, TLU_CLOCK_ENABLE, TLU_ASSERT_VETO, TLU_BUSY, TRIGGER_ACKNOWLEDGE, TRIGGER_VETO, TLU_TRIGGER_ACCEPT_ERROR, TLU_TRIGGER_LOW_TIMEOUT_ERROR, TRIGGER_FLAG, TRIGGER, TRIGGER_MODE, state})
//.TRIGGER_CLK(CLK_160),
//.TRIG0({FMODE, FSTROBE, FREAD, CMD_BUS_WR, RX_BUS_WR, FIFO_WR, BUS_DATA_IN, FE_RX ,WR_B, RD_B})
);
`endif
endmodule
|
module sky130_fd_sc_lp__a22oi (
Y ,
A1 ,
A2 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire nand0_out ;
wire nand1_out ;
wire and0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
nand nand0 (nand0_out , A2, A1 );
nand nand1 (nand1_out , B2, B1 );
and and0 (and0_out_Y , nand0_out, nand1_out );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, and0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
|
module MPUC1307 ( CLK,DS ,ED, MPYJ,DR,DI ,DOR ,DOI );
parameter total_bits = 32;
input CLK ;
wire CLK ;
input DS ;
wire DS ;
input ED; //data strobe
input MPYJ ; //the result is multiplied by -j
wire MPYJ ;
input [total_bits-1:0] DR ;
wire signed [total_bits-1:0] DR ;
input [total_bits-1:0] DI ;
wire signed [total_bits-1:0] DI ;
output [total_bits:0] DOR ;
reg [total_bits:0] DOR ;
output [total_bits:0] DOI ;
reg [total_bits:0] DOI ;
reg signed [total_bits+2 :0] dx5;
reg signed [total_bits-1 :0] dx7;
reg signed [total_bits-1 :0] dii;
reg signed [total_bits : 0] dt;
wire signed [total_bits+3 : 0] dx5p;
wire signed [total_bits+3 : 0] dot;
reg edd,edd2, edd3; //delayed data enable impulse
reg mpyjd,mpyjd2,mpyjd3;
reg [total_bits:0] doo ;
reg [total_bits:0] droo ;
always @(posedge CLK)
begin
if (ED) begin
edd<=DS;
edd2<=edd;
edd3<=edd2;
mpyjd<=MPYJ;
mpyjd2<=mpyjd;
mpyjd3<=mpyjd2; //1_0100_1110_0111_1011
if (DS) begin // 1_0101_00T0_1000_0T0T
dx5<=DR+(DR <<2); //multiply by 5
dx7<=DR-(DR>>>3); //multiply by 7, shifted right to 2
dt<=DR;
dii<=DI;
end
else begin
dx5<=dii+(dii <<2); //multiply by 5
dx7<=dii-(dii>>>3); //multiply by 7, shifted right to 3
dt<=dii;
end
doo<=dot >>>3;
droo<=doo;
if (edd3)
if (mpyjd3) begin
DOR<=doo;
DOI<= - droo; end
else begin
DOR<=droo;
DOI<= doo; end
end
end
assign dx5p=(dx5<<1)+(dx7>>>1); // multiply by 1_0101_00T
assign dot= (dx5p+(dt>>>6) -(dx5>>>13));// multiply by 1_0101_00T0_1000_0T0T
endmodule
|
module merlin_pfu
#(
parameter C_FIFO_PASSTHROUGH = 0,
parameter C_FIFO_DEPTH_X = 2, // depth >= read latency + 2
parameter C_WORD_RESET_VECTOR = { `RV_XLEN-2 {1'b0} }
)
(
// global
input wire clk_i,
input wire reset_i,
// instruction cache interface
input wire ireqready_i,
output wire ireqvalid_o,
output wire [1:0] ireqhpl_o,
output wire [`RV_XLEN-1:0] ireqaddr_o, // TODO - consider bypassing the pc on a jump
output wire irspready_o,
input wire irspvalid_i,
input wire irsprerr_i,
input wire [`RV_XLEN-1:0] irspdata_i,
// decoder interface
output wire ids_dav_o, // new fetch available
input wire ids_ack_i, // ack this fetch
input wire [1:0] ids_ack_size_i, // size of this ack TODO
output wire [`RV_SOFID_RANGE] ids_sofid_o, // first fetch since vectoring
output wire [31:0] ids_ins_o, // instruction fetched
output wire ids_ferr_o, // this instruction fetch resulted in error
output wire [`RV_XLEN-1:0] ids_pc_o, // address of this instruction
// ex stage vectoring interface
input wire exs_pc_wr_i,
input wire [`RV_XLEN-1:0] exs_pc_din_i,
// pfu stage interface
input wire [1:0] exs_hpl_i
);
//--------------------------------------------------------------
// interface assignments
// ibus debt
reg ibus_debt;
wire request;
wire response;
// fifo level counter
reg [C_FIFO_DEPTH_X:0] fifo_level_q;
reg fifo_accepting;
// program counter
reg [`RV_XLEN-1:0] pc_q;
reg [`RV_XLEN-1:0] request_addr_q;
// vectoring flag register
reg vectoring_q;
// sofid register
reg [`RV_SOFID_RANGE] sofid_q;
// fifo
parameter C_SOFID_SZ = `RV_SOFID_SZ;
parameter C_FIFO_WIDTH = C_SOFID_SZ + 1 + `RV_XLEN + `RV_XLEN;
//
parameter C_SOFID_LSB = 1 + 2 * `RV_XLEN;
parameter C_FERR_LSB = 2 * `RV_XLEN;
parameter C_FIFO_PC_LSB = `RV_XLEN;
parameter C_FIFO_INS_LSB = 0;
//
wire fifo_empty;
wire [C_FIFO_WIDTH-1:0] fifo_din;
wire [C_FIFO_WIDTH-1:0] fifo_dout;
wire [`RV_XLEN-1:0] fifo_dout_data;
//--------------------------------------------------------------
//--------------------------------------------------------------
// interface assignments
//--------------------------------------------------------------
assign ireqhpl_o = exs_hpl_i;
assign ireqvalid_o = fifo_accepting & ~exs_pc_wr_i & (~ibus_debt | response);
assign ireqaddr_o = { pc_q[`RV_XLEN-1:`RV_XLEN_X-3], { `RV_XLEN_X-3 {1'b0} } };
assign irspready_o = 1'b1; //irspvalid_i; // always ready
//
assign ids_dav_o = ~fifo_empty;
assign ids_ins_o = fifo_dout_data[31:0];
//--------------------------------------------------------------
// ibus debt
//--------------------------------------------------------------
assign request = ireqvalid_o & ireqready_i;
assign response = irspvalid_i & irspready_o;
//
always @ `RV_SYNC_LOGIC_CLOCK_RESET(clk_i, reset_i) begin
if (reset_i) begin
ibus_debt <= 1'b0;
end else begin
if (request & ~response) begin
ibus_debt <= 1'b1;
end else if (~request & response) begin
ibus_debt <= 1'b0;
end
end
end
//--------------------------------------------------------------
// fifo level counter
//--------------------------------------------------------------
always @ `RV_SYNC_LOGIC_CLOCK_RESET(clk_i, reset_i) begin
if (reset_i) begin
fifo_level_q <= { 1'b1, { C_FIFO_DEPTH_X {1'b0} } };
end else begin
//*
if (exs_pc_wr_i) begin
fifo_level_q <= { 1'b1, { C_FIFO_DEPTH_X {1'b0} } };
end else
/**/
if (request & ~ids_ack_i) begin
fifo_level_q <= fifo_level_q - { { C_FIFO_DEPTH_X {1'b0} }, 1'b1 };
end else if (~request & ids_ack_i) begin
fifo_level_q <= fifo_level_q + { { C_FIFO_DEPTH_X {1'b0} }, 1'b1 };
end
end
end
always @ (*) begin
if (|fifo_level_q) begin
fifo_accepting = 1'b1;
end else begin
fifo_accepting = 1'b0;
end
end
//--------------------------------------------------------------
// program counter
//--------------------------------------------------------------
always @ `RV_SYNC_LOGIC_CLOCK_RESET(clk_i, reset_i) begin
if (reset_i) begin
pc_q <= { C_WORD_RESET_VECTOR, 2'b0 };
end else begin
if (exs_pc_wr_i) begin
pc_q <= exs_pc_din_i;
end else if (request) begin
pc_q <= pc_q + { { `RV_XLEN-(`RV_XLEN_X-2) {1'b0} }, 1'b1, { `RV_XLEN_X-3 {1'b0} } };
end
end
end
always @ `RV_SYNC_LOGIC_CLOCK(clk_i) begin
if (request) begin
request_addr_q <= pc_q;
end
end
//--------------------------------------------------------------
// vectoring flag register
//--------------------------------------------------------------
always @ `RV_SYNC_LOGIC_CLOCK_RESET(clk_i, reset_i) begin
if (reset_i) begin
vectoring_q <= 1'b0;
end else begin
if (exs_pc_wr_i) begin
vectoring_q <= 1'b1;
end else if (request) begin
vectoring_q <= 1'b0;
end
end
end
//--------------------------------------------------------------
// sofid register
//--------------------------------------------------------------
always @ `RV_SYNC_LOGIC_CLOCK_RESET(clk_i, reset_i) begin
if (reset_i) begin
sofid_q <= `RV_SOFID_RUN;
end else begin
if (vectoring_q & request) begin
sofid_q <= `RV_SOFID_JUMP;
end else if (response) begin
sofid_q <= `RV_SOFID_RUN;
end
end
end
//--------------------------------------------------------------
// fifo
//--------------------------------------------------------------
assign fifo_din[ C_SOFID_LSB +: C_SOFID_SZ] = sofid_q; // TODO
assign fifo_din[ C_FERR_LSB +: 1] = irsprerr_i;
assign fifo_din[ C_FIFO_PC_LSB +: `RV_XLEN] = request_addr_q;
assign fifo_din[C_FIFO_INS_LSB +: `RV_XLEN] = irspdata_i;
//
assign ids_sofid_o = fifo_dout[ C_SOFID_LSB +: C_SOFID_SZ];
assign ids_ferr_o = fifo_dout[ C_FERR_LSB +: 1];
assign ids_pc_o = fifo_dout[ C_FIFO_PC_LSB +: `RV_XLEN];
assign fifo_dout_data = fifo_dout[C_FIFO_INS_LSB +: `RV_XLEN];
//
merlin_fifo
#(
.C_FIFO_PASSTHROUGH (C_FIFO_PASSTHROUGH),
.C_FIFO_WIDTH (C_FIFO_WIDTH),
.C_FIFO_DEPTH_X (C_FIFO_DEPTH_X)
) i_merlin_fifo (
// global
.clk_i (clk_i),
.reset_i (reset_i),
// control and status
.flush_i (exs_pc_wr_i | vectoring_q),
.empty_o (fifo_empty),
.full_o (),
// write port
.wr_i (response),
.din_i (fifo_din),
// read port
.rd_i (ids_ack_i),
.dout_o (fifo_dout)
);
endmodule
|
module CvtColor_1 (
ap_clk,
ap_rst,
ap_start,
ap_done,
ap_continue,
ap_idle,
ap_ready,
p_src_rows_V_dout,
p_src_rows_V_empty_n,
p_src_rows_V_read,
p_src_cols_V_dout,
p_src_cols_V_empty_n,
p_src_cols_V_read,
p_src_data_stream_0_V_dout,
p_src_data_stream_0_V_empty_n,
p_src_data_stream_0_V_read,
p_src_data_stream_1_V_dout,
p_src_data_stream_1_V_empty_n,
p_src_data_stream_1_V_read,
p_src_data_stream_2_V_dout,
p_src_data_stream_2_V_empty_n,
p_src_data_stream_2_V_read,
p_dst_data_stream_0_V_din,
p_dst_data_stream_0_V_full_n,
p_dst_data_stream_0_V_write,
p_dst_data_stream_1_V_din,
p_dst_data_stream_1_V_full_n,
p_dst_data_stream_1_V_write,
p_dst_data_stream_2_V_din,
p_dst_data_stream_2_V_full_n,
p_dst_data_stream_2_V_write
);
parameter ap_ST_fsm_state1 = 4'd1;
parameter ap_ST_fsm_state2 = 4'd2;
parameter ap_ST_fsm_pp0_stage0 = 4'd4;
parameter ap_ST_fsm_state14 = 4'd8;
input ap_clk;
input ap_rst;
input ap_start;
output ap_done;
input ap_continue;
output ap_idle;
output ap_ready;
input [15:0] p_src_rows_V_dout;
input p_src_rows_V_empty_n;
output p_src_rows_V_read;
input [15:0] p_src_cols_V_dout;
input p_src_cols_V_empty_n;
output p_src_cols_V_read;
input [7:0] p_src_data_stream_0_V_dout;
input p_src_data_stream_0_V_empty_n;
output p_src_data_stream_0_V_read;
input [7:0] p_src_data_stream_1_V_dout;
input p_src_data_stream_1_V_empty_n;
output p_src_data_stream_1_V_read;
input [7:0] p_src_data_stream_2_V_dout;
input p_src_data_stream_2_V_empty_n;
output p_src_data_stream_2_V_read;
output [7:0] p_dst_data_stream_0_V_din;
input p_dst_data_stream_0_V_full_n;
output p_dst_data_stream_0_V_write;
output [7:0] p_dst_data_stream_1_V_din;
input p_dst_data_stream_1_V_full_n;
output p_dst_data_stream_1_V_write;
output [7:0] p_dst_data_stream_2_V_din;
input p_dst_data_stream_2_V_full_n;
output p_dst_data_stream_2_V_write;
reg ap_done;
reg ap_idle;
reg ap_ready;
reg p_src_rows_V_read;
reg p_src_cols_V_read;
reg p_src_data_stream_0_V_read;
reg p_src_data_stream_1_V_read;
reg p_src_data_stream_2_V_read;
reg p_dst_data_stream_0_V_write;
reg p_dst_data_stream_1_V_write;
reg p_dst_data_stream_2_V_write;
reg ap_done_reg;
(* fsm_encoding = "none" *) reg [3:0] ap_CS_fsm;
wire ap_CS_fsm_state1;
wire [2:0] sector_data_0_address0;
reg sector_data_0_ce0;
wire [1:0] sector_data_0_q0;
wire [2:0] sector_data_1_address0;
reg sector_data_1_ce0;
wire [1:0] sector_data_1_q0;
wire [2:0] sector_data_2_address0;
reg sector_data_2_ce0;
wire [1:0] sector_data_2_q0;
reg p_src_rows_V_blk_n;
reg p_src_cols_V_blk_n;
reg p_src_data_stream_0_V_blk_n;
wire ap_CS_fsm_pp0_stage0;
reg ap_enable_reg_pp0_iter1;
wire ap_block_pp0_stage0;
reg [0:0] tmp_53_i_reg_783;
reg p_src_data_stream_1_V_blk_n;
reg p_src_data_stream_2_V_blk_n;
reg p_dst_data_stream_0_V_blk_n;
reg ap_enable_reg_pp0_iter10;
reg [0:0] ap_reg_pp0_iter9_tmp_53_i_reg_783;
reg p_dst_data_stream_1_V_blk_n;
reg p_dst_data_stream_2_V_blk_n;
reg [10:0] j_i_reg_226;
reg [15:0] p_src_cols_V_read_reg_764;
reg ap_block_state1;
reg [15:0] p_src_rows_V_read_reg_769;
wire [0:0] tmp_i_fu_241_p2;
wire ap_CS_fsm_state2;
wire [10:0] i_fu_246_p2;
reg [10:0] i_reg_778;
wire [0:0] tmp_53_i_fu_256_p2;
wire ap_block_state3_pp0_stage0_iter0;
reg ap_block_state4_pp0_stage0_iter1;
wire ap_block_state5_pp0_stage0_iter2;
wire ap_block_state6_pp0_stage0_iter3;
wire ap_block_state7_pp0_stage0_iter4;
wire ap_block_state8_pp0_stage0_iter5;
wire ap_block_state9_pp0_stage0_iter6;
wire ap_block_state10_pp0_stage0_iter7;
wire ap_block_state11_pp0_stage0_iter8;
wire ap_block_state12_pp0_stage0_iter9;
reg ap_block_state13_pp0_stage0_iter10;
reg ap_block_pp0_stage0_11001;
reg [0:0] ap_reg_pp0_iter1_tmp_53_i_reg_783;
reg [0:0] ap_reg_pp0_iter2_tmp_53_i_reg_783;
reg [0:0] ap_reg_pp0_iter3_tmp_53_i_reg_783;
reg [0:0] ap_reg_pp0_iter4_tmp_53_i_reg_783;
reg [0:0] ap_reg_pp0_iter5_tmp_53_i_reg_783;
reg [0:0] ap_reg_pp0_iter6_tmp_53_i_reg_783;
reg [0:0] ap_reg_pp0_iter7_tmp_53_i_reg_783;
reg [0:0] ap_reg_pp0_iter8_tmp_53_i_reg_783;
wire [10:0] j_fu_261_p2;
reg ap_enable_reg_pp0_iter0;
reg [7:0] tmp_26_reg_792;
reg [7:0] ap_reg_pp0_iter2_tmp_26_reg_792;
reg [7:0] tmp_27_reg_797;
reg [7:0] ap_reg_pp0_iter2_tmp_27_reg_797;
reg [7:0] ap_reg_pp0_iter3_tmp_27_reg_797;
reg [7:0] tmp_28_reg_804;
reg [7:0] ap_reg_pp0_iter2_tmp_28_reg_804;
reg [0:0] tmp_reg_811;
reg [0:0] ap_reg_pp0_iter2_tmp_reg_811;
wire [6:0] tmp_10_fu_275_p1;
reg [6:0] tmp_10_reg_816;
reg [6:0] ap_reg_pp0_iter2_tmp_10_reg_816;
wire [26:0] p_Val2_i_fu_752_p2;
reg [26:0] p_Val2_i_reg_821;
wire [23:0] r_V_3_fu_758_p2;
reg [23:0] r_V_3_reg_827;
wire [27:0] tab_0_V_fu_346_p3;
reg [27:0] tab_0_V_reg_833;
reg [27:0] ap_reg_pp0_iter4_tab_0_V_reg_833;
reg [27:0] ap_reg_pp0_iter5_tab_0_V_reg_833;
reg [27:0] ap_reg_pp0_iter6_tab_0_V_reg_833;
reg [27:0] ap_reg_pp0_iter7_tab_0_V_reg_833;
reg [27:0] ap_reg_pp0_iter8_tab_0_V_reg_833;
wire [4:0] tmp_s_fu_356_p4;
reg [4:0] tmp_s_reg_843;
reg [4:0] ap_reg_pp0_iter5_tmp_s_reg_843;
wire [24:0] f_V_fu_377_p2;
reg [24:0] f_V_reg_850;
wire [27:0] tab_1_V_fu_390_p2;
reg [27:0] tab_1_V_reg_855;
reg [27:0] ap_reg_pp0_iter5_tab_1_V_reg_855;
reg [27:0] ap_reg_pp0_iter6_tab_1_V_reg_855;
reg [27:0] ap_reg_pp0_iter7_tab_1_V_reg_855;
reg [27:0] ap_reg_pp0_iter8_tab_1_V_reg_855;
wire [28:0] r_V_fu_402_p2;
reg signed [28:0] r_V_reg_863;
wire [4:0] h_i_1_fu_434_p3;
reg [4:0] h_i_1_reg_878;
wire [46:0] grp_fu_418_p2;
reg [46:0] p_Val2_4_i_reg_883;
reg [27:0] tab_2_V_reg_904;
reg [27:0] tab_3_V_reg_911;
reg [1:0] sector_data_0_load_reg_918;
reg [1:0] sector_data_1_load_reg_923;
reg [1:0] sector_data_2_load_reg_928;
wire [7:0] p_Val2_20_fu_570_p3;
reg [7:0] p_Val2_20_reg_933;
wire [7:0] p_Val2_21_fu_657_p3;
reg [7:0] p_Val2_21_reg_938;
wire [7:0] p_Val2_22_fu_744_p3;
reg [7:0] p_Val2_22_reg_943;
reg ap_block_pp0_stage0_subdone;
reg ap_condition_pp0_exit_iter0_state3;
reg ap_enable_reg_pp0_iter2;
reg ap_enable_reg_pp0_iter3;
reg ap_enable_reg_pp0_iter4;
reg ap_enable_reg_pp0_iter5;
reg ap_enable_reg_pp0_iter6;
reg ap_enable_reg_pp0_iter7;
reg ap_enable_reg_pp0_iter8;
reg ap_enable_reg_pp0_iter9;
reg [10:0] i_i_reg_215;
wire ap_CS_fsm_state14;
wire [63:0] tmp_79_i_fu_441_p1;
reg ap_block_pp0_stage0_01001;
wire [15:0] i_cast_i_cast_fu_237_p1;
wire [15:0] j_cast_i_cast_fu_252_p1;
wire [18:0] r_V_4_fu_279_p4;
wire [8:0] tmp_62_i_fu_303_p1;
wire [8:0] tmp_61_i_fu_300_p1;
wire [8:0] tmp_63_i_fu_306_p2;
wire [27:0] tmp_65_i_fu_312_p3;
wire [27:0] p_Val2_cast_i_fu_297_p1;
wire [25:0] tmp_66_i_fu_326_p3;
wire [26:0] tmp_66_cast_i_fu_333_p1;
(* use_dsp48 = "no" *) wire [26:0] p_Val2_2_i_fu_337_p2;
wire [27:0] p_Val2_1_i_fu_320_p2;
wire [27:0] p_Val2_2_cast_i_fu_342_p1;
wire [23:0] tmp_55_i_fu_365_p3;
wire [24:0] r_V_10_cast1_i_cast_fu_353_p1;
wire [24:0] tmp_55_cast_i_cast_fu_373_p1;
wire [27:0] tmp_67_i_fu_383_p3;
wire [28:0] tmp_68_i_fu_395_p1;
wire [28:0] tmp_69_i_fu_398_p1;
wire signed [27:0] f_V_cast_fu_408_p1;
wire [27:0] grp_fu_418_p1;
wire [0:0] tmp_58_i_fu_424_p2;
wire [4:0] h_i_fu_429_p2;
wire [46:0] tmp_71_i_fu_447_p3;
wire [46:0] p_Val2_5_fu_454_p2;
wire [46:0] tmp_76_i_fu_469_p3;
wire [46:0] p_Val2_6_fu_476_p2;
wire [27:0] p_Val2_7_fu_491_p6;
wire [0:0] tmp_11_fu_510_p3;
wire [7:0] p_Val2_8_fu_500_p4;
wire [7:0] tmp_i_i_i_fu_518_p1;
wire [7:0] p_Val2_9_fu_530_p2;
wire [0:0] tmp_13_fu_536_p3;
wire [0:0] tmp_12_fu_522_p3;
wire [0:0] tmp_14_i_i_i_fu_544_p2;
wire [0:0] carry_fu_550_p2;
wire [0:0] lD_fu_556_p3;
wire [0:0] Range1_all_ones_fu_564_p2;
wire [27:0] p_Val2_11_fu_578_p6;
wire [0:0] tmp_15_fu_597_p3;
wire [7:0] p_Val2_12_fu_587_p4;
wire [7:0] tmp_i_i109_i_fu_605_p1;
wire [7:0] p_Val2_13_fu_617_p2;
wire [0:0] tmp_17_fu_623_p3;
wire [0:0] tmp_16_fu_609_p3;
wire [0:0] tmp_14_i_i113_i_fu_631_p2;
wire [0:0] carry_1_fu_637_p2;
wire [0:0] lD_1_fu_643_p3;
wire [0:0] Range1_all_ones_6_fu_651_p2;
wire [27:0] p_Val2_s_fu_665_p6;
wire [0:0] tmp_19_fu_684_p3;
wire [7:0] p_Val2_17_fu_674_p4;
wire [7:0] tmp_i_i122_i_fu_692_p1;
wire [7:0] p_Val2_18_fu_704_p2;
wire [0:0] tmp_21_fu_710_p3;
wire [0:0] tmp_20_fu_696_p3;
wire [0:0] tmp_14_i_i126_i_fu_718_p2;
wire [0:0] carry_2_fu_724_p2;
wire [0:0] lD_2_fu_730_p3;
wire [0:0] Range1_all_ones_7_fu_738_p2;
wire [18:0] p_Val2_i_fu_752_p0;
wire [7:0] p_Val2_i_fu_752_p1;
wire [15:0] r_V_3_fu_758_p0;
wire [7:0] r_V_3_fu_758_p1;
reg grp_fu_418_ce;
reg [3:0] ap_NS_fsm;
reg ap_idle_pp0;
wire ap_enable_pp0;
wire [46:0] grp_fu_418_p10;
wire [26:0] p_Val2_i_fu_752_p00;
wire [26:0] p_Val2_i_fu_752_p10;
wire [23:0] r_V_3_fu_758_p10;
// power-on initialization
initial begin
#0 ap_done_reg = 1'b0;
#0 ap_CS_fsm = 4'd1;
#0 ap_enable_reg_pp0_iter1 = 1'b0;
#0 ap_enable_reg_pp0_iter10 = 1'b0;
#0 ap_enable_reg_pp0_iter0 = 1'b0;
#0 ap_enable_reg_pp0_iter2 = 1'b0;
#0 ap_enable_reg_pp0_iter3 = 1'b0;
#0 ap_enable_reg_pp0_iter4 = 1'b0;
#0 ap_enable_reg_pp0_iter5 = 1'b0;
#0 ap_enable_reg_pp0_iter6 = 1'b0;
#0 ap_enable_reg_pp0_iter7 = 1'b0;
#0 ap_enable_reg_pp0_iter8 = 1'b0;
#0 ap_enable_reg_pp0_iter9 = 1'b0;
end
CvtColor_1_sectormb6 #(
.DataWidth( 2 ),
.AddressRange( 6 ),
.AddressWidth( 3 ))
sector_data_0_U(
.clk(ap_clk),
.reset(ap_rst),
.address0(sector_data_0_address0),
.ce0(sector_data_0_ce0),
.q0(sector_data_0_q0)
);
CvtColor_1_sectorncg #(
.DataWidth( 2 ),
.AddressRange( 6 ),
.AddressWidth( 3 ))
sector_data_1_U(
.clk(ap_clk),
.reset(ap_rst),
.address0(sector_data_1_address0),
.ce0(sector_data_1_ce0),
.q0(sector_data_1_q0)
);
CvtColor_1_sectorocq #(
.DataWidth( 2 ),
.AddressRange( 6 ),
.AddressWidth( 3 ))
sector_data_2_U(
.clk(ap_clk),
.reset(ap_rst),
.address0(sector_data_2_address0),
.ce0(sector_data_2_ce0),
.q0(sector_data_2_q0)
);
hls_saturation_enpcA #(
.ID( 1 ),
.NUM_STAGE( 3 ),
.din0_WIDTH( 29 ),
.din1_WIDTH( 28 ),
.dout_WIDTH( 47 ))
hls_saturation_enpcA_U60(
.clk(ap_clk),
.reset(ap_rst),
.din0(r_V_reg_863),
.din1(grp_fu_418_p1),
.ce(grp_fu_418_ce),
.dout(grp_fu_418_p2)
);
hls_saturation_enqcK #(
.ID( 1 ),
.NUM_STAGE( 1 ),
.din0_WIDTH( 28 ),
.din1_WIDTH( 28 ),
.din2_WIDTH( 28 ),
.din3_WIDTH( 28 ),
.din4_WIDTH( 2 ),
.dout_WIDTH( 28 ))
hls_saturation_enqcK_U61(
.din0(ap_reg_pp0_iter8_tab_0_V_reg_833),
.din1(ap_reg_pp0_iter8_tab_1_V_reg_855),
.din2(tab_2_V_reg_904),
.din3(tab_3_V_reg_911),
.din4(sector_data_0_load_reg_918),
.dout(p_Val2_7_fu_491_p6)
);
hls_saturation_enqcK #(
.ID( 1 ),
.NUM_STAGE( 1 ),
.din0_WIDTH( 28 ),
.din1_WIDTH( 28 ),
.din2_WIDTH( 28 ),
.din3_WIDTH( 28 ),
.din4_WIDTH( 2 ),
.dout_WIDTH( 28 ))
hls_saturation_enqcK_U62(
.din0(ap_reg_pp0_iter8_tab_0_V_reg_833),
.din1(ap_reg_pp0_iter8_tab_1_V_reg_855),
.din2(tab_2_V_reg_904),
.din3(tab_3_V_reg_911),
.din4(sector_data_1_load_reg_923),
.dout(p_Val2_11_fu_578_p6)
);
hls_saturation_enqcK #(
.ID( 1 ),
.NUM_STAGE( 1 ),
.din0_WIDTH( 28 ),
.din1_WIDTH( 28 ),
.din2_WIDTH( 28 ),
.din3_WIDTH( 28 ),
.din4_WIDTH( 2 ),
.dout_WIDTH( 28 ))
hls_saturation_enqcK_U63(
.din0(ap_reg_pp0_iter8_tab_0_V_reg_833),
.din1(ap_reg_pp0_iter8_tab_1_V_reg_855),
.din2(tab_2_V_reg_904),
.din3(tab_3_V_reg_911),
.din4(sector_data_2_load_reg_928),
.dout(p_Val2_s_fu_665_p6)
);
hls_saturation_enrcU #(
.ID( 1 ),
.NUM_STAGE( 1 ),
.din0_WIDTH( 19 ),
.din1_WIDTH( 8 ),
.dout_WIDTH( 27 ))
hls_saturation_enrcU_U64(
.din0(p_Val2_i_fu_752_p0),
.din1(p_Val2_i_fu_752_p1),
.dout(p_Val2_i_fu_752_p2)
);
hls_saturation_ensc4 #(
.ID( 1 ),
.NUM_STAGE( 1 ),
.din0_WIDTH( 16 ),
.din1_WIDTH( 8 ),
.dout_WIDTH( 24 ))
hls_saturation_ensc4_U65(
.din0(r_V_3_fu_758_p0),
.din1(r_V_3_fu_758_p1),
.dout(r_V_3_fu_758_p2)
);
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_CS_fsm <= ap_ST_fsm_state1;
end else begin
ap_CS_fsm <= ap_NS_fsm;
end
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_done_reg <= 1'b0;
end else begin
if ((ap_continue == 1'b1)) begin
ap_done_reg <= 1'b0;
end else if (((1'b1 == ap_CS_fsm_state2) & (tmp_i_fu_241_p2 == 1'd0))) begin
ap_done_reg <= 1'b1;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_enable_reg_pp0_iter0 <= 1'b0;
end else begin
if (((1'b0 == ap_block_pp0_stage0_subdone) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_condition_pp0_exit_iter0_state3))) begin
ap_enable_reg_pp0_iter0 <= 1'b0;
end else if (((1'b1 == ap_CS_fsm_state2) & (tmp_i_fu_241_p2 == 1'd1))) begin
ap_enable_reg_pp0_iter0 <= 1'b1;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_enable_reg_pp0_iter1 <= 1'b0;
end else begin
if ((1'b0 == ap_block_pp0_stage0_subdone)) begin
if ((1'b1 == ap_condition_pp0_exit_iter0_state3)) begin
ap_enable_reg_pp0_iter1 <= (1'b1 ^ ap_condition_pp0_exit_iter0_state3);
end else if ((1'b1 == 1'b1)) begin
ap_enable_reg_pp0_iter1 <= ap_enable_reg_pp0_iter0;
end
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_enable_reg_pp0_iter10 <= 1'b0;
end else begin
if ((1'b0 == ap_block_pp0_stage0_subdone)) begin
ap_enable_reg_pp0_iter10 <= ap_enable_reg_pp0_iter9;
end else if (((1'b1 == ap_CS_fsm_state2) & (tmp_i_fu_241_p2 == 1'd1))) begin
ap_enable_reg_pp0_iter10 <= 1'b0;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_enable_reg_pp0_iter2 <= 1'b0;
end else begin
if ((1'b0 == ap_block_pp0_stage0_subdone)) begin
ap_enable_reg_pp0_iter2 <= ap_enable_reg_pp0_iter1;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_enable_reg_pp0_iter3 <= 1'b0;
end else begin
if ((1'b0 == ap_block_pp0_stage0_subdone)) begin
ap_enable_reg_pp0_iter3 <= ap_enable_reg_pp0_iter2;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_enable_reg_pp0_iter4 <= 1'b0;
end else begin
if ((1'b0 == ap_block_pp0_stage0_subdone)) begin
ap_enable_reg_pp0_iter4 <= ap_enable_reg_pp0_iter3;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_enable_reg_pp0_iter5 <= 1'b0;
end else begin
if ((1'b0 == ap_block_pp0_stage0_subdone)) begin
ap_enable_reg_pp0_iter5 <= ap_enable_reg_pp0_iter4;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_enable_reg_pp0_iter6 <= 1'b0;
end else begin
if ((1'b0 == ap_block_pp0_stage0_subdone)) begin
ap_enable_reg_pp0_iter6 <= ap_enable_reg_pp0_iter5;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_enable_reg_pp0_iter7 <= 1'b0;
end else begin
if ((1'b0 == ap_block_pp0_stage0_subdone)) begin
ap_enable_reg_pp0_iter7 <= ap_enable_reg_pp0_iter6;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_enable_reg_pp0_iter8 <= 1'b0;
end else begin
if ((1'b0 == ap_block_pp0_stage0_subdone)) begin
ap_enable_reg_pp0_iter8 <= ap_enable_reg_pp0_iter7;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_enable_reg_pp0_iter9 <= 1'b0;
end else begin
if ((1'b0 == ap_block_pp0_stage0_subdone)) begin
ap_enable_reg_pp0_iter9 <= ap_enable_reg_pp0_iter8;
end
end
end
always @ (posedge ap_clk) begin
if ((1'b1 == ap_CS_fsm_state14)) begin
i_i_reg_215 <= i_reg_778;
end else if ((~((ap_start == 1'b0) | (p_src_cols_V_empty_n == 1'b0) | (p_src_rows_V_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
i_i_reg_215 <= 11'd0;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001) & (tmp_53_i_fu_256_p2 == 1'd1))) begin
j_i_reg_226 <= j_fu_261_p2;
end else if (((1'b1 == ap_CS_fsm_state2) & (tmp_i_fu_241_p2 == 1'd1))) begin
j_i_reg_226 <= 11'd0;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0_11001))) begin
ap_reg_pp0_iter1_tmp_53_i_reg_783 <= tmp_53_i_reg_783;
tmp_53_i_reg_783 <= tmp_53_i_fu_256_p2;
end
end
always @ (posedge ap_clk) begin
if ((1'b0 == ap_block_pp0_stage0_11001)) begin
ap_reg_pp0_iter2_tmp_10_reg_816 <= tmp_10_reg_816;
ap_reg_pp0_iter2_tmp_26_reg_792 <= tmp_26_reg_792;
ap_reg_pp0_iter2_tmp_27_reg_797 <= tmp_27_reg_797;
ap_reg_pp0_iter2_tmp_28_reg_804 <= tmp_28_reg_804;
ap_reg_pp0_iter2_tmp_53_i_reg_783 <= ap_reg_pp0_iter1_tmp_53_i_reg_783;
ap_reg_pp0_iter2_tmp_reg_811 <= tmp_reg_811;
ap_reg_pp0_iter3_tmp_27_reg_797 <= ap_reg_pp0_iter2_tmp_27_reg_797;
ap_reg_pp0_iter3_tmp_53_i_reg_783 <= ap_reg_pp0_iter2_tmp_53_i_reg_783;
ap_reg_pp0_iter4_tab_0_V_reg_833 <= tab_0_V_reg_833;
ap_reg_pp0_iter4_tmp_53_i_reg_783 <= ap_reg_pp0_iter3_tmp_53_i_reg_783;
ap_reg_pp0_iter5_tab_0_V_reg_833 <= ap_reg_pp0_iter4_tab_0_V_reg_833;
ap_reg_pp0_iter5_tab_1_V_reg_855 <= tab_1_V_reg_855;
ap_reg_pp0_iter5_tmp_53_i_reg_783 <= ap_reg_pp0_iter4_tmp_53_i_reg_783;
ap_reg_pp0_iter5_tmp_s_reg_843 <= tmp_s_reg_843;
ap_reg_pp0_iter6_tab_0_V_reg_833 <= ap_reg_pp0_iter5_tab_0_V_reg_833;
ap_reg_pp0_iter6_tab_1_V_reg_855 <= ap_reg_pp0_iter5_tab_1_V_reg_855;
ap_reg_pp0_iter6_tmp_53_i_reg_783 <= ap_reg_pp0_iter5_tmp_53_i_reg_783;
ap_reg_pp0_iter7_tab_0_V_reg_833 <= ap_reg_pp0_iter6_tab_0_V_reg_833;
ap_reg_pp0_iter7_tab_1_V_reg_855 <= ap_reg_pp0_iter6_tab_1_V_reg_855;
ap_reg_pp0_iter7_tmp_53_i_reg_783 <= ap_reg_pp0_iter6_tmp_53_i_reg_783;
ap_reg_pp0_iter8_tab_0_V_reg_833 <= ap_reg_pp0_iter7_tab_0_V_reg_833;
ap_reg_pp0_iter8_tab_1_V_reg_855 <= ap_reg_pp0_iter7_tab_1_V_reg_855;
ap_reg_pp0_iter8_tmp_53_i_reg_783 <= ap_reg_pp0_iter7_tmp_53_i_reg_783;
ap_reg_pp0_iter9_tmp_53_i_reg_783 <= ap_reg_pp0_iter8_tmp_53_i_reg_783;
end
end
always @ (posedge ap_clk) begin
if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_reg_pp0_iter3_tmp_53_i_reg_783 == 1'd1))) begin
f_V_reg_850 <= f_V_fu_377_p2;
r_V_reg_863 <= r_V_fu_402_p2;
tab_1_V_reg_855 <= tab_1_V_fu_390_p2;
tmp_s_reg_843 <= {{r_V_3_reg_827[23:19]}};
end
end
always @ (posedge ap_clk) begin
if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_reg_pp0_iter5_tmp_53_i_reg_783 == 1'd1))) begin
h_i_1_reg_878 <= h_i_1_fu_434_p3;
end
end
always @ (posedge ap_clk) begin
if ((1'b1 == ap_CS_fsm_state2)) begin
i_reg_778 <= i_fu_246_p2;
end
end
always @ (posedge ap_clk) begin
if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_reg_pp0_iter8_tmp_53_i_reg_783 == 1'd1))) begin
p_Val2_20_reg_933 <= p_Val2_20_fu_570_p3;
p_Val2_21_reg_938 <= p_Val2_21_fu_657_p3;
p_Val2_22_reg_943 <= p_Val2_22_fu_744_p3;
end
end
always @ (posedge ap_clk) begin
if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_reg_pp0_iter6_tmp_53_i_reg_783 == 1'd1))) begin
p_Val2_4_i_reg_883 <= grp_fu_418_p2;
end
end
always @ (posedge ap_clk) begin
if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_reg_pp0_iter1_tmp_53_i_reg_783 == 1'd1))) begin
p_Val2_i_reg_821 <= p_Val2_i_fu_752_p2;
end
end
always @ (posedge ap_clk) begin
if ((~((ap_start == 1'b0) | (p_src_cols_V_empty_n == 1'b0) | (p_src_rows_V_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
p_src_cols_V_read_reg_764 <= p_src_cols_V_dout;
p_src_rows_V_read_reg_769 <= p_src_rows_V_dout;
end
end
always @ (posedge ap_clk) begin
if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_reg_pp0_iter2_tmp_53_i_reg_783 == 1'd1))) begin
r_V_3_reg_827 <= r_V_3_fu_758_p2;
tab_0_V_reg_833 <= tab_0_V_fu_346_p3;
end
end
always @ (posedge ap_clk) begin
if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_reg_pp0_iter7_tmp_53_i_reg_783 == 1'd1))) begin
sector_data_0_load_reg_918 <= sector_data_0_q0;
sector_data_1_load_reg_923 <= sector_data_1_q0;
sector_data_2_load_reg_928 <= sector_data_2_q0;
tab_2_V_reg_904 <= {{p_Val2_5_fu_454_p2[46:19]}};
tab_3_V_reg_911 <= {{p_Val2_6_fu_476_p2[46:19]}};
end
end
always @ (posedge ap_clk) begin
if (((tmp_53_i_reg_783 == 1'd1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0_11001))) begin
tmp_10_reg_816 <= tmp_10_fu_275_p1;
tmp_26_reg_792 <= p_src_data_stream_0_V_dout;
tmp_27_reg_797 <= p_src_data_stream_1_V_dout;
tmp_28_reg_804 <= p_src_data_stream_2_V_dout;
tmp_reg_811 <= p_src_data_stream_1_V_dout[32'd7];
end
end
always @ (*) begin
if ((tmp_53_i_fu_256_p2 == 1'd0)) begin
ap_condition_pp0_exit_iter0_state3 = 1'b1;
end else begin
ap_condition_pp0_exit_iter0_state3 = 1'b0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state2) & (tmp_i_fu_241_p2 == 1'd0))) begin
ap_done = 1'b1;
end else begin
ap_done = ap_done_reg;
end
end
always @ (*) begin
if (((ap_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin
ap_idle = 1'b1;
end else begin
ap_idle = 1'b0;
end
end
always @ (*) begin
if (((ap_enable_reg_pp0_iter1 == 1'b0) & (ap_enable_reg_pp0_iter9 == 1'b0) & (ap_enable_reg_pp0_iter8 == 1'b0) & (ap_enable_reg_pp0_iter7 == 1'b0) & (ap_enable_reg_pp0_iter6 == 1'b0) & (ap_enable_reg_pp0_iter5 == 1'b0) & (ap_enable_reg_pp0_iter4 == 1'b0) & (ap_enable_reg_pp0_iter3 == 1'b0) & (ap_enable_reg_pp0_iter2 == 1'b0) & (ap_enable_reg_pp0_iter0 == 1'b0) & (ap_enable_reg_pp0_iter10 == 1'b0))) begin
ap_idle_pp0 = 1'b1;
end else begin
ap_idle_pp0 = 1'b0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state2) & (tmp_i_fu_241_p2 == 1'd0))) begin
ap_ready = 1'b1;
end else begin
ap_ready = 1'b0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0_11001))) begin
grp_fu_418_ce = 1'b1;
end else begin
grp_fu_418_ce = 1'b0;
end
end
always @ (*) begin
if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter10 == 1'b1) & (ap_reg_pp0_iter9_tmp_53_i_reg_783 == 1'd1))) begin
p_dst_data_stream_0_V_blk_n = p_dst_data_stream_0_V_full_n;
end else begin
p_dst_data_stream_0_V_blk_n = 1'b1;
end
end
always @ (*) begin
if (((ap_enable_reg_pp0_iter10 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_reg_pp0_iter9_tmp_53_i_reg_783 == 1'd1))) begin
p_dst_data_stream_0_V_write = 1'b1;
end else begin
p_dst_data_stream_0_V_write = 1'b0;
end
end
always @ (*) begin
if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter10 == 1'b1) & (ap_reg_pp0_iter9_tmp_53_i_reg_783 == 1'd1))) begin
p_dst_data_stream_1_V_blk_n = p_dst_data_stream_1_V_full_n;
end else begin
p_dst_data_stream_1_V_blk_n = 1'b1;
end
end
always @ (*) begin
if (((ap_enable_reg_pp0_iter10 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_reg_pp0_iter9_tmp_53_i_reg_783 == 1'd1))) begin
p_dst_data_stream_1_V_write = 1'b1;
end else begin
p_dst_data_stream_1_V_write = 1'b0;
end
end
always @ (*) begin
if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter10 == 1'b1) & (ap_reg_pp0_iter9_tmp_53_i_reg_783 == 1'd1))) begin
p_dst_data_stream_2_V_blk_n = p_dst_data_stream_2_V_full_n;
end else begin
p_dst_data_stream_2_V_blk_n = 1'b1;
end
end
always @ (*) begin
if (((ap_enable_reg_pp0_iter10 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_reg_pp0_iter9_tmp_53_i_reg_783 == 1'd1))) begin
p_dst_data_stream_2_V_write = 1'b1;
end else begin
p_dst_data_stream_2_V_write = 1'b0;
end
end
always @ (*) begin
if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
p_src_cols_V_blk_n = p_src_cols_V_empty_n;
end else begin
p_src_cols_V_blk_n = 1'b1;
end
end
always @ (*) begin
if ((~((ap_start == 1'b0) | (p_src_cols_V_empty_n == 1'b0) | (p_src_rows_V_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
p_src_cols_V_read = 1'b1;
end else begin
p_src_cols_V_read = 1'b0;
end
end
always @ (*) begin
if (((tmp_53_i_reg_783 == 1'd1) & (1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin
p_src_data_stream_0_V_blk_n = p_src_data_stream_0_V_empty_n;
end else begin
p_src_data_stream_0_V_blk_n = 1'b1;
end
end
always @ (*) begin
if (((tmp_53_i_reg_783 == 1'd1) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0_11001))) begin
p_src_data_stream_0_V_read = 1'b1;
end else begin
p_src_data_stream_0_V_read = 1'b0;
end
end
always @ (*) begin
if (((tmp_53_i_reg_783 == 1'd1) & (1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin
p_src_data_stream_1_V_blk_n = p_src_data_stream_1_V_empty_n;
end else begin
p_src_data_stream_1_V_blk_n = 1'b1;
end
end
always @ (*) begin
if (((tmp_53_i_reg_783 == 1'd1) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0_11001))) begin
p_src_data_stream_1_V_read = 1'b1;
end else begin
p_src_data_stream_1_V_read = 1'b0;
end
end
always @ (*) begin
if (((tmp_53_i_reg_783 == 1'd1) & (1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin
p_src_data_stream_2_V_blk_n = p_src_data_stream_2_V_empty_n;
end else begin
p_src_data_stream_2_V_blk_n = 1'b1;
end
end
always @ (*) begin
if (((tmp_53_i_reg_783 == 1'd1) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0_11001))) begin
p_src_data_stream_2_V_read = 1'b1;
end else begin
p_src_data_stream_2_V_read = 1'b0;
end
end
always @ (*) begin
if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
p_src_rows_V_blk_n = p_src_rows_V_empty_n;
end else begin
p_src_rows_V_blk_n = 1'b1;
end
end
always @ (*) begin
if ((~((ap_start == 1'b0) | (p_src_cols_V_empty_n == 1'b0) | (p_src_rows_V_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
p_src_rows_V_read = 1'b1;
end else begin
p_src_rows_V_read = 1'b0;
end
end
always @ (*) begin
if (((ap_enable_reg_pp0_iter7 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin
sector_data_0_ce0 = 1'b1;
end else begin
sector_data_0_ce0 = 1'b0;
end
end
always @ (*) begin
if (((ap_enable_reg_pp0_iter7 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin
sector_data_1_ce0 = 1'b1;
end else begin
sector_data_1_ce0 = 1'b0;
end
end
always @ (*) begin
if (((ap_enable_reg_pp0_iter7 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin
sector_data_2_ce0 = 1'b1;
end else begin
sector_data_2_ce0 = 1'b0;
end
end
always @ (*) begin
case (ap_CS_fsm)
ap_ST_fsm_state1 : begin
if ((~((ap_start == 1'b0) | (p_src_cols_V_empty_n == 1'b0) | (p_src_rows_V_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
ap_NS_fsm = ap_ST_fsm_state2;
end else begin
ap_NS_fsm = ap_ST_fsm_state1;
end
end
ap_ST_fsm_state2 : begin
if (((1'b1 == ap_CS_fsm_state2) & (tmp_i_fu_241_p2 == 1'd0))) begin
ap_NS_fsm = ap_ST_fsm_state1;
end else begin
ap_NS_fsm = ap_ST_fsm_pp0_stage0;
end
end
ap_ST_fsm_pp0_stage0 : begin
if ((~((ap_enable_reg_pp0_iter1 == 1'b0) & (1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter0 == 1'b1) & (tmp_53_i_fu_256_p2 == 1'd0)) & ~((ap_enable_reg_pp0_iter9 == 1'b0) & (1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter10 == 1'b1)))) begin
ap_NS_fsm = ap_ST_fsm_pp0_stage0;
end else if ((((ap_enable_reg_pp0_iter1 == 1'b0) & (1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter0 == 1'b1) & (tmp_53_i_fu_256_p2 == 1'd0)) | ((ap_enable_reg_pp0_iter9 == 1'b0) & (1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter10 == 1'b1)))) begin
ap_NS_fsm = ap_ST_fsm_state14;
end else begin
ap_NS_fsm = ap_ST_fsm_pp0_stage0;
end
end
ap_ST_fsm_state14 : begin
ap_NS_fsm = ap_ST_fsm_state2;
end
default : begin
ap_NS_fsm = 'bx;
end
endcase
end
assign Range1_all_ones_6_fu_651_p2 = (lD_1_fu_643_p3 | carry_1_fu_637_p2);
assign Range1_all_ones_7_fu_738_p2 = (lD_2_fu_730_p3 | carry_2_fu_724_p2);
assign Range1_all_ones_fu_564_p2 = (lD_fu_556_p3 | carry_fu_550_p2);
assign ap_CS_fsm_pp0_stage0 = ap_CS_fsm[32'd2];
assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0];
assign ap_CS_fsm_state14 = ap_CS_fsm[32'd3];
assign ap_CS_fsm_state2 = ap_CS_fsm[32'd1];
assign ap_block_pp0_stage0 = ~(1'b1 == 1'b1);
always @ (*) begin
ap_block_pp0_stage0_01001 = (((ap_enable_reg_pp0_iter1 == 1'b1) & (((tmp_53_i_reg_783 == 1'd1) & (p_src_data_stream_2_V_empty_n == 1'b0)) | ((tmp_53_i_reg_783 == 1'd1) & (p_src_data_stream_1_V_empty_n == 1'b0)) | ((tmp_53_i_reg_783 == 1'd1) & (p_src_data_stream_0_V_empty_n == 1'b0)))) | ((ap_enable_reg_pp0_iter10 == 1'b1) & (((p_dst_data_stream_2_V_full_n == 1'b0) & (ap_reg_pp0_iter9_tmp_53_i_reg_783 == 1'd1)) | ((p_dst_data_stream_1_V_full_n == 1'b0) & (ap_reg_pp0_iter9_tmp_53_i_reg_783 == 1'd1)) | ((p_dst_data_stream_0_V_full_n == 1'b0) & (ap_reg_pp0_iter9_tmp_53_i_reg_783 == 1'd1)))));
end
always @ (*) begin
ap_block_pp0_stage0_11001 = (((ap_enable_reg_pp0_iter1 == 1'b1) & (((tmp_53_i_reg_783 == 1'd1) & (p_src_data_stream_2_V_empty_n == 1'b0)) | ((tmp_53_i_reg_783 == 1'd1) & (p_src_data_stream_1_V_empty_n == 1'b0)) | ((tmp_53_i_reg_783 == 1'd1) & (p_src_data_stream_0_V_empty_n == 1'b0)))) | ((ap_enable_reg_pp0_iter10 == 1'b1) & (((p_dst_data_stream_2_V_full_n == 1'b0) & (ap_reg_pp0_iter9_tmp_53_i_reg_783 == 1'd1)) | ((p_dst_data_stream_1_V_full_n == 1'b0) & (ap_reg_pp0_iter9_tmp_53_i_reg_783 == 1'd1)) | ((p_dst_data_stream_0_V_full_n == 1'b0) & (ap_reg_pp0_iter9_tmp_53_i_reg_783 == 1'd1)))));
end
always @ (*) begin
ap_block_pp0_stage0_subdone = (((ap_enable_reg_pp0_iter1 == 1'b1) & (((tmp_53_i_reg_783 == 1'd1) & (p_src_data_stream_2_V_empty_n == 1'b0)) | ((tmp_53_i_reg_783 == 1'd1) & (p_src_data_stream_1_V_empty_n == 1'b0)) | ((tmp_53_i_reg_783 == 1'd1) & (p_src_data_stream_0_V_empty_n == 1'b0)))) | ((ap_enable_reg_pp0_iter10 == 1'b1) & (((p_dst_data_stream_2_V_full_n == 1'b0) & (ap_reg_pp0_iter9_tmp_53_i_reg_783 == 1'd1)) | ((p_dst_data_stream_1_V_full_n == 1'b0) & (ap_reg_pp0_iter9_tmp_53_i_reg_783 == 1'd1)) | ((p_dst_data_stream_0_V_full_n == 1'b0) & (ap_reg_pp0_iter9_tmp_53_i_reg_783 == 1'd1)))));
end
always @ (*) begin
ap_block_state1 = ((ap_start == 1'b0) | (p_src_cols_V_empty_n == 1'b0) | (p_src_rows_V_empty_n == 1'b0) | (ap_done_reg == 1'b1));
end
assign ap_block_state10_pp0_stage0_iter7 = ~(1'b1 == 1'b1);
assign ap_block_state11_pp0_stage0_iter8 = ~(1'b1 == 1'b1);
assign ap_block_state12_pp0_stage0_iter9 = ~(1'b1 == 1'b1);
always @ (*) begin
ap_block_state13_pp0_stage0_iter10 = (((p_dst_data_stream_2_V_full_n == 1'b0) & (ap_reg_pp0_iter9_tmp_53_i_reg_783 == 1'd1)) | ((p_dst_data_stream_1_V_full_n == 1'b0) & (ap_reg_pp0_iter9_tmp_53_i_reg_783 == 1'd1)) | ((p_dst_data_stream_0_V_full_n == 1'b0) & (ap_reg_pp0_iter9_tmp_53_i_reg_783 == 1'd1)));
end
assign ap_block_state3_pp0_stage0_iter0 = ~(1'b1 == 1'b1);
always @ (*) begin
ap_block_state4_pp0_stage0_iter1 = (((tmp_53_i_reg_783 == 1'd1) & (p_src_data_stream_2_V_empty_n == 1'b0)) | ((tmp_53_i_reg_783 == 1'd1) & (p_src_data_stream_1_V_empty_n == 1'b0)) | ((tmp_53_i_reg_783 == 1'd1) & (p_src_data_stream_0_V_empty_n == 1'b0)));
end
assign ap_block_state5_pp0_stage0_iter2 = ~(1'b1 == 1'b1);
assign ap_block_state6_pp0_stage0_iter3 = ~(1'b1 == 1'b1);
assign ap_block_state7_pp0_stage0_iter4 = ~(1'b1 == 1'b1);
assign ap_block_state8_pp0_stage0_iter5 = ~(1'b1 == 1'b1);
assign ap_block_state9_pp0_stage0_iter6 = ~(1'b1 == 1'b1);
assign ap_enable_pp0 = (ap_idle_pp0 ^ 1'b1);
assign carry_1_fu_637_p2 = (tmp_16_fu_609_p3 & tmp_14_i_i113_i_fu_631_p2);
assign carry_2_fu_724_p2 = (tmp_20_fu_696_p3 & tmp_14_i_i126_i_fu_718_p2);
assign carry_fu_550_p2 = (tmp_14_i_i_i_fu_544_p2 & tmp_12_fu_522_p3);
assign f_V_cast_fu_408_p1 = $signed(f_V_reg_850);
assign f_V_fu_377_p2 = (r_V_10_cast1_i_cast_fu_353_p1 - tmp_55_cast_i_cast_fu_373_p1);
assign grp_fu_418_p1 = grp_fu_418_p10;
assign grp_fu_418_p10 = $unsigned(f_V_cast_fu_408_p1);
assign h_i_1_fu_434_p3 = ((tmp_58_i_fu_424_p2[0:0] === 1'b1) ? h_i_fu_429_p2 : ap_reg_pp0_iter5_tmp_s_reg_843);
assign h_i_fu_429_p2 = ($signed(5'd26) + $signed(ap_reg_pp0_iter5_tmp_s_reg_843));
assign i_cast_i_cast_fu_237_p1 = i_i_reg_215;
assign i_fu_246_p2 = (i_i_reg_215 + 11'd1);
assign j_cast_i_cast_fu_252_p1 = j_i_reg_226;
assign j_fu_261_p2 = (j_i_reg_226 + 11'd1);
assign lD_1_fu_643_p3 = p_Val2_11_fu_578_p6[32'd27];
assign lD_2_fu_730_p3 = p_Val2_s_fu_665_p6[32'd27];
assign lD_fu_556_p3 = p_Val2_7_fu_491_p6[32'd27];
assign p_Val2_12_fu_587_p4 = {{p_Val2_11_fu_578_p6[26:19]}};
assign p_Val2_13_fu_617_p2 = (p_Val2_12_fu_587_p4 + tmp_i_i109_i_fu_605_p1);
assign p_Val2_17_fu_674_p4 = {{p_Val2_s_fu_665_p6[26:19]}};
assign p_Val2_18_fu_704_p2 = (p_Val2_17_fu_674_p4 + tmp_i_i122_i_fu_692_p1);
assign p_Val2_1_i_fu_320_p2 = (tmp_65_i_fu_312_p3 - p_Val2_cast_i_fu_297_p1);
assign p_Val2_20_fu_570_p3 = ((Range1_all_ones_fu_564_p2[0:0] === 1'b1) ? 8'd255 : p_Val2_9_fu_530_p2);
assign p_Val2_21_fu_657_p3 = ((Range1_all_ones_6_fu_651_p2[0:0] === 1'b1) ? 8'd255 : p_Val2_13_fu_617_p2);
assign p_Val2_22_fu_744_p3 = ((Range1_all_ones_7_fu_738_p2[0:0] === 1'b1) ? 8'd255 : p_Val2_18_fu_704_p2);
assign p_Val2_2_cast_i_fu_342_p1 = p_Val2_2_i_fu_337_p2;
assign p_Val2_2_i_fu_337_p2 = (p_Val2_i_reg_821 + tmp_66_cast_i_fu_333_p1);
assign p_Val2_5_fu_454_p2 = (tmp_71_i_fu_447_p3 - p_Val2_4_i_reg_883);
assign p_Val2_6_fu_476_p2 = (tmp_76_i_fu_469_p3 + p_Val2_4_i_reg_883);
assign p_Val2_8_fu_500_p4 = {{p_Val2_7_fu_491_p6[26:19]}};
assign p_Val2_9_fu_530_p2 = (p_Val2_8_fu_500_p4 + tmp_i_i_i_fu_518_p1);
assign p_Val2_cast_i_fu_297_p1 = p_Val2_i_reg_821;
assign p_Val2_i_fu_752_p0 = p_Val2_i_fu_752_p00;
assign p_Val2_i_fu_752_p00 = r_V_4_fu_279_p4;
assign p_Val2_i_fu_752_p1 = p_Val2_i_fu_752_p10;
assign p_Val2_i_fu_752_p10 = tmp_27_reg_797;
assign p_dst_data_stream_0_V_din = p_Val2_20_reg_933;
assign p_dst_data_stream_1_V_din = p_Val2_21_reg_938;
assign p_dst_data_stream_2_V_din = p_Val2_22_reg_943;
assign r_V_10_cast1_i_cast_fu_353_p1 = r_V_3_reg_827;
assign r_V_3_fu_758_p0 = 24'd17476;
assign r_V_3_fu_758_p1 = r_V_3_fu_758_p10;
assign r_V_3_fu_758_p10 = ap_reg_pp0_iter2_tmp_26_reg_792;
assign r_V_4_fu_279_p4 = {{{tmp_28_reg_804}, {tmp_28_reg_804}}, {3'd0}};
assign r_V_fu_402_p2 = (tmp_68_i_fu_395_p1 - tmp_69_i_fu_398_p1);
assign sector_data_0_address0 = tmp_79_i_fu_441_p1;
assign sector_data_1_address0 = tmp_79_i_fu_441_p1;
assign sector_data_2_address0 = tmp_79_i_fu_441_p1;
assign tab_0_V_fu_346_p3 = ((ap_reg_pp0_iter2_tmp_reg_811[0:0] === 1'b1) ? p_Val2_1_i_fu_320_p2 : p_Val2_2_cast_i_fu_342_p1);
assign tab_1_V_fu_390_p2 = (tmp_67_i_fu_383_p3 - tab_0_V_reg_833);
assign tmp_10_fu_275_p1 = p_src_data_stream_1_V_dout[6:0];
assign tmp_11_fu_510_p3 = p_Val2_7_fu_491_p6[32'd18];
assign tmp_12_fu_522_p3 = p_Val2_7_fu_491_p6[32'd26];
assign tmp_13_fu_536_p3 = p_Val2_9_fu_530_p2[32'd7];
assign tmp_14_i_i113_i_fu_631_p2 = (tmp_17_fu_623_p3 ^ 1'd1);
assign tmp_14_i_i126_i_fu_718_p2 = (tmp_21_fu_710_p3 ^ 1'd1);
assign tmp_14_i_i_i_fu_544_p2 = (tmp_13_fu_536_p3 ^ 1'd1);
assign tmp_15_fu_597_p3 = p_Val2_11_fu_578_p6[32'd18];
assign tmp_16_fu_609_p3 = p_Val2_11_fu_578_p6[32'd26];
assign tmp_17_fu_623_p3 = p_Val2_13_fu_617_p2[32'd7];
assign tmp_19_fu_684_p3 = p_Val2_s_fu_665_p6[32'd18];
assign tmp_20_fu_696_p3 = p_Val2_s_fu_665_p6[32'd26];
assign tmp_21_fu_710_p3 = p_Val2_18_fu_704_p2[32'd7];
assign tmp_53_i_fu_256_p2 = ((j_cast_i_cast_fu_252_p1 < p_src_cols_V_read_reg_764) ? 1'b1 : 1'b0);
assign tmp_55_cast_i_cast_fu_373_p1 = tmp_55_i_fu_365_p3;
assign tmp_55_i_fu_365_p3 = {{tmp_s_fu_356_p4}, {19'd0}};
assign tmp_58_i_fu_424_p2 = ((ap_reg_pp0_iter5_tmp_s_reg_843 > 5'd5) ? 1'b1 : 1'b0);
assign tmp_61_i_fu_300_p1 = ap_reg_pp0_iter2_tmp_28_reg_804;
assign tmp_62_i_fu_303_p1 = ap_reg_pp0_iter2_tmp_27_reg_797;
assign tmp_63_i_fu_306_p2 = (tmp_62_i_fu_303_p1 + tmp_61_i_fu_300_p1);
assign tmp_65_i_fu_312_p3 = {{tmp_63_i_fu_306_p2}, {19'd0}};
assign tmp_66_cast_i_fu_333_p1 = tmp_66_i_fu_326_p3;
assign tmp_66_i_fu_326_p3 = {{ap_reg_pp0_iter2_tmp_10_reg_816}, {19'd0}};
assign tmp_67_i_fu_383_p3 = {{ap_reg_pp0_iter3_tmp_27_reg_797}, {20'd0}};
assign tmp_68_i_fu_395_p1 = tab_0_V_reg_833;
assign tmp_69_i_fu_398_p1 = tab_1_V_fu_390_p2;
assign tmp_71_i_fu_447_p3 = {{ap_reg_pp0_iter7_tab_0_V_reg_833}, {19'd0}};
assign tmp_76_i_fu_469_p3 = {{ap_reg_pp0_iter7_tab_1_V_reg_855}, {19'd0}};
assign tmp_79_i_fu_441_p1 = h_i_1_reg_878;
assign tmp_i_fu_241_p2 = ((i_cast_i_cast_fu_237_p1 < p_src_rows_V_read_reg_769) ? 1'b1 : 1'b0);
assign tmp_i_i109_i_fu_605_p1 = tmp_15_fu_597_p3;
assign tmp_i_i122_i_fu_692_p1 = tmp_19_fu_684_p3;
assign tmp_i_i_i_fu_518_p1 = tmp_11_fu_510_p3;
assign tmp_s_fu_356_p4 = {{r_V_3_reg_827[23:19]}};
endmodule
|
module frame_detector
(
input clk400,
input clk80,
input reset,
input enable,
input sdata,
output reg [4:0]pdata,
output reg error
);
reg [5:0]s; // shift register
reg detect; // 000001 pattern detected
reg [2:0]c; // frame pos counter
wire sync = c[2]; // periodic frame sync signal
reg [4:0]p; // parallel data register
reg e; // error flag
always @(posedge clk400 or posedge reset)
begin
if (reset)
begin
s <= 0;
detect <= 0;
c <= 0;
p <= 0;
e <= 0;
end
else if (enable)
begin
s <= {s[4:0],sdata};
detect <= (s[5:0] == 6'b100000) || (s[5:0] == 6'b011111);
if (sync || detect) c <= 3'd0; else c <= c + 3'd1;
if (sync) p <= s[5:1];
if (sync) e <= 0; else if (detect) e <= 1;
end
end
always @(posedge clk80 or posedge reset)
begin
if (reset)
begin
pdata <= 5'd0;
error <= 0;
end
else if (enable)
begin
pdata <= p;
error <= e;
end
else
begin
pdata <= 5'd0;
error <= 0;
end
end
endmodule
|
module sky130_fd_sc_hdll__sdfxbp (
Q ,
Q_N,
CLK,
D ,
SCD,
SCE
);
// Module ports
output Q ;
output Q_N;
input CLK;
input D ;
input SCD;
input SCE;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire buf_Q ;
wire mux_out ;
reg notifier ;
wire D_delayed ;
wire SCD_delayed;
wire SCE_delayed;
wire CLK_delayed;
wire awake ;
wire cond1 ;
wire cond2 ;
wire cond3 ;
// Name Output Other arguments
sky130_fd_sc_hdll__udp_mux_2to1 mux_2to10 (mux_out, D_delayed, SCD_delayed, SCE_delayed );
sky130_fd_sc_hdll__udp_dff$P_pp$PG$N dff0 (buf_Q , mux_out, CLK_delayed, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond1 = ( ( SCE_delayed === 1'b0 ) && awake );
assign cond2 = ( ( SCE_delayed === 1'b1 ) && awake );
assign cond3 = ( ( D_delayed !== SCD_delayed ) && awake );
buf buf0 (Q , buf_Q );
not not0 (Q_N , buf_Q );
endmodule
|
module top();
// Inputs are registered
reg A;
reg VGND;
reg VNB;
reg VPB;
reg VPWR;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 VGND = 1'b0;
#60 VNB = 1'b0;
#80 VPB = 1'b0;
#100 VPWR = 1'b0;
#120 A = 1'b1;
#140 VGND = 1'b1;
#160 VNB = 1'b1;
#180 VPB = 1'b1;
#200 VPWR = 1'b1;
#220 A = 1'b0;
#240 VGND = 1'b0;
#260 VNB = 1'b0;
#280 VPB = 1'b0;
#300 VPWR = 1'b0;
#320 VPWR = 1'b1;
#340 VPB = 1'b1;
#360 VNB = 1'b1;
#380 VGND = 1'b1;
#400 A = 1'b1;
#420 VPWR = 1'bx;
#440 VPB = 1'bx;
#460 VNB = 1'bx;
#480 VGND = 1'bx;
#500 A = 1'bx;
end
sky130_fd_sc_hd__probec_p dut (.A(A), .VGND(VGND), .VNB(VNB), .VPB(VPB), .VPWR(VPWR), .X(X));
endmodule
|
module bb_proc
(
output bs_data,
output package_complete,
output crc_check_pass,
input clk_200K,
input pie_code,
input clk_dpie,
input rst
);
wire clk_crc5;
wire clk_crc16;
wire clk_blf;
wire clk_cp;
wire clk_prng;
wire clk_frm;
wire clk_fm0;
wire clk_mil;
wire clk_mem;
wire rst_n;
wire rst_for_new_package;
wire rst_crc16;
wire start_working;
wire dr;
wire [1:0]m;
wire en_crc5;
wire en_crc16;
wire en_2nd_clk_cp;
wire en_prng_idol;
wire en_prng_act;
wire en_tx;
wire en_if;
wire packet_complete_sync;
wire en_crc16_for_rpy;
wire reply_complete;
wire rd_complete;
wire bs_complete;
wire [7:0]cmd;
wire [51:0]param;
wire [15:0]crc_16;
wire reply_data;
wire trext;
wire [18:0]addr;
wire [15:0]prn;
wire rd_data;
wire pre_p_complete;
wire p_complete;
wire [5:0]A;
wire [15:0]Q;
wire CEN;
// --- Clock/Reset Generator ---
crg crg_1
(
.clk_crc5(clk_crc5),
.clk_crc16(clk_crc16),
.clk_blf(clk_blf),
.clk_cp(clk_cp),
.clk_prng(clk_prng),
.clk_frm(clk_frm),
.clk_fm0(clk_fm0),
.clk_mil(clk_mil),
.clk_if(clk_mem),
.rst_n(rst_n),
.clk_200K(clk_200K),
.clk_dpie(clk_dpie),
.pie_code(pie_code),
.rst(rst),
.rst_for_new_package(rst_for_new_package),
.rst_crc16(rst_crc16),
.start_working(start_working),
.dr(dr),
.m(m),
.en_crc5(en_crc5),
.en_crc16(en_crc16),
.en_2nd_clk_cp(en_2nd_clk_cp),
.en_prng_idol(en_prng_idol),
.en_prng_act(en_prng_act),
.en_tx(en_tx),
.en_if(en_if),
.packet_complete_sync(packet_complete_sync),
.en_crc16_for_rpy(en_crc16_for_rpy),
.reply_complete(reply_complete),
.rd_complete(rd_complete),
.bs_complete(bs_complete)
);
// --- RX (including Frame-Sync Detector, CRC-5, CRC-16 and Command Buffer) ---
rx rx_1
(
.cmd(cmd),
.param(param),
.package_complete(package_complete),
.crc_check_pass(crc_check_pass),
.crc_16(crc_16),
.en_crc5(en_crc5),
.en_crc16(en_crc16),
.pie_code(pie_code),
.clk_dpie(clk_dpie),
.clk_crc5(clk_crc5),
.clk_crc16(clk_crc16),
.rst_n(rst_n),
.rst_for_new_package(rst_for_new_package),
.rst_crc16(rst_crc16),
.reply_data(reply_data),
.en_crc16_for_rpy(en_crc16_for_rpy)
);
// --- Synchronizer (convential two flip-flop) ---
two_dff_sync two_dff_sync_1
(
.data_out(packet_complete_sync),
.clk_ad(clk_dpie),
.clk_bd(clk_blf),
.rst_n(rst_n),
.data_in(package_complete)
);
// --- Command Processor ---
cmd_proc cmd_proc_1
(
.reply_data(reply_data),
.reply_complete(reply_complete),
.dr(dr),
.m(m),
.trext(trext),
.en_2nd_clk_cp(en_2nd_clk_cp),
.en_tx(en_tx),
.en_prng_idol(en_prng_idol),
.en_prng_act(en_prng_act),
.en_crc16_for_rpy(en_crc16_for_rpy),
.en_if(en_if),
.addr(addr),
.clk_cp(clk_cp),
.clk_frm(clk_frm),
.rst_n(rst_n),
.rst_for_new_package(rst_for_new_package),
.cmd(cmd),
.param(param),
.prn(prn),
.crc_check_pass(crc_check_pass),
.rd_data(rd_data),
.pre_p_complete(pre_p_complete),
.p_complete(p_complete),
.rd_complete(rd_complete)
);
// --- Pseudo Ramdon Number Generator ---
prng prng_1
(
.prn(prn),
.clk_prng(clk_prng),
.rst_n(rst_n)
);
// --- Memory Interface ---
mem_if mem_if_1
(
.rd_data(rd_data),
.rd_complete(rd_complete),
.A(A),
.CEN(CEN),
.addr(addr),
.Q(Q),
.clk_if(clk_mem),
.rst_for_new_package(rst_for_new_package)
);
// --- ROM (64 words, 16 bits per word) ---
rom_64x16 rom_64x16_1
(
.Q(Q),
.CLK(clk_mem),
.CEN(CEN),
.A(A)
);
// --- TX (including Frame Generator, FM0 Encoder, Miller Encoder) ---
tx tx_1
(
.bs_data(bs_data),
.pre_p_complete(pre_p_complete),
.p_complete(p_complete),
.bs_complete(bs_complete),
.clk_blf(clk_blf),
.clk_frm(clk_frm),
.clk_fm0(clk_fm0),
.clk_mil(clk_mil),
.rst_for_new_package(rst_for_new_package),
.reply_data(reply_data),
.crc_16(crc_16),
.m(m),
.trext(trext),
.reply_complete(reply_complete),
.en_crc16_for_rpy(en_crc16_for_rpy),
.start_working(start_working)
);
endmodule
|
module sonic_sensor(
input clk,
input rst,
input req,
output [0:0] busy,
inout sig,
output finish,
output [31:0] out_data
);
parameter STATE_INIT = 0,
STATE_IDLE = 1,
STATE_OUT_SIG = 2,
STATE_OUT_END = 3,
STATE_WAIT750 = 4,
STATE_IN_SIG_WAIT = 5,
STATE_IN_SIG = 6,
STATE_IN_SIG_END = 7,
STATE_WAIT200 = 8,
STATE_PROCESS_END = 9;
reg [3:0] state;
reg [31:0] echo;
reg [32:0] counter;
reg [31:0] result;
wire count_5u;
wire count_750u;
wire count_200u;
wire echo_fl;
reg busy_reg;
reg finish_reg;
//for debug
// assign count_5u = counter == 5;
// assign count_750u = counter == 75;
// assign count_200u = counter == 20;
// assign echo_fl = (counter > 100)? 1 : 0;
assign count_5u = counter == 499;
assign count_750u = counter == 74998;
assign count_200u = counter == 19999;
assign echo_fl = (echo == 1850000)? 1 : 0; // 18.5ms @ 100MHz
assign sig = (state == STATE_OUT_SIG)? 1 : 1'bZ;
assign busy = busy_reg;
assign finish = finish_reg;
always @(posedge clk)
begin
if(rst) begin
busy_reg <= 0;
finish_reg <= 0;
end
else
case(state)
STATE_INIT: begin
busy_reg <= 0;
finish_reg <= 0;
end
STATE_IDLE: begin
if(req)
busy_reg <= 1;
else begin
busy_reg <= 0;
finish_reg <= 0;
end
end
STATE_PROCESS_END: begin
busy_reg <= 0;
finish_reg <= 1;
end
endcase
end
//state unit
always @(posedge clk)
begin
if(rst)
state <= 0;
else case(state)
STATE_INIT: state <= STATE_IDLE;
STATE_IDLE: if(req) state <= STATE_OUT_SIG;
STATE_OUT_SIG:if(count_5u) state <= STATE_OUT_END;
STATE_OUT_END: state <= STATE_WAIT750;
STATE_WAIT750:if(count_750u) state <= STATE_IN_SIG_WAIT;
STATE_IN_SIG_WAIT: state <= STATE_IN_SIG;
STATE_IN_SIG:begin
if(echo_fl || sig == 0) state <= STATE_IN_SIG_END;
end
STATE_IN_SIG_END: state <= STATE_WAIT200;
STATE_WAIT200:if(count_200u) state <= STATE_PROCESS_END;
STATE_PROCESS_END: state <= STATE_IDLE;
default: state <= STATE_INIT;
endcase
end
//counter
always @(posedge clk)
begin
if(rst)
counter <= 0;
else
case(state)
STATE_OUT_SIG: counter <= counter + 1;
STATE_WAIT750: counter <= counter + 1;
STATE_IN_SIG : counter <= counter + 1;
STATE_WAIT200: counter <= counter + 1;
default: counter <= 0;
endcase
end
//output
always @(posedge clk)
begin
if(rst)
echo <= 0;
else if(state == STATE_IN_SIG)begin
echo <= echo + 1;
end
else if (state == STATE_PROCESS_END)
echo <= 0;
end
always @(posedge clk)begin
if(rst)
result <= 0;
else if(state == STATE_PROCESS_END)
result <= echo;
end
assign out_data = result[31:0];
endmodule
|
module dcfifo_32in_32out_16kb(rst, wr_clk, rd_clk, din, wr_en, rd_en, dout, full, empty, wr_data_count)
/* synthesis syn_black_box black_box_pad_pin="rst,wr_clk,rd_clk,din[31:0],wr_en,rd_en,dout[31:0],full,empty,wr_data_count[0:0]" */;
input rst;
input wr_clk;
input rd_clk;
input [31:0]din;
input wr_en;
input rd_en;
output [31:0]dout;
output full;
output empty;
output [0:0]wr_data_count;
endmodule
|
module prbs_gen #
(
parameter PRBS_WIDTH = 4
)
(
input clk,
input clk_en,
input rst,
output [PRBS_WIDTH-1:0] prbs_o
// output reg [3:0] prbs_shift_value
);
localparam PRBS_OFFSET = 0;
reg [PRBS_WIDTH - 1:0] Next_LFSR_Reg;
reg [PRBS_WIDTH - 1:0] LFSR_Reg;
reg [3:0] prbs_shift_value;
reg Bits_all, Feedback;
integer i;
always @ (posedge clk)
begin
if (rst )
LFSR_Reg <= {{PRBS_WIDTH-1{1'b0}},1'b1};
else if (clk_en) begin
if ( PRBS_OFFSET == 0)
// $display("prbs_value = 0x%h",LFSR_Reg);
LFSR_Reg <= Next_LFSR_Reg;
prbs_shift_value <= {prbs_shift_value[2:0],LFSR_Reg[PRBS_WIDTH-1]};
end
end
always @ (LFSR_Reg)
begin :LFSR_Next
Bits_all = ~| LFSR_Reg[PRBS_WIDTH-2:0];
Feedback = LFSR_Reg[PRBS_WIDTH-1]^Bits_all;
for (i = PRBS_WIDTH - 1; i >= 1 ; i = i-1)
Next_LFSR_Reg[i] = LFSR_Reg[i-1];
// Many to one feedback taps for 2^n sequence
// 4 logic levels required for PRBS_WIDTH = 64
case (PRBS_WIDTH)
32'd4:
Next_LFSR_Reg[0] = Feedback^LFSR_Reg[2];
32'd8:
Next_LFSR_Reg[0] = Feedback^LFSR_Reg[3]^LFSR_Reg[4]^LFSR_Reg[5];
32'd10:
Next_LFSR_Reg[0] = Feedback^LFSR_Reg[6];
32'd14:
Next_LFSR_Reg[0] = Feedback^LFSR_Reg[0]^LFSR_Reg[2]^LFSR_Reg[4];
32'd24:
Next_LFSR_Reg[0] = Feedback^LFSR_Reg[16]^LFSR_Reg[21]^LFSR_Reg[22];
32'd32:
Next_LFSR_Reg[0] = Feedback^LFSR_Reg[0]^LFSR_Reg[1]^LFSR_Reg[21];
32'd42:
Next_LFSR_Reg[0] = Feedback^LFSR_Reg[18]^LFSR_Reg[19]^LFSR_Reg[40];
32'd56:
Next_LFSR_Reg[0] = Feedback^LFSR_Reg[33]^LFSR_Reg[34]^LFSR_Reg[54];
32'd64:
Next_LFSR_Reg[0] = Feedback^LFSR_Reg[59]^LFSR_Reg[60]^LFSR_Reg[62];
32'd72:
Next_LFSR_Reg[0] = Feedback^LFSR_Reg[18]^LFSR_Reg[24]^LFSR_Reg[65];
default:
Next_LFSR_Reg[0] = Feedback^LFSR_Reg[59]^LFSR_Reg[60]^LFSR_Reg[62];
endcase
end
assign prbs_o = LFSR_Reg;
endmodule
|
module sky130_fd_sc_lp__a41oi (
Y ,
A1,
A2,
A3,
A4,
B1
);
// Module ports
output Y ;
input A1;
input A2;
input A3;
input A4;
input B1;
// Local signals
wire and0_out ;
wire nor0_out_Y;
// Name Output Other arguments
and and0 (and0_out , A1, A2, A3, A4 );
nor nor0 (nor0_out_Y, B1, and0_out );
buf buf0 (Y , nor0_out_Y );
endmodule
|
module bomb (
address,
clock,
q);
input [11:0] address;
input clock;
output [11:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [11:0] sub_wire0;
wire [11:0] q = sub_wire0[11:0];
altsyncram altsyncram_component (
.address_a (address),
.clock0 (clock),
.q_a (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.address_b (1'b1),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_a ({12{1'b1}}),
.data_b (1'b1),
.eccstatus (),
.q_b (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_a (1'b0),
.wren_b (1'b0));
defparam
altsyncram_component.address_aclr_a = "NONE",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.init_file = "../sprites-new/bomb.mif",
altsyncram_component.intended_device_family = "Cyclone V",
altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 4096,
altsyncram_component.operation_mode = "ROM",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_reg_a = "UNREGISTERED",
altsyncram_component.widthad_a = 12,
altsyncram_component.width_a = 12,
altsyncram_component.width_byteena_a = 1;
endmodule
|
module to external system
);
//// BEGIN Wire declarations made by MVP
//wire [`M14K_UDI_EXT_FROMUDI_WIDTH-1:0] /*[0:0]*/ UDI_fromudi ;
//// END Wire declarations made by MVP
wire [31:0] udi_res ;
wire [1:0] udi_ctl_sum_mode_d ; //0- none 1- + 2- +>> 3- bypass
wire udi_ctl_res_sel_d ; //1- comparing
wire udi_ctl_thr_wr ; //1- wr_thr
wire [1:0] udi_ctl_sum_mode ; //0- none 1- + 2- +>> 3- bypass
wire udi_ctl_res_sel ; //1- comparing
wire udi_stall ;
wire udi_stall_1 ;
wire udi_stall_1_d ;
wire udi_stall_2_d ;
wire udi_stall_dd ;
localparam UDI_MAJ_OP = 6'd28 ; //RD = RS[31:16]^2 + RT[31:16]^2
localparam UDI_0 = 6'd16 ; //RD = RS[31:16]^2 + RT[31:16]^2
localparam UDI_1 = 6'd17 ; //RD = (RS[31:16]^2 + RT[31:16]^2) >> 1
localparam UDI_2 = 6'd18 ; //RD = RS[31:16]^2
localparam UDI_3 = 6'd19 ; //stored_threshold = RS
localparam UDI_4 = 6'd20 ; //RD = ( (RS[31:16]^2 + RT[31:16]^2) > stored_threshold ) ? 1 : 0
localparam UDI_5 = 6'd21 ; //RD = ( ((RS[31:16]^2 + RT[31:16]^2) >> 1) > stored_threshold ) ? 1 : 0
localparam UDI_6 = 6'd22 ; //RD = (RS[31:16]^2 > stored_threshold ) ? 1 : 0
localparam CTL_THR_WR_OFF = 1'b0 ;
localparam CTL_THR_WR_ON = 1'b1 ;
localparam CTL_SUM_MODE_NONE = 2'b00 ;
localparam CTL_SUM_MODE_SUM = 2'b01 ;
localparam CTL_SUM_MODE_SUMSHIFT = 2'b10 ;
localparam CTL_SUM_MODE_BYPASS = 2'b11 ;
localparam CTL_RES_CALC = 1'b0 ;
localparam CTL_RES_COMP = 1'b1 ;
assign UDI_fromudi[`M14K_UDI_EXT_FROMUDI_WIDTH-1:0] = {`M14K_UDI_EXT_FROMUDI_WIDTH{1'b0}} ;
assign UDI_ri_e = (UDI_irvalid_e && UDI_ir_e[31:26] == UDI_MAJ_OP && UDI_ir_e[5:4] == 2'b01 &&
( UDI_ir_e[5:0] != UDI_0 &&
UDI_ir_e[5:0] != UDI_1 &&
UDI_ir_e[5:0] != UDI_2 &&
UDI_ir_e[5:0] != UDI_3 &&
UDI_ir_e[5:0] != UDI_4 &&
UDI_ir_e[5:0] != UDI_5 &&
UDI_ir_e[5:0] != UDI_6
)
) ? 1'b1 : 1'b0 ; // Illegal Spec2 Instn.
assign UDI_present = 1'b1 ;
assign UDI_honor_cee = 1'b0 ;
assign UDI_rd_m = udi_res ;
assign UDI_wrreg_e = (UDI_ir_e[5:0] == UDI_3) ? 5'd0 : UDI_ir_e[15:11] ;
assign udi_ctl_thr_wr = (UDI_irvalid_e && UDI_ir_e[31:26] == UDI_MAJ_OP && UDI_ir_e[5:0] == UDI_3) ? CTL_THR_WR_ON : CTL_THR_WR_OFF ;
assign udi_ctl_sum_mode = (UDI_irvalid_e && UDI_ir_e[31:26] == UDI_MAJ_OP && (UDI_ir_e[5:0] == UDI_0 || UDI_ir_e[5:0] == UDI_4))
? CTL_SUM_MODE_SUM : (UDI_irvalid_e && UDI_ir_e[31:26] == UDI_MAJ_OP && (UDI_ir_e[5:0] == UDI_1 || UDI_ir_e[5:0] == UDI_5))
? CTL_SUM_MODE_SUMSHIFT : (UDI_irvalid_e && UDI_ir_e[31:26] == UDI_MAJ_OP && (UDI_ir_e[5:0] == UDI_2 || UDI_ir_e[5:0] == UDI_6))
? CTL_SUM_MODE_BYPASS : CTL_SUM_MODE_NONE ;
assign udi_ctl_res_sel = (UDI_irvalid_e && UDI_ir_e[31:26] == UDI_MAJ_OP &&
(UDI_ir_e[5:0] == UDI_0 || UDI_ir_e[5:0] == UDI_1 || UDI_ir_e[5:0] == UDI_2 || UDI_ir_e[5:0] == UDI_3))
? CTL_RES_CALC : CTL_RES_COMP ;
assign UDI_stall_m = ~UDI_kill_m & (udi_stall_1_d | udi_stall_dd) ;
assign udi_stall_1 = (UDI_ir_e[5:0] == UDI_2 || UDI_ir_e[5:0] == UDI_6) ? 1'b0 : 1'b1 ;
assign udi_stall = (UDI_irvalid_e && UDI_ir_e[31:26] == UDI_MAJ_OP && UDI_ir_e[5:4] == 2'b01 &&
( UDI_ir_e[5:0] == UDI_0 ||
UDI_ir_e[5:0] == UDI_1 ||
UDI_ir_e[5:0] == UDI_2 ||
UDI_ir_e[5:0] == UDI_4 ||
UDI_ir_e[5:0] == UDI_5 ||
UDI_ir_e[5:0] == UDI_6
)
) ? 1'b1 : 1'b0 ;
udi_inst_pow udi_inst_pow_u(
.gclk ( UDI_gclk ), //input
.gscanenable ( UDI_gscanenable ), //input
.in_rs ( UDI_rs_e ), //input [31:0]
.in_rt ( UDI_rt_e[31:16] ), //input [15:0]
.out_rd ( udi_res ), //output [31:0]
.udi_ctl_thr_wr ( udi_ctl_thr_wr ), //input
.udi_ctl_sum_mode ( udi_ctl_sum_mode_d ), //input [1:0]
.udi_ctl_res_sel ( udi_ctl_res_sel_d ) //input
);
mvp_cregister_wide #(2) _udi_ctl_sum_mode_1_0_(udi_ctl_sum_mode_d,UDI_gscanenable, (UDI_irvalid_e && UDI_ir_e[31:26] == UDI_MAJ_OP), UDI_gclk, udi_ctl_sum_mode);
mvp_cregister_wide #(1) _udi_ctl_res_sel_(udi_ctl_res_sel_d,UDI_gscanenable, (UDI_irvalid_e && UDI_ir_e[31:26] == UDI_MAJ_OP), UDI_gclk, udi_ctl_res_sel);
mvp_register #(1) _udi_stall_0_(udi_stall_1_d, UDI_gclk, udi_stall);
mvp_register #(1) _udi_stall_1_(udi_stall_2_d, UDI_gclk, udi_stall_1);
mvp_register #(1) _udi_stall_2_(udi_stall_dd, UDI_gclk, udi_stall_1_d & udi_stall_2_d);
endmodule
|
module txuart #(
// {{{
parameter [30:0] INITIAL_SETUP = 31'd868,
//
localparam [3:0] TXU_BIT_ZERO = 4'h0,
localparam [3:0] TXU_BIT_ONE = 4'h1,
localparam [3:0] TXU_BIT_TWO = 4'h2,
localparam [3:0] TXU_BIT_THREE = 4'h3,
// localparam [3:0] TXU_BIT_FOUR = 4'h4,
// localparam [3:0] TXU_BIT_FIVE = 4'h5,
// localparam [3:0] TXU_BIT_SIX = 4'h6,
localparam [3:0] TXU_BIT_SEVEN = 4'h7,
localparam [3:0] TXU_PARITY = 4'h8,
localparam [3:0] TXU_STOP = 4'h9,
localparam [3:0] TXU_SECOND_STOP = 4'ha,
//
localparam [3:0] TXU_BREAK = 4'he,
localparam [3:0] TXU_IDLE = 4'hf
// }}}
) (
// {{{
input wire i_clk, i_reset,
input wire [30:0] i_setup,
input wire i_break,
input wire i_wr,
input wire [7:0] i_data,
// Hardware flow control Ready-To-Send bit. Set this to one to
// use the core without flow control. (A more appropriate name
// would be the Ready-To-Receive bit ...)
input wire i_cts_n,
// And the UART input line itself
output reg o_uart_tx,
// A line to tell others when we are ready to accept data. If
// (i_wr)&&(!o_busy) is ever true, then the core has accepted a
// byte for transmission.
output wire o_busy
// }}}
);
// Signal declarations
// {{{
wire [27:0] clocks_per_baud, break_condition;
wire [1:0] i_data_bits, data_bits;
wire use_parity, parity_odd, dblstop, fixd_parity,
fixdp_value, hw_flow_control, i_parity_odd;
reg [30:0] r_setup;
assign clocks_per_baud = { 4'h0, r_setup[23:0] };
assign break_condition = { r_setup[23:0], 4'h0 };
assign hw_flow_control = !r_setup[30];
assign i_data_bits = i_setup[29:28];
assign data_bits = r_setup[29:28];
assign dblstop = r_setup[27];
assign use_parity = r_setup[26];
assign fixd_parity = r_setup[25];
assign i_parity_odd = i_setup[24];
assign parity_odd = r_setup[24];
assign fixdp_value = r_setup[24];
reg [27:0] baud_counter;
reg [3:0] state;
reg [7:0] lcl_data;
reg calc_parity, r_busy, zero_baud_counter, last_state;
reg q_cts_n, qq_cts_n, ck_cts;
// }}}
// CTS: ck_cts
// {{{
// First step ... handle any hardware flow control, if so enabled.
//
// Clock in the flow control data, two clocks to avoid metastability
// Default to using hardware flow control (uart_setup[30]==0 to use it).
// Set this high order bit off if you do not wish to use it.
//
// While we might wish to give initial values to q_rts and ck_cts,
// 1) it's not required since the transmitter starts in a long wait
// state, and 2) doing so will prevent the synthesizer from optimizing
// this pin in the case it is hard set to 1'b1 external to this
// peripheral.
//
// initial q_cts_n = 1'b1;
// initial qq_cts_n = 1'b1;
// initial ck_cts = 1'b0;
always @(posedge i_clk)
{ qq_cts_n, q_cts_n } <= { q_cts_n, i_cts_n };
always @(posedge i_clk)
ck_cts <= (!qq_cts_n)||(!hw_flow_control);
// }}}
// r_busy, state
// {{{
initial r_busy = 1'b1;
initial state = TXU_IDLE;
always @(posedge i_clk)
if (i_reset)
begin
r_busy <= 1'b1;
state <= TXU_IDLE;
end else if (i_break)
begin
state <= TXU_BREAK;
r_busy <= 1'b1;
end else if (!zero_baud_counter)
begin // r_busy needs to be set coming into here
r_busy <= 1'b1;
end else if (state == TXU_BREAK)
begin
state <= TXU_IDLE;
r_busy <= !ck_cts;
end else if (state == TXU_IDLE) // STATE_IDLE
begin
if ((i_wr)&&(!r_busy))
begin // Immediately start us off with a start bit
r_busy <= 1'b1;
case(i_data_bits)
2'b00: state <= TXU_BIT_ZERO;
2'b01: state <= TXU_BIT_ONE;
2'b10: state <= TXU_BIT_TWO;
2'b11: state <= TXU_BIT_THREE;
endcase
end else begin // Stay in idle
r_busy <= !ck_cts;
end
end else begin
// One clock tick in each of these states ...
// baud_counter <= clocks_per_baud - 28'h01;
r_busy <= 1'b1;
if (state[3] == 0) // First 8 bits
begin
if (state == TXU_BIT_SEVEN)
state <= (use_parity)? TXU_PARITY:TXU_STOP;
else
state <= state + 1;
end else if (state == TXU_PARITY)
begin
state <= TXU_STOP;
end else if (state == TXU_STOP)
begin // two stop bit(s)
if (dblstop)
state <= TXU_SECOND_STOP;
else
state <= TXU_IDLE;
end else // `TXU_SECOND_STOP and default:
begin
state <= TXU_IDLE; // Go back to idle
// Still r_busy, since we need to wait
// for the baud clock to finish counting
// out this last bit.
end
end
// }}}
// o_busy
// {{{
// This is a wire, designed to be true is we are ever busy above.
// originally, this was going to be true if we were ever not in the
// idle state. The logic has since become more complex, hence we have
// a register dedicated to this and just copy out that registers value.
assign o_busy = (r_busy);
// }}}
// r_setup
// {{{
// Our setup register. Accept changes between any pair of transmitted
// words. The register itself has many fields to it. These are
// broken out up top, and indicate what 1) our baud rate is, 2) our
// number of stop bits, 3) what type of parity we are using, and 4)
// the size of our data word.
initial r_setup = INITIAL_SETUP;
always @(posedge i_clk)
if (!o_busy)
r_setup <= i_setup;
// }}}
// lcl_data
// {{{
// This is our working copy of the i_data register which we use
// when transmitting. It is only of interest during transmit, and is
// allowed to be whatever at any other time. Hence, if r_busy isn't
// true, we can always set it. On the one clock where r_busy isn't
// true and i_wr is, we set it and r_busy is true thereafter.
// Then, on any zero_baud_counter (i.e. change between baud intervals)
// we simple logically shift the register right to grab the next bit.
initial lcl_data = 8'hff;
always @(posedge i_clk)
if (!r_busy)
lcl_data <= i_data;
else if (zero_baud_counter)
lcl_data <= { 1'b0, lcl_data[7:1] };
// }}}
// o_uart_tx
// {{{
// This is the final result/output desired of this core. It's all
// centered about o_uart_tx. This is what finally needs to follow
// the UART protocol.
//
// Ok, that said, our rules are:
// 1'b0 on any break condition
// 1'b0 on a start bit (IDLE, write, and not busy)
// lcl_data[0] during any data transfer, but only at the baud
// change
// PARITY -- During the parity bit. This depends upon whether or
// not the parity bit is fixed, then what it's fixed to,
// or changing, and hence what it's calculated value is.
// 1'b1 at all other times (stop bits, idle, etc)
initial o_uart_tx = 1'b1;
always @(posedge i_clk)
if (i_reset)
o_uart_tx <= 1'b1;
else if ((i_break)||((i_wr)&&(!r_busy)))
o_uart_tx <= 1'b0;
else if (zero_baud_counter)
casez(state)
4'b0???: o_uart_tx <= lcl_data[0];
TXU_PARITY: o_uart_tx <= calc_parity;
default: o_uart_tx <= 1'b1;
endcase
// }}}
// calc_parity
// {{{
// Calculate the parity to be placed into the parity bit. If the
// parity is fixed, then the parity bit is given by the fixed parity
// value (r_setup[24]). Otherwise the parity is given by the GF2
// sum of all the data bits (plus one for even parity).
initial calc_parity = 1'b0;
always @(posedge i_clk)
if (!o_busy)
calc_parity <= i_setup[24];
else if (fixd_parity)
calc_parity <= fixdp_value;
else if (zero_baud_counter)
begin
if (state[3] == 0) // First 8 bits of msg
calc_parity <= calc_parity ^ lcl_data[0];
else if (state == TXU_IDLE)
calc_parity <= parity_odd;
end else if (!r_busy)
calc_parity <= parity_odd;
// }}}
// baud_counter, zero_baud_counter
// {{{
// All of the above logic is driven by the baud counter. Bits must last
// {{{
// clocks_per_baud in length, and this baud counter is what we use to
// make certain of that.
//
// The basic logic is this: at the beginning of a bit interval, start
// the baud counter and set it to count clocks_per_baud. When it gets
// to zero, restart it.
//
// However, comparing a 28'bit number to zero can be rather complex--
// especially if we wish to do anything else on that same clock. For
// that reason, we create "zero_baud_counter". zero_baud_counter is
// nothing more than a flag that is true anytime baud_counter is zero.
// It's true when the logic (above) needs to step to the next bit.
// Simple enough?
//
// I wish we could stop there, but there are some other (ugly)
// conditions to deal with that offer exceptions to this basic logic.
//
// 1. When the user has commanded a BREAK across the line, we need to
// wait several baud intervals following the break before we start
// transmitting, to give any receiver a chance to recognize that we are
// out of the break condition, and to know that the next bit will be
// a stop bit.
//
// 2. A reset is similar to a break condition--on both we wait several
// baud intervals before allowing a start bit.
//
// 3. In the idle state, we stop our counter--so that upon a request
// to transmit when idle we can start transmitting immediately, rather
// than waiting for the end of the next (fictitious and arbitrary) baud
// interval.
//
// When (i_wr)&&(!r_busy)&&(state == TXU_IDLE) then we're not only in
// the idle state, but we also just accepted a command to start writing
// the next word. At this point, the baud counter needs to be reset
// to the number of clocks per baud, and zero_baud_counter set to zero.
//
// The logic is a bit twisted here, in that it will only check for the
// above condition when zero_baud_counter is false--so as to make
// certain the STOP bit is complete.
// }}}
initial zero_baud_counter = 1'b0;
initial baud_counter = 28'h05;
always @(posedge i_clk)
begin
zero_baud_counter <= (baud_counter == 28'h01);
if ((i_reset)||(i_break))
begin
// Give ourselves 16 bauds before being ready
baud_counter <= break_condition;
zero_baud_counter <= 1'b0;
end else if (!zero_baud_counter)
baud_counter <= baud_counter - 28'h01;
else if (state == TXU_BREAK)
begin
baud_counter <= 0;
zero_baud_counter <= 1'b1;
end else if (state == TXU_IDLE)
begin
baud_counter <= 28'h0;
zero_baud_counter <= 1'b1;
if ((i_wr)&&(!r_busy))
begin
baud_counter <= { 4'h0, i_setup[23:0]} - 28'h01;
zero_baud_counter <= 1'b0;
end
end else if (last_state)
baud_counter <= clocks_per_baud - 28'h02;
else
baud_counter <= clocks_per_baud - 28'h01;
end
// }}}
// last_state
// {{{
initial last_state = 1'b0;
always @(posedge i_clk)
if (dblstop)
last_state <= (state == TXU_SECOND_STOP);
else
last_state <= (state == TXU_STOP);
// }}}
// Make Verilator happy
// {{{
// Verilator lint_off UNUSED
wire unused;
assign unused = &{ 1'b0, i_parity_odd, data_bits };
// Verilator lint_on UNUSED
// }}}
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
//
// Formal properties
// {{{
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
`ifdef FORMAL
// Declarations
// {{{
reg fsv_parity;
reg [30:0] fsv_setup;
reg [7:0] fsv_data;
reg f_past_valid;
//
// Our various sequence data declarations
reg [5:0] f_five_seq;
reg [6:0] f_six_seq;
reg [7:0] f_seven_seq;
reg [8:0] f_eight_seq;
reg [2:0] f_stop_seq; // parity bit, stop bit, double stop bit
// }}}
initial f_past_valid = 1'b0;
always @(posedge i_clk)
f_past_valid <= 1'b1;
always @(posedge i_clk)
if ((i_wr)&&(!o_busy))
fsv_data <= i_data;
initial fsv_setup = INITIAL_SETUP;
always @(posedge i_clk)
if (!o_busy)
fsv_setup <= i_setup;
always @(*)
assert(r_setup == fsv_setup);
always @(posedge i_clk)
assert(zero_baud_counter == (baud_counter == 0));
always @(*)
if (!o_busy)
assert(zero_baud_counter);
/*
*
* Will only pass if !i_break && !i_reset, otherwise the setup can
* change in the middle of this operation
*
always @(posedge i_clk)
if ((f_past_valid)&&(!$past(i_reset))&&(!$past(i_break))
&&(($past(o_busy))||($past(i_wr))))
assert(baud_counter <= { fsv_setup[23:0], 4'h0 });
*/
// A single baud interval
always @(posedge i_clk)
if ((f_past_valid)&&(!$past(zero_baud_counter))
&&(!$past(i_reset))&&(!$past(i_break)))
begin
assert($stable(o_uart_tx));
assert($stable(state));
assert($stable(lcl_data));
if ((state != TXU_IDLE)&&(state != TXU_BREAK))
assert($stable(calc_parity));
assert(baud_counter == $past(baud_counter)-1'b1);
end
//
// One byte transmitted
//
// DATA = the byte that is sent
// CKS = the number of clocks per bit
//
////////////////////////////////////////////////////////////////////////
//
// Five bit data
// {{{
////////////////////////////////////////////////////////////////////////
//
//
initial f_five_seq = 0;
always @(posedge i_clk)
if ((i_reset)||(i_break))
f_five_seq = 0;
else if ((state == TXU_IDLE)&&(i_wr)&&(!o_busy)
&&(i_data_bits == 2'b11)) // five data bits
f_five_seq <= 1;
else if (zero_baud_counter)
f_five_seq <= f_five_seq << 1;
always @(*)
if (|f_five_seq)
begin
assert(fsv_setup[29:28] == data_bits);
assert(data_bits == 2'b11);
assert(baud_counter < fsv_setup[23:0]);
assert(1'b0 == |f_six_seq);
assert(1'b0 == |f_seven_seq);
assert(1'b0 == |f_eight_seq);
assert(r_busy);
assert(state > 4'h2);
end
always @(*)
case(f_five_seq)
6'h00: begin assert(1); end
6'h01: begin
assert(state == 4'h3);
assert(o_uart_tx == 1'b0);
assert(lcl_data[4:0] == fsv_data[4:0]);
if (!fixd_parity)
assert(calc_parity == parity_odd);
end
6'h02: begin
assert(state == 4'h4);
assert(o_uart_tx == fsv_data[0]);
assert(lcl_data[3:0] == fsv_data[4:1]);
if (!fixd_parity)
assert(calc_parity == fsv_data[0] ^ parity_odd);
end
6'h04: begin
assert(state == 4'h5);
assert(o_uart_tx == fsv_data[1]);
assert(lcl_data[2:0] == fsv_data[4:2]);
if (!fixd_parity)
assert(calc_parity == (^fsv_data[1:0]) ^ parity_odd);
end
6'h08: begin
assert(state == 4'h6);
assert(o_uart_tx == fsv_data[2]);
assert(lcl_data[1:0] == fsv_data[4:3]);
if (!fixd_parity)
assert(calc_parity == (^fsv_data[2:0]) ^ parity_odd);
end
6'h10: begin
assert(state == 4'h7);
assert(o_uart_tx == fsv_data[3]);
assert(lcl_data[0] == fsv_data[4]);
if (!fixd_parity)
assert(calc_parity == (^fsv_data[3:0]) ^ parity_odd);
end
6'h20: begin
if (use_parity)
assert(state == 4'h8);
else
assert(state == 4'h9);
assert(o_uart_tx == fsv_data[4]);
if (!fixd_parity)
assert(calc_parity == (^fsv_data[4:0]) ^ parity_odd);
end
default: begin assert(0); end
endcase
// }}}
////////////////////////////////////////////////////////////////////////
//
// Six bit data
// {{{
////////////////////////////////////////////////////////////////////////
//
//
initial f_six_seq = 0;
always @(posedge i_clk)
if ((i_reset)||(i_break))
f_six_seq = 0;
else if ((state == TXU_IDLE)&&(i_wr)&&(!o_busy)
&&(i_data_bits == 2'b10)) // six data bits
f_six_seq <= 1;
else if (zero_baud_counter)
f_six_seq <= f_six_seq << 1;
always @(*)
if (|f_six_seq)
begin
assert(fsv_setup[29:28] == 2'b10);
assert(fsv_setup[29:28] == data_bits);
assert(baud_counter < fsv_setup[23:0]);
assert(1'b0 == |f_five_seq);
assert(1'b0 == |f_seven_seq);
assert(1'b0 == |f_eight_seq);
assert(r_busy);
assert(state > 4'h1);
end
always @(*)
case(f_six_seq)
7'h00: begin assert(1); end
7'h01: begin
assert(state == 4'h2);
assert(o_uart_tx == 1'b0);
assert(lcl_data[5:0] == fsv_data[5:0]);
if (!fixd_parity)
assert(calc_parity == parity_odd);
end
7'h02: begin
assert(state == 4'h3);
assert(o_uart_tx == fsv_data[0]);
assert(lcl_data[4:0] == fsv_data[5:1]);
if (!fixd_parity)
assert(calc_parity == fsv_data[0] ^ parity_odd);
end
7'h04: begin
assert(state == 4'h4);
assert(o_uart_tx == fsv_data[1]);
assert(lcl_data[3:0] == fsv_data[5:2]);
if (!fixd_parity)
assert(calc_parity == (^fsv_data[1:0]) ^ parity_odd);
end
7'h08: begin
assert(state == 4'h5);
assert(o_uart_tx == fsv_data[2]);
assert(lcl_data[2:0] == fsv_data[5:3]);
if (!fixd_parity)
assert(calc_parity == (^fsv_data[2:0]) ^ parity_odd);
end
7'h10: begin
assert(state == 4'h6);
assert(o_uart_tx == fsv_data[3]);
assert(lcl_data[1:0] == fsv_data[5:4]);
if (!fixd_parity)
assert(calc_parity == (^fsv_data[3:0]) ^ parity_odd);
end
7'h20: begin
assert(state == 4'h7);
assert(lcl_data[0] == fsv_data[5]);
assert(o_uart_tx == fsv_data[4]);
if (!fixd_parity)
assert(calc_parity == ((^fsv_data[4:0]) ^ parity_odd));
end
7'h40: begin
if (use_parity)
assert(state == 4'h8);
else
assert(state == 4'h9);
assert(o_uart_tx == fsv_data[5]);
if (!fixd_parity)
assert(calc_parity == ((^fsv_data[5:0]) ^ parity_odd));
end
default: begin if (f_past_valid) assert(0); end
endcase
// }}}
////////////////////////////////////////////////////////////////////////
//
// Seven bit data
// {{{
////////////////////////////////////////////////////////////////////////
//
//
initial f_seven_seq = 0;
always @(posedge i_clk)
if ((i_reset)||(i_break))
f_seven_seq = 0;
else if ((state == TXU_IDLE)&&(i_wr)&&(!o_busy)
&&(i_data_bits == 2'b01)) // seven data bits
f_seven_seq <= 1;
else if (zero_baud_counter)
f_seven_seq <= f_seven_seq << 1;
always @(*)
if (|f_seven_seq)
begin
assert(fsv_setup[29:28] == 2'b01);
assert(fsv_setup[29:28] == data_bits);
assert(baud_counter < fsv_setup[23:0]);
assert(1'b0 == |f_five_seq);
assert(1'b0 == |f_six_seq);
assert(1'b0 == |f_eight_seq);
assert(r_busy);
assert(state != 4'h0);
end
always @(*)
case(f_seven_seq)
8'h00: begin assert(1); end
8'h01: begin
assert(state == 4'h1);
assert(o_uart_tx == 1'b0);
assert(lcl_data[6:0] == fsv_data[6:0]);
if (!fixd_parity)
assert(calc_parity == parity_odd);
end
8'h02: begin
assert(state == 4'h2);
assert(o_uart_tx == fsv_data[0]);
assert(lcl_data[5:0] == fsv_data[6:1]);
if (!fixd_parity)
assert(calc_parity == fsv_data[0] ^ parity_odd);
end
8'h04: begin
assert(state == 4'h3);
assert(o_uart_tx == fsv_data[1]);
assert(lcl_data[4:0] == fsv_data[6:2]);
if (!fixd_parity)
assert(calc_parity == (^fsv_data[1:0]) ^ parity_odd);
end
8'h08: begin
assert(state == 4'h4);
assert(o_uart_tx == fsv_data[2]);
assert(lcl_data[3:0] == fsv_data[6:3]);
if (!fixd_parity)
assert(calc_parity == (^fsv_data[2:0]) ^ parity_odd);
end
8'h10: begin
assert(state == 4'h5);
assert(o_uart_tx == fsv_data[3]);
assert(lcl_data[2:0] == fsv_data[6:4]);
if (!fixd_parity)
assert(calc_parity == (^fsv_data[3:0]) ^ parity_odd);
end
8'h20: begin
assert(state == 4'h6);
assert(o_uart_tx == fsv_data[4]);
assert(lcl_data[1:0] == fsv_data[6:5]);
if (!fixd_parity)
assert(calc_parity == ((^fsv_data[4:0]) ^ parity_odd));
end
8'h40: begin
assert(state == 4'h7);
assert(lcl_data[0] == fsv_data[6]);
assert(o_uart_tx == fsv_data[5]);
if (!fixd_parity)
assert(calc_parity == ((^fsv_data[5:0]) ^ parity_odd));
end
8'h80: begin
if (use_parity)
assert(state == 4'h8);
else
assert(state == 4'h9);
assert(o_uart_tx == fsv_data[6]);
if (!fixd_parity)
assert(calc_parity == ((^fsv_data[6:0]) ^ parity_odd));
end
default: begin if (f_past_valid) assert(0); end
endcase
// }}}
////////////////////////////////////////////////////////////////////////
//
// Eight bit data
// {{{
////////////////////////////////////////////////////////////////////////
initial f_eight_seq = 0;
always @(posedge i_clk)
if ((i_reset)||(i_break))
f_eight_seq = 0;
else if ((state == TXU_IDLE)&&(i_wr)&&(!o_busy)
&&(i_data_bits == 2'b00)) // Eight data bits
f_eight_seq <= 1;
else if (zero_baud_counter)
f_eight_seq <= f_eight_seq << 1;
always @(*)
if (|f_eight_seq)
begin
assert(fsv_setup[29:28] == 2'b00);
assert(fsv_setup[29:28] == data_bits);
assert(baud_counter < { 6'h0, fsv_setup[23:0]});
assert(1'b0 == |f_five_seq);
assert(1'b0 == |f_six_seq);
assert(1'b0 == |f_seven_seq);
assert(r_busy);
end
always @(*)
case(f_eight_seq)
9'h000: begin assert(1); end
9'h001: begin
assert(state == 4'h0);
assert(o_uart_tx == 1'b0);
assert(lcl_data[7:0] == fsv_data[7:0]);
if (!fixd_parity)
assert(calc_parity == parity_odd);
end
9'h002: begin
assert(state == 4'h1);
assert(o_uart_tx == fsv_data[0]);
assert(lcl_data[6:0] == fsv_data[7:1]);
if (!fixd_parity)
assert(calc_parity == fsv_data[0] ^ parity_odd);
end
9'h004: begin
assert(state == 4'h2);
assert(o_uart_tx == fsv_data[1]);
assert(lcl_data[5:0] == fsv_data[7:2]);
if (!fixd_parity)
assert(calc_parity == (^fsv_data[1:0]) ^ parity_odd);
end
9'h008: begin
assert(state == 4'h3);
assert(o_uart_tx == fsv_data[2]);
assert(lcl_data[4:0] == fsv_data[7:3]);
if (!fixd_parity)
assert(calc_parity == (^fsv_data[2:0]) ^ parity_odd);
end
9'h010: begin
assert(state == 4'h4);
assert(o_uart_tx == fsv_data[3]);
assert(lcl_data[3:0] == fsv_data[7:4]);
if (!fixd_parity)
assert(calc_parity == (^fsv_data[3:0]) ^ parity_odd);
end
9'h020: begin
assert(state == 4'h5);
assert(o_uart_tx == fsv_data[4]);
assert(lcl_data[2:0] == fsv_data[7:5]);
if (!fixd_parity)
assert(calc_parity == (^fsv_data[4:0]) ^ parity_odd);
end
9'h040: begin
assert(state == 4'h6);
assert(o_uart_tx == fsv_data[5]);
assert(lcl_data[1:0] == fsv_data[7:6]);
if (!fixd_parity)
assert(calc_parity == (^fsv_data[5:0]) ^ parity_odd);
end
9'h080: begin
assert(state == 4'h7);
assert(o_uart_tx == fsv_data[6]);
assert(lcl_data[0] == fsv_data[7]);
if (!fixd_parity)
assert(calc_parity == ((^fsv_data[6:0]) ^ parity_odd));
end
9'h100: begin
if (use_parity)
assert(state == 4'h8);
else
assert(state == 4'h9);
assert(o_uart_tx == fsv_data[7]);
if (!fixd_parity)
assert(calc_parity == ((^fsv_data[7:0]) ^ parity_odd));
end
default: begin if (f_past_valid) assert(0); end
endcase
// }}}
////////////////////////////////////////////////////////////////////////
//
// Combined properties for all of the data sequences
// {{{
////////////////////////////////////////////////////////////////////////
//
always @(posedge i_clk)
if (((|f_five_seq[5:0]) || (|f_six_seq[6:0]) || (|f_seven_seq[7:0])
|| (|f_eight_seq[8:0]))
&& ($past(zero_baud_counter)))
assert(baud_counter == { 4'h0, fsv_setup[23:0] }-1);
// }}}
////////////////////////////////////////////////////////////////////////
//
// The stop sequence
// {{{
////////////////////////////////////////////////////////////////////////
//
// This consists of any parity bit, as well as one or two stop bits
//
initial f_stop_seq = 1'b0;
always @(posedge i_clk)
if ((i_reset)||(i_break))
f_stop_seq <= 0;
else if (zero_baud_counter)
begin
f_stop_seq <= 0;
if (f_stop_seq[0]) // Coming from a parity bit
begin
if (dblstop)
f_stop_seq[1] <= 1'b1;
else
f_stop_seq[2] <= 1'b1;
end
if (f_stop_seq[1])
f_stop_seq[2] <= 1'b1;
if (f_eight_seq[8] | f_seven_seq[7] | f_six_seq[6]
| f_five_seq[5])
begin
if (use_parity)
f_stop_seq[0] <= 1'b1;
else if (dblstop)
f_stop_seq[1] <= 1'b1;
else
f_stop_seq[2] <= 1'b1;
end
end
always @(*)
if (|f_stop_seq)
begin
assert(1'b0 == |f_five_seq[4:0]);
assert(1'b0 == |f_six_seq[5:0]);
assert(1'b0 == |f_seven_seq[6:0]);
assert(1'b0 == |f_eight_seq[7:0]);
assert(r_busy);
end
always @(*)
if (f_stop_seq[0])
begin
// 9 if dblstop and use_parity
if (dblstop)
assert(state == TXU_STOP);
else
assert(state == TXU_STOP);
assert(use_parity);
assert(o_uart_tx == fsv_parity);
end
always @(*)
if (f_stop_seq[1])
begin
// if (!use_parity)
assert(state == TXU_SECOND_STOP);
assert(dblstop);
assert(o_uart_tx);
end
always @(*)
if (f_stop_seq[2])
begin
assert(state == 4'hf);
assert(o_uart_tx);
assert(baud_counter < fsv_setup[23:0]-1'b1);
end
always @(*)
if (fsv_setup[25])
fsv_parity <= fsv_setup[24];
else
case(fsv_setup[29:28])
2'b00: fsv_parity = (^fsv_data[7:0]) ^ fsv_setup[24];
2'b01: fsv_parity = (^fsv_data[6:0]) ^ fsv_setup[24];
2'b10: fsv_parity = (^fsv_data[5:0]) ^ fsv_setup[24];
2'b11: fsv_parity = (^fsv_data[4:0]) ^ fsv_setup[24];
endcase
// }}}
//////////////////////////////////////////////////////////////////////
//
// The break sequence
// {{{
//////////////////////////////////////////////////////////////////////
reg [1:0] f_break_seq;
initial f_break_seq = 2'b00;
always @(posedge i_clk)
if (i_reset)
f_break_seq <= 2'b00;
else if (i_break)
f_break_seq <= 2'b01;
else if (!zero_baud_counter)
f_break_seq <= { |f_break_seq, 1'b0 };
else
f_break_seq <= 0;
always @(posedge i_clk)
if (f_break_seq[0])
assert(baud_counter == { $past(fsv_setup[23:0]), 4'h0 });
always @(posedge i_clk)
if ((f_past_valid)&&($past(f_break_seq[1]))&&(state != TXU_BREAK))
begin
assert(state == TXU_IDLE);
assert(o_uart_tx == 1'b1);
end
always @(*)
if (|f_break_seq)
begin
assert(state == TXU_BREAK);
assert(r_busy);
assert(o_uart_tx == 1'b0);
end
// }}}
//////////////////////////////////////////////////////////////////////
//
// Properties for use during induction if we are made a submodule of
// the rxuart
// {{{
//////////////////////////////////////////////////////////////////////
//
// Need enough bits for reset (24+4) plus enough bits for all of the
// various characters, 24+4, so 24+5 is a minimum of this counter
//
`ifndef TXUART
reg [28:0] f_counter;
initial f_counter = 0;
always @(posedge i_clk)
if (!o_busy)
f_counter <= 1'b0;
else
f_counter <= f_counter + 1'b1;
always @(*)
if (f_five_seq[0]|f_six_seq[0]|f_seven_seq[0]|f_eight_seq[0])
// {{{
assert(f_counter == (fsv_setup[23:0] - baud_counter - 1));
// }}}
else if (f_five_seq[1]|f_six_seq[1]|f_seven_seq[1]|f_eight_seq[1])
// {{{
assert(f_counter == ({4'h0, fsv_setup[23:0], 1'b0} - baud_counter - 1));
// }}}
else if (f_five_seq[2]|f_six_seq[2]|f_seven_seq[2]|f_eight_seq[2])
// {{{
assert(f_counter == ({4'h0, fsv_setup[23:0], 1'b0}
+{5'h0, fsv_setup[23:0]}
- baud_counter - 1));
// }}}
else if (f_five_seq[3]|f_six_seq[3]|f_seven_seq[3]|f_eight_seq[3])
// {{{
assert(f_counter == ({3'h0, fsv_setup[23:0], 2'b0}
- baud_counter - 1));
// }}}
else if (f_five_seq[4]|f_six_seq[4]|f_seven_seq[4]|f_eight_seq[4])
// {{{
assert(f_counter == ({3'h0, fsv_setup[23:0], 2'b0}
+{5'h0, fsv_setup[23:0]}
- baud_counter - 1));
// }}}
else if (f_five_seq[5]|f_six_seq[5]|f_seven_seq[5]|f_eight_seq[5])
// {{{
assert(f_counter == ({3'h0, fsv_setup[23:0], 2'b0}
+{4'h0, fsv_setup[23:0], 1'b0}
- baud_counter - 1));
// }}}
else if (f_six_seq[6]|f_seven_seq[6]|f_eight_seq[6])
// {{{
assert(f_counter == ({3'h0, fsv_setup[23:0], 2'b0}
+{5'h0, fsv_setup[23:0]}
+{4'h0, fsv_setup[23:0], 1'b0}
- baud_counter - 1));
// }}}
else if (f_seven_seq[7]|f_eight_seq[7])
// {{{
assert(f_counter == ({2'h0, fsv_setup[23:0], 3'b0} // 8
- baud_counter - 1));
// }}}
else if (f_eight_seq[8])
// {{{
assert(f_counter == ({2'h0, fsv_setup[23:0], 3'b0} // 9
+{5'h0, fsv_setup[23:0]}
- baud_counter - 1));
// }}}
else if (f_stop_seq[0] || (!use_parity && f_stop_seq[1]))
begin
// {{{
// Parity bit, or first of two stop bits
case(data_bits)
2'b00: assert(f_counter == ({2'h0, fsv_setup[23:0], 3'b0}
+{4'h0, fsv_setup[23:0], 1'b0} // 10
- baud_counter - 1));
2'b01: assert(f_counter == ({2'h0, fsv_setup[23:0], 3'b0}
+{5'h0, fsv_setup[23:0]} // 9
- baud_counter - 1));
2'b10: assert(f_counter == ({2'h0, fsv_setup[23:0], 3'b0}
- baud_counter - 1)); // 8
2'b11: assert(f_counter == ({3'h0, fsv_setup[23:0], 2'b0}
+{5'h0, fsv_setup[23:0]} // 7
+{4'h0, fsv_setup[23:0], 1'b0}
- baud_counter - 1));
endcase
// }}}
end else if (!use_parity && !dblstop && f_stop_seq[2])
begin
// {{{
// No parity, single stop bit
// Different from the one above, since the last counter is has
// one fewer items within it
case(data_bits)
2'b00: assert(f_counter == ({2'h0, fsv_setup[23:0], 3'b0}
+{4'h0, fsv_setup[23:0], 1'b0} // 10
- baud_counter - 2));
2'b01: assert(f_counter == ({2'h0, fsv_setup[23:0], 3'b0}
+{5'h0, fsv_setup[23:0]} // 9
- baud_counter - 2));
2'b10: assert(f_counter == ({2'h0, fsv_setup[23:0], 3'b0}
- baud_counter - 2)); // 8
2'b11: assert(f_counter == ({3'h0, fsv_setup[23:0], 2'b0}
+{5'h0, fsv_setup[23:0]} // 7
+{4'h0, fsv_setup[23:0], 1'b0}
- baud_counter - 2));
endcase
// }}}
end else if (f_stop_seq[1])
begin
// {{{
// Parity and the first of two stop bits
assert(dblstop && use_parity);
case(data_bits)
2'b00: assert(f_counter == ({2'h0, fsv_setup[23:0], 3'b0}
+{5'h0, fsv_setup[23:0]} // 11
+{4'h0, fsv_setup[23:0], 1'b0}
- baud_counter - 1));
2'b01: assert(f_counter == ({2'h0, fsv_setup[23:0], 3'b0}
+{4'h0, fsv_setup[23:0], 1'b0} // 10
- baud_counter - 1));
2'b10: assert(f_counter == ({2'h0, fsv_setup[23:0], 3'b0}
+{5'h0, fsv_setup[23:0]} // 9
- baud_counter - 1));
2'b11: assert(f_counter == ({2'h0, fsv_setup[23:0], 3'b0}
- baud_counter - 1)); // 8
endcase
// }}}
end else if ((dblstop ^ use_parity) && f_stop_seq[2])
begin
// {{{
// Parity and one stop bit
// assert(!dblstop && use_parity);
case(data_bits)
2'b00: assert(f_counter == ({2'h0, fsv_setup[23:0], 3'b0}
+{5'h0, fsv_setup[23:0]} // 11
+{4'h0, fsv_setup[23:0], 1'b0}
- baud_counter - 2));
2'b01: assert(f_counter == ({2'h0, fsv_setup[23:0], 3'b0}
+{4'h0, fsv_setup[23:0], 1'b0} // 10
- baud_counter - 2));
2'b10: assert(f_counter == ({2'h0, fsv_setup[23:0], 3'b0}
+{5'h0, fsv_setup[23:0]} // 9
- baud_counter - 2));
2'b11: assert(f_counter == ({2'h0, fsv_setup[23:0], 3'b0}
- baud_counter - 2)); // 8
endcase
// }}}
end else if (f_stop_seq[2])
begin
// {{{
assert(dblstop);
assert(use_parity);
// Parity and two stop bits
case(data_bits)
2'b00: assert(f_counter == ({2'h0, fsv_setup[23:0], 3'b0}
+{3'h0, fsv_setup[23:0], 2'b00} // 12
- baud_counter - 2));
2'b01: assert(f_counter == ({2'h0, fsv_setup[23:0], 3'b0}
+{5'h0, fsv_setup[23:0]} // 11
+{4'h0, fsv_setup[23:0], 1'b0}
- baud_counter - 2));
2'b10: assert(f_counter == ({2'h0, fsv_setup[23:0], 3'b0}
+{4'h0, fsv_setup[23:0], 1'b0} // 10
- baud_counter - 2));
2'b11: assert(f_counter == ({2'h0, fsv_setup[23:0], 3'b0}
+{5'h0, fsv_setup[23:0]} // 9
- baud_counter - 2));
endcase
// }}}
end
`endif
// }}}
//////////////////////////////////////////////////////////////////////
//
// Other properties, not necessarily associated with any sequences
//
//////////////////////////////////////////////////////////////////////
always @(*)
assert((state < 4'hb)||(state >= 4'he));
//////////////////////////////////////////////////////////////////////
//
// Careless/limiting assumption section
//
//////////////////////////////////////////////////////////////////////
always @(*)
assume(i_setup[23:0] > 2);
always @(*)
assert(fsv_setup[23:0] > 2);
`endif // FORMAL
// }}}
endmodule
|
module sky130_fd_sc_hd__dlclkp (
GCLK,
GATE,
CLK
);
// Module ports
output GCLK;
input GATE;
input CLK ;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire m0 ;
wire clkn ;
wire CLK_delayed ;
wire GATE_delayed;
reg notifier ;
wire awake ;
// Name Output Other arguments
not not0 (clkn , CLK_delayed );
sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);
and and0 (GCLK , m0, CLK_delayed );
assign awake = ( VPWR === 1'b1 );
endmodule
|
module pcie3_7x_0_pipe_user #
(
parameter PCIE_SIM_MODE = "FALSE", // PCIe sim mode
parameter PCIE_USE_MODE = "3.0", // PCIe sim version
parameter PCIE_OOBCLK_MODE = 1, // PCIe OOB clock mode
parameter RXCDRLOCK_MAX = 4'd15, // RXCDRLOCK max count
parameter RXVALID_MAX = 4'd15, // RXVALID max count
parameter CONVERGE_MAX = 22'd3125000 // Convergence max count
)
(
//---------- Input -------------------------------------
input USER_TXUSRCLK,
input USER_RXUSRCLK,
input USER_OOBCLK_IN,
input USER_RST_N,
input USER_RXUSRCLK_RST_N,
input USER_PCLK_SEL,
input USER_RESETOVRD_START,
input USER_TXRESETDONE,
input USER_RXRESETDONE,
input USER_TXELECIDLE,
input USER_TXCOMPLIANCE,
input USER_RXCDRLOCK_IN,
input USER_RXVALID_IN,
input USER_RXSTATUS_IN,
input USER_PHYSTATUS_IN,
input USER_RATE_DONE,
input USER_RST_IDLE,
input USER_RATE_RXSYNC,
input USER_RATE_IDLE,
input USER_RATE_GEN3,
input USER_RXEQ_ADAPT_DONE,
//---------- Output ------------------------------------
output USER_OOBCLK,
output USER_RESETOVRD,
output USER_TXPMARESET,
output USER_RXPMARESET,
output USER_RXCDRRESET,
output USER_RXCDRFREQRESET,
output USER_RXDFELPMRESET,
output USER_EYESCANRESET,
output USER_TXPCSRESET,
output USER_RXPCSRESET,
output USER_RXBUFRESET,
output USER_RESETOVRD_DONE,
output USER_RESETDONE,
output USER_ACTIVE_LANE,
output USER_RXCDRLOCK_OUT,
output USER_RXVALID_OUT,
output USER_PHYSTATUS_OUT,
output USER_PHYSTATUS_RST,
output USER_GEN3_RDY,
output USER_RX_CONVERGE
);
//---------- Input Registers ---------------------------
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg pclk_sel_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg resetovrd_start_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txresetdone_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxresetdone_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txelecidle_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txcompliance_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxcdrlock_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxvalid_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxstatus_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rate_done_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rst_idle_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rate_rxsync_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rate_idle_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rate_gen3_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxeq_adapt_done_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg pclk_sel_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg resetovrd_start_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txresetdone_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxresetdone_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txelecidle_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txcompliance_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxcdrlock_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxvalid_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxstatus_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rate_done_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rst_idle_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rate_rxsync_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rate_idle_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rate_gen3_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxeq_adapt_done_reg2;
//---------- Internal Signal ---------------------------
reg [ 1:0] oobclk_cnt = 2'd0;
reg [ 7:0] reset_cnt = 8'd127;
reg [ 3:0] rxcdrlock_cnt = 4'd0;
reg [ 3:0] rxvalid_cnt = 4'd0;
reg [21:0] converge_cnt = 22'd0;
reg converge_gen3 = 1'd0;
//---------- Output Registers --------------------------
reg oobclk = 1'd0;
reg [ 7:0] reset = 8'h00;
reg gen3_rdy = 1'd0;
reg [ 1:0] fsm = 2'd0;
//---------- FSM ---------------------------------------
localparam FSM_IDLE = 2'd0;
localparam FSM_RESETOVRD = 2'd1;
localparam FSM_RESET_INIT = 2'd2;
localparam FSM_RESET = 2'd3;
//---------- Simulation Speedup ------------------------
localparam converge_max_cnt = (PCIE_SIM_MODE == "TRUE") ? 22'd100 : CONVERGE_MAX;
//---------- Input FF ----------------------------------------------------------
always @ (posedge USER_TXUSRCLK)
begin
if (!USER_RST_N)
begin
//---------- 1st Stage FF --------------------------
pclk_sel_reg1 <= 1'd0;
resetovrd_start_reg1 <= 1'd0;
txresetdone_reg1 <= 1'd0;
rxresetdone_reg1 <= 1'd0;
txelecidle_reg1 <= 1'd0;
txcompliance_reg1 <= 1'd0;
rxcdrlock_reg1 <= 1'd0;
rxeq_adapt_done_reg1 <= 1'd0;
//---------- 2nd Stage FF --------------------------
pclk_sel_reg2 <= 1'd0;
resetovrd_start_reg2 <= 1'd0;
txresetdone_reg2 <= 1'd0;
rxresetdone_reg2 <= 1'd0;
txelecidle_reg2 <= 1'd0;
txcompliance_reg2 <= 1'd0;
rxcdrlock_reg2 <= 1'd0;
rxeq_adapt_done_reg2 <= 1'd0;
end
else
begin
//---------- 1st Stage FF --------------------------
pclk_sel_reg1 <= USER_PCLK_SEL;
resetovrd_start_reg1 <= USER_RESETOVRD_START;
txresetdone_reg1 <= USER_TXRESETDONE;
rxresetdone_reg1 <= USER_RXRESETDONE;
txelecidle_reg1 <= USER_TXELECIDLE;
txcompliance_reg1 <= USER_TXCOMPLIANCE;
rxcdrlock_reg1 <= USER_RXCDRLOCK_IN;
rxeq_adapt_done_reg1 <= USER_RXEQ_ADAPT_DONE;
//---------- 2nd Stage FF --------------------------
pclk_sel_reg2 <= pclk_sel_reg1;
resetovrd_start_reg2 <= resetovrd_start_reg1;
txresetdone_reg2 <= txresetdone_reg1;
rxresetdone_reg2 <= rxresetdone_reg1;
txelecidle_reg2 <= txelecidle_reg1;
txcompliance_reg2 <= txcompliance_reg1;
rxcdrlock_reg2 <= rxcdrlock_reg1;
rxeq_adapt_done_reg2 <= rxeq_adapt_done_reg1;
end
end
//---------- Input FF ----------------------------------------------------------
always @ (posedge USER_RXUSRCLK)
begin
if (!USER_RXUSRCLK_RST_N)
begin
//---------- 1st Stage FF --------------------------
rxvalid_reg1 <= 1'd0;
rxstatus_reg1 <= 1'd0;
rst_idle_reg1 <= 1'd0;
rate_done_reg1 <= 1'd0;
rate_rxsync_reg1 <= 1'd0;
rate_idle_reg1 <= 1'd0;
rate_gen3_reg1 <= 1'd0;
//---------- 2nd Stage FF --------------------------
rxvalid_reg2 <= 1'd0;
rxstatus_reg2 <= 1'd0;
rst_idle_reg2 <= 1'd0;
rate_done_reg2 <= 1'd0;
rate_rxsync_reg2 <= 1'd0;
rate_idle_reg2 <= 1'd0;
rate_gen3_reg2 <= 1'd0;
end
else
begin
//---------- 1st Stage FF --------------------------
rxvalid_reg1 <= USER_RXVALID_IN;
rxstatus_reg1 <= USER_RXSTATUS_IN;
rst_idle_reg1 <= USER_RST_IDLE;
rate_done_reg1 <= USER_RATE_DONE;
rate_rxsync_reg1 <= USER_RATE_RXSYNC;
rate_idle_reg1 <= USER_RATE_IDLE;
rate_gen3_reg1 <= USER_RATE_GEN3;
//---------- 2nd Stage FF --------------------------
rxvalid_reg2 <= rxvalid_reg1;
rxstatus_reg2 <= rxstatus_reg1;
rst_idle_reg2 <= rst_idle_reg1;
rate_done_reg2 <= rate_done_reg1;
rate_rxsync_reg2 <= rate_rxsync_reg1;
rate_idle_reg2 <= rate_idle_reg1;
rate_gen3_reg2 <= rate_gen3_reg1;
end
end
//---------- Generate Reset Override -------------------------------------------
generate if (PCIE_USE_MODE == "1.0")
begin : resetovrd
//---------- Reset Counter -------------------------------------------------
always @ (posedge USER_TXUSRCLK)
begin
if (!USER_RST_N)
reset_cnt <= 8'd127;
else
//---------- Decrement Counter ---------------------
if (((fsm == FSM_RESETOVRD) || (fsm == FSM_RESET)) && (reset_cnt != 8'd0))
reset_cnt <= reset_cnt - 8'd1;
//---------- Reset Counter -------------------------
else
case (reset)
8'b00000000 : reset_cnt <= 8'd127; // Programmable PMARESET time
8'b11111111 : reset_cnt <= 8'd127; // Programmable RXCDRRESET time
8'b11111110 : reset_cnt <= 8'd127; // Programmable RXCDRFREQRESET time
8'b11111100 : reset_cnt <= 8'd127; // Programmable RXDFELPMRESET time
8'b11111000 : reset_cnt <= 8'd127; // Programmable EYESCANRESET time
8'b11110000 : reset_cnt <= 8'd127; // Programmable PCSRESET time
8'b11100000 : reset_cnt <= 8'd127; // Programmable RXBUFRESET time
8'b11000000 : reset_cnt <= 8'd127; // Programmable RESETOVRD deassertion time
8'b10000000 : reset_cnt <= 8'd127;
default : reset_cnt <= 8'd127;
endcase
end
//---------- Reset Shift Register ------------------------------------------
always @ (posedge USER_TXUSRCLK)
begin
if (!USER_RST_N)
reset <= 8'h00;
else
//---------- Initialize Reset Register ---------
if (fsm == FSM_RESET_INIT)
reset <= 8'hFF;
//---------- Shift Reset Register --------------
else if ((fsm == FSM_RESET) && (reset_cnt == 8'd0))
reset <= {reset[6:0], 1'd0};
//---------- Hold Reset Register ---------------
else
reset <= reset;
end
//---------- Reset Override FSM --------------------------------------------
always @ (posedge USER_TXUSRCLK)
begin
if (!USER_RST_N)
fsm <= FSM_IDLE;
else
begin
case (fsm)
//---------- Idle State ------------------------
FSM_IDLE : fsm <= resetovrd_start_reg2 ? FSM_RESETOVRD : FSM_IDLE;
//---------- Assert RESETOVRD ------------------
FSM_RESETOVRD : fsm <= (reset_cnt == 8'd0) ? FSM_RESET_INIT : FSM_RESETOVRD;
//---------- Initialize Reset ------------------
FSM_RESET_INIT : fsm <= FSM_RESET;
//---------- Shift Reset -----------------------
FSM_RESET : fsm <= ((reset == 8'd0) && rxresetdone_reg2) ? FSM_IDLE : FSM_RESET;
//---------- Default State ---------------------
default : fsm <= FSM_IDLE;
endcase
end
end
end
//---------- Disable Reset Override --------------------------------------------
else
begin : resetovrd_disble
//---------- Generate Default Signals --------------------------------------
always @ (posedge USER_TXUSRCLK)
begin
if (!USER_RST_N)
begin
reset_cnt <= 8'hFF;
reset <= 8'd0;
fsm <= 2'd0;
end
else
begin
reset_cnt <= 8'hFF;
reset <= 8'd0;
fsm <= 2'd0;
end
end
end
endgenerate
//---------- Generate OOB Clock Divider ------------------------
generate if (PCIE_OOBCLK_MODE == 1)
begin : oobclk_div
//---------- OOB Clock Divider -----------------------------
always @ (posedge USER_OOBCLK_IN)
begin
if (!USER_RST_N)
begin
oobclk_cnt <= 2'd0;
oobclk <= 1'd0;
end
else
begin
oobclk_cnt <= oobclk_cnt + 2'd1;
oobclk <= pclk_sel_reg2 ? oobclk_cnt[1] : oobclk_cnt[0];
end
end
end
else
begin : oobclk_div_disable
//---------- OOB Clock Default -------------------------
always @ (posedge USER_OOBCLK_IN)
begin
if (!USER_RST_N)
begin
oobclk_cnt <= 2'd0;
oobclk <= 1'd0;
end
else
begin
oobclk_cnt <= 2'd0;
oobclk <= 1'd0;
end
end
end
endgenerate
//---------- RXCDRLOCK Filter --------------------------------------------------
always @ (posedge USER_TXUSRCLK)
begin
if (!USER_RST_N)
rxcdrlock_cnt <= 4'd0;
else
//---------- Increment RXCDRLOCK Counter -----------
if (rxcdrlock_reg2 && (rxcdrlock_cnt != RXCDRLOCK_MAX))
rxcdrlock_cnt <= rxcdrlock_cnt + 4'd1;
//---------- Hold RXCDRLOCK Counter ----------------
else if (rxcdrlock_reg2 && (rxcdrlock_cnt == RXCDRLOCK_MAX))
rxcdrlock_cnt <= rxcdrlock_cnt;
//---------- Reset RXCDRLOCK Counter ---------------
else
rxcdrlock_cnt <= 4'd0;
end
//---------- RXVALID Filter ----------------------------------------------------
always @ (posedge USER_RXUSRCLK)
begin
if (!USER_RXUSRCLK_RST_N)
rxvalid_cnt <= 4'd0;
else
//---------- Increment RXVALID Counter -------------
if (rxvalid_reg2 && (rxvalid_cnt != RXVALID_MAX) && (!rxstatus_reg2))
rxvalid_cnt <= rxvalid_cnt + 4'd1;
//---------- Hold RXVALID Counter ------------------
else if (rxvalid_reg2 && (rxvalid_cnt == RXVALID_MAX))
rxvalid_cnt <= rxvalid_cnt;
//---------- Reset RXVALID Counter -----------------
else
rxvalid_cnt <= 4'd0;
end
//---------- Converge Counter --------------------------------------------------
always @ (posedge USER_TXUSRCLK)
begin
if (!USER_RST_N)
converge_cnt <= 22'd0;
else
//---------- Enter Gen1/Gen2 -----------------------
if (rst_idle_reg2 && rate_idle_reg2 && !rate_gen3_reg2)
begin
//---------- Increment Converge Counter --------
if (converge_cnt < converge_max_cnt)
converge_cnt <= converge_cnt + 22'd1;
//---------- Hold Converge Counter -------------
else
converge_cnt <= converge_cnt;
end
//---------- Reset Converge Counter ----------------
else
converge_cnt <= 22'd0;
end
//---------- Converge ----------------------------------------------------------
always @ (posedge USER_TXUSRCLK)
begin
if (!USER_RST_N)
converge_gen3 <= 1'd0;
else
//---------- Enter Gen3 ----------------------------
if (rate_gen3_reg2)
//---------- Wait for RX equalization adapt done
if (rxeq_adapt_done_reg2)
converge_gen3 <= 1'd1;
else
converge_gen3 <= converge_gen3;
//-------- Exit Gen3 -------------------------------
else
converge_gen3 <= 1'd0;
end
//---------- GEN3_RDY Generator ------------------------------------------------
always @ (posedge USER_RXUSRCLK)
begin
if (!USER_RXUSRCLK_RST_N)
gen3_rdy <= 1'd0;
else
gen3_rdy <= rate_idle_reg2 && rate_gen3_reg2;
end
//---------- PIPE User Override Reset Output -----------------------------------
assign USER_RESETOVRD = (fsm != FSM_IDLE);
assign USER_TXPMARESET = 1'd0;
assign USER_RXPMARESET = reset[0];
assign USER_RXCDRRESET = reset[1];
assign USER_RXCDRFREQRESET = reset[2];
assign USER_RXDFELPMRESET = reset[3];
assign USER_EYESCANRESET = reset[4];
assign USER_TXPCSRESET = 1'd0;
assign USER_RXPCSRESET = reset[5];
assign USER_RXBUFRESET = reset[6];
assign USER_RESETOVRD_DONE = (fsm == FSM_IDLE);
//---------- PIPE User Output --------------------------------------------------
assign USER_OOBCLK = oobclk;
assign USER_RESETDONE = (txresetdone_reg2 && rxresetdone_reg2);
assign USER_ACTIVE_LANE = !(txelecidle_reg2 && txcompliance_reg2);
//----------------------------------------------------------
assign USER_RXCDRLOCK_OUT = (USER_RXCDRLOCK_IN && (rxcdrlock_cnt == RXCDRLOCK_MAX)); // Filtered RXCDRLOCK
//----------------------------------------------------------
assign USER_RXVALID_OUT = ((USER_RXVALID_IN && (rxvalid_cnt == RXVALID_MAX)) && // Filtered RXVALID
rst_idle_reg2 && // Force RXVALID = 0 during reset
rate_idle_reg2); // Force RXVALID = 0 during rate change
//----------------------------------------------------------
assign USER_PHYSTATUS_OUT = (!rst_idle_reg2 || // Force PHYSTATUS = 1 during reset
((rate_idle_reg2 || rate_rxsync_reg2) && USER_PHYSTATUS_IN) || // Raw PHYSTATUS
rate_done_reg2); // Gated PHYSTATUS for rate change
//----------------------------------------------------------
assign USER_PHYSTATUS_RST = !rst_idle_reg2; // Filtered PHYSTATUS for reset
//----------------------------------------------------------
assign USER_GEN3_RDY = gen3_rdy;
//----------------------------------------------------------
assign USER_RX_CONVERGE = (converge_cnt == converge_max_cnt) || converge_gen3;
endmodule
|
module VGA_Ctrl ( // Host Side
iRed,
iGreen,
iBlue,
oCurrent_X,
oCurrent_Y,
oAddress,
oRequest,
// VGA Side
oVGA_R,
oVGA_G,
oVGA_B,
oVGA_HS,
oVGA_VS,
oVGA_SYNC,
oVGA_BLANK,
oVGA_CLOCK,
// Control Signal
iCLK,
iRST_N );
// Host Side
input [9:0] iRed;
input [9:0] iGreen;
input [9:0] iBlue;
output [21:0] oAddress;
output [10:0] oCurrent_X;
output [10:0] oCurrent_Y;
output oRequest;
// VGA Side
output [9:0] oVGA_R;
output [9:0] oVGA_G;
output [9:0] oVGA_B;
output reg oVGA_HS;
output reg oVGA_VS;
output oVGA_SYNC;
output oVGA_BLANK;
output oVGA_CLOCK;
// Control Signal
input iCLK;
input iRST_N;
// Internal Registers
reg [10:0] H_Cont;
reg [10:0] V_Cont;
////////////////////////////////////////////////////////////
// Horizontal Parameter
parameter H_FRONT = 16;
parameter H_SYNC = 96;
parameter H_BACK = 48;
parameter H_ACT = 640;
parameter H_BLANK = H_FRONT+H_SYNC+H_BACK; //160
parameter H_TOTAL = H_FRONT+H_SYNC+H_BACK+H_ACT; //800
////////////////////////////////////////////////////////////
// Vertical Parameter
parameter V_FRONT = 11;
parameter V_SYNC = 2;
parameter V_BACK = 31;
parameter V_ACT = 480;
parameter V_BLANK = V_FRONT+V_SYNC+V_BACK; //44
parameter V_TOTAL = V_FRONT+V_SYNC+V_BACK+V_ACT; //524
////////////////////////////////////////////////////////////
assign oVGA_SYNC = 1'b1; // This pin is unused.
assign oVGA_BLANK = ~((H_Cont<H_BLANK)||(V_Cont<V_BLANK));
assign oVGA_CLOCK = ~iCLK;
assign oVGA_R = iRed;
assign oVGA_G = iGreen;
assign oVGA_B = iBlue;
assign oAddress = oCurrent_Y*H_ACT+oCurrent_X;
assign oRequest = ((H_Cont>=H_BLANK && H_Cont<H_TOTAL) &&
(V_Cont>=V_BLANK && V_Cont<V_TOTAL));
assign oCurrent_X = (H_Cont>=H_BLANK) ? H_Cont-H_BLANK : 11'h0 ;
assign oCurrent_Y = (V_Cont>=V_BLANK) ? V_Cont-V_BLANK : 11'h0 ;
// Horizontal Generator: Refer to the pixel clock
always@(posedge iCLK or negedge iRST_N)
begin
if(!iRST_N)
begin
H_Cont <= 0;
oVGA_HS <= 1;
end
else
begin
if(H_Cont<H_TOTAL)
H_Cont <= H_Cont+1'b1;
else
H_Cont <= 0;
// Horizontal Sync
if(H_Cont==H_FRONT-1) // Front porch end
oVGA_HS <= 1'b0;
if(H_Cont==H_FRONT+H_SYNC-1) // Sync pulse end
oVGA_HS <= 1'b1;
end
end
// Vertical Generator: Refer to the horizontal sync
always@(posedge oVGA_HS or negedge iRST_N)
begin
if(!iRST_N)
begin
V_Cont <= 0;
oVGA_VS <= 1;
end
else
begin
if(V_Cont<V_TOTAL)
V_Cont <= V_Cont+1'b1;
else
V_Cont <= 0;
// Vertical Sync
if(V_Cont==V_FRONT-1) // Front porch end
oVGA_VS <= 1'b0;
if(V_Cont==V_FRONT+V_SYNC-1) // Sync pulse end
oVGA_VS <= 1'b1;
end
end
endmodule
|
module test_mem_dev #(
parameter READ_FIFO_SIZE = 8,
parameter WRITE_FIFO_SIZE = 8,
parameter ADDRESS_WIDTH = 8
)(
input clk,
input rst,
//Write Side
input write_enable,
input [63:0] write_addr,
input write_addr_inc,
input write_addr_dec,
output write_finished,
input [23:0] write_count,
input write_flush,
output [1:0] write_ready,
input [1:0] write_activate,
output [23:0] write_size,
input write_strobe,
input [31:0] write_data,
//Read Side
input read_enable,
input [63:0] read_addr,
input read_addr_inc,
input read_addr_dec,
output read_busy,
output read_error,
input [23:0] read_count,
input read_flush,
output read_ready,
output read_activate,
output [23:0] read_size,
output [31:0] read_data,
input read_strobe
);
//Local Parameters
//Registers/Wires
reg [ADDRESS_WIDTH - 1:0] mem_addr_in;
reg [ADDRESS_WIDTH - 1:0] mem_addr_out;
reg [23:0] local_write_count;
reg [23:0] mem_write_count;
wire mem_write_overflow;
reg [23:0] local_read_size;
reg [23:0] mem_read_count;
reg mem_read_strobe;
reg mem_write_strobe;
reg prev_write_enable;
wire posedge_write_enable;
reg prev_read_enable;
wire posedge_read_enable;
reg [31:0] prev_f2m_data;
reg f2m_data_error;
reg [31:0] prev_m2f_data;
reg m2f_data_error;
reg f2m_strobe;
wire f2m_ready;
reg f2m_activate;
wire [23:0] f2m_size;
wire [31:0] f2m_data;
reg [23:0] f2m_count;
wire [1:0] m2f_ready;
reg [1:0] m2f_activate;
wire [23:0] m2f_size;
reg m2f_strobe;
wire [31:0] m2f_data;
reg [23:0] m2f_count;
reg first_write;
wire [31:0] din;
wire wea;
reg fill_mem;
reg [31:0] fill_mem_data;
reg fill_mem_wea;
wire write_fifo_empty;
//Submodules
blk_mem #(
.DATA_WIDTH (32 ),
.ADDRESS_WIDTH (ADDRESS_WIDTH ),
.INC_NUM_PATTERN (1 )
) mem (
.clka (clk ),
.wea (wea ),
.dina (din ),
.addra (mem_addr_in ),
.clkb (clk ),
.doutb (m2f_data ),
.addrb (mem_addr_out )
);
ppfifo#(
.DATA_WIDTH (32 ),
.ADDRESS_WIDTH (WRITE_FIFO_SIZE)
)fifo_to_mem (
.reset (rst ),
//Write
.write_clock (clk ),
.write_ready (write_ready ),
.write_activate (write_activate ),
.write_fifo_size (write_size ),
.write_strobe (write_strobe ),
.write_data (write_data ),
.starved (write_fifo_empty),
//Read
.read_clock (clk ),
.read_strobe (f2m_strobe ),
.read_ready (f2m_ready ),
.read_activate (f2m_activate ),
.read_count (f2m_size ),
.read_data (f2m_data )
//.inactive ( )
);
ppfifo#(
.DATA_WIDTH (32 ),
.ADDRESS_WIDTH (READ_FIFO_SIZE )
)mem_to_fifo (
.reset (rst ),
//Write
.write_clock (clk ),
.write_ready (m2f_ready ),
.write_activate (m2f_activate ),
.write_fifo_size (m2f_size ),
.write_strobe (m2f_strobe ),
.write_data (m2f_data ),
//.starved ( ),
//Read
.read_clock (clk ),
.read_strobe (read_strobe ),
.read_ready (read_ready ),
.read_activate (read_activate ),
.read_count (read_size ),
.read_data (read_data )
//.inactive ( )
);
//Asynchronous Logic
assign posedge_write_enable = !prev_write_enable && write_enable;
assign posedge_read_enable = !prev_read_enable && read_enable;
assign mem_write_overflow = (mem_write_count > local_write_count);
assign write_finished = ((mem_write_count >= local_write_count) && write_fifo_empty);
assign mem_read_overflow = (mem_read_count > local_read_size);
assign read_finished = (mem_read_count >= local_read_size);
assign din = fill_mem ? fill_mem_data: f2m_data;
assign wea = fill_mem ? fill_mem_wea: f2m_strobe;
assign read_error = m2f_data_error;
//Synchronous Logic
always @ (posedge clk) begin
if (rst) begin
mem_addr_in <= 0;
mem_addr_out <= 0;
f2m_strobe <= 0;
f2m_activate <= 0;
f2m_count <= 0;
m2f_activate <= 0;
m2f_strobe <= 0;
m2f_count <= 0;
prev_write_enable <= 0;
prev_read_enable <= 0;
local_write_count <= 0;
local_read_size <= 0;
mem_write_count <= 0;
mem_read_count <= 0;
mem_read_strobe <= 0;
mem_write_strobe <= 0;
f2m_data_error <= 0;
m2f_data_error <= 0;
prev_f2m_data <= 0;
first_write <= 0;
fill_mem <= 1;
fill_mem_data <= 0;
fill_mem_wea <= 1;
prev_m2f_data <= 0;
end
//Fill Memory Device
else if (fill_mem) begin
fill_mem_wea <= 1;
if (mem_addr_in < (2 ** ADDRESS_WIDTH - 1)) begin
fill_mem_data <= mem_addr_in + 1;
mem_addr_in <= mem_addr_in + 1;
end
else begin
fill_mem <= 0;
fill_mem_wea <= 0;
end
end
else begin
//Strobes
f2m_strobe <= 0;
m2f_strobe <= 0;
mem_read_strobe <= 0;
mem_write_strobe <= 0;
f2m_data_error <= 0;
first_write <= 0;
m2f_data_error <= 0;
//Errors (Incomming)
if ((f2m_count > 0) && mem_write_strobe && !write_flush) begin
if ((prev_f2m_data == (2 ** ADDRESS_WIDTH) - 1) && (f2m_data != 0)) begin
//if ((mem_addr_in == (2 ** ADDRESS_WIDTH) - 1) && (f2m_data != 0)) begin
f2m_data_error <= 1;
$display ("Write: Wrap Error @ 0x%h: 0x%h != 0x%h", mem_addr_in, prev_f2m_data + 1, f2m_data);
end
else if ((prev_f2m_data + 1) != f2m_data) begin
if (first_write) begin
if (prev_f2m_data != f2m_data) begin
f2m_data_error <= 1;
$display ("Write: First Write Error @ 0x%h: 0x%h != 0x%h", mem_addr_in, prev_f2m_data + 1, f2m_data);
end
end
else begin
f2m_data_error <= 1;
$display ("Write: Error @ 0x%h: 0x%h != 0x%h", mem_addr_in, prev_f2m_data + 1, f2m_data);
end
end
end
//Error (Outgoing)
//if ((m2f_count > 0) && mem_read_strobe && !read_flush) begin
if ((m2f_count > 0) && m2f_strobe && !read_flush && ((m2f_activate & m2f_ready) == 0)) begin
if (((prev_m2f_data + 1)== (2 ** ADDRESS_WIDTH)) && (m2f_data != 0))begin
m2f_data_error <= 1;
$display ("Read: Wrap Error @ 0x%h should be 0", prev_m2f_data);
end
else if ((prev_m2f_data + 1) != m2f_data) begin
m2f_data_error <= 1;
$display ("Read: Error @ 0x%h: 0x%h != 0x%h", mem_addr_out, m2f_data, (prev_m2f_data + 1));
end
end
//Store Memory Address
if (posedge_write_enable) begin
mem_addr_in <= write_addr[ADDRESS_WIDTH - 1: 0];
local_write_count <= write_count;
mem_write_count <= 0;
end
if (posedge_read_enable) begin
mem_addr_out <= read_addr[ADDRESS_WIDTH - 1: 0];
local_read_size <= read_count;
mem_read_count <= 0;
end
//If available get a peice of the FIFO that I can write data to the memory
if (!f2m_activate && f2m_ready) begin
f2m_activate <= 1;
f2m_count <= 0;
end
//If there is an available FIFO to write to grab it
if ((m2f_activate == 0) && (m2f_ready > 0)) begin
m2f_count <= 0;
if (m2f_ready[0]) begin
m2f_activate[0] <= 1;
end
else begin
m2f_activate[1] <= 1;
end
end
if (mem_read_strobe) begin
if (read_addr_inc) begin
mem_addr_out <= mem_addr_out + 1;
end
else if (read_addr_dec) begin
mem_addr_out <= mem_addr_out - 1;
end
m2f_strobe <= 1;
end
if (!m2f_strobe &&
!mem_read_strobe && (m2f_activate > 0) &&
((m2f_count >= m2f_size) ||
(mem_read_count > 0 &&
m2f_count >= mem_read_count))) begin
m2f_activate <= 0;
end
if (mem_write_strobe) begin
mem_write_count <= mem_write_count + 1;
if (write_addr_inc) begin
mem_addr_in <= mem_addr_in + 1;
end
else if (write_addr_dec) begin
mem_addr_in <= mem_addr_in - 1;
end
end
//if (write_enable) begin
if (f2m_count < f2m_size) begin
if (f2m_activate) begin
f2m_strobe <= 1;
mem_write_strobe <= 1;
f2m_count <= f2m_count + 1;
if (f2m_count == 0) begin
first_write <= 1;
end
end
end
else begin
f2m_activate <= 0;
end
//end
if (mem_read_count < local_read_size) begin
if (read_enable) begin
if ((m2f_activate > 0) && (m2f_count < m2f_size)) begin
m2f_count <= m2f_count + 1;
mem_read_strobe <= 1;
mem_read_count <= mem_read_count + 1;
end
end
end
if (m2f_strobe) begin
prev_m2f_data <= m2f_data;
end
prev_f2m_data <= f2m_data;
prev_write_enable <= write_enable;
prev_read_enable <= read_enable;
end
end
endmodule
|
module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outreadylatency_check ( .error(1'b1) );
end
endgenerate
niosii_mm_interconnect_0_avalon_st_adapter_005_error_adapter_0 error_adapter_0 (
.clk (in_clk_0_clk), // clk.clk
.reset_n (~in_rst_0_reset), // reset.reset_n
.in_data (in_0_data), // in.data
.in_valid (in_0_valid), // .valid
.in_ready (in_0_ready), // .ready
.out_data (out_0_data), // out.data
.out_valid (out_0_valid), // .valid
.out_ready (out_0_ready), // .ready
.out_error (out_0_error) // .error
);
endmodule
|
module c1_wait(
input CLK_68KCLK, nAS,
input nROM_ZONE, nPORT_ZONE, nCARD_ZONE,
input nROMWAIT, nPWAIT0, nPWAIT1, PDTACK,
output nDTACK
);
reg [1:0] WAIT_CNT;
//assign nPDTACK = ~(nPORT_ZONE | PDTACK); // Really a NOR ? May stall CPU if PDTACK = GND
assign nDTACK = nAS | |{WAIT_CNT}; // Is it nVALID instead of nAS ?
//assign nCLK_68KCLK = ~nCLK_68KCLK;
always @(negedge CLK_68KCLK)
begin
if (!nAS)
begin
// Count down only when nAS low
if (WAIT_CNT) WAIT_CNT <= WAIT_CNT - 1'b1;
end
else
begin
if (!nROM_ZONE)
WAIT_CNT <= ~nROMWAIT; // 0~1 or 1~2 wait cycles ?
else if (!nPORT_ZONE)
WAIT_CNT <= ~{nPWAIT0, nPWAIT1}; // Needs checking
else if (!nCARD_ZONE)
WAIT_CNT <= 2; // MAME and mvstech says so, to check
else
WAIT_CNT <= 0;
end
end
endmodule
|
module altera_mem_if_ddr3_phy_0001_fr_cycle_shifter(
clk,
reset_n,
shift_by,
datain,
dataout
);
// ********************************************************************************************************************************
// BEGIN PARAMETER SECTION
// All parameters default to "" will have their values passed in from higher level wrapper with the controller and driver
parameter DATA_WIDTH = "";
parameter REG_POST_RESET_HIGH = "false";
localparam RATE_MULT = 2;
localparam FULL_DATA_WIDTH = DATA_WIDTH*RATE_MULT;
// END PARAMETER SECTION
// ********************************************************************************************************************************
input clk;
input reset_n;
input [1:0] shift_by;
input [FULL_DATA_WIDTH-1:0] datain;
output [FULL_DATA_WIDTH-1:0] dataout;
reg [FULL_DATA_WIDTH-1:0] datain_r;
always @(posedge clk or negedge reset_n)
begin
if (~reset_n) begin
if (REG_POST_RESET_HIGH == "true")
datain_r <= {FULL_DATA_WIDTH{1'b1}};
else
datain_r <= {FULL_DATA_WIDTH{1'b0}};
end else begin
datain_r <= datain;
end
end
wire [DATA_WIDTH-1:0] datain_t0 = datain[(DATA_WIDTH*1)-1:(DATA_WIDTH*0)];
wire [DATA_WIDTH-1:0] datain_t1 = datain[(DATA_WIDTH*2)-1:(DATA_WIDTH*1)];
wire [DATA_WIDTH-1:0] datain_r_t1 = datain_r[(DATA_WIDTH*2)-1:(DATA_WIDTH*1)];
assign dataout = (shift_by[0] == 1'b1) ? {datain_t0, datain_r_t1} : {datain_t1, datain_t0};
endmodule
|
module WcaAdc
(
input clock_sample,
input clock_rf_data,
input reset,
input enable,
//DMA Interface .
input wire [13:0] dmaCtrl, //DMA address and control lines { addr[9:0], nAddrStrobe, nReadStrobe, nWriteStrobe, cpuclock }
inout wire [15:0] dmaData, //Tri-state I/O data.
//RF Chip Interface. 2 Receive channels, 1 transmit.
input wire rx1_iqsel,
input wire [11:0] rx1_data,
input wire rx2_iqsel,
input wire [11:0] rx2_data,
output reg [11:0] tx1_data,
output wire tx1_iqsel,
output wire rf1_rxen,
output wire rf1_txen,
output wire rf2_rxen,
output wire rf_rxclk, //Lime receive ADC clock.
output wire rf_txclk, //Lime transmit ADC clock.
//DAC Output dma_data
input wire [11:0] tx_i,
input wire [11:0] tx_q,
//Buffer ADC input dma_data.
output reg [11:0] rx0_i,
output reg [11:0] rx0_q,
output reg [11:0] rx1_i,
output reg [11:0] rx1_q
);
//RF Interface. (WRITE)
// bit# | Description
//-------|----------------------------------------------------------
// 0-1 RX Input Mode
// 0 = txd Loopback (counter in UT version)
// 1 = rf1_rx input.
// 2 = rf2_rx input.
// 3 = Fixed Test Pattern DSP0 i = AA0, q = BB1; DSP2 (if available) i=CC0, q=DD1;
//
// 2 "rf1_rxen" output line - set to 1 to enable, 0 to disable. Enables disables the
// Lime chip #1 receive ADC function. If RF Interfane not enabled in FR_MCTRL_0,
// this is disabled.
//
// 3 "rf1_txen" output pin state - set to 1 to enable, 0 to disable Enables / disables the
// Lime chip #1 transmit DAC function. If RF interface not enabled in FR_MCTRL_0,
// this is disabled.
//
// 4 "rf2_rxen" output pin state - set to 1 to enable, 0 to disable. Enables / disables the
// Lime chip #2 receive ADC function. If RF interface not enabled in FR_MCTRL_0,
// this is disabled.
//
// 5 "rf_rxclk" enable (1) / (0). If enabled the rf_rxclk pin will turn on and provide clock
// signals to the receive functions of the Lime chips. If disabled, clock output will be low.
// If RF interface not enabled in FR_MCTRL_0, clock output is disabled.
//
// 6 "rf_txclk" enable (1) / (0). If enabled the tx_rxclk pin will turn on and provide clock
// signals to the transmit functions of Lime chip #1. If disabled, clock output will be low.
// If RF interface not enabled in FR_MCTRL_0, clock output is disabled.
//
// 7-15 Reserved.
//
wire [15:0] rf_ctrl;
WcaWriteWordReg #(`FR_RF_CTRL) sr_rf_ctrl
(.reset(reset), .out( rf_ctrl), .dmaCtrl(dmaCtrl), .dmaData(dmaData) );
//------------------------------------------------------------
// Lime chip control.
//------------------------------------------------------------
assign rf1_rxen = enable & rf_ctrl[2];
assign rf1_txen = enable & rf_ctrl[3];
assign rf2_rxen = enable & rf_ctrl[4];
assign rf_rxclk = (enable & rf_ctrl[5]) ? clock_rf_data : 1'b0;
assign rf_txclk = (enable & rf_ctrl[6]) ? clock_rf_data : 1'b0;
assign tx1_iqsel = (rf1_txen) ? clock_sample : 1'b0;
//------------------------------------------------------------
// Rx1 and Rx2 Interface.Selector.
//------------------------------------------------------------
//Break out receive dma_data into separate I/Q paths
//so we can process in dsp.
always @(posedge clock_rf_data)
begin
case( { enable, rf_ctrl[1:0]} )
3'b100 : // 0 is loop back.tx back on to rx.
begin
if( clock_sample )
begin
rx0_i <= #1 tx_i[11:0];
rx1_i <= #1 tx_i[11:0];
end
else
begin
rx0_q <= #1 tx_q[11:0];
rx1_q <= #1 tx_q[11:0];
end
end
3'b101 : //1 is rx 1.
begin
if( rx1_iqsel )
rx0_i <= #1 rx1_data;
else
rx0_q <= #1 rx1_data;
if( rx2_iqsel )
rx1_i <= #1 rx2_data;
else
rx1_q <= #1 rx2_data;
end
3'b110 : // 2 is rx 2.
begin
if( rx2_iqsel )
rx0_i <= #1 rx2_data;
else
rx0_q <= #1 rx2_data;
if( rx1_iqsel )
rx1_i <= #1 rx1_data;
else
rx1_q <= #1 rx1_data;
end
3'b111 : //3 is test pattern.
begin
rx0_i <= #1 12'd256;
rx0_q <= #1 -12'd256;
rx1_i <= #1 12'd256;
rx1_q <= #1 -12'd256;
end
default: //Default is nothing.
begin
rx0_i <= #1 12'd0;
rx0_q <= #2 12'd0;
rx1_i <= #2 12'd0;
rx1_q <= #2 12'd0;
end
endcase
end
//------------------------------------------------------------
// RSSI Implementation
//------------------------------------------------------------
wire [7:0] rssi_q0;
wire [7:0] rssi_i0;
//Construct Inphase RSSI function
rssi RssiInphase(
.clock(clock_sample), .reset(reset), .enable(enable),
.adc(rx0_i),
.rssi(rssi_i0)
);
//RSSI Quadrature Function
rssi RssiQuadrature(
.clock(clock_sample), .reset(reset), .enable(enable),
.adc(rx0_q),
.rssi(rssi_q0)
);
WcaReadWordReg #(`FR_ADC_RSSI) AdcRssiReadRegister
( .reset(reset), .clockIn(clock_sample), .enableIn(1'b1), .in( {rssi_q0, rssi_i0} ),.dmaCtrl(dmaCtrl), .dmaData(dmaData));
//------------------------------------------------------------
// DC Bias Detection.
//------------------------------------------------------------
rx_dcoffset #(`FR_ADC_IBIAS) OffsetInphase(
.clock(clock_sample), .enable(enable), .reset(reset),
.adc_in(rx0_i),
.dmaCtrl(dmaCtrl), .dmaData(dmaData)
);
rx_dcoffset #(`FR_ADC_QBIAS) OffsetQuadrature(
.clock(clock_sample), .enable(enable), .reset(reset),
.adc_in(rx0_q),
.dmaCtrl(dmaCtrl), .dmaData(dmaData)
);
//------------------------------------------------------------
// Tx1 Data Output.
//------------------------------------------------------------
always @(posedge clock_rf_data)
begin
if( rf1_txen)
begin
if( clock_sample )
tx1_data <= #1 tx_i[11:0];
else
tx1_data <= #1 tx_q[11:0];
end
else
tx1_data <= #1 15'd0;
end
endmodule
|
module tb_spi_i2s_ipi_clk_div();
localparam TB_PARAM_CNT_WIDTH = 8;
localparam TB_PARAM_STAGE_NUM = 3;
function integer clogb2;
input [31:0] value;
reg div2;
begin
for (clogb2 = 0; value > 0; clogb2 = clogb2 + 1)
value = value >> 1;
end
endfunction
wire clkd_clk_out_o;
wire clkd_time_base_o;
reg [clogb2(TB_PARAM_CNT_WIDTH) - 1 : 0] clkd_clk_div_sel_i;
reg clkd_enable_i;
reg clkd_clk;
reg clkd_rst_n;
integer i;
spi_i2s_ipi_clk_div
#(
.PARAM_CNT_WIDTH ( TB_PARAM_CNT_WIDTH ),
.PARAM_STAGE_WIDTH ( TB_PARAM_STAGE_NUM )
)
CLK_DIV
(
.clkd_clk_out_o ( clkd_clk_out_o ),
.clkd_time_base_o ( clkd_time_base_o ),
.clkd_clk_div_sel_i ( clkd_clk_div_sel_i),
.clkd_enable_i ( clkd_enable_i ),
.clkd_clk ( clkd_clk ),
.clkd_rst_n ( clkd_rst_n )
);
initial
begin
clkd_clk = 0;
clkd_rst_n = 0;
clkd_enable_i = 0;
clkd_clk_div_sel_i = 0;
@(posedge clkd_clk);
@(posedge clkd_clk);
clkd_rst_n = 1;
clkd_enable_i = 1;
for(i = 0; i < 8; i = i + 1)
begin
repeat(10*2**i)
@(posedge clkd_clk);
if(i != 0)
@(posedge clkd_time_base_o);
clkd_enable_i = 0;
clkd_clk_div_sel_i = i + 1;
@(posedge clkd_clk);
clkd_enable_i = 1;
end
$stop;
end
always #10
clkd_clk = !clkd_clk;
endmodule
|
module top();
// Inputs are registered
reg A0;
reg A1;
reg S;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A0 = 1'bX;
A1 = 1'bX;
S = 1'bX;
#20 A0 = 1'b0;
#40 A1 = 1'b0;
#60 S = 1'b0;
#80 A0 = 1'b1;
#100 A1 = 1'b1;
#120 S = 1'b1;
#140 A0 = 1'b0;
#160 A1 = 1'b0;
#180 S = 1'b0;
#200 S = 1'b1;
#220 A1 = 1'b1;
#240 A0 = 1'b1;
#260 S = 1'bx;
#280 A1 = 1'bx;
#300 A0 = 1'bx;
end
sky130_fd_sc_lp__udp_mux_2to1_N dut (.A0(A0), .A1(A1), .S(S), .Y(Y));
endmodule
|
module dpram_64x64 (
byteena_a,
clock,
data,
rdaddress,
wraddress,
wren,
q);
input [7:0] byteena_a;
input clock;
input [63:0] data;
input [5:0] rdaddress;
input [5:0] wraddress;
input wren;
output [63:0] q;
wire [63:0] sub_wire0;
wire [63:0] q = sub_wire0[63:0];
altsyncram altsyncram_component (
.wren_a (wren),
.clock0 (clock),
.byteena_a (byteena_a),
.address_a (wraddress),
.address_b (rdaddress),
.data_a (data),
.q_b (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_b ({64{1'b1}}),
.eccstatus (),
.q_a (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_b (1'b0));
defparam
altsyncram_component.address_aclr_b = "NONE",
altsyncram_component.address_reg_b = "CLOCK0",
altsyncram_component.byte_size = 8,
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_input_b = "BYPASS",
altsyncram_component.clock_enable_output_b = "BYPASS",
altsyncram_component.intended_device_family = "Cyclone III",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 64,
altsyncram_component.numwords_b = 64,
altsyncram_component.operation_mode = "DUAL_PORT",
altsyncram_component.outdata_aclr_b = "NONE",
altsyncram_component.outdata_reg_b = "UNREGISTERED",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE",
altsyncram_component.widthad_a = 6,
altsyncram_component.widthad_b = 6,
altsyncram_component.width_a = 64,
altsyncram_component.width_b = 64,
altsyncram_component.width_byteena_a = 8;
endmodule
|
module pad_misc(io_tdo_en ,bscan_hiz_l_in ,bscan_update_dr_in ,tdi ,
spare_misc_pad ,spare_misc_pad_to_core ,spare_misc_pindata ,
spare_misc_pin ,burnin ,io_burnin ,spare_misc_paddata ,
spare_misc_padoe ,vreg_selbg_l ,io_pmi ,tck2 ,pad_misc_bsi ,
pad_misc_se ,pad_misc_si ,pad_misc_so ,bscan_clock_dr_in ,ssi_miso
,ssi_mosi ,temp_trig ,jbus_arst_l ,jbus_adbginit_l ,ext_int_l ,
vdd_sense ,jbus_gdbginit_l ,bscan_shift_dr_out ,bscan_update_dr_out
,bscan_clock_dr_out ,bscan_mode_ctl_out ,pmi ,io_ext_int_l ,
pll_char_in ,jbus_grst_l ,jbus_gclk ,vss_sense ,clk_stretch ,
pwron_rst_l ,test_mode ,vddo ,io_trigin ,pmo ,pgrm_en ,io_test_mode
,clk_misc_cken ,hstl_vref ,tms ,pcm_misc_oe ,io_pwron_rst_l ,
io_tms ,io_pmo ,io_pgrm_en ,io_pll_char_in ,io_tdo ,jbi_io_ssi_sck
,jbi_io_ssi_mosi ,io_trst_l ,io_tck ,io_tdi ,io_temp_trig ,
spare_misc_pin_to_core ,io_jbi_ssi_miso ,tck ,tdo ,trst_l ,ssi_sck
,bscan_mode_ctl_in ,bscan_shift_dr_in ,bscan_hiz_l_out ,
pad_misc_bso ,io_tck2 ,spare_misc_pinoe ,io_vreg_selbg_l ,
io_clk_stretch ,trigin );
output [2:0] spare_misc_pad_to_core ;
input [2:0] spare_misc_paddata ;
input [2:0] spare_misc_padoe ;
inout [2:0] spare_misc_pad ;
output io_burnin ;
output io_pmi ;
output pad_misc_so ;
output bscan_shift_dr_out ;
output bscan_update_dr_out ;
output bscan_clock_dr_out ;
output bscan_mode_ctl_out ;
output io_ext_int_l ;
output io_trigin ;
output io_test_mode ;
output io_pwron_rst_l ;
output io_tms ;
output io_pgrm_en ;
output io_pll_char_in ;
output io_trst_l ;
output io_tck ;
output io_tdi ;
output io_temp_trig ;
output spare_misc_pin_to_core ;
output io_jbi_ssi_miso ;
output bscan_hiz_l_out ;
output pad_misc_bso ;
output io_tck2 ;
output io_vreg_selbg_l ;
output io_clk_stretch ;
input io_tdo_en ;
input bscan_hiz_l_in ;
input bscan_update_dr_in ;
input spare_misc_pindata ;
input pad_misc_bsi ;
input pad_misc_se ;
input pad_misc_si ;
input bscan_clock_dr_in ;
input jbus_arst_l ;
input jbus_adbginit_l ;
input jbus_gdbginit_l ;
input jbus_grst_l ;
input jbus_gclk ;
input vddo ;
input clk_misc_cken ;
input pcm_misc_oe ;
input io_pmo ;
input io_tdo ;
input jbi_io_ssi_sck ;
input jbi_io_ssi_mosi ;
input bscan_mode_ctl_in ;
input bscan_shift_dr_in ;
input spare_misc_pinoe ;
inout tdi ;
inout spare_misc_pin ;
inout burnin ;
inout vreg_selbg_l ;
inout tck2 ;
inout ssi_miso ;
inout ssi_mosi ;
inout temp_trig ;
inout ext_int_l ;
inout vdd_sense ;
inout pmi ;
inout pll_char_in ;
inout vss_sense ;
inout clk_stretch ;
inout pwron_rst_l ;
inout test_mode ;
inout pmo ;
inout pgrm_en ;
inout hstl_vref ;
inout tms ;
inout tck ;
inout tdo ;
inout trst_l ;
inout ssi_sck ;
inout trigin ;
supply1 vdd ;
supply0 vss ;
wire net282 ;
wire net300 ;
wire net283 ;
wire net301 ;
wire net284 ;
wire net302 ;
wire net285 ;
wire net286 ;
wire net287 ;
wire net288 ;
wire net305 ;
wire chunk1_so ;
wire chunk5_so ;
wire net296 ;
wire net297 ;
wire net412 ;
wire net298 ;
wire net413 ;
wire net299 ;
wire chunk2_bso ;
wire net0251 ;
wire chunk1_bso ;
wire net0254 ;
wire net324 ;
wire net0257 ;
wire net325 ;
wire net326 ;
wire net327 ;
wire net328 ;
wire net329 ;
wire reset_l ;
wire net330 ;
wire net338 ;
wire net339 ;
wire net340 ;
wire net341 ;
wire net342 ;
wire net343 ;
wire net344 ;
wire net346 ;
wire chunk3_bso ;
wire rclk ;
wire misc_si_1 ;
wire misc_si_2 ;
wire header_si ;
wire chunk2_so ;
wire net273 ;
bw_u1_minbuf_4x I141 (
.z (header_si ),
.a (misc_si_2 ) );
bw_clk_cl_misc_jbus pad_misc_header (
.arst_l (jbus_arst_l ),
.adbginit_l (jbus_adbginit_l ),
.se (pad_misc_se ),
.si (pad_misc_si ),
.cluster_grst_l (reset_l ),
.so (misc_si_1 ),
.dbginit_l (net273 ),
.rclk (rclk ),
.gclk (jbus_gclk ),
.cluster_cken (clk_misc_cken ),
.grst_l (jbus_grst_l ),
.gdbginit_l (jbus_gdbginit_l ) );
bw_u1_ckbuf_1p5x so_ckbuf (
.clk (net0251 ),
.rclk (rclk ) );
bw_u1_scanl_2x lockup_bso (
.so (net0254 ),
.sd (chunk1_bso ),
.ck (net341 ) );
bw_u1_minbuf_1x si_minbuf1 (
.z (misc_si_2 ),
.a (misc_si_1 ) );
bw_io_misc_rpt rpt0 (
.in2 (bscan_mode_ctl_in ),
.out2 (net343 ),
.out3 (net342 ),
.out4 (net341 ),
.out5 (net340 ),
.out6 (net339 ),
.out7 (net338 ),
.in3 (bscan_shift_dr_in ),
.in4 (bscan_clock_dr_in ),
.in5 (bscan_update_dr_in ),
.in6 (reset_l ),
.in7 (pad_misc_se ),
.in1 (bscan_hiz_l_in ),
.out1 (net344 ) );
bw_io_misc_rpt rpt1 (
.in2 (net343 ),
.out2 (net329 ),
.out3 (net328 ),
.out4 (net327 ),
.out5 (net326 ),
.out6 (net325 ),
.out7 (net324 ),
.in3 (net342 ),
.in4 (net341 ),
.in5 (net340 ),
.in6 (net339 ),
.in7 (net338 ),
.in1 (net344 ),
.out1 (net330 ) );
bw_io_misc_rpt rpt2 (
.in2 (net329 ),
.out2 (net287 ),
.out3 (net286 ),
.out4 (net285 ),
.out5 (net284 ),
.out6 (net283 ),
.out7 (net282 ),
.in3 (net328 ),
.in4 (net327 ),
.in5 (net326 ),
.in6 (net325 ),
.in7 (net324 ),
.in1 (net330 ),
.out1 (net288 ) );
bw_io_misc_rpt rpt3 (
.in2 (net287 ),
.out2 (net301 ),
.out3 (net300 ),
.out4 (net299 ),
.out5 (net298 ),
.out6 (net297 ),
.out7 (net296 ),
.in3 (net286 ),
.in4 (net285 ),
.in5 (net284 ),
.in6 (net283 ),
.in7 (net282 ),
.in1 (net288 ),
.out1 (net302 ) );
bw_io_misc_rpt rpt4 (
.in2 (net301 ),
.out2 (bscan_mode_ctl_out ),
.out3 (bscan_shift_dr_out ),
.out4 (bscan_clock_dr_out ),
.out5 (bscan_update_dr_out ),
.out6 (net346 ),
.out7 (net305 ),
.in3 (net300 ),
.in4 (net299 ),
.in5 (net298 ),
.in6 (vss ),
.in7 (vss ),
.in1 (net302 ),
.out1 (bscan_hiz_l_out ) );
bw_u1_buf_20x so_buf (
.z (pad_misc_so ),
.a (net0257 ) );
bw_u1_scanl_2x lockup_so (
.so (net0257 ),
.sd (chunk5_so ),
.ck (net0251 ) );
bw_io_hstl_drv hstl_vref_dummy (
.cbu ({vss ,vss ,vss ,vss ,vdd ,vdd ,vdd ,vdd } ),
.cbd ({vss ,vss ,vss ,vss ,vdd ,vdd ,vdd ,vdd } ),
.pad (hstl_vref ),
.sel_data_n (vss ),
.pad_up (vss ),
.pad_dn_l (vdd ),
.por (vss ),
.bsr_up (vss ),
.bsr_dn_l (vdd ),
.vddo (vddo ) );
bw_io_misc_chunk1 chunk1 (
.obsel ({vss ,vss } ),
.io_ext_int_l (io_ext_int_l ),
.spare_misc_pinoe (spare_misc_pinoe ),
.sel_bypass (vss ),
.vss_sense (vss_sense ),
.vdd_sense (vdd_sense ),
.test_mode (test_mode ),
.ext_int_l (ext_int_l ),
.temp_trig (temp_trig ),
.spare_misc_pindata (spare_misc_pindata ),
.ckd (vss ),
.vref (hstl_vref ),
.vddo (vddo ),
.clk_stretch (clk_stretch ),
.hiz_l (net344 ),
.rst_val_dn (vdd ),
.rst_val_up (vdd ),
.reset_l (net339 ),
.mode_ctl (net343 ),
.update_dr (net340 ),
.io_test_mode (io_test_mode ),
.shift_dr (net342 ),
.clock_dr (net341 ),
.io_clk_stretch (io_clk_stretch ),
.por_l (vdd ),
.rst_io_l (vdd ),
.bsi (chunk2_bso ),
.se (net338 ),
.si (header_si ),
.so (chunk1_so ),
.bso (chunk1_bso ),
.clk (rclk ),
.io_pgrm_en (io_pgrm_en ),
.io_burnin (io_burnin ),
.burnin (burnin ),
.pgrm_en (pgrm_en ),
.io_temp_trig (io_temp_trig ),
.pwron_rst_l (pwron_rst_l ),
.io_pwron_rst_l (io_pwron_rst_l ),
.spare_misc_pin (spare_misc_pin ),
.spare_misc_pin_to_core (spare_misc_pin_to_core ) );
bw_io_misc_chunk2 chunk2 (
.obsel ({vss ,vss } ),
.io_pll_char_in (io_pll_char_in ),
.sel_bypass (vss ),
.tck2 (tck2 ),
.io_tck2 (io_tck2 ),
.pll_char_in (pll_char_in ),
.ssi_mosi (ssi_mosi ),
.jbi_io_ssi_mosi (jbi_io_ssi_mosi ),
.ssi_miso (ssi_miso ),
.io_jbi_ssi_miso (io_jbi_ssi_miso ),
.vddo (vddo ),
.vref (hstl_vref ),
.ckd (vss ),
.so (chunk2_so ),
.bso (chunk2_bso ),
.rst_val_up (vdd ),
.rst_val_dn (vdd ),
.reset_l (net325 ),
.si (chunk1_so ),
.se (net324 ),
.bsi (chunk3_bso ),
.rst_io_l (vdd ),
.hiz_l (net330 ),
.shift_dr (net328 ),
.update_dr (net326 ),
.clock_dr (net327 ),
.mode_ctl (net329 ),
.clk (rclk ),
.por_l (vdd ) );
bw_io_misc_chunk3 chunk3 (
.spare_misc_pad ({spare_misc_pad[0] } ),
.spare_misc_paddata ({spare_misc_paddata[0] } ),
.spare_misc_pad_to_core ({spare_misc_pad_to_core[0] } ),
.obsel ({vss ,vss } ),
.spare_misc_padoe ({spare_misc_padoe[0] } ),
.ssi_sck (ssi_sck ),
.jbi_io_ssi_sck (jbi_io_ssi_sck ),
.trigin (trigin ),
.io_trigin (io_trigin ),
.io_tms (io_tms ),
.io_vreg_selbg_l (io_vreg_selbg_l ),
.clk (rclk ),
.ckd (vss ),
.vref (hstl_vref ),
.vddo (vddo ),
.rst_val_up (vdd ),
.tms (tms ),
.sel_bypass (vss ),
.mode_ctl (net287 ),
.rst_val_dn (vdd ),
.bsi (net412 ),
.clock_dr (net285 ),
.shift_dr (net286 ),
.hiz_l (net288 ),
.update_dr (net284 ),
.rst_io_l (vdd ),
.por_l (vdd ),
.se (net282 ),
.si (chunk2_so ),
.reset_l (net283 ),
.so (net413 ),
.bso (chunk3_bso ),
.hstl_vref (hstl_vref ),
.vreg_selbg_l (vreg_selbg_l ) );
bw_u1_buf_30x bso_buf (
.z (pad_misc_bso ),
.a (net0254 ) );
bw_io_misc_chunk5 chunk5 (
.spare_misc_pad ({spare_misc_pad[2:1] } ),
.spare_misc_paddata ({spare_misc_paddata[2:1] } ),
.obsel ({vss ,vss } ),
.spare_misc_padoe ({spare_misc_padoe[2:1] } ),
.spare_misc_pad_to_core ({spare_misc_pad_to_core[2:1] } ),
.clk (rclk ),
.sel_bypass (vss ),
.io_tdo_en (io_tdo_en ),
.ckd (vss ),
.vref (hstl_vref ),
.vddo (vddo ),
.io_tdo (io_tdo ),
.rst_val_up (vdd ),
.io_tdi (io_tdi ),
.mode_ctl (net301 ),
.rst_val_dn (vdd ),
.io_trst_l (io_trst_l ),
.bsi (pad_misc_bsi ),
.io_tck (io_tck ),
.clock_dr (net299 ),
.tck (tck ),
.shift_dr (net300 ),
.trst_l (trst_l ),
.hiz_l (net302 ),
.tdi (tdi ),
.update_dr (net298 ),
.rst_io_l (vdd ),
.por_l (vdd ),
.tdo (tdo ),
.se (net296 ),
.si (net413 ),
.reset_l (net297 ),
.so (chunk5_so ),
.bso (net412 ) );
bw_io_misc_chunk6 chunk6 (
.io_pmi (io_pmi ),
.pcm_misc_oe (pcm_misc_oe ),
.vddo (vddo ),
.pmo (pmo ),
.io_pmo (io_pmo ),
.por_l (vdd ),
.pmi (pmi ) );
endmodule
|
module sky130_fd_sc_ms__nor3b (
Y ,
A ,
B ,
C_N ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input C_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
|
module sky130_fd_sc_hvl__lsbufhv2lv_simple (
X ,
A ,
VPWR ,
VGND ,
LVPWR,
VPB ,
VNB
);
output X ;
input A ;
input VPWR ;
input VGND ;
input LVPWR;
input VPB ;
input VNB ;
endmodule
|
module sc_0_1_dbg_rptr(/*AUTOARG*/
// Outputs
l2_dbgbus_out, enable_01, so,
// Inputs
dbgbus_b0, dbgbus_b1, rclk, si, se
);
output [39:0] l2_dbgbus_out ;
output enable_01;
input [40:0] dbgbus_b0;
input [40:0] dbgbus_b1;
input rclk;
input si, se;
output so;
wire [39:0] l2_dbgbus_out_prev ;
wire enable_01_prev;
wire int_scanout;
// connect scanout of the last flop to int_scanout.
// The output of the lockup latch is
// the scanout of this dbb (so)
bw_u1_scanlg_2x so_lockup(.so(so), .sd(int_scanout), .ck(rclk), .se(se));
// Row0
mux2ds #(20) mux_dbgmuxb01_row0 (.dout (l2_dbgbus_out_prev[19:0]),
.in0(dbgbus_b0[19:0]),
.in1(dbgbus_b1[19:0]),
.sel0(dbgbus_b0[40]),
.sel1(~dbgbus_b0[40]));
dff_s #(20) ff_dbgmuxb01_row0 (.q(l2_dbgbus_out[19:0]),
.din(l2_dbgbus_out_prev[19:0]),
.clk(rclk), .se(1'b0), .si(), .so() );
// Row1
mux2ds #(20) mux_dbgmuxb01_row1 (.dout (l2_dbgbus_out_prev[39:20]),
.in0(dbgbus_b0[39:20]),
.in1(dbgbus_b1[39:20]),
.sel0(dbgbus_b0[40]),
.sel1(~dbgbus_b0[40]));
dff_s #(20) ff_dbgmuxb01_row1 (.q(l2_dbgbus_out[39:20]),
.din(l2_dbgbus_out_prev[39:20]),
.clk(rclk), .se(1'b0), .si(), .so() );
assign enable_01_prev = dbgbus_b0[40] | dbgbus_b1[40] ;
dff_s #(1) ff_valid (.q(enable_01),
.din(enable_01_prev),
.clk(rclk), .se(1'b0), .si(), .so() );
endmodule
|
module alu
#(parameter nat_w = `SENIOR_NATIVE_WIDTH,
parameter ctrl_w = `ALU_CTRL_WIDTH,
parameter mac_flags_w = `MAC_NUM_FLAGS,
parameter alu_flags_w = `ALU_NUM_FLAGS,
parameter spr_dat_w = `SPR_DATA_BUS_WIDTH,
parameter spr_adr_w = `SPR_ADR_BUS_WIDTH
)
(
input wire clk_i,
input wire reset_i,
input wire [ctrl_w-1:0] ctrl_i,
input wire [nat_w-1:0] opa_i,
input wire [nat_w-1:0] opb_i,
input wire condition_check_i,
input wire [mac_flags_w-1:0] mac_flags_i,
output wire [alu_flags_w-1:0] flags_o,
output wire [mac_flags_w-1:0] masked_mac_flags_o,
output reg [nat_w-1:0] result_o,
output reg [nat_w-1:0] result_unr_o,
input wire [spr_dat_w-1:0] spr_dat_i,
input wire [spr_adr_w-1:0] spr_adr_i,
input wire spr_wren_i,
output reg [spr_dat_w-1:0] spr_dat_o
);
`include "std_messages.vh"
// Internal Declarations
reg [1:0] opa_sel_sig;
reg [nat_w-1:0] opa_sig;
reg [nat_w-1:0] opb_sig;
wire [(nat_w-1):0] add_sig;
wire add_carry;
reg max_sig;
reg [nat_w-1:0] mxmn_sig;
reg cin_sig;
reg [nat_w-1:0] add_sat_sig;
reg led_cnt_sig;
reg [nat_w-1:0] led_sig;
reg [nat_w-1:0] logic_sig;
reg [(nat_w-1)+1:0] shift_sig;
reg [(mac_flags_w+alu_flags_w)-1:0] aox_flag_sig;
reg [alu_flags_w-1:0] flags_reg;
reg [alu_flags_w-1:0] flags_sig;
wire mx_minmax;
wire mx_opa_inv;
wire [1:0] mx_ci;
min_max_ctrl min_max_ctrl
(
// Outputs
.mx_minmax_o (mx_minmax),
// Inputs
.function_i (ctrl_i`ALU_FUNCTION),
.opb_sign_i (opb_i[nat_w-1]),
.opa_sign_i (opa_i[nat_w-1]),
.carry_i (add_carry)
);
adder_ctrl adder_ctrl
(
// Outputs
.mx_opa_inv_o (mx_opa_inv),
.mx_ci_o (mx_ci),
// Inputs
.function_i (ctrl_i`ALU_FUNCTION),
.opa_sign_i (opa_i[nat_w-1])
);
assign flags_o = flags_reg;
assign masked_mac_flags_o[`MAC_FLAG_MZ]=aox_flag_sig[4];
assign masked_mac_flags_o[`MAC_FLAG_MN]=aox_flag_sig[5];
assign masked_mac_flags_o[`MAC_FLAG_MS]=aox_flag_sig[6];
assign masked_mac_flags_o[`MAC_FLAG_MV]=aox_flag_sig[7];
// Compute Adder
assign {add_carry,add_sig}=opa_sig+opb_sig+cin_sig;
wire add_pos_overflow;
wire add_neg_overflow;
wire abs_overflow;
assign add_pos_overflow = ~opa_sig[nat_w-1] & ~opb_sig[nat_w-1] & add_sig[nat_w-1];
assign add_neg_overflow = opa_sig[nat_w-1] & opb_sig[nat_w-1] & ~add_sig[nat_w-1];
assign abs_overflow = opa_i[nat_w-1] & add_sig[nat_w-1];
// Mux to select mux signal for Operand A
always @(*) begin
case (ctrl_i`ALU_OPA)
2'b00: opa_sel_sig=2'b00;
2'b01: opa_sel_sig=2'b01;
2'b10: opa_sel_sig={1'b0,opa_i[15]};
2'b11: opa_sel_sig=2'b11;
endcase
end
//Mux to select Operand A
always@* begin
case(mx_opa_inv)
1'b0: opa_sig=opa_i;
1'b1: opa_sig=~(opa_i);
endcase // case(mx_opa_inv)
end
//Mux to select Operand B
always@(*) begin
casex(ctrl_i`ALU_OPB)
2'b00: opb_sig=opb_i;
2'b01: opb_sig=0;
2'b1x: opb_sig=opb_i;
endcase
end
//Mux to select Carry for adder
always@* begin
case(mx_ci)
2'b00: cin_sig = 0;
2'b01: cin_sig = 1;
2'b10: cin_sig = flags_reg[`ALU_FLAG_AC];
default: begin
cin_sig=0;
if(defined_but_illegal(mx_ci,2,"mx_ci")) begin
$stop;
end
end
endcase // case(mx_ci_o)
end
always@* begin
case (mx_minmax)
1'b0: mxmn_sig=opa_i;
1'b1: mxmn_sig=opb_i;
endcase
end
reg sat_carry;
//Check Saturation
always@(*) begin
sat_carry = 0;
casex ({ctrl_i`ALU_ABS_SAT,add_neg_overflow,add_pos_overflow})
3'b000: add_sat_sig=add_sig;
3'b001: begin
add_sat_sig=16'b0111111111111111;
sat_carry = 1;
end
3'b010: begin
add_sat_sig=16'b1000000000000000;
sat_carry = 1;
end
3'b011: begin
add_sat_sig=add_sig;
$display("illagal to be here");
$stop;
end
3'b1xx: begin
add_sat_sig=abs_overflow ? 16'h7fff : add_sig;
end
endcase
end
//Mux to select the Leading bit to be counted
always@(*) begin
case (ctrl_i`ALU_LED)
2'b00: led_cnt_sig=1'b0;
2'b01: led_cnt_sig=1'b1;
2'b10: led_cnt_sig=opa_i[15];
2'b11: led_cnt_sig=flags_reg[`ALU_FLAG_AC];
endcase
end
// compute leading x
always@(*) begin
if(led_cnt_sig) begin
casex(opa_i)
16'b0xxxxxxxxxxxxxxx: led_sig = 16'd0;
16'b1111111111111111: led_sig = 16'd16;
16'b111111111111111x: led_sig = 16'd15;
16'b11111111111111xx: led_sig = 16'd14;
16'b1111111111111xxx: led_sig = 16'd13;
16'b111111111111xxxx: led_sig = 16'd12;
16'b11111111111xxxxx: led_sig = 16'd11;
16'b1111111111xxxxxx: led_sig = 16'd10;
16'b111111111xxxxxxx: led_sig = 16'd9;
16'b11111111xxxxxxxx: led_sig = 16'd8;
16'b1111111xxxxxxxxx: led_sig = 16'd7;
16'b111111xxxxxxxxxx: led_sig = 16'd6;
16'b11111xxxxxxxxxxx: led_sig = 16'd5;
16'b1111xxxxxxxxxxxx: led_sig = 16'd4;
16'b111xxxxxxxxxxxxx: led_sig = 16'd3;
16'b11xxxxxxxxxxxxxx: led_sig = 16'd2;
16'b1xxxxxxxxxxxxxxx: led_sig = 16'd1;
endcase // casex(opa_i)
end
else begin
casex(opa_i)
16'b1xxxxxxxxxxxxxxx: led_sig = 16'd0;
16'b0000000000000000: led_sig = 16'd16;
16'b000000000000000x: led_sig = 16'd15;
16'b00000000000000xx: led_sig = 16'd14;
16'b0000000000000xxx: led_sig = 16'd13;
16'b000000000000xxxx: led_sig = 16'd12;
16'b00000000000xxxxx: led_sig = 16'd11;
16'b0000000000xxxxxx: led_sig = 16'd10;
16'b000000000xxxxxxx: led_sig = 16'd9;
16'b00000000xxxxxxxx: led_sig = 16'd8;
16'b0000000xxxxxxxxx: led_sig = 16'd7;
16'b000000xxxxxxxxxx: led_sig = 16'd6;
16'b00000xxxxxxxxxxx: led_sig = 16'd5;
16'b0000xxxxxxxxxxxx: led_sig = 16'd4;
16'b000xxxxxxxxxxxxx: led_sig = 16'd3;
16'b00xxxxxxxxxxxxxx: led_sig = 16'd2;
16'b0xxxxxxxxxxxxxxx: led_sig = 16'd1;
endcase // casex(opa_i)
end // else: !if(led_cnt_sig)
end // always@ (*)
//Mux and logic to select the logic operation
always@(*) begin
case (ctrl_i`ALU_LOGIC)
2'b00: logic_sig=opa_i & opb_i;
2'b01: logic_sig=opa_i | opb_i;
2'b10: logic_sig=opa_i ^ opb_i;
default: begin
logic_sig=0;
if(defined_but_illegal(ctrl_i`ALU_LOGIC,2,"ctrl_i`ALU_LOGIC")) begin
$stop;
end
end
endcase
end
wire signed [17:0] shift_vector;
reg right_shift_carry;
assign shift_vector = {opa_i[15], opa_i, 1'b0};
// Mux and logic for selecting shift type
always@(*) begin
right_shift_carry = 0;
case (ctrl_i`ALU_SHIFT)
//arithmetic right shift
3'b000: begin
{shift_sig,right_shift_carry} = shift_vector >>> opb_i[4:0];
end
// logical right shift
3'b010: begin
{shift_sig,right_shift_carry} = {1'b0, opa_i, 1'b0} >> opb_i[4:0];
end
3'b001: // arithmetic left shift
begin
shift_sig = {1'b0, opa_i} << opb_i[4:0];
end
3'b011: // logical left shift
begin
shift_sig = {1'b0, opa_i} << opb_i[4:0];
end
3'b100: // right rotation without carry
begin
shift_sig[16] = 0;
case(opb_i[3:0])
0: shift_sig[15:0]=opa_i;
1: shift_sig[15:0]={opa_i[0],opa_i[15:1]};
2: shift_sig[15:0]={opa_i[1:0],opa_i[15:2]};
3: shift_sig[15:0]={opa_i[2:0],opa_i[15:3]};
4: shift_sig[15:0]={opa_i[3:0],opa_i[15:4]};
5: shift_sig[15:0]={opa_i[4:0],opa_i[15:5]};
6: shift_sig[15:0]={opa_i[5:0],opa_i[15:6]};
7: shift_sig[15:0]={opa_i[6:0],opa_i[15:7]};
8: shift_sig[15:0]={opa_i[7:0],opa_i[15:8]};
9: shift_sig[15:0]={opa_i[8:0],opa_i[15:9]};
10: shift_sig[15:0]={opa_i[9:0],opa_i[15:10]};
11: shift_sig[15:0]={opa_i[10:0],opa_i[15:11]};
12: shift_sig[15:0]={opa_i[11:0],opa_i[15:12]};
13: shift_sig[15:0]={opa_i[12:0],opa_i[15:13]};
14: shift_sig[15:0]={opa_i[13:0],opa_i[15:14]};
15: shift_sig[15:0]={opa_i[14:0],opa_i[15]};
endcase
end
// left rotation without carry
3'b101: begin
shift_sig[16] = 0;
case(opb_i[3:0])
0: shift_sig[15:0]=opa_i;
1: shift_sig[15:0]={opa_i[14:0],opa_i[15]};
2: shift_sig[15:0]={opa_i[13:0],opa_i[15:14]};
3: shift_sig[15:0]={opa_i[12:0],opa_i[15:13]};
4: shift_sig[15:0]={opa_i[11:0],opa_i[15:12]};
5: shift_sig[15:0]={opa_i[10:0],opa_i[15:11]};
6: shift_sig[15:0]={opa_i[9:0],opa_i[15:10]};
7: shift_sig[15:0]={opa_i[8:0],opa_i[15:9]};
8: shift_sig[15:0]={opa_i[7:0],opa_i[15:8]};
9: shift_sig[15:0]={opa_i[6:0],opa_i[15:7]};
10: shift_sig[15:0]={opa_i[5:0],opa_i[15:6]};
11: shift_sig[15:0]={opa_i[4:0],opa_i[15:5]};
12: shift_sig[15:0]={opa_i[3:0],opa_i[15:4]};
13: shift_sig[15:0]={opa_i[2:0],opa_i[15:3]};
14: shift_sig[15:0]={opa_i[1:0],opa_i[15:2]};
15: shift_sig[15:0]={opa_i[0],opa_i[15:1]};
endcase
end
//right rotation with carry
3'b110: begin
case(opb_i[4:0])
0: shift_sig={flags_reg[`ALU_FLAG_AC],opa_i};
1: shift_sig={opa_i[0],flags_reg[`ALU_FLAG_AC],opa_i[15:1]};
2: shift_sig={opa_i[1:0],flags_reg[`ALU_FLAG_AC],opa_i[15:2]};
3: shift_sig={opa_i[2:0],flags_reg[`ALU_FLAG_AC],opa_i[15:3]};
4: shift_sig={opa_i[3:0],flags_reg[`ALU_FLAG_AC],opa_i[15:4]};
5: shift_sig={opa_i[4:0],flags_reg[`ALU_FLAG_AC],opa_i[15:5]};
6: shift_sig={opa_i[5:0],flags_reg[`ALU_FLAG_AC],opa_i[15:6]};
7: shift_sig={opa_i[6:0],flags_reg[`ALU_FLAG_AC],opa_i[15:7]};
8: shift_sig={opa_i[7:0],flags_reg[`ALU_FLAG_AC],opa_i[15:8]};
9: shift_sig={opa_i[8:0],flags_reg[`ALU_FLAG_AC],opa_i[15:9]};
10: shift_sig={opa_i[9:0],flags_reg[`ALU_FLAG_AC],opa_i[15:10]};
11: shift_sig={opa_i[10:0],flags_reg[`ALU_FLAG_AC],opa_i[15:11]};
12: shift_sig={opa_i[11:0],flags_reg[`ALU_FLAG_AC],opa_i[15:12]};
13: shift_sig={opa_i[12:0],flags_reg[`ALU_FLAG_AC],opa_i[15:13]};
14: shift_sig={opa_i[13:0],flags_reg[`ALU_FLAG_AC],opa_i[15:14]};
15: shift_sig={opa_i[14:0],flags_reg[`ALU_FLAG_AC],opa_i[15]};
16: shift_sig={opa_i[15:0],flags_reg[`ALU_FLAG_AC]};
default: begin
shift_sig={opa_i[15:0],flags_reg[`ALU_FLAG_AC]};
$display("Warning: undefined value (%h) used for right rotation with carry on opa_i[4:0] in %m", opa_i[4:0]);
end
endcase
end
3'b111: // left rotation with carry
begin
case(opb_i[4:0])
0: shift_sig={flags_reg[`ALU_FLAG_AC],opa_i[15:0]};
1: shift_sig={opa_i[15:0],flags_reg[`ALU_FLAG_AC]};
2: shift_sig={opa_i[14:0],flags_reg[`ALU_FLAG_AC],opa_i[15]};
3: shift_sig={opa_i[13:0],flags_reg[`ALU_FLAG_AC],opa_i[15:14]};
4: shift_sig={opa_i[12:0],flags_reg[`ALU_FLAG_AC],opa_i[15:13]};
5: shift_sig={opa_i[11:0],flags_reg[`ALU_FLAG_AC],opa_i[15:12]};
6: shift_sig={opa_i[10:0],flags_reg[`ALU_FLAG_AC],opa_i[15:11]};
7: shift_sig={opa_i[9:0],flags_reg[`ALU_FLAG_AC],opa_i[15:10]};
8: shift_sig={opa_i[8:0],flags_reg[`ALU_FLAG_AC],opa_i[15:9]};
9: shift_sig={opa_i[7:0],flags_reg[`ALU_FLAG_AC],opa_i[15:8]};
10: shift_sig={opa_i[6:0],flags_reg[`ALU_FLAG_AC],opa_i[15:7]};
11: shift_sig={opa_i[5:0],flags_reg[`ALU_FLAG_AC],opa_i[15:6]};
12: shift_sig={opa_i[4:0],flags_reg[`ALU_FLAG_AC],opa_i[15:5]};
13: shift_sig={opa_i[3:0],flags_reg[`ALU_FLAG_AC],opa_i[15:4]};
14: shift_sig={opa_i[2:0],flags_reg[`ALU_FLAG_AC],opa_i[15:3]};
15: shift_sig={opa_i[1:0],flags_reg[`ALU_FLAG_AC],opa_i[15:2]};
16: shift_sig={opa_i[0],flags_reg[`ALU_FLAG_AC],opa_i[15:1]};
default: begin
shift_sig=0;
$display("Warning: undefined value (%h) used for left rotation with carry on opa_i[4:0] in %m", opa_i[4:0]);
end
endcase
end
endcase
end
reg [nat_w-1:0] result;
// Mux for selecting the output operation
always@* begin
case (ctrl_i`ALU_OUT)
3'b000: result=led_sig;
3'b001: result=shift_sig[15:0];
3'b010: result=logic_sig;
3'b011: result=mxmn_sig;
3'b100: result=add_sig;
3'b101: result=add_sat_sig;
3'b110: result={8'b0, //Reserved
aox_flag_sig[7], //MV
aox_flag_sig[6], //MS
aox_flag_sig[5], //MN
aox_flag_sig[4], //MZ
flags_reg[`ALU_FLAG_AV],
flags_reg[`ALU_FLAG_AC],
flags_reg[`ALU_FLAG_AN],
flags_reg[`ALU_FLAG_AZ]};
default: begin
result=add_sat_sig;
if(defined_but_illegal(ctrl_i`ALU_OUT,3,"ctrl_i`ALU_OUT")) begin
$stop;
end
end
endcase
end
always @(*) begin
result_unr_o = result;
end
always@(posedge clk_i) begin
result_o <= result;
end
// and or xor flags
always@(*) begin
case (ctrl_i`ALU_AOX)
2'b00:
begin
aox_flag_sig[0] = flags_reg[`ALU_FLAG_AZ] & opa_i[0];
aox_flag_sig[1] = flags_reg[`ALU_FLAG_AN] & opa_i[1];
aox_flag_sig[2] = flags_reg[`ALU_FLAG_AC] & opa_i[2];
aox_flag_sig[3] = flags_reg[`ALU_FLAG_AV] & opa_i[3];
aox_flag_sig[4] = mac_flags_i[`MAC_FLAG_MZ] & opa_i[4];
aox_flag_sig[5] = mac_flags_i[`MAC_FLAG_MN] & opa_i[5];
aox_flag_sig[6] = mac_flags_i[`MAC_FLAG_MS] & opa_i[6];
aox_flag_sig[7] = mac_flags_i[`MAC_FLAG_MV] & opa_i[7];
end
2'b10:
begin
aox_flag_sig[0] = flags_reg[`ALU_FLAG_AZ] ^ opa_i[0];
aox_flag_sig[1] = flags_reg[`ALU_FLAG_AN] ^ opa_i[1];
aox_flag_sig[2] = flags_reg[`ALU_FLAG_AC] ^ opa_i[2];
aox_flag_sig[3] = flags_reg[`ALU_FLAG_AV] ^ opa_i[3];
aox_flag_sig[4] = mac_flags_i[`MAC_FLAG_MZ] ^ opa_i[4];
aox_flag_sig[5] = mac_flags_i[`MAC_FLAG_MN] ^ opa_i[5];
aox_flag_sig[6] = mac_flags_i[`MAC_FLAG_MS] ^ opa_i[6];
aox_flag_sig[7] = mac_flags_i[`MAC_FLAG_MV] ^ opa_i[7];
end
2'b01:
begin
aox_flag_sig[0] = flags_reg[`ALU_FLAG_AZ] | opa_i[0];
aox_flag_sig[1] = flags_reg[`ALU_FLAG_AN] | opa_i[1];
aox_flag_sig[2] = flags_reg[`ALU_FLAG_AC] | opa_i[2];
aox_flag_sig[3] = flags_reg[`ALU_FLAG_AV] | opa_i[3];
aox_flag_sig[4] = mac_flags_i[`MAC_FLAG_MZ] | opa_i[4];
aox_flag_sig[5] = mac_flags_i[`MAC_FLAG_MN] | opa_i[5];
aox_flag_sig[6] = mac_flags_i[`MAC_FLAG_MS] | opa_i[6];
aox_flag_sig[7] = mac_flags_i[`MAC_FLAG_MV] | opa_i[7];
end
default: begin
aox_flag_sig = 0;
if(defined_but_illegal(ctrl_i`ALU_AOX,2,"ctrl_i`ALU_AOX")) begin
$stop;
end
end
endcase
end
// zero flag
always@(*) begin
case (ctrl_i`ALU_AZ)
2'b01: flags_sig[`ALU_FLAG_AZ]=~(|result);
2'b10: flags_sig[`ALU_FLAG_AZ]=aox_flag_sig[0];
default: flags_sig[`ALU_FLAG_AZ]=flags_reg[`ALU_FLAG_AZ];
endcase
end
// negative flag
always@(*) begin
case (ctrl_i`ALU_AN)
2'b01: flags_sig[`ALU_FLAG_AN]=result[15];
2'b10: flags_sig[`ALU_FLAG_AN]=aox_flag_sig[1];
default: flags_sig[`ALU_FLAG_AN]=flags_reg[`ALU_FLAG_AN];
endcase
end
// saturate/carry flag
always@(*) begin
case (ctrl_i`ALU_AC)
3'b000: flags_sig[`ALU_FLAG_AC]=flags_reg[`ALU_FLAG_AC];
3'b001: begin
flags_sig[`ALU_FLAG_AC]=opa_i[15];
$stop;
end
3'b010: begin
case(ctrl_i`ALU_SHIFT)
3'b000: flags_sig[`ALU_FLAG_AC]=right_shift_carry;
3'b001: flags_sig[`ALU_FLAG_AC]=shift_sig[16];
3'b010: flags_sig[`ALU_FLAG_AC]=right_shift_carry;
3'b011: flags_sig[`ALU_FLAG_AC]=shift_sig[16];
3'b100: flags_sig[`ALU_FLAG_AC]=shift_sig[15];
3'b101: flags_sig[`ALU_FLAG_AC]=shift_sig[0];
3'b110: flags_sig[`ALU_FLAG_AC]=shift_sig[16];
3'b111: flags_sig[`ALU_FLAG_AC]=shift_sig[16];
endcase // casex(ctrl_i`ALU_shift)
end
3'b011: flags_sig[`ALU_FLAG_AC]=add_carry;
3'b100: flags_sig[`ALU_FLAG_AC]=aox_flag_sig[2];
3'b101: flags_sig[`ALU_FLAG_AC]=add_carry;
3'b110: flags_sig[`ALU_FLAG_AC]=sat_carry;
3'b111: flags_sig[`ALU_FLAG_AC]=0;
endcase
end
//overflow flag
always@(*) begin
case (ctrl_i`ALU_AV)
2'b00: flags_sig[`ALU_FLAG_AV]=flags_reg[`ALU_FLAG_AV];
2'b01: flags_sig[`ALU_FLAG_AV]=add_pos_overflow | add_neg_overflow ;
2'b10: flags_sig[`ALU_FLAG_AV]=aox_flag_sig[3];
2'b11: flags_sig[`ALU_FLAG_AV]=0;
default: begin
flags_sig[`ALU_FLAG_AV]=flags_reg[`ALU_FLAG_AV];
if(defined_but_illegal(ctrl_i`ALU_AV,2,"ctrl_i`ALU_AV")) begin
$stop;
end
end
endcase
end
reg spr_write_flags;
reg [spr_dat_w-1:`MAC_NUM_FLAGS+`ALU_NUM_FLAGS] spr_fl0_extra_store;
always@* begin
spr_dat_o = 0;
case(spr_adr_i)
(`SPR_CP_GROUP+`SPR_STATUS_FLAGS): begin
spr_write_flags = spr_wren_i;
spr_dat_o = {spr_fl0_extra_store,`MAC_NUM_FLAGS'b0,flags_reg};
end
default: spr_write_flags = 0;
endcase // case(spr_adr_i)
end
// register flags
always @(posedge clk_i) begin
if (!reset_i) begin
flags_reg<=0;
spr_fl0_extra_store <= 0;
end
else begin
if (spr_write_flags) begin
spr_fl0_extra_store <= spr_dat_i[spr_dat_w-1:`MAC_NUM_FLAGS+`ALU_NUM_FLAGS];
flags_reg <= spr_dat_i[3:0];
end
else if (condition_check_i) begin
flags_reg<=flags_sig;
end
end // else: !if(!reset_i)
end // always @ (posedge clk_i)
endmodule
|
module sky130_fd_sc_hdll__xnor3 (
//# {{data|Data Signals}}
input A,
input B,
input C,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
|
module sky130_fd_sc_hdll__sdfrtp (
Q ,
CLK ,
D ,
SCD ,
SCE ,
RESET_B
);
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input RESET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
|
module system_ov7670_controller_1_0(clk, resend, config_finished, sioc, siod, reset,
pwdn, xclk)
/* synthesis syn_black_box black_box_pad_pin="clk,resend,config_finished,sioc,siod,reset,pwdn,xclk" */;
input clk;
input resend;
output config_finished;
output sioc;
inout siod;
output reset;
output pwdn;
output xclk;
endmodule
|
module outputs)
wire clk; // From I73 of bw_u1_ckbuf_33x.v
wire scan_data_0; // From spare_ff_5_ of bw_u1_soffasr_2x.v
wire scan_data_1; // From spare_ff_4_ of bw_u1_soffasr_2x.v
wire scan_data_10; // From gdbginit_ff of bw_u1_soffasr_2x.v
wire scan_data_11; // From gclk_ff of bw_u1_soffasr_2x.v
wire scan_data_2; // From spare_ff_3_ of bw_u1_soffasr_2x.v
wire scan_data_3; // From spare_ff_2_ of bw_u1_soffasr_2x.v
wire scan_data_4; // From spare_ff_1_ of bw_u1_soffasr_2x.v
wire scan_data_5; // From spare_ff_0_ of bw_u1_soffasr_2x.v
wire scan_data_6; // From jbussync2_ff of bw_u1_soffasr_2x.v
wire scan_data_7; // From jbussync1_ff of bw_u1_soffasr_2x.v
wire scan_data_8; // From ddrsync2_ff of bw_u1_soffasr_2x.v
wire scan_data_9; // From ddrsync1_ff of bw_u1_soffasr_2x.v
// End of automatics
/* bw_u1_ckbuf_33x AUTO_TEMPLATE (
.clk (clk ),
.rclk (gclk ) ); */
bw_u1_ckbuf_33x I73
(/*AUTOINST*/
// Outputs
.clk (clk ), // Templated
// Inputs
.rclk (gclk )); // Templated
/* bw_u1_soffasr_2x AUTO_TEMPLATE (
.q (sparc_out[@]),
.d (spare_in[@]),
.ck (clk ),
.r_l (agrst_l ),
.s_l (1'b1),
.sd (scan_data_@"(- 4 @)" ),
.so (scan_data_@"(- 5 @)" ),
); */
bw_u1_soffasr_2x spare_ff_5_
(
// Inputs
.sd (sd ),
/*AUTOINST*/
// Outputs
.q (sparc_out[5]), // Templated
.so (scan_data_0 ), // Templated
// Inputs
.ck (clk ), // Templated
.d (spare_in[5]), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (se));
bw_u1_soffasr_2x spare_ff_4_
(
/*AUTOINST*/
// Outputs
.q (sparc_out[4]), // Templated
.so (scan_data_1 ), // Templated
// Inputs
.ck (clk ), // Templated
.d (spare_in[4]), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (se),
.sd (scan_data_0 )); // Templated
bw_u1_soffasr_2x spare_ff_3_
(
/*AUTOINST*/
// Outputs
.q (sparc_out[3]), // Templated
.so (scan_data_2 ), // Templated
// Inputs
.ck (clk ), // Templated
.d (spare_in[3]), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (se),
.sd (scan_data_1 )); // Templated
bw_u1_soffasr_2x spare_ff_2_
(
/*AUTOINST*/
// Outputs
.q (sparc_out[2]), // Templated
.so (scan_data_3 ), // Templated
// Inputs
.ck (clk ), // Templated
.d (spare_in[2]), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (se),
.sd (scan_data_2 )); // Templated
bw_u1_soffasr_2x spare_ff_1_
(
/*AUTOINST*/
// Outputs
.q (sparc_out[1]), // Templated
.so (scan_data_4 ), // Templated
// Inputs
.ck (clk ), // Templated
.d (spare_in[1]), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (se),
.sd (scan_data_3 )); // Templated
bw_u1_soffasr_2x spare_ff_0_
(
/*AUTOINST*/
// Outputs
.q (sparc_out[0]), // Templated
.so (scan_data_5 ), // Templated
// Inputs
.ck (clk ), // Templated
.d (spare_in[0]), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (se),
.sd (scan_data_4 )); // Templated
/* bw_u1_soffasr_2x AUTO_TEMPLATE (
.q (cken_out[@] ),
.d (cken_in[@] ),
.ck (clk ),
.r_l (agrst_l ),
.s_l (1'b1),
.se (1'b0),
.sd (1'b0),
.so (),
); */
bw_u1_soffasr_2x cken_ff_25_
( /*AUTOINST*/
// Outputs
.q (cken_out[25] ), // Templated
.so (), // Templated
// Inputs
.ck (clk ), // Templated
.d (cken_in[25] ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (1'b0), // Templated
.sd (1'b0)); // Templated
bw_u1_soffasr_2x cken_ff_24_
( /*AUTOINST*/
// Outputs
.q (cken_out[24] ), // Templated
.so (), // Templated
// Inputs
.ck (clk ), // Templated
.d (cken_in[24] ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (1'b0), // Templated
.sd (1'b0)); // Templated
bw_u1_soffasr_2x cken_ff_23_
( /*AUTOINST*/
// Outputs
.q (cken_out[23] ), // Templated
.so (), // Templated
// Inputs
.ck (clk ), // Templated
.d (cken_in[23] ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (1'b0), // Templated
.sd (1'b0)); // Templated
bw_u1_soffasr_2x cken_ff_22_
( /*AUTOINST*/
// Outputs
.q (cken_out[22] ), // Templated
.so (), // Templated
// Inputs
.ck (clk ), // Templated
.d (cken_in[22] ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (1'b0), // Templated
.sd (1'b0)); // Templated
bw_u1_soffasr_2x cken_ff_21_
( /*AUTOINST*/
// Outputs
.q (cken_out[21] ), // Templated
.so (), // Templated
// Inputs
.ck (clk ), // Templated
.d (cken_in[21] ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (1'b0), // Templated
.sd (1'b0)); // Templated
bw_u1_soffasr_2x cken_ff_20_
( /*AUTOINST*/
// Outputs
.q (cken_out[20] ), // Templated
.so (), // Templated
// Inputs
.ck (clk ), // Templated
.d (cken_in[20] ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (1'b0), // Templated
.sd (1'b0)); // Templated
bw_u1_soffasr_2x cken_ff_19_
( /*AUTOINST*/
// Outputs
.q (cken_out[19] ), // Templated
.so (), // Templated
// Inputs
.ck (clk ), // Templated
.d (cken_in[19] ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (1'b0), // Templated
.sd (1'b0)); // Templated
bw_u1_soffasr_2x cken_ff_18_
( /*AUTOINST*/
// Outputs
.q (cken_out[18] ), // Templated
.so (), // Templated
// Inputs
.ck (clk ), // Templated
.d (cken_in[18] ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (1'b0), // Templated
.sd (1'b0)); // Templated
bw_u1_soffasr_2x cken_ff_17_
( /*AUTOINST*/
// Outputs
.q (cken_out[17] ), // Templated
.so (), // Templated
// Inputs
.ck (clk ), // Templated
.d (cken_in[17] ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (1'b0), // Templated
.sd (1'b0)); // Templated
bw_u1_soffasr_2x cken_ff_16_
( /*AUTOINST*/
// Outputs
.q (cken_out[16] ), // Templated
.so (), // Templated
// Inputs
.ck (clk ), // Templated
.d (cken_in[16] ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (1'b0), // Templated
.sd (1'b0)); // Templated
bw_u1_soffasr_2x cken_ff_15_
( /*AUTOINST*/
// Outputs
.q (cken_out[15] ), // Templated
.so (), // Templated
// Inputs
.ck (clk ), // Templated
.d (cken_in[15] ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (1'b0), // Templated
.sd (1'b0)); // Templated
bw_u1_soffasr_2x cken_ff_14_
( /*AUTOINST*/
// Outputs
.q (cken_out[14] ), // Templated
.so (), // Templated
// Inputs
.ck (clk ), // Templated
.d (cken_in[14] ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (1'b0), // Templated
.sd (1'b0)); // Templated
bw_u1_soffasr_2x cken_ff_13_
( /*AUTOINST*/
// Outputs
.q (cken_out[13] ), // Templated
.so (), // Templated
// Inputs
.ck (clk ), // Templated
.d (cken_in[13] ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (1'b0), // Templated
.sd (1'b0)); // Templated
bw_u1_soffasr_2x cken_ff_12_
( /*AUTOINST*/
// Outputs
.q (cken_out[12] ), // Templated
.so (), // Templated
// Inputs
.ck (clk ), // Templated
.d (cken_in[12] ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (1'b0), // Templated
.sd (1'b0)); // Templated
bw_u1_soffasr_2x cken_ff_11_
( /*AUTOINST*/
// Outputs
.q (cken_out[11] ), // Templated
.so (), // Templated
// Inputs
.ck (clk ), // Templated
.d (cken_in[11] ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (1'b0), // Templated
.sd (1'b0)); // Templated
bw_u1_soffasr_2x cken_ff_10_
( /*AUTOINST*/
// Outputs
.q (cken_out[10] ), // Templated
.so (), // Templated
// Inputs
.ck (clk ), // Templated
.d (cken_in[10] ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (1'b0), // Templated
.sd (1'b0)); // Templated
bw_u1_soffasr_2x cken_ff_9_
( /*AUTOINST*/
// Outputs
.q (cken_out[9] ), // Templated
.so (), // Templated
// Inputs
.ck (clk ), // Templated
.d (cken_in[9] ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (1'b0), // Templated
.sd (1'b0)); // Templated
bw_u1_soffasr_2x cken_ff_8_
( /*AUTOINST*/
// Outputs
.q (cken_out[8] ), // Templated
.so (), // Templated
// Inputs
.ck (clk ), // Templated
.d (cken_in[8] ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (1'b0), // Templated
.sd (1'b0)); // Templated
bw_u1_soffasr_2x cken_ff_7_
( /*AUTOINST*/
// Outputs
.q (cken_out[7] ), // Templated
.so (), // Templated
// Inputs
.ck (clk ), // Templated
.d (cken_in[7] ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (1'b0), // Templated
.sd (1'b0)); // Templated
bw_u1_soffasr_2x cken_ff_6_
( /*AUTOINST*/
// Outputs
.q (cken_out[6] ), // Templated
.so (), // Templated
// Inputs
.ck (clk ), // Templated
.d (cken_in[6] ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (1'b0), // Templated
.sd (1'b0)); // Templated
bw_u1_soffasr_2x cken_ff_5_
( /*AUTOINST*/
// Outputs
.q (cken_out[5] ), // Templated
.so (), // Templated
// Inputs
.ck (clk ), // Templated
.d (cken_in[5] ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (1'b0), // Templated
.sd (1'b0)); // Templated
bw_u1_soffasr_2x cken_ff_4_
( /*AUTOINST*/
// Outputs
.q (cken_out[4] ), // Templated
.so (), // Templated
// Inputs
.ck (clk ), // Templated
.d (cken_in[4] ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (1'b0), // Templated
.sd (1'b0)); // Templated
bw_u1_soffasr_2x cken_ff_3_
( /*AUTOINST*/
// Outputs
.q (cken_out[3] ), // Templated
.so (), // Templated
// Inputs
.ck (clk ), // Templated
.d (cken_in[3] ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (1'b0), // Templated
.sd (1'b0)); // Templated
bw_u1_soffasr_2x cken_ff_2_
( /*AUTOINST*/
// Outputs
.q (cken_out[2] ), // Templated
.so (), // Templated
// Inputs
.ck (clk ), // Templated
.d (cken_in[2] ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (1'b0), // Templated
.sd (1'b0)); // Templated
bw_u1_soffasr_2x cken_ff_1_
( /*AUTOINST*/
// Outputs
.q (cken_out[1] ), // Templated
.so (), // Templated
// Inputs
.ck (clk ), // Templated
.d (cken_in[1] ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (1'b0), // Templated
.sd (1'b0)); // Templated
bw_u1_soffasr_2x cken_ff_0_
( /*AUTOINST*/
// Outputs
.q (cken_out[0] ), // Templated
.so (), // Templated
// Inputs
.ck (clk ), // Templated
.d (cken_in[0] ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (1'b0), // Templated
.sd (1'b0)); // Templated
/* bw_u1_soffasr_2x AUTO_TEMPLATE (
.ck (clk ),
.r_l (agrst_l ),
.s_l (1'b1),
.se (se ),
); */
bw_u1_soffasr_2x ddrsync1_ff
(
// Outputs
.q (ddrsync1_out ),
.so (scan_data_9 ),
// Inputs
.d (ddrsync1_in ),
.sd (scan_data_8 ),
/*AUTOINST*/
// Inputs
.ck (clk ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (se )); // Templated
bw_u1_soffasr_2x ddrsync2_ff
(
// Outputs
.q (ddrsync2_out ),
.so (scan_data_8 ),
// Inputs
.d (ddrsync2_in ),
.sd (scan_data_7 ),
/*AUTOINST*/
// Inputs
.ck (clk ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (se )); // Templated
bw_u1_soffasr_2x jbussync1_ff
(
// Outputs
.q (jbussync1_out ),
.so (scan_data_7 ),
// Inputs
.d (jbussync1_in ),
.sd (scan_data_6 ),
/*AUTOINST*/
// Inputs
.ck (clk ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (se )); // Templated
bw_u1_soffasr_2x jbussync2_ff
(
// Outputs
.q (jbussync2_out ),
.so (scan_data_6 ),
// Inputs
.d (jbussync2_in ),
.sd (scan_data_5 ),
/*AUTOINST*/
// Inputs
.ck (clk ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (se )); // Templated
bw_u1_soffasr_2x gdbginit_ff
(
// Outputs
.q (gdbginit_out ),
.so (scan_data_10 ),
// Inputs
.d (gdbginit_in ),
.sd (scan_data_9 ),
.r_l (adbginit_l),
/*AUTOINST*/
// Inputs
.ck (clk ), // Templated
.s_l (1'b1), // Templated
.se (se )); // Templated
bw_u1_soffasr_2x gclk_ff
(
// Outputs
.q (grst_out ),
.so (scan_data_11 ),
// Inputs
.d (grst_in ),
.sd (scan_data_10 ),
/*AUTOINST*/
// Inputs
.ck (clk ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (se )); // Templated
/* bw_u1_scanlg_2x AUTO_TEMPLATE (
.sd (scan_data_11 ),
.ck (clk ),
); */
bw_u1_scanlg_2x scanout_latch
( /*AUTOINST*/
// Outputs
.so (so),
// Inputs
.sd (scan_data_11 ), // Templated
.ck (clk ), // Templated
.se (1'b1));
endmodule
|
module sky130_fd_sc_ms__a2bb2oi (
Y ,
A1_N,
A2_N,
B1 ,
B2
);
output Y ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
|
module SevenSegDriver(D3, D2, D1, D0, Display, Reset, Clock, Select);
SevenSegDriver DisplayUnit(F1code,F0code,S1code,S0code,Display,Reset,clock,Transistors);
endmodule
|
module mult_16x16 (
input wire [15:0] A,
input wire [15:0] B,
output wire [31:0] Z
);
assign Z = A * B;
endmodule
|
module mult_20x18 (
input wire [19:0] A,
input wire [17:0] B,
output wire [37:0] Z
);
assign Z = A * B;
endmodule
|
module mult_8x8 (
input wire [ 7:0] A,
input wire [ 7:0] B,
output wire [15:0] Z
);
assign Z = A * B;
endmodule
|
module mult_10x9 (
input wire [ 9:0] A,
input wire [ 8:0] B,
output wire [18:0] Z
);
assign Z = A * B;
endmodule
|
module TimeHoldOver_Qsys_nios2_gen2_0_cpu_test_bench (
// inputs:
A_cmp_result,
A_ctrl_ld_non_bypass,
A_en,
A_exc_active_no_break_no_crst,
A_exc_allowed,
A_exc_any_active,
A_exc_hbreak_pri1,
A_exc_highest_pri_exc_id,
A_exc_inst_fetch,
A_exc_norm_intr_pri5,
A_st_data,
A_valid,
A_wr_data_unfiltered,
A_wr_dst_reg,
E_add_br_to_taken_history_unfiltered,
M_bht_ptr_unfiltered,
M_bht_wr_data_unfiltered,
M_bht_wr_en_unfiltered,
M_mem_baddr,
M_target_pcb,
M_valid,
W_badaddr_reg,
W_bstatus_reg,
W_dst_regnum,
W_dst_regset,
W_estatus_reg,
W_exception_reg,
W_iw,
W_iw_op,
W_iw_opx,
W_pcb,
W_status_reg,
W_valid,
W_vinst,
W_wr_dst_reg,
clk,
d_address,
d_byteenable,
d_read,
d_readdatavalid,
d_write,
i_address,
i_read,
i_readdatavalid,
reset_n,
// outputs:
A_wr_data_filtered,
E_add_br_to_taken_history_filtered,
M_bht_ptr_filtered,
M_bht_wr_data_filtered,
M_bht_wr_en_filtered,
test_has_ended
)
;
output [ 31: 0] A_wr_data_filtered;
output E_add_br_to_taken_history_filtered;
output [ 7: 0] M_bht_ptr_filtered;
output [ 1: 0] M_bht_wr_data_filtered;
output M_bht_wr_en_filtered;
output test_has_ended;
input A_cmp_result;
input A_ctrl_ld_non_bypass;
input A_en;
input A_exc_active_no_break_no_crst;
input A_exc_allowed;
input A_exc_any_active;
input A_exc_hbreak_pri1;
input [ 31: 0] A_exc_highest_pri_exc_id;
input A_exc_inst_fetch;
input A_exc_norm_intr_pri5;
input [ 31: 0] A_st_data;
input A_valid;
input [ 31: 0] A_wr_data_unfiltered;
input A_wr_dst_reg;
input E_add_br_to_taken_history_unfiltered;
input [ 7: 0] M_bht_ptr_unfiltered;
input [ 1: 0] M_bht_wr_data_unfiltered;
input M_bht_wr_en_unfiltered;
input [ 24: 0] M_mem_baddr;
input [ 24: 0] M_target_pcb;
input M_valid;
input [ 31: 0] W_badaddr_reg;
input [ 31: 0] W_bstatus_reg;
input [ 4: 0] W_dst_regnum;
input [ 5: 0] W_dst_regset;
input [ 31: 0] W_estatus_reg;
input [ 31: 0] W_exception_reg;
input [ 31: 0] W_iw;
input [ 5: 0] W_iw_op;
input [ 5: 0] W_iw_opx;
input [ 24: 0] W_pcb;
input [ 31: 0] W_status_reg;
input W_valid;
input [ 71: 0] W_vinst;
input W_wr_dst_reg;
input clk;
input [ 24: 0] d_address;
input [ 3: 0] d_byteenable;
input d_read;
input d_readdatavalid;
input d_write;
input [ 24: 0] i_address;
input i_read;
input i_readdatavalid;
input reset_n;
wire A_iw_invalid;
reg [ 24: 0] A_mem_baddr;
reg [ 24: 0] A_target_pcb;
wire [ 31: 0] A_wr_data_filtered;
wire A_wr_data_unfiltered_0_is_x;
wire A_wr_data_unfiltered_10_is_x;
wire A_wr_data_unfiltered_11_is_x;
wire A_wr_data_unfiltered_12_is_x;
wire A_wr_data_unfiltered_13_is_x;
wire A_wr_data_unfiltered_14_is_x;
wire A_wr_data_unfiltered_15_is_x;
wire A_wr_data_unfiltered_16_is_x;
wire A_wr_data_unfiltered_17_is_x;
wire A_wr_data_unfiltered_18_is_x;
wire A_wr_data_unfiltered_19_is_x;
wire A_wr_data_unfiltered_1_is_x;
wire A_wr_data_unfiltered_20_is_x;
wire A_wr_data_unfiltered_21_is_x;
wire A_wr_data_unfiltered_22_is_x;
wire A_wr_data_unfiltered_23_is_x;
wire A_wr_data_unfiltered_24_is_x;
wire A_wr_data_unfiltered_25_is_x;
wire A_wr_data_unfiltered_26_is_x;
wire A_wr_data_unfiltered_27_is_x;
wire A_wr_data_unfiltered_28_is_x;
wire A_wr_data_unfiltered_29_is_x;
wire A_wr_data_unfiltered_2_is_x;
wire A_wr_data_unfiltered_30_is_x;
wire A_wr_data_unfiltered_31_is_x;
wire A_wr_data_unfiltered_3_is_x;
wire A_wr_data_unfiltered_4_is_x;
wire A_wr_data_unfiltered_5_is_x;
wire A_wr_data_unfiltered_6_is_x;
wire A_wr_data_unfiltered_7_is_x;
wire A_wr_data_unfiltered_8_is_x;
wire A_wr_data_unfiltered_9_is_x;
wire E_add_br_to_taken_history_filtered;
wire E_add_br_to_taken_history_unfiltered_is_x;
wire [ 7: 0] M_bht_ptr_filtered;
wire M_bht_ptr_unfiltered_0_is_x;
wire M_bht_ptr_unfiltered_1_is_x;
wire M_bht_ptr_unfiltered_2_is_x;
wire M_bht_ptr_unfiltered_3_is_x;
wire M_bht_ptr_unfiltered_4_is_x;
wire M_bht_ptr_unfiltered_5_is_x;
wire M_bht_ptr_unfiltered_6_is_x;
wire M_bht_ptr_unfiltered_7_is_x;
wire [ 1: 0] M_bht_wr_data_filtered;
wire M_bht_wr_data_unfiltered_0_is_x;
wire M_bht_wr_data_unfiltered_1_is_x;
wire M_bht_wr_en_filtered;
wire M_bht_wr_en_unfiltered_is_x;
reg W_cmp_result;
reg W_exc_any_active;
reg [ 31: 0] W_exc_highest_pri_exc_id;
wire W_is_opx_inst;
reg W_iw_invalid;
wire W_op_add;
wire W_op_addi;
wire W_op_and;
wire W_op_andhi;
wire W_op_andi;
wire W_op_beq;
wire W_op_bge;
wire W_op_bgeu;
wire W_op_blt;
wire W_op_bltu;
wire W_op_bne;
wire W_op_br;
wire W_op_break;
wire W_op_bret;
wire W_op_call;
wire W_op_callr;
wire W_op_cmpeq;
wire W_op_cmpeqi;
wire W_op_cmpge;
wire W_op_cmpgei;
wire W_op_cmpgeu;
wire W_op_cmpgeui;
wire W_op_cmplt;
wire W_op_cmplti;
wire W_op_cmpltu;
wire W_op_cmpltui;
wire W_op_cmpne;
wire W_op_cmpnei;
wire W_op_crst;
wire W_op_custom;
wire W_op_div;
wire W_op_divu;
wire W_op_eret;
wire W_op_flushd;
wire W_op_flushda;
wire W_op_flushi;
wire W_op_flushp;
wire W_op_hbreak;
wire W_op_initd;
wire W_op_initda;
wire W_op_initi;
wire W_op_intr;
wire W_op_jmp;
wire W_op_jmpi;
wire W_op_ldb;
wire W_op_ldbio;
wire W_op_ldbu;
wire W_op_ldbuio;
wire W_op_ldh;
wire W_op_ldhio;
wire W_op_ldhu;
wire W_op_ldhuio;
wire W_op_ldl;
wire W_op_ldw;
wire W_op_ldwio;
wire W_op_mul;
wire W_op_muli;
wire W_op_mulxss;
wire W_op_mulxsu;
wire W_op_mulxuu;
wire W_op_nextpc;
wire W_op_nor;
wire W_op_op_rsv02;
wire W_op_op_rsv09;
wire W_op_op_rsv10;
wire W_op_op_rsv17;
wire W_op_op_rsv18;
wire W_op_op_rsv25;
wire W_op_op_rsv26;
wire W_op_op_rsv33;
wire W_op_op_rsv34;
wire W_op_op_rsv41;
wire W_op_op_rsv42;
wire W_op_op_rsv49;
wire W_op_op_rsv57;
wire W_op_op_rsv61;
wire W_op_op_rsv62;
wire W_op_op_rsv63;
wire W_op_opx_rsv00;
wire W_op_opx_rsv10;
wire W_op_opx_rsv15;
wire W_op_opx_rsv17;
wire W_op_opx_rsv21;
wire W_op_opx_rsv25;
wire W_op_opx_rsv33;
wire W_op_opx_rsv34;
wire W_op_opx_rsv35;
wire W_op_opx_rsv42;
wire W_op_opx_rsv43;
wire W_op_opx_rsv44;
wire W_op_opx_rsv47;
wire W_op_opx_rsv50;
wire W_op_opx_rsv51;
wire W_op_opx_rsv55;
wire W_op_opx_rsv56;
wire W_op_opx_rsv60;
wire W_op_opx_rsv63;
wire W_op_or;
wire W_op_orhi;
wire W_op_ori;
wire W_op_rdctl;
wire W_op_rdprs;
wire W_op_ret;
wire W_op_rol;
wire W_op_roli;
wire W_op_ror;
wire W_op_sll;
wire W_op_slli;
wire W_op_sra;
wire W_op_srai;
wire W_op_srl;
wire W_op_srli;
wire W_op_stb;
wire W_op_stbio;
wire W_op_stc;
wire W_op_sth;
wire W_op_sthio;
wire W_op_stw;
wire W_op_stwio;
wire W_op_sub;
wire W_op_sync;
wire W_op_trap;
wire W_op_wrctl;
wire W_op_wrprs;
wire W_op_xor;
wire W_op_xorhi;
wire W_op_xori;
reg [ 31: 0] W_st_data;
reg [ 24: 0] W_target_pcb;
reg W_valid_crst;
reg W_valid_hbreak;
reg W_valid_intr;
reg [ 31: 0] W_wr_data_filtered;
wire test_has_ended;
assign W_op_call = W_iw_op == 0;
assign W_op_jmpi = W_iw_op == 1;
assign W_op_op_rsv02 = W_iw_op == 2;
assign W_op_ldbu = W_iw_op == 3;
assign W_op_addi = W_iw_op == 4;
assign W_op_stb = W_iw_op == 5;
assign W_op_br = W_iw_op == 6;
assign W_op_ldb = W_iw_op == 7;
assign W_op_cmpgei = W_iw_op == 8;
assign W_op_op_rsv09 = W_iw_op == 9;
assign W_op_op_rsv10 = W_iw_op == 10;
assign W_op_ldhu = W_iw_op == 11;
assign W_op_andi = W_iw_op == 12;
assign W_op_sth = W_iw_op == 13;
assign W_op_bge = W_iw_op == 14;
assign W_op_ldh = W_iw_op == 15;
assign W_op_cmplti = W_iw_op == 16;
assign W_op_op_rsv17 = W_iw_op == 17;
assign W_op_op_rsv18 = W_iw_op == 18;
assign W_op_initda = W_iw_op == 19;
assign W_op_ori = W_iw_op == 20;
assign W_op_stw = W_iw_op == 21;
assign W_op_blt = W_iw_op == 22;
assign W_op_ldw = W_iw_op == 23;
assign W_op_cmpnei = W_iw_op == 24;
assign W_op_op_rsv25 = W_iw_op == 25;
assign W_op_op_rsv26 = W_iw_op == 26;
assign W_op_flushda = W_iw_op == 27;
assign W_op_xori = W_iw_op == 28;
assign W_op_stc = W_iw_op == 29;
assign W_op_bne = W_iw_op == 30;
assign W_op_ldl = W_iw_op == 31;
assign W_op_cmpeqi = W_iw_op == 32;
assign W_op_op_rsv33 = W_iw_op == 33;
assign W_op_op_rsv34 = W_iw_op == 34;
assign W_op_ldbuio = W_iw_op == 35;
assign W_op_muli = W_iw_op == 36;
assign W_op_stbio = W_iw_op == 37;
assign W_op_beq = W_iw_op == 38;
assign W_op_ldbio = W_iw_op == 39;
assign W_op_cmpgeui = W_iw_op == 40;
assign W_op_op_rsv41 = W_iw_op == 41;
assign W_op_op_rsv42 = W_iw_op == 42;
assign W_op_ldhuio = W_iw_op == 43;
assign W_op_andhi = W_iw_op == 44;
assign W_op_sthio = W_iw_op == 45;
assign W_op_bgeu = W_iw_op == 46;
assign W_op_ldhio = W_iw_op == 47;
assign W_op_cmpltui = W_iw_op == 48;
assign W_op_op_rsv49 = W_iw_op == 49;
assign W_op_custom = W_iw_op == 50;
assign W_op_initd = W_iw_op == 51;
assign W_op_orhi = W_iw_op == 52;
assign W_op_stwio = W_iw_op == 53;
assign W_op_bltu = W_iw_op == 54;
assign W_op_ldwio = W_iw_op == 55;
assign W_op_rdprs = W_iw_op == 56;
assign W_op_op_rsv57 = W_iw_op == 57;
assign W_op_flushd = W_iw_op == 59;
assign W_op_xorhi = W_iw_op == 60;
assign W_op_op_rsv61 = W_iw_op == 61;
assign W_op_op_rsv62 = W_iw_op == 62;
assign W_op_op_rsv63 = W_iw_op == 63;
assign W_op_opx_rsv00 = (W_iw_opx == 0) & W_is_opx_inst;
assign W_op_eret = (W_iw_opx == 1) & W_is_opx_inst;
assign W_op_roli = (W_iw_opx == 2) & W_is_opx_inst;
assign W_op_rol = (W_iw_opx == 3) & W_is_opx_inst;
assign W_op_flushp = (W_iw_opx == 4) & W_is_opx_inst;
assign W_op_ret = (W_iw_opx == 5) & W_is_opx_inst;
assign W_op_nor = (W_iw_opx == 6) & W_is_opx_inst;
assign W_op_mulxuu = (W_iw_opx == 7) & W_is_opx_inst;
assign W_op_cmpge = (W_iw_opx == 8) & W_is_opx_inst;
assign W_op_bret = (W_iw_opx == 9) & W_is_opx_inst;
assign W_op_opx_rsv10 = (W_iw_opx == 10) & W_is_opx_inst;
assign W_op_ror = (W_iw_opx == 11) & W_is_opx_inst;
assign W_op_flushi = (W_iw_opx == 12) & W_is_opx_inst;
assign W_op_jmp = (W_iw_opx == 13) & W_is_opx_inst;
assign W_op_and = (W_iw_opx == 14) & W_is_opx_inst;
assign W_op_opx_rsv15 = (W_iw_opx == 15) & W_is_opx_inst;
assign W_op_cmplt = (W_iw_opx == 16) & W_is_opx_inst;
assign W_op_opx_rsv17 = (W_iw_opx == 17) & W_is_opx_inst;
assign W_op_slli = (W_iw_opx == 18) & W_is_opx_inst;
assign W_op_sll = (W_iw_opx == 19) & W_is_opx_inst;
assign W_op_wrprs = (W_iw_opx == 20) & W_is_opx_inst;
assign W_op_opx_rsv21 = (W_iw_opx == 21) & W_is_opx_inst;
assign W_op_or = (W_iw_opx == 22) & W_is_opx_inst;
assign W_op_mulxsu = (W_iw_opx == 23) & W_is_opx_inst;
assign W_op_cmpne = (W_iw_opx == 24) & W_is_opx_inst;
assign W_op_opx_rsv25 = (W_iw_opx == 25) & W_is_opx_inst;
assign W_op_srli = (W_iw_opx == 26) & W_is_opx_inst;
assign W_op_srl = (W_iw_opx == 27) & W_is_opx_inst;
assign W_op_nextpc = (W_iw_opx == 28) & W_is_opx_inst;
assign W_op_callr = (W_iw_opx == 29) & W_is_opx_inst;
assign W_op_xor = (W_iw_opx == 30) & W_is_opx_inst;
assign W_op_mulxss = (W_iw_opx == 31) & W_is_opx_inst;
assign W_op_cmpeq = (W_iw_opx == 32) & W_is_opx_inst;
assign W_op_opx_rsv33 = (W_iw_opx == 33) & W_is_opx_inst;
assign W_op_opx_rsv34 = (W_iw_opx == 34) & W_is_opx_inst;
assign W_op_opx_rsv35 = (W_iw_opx == 35) & W_is_opx_inst;
assign W_op_divu = (W_iw_opx == 36) & W_is_opx_inst;
assign W_op_div = (W_iw_opx == 37) & W_is_opx_inst;
assign W_op_rdctl = (W_iw_opx == 38) & W_is_opx_inst;
assign W_op_mul = (W_iw_opx == 39) & W_is_opx_inst;
assign W_op_cmpgeu = (W_iw_opx == 40) & W_is_opx_inst;
assign W_op_initi = (W_iw_opx == 41) & W_is_opx_inst;
assign W_op_opx_rsv42 = (W_iw_opx == 42) & W_is_opx_inst;
assign W_op_opx_rsv43 = (W_iw_opx == 43) & W_is_opx_inst;
assign W_op_opx_rsv44 = (W_iw_opx == 44) & W_is_opx_inst;
assign W_op_trap = (W_iw_opx == 45) & W_is_opx_inst;
assign W_op_wrctl = (W_iw_opx == 46) & W_is_opx_inst;
assign W_op_opx_rsv47 = (W_iw_opx == 47) & W_is_opx_inst;
assign W_op_cmpltu = (W_iw_opx == 48) & W_is_opx_inst;
assign W_op_add = (W_iw_opx == 49) & W_is_opx_inst;
assign W_op_opx_rsv50 = (W_iw_opx == 50) & W_is_opx_inst;
assign W_op_opx_rsv51 = (W_iw_opx == 51) & W_is_opx_inst;
assign W_op_break = (W_iw_opx == 52) & W_is_opx_inst;
assign W_op_hbreak = (W_iw_opx == 53) & W_is_opx_inst;
assign W_op_sync = (W_iw_opx == 54) & W_is_opx_inst;
assign W_op_opx_rsv55 = (W_iw_opx == 55) & W_is_opx_inst;
assign W_op_opx_rsv56 = (W_iw_opx == 56) & W_is_opx_inst;
assign W_op_sub = (W_iw_opx == 57) & W_is_opx_inst;
assign W_op_srai = (W_iw_opx == 58) & W_is_opx_inst;
assign W_op_sra = (W_iw_opx == 59) & W_is_opx_inst;
assign W_op_opx_rsv60 = (W_iw_opx == 60) & W_is_opx_inst;
assign W_op_intr = (W_iw_opx == 61) & W_is_opx_inst;
assign W_op_crst = (W_iw_opx == 62) & W_is_opx_inst;
assign W_op_opx_rsv63 = (W_iw_opx == 63) & W_is_opx_inst;
assign W_is_opx_inst = W_iw_op == 58;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
A_target_pcb <= 0;
else if (A_en)
A_target_pcb <= M_target_pcb;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
A_mem_baddr <= 0;
else if (A_en)
A_mem_baddr <= M_mem_baddr;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
W_wr_data_filtered <= 0;
else
W_wr_data_filtered <= A_wr_data_filtered;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
W_st_data <= 0;
else
W_st_data <= A_st_data;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
W_cmp_result <= 0;
else
W_cmp_result <= A_cmp_result;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
W_target_pcb <= 0;
else
W_target_pcb <= A_target_pcb;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
W_valid_hbreak <= 0;
else
W_valid_hbreak <= A_exc_allowed & A_exc_hbreak_pri1;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
W_valid_crst <= 0;
else
W_valid_crst <= A_exc_allowed & 0;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
W_valid_intr <= 0;
else
W_valid_intr <= A_exc_allowed & A_exc_norm_intr_pri5;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
W_exc_any_active <= 0;
else
W_exc_any_active <= A_exc_any_active;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
W_exc_highest_pri_exc_id <= 0;
else
W_exc_highest_pri_exc_id <= A_exc_highest_pri_exc_id;
end
assign A_iw_invalid = A_exc_inst_fetch & A_exc_active_no_break_no_crst;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
W_iw_invalid <= 0;
else
W_iw_invalid <= A_iw_invalid;
end
assign test_has_ended = 1'b0;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
//Clearing 'X' data bits
assign A_wr_data_unfiltered_0_is_x = ^(A_wr_data_unfiltered[0]) === 1'bx;
assign A_wr_data_filtered[0] = (A_wr_data_unfiltered_0_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[0];
assign A_wr_data_unfiltered_1_is_x = ^(A_wr_data_unfiltered[1]) === 1'bx;
assign A_wr_data_filtered[1] = (A_wr_data_unfiltered_1_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[1];
assign A_wr_data_unfiltered_2_is_x = ^(A_wr_data_unfiltered[2]) === 1'bx;
assign A_wr_data_filtered[2] = (A_wr_data_unfiltered_2_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[2];
assign A_wr_data_unfiltered_3_is_x = ^(A_wr_data_unfiltered[3]) === 1'bx;
assign A_wr_data_filtered[3] = (A_wr_data_unfiltered_3_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[3];
assign A_wr_data_unfiltered_4_is_x = ^(A_wr_data_unfiltered[4]) === 1'bx;
assign A_wr_data_filtered[4] = (A_wr_data_unfiltered_4_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[4];
assign A_wr_data_unfiltered_5_is_x = ^(A_wr_data_unfiltered[5]) === 1'bx;
assign A_wr_data_filtered[5] = (A_wr_data_unfiltered_5_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[5];
assign A_wr_data_unfiltered_6_is_x = ^(A_wr_data_unfiltered[6]) === 1'bx;
assign A_wr_data_filtered[6] = (A_wr_data_unfiltered_6_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[6];
assign A_wr_data_unfiltered_7_is_x = ^(A_wr_data_unfiltered[7]) === 1'bx;
assign A_wr_data_filtered[7] = (A_wr_data_unfiltered_7_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[7];
assign A_wr_data_unfiltered_8_is_x = ^(A_wr_data_unfiltered[8]) === 1'bx;
assign A_wr_data_filtered[8] = (A_wr_data_unfiltered_8_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[8];
assign A_wr_data_unfiltered_9_is_x = ^(A_wr_data_unfiltered[9]) === 1'bx;
assign A_wr_data_filtered[9] = (A_wr_data_unfiltered_9_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[9];
assign A_wr_data_unfiltered_10_is_x = ^(A_wr_data_unfiltered[10]) === 1'bx;
assign A_wr_data_filtered[10] = (A_wr_data_unfiltered_10_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[10];
assign A_wr_data_unfiltered_11_is_x = ^(A_wr_data_unfiltered[11]) === 1'bx;
assign A_wr_data_filtered[11] = (A_wr_data_unfiltered_11_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[11];
assign A_wr_data_unfiltered_12_is_x = ^(A_wr_data_unfiltered[12]) === 1'bx;
assign A_wr_data_filtered[12] = (A_wr_data_unfiltered_12_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[12];
assign A_wr_data_unfiltered_13_is_x = ^(A_wr_data_unfiltered[13]) === 1'bx;
assign A_wr_data_filtered[13] = (A_wr_data_unfiltered_13_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[13];
assign A_wr_data_unfiltered_14_is_x = ^(A_wr_data_unfiltered[14]) === 1'bx;
assign A_wr_data_filtered[14] = (A_wr_data_unfiltered_14_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[14];
assign A_wr_data_unfiltered_15_is_x = ^(A_wr_data_unfiltered[15]) === 1'bx;
assign A_wr_data_filtered[15] = (A_wr_data_unfiltered_15_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[15];
assign A_wr_data_unfiltered_16_is_x = ^(A_wr_data_unfiltered[16]) === 1'bx;
assign A_wr_data_filtered[16] = (A_wr_data_unfiltered_16_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[16];
assign A_wr_data_unfiltered_17_is_x = ^(A_wr_data_unfiltered[17]) === 1'bx;
assign A_wr_data_filtered[17] = (A_wr_data_unfiltered_17_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[17];
assign A_wr_data_unfiltered_18_is_x = ^(A_wr_data_unfiltered[18]) === 1'bx;
assign A_wr_data_filtered[18] = (A_wr_data_unfiltered_18_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[18];
assign A_wr_data_unfiltered_19_is_x = ^(A_wr_data_unfiltered[19]) === 1'bx;
assign A_wr_data_filtered[19] = (A_wr_data_unfiltered_19_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[19];
assign A_wr_data_unfiltered_20_is_x = ^(A_wr_data_unfiltered[20]) === 1'bx;
assign A_wr_data_filtered[20] = (A_wr_data_unfiltered_20_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[20];
assign A_wr_data_unfiltered_21_is_x = ^(A_wr_data_unfiltered[21]) === 1'bx;
assign A_wr_data_filtered[21] = (A_wr_data_unfiltered_21_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[21];
assign A_wr_data_unfiltered_22_is_x = ^(A_wr_data_unfiltered[22]) === 1'bx;
assign A_wr_data_filtered[22] = (A_wr_data_unfiltered_22_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[22];
assign A_wr_data_unfiltered_23_is_x = ^(A_wr_data_unfiltered[23]) === 1'bx;
assign A_wr_data_filtered[23] = (A_wr_data_unfiltered_23_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[23];
assign A_wr_data_unfiltered_24_is_x = ^(A_wr_data_unfiltered[24]) === 1'bx;
assign A_wr_data_filtered[24] = (A_wr_data_unfiltered_24_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[24];
assign A_wr_data_unfiltered_25_is_x = ^(A_wr_data_unfiltered[25]) === 1'bx;
assign A_wr_data_filtered[25] = (A_wr_data_unfiltered_25_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[25];
assign A_wr_data_unfiltered_26_is_x = ^(A_wr_data_unfiltered[26]) === 1'bx;
assign A_wr_data_filtered[26] = (A_wr_data_unfiltered_26_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[26];
assign A_wr_data_unfiltered_27_is_x = ^(A_wr_data_unfiltered[27]) === 1'bx;
assign A_wr_data_filtered[27] = (A_wr_data_unfiltered_27_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[27];
assign A_wr_data_unfiltered_28_is_x = ^(A_wr_data_unfiltered[28]) === 1'bx;
assign A_wr_data_filtered[28] = (A_wr_data_unfiltered_28_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[28];
assign A_wr_data_unfiltered_29_is_x = ^(A_wr_data_unfiltered[29]) === 1'bx;
assign A_wr_data_filtered[29] = (A_wr_data_unfiltered_29_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[29];
assign A_wr_data_unfiltered_30_is_x = ^(A_wr_data_unfiltered[30]) === 1'bx;
assign A_wr_data_filtered[30] = (A_wr_data_unfiltered_30_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[30];
assign A_wr_data_unfiltered_31_is_x = ^(A_wr_data_unfiltered[31]) === 1'bx;
assign A_wr_data_filtered[31] = (A_wr_data_unfiltered_31_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[31];
//Clearing 'X' data bits
assign E_add_br_to_taken_history_unfiltered_is_x = ^(E_add_br_to_taken_history_unfiltered) === 1'bx;
assign E_add_br_to_taken_history_filtered = E_add_br_to_taken_history_unfiltered_is_x ? 1'b0 : E_add_br_to_taken_history_unfiltered;
//Clearing 'X' data bits
assign M_bht_wr_en_unfiltered_is_x = ^(M_bht_wr_en_unfiltered) === 1'bx;
assign M_bht_wr_en_filtered = M_bht_wr_en_unfiltered_is_x ? 1'b0 : M_bht_wr_en_unfiltered;
//Clearing 'X' data bits
assign M_bht_wr_data_unfiltered_0_is_x = ^(M_bht_wr_data_unfiltered[0]) === 1'bx;
assign M_bht_wr_data_filtered[0] = M_bht_wr_data_unfiltered_0_is_x ? 1'b0 : M_bht_wr_data_unfiltered[0];
assign M_bht_wr_data_unfiltered_1_is_x = ^(M_bht_wr_data_unfiltered[1]) === 1'bx;
assign M_bht_wr_data_filtered[1] = M_bht_wr_data_unfiltered_1_is_x ? 1'b0 : M_bht_wr_data_unfiltered[1];
//Clearing 'X' data bits
assign M_bht_ptr_unfiltered_0_is_x = ^(M_bht_ptr_unfiltered[0]) === 1'bx;
assign M_bht_ptr_filtered[0] = M_bht_ptr_unfiltered_0_is_x ? 1'b0 : M_bht_ptr_unfiltered[0];
assign M_bht_ptr_unfiltered_1_is_x = ^(M_bht_ptr_unfiltered[1]) === 1'bx;
assign M_bht_ptr_filtered[1] = M_bht_ptr_unfiltered_1_is_x ? 1'b0 : M_bht_ptr_unfiltered[1];
assign M_bht_ptr_unfiltered_2_is_x = ^(M_bht_ptr_unfiltered[2]) === 1'bx;
assign M_bht_ptr_filtered[2] = M_bht_ptr_unfiltered_2_is_x ? 1'b0 : M_bht_ptr_unfiltered[2];
assign M_bht_ptr_unfiltered_3_is_x = ^(M_bht_ptr_unfiltered[3]) === 1'bx;
assign M_bht_ptr_filtered[3] = M_bht_ptr_unfiltered_3_is_x ? 1'b0 : M_bht_ptr_unfiltered[3];
assign M_bht_ptr_unfiltered_4_is_x = ^(M_bht_ptr_unfiltered[4]) === 1'bx;
assign M_bht_ptr_filtered[4] = M_bht_ptr_unfiltered_4_is_x ? 1'b0 : M_bht_ptr_unfiltered[4];
assign M_bht_ptr_unfiltered_5_is_x = ^(M_bht_ptr_unfiltered[5]) === 1'bx;
assign M_bht_ptr_filtered[5] = M_bht_ptr_unfiltered_5_is_x ? 1'b0 : M_bht_ptr_unfiltered[5];
assign M_bht_ptr_unfiltered_6_is_x = ^(M_bht_ptr_unfiltered[6]) === 1'bx;
assign M_bht_ptr_filtered[6] = M_bht_ptr_unfiltered_6_is_x ? 1'b0 : M_bht_ptr_unfiltered[6];
assign M_bht_ptr_unfiltered_7_is_x = ^(M_bht_ptr_unfiltered[7]) === 1'bx;
assign M_bht_ptr_filtered[7] = M_bht_ptr_unfiltered_7_is_x ? 1'b0 : M_bht_ptr_unfiltered[7];
always @(posedge clk)
begin
if (reset_n)
if (^(W_wr_dst_reg) === 1'bx)
begin
$write("%0d ns: ERROR: TimeHoldOver_Qsys_nios2_gen2_0_cpu_test_bench/W_wr_dst_reg is 'x'\n", $time);
$stop;
end
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
end
else if (W_wr_dst_reg)
if (^(W_dst_regnum) === 1'bx)
begin
$write("%0d ns: ERROR: TimeHoldOver_Qsys_nios2_gen2_0_cpu_test_bench/W_dst_regnum is 'x'\n", $time);
$stop;
end
end
always @(posedge clk)
begin
if (reset_n)
if (^(W_valid) === 1'bx)
begin
$write("%0d ns: ERROR: TimeHoldOver_Qsys_nios2_gen2_0_cpu_test_bench/W_valid is 'x'\n", $time);
$stop;
end
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
end
else if (W_valid)
if (^(W_pcb) === 1'bx)
begin
$write("%0d ns: ERROR: TimeHoldOver_Qsys_nios2_gen2_0_cpu_test_bench/W_pcb is 'x'\n", $time);
$stop;
end
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
end
else if (W_valid)
if (^(W_iw) === 1'bx)
begin
$write("%0d ns: ERROR: TimeHoldOver_Qsys_nios2_gen2_0_cpu_test_bench/W_iw is 'x'\n", $time);
$stop;
end
end
always @(posedge clk)
begin
if (reset_n)
if (^(A_en) === 1'bx)
begin
$write("%0d ns: ERROR: TimeHoldOver_Qsys_nios2_gen2_0_cpu_test_bench/A_en is 'x'\n", $time);
$stop;
end
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
end
else if (W_wr_dst_reg)
if (^(W_dst_regset) === 1'bx)
begin
$write("%0d ns: ERROR: TimeHoldOver_Qsys_nios2_gen2_0_cpu_test_bench/W_dst_regset is 'x'\n", $time);
$stop;
end
end
always @(posedge clk)
begin
if (reset_n)
if (^(M_valid) === 1'bx)
begin
$write("%0d ns: ERROR: TimeHoldOver_Qsys_nios2_gen2_0_cpu_test_bench/M_valid is 'x'\n", $time);
$stop;
end
end
always @(posedge clk)
begin
if (reset_n)
if (^(A_valid) === 1'bx)
begin
$write("%0d ns: ERROR: TimeHoldOver_Qsys_nios2_gen2_0_cpu_test_bench/A_valid is 'x'\n", $time);
$stop;
end
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
end
else if (A_valid & A_en & A_wr_dst_reg)
if (^(A_wr_data_unfiltered) === 1'bx)
begin
$write("%0d ns: WARNING: TimeHoldOver_Qsys_nios2_gen2_0_cpu_test_bench/A_wr_data_unfiltered is 'x'\n", $time);
end
end
always @(posedge clk)
begin
if (reset_n)
if (^(W_status_reg) === 1'bx)
begin
$write("%0d ns: ERROR: TimeHoldOver_Qsys_nios2_gen2_0_cpu_test_bench/W_status_reg is 'x'\n", $time);
$stop;
end
end
always @(posedge clk)
begin
if (reset_n)
if (^(W_estatus_reg) === 1'bx)
begin
$write("%0d ns: ERROR: TimeHoldOver_Qsys_nios2_gen2_0_cpu_test_bench/W_estatus_reg is 'x'\n", $time);
$stop;
end
end
always @(posedge clk)
begin
if (reset_n)
if (^(W_bstatus_reg) === 1'bx)
begin
$write("%0d ns: ERROR: TimeHoldOver_Qsys_nios2_gen2_0_cpu_test_bench/W_bstatus_reg is 'x'\n", $time);
$stop;
end
end
always @(posedge clk)
begin
if (reset_n)
if (^(W_exception_reg) === 1'bx)
begin
$write("%0d ns: ERROR: TimeHoldOver_Qsys_nios2_gen2_0_cpu_test_bench/W_exception_reg is 'x'\n", $time);
$stop;
end
end
always @(posedge clk)
begin
if (reset_n)
if (^(W_badaddr_reg) === 1'bx)
begin
$write("%0d ns: ERROR: TimeHoldOver_Qsys_nios2_gen2_0_cpu_test_bench/W_badaddr_reg is 'x'\n", $time);
$stop;
end
end
always @(posedge clk)
begin
if (reset_n)
if (^(A_exc_any_active) === 1'bx)
begin
$write("%0d ns: ERROR: TimeHoldOver_Qsys_nios2_gen2_0_cpu_test_bench/A_exc_any_active is 'x'\n", $time);
$stop;
end
end
always @(posedge clk)
begin
if (reset_n)
if (^(i_read) === 1'bx)
begin
$write("%0d ns: ERROR: TimeHoldOver_Qsys_nios2_gen2_0_cpu_test_bench/i_read is 'x'\n", $time);
$stop;
end
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
end
else if (i_read)
if (^(i_address) === 1'bx)
begin
$write("%0d ns: ERROR: TimeHoldOver_Qsys_nios2_gen2_0_cpu_test_bench/i_address is 'x'\n", $time);
$stop;
end
end
always @(posedge clk)
begin
if (reset_n)
if (^(d_write) === 1'bx)
begin
$write("%0d ns: ERROR: TimeHoldOver_Qsys_nios2_gen2_0_cpu_test_bench/d_write is 'x'\n", $time);
$stop;
end
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
end
else if (d_write)
if (^(d_byteenable) === 1'bx)
begin
$write("%0d ns: ERROR: TimeHoldOver_Qsys_nios2_gen2_0_cpu_test_bench/d_byteenable is 'x'\n", $time);
$stop;
end
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
end
else if (d_write | d_read)
if (^(d_address) === 1'bx)
begin
$write("%0d ns: ERROR: TimeHoldOver_Qsys_nios2_gen2_0_cpu_test_bench/d_address is 'x'\n", $time);
$stop;
end
end
always @(posedge clk)
begin
if (reset_n)
if (^(d_read) === 1'bx)
begin
$write("%0d ns: ERROR: TimeHoldOver_Qsys_nios2_gen2_0_cpu_test_bench/d_read is 'x'\n", $time);
$stop;
end
end
always @(posedge clk)
begin
if (reset_n)
if (^(i_readdatavalid) === 1'bx)
begin
$write("%0d ns: ERROR: TimeHoldOver_Qsys_nios2_gen2_0_cpu_test_bench/i_readdatavalid is 'x'\n", $time);
$stop;
end
end
always @(posedge clk)
begin
if (reset_n)
if (^(d_readdatavalid) === 1'bx)
begin
$write("%0d ns: ERROR: TimeHoldOver_Qsys_nios2_gen2_0_cpu_test_bench/d_readdatavalid is 'x'\n", $time);
$stop;
end
end
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
//
// assign A_wr_data_filtered = A_wr_data_unfiltered;
//
//
// assign E_add_br_to_taken_history_filtered = E_add_br_to_taken_history_unfiltered;
//
//
// assign M_bht_wr_en_filtered = M_bht_wr_en_unfiltered;
//
//
// assign M_bht_wr_data_filtered = M_bht_wr_data_unfiltered;
//
//
// assign M_bht_ptr_filtered = M_bht_ptr_unfiltered;
//
//synthesis read_comments_as_HDL off
endmodule
|
module ila_0 (
clk,
probe0,
probe1,
probe2,
probe3,
probe4,
probe5,
probe6,
probe7,
probe8,
probe9,
probe10,
probe11,
probe12,
probe13,
probe14,
probe15,
probe16,
probe17,
probe18,
probe19,
probe20
);
input clk;
input [63 : 0] probe0;
input [63 : 0] probe1;
input [0 : 0] probe2;
input [0 : 0] probe3;
input [0 : 0] probe4;
input [0 : 0] probe5;
input [0 : 0] probe6;
input [63 : 0] probe7;
input [0 : 0] probe8;
input [0 : 0] probe9;
input [0 : 0] probe10;
input [0 : 0] probe11;
input [63 : 0] probe12;
input [0 : 0] probe13;
input [0 : 0] probe14;
input [0 : 0] probe15;
input [0 : 0] probe16;
input [0 : 0] probe17;
input [7 : 0] probe18;
input [7 : 0] probe19;
input [0 : 0] probe20;
wire [16:0] sl_oport0;
wire [36:0] sl_iport0;
ila_v6_2_0_ila #(
.C_XLNX_HW_PROBE_INFO("DEFAULT"),
.C_XDEVICEFAMILY("kintex7"),
.C_CORE_TYPE(1),
.C_CORE_INFO1(0),
.C_CORE_INFO2(0),
.C_CAPTURE_TYPE(0),
.C_MU_TYPE(0),
.C_TC_TYPE(0),
.C_NUM_OF_PROBES(21),
.C_DATA_DEPTH(2048),
.C_MAJOR_VERSION(2016),
.C_MINOR_VERSION(3),
.C_BUILD_REVISION(0),
.C_CORE_MAJOR_VER(6),
.C_CORE_MINOR_VER(2),
.C_XSDB_SLAVE_TYPE(17),
.C_NEXT_SLAVE(0),
.C_CSE_DRV_VER(2),
.C_USE_TEST_REG(1),
.C_PIPE_IFACE(1),
.C_RAM_STYLE("SUBCORE"),
.C_TRIGOUT_EN(0),
.C_TRIGIN_EN(0),
.C_ADV_TRIGGER(0),
.C_EN_DDR_ILA(0),
.C_DDR_CLK_GEN(0),
.C_CLK_FREQ(200),
.C_CLK_PERIOD(5.0),
.C_CLKFBOUT_MULT_F(10),
.C_DIVCLK_DIVIDE(3),
.C_CLKOUT0_DIVIDE_F(10),
.C_EN_STRG_QUAL(0),
.C_INPUT_PIPE_STAGES(0),
.C_EN_TIME_TAG (0),
.C_TIME_TAG_WIDTH (32),
.C_ILA_CLK_FREQ(2000000),
.C_PROBE0_WIDTH(64),
.C_PROBE1_WIDTH(64),
.C_PROBE2_WIDTH(1),
.C_PROBE3_WIDTH(1),
.C_PROBE4_WIDTH(1),
.C_PROBE5_WIDTH(1),
.C_PROBE6_WIDTH(1),
.C_PROBE7_WIDTH(64),
.C_PROBE8_WIDTH(1),
.C_PROBE9_WIDTH(1),
.C_PROBE10_WIDTH(1),
.C_PROBE11_WIDTH(1),
.C_PROBE12_WIDTH(64),
.C_PROBE13_WIDTH(1),
.C_PROBE14_WIDTH(1),
.C_PROBE15_WIDTH(1),
.C_PROBE16_WIDTH(1),
.C_PROBE17_WIDTH(1),
.C_PROBE18_WIDTH(8),
.C_PROBE19_WIDTH(8),
.C_PROBE20_WIDTH(1),
.C_PROBE21_WIDTH(1),
.C_PROBE22_WIDTH(1),
.C_PROBE23_WIDTH(1),
.C_PROBE24_WIDTH(1),
.C_PROBE25_WIDTH(1),
.C_PROBE26_WIDTH(1),
.C_PROBE27_WIDTH(1),
.C_PROBE28_WIDTH(1),
.C_PROBE29_WIDTH(1),
.C_PROBE30_WIDTH(1),
.C_PROBE31_WIDTH(1),
.C_PROBE32_WIDTH(1),
.C_PROBE33_WIDTH(1),
.C_PROBE34_WIDTH(1),
.C_PROBE35_WIDTH(1),
.C_PROBE36_WIDTH(1),
.C_PROBE37_WIDTH(1),
.C_PROBE38_WIDTH(1),
.C_PROBE39_WIDTH(1),
.C_PROBE40_WIDTH(1),
.C_PROBE41_WIDTH(1),
.C_PROBE42_WIDTH(1),
.C_PROBE43_WIDTH(1),
.C_PROBE44_WIDTH(1),
.C_PROBE45_WIDTH(1),
.C_PROBE46_WIDTH(1),
.C_PROBE47_WIDTH(1),
.C_PROBE48_WIDTH(1),
.C_PROBE49_WIDTH(1),
.C_PROBE50_WIDTH(1),
.C_PROBE51_WIDTH(1),
.C_PROBE52_WIDTH(1),
.C_PROBE53_WIDTH(1),
.C_PROBE54_WIDTH(1),
.C_PROBE55_WIDTH(1),
.C_PROBE56_WIDTH(1),
.C_PROBE57_WIDTH(1),
.C_PROBE58_WIDTH(1),
.C_PROBE59_WIDTH(1),
.C_PROBE60_WIDTH(1),
.C_PROBE61_WIDTH(1),
.C_PROBE62_WIDTH(1),
.C_PROBE63_WIDTH(1),
.C_PROBE64_WIDTH(1),
.C_PROBE65_WIDTH(1),
.C_PROBE66_WIDTH(1),
.C_PROBE67_WIDTH(1),
.C_PROBE68_WIDTH(1),
.C_PROBE69_WIDTH(1),
.C_PROBE70_WIDTH(1),
.C_PROBE71_WIDTH(1),
.C_PROBE72_WIDTH(1),
.C_PROBE73_WIDTH(1),
.C_PROBE74_WIDTH(1),
.C_PROBE75_WIDTH(1),
.C_PROBE76_WIDTH(1),
.C_PROBE77_WIDTH(1),
.C_PROBE78_WIDTH(1),
.C_PROBE79_WIDTH(1),
.C_PROBE80_WIDTH(1),
.C_PROBE81_WIDTH(1),
.C_PROBE82_WIDTH(1),
.C_PROBE83_WIDTH(1),
.C_PROBE84_WIDTH(1),
.C_PROBE85_WIDTH(1),
.C_PROBE86_WIDTH(1),
.C_PROBE87_WIDTH(1),
.C_PROBE88_WIDTH(1),
.C_PROBE89_WIDTH(1),
.C_PROBE90_WIDTH(1),
.C_PROBE91_WIDTH(1),
.C_PROBE92_WIDTH(1),
.C_PROBE93_WIDTH(1),
.C_PROBE94_WIDTH(1),
.C_PROBE95_WIDTH(1),
.C_PROBE96_WIDTH(1),
.C_PROBE97_WIDTH(1),
.C_PROBE98_WIDTH(1),
.C_PROBE99_WIDTH(1),
.C_PROBE100_WIDTH(1),
.C_PROBE101_WIDTH(1),
.C_PROBE102_WIDTH(1),
.C_PROBE103_WIDTH(1),
.C_PROBE104_WIDTH(1),
.C_PROBE105_WIDTH(1),
.C_PROBE106_WIDTH(1),
.C_PROBE107_WIDTH(1),
.C_PROBE108_WIDTH(1),
.C_PROBE109_WIDTH(1),
.C_PROBE110_WIDTH(1),
.C_PROBE111_WIDTH(1),
.C_PROBE112_WIDTH(1),
.C_PROBE113_WIDTH(1),
.C_PROBE114_WIDTH(1),
.C_PROBE115_WIDTH(1),
.C_PROBE116_WIDTH(1),
.C_PROBE117_WIDTH(1),
.C_PROBE118_WIDTH(1),
.C_PROBE119_WIDTH(1),
.C_PROBE120_WIDTH(1),
.C_PROBE121_WIDTH(1),
.C_PROBE122_WIDTH(1),
.C_PROBE123_WIDTH(1),
.C_PROBE124_WIDTH(1),
.C_PROBE125_WIDTH(1),
.C_PROBE126_WIDTH(1),
.C_PROBE127_WIDTH(1),
.C_PROBE128_WIDTH(1),
.C_PROBE129_WIDTH(1),
.C_PROBE130_WIDTH(1),
.C_PROBE131_WIDTH(1),
.C_PROBE132_WIDTH(1),
.C_PROBE133_WIDTH(1),
.C_PROBE134_WIDTH(1),
.C_PROBE135_WIDTH(1),
.C_PROBE136_WIDTH(1),
.C_PROBE137_WIDTH(1),
.C_PROBE138_WIDTH(1),
.C_PROBE139_WIDTH(1),
.C_PROBE140_WIDTH(1),
.C_PROBE141_WIDTH(1),
.C_PROBE142_WIDTH(1),
.C_PROBE143_WIDTH(1),
.C_PROBE144_WIDTH(1),
.C_PROBE145_WIDTH(1),
.C_PROBE146_WIDTH(1),
.C_PROBE147_WIDTH(1),
.C_PROBE148_WIDTH(1),
.C_PROBE149_WIDTH(1),
.C_PROBE150_WIDTH(1),
.C_PROBE151_WIDTH(1),
.C_PROBE152_WIDTH(1),
.C_PROBE153_WIDTH(1),
.C_PROBE154_WIDTH(1),
.C_PROBE155_WIDTH(1),
.C_PROBE156_WIDTH(1),
.C_PROBE157_WIDTH(1),
.C_PROBE158_WIDTH(1),
.C_PROBE159_WIDTH(1),
.C_PROBE160_WIDTH(1),
.C_PROBE161_WIDTH(1),
.C_PROBE162_WIDTH(1),
.C_PROBE163_WIDTH(1),
.C_PROBE164_WIDTH(1),
.C_PROBE165_WIDTH(1),
.C_PROBE166_WIDTH(1),
.C_PROBE167_WIDTH(1),
.C_PROBE168_WIDTH(1),
.C_PROBE169_WIDTH(1),
.C_PROBE170_WIDTH(1),
.C_PROBE171_WIDTH(1),
.C_PROBE172_WIDTH(1),
.C_PROBE173_WIDTH(1),
.C_PROBE174_WIDTH(1),
.C_PROBE175_WIDTH(1),
.C_PROBE176_WIDTH(1),
.C_PROBE177_WIDTH(1),
.C_PROBE178_WIDTH(1),
.C_PROBE179_WIDTH(1),
.C_PROBE180_WIDTH(1),
.C_PROBE181_WIDTH(1),
.C_PROBE182_WIDTH(1),
.C_PROBE183_WIDTH(1),
.C_PROBE184_WIDTH(1),
.C_PROBE185_WIDTH(1),
.C_PROBE186_WIDTH(1),
.C_PROBE187_WIDTH(1),
.C_PROBE188_WIDTH(1),
.C_PROBE189_WIDTH(1),
.C_PROBE190_WIDTH(1),
.C_PROBE191_WIDTH(1),
.C_PROBE192_WIDTH(1),
.C_PROBE193_WIDTH(1),
.C_PROBE194_WIDTH(1),
.C_PROBE195_WIDTH(1),
.C_PROBE196_WIDTH(1),
.C_PROBE197_WIDTH(1),
.C_PROBE198_WIDTH(1),
.C_PROBE199_WIDTH(1),
.C_PROBE200_WIDTH(1),
.C_PROBE201_WIDTH(1),
.C_PROBE202_WIDTH(1),
.C_PROBE203_WIDTH(1),
.C_PROBE204_WIDTH(1),
.C_PROBE205_WIDTH(1),
.C_PROBE206_WIDTH(1),
.C_PROBE207_WIDTH(1),
.C_PROBE208_WIDTH(1),
.C_PROBE209_WIDTH(1),
.C_PROBE210_WIDTH(1),
.C_PROBE211_WIDTH(1),
.C_PROBE212_WIDTH(1),
.C_PROBE213_WIDTH(1),
.C_PROBE214_WIDTH(1),
.C_PROBE215_WIDTH(1),
.C_PROBE216_WIDTH(1),
.C_PROBE217_WIDTH(1),
.C_PROBE218_WIDTH(1),
.C_PROBE219_WIDTH(1),
.C_PROBE220_WIDTH(1),
.C_PROBE221_WIDTH(1),
.C_PROBE222_WIDTH(1),
.C_PROBE223_WIDTH(1),
.C_PROBE224_WIDTH(1),
.C_PROBE225_WIDTH(1),
.C_PROBE226_WIDTH(1),
.C_PROBE227_WIDTH(1),
.C_PROBE228_WIDTH(1),
.C_PROBE229_WIDTH(1),
.C_PROBE230_WIDTH(1),
.C_PROBE231_WIDTH(1),
.C_PROBE232_WIDTH(1),
.C_PROBE233_WIDTH(1),
.C_PROBE234_WIDTH(1),
.C_PROBE235_WIDTH(1),
.C_PROBE236_WIDTH(1),
.C_PROBE237_WIDTH(1),
.C_PROBE238_WIDTH(1),
.C_PROBE239_WIDTH(1),
.C_PROBE240_WIDTH(1),
.C_PROBE241_WIDTH(1),
.C_PROBE242_WIDTH(1),
.C_PROBE243_WIDTH(1),
.C_PROBE244_WIDTH(1),
.C_PROBE245_WIDTH(1),
.C_PROBE246_WIDTH(1),
.C_PROBE247_WIDTH(1),
.C_PROBE248_WIDTH(1),
.C_PROBE249_WIDTH(1),
.C_PROBE250_WIDTH(1),
.C_PROBE251_WIDTH(1),
.C_PROBE252_WIDTH(1),
.C_PROBE253_WIDTH(1),
.C_PROBE254_WIDTH(1),
.C_PROBE255_WIDTH(1),
.C_PROBE256_WIDTH(1),
.C_PROBE257_WIDTH(1),
.C_PROBE258_WIDTH(1),
.C_PROBE259_WIDTH(1),
.C_PROBE260_WIDTH(1),
.C_PROBE261_WIDTH(1),
.C_PROBE262_WIDTH(1),
.C_PROBE263_WIDTH(1),
.C_PROBE264_WIDTH(1),
.C_PROBE265_WIDTH(1),
.C_PROBE266_WIDTH(1),
.C_PROBE267_WIDTH(1),
.C_PROBE268_WIDTH(1),
.C_PROBE269_WIDTH(1),
.C_PROBE270_WIDTH(1),
.C_PROBE271_WIDTH(1),
.C_PROBE272_WIDTH(1),
.C_PROBE273_WIDTH(1),
.C_PROBE274_WIDTH(1),
.C_PROBE275_WIDTH(1),
.C_PROBE276_WIDTH(1),
.C_PROBE277_WIDTH(1),
.C_PROBE278_WIDTH(1),
.C_PROBE279_WIDTH(1),
.C_PROBE280_WIDTH(1),
.C_PROBE281_WIDTH(1),
.C_PROBE282_WIDTH(1),
.C_PROBE283_WIDTH(1),
.C_PROBE284_WIDTH(1),
.C_PROBE285_WIDTH(1),
.C_PROBE286_WIDTH(1),
.C_PROBE287_WIDTH(1),
.C_PROBE288_WIDTH(1),
.C_PROBE289_WIDTH(1),
.C_PROBE290_WIDTH(1),
.C_PROBE291_WIDTH(1),
.C_PROBE292_WIDTH(1),
.C_PROBE293_WIDTH(1),
.C_PROBE294_WIDTH(1),
.C_PROBE295_WIDTH(1),
.C_PROBE296_WIDTH(1),
.C_PROBE297_WIDTH(1),
.C_PROBE298_WIDTH(1),
.C_PROBE299_WIDTH(1),
.C_PROBE300_WIDTH(1),
.C_PROBE301_WIDTH(1),
.C_PROBE302_WIDTH(1),
.C_PROBE303_WIDTH(1),
.C_PROBE304_WIDTH(1),
.C_PROBE305_WIDTH(1),
.C_PROBE306_WIDTH(1),
.C_PROBE307_WIDTH(1),
.C_PROBE308_WIDTH(1),
.C_PROBE309_WIDTH(1),
.C_PROBE310_WIDTH(1),
.C_PROBE311_WIDTH(1),
.C_PROBE312_WIDTH(1),
.C_PROBE313_WIDTH(1),
.C_PROBE314_WIDTH(1),
.C_PROBE315_WIDTH(1),
.C_PROBE316_WIDTH(1),
.C_PROBE317_WIDTH(1),
.C_PROBE318_WIDTH(1),
.C_PROBE319_WIDTH(1),
.C_PROBE320_WIDTH(1),
.C_PROBE321_WIDTH(1),
.C_PROBE322_WIDTH(1),
.C_PROBE323_WIDTH(1),
.C_PROBE324_WIDTH(1),
.C_PROBE325_WIDTH(1),
.C_PROBE326_WIDTH(1),
.C_PROBE327_WIDTH(1),
.C_PROBE328_WIDTH(1),
.C_PROBE329_WIDTH(1),
.C_PROBE330_WIDTH(1),
.C_PROBE331_WIDTH(1),
.C_PROBE332_WIDTH(1),
.C_PROBE333_WIDTH(1),
.C_PROBE334_WIDTH(1),
.C_PROBE335_WIDTH(1),
.C_PROBE336_WIDTH(1),
.C_PROBE337_WIDTH(1),
.C_PROBE338_WIDTH(1),
.C_PROBE339_WIDTH(1),
.C_PROBE340_WIDTH(1),
.C_PROBE341_WIDTH(1),
.C_PROBE342_WIDTH(1),
.C_PROBE343_WIDTH(1),
.C_PROBE344_WIDTH(1),
.C_PROBE345_WIDTH(1),
.C_PROBE346_WIDTH(1),
.C_PROBE347_WIDTH(1),
.C_PROBE348_WIDTH(1),
.C_PROBE349_WIDTH(1),
.C_PROBE350_WIDTH(1),
.C_PROBE351_WIDTH(1),
.C_PROBE352_WIDTH(1),
.C_PROBE353_WIDTH(1),
.C_PROBE354_WIDTH(1),
.C_PROBE355_WIDTH(1),
.C_PROBE356_WIDTH(1),
.C_PROBE357_WIDTH(1),
.C_PROBE358_WIDTH(1),
.C_PROBE359_WIDTH(1),
.C_PROBE360_WIDTH(1),
.C_PROBE361_WIDTH(1),
.C_PROBE362_WIDTH(1),
.C_PROBE363_WIDTH(1),
.C_PROBE364_WIDTH(1),
.C_PROBE365_WIDTH(1),
.C_PROBE366_WIDTH(1),
.C_PROBE367_WIDTH(1),
.C_PROBE368_WIDTH(1),
.C_PROBE369_WIDTH(1),
.C_PROBE370_WIDTH(1),
.C_PROBE371_WIDTH(1),
.C_PROBE372_WIDTH(1),
.C_PROBE373_WIDTH(1),
.C_PROBE374_WIDTH(1),
.C_PROBE375_WIDTH(1),
.C_PROBE376_WIDTH(1),
.C_PROBE377_WIDTH(1),
.C_PROBE378_WIDTH(1),
.C_PROBE379_WIDTH(1),
.C_PROBE380_WIDTH(1),
.C_PROBE381_WIDTH(1),
.C_PROBE382_WIDTH(1),
.C_PROBE383_WIDTH(1),
.C_PROBE384_WIDTH(1),
.C_PROBE385_WIDTH(1),
.C_PROBE386_WIDTH(1),
.C_PROBE387_WIDTH(1),
.C_PROBE388_WIDTH(1),
.C_PROBE389_WIDTH(1),
.C_PROBE390_WIDTH(1),
.C_PROBE391_WIDTH(1),
.C_PROBE392_WIDTH(1),
.C_PROBE393_WIDTH(1),
.C_PROBE394_WIDTH(1),
.C_PROBE395_WIDTH(1),
.C_PROBE396_WIDTH(1),
.C_PROBE397_WIDTH(1),
.C_PROBE398_WIDTH(1),
.C_PROBE399_WIDTH(1),
.C_PROBE400_WIDTH(1),
.C_PROBE401_WIDTH(1),
.C_PROBE402_WIDTH(1),
.C_PROBE403_WIDTH(1),
.C_PROBE404_WIDTH(1),
.C_PROBE405_WIDTH(1),
.C_PROBE406_WIDTH(1),
.C_PROBE407_WIDTH(1),
.C_PROBE408_WIDTH(1),
.C_PROBE409_WIDTH(1),
.C_PROBE410_WIDTH(1),
.C_PROBE411_WIDTH(1),
.C_PROBE412_WIDTH(1),
.C_PROBE413_WIDTH(1),
.C_PROBE414_WIDTH(1),
.C_PROBE415_WIDTH(1),
.C_PROBE416_WIDTH(1),
.C_PROBE417_WIDTH(1),
.C_PROBE418_WIDTH(1),
.C_PROBE419_WIDTH(1),
.C_PROBE420_WIDTH(1),
.C_PROBE421_WIDTH(1),
.C_PROBE422_WIDTH(1),
.C_PROBE423_WIDTH(1),
.C_PROBE424_WIDTH(1),
.C_PROBE425_WIDTH(1),
.C_PROBE426_WIDTH(1),
.C_PROBE427_WIDTH(1),
.C_PROBE428_WIDTH(1),
.C_PROBE429_WIDTH(1),
.C_PROBE430_WIDTH(1),
.C_PROBE431_WIDTH(1),
.C_PROBE432_WIDTH(1),
.C_PROBE433_WIDTH(1),
.C_PROBE434_WIDTH(1),
.C_PROBE435_WIDTH(1),
.C_PROBE436_WIDTH(1),
.C_PROBE437_WIDTH(1),
.C_PROBE438_WIDTH(1),
.C_PROBE439_WIDTH(1),
.C_PROBE440_WIDTH(1),
.C_PROBE441_WIDTH(1),
.C_PROBE442_WIDTH(1),
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.C_PROBE31_MU_CNT(1),
.C_PROBE32_MU_CNT(1),
.C_PROBE33_MU_CNT(1),
.C_PROBE34_MU_CNT(1),
.C_PROBE35_MU_CNT(1),
.C_PROBE36_MU_CNT(1),
.C_PROBE37_MU_CNT(1),
.C_PROBE38_MU_CNT(1),
.C_PROBE39_MU_CNT(1),
.C_PROBE40_MU_CNT(1),
.C_PROBE41_MU_CNT(1),
.C_PROBE42_MU_CNT(1),
.C_PROBE43_MU_CNT(1),
.C_PROBE44_MU_CNT(1),
.C_PROBE45_MU_CNT(1),
.C_PROBE46_MU_CNT(1),
.C_PROBE47_MU_CNT(1),
.C_PROBE48_MU_CNT(1),
.C_PROBE49_MU_CNT(1),
.C_PROBE50_MU_CNT(1),
.C_PROBE51_MU_CNT(1),
.C_PROBE52_MU_CNT(1),
.C_PROBE53_MU_CNT(1),
.C_PROBE54_MU_CNT(1),
.C_PROBE55_MU_CNT(1),
.C_PROBE56_MU_CNT(1),
.C_PROBE57_MU_CNT(1),
.C_PROBE58_MU_CNT(1),
.C_PROBE59_MU_CNT(1),
.C_PROBE60_MU_CNT(1),
.C_PROBE61_MU_CNT(1),
.C_PROBE62_MU_CNT(1),
.C_PROBE63_MU_CNT(1),
.C_PROBE64_MU_CNT(1),
.C_PROBE65_MU_CNT(1),
.C_PROBE66_MU_CNT(1),
.C_PROBE67_MU_CNT(1),
.C_PROBE68_MU_CNT(1),
.C_PROBE69_MU_CNT(1),
.C_PROBE70_MU_CNT(1),
.C_PROBE71_MU_CNT(1),
.C_PROBE72_MU_CNT(1),
.C_PROBE73_MU_CNT(1),
.C_PROBE74_MU_CNT(1),
.C_PROBE75_MU_CNT(1),
.C_PROBE76_MU_CNT(1),
.C_PROBE77_MU_CNT(1),
.C_PROBE78_MU_CNT(1),
.C_PROBE79_MU_CNT(1),
.C_PROBE80_MU_CNT(1),
.C_PROBE81_MU_CNT(1),
.C_PROBE82_MU_CNT(1),
.C_PROBE83_MU_CNT(1),
.C_PROBE84_MU_CNT(1),
.C_PROBE85_MU_CNT(1),
.C_PROBE86_MU_CNT(1),
.C_PROBE87_MU_CNT(1),
.C_PROBE88_MU_CNT(1),
.C_PROBE89_MU_CNT(1),
.C_PROBE90_MU_CNT(1),
.C_PROBE91_MU_CNT(1),
.C_PROBE92_MU_CNT(1),
.C_PROBE93_MU_CNT(1),
.C_PROBE94_MU_CNT(1),
.C_PROBE95_MU_CNT(1),
.C_PROBE96_MU_CNT(1),
.C_PROBE97_MU_CNT(1),
.C_PROBE98_MU_CNT(1),
.C_PROBE99_MU_CNT(1),
.C_PROBE100_MU_CNT(1),
.C_PROBE101_MU_CNT(1),
.C_PROBE102_MU_CNT(1),
.C_PROBE103_MU_CNT(1),
.C_PROBE104_MU_CNT(1),
.C_PROBE105_MU_CNT(1),
.C_PROBE106_MU_CNT(1),
.C_PROBE107_MU_CNT(1),
.C_PROBE108_MU_CNT(1),
.C_PROBE109_MU_CNT(1),
.C_PROBE110_MU_CNT(1),
.C_PROBE111_MU_CNT(1),
.C_PROBE112_MU_CNT(1),
.C_PROBE113_MU_CNT(1),
.C_PROBE114_MU_CNT(1),
.C_PROBE115_MU_CNT(1),
.C_PROBE116_MU_CNT(1),
.C_PROBE117_MU_CNT(1),
.C_PROBE118_MU_CNT(1),
.C_PROBE119_MU_CNT(1),
.C_PROBE120_MU_CNT(1),
.C_PROBE121_MU_CNT(1),
.C_PROBE122_MU_CNT(1),
.C_PROBE123_MU_CNT(1),
.C_PROBE124_MU_CNT(1),
.C_PROBE125_MU_CNT(1),
.C_PROBE126_MU_CNT(1),
.C_PROBE127_MU_CNT(1),
.C_PROBE128_MU_CNT(1),
.C_PROBE129_MU_CNT(1),
.C_PROBE130_MU_CNT(1),
.C_PROBE131_MU_CNT(1),
.C_PROBE132_MU_CNT(1),
.C_PROBE133_MU_CNT(1),
.C_PROBE134_MU_CNT(1),
.C_PROBE135_MU_CNT(1),
.C_PROBE136_MU_CNT(1),
.C_PROBE137_MU_CNT(1),
.C_PROBE138_MU_CNT(1),
.C_PROBE139_MU_CNT(1),
.C_PROBE140_MU_CNT(1),
.C_PROBE141_MU_CNT(1),
.C_PROBE142_MU_CNT(1),
.C_PROBE143_MU_CNT(1),
.C_PROBE144_MU_CNT(1),
.C_PROBE145_MU_CNT(1),
.C_PROBE146_MU_CNT(1),
.C_PROBE147_MU_CNT(1),
.C_PROBE148_MU_CNT(1),
.C_PROBE149_MU_CNT(1),
.C_PROBE150_MU_CNT(1),
.C_PROBE151_MU_CNT(1),
.C_PROBE152_MU_CNT(1),
.C_PROBE153_MU_CNT(1),
.C_PROBE154_MU_CNT(1),
.C_PROBE155_MU_CNT(1),
.C_PROBE156_MU_CNT(1),
.C_PROBE157_MU_CNT(1),
.C_PROBE158_MU_CNT(1),
.C_PROBE159_MU_CNT(1),
.C_PROBE160_MU_CNT(1),
.C_PROBE161_MU_CNT(1),
.C_PROBE162_MU_CNT(1),
.C_PROBE163_MU_CNT(1),
.C_PROBE164_MU_CNT(1),
.C_PROBE165_MU_CNT(1),
.C_PROBE166_MU_CNT(1),
.C_PROBE167_MU_CNT(1),
.C_PROBE168_MU_CNT(1),
.C_PROBE169_MU_CNT(1),
.C_PROBE170_MU_CNT(1),
.C_PROBE171_MU_CNT(1),
.C_PROBE172_MU_CNT(1),
.C_PROBE173_MU_CNT(1),
.C_PROBE174_MU_CNT(1),
.C_PROBE175_MU_CNT(1),
.C_PROBE176_MU_CNT(1),
.C_PROBE177_MU_CNT(1),
.C_PROBE178_MU_CNT(1),
.C_PROBE179_MU_CNT(1),
.C_PROBE180_MU_CNT(1),
.C_PROBE181_MU_CNT(1),
.C_PROBE182_MU_CNT(1),
.C_PROBE183_MU_CNT(1),
.C_PROBE184_MU_CNT(1),
.C_PROBE185_MU_CNT(1),
.C_PROBE186_MU_CNT(1),
.C_PROBE187_MU_CNT(1),
.C_PROBE188_MU_CNT(1),
.C_PROBE189_MU_CNT(1),
.C_PROBE190_MU_CNT(1),
.C_PROBE191_MU_CNT(1),
.C_PROBE192_MU_CNT(1),
.C_PROBE193_MU_CNT(1),
.C_PROBE194_MU_CNT(1),
.C_PROBE195_MU_CNT(1),
.C_PROBE196_MU_CNT(1),
.C_PROBE197_MU_CNT(1),
.C_PROBE198_MU_CNT(1),
.C_PROBE199_MU_CNT(1),
.C_PROBE200_MU_CNT(1),
.C_PROBE201_MU_CNT(1),
.C_PROBE202_MU_CNT(1),
.C_PROBE203_MU_CNT(1),
.C_PROBE204_MU_CNT(1),
.C_PROBE205_MU_CNT(1),
.C_PROBE206_MU_CNT(1),
.C_PROBE207_MU_CNT(1),
.C_PROBE208_MU_CNT(1),
.C_PROBE209_MU_CNT(1),
.C_PROBE210_MU_CNT(1),
.C_PROBE211_MU_CNT(1),
.C_PROBE212_MU_CNT(1),
.C_PROBE213_MU_CNT(1),
.C_PROBE214_MU_CNT(1),
.C_PROBE215_MU_CNT(1),
.C_PROBE216_MU_CNT(1),
.C_PROBE217_MU_CNT(1),
.C_PROBE218_MU_CNT(1),
.C_PROBE219_MU_CNT(1),
.C_PROBE220_MU_CNT(1),
.C_PROBE221_MU_CNT(1),
.C_PROBE222_MU_CNT(1),
.C_PROBE223_MU_CNT(1),
.C_PROBE224_MU_CNT(1),
.C_PROBE225_MU_CNT(1),
.C_PROBE226_MU_CNT(1),
.C_PROBE227_MU_CNT(1),
.C_PROBE228_MU_CNT(1),
.C_PROBE229_MU_CNT(1),
.C_PROBE230_MU_CNT(1),
.C_PROBE231_MU_CNT(1),
.C_PROBE232_MU_CNT(1),
.C_PROBE233_MU_CNT(1),
.C_PROBE234_MU_CNT(1),
.C_PROBE235_MU_CNT(1),
.C_PROBE236_MU_CNT(1),
.C_PROBE237_MU_CNT(1),
.C_PROBE238_MU_CNT(1),
.C_PROBE239_MU_CNT(1),
.C_PROBE240_MU_CNT(1),
.C_PROBE241_MU_CNT(1),
.C_PROBE242_MU_CNT(1),
.C_PROBE243_MU_CNT(1),
.C_PROBE244_MU_CNT(1),
.C_PROBE245_MU_CNT(1),
.C_PROBE246_MU_CNT(1),
.C_PROBE247_MU_CNT(1),
.C_PROBE248_MU_CNT(1),
.C_PROBE249_MU_CNT(1),
.C_PROBE250_MU_CNT(1),
.C_PROBE251_MU_CNT(1),
.C_PROBE252_MU_CNT(1),
.C_PROBE253_MU_CNT(1),
.C_PROBE254_MU_CNT(1),
.C_PROBE255_MU_CNT(1),
.C_PROBE256_MU_CNT(1),
.C_PROBE257_MU_CNT(1),
.C_PROBE258_MU_CNT(1),
.C_PROBE259_MU_CNT(1),
.C_PROBE260_MU_CNT(1),
.C_PROBE261_MU_CNT(1),
.C_PROBE262_MU_CNT(1),
.C_PROBE263_MU_CNT(1),
.C_PROBE264_MU_CNT(1),
.C_PROBE265_MU_CNT(1),
.C_PROBE266_MU_CNT(1),
.C_PROBE267_MU_CNT(1),
.C_PROBE268_MU_CNT(1),
.C_PROBE269_MU_CNT(1),
.C_PROBE270_MU_CNT(1),
.C_PROBE271_MU_CNT(1),
.C_PROBE272_MU_CNT(1),
.C_PROBE273_MU_CNT(1),
.C_PROBE274_MU_CNT(1),
.C_PROBE275_MU_CNT(1),
.C_PROBE276_MU_CNT(1),
.C_PROBE277_MU_CNT(1),
.C_PROBE278_MU_CNT(1),
.C_PROBE279_MU_CNT(1),
.C_PROBE280_MU_CNT(1),
.C_PROBE281_MU_CNT(1),
.C_PROBE282_MU_CNT(1),
.C_PROBE283_MU_CNT(1),
.C_PROBE284_MU_CNT(1),
.C_PROBE285_MU_CNT(1),
.C_PROBE286_MU_CNT(1),
.C_PROBE287_MU_CNT(1),
.C_PROBE288_MU_CNT(1),
.C_PROBE289_MU_CNT(1),
.C_PROBE290_MU_CNT(1),
.C_PROBE291_MU_CNT(1),
.C_PROBE292_MU_CNT(1),
.C_PROBE293_MU_CNT(1),
.C_PROBE294_MU_CNT(1),
.C_PROBE295_MU_CNT(1),
.C_PROBE296_MU_CNT(1),
.C_PROBE297_MU_CNT(1),
.C_PROBE298_MU_CNT(1),
.C_PROBE299_MU_CNT(1),
.C_PROBE300_MU_CNT(1),
.C_PROBE301_MU_CNT(1),
.C_PROBE302_MU_CNT(1),
.C_PROBE303_MU_CNT(1),
.C_PROBE304_MU_CNT(1),
.C_PROBE305_MU_CNT(1),
.C_PROBE306_MU_CNT(1),
.C_PROBE307_MU_CNT(1),
.C_PROBE308_MU_CNT(1),
.C_PROBE309_MU_CNT(1),
.C_PROBE310_MU_CNT(1),
.C_PROBE311_MU_CNT(1),
.C_PROBE312_MU_CNT(1),
.C_PROBE313_MU_CNT(1),
.C_PROBE314_MU_CNT(1),
.C_PROBE315_MU_CNT(1),
.C_PROBE316_MU_CNT(1),
.C_PROBE317_MU_CNT(1),
.C_PROBE318_MU_CNT(1),
.C_PROBE319_MU_CNT(1),
.C_PROBE320_MU_CNT(1),
.C_PROBE321_MU_CNT(1),
.C_PROBE322_MU_CNT(1),
.C_PROBE323_MU_CNT(1),
.C_PROBE324_MU_CNT(1),
.C_PROBE325_MU_CNT(1),
.C_PROBE326_MU_CNT(1),
.C_PROBE327_MU_CNT(1),
.C_PROBE328_MU_CNT(1),
.C_PROBE329_MU_CNT(1),
.C_PROBE330_MU_CNT(1),
.C_PROBE331_MU_CNT(1),
.C_PROBE332_MU_CNT(1),
.C_PROBE333_MU_CNT(1),
.C_PROBE334_MU_CNT(1),
.C_PROBE335_MU_CNT(1),
.C_PROBE336_MU_CNT(1),
.C_PROBE337_MU_CNT(1),
.C_PROBE338_MU_CNT(1),
.C_PROBE339_MU_CNT(1),
.C_PROBE340_MU_CNT(1),
.C_PROBE341_MU_CNT(1),
.C_PROBE342_MU_CNT(1),
.C_PROBE343_MU_CNT(1),
.C_PROBE344_MU_CNT(1),
.C_PROBE345_MU_CNT(1),
.C_PROBE346_MU_CNT(1),
.C_PROBE347_MU_CNT(1),
.C_PROBE348_MU_CNT(1),
.C_PROBE349_MU_CNT(1),
.C_PROBE350_MU_CNT(1),
.C_PROBE351_MU_CNT(1),
.C_PROBE352_MU_CNT(1),
.C_PROBE353_MU_CNT(1),
.C_PROBE354_MU_CNT(1),
.C_PROBE355_MU_CNT(1),
.C_PROBE356_MU_CNT(1),
.C_PROBE357_MU_CNT(1),
.C_PROBE358_MU_CNT(1),
.C_PROBE359_MU_CNT(1),
.C_PROBE360_MU_CNT(1),
.C_PROBE361_MU_CNT(1),
.C_PROBE362_MU_CNT(1),
.C_PROBE363_MU_CNT(1),
.C_PROBE364_MU_CNT(1),
.C_PROBE365_MU_CNT(1),
.C_PROBE366_MU_CNT(1),
.C_PROBE367_MU_CNT(1),
.C_PROBE368_MU_CNT(1),
.C_PROBE369_MU_CNT(1),
.C_PROBE370_MU_CNT(1),
.C_PROBE371_MU_CNT(1),
.C_PROBE372_MU_CNT(1),
.C_PROBE373_MU_CNT(1),
.C_PROBE374_MU_CNT(1),
.C_PROBE375_MU_CNT(1),
.C_PROBE376_MU_CNT(1),
.C_PROBE377_MU_CNT(1),
.C_PROBE378_MU_CNT(1),
.C_PROBE379_MU_CNT(1),
.C_PROBE380_MU_CNT(1),
.C_PROBE381_MU_CNT(1),
.C_PROBE382_MU_CNT(1),
.C_PROBE383_MU_CNT(1),
.C_PROBE384_MU_CNT(1),
.C_PROBE385_MU_CNT(1),
.C_PROBE386_MU_CNT(1),
.C_PROBE387_MU_CNT(1),
.C_PROBE388_MU_CNT(1),
.C_PROBE389_MU_CNT(1),
.C_PROBE390_MU_CNT(1),
.C_PROBE391_MU_CNT(1),
.C_PROBE392_MU_CNT(1),
.C_PROBE393_MU_CNT(1),
.C_PROBE394_MU_CNT(1),
.C_PROBE395_MU_CNT(1),
.C_PROBE396_MU_CNT(1),
.C_PROBE397_MU_CNT(1),
.C_PROBE398_MU_CNT(1),
.C_PROBE399_MU_CNT(1),
.C_PROBE400_MU_CNT(1),
.C_PROBE401_MU_CNT(1),
.C_PROBE402_MU_CNT(1),
.C_PROBE403_MU_CNT(1),
.C_PROBE404_MU_CNT(1),
.C_PROBE405_MU_CNT(1),
.C_PROBE406_MU_CNT(1),
.C_PROBE407_MU_CNT(1),
.C_PROBE408_MU_CNT(1),
.C_PROBE409_MU_CNT(1),
.C_PROBE410_MU_CNT(1),
.C_PROBE411_MU_CNT(1),
.C_PROBE412_MU_CNT(1),
.C_PROBE413_MU_CNT(1),
.C_PROBE414_MU_CNT(1),
.C_PROBE415_MU_CNT(1),
.C_PROBE416_MU_CNT(1),
.C_PROBE417_MU_CNT(1),
.C_PROBE418_MU_CNT(1),
.C_PROBE419_MU_CNT(1),
.C_PROBE420_MU_CNT(1),
.C_PROBE421_MU_CNT(1),
.C_PROBE422_MU_CNT(1),
.C_PROBE423_MU_CNT(1),
.C_PROBE424_MU_CNT(1),
.C_PROBE425_MU_CNT(1),
.C_PROBE426_MU_CNT(1),
.C_PROBE427_MU_CNT(1),
.C_PROBE428_MU_CNT(1),
.C_PROBE429_MU_CNT(1),
.C_PROBE430_MU_CNT(1),
.C_PROBE431_MU_CNT(1),
.C_PROBE432_MU_CNT(1),
.C_PROBE433_MU_CNT(1),
.C_PROBE434_MU_CNT(1),
.C_PROBE435_MU_CNT(1),
.C_PROBE436_MU_CNT(1),
.C_PROBE437_MU_CNT(1),
.C_PROBE438_MU_CNT(1),
.C_PROBE439_MU_CNT(1),
.C_PROBE440_MU_CNT(1),
.C_PROBE441_MU_CNT(1),
.C_PROBE442_MU_CNT(1),
.C_PROBE443_MU_CNT(1),
.C_PROBE444_MU_CNT(1),
.C_PROBE445_MU_CNT(1),
.C_PROBE446_MU_CNT(1),
.C_PROBE447_MU_CNT(1),
.C_PROBE448_MU_CNT(1),
.C_PROBE449_MU_CNT(1),
.C_PROBE450_MU_CNT(1),
.C_PROBE451_MU_CNT(1),
.C_PROBE452_MU_CNT(1),
.C_PROBE453_MU_CNT(1),
.C_PROBE454_MU_CNT(1),
.C_PROBE455_MU_CNT(1),
.C_PROBE456_MU_CNT(1),
.C_PROBE457_MU_CNT(1),
.C_PROBE458_MU_CNT(1),
.C_PROBE459_MU_CNT(1),
.C_PROBE460_MU_CNT(1),
.C_PROBE461_MU_CNT(1),
.C_PROBE462_MU_CNT(1),
.C_PROBE463_MU_CNT(1),
.C_PROBE464_MU_CNT(1),
.C_PROBE465_MU_CNT(1),
.C_PROBE466_MU_CNT(1),
.C_PROBE467_MU_CNT(1),
.C_PROBE468_MU_CNT(1),
.C_PROBE469_MU_CNT(1),
.C_PROBE470_MU_CNT(1),
.C_PROBE471_MU_CNT(1),
.C_PROBE472_MU_CNT(1),
.C_PROBE473_MU_CNT(1),
.C_PROBE474_MU_CNT(1),
.C_PROBE475_MU_CNT(1),
.C_PROBE476_MU_CNT(1),
.C_PROBE477_MU_CNT(1),
.C_PROBE478_MU_CNT(1),
.C_PROBE479_MU_CNT(1),
.C_PROBE480_MU_CNT(1),
.C_PROBE481_MU_CNT(1),
.C_PROBE482_MU_CNT(1),
.C_PROBE483_MU_CNT(1),
.C_PROBE484_MU_CNT(1),
.C_PROBE485_MU_CNT(1),
.C_PROBE486_MU_CNT(1),
.C_PROBE487_MU_CNT(1),
.C_PROBE488_MU_CNT(1),
.C_PROBE489_MU_CNT(1),
.C_PROBE490_MU_CNT(1),
.C_PROBE491_MU_CNT(1),
.C_PROBE492_MU_CNT(1),
.C_PROBE493_MU_CNT(1),
.C_PROBE494_MU_CNT(1),
.C_PROBE495_MU_CNT(1),
.C_PROBE496_MU_CNT(1),
.C_PROBE497_MU_CNT(1),
.C_PROBE498_MU_CNT(1),
.C_PROBE499_MU_CNT(1),
.C_PROBE500_MU_CNT(1),
.C_PROBE501_MU_CNT(1),
.C_PROBE502_MU_CNT(1),
.C_PROBE503_MU_CNT(1),
.C_PROBE504_MU_CNT(1),
.C_PROBE505_MU_CNT(1),
.C_PROBE506_MU_CNT(1),
.C_PROBE507_MU_CNT(1),
.C_PROBE508_MU_CNT(1),
.C_PROBE509_MU_CNT(1),
.C_PROBE510_MU_CNT(1),
.C_PROBE511_MU_CNT(1),
.C_PROBE512_MU_CNT(1),
.C_PROBE513_MU_CNT(1),
.C_PROBE514_MU_CNT(1),
.C_PROBE515_MU_CNT(1),
.C_PROBE516_MU_CNT(1),
.C_PROBE517_MU_CNT(1),
.C_PROBE518_MU_CNT(1),
.C_PROBE519_MU_CNT(1),
.C_PROBE520_MU_CNT(1),
.C_PROBE521_MU_CNT(1),
.C_PROBE522_MU_CNT(1),
.C_PROBE523_MU_CNT(1),
.C_PROBE524_MU_CNT(1),
.C_PROBE525_MU_CNT(1),
.C_PROBE526_MU_CNT(1),
.C_PROBE527_MU_CNT(1),
.C_PROBE528_MU_CNT(1),
.C_PROBE529_MU_CNT(1),
.C_PROBE530_MU_CNT(1),
.C_PROBE531_MU_CNT(1),
.C_PROBE532_MU_CNT(1),
.C_PROBE533_MU_CNT(1),
.C_PROBE534_MU_CNT(1),
.C_PROBE535_MU_CNT(1),
.C_PROBE536_MU_CNT(1),
.C_PROBE537_MU_CNT(1),
.C_PROBE538_MU_CNT(1),
.C_PROBE539_MU_CNT(1),
.C_PROBE540_MU_CNT(1),
.C_PROBE541_MU_CNT(1),
.C_PROBE542_MU_CNT(1),
.C_PROBE543_MU_CNT(1),
.C_PROBE544_MU_CNT(1),
.C_PROBE545_MU_CNT(1),
.C_PROBE546_MU_CNT(1),
.C_PROBE547_MU_CNT(1),
.C_PROBE548_MU_CNT(1),
.C_PROBE549_MU_CNT(1),
.C_PROBE550_MU_CNT(1),
.C_PROBE551_MU_CNT(1),
.C_PROBE552_MU_CNT(1),
.C_PROBE553_MU_CNT(1),
.C_PROBE554_MU_CNT(1),
.C_PROBE555_MU_CNT(1),
.C_PROBE556_MU_CNT(1),
.C_PROBE557_MU_CNT(1),
.C_PROBE558_MU_CNT(1),
.C_PROBE559_MU_CNT(1),
.C_PROBE560_MU_CNT(1),
.C_PROBE561_MU_CNT(1),
.C_PROBE562_MU_CNT(1),
.C_PROBE563_MU_CNT(1),
.C_PROBE564_MU_CNT(1),
.C_PROBE565_MU_CNT(1),
.C_PROBE566_MU_CNT(1),
.C_PROBE567_MU_CNT(1),
.C_PROBE568_MU_CNT(1),
.C_PROBE569_MU_CNT(1),
.C_PROBE570_MU_CNT(1),
.C_PROBE571_MU_CNT(1),
.C_PROBE572_MU_CNT(1),
.C_PROBE573_MU_CNT(1),
.C_PROBE574_MU_CNT(1),
.C_PROBE575_MU_CNT(1),
.C_PROBE576_MU_CNT(1),
.C_PROBE577_MU_CNT(1),
.C_PROBE578_MU_CNT(1),
.C_PROBE579_MU_CNT(1),
.C_PROBE580_MU_CNT(1),
.C_PROBE581_MU_CNT(1),
.C_PROBE582_MU_CNT(1),
.C_PROBE583_MU_CNT(1),
.C_PROBE584_MU_CNT(1),
.C_PROBE585_MU_CNT(1),
.C_PROBE586_MU_CNT(1),
.C_PROBE587_MU_CNT(1),
.C_PROBE588_MU_CNT(1),
.C_PROBE589_MU_CNT(1),
.C_PROBE590_MU_CNT(1),
.C_PROBE591_MU_CNT(1),
.C_PROBE592_MU_CNT(1),
.C_PROBE593_MU_CNT(1),
.C_PROBE594_MU_CNT(1),
.C_PROBE595_MU_CNT(1),
.C_PROBE596_MU_CNT(1),
.C_PROBE597_MU_CNT(1),
.C_PROBE598_MU_CNT(1),
.C_PROBE599_MU_CNT(1),
.C_PROBE600_MU_CNT(1),
.C_PROBE601_MU_CNT(1),
.C_PROBE602_MU_CNT(1),
.C_PROBE603_MU_CNT(1),
.C_PROBE604_MU_CNT(1),
.C_PROBE605_MU_CNT(1),
.C_PROBE606_MU_CNT(1),
.C_PROBE607_MU_CNT(1),
.C_PROBE608_MU_CNT(1),
.C_PROBE609_MU_CNT(1),
.C_PROBE610_MU_CNT(1),
.C_PROBE611_MU_CNT(1),
.C_PROBE612_MU_CNT(1),
.C_PROBE613_MU_CNT(1),
.C_PROBE614_MU_CNT(1),
.C_PROBE615_MU_CNT(1),
.C_PROBE616_MU_CNT(1),
.C_PROBE617_MU_CNT(1),
.C_PROBE618_MU_CNT(1),
.C_PROBE619_MU_CNT(1),
.C_PROBE620_MU_CNT(1),
.C_PROBE621_MU_CNT(1),
.C_PROBE622_MU_CNT(1),
.C_PROBE623_MU_CNT(1),
.C_PROBE624_MU_CNT(1),
.C_PROBE625_MU_CNT(1),
.C_PROBE626_MU_CNT(1),
.C_PROBE627_MU_CNT(1),
.C_PROBE628_MU_CNT(1),
.C_PROBE629_MU_CNT(1),
.C_PROBE630_MU_CNT(1),
.C_PROBE631_MU_CNT(1),
.C_PROBE632_MU_CNT(1),
.C_PROBE633_MU_CNT(1),
.C_PROBE634_MU_CNT(1),
.C_PROBE635_MU_CNT(1),
.C_PROBE636_MU_CNT(1),
.C_PROBE637_MU_CNT(1),
.C_PROBE638_MU_CNT(1),
.C_PROBE639_MU_CNT(1),
.C_PROBE640_MU_CNT(1),
.C_PROBE641_MU_CNT(1),
.C_PROBE642_MU_CNT(1),
.C_PROBE643_MU_CNT(1),
.C_PROBE644_MU_CNT(1),
.C_PROBE645_MU_CNT(1),
.C_PROBE646_MU_CNT(1),
.C_PROBE647_MU_CNT(1),
.C_PROBE648_MU_CNT(1),
.C_PROBE649_MU_CNT(1),
.C_PROBE650_MU_CNT(1),
.C_PROBE651_MU_CNT(1),
.C_PROBE652_MU_CNT(1),
.C_PROBE653_MU_CNT(1),
.C_PROBE654_MU_CNT(1),
.C_PROBE655_MU_CNT(1),
.C_PROBE656_MU_CNT(1),
.C_PROBE657_MU_CNT(1),
.C_PROBE658_MU_CNT(1),
.C_PROBE659_MU_CNT(1),
.C_PROBE660_MU_CNT(1),
.C_PROBE661_MU_CNT(1),
.C_PROBE662_MU_CNT(1),
.C_PROBE663_MU_CNT(1),
.C_PROBE664_MU_CNT(1),
.C_PROBE665_MU_CNT(1),
.C_PROBE666_MU_CNT(1),
.C_PROBE667_MU_CNT(1),
.C_PROBE668_MU_CNT(1),
.C_PROBE669_MU_CNT(1),
.C_PROBE670_MU_CNT(1),
.C_PROBE671_MU_CNT(1),
.C_PROBE672_MU_CNT(1),
.C_PROBE673_MU_CNT(1),
.C_PROBE674_MU_CNT(1),
.C_PROBE675_MU_CNT(1),
.C_PROBE676_MU_CNT(1),
.C_PROBE677_MU_CNT(1),
.C_PROBE678_MU_CNT(1),
.C_PROBE679_MU_CNT(1),
.C_PROBE680_MU_CNT(1),
.C_PROBE681_MU_CNT(1),
.C_PROBE682_MU_CNT(1),
.C_PROBE683_MU_CNT(1),
.C_PROBE684_MU_CNT(1),
.C_PROBE685_MU_CNT(1),
.C_PROBE686_MU_CNT(1),
.C_PROBE687_MU_CNT(1),
.C_PROBE688_MU_CNT(1),
.C_PROBE689_MU_CNT(1),
.C_PROBE690_MU_CNT(1),
.C_PROBE691_MU_CNT(1),
.C_PROBE692_MU_CNT(1),
.C_PROBE693_MU_CNT(1),
.C_PROBE694_MU_CNT(1),
.C_PROBE695_MU_CNT(1),
.C_PROBE696_MU_CNT(1),
.C_PROBE697_MU_CNT(1),
.C_PROBE698_MU_CNT(1),
.C_PROBE699_MU_CNT(1),
.C_PROBE700_MU_CNT(1),
.C_PROBE701_MU_CNT(1),
.C_PROBE702_MU_CNT(1),
.C_PROBE703_MU_CNT(1),
.C_PROBE704_MU_CNT(1),
.C_PROBE705_MU_CNT(1),
.C_PROBE706_MU_CNT(1),
.C_PROBE707_MU_CNT(1),
.C_PROBE708_MU_CNT(1),
.C_PROBE709_MU_CNT(1),
.C_PROBE710_MU_CNT(1),
.C_PROBE711_MU_CNT(1),
.C_PROBE712_MU_CNT(1),
.C_PROBE713_MU_CNT(1),
.C_PROBE714_MU_CNT(1),
.C_PROBE715_MU_CNT(1),
.C_PROBE716_MU_CNT(1),
.C_PROBE717_MU_CNT(1),
.C_PROBE718_MU_CNT(1),
.C_PROBE719_MU_CNT(1),
.C_PROBE720_MU_CNT(1),
.C_PROBE721_MU_CNT(1),
.C_PROBE722_MU_CNT(1),
.C_PROBE723_MU_CNT(1),
.C_PROBE724_MU_CNT(1),
.C_PROBE725_MU_CNT(1),
.C_PROBE726_MU_CNT(1),
.C_PROBE727_MU_CNT(1),
.C_PROBE728_MU_CNT(1),
.C_PROBE729_MU_CNT(1),
.C_PROBE730_MU_CNT(1),
.C_PROBE731_MU_CNT(1),
.C_PROBE732_MU_CNT(1),
.C_PROBE733_MU_CNT(1),
.C_PROBE734_MU_CNT(1),
.C_PROBE735_MU_CNT(1),
.C_PROBE736_MU_CNT(1),
.C_PROBE737_MU_CNT(1),
.C_PROBE738_MU_CNT(1),
.C_PROBE739_MU_CNT(1),
.C_PROBE740_MU_CNT(1),
.C_PROBE741_MU_CNT(1),
.C_PROBE742_MU_CNT(1),
.C_PROBE743_MU_CNT(1),
.C_PROBE744_MU_CNT(1),
.C_PROBE745_MU_CNT(1),
.C_PROBE746_MU_CNT(1),
.C_PROBE747_MU_CNT(1),
.C_PROBE748_MU_CNT(1),
.C_PROBE749_MU_CNT(1),
.C_PROBE750_MU_CNT(1),
.C_PROBE751_MU_CNT(1),
.C_PROBE752_MU_CNT(1),
.C_PROBE753_MU_CNT(1),
.C_PROBE754_MU_CNT(1),
.C_PROBE755_MU_CNT(1),
.C_PROBE756_MU_CNT(1),
.C_PROBE757_MU_CNT(1),
.C_PROBE758_MU_CNT(1),
.C_PROBE759_MU_CNT(1),
.C_PROBE760_MU_CNT(1),
.C_PROBE761_MU_CNT(1),
.C_PROBE762_MU_CNT(1),
.C_PROBE763_MU_CNT(1),
.C_PROBE764_MU_CNT(1),
.C_PROBE765_MU_CNT(1),
.C_PROBE766_MU_CNT(1),
.C_PROBE767_MU_CNT(1),
.C_PROBE768_MU_CNT(1),
.C_PROBE769_MU_CNT(1),
.C_PROBE770_MU_CNT(1),
.C_PROBE771_MU_CNT(1),
.C_PROBE772_MU_CNT(1),
.C_PROBE773_MU_CNT(1),
.C_PROBE774_MU_CNT(1),
.C_PROBE775_MU_CNT(1),
.C_PROBE776_MU_CNT(1),
.C_PROBE777_MU_CNT(1),
.C_PROBE778_MU_CNT(1),
.C_PROBE779_MU_CNT(1),
.C_PROBE780_MU_CNT(1),
.C_PROBE781_MU_CNT(1),
.C_PROBE782_MU_CNT(1),
.C_PROBE783_MU_CNT(1),
.C_PROBE784_MU_CNT(1),
.C_PROBE785_MU_CNT(1),
.C_PROBE786_MU_CNT(1),
.C_PROBE787_MU_CNT(1),
.C_PROBE788_MU_CNT(1),
.C_PROBE789_MU_CNT(1),
.C_PROBE790_MU_CNT(1),
.C_PROBE791_MU_CNT(1),
.C_PROBE792_MU_CNT(1),
.C_PROBE793_MU_CNT(1),
.C_PROBE794_MU_CNT(1),
.C_PROBE795_MU_CNT(1),
.C_PROBE796_MU_CNT(1),
.C_PROBE797_MU_CNT(1),
.C_PROBE798_MU_CNT(1),
.C_PROBE799_MU_CNT(1),
.C_PROBE800_MU_CNT(1),
.C_PROBE801_MU_CNT(1),
.C_PROBE802_MU_CNT(1),
.C_PROBE803_MU_CNT(1),
.C_PROBE804_MU_CNT(1),
.C_PROBE805_MU_CNT(1),
.C_PROBE806_MU_CNT(1),
.C_PROBE807_MU_CNT(1),
.C_PROBE808_MU_CNT(1),
.C_PROBE809_MU_CNT(1),
.C_PROBE810_MU_CNT(1),
.C_PROBE811_MU_CNT(1),
.C_PROBE812_MU_CNT(1),
.C_PROBE813_MU_CNT(1),
.C_PROBE814_MU_CNT(1),
.C_PROBE815_MU_CNT(1),
.C_PROBE816_MU_CNT(1),
.C_PROBE817_MU_CNT(1),
.C_PROBE818_MU_CNT(1),
.C_PROBE819_MU_CNT(1),
.C_PROBE820_MU_CNT(1),
.C_PROBE821_MU_CNT(1),
.C_PROBE822_MU_CNT(1),
.C_PROBE823_MU_CNT(1),
.C_PROBE824_MU_CNT(1),
.C_PROBE825_MU_CNT(1),
.C_PROBE826_MU_CNT(1),
.C_PROBE827_MU_CNT(1),
.C_PROBE828_MU_CNT(1),
.C_PROBE829_MU_CNT(1),
.C_PROBE830_MU_CNT(1),
.C_PROBE831_MU_CNT(1),
.C_PROBE832_MU_CNT(1),
.C_PROBE833_MU_CNT(1),
.C_PROBE834_MU_CNT(1),
.C_PROBE835_MU_CNT(1),
.C_PROBE836_MU_CNT(1),
.C_PROBE837_MU_CNT(1),
.C_PROBE838_MU_CNT(1),
.C_PROBE839_MU_CNT(1),
.C_PROBE840_MU_CNT(1),
.C_PROBE841_MU_CNT(1),
.C_PROBE842_MU_CNT(1),
.C_PROBE843_MU_CNT(1),
.C_PROBE844_MU_CNT(1),
.C_PROBE845_MU_CNT(1),
.C_PROBE846_MU_CNT(1),
.C_PROBE847_MU_CNT(1),
.C_PROBE848_MU_CNT(1),
.C_PROBE849_MU_CNT(1),
.C_PROBE850_MU_CNT(1),
.C_PROBE851_MU_CNT(1),
.C_PROBE852_MU_CNT(1),
.C_PROBE853_MU_CNT(1),
.C_PROBE854_MU_CNT(1),
.C_PROBE855_MU_CNT(1),
.C_PROBE856_MU_CNT(1),
.C_PROBE857_MU_CNT(1),
.C_PROBE858_MU_CNT(1),
.C_PROBE859_MU_CNT(1),
.C_PROBE860_MU_CNT(1),
.C_PROBE861_MU_CNT(1),
.C_PROBE862_MU_CNT(1),
.C_PROBE863_MU_CNT(1),
.C_PROBE864_MU_CNT(1),
.C_PROBE865_MU_CNT(1),
.C_PROBE866_MU_CNT(1),
.C_PROBE867_MU_CNT(1),
.C_PROBE868_MU_CNT(1),
.C_PROBE869_MU_CNT(1),
.C_PROBE870_MU_CNT(1),
.C_PROBE871_MU_CNT(1),
.C_PROBE872_MU_CNT(1),
.C_PROBE873_MU_CNT(1),
.C_PROBE874_MU_CNT(1),
.C_PROBE875_MU_CNT(1),
.C_PROBE876_MU_CNT(1),
.C_PROBE877_MU_CNT(1),
.C_PROBE878_MU_CNT(1),
.C_PROBE879_MU_CNT(1),
.C_PROBE880_MU_CNT(1),
.C_PROBE881_MU_CNT(1),
.C_PROBE882_MU_CNT(1),
.C_PROBE883_MU_CNT(1),
.C_PROBE884_MU_CNT(1),
.C_PROBE885_MU_CNT(1),
.C_PROBE886_MU_CNT(1),
.C_PROBE887_MU_CNT(1),
.C_PROBE888_MU_CNT(1),
.C_PROBE889_MU_CNT(1),
.C_PROBE890_MU_CNT(1),
.C_PROBE891_MU_CNT(1),
.C_PROBE892_MU_CNT(1),
.C_PROBE893_MU_CNT(1),
.C_PROBE894_MU_CNT(1),
.C_PROBE895_MU_CNT(1),
.C_PROBE896_MU_CNT(1),
.C_PROBE897_MU_CNT(1),
.C_PROBE898_MU_CNT(1),
.C_PROBE899_MU_CNT(1),
.C_PROBE900_MU_CNT(1),
.C_PROBE901_MU_CNT(1),
.C_PROBE902_MU_CNT(1),
.C_PROBE903_MU_CNT(1),
.C_PROBE904_MU_CNT(1),
.C_PROBE905_MU_CNT(1),
.C_PROBE906_MU_CNT(1),
.C_PROBE907_MU_CNT(1),
.C_PROBE908_MU_CNT(1),
.C_PROBE909_MU_CNT(1),
.C_PROBE910_MU_CNT(1),
.C_PROBE911_MU_CNT(1),
.C_PROBE912_MU_CNT(1),
.C_PROBE913_MU_CNT(1),
.C_PROBE914_MU_CNT(1),
.C_PROBE915_MU_CNT(1),
.C_PROBE916_MU_CNT(1),
.C_PROBE917_MU_CNT(1),
.C_PROBE918_MU_CNT(1),
.C_PROBE919_MU_CNT(1),
.C_PROBE920_MU_CNT(1),
.C_PROBE921_MU_CNT(1),
.C_PROBE922_MU_CNT(1),
.C_PROBE923_MU_CNT(1),
.C_PROBE924_MU_CNT(1),
.C_PROBE925_MU_CNT(1),
.C_PROBE926_MU_CNT(1),
.C_PROBE927_MU_CNT(1),
.C_PROBE928_MU_CNT(1),
.C_PROBE929_MU_CNT(1),
.C_PROBE930_MU_CNT(1),
.C_PROBE931_MU_CNT(1),
.C_PROBE932_MU_CNT(1),
.C_PROBE933_MU_CNT(1),
.C_PROBE934_MU_CNT(1),
.C_PROBE935_MU_CNT(1),
.C_PROBE936_MU_CNT(1),
.C_PROBE937_MU_CNT(1),
.C_PROBE938_MU_CNT(1),
.C_PROBE939_MU_CNT(1),
.C_PROBE940_MU_CNT(1),
.C_PROBE941_MU_CNT(1),
.C_PROBE942_MU_CNT(1),
.C_PROBE943_MU_CNT(1),
.C_PROBE944_MU_CNT(1),
.C_PROBE945_MU_CNT(1),
.C_PROBE946_MU_CNT(1),
.C_PROBE947_MU_CNT(1),
.C_PROBE948_MU_CNT(1),
.C_PROBE949_MU_CNT(1),
.C_PROBE950_MU_CNT(1),
.C_PROBE951_MU_CNT(1),
.C_PROBE952_MU_CNT(1),
.C_PROBE953_MU_CNT(1),
.C_PROBE954_MU_CNT(1),
.C_PROBE955_MU_CNT(1),
.C_PROBE956_MU_CNT(1),
.C_PROBE957_MU_CNT(1),
.C_PROBE958_MU_CNT(1),
.C_PROBE959_MU_CNT(1),
.C_PROBE960_MU_CNT(1),
.C_PROBE961_MU_CNT(1),
.C_PROBE962_MU_CNT(1),
.C_PROBE963_MU_CNT(1),
.C_PROBE964_MU_CNT(1),
.C_PROBE965_MU_CNT(1),
.C_PROBE966_MU_CNT(1),
.C_PROBE967_MU_CNT(1),
.C_PROBE968_MU_CNT(1),
.C_PROBE969_MU_CNT(1),
.C_PROBE970_MU_CNT(1),
.C_PROBE971_MU_CNT(1),
.C_PROBE972_MU_CNT(1),
.C_PROBE973_MU_CNT(1),
.C_PROBE974_MU_CNT(1),
.C_PROBE975_MU_CNT(1),
.C_PROBE976_MU_CNT(1),
.C_PROBE977_MU_CNT(1),
.C_PROBE978_MU_CNT(1),
.C_PROBE979_MU_CNT(1),
.C_PROBE980_MU_CNT(1),
.C_PROBE981_MU_CNT(1),
.C_PROBE982_MU_CNT(1),
.C_PROBE983_MU_CNT(1),
.C_PROBE984_MU_CNT(1),
.C_PROBE985_MU_CNT(1),
.C_PROBE986_MU_CNT(1),
.C_PROBE987_MU_CNT(1),
.C_PROBE988_MU_CNT(1),
.C_PROBE989_MU_CNT(1),
.C_PROBE990_MU_CNT(1),
.C_PROBE991_MU_CNT(1),
.C_PROBE992_MU_CNT(1),
.C_PROBE993_MU_CNT(1),
.C_PROBE994_MU_CNT(1),
.C_PROBE995_MU_CNT(1),
.C_PROBE996_MU_CNT(1),
.C_PROBE997_MU_CNT(1),
.C_PROBE998_MU_CNT(1),
.C_PROBE999_MU_CNT(1),
.C_PROBE1000_MU_CNT(1),
.C_PROBE1001_MU_CNT(1),
.C_PROBE1002_MU_CNT(1),
.C_PROBE1003_MU_CNT(1),
.C_PROBE1004_MU_CNT(1),
.C_PROBE1005_MU_CNT(1),
.C_PROBE1006_MU_CNT(1),
.C_PROBE1007_MU_CNT(1),
.C_PROBE1008_MU_CNT(1),
.C_PROBE1009_MU_CNT(1),
.C_PROBE1010_MU_CNT(1),
.C_PROBE1011_MU_CNT(1),
.C_PROBE1012_MU_CNT(1),
.C_PROBE1013_MU_CNT(1),
.C_PROBE1014_MU_CNT(1),
.C_PROBE1015_MU_CNT(1),
.C_PROBE1016_MU_CNT(1),
.C_PROBE1017_MU_CNT(1),
.C_PROBE1018_MU_CNT(1),
.C_PROBE1019_MU_CNT(1),
.C_PROBE1020_MU_CNT(1),
.C_PROBE1021_MU_CNT(1),
.C_PROBE1022_MU_CNT(1),
.C_PROBE1023_MU_CNT(1),
.C_PROBE0_TYPE(0),
.C_PROBE1_TYPE(0),
.C_PROBE2_TYPE(0),
.C_PROBE3_TYPE(0),
.C_PROBE4_TYPE(0),
.C_PROBE5_TYPE(0),
.C_PROBE6_TYPE(0),
.C_PROBE7_TYPE(0),
.C_PROBE8_TYPE(0),
.C_PROBE9_TYPE(0),
.C_PROBE10_TYPE(0),
.C_PROBE11_TYPE(0),
.C_PROBE12_TYPE(0),
.C_PROBE13_TYPE(0),
.C_PROBE14_TYPE(0),
.C_PROBE15_TYPE(0),
.C_PROBE16_TYPE(0),
.C_PROBE17_TYPE(0),
.C_PROBE18_TYPE(0),
.C_PROBE19_TYPE(0),
.C_PROBE20_TYPE(0),
.C_PROBE21_TYPE(1),
.C_PROBE22_TYPE(1),
.C_PROBE23_TYPE(1),
.C_PROBE24_TYPE(1),
.C_PROBE25_TYPE(1),
.C_PROBE26_TYPE(1),
.C_PROBE27_TYPE(1),
.C_PROBE28_TYPE(1),
.C_PROBE29_TYPE(1),
.C_PROBE30_TYPE(1),
.C_PROBE31_TYPE(1),
.C_PROBE32_TYPE(1),
.C_PROBE33_TYPE(1),
.C_PROBE34_TYPE(1),
.C_PROBE35_TYPE(1),
.C_PROBE36_TYPE(1),
.C_PROBE37_TYPE(1),
.C_PROBE38_TYPE(1),
.C_PROBE39_TYPE(1),
.C_PROBE40_TYPE(1),
.C_PROBE41_TYPE(1),
.C_PROBE42_TYPE(1),
.C_PROBE43_TYPE(1),
.C_PROBE44_TYPE(1),
.C_PROBE45_TYPE(1),
.C_PROBE46_TYPE(1),
.C_PROBE47_TYPE(1),
.C_PROBE48_TYPE(1),
.C_PROBE49_TYPE(1),
.C_PROBE50_TYPE(1),
.C_PROBE51_TYPE(1),
.C_PROBE52_TYPE(1),
.C_PROBE53_TYPE(1),
.C_PROBE54_TYPE(1),
.C_PROBE55_TYPE(1),
.C_PROBE56_TYPE(1),
.C_PROBE57_TYPE(1),
.C_PROBE58_TYPE(1),
.C_PROBE59_TYPE(1),
.C_PROBE60_TYPE(1),
.C_PROBE61_TYPE(1),
.C_PROBE62_TYPE(1),
.C_PROBE63_TYPE(1),
.C_PROBE64_TYPE(1),
.C_PROBE65_TYPE(1),
.C_PROBE66_TYPE(1),
.C_PROBE67_TYPE(1),
.C_PROBE68_TYPE(1),
.C_PROBE69_TYPE(1),
.C_PROBE70_TYPE(1),
.C_PROBE71_TYPE(1),
.C_PROBE72_TYPE(1),
.C_PROBE73_TYPE(1),
.C_PROBE74_TYPE(1),
.C_PROBE75_TYPE(1),
.C_PROBE76_TYPE(1),
.C_PROBE77_TYPE(1),
.C_PROBE78_TYPE(1),
.C_PROBE79_TYPE(1),
.C_PROBE80_TYPE(1),
.C_PROBE81_TYPE(1),
.C_PROBE82_TYPE(1),
.C_PROBE83_TYPE(1),
.C_PROBE84_TYPE(1),
.C_PROBE85_TYPE(1),
.C_PROBE86_TYPE(1),
.C_PROBE87_TYPE(1),
.C_PROBE88_TYPE(1),
.C_PROBE89_TYPE(1),
.C_PROBE90_TYPE(1),
.C_PROBE91_TYPE(1),
.C_PROBE92_TYPE(1),
.C_PROBE93_TYPE(1),
.C_PROBE94_TYPE(1),
.C_PROBE95_TYPE(1),
.C_PROBE96_TYPE(1),
.C_PROBE97_TYPE(1),
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.C_PROBE726_TYPE(1),
.C_PROBE727_TYPE(1),
.C_PROBE728_TYPE(1),
.C_PROBE729_TYPE(1),
.C_PROBE730_TYPE(1),
.C_PROBE731_TYPE(1),
.C_PROBE732_TYPE(1),
.C_PROBE733_TYPE(1),
.C_PROBE734_TYPE(1),
.C_PROBE735_TYPE(1),
.C_PROBE736_TYPE(1),
.C_PROBE737_TYPE(1),
.C_PROBE738_TYPE(1),
.C_PROBE739_TYPE(1),
.C_PROBE740_TYPE(1),
.C_PROBE741_TYPE(1),
.C_PROBE742_TYPE(1),
.C_PROBE743_TYPE(1),
.C_PROBE744_TYPE(1),
.C_PROBE745_TYPE(1),
.C_PROBE746_TYPE(1),
.C_PROBE747_TYPE(1),
.C_PROBE748_TYPE(1),
.C_PROBE749_TYPE(1),
.C_PROBE750_TYPE(1),
.C_PROBE751_TYPE(1),
.C_PROBE752_TYPE(1),
.C_PROBE753_TYPE(1),
.C_PROBE754_TYPE(1),
.C_PROBE755_TYPE(1),
.C_PROBE756_TYPE(1),
.C_PROBE757_TYPE(1),
.C_PROBE758_TYPE(1),
.C_PROBE759_TYPE(1),
.C_PROBE760_TYPE(1),
.C_PROBE761_TYPE(1),
.C_PROBE762_TYPE(1),
.C_PROBE763_TYPE(1),
.C_PROBE764_TYPE(1),
.C_PROBE765_TYPE(1),
.C_PROBE766_TYPE(1),
.C_PROBE767_TYPE(1),
.C_PROBE768_TYPE(1),
.C_PROBE769_TYPE(1),
.C_PROBE770_TYPE(1),
.C_PROBE771_TYPE(1),
.C_PROBE772_TYPE(1),
.C_PROBE773_TYPE(1),
.C_PROBE774_TYPE(1),
.C_PROBE775_TYPE(1),
.C_PROBE776_TYPE(1),
.C_PROBE777_TYPE(1),
.C_PROBE778_TYPE(1),
.C_PROBE779_TYPE(1),
.C_PROBE780_TYPE(1),
.C_PROBE781_TYPE(1),
.C_PROBE782_TYPE(1),
.C_PROBE783_TYPE(1),
.C_PROBE784_TYPE(1),
.C_PROBE785_TYPE(1),
.C_PROBE786_TYPE(1),
.C_PROBE787_TYPE(1),
.C_PROBE788_TYPE(1),
.C_PROBE789_TYPE(1),
.C_PROBE790_TYPE(1),
.C_PROBE791_TYPE(1),
.C_PROBE792_TYPE(1),
.C_PROBE793_TYPE(1),
.C_PROBE794_TYPE(1),
.C_PROBE795_TYPE(1),
.C_PROBE796_TYPE(1),
.C_PROBE797_TYPE(1),
.C_PROBE798_TYPE(1),
.C_PROBE799_TYPE(1),
.C_PROBE800_TYPE(1),
.C_PROBE801_TYPE(1),
.C_PROBE802_TYPE(1),
.C_PROBE803_TYPE(1),
.C_PROBE804_TYPE(1),
.C_PROBE805_TYPE(1),
.C_PROBE806_TYPE(1),
.C_PROBE807_TYPE(1),
.C_PROBE808_TYPE(1),
.C_PROBE809_TYPE(1),
.C_PROBE810_TYPE(1),
.C_PROBE811_TYPE(1),
.C_PROBE812_TYPE(1),
.C_PROBE813_TYPE(1),
.C_PROBE814_TYPE(1),
.C_PROBE815_TYPE(1),
.C_PROBE816_TYPE(1),
.C_PROBE817_TYPE(1),
.C_PROBE818_TYPE(1),
.C_PROBE819_TYPE(1),
.C_PROBE820_TYPE(1),
.C_PROBE821_TYPE(1),
.C_PROBE822_TYPE(1),
.C_PROBE823_TYPE(1),
.C_PROBE824_TYPE(1),
.C_PROBE825_TYPE(1),
.C_PROBE826_TYPE(1),
.C_PROBE827_TYPE(1),
.C_PROBE828_TYPE(1),
.C_PROBE829_TYPE(1),
.C_PROBE830_TYPE(1),
.C_PROBE831_TYPE(1),
.C_PROBE832_TYPE(1),
.C_PROBE833_TYPE(1),
.C_PROBE834_TYPE(1),
.C_PROBE835_TYPE(1),
.C_PROBE836_TYPE(1),
.C_PROBE837_TYPE(1),
.C_PROBE838_TYPE(1),
.C_PROBE839_TYPE(1),
.C_PROBE840_TYPE(1),
.C_PROBE841_TYPE(1),
.C_PROBE842_TYPE(1),
.C_PROBE843_TYPE(1),
.C_PROBE844_TYPE(1),
.C_PROBE845_TYPE(1),
.C_PROBE846_TYPE(1),
.C_PROBE847_TYPE(1),
.C_PROBE848_TYPE(1),
.C_PROBE849_TYPE(1),
.C_PROBE850_TYPE(1),
.C_PROBE851_TYPE(1),
.C_PROBE852_TYPE(1),
.C_PROBE853_TYPE(1),
.C_PROBE854_TYPE(1),
.C_PROBE855_TYPE(1),
.C_PROBE856_TYPE(1),
.C_PROBE857_TYPE(1),
.C_PROBE858_TYPE(1),
.C_PROBE859_TYPE(1),
.C_PROBE860_TYPE(1),
.C_PROBE861_TYPE(1),
.C_PROBE862_TYPE(1),
.C_PROBE863_TYPE(1),
.C_PROBE864_TYPE(1),
.C_PROBE865_TYPE(1),
.C_PROBE866_TYPE(1),
.C_PROBE867_TYPE(1),
.C_PROBE868_TYPE(1),
.C_PROBE869_TYPE(1),
.C_PROBE870_TYPE(1),
.C_PROBE871_TYPE(1),
.C_PROBE872_TYPE(1),
.C_PROBE873_TYPE(1),
.C_PROBE874_TYPE(1),
.C_PROBE875_TYPE(1),
.C_PROBE876_TYPE(1),
.C_PROBE877_TYPE(1),
.C_PROBE878_TYPE(1),
.C_PROBE879_TYPE(1),
.C_PROBE880_TYPE(1),
.C_PROBE881_TYPE(1),
.C_PROBE882_TYPE(1),
.C_PROBE883_TYPE(1),
.C_PROBE884_TYPE(1),
.C_PROBE885_TYPE(1),
.C_PROBE886_TYPE(1),
.C_PROBE887_TYPE(1),
.C_PROBE888_TYPE(1),
.C_PROBE889_TYPE(1),
.C_PROBE890_TYPE(1),
.C_PROBE891_TYPE(1),
.C_PROBE892_TYPE(1),
.C_PROBE893_TYPE(1),
.C_PROBE894_TYPE(1),
.C_PROBE895_TYPE(1),
.C_PROBE896_TYPE(1),
.C_PROBE897_TYPE(1),
.C_PROBE898_TYPE(1),
.C_PROBE899_TYPE(1),
.C_PROBE900_TYPE(1),
.C_PROBE901_TYPE(1),
.C_PROBE902_TYPE(1),
.C_PROBE903_TYPE(1),
.C_PROBE904_TYPE(1),
.C_PROBE905_TYPE(1),
.C_PROBE906_TYPE(1),
.C_PROBE907_TYPE(1),
.C_PROBE908_TYPE(1),
.C_PROBE909_TYPE(1),
.C_PROBE910_TYPE(1),
.C_PROBE911_TYPE(1),
.C_PROBE912_TYPE(1),
.C_PROBE913_TYPE(1),
.C_PROBE914_TYPE(1),
.C_PROBE915_TYPE(1),
.C_PROBE916_TYPE(1),
.C_PROBE917_TYPE(1),
.C_PROBE918_TYPE(1),
.C_PROBE919_TYPE(1),
.C_PROBE920_TYPE(1),
.C_PROBE921_TYPE(1),
.C_PROBE922_TYPE(1),
.C_PROBE923_TYPE(1),
.C_PROBE924_TYPE(1),
.C_PROBE925_TYPE(1),
.C_PROBE926_TYPE(1),
.C_PROBE927_TYPE(1),
.C_PROBE928_TYPE(1),
.C_PROBE929_TYPE(1),
.C_PROBE930_TYPE(1),
.C_PROBE931_TYPE(1),
.C_PROBE932_TYPE(1),
.C_PROBE933_TYPE(1),
.C_PROBE934_TYPE(1),
.C_PROBE935_TYPE(1),
.C_PROBE936_TYPE(1),
.C_PROBE937_TYPE(1),
.C_PROBE938_TYPE(1),
.C_PROBE939_TYPE(1),
.C_PROBE940_TYPE(1),
.C_PROBE941_TYPE(1),
.C_PROBE942_TYPE(1),
.C_PROBE943_TYPE(1),
.C_PROBE944_TYPE(1),
.C_PROBE945_TYPE(1),
.C_PROBE946_TYPE(1),
.C_PROBE947_TYPE(1),
.C_PROBE948_TYPE(1),
.C_PROBE949_TYPE(1),
.C_PROBE950_TYPE(1),
.C_PROBE951_TYPE(1),
.C_PROBE952_TYPE(1),
.C_PROBE953_TYPE(1),
.C_PROBE954_TYPE(1),
.C_PROBE955_TYPE(1),
.C_PROBE956_TYPE(1),
.C_PROBE957_TYPE(1),
.C_PROBE958_TYPE(1),
.C_PROBE959_TYPE(1),
.C_PROBE960_TYPE(1),
.C_PROBE961_TYPE(1),
.C_PROBE962_TYPE(1),
.C_PROBE963_TYPE(1),
.C_PROBE964_TYPE(1),
.C_PROBE965_TYPE(1),
.C_PROBE966_TYPE(1),
.C_PROBE967_TYPE(1),
.C_PROBE968_TYPE(1),
.C_PROBE969_TYPE(1),
.C_PROBE970_TYPE(1),
.C_PROBE971_TYPE(1),
.C_PROBE972_TYPE(1),
.C_PROBE973_TYPE(1),
.C_PROBE974_TYPE(1),
.C_PROBE975_TYPE(1),
.C_PROBE976_TYPE(1),
.C_PROBE977_TYPE(1),
.C_PROBE978_TYPE(1),
.C_PROBE979_TYPE(1),
.C_PROBE980_TYPE(1),
.C_PROBE981_TYPE(1),
.C_PROBE982_TYPE(1),
.C_PROBE983_TYPE(1),
.C_PROBE984_TYPE(1),
.C_PROBE985_TYPE(1),
.C_PROBE986_TYPE(1),
.C_PROBE987_TYPE(1),
.C_PROBE988_TYPE(1),
.C_PROBE989_TYPE(1),
.C_PROBE990_TYPE(1),
.C_PROBE991_TYPE(1),
.C_PROBE992_TYPE(1),
.C_PROBE993_TYPE(1),
.C_PROBE994_TYPE(1),
.C_PROBE995_TYPE(1),
.C_PROBE996_TYPE(1),
.C_PROBE997_TYPE(1),
.C_PROBE998_TYPE(1),
.C_PROBE999_TYPE(1),
.C_PROBE1000_TYPE(1),
.C_PROBE1001_TYPE(1),
.C_PROBE1002_TYPE(1),
.C_PROBE1003_TYPE(1),
.C_PROBE1004_TYPE(1),
.C_PROBE1005_TYPE(1),
.C_PROBE1006_TYPE(1),
.C_PROBE1007_TYPE(1),
.C_PROBE1008_TYPE(1),
.C_PROBE1009_TYPE(1),
.C_PROBE1010_TYPE(1),
.C_PROBE1011_TYPE(1),
.C_PROBE1012_TYPE(1),
.C_PROBE1013_TYPE(1),
.C_PROBE1014_TYPE(1),
.C_PROBE1015_TYPE(1),
.C_PROBE1016_TYPE(1),
.C_PROBE1017_TYPE(1),
.C_PROBE1018_TYPE(1),
.C_PROBE1019_TYPE(1),
.C_PROBE1020_TYPE(1),
.C_PROBE1021_TYPE(1),
.C_PROBE1022_TYPE(1),
.C_PROBE1023_TYPE(1)
) inst (
.clk(clk),
.sl_iport0(sl_iport0),
.sl_oport0(sl_oport0),
.probe0(probe0),
.probe1(probe1),
.probe2(probe2),
.probe3(probe3),
.probe4(probe4),
.probe5(probe5),
.probe6(probe6),
.probe7(probe7),
.probe8(probe8),
.probe9(probe9),
.probe10(probe10),
.probe11(probe11),
.probe12(probe12),
.probe13(probe13),
.probe14(probe14),
.probe15(probe15),
.probe16(probe16),
.probe17(probe17),
.probe18(probe18),
.probe19(probe19),
.probe20(probe20),
.probe21(0),
.probe22(0),
.probe23(0),
.probe24(0),
.probe25(0),
.probe26(0),
.probe27(0),
.probe28(0),
.probe29(0),
.probe30(0),
.probe31(0),
.probe32(0),
.probe33(0),
.probe34(0),
.probe35(0),
.probe36(0),
.probe37(0),
.probe38(0),
.probe39(0),
.probe40(0),
.probe41(0),
.probe42(0),
.probe43(0),
.probe44(0),
.probe45(0),
.probe46(0),
.probe47(0),
.probe48(0),
.probe49(0),
.probe50(0),
.probe51(0),
.probe52(0),
.probe53(0),
.probe54(0),
.probe55(0),
.probe56(0),
.probe57(0),
.probe58(0),
.probe59(0),
.probe60(0),
.probe61(0),
.probe62(0),
.probe63(0),
.probe64(0),
.probe65(0),
.probe66(0),
.probe67(0),
.probe68(0),
.probe69(0),
.probe70(0),
.probe71(0),
.probe72(0),
.probe73(0),
.probe74(0),
.probe75(0),
.probe76(0),
.probe77(0),
.probe78(0),
.probe79(0),
.probe80(0),
.probe81(0),
.probe82(0),
.probe83(0),
.probe84(0),
.probe85(0),
.probe86(0),
.probe87(0),
.probe88(0),
.probe89(0),
.probe90(0),
.probe91(0),
.probe92(0),
.probe93(0),
.probe94(0),
.probe95(0),
.probe96(0),
.probe97(0),
.probe98(0),
.probe99(0),
.probe100(0),
.probe101(0),
.probe102(0),
.probe103(0),
.probe104(0),
.probe105(0),
.probe106(0),
.probe107(0),
.probe108(0),
.probe109(0),
.probe110(0),
.probe111(0),
.probe112(0),
.probe113(0),
.probe114(0),
.probe115(0),
.probe116(0),
.probe117(0),
.probe118(0),
.probe119(0),
.probe120(0),
.probe121(0),
.probe122(0),
.probe123(0),
.probe124(0),
.probe125(0),
.probe126(0),
.probe127(0),
.probe128(0),
.probe129(0),
.probe130(0),
.probe131(0),
.probe132(0),
.probe133(0),
.probe134(0),
.probe135(0),
.probe136(0),
.probe137(0),
.probe138(0),
.probe139(0),
.probe140(0),
.probe141(0),
.probe142(0),
.probe143(0),
.probe144(0),
.probe145(0),
.probe146(0),
.probe147(0),
.probe148(0),
.probe149(0),
.probe150(0),
.probe151(0),
.probe152(0),
.probe153(0),
.probe154(0),
.probe155(0),
.probe156(0),
.probe157(0),
.probe158(0),
.probe159(0),
.probe160(0),
.probe161(0),
.probe162(0),
.probe163(0),
.probe164(0),
.probe165(0),
.probe166(0),
.probe167(0),
.probe168(0),
.probe169(0),
.probe170(0),
.probe171(0),
.probe172(0),
.probe173(0),
.probe174(0),
.probe175(0),
.probe176(0),
.probe177(0),
.probe178(0),
.probe179(0),
.probe180(0),
.probe181(0),
.probe182(0),
.probe183(0),
.probe184(0),
.probe185(0),
.probe186(0),
.probe187(0),
.probe188(0),
.probe189(0),
.probe190(0),
.probe191(0),
.probe192(0),
.probe193(0),
.probe194(0),
.probe195(0),
.probe196(0),
.probe197(0),
.probe198(0),
.probe199(0),
.probe200(0),
.probe201(0),
.probe202(0),
.probe203(0),
.probe204(0),
.probe205(0),
.probe206(0),
.probe207(0),
.probe208(0),
.probe209(0),
.probe210(0),
.probe211(0),
.probe212(0),
.probe213(0),
.probe214(0),
.probe215(0),
.probe216(0),
.probe217(0),
.probe218(0),
.probe219(0),
.probe220(0),
.probe221(0),
.probe222(0),
.probe223(0),
.probe224(0),
.probe225(0),
.probe226(0),
.probe227(0),
.probe228(0),
.probe229(0),
.probe230(0),
.probe231(0),
.probe232(0),
.probe233(0),
.probe234(0),
.probe235(0),
.probe236(0),
.probe237(0),
.probe238(0),
.probe239(0),
.probe240(0),
.probe241(0),
.probe242(0),
.probe243(0),
.probe244(0),
.probe245(0),
.probe246(0),
.probe247(0),
.probe248(0),
.probe249(0),
.probe250(0),
.probe251(0),
.probe252(0),
.probe253(0),
.probe254(0),
.probe255(0),
.probe256(0),
.probe257(0),
.probe258(0),
.probe259(0),
.probe260(0),
.probe261(0),
.probe262(0),
.probe263(0),
.probe264(0),
.probe265(0),
.probe266(0),
.probe267(0),
.probe268(0),
.probe269(0),
.probe270(0),
.probe271(0),
.probe272(0),
.probe273(0),
.probe274(0),
.probe275(0),
.probe276(0),
.probe277(0),
.probe278(0),
.probe279(0),
.probe280(0),
.probe281(0),
.probe282(0),
.probe283(0),
.probe284(0),
.probe285(0),
.probe286(0),
.probe287(0),
.probe288(0),
.probe289(0),
.probe290(0),
.probe291(0),
.probe292(0),
.probe293(0),
.probe294(0),
.probe295(0),
.probe296(0),
.probe297(0),
.probe298(0),
.probe299(0),
.probe300(0),
.probe301(0),
.probe302(0),
.probe303(0),
.probe304(0),
.probe305(0),
.probe306(0),
.probe307(0),
.probe308(0),
.probe309(0),
.probe310(0),
.probe311(0),
.probe312(0),
.probe313(0),
.probe314(0),
.probe315(0),
.probe316(0),
.probe317(0),
.probe318(0),
.probe319(0),
.probe320(0),
.probe321(0),
.probe322(0),
.probe323(0),
.probe324(0),
.probe325(0),
.probe326(0),
.probe327(0),
.probe328(0),
.probe329(0),
.probe330(0),
.probe331(0),
.probe332(0),
.probe333(0),
.probe334(0),
.probe335(0),
.probe336(0),
.probe337(0),
.probe338(0),
.probe339(0),
.probe340(0),
.probe341(0),
.probe342(0),
.probe343(0),
.probe344(0),
.probe345(0),
.probe346(0),
.probe347(0),
.probe348(0),
.probe349(0),
.probe350(0),
.probe351(0),
.probe352(0),
.probe353(0),
.probe354(0),
.probe355(0),
.probe356(0),
.probe357(0),
.probe358(0),
.probe359(0),
.probe360(0),
.probe361(0),
.probe362(0),
.probe363(0),
.probe364(0),
.probe365(0),
.probe366(0),
.probe367(0),
.probe368(0),
.probe369(0),
.probe370(0),
.probe371(0),
.probe372(0),
.probe373(0),
.probe374(0),
.probe375(0),
.probe376(0),
.probe377(0),
.probe378(0),
.probe379(0),
.probe380(0),
.probe381(0),
.probe382(0),
.probe383(0),
.probe384(0),
.probe385(0),
.probe386(0),
.probe387(0),
.probe388(0),
.probe389(0),
.probe390(0),
.probe391(0),
.probe392(0),
.probe393(0),
.probe394(0),
.probe395(0),
.probe396(0),
.probe397(0),
.probe398(0),
.probe399(0),
.probe400(0),
.probe401(0),
.probe402(0),
.probe403(0),
.probe404(0),
.probe405(0),
.probe406(0),
.probe407(0),
.probe408(0),
.probe409(0),
.probe410(0),
.probe411(0),
.probe412(0),
.probe413(0),
.probe414(0),
.probe415(0),
.probe416(0),
.probe417(0),
.probe418(0),
.probe419(0),
.probe420(0),
.probe421(0),
.probe422(0),
.probe423(0),
.probe424(0),
.probe425(0),
.probe426(0),
.probe427(0),
.probe428(0),
.probe429(0),
.probe430(0),
.probe431(0),
.probe432(0),
.probe433(0),
.probe434(0),
.probe435(0),
.probe436(0),
.probe437(0),
.probe438(0),
.probe439(0),
.probe440(0),
.probe441(0),
.probe442(0),
.probe443(0),
.probe444(0),
.probe445(0),
.probe446(0),
.probe447(0),
.probe448(0),
.probe449(0),
.probe450(0),
.probe451(0),
.probe452(0),
.probe453(0),
.probe454(0),
.probe455(0),
.probe456(0),
.probe457(0),
.probe458(0),
.probe459(0),
.probe460(0),
.probe461(0),
.probe462(0),
.probe463(0),
.probe464(0),
.probe465(0),
.probe466(0),
.probe467(0),
.probe468(0),
.probe469(0),
.probe470(0),
.probe471(0),
.probe472(0),
.probe473(0),
.probe474(0),
.probe475(0),
.probe476(0),
.probe477(0),
.probe478(0),
.probe479(0),
.probe480(0),
.probe481(0),
.probe482(0),
.probe483(0),
.probe484(0),
.probe485(0),
.probe486(0),
.probe487(0),
.probe488(0),
.probe489(0),
.probe490(0),
.probe491(0),
.probe492(0),
.probe493(0),
.probe494(0),
.probe495(0),
.probe496(0),
.probe497(0),
.probe498(0),
.probe499(0),
.probe500(0),
.probe501(0),
.probe502(0),
.probe503(0),
.probe504(0),
.probe505(0),
.probe506(0),
.probe507(0),
.probe508(0),
.probe509(0),
.probe510(0),
.probe511(0),
.probe512(0),
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)/* synthesis syn_noprune=1 */;
endmodule
|
module sky130_fd_sc_hs__o21bai (
Y ,
A1 ,
A2 ,
B1_N,
VPWR,
VGND
);
output Y ;
input A1 ;
input A2 ;
input B1_N;
input VPWR;
input VGND;
endmodule
|
module rcswitch_test;
reg [39:0] addr;
reg [39:0] chan;
reg [15:0] stat;
reg send;
initial begin
#0 addr = 40'b10001000_10001000_10001000_10001000_10001000; // 11111
#0 chan = 40'b10001000_10001110_10001110_10001110_10001110; // 0FFFF = A
#0 stat = 16'b10001110_10001000; // F0 = ON
#2 send = 1;
#100 send = 0;
#300 $finish;
end
// clock
reg clk = 0;
always #1 clk = !clk;
wire ready;
wire out;
rcswitch_send rcswitch_send_inst (
.clk(clk),
.rst(1'b0),
.send(send),
.addr(addr),
.chan(chan),
.stat(stat),
.ready(ready),
.out(out)
);
initial
begin
$dumpfile("rcswitch_send.vcd");
$dumpvars(0, rcswitch_send_inst);
end
endmodule
|
module mcu_cmd(
input clk,
input cmd_ready,
input param_ready,
input [7:0] cmd_data,
input [7:0] param_data,
output [2:0] mcu_mapper,
output reg mcu_rrq = 0,
output mcu_write,
output reg mcu_wrq = 0,
input mcu_rq_rdy,
output [7:0] mcu_data_out,
input [7:0] mcu_data_in,
output [7:0] spi_data_out,
input [31:0] spi_byte_cnt,
input [2:0] spi_bit_cnt,
output [23:0] addr_out,
output [23:0] saveram_mask_out,
output [23:0] rom_mask_out,
// SD "DMA" extension
output SD_DMA_EN,
input SD_DMA_STATUS,
input SD_DMA_NEXTADDR,
input [7:0] SD_DMA_SRAM_DATA,
input SD_DMA_SRAM_WE,
output [1:0] SD_DMA_TGT,
output SD_DMA_PARTIAL,
output [10:0] SD_DMA_PARTIAL_START,
output [10:0] SD_DMA_PARTIAL_END,
output reg SD_DMA_START_MID_BLOCK,
output reg SD_DMA_END_MID_BLOCK,
// DAC
output [10:0] dac_addr_out,
input DAC_STATUS,
output reg dac_play_out = 0,
output reg dac_reset_out = 0,
output reg [2:0] dac_vol_select_out = 3'b000,
output reg dac_palmode_out = 0,
output reg [8:0] dac_ptr_out = 0,
// MSU data
output [13:0] msu_addr_out,
input [7:0] MSU_STATUS,
output [5:0] msu_status_reset_out,
output [5:0] msu_status_set_out,
output msu_status_reset_we,
input [31:0] msu_addressrq,
input [15:0] msu_trackrq,
input [7:0] msu_volumerq,
output [13:0] msu_ptr_out,
output msu_reset_out,
// BS-X
output [7:0] bsx_regs_reset_out,
output [7:0] bsx_regs_set_out,
output bsx_regs_reset_we,
// generic RTC
output [55:0] rtc_data_out,
output rtc_pgm_we,
// S-RTC
output srtc_reset,
// uPD77C25
output reg [23:0] dspx_pgm_data_out,
output reg [10:0] dspx_pgm_addr_out,
output reg dspx_pgm_we_out,
output reg [15:0] dspx_dat_data_out,
output reg [10:0] dspx_dat_addr_out,
output reg dspx_dat_we_out,
output reg dspx_reset_out,
// feature enable
output reg [7:0] featurebits_out,
output reg region_out,
// SNES sync/clk
input snes_sysclk,
// snes cmd interface
input [7:0] snescmd_data_in,
output reg [7:0] snescmd_data_out,
output reg [8:0] snescmd_addr_out,
output reg snescmd_we_out,
// cheat configuration
output reg [7:0] cheat_pgm_idx_out,
output reg [31:0] cheat_pgm_data_out,
output reg cheat_pgm_we_out,
// DSP core features
output reg [15:0] dsp_feat_out = 16'h0000
);
initial begin
dspx_pgm_addr_out = 11'b00000000000;
dspx_dat_addr_out = 10'b0000000000;
dspx_reset_out = 1'b1;
region_out = 0;
SD_DMA_START_MID_BLOCK = 0;
SD_DMA_END_MID_BLOCK = 0;
end
wire [31:0] snes_sysclk_freq;
clk_test snes_clk_test (
.clk(clk),
.sysclk(snes_sysclk),
.snes_sysclk_freq(snes_sysclk_freq)
);
reg [2:0] MAPPER_BUF;
reg [23:0] ADDR_OUT_BUF;
reg [10:0] DAC_ADDR_OUT_BUF;
reg [7:0] DAC_VOL_OUT_BUF;
reg [13:0] MSU_ADDR_OUT_BUF;
reg [13:0] MSU_PTR_OUT_BUF;
reg [5:0] msu_status_set_out_buf;
reg [5:0] msu_status_reset_out_buf;
reg msu_status_reset_we_buf = 0;
reg MSU_RESET_OUT_BUF;
reg [7:0] bsx_regs_set_out_buf;
reg [7:0] bsx_regs_reset_out_buf;
reg bsx_regs_reset_we_buf;
reg [55:0] rtc_data_out_buf;
reg rtc_pgm_we_buf;
reg srtc_reset_buf;
initial srtc_reset_buf = 0;
reg [31:0] SNES_SYSCLK_FREQ_BUF;
reg [7:0] MCU_DATA_OUT_BUF;
reg [7:0] MCU_DATA_IN_BUF;
reg [2:0] mcu_nextaddr_buf;
reg [7:0] dsp_feat_tmp;
wire mcu_nextaddr;
reg DAC_STATUSr;
reg SD_DMA_STATUSr;
reg [7:0] MSU_STATUSr;
always @(posedge clk) begin
DAC_STATUSr <= DAC_STATUS;
SD_DMA_STATUSr <= SD_DMA_STATUS;
MSU_STATUSr <= MSU_STATUS;
end
reg SD_DMA_PARTIALr;
assign SD_DMA_PARTIAL = SD_DMA_PARTIALr;
reg SD_DMA_ENr;
assign SD_DMA_EN = SD_DMA_ENr;
reg [1:0] SD_DMA_TGTr;
assign SD_DMA_TGT = SD_DMA_TGTr;
reg [10:0] SD_DMA_PARTIAL_STARTr;
reg [10:0] SD_DMA_PARTIAL_ENDr;
assign SD_DMA_PARTIAL_START = SD_DMA_PARTIAL_STARTr;
assign SD_DMA_PARTIAL_END = SD_DMA_PARTIAL_ENDr;
reg [23:0] SAVERAM_MASK;
reg [23:0] ROM_MASK;
assign spi_data_out = MCU_DATA_IN_BUF;
initial begin
ADDR_OUT_BUF = 0;
DAC_ADDR_OUT_BUF = 0;
MSU_ADDR_OUT_BUF = 0;
SD_DMA_ENr = 0;
MAPPER_BUF = 1;
SD_DMA_PARTIALr = 0;
end
// command interpretation
always @(posedge clk) begin
snescmd_we_out <= 1'b0;
cheat_pgm_we_out <= 1'b0;
dac_reset_out <= 1'b0;
MSU_RESET_OUT_BUF <= 1'b0;
if (cmd_ready) begin
case (cmd_data[7:4])
4'h3: // select mapper
MAPPER_BUF <= cmd_data[2:0];
4'h4: begin// SD DMA
SD_DMA_ENr <= 1;
SD_DMA_TGTr <= cmd_data[1:0];
SD_DMA_PARTIALr <= cmd_data[2];
end
4'h8: SD_DMA_TGTr <= 2'b00;
4'h9: SD_DMA_TGTr <= 2'b00; // cmd_data[1:0]; // not implemented
// 4'hE:
// select memory unit
endcase
end else if (param_ready) begin
casex (cmd_data[7:0])
8'h1x:
case (spi_byte_cnt)
32'h2:
ROM_MASK[23:16] <= param_data;
32'h3:
ROM_MASK[15:8] <= param_data;
32'h4:
ROM_MASK[7:0] <= param_data;
endcase
8'h2x:
case (spi_byte_cnt)
32'h2:
SAVERAM_MASK[23:16] <= param_data;
32'h3:
SAVERAM_MASK[15:8] <= param_data;
32'h4:
SAVERAM_MASK[7:0] <= param_data;
endcase
8'h4x:
SD_DMA_ENr <= 1'b0;
8'h6x:
case (spi_byte_cnt)
32'h2: begin
SD_DMA_START_MID_BLOCK <= param_data[7];
SD_DMA_PARTIAL_STARTr[10:9] <= param_data[1:0];
end
32'h3:
SD_DMA_PARTIAL_STARTr[8:0] <= {param_data, 1'b0};
32'h4: begin
SD_DMA_END_MID_BLOCK <= param_data[7];
SD_DMA_PARTIAL_ENDr[10:9] <= param_data[1:0];
end
32'h5:
SD_DMA_PARTIAL_ENDr[8:0] <= {param_data, 1'b0};
endcase
8'h9x:
MCU_DATA_OUT_BUF <= param_data;
8'hd0:
case (spi_byte_cnt)
32'h2:
snescmd_addr_out[7:0] <= param_data;
32'h3:
snescmd_addr_out[8] <= param_data[0];
endcase
8'hd1:
snescmd_addr_out <= snescmd_addr_out + 1;
8'hd2: begin
case (spi_byte_cnt)
32'h2:
snescmd_we_out <= 1'b1;
32'h3:
snescmd_addr_out <= snescmd_addr_out + 1;
endcase
snescmd_data_out <= param_data;
end
8'hd3: begin
case (spi_byte_cnt)
32'h2:
cheat_pgm_idx_out <= param_data[2:0];
32'h3:
cheat_pgm_data_out[31:24] <= param_data;
32'h4:
cheat_pgm_data_out[23:16] <= param_data;
32'h5:
cheat_pgm_data_out[15:8] <= param_data;
32'h6: begin
cheat_pgm_data_out[7:0] <= param_data;
cheat_pgm_we_out <= 1'b1;
end
endcase
end
8'he0:
case (spi_byte_cnt)
32'h2: begin
msu_status_set_out_buf <= param_data[5:0];
end
32'h3: begin
msu_status_reset_out_buf <= param_data[5:0];
msu_status_reset_we_buf <= 1'b1;
end
32'h4:
msu_status_reset_we_buf <= 1'b0;
endcase
8'he1: // pause DAC
dac_play_out <= 1'b0;
8'he2: // resume DAC
dac_play_out <= 1'b1;
8'he3: // reset DAC (set DAC playback address = 0)
case (spi_byte_cnt)
32'h2:
dac_ptr_out[8] <= param_data[0];
32'h3: begin
dac_ptr_out[7:0] <= param_data;
dac_reset_out <= 1'b1; // reset by default value, see above
end
endcase
8'he4: // reset MSU read buffer pointer
case (spi_byte_cnt)
32'h2: begin
MSU_PTR_OUT_BUF[13:8] <= param_data[5:0];
MSU_PTR_OUT_BUF[7:0] <= 8'h0;
end
32'h3: begin
MSU_PTR_OUT_BUF[7:0] <= param_data;
MSU_RESET_OUT_BUF <= 1'b1;
end
endcase
8'he5:
case (spi_byte_cnt)
32'h2:
rtc_data_out_buf[55:48] <= param_data;
32'h3:
rtc_data_out_buf[47:40] <= param_data;
32'h4:
rtc_data_out_buf[39:32] <= param_data;
32'h5:
rtc_data_out_buf[31:24] <= param_data;
32'h6:
rtc_data_out_buf[23:16] <= param_data;
32'h7:
rtc_data_out_buf[15:8] <= param_data;
32'h8: begin
rtc_data_out_buf[7:0] <= param_data;
rtc_pgm_we_buf <= 1'b1;
end
32'h9:
rtc_pgm_we_buf <= 1'b0;
endcase
8'he6:
case (spi_byte_cnt)
32'h2: begin
bsx_regs_set_out_buf <= param_data[7:0];
end
32'h3: begin
bsx_regs_reset_out_buf <= param_data[7:0];
bsx_regs_reset_we_buf <= 1'b1;
end
32'h4:
bsx_regs_reset_we_buf <= 1'b0;
endcase
8'he7:
case (spi_byte_cnt)
32'h2: begin
srtc_reset_buf <= 1'b1;
end
32'h3: begin
srtc_reset_buf <= 1'b0;
end
endcase
8'he8: begin// reset DSPx PGM+DAT address
case (spi_byte_cnt)
32'h2: begin
dspx_pgm_addr_out <= 11'b00000000000;
dspx_dat_addr_out <= 10'b0000000000;
end
endcase
end
8'he9:// write DSPx PGM w/ increment
case (spi_byte_cnt)
32'h2: dspx_pgm_data_out[23:16] <= param_data[7:0];
32'h3: dspx_pgm_data_out[15:8] <= param_data[7:0];
32'h4: dspx_pgm_data_out[7:0] <= param_data[7:0];
32'h5: dspx_pgm_we_out <= 1'b1;
32'h6: begin
dspx_pgm_we_out <= 1'b0;
dspx_pgm_addr_out <= dspx_pgm_addr_out + 1;
end
endcase
8'hea:// write DSPx DAT w/ increment
case (spi_byte_cnt)
32'h2: dspx_dat_data_out[15:8] <= param_data[7:0];
32'h3: dspx_dat_data_out[7:0] <= param_data[7:0];
32'h4: dspx_dat_we_out <= 1'b1;
32'h5: begin
dspx_dat_we_out <= 1'b0;
dspx_dat_addr_out <= dspx_dat_addr_out + 1;
end
endcase
8'heb: // control DSPx reset
dspx_reset_out <= param_data[0];
8'hec:
begin // set DAC properties
dac_vol_select_out <= param_data[2:0];
dac_palmode_out <= param_data[7];
end
8'hed:
featurebits_out <= param_data;
8'hee:
region_out <= param_data[0];
8'hef:
case (spi_byte_cnt)
32'h2: dsp_feat_tmp <= param_data[7:0];
32'h3: begin
dsp_feat_out <= {dsp_feat_tmp, param_data[7:0]};
end
endcase
endcase
end
end
always @(posedge clk) begin
if(param_ready && cmd_data[7:4] == 4'h0) begin
case (cmd_data[1:0])
2'b01: begin
case (spi_byte_cnt)
32'h2: begin
DAC_ADDR_OUT_BUF[10:8] <= param_data[2:0];
DAC_ADDR_OUT_BUF[7:0] <= 8'b0;
end
32'h3:
DAC_ADDR_OUT_BUF[7:0] <= param_data;
endcase
end
2'b10: begin
case (spi_byte_cnt)
32'h2: begin
MSU_ADDR_OUT_BUF[13:8] <= param_data[5:0];
MSU_ADDR_OUT_BUF[7:0] <= 8'b0;
end
32'h3:
MSU_ADDR_OUT_BUF[7:0] <= param_data;
endcase
end
default:
case (spi_byte_cnt)
32'h2: begin
ADDR_OUT_BUF[23:16] <= param_data;
ADDR_OUT_BUF[15:0] <= 16'b0;
end
32'h3:
ADDR_OUT_BUF[15:8] <= param_data;
32'h4:
ADDR_OUT_BUF[7:0] <= param_data;
endcase
endcase
end else if (SD_DMA_NEXTADDR | (mcu_nextaddr & (cmd_data[7:5] == 3'h4)
&& (cmd_data[3])
&& (spi_byte_cnt >= (32'h1+cmd_data[4])))
) begin
case (SD_DMA_TGTr)
2'b00: ADDR_OUT_BUF <= ADDR_OUT_BUF + 1;
2'b01: DAC_ADDR_OUT_BUF <= DAC_ADDR_OUT_BUF + 1;
2'b10: MSU_ADDR_OUT_BUF <= MSU_ADDR_OUT_BUF + 1;
endcase
end
end
// value fetch during last SPI bit
always @(posedge clk) begin
if (cmd_data[7:4] == 4'h8 && mcu_nextaddr)
MCU_DATA_IN_BUF <= mcu_data_in;
else if (cmd_ready | param_ready /* bit_cnt == 7 */) begin
if (cmd_data[7:4] == 4'hA)
MCU_DATA_IN_BUF <= snescmd_data_in;
if (cmd_data[7:0] == 8'hF0)
MCU_DATA_IN_BUF <= 8'hA5;
else if (cmd_data[7:0] == 8'hF1)
case (spi_byte_cnt[0])
1'b1: // buffer status (1st byte)
MCU_DATA_IN_BUF <= {SD_DMA_STATUSr, DAC_STATUSr, MSU_STATUSr[7], 5'b0};
1'b0: // control status (2nd byte)
MCU_DATA_IN_BUF <= {1'b0, MSU_STATUSr[6:0]};
endcase
else if (cmd_data[7:0] == 8'hF2)
case (spi_byte_cnt)
32'h1:
MCU_DATA_IN_BUF <= msu_addressrq[31:24];
32'h2:
MCU_DATA_IN_BUF <= msu_addressrq[23:16];
32'h3:
MCU_DATA_IN_BUF <= msu_addressrq[15:8];
32'h4:
MCU_DATA_IN_BUF <= msu_addressrq[7:0];
endcase
else if (cmd_data[7:0] == 8'hF3)
case (spi_byte_cnt)
32'h1:
MCU_DATA_IN_BUF <= msu_trackrq[15:8];
32'h2:
MCU_DATA_IN_BUF <= msu_trackrq[7:0];
endcase
else if (cmd_data[7:0] == 8'hF4)
MCU_DATA_IN_BUF <= msu_volumerq;
else if (cmd_data[7:0] == 8'hFE)
case (spi_byte_cnt)
32'h1:
SNES_SYSCLK_FREQ_BUF <= snes_sysclk_freq;
32'h2:
MCU_DATA_IN_BUF <= SNES_SYSCLK_FREQ_BUF[31:24];
32'h3:
MCU_DATA_IN_BUF <= SNES_SYSCLK_FREQ_BUF[23:16];
32'h4:
MCU_DATA_IN_BUF <= SNES_SYSCLK_FREQ_BUF[15:8];
32'h5:
MCU_DATA_IN_BUF <= SNES_SYSCLK_FREQ_BUF[7:0];
endcase
else if (cmd_data[7:0] == 8'hFF)
MCU_DATA_IN_BUF <= param_data;
else if (cmd_data[7:0] == 8'hD1)
MCU_DATA_IN_BUF <= snescmd_data_in;
end
end
// nextaddr pulse generation
always @(posedge clk) begin
mcu_nextaddr_buf <= {mcu_nextaddr_buf[1:0], mcu_rq_rdy};
end
always @(posedge clk) begin
mcu_rrq <= 1'b0;
if((param_ready | cmd_ready) && cmd_data[7:4] == 4'h8) begin
mcu_rrq <= 1'b1;
end
end
always @(posedge clk) begin
mcu_wrq <= 1'b0;
if(param_ready && cmd_data[7:4] == 4'h9) begin
mcu_wrq <= 1'b1;
end
end
// trigger for nextaddr
assign mcu_nextaddr = mcu_nextaddr_buf == 2'b01;
assign mcu_write = SD_DMA_STATUS
?(SD_DMA_TGTr == 2'b00
? SD_DMA_SRAM_WE
: 1'b1
)
: 1'b1;
assign addr_out = ADDR_OUT_BUF;
assign dac_addr_out = DAC_ADDR_OUT_BUF;
assign msu_addr_out = MSU_ADDR_OUT_BUF;
assign msu_status_reset_we = msu_status_reset_we_buf;
assign msu_status_reset_out = msu_status_reset_out_buf;
assign msu_status_set_out = msu_status_set_out_buf;
assign msu_reset_out = MSU_RESET_OUT_BUF;
assign msu_ptr_out = MSU_PTR_OUT_BUF;
assign bsx_regs_reset_we = bsx_regs_reset_we_buf;
assign bsx_regs_reset_out = bsx_regs_reset_out_buf;
assign bsx_regs_set_out = bsx_regs_set_out_buf;
assign rtc_data_out = rtc_data_out_buf;
assign rtc_pgm_we = rtc_pgm_we_buf;
assign srtc_reset = srtc_reset_buf;
assign mcu_data_out = SD_DMA_STATUS ? SD_DMA_SRAM_DATA : MCU_DATA_OUT_BUF;
assign mcu_mapper = MAPPER_BUF;
assign rom_mask_out = ROM_MASK;
assign saveram_mask_out = SAVERAM_MASK;
assign DBG_mcu_nextaddr = mcu_nextaddr;
endmodule
|
module sky130_fd_sc_ms__clkdlyinv3sd3 (
Y ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire not0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
not not0 (not0_out_Y , A );
sky130_fd_sc_ms__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, not0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
|
module trim_dac_ctrl (
input clk40,
input rst,
input [6:0] lut_in,
input [4:0] lut_addr,
input lut_we,
input load_dacs,
output serial_out,
output clk_out,
output enable_out
);
/*input clk40;
input rst;
input [6:0] lut_in;
input [4:0] lut_addr;
input lut_we;
input load_dacs;
output serial_out;
output clk_out;
output enable_out;
*/
// Instantiate LUT
wire [13:0] lut_out;
reg [3:0] lut_out_addr;
dp_lut_7x5_14x4 trim_lut (
.clk(clk40),
.din_a(lut_in),
.we_a(lut_we),
.addr_a(lut_addr),
.dout_b(lut_out),
.addr_b(lut_out_addr)
);
reg clk20A, clk20B;
// Instantiate the 3 shift registers
reg [3:0] dac_addr;
reg shift_en;
reg shreg1_ld_en, shreg2_ld_en, shreg3_ld_en;
wire [31:0] shreg_pin;
wire shreg1_out, shreg2_out;
shift_reg_32 shreg1(
.clk(clk20A),
.p_load(shreg1_ld_en),
.p_data(shreg_pin),
.s_in(1'b0),
.s_out(shreg1_out),
.shift_en(shift_en)
);
shift_reg_32 shreg2(
.clk(clk20A),
.p_load(shreg2_ld_en),
.p_data(shreg_pin),
.s_in(shreg1_out),
.s_out(shreg2_out),
.shift_en(shift_en)
);
shift_reg_32 shreg3(
.clk(clk20A),
.p_load(shreg3_ld_en),
.p_data(shreg_pin),
.s_in(shreg2_out),
.s_out(serial_out),
.shift_en(shift_en)
);
// Form shift reg parallel input
assign shreg_pin = {8'b0, 4'b0011, dac_addr, lut_out[11:0], 4'b0};
// Assign DAC chip clock. 180 deg. phase shift so rising edge is in the middle
// of serial out data bits. Only output when DAC chips enabled
reg clk_mask;
assign clk_out = (clk_mask & ~clk20A);
// The DAC chip enable is active low. Require it to stay active one cycle longer
// than the shift enable, and also activate one earlier, so use extra cycle regs
reg early_cycle, late_cycle;
assign enable_out = ~(shift_en | early_cycle | late_cycle);
//Divide te 40MHz and generate two clocks in quadrature
//One phase A clock shregs and, inverted, clocks DAC chips
//Other phase generates enables to avoid edge transitions
always @(posedge clk40) begin
if (rst) begin
clk20A <= 0;
end else begin
clk20A <= ~clk20A;
end
end
always @(negedge clk40) begin
if (rst) begin
clk20B <= 0;
end else begin
clk20B <= ~clk20B;
end
end
// Create mask to stop DAC chip clock
always @(posedge clk20A) begin
if (rst) begin
clk_mask <= 0;
end else begin
if (shift_en | early_cycle) begin
clk_mask <= 1;
end else begin
clk_mask <= 0;
end
end
end
// Extend synchronous trigger in order to ensure the divided clock spots it
reg trig_a, trig_b;
wire long_trig;
always @(posedge clk40) begin
trig_a <= load_dacs;
trig_b <= trig_a;
end
assign long_trig = trig_a | trig_b;
// Wait for load_dacs synchronous trigger, then begin to step through a state machine
// The machine first loads the 3 shregs with DAC A values for each chip, i.e channels
// 1, 4 & 7
reg [8:0] state_count;
always @(negedge clk20B) begin
if (rst) begin
shift_en <= 0;
state_count <= 0;
shreg1_ld_en <= 0;
shreg2_ld_en <= 0;
shreg3_ld_en <= 0;
early_cycle <= 0;
late_cycle <= 0;
end else begin
early_cycle <= 0;
late_cycle <= 0;
if (long_trig) begin
//Start state machine
state_count <= 9'd1;
end else begin
state_count <= state_count + 1;
case (state_count)
9'd0: state_count <= 0;
9'd1: begin
//Specify address of dac A for all chips
dac_addr <= 4'b0000;
//Load shreg1 with ch7 dac code
lut_out_addr <= 4'd0;
shreg1_ld_en <= 1;
end
9'd2: begin
//Load shreg2 with ch4 dac code
shreg1_ld_en <= 0;
lut_out_addr <= 4'd1;
shreg2_ld_en <= 1;
end
9'd3: begin
//Load shreg3 with ch1 dac code
shreg2_ld_en <= 0;
lut_out_addr <= 4'd2;
shreg3_ld_en <= 1;
end
9'd4: begin
//shregs loaded
shreg3_ld_en <= 0;
//Begin enabling DAC chips
early_cycle <= 1;
end
9'd5: begin
//Enable shift register data to be shifted out onto DAC chips
shift_en <= 1;
end
9'd100: begin
//All data shifted out of shregs onto DAC chips
shift_en <= 0; // [updates dacs]
late_cycle <= 1;
end
9'd101: begin
//Specify address of dac B for all chips
dac_addr <= 4'b0001;
//Load shreg1 with ch8 dac code
lut_out_addr <= 4'd3;
shreg1_ld_en <= 1;
end
9'd102: begin
//Load shreg2 with ch5 dac code
shreg1_ld_en <= 0;
lut_out_addr <= 4'd4;
shreg2_ld_en <= 1;
end
9'd103: begin
//Load shreg3 with ch2 dac code
shreg2_ld_en <= 0;
lut_out_addr <= 4'd5;
shreg3_ld_en <= 1;
end
9'd104: begin
//shregs loaded
shreg3_ld_en <= 0;
//Begin enabling DAC chips
early_cycle <= 1;
end
9'd105: begin
//Enable shift register data to be shifted out onto DAC chips
shift_en <= 1;
end
9'd200: begin
//All data shifted out of shregs onto DAC chips
shift_en <= 0; // [updates dacs]
late_cycle <= 1;
end
9'd201: begin
//Specify address of dac C for all chips
dac_addr <= 4'b0010;
//Load shreg1 with ch9 dac code
lut_out_addr <= 4'd6;
shreg1_ld_en <= 1;
end
9'd202: begin
//Load shreg2 with ch6 dac code
shreg1_ld_en <= 0;
lut_out_addr <= 4'd7;
shreg2_ld_en <= 1;
end
9'd203: begin
//Load shreg3 with ch3 dac code
shreg2_ld_en <= 0;
lut_out_addr <= 4'd8;
shreg3_ld_en <= 1;
end
9'd204: begin
//shregs loaded
shreg3_ld_en <= 0;
//Begin enabling DAC chips
early_cycle <= 1;
end
9'd205: begin
//Enable shift register data to be shifted out onto DAC chips
shift_en <= 1;
end
9'd300: begin
//All data shifted out of shregs onto DAC chips
shift_en <= 0; // [updates dacs]
late_cycle <= 1;
state_count <= 0;
end
endcase
end
end
end
endmodule
|
module dp_lut_7x5_14x4 (
clk,
din_a,
we_a,
addr_a,
dout_b,
addr_b
);
input clk;
input we_a;
input [4:0] addr_a;
input [6:0] din_a;
input [3:0] addr_b;
output [13:0] dout_b;
reg [6:0] lut [0:31];
//Write routine
always @(posedge clk) begin
if (we_a) begin
lut[addr_a] <= din_a;
end
end
//Output
assign dout_b = {lut[2*addr_b + 1], lut[2*addr_b]};
endmodule
|
module shift_reg_32 (
clk,
p_load,
p_data,
s_in,
s_out,
shift_en
);
input clk;
input s_in;
input p_load;
input [31:0] p_data;
input shift_en;
output s_out;
reg [31:0] shreg;
always @(posedge clk) begin
if (p_load) begin
shreg = p_data;
end else begin
if (shift_en) begin
shreg = {shreg[30:0], s_in};
end
end
end
assign s_out = shreg[31];
endmodule
|
module system_acl_iface_mm_interconnect_0 (
input wire [11:0] hps_h2f_lw_axi_master_awid, // hps_h2f_lw_axi_master.awid
input wire [20:0] hps_h2f_lw_axi_master_awaddr, // .awaddr
input wire [3:0] hps_h2f_lw_axi_master_awlen, // .awlen
input wire [2:0] hps_h2f_lw_axi_master_awsize, // .awsize
input wire [1:0] hps_h2f_lw_axi_master_awburst, // .awburst
input wire [1:0] hps_h2f_lw_axi_master_awlock, // .awlock
input wire [3:0] hps_h2f_lw_axi_master_awcache, // .awcache
input wire [2:0] hps_h2f_lw_axi_master_awprot, // .awprot
input wire hps_h2f_lw_axi_master_awvalid, // .awvalid
output wire hps_h2f_lw_axi_master_awready, // .awready
input wire [11:0] hps_h2f_lw_axi_master_wid, // .wid
input wire [31:0] hps_h2f_lw_axi_master_wdata, // .wdata
input wire [3:0] hps_h2f_lw_axi_master_wstrb, // .wstrb
input wire hps_h2f_lw_axi_master_wlast, // .wlast
input wire hps_h2f_lw_axi_master_wvalid, // .wvalid
output wire hps_h2f_lw_axi_master_wready, // .wready
output wire [11:0] hps_h2f_lw_axi_master_bid, // .bid
output wire [1:0] hps_h2f_lw_axi_master_bresp, // .bresp
output wire hps_h2f_lw_axi_master_bvalid, // .bvalid
input wire hps_h2f_lw_axi_master_bready, // .bready
input wire [11:0] hps_h2f_lw_axi_master_arid, // .arid
input wire [20:0] hps_h2f_lw_axi_master_araddr, // .araddr
input wire [3:0] hps_h2f_lw_axi_master_arlen, // .arlen
input wire [2:0] hps_h2f_lw_axi_master_arsize, // .arsize
input wire [1:0] hps_h2f_lw_axi_master_arburst, // .arburst
input wire [1:0] hps_h2f_lw_axi_master_arlock, // .arlock
input wire [3:0] hps_h2f_lw_axi_master_arcache, // .arcache
input wire [2:0] hps_h2f_lw_axi_master_arprot, // .arprot
input wire hps_h2f_lw_axi_master_arvalid, // .arvalid
output wire hps_h2f_lw_axi_master_arready, // .arready
output wire [11:0] hps_h2f_lw_axi_master_rid, // .rid
output wire [31:0] hps_h2f_lw_axi_master_rdata, // .rdata
output wire [1:0] hps_h2f_lw_axi_master_rresp, // .rresp
output wire hps_h2f_lw_axi_master_rlast, // .rlast
output wire hps_h2f_lw_axi_master_rvalid, // .rvalid
input wire hps_h2f_lw_axi_master_rready, // .rready
input wire config_clk_out_clk_clk, // config_clk_out_clk.clk
input wire hps_h2f_lw_axi_master_agent_clk_reset_reset_bridge_in_reset_reset, // hps_h2f_lw_axi_master_agent_clk_reset_reset_bridge_in_reset.reset
input wire version_id_clk_reset_reset_bridge_in_reset_reset, // version_id_clk_reset_reset_bridge_in_reset.reset
output wire [10:0] acl_kernel_clk_ctrl_address, // acl_kernel_clk_ctrl.address
output wire acl_kernel_clk_ctrl_write, // .write
output wire acl_kernel_clk_ctrl_read, // .read
input wire [31:0] acl_kernel_clk_ctrl_readdata, // .readdata
output wire [31:0] acl_kernel_clk_ctrl_writedata, // .writedata
output wire [0:0] acl_kernel_clk_ctrl_burstcount, // .burstcount
output wire [3:0] acl_kernel_clk_ctrl_byteenable, // .byteenable
input wire acl_kernel_clk_ctrl_readdatavalid, // .readdatavalid
input wire acl_kernel_clk_ctrl_waitrequest, // .waitrequest
output wire acl_kernel_clk_ctrl_debugaccess, // .debugaccess
output wire [13:0] acl_kernel_interface_kernel_cntrl_address, // acl_kernel_interface_kernel_cntrl.address
output wire acl_kernel_interface_kernel_cntrl_write, // .write
output wire acl_kernel_interface_kernel_cntrl_read, // .read
input wire [31:0] acl_kernel_interface_kernel_cntrl_readdata, // .readdata
output wire [31:0] acl_kernel_interface_kernel_cntrl_writedata, // .writedata
output wire [0:0] acl_kernel_interface_kernel_cntrl_burstcount, // .burstcount
output wire [3:0] acl_kernel_interface_kernel_cntrl_byteenable, // .byteenable
input wire acl_kernel_interface_kernel_cntrl_readdatavalid, // .readdatavalid
input wire acl_kernel_interface_kernel_cntrl_waitrequest, // .waitrequest
output wire acl_kernel_interface_kernel_cntrl_debugaccess, // .debugaccess
output wire version_id_s_read, // version_id_s.read
input wire [31:0] version_id_s_readdata // .readdata
);
wire version_id_s_agent_m0_waitrequest; // version_id_s_translator:uav_waitrequest -> version_id_s_agent:m0_waitrequest
wire [2:0] version_id_s_agent_m0_burstcount; // version_id_s_agent:m0_burstcount -> version_id_s_translator:uav_burstcount
wire [31:0] version_id_s_agent_m0_writedata; // version_id_s_agent:m0_writedata -> version_id_s_translator:uav_writedata
wire [20:0] version_id_s_agent_m0_address; // version_id_s_agent:m0_address -> version_id_s_translator:uav_address
wire version_id_s_agent_m0_write; // version_id_s_agent:m0_write -> version_id_s_translator:uav_write
wire version_id_s_agent_m0_lock; // version_id_s_agent:m0_lock -> version_id_s_translator:uav_lock
wire version_id_s_agent_m0_read; // version_id_s_agent:m0_read -> version_id_s_translator:uav_read
wire [31:0] version_id_s_agent_m0_readdata; // version_id_s_translator:uav_readdata -> version_id_s_agent:m0_readdata
wire version_id_s_agent_m0_readdatavalid; // version_id_s_translator:uav_readdatavalid -> version_id_s_agent:m0_readdatavalid
wire version_id_s_agent_m0_debugaccess; // version_id_s_agent:m0_debugaccess -> version_id_s_translator:uav_debugaccess
wire [3:0] version_id_s_agent_m0_byteenable; // version_id_s_agent:m0_byteenable -> version_id_s_translator:uav_byteenable
wire version_id_s_agent_rf_source_endofpacket; // version_id_s_agent:rf_source_endofpacket -> version_id_s_agent_rsp_fifo:in_endofpacket
wire version_id_s_agent_rf_source_valid; // version_id_s_agent:rf_source_valid -> version_id_s_agent_rsp_fifo:in_valid
wire version_id_s_agent_rf_source_startofpacket; // version_id_s_agent:rf_source_startofpacket -> version_id_s_agent_rsp_fifo:in_startofpacket
wire [114:0] version_id_s_agent_rf_source_data; // version_id_s_agent:rf_source_data -> version_id_s_agent_rsp_fifo:in_data
wire version_id_s_agent_rf_source_ready; // version_id_s_agent_rsp_fifo:in_ready -> version_id_s_agent:rf_source_ready
wire version_id_s_agent_rsp_fifo_out_endofpacket; // version_id_s_agent_rsp_fifo:out_endofpacket -> version_id_s_agent:rf_sink_endofpacket
wire version_id_s_agent_rsp_fifo_out_valid; // version_id_s_agent_rsp_fifo:out_valid -> version_id_s_agent:rf_sink_valid
wire version_id_s_agent_rsp_fifo_out_startofpacket; // version_id_s_agent_rsp_fifo:out_startofpacket -> version_id_s_agent:rf_sink_startofpacket
wire [114:0] version_id_s_agent_rsp_fifo_out_data; // version_id_s_agent_rsp_fifo:out_data -> version_id_s_agent:rf_sink_data
wire version_id_s_agent_rsp_fifo_out_ready; // version_id_s_agent:rf_sink_ready -> version_id_s_agent_rsp_fifo:out_ready
wire version_id_s_agent_rdata_fifo_src_valid; // version_id_s_agent:rdata_fifo_src_valid -> version_id_s_agent_rdata_fifo:in_valid
wire [33:0] version_id_s_agent_rdata_fifo_src_data; // version_id_s_agent:rdata_fifo_src_data -> version_id_s_agent_rdata_fifo:in_data
wire version_id_s_agent_rdata_fifo_src_ready; // version_id_s_agent_rdata_fifo:in_ready -> version_id_s_agent:rdata_fifo_src_ready
wire version_id_s_agent_rdata_fifo_out_valid; // version_id_s_agent_rdata_fifo:out_valid -> version_id_s_agent:rdata_fifo_sink_valid
wire [33:0] version_id_s_agent_rdata_fifo_out_data; // version_id_s_agent_rdata_fifo:out_data -> version_id_s_agent:rdata_fifo_sink_data
wire version_id_s_agent_rdata_fifo_out_ready; // version_id_s_agent:rdata_fifo_sink_ready -> version_id_s_agent_rdata_fifo:out_ready
wire acl_kernel_interface_kernel_cntrl_agent_m0_waitrequest; // acl_kernel_interface_kernel_cntrl_translator:uav_waitrequest -> acl_kernel_interface_kernel_cntrl_agent:m0_waitrequest
wire [2:0] acl_kernel_interface_kernel_cntrl_agent_m0_burstcount; // acl_kernel_interface_kernel_cntrl_agent:m0_burstcount -> acl_kernel_interface_kernel_cntrl_translator:uav_burstcount
wire [31:0] acl_kernel_interface_kernel_cntrl_agent_m0_writedata; // acl_kernel_interface_kernel_cntrl_agent:m0_writedata -> acl_kernel_interface_kernel_cntrl_translator:uav_writedata
wire [20:0] acl_kernel_interface_kernel_cntrl_agent_m0_address; // acl_kernel_interface_kernel_cntrl_agent:m0_address -> acl_kernel_interface_kernel_cntrl_translator:uav_address
wire acl_kernel_interface_kernel_cntrl_agent_m0_write; // acl_kernel_interface_kernel_cntrl_agent:m0_write -> acl_kernel_interface_kernel_cntrl_translator:uav_write
wire acl_kernel_interface_kernel_cntrl_agent_m0_lock; // acl_kernel_interface_kernel_cntrl_agent:m0_lock -> acl_kernel_interface_kernel_cntrl_translator:uav_lock
wire acl_kernel_interface_kernel_cntrl_agent_m0_read; // acl_kernel_interface_kernel_cntrl_agent:m0_read -> acl_kernel_interface_kernel_cntrl_translator:uav_read
wire [31:0] acl_kernel_interface_kernel_cntrl_agent_m0_readdata; // acl_kernel_interface_kernel_cntrl_translator:uav_readdata -> acl_kernel_interface_kernel_cntrl_agent:m0_readdata
wire acl_kernel_interface_kernel_cntrl_agent_m0_readdatavalid; // acl_kernel_interface_kernel_cntrl_translator:uav_readdatavalid -> acl_kernel_interface_kernel_cntrl_agent:m0_readdatavalid
wire acl_kernel_interface_kernel_cntrl_agent_m0_debugaccess; // acl_kernel_interface_kernel_cntrl_agent:m0_debugaccess -> acl_kernel_interface_kernel_cntrl_translator:uav_debugaccess
wire [3:0] acl_kernel_interface_kernel_cntrl_agent_m0_byteenable; // acl_kernel_interface_kernel_cntrl_agent:m0_byteenable -> acl_kernel_interface_kernel_cntrl_translator:uav_byteenable
wire acl_kernel_interface_kernel_cntrl_agent_rf_source_endofpacket; // acl_kernel_interface_kernel_cntrl_agent:rf_source_endofpacket -> acl_kernel_interface_kernel_cntrl_agent_rsp_fifo:in_endofpacket
wire acl_kernel_interface_kernel_cntrl_agent_rf_source_valid; // acl_kernel_interface_kernel_cntrl_agent:rf_source_valid -> acl_kernel_interface_kernel_cntrl_agent_rsp_fifo:in_valid
wire acl_kernel_interface_kernel_cntrl_agent_rf_source_startofpacket; // acl_kernel_interface_kernel_cntrl_agent:rf_source_startofpacket -> acl_kernel_interface_kernel_cntrl_agent_rsp_fifo:in_startofpacket
wire [114:0] acl_kernel_interface_kernel_cntrl_agent_rf_source_data; // acl_kernel_interface_kernel_cntrl_agent:rf_source_data -> acl_kernel_interface_kernel_cntrl_agent_rsp_fifo:in_data
wire acl_kernel_interface_kernel_cntrl_agent_rf_source_ready; // acl_kernel_interface_kernel_cntrl_agent_rsp_fifo:in_ready -> acl_kernel_interface_kernel_cntrl_agent:rf_source_ready
wire acl_kernel_interface_kernel_cntrl_agent_rsp_fifo_out_endofpacket; // acl_kernel_interface_kernel_cntrl_agent_rsp_fifo:out_endofpacket -> acl_kernel_interface_kernel_cntrl_agent:rf_sink_endofpacket
wire acl_kernel_interface_kernel_cntrl_agent_rsp_fifo_out_valid; // acl_kernel_interface_kernel_cntrl_agent_rsp_fifo:out_valid -> acl_kernel_interface_kernel_cntrl_agent:rf_sink_valid
wire acl_kernel_interface_kernel_cntrl_agent_rsp_fifo_out_startofpacket; // acl_kernel_interface_kernel_cntrl_agent_rsp_fifo:out_startofpacket -> acl_kernel_interface_kernel_cntrl_agent:rf_sink_startofpacket
wire [114:0] acl_kernel_interface_kernel_cntrl_agent_rsp_fifo_out_data; // acl_kernel_interface_kernel_cntrl_agent_rsp_fifo:out_data -> acl_kernel_interface_kernel_cntrl_agent:rf_sink_data
wire acl_kernel_interface_kernel_cntrl_agent_rsp_fifo_out_ready; // acl_kernel_interface_kernel_cntrl_agent:rf_sink_ready -> acl_kernel_interface_kernel_cntrl_agent_rsp_fifo:out_ready
wire acl_kernel_interface_kernel_cntrl_agent_rdata_fifo_src_valid; // acl_kernel_interface_kernel_cntrl_agent:rdata_fifo_src_valid -> acl_kernel_interface_kernel_cntrl_agent_rdata_fifo:in_valid
wire [33:0] acl_kernel_interface_kernel_cntrl_agent_rdata_fifo_src_data; // acl_kernel_interface_kernel_cntrl_agent:rdata_fifo_src_data -> acl_kernel_interface_kernel_cntrl_agent_rdata_fifo:in_data
wire acl_kernel_interface_kernel_cntrl_agent_rdata_fifo_src_ready; // acl_kernel_interface_kernel_cntrl_agent_rdata_fifo:in_ready -> acl_kernel_interface_kernel_cntrl_agent:rdata_fifo_src_ready
wire acl_kernel_interface_kernel_cntrl_agent_rdata_fifo_out_valid; // acl_kernel_interface_kernel_cntrl_agent_rdata_fifo:out_valid -> acl_kernel_interface_kernel_cntrl_agent:rdata_fifo_sink_valid
wire [33:0] acl_kernel_interface_kernel_cntrl_agent_rdata_fifo_out_data; // acl_kernel_interface_kernel_cntrl_agent_rdata_fifo:out_data -> acl_kernel_interface_kernel_cntrl_agent:rdata_fifo_sink_data
wire acl_kernel_interface_kernel_cntrl_agent_rdata_fifo_out_ready; // acl_kernel_interface_kernel_cntrl_agent:rdata_fifo_sink_ready -> acl_kernel_interface_kernel_cntrl_agent_rdata_fifo:out_ready
wire acl_kernel_clk_ctrl_agent_m0_waitrequest; // acl_kernel_clk_ctrl_translator:uav_waitrequest -> acl_kernel_clk_ctrl_agent:m0_waitrequest
wire [2:0] acl_kernel_clk_ctrl_agent_m0_burstcount; // acl_kernel_clk_ctrl_agent:m0_burstcount -> acl_kernel_clk_ctrl_translator:uav_burstcount
wire [31:0] acl_kernel_clk_ctrl_agent_m0_writedata; // acl_kernel_clk_ctrl_agent:m0_writedata -> acl_kernel_clk_ctrl_translator:uav_writedata
wire [20:0] acl_kernel_clk_ctrl_agent_m0_address; // acl_kernel_clk_ctrl_agent:m0_address -> acl_kernel_clk_ctrl_translator:uav_address
wire acl_kernel_clk_ctrl_agent_m0_write; // acl_kernel_clk_ctrl_agent:m0_write -> acl_kernel_clk_ctrl_translator:uav_write
wire acl_kernel_clk_ctrl_agent_m0_lock; // acl_kernel_clk_ctrl_agent:m0_lock -> acl_kernel_clk_ctrl_translator:uav_lock
wire acl_kernel_clk_ctrl_agent_m0_read; // acl_kernel_clk_ctrl_agent:m0_read -> acl_kernel_clk_ctrl_translator:uav_read
wire [31:0] acl_kernel_clk_ctrl_agent_m0_readdata; // acl_kernel_clk_ctrl_translator:uav_readdata -> acl_kernel_clk_ctrl_agent:m0_readdata
wire acl_kernel_clk_ctrl_agent_m0_readdatavalid; // acl_kernel_clk_ctrl_translator:uav_readdatavalid -> acl_kernel_clk_ctrl_agent:m0_readdatavalid
wire acl_kernel_clk_ctrl_agent_m0_debugaccess; // acl_kernel_clk_ctrl_agent:m0_debugaccess -> acl_kernel_clk_ctrl_translator:uav_debugaccess
wire [3:0] acl_kernel_clk_ctrl_agent_m0_byteenable; // acl_kernel_clk_ctrl_agent:m0_byteenable -> acl_kernel_clk_ctrl_translator:uav_byteenable
wire acl_kernel_clk_ctrl_agent_rf_source_endofpacket; // acl_kernel_clk_ctrl_agent:rf_source_endofpacket -> acl_kernel_clk_ctrl_agent_rsp_fifo:in_endofpacket
wire acl_kernel_clk_ctrl_agent_rf_source_valid; // acl_kernel_clk_ctrl_agent:rf_source_valid -> acl_kernel_clk_ctrl_agent_rsp_fifo:in_valid
wire acl_kernel_clk_ctrl_agent_rf_source_startofpacket; // acl_kernel_clk_ctrl_agent:rf_source_startofpacket -> acl_kernel_clk_ctrl_agent_rsp_fifo:in_startofpacket
wire [114:0] acl_kernel_clk_ctrl_agent_rf_source_data; // acl_kernel_clk_ctrl_agent:rf_source_data -> acl_kernel_clk_ctrl_agent_rsp_fifo:in_data
wire acl_kernel_clk_ctrl_agent_rf_source_ready; // acl_kernel_clk_ctrl_agent_rsp_fifo:in_ready -> acl_kernel_clk_ctrl_agent:rf_source_ready
wire acl_kernel_clk_ctrl_agent_rsp_fifo_out_endofpacket; // acl_kernel_clk_ctrl_agent_rsp_fifo:out_endofpacket -> acl_kernel_clk_ctrl_agent:rf_sink_endofpacket
wire acl_kernel_clk_ctrl_agent_rsp_fifo_out_valid; // acl_kernel_clk_ctrl_agent_rsp_fifo:out_valid -> acl_kernel_clk_ctrl_agent:rf_sink_valid
wire acl_kernel_clk_ctrl_agent_rsp_fifo_out_startofpacket; // acl_kernel_clk_ctrl_agent_rsp_fifo:out_startofpacket -> acl_kernel_clk_ctrl_agent:rf_sink_startofpacket
wire [114:0] acl_kernel_clk_ctrl_agent_rsp_fifo_out_data; // acl_kernel_clk_ctrl_agent_rsp_fifo:out_data -> acl_kernel_clk_ctrl_agent:rf_sink_data
wire acl_kernel_clk_ctrl_agent_rsp_fifo_out_ready; // acl_kernel_clk_ctrl_agent:rf_sink_ready -> acl_kernel_clk_ctrl_agent_rsp_fifo:out_ready
wire acl_kernel_clk_ctrl_agent_rdata_fifo_src_valid; // acl_kernel_clk_ctrl_agent:rdata_fifo_src_valid -> acl_kernel_clk_ctrl_agent_rdata_fifo:in_valid
wire [33:0] acl_kernel_clk_ctrl_agent_rdata_fifo_src_data; // acl_kernel_clk_ctrl_agent:rdata_fifo_src_data -> acl_kernel_clk_ctrl_agent_rdata_fifo:in_data
wire acl_kernel_clk_ctrl_agent_rdata_fifo_src_ready; // acl_kernel_clk_ctrl_agent_rdata_fifo:in_ready -> acl_kernel_clk_ctrl_agent:rdata_fifo_src_ready
wire acl_kernel_clk_ctrl_agent_rdata_fifo_out_valid; // acl_kernel_clk_ctrl_agent_rdata_fifo:out_valid -> acl_kernel_clk_ctrl_agent:rdata_fifo_sink_valid
wire [33:0] acl_kernel_clk_ctrl_agent_rdata_fifo_out_data; // acl_kernel_clk_ctrl_agent_rdata_fifo:out_data -> acl_kernel_clk_ctrl_agent:rdata_fifo_sink_data
wire acl_kernel_clk_ctrl_agent_rdata_fifo_out_ready; // acl_kernel_clk_ctrl_agent:rdata_fifo_sink_ready -> acl_kernel_clk_ctrl_agent_rdata_fifo:out_ready
wire hps_h2f_lw_axi_master_agent_write_cp_endofpacket; // hps_h2f_lw_axi_master_agent:write_cp_endofpacket -> router:sink_endofpacket
wire hps_h2f_lw_axi_master_agent_write_cp_valid; // hps_h2f_lw_axi_master_agent:write_cp_valid -> router:sink_valid
wire hps_h2f_lw_axi_master_agent_write_cp_startofpacket; // hps_h2f_lw_axi_master_agent:write_cp_startofpacket -> router:sink_startofpacket
wire [113:0] hps_h2f_lw_axi_master_agent_write_cp_data; // hps_h2f_lw_axi_master_agent:write_cp_data -> router:sink_data
wire hps_h2f_lw_axi_master_agent_write_cp_ready; // router:sink_ready -> hps_h2f_lw_axi_master_agent:write_cp_ready
wire hps_h2f_lw_axi_master_agent_read_cp_endofpacket; // hps_h2f_lw_axi_master_agent:read_cp_endofpacket -> router_001:sink_endofpacket
wire hps_h2f_lw_axi_master_agent_read_cp_valid; // hps_h2f_lw_axi_master_agent:read_cp_valid -> router_001:sink_valid
wire hps_h2f_lw_axi_master_agent_read_cp_startofpacket; // hps_h2f_lw_axi_master_agent:read_cp_startofpacket -> router_001:sink_startofpacket
wire [113:0] hps_h2f_lw_axi_master_agent_read_cp_data; // hps_h2f_lw_axi_master_agent:read_cp_data -> router_001:sink_data
wire hps_h2f_lw_axi_master_agent_read_cp_ready; // router_001:sink_ready -> hps_h2f_lw_axi_master_agent:read_cp_ready
wire version_id_s_agent_rp_endofpacket; // version_id_s_agent:rp_endofpacket -> router_002:sink_endofpacket
wire version_id_s_agent_rp_valid; // version_id_s_agent:rp_valid -> router_002:sink_valid
wire version_id_s_agent_rp_startofpacket; // version_id_s_agent:rp_startofpacket -> router_002:sink_startofpacket
wire [113:0] version_id_s_agent_rp_data; // version_id_s_agent:rp_data -> router_002:sink_data
wire version_id_s_agent_rp_ready; // router_002:sink_ready -> version_id_s_agent:rp_ready
wire router_002_src_endofpacket; // router_002:src_endofpacket -> rsp_demux:sink_endofpacket
wire router_002_src_valid; // router_002:src_valid -> rsp_demux:sink_valid
wire router_002_src_startofpacket; // router_002:src_startofpacket -> rsp_demux:sink_startofpacket
wire [113:0] router_002_src_data; // router_002:src_data -> rsp_demux:sink_data
wire [2:0] router_002_src_channel; // router_002:src_channel -> rsp_demux:sink_channel
wire router_002_src_ready; // rsp_demux:sink_ready -> router_002:src_ready
wire acl_kernel_interface_kernel_cntrl_agent_rp_endofpacket; // acl_kernel_interface_kernel_cntrl_agent:rp_endofpacket -> router_003:sink_endofpacket
wire acl_kernel_interface_kernel_cntrl_agent_rp_valid; // acl_kernel_interface_kernel_cntrl_agent:rp_valid -> router_003:sink_valid
wire acl_kernel_interface_kernel_cntrl_agent_rp_startofpacket; // acl_kernel_interface_kernel_cntrl_agent:rp_startofpacket -> router_003:sink_startofpacket
wire [113:0] acl_kernel_interface_kernel_cntrl_agent_rp_data; // acl_kernel_interface_kernel_cntrl_agent:rp_data -> router_003:sink_data
wire acl_kernel_interface_kernel_cntrl_agent_rp_ready; // router_003:sink_ready -> acl_kernel_interface_kernel_cntrl_agent:rp_ready
wire router_003_src_endofpacket; // router_003:src_endofpacket -> rsp_demux_001:sink_endofpacket
wire router_003_src_valid; // router_003:src_valid -> rsp_demux_001:sink_valid
wire router_003_src_startofpacket; // router_003:src_startofpacket -> rsp_demux_001:sink_startofpacket
wire [113:0] router_003_src_data; // router_003:src_data -> rsp_demux_001:sink_data
wire [2:0] router_003_src_channel; // router_003:src_channel -> rsp_demux_001:sink_channel
wire router_003_src_ready; // rsp_demux_001:sink_ready -> router_003:src_ready
wire acl_kernel_clk_ctrl_agent_rp_endofpacket; // acl_kernel_clk_ctrl_agent:rp_endofpacket -> router_004:sink_endofpacket
wire acl_kernel_clk_ctrl_agent_rp_valid; // acl_kernel_clk_ctrl_agent:rp_valid -> router_004:sink_valid
wire acl_kernel_clk_ctrl_agent_rp_startofpacket; // acl_kernel_clk_ctrl_agent:rp_startofpacket -> router_004:sink_startofpacket
wire [113:0] acl_kernel_clk_ctrl_agent_rp_data; // acl_kernel_clk_ctrl_agent:rp_data -> router_004:sink_data
wire acl_kernel_clk_ctrl_agent_rp_ready; // router_004:sink_ready -> acl_kernel_clk_ctrl_agent:rp_ready
wire router_004_src_endofpacket; // router_004:src_endofpacket -> rsp_demux_002:sink_endofpacket
wire router_004_src_valid; // router_004:src_valid -> rsp_demux_002:sink_valid
wire router_004_src_startofpacket; // router_004:src_startofpacket -> rsp_demux_002:sink_startofpacket
wire [113:0] router_004_src_data; // router_004:src_data -> rsp_demux_002:sink_data
wire [2:0] router_004_src_channel; // router_004:src_channel -> rsp_demux_002:sink_channel
wire router_004_src_ready; // rsp_demux_002:sink_ready -> router_004:src_ready
wire router_src_endofpacket; // router:src_endofpacket -> hps_h2f_lw_axi_master_wr_limiter:cmd_sink_endofpacket
wire router_src_valid; // router:src_valid -> hps_h2f_lw_axi_master_wr_limiter:cmd_sink_valid
wire router_src_startofpacket; // router:src_startofpacket -> hps_h2f_lw_axi_master_wr_limiter:cmd_sink_startofpacket
wire [113:0] router_src_data; // router:src_data -> hps_h2f_lw_axi_master_wr_limiter:cmd_sink_data
wire [2:0] router_src_channel; // router:src_channel -> hps_h2f_lw_axi_master_wr_limiter:cmd_sink_channel
wire router_src_ready; // hps_h2f_lw_axi_master_wr_limiter:cmd_sink_ready -> router:src_ready
wire hps_h2f_lw_axi_master_wr_limiter_cmd_src_endofpacket; // hps_h2f_lw_axi_master_wr_limiter:cmd_src_endofpacket -> cmd_demux:sink_endofpacket
wire hps_h2f_lw_axi_master_wr_limiter_cmd_src_startofpacket; // hps_h2f_lw_axi_master_wr_limiter:cmd_src_startofpacket -> cmd_demux:sink_startofpacket
wire [113:0] hps_h2f_lw_axi_master_wr_limiter_cmd_src_data; // hps_h2f_lw_axi_master_wr_limiter:cmd_src_data -> cmd_demux:sink_data
wire [2:0] hps_h2f_lw_axi_master_wr_limiter_cmd_src_channel; // hps_h2f_lw_axi_master_wr_limiter:cmd_src_channel -> cmd_demux:sink_channel
wire hps_h2f_lw_axi_master_wr_limiter_cmd_src_ready; // cmd_demux:sink_ready -> hps_h2f_lw_axi_master_wr_limiter:cmd_src_ready
wire rsp_mux_src_endofpacket; // rsp_mux:src_endofpacket -> hps_h2f_lw_axi_master_wr_limiter:rsp_sink_endofpacket
wire rsp_mux_src_valid; // rsp_mux:src_valid -> hps_h2f_lw_axi_master_wr_limiter:rsp_sink_valid
wire rsp_mux_src_startofpacket; // rsp_mux:src_startofpacket -> hps_h2f_lw_axi_master_wr_limiter:rsp_sink_startofpacket
wire [113:0] rsp_mux_src_data; // rsp_mux:src_data -> hps_h2f_lw_axi_master_wr_limiter:rsp_sink_data
wire [2:0] rsp_mux_src_channel; // rsp_mux:src_channel -> hps_h2f_lw_axi_master_wr_limiter:rsp_sink_channel
wire rsp_mux_src_ready; // hps_h2f_lw_axi_master_wr_limiter:rsp_sink_ready -> rsp_mux:src_ready
wire hps_h2f_lw_axi_master_wr_limiter_rsp_src_endofpacket; // hps_h2f_lw_axi_master_wr_limiter:rsp_src_endofpacket -> hps_h2f_lw_axi_master_agent:write_rp_endofpacket
wire hps_h2f_lw_axi_master_wr_limiter_rsp_src_valid; // hps_h2f_lw_axi_master_wr_limiter:rsp_src_valid -> hps_h2f_lw_axi_master_agent:write_rp_valid
wire hps_h2f_lw_axi_master_wr_limiter_rsp_src_startofpacket; // hps_h2f_lw_axi_master_wr_limiter:rsp_src_startofpacket -> hps_h2f_lw_axi_master_agent:write_rp_startofpacket
wire [113:0] hps_h2f_lw_axi_master_wr_limiter_rsp_src_data; // hps_h2f_lw_axi_master_wr_limiter:rsp_src_data -> hps_h2f_lw_axi_master_agent:write_rp_data
wire [2:0] hps_h2f_lw_axi_master_wr_limiter_rsp_src_channel; // hps_h2f_lw_axi_master_wr_limiter:rsp_src_channel -> hps_h2f_lw_axi_master_agent:write_rp_channel
wire hps_h2f_lw_axi_master_wr_limiter_rsp_src_ready; // hps_h2f_lw_axi_master_agent:write_rp_ready -> hps_h2f_lw_axi_master_wr_limiter:rsp_src_ready
wire router_001_src_endofpacket; // router_001:src_endofpacket -> hps_h2f_lw_axi_master_rd_limiter:cmd_sink_endofpacket
wire router_001_src_valid; // router_001:src_valid -> hps_h2f_lw_axi_master_rd_limiter:cmd_sink_valid
wire router_001_src_startofpacket; // router_001:src_startofpacket -> hps_h2f_lw_axi_master_rd_limiter:cmd_sink_startofpacket
wire [113:0] router_001_src_data; // router_001:src_data -> hps_h2f_lw_axi_master_rd_limiter:cmd_sink_data
wire [2:0] router_001_src_channel; // router_001:src_channel -> hps_h2f_lw_axi_master_rd_limiter:cmd_sink_channel
wire router_001_src_ready; // hps_h2f_lw_axi_master_rd_limiter:cmd_sink_ready -> router_001:src_ready
wire hps_h2f_lw_axi_master_rd_limiter_cmd_src_endofpacket; // hps_h2f_lw_axi_master_rd_limiter:cmd_src_endofpacket -> cmd_demux_001:sink_endofpacket
wire hps_h2f_lw_axi_master_rd_limiter_cmd_src_startofpacket; // hps_h2f_lw_axi_master_rd_limiter:cmd_src_startofpacket -> cmd_demux_001:sink_startofpacket
wire [113:0] hps_h2f_lw_axi_master_rd_limiter_cmd_src_data; // hps_h2f_lw_axi_master_rd_limiter:cmd_src_data -> cmd_demux_001:sink_data
wire [2:0] hps_h2f_lw_axi_master_rd_limiter_cmd_src_channel; // hps_h2f_lw_axi_master_rd_limiter:cmd_src_channel -> cmd_demux_001:sink_channel
wire hps_h2f_lw_axi_master_rd_limiter_cmd_src_ready; // cmd_demux_001:sink_ready -> hps_h2f_lw_axi_master_rd_limiter:cmd_src_ready
wire rsp_mux_001_src_endofpacket; // rsp_mux_001:src_endofpacket -> hps_h2f_lw_axi_master_rd_limiter:rsp_sink_endofpacket
wire rsp_mux_001_src_valid; // rsp_mux_001:src_valid -> hps_h2f_lw_axi_master_rd_limiter:rsp_sink_valid
wire rsp_mux_001_src_startofpacket; // rsp_mux_001:src_startofpacket -> hps_h2f_lw_axi_master_rd_limiter:rsp_sink_startofpacket
wire [113:0] rsp_mux_001_src_data; // rsp_mux_001:src_data -> hps_h2f_lw_axi_master_rd_limiter:rsp_sink_data
wire [2:0] rsp_mux_001_src_channel; // rsp_mux_001:src_channel -> hps_h2f_lw_axi_master_rd_limiter:rsp_sink_channel
wire rsp_mux_001_src_ready; // hps_h2f_lw_axi_master_rd_limiter:rsp_sink_ready -> rsp_mux_001:src_ready
wire hps_h2f_lw_axi_master_rd_limiter_rsp_src_endofpacket; // hps_h2f_lw_axi_master_rd_limiter:rsp_src_endofpacket -> hps_h2f_lw_axi_master_agent:read_rp_endofpacket
wire hps_h2f_lw_axi_master_rd_limiter_rsp_src_valid; // hps_h2f_lw_axi_master_rd_limiter:rsp_src_valid -> hps_h2f_lw_axi_master_agent:read_rp_valid
wire hps_h2f_lw_axi_master_rd_limiter_rsp_src_startofpacket; // hps_h2f_lw_axi_master_rd_limiter:rsp_src_startofpacket -> hps_h2f_lw_axi_master_agent:read_rp_startofpacket
wire [113:0] hps_h2f_lw_axi_master_rd_limiter_rsp_src_data; // hps_h2f_lw_axi_master_rd_limiter:rsp_src_data -> hps_h2f_lw_axi_master_agent:read_rp_data
wire [2:0] hps_h2f_lw_axi_master_rd_limiter_rsp_src_channel; // hps_h2f_lw_axi_master_rd_limiter:rsp_src_channel -> hps_h2f_lw_axi_master_agent:read_rp_channel
wire hps_h2f_lw_axi_master_rd_limiter_rsp_src_ready; // hps_h2f_lw_axi_master_agent:read_rp_ready -> hps_h2f_lw_axi_master_rd_limiter:rsp_src_ready
wire cmd_mux_src_endofpacket; // cmd_mux:src_endofpacket -> version_id_s_burst_adapter:sink0_endofpacket
wire cmd_mux_src_valid; // cmd_mux:src_valid -> version_id_s_burst_adapter:sink0_valid
wire cmd_mux_src_startofpacket; // cmd_mux:src_startofpacket -> version_id_s_burst_adapter:sink0_startofpacket
wire [113:0] cmd_mux_src_data; // cmd_mux:src_data -> version_id_s_burst_adapter:sink0_data
wire [2:0] cmd_mux_src_channel; // cmd_mux:src_channel -> version_id_s_burst_adapter:sink0_channel
wire cmd_mux_src_ready; // version_id_s_burst_adapter:sink0_ready -> cmd_mux:src_ready
wire version_id_s_burst_adapter_source0_endofpacket; // version_id_s_burst_adapter:source0_endofpacket -> version_id_s_agent:cp_endofpacket
wire version_id_s_burst_adapter_source0_valid; // version_id_s_burst_adapter:source0_valid -> version_id_s_agent:cp_valid
wire version_id_s_burst_adapter_source0_startofpacket; // version_id_s_burst_adapter:source0_startofpacket -> version_id_s_agent:cp_startofpacket
wire [113:0] version_id_s_burst_adapter_source0_data; // version_id_s_burst_adapter:source0_data -> version_id_s_agent:cp_data
wire version_id_s_burst_adapter_source0_ready; // version_id_s_agent:cp_ready -> version_id_s_burst_adapter:source0_ready
wire [2:0] version_id_s_burst_adapter_source0_channel; // version_id_s_burst_adapter:source0_channel -> version_id_s_agent:cp_channel
wire cmd_mux_001_src_endofpacket; // cmd_mux_001:src_endofpacket -> acl_kernel_interface_kernel_cntrl_burst_adapter:sink0_endofpacket
wire cmd_mux_001_src_valid; // cmd_mux_001:src_valid -> acl_kernel_interface_kernel_cntrl_burst_adapter:sink0_valid
wire cmd_mux_001_src_startofpacket; // cmd_mux_001:src_startofpacket -> acl_kernel_interface_kernel_cntrl_burst_adapter:sink0_startofpacket
wire [113:0] cmd_mux_001_src_data; // cmd_mux_001:src_data -> acl_kernel_interface_kernel_cntrl_burst_adapter:sink0_data
wire [2:0] cmd_mux_001_src_channel; // cmd_mux_001:src_channel -> acl_kernel_interface_kernel_cntrl_burst_adapter:sink0_channel
wire cmd_mux_001_src_ready; // acl_kernel_interface_kernel_cntrl_burst_adapter:sink0_ready -> cmd_mux_001:src_ready
wire acl_kernel_interface_kernel_cntrl_burst_adapter_source0_endofpacket; // acl_kernel_interface_kernel_cntrl_burst_adapter:source0_endofpacket -> acl_kernel_interface_kernel_cntrl_agent:cp_endofpacket
wire acl_kernel_interface_kernel_cntrl_burst_adapter_source0_valid; // acl_kernel_interface_kernel_cntrl_burst_adapter:source0_valid -> acl_kernel_interface_kernel_cntrl_agent:cp_valid
wire acl_kernel_interface_kernel_cntrl_burst_adapter_source0_startofpacket; // acl_kernel_interface_kernel_cntrl_burst_adapter:source0_startofpacket -> acl_kernel_interface_kernel_cntrl_agent:cp_startofpacket
wire [113:0] acl_kernel_interface_kernel_cntrl_burst_adapter_source0_data; // acl_kernel_interface_kernel_cntrl_burst_adapter:source0_data -> acl_kernel_interface_kernel_cntrl_agent:cp_data
wire acl_kernel_interface_kernel_cntrl_burst_adapter_source0_ready; // acl_kernel_interface_kernel_cntrl_agent:cp_ready -> acl_kernel_interface_kernel_cntrl_burst_adapter:source0_ready
wire [2:0] acl_kernel_interface_kernel_cntrl_burst_adapter_source0_channel; // acl_kernel_interface_kernel_cntrl_burst_adapter:source0_channel -> acl_kernel_interface_kernel_cntrl_agent:cp_channel
wire cmd_mux_002_src_endofpacket; // cmd_mux_002:src_endofpacket -> acl_kernel_clk_ctrl_burst_adapter:sink0_endofpacket
wire cmd_mux_002_src_valid; // cmd_mux_002:src_valid -> acl_kernel_clk_ctrl_burst_adapter:sink0_valid
wire cmd_mux_002_src_startofpacket; // cmd_mux_002:src_startofpacket -> acl_kernel_clk_ctrl_burst_adapter:sink0_startofpacket
wire [113:0] cmd_mux_002_src_data; // cmd_mux_002:src_data -> acl_kernel_clk_ctrl_burst_adapter:sink0_data
wire [2:0] cmd_mux_002_src_channel; // cmd_mux_002:src_channel -> acl_kernel_clk_ctrl_burst_adapter:sink0_channel
wire cmd_mux_002_src_ready; // acl_kernel_clk_ctrl_burst_adapter:sink0_ready -> cmd_mux_002:src_ready
wire acl_kernel_clk_ctrl_burst_adapter_source0_endofpacket; // acl_kernel_clk_ctrl_burst_adapter:source0_endofpacket -> acl_kernel_clk_ctrl_agent:cp_endofpacket
wire acl_kernel_clk_ctrl_burst_adapter_source0_valid; // acl_kernel_clk_ctrl_burst_adapter:source0_valid -> acl_kernel_clk_ctrl_agent:cp_valid
wire acl_kernel_clk_ctrl_burst_adapter_source0_startofpacket; // acl_kernel_clk_ctrl_burst_adapter:source0_startofpacket -> acl_kernel_clk_ctrl_agent:cp_startofpacket
wire [113:0] acl_kernel_clk_ctrl_burst_adapter_source0_data; // acl_kernel_clk_ctrl_burst_adapter:source0_data -> acl_kernel_clk_ctrl_agent:cp_data
wire acl_kernel_clk_ctrl_burst_adapter_source0_ready; // acl_kernel_clk_ctrl_agent:cp_ready -> acl_kernel_clk_ctrl_burst_adapter:source0_ready
wire [2:0] acl_kernel_clk_ctrl_burst_adapter_source0_channel; // acl_kernel_clk_ctrl_burst_adapter:source0_channel -> acl_kernel_clk_ctrl_agent:cp_channel
wire cmd_demux_src0_endofpacket; // cmd_demux:src0_endofpacket -> cmd_mux:sink0_endofpacket
wire cmd_demux_src0_valid; // cmd_demux:src0_valid -> cmd_mux:sink0_valid
wire cmd_demux_src0_startofpacket; // cmd_demux:src0_startofpacket -> cmd_mux:sink0_startofpacket
wire [113:0] cmd_demux_src0_data; // cmd_demux:src0_data -> cmd_mux:sink0_data
wire [2:0] cmd_demux_src0_channel; // cmd_demux:src0_channel -> cmd_mux:sink0_channel
wire cmd_demux_src0_ready; // cmd_mux:sink0_ready -> cmd_demux:src0_ready
wire cmd_demux_src1_endofpacket; // cmd_demux:src1_endofpacket -> cmd_mux_001:sink0_endofpacket
wire cmd_demux_src1_valid; // cmd_demux:src1_valid -> cmd_mux_001:sink0_valid
wire cmd_demux_src1_startofpacket; // cmd_demux:src1_startofpacket -> cmd_mux_001:sink0_startofpacket
wire [113:0] cmd_demux_src1_data; // cmd_demux:src1_data -> cmd_mux_001:sink0_data
wire [2:0] cmd_demux_src1_channel; // cmd_demux:src1_channel -> cmd_mux_001:sink0_channel
wire cmd_demux_src1_ready; // cmd_mux_001:sink0_ready -> cmd_demux:src1_ready
wire cmd_demux_src2_endofpacket; // cmd_demux:src2_endofpacket -> cmd_mux_002:sink0_endofpacket
wire cmd_demux_src2_valid; // cmd_demux:src2_valid -> cmd_mux_002:sink0_valid
wire cmd_demux_src2_startofpacket; // cmd_demux:src2_startofpacket -> cmd_mux_002:sink0_startofpacket
wire [113:0] cmd_demux_src2_data; // cmd_demux:src2_data -> cmd_mux_002:sink0_data
wire [2:0] cmd_demux_src2_channel; // cmd_demux:src2_channel -> cmd_mux_002:sink0_channel
wire cmd_demux_src2_ready; // cmd_mux_002:sink0_ready -> cmd_demux:src2_ready
wire cmd_demux_001_src0_endofpacket; // cmd_demux_001:src0_endofpacket -> cmd_mux:sink1_endofpacket
wire cmd_demux_001_src0_valid; // cmd_demux_001:src0_valid -> cmd_mux:sink1_valid
wire cmd_demux_001_src0_startofpacket; // cmd_demux_001:src0_startofpacket -> cmd_mux:sink1_startofpacket
wire [113:0] cmd_demux_001_src0_data; // cmd_demux_001:src0_data -> cmd_mux:sink1_data
wire [2:0] cmd_demux_001_src0_channel; // cmd_demux_001:src0_channel -> cmd_mux:sink1_channel
wire cmd_demux_001_src0_ready; // cmd_mux:sink1_ready -> cmd_demux_001:src0_ready
wire cmd_demux_001_src1_endofpacket; // cmd_demux_001:src1_endofpacket -> cmd_mux_001:sink1_endofpacket
wire cmd_demux_001_src1_valid; // cmd_demux_001:src1_valid -> cmd_mux_001:sink1_valid
wire cmd_demux_001_src1_startofpacket; // cmd_demux_001:src1_startofpacket -> cmd_mux_001:sink1_startofpacket
wire [113:0] cmd_demux_001_src1_data; // cmd_demux_001:src1_data -> cmd_mux_001:sink1_data
wire [2:0] cmd_demux_001_src1_channel; // cmd_demux_001:src1_channel -> cmd_mux_001:sink1_channel
wire cmd_demux_001_src1_ready; // cmd_mux_001:sink1_ready -> cmd_demux_001:src1_ready
wire cmd_demux_001_src2_endofpacket; // cmd_demux_001:src2_endofpacket -> cmd_mux_002:sink1_endofpacket
wire cmd_demux_001_src2_valid; // cmd_demux_001:src2_valid -> cmd_mux_002:sink1_valid
wire cmd_demux_001_src2_startofpacket; // cmd_demux_001:src2_startofpacket -> cmd_mux_002:sink1_startofpacket
wire [113:0] cmd_demux_001_src2_data; // cmd_demux_001:src2_data -> cmd_mux_002:sink1_data
wire [2:0] cmd_demux_001_src2_channel; // cmd_demux_001:src2_channel -> cmd_mux_002:sink1_channel
wire cmd_demux_001_src2_ready; // cmd_mux_002:sink1_ready -> cmd_demux_001:src2_ready
wire rsp_demux_src0_endofpacket; // rsp_demux:src0_endofpacket -> rsp_mux:sink0_endofpacket
wire rsp_demux_src0_valid; // rsp_demux:src0_valid -> rsp_mux:sink0_valid
wire rsp_demux_src0_startofpacket; // rsp_demux:src0_startofpacket -> rsp_mux:sink0_startofpacket
wire [113:0] rsp_demux_src0_data; // rsp_demux:src0_data -> rsp_mux:sink0_data
wire [2:0] rsp_demux_src0_channel; // rsp_demux:src0_channel -> rsp_mux:sink0_channel
wire rsp_demux_src0_ready; // rsp_mux:sink0_ready -> rsp_demux:src0_ready
wire rsp_demux_src1_endofpacket; // rsp_demux:src1_endofpacket -> rsp_mux_001:sink0_endofpacket
wire rsp_demux_src1_valid; // rsp_demux:src1_valid -> rsp_mux_001:sink0_valid
wire rsp_demux_src1_startofpacket; // rsp_demux:src1_startofpacket -> rsp_mux_001:sink0_startofpacket
wire [113:0] rsp_demux_src1_data; // rsp_demux:src1_data -> rsp_mux_001:sink0_data
wire [2:0] rsp_demux_src1_channel; // rsp_demux:src1_channel -> rsp_mux_001:sink0_channel
wire rsp_demux_src1_ready; // rsp_mux_001:sink0_ready -> rsp_demux:src1_ready
wire rsp_demux_001_src0_endofpacket; // rsp_demux_001:src0_endofpacket -> rsp_mux:sink1_endofpacket
wire rsp_demux_001_src0_valid; // rsp_demux_001:src0_valid -> rsp_mux:sink1_valid
wire rsp_demux_001_src0_startofpacket; // rsp_demux_001:src0_startofpacket -> rsp_mux:sink1_startofpacket
wire [113:0] rsp_demux_001_src0_data; // rsp_demux_001:src0_data -> rsp_mux:sink1_data
wire [2:0] rsp_demux_001_src0_channel; // rsp_demux_001:src0_channel -> rsp_mux:sink1_channel
wire rsp_demux_001_src0_ready; // rsp_mux:sink1_ready -> rsp_demux_001:src0_ready
wire rsp_demux_001_src1_endofpacket; // rsp_demux_001:src1_endofpacket -> rsp_mux_001:sink1_endofpacket
wire rsp_demux_001_src1_valid; // rsp_demux_001:src1_valid -> rsp_mux_001:sink1_valid
wire rsp_demux_001_src1_startofpacket; // rsp_demux_001:src1_startofpacket -> rsp_mux_001:sink1_startofpacket
wire [113:0] rsp_demux_001_src1_data; // rsp_demux_001:src1_data -> rsp_mux_001:sink1_data
wire [2:0] rsp_demux_001_src1_channel; // rsp_demux_001:src1_channel -> rsp_mux_001:sink1_channel
wire rsp_demux_001_src1_ready; // rsp_mux_001:sink1_ready -> rsp_demux_001:src1_ready
wire rsp_demux_002_src0_endofpacket; // rsp_demux_002:src0_endofpacket -> rsp_mux:sink2_endofpacket
wire rsp_demux_002_src0_valid; // rsp_demux_002:src0_valid -> rsp_mux:sink2_valid
wire rsp_demux_002_src0_startofpacket; // rsp_demux_002:src0_startofpacket -> rsp_mux:sink2_startofpacket
wire [113:0] rsp_demux_002_src0_data; // rsp_demux_002:src0_data -> rsp_mux:sink2_data
wire [2:0] rsp_demux_002_src0_channel; // rsp_demux_002:src0_channel -> rsp_mux:sink2_channel
wire rsp_demux_002_src0_ready; // rsp_mux:sink2_ready -> rsp_demux_002:src0_ready
wire rsp_demux_002_src1_endofpacket; // rsp_demux_002:src1_endofpacket -> rsp_mux_001:sink2_endofpacket
wire rsp_demux_002_src1_valid; // rsp_demux_002:src1_valid -> rsp_mux_001:sink2_valid
wire rsp_demux_002_src1_startofpacket; // rsp_demux_002:src1_startofpacket -> rsp_mux_001:sink2_startofpacket
wire [113:0] rsp_demux_002_src1_data; // rsp_demux_002:src1_data -> rsp_mux_001:sink2_data
wire [2:0] rsp_demux_002_src1_channel; // rsp_demux_002:src1_channel -> rsp_mux_001:sink2_channel
wire rsp_demux_002_src1_ready; // rsp_mux_001:sink2_ready -> rsp_demux_002:src1_ready
wire [2:0] hps_h2f_lw_axi_master_wr_limiter_cmd_valid_data; // hps_h2f_lw_axi_master_wr_limiter:cmd_src_valid -> cmd_demux:sink_valid
wire [2:0] hps_h2f_lw_axi_master_rd_limiter_cmd_valid_data; // hps_h2f_lw_axi_master_rd_limiter:cmd_src_valid -> cmd_demux_001:sink_valid
altera_merlin_slave_translator #(
.AV_ADDRESS_W (1),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (21),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) version_id_s_translator (
.clk (config_clk_out_clk_clk), // clk.clk
.reset (version_id_clk_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (version_id_s_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (version_id_s_agent_m0_burstcount), // .burstcount
.uav_read (version_id_s_agent_m0_read), // .read
.uav_write (version_id_s_agent_m0_write), // .write
.uav_waitrequest (version_id_s_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (version_id_s_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (version_id_s_agent_m0_byteenable), // .byteenable
.uav_readdata (version_id_s_agent_m0_readdata), // .readdata
.uav_writedata (version_id_s_agent_m0_writedata), // .writedata
.uav_lock (version_id_s_agent_m0_lock), // .lock
.uav_debugaccess (version_id_s_agent_m0_debugaccess), // .debugaccess
.av_read (version_id_s_read), // avalon_anti_slave_0.read
.av_readdata (version_id_s_readdata), // .readdata
.av_address (), // (terminated)
.av_write (), // (terminated)
.av_writedata (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponserequest (1'b0), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponserequest (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (14),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (21),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (1),
.USE_WAITREQUEST (1),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (1),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (0),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) acl_kernel_interface_kernel_cntrl_translator (
.clk (config_clk_out_clk_clk), // clk.clk
.reset (version_id_clk_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (acl_kernel_interface_kernel_cntrl_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (acl_kernel_interface_kernel_cntrl_agent_m0_burstcount), // .burstcount
.uav_read (acl_kernel_interface_kernel_cntrl_agent_m0_read), // .read
.uav_write (acl_kernel_interface_kernel_cntrl_agent_m0_write), // .write
.uav_waitrequest (acl_kernel_interface_kernel_cntrl_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (acl_kernel_interface_kernel_cntrl_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (acl_kernel_interface_kernel_cntrl_agent_m0_byteenable), // .byteenable
.uav_readdata (acl_kernel_interface_kernel_cntrl_agent_m0_readdata), // .readdata
.uav_writedata (acl_kernel_interface_kernel_cntrl_agent_m0_writedata), // .writedata
.uav_lock (acl_kernel_interface_kernel_cntrl_agent_m0_lock), // .lock
.uav_debugaccess (acl_kernel_interface_kernel_cntrl_agent_m0_debugaccess), // .debugaccess
.av_address (acl_kernel_interface_kernel_cntrl_address), // avalon_anti_slave_0.address
.av_write (acl_kernel_interface_kernel_cntrl_write), // .write
.av_read (acl_kernel_interface_kernel_cntrl_read), // .read
.av_readdata (acl_kernel_interface_kernel_cntrl_readdata), // .readdata
.av_writedata (acl_kernel_interface_kernel_cntrl_writedata), // .writedata
.av_burstcount (acl_kernel_interface_kernel_cntrl_burstcount), // .burstcount
.av_byteenable (acl_kernel_interface_kernel_cntrl_byteenable), // .byteenable
.av_readdatavalid (acl_kernel_interface_kernel_cntrl_readdatavalid), // .readdatavalid
.av_waitrequest (acl_kernel_interface_kernel_cntrl_waitrequest), // .waitrequest
.av_debugaccess (acl_kernel_interface_kernel_cntrl_debugaccess), // .debugaccess
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponserequest (1'b0), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponserequest (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (11),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (21),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (1),
.USE_WAITREQUEST (1),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (1),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (0),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) acl_kernel_clk_ctrl_translator (
.clk (config_clk_out_clk_clk), // clk.clk
.reset (version_id_clk_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (acl_kernel_clk_ctrl_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (acl_kernel_clk_ctrl_agent_m0_burstcount), // .burstcount
.uav_read (acl_kernel_clk_ctrl_agent_m0_read), // .read
.uav_write (acl_kernel_clk_ctrl_agent_m0_write), // .write
.uav_waitrequest (acl_kernel_clk_ctrl_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (acl_kernel_clk_ctrl_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (acl_kernel_clk_ctrl_agent_m0_byteenable), // .byteenable
.uav_readdata (acl_kernel_clk_ctrl_agent_m0_readdata), // .readdata
.uav_writedata (acl_kernel_clk_ctrl_agent_m0_writedata), // .writedata
.uav_lock (acl_kernel_clk_ctrl_agent_m0_lock), // .lock
.uav_debugaccess (acl_kernel_clk_ctrl_agent_m0_debugaccess), // .debugaccess
.av_address (acl_kernel_clk_ctrl_address), // avalon_anti_slave_0.address
.av_write (acl_kernel_clk_ctrl_write), // .write
.av_read (acl_kernel_clk_ctrl_read), // .read
.av_readdata (acl_kernel_clk_ctrl_readdata), // .readdata
.av_writedata (acl_kernel_clk_ctrl_writedata), // .writedata
.av_burstcount (acl_kernel_clk_ctrl_burstcount), // .burstcount
.av_byteenable (acl_kernel_clk_ctrl_byteenable), // .byteenable
.av_readdatavalid (acl_kernel_clk_ctrl_readdatavalid), // .readdatavalid
.av_waitrequest (acl_kernel_clk_ctrl_waitrequest), // .waitrequest
.av_debugaccess (acl_kernel_clk_ctrl_debugaccess), // .debugaccess
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponserequest (1'b0), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponserequest (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_axi_master_ni #(
.ID_WIDTH (12),
.ADDR_WIDTH (21),
.RDATA_WIDTH (32),
.WDATA_WIDTH (32),
.ADDR_USER_WIDTH (1),
.DATA_USER_WIDTH (1),
.AXI_BURST_LENGTH_WIDTH (4),
.AXI_LOCK_WIDTH (2),
.AXI_VERSION ("AXI3"),
.WRITE_ISSUING_CAPABILITY (8),
.READ_ISSUING_CAPABILITY (8),
.PKT_BEGIN_BURST (84),
.PKT_CACHE_H (108),
.PKT_CACHE_L (105),
.PKT_ADDR_SIDEBAND_H (82),
.PKT_ADDR_SIDEBAND_L (82),
.PKT_PROTECTION_H (104),
.PKT_PROTECTION_L (102),
.PKT_BURST_SIZE_H (79),
.PKT_BURST_SIZE_L (77),
.PKT_BURST_TYPE_H (81),
.PKT_BURST_TYPE_L (80),
.PKT_RESPONSE_STATUS_L (109),
.PKT_RESPONSE_STATUS_H (110),
.PKT_BURSTWRAP_H (76),
.PKT_BURSTWRAP_L (70),
.PKT_BYTE_CNT_H (69),
.PKT_BYTE_CNT_L (63),
.PKT_ADDR_H (56),
.PKT_ADDR_L (36),
.PKT_TRANS_EXCLUSIVE (62),
.PKT_TRANS_LOCK (61),
.PKT_TRANS_COMPRESSED_READ (57),
.PKT_TRANS_POSTED (58),
.PKT_TRANS_WRITE (59),
.PKT_TRANS_READ (60),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (87),
.PKT_SRC_ID_L (86),
.PKT_DEST_ID_H (89),
.PKT_DEST_ID_L (88),
.PKT_THREAD_ID_H (101),
.PKT_THREAD_ID_L (90),
.PKT_QOS_L (85),
.PKT_QOS_H (85),
.PKT_ORI_BURST_SIZE_L (111),
.PKT_ORI_BURST_SIZE_H (113),
.PKT_DATA_SIDEBAND_H (83),
.PKT_DATA_SIDEBAND_L (83),
.ST_DATA_W (114),
.ST_CHANNEL_W (3),
.ID (0)
) hps_h2f_lw_axi_master_agent (
.aclk (config_clk_out_clk_clk), // clk.clk
.aresetn (~hps_h2f_lw_axi_master_agent_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset_n
.write_cp_valid (hps_h2f_lw_axi_master_agent_write_cp_valid), // write_cp.valid
.write_cp_data (hps_h2f_lw_axi_master_agent_write_cp_data), // .data
.write_cp_startofpacket (hps_h2f_lw_axi_master_agent_write_cp_startofpacket), // .startofpacket
.write_cp_endofpacket (hps_h2f_lw_axi_master_agent_write_cp_endofpacket), // .endofpacket
.write_cp_ready (hps_h2f_lw_axi_master_agent_write_cp_ready), // .ready
.write_rp_valid (hps_h2f_lw_axi_master_wr_limiter_rsp_src_valid), // write_rp.valid
.write_rp_data (hps_h2f_lw_axi_master_wr_limiter_rsp_src_data), // .data
.write_rp_channel (hps_h2f_lw_axi_master_wr_limiter_rsp_src_channel), // .channel
.write_rp_startofpacket (hps_h2f_lw_axi_master_wr_limiter_rsp_src_startofpacket), // .startofpacket
.write_rp_endofpacket (hps_h2f_lw_axi_master_wr_limiter_rsp_src_endofpacket), // .endofpacket
.write_rp_ready (hps_h2f_lw_axi_master_wr_limiter_rsp_src_ready), // .ready
.read_cp_valid (hps_h2f_lw_axi_master_agent_read_cp_valid), // read_cp.valid
.read_cp_data (hps_h2f_lw_axi_master_agent_read_cp_data), // .data
.read_cp_startofpacket (hps_h2f_lw_axi_master_agent_read_cp_startofpacket), // .startofpacket
.read_cp_endofpacket (hps_h2f_lw_axi_master_agent_read_cp_endofpacket), // .endofpacket
.read_cp_ready (hps_h2f_lw_axi_master_agent_read_cp_ready), // .ready
.read_rp_valid (hps_h2f_lw_axi_master_rd_limiter_rsp_src_valid), // read_rp.valid
.read_rp_data (hps_h2f_lw_axi_master_rd_limiter_rsp_src_data), // .data
.read_rp_channel (hps_h2f_lw_axi_master_rd_limiter_rsp_src_channel), // .channel
.read_rp_startofpacket (hps_h2f_lw_axi_master_rd_limiter_rsp_src_startofpacket), // .startofpacket
.read_rp_endofpacket (hps_h2f_lw_axi_master_rd_limiter_rsp_src_endofpacket), // .endofpacket
.read_rp_ready (hps_h2f_lw_axi_master_rd_limiter_rsp_src_ready), // .ready
.awid (hps_h2f_lw_axi_master_awid), // altera_axi_slave.awid
.awaddr (hps_h2f_lw_axi_master_awaddr), // .awaddr
.awlen (hps_h2f_lw_axi_master_awlen), // .awlen
.awsize (hps_h2f_lw_axi_master_awsize), // .awsize
.awburst (hps_h2f_lw_axi_master_awburst), // .awburst
.awlock (hps_h2f_lw_axi_master_awlock), // .awlock
.awcache (hps_h2f_lw_axi_master_awcache), // .awcache
.awprot (hps_h2f_lw_axi_master_awprot), // .awprot
.awvalid (hps_h2f_lw_axi_master_awvalid), // .awvalid
.awready (hps_h2f_lw_axi_master_awready), // .awready
.wid (hps_h2f_lw_axi_master_wid), // .wid
.wdata (hps_h2f_lw_axi_master_wdata), // .wdata
.wstrb (hps_h2f_lw_axi_master_wstrb), // .wstrb
.wlast (hps_h2f_lw_axi_master_wlast), // .wlast
.wvalid (hps_h2f_lw_axi_master_wvalid), // .wvalid
.wready (hps_h2f_lw_axi_master_wready), // .wready
.bid (hps_h2f_lw_axi_master_bid), // .bid
.bresp (hps_h2f_lw_axi_master_bresp), // .bresp
.bvalid (hps_h2f_lw_axi_master_bvalid), // .bvalid
.bready (hps_h2f_lw_axi_master_bready), // .bready
.arid (hps_h2f_lw_axi_master_arid), // .arid
.araddr (hps_h2f_lw_axi_master_araddr), // .araddr
.arlen (hps_h2f_lw_axi_master_arlen), // .arlen
.arsize (hps_h2f_lw_axi_master_arsize), // .arsize
.arburst (hps_h2f_lw_axi_master_arburst), // .arburst
.arlock (hps_h2f_lw_axi_master_arlock), // .arlock
.arcache (hps_h2f_lw_axi_master_arcache), // .arcache
.arprot (hps_h2f_lw_axi_master_arprot), // .arprot
.arvalid (hps_h2f_lw_axi_master_arvalid), // .arvalid
.arready (hps_h2f_lw_axi_master_arready), // .arready
.rid (hps_h2f_lw_axi_master_rid), // .rid
.rdata (hps_h2f_lw_axi_master_rdata), // .rdata
.rresp (hps_h2f_lw_axi_master_rresp), // .rresp
.rlast (hps_h2f_lw_axi_master_rlast), // .rlast
.rvalid (hps_h2f_lw_axi_master_rvalid), // .rvalid
.rready (hps_h2f_lw_axi_master_rready), // .rready
.awuser (1'b0), // (terminated)
.aruser (1'b0), // (terminated)
.awqos (4'b0000), // (terminated)
.arqos (4'b0000), // (terminated)
.awregion (4'b0000), // (terminated)
.arregion (4'b0000), // (terminated)
.wuser (1'b0), // (terminated)
.ruser (), // (terminated)
.buser () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BEGIN_BURST (84),
.PKT_SYMBOL_W (8),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_ADDR_H (56),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (57),
.PKT_TRANS_POSTED (58),
.PKT_TRANS_WRITE (59),
.PKT_TRANS_READ (60),
.PKT_TRANS_LOCK (61),
.PKT_SRC_ID_H (87),
.PKT_SRC_ID_L (86),
.PKT_DEST_ID_H (89),
.PKT_DEST_ID_L (88),
.PKT_BURSTWRAP_H (76),
.PKT_BURSTWRAP_L (70),
.PKT_BYTE_CNT_H (69),
.PKT_BYTE_CNT_L (63),
.PKT_PROTECTION_H (104),
.PKT_PROTECTION_L (102),
.PKT_RESPONSE_STATUS_H (110),
.PKT_RESPONSE_STATUS_L (109),
.PKT_BURST_SIZE_H (79),
.PKT_BURST_SIZE_L (77),
.PKT_ORI_BURST_SIZE_L (111),
.PKT_ORI_BURST_SIZE_H (113),
.ST_CHANNEL_W (3),
.ST_DATA_W (114),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (1),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) version_id_s_agent (
.clk (config_clk_out_clk_clk), // clk.clk
.reset (version_id_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (version_id_s_agent_m0_address), // m0.address
.m0_burstcount (version_id_s_agent_m0_burstcount), // .burstcount
.m0_byteenable (version_id_s_agent_m0_byteenable), // .byteenable
.m0_debugaccess (version_id_s_agent_m0_debugaccess), // .debugaccess
.m0_lock (version_id_s_agent_m0_lock), // .lock
.m0_readdata (version_id_s_agent_m0_readdata), // .readdata
.m0_readdatavalid (version_id_s_agent_m0_readdatavalid), // .readdatavalid
.m0_read (version_id_s_agent_m0_read), // .read
.m0_waitrequest (version_id_s_agent_m0_waitrequest), // .waitrequest
.m0_writedata (version_id_s_agent_m0_writedata), // .writedata
.m0_write (version_id_s_agent_m0_write), // .write
.rp_endofpacket (version_id_s_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (version_id_s_agent_rp_ready), // .ready
.rp_valid (version_id_s_agent_rp_valid), // .valid
.rp_data (version_id_s_agent_rp_data), // .data
.rp_startofpacket (version_id_s_agent_rp_startofpacket), // .startofpacket
.cp_ready (version_id_s_burst_adapter_source0_ready), // cp.ready
.cp_valid (version_id_s_burst_adapter_source0_valid), // .valid
.cp_data (version_id_s_burst_adapter_source0_data), // .data
.cp_startofpacket (version_id_s_burst_adapter_source0_startofpacket), // .startofpacket
.cp_endofpacket (version_id_s_burst_adapter_source0_endofpacket), // .endofpacket
.cp_channel (version_id_s_burst_adapter_source0_channel), // .channel
.rf_sink_ready (version_id_s_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (version_id_s_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (version_id_s_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (version_id_s_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (version_id_s_agent_rsp_fifo_out_data), // .data
.rf_source_ready (version_id_s_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (version_id_s_agent_rf_source_valid), // .valid
.rf_source_startofpacket (version_id_s_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (version_id_s_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (version_id_s_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (version_id_s_agent_rdata_fifo_out_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (version_id_s_agent_rdata_fifo_out_valid), // .valid
.rdata_fifo_sink_data (version_id_s_agent_rdata_fifo_out_data), // .data
.rdata_fifo_src_ready (version_id_s_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (version_id_s_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (version_id_s_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponserequest (), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (115),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) version_id_s_agent_rsp_fifo (
.clk (config_clk_out_clk_clk), // clk.clk
.reset (version_id_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (version_id_s_agent_rf_source_data), // in.data
.in_valid (version_id_s_agent_rf_source_valid), // .valid
.in_ready (version_id_s_agent_rf_source_ready), // .ready
.in_startofpacket (version_id_s_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (version_id_s_agent_rf_source_endofpacket), // .endofpacket
.out_data (version_id_s_agent_rsp_fifo_out_data), // out.data
.out_valid (version_id_s_agent_rsp_fifo_out_valid), // .valid
.out_ready (version_id_s_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (version_id_s_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (version_id_s_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (34),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (0),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (0),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) version_id_s_agent_rdata_fifo (
.clk (config_clk_out_clk_clk), // clk.clk
.reset (version_id_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (version_id_s_agent_rdata_fifo_src_data), // in.data
.in_valid (version_id_s_agent_rdata_fifo_src_valid), // .valid
.in_ready (version_id_s_agent_rdata_fifo_src_ready), // .ready
.out_data (version_id_s_agent_rdata_fifo_out_data), // out.data
.out_valid (version_id_s_agent_rdata_fifo_out_valid), // .valid
.out_ready (version_id_s_agent_rdata_fifo_out_ready), // .ready
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_startofpacket (1'b0), // (terminated)
.in_endofpacket (1'b0), // (terminated)
.out_startofpacket (), // (terminated)
.out_endofpacket (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BEGIN_BURST (84),
.PKT_SYMBOL_W (8),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_ADDR_H (56),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (57),
.PKT_TRANS_POSTED (58),
.PKT_TRANS_WRITE (59),
.PKT_TRANS_READ (60),
.PKT_TRANS_LOCK (61),
.PKT_SRC_ID_H (87),
.PKT_SRC_ID_L (86),
.PKT_DEST_ID_H (89),
.PKT_DEST_ID_L (88),
.PKT_BURSTWRAP_H (76),
.PKT_BURSTWRAP_L (70),
.PKT_BYTE_CNT_H (69),
.PKT_BYTE_CNT_L (63),
.PKT_PROTECTION_H (104),
.PKT_PROTECTION_L (102),
.PKT_RESPONSE_STATUS_H (110),
.PKT_RESPONSE_STATUS_L (109),
.PKT_BURST_SIZE_H (79),
.PKT_BURST_SIZE_L (77),
.PKT_ORI_BURST_SIZE_L (111),
.PKT_ORI_BURST_SIZE_H (113),
.ST_CHANNEL_W (3),
.ST_DATA_W (114),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (1),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) acl_kernel_interface_kernel_cntrl_agent (
.clk (config_clk_out_clk_clk), // clk.clk
.reset (version_id_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (acl_kernel_interface_kernel_cntrl_agent_m0_address), // m0.address
.m0_burstcount (acl_kernel_interface_kernel_cntrl_agent_m0_burstcount), // .burstcount
.m0_byteenable (acl_kernel_interface_kernel_cntrl_agent_m0_byteenable), // .byteenable
.m0_debugaccess (acl_kernel_interface_kernel_cntrl_agent_m0_debugaccess), // .debugaccess
.m0_lock (acl_kernel_interface_kernel_cntrl_agent_m0_lock), // .lock
.m0_readdata (acl_kernel_interface_kernel_cntrl_agent_m0_readdata), // .readdata
.m0_readdatavalid (acl_kernel_interface_kernel_cntrl_agent_m0_readdatavalid), // .readdatavalid
.m0_read (acl_kernel_interface_kernel_cntrl_agent_m0_read), // .read
.m0_waitrequest (acl_kernel_interface_kernel_cntrl_agent_m0_waitrequest), // .waitrequest
.m0_writedata (acl_kernel_interface_kernel_cntrl_agent_m0_writedata), // .writedata
.m0_write (acl_kernel_interface_kernel_cntrl_agent_m0_write), // .write
.rp_endofpacket (acl_kernel_interface_kernel_cntrl_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (acl_kernel_interface_kernel_cntrl_agent_rp_ready), // .ready
.rp_valid (acl_kernel_interface_kernel_cntrl_agent_rp_valid), // .valid
.rp_data (acl_kernel_interface_kernel_cntrl_agent_rp_data), // .data
.rp_startofpacket (acl_kernel_interface_kernel_cntrl_agent_rp_startofpacket), // .startofpacket
.cp_ready (acl_kernel_interface_kernel_cntrl_burst_adapter_source0_ready), // cp.ready
.cp_valid (acl_kernel_interface_kernel_cntrl_burst_adapter_source0_valid), // .valid
.cp_data (acl_kernel_interface_kernel_cntrl_burst_adapter_source0_data), // .data
.cp_startofpacket (acl_kernel_interface_kernel_cntrl_burst_adapter_source0_startofpacket), // .startofpacket
.cp_endofpacket (acl_kernel_interface_kernel_cntrl_burst_adapter_source0_endofpacket), // .endofpacket
.cp_channel (acl_kernel_interface_kernel_cntrl_burst_adapter_source0_channel), // .channel
.rf_sink_ready (acl_kernel_interface_kernel_cntrl_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (acl_kernel_interface_kernel_cntrl_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (acl_kernel_interface_kernel_cntrl_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (acl_kernel_interface_kernel_cntrl_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (acl_kernel_interface_kernel_cntrl_agent_rsp_fifo_out_data), // .data
.rf_source_ready (acl_kernel_interface_kernel_cntrl_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (acl_kernel_interface_kernel_cntrl_agent_rf_source_valid), // .valid
.rf_source_startofpacket (acl_kernel_interface_kernel_cntrl_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (acl_kernel_interface_kernel_cntrl_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (acl_kernel_interface_kernel_cntrl_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (acl_kernel_interface_kernel_cntrl_agent_rdata_fifo_out_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (acl_kernel_interface_kernel_cntrl_agent_rdata_fifo_out_valid), // .valid
.rdata_fifo_sink_data (acl_kernel_interface_kernel_cntrl_agent_rdata_fifo_out_data), // .data
.rdata_fifo_src_ready (acl_kernel_interface_kernel_cntrl_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (acl_kernel_interface_kernel_cntrl_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (acl_kernel_interface_kernel_cntrl_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponserequest (), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (115),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) acl_kernel_interface_kernel_cntrl_agent_rsp_fifo (
.clk (config_clk_out_clk_clk), // clk.clk
.reset (version_id_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (acl_kernel_interface_kernel_cntrl_agent_rf_source_data), // in.data
.in_valid (acl_kernel_interface_kernel_cntrl_agent_rf_source_valid), // .valid
.in_ready (acl_kernel_interface_kernel_cntrl_agent_rf_source_ready), // .ready
.in_startofpacket (acl_kernel_interface_kernel_cntrl_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (acl_kernel_interface_kernel_cntrl_agent_rf_source_endofpacket), // .endofpacket
.out_data (acl_kernel_interface_kernel_cntrl_agent_rsp_fifo_out_data), // out.data
.out_valid (acl_kernel_interface_kernel_cntrl_agent_rsp_fifo_out_valid), // .valid
.out_ready (acl_kernel_interface_kernel_cntrl_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (acl_kernel_interface_kernel_cntrl_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (acl_kernel_interface_kernel_cntrl_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (34),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (0),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (0),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) acl_kernel_interface_kernel_cntrl_agent_rdata_fifo (
.clk (config_clk_out_clk_clk), // clk.clk
.reset (version_id_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (acl_kernel_interface_kernel_cntrl_agent_rdata_fifo_src_data), // in.data
.in_valid (acl_kernel_interface_kernel_cntrl_agent_rdata_fifo_src_valid), // .valid
.in_ready (acl_kernel_interface_kernel_cntrl_agent_rdata_fifo_src_ready), // .ready
.out_data (acl_kernel_interface_kernel_cntrl_agent_rdata_fifo_out_data), // out.data
.out_valid (acl_kernel_interface_kernel_cntrl_agent_rdata_fifo_out_valid), // .valid
.out_ready (acl_kernel_interface_kernel_cntrl_agent_rdata_fifo_out_ready), // .ready
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_startofpacket (1'b0), // (terminated)
.in_endofpacket (1'b0), // (terminated)
.out_startofpacket (), // (terminated)
.out_endofpacket (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BEGIN_BURST (84),
.PKT_SYMBOL_W (8),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_ADDR_H (56),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (57),
.PKT_TRANS_POSTED (58),
.PKT_TRANS_WRITE (59),
.PKT_TRANS_READ (60),
.PKT_TRANS_LOCK (61),
.PKT_SRC_ID_H (87),
.PKT_SRC_ID_L (86),
.PKT_DEST_ID_H (89),
.PKT_DEST_ID_L (88),
.PKT_BURSTWRAP_H (76),
.PKT_BURSTWRAP_L (70),
.PKT_BYTE_CNT_H (69),
.PKT_BYTE_CNT_L (63),
.PKT_PROTECTION_H (104),
.PKT_PROTECTION_L (102),
.PKT_RESPONSE_STATUS_H (110),
.PKT_RESPONSE_STATUS_L (109),
.PKT_BURST_SIZE_H (79),
.PKT_BURST_SIZE_L (77),
.PKT_ORI_BURST_SIZE_L (111),
.PKT_ORI_BURST_SIZE_H (113),
.ST_CHANNEL_W (3),
.ST_DATA_W (114),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (1),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) acl_kernel_clk_ctrl_agent (
.clk (config_clk_out_clk_clk), // clk.clk
.reset (version_id_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (acl_kernel_clk_ctrl_agent_m0_address), // m0.address
.m0_burstcount (acl_kernel_clk_ctrl_agent_m0_burstcount), // .burstcount
.m0_byteenable (acl_kernel_clk_ctrl_agent_m0_byteenable), // .byteenable
.m0_debugaccess (acl_kernel_clk_ctrl_agent_m0_debugaccess), // .debugaccess
.m0_lock (acl_kernel_clk_ctrl_agent_m0_lock), // .lock
.m0_readdata (acl_kernel_clk_ctrl_agent_m0_readdata), // .readdata
.m0_readdatavalid (acl_kernel_clk_ctrl_agent_m0_readdatavalid), // .readdatavalid
.m0_read (acl_kernel_clk_ctrl_agent_m0_read), // .read
.m0_waitrequest (acl_kernel_clk_ctrl_agent_m0_waitrequest), // .waitrequest
.m0_writedata (acl_kernel_clk_ctrl_agent_m0_writedata), // .writedata
.m0_write (acl_kernel_clk_ctrl_agent_m0_write), // .write
.rp_endofpacket (acl_kernel_clk_ctrl_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (acl_kernel_clk_ctrl_agent_rp_ready), // .ready
.rp_valid (acl_kernel_clk_ctrl_agent_rp_valid), // .valid
.rp_data (acl_kernel_clk_ctrl_agent_rp_data), // .data
.rp_startofpacket (acl_kernel_clk_ctrl_agent_rp_startofpacket), // .startofpacket
.cp_ready (acl_kernel_clk_ctrl_burst_adapter_source0_ready), // cp.ready
.cp_valid (acl_kernel_clk_ctrl_burst_adapter_source0_valid), // .valid
.cp_data (acl_kernel_clk_ctrl_burst_adapter_source0_data), // .data
.cp_startofpacket (acl_kernel_clk_ctrl_burst_adapter_source0_startofpacket), // .startofpacket
.cp_endofpacket (acl_kernel_clk_ctrl_burst_adapter_source0_endofpacket), // .endofpacket
.cp_channel (acl_kernel_clk_ctrl_burst_adapter_source0_channel), // .channel
.rf_sink_ready (acl_kernel_clk_ctrl_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (acl_kernel_clk_ctrl_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (acl_kernel_clk_ctrl_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (acl_kernel_clk_ctrl_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (acl_kernel_clk_ctrl_agent_rsp_fifo_out_data), // .data
.rf_source_ready (acl_kernel_clk_ctrl_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (acl_kernel_clk_ctrl_agent_rf_source_valid), // .valid
.rf_source_startofpacket (acl_kernel_clk_ctrl_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (acl_kernel_clk_ctrl_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (acl_kernel_clk_ctrl_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (acl_kernel_clk_ctrl_agent_rdata_fifo_out_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (acl_kernel_clk_ctrl_agent_rdata_fifo_out_valid), // .valid
.rdata_fifo_sink_data (acl_kernel_clk_ctrl_agent_rdata_fifo_out_data), // .data
.rdata_fifo_src_ready (acl_kernel_clk_ctrl_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (acl_kernel_clk_ctrl_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (acl_kernel_clk_ctrl_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponserequest (), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (115),
.FIFO_DEPTH (5),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) acl_kernel_clk_ctrl_agent_rsp_fifo (
.clk (config_clk_out_clk_clk), // clk.clk
.reset (version_id_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (acl_kernel_clk_ctrl_agent_rf_source_data), // in.data
.in_valid (acl_kernel_clk_ctrl_agent_rf_source_valid), // .valid
.in_ready (acl_kernel_clk_ctrl_agent_rf_source_ready), // .ready
.in_startofpacket (acl_kernel_clk_ctrl_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (acl_kernel_clk_ctrl_agent_rf_source_endofpacket), // .endofpacket
.out_data (acl_kernel_clk_ctrl_agent_rsp_fifo_out_data), // out.data
.out_valid (acl_kernel_clk_ctrl_agent_rsp_fifo_out_valid), // .valid
.out_ready (acl_kernel_clk_ctrl_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (acl_kernel_clk_ctrl_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (acl_kernel_clk_ctrl_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (34),
.FIFO_DEPTH (8),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (0),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (3),
.USE_MEMORY_BLOCKS (1),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) acl_kernel_clk_ctrl_agent_rdata_fifo (
.clk (config_clk_out_clk_clk), // clk.clk
.reset (version_id_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (acl_kernel_clk_ctrl_agent_rdata_fifo_src_data), // in.data
.in_valid (acl_kernel_clk_ctrl_agent_rdata_fifo_src_valid), // .valid
.in_ready (acl_kernel_clk_ctrl_agent_rdata_fifo_src_ready), // .ready
.out_data (acl_kernel_clk_ctrl_agent_rdata_fifo_out_data), // out.data
.out_valid (acl_kernel_clk_ctrl_agent_rdata_fifo_out_valid), // .valid
.out_ready (acl_kernel_clk_ctrl_agent_rdata_fifo_out_ready), // .ready
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_startofpacket (1'b0), // (terminated)
.in_endofpacket (1'b0), // (terminated)
.out_startofpacket (), // (terminated)
.out_endofpacket (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
system_acl_iface_mm_interconnect_0_router router (
.sink_ready (hps_h2f_lw_axi_master_agent_write_cp_ready), // sink.ready
.sink_valid (hps_h2f_lw_axi_master_agent_write_cp_valid), // .valid
.sink_data (hps_h2f_lw_axi_master_agent_write_cp_data), // .data
.sink_startofpacket (hps_h2f_lw_axi_master_agent_write_cp_startofpacket), // .startofpacket
.sink_endofpacket (hps_h2f_lw_axi_master_agent_write_cp_endofpacket), // .endofpacket
.clk (config_clk_out_clk_clk), // clk.clk
.reset (hps_h2f_lw_axi_master_agent_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_src_ready), // src.ready
.src_valid (router_src_valid), // .valid
.src_data (router_src_data), // .data
.src_channel (router_src_channel), // .channel
.src_startofpacket (router_src_startofpacket), // .startofpacket
.src_endofpacket (router_src_endofpacket) // .endofpacket
);
system_acl_iface_mm_interconnect_0_router router_001 (
.sink_ready (hps_h2f_lw_axi_master_agent_read_cp_ready), // sink.ready
.sink_valid (hps_h2f_lw_axi_master_agent_read_cp_valid), // .valid
.sink_data (hps_h2f_lw_axi_master_agent_read_cp_data), // .data
.sink_startofpacket (hps_h2f_lw_axi_master_agent_read_cp_startofpacket), // .startofpacket
.sink_endofpacket (hps_h2f_lw_axi_master_agent_read_cp_endofpacket), // .endofpacket
.clk (config_clk_out_clk_clk), // clk.clk
.reset (hps_h2f_lw_axi_master_agent_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_001_src_ready), // src.ready
.src_valid (router_001_src_valid), // .valid
.src_data (router_001_src_data), // .data
.src_channel (router_001_src_channel), // .channel
.src_startofpacket (router_001_src_startofpacket), // .startofpacket
.src_endofpacket (router_001_src_endofpacket) // .endofpacket
);
system_acl_iface_mm_interconnect_0_router_002 router_002 (
.sink_ready (version_id_s_agent_rp_ready), // sink.ready
.sink_valid (version_id_s_agent_rp_valid), // .valid
.sink_data (version_id_s_agent_rp_data), // .data
.sink_startofpacket (version_id_s_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (version_id_s_agent_rp_endofpacket), // .endofpacket
.clk (config_clk_out_clk_clk), // clk.clk
.reset (version_id_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_002_src_ready), // src.ready
.src_valid (router_002_src_valid), // .valid
.src_data (router_002_src_data), // .data
.src_channel (router_002_src_channel), // .channel
.src_startofpacket (router_002_src_startofpacket), // .startofpacket
.src_endofpacket (router_002_src_endofpacket) // .endofpacket
);
system_acl_iface_mm_interconnect_0_router_002 router_003 (
.sink_ready (acl_kernel_interface_kernel_cntrl_agent_rp_ready), // sink.ready
.sink_valid (acl_kernel_interface_kernel_cntrl_agent_rp_valid), // .valid
.sink_data (acl_kernel_interface_kernel_cntrl_agent_rp_data), // .data
.sink_startofpacket (acl_kernel_interface_kernel_cntrl_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (acl_kernel_interface_kernel_cntrl_agent_rp_endofpacket), // .endofpacket
.clk (config_clk_out_clk_clk), // clk.clk
.reset (version_id_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_003_src_ready), // src.ready
.src_valid (router_003_src_valid), // .valid
.src_data (router_003_src_data), // .data
.src_channel (router_003_src_channel), // .channel
.src_startofpacket (router_003_src_startofpacket), // .startofpacket
.src_endofpacket (router_003_src_endofpacket) // .endofpacket
);
system_acl_iface_mm_interconnect_0_router_002 router_004 (
.sink_ready (acl_kernel_clk_ctrl_agent_rp_ready), // sink.ready
.sink_valid (acl_kernel_clk_ctrl_agent_rp_valid), // .valid
.sink_data (acl_kernel_clk_ctrl_agent_rp_data), // .data
.sink_startofpacket (acl_kernel_clk_ctrl_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (acl_kernel_clk_ctrl_agent_rp_endofpacket), // .endofpacket
.clk (config_clk_out_clk_clk), // clk.clk
.reset (version_id_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_004_src_ready), // src.ready
.src_valid (router_004_src_valid), // .valid
.src_data (router_004_src_data), // .data
.src_channel (router_004_src_channel), // .channel
.src_startofpacket (router_004_src_startofpacket), // .startofpacket
.src_endofpacket (router_004_src_endofpacket) // .endofpacket
);
altera_merlin_traffic_limiter #(
.PKT_DEST_ID_H (89),
.PKT_DEST_ID_L (88),
.PKT_SRC_ID_H (87),
.PKT_SRC_ID_L (86),
.PKT_TRANS_POSTED (58),
.PKT_TRANS_WRITE (59),
.MAX_OUTSTANDING_RESPONSES (6),
.PIPELINED (0),
.ST_DATA_W (114),
.ST_CHANNEL_W (3),
.VALID_WIDTH (3),
.ENFORCE_ORDER (1),
.PREVENT_HAZARDS (0),
.PKT_BYTE_CNT_H (69),
.PKT_BYTE_CNT_L (63),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.REORDER (0)
) hps_h2f_lw_axi_master_wr_limiter (
.clk (config_clk_out_clk_clk), // clk.clk
.reset (hps_h2f_lw_axi_master_agent_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.cmd_sink_ready (router_src_ready), // cmd_sink.ready
.cmd_sink_valid (router_src_valid), // .valid
.cmd_sink_data (router_src_data), // .data
.cmd_sink_channel (router_src_channel), // .channel
.cmd_sink_startofpacket (router_src_startofpacket), // .startofpacket
.cmd_sink_endofpacket (router_src_endofpacket), // .endofpacket
.cmd_src_ready (hps_h2f_lw_axi_master_wr_limiter_cmd_src_ready), // cmd_src.ready
.cmd_src_data (hps_h2f_lw_axi_master_wr_limiter_cmd_src_data), // .data
.cmd_src_channel (hps_h2f_lw_axi_master_wr_limiter_cmd_src_channel), // .channel
.cmd_src_startofpacket (hps_h2f_lw_axi_master_wr_limiter_cmd_src_startofpacket), // .startofpacket
.cmd_src_endofpacket (hps_h2f_lw_axi_master_wr_limiter_cmd_src_endofpacket), // .endofpacket
.rsp_sink_ready (rsp_mux_src_ready), // rsp_sink.ready
.rsp_sink_valid (rsp_mux_src_valid), // .valid
.rsp_sink_channel (rsp_mux_src_channel), // .channel
.rsp_sink_data (rsp_mux_src_data), // .data
.rsp_sink_startofpacket (rsp_mux_src_startofpacket), // .startofpacket
.rsp_sink_endofpacket (rsp_mux_src_endofpacket), // .endofpacket
.rsp_src_ready (hps_h2f_lw_axi_master_wr_limiter_rsp_src_ready), // rsp_src.ready
.rsp_src_valid (hps_h2f_lw_axi_master_wr_limiter_rsp_src_valid), // .valid
.rsp_src_data (hps_h2f_lw_axi_master_wr_limiter_rsp_src_data), // .data
.rsp_src_channel (hps_h2f_lw_axi_master_wr_limiter_rsp_src_channel), // .channel
.rsp_src_startofpacket (hps_h2f_lw_axi_master_wr_limiter_rsp_src_startofpacket), // .startofpacket
.rsp_src_endofpacket (hps_h2f_lw_axi_master_wr_limiter_rsp_src_endofpacket), // .endofpacket
.cmd_src_valid (hps_h2f_lw_axi_master_wr_limiter_cmd_valid_data) // cmd_valid.data
);
altera_merlin_traffic_limiter #(
.PKT_DEST_ID_H (89),
.PKT_DEST_ID_L (88),
.PKT_SRC_ID_H (87),
.PKT_SRC_ID_L (86),
.PKT_TRANS_POSTED (58),
.PKT_TRANS_WRITE (59),
.MAX_OUTSTANDING_RESPONSES (6),
.PIPELINED (0),
.ST_DATA_W (114),
.ST_CHANNEL_W (3),
.VALID_WIDTH (3),
.ENFORCE_ORDER (1),
.PREVENT_HAZARDS (0),
.PKT_BYTE_CNT_H (69),
.PKT_BYTE_CNT_L (63),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.REORDER (0)
) hps_h2f_lw_axi_master_rd_limiter (
.clk (config_clk_out_clk_clk), // clk.clk
.reset (hps_h2f_lw_axi_master_agent_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.cmd_sink_ready (router_001_src_ready), // cmd_sink.ready
.cmd_sink_valid (router_001_src_valid), // .valid
.cmd_sink_data (router_001_src_data), // .data
.cmd_sink_channel (router_001_src_channel), // .channel
.cmd_sink_startofpacket (router_001_src_startofpacket), // .startofpacket
.cmd_sink_endofpacket (router_001_src_endofpacket), // .endofpacket
.cmd_src_ready (hps_h2f_lw_axi_master_rd_limiter_cmd_src_ready), // cmd_src.ready
.cmd_src_data (hps_h2f_lw_axi_master_rd_limiter_cmd_src_data), // .data
.cmd_src_channel (hps_h2f_lw_axi_master_rd_limiter_cmd_src_channel), // .channel
.cmd_src_startofpacket (hps_h2f_lw_axi_master_rd_limiter_cmd_src_startofpacket), // .startofpacket
.cmd_src_endofpacket (hps_h2f_lw_axi_master_rd_limiter_cmd_src_endofpacket), // .endofpacket
.rsp_sink_ready (rsp_mux_001_src_ready), // rsp_sink.ready
.rsp_sink_valid (rsp_mux_001_src_valid), // .valid
.rsp_sink_channel (rsp_mux_001_src_channel), // .channel
.rsp_sink_data (rsp_mux_001_src_data), // .data
.rsp_sink_startofpacket (rsp_mux_001_src_startofpacket), // .startofpacket
.rsp_sink_endofpacket (rsp_mux_001_src_endofpacket), // .endofpacket
.rsp_src_ready (hps_h2f_lw_axi_master_rd_limiter_rsp_src_ready), // rsp_src.ready
.rsp_src_valid (hps_h2f_lw_axi_master_rd_limiter_rsp_src_valid), // .valid
.rsp_src_data (hps_h2f_lw_axi_master_rd_limiter_rsp_src_data), // .data
.rsp_src_channel (hps_h2f_lw_axi_master_rd_limiter_rsp_src_channel), // .channel
.rsp_src_startofpacket (hps_h2f_lw_axi_master_rd_limiter_rsp_src_startofpacket), // .startofpacket
.rsp_src_endofpacket (hps_h2f_lw_axi_master_rd_limiter_rsp_src_endofpacket), // .endofpacket
.cmd_src_valid (hps_h2f_lw_axi_master_rd_limiter_cmd_valid_data) // cmd_valid.data
);
altera_merlin_burst_adapter #(
.PKT_ADDR_H (56),
.PKT_ADDR_L (36),
.PKT_BEGIN_BURST (84),
.PKT_BYTE_CNT_H (69),
.PKT_BYTE_CNT_L (63),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_BURST_SIZE_H (79),
.PKT_BURST_SIZE_L (77),
.PKT_BURST_TYPE_H (81),
.PKT_BURST_TYPE_L (80),
.PKT_BURSTWRAP_H (76),
.PKT_BURSTWRAP_L (70),
.PKT_TRANS_COMPRESSED_READ (57),
.PKT_TRANS_WRITE (59),
.PKT_TRANS_READ (60),
.OUT_NARROW_SIZE (0),
.IN_NARROW_SIZE (1),
.OUT_FIXED (0),
.OUT_COMPLETE_WRAP (0),
.ST_DATA_W (114),
.ST_CHANNEL_W (3),
.OUT_BYTE_CNT_H (65),
.OUT_BURSTWRAP_H (76),
.COMPRESSED_READ_SUPPORT (1),
.BYTEENABLE_SYNTHESIS (1),
.PIPE_INPUTS (0),
.NO_WRAP_SUPPORT (0),
.INCOMPLETE_WRAP_SUPPORT (0),
.BURSTWRAP_CONST_MASK (0),
.BURSTWRAP_CONST_VALUE (0),
.ADAPTER_VERSION ("13.1")
) version_id_s_burst_adapter (
.clk (config_clk_out_clk_clk), // cr0.clk
.reset (version_id_clk_reset_reset_bridge_in_reset_reset), // cr0_reset.reset
.sink0_valid (cmd_mux_src_valid), // sink0.valid
.sink0_data (cmd_mux_src_data), // .data
.sink0_channel (cmd_mux_src_channel), // .channel
.sink0_startofpacket (cmd_mux_src_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_mux_src_endofpacket), // .endofpacket
.sink0_ready (cmd_mux_src_ready), // .ready
.source0_valid (version_id_s_burst_adapter_source0_valid), // source0.valid
.source0_data (version_id_s_burst_adapter_source0_data), // .data
.source0_channel (version_id_s_burst_adapter_source0_channel), // .channel
.source0_startofpacket (version_id_s_burst_adapter_source0_startofpacket), // .startofpacket
.source0_endofpacket (version_id_s_burst_adapter_source0_endofpacket), // .endofpacket
.source0_ready (version_id_s_burst_adapter_source0_ready) // .ready
);
altera_merlin_burst_adapter #(
.PKT_ADDR_H (56),
.PKT_ADDR_L (36),
.PKT_BEGIN_BURST (84),
.PKT_BYTE_CNT_H (69),
.PKT_BYTE_CNT_L (63),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_BURST_SIZE_H (79),
.PKT_BURST_SIZE_L (77),
.PKT_BURST_TYPE_H (81),
.PKT_BURST_TYPE_L (80),
.PKT_BURSTWRAP_H (76),
.PKT_BURSTWRAP_L (70),
.PKT_TRANS_COMPRESSED_READ (57),
.PKT_TRANS_WRITE (59),
.PKT_TRANS_READ (60),
.OUT_NARROW_SIZE (0),
.IN_NARROW_SIZE (1),
.OUT_FIXED (0),
.OUT_COMPLETE_WRAP (0),
.ST_DATA_W (114),
.ST_CHANNEL_W (3),
.OUT_BYTE_CNT_H (65),
.OUT_BURSTWRAP_H (76),
.COMPRESSED_READ_SUPPORT (1),
.BYTEENABLE_SYNTHESIS (1),
.PIPE_INPUTS (0),
.NO_WRAP_SUPPORT (0),
.INCOMPLETE_WRAP_SUPPORT (0),
.BURSTWRAP_CONST_MASK (0),
.BURSTWRAP_CONST_VALUE (0),
.ADAPTER_VERSION ("13.1")
) acl_kernel_interface_kernel_cntrl_burst_adapter (
.clk (config_clk_out_clk_clk), // cr0.clk
.reset (version_id_clk_reset_reset_bridge_in_reset_reset), // cr0_reset.reset
.sink0_valid (cmd_mux_001_src_valid), // sink0.valid
.sink0_data (cmd_mux_001_src_data), // .data
.sink0_channel (cmd_mux_001_src_channel), // .channel
.sink0_startofpacket (cmd_mux_001_src_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_mux_001_src_endofpacket), // .endofpacket
.sink0_ready (cmd_mux_001_src_ready), // .ready
.source0_valid (acl_kernel_interface_kernel_cntrl_burst_adapter_source0_valid), // source0.valid
.source0_data (acl_kernel_interface_kernel_cntrl_burst_adapter_source0_data), // .data
.source0_channel (acl_kernel_interface_kernel_cntrl_burst_adapter_source0_channel), // .channel
.source0_startofpacket (acl_kernel_interface_kernel_cntrl_burst_adapter_source0_startofpacket), // .startofpacket
.source0_endofpacket (acl_kernel_interface_kernel_cntrl_burst_adapter_source0_endofpacket), // .endofpacket
.source0_ready (acl_kernel_interface_kernel_cntrl_burst_adapter_source0_ready) // .ready
);
altera_merlin_burst_adapter #(
.PKT_ADDR_H (56),
.PKT_ADDR_L (36),
.PKT_BEGIN_BURST (84),
.PKT_BYTE_CNT_H (69),
.PKT_BYTE_CNT_L (63),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_BURST_SIZE_H (79),
.PKT_BURST_SIZE_L (77),
.PKT_BURST_TYPE_H (81),
.PKT_BURST_TYPE_L (80),
.PKT_BURSTWRAP_H (76),
.PKT_BURSTWRAP_L (70),
.PKT_TRANS_COMPRESSED_READ (57),
.PKT_TRANS_WRITE (59),
.PKT_TRANS_READ (60),
.OUT_NARROW_SIZE (0),
.IN_NARROW_SIZE (1),
.OUT_FIXED (0),
.OUT_COMPLETE_WRAP (0),
.ST_DATA_W (114),
.ST_CHANNEL_W (3),
.OUT_BYTE_CNT_H (65),
.OUT_BURSTWRAP_H (76),
.COMPRESSED_READ_SUPPORT (1),
.BYTEENABLE_SYNTHESIS (1),
.PIPE_INPUTS (0),
.NO_WRAP_SUPPORT (0),
.INCOMPLETE_WRAP_SUPPORT (0),
.BURSTWRAP_CONST_MASK (0),
.BURSTWRAP_CONST_VALUE (0),
.ADAPTER_VERSION ("13.1")
) acl_kernel_clk_ctrl_burst_adapter (
.clk (config_clk_out_clk_clk), // cr0.clk
.reset (version_id_clk_reset_reset_bridge_in_reset_reset), // cr0_reset.reset
.sink0_valid (cmd_mux_002_src_valid), // sink0.valid
.sink0_data (cmd_mux_002_src_data), // .data
.sink0_channel (cmd_mux_002_src_channel), // .channel
.sink0_startofpacket (cmd_mux_002_src_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_mux_002_src_endofpacket), // .endofpacket
.sink0_ready (cmd_mux_002_src_ready), // .ready
.source0_valid (acl_kernel_clk_ctrl_burst_adapter_source0_valid), // source0.valid
.source0_data (acl_kernel_clk_ctrl_burst_adapter_source0_data), // .data
.source0_channel (acl_kernel_clk_ctrl_burst_adapter_source0_channel), // .channel
.source0_startofpacket (acl_kernel_clk_ctrl_burst_adapter_source0_startofpacket), // .startofpacket
.source0_endofpacket (acl_kernel_clk_ctrl_burst_adapter_source0_endofpacket), // .endofpacket
.source0_ready (acl_kernel_clk_ctrl_burst_adapter_source0_ready) // .ready
);
system_acl_iface_mm_interconnect_0_cmd_demux cmd_demux (
.clk (config_clk_out_clk_clk), // clk.clk
.reset (hps_h2f_lw_axi_master_agent_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (hps_h2f_lw_axi_master_wr_limiter_cmd_src_ready), // sink.ready
.sink_channel (hps_h2f_lw_axi_master_wr_limiter_cmd_src_channel), // .channel
.sink_data (hps_h2f_lw_axi_master_wr_limiter_cmd_src_data), // .data
.sink_startofpacket (hps_h2f_lw_axi_master_wr_limiter_cmd_src_startofpacket), // .startofpacket
.sink_endofpacket (hps_h2f_lw_axi_master_wr_limiter_cmd_src_endofpacket), // .endofpacket
.sink_valid (hps_h2f_lw_axi_master_wr_limiter_cmd_valid_data), // sink_valid.data
.src0_ready (cmd_demux_src0_ready), // src0.ready
.src0_valid (cmd_demux_src0_valid), // .valid
.src0_data (cmd_demux_src0_data), // .data
.src0_channel (cmd_demux_src0_channel), // .channel
.src0_startofpacket (cmd_demux_src0_startofpacket), // .startofpacket
.src0_endofpacket (cmd_demux_src0_endofpacket), // .endofpacket
.src1_ready (cmd_demux_src1_ready), // src1.ready
.src1_valid (cmd_demux_src1_valid), // .valid
.src1_data (cmd_demux_src1_data), // .data
.src1_channel (cmd_demux_src1_channel), // .channel
.src1_startofpacket (cmd_demux_src1_startofpacket), // .startofpacket
.src1_endofpacket (cmd_demux_src1_endofpacket), // .endofpacket
.src2_ready (cmd_demux_src2_ready), // src2.ready
.src2_valid (cmd_demux_src2_valid), // .valid
.src2_data (cmd_demux_src2_data), // .data
.src2_channel (cmd_demux_src2_channel), // .channel
.src2_startofpacket (cmd_demux_src2_startofpacket), // .startofpacket
.src2_endofpacket (cmd_demux_src2_endofpacket) // .endofpacket
);
system_acl_iface_mm_interconnect_0_cmd_demux cmd_demux_001 (
.clk (config_clk_out_clk_clk), // clk.clk
.reset (hps_h2f_lw_axi_master_agent_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (hps_h2f_lw_axi_master_rd_limiter_cmd_src_ready), // sink.ready
.sink_channel (hps_h2f_lw_axi_master_rd_limiter_cmd_src_channel), // .channel
.sink_data (hps_h2f_lw_axi_master_rd_limiter_cmd_src_data), // .data
.sink_startofpacket (hps_h2f_lw_axi_master_rd_limiter_cmd_src_startofpacket), // .startofpacket
.sink_endofpacket (hps_h2f_lw_axi_master_rd_limiter_cmd_src_endofpacket), // .endofpacket
.sink_valid (hps_h2f_lw_axi_master_rd_limiter_cmd_valid_data), // sink_valid.data
.src0_ready (cmd_demux_001_src0_ready), // src0.ready
.src0_valid (cmd_demux_001_src0_valid), // .valid
.src0_data (cmd_demux_001_src0_data), // .data
.src0_channel (cmd_demux_001_src0_channel), // .channel
.src0_startofpacket (cmd_demux_001_src0_startofpacket), // .startofpacket
.src0_endofpacket (cmd_demux_001_src0_endofpacket), // .endofpacket
.src1_ready (cmd_demux_001_src1_ready), // src1.ready
.src1_valid (cmd_demux_001_src1_valid), // .valid
.src1_data (cmd_demux_001_src1_data), // .data
.src1_channel (cmd_demux_001_src1_channel), // .channel
.src1_startofpacket (cmd_demux_001_src1_startofpacket), // .startofpacket
.src1_endofpacket (cmd_demux_001_src1_endofpacket), // .endofpacket
.src2_ready (cmd_demux_001_src2_ready), // src2.ready
.src2_valid (cmd_demux_001_src2_valid), // .valid
.src2_data (cmd_demux_001_src2_data), // .data
.src2_channel (cmd_demux_001_src2_channel), // .channel
.src2_startofpacket (cmd_demux_001_src2_startofpacket), // .startofpacket
.src2_endofpacket (cmd_demux_001_src2_endofpacket) // .endofpacket
);
system_acl_iface_mm_interconnect_0_cmd_mux cmd_mux (
.clk (config_clk_out_clk_clk), // clk.clk
.reset (version_id_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_src_ready), // src.ready
.src_valid (cmd_mux_src_valid), // .valid
.src_data (cmd_mux_src_data), // .data
.src_channel (cmd_mux_src_channel), // .channel
.src_startofpacket (cmd_mux_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src0_ready), // sink0.ready
.sink0_valid (cmd_demux_src0_valid), // .valid
.sink0_channel (cmd_demux_src0_channel), // .channel
.sink0_data (cmd_demux_src0_data), // .data
.sink0_startofpacket (cmd_demux_src0_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src0_endofpacket), // .endofpacket
.sink1_ready (cmd_demux_001_src0_ready), // sink1.ready
.sink1_valid (cmd_demux_001_src0_valid), // .valid
.sink1_channel (cmd_demux_001_src0_channel), // .channel
.sink1_data (cmd_demux_001_src0_data), // .data
.sink1_startofpacket (cmd_demux_001_src0_startofpacket), // .startofpacket
.sink1_endofpacket (cmd_demux_001_src0_endofpacket) // .endofpacket
);
system_acl_iface_mm_interconnect_0_cmd_mux cmd_mux_001 (
.clk (config_clk_out_clk_clk), // clk.clk
.reset (version_id_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_001_src_ready), // src.ready
.src_valid (cmd_mux_001_src_valid), // .valid
.src_data (cmd_mux_001_src_data), // .data
.src_channel (cmd_mux_001_src_channel), // .channel
.src_startofpacket (cmd_mux_001_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_001_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src1_ready), // sink0.ready
.sink0_valid (cmd_demux_src1_valid), // .valid
.sink0_channel (cmd_demux_src1_channel), // .channel
.sink0_data (cmd_demux_src1_data), // .data
.sink0_startofpacket (cmd_demux_src1_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src1_endofpacket), // .endofpacket
.sink1_ready (cmd_demux_001_src1_ready), // sink1.ready
.sink1_valid (cmd_demux_001_src1_valid), // .valid
.sink1_channel (cmd_demux_001_src1_channel), // .channel
.sink1_data (cmd_demux_001_src1_data), // .data
.sink1_startofpacket (cmd_demux_001_src1_startofpacket), // .startofpacket
.sink1_endofpacket (cmd_demux_001_src1_endofpacket) // .endofpacket
);
system_acl_iface_mm_interconnect_0_cmd_mux cmd_mux_002 (
.clk (config_clk_out_clk_clk), // clk.clk
.reset (version_id_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_002_src_ready), // src.ready
.src_valid (cmd_mux_002_src_valid), // .valid
.src_data (cmd_mux_002_src_data), // .data
.src_channel (cmd_mux_002_src_channel), // .channel
.src_startofpacket (cmd_mux_002_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_002_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src2_ready), // sink0.ready
.sink0_valid (cmd_demux_src2_valid), // .valid
.sink0_channel (cmd_demux_src2_channel), // .channel
.sink0_data (cmd_demux_src2_data), // .data
.sink0_startofpacket (cmd_demux_src2_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src2_endofpacket), // .endofpacket
.sink1_ready (cmd_demux_001_src2_ready), // sink1.ready
.sink1_valid (cmd_demux_001_src2_valid), // .valid
.sink1_channel (cmd_demux_001_src2_channel), // .channel
.sink1_data (cmd_demux_001_src2_data), // .data
.sink1_startofpacket (cmd_demux_001_src2_startofpacket), // .startofpacket
.sink1_endofpacket (cmd_demux_001_src2_endofpacket) // .endofpacket
);
system_acl_iface_mm_interconnect_0_rsp_demux rsp_demux (
.clk (config_clk_out_clk_clk), // clk.clk
.reset (version_id_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_002_src_ready), // sink.ready
.sink_channel (router_002_src_channel), // .channel
.sink_data (router_002_src_data), // .data
.sink_startofpacket (router_002_src_startofpacket), // .startofpacket
.sink_endofpacket (router_002_src_endofpacket), // .endofpacket
.sink_valid (router_002_src_valid), // .valid
.src0_ready (rsp_demux_src0_ready), // src0.ready
.src0_valid (rsp_demux_src0_valid), // .valid
.src0_data (rsp_demux_src0_data), // .data
.src0_channel (rsp_demux_src0_channel), // .channel
.src0_startofpacket (rsp_demux_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_src0_endofpacket), // .endofpacket
.src1_ready (rsp_demux_src1_ready), // src1.ready
.src1_valid (rsp_demux_src1_valid), // .valid
.src1_data (rsp_demux_src1_data), // .data
.src1_channel (rsp_demux_src1_channel), // .channel
.src1_startofpacket (rsp_demux_src1_startofpacket), // .startofpacket
.src1_endofpacket (rsp_demux_src1_endofpacket) // .endofpacket
);
system_acl_iface_mm_interconnect_0_rsp_demux rsp_demux_001 (
.clk (config_clk_out_clk_clk), // clk.clk
.reset (version_id_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_003_src_ready), // sink.ready
.sink_channel (router_003_src_channel), // .channel
.sink_data (router_003_src_data), // .data
.sink_startofpacket (router_003_src_startofpacket), // .startofpacket
.sink_endofpacket (router_003_src_endofpacket), // .endofpacket
.sink_valid (router_003_src_valid), // .valid
.src0_ready (rsp_demux_001_src0_ready), // src0.ready
.src0_valid (rsp_demux_001_src0_valid), // .valid
.src0_data (rsp_demux_001_src0_data), // .data
.src0_channel (rsp_demux_001_src0_channel), // .channel
.src0_startofpacket (rsp_demux_001_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_001_src0_endofpacket), // .endofpacket
.src1_ready (rsp_demux_001_src1_ready), // src1.ready
.src1_valid (rsp_demux_001_src1_valid), // .valid
.src1_data (rsp_demux_001_src1_data), // .data
.src1_channel (rsp_demux_001_src1_channel), // .channel
.src1_startofpacket (rsp_demux_001_src1_startofpacket), // .startofpacket
.src1_endofpacket (rsp_demux_001_src1_endofpacket) // .endofpacket
);
system_acl_iface_mm_interconnect_0_rsp_demux rsp_demux_002 (
.clk (config_clk_out_clk_clk), // clk.clk
.reset (version_id_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_004_src_ready), // sink.ready
.sink_channel (router_004_src_channel), // .channel
.sink_data (router_004_src_data), // .data
.sink_startofpacket (router_004_src_startofpacket), // .startofpacket
.sink_endofpacket (router_004_src_endofpacket), // .endofpacket
.sink_valid (router_004_src_valid), // .valid
.src0_ready (rsp_demux_002_src0_ready), // src0.ready
.src0_valid (rsp_demux_002_src0_valid), // .valid
.src0_data (rsp_demux_002_src0_data), // .data
.src0_channel (rsp_demux_002_src0_channel), // .channel
.src0_startofpacket (rsp_demux_002_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_002_src0_endofpacket), // .endofpacket
.src1_ready (rsp_demux_002_src1_ready), // src1.ready
.src1_valid (rsp_demux_002_src1_valid), // .valid
.src1_data (rsp_demux_002_src1_data), // .data
.src1_channel (rsp_demux_002_src1_channel), // .channel
.src1_startofpacket (rsp_demux_002_src1_startofpacket), // .startofpacket
.src1_endofpacket (rsp_demux_002_src1_endofpacket) // .endofpacket
);
system_acl_iface_mm_interconnect_0_rsp_mux rsp_mux (
.clk (config_clk_out_clk_clk), // clk.clk
.reset (hps_h2f_lw_axi_master_agent_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (rsp_mux_src_ready), // src.ready
.src_valid (rsp_mux_src_valid), // .valid
.src_data (rsp_mux_src_data), // .data
.src_channel (rsp_mux_src_channel), // .channel
.src_startofpacket (rsp_mux_src_startofpacket), // .startofpacket
.src_endofpacket (rsp_mux_src_endofpacket), // .endofpacket
.sink0_ready (rsp_demux_src0_ready), // sink0.ready
.sink0_valid (rsp_demux_src0_valid), // .valid
.sink0_channel (rsp_demux_src0_channel), // .channel
.sink0_data (rsp_demux_src0_data), // .data
.sink0_startofpacket (rsp_demux_src0_startofpacket), // .startofpacket
.sink0_endofpacket (rsp_demux_src0_endofpacket), // .endofpacket
.sink1_ready (rsp_demux_001_src0_ready), // sink1.ready
.sink1_valid (rsp_demux_001_src0_valid), // .valid
.sink1_channel (rsp_demux_001_src0_channel), // .channel
.sink1_data (rsp_demux_001_src0_data), // .data
.sink1_startofpacket (rsp_demux_001_src0_startofpacket), // .startofpacket
.sink1_endofpacket (rsp_demux_001_src0_endofpacket), // .endofpacket
.sink2_ready (rsp_demux_002_src0_ready), // sink2.ready
.sink2_valid (rsp_demux_002_src0_valid), // .valid
.sink2_channel (rsp_demux_002_src0_channel), // .channel
.sink2_data (rsp_demux_002_src0_data), // .data
.sink2_startofpacket (rsp_demux_002_src0_startofpacket), // .startofpacket
.sink2_endofpacket (rsp_demux_002_src0_endofpacket) // .endofpacket
);
system_acl_iface_mm_interconnect_0_rsp_mux rsp_mux_001 (
.clk (config_clk_out_clk_clk), // clk.clk
.reset (hps_h2f_lw_axi_master_agent_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (rsp_mux_001_src_ready), // src.ready
.src_valid (rsp_mux_001_src_valid), // .valid
.src_data (rsp_mux_001_src_data), // .data
.src_channel (rsp_mux_001_src_channel), // .channel
.src_startofpacket (rsp_mux_001_src_startofpacket), // .startofpacket
.src_endofpacket (rsp_mux_001_src_endofpacket), // .endofpacket
.sink0_ready (rsp_demux_src1_ready), // sink0.ready
.sink0_valid (rsp_demux_src1_valid), // .valid
.sink0_channel (rsp_demux_src1_channel), // .channel
.sink0_data (rsp_demux_src1_data), // .data
.sink0_startofpacket (rsp_demux_src1_startofpacket), // .startofpacket
.sink0_endofpacket (rsp_demux_src1_endofpacket), // .endofpacket
.sink1_ready (rsp_demux_001_src1_ready), // sink1.ready
.sink1_valid (rsp_demux_001_src1_valid), // .valid
.sink1_channel (rsp_demux_001_src1_channel), // .channel
.sink1_data (rsp_demux_001_src1_data), // .data
.sink1_startofpacket (rsp_demux_001_src1_startofpacket), // .startofpacket
.sink1_endofpacket (rsp_demux_001_src1_endofpacket), // .endofpacket
.sink2_ready (rsp_demux_002_src1_ready), // sink2.ready
.sink2_valid (rsp_demux_002_src1_valid), // .valid
.sink2_channel (rsp_demux_002_src1_channel), // .channel
.sink2_data (rsp_demux_002_src1_data), // .data
.sink2_startofpacket (rsp_demux_002_src1_startofpacket), // .startofpacket
.sink2_endofpacket (rsp_demux_002_src1_endofpacket) // .endofpacket
);
endmodule
|
module dps_utim64(
//System
input wire iCLOCK, //Global Clock
input wire inRESET,
//Timer Clock
input wire iTIMER_CLOCK,
//Counter
input wire iREQ_VALID,
output wire oREQ_BUSY,
input wire iREQ_RW,
input wire [4:0] iREQ_ADDR,
input wire [31:0] iREQ_DATA,
output wire oREQ_VALID,
output wire [31:0] oREQ_DATA,
//Interrupt
output wire oIRQ_VALID,
input wire iIRQ_ACK
);
wire [3:0] utim64a_irq;
wire [3:0] utim64b_irq;
reg [1:0] b_irq_state;
reg [7:0] b_irq_flags;
reg b_flag_buffer_valid;
reg [7:0] b_flag_buffer_flags;
wire utim64a_busy;
wire utim64b_busy;
wire utim64a_req_cc;
wire utim64b_req_cc;
wire utim64_flags_cc;
assign utim64a_req_cc = !utim64a_busy && !utim64b_busy && iREQ_VALID && (iREQ_ADDR >= 5'h0 && iREQ_ADDR <= 5'he);
assign utim64b_req_cc = !utim64a_busy && !utim64b_busy && iREQ_VALID && (iREQ_ADDR >= 5'h10 && iREQ_ADDR <= 5'h1e);
assign utim64_flags_cc = !utim64a_busy && !utim64b_busy && iREQ_VALID && !iREQ_RW && (iREQ_ADDR == 5'h1f);
wire utim64a_out_valid;
wire utim64b_out_valid;
wire [31:0] utim64a_out_data;
wire [31:0] utim64b_out_data;
/************************************
Module Select State
************************************/
parameter L_PARAM_MAIN_STT_IDLE = 1'h0;
parameter L_PARAM_MAIN_STT_RD_WAIT = 1'h1;
reg [1:0] b_modsel; //0:UTIM64A | 1:UTIM64B | 2:FLAGS
reg b_state;
always@(posedge iCLOCK or negedge inRESET)begin
if(!inRESET)begin
b_state <= L_PARAM_MAIN_STT_IDLE;
b_modsel <= 2'b00;
end
else begin
case(b_state)
L_PARAM_MAIN_STT_IDLE:
begin
if(!iREQ_RW)begin
if(utim64a_req_cc)begin
b_state <= L_PARAM_MAIN_STT_RD_WAIT;
b_modsel <= 2'b00;
end
else if(utim64b_req_cc)begin
b_state <= L_PARAM_MAIN_STT_RD_WAIT;
b_modsel <= 2'b01;
end
else if(utim64_flags_cc)begin
b_state <= L_PARAM_MAIN_STT_RD_WAIT;
b_modsel <= 2'b10;
end
end
end
L_PARAM_MAIN_STT_RD_WAIT:
begin
if(utim64a_out_valid || utim64b_out_valid || b_flag_buffer_valid)begin
b_state <= L_PARAM_MAIN_STT_IDLE;
end
end
endcase
end
end
/************************************
Timer Module
************************************/
dps_utim64_module UTIM64A(
//System
.iIF_CLOCK(iCLOCK),
.iTIMER_CLOCK(iTIMER_CLOCK),
.inRESET(inRESET),
//Counter
.iREQ_VALID(utim64a_req_cc),
.oREQ_BUSY(utim64a_busy),
.iREQ_RW(iREQ_RW),
.iREQ_ADDR(iREQ_ADDR[3:0]),
.iREQ_DATA(iREQ_DATA),
.oREQ_VALID(utim64a_out_valid),
.oREQ_DATA(utim64a_out_data),
//Interrupt
.oIRQ_IRQ(utim64a_irq)
);
dps_utim64_module UTIM64B(
//System
.iIF_CLOCK(iCLOCK),
.iTIMER_CLOCK(iTIMER_CLOCK),
.inRESET(inRESET),
//Counter
.iREQ_VALID(utim64b_req_cc),
.oREQ_BUSY(utim64b_busy),
.iREQ_RW(iREQ_RW),
.iREQ_ADDR({1'b0, iREQ_ADDR[2:0]}),
.iREQ_DATA(iREQ_DATA),
.oREQ_VALID(utim64b_out_valid),
.oREQ_DATA(utim64b_out_data),
//Interrupt
.oIRQ_IRQ(utim64b_irq)
);
/************************************
IRQ Flags
************************************/
parameter L_PARAM_IRQ_STT_IDLE = 2'h0;
parameter L_PARAM_IRQ_STT_IRQ = 2'h1;
parameter L_PARAM_IRQ_STT_FLAG = 2'h2;
always@(posedge iCLOCK or negedge inRESET)begin
if(!inRESET)begin
b_irq_state <= L_PARAM_IRQ_STT_IDLE;
b_irq_flags <= 8'h0;
end
else begin
case(b_irq_state)
L_PARAM_IRQ_STT_IDLE:
begin
if(|{utim64a_irq, utim64b_irq})begin
b_irq_state <= L_PARAM_IRQ_STT_IRQ;
b_irq_flags <= b_irq_flags | {utim64b_irq, utim64a_irq};
end
begin
b_irq_flags <= b_irq_flags | {utim64b_irq, utim64a_irq};
end
/*
if(|{utim64a_irq, utim64b_irq})begin
b_irq_state <= L_PARAM_IRQ_STT_IRQ;
if(utim64_flags_cc)begin
b_irq_flags <= {utim64a_irq, utim64b_irq};
end
else begin
b_irq_flags <= b_irq_flags | {utim64a_irq, utim64b_irq};
end
end
else begin
if(utim64_flags_cc)begin
b_irq_flags <= 8'h00;
end
else begin
b_irq_flags <= b_irq_flags;
end
end
*/
end
L_PARAM_IRQ_STT_IRQ:
begin
if(iIRQ_ACK)begin
b_irq_state <= L_PARAM_IRQ_STT_FLAG;
end
b_irq_flags <= b_irq_flags | {utim64b_irq, utim64a_irq};
/*
if(iIRQ_ACK)begin
if(utim64_flags_cc)begin
//Flag Load Condition
b_irq_state <= (utim64a_irq || utim64b_irq)? L_PARAM_IRQ_STT_IRQ : L_PARAM_IRQ_STT_IDLE;
b_irq_flags <= (utim64a_irq || utim64b_irq)? {utim64a_irq, utim64b_irq} : 8'h00;
end
else begin
//Not Flag Load Condition
b_irq_state <= (utim64a_irq || utim64b_irq)? L_PARAM_IRQ_STT_IRQ : L_PARAM_IRQ_STT_IDLE;
b_irq_flags <= (utim64a_irq || utim64b_irq)? (b_irq_flags | {utim64a_irq, utim64b_irq}) : b_irq_flags;
end
end
else begin
if(utim64_flags_cc)begin
//Flag Load Condition
b_irq_state <= L_PARAM_IRQ_STT_IRQ;
b_irq_flags <= (utim64a_irq || utim64b_irq)? {utim64a_irq, utim64b_irq} : 8'h00;
end
else begin
//Not Flag Load Condition
b_irq_state <= L_PARAM_IRQ_STT_IRQ;
b_irq_flags <= (utim64a_irq || utim64b_irq)? (b_irq_flags | {utim64a_irq, utim64b_irq}) : b_irq_flags;
end
end
*/
end
L_PARAM_IRQ_STT_FLAG:
begin
if(utim64_flags_cc)begin
//Flag Load Condition
b_irq_state <= L_PARAM_IRQ_STT_IDLE;
b_irq_flags <= {utim64b_irq, utim64a_irq};
end
else begin
//Not Flag Load Condition
b_irq_flags <= b_irq_flags | {utim64b_irq, utim64a_irq};
end
end
default:
begin
b_irq_state <= L_PARAM_IRQ_STT_IDLE;
end
endcase
end
end
always@(posedge iCLOCK or negedge inRESET)begin
if(!inRESET)begin
b_flag_buffer_valid <= 1'b0;
b_flag_buffer_flags <= 8'h0;
end
else begin
b_flag_buffer_valid <= utim64_flags_cc;//utim64_flags_cc && (b_irq_state == L_PARAM_IRQ_STT_IRQ);
b_flag_buffer_flags <= b_irq_flags;
end
end
/************************************
Assign
************************************/
assign oIRQ_VALID = (b_irq_state == L_PARAM_IRQ_STT_IRQ)? 1'b1 : 1'b0;
assign oREQ_BUSY = (b_state != L_PARAM_MAIN_STT_IDLE) || utim64a_busy || utim64b_busy;
assign oREQ_VALID = utim64a_out_valid || utim64b_out_valid || b_flag_buffer_valid;
assign oREQ_DATA = (b_modsel == 2'h0)? utim64a_out_data : (
(b_modsel == 2'h1)? utim64b_out_data : b_flag_buffer_flags
);
endmodule
|
module sky130_fd_sc_ms__and2 (
X,
A,
B
);
// Module ports
output X;
input A;
input B;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire and0_out_X;
// Name Output Other arguments
and and0 (and0_out_X, A, B );
buf buf0 (X , and0_out_X );
endmodule
|
module sky130_fd_sc_ms__decap ();
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// No contents.
endmodule
|
module execute(
input wire iCLOCK,
input wire inRESET,
input wire iRESET_SYNC,
//Event CTRL
input wire iEVENT_HOLD,
input wire iEVENT_START,
input wire iEVENT_IRQ_FRONT2BACK,
input wire iEVENT_IRQ_BACK2FRONT,
input wire iEVENT_END,
//Lock
output wire oEXCEPTION_LOCK,
//System Register
input wire [31:0] iSYSREG_PFLAGR,
output wire [31:0] oSYSREG_FLAGR,
//Pipeline
input wire iPREVIOUS_VALID,
input wire iPREVIOUS_FAULT_PAGEFAULT,
input wire iPREVIOUS_FAULT_PRIVILEGE_ERROR,
input wire iPREVIOUS_FAULT_INVALID_INST,
input wire iPREVIOUS_PAGING_ENA,
input wire iPREVIOUS_KERNEL_ACCESS,
input wire iPREVIOUS_BRANCH_PREDICT,
input wire [31:0] iPREVIOUS_BRANCH_PREDICT_ADDR,
input wire [31:0] iPREVIOUS_SYSREG_PSR,
input wire [63:0] iPREVIOUS_SYSREG_FRCR,
input wire [31:0] iPREVIOUS_SYSREG_TIDR,
input wire [31:0] iPREVIOUS_SYSREG_PDTR,
input wire [31:0] iPREVIOUS_SYSREG_KPDTR,
input wire iPREVIOUS_DESTINATION_SYSREG,
input wire [4:0] iPREVIOUS_DESTINATION,
input wire iPREVIOUS_WRITEBACK,
input wire iPREVIOUS_FLAGS_WRITEBACK,
input wire [4:0] iPREVIOUS_CMD,
input wire [3:0] iPREVIOUS_CC_AFE,
input wire [31:0] iPREVIOUS_SPR,
input wire [31:0] iPREVIOUS_SOURCE0,
input wire [31:0] iPREVIOUS_SOURCE1,
input wire [5:0] iPREVIOUS_ADV_DATA,
input wire [4:0] iPREVIOUS_SOURCE0_POINTER,
input wire [4:0] iPREVIOUS_SOURCE1_POINTER,
input wire iPREVIOUS_SOURCE0_SYSREG,
input wire iPREVIOUS_SOURCE1_SYSREG,
input wire iPREVIOUS_SOURCE1_IMM,
input wire iPREVIOUS_SOURCE0_FLAGS,
input wire iPREVIOUS_ADV_ACTIVE,
input wire iPREVIOUS_EX_SYS_REG,
input wire iPREVIOUS_EX_SYS_LDST,
input wire iPREVIOUS_EX_LOGIC,
input wire iPREVIOUS_EX_SHIFT,
input wire iPREVIOUS_EX_ADDER,
input wire iPREVIOUS_EX_MUL,
input wire iPREVIOUS_EX_SDIV,
input wire iPREVIOUS_EX_UDIV,
input wire iPREVIOUS_EX_LDST,
input wire iPREVIOUS_EX_BRANCH,
input wire [31:0] iPREVIOUS_PC,
output wire oPREVIOUS_LOCK,
//Load Store Pipe
output wire oDATAIO_REQ,
input wire iDATAIO_BUSY,
output wire [1:0] oDATAIO_ORDER, //00=Byte Order 01=2Byte Order 10= Word Order 11= None
output wire [3:0] oDATAIO_MASK, //[0]=Byte0, [1]=Byte1...
output wire oDATAIO_RW, //0=Read 1=Write
output wire [13:0] oDATAIO_ASID,
output wire [1:0] oDATAIO_MMUMOD,
output wire [2:0] oDATAIO_MMUPS,
output wire [31:0] oDATAIO_PDT,
output wire [31:0] oDATAIO_ADDR,
output wire [31:0] oDATAIO_DATA,
input wire iDATAIO_REQ,
input wire [11:0] iDATAIO_MMU_FLAGS,
input wire [31:0] iDATAIO_DATA,
//Writeback
output wire oNEXT_VALID,
output wire [31:0] oNEXT_DATA,
output wire [4:0] oNEXT_DESTINATION,
output wire oNEXT_DESTINATION_SYSREG,
output wire oNEXT_WRITEBACK,
output wire oNEXT_SPR_WRITEBACK,
output wire [31:0] oNEXT_SPR,
output wire [63:0] oNEXT_FRCR,
output wire [31:0] oNEXT_PC,
//System Register Write
output wire oPDTR_WRITEBACK,
//Branch
output wire [31:0] oBRANCH_ADDR,
output wire oJUMP_VALID,
output wire oINTR_VALID,
output wire oIDTSET_VALID,
output wire oPDTSET_VALID,
output wire oPSRSET_VALID,
output wire oFAULT_VALID,
output wire [6:0] oFAULT_NUM,
output wire [31:0] oFAULT_FI0R,
output wire [31:0] oFAULT_FI1R,
//Branch Predictor
output wire oBPREDICT_JUMP_INST,
output wire oBPREDICT_PREDICT, //Branch Guess
output wire oBPREDICT_HIT, //Guess Hit!
output wire oBPREDICT_JUMP, //Branch Active
output wire [31:0] oBPREDICT_JUMP_ADDR, //Branch Address
output wire [31:0] oBPREDICT_INST_ADDR, //Branch Instruction Memory Address
//Debug
input wire iDEBUG_CTRL_REQ,
input wire iDEBUG_CTRL_STOP,
input wire iDEBUG_CTRL_START,
output wire oDEBUG_CTRL_ACK,
output wire [31:0] oDEBUG_REG_OUT_FLAGR
);
/*********************************************************************************************************
Wire
*********************************************************************************************************/
localparam L_PARAM_STT_NORMAL = 3'h0;
localparam L_PARAM_STT_DIV_WAIT = 3'h1;
localparam L_PARAM_STT_LOAD = 3'h2;
localparam L_PARAM_STT_STORE = 3'h3;
localparam L_PARAM_STT_BRANCH = 3'h4;
localparam L_PARAM_STT_RELOAD = 3'h5;
localparam L_PARAM_STT_EXCEPTION = 3'h6;
localparam L_PARAM_STT_HALT = 3'h7;
reg b_valid;
reg [31:0] b_sysreg_psr;
reg [31:0] b_sysreg_tidr;
reg [31:0] b_sysreg_pdt;
reg [2:0] b_state;
reg b_load_store;
reg b_writeback;
reg b_destination_sysreg;
reg [4:0] b_destination;
reg [3:0] b_afe;
reg [31:0] b_r_data;
reg b_spr_writeback;
reg [31:0] b_r_spr;
reg [31:0] b_pc;
reg [63:0] b_frcr;
wire div_wait;
wire debugger_pipeline_stop;
wire lock_condition = (b_state != L_PARAM_STT_NORMAL) || div_wait || debugger_pipeline_stop;// || iDATAIO_BUSY;
wire io_lock_condition = iDATAIO_BUSY;
assign oPREVIOUS_LOCK = lock_condition || iEVENT_HOLD || iEVENT_HOLD;
wire [31:0] ex_module_source0;
wire [31:0] ex_module_source1;
wire forwarding_reg_gr_valid;
wire [31:0] forwarding_reg_gr_data;
wire [4:0] forwarding_reg_gr_dest;
wire forwarding_reg_gr_dest_sysreg;
wire forwarding_reg_spr_valid;
wire [31:0] forwarding_reg_spr_data;
wire forwarding_reg_frcr_valid;
wire [63:0] forwarding_reg_frcr_data;
wire [31:0] ex_module_spr;// = forwarding_reg_spr_data;
wire [31:0] ex_module_pdtr;
wire [31:0] ex_module_kpdtr;
wire [31:0] ex_module_tidr;
wire [31:0] ex_module_psr;
//System Register
wire sys_reg_sf = 1'b0;
wire sys_reg_of = 1'b0;
wire sys_reg_cf = 1'b0;
wire sys_reg_pf = 1'b0;
wire sys_reg_zf = 1'b0;
wire [4:0] sys_reg_flags = {sys_reg_sf, sys_reg_of, sys_reg_cf, sys_reg_pf, sys_reg_zf};
wire [31:0] sys_reg_data;
//Logic
wire logic_sf;
wire logic_of;
wire logic_cf;
wire logic_pf;
wire logic_zf;
wire [31:0] logic_data;
wire [4:0] logic_flags = {logic_sf, logic_of, logic_cf, logic_pf, logic_zf};
//Shift
wire shift_sf, shift_of, shift_cf, shift_pf, shift_zf;
wire [31:0] shift_data;
wire [4:0] shift_flags = {shift_sf, shift_of, shift_cf, shift_pf, shift_zf};
//Adder
wire [31:0] adder_data;
wire adder_sf, adder_of, adder_cf, adder_pf, adder_zf;
wire [4:0] adder_flags = {adder_sf, adder_of, adder_cf, adder_pf, adder_zf};
//Mul
wire [4:0] mul_flags;
wire [31:0] mul_data;
//Div
wire [31:0] div_out_data;
wire div_out_valid;
/*
//Load Store
wire ldst_spr_valid;
wire [31:0] ldst_spr;
wire ldst_pipe_rw;
wire [31:0] ldst_pipe_addr;
wire [31:0] ldst_pipe_pdt;
wire [31:0] ldst_pipe_data;
wire [1:0] ldst_pipe_order;
wire [1:0] load_pipe_shift;
wire [3:0] ldst_pipe_mask;
*/
//Branch
wire [31:0] branch_branch_addr;
wire branch_jump_valid;
wire branch_not_jump_valid;
wire branch_ib_valid;
wire branch_halt_valid;
//AFE
wire [31:0] result_data_with_afe;
//Flag
wire [4:0] sysreg_flags_register;
/*********************************************************************************************************
Debug Module
*********************************************************************************************************/
execute_debugger DEBUGGER(
.iCLOCK(iCLOCK),
.inRESET(inRESET),
.iRESET_SYNC(iRESET_SYNC),
//Debugger Port
.iDEBUG_CTRL_REQ(iDEBUG_CTRL_REQ),
.iDEBUG_CTRL_STOP(iDEBUG_CTRL_STOP),
.iDEBUG_CTRL_START(iDEBUG_CTRL_START),
.oDEBUG_CTRL_ACK(oDEBUG_CTRL_ACK),
.oDEBUG_REG_OUT_FLAGR(oDEBUG_REG_OUT_FLAGR),
//Pipeline
.oPIPELINE_STOP(debugger_pipeline_stop),
//Registers
.iREGISTER_FLAGR(sysreg_flags_register),
//Busy
.iBUSY(lock_condition)
);
/*********************************************************************************************************
Forwarding
*********************************************************************************************************/
execute_forwarding_register FORWARDING_REGISTER(
.iCLOCK(iCLOCK),
.inRESET(inRESET),
.iRESET_SYNC(iEVENT_HOLD || iEVENT_START || iRESET_SYNC),
//Writeback - General Register
.iWB_GR_VALID(b_valid && b_writeback),
.iWB_GR_DATA(result_data_with_afe),
.iWB_GR_DEST(b_destination),
.iWB_GR_DEST_SYSREG(b_destination_sysreg),
//Writeback - Stack Point Register
.iWB_SPR_VALID(b_valid && b_spr_writeback),
.iWB_SPR_DATA(b_r_spr),
//Writeback Auto - Stack Point Register
.iWB_AUTO_SPR_VALID(b_valid && b_destination_sysreg && b_writeback && b_destination == `SYSREG_SPR),
.iWB_AUTO_SPR_DATA(result_data_with_afe),
//Current -Stak Point Register
.iCUUR_SPR_DATA(iPREVIOUS_SPR),
//Writeback - FRCR
.iWB_FRCR_VALID(b_valid),
.iWB_FRCR_DATA(b_frcr),
//Current - FRCR
.iCUUR_FRCR_DATA(iPREVIOUS_SYSREG_FRCR),
//Fowerding Register Output
.oFDR_GR_VALID(forwarding_reg_gr_valid),
.oFDR_GR_DATA(forwarding_reg_gr_data),
.oFDR_GR_DEST(forwarding_reg_gr_dest),
.oFDR_GR_DEST_SYSREG(forwarding_reg_gr_dest_sysreg),
//Fowerding Register Output
.oFDR_SPR_VALID(forwarding_reg_spr_valid),
.oFDR_SPR_DATA(forwarding_reg_spr_data),
//Forwerding Register Output
.oFDR_FRCR_VALID(forwarding_reg_frcr_valid),
.oFDR_FRCR_DATA(forwarding_reg_frcr_data)
);
execute_forwarding FORWARDING_RS0(
.iCLOCK(iCLOCK),
.inRESET(inRESET),
.iRESET_SYNC(iEVENT_HOLD || iEVENT_START || iRESET_SYNC),
//Writeback - General Register
.iWB_GR_VALID(b_valid && b_writeback),
.iWB_GR_DATA(result_data_with_afe),
.iWB_GR_DEST(b_destination),
.iWB_GR_DEST_SYSREG(b_destination_sysreg),
//Writeback - Stack Point Register
.iWB_SPR_VALID(b_valid && b_spr_writeback),
.iWB_SPR_DATA(b_r_spr),
//Writeback - FRCR
.iWR_FRCR_VALID(b_valid),
.iWR_FRCR_DATA(b_frcr),
//Previous Writeback - General Register
.iPREV_WB_GR_VALID(forwarding_reg_gr_valid),
.iPREV_WB_GR_DATA(forwarding_reg_gr_data),
.iPREV_WB_GR_DEST(forwarding_reg_gr_dest),
.iPREV_WB_GR_DEST_SYSREG(forwarding_reg_gr_dest_sysreg),
//Previous Writeback - Stack Point Register
.iPREV_WB_SPR_VALID(forwarding_reg_spr_valid),
.iPREV_WB_SPR_DATA(forwarding_reg_spr_data),
//Previous Writeback - FRCR
.iPREV_WB_FRCR_VALID(forwarding_reg_frcr_valid),
.iPREV_WB_FRCR_DATA(forwarding_reg_frcr_data),
//Source
.iPREVIOUS_SOURCE_SYSREG(iPREVIOUS_SOURCE0_SYSREG),
.iPREVIOUS_SOURCE_POINTER(iPREVIOUS_SOURCE0_POINTER),
.iPREVIOUS_SOURCE_IMM(1'b0/*iPREVIOUS_SOURCE0_IMM*/),
.iPREVIOUS_SOURCE_DATA(iPREVIOUS_SOURCE0),
.iPREVIOUS_SOURCE_PDTR(iPREVIOUS_SYSREG_PDTR),
.iPREVIOUS_SOURCE_KPDTR(iPREVIOUS_SYSREG_KPDTR),
.iPREVIOUS_SOURCE_TIDR(iPREVIOUS_SYSREG_TIDR),
.iPREVIOUS_SOURCE_PSR(iPREVIOUS_SYSREG_PSR),
//Output
.oNEXT_SOURCE_DATA(ex_module_source0),
.oNEXT_SOURCE_SPR(ex_module_spr),
.oNEXT_SOURCE_PDTR(ex_module_pdtr),
.oNEXT_SOURCE_KPDTR(ex_module_kpdtr),
.oNEXT_SOURCE_TIDR(ex_module_tidr),
.oNEXT_SOURCE_PSR(ex_module_psr)
);
/*
assign ex_module_pdtr = iPREVIOUS_SYSREG_PDTR;
assign ex_module_tidr = iPREVIOUS_SYSREG_TIDR;
assign ex_module_psr = iPREVIOUS_SYSREG_PSR;
*/
execute_forwarding FORWARDING_RS1(
.iCLOCK(iCLOCK),
.inRESET(inRESET),
.iRESET_SYNC(iEVENT_HOLD || iEVENT_START || iRESET_SYNC),
//Writeback - General Register
.iWB_GR_VALID(b_valid && b_writeback),
.iWB_GR_DATA(result_data_with_afe),
.iWB_GR_DEST(b_destination),
.iWB_GR_DEST_SYSREG(b_destination_sysreg),
//Writeback - Stack Point Register
.iWB_SPR_VALID(b_valid && b_spr_writeback),
.iWB_SPR_DATA(b_r_spr),
//Writeback - FRCR
.iWR_FRCR_VALID(b_valid),
.iWR_FRCR_DATA(b_frcr),
//Previous Writeback - General Register
.iPREV_WB_GR_VALID(forwarding_reg_gr_valid),
.iPREV_WB_GR_DATA(forwarding_reg_gr_data),
.iPREV_WB_GR_DEST(forwarding_reg_gr_dest),
.iPREV_WB_GR_DEST_SYSREG(forwarding_reg_gr_dest_sysreg),
//Previous Writeback - Stack Point Register
.iPREV_WB_SPR_VALID(forwarding_reg_spr_valid),
.iPREV_WB_SPR_DATA(forwarding_reg_spr_data),
//Previous Writeback - FRCR
.iPREV_WB_FRCR_VALID(forwarding_reg_frcr_valid),
.iPREV_WB_FRCR_DATA(forwarding_reg_frcr_data),
//Source
.iPREVIOUS_SOURCE_SYSREG(iPREVIOUS_SOURCE1_SYSREG),
.iPREVIOUS_SOURCE_POINTER(iPREVIOUS_SOURCE1_POINTER),
.iPREVIOUS_SOURCE_IMM(iPREVIOUS_SOURCE1_IMM),
.iPREVIOUS_SOURCE_DATA(iPREVIOUS_SOURCE1),
.iPREVIOUS_SOURCE_PDTR(iPREVIOUS_SYSREG_PDTR),
.iPREVIOUS_SOURCE_KPDTR(iPREVIOUS_SYSREG_KPDTR),
.iPREVIOUS_SOURCE_TIDR(iPREVIOUS_SYSREG_TIDR),
.iPREVIOUS_SOURCE_PSR(iPREVIOUS_SYSREG_PSR),
//Output
.oNEXT_SOURCE_DATA(ex_module_source1),
.oNEXT_SOURCE_SPR(),
.oNEXT_SOURCE_PDTR(),
.oNEXT_SOURCE_KPDTR(),
.oNEXT_SOURCE_TIDR(),
.oNEXT_SOURCE_PSR()
);
/****************************************
Flag Register
****************************************/
execute_flag_register REG_FLAG(
.iCLOCK(iCLOCK),
.inRESET(inRESET),
.iRESET_SYNC(iRESET_SYNC),
//Control
.iCTRL_HOLD(iEVENT_HOLD || iEVENT_HOLD || iEVENT_START),
//PFLAGR
.iPFLAGR_VALID(iEVENT_IRQ_BACK2FRONT),
.iPFLAGR(iSYSREG_PFLAGR[4:0]),
//Prev
.iPREV_INST_VALID(iPREVIOUS_VALID),
.iPREV_BUSY(lock_condition),
.iPREV_FLAG_WRITE(iPREVIOUS_FLAGS_WRITEBACK),
//Shift
.iSHIFT_VALID(iPREVIOUS_EX_SHIFT),
.iSHIFT_FLAG(shift_flags),
//Adder
.iADDER_VALID(iPREVIOUS_EX_ADDER),
.iADDER_FLAG(adder_flags),
//Mul
.iMUL_VALID(iPREVIOUS_EX_MUL),
.iMUL_FLAG(mul_flags),
//Logic
.iLOGIC_VALID(iPREVIOUS_EX_LOGIC),
.iLOGIC_FLAG(logic_flags),
//oUTPUT
.oFLAG(sysreg_flags_register)
);
/*********************************************************************************************************
Execute
*********************************************************************************************************/
/****************************************
Logic
****************************************/
wire [4:0] logic_cmd;
execute_logic_decode EXE_LOGIC_DECODER(
.iPREV_INST(iPREVIOUS_CMD),
.oNEXT_INST(logic_cmd)
);
execute_logic #(32) EXE_LOGIC(
.iCONTROL_CMD(logic_cmd),
.iDATA_0(ex_module_source0),
.iDATA_1(ex_module_source1),
.oDATA(logic_data),
.oSF(logic_sf),
.oOF(logic_of),
.oCF(logic_cf),
.oPF(logic_pf),
.oZF(logic_zf)
);
/****************************************
Shift
****************************************/
wire [2:0] shift_cmd;
execute_shift_decode EXE_SHIFT_DECODER(
.iPREV_INST(iPREVIOUS_CMD),
.oNEXT_INST(shift_cmd)
);
execute_shift #(32) EXE_SHIFT(
.iCONTROL_MODE(shift_cmd),
.iDATA_0(ex_module_source0),
.iDATA_1(ex_module_source1),
.oDATA(shift_data),
.oSF(shift_sf),
.oOF(shift_of),
.oCF(shift_cf),
.oPF(shift_pf),
.oZF(shift_zf)
);
/****************************************
Adder
****************************************/
execute_adder #(32) EXE_ADDER(
.iDATA_0(ex_module_source0),
.iDATA_1(ex_module_source1),
.iADDER_CMD(iPREVIOUS_CMD),
.oDATA(adder_data),
.oSF(adder_sf),
.oOF(adder_of),
.oCF(adder_cf),
.oPF(adder_pf),
.oZF(adder_zf)
);
/****************************************
Mul
****************************************/
execute_mul EXE_MUL(
.iCMD(iPREVIOUS_CMD),
.iDATA_0(ex_module_source0),
.iDATA_1(ex_module_source1),
.oDATA(mul_data),
.oFLAGS(mul_flags)
);
/*
wire [4:0] mul_flags = (iPREVIOUS_CMD == `EXE_MUL_MULH)? {mul_sf_h, mul_of_h, mul_cf_h, mul_pf_h, mul_zf_h} : {mul_sf_l, mul_of_l, mul_cf_l, mul_pf_l, mul_zf_l};
wire [31:0] mul_data = (iPREVIOUS_CMD == `EXE_MUL_MULH)? mul_tmp[63:32] : mul_tmp[31:0];
execute_mul_booth32 EXE_MUL_BOOTH(
//iDATA
.iDATA_0(ex_module_source0),
.iDATA_1(ex_module_source1),
//oDATA
.oDATA(mul_tmp),
.oHSF(mul_sf_h),
.oHCF(mul_cf_h),
.oHOF(mul_of_h),
.oHPF(mul_pf_h),
.oHZF(mul_zf_h),
.oLSF(mul_sf_l),
.oLCF(mul_cf_l),
.oLOF(mul_of_l),
.oLPF(mul_pf_l),
.oLZF(mul_zf_l)
);
*/
/****************************************
Div
****************************************/
execute_div EXE_DIV(
.iCLOCK(iCLOCK),
.inRESET(inRESET),
.iRESET_SYNC(iEVENT_HOLD || iEVENT_START || iRESET_SYNC),
//FLAG
.oFLAG_WAITING_DIV(div_wait),
//Prev
.iPREV_VALID(iPREVIOUS_VALID),
.iPREV_UDIV(iPREVIOUS_EX_UDIV),
.iPREV_SDIV(iPREVIOUS_EX_SDIV),
.iCMD(iPREVIOUS_CMD),
//iDATA
.iDATA_0(ex_module_source0),
.iDATA_1(ex_module_source1),
//oDATA
.iBUSY(lock_condition),
.oDATA_VALID(div_out_valid),
.oDATA(div_out_data)
);
/****************************************
Address calculate(Load Store)
****************************************/
//Load Store
wire ldst_spr_valid;
wire [31:0] ldst_spr;
wire ldst_pipe_rw;
wire [31:0] ldst_pipe_pdt;
wire [31:0] ldst_pipe_addr;
wire [31:0] ldst_pipe_data;
wire [1:0] ldst_pipe_order;
wire [1:0] load_pipe_shift;
wire [3:0] ldst_pipe_mask;
execute_adder_calc LDST_CALC_ADDR(
//Prev
.iCMD(iPREVIOUS_CMD),
.iLOADSTORE_MODE(iPREVIOUS_EX_LDST),
.iSOURCE0(ex_module_source0),
.iSOURCE1(ex_module_source1),
.iADV_ACTIVE(iPREVIOUS_ADV_ACTIVE),
//.iADV_DATA({26'h0, iPREVIOUS_ADV_DATA}),
.iADV_DATA({{26{iPREVIOUS_ADV_DATA[5]}}, iPREVIOUS_ADV_DATA}),
.iSPR(ex_module_spr),
.iPSR(ex_module_psr),
.iPDTR(ex_module_pdtr),
.iKPDTR(ex_module_kpdtr),
.iPC(iPREVIOUS_PC - 32'h4),
//Output - Writeback
.oOUT_SPR_VALID(ldst_spr_valid),
.oOUT_SPR(ldst_spr),
.oOUT_DATA(),
//Output - LDST Pipe
.oLDST_RW(ldst_pipe_rw),
.oLDST_PDT(ldst_pipe_pdt),
.oLDST_ADDR(ldst_pipe_addr),
.oLDST_DATA(ldst_pipe_data),
.oLDST_ORDER(ldst_pipe_order),
.oLDST_MASK(ldst_pipe_mask),
.oLOAD_SHIFT(load_pipe_shift)
);
//Load Store
wire [1:0] load_shift;
wire [3:0] load_mask;
execute_load_store STAGE_LDST(
.iCLOCK(iCLOCK),
.inRESET(inRESET),
.iRESET_SYNC(iRESET_SYNC),
//Event CTRL
.iEVENT_HOLD(iEVENT_HOLD),
.iEVENT_START(iEVENT_START),
.iEVENT_IRQ_FRONT2BACK(iEVENT_IRQ_FRONT2BACK),
.iEVENT_IRQ_BACK2FRONT(iEVENT_IRQ_BACK2FRONT),
.iEVENT_END(iEVENT_END),
//State
.iSTATE_NORMAL(b_state == L_PARAM_STT_NORMAL),
.iSTATE_LOAD(b_state == L_PARAM_STT_LOAD),
.iSTATE_STORE(b_state == L_PARAM_STT_STORE),
/*************************************
Previous
*************************************/
//Previous - PREDICT
.iPREV_VALID(iPREVIOUS_VALID),
.iPREV_EX_LDST(iPREVIOUS_EX_LDST),
//System Register
.iPREV_PSR(ex_module_psr),
.iPREV_TIDR(ex_module_tidr),
//Writeback
.iPREV_SPR_VALID(ldst_spr_valid),
.iPREV_SPR(ldst_spr),
//Output - LDST Pipe
.iPREV_LDST_RW(ldst_pipe_rw),
.iPREV_LDST_PDT(ldst_pipe_pdt),
.iPREV_LDST_ADDR(ldst_pipe_addr),
.iPREV_LDST_DATA(ldst_pipe_data),
.iPREV_LDST_ORDER(ldst_pipe_order),
.iPREV_LDST_MASK(ldst_pipe_mask),
.iPREV_LOAD_SHIFT(load_pipe_shift),
/*************************************
MA
*************************************/
//Output - LDST Pipe
.oLDST_REQ(oDATAIO_REQ),
.iLDST_BUSY(iEVENT_HOLD || io_lock_condition),
.oLDST_RW(oDATAIO_RW),
.oLDST_PDT(oDATAIO_PDT),
.oLDST_ADDR(oDATAIO_ADDR),
.oLDST_DATA(oDATAIO_DATA),
.oLDST_ORDER(oDATAIO_ORDER),
.oLDST_MASK(oDATAIO_MASK),
.oLDST_ASID(oDATAIO_ASID),
.oLDST_MMUMOD(oDATAIO_MMUMOD),
.oLDST_MMUPS(oDATAIO_MMUPS),
.iLDST_VALID(iDATAIO_REQ),
/*************************************
Next
*************************************/
//Next
.iNEXT_BUSY(lock_condition),
.oNEXT_VALID(),
.oNEXT_SPR_VALID(),
.oNEXT_SPR(),
.oNEXT_SHIFT(load_shift), //It's for after load data sigals
.oNEXT_MASK(load_mask) //It's for after load data sigals
);
//Load Data Mask and Shft
wire [31:0] load_data;
execute_load_data LOAD_MASK(
.iMASK(load_mask),
.iSHIFT(load_shift),
.iDATA(iDATAIO_DATA),
.oDATA(load_data)
);
/****************************************
System Register
****************************************/
wire sysreg_ctrl_idt_valid;
wire sysreg_ctrl_pdt_valid;
wire sysreg_ctrl_psr_valid;
wire [31:0] sysreg_reload_addr;
execute_sys_reg EXE_SYS_REG(
.iCMD(iPREVIOUS_CMD),
.iPC(iPREVIOUS_PC),
.iSOURCE0(ex_module_source0),
.iSOURCE1(ex_module_source1),
.oOUT(sys_reg_data),
.oCTRL_IDT_VALID(sysreg_ctrl_idt_valid),
.oCTRL_PDT_VALID(sysreg_ctrl_pdt_valid),
.oCTRL_PSR_VALID(sysreg_ctrl_psr_valid),
.oCTRL_RELOAD_ADDR(sysreg_reload_addr)
);
/****************************************
Jump
****************************************/
//Branch
execute_branch EXE_BRANCH(
.iDATA_0(ex_module_source0),
.iDATA_1(ex_module_source1),
.iPC(iPREVIOUS_PC - 32'h4),
.iFLAG(sysreg_flags_register),
.iCC(iPREVIOUS_CC_AFE),
.iCMD(iPREVIOUS_CMD),
.oBRANCH_ADDR(branch_branch_addr),
.oJUMP_VALID(branch_jump_valid),
.oNOT_JUMP_VALID(branch_not_jump_valid),
.oIB_VALID(branch_ib_valid),
.oHALT_VALID(branch_halt_valid)
);
//Branch Predict
wire branch_with_predict_predict_ena;
wire branch_with_predict_predict_hit;
wire branch_with_predict_branch_valid;
wire branch_with_predict_ib_valid;
wire [31:0] branch_with_predict_jump_addr;
//Branch Predicter
execute_branch_predict EXE_BRANCH_PREDICT(
//State
.iSTATE_NORMAL(b_state == L_PARAM_STT_NORMAL),
//Previous - PREDICT
.iPREV_VALID(iPREVIOUS_VALID),
.iPREV_EX_BRANCH(iPREVIOUS_EX_BRANCH),
.iPREV_BRANCH_PREDICT_ENA(iPREVIOUS_BRANCH_PREDICT),
.iPREV_BRANCH_PREDICT_ADDR(iPREVIOUS_BRANCH_PREDICT_ADDR),
//BRANCH
.iPREV_BRANCH_VALID(branch_jump_valid),
.iPREV_BRANCH_IB_VALID(branch_ib_valid),
.iPREV_JUMP_ADDR(branch_branch_addr),
//Next
.iNEXT_BUSY(lock_condition),
.oNEXT_PREDICT_HIT(branch_with_predict_predict_hit)
);
wire branch_valid_with_predict_miss = branch_not_jump_valid && iPREVIOUS_BRANCH_PREDICT; //not need jump, but predict jump
wire branch_valid_with_predict_addr_miss = branch_jump_valid && !(iPREVIOUS_BRANCH_PREDICT && branch_with_predict_predict_hit); //need jump, but predict addr is diffelent (predict address diffelent)
wire branch_valid_with_predict = branch_valid_with_predict_miss || branch_valid_with_predict_addr_miss;
//Jump
wire jump_stage_predict_ena;
wire jump_stage_predict_hit;
wire jump_stage_jump_valid;
wire [31:0] jump_stage_jump_addr;
wire jump_normal_jump_inst;
wire jump_stage_branch_valid;
wire jump_stage_branch_ib_valid;
wire jump_stage_sysreg_idt_valid;
wire jump_stage_sysreg_pdt_valid;
wire jump_stage_sysreg_psr_valid;
execute_jump STAGE_JUMP(
.iCLOCK(iCLOCK),
.inRESET(inRESET),
.iRESET_SYNC(iRESET_SYNC),
//Event CTRL
.iEVENT_HOLD(iEVENT_HOLD),
.iEVENT_START(iEVENT_START),
.iEVENT_IRQ_FRONT2BACK(iEVENT_IRQ_FRONT2BACK),
.iEVENT_IRQ_BACK2FRONT(iEVENT_IRQ_BACK2FRONT),
.iEVENT_END(iEVENT_END),
//State
.iSTATE_NORMAL(b_state == L_PARAM_STT_NORMAL),
//Previous - PREDICT
.iPREV_VALID(iPREVIOUS_VALID),
.iPREV_EX_BRANCH(iPREVIOUS_EX_BRANCH),
.iPREV_EX_SYS_REG(iPREVIOUS_EX_SYS_REG),
.iPREV_PC(iPREVIOUS_PC),
.iPREV_BRANCH_PREDICT_ENA(iPREVIOUS_BRANCH_PREDICT),
.iPREV_BRANCH_PREDICT_HIT(branch_with_predict_predict_hit),
.iPREV_BRANCH_NORMAL_JUMP_INST(branch_jump_valid || branch_not_jump_valid), //ignore branch predict result
//BRANCH
.iPREV_BRANCH_PREDICT_MISS_VALID(branch_valid_with_predict_miss),
.iPREV_BRANCH_PREDICT_ADDR_MISS_VALID(branch_valid_with_predict_addr_miss),
.iPREV_BRANCH_IB_VALID(branch_ib_valid),
.iPREV_BRANCH_ADDR(branch_branch_addr),
//SYSREG JUMP
.iPREV_SYSREG_IDT_VALID(sysreg_ctrl_idt_valid),
.iPREV_SYSREG_PDT_VALID(sysreg_ctrl_pdt_valid),
.iPREV_SYSREG_PSR_VALID(sysreg_ctrl_psr_valid),
.iPREV_SYSREG_ADDR(sysreg_reload_addr),
/*************************************
Next
*************************************/
//Next
.iNEXT_BUSY(lock_condition),
.oNEXT_PREDICT_ENA(jump_stage_predict_ena),
.oNEXT_PREDICT_HIT(jump_stage_predict_hit),
.oNEXT_JUMP_VALID(jump_stage_jump_valid),
.oNEXT_JUMP_ADDR(jump_stage_jump_addr),
//for Branch Predictor
.oNEXT_NORMAL_JUMP_INST(jump_normal_jump_inst), //ignore branch predict result
//Kaind of Jump
.oNEXT_TYPE_BRANCH_VALID(jump_stage_branch_valid),
.oNEXT_TYPE_BRANCH_IB_VALID(jump_stage_branch_ib_valid),
.oNEXT_TYPE_SYSREG_IDT_VALID(jump_stage_sysreg_idt_valid),
.oNEXT_TYPE_SYSREG_PDT_VALID(jump_stage_sysreg_pdt_valid),
.oNEXT_TYPE_SYSREG_PSR_VALID(jump_stage_sysreg_psr_valid)
);
/*********************************************************************************************************
Exception
*********************************************************************************************************/
wire except_inst_valid;
wire [6:0] except_inst_num;
wire except_ldst_valid;
wire [6:0] except_ldst_num;
execute_exception_check_inst EXE_EXCEPTION_INST(
//Execute Module State
.iPREV_STATE_NORMAL(b_state == L_PARAM_STT_NORMAL),
//Previous Instruxtion
.iPREV_FAULT_PAGEFAULT(iPREVIOUS_FAULT_PAGEFAULT),
.iPREV_FAULT_PRIVILEGE_ERROR(iPREVIOUS_FAULT_PRIVILEGE_ERROR),
.iPREV_FAULT_INVALID_INST(iPREVIOUS_FAULT_INVALID_INST),
.iPREV_FAULT_DIVIDE_ZERO((iPREVIOUS_EX_SDIV || iPREVIOUS_EX_UDIV) && (ex_module_source1 == 32'h0)),
//Output Exception
.oEXCEPT_VALID(except_inst_valid),
.oEXCEPT_NUM(except_inst_num)
);
execute_exception_check_ldst EXE_EXCEPTION_LDST(
.iCLOCK(iCLOCK),
.inRESET(inRESET),
.iRESET_SYNC(iRESET_SYNC),
//Event CTRL
.iEVENT_HOLD(iEVENT_HOLD),
.iEVENT_START(iEVENT_START),
.iEVENT_IRQ_FRONT2BACK(iEVENT_IRQ_FRONT2BACK),
.iEVENT_IRQ_BACK2FRONT(iEVENT_IRQ_BACK2FRONT),
.iEVENT_END(iEVENT_END),
//Execute Module State
.iPREV_STATE_NORMAL(b_state == L_PARAM_STT_NORMAL),
.iPREV_STATE_LDST(b_state == L_PARAM_STT_LOAD),
//Previous Instruxtion
.iPREV_VALID(b_state == L_PARAM_STT_NORMAL && iPREVIOUS_VALID && !lock_condition),
.iPREV_KERNEL_ACCESS(iPREVIOUS_KERNEL_ACCESS),
.iPREV_PAGING_ENA(iPREVIOUS_PAGING_ENA),
.iPREV_LDST_RW(ldst_pipe_rw),
//Load Store
.iLDST_VALID(iDATAIO_REQ),
.iLDST_MMU_FLAG(iDATAIO_MMU_FLAGS),
//Output Exception
.oEXCEPT_VALID(except_ldst_valid),
.oEXCEPT_NUM(except_ldst_num)
);
wire exception_valid;
wire [6:0] exception_num;
wire [31:0] exception_fi0r;
wire [31:0] exception_fi1r;
execute_exception STAGE_EXCEPTION(
.iCLOCK(iCLOCK),
.inRESET(inRESET),
.iRESET_SYNC(iRESET_SYNC),
//Event CTRL
.iEVENT_HOLD(iEVENT_HOLD),
.iEVENT_START(iEVENT_START),
.iEVENT_IRQ_FRONT2BACK(iEVENT_IRQ_FRONT2BACK),
.iEVENT_IRQ_BACK2FRONT(iEVENT_IRQ_BACK2FRONT),
.iEVENT_END(iEVENT_END),
//Execute Module State
.iPREV_STATE_NORMAL(b_state == L_PARAM_STT_NORMAL),
.iPREV_STATE_LDST(b_state == L_PARAM_STT_LOAD),
//Previous Instruxtion
.iPREV_VALID(b_state == L_PARAM_STT_NORMAL && iPREVIOUS_VALID && !lock_condition),
.iPREV_KERNEL_ACCESS(iPREVIOUS_KERNEL_ACCESS),
.iPREV_PC(iPREVIOUS_PC),
//Instruction Exception
.iEXCEPT_INST_VALID(except_inst_valid),
.iEXCEPT_INST_NUM(except_inst_num),
//Load Store Exception
.iEXCEPT_LDST_VALID(except_ldst_valid),
.iEXCEPT_LDST_NUM(except_ldst_num),
//Output Exception
.oEXCEPT_VALID(exception_valid),
.oEXCEPT_NUM(exception_num),
.oEXCEPT_FI0R(exception_fi0r),
.oEXCEPT_FI1R(exception_fi1r)
);
/*********************************************************************************************************
Pipelined Register
*********************************************************************************************************/
/****************************************
State
****************************************/
always@(posedge iCLOCK or negedge inRESET)begin
if(!inRESET)begin
b_state <= L_PARAM_STT_NORMAL;
end
else if(iEVENT_HOLD || iEVENT_START || iRESET_SYNC)begin
b_state <= L_PARAM_STT_NORMAL;
end
else begin
case(b_state)
L_PARAM_STT_NORMAL:
begin
if(iPREVIOUS_VALID && !lock_condition)begin
//Fault Check
if(except_inst_valid)begin
b_state <= L_PARAM_STT_EXCEPTION;
end
//Execute
else begin
//Div instruction
if(iPREVIOUS_EX_SDIV || iPREVIOUS_EX_UDIV)begin
b_state <= L_PARAM_STT_DIV_WAIT;
end
//Load Store
else if(iPREVIOUS_EX_LDST)begin
if(!ldst_pipe_rw)begin
b_state <= L_PARAM_STT_LOAD;
end
else begin
b_state <= L_PARAM_STT_STORE;
end
end
//Branch
else if(iPREVIOUS_EX_BRANCH)begin
//Halt
if(branch_halt_valid)begin
b_state <= L_PARAM_STT_HALT;
end
//Interrupt Return Branch
else if(branch_ib_valid)begin
b_state <= L_PARAM_STT_BRANCH;
end
//Branch(with Branch predict)
else if(branch_valid_with_predict)begin
b_state <= L_PARAM_STT_BRANCH;
end
end
//System Register(for need re-load instructions)
if(iPREVIOUS_EX_SYS_REG)begin
if(sysreg_ctrl_idt_valid || sysreg_ctrl_pdt_valid || sysreg_ctrl_psr_valid)begin
b_state <= L_PARAM_STT_RELOAD;
end
end
end
end
end
L_PARAM_STT_DIV_WAIT:
begin
if(div_out_valid)begin
b_state <= L_PARAM_STT_NORMAL;
end
end
L_PARAM_STT_LOAD:
begin
if(iDATAIO_REQ)begin
//Pagefault || Exception Check(Load)
if(except_ldst_valid)begin
b_state <= L_PARAM_STT_EXCEPTION;
end
//Non Error
else begin
b_state <= L_PARAM_STT_NORMAL;
end
end
end
L_PARAM_STT_STORE:
begin
if(iDATAIO_REQ)begin
//Pagefault
//Exception Check(Load)
if(except_ldst_valid)begin
b_state <= L_PARAM_STT_EXCEPTION;
end
//Non Error
else begin
b_state <= L_PARAM_STT_NORMAL;
end
end
end
L_PARAM_STT_BRANCH:
begin
//Branch Wait
b_state <= L_PARAM_STT_BRANCH;
end
L_PARAM_STT_RELOAD:
begin
//Branch Wait
b_state <= L_PARAM_STT_RELOAD;
end
L_PARAM_STT_EXCEPTION:
begin
b_state <= L_PARAM_STT_EXCEPTION;
end
L_PARAM_STT_HALT:
begin
b_state <= L_PARAM_STT_HALT;
end
endcase
end
end //state always
/****************************************
For PC
****************************************/
always@(posedge iCLOCK or negedge inRESET)begin
if(!inRESET)begin
b_pc <= 32'h0;
end
else if(iEVENT_HOLD || iEVENT_START || iRESET_SYNC)begin
b_pc <= 32'h0;
end
else begin
case(b_state)
L_PARAM_STT_NORMAL:
begin
if(iPREVIOUS_VALID && !lock_condition)begin
b_pc <= iPREVIOUS_PC;
end
end
default:
begin
b_pc <= b_pc;
end
endcase
end
end
/****************************************
For FRCR
****************************************/
always@(posedge iCLOCK or negedge inRESET)begin
if(!inRESET)begin
b_frcr <= 64'h0;
end
else if(iEVENT_HOLD || iEVENT_START || iRESET_SYNC)begin
b_frcr <= 64'h0;
end
else begin
case(b_state)
L_PARAM_STT_NORMAL:
begin
if(iPREVIOUS_VALID && !lock_condition)begin
b_frcr <= iPREVIOUS_SYSREG_FRCR;
end
end
default:
begin
b_frcr <= b_frcr;
end
endcase
end
end
/****************************************
Result Data
****************************************/
always@(posedge iCLOCK or negedge inRESET)begin
if(!inRESET)begin
b_r_data <= 32'h0;
end
else if(iEVENT_HOLD || iEVENT_START || iRESET_SYNC)begin
b_r_data <= 32'h0;
end
else begin
case(b_state)
L_PARAM_STT_NORMAL:
begin
if(iPREVIOUS_VALID && !lock_condition)begin
//SPR Read Store
if(iPREVIOUS_EX_SYS_LDST)begin
b_r_data <= ldst_spr;
end
//System Register
else if(iPREVIOUS_EX_SYS_REG)begin
b_r_data <= sys_reg_data;
end
//Logic
else if(iPREVIOUS_EX_LOGIC)begin
b_r_data <= logic_data;
end
//SHIFT
else if(iPREVIOUS_EX_SHIFT)begin
b_r_data <= shift_data;
end
//ADDER
else if(iPREVIOUS_EX_ADDER)begin
b_r_data <= adder_data;
end
//MUL
else if(iPREVIOUS_EX_MUL)begin
b_r_data <= mul_data;
end
//Error
else begin
b_r_data <= 32'h0;
end
end
end
L_PARAM_STT_DIV_WAIT:
begin
if(div_out_valid)begin
b_r_data <= div_out_data;
end
else begin
b_r_data <= 32'h0;
end
end
L_PARAM_STT_LOAD:
begin
if(iDATAIO_REQ)begin
b_r_data <= load_data;
end
end
default:
begin
b_r_data <= 32'h0;
end
endcase
end
end
always@(posedge iCLOCK or negedge inRESET)begin
if(!inRESET)begin
b_r_spr <= 32'h0;
end
else if(iEVENT_HOLD || iEVENT_START || iRESET_SYNC)begin
b_r_spr <= 32'h0;
end
else begin
case(b_state)
L_PARAM_STT_NORMAL:
begin
if(iPREVIOUS_EX_LDST || iPREVIOUS_EX_SYS_LDST)begin
b_r_spr <= ldst_spr;
end
end
default:
begin
b_r_spr <= b_r_spr;
end
endcase
end
end
/****************************************
Execute Category
****************************************/
reg b_ex_category_ldst;
reg b_ex_category_branch;
always@(posedge iCLOCK or negedge inRESET)begin
if(!inRESET)begin
b_ex_category_ldst <= 1'b0;
end
else if(iEVENT_HOLD || iEVENT_START || iRESET_SYNC)begin
b_ex_category_ldst <= 1'b0;
end
else begin
if(b_state == L_PARAM_STT_NORMAL && iPREVIOUS_VALID && !lock_condition)begin
b_ex_category_ldst <= iPREVIOUS_EX_LDST;
b_ex_category_branch <= iPREVIOUS_EX_BRANCH;
end
end
end
/****************************************
Pass Line
****************************************/
always@(posedge iCLOCK or negedge inRESET)begin
if(!inRESET)begin
b_writeback <= 1'b0;
b_destination_sysreg <= 1'b0;
b_destination <= 5'h0;
b_afe <= 4'h0;
b_spr_writeback <= 1'b0;
end
else if(iEVENT_HOLD || iRESET_SYNC || iEVENT_START)begin
b_writeback <= 1'b0;
b_destination_sysreg <= 1'b0;
b_destination <= 5'h0;
b_afe <= 4'h0;
b_spr_writeback <= 1'b0;
end
else if(b_state == L_PARAM_STT_NORMAL)begin
if(iPREVIOUS_VALID && !lock_condition)begin
if(iPREVIOUS_EX_SDIV || iPREVIOUS_EX_UDIV || iPREVIOUS_EX_LDST || iPREVIOUS_EX_SYS_LDST || iPREVIOUS_EX_SYS_REG || iPREVIOUS_EX_LOGIC || iPREVIOUS_EX_SHIFT || iPREVIOUS_EX_ADDER || iPREVIOUS_EX_MUL)begin
b_writeback <= iPREVIOUS_WRITEBACK && (!except_inst_valid);
b_destination_sysreg <= iPREVIOUS_DESTINATION_SYSREG;
b_destination <= iPREVIOUS_DESTINATION;
b_afe <= iPREVIOUS_CC_AFE;
b_spr_writeback <= (iPREVIOUS_EX_LDST || iPREVIOUS_EX_SYS_LDST) && ldst_spr_valid;
end
else if(iPREVIOUS_EX_BRANCH)begin
b_writeback <= 1'b0;
b_destination_sysreg <= iPREVIOUS_DESTINATION_SYSREG;
b_destination <= iPREVIOUS_DESTINATION;
b_afe <= iPREVIOUS_CC_AFE;
b_spr_writeback <= 1'b0;
end
end
end
end
/****************************************
Valid
****************************************/
always@(posedge iCLOCK or negedge inRESET)begin
if(!inRESET)begin
b_valid <= 1'b0;
end
else if(iEVENT_HOLD || iEVENT_START || iRESET_SYNC)begin
b_valid <= 1'b0;
end
else begin
case(b_state)
L_PARAM_STT_NORMAL:
begin
//Fault Check
if(iPREVIOUS_VALID && !lock_condition && except_inst_valid)begin
b_valid <= 1'b1;
end
else if(iPREVIOUS_VALID && !lock_condition && (iPREVIOUS_EX_SDIV || iPREVIOUS_EX_UDIV || (iPREVIOUS_EX_LDST && !ldst_pipe_rw)))begin
b_valid <= 1'b0;
end
else if(iPREVIOUS_VALID && !lock_condition && iPREVIOUS_EX_BRANCH)begin
//Halt
if(branch_halt_valid)begin
b_valid <= 1'b1;
end
//Interrupt Return Branch
else if(branch_ib_valid)begin
b_valid <= 1'b1;
end
//Branch(with Branch predict) - True
else if(branch_valid_with_predict)begin
b_valid <= 1'b1;
end
else if(branch_with_predict_predict_hit)begin
b_valid <= 1'b1;
end
else begin
//b_valid <= 1'b0;
b_valid <= 1'b1;
end
end
else begin
b_valid <= iPREVIOUS_VALID && !lock_condition;
end
end
L_PARAM_STT_DIV_WAIT:
begin
if(div_out_valid)begin
b_valid <= 1'b1;
end
end
L_PARAM_STT_LOAD:
begin
if(iDATAIO_REQ)begin
//not error
if(!except_ldst_valid)begin
b_valid <= 1'b1;
end
end
end
L_PARAM_STT_STORE:
begin
if(iDATAIO_REQ)begin
//not error
if(!except_ldst_valid)begin
b_valid <= 1'b1;
end
end
end
default:
begin
b_valid <= 1'b0;
end
endcase
end
end
/*********************************************************************************************************
AFE
*********************************************************************************************************/
/****************************************
AFE - for Load Store
****************************************/
wire [31:0] afe_ldst_data_result;
execute_afe_load_store AFE_LDST(
//AFE-Conrtol
.iAFE_CODE(b_afe),
//Data-In/Out
.iDATA(b_r_data),
.oDATA(afe_ldst_data_result)
);
/****************************************
AFE - Select
****************************************/
execute_afe AFE_SELECT(
.iAFE_LDST(b_ex_category_ldst),
.iAFE_LDST_DATA(afe_ldst_data_result),
.iRAW_DATA(b_r_data),
.oDATA(result_data_with_afe)
);
/*********************************************************************************************************
Assign
*********************************************************************************************************/
//Fault
assign oFAULT_VALID = exception_valid;
assign oFAULT_NUM = exception_num;
assign oFAULT_FI0R = exception_fi0r;
assign oFAULT_FI1R = exception_fi1r;
//Branch Predict
assign oBPREDICT_JUMP_INST = jump_normal_jump_inst; //Is normal jump Instruction?
assign oBPREDICT_PREDICT = jump_stage_predict_ena;
assign oBPREDICT_HIT = b_ex_category_branch && (jump_stage_predict_hit);
assign oBPREDICT_JUMP = jump_stage_jump_valid; //it same of Unhit
assign oBPREDICT_JUMP_ADDR = jump_stage_jump_addr;
assign oBPREDICT_INST_ADDR = b_pc - 32'h00000004;
//Branch - Controller
assign oBRANCH_ADDR = jump_stage_jump_addr;
assign oJUMP_VALID = jump_stage_jump_valid;
assign oINTR_VALID = jump_stage_branch_ib_valid;
assign oIDTSET_VALID = jump_stage_sysreg_idt_valid;
assign oPDTSET_VALID = jump_stage_sysreg_pdt_valid;
assign oPSRSET_VALID = jump_stage_sysreg_psr_valid;
//Writeback
assign oNEXT_VALID = b_valid && !iEVENT_HOLD;
assign oNEXT_DATA = result_data_with_afe;
assign oNEXT_DESTINATION = b_destination;
assign oNEXT_DESTINATION_SYSREG = b_destination_sysreg;
assign oNEXT_WRITEBACK = b_writeback && !except_ldst_valid && (b_state != L_PARAM_STT_BRANCH);
assign oNEXT_SPR_WRITEBACK = b_spr_writeback && !except_ldst_valid && (b_state != L_PARAM_STT_BRANCH);
assign oNEXT_SPR = b_r_spr;
assign oNEXT_FRCR = b_frcr;
assign oNEXT_PC = b_pc;
//System Register Writeback
assign oPDTR_WRITEBACK = b_destination_sysreg && b_writeback && (b_destination == `SYSREG_PDTR);
assign oEXCEPTION_LOCK = (b_state == L_PARAM_STT_DIV_WAIT) || (b_state == L_PARAM_STT_LOAD) || (b_state == L_PARAM_STT_STORE) || (b_state == L_PARAM_STT_RELOAD);
assign oSYSREG_FLAGR = {27'h0, sysreg_flags_register};
/*********************************************************************************************************
Assertion
*********************************************************************************************************/
/*************************************************
Assertion - SVA
*************************************************/
//synthesis translate_off
`ifdef MIST1032ISA_SVA_ASSERTION
property PRO_DATAPIPE_REQ_ACK;
@(posedge iCLOCK) disable iff (!inRESET || iEVENT_START || iRESET_SYNC) (oDATAIO_REQ |-> ##[1:50] iDATAIO_REQ);
endproperty
assert property(PRO_DATAPIPE_REQ_ACK);
`endif
//synthesis translate_on
/*************************************************
Verilog Assertion
*************************************************/
//synthesis translate_off
function [31:0] func_assert_write_data;
input [4:0] func_mask;
input [31:0] func_data;
begin
if(func_mask == 4'hf)begin
func_assert_write_data = func_data;
end
else if(func_mask == 4'b0011)begin
func_assert_write_data = {16'h0, func_data[15:0]};
end
else if(func_mask == 4'b1100)begin
func_assert_write_data = {16'h0, func_data[31:16]};
end
else if(func_mask == 4'b1000)begin
func_assert_write_data = {24'h0, func_data[31:24]};
end
else if(func_mask == 4'b0100)begin
func_assert_write_data = {24'h0, func_data[23:16]};
end
else if(func_mask == 4'b0010)begin
func_assert_write_data = {24'h0, func_data[15:8]};
end
else if(func_mask == 4'b0001)begin
func_assert_write_data = {24'h0, func_data[7:0]};
end
else begin
func_assert_write_data = 32'h0;
end
end
endfunction
//`ifdef MIST1032ISA_VLG_ASSERTION
localparam time_ena = 0;
/*
integer F_HANDLE;
initial F_HANDLE = $fopen("ldst_time_dump.log");
*/
wire [31:0] for_assertion_store_real_data = func_assert_write_data(oDATAIO_MASK, oDATAIO_DATA);
//synthesis translate_on
/*
--------------------------------
[S], "PC", "spr", "addr", "data"
[L], "PC", "spr", "addr", "data"
--------------------------------
*/
endmodule
|
module hapara_axis_id_dispatcher_v1_0 #
(
// Users to add parameters here
parameter integer NUM_SLAVES = 1,
parameter integer DATA_WIDTH = 32
// User parameters ends
)
(
// Users to add ports here
input wire [NUM_SLAVES-1: 0] priority_sel,
// User ports ends
// Do not modify the ports beyond this line
// Ports of Axi Slave Bus Interface S00_AXIS
input wire s00_axis_aclk,
input wire s00_axis_aresetn,
output wire s00_axis_tready,
input wire [DATA_WIDTH-1 : 0] s00_axis_tdata,
input wire s00_axis_tlast,
input wire s00_axis_tvalid,
// Ports of Axi Master Bus Interface M00_AXIS
input wire m00_axis_aclk,
input wire m00_axis_aresetn,
output wire m00_axis_tvalid,
output wire [DATA_WIDTH-1 : 0] m00_axis_tdata,
output wire m00_axis_tlast,
input wire m00_axis_tready,
// Ports of Axi Master Bus Interface M01_AXIS
input wire m01_axis_aclk,
input wire m01_axis_aresetn,
output wire m01_axis_tvalid,
output wire [DATA_WIDTH-1 : 0] m01_axis_tdata,
output wire m01_axis_tlast,
input wire m01_axis_tready,
// Ports of Axi Master Bus Interface M02_AXIS
input wire m02_axis_aclk,
input wire m02_axis_aresetn,
output wire m02_axis_tvalid,
output wire [DATA_WIDTH-1 : 0] m02_axis_tdata,
output wire m02_axis_tlast,
input wire m02_axis_tready,
// Ports of Axi Master Bus Interface M03_AXIS
input wire m03_axis_aclk,
input wire m03_axis_aresetn,
output wire m03_axis_tvalid,
output wire [DATA_WIDTH-1 : 0] m03_axis_tdata,
output wire m03_axis_tlast,
input wire m03_axis_tready,
// Ports of Axi Master Bus Interface M04_AXIS
input wire m04_axis_aclk,
input wire m04_axis_aresetn,
output wire m04_axis_tvalid,
output wire [DATA_WIDTH-1 : 0] m04_axis_tdata,
output wire m04_axis_tlast,
input wire m04_axis_tready,
// Ports of Axi Master Bus Interface M05_AXIS
input wire m05_axis_aclk,
input wire m05_axis_aresetn,
output wire m05_axis_tvalid,
output wire [DATA_WIDTH-1 : 0] m05_axis_tdata,
output wire m05_axis_tlast,
input wire m05_axis_tready,
// Ports of Axi Master Bus Interface M06_AXIS
input wire m06_axis_aclk,
input wire m06_axis_aresetn,
output wire m06_axis_tvalid,
output wire [DATA_WIDTH-1 : 0] m06_axis_tdata,
output wire m06_axis_tlast,
input wire m06_axis_tready,
// Ports of Axi Master Bus Interface M07_AXIS
input wire m07_axis_aclk,
input wire m07_axis_aresetn,
output wire m07_axis_tvalid,
output wire [DATA_WIDTH-1 : 0] m07_axis_tdata,
output wire m07_axis_tlast,
input wire m07_axis_tready
);
localparam dispatch = 4'b0001;
localparam waitslave = 4'b0010;
localparam terminate = 4'b0100;
localparam waitdata = 4'b1000;
reg [3 : 0] curr_state;
reg [3 : 0] next_state;
// Logic for curr_state
always @(posedge s00_axis_aclk) begin
if (!s00_axis_aresetn) begin
// reset
curr_state <= dispatch;
end
else begin
curr_state <= next_state;
end
end
wire slaves_ready;
// Logic for next_state
always @(s00_axis_tdata or slaves_ready or curr_state) begin
case (curr_state)
dispatch:
if (s00_axis_tdata == {DATA_WIDTH{1'b1}}) begin
next_state = waitslave;
end
else begin
next_state = dispatch;
end
waitslave:
if (slaves_ready) begin
next_state = terminate;
end
else begin
next_state = waitslave;
end
terminate:
next_state = waitdata;
waitdata:
if (s00_axis_tdata != {DATA_WIDTH{1'b1}}) begin
next_state = dispatch;
end
else begin
next_state = waitdata;
end
default:
next_state = 3'bxxx;
endcase
end
assign m00_axis_tdata = s00_axis_tdata;
assign m00_axis_tlast = s00_axis_tlast;
assign m01_axis_tdata = s00_axis_tdata;
assign m01_axis_tlast = s00_axis_tlast;
assign m02_axis_tdata = s00_axis_tdata;
assign m02_axis_tlast = s00_axis_tlast;
assign m03_axis_tdata = s00_axis_tdata;
assign m03_axis_tlast = s00_axis_tlast;
assign m04_axis_tdata = s00_axis_tdata;
assign m04_axis_tlast = s00_axis_tlast;
assign m05_axis_tdata = s00_axis_tdata;
assign m05_axis_tlast = s00_axis_tlast;
assign m06_axis_tdata = s00_axis_tdata;
assign m06_axis_tlast = s00_axis_tlast;
assign m07_axis_tdata = s00_axis_tdata;
assign m07_axis_tlast = s00_axis_tlast;
// Add user logic here
generate if (NUM_SLAVES == 1)
begin: NUM_SLAVES_1
assign s00_axis_tready = (curr_state == dispatch || curr_state == terminate) &&
m00_axis_tready;
assign m00_axis_tvalid = (curr_state == terminate) ||
(curr_state == dispatch &&
s00_axis_tdata != {DATA_WIDTH{1'b1}} &&
s00_axis_tvalid &&
priority_sel[0]);
assign slaves_ready = m00_axis_tready;
end
endgenerate
generate if (NUM_SLAVES == 2)
begin: NUM_SLAVES_2
assign s00_axis_tready = (curr_state == dispatch || curr_state == terminate) &&
(m00_axis_tready ||
m01_axis_tready);
assign m00_axis_tvalid = (curr_state == terminate) ||
(curr_state == dispatch &&
s00_axis_tdata != {DATA_WIDTH{1'b1}} &&
s00_axis_tvalid &&
~priority_sel[1] &&
priority_sel[0]);
assign m01_axis_tvalid = (curr_state == terminate) ||
(curr_state == dispatch &&
s00_axis_tdata != {DATA_WIDTH{1'b1}} &&
s00_axis_tvalid &&
priority_sel[1]);
assign slaves_ready = m00_axis_tready &
m01_axis_tready;
end
endgenerate
generate if (NUM_SLAVES == 3)
begin: NUM_SLAVES_3
assign s00_axis_tready = (curr_state == dispatch || curr_state == terminate) &&
(m00_axis_tready ||
m01_axis_tready ||
m02_axis_tready);
assign m00_axis_tvalid = (curr_state == terminate) ||
(curr_state == dispatch &&
s00_axis_tdata != {DATA_WIDTH{1'b1}} &&
s00_axis_tvalid &&
s00_axis_tvalid &&
~priority_sel[2] &&
~priority_sel[1] &&
priority_sel[0]);
assign m01_axis_tvalid = (curr_state == terminate) ||
(curr_state == dispatch &&
s00_axis_tdata != {DATA_WIDTH{1'b1}} &&
s00_axis_tvalid &&
~priority_sel[2] &&
priority_sel[1]);
assign m02_axis_tvalid = (curr_state == terminate) ||
(curr_state == dispatch &&
s00_axis_tdata != {DATA_WIDTH{1'b1}} &&
s00_axis_tvalid &&
priority_sel[2]);
assign slaves_ready = m00_axis_tready &
m01_axis_tready &
m02_axis_tready;
end
endgenerate
generate if (NUM_SLAVES == 4)
begin: NUM_SLAVES_4
assign s00_axis_tready = (curr_state == dispatch || curr_state == terminate) &&
(m00_axis_tready ||
m01_axis_tready ||
m02_axis_tready ||
m03_axis_tready);
assign m00_axis_tvalid = (curr_state == terminate) ||
(curr_state == dispatch &&
s00_axis_tdata != {DATA_WIDTH{1'b1}} &&
s00_axis_tvalid &&
~priority_sel[3] &&
~priority_sel[2] &&
~priority_sel[1] &&
priority_sel[0]);
assign m01_axis_tvalid = (curr_state == terminate) ||
(curr_state == dispatch &&
s00_axis_tdata != {DATA_WIDTH{1'b1}} &&
s00_axis_tvalid &&
~priority_sel[3] &&
~priority_sel[2] &&
priority_sel[1]);
assign m02_axis_tvalid = (curr_state == terminate) ||
(curr_state == dispatch &&
s00_axis_tdata != {DATA_WIDTH{1'b1}} &&
s00_axis_tvalid &&
~priority_sel[3] &&
priority_sel[2]);
assign m03_axis_tvalid = (curr_state == terminate) ||
(curr_state == dispatch &&
s00_axis_tdata != {DATA_WIDTH{1'b1}} &&
s00_axis_tvalid &&
priority_sel[3]);
assign slaves_ready = m00_axis_tready &
m01_axis_tready &
m02_axis_tready &
m03_axis_tready;
end
endgenerate
generate if (NUM_SLAVES == 5)
begin: NUM_SLAVES_5
assign s00_axis_tready = (curr_state == dispatch || curr_state == terminate) &&
(m00_axis_tready ||
m01_axis_tready ||
m02_axis_tready ||
m03_axis_tready ||
m04_axis_tready);
assign m00_axis_tvalid = (curr_state == terminate) ||
(curr_state == dispatch &&
s00_axis_tdata != {DATA_WIDTH{1'b1}} &&
s00_axis_tvalid &&
~priority_sel[4] &&
~priority_sel[3] &&
~priority_sel[2] &&
~priority_sel[1] &&
priority_sel[0]);
assign m01_axis_tvalid = (curr_state == terminate) ||
(curr_state == dispatch &&
s00_axis_tdata != {DATA_WIDTH{1'b1}} &&
s00_axis_tvalid &&
~priority_sel[4] &&
~priority_sel[3] &&
~priority_sel[2] &&
priority_sel[1]);
assign m02_axis_tvalid = (curr_state == terminate) ||
(curr_state == dispatch &&
s00_axis_tdata != {DATA_WIDTH{1'b1}} &&
s00_axis_tvalid &&
~priority_sel[4] &&
~priority_sel[3] &&
priority_sel[2]);
assign m03_axis_tvalid = (curr_state == terminate) ||
(curr_state == dispatch &&
s00_axis_tdata != {DATA_WIDTH{1'b1}} &&
s00_axis_tvalid &&
~priority_sel[4] &&
priority_sel[3]);
assign m04_axis_tvalid = (curr_state == terminate) ||
(curr_state == dispatch &&
s00_axis_tdata != {DATA_WIDTH{1'b1}} &&
s00_axis_tvalid &&
priority_sel[4]);
assign slaves_ready = m00_axis_tready &
m01_axis_tready &
m02_axis_tready &
m03_axis_tready &
m04_axis_tready;
end
endgenerate
generate if (NUM_SLAVES == 6)
begin: NUM_SLAVES_6
assign s00_axis_tready = (curr_state == dispatch || curr_state == terminate) &&
(m00_axis_tready ||
m01_axis_tready ||
m02_axis_tready ||
m03_axis_tready ||
m04_axis_tready ||
m05_axis_tready);
assign m00_axis_tvalid = (curr_state == terminate) ||
(curr_state == dispatch &&
s00_axis_tdata != {DATA_WIDTH{1'b1}} &&
s00_axis_tvalid &&
~priority_sel[5] &&
~priority_sel[4] &&
~priority_sel[3] &&
~priority_sel[2] &&
~priority_sel[1] &&
priority_sel[0]);
assign m01_axis_tvalid = (curr_state == terminate) ||
(curr_state == dispatch &&
s00_axis_tdata != {DATA_WIDTH{1'b1}} &&
s00_axis_tvalid &&
~priority_sel[5] &&
~priority_sel[4] &&
~priority_sel[3] &&
~priority_sel[2] &&
priority_sel[1]);
assign m02_axis_tvalid = (curr_state == terminate) ||
(curr_state == dispatch &&
s00_axis_tdata != {DATA_WIDTH{1'b1}} &&
s00_axis_tvalid &&
~priority_sel[5] &&
~priority_sel[4] &&
~priority_sel[3] &&
priority_sel[2]);
assign m03_axis_tvalid = (curr_state == terminate) ||
(curr_state == dispatch &&
s00_axis_tdata != {DATA_WIDTH{1'b1}} &&
s00_axis_tvalid &&
~priority_sel[5] &&
~priority_sel[4] &&
priority_sel[3]);
assign m04_axis_tvalid = (curr_state == terminate) ||
(curr_state == dispatch &&
s00_axis_tdata != {DATA_WIDTH{1'b1}} &&
s00_axis_tvalid &&
~priority_sel[5] &&
priority_sel[4]);
assign m05_axis_tvalid = (curr_state == terminate) ||
(curr_state == dispatch &&
s00_axis_tdata != {DATA_WIDTH{1'b1}} &&
s00_axis_tvalid &&
priority_sel[5]);
assign slaves_ready = m00_axis_tready &
m01_axis_tready &
m02_axis_tready &
m03_axis_tready &
m04_axis_tready &
m05_axis_tready;
end
endgenerate
generate if (NUM_SLAVES == 7)
begin: NUM_SLAVES_7
assign s00_axis_tready = (curr_state == dispatch || curr_state == terminate) &&
(m00_axis_tready ||
m01_axis_tready ||
m02_axis_tready ||
m03_axis_tready ||
m04_axis_tready ||
m05_axis_tready ||
m06_axis_tready);
assign m00_axis_tvalid = (curr_state == terminate) ||
(curr_state == dispatch &&
s00_axis_tdata != {DATA_WIDTH{1'b1}} &&
s00_axis_tvalid &&
~priority_sel[6] &&
~priority_sel[5] &&
~priority_sel[4] &&
~priority_sel[3] &&
~priority_sel[2] &&
~priority_sel[1] &&
priority_sel[0]);
assign m01_axis_tvalid = (curr_state == terminate) ||
(curr_state == dispatch &&
s00_axis_tdata != {DATA_WIDTH{1'b1}} &&
s00_axis_tvalid &&
~priority_sel[6] &&
~priority_sel[5] &&
~priority_sel[4] &&
~priority_sel[3] &&
~priority_sel[2] &&
priority_sel[1]);
assign m02_axis_tvalid = (curr_state == terminate) ||
(curr_state == dispatch &&
s00_axis_tdata != {DATA_WIDTH{1'b1}} &&
s00_axis_tvalid &&
~priority_sel[6] &&
~priority_sel[5] &&
~priority_sel[4] &&
~priority_sel[3] &&
priority_sel[2]);
assign m03_axis_tvalid = (curr_state == terminate) ||
(curr_state == dispatch &&
s00_axis_tdata != {DATA_WIDTH{1'b1}} &&
s00_axis_tvalid &&
~priority_sel[6] &&
~priority_sel[5] &&
~priority_sel[4] &&
priority_sel[3]);
assign m04_axis_tvalid = (curr_state == terminate) ||
(curr_state == dispatch &&
s00_axis_tdata != {DATA_WIDTH{1'b1}} &&
s00_axis_tvalid &&
~priority_sel[6] &&
~priority_sel[5] &&
priority_sel[4]);
assign m05_axis_tvalid = (curr_state == terminate) ||
(curr_state == dispatch &&
s00_axis_tdata != {DATA_WIDTH{1'b1}} &&
s00_axis_tvalid &&
~priority_sel[6] &&
priority_sel[5]);
assign m06_axis_tvalid = (curr_state == terminate) ||
(curr_state == dispatch &&
s00_axis_tdata != {DATA_WIDTH{1'b1}} &&
s00_axis_tvalid &&
priority_sel[6]);
assign slaves_ready = m00_axis_tready &
m01_axis_tready &
m02_axis_tready &
m03_axis_tready &
m04_axis_tready &
m05_axis_tready &
m06_axis_tready;
end
endgenerate
generate if (NUM_SLAVES == 8)
begin: NUM_SLAVES_8
assign s00_axis_tready = (curr_state == dispatch || curr_state == terminate) &&
(m00_axis_tready ||
m01_axis_tready ||
m02_axis_tready ||
m03_axis_tready ||
m04_axis_tready ||
m05_axis_tready ||
m06_axis_tready ||
m07_axis_tready);
assign m00_axis_tvalid = (curr_state == terminate) ||
(curr_state == dispatch &&
s00_axis_tdata != {DATA_WIDTH{1'b1}} &&
s00_axis_tvalid &&
~priority_sel[7] &&
~priority_sel[6] &&
~priority_sel[5] &&
~priority_sel[4] &&
~priority_sel[3] &&
~priority_sel[2] &&
~priority_sel[1] &&
priority_sel[0]);
assign m01_axis_tvalid = (curr_state == terminate) ||
(curr_state == dispatch &&
s00_axis_tdata != {DATA_WIDTH{1'b1}} &&
s00_axis_tvalid &&
~priority_sel[7] &&
~priority_sel[6] &&
~priority_sel[5] &&
~priority_sel[4] &&
~priority_sel[3] &&
~priority_sel[2] &&
priority_sel[1]);
assign m02_axis_tvalid = (curr_state == terminate) ||
(curr_state == dispatch &&
s00_axis_tdata != {DATA_WIDTH{1'b1}} &&
s00_axis_tvalid &&
~priority_sel[7] &&
~priority_sel[6] &&
~priority_sel[5] &&
~priority_sel[4] &&
~priority_sel[3] &&
priority_sel[2]);
assign m03_axis_tvalid = (curr_state == terminate) ||
(curr_state == dispatch &&
s00_axis_tdata != {DATA_WIDTH{1'b1}} &&
s00_axis_tvalid &&
~priority_sel[7] &&
~priority_sel[6] &&
~priority_sel[5] &&
~priority_sel[4] &&
priority_sel[3]);
assign m04_axis_tvalid = (curr_state == terminate) ||
(curr_state == dispatch &&
s00_axis_tdata != {DATA_WIDTH{1'b1}} &&
s00_axis_tvalid &&
~priority_sel[7] &&
~priority_sel[6] &&
~priority_sel[5] &&
priority_sel[4]);
assign m05_axis_tvalid = (curr_state == terminate) ||
(curr_state == dispatch &&
s00_axis_tdata != {DATA_WIDTH{1'b1}} &&
s00_axis_tvalid &&
~priority_sel[7] &&
~priority_sel[6] &&
priority_sel[5]);
assign m06_axis_tvalid = (curr_state == terminate) ||
(curr_state == dispatch &&
s00_axis_tdata != {DATA_WIDTH{1'b1}} &&
s00_axis_tvalid &&
~priority_sel[7] &&
priority_sel[6]);
assign m07_axis_tvalid = (curr_state == terminate) ||
(curr_state == dispatch &&
s00_axis_tdata != {DATA_WIDTH{1'b1}} &&
s00_axis_tvalid &&
priority_sel[7]);
assign slaves_ready = m00_axis_tready &
m01_axis_tready &
m02_axis_tready &
m03_axis_tready &
m04_axis_tready &
m05_axis_tready &
m06_axis_tready &
m07_axis_tready;
end
endgenerate
// User logic ends
endmodule
|
module CORDIC_Element_test;
//defination for Variables
reg clk;
reg reset;
reg[(`WIDTH-1):0] test_vector_x[(`ORDER+1):0];
reg[(`WIDTH-1):0] test_vector_y[(`ORDER+1):0];
reg[(`WIDTH-1):0] test_vector_z[(`ORDER+1):0];
//Test Vector Value
wire[(`WIDTH-1):0] x[(`ORDER+1):0];
wire[(`WIDTH-1):0] y[(`ORDER+1):0];
wire[(`WIDTH-1):0] z[(`ORDER+1):0];
//middle signals
reg[(`WIDTH-1):0] comp_x[(`ORDER+1):0];
reg[(`WIDTH-1):0] comp_y[(`ORDER+1):0];
reg[(`WIDTH-1):0] comp_z[(`ORDER+1):0];
//Results right? Comparision results
reg[3:0] loop;
//Connection to the modules
CORDIC_elemet #(.ADDRESS_WIDTH(`WIDTH-1), .VALUE_WIDTH(`WIDTH-1), .e_k(14'h3243), .ORDER(0) )
CE0 ( .CLK(clk), .RESET_n(reset),
.x_k(x[0]), .y_k(y[0]), .z_k(z[0]),
.x_k1(x[1]), .y_k1(y[1]), .z_k1(z[1]) );
CORDIC_elemet #(.ADDRESS_WIDTH(`WIDTH-1), .VALUE_WIDTH(`WIDTH-1), .e_k(14'h1DAC), .ORDER(1) )
CE1 ( .CLK(clk), .RESET_n(reset),
.x_k(x[1]), .y_k(y[1]), .z_k(z[1]),
.x_k1(x[2]), .y_k1(y[2]), .z_k1(z[2]) );
CORDIC_elemet #(.ADDRESS_WIDTH(`WIDTH-1), .VALUE_WIDTH(`WIDTH-1), .e_k(14'h0FAD), .ORDER(2) )
CE2 ( .CLK(clk), .RESET_n(reset),
.x_k(x[2]), .y_k(y[2]), .z_k(z[2]),
.x_k1(x[3]), .y_k1(y[3]), .z_k1(z[3]) );
CORDIC_elemet #(.ADDRESS_WIDTH(`WIDTH-1), .VALUE_WIDTH(`WIDTH-1), .e_k(14'h07F5), .ORDER(3) )
CE3 ( .CLK(clk), .RESET_n(reset),
.x_k(x[3]), .y_k(y[3]), .z_k(z[3]),
.x_k1(x[4]), .y_k1(y[4]), .z_k1(z[4]) );
CORDIC_elemet #(.ADDRESS_WIDTH(`WIDTH-1), .VALUE_WIDTH(`WIDTH-1), .e_k(14'h03FE), .ORDER(4) )
CE4 ( .CLK(clk), .RESET_n(reset),
.x_k(x[4]), .y_k(y[4]), .z_k(z[4]),
.x_k1(x[5]), .y_k1(y[5]), .z_k1(z[5]) );
CORDIC_elemet #(.ADDRESS_WIDTH(`WIDTH-1), .VALUE_WIDTH(`WIDTH-1), .e_k(14'h01FF), .ORDER(5) )
CE5 ( .CLK(clk), .RESET_n(reset),
.x_k(x[5]), .y_k(y[5]), .z_k(z[5]),
.x_k1(x[6]), .y_k1(y[6]), .z_k1(z[6]) );
CORDIC_elemet #(.ADDRESS_WIDTH(`WIDTH-1), .VALUE_WIDTH(`WIDTH-1), .e_k(14'h00FF), .ORDER(6) )
CE6 ( .CLK(clk), .RESET_n(reset),
.x_k(x[6]), .y_k(y[6]), .z_k(z[6]),
.x_k1(x[7]), .y_k1(y[7]), .z_k1(z[7]) );
CORDIC_elemet #(.ADDRESS_WIDTH(`WIDTH-1), .VALUE_WIDTH(`WIDTH-1), .e_k(14'h007F), .ORDER(7) )
CE7 ( .CLK(clk), .RESET_n(reset),
.x_k(x[7]), .y_k(y[7]), .z_k(z[7]),
.x_k1(x[8]), .y_k1(y[8]), .z_k1(z[8]) );
CORDIC_elemet #(.ADDRESS_WIDTH(`WIDTH-1), .VALUE_WIDTH(`WIDTH-1), .e_k(14'h003F), .ORDER(8) )
CE8 ( .CLK(clk), .RESET_n(reset),
.x_k(x[8]), .y_k(y[8]), .z_k(z[8]),
.x_k1(x[9]), .y_k1(y[9]), .z_k1(z[9]) );
CORDIC_elemet #(.ADDRESS_WIDTH(`WIDTH-1), .VALUE_WIDTH(`WIDTH-1), .e_k(14'h001F), .ORDER(9) )
CE9 ( .CLK(clk), .RESET_n(reset),
.x_k(x[9]), .y_k(y[9]), .z_k(z[9]),
.x_k1(x[10]), .y_k1(y[10]), .z_k1(z[10]) );
CORDIC_elemet #(.ADDRESS_WIDTH(`WIDTH-1), .VALUE_WIDTH(`WIDTH-1), .e_k(14'h000F), .ORDER(10) )
CE10 ( .CLK(clk), .RESET_n(reset),
.x_k(x[10]), .y_k(y[10]), .z_k(z[10]),
.x_k1(x[11]), .y_k1(y[11]), .z_k1(z[11]) );
CORDIC_elemet #(.ADDRESS_WIDTH(`WIDTH-1), .VALUE_WIDTH(`WIDTH-1), .e_k(14'h0007), .ORDER(11) )
CE11 ( .CLK(clk), .RESET_n(reset),
.x_k(x[11]), .y_k(y[11]), .z_k(z[11]),
.x_k1(x[12]), .y_k1(y[12]), .z_k1(z[12]) );
CORDIC_elemet #(.ADDRESS_WIDTH(`WIDTH-1), .VALUE_WIDTH(`WIDTH-1), .e_k(14'h0003), .ORDER(12) )
CE12 ( .CLK(clk), .RESET_n(reset),
.x_k(x[12]), .y_k(y[12]), .z_k(z[12]),
.x_k1(x[13]), .y_k1(y[13]), .z_k1(z[13]) );
//Clock generation
initial
begin
clk = 0;
//Reset
forever
begin
#10 clk = !clk;
//Reverse the clock in each 10ns
end
end
//Reset operation
initial
begin
reset = 0;
//Reset enable
#14 reset = 1;
//Counter starts
end
//Load the test vectors
initial
begin
$readmemh("triangle_x_test_vector.txt", test_vector_x);
$readmemh("triangle_y_test_vector.txt", test_vector_y);
$readmemh("triangle_z_test_vector.txt", test_vector_z);
end
//Load the input of 0 order element
//assign x[0] = test_vector_x[0];
//assign y[0] = test_vector_y[0];
//assign z[0] = test_vector_z[0];
assign x[0] = test_vector_x[0];
assign y[0] = test_vector_y[0];
assign z[0] = 0;
//Comparision
always @(posedge clk)
begin
if ( !reset)
//reset statement: counter keeps at 0
begin
for (loop = 0; loop <= (`ORDER+1); loop = loop + 1)
begin
comp_x[loop] <= 1'b0;
comp_y[loop] <= 1'b0;
comp_z[loop] <= 1'b0;
end
end
else
begin
for (loop = 0; loop <= (`ORDER+1); loop = loop + 1)
begin
comp_x[loop] <= (x[loop]>>>1 - test_vector_x[loop]);
comp_y[loop] <= (y[loop]>>>1 - test_vector_y[loop]);
comp_z[loop] <= (z[loop]>>>1 - test_vector_z[loop]);
end
end
end
endmodule
|
module sky130_fd_sc_hs__or4 (
VPWR,
VGND,
X ,
A ,
B ,
C ,
D
);
// Module ports
input VPWR;
input VGND;
output X ;
input A ;
input B ;
input C ;
input D ;
// Local signals
wire or0_out_X ;
wire u_vpwr_vgnd0_out_X;
// Name Output Other arguments
or or0 (or0_out_X , D, C, B, A );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_X, or0_out_X, VPWR, VGND);
buf buf0 (X , u_vpwr_vgnd0_out_X );
endmodule
|
module sky130_fd_sc_ms__xnor3 (
X ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire xnor0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
xnor xnor0 (xnor0_out_X , A, B, C );
sky130_fd_sc_ms__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, xnor0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
|
module sky130_fd_sc_hdll__nand4bb (
Y ,
A_N ,
B_N ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A_N ;
input B_N ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire nand0_out ;
wire or0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
nand nand0 (nand0_out , D, C );
or or0 (or0_out_Y , B_N, A_N, nand0_out );
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, or0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
|
module BRAM
(DOBDO,
ETH_CLK_OBUF,
ADDRBWRADDR,
pwropt);
output [3:0]DOBDO;
input ETH_CLK_OBUF;
input [12:0]ADDRBWRADDR;
input pwropt;
wire [12:0]ADDRBWRADDR;
wire [3:0]DOBDO;
wire ETH_CLK_OBUF;
wire pwropt;
wire NLW_MEMORY_reg_0_CASCADEOUTA_UNCONNECTED;
wire NLW_MEMORY_reg_0_CASCADEOUTB_UNCONNECTED;
wire NLW_MEMORY_reg_0_DBITERR_UNCONNECTED;
wire NLW_MEMORY_reg_0_INJECTDBITERR_UNCONNECTED;
wire NLW_MEMORY_reg_0_INJECTSBITERR_UNCONNECTED;
wire NLW_MEMORY_reg_0_REGCEAREGCE_UNCONNECTED;
wire NLW_MEMORY_reg_0_REGCEB_UNCONNECTED;
wire NLW_MEMORY_reg_0_SBITERR_UNCONNECTED;
wire [31:0]NLW_MEMORY_reg_0_DOADO_UNCONNECTED;
wire [31:4]NLW_MEMORY_reg_0_DOBDO_UNCONNECTED;
wire [3:0]NLW_MEMORY_reg_0_DOPADOP_UNCONNECTED;
wire [3:0]NLW_MEMORY_reg_0_DOPBDOP_UNCONNECTED;
wire [7:0]NLW_MEMORY_reg_0_ECCPARITY_UNCONNECTED;
wire [8:0]NLW_MEMORY_reg_0_RDADDRECC_UNCONNECTED;
(* IS_CLOCK_GATED *)
(* METHODOLOGY_DRC_VIOS = "{SYNTH-6 {cell *THIS*}}" *)
(* POWER_OPTED_CE = "ENBWREN=NEW" *)
(* RTL_RAM_BITS = "60000" *)
(* RTL_RAM_NAME = "MEMORY" *)
(* bram_addr_begin = "0" *)
(* bram_addr_end = "8191" *)
(* bram_slice_begin = "0" *)
(* bram_slice_end = "3" *)
RAMB36E1 #(
.DOA_REG(0),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.IS_ENBWREN_INVERTED(1'b1),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(4),
.READ_WIDTH_B(4),
.RSTREG_PRIORITY_A("RSTREG"),
.RSTREG_PRIORITY_B("RSTREG"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("NO_CHANGE"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(4),
.WRITE_WIDTH_B(4))
MEMORY_reg_0
(.ADDRARDADDR({1'b1,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b1,1'b1}),
.ADDRBWRADDR({1'b1,ADDRBWRADDR,1'b1,1'b1}),
.CASCADEINA(1'b1),
.CASCADEINB(1'b1),
.CASCADEOUTA(NLW_MEMORY_reg_0_CASCADEOUTA_UNCONNECTED),
.CASCADEOUTB(NLW_MEMORY_reg_0_CASCADEOUTB_UNCONNECTED),
.CLKARDCLK(ETH_CLK_OBUF),
.CLKBWRCLK(ETH_CLK_OBUF),
.DBITERR(NLW_MEMORY_reg_0_DBITERR_UNCONNECTED),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b1,1'b1,1'b1,1'b1}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO(NLW_MEMORY_reg_0_DOADO_UNCONNECTED[31:0]),
.DOBDO({NLW_MEMORY_reg_0_DOBDO_UNCONNECTED[31:4],DOBDO}),
.DOPADOP(NLW_MEMORY_reg_0_DOPADOP_UNCONNECTED[3:0]),
.DOPBDOP(NLW_MEMORY_reg_0_DOPBDOP_UNCONNECTED[3:0]),
.ECCPARITY(NLW_MEMORY_reg_0_ECCPARITY_UNCONNECTED[7:0]),
.ENARDEN(1'b1),
.ENBWREN(pwropt),
.INJECTDBITERR(NLW_MEMORY_reg_0_INJECTDBITERR_UNCONNECTED),
.INJECTSBITERR(NLW_MEMORY_reg_0_INJECTSBITERR_UNCONNECTED),
.RDADDRECC(NLW_MEMORY_reg_0_RDADDRECC_UNCONNECTED[8:0]),
.REGCEAREGCE(NLW_MEMORY_reg_0_REGCEAREGCE_UNCONNECTED),
.REGCEB(NLW_MEMORY_reg_0_REGCEB_UNCONNECTED),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(NLW_MEMORY_reg_0_SBITERR_UNCONNECTED),
.WEA({1'b1,1'b1,1'b1,1'b1}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule
|
module BSP
(CLK_IN,
RST,
ETH_CLK,
PHY_RESET_N,
RXDV,
RXER,
RXD,
TXD,
TXEN,
JC,
SDA,
SCL,
KD,
KC,
AUDIO,
AUDIO_EN,
VGA_R,
VGA_G,
VGA_B,
HSYNCH,
VSYNCH,
GPIO_LEDS,
GPIO_SWITCHES,
GPIO_BUTTONS,
LED_R_PWM,
LED_G_PWM,
LED_B_PWM,
SEVEN_SEGMENT_CATHODE,
SEVEN_SEGMENT_ANNODE,
RS232_RX,
RS232_TX);
input CLK_IN;
input RST;
output ETH_CLK;
output PHY_RESET_N;
input RXDV;
input RXER;
input [1:0]RXD;
output [1:0]TXD;
output TXEN;
inout [7:0]JC;
inout SDA;
inout SCL;
input KD;
input KC;
output AUDIO;
output AUDIO_EN;
output [3:0]VGA_R;
output [3:0]VGA_G;
output [3:0]VGA_B;
output HSYNCH;
output VSYNCH;
output [15:0]GPIO_LEDS;
input [15:0]GPIO_SWITCHES;
input [4:0]GPIO_BUTTONS;
output LED_R_PWM;
output LED_G_PWM;
output LED_B_PWM;
output [6:0]SEVEN_SEGMENT_CATHODE;
output [7:0]SEVEN_SEGMENT_ANNODE;
input RS232_RX;
output RS232_TX;
wire AUDIO;
wire AUDIO_EN;
wire CLKFB;
wire CLKIN;
(* IBUF_LOW_PWR *) wire CLK_IN;
wire ETH_CLK;
wire ETH_CLK_OBUF;
wire \GPIO_BUTTONS[0] ;
wire \GPIO_BUTTONS[0]_IBUF ;
wire \GPIO_BUTTONS[1] ;
wire \GPIO_BUTTONS[1]_IBUF ;
wire \GPIO_BUTTONS[2] ;
wire \GPIO_BUTTONS[2]_IBUF ;
wire \GPIO_BUTTONS[3] ;
wire \GPIO_BUTTONS[3]_IBUF ;
wire \GPIO_BUTTONS[4] ;
wire \GPIO_BUTTONS[4]_IBUF ;
wire [15:0]GPIO_LEDS;
wire \GPIO_SWITCHES[0] ;
wire \GPIO_SWITCHES[0]_IBUF ;
wire \GPIO_SWITCHES[10] ;
wire \GPIO_SWITCHES[10]_IBUF ;
wire \GPIO_SWITCHES[11] ;
wire \GPIO_SWITCHES[11]_IBUF ;
wire \GPIO_SWITCHES[12] ;
wire \GPIO_SWITCHES[12]_IBUF ;
wire \GPIO_SWITCHES[13] ;
wire \GPIO_SWITCHES[13]_IBUF ;
wire \GPIO_SWITCHES[14] ;
wire \GPIO_SWITCHES[14]_IBUF ;
wire \GPIO_SWITCHES[15] ;
wire \GPIO_SWITCHES[15]_IBUF ;
wire \GPIO_SWITCHES[1] ;
wire \GPIO_SWITCHES[1]_IBUF ;
wire \GPIO_SWITCHES[2] ;
wire \GPIO_SWITCHES[2]_IBUF ;
wire \GPIO_SWITCHES[3] ;
wire \GPIO_SWITCHES[3]_IBUF ;
wire \GPIO_SWITCHES[4] ;
wire \GPIO_SWITCHES[4]_IBUF ;
wire \GPIO_SWITCHES[5] ;
wire \GPIO_SWITCHES[5]_IBUF ;
wire \GPIO_SWITCHES[6] ;
wire \GPIO_SWITCHES[6]_IBUF ;
wire \GPIO_SWITCHES[7] ;
wire \GPIO_SWITCHES[7]_IBUF ;
wire \GPIO_SWITCHES[8] ;
wire \GPIO_SWITCHES[8]_IBUF ;
wire \GPIO_SWITCHES[9] ;
wire \GPIO_SWITCHES[9]_IBUF ;
wire HSYNCH;
wire HSYNCH_OBUF;
wire IN1_ACK;
wire IN1_STB;
wire INTERNAL_RST_reg_n_0;
wire [7:0]JC;
wire [1:1]JC_IBUF;
wire KC;
wire KC_IBUF;
wire KD;
wire KD_IBUF;
wire LED_B_PWM;
wire LED_B_PWM_OBUF;
wire LED_G_PWM;
wire LED_G_PWM_OBUF;
wire LED_R_PWM;
wire LED_R_PWM_OBUF;
wire NOT_LOCKED;
wire NOT_LOCKED_i_1_n_0;
wire PHY_RESET_N;
wire PHY_RESET_N_OBUF;
wire RS232_RX;
wire RS232_RX_IBUF;
wire RS232_TX;
wire RS232_TX_OBUF;
wire RST;
wire RST_IBUF;
wire RXDV;
wire RXDV_IBUF;
wire \RXD[0] ;
wire \RXD[0]_IBUF ;
wire \RXD[1] ;
wire \RXD[1]_IBUF ;
wire RXER;
wire RXER_IBUF;
(* DRIVE = "12" *) (* IBUF_LOW_PWR *) (* SLEW = "SLOW" *) wire SCL;
wire SCL_IBUF;
wire SCL_TRI;
wire SDA;
wire SDA_IBUF;
wire SDA_TRI;
wire [7:0]SEVEN_SEGMENT_ANNODE;
wire [6:0]SEVEN_SEGMENT_CATHODE;
wire [1:0]TXD;
wire [1:0]TXD_OBUF;
wire TXEN;
wire TXEN_OBUF;
wire USER_DESIGN_INST_1_n_1;
wire USER_DESIGN_INST_1_n_2;
wire USER_DESIGN_INST_1_n_3;
wire USER_DESIGN_INST_1_n_4;
wire USER_DESIGN_INST_1_n_5;
wire USER_DESIGN_INST_1_n_6;
wire USER_DESIGN_INST_1_n_7;
wire USER_DESIGN_INST_1_n_8;
wire [3:0]VGA_B;
wire [0:0]VGA_B_OBUF;
wire [3:0]VGA_G;
wire [3:0]VGA_R;
wire VSYNCH;
wire VSYNCH_OBUF;
wire clk0;
wire clkdv;
wire locked_internal;
wire NLW_dcm_sp_inst_CLKFBOUTB_UNCONNECTED;
wire NLW_dcm_sp_inst_CLKFBSTOPPED_UNCONNECTED;
wire NLW_dcm_sp_inst_CLKINSTOPPED_UNCONNECTED;
wire NLW_dcm_sp_inst_CLKOUT0_UNCONNECTED;
wire NLW_dcm_sp_inst_CLKOUT0B_UNCONNECTED;
wire NLW_dcm_sp_inst_CLKOUT1_UNCONNECTED;
wire NLW_dcm_sp_inst_CLKOUT1B_UNCONNECTED;
wire NLW_dcm_sp_inst_CLKOUT2_UNCONNECTED;
wire NLW_dcm_sp_inst_CLKOUT2B_UNCONNECTED;
wire NLW_dcm_sp_inst_CLKOUT3_UNCONNECTED;
wire NLW_dcm_sp_inst_CLKOUT3B_UNCONNECTED;
wire NLW_dcm_sp_inst_CLKOUT5_UNCONNECTED;
wire NLW_dcm_sp_inst_CLKOUT6_UNCONNECTED;
wire NLW_dcm_sp_inst_DRDY_UNCONNECTED;
wire NLW_dcm_sp_inst_PSDONE_UNCONNECTED;
wire [15:0]NLW_dcm_sp_inst_DO_UNCONNECTED;
wire NLW_ethernet_inst_1_RXDV_IBUF_UNCONNECTED;
wire NLW_ethernet_inst_1_RXER_IBUF_UNCONNECTED;
wire [1:0]NLW_ethernet_inst_1_D_UNCONNECTED;
PULLUP pullup_KC
(.O(KC));
PULLUP pullup_KD
(.O(KD));
initial begin
$sdf_annotate("cpu_impl_netlist.sdf",,,,"tool_control");
end
assign \GPIO_BUTTONS[0] = GPIO_BUTTONS[0];
assign \GPIO_BUTTONS[1] = GPIO_BUTTONS[1];
assign \GPIO_BUTTONS[2] = GPIO_BUTTONS[2];
assign \GPIO_BUTTONS[3] = GPIO_BUTTONS[3];
assign \GPIO_BUTTONS[4] = GPIO_BUTTONS[4];
assign \GPIO_SWITCHES[0] = GPIO_SWITCHES[0];
assign \GPIO_SWITCHES[10] = GPIO_SWITCHES[10];
assign \GPIO_SWITCHES[11] = GPIO_SWITCHES[11];
assign \GPIO_SWITCHES[12] = GPIO_SWITCHES[12];
assign \GPIO_SWITCHES[13] = GPIO_SWITCHES[13];
assign \GPIO_SWITCHES[14] = GPIO_SWITCHES[14];
assign \GPIO_SWITCHES[15] = GPIO_SWITCHES[15];
assign \GPIO_SWITCHES[1] = GPIO_SWITCHES[1];
assign \GPIO_SWITCHES[2] = GPIO_SWITCHES[2];
assign \GPIO_SWITCHES[3] = GPIO_SWITCHES[3];
assign \GPIO_SWITCHES[4] = GPIO_SWITCHES[4];
assign \GPIO_SWITCHES[5] = GPIO_SWITCHES[5];
assign \GPIO_SWITCHES[6] = GPIO_SWITCHES[6];
assign \GPIO_SWITCHES[7] = GPIO_SWITCHES[7];
assign \GPIO_SWITCHES[8] = GPIO_SWITCHES[8];
assign \GPIO_SWITCHES[9] = GPIO_SWITCHES[9];
assign \RXD[0] = RXD[0];
assign \RXD[1] = RXD[1];
OBUF AUDIO_EN_OBUF_inst
(.I(1'b1),
.O(AUDIO_EN));
OBUF AUDIO_OBUF_inst
(.I(1'b0),
.O(AUDIO));
(* box_type = "PRIMITIVE" *)
BUFG BUFG_INST1
(.I(clkdv),
.O(ETH_CLK_OBUF));
(* box_type = "PRIMITIVE" *)
BUFG BUFG_INST2
(.I(clk0),
.O(CLKFB));
CHARSVGA CHARSVGA_INST_1
(.ETH_CLK_OBUF(ETH_CLK_OBUF),
.HSYNCH(HSYNCH_OBUF),
.INTERNAL_RST_reg(INTERNAL_RST_reg_n_0),
.VGA_B_OBUF(VGA_B_OBUF),
.VSYNCH(VSYNCH_OBUF));
OBUF ETH_CLK_OBUF_inst
(.I(ETH_CLK_OBUF),
.O(ETH_CLK));
(* OPT_INSERTED *)
IBUF \GPIO_BUTTONS[0]_IBUF_inst
(.I(\GPIO_BUTTONS[0] ),
.O(\GPIO_BUTTONS[0]_IBUF ));
(* OPT_INSERTED *)
IBUF \GPIO_BUTTONS[1]_IBUF_inst
(.I(\GPIO_BUTTONS[1] ),
.O(\GPIO_BUTTONS[1]_IBUF ));
(* OPT_INSERTED *)
IBUF \GPIO_BUTTONS[2]_IBUF_inst
(.I(\GPIO_BUTTONS[2] ),
.O(\GPIO_BUTTONS[2]_IBUF ));
(* OPT_INSERTED *)
IBUF \GPIO_BUTTONS[3]_IBUF_inst
(.I(\GPIO_BUTTONS[3] ),
.O(\GPIO_BUTTONS[3]_IBUF ));
(* OPT_INSERTED *)
IBUF \GPIO_BUTTONS[4]_IBUF_inst
(.I(\GPIO_BUTTONS[4] ),
.O(\GPIO_BUTTONS[4]_IBUF ));
OBUF \GPIO_LEDS_OBUF[0]_inst
(.I(1'b0),
.O(GPIO_LEDS[0]));
OBUF \GPIO_LEDS_OBUF[10]_inst
(.I(1'b0),
.O(GPIO_LEDS[10]));
OBUF \GPIO_LEDS_OBUF[11]_inst
(.I(1'b0),
.O(GPIO_LEDS[11]));
OBUF \GPIO_LEDS_OBUF[12]_inst
(.I(1'b0),
.O(GPIO_LEDS[12]));
OBUF \GPIO_LEDS_OBUF[13]_inst
(.I(1'b0),
.O(GPIO_LEDS[13]));
OBUF \GPIO_LEDS_OBUF[14]_inst
(.I(1'b0),
.O(GPIO_LEDS[14]));
OBUF \GPIO_LEDS_OBUF[15]_inst
(.I(1'b0),
.O(GPIO_LEDS[15]));
OBUF \GPIO_LEDS_OBUF[1]_inst
(.I(1'b0),
.O(GPIO_LEDS[1]));
OBUF \GPIO_LEDS_OBUF[2]_inst
(.I(1'b0),
.O(GPIO_LEDS[2]));
OBUF \GPIO_LEDS_OBUF[3]_inst
(.I(1'b0),
.O(GPIO_LEDS[3]));
OBUF \GPIO_LEDS_OBUF[4]_inst
(.I(1'b0),
.O(GPIO_LEDS[4]));
OBUF \GPIO_LEDS_OBUF[5]_inst
(.I(1'b0),
.O(GPIO_LEDS[5]));
OBUF \GPIO_LEDS_OBUF[6]_inst
(.I(1'b0),
.O(GPIO_LEDS[6]));
OBUF \GPIO_LEDS_OBUF[7]_inst
(.I(1'b0),
.O(GPIO_LEDS[7]));
OBUF \GPIO_LEDS_OBUF[8]_inst
(.I(1'b0),
.O(GPIO_LEDS[8]));
OBUF \GPIO_LEDS_OBUF[9]_inst
(.I(1'b0),
.O(GPIO_LEDS[9]));
(* OPT_INSERTED *)
IBUF \GPIO_SWITCHES[0]_IBUF_inst
(.I(\GPIO_SWITCHES[0] ),
.O(\GPIO_SWITCHES[0]_IBUF ));
(* OPT_INSERTED *)
IBUF \GPIO_SWITCHES[10]_IBUF_inst
(.I(\GPIO_SWITCHES[10] ),
.O(\GPIO_SWITCHES[10]_IBUF ));
(* OPT_INSERTED *)
IBUF \GPIO_SWITCHES[11]_IBUF_inst
(.I(\GPIO_SWITCHES[11] ),
.O(\GPIO_SWITCHES[11]_IBUF ));
(* OPT_INSERTED *)
IBUF \GPIO_SWITCHES[12]_IBUF_inst
(.I(\GPIO_SWITCHES[12] ),
.O(\GPIO_SWITCHES[12]_IBUF ));
(* OPT_INSERTED *)
IBUF \GPIO_SWITCHES[13]_IBUF_inst
(.I(\GPIO_SWITCHES[13] ),
.O(\GPIO_SWITCHES[13]_IBUF ));
(* OPT_INSERTED *)
IBUF \GPIO_SWITCHES[14]_IBUF_inst
(.I(\GPIO_SWITCHES[14] ),
.O(\GPIO_SWITCHES[14]_IBUF ));
(* OPT_INSERTED *)
IBUF \GPIO_SWITCHES[15]_IBUF_inst
(.I(\GPIO_SWITCHES[15] ),
.O(\GPIO_SWITCHES[15]_IBUF ));
(* OPT_INSERTED *)
IBUF \GPIO_SWITCHES[1]_IBUF_inst
(.I(\GPIO_SWITCHES[1] ),
.O(\GPIO_SWITCHES[1]_IBUF ));
(* OPT_INSERTED *)
IBUF \GPIO_SWITCHES[2]_IBUF_inst
(.I(\GPIO_SWITCHES[2] ),
.O(\GPIO_SWITCHES[2]_IBUF ));
(* OPT_INSERTED *)
IBUF \GPIO_SWITCHES[3]_IBUF_inst
(.I(\GPIO_SWITCHES[3] ),
.O(\GPIO_SWITCHES[3]_IBUF ));
(* OPT_INSERTED *)
IBUF \GPIO_SWITCHES[4]_IBUF_inst
(.I(\GPIO_SWITCHES[4] ),
.O(\GPIO_SWITCHES[4]_IBUF ));
(* OPT_INSERTED *)
IBUF \GPIO_SWITCHES[5]_IBUF_inst
(.I(\GPIO_SWITCHES[5] ),
.O(\GPIO_SWITCHES[5]_IBUF ));
(* OPT_INSERTED *)
IBUF \GPIO_SWITCHES[6]_IBUF_inst
(.I(\GPIO_SWITCHES[6] ),
.O(\GPIO_SWITCHES[6]_IBUF ));
(* OPT_INSERTED *)
IBUF \GPIO_SWITCHES[7]_IBUF_inst
(.I(\GPIO_SWITCHES[7] ),
.O(\GPIO_SWITCHES[7]_IBUF ));
(* OPT_INSERTED *)
IBUF \GPIO_SWITCHES[8]_IBUF_inst
(.I(\GPIO_SWITCHES[8] ),
.O(\GPIO_SWITCHES[8]_IBUF ));
(* OPT_INSERTED *)
IBUF \GPIO_SWITCHES[9]_IBUF_inst
(.I(\GPIO_SWITCHES[9] ),
.O(\GPIO_SWITCHES[9]_IBUF ));
OBUF HSYNCH_OBUF_inst
(.I(HSYNCH_OBUF),
.O(HSYNCH));
I2C I2C_INST_1
(.ETH_CLK_OBUF(ETH_CLK_OBUF),
.INTERNAL_RST_reg(INTERNAL_RST_reg_n_0),
.SCL_IBUF(SCL_IBUF),
.SCL_TRI(SCL_TRI),
.SDA_IBUF(SDA_IBUF),
.SDA_TRI(SDA_TRI));
FDRE INTERNAL_RST_reg
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(NOT_LOCKED),
.Q(INTERNAL_RST_reg_n_0),
.R(1'b0));
OBUF \JC_OBUF[0]_inst
(.I(1'b1),
.O(JC[0]));
OBUF \JC_OBUF[1]_inst
(.I(JC_IBUF),
.O(JC[1]));
(* OPT_INSERTED *)
IBUF KC_IBUF_inst
(.I(KC),
.O(KC_IBUF));
(* OPT_INSERTED *)
IBUF KD_IBUF_inst
(.I(KD),
.O(KD_IBUF));
OBUF LED_B_PWM_OBUF_inst
(.I(LED_B_PWM_OBUF),
.O(LED_B_PWM));
OBUF LED_G_PWM_OBUF_inst
(.I(LED_G_PWM_OBUF),
.O(LED_G_PWM));
OBUF LED_R_PWM_OBUF_inst
(.I(LED_R_PWM_OBUF),
.O(LED_R_PWM));
LUT1 #(
.INIT(2'h1))
NOT_LOCKED_i_1
(.I0(locked_internal),
.O(NOT_LOCKED_i_1_n_0));
FDRE NOT_LOCKED_reg
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(NOT_LOCKED_i_1_n_0),
.Q(NOT_LOCKED),
.R(1'b0));
OBUF PHY_RESET_N_OBUF_inst
(.I(PHY_RESET_N_OBUF),
.O(PHY_RESET_N));
LUT1 #(
.INIT(2'h1))
PHY_RESET_N_OBUF_inst_i_1
(.I0(INTERNAL_RST_reg_n_0),
.O(PHY_RESET_N_OBUF));
PWM PWM_INST_1
(.ETH_CLK_OBUF(ETH_CLK_OBUF),
.LED_R_PWM_OBUF(LED_R_PWM_OBUF));
PWM_0 PWM_INST_2
(.ETH_CLK_OBUF(ETH_CLK_OBUF),
.LED_G_PWM_OBUF(LED_G_PWM_OBUF));
PWM_1 PWM_INST_3
(.ETH_CLK_OBUF(ETH_CLK_OBUF),
.LED_B_PWM_OBUF(LED_B_PWM_OBUF));
(* OPT_INSERTED *)
IBUF RS232_RX_IBUF_inst
(.I(RS232_RX),
.O(RS232_RX_IBUF));
OBUF RS232_TX_OBUF_inst
(.I(RS232_TX_OBUF),
.O(RS232_TX));
IBUF RST_IBUF_inst
(.I(RST),
.O(RST_IBUF));
(* OPT_INSERTED *)
IBUF RXDV_IBUF_inst
(.I(RXDV),
.O(RXDV_IBUF));
(* OPT_INSERTED *)
IBUF \RXD[0]_IBUF_inst
(.I(\RXD[0] ),
.O(\RXD[0]_IBUF ));
(* OPT_INSERTED *)
IBUF \RXD[1]_IBUF_inst
(.I(\RXD[1] ),
.O(\RXD[1]_IBUF ));
(* OPT_INSERTED *)
IBUF RXER_IBUF_inst
(.I(RXER),
.O(RXER_IBUF));
IOBUF_HD3 SCL_IOBUF_inst
(.I(1'b0),
.IO(SCL),
.O(SCL_IBUF),
.T(SCL_TRI));
IOBUF_UNIQ_BASE_ SDA_IOBUF_inst
(.I(1'b0),
.IO(SDA),
.O(SDA_IBUF),
.T(SDA_TRI));
serial_output SERIAL_OUTPUT_INST_1
(.ETH_CLK_OBUF(ETH_CLK_OBUF),
.IN1_ACK(IN1_ACK),
.IN1_STB(IN1_STB),
.INTERNAL_RST_reg(INTERNAL_RST_reg_n_0),
.Q({USER_DESIGN_INST_1_n_1,USER_DESIGN_INST_1_n_2,USER_DESIGN_INST_1_n_3,USER_DESIGN_INST_1_n_4,USER_DESIGN_INST_1_n_5,USER_DESIGN_INST_1_n_6,USER_DESIGN_INST_1_n_7,USER_DESIGN_INST_1_n_8}),
.RS232_TX_OBUF(RS232_TX_OBUF));
OBUF \SEVEN_SEGMENT_ANNODE_OBUF[0]_inst
(.I(1'b1),
.O(SEVEN_SEGMENT_ANNODE[0]));
OBUF \SEVEN_SEGMENT_ANNODE_OBUF[1]_inst
(.I(1'b1),
.O(SEVEN_SEGMENT_ANNODE[1]));
OBUF \SEVEN_SEGMENT_ANNODE_OBUF[2]_inst
(.I(1'b1),
.O(SEVEN_SEGMENT_ANNODE[2]));
OBUF \SEVEN_SEGMENT_ANNODE_OBUF[3]_inst
(.I(1'b1),
.O(SEVEN_SEGMENT_ANNODE[3]));
OBUF \SEVEN_SEGMENT_ANNODE_OBUF[4]_inst
(.I(1'b1),
.O(SEVEN_SEGMENT_ANNODE[4]));
OBUF \SEVEN_SEGMENT_ANNODE_OBUF[5]_inst
(.I(1'b1),
.O(SEVEN_SEGMENT_ANNODE[5]));
OBUF \SEVEN_SEGMENT_ANNODE_OBUF[6]_inst
(.I(1'b1),
.O(SEVEN_SEGMENT_ANNODE[6]));
OBUF \SEVEN_SEGMENT_ANNODE_OBUF[7]_inst
(.I(1'b1),
.O(SEVEN_SEGMENT_ANNODE[7]));
OBUF \SEVEN_SEGMENT_CATHODE_OBUF[0]_inst
(.I(1'b1),
.O(SEVEN_SEGMENT_CATHODE[0]));
OBUF \SEVEN_SEGMENT_CATHODE_OBUF[1]_inst
(.I(1'b1),
.O(SEVEN_SEGMENT_CATHODE[1]));
OBUF \SEVEN_SEGMENT_CATHODE_OBUF[2]_inst
(.I(1'b1),
.O(SEVEN_SEGMENT_CATHODE[2]));
OBUF \SEVEN_SEGMENT_CATHODE_OBUF[3]_inst
(.I(1'b1),
.O(SEVEN_SEGMENT_CATHODE[3]));
OBUF \SEVEN_SEGMENT_CATHODE_OBUF[4]_inst
(.I(1'b1),
.O(SEVEN_SEGMENT_CATHODE[4]));
OBUF \SEVEN_SEGMENT_CATHODE_OBUF[5]_inst
(.I(1'b1),
.O(SEVEN_SEGMENT_CATHODE[5]));
OBUF \SEVEN_SEGMENT_CATHODE_OBUF[6]_inst
(.I(1'b1),
.O(SEVEN_SEGMENT_CATHODE[6]));
OBUF \TXD_OBUF[0]_inst
(.I(TXD_OBUF[0]),
.O(TXD[0]));
OBUF \TXD_OBUF[1]_inst
(.I(TXD_OBUF[1]),
.O(TXD[1]));
OBUF TXEN_OBUF_inst
(.I(TXEN_OBUF),
.O(TXEN));
user_design USER_DESIGN_INST_1
(.ETH_CLK_OBUF(ETH_CLK_OBUF),
.IN1_ACK(IN1_ACK),
.IN1_STB(IN1_STB),
.INTERNAL_RST_reg(INTERNAL_RST_reg_n_0),
.output_rs232_tx({USER_DESIGN_INST_1_n_1,USER_DESIGN_INST_1_n_2,USER_DESIGN_INST_1_n_3,USER_DESIGN_INST_1_n_4,USER_DESIGN_INST_1_n_5,USER_DESIGN_INST_1_n_6,USER_DESIGN_INST_1_n_7,USER_DESIGN_INST_1_n_8}));
OBUF \VGA_B_OBUF[0]_inst
(.I(VGA_B_OBUF),
.O(VGA_B[0]));
OBUF \VGA_B_OBUF[1]_inst
(.I(VGA_B_OBUF),
.O(VGA_B[1]));
OBUF \VGA_B_OBUF[2]_inst
(.I(VGA_B_OBUF),
.O(VGA_B[2]));
OBUF \VGA_B_OBUF[3]_inst
(.I(VGA_B_OBUF),
.O(VGA_B[3]));
OBUF \VGA_G_OBUF[0]_inst
(.I(VGA_B_OBUF),
.O(VGA_G[0]));
OBUF \VGA_G_OBUF[1]_inst
(.I(VGA_B_OBUF),
.O(VGA_G[1]));
OBUF \VGA_G_OBUF[2]_inst
(.I(VGA_B_OBUF),
.O(VGA_G[2]));
OBUF \VGA_G_OBUF[3]_inst
(.I(VGA_B_OBUF),
.O(VGA_G[3]));
OBUF \VGA_R_OBUF[0]_inst
(.I(VGA_B_OBUF),
.O(VGA_R[0]));
OBUF \VGA_R_OBUF[1]_inst
(.I(VGA_B_OBUF),
.O(VGA_R[1]));
OBUF \VGA_R_OBUF[2]_inst
(.I(VGA_B_OBUF),
.O(VGA_R[2]));
OBUF \VGA_R_OBUF[3]_inst
(.I(VGA_B_OBUF),
.O(VGA_R[3]));
OBUF VSYNCH_OBUF_inst
(.I(VSYNCH_OBUF),
.O(VSYNCH));
(* CAPACITANCE = "DONT_CARE" *)
(* IBUF_DELAY_VALUE = "0" *)
(* XILINX_LEGACY_PRIM = "IBUFG" *)
(* box_type = "PRIMITIVE" *)
IBUF #(
.IOSTANDARD("DEFAULT"))
clkin1_buf
(.I(CLK_IN),
.O(CLKIN));
(* XILINX_LEGACY_PRIM = "DCM_SP" *)
(* XILINX_TRANSFORM_PINMAP = "STATUS[7]:DO[7] STATUS[6]:DO[6] STATUS[5]:DO[5] STATUS[4]:DO[4] STATUS[3]:DO[3] STATUS[2]:DO[2] STATUS[1]:DO[1] STATUS[0]:DO[0] CLKIN:CLKIN1 CLKFX:CLKOUT0 CLKFX180:CLKOUT0B CLK2X:CLKOUT1 CLK2X180:CLKOUT1B CLK90:CLKOUT2 CLK270:CLKOUT2B CLKDV:CLKOUT4 CLK0:CLKFBOUT CLK180:CLKFBOUTB CLKFB:CLKFBIN" *)
(* box_type = "PRIMITIVE" *)
MMCME2_ADV #(
.BANDWIDTH("OPTIMIZED"),
.CLKFBOUT_MULT_F(8.000000),
.CLKFBOUT_PHASE(0.000000),
.CLKFBOUT_USE_FINE_PS("FALSE"),
.CLKIN1_PERIOD(10.000000),
.CLKIN2_PERIOD(0.000000),
.CLKOUT0_DIVIDE_F(2.000000),
.CLKOUT0_DUTY_CYCLE(0.500000),
.CLKOUT0_PHASE(0.000000),
.CLKOUT0_USE_FINE_PS("FALSE"),
.CLKOUT1_DIVIDE(4),
.CLKOUT1_DUTY_CYCLE(0.500000),
.CLKOUT1_PHASE(0.000000),
.CLKOUT1_USE_FINE_PS("FALSE"),
.CLKOUT2_DIVIDE(8),
.CLKOUT2_DUTY_CYCLE(0.500000),
.CLKOUT2_PHASE(90.000000),
.CLKOUT2_USE_FINE_PS("FALSE"),
.CLKOUT3_DIVIDE(8),
.CLKOUT3_DUTY_CYCLE(0.500000),
.CLKOUT3_PHASE(0.000000),
.CLKOUT3_USE_FINE_PS("FALSE"),
.CLKOUT4_CASCADE("FALSE"),
.CLKOUT4_DIVIDE(16),
.CLKOUT4_DUTY_CYCLE(0.500000),
.CLKOUT4_PHASE(0.000000),
.CLKOUT4_USE_FINE_PS("FALSE"),
.CLKOUT5_DIVIDE(1),
.CLKOUT5_DUTY_CYCLE(0.500000),
.CLKOUT5_PHASE(0.000000),
.CLKOUT5_USE_FINE_PS("FALSE"),
.CLKOUT6_DIVIDE(1),
.CLKOUT6_DUTY_CYCLE(0.500000),
.CLKOUT6_PHASE(0.000000),
.CLKOUT6_USE_FINE_PS("FALSE"),
.COMPENSATION("ZHOLD"),
.DIVCLK_DIVIDE(1),
.IS_PSINCDEC_INVERTED(1'b1),
.IS_RST_INVERTED(1'b1),
.REF_JITTER1(0.010000),
.REF_JITTER2(0.010000),
.STARTUP_WAIT("FALSE"))
dcm_sp_inst
(.CLKFBIN(CLKFB),
.CLKFBOUT(clk0),
.CLKFBOUTB(NLW_dcm_sp_inst_CLKFBOUTB_UNCONNECTED),
.CLKFBSTOPPED(NLW_dcm_sp_inst_CLKFBSTOPPED_UNCONNECTED),
.CLKIN1(CLKIN),
.CLKIN2(1'b0),
.CLKINSEL(1'b1),
.CLKINSTOPPED(NLW_dcm_sp_inst_CLKINSTOPPED_UNCONNECTED),
.CLKOUT0(NLW_dcm_sp_inst_CLKOUT0_UNCONNECTED),
.CLKOUT0B(NLW_dcm_sp_inst_CLKOUT0B_UNCONNECTED),
.CLKOUT1(NLW_dcm_sp_inst_CLKOUT1_UNCONNECTED),
.CLKOUT1B(NLW_dcm_sp_inst_CLKOUT1B_UNCONNECTED),
.CLKOUT2(NLW_dcm_sp_inst_CLKOUT2_UNCONNECTED),
.CLKOUT2B(NLW_dcm_sp_inst_CLKOUT2B_UNCONNECTED),
.CLKOUT3(NLW_dcm_sp_inst_CLKOUT3_UNCONNECTED),
.CLKOUT3B(NLW_dcm_sp_inst_CLKOUT3B_UNCONNECTED),
.CLKOUT4(clkdv),
.CLKOUT5(NLW_dcm_sp_inst_CLKOUT5_UNCONNECTED),
.CLKOUT6(NLW_dcm_sp_inst_CLKOUT6_UNCONNECTED),
.DADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DCLK(1'b0),
.DEN(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DO(NLW_dcm_sp_inst_DO_UNCONNECTED[15:0]),
.DRDY(NLW_dcm_sp_inst_DRDY_UNCONNECTED),
.DWE(1'b0),
.LOCKED(locked_internal),
.PSCLK(1'b0),
.PSDONE(NLW_dcm_sp_inst_PSDONE_UNCONNECTED),
.PSEN(1'b0),
.PSINCDEC(1'b0),
.PWRDWN(1'b0),
.RST(RST_IBUF));
rmii_ethernet ethernet_inst_1
(.D(NLW_ethernet_inst_1_D_UNCONNECTED[1:0]),
.ETH_CLK_OBUF(ETH_CLK_OBUF),
.INTERNAL_RST_reg(INTERNAL_RST_reg_n_0),
.RXDV_IBUF(NLW_ethernet_inst_1_RXDV_IBUF_UNCONNECTED),
.RXER_IBUF(NLW_ethernet_inst_1_RXER_IBUF_UNCONNECTED),
.TXD_OBUF(TXD_OBUF),
.TXEN_OBUF(TXEN_OBUF));
pwm_audio pwm_audio_inst_1
(.ETH_CLK_OBUF(ETH_CLK_OBUF),
.INTERNAL_RST_reg(INTERNAL_RST_reg_n_0),
.JC_IBUF(JC_IBUF));
endmodule
|
module CHARSVGA
(HSYNCH,
VSYNCH,
VGA_B_OBUF,
ETH_CLK_OBUF,
INTERNAL_RST_reg);
output HSYNCH;
output VSYNCH;
output [0:0]VGA_B_OBUF;
input ETH_CLK_OBUF;
input INTERNAL_RST_reg;
wire [12:1]AOUT;
wire BLANK;
wire BLANK_DEL;
wire BLANK_DEL_DEL;
wire [3:0]DOUT;
wire ETH_CLK_OBUF;
wire HSYNCH;
wire HSYNCH_DEL;
wire INTERNAL_RST_reg;
wire [2:0]PIXCOL_DEL;
wire \PIXCOL_DEL_DEL_reg_n_0_[0] ;
wire \PIXCOL_DEL_DEL_reg_n_0_[1] ;
wire \PIXCOL_DEL_DEL_reg_n_0_[2] ;
wire [7:0]PIXELS_reg__0;
wire TIMEING1_n_0;
wire TIMEING1_n_1;
wire TIMEING1_n_15;
wire TIMEING1_n_16;
wire TIMEING1_n_17;
wire TIMEING1_n_18;
wire TIMEING1_n_19;
wire TIMEING1_n_2;
wire TIMEING1_n_20;
wire [0:0]VGA_B_OBUF;
wire \VGA_R_OBUF[3]_inst_i_2_n_0 ;
wire \VGA_R_OBUF[3]_inst_i_3_n_0 ;
wire VSYNCH;
wire VSYNCH_DEL;
wire [2:0]sel;
wire NLW_PIXELS_reg_REGCEAREGCE_UNCONNECTED;
wire NLW_PIXELS_reg_REGCEB_UNCONNECTED;
wire [15:8]NLW_PIXELS_reg_DOADO_UNCONNECTED;
wire [15:0]NLW_PIXELS_reg_DOBDO_UNCONNECTED;
wire [1:0]NLW_PIXELS_reg_DOPADOP_UNCONNECTED;
wire [1:0]NLW_PIXELS_reg_DOPBDOP_UNCONNECTED;
FDRE BLANK_DEL_DEL_reg
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(BLANK_DEL),
.Q(BLANK_DEL_DEL),
.R(1'b0));
FDRE BLANK_DEL_reg
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(BLANK),
.Q(BLANK_DEL),
.R(1'b0));
BRAM BRAM_INST_1
(.ADDRBWRADDR({AOUT,TIMEING1_n_15}),
.DOBDO(DOUT),
.ETH_CLK_OBUF(ETH_CLK_OBUF),
.pwropt(BLANK));
FDRE HSYNCH_DEL_reg
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(TIMEING1_n_19),
.Q(HSYNCH_DEL),
.R(1'b0));
FDRE HSYNCH_reg
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(HSYNCH_DEL),
.Q(HSYNCH),
.R(1'b0));
FDRE \PIXCOL_DEL_DEL_reg[0]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(PIXCOL_DEL[0]),
.Q(\PIXCOL_DEL_DEL_reg_n_0_[0] ),
.R(1'b0));
FDRE \PIXCOL_DEL_DEL_reg[1]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(PIXCOL_DEL[1]),
.Q(\PIXCOL_DEL_DEL_reg_n_0_[1] ),
.R(1'b0));
FDRE \PIXCOL_DEL_DEL_reg[2]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(PIXCOL_DEL[2]),
.Q(\PIXCOL_DEL_DEL_reg_n_0_[2] ),
.R(1'b0));
FDRE \PIXCOL_DEL_reg[0]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(TIMEING1_n_0),
.Q(PIXCOL_DEL[0]),
.R(1'b0));
FDRE \PIXCOL_DEL_reg[1]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(TIMEING1_n_1),
.Q(PIXCOL_DEL[1]),
.R(1'b0));
FDRE \PIXCOL_DEL_reg[2]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(TIMEING1_n_2),
.Q(PIXCOL_DEL[2]),
.R(1'b0));
(* IS_CLOCK_GATED *)
(* METHODOLOGY_DRC_VIOS = "{SYNTH-6 {cell *THIS*}}" *)
(* POWER_OPTED_CE = "ENARDEN=NEW" *)
(* RTL_RAM_BITS = "16384" *)
(* RTL_RAM_NAME = "PIXELS" *)
(* bram_addr_begin = "0" *)
(* bram_addr_end = "2047" *)
(* bram_slice_begin = "0" *)
(* bram_slice_end = "17" *)
RAMB18E1 #(
.DOA_REG(0),
.DOB_REG(0),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000143E143E1400000000000000141400000800080808080000000000000000),
.INIT_09(256'h0000000000000808006C12320C12120C00E2A4E8102E4A8E00081E281C0A3C08),
.INIT_0A(256'h00101010FE1010100000000022143E0800081020202010080008040202020408),
.INIT_0B(256'h00000204081020400000080000000000000000003E0000000008080000000000),
.INIT_0C(256'h00001C222010221C00003E040810221C00003E0808080C0800001C262A2A321C),
.INIT_0D(256'h000008081020223E00001C221E02221C00001C22203E023E00003C103E121418),
.INIT_0E(256'h0008080000000800000008000000080000001C22203C221C00001C22221C221C),
.INIT_0F(256'h000008000818221C000204081008040200003E00003E00000010080402040810),
.INIT_10(256'h00001C220202221C00001E22221E221E00002222223E221C006CA2BAAABA827C),
.INIT_11(256'h00001C223A02221C00000202021E023E00003E02021E023E00001E222222221E),
.INIT_12(256'h000022120A060A1200000C121010103800003E080808083E00002222223E2222),
.INIT_13(256'h00001C222222221C000022322A262222000022222A2A362200003E0202020202),
.INIT_14(256'h00001E20201C023C000022120A1E221E00681C222222221C000002021E22221E),
.INIT_15(256'h0000142A2A222222000008141422222200001C2222222222000008080808083E),
.INIT_16(256'h001808080808081800003E020408103E00000808081C22220000221408081422),
.INIT_17(256'h00FF000000000000000000000022140800181010101010180000402010080402),
.INIT_18(256'h00001C2202021C0000001E22261A020200005C223C201C000000000000001008),
.INIT_19(256'h001C203C22223C00000002020E02221C00001C023E221C0000003C22322C2020),
.INIT_1A(256'h000022120E0A1202000C12101018001000001C08080C000800002222261A0202),
.INIT_1B(256'h00001C2222221C000000242424241A0000002A2A2A2A160000003E080808080C),
.INIT_1C(256'h00001E201C023C000000040404241A000020203C22322C000002021E22221E00),
.INIT_1D(256'h0000142A2A222200000008141422220000002C121212120000001C22020E0202),
.INIT_1E(256'h001008080408081000003E0408103E00001C203C222222000000221408142200),
.INIT_1F(256'h000000000000000000000060920C000000040808100808040008080808080808),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000143E143E1400000000000000141400000800080808080000000000000000),
.INIT_29(256'h0000000000000808006C12320C12120C00E2A4E8102E4A8E00081E281C0A3C08),
.INIT_2A(256'h00101010FE1010100000000022143E0800081020202010080008040202020408),
.INIT_2B(256'h00000204081020400000080000000000000000003E0000000008080000000000),
.INIT_2C(256'h00001C222010221C00003E040810221C00003E0808080C0800001C262A2A321C),
.INIT_2D(256'h000008081020223E00001C221E02221C00001C22203E023E00003C103E121418),
.INIT_2E(256'h0008080000000800000008000000080000001C22203C221C00001C22221C221C),
.INIT_2F(256'h000008000818221C000204081008040200003E00003E00000010080402040810),
.INIT_30(256'h00001C220202221C00001E22221E221E00002222223E221C006CA2BAAABA827C),
.INIT_31(256'h00001C223A02221C00000202021E023E00003E02021E023E00001E222222221E),
.INIT_32(256'h000022120A060A1200000C121010103800003E080808083E00002222223E2222),
.INIT_33(256'h00001C222222221C000022322A262222000022222A2A362200003E0202020202),
.INIT_34(256'h00001E20201C023C000022120A1E221E00681C222222221C000002021E22221E),
.INIT_35(256'h0000142A2A222222000008141422222200001C2222222222000008080808083E),
.INIT_36(256'h001808080808081800003E020408103E00000808081C22220000221408081422),
.INIT_37(256'h00FF000000000000000000000022140800181010101010180000402010080402),
.INIT_38(256'h00001C2202021C0000001E22261A020200005C223C201C000000000000001008),
.INIT_39(256'h001C203C22223C00000002020E02221C00001C023E221C0000003C22322C2020),
.INIT_3A(256'h000022120E0A1202000C12101018001000001C08080C000800002222261A0202),
.INIT_3B(256'h00001C2222221C000000242424241A0000002A2A2A2A160000003E080808080C),
.INIT_3C(256'h00001E201C023C000000040404241A000020203C22322C000002021E22221E00),
.INIT_3D(256'h0000142A2A222200000008141422220000002C121212120000001C22020E0202),
.INIT_3E(256'h001008080408081000003E0408103E00001C203C222222000000221408142200),
.INIT_3F(256'h000000000000000000000060920C000000040808100808040008080808080808),
.INIT_A(18'h00000),
.INIT_B(18'h00000),
.IS_ENARDEN_INVERTED(1'b1),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("PERFORMANCE"),
.READ_WIDTH_A(9),
.READ_WIDTH_B(0),
.RSTREG_PRIORITY_A("RSTREG"),
.RSTREG_PRIORITY_B("RSTREG"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(18'h00000),
.SRVAL_B(18'h00000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(9),
.WRITE_WIDTH_B(0))
PIXELS_reg
(.ADDRARDADDR({DOUT,DOUT,sel,1'b0,1'b0,1'b0}),
.ADDRBWRADDR({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
.CLKARDCLK(ETH_CLK_OBUF),
.CLKBWRCLK(1'b0),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
.DIBDI({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
.DIPADIP({1'b0,1'b0}),
.DIPBDIP({1'b1,1'b1}),
.DOADO({NLW_PIXELS_reg_DOADO_UNCONNECTED[15:8],PIXELS_reg__0}),
.DOBDO(NLW_PIXELS_reg_DOBDO_UNCONNECTED[15:0]),
.DOPADOP(NLW_PIXELS_reg_DOPADOP_UNCONNECTED[1:0]),
.DOPBDOP(NLW_PIXELS_reg_DOPBDOP_UNCONNECTED[1:0]),
.ENARDEN(BLANK_DEL),
.ENBWREN(1'b0),
.REGCEAREGCE(NLW_PIXELS_reg_REGCEAREGCE_UNCONNECTED),
.REGCEB(NLW_PIXELS_reg_REGCEB_UNCONNECTED),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.WEA({1'b0,1'b0}),
.WEBWE({1'b0,1'b0,1'b0,1'b0}));
FDRE \PIXROW_DEL_reg[0]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(TIMEING1_n_16),
.Q(sel[0]),
.R(1'b0));
FDRE \PIXROW_DEL_reg[1]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(TIMEING1_n_17),
.Q(sel[1]),
.R(1'b0));
FDRE \PIXROW_DEL_reg[2]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(TIMEING1_n_18),
.Q(sel[2]),
.R(1'b0));
VIDEO_TIME_GEN TIMEING1
(.ADDRBWRADDR({AOUT,TIMEING1_n_15}),
.BLANK(BLANK),
.D(TIMEING1_n_18),
.ETH_CLK_OBUF(ETH_CLK_OBUF),
.HSYNCH_DEL_reg(TIMEING1_n_19),
.INTERNAL_RST_reg(INTERNAL_RST_reg),
.\PIXCOL_DEL_reg[0] (TIMEING1_n_0),
.\PIXCOL_DEL_reg[1] (TIMEING1_n_1),
.\PIXCOL_DEL_reg[2] (TIMEING1_n_2),
.\PIXROW_DEL_reg[0] (TIMEING1_n_16),
.\PIXROW_DEL_reg[1] (TIMEING1_n_17),
.VSYNCH_DEL_reg(TIMEING1_n_20));
LUT4 #(
.INIT(16'h00E2))
\VGA_R_OBUF[3]_inst_i_1
(.I0(\VGA_R_OBUF[3]_inst_i_2_n_0 ),
.I1(\PIXCOL_DEL_DEL_reg_n_0_[2] ),
.I2(\VGA_R_OBUF[3]_inst_i_3_n_0 ),
.I3(BLANK_DEL_DEL),
.O(VGA_B_OBUF));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\VGA_R_OBUF[3]_inst_i_2
(.I0(PIXELS_reg__0[3]),
.I1(PIXELS_reg__0[2]),
.I2(\PIXCOL_DEL_DEL_reg_n_0_[1] ),
.I3(PIXELS_reg__0[1]),
.I4(\PIXCOL_DEL_DEL_reg_n_0_[0] ),
.I5(PIXELS_reg__0[0]),
.O(\VGA_R_OBUF[3]_inst_i_2_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\VGA_R_OBUF[3]_inst_i_3
(.I0(PIXELS_reg__0[7]),
.I1(PIXELS_reg__0[6]),
.I2(\PIXCOL_DEL_DEL_reg_n_0_[1] ),
.I3(PIXELS_reg__0[5]),
.I4(\PIXCOL_DEL_DEL_reg_n_0_[0] ),
.I5(PIXELS_reg__0[4]),
.O(\VGA_R_OBUF[3]_inst_i_3_n_0 ));
FDRE VSYNCH_DEL_reg
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(TIMEING1_n_20),
.Q(VSYNCH_DEL),
.R(1'b0));
FDRE VSYNCH_reg
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(VSYNCH_DEL),
.Q(VSYNCH),
.R(1'b0));
endmodule
|
module I2C
(SDA_TRI,
SCL_TRI,
ETH_CLK_OBUF,
SCL_IBUF,
INTERNAL_RST_reg,
SDA_IBUF);
output SDA_TRI;
output SCL_TRI;
input ETH_CLK_OBUF;
input SCL_IBUF;
input INTERNAL_RST_reg;
input SDA_IBUF;
wire BIT_i_1_n_0;
wire BIT_i_2_n_0;
wire BIT_i_3_n_0;
wire BIT_reg_n_0;
wire [2:0]COUNT;
wire \COUNT[0]_i_1__0_n_0 ;
wire \COUNT[1]_i_1__0_n_0 ;
wire \COUNT[2]_i_1_n_0 ;
wire \COUNT[2]_i_2_n_0 ;
wire ETH_CLK_OBUF;
wire [3:0]GET_BIT_RETURN;
wire \GET_BIT_RETURN[0]_i_1_n_0 ;
wire \GET_BIT_RETURN[3]_i_1_n_0 ;
wire INTERNAL_RST_reg;
wire SCL_IBUF;
wire SCL_I_D;
wire SCL_I_SYNCH;
wire SCL_O_i_1_n_0;
wire SCL_O_i_2_n_0;
wire SCL_O_i_3_n_0;
wire SCL_O_i_4_n_0;
wire SCL_TRI;
wire SDA_IBUF;
wire SDA_I_D;
wire SDA_I_SYNCH;
wire SDA_O_i_1_n_0;
wire SDA_O_i_2_n_0;
wire SDA_TRI;
wire [3:0]SEND_BIT_RETURN;
wire \SEND_BIT_RETURN[0]_i_1_n_0 ;
wire \SEND_BIT_RETURN[3]_i_1_n_0 ;
wire STARTED;
wire STARTED_i_1_n_0;
wire STARTED_i_2_n_0;
wire \STATE[0]_i_2_n_0 ;
wire \STATE[0]_i_3_n_0 ;
wire \STATE[1]_i_1_n_0 ;
wire \STATE[1]_i_2_n_0 ;
wire \STATE[1]_i_3_n_0 ;
wire \STATE[1]_i_4_n_0 ;
wire \STATE[2]_i_1_n_0 ;
wire \STATE[3]_i_2_n_0 ;
wire \STATE[3]_i_3_n_0 ;
wire \STATE[4]_i_1_n_0 ;
wire \STATE[4]_i_2_n_0 ;
wire \STATE[4]_i_3_n_0 ;
wire \STATE[4]_i_4_n_0 ;
wire \STATE[4]_i_5_n_0 ;
wire \STATE[4]_i_6_n_0 ;
wire \STATE_reg[0]_i_1_n_0 ;
wire \STATE_reg[3]_i_1_n_0 ;
wire \STATE_reg_n_0_[0] ;
wire \STATE_reg_n_0_[1] ;
wire \STATE_reg_n_0_[2] ;
wire \STATE_reg_n_0_[3] ;
wire \STATE_reg_n_0_[4] ;
wire S_I2C_IN_ACK_i_1_n_0;
wire S_I2C_IN_ACK_reg_n_0;
wire S_I2C_OUT_STB_i_1_n_0;
wire S_I2C_OUT_STB_reg_n_0;
wire \TIMER[0]_i_1_n_0 ;
wire \TIMER[0]_i_2_n_0 ;
wire \TIMER[0]_i_3_n_0 ;
wire \TIMER[10]_i_1_n_0 ;
wire \TIMER[10]_i_2_n_0 ;
wire \TIMER[10]_i_3_n_0 ;
wire \TIMER[10]_i_5_n_0 ;
wire \TIMER[10]_i_6_n_0 ;
wire \TIMER[10]_i_7_n_0 ;
wire \TIMER[11]_i_1_n_0 ;
wire \TIMER[1]_i_1__2_n_0 ;
wire \TIMER[2]_i_1_n_0 ;
wire \TIMER[3]_i_1__2_n_0 ;
wire \TIMER[4]_i_1__2_n_0 ;
wire \TIMER[4]_i_3_n_0 ;
wire \TIMER[4]_i_4_n_0 ;
wire \TIMER[4]_i_5_n_0 ;
wire \TIMER[4]_i_6_n_0 ;
wire \TIMER[5]_i_1__2_n_0 ;
wire \TIMER[5]_i_3_n_0 ;
wire \TIMER[5]_i_4_n_0 ;
wire \TIMER[5]_i_5_n_0 ;
wire \TIMER[5]_i_6_n_0 ;
wire \TIMER[6]_i_1_n_0 ;
wire \TIMER[7]_i_1_n_0 ;
wire \TIMER[8]_i_1_n_0 ;
wire \TIMER[9]_i_1__2_n_0 ;
wire \TIMER_reg[10]_i_4_n_5 ;
wire \TIMER_reg[10]_i_4_n_6 ;
wire \TIMER_reg[10]_i_4_n_7 ;
wire \TIMER_reg[4]_i_2_n_0 ;
wire \TIMER_reg[4]_i_2_n_4 ;
wire \TIMER_reg[4]_i_2_n_5 ;
wire \TIMER_reg[4]_i_2_n_6 ;
wire \TIMER_reg[4]_i_2_n_7 ;
wire \TIMER_reg[5]_i_2_n_0 ;
wire \TIMER_reg[5]_i_2_n_4 ;
wire \TIMER_reg[5]_i_2_n_5 ;
wire \TIMER_reg[5]_i_2_n_6 ;
wire \TIMER_reg[5]_i_2_n_7 ;
wire \TIMER_reg_n_0_[0] ;
wire \TIMER_reg_n_0_[10] ;
wire \TIMER_reg_n_0_[11] ;
wire \TIMER_reg_n_0_[1] ;
wire \TIMER_reg_n_0_[2] ;
wire \TIMER_reg_n_0_[3] ;
wire \TIMER_reg_n_0_[4] ;
wire \TIMER_reg_n_0_[5] ;
wire \TIMER_reg_n_0_[6] ;
wire \TIMER_reg_n_0_[7] ;
wire \TIMER_reg_n_0_[8] ;
wire \TIMER_reg_n_0_[9] ;
wire g0_b0_n_0;
wire [3:0]\NLW_TIMER_reg[10]_i_4_CO_UNCONNECTED ;
wire [3:3]\NLW_TIMER_reg[10]_i_4_O_UNCONNECTED ;
wire [2:0]\NLW_TIMER_reg[4]_i_2_CO_UNCONNECTED ;
wire [2:0]\NLW_TIMER_reg[5]_i_2_CO_UNCONNECTED ;
LUT6 #(
.INIT(64'hFFF0FA3300000A00))
BIT_i_1
(.I0(SDA_I_SYNCH),
.I1(BIT_i_2_n_0),
.I2(BIT_i_3_n_0),
.I3(\STATE_reg_n_0_[4] ),
.I4(\STATE_reg_n_0_[2] ),
.I5(BIT_reg_n_0),
.O(BIT_i_1_n_0));
LUT3 #(
.INIT(8'h40))
BIT_i_2
(.I0(\STATE_reg_n_0_[1] ),
.I1(\STATE_reg_n_0_[0] ),
.I2(\STATE_reg_n_0_[3] ),
.O(BIT_i_2_n_0));
LUT3 #(
.INIT(8'hEF))
BIT_i_3
(.I0(\STATE_reg_n_0_[0] ),
.I1(\STATE_reg_n_0_[3] ),
.I2(\STATE_reg_n_0_[1] ),
.O(BIT_i_3_n_0));
FDRE BIT_reg
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(BIT_i_1_n_0),
.Q(BIT_reg_n_0),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair23" *)
LUT4 #(
.INIT(16'h1FF0))
\COUNT[0]_i_1__0
(.I0(\STATE_reg_n_0_[2] ),
.I1(\STATE_reg_n_0_[1] ),
.I2(\COUNT[2]_i_2_n_0 ),
.I3(COUNT[0]),
.O(\COUNT[0]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair23" *)
LUT5 #(
.INIT(32'hF1FF1F00))
\COUNT[1]_i_1__0
(.I0(\STATE_reg_n_0_[1] ),
.I1(\STATE_reg_n_0_[2] ),
.I2(COUNT[0]),
.I3(\COUNT[2]_i_2_n_0 ),
.I4(COUNT[1]),
.O(\COUNT[1]_i_1__0_n_0 ));
LUT6 #(
.INIT(64'hFFF1FFFF111F0000))
\COUNT[2]_i_1
(.I0(\STATE_reg_n_0_[2] ),
.I1(\STATE_reg_n_0_[1] ),
.I2(COUNT[0]),
.I3(COUNT[1]),
.I4(\COUNT[2]_i_2_n_0 ),
.I5(COUNT[2]),
.O(\COUNT[2]_i_1_n_0 ));
LUT5 #(
.INIT(32'h00100401))
\COUNT[2]_i_2
(.I0(\STATE_reg_n_0_[4] ),
.I1(\STATE_reg_n_0_[3] ),
.I2(\STATE_reg_n_0_[2] ),
.I3(\STATE_reg_n_0_[1] ),
.I4(\STATE_reg_n_0_[0] ),
.O(\COUNT[2]_i_2_n_0 ));
FDRE \COUNT_reg[0]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(\COUNT[0]_i_1__0_n_0 ),
.Q(COUNT[0]),
.R(1'b0));
FDRE \COUNT_reg[1]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(\COUNT[1]_i_1__0_n_0 ),
.Q(COUNT[1]),
.R(1'b0));
FDRE \COUNT_reg[2]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(\COUNT[2]_i_1_n_0 ),
.Q(COUNT[2]),
.R(1'b0));
LUT6 #(
.INIT(64'hFBFFFFFF00000010))
\GET_BIT_RETURN[0]_i_1
(.I0(\STATE_reg_n_0_[4] ),
.I1(\STATE_reg_n_0_[3] ),
.I2(\STATE_reg_n_0_[2] ),
.I3(\STATE_reg_n_0_[1] ),
.I4(\STATE_reg_n_0_[0] ),
.I5(GET_BIT_RETURN[0]),
.O(\GET_BIT_RETURN[0]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFEF04000000))
\GET_BIT_RETURN[3]_i_1
(.I0(\STATE_reg_n_0_[4] ),
.I1(\STATE_reg_n_0_[3] ),
.I2(\STATE_reg_n_0_[2] ),
.I3(\STATE_reg_n_0_[1] ),
.I4(\STATE_reg_n_0_[0] ),
.I5(GET_BIT_RETURN[3]),
.O(\GET_BIT_RETURN[3]_i_1_n_0 ));
FDRE \GET_BIT_RETURN_reg[0]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(\GET_BIT_RETURN[0]_i_1_n_0 ),
.Q(GET_BIT_RETURN[0]),
.R(1'b0));
FDRE \GET_BIT_RETURN_reg[3]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(\GET_BIT_RETURN[3]_i_1_n_0 ),
.Q(GET_BIT_RETURN[3]),
.R(1'b0));
FDRE SCL_I_D_reg
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(SCL_IBUF),
.Q(SCL_I_D),
.R(1'b0));
FDRE SCL_I_SYNCH_reg
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(SCL_I_D),
.Q(SCL_I_SYNCH),
.R(1'b0));
LUT6 #(
.INIT(64'h403FFFFF403F0000))
SCL_O_i_1
(.I0(\STATE_reg_n_0_[0] ),
.I1(\STATE_reg_n_0_[3] ),
.I2(\STATE_reg_n_0_[2] ),
.I3(\STATE_reg_n_0_[1] ),
.I4(SCL_O_i_2_n_0),
.I5(SCL_TRI),
.O(SCL_O_i_1_n_0));
LUT6 #(
.INIT(64'hFFFFFFFF01000000))
SCL_O_i_2
(.I0(\TIMER[0]_i_2_n_0 ),
.I1(SCL_O_i_3_n_0),
.I2(\TIMER_reg_n_0_[0] ),
.I3(\STATE_reg_n_0_[2] ),
.I4(\STATE_reg_n_0_[0] ),
.I5(SCL_O_i_4_n_0),
.O(SCL_O_i_2_n_0));
LUT2 #(
.INIT(4'h1))
SCL_O_i_3
(.I0(\STATE_reg_n_0_[4] ),
.I1(\STATE_reg_n_0_[3] ),
.O(SCL_O_i_3_n_0));
LUT6 #(
.INIT(64'h3C0C0C2C3C000000))
SCL_O_i_4
(.I0(\TIMER[10]_i_3_n_0 ),
.I1(\STATE_reg_n_0_[0] ),
.I2(\STATE_reg_n_0_[1] ),
.I3(\STATE_reg_n_0_[2] ),
.I4(\STATE_reg_n_0_[3] ),
.I5(\STATE_reg_n_0_[4] ),
.O(SCL_O_i_4_n_0));
FDSE SCL_O_reg
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(SCL_O_i_1_n_0),
.Q(SCL_TRI),
.S(INTERNAL_RST_reg));
FDRE SDA_I_D_reg
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(SDA_IBUF),
.Q(SDA_I_D),
.R(1'b0));
FDRE SDA_I_SYNCH_reg
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(SDA_I_D),
.Q(SDA_I_SYNCH),
.R(1'b0));
LUT6 #(
.INIT(64'hADA5FFFFADA50000))
SDA_O_i_1
(.I0(\STATE_reg_n_0_[3] ),
.I1(BIT_reg_n_0),
.I2(\STATE_reg_n_0_[1] ),
.I3(\STATE_reg_n_0_[2] ),
.I4(SDA_O_i_2_n_0),
.I5(SDA_TRI),
.O(SDA_O_i_1_n_0));
LUT6 #(
.INIT(64'h9098803080988030))
SDA_O_i_2
(.I0(\STATE_reg_n_0_[2] ),
.I1(\STATE_reg_n_0_[0] ),
.I2(\STATE_reg_n_0_[4] ),
.I3(\STATE_reg_n_0_[1] ),
.I4(\STATE_reg_n_0_[3] ),
.I5(\TIMER[10]_i_3_n_0 ),
.O(SDA_O_i_2_n_0));
FDSE SDA_O_reg
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(SDA_O_i_1_n_0),
.Q(SDA_TRI),
.S(INTERNAL_RST_reg));
LUT6 #(
.INIT(64'hFFFFFFBF01000000))
\SEND_BIT_RETURN[0]_i_1
(.I0(\STATE_reg_n_0_[4] ),
.I1(\STATE_reg_n_0_[3] ),
.I2(\STATE_reg_n_0_[0] ),
.I3(\STATE_reg_n_0_[1] ),
.I4(\STATE_reg_n_0_[2] ),
.I5(SEND_BIT_RETURN[0]),
.O(\SEND_BIT_RETURN[0]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFEFFFFFF00000040))
\SEND_BIT_RETURN[3]_i_1
(.I0(\STATE_reg_n_0_[4] ),
.I1(\STATE_reg_n_0_[3] ),
.I2(\STATE_reg_n_0_[0] ),
.I3(\STATE_reg_n_0_[1] ),
.I4(\STATE_reg_n_0_[2] ),
.I5(SEND_BIT_RETURN[3]),
.O(\SEND_BIT_RETURN[3]_i_1_n_0 ));
FDRE \SEND_BIT_RETURN_reg[0]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(\SEND_BIT_RETURN[0]_i_1_n_0 ),
.Q(SEND_BIT_RETURN[0]),
.R(1'b0));
FDRE \SEND_BIT_RETURN_reg[3]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(\SEND_BIT_RETURN[3]_i_1_n_0 ),
.Q(SEND_BIT_RETURN[3]),
.R(1'b0));
LUT6 #(
.INIT(64'h7FFDFFFD08000000))
STARTED_i_1
(.I0(STARTED_i_2_n_0),
.I1(\STATE_reg_n_0_[4] ),
.I2(\STATE_reg_n_0_[3] ),
.I3(\STATE_reg_n_0_[2] ),
.I4(\TIMER[10]_i_3_n_0 ),
.I5(STARTED),
.O(STARTED_i_1_n_0));
LUT4 #(
.INIT(16'hEAAB))
STARTED_i_2
(.I0(\STATE_reg_n_0_[3] ),
.I1(\STATE_reg_n_0_[1] ),
.I2(\STATE_reg_n_0_[2] ),
.I3(\STATE_reg_n_0_[0] ),
.O(STARTED_i_2_n_0));
FDRE STARTED_reg
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(STARTED_i_1_n_0),
.Q(STARTED),
.R(1'b0));
LUT5 #(
.INIT(32'hB0FC3CCF))
\STATE[0]_i_2
(.I0(SEND_BIT_RETURN[0]),
.I1(\STATE_reg_n_0_[3] ),
.I2(\STATE_reg_n_0_[1] ),
.I3(\STATE_reg_n_0_[0] ),
.I4(\STATE_reg_n_0_[2] ),
.O(\STATE[0]_i_2_n_0 ));
LUT6 #(
.INIT(64'h040004005F5F5A5F))
\STATE[0]_i_3
(.I0(\STATE_reg_n_0_[3] ),
.I1(STARTED),
.I2(\STATE_reg_n_0_[2] ),
.I3(\STATE_reg_n_0_[1] ),
.I4(GET_BIT_RETURN[0]),
.I5(\STATE_reg_n_0_[0] ),
.O(\STATE[0]_i_3_n_0 ));
LUT2 #(
.INIT(4'h2))
\STATE[1]_i_1
(.I0(\STATE[1]_i_2_n_0 ),
.I1(\STATE[1]_i_3_n_0 ),
.O(\STATE[1]_i_1_n_0 ));
LUT6 #(
.INIT(64'h12781258FFFFFFFF))
\STATE[1]_i_2
(.I0(\STATE_reg_n_0_[1] ),
.I1(\STATE_reg_n_0_[2] ),
.I2(\STATE_reg_n_0_[0] ),
.I3(\STATE_reg_n_0_[3] ),
.I4(STARTED),
.I5(\STATE_reg_n_0_[4] ),
.O(\STATE[1]_i_2_n_0 ));
LUT6 #(
.INIT(64'h0005010555155055))
\STATE[1]_i_3
(.I0(\STATE_reg_n_0_[4] ),
.I1(\STATE[1]_i_4_n_0 ),
.I2(\STATE_reg_n_0_[3] ),
.I3(\STATE_reg_n_0_[0] ),
.I4(\STATE_reg_n_0_[1] ),
.I5(\STATE_reg_n_0_[2] ),
.O(\STATE[1]_i_3_n_0 ));
LUT3 #(
.INIT(8'h01))
\STATE[1]_i_4
(.I0(COUNT[2]),
.I1(COUNT[1]),
.I2(COUNT[0]),
.O(\STATE[1]_i_4_n_0 ));
LUT6 #(
.INIT(64'h406EB828406E3828))
\STATE[2]_i_1
(.I0(\STATE_reg_n_0_[2] ),
.I1(\STATE_reg_n_0_[1] ),
.I2(\STATE_reg_n_0_[0] ),
.I3(\STATE_reg_n_0_[3] ),
.I4(\STATE_reg_n_0_[4] ),
.I5(SEND_BIT_RETURN[0]),
.O(\STATE[2]_i_1_n_0 ));
LUT5 #(
.INIT(32'h8F00F5F0))
\STATE[3]_i_2
(.I0(\STATE_reg_n_0_[2] ),
.I1(SEND_BIT_RETURN[3]),
.I2(\STATE_reg_n_0_[1] ),
.I3(\STATE_reg_n_0_[3] ),
.I4(\STATE_reg_n_0_[0] ),
.O(\STATE[3]_i_2_n_0 ));
LUT5 #(
.INIT(32'h0F0F0200))
\STATE[3]_i_3
(.I0(GET_BIT_RETURN[3]),
.I1(\STATE_reg_n_0_[0] ),
.I2(\STATE_reg_n_0_[2] ),
.I3(\STATE_reg_n_0_[1] ),
.I4(\STATE_reg_n_0_[3] ),
.O(\STATE[3]_i_3_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFF4F4F0FF))
\STATE[4]_i_1
(.I0(\STATE[4]_i_3_n_0 ),
.I1(\STATE_reg_n_0_[0] ),
.I2(\STATE[4]_i_4_n_0 ),
.I3(\STATE[4]_i_5_n_0 ),
.I4(\STATE_reg_n_0_[1] ),
.I5(\STATE[4]_i_6_n_0 ),
.O(\STATE[4]_i_1_n_0 ));
LUT5 #(
.INIT(32'h1301FD80))
\STATE[4]_i_2
(.I0(\STATE_reg_n_0_[1] ),
.I1(\STATE_reg_n_0_[3] ),
.I2(\STATE_reg_n_0_[0] ),
.I3(\STATE_reg_n_0_[4] ),
.I4(\STATE_reg_n_0_[2] ),
.O(\STATE[4]_i_2_n_0 ));
LUT6 #(
.INIT(64'hEEEEEE0FEE00EE0F))
\STATE[4]_i_3
(.I0(\TIMER_reg_n_0_[0] ),
.I1(\TIMER[0]_i_2_n_0 ),
.I2(S_I2C_OUT_STB_reg_n_0),
.I3(\STATE_reg_n_0_[3] ),
.I4(\STATE_reg_n_0_[4] ),
.I5(\STATE_reg_n_0_[2] ),
.O(\STATE[4]_i_3_n_0 ));
LUT5 #(
.INIT(32'h80AA8000))
\STATE[4]_i_4
(.I0(\TIMER[10]_i_3_n_0 ),
.I1(\STATE_reg_n_0_[2] ),
.I2(\STATE_reg_n_0_[3] ),
.I3(\STATE_reg_n_0_[0] ),
.I4(\STATE_reg_n_0_[4] ),
.O(\STATE[4]_i_4_n_0 ));
LUT6 #(
.INIT(64'hFC0C0CDCFCFCDCDC))
\STATE[4]_i_5
(.I0(S_I2C_IN_ACK_reg_n_0),
.I1(\STATE_reg_n_0_[4] ),
.I2(\STATE_reg_n_0_[0] ),
.I3(\STATE_reg_n_0_[3] ),
.I4(\STATE_reg_n_0_[2] ),
.I5(SCL_I_SYNCH),
.O(\STATE[4]_i_5_n_0 ));
LUT5 #(
.INIT(32'h004075BB))
\STATE[4]_i_6
(.I0(\STATE_reg_n_0_[2] ),
.I1(\STATE_reg_n_0_[0] ),
.I2(SCL_I_SYNCH),
.I3(\STATE_reg_n_0_[3] ),
.I4(\STATE_reg_n_0_[4] ),
.O(\STATE[4]_i_6_n_0 ));
FDRE \STATE_reg[0]
(.C(ETH_CLK_OBUF),
.CE(\STATE[4]_i_1_n_0 ),
.D(\STATE_reg[0]_i_1_n_0 ),
.Q(\STATE_reg_n_0_[0] ),
.R(INTERNAL_RST_reg));
MUXF7 \STATE_reg[0]_i_1
(.I0(\STATE[0]_i_2_n_0 ),
.I1(\STATE[0]_i_3_n_0 ),
.O(\STATE_reg[0]_i_1_n_0 ),
.S(\STATE_reg_n_0_[4] ));
FDRE \STATE_reg[1]
(.C(ETH_CLK_OBUF),
.CE(\STATE[4]_i_1_n_0 ),
.D(\STATE[1]_i_1_n_0 ),
.Q(\STATE_reg_n_0_[1] ),
.R(INTERNAL_RST_reg));
FDRE \STATE_reg[2]
(.C(ETH_CLK_OBUF),
.CE(\STATE[4]_i_1_n_0 ),
.D(\STATE[2]_i_1_n_0 ),
.Q(\STATE_reg_n_0_[2] ),
.R(INTERNAL_RST_reg));
FDRE \STATE_reg[3]
(.C(ETH_CLK_OBUF),
.CE(\STATE[4]_i_1_n_0 ),
.D(\STATE_reg[3]_i_1_n_0 ),
.Q(\STATE_reg_n_0_[3] ),
.R(INTERNAL_RST_reg));
MUXF7 \STATE_reg[3]_i_1
(.I0(\STATE[3]_i_2_n_0 ),
.I1(\STATE[3]_i_3_n_0 ),
.O(\STATE_reg[3]_i_1_n_0 ),
.S(\STATE_reg_n_0_[4] ));
FDRE \STATE_reg[4]
(.C(ETH_CLK_OBUF),
.CE(\STATE[4]_i_1_n_0 ),
.D(\STATE[4]_i_2_n_0 ),
.Q(\STATE_reg_n_0_[4] ),
.R(INTERNAL_RST_reg));
LUT6 #(
.INIT(64'hFFFEFFFF00010000))
S_I2C_IN_ACK_i_1
(.I0(\STATE_reg_n_0_[2] ),
.I1(\STATE_reg_n_0_[1] ),
.I2(\STATE_reg_n_0_[3] ),
.I3(\STATE_reg_n_0_[4] ),
.I4(\STATE_reg_n_0_[0] ),
.I5(S_I2C_IN_ACK_reg_n_0),
.O(S_I2C_IN_ACK_i_1_n_0));
FDRE S_I2C_IN_ACK_reg
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(S_I2C_IN_ACK_i_1_n_0),
.Q(S_I2C_IN_ACK_reg_n_0),
.R(1'b0));
LUT6 #(
.INIT(64'hFFFDFFFF00020000))
S_I2C_OUT_STB_i_1
(.I0(\STATE_reg_n_0_[1] ),
.I1(\STATE_reg_n_0_[2] ),
.I2(\STATE_reg_n_0_[3] ),
.I3(\STATE_reg_n_0_[4] ),
.I4(\STATE_reg_n_0_[0] ),
.I5(S_I2C_OUT_STB_reg_n_0),
.O(S_I2C_OUT_STB_i_1_n_0));
FDRE S_I2C_OUT_STB_reg
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(S_I2C_OUT_STB_i_1_n_0),
.Q(S_I2C_OUT_STB_reg_n_0),
.R(INTERNAL_RST_reg));
LUT5 #(
.INIT(32'h00FFA800))
\TIMER[0]_i_1
(.I0(\TIMER[0]_i_2_n_0 ),
.I1(\STATE_reg_n_0_[4] ),
.I2(\STATE_reg_n_0_[3] ),
.I3(g0_b0_n_0),
.I4(\TIMER_reg_n_0_[0] ),
.O(\TIMER[0]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFFFFFFE))
\TIMER[0]_i_2
(.I0(\TIMER_reg_n_0_[3] ),
.I1(\TIMER_reg_n_0_[11] ),
.I2(\TIMER_reg_n_0_[7] ),
.I3(\TIMER_reg_n_0_[2] ),
.I4(\TIMER_reg_n_0_[1] ),
.I5(\TIMER[0]_i_3_n_0 ),
.O(\TIMER[0]_i_2_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFFFFFFE))
\TIMER[0]_i_3
(.I0(\TIMER_reg_n_0_[6] ),
.I1(\TIMER_reg_n_0_[8] ),
.I2(\TIMER_reg_n_0_[9] ),
.I3(\TIMER_reg_n_0_[10] ),
.I4(\TIMER_reg_n_0_[5] ),
.I5(\TIMER_reg_n_0_[4] ),
.O(\TIMER[0]_i_3_n_0 ));
LUT2 #(
.INIT(4'h8))
\TIMER[10]_i_1
(.I0(\TIMER[10]_i_3_n_0 ),
.I1(g0_b0_n_0),
.O(\TIMER[10]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair30" *)
LUT3 #(
.INIT(8'hA8))
\TIMER[10]_i_2
(.I0(\TIMER_reg[10]_i_4_n_6 ),
.I1(\STATE_reg_n_0_[3] ),
.I2(\STATE_reg_n_0_[4] ),
.O(\TIMER[10]_i_2_n_0 ));
LUT2 #(
.INIT(4'h1))
\TIMER[10]_i_3
(.I0(\TIMER_reg_n_0_[0] ),
.I1(\TIMER[0]_i_2_n_0 ),
.O(\TIMER[10]_i_3_n_0 ));
LUT1 #(
.INIT(2'h1))
\TIMER[10]_i_5
(.I0(\TIMER_reg_n_0_[11] ),
.O(\TIMER[10]_i_5_n_0 ));
LUT1 #(
.INIT(2'h1))
\TIMER[10]_i_6
(.I0(\TIMER_reg_n_0_[10] ),
.O(\TIMER[10]_i_6_n_0 ));
LUT1 #(
.INIT(2'h1))
\TIMER[10]_i_7
(.I0(\TIMER_reg_n_0_[9] ),
.O(\TIMER[10]_i_7_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair28" *)
LUT3 #(
.INIT(8'hAB))
\TIMER[11]_i_1
(.I0(\TIMER_reg[10]_i_4_n_5 ),
.I1(\STATE_reg_n_0_[3] ),
.I2(\STATE_reg_n_0_[4] ),
.O(\TIMER[11]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair30" *)
LUT3 #(
.INIT(8'hA8))
\TIMER[1]_i_1__2
(.I0(\TIMER_reg[4]_i_2_n_7 ),
.I1(\STATE_reg_n_0_[3] ),
.I2(\STATE_reg_n_0_[4] ),
.O(\TIMER[1]_i_1__2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair27" *)
LUT3 #(
.INIT(8'hAB))
\TIMER[2]_i_1
(.I0(\TIMER_reg[4]_i_2_n_6 ),
.I1(\STATE_reg_n_0_[3] ),
.I2(\STATE_reg_n_0_[4] ),
.O(\TIMER[2]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair31" *)
LUT3 #(
.INIT(8'hA8))
\TIMER[3]_i_1__2
(.I0(\TIMER_reg[4]_i_2_n_5 ),
.I1(\STATE_reg_n_0_[3] ),
.I2(\STATE_reg_n_0_[4] ),
.O(\TIMER[3]_i_1__2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair32" *)
LUT3 #(
.INIT(8'hA8))
\TIMER[4]_i_1__2
(.I0(\TIMER_reg[4]_i_2_n_4 ),
.I1(\STATE_reg_n_0_[3] ),
.I2(\STATE_reg_n_0_[4] ),
.O(\TIMER[4]_i_1__2_n_0 ));
LUT1 #(
.INIT(2'h1))
\TIMER[4]_i_3
(.I0(\TIMER_reg_n_0_[4] ),
.O(\TIMER[4]_i_3_n_0 ));
LUT1 #(
.INIT(2'h1))
\TIMER[4]_i_4
(.I0(\TIMER_reg_n_0_[3] ),
.O(\TIMER[4]_i_4_n_0 ));
LUT1 #(
.INIT(2'h1))
\TIMER[4]_i_5
(.I0(\TIMER_reg_n_0_[2] ),
.O(\TIMER[4]_i_5_n_0 ));
LUT1 #(
.INIT(2'h1))
\TIMER[4]_i_6
(.I0(\TIMER_reg_n_0_[1] ),
.O(\TIMER[4]_i_6_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair32" *)
LUT3 #(
.INIT(8'hA8))
\TIMER[5]_i_1__2
(.I0(\TIMER_reg[5]_i_2_n_7 ),
.I1(\STATE_reg_n_0_[3] ),
.I2(\STATE_reg_n_0_[4] ),
.O(\TIMER[5]_i_1__2_n_0 ));
LUT1 #(
.INIT(2'h1))
\TIMER[5]_i_3
(.I0(\TIMER_reg_n_0_[8] ),
.O(\TIMER[5]_i_3_n_0 ));
LUT1 #(
.INIT(2'h1))
\TIMER[5]_i_4
(.I0(\TIMER_reg_n_0_[7] ),
.O(\TIMER[5]_i_4_n_0 ));
LUT1 #(
.INIT(2'h1))
\TIMER[5]_i_5
(.I0(\TIMER_reg_n_0_[6] ),
.O(\TIMER[5]_i_5_n_0 ));
LUT1 #(
.INIT(2'h1))
\TIMER[5]_i_6
(.I0(\TIMER_reg_n_0_[5] ),
.O(\TIMER[5]_i_6_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair28" *)
LUT3 #(
.INIT(8'hAB))
\TIMER[6]_i_1
(.I0(\TIMER_reg[5]_i_2_n_6 ),
.I1(\STATE_reg_n_0_[3] ),
.I2(\STATE_reg_n_0_[4] ),
.O(\TIMER[6]_i_1_n_0 ));
LUT3 #(
.INIT(8'hAB))
\TIMER[7]_i_1
(.I0(\TIMER_reg[5]_i_2_n_5 ),
.I1(\STATE_reg_n_0_[3] ),
.I2(\STATE_reg_n_0_[4] ),
.O(\TIMER[7]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair27" *)
LUT3 #(
.INIT(8'hAB))
\TIMER[8]_i_1
(.I0(\TIMER_reg[5]_i_2_n_4 ),
.I1(\STATE_reg_n_0_[3] ),
.I2(\STATE_reg_n_0_[4] ),
.O(\TIMER[8]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair31" *)
LUT3 #(
.INIT(8'hA8))
\TIMER[9]_i_1__2
(.I0(\TIMER_reg[10]_i_4_n_7 ),
.I1(\STATE_reg_n_0_[3] ),
.I2(\STATE_reg_n_0_[4] ),
.O(\TIMER[9]_i_1__2_n_0 ));
FDRE \TIMER_reg[0]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(\TIMER[0]_i_1_n_0 ),
.Q(\TIMER_reg_n_0_[0] ),
.R(1'b0));
FDRE \TIMER_reg[10]
(.C(ETH_CLK_OBUF),
.CE(g0_b0_n_0),
.D(\TIMER[10]_i_2_n_0 ),
.Q(\TIMER_reg_n_0_[10] ),
.R(\TIMER[10]_i_1_n_0 ));
CARRY4 \TIMER_reg[10]_i_4
(.CI(\TIMER_reg[5]_i_2_n_0 ),
.CO(\NLW_TIMER_reg[10]_i_4_CO_UNCONNECTED [3:0]),
.CYINIT(1'b0),
.DI({1'b0,1'b0,\TIMER_reg_n_0_[10] ,\TIMER_reg_n_0_[9] }),
.O({\NLW_TIMER_reg[10]_i_4_O_UNCONNECTED [3],\TIMER_reg[10]_i_4_n_5 ,\TIMER_reg[10]_i_4_n_6 ,\TIMER_reg[10]_i_4_n_7 }),
.S({1'b0,\TIMER[10]_i_5_n_0 ,\TIMER[10]_i_6_n_0 ,\TIMER[10]_i_7_n_0 }));
FDSE \TIMER_reg[11]
(.C(ETH_CLK_OBUF),
.CE(g0_b0_n_0),
.D(\TIMER[11]_i_1_n_0 ),
.Q(\TIMER_reg_n_0_[11] ),
.S(\TIMER[10]_i_1_n_0 ));
FDRE \TIMER_reg[1]
(.C(ETH_CLK_OBUF),
.CE(g0_b0_n_0),
.D(\TIMER[1]_i_1__2_n_0 ),
.Q(\TIMER_reg_n_0_[1] ),
.R(\TIMER[10]_i_1_n_0 ));
FDSE \TIMER_reg[2]
(.C(ETH_CLK_OBUF),
.CE(g0_b0_n_0),
.D(\TIMER[2]_i_1_n_0 ),
.Q(\TIMER_reg_n_0_[2] ),
.S(\TIMER[10]_i_1_n_0 ));
FDRE \TIMER_reg[3]
(.C(ETH_CLK_OBUF),
.CE(g0_b0_n_0),
.D(\TIMER[3]_i_1__2_n_0 ),
.Q(\TIMER_reg_n_0_[3] ),
.R(\TIMER[10]_i_1_n_0 ));
FDRE \TIMER_reg[4]
(.C(ETH_CLK_OBUF),
.CE(g0_b0_n_0),
.D(\TIMER[4]_i_1__2_n_0 ),
.Q(\TIMER_reg_n_0_[4] ),
.R(\TIMER[10]_i_1_n_0 ));
CARRY4 \TIMER_reg[4]_i_2
(.CI(1'b0),
.CO({\TIMER_reg[4]_i_2_n_0 ,\NLW_TIMER_reg[4]_i_2_CO_UNCONNECTED [2:0]}),
.CYINIT(\TIMER_reg_n_0_[0] ),
.DI({\TIMER_reg_n_0_[4] ,\TIMER_reg_n_0_[3] ,\TIMER_reg_n_0_[2] ,\TIMER_reg_n_0_[1] }),
.O({\TIMER_reg[4]_i_2_n_4 ,\TIMER_reg[4]_i_2_n_5 ,\TIMER_reg[4]_i_2_n_6 ,\TIMER_reg[4]_i_2_n_7 }),
.S({\TIMER[4]_i_3_n_0 ,\TIMER[4]_i_4_n_0 ,\TIMER[4]_i_5_n_0 ,\TIMER[4]_i_6_n_0 }));
FDRE \TIMER_reg[5]
(.C(ETH_CLK_OBUF),
.CE(g0_b0_n_0),
.D(\TIMER[5]_i_1__2_n_0 ),
.Q(\TIMER_reg_n_0_[5] ),
.R(\TIMER[10]_i_1_n_0 ));
CARRY4 \TIMER_reg[5]_i_2
(.CI(\TIMER_reg[4]_i_2_n_0 ),
.CO({\TIMER_reg[5]_i_2_n_0 ,\NLW_TIMER_reg[5]_i_2_CO_UNCONNECTED [2:0]}),
.CYINIT(1'b0),
.DI({\TIMER_reg_n_0_[8] ,\TIMER_reg_n_0_[7] ,\TIMER_reg_n_0_[6] ,\TIMER_reg_n_0_[5] }),
.O({\TIMER_reg[5]_i_2_n_4 ,\TIMER_reg[5]_i_2_n_5 ,\TIMER_reg[5]_i_2_n_6 ,\TIMER_reg[5]_i_2_n_7 }),
.S({\TIMER[5]_i_3_n_0 ,\TIMER[5]_i_4_n_0 ,\TIMER[5]_i_5_n_0 ,\TIMER[5]_i_6_n_0 }));
FDSE \TIMER_reg[6]
(.C(ETH_CLK_OBUF),
.CE(g0_b0_n_0),
.D(\TIMER[6]_i_1_n_0 ),
.Q(\TIMER_reg_n_0_[6] ),
.S(\TIMER[10]_i_1_n_0 ));
FDSE \TIMER_reg[7]
(.C(ETH_CLK_OBUF),
.CE(g0_b0_n_0),
.D(\TIMER[7]_i_1_n_0 ),
.Q(\TIMER_reg_n_0_[7] ),
.S(\TIMER[10]_i_1_n_0 ));
FDSE \TIMER_reg[8]
(.C(ETH_CLK_OBUF),
.CE(g0_b0_n_0),
.D(\TIMER[8]_i_1_n_0 ),
.Q(\TIMER_reg_n_0_[8] ),
.S(\TIMER[10]_i_1_n_0 ));
FDRE \TIMER_reg[9]
(.C(ETH_CLK_OBUF),
.CE(g0_b0_n_0),
.D(\TIMER[9]_i_1__2_n_0 ),
.Q(\TIMER_reg_n_0_[9] ),
.R(\TIMER[10]_i_1_n_0 ));
LUT5 #(
.INIT(32'h1DD5A001))
g0_b0
(.I0(\STATE_reg_n_0_[0] ),
.I1(\STATE_reg_n_0_[1] ),
.I2(\STATE_reg_n_0_[2] ),
.I3(\STATE_reg_n_0_[3] ),
.I4(\STATE_reg_n_0_[4] ),
.O(g0_b0_n_0));
endmodule
|
module IOBUF_UNIQ_BASE_
(IO,
O,
I,
T);
inout IO;
output O;
input I;
input T;
wire I;
wire IO;
wire O;
wire T;
IBUF IBUF
(.I(IO),
.O(O));
OBUFT OBUFT
(.I(I),
.O(IO),
.T(T));
endmodule
|
module IOBUF_HD3
(IO,
O,
I,
T);
inout IO;
output O;
input I;
input T;
wire I;
wire IO;
wire O;
wire T;
IBUF #(
.IOSTANDARD("DEFAULT"))
IBUF
(.I(IO),
.O(O));
OBUFT #(
.IOSTANDARD("DEFAULT"))
OBUFT
(.I(I),
.O(IO),
.T(T));
endmodule
|
module PWM
(LED_R_PWM_OBUF,
ETH_CLK_OBUF);
output LED_R_PWM_OBUF;
input ETH_CLK_OBUF;
wire \COUNT[0]_i_1__1_n_0 ;
wire \COUNT[1]_i_1__1_n_0 ;
wire \COUNT[1]_i_2_n_0 ;
wire \COUNT[2]_i_1__0_n_0 ;
wire \COUNT[3]_i_1_n_0 ;
wire \COUNT[3]_i_2_n_0 ;
wire \COUNT[4]_i_1_n_0 ;
wire \COUNT[5]_i_1_n_0 ;
wire \COUNT[6]_i_1_n_0 ;
wire \COUNT[7]_i_1_n_0 ;
wire \COUNT[7]_i_2_n_0 ;
wire \COUNT[7]_i_3_n_0 ;
wire \COUNT_reg_n_0_[0] ;
wire \COUNT_reg_n_0_[1] ;
wire \COUNT_reg_n_0_[2] ;
wire \COUNT_reg_n_0_[3] ;
wire \COUNT_reg_n_0_[4] ;
wire \COUNT_reg_n_0_[5] ;
wire \COUNT_reg_n_0_[6] ;
wire \COUNT_reg_n_0_[7] ;
wire ETH_CLK_OBUF;
wire LED_R_PWM_OBUF;
wire OUT_BIT_i_10_n_0;
wire OUT_BIT_i_1_n_0;
wire OUT_BIT_i_3_n_0;
wire OUT_BIT_i_4_n_0;
wire OUT_BIT_i_5_n_0;
wire OUT_BIT_i_6_n_0;
wire OUT_BIT_i_7_n_0;
wire OUT_BIT_i_8_n_0;
wire OUT_BIT_i_9_n_0;
wire [9:0]TIMER;
wire \TIMER[4]_i_2_n_0 ;
wire \TIMER[9]_i_2_n_0 ;
wire \TIMER_reg_n_0_[0] ;
wire \TIMER_reg_n_0_[1] ;
wire \TIMER_reg_n_0_[2] ;
wire \TIMER_reg_n_0_[3] ;
wire \TIMER_reg_n_0_[4] ;
wire \TIMER_reg_n_0_[5] ;
wire \TIMER_reg_n_0_[6] ;
wire \TIMER_reg_n_0_[7] ;
wire \TIMER_reg_n_0_[8] ;
wire \TIMER_reg_n_0_[9] ;
wire p_0_in;
wire [2:0]NLW_OUT_BIT_reg_i_2_CO_UNCONNECTED;
wire [3:0]NLW_OUT_BIT_reg_i_2_O_UNCONNECTED;
LUT6 #(
.INIT(64'h2333333333333333))
\COUNT[0]_i_1__1
(.I0(\COUNT[7]_i_3_n_0 ),
.I1(\COUNT_reg_n_0_[0] ),
.I2(\COUNT_reg_n_0_[5] ),
.I3(\COUNT_reg_n_0_[4] ),
.I4(\COUNT_reg_n_0_[7] ),
.I5(\COUNT_reg_n_0_[6] ),
.O(\COUNT[0]_i_1__1_n_0 ));
LUT5 #(
.INIT(32'h00FFBF00))
\COUNT[1]_i_1__1
(.I0(\COUNT[1]_i_2_n_0 ),
.I1(\COUNT_reg_n_0_[3] ),
.I2(\COUNT_reg_n_0_[2] ),
.I3(\COUNT_reg_n_0_[1] ),
.I4(\COUNT_reg_n_0_[0] ),
.O(\COUNT[1]_i_1__1_n_0 ));
LUT4 #(
.INIT(16'h7FFF))
\COUNT[1]_i_2
(.I0(\COUNT_reg_n_0_[5] ),
.I1(\COUNT_reg_n_0_[4] ),
.I2(\COUNT_reg_n_0_[7] ),
.I3(\COUNT_reg_n_0_[6] ),
.O(\COUNT[1]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair36" *)
LUT5 #(
.INIT(32'hFFC011C0))
\COUNT[2]_i_1__0
(.I0(\COUNT_reg_n_0_[3] ),
.I1(\COUNT_reg_n_0_[0] ),
.I2(\COUNT_reg_n_0_[1] ),
.I3(\COUNT_reg_n_0_[2] ),
.I4(\COUNT[3]_i_2_n_0 ),
.O(\COUNT[2]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair36" *)
LUT5 #(
.INIT(32'hFF805580))
\COUNT[3]_i_1
(.I0(\COUNT_reg_n_0_[2] ),
.I1(\COUNT_reg_n_0_[1] ),
.I2(\COUNT_reg_n_0_[0] ),
.I3(\COUNT_reg_n_0_[3] ),
.I4(\COUNT[3]_i_2_n_0 ),
.O(\COUNT[3]_i_1_n_0 ));
LUT6 #(
.INIT(64'h15555555FFFFFFFF))
\COUNT[3]_i_2
(.I0(\COUNT_reg_n_0_[0] ),
.I1(\COUNT_reg_n_0_[5] ),
.I2(\COUNT_reg_n_0_[4] ),
.I3(\COUNT_reg_n_0_[7] ),
.I4(\COUNT_reg_n_0_[6] ),
.I5(\COUNT_reg_n_0_[1] ),
.O(\COUNT[3]_i_2_n_0 ));
LUT6 #(
.INIT(64'hFF00FF7F00FF0000))
\COUNT[4]_i_1
(.I0(\COUNT_reg_n_0_[7] ),
.I1(\COUNT_reg_n_0_[6] ),
.I2(\COUNT_reg_n_0_[5] ),
.I3(\COUNT[7]_i_3_n_0 ),
.I4(\COUNT_reg_n_0_[0] ),
.I5(\COUNT_reg_n_0_[4] ),
.O(\COUNT[4]_i_1_n_0 ));
LUT6 #(
.INIT(64'hAABFFFFF55000000))
\COUNT[5]_i_1
(.I0(\COUNT[7]_i_3_n_0 ),
.I1(\COUNT_reg_n_0_[7] ),
.I2(\COUNT_reg_n_0_[6] ),
.I3(\COUNT_reg_n_0_[0] ),
.I4(\COUNT_reg_n_0_[4] ),
.I5(\COUNT_reg_n_0_[5] ),
.O(\COUNT[5]_i_1_n_0 ));
LUT6 #(
.INIT(64'hF01CF0F0F0F0F0F0))
\COUNT[6]_i_1
(.I0(\COUNT_reg_n_0_[7] ),
.I1(\COUNT_reg_n_0_[0] ),
.I2(\COUNT_reg_n_0_[6] ),
.I3(\COUNT[7]_i_3_n_0 ),
.I4(\COUNT_reg_n_0_[5] ),
.I5(\COUNT_reg_n_0_[4] ),
.O(\COUNT[6]_i_1_n_0 ));
LUT6 #(
.INIT(64'h0000000000000001))
\COUNT[7]_i_1
(.I0(\TIMER_reg_n_0_[9] ),
.I1(\TIMER_reg_n_0_[7] ),
.I2(\TIMER_reg_n_0_[5] ),
.I3(\TIMER_reg_n_0_[6] ),
.I4(\TIMER_reg_n_0_[8] ),
.I5(\TIMER[9]_i_2_n_0 ),
.O(\COUNT[7]_i_1_n_0 ));
LUT6 #(
.INIT(64'hF7FFF7FF08000000))
\COUNT[7]_i_2
(.I0(\COUNT_reg_n_0_[4] ),
.I1(\COUNT_reg_n_0_[5] ),
.I2(\COUNT[7]_i_3_n_0 ),
.I3(\COUNT_reg_n_0_[6] ),
.I4(\COUNT_reg_n_0_[0] ),
.I5(\COUNT_reg_n_0_[7] ),
.O(\COUNT[7]_i_2_n_0 ));
LUT3 #(
.INIT(8'h7F))
\COUNT[7]_i_3
(.I0(\COUNT_reg_n_0_[3] ),
.I1(\COUNT_reg_n_0_[2] ),
.I2(\COUNT_reg_n_0_[1] ),
.O(\COUNT[7]_i_3_n_0 ));
FDRE #(
.INIT(1'b0))
\COUNT_reg[0]
(.C(ETH_CLK_OBUF),
.CE(\COUNT[7]_i_1_n_0 ),
.D(\COUNT[0]_i_1__1_n_0 ),
.Q(\COUNT_reg_n_0_[0] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\COUNT_reg[1]
(.C(ETH_CLK_OBUF),
.CE(\COUNT[7]_i_1_n_0 ),
.D(\COUNT[1]_i_1__1_n_0 ),
.Q(\COUNT_reg_n_0_[1] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\COUNT_reg[2]
(.C(ETH_CLK_OBUF),
.CE(\COUNT[7]_i_1_n_0 ),
.D(\COUNT[2]_i_1__0_n_0 ),
.Q(\COUNT_reg_n_0_[2] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\COUNT_reg[3]
(.C(ETH_CLK_OBUF),
.CE(\COUNT[7]_i_1_n_0 ),
.D(\COUNT[3]_i_1_n_0 ),
.Q(\COUNT_reg_n_0_[3] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\COUNT_reg[4]
(.C(ETH_CLK_OBUF),
.CE(\COUNT[7]_i_1_n_0 ),
.D(\COUNT[4]_i_1_n_0 ),
.Q(\COUNT_reg_n_0_[4] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\COUNT_reg[5]
(.C(ETH_CLK_OBUF),
.CE(\COUNT[7]_i_1_n_0 ),
.D(\COUNT[5]_i_1_n_0 ),
.Q(\COUNT_reg_n_0_[5] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\COUNT_reg[6]
(.C(ETH_CLK_OBUF),
.CE(\COUNT[7]_i_1_n_0 ),
.D(\COUNT[6]_i_1_n_0 ),
.Q(\COUNT_reg_n_0_[6] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\COUNT_reg[7]
(.C(ETH_CLK_OBUF),
.CE(\COUNT[7]_i_1_n_0 ),
.D(\COUNT[7]_i_2_n_0 ),
.Q(\COUNT_reg_n_0_[7] ),
.R(1'b0));
LUT1 #(
.INIT(2'h1))
OUT_BIT_i_1
(.I0(p_0_in),
.O(OUT_BIT_i_1_n_0));
LUT2 #(
.INIT(4'h1))
OUT_BIT_i_10
(.I0(\COUNT_reg_n_0_[0] ),
.I1(\COUNT_reg_n_0_[1] ),
.O(OUT_BIT_i_10_n_0));
LUT2 #(
.INIT(4'hE))
OUT_BIT_i_3
(.I0(\COUNT_reg_n_0_[6] ),
.I1(\COUNT_reg_n_0_[7] ),
.O(OUT_BIT_i_3_n_0));
LUT2 #(
.INIT(4'hE))
OUT_BIT_i_4
(.I0(\COUNT_reg_n_0_[4] ),
.I1(\COUNT_reg_n_0_[5] ),
.O(OUT_BIT_i_4_n_0));
LUT2 #(
.INIT(4'hE))
OUT_BIT_i_5
(.I0(\COUNT_reg_n_0_[2] ),
.I1(\COUNT_reg_n_0_[3] ),
.O(OUT_BIT_i_5_n_0));
LUT2 #(
.INIT(4'hE))
OUT_BIT_i_6
(.I0(\COUNT_reg_n_0_[0] ),
.I1(\COUNT_reg_n_0_[1] ),
.O(OUT_BIT_i_6_n_0));
LUT2 #(
.INIT(4'h1))
OUT_BIT_i_7
(.I0(\COUNT_reg_n_0_[6] ),
.I1(\COUNT_reg_n_0_[7] ),
.O(OUT_BIT_i_7_n_0));
LUT2 #(
.INIT(4'h1))
OUT_BIT_i_8
(.I0(\COUNT_reg_n_0_[4] ),
.I1(\COUNT_reg_n_0_[5] ),
.O(OUT_BIT_i_8_n_0));
LUT2 #(
.INIT(4'h1))
OUT_BIT_i_9
(.I0(\COUNT_reg_n_0_[2] ),
.I1(\COUNT_reg_n_0_[3] ),
.O(OUT_BIT_i_9_n_0));
FDRE OUT_BIT_reg
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(OUT_BIT_i_1_n_0),
.Q(LED_R_PWM_OBUF),
.R(1'b0));
CARRY4 OUT_BIT_reg_i_2
(.CI(1'b0),
.CO({p_0_in,NLW_OUT_BIT_reg_i_2_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b1),
.DI({OUT_BIT_i_3_n_0,OUT_BIT_i_4_n_0,OUT_BIT_i_5_n_0,OUT_BIT_i_6_n_0}),
.O(NLW_OUT_BIT_reg_i_2_O_UNCONNECTED[3:0]),
.S({OUT_BIT_i_7_n_0,OUT_BIT_i_8_n_0,OUT_BIT_i_9_n_0,OUT_BIT_i_10_n_0}));
(* SOFT_HLUTNM = "soft_lutpair37" *)
LUT1 #(
.INIT(2'h1))
\TIMER[0]_i_1__0
(.I0(\TIMER_reg_n_0_[0] ),
.O(TIMER[0]));
(* SOFT_HLUTNM = "soft_lutpair37" *)
LUT2 #(
.INIT(4'h9))
\TIMER[1]_i_1
(.I0(\TIMER_reg_n_0_[1] ),
.I1(\TIMER_reg_n_0_[0] ),
.O(TIMER[1]));
LUT3 #(
.INIT(8'hA9))
\TIMER[2]_i_1__0
(.I0(\TIMER_reg_n_0_[2] ),
.I1(\TIMER_reg_n_0_[0] ),
.I2(\TIMER_reg_n_0_[1] ),
.O(TIMER[2]));
LUT6 #(
.INIT(64'hF0F0F0F0F0F0F00E))
\TIMER[3]_i_1
(.I0(\TIMER[4]_i_2_n_0 ),
.I1(\TIMER_reg_n_0_[4] ),
.I2(\TIMER_reg_n_0_[3] ),
.I3(\TIMER_reg_n_0_[1] ),
.I4(\TIMER_reg_n_0_[0] ),
.I5(\TIMER_reg_n_0_[2] ),
.O(TIMER[3]));
LUT6 #(
.INIT(64'hFFFE0001FFFE0000))
\TIMER[4]_i_1
(.I0(\TIMER_reg_n_0_[3] ),
.I1(\TIMER_reg_n_0_[1] ),
.I2(\TIMER_reg_n_0_[0] ),
.I3(\TIMER_reg_n_0_[2] ),
.I4(\TIMER_reg_n_0_[4] ),
.I5(\TIMER[4]_i_2_n_0 ),
.O(TIMER[4]));
LUT5 #(
.INIT(32'hFFFFFFFE))
\TIMER[4]_i_2
(.I0(\TIMER_reg_n_0_[8] ),
.I1(\TIMER_reg_n_0_[6] ),
.I2(\TIMER_reg_n_0_[5] ),
.I3(\TIMER_reg_n_0_[7] ),
.I4(\TIMER_reg_n_0_[9] ),
.O(\TIMER[4]_i_2_n_0 ));
LUT6 #(
.INIT(64'hAAAAAAAAAAAAAAA9))
\TIMER[5]_i_1
(.I0(\TIMER_reg_n_0_[5] ),
.I1(\TIMER_reg_n_0_[3] ),
.I2(\TIMER_reg_n_0_[1] ),
.I3(\TIMER_reg_n_0_[0] ),
.I4(\TIMER_reg_n_0_[2] ),
.I5(\TIMER_reg_n_0_[4] ),
.O(TIMER[5]));
LUT3 #(
.INIT(8'hE1))
\TIMER[6]_i_1__0
(.I0(\TIMER[9]_i_2_n_0 ),
.I1(\TIMER_reg_n_0_[5] ),
.I2(\TIMER_reg_n_0_[6] ),
.O(TIMER[6]));
(* SOFT_HLUTNM = "soft_lutpair34" *)
LUT4 #(
.INIT(16'hFE01))
\TIMER[7]_i_1__0
(.I0(\TIMER[9]_i_2_n_0 ),
.I1(\TIMER_reg_n_0_[6] ),
.I2(\TIMER_reg_n_0_[5] ),
.I3(\TIMER_reg_n_0_[7] ),
.O(TIMER[7]));
(* SOFT_HLUTNM = "soft_lutpair34" *)
LUT5 #(
.INIT(32'hFFFE0001))
\TIMER[8]_i_1__0
(.I0(\TIMER[9]_i_2_n_0 ),
.I1(\TIMER_reg_n_0_[7] ),
.I2(\TIMER_reg_n_0_[5] ),
.I3(\TIMER_reg_n_0_[6] ),
.I4(\TIMER_reg_n_0_[8] ),
.O(TIMER[8]));
LUT6 #(
.INIT(64'hFFFFFFFE00000001))
\TIMER[9]_i_1
(.I0(\TIMER[9]_i_2_n_0 ),
.I1(\TIMER_reg_n_0_[8] ),
.I2(\TIMER_reg_n_0_[6] ),
.I3(\TIMER_reg_n_0_[5] ),
.I4(\TIMER_reg_n_0_[7] ),
.I5(\TIMER_reg_n_0_[9] ),
.O(TIMER[9]));
LUT5 #(
.INIT(32'hFFFFFFFE))
\TIMER[9]_i_2
(.I0(\TIMER_reg_n_0_[3] ),
.I1(\TIMER_reg_n_0_[1] ),
.I2(\TIMER_reg_n_0_[0] ),
.I3(\TIMER_reg_n_0_[2] ),
.I4(\TIMER_reg_n_0_[4] ),
.O(\TIMER[9]_i_2_n_0 ));
FDRE #(
.INIT(1'b1))
\TIMER_reg[0]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(TIMER[0]),
.Q(\TIMER_reg_n_0_[0] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\TIMER_reg[1]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(TIMER[1]),
.Q(\TIMER_reg_n_0_[1] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\TIMER_reg[2]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(TIMER[2]),
.Q(\TIMER_reg_n_0_[2] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\TIMER_reg[3]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(TIMER[3]),
.Q(\TIMER_reg_n_0_[3] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\TIMER_reg[4]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(TIMER[4]),
.Q(\TIMER_reg_n_0_[4] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\TIMER_reg[5]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(TIMER[5]),
.Q(\TIMER_reg_n_0_[5] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\TIMER_reg[6]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(TIMER[6]),
.Q(\TIMER_reg_n_0_[6] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\TIMER_reg[7]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(TIMER[7]),
.Q(\TIMER_reg_n_0_[7] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\TIMER_reg[8]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(TIMER[8]),
.Q(\TIMER_reg_n_0_[8] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\TIMER_reg[9]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(TIMER[9]),
.Q(\TIMER_reg_n_0_[9] ),
.R(1'b0));
endmodule
|
module PWM_0
(LED_G_PWM_OBUF,
ETH_CLK_OBUF);
output LED_G_PWM_OBUF;
input ETH_CLK_OBUF;
wire \COUNT[0]_i_1__2_n_0 ;
wire \COUNT[1]_i_1__2_n_0 ;
wire \COUNT[1]_i_2__0_n_0 ;
wire \COUNT[2]_i_1__1_n_0 ;
wire \COUNT[3]_i_1__0_n_0 ;
wire \COUNT[3]_i_2__0_n_0 ;
wire \COUNT[4]_i_1__0_n_0 ;
wire \COUNT[5]_i_1__0_n_0 ;
wire \COUNT[6]_i_1__0_n_0 ;
wire \COUNT[7]_i_1__0_n_0 ;
wire \COUNT[7]_i_2__0_n_0 ;
wire \COUNT[7]_i_3__0_n_0 ;
wire \COUNT_reg_n_0_[0] ;
wire \COUNT_reg_n_0_[1] ;
wire \COUNT_reg_n_0_[2] ;
wire \COUNT_reg_n_0_[3] ;
wire \COUNT_reg_n_0_[4] ;
wire \COUNT_reg_n_0_[5] ;
wire \COUNT_reg_n_0_[6] ;
wire \COUNT_reg_n_0_[7] ;
wire ETH_CLK_OBUF;
wire LED_G_PWM_OBUF;
wire OUT_BIT_i_10__0_n_0;
wire OUT_BIT_i_1__0_n_0;
wire OUT_BIT_i_3__0_n_0;
wire OUT_BIT_i_4__0_n_0;
wire OUT_BIT_i_5__0_n_0;
wire OUT_BIT_i_6__0_n_0;
wire OUT_BIT_i_7__0_n_0;
wire OUT_BIT_i_8__0_n_0;
wire OUT_BIT_i_9__0_n_0;
wire [9:0]TIMER;
wire \TIMER[4]_i_2__0_n_0 ;
wire \TIMER[9]_i_2__0_n_0 ;
wire \TIMER_reg_n_0_[0] ;
wire \TIMER_reg_n_0_[1] ;
wire \TIMER_reg_n_0_[2] ;
wire \TIMER_reg_n_0_[3] ;
wire \TIMER_reg_n_0_[4] ;
wire \TIMER_reg_n_0_[5] ;
wire \TIMER_reg_n_0_[6] ;
wire \TIMER_reg_n_0_[7] ;
wire \TIMER_reg_n_0_[8] ;
wire \TIMER_reg_n_0_[9] ;
wire p_0_in;
wire [2:0]NLW_OUT_BIT_reg_i_2__0_CO_UNCONNECTED;
wire [3:0]NLW_OUT_BIT_reg_i_2__0_O_UNCONNECTED;
LUT6 #(
.INIT(64'h2333333333333333))
\COUNT[0]_i_1__2
(.I0(\COUNT[7]_i_3__0_n_0 ),
.I1(\COUNT_reg_n_0_[0] ),
.I2(\COUNT_reg_n_0_[5] ),
.I3(\COUNT_reg_n_0_[4] ),
.I4(\COUNT_reg_n_0_[7] ),
.I5(\COUNT_reg_n_0_[6] ),
.O(\COUNT[0]_i_1__2_n_0 ));
LUT5 #(
.INIT(32'h00FFBF00))
\COUNT[1]_i_1__2
(.I0(\COUNT[1]_i_2__0_n_0 ),
.I1(\COUNT_reg_n_0_[3] ),
.I2(\COUNT_reg_n_0_[2] ),
.I3(\COUNT_reg_n_0_[1] ),
.I4(\COUNT_reg_n_0_[0] ),
.O(\COUNT[1]_i_1__2_n_0 ));
LUT4 #(
.INIT(16'h7FFF))
\COUNT[1]_i_2__0
(.I0(\COUNT_reg_n_0_[5] ),
.I1(\COUNT_reg_n_0_[4] ),
.I2(\COUNT_reg_n_0_[7] ),
.I3(\COUNT_reg_n_0_[6] ),
.O(\COUNT[1]_i_2__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair41" *)
LUT5 #(
.INIT(32'hFFC011C0))
\COUNT[2]_i_1__1
(.I0(\COUNT_reg_n_0_[3] ),
.I1(\COUNT_reg_n_0_[0] ),
.I2(\COUNT_reg_n_0_[1] ),
.I3(\COUNT_reg_n_0_[2] ),
.I4(\COUNT[3]_i_2__0_n_0 ),
.O(\COUNT[2]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair41" *)
LUT5 #(
.INIT(32'hFF805580))
\COUNT[3]_i_1__0
(.I0(\COUNT_reg_n_0_[2] ),
.I1(\COUNT_reg_n_0_[1] ),
.I2(\COUNT_reg_n_0_[0] ),
.I3(\COUNT_reg_n_0_[3] ),
.I4(\COUNT[3]_i_2__0_n_0 ),
.O(\COUNT[3]_i_1__0_n_0 ));
LUT6 #(
.INIT(64'h15555555FFFFFFFF))
\COUNT[3]_i_2__0
(.I0(\COUNT_reg_n_0_[0] ),
.I1(\COUNT_reg_n_0_[5] ),
.I2(\COUNT_reg_n_0_[4] ),
.I3(\COUNT_reg_n_0_[7] ),
.I4(\COUNT_reg_n_0_[6] ),
.I5(\COUNT_reg_n_0_[1] ),
.O(\COUNT[3]_i_2__0_n_0 ));
LUT6 #(
.INIT(64'hFF00FF7F00FF0000))
\COUNT[4]_i_1__0
(.I0(\COUNT_reg_n_0_[7] ),
.I1(\COUNT_reg_n_0_[6] ),
.I2(\COUNT_reg_n_0_[5] ),
.I3(\COUNT[7]_i_3__0_n_0 ),
.I4(\COUNT_reg_n_0_[0] ),
.I5(\COUNT_reg_n_0_[4] ),
.O(\COUNT[4]_i_1__0_n_0 ));
LUT6 #(
.INIT(64'hAABFFFFF55000000))
\COUNT[5]_i_1__0
(.I0(\COUNT[7]_i_3__0_n_0 ),
.I1(\COUNT_reg_n_0_[7] ),
.I2(\COUNT_reg_n_0_[6] ),
.I3(\COUNT_reg_n_0_[0] ),
.I4(\COUNT_reg_n_0_[4] ),
.I5(\COUNT_reg_n_0_[5] ),
.O(\COUNT[5]_i_1__0_n_0 ));
LUT6 #(
.INIT(64'hF01CF0F0F0F0F0F0))
\COUNT[6]_i_1__0
(.I0(\COUNT_reg_n_0_[7] ),
.I1(\COUNT_reg_n_0_[0] ),
.I2(\COUNT_reg_n_0_[6] ),
.I3(\COUNT[7]_i_3__0_n_0 ),
.I4(\COUNT_reg_n_0_[5] ),
.I5(\COUNT_reg_n_0_[4] ),
.O(\COUNT[6]_i_1__0_n_0 ));
LUT6 #(
.INIT(64'h0000000000000001))
\COUNT[7]_i_1__0
(.I0(\TIMER_reg_n_0_[9] ),
.I1(\TIMER_reg_n_0_[7] ),
.I2(\TIMER_reg_n_0_[5] ),
.I3(\TIMER_reg_n_0_[6] ),
.I4(\TIMER_reg_n_0_[8] ),
.I5(\TIMER[9]_i_2__0_n_0 ),
.O(\COUNT[7]_i_1__0_n_0 ));
LUT6 #(
.INIT(64'hF7FFF7FF08000000))
\COUNT[7]_i_2__0
(.I0(\COUNT_reg_n_0_[4] ),
.I1(\COUNT_reg_n_0_[5] ),
.I2(\COUNT[7]_i_3__0_n_0 ),
.I3(\COUNT_reg_n_0_[6] ),
.I4(\COUNT_reg_n_0_[0] ),
.I5(\COUNT_reg_n_0_[7] ),
.O(\COUNT[7]_i_2__0_n_0 ));
LUT3 #(
.INIT(8'h7F))
\COUNT[7]_i_3__0
(.I0(\COUNT_reg_n_0_[3] ),
.I1(\COUNT_reg_n_0_[2] ),
.I2(\COUNT_reg_n_0_[1] ),
.O(\COUNT[7]_i_3__0_n_0 ));
FDRE #(
.INIT(1'b0))
\COUNT_reg[0]
(.C(ETH_CLK_OBUF),
.CE(\COUNT[7]_i_1__0_n_0 ),
.D(\COUNT[0]_i_1__2_n_0 ),
.Q(\COUNT_reg_n_0_[0] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\COUNT_reg[1]
(.C(ETH_CLK_OBUF),
.CE(\COUNT[7]_i_1__0_n_0 ),
.D(\COUNT[1]_i_1__2_n_0 ),
.Q(\COUNT_reg_n_0_[1] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\COUNT_reg[2]
(.C(ETH_CLK_OBUF),
.CE(\COUNT[7]_i_1__0_n_0 ),
.D(\COUNT[2]_i_1__1_n_0 ),
.Q(\COUNT_reg_n_0_[2] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\COUNT_reg[3]
(.C(ETH_CLK_OBUF),
.CE(\COUNT[7]_i_1__0_n_0 ),
.D(\COUNT[3]_i_1__0_n_0 ),
.Q(\COUNT_reg_n_0_[3] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\COUNT_reg[4]
(.C(ETH_CLK_OBUF),
.CE(\COUNT[7]_i_1__0_n_0 ),
.D(\COUNT[4]_i_1__0_n_0 ),
.Q(\COUNT_reg_n_0_[4] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\COUNT_reg[5]
(.C(ETH_CLK_OBUF),
.CE(\COUNT[7]_i_1__0_n_0 ),
.D(\COUNT[5]_i_1__0_n_0 ),
.Q(\COUNT_reg_n_0_[5] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\COUNT_reg[6]
(.C(ETH_CLK_OBUF),
.CE(\COUNT[7]_i_1__0_n_0 ),
.D(\COUNT[6]_i_1__0_n_0 ),
.Q(\COUNT_reg_n_0_[6] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\COUNT_reg[7]
(.C(ETH_CLK_OBUF),
.CE(\COUNT[7]_i_1__0_n_0 ),
.D(\COUNT[7]_i_2__0_n_0 ),
.Q(\COUNT_reg_n_0_[7] ),
.R(1'b0));
LUT2 #(
.INIT(4'h1))
OUT_BIT_i_10__0
(.I0(\COUNT_reg_n_0_[0] ),
.I1(\COUNT_reg_n_0_[1] ),
.O(OUT_BIT_i_10__0_n_0));
LUT1 #(
.INIT(2'h1))
OUT_BIT_i_1__0
(.I0(p_0_in),
.O(OUT_BIT_i_1__0_n_0));
LUT2 #(
.INIT(4'hE))
OUT_BIT_i_3__0
(.I0(\COUNT_reg_n_0_[6] ),
.I1(\COUNT_reg_n_0_[7] ),
.O(OUT_BIT_i_3__0_n_0));
LUT2 #(
.INIT(4'hE))
OUT_BIT_i_4__0
(.I0(\COUNT_reg_n_0_[4] ),
.I1(\COUNT_reg_n_0_[5] ),
.O(OUT_BIT_i_4__0_n_0));
LUT2 #(
.INIT(4'hE))
OUT_BIT_i_5__0
(.I0(\COUNT_reg_n_0_[2] ),
.I1(\COUNT_reg_n_0_[3] ),
.O(OUT_BIT_i_5__0_n_0));
LUT2 #(
.INIT(4'hE))
OUT_BIT_i_6__0
(.I0(\COUNT_reg_n_0_[0] ),
.I1(\COUNT_reg_n_0_[1] ),
.O(OUT_BIT_i_6__0_n_0));
LUT2 #(
.INIT(4'h1))
OUT_BIT_i_7__0
(.I0(\COUNT_reg_n_0_[6] ),
.I1(\COUNT_reg_n_0_[7] ),
.O(OUT_BIT_i_7__0_n_0));
LUT2 #(
.INIT(4'h1))
OUT_BIT_i_8__0
(.I0(\COUNT_reg_n_0_[4] ),
.I1(\COUNT_reg_n_0_[5] ),
.O(OUT_BIT_i_8__0_n_0));
LUT2 #(
.INIT(4'h1))
OUT_BIT_i_9__0
(.I0(\COUNT_reg_n_0_[2] ),
.I1(\COUNT_reg_n_0_[3] ),
.O(OUT_BIT_i_9__0_n_0));
FDRE OUT_BIT_reg
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(OUT_BIT_i_1__0_n_0),
.Q(LED_G_PWM_OBUF),
.R(1'b0));
CARRY4 OUT_BIT_reg_i_2__0
(.CI(1'b0),
.CO({p_0_in,NLW_OUT_BIT_reg_i_2__0_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b1),
.DI({OUT_BIT_i_3__0_n_0,OUT_BIT_i_4__0_n_0,OUT_BIT_i_5__0_n_0,OUT_BIT_i_6__0_n_0}),
.O(NLW_OUT_BIT_reg_i_2__0_O_UNCONNECTED[3:0]),
.S({OUT_BIT_i_7__0_n_0,OUT_BIT_i_8__0_n_0,OUT_BIT_i_9__0_n_0,OUT_BIT_i_10__0_n_0}));
(* SOFT_HLUTNM = "soft_lutpair42" *)
LUT1 #(
.INIT(2'h1))
\TIMER[0]_i_1__1
(.I0(\TIMER_reg_n_0_[0] ),
.O(TIMER[0]));
(* SOFT_HLUTNM = "soft_lutpair42" *)
LUT2 #(
.INIT(4'h9))
\TIMER[1]_i_1__0
(.I0(\TIMER_reg_n_0_[1] ),
.I1(\TIMER_reg_n_0_[0] ),
.O(TIMER[1]));
LUT3 #(
.INIT(8'hA9))
\TIMER[2]_i_1__1
(.I0(\TIMER_reg_n_0_[2] ),
.I1(\TIMER_reg_n_0_[0] ),
.I2(\TIMER_reg_n_0_[1] ),
.O(TIMER[2]));
LUT6 #(
.INIT(64'hF0F0F0F0F0F0F00E))
\TIMER[3]_i_1__0
(.I0(\TIMER[4]_i_2__0_n_0 ),
.I1(\TIMER_reg_n_0_[4] ),
.I2(\TIMER_reg_n_0_[3] ),
.I3(\TIMER_reg_n_0_[1] ),
.I4(\TIMER_reg_n_0_[0] ),
.I5(\TIMER_reg_n_0_[2] ),
.O(TIMER[3]));
LUT6 #(
.INIT(64'hFFFE0001FFFE0000))
\TIMER[4]_i_1__0
(.I0(\TIMER_reg_n_0_[3] ),
.I1(\TIMER_reg_n_0_[1] ),
.I2(\TIMER_reg_n_0_[0] ),
.I3(\TIMER_reg_n_0_[2] ),
.I4(\TIMER_reg_n_0_[4] ),
.I5(\TIMER[4]_i_2__0_n_0 ),
.O(TIMER[4]));
LUT5 #(
.INIT(32'hFFFFFFFE))
\TIMER[4]_i_2__0
(.I0(\TIMER_reg_n_0_[8] ),
.I1(\TIMER_reg_n_0_[6] ),
.I2(\TIMER_reg_n_0_[5] ),
.I3(\TIMER_reg_n_0_[7] ),
.I4(\TIMER_reg_n_0_[9] ),
.O(\TIMER[4]_i_2__0_n_0 ));
LUT6 #(
.INIT(64'hAAAAAAAAAAAAAAA9))
\TIMER[5]_i_1__0
(.I0(\TIMER_reg_n_0_[5] ),
.I1(\TIMER_reg_n_0_[3] ),
.I2(\TIMER_reg_n_0_[1] ),
.I3(\TIMER_reg_n_0_[0] ),
.I4(\TIMER_reg_n_0_[2] ),
.I5(\TIMER_reg_n_0_[4] ),
.O(TIMER[5]));
LUT3 #(
.INIT(8'hE1))
\TIMER[6]_i_1__1
(.I0(\TIMER[9]_i_2__0_n_0 ),
.I1(\TIMER_reg_n_0_[5] ),
.I2(\TIMER_reg_n_0_[6] ),
.O(TIMER[6]));
(* SOFT_HLUTNM = "soft_lutpair39" *)
LUT4 #(
.INIT(16'hFE01))
\TIMER[7]_i_1__1
(.I0(\TIMER[9]_i_2__0_n_0 ),
.I1(\TIMER_reg_n_0_[6] ),
.I2(\TIMER_reg_n_0_[5] ),
.I3(\TIMER_reg_n_0_[7] ),
.O(TIMER[7]));
(* SOFT_HLUTNM = "soft_lutpair39" *)
LUT5 #(
.INIT(32'hFFFE0001))
\TIMER[8]_i_1__1
(.I0(\TIMER[9]_i_2__0_n_0 ),
.I1(\TIMER_reg_n_0_[7] ),
.I2(\TIMER_reg_n_0_[5] ),
.I3(\TIMER_reg_n_0_[6] ),
.I4(\TIMER_reg_n_0_[8] ),
.O(TIMER[8]));
LUT6 #(
.INIT(64'hFFFFFFFE00000001))
\TIMER[9]_i_1__0
(.I0(\TIMER[9]_i_2__0_n_0 ),
.I1(\TIMER_reg_n_0_[8] ),
.I2(\TIMER_reg_n_0_[6] ),
.I3(\TIMER_reg_n_0_[5] ),
.I4(\TIMER_reg_n_0_[7] ),
.I5(\TIMER_reg_n_0_[9] ),
.O(TIMER[9]));
LUT5 #(
.INIT(32'hFFFFFFFE))
\TIMER[9]_i_2__0
(.I0(\TIMER_reg_n_0_[3] ),
.I1(\TIMER_reg_n_0_[1] ),
.I2(\TIMER_reg_n_0_[0] ),
.I3(\TIMER_reg_n_0_[2] ),
.I4(\TIMER_reg_n_0_[4] ),
.O(\TIMER[9]_i_2__0_n_0 ));
FDRE #(
.INIT(1'b1))
\TIMER_reg[0]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(TIMER[0]),
.Q(\TIMER_reg_n_0_[0] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\TIMER_reg[1]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(TIMER[1]),
.Q(\TIMER_reg_n_0_[1] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\TIMER_reg[2]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(TIMER[2]),
.Q(\TIMER_reg_n_0_[2] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\TIMER_reg[3]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(TIMER[3]),
.Q(\TIMER_reg_n_0_[3] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\TIMER_reg[4]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(TIMER[4]),
.Q(\TIMER_reg_n_0_[4] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\TIMER_reg[5]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(TIMER[5]),
.Q(\TIMER_reg_n_0_[5] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\TIMER_reg[6]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(TIMER[6]),
.Q(\TIMER_reg_n_0_[6] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\TIMER_reg[7]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(TIMER[7]),
.Q(\TIMER_reg_n_0_[7] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\TIMER_reg[8]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(TIMER[8]),
.Q(\TIMER_reg_n_0_[8] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\TIMER_reg[9]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(TIMER[9]),
.Q(\TIMER_reg_n_0_[9] ),
.R(1'b0));
endmodule
|
module PWM_1
(LED_B_PWM_OBUF,
ETH_CLK_OBUF);
output LED_B_PWM_OBUF;
input ETH_CLK_OBUF;
wire \COUNT[0]_i_1__3_n_0 ;
wire \COUNT[1]_i_1__3_n_0 ;
wire \COUNT[1]_i_2__1_n_0 ;
wire \COUNT[2]_i_1__2_n_0 ;
wire \COUNT[3]_i_1__1_n_0 ;
wire \COUNT[3]_i_2__1_n_0 ;
wire \COUNT[4]_i_1__1_n_0 ;
wire \COUNT[5]_i_1__1_n_0 ;
wire \COUNT[6]_i_1__1_n_0 ;
wire \COUNT[7]_i_1__1_n_0 ;
wire \COUNT[7]_i_2__1_n_0 ;
wire \COUNT[7]_i_3__1_n_0 ;
wire \COUNT_reg_n_0_[0] ;
wire \COUNT_reg_n_0_[1] ;
wire \COUNT_reg_n_0_[2] ;
wire \COUNT_reg_n_0_[3] ;
wire \COUNT_reg_n_0_[4] ;
wire \COUNT_reg_n_0_[5] ;
wire \COUNT_reg_n_0_[6] ;
wire \COUNT_reg_n_0_[7] ;
wire ETH_CLK_OBUF;
wire LED_B_PWM_OBUF;
wire OUT_BIT_i_10__1_n_0;
wire OUT_BIT_i_1__1_n_0;
wire OUT_BIT_i_3__1_n_0;
wire OUT_BIT_i_4__1_n_0;
wire OUT_BIT_i_5__1_n_0;
wire OUT_BIT_i_6__1_n_0;
wire OUT_BIT_i_7__1_n_0;
wire OUT_BIT_i_8__1_n_0;
wire OUT_BIT_i_9__1_n_0;
wire [9:0]TIMER;
wire \TIMER[4]_i_2__1_n_0 ;
wire \TIMER[9]_i_2__1_n_0 ;
wire \TIMER_reg_n_0_[0] ;
wire \TIMER_reg_n_0_[1] ;
wire \TIMER_reg_n_0_[2] ;
wire \TIMER_reg_n_0_[3] ;
wire \TIMER_reg_n_0_[4] ;
wire \TIMER_reg_n_0_[5] ;
wire \TIMER_reg_n_0_[6] ;
wire \TIMER_reg_n_0_[7] ;
wire \TIMER_reg_n_0_[8] ;
wire \TIMER_reg_n_0_[9] ;
wire p_0_in;
wire [2:0]NLW_OUT_BIT_reg_i_2__1_CO_UNCONNECTED;
wire [3:0]NLW_OUT_BIT_reg_i_2__1_O_UNCONNECTED;
LUT6 #(
.INIT(64'h2333333333333333))
\COUNT[0]_i_1__3
(.I0(\COUNT[7]_i_3__1_n_0 ),
.I1(\COUNT_reg_n_0_[0] ),
.I2(\COUNT_reg_n_0_[5] ),
.I3(\COUNT_reg_n_0_[4] ),
.I4(\COUNT_reg_n_0_[7] ),
.I5(\COUNT_reg_n_0_[6] ),
.O(\COUNT[0]_i_1__3_n_0 ));
LUT5 #(
.INIT(32'h00FFBF00))
\COUNT[1]_i_1__3
(.I0(\COUNT[1]_i_2__1_n_0 ),
.I1(\COUNT_reg_n_0_[3] ),
.I2(\COUNT_reg_n_0_[2] ),
.I3(\COUNT_reg_n_0_[1] ),
.I4(\COUNT_reg_n_0_[0] ),
.O(\COUNT[1]_i_1__3_n_0 ));
LUT4 #(
.INIT(16'h7FFF))
\COUNT[1]_i_2__1
(.I0(\COUNT_reg_n_0_[5] ),
.I1(\COUNT_reg_n_0_[4] ),
.I2(\COUNT_reg_n_0_[7] ),
.I3(\COUNT_reg_n_0_[6] ),
.O(\COUNT[1]_i_2__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair46" *)
LUT5 #(
.INIT(32'hFFC011C0))
\COUNT[2]_i_1__2
(.I0(\COUNT_reg_n_0_[3] ),
.I1(\COUNT_reg_n_0_[0] ),
.I2(\COUNT_reg_n_0_[1] ),
.I3(\COUNT_reg_n_0_[2] ),
.I4(\COUNT[3]_i_2__1_n_0 ),
.O(\COUNT[2]_i_1__2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair46" *)
LUT5 #(
.INIT(32'hFF805580))
\COUNT[3]_i_1__1
(.I0(\COUNT_reg_n_0_[2] ),
.I1(\COUNT_reg_n_0_[1] ),
.I2(\COUNT_reg_n_0_[0] ),
.I3(\COUNT_reg_n_0_[3] ),
.I4(\COUNT[3]_i_2__1_n_0 ),
.O(\COUNT[3]_i_1__1_n_0 ));
LUT6 #(
.INIT(64'h15555555FFFFFFFF))
\COUNT[3]_i_2__1
(.I0(\COUNT_reg_n_0_[0] ),
.I1(\COUNT_reg_n_0_[5] ),
.I2(\COUNT_reg_n_0_[4] ),
.I3(\COUNT_reg_n_0_[7] ),
.I4(\COUNT_reg_n_0_[6] ),
.I5(\COUNT_reg_n_0_[1] ),
.O(\COUNT[3]_i_2__1_n_0 ));
LUT6 #(
.INIT(64'hFF00FF7F00FF0000))
\COUNT[4]_i_1__1
(.I0(\COUNT_reg_n_0_[7] ),
.I1(\COUNT_reg_n_0_[6] ),
.I2(\COUNT_reg_n_0_[5] ),
.I3(\COUNT[7]_i_3__1_n_0 ),
.I4(\COUNT_reg_n_0_[0] ),
.I5(\COUNT_reg_n_0_[4] ),
.O(\COUNT[4]_i_1__1_n_0 ));
LUT6 #(
.INIT(64'hAABFFFFF55000000))
\COUNT[5]_i_1__1
(.I0(\COUNT[7]_i_3__1_n_0 ),
.I1(\COUNT_reg_n_0_[7] ),
.I2(\COUNT_reg_n_0_[6] ),
.I3(\COUNT_reg_n_0_[0] ),
.I4(\COUNT_reg_n_0_[4] ),
.I5(\COUNT_reg_n_0_[5] ),
.O(\COUNT[5]_i_1__1_n_0 ));
LUT6 #(
.INIT(64'hF01CF0F0F0F0F0F0))
\COUNT[6]_i_1__1
(.I0(\COUNT_reg_n_0_[7] ),
.I1(\COUNT_reg_n_0_[0] ),
.I2(\COUNT_reg_n_0_[6] ),
.I3(\COUNT[7]_i_3__1_n_0 ),
.I4(\COUNT_reg_n_0_[5] ),
.I5(\COUNT_reg_n_0_[4] ),
.O(\COUNT[6]_i_1__1_n_0 ));
LUT6 #(
.INIT(64'h0000000000000001))
\COUNT[7]_i_1__1
(.I0(\TIMER_reg_n_0_[9] ),
.I1(\TIMER_reg_n_0_[7] ),
.I2(\TIMER_reg_n_0_[5] ),
.I3(\TIMER_reg_n_0_[6] ),
.I4(\TIMER_reg_n_0_[8] ),
.I5(\TIMER[9]_i_2__1_n_0 ),
.O(\COUNT[7]_i_1__1_n_0 ));
LUT6 #(
.INIT(64'hF7FFF7FF08000000))
\COUNT[7]_i_2__1
(.I0(\COUNT_reg_n_0_[4] ),
.I1(\COUNT_reg_n_0_[5] ),
.I2(\COUNT[7]_i_3__1_n_0 ),
.I3(\COUNT_reg_n_0_[6] ),
.I4(\COUNT_reg_n_0_[0] ),
.I5(\COUNT_reg_n_0_[7] ),
.O(\COUNT[7]_i_2__1_n_0 ));
LUT3 #(
.INIT(8'h7F))
\COUNT[7]_i_3__1
(.I0(\COUNT_reg_n_0_[3] ),
.I1(\COUNT_reg_n_0_[2] ),
.I2(\COUNT_reg_n_0_[1] ),
.O(\COUNT[7]_i_3__1_n_0 ));
FDRE #(
.INIT(1'b0))
\COUNT_reg[0]
(.C(ETH_CLK_OBUF),
.CE(\COUNT[7]_i_1__1_n_0 ),
.D(\COUNT[0]_i_1__3_n_0 ),
.Q(\COUNT_reg_n_0_[0] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\COUNT_reg[1]
(.C(ETH_CLK_OBUF),
.CE(\COUNT[7]_i_1__1_n_0 ),
.D(\COUNT[1]_i_1__3_n_0 ),
.Q(\COUNT_reg_n_0_[1] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\COUNT_reg[2]
(.C(ETH_CLK_OBUF),
.CE(\COUNT[7]_i_1__1_n_0 ),
.D(\COUNT[2]_i_1__2_n_0 ),
.Q(\COUNT_reg_n_0_[2] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\COUNT_reg[3]
(.C(ETH_CLK_OBUF),
.CE(\COUNT[7]_i_1__1_n_0 ),
.D(\COUNT[3]_i_1__1_n_0 ),
.Q(\COUNT_reg_n_0_[3] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\COUNT_reg[4]
(.C(ETH_CLK_OBUF),
.CE(\COUNT[7]_i_1__1_n_0 ),
.D(\COUNT[4]_i_1__1_n_0 ),
.Q(\COUNT_reg_n_0_[4] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\COUNT_reg[5]
(.C(ETH_CLK_OBUF),
.CE(\COUNT[7]_i_1__1_n_0 ),
.D(\COUNT[5]_i_1__1_n_0 ),
.Q(\COUNT_reg_n_0_[5] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\COUNT_reg[6]
(.C(ETH_CLK_OBUF),
.CE(\COUNT[7]_i_1__1_n_0 ),
.D(\COUNT[6]_i_1__1_n_0 ),
.Q(\COUNT_reg_n_0_[6] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\COUNT_reg[7]
(.C(ETH_CLK_OBUF),
.CE(\COUNT[7]_i_1__1_n_0 ),
.D(\COUNT[7]_i_2__1_n_0 ),
.Q(\COUNT_reg_n_0_[7] ),
.R(1'b0));
LUT2 #(
.INIT(4'h1))
OUT_BIT_i_10__1
(.I0(\COUNT_reg_n_0_[0] ),
.I1(\COUNT_reg_n_0_[1] ),
.O(OUT_BIT_i_10__1_n_0));
LUT1 #(
.INIT(2'h1))
OUT_BIT_i_1__1
(.I0(p_0_in),
.O(OUT_BIT_i_1__1_n_0));
LUT2 #(
.INIT(4'hE))
OUT_BIT_i_3__1
(.I0(\COUNT_reg_n_0_[6] ),
.I1(\COUNT_reg_n_0_[7] ),
.O(OUT_BIT_i_3__1_n_0));
LUT2 #(
.INIT(4'hE))
OUT_BIT_i_4__1
(.I0(\COUNT_reg_n_0_[4] ),
.I1(\COUNT_reg_n_0_[5] ),
.O(OUT_BIT_i_4__1_n_0));
LUT2 #(
.INIT(4'hE))
OUT_BIT_i_5__1
(.I0(\COUNT_reg_n_0_[2] ),
.I1(\COUNT_reg_n_0_[3] ),
.O(OUT_BIT_i_5__1_n_0));
LUT2 #(
.INIT(4'hE))
OUT_BIT_i_6__1
(.I0(\COUNT_reg_n_0_[0] ),
.I1(\COUNT_reg_n_0_[1] ),
.O(OUT_BIT_i_6__1_n_0));
LUT2 #(
.INIT(4'h1))
OUT_BIT_i_7__1
(.I0(\COUNT_reg_n_0_[6] ),
.I1(\COUNT_reg_n_0_[7] ),
.O(OUT_BIT_i_7__1_n_0));
LUT2 #(
.INIT(4'h1))
OUT_BIT_i_8__1
(.I0(\COUNT_reg_n_0_[4] ),
.I1(\COUNT_reg_n_0_[5] ),
.O(OUT_BIT_i_8__1_n_0));
LUT2 #(
.INIT(4'h1))
OUT_BIT_i_9__1
(.I0(\COUNT_reg_n_0_[2] ),
.I1(\COUNT_reg_n_0_[3] ),
.O(OUT_BIT_i_9__1_n_0));
FDRE OUT_BIT_reg
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(OUT_BIT_i_1__1_n_0),
.Q(LED_B_PWM_OBUF),
.R(1'b0));
CARRY4 OUT_BIT_reg_i_2__1
(.CI(1'b0),
.CO({p_0_in,NLW_OUT_BIT_reg_i_2__1_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b1),
.DI({OUT_BIT_i_3__1_n_0,OUT_BIT_i_4__1_n_0,OUT_BIT_i_5__1_n_0,OUT_BIT_i_6__1_n_0}),
.O(NLW_OUT_BIT_reg_i_2__1_O_UNCONNECTED[3:0]),
.S({OUT_BIT_i_7__1_n_0,OUT_BIT_i_8__1_n_0,OUT_BIT_i_9__1_n_0,OUT_BIT_i_10__1_n_0}));
(* SOFT_HLUTNM = "soft_lutpair47" *)
LUT1 #(
.INIT(2'h1))
\TIMER[0]_i_1__2
(.I0(\TIMER_reg_n_0_[0] ),
.O(TIMER[0]));
(* SOFT_HLUTNM = "soft_lutpair47" *)
LUT2 #(
.INIT(4'h9))
\TIMER[1]_i_1__1
(.I0(\TIMER_reg_n_0_[1] ),
.I1(\TIMER_reg_n_0_[0] ),
.O(TIMER[1]));
LUT3 #(
.INIT(8'hA9))
\TIMER[2]_i_1__2
(.I0(\TIMER_reg_n_0_[2] ),
.I1(\TIMER_reg_n_0_[0] ),
.I2(\TIMER_reg_n_0_[1] ),
.O(TIMER[2]));
LUT6 #(
.INIT(64'hF0F0F0F0F0F0F00E))
\TIMER[3]_i_1__1
(.I0(\TIMER[4]_i_2__1_n_0 ),
.I1(\TIMER_reg_n_0_[4] ),
.I2(\TIMER_reg_n_0_[3] ),
.I3(\TIMER_reg_n_0_[1] ),
.I4(\TIMER_reg_n_0_[0] ),
.I5(\TIMER_reg_n_0_[2] ),
.O(TIMER[3]));
LUT6 #(
.INIT(64'hFFFE0001FFFE0000))
\TIMER[4]_i_1__1
(.I0(\TIMER_reg_n_0_[3] ),
.I1(\TIMER_reg_n_0_[1] ),
.I2(\TIMER_reg_n_0_[0] ),
.I3(\TIMER_reg_n_0_[2] ),
.I4(\TIMER_reg_n_0_[4] ),
.I5(\TIMER[4]_i_2__1_n_0 ),
.O(TIMER[4]));
LUT5 #(
.INIT(32'hFFFFFFFE))
\TIMER[4]_i_2__1
(.I0(\TIMER_reg_n_0_[8] ),
.I1(\TIMER_reg_n_0_[6] ),
.I2(\TIMER_reg_n_0_[5] ),
.I3(\TIMER_reg_n_0_[7] ),
.I4(\TIMER_reg_n_0_[9] ),
.O(\TIMER[4]_i_2__1_n_0 ));
LUT6 #(
.INIT(64'hAAAAAAAAAAAAAAA9))
\TIMER[5]_i_1__1
(.I0(\TIMER_reg_n_0_[5] ),
.I1(\TIMER_reg_n_0_[3] ),
.I2(\TIMER_reg_n_0_[1] ),
.I3(\TIMER_reg_n_0_[0] ),
.I4(\TIMER_reg_n_0_[2] ),
.I5(\TIMER_reg_n_0_[4] ),
.O(TIMER[5]));
LUT3 #(
.INIT(8'hE1))
\TIMER[6]_i_1__2
(.I0(\TIMER[9]_i_2__1_n_0 ),
.I1(\TIMER_reg_n_0_[5] ),
.I2(\TIMER_reg_n_0_[6] ),
.O(TIMER[6]));
(* SOFT_HLUTNM = "soft_lutpair44" *)
LUT4 #(
.INIT(16'hFE01))
\TIMER[7]_i_1__2
(.I0(\TIMER[9]_i_2__1_n_0 ),
.I1(\TIMER_reg_n_0_[6] ),
.I2(\TIMER_reg_n_0_[5] ),
.I3(\TIMER_reg_n_0_[7] ),
.O(TIMER[7]));
(* SOFT_HLUTNM = "soft_lutpair44" *)
LUT5 #(
.INIT(32'hFFFE0001))
\TIMER[8]_i_1__2
(.I0(\TIMER[9]_i_2__1_n_0 ),
.I1(\TIMER_reg_n_0_[7] ),
.I2(\TIMER_reg_n_0_[5] ),
.I3(\TIMER_reg_n_0_[6] ),
.I4(\TIMER_reg_n_0_[8] ),
.O(TIMER[8]));
LUT6 #(
.INIT(64'hFFFFFFFE00000001))
\TIMER[9]_i_1__1
(.I0(\TIMER[9]_i_2__1_n_0 ),
.I1(\TIMER_reg_n_0_[8] ),
.I2(\TIMER_reg_n_0_[6] ),
.I3(\TIMER_reg_n_0_[5] ),
.I4(\TIMER_reg_n_0_[7] ),
.I5(\TIMER_reg_n_0_[9] ),
.O(TIMER[9]));
LUT5 #(
.INIT(32'hFFFFFFFE))
\TIMER[9]_i_2__1
(.I0(\TIMER_reg_n_0_[3] ),
.I1(\TIMER_reg_n_0_[1] ),
.I2(\TIMER_reg_n_0_[0] ),
.I3(\TIMER_reg_n_0_[2] ),
.I4(\TIMER_reg_n_0_[4] ),
.O(\TIMER[9]_i_2__1_n_0 ));
FDRE #(
.INIT(1'b1))
\TIMER_reg[0]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(TIMER[0]),
.Q(\TIMER_reg_n_0_[0] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\TIMER_reg[1]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(TIMER[1]),
.Q(\TIMER_reg_n_0_[1] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\TIMER_reg[2]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(TIMER[2]),
.Q(\TIMER_reg_n_0_[2] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\TIMER_reg[3]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(TIMER[3]),
.Q(\TIMER_reg_n_0_[3] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\TIMER_reg[4]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(TIMER[4]),
.Q(\TIMER_reg_n_0_[4] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\TIMER_reg[5]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(TIMER[5]),
.Q(\TIMER_reg_n_0_[5] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\TIMER_reg[6]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(TIMER[6]),
.Q(\TIMER_reg_n_0_[6] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\TIMER_reg[7]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(TIMER[7]),
.Q(\TIMER_reg_n_0_[7] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\TIMER_reg[8]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(TIMER[8]),
.Q(\TIMER_reg_n_0_[8] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\TIMER_reg[9]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(TIMER[9]),
.Q(\TIMER_reg_n_0_[9] ),
.R(1'b0));
endmodule
|
module RAM32M_UNIQ_BASE_
(DOA,
DOB,
DOC,
DOD,
ADDRA,
ADDRB,
ADDRC,
ADDRD,
DIA,
DIB,
DIC,
DID,
WCLK,
WE);
output [1:0]DOA;
output [1:0]DOB;
output [1:0]DOC;
output [1:0]DOD;
input [4:0]ADDRA;
input [4:0]ADDRB;
input [4:0]ADDRC;
input [4:0]ADDRD;
input [1:0]DIA;
input [1:0]DIB;
input [1:0]DIC;
input [1:0]DID;
input WCLK;
input WE;
wire ADDRA0;
wire ADDRA1;
wire ADDRA2;
wire ADDRA3;
wire ADDRA4;
wire ADDRB0;
wire ADDRB1;
wire ADDRB2;
wire ADDRB3;
wire ADDRB4;
wire ADDRC0;
wire ADDRC1;
wire ADDRC2;
wire ADDRC3;
wire ADDRC4;
wire ADDRD0;
wire ADDRD1;
wire ADDRD2;
wire ADDRD3;
wire ADDRD4;
wire DIA0;
wire DIA1;
wire DIB0;
wire DIB1;
wire DIC0;
wire DIC1;
wire DID0;
wire DID1;
wire DOA0;
wire DOA1;
wire DOB0;
wire DOB1;
wire DOC0;
wire DOC1;
wire DOD0;
wire DOD1;
wire WCLK;
wire WE;
assign ADDRA0 = ADDRA[0];
assign ADDRA1 = ADDRA[1];
assign ADDRA2 = ADDRA[2];
assign ADDRA3 = ADDRA[3];
assign ADDRA4 = ADDRA[4];
assign ADDRB0 = ADDRB[0];
assign ADDRB1 = ADDRB[1];
assign ADDRB2 = ADDRB[2];
assign ADDRB3 = ADDRB[3];
assign ADDRB4 = ADDRB[4];
assign ADDRC0 = ADDRC[0];
assign ADDRC1 = ADDRC[1];
assign ADDRC2 = ADDRC[2];
assign ADDRC3 = ADDRC[3];
assign ADDRC4 = ADDRC[4];
assign ADDRD0 = ADDRD[0];
assign ADDRD1 = ADDRD[1];
assign ADDRD2 = ADDRD[2];
assign ADDRD3 = ADDRD[3];
assign ADDRD4 = ADDRD[4];
assign DIA0 = DIA[0];
assign DIA1 = DIA[1];
assign DIB0 = DIB[0];
assign DIB1 = DIB[1];
assign DIC0 = DIC[0];
assign DIC1 = DIC[1];
assign DID0 = DID[0];
assign DID1 = DID[1];
assign DOA[1] = DOA1;
assign DOA[0] = DOA0;
assign DOB[1] = DOB1;
assign DOB[0] = DOB0;
assign DOC[1] = DOC1;
assign DOC[0] = DOC0;
assign DOD[1] = DOD1;
assign DOD[0] = DOD0;
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMA
(.CLK(WCLK),
.I(DIA0),
.O(DOA0),
.RADR0(ADDRA0),
.RADR1(ADDRA1),
.RADR2(ADDRA2),
.RADR3(ADDRA3),
.RADR4(ADDRA4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMA_D1
(.CLK(WCLK),
.I(DIA1),
.O(DOA1),
.RADR0(ADDRA0),
.RADR1(ADDRA1),
.RADR2(ADDRA2),
.RADR3(ADDRA3),
.RADR4(ADDRA4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMB
(.CLK(WCLK),
.I(DIB0),
.O(DOB0),
.RADR0(ADDRB0),
.RADR1(ADDRB1),
.RADR2(ADDRB2),
.RADR3(ADDRB3),
.RADR4(ADDRB4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMB_D1
(.CLK(WCLK),
.I(DIB1),
.O(DOB1),
.RADR0(ADDRB0),
.RADR1(ADDRB1),
.RADR2(ADDRB2),
.RADR3(ADDRB3),
.RADR4(ADDRB4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMC
(.CLK(WCLK),
.I(DIC0),
.O(DOC0),
.RADR0(ADDRC0),
.RADR1(ADDRC1),
.RADR2(ADDRC2),
.RADR3(ADDRC3),
.RADR4(ADDRC4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMC_D1
(.CLK(WCLK),
.I(DIC1),
.O(DOC1),
.RADR0(ADDRC0),
.RADR1(ADDRC1),
.RADR2(ADDRC2),
.RADR3(ADDRC3),
.RADR4(ADDRC4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMS32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMD
(.ADR0(ADDRD0),
.ADR1(ADDRD1),
.ADR2(ADDRD2),
.ADR3(ADDRD3),
.ADR4(ADDRD4),
.CLK(WCLK),
.I(DID0),
.O(DOD0),
.WE(WE));
RAMS32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMD_D1
(.ADR0(ADDRD0),
.ADR1(ADDRD1),
.ADR2(ADDRD2),
.ADR3(ADDRD3),
.ADR4(ADDRD4),
.CLK(WCLK),
.I(DID1),
.O(DOD1),
.WE(WE));
endmodule
|
module RAM32M_HD10
(DOA,
DOB,
DOC,
DOD,
ADDRA,
ADDRB,
ADDRC,
ADDRD,
DIA,
DIB,
DIC,
DID,
WCLK,
WE);
output [1:0]DOA;
output [1:0]DOB;
output [1:0]DOC;
output [1:0]DOD;
input [4:0]ADDRA;
input [4:0]ADDRB;
input [4:0]ADDRC;
input [4:0]ADDRD;
input [1:0]DIA;
input [1:0]DIB;
input [1:0]DIC;
input [1:0]DID;
input WCLK;
input WE;
wire ADDRA0;
wire ADDRA1;
wire ADDRA2;
wire ADDRA3;
wire ADDRA4;
wire ADDRB0;
wire ADDRB1;
wire ADDRB2;
wire ADDRB3;
wire ADDRB4;
wire ADDRC0;
wire ADDRC1;
wire ADDRC2;
wire ADDRC3;
wire ADDRC4;
wire ADDRD0;
wire ADDRD1;
wire ADDRD2;
wire ADDRD3;
wire ADDRD4;
wire DIA0;
wire DIA1;
wire DIB0;
wire DIB1;
wire DIC0;
wire DIC1;
wire DID0;
wire DID1;
wire DOA0;
wire DOA1;
wire DOB0;
wire DOB1;
wire DOC0;
wire DOC1;
wire DOD0;
wire DOD1;
wire WCLK;
wire WE;
assign ADDRA0 = ADDRA[0];
assign ADDRA1 = ADDRA[1];
assign ADDRA2 = ADDRA[2];
assign ADDRA3 = ADDRA[3];
assign ADDRA4 = ADDRA[4];
assign ADDRB0 = ADDRB[0];
assign ADDRB1 = ADDRB[1];
assign ADDRB2 = ADDRB[2];
assign ADDRB3 = ADDRB[3];
assign ADDRB4 = ADDRB[4];
assign ADDRC0 = ADDRC[0];
assign ADDRC1 = ADDRC[1];
assign ADDRC2 = ADDRC[2];
assign ADDRC3 = ADDRC[3];
assign ADDRC4 = ADDRC[4];
assign ADDRD0 = ADDRD[0];
assign ADDRD1 = ADDRD[1];
assign ADDRD2 = ADDRD[2];
assign ADDRD3 = ADDRD[3];
assign ADDRD4 = ADDRD[4];
assign DIA0 = DIA[0];
assign DIA1 = DIA[1];
assign DIB0 = DIB[0];
assign DIB1 = DIB[1];
assign DIC0 = DIC[0];
assign DIC1 = DIC[1];
assign DID0 = DID[0];
assign DID1 = DID[1];
assign DOA[1] = DOA1;
assign DOA[0] = DOA0;
assign DOB[1] = DOB1;
assign DOB[0] = DOB0;
assign DOC[1] = DOC1;
assign DOC[0] = DOC0;
assign DOD[1] = DOD1;
assign DOD[0] = DOD0;
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMA
(.CLK(WCLK),
.I(DIA0),
.O(DOA0),
.RADR0(ADDRA0),
.RADR1(ADDRA1),
.RADR2(ADDRA2),
.RADR3(ADDRA3),
.RADR4(ADDRA4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMA_D1
(.CLK(WCLK),
.I(DIA1),
.O(DOA1),
.RADR0(ADDRA0),
.RADR1(ADDRA1),
.RADR2(ADDRA2),
.RADR3(ADDRA3),
.RADR4(ADDRA4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMB
(.CLK(WCLK),
.I(DIB0),
.O(DOB0),
.RADR0(ADDRB0),
.RADR1(ADDRB1),
.RADR2(ADDRB2),
.RADR3(ADDRB3),
.RADR4(ADDRB4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMB_D1
(.CLK(WCLK),
.I(DIB1),
.O(DOB1),
.RADR0(ADDRB0),
.RADR1(ADDRB1),
.RADR2(ADDRB2),
.RADR3(ADDRB3),
.RADR4(ADDRB4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMC
(.CLK(WCLK),
.I(DIC0),
.O(DOC0),
.RADR0(ADDRC0),
.RADR1(ADDRC1),
.RADR2(ADDRC2),
.RADR3(ADDRC3),
.RADR4(ADDRC4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMC_D1
(.CLK(WCLK),
.I(DIC1),
.O(DOC1),
.RADR0(ADDRC0),
.RADR1(ADDRC1),
.RADR2(ADDRC2),
.RADR3(ADDRC3),
.RADR4(ADDRC4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMS32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMD
(.ADR0(ADDRD0),
.ADR1(ADDRD1),
.ADR2(ADDRD2),
.ADR3(ADDRD3),
.ADR4(ADDRD4),
.CLK(WCLK),
.I(DID0),
.O(DOD0),
.WE(WE));
RAMS32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMD_D1
(.ADR0(ADDRD0),
.ADR1(ADDRD1),
.ADR2(ADDRD2),
.ADR3(ADDRD3),
.ADR4(ADDRD4),
.CLK(WCLK),
.I(DID1),
.O(DOD1),
.WE(WE));
endmodule
|
module RAM32M_HD11
(DOA,
DOB,
DOC,
DOD,
ADDRA,
ADDRB,
ADDRC,
ADDRD,
DIA,
DIB,
DIC,
DID,
WCLK,
WE);
output [1:0]DOA;
output [1:0]DOB;
output [1:0]DOC;
output [1:0]DOD;
input [4:0]ADDRA;
input [4:0]ADDRB;
input [4:0]ADDRC;
input [4:0]ADDRD;
input [1:0]DIA;
input [1:0]DIB;
input [1:0]DIC;
input [1:0]DID;
input WCLK;
input WE;
wire ADDRA0;
wire ADDRA1;
wire ADDRA2;
wire ADDRA3;
wire ADDRA4;
wire ADDRB0;
wire ADDRB1;
wire ADDRB2;
wire ADDRB3;
wire ADDRB4;
wire ADDRC0;
wire ADDRC1;
wire ADDRC2;
wire ADDRC3;
wire ADDRC4;
wire ADDRD0;
wire ADDRD1;
wire ADDRD2;
wire ADDRD3;
wire ADDRD4;
wire DIA0;
wire DIA1;
wire DIB0;
wire DIB1;
wire DIC0;
wire DIC1;
wire DID0;
wire DID1;
wire DOA0;
wire DOA1;
wire DOB0;
wire DOB1;
wire DOC0;
wire DOC1;
wire DOD0;
wire DOD1;
wire WCLK;
wire WE;
assign ADDRA0 = ADDRA[0];
assign ADDRA1 = ADDRA[1];
assign ADDRA2 = ADDRA[2];
assign ADDRA3 = ADDRA[3];
assign ADDRA4 = ADDRA[4];
assign ADDRB0 = ADDRB[0];
assign ADDRB1 = ADDRB[1];
assign ADDRB2 = ADDRB[2];
assign ADDRB3 = ADDRB[3];
assign ADDRB4 = ADDRB[4];
assign ADDRC0 = ADDRC[0];
assign ADDRC1 = ADDRC[1];
assign ADDRC2 = ADDRC[2];
assign ADDRC3 = ADDRC[3];
assign ADDRC4 = ADDRC[4];
assign ADDRD0 = ADDRD[0];
assign ADDRD1 = ADDRD[1];
assign ADDRD2 = ADDRD[2];
assign ADDRD3 = ADDRD[3];
assign ADDRD4 = ADDRD[4];
assign DIA0 = DIA[0];
assign DIA1 = DIA[1];
assign DIB0 = DIB[0];
assign DIB1 = DIB[1];
assign DIC0 = DIC[0];
assign DIC1 = DIC[1];
assign DID0 = DID[0];
assign DID1 = DID[1];
assign DOA[1] = DOA1;
assign DOA[0] = DOA0;
assign DOB[1] = DOB1;
assign DOB[0] = DOB0;
assign DOC[1] = DOC1;
assign DOC[0] = DOC0;
assign DOD[1] = DOD1;
assign DOD[0] = DOD0;
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMA
(.CLK(WCLK),
.I(DIA0),
.O(DOA0),
.RADR0(ADDRA0),
.RADR1(ADDRA1),
.RADR2(ADDRA2),
.RADR3(ADDRA3),
.RADR4(ADDRA4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMA_D1
(.CLK(WCLK),
.I(DIA1),
.O(DOA1),
.RADR0(ADDRA0),
.RADR1(ADDRA1),
.RADR2(ADDRA2),
.RADR3(ADDRA3),
.RADR4(ADDRA4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMB
(.CLK(WCLK),
.I(DIB0),
.O(DOB0),
.RADR0(ADDRB0),
.RADR1(ADDRB1),
.RADR2(ADDRB2),
.RADR3(ADDRB3),
.RADR4(ADDRB4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMB_D1
(.CLK(WCLK),
.I(DIB1),
.O(DOB1),
.RADR0(ADDRB0),
.RADR1(ADDRB1),
.RADR2(ADDRB2),
.RADR3(ADDRB3),
.RADR4(ADDRB4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMC
(.CLK(WCLK),
.I(DIC0),
.O(DOC0),
.RADR0(ADDRC0),
.RADR1(ADDRC1),
.RADR2(ADDRC2),
.RADR3(ADDRC3),
.RADR4(ADDRC4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMC_D1
(.CLK(WCLK),
.I(DIC1),
.O(DOC1),
.RADR0(ADDRC0),
.RADR1(ADDRC1),
.RADR2(ADDRC2),
.RADR3(ADDRC3),
.RADR4(ADDRC4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMS32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMD
(.ADR0(ADDRD0),
.ADR1(ADDRD1),
.ADR2(ADDRD2),
.ADR3(ADDRD3),
.ADR4(ADDRD4),
.CLK(WCLK),
.I(DID0),
.O(DOD0),
.WE(WE));
RAMS32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMD_D1
(.ADR0(ADDRD0),
.ADR1(ADDRD1),
.ADR2(ADDRD2),
.ADR3(ADDRD3),
.ADR4(ADDRD4),
.CLK(WCLK),
.I(DID1),
.O(DOD1),
.WE(WE));
endmodule
|
module RAM32M_HD12
(DOA,
DOB,
DOC,
DOD,
ADDRA,
ADDRB,
ADDRC,
ADDRD,
DIA,
DIB,
DIC,
DID,
WCLK,
WE);
output [1:0]DOA;
output [1:0]DOB;
output [1:0]DOC;
output [1:0]DOD;
input [4:0]ADDRA;
input [4:0]ADDRB;
input [4:0]ADDRC;
input [4:0]ADDRD;
input [1:0]DIA;
input [1:0]DIB;
input [1:0]DIC;
input [1:0]DID;
input WCLK;
input WE;
wire ADDRA0;
wire ADDRA1;
wire ADDRA2;
wire ADDRA3;
wire ADDRA4;
wire ADDRB0;
wire ADDRB1;
wire ADDRB2;
wire ADDRB3;
wire ADDRB4;
wire ADDRC0;
wire ADDRC1;
wire ADDRC2;
wire ADDRC3;
wire ADDRC4;
wire ADDRD0;
wire ADDRD1;
wire ADDRD2;
wire ADDRD3;
wire ADDRD4;
wire DIA0;
wire DIA1;
wire DIB0;
wire DIB1;
wire DIC0;
wire DIC1;
wire DID0;
wire DID1;
wire DOA0;
wire DOA1;
wire DOB0;
wire DOB1;
wire DOC0;
wire DOC1;
wire DOD0;
wire DOD1;
wire WCLK;
wire WE;
assign ADDRA0 = ADDRA[0];
assign ADDRA1 = ADDRA[1];
assign ADDRA2 = ADDRA[2];
assign ADDRA3 = ADDRA[3];
assign ADDRA4 = ADDRA[4];
assign ADDRB0 = ADDRB[0];
assign ADDRB1 = ADDRB[1];
assign ADDRB2 = ADDRB[2];
assign ADDRB3 = ADDRB[3];
assign ADDRB4 = ADDRB[4];
assign ADDRC0 = ADDRC[0];
assign ADDRC1 = ADDRC[1];
assign ADDRC2 = ADDRC[2];
assign ADDRC3 = ADDRC[3];
assign ADDRC4 = ADDRC[4];
assign ADDRD0 = ADDRD[0];
assign ADDRD1 = ADDRD[1];
assign ADDRD2 = ADDRD[2];
assign ADDRD3 = ADDRD[3];
assign ADDRD4 = ADDRD[4];
assign DIA0 = DIA[0];
assign DIA1 = DIA[1];
assign DIB0 = DIB[0];
assign DIB1 = DIB[1];
assign DIC0 = DIC[0];
assign DIC1 = DIC[1];
assign DID0 = DID[0];
assign DID1 = DID[1];
assign DOA[1] = DOA1;
assign DOA[0] = DOA0;
assign DOB[1] = DOB1;
assign DOB[0] = DOB0;
assign DOC[1] = DOC1;
assign DOC[0] = DOC0;
assign DOD[1] = DOD1;
assign DOD[0] = DOD0;
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMA
(.CLK(WCLK),
.I(DIA0),
.O(DOA0),
.RADR0(ADDRA0),
.RADR1(ADDRA1),
.RADR2(ADDRA2),
.RADR3(ADDRA3),
.RADR4(ADDRA4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMA_D1
(.CLK(WCLK),
.I(DIA1),
.O(DOA1),
.RADR0(ADDRA0),
.RADR1(ADDRA1),
.RADR2(ADDRA2),
.RADR3(ADDRA3),
.RADR4(ADDRA4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMB
(.CLK(WCLK),
.I(DIB0),
.O(DOB0),
.RADR0(ADDRB0),
.RADR1(ADDRB1),
.RADR2(ADDRB2),
.RADR3(ADDRB3),
.RADR4(ADDRB4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMB_D1
(.CLK(WCLK),
.I(DIB1),
.O(DOB1),
.RADR0(ADDRB0),
.RADR1(ADDRB1),
.RADR2(ADDRB2),
.RADR3(ADDRB3),
.RADR4(ADDRB4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMC
(.CLK(WCLK),
.I(DIC0),
.O(DOC0),
.RADR0(ADDRC0),
.RADR1(ADDRC1),
.RADR2(ADDRC2),
.RADR3(ADDRC3),
.RADR4(ADDRC4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMC_D1
(.CLK(WCLK),
.I(DIC1),
.O(DOC1),
.RADR0(ADDRC0),
.RADR1(ADDRC1),
.RADR2(ADDRC2),
.RADR3(ADDRC3),
.RADR4(ADDRC4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMS32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMD
(.ADR0(ADDRD0),
.ADR1(ADDRD1),
.ADR2(ADDRD2),
.ADR3(ADDRD3),
.ADR4(ADDRD4),
.CLK(WCLK),
.I(DID0),
.O(DOD0),
.WE(WE));
RAMS32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMD_D1
(.ADR0(ADDRD0),
.ADR1(ADDRD1),
.ADR2(ADDRD2),
.ADR3(ADDRD3),
.ADR4(ADDRD4),
.CLK(WCLK),
.I(DID1),
.O(DOD1),
.WE(WE));
endmodule
|
module RAM32M_HD13
(DOA,
DOB,
DOC,
DOD,
ADDRA,
ADDRB,
ADDRC,
ADDRD,
DIA,
DIB,
DIC,
DID,
WCLK,
WE);
output [1:0]DOA;
output [1:0]DOB;
output [1:0]DOC;
output [1:0]DOD;
input [4:0]ADDRA;
input [4:0]ADDRB;
input [4:0]ADDRC;
input [4:0]ADDRD;
input [1:0]DIA;
input [1:0]DIB;
input [1:0]DIC;
input [1:0]DID;
input WCLK;
input WE;
wire ADDRA0;
wire ADDRA1;
wire ADDRA2;
wire ADDRA3;
wire ADDRA4;
wire ADDRB0;
wire ADDRB1;
wire ADDRB2;
wire ADDRB3;
wire ADDRB4;
wire ADDRC0;
wire ADDRC1;
wire ADDRC2;
wire ADDRC3;
wire ADDRC4;
wire ADDRD0;
wire ADDRD1;
wire ADDRD2;
wire ADDRD3;
wire ADDRD4;
wire DIA0;
wire DIA1;
wire DIB0;
wire DIB1;
wire DIC0;
wire DIC1;
wire DID0;
wire DID1;
wire DOA0;
wire DOA1;
wire DOB0;
wire DOB1;
wire DOC0;
wire DOC1;
wire DOD0;
wire DOD1;
wire WCLK;
wire WE;
assign ADDRA0 = ADDRA[0];
assign ADDRA1 = ADDRA[1];
assign ADDRA2 = ADDRA[2];
assign ADDRA3 = ADDRA[3];
assign ADDRA4 = ADDRA[4];
assign ADDRB0 = ADDRB[0];
assign ADDRB1 = ADDRB[1];
assign ADDRB2 = ADDRB[2];
assign ADDRB3 = ADDRB[3];
assign ADDRB4 = ADDRB[4];
assign ADDRC0 = ADDRC[0];
assign ADDRC1 = ADDRC[1];
assign ADDRC2 = ADDRC[2];
assign ADDRC3 = ADDRC[3];
assign ADDRC4 = ADDRC[4];
assign ADDRD0 = ADDRD[0];
assign ADDRD1 = ADDRD[1];
assign ADDRD2 = ADDRD[2];
assign ADDRD3 = ADDRD[3];
assign ADDRD4 = ADDRD[4];
assign DIA0 = DIA[0];
assign DIA1 = DIA[1];
assign DIB0 = DIB[0];
assign DIB1 = DIB[1];
assign DIC0 = DIC[0];
assign DIC1 = DIC[1];
assign DID0 = DID[0];
assign DID1 = DID[1];
assign DOA[1] = DOA1;
assign DOA[0] = DOA0;
assign DOB[1] = DOB1;
assign DOB[0] = DOB0;
assign DOC[1] = DOC1;
assign DOC[0] = DOC0;
assign DOD[1] = DOD1;
assign DOD[0] = DOD0;
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMA
(.CLK(WCLK),
.I(DIA0),
.O(DOA0),
.RADR0(ADDRA0),
.RADR1(ADDRA1),
.RADR2(ADDRA2),
.RADR3(ADDRA3),
.RADR4(ADDRA4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMA_D1
(.CLK(WCLK),
.I(DIA1),
.O(DOA1),
.RADR0(ADDRA0),
.RADR1(ADDRA1),
.RADR2(ADDRA2),
.RADR3(ADDRA3),
.RADR4(ADDRA4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMB
(.CLK(WCLK),
.I(DIB0),
.O(DOB0),
.RADR0(ADDRB0),
.RADR1(ADDRB1),
.RADR2(ADDRB2),
.RADR3(ADDRB3),
.RADR4(ADDRB4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMB_D1
(.CLK(WCLK),
.I(DIB1),
.O(DOB1),
.RADR0(ADDRB0),
.RADR1(ADDRB1),
.RADR2(ADDRB2),
.RADR3(ADDRB3),
.RADR4(ADDRB4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMC
(.CLK(WCLK),
.I(DIC0),
.O(DOC0),
.RADR0(ADDRC0),
.RADR1(ADDRC1),
.RADR2(ADDRC2),
.RADR3(ADDRC3),
.RADR4(ADDRC4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMC_D1
(.CLK(WCLK),
.I(DIC1),
.O(DOC1),
.RADR0(ADDRC0),
.RADR1(ADDRC1),
.RADR2(ADDRC2),
.RADR3(ADDRC3),
.RADR4(ADDRC4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMS32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMD
(.ADR0(ADDRD0),
.ADR1(ADDRD1),
.ADR2(ADDRD2),
.ADR3(ADDRD3),
.ADR4(ADDRD4),
.CLK(WCLK),
.I(DID0),
.O(DOD0),
.WE(WE));
RAMS32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMD_D1
(.ADR0(ADDRD0),
.ADR1(ADDRD1),
.ADR2(ADDRD2),
.ADR3(ADDRD3),
.ADR4(ADDRD4),
.CLK(WCLK),
.I(DID1),
.O(DOD1),
.WE(WE));
endmodule
|
module RAM32M_HD14
(DOA,
DOB,
DOC,
DOD,
ADDRA,
ADDRB,
ADDRC,
ADDRD,
DIA,
DIB,
DIC,
DID,
WCLK,
WE);
output [1:0]DOA;
output [1:0]DOB;
output [1:0]DOC;
output [1:0]DOD;
input [4:0]ADDRA;
input [4:0]ADDRB;
input [4:0]ADDRC;
input [4:0]ADDRD;
input [1:0]DIA;
input [1:0]DIB;
input [1:0]DIC;
input [1:0]DID;
input WCLK;
input WE;
wire ADDRA0;
wire ADDRA1;
wire ADDRA2;
wire ADDRA3;
wire ADDRA4;
wire ADDRB0;
wire ADDRB1;
wire ADDRB2;
wire ADDRB3;
wire ADDRB4;
wire ADDRC0;
wire ADDRC1;
wire ADDRC2;
wire ADDRC3;
wire ADDRC4;
wire ADDRD0;
wire ADDRD1;
wire ADDRD2;
wire ADDRD3;
wire ADDRD4;
wire DIA0;
wire DIA1;
wire DIB0;
wire DIB1;
wire DIC0;
wire DIC1;
wire DID0;
wire DID1;
wire DOA0;
wire DOA1;
wire DOB0;
wire DOB1;
wire DOC0;
wire DOC1;
wire DOD0;
wire DOD1;
wire WCLK;
wire WE;
assign ADDRA0 = ADDRA[0];
assign ADDRA1 = ADDRA[1];
assign ADDRA2 = ADDRA[2];
assign ADDRA3 = ADDRA[3];
assign ADDRA4 = ADDRA[4];
assign ADDRB0 = ADDRB[0];
assign ADDRB1 = ADDRB[1];
assign ADDRB2 = ADDRB[2];
assign ADDRB3 = ADDRB[3];
assign ADDRB4 = ADDRB[4];
assign ADDRC0 = ADDRC[0];
assign ADDRC1 = ADDRC[1];
assign ADDRC2 = ADDRC[2];
assign ADDRC3 = ADDRC[3];
assign ADDRC4 = ADDRC[4];
assign ADDRD0 = ADDRD[0];
assign ADDRD1 = ADDRD[1];
assign ADDRD2 = ADDRD[2];
assign ADDRD3 = ADDRD[3];
assign ADDRD4 = ADDRD[4];
assign DIA0 = DIA[0];
assign DIA1 = DIA[1];
assign DIB0 = DIB[0];
assign DIB1 = DIB[1];
assign DIC0 = DIC[0];
assign DIC1 = DIC[1];
assign DID0 = DID[0];
assign DID1 = DID[1];
assign DOA[1] = DOA1;
assign DOA[0] = DOA0;
assign DOB[1] = DOB1;
assign DOB[0] = DOB0;
assign DOC[1] = DOC1;
assign DOC[0] = DOC0;
assign DOD[1] = DOD1;
assign DOD[0] = DOD0;
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMA
(.CLK(WCLK),
.I(DIA0),
.O(DOA0),
.RADR0(ADDRA0),
.RADR1(ADDRA1),
.RADR2(ADDRA2),
.RADR3(ADDRA3),
.RADR4(ADDRA4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMA_D1
(.CLK(WCLK),
.I(DIA1),
.O(DOA1),
.RADR0(ADDRA0),
.RADR1(ADDRA1),
.RADR2(ADDRA2),
.RADR3(ADDRA3),
.RADR4(ADDRA4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMB
(.CLK(WCLK),
.I(DIB0),
.O(DOB0),
.RADR0(ADDRB0),
.RADR1(ADDRB1),
.RADR2(ADDRB2),
.RADR3(ADDRB3),
.RADR4(ADDRB4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMB_D1
(.CLK(WCLK),
.I(DIB1),
.O(DOB1),
.RADR0(ADDRB0),
.RADR1(ADDRB1),
.RADR2(ADDRB2),
.RADR3(ADDRB3),
.RADR4(ADDRB4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMC
(.CLK(WCLK),
.I(DIC0),
.O(DOC0),
.RADR0(ADDRC0),
.RADR1(ADDRC1),
.RADR2(ADDRC2),
.RADR3(ADDRC3),
.RADR4(ADDRC4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMC_D1
(.CLK(WCLK),
.I(DIC1),
.O(DOC1),
.RADR0(ADDRC0),
.RADR1(ADDRC1),
.RADR2(ADDRC2),
.RADR3(ADDRC3),
.RADR4(ADDRC4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMS32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMD
(.ADR0(ADDRD0),
.ADR1(ADDRD1),
.ADR2(ADDRD2),
.ADR3(ADDRD3),
.ADR4(ADDRD4),
.CLK(WCLK),
.I(DID0),
.O(DOD0),
.WE(WE));
RAMS32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMD_D1
(.ADR0(ADDRD0),
.ADR1(ADDRD1),
.ADR2(ADDRD2),
.ADR3(ADDRD3),
.ADR4(ADDRD4),
.CLK(WCLK),
.I(DID1),
.O(DOD1),
.WE(WE));
endmodule
|
module RAM32M_HD4
(DOA,
DOB,
DOC,
DOD,
ADDRA,
ADDRB,
ADDRC,
ADDRD,
DIA,
DIB,
DIC,
DID,
WCLK,
WE);
output [1:0]DOA;
output [1:0]DOB;
output [1:0]DOC;
output [1:0]DOD;
input [4:0]ADDRA;
input [4:0]ADDRB;
input [4:0]ADDRC;
input [4:0]ADDRD;
input [1:0]DIA;
input [1:0]DIB;
input [1:0]DIC;
input [1:0]DID;
input WCLK;
input WE;
wire ADDRA0;
wire ADDRA1;
wire ADDRA2;
wire ADDRA3;
wire ADDRA4;
wire ADDRB0;
wire ADDRB1;
wire ADDRB2;
wire ADDRB3;
wire ADDRB4;
wire ADDRC0;
wire ADDRC1;
wire ADDRC2;
wire ADDRC3;
wire ADDRC4;
wire ADDRD0;
wire ADDRD1;
wire ADDRD2;
wire ADDRD3;
wire ADDRD4;
wire DIA0;
wire DIA1;
wire DIB0;
wire DIB1;
wire DIC0;
wire DIC1;
wire DID0;
wire DID1;
wire DOA0;
wire DOA1;
wire DOB0;
wire DOB1;
wire DOC0;
wire DOC1;
wire DOD0;
wire DOD1;
wire WCLK;
wire WE;
assign ADDRA0 = ADDRA[0];
assign ADDRA1 = ADDRA[1];
assign ADDRA2 = ADDRA[2];
assign ADDRA3 = ADDRA[3];
assign ADDRA4 = ADDRA[4];
assign ADDRB0 = ADDRB[0];
assign ADDRB1 = ADDRB[1];
assign ADDRB2 = ADDRB[2];
assign ADDRB3 = ADDRB[3];
assign ADDRB4 = ADDRB[4];
assign ADDRC0 = ADDRC[0];
assign ADDRC1 = ADDRC[1];
assign ADDRC2 = ADDRC[2];
assign ADDRC3 = ADDRC[3];
assign ADDRC4 = ADDRC[4];
assign ADDRD0 = ADDRD[0];
assign ADDRD1 = ADDRD[1];
assign ADDRD2 = ADDRD[2];
assign ADDRD3 = ADDRD[3];
assign ADDRD4 = ADDRD[4];
assign DIA0 = DIA[0];
assign DIA1 = DIA[1];
assign DIB0 = DIB[0];
assign DIB1 = DIB[1];
assign DIC0 = DIC[0];
assign DIC1 = DIC[1];
assign DID0 = DID[0];
assign DID1 = DID[1];
assign DOA[1] = DOA1;
assign DOA[0] = DOA0;
assign DOB[1] = DOB1;
assign DOB[0] = DOB0;
assign DOC[1] = DOC1;
assign DOC[0] = DOC0;
assign DOD[1] = DOD1;
assign DOD[0] = DOD0;
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMA
(.CLK(WCLK),
.I(DIA0),
.O(DOA0),
.RADR0(ADDRA0),
.RADR1(ADDRA1),
.RADR2(ADDRA2),
.RADR3(ADDRA3),
.RADR4(ADDRA4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMA_D1
(.CLK(WCLK),
.I(DIA1),
.O(DOA1),
.RADR0(ADDRA0),
.RADR1(ADDRA1),
.RADR2(ADDRA2),
.RADR3(ADDRA3),
.RADR4(ADDRA4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMB
(.CLK(WCLK),
.I(DIB0),
.O(DOB0),
.RADR0(ADDRB0),
.RADR1(ADDRB1),
.RADR2(ADDRB2),
.RADR3(ADDRB3),
.RADR4(ADDRB4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMB_D1
(.CLK(WCLK),
.I(DIB1),
.O(DOB1),
.RADR0(ADDRB0),
.RADR1(ADDRB1),
.RADR2(ADDRB2),
.RADR3(ADDRB3),
.RADR4(ADDRB4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMC
(.CLK(WCLK),
.I(DIC0),
.O(DOC0),
.RADR0(ADDRC0),
.RADR1(ADDRC1),
.RADR2(ADDRC2),
.RADR3(ADDRC3),
.RADR4(ADDRC4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMC_D1
(.CLK(WCLK),
.I(DIC1),
.O(DOC1),
.RADR0(ADDRC0),
.RADR1(ADDRC1),
.RADR2(ADDRC2),
.RADR3(ADDRC3),
.RADR4(ADDRC4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMS32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMD
(.ADR0(ADDRD0),
.ADR1(ADDRD1),
.ADR2(ADDRD2),
.ADR3(ADDRD3),
.ADR4(ADDRD4),
.CLK(WCLK),
.I(DID0),
.O(DOD0),
.WE(WE));
RAMS32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMD_D1
(.ADR0(ADDRD0),
.ADR1(ADDRD1),
.ADR2(ADDRD2),
.ADR3(ADDRD3),
.ADR4(ADDRD4),
.CLK(WCLK),
.I(DID1),
.O(DOD1),
.WE(WE));
endmodule
|
module RAM32M_HD5
(DOA,
DOB,
DOC,
DOD,
ADDRA,
ADDRB,
ADDRC,
ADDRD,
DIA,
DIB,
DIC,
DID,
WCLK,
WE);
output [1:0]DOA;
output [1:0]DOB;
output [1:0]DOC;
output [1:0]DOD;
input [4:0]ADDRA;
input [4:0]ADDRB;
input [4:0]ADDRC;
input [4:0]ADDRD;
input [1:0]DIA;
input [1:0]DIB;
input [1:0]DIC;
input [1:0]DID;
input WCLK;
input WE;
wire ADDRA0;
wire ADDRA1;
wire ADDRA2;
wire ADDRA3;
wire ADDRA4;
wire ADDRB0;
wire ADDRB1;
wire ADDRB2;
wire ADDRB3;
wire ADDRB4;
wire ADDRC0;
wire ADDRC1;
wire ADDRC2;
wire ADDRC3;
wire ADDRC4;
wire ADDRD0;
wire ADDRD1;
wire ADDRD2;
wire ADDRD3;
wire ADDRD4;
wire DIA0;
wire DIA1;
wire DIB0;
wire DIB1;
wire DIC0;
wire DIC1;
wire DID0;
wire DID1;
wire DOA0;
wire DOA1;
wire DOB0;
wire DOB1;
wire DOC0;
wire DOC1;
wire DOD0;
wire DOD1;
wire WCLK;
wire WE;
assign ADDRA0 = ADDRA[0];
assign ADDRA1 = ADDRA[1];
assign ADDRA2 = ADDRA[2];
assign ADDRA3 = ADDRA[3];
assign ADDRA4 = ADDRA[4];
assign ADDRB0 = ADDRB[0];
assign ADDRB1 = ADDRB[1];
assign ADDRB2 = ADDRB[2];
assign ADDRB3 = ADDRB[3];
assign ADDRB4 = ADDRB[4];
assign ADDRC0 = ADDRC[0];
assign ADDRC1 = ADDRC[1];
assign ADDRC2 = ADDRC[2];
assign ADDRC3 = ADDRC[3];
assign ADDRC4 = ADDRC[4];
assign ADDRD0 = ADDRD[0];
assign ADDRD1 = ADDRD[1];
assign ADDRD2 = ADDRD[2];
assign ADDRD3 = ADDRD[3];
assign ADDRD4 = ADDRD[4];
assign DIA0 = DIA[0];
assign DIA1 = DIA[1];
assign DIB0 = DIB[0];
assign DIB1 = DIB[1];
assign DIC0 = DIC[0];
assign DIC1 = DIC[1];
assign DID0 = DID[0];
assign DID1 = DID[1];
assign DOA[1] = DOA1;
assign DOA[0] = DOA0;
assign DOB[1] = DOB1;
assign DOB[0] = DOB0;
assign DOC[1] = DOC1;
assign DOC[0] = DOC0;
assign DOD[1] = DOD1;
assign DOD[0] = DOD0;
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMA
(.CLK(WCLK),
.I(DIA0),
.O(DOA0),
.RADR0(ADDRA0),
.RADR1(ADDRA1),
.RADR2(ADDRA2),
.RADR3(ADDRA3),
.RADR4(ADDRA4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMA_D1
(.CLK(WCLK),
.I(DIA1),
.O(DOA1),
.RADR0(ADDRA0),
.RADR1(ADDRA1),
.RADR2(ADDRA2),
.RADR3(ADDRA3),
.RADR4(ADDRA4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMB
(.CLK(WCLK),
.I(DIB0),
.O(DOB0),
.RADR0(ADDRB0),
.RADR1(ADDRB1),
.RADR2(ADDRB2),
.RADR3(ADDRB3),
.RADR4(ADDRB4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMB_D1
(.CLK(WCLK),
.I(DIB1),
.O(DOB1),
.RADR0(ADDRB0),
.RADR1(ADDRB1),
.RADR2(ADDRB2),
.RADR3(ADDRB3),
.RADR4(ADDRB4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMC
(.CLK(WCLK),
.I(DIC0),
.O(DOC0),
.RADR0(ADDRC0),
.RADR1(ADDRC1),
.RADR2(ADDRC2),
.RADR3(ADDRC3),
.RADR4(ADDRC4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMC_D1
(.CLK(WCLK),
.I(DIC1),
.O(DOC1),
.RADR0(ADDRC0),
.RADR1(ADDRC1),
.RADR2(ADDRC2),
.RADR3(ADDRC3),
.RADR4(ADDRC4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMS32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMD
(.ADR0(ADDRD0),
.ADR1(ADDRD1),
.ADR2(ADDRD2),
.ADR3(ADDRD3),
.ADR4(ADDRD4),
.CLK(WCLK),
.I(DID0),
.O(DOD0),
.WE(WE));
RAMS32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMD_D1
(.ADR0(ADDRD0),
.ADR1(ADDRD1),
.ADR2(ADDRD2),
.ADR3(ADDRD3),
.ADR4(ADDRD4),
.CLK(WCLK),
.I(DID1),
.O(DOD1),
.WE(WE));
endmodule
|
module RAM32M_HD6
(DOA,
DOB,
DOC,
DOD,
ADDRA,
ADDRB,
ADDRC,
ADDRD,
DIA,
DIB,
DIC,
DID,
WCLK,
WE);
output [1:0]DOA;
output [1:0]DOB;
output [1:0]DOC;
output [1:0]DOD;
input [4:0]ADDRA;
input [4:0]ADDRB;
input [4:0]ADDRC;
input [4:0]ADDRD;
input [1:0]DIA;
input [1:0]DIB;
input [1:0]DIC;
input [1:0]DID;
input WCLK;
input WE;
wire ADDRA0;
wire ADDRA1;
wire ADDRA2;
wire ADDRA3;
wire ADDRA4;
wire ADDRB0;
wire ADDRB1;
wire ADDRB2;
wire ADDRB3;
wire ADDRB4;
wire ADDRC0;
wire ADDRC1;
wire ADDRC2;
wire ADDRC3;
wire ADDRC4;
wire ADDRD0;
wire ADDRD1;
wire ADDRD2;
wire ADDRD3;
wire ADDRD4;
wire DIA0;
wire DIA1;
wire DIB0;
wire DIB1;
wire DIC0;
wire DIC1;
wire DID0;
wire DID1;
wire DOA0;
wire DOA1;
wire DOB0;
wire DOB1;
wire DOC0;
wire DOC1;
wire DOD0;
wire DOD1;
wire WCLK;
wire WE;
assign ADDRA0 = ADDRA[0];
assign ADDRA1 = ADDRA[1];
assign ADDRA2 = ADDRA[2];
assign ADDRA3 = ADDRA[3];
assign ADDRA4 = ADDRA[4];
assign ADDRB0 = ADDRB[0];
assign ADDRB1 = ADDRB[1];
assign ADDRB2 = ADDRB[2];
assign ADDRB3 = ADDRB[3];
assign ADDRB4 = ADDRB[4];
assign ADDRC0 = ADDRC[0];
assign ADDRC1 = ADDRC[1];
assign ADDRC2 = ADDRC[2];
assign ADDRC3 = ADDRC[3];
assign ADDRC4 = ADDRC[4];
assign ADDRD0 = ADDRD[0];
assign ADDRD1 = ADDRD[1];
assign ADDRD2 = ADDRD[2];
assign ADDRD3 = ADDRD[3];
assign ADDRD4 = ADDRD[4];
assign DIA0 = DIA[0];
assign DIA1 = DIA[1];
assign DIB0 = DIB[0];
assign DIB1 = DIB[1];
assign DIC0 = DIC[0];
assign DIC1 = DIC[1];
assign DID0 = DID[0];
assign DID1 = DID[1];
assign DOA[1] = DOA1;
assign DOA[0] = DOA0;
assign DOB[1] = DOB1;
assign DOB[0] = DOB0;
assign DOC[1] = DOC1;
assign DOC[0] = DOC0;
assign DOD[1] = DOD1;
assign DOD[0] = DOD0;
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMA
(.CLK(WCLK),
.I(DIA0),
.O(DOA0),
.RADR0(ADDRA0),
.RADR1(ADDRA1),
.RADR2(ADDRA2),
.RADR3(ADDRA3),
.RADR4(ADDRA4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMA_D1
(.CLK(WCLK),
.I(DIA1),
.O(DOA1),
.RADR0(ADDRA0),
.RADR1(ADDRA1),
.RADR2(ADDRA2),
.RADR3(ADDRA3),
.RADR4(ADDRA4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMB
(.CLK(WCLK),
.I(DIB0),
.O(DOB0),
.RADR0(ADDRB0),
.RADR1(ADDRB1),
.RADR2(ADDRB2),
.RADR3(ADDRB3),
.RADR4(ADDRB4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMB_D1
(.CLK(WCLK),
.I(DIB1),
.O(DOB1),
.RADR0(ADDRB0),
.RADR1(ADDRB1),
.RADR2(ADDRB2),
.RADR3(ADDRB3),
.RADR4(ADDRB4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMC
(.CLK(WCLK),
.I(DIC0),
.O(DOC0),
.RADR0(ADDRC0),
.RADR1(ADDRC1),
.RADR2(ADDRC2),
.RADR3(ADDRC3),
.RADR4(ADDRC4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMC_D1
(.CLK(WCLK),
.I(DIC1),
.O(DOC1),
.RADR0(ADDRC0),
.RADR1(ADDRC1),
.RADR2(ADDRC2),
.RADR3(ADDRC3),
.RADR4(ADDRC4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMS32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMD
(.ADR0(ADDRD0),
.ADR1(ADDRD1),
.ADR2(ADDRD2),
.ADR3(ADDRD3),
.ADR4(ADDRD4),
.CLK(WCLK),
.I(DID0),
.O(DOD0),
.WE(WE));
RAMS32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMD_D1
(.ADR0(ADDRD0),
.ADR1(ADDRD1),
.ADR2(ADDRD2),
.ADR3(ADDRD3),
.ADR4(ADDRD4),
.CLK(WCLK),
.I(DID1),
.O(DOD1),
.WE(WE));
endmodule
|
module RAM32M_HD7
(DOA,
DOB,
DOC,
DOD,
ADDRA,
ADDRB,
ADDRC,
ADDRD,
DIA,
DIB,
DIC,
DID,
WCLK,
WE);
output [1:0]DOA;
output [1:0]DOB;
output [1:0]DOC;
output [1:0]DOD;
input [4:0]ADDRA;
input [4:0]ADDRB;
input [4:0]ADDRC;
input [4:0]ADDRD;
input [1:0]DIA;
input [1:0]DIB;
input [1:0]DIC;
input [1:0]DID;
input WCLK;
input WE;
wire ADDRA0;
wire ADDRA1;
wire ADDRA2;
wire ADDRA3;
wire ADDRA4;
wire ADDRB0;
wire ADDRB1;
wire ADDRB2;
wire ADDRB3;
wire ADDRB4;
wire ADDRC0;
wire ADDRC1;
wire ADDRC2;
wire ADDRC3;
wire ADDRC4;
wire ADDRD0;
wire ADDRD1;
wire ADDRD2;
wire ADDRD3;
wire ADDRD4;
wire DIA0;
wire DIA1;
wire DIB0;
wire DIB1;
wire DIC0;
wire DIC1;
wire DID0;
wire DID1;
wire DOA0;
wire DOA1;
wire DOB0;
wire DOB1;
wire DOC0;
wire DOC1;
wire DOD0;
wire DOD1;
wire WCLK;
wire WE;
assign ADDRA0 = ADDRA[0];
assign ADDRA1 = ADDRA[1];
assign ADDRA2 = ADDRA[2];
assign ADDRA3 = ADDRA[3];
assign ADDRA4 = ADDRA[4];
assign ADDRB0 = ADDRB[0];
assign ADDRB1 = ADDRB[1];
assign ADDRB2 = ADDRB[2];
assign ADDRB3 = ADDRB[3];
assign ADDRB4 = ADDRB[4];
assign ADDRC0 = ADDRC[0];
assign ADDRC1 = ADDRC[1];
assign ADDRC2 = ADDRC[2];
assign ADDRC3 = ADDRC[3];
assign ADDRC4 = ADDRC[4];
assign ADDRD0 = ADDRD[0];
assign ADDRD1 = ADDRD[1];
assign ADDRD2 = ADDRD[2];
assign ADDRD3 = ADDRD[3];
assign ADDRD4 = ADDRD[4];
assign DIA0 = DIA[0];
assign DIA1 = DIA[1];
assign DIB0 = DIB[0];
assign DIB1 = DIB[1];
assign DIC0 = DIC[0];
assign DIC1 = DIC[1];
assign DID0 = DID[0];
assign DID1 = DID[1];
assign DOA[1] = DOA1;
assign DOA[0] = DOA0;
assign DOB[1] = DOB1;
assign DOB[0] = DOB0;
assign DOC[1] = DOC1;
assign DOC[0] = DOC0;
assign DOD[1] = DOD1;
assign DOD[0] = DOD0;
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMA
(.CLK(WCLK),
.I(DIA0),
.O(DOA0),
.RADR0(ADDRA0),
.RADR1(ADDRA1),
.RADR2(ADDRA2),
.RADR3(ADDRA3),
.RADR4(ADDRA4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMA_D1
(.CLK(WCLK),
.I(DIA1),
.O(DOA1),
.RADR0(ADDRA0),
.RADR1(ADDRA1),
.RADR2(ADDRA2),
.RADR3(ADDRA3),
.RADR4(ADDRA4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMB
(.CLK(WCLK),
.I(DIB0),
.O(DOB0),
.RADR0(ADDRB0),
.RADR1(ADDRB1),
.RADR2(ADDRB2),
.RADR3(ADDRB3),
.RADR4(ADDRB4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMB_D1
(.CLK(WCLK),
.I(DIB1),
.O(DOB1),
.RADR0(ADDRB0),
.RADR1(ADDRB1),
.RADR2(ADDRB2),
.RADR3(ADDRB3),
.RADR4(ADDRB4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMC
(.CLK(WCLK),
.I(DIC0),
.O(DOC0),
.RADR0(ADDRC0),
.RADR1(ADDRC1),
.RADR2(ADDRC2),
.RADR3(ADDRC3),
.RADR4(ADDRC4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMC_D1
(.CLK(WCLK),
.I(DIC1),
.O(DOC1),
.RADR0(ADDRC0),
.RADR1(ADDRC1),
.RADR2(ADDRC2),
.RADR3(ADDRC3),
.RADR4(ADDRC4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMS32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMD
(.ADR0(ADDRD0),
.ADR1(ADDRD1),
.ADR2(ADDRD2),
.ADR3(ADDRD3),
.ADR4(ADDRD4),
.CLK(WCLK),
.I(DID0),
.O(DOD0),
.WE(WE));
RAMS32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMD_D1
(.ADR0(ADDRD0),
.ADR1(ADDRD1),
.ADR2(ADDRD2),
.ADR3(ADDRD3),
.ADR4(ADDRD4),
.CLK(WCLK),
.I(DID1),
.O(DOD1),
.WE(WE));
endmodule
|
module RAM32M_HD8
(DOA,
DOB,
DOC,
DOD,
ADDRA,
ADDRB,
ADDRC,
ADDRD,
DIA,
DIB,
DIC,
DID,
WCLK,
WE);
output [1:0]DOA;
output [1:0]DOB;
output [1:0]DOC;
output [1:0]DOD;
input [4:0]ADDRA;
input [4:0]ADDRB;
input [4:0]ADDRC;
input [4:0]ADDRD;
input [1:0]DIA;
input [1:0]DIB;
input [1:0]DIC;
input [1:0]DID;
input WCLK;
input WE;
wire ADDRA0;
wire ADDRA1;
wire ADDRA2;
wire ADDRA3;
wire ADDRA4;
wire ADDRB0;
wire ADDRB1;
wire ADDRB2;
wire ADDRB3;
wire ADDRB4;
wire ADDRC0;
wire ADDRC1;
wire ADDRC2;
wire ADDRC3;
wire ADDRC4;
wire ADDRD0;
wire ADDRD1;
wire ADDRD2;
wire ADDRD3;
wire ADDRD4;
wire DIA0;
wire DIA1;
wire DIB0;
wire DIB1;
wire DIC0;
wire DIC1;
wire DID0;
wire DID1;
wire DOA0;
wire DOA1;
wire DOB0;
wire DOB1;
wire DOC0;
wire DOC1;
wire DOD0;
wire DOD1;
wire WCLK;
wire WE;
assign ADDRA0 = ADDRA[0];
assign ADDRA1 = ADDRA[1];
assign ADDRA2 = ADDRA[2];
assign ADDRA3 = ADDRA[3];
assign ADDRA4 = ADDRA[4];
assign ADDRB0 = ADDRB[0];
assign ADDRB1 = ADDRB[1];
assign ADDRB2 = ADDRB[2];
assign ADDRB3 = ADDRB[3];
assign ADDRB4 = ADDRB[4];
assign ADDRC0 = ADDRC[0];
assign ADDRC1 = ADDRC[1];
assign ADDRC2 = ADDRC[2];
assign ADDRC3 = ADDRC[3];
assign ADDRC4 = ADDRC[4];
assign ADDRD0 = ADDRD[0];
assign ADDRD1 = ADDRD[1];
assign ADDRD2 = ADDRD[2];
assign ADDRD3 = ADDRD[3];
assign ADDRD4 = ADDRD[4];
assign DIA0 = DIA[0];
assign DIA1 = DIA[1];
assign DIB0 = DIB[0];
assign DIB1 = DIB[1];
assign DIC0 = DIC[0];
assign DIC1 = DIC[1];
assign DID0 = DID[0];
assign DID1 = DID[1];
assign DOA[1] = DOA1;
assign DOA[0] = DOA0;
assign DOB[1] = DOB1;
assign DOB[0] = DOB0;
assign DOC[1] = DOC1;
assign DOC[0] = DOC0;
assign DOD[1] = DOD1;
assign DOD[0] = DOD0;
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMA
(.CLK(WCLK),
.I(DIA0),
.O(DOA0),
.RADR0(ADDRA0),
.RADR1(ADDRA1),
.RADR2(ADDRA2),
.RADR3(ADDRA3),
.RADR4(ADDRA4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMA_D1
(.CLK(WCLK),
.I(DIA1),
.O(DOA1),
.RADR0(ADDRA0),
.RADR1(ADDRA1),
.RADR2(ADDRA2),
.RADR3(ADDRA3),
.RADR4(ADDRA4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMB
(.CLK(WCLK),
.I(DIB0),
.O(DOB0),
.RADR0(ADDRB0),
.RADR1(ADDRB1),
.RADR2(ADDRB2),
.RADR3(ADDRB3),
.RADR4(ADDRB4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMB_D1
(.CLK(WCLK),
.I(DIB1),
.O(DOB1),
.RADR0(ADDRB0),
.RADR1(ADDRB1),
.RADR2(ADDRB2),
.RADR3(ADDRB3),
.RADR4(ADDRB4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMC
(.CLK(WCLK),
.I(DIC0),
.O(DOC0),
.RADR0(ADDRC0),
.RADR1(ADDRC1),
.RADR2(ADDRC2),
.RADR3(ADDRC3),
.RADR4(ADDRC4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMC_D1
(.CLK(WCLK),
.I(DIC1),
.O(DOC1),
.RADR0(ADDRC0),
.RADR1(ADDRC1),
.RADR2(ADDRC2),
.RADR3(ADDRC3),
.RADR4(ADDRC4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMS32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMD
(.ADR0(ADDRD0),
.ADR1(ADDRD1),
.ADR2(ADDRD2),
.ADR3(ADDRD3),
.ADR4(ADDRD4),
.CLK(WCLK),
.I(DID0),
.O(DOD0),
.WE(WE));
RAMS32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMD_D1
(.ADR0(ADDRD0),
.ADR1(ADDRD1),
.ADR2(ADDRD2),
.ADR3(ADDRD3),
.ADR4(ADDRD4),
.CLK(WCLK),
.I(DID1),
.O(DOD1),
.WE(WE));
endmodule
|
module RAM32M_HD9
(DOA,
DOB,
DOC,
DOD,
ADDRA,
ADDRB,
ADDRC,
ADDRD,
DIA,
DIB,
DIC,
DID,
WCLK,
WE);
output [1:0]DOA;
output [1:0]DOB;
output [1:0]DOC;
output [1:0]DOD;
input [4:0]ADDRA;
input [4:0]ADDRB;
input [4:0]ADDRC;
input [4:0]ADDRD;
input [1:0]DIA;
input [1:0]DIB;
input [1:0]DIC;
input [1:0]DID;
input WCLK;
input WE;
wire ADDRA0;
wire ADDRA1;
wire ADDRA2;
wire ADDRA3;
wire ADDRA4;
wire ADDRB0;
wire ADDRB1;
wire ADDRB2;
wire ADDRB3;
wire ADDRB4;
wire ADDRC0;
wire ADDRC1;
wire ADDRC2;
wire ADDRC3;
wire ADDRC4;
wire ADDRD0;
wire ADDRD1;
wire ADDRD2;
wire ADDRD3;
wire ADDRD4;
wire DIA0;
wire DIA1;
wire DIB0;
wire DIB1;
wire DIC0;
wire DIC1;
wire DID0;
wire DID1;
wire DOA0;
wire DOA1;
wire DOB0;
wire DOB1;
wire DOC0;
wire DOC1;
wire DOD0;
wire DOD1;
wire WCLK;
wire WE;
assign ADDRA0 = ADDRA[0];
assign ADDRA1 = ADDRA[1];
assign ADDRA2 = ADDRA[2];
assign ADDRA3 = ADDRA[3];
assign ADDRA4 = ADDRA[4];
assign ADDRB0 = ADDRB[0];
assign ADDRB1 = ADDRB[1];
assign ADDRB2 = ADDRB[2];
assign ADDRB3 = ADDRB[3];
assign ADDRB4 = ADDRB[4];
assign ADDRC0 = ADDRC[0];
assign ADDRC1 = ADDRC[1];
assign ADDRC2 = ADDRC[2];
assign ADDRC3 = ADDRC[3];
assign ADDRC4 = ADDRC[4];
assign ADDRD0 = ADDRD[0];
assign ADDRD1 = ADDRD[1];
assign ADDRD2 = ADDRD[2];
assign ADDRD3 = ADDRD[3];
assign ADDRD4 = ADDRD[4];
assign DIA0 = DIA[0];
assign DIA1 = DIA[1];
assign DIB0 = DIB[0];
assign DIB1 = DIB[1];
assign DIC0 = DIC[0];
assign DIC1 = DIC[1];
assign DID0 = DID[0];
assign DID1 = DID[1];
assign DOA[1] = DOA1;
assign DOA[0] = DOA0;
assign DOB[1] = DOB1;
assign DOB[0] = DOB0;
assign DOC[1] = DOC1;
assign DOC[0] = DOC0;
assign DOD[1] = DOD1;
assign DOD[0] = DOD0;
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMA
(.CLK(WCLK),
.I(DIA0),
.O(DOA0),
.RADR0(ADDRA0),
.RADR1(ADDRA1),
.RADR2(ADDRA2),
.RADR3(ADDRA3),
.RADR4(ADDRA4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMA_D1
(.CLK(WCLK),
.I(DIA1),
.O(DOA1),
.RADR0(ADDRA0),
.RADR1(ADDRA1),
.RADR2(ADDRA2),
.RADR3(ADDRA3),
.RADR4(ADDRA4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMB
(.CLK(WCLK),
.I(DIB0),
.O(DOB0),
.RADR0(ADDRB0),
.RADR1(ADDRB1),
.RADR2(ADDRB2),
.RADR3(ADDRB3),
.RADR4(ADDRB4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMB_D1
(.CLK(WCLK),
.I(DIB1),
.O(DOB1),
.RADR0(ADDRB0),
.RADR1(ADDRB1),
.RADR2(ADDRB2),
.RADR3(ADDRB3),
.RADR4(ADDRB4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMC
(.CLK(WCLK),
.I(DIC0),
.O(DOC0),
.RADR0(ADDRC0),
.RADR1(ADDRC1),
.RADR2(ADDRC2),
.RADR3(ADDRC3),
.RADR4(ADDRC4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMC_D1
(.CLK(WCLK),
.I(DIC1),
.O(DOC1),
.RADR0(ADDRC0),
.RADR1(ADDRC1),
.RADR2(ADDRC2),
.RADR3(ADDRC3),
.RADR4(ADDRC4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMS32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMD
(.ADR0(ADDRD0),
.ADR1(ADDRD1),
.ADR2(ADDRD2),
.ADR3(ADDRD3),
.ADR4(ADDRD4),
.CLK(WCLK),
.I(DID0),
.O(DOD0),
.WE(WE));
RAMS32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMD_D1
(.ADR0(ADDRD0),
.ADR1(ADDRD1),
.ADR2(ADDRD2),
.ADR3(ADDRD3),
.ADR4(ADDRD4),
.CLK(WCLK),
.I(DID1),
.O(DOD1),
.WE(WE));
endmodule
|
module VIDEO_TIME_GEN
(\PIXCOL_DEL_reg[0] ,
\PIXCOL_DEL_reg[1] ,
\PIXCOL_DEL_reg[2] ,
ADDRBWRADDR,
\PIXROW_DEL_reg[0] ,
\PIXROW_DEL_reg[1] ,
D,
HSYNCH_DEL_reg,
VSYNCH_DEL_reg,
BLANK,
ETH_CLK_OBUF,
INTERNAL_RST_reg);
output \PIXCOL_DEL_reg[0] ;
output \PIXCOL_DEL_reg[1] ;
output \PIXCOL_DEL_reg[2] ;
output [12:0]ADDRBWRADDR;
output \PIXROW_DEL_reg[0] ;
output \PIXROW_DEL_reg[1] ;
output [0:0]D;
output HSYNCH_DEL_reg;
output VSYNCH_DEL_reg;
output BLANK;
input ETH_CLK_OBUF;
input INTERNAL_RST_reg;
wire [12:0]ADDRBWRADDR;
wire BLANK;
wire \COL_ADDRESS[0]_i_1_n_0 ;
wire \COL_ADDRESS[1]_i_1_n_0 ;
wire \COL_ADDRESS[2]_i_1_n_0 ;
wire \COL_ADDRESS[3]_i_1_n_0 ;
wire \COL_ADDRESS[4]_i_1_n_0 ;
wire \COL_ADDRESS[5]_i_1_n_0 ;
wire \COL_ADDRESS[6]_i_1_n_0 ;
wire \COL_ADDRESS[6]_i_2_n_0 ;
wire \COL_ADDRESS[6]_i_3_n_0 ;
wire \COL_ADDRESS_reg_n_0_[1] ;
wire \COL_ADDRESS_reg_n_0_[2] ;
wire \COL_ADDRESS_reg_n_0_[3] ;
wire \COL_ADDRESS_reg_n_0_[4] ;
wire \COL_ADDRESS_reg_n_0_[5] ;
wire \COL_ADDRESS_reg_n_0_[6] ;
wire [0:0]D;
wire ETH_CLK_OBUF;
wire HBLANK_i_1_n_0;
wire HBLANK_i_2_n_0;
wire HBLANK_i_3_n_0;
wire HBLANK_i_4_n_0;
wire HBLANK_i_5_n_0;
wire HBLANK_i_6_n_0;
wire HBLANK_reg_n_0;
wire HSYNCH_DEL_reg;
wire [10:0]HTIMER;
wire \HTIMER[0]_i_2_n_0 ;
wire \HTIMER[0]_i_3_n_0 ;
wire \HTIMER[10]_i_2_n_0 ;
wire \HTIMER[10]_i_3_n_0 ;
wire \HTIMER[10]_i_4_n_0 ;
wire \HTIMER[2]_i_1_n_0 ;
wire \HTIMER[4]_i_2_n_0 ;
wire \HTIMER[5]_i_1_n_0 ;
wire \HTIMER[6]_i_1_n_0 ;
wire \HTIMER[9]_i_2_n_0 ;
wire INTERNAL_RST_reg;
wire INTHSYNCH_i_1_n_0;
wire INTVSYNCH2_out;
wire INTVSYNCH_i_1_n_0;
wire INTVSYNCH_i_3_n_0;
wire MEMORY_reg_0_i_11_n_0;
wire MEMORY_reg_0_i_12_n_0;
wire MEMORY_reg_0_i_13_n_0;
wire MEMORY_reg_0_i_14_n_0;
wire MEMORY_reg_0_i_15_n_0;
wire MEMORY_reg_0_i_16_n_0;
wire MEMORY_reg_0_i_2_n_0;
wire MEMORY_reg_0_i_3_n_0;
wire \PIXCOL_DEL_reg[0] ;
wire \PIXCOL_DEL_reg[1] ;
wire \PIXCOL_DEL_reg[2] ;
wire \PIXROW_DEL_reg[0] ;
wire \PIXROW_DEL_reg[1] ;
wire \PIX_COL_ADDRESS[0]_i_1_n_0 ;
wire \PIX_COL_ADDRESS[1]_i_1_n_0 ;
wire \PIX_COL_ADDRESS[2]_i_1_n_0 ;
wire \PIX_ROW_ADDRESS[0]_i_1_n_0 ;
wire \PIX_ROW_ADDRESS[1]_i_1_n_0 ;
wire \PIX_ROW_ADDRESS[2]_i_1_n_0 ;
wire \PIX_ROW_ADDRESS[2]_i_2_n_0 ;
wire \PIX_ROW_ADDRESS[2]_i_3_n_0 ;
wire [12:1]ROW_ADDRESS;
wire \ROW_ADDRESS[12]_i_1_n_0 ;
wire \ROW_ADDRESS[12]_i_3_n_0 ;
wire \ROW_ADDRESS[12]_i_4_n_0 ;
wire \ROW_ADDRESS[4]_i_5_n_0 ;
wire \ROW_ADDRESS[8]_i_5_n_0 ;
wire \ROW_ADDRESS[8]_i_6_n_0 ;
wire [12:1]ROW_ADDRESS_0;
wire \ROW_ADDRESS_reg[12]_i_5_n_4 ;
wire \ROW_ADDRESS_reg[12]_i_5_n_5 ;
wire \ROW_ADDRESS_reg[12]_i_5_n_6 ;
wire \ROW_ADDRESS_reg[12]_i_5_n_7 ;
wire \ROW_ADDRESS_reg[4]_i_2_n_0 ;
wire \ROW_ADDRESS_reg[4]_i_2_n_4 ;
wire \ROW_ADDRESS_reg[4]_i_2_n_5 ;
wire \ROW_ADDRESS_reg[4]_i_2_n_6 ;
wire \ROW_ADDRESS_reg[4]_i_2_n_7 ;
wire \ROW_ADDRESS_reg[8]_i_2_n_0 ;
wire \ROW_ADDRESS_reg[8]_i_2_n_4 ;
wire \ROW_ADDRESS_reg[8]_i_2_n_5 ;
wire \ROW_ADDRESS_reg[8]_i_2_n_6 ;
wire \ROW_ADDRESS_reg[8]_i_2_n_7 ;
wire VBLANK_i_1_n_0;
wire VBLANK_i_2_n_0;
wire VBLANK_i_3_n_0;
wire VBLANK_i_4_n_0;
wire VBLANK_i_5_n_0;
wire VBLANK_i_6_n_0;
wire VBLANK_i_7_n_0;
wire VBLANK_reg_n_0;
wire VSYNCH_DEL_reg;
wire [9:0]VTIMER;
wire \VTIMER[0]_i_1_n_0 ;
wire \VTIMER[2]_i_2_n_0 ;
wire \VTIMER[2]_i_3_n_0 ;
wire \VTIMER[5]_i_1_n_0 ;
wire \VTIMER[9]_i_2_n_0 ;
wire \VTIMER[9]_i_3_n_0 ;
wire \VTIMER[9]_i_4_n_0 ;
wire \VTIMER[9]_i_5_n_0 ;
wire [9:1]VTIMER_1;
wire VTIMER_EN;
wire VTIMER_EN_i_1_n_0;
wire [10:0]sel0;
wire [3:0]NLW_MEMORY_reg_0_i_1_CO_UNCONNECTED;
wire [2:0]NLW_MEMORY_reg_0_i_2_CO_UNCONNECTED;
wire [2:0]NLW_MEMORY_reg_0_i_3_CO_UNCONNECTED;
wire [0:0]NLW_MEMORY_reg_0_i_3_O_UNCONNECTED;
wire [3:0]\NLW_ROW_ADDRESS_reg[12]_i_5_CO_UNCONNECTED ;
wire [2:0]\NLW_ROW_ADDRESS_reg[4]_i_2_CO_UNCONNECTED ;
wire [2:0]\NLW_ROW_ADDRESS_reg[8]_i_2_CO_UNCONNECTED ;
LUT2 #(
.INIT(4'hE))
BLANK_DEL_i_1
(.I0(VBLANK_reg_n_0),
.I1(HBLANK_reg_n_0),
.O(BLANK));
LUT1 #(
.INIT(2'h1))
\COL_ADDRESS[0]_i_1
(.I0(ADDRBWRADDR[0]),
.O(\COL_ADDRESS[0]_i_1_n_0 ));
LUT2 #(
.INIT(4'h6))
\COL_ADDRESS[1]_i_1
(.I0(\COL_ADDRESS_reg_n_0_[1] ),
.I1(ADDRBWRADDR[0]),
.O(\COL_ADDRESS[1]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFFF00000000EFFF))
\COL_ADDRESS[2]_i_1
(.I0(\COL_ADDRESS_reg_n_0_[4] ),
.I1(\COL_ADDRESS_reg_n_0_[3] ),
.I2(\COL_ADDRESS_reg_n_0_[6] ),
.I3(\COL_ADDRESS_reg_n_0_[5] ),
.I4(\COL_ADDRESS[6]_i_3_n_0 ),
.I5(\COL_ADDRESS_reg_n_0_[2] ),
.O(\COL_ADDRESS[2]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT4 #(
.INIT(16'h6AAA))
\COL_ADDRESS[3]_i_1
(.I0(\COL_ADDRESS_reg_n_0_[3] ),
.I1(\COL_ADDRESS_reg_n_0_[1] ),
.I2(ADDRBWRADDR[0]),
.I3(\COL_ADDRESS_reg_n_0_[2] ),
.O(\COL_ADDRESS[3]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT5 #(
.INIT(32'h6AAAAAAA))
\COL_ADDRESS[4]_i_1
(.I0(\COL_ADDRESS_reg_n_0_[4] ),
.I1(\COL_ADDRESS_reg_n_0_[2] ),
.I2(ADDRBWRADDR[0]),
.I3(\COL_ADDRESS_reg_n_0_[1] ),
.I4(\COL_ADDRESS_reg_n_0_[3] ),
.O(\COL_ADDRESS[4]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFF3FFFFD00C00000))
\COL_ADDRESS[5]_i_1
(.I0(\COL_ADDRESS_reg_n_0_[6] ),
.I1(\COL_ADDRESS_reg_n_0_[4] ),
.I2(\COL_ADDRESS_reg_n_0_[2] ),
.I3(\COL_ADDRESS[6]_i_3_n_0 ),
.I4(\COL_ADDRESS_reg_n_0_[3] ),
.I5(\COL_ADDRESS_reg_n_0_[5] ),
.O(\COL_ADDRESS[5]_i_1_n_0 ));
LUT5 #(
.INIT(32'h00000080))
\COL_ADDRESS[6]_i_1
(.I0(\PIXCOL_DEL_reg[0] ),
.I1(\PIXCOL_DEL_reg[1] ),
.I2(\PIXCOL_DEL_reg[2] ),
.I3(HBLANK_reg_n_0),
.I4(VBLANK_reg_n_0),
.O(\COL_ADDRESS[6]_i_1_n_0 ));
LUT6 #(
.INIT(64'hDFFEFFFF20000000))
\COL_ADDRESS[6]_i_2
(.I0(\COL_ADDRESS_reg_n_0_[3] ),
.I1(\COL_ADDRESS[6]_i_3_n_0 ),
.I2(\COL_ADDRESS_reg_n_0_[2] ),
.I3(\COL_ADDRESS_reg_n_0_[4] ),
.I4(\COL_ADDRESS_reg_n_0_[5] ),
.I5(\COL_ADDRESS_reg_n_0_[6] ),
.O(\COL_ADDRESS[6]_i_2_n_0 ));
LUT2 #(
.INIT(4'h7))
\COL_ADDRESS[6]_i_3
(.I0(\COL_ADDRESS_reg_n_0_[1] ),
.I1(ADDRBWRADDR[0]),
.O(\COL_ADDRESS[6]_i_3_n_0 ));
FDRE \COL_ADDRESS_reg[0]
(.C(ETH_CLK_OBUF),
.CE(\COL_ADDRESS[6]_i_1_n_0 ),
.D(\COL_ADDRESS[0]_i_1_n_0 ),
.Q(ADDRBWRADDR[0]),
.R(INTERNAL_RST_reg));
FDRE \COL_ADDRESS_reg[1]
(.C(ETH_CLK_OBUF),
.CE(\COL_ADDRESS[6]_i_1_n_0 ),
.D(\COL_ADDRESS[1]_i_1_n_0 ),
.Q(\COL_ADDRESS_reg_n_0_[1] ),
.R(INTERNAL_RST_reg));
FDRE \COL_ADDRESS_reg[2]
(.C(ETH_CLK_OBUF),
.CE(\COL_ADDRESS[6]_i_1_n_0 ),
.D(\COL_ADDRESS[2]_i_1_n_0 ),
.Q(\COL_ADDRESS_reg_n_0_[2] ),
.R(INTERNAL_RST_reg));
FDRE \COL_ADDRESS_reg[3]
(.C(ETH_CLK_OBUF),
.CE(\COL_ADDRESS[6]_i_1_n_0 ),
.D(\COL_ADDRESS[3]_i_1_n_0 ),
.Q(\COL_ADDRESS_reg_n_0_[3] ),
.R(INTERNAL_RST_reg));
FDRE \COL_ADDRESS_reg[4]
(.C(ETH_CLK_OBUF),
.CE(\COL_ADDRESS[6]_i_1_n_0 ),
.D(\COL_ADDRESS[4]_i_1_n_0 ),
.Q(\COL_ADDRESS_reg_n_0_[4] ),
.R(INTERNAL_RST_reg));
FDRE \COL_ADDRESS_reg[5]
(.C(ETH_CLK_OBUF),
.CE(\COL_ADDRESS[6]_i_1_n_0 ),
.D(\COL_ADDRESS[5]_i_1_n_0 ),
.Q(\COL_ADDRESS_reg_n_0_[5] ),
.R(INTERNAL_RST_reg));
FDRE \COL_ADDRESS_reg[6]
(.C(ETH_CLK_OBUF),
.CE(\COL_ADDRESS[6]_i_1_n_0 ),
.D(\COL_ADDRESS[6]_i_2_n_0 ),
.Q(\COL_ADDRESS_reg_n_0_[6] ),
.R(INTERNAL_RST_reg));
LUT6 #(
.INIT(64'hFFFFFFFFFFF70000))
HBLANK_i_1
(.I0(HBLANK_i_2_n_0),
.I1(sel0[7]),
.I2(sel0[8]),
.I3(sel0[6]),
.I4(HBLANK_reg_n_0),
.I5(HBLANK_i_3_n_0),
.O(HBLANK_i_1_n_0));
LUT6 #(
.INIT(64'h0000000010000000))
HBLANK_i_2
(.I0(sel0[9]),
.I1(sel0[10]),
.I2(sel0[5]),
.I3(sel0[4]),
.I4(sel0[3]),
.I5(HBLANK_i_4_n_0),
.O(HBLANK_i_2_n_0));
LUT6 #(
.INIT(64'hAAAAABAAAAAAAAAA))
HBLANK_i_3
(.I0(INTERNAL_RST_reg),
.I1(HBLANK_i_5_n_0),
.I2(sel0[0]),
.I3(sel0[3]),
.I4(HBLANK_i_6_n_0),
.I5(\HTIMER[0]_i_3_n_0 ),
.O(HBLANK_i_3_n_0));
LUT3 #(
.INIT(8'hFE))
HBLANK_i_4
(.I0(sel0[2]),
.I1(sel0[1]),
.I2(sel0[0]),
.O(HBLANK_i_4_n_0));
LUT3 #(
.INIT(8'hBF))
HBLANK_i_5
(.I0(sel0[10]),
.I1(sel0[8]),
.I2(sel0[9]),
.O(HBLANK_i_5_n_0));
LUT2 #(
.INIT(4'h7))
HBLANK_i_6
(.I0(sel0[7]),
.I1(sel0[6]),
.O(HBLANK_i_6_n_0));
FDRE HBLANK_reg
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(HBLANK_i_1_n_0),
.Q(HBLANK_reg_n_0),
.R(1'b0));
LUT5 #(
.INIT(32'h0000FDFF))
\HTIMER[0]_i_1
(.I0(\HTIMER[0]_i_2_n_0 ),
.I1(sel0[6]),
.I2(sel0[3]),
.I3(\HTIMER[0]_i_3_n_0 ),
.I4(sel0[0]),
.O(HTIMER[0]));
LUT4 #(
.INIT(16'h0010))
\HTIMER[0]_i_2
(.I0(sel0[8]),
.I1(sel0[7]),
.I2(sel0[10]),
.I3(sel0[9]),
.O(\HTIMER[0]_i_2_n_0 ));
LUT4 #(
.INIT(16'h0010))
\HTIMER[0]_i_3
(.I0(sel0[2]),
.I1(sel0[1]),
.I2(sel0[4]),
.I3(sel0[5]),
.O(\HTIMER[0]_i_3_n_0 ));
LUT5 #(
.INIT(32'h3AAAAAAA))
\HTIMER[10]_i_1
(.I0(\HTIMER[10]_i_2_n_0 ),
.I1(sel0[10]),
.I2(sel0[8]),
.I3(sel0[9]),
.I4(\HTIMER[10]_i_3_n_0 ),
.O(HTIMER[10]));
LUT6 #(
.INIT(64'hAAAAAAA8AAAAAAAA))
\HTIMER[10]_i_2
(.I0(sel0[10]),
.I1(sel0[8]),
.I2(sel0[6]),
.I3(sel0[9]),
.I4(sel0[7]),
.I5(\HTIMER[10]_i_4_n_0 ),
.O(\HTIMER[10]_i_2_n_0 ));
LUT3 #(
.INIT(8'h40))
\HTIMER[10]_i_3
(.I0(\HTIMER[9]_i_2_n_0 ),
.I1(sel0[6]),
.I2(sel0[7]),
.O(\HTIMER[10]_i_3_n_0 ));
LUT6 #(
.INIT(64'h0000000000000010))
\HTIMER[10]_i_4
(.I0(sel0[5]),
.I1(sel0[3]),
.I2(sel0[4]),
.I3(sel0[2]),
.I4(sel0[1]),
.I5(sel0[0]),
.O(\HTIMER[10]_i_4_n_0 ));
LUT2 #(
.INIT(4'h6))
\HTIMER[1]_i_1
(.I0(sel0[0]),
.I1(sel0[1]),
.O(HTIMER[1]));
(* SOFT_HLUTNM = "soft_lutpair8" *)
LUT3 #(
.INIT(8'h6A))
\HTIMER[2]_i_1
(.I0(sel0[2]),
.I1(sel0[1]),
.I2(sel0[0]),
.O(\HTIMER[2]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair8" *)
LUT4 #(
.INIT(16'h6AAA))
\HTIMER[3]_i_1
(.I0(sel0[3]),
.I1(sel0[1]),
.I2(sel0[0]),
.I3(sel0[2]),
.O(HTIMER[3]));
LUT6 #(
.INIT(64'h1555555540000000))
\HTIMER[4]_i_1
(.I0(\HTIMER[4]_i_2_n_0 ),
.I1(sel0[2]),
.I2(sel0[0]),
.I3(sel0[1]),
.I4(sel0[3]),
.I5(sel0[4]),
.O(HTIMER[4]));
LUT6 #(
.INIT(64'h0000000000000200))
\HTIMER[4]_i_2
(.I0(\HTIMER[10]_i_4_n_0 ),
.I1(sel0[8]),
.I2(sel0[7]),
.I3(sel0[10]),
.I4(sel0[9]),
.I5(sel0[6]),
.O(\HTIMER[4]_i_2_n_0 ));
LUT6 #(
.INIT(64'h6AAAAAAAAAAAAAAA))
\HTIMER[5]_i_1
(.I0(sel0[5]),
.I1(sel0[4]),
.I2(sel0[3]),
.I3(sel0[1]),
.I4(sel0[0]),
.I5(sel0[2]),
.O(\HTIMER[5]_i_1_n_0 ));
LUT2 #(
.INIT(4'h9))
\HTIMER[6]_i_1
(.I0(sel0[6]),
.I1(\HTIMER[9]_i_2_n_0 ),
.O(\HTIMER[6]_i_1_n_0 ));
LUT3 #(
.INIT(8'h9A))
\HTIMER[7]_i_1
(.I0(sel0[7]),
.I1(\HTIMER[9]_i_2_n_0 ),
.I2(sel0[6]),
.O(HTIMER[7]));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT4 #(
.INIT(16'hAA6A))
\HTIMER[8]_i_1
(.I0(sel0[8]),
.I1(sel0[7]),
.I2(sel0[6]),
.I3(\HTIMER[9]_i_2_n_0 ),
.O(HTIMER[8]));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT5 #(
.INIT(32'h9AAAAAAA))
\HTIMER[9]_i_1
(.I0(sel0[9]),
.I1(\HTIMER[9]_i_2_n_0 ),
.I2(sel0[6]),
.I3(sel0[7]),
.I4(sel0[8]),
.O(HTIMER[9]));
LUT6 #(
.INIT(64'h7FFFFFFFFFFFFFFF))
\HTIMER[9]_i_2
(.I0(sel0[4]),
.I1(sel0[3]),
.I2(sel0[1]),
.I3(sel0[0]),
.I4(sel0[2]),
.I5(sel0[5]),
.O(\HTIMER[9]_i_2_n_0 ));
FDRE \HTIMER_reg[0]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(HTIMER[0]),
.Q(sel0[0]),
.R(INTERNAL_RST_reg));
FDRE \HTIMER_reg[10]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(HTIMER[10]),
.Q(sel0[10]),
.R(INTERNAL_RST_reg));
FDRE \HTIMER_reg[1]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(HTIMER[1]),
.Q(sel0[1]),
.R(INTERNAL_RST_reg));
FDRE \HTIMER_reg[2]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(\HTIMER[2]_i_1_n_0 ),
.Q(sel0[2]),
.R(INTERNAL_RST_reg));
FDRE \HTIMER_reg[3]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(HTIMER[3]),
.Q(sel0[3]),
.R(INTERNAL_RST_reg));
FDRE \HTIMER_reg[4]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(HTIMER[4]),
.Q(sel0[4]),
.R(INTERNAL_RST_reg));
FDRE \HTIMER_reg[5]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(\HTIMER[5]_i_1_n_0 ),
.Q(sel0[5]),
.R(INTERNAL_RST_reg));
FDRE \HTIMER_reg[6]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(\HTIMER[6]_i_1_n_0 ),
.Q(sel0[6]),
.R(INTERNAL_RST_reg));
FDRE \HTIMER_reg[7]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(HTIMER[7]),
.Q(sel0[7]),
.R(INTERNAL_RST_reg));
FDRE \HTIMER_reg[8]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(HTIMER[8]),
.Q(sel0[8]),
.R(INTERNAL_RST_reg));
FDRE \HTIMER_reg[9]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(HTIMER[9]),
.Q(sel0[9]),
.R(INTERNAL_RST_reg));
LUT6 #(
.INIT(64'h00000000AAAEAAAA))
INTHSYNCH_i_1
(.I0(HSYNCH_DEL_reg),
.I1(HBLANK_i_2_n_0),
.I2(sel0[7]),
.I3(sel0[8]),
.I4(sel0[6]),
.I5(VTIMER_EN_i_1_n_0),
.O(INTHSYNCH_i_1_n_0));
FDRE INTHSYNCH_reg
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(INTHSYNCH_i_1_n_0),
.Q(HSYNCH_DEL_reg),
.R(1'b0));
LUT6 #(
.INIT(64'h00000000EEEE0EEE))
INTVSYNCH_i_1
(.I0(VSYNCH_DEL_reg),
.I1(INTVSYNCH2_out),
.I2(\VTIMER[2]_i_2_n_0 ),
.I3(VTIMER_EN),
.I4(VTIMER[0]),
.I5(INTERNAL_RST_reg),
.O(INTVSYNCH_i_1_n_0));
LUT6 #(
.INIT(64'h0000000000000002))
INTVSYNCH_i_2
(.I0(VBLANK_i_2_n_0),
.I1(VTIMER[0]),
.I2(INTVSYNCH_i_3_n_0),
.I3(VTIMER[3]),
.I4(VTIMER[5]),
.I5(VTIMER[4]),
.O(INTVSYNCH2_out));
LUT2 #(
.INIT(4'h7))
INTVSYNCH_i_3
(.I0(VTIMER[1]),
.I1(VTIMER[2]),
.O(INTVSYNCH_i_3_n_0));
FDRE INTVSYNCH_reg
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(INTVSYNCH_i_1_n_0),
.Q(VSYNCH_DEL_reg),
.R(1'b0));
CARRY4 MEMORY_reg_0_i_1
(.CI(MEMORY_reg_0_i_2_n_0),
.CO(NLW_MEMORY_reg_0_i_1_CO_UNCONNECTED[3:0]),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(ADDRBWRADDR[12:9]),
.S(ROW_ADDRESS[12:9]));
LUT2 #(
.INIT(4'h6))
MEMORY_reg_0_i_11
(.I0(ROW_ADDRESS[6]),
.I1(\COL_ADDRESS_reg_n_0_[6] ),
.O(MEMORY_reg_0_i_11_n_0));
LUT2 #(
.INIT(4'h6))
MEMORY_reg_0_i_12
(.I0(ROW_ADDRESS[5]),
.I1(\COL_ADDRESS_reg_n_0_[5] ),
.O(MEMORY_reg_0_i_12_n_0));
LUT2 #(
.INIT(4'h6))
MEMORY_reg_0_i_13
(.I0(ROW_ADDRESS[4]),
.I1(\COL_ADDRESS_reg_n_0_[4] ),
.O(MEMORY_reg_0_i_13_n_0));
LUT2 #(
.INIT(4'h6))
MEMORY_reg_0_i_14
(.I0(ROW_ADDRESS[3]),
.I1(\COL_ADDRESS_reg_n_0_[3] ),
.O(MEMORY_reg_0_i_14_n_0));
LUT2 #(
.INIT(4'h6))
MEMORY_reg_0_i_15
(.I0(ROW_ADDRESS[2]),
.I1(\COL_ADDRESS_reg_n_0_[2] ),
.O(MEMORY_reg_0_i_15_n_0));
LUT2 #(
.INIT(4'h6))
MEMORY_reg_0_i_16
(.I0(ROW_ADDRESS[1]),
.I1(\COL_ADDRESS_reg_n_0_[1] ),
.O(MEMORY_reg_0_i_16_n_0));
CARRY4 MEMORY_reg_0_i_2
(.CI(MEMORY_reg_0_i_3_n_0),
.CO({MEMORY_reg_0_i_2_n_0,NLW_MEMORY_reg_0_i_2_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b0),
.DI({1'b0,1'b0,ROW_ADDRESS[6:5]}),
.O(ADDRBWRADDR[8:5]),
.S({ROW_ADDRESS[8:7],MEMORY_reg_0_i_11_n_0,MEMORY_reg_0_i_12_n_0}));
CARRY4 MEMORY_reg_0_i_3
(.CI(1'b0),
.CO({MEMORY_reg_0_i_3_n_0,NLW_MEMORY_reg_0_i_3_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b0),
.DI(ROW_ADDRESS[4:1]),
.O({ADDRBWRADDR[4:2],NLW_MEMORY_reg_0_i_3_O_UNCONNECTED[0]}),
.S({MEMORY_reg_0_i_13_n_0,MEMORY_reg_0_i_14_n_0,MEMORY_reg_0_i_15_n_0,MEMORY_reg_0_i_16_n_0}));
LUT2 #(
.INIT(4'h6))
MEMORY_reg_0_i_4
(.I0(ROW_ADDRESS[1]),
.I1(\COL_ADDRESS_reg_n_0_[1] ),
.O(ADDRBWRADDR[1]));
LUT3 #(
.INIT(8'hE1))
\PIX_COL_ADDRESS[0]_i_1
(.I0(VBLANK_reg_n_0),
.I1(HBLANK_reg_n_0),
.I2(\PIXCOL_DEL_reg[0] ),
.O(\PIX_COL_ADDRESS[0]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT4 #(
.INIT(16'hFD02))
\PIX_COL_ADDRESS[1]_i_1
(.I0(\PIXCOL_DEL_reg[0] ),
.I1(HBLANK_reg_n_0),
.I2(VBLANK_reg_n_0),
.I3(\PIXCOL_DEL_reg[1] ),
.O(\PIX_COL_ADDRESS[1]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT5 #(
.INIT(32'hFFF70008))
\PIX_COL_ADDRESS[2]_i_1
(.I0(\PIXCOL_DEL_reg[0] ),
.I1(\PIXCOL_DEL_reg[1] ),
.I2(HBLANK_reg_n_0),
.I3(VBLANK_reg_n_0),
.I4(\PIXCOL_DEL_reg[2] ),
.O(\PIX_COL_ADDRESS[2]_i_1_n_0 ));
FDRE \PIX_COL_ADDRESS_reg[0]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(\PIX_COL_ADDRESS[0]_i_1_n_0 ),
.Q(\PIXCOL_DEL_reg[0] ),
.R(INTERNAL_RST_reg));
FDRE \PIX_COL_ADDRESS_reg[1]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(\PIX_COL_ADDRESS[1]_i_1_n_0 ),
.Q(\PIXCOL_DEL_reg[1] ),
.R(INTERNAL_RST_reg));
FDRE \PIX_COL_ADDRESS_reg[2]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(\PIX_COL_ADDRESS[2]_i_1_n_0 ),
.Q(\PIXCOL_DEL_reg[2] ),
.R(INTERNAL_RST_reg));
LUT2 #(
.INIT(4'h6))
\PIX_ROW_ADDRESS[0]_i_1
(.I0(\PIX_ROW_ADDRESS[2]_i_2_n_0 ),
.I1(\PIXROW_DEL_reg[0] ),
.O(\PIX_ROW_ADDRESS[0]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT3 #(
.INIT(8'h78))
\PIX_ROW_ADDRESS[1]_i_1
(.I0(\PIXROW_DEL_reg[0] ),
.I1(\PIX_ROW_ADDRESS[2]_i_2_n_0 ),
.I2(\PIXROW_DEL_reg[1] ),
.O(\PIX_ROW_ADDRESS[1]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT4 #(
.INIT(16'h7F80))
\PIX_ROW_ADDRESS[2]_i_1
(.I0(\PIXROW_DEL_reg[0] ),
.I1(\PIXROW_DEL_reg[1] ),
.I2(\PIX_ROW_ADDRESS[2]_i_2_n_0 ),
.I3(D),
.O(\PIX_ROW_ADDRESS[2]_i_1_n_0 ));
LUT6 #(
.INIT(64'h0000000010000000))
\PIX_ROW_ADDRESS[2]_i_2
(.I0(VBLANK_reg_n_0),
.I1(HBLANK_reg_n_0),
.I2(\PIXCOL_DEL_reg[2] ),
.I3(\PIXCOL_DEL_reg[1] ),
.I4(\PIXCOL_DEL_reg[0] ),
.I5(\PIX_ROW_ADDRESS[2]_i_3_n_0 ),
.O(\PIX_ROW_ADDRESS[2]_i_2_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFFFFFF7))
\PIX_ROW_ADDRESS[2]_i_3
(.I0(\COL_ADDRESS_reg_n_0_[5] ),
.I1(\COL_ADDRESS_reg_n_0_[6] ),
.I2(\COL_ADDRESS_reg_n_0_[2] ),
.I3(\COL_ADDRESS_reg_n_0_[3] ),
.I4(\COL_ADDRESS_reg_n_0_[4] ),
.I5(\COL_ADDRESS[6]_i_3_n_0 ),
.O(\PIX_ROW_ADDRESS[2]_i_3_n_0 ));
FDRE \PIX_ROW_ADDRESS_reg[0]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(\PIX_ROW_ADDRESS[0]_i_1_n_0 ),
.Q(\PIXROW_DEL_reg[0] ),
.R(INTERNAL_RST_reg));
FDRE \PIX_ROW_ADDRESS_reg[1]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(\PIX_ROW_ADDRESS[1]_i_1_n_0 ),
.Q(\PIXROW_DEL_reg[1] ),
.R(INTERNAL_RST_reg));
FDRE \PIX_ROW_ADDRESS_reg[2]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(\PIX_ROW_ADDRESS[2]_i_1_n_0 ),
.Q(D),
.R(INTERNAL_RST_reg));
(* SOFT_HLUTNM = "soft_lutpair17" *)
LUT3 #(
.INIT(8'h70))
\ROW_ADDRESS[10]_i_1
(.I0(\ROW_ADDRESS[12]_i_3_n_0 ),
.I1(\ROW_ADDRESS[12]_i_4_n_0 ),
.I2(\ROW_ADDRESS_reg[12]_i_5_n_6 ),
.O(ROW_ADDRESS_0[10]));
(* SOFT_HLUTNM = "soft_lutpair16" *)
LUT3 #(
.INIT(8'h70))
\ROW_ADDRESS[11]_i_1
(.I0(\ROW_ADDRESS[12]_i_3_n_0 ),
.I1(\ROW_ADDRESS[12]_i_4_n_0 ),
.I2(\ROW_ADDRESS_reg[12]_i_5_n_5 ),
.O(ROW_ADDRESS_0[11]));
LUT4 #(
.INIT(16'h8000))
\ROW_ADDRESS[12]_i_1
(.I0(\PIX_ROW_ADDRESS[2]_i_2_n_0 ),
.I1(D),
.I2(\PIXROW_DEL_reg[0] ),
.I3(\PIXROW_DEL_reg[1] ),
.O(\ROW_ADDRESS[12]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair15" *)
LUT3 #(
.INIT(8'h70))
\ROW_ADDRESS[12]_i_2
(.I0(\ROW_ADDRESS[12]_i_3_n_0 ),
.I1(\ROW_ADDRESS[12]_i_4_n_0 ),
.I2(\ROW_ADDRESS_reg[12]_i_5_n_4 ),
.O(ROW_ADDRESS_0[12]));
LUT6 #(
.INIT(64'h0040000000000000))
\ROW_ADDRESS[12]_i_3
(.I0(ROW_ADDRESS[9]),
.I1(ROW_ADDRESS[10]),
.I2(ROW_ADDRESS[7]),
.I3(ROW_ADDRESS[8]),
.I4(ROW_ADDRESS[11]),
.I5(ROW_ADDRESS[12]),
.O(\ROW_ADDRESS[12]_i_3_n_0 ));
LUT6 #(
.INIT(64'h0000000000000080))
\ROW_ADDRESS[12]_i_4
(.I0(ROW_ADDRESS[6]),
.I1(ROW_ADDRESS[5]),
.I2(ROW_ADDRESS[3]),
.I3(ROW_ADDRESS[4]),
.I4(ROW_ADDRESS[1]),
.I5(ROW_ADDRESS[2]),
.O(\ROW_ADDRESS[12]_i_4_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair15" *)
LUT3 #(
.INIT(8'h70))
\ROW_ADDRESS[1]_i_1
(.I0(\ROW_ADDRESS[12]_i_3_n_0 ),
.I1(\ROW_ADDRESS[12]_i_4_n_0 ),
.I2(\ROW_ADDRESS_reg[4]_i_2_n_7 ),
.O(ROW_ADDRESS_0[1]));
(* SOFT_HLUTNM = "soft_lutpair16" *)
LUT3 #(
.INIT(8'h70))
\ROW_ADDRESS[2]_i_1
(.I0(\ROW_ADDRESS[12]_i_3_n_0 ),
.I1(\ROW_ADDRESS[12]_i_4_n_0 ),
.I2(\ROW_ADDRESS_reg[4]_i_2_n_6 ),
.O(ROW_ADDRESS_0[2]));
(* SOFT_HLUTNM = "soft_lutpair17" *)
LUT3 #(
.INIT(8'h70))
\ROW_ADDRESS[3]_i_1
(.I0(\ROW_ADDRESS[12]_i_3_n_0 ),
.I1(\ROW_ADDRESS[12]_i_4_n_0 ),
.I2(\ROW_ADDRESS_reg[4]_i_2_n_5 ),
.O(ROW_ADDRESS_0[3]));
(* SOFT_HLUTNM = "soft_lutpair19" *)
LUT3 #(
.INIT(8'h70))
\ROW_ADDRESS[4]_i_1
(.I0(\ROW_ADDRESS[12]_i_3_n_0 ),
.I1(\ROW_ADDRESS[12]_i_4_n_0 ),
.I2(\ROW_ADDRESS_reg[4]_i_2_n_4 ),
.O(ROW_ADDRESS_0[4]));
LUT1 #(
.INIT(2'h1))
\ROW_ADDRESS[4]_i_5
(.I0(ROW_ADDRESS[2]),
.O(\ROW_ADDRESS[4]_i_5_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair20" *)
LUT3 #(
.INIT(8'h70))
\ROW_ADDRESS[5]_i_1
(.I0(\ROW_ADDRESS[12]_i_3_n_0 ),
.I1(\ROW_ADDRESS[12]_i_4_n_0 ),
.I2(\ROW_ADDRESS_reg[8]_i_2_n_7 ),
.O(ROW_ADDRESS_0[5]));
(* SOFT_HLUTNM = "soft_lutpair21" *)
LUT3 #(
.INIT(8'h70))
\ROW_ADDRESS[6]_i_1
(.I0(\ROW_ADDRESS[12]_i_3_n_0 ),
.I1(\ROW_ADDRESS[12]_i_4_n_0 ),
.I2(\ROW_ADDRESS_reg[8]_i_2_n_6 ),
.O(ROW_ADDRESS_0[6]));
(* SOFT_HLUTNM = "soft_lutpair21" *)
LUT3 #(
.INIT(8'h70))
\ROW_ADDRESS[7]_i_1
(.I0(\ROW_ADDRESS[12]_i_3_n_0 ),
.I1(\ROW_ADDRESS[12]_i_4_n_0 ),
.I2(\ROW_ADDRESS_reg[8]_i_2_n_5 ),
.O(ROW_ADDRESS_0[7]));
(* SOFT_HLUTNM = "soft_lutpair20" *)
LUT3 #(
.INIT(8'h70))
\ROW_ADDRESS[8]_i_1
(.I0(\ROW_ADDRESS[12]_i_3_n_0 ),
.I1(\ROW_ADDRESS[12]_i_4_n_0 ),
.I2(\ROW_ADDRESS_reg[8]_i_2_n_4 ),
.O(ROW_ADDRESS_0[8]));
LUT1 #(
.INIT(2'h1))
\ROW_ADDRESS[8]_i_5
(.I0(ROW_ADDRESS[6]),
.O(\ROW_ADDRESS[8]_i_5_n_0 ));
LUT1 #(
.INIT(2'h1))
\ROW_ADDRESS[8]_i_6
(.I0(ROW_ADDRESS[5]),
.O(\ROW_ADDRESS[8]_i_6_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair19" *)
LUT3 #(
.INIT(8'h70))
\ROW_ADDRESS[9]_i_1
(.I0(\ROW_ADDRESS[12]_i_3_n_0 ),
.I1(\ROW_ADDRESS[12]_i_4_n_0 ),
.I2(\ROW_ADDRESS_reg[12]_i_5_n_7 ),
.O(ROW_ADDRESS_0[9]));
FDRE \ROW_ADDRESS_reg[10]
(.C(ETH_CLK_OBUF),
.CE(\ROW_ADDRESS[12]_i_1_n_0 ),
.D(ROW_ADDRESS_0[10]),
.Q(ROW_ADDRESS[10]),
.R(INTERNAL_RST_reg));
FDRE \ROW_ADDRESS_reg[11]
(.C(ETH_CLK_OBUF),
.CE(\ROW_ADDRESS[12]_i_1_n_0 ),
.D(ROW_ADDRESS_0[11]),
.Q(ROW_ADDRESS[11]),
.R(INTERNAL_RST_reg));
FDRE \ROW_ADDRESS_reg[12]
(.C(ETH_CLK_OBUF),
.CE(\ROW_ADDRESS[12]_i_1_n_0 ),
.D(ROW_ADDRESS_0[12]),
.Q(ROW_ADDRESS[12]),
.R(INTERNAL_RST_reg));
CARRY4 \ROW_ADDRESS_reg[12]_i_5
(.CI(\ROW_ADDRESS_reg[8]_i_2_n_0 ),
.CO(\NLW_ROW_ADDRESS_reg[12]_i_5_CO_UNCONNECTED [3:0]),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O({\ROW_ADDRESS_reg[12]_i_5_n_4 ,\ROW_ADDRESS_reg[12]_i_5_n_5 ,\ROW_ADDRESS_reg[12]_i_5_n_6 ,\ROW_ADDRESS_reg[12]_i_5_n_7 }),
.S(ROW_ADDRESS[12:9]));
FDRE \ROW_ADDRESS_reg[1]
(.C(ETH_CLK_OBUF),
.CE(\ROW_ADDRESS[12]_i_1_n_0 ),
.D(ROW_ADDRESS_0[1]),
.Q(ROW_ADDRESS[1]),
.R(INTERNAL_RST_reg));
FDRE \ROW_ADDRESS_reg[2]
(.C(ETH_CLK_OBUF),
.CE(\ROW_ADDRESS[12]_i_1_n_0 ),
.D(ROW_ADDRESS_0[2]),
.Q(ROW_ADDRESS[2]),
.R(INTERNAL_RST_reg));
FDRE \ROW_ADDRESS_reg[3]
(.C(ETH_CLK_OBUF),
.CE(\ROW_ADDRESS[12]_i_1_n_0 ),
.D(ROW_ADDRESS_0[3]),
.Q(ROW_ADDRESS[3]),
.R(INTERNAL_RST_reg));
FDRE \ROW_ADDRESS_reg[4]
(.C(ETH_CLK_OBUF),
.CE(\ROW_ADDRESS[12]_i_1_n_0 ),
.D(ROW_ADDRESS_0[4]),
.Q(ROW_ADDRESS[4]),
.R(INTERNAL_RST_reg));
CARRY4 \ROW_ADDRESS_reg[4]_i_2
(.CI(1'b0),
.CO({\ROW_ADDRESS_reg[4]_i_2_n_0 ,\NLW_ROW_ADDRESS_reg[4]_i_2_CO_UNCONNECTED [2:0]}),
.CYINIT(1'b0),
.DI({1'b0,1'b0,ROW_ADDRESS[2],1'b0}),
.O({\ROW_ADDRESS_reg[4]_i_2_n_4 ,\ROW_ADDRESS_reg[4]_i_2_n_5 ,\ROW_ADDRESS_reg[4]_i_2_n_6 ,\ROW_ADDRESS_reg[4]_i_2_n_7 }),
.S({ROW_ADDRESS[4:3],\ROW_ADDRESS[4]_i_5_n_0 ,ROW_ADDRESS[1]}));
FDRE \ROW_ADDRESS_reg[5]
(.C(ETH_CLK_OBUF),
.CE(\ROW_ADDRESS[12]_i_1_n_0 ),
.D(ROW_ADDRESS_0[5]),
.Q(ROW_ADDRESS[5]),
.R(INTERNAL_RST_reg));
FDRE \ROW_ADDRESS_reg[6]
(.C(ETH_CLK_OBUF),
.CE(\ROW_ADDRESS[12]_i_1_n_0 ),
.D(ROW_ADDRESS_0[6]),
.Q(ROW_ADDRESS[6]),
.R(INTERNAL_RST_reg));
FDRE \ROW_ADDRESS_reg[7]
(.C(ETH_CLK_OBUF),
.CE(\ROW_ADDRESS[12]_i_1_n_0 ),
.D(ROW_ADDRESS_0[7]),
.Q(ROW_ADDRESS[7]),
.R(INTERNAL_RST_reg));
FDRE \ROW_ADDRESS_reg[8]
(.C(ETH_CLK_OBUF),
.CE(\ROW_ADDRESS[12]_i_1_n_0 ),
.D(ROW_ADDRESS_0[8]),
.Q(ROW_ADDRESS[8]),
.R(INTERNAL_RST_reg));
CARRY4 \ROW_ADDRESS_reg[8]_i_2
(.CI(\ROW_ADDRESS_reg[4]_i_2_n_0 ),
.CO({\ROW_ADDRESS_reg[8]_i_2_n_0 ,\NLW_ROW_ADDRESS_reg[8]_i_2_CO_UNCONNECTED [2:0]}),
.CYINIT(1'b0),
.DI({1'b0,1'b0,ROW_ADDRESS[6:5]}),
.O({\ROW_ADDRESS_reg[8]_i_2_n_4 ,\ROW_ADDRESS_reg[8]_i_2_n_5 ,\ROW_ADDRESS_reg[8]_i_2_n_6 ,\ROW_ADDRESS_reg[8]_i_2_n_7 }),
.S({ROW_ADDRESS[8:7],\ROW_ADDRESS[8]_i_5_n_0 ,\ROW_ADDRESS[8]_i_6_n_0 }));
FDRE \ROW_ADDRESS_reg[9]
(.C(ETH_CLK_OBUF),
.CE(\ROW_ADDRESS[12]_i_1_n_0 ),
.D(ROW_ADDRESS_0[9]),
.Q(ROW_ADDRESS[9]),
.R(INTERNAL_RST_reg));
LUT4 #(
.INIT(16'hFFD0))
VBLANK_i_1
(.I0(VBLANK_i_2_n_0),
.I1(VBLANK_i_3_n_0),
.I2(VBLANK_reg_n_0),
.I3(VBLANK_i_4_n_0),
.O(VBLANK_i_1_n_0));
LUT5 #(
.INIT(32'h00000004))
VBLANK_i_2
(.I0(VTIMER[7]),
.I1(VTIMER_EN),
.I2(VTIMER[8]),
.I3(VTIMER[9]),
.I4(VTIMER[6]),
.O(VBLANK_i_2_n_0));
LUT6 #(
.INIT(64'hFFFFFBFFFFFFFFFF))
VBLANK_i_3
(.I0(VTIMER[2]),
.I1(VTIMER[0]),
.I2(VTIMER[1]),
.I3(VTIMER[5]),
.I4(VTIMER[4]),
.I5(VTIMER[3]),
.O(VBLANK_i_3_n_0));
LUT6 #(
.INIT(64'hAAAAAAAAAAAAAABA))
VBLANK_i_4
(.I0(INTERNAL_RST_reg),
.I1(VBLANK_i_5_n_0),
.I2(VTIMER_EN),
.I3(VBLANK_i_6_n_0),
.I4(VTIMER[6]),
.I5(VBLANK_i_7_n_0),
.O(VBLANK_i_4_n_0));
LUT3 #(
.INIT(8'hFE))
VBLANK_i_5
(.I0(VTIMER[3]),
.I1(VTIMER[5]),
.I2(VTIMER[4]),
.O(VBLANK_i_5_n_0));
LUT3 #(
.INIT(8'hFB))
VBLANK_i_6
(.I0(VTIMER[1]),
.I1(VTIMER[0]),
.I2(VTIMER[2]),
.O(VBLANK_i_6_n_0));
LUT3 #(
.INIT(8'hDF))
VBLANK_i_7
(.I0(VTIMER[9]),
.I1(VTIMER[8]),
.I2(VTIMER[7]),
.O(VBLANK_i_7_n_0));
FDRE VBLANK_reg
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(VBLANK_i_1_n_0),
.Q(VBLANK_reg_n_0),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair14" *)
LUT2 #(
.INIT(4'h1))
\VTIMER[0]_i_1
(.I0(VTIMER[0]),
.I1(\VTIMER[2]_i_2_n_0 ),
.O(\VTIMER[0]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair14" *)
LUT3 #(
.INIT(8'h06))
\VTIMER[1]_i_1
(.I0(VTIMER[0]),
.I1(VTIMER[1]),
.I2(\VTIMER[2]_i_2_n_0 ),
.O(VTIMER_1[1]));
LUT4 #(
.INIT(16'h0078))
\VTIMER[2]_i_1
(.I0(VTIMER[1]),
.I1(VTIMER[0]),
.I2(VTIMER[2]),
.I3(\VTIMER[2]_i_2_n_0 ),
.O(VTIMER_1[2]));
LUT6 #(
.INIT(64'h0222000000000000))
\VTIMER[2]_i_2
(.I0(\VTIMER[2]_i_3_n_0 ),
.I1(VTIMER[5]),
.I2(VTIMER[3]),
.I3(VTIMER[4]),
.I4(VTIMER[1]),
.I5(VTIMER[2]),
.O(\VTIMER[2]_i_2_n_0 ));
LUT6 #(
.INIT(64'h0000000000400000))
\VTIMER[2]_i_3
(.I0(VTIMER[8]),
.I1(VTIMER[9]),
.I2(VTIMER[4]),
.I3(VTIMER[5]),
.I4(VTIMER[7]),
.I5(VTIMER[6]),
.O(\VTIMER[2]_i_3_n_0 ));
LUT4 #(
.INIT(16'h6AAA))
\VTIMER[3]_i_1
(.I0(VTIMER[3]),
.I1(VTIMER[2]),
.I2(VTIMER[1]),
.I3(VTIMER[0]),
.O(VTIMER_1[3]));
LUT6 #(
.INIT(64'h000000007FFF8000))
\VTIMER[4]_i_1
(.I0(VTIMER[0]),
.I1(VTIMER[1]),
.I2(VTIMER[2]),
.I3(VTIMER[3]),
.I4(VTIMER[4]),
.I5(\VTIMER[9]_i_3_n_0 ),
.O(VTIMER_1[4]));
LUT6 #(
.INIT(64'h6AAAAAAAAAAAAAAA))
\VTIMER[5]_i_1
(.I0(VTIMER[5]),
.I1(VTIMER[4]),
.I2(VTIMER[0]),
.I3(VTIMER[1]),
.I4(VTIMER[2]),
.I5(VTIMER[3]),
.O(\VTIMER[5]_i_1_n_0 ));
LUT2 #(
.INIT(4'h6))
\VTIMER[6]_i_1
(.I0(VTIMER[6]),
.I1(\VTIMER[9]_i_2_n_0 ),
.O(VTIMER_1[6]));
(* SOFT_HLUTNM = "soft_lutpair10" *)
LUT4 #(
.INIT(16'h1540))
\VTIMER[7]_i_1
(.I0(\VTIMER[9]_i_3_n_0 ),
.I1(\VTIMER[9]_i_2_n_0 ),
.I2(VTIMER[6]),
.I3(VTIMER[7]),
.O(VTIMER_1[7]));
(* SOFT_HLUTNM = "soft_lutpair10" *)
LUT4 #(
.INIT(16'h6AAA))
\VTIMER[8]_i_1
(.I0(VTIMER[8]),
.I1(VTIMER[7]),
.I2(VTIMER[6]),
.I3(\VTIMER[9]_i_2_n_0 ),
.O(VTIMER_1[8]));
LUT6 #(
.INIT(64'h000000006AAAAAAA))
\VTIMER[9]_i_1
(.I0(VTIMER[9]),
.I1(\VTIMER[9]_i_2_n_0 ),
.I2(VTIMER[6]),
.I3(VTIMER[7]),
.I4(VTIMER[8]),
.I5(\VTIMER[9]_i_3_n_0 ),
.O(VTIMER_1[9]));
LUT6 #(
.INIT(64'h8000000000000000))
\VTIMER[9]_i_2
(.I0(VTIMER[5]),
.I1(VTIMER[4]),
.I2(VTIMER[0]),
.I3(VTIMER[1]),
.I4(VTIMER[2]),
.I5(VTIMER[3]),
.O(\VTIMER[9]_i_2_n_0 ));
LUT5 #(
.INIT(32'h00000020))
\VTIMER[9]_i_3
(.I0(VTIMER[7]),
.I1(\VTIMER[9]_i_4_n_0 ),
.I2(VTIMER[9]),
.I3(VTIMER[8]),
.I4(\VTIMER[9]_i_5_n_0 ),
.O(\VTIMER[9]_i_3_n_0 ));
LUT4 #(
.INIT(16'hF8FF))
\VTIMER[9]_i_4
(.I0(VTIMER[6]),
.I1(VTIMER[7]),
.I2(VTIMER[5]),
.I3(VTIMER[4]),
.O(\VTIMER[9]_i_4_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFF7F7F7))
\VTIMER[9]_i_5
(.I0(VTIMER[1]),
.I1(VTIMER[2]),
.I2(VTIMER[0]),
.I3(VTIMER[4]),
.I4(VTIMER[3]),
.I5(VTIMER[5]),
.O(\VTIMER[9]_i_5_n_0 ));
LUT2 #(
.INIT(4'hE))
VTIMER_EN_i_1
(.I0(INTERNAL_RST_reg),
.I1(\HTIMER[4]_i_2_n_0 ),
.O(VTIMER_EN_i_1_n_0));
FDRE VTIMER_EN_reg
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(VTIMER_EN_i_1_n_0),
.Q(VTIMER_EN),
.R(1'b0));
FDRE \VTIMER_reg[0]
(.C(ETH_CLK_OBUF),
.CE(VTIMER_EN),
.D(\VTIMER[0]_i_1_n_0 ),
.Q(VTIMER[0]),
.R(INTERNAL_RST_reg));
FDRE \VTIMER_reg[1]
(.C(ETH_CLK_OBUF),
.CE(VTIMER_EN),
.D(VTIMER_1[1]),
.Q(VTIMER[1]),
.R(INTERNAL_RST_reg));
FDRE \VTIMER_reg[2]
(.C(ETH_CLK_OBUF),
.CE(VTIMER_EN),
.D(VTIMER_1[2]),
.Q(VTIMER[2]),
.R(INTERNAL_RST_reg));
FDRE \VTIMER_reg[3]
(.C(ETH_CLK_OBUF),
.CE(VTIMER_EN),
.D(VTIMER_1[3]),
.Q(VTIMER[3]),
.R(INTERNAL_RST_reg));
FDRE \VTIMER_reg[4]
(.C(ETH_CLK_OBUF),
.CE(VTIMER_EN),
.D(VTIMER_1[4]),
.Q(VTIMER[4]),
.R(INTERNAL_RST_reg));
FDRE \VTIMER_reg[5]
(.C(ETH_CLK_OBUF),
.CE(VTIMER_EN),
.D(\VTIMER[5]_i_1_n_0 ),
.Q(VTIMER[5]),
.R(INTERNAL_RST_reg));
FDRE \VTIMER_reg[6]
(.C(ETH_CLK_OBUF),
.CE(VTIMER_EN),
.D(VTIMER_1[6]),
.Q(VTIMER[6]),
.R(INTERNAL_RST_reg));
FDRE \VTIMER_reg[7]
(.C(ETH_CLK_OBUF),
.CE(VTIMER_EN),
.D(VTIMER_1[7]),
.Q(VTIMER[7]),
.R(INTERNAL_RST_reg));
FDRE \VTIMER_reg[8]
(.C(ETH_CLK_OBUF),
.CE(VTIMER_EN),
.D(VTIMER_1[8]),
.Q(VTIMER[8]),
.R(INTERNAL_RST_reg));
FDRE \VTIMER_reg[9]
(.C(ETH_CLK_OBUF),
.CE(VTIMER_EN),
.D(VTIMER_1[9]),
.Q(VTIMER[9]),
.R(INTERNAL_RST_reg));
endmodule
|
module main_0
(IN1_STB,
output_rs232_tx,
IN1_ACK,
ETH_CLK_OBUF,
INTERNAL_RST_reg);
output IN1_STB;
output [7:0]output_rs232_tx;
input IN1_ACK;
input ETH_CLK_OBUF;
input INTERNAL_RST_reg;
wire ETH_CLK_OBUF;
wire IN1_ACK;
wire IN1_STB;
wire INTERNAL_RST_reg;
wire [3:0]address_a;
wire [3:0]address_a_2;
wire [3:0]address_b_2;
wire [3:0]address_z;
wire [3:0]address_z_2;
wire [3:0]address_z_3;
wire \address_z_3[3]_i_1_n_0 ;
wire [15:1]data1;
wire [16:1]data2;
wire [31:0]data3;
wire instruction0;
wire \instruction[0]_i_4_n_0 ;
wire \instruction[0]_i_5_n_0 ;
wire \instruction[0]_i_6_n_0 ;
wire \instruction[0]_i_7_n_0 ;
wire \instruction[15]_i_2_n_0 ;
wire \instruction[15]_i_3_n_0 ;
wire \instruction[15]_i_4_n_0 ;
wire \instruction[15]_i_5_n_0 ;
wire \instruction[15]_i_6_n_0 ;
wire \instruction[15]_i_7_n_0 ;
wire \instruction[16]_i_4_n_0 ;
wire \instruction[16]_i_5_n_0 ;
wire \instruction[16]_i_6_n_0 ;
wire \instruction[16]_i_7_n_0 ;
wire \instruction[17]_i_4_n_0 ;
wire \instruction[17]_i_5_n_0 ;
wire \instruction[17]_i_6_n_0 ;
wire \instruction[17]_i_7_n_0 ;
wire \instruction[18]_i_4_n_0 ;
wire \instruction[18]_i_5_n_0 ;
wire \instruction[18]_i_6_n_0 ;
wire \instruction[18]_i_7_n_0 ;
wire \instruction[19]_i_4_n_0 ;
wire \instruction[19]_i_5_n_0 ;
wire \instruction[19]_i_6_n_0 ;
wire \instruction[19]_i_7_n_0 ;
wire \instruction[1]_i_4_n_0 ;
wire \instruction[1]_i_5_n_0 ;
wire \instruction[1]_i_6_n_0 ;
wire \instruction[1]_i_7_n_0 ;
wire \instruction[20]_i_4_n_0 ;
wire \instruction[20]_i_5_n_0 ;
wire \instruction[20]_i_6_n_0 ;
wire \instruction[20]_i_7_n_0 ;
wire \instruction[21]_i_4_n_0 ;
wire \instruction[21]_i_5_n_0 ;
wire \instruction[21]_i_6_n_0 ;
wire \instruction[21]_i_7_n_0 ;
wire \instruction[22]_i_4_n_0 ;
wire \instruction[22]_i_5_n_0 ;
wire \instruction[22]_i_6_n_0 ;
wire \instruction[22]_i_7_n_0 ;
wire \instruction[23]_i_4_n_0 ;
wire \instruction[23]_i_5_n_0 ;
wire \instruction[23]_i_6_n_0 ;
wire \instruction[23]_i_7_n_0 ;
wire \instruction[24]_i_4_n_0 ;
wire \instruction[24]_i_5_n_0 ;
wire \instruction[24]_i_6_n_0 ;
wire \instruction[24]_i_7_n_0 ;
wire \instruction[25]_i_4_n_0 ;
wire \instruction[25]_i_5_n_0 ;
wire \instruction[25]_i_6_n_0 ;
wire \instruction[25]_i_7_n_0 ;
wire \instruction[26]_i_4_n_0 ;
wire \instruction[26]_i_5_n_0 ;
wire \instruction[26]_i_6_n_0 ;
wire \instruction[26]_i_7_n_0 ;
wire \instruction[27]_i_2_n_0 ;
wire \instruction[27]_i_3_n_0 ;
wire \instruction[27]_i_4_n_0 ;
wire \instruction[27]_i_5_n_0 ;
wire \instruction[27]_i_6_n_0 ;
wire \instruction[2]_i_4_n_0 ;
wire \instruction[2]_i_5_n_0 ;
wire \instruction[2]_i_6_n_0 ;
wire \instruction[2]_i_7_n_0 ;
wire \instruction[3]_i_4_n_0 ;
wire \instruction[3]_i_5_n_0 ;
wire \instruction[3]_i_6_n_0 ;
wire \instruction[3]_i_7_n_0 ;
wire \instruction[4]_i_1_n_0 ;
wire \instruction[4]_i_3_n_0 ;
wire \instruction[4]_i_4_n_0 ;
wire \instruction[4]_i_5_n_0 ;
wire \instruction[4]_i_6_n_0 ;
wire \instruction[5]_i_4_n_0 ;
wire \instruction[5]_i_5_n_0 ;
wire \instruction[5]_i_6_n_0 ;
wire \instruction[5]_i_7_n_0 ;
wire \instruction[6]_i_4_n_0 ;
wire \instruction[6]_i_5_n_0 ;
wire \instruction[6]_i_6_n_0 ;
wire \instruction[6]_i_7_n_0 ;
wire \instruction[7]_i_4_n_0 ;
wire \instruction[7]_i_5_n_0 ;
wire \instruction[7]_i_6_n_0 ;
wire \instruction[7]_i_7_n_0 ;
wire \instruction_reg[0]_i_1_n_0 ;
wire \instruction_reg[0]_i_2_n_0 ;
wire \instruction_reg[0]_i_3_n_0 ;
wire \instruction_reg[15]_i_1_n_0 ;
wire \instruction_reg[16]_i_1_n_0 ;
wire \instruction_reg[16]_i_2_n_0 ;
wire \instruction_reg[16]_i_3_n_0 ;
wire \instruction_reg[17]_i_1_n_0 ;
wire \instruction_reg[17]_i_2_n_0 ;
wire \instruction_reg[17]_i_3_n_0 ;
wire \instruction_reg[18]_i_1_n_0 ;
wire \instruction_reg[18]_i_2_n_0 ;
wire \instruction_reg[18]_i_3_n_0 ;
wire \instruction_reg[19]_i_1_n_0 ;
wire \instruction_reg[19]_i_2_n_0 ;
wire \instruction_reg[19]_i_3_n_0 ;
wire \instruction_reg[1]_i_1_n_0 ;
wire \instruction_reg[1]_i_2_n_0 ;
wire \instruction_reg[1]_i_3_n_0 ;
wire \instruction_reg[20]_i_1_n_0 ;
wire \instruction_reg[20]_i_2_n_0 ;
wire \instruction_reg[20]_i_3_n_0 ;
wire \instruction_reg[21]_i_1_n_0 ;
wire \instruction_reg[21]_i_2_n_0 ;
wire \instruction_reg[21]_i_3_n_0 ;
wire \instruction_reg[22]_i_1_n_0 ;
wire \instruction_reg[22]_i_2_n_0 ;
wire \instruction_reg[22]_i_3_n_0 ;
wire \instruction_reg[23]_i_1_n_0 ;
wire \instruction_reg[23]_i_2_n_0 ;
wire \instruction_reg[23]_i_3_n_0 ;
wire \instruction_reg[24]_i_1_n_0 ;
wire \instruction_reg[24]_i_2_n_0 ;
wire \instruction_reg[24]_i_3_n_0 ;
wire \instruction_reg[25]_i_1_n_0 ;
wire \instruction_reg[25]_i_2_n_0 ;
wire \instruction_reg[25]_i_3_n_0 ;
wire \instruction_reg[26]_i_1_n_0 ;
wire \instruction_reg[26]_i_2_n_0 ;
wire \instruction_reg[26]_i_3_n_0 ;
wire \instruction_reg[27]_i_1_n_0 ;
wire \instruction_reg[2]_i_1_n_0 ;
wire \instruction_reg[2]_i_2_n_0 ;
wire \instruction_reg[2]_i_3_n_0 ;
wire \instruction_reg[3]_i_1_n_0 ;
wire \instruction_reg[3]_i_2_n_0 ;
wire \instruction_reg[3]_i_3_n_0 ;
wire \instruction_reg[4]_i_2_n_0 ;
wire \instruction_reg[5]_i_1_n_0 ;
wire \instruction_reg[5]_i_2_n_0 ;
wire \instruction_reg[5]_i_3_n_0 ;
wire \instruction_reg[6]_i_1_n_0 ;
wire \instruction_reg[6]_i_2_n_0 ;
wire \instruction_reg[6]_i_3_n_0 ;
wire \instruction_reg[7]_i_1_n_0 ;
wire \instruction_reg[7]_i_2_n_0 ;
wire \instruction_reg[7]_i_3_n_0 ;
wire \instruction_reg_n_0_[0] ;
wire \instruction_reg_n_0_[15] ;
wire \instruction_reg_n_0_[1] ;
wire \instruction_reg_n_0_[2] ;
wire \instruction_reg_n_0_[3] ;
wire \instruction_reg_n_0_[4] ;
wire \instruction_reg_n_0_[5] ;
wire \instruction_reg_n_0_[6] ;
wire \instruction_reg_n_0_[7] ;
wire [15:4]literal_2;
wire [31:0]load_data;
wire memory_reg_1_ENARDEN_cooolgate_en_sig_1;
wire memory_reg_2_ENARDEN_cooolgate_en_sig_2;
wire memory_reg_3_ENARDEN_cooolgate_en_sig_3;
wire memory_reg_4_ENARDEN_cooolgate_en_sig_4;
wire memory_reg_5_ENARDEN_cooolgate_en_sig_5;
wire memory_reg_6_ENARDEN_cooolgate_en_sig_6;
wire memory_reg_7_ENARDEN_cooolgate_en_sig_7;
wire [3:0]opcode;
wire [3:0]opcode_2;
wire opcode_20;
wire operand_a1;
wire operand_b1;
wire [7:0]output_rs232_tx;
wire p_0_in;
wire \program_counter[10]_i_1_n_0 ;
wire \program_counter[11]_i_1_n_0 ;
wire \program_counter[12]_i_1_n_0 ;
wire \program_counter[13]_i_1_n_0 ;
wire \program_counter[14]_i_1_n_0 ;
wire \program_counter[14]_i_2_n_0 ;
wire \program_counter[14]_i_3_n_0 ;
wire \program_counter[15]_i_1_n_0 ;
wire \program_counter[15]_i_3_n_0 ;
wire \program_counter[8]_i_1_n_0 ;
wire \program_counter[9]_i_1_n_0 ;
wire [15:0]program_counter_1;
wire [15:0]program_counter_2;
wire \program_counter_reg[12]_i_2_n_0 ;
wire \program_counter_reg_n_0_[0] ;
wire \program_counter_reg_n_0_[10] ;
wire \program_counter_reg_n_0_[11] ;
wire \program_counter_reg_n_0_[12] ;
wire \program_counter_reg_n_0_[13] ;
wire \program_counter_reg_n_0_[14] ;
wire \program_counter_reg_n_0_[15] ;
wire \program_counter_reg_n_0_[1] ;
wire \program_counter_reg_n_0_[2] ;
wire \program_counter_reg_n_0_[3] ;
wire \program_counter_reg_n_0_[4] ;
wire \program_counter_reg_n_0_[5] ;
wire \program_counter_reg_n_0_[6] ;
wire \program_counter_reg_n_0_[7] ;
wire \program_counter_reg_n_0_[8] ;
wire \program_counter_reg_n_0_[9] ;
wire \program_counter_reg_rep[4]_i_2_n_0 ;
wire \program_counter_reg_rep[7]_i_4_n_0 ;
wire \program_counter_reg_rep_n_0_[0] ;
wire \program_counter_reg_rep_n_0_[1] ;
wire \program_counter_reg_rep_n_0_[2] ;
wire \program_counter_reg_rep_n_0_[3] ;
wire \program_counter_reg_rep_n_0_[4] ;
wire \program_counter_reg_rep_n_0_[5] ;
wire \program_counter_reg_rep_n_0_[6] ;
wire \program_counter_reg_rep_n_0_[7] ;
wire \program_counter_rep[0]_i_1_n_0 ;
wire \program_counter_rep[0]_i_2_n_0 ;
wire \program_counter_rep[1]_i_1_n_0 ;
wire \program_counter_rep[1]_i_2_n_0 ;
wire \program_counter_rep[2]_i_1_n_0 ;
wire \program_counter_rep[2]_i_2_n_0 ;
wire \program_counter_rep[3]_i_1_n_0 ;
wire \program_counter_rep[3]_i_2_n_0 ;
wire \program_counter_rep[4]_i_1_n_0 ;
wire \program_counter_rep[4]_i_3_n_0 ;
wire \program_counter_rep[5]_i_1_n_0 ;
wire \program_counter_rep[5]_i_2_n_0 ;
wire \program_counter_rep[6]_i_1_n_0 ;
wire \program_counter_rep[6]_i_2_n_0 ;
wire \program_counter_rep[7]_i_10_n_0 ;
wire \program_counter_rep[7]_i_15_n_0 ;
wire \program_counter_rep[7]_i_16_n_0 ;
wire \program_counter_rep[7]_i_17_n_0 ;
wire \program_counter_rep[7]_i_18_n_0 ;
wire \program_counter_rep[7]_i_19_n_0 ;
wire \program_counter_rep[7]_i_20_n_0 ;
wire \program_counter_rep[7]_i_21_n_0 ;
wire \program_counter_rep[7]_i_22_n_0 ;
wire \program_counter_rep[7]_i_23_n_0 ;
wire \program_counter_rep[7]_i_24_n_0 ;
wire \program_counter_rep[7]_i_25_n_0 ;
wire \program_counter_rep[7]_i_26_n_0 ;
wire \program_counter_rep[7]_i_2_n_0 ;
wire \program_counter_rep[7]_i_3_n_0 ;
wire \program_counter_rep[7]_i_5_n_0 ;
wire \program_counter_rep[7]_i_6_n_0 ;
wire \program_counter_rep[7]_i_7_n_0 ;
wire \program_counter_rep[7]_i_8_n_0 ;
wire \program_counter_rep[7]_i_9_n_0 ;
wire [31:0]register_a;
wire [31:0]register_b;
wire [31:0]result;
wire \result[0]_i_1_n_0 ;
wire \result[0]_i_2_n_0 ;
wire \result[10]_i_1_n_0 ;
wire \result[10]_i_2_n_0 ;
wire \result[11]_i_10_n_0 ;
wire \result[11]_i_11_n_0 ;
wire \result[11]_i_12_n_0 ;
wire \result[11]_i_1_n_0 ;
wire \result[11]_i_2_n_0 ;
wire \result[11]_i_5_n_0 ;
wire \result[11]_i_6_n_0 ;
wire \result[11]_i_7_n_0 ;
wire \result[11]_i_8_n_0 ;
wire \result[11]_i_9_n_0 ;
wire \result[12]_i_1_n_0 ;
wire \result[12]_i_2_n_0 ;
wire \result[13]_i_1_n_0 ;
wire \result[13]_i_2_n_0 ;
wire \result[14]_i_1_n_0 ;
wire \result[14]_i_2_n_0 ;
wire \result[15]_i_10_n_0 ;
wire \result[15]_i_11_n_0 ;
wire \result[15]_i_12_n_0 ;
wire \result[15]_i_1_n_0 ;
wire \result[15]_i_2_n_0 ;
wire \result[15]_i_5_n_0 ;
wire \result[15]_i_6_n_0 ;
wire \result[15]_i_7_n_0 ;
wire \result[15]_i_8_n_0 ;
wire \result[15]_i_9_n_0 ;
wire \result[16]_i_1_n_0 ;
wire \result[16]_i_2_n_0 ;
wire \result[16]_i_4_n_0 ;
wire \result[17]_i_1_n_0 ;
wire \result[17]_i_2_n_0 ;
wire \result[18]_i_1_n_0 ;
wire \result[18]_i_2_n_0 ;
wire \result[19]_i_10_n_0 ;
wire \result[19]_i_11_n_0 ;
wire \result[19]_i_12_n_0 ;
wire \result[19]_i_1_n_0 ;
wire \result[19]_i_2_n_0 ;
wire \result[19]_i_5_n_0 ;
wire \result[19]_i_6_n_0 ;
wire \result[19]_i_7_n_0 ;
wire \result[19]_i_8_n_0 ;
wire \result[19]_i_9_n_0 ;
wire \result[1]_i_1_n_0 ;
wire \result[1]_i_2_n_0 ;
wire \result[20]_i_1_n_0 ;
wire \result[20]_i_2_n_0 ;
wire \result[21]_i_1_n_0 ;
wire \result[21]_i_2_n_0 ;
wire \result[22]_i_1_n_0 ;
wire \result[22]_i_2_n_0 ;
wire \result[23]_i_10_n_0 ;
wire \result[23]_i_11_n_0 ;
wire \result[23]_i_12_n_0 ;
wire \result[23]_i_1_n_0 ;
wire \result[23]_i_2_n_0 ;
wire \result[23]_i_5_n_0 ;
wire \result[23]_i_6_n_0 ;
wire \result[23]_i_7_n_0 ;
wire \result[23]_i_8_n_0 ;
wire \result[23]_i_9_n_0 ;
wire \result[24]_i_1_n_0 ;
wire \result[24]_i_2_n_0 ;
wire \result[25]_i_1_n_0 ;
wire \result[25]_i_2_n_0 ;
wire \result[26]_i_1_n_0 ;
wire \result[26]_i_2_n_0 ;
wire \result[27]_i_10_n_0 ;
wire \result[27]_i_11_n_0 ;
wire \result[27]_i_12_n_0 ;
wire \result[27]_i_1_n_0 ;
wire \result[27]_i_2_n_0 ;
wire \result[27]_i_5_n_0 ;
wire \result[27]_i_6_n_0 ;
wire \result[27]_i_7_n_0 ;
wire \result[27]_i_8_n_0 ;
wire \result[27]_i_9_n_0 ;
wire \result[28]_i_1_n_0 ;
wire \result[28]_i_2_n_0 ;
wire \result[29]_i_1_n_0 ;
wire \result[29]_i_2_n_0 ;
wire \result[2]_i_1_n_0 ;
wire \result[2]_i_2_n_0 ;
wire \result[30]_i_1_n_0 ;
wire \result[30]_i_2_n_0 ;
wire \result[31]_i_10_n_0 ;
wire \result[31]_i_11_n_0 ;
wire \result[31]_i_12_n_0 ;
wire \result[31]_i_13_n_0 ;
wire \result[31]_i_14_n_0 ;
wire \result[31]_i_15_n_0 ;
wire \result[31]_i_1_n_0 ;
wire \result[31]_i_2_n_0 ;
wire \result[31]_i_3_n_0 ;
wire \result[31]_i_4_n_0 ;
wire \result[31]_i_5_n_0 ;
wire \result[31]_i_8_n_0 ;
wire \result[31]_i_9_n_0 ;
wire \result[3]_i_10_n_0 ;
wire \result[3]_i_11_n_0 ;
wire \result[3]_i_12_n_0 ;
wire \result[3]_i_13_n_0 ;
wire \result[3]_i_14_n_0 ;
wire \result[3]_i_15_n_0 ;
wire \result[3]_i_16_n_0 ;
wire \result[3]_i_1_n_0 ;
wire \result[3]_i_2_n_0 ;
wire \result[3]_i_5_n_0 ;
wire \result[3]_i_6_n_0 ;
wire \result[3]_i_7_n_0 ;
wire \result[3]_i_8_n_0 ;
wire \result[3]_i_9_n_0 ;
wire \result[4]_i_1_n_0 ;
wire \result[4]_i_2_n_0 ;
wire \result[5]_i_1_n_0 ;
wire \result[5]_i_2_n_0 ;
wire \result[6]_i_1_n_0 ;
wire \result[6]_i_2_n_0 ;
wire \result[7]_i_10_n_0 ;
wire \result[7]_i_11_n_0 ;
wire \result[7]_i_12_n_0 ;
wire \result[7]_i_1_n_0 ;
wire \result[7]_i_2_n_0 ;
wire \result[7]_i_5_n_0 ;
wire \result[7]_i_6_n_0 ;
wire \result[7]_i_7_n_0 ;
wire \result[7]_i_8_n_0 ;
wire \result[7]_i_9_n_0 ;
wire \result[8]_i_1_n_0 ;
wire \result[8]_i_2_n_0 ;
wire \result[9]_i_1_n_0 ;
wire \result[9]_i_2_n_0 ;
wire \result_reg[11]_i_3_n_0 ;
wire \result_reg[11]_i_3_n_4 ;
wire \result_reg[11]_i_3_n_5 ;
wire \result_reg[11]_i_3_n_6 ;
wire \result_reg[11]_i_3_n_7 ;
wire \result_reg[11]_i_4_n_0 ;
wire \result_reg[12]_i_3_n_0 ;
wire \result_reg[15]_i_3_n_0 ;
wire \result_reg[15]_i_3_n_4 ;
wire \result_reg[15]_i_3_n_5 ;
wire \result_reg[15]_i_3_n_6 ;
wire \result_reg[15]_i_3_n_7 ;
wire \result_reg[15]_i_4_n_0 ;
wire \result_reg[19]_i_3_n_0 ;
wire \result_reg[19]_i_3_n_4 ;
wire \result_reg[19]_i_3_n_5 ;
wire \result_reg[19]_i_3_n_6 ;
wire \result_reg[19]_i_3_n_7 ;
wire \result_reg[19]_i_4_n_0 ;
wire \result_reg[23]_i_3_n_0 ;
wire \result_reg[23]_i_3_n_4 ;
wire \result_reg[23]_i_3_n_5 ;
wire \result_reg[23]_i_3_n_6 ;
wire \result_reg[23]_i_3_n_7 ;
wire \result_reg[23]_i_4_n_0 ;
wire \result_reg[27]_i_3_n_0 ;
wire \result_reg[27]_i_3_n_4 ;
wire \result_reg[27]_i_3_n_5 ;
wire \result_reg[27]_i_3_n_6 ;
wire \result_reg[27]_i_3_n_7 ;
wire \result_reg[27]_i_4_n_0 ;
wire \result_reg[31]_i_6_n_4 ;
wire \result_reg[31]_i_6_n_5 ;
wire \result_reg[31]_i_6_n_6 ;
wire \result_reg[31]_i_6_n_7 ;
wire \result_reg[3]_i_3_n_0 ;
wire \result_reg[3]_i_3_n_4 ;
wire \result_reg[3]_i_3_n_5 ;
wire \result_reg[3]_i_3_n_6 ;
wire \result_reg[3]_i_3_n_7 ;
wire \result_reg[3]_i_4_n_0 ;
wire \result_reg[4]_i_3_n_0 ;
wire \result_reg[7]_i_3_n_0 ;
wire \result_reg[7]_i_3_n_4 ;
wire \result_reg[7]_i_3_n_5 ;
wire \result_reg[7]_i_3_n_6 ;
wire \result_reg[7]_i_3_n_7 ;
wire \result_reg[7]_i_4_n_0 ;
wire \result_reg[8]_i_3_n_0 ;
wire \s_output_rs232_tx[7]_i_1_n_0 ;
wire \s_output_rs232_tx[7]_i_2_n_0 ;
wire \s_output_rs232_tx[7]_i_3_n_0 ;
wire \s_output_rs232_tx[7]_i_4_n_0 ;
wire \s_output_rs232_tx[7]_i_5_n_0 ;
wire \s_output_rs232_tx[7]_i_6_n_0 ;
wire \s_output_rs232_tx[7]_i_7_n_0 ;
wire \s_output_rs232_tx[7]_i_8_n_0 ;
wire \s_output_rs232_tx_stb[0]_i_1_n_0 ;
wire \state[0]_i_1_n_0 ;
wire \state[1]_i_1_n_0 ;
wire \state[2]_i_10_n_0 ;
wire \state[2]_i_11_n_0 ;
wire \state[2]_i_12_n_0 ;
wire \state[2]_i_1_n_0 ;
wire \state[2]_i_2_n_0 ;
wire \state[2]_i_3_n_0 ;
wire \state[2]_i_4_n_0 ;
wire \state[2]_i_5_n_0 ;
wire \state[2]_i_6_n_0 ;
wire \state[2]_i_7_n_0 ;
wire \state[2]_i_8_n_0 ;
wire \state[2]_i_9_n_0 ;
wire \state_reg_n_0_[0] ;
wire \state_reg_n_0_[1] ;
wire \state_reg_n_0_[2] ;
wire [31:0]store_data;
wire write_enable;
wire [31:0]write_output;
wire \write_output[0]_i_1_n_0 ;
wire \write_output[10]_i_1_n_0 ;
wire \write_output[11]_i_1_n_0 ;
wire \write_output[12]_i_1_n_0 ;
wire \write_output[13]_i_1_n_0 ;
wire \write_output[14]_i_1_n_0 ;
wire \write_output[15]_i_1_n_0 ;
wire \write_output[16]_i_1_n_0 ;
wire \write_output[17]_i_1_n_0 ;
wire \write_output[18]_i_1_n_0 ;
wire \write_output[19]_i_1_n_0 ;
wire \write_output[1]_i_1_n_0 ;
wire \write_output[20]_i_1_n_0 ;
wire \write_output[21]_i_1_n_0 ;
wire \write_output[22]_i_1_n_0 ;
wire \write_output[23]_i_1_n_0 ;
wire \write_output[24]_i_1_n_0 ;
wire \write_output[25]_i_1_n_0 ;
wire \write_output[26]_i_1_n_0 ;
wire \write_output[27]_i_1_n_0 ;
wire \write_output[28]_i_1_n_0 ;
wire \write_output[29]_i_1_n_0 ;
wire \write_output[2]_i_1_n_0 ;
wire \write_output[30]_i_1_n_0 ;
wire \write_output[31]_i_1_n_0 ;
wire \write_output[31]_i_2_n_0 ;
wire \write_output[31]_i_3_n_0 ;
wire \write_output[31]_i_4_n_0 ;
wire \write_output[3]_i_1_n_0 ;
wire \write_output[4]_i_1_n_0 ;
wire \write_output[5]_i_1_n_0 ;
wire \write_output[6]_i_1_n_0 ;
wire \write_output[7]_i_1_n_0 ;
wire \write_output[8]_i_1_n_0 ;
wire \write_output[9]_i_1_n_0 ;
wire [7:0]write_value;
wire \write_value[7]_i_3_n_0 ;
wire NLW_memory_reg_0_CASCADEOUTA_UNCONNECTED;
wire NLW_memory_reg_0_CASCADEOUTB_UNCONNECTED;
wire NLW_memory_reg_0_DBITERR_UNCONNECTED;
wire NLW_memory_reg_0_INJECTDBITERR_UNCONNECTED;
wire NLW_memory_reg_0_INJECTSBITERR_UNCONNECTED;
wire NLW_memory_reg_0_REGCEAREGCE_UNCONNECTED;
wire NLW_memory_reg_0_REGCEB_UNCONNECTED;
wire NLW_memory_reg_0_SBITERR_UNCONNECTED;
wire [31:4]NLW_memory_reg_0_DOADO_UNCONNECTED;
wire [31:0]NLW_memory_reg_0_DOBDO_UNCONNECTED;
wire [3:0]NLW_memory_reg_0_DOPADOP_UNCONNECTED;
wire [3:0]NLW_memory_reg_0_DOPBDOP_UNCONNECTED;
wire [7:0]NLW_memory_reg_0_ECCPARITY_UNCONNECTED;
wire [8:0]NLW_memory_reg_0_RDADDRECC_UNCONNECTED;
wire NLW_memory_reg_1_CASCADEOUTA_UNCONNECTED;
wire NLW_memory_reg_1_CASCADEOUTB_UNCONNECTED;
wire NLW_memory_reg_1_DBITERR_UNCONNECTED;
wire NLW_memory_reg_1_INJECTDBITERR_UNCONNECTED;
wire NLW_memory_reg_1_INJECTSBITERR_UNCONNECTED;
wire NLW_memory_reg_1_REGCEAREGCE_UNCONNECTED;
wire NLW_memory_reg_1_REGCEB_UNCONNECTED;
wire NLW_memory_reg_1_SBITERR_UNCONNECTED;
wire [31:4]NLW_memory_reg_1_DOADO_UNCONNECTED;
wire [31:0]NLW_memory_reg_1_DOBDO_UNCONNECTED;
wire [3:0]NLW_memory_reg_1_DOPADOP_UNCONNECTED;
wire [3:0]NLW_memory_reg_1_DOPBDOP_UNCONNECTED;
wire [7:0]NLW_memory_reg_1_ECCPARITY_UNCONNECTED;
wire [8:0]NLW_memory_reg_1_RDADDRECC_UNCONNECTED;
wire NLW_memory_reg_2_CASCADEOUTA_UNCONNECTED;
wire NLW_memory_reg_2_CASCADEOUTB_UNCONNECTED;
wire NLW_memory_reg_2_DBITERR_UNCONNECTED;
wire NLW_memory_reg_2_INJECTDBITERR_UNCONNECTED;
wire NLW_memory_reg_2_INJECTSBITERR_UNCONNECTED;
wire NLW_memory_reg_2_REGCEAREGCE_UNCONNECTED;
wire NLW_memory_reg_2_REGCEB_UNCONNECTED;
wire NLW_memory_reg_2_SBITERR_UNCONNECTED;
wire [31:4]NLW_memory_reg_2_DOADO_UNCONNECTED;
wire [31:0]NLW_memory_reg_2_DOBDO_UNCONNECTED;
wire [3:0]NLW_memory_reg_2_DOPADOP_UNCONNECTED;
wire [3:0]NLW_memory_reg_2_DOPBDOP_UNCONNECTED;
wire [7:0]NLW_memory_reg_2_ECCPARITY_UNCONNECTED;
wire [8:0]NLW_memory_reg_2_RDADDRECC_UNCONNECTED;
wire NLW_memory_reg_3_CASCADEOUTA_UNCONNECTED;
wire NLW_memory_reg_3_CASCADEOUTB_UNCONNECTED;
wire NLW_memory_reg_3_DBITERR_UNCONNECTED;
wire NLW_memory_reg_3_INJECTDBITERR_UNCONNECTED;
wire NLW_memory_reg_3_INJECTSBITERR_UNCONNECTED;
wire NLW_memory_reg_3_REGCEAREGCE_UNCONNECTED;
wire NLW_memory_reg_3_REGCEB_UNCONNECTED;
wire NLW_memory_reg_3_SBITERR_UNCONNECTED;
wire [31:4]NLW_memory_reg_3_DOADO_UNCONNECTED;
wire [31:0]NLW_memory_reg_3_DOBDO_UNCONNECTED;
wire [3:0]NLW_memory_reg_3_DOPADOP_UNCONNECTED;
wire [3:0]NLW_memory_reg_3_DOPBDOP_UNCONNECTED;
wire [7:0]NLW_memory_reg_3_ECCPARITY_UNCONNECTED;
wire [8:0]NLW_memory_reg_3_RDADDRECC_UNCONNECTED;
wire NLW_memory_reg_4_CASCADEOUTA_UNCONNECTED;
wire NLW_memory_reg_4_CASCADEOUTB_UNCONNECTED;
wire NLW_memory_reg_4_DBITERR_UNCONNECTED;
wire NLW_memory_reg_4_INJECTDBITERR_UNCONNECTED;
wire NLW_memory_reg_4_INJECTSBITERR_UNCONNECTED;
wire NLW_memory_reg_4_REGCEAREGCE_UNCONNECTED;
wire NLW_memory_reg_4_REGCEB_UNCONNECTED;
wire NLW_memory_reg_4_SBITERR_UNCONNECTED;
wire [31:4]NLW_memory_reg_4_DOADO_UNCONNECTED;
wire [31:0]NLW_memory_reg_4_DOBDO_UNCONNECTED;
wire [3:0]NLW_memory_reg_4_DOPADOP_UNCONNECTED;
wire [3:0]NLW_memory_reg_4_DOPBDOP_UNCONNECTED;
wire [7:0]NLW_memory_reg_4_ECCPARITY_UNCONNECTED;
wire [8:0]NLW_memory_reg_4_RDADDRECC_UNCONNECTED;
wire NLW_memory_reg_5_CASCADEOUTA_UNCONNECTED;
wire NLW_memory_reg_5_CASCADEOUTB_UNCONNECTED;
wire NLW_memory_reg_5_DBITERR_UNCONNECTED;
wire NLW_memory_reg_5_INJECTDBITERR_UNCONNECTED;
wire NLW_memory_reg_5_INJECTSBITERR_UNCONNECTED;
wire NLW_memory_reg_5_REGCEAREGCE_UNCONNECTED;
wire NLW_memory_reg_5_REGCEB_UNCONNECTED;
wire NLW_memory_reg_5_SBITERR_UNCONNECTED;
wire [31:4]NLW_memory_reg_5_DOADO_UNCONNECTED;
wire [31:0]NLW_memory_reg_5_DOBDO_UNCONNECTED;
wire [3:0]NLW_memory_reg_5_DOPADOP_UNCONNECTED;
wire [3:0]NLW_memory_reg_5_DOPBDOP_UNCONNECTED;
wire [7:0]NLW_memory_reg_5_ECCPARITY_UNCONNECTED;
wire [8:0]NLW_memory_reg_5_RDADDRECC_UNCONNECTED;
wire NLW_memory_reg_6_CASCADEOUTA_UNCONNECTED;
wire NLW_memory_reg_6_CASCADEOUTB_UNCONNECTED;
wire NLW_memory_reg_6_DBITERR_UNCONNECTED;
wire NLW_memory_reg_6_INJECTDBITERR_UNCONNECTED;
wire NLW_memory_reg_6_INJECTSBITERR_UNCONNECTED;
wire NLW_memory_reg_6_REGCEAREGCE_UNCONNECTED;
wire NLW_memory_reg_6_REGCEB_UNCONNECTED;
wire NLW_memory_reg_6_SBITERR_UNCONNECTED;
wire [31:4]NLW_memory_reg_6_DOADO_UNCONNECTED;
wire [31:0]NLW_memory_reg_6_DOBDO_UNCONNECTED;
wire [3:0]NLW_memory_reg_6_DOPADOP_UNCONNECTED;
wire [3:0]NLW_memory_reg_6_DOPBDOP_UNCONNECTED;
wire [7:0]NLW_memory_reg_6_ECCPARITY_UNCONNECTED;
wire [8:0]NLW_memory_reg_6_RDADDRECC_UNCONNECTED;
wire NLW_memory_reg_7_CASCADEOUTA_UNCONNECTED;
wire NLW_memory_reg_7_CASCADEOUTB_UNCONNECTED;
wire NLW_memory_reg_7_DBITERR_UNCONNECTED;
wire NLW_memory_reg_7_INJECTDBITERR_UNCONNECTED;
wire NLW_memory_reg_7_INJECTSBITERR_UNCONNECTED;
wire NLW_memory_reg_7_REGCEAREGCE_UNCONNECTED;
wire NLW_memory_reg_7_REGCEB_UNCONNECTED;
wire NLW_memory_reg_7_SBITERR_UNCONNECTED;
wire [31:4]NLW_memory_reg_7_DOADO_UNCONNECTED;
wire [31:0]NLW_memory_reg_7_DOBDO_UNCONNECTED;
wire [3:0]NLW_memory_reg_7_DOPADOP_UNCONNECTED;
wire [3:0]NLW_memory_reg_7_DOPBDOP_UNCONNECTED;
wire [7:0]NLW_memory_reg_7_ECCPARITY_UNCONNECTED;
wire [8:0]NLW_memory_reg_7_RDADDRECC_UNCONNECTED;
wire [2:0]\NLW_program_counter_reg[12]_i_2_CO_UNCONNECTED ;
wire [3:0]\NLW_program_counter_reg[15]_i_2_CO_UNCONNECTED ;
wire [3:3]\NLW_program_counter_reg[15]_i_2_O_UNCONNECTED ;
wire [2:0]\NLW_program_counter_reg_rep[4]_i_2_CO_UNCONNECTED ;
wire [2:0]\NLW_program_counter_reg_rep[7]_i_4_CO_UNCONNECTED ;
wire [1:0]NLW_registers_reg_r1_0_15_0_5_DOD_UNCONNECTED;
wire [1:0]NLW_registers_reg_r1_0_15_12_17_DOD_UNCONNECTED;
wire [1:0]NLW_registers_reg_r1_0_15_18_23_DOD_UNCONNECTED;
wire [1:0]NLW_registers_reg_r1_0_15_24_29_DOD_UNCONNECTED;
wire [1:0]NLW_registers_reg_r1_0_15_30_31_DOB_UNCONNECTED;
wire [1:0]NLW_registers_reg_r1_0_15_30_31_DOC_UNCONNECTED;
wire [1:0]NLW_registers_reg_r1_0_15_30_31_DOD_UNCONNECTED;
wire [1:0]NLW_registers_reg_r1_0_15_6_11_DOD_UNCONNECTED;
wire [1:0]NLW_registers_reg_r2_0_15_0_5_DOD_UNCONNECTED;
wire [1:0]NLW_registers_reg_r2_0_15_12_17_DOD_UNCONNECTED;
wire [1:0]NLW_registers_reg_r2_0_15_18_23_DOD_UNCONNECTED;
wire [1:0]NLW_registers_reg_r2_0_15_24_29_DOD_UNCONNECTED;
wire [1:0]NLW_registers_reg_r2_0_15_30_31_DOB_UNCONNECTED;
wire [1:0]NLW_registers_reg_r2_0_15_30_31_DOC_UNCONNECTED;
wire [1:0]NLW_registers_reg_r2_0_15_30_31_DOD_UNCONNECTED;
wire [1:0]NLW_registers_reg_r2_0_15_6_11_DOD_UNCONNECTED;
wire [2:0]\NLW_result_reg[11]_i_3_CO_UNCONNECTED ;
wire [2:0]\NLW_result_reg[11]_i_4_CO_UNCONNECTED ;
wire [2:0]\NLW_result_reg[12]_i_3_CO_UNCONNECTED ;
wire [2:0]\NLW_result_reg[15]_i_3_CO_UNCONNECTED ;
wire [2:0]\NLW_result_reg[15]_i_4_CO_UNCONNECTED ;
wire [2:0]\NLW_result_reg[16]_i_3_CO_UNCONNECTED ;
wire [3:3]\NLW_result_reg[16]_i_3_O_UNCONNECTED ;
wire [2:0]\NLW_result_reg[19]_i_3_CO_UNCONNECTED ;
wire [2:0]\NLW_result_reg[19]_i_4_CO_UNCONNECTED ;
wire [2:0]\NLW_result_reg[23]_i_3_CO_UNCONNECTED ;
wire [2:0]\NLW_result_reg[23]_i_4_CO_UNCONNECTED ;
wire [2:0]\NLW_result_reg[27]_i_3_CO_UNCONNECTED ;
wire [2:0]\NLW_result_reg[27]_i_4_CO_UNCONNECTED ;
wire [3:0]\NLW_result_reg[31]_i_6_CO_UNCONNECTED ;
wire [3:0]\NLW_result_reg[31]_i_7_CO_UNCONNECTED ;
wire [2:0]\NLW_result_reg[3]_i_3_CO_UNCONNECTED ;
wire [2:0]\NLW_result_reg[3]_i_4_CO_UNCONNECTED ;
wire [2:0]\NLW_result_reg[4]_i_3_CO_UNCONNECTED ;
wire [2:0]\NLW_result_reg[7]_i_3_CO_UNCONNECTED ;
wire [2:0]\NLW_result_reg[7]_i_4_CO_UNCONNECTED ;
wire [2:0]\NLW_result_reg[8]_i_3_CO_UNCONNECTED ;
FDRE \address_a_2_reg[0]
(.C(ETH_CLK_OBUF),
.CE(opcode_20),
.D(address_a[0]),
.Q(address_a_2[0]),
.R(1'b0));
FDRE \address_a_2_reg[1]
(.C(ETH_CLK_OBUF),
.CE(opcode_20),
.D(address_a[1]),
.Q(address_a_2[1]),
.R(1'b0));
FDRE \address_a_2_reg[2]
(.C(ETH_CLK_OBUF),
.CE(opcode_20),
.D(address_a[2]),
.Q(address_a_2[2]),
.R(1'b0));
FDRE \address_a_2_reg[3]
(.C(ETH_CLK_OBUF),
.CE(opcode_20),
.D(address_a[3]),
.Q(address_a_2[3]),
.R(1'b0));
FDRE \address_b_2_reg[0]
(.C(ETH_CLK_OBUF),
.CE(opcode_20),
.D(\instruction_reg_n_0_[0] ),
.Q(address_b_2[0]),
.R(1'b0));
FDRE \address_b_2_reg[1]
(.C(ETH_CLK_OBUF),
.CE(opcode_20),
.D(\instruction_reg_n_0_[1] ),
.Q(address_b_2[1]),
.R(1'b0));
FDRE \address_b_2_reg[2]
(.C(ETH_CLK_OBUF),
.CE(opcode_20),
.D(\instruction_reg_n_0_[2] ),
.Q(address_b_2[2]),
.R(1'b0));
FDRE \address_b_2_reg[3]
(.C(ETH_CLK_OBUF),
.CE(opcode_20),
.D(\instruction_reg_n_0_[3] ),
.Q(address_b_2[3]),
.R(1'b0));
FDRE \address_z_2_reg[0]
(.C(ETH_CLK_OBUF),
.CE(opcode_20),
.D(address_z[0]),
.Q(address_z_2[0]),
.R(1'b0));
FDRE \address_z_2_reg[1]
(.C(ETH_CLK_OBUF),
.CE(opcode_20),
.D(address_z[1]),
.Q(address_z_2[1]),
.R(1'b0));
FDRE \address_z_2_reg[2]
(.C(ETH_CLK_OBUF),
.CE(opcode_20),
.D(address_z[2]),
.Q(address_z_2[2]),
.R(1'b0));
FDRE \address_z_2_reg[3]
(.C(ETH_CLK_OBUF),
.CE(opcode_20),
.D(address_z[3]),
.Q(address_z_2[3]),
.R(1'b0));
LUT3 #(
.INIT(8'h40))
\address_z_3[3]_i_1
(.I0(\state_reg_n_0_[2] ),
.I1(\state_reg_n_0_[1] ),
.I2(\state_reg_n_0_[0] ),
.O(\address_z_3[3]_i_1_n_0 ));
FDRE \address_z_3_reg[0]
(.C(ETH_CLK_OBUF),
.CE(\address_z_3[3]_i_1_n_0 ),
.D(address_z_2[0]),
.Q(address_z_3[0]),
.R(INTERNAL_RST_reg));
FDRE \address_z_3_reg[1]
(.C(ETH_CLK_OBUF),
.CE(\address_z_3[3]_i_1_n_0 ),
.D(address_z_2[1]),
.Q(address_z_3[1]),
.R(INTERNAL_RST_reg));
FDRE \address_z_3_reg[2]
(.C(ETH_CLK_OBUF),
.CE(\address_z_3[3]_i_1_n_0 ),
.D(address_z_2[2]),
.Q(address_z_3[2]),
.R(INTERNAL_RST_reg));
FDRE \address_z_3_reg[3]
(.C(ETH_CLK_OBUF),
.CE(\address_z_3[3]_i_1_n_0 ),
.D(address_z_2[3]),
.Q(address_z_3[3]),
.R(INTERNAL_RST_reg));
LUT6 #(
.INIT(64'hF001000000F05200))
\instruction[0]_i_4
(.I0(\program_counter_reg_rep_n_0_[2] ),
.I1(\program_counter_reg_rep_n_0_[7] ),
.I2(\program_counter_reg_rep_n_0_[6] ),
.I3(\program_counter_reg_rep_n_0_[5] ),
.I4(\program_counter_reg_rep_n_0_[4] ),
.I5(\program_counter_reg_rep_n_0_[3] ),
.O(\instruction[0]_i_4_n_0 ));
LUT6 #(
.INIT(64'h03A0A8E454A04452))
\instruction[0]_i_5
(.I0(\program_counter_reg_rep_n_0_[2] ),
.I1(\program_counter_reg_rep_n_0_[7] ),
.I2(\program_counter_reg_rep_n_0_[6] ),
.I3(\program_counter_reg_rep_n_0_[4] ),
.I4(\program_counter_reg_rep_n_0_[5] ),
.I5(\program_counter_reg_rep_n_0_[3] ),
.O(\instruction[0]_i_5_n_0 ));
LUT6 #(
.INIT(64'h050F55AA004622FC))
\instruction[0]_i_6
(.I0(\program_counter_reg_rep_n_0_[2] ),
.I1(\program_counter_reg_rep_n_0_[7] ),
.I2(\program_counter_reg_rep_n_0_[6] ),
.I3(\program_counter_reg_rep_n_0_[3] ),
.I4(\program_counter_reg_rep_n_0_[5] ),
.I5(\program_counter_reg_rep_n_0_[4] ),
.O(\instruction[0]_i_6_n_0 ));
LUT6 #(
.INIT(64'h05EE010002452252))
\instruction[0]_i_7
(.I0(\program_counter_reg_rep_n_0_[2] ),
.I1(\program_counter_reg_rep_n_0_[7] ),
.I2(\program_counter_reg_rep_n_0_[6] ),
.I3(\program_counter_reg_rep_n_0_[3] ),
.I4(\program_counter_reg_rep_n_0_[4] ),
.I5(\program_counter_reg_rep_n_0_[5] ),
.O(\instruction[0]_i_7_n_0 ));
LUT5 #(
.INIT(32'h8888B888))
\instruction[15]_i_2
(.I0(\instruction[15]_i_4_n_0 ),
.I1(\program_counter_reg_rep_n_0_[1] ),
.I2(\program_counter_reg_rep_n_0_[6] ),
.I3(\instruction[15]_i_5_n_0 ),
.I4(\program_counter_reg_rep_n_0_[2] ),
.O(\instruction[15]_i_2_n_0 ));
LUT6 #(
.INIT(64'h0008FFFF00080000))
\instruction[15]_i_3
(.I0(\program_counter_reg_rep_n_0_[6] ),
.I1(\instruction[15]_i_6_n_0 ),
.I2(\program_counter_reg_rep_n_0_[3] ),
.I3(\program_counter_reg_rep_n_0_[2] ),
.I4(\program_counter_reg_rep_n_0_[1] ),
.I5(\instruction[15]_i_7_n_0 ),
.O(\instruction[15]_i_3_n_0 ));
LUT6 #(
.INIT(64'h0A50500508444000))
\instruction[15]_i_4
(.I0(\program_counter_reg_rep_n_0_[2] ),
.I1(\program_counter_reg_rep_n_0_[7] ),
.I2(\program_counter_reg_rep_n_0_[5] ),
.I3(\program_counter_reg_rep_n_0_[4] ),
.I4(\program_counter_reg_rep_n_0_[3] ),
.I5(\program_counter_reg_rep_n_0_[6] ),
.O(\instruction[15]_i_4_n_0 ));
LUT3 #(
.INIT(8'h94))
\instruction[15]_i_5
(.I0(\program_counter_reg_rep_n_0_[3] ),
.I1(\program_counter_reg_rep_n_0_[4] ),
.I2(\program_counter_reg_rep_n_0_[5] ),
.O(\instruction[15]_i_5_n_0 ));
LUT2 #(
.INIT(4'h1))
\instruction[15]_i_6
(.I0(\program_counter_reg_rep_n_0_[5] ),
.I1(\program_counter_reg_rep_n_0_[4] ),
.O(\instruction[15]_i_6_n_0 ));
LUT6 #(
.INIT(64'hC3000044C0000040))
\instruction[15]_i_7
(.I0(\program_counter_reg_rep_n_0_[5] ),
.I1(\program_counter_reg_rep_n_0_[2] ),
.I2(\program_counter_reg_rep_n_0_[6] ),
.I3(\program_counter_reg_rep_n_0_[4] ),
.I4(\program_counter_reg_rep_n_0_[3] ),
.I5(\program_counter_reg_rep_n_0_[7] ),
.O(\instruction[15]_i_7_n_0 ));
LUT6 #(
.INIT(64'hAD8850A08AF8A8F4))
\instruction[16]_i_4
(.I0(\program_counter_reg_rep_n_0_[2] ),
.I1(\program_counter_reg_rep_n_0_[7] ),
.I2(\program_counter_reg_rep_n_0_[6] ),
.I3(\program_counter_reg_rep_n_0_[4] ),
.I4(\program_counter_reg_rep_n_0_[5] ),
.I5(\program_counter_reg_rep_n_0_[3] ),
.O(\instruction[16]_i_4_n_0 ));
LUT6 #(
.INIT(64'h8FD8EC44A8F8E4F9))
\instruction[16]_i_5
(.I0(\program_counter_reg_rep_n_0_[2] ),
.I1(\program_counter_reg_rep_n_0_[7] ),
.I2(\program_counter_reg_rep_n_0_[6] ),
.I3(\program_counter_reg_rep_n_0_[3] ),
.I4(\program_counter_reg_rep_n_0_[5] ),
.I5(\program_counter_reg_rep_n_0_[4] ),
.O(\instruction[16]_i_5_n_0 ));
LUT6 #(
.INIT(64'h0FA0F4F80050CCEC))
\instruction[16]_i_6
(.I0(\program_counter_reg_rep_n_0_[2] ),
.I1(\program_counter_reg_rep_n_0_[7] ),
.I2(\program_counter_reg_rep_n_0_[6] ),
.I3(\program_counter_reg_rep_n_0_[4] ),
.I4(\program_counter_reg_rep_n_0_[5] ),
.I5(\program_counter_reg_rep_n_0_[3] ),
.O(\instruction[16]_i_6_n_0 ));
LUT6 #(
.INIT(64'hDD00F8F45A0050F0))
\instruction[16]_i_7
(.I0(\program_counter_reg_rep_n_0_[2] ),
.I1(\program_counter_reg_rep_n_0_[7] ),
.I2(\program_counter_reg_rep_n_0_[6] ),
.I3(\program_counter_reg_rep_n_0_[4] ),
.I4(\program_counter_reg_rep_n_0_[5] ),
.I5(\program_counter_reg_rep_n_0_[3] ),
.O(\instruction[16]_i_7_n_0 ));
LUT6 #(
.INIT(64'h21CE54EEAAF921FC))
\instruction[17]_i_4
(.I0(\program_counter_reg_rep_n_0_[2] ),
.I1(\program_counter_reg_rep_n_0_[7] ),
.I2(\program_counter_reg_rep_n_0_[6] ),
.I3(\program_counter_reg_rep_n_0_[3] ),
.I4(\program_counter_reg_rep_n_0_[5] ),
.I5(\program_counter_reg_rep_n_0_[4] ),
.O(\instruction[17]_i_4_n_0 ));
LUT6 #(
.INIT(64'hDF7564BAED5476B9))
\instruction[17]_i_5
(.I0(\program_counter_reg_rep_n_0_[2] ),
.I1(\program_counter_reg_rep_n_0_[7] ),
.I2(\program_counter_reg_rep_n_0_[6] ),
.I3(\program_counter_reg_rep_n_0_[3] ),
.I4(\program_counter_reg_rep_n_0_[4] ),
.I5(\program_counter_reg_rep_n_0_[5] ),
.O(\instruction[17]_i_5_n_0 ));
LUT6 #(
.INIT(64'hCF98FDB8FECDFCEE))
\instruction[17]_i_6
(.I0(\program_counter_reg_rep_n_0_[2] ),
.I1(\program_counter_reg_rep_n_0_[7] ),
.I2(\program_counter_reg_rep_n_0_[6] ),
.I3(\program_counter_reg_rep_n_0_[3] ),
.I4(\program_counter_reg_rep_n_0_[4] ),
.I5(\program_counter_reg_rep_n_0_[5] ),
.O(\instruction[17]_i_6_n_0 ));
LUT6 #(
.INIT(64'hFD12B8B246017530))
\instruction[17]_i_7
(.I0(\program_counter_reg_rep_n_0_[2] ),
.I1(\program_counter_reg_rep_n_0_[7] ),
.I2(\program_counter_reg_rep_n_0_[6] ),
.I3(\program_counter_reg_rep_n_0_[3] ),
.I4(\program_counter_reg_rep_n_0_[5] ),
.I5(\program_counter_reg_rep_n_0_[4] ),
.O(\instruction[17]_i_7_n_0 ));
LUT6 #(
.INIT(64'hBB838C3888808800))
\instruction[18]_i_4
(.I0(\program_counter_reg_rep_n_0_[7] ),
.I1(\program_counter_reg_rep_n_0_[2] ),
.I2(\program_counter_reg_rep_n_0_[4] ),
.I3(\program_counter_reg_rep_n_0_[5] ),
.I4(\program_counter_reg_rep_n_0_[3] ),
.I5(\program_counter_reg_rep_n_0_[6] ),
.O(\instruction[18]_i_4_n_0 ));
LUT6 #(
.INIT(64'h88D858D488880884))
\instruction[18]_i_5
(.I0(\program_counter_reg_rep_n_0_[2] ),
.I1(\program_counter_reg_rep_n_0_[7] ),
.I2(\program_counter_reg_rep_n_0_[3] ),
.I3(\program_counter_reg_rep_n_0_[4] ),
.I4(\program_counter_reg_rep_n_0_[5] ),
.I5(\program_counter_reg_rep_n_0_[6] ),
.O(\instruction[18]_i_5_n_0 ));
LUT6 #(
.INIT(64'hC8808C3888008800))
\instruction[18]_i_6
(.I0(\program_counter_reg_rep_n_0_[7] ),
.I1(\program_counter_reg_rep_n_0_[2] ),
.I2(\program_counter_reg_rep_n_0_[3] ),
.I3(\program_counter_reg_rep_n_0_[5] ),
.I4(\program_counter_reg_rep_n_0_[4] ),
.I5(\program_counter_reg_rep_n_0_[6] ),
.O(\instruction[18]_i_6_n_0 ));
LUT6 #(
.INIT(64'hCEEC0000CDDC0000))
\instruction[18]_i_7
(.I0(\program_counter_reg_rep_n_0_[2] ),
.I1(\program_counter_reg_rep_n_0_[7] ),
.I2(\program_counter_reg_rep_n_0_[6] ),
.I3(\program_counter_reg_rep_n_0_[4] ),
.I4(\program_counter_reg_rep_n_0_[5] ),
.I5(\program_counter_reg_rep_n_0_[3] ),
.O(\instruction[18]_i_7_n_0 ));
LUT6 #(
.INIT(64'h0F0000000C004040))
\instruction[19]_i_4
(.I0(\program_counter_reg_rep_n_0_[2] ),
.I1(\program_counter_reg_rep_n_0_[7] ),
.I2(\program_counter_reg_rep_n_0_[3] ),
.I3(\program_counter_reg_rep_n_0_[5] ),
.I4(\program_counter_reg_rep_n_0_[4] ),
.I5(\program_counter_reg_rep_n_0_[6] ),
.O(\instruction[19]_i_4_n_0 ));
LUT5 #(
.INIT(32'h80200000))
\instruction[19]_i_5
(.I0(\program_counter_reg_rep_n_0_[6] ),
.I1(\program_counter_reg_rep_n_0_[3] ),
.I2(\program_counter_reg_rep_n_0_[4] ),
.I3(\program_counter_reg_rep_n_0_[5] ),
.I4(\program_counter_reg_rep_n_0_[2] ),
.O(\instruction[19]_i_5_n_0 ));
LUT6 #(
.INIT(64'h3000C30000008000))
\instruction[19]_i_6
(.I0(\program_counter_reg_rep_n_0_[7] ),
.I1(\program_counter_reg_rep_n_0_[2] ),
.I2(\program_counter_reg_rep_n_0_[5] ),
.I3(\program_counter_reg_rep_n_0_[4] ),
.I4(\program_counter_reg_rep_n_0_[3] ),
.I5(\program_counter_reg_rep_n_0_[6] ),
.O(\instruction[19]_i_6_n_0 ));
LUT6 #(
.INIT(64'h0A0050004848C88C))
\instruction[19]_i_7
(.I0(\program_counter_reg_rep_n_0_[2] ),
.I1(\program_counter_reg_rep_n_0_[7] ),
.I2(\program_counter_reg_rep_n_0_[3] ),
.I3(\program_counter_reg_rep_n_0_[5] ),
.I4(\program_counter_reg_rep_n_0_[4] ),
.I5(\program_counter_reg_rep_n_0_[6] ),
.O(\instruction[19]_i_7_n_0 ));
LUT6 #(
.INIT(64'h5251424061405040))
\instruction[1]_i_4
(.I0(\program_counter_reg_rep_n_0_[2] ),
.I1(\program_counter_reg_rep_n_0_[7] ),
.I2(\program_counter_reg_rep_n_0_[5] ),
.I3(\program_counter_reg_rep_n_0_[6] ),
.I4(\program_counter_reg_rep_n_0_[4] ),
.I5(\program_counter_reg_rep_n_0_[3] ),
.O(\instruction[1]_i_4_n_0 ));
LUT6 #(
.INIT(64'hCD54A80256456510))
\instruction[1]_i_5
(.I0(\program_counter_reg_rep_n_0_[2] ),
.I1(\program_counter_reg_rep_n_0_[7] ),
.I2(\program_counter_reg_rep_n_0_[6] ),
.I3(\program_counter_reg_rep_n_0_[3] ),
.I4(\program_counter_reg_rep_n_0_[5] ),
.I5(\program_counter_reg_rep_n_0_[4] ),
.O(\instruction[1]_i_5_n_0 ));
LUT6 #(
.INIT(64'h64476522444602B8))
\instruction[1]_i_6
(.I0(\program_counter_reg_rep_n_0_[2] ),
.I1(\program_counter_reg_rep_n_0_[7] ),
.I2(\program_counter_reg_rep_n_0_[6] ),
.I3(\program_counter_reg_rep_n_0_[3] ),
.I4(\program_counter_reg_rep_n_0_[5] ),
.I5(\program_counter_reg_rep_n_0_[4] ),
.O(\instruction[1]_i_6_n_0 ));
LUT6 #(
.INIT(64'h4445000202000298))
\instruction[1]_i_7
(.I0(\program_counter_reg_rep_n_0_[2] ),
.I1(\program_counter_reg_rep_n_0_[7] ),
.I2(\program_counter_reg_rep_n_0_[6] ),
.I3(\program_counter_reg_rep_n_0_[5] ),
.I4(\program_counter_reg_rep_n_0_[4] ),
.I5(\program_counter_reg_rep_n_0_[3] ),
.O(\instruction[1]_i_7_n_0 ));
LUT6 #(
.INIT(64'hA00000500050A0A1))
\instruction[20]_i_4
(.I0(\program_counter_reg_rep_n_0_[2] ),
.I1(\program_counter_reg_rep_n_0_[7] ),
.I2(\program_counter_reg_rep_n_0_[6] ),
.I3(\program_counter_reg_rep_n_0_[4] ),
.I4(\program_counter_reg_rep_n_0_[5] ),
.I5(\program_counter_reg_rep_n_0_[3] ),
.O(\instruction[20]_i_4_n_0 ));
LUT6 #(
.INIT(64'h8AE4F84454F04451))
\instruction[20]_i_5
(.I0(\program_counter_reg_rep_n_0_[2] ),
.I1(\program_counter_reg_rep_n_0_[7] ),
.I2(\program_counter_reg_rep_n_0_[6] ),
.I3(\program_counter_reg_rep_n_0_[4] ),
.I4(\program_counter_reg_rep_n_0_[5] ),
.I5(\program_counter_reg_rep_n_0_[3] ),
.O(\instruction[20]_i_5_n_0 ));
LUT6 #(
.INIT(64'h0500F4A8000008AC))
\instruction[20]_i_6
(.I0(\program_counter_reg_rep_n_0_[2] ),
.I1(\program_counter_reg_rep_n_0_[7] ),
.I2(\program_counter_reg_rep_n_0_[6] ),
.I3(\program_counter_reg_rep_n_0_[4] ),
.I4(\program_counter_reg_rep_n_0_[5] ),
.I5(\program_counter_reg_rep_n_0_[3] ),
.O(\instruction[20]_i_6_n_0 ));
LUT6 #(
.INIT(64'h00FFEC0005CCFF00))
\instruction[20]_i_7
(.I0(\program_counter_reg_rep_n_0_[2] ),
.I1(\program_counter_reg_rep_n_0_[7] ),
.I2(\program_counter_reg_rep_n_0_[3] ),
.I3(\program_counter_reg_rep_n_0_[6] ),
.I4(\program_counter_reg_rep_n_0_[5] ),
.I5(\program_counter_reg_rep_n_0_[4] ),
.O(\instruction[20]_i_7_n_0 ));
LUT6 #(
.INIT(64'h20551010AA5421A3))
\instruction[21]_i_4
(.I0(\program_counter_reg_rep_n_0_[2] ),
.I1(\program_counter_reg_rep_n_0_[7] ),
.I2(\program_counter_reg_rep_n_0_[6] ),
.I3(\program_counter_reg_rep_n_0_[4] ),
.I4(\program_counter_reg_rep_n_0_[3] ),
.I5(\program_counter_reg_rep_n_0_[5] ),
.O(\instruction[21]_i_4_n_0 ));
LUT6 #(
.INIT(64'hEEFC5466EE45B9F9))
\instruction[21]_i_5
(.I0(\program_counter_reg_rep_n_0_[2] ),
.I1(\program_counter_reg_rep_n_0_[7] ),
.I2(\program_counter_reg_rep_n_0_[6] ),
.I3(\program_counter_reg_rep_n_0_[5] ),
.I4(\program_counter_reg_rep_n_0_[3] ),
.I5(\program_counter_reg_rep_n_0_[4] ),
.O(\instruction[21]_i_5_n_0 ));
LUT6 #(
.INIT(64'h55AFF5D80052AAFC))
\instruction[21]_i_6
(.I0(\program_counter_reg_rep_n_0_[2] ),
.I1(\program_counter_reg_rep_n_0_[7] ),
.I2(\program_counter_reg_rep_n_0_[6] ),
.I3(\program_counter_reg_rep_n_0_[3] ),
.I4(\program_counter_reg_rep_n_0_[5] ),
.I5(\program_counter_reg_rep_n_0_[4] ),
.O(\instruction[21]_i_6_n_0 ));
LUT6 #(
.INIT(64'h0FA25F8955F854F6))
\instruction[21]_i_7
(.I0(\program_counter_reg_rep_n_0_[2] ),
.I1(\program_counter_reg_rep_n_0_[7] ),
.I2(\program_counter_reg_rep_n_0_[6] ),
.I3(\program_counter_reg_rep_n_0_[5] ),
.I4(\program_counter_reg_rep_n_0_[3] ),
.I5(\program_counter_reg_rep_n_0_[4] ),
.O(\instruction[21]_i_7_n_0 ));
LUT6 #(
.INIT(64'hAA80AA000080280C))
\instruction[22]_i_4
(.I0(\program_counter_reg_rep_n_0_[2] ),
.I1(\program_counter_reg_rep_n_0_[6] ),
.I2(\program_counter_reg_rep_n_0_[4] ),
.I3(\program_counter_reg_rep_n_0_[5] ),
.I4(\program_counter_reg_rep_n_0_[3] ),
.I5(\program_counter_reg_rep_n_0_[7] ),
.O(\instruction[22]_i_4_n_0 ));
LUT6 #(
.INIT(64'h8888300488880000))
\instruction[22]_i_5
(.I0(\program_counter_reg_rep_n_0_[7] ),
.I1(\program_counter_reg_rep_n_0_[2] ),
.I2(\program_counter_reg_rep_n_0_[3] ),
.I3(\program_counter_reg_rep_n_0_[4] ),
.I4(\program_counter_reg_rep_n_0_[5] ),
.I5(\program_counter_reg_rep_n_0_[6] ),
.O(\instruction[22]_i_5_n_0 ));
LUT6 #(
.INIT(64'h0000200000152001))
\instruction[22]_i_6
(.I0(\program_counter_reg_rep_n_0_[2] ),
.I1(\program_counter_reg_rep_n_0_[3] ),
.I2(\program_counter_reg_rep_n_0_[5] ),
.I3(\program_counter_reg_rep_n_0_[4] ),
.I4(\program_counter_reg_rep_n_0_[6] ),
.I5(\program_counter_reg_rep_n_0_[7] ),
.O(\instruction[22]_i_6_n_0 ));
LUT5 #(
.INIT(32'h20C01000))
\instruction[22]_i_7
(.I0(\program_counter_reg_rep_n_0_[2] ),
.I1(\program_counter_reg_rep_n_0_[6] ),
.I2(\program_counter_reg_rep_n_0_[4] ),
.I3(\program_counter_reg_rep_n_0_[5] ),
.I4(\program_counter_reg_rep_n_0_[3] ),
.O(\instruction[22]_i_7_n_0 ));
LUT6 #(
.INIT(64'h56E54554A0020208))
\instruction[23]_i_4
(.I0(\program_counter_reg_rep_n_0_[2] ),
.I1(\program_counter_reg_rep_n_0_[7] ),
.I2(\program_counter_reg_rep_n_0_[6] ),
.I3(\program_counter_reg_rep_n_0_[3] ),
.I4(\program_counter_reg_rep_n_0_[5] ),
.I5(\program_counter_reg_rep_n_0_[4] ),
.O(\instruction[23]_i_4_n_0 ));
LUT6 #(
.INIT(64'h54A0550046190846))
\instruction[23]_i_5
(.I0(\program_counter_reg_rep_n_0_[2] ),
.I1(\program_counter_reg_rep_n_0_[7] ),
.I2(\program_counter_reg_rep_n_0_[6] ),
.I3(\program_counter_reg_rep_n_0_[3] ),
.I4(\program_counter_reg_rep_n_0_[4] ),
.I5(\program_counter_reg_rep_n_0_[5] ),
.O(\instruction[23]_i_5_n_0 ));
LUT6 #(
.INIT(64'h2010002202010500))
\instruction[23]_i_6
(.I0(\program_counter_reg_rep_n_0_[2] ),
.I1(\program_counter_reg_rep_n_0_[7] ),
.I2(\program_counter_reg_rep_n_0_[6] ),
.I3(\program_counter_reg_rep_n_0_[3] ),
.I4(\program_counter_reg_rep_n_0_[5] ),
.I5(\program_counter_reg_rep_n_0_[4] ),
.O(\instruction[23]_i_6_n_0 ));
LUT6 #(
.INIT(64'h62400A2840D20A49))
\instruction[23]_i_7
(.I0(\program_counter_reg_rep_n_0_[2] ),
.I1(\program_counter_reg_rep_n_0_[7] ),
.I2(\program_counter_reg_rep_n_0_[4] ),
.I3(\program_counter_reg_rep_n_0_[5] ),
.I4(\program_counter_reg_rep_n_0_[3] ),
.I5(\program_counter_reg_rep_n_0_[6] ),
.O(\instruction[23]_i_7_n_0 ));
LUT6 #(
.INIT(64'hFFEFFFDFCEC4C8C8))
\instruction[24]_i_4
(.I0(\program_counter_reg_rep_n_0_[2] ),
.I1(\program_counter_reg_rep_n_0_[7] ),
.I2(\program_counter_reg_rep_n_0_[3] ),
.I3(\program_counter_reg_rep_n_0_[5] ),
.I4(\program_counter_reg_rep_n_0_[4] ),
.I5(\program_counter_reg_rep_n_0_[6] ),
.O(\instruction[24]_i_4_n_0 ));
LUT6 #(
.INIT(64'hFEFCFCCCFCF8FCFD))
\instruction[24]_i_5
(.I0(\program_counter_reg_rep_n_0_[2] ),
.I1(\program_counter_reg_rep_n_0_[7] ),
.I2(\program_counter_reg_rep_n_0_[6] ),
.I3(\program_counter_reg_rep_n_0_[4] ),
.I4(\program_counter_reg_rep_n_0_[5] ),
.I5(\program_counter_reg_rep_n_0_[3] ),
.O(\instruction[24]_i_5_n_0 ));
LUT6 #(
.INIT(64'hF588F4FCFA50D8FC))
\instruction[24]_i_6
(.I0(\program_counter_reg_rep_n_0_[2] ),
.I1(\program_counter_reg_rep_n_0_[7] ),
.I2(\program_counter_reg_rep_n_0_[6] ),
.I3(\program_counter_reg_rep_n_0_[4] ),
.I4(\program_counter_reg_rep_n_0_[5] ),
.I5(\program_counter_reg_rep_n_0_[3] ),
.O(\instruction[24]_i_6_n_0 ));
LUT6 #(
.INIT(64'hEDFFFAC8FDCCFFCC))
\instruction[24]_i_7
(.I0(\program_counter_reg_rep_n_0_[2] ),
.I1(\program_counter_reg_rep_n_0_[7] ),
.I2(\program_counter_reg_rep_n_0_[3] ),
.I3(\program_counter_reg_rep_n_0_[6] ),
.I4(\program_counter_reg_rep_n_0_[5] ),
.I5(\program_counter_reg_rep_n_0_[4] ),
.O(\instruction[24]_i_7_n_0 ));
LUT6 #(
.INIT(64'h45EC308A46452144))
\instruction[25]_i_4
(.I0(\program_counter_reg_rep_n_0_[2] ),
.I1(\program_counter_reg_rep_n_0_[7] ),
.I2(\program_counter_reg_rep_n_0_[6] ),
.I3(\program_counter_reg_rep_n_0_[3] ),
.I4(\program_counter_reg_rep_n_0_[5] ),
.I5(\program_counter_reg_rep_n_0_[4] ),
.O(\instruction[25]_i_4_n_0 ));
LUT6 #(
.INIT(64'h0189010000463200))
\instruction[25]_i_5
(.I0(\program_counter_reg_rep_n_0_[2] ),
.I1(\program_counter_reg_rep_n_0_[7] ),
.I2(\program_counter_reg_rep_n_0_[6] ),
.I3(\program_counter_reg_rep_n_0_[3] ),
.I4(\program_counter_reg_rep_n_0_[5] ),
.I5(\program_counter_reg_rep_n_0_[4] ),
.O(\instruction[25]_i_5_n_0 ));
LUT6 #(
.INIT(64'hCECEFDEC0A050052))
\instruction[25]_i_6
(.I0(\program_counter_reg_rep_n_0_[2] ),
.I1(\program_counter_reg_rep_n_0_[7] ),
.I2(\program_counter_reg_rep_n_0_[6] ),
.I3(\program_counter_reg_rep_n_0_[3] ),
.I4(\program_counter_reg_rep_n_0_[4] ),
.I5(\program_counter_reg_rep_n_0_[5] ),
.O(\instruction[25]_i_6_n_0 ));
LUT6 #(
.INIT(64'hD88804128A890108))
\instruction[25]_i_7
(.I0(\program_counter_reg_rep_n_0_[2] ),
.I1(\program_counter_reg_rep_n_0_[7] ),
.I2(\program_counter_reg_rep_n_0_[6] ),
.I3(\program_counter_reg_rep_n_0_[3] ),
.I4(\program_counter_reg_rep_n_0_[5] ),
.I5(\program_counter_reg_rep_n_0_[4] ),
.O(\instruction[25]_i_7_n_0 ));
LUT6 #(
.INIT(64'h20FF910020009000))
\instruction[26]_i_4
(.I0(\program_counter_reg_rep_n_0_[5] ),
.I1(\program_counter_reg_rep_n_0_[3] ),
.I2(\program_counter_reg_rep_n_0_[6] ),
.I3(\program_counter_reg_rep_n_0_[2] ),
.I4(\program_counter_reg_rep_n_0_[4] ),
.I5(\program_counter_reg_rep_n_0_[7] ),
.O(\instruction[26]_i_4_n_0 ));
LUT6 #(
.INIT(64'h5405A58A4400A088))
\instruction[26]_i_5
(.I0(\program_counter_reg_rep_n_0_[2] ),
.I1(\program_counter_reg_rep_n_0_[7] ),
.I2(\program_counter_reg_rep_n_0_[5] ),
.I3(\program_counter_reg_rep_n_0_[4] ),
.I4(\program_counter_reg_rep_n_0_[3] ),
.I5(\program_counter_reg_rep_n_0_[6] ),
.O(\instruction[26]_i_5_n_0 ));
LUT6 #(
.INIT(64'h0077000020201000))
\instruction[26]_i_6
(.I0(\program_counter_reg_rep_n_0_[2] ),
.I1(\program_counter_reg_rep_n_0_[4] ),
.I2(\program_counter_reg_rep_n_0_[7] ),
.I3(\program_counter_reg_rep_n_0_[3] ),
.I4(\program_counter_reg_rep_n_0_[5] ),
.I5(\program_counter_reg_rep_n_0_[6] ),
.O(\instruction[26]_i_6_n_0 ));
LUT6 #(
.INIT(64'hE5EA080840C00848))
\instruction[26]_i_7
(.I0(\program_counter_reg_rep_n_0_[2] ),
.I1(\program_counter_reg_rep_n_0_[7] ),
.I2(\program_counter_reg_rep_n_0_[3] ),
.I3(\program_counter_reg_rep_n_0_[5] ),
.I4(\program_counter_reg_rep_n_0_[4] ),
.I5(\program_counter_reg_rep_n_0_[6] ),
.O(\instruction[26]_i_7_n_0 ));
LUT6 #(
.INIT(64'h4000434000000000))
\instruction[27]_i_2
(.I0(\program_counter_reg_rep_n_0_[1] ),
.I1(\program_counter_reg_rep_n_0_[2] ),
.I2(\program_counter_reg_rep_n_0_[3] ),
.I3(\program_counter_reg_rep_n_0_[5] ),
.I4(\program_counter_reg_rep_n_0_[4] ),
.I5(\program_counter_reg_rep_n_0_[7] ),
.O(\instruction[27]_i_2_n_0 ));
LUT6 #(
.INIT(64'hC0A0C0A00F000000))
\instruction[27]_i_3
(.I0(\instruction[27]_i_4_n_0 ),
.I1(\instruction[27]_i_5_n_0 ),
.I2(\program_counter_reg_rep_n_0_[1] ),
.I3(\program_counter_reg_rep_n_0_[7] ),
.I4(\instruction[27]_i_6_n_0 ),
.I5(\program_counter_reg_rep_n_0_[2] ),
.O(\instruction[27]_i_3_n_0 ));
LUT4 #(
.INIT(16'h4000))
\instruction[27]_i_4
(.I0(\program_counter_reg_rep_n_0_[3] ),
.I1(\program_counter_reg_rep_n_0_[5] ),
.I2(\program_counter_reg_rep_n_0_[4] ),
.I3(\program_counter_reg_rep_n_0_[6] ),
.O(\instruction[27]_i_4_n_0 ));
LUT2 #(
.INIT(4'h2))
\instruction[27]_i_5
(.I0(\program_counter_reg_rep_n_0_[5] ),
.I1(\program_counter_reg_rep_n_0_[3] ),
.O(\instruction[27]_i_5_n_0 ));
LUT3 #(
.INIT(8'h04))
\instruction[27]_i_6
(.I0(\program_counter_reg_rep_n_0_[4] ),
.I1(\program_counter_reg_rep_n_0_[5] ),
.I2(\program_counter_reg_rep_n_0_[3] ),
.O(\instruction[27]_i_6_n_0 ));
LUT6 #(
.INIT(64'h55000550A151A200))
\instruction[2]_i_4
(.I0(\program_counter_reg_rep_n_0_[2] ),
.I1(\program_counter_reg_rep_n_0_[7] ),
.I2(\program_counter_reg_rep_n_0_[6] ),
.I3(\program_counter_reg_rep_n_0_[3] ),
.I4(\program_counter_reg_rep_n_0_[4] ),
.I5(\program_counter_reg_rep_n_0_[5] ),
.O(\instruction[2]_i_4_n_0 ));
LUT6 #(
.INIT(64'h055EAAE410000212))
\instruction[2]_i_5
(.I0(\program_counter_reg_rep_n_0_[2] ),
.I1(\program_counter_reg_rep_n_0_[7] ),
.I2(\program_counter_reg_rep_n_0_[6] ),
.I3(\program_counter_reg_rep_n_0_[4] ),
.I4(\program_counter_reg_rep_n_0_[5] ),
.I5(\program_counter_reg_rep_n_0_[3] ),
.O(\instruction[2]_i_5_n_0 ));
LUT6 #(
.INIT(64'h888800AA0045CD28))
\instruction[2]_i_6
(.I0(\program_counter_reg_rep_n_0_[2] ),
.I1(\program_counter_reg_rep_n_0_[4] ),
.I2(\program_counter_reg_rep_n_0_[7] ),
.I3(\program_counter_reg_rep_n_0_[5] ),
.I4(\program_counter_reg_rep_n_0_[3] ),
.I5(\program_counter_reg_rep_n_0_[6] ),
.O(\instruction[2]_i_6_n_0 ));
LUT6 #(
.INIT(64'h000A050000010210))
\instruction[2]_i_7
(.I0(\program_counter_reg_rep_n_0_[2] ),
.I1(\program_counter_reg_rep_n_0_[7] ),
.I2(\program_counter_reg_rep_n_0_[6] ),
.I3(\program_counter_reg_rep_n_0_[3] ),
.I4(\program_counter_reg_rep_n_0_[4] ),
.I5(\program_counter_reg_rep_n_0_[5] ),
.O(\instruction[2]_i_7_n_0 ));
LUT6 #(
.INIT(64'h1088139A8B518B44))
\instruction[3]_i_4
(.I0(\program_counter_reg_rep_n_0_[2] ),
.I1(\program_counter_reg_rep_n_0_[7] ),
.I2(\program_counter_reg_rep_n_0_[6] ),
.I3(\program_counter_reg_rep_n_0_[3] ),
.I4(\program_counter_reg_rep_n_0_[5] ),
.I5(\program_counter_reg_rep_n_0_[4] ),
.O(\instruction[3]_i_4_n_0 ));
LUT6 #(
.INIT(64'h00565547AB460010))
\instruction[3]_i_5
(.I0(\program_counter_reg_rep_n_0_[2] ),
.I1(\program_counter_reg_rep_n_0_[7] ),
.I2(\program_counter_reg_rep_n_0_[6] ),
.I3(\program_counter_reg_rep_n_0_[4] ),
.I4(\program_counter_reg_rep_n_0_[3] ),
.I5(\program_counter_reg_rep_n_0_[5] ),
.O(\instruction[3]_i_5_n_0 ));
LUT6 #(
.INIT(64'hEEEE465570510B2A))
\instruction[3]_i_6
(.I0(\program_counter_reg_rep_n_0_[2] ),
.I1(\program_counter_reg_rep_n_0_[7] ),
.I2(\program_counter_reg_rep_n_0_[5] ),
.I3(\program_counter_reg_rep_n_0_[6] ),
.I4(\program_counter_reg_rep_n_0_[3] ),
.I5(\program_counter_reg_rep_n_0_[4] ),
.O(\instruction[3]_i_6_n_0 ));
LUT6 #(
.INIT(64'h5041426200013331))
\instruction[3]_i_7
(.I0(\program_counter_reg_rep_n_0_[2] ),
.I1(\program_counter_reg_rep_n_0_[7] ),
.I2(\program_counter_reg_rep_n_0_[3] ),
.I3(\program_counter_reg_rep_n_0_[5] ),
.I4(\program_counter_reg_rep_n_0_[6] ),
.I5(\program_counter_reg_rep_n_0_[4] ),
.O(\instruction[3]_i_7_n_0 ));
LUT6 #(
.INIT(64'hB888B888B8BBB888))
\instruction[4]_i_1
(.I0(\instruction_reg[4]_i_2_n_0 ),
.I1(\program_counter_reg_rep_n_0_[0] ),
.I2(\instruction[4]_i_3_n_0 ),
.I3(\program_counter_reg_rep_n_0_[1] ),
.I4(\instruction[4]_i_4_n_0 ),
.I5(\program_counter_reg_rep_n_0_[2] ),
.O(\instruction[4]_i_1_n_0 ));
LUT6 #(
.INIT(64'h0054A84410000011))
\instruction[4]_i_3
(.I0(\program_counter_reg_rep_n_0_[2] ),
.I1(\program_counter_reg_rep_n_0_[7] ),
.I2(\program_counter_reg_rep_n_0_[6] ),
.I3(\program_counter_reg_rep_n_0_[4] ),
.I4(\program_counter_reg_rep_n_0_[5] ),
.I5(\program_counter_reg_rep_n_0_[3] ),
.O(\instruction[4]_i_3_n_0 ));
LUT4 #(
.INIT(16'h8600))
\instruction[4]_i_4
(.I0(\program_counter_reg_rep_n_0_[5] ),
.I1(\program_counter_reg_rep_n_0_[4] ),
.I2(\program_counter_reg_rep_n_0_[3] ),
.I3(\program_counter_reg_rep_n_0_[6] ),
.O(\instruction[4]_i_4_n_0 ));
LUT6 #(
.INIT(64'hCF000050C0300040))
\instruction[4]_i_5
(.I0(\program_counter_reg_rep_n_0_[5] ),
.I1(\program_counter_reg_rep_n_0_[6] ),
.I2(\program_counter_reg_rep_n_0_[2] ),
.I3(\program_counter_reg_rep_n_0_[3] ),
.I4(\program_counter_reg_rep_n_0_[4] ),
.I5(\program_counter_reg_rep_n_0_[7] ),
.O(\instruction[4]_i_5_n_0 ));
LUT6 #(
.INIT(64'h0000000001000004))
\instruction[4]_i_6
(.I0(\program_counter_reg_rep_n_0_[7] ),
.I1(\program_counter_reg_rep_n_0_[6] ),
.I2(\program_counter_reg_rep_n_0_[5] ),
.I3(\program_counter_reg_rep_n_0_[4] ),
.I4(\program_counter_reg_rep_n_0_[3] ),
.I5(\program_counter_reg_rep_n_0_[2] ),
.O(\instruction[4]_i_6_n_0 ));
LUT6 #(
.INIT(64'h54A1440244105600))
\instruction[5]_i_4
(.I0(\program_counter_reg_rep_n_0_[2] ),
.I1(\program_counter_reg_rep_n_0_[7] ),
.I2(\program_counter_reg_rep_n_0_[6] ),
.I3(\program_counter_reg_rep_n_0_[5] ),
.I4(\program_counter_reg_rep_n_0_[4] ),
.I5(\program_counter_reg_rep_n_0_[3] ),
.O(\instruction[5]_i_4_n_0 ));
LUT6 #(
.INIT(64'h44545544AA414412))
\instruction[5]_i_5
(.I0(\program_counter_reg_rep_n_0_[2] ),
.I1(\program_counter_reg_rep_n_0_[7] ),
.I2(\program_counter_reg_rep_n_0_[6] ),
.I3(\program_counter_reg_rep_n_0_[3] ),
.I4(\program_counter_reg_rep_n_0_[4] ),
.I5(\program_counter_reg_rep_n_0_[5] ),
.O(\instruction[5]_i_5_n_0 ));
LUT6 #(
.INIT(64'hA0A0000A0041A508))
\instruction[5]_i_6
(.I0(\program_counter_reg_rep_n_0_[2] ),
.I1(\program_counter_reg_rep_n_0_[7] ),
.I2(\program_counter_reg_rep_n_0_[4] ),
.I3(\program_counter_reg_rep_n_0_[5] ),
.I4(\program_counter_reg_rep_n_0_[3] ),
.I5(\program_counter_reg_rep_n_0_[6] ),
.O(\instruction[5]_i_6_n_0 ));
LUT6 #(
.INIT(64'h2000000020010048))
\instruction[5]_i_7
(.I0(\program_counter_reg_rep_n_0_[2] ),
.I1(\program_counter_reg_rep_n_0_[3] ),
.I2(\program_counter_reg_rep_n_0_[4] ),
.I3(\program_counter_reg_rep_n_0_[5] ),
.I4(\program_counter_reg_rep_n_0_[6] ),
.I5(\program_counter_reg_rep_n_0_[7] ),
.O(\instruction[5]_i_7_n_0 ));
LUT6 #(
.INIT(64'h10A1000200501000))
\instruction[6]_i_4
(.I0(\program_counter_reg_rep_n_0_[2] ),
.I1(\program_counter_reg_rep_n_0_[7] ),
.I2(\program_counter_reg_rep_n_0_[6] ),
.I3(\program_counter_reg_rep_n_0_[5] ),
.I4(\program_counter_reg_rep_n_0_[4] ),
.I5(\program_counter_reg_rep_n_0_[3] ),
.O(\instruction[6]_i_4_n_0 ));
LUT6 #(
.INIT(64'hCAD4D0C5CAC4C0C2))
\instruction[6]_i_5
(.I0(\program_counter_reg_rep_n_0_[2] ),
.I1(\program_counter_reg_rep_n_0_[7] ),
.I2(\program_counter_reg_rep_n_0_[5] ),
.I3(\program_counter_reg_rep_n_0_[4] ),
.I4(\program_counter_reg_rep_n_0_[3] ),
.I5(\program_counter_reg_rep_n_0_[6] ),
.O(\instruction[6]_i_5_n_0 ));
LUT6 #(
.INIT(64'hE000A402000101F8))
\instruction[6]_i_6
(.I0(\program_counter_reg_rep_n_0_[2] ),
.I1(\program_counter_reg_rep_n_0_[7] ),
.I2(\program_counter_reg_rep_n_0_[6] ),
.I3(\program_counter_reg_rep_n_0_[3] ),
.I4(\program_counter_reg_rep_n_0_[5] ),
.I5(\program_counter_reg_rep_n_0_[4] ),
.O(\instruction[6]_i_6_n_0 ));
LUT6 #(
.INIT(64'h0000010000000251))
\instruction[6]_i_7
(.I0(\program_counter_reg_rep_n_0_[2] ),
.I1(\program_counter_reg_rep_n_0_[7] ),
.I2(\program_counter_reg_rep_n_0_[6] ),
.I3(\program_counter_reg_rep_n_0_[3] ),
.I4(\program_counter_reg_rep_n_0_[5] ),
.I5(\program_counter_reg_rep_n_0_[4] ),
.O(\instruction[6]_i_7_n_0 ));
LUT6 #(
.INIT(64'h00000000FF208220))
\instruction[7]_i_4
(.I0(\program_counter_reg_rep_n_0_[6] ),
.I1(\program_counter_reg_rep_n_0_[3] ),
.I2(\program_counter_reg_rep_n_0_[4] ),
.I3(\program_counter_reg_rep_n_0_[5] ),
.I4(\program_counter_reg_rep_n_0_[7] ),
.I5(\program_counter_reg_rep_n_0_[2] ),
.O(\instruction[7]_i_4_n_0 ));
LUT6 #(
.INIT(64'h0A54500508440000))
\instruction[7]_i_5
(.I0(\program_counter_reg_rep_n_0_[2] ),
.I1(\program_counter_reg_rep_n_0_[7] ),
.I2(\program_counter_reg_rep_n_0_[5] ),
.I3(\program_counter_reg_rep_n_0_[4] ),
.I4(\program_counter_reg_rep_n_0_[3] ),
.I5(\program_counter_reg_rep_n_0_[6] ),
.O(\instruction[7]_i_5_n_0 ));
LUT6 #(
.INIT(64'hBB30303C88000008))
\instruction[7]_i_6
(.I0(\program_counter_reg_rep_n_0_[6] ),
.I1(\program_counter_reg_rep_n_0_[2] ),
.I2(\program_counter_reg_rep_n_0_[5] ),
.I3(\program_counter_reg_rep_n_0_[3] ),
.I4(\program_counter_reg_rep_n_0_[4] ),
.I5(\program_counter_reg_rep_n_0_[7] ),
.O(\instruction[7]_i_6_n_0 ));
LUT6 #(
.INIT(64'h0C00000308000000))
\instruction[7]_i_7
(.I0(\program_counter_reg_rep_n_0_[7] ),
.I1(\program_counter_reg_rep_n_0_[2] ),
.I2(\program_counter_reg_rep_n_0_[3] ),
.I3(\program_counter_reg_rep_n_0_[5] ),
.I4(\program_counter_reg_rep_n_0_[4] ),
.I5(\program_counter_reg_rep_n_0_[6] ),
.O(\instruction[7]_i_7_n_0 ));
FDRE \instruction_reg[0]
(.C(ETH_CLK_OBUF),
.CE(instruction0),
.D(\instruction_reg[0]_i_1_n_0 ),
.Q(\instruction_reg_n_0_[0] ),
.R(1'b0));
MUXF8 \instruction_reg[0]_i_1
(.I0(\instruction_reg[0]_i_2_n_0 ),
.I1(\instruction_reg[0]_i_3_n_0 ),
.O(\instruction_reg[0]_i_1_n_0 ),
.S(\program_counter_reg_rep_n_0_[0] ));
MUXF7 \instruction_reg[0]_i_2
(.I0(\instruction[0]_i_4_n_0 ),
.I1(\instruction[0]_i_5_n_0 ),
.O(\instruction_reg[0]_i_2_n_0 ),
.S(\program_counter_reg_rep_n_0_[1] ));
MUXF7 \instruction_reg[0]_i_3
(.I0(\instruction[0]_i_6_n_0 ),
.I1(\instruction[0]_i_7_n_0 ),
.O(\instruction_reg[0]_i_3_n_0 ),
.S(\program_counter_reg_rep_n_0_[1] ));
FDRE \instruction_reg[15]
(.C(ETH_CLK_OBUF),
.CE(instruction0),
.D(\instruction_reg[15]_i_1_n_0 ),
.Q(\instruction_reg_n_0_[15] ),
.R(1'b0));
MUXF7 \instruction_reg[15]_i_1
(.I0(\instruction[15]_i_2_n_0 ),
.I1(\instruction[15]_i_3_n_0 ),
.O(\instruction_reg[15]_i_1_n_0 ),
.S(\program_counter_reg_rep_n_0_[0] ));
FDRE \instruction_reg[16]
(.C(ETH_CLK_OBUF),
.CE(instruction0),
.D(\instruction_reg[16]_i_1_n_0 ),
.Q(address_a[0]),
.R(1'b0));
MUXF8 \instruction_reg[16]_i_1
(.I0(\instruction_reg[16]_i_2_n_0 ),
.I1(\instruction_reg[16]_i_3_n_0 ),
.O(\instruction_reg[16]_i_1_n_0 ),
.S(\program_counter_reg_rep_n_0_[0] ));
MUXF7 \instruction_reg[16]_i_2
(.I0(\instruction[16]_i_4_n_0 ),
.I1(\instruction[16]_i_5_n_0 ),
.O(\instruction_reg[16]_i_2_n_0 ),
.S(\program_counter_reg_rep_n_0_[1] ));
MUXF7 \instruction_reg[16]_i_3
(.I0(\instruction[16]_i_6_n_0 ),
.I1(\instruction[16]_i_7_n_0 ),
.O(\instruction_reg[16]_i_3_n_0 ),
.S(\program_counter_reg_rep_n_0_[1] ));
FDRE \instruction_reg[17]
(.C(ETH_CLK_OBUF),
.CE(instruction0),
.D(\instruction_reg[17]_i_1_n_0 ),
.Q(address_a[1]),
.R(1'b0));
MUXF8 \instruction_reg[17]_i_1
(.I0(\instruction_reg[17]_i_2_n_0 ),
.I1(\instruction_reg[17]_i_3_n_0 ),
.O(\instruction_reg[17]_i_1_n_0 ),
.S(\program_counter_reg_rep_n_0_[0] ));
MUXF7 \instruction_reg[17]_i_2
(.I0(\instruction[17]_i_4_n_0 ),
.I1(\instruction[17]_i_5_n_0 ),
.O(\instruction_reg[17]_i_2_n_0 ),
.S(\program_counter_reg_rep_n_0_[1] ));
MUXF7 \instruction_reg[17]_i_3
(.I0(\instruction[17]_i_6_n_0 ),
.I1(\instruction[17]_i_7_n_0 ),
.O(\instruction_reg[17]_i_3_n_0 ),
.S(\program_counter_reg_rep_n_0_[1] ));
FDRE \instruction_reg[18]
(.C(ETH_CLK_OBUF),
.CE(instruction0),
.D(\instruction_reg[18]_i_1_n_0 ),
.Q(address_a[2]),
.R(1'b0));
MUXF8 \instruction_reg[18]_i_1
(.I0(\instruction_reg[18]_i_2_n_0 ),
.I1(\instruction_reg[18]_i_3_n_0 ),
.O(\instruction_reg[18]_i_1_n_0 ),
.S(\program_counter_reg_rep_n_0_[0] ));
MUXF7 \instruction_reg[18]_i_2
(.I0(\instruction[18]_i_4_n_0 ),
.I1(\instruction[18]_i_5_n_0 ),
.O(\instruction_reg[18]_i_2_n_0 ),
.S(\program_counter_reg_rep_n_0_[1] ));
MUXF7 \instruction_reg[18]_i_3
(.I0(\instruction[18]_i_6_n_0 ),
.I1(\instruction[18]_i_7_n_0 ),
.O(\instruction_reg[18]_i_3_n_0 ),
.S(\program_counter_reg_rep_n_0_[1] ));
FDRE \instruction_reg[19]
(.C(ETH_CLK_OBUF),
.CE(instruction0),
.D(\instruction_reg[19]_i_1_n_0 ),
.Q(address_a[3]),
.R(1'b0));
MUXF8 \instruction_reg[19]_i_1
(.I0(\instruction_reg[19]_i_2_n_0 ),
.I1(\instruction_reg[19]_i_3_n_0 ),
.O(\instruction_reg[19]_i_1_n_0 ),
.S(\program_counter_reg_rep_n_0_[0] ));
MUXF7 \instruction_reg[19]_i_2
(.I0(\instruction[19]_i_4_n_0 ),
.I1(\instruction[19]_i_5_n_0 ),
.O(\instruction_reg[19]_i_2_n_0 ),
.S(\program_counter_reg_rep_n_0_[1] ));
MUXF7 \instruction_reg[19]_i_3
(.I0(\instruction[19]_i_6_n_0 ),
.I1(\instruction[19]_i_7_n_0 ),
.O(\instruction_reg[19]_i_3_n_0 ),
.S(\program_counter_reg_rep_n_0_[1] ));
FDRE \instruction_reg[1]
(.C(ETH_CLK_OBUF),
.CE(instruction0),
.D(\instruction_reg[1]_i_1_n_0 ),
.Q(\instruction_reg_n_0_[1] ),
.R(1'b0));
MUXF8 \instruction_reg[1]_i_1
(.I0(\instruction_reg[1]_i_2_n_0 ),
.I1(\instruction_reg[1]_i_3_n_0 ),
.O(\instruction_reg[1]_i_1_n_0 ),
.S(\program_counter_reg_rep_n_0_[0] ));
MUXF7 \instruction_reg[1]_i_2
(.I0(\instruction[1]_i_4_n_0 ),
.I1(\instruction[1]_i_5_n_0 ),
.O(\instruction_reg[1]_i_2_n_0 ),
.S(\program_counter_reg_rep_n_0_[1] ));
MUXF7 \instruction_reg[1]_i_3
(.I0(\instruction[1]_i_6_n_0 ),
.I1(\instruction[1]_i_7_n_0 ),
.O(\instruction_reg[1]_i_3_n_0 ),
.S(\program_counter_reg_rep_n_0_[1] ));
FDRE \instruction_reg[20]
(.C(ETH_CLK_OBUF),
.CE(instruction0),
.D(\instruction_reg[20]_i_1_n_0 ),
.Q(address_z[0]),
.R(1'b0));
MUXF8 \instruction_reg[20]_i_1
(.I0(\instruction_reg[20]_i_2_n_0 ),
.I1(\instruction_reg[20]_i_3_n_0 ),
.O(\instruction_reg[20]_i_1_n_0 ),
.S(\program_counter_reg_rep_n_0_[0] ));
MUXF7 \instruction_reg[20]_i_2
(.I0(\instruction[20]_i_4_n_0 ),
.I1(\instruction[20]_i_5_n_0 ),
.O(\instruction_reg[20]_i_2_n_0 ),
.S(\program_counter_reg_rep_n_0_[1] ));
MUXF7 \instruction_reg[20]_i_3
(.I0(\instruction[20]_i_6_n_0 ),
.I1(\instruction[20]_i_7_n_0 ),
.O(\instruction_reg[20]_i_3_n_0 ),
.S(\program_counter_reg_rep_n_0_[1] ));
FDRE \instruction_reg[21]
(.C(ETH_CLK_OBUF),
.CE(instruction0),
.D(\instruction_reg[21]_i_1_n_0 ),
.Q(address_z[1]),
.R(1'b0));
MUXF8 \instruction_reg[21]_i_1
(.I0(\instruction_reg[21]_i_2_n_0 ),
.I1(\instruction_reg[21]_i_3_n_0 ),
.O(\instruction_reg[21]_i_1_n_0 ),
.S(\program_counter_reg_rep_n_0_[0] ));
MUXF7 \instruction_reg[21]_i_2
(.I0(\instruction[21]_i_4_n_0 ),
.I1(\instruction[21]_i_5_n_0 ),
.O(\instruction_reg[21]_i_2_n_0 ),
.S(\program_counter_reg_rep_n_0_[1] ));
MUXF7 \instruction_reg[21]_i_3
(.I0(\instruction[21]_i_6_n_0 ),
.I1(\instruction[21]_i_7_n_0 ),
.O(\instruction_reg[21]_i_3_n_0 ),
.S(\program_counter_reg_rep_n_0_[1] ));
FDRE \instruction_reg[22]
(.C(ETH_CLK_OBUF),
.CE(instruction0),
.D(\instruction_reg[22]_i_1_n_0 ),
.Q(address_z[2]),
.R(1'b0));
MUXF8 \instruction_reg[22]_i_1
(.I0(\instruction_reg[22]_i_2_n_0 ),
.I1(\instruction_reg[22]_i_3_n_0 ),
.O(\instruction_reg[22]_i_1_n_0 ),
.S(\program_counter_reg_rep_n_0_[0] ));
MUXF7 \instruction_reg[22]_i_2
(.I0(\instruction[22]_i_4_n_0 ),
.I1(\instruction[22]_i_5_n_0 ),
.O(\instruction_reg[22]_i_2_n_0 ),
.S(\program_counter_reg_rep_n_0_[1] ));
MUXF7 \instruction_reg[22]_i_3
(.I0(\instruction[22]_i_6_n_0 ),
.I1(\instruction[22]_i_7_n_0 ),
.O(\instruction_reg[22]_i_3_n_0 ),
.S(\program_counter_reg_rep_n_0_[1] ));
FDRE \instruction_reg[23]
(.C(ETH_CLK_OBUF),
.CE(instruction0),
.D(\instruction_reg[23]_i_1_n_0 ),
.Q(address_z[3]),
.R(1'b0));
MUXF8 \instruction_reg[23]_i_1
(.I0(\instruction_reg[23]_i_2_n_0 ),
.I1(\instruction_reg[23]_i_3_n_0 ),
.O(\instruction_reg[23]_i_1_n_0 ),
.S(\program_counter_reg_rep_n_0_[0] ));
MUXF7 \instruction_reg[23]_i_2
(.I0(\instruction[23]_i_4_n_0 ),
.I1(\instruction[23]_i_5_n_0 ),
.O(\instruction_reg[23]_i_2_n_0 ),
.S(\program_counter_reg_rep_n_0_[1] ));
MUXF7 \instruction_reg[23]_i_3
(.I0(\instruction[23]_i_6_n_0 ),
.I1(\instruction[23]_i_7_n_0 ),
.O(\instruction_reg[23]_i_3_n_0 ),
.S(\program_counter_reg_rep_n_0_[1] ));
FDRE \instruction_reg[24]
(.C(ETH_CLK_OBUF),
.CE(instruction0),
.D(\instruction_reg[24]_i_1_n_0 ),
.Q(opcode[0]),
.R(1'b0));
MUXF8 \instruction_reg[24]_i_1
(.I0(\instruction_reg[24]_i_2_n_0 ),
.I1(\instruction_reg[24]_i_3_n_0 ),
.O(\instruction_reg[24]_i_1_n_0 ),
.S(\program_counter_reg_rep_n_0_[0] ));
MUXF7 \instruction_reg[24]_i_2
(.I0(\instruction[24]_i_4_n_0 ),
.I1(\instruction[24]_i_5_n_0 ),
.O(\instruction_reg[24]_i_2_n_0 ),
.S(\program_counter_reg_rep_n_0_[1] ));
MUXF7 \instruction_reg[24]_i_3
(.I0(\instruction[24]_i_6_n_0 ),
.I1(\instruction[24]_i_7_n_0 ),
.O(\instruction_reg[24]_i_3_n_0 ),
.S(\program_counter_reg_rep_n_0_[1] ));
FDRE \instruction_reg[25]
(.C(ETH_CLK_OBUF),
.CE(instruction0),
.D(\instruction_reg[25]_i_1_n_0 ),
.Q(opcode[1]),
.R(1'b0));
MUXF8 \instruction_reg[25]_i_1
(.I0(\instruction_reg[25]_i_2_n_0 ),
.I1(\instruction_reg[25]_i_3_n_0 ),
.O(\instruction_reg[25]_i_1_n_0 ),
.S(\program_counter_reg_rep_n_0_[0] ));
MUXF7 \instruction_reg[25]_i_2
(.I0(\instruction[25]_i_4_n_0 ),
.I1(\instruction[25]_i_5_n_0 ),
.O(\instruction_reg[25]_i_2_n_0 ),
.S(\program_counter_reg_rep_n_0_[1] ));
MUXF7 \instruction_reg[25]_i_3
(.I0(\instruction[25]_i_6_n_0 ),
.I1(\instruction[25]_i_7_n_0 ),
.O(\instruction_reg[25]_i_3_n_0 ),
.S(\program_counter_reg_rep_n_0_[1] ));
FDRE \instruction_reg[26]
(.C(ETH_CLK_OBUF),
.CE(instruction0),
.D(\instruction_reg[26]_i_1_n_0 ),
.Q(opcode[2]),
.R(1'b0));
MUXF8 \instruction_reg[26]_i_1
(.I0(\instruction_reg[26]_i_2_n_0 ),
.I1(\instruction_reg[26]_i_3_n_0 ),
.O(\instruction_reg[26]_i_1_n_0 ),
.S(\program_counter_reg_rep_n_0_[0] ));
MUXF7 \instruction_reg[26]_i_2
(.I0(\instruction[26]_i_4_n_0 ),
.I1(\instruction[26]_i_5_n_0 ),
.O(\instruction_reg[26]_i_2_n_0 ),
.S(\program_counter_reg_rep_n_0_[1] ));
MUXF7 \instruction_reg[26]_i_3
(.I0(\instruction[26]_i_6_n_0 ),
.I1(\instruction[26]_i_7_n_0 ),
.O(\instruction_reg[26]_i_3_n_0 ),
.S(\program_counter_reg_rep_n_0_[1] ));
FDRE \instruction_reg[27]
(.C(ETH_CLK_OBUF),
.CE(instruction0),
.D(\instruction_reg[27]_i_1_n_0 ),
.Q(opcode[3]),
.R(1'b0));
MUXF7 \instruction_reg[27]_i_1
(.I0(\instruction[27]_i_2_n_0 ),
.I1(\instruction[27]_i_3_n_0 ),
.O(\instruction_reg[27]_i_1_n_0 ),
.S(\program_counter_reg_rep_n_0_[0] ));
FDRE \instruction_reg[2]
(.C(ETH_CLK_OBUF),
.CE(instruction0),
.D(\instruction_reg[2]_i_1_n_0 ),
.Q(\instruction_reg_n_0_[2] ),
.R(1'b0));
MUXF8 \instruction_reg[2]_i_1
(.I0(\instruction_reg[2]_i_2_n_0 ),
.I1(\instruction_reg[2]_i_3_n_0 ),
.O(\instruction_reg[2]_i_1_n_0 ),
.S(\program_counter_reg_rep_n_0_[0] ));
MUXF7 \instruction_reg[2]_i_2
(.I0(\instruction[2]_i_4_n_0 ),
.I1(\instruction[2]_i_5_n_0 ),
.O(\instruction_reg[2]_i_2_n_0 ),
.S(\program_counter_reg_rep_n_0_[1] ));
MUXF7 \instruction_reg[2]_i_3
(.I0(\instruction[2]_i_6_n_0 ),
.I1(\instruction[2]_i_7_n_0 ),
.O(\instruction_reg[2]_i_3_n_0 ),
.S(\program_counter_reg_rep_n_0_[1] ));
FDRE \instruction_reg[3]
(.C(ETH_CLK_OBUF),
.CE(instruction0),
.D(\instruction_reg[3]_i_1_n_0 ),
.Q(\instruction_reg_n_0_[3] ),
.R(1'b0));
MUXF8 \instruction_reg[3]_i_1
(.I0(\instruction_reg[3]_i_2_n_0 ),
.I1(\instruction_reg[3]_i_3_n_0 ),
.O(\instruction_reg[3]_i_1_n_0 ),
.S(\program_counter_reg_rep_n_0_[0] ));
MUXF7 \instruction_reg[3]_i_2
(.I0(\instruction[3]_i_4_n_0 ),
.I1(\instruction[3]_i_5_n_0 ),
.O(\instruction_reg[3]_i_2_n_0 ),
.S(\program_counter_reg_rep_n_0_[1] ));
MUXF7 \instruction_reg[3]_i_3
(.I0(\instruction[3]_i_6_n_0 ),
.I1(\instruction[3]_i_7_n_0 ),
.O(\instruction_reg[3]_i_3_n_0 ),
.S(\program_counter_reg_rep_n_0_[1] ));
FDRE \instruction_reg[4]
(.C(ETH_CLK_OBUF),
.CE(instruction0),
.D(\instruction[4]_i_1_n_0 ),
.Q(\instruction_reg_n_0_[4] ),
.R(1'b0));
MUXF7 \instruction_reg[4]_i_2
(.I0(\instruction[4]_i_5_n_0 ),
.I1(\instruction[4]_i_6_n_0 ),
.O(\instruction_reg[4]_i_2_n_0 ),
.S(\program_counter_reg_rep_n_0_[1] ));
FDRE \instruction_reg[5]
(.C(ETH_CLK_OBUF),
.CE(instruction0),
.D(\instruction_reg[5]_i_1_n_0 ),
.Q(\instruction_reg_n_0_[5] ),
.R(1'b0));
MUXF8 \instruction_reg[5]_i_1
(.I0(\instruction_reg[5]_i_2_n_0 ),
.I1(\instruction_reg[5]_i_3_n_0 ),
.O(\instruction_reg[5]_i_1_n_0 ),
.S(\program_counter_reg_rep_n_0_[0] ));
MUXF7 \instruction_reg[5]_i_2
(.I0(\instruction[5]_i_4_n_0 ),
.I1(\instruction[5]_i_5_n_0 ),
.O(\instruction_reg[5]_i_2_n_0 ),
.S(\program_counter_reg_rep_n_0_[1] ));
MUXF7 \instruction_reg[5]_i_3
(.I0(\instruction[5]_i_6_n_0 ),
.I1(\instruction[5]_i_7_n_0 ),
.O(\instruction_reg[5]_i_3_n_0 ),
.S(\program_counter_reg_rep_n_0_[1] ));
FDRE \instruction_reg[6]
(.C(ETH_CLK_OBUF),
.CE(instruction0),
.D(\instruction_reg[6]_i_1_n_0 ),
.Q(\instruction_reg_n_0_[6] ),
.R(1'b0));
MUXF8 \instruction_reg[6]_i_1
(.I0(\instruction_reg[6]_i_2_n_0 ),
.I1(\instruction_reg[6]_i_3_n_0 ),
.O(\instruction_reg[6]_i_1_n_0 ),
.S(\program_counter_reg_rep_n_0_[0] ));
MUXF7 \instruction_reg[6]_i_2
(.I0(\instruction[6]_i_4_n_0 ),
.I1(\instruction[6]_i_5_n_0 ),
.O(\instruction_reg[6]_i_2_n_0 ),
.S(\program_counter_reg_rep_n_0_[1] ));
MUXF7 \instruction_reg[6]_i_3
(.I0(\instruction[6]_i_6_n_0 ),
.I1(\instruction[6]_i_7_n_0 ),
.O(\instruction_reg[6]_i_3_n_0 ),
.S(\program_counter_reg_rep_n_0_[1] ));
FDRE \instruction_reg[7]
(.C(ETH_CLK_OBUF),
.CE(instruction0),
.D(\instruction_reg[7]_i_1_n_0 ),
.Q(\instruction_reg_n_0_[7] ),
.R(1'b0));
MUXF8 \instruction_reg[7]_i_1
(.I0(\instruction_reg[7]_i_2_n_0 ),
.I1(\instruction_reg[7]_i_3_n_0 ),
.O(\instruction_reg[7]_i_1_n_0 ),
.S(\program_counter_reg_rep_n_0_[0] ));
MUXF7 \instruction_reg[7]_i_2
(.I0(\instruction[7]_i_4_n_0 ),
.I1(\instruction[7]_i_5_n_0 ),
.O(\instruction_reg[7]_i_2_n_0 ),
.S(\program_counter_reg_rep_n_0_[1] ));
MUXF7 \instruction_reg[7]_i_3
(.I0(\instruction[7]_i_6_n_0 ),
.I1(\instruction[7]_i_7_n_0 ),
.O(\instruction_reg[7]_i_3_n_0 ),
.S(\program_counter_reg_rep_n_0_[1] ));
FDRE \literal_2_reg[15]
(.C(ETH_CLK_OBUF),
.CE(opcode_20),
.D(\instruction_reg_n_0_[15] ),
.Q(literal_2[15]),
.R(1'b0));
FDRE \literal_2_reg[4]
(.C(ETH_CLK_OBUF),
.CE(opcode_20),
.D(\instruction_reg_n_0_[4] ),
.Q(literal_2[4]),
.R(1'b0));
FDRE \literal_2_reg[5]
(.C(ETH_CLK_OBUF),
.CE(opcode_20),
.D(\instruction_reg_n_0_[5] ),
.Q(literal_2[5]),
.R(1'b0));
FDRE \literal_2_reg[6]
(.C(ETH_CLK_OBUF),
.CE(opcode_20),
.D(\instruction_reg_n_0_[6] ),
.Q(literal_2[6]),
.R(1'b0));
FDRE \literal_2_reg[7]
(.C(ETH_CLK_OBUF),
.CE(opcode_20),
.D(\instruction_reg_n_0_[7] ),
.Q(literal_2[7]),
.R(1'b0));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-6 {cell *THIS*}}" *)
(* RTL_RAM_BITS = "131104" *)
(* RTL_RAM_NAME = "memory" *)
(* bram_addr_begin = "0" *)
(* bram_addr_end = "8191" *)
(* bram_slice_begin = "0" *)
(* bram_slice_end = "3" *)
RAMB36E1 #(
.DOA_REG(0),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("PERFORMANCE"),
.READ_WIDTH_A(4),
.READ_WIDTH_B(0),
.RSTREG_PRIORITY_A("RSTREG"),
.RSTREG_PRIORITY_B("RSTREG"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("READ_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(4),
.WRITE_WIDTH_B(0))
memory_reg_0
(.ADDRARDADDR({1'b1,\write_output[12]_i_1_n_0 ,\write_output[11]_i_1_n_0 ,\write_output[10]_i_1_n_0 ,\write_output[9]_i_1_n_0 ,\write_output[8]_i_1_n_0 ,\write_output[7]_i_1_n_0 ,\write_output[6]_i_1_n_0 ,\write_output[5]_i_1_n_0 ,\write_output[4]_i_1_n_0 ,\write_output[3]_i_1_n_0 ,\write_output[2]_i_1_n_0 ,\write_output[1]_i_1_n_0 ,\write_output[0]_i_1_n_0 ,1'b1,1'b1}),
.ADDRBWRADDR({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
.CASCADEINA(1'b1),
.CASCADEINB(1'b0),
.CASCADEOUTA(NLW_memory_reg_0_CASCADEOUTA_UNCONNECTED),
.CASCADEOUTB(NLW_memory_reg_0_CASCADEOUTB_UNCONNECTED),
.CLKARDCLK(ETH_CLK_OBUF),
.CLKBWRCLK(1'b0),
.DBITERR(NLW_memory_reg_0_DBITERR_UNCONNECTED),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,store_data[3:0]}),
.DIBDI({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b1,1'b1,1'b1,1'b1}),
.DOADO({NLW_memory_reg_0_DOADO_UNCONNECTED[31:4],load_data[3:0]}),
.DOBDO(NLW_memory_reg_0_DOBDO_UNCONNECTED[31:0]),
.DOPADOP(NLW_memory_reg_0_DOPADOP_UNCONNECTED[3:0]),
.DOPBDOP(NLW_memory_reg_0_DOPBDOP_UNCONNECTED[3:0]),
.ECCPARITY(NLW_memory_reg_0_ECCPARITY_UNCONNECTED[7:0]),
.ENARDEN(1'b1),
.ENBWREN(1'b0),
.INJECTDBITERR(NLW_memory_reg_0_INJECTDBITERR_UNCONNECTED),
.INJECTSBITERR(NLW_memory_reg_0_INJECTSBITERR_UNCONNECTED),
.RDADDRECC(NLW_memory_reg_0_RDADDRECC_UNCONNECTED[8:0]),
.REGCEAREGCE(NLW_memory_reg_0_REGCEAREGCE_UNCONNECTED),
.REGCEB(NLW_memory_reg_0_REGCEB_UNCONNECTED),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(NLW_memory_reg_0_SBITERR_UNCONNECTED),
.WEA({1'b0,1'b0,1'b0,p_0_in}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
LUT6 #(
.INIT(64'h0000000000000800))
memory_reg_0_i_1
(.I0(\state_reg_n_0_[0] ),
.I1(opcode_20),
.I2(opcode_2[3]),
.I3(opcode_2[1]),
.I4(opcode_2[2]),
.I5(opcode_2[0]),
.O(p_0_in));
(* IS_CLOCK_GATED *)
(* METHODOLOGY_DRC_VIOS = "{SYNTH-6 {cell *THIS*}}" *)
(* POWER_OPTED_CE = "ENARDEN=NEW" *)
(* RTL_RAM_BITS = "131104" *)
(* RTL_RAM_NAME = "memory" *)
(* bram_addr_begin = "0" *)
(* bram_addr_end = "8191" *)
(* bram_slice_begin = "4" *)
(* bram_slice_end = "7" *)
RAMB36E1 #(
.DOA_REG(0),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("PERFORMANCE"),
.READ_WIDTH_A(4),
.READ_WIDTH_B(0),
.RSTREG_PRIORITY_A("RSTREG"),
.RSTREG_PRIORITY_B("RSTREG"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("READ_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(4),
.WRITE_WIDTH_B(0))
memory_reg_1
(.ADDRARDADDR({1'b1,\write_output[12]_i_1_n_0 ,\write_output[11]_i_1_n_0 ,\write_output[10]_i_1_n_0 ,\write_output[9]_i_1_n_0 ,\write_output[8]_i_1_n_0 ,\write_output[7]_i_1_n_0 ,\write_output[6]_i_1_n_0 ,\write_output[5]_i_1_n_0 ,\write_output[4]_i_1_n_0 ,\write_output[3]_i_1_n_0 ,\write_output[2]_i_1_n_0 ,\write_output[1]_i_1_n_0 ,\write_output[0]_i_1_n_0 ,1'b1,1'b1}),
.ADDRBWRADDR({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
.CASCADEINA(1'b1),
.CASCADEINB(1'b0),
.CASCADEOUTA(NLW_memory_reg_1_CASCADEOUTA_UNCONNECTED),
.CASCADEOUTB(NLW_memory_reg_1_CASCADEOUTB_UNCONNECTED),
.CLKARDCLK(ETH_CLK_OBUF),
.CLKBWRCLK(1'b0),
.DBITERR(NLW_memory_reg_1_DBITERR_UNCONNECTED),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,store_data[7:4]}),
.DIBDI({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b1,1'b1,1'b1,1'b1}),
.DOADO({NLW_memory_reg_1_DOADO_UNCONNECTED[31:4],load_data[7:4]}),
.DOBDO(NLW_memory_reg_1_DOBDO_UNCONNECTED[31:0]),
.DOPADOP(NLW_memory_reg_1_DOPADOP_UNCONNECTED[3:0]),
.DOPBDOP(NLW_memory_reg_1_DOPBDOP_UNCONNECTED[3:0]),
.ECCPARITY(NLW_memory_reg_1_ECCPARITY_UNCONNECTED[7:0]),
.ENARDEN(memory_reg_1_ENARDEN_cooolgate_en_sig_1),
.ENBWREN(1'b0),
.INJECTDBITERR(NLW_memory_reg_1_INJECTDBITERR_UNCONNECTED),
.INJECTSBITERR(NLW_memory_reg_1_INJECTSBITERR_UNCONNECTED),
.RDADDRECC(NLW_memory_reg_1_RDADDRECC_UNCONNECTED[8:0]),
.REGCEAREGCE(NLW_memory_reg_1_REGCEAREGCE_UNCONNECTED),
.REGCEB(NLW_memory_reg_1_REGCEB_UNCONNECTED),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(NLW_memory_reg_1_SBITERR_UNCONNECTED),
.WEA({1'b0,1'b0,1'b0,p_0_in}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
LUT4 #(
.INIT(16'hff01))
memory_reg_1_ENARDEN_cooolgate_en_gate_1
(.I0(\state[1]_i_1_n_0 ),
.I1(\state[0]_i_1_n_0 ),
.I2(INTERNAL_RST_reg),
.I3(p_0_in),
.O(memory_reg_1_ENARDEN_cooolgate_en_sig_1));
(* IS_CLOCK_GATED *)
(* METHODOLOGY_DRC_VIOS = "{SYNTH-6 {cell *THIS*}}" *)
(* POWER_OPTED_CE = "ENARDEN=NEW" *)
(* RTL_RAM_BITS = "131104" *)
(* RTL_RAM_NAME = "memory" *)
(* bram_addr_begin = "0" *)
(* bram_addr_end = "8191" *)
(* bram_slice_begin = "8" *)
(* bram_slice_end = "11" *)
RAMB36E1 #(
.DOA_REG(0),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("PERFORMANCE"),
.READ_WIDTH_A(4),
.READ_WIDTH_B(0),
.RSTREG_PRIORITY_A("RSTREG"),
.RSTREG_PRIORITY_B("RSTREG"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("READ_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(4),
.WRITE_WIDTH_B(0))
memory_reg_2
(.ADDRARDADDR({1'b1,\write_output[12]_i_1_n_0 ,\write_output[11]_i_1_n_0 ,\write_output[10]_i_1_n_0 ,\write_output[9]_i_1_n_0 ,\write_output[8]_i_1_n_0 ,\write_output[7]_i_1_n_0 ,\write_output[6]_i_1_n_0 ,\write_output[5]_i_1_n_0 ,\write_output[4]_i_1_n_0 ,\write_output[3]_i_1_n_0 ,\write_output[2]_i_1_n_0 ,\write_output[1]_i_1_n_0 ,\write_output[0]_i_1_n_0 ,1'b1,1'b1}),
.ADDRBWRADDR({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
.CASCADEINA(1'b1),
.CASCADEINB(1'b0),
.CASCADEOUTA(NLW_memory_reg_2_CASCADEOUTA_UNCONNECTED),
.CASCADEOUTB(NLW_memory_reg_2_CASCADEOUTB_UNCONNECTED),
.CLKARDCLK(ETH_CLK_OBUF),
.CLKBWRCLK(1'b0),
.DBITERR(NLW_memory_reg_2_DBITERR_UNCONNECTED),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,store_data[11:8]}),
.DIBDI({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b1,1'b1,1'b1,1'b1}),
.DOADO({NLW_memory_reg_2_DOADO_UNCONNECTED[31:4],load_data[11:8]}),
.DOBDO(NLW_memory_reg_2_DOBDO_UNCONNECTED[31:0]),
.DOPADOP(NLW_memory_reg_2_DOPADOP_UNCONNECTED[3:0]),
.DOPBDOP(NLW_memory_reg_2_DOPBDOP_UNCONNECTED[3:0]),
.ECCPARITY(NLW_memory_reg_2_ECCPARITY_UNCONNECTED[7:0]),
.ENARDEN(memory_reg_2_ENARDEN_cooolgate_en_sig_2),
.ENBWREN(1'b0),
.INJECTDBITERR(NLW_memory_reg_2_INJECTDBITERR_UNCONNECTED),
.INJECTSBITERR(NLW_memory_reg_2_INJECTSBITERR_UNCONNECTED),
.RDADDRECC(NLW_memory_reg_2_RDADDRECC_UNCONNECTED[8:0]),
.REGCEAREGCE(NLW_memory_reg_2_REGCEAREGCE_UNCONNECTED),
.REGCEB(NLW_memory_reg_2_REGCEB_UNCONNECTED),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(NLW_memory_reg_2_SBITERR_UNCONNECTED),
.WEA({1'b0,1'b0,1'b0,p_0_in}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
LUT4 #(
.INIT(16'hff01))
memory_reg_2_ENARDEN_cooolgate_en_gate_3
(.I0(\state[1]_i_1_n_0 ),
.I1(\state[0]_i_1_n_0 ),
.I2(INTERNAL_RST_reg),
.I3(p_0_in),
.O(memory_reg_2_ENARDEN_cooolgate_en_sig_2));
LUT3 #(
.INIT(8'hB8))
memory_reg_2_i_1
(.I0(result[11]),
.I1(operand_b1),
.I2(register_b[11]),
.O(store_data[11]));
LUT3 #(
.INIT(8'hB8))
memory_reg_2_i_2
(.I0(result[10]),
.I1(operand_b1),
.I2(register_b[10]),
.O(store_data[10]));
LUT3 #(
.INIT(8'hB8))
memory_reg_2_i_3
(.I0(result[9]),
.I1(operand_b1),
.I2(register_b[9]),
.O(store_data[9]));
LUT3 #(
.INIT(8'hB8))
memory_reg_2_i_4
(.I0(result[8]),
.I1(operand_b1),
.I2(register_b[8]),
.O(store_data[8]));
(* IS_CLOCK_GATED *)
(* METHODOLOGY_DRC_VIOS = "{SYNTH-6 {cell *THIS*}}" *)
(* POWER_OPTED_CE = "ENARDEN=NEW" *)
(* RTL_RAM_BITS = "131104" *)
(* RTL_RAM_NAME = "memory" *)
(* bram_addr_begin = "0" *)
(* bram_addr_end = "8191" *)
(* bram_slice_begin = "12" *)
(* bram_slice_end = "15" *)
RAMB36E1 #(
.DOA_REG(0),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("PERFORMANCE"),
.READ_WIDTH_A(4),
.READ_WIDTH_B(0),
.RSTREG_PRIORITY_A("RSTREG"),
.RSTREG_PRIORITY_B("RSTREG"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("READ_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(4),
.WRITE_WIDTH_B(0))
memory_reg_3
(.ADDRARDADDR({1'b1,\write_output[12]_i_1_n_0 ,\write_output[11]_i_1_n_0 ,\write_output[10]_i_1_n_0 ,\write_output[9]_i_1_n_0 ,\write_output[8]_i_1_n_0 ,\write_output[7]_i_1_n_0 ,\write_output[6]_i_1_n_0 ,\write_output[5]_i_1_n_0 ,\write_output[4]_i_1_n_0 ,\write_output[3]_i_1_n_0 ,\write_output[2]_i_1_n_0 ,\write_output[1]_i_1_n_0 ,\write_output[0]_i_1_n_0 ,1'b1,1'b1}),
.ADDRBWRADDR({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
.CASCADEINA(1'b1),
.CASCADEINB(1'b0),
.CASCADEOUTA(NLW_memory_reg_3_CASCADEOUTA_UNCONNECTED),
.CASCADEOUTB(NLW_memory_reg_3_CASCADEOUTB_UNCONNECTED),
.CLKARDCLK(ETH_CLK_OBUF),
.CLKBWRCLK(1'b0),
.DBITERR(NLW_memory_reg_3_DBITERR_UNCONNECTED),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,store_data[15:12]}),
.DIBDI({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b1,1'b1,1'b1,1'b1}),
.DOADO({NLW_memory_reg_3_DOADO_UNCONNECTED[31:4],load_data[15:12]}),
.DOBDO(NLW_memory_reg_3_DOBDO_UNCONNECTED[31:0]),
.DOPADOP(NLW_memory_reg_3_DOPADOP_UNCONNECTED[3:0]),
.DOPBDOP(NLW_memory_reg_3_DOPBDOP_UNCONNECTED[3:0]),
.ECCPARITY(NLW_memory_reg_3_ECCPARITY_UNCONNECTED[7:0]),
.ENARDEN(memory_reg_3_ENARDEN_cooolgate_en_sig_3),
.ENBWREN(1'b0),
.INJECTDBITERR(NLW_memory_reg_3_INJECTDBITERR_UNCONNECTED),
.INJECTSBITERR(NLW_memory_reg_3_INJECTSBITERR_UNCONNECTED),
.RDADDRECC(NLW_memory_reg_3_RDADDRECC_UNCONNECTED[8:0]),
.REGCEAREGCE(NLW_memory_reg_3_REGCEAREGCE_UNCONNECTED),
.REGCEB(NLW_memory_reg_3_REGCEB_UNCONNECTED),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(NLW_memory_reg_3_SBITERR_UNCONNECTED),
.WEA({1'b0,1'b0,1'b0,p_0_in}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
LUT4 #(
.INIT(16'hff01))
memory_reg_3_ENARDEN_cooolgate_en_gate_5
(.I0(\state[1]_i_1_n_0 ),
.I1(\state[0]_i_1_n_0 ),
.I2(INTERNAL_RST_reg),
.I3(p_0_in),
.O(memory_reg_3_ENARDEN_cooolgate_en_sig_3));
LUT3 #(
.INIT(8'hB8))
memory_reg_3_i_1
(.I0(result[15]),
.I1(operand_b1),
.I2(register_b[15]),
.O(store_data[15]));
LUT3 #(
.INIT(8'hB8))
memory_reg_3_i_2
(.I0(result[14]),
.I1(operand_b1),
.I2(register_b[14]),
.O(store_data[14]));
LUT3 #(
.INIT(8'hB8))
memory_reg_3_i_3
(.I0(result[13]),
.I1(operand_b1),
.I2(register_b[13]),
.O(store_data[13]));
LUT3 #(
.INIT(8'hB8))
memory_reg_3_i_4
(.I0(result[12]),
.I1(operand_b1),
.I2(register_b[12]),
.O(store_data[12]));
(* IS_CLOCK_GATED *)
(* METHODOLOGY_DRC_VIOS = "{SYNTH-6 {cell *THIS*}}" *)
(* POWER_OPTED_CE = "ENARDEN=NEW" *)
(* RTL_RAM_BITS = "131104" *)
(* RTL_RAM_NAME = "memory" *)
(* bram_addr_begin = "0" *)
(* bram_addr_end = "8191" *)
(* bram_slice_begin = "16" *)
(* bram_slice_end = "19" *)
RAMB36E1 #(
.DOA_REG(0),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("PERFORMANCE"),
.READ_WIDTH_A(4),
.READ_WIDTH_B(0),
.RSTREG_PRIORITY_A("RSTREG"),
.RSTREG_PRIORITY_B("RSTREG"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("READ_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(4),
.WRITE_WIDTH_B(0))
memory_reg_4
(.ADDRARDADDR({1'b1,\write_output[12]_i_1_n_0 ,\write_output[11]_i_1_n_0 ,\write_output[10]_i_1_n_0 ,\write_output[9]_i_1_n_0 ,\write_output[8]_i_1_n_0 ,\write_output[7]_i_1_n_0 ,\write_output[6]_i_1_n_0 ,\write_output[5]_i_1_n_0 ,\write_output[4]_i_1_n_0 ,\write_output[3]_i_1_n_0 ,\write_output[2]_i_1_n_0 ,\write_output[1]_i_1_n_0 ,\write_output[0]_i_1_n_0 ,1'b1,1'b1}),
.ADDRBWRADDR({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
.CASCADEINA(1'b1),
.CASCADEINB(1'b0),
.CASCADEOUTA(NLW_memory_reg_4_CASCADEOUTA_UNCONNECTED),
.CASCADEOUTB(NLW_memory_reg_4_CASCADEOUTB_UNCONNECTED),
.CLKARDCLK(ETH_CLK_OBUF),
.CLKBWRCLK(1'b0),
.DBITERR(NLW_memory_reg_4_DBITERR_UNCONNECTED),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,store_data[19:16]}),
.DIBDI({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b1,1'b1,1'b1,1'b1}),
.DOADO({NLW_memory_reg_4_DOADO_UNCONNECTED[31:4],load_data[19:16]}),
.DOBDO(NLW_memory_reg_4_DOBDO_UNCONNECTED[31:0]),
.DOPADOP(NLW_memory_reg_4_DOPADOP_UNCONNECTED[3:0]),
.DOPBDOP(NLW_memory_reg_4_DOPBDOP_UNCONNECTED[3:0]),
.ECCPARITY(NLW_memory_reg_4_ECCPARITY_UNCONNECTED[7:0]),
.ENARDEN(memory_reg_4_ENARDEN_cooolgate_en_sig_4),
.ENBWREN(1'b0),
.INJECTDBITERR(NLW_memory_reg_4_INJECTDBITERR_UNCONNECTED),
.INJECTSBITERR(NLW_memory_reg_4_INJECTSBITERR_UNCONNECTED),
.RDADDRECC(NLW_memory_reg_4_RDADDRECC_UNCONNECTED[8:0]),
.REGCEAREGCE(NLW_memory_reg_4_REGCEAREGCE_UNCONNECTED),
.REGCEB(NLW_memory_reg_4_REGCEB_UNCONNECTED),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(NLW_memory_reg_4_SBITERR_UNCONNECTED),
.WEA({1'b0,1'b0,1'b0,p_0_in}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
LUT4 #(
.INIT(16'hff01))
memory_reg_4_ENARDEN_cooolgate_en_gate_7
(.I0(\state[1]_i_1_n_0 ),
.I1(\state[0]_i_1_n_0 ),
.I2(INTERNAL_RST_reg),
.I3(p_0_in),
.O(memory_reg_4_ENARDEN_cooolgate_en_sig_4));
LUT3 #(
.INIT(8'hB8))
memory_reg_4_i_1
(.I0(result[19]),
.I1(operand_b1),
.I2(register_b[19]),
.O(store_data[19]));
LUT3 #(
.INIT(8'hB8))
memory_reg_4_i_2
(.I0(result[18]),
.I1(operand_b1),
.I2(register_b[18]),
.O(store_data[18]));
LUT3 #(
.INIT(8'hB8))
memory_reg_4_i_3
(.I0(result[17]),
.I1(operand_b1),
.I2(register_b[17]),
.O(store_data[17]));
LUT3 #(
.INIT(8'hB8))
memory_reg_4_i_4
(.I0(result[16]),
.I1(operand_b1),
.I2(register_b[16]),
.O(store_data[16]));
(* IS_CLOCK_GATED *)
(* METHODOLOGY_DRC_VIOS = "{SYNTH-6 {cell *THIS*}}" *)
(* POWER_OPTED_CE = "ENARDEN=NEW" *)
(* RTL_RAM_BITS = "131104" *)
(* RTL_RAM_NAME = "memory" *)
(* bram_addr_begin = "0" *)
(* bram_addr_end = "8191" *)
(* bram_slice_begin = "20" *)
(* bram_slice_end = "23" *)
RAMB36E1 #(
.DOA_REG(0),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("PERFORMANCE"),
.READ_WIDTH_A(4),
.READ_WIDTH_B(0),
.RSTREG_PRIORITY_A("RSTREG"),
.RSTREG_PRIORITY_B("RSTREG"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("READ_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(4),
.WRITE_WIDTH_B(0))
memory_reg_5
(.ADDRARDADDR({1'b1,\write_output[12]_i_1_n_0 ,\write_output[11]_i_1_n_0 ,\write_output[10]_i_1_n_0 ,\write_output[9]_i_1_n_0 ,\write_output[8]_i_1_n_0 ,\write_output[7]_i_1_n_0 ,\write_output[6]_i_1_n_0 ,\write_output[5]_i_1_n_0 ,\write_output[4]_i_1_n_0 ,\write_output[3]_i_1_n_0 ,\write_output[2]_i_1_n_0 ,\write_output[1]_i_1_n_0 ,\write_output[0]_i_1_n_0 ,1'b1,1'b1}),
.ADDRBWRADDR({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
.CASCADEINA(1'b1),
.CASCADEINB(1'b0),
.CASCADEOUTA(NLW_memory_reg_5_CASCADEOUTA_UNCONNECTED),
.CASCADEOUTB(NLW_memory_reg_5_CASCADEOUTB_UNCONNECTED),
.CLKARDCLK(ETH_CLK_OBUF),
.CLKBWRCLK(1'b0),
.DBITERR(NLW_memory_reg_5_DBITERR_UNCONNECTED),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,store_data[23:20]}),
.DIBDI({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b1,1'b1,1'b1,1'b1}),
.DOADO({NLW_memory_reg_5_DOADO_UNCONNECTED[31:4],load_data[23:20]}),
.DOBDO(NLW_memory_reg_5_DOBDO_UNCONNECTED[31:0]),
.DOPADOP(NLW_memory_reg_5_DOPADOP_UNCONNECTED[3:0]),
.DOPBDOP(NLW_memory_reg_5_DOPBDOP_UNCONNECTED[3:0]),
.ECCPARITY(NLW_memory_reg_5_ECCPARITY_UNCONNECTED[7:0]),
.ENARDEN(memory_reg_5_ENARDEN_cooolgate_en_sig_5),
.ENBWREN(1'b0),
.INJECTDBITERR(NLW_memory_reg_5_INJECTDBITERR_UNCONNECTED),
.INJECTSBITERR(NLW_memory_reg_5_INJECTSBITERR_UNCONNECTED),
.RDADDRECC(NLW_memory_reg_5_RDADDRECC_UNCONNECTED[8:0]),
.REGCEAREGCE(NLW_memory_reg_5_REGCEAREGCE_UNCONNECTED),
.REGCEB(NLW_memory_reg_5_REGCEB_UNCONNECTED),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(NLW_memory_reg_5_SBITERR_UNCONNECTED),
.WEA({1'b0,1'b0,1'b0,p_0_in}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
LUT4 #(
.INIT(16'hff01))
memory_reg_5_ENARDEN_cooolgate_en_gate_9
(.I0(\state[1]_i_1_n_0 ),
.I1(\state[0]_i_1_n_0 ),
.I2(INTERNAL_RST_reg),
.I3(p_0_in),
.O(memory_reg_5_ENARDEN_cooolgate_en_sig_5));
LUT3 #(
.INIT(8'hB8))
memory_reg_5_i_1
(.I0(result[23]),
.I1(operand_b1),
.I2(register_b[23]),
.O(store_data[23]));
LUT3 #(
.INIT(8'hB8))
memory_reg_5_i_2
(.I0(result[22]),
.I1(operand_b1),
.I2(register_b[22]),
.O(store_data[22]));
LUT3 #(
.INIT(8'hB8))
memory_reg_5_i_3
(.I0(result[21]),
.I1(operand_b1),
.I2(register_b[21]),
.O(store_data[21]));
LUT3 #(
.INIT(8'hB8))
memory_reg_5_i_4
(.I0(result[20]),
.I1(operand_b1),
.I2(register_b[20]),
.O(store_data[20]));
(* IS_CLOCK_GATED *)
(* METHODOLOGY_DRC_VIOS = "{SYNTH-6 {cell *THIS*}}" *)
(* POWER_OPTED_CE = "ENARDEN=NEW" *)
(* RTL_RAM_BITS = "131104" *)
(* RTL_RAM_NAME = "memory" *)
(* bram_addr_begin = "0" *)
(* bram_addr_end = "8191" *)
(* bram_slice_begin = "24" *)
(* bram_slice_end = "27" *)
RAMB36E1 #(
.DOA_REG(0),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("PERFORMANCE"),
.READ_WIDTH_A(4),
.READ_WIDTH_B(0),
.RSTREG_PRIORITY_A("RSTREG"),
.RSTREG_PRIORITY_B("RSTREG"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("READ_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(4),
.WRITE_WIDTH_B(0))
memory_reg_6
(.ADDRARDADDR({1'b1,\write_output[12]_i_1_n_0 ,\write_output[11]_i_1_n_0 ,\write_output[10]_i_1_n_0 ,\write_output[9]_i_1_n_0 ,\write_output[8]_i_1_n_0 ,\write_output[7]_i_1_n_0 ,\write_output[6]_i_1_n_0 ,\write_output[5]_i_1_n_0 ,\write_output[4]_i_1_n_0 ,\write_output[3]_i_1_n_0 ,\write_output[2]_i_1_n_0 ,\write_output[1]_i_1_n_0 ,\write_output[0]_i_1_n_0 ,1'b1,1'b1}),
.ADDRBWRADDR({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
.CASCADEINA(1'b1),
.CASCADEINB(1'b0),
.CASCADEOUTA(NLW_memory_reg_6_CASCADEOUTA_UNCONNECTED),
.CASCADEOUTB(NLW_memory_reg_6_CASCADEOUTB_UNCONNECTED),
.CLKARDCLK(ETH_CLK_OBUF),
.CLKBWRCLK(1'b0),
.DBITERR(NLW_memory_reg_6_DBITERR_UNCONNECTED),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,store_data[27:24]}),
.DIBDI({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b1,1'b1,1'b1,1'b1}),
.DOADO({NLW_memory_reg_6_DOADO_UNCONNECTED[31:4],load_data[27:24]}),
.DOBDO(NLW_memory_reg_6_DOBDO_UNCONNECTED[31:0]),
.DOPADOP(NLW_memory_reg_6_DOPADOP_UNCONNECTED[3:0]),
.DOPBDOP(NLW_memory_reg_6_DOPBDOP_UNCONNECTED[3:0]),
.ECCPARITY(NLW_memory_reg_6_ECCPARITY_UNCONNECTED[7:0]),
.ENARDEN(memory_reg_6_ENARDEN_cooolgate_en_sig_6),
.ENBWREN(1'b0),
.INJECTDBITERR(NLW_memory_reg_6_INJECTDBITERR_UNCONNECTED),
.INJECTSBITERR(NLW_memory_reg_6_INJECTSBITERR_UNCONNECTED),
.RDADDRECC(NLW_memory_reg_6_RDADDRECC_UNCONNECTED[8:0]),
.REGCEAREGCE(NLW_memory_reg_6_REGCEAREGCE_UNCONNECTED),
.REGCEB(NLW_memory_reg_6_REGCEB_UNCONNECTED),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(NLW_memory_reg_6_SBITERR_UNCONNECTED),
.WEA({1'b0,1'b0,1'b0,p_0_in}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
LUT4 #(
.INIT(16'hff01))
memory_reg_6_ENARDEN_cooolgate_en_gate_11
(.I0(\state[1]_i_1_n_0 ),
.I1(\state[0]_i_1_n_0 ),
.I2(INTERNAL_RST_reg),
.I3(p_0_in),
.O(memory_reg_6_ENARDEN_cooolgate_en_sig_6));
LUT3 #(
.INIT(8'hB8))
memory_reg_6_i_1
(.I0(result[27]),
.I1(operand_b1),
.I2(register_b[27]),
.O(store_data[27]));
LUT3 #(
.INIT(8'hB8))
memory_reg_6_i_2
(.I0(result[26]),
.I1(operand_b1),
.I2(register_b[26]),
.O(store_data[26]));
LUT3 #(
.INIT(8'hB8))
memory_reg_6_i_3
(.I0(result[25]),
.I1(operand_b1),
.I2(register_b[25]),
.O(store_data[25]));
LUT3 #(
.INIT(8'hB8))
memory_reg_6_i_4
(.I0(result[24]),
.I1(operand_b1),
.I2(register_b[24]),
.O(store_data[24]));
(* IS_CLOCK_GATED *)
(* METHODOLOGY_DRC_VIOS = "{SYNTH-6 {cell *THIS*}}" *)
(* POWER_OPTED_CE = "ENARDEN=NEW" *)
(* RTL_RAM_BITS = "131104" *)
(* RTL_RAM_NAME = "memory" *)
(* bram_addr_begin = "0" *)
(* bram_addr_end = "8191" *)
(* bram_slice_begin = "28" *)
(* bram_slice_end = "31" *)
RAMB36E1 #(
.DOA_REG(0),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("PERFORMANCE"),
.READ_WIDTH_A(4),
.READ_WIDTH_B(0),
.RSTREG_PRIORITY_A("RSTREG"),
.RSTREG_PRIORITY_B("RSTREG"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("READ_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(4),
.WRITE_WIDTH_B(0))
memory_reg_7
(.ADDRARDADDR({1'b1,\write_output[12]_i_1_n_0 ,\write_output[11]_i_1_n_0 ,\write_output[10]_i_1_n_0 ,\write_output[9]_i_1_n_0 ,\write_output[8]_i_1_n_0 ,\write_output[7]_i_1_n_0 ,\write_output[6]_i_1_n_0 ,\write_output[5]_i_1_n_0 ,\write_output[4]_i_1_n_0 ,\write_output[3]_i_1_n_0 ,\write_output[2]_i_1_n_0 ,\write_output[1]_i_1_n_0 ,\write_output[0]_i_1_n_0 ,1'b1,1'b1}),
.ADDRBWRADDR({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
.CASCADEINA(1'b1),
.CASCADEINB(1'b0),
.CASCADEOUTA(NLW_memory_reg_7_CASCADEOUTA_UNCONNECTED),
.CASCADEOUTB(NLW_memory_reg_7_CASCADEOUTB_UNCONNECTED),
.CLKARDCLK(ETH_CLK_OBUF),
.CLKBWRCLK(1'b0),
.DBITERR(NLW_memory_reg_7_DBITERR_UNCONNECTED),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,store_data[31:28]}),
.DIBDI({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b1,1'b1,1'b1,1'b1}),
.DOADO({NLW_memory_reg_7_DOADO_UNCONNECTED[31:4],load_data[31:28]}),
.DOBDO(NLW_memory_reg_7_DOBDO_UNCONNECTED[31:0]),
.DOPADOP(NLW_memory_reg_7_DOPADOP_UNCONNECTED[3:0]),
.DOPBDOP(NLW_memory_reg_7_DOPBDOP_UNCONNECTED[3:0]),
.ECCPARITY(NLW_memory_reg_7_ECCPARITY_UNCONNECTED[7:0]),
.ENARDEN(memory_reg_7_ENARDEN_cooolgate_en_sig_7),
.ENBWREN(1'b0),
.INJECTDBITERR(NLW_memory_reg_7_INJECTDBITERR_UNCONNECTED),
.INJECTSBITERR(NLW_memory_reg_7_INJECTSBITERR_UNCONNECTED),
.RDADDRECC(NLW_memory_reg_7_RDADDRECC_UNCONNECTED[8:0]),
.REGCEAREGCE(NLW_memory_reg_7_REGCEAREGCE_UNCONNECTED),
.REGCEB(NLW_memory_reg_7_REGCEB_UNCONNECTED),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(NLW_memory_reg_7_SBITERR_UNCONNECTED),
.WEA({1'b0,1'b0,1'b0,p_0_in}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
LUT4 #(
.INIT(16'hff01))
memory_reg_7_ENARDEN_cooolgate_en_gate_13
(.I0(\state[1]_i_1_n_0 ),
.I1(\state[0]_i_1_n_0 ),
.I2(INTERNAL_RST_reg),
.I3(p_0_in),
.O(memory_reg_7_ENARDEN_cooolgate_en_sig_7));
LUT3 #(
.INIT(8'hB8))
memory_reg_7_i_1
(.I0(result[31]),
.I1(operand_b1),
.I2(register_b[31]),
.O(store_data[31]));
LUT3 #(
.INIT(8'hB8))
memory_reg_7_i_2
(.I0(result[30]),
.I1(operand_b1),
.I2(register_b[30]),
.O(store_data[30]));
LUT3 #(
.INIT(8'hB8))
memory_reg_7_i_3
(.I0(result[29]),
.I1(operand_b1),
.I2(register_b[29]),
.O(store_data[29]));
LUT3 #(
.INIT(8'hB8))
memory_reg_7_i_4
(.I0(result[28]),
.I1(operand_b1),
.I2(register_b[28]),
.O(store_data[28]));
LUT2 #(
.INIT(4'h2))
\opcode_2[3]_i_1
(.I0(\state_reg_n_0_[1] ),
.I1(\state_reg_n_0_[2] ),
.O(opcode_20));
FDRE \opcode_2_reg[0]
(.C(ETH_CLK_OBUF),
.CE(opcode_20),
.D(opcode[0]),
.Q(opcode_2[0]),
.R(1'b0));
FDRE \opcode_2_reg[1]
(.C(ETH_CLK_OBUF),
.CE(opcode_20),
.D(opcode[1]),
.Q(opcode_2[1]),
.R(1'b0));
FDRE \opcode_2_reg[2]
(.C(ETH_CLK_OBUF),
.CE(opcode_20),
.D(opcode[2]),
.Q(opcode_2[2]),
.R(1'b0));
FDRE \opcode_2_reg[3]
(.C(ETH_CLK_OBUF),
.CE(opcode_20),
.D(opcode[3]),
.Q(opcode_2[3]),
.R(1'b0));
LUT5 #(
.INIT(32'hFF4F4444))
\program_counter[10]_i_1
(.I0(\program_counter_rep[7]_i_3_n_0 ),
.I1(data1[10]),
.I2(opcode_2[2]),
.I3(\write_output[10]_i_1_n_0 ),
.I4(\program_counter[14]_i_2_n_0 ),
.O(\program_counter[10]_i_1_n_0 ));
LUT5 #(
.INIT(32'hFF4F4444))
\program_counter[11]_i_1
(.I0(\program_counter_rep[7]_i_3_n_0 ),
.I1(data1[11]),
.I2(opcode_2[2]),
.I3(\write_output[11]_i_1_n_0 ),
.I4(\program_counter[14]_i_2_n_0 ),
.O(\program_counter[11]_i_1_n_0 ));
LUT5 #(
.INIT(32'hFF4F4444))
\program_counter[12]_i_1
(.I0(\program_counter_rep[7]_i_3_n_0 ),
.I1(data1[12]),
.I2(opcode_2[2]),
.I3(\write_output[12]_i_1_n_0 ),
.I4(\program_counter[14]_i_2_n_0 ),
.O(\program_counter[12]_i_1_n_0 ));
LUT5 #(
.INIT(32'hFF4F4444))
\program_counter[13]_i_1
(.I0(\program_counter_rep[7]_i_3_n_0 ),
.I1(data1[13]),
.I2(opcode_2[2]),
.I3(\write_output[13]_i_1_n_0 ),
.I4(\program_counter[14]_i_2_n_0 ),
.O(\program_counter[13]_i_1_n_0 ));
LUT5 #(
.INIT(32'hFF4F4444))
\program_counter[14]_i_1
(.I0(\program_counter_rep[7]_i_3_n_0 ),
.I1(data1[14]),
.I2(opcode_2[2]),
.I3(\write_output[14]_i_1_n_0 ),
.I4(\program_counter[14]_i_2_n_0 ),
.O(\program_counter[14]_i_1_n_0 ));
LUT6 #(
.INIT(64'hAAAAAAAA80808088))
\program_counter[14]_i_2
(.I0(\program_counter[15]_i_3_n_0 ),
.I1(literal_2[15]),
.I2(opcode_2[1]),
.I3(\program_counter_rep[7]_i_10_n_0 ),
.I4(\program_counter[14]_i_3_n_0 ),
.I5(opcode_2[2]),
.O(\program_counter[14]_i_2_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFFFFFFE))
\program_counter[14]_i_3
(.I0(\state[2]_i_12_n_0 ),
.I1(\state[2]_i_11_n_0 ),
.I2(\program_counter_rep[7]_i_25_n_0 ),
.I3(\program_counter_rep[7]_i_24_n_0 ),
.I4(\program_counter_rep[7]_i_23_n_0 ),
.I5(\state[2]_i_9_n_0 ),
.O(\program_counter[14]_i_3_n_0 ));
LUT6 #(
.INIT(64'hE2AAE2AAF3AAC0AA))
\program_counter[15]_i_1
(.I0(data1[15]),
.I1(opcode_2[2]),
.I2(\write_output[15]_i_1_n_0 ),
.I3(\program_counter[15]_i_3_n_0 ),
.I4(literal_2[15]),
.I5(\program_counter_rep[7]_i_5_n_0 ),
.O(\program_counter[15]_i_1_n_0 ));
LUT6 #(
.INIT(64'h0008000808800000))
\program_counter[15]_i_3
(.I0(\state_reg_n_0_[1] ),
.I1(\state_reg_n_0_[0] ),
.I2(opcode_2[0]),
.I3(opcode_2[2]),
.I4(opcode_2[1]),
.I5(opcode_2[3]),
.O(\program_counter[15]_i_3_n_0 ));
LUT5 #(
.INIT(32'hFF4F4444))
\program_counter[8]_i_1
(.I0(\program_counter_rep[7]_i_3_n_0 ),
.I1(data1[8]),
.I2(opcode_2[2]),
.I3(\write_output[8]_i_1_n_0 ),
.I4(\program_counter[14]_i_2_n_0 ),
.O(\program_counter[8]_i_1_n_0 ));
LUT5 #(
.INIT(32'hFF4F4444))
\program_counter[9]_i_1
(.I0(\program_counter_rep[7]_i_3_n_0 ),
.I1(data1[9]),
.I2(opcode_2[2]),
.I3(\write_output[9]_i_1_n_0 ),
.I4(\program_counter[14]_i_2_n_0 ),
.O(\program_counter[9]_i_1_n_0 ));
FDRE \program_counter_1_reg[0]
(.C(ETH_CLK_OBUF),
.CE(instruction0),
.D(\program_counter_reg_n_0_[0] ),
.Q(program_counter_1[0]),
.R(1'b0));
FDRE \program_counter_1_reg[10]
(.C(ETH_CLK_OBUF),
.CE(instruction0),
.D(\program_counter_reg_n_0_[10] ),
.Q(program_counter_1[10]),
.R(1'b0));
FDRE \program_counter_1_reg[11]
(.C(ETH_CLK_OBUF),
.CE(instruction0),
.D(\program_counter_reg_n_0_[11] ),
.Q(program_counter_1[11]),
.R(1'b0));
FDRE \program_counter_1_reg[12]
(.C(ETH_CLK_OBUF),
.CE(instruction0),
.D(\program_counter_reg_n_0_[12] ),
.Q(program_counter_1[12]),
.R(1'b0));
FDRE \program_counter_1_reg[13]
(.C(ETH_CLK_OBUF),
.CE(instruction0),
.D(\program_counter_reg_n_0_[13] ),
.Q(program_counter_1[13]),
.R(1'b0));
FDRE \program_counter_1_reg[14]
(.C(ETH_CLK_OBUF),
.CE(instruction0),
.D(\program_counter_reg_n_0_[14] ),
.Q(program_counter_1[14]),
.R(1'b0));
FDRE \program_counter_1_reg[15]
(.C(ETH_CLK_OBUF),
.CE(instruction0),
.D(\program_counter_reg_n_0_[15] ),
.Q(program_counter_1[15]),
.R(1'b0));
FDRE \program_counter_1_reg[1]
(.C(ETH_CLK_OBUF),
.CE(instruction0),
.D(\program_counter_reg_n_0_[1] ),
.Q(program_counter_1[1]),
.R(1'b0));
FDRE \program_counter_1_reg[2]
(.C(ETH_CLK_OBUF),
.CE(instruction0),
.D(\program_counter_reg_n_0_[2] ),
.Q(program_counter_1[2]),
.R(1'b0));
FDRE \program_counter_1_reg[3]
(.C(ETH_CLK_OBUF),
.CE(instruction0),
.D(\program_counter_reg_n_0_[3] ),
.Q(program_counter_1[3]),
.R(1'b0));
FDRE \program_counter_1_reg[4]
(.C(ETH_CLK_OBUF),
.CE(instruction0),
.D(\program_counter_reg_n_0_[4] ),
.Q(program_counter_1[4]),
.R(1'b0));
FDRE \program_counter_1_reg[5]
(.C(ETH_CLK_OBUF),
.CE(instruction0),
.D(\program_counter_reg_n_0_[5] ),
.Q(program_counter_1[5]),
.R(1'b0));
FDRE \program_counter_1_reg[6]
(.C(ETH_CLK_OBUF),
.CE(instruction0),
.D(\program_counter_reg_n_0_[6] ),
.Q(program_counter_1[6]),
.R(1'b0));
FDRE \program_counter_1_reg[7]
(.C(ETH_CLK_OBUF),
.CE(instruction0),
.D(\program_counter_reg_n_0_[7] ),
.Q(program_counter_1[7]),
.R(1'b0));
FDRE \program_counter_1_reg[8]
(.C(ETH_CLK_OBUF),
.CE(instruction0),
.D(\program_counter_reg_n_0_[8] ),
.Q(program_counter_1[8]),
.R(1'b0));
FDRE \program_counter_1_reg[9]
(.C(ETH_CLK_OBUF),
.CE(instruction0),
.D(\program_counter_reg_n_0_[9] ),
.Q(program_counter_1[9]),
.R(1'b0));
FDRE \program_counter_2_reg[0]
(.C(ETH_CLK_OBUF),
.CE(opcode_20),
.D(program_counter_1[0]),
.Q(program_counter_2[0]),
.R(1'b0));
FDRE \program_counter_2_reg[10]
(.C(ETH_CLK_OBUF),
.CE(opcode_20),
.D(program_counter_1[10]),
.Q(program_counter_2[10]),
.R(1'b0));
FDRE \program_counter_2_reg[11]
(.C(ETH_CLK_OBUF),
.CE(opcode_20),
.D(program_counter_1[11]),
.Q(program_counter_2[11]),
.R(1'b0));
FDRE \program_counter_2_reg[12]
(.C(ETH_CLK_OBUF),
.CE(opcode_20),
.D(program_counter_1[12]),
.Q(program_counter_2[12]),
.R(1'b0));
FDRE \program_counter_2_reg[13]
(.C(ETH_CLK_OBUF),
.CE(opcode_20),
.D(program_counter_1[13]),
.Q(program_counter_2[13]),
.R(1'b0));
FDRE \program_counter_2_reg[14]
(.C(ETH_CLK_OBUF),
.CE(opcode_20),
.D(program_counter_1[14]),
.Q(program_counter_2[14]),
.R(1'b0));
FDRE \program_counter_2_reg[15]
(.C(ETH_CLK_OBUF),
.CE(opcode_20),
.D(program_counter_1[15]),
.Q(program_counter_2[15]),
.R(1'b0));
FDRE \program_counter_2_reg[1]
(.C(ETH_CLK_OBUF),
.CE(opcode_20),
.D(program_counter_1[1]),
.Q(program_counter_2[1]),
.R(1'b0));
FDRE \program_counter_2_reg[2]
(.C(ETH_CLK_OBUF),
.CE(opcode_20),
.D(program_counter_1[2]),
.Q(program_counter_2[2]),
.R(1'b0));
FDRE \program_counter_2_reg[3]
(.C(ETH_CLK_OBUF),
.CE(opcode_20),
.D(program_counter_1[3]),
.Q(program_counter_2[3]),
.R(1'b0));
FDRE \program_counter_2_reg[4]
(.C(ETH_CLK_OBUF),
.CE(opcode_20),
.D(program_counter_1[4]),
.Q(program_counter_2[4]),
.R(1'b0));
FDRE \program_counter_2_reg[5]
(.C(ETH_CLK_OBUF),
.CE(opcode_20),
.D(program_counter_1[5]),
.Q(program_counter_2[5]),
.R(1'b0));
FDRE \program_counter_2_reg[6]
(.C(ETH_CLK_OBUF),
.CE(opcode_20),
.D(program_counter_1[6]),
.Q(program_counter_2[6]),
.R(1'b0));
FDRE \program_counter_2_reg[7]
(.C(ETH_CLK_OBUF),
.CE(opcode_20),
.D(program_counter_1[7]),
.Q(program_counter_2[7]),
.R(1'b0));
FDRE \program_counter_2_reg[8]
(.C(ETH_CLK_OBUF),
.CE(opcode_20),
.D(program_counter_1[8]),
.Q(program_counter_2[8]),
.R(1'b0));
FDRE \program_counter_2_reg[9]
(.C(ETH_CLK_OBUF),
.CE(opcode_20),
.D(program_counter_1[9]),
.Q(program_counter_2[9]),
.R(1'b0));
FDRE \program_counter_reg[0]
(.C(ETH_CLK_OBUF),
.CE(instruction0),
.D(\program_counter_rep[0]_i_1_n_0 ),
.Q(\program_counter_reg_n_0_[0] ),
.R(INTERNAL_RST_reg));
FDRE \program_counter_reg[10]
(.C(ETH_CLK_OBUF),
.CE(instruction0),
.D(\program_counter[10]_i_1_n_0 ),
.Q(\program_counter_reg_n_0_[10] ),
.R(INTERNAL_RST_reg));
FDRE \program_counter_reg[11]
(.C(ETH_CLK_OBUF),
.CE(instruction0),
.D(\program_counter[11]_i_1_n_0 ),
.Q(\program_counter_reg_n_0_[11] ),
.R(INTERNAL_RST_reg));
FDRE \program_counter_reg[12]
(.C(ETH_CLK_OBUF),
.CE(instruction0),
.D(\program_counter[12]_i_1_n_0 ),
.Q(\program_counter_reg_n_0_[12] ),
.R(INTERNAL_RST_reg));
CARRY4 \program_counter_reg[12]_i_2
(.CI(\program_counter_reg_rep[7]_i_4_n_0 ),
.CO({\program_counter_reg[12]_i_2_n_0 ,\NLW_program_counter_reg[12]_i_2_CO_UNCONNECTED [2:0]}),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(data1[12:9]),
.S({\program_counter_reg_n_0_[12] ,\program_counter_reg_n_0_[11] ,\program_counter_reg_n_0_[10] ,\program_counter_reg_n_0_[9] }));
FDRE \program_counter_reg[13]
(.C(ETH_CLK_OBUF),
.CE(instruction0),
.D(\program_counter[13]_i_1_n_0 ),
.Q(\program_counter_reg_n_0_[13] ),
.R(INTERNAL_RST_reg));
FDRE \program_counter_reg[14]
(.C(ETH_CLK_OBUF),
.CE(instruction0),
.D(\program_counter[14]_i_1_n_0 ),
.Q(\program_counter_reg_n_0_[14] ),
.R(INTERNAL_RST_reg));
FDRE \program_counter_reg[15]
(.C(ETH_CLK_OBUF),
.CE(instruction0),
.D(\program_counter[15]_i_1_n_0 ),
.Q(\program_counter_reg_n_0_[15] ),
.R(INTERNAL_RST_reg));
CARRY4 \program_counter_reg[15]_i_2
(.CI(\program_counter_reg[12]_i_2_n_0 ),
.CO(\NLW_program_counter_reg[15]_i_2_CO_UNCONNECTED [3:0]),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O({\NLW_program_counter_reg[15]_i_2_O_UNCONNECTED [3],data1[15:13]}),
.S({1'b0,\program_counter_reg_n_0_[15] ,\program_counter_reg_n_0_[14] ,\program_counter_reg_n_0_[13] }));
FDRE \program_counter_reg[1]
(.C(ETH_CLK_OBUF),
.CE(instruction0),
.D(\program_counter_rep[1]_i_1_n_0 ),
.Q(\program_counter_reg_n_0_[1] ),
.R(INTERNAL_RST_reg));
FDRE \program_counter_reg[2]
(.C(ETH_CLK_OBUF),
.CE(instruction0),
.D(\program_counter_rep[2]_i_1_n_0 ),
.Q(\program_counter_reg_n_0_[2] ),
.R(INTERNAL_RST_reg));
FDRE \program_counter_reg[3]
(.C(ETH_CLK_OBUF),
.CE(instruction0),
.D(\program_counter_rep[3]_i_1_n_0 ),
.Q(\program_counter_reg_n_0_[3] ),
.R(INTERNAL_RST_reg));
FDRE \program_counter_reg[4]
(.C(ETH_CLK_OBUF),
.CE(instruction0),
.D(\program_counter_rep[4]_i_1_n_0 ),
.Q(\program_counter_reg_n_0_[4] ),
.R(INTERNAL_RST_reg));
FDRE \program_counter_reg[5]
(.C(ETH_CLK_OBUF),
.CE(instruction0),
.D(\program_counter_rep[5]_i_1_n_0 ),
.Q(\program_counter_reg_n_0_[5] ),
.R(INTERNAL_RST_reg));
FDRE \program_counter_reg[6]
(.C(ETH_CLK_OBUF),
.CE(instruction0),
.D(\program_counter_rep[6]_i_1_n_0 ),
.Q(\program_counter_reg_n_0_[6] ),
.R(INTERNAL_RST_reg));
FDRE \program_counter_reg[7]
(.C(ETH_CLK_OBUF),
.CE(instruction0),
.D(\program_counter_rep[7]_i_2_n_0 ),
.Q(\program_counter_reg_n_0_[7] ),
.R(INTERNAL_RST_reg));
FDRE \program_counter_reg[8]
(.C(ETH_CLK_OBUF),
.CE(instruction0),
.D(\program_counter[8]_i_1_n_0 ),
.Q(\program_counter_reg_n_0_[8] ),
.R(INTERNAL_RST_reg));
FDRE \program_counter_reg[9]
(.C(ETH_CLK_OBUF),
.CE(instruction0),
.D(\program_counter[9]_i_1_n_0 ),
.Q(\program_counter_reg_n_0_[9] ),
.R(INTERNAL_RST_reg));
(* equivalent_register_removal = "no" *)
FDRE \program_counter_reg_rep[0]
(.C(ETH_CLK_OBUF),
.CE(instruction0),
.D(\program_counter_rep[0]_i_1_n_0 ),
.Q(\program_counter_reg_rep_n_0_[0] ),
.R(INTERNAL_RST_reg));
(* equivalent_register_removal = "no" *)
FDRE \program_counter_reg_rep[1]
(.C(ETH_CLK_OBUF),
.CE(instruction0),
.D(\program_counter_rep[1]_i_1_n_0 ),
.Q(\program_counter_reg_rep_n_0_[1] ),
.R(INTERNAL_RST_reg));
(* equivalent_register_removal = "no" *)
FDRE \program_counter_reg_rep[2]
(.C(ETH_CLK_OBUF),
.CE(instruction0),
.D(\program_counter_rep[2]_i_1_n_0 ),
.Q(\program_counter_reg_rep_n_0_[2] ),
.R(INTERNAL_RST_reg));
(* equivalent_register_removal = "no" *)
FDRE \program_counter_reg_rep[3]
(.C(ETH_CLK_OBUF),
.CE(instruction0),
.D(\program_counter_rep[3]_i_1_n_0 ),
.Q(\program_counter_reg_rep_n_0_[3] ),
.R(INTERNAL_RST_reg));
(* equivalent_register_removal = "no" *)
FDRE \program_counter_reg_rep[4]
(.C(ETH_CLK_OBUF),
.CE(instruction0),
.D(\program_counter_rep[4]_i_1_n_0 ),
.Q(\program_counter_reg_rep_n_0_[4] ),
.R(INTERNAL_RST_reg));
CARRY4 \program_counter_reg_rep[4]_i_2
(.CI(1'b0),
.CO({\program_counter_reg_rep[4]_i_2_n_0 ,\NLW_program_counter_reg_rep[4]_i_2_CO_UNCONNECTED [2:0]}),
.CYINIT(\program_counter_reg_n_0_[0] ),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(data1[4:1]),
.S({\program_counter_reg_n_0_[4] ,\program_counter_reg_n_0_[3] ,\program_counter_reg_n_0_[2] ,\program_counter_reg_n_0_[1] }));
(* equivalent_register_removal = "no" *)
FDRE \program_counter_reg_rep[5]
(.C(ETH_CLK_OBUF),
.CE(instruction0),
.D(\program_counter_rep[5]_i_1_n_0 ),
.Q(\program_counter_reg_rep_n_0_[5] ),
.R(INTERNAL_RST_reg));
(* equivalent_register_removal = "no" *)
FDRE \program_counter_reg_rep[6]
(.C(ETH_CLK_OBUF),
.CE(instruction0),
.D(\program_counter_rep[6]_i_1_n_0 ),
.Q(\program_counter_reg_rep_n_0_[6] ),
.R(INTERNAL_RST_reg));
(* equivalent_register_removal = "no" *)
FDRE \program_counter_reg_rep[7]
(.C(ETH_CLK_OBUF),
.CE(instruction0),
.D(\program_counter_rep[7]_i_2_n_0 ),
.Q(\program_counter_reg_rep_n_0_[7] ),
.R(INTERNAL_RST_reg));
CARRY4 \program_counter_reg_rep[7]_i_4
(.CI(\program_counter_reg_rep[4]_i_2_n_0 ),
.CO({\program_counter_reg_rep[7]_i_4_n_0 ,\NLW_program_counter_reg_rep[7]_i_4_CO_UNCONNECTED [2:0]}),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(data1[8:5]),
.S({\program_counter_reg_n_0_[8] ,\program_counter_reg_n_0_[7] ,\program_counter_reg_n_0_[6] ,\program_counter_reg_n_0_[5] }));
LUT6 #(
.INIT(64'hF1FFF1F111111111))
\program_counter_rep[0]_i_1
(.I0(\program_counter_rep[7]_i_3_n_0 ),
.I1(\program_counter_reg_n_0_[0] ),
.I2(opcode_2[2]),
.I3(\program_counter_rep[7]_i_5_n_0 ),
.I4(address_b_2[0]),
.I5(\program_counter_rep[0]_i_2_n_0 ),
.O(\program_counter_rep[0]_i_1_n_0 ));
LUT5 #(
.INIT(32'h8A80AAAA))
\program_counter_rep[0]_i_2
(.I0(\program_counter[15]_i_3_n_0 ),
.I1(result[0]),
.I2(operand_a1),
.I3(register_a[0]),
.I4(opcode_2[2]),
.O(\program_counter_rep[0]_i_2_n_0 ));
LUT6 #(
.INIT(64'hF4FFF4F444444444))
\program_counter_rep[1]_i_1
(.I0(\program_counter_rep[7]_i_3_n_0 ),
.I1(data1[1]),
.I2(opcode_2[2]),
.I3(\program_counter_rep[7]_i_5_n_0 ),
.I4(address_b_2[1]),
.I5(\program_counter_rep[1]_i_2_n_0 ),
.O(\program_counter_rep[1]_i_1_n_0 ));
LUT5 #(
.INIT(32'h8A80AAAA))
\program_counter_rep[1]_i_2
(.I0(\program_counter[15]_i_3_n_0 ),
.I1(result[1]),
.I2(operand_a1),
.I3(register_a[1]),
.I4(opcode_2[2]),
.O(\program_counter_rep[1]_i_2_n_0 ));
LUT6 #(
.INIT(64'hF4FFF4F444444444))
\program_counter_rep[2]_i_1
(.I0(\program_counter_rep[7]_i_3_n_0 ),
.I1(data1[2]),
.I2(opcode_2[2]),
.I3(\program_counter_rep[7]_i_5_n_0 ),
.I4(address_b_2[2]),
.I5(\program_counter_rep[2]_i_2_n_0 ),
.O(\program_counter_rep[2]_i_1_n_0 ));
LUT5 #(
.INIT(32'h8A80AAAA))
\program_counter_rep[2]_i_2
(.I0(\program_counter[15]_i_3_n_0 ),
.I1(result[2]),
.I2(operand_a1),
.I3(register_a[2]),
.I4(opcode_2[2]),
.O(\program_counter_rep[2]_i_2_n_0 ));
LUT6 #(
.INIT(64'hF4FFF4F444444444))
\program_counter_rep[3]_i_1
(.I0(\program_counter_rep[7]_i_3_n_0 ),
.I1(data1[3]),
.I2(opcode_2[2]),
.I3(\program_counter_rep[7]_i_5_n_0 ),
.I4(address_b_2[3]),
.I5(\program_counter_rep[3]_i_2_n_0 ),
.O(\program_counter_rep[3]_i_1_n_0 ));
LUT5 #(
.INIT(32'h8A80AAAA))
\program_counter_rep[3]_i_2
(.I0(\program_counter[15]_i_3_n_0 ),
.I1(result[3]),
.I2(operand_a1),
.I3(register_a[3]),
.I4(opcode_2[2]),
.O(\program_counter_rep[3]_i_2_n_0 ));
LUT6 #(
.INIT(64'hF4FFF4F444444444))
\program_counter_rep[4]_i_1
(.I0(\program_counter_rep[7]_i_3_n_0 ),
.I1(data1[4]),
.I2(opcode_2[2]),
.I3(\program_counter_rep[7]_i_5_n_0 ),
.I4(literal_2[4]),
.I5(\program_counter_rep[4]_i_3_n_0 ),
.O(\program_counter_rep[4]_i_1_n_0 ));
LUT5 #(
.INIT(32'h8A80AAAA))
\program_counter_rep[4]_i_3
(.I0(\program_counter[15]_i_3_n_0 ),
.I1(result[4]),
.I2(operand_a1),
.I3(register_a[4]),
.I4(opcode_2[2]),
.O(\program_counter_rep[4]_i_3_n_0 ));
LUT6 #(
.INIT(64'hF4FFF4F444444444))
\program_counter_rep[5]_i_1
(.I0(\program_counter_rep[7]_i_3_n_0 ),
.I1(data1[5]),
.I2(opcode_2[2]),
.I3(\program_counter_rep[7]_i_5_n_0 ),
.I4(literal_2[5]),
.I5(\program_counter_rep[5]_i_2_n_0 ),
.O(\program_counter_rep[5]_i_1_n_0 ));
LUT5 #(
.INIT(32'h8A80AAAA))
\program_counter_rep[5]_i_2
(.I0(\program_counter[15]_i_3_n_0 ),
.I1(result[5]),
.I2(operand_a1),
.I3(register_a[5]),
.I4(opcode_2[2]),
.O(\program_counter_rep[5]_i_2_n_0 ));
LUT6 #(
.INIT(64'hF4FFF4F444444444))
\program_counter_rep[6]_i_1
(.I0(\program_counter_rep[7]_i_3_n_0 ),
.I1(data1[6]),
.I2(opcode_2[2]),
.I3(\program_counter_rep[7]_i_5_n_0 ),
.I4(literal_2[6]),
.I5(\program_counter_rep[6]_i_2_n_0 ),
.O(\program_counter_rep[6]_i_1_n_0 ));
LUT5 #(
.INIT(32'h8A80AAAA))
\program_counter_rep[6]_i_2
(.I0(\program_counter[15]_i_3_n_0 ),
.I1(result[6]),
.I2(operand_a1),
.I3(register_a[6]),
.I4(opcode_2[2]),
.O(\program_counter_rep[6]_i_2_n_0 ));
LUT3 #(
.INIT(8'h32))
\program_counter_rep[7]_i_1
(.I0(\state_reg_n_0_[1] ),
.I1(\state_reg_n_0_[2] ),
.I2(\state_reg_n_0_[0] ),
.O(instruction0));
LUT5 #(
.INIT(32'hFFFFFFFE))
\program_counter_rep[7]_i_10
(.I0(\write_output[1]_i_1_n_0 ),
.I1(\write_output[0]_i_1_n_0 ),
.I2(\program_counter_rep[7]_i_26_n_0 ),
.I3(\write_output[2]_i_1_n_0 ),
.I4(\write_output[3]_i_1_n_0 ),
.O(\program_counter_rep[7]_i_10_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFFFFFFE))
\program_counter_rep[7]_i_15
(.I0(\write_output[3]_i_1_n_0 ),
.I1(\write_output[2]_i_1_n_0 ),
.I2(\write_output[6]_i_1_n_0 ),
.I3(\write_output[7]_i_1_n_0 ),
.I4(\write_output[4]_i_1_n_0 ),
.I5(\write_output[5]_i_1_n_0 ),
.O(\program_counter_rep[7]_i_15_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFEFFFEEE))
\program_counter_rep[7]_i_16
(.I0(\write_output[11]_i_1_n_0 ),
.I1(\write_output[10]_i_1_n_0 ),
.I2(result[13]),
.I3(operand_a1),
.I4(register_a[13]),
.I5(\write_output[12]_i_1_n_0 ),
.O(\program_counter_rep[7]_i_16_n_0 ));
LUT5 #(
.INIT(32'hFFFACCFA))
\program_counter_rep[7]_i_17
(.I0(register_a[16]),
.I1(result[16]),
.I2(register_a[17]),
.I3(operand_a1),
.I4(result[17]),
.O(\program_counter_rep[7]_i_17_n_0 ));
LUT5 #(
.INIT(32'hFFFACCFA))
\program_counter_rep[7]_i_18
(.I0(register_a[18]),
.I1(result[18]),
.I2(register_a[19]),
.I3(operand_a1),
.I4(result[19]),
.O(\program_counter_rep[7]_i_18_n_0 ));
LUT5 #(
.INIT(32'hFFFACCFA))
\program_counter_rep[7]_i_19
(.I0(register_a[14]),
.I1(result[14]),
.I2(register_a[15]),
.I3(operand_a1),
.I4(result[15]),
.O(\program_counter_rep[7]_i_19_n_0 ));
LUT6 #(
.INIT(64'hF4FFF4F444444444))
\program_counter_rep[7]_i_2
(.I0(\program_counter_rep[7]_i_3_n_0 ),
.I1(data1[7]),
.I2(opcode_2[2]),
.I3(\program_counter_rep[7]_i_5_n_0 ),
.I4(literal_2[7]),
.I5(\program_counter_rep[7]_i_6_n_0 ),
.O(\program_counter_rep[7]_i_2_n_0 ));
LUT5 #(
.INIT(32'hFFFACCFA))
\program_counter_rep[7]_i_20
(.I0(register_a[22]),
.I1(result[22]),
.I2(register_a[23]),
.I3(operand_a1),
.I4(result[23]),
.O(\program_counter_rep[7]_i_20_n_0 ));
LUT5 #(
.INIT(32'hFFFACCFA))
\program_counter_rep[7]_i_21
(.I0(register_a[24]),
.I1(result[24]),
.I2(register_a[25]),
.I3(operand_a1),
.I4(result[25]),
.O(\program_counter_rep[7]_i_21_n_0 ));
LUT5 #(
.INIT(32'hFFFACCFA))
\program_counter_rep[7]_i_22
(.I0(register_a[20]),
.I1(result[20]),
.I2(register_a[21]),
.I3(operand_a1),
.I4(result[21]),
.O(\program_counter_rep[7]_i_22_n_0 ));
LUT5 #(
.INIT(32'hFFFACCFA))
\program_counter_rep[7]_i_23
(.I0(register_a[28]),
.I1(result[28]),
.I2(register_a[29]),
.I3(operand_a1),
.I4(result[29]),
.O(\program_counter_rep[7]_i_23_n_0 ));
LUT5 #(
.INIT(32'hFFFACCFA))
\program_counter_rep[7]_i_24
(.I0(register_a[30]),
.I1(result[30]),
.I2(register_a[31]),
.I3(operand_a1),
.I4(result[31]),
.O(\program_counter_rep[7]_i_24_n_0 ));
LUT5 #(
.INIT(32'hFFFACCFA))
\program_counter_rep[7]_i_25
(.I0(register_a[26]),
.I1(result[26]),
.I2(register_a[27]),
.I3(operand_a1),
.I4(result[27]),
.O(\program_counter_rep[7]_i_25_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFFFEFEA))
\program_counter_rep[7]_i_26
(.I0(\write_output[5]_i_1_n_0 ),
.I1(result[4]),
.I2(operand_a1),
.I3(register_a[4]),
.I4(\write_output[7]_i_1_n_0 ),
.I5(\write_output[6]_i_1_n_0 ),
.O(\program_counter_rep[7]_i_26_n_0 ));
LUT6 #(
.INIT(64'hAAAAAAAA8888888A))
\program_counter_rep[7]_i_3
(.I0(\program_counter[15]_i_3_n_0 ),
.I1(\program_counter_rep[7]_i_7_n_0 ),
.I2(\program_counter_rep[7]_i_8_n_0 ),
.I3(\program_counter_rep[7]_i_9_n_0 ),
.I4(\program_counter_rep[7]_i_10_n_0 ),
.I5(opcode_2[1]),
.O(\program_counter_rep[7]_i_3_n_0 ));
LUT6 #(
.INIT(64'h00000000FFFFFFFE))
\program_counter_rep[7]_i_5
(.I0(\program_counter_rep[7]_i_8_n_0 ),
.I1(\program_counter_rep[7]_i_9_n_0 ),
.I2(\write_output[1]_i_1_n_0 ),
.I3(\write_output[0]_i_1_n_0 ),
.I4(\program_counter_rep[7]_i_15_n_0 ),
.I5(opcode_2[1]),
.O(\program_counter_rep[7]_i_5_n_0 ));
LUT5 #(
.INIT(32'h8A80AAAA))
\program_counter_rep[7]_i_6
(.I0(\program_counter[15]_i_3_n_0 ),
.I1(result[7]),
.I2(operand_a1),
.I3(register_a[7]),
.I4(opcode_2[2]),
.O(\program_counter_rep[7]_i_6_n_0 ));
LUT4 #(
.INIT(16'h02A2))
\program_counter_rep[7]_i_7
(.I0(opcode_2[2]),
.I1(register_a[15]),
.I2(operand_a1),
.I3(result[15]),
.O(\program_counter_rep[7]_i_7_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFFFFFFE))
\program_counter_rep[7]_i_8
(.I0(\program_counter_rep[7]_i_16_n_0 ),
.I1(\write_output[8]_i_1_n_0 ),
.I2(\write_output[9]_i_1_n_0 ),
.I3(\program_counter_rep[7]_i_17_n_0 ),
.I4(\program_counter_rep[7]_i_18_n_0 ),
.I5(\program_counter_rep[7]_i_19_n_0 ),
.O(\program_counter_rep[7]_i_8_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFFFFFFE))
\program_counter_rep[7]_i_9
(.I0(\program_counter_rep[7]_i_20_n_0 ),
.I1(\program_counter_rep[7]_i_21_n_0 ),
.I2(\program_counter_rep[7]_i_22_n_0 ),
.I3(\program_counter_rep[7]_i_23_n_0 ),
.I4(\program_counter_rep[7]_i_24_n_0 ),
.I5(\program_counter_rep[7]_i_25_n_0 ),
.O(\program_counter_rep[7]_i_9_n_0 ));
(* INIT_A = "64'h0000000000000000" *)
(* INIT_B = "64'h0000000000000000" *)
(* INIT_C = "64'h0000000000000000" *)
(* INIT_D = "64'h0000000000000000" *)
RAM32M_UNIQ_BASE_ registers_reg_r1_0_15_0_5
(.ADDRA({1'b0,address_b_2}),
.ADDRB({1'b0,address_b_2}),
.ADDRC({1'b0,address_b_2}),
.ADDRD({1'b0,address_z_3}),
.DIA(result[1:0]),
.DIB(result[3:2]),
.DIC(result[5:4]),
.DID({1'b0,1'b0}),
.DOA(register_b[1:0]),
.DOB(register_b[3:2]),
.DOC(register_b[5:4]),
.DOD(NLW_registers_reg_r1_0_15_0_5_DOD_UNCONNECTED[1:0]),
.WCLK(ETH_CLK_OBUF),
.WE(write_enable));
(* INIT_A = "64'h0000000000000000" *)
(* INIT_B = "64'h0000000000000000" *)
(* INIT_C = "64'h0000000000000000" *)
(* INIT_D = "64'h0000000000000000" *)
RAM32M_HD5 registers_reg_r1_0_15_12_17
(.ADDRA({1'b0,address_b_2}),
.ADDRB({1'b0,address_b_2}),
.ADDRC({1'b0,address_b_2}),
.ADDRD({1'b0,address_z_3}),
.DIA(result[13:12]),
.DIB(result[15:14]),
.DIC(result[17:16]),
.DID({1'b0,1'b0}),
.DOA(register_b[13:12]),
.DOB(register_b[15:14]),
.DOC(register_b[17:16]),
.DOD(NLW_registers_reg_r1_0_15_12_17_DOD_UNCONNECTED[1:0]),
.WCLK(ETH_CLK_OBUF),
.WE(write_enable));
(* INIT_A = "64'h0000000000000000" *)
(* INIT_B = "64'h0000000000000000" *)
(* INIT_C = "64'h0000000000000000" *)
(* INIT_D = "64'h0000000000000000" *)
RAM32M_HD6 registers_reg_r1_0_15_18_23
(.ADDRA({1'b0,address_b_2}),
.ADDRB({1'b0,address_b_2}),
.ADDRC({1'b0,address_b_2}),
.ADDRD({1'b0,address_z_3}),
.DIA(result[19:18]),
.DIB(result[21:20]),
.DIC(result[23:22]),
.DID({1'b0,1'b0}),
.DOA(register_b[19:18]),
.DOB(register_b[21:20]),
.DOC(register_b[23:22]),
.DOD(NLW_registers_reg_r1_0_15_18_23_DOD_UNCONNECTED[1:0]),
.WCLK(ETH_CLK_OBUF),
.WE(write_enable));
(* INIT_A = "64'h0000000000000000" *)
(* INIT_B = "64'h0000000000000000" *)
(* INIT_C = "64'h0000000000000000" *)
(* INIT_D = "64'h0000000000000000" *)
RAM32M_HD7 registers_reg_r1_0_15_24_29
(.ADDRA({1'b0,address_b_2}),
.ADDRB({1'b0,address_b_2}),
.ADDRC({1'b0,address_b_2}),
.ADDRD({1'b0,address_z_3}),
.DIA(result[25:24]),
.DIB(result[27:26]),
.DIC(result[29:28]),
.DID({1'b0,1'b0}),
.DOA(register_b[25:24]),
.DOB(register_b[27:26]),
.DOC(register_b[29:28]),
.DOD(NLW_registers_reg_r1_0_15_24_29_DOD_UNCONNECTED[1:0]),
.WCLK(ETH_CLK_OBUF),
.WE(write_enable));
(* INIT_A = "64'h0000000000000000" *)
(* INIT_B = "64'h0000000000000000" *)
(* INIT_C = "64'h0000000000000000" *)
(* INIT_D = "64'h0000000000000000" *)
RAM32M_HD8 registers_reg_r1_0_15_30_31
(.ADDRA({1'b0,address_b_2}),
.ADDRB({1'b0,address_b_2}),
.ADDRC({1'b0,address_b_2}),
.ADDRD({1'b0,address_z_3}),
.DIA(result[31:30]),
.DIB({1'b0,1'b0}),
.DIC({1'b0,1'b0}),
.DID({1'b0,1'b0}),
.DOA(register_b[31:30]),
.DOB(NLW_registers_reg_r1_0_15_30_31_DOB_UNCONNECTED[1:0]),
.DOC(NLW_registers_reg_r1_0_15_30_31_DOC_UNCONNECTED[1:0]),
.DOD(NLW_registers_reg_r1_0_15_30_31_DOD_UNCONNECTED[1:0]),
.WCLK(ETH_CLK_OBUF),
.WE(write_enable));
(* INIT_A = "64'h0000000000000000" *)
(* INIT_B = "64'h0000000000000000" *)
(* INIT_C = "64'h0000000000000000" *)
(* INIT_D = "64'h0000000000000000" *)
RAM32M_HD4 registers_reg_r1_0_15_6_11
(.ADDRA({1'b0,address_b_2}),
.ADDRB({1'b0,address_b_2}),
.ADDRC({1'b0,address_b_2}),
.ADDRD({1'b0,address_z_3}),
.DIA(result[7:6]),
.DIB(result[9:8]),
.DIC(result[11:10]),
.DID({1'b0,1'b0}),
.DOA(register_b[7:6]),
.DOB(register_b[9:8]),
.DOC(register_b[11:10]),
.DOD(NLW_registers_reg_r1_0_15_6_11_DOD_UNCONNECTED[1:0]),
.WCLK(ETH_CLK_OBUF),
.WE(write_enable));
(* INIT_A = "64'h0000000000000000" *)
(* INIT_B = "64'h0000000000000000" *)
(* INIT_C = "64'h0000000000000000" *)
(* INIT_D = "64'h0000000000000000" *)
RAM32M_HD9 registers_reg_r2_0_15_0_5
(.ADDRA({1'b0,address_a_2}),
.ADDRB({1'b0,address_a_2}),
.ADDRC({1'b0,address_a_2}),
.ADDRD({1'b0,address_z_3}),
.DIA(result[1:0]),
.DIB(result[3:2]),
.DIC(result[5:4]),
.DID({1'b0,1'b0}),
.DOA(register_a[1:0]),
.DOB(register_a[3:2]),
.DOC(register_a[5:4]),
.DOD(NLW_registers_reg_r2_0_15_0_5_DOD_UNCONNECTED[1:0]),
.WCLK(ETH_CLK_OBUF),
.WE(write_enable));
(* INIT_A = "64'h0000000000000000" *)
(* INIT_B = "64'h0000000000000000" *)
(* INIT_C = "64'h0000000000000000" *)
(* INIT_D = "64'h0000000000000000" *)
RAM32M_HD11 registers_reg_r2_0_15_12_17
(.ADDRA({1'b0,address_a_2}),
.ADDRB({1'b0,address_a_2}),
.ADDRC({1'b0,address_a_2}),
.ADDRD({1'b0,address_z_3}),
.DIA(result[13:12]),
.DIB(result[15:14]),
.DIC(result[17:16]),
.DID({1'b0,1'b0}),
.DOA(register_a[13:12]),
.DOB(register_a[15:14]),
.DOC(register_a[17:16]),
.DOD(NLW_registers_reg_r2_0_15_12_17_DOD_UNCONNECTED[1:0]),
.WCLK(ETH_CLK_OBUF),
.WE(write_enable));
(* INIT_A = "64'h0000000000000000" *)
(* INIT_B = "64'h0000000000000000" *)
(* INIT_C = "64'h0000000000000000" *)
(* INIT_D = "64'h0000000000000000" *)
RAM32M_HD12 registers_reg_r2_0_15_18_23
(.ADDRA({1'b0,address_a_2}),
.ADDRB({1'b0,address_a_2}),
.ADDRC({1'b0,address_a_2}),
.ADDRD({1'b0,address_z_3}),
.DIA(result[19:18]),
.DIB(result[21:20]),
.DIC(result[23:22]),
.DID({1'b0,1'b0}),
.DOA(register_a[19:18]),
.DOB(register_a[21:20]),
.DOC(register_a[23:22]),
.DOD(NLW_registers_reg_r2_0_15_18_23_DOD_UNCONNECTED[1:0]),
.WCLK(ETH_CLK_OBUF),
.WE(write_enable));
(* INIT_A = "64'h0000000000000000" *)
(* INIT_B = "64'h0000000000000000" *)
(* INIT_C = "64'h0000000000000000" *)
(* INIT_D = "64'h0000000000000000" *)
RAM32M_HD13 registers_reg_r2_0_15_24_29
(.ADDRA({1'b0,address_a_2}),
.ADDRB({1'b0,address_a_2}),
.ADDRC({1'b0,address_a_2}),
.ADDRD({1'b0,address_z_3}),
.DIA(result[25:24]),
.DIB(result[27:26]),
.DIC(result[29:28]),
.DID({1'b0,1'b0}),
.DOA(register_a[25:24]),
.DOB(register_a[27:26]),
.DOC(register_a[29:28]),
.DOD(NLW_registers_reg_r2_0_15_24_29_DOD_UNCONNECTED[1:0]),
.WCLK(ETH_CLK_OBUF),
.WE(write_enable));
(* INIT_A = "64'h0000000000000000" *)
(* INIT_B = "64'h0000000000000000" *)
(* INIT_C = "64'h0000000000000000" *)
(* INIT_D = "64'h0000000000000000" *)
RAM32M_HD14 registers_reg_r2_0_15_30_31
(.ADDRA({1'b0,address_a_2}),
.ADDRB({1'b0,address_a_2}),
.ADDRC({1'b0,address_a_2}),
.ADDRD({1'b0,address_z_3}),
.DIA(result[31:30]),
.DIB({1'b0,1'b0}),
.DIC({1'b0,1'b0}),
.DID({1'b0,1'b0}),
.DOA(register_a[31:30]),
.DOB(NLW_registers_reg_r2_0_15_30_31_DOB_UNCONNECTED[1:0]),
.DOC(NLW_registers_reg_r2_0_15_30_31_DOC_UNCONNECTED[1:0]),
.DOD(NLW_registers_reg_r2_0_15_30_31_DOD_UNCONNECTED[1:0]),
.WCLK(ETH_CLK_OBUF),
.WE(write_enable));
(* INIT_A = "64'h0000000000000000" *)
(* INIT_B = "64'h0000000000000000" *)
(* INIT_C = "64'h0000000000000000" *)
(* INIT_D = "64'h0000000000000000" *)
RAM32M_HD10 registers_reg_r2_0_15_6_11
(.ADDRA({1'b0,address_a_2}),
.ADDRB({1'b0,address_a_2}),
.ADDRC({1'b0,address_a_2}),
.ADDRD({1'b0,address_z_3}),
.DIA(result[7:6]),
.DIB(result[9:8]),
.DIC(result[11:10]),
.DID({1'b0,1'b0}),
.DOA(register_a[7:6]),
.DOB(register_a[9:8]),
.DOC(register_a[11:10]),
.DOD(NLW_registers_reg_r2_0_15_6_11_DOD_UNCONNECTED[1:0]),
.WCLK(ETH_CLK_OBUF),
.WE(write_enable));
(* SOFT_HLUTNM = "soft_lutpair70" *)
LUT3 #(
.INIT(8'hB8))
\result[0]_i_1
(.I0(\result[0]_i_2_n_0 ),
.I1(\state_reg_n_0_[0] ),
.I2(load_data[0]),
.O(\result[0]_i_1_n_0 ));
LUT6 #(
.INIT(64'hA0A0AFAFCFC0CFC0))
\result[0]_i_2
(.I0(address_b_2[0]),
.I1(\result_reg[3]_i_3_n_7 ),
.I2(\result[31]_i_3_n_0 ),
.I3(data3[0]),
.I4(program_counter_2[0]),
.I5(\result[16]_i_4_n_0 ),
.O(\result[0]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair68" *)
LUT3 #(
.INIT(8'hB8))
\result[10]_i_1
(.I0(\result[10]_i_2_n_0 ),
.I1(\state_reg_n_0_[0] ),
.I2(load_data[10]),
.O(\result[10]_i_1_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\result[10]_i_2
(.I0(literal_2[15]),
.I1(\result_reg[11]_i_3_n_5 ),
.I2(\result[31]_i_3_n_0 ),
.I3(data2[10]),
.I4(\result[16]_i_4_n_0 ),
.I5(data3[10]),
.O(\result[10]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair73" *)
LUT3 #(
.INIT(8'hB8))
\result[11]_i_1
(.I0(\result[11]_i_2_n_0 ),
.I1(\state_reg_n_0_[0] ),
.I2(load_data[11]),
.O(\result[11]_i_1_n_0 ));
LUT5 #(
.INIT(32'h111E22D2))
\result[11]_i_10
(.I0(register_a[10]),
.I1(operand_a1),
.I2(register_b[10]),
.I3(operand_b1),
.I4(result[10]),
.O(\result[11]_i_10_n_0 ));
LUT5 #(
.INIT(32'h111E22D2))
\result[11]_i_11
(.I0(register_a[9]),
.I1(operand_a1),
.I2(register_b[9]),
.I3(operand_b1),
.I4(result[9]),
.O(\result[11]_i_11_n_0 ));
LUT5 #(
.INIT(32'h111E22D2))
\result[11]_i_12
(.I0(register_a[8]),
.I1(operand_a1),
.I2(register_b[8]),
.I3(operand_b1),
.I4(result[8]),
.O(\result[11]_i_12_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\result[11]_i_2
(.I0(literal_2[15]),
.I1(\result_reg[11]_i_3_n_4 ),
.I2(\result[31]_i_3_n_0 ),
.I3(data2[11]),
.I4(\result[16]_i_4_n_0 ),
.I5(data3[11]),
.O(\result[11]_i_2_n_0 ));
LUT4 #(
.INIT(16'h1DE2))
\result[11]_i_5
(.I0(register_a[11]),
.I1(operand_a1),
.I2(result[11]),
.I3(literal_2[15]),
.O(\result[11]_i_5_n_0 ));
LUT4 #(
.INIT(16'h1DE2))
\result[11]_i_6
(.I0(register_a[10]),
.I1(operand_a1),
.I2(result[10]),
.I3(literal_2[15]),
.O(\result[11]_i_6_n_0 ));
LUT4 #(
.INIT(16'h1DE2))
\result[11]_i_7
(.I0(register_a[9]),
.I1(operand_a1),
.I2(result[9]),
.I3(literal_2[15]),
.O(\result[11]_i_7_n_0 ));
LUT4 #(
.INIT(16'h1DE2))
\result[11]_i_8
(.I0(register_a[8]),
.I1(operand_a1),
.I2(result[8]),
.I3(literal_2[15]),
.O(\result[11]_i_8_n_0 ));
LUT5 #(
.INIT(32'h111E22D2))
\result[11]_i_9
(.I0(register_a[11]),
.I1(operand_a1),
.I2(register_b[11]),
.I3(operand_b1),
.I4(result[11]),
.O(\result[11]_i_9_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair71" *)
LUT3 #(
.INIT(8'hB8))
\result[12]_i_1
(.I0(\result[12]_i_2_n_0 ),
.I1(\state_reg_n_0_[0] ),
.I2(load_data[12]),
.O(\result[12]_i_1_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\result[12]_i_2
(.I0(literal_2[15]),
.I1(\result_reg[15]_i_3_n_7 ),
.I2(\result[31]_i_3_n_0 ),
.I3(data2[12]),
.I4(\result[16]_i_4_n_0 ),
.I5(data3[12]),
.O(\result[12]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair66" *)
LUT3 #(
.INIT(8'hB8))
\result[13]_i_1
(.I0(\result[13]_i_2_n_0 ),
.I1(\state_reg_n_0_[0] ),
.I2(load_data[13]),
.O(\result[13]_i_1_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\result[13]_i_2
(.I0(literal_2[15]),
.I1(\result_reg[15]_i_3_n_6 ),
.I2(\result[31]_i_3_n_0 ),
.I3(data2[13]),
.I4(\result[16]_i_4_n_0 ),
.I5(data3[13]),
.O(\result[13]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair67" *)
LUT3 #(
.INIT(8'hB8))
\result[14]_i_1
(.I0(\result[14]_i_2_n_0 ),
.I1(\state_reg_n_0_[0] ),
.I2(load_data[14]),
.O(\result[14]_i_1_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\result[14]_i_2
(.I0(literal_2[15]),
.I1(\result_reg[15]_i_3_n_5 ),
.I2(\result[31]_i_3_n_0 ),
.I3(data2[14]),
.I4(\result[16]_i_4_n_0 ),
.I5(data3[14]),
.O(\result[14]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair73" *)
LUT3 #(
.INIT(8'hB8))
\result[15]_i_1
(.I0(\result[15]_i_2_n_0 ),
.I1(\state_reg_n_0_[0] ),
.I2(load_data[15]),
.O(\result[15]_i_1_n_0 ));
LUT5 #(
.INIT(32'h111E22D2))
\result[15]_i_10
(.I0(register_a[14]),
.I1(operand_a1),
.I2(register_b[14]),
.I3(operand_b1),
.I4(result[14]),
.O(\result[15]_i_10_n_0 ));
LUT5 #(
.INIT(32'h111E22D2))
\result[15]_i_11
(.I0(register_a[13]),
.I1(operand_a1),
.I2(register_b[13]),
.I3(operand_b1),
.I4(result[13]),
.O(\result[15]_i_11_n_0 ));
LUT5 #(
.INIT(32'h111E22D2))
\result[15]_i_12
(.I0(register_a[12]),
.I1(operand_a1),
.I2(register_b[12]),
.I3(operand_b1),
.I4(result[12]),
.O(\result[15]_i_12_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\result[15]_i_2
(.I0(literal_2[15]),
.I1(\result_reg[15]_i_3_n_4 ),
.I2(\result[31]_i_3_n_0 ),
.I3(data2[15]),
.I4(\result[16]_i_4_n_0 ),
.I5(data3[15]),
.O(\result[15]_i_2_n_0 ));
LUT4 #(
.INIT(16'h1DE2))
\result[15]_i_5
(.I0(register_a[15]),
.I1(operand_a1),
.I2(result[15]),
.I3(literal_2[15]),
.O(\result[15]_i_5_n_0 ));
LUT4 #(
.INIT(16'h1DE2))
\result[15]_i_6
(.I0(register_a[14]),
.I1(operand_a1),
.I2(result[14]),
.I3(literal_2[15]),
.O(\result[15]_i_6_n_0 ));
LUT4 #(
.INIT(16'h1DE2))
\result[15]_i_7
(.I0(register_a[13]),
.I1(operand_a1),
.I2(result[13]),
.I3(literal_2[15]),
.O(\result[15]_i_7_n_0 ));
LUT4 #(
.INIT(16'h1DE2))
\result[15]_i_8
(.I0(register_a[12]),
.I1(operand_a1),
.I2(result[12]),
.I3(literal_2[15]),
.O(\result[15]_i_8_n_0 ));
LUT5 #(
.INIT(32'h111E22D2))
\result[15]_i_9
(.I0(register_a[15]),
.I1(operand_a1),
.I2(register_b[15]),
.I3(operand_b1),
.I4(result[15]),
.O(\result[15]_i_9_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair72" *)
LUT3 #(
.INIT(8'hB8))
\result[16]_i_1
(.I0(\result[16]_i_2_n_0 ),
.I1(\state_reg_n_0_[0] ),
.I2(load_data[16]),
.O(\result[16]_i_1_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\result[16]_i_2
(.I0(literal_2[15]),
.I1(\result_reg[19]_i_3_n_7 ),
.I2(\result[31]_i_3_n_0 ),
.I3(data2[16]),
.I4(\result[16]_i_4_n_0 ),
.I5(data3[16]),
.O(\result[16]_i_2_n_0 ));
LUT3 #(
.INIT(8'h45))
\result[16]_i_4
(.I0(opcode_2[2]),
.I1(opcode_2[1]),
.I2(opcode_2[0]),
.O(\result[16]_i_4_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair74" *)
LUT3 #(
.INIT(8'hB8))
\result[17]_i_1
(.I0(\result[17]_i_2_n_0 ),
.I1(\state_reg_n_0_[0] ),
.I2(load_data[17]),
.O(\result[17]_i_1_n_0 ));
LUT6 #(
.INIT(64'hF0FC000CF0FA000A))
\result[17]_i_2
(.I0(literal_2[15]),
.I1(\result_reg[19]_i_3_n_6 ),
.I2(opcode_2[2]),
.I3(opcode_2[1]),
.I4(data3[17]),
.I5(opcode_2[0]),
.O(\result[17]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair74" *)
LUT3 #(
.INIT(8'hB8))
\result[18]_i_1
(.I0(\result[18]_i_2_n_0 ),
.I1(\state_reg_n_0_[0] ),
.I2(load_data[18]),
.O(\result[18]_i_1_n_0 ));
LUT6 #(
.INIT(64'hF0FC000CF0FA000A))
\result[18]_i_2
(.I0(literal_2[15]),
.I1(\result_reg[19]_i_3_n_5 ),
.I2(opcode_2[2]),
.I3(opcode_2[1]),
.I4(data3[18]),
.I5(opcode_2[0]),
.O(\result[18]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair75" *)
LUT3 #(
.INIT(8'hB8))
\result[19]_i_1
(.I0(\result[19]_i_2_n_0 ),
.I1(\state_reg_n_0_[0] ),
.I2(load_data[19]),
.O(\result[19]_i_1_n_0 ));
LUT5 #(
.INIT(32'h111E22D2))
\result[19]_i_10
(.I0(register_a[18]),
.I1(operand_a1),
.I2(register_b[18]),
.I3(operand_b1),
.I4(result[18]),
.O(\result[19]_i_10_n_0 ));
LUT5 #(
.INIT(32'h111E22D2))
\result[19]_i_11
(.I0(register_a[17]),
.I1(operand_a1),
.I2(register_b[17]),
.I3(operand_b1),
.I4(result[17]),
.O(\result[19]_i_11_n_0 ));
LUT5 #(
.INIT(32'h111E22D2))
\result[19]_i_12
(.I0(register_a[16]),
.I1(operand_a1),
.I2(register_b[16]),
.I3(operand_b1),
.I4(result[16]),
.O(\result[19]_i_12_n_0 ));
LUT6 #(
.INIT(64'hF0FC000CF0FA000A))
\result[19]_i_2
(.I0(literal_2[15]),
.I1(\result_reg[19]_i_3_n_4 ),
.I2(opcode_2[2]),
.I3(opcode_2[1]),
.I4(data3[19]),
.I5(opcode_2[0]),
.O(\result[19]_i_2_n_0 ));
LUT5 #(
.INIT(32'hFFFB0008))
\result[19]_i_5
(.I0(result[19]),
.I1(write_enable),
.I2(\write_output[31]_i_3_n_0 ),
.I3(\write_output[31]_i_4_n_0 ),
.I4(register_a[19]),
.O(\result[19]_i_5_n_0 ));
LUT5 #(
.INIT(32'hFFFB0008))
\result[19]_i_6
(.I0(result[18]),
.I1(write_enable),
.I2(\write_output[31]_i_3_n_0 ),
.I3(\write_output[31]_i_4_n_0 ),
.I4(register_a[18]),
.O(\result[19]_i_6_n_0 ));
LUT5 #(
.INIT(32'hFFFB0008))
\result[19]_i_7
(.I0(result[17]),
.I1(write_enable),
.I2(\write_output[31]_i_3_n_0 ),
.I3(\write_output[31]_i_4_n_0 ),
.I4(register_a[17]),
.O(\result[19]_i_7_n_0 ));
LUT5 #(
.INIT(32'hFFFB0008))
\result[19]_i_8
(.I0(result[16]),
.I1(write_enable),
.I2(\write_output[31]_i_3_n_0 ),
.I3(\write_output[31]_i_4_n_0 ),
.I4(register_a[16]),
.O(\result[19]_i_8_n_0 ));
LUT5 #(
.INIT(32'h111E22D2))
\result[19]_i_9
(.I0(register_a[19]),
.I1(operand_a1),
.I2(register_b[19]),
.I3(operand_b1),
.I4(result[19]),
.O(\result[19]_i_9_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair69" *)
LUT3 #(
.INIT(8'hB8))
\result[1]_i_1
(.I0(\result[1]_i_2_n_0 ),
.I1(\state_reg_n_0_[0] ),
.I2(load_data[1]),
.O(\result[1]_i_1_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\result[1]_i_2
(.I0(address_b_2[1]),
.I1(\result_reg[3]_i_3_n_6 ),
.I2(\result[31]_i_3_n_0 ),
.I3(data2[1]),
.I4(\result[16]_i_4_n_0 ),
.I5(data3[1]),
.O(\result[1]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair76" *)
LUT3 #(
.INIT(8'hB8))
\result[20]_i_1
(.I0(\result[20]_i_2_n_0 ),
.I1(\state_reg_n_0_[0] ),
.I2(load_data[20]),
.O(\result[20]_i_1_n_0 ));
LUT6 #(
.INIT(64'hF0FC000CF0FA000A))
\result[20]_i_2
(.I0(literal_2[15]),
.I1(\result_reg[23]_i_3_n_7 ),
.I2(opcode_2[2]),
.I3(opcode_2[1]),
.I4(data3[20]),
.I5(opcode_2[0]),
.O(\result[20]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair75" *)
LUT3 #(
.INIT(8'hB8))
\result[21]_i_1
(.I0(\result[21]_i_2_n_0 ),
.I1(\state_reg_n_0_[0] ),
.I2(load_data[21]),
.O(\result[21]_i_1_n_0 ));
LUT6 #(
.INIT(64'hF0FC000CF0FA000A))
\result[21]_i_2
(.I0(literal_2[15]),
.I1(\result_reg[23]_i_3_n_6 ),
.I2(opcode_2[2]),
.I3(opcode_2[1]),
.I4(data3[21]),
.I5(opcode_2[0]),
.O(\result[21]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair76" *)
LUT3 #(
.INIT(8'hB8))
\result[22]_i_1
(.I0(\result[22]_i_2_n_0 ),
.I1(\state_reg_n_0_[0] ),
.I2(load_data[22]),
.O(\result[22]_i_1_n_0 ));
LUT6 #(
.INIT(64'hF0FC000CF0FA000A))
\result[22]_i_2
(.I0(literal_2[15]),
.I1(\result_reg[23]_i_3_n_5 ),
.I2(opcode_2[2]),
.I3(opcode_2[1]),
.I4(data3[22]),
.I5(opcode_2[0]),
.O(\result[22]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair77" *)
LUT3 #(
.INIT(8'hB8))
\result[23]_i_1
(.I0(\result[23]_i_2_n_0 ),
.I1(\state_reg_n_0_[0] ),
.I2(load_data[23]),
.O(\result[23]_i_1_n_0 ));
LUT5 #(
.INIT(32'h111E22D2))
\result[23]_i_10
(.I0(register_a[22]),
.I1(operand_a1),
.I2(register_b[22]),
.I3(operand_b1),
.I4(result[22]),
.O(\result[23]_i_10_n_0 ));
LUT5 #(
.INIT(32'h111E22D2))
\result[23]_i_11
(.I0(register_a[21]),
.I1(operand_a1),
.I2(register_b[21]),
.I3(operand_b1),
.I4(result[21]),
.O(\result[23]_i_11_n_0 ));
LUT5 #(
.INIT(32'h111E22D2))
\result[23]_i_12
(.I0(register_a[20]),
.I1(operand_a1),
.I2(register_b[20]),
.I3(operand_b1),
.I4(result[20]),
.O(\result[23]_i_12_n_0 ));
LUT6 #(
.INIT(64'hF0FC000CF0FA000A))
\result[23]_i_2
(.I0(literal_2[15]),
.I1(\result_reg[23]_i_3_n_4 ),
.I2(opcode_2[2]),
.I3(opcode_2[1]),
.I4(data3[23]),
.I5(opcode_2[0]),
.O(\result[23]_i_2_n_0 ));
LUT5 #(
.INIT(32'hFFFB0008))
\result[23]_i_5
(.I0(result[23]),
.I1(write_enable),
.I2(\write_output[31]_i_3_n_0 ),
.I3(\write_output[31]_i_4_n_0 ),
.I4(register_a[23]),
.O(\result[23]_i_5_n_0 ));
LUT5 #(
.INIT(32'hFFFB0008))
\result[23]_i_6
(.I0(result[22]),
.I1(write_enable),
.I2(\write_output[31]_i_3_n_0 ),
.I3(\write_output[31]_i_4_n_0 ),
.I4(register_a[22]),
.O(\result[23]_i_6_n_0 ));
LUT5 #(
.INIT(32'hFFFB0008))
\result[23]_i_7
(.I0(result[21]),
.I1(write_enable),
.I2(\write_output[31]_i_3_n_0 ),
.I3(\write_output[31]_i_4_n_0 ),
.I4(register_a[21]),
.O(\result[23]_i_7_n_0 ));
LUT5 #(
.INIT(32'hFFFB0008))
\result[23]_i_8
(.I0(result[20]),
.I1(write_enable),
.I2(\write_output[31]_i_3_n_0 ),
.I3(\write_output[31]_i_4_n_0 ),
.I4(register_a[20]),
.O(\result[23]_i_8_n_0 ));
LUT5 #(
.INIT(32'h111E22D2))
\result[23]_i_9
(.I0(register_a[23]),
.I1(operand_a1),
.I2(register_b[23]),
.I3(operand_b1),
.I4(result[23]),
.O(\result[23]_i_9_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair77" *)
LUT3 #(
.INIT(8'hB8))
\result[24]_i_1
(.I0(\result[24]_i_2_n_0 ),
.I1(\state_reg_n_0_[0] ),
.I2(load_data[24]),
.O(\result[24]_i_1_n_0 ));
LUT6 #(
.INIT(64'hF0FC000CF0FA000A))
\result[24]_i_2
(.I0(literal_2[15]),
.I1(\result_reg[27]_i_3_n_7 ),
.I2(opcode_2[2]),
.I3(opcode_2[1]),
.I4(data3[24]),
.I5(opcode_2[0]),
.O(\result[24]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair78" *)
LUT3 #(
.INIT(8'hB8))
\result[25]_i_1
(.I0(\result[25]_i_2_n_0 ),
.I1(\state_reg_n_0_[0] ),
.I2(load_data[25]),
.O(\result[25]_i_1_n_0 ));
LUT6 #(
.INIT(64'hF0FC000CF0FA000A))
\result[25]_i_2
(.I0(literal_2[15]),
.I1(\result_reg[27]_i_3_n_6 ),
.I2(opcode_2[2]),
.I3(opcode_2[1]),
.I4(data3[25]),
.I5(opcode_2[0]),
.O(\result[25]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair78" *)
LUT3 #(
.INIT(8'hB8))
\result[26]_i_1
(.I0(\result[26]_i_2_n_0 ),
.I1(\state_reg_n_0_[0] ),
.I2(load_data[26]),
.O(\result[26]_i_1_n_0 ));
LUT6 #(
.INIT(64'hF0FC000CF0FA000A))
\result[26]_i_2
(.I0(literal_2[15]),
.I1(\result_reg[27]_i_3_n_5 ),
.I2(opcode_2[2]),
.I3(opcode_2[1]),
.I4(data3[26]),
.I5(opcode_2[0]),
.O(\result[26]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair80" *)
LUT3 #(
.INIT(8'hB8))
\result[27]_i_1
(.I0(\result[27]_i_2_n_0 ),
.I1(\state_reg_n_0_[0] ),
.I2(load_data[27]),
.O(\result[27]_i_1_n_0 ));
LUT5 #(
.INIT(32'h111E22D2))
\result[27]_i_10
(.I0(register_a[26]),
.I1(operand_a1),
.I2(register_b[26]),
.I3(operand_b1),
.I4(result[26]),
.O(\result[27]_i_10_n_0 ));
LUT5 #(
.INIT(32'h111E22D2))
\result[27]_i_11
(.I0(register_a[25]),
.I1(operand_a1),
.I2(register_b[25]),
.I3(operand_b1),
.I4(result[25]),
.O(\result[27]_i_11_n_0 ));
LUT5 #(
.INIT(32'h111E22D2))
\result[27]_i_12
(.I0(register_a[24]),
.I1(operand_a1),
.I2(register_b[24]),
.I3(operand_b1),
.I4(result[24]),
.O(\result[27]_i_12_n_0 ));
LUT6 #(
.INIT(64'hF0FC000CF0FA000A))
\result[27]_i_2
(.I0(literal_2[15]),
.I1(\result_reg[27]_i_3_n_4 ),
.I2(opcode_2[2]),
.I3(opcode_2[1]),
.I4(data3[27]),
.I5(opcode_2[0]),
.O(\result[27]_i_2_n_0 ));
LUT5 #(
.INIT(32'hFFFB0008))
\result[27]_i_5
(.I0(result[27]),
.I1(write_enable),
.I2(\write_output[31]_i_3_n_0 ),
.I3(\write_output[31]_i_4_n_0 ),
.I4(register_a[27]),
.O(\result[27]_i_5_n_0 ));
LUT5 #(
.INIT(32'hFFFB0008))
\result[27]_i_6
(.I0(result[26]),
.I1(write_enable),
.I2(\write_output[31]_i_3_n_0 ),
.I3(\write_output[31]_i_4_n_0 ),
.I4(register_a[26]),
.O(\result[27]_i_6_n_0 ));
LUT5 #(
.INIT(32'hFFFB0008))
\result[27]_i_7
(.I0(result[25]),
.I1(write_enable),
.I2(\write_output[31]_i_3_n_0 ),
.I3(\write_output[31]_i_4_n_0 ),
.I4(register_a[25]),
.O(\result[27]_i_7_n_0 ));
LUT5 #(
.INIT(32'hFFFB0008))
\result[27]_i_8
(.I0(result[24]),
.I1(write_enable),
.I2(\write_output[31]_i_3_n_0 ),
.I3(\write_output[31]_i_4_n_0 ),
.I4(register_a[24]),
.O(\result[27]_i_8_n_0 ));
LUT5 #(
.INIT(32'h111E22D2))
\result[27]_i_9
(.I0(register_a[27]),
.I1(operand_a1),
.I2(register_b[27]),
.I3(operand_b1),
.I4(result[27]),
.O(\result[27]_i_9_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair80" *)
LUT3 #(
.INIT(8'hB8))
\result[28]_i_1
(.I0(\result[28]_i_2_n_0 ),
.I1(\state_reg_n_0_[0] ),
.I2(load_data[28]),
.O(\result[28]_i_1_n_0 ));
LUT6 #(
.INIT(64'hF0FC000CF0FA000A))
\result[28]_i_2
(.I0(literal_2[15]),
.I1(\result_reg[31]_i_6_n_7 ),
.I2(opcode_2[2]),
.I3(opcode_2[1]),
.I4(data3[28]),
.I5(opcode_2[0]),
.O(\result[28]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair81" *)
LUT3 #(
.INIT(8'hB8))
\result[29]_i_1
(.I0(\result[29]_i_2_n_0 ),
.I1(\state_reg_n_0_[0] ),
.I2(load_data[29]),
.O(\result[29]_i_1_n_0 ));
LUT6 #(
.INIT(64'hF0FC000CF0FA000A))
\result[29]_i_2
(.I0(literal_2[15]),
.I1(\result_reg[31]_i_6_n_6 ),
.I2(opcode_2[2]),
.I3(opcode_2[1]),
.I4(data3[29]),
.I5(opcode_2[0]),
.O(\result[29]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair71" *)
LUT3 #(
.INIT(8'hB8))
\result[2]_i_1
(.I0(\result[2]_i_2_n_0 ),
.I1(\state_reg_n_0_[0] ),
.I2(load_data[2]),
.O(\result[2]_i_1_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\result[2]_i_2
(.I0(address_b_2[2]),
.I1(\result_reg[3]_i_3_n_5 ),
.I2(\result[31]_i_3_n_0 ),
.I3(data2[2]),
.I4(\result[16]_i_4_n_0 ),
.I5(data3[2]),
.O(\result[2]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair81" *)
LUT3 #(
.INIT(8'hB8))
\result[30]_i_1
(.I0(\result[30]_i_2_n_0 ),
.I1(\state_reg_n_0_[0] ),
.I2(load_data[30]),
.O(\result[30]_i_1_n_0 ));
LUT6 #(
.INIT(64'hF0FC000CF0FA000A))
\result[30]_i_2
(.I0(literal_2[15]),
.I1(\result_reg[31]_i_6_n_5 ),
.I2(opcode_2[2]),
.I3(opcode_2[1]),
.I4(data3[30]),
.I5(opcode_2[0]),
.O(\result[30]_i_2_n_0 ));
LUT6 #(
.INIT(64'h005400000000FF00))
\result[31]_i_1
(.I0(opcode_2[3]),
.I1(\result[31]_i_3_n_0 ),
.I2(\result[31]_i_4_n_0 ),
.I3(\state_reg_n_0_[2] ),
.I4(\state_reg_n_0_[1] ),
.I5(\state_reg_n_0_[0] ),
.O(\result[31]_i_1_n_0 ));
LUT5 #(
.INIT(32'hFFFB0008))
\result[31]_i_10
(.I0(result[29]),
.I1(write_enable),
.I2(\write_output[31]_i_3_n_0 ),
.I3(\write_output[31]_i_4_n_0 ),
.I4(register_a[29]),
.O(\result[31]_i_10_n_0 ));
LUT5 #(
.INIT(32'hFFFB0008))
\result[31]_i_11
(.I0(result[28]),
.I1(write_enable),
.I2(\write_output[31]_i_3_n_0 ),
.I3(\write_output[31]_i_4_n_0 ),
.I4(register_a[28]),
.O(\result[31]_i_11_n_0 ));
LUT5 #(
.INIT(32'h111E22D2))
\result[31]_i_12
(.I0(register_a[31]),
.I1(operand_a1),
.I2(register_b[31]),
.I3(operand_b1),
.I4(result[31]),
.O(\result[31]_i_12_n_0 ));
LUT5 #(
.INIT(32'h111E22D2))
\result[31]_i_13
(.I0(register_a[30]),
.I1(operand_a1),
.I2(register_b[30]),
.I3(operand_b1),
.I4(result[30]),
.O(\result[31]_i_13_n_0 ));
LUT5 #(
.INIT(32'h111E22D2))
\result[31]_i_14
(.I0(register_a[29]),
.I1(operand_a1),
.I2(register_b[29]),
.I3(operand_b1),
.I4(result[29]),
.O(\result[31]_i_14_n_0 ));
LUT5 #(
.INIT(32'h111E22D2))
\result[31]_i_15
(.I0(register_a[28]),
.I1(operand_a1),
.I2(register_b[28]),
.I3(operand_b1),
.I4(result[28]),
.O(\result[31]_i_15_n_0 ));
LUT3 #(
.INIT(8'hB8))
\result[31]_i_2
(.I0(\result[31]_i_5_n_0 ),
.I1(\state_reg_n_0_[0] ),
.I2(load_data[31]),
.O(\result[31]_i_2_n_0 ));
LUT2 #(
.INIT(4'h1))
\result[31]_i_3
(.I0(opcode_2[2]),
.I1(opcode_2[1]),
.O(\result[31]_i_3_n_0 ));
LUT2 #(
.INIT(4'h8))
\result[31]_i_4
(.I0(opcode_2[0]),
.I1(opcode_2[1]),
.O(\result[31]_i_4_n_0 ));
LUT6 #(
.INIT(64'hF0FC000CF0FA000A))
\result[31]_i_5
(.I0(literal_2[15]),
.I1(\result_reg[31]_i_6_n_4 ),
.I2(opcode_2[2]),
.I3(opcode_2[1]),
.I4(data3[31]),
.I5(opcode_2[0]),
.O(\result[31]_i_5_n_0 ));
LUT5 #(
.INIT(32'hFFFB0008))
\result[31]_i_8
(.I0(result[31]),
.I1(write_enable),
.I2(\write_output[31]_i_3_n_0 ),
.I3(\write_output[31]_i_4_n_0 ),
.I4(register_a[31]),
.O(\result[31]_i_8_n_0 ));
LUT5 #(
.INIT(32'hFFFB0008))
\result[31]_i_9
(.I0(result[30]),
.I1(write_enable),
.I2(\write_output[31]_i_3_n_0 ),
.I3(\write_output[31]_i_4_n_0 ),
.I4(register_a[30]),
.O(\result[31]_i_9_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair70" *)
LUT3 #(
.INIT(8'hB8))
\result[3]_i_1
(.I0(\result[3]_i_2_n_0 ),
.I1(\state_reg_n_0_[0] ),
.I2(load_data[3]),
.O(\result[3]_i_1_n_0 ));
LUT4 #(
.INIT(16'h1DE2))
\result[3]_i_10
(.I0(register_a[0]),
.I1(operand_a1),
.I2(result[0]),
.I3(address_b_2[0]),
.O(\result[3]_i_10_n_0 ));
LUT3 #(
.INIT(8'hB8))
\result[3]_i_11
(.I0(result[1]),
.I1(operand_a1),
.I2(register_a[1]),
.O(\result[3]_i_11_n_0 ));
LUT3 #(
.INIT(8'hB8))
\result[3]_i_12
(.I0(result[0]),
.I1(operand_a1),
.I2(register_a[0]),
.O(\result[3]_i_12_n_0 ));
LUT5 #(
.INIT(32'h111E22D2))
\result[3]_i_13
(.I0(register_a[3]),
.I1(operand_a1),
.I2(register_b[3]),
.I3(operand_b1),
.I4(result[3]),
.O(\result[3]_i_13_n_0 ));
LUT5 #(
.INIT(32'h111E22D2))
\result[3]_i_14
(.I0(register_a[2]),
.I1(operand_a1),
.I2(register_b[2]),
.I3(operand_b1),
.I4(result[2]),
.O(\result[3]_i_14_n_0 ));
LUT5 #(
.INIT(32'h111E22D2))
\result[3]_i_15
(.I0(register_a[1]),
.I1(operand_a1),
.I2(register_b[1]),
.I3(operand_b1),
.I4(result[1]),
.O(\result[3]_i_15_n_0 ));
LUT5 #(
.INIT(32'h111E22D2))
\result[3]_i_16
(.I0(register_a[0]),
.I1(operand_a1),
.I2(register_b[0]),
.I3(operand_b1),
.I4(result[0]),
.O(\result[3]_i_16_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\result[3]_i_2
(.I0(address_b_2[3]),
.I1(\result_reg[3]_i_3_n_4 ),
.I2(\result[31]_i_3_n_0 ),
.I3(data2[3]),
.I4(\result[16]_i_4_n_0 ),
.I5(data3[3]),
.O(\result[3]_i_2_n_0 ));
LUT3 #(
.INIT(8'hB8))
\result[3]_i_5
(.I0(result[1]),
.I1(operand_a1),
.I2(register_a[1]),
.O(\result[3]_i_5_n_0 ));
LUT3 #(
.INIT(8'hB8))
\result[3]_i_6
(.I0(result[0]),
.I1(operand_a1),
.I2(register_a[0]),
.O(\result[3]_i_6_n_0 ));
LUT4 #(
.INIT(16'h1DE2))
\result[3]_i_7
(.I0(register_a[3]),
.I1(operand_a1),
.I2(result[3]),
.I3(address_b_2[3]),
.O(\result[3]_i_7_n_0 ));
LUT4 #(
.INIT(16'h1DE2))
\result[3]_i_8
(.I0(register_a[2]),
.I1(operand_a1),
.I2(result[2]),
.I3(address_b_2[2]),
.O(\result[3]_i_8_n_0 ));
LUT4 #(
.INIT(16'h1DE2))
\result[3]_i_9
(.I0(register_a[1]),
.I1(operand_a1),
.I2(result[1]),
.I3(address_b_2[1]),
.O(\result[3]_i_9_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair68" *)
LUT3 #(
.INIT(8'hB8))
\result[4]_i_1
(.I0(\result[4]_i_2_n_0 ),
.I1(\state_reg_n_0_[0] ),
.I2(load_data[4]),
.O(\result[4]_i_1_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\result[4]_i_2
(.I0(literal_2[4]),
.I1(\result_reg[7]_i_3_n_7 ),
.I2(\result[31]_i_3_n_0 ),
.I3(data2[4]),
.I4(\result[16]_i_4_n_0 ),
.I5(data3[4]),
.O(\result[4]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair67" *)
LUT3 #(
.INIT(8'hB8))
\result[5]_i_1
(.I0(\result[5]_i_2_n_0 ),
.I1(\state_reg_n_0_[0] ),
.I2(load_data[5]),
.O(\result[5]_i_1_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\result[5]_i_2
(.I0(literal_2[5]),
.I1(\result_reg[7]_i_3_n_6 ),
.I2(\result[31]_i_3_n_0 ),
.I3(data2[5]),
.I4(\result[16]_i_4_n_0 ),
.I5(data3[5]),
.O(\result[5]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair72" *)
LUT3 #(
.INIT(8'hB8))
\result[6]_i_1
(.I0(\result[6]_i_2_n_0 ),
.I1(\state_reg_n_0_[0] ),
.I2(load_data[6]),
.O(\result[6]_i_1_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\result[6]_i_2
(.I0(literal_2[6]),
.I1(\result_reg[7]_i_3_n_5 ),
.I2(\result[31]_i_3_n_0 ),
.I3(data2[6]),
.I4(\result[16]_i_4_n_0 ),
.I5(data3[6]),
.O(\result[6]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair66" *)
LUT3 #(
.INIT(8'hB8))
\result[7]_i_1
(.I0(\result[7]_i_2_n_0 ),
.I1(\state_reg_n_0_[0] ),
.I2(load_data[7]),
.O(\result[7]_i_1_n_0 ));
LUT5 #(
.INIT(32'h111E22D2))
\result[7]_i_10
(.I0(register_a[6]),
.I1(operand_a1),
.I2(register_b[6]),
.I3(operand_b1),
.I4(result[6]),
.O(\result[7]_i_10_n_0 ));
LUT5 #(
.INIT(32'h111E22D2))
\result[7]_i_11
(.I0(register_a[5]),
.I1(operand_a1),
.I2(register_b[5]),
.I3(operand_b1),
.I4(result[5]),
.O(\result[7]_i_11_n_0 ));
LUT5 #(
.INIT(32'h111E22D2))
\result[7]_i_12
(.I0(register_a[4]),
.I1(operand_a1),
.I2(register_b[4]),
.I3(operand_b1),
.I4(result[4]),
.O(\result[7]_i_12_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\result[7]_i_2
(.I0(literal_2[7]),
.I1(\result_reg[7]_i_3_n_4 ),
.I2(\result[31]_i_3_n_0 ),
.I3(data2[7]),
.I4(\result[16]_i_4_n_0 ),
.I5(data3[7]),
.O(\result[7]_i_2_n_0 ));
LUT4 #(
.INIT(16'h1DE2))
\result[7]_i_5
(.I0(register_a[7]),
.I1(operand_a1),
.I2(result[7]),
.I3(literal_2[7]),
.O(\result[7]_i_5_n_0 ));
LUT4 #(
.INIT(16'h1DE2))
\result[7]_i_6
(.I0(register_a[6]),
.I1(operand_a1),
.I2(result[6]),
.I3(literal_2[6]),
.O(\result[7]_i_6_n_0 ));
LUT4 #(
.INIT(16'h1DE2))
\result[7]_i_7
(.I0(register_a[5]),
.I1(operand_a1),
.I2(result[5]),
.I3(literal_2[5]),
.O(\result[7]_i_7_n_0 ));
LUT4 #(
.INIT(16'h1DE2))
\result[7]_i_8
(.I0(register_a[4]),
.I1(operand_a1),
.I2(result[4]),
.I3(literal_2[4]),
.O(\result[7]_i_8_n_0 ));
LUT5 #(
.INIT(32'h111E22D2))
\result[7]_i_9
(.I0(register_a[7]),
.I1(operand_a1),
.I2(register_b[7]),
.I3(operand_b1),
.I4(result[7]),
.O(\result[7]_i_9_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair69" *)
LUT3 #(
.INIT(8'hB8))
\result[8]_i_1
(.I0(\result[8]_i_2_n_0 ),
.I1(\state_reg_n_0_[0] ),
.I2(load_data[8]),
.O(\result[8]_i_1_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\result[8]_i_2
(.I0(literal_2[15]),
.I1(\result_reg[11]_i_3_n_7 ),
.I2(\result[31]_i_3_n_0 ),
.I3(data2[8]),
.I4(\result[16]_i_4_n_0 ),
.I5(data3[8]),
.O(\result[8]_i_2_n_0 ));
LUT3 #(
.INIT(8'hB8))
\result[9]_i_1
(.I0(\result[9]_i_2_n_0 ),
.I1(\state_reg_n_0_[0] ),
.I2(load_data[9]),
.O(\result[9]_i_1_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\result[9]_i_2
(.I0(literal_2[15]),
.I1(\result_reg[11]_i_3_n_6 ),
.I2(\result[31]_i_3_n_0 ),
.I3(data2[9]),
.I4(\result[16]_i_4_n_0 ),
.I5(data3[9]),
.O(\result[9]_i_2_n_0 ));
FDRE \result_reg[0]
(.C(ETH_CLK_OBUF),
.CE(\result[31]_i_1_n_0 ),
.D(\result[0]_i_1_n_0 ),
.Q(result[0]),
.R(INTERNAL_RST_reg));
FDRE \result_reg[10]
(.C(ETH_CLK_OBUF),
.CE(\result[31]_i_1_n_0 ),
.D(\result[10]_i_1_n_0 ),
.Q(result[10]),
.R(INTERNAL_RST_reg));
FDRE \result_reg[11]
(.C(ETH_CLK_OBUF),
.CE(\result[31]_i_1_n_0 ),
.D(\result[11]_i_1_n_0 ),
.Q(result[11]),
.R(INTERNAL_RST_reg));
CARRY4 \result_reg[11]_i_3
(.CI(\result_reg[7]_i_3_n_0 ),
.CO({\result_reg[11]_i_3_n_0 ,\NLW_result_reg[11]_i_3_CO_UNCONNECTED [2:0]}),
.CYINIT(1'b0),
.DI({\write_output[11]_i_1_n_0 ,\write_output[10]_i_1_n_0 ,\write_output[9]_i_1_n_0 ,\write_output[8]_i_1_n_0 }),
.O({\result_reg[11]_i_3_n_4 ,\result_reg[11]_i_3_n_5 ,\result_reg[11]_i_3_n_6 ,\result_reg[11]_i_3_n_7 }),
.S({\result[11]_i_5_n_0 ,\result[11]_i_6_n_0 ,\result[11]_i_7_n_0 ,\result[11]_i_8_n_0 }));
CARRY4 \result_reg[11]_i_4
(.CI(\result_reg[7]_i_4_n_0 ),
.CO({\result_reg[11]_i_4_n_0 ,\NLW_result_reg[11]_i_4_CO_UNCONNECTED [2:0]}),
.CYINIT(1'b0),
.DI({\write_output[11]_i_1_n_0 ,\write_output[10]_i_1_n_0 ,\write_output[9]_i_1_n_0 ,\write_output[8]_i_1_n_0 }),
.O(data3[11:8]),
.S({\result[11]_i_9_n_0 ,\result[11]_i_10_n_0 ,\result[11]_i_11_n_0 ,\result[11]_i_12_n_0 }));
FDRE \result_reg[12]
(.C(ETH_CLK_OBUF),
.CE(\result[31]_i_1_n_0 ),
.D(\result[12]_i_1_n_0 ),
.Q(result[12]),
.R(INTERNAL_RST_reg));
CARRY4 \result_reg[12]_i_3
(.CI(\result_reg[8]_i_3_n_0 ),
.CO({\result_reg[12]_i_3_n_0 ,\NLW_result_reg[12]_i_3_CO_UNCONNECTED [2:0]}),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(data2[12:9]),
.S(program_counter_2[12:9]));
FDRE \result_reg[13]
(.C(ETH_CLK_OBUF),
.CE(\result[31]_i_1_n_0 ),
.D(\result[13]_i_1_n_0 ),
.Q(result[13]),
.R(INTERNAL_RST_reg));
FDRE \result_reg[14]
(.C(ETH_CLK_OBUF),
.CE(\result[31]_i_1_n_0 ),
.D(\result[14]_i_1_n_0 ),
.Q(result[14]),
.R(INTERNAL_RST_reg));
FDRE \result_reg[15]
(.C(ETH_CLK_OBUF),
.CE(\result[31]_i_1_n_0 ),
.D(\result[15]_i_1_n_0 ),
.Q(result[15]),
.R(INTERNAL_RST_reg));
CARRY4 \result_reg[15]_i_3
(.CI(\result_reg[11]_i_3_n_0 ),
.CO({\result_reg[15]_i_3_n_0 ,\NLW_result_reg[15]_i_3_CO_UNCONNECTED [2:0]}),
.CYINIT(1'b0),
.DI({\write_output[15]_i_1_n_0 ,\write_output[14]_i_1_n_0 ,\write_output[13]_i_1_n_0 ,\write_output[12]_i_1_n_0 }),
.O({\result_reg[15]_i_3_n_4 ,\result_reg[15]_i_3_n_5 ,\result_reg[15]_i_3_n_6 ,\result_reg[15]_i_3_n_7 }),
.S({\result[15]_i_5_n_0 ,\result[15]_i_6_n_0 ,\result[15]_i_7_n_0 ,\result[15]_i_8_n_0 }));
CARRY4 \result_reg[15]_i_4
(.CI(\result_reg[11]_i_4_n_0 ),
.CO({\result_reg[15]_i_4_n_0 ,\NLW_result_reg[15]_i_4_CO_UNCONNECTED [2:0]}),
.CYINIT(1'b0),
.DI({\write_output[15]_i_1_n_0 ,\write_output[14]_i_1_n_0 ,\write_output[13]_i_1_n_0 ,\write_output[12]_i_1_n_0 }),
.O(data3[15:12]),
.S({\result[15]_i_9_n_0 ,\result[15]_i_10_n_0 ,\result[15]_i_11_n_0 ,\result[15]_i_12_n_0 }));
FDRE \result_reg[16]
(.C(ETH_CLK_OBUF),
.CE(\result[31]_i_1_n_0 ),
.D(\result[16]_i_1_n_0 ),
.Q(result[16]),
.R(INTERNAL_RST_reg));
CARRY4 \result_reg[16]_i_3
(.CI(\result_reg[12]_i_3_n_0 ),
.CO({data2[16],\NLW_result_reg[16]_i_3_CO_UNCONNECTED [2:0]}),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O({\NLW_result_reg[16]_i_3_O_UNCONNECTED [3],data2[15:13]}),
.S({1'b1,program_counter_2[15:13]}));
FDRE \result_reg[17]
(.C(ETH_CLK_OBUF),
.CE(\result[31]_i_1_n_0 ),
.D(\result[17]_i_1_n_0 ),
.Q(result[17]),
.R(INTERNAL_RST_reg));
FDRE \result_reg[18]
(.C(ETH_CLK_OBUF),
.CE(\result[31]_i_1_n_0 ),
.D(\result[18]_i_1_n_0 ),
.Q(result[18]),
.R(INTERNAL_RST_reg));
FDRE \result_reg[19]
(.C(ETH_CLK_OBUF),
.CE(\result[31]_i_1_n_0 ),
.D(\result[19]_i_1_n_0 ),
.Q(result[19]),
.R(INTERNAL_RST_reg));
CARRY4 \result_reg[19]_i_3
(.CI(\result_reg[15]_i_3_n_0 ),
.CO({\result_reg[19]_i_3_n_0 ,\NLW_result_reg[19]_i_3_CO_UNCONNECTED [2:0]}),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O({\result_reg[19]_i_3_n_4 ,\result_reg[19]_i_3_n_5 ,\result_reg[19]_i_3_n_6 ,\result_reg[19]_i_3_n_7 }),
.S({\result[19]_i_5_n_0 ,\result[19]_i_6_n_0 ,\result[19]_i_7_n_0 ,\result[19]_i_8_n_0 }));
CARRY4 \result_reg[19]_i_4
(.CI(\result_reg[15]_i_4_n_0 ),
.CO({\result_reg[19]_i_4_n_0 ,\NLW_result_reg[19]_i_4_CO_UNCONNECTED [2:0]}),
.CYINIT(1'b0),
.DI({\write_output[19]_i_1_n_0 ,\write_output[18]_i_1_n_0 ,\write_output[17]_i_1_n_0 ,\write_output[16]_i_1_n_0 }),
.O(data3[19:16]),
.S({\result[19]_i_9_n_0 ,\result[19]_i_10_n_0 ,\result[19]_i_11_n_0 ,\result[19]_i_12_n_0 }));
FDRE \result_reg[1]
(.C(ETH_CLK_OBUF),
.CE(\result[31]_i_1_n_0 ),
.D(\result[1]_i_1_n_0 ),
.Q(result[1]),
.R(INTERNAL_RST_reg));
FDRE \result_reg[20]
(.C(ETH_CLK_OBUF),
.CE(\result[31]_i_1_n_0 ),
.D(\result[20]_i_1_n_0 ),
.Q(result[20]),
.R(INTERNAL_RST_reg));
FDRE \result_reg[21]
(.C(ETH_CLK_OBUF),
.CE(\result[31]_i_1_n_0 ),
.D(\result[21]_i_1_n_0 ),
.Q(result[21]),
.R(INTERNAL_RST_reg));
FDRE \result_reg[22]
(.C(ETH_CLK_OBUF),
.CE(\result[31]_i_1_n_0 ),
.D(\result[22]_i_1_n_0 ),
.Q(result[22]),
.R(INTERNAL_RST_reg));
FDRE \result_reg[23]
(.C(ETH_CLK_OBUF),
.CE(\result[31]_i_1_n_0 ),
.D(\result[23]_i_1_n_0 ),
.Q(result[23]),
.R(INTERNAL_RST_reg));
CARRY4 \result_reg[23]_i_3
(.CI(\result_reg[19]_i_3_n_0 ),
.CO({\result_reg[23]_i_3_n_0 ,\NLW_result_reg[23]_i_3_CO_UNCONNECTED [2:0]}),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O({\result_reg[23]_i_3_n_4 ,\result_reg[23]_i_3_n_5 ,\result_reg[23]_i_3_n_6 ,\result_reg[23]_i_3_n_7 }),
.S({\result[23]_i_5_n_0 ,\result[23]_i_6_n_0 ,\result[23]_i_7_n_0 ,\result[23]_i_8_n_0 }));
CARRY4 \result_reg[23]_i_4
(.CI(\result_reg[19]_i_4_n_0 ),
.CO({\result_reg[23]_i_4_n_0 ,\NLW_result_reg[23]_i_4_CO_UNCONNECTED [2:0]}),
.CYINIT(1'b0),
.DI({\write_output[23]_i_1_n_0 ,\write_output[22]_i_1_n_0 ,\write_output[21]_i_1_n_0 ,\write_output[20]_i_1_n_0 }),
.O(data3[23:20]),
.S({\result[23]_i_9_n_0 ,\result[23]_i_10_n_0 ,\result[23]_i_11_n_0 ,\result[23]_i_12_n_0 }));
FDRE \result_reg[24]
(.C(ETH_CLK_OBUF),
.CE(\result[31]_i_1_n_0 ),
.D(\result[24]_i_1_n_0 ),
.Q(result[24]),
.R(INTERNAL_RST_reg));
FDRE \result_reg[25]
(.C(ETH_CLK_OBUF),
.CE(\result[31]_i_1_n_0 ),
.D(\result[25]_i_1_n_0 ),
.Q(result[25]),
.R(INTERNAL_RST_reg));
FDRE \result_reg[26]
(.C(ETH_CLK_OBUF),
.CE(\result[31]_i_1_n_0 ),
.D(\result[26]_i_1_n_0 ),
.Q(result[26]),
.R(INTERNAL_RST_reg));
FDRE \result_reg[27]
(.C(ETH_CLK_OBUF),
.CE(\result[31]_i_1_n_0 ),
.D(\result[27]_i_1_n_0 ),
.Q(result[27]),
.R(INTERNAL_RST_reg));
CARRY4 \result_reg[27]_i_3
(.CI(\result_reg[23]_i_3_n_0 ),
.CO({\result_reg[27]_i_3_n_0 ,\NLW_result_reg[27]_i_3_CO_UNCONNECTED [2:0]}),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O({\result_reg[27]_i_3_n_4 ,\result_reg[27]_i_3_n_5 ,\result_reg[27]_i_3_n_6 ,\result_reg[27]_i_3_n_7 }),
.S({\result[27]_i_5_n_0 ,\result[27]_i_6_n_0 ,\result[27]_i_7_n_0 ,\result[27]_i_8_n_0 }));
CARRY4 \result_reg[27]_i_4
(.CI(\result_reg[23]_i_4_n_0 ),
.CO({\result_reg[27]_i_4_n_0 ,\NLW_result_reg[27]_i_4_CO_UNCONNECTED [2:0]}),
.CYINIT(1'b0),
.DI({\write_output[27]_i_1_n_0 ,\write_output[26]_i_1_n_0 ,\write_output[25]_i_1_n_0 ,\write_output[24]_i_1_n_0 }),
.O(data3[27:24]),
.S({\result[27]_i_9_n_0 ,\result[27]_i_10_n_0 ,\result[27]_i_11_n_0 ,\result[27]_i_12_n_0 }));
FDRE \result_reg[28]
(.C(ETH_CLK_OBUF),
.CE(\result[31]_i_1_n_0 ),
.D(\result[28]_i_1_n_0 ),
.Q(result[28]),
.R(INTERNAL_RST_reg));
FDRE \result_reg[29]
(.C(ETH_CLK_OBUF),
.CE(\result[31]_i_1_n_0 ),
.D(\result[29]_i_1_n_0 ),
.Q(result[29]),
.R(INTERNAL_RST_reg));
FDRE \result_reg[2]
(.C(ETH_CLK_OBUF),
.CE(\result[31]_i_1_n_0 ),
.D(\result[2]_i_1_n_0 ),
.Q(result[2]),
.R(INTERNAL_RST_reg));
FDRE \result_reg[30]
(.C(ETH_CLK_OBUF),
.CE(\result[31]_i_1_n_0 ),
.D(\result[30]_i_1_n_0 ),
.Q(result[30]),
.R(INTERNAL_RST_reg));
FDRE \result_reg[31]
(.C(ETH_CLK_OBUF),
.CE(\result[31]_i_1_n_0 ),
.D(\result[31]_i_2_n_0 ),
.Q(result[31]),
.R(INTERNAL_RST_reg));
CARRY4 \result_reg[31]_i_6
(.CI(\result_reg[27]_i_3_n_0 ),
.CO(\NLW_result_reg[31]_i_6_CO_UNCONNECTED [3:0]),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O({\result_reg[31]_i_6_n_4 ,\result_reg[31]_i_6_n_5 ,\result_reg[31]_i_6_n_6 ,\result_reg[31]_i_6_n_7 }),
.S({\result[31]_i_8_n_0 ,\result[31]_i_9_n_0 ,\result[31]_i_10_n_0 ,\result[31]_i_11_n_0 }));
CARRY4 \result_reg[31]_i_7
(.CI(\result_reg[27]_i_4_n_0 ),
.CO(\NLW_result_reg[31]_i_7_CO_UNCONNECTED [3:0]),
.CYINIT(1'b0),
.DI({1'b0,\write_output[30]_i_1_n_0 ,\write_output[29]_i_1_n_0 ,\write_output[28]_i_1_n_0 }),
.O(data3[31:28]),
.S({\result[31]_i_12_n_0 ,\result[31]_i_13_n_0 ,\result[31]_i_14_n_0 ,\result[31]_i_15_n_0 }));
FDRE \result_reg[3]
(.C(ETH_CLK_OBUF),
.CE(\result[31]_i_1_n_0 ),
.D(\result[3]_i_1_n_0 ),
.Q(result[3]),
.R(INTERNAL_RST_reg));
CARRY4 \result_reg[3]_i_3
(.CI(1'b0),
.CO({\result_reg[3]_i_3_n_0 ,\NLW_result_reg[3]_i_3_CO_UNCONNECTED [2:0]}),
.CYINIT(1'b0),
.DI({\write_output[3]_i_1_n_0 ,\write_output[2]_i_1_n_0 ,\result[3]_i_5_n_0 ,\result[3]_i_6_n_0 }),
.O({\result_reg[3]_i_3_n_4 ,\result_reg[3]_i_3_n_5 ,\result_reg[3]_i_3_n_6 ,\result_reg[3]_i_3_n_7 }),
.S({\result[3]_i_7_n_0 ,\result[3]_i_8_n_0 ,\result[3]_i_9_n_0 ,\result[3]_i_10_n_0 }));
CARRY4 \result_reg[3]_i_4
(.CI(1'b0),
.CO({\result_reg[3]_i_4_n_0 ,\NLW_result_reg[3]_i_4_CO_UNCONNECTED [2:0]}),
.CYINIT(1'b0),
.DI({\write_output[3]_i_1_n_0 ,\write_output[2]_i_1_n_0 ,\result[3]_i_11_n_0 ,\result[3]_i_12_n_0 }),
.O(data3[3:0]),
.S({\result[3]_i_13_n_0 ,\result[3]_i_14_n_0 ,\result[3]_i_15_n_0 ,\result[3]_i_16_n_0 }));
FDRE \result_reg[4]
(.C(ETH_CLK_OBUF),
.CE(\result[31]_i_1_n_0 ),
.D(\result[4]_i_1_n_0 ),
.Q(result[4]),
.R(INTERNAL_RST_reg));
CARRY4 \result_reg[4]_i_3
(.CI(1'b0),
.CO({\result_reg[4]_i_3_n_0 ,\NLW_result_reg[4]_i_3_CO_UNCONNECTED [2:0]}),
.CYINIT(program_counter_2[0]),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(data2[4:1]),
.S(program_counter_2[4:1]));
FDRE \result_reg[5]
(.C(ETH_CLK_OBUF),
.CE(\result[31]_i_1_n_0 ),
.D(\result[5]_i_1_n_0 ),
.Q(result[5]),
.R(INTERNAL_RST_reg));
FDRE \result_reg[6]
(.C(ETH_CLK_OBUF),
.CE(\result[31]_i_1_n_0 ),
.D(\result[6]_i_1_n_0 ),
.Q(result[6]),
.R(INTERNAL_RST_reg));
FDRE \result_reg[7]
(.C(ETH_CLK_OBUF),
.CE(\result[31]_i_1_n_0 ),
.D(\result[7]_i_1_n_0 ),
.Q(result[7]),
.R(INTERNAL_RST_reg));
CARRY4 \result_reg[7]_i_3
(.CI(\result_reg[3]_i_3_n_0 ),
.CO({\result_reg[7]_i_3_n_0 ,\NLW_result_reg[7]_i_3_CO_UNCONNECTED [2:0]}),
.CYINIT(1'b0),
.DI({\write_output[7]_i_1_n_0 ,\write_output[6]_i_1_n_0 ,\write_output[5]_i_1_n_0 ,\write_output[4]_i_1_n_0 }),
.O({\result_reg[7]_i_3_n_4 ,\result_reg[7]_i_3_n_5 ,\result_reg[7]_i_3_n_6 ,\result_reg[7]_i_3_n_7 }),
.S({\result[7]_i_5_n_0 ,\result[7]_i_6_n_0 ,\result[7]_i_7_n_0 ,\result[7]_i_8_n_0 }));
CARRY4 \result_reg[7]_i_4
(.CI(\result_reg[3]_i_4_n_0 ),
.CO({\result_reg[7]_i_4_n_0 ,\NLW_result_reg[7]_i_4_CO_UNCONNECTED [2:0]}),
.CYINIT(1'b0),
.DI({\write_output[7]_i_1_n_0 ,\write_output[6]_i_1_n_0 ,\write_output[5]_i_1_n_0 ,\write_output[4]_i_1_n_0 }),
.O(data3[7:4]),
.S({\result[7]_i_9_n_0 ,\result[7]_i_10_n_0 ,\result[7]_i_11_n_0 ,\result[7]_i_12_n_0 }));
FDRE \result_reg[8]
(.C(ETH_CLK_OBUF),
.CE(\result[31]_i_1_n_0 ),
.D(\result[8]_i_1_n_0 ),
.Q(result[8]),
.R(INTERNAL_RST_reg));
CARRY4 \result_reg[8]_i_3
(.CI(\result_reg[4]_i_3_n_0 ),
.CO({\result_reg[8]_i_3_n_0 ,\NLW_result_reg[8]_i_3_CO_UNCONNECTED [2:0]}),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(data2[8:5]),
.S(program_counter_2[8:5]));
FDRE \result_reg[9]
(.C(ETH_CLK_OBUF),
.CE(\result[31]_i_1_n_0 ),
.D(\result[9]_i_1_n_0 ),
.Q(result[9]),
.R(INTERNAL_RST_reg));
LUT3 #(
.INIT(8'h80))
\s_output_rs232_tx[7]_i_1
(.I0(\state_reg_n_0_[1] ),
.I1(\state_reg_n_0_[0] ),
.I2(\s_output_rs232_tx[7]_i_2_n_0 ),
.O(\s_output_rs232_tx[7]_i_1_n_0 ));
LUT6 #(
.INIT(64'h8000000000000000))
\s_output_rs232_tx[7]_i_2
(.I0(\s_output_rs232_tx[7]_i_3_n_0 ),
.I1(\s_output_rs232_tx[7]_i_4_n_0 ),
.I2(\s_output_rs232_tx[7]_i_5_n_0 ),
.I3(\s_output_rs232_tx[7]_i_6_n_0 ),
.I4(\s_output_rs232_tx[7]_i_7_n_0 ),
.I5(\s_output_rs232_tx[7]_i_8_n_0 ),
.O(\s_output_rs232_tx[7]_i_2_n_0 ));
LUT6 #(
.INIT(64'h0000000000000001))
\s_output_rs232_tx[7]_i_3
(.I0(write_output[15]),
.I1(write_output[16]),
.I2(write_output[10]),
.I3(write_output[25]),
.I4(write_output[13]),
.I5(write_output[30]),
.O(\s_output_rs232_tx[7]_i_3_n_0 ));
LUT3 #(
.INIT(8'h01))
\s_output_rs232_tx[7]_i_4
(.I0(write_output[14]),
.I1(write_output[26]),
.I2(write_output[20]),
.O(\s_output_rs232_tx[7]_i_4_n_0 ));
LUT6 #(
.INIT(64'h0000000000000001))
\s_output_rs232_tx[7]_i_5
(.I0(write_output[6]),
.I1(write_output[31]),
.I2(write_output[28]),
.I3(write_output[7]),
.I4(write_output[12]),
.I5(write_output[19]),
.O(\s_output_rs232_tx[7]_i_5_n_0 ));
LUT6 #(
.INIT(64'h0000000000000010))
\s_output_rs232_tx[7]_i_6
(.I0(write_output[1]),
.I1(write_output[11]),
.I2(\state_reg_n_0_[2] ),
.I3(write_output[24]),
.I4(write_output[21]),
.I5(write_output[3]),
.O(\s_output_rs232_tx[7]_i_6_n_0 ));
LUT6 #(
.INIT(64'h0000000000000001))
\s_output_rs232_tx[7]_i_7
(.I0(write_output[22]),
.I1(write_output[5]),
.I2(write_output[17]),
.I3(write_output[18]),
.I4(write_output[0]),
.I5(write_output[29]),
.O(\s_output_rs232_tx[7]_i_7_n_0 ));
LUT6 #(
.INIT(64'h0000000000000001))
\s_output_rs232_tx[7]_i_8
(.I0(write_output[9]),
.I1(write_output[4]),
.I2(write_output[27]),
.I3(write_output[8]),
.I4(write_output[23]),
.I5(write_output[2]),
.O(\s_output_rs232_tx[7]_i_8_n_0 ));
FDRE \s_output_rs232_tx_reg[0]
(.C(ETH_CLK_OBUF),
.CE(\s_output_rs232_tx[7]_i_1_n_0 ),
.D(write_value[0]),
.Q(output_rs232_tx[0]),
.R(1'b0));
FDRE \s_output_rs232_tx_reg[1]
(.C(ETH_CLK_OBUF),
.CE(\s_output_rs232_tx[7]_i_1_n_0 ),
.D(write_value[1]),
.Q(output_rs232_tx[1]),
.R(1'b0));
FDRE \s_output_rs232_tx_reg[2]
(.C(ETH_CLK_OBUF),
.CE(\s_output_rs232_tx[7]_i_1_n_0 ),
.D(write_value[2]),
.Q(output_rs232_tx[2]),
.R(1'b0));
FDRE \s_output_rs232_tx_reg[3]
(.C(ETH_CLK_OBUF),
.CE(\s_output_rs232_tx[7]_i_1_n_0 ),
.D(write_value[3]),
.Q(output_rs232_tx[3]),
.R(1'b0));
FDRE \s_output_rs232_tx_reg[4]
(.C(ETH_CLK_OBUF),
.CE(\s_output_rs232_tx[7]_i_1_n_0 ),
.D(write_value[4]),
.Q(output_rs232_tx[4]),
.R(1'b0));
FDRE \s_output_rs232_tx_reg[5]
(.C(ETH_CLK_OBUF),
.CE(\s_output_rs232_tx[7]_i_1_n_0 ),
.D(write_value[5]),
.Q(output_rs232_tx[5]),
.R(1'b0));
FDRE \s_output_rs232_tx_reg[6]
(.C(ETH_CLK_OBUF),
.CE(\s_output_rs232_tx[7]_i_1_n_0 ),
.D(write_value[6]),
.Q(output_rs232_tx[6]),
.R(1'b0));
FDRE \s_output_rs232_tx_reg[7]
(.C(ETH_CLK_OBUF),
.CE(\s_output_rs232_tx[7]_i_1_n_0 ),
.D(write_value[7]),
.Q(output_rs232_tx[7]),
.R(1'b0));
LUT5 #(
.INIT(32'h7FFF8080))
\s_output_rs232_tx_stb[0]_i_1
(.I0(\state_reg_n_0_[1] ),
.I1(\state_reg_n_0_[0] ),
.I2(\s_output_rs232_tx[7]_i_2_n_0 ),
.I3(IN1_ACK),
.I4(IN1_STB),
.O(\s_output_rs232_tx_stb[0]_i_1_n_0 ));
FDRE \s_output_rs232_tx_stb_reg[0]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(\s_output_rs232_tx_stb[0]_i_1_n_0 ),
.Q(IN1_STB),
.R(INTERNAL_RST_reg));
LUT6 #(
.INIT(64'hFF8AFFFFFFAA0000))
\state[0]_i_1
(.I0(\state_reg_n_0_[1] ),
.I1(opcode_2[1]),
.I2(opcode_2[2]),
.I3(\state_reg_n_0_[2] ),
.I4(\state[2]_i_2_n_0 ),
.I5(\state_reg_n_0_[0] ),
.O(\state[0]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFF8FFFFFFFFF0000))
\state[1]_i_1
(.I0(\result[31]_i_3_n_0 ),
.I1(opcode_2[0]),
.I2(\state_reg_n_0_[0] ),
.I3(\state_reg_n_0_[2] ),
.I4(\state[2]_i_2_n_0 ),
.I5(\state_reg_n_0_[1] ),
.O(\state[1]_i_1_n_0 ));
LUT6 #(
.INIT(64'h0000FFFF08000000))
\state[2]_i_1
(.I0(\state_reg_n_0_[0] ),
.I1(\state_reg_n_0_[1] ),
.I2(opcode_2[1]),
.I3(opcode_2[0]),
.I4(\state[2]_i_2_n_0 ),
.I5(\state_reg_n_0_[2] ),
.O(\state[2]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFFFFFFE))
\state[2]_i_10
(.I0(\write_output[27]_i_1_n_0 ),
.I1(\write_output[26]_i_1_n_0 ),
.I2(\write_output[30]_i_1_n_0 ),
.I3(\write_output[31]_i_2_n_0 ),
.I4(\write_output[28]_i_1_n_0 ),
.I5(\write_output[29]_i_1_n_0 ),
.O(\state[2]_i_10_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFFFFFFE))
\state[2]_i_11
(.I0(\write_output[9]_i_1_n_0 ),
.I1(\write_output[8]_i_1_n_0 ),
.I2(\write_output[12]_i_1_n_0 ),
.I3(\write_output[13]_i_1_n_0 ),
.I4(\write_output[10]_i_1_n_0 ),
.I5(\write_output[11]_i_1_n_0 ),
.O(\state[2]_i_11_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFFFFFFE))
\state[2]_i_12
(.I0(\write_output[15]_i_1_n_0 ),
.I1(\write_output[14]_i_1_n_0 ),
.I2(\write_output[18]_i_1_n_0 ),
.I3(\write_output[19]_i_1_n_0 ),
.I4(\write_output[16]_i_1_n_0 ),
.I5(\write_output[17]_i_1_n_0 ),
.O(\state[2]_i_12_n_0 ));
LUT6 #(
.INIT(64'hFFFFBBABAAAAAAAA))
\state[2]_i_2
(.I0(\state[2]_i_3_n_0 ),
.I1(\state[2]_i_4_n_0 ),
.I2(\state[2]_i_5_n_0 ),
.I3(opcode_2[1]),
.I4(\state[2]_i_6_n_0 ),
.I5(\state[2]_i_7_n_0 ),
.O(\state[2]_i_2_n_0 ));
LUT6 #(
.INIT(64'h8080FFFF00FFFF00))
\state[2]_i_3
(.I0(\s_output_rs232_tx[7]_i_2_n_0 ),
.I1(IN1_STB),
.I2(IN1_ACK),
.I3(\state_reg_n_0_[2] ),
.I4(\state_reg_n_0_[1] ),
.I5(\state_reg_n_0_[0] ),
.O(\state[2]_i_3_n_0 ));
LUT3 #(
.INIT(8'hEF))
\state[2]_i_4
(.I0(opcode_2[0]),
.I1(opcode_2[2]),
.I2(opcode_2[3]),
.O(\state[2]_i_4_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFFFFFFE))
\state[2]_i_5
(.I0(\program_counter_rep[7]_i_15_n_0 ),
.I1(\state[2]_i_8_n_0 ),
.I2(\state[2]_i_9_n_0 ),
.I3(\state[2]_i_10_n_0 ),
.I4(\state[2]_i_11_n_0 ),
.I5(\state[2]_i_12_n_0 ),
.O(\state[2]_i_5_n_0 ));
LUT4 #(
.INIT(16'h046A))
\state[2]_i_6
(.I0(opcode_2[2]),
.I1(opcode_2[0]),
.I2(opcode_2[1]),
.I3(opcode_2[3]),
.O(\state[2]_i_6_n_0 ));
LUT2 #(
.INIT(4'h2))
\state[2]_i_7
(.I0(\state_reg_n_0_[0] ),
.I1(\state_reg_n_0_[2] ),
.O(\state[2]_i_7_n_0 ));
LUT5 #(
.INIT(32'hFFFACCFA))
\state[2]_i_8
(.I0(register_a[0]),
.I1(result[0]),
.I2(register_a[1]),
.I3(operand_a1),
.I4(result[1]),
.O(\state[2]_i_8_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFFFFFFE))
\state[2]_i_9
(.I0(\write_output[21]_i_1_n_0 ),
.I1(\write_output[20]_i_1_n_0 ),
.I2(\write_output[24]_i_1_n_0 ),
.I3(\write_output[25]_i_1_n_0 ),
.I4(\write_output[22]_i_1_n_0 ),
.I5(\write_output[23]_i_1_n_0 ),
.O(\state[2]_i_9_n_0 ));
FDSE \state_reg[0]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(\state[0]_i_1_n_0 ),
.Q(\state_reg_n_0_[0] ),
.S(INTERNAL_RST_reg));
FDRE \state_reg[1]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(\state[1]_i_1_n_0 ),
.Q(\state_reg_n_0_[1] ),
.R(INTERNAL_RST_reg));
FDRE \state_reg[2]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(\state[2]_i_1_n_0 ),
.Q(\state_reg_n_0_[2] ),
.R(INTERNAL_RST_reg));
FDRE write_enable_reg
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(\result[31]_i_1_n_0 ),
.Q(write_enable),
.R(1'b0));
LUT3 #(
.INIT(8'hB8))
\write_output[0]_i_1
(.I0(result[0]),
.I1(operand_a1),
.I2(register_a[0]),
.O(\write_output[0]_i_1_n_0 ));
LUT5 #(
.INIT(32'hFFFB0008))
\write_output[10]_i_1
(.I0(result[10]),
.I1(write_enable),
.I2(\write_output[31]_i_3_n_0 ),
.I3(\write_output[31]_i_4_n_0 ),
.I4(register_a[10]),
.O(\write_output[10]_i_1_n_0 ));
LUT5 #(
.INIT(32'hFFFB0008))
\write_output[11]_i_1
(.I0(result[11]),
.I1(write_enable),
.I2(\write_output[31]_i_3_n_0 ),
.I3(\write_output[31]_i_4_n_0 ),
.I4(register_a[11]),
.O(\write_output[11]_i_1_n_0 ));
LUT5 #(
.INIT(32'hFFFB0008))
\write_output[12]_i_1
(.I0(result[12]),
.I1(write_enable),
.I2(\write_output[31]_i_3_n_0 ),
.I3(\write_output[31]_i_4_n_0 ),
.I4(register_a[12]),
.O(\write_output[12]_i_1_n_0 ));
LUT5 #(
.INIT(32'hFFFB0008))
\write_output[13]_i_1
(.I0(result[13]),
.I1(write_enable),
.I2(\write_output[31]_i_3_n_0 ),
.I3(\write_output[31]_i_4_n_0 ),
.I4(register_a[13]),
.O(\write_output[13]_i_1_n_0 ));
LUT5 #(
.INIT(32'hFFFB0008))
\write_output[14]_i_1
(.I0(result[14]),
.I1(write_enable),
.I2(\write_output[31]_i_3_n_0 ),
.I3(\write_output[31]_i_4_n_0 ),
.I4(register_a[14]),
.O(\write_output[14]_i_1_n_0 ));
LUT5 #(
.INIT(32'hFFFB0008))
\write_output[15]_i_1
(.I0(result[15]),
.I1(write_enable),
.I2(\write_output[31]_i_3_n_0 ),
.I3(\write_output[31]_i_4_n_0 ),
.I4(register_a[15]),
.O(\write_output[15]_i_1_n_0 ));
LUT5 #(
.INIT(32'hFFFB0008))
\write_output[16]_i_1
(.I0(result[16]),
.I1(write_enable),
.I2(\write_output[31]_i_3_n_0 ),
.I3(\write_output[31]_i_4_n_0 ),
.I4(register_a[16]),
.O(\write_output[16]_i_1_n_0 ));
LUT5 #(
.INIT(32'hFFFB0008))
\write_output[17]_i_1
(.I0(result[17]),
.I1(write_enable),
.I2(\write_output[31]_i_3_n_0 ),
.I3(\write_output[31]_i_4_n_0 ),
.I4(register_a[17]),
.O(\write_output[17]_i_1_n_0 ));
LUT5 #(
.INIT(32'hFFFB0008))
\write_output[18]_i_1
(.I0(result[18]),
.I1(write_enable),
.I2(\write_output[31]_i_3_n_0 ),
.I3(\write_output[31]_i_4_n_0 ),
.I4(register_a[18]),
.O(\write_output[18]_i_1_n_0 ));
LUT5 #(
.INIT(32'hFFFB0008))
\write_output[19]_i_1
(.I0(result[19]),
.I1(write_enable),
.I2(\write_output[31]_i_3_n_0 ),
.I3(\write_output[31]_i_4_n_0 ),
.I4(register_a[19]),
.O(\write_output[19]_i_1_n_0 ));
LUT3 #(
.INIT(8'hB8))
\write_output[1]_i_1
(.I0(result[1]),
.I1(operand_a1),
.I2(register_a[1]),
.O(\write_output[1]_i_1_n_0 ));
LUT6 #(
.INIT(64'h2002000000002002))
\write_output[1]_i_2
(.I0(write_enable),
.I1(\write_output[31]_i_3_n_0 ),
.I2(address_a_2[0]),
.I3(address_z_3[0]),
.I4(address_a_2[3]),
.I5(address_z_3[3]),
.O(operand_a1));
LUT5 #(
.INIT(32'hFFFB0008))
\write_output[20]_i_1
(.I0(result[20]),
.I1(write_enable),
.I2(\write_output[31]_i_3_n_0 ),
.I3(\write_output[31]_i_4_n_0 ),
.I4(register_a[20]),
.O(\write_output[20]_i_1_n_0 ));
LUT5 #(
.INIT(32'hFFFB0008))
\write_output[21]_i_1
(.I0(result[21]),
.I1(write_enable),
.I2(\write_output[31]_i_3_n_0 ),
.I3(\write_output[31]_i_4_n_0 ),
.I4(register_a[21]),
.O(\write_output[21]_i_1_n_0 ));
LUT5 #(
.INIT(32'hFFFB0008))
\write_output[22]_i_1
(.I0(result[22]),
.I1(write_enable),
.I2(\write_output[31]_i_3_n_0 ),
.I3(\write_output[31]_i_4_n_0 ),
.I4(register_a[22]),
.O(\write_output[22]_i_1_n_0 ));
LUT5 #(
.INIT(32'hFFFB0008))
\write_output[23]_i_1
(.I0(result[23]),
.I1(write_enable),
.I2(\write_output[31]_i_3_n_0 ),
.I3(\write_output[31]_i_4_n_0 ),
.I4(register_a[23]),
.O(\write_output[23]_i_1_n_0 ));
LUT5 #(
.INIT(32'hFFFB0008))
\write_output[24]_i_1
(.I0(result[24]),
.I1(write_enable),
.I2(\write_output[31]_i_3_n_0 ),
.I3(\write_output[31]_i_4_n_0 ),
.I4(register_a[24]),
.O(\write_output[24]_i_1_n_0 ));
LUT5 #(
.INIT(32'hFFFB0008))
\write_output[25]_i_1
(.I0(result[25]),
.I1(write_enable),
.I2(\write_output[31]_i_3_n_0 ),
.I3(\write_output[31]_i_4_n_0 ),
.I4(register_a[25]),
.O(\write_output[25]_i_1_n_0 ));
LUT5 #(
.INIT(32'hFFFB0008))
\write_output[26]_i_1
(.I0(result[26]),
.I1(write_enable),
.I2(\write_output[31]_i_3_n_0 ),
.I3(\write_output[31]_i_4_n_0 ),
.I4(register_a[26]),
.O(\write_output[26]_i_1_n_0 ));
LUT5 #(
.INIT(32'hFFFB0008))
\write_output[27]_i_1
(.I0(result[27]),
.I1(write_enable),
.I2(\write_output[31]_i_3_n_0 ),
.I3(\write_output[31]_i_4_n_0 ),
.I4(register_a[27]),
.O(\write_output[27]_i_1_n_0 ));
LUT5 #(
.INIT(32'hFFFB0008))
\write_output[28]_i_1
(.I0(result[28]),
.I1(write_enable),
.I2(\write_output[31]_i_3_n_0 ),
.I3(\write_output[31]_i_4_n_0 ),
.I4(register_a[28]),
.O(\write_output[28]_i_1_n_0 ));
LUT5 #(
.INIT(32'hFFFB0008))
\write_output[29]_i_1
(.I0(result[29]),
.I1(write_enable),
.I2(\write_output[31]_i_3_n_0 ),
.I3(\write_output[31]_i_4_n_0 ),
.I4(register_a[29]),
.O(\write_output[29]_i_1_n_0 ));
LUT5 #(
.INIT(32'hFFFB0008))
\write_output[2]_i_1
(.I0(result[2]),
.I1(write_enable),
.I2(\write_output[31]_i_3_n_0 ),
.I3(\write_output[31]_i_4_n_0 ),
.I4(register_a[2]),
.O(\write_output[2]_i_1_n_0 ));
LUT5 #(
.INIT(32'hFFFB0008))
\write_output[30]_i_1
(.I0(result[30]),
.I1(write_enable),
.I2(\write_output[31]_i_3_n_0 ),
.I3(\write_output[31]_i_4_n_0 ),
.I4(register_a[30]),
.O(\write_output[30]_i_1_n_0 ));
LUT6 #(
.INIT(64'h0000008000000000))
\write_output[31]_i_1
(.I0(\state_reg_n_0_[0] ),
.I1(opcode_20),
.I2(opcode_2[0]),
.I3(opcode_2[1]),
.I4(opcode_2[2]),
.I5(opcode_2[3]),
.O(\write_output[31]_i_1_n_0 ));
LUT5 #(
.INIT(32'hFFFB0008))
\write_output[31]_i_2
(.I0(result[31]),
.I1(write_enable),
.I2(\write_output[31]_i_3_n_0 ),
.I3(\write_output[31]_i_4_n_0 ),
.I4(register_a[31]),
.O(\write_output[31]_i_2_n_0 ));
LUT4 #(
.INIT(16'h6FF6))
\write_output[31]_i_3
(.I0(address_a_2[2]),
.I1(address_z_3[2]),
.I2(address_a_2[1]),
.I3(address_z_3[1]),
.O(\write_output[31]_i_3_n_0 ));
LUT4 #(
.INIT(16'h6FF6))
\write_output[31]_i_4
(.I0(address_a_2[0]),
.I1(address_z_3[0]),
.I2(address_a_2[3]),
.I3(address_z_3[3]),
.O(\write_output[31]_i_4_n_0 ));
LUT5 #(
.INIT(32'hFFFB0008))
\write_output[3]_i_1
(.I0(result[3]),
.I1(write_enable),
.I2(\write_output[31]_i_3_n_0 ),
.I3(\write_output[31]_i_4_n_0 ),
.I4(register_a[3]),
.O(\write_output[3]_i_1_n_0 ));
LUT5 #(
.INIT(32'hFFFB0008))
\write_output[4]_i_1
(.I0(result[4]),
.I1(write_enable),
.I2(\write_output[31]_i_3_n_0 ),
.I3(\write_output[31]_i_4_n_0 ),
.I4(register_a[4]),
.O(\write_output[4]_i_1_n_0 ));
LUT5 #(
.INIT(32'hFFFB0008))
\write_output[5]_i_1
(.I0(result[5]),
.I1(write_enable),
.I2(\write_output[31]_i_3_n_0 ),
.I3(\write_output[31]_i_4_n_0 ),
.I4(register_a[5]),
.O(\write_output[5]_i_1_n_0 ));
LUT5 #(
.INIT(32'hFFFB0008))
\write_output[6]_i_1
(.I0(result[6]),
.I1(write_enable),
.I2(\write_output[31]_i_3_n_0 ),
.I3(\write_output[31]_i_4_n_0 ),
.I4(register_a[6]),
.O(\write_output[6]_i_1_n_0 ));
LUT5 #(
.INIT(32'hFFFB0008))
\write_output[7]_i_1
(.I0(result[7]),
.I1(write_enable),
.I2(\write_output[31]_i_3_n_0 ),
.I3(\write_output[31]_i_4_n_0 ),
.I4(register_a[7]),
.O(\write_output[7]_i_1_n_0 ));
LUT5 #(
.INIT(32'hFFFB0008))
\write_output[8]_i_1
(.I0(result[8]),
.I1(write_enable),
.I2(\write_output[31]_i_3_n_0 ),
.I3(\write_output[31]_i_4_n_0 ),
.I4(register_a[8]),
.O(\write_output[8]_i_1_n_0 ));
LUT5 #(
.INIT(32'hFFFB0008))
\write_output[9]_i_1
(.I0(result[9]),
.I1(write_enable),
.I2(\write_output[31]_i_3_n_0 ),
.I3(\write_output[31]_i_4_n_0 ),
.I4(register_a[9]),
.O(\write_output[9]_i_1_n_0 ));
FDRE \write_output_reg[0]
(.C(ETH_CLK_OBUF),
.CE(\write_output[31]_i_1_n_0 ),
.D(\write_output[0]_i_1_n_0 ),
.Q(write_output[0]),
.R(1'b0));
FDRE \write_output_reg[10]
(.C(ETH_CLK_OBUF),
.CE(\write_output[31]_i_1_n_0 ),
.D(\write_output[10]_i_1_n_0 ),
.Q(write_output[10]),
.R(1'b0));
FDRE \write_output_reg[11]
(.C(ETH_CLK_OBUF),
.CE(\write_output[31]_i_1_n_0 ),
.D(\write_output[11]_i_1_n_0 ),
.Q(write_output[11]),
.R(1'b0));
FDRE \write_output_reg[12]
(.C(ETH_CLK_OBUF),
.CE(\write_output[31]_i_1_n_0 ),
.D(\write_output[12]_i_1_n_0 ),
.Q(write_output[12]),
.R(1'b0));
FDRE \write_output_reg[13]
(.C(ETH_CLK_OBUF),
.CE(\write_output[31]_i_1_n_0 ),
.D(\write_output[13]_i_1_n_0 ),
.Q(write_output[13]),
.R(1'b0));
FDRE \write_output_reg[14]
(.C(ETH_CLK_OBUF),
.CE(\write_output[31]_i_1_n_0 ),
.D(\write_output[14]_i_1_n_0 ),
.Q(write_output[14]),
.R(1'b0));
FDRE \write_output_reg[15]
(.C(ETH_CLK_OBUF),
.CE(\write_output[31]_i_1_n_0 ),
.D(\write_output[15]_i_1_n_0 ),
.Q(write_output[15]),
.R(1'b0));
FDRE \write_output_reg[16]
(.C(ETH_CLK_OBUF),
.CE(\write_output[31]_i_1_n_0 ),
.D(\write_output[16]_i_1_n_0 ),
.Q(write_output[16]),
.R(1'b0));
FDRE \write_output_reg[17]
(.C(ETH_CLK_OBUF),
.CE(\write_output[31]_i_1_n_0 ),
.D(\write_output[17]_i_1_n_0 ),
.Q(write_output[17]),
.R(1'b0));
FDRE \write_output_reg[18]
(.C(ETH_CLK_OBUF),
.CE(\write_output[31]_i_1_n_0 ),
.D(\write_output[18]_i_1_n_0 ),
.Q(write_output[18]),
.R(1'b0));
FDRE \write_output_reg[19]
(.C(ETH_CLK_OBUF),
.CE(\write_output[31]_i_1_n_0 ),
.D(\write_output[19]_i_1_n_0 ),
.Q(write_output[19]),
.R(1'b0));
FDRE \write_output_reg[1]
(.C(ETH_CLK_OBUF),
.CE(\write_output[31]_i_1_n_0 ),
.D(\write_output[1]_i_1_n_0 ),
.Q(write_output[1]),
.R(1'b0));
FDRE \write_output_reg[20]
(.C(ETH_CLK_OBUF),
.CE(\write_output[31]_i_1_n_0 ),
.D(\write_output[20]_i_1_n_0 ),
.Q(write_output[20]),
.R(1'b0));
FDRE \write_output_reg[21]
(.C(ETH_CLK_OBUF),
.CE(\write_output[31]_i_1_n_0 ),
.D(\write_output[21]_i_1_n_0 ),
.Q(write_output[21]),
.R(1'b0));
FDRE \write_output_reg[22]
(.C(ETH_CLK_OBUF),
.CE(\write_output[31]_i_1_n_0 ),
.D(\write_output[22]_i_1_n_0 ),
.Q(write_output[22]),
.R(1'b0));
FDRE \write_output_reg[23]
(.C(ETH_CLK_OBUF),
.CE(\write_output[31]_i_1_n_0 ),
.D(\write_output[23]_i_1_n_0 ),
.Q(write_output[23]),
.R(1'b0));
FDRE \write_output_reg[24]
(.C(ETH_CLK_OBUF),
.CE(\write_output[31]_i_1_n_0 ),
.D(\write_output[24]_i_1_n_0 ),
.Q(write_output[24]),
.R(1'b0));
FDRE \write_output_reg[25]
(.C(ETH_CLK_OBUF),
.CE(\write_output[31]_i_1_n_0 ),
.D(\write_output[25]_i_1_n_0 ),
.Q(write_output[25]),
.R(1'b0));
FDRE \write_output_reg[26]
(.C(ETH_CLK_OBUF),
.CE(\write_output[31]_i_1_n_0 ),
.D(\write_output[26]_i_1_n_0 ),
.Q(write_output[26]),
.R(1'b0));
FDRE \write_output_reg[27]
(.C(ETH_CLK_OBUF),
.CE(\write_output[31]_i_1_n_0 ),
.D(\write_output[27]_i_1_n_0 ),
.Q(write_output[27]),
.R(1'b0));
FDRE \write_output_reg[28]
(.C(ETH_CLK_OBUF),
.CE(\write_output[31]_i_1_n_0 ),
.D(\write_output[28]_i_1_n_0 ),
.Q(write_output[28]),
.R(1'b0));
FDRE \write_output_reg[29]
(.C(ETH_CLK_OBUF),
.CE(\write_output[31]_i_1_n_0 ),
.D(\write_output[29]_i_1_n_0 ),
.Q(write_output[29]),
.R(1'b0));
FDRE \write_output_reg[2]
(.C(ETH_CLK_OBUF),
.CE(\write_output[31]_i_1_n_0 ),
.D(\write_output[2]_i_1_n_0 ),
.Q(write_output[2]),
.R(1'b0));
FDRE \write_output_reg[30]
(.C(ETH_CLK_OBUF),
.CE(\write_output[31]_i_1_n_0 ),
.D(\write_output[30]_i_1_n_0 ),
.Q(write_output[30]),
.R(1'b0));
FDRE \write_output_reg[31]
(.C(ETH_CLK_OBUF),
.CE(\write_output[31]_i_1_n_0 ),
.D(\write_output[31]_i_2_n_0 ),
.Q(write_output[31]),
.R(1'b0));
FDRE \write_output_reg[3]
(.C(ETH_CLK_OBUF),
.CE(\write_output[31]_i_1_n_0 ),
.D(\write_output[3]_i_1_n_0 ),
.Q(write_output[3]),
.R(1'b0));
FDRE \write_output_reg[4]
(.C(ETH_CLK_OBUF),
.CE(\write_output[31]_i_1_n_0 ),
.D(\write_output[4]_i_1_n_0 ),
.Q(write_output[4]),
.R(1'b0));
FDRE \write_output_reg[5]
(.C(ETH_CLK_OBUF),
.CE(\write_output[31]_i_1_n_0 ),
.D(\write_output[5]_i_1_n_0 ),
.Q(write_output[5]),
.R(1'b0));
FDRE \write_output_reg[6]
(.C(ETH_CLK_OBUF),
.CE(\write_output[31]_i_1_n_0 ),
.D(\write_output[6]_i_1_n_0 ),
.Q(write_output[6]),
.R(1'b0));
FDRE \write_output_reg[7]
(.C(ETH_CLK_OBUF),
.CE(\write_output[31]_i_1_n_0 ),
.D(\write_output[7]_i_1_n_0 ),
.Q(write_output[7]),
.R(1'b0));
FDRE \write_output_reg[8]
(.C(ETH_CLK_OBUF),
.CE(\write_output[31]_i_1_n_0 ),
.D(\write_output[8]_i_1_n_0 ),
.Q(write_output[8]),
.R(1'b0));
FDRE \write_output_reg[9]
(.C(ETH_CLK_OBUF),
.CE(\write_output[31]_i_1_n_0 ),
.D(\write_output[9]_i_1_n_0 ),
.Q(write_output[9]),
.R(1'b0));
LUT3 #(
.INIT(8'hB8))
\write_value[0]_i_1
(.I0(result[0]),
.I1(operand_b1),
.I2(register_b[0]),
.O(store_data[0]));
LUT3 #(
.INIT(8'hB8))
\write_value[1]_i_1
(.I0(result[1]),
.I1(operand_b1),
.I2(register_b[1]),
.O(store_data[1]));
LUT3 #(
.INIT(8'hB8))
\write_value[2]_i_1
(.I0(result[2]),
.I1(operand_b1),
.I2(register_b[2]),
.O(store_data[2]));
LUT3 #(
.INIT(8'hB8))
\write_value[3]_i_1
(.I0(result[3]),
.I1(operand_b1),
.I2(register_b[3]),
.O(store_data[3]));
LUT3 #(
.INIT(8'hB8))
\write_value[4]_i_1
(.I0(result[4]),
.I1(operand_b1),
.I2(register_b[4]),
.O(store_data[4]));
LUT3 #(
.INIT(8'hB8))
\write_value[5]_i_1
(.I0(result[5]),
.I1(operand_b1),
.I2(register_b[5]),
.O(store_data[5]));
LUT3 #(
.INIT(8'hB8))
\write_value[6]_i_1
(.I0(result[6]),
.I1(operand_b1),
.I2(register_b[6]),
.O(store_data[6]));
LUT3 #(
.INIT(8'hB8))
\write_value[7]_i_1
(.I0(result[7]),
.I1(operand_b1),
.I2(register_b[7]),
.O(store_data[7]));
LUT6 #(
.INIT(64'h2002000000002002))
\write_value[7]_i_2
(.I0(write_enable),
.I1(\write_value[7]_i_3_n_0 ),
.I2(address_z_3[0]),
.I3(address_b_2[0]),
.I4(address_z_3[3]),
.I5(address_b_2[3]),
.O(operand_b1));
LUT4 #(
.INIT(16'h6FF6))
\write_value[7]_i_3
(.I0(address_z_3[2]),
.I1(address_b_2[2]),
.I2(address_z_3[1]),
.I3(address_b_2[1]),
.O(\write_value[7]_i_3_n_0 ));
FDRE \write_value_reg[0]
(.C(ETH_CLK_OBUF),
.CE(\write_output[31]_i_1_n_0 ),
.D(store_data[0]),
.Q(write_value[0]),
.R(1'b0));
FDRE \write_value_reg[1]
(.C(ETH_CLK_OBUF),
.CE(\write_output[31]_i_1_n_0 ),
.D(store_data[1]),
.Q(write_value[1]),
.R(1'b0));
FDRE \write_value_reg[2]
(.C(ETH_CLK_OBUF),
.CE(\write_output[31]_i_1_n_0 ),
.D(store_data[2]),
.Q(write_value[2]),
.R(1'b0));
FDRE \write_value_reg[3]
(.C(ETH_CLK_OBUF),
.CE(\write_output[31]_i_1_n_0 ),
.D(store_data[3]),
.Q(write_value[3]),
.R(1'b0));
FDRE \write_value_reg[4]
(.C(ETH_CLK_OBUF),
.CE(\write_output[31]_i_1_n_0 ),
.D(store_data[4]),
.Q(write_value[4]),
.R(1'b0));
FDRE \write_value_reg[5]
(.C(ETH_CLK_OBUF),
.CE(\write_output[31]_i_1_n_0 ),
.D(store_data[5]),
.Q(write_value[5]),
.R(1'b0));
FDRE \write_value_reg[6]
(.C(ETH_CLK_OBUF),
.CE(\write_output[31]_i_1_n_0 ),
.D(store_data[6]),
.Q(write_value[6]),
.R(1'b0));
FDRE \write_value_reg[7]
(.C(ETH_CLK_OBUF),
.CE(\write_output[31]_i_1_n_0 ),
.D(store_data[7]),
.Q(write_value[7]),
.R(1'b0));
endmodule
|
module pwm_audio
(JC_IBUF,
INTERNAL_RST_reg,
ETH_CLK_OBUF);
output [0:0]JC_IBUF;
input INTERNAL_RST_reg;
input ETH_CLK_OBUF;
wire \COUNT[10]_i_2_n_0 ;
wire \COUNT[10]_i_4_n_0 ;
wire \COUNT[10]_i_5_n_0 ;
wire \COUNT[10]_i_6_n_0 ;
wire \COUNT[9]_i_2_n_0 ;
wire [10:0]COUNT_reg__0;
wire ETH_CLK_OBUF;
wire INTERNAL_RST_reg;
wire [0:0]JC_IBUF;
wire STATE;
wire STATE_i_1_n_0;
wire STATE_reg_n_0;
wire S_DATA_IN_ACK_i_1_n_0;
wire [10:0]p_0_in;
(* SOFT_HLUTNM = "soft_lutpair172" *)
LUT1 #(
.INIT(2'h1))
\COUNT[0]_i_1__4
(.I0(COUNT_reg__0[0]),
.O(p_0_in[0]));
LUT2 #(
.INIT(4'h2))
\COUNT[10]_i_1
(.I0(JC_IBUF),
.I1(STATE_reg_n_0),
.O(STATE));
LUT2 #(
.INIT(4'h2))
\COUNT[10]_i_2
(.I0(STATE_reg_n_0),
.I1(\COUNT[10]_i_4_n_0 ),
.O(\COUNT[10]_i_2_n_0 ));
LUT3 #(
.INIT(8'h6A))
\COUNT[10]_i_3
(.I0(COUNT_reg__0[10]),
.I1(\COUNT[10]_i_5_n_0 ),
.I2(COUNT_reg__0[9]),
.O(p_0_in[10]));
LUT6 #(
.INIT(64'h0000800000000000))
\COUNT[10]_i_4
(.I0(COUNT_reg__0[2]),
.I1(COUNT_reg__0[3]),
.I2(COUNT_reg__0[6]),
.I3(COUNT_reg__0[5]),
.I4(COUNT_reg__0[7]),
.I5(\COUNT[10]_i_6_n_0 ),
.O(\COUNT[10]_i_4_n_0 ));
LUT5 #(
.INIT(32'h80000000))
\COUNT[10]_i_5
(.I0(COUNT_reg__0[8]),
.I1(COUNT_reg__0[7]),
.I2(\COUNT[9]_i_2_n_0 ),
.I3(COUNT_reg__0[6]),
.I4(COUNT_reg__0[5]),
.O(\COUNT[10]_i_5_n_0 ));
LUT6 #(
.INIT(64'h0000000000000004))
\COUNT[10]_i_6
(.I0(COUNT_reg__0[9]),
.I1(COUNT_reg__0[10]),
.I2(COUNT_reg__0[4]),
.I3(COUNT_reg__0[8]),
.I4(COUNT_reg__0[0]),
.I5(COUNT_reg__0[1]),
.O(\COUNT[10]_i_6_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair172" *)
LUT2 #(
.INIT(4'h6))
\COUNT[1]_i_1__4
(.I0(COUNT_reg__0[0]),
.I1(COUNT_reg__0[1]),
.O(p_0_in[1]));
(* SOFT_HLUTNM = "soft_lutpair171" *)
LUT3 #(
.INIT(8'h78))
\COUNT[2]_i_1__3
(.I0(COUNT_reg__0[0]),
.I1(COUNT_reg__0[1]),
.I2(COUNT_reg__0[2]),
.O(p_0_in[2]));
(* SOFT_HLUTNM = "soft_lutpair171" *)
LUT4 #(
.INIT(16'h6AAA))
\COUNT[3]_i_1__2
(.I0(COUNT_reg__0[3]),
.I1(COUNT_reg__0[0]),
.I2(COUNT_reg__0[1]),
.I3(COUNT_reg__0[2]),
.O(p_0_in[3]));
LUT5 #(
.INIT(32'h7FFF8000))
\COUNT[4]_i_1__2
(.I0(COUNT_reg__0[1]),
.I1(COUNT_reg__0[0]),
.I2(COUNT_reg__0[3]),
.I3(COUNT_reg__0[2]),
.I4(COUNT_reg__0[4]),
.O(p_0_in[4]));
LUT6 #(
.INIT(64'h6AAAAAAAAAAAAAAA))
\COUNT[5]_i_1__2
(.I0(COUNT_reg__0[5]),
.I1(COUNT_reg__0[1]),
.I2(COUNT_reg__0[0]),
.I3(COUNT_reg__0[3]),
.I4(COUNT_reg__0[2]),
.I5(COUNT_reg__0[4]),
.O(p_0_in[5]));
(* SOFT_HLUTNM = "soft_lutpair170" *)
LUT3 #(
.INIT(8'h6A))
\COUNT[6]_i_1__2
(.I0(COUNT_reg__0[6]),
.I1(\COUNT[9]_i_2_n_0 ),
.I2(COUNT_reg__0[5]),
.O(p_0_in[6]));
(* SOFT_HLUTNM = "soft_lutpair170" *)
LUT4 #(
.INIT(16'h6AAA))
\COUNT[7]_i_1__2
(.I0(COUNT_reg__0[7]),
.I1(COUNT_reg__0[5]),
.I2(COUNT_reg__0[6]),
.I3(\COUNT[9]_i_2_n_0 ),
.O(p_0_in[7]));
LUT5 #(
.INIT(32'h6AAAAAAA))
\COUNT[8]_i_1
(.I0(COUNT_reg__0[8]),
.I1(COUNT_reg__0[7]),
.I2(\COUNT[9]_i_2_n_0 ),
.I3(COUNT_reg__0[6]),
.I4(COUNT_reg__0[5]),
.O(p_0_in[8]));
LUT6 #(
.INIT(64'h6AAAAAAAAAAAAAAA))
\COUNT[9]_i_1
(.I0(COUNT_reg__0[9]),
.I1(COUNT_reg__0[5]),
.I2(COUNT_reg__0[6]),
.I3(\COUNT[9]_i_2_n_0 ),
.I4(COUNT_reg__0[7]),
.I5(COUNT_reg__0[8]),
.O(p_0_in[9]));
LUT5 #(
.INIT(32'h80000000))
\COUNT[9]_i_2
(.I0(COUNT_reg__0[4]),
.I1(COUNT_reg__0[2]),
.I2(COUNT_reg__0[3]),
.I3(COUNT_reg__0[0]),
.I4(COUNT_reg__0[1]),
.O(\COUNT[9]_i_2_n_0 ));
FDRE \COUNT_reg[0]
(.C(ETH_CLK_OBUF),
.CE(\COUNT[10]_i_2_n_0 ),
.D(p_0_in[0]),
.Q(COUNT_reg__0[0]),
.R(STATE));
FDRE \COUNT_reg[10]
(.C(ETH_CLK_OBUF),
.CE(\COUNT[10]_i_2_n_0 ),
.D(p_0_in[10]),
.Q(COUNT_reg__0[10]),
.R(STATE));
FDRE \COUNT_reg[1]
(.C(ETH_CLK_OBUF),
.CE(\COUNT[10]_i_2_n_0 ),
.D(p_0_in[1]),
.Q(COUNT_reg__0[1]),
.R(STATE));
FDRE \COUNT_reg[2]
(.C(ETH_CLK_OBUF),
.CE(\COUNT[10]_i_2_n_0 ),
.D(p_0_in[2]),
.Q(COUNT_reg__0[2]),
.R(STATE));
FDRE \COUNT_reg[3]
(.C(ETH_CLK_OBUF),
.CE(\COUNT[10]_i_2_n_0 ),
.D(p_0_in[3]),
.Q(COUNT_reg__0[3]),
.R(STATE));
FDRE \COUNT_reg[4]
(.C(ETH_CLK_OBUF),
.CE(\COUNT[10]_i_2_n_0 ),
.D(p_0_in[4]),
.Q(COUNT_reg__0[4]),
.R(STATE));
FDRE \COUNT_reg[5]
(.C(ETH_CLK_OBUF),
.CE(\COUNT[10]_i_2_n_0 ),
.D(p_0_in[5]),
.Q(COUNT_reg__0[5]),
.R(STATE));
FDRE \COUNT_reg[6]
(.C(ETH_CLK_OBUF),
.CE(\COUNT[10]_i_2_n_0 ),
.D(p_0_in[6]),
.Q(COUNT_reg__0[6]),
.R(STATE));
FDRE \COUNT_reg[7]
(.C(ETH_CLK_OBUF),
.CE(\COUNT[10]_i_2_n_0 ),
.D(p_0_in[7]),
.Q(COUNT_reg__0[7]),
.R(STATE));
FDRE \COUNT_reg[8]
(.C(ETH_CLK_OBUF),
.CE(\COUNT[10]_i_2_n_0 ),
.D(p_0_in[8]),
.Q(COUNT_reg__0[8]),
.R(STATE));
FDRE \COUNT_reg[9]
(.C(ETH_CLK_OBUF),
.CE(\COUNT[10]_i_2_n_0 ),
.D(p_0_in[9]),
.Q(COUNT_reg__0[9]),
.R(STATE));
LUT3 #(
.INIT(8'h4E))
STATE_i_1
(.I0(STATE_reg_n_0),
.I1(JC_IBUF),
.I2(\COUNT[10]_i_4_n_0 ),
.O(STATE_i_1_n_0));
FDRE STATE_reg
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(STATE_i_1_n_0),
.Q(STATE_reg_n_0),
.R(INTERNAL_RST_reg));
LUT3 #(
.INIT(8'h09))
S_DATA_IN_ACK_i_1
(.I0(STATE_reg_n_0),
.I1(JC_IBUF),
.I2(INTERNAL_RST_reg),
.O(S_DATA_IN_ACK_i_1_n_0));
FDRE S_DATA_IN_ACK_reg
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(S_DATA_IN_ACK_i_1_n_0),
.Q(JC_IBUF),
.R(1'b0));
endmodule
|
module rmii_ethernet
(TXEN_OBUF,
TXD_OBUF,
ETH_CLK_OBUF,
RXDV_IBUF,
RXER_IBUF,
INTERNAL_RST_reg,
D);
output TXEN_OBUF;
output [1:0]TXD_OBUF;
input ETH_CLK_OBUF;
input RXDV_IBUF;
input RXER_IBUF;
input INTERNAL_RST_reg;
input [1:0]D;
wire DONE;
wire DONE_DEL;
wire DONE_SYNC;
wire DONE_i_1_n_0;
wire ETH_CLK_OBUF;
wire GO;
wire GO_DEL;
wire GO_SYNC;
wire GO_i_1_n_0;
wire INTERNAL_RST_reg;
wire NEXTCRC32_D80108_out;
wire NEXTCRC32_D80177_out;
wire NEXTCRC32_D80181_out;
wire NEXTCRC32_D80189_out;
wire NEXTCRC32_D80195_out;
wire NEXTCRC32_D80203_out;
wire NEXTCRC32_D80217_out;
wire NEXTCRC32_D8070_out;
wire NEXTCRC32_D8074_out;
wire \PREAMBLE_COUNT[0]_i_1_n_0 ;
wire \PREAMBLE_COUNT[1]_i_1_n_0 ;
wire \PREAMBLE_COUNT[2]_i_1_n_0 ;
wire \PREAMBLE_COUNT[3]_i_1_n_0 ;
wire \PREAMBLE_COUNT[4]_i_1_n_0 ;
wire \PREAMBLE_COUNT[4]_i_2_n_0 ;
wire \PREAMBLE_COUNT[4]_i_3_n_0 ;
wire \PREAMBLE_COUNT[4]_i_4_n_0 ;
wire \PREAMBLE_COUNT_reg_n_0_[0] ;
wire \PREAMBLE_COUNT_reg_n_0_[1] ;
wire \PREAMBLE_COUNT_reg_n_0_[2] ;
wire \PREAMBLE_COUNT_reg_n_0_[3] ;
wire \PREAMBLE_COUNT_reg_n_0_[4] ;
wire S_TX_ACK_i_1_n_0;
wire S_TX_ACK_reg_n_0;
wire \TXD[0]_i_10_n_0 ;
wire \TXD[0]_i_11_n_0 ;
wire \TXD[0]_i_1_n_0 ;
wire \TXD[0]_i_2_n_0 ;
wire \TXD[0]_i_3_n_0 ;
wire \TXD[0]_i_6_n_0 ;
wire \TXD[0]_i_7_n_0 ;
wire \TXD[0]_i_8_n_0 ;
wire \TXD[0]_i_9_n_0 ;
wire \TXD[1]_i_10_n_0 ;
wire \TXD[1]_i_11_n_0 ;
wire \TXD[1]_i_12_n_0 ;
wire \TXD[1]_i_1_n_0 ;
wire \TXD[1]_i_2_n_0 ;
wire \TXD[1]_i_3_n_0 ;
wire \TXD[1]_i_4_n_0 ;
wire \TXD[1]_i_7_n_0 ;
wire \TXD[1]_i_8_n_0 ;
wire \TXD[1]_i_9_n_0 ;
wire [1:0]TXD_OBUF;
wire \TXD_reg[0]_i_4_n_0 ;
wire \TXD_reg[0]_i_5_n_0 ;
wire \TXD_reg[1]_i_5_n_0 ;
wire \TXD_reg[1]_i_6_n_0 ;
wire TXEN_OBUF;
wire TXEN_i_1_n_0;
wire \TX_CRC[0]_i_1_n_0 ;
wire \TX_CRC[10]_i_3_n_0 ;
wire \TX_CRC[10]_i_4_n_0 ;
wire \TX_CRC[10]_i_5_n_0 ;
wire \TX_CRC[11]_i_1_n_0 ;
wire \TX_CRC[11]_i_2_n_0 ;
wire \TX_CRC[11]_i_3_n_0 ;
wire \TX_CRC[11]_i_4_n_0 ;
wire \TX_CRC[12]_i_1_n_0 ;
wire \TX_CRC[12]_i_2_n_0 ;
wire \TX_CRC[12]_i_3_n_0 ;
wire \TX_CRC[12]_i_4_n_0 ;
wire \TX_CRC[12]_i_5_n_0 ;
wire \TX_CRC[12]_i_6_n_0 ;
wire \TX_CRC[12]_i_7_n_0 ;
wire \TX_CRC[13]_i_3_n_0 ;
wire \TX_CRC[13]_i_4_n_0 ;
wire \TX_CRC[13]_i_5_n_0 ;
wire \TX_CRC[14]_i_2_n_0 ;
wire \TX_CRC[14]_i_3_n_0 ;
wire \TX_CRC[14]_i_4_n_0 ;
wire \TX_CRC[14]_i_5_n_0 ;
wire \TX_CRC[15]_i_1_n_0 ;
wire \TX_CRC[15]_i_2_n_0 ;
wire \TX_CRC[15]_i_3_n_0 ;
wire \TX_CRC[15]_i_4_n_0 ;
wire \TX_CRC[15]_i_5_n_0 ;
wire \TX_CRC[16]_i_1_n_0 ;
wire \TX_CRC[16]_i_2_n_0 ;
wire \TX_CRC[16]_i_3_n_0 ;
wire \TX_CRC[17]_i_3_n_0 ;
wire \TX_CRC[17]_i_5_n_0 ;
wire \TX_CRC[18]_i_2_n_0 ;
wire \TX_CRC[18]_i_3_n_0 ;
wire \TX_CRC[19]_i_1_n_0 ;
wire \TX_CRC[19]_i_2_n_0 ;
wire \TX_CRC[1]_i_2_n_0 ;
wire \TX_CRC[1]_i_5_n_0 ;
wire \TX_CRC[20]_i_1_n_0 ;
wire \TX_CRC[21]_i_1_n_0 ;
wire \TX_CRC[22]_i_1_n_0 ;
wire \TX_CRC[23]_i_2_n_0 ;
wire \TX_CRC[24]_i_3_n_0 ;
wire \TX_CRC[24]_i_4_n_0 ;
wire \TX_CRC[24]_i_5_n_0 ;
wire \TX_CRC[25]_i_2_n_0 ;
wire \TX_CRC[25]_i_3_n_0 ;
wire \TX_CRC[26]_i_1_n_0 ;
wire \TX_CRC[26]_i_2_n_0 ;
wire \TX_CRC[26]_i_3_n_0 ;
wire \TX_CRC[26]_i_4_n_0 ;
wire \TX_CRC[27]_i_2_n_0 ;
wire \TX_CRC[27]_i_3_n_0 ;
wire \TX_CRC[27]_i_4_n_0 ;
wire \TX_CRC[28]_i_2_n_0 ;
wire \TX_CRC[28]_i_3_n_0 ;
wire \TX_CRC[29]_i_2_n_0 ;
wire \TX_CRC[29]_i_3_n_0 ;
wire \TX_CRC[29]_i_4_n_0 ;
wire \TX_CRC[29]_i_5_n_0 ;
wire \TX_CRC[2]_i_1_n_0 ;
wire \TX_CRC[2]_i_2_n_0 ;
wire \TX_CRC[2]_i_3_n_0 ;
wire \TX_CRC[2]_i_4_n_0 ;
wire \TX_CRC[2]_i_5_n_0 ;
wire \TX_CRC[30]_i_2_n_0 ;
wire \TX_CRC[30]_i_3_n_0 ;
wire \TX_CRC[31]_i_1_n_0 ;
wire \TX_CRC[31]_i_2_n_0 ;
wire \TX_CRC[31]_i_3_n_0 ;
wire \TX_CRC[3]_i_3_n_0 ;
wire \TX_CRC[3]_i_4_n_0 ;
wire \TX_CRC[4]_i_2_n_0 ;
wire \TX_CRC[4]_i_3_n_0 ;
wire \TX_CRC[4]_i_4_n_0 ;
wire \TX_CRC[4]_i_5_n_0 ;
wire \TX_CRC[5]_i_4_n_0 ;
wire \TX_CRC[5]_i_5_n_0 ;
wire \TX_CRC[5]_i_6_n_0 ;
wire \TX_CRC[6]_i_2_n_0 ;
wire \TX_CRC[6]_i_3_n_0 ;
wire \TX_CRC[6]_i_4_n_0 ;
wire \TX_CRC[6]_i_5_n_0 ;
wire \TX_CRC[7]_i_1_n_0 ;
wire \TX_CRC[7]_i_2_n_0 ;
wire \TX_CRC[7]_i_3_n_0 ;
wire \TX_CRC[7]_i_4_n_0 ;
wire \TX_CRC[8]_i_1_n_0 ;
wire \TX_CRC[9]_i_1_n_0 ;
wire \TX_CRC[9]_i_2_n_0 ;
wire \TX_CRC[9]_i_3_n_0 ;
wire \TX_CRC[9]_i_4_n_0 ;
wire \TX_CRC_reg[10]_i_1_n_0 ;
wire \TX_CRC_reg[13]_i_1_n_0 ;
wire \TX_CRC_reg[14]_i_1_n_0 ;
wire \TX_CRC_reg[17]_i_1_n_0 ;
wire \TX_CRC_reg[18]_i_1_n_0 ;
wire \TX_CRC_reg[1]_i_1_n_0 ;
wire \TX_CRC_reg[23]_i_1_n_0 ;
wire \TX_CRC_reg[24]_i_1_n_0 ;
wire \TX_CRC_reg[25]_i_1_n_0 ;
wire \TX_CRC_reg[27]_i_1_n_0 ;
wire \TX_CRC_reg[28]_i_1_n_0 ;
wire \TX_CRC_reg[29]_i_1_n_0 ;
wire \TX_CRC_reg[30]_i_1_n_0 ;
wire \TX_CRC_reg[3]_i_1_n_0 ;
wire \TX_CRC_reg[4]_i_1_n_0 ;
wire \TX_CRC_reg[5]_i_1_n_0 ;
wire \TX_CRC_reg[6]_i_1_n_0 ;
wire \TX_CRC_reg_n_0_[0] ;
wire \TX_CRC_reg_n_0_[10] ;
wire \TX_CRC_reg_n_0_[11] ;
wire \TX_CRC_reg_n_0_[12] ;
wire \TX_CRC_reg_n_0_[13] ;
wire \TX_CRC_reg_n_0_[14] ;
wire \TX_CRC_reg_n_0_[15] ;
wire \TX_CRC_reg_n_0_[16] ;
wire \TX_CRC_reg_n_0_[17] ;
wire \TX_CRC_reg_n_0_[18] ;
wire \TX_CRC_reg_n_0_[19] ;
wire \TX_CRC_reg_n_0_[20] ;
wire \TX_CRC_reg_n_0_[21] ;
wire \TX_CRC_reg_n_0_[22] ;
wire \TX_CRC_reg_n_0_[23] ;
wire \TX_CRC_reg_n_0_[8] ;
wire \TX_CRC_reg_n_0_[9] ;
wire [10:1]TX_IN_COUNT;
wire \TX_IN_COUNT[10]_i_1_n_0 ;
wire \TX_IN_COUNT[10]_i_2_n_0 ;
wire \TX_IN_COUNT[10]_i_3_n_0 ;
wire \TX_IN_COUNT[10]_i_4_n_0 ;
wire \TX_IN_COUNT[1]_i_1_n_0 ;
wire \TX_IN_COUNT[2]_i_1_n_0 ;
wire \TX_IN_COUNT[3]_i_1_n_0 ;
wire \TX_IN_COUNT[4]_i_1_n_0 ;
wire \TX_IN_COUNT[5]_i_1_n_0 ;
wire \TX_IN_COUNT[6]_i_1_n_0 ;
wire \TX_IN_COUNT[7]_i_1_n_0 ;
wire \TX_IN_COUNT[8]_i_1_n_0 ;
wire \TX_IN_COUNT[9]_i_1_n_0 ;
wire TX_MEMORY_reg_ENBWREN_cooolgate_en_sig_9;
wire TX_MEMORY_reg_n_59;
wire TX_MEMORY_reg_n_67;
wire [0:0]TX_OUT_COUNT0_in;
wire \TX_OUT_COUNT[10]_i_1_n_0 ;
wire \TX_OUT_COUNT[10]_i_2_n_0 ;
wire \TX_OUT_COUNT[10]_i_3_n_0 ;
wire \TX_OUT_COUNT[10]_i_4_n_0 ;
wire \TX_OUT_COUNT[10]_i_5_n_0 ;
wire \TX_OUT_COUNT[10]_i_6_n_0 ;
wire \TX_OUT_COUNT[10]_i_7_n_0 ;
wire \TX_OUT_COUNT[10]_i_8_n_0 ;
wire \TX_OUT_COUNT[1]_i_1_n_0 ;
wire \TX_OUT_COUNT[2]_i_1_n_0 ;
wire \TX_OUT_COUNT[3]_i_1_n_0 ;
wire \TX_OUT_COUNT[4]_i_1_n_0 ;
wire \TX_OUT_COUNT[5]_i_1_n_0 ;
wire \TX_OUT_COUNT[6]_i_1_n_0 ;
wire \TX_OUT_COUNT[7]_i_1_n_0 ;
wire \TX_OUT_COUNT[8]_i_1_n_0 ;
wire \TX_OUT_COUNT[8]_i_2_n_0 ;
wire \TX_OUT_COUNT[9]_i_1_n_0 ;
wire \TX_OUT_COUNT_reg_n_0_[0] ;
wire \TX_OUT_COUNT_reg_n_0_[10] ;
wire \TX_OUT_COUNT_reg_n_0_[1] ;
wire \TX_OUT_COUNT_reg_n_0_[2] ;
wire \TX_OUT_COUNT_reg_n_0_[3] ;
wire \TX_OUT_COUNT_reg_n_0_[4] ;
wire \TX_OUT_COUNT_reg_n_0_[5] ;
wire \TX_OUT_COUNT_reg_n_0_[6] ;
wire \TX_OUT_COUNT_reg_n_0_[7] ;
wire \TX_OUT_COUNT_reg_n_0_[8] ;
wire \TX_OUT_COUNT_reg_n_0_[9] ;
wire \TX_PACKET_STATE[0]_i_1_n_0 ;
wire \TX_PACKET_STATE[1]_i_10_n_0 ;
wire \TX_PACKET_STATE[1]_i_11_n_0 ;
wire \TX_PACKET_STATE[1]_i_12_n_0 ;
wire \TX_PACKET_STATE[1]_i_13_n_0 ;
wire \TX_PACKET_STATE[1]_i_1_n_0 ;
wire \TX_PACKET_STATE[1]_i_4_n_0 ;
wire \TX_PACKET_STATE[1]_i_5_n_0 ;
wire \TX_PACKET_STATE[1]_i_6_n_0 ;
wire \TX_PACKET_STATE[1]_i_7_n_0 ;
wire \TX_PACKET_STATE[1]_i_8_n_0 ;
wire \TX_PACKET_STATE[1]_i_9_n_0 ;
wire \TX_PACKET_STATE_reg[1]_i_2_n_2 ;
wire \TX_PACKET_STATE_reg[1]_i_3_n_0 ;
wire \TX_PACKET_STATE_reg_n_0_[0] ;
wire \TX_PACKET_STATE_reg_n_0_[1] ;
wire \TX_PHY_STATE[0]_i_1_n_0 ;
wire \TX_PHY_STATE[1]_i_1_n_0 ;
wire \TX_PHY_STATE[2]_i_1_n_0 ;
wire \TX_PHY_STATE[2]_i_2_n_0 ;
wire \TX_PHY_STATE[2]_i_3_n_0 ;
wire \TX_PHY_STATE[2]_i_4_n_0 ;
wire \TX_PHY_STATE[3]_i_1_n_0 ;
wire \TX_PHY_STATE[3]_i_2_n_0 ;
wire \TX_PHY_STATE[3]_i_3_n_0 ;
wire \TX_PHY_STATE[3]_i_4_n_0 ;
wire \TX_PHY_STATE[3]_i_5_n_0 ;
wire \TX_PHY_STATE[4]_i_1_n_0 ;
wire \TX_PHY_STATE[4]_i_2_n_0 ;
wire \TX_PHY_STATE[4]_i_3_n_0 ;
wire \TX_PHY_STATE[4]_i_4_n_0 ;
wire \TX_PHY_STATE_reg_n_0_[0] ;
wire \TX_PHY_STATE_reg_n_0_[1] ;
wire \TX_PHY_STATE_reg_n_0_[2] ;
wire \TX_PHY_STATE_reg_n_0_[3] ;
wire \TX_PHY_STATE_reg_n_0_[4] ;
wire [10:0]TX_READ_ADDRESS;
wire [10:1]TX_READ_ADDRESS0;
wire \TX_READ_ADDRESS_rep[0]_i_1_n_0 ;
wire \TX_READ_ADDRESS_rep[9]_i_1_n_0 ;
wire \TX_READ_ADDRESS_rep[9]_i_2_n_0 ;
wire \TX_READ_ADDRESS_rep[9]_i_4_n_0 ;
wire TX_WRITE;
wire [10:0]TX_WRITE_ADDRESS;
wire \TX_WRITE_ADDRESS[0]_i_1_n_0 ;
wire \TX_WRITE_ADDRESS[10]_i_1_n_0 ;
wire \TX_WRITE_ADDRESS[10]_i_2_n_0 ;
wire \TX_WRITE_ADDRESS[10]_i_3_n_0 ;
wire \TX_WRITE_ADDRESS[1]_i_1_n_0 ;
wire \TX_WRITE_ADDRESS[2]_i_1_n_0 ;
wire \TX_WRITE_ADDRESS[3]_i_1_n_0 ;
wire \TX_WRITE_ADDRESS[4]_i_1_n_0 ;
wire \TX_WRITE_ADDRESS[5]_i_1_n_0 ;
wire \TX_WRITE_ADDRESS[5]_i_2_n_0 ;
wire \TX_WRITE_ADDRESS[6]_i_1_n_0 ;
wire \TX_WRITE_ADDRESS[7]_i_1_n_0 ;
wire \TX_WRITE_ADDRESS[8]_i_1_n_0 ;
wire \TX_WRITE_ADDRESS[9]_i_1_n_0 ;
wire \TX_WRITE_ADDRESS[9]_i_2_n_0 ;
wire [10:0]TX_WRITE_ADDRESS_DEL;
wire TX_WRITE_i_1_n_0;
wire p_0_in167_in;
wire p_0_in66_in;
wire p_168_in;
wire [1:0]p_16_in;
wire [1:0]p_17_in;
wire [1:0]p_18_in;
wire p_1_in126_in;
wire p_1_in128_in;
wire p_1_in130_in;
wire p_1_in132_in;
wire p_1_in133_in;
wire p_1_in135_in;
wire p_1_in136_in;
wire p_202_in;
wire [1:0]p_20_in;
wire p_214_in;
wire [1:0]p_21_in;
wire p_222_in;
wire p_224_in;
wire [1:0]p_22_in;
wire [7:0]slv1_out;
wire NLW_TX_MEMORY_reg_CASCADEOUTA_UNCONNECTED;
wire NLW_TX_MEMORY_reg_CASCADEOUTB_UNCONNECTED;
wire NLW_TX_MEMORY_reg_DBITERR_UNCONNECTED;
wire NLW_TX_MEMORY_reg_INJECTDBITERR_UNCONNECTED;
wire NLW_TX_MEMORY_reg_INJECTSBITERR_UNCONNECTED;
wire NLW_TX_MEMORY_reg_REGCEAREGCE_UNCONNECTED;
wire NLW_TX_MEMORY_reg_REGCEB_UNCONNECTED;
wire NLW_TX_MEMORY_reg_SBITERR_UNCONNECTED;
wire [31:0]NLW_TX_MEMORY_reg_DOADO_UNCONNECTED;
wire [31:16]NLW_TX_MEMORY_reg_DOBDO_UNCONNECTED;
wire [3:0]NLW_TX_MEMORY_reg_DOPADOP_UNCONNECTED;
wire [3:0]NLW_TX_MEMORY_reg_DOPBDOP_UNCONNECTED;
wire [7:0]NLW_TX_MEMORY_reg_ECCPARITY_UNCONNECTED;
wire [8:0]NLW_TX_MEMORY_reg_RDADDRECC_UNCONNECTED;
wire [3:0]\NLW_TX_PACKET_STATE_reg[1]_i_2_CO_UNCONNECTED ;
wire [3:0]\NLW_TX_PACKET_STATE_reg[1]_i_2_O_UNCONNECTED ;
wire [2:0]\NLW_TX_PACKET_STATE_reg[1]_i_3_CO_UNCONNECTED ;
wire [3:0]\NLW_TX_PACKET_STATE_reg[1]_i_3_O_UNCONNECTED ;
FDRE DONE_DEL_reg
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(DONE),
.Q(DONE_DEL),
.R(1'b0));
FDRE DONE_SYNC_reg
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(DONE_DEL),
.Q(DONE_SYNC),
.R(1'b0));
LUT6 #(
.INIT(64'hBFFFFFFF80000000))
DONE_i_1
(.I0(GO_SYNC),
.I1(\TX_PHY_STATE_reg_n_0_[4] ),
.I2(\TX_PHY_STATE_reg_n_0_[3] ),
.I3(\TX_PHY_STATE_reg_n_0_[1] ),
.I4(\TX_PHY_STATE_reg_n_0_[2] ),
.I5(DONE),
.O(DONE_i_1_n_0));
FDRE DONE_reg
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(DONE_i_1_n_0),
.Q(DONE),
.R(INTERNAL_RST_reg));
FDRE GO_DEL_reg
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(GO),
.Q(GO_DEL),
.R(1'b0));
FDRE GO_SYNC_reg
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(GO_DEL),
.Q(GO_SYNC),
.R(1'b0));
LUT4 #(
.INIT(16'hF704))
GO_i_1
(.I0(DONE_SYNC),
.I1(\TX_PACKET_STATE_reg_n_0_[1] ),
.I2(\TX_PACKET_STATE_reg_n_0_[0] ),
.I3(GO),
.O(GO_i_1_n_0));
FDRE GO_reg
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(GO_i_1_n_0),
.Q(GO),
.R(INTERNAL_RST_reg));
LUT1 #(
.INIT(2'h1))
\PREAMBLE_COUNT[0]_i_1
(.I0(\PREAMBLE_COUNT_reg_n_0_[0] ),
.O(\PREAMBLE_COUNT[0]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair149" *)
LUT2 #(
.INIT(4'h9))
\PREAMBLE_COUNT[1]_i_1
(.I0(\PREAMBLE_COUNT_reg_n_0_[0] ),
.I1(\PREAMBLE_COUNT_reg_n_0_[1] ),
.O(\PREAMBLE_COUNT[1]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFDFDFDDD00000020))
\PREAMBLE_COUNT[2]_i_1
(.I0(\PREAMBLE_COUNT[4]_i_4_n_0 ),
.I1(\TX_PHY_STATE_reg_n_0_[4] ),
.I2(\TX_PHY_STATE_reg_n_0_[0] ),
.I3(\PREAMBLE_COUNT_reg_n_0_[0] ),
.I4(\PREAMBLE_COUNT_reg_n_0_[1] ),
.I5(\PREAMBLE_COUNT_reg_n_0_[2] ),
.O(\PREAMBLE_COUNT[2]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair149" *)
LUT4 #(
.INIT(16'hFE01))
\PREAMBLE_COUNT[3]_i_1
(.I0(\PREAMBLE_COUNT_reg_n_0_[2] ),
.I1(\PREAMBLE_COUNT_reg_n_0_[0] ),
.I2(\PREAMBLE_COUNT_reg_n_0_[1] ),
.I3(\PREAMBLE_COUNT_reg_n_0_[3] ),
.O(\PREAMBLE_COUNT[3]_i_1_n_0 ));
LUT3 #(
.INIT(8'h02))
\PREAMBLE_COUNT[4]_i_1
(.I0(\PREAMBLE_COUNT[4]_i_4_n_0 ),
.I1(\TX_PHY_STATE_reg_n_0_[4] ),
.I2(\TX_PHY_STATE_reg_n_0_[0] ),
.O(\PREAMBLE_COUNT[4]_i_1_n_0 ));
LUT2 #(
.INIT(4'h2))
\PREAMBLE_COUNT[4]_i_2
(.I0(\PREAMBLE_COUNT[4]_i_4_n_0 ),
.I1(\TX_PHY_STATE_reg_n_0_[4] ),
.O(\PREAMBLE_COUNT[4]_i_2_n_0 ));
LUT5 #(
.INIT(32'hFFFE0001))
\PREAMBLE_COUNT[4]_i_3
(.I0(\PREAMBLE_COUNT_reg_n_0_[3] ),
.I1(\PREAMBLE_COUNT_reg_n_0_[1] ),
.I2(\PREAMBLE_COUNT_reg_n_0_[0] ),
.I3(\PREAMBLE_COUNT_reg_n_0_[2] ),
.I4(\PREAMBLE_COUNT_reg_n_0_[4] ),
.O(\PREAMBLE_COUNT[4]_i_3_n_0 ));
LUT6 #(
.INIT(64'h0000000001110100))
\PREAMBLE_COUNT[4]_i_4
(.I0(\TX_PHY_STATE_reg_n_0_[1] ),
.I1(\TX_PHY_STATE_reg_n_0_[2] ),
.I2(\TX_PHY_STATE[4]_i_4_n_0 ),
.I3(\TX_PHY_STATE_reg_n_0_[0] ),
.I4(GO_SYNC),
.I5(\TX_PHY_STATE_reg_n_0_[3] ),
.O(\PREAMBLE_COUNT[4]_i_4_n_0 ));
FDSE \PREAMBLE_COUNT_reg[0]
(.C(ETH_CLK_OBUF),
.CE(\PREAMBLE_COUNT[4]_i_2_n_0 ),
.D(\PREAMBLE_COUNT[0]_i_1_n_0 ),
.Q(\PREAMBLE_COUNT_reg_n_0_[0] ),
.S(\PREAMBLE_COUNT[4]_i_1_n_0 ));
FDSE \PREAMBLE_COUNT_reg[1]
(.C(ETH_CLK_OBUF),
.CE(\PREAMBLE_COUNT[4]_i_2_n_0 ),
.D(\PREAMBLE_COUNT[1]_i_1_n_0 ),
.Q(\PREAMBLE_COUNT_reg_n_0_[1] ),
.S(\PREAMBLE_COUNT[4]_i_1_n_0 ));
FDRE \PREAMBLE_COUNT_reg[2]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(\PREAMBLE_COUNT[2]_i_1_n_0 ),
.Q(\PREAMBLE_COUNT_reg_n_0_[2] ),
.R(1'b0));
FDSE \PREAMBLE_COUNT_reg[3]
(.C(ETH_CLK_OBUF),
.CE(\PREAMBLE_COUNT[4]_i_2_n_0 ),
.D(\PREAMBLE_COUNT[3]_i_1_n_0 ),
.Q(\PREAMBLE_COUNT_reg_n_0_[3] ),
.S(\PREAMBLE_COUNT[4]_i_1_n_0 ));
FDSE \PREAMBLE_COUNT_reg[4]
(.C(ETH_CLK_OBUF),
.CE(\PREAMBLE_COUNT[4]_i_2_n_0 ),
.D(\PREAMBLE_COUNT[4]_i_3_n_0 ),
.Q(\PREAMBLE_COUNT_reg_n_0_[4] ),
.S(\PREAMBLE_COUNT[4]_i_1_n_0 ));
LUT4 #(
.INIT(16'hAE55))
S_TX_ACK_i_1
(.I0(\TX_PACKET_STATE_reg_n_0_[1] ),
.I1(\TX_PACKET_STATE_reg_n_0_[0] ),
.I2(\TX_PACKET_STATE_reg[1]_i_2_n_2 ),
.I3(S_TX_ACK_reg_n_0),
.O(S_TX_ACK_i_1_n_0));
FDRE S_TX_ACK_reg
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(S_TX_ACK_i_1_n_0),
.Q(S_TX_ACK_reg_n_0),
.R(INTERNAL_RST_reg));
(* SOFT_HLUTNM = "soft_lutpair158" *)
LUT3 #(
.INIT(8'hB8))
\TXD[0]_i_1
(.I0(\TXD[0]_i_2_n_0 ),
.I1(\TXD[1]_i_3_n_0 ),
.I2(TXD_OBUF[0]),
.O(\TXD[0]_i_1_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\TXD[0]_i_10
(.I0(p_18_in[0]),
.I1(TX_MEMORY_reg_n_67),
.I2(\TX_PHY_STATE_reg_n_0_[1] ),
.I3(p_20_in[0]),
.I4(\TX_PHY_STATE_reg_n_0_[0] ),
.I5(p_21_in[0]),
.O(\TXD[0]_i_10_n_0 ));
LUT6 #(
.INIT(64'h5F503F3F5F503030))
\TXD[0]_i_11
(.I0(slv1_out[5]),
.I1(slv1_out[7]),
.I2(\TX_PHY_STATE_reg_n_0_[1] ),
.I3(p_16_in[0]),
.I4(\TX_PHY_STATE_reg_n_0_[0] ),
.I5(p_17_in[0]),
.O(\TXD[0]_i_11_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\TXD[0]_i_2
(.I0(\TXD[0]_i_3_n_0 ),
.I1(\TXD_reg[0]_i_4_n_0 ),
.I2(\TX_PHY_STATE_reg_n_0_[4] ),
.I3(\TXD_reg[0]_i_5_n_0 ),
.I4(\TX_PHY_STATE_reg_n_0_[3] ),
.I5(\TXD[0]_i_6_n_0 ),
.O(\TXD[0]_i_2_n_0 ));
LUT5 #(
.INIT(32'h47FF4700))
\TXD[0]_i_3
(.I0(p_1_in126_in),
.I1(\TX_PHY_STATE_reg_n_0_[0] ),
.I2(p_1_in130_in),
.I3(\TX_PHY_STATE_reg_n_0_[2] ),
.I4(\TXD[0]_i_7_n_0 ),
.O(\TXD[0]_i_3_n_0 ));
LUT5 #(
.INIT(32'hE2FFFFFF))
\TXD[0]_i_6
(.I0(TX_MEMORY_reg_n_59),
.I1(\TX_PHY_STATE_reg_n_0_[0] ),
.I2(p_22_in[0]),
.I3(\TX_PHY_STATE_reg_n_0_[2] ),
.I4(\TX_PHY_STATE_reg_n_0_[1] ),
.O(\TXD[0]_i_6_n_0 ));
LUT6 #(
.INIT(64'h505F3030505F3F3F))
\TXD[0]_i_7
(.I0(p_1_in133_in),
.I1(p_1_in136_in),
.I2(\TX_PHY_STATE_reg_n_0_[1] ),
.I3(\TX_CRC_reg_n_0_[9] ),
.I4(\TX_PHY_STATE_reg_n_0_[0] ),
.I5(\TX_CRC_reg_n_0_[11] ),
.O(\TXD[0]_i_7_n_0 ));
LUT6 #(
.INIT(64'h505F3030505F3F3F))
\TXD[0]_i_8
(.I0(\TX_CRC_reg_n_0_[21] ),
.I1(\TX_CRC_reg_n_0_[23] ),
.I2(\TX_PHY_STATE_reg_n_0_[1] ),
.I3(slv1_out[1]),
.I4(\TX_PHY_STATE_reg_n_0_[0] ),
.I5(slv1_out[3]),
.O(\TXD[0]_i_8_n_0 ));
LUT6 #(
.INIT(64'h505F3030505F3F3F))
\TXD[0]_i_9
(.I0(\TX_CRC_reg_n_0_[13] ),
.I1(\TX_CRC_reg_n_0_[15] ),
.I2(\TX_PHY_STATE_reg_n_0_[1] ),
.I3(\TX_CRC_reg_n_0_[17] ),
.I4(\TX_PHY_STATE_reg_n_0_[0] ),
.I5(\TX_CRC_reg_n_0_[19] ),
.O(\TXD[0]_i_9_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair158" *)
LUT3 #(
.INIT(8'hB8))
\TXD[1]_i_1
(.I0(\TXD[1]_i_2_n_0 ),
.I1(\TXD[1]_i_3_n_0 ),
.I2(TXD_OBUF[1]),
.O(\TXD[1]_i_1_n_0 ));
LUT6 #(
.INIT(64'h505F3030505F3F3F))
\TXD[1]_i_10
(.I0(\TX_CRC_reg_n_0_[12] ),
.I1(\TX_CRC_reg_n_0_[14] ),
.I2(\TX_PHY_STATE_reg_n_0_[1] ),
.I3(\TX_CRC_reg_n_0_[16] ),
.I4(\TX_PHY_STATE_reg_n_0_[0] ),
.I5(\TX_CRC_reg_n_0_[18] ),
.O(\TXD[1]_i_10_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\TXD[1]_i_11
(.I0(p_18_in[1]),
.I1(p_0_in66_in),
.I2(\TX_PHY_STATE_reg_n_0_[1] ),
.I3(p_20_in[1]),
.I4(\TX_PHY_STATE_reg_n_0_[0] ),
.I5(p_21_in[1]),
.O(\TXD[1]_i_11_n_0 ));
LUT6 #(
.INIT(64'h5F503F3F5F503030))
\TXD[1]_i_12
(.I0(slv1_out[4]),
.I1(slv1_out[6]),
.I2(\TX_PHY_STATE_reg_n_0_[1] ),
.I3(p_16_in[1]),
.I4(\TX_PHY_STATE_reg_n_0_[0] ),
.I5(p_17_in[1]),
.O(\TXD[1]_i_12_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\TXD[1]_i_2
(.I0(\TXD[1]_i_4_n_0 ),
.I1(\TXD_reg[1]_i_5_n_0 ),
.I2(\TX_PHY_STATE_reg_n_0_[4] ),
.I3(\TXD_reg[1]_i_6_n_0 ),
.I4(\TX_PHY_STATE_reg_n_0_[3] ),
.I5(\TXD[1]_i_7_n_0 ),
.O(\TXD[1]_i_2_n_0 ));
LUT5 #(
.INIT(32'hBFFFFFFE))
\TXD[1]_i_3
(.I0(\TX_PHY_STATE_reg_n_0_[0] ),
.I1(\TX_PHY_STATE_reg_n_0_[3] ),
.I2(\TX_PHY_STATE_reg_n_0_[4] ),
.I3(\TX_PHY_STATE_reg_n_0_[1] ),
.I4(\TX_PHY_STATE_reg_n_0_[2] ),
.O(\TXD[1]_i_3_n_0 ));
LUT5 #(
.INIT(32'h47FF4700))
\TXD[1]_i_4
(.I0(\TX_CRC_reg_n_0_[0] ),
.I1(\TX_PHY_STATE_reg_n_0_[0] ),
.I2(p_1_in128_in),
.I3(\TX_PHY_STATE_reg_n_0_[2] ),
.I4(\TXD[1]_i_8_n_0 ),
.O(\TXD[1]_i_4_n_0 ));
LUT5 #(
.INIT(32'hA8882808))
\TXD[1]_i_7
(.I0(\TX_PHY_STATE_reg_n_0_[2] ),
.I1(\TX_PHY_STATE_reg_n_0_[0] ),
.I2(\TX_PHY_STATE_reg_n_0_[1] ),
.I3(p_0_in167_in),
.I4(p_22_in[1]),
.O(\TXD[1]_i_7_n_0 ));
LUT6 #(
.INIT(64'h505F3030505F3F3F))
\TXD[1]_i_8
(.I0(p_1_in132_in),
.I1(p_1_in135_in),
.I2(\TX_PHY_STATE_reg_n_0_[1] ),
.I3(\TX_CRC_reg_n_0_[8] ),
.I4(\TX_PHY_STATE_reg_n_0_[0] ),
.I5(\TX_CRC_reg_n_0_[10] ),
.O(\TXD[1]_i_8_n_0 ));
LUT6 #(
.INIT(64'h505F3030505F3F3F))
\TXD[1]_i_9
(.I0(\TX_CRC_reg_n_0_[20] ),
.I1(\TX_CRC_reg_n_0_[22] ),
.I2(\TX_PHY_STATE_reg_n_0_[1] ),
.I3(slv1_out[0]),
.I4(\TX_PHY_STATE_reg_n_0_[0] ),
.I5(slv1_out[2]),
.O(\TXD[1]_i_9_n_0 ));
FDRE \TXD_reg[0]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(\TXD[0]_i_1_n_0 ),
.Q(TXD_OBUF[0]),
.R(INTERNAL_RST_reg));
MUXF7 \TXD_reg[0]_i_4
(.I0(\TXD[0]_i_8_n_0 ),
.I1(\TXD[0]_i_9_n_0 ),
.O(\TXD_reg[0]_i_4_n_0 ),
.S(\TX_PHY_STATE_reg_n_0_[2] ));
MUXF7 \TXD_reg[0]_i_5
(.I0(\TXD[0]_i_10_n_0 ),
.I1(\TXD[0]_i_11_n_0 ),
.O(\TXD_reg[0]_i_5_n_0 ),
.S(\TX_PHY_STATE_reg_n_0_[2] ));
FDRE \TXD_reg[1]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(\TXD[1]_i_1_n_0 ),
.Q(TXD_OBUF[1]),
.R(INTERNAL_RST_reg));
MUXF7 \TXD_reg[1]_i_5
(.I0(\TXD[1]_i_9_n_0 ),
.I1(\TXD[1]_i_10_n_0 ),
.O(\TXD_reg[1]_i_5_n_0 ),
.S(\TX_PHY_STATE_reg_n_0_[2] ));
MUXF7 \TXD_reg[1]_i_6
(.I0(\TXD[1]_i_11_n_0 ),
.I1(\TXD[1]_i_12_n_0 ),
.O(\TXD_reg[1]_i_6_n_0 ),
.S(\TX_PHY_STATE_reg_n_0_[2] ));
LUT6 #(
.INIT(64'h7F7FFFFF00000100))
TXEN_i_1
(.I0(\TX_PHY_STATE_reg_n_0_[4] ),
.I1(\TX_PHY_STATE_reg_n_0_[3] ),
.I2(\TX_PHY_STATE_reg_n_0_[2] ),
.I3(\TX_PHY_STATE_reg_n_0_[0] ),
.I4(\TX_PHY_STATE_reg_n_0_[1] ),
.I5(TXEN_OBUF),
.O(TXEN_i_1_n_0));
FDRE TXEN_reg
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(TXEN_i_1_n_0),
.Q(TXEN_OBUF),
.R(INTERNAL_RST_reg));
LUT6 #(
.INIT(64'h8BB8744774478BB8))
\TX_CRC[0]_i_1
(.I0(\TX_CRC[12]_i_3_n_0 ),
.I1(\TX_PHY_STATE_reg_n_0_[2] ),
.I2(p_0_in167_in),
.I3(p_20_in[1]),
.I4(slv1_out[6]),
.I5(slv1_out[0]),
.O(\TX_CRC[0]_i_1_n_0 ));
LUT5 #(
.INIT(32'h96696996))
\TX_CRC[10]_i_2
(.I0(p_21_in[1]),
.I1(p_20_in[1]),
.I2(\TX_CRC[10]_i_4_n_0 ),
.I3(p_21_in[0]),
.I4(p_22_in[0]),
.O(NEXTCRC32_D80189_out));
LUT5 #(
.INIT(32'h96696996))
\TX_CRC[10]_i_3
(.I0(slv1_out[2]),
.I1(slv1_out[3]),
.I2(p_18_in[0]),
.I3(slv1_out[0]),
.I4(\TX_CRC[10]_i_5_n_0 ),
.O(\TX_CRC[10]_i_3_n_0 ));
LUT5 #(
.INIT(32'h96696996))
\TX_CRC[10]_i_4
(.I0(p_1_in128_in),
.I1(slv1_out[5]),
.I2(slv1_out[0]),
.I3(slv1_out[3]),
.I4(slv1_out[2]),
.O(\TX_CRC[10]_i_4_n_0 ));
LUT5 #(
.INIT(32'h96696996))
\TX_CRC[10]_i_5
(.I0(slv1_out[5]),
.I1(p_1_in128_in),
.I2(p_16_in[1]),
.I3(p_17_in[1]),
.I4(p_17_in[0]),
.O(\TX_CRC[10]_i_5_n_0 ));
LUT6 #(
.INIT(64'hF0660F990F99F066))
\TX_CRC[11]_i_1
(.I0(p_21_in[0]),
.I1(\TX_CRC[11]_i_2_n_0 ),
.I2(\TX_CRC[11]_i_3_n_0 ),
.I3(\TX_PHY_STATE_reg_n_0_[2] ),
.I4(p_1_in130_in),
.I5(slv1_out[4]),
.O(\TX_CRC[11]_i_1_n_0 ));
LUT6 #(
.INIT(64'h6996966996696996))
\TX_CRC[11]_i_2
(.I0(p_22_in[1]),
.I1(p_20_in[1]),
.I2(slv1_out[0]),
.I3(slv1_out[1]),
.I4(slv1_out[3]),
.I5(p_20_in[0]),
.O(\TX_CRC[11]_i_2_n_0 ));
LUT6 #(
.INIT(64'h6996966996696996))
\TX_CRC[11]_i_3
(.I0(p_16_in[1]),
.I1(p_17_in[0]),
.I2(slv1_out[0]),
.I3(p_16_in[0]),
.I4(slv1_out[1]),
.I5(\TX_CRC[11]_i_4_n_0 ),
.O(\TX_CRC[11]_i_3_n_0 ));
LUT2 #(
.INIT(4'h6))
\TX_CRC[11]_i_4
(.I0(slv1_out[3]),
.I1(p_18_in[1]),
.O(\TX_CRC[11]_i_4_n_0 ));
LUT6 #(
.INIT(64'h960096FF96FF9600))
\TX_CRC[12]_i_1
(.I0(\TX_CRC[12]_i_2_n_0 ),
.I1(\TX_CRC[12]_i_3_n_0 ),
.I2(\TX_CRC[12]_i_4_n_0 ),
.I3(\TX_PHY_STATE_reg_n_0_[2] ),
.I4(\TX_CRC[12]_i_5_n_0 ),
.I5(\TX_CRC[12]_i_6_n_0 ),
.O(\TX_CRC[12]_i_1_n_0 ));
LUT2 #(
.INIT(4'h6))
\TX_CRC[12]_i_2
(.I0(p_18_in[0]),
.I1(p_16_in[0]),
.O(\TX_CRC[12]_i_2_n_0 ));
LUT2 #(
.INIT(4'h6))
\TX_CRC[12]_i_3
(.I0(p_16_in[1]),
.I1(p_0_in66_in),
.O(\TX_CRC[12]_i_3_n_0 ));
LUT5 #(
.INIT(32'h96696996))
\TX_CRC[12]_i_4
(.I0(p_17_in[1]),
.I1(p_1_in132_in),
.I2(slv1_out[5]),
.I3(p_18_in[1]),
.I4(\TX_CRC[12]_i_7_n_0 ),
.O(\TX_CRC[12]_i_4_n_0 ));
LUT2 #(
.INIT(4'h6))
\TX_CRC[12]_i_5
(.I0(p_22_in[0]),
.I1(p_20_in[0]),
.O(\TX_CRC[12]_i_5_n_0 ));
LUT6 #(
.INIT(64'h6996966996696996))
\TX_CRC[12]_i_6
(.I0(\TX_CRC[2]_i_4_n_0 ),
.I1(p_20_in[1]),
.I2(\TX_CRC[12]_i_7_n_0 ),
.I3(slv1_out[5]),
.I4(p_1_in132_in),
.I5(p_22_in[1]),
.O(\TX_CRC[12]_i_6_n_0 ));
LUT5 #(
.INIT(32'h96696996))
\TX_CRC[12]_i_7
(.I0(slv1_out[6]),
.I1(slv1_out[2]),
.I2(slv1_out[0]),
.I3(slv1_out[1]),
.I4(slv1_out[4]),
.O(\TX_CRC[12]_i_7_n_0 ));
LUT6 #(
.INIT(64'h6996966996696996))
\TX_CRC[13]_i_2
(.I0(\TX_CRC[2]_i_4_n_0 ),
.I1(p_20_in[0]),
.I2(p_22_in[0]),
.I3(\TX_CRC[13]_i_4_n_0 ),
.I4(p_21_in[0]),
.I5(TX_MEMORY_reg_n_59),
.O(NEXTCRC32_D80195_out));
LUT6 #(
.INIT(64'h6996966996696996))
\TX_CRC[13]_i_3
(.I0(\TX_CRC[13]_i_5_n_0 ),
.I1(TX_MEMORY_reg_n_67),
.I2(p_18_in[0]),
.I3(\TX_CRC[13]_i_4_n_0 ),
.I4(p_0_in66_in),
.I5(p_16_in[0]),
.O(\TX_CRC[13]_i_3_n_0 ));
LUT5 #(
.INIT(32'h96696996))
\TX_CRC[13]_i_4
(.I0(\TX_CRC[3]_i_4_n_0 ),
.I1(slv1_out[1]),
.I2(slv1_out[5]),
.I3(slv1_out[6]),
.I4(p_1_in133_in),
.O(\TX_CRC[13]_i_4_n_0 ));
LUT2 #(
.INIT(4'h6))
\TX_CRC[13]_i_5
(.I0(p_17_in[0]),
.I1(p_17_in[1]),
.O(\TX_CRC[13]_i_5_n_0 ));
LUT6 #(
.INIT(64'h6996966996696996))
\TX_CRC[14]_i_2
(.I0(p_21_in[1]),
.I1(p_0_in167_in),
.I2(p_21_in[0]),
.I3(\TX_CRC[14]_i_4_n_0 ),
.I4(TX_MEMORY_reg_n_59),
.I5(p_22_in[1]),
.O(\TX_CRC[14]_i_2_n_0 ));
LUT6 #(
.INIT(64'h6996966996696996))
\TX_CRC[14]_i_3
(.I0(p_18_in[1]),
.I1(slv1_out[3]),
.I2(p_17_in[1]),
.I3(\TX_CRC[14]_i_5_n_0 ),
.I4(TX_MEMORY_reg_n_67),
.I5(p_0_in66_in),
.O(\TX_CRC[14]_i_3_n_0 ));
LUT6 #(
.INIT(64'h6996966996696996))
\TX_CRC[14]_i_4
(.I0(p_1_in135_in),
.I1(slv1_out[7]),
.I2(slv1_out[4]),
.I3(slv1_out[3]),
.I4(slv1_out[6]),
.I5(slv1_out[2]),
.O(\TX_CRC[14]_i_4_n_0 ));
LUT6 #(
.INIT(64'h6996966996696996))
\TX_CRC[14]_i_5
(.I0(p_17_in[0]),
.I1(slv1_out[2]),
.I2(slv1_out[6]),
.I3(slv1_out[4]),
.I4(slv1_out[7]),
.I5(p_1_in135_in),
.O(\TX_CRC[14]_i_5_n_0 ));
LUT6 #(
.INIT(64'h9F90606F909F6F60))
\TX_CRC[15]_i_1
(.I0(\TX_CRC[15]_i_2_n_0 ),
.I1(\TX_CRC[15]_i_3_n_0 ),
.I2(\TX_PHY_STATE_reg_n_0_[2] ),
.I3(\TX_CRC[15]_i_4_n_0 ),
.I4(slv1_out[3]),
.I5(\TX_CRC[15]_i_5_n_0 ),
.O(\TX_CRC[15]_i_1_n_0 ));
LUT2 #(
.INIT(4'h6))
\TX_CRC[15]_i_2
(.I0(p_18_in[1]),
.I1(slv1_out[4]),
.O(\TX_CRC[15]_i_2_n_0 ));
LUT6 #(
.INIT(64'h6996966996696996))
\TX_CRC[15]_i_3
(.I0(TX_MEMORY_reg_n_67),
.I1(p_17_in[0]),
.I2(slv1_out[5]),
.I3(p_18_in[0]),
.I4(slv1_out[7]),
.I5(p_1_in136_in),
.O(\TX_CRC[15]_i_3_n_0 ));
LUT2 #(
.INIT(4'h6))
\TX_CRC[15]_i_4
(.I0(slv1_out[4]),
.I1(p_22_in[1]),
.O(\TX_CRC[15]_i_4_n_0 ));
LUT6 #(
.INIT(64'h6996966996696996))
\TX_CRC[15]_i_5
(.I0(p_21_in[0]),
.I1(p_22_in[0]),
.I2(slv1_out[5]),
.I3(TX_MEMORY_reg_n_59),
.I4(slv1_out[7]),
.I5(p_1_in136_in),
.O(\TX_CRC[15]_i_5_n_0 ));
LUT6 #(
.INIT(64'h9F90606F909F6F60))
\TX_CRC[16]_i_1
(.I0(p_18_in[1]),
.I1(\TX_CRC[16]_i_2_n_0 ),
.I2(\TX_PHY_STATE_reg_n_0_[2] ),
.I3(slv1_out[4]),
.I4(slv1_out[0]),
.I5(\TX_CRC[16]_i_3_n_0 ),
.O(\TX_CRC[16]_i_1_n_0 ));
LUT5 #(
.INIT(32'h96696996))
\TX_CRC[16]_i_2
(.I0(p_18_in[0]),
.I1(slv1_out[4]),
.I2(slv1_out[5]),
.I3(\TX_CRC_reg_n_0_[8] ),
.I4(p_16_in[1]),
.O(\TX_CRC[16]_i_2_n_0 ));
LUT5 #(
.INIT(32'h96696996))
\TX_CRC[16]_i_3
(.I0(p_20_in[1]),
.I1(p_22_in[1]),
.I2(p_22_in[0]),
.I3(slv1_out[5]),
.I4(\TX_CRC_reg_n_0_[8] ),
.O(\TX_CRC[16]_i_3_n_0 ));
LUT6 #(
.INIT(64'h6996966996696996))
\TX_CRC[17]_i_2
(.I0(slv1_out[1]),
.I1(p_0_in167_in),
.I2(p_22_in[0]),
.I3(slv1_out[5]),
.I4(p_202_in),
.I5(p_20_in[0]),
.O(NEXTCRC32_D80203_out));
LUT6 #(
.INIT(64'h6996966996696996))
\TX_CRC[17]_i_3
(.I0(\TX_CRC[17]_i_5_n_0 ),
.I1(slv1_out[6]),
.I2(\TX_CRC_reg_n_0_[9] ),
.I3(slv1_out[5]),
.I4(slv1_out[1]),
.I5(p_18_in[0]),
.O(\TX_CRC[17]_i_3_n_0 ));
LUT2 #(
.INIT(4'h6))
\TX_CRC[17]_i_4
(.I0(slv1_out[6]),
.I1(\TX_CRC_reg_n_0_[9] ),
.O(p_202_in));
LUT2 #(
.INIT(4'h6))
\TX_CRC[17]_i_5
(.I0(p_0_in66_in),
.I1(p_16_in[0]),
.O(\TX_CRC[17]_i_5_n_0 ));
LUT6 #(
.INIT(64'h6996966996696996))
\TX_CRC[18]_i_2
(.I0(slv1_out[2]),
.I1(\TX_CRC[2]_i_4_n_0 ),
.I2(slv1_out[6]),
.I3(TX_MEMORY_reg_n_59),
.I4(\TX_CRC_reg_n_0_[10] ),
.I5(slv1_out[7]),
.O(\TX_CRC[18]_i_2_n_0 ));
LUT6 #(
.INIT(64'h6996966996696996))
\TX_CRC[18]_i_3
(.I0(\TX_CRC[29]_i_5_n_0 ),
.I1(slv1_out[7]),
.I2(\TX_CRC_reg_n_0_[10] ),
.I3(slv1_out[6]),
.I4(slv1_out[2]),
.I5(p_17_in[1]),
.O(\TX_CRC[18]_i_3_n_0 ));
LUT6 #(
.INIT(64'h9F90909F606F6F60))
\TX_CRC[19]_i_1
(.I0(TX_MEMORY_reg_n_67),
.I1(p_17_in[0]),
.I2(\TX_PHY_STATE_reg_n_0_[2] ),
.I3(TX_MEMORY_reg_n_59),
.I4(p_21_in[0]),
.I5(\TX_CRC[19]_i_2_n_0 ),
.O(\TX_CRC[19]_i_1_n_0 ));
LUT3 #(
.INIT(8'h96))
\TX_CRC[19]_i_2
(.I0(\TX_CRC_reg_n_0_[11] ),
.I1(slv1_out[7]),
.I2(slv1_out[3]),
.O(\TX_CRC[19]_i_2_n_0 ));
LUT6 #(
.INIT(64'h6996966996696996))
\TX_CRC[1]_i_2
(.I0(p_0_in167_in),
.I1(p_20_in[0]),
.I2(p_20_in[1]),
.I3(\TX_CRC[24]_i_4_n_0 ),
.I4(TX_MEMORY_reg_n_59),
.I5(p_168_in),
.O(\TX_CRC[1]_i_2_n_0 ));
LUT5 #(
.INIT(32'h96696996))
\TX_CRC[1]_i_3
(.I0(\TX_CRC[1]_i_5_n_0 ),
.I1(slv1_out[1]),
.I2(slv1_out[7]),
.I3(TX_MEMORY_reg_n_67),
.I4(slv1_out[0]),
.O(NEXTCRC32_D8070_out));
LUT2 #(
.INIT(4'h6))
\TX_CRC[1]_i_4
(.I0(slv1_out[0]),
.I1(slv1_out[6]),
.O(p_168_in));
LUT4 #(
.INIT(16'h6996))
\TX_CRC[1]_i_5
(.I0(p_16_in[0]),
.I1(slv1_out[6]),
.I2(p_0_in66_in),
.I3(p_16_in[1]),
.O(\TX_CRC[1]_i_5_n_0 ));
LUT5 #(
.INIT(32'hB84747B8))
\TX_CRC[20]_i_1
(.I0(p_18_in[1]),
.I1(\TX_PHY_STATE_reg_n_0_[2] ),
.I2(p_22_in[1]),
.I3(slv1_out[4]),
.I4(\TX_CRC_reg_n_0_[12] ),
.O(\TX_CRC[20]_i_1_n_0 ));
LUT5 #(
.INIT(32'hB84747B8))
\TX_CRC[21]_i_1
(.I0(p_18_in[0]),
.I1(\TX_PHY_STATE_reg_n_0_[2] ),
.I2(p_22_in[0]),
.I3(\TX_CRC_reg_n_0_[13] ),
.I4(slv1_out[5]),
.O(\TX_CRC[21]_i_1_n_0 ));
LUT5 #(
.INIT(32'hB84747B8))
\TX_CRC[22]_i_1
(.I0(p_16_in[1]),
.I1(\TX_PHY_STATE_reg_n_0_[2] ),
.I2(p_20_in[1]),
.I3(\TX_CRC_reg_n_0_[14] ),
.I4(slv1_out[0]),
.O(\TX_CRC[22]_i_1_n_0 ));
LUT6 #(
.INIT(64'h6996966996696996))
\TX_CRC[23]_i_2
(.I0(p_20_in[1]),
.I1(slv1_out[0]),
.I2(p_20_in[0]),
.I3(p_0_in167_in),
.I4(p_214_in),
.I5(slv1_out[6]),
.O(\TX_CRC[23]_i_2_n_0 ));
LUT6 #(
.INIT(64'h6996966996696996))
\TX_CRC[23]_i_3
(.I0(\TX_CRC[12]_i_3_n_0 ),
.I1(slv1_out[6]),
.I2(p_16_in[0]),
.I3(slv1_out[0]),
.I4(slv1_out[1]),
.I5(\TX_CRC_reg_n_0_[15] ),
.O(NEXTCRC32_D80108_out));
LUT2 #(
.INIT(4'h6))
\TX_CRC[23]_i_4
(.I0(slv1_out[1]),
.I1(\TX_CRC_reg_n_0_[15] ),
.O(p_214_in));
LUT6 #(
.INIT(64'h6996966996696996))
\TX_CRC[24]_i_2
(.I0(\TX_CRC[24]_i_4_n_0 ),
.I1(TX_MEMORY_reg_n_59),
.I2(slv1_out[2]),
.I3(\TX_CRC_reg_n_0_[16] ),
.I4(p_20_in[0]),
.I5(p_21_in[1]),
.O(NEXTCRC32_D80217_out));
LUT6 #(
.INIT(64'h6996966996696996))
\TX_CRC[24]_i_3
(.I0(TX_MEMORY_reg_n_67),
.I1(p_16_in[0]),
.I2(\TX_CRC_reg_n_0_[16] ),
.I3(slv1_out[2]),
.I4(slv1_out[7]),
.I5(\TX_CRC[24]_i_5_n_0 ),
.O(\TX_CRC[24]_i_3_n_0 ));
LUT2 #(
.INIT(4'h6))
\TX_CRC[24]_i_4
(.I0(slv1_out[7]),
.I1(slv1_out[1]),
.O(\TX_CRC[24]_i_4_n_0 ));
LUT2 #(
.INIT(4'h6))
\TX_CRC[24]_i_5
(.I0(slv1_out[1]),
.I1(p_17_in[1]),
.O(\TX_CRC[24]_i_5_n_0 ));
LUT5 #(
.INIT(32'h96696996))
\TX_CRC[25]_i_2
(.I0(slv1_out[3]),
.I1(\TX_CRC_reg_n_0_[17] ),
.I2(slv1_out[2]),
.I3(p_21_in[1]),
.I4(p_21_in[0]),
.O(\TX_CRC[25]_i_2_n_0 ));
LUT5 #(
.INIT(32'h96696996))
\TX_CRC[25]_i_3
(.I0(slv1_out[2]),
.I1(p_17_in[1]),
.I2(slv1_out[3]),
.I3(\TX_CRC_reg_n_0_[17] ),
.I4(p_17_in[0]),
.O(\TX_CRC[25]_i_3_n_0 ));
LUT6 #(
.INIT(64'h6996FFFF69960000))
\TX_CRC[26]_i_1
(.I0(p_16_in[1]),
.I1(\TX_CRC[26]_i_2_n_0 ),
.I2(p_0_in66_in),
.I3(p_17_in[0]),
.I4(\TX_PHY_STATE_reg_n_0_[2] ),
.I5(\TX_CRC[26]_i_3_n_0 ),
.O(\TX_CRC[26]_i_1_n_0 ));
LUT6 #(
.INIT(64'h6996966996696996))
\TX_CRC[26]_i_2
(.I0(p_18_in[1]),
.I1(slv1_out[6]),
.I2(slv1_out[3]),
.I3(slv1_out[0]),
.I4(\TX_CRC_reg_n_0_[18] ),
.I5(slv1_out[4]),
.O(\TX_CRC[26]_i_2_n_0 ));
LUT4 #(
.INIT(16'h6996))
\TX_CRC[26]_i_3
(.I0(p_0_in167_in),
.I1(p_20_in[1]),
.I2(\TX_CRC[26]_i_4_n_0 ),
.I3(p_22_in[1]),
.O(\TX_CRC[26]_i_3_n_0 ));
LUT6 #(
.INIT(64'h6996966996696996))
\TX_CRC[26]_i_4
(.I0(p_21_in[0]),
.I1(slv1_out[6]),
.I2(slv1_out[3]),
.I3(slv1_out[0]),
.I4(\TX_CRC_reg_n_0_[18] ),
.I5(slv1_out[4]),
.O(\TX_CRC[26]_i_4_n_0 ));
LUT6 #(
.INIT(64'h6996966996696996))
\TX_CRC[27]_i_2
(.I0(p_22_in[1]),
.I1(slv1_out[1]),
.I2(\TX_CRC[12]_i_5_n_0 ),
.I3(\TX_CRC[27]_i_4_n_0 ),
.I4(p_222_in),
.I5(TX_MEMORY_reg_n_59),
.O(\TX_CRC[27]_i_2_n_0 ));
LUT6 #(
.INIT(64'h6996966996696996))
\TX_CRC[27]_i_3
(.I0(slv1_out[1]),
.I1(\TX_CRC[12]_i_2_n_0 ),
.I2(p_18_in[1]),
.I3(\TX_CRC[27]_i_4_n_0 ),
.I4(TX_MEMORY_reg_n_67),
.I5(p_222_in),
.O(\TX_CRC[27]_i_3_n_0 ));
LUT2 #(
.INIT(4'h6))
\TX_CRC[27]_i_4
(.I0(slv1_out[7]),
.I1(slv1_out[4]),
.O(\TX_CRC[27]_i_4_n_0 ));
LUT2 #(
.INIT(4'h6))
\TX_CRC[27]_i_5
(.I0(slv1_out[5]),
.I1(\TX_CRC_reg_n_0_[19] ),
.O(p_222_in));
LUT6 #(
.INIT(64'h6996966996696996))
\TX_CRC[28]_i_2
(.I0(slv1_out[2]),
.I1(p_0_in167_in),
.I2(p_22_in[0]),
.I3(slv1_out[5]),
.I4(p_224_in),
.I5(p_21_in[1]),
.O(\TX_CRC[28]_i_2_n_0 ));
LUT6 #(
.INIT(64'h6996966996696996))
\TX_CRC[28]_i_3
(.I0(slv1_out[2]),
.I1(slv1_out[5]),
.I2(p_18_in[0]),
.I3(p_17_in[1]),
.I4(p_0_in66_in),
.I5(p_224_in),
.O(\TX_CRC[28]_i_3_n_0 ));
LUT2 #(
.INIT(4'h6))
\TX_CRC[28]_i_4
(.I0(slv1_out[6]),
.I1(\TX_CRC_reg_n_0_[20] ),
.O(p_224_in));
LUT6 #(
.INIT(64'h6996966996696996))
\TX_CRC[29]_i_2
(.I0(\TX_CRC[29]_i_4_n_0 ),
.I1(p_0_in167_in),
.I2(p_21_in[0]),
.I3(\TX_CRC_reg_n_0_[21] ),
.I4(slv1_out[7]),
.I5(TX_MEMORY_reg_n_59),
.O(\TX_CRC[29]_i_2_n_0 ));
LUT6 #(
.INIT(64'h6996966996696996))
\TX_CRC[29]_i_3
(.I0(slv1_out[6]),
.I1(\TX_CRC[29]_i_5_n_0 ),
.I2(slv1_out[3]),
.I3(p_17_in[0]),
.I4(\TX_CRC_reg_n_0_[21] ),
.I5(slv1_out[7]),
.O(\TX_CRC[29]_i_3_n_0 ));
LUT2 #(
.INIT(4'h6))
\TX_CRC[29]_i_4
(.I0(slv1_out[3]),
.I1(slv1_out[6]),
.O(\TX_CRC[29]_i_4_n_0 ));
LUT2 #(
.INIT(4'h6))
\TX_CRC[29]_i_5
(.I0(TX_MEMORY_reg_n_67),
.I1(p_0_in66_in),
.O(\TX_CRC[29]_i_5_n_0 ));
LUT6 #(
.INIT(64'h4B78784B784B4B78))
\TX_CRC[2]_i_1
(.I0(\TX_CRC[2]_i_2_n_0 ),
.I1(\TX_PHY_STATE_reg_n_0_[2] ),
.I2(slv1_out[0]),
.I3(\TX_CRC[2]_i_3_n_0 ),
.I4(p_20_in[0]),
.I5(\TX_CRC[2]_i_4_n_0 ),
.O(\TX_CRC[2]_i_1_n_0 ));
LUT6 #(
.INIT(64'h6996966996696996))
\TX_CRC[2]_i_2
(.I0(p_0_in66_in),
.I1(p_16_in[0]),
.I2(TX_MEMORY_reg_n_67),
.I3(\TX_CRC[2]_i_5_n_0 ),
.I4(p_16_in[1]),
.I5(p_17_in[1]),
.O(\TX_CRC[2]_i_2_n_0 ));
LUT6 #(
.INIT(64'h6996966996696996))
\TX_CRC[2]_i_3
(.I0(p_20_in[1]),
.I1(TX_MEMORY_reg_n_59),
.I2(slv1_out[2]),
.I3(slv1_out[1]),
.I4(slv1_out[7]),
.I5(slv1_out[6]),
.O(\TX_CRC[2]_i_3_n_0 ));
LUT2 #(
.INIT(4'h6))
\TX_CRC[2]_i_4
(.I0(p_0_in167_in),
.I1(p_21_in[1]),
.O(\TX_CRC[2]_i_4_n_0 ));
LUT4 #(
.INIT(16'h6996))
\TX_CRC[2]_i_5
(.I0(slv1_out[6]),
.I1(slv1_out[7]),
.I2(slv1_out[1]),
.I3(slv1_out[2]),
.O(\TX_CRC[2]_i_5_n_0 ));
LUT5 #(
.INIT(32'h96696996))
\TX_CRC[30]_i_2
(.I0(p_22_in[1]),
.I1(slv1_out[4]),
.I2(TX_MEMORY_reg_n_59),
.I3(slv1_out[7]),
.I4(\TX_CRC_reg_n_0_[22] ),
.O(\TX_CRC[30]_i_2_n_0 ));
LUT5 #(
.INIT(32'h96696996))
\TX_CRC[30]_i_3
(.I0(slv1_out[4]),
.I1(p_18_in[1]),
.I2(slv1_out[7]),
.I3(\TX_CRC_reg_n_0_[22] ),
.I4(TX_MEMORY_reg_n_67),
.O(\TX_CRC[30]_i_3_n_0 ));
LUT5 #(
.INIT(32'h00000008))
\TX_CRC[31]_i_1
(.I0(\TX_PHY_STATE_reg_n_0_[2] ),
.I1(\TX_PHY_STATE_reg_n_0_[0] ),
.I2(\TX_PHY_STATE_reg_n_0_[1] ),
.I3(\TX_PHY_STATE_reg_n_0_[4] ),
.I4(\TX_PHY_STATE_reg_n_0_[3] ),
.O(\TX_CRC[31]_i_1_n_0 ));
LUT5 #(
.INIT(32'h10101000))
\TX_CRC[31]_i_2
(.I0(\TX_PHY_STATE_reg_n_0_[4] ),
.I1(\TX_PHY_STATE_reg_n_0_[1] ),
.I2(\TX_PHY_STATE_reg_n_0_[0] ),
.I3(\TX_PHY_STATE_reg_n_0_[2] ),
.I4(\TX_PHY_STATE_reg_n_0_[3] ),
.O(\TX_CRC[31]_i_2_n_0 ));
LUT5 #(
.INIT(32'hB84747B8))
\TX_CRC[31]_i_3
(.I0(p_18_in[0]),
.I1(\TX_PHY_STATE_reg_n_0_[2] ),
.I2(p_22_in[0]),
.I3(\TX_CRC_reg_n_0_[23] ),
.I4(slv1_out[5]),
.O(\TX_CRC[31]_i_3_n_0 ));
LUT6 #(
.INIT(64'h6996966996696996))
\TX_CRC[3]_i_2
(.I0(p_21_in[1]),
.I1(TX_MEMORY_reg_n_59),
.I2(p_21_in[0]),
.I3(\TX_CRC[3]_i_4_n_0 ),
.I4(slv1_out[1]),
.I5(p_20_in[0]),
.O(NEXTCRC32_D80177_out));
LUT6 #(
.INIT(64'h6996966996696996))
\TX_CRC[3]_i_3
(.I0(TX_MEMORY_reg_n_67),
.I1(p_16_in[0]),
.I2(p_17_in[0]),
.I3(\TX_CRC[3]_i_4_n_0 ),
.I4(slv1_out[1]),
.I5(p_17_in[1]),
.O(\TX_CRC[3]_i_3_n_0 ));
LUT3 #(
.INIT(8'h96))
\TX_CRC[3]_i_4
(.I0(slv1_out[7]),
.I1(slv1_out[2]),
.I2(slv1_out[3]),
.O(\TX_CRC[3]_i_4_n_0 ));
LUT5 #(
.INIT(32'h96696996))
\TX_CRC[4]_i_2
(.I0(p_21_in[1]),
.I1(p_0_in167_in),
.I2(\TX_CRC[4]_i_4_n_0 ),
.I3(p_22_in[1]),
.I4(p_21_in[0]),
.O(\TX_CRC[4]_i_2_n_0 ));
LUT5 #(
.INIT(32'h96696996))
\TX_CRC[4]_i_3
(.I0(slv1_out[4]),
.I1(slv1_out[3]),
.I2(slv1_out[0]),
.I3(p_18_in[1]),
.I4(\TX_CRC[4]_i_5_n_0 ),
.O(\TX_CRC[4]_i_3_n_0 ));
LUT6 #(
.INIT(64'h6996966996696996))
\TX_CRC[4]_i_4
(.I0(p_20_in[1]),
.I1(slv1_out[2]),
.I2(slv1_out[6]),
.I3(slv1_out[3]),
.I4(slv1_out[0]),
.I5(slv1_out[4]),
.O(\TX_CRC[4]_i_4_n_0 ));
LUT6 #(
.INIT(64'h6996966996696996))
\TX_CRC[4]_i_5
(.I0(p_17_in[1]),
.I1(slv1_out[6]),
.I2(slv1_out[2]),
.I3(p_17_in[0]),
.I4(p_16_in[1]),
.I5(p_0_in66_in),
.O(\TX_CRC[4]_i_5_n_0 ));
LUT5 #(
.INIT(32'h96696996))
\TX_CRC[5]_i_2
(.I0(p_0_in167_in),
.I1(p_20_in[1]),
.I2(\TX_CRC[5]_i_4_n_0 ),
.I3(p_21_in[0]),
.I4(p_22_in[0]),
.O(NEXTCRC32_D80181_out));
LUT5 #(
.INIT(32'h96696996))
\TX_CRC[5]_i_3
(.I0(TX_MEMORY_reg_n_67),
.I1(p_17_in[0]),
.I2(p_16_in[1]),
.I3(p_0_in66_in),
.I4(\TX_CRC[5]_i_5_n_0 ),
.O(NEXTCRC32_D8074_out));
LUT6 #(
.INIT(64'h6996966996696996))
\TX_CRC[5]_i_4
(.I0(p_20_in[0]),
.I1(TX_MEMORY_reg_n_59),
.I2(\TX_CRC[5]_i_6_n_0 ),
.I3(slv1_out[1]),
.I4(\TX_CRC[27]_i_4_n_0 ),
.I5(p_22_in[1]),
.O(\TX_CRC[5]_i_4_n_0 ));
LUT6 #(
.INIT(64'h6996966996696996))
\TX_CRC[5]_i_5
(.I0(\TX_CRC[12]_i_2_n_0 ),
.I1(slv1_out[1]),
.I2(slv1_out[4]),
.I3(slv1_out[7]),
.I4(\TX_CRC[5]_i_6_n_0 ),
.I5(p_18_in[1]),
.O(\TX_CRC[5]_i_5_n_0 ));
LUT4 #(
.INIT(16'h6996))
\TX_CRC[5]_i_6
(.I0(slv1_out[0]),
.I1(slv1_out[5]),
.I2(slv1_out[6]),
.I3(slv1_out[3]),
.O(\TX_CRC[5]_i_6_n_0 ));
LUT6 #(
.INIT(64'h6996966996696996))
\TX_CRC[6]_i_2
(.I0(p_20_in[0]),
.I1(p_22_in[0]),
.I2(p_22_in[1]),
.I3(\TX_CRC[6]_i_4_n_0 ),
.I4(TX_MEMORY_reg_n_59),
.I5(\TX_CRC[2]_i_4_n_0 ),
.O(\TX_CRC[6]_i_2_n_0 ));
LUT6 #(
.INIT(64'h6996966996696996))
\TX_CRC[6]_i_3
(.I0(p_18_in[0]),
.I1(p_16_in[0]),
.I2(slv1_out[2]),
.I3(slv1_out[6]),
.I4(p_17_in[1]),
.I5(\TX_CRC[6]_i_5_n_0 ),
.O(\TX_CRC[6]_i_3_n_0 ));
LUT6 #(
.INIT(64'h6996966996696996))
\TX_CRC[6]_i_4
(.I0(slv1_out[4]),
.I1(slv1_out[7]),
.I2(slv1_out[1]),
.I3(slv1_out[5]),
.I4(slv1_out[6]),
.I5(slv1_out[2]),
.O(\TX_CRC[6]_i_4_n_0 ));
LUT6 #(
.INIT(64'h6996966996696996))
\TX_CRC[6]_i_5
(.I0(p_0_in66_in),
.I1(TX_MEMORY_reg_n_67),
.I2(\TX_CRC[27]_i_4_n_0 ),
.I3(slv1_out[5]),
.I4(slv1_out[1]),
.I5(p_18_in[1]),
.O(\TX_CRC[6]_i_5_n_0 ));
LUT6 #(
.INIT(64'h690096FF69FF9600))
\TX_CRC[7]_i_1
(.I0(slv1_out[5]),
.I1(p_18_in[0]),
.I2(\TX_CRC[7]_i_2_n_0 ),
.I3(\TX_PHY_STATE_reg_n_0_[2] ),
.I4(\TX_CRC[7]_i_3_n_0 ),
.I5(\TX_CRC[7]_i_4_n_0 ),
.O(\TX_CRC[7]_i_1_n_0 ));
LUT4 #(
.INIT(16'h6996))
\TX_CRC[7]_i_2
(.I0(TX_MEMORY_reg_n_67),
.I1(p_16_in[1]),
.I2(p_17_in[1]),
.I3(p_17_in[0]),
.O(\TX_CRC[7]_i_2_n_0 ));
LUT4 #(
.INIT(16'h6996))
\TX_CRC[7]_i_3
(.I0(slv1_out[3]),
.I1(slv1_out[2]),
.I2(slv1_out[7]),
.I3(slv1_out[0]),
.O(\TX_CRC[7]_i_3_n_0 ));
LUT6 #(
.INIT(64'h6996966996696996))
\TX_CRC[7]_i_4
(.I0(p_20_in[1]),
.I1(p_21_in[1]),
.I2(slv1_out[5]),
.I3(TX_MEMORY_reg_n_59),
.I4(p_21_in[0]),
.I5(p_22_in[0]),
.O(\TX_CRC[7]_i_4_n_0 ));
LUT6 #(
.INIT(64'hF0660F990F99F066))
\TX_CRC[8]_i_1
(.I0(p_21_in[0]),
.I1(\TX_CRC[11]_i_2_n_0 ),
.I2(\TX_CRC[11]_i_3_n_0 ),
.I3(\TX_PHY_STATE_reg_n_0_[2] ),
.I4(\TX_CRC_reg_n_0_[0] ),
.I5(slv1_out[4]),
.O(\TX_CRC[8]_i_1_n_0 ));
LUT6 #(
.INIT(64'h8BB8B88BB88B8BB8))
\TX_CRC[9]_i_1
(.I0(\TX_CRC[9]_i_2_n_0 ),
.I1(\TX_PHY_STATE_reg_n_0_[2] ),
.I2(p_22_in[1]),
.I3(slv1_out[1]),
.I4(slv1_out[4]),
.I5(\TX_CRC[9]_i_3_n_0 ),
.O(\TX_CRC[9]_i_1_n_0 ));
LUT5 #(
.INIT(32'h96696996))
\TX_CRC[9]_i_2
(.I0(p_18_in[0]),
.I1(p_16_in[0]),
.I2(slv1_out[5]),
.I3(p_1_in126_in),
.I4(\TX_CRC[9]_i_4_n_0 ),
.O(\TX_CRC[9]_i_2_n_0 ));
LUT6 #(
.INIT(64'h6996966996696996))
\TX_CRC[9]_i_3
(.I0(p_22_in[0]),
.I1(p_20_in[0]),
.I2(slv1_out[2]),
.I3(p_21_in[1]),
.I4(slv1_out[5]),
.I5(p_1_in126_in),
.O(\TX_CRC[9]_i_3_n_0 ));
LUT5 #(
.INIT(32'h96696996))
\TX_CRC[9]_i_4
(.I0(slv1_out[2]),
.I1(p_17_in[1]),
.I2(slv1_out[4]),
.I3(slv1_out[1]),
.I4(p_18_in[1]),
.O(\TX_CRC[9]_i_4_n_0 ));
FDSE \TX_CRC_reg[0]
(.C(ETH_CLK_OBUF),
.CE(\TX_CRC[31]_i_2_n_0 ),
.D(\TX_CRC[0]_i_1_n_0 ),
.Q(\TX_CRC_reg_n_0_[0] ),
.S(\TX_CRC[31]_i_1_n_0 ));
FDSE \TX_CRC_reg[10]
(.C(ETH_CLK_OBUF),
.CE(\TX_CRC[31]_i_2_n_0 ),
.D(\TX_CRC_reg[10]_i_1_n_0 ),
.Q(\TX_CRC_reg_n_0_[10] ),
.S(\TX_CRC[31]_i_1_n_0 ));
MUXF7 \TX_CRC_reg[10]_i_1
(.I0(NEXTCRC32_D80189_out),
.I1(\TX_CRC[10]_i_3_n_0 ),
.O(\TX_CRC_reg[10]_i_1_n_0 ),
.S(\TX_PHY_STATE_reg_n_0_[2] ));
FDSE \TX_CRC_reg[11]
(.C(ETH_CLK_OBUF),
.CE(\TX_CRC[31]_i_2_n_0 ),
.D(\TX_CRC[11]_i_1_n_0 ),
.Q(\TX_CRC_reg_n_0_[11] ),
.S(\TX_CRC[31]_i_1_n_0 ));
FDSE \TX_CRC_reg[12]
(.C(ETH_CLK_OBUF),
.CE(\TX_CRC[31]_i_2_n_0 ),
.D(\TX_CRC[12]_i_1_n_0 ),
.Q(\TX_CRC_reg_n_0_[12] ),
.S(\TX_CRC[31]_i_1_n_0 ));
FDSE \TX_CRC_reg[13]
(.C(ETH_CLK_OBUF),
.CE(\TX_CRC[31]_i_2_n_0 ),
.D(\TX_CRC_reg[13]_i_1_n_0 ),
.Q(\TX_CRC_reg_n_0_[13] ),
.S(\TX_CRC[31]_i_1_n_0 ));
MUXF7 \TX_CRC_reg[13]_i_1
(.I0(NEXTCRC32_D80195_out),
.I1(\TX_CRC[13]_i_3_n_0 ),
.O(\TX_CRC_reg[13]_i_1_n_0 ),
.S(\TX_PHY_STATE_reg_n_0_[2] ));
FDSE \TX_CRC_reg[14]
(.C(ETH_CLK_OBUF),
.CE(\TX_CRC[31]_i_2_n_0 ),
.D(\TX_CRC_reg[14]_i_1_n_0 ),
.Q(\TX_CRC_reg_n_0_[14] ),
.S(\TX_CRC[31]_i_1_n_0 ));
MUXF7 \TX_CRC_reg[14]_i_1
(.I0(\TX_CRC[14]_i_2_n_0 ),
.I1(\TX_CRC[14]_i_3_n_0 ),
.O(\TX_CRC_reg[14]_i_1_n_0 ),
.S(\TX_PHY_STATE_reg_n_0_[2] ));
FDSE \TX_CRC_reg[15]
(.C(ETH_CLK_OBUF),
.CE(\TX_CRC[31]_i_2_n_0 ),
.D(\TX_CRC[15]_i_1_n_0 ),
.Q(\TX_CRC_reg_n_0_[15] ),
.S(\TX_CRC[31]_i_1_n_0 ));
FDSE \TX_CRC_reg[16]
(.C(ETH_CLK_OBUF),
.CE(\TX_CRC[31]_i_2_n_0 ),
.D(\TX_CRC[16]_i_1_n_0 ),
.Q(\TX_CRC_reg_n_0_[16] ),
.S(\TX_CRC[31]_i_1_n_0 ));
FDSE \TX_CRC_reg[17]
(.C(ETH_CLK_OBUF),
.CE(\TX_CRC[31]_i_2_n_0 ),
.D(\TX_CRC_reg[17]_i_1_n_0 ),
.Q(\TX_CRC_reg_n_0_[17] ),
.S(\TX_CRC[31]_i_1_n_0 ));
MUXF7 \TX_CRC_reg[17]_i_1
(.I0(NEXTCRC32_D80203_out),
.I1(\TX_CRC[17]_i_3_n_0 ),
.O(\TX_CRC_reg[17]_i_1_n_0 ),
.S(\TX_PHY_STATE_reg_n_0_[2] ));
FDSE \TX_CRC_reg[18]
(.C(ETH_CLK_OBUF),
.CE(\TX_CRC[31]_i_2_n_0 ),
.D(\TX_CRC_reg[18]_i_1_n_0 ),
.Q(\TX_CRC_reg_n_0_[18] ),
.S(\TX_CRC[31]_i_1_n_0 ));
MUXF7 \TX_CRC_reg[18]_i_1
(.I0(\TX_CRC[18]_i_2_n_0 ),
.I1(\TX_CRC[18]_i_3_n_0 ),
.O(\TX_CRC_reg[18]_i_1_n_0 ),
.S(\TX_PHY_STATE_reg_n_0_[2] ));
FDSE \TX_CRC_reg[19]
(.C(ETH_CLK_OBUF),
.CE(\TX_CRC[31]_i_2_n_0 ),
.D(\TX_CRC[19]_i_1_n_0 ),
.Q(\TX_CRC_reg_n_0_[19] ),
.S(\TX_CRC[31]_i_1_n_0 ));
FDSE \TX_CRC_reg[1]
(.C(ETH_CLK_OBUF),
.CE(\TX_CRC[31]_i_2_n_0 ),
.D(\TX_CRC_reg[1]_i_1_n_0 ),
.Q(p_1_in126_in),
.S(\TX_CRC[31]_i_1_n_0 ));
MUXF7 \TX_CRC_reg[1]_i_1
(.I0(\TX_CRC[1]_i_2_n_0 ),
.I1(NEXTCRC32_D8070_out),
.O(\TX_CRC_reg[1]_i_1_n_0 ),
.S(\TX_PHY_STATE_reg_n_0_[2] ));
FDSE \TX_CRC_reg[20]
(.C(ETH_CLK_OBUF),
.CE(\TX_CRC[31]_i_2_n_0 ),
.D(\TX_CRC[20]_i_1_n_0 ),
.Q(\TX_CRC_reg_n_0_[20] ),
.S(\TX_CRC[31]_i_1_n_0 ));
FDSE \TX_CRC_reg[21]
(.C(ETH_CLK_OBUF),
.CE(\TX_CRC[31]_i_2_n_0 ),
.D(\TX_CRC[21]_i_1_n_0 ),
.Q(\TX_CRC_reg_n_0_[21] ),
.S(\TX_CRC[31]_i_1_n_0 ));
FDSE \TX_CRC_reg[22]
(.C(ETH_CLK_OBUF),
.CE(\TX_CRC[31]_i_2_n_0 ),
.D(\TX_CRC[22]_i_1_n_0 ),
.Q(\TX_CRC_reg_n_0_[22] ),
.S(\TX_CRC[31]_i_1_n_0 ));
FDSE \TX_CRC_reg[23]
(.C(ETH_CLK_OBUF),
.CE(\TX_CRC[31]_i_2_n_0 ),
.D(\TX_CRC_reg[23]_i_1_n_0 ),
.Q(\TX_CRC_reg_n_0_[23] ),
.S(\TX_CRC[31]_i_1_n_0 ));
MUXF7 \TX_CRC_reg[23]_i_1
(.I0(\TX_CRC[23]_i_2_n_0 ),
.I1(NEXTCRC32_D80108_out),
.O(\TX_CRC_reg[23]_i_1_n_0 ),
.S(\TX_PHY_STATE_reg_n_0_[2] ));
FDSE \TX_CRC_reg[24]
(.C(ETH_CLK_OBUF),
.CE(\TX_CRC[31]_i_2_n_0 ),
.D(\TX_CRC_reg[24]_i_1_n_0 ),
.Q(slv1_out[0]),
.S(\TX_CRC[31]_i_1_n_0 ));
MUXF7 \TX_CRC_reg[24]_i_1
(.I0(NEXTCRC32_D80217_out),
.I1(\TX_CRC[24]_i_3_n_0 ),
.O(\TX_CRC_reg[24]_i_1_n_0 ),
.S(\TX_PHY_STATE_reg_n_0_[2] ));
FDSE \TX_CRC_reg[25]
(.C(ETH_CLK_OBUF),
.CE(\TX_CRC[31]_i_2_n_0 ),
.D(\TX_CRC_reg[25]_i_1_n_0 ),
.Q(slv1_out[1]),
.S(\TX_CRC[31]_i_1_n_0 ));
MUXF7 \TX_CRC_reg[25]_i_1
(.I0(\TX_CRC[25]_i_2_n_0 ),
.I1(\TX_CRC[25]_i_3_n_0 ),
.O(\TX_CRC_reg[25]_i_1_n_0 ),
.S(\TX_PHY_STATE_reg_n_0_[2] ));
FDSE \TX_CRC_reg[26]
(.C(ETH_CLK_OBUF),
.CE(\TX_CRC[31]_i_2_n_0 ),
.D(\TX_CRC[26]_i_1_n_0 ),
.Q(slv1_out[2]),
.S(\TX_CRC[31]_i_1_n_0 ));
FDSE \TX_CRC_reg[27]
(.C(ETH_CLK_OBUF),
.CE(\TX_CRC[31]_i_2_n_0 ),
.D(\TX_CRC_reg[27]_i_1_n_0 ),
.Q(slv1_out[3]),
.S(\TX_CRC[31]_i_1_n_0 ));
MUXF7 \TX_CRC_reg[27]_i_1
(.I0(\TX_CRC[27]_i_2_n_0 ),
.I1(\TX_CRC[27]_i_3_n_0 ),
.O(\TX_CRC_reg[27]_i_1_n_0 ),
.S(\TX_PHY_STATE_reg_n_0_[2] ));
FDSE \TX_CRC_reg[28]
(.C(ETH_CLK_OBUF),
.CE(\TX_CRC[31]_i_2_n_0 ),
.D(\TX_CRC_reg[28]_i_1_n_0 ),
.Q(slv1_out[4]),
.S(\TX_CRC[31]_i_1_n_0 ));
MUXF7 \TX_CRC_reg[28]_i_1
(.I0(\TX_CRC[28]_i_2_n_0 ),
.I1(\TX_CRC[28]_i_3_n_0 ),
.O(\TX_CRC_reg[28]_i_1_n_0 ),
.S(\TX_PHY_STATE_reg_n_0_[2] ));
FDSE \TX_CRC_reg[29]
(.C(ETH_CLK_OBUF),
.CE(\TX_CRC[31]_i_2_n_0 ),
.D(\TX_CRC_reg[29]_i_1_n_0 ),
.Q(slv1_out[5]),
.S(\TX_CRC[31]_i_1_n_0 ));
MUXF7 \TX_CRC_reg[29]_i_1
(.I0(\TX_CRC[29]_i_2_n_0 ),
.I1(\TX_CRC[29]_i_3_n_0 ),
.O(\TX_CRC_reg[29]_i_1_n_0 ),
.S(\TX_PHY_STATE_reg_n_0_[2] ));
FDSE \TX_CRC_reg[2]
(.C(ETH_CLK_OBUF),
.CE(\TX_CRC[31]_i_2_n_0 ),
.D(\TX_CRC[2]_i_1_n_0 ),
.Q(p_1_in128_in),
.S(\TX_CRC[31]_i_1_n_0 ));
FDSE \TX_CRC_reg[30]
(.C(ETH_CLK_OBUF),
.CE(\TX_CRC[31]_i_2_n_0 ),
.D(\TX_CRC_reg[30]_i_1_n_0 ),
.Q(slv1_out[6]),
.S(\TX_CRC[31]_i_1_n_0 ));
MUXF7 \TX_CRC_reg[30]_i_1
(.I0(\TX_CRC[30]_i_2_n_0 ),
.I1(\TX_CRC[30]_i_3_n_0 ),
.O(\TX_CRC_reg[30]_i_1_n_0 ),
.S(\TX_PHY_STATE_reg_n_0_[2] ));
FDSE \TX_CRC_reg[31]
(.C(ETH_CLK_OBUF),
.CE(\TX_CRC[31]_i_2_n_0 ),
.D(\TX_CRC[31]_i_3_n_0 ),
.Q(slv1_out[7]),
.S(\TX_CRC[31]_i_1_n_0 ));
FDSE \TX_CRC_reg[3]
(.C(ETH_CLK_OBUF),
.CE(\TX_CRC[31]_i_2_n_0 ),
.D(\TX_CRC_reg[3]_i_1_n_0 ),
.Q(p_1_in130_in),
.S(\TX_CRC[31]_i_1_n_0 ));
MUXF7 \TX_CRC_reg[3]_i_1
(.I0(NEXTCRC32_D80177_out),
.I1(\TX_CRC[3]_i_3_n_0 ),
.O(\TX_CRC_reg[3]_i_1_n_0 ),
.S(\TX_PHY_STATE_reg_n_0_[2] ));
FDSE \TX_CRC_reg[4]
(.C(ETH_CLK_OBUF),
.CE(\TX_CRC[31]_i_2_n_0 ),
.D(\TX_CRC_reg[4]_i_1_n_0 ),
.Q(p_1_in132_in),
.S(\TX_CRC[31]_i_1_n_0 ));
MUXF7 \TX_CRC_reg[4]_i_1
(.I0(\TX_CRC[4]_i_2_n_0 ),
.I1(\TX_CRC[4]_i_3_n_0 ),
.O(\TX_CRC_reg[4]_i_1_n_0 ),
.S(\TX_PHY_STATE_reg_n_0_[2] ));
FDSE \TX_CRC_reg[5]
(.C(ETH_CLK_OBUF),
.CE(\TX_CRC[31]_i_2_n_0 ),
.D(\TX_CRC_reg[5]_i_1_n_0 ),
.Q(p_1_in133_in),
.S(\TX_CRC[31]_i_1_n_0 ));
MUXF7 \TX_CRC_reg[5]_i_1
(.I0(NEXTCRC32_D80181_out),
.I1(NEXTCRC32_D8074_out),
.O(\TX_CRC_reg[5]_i_1_n_0 ),
.S(\TX_PHY_STATE_reg_n_0_[2] ));
FDSE \TX_CRC_reg[6]
(.C(ETH_CLK_OBUF),
.CE(\TX_CRC[31]_i_2_n_0 ),
.D(\TX_CRC_reg[6]_i_1_n_0 ),
.Q(p_1_in135_in),
.S(\TX_CRC[31]_i_1_n_0 ));
MUXF7 \TX_CRC_reg[6]_i_1
(.I0(\TX_CRC[6]_i_2_n_0 ),
.I1(\TX_CRC[6]_i_3_n_0 ),
.O(\TX_CRC_reg[6]_i_1_n_0 ),
.S(\TX_PHY_STATE_reg_n_0_[2] ));
FDSE \TX_CRC_reg[7]
(.C(ETH_CLK_OBUF),
.CE(\TX_CRC[31]_i_2_n_0 ),
.D(\TX_CRC[7]_i_1_n_0 ),
.Q(p_1_in136_in),
.S(\TX_CRC[31]_i_1_n_0 ));
FDSE \TX_CRC_reg[8]
(.C(ETH_CLK_OBUF),
.CE(\TX_CRC[31]_i_2_n_0 ),
.D(\TX_CRC[8]_i_1_n_0 ),
.Q(\TX_CRC_reg_n_0_[8] ),
.S(\TX_CRC[31]_i_1_n_0 ));
FDSE \TX_CRC_reg[9]
(.C(ETH_CLK_OBUF),
.CE(\TX_CRC[31]_i_2_n_0 ),
.D(\TX_CRC[9]_i_1_n_0 ),
.Q(\TX_CRC_reg_n_0_[9] ),
.S(\TX_CRC[31]_i_1_n_0 ));
LUT3 #(
.INIT(8'h04))
\TX_IN_COUNT[10]_i_1
(.I0(\TX_PACKET_STATE_reg_n_0_[1] ),
.I1(S_TX_ACK_reg_n_0),
.I2(\TX_PACKET_STATE_reg_n_0_[0] ),
.O(\TX_IN_COUNT[10]_i_1_n_0 ));
LUT4 #(
.INIT(16'h0444))
\TX_IN_COUNT[10]_i_2
(.I0(\TX_PACKET_STATE_reg_n_0_[1] ),
.I1(S_TX_ACK_reg_n_0),
.I2(\TX_PACKET_STATE_reg_n_0_[0] ),
.I3(\TX_PACKET_STATE_reg[1]_i_2_n_2 ),
.O(\TX_IN_COUNT[10]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair94" *)
LUT5 #(
.INIT(32'hAAAA6AAA))
\TX_IN_COUNT[10]_i_3
(.I0(TX_IN_COUNT[10]),
.I1(TX_IN_COUNT[9]),
.I2(TX_IN_COUNT[8]),
.I3(TX_IN_COUNT[7]),
.I4(\TX_IN_COUNT[10]_i_4_n_0 ),
.O(\TX_IN_COUNT[10]_i_3_n_0 ));
LUT6 #(
.INIT(64'h7FFFFFFFFFFFFFFF))
\TX_IN_COUNT[10]_i_4
(.I0(TX_IN_COUNT[5]),
.I1(TX_IN_COUNT[3]),
.I2(TX_IN_COUNT[1]),
.I3(TX_IN_COUNT[2]),
.I4(TX_IN_COUNT[4]),
.I5(TX_IN_COUNT[6]),
.O(\TX_IN_COUNT[10]_i_4_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair88" *)
LUT5 #(
.INIT(32'hFFBF0444))
\TX_IN_COUNT[1]_i_1
(.I0(\TX_PACKET_STATE_reg_n_0_[1] ),
.I1(S_TX_ACK_reg_n_0),
.I2(\TX_PACKET_STATE_reg_n_0_[0] ),
.I3(\TX_PACKET_STATE_reg[1]_i_2_n_2 ),
.I4(TX_IN_COUNT[1]),
.O(\TX_IN_COUNT[1]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFCFDFCF00002000))
\TX_IN_COUNT[2]_i_1
(.I0(TX_IN_COUNT[1]),
.I1(\TX_PACKET_STATE_reg_n_0_[1] ),
.I2(S_TX_ACK_reg_n_0),
.I3(\TX_PACKET_STATE_reg_n_0_[0] ),
.I4(\TX_PACKET_STATE_reg[1]_i_2_n_2 ),
.I5(TX_IN_COUNT[2]),
.O(\TX_IN_COUNT[2]_i_1_n_0 ));
LUT3 #(
.INIT(8'h6A))
\TX_IN_COUNT[3]_i_1
(.I0(TX_IN_COUNT[3]),
.I1(TX_IN_COUNT[2]),
.I2(TX_IN_COUNT[1]),
.O(\TX_IN_COUNT[3]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair96" *)
LUT4 #(
.INIT(16'h6AAA))
\TX_IN_COUNT[4]_i_1
(.I0(TX_IN_COUNT[4]),
.I1(TX_IN_COUNT[3]),
.I2(TX_IN_COUNT[1]),
.I3(TX_IN_COUNT[2]),
.O(\TX_IN_COUNT[4]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair96" *)
LUT5 #(
.INIT(32'h6AAAAAAA))
\TX_IN_COUNT[5]_i_1
(.I0(TX_IN_COUNT[5]),
.I1(TX_IN_COUNT[4]),
.I2(TX_IN_COUNT[2]),
.I3(TX_IN_COUNT[1]),
.I4(TX_IN_COUNT[3]),
.O(\TX_IN_COUNT[5]_i_1_n_0 ));
LUT6 #(
.INIT(64'h6AAAAAAAAAAAAAAA))
\TX_IN_COUNT[6]_i_1
(.I0(TX_IN_COUNT[6]),
.I1(TX_IN_COUNT[5]),
.I2(TX_IN_COUNT[3]),
.I3(TX_IN_COUNT[1]),
.I4(TX_IN_COUNT[2]),
.I5(TX_IN_COUNT[4]),
.O(\TX_IN_COUNT[6]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair163" *)
LUT2 #(
.INIT(4'h9))
\TX_IN_COUNT[7]_i_1
(.I0(TX_IN_COUNT[7]),
.I1(\TX_IN_COUNT[10]_i_4_n_0 ),
.O(\TX_IN_COUNT[7]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair163" *)
LUT3 #(
.INIT(8'hA6))
\TX_IN_COUNT[8]_i_1
(.I0(TX_IN_COUNT[8]),
.I1(TX_IN_COUNT[7]),
.I2(\TX_IN_COUNT[10]_i_4_n_0 ),
.O(\TX_IN_COUNT[8]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair94" *)
LUT4 #(
.INIT(16'h9AAA))
\TX_IN_COUNT[9]_i_1
(.I0(TX_IN_COUNT[9]),
.I1(\TX_IN_COUNT[10]_i_4_n_0 ),
.I2(TX_IN_COUNT[7]),
.I3(TX_IN_COUNT[8]),
.O(\TX_IN_COUNT[9]_i_1_n_0 ));
FDRE \TX_IN_COUNT_reg[10]
(.C(ETH_CLK_OBUF),
.CE(\TX_IN_COUNT[10]_i_2_n_0 ),
.D(\TX_IN_COUNT[10]_i_3_n_0 ),
.Q(TX_IN_COUNT[10]),
.R(\TX_IN_COUNT[10]_i_1_n_0 ));
FDRE \TX_IN_COUNT_reg[1]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(\TX_IN_COUNT[1]_i_1_n_0 ),
.Q(TX_IN_COUNT[1]),
.R(1'b0));
FDRE \TX_IN_COUNT_reg[2]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(\TX_IN_COUNT[2]_i_1_n_0 ),
.Q(TX_IN_COUNT[2]),
.R(1'b0));
FDRE \TX_IN_COUNT_reg[3]
(.C(ETH_CLK_OBUF),
.CE(\TX_IN_COUNT[10]_i_2_n_0 ),
.D(\TX_IN_COUNT[3]_i_1_n_0 ),
.Q(TX_IN_COUNT[3]),
.R(\TX_IN_COUNT[10]_i_1_n_0 ));
FDRE \TX_IN_COUNT_reg[4]
(.C(ETH_CLK_OBUF),
.CE(\TX_IN_COUNT[10]_i_2_n_0 ),
.D(\TX_IN_COUNT[4]_i_1_n_0 ),
.Q(TX_IN_COUNT[4]),
.R(\TX_IN_COUNT[10]_i_1_n_0 ));
FDRE \TX_IN_COUNT_reg[5]
(.C(ETH_CLK_OBUF),
.CE(\TX_IN_COUNT[10]_i_2_n_0 ),
.D(\TX_IN_COUNT[5]_i_1_n_0 ),
.Q(TX_IN_COUNT[5]),
.R(\TX_IN_COUNT[10]_i_1_n_0 ));
FDRE \TX_IN_COUNT_reg[6]
(.C(ETH_CLK_OBUF),
.CE(\TX_IN_COUNT[10]_i_2_n_0 ),
.D(\TX_IN_COUNT[6]_i_1_n_0 ),
.Q(TX_IN_COUNT[6]),
.R(\TX_IN_COUNT[10]_i_1_n_0 ));
FDRE \TX_IN_COUNT_reg[7]
(.C(ETH_CLK_OBUF),
.CE(\TX_IN_COUNT[10]_i_2_n_0 ),
.D(\TX_IN_COUNT[7]_i_1_n_0 ),
.Q(TX_IN_COUNT[7]),
.R(\TX_IN_COUNT[10]_i_1_n_0 ));
FDRE \TX_IN_COUNT_reg[8]
(.C(ETH_CLK_OBUF),
.CE(\TX_IN_COUNT[10]_i_2_n_0 ),
.D(\TX_IN_COUNT[8]_i_1_n_0 ),
.Q(TX_IN_COUNT[8]),
.R(\TX_IN_COUNT[10]_i_1_n_0 ));
FDRE \TX_IN_COUNT_reg[9]
(.C(ETH_CLK_OBUF),
.CE(\TX_IN_COUNT[10]_i_2_n_0 ),
.D(\TX_IN_COUNT[9]_i_1_n_0 ),
.Q(TX_IN_COUNT[9]),
.R(\TX_IN_COUNT[10]_i_1_n_0 ));
(* IS_CLOCK_GATED *)
(* METHODOLOGY_DRC_VIOS = "{SYNTH-6 {cell *THIS*}}" *)
(* POWER_OPTED_CE = "ENBWREN=NEW" *)
(* RTL_RAM_BITS = "16400" *)
(* RTL_RAM_NAME = "TX_MEMORY" *)
(* bram_addr_begin = "0" *)
(* bram_addr_end = "2047" *)
(* bram_slice_begin = "0" *)
(* bram_slice_end = "17" *)
RAMB36E1 #(
.DOA_REG(0),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(18),
.READ_WIDTH_B(18),
.RSTREG_PRIORITY_A("RSTREG"),
.RSTREG_PRIORITY_B("RSTREG"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("NO_CHANGE"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(18),
.WRITE_WIDTH_B(18))
TX_MEMORY_reg
(.ADDRARDADDR({1'b1,TX_WRITE_ADDRESS_DEL,1'b1,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b1,TX_READ_ADDRESS,1'b1,1'b1,1'b1,1'b1}),
.CASCADEINA(1'b1),
.CASCADEINB(1'b1),
.CASCADEOUTA(NLW_TX_MEMORY_reg_CASCADEOUTA_UNCONNECTED),
.CASCADEOUTB(NLW_TX_MEMORY_reg_CASCADEOUTB_UNCONNECTED),
.CLKARDCLK(ETH_CLK_OBUF),
.CLKBWRCLK(ETH_CLK_OBUF),
.DBITERR(NLW_TX_MEMORY_reg_DBITERR_UNCONNECTED),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO(NLW_TX_MEMORY_reg_DOADO_UNCONNECTED[31:0]),
.DOBDO({NLW_TX_MEMORY_reg_DOBDO_UNCONNECTED[31:16],p_20_in,p_21_in,p_22_in,p_0_in167_in,TX_MEMORY_reg_n_59,p_16_in,p_17_in,p_18_in,p_0_in66_in,TX_MEMORY_reg_n_67}),
.DOPADOP(NLW_TX_MEMORY_reg_DOPADOP_UNCONNECTED[3:0]),
.DOPBDOP(NLW_TX_MEMORY_reg_DOPBDOP_UNCONNECTED[3:0]),
.ECCPARITY(NLW_TX_MEMORY_reg_ECCPARITY_UNCONNECTED[7:0]),
.ENARDEN(TX_WRITE),
.ENBWREN(TX_MEMORY_reg_ENBWREN_cooolgate_en_sig_9),
.INJECTDBITERR(NLW_TX_MEMORY_reg_INJECTDBITERR_UNCONNECTED),
.INJECTSBITERR(NLW_TX_MEMORY_reg_INJECTSBITERR_UNCONNECTED),
.RDADDRECC(NLW_TX_MEMORY_reg_RDADDRECC_UNCONNECTED[8:0]),
.REGCEAREGCE(NLW_TX_MEMORY_reg_REGCEAREGCE_UNCONNECTED),
.REGCEB(NLW_TX_MEMORY_reg_REGCEB_UNCONNECTED),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(NLW_TX_MEMORY_reg_SBITERR_UNCONNECTED),
.WEA({1'b0,1'b0,1'b1,1'b1}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
LUT4 #(
.INIT(16'hff35))
TX_MEMORY_reg_ENBWREN_cooolgate_en_gate_17
(.I0(\TX_PHY_STATE_reg_n_0_[4] ),
.I1(\TX_PHY_STATE[4]_i_2_n_0 ),
.I2(\TX_PHY_STATE[4]_i_1_n_0 ),
.I3(INTERNAL_RST_reg),
.O(TX_MEMORY_reg_ENBWREN_cooolgate_en_sig_9));
(* SOFT_HLUTNM = "soft_lutpair159" *)
LUT2 #(
.INIT(4'h7))
\TX_OUT_COUNT[0]_i_1
(.I0(\TX_OUT_COUNT_reg_n_0_[0] ),
.I1(\TX_PHY_STATE_reg_n_0_[3] ),
.O(TX_OUT_COUNT0_in));
LUT6 #(
.INIT(64'h00000000AA100010))
\TX_OUT_COUNT[10]_i_1
(.I0(\TX_PHY_STATE_reg_n_0_[3] ),
.I1(\TX_PHY_STATE_reg_n_0_[2] ),
.I2(GO_SYNC),
.I3(\TX_PHY_STATE_reg_n_0_[0] ),
.I4(\TX_OUT_COUNT[10]_i_3_n_0 ),
.I5(\TX_OUT_COUNT[10]_i_4_n_0 ),
.O(\TX_OUT_COUNT[10]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair150" *)
LUT4 #(
.INIT(16'hE133))
\TX_OUT_COUNT[10]_i_2
(.I0(\TX_OUT_COUNT_reg_n_0_[9] ),
.I1(\TX_OUT_COUNT[10]_i_5_n_0 ),
.I2(\TX_OUT_COUNT_reg_n_0_[10] ),
.I3(\TX_PHY_STATE_reg_n_0_[3] ),
.O(\TX_OUT_COUNT[10]_i_2_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFFFFF7F))
\TX_OUT_COUNT[10]_i_3
(.I0(\TX_OUT_COUNT[10]_i_6_n_0 ),
.I1(\TX_OUT_COUNT[10]_i_7_n_0 ),
.I2(\TX_OUT_COUNT[10]_i_8_n_0 ),
.I3(\TX_OUT_COUNT_reg_n_0_[0] ),
.I4(\TX_OUT_COUNT_reg_n_0_[1] ),
.I5(\TX_OUT_COUNT_reg_n_0_[2] ),
.O(\TX_OUT_COUNT[10]_i_3_n_0 ));
LUT2 #(
.INIT(4'hE))
\TX_OUT_COUNT[10]_i_4
(.I0(\TX_PHY_STATE_reg_n_0_[1] ),
.I1(\TX_PHY_STATE_reg_n_0_[4] ),
.O(\TX_OUT_COUNT[10]_i_4_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFEF0F0F0F0))
\TX_OUT_COUNT[10]_i_5
(.I0(\TX_OUT_COUNT_reg_n_0_[7] ),
.I1(\TX_OUT_COUNT_reg_n_0_[5] ),
.I2(\TX_OUT_COUNT[8]_i_2_n_0 ),
.I3(\TX_OUT_COUNT_reg_n_0_[6] ),
.I4(\TX_OUT_COUNT_reg_n_0_[8] ),
.I5(\TX_PHY_STATE_reg_n_0_[3] ),
.O(\TX_OUT_COUNT[10]_i_5_n_0 ));
LUT3 #(
.INIT(8'h01))
\TX_OUT_COUNT[10]_i_6
(.I0(\TX_OUT_COUNT_reg_n_0_[3] ),
.I1(\TX_OUT_COUNT_reg_n_0_[4] ),
.I2(\TX_OUT_COUNT_reg_n_0_[5] ),
.O(\TX_OUT_COUNT[10]_i_6_n_0 ));
LUT2 #(
.INIT(4'h1))
\TX_OUT_COUNT[10]_i_7
(.I0(\TX_OUT_COUNT_reg_n_0_[10] ),
.I1(\TX_OUT_COUNT_reg_n_0_[9] ),
.O(\TX_OUT_COUNT[10]_i_7_n_0 ));
LUT3 #(
.INIT(8'h01))
\TX_OUT_COUNT[10]_i_8
(.I0(\TX_OUT_COUNT_reg_n_0_[6] ),
.I1(\TX_OUT_COUNT_reg_n_0_[8] ),
.I2(\TX_OUT_COUNT_reg_n_0_[7] ),
.O(\TX_OUT_COUNT[10]_i_8_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair159" *)
LUT3 #(
.INIT(8'h9F))
\TX_OUT_COUNT[1]_i_1
(.I0(\TX_OUT_COUNT_reg_n_0_[0] ),
.I1(\TX_OUT_COUNT_reg_n_0_[1] ),
.I2(\TX_PHY_STATE_reg_n_0_[3] ),
.O(\TX_OUT_COUNT[1]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair87" *)
LUT4 #(
.INIT(16'hE1FF))
\TX_OUT_COUNT[2]_i_1
(.I0(\TX_OUT_COUNT_reg_n_0_[1] ),
.I1(\TX_OUT_COUNT_reg_n_0_[0] ),
.I2(\TX_OUT_COUNT_reg_n_0_[2] ),
.I3(\TX_PHY_STATE_reg_n_0_[3] ),
.O(\TX_OUT_COUNT[2]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair87" *)
LUT5 #(
.INIT(32'hFE01FFFF))
\TX_OUT_COUNT[3]_i_1
(.I0(\TX_OUT_COUNT_reg_n_0_[2] ),
.I1(\TX_OUT_COUNT_reg_n_0_[0] ),
.I2(\TX_OUT_COUNT_reg_n_0_[1] ),
.I3(\TX_OUT_COUNT_reg_n_0_[3] ),
.I4(\TX_PHY_STATE_reg_n_0_[3] ),
.O(\TX_OUT_COUNT[3]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFFE0001FFFFFFFF))
\TX_OUT_COUNT[4]_i_1
(.I0(\TX_OUT_COUNT_reg_n_0_[3] ),
.I1(\TX_OUT_COUNT_reg_n_0_[1] ),
.I2(\TX_OUT_COUNT_reg_n_0_[0] ),
.I3(\TX_OUT_COUNT_reg_n_0_[2] ),
.I4(\TX_OUT_COUNT_reg_n_0_[4] ),
.I5(\TX_PHY_STATE_reg_n_0_[3] ),
.O(\TX_OUT_COUNT[4]_i_1_n_0 ));
LUT3 #(
.INIT(8'h95))
\TX_OUT_COUNT[5]_i_1
(.I0(\TX_OUT_COUNT[8]_i_2_n_0 ),
.I1(\TX_OUT_COUNT_reg_n_0_[5] ),
.I2(\TX_PHY_STATE_reg_n_0_[3] ),
.O(\TX_OUT_COUNT[5]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair86" *)
LUT4 #(
.INIT(16'hE133))
\TX_OUT_COUNT[6]_i_1
(.I0(\TX_OUT_COUNT_reg_n_0_[5] ),
.I1(\TX_OUT_COUNT[8]_i_2_n_0 ),
.I2(\TX_OUT_COUNT_reg_n_0_[6] ),
.I3(\TX_PHY_STATE_reg_n_0_[3] ),
.O(\TX_OUT_COUNT[6]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair86" *)
LUT5 #(
.INIT(32'hFE013333))
\TX_OUT_COUNT[7]_i_1
(.I0(\TX_OUT_COUNT_reg_n_0_[6] ),
.I1(\TX_OUT_COUNT[8]_i_2_n_0 ),
.I2(\TX_OUT_COUNT_reg_n_0_[5] ),
.I3(\TX_OUT_COUNT_reg_n_0_[7] ),
.I4(\TX_PHY_STATE_reg_n_0_[3] ),
.O(\TX_OUT_COUNT[7]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFFE00010F0F0F0F))
\TX_OUT_COUNT[8]_i_1
(.I0(\TX_OUT_COUNT_reg_n_0_[7] ),
.I1(\TX_OUT_COUNT_reg_n_0_[5] ),
.I2(\TX_OUT_COUNT[8]_i_2_n_0 ),
.I3(\TX_OUT_COUNT_reg_n_0_[6] ),
.I4(\TX_OUT_COUNT_reg_n_0_[8] ),
.I5(\TX_PHY_STATE_reg_n_0_[3] ),
.O(\TX_OUT_COUNT[8]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFE00000000))
\TX_OUT_COUNT[8]_i_2
(.I0(\TX_OUT_COUNT_reg_n_0_[3] ),
.I1(\TX_OUT_COUNT_reg_n_0_[1] ),
.I2(\TX_OUT_COUNT_reg_n_0_[0] ),
.I3(\TX_OUT_COUNT_reg_n_0_[2] ),
.I4(\TX_OUT_COUNT_reg_n_0_[4] ),
.I5(\TX_PHY_STATE_reg_n_0_[3] ),
.O(\TX_OUT_COUNT[8]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair150" *)
LUT3 #(
.INIT(8'h95))
\TX_OUT_COUNT[9]_i_1
(.I0(\TX_OUT_COUNT[10]_i_5_n_0 ),
.I1(\TX_OUT_COUNT_reg_n_0_[9] ),
.I2(\TX_PHY_STATE_reg_n_0_[3] ),
.O(\TX_OUT_COUNT[9]_i_1_n_0 ));
FDRE \TX_OUT_COUNT_reg[0]
(.C(ETH_CLK_OBUF),
.CE(\TX_OUT_COUNT[10]_i_1_n_0 ),
.D(TX_OUT_COUNT0_in),
.Q(\TX_OUT_COUNT_reg_n_0_[0] ),
.R(1'b0));
FDRE \TX_OUT_COUNT_reg[10]
(.C(ETH_CLK_OBUF),
.CE(\TX_OUT_COUNT[10]_i_1_n_0 ),
.D(\TX_OUT_COUNT[10]_i_2_n_0 ),
.Q(\TX_OUT_COUNT_reg_n_0_[10] ),
.R(1'b0));
FDRE \TX_OUT_COUNT_reg[1]
(.C(ETH_CLK_OBUF),
.CE(\TX_OUT_COUNT[10]_i_1_n_0 ),
.D(\TX_OUT_COUNT[1]_i_1_n_0 ),
.Q(\TX_OUT_COUNT_reg_n_0_[1] ),
.R(1'b0));
FDRE \TX_OUT_COUNT_reg[2]
(.C(ETH_CLK_OBUF),
.CE(\TX_OUT_COUNT[10]_i_1_n_0 ),
.D(\TX_OUT_COUNT[2]_i_1_n_0 ),
.Q(\TX_OUT_COUNT_reg_n_0_[2] ),
.R(1'b0));
FDRE \TX_OUT_COUNT_reg[3]
(.C(ETH_CLK_OBUF),
.CE(\TX_OUT_COUNT[10]_i_1_n_0 ),
.D(\TX_OUT_COUNT[3]_i_1_n_0 ),
.Q(\TX_OUT_COUNT_reg_n_0_[3] ),
.R(1'b0));
FDRE \TX_OUT_COUNT_reg[4]
(.C(ETH_CLK_OBUF),
.CE(\TX_OUT_COUNT[10]_i_1_n_0 ),
.D(\TX_OUT_COUNT[4]_i_1_n_0 ),
.Q(\TX_OUT_COUNT_reg_n_0_[4] ),
.R(1'b0));
FDRE \TX_OUT_COUNT_reg[5]
(.C(ETH_CLK_OBUF),
.CE(\TX_OUT_COUNT[10]_i_1_n_0 ),
.D(\TX_OUT_COUNT[5]_i_1_n_0 ),
.Q(\TX_OUT_COUNT_reg_n_0_[5] ),
.R(1'b0));
FDRE \TX_OUT_COUNT_reg[6]
(.C(ETH_CLK_OBUF),
.CE(\TX_OUT_COUNT[10]_i_1_n_0 ),
.D(\TX_OUT_COUNT[6]_i_1_n_0 ),
.Q(\TX_OUT_COUNT_reg_n_0_[6] ),
.R(1'b0));
FDRE \TX_OUT_COUNT_reg[7]
(.C(ETH_CLK_OBUF),
.CE(\TX_OUT_COUNT[10]_i_1_n_0 ),
.D(\TX_OUT_COUNT[7]_i_1_n_0 ),
.Q(\TX_OUT_COUNT_reg_n_0_[7] ),
.R(1'b0));
FDRE \TX_OUT_COUNT_reg[8]
(.C(ETH_CLK_OBUF),
.CE(\TX_OUT_COUNT[10]_i_1_n_0 ),
.D(\TX_OUT_COUNT[8]_i_1_n_0 ),
.Q(\TX_OUT_COUNT_reg_n_0_[8] ),
.R(1'b0));
FDRE \TX_OUT_COUNT_reg[9]
(.C(ETH_CLK_OBUF),
.CE(\TX_OUT_COUNT[10]_i_1_n_0 ),
.D(\TX_OUT_COUNT[9]_i_1_n_0 ),
.Q(\TX_OUT_COUNT_reg_n_0_[9] ),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair95" *)
LUT5 #(
.INIT(32'hFF007C7C))
\TX_PACKET_STATE[0]_i_1
(.I0(\TX_PACKET_STATE_reg[1]_i_2_n_2 ),
.I1(\TX_PACKET_STATE_reg_n_0_[0] ),
.I2(S_TX_ACK_reg_n_0),
.I3(DONE_SYNC),
.I4(\TX_PACKET_STATE_reg_n_0_[1] ),
.O(\TX_PACKET_STATE[0]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair95" *)
LUT5 #(
.INIT(32'hFF338080))
\TX_PACKET_STATE[1]_i_1
(.I0(\TX_PACKET_STATE_reg[1]_i_2_n_2 ),
.I1(\TX_PACKET_STATE_reg_n_0_[0] ),
.I2(S_TX_ACK_reg_n_0),
.I3(DONE_SYNC),
.I4(\TX_PACKET_STATE_reg_n_0_[1] ),
.O(\TX_PACKET_STATE[1]_i_1_n_0 ));
LUT2 #(
.INIT(4'h1))
\TX_PACKET_STATE[1]_i_10
(.I0(TX_IN_COUNT[6]),
.I1(TX_IN_COUNT[7]),
.O(\TX_PACKET_STATE[1]_i_10_n_0 ));
LUT2 #(
.INIT(4'h1))
\TX_PACKET_STATE[1]_i_11
(.I0(TX_IN_COUNT[4]),
.I1(TX_IN_COUNT[5]),
.O(\TX_PACKET_STATE[1]_i_11_n_0 ));
LUT2 #(
.INIT(4'h1))
\TX_PACKET_STATE[1]_i_12
(.I0(TX_IN_COUNT[2]),
.I1(TX_IN_COUNT[3]),
.O(\TX_PACKET_STATE[1]_i_12_n_0 ));
LUT1 #(
.INIT(2'h1))
\TX_PACKET_STATE[1]_i_13
(.I0(TX_IN_COUNT[1]),
.O(\TX_PACKET_STATE[1]_i_13_n_0 ));
LUT2 #(
.INIT(4'hE))
\TX_PACKET_STATE[1]_i_4
(.I0(TX_IN_COUNT[9]),
.I1(TX_IN_COUNT[8]),
.O(\TX_PACKET_STATE[1]_i_4_n_0 ));
LUT1 #(
.INIT(2'h1))
\TX_PACKET_STATE[1]_i_5
(.I0(TX_IN_COUNT[10]),
.O(\TX_PACKET_STATE[1]_i_5_n_0 ));
LUT2 #(
.INIT(4'h1))
\TX_PACKET_STATE[1]_i_6
(.I0(TX_IN_COUNT[8]),
.I1(TX_IN_COUNT[9]),
.O(\TX_PACKET_STATE[1]_i_6_n_0 ));
LUT2 #(
.INIT(4'hE))
\TX_PACKET_STATE[1]_i_7
(.I0(TX_IN_COUNT[7]),
.I1(TX_IN_COUNT[6]),
.O(\TX_PACKET_STATE[1]_i_7_n_0 ));
LUT2 #(
.INIT(4'hE))
\TX_PACKET_STATE[1]_i_8
(.I0(TX_IN_COUNT[5]),
.I1(TX_IN_COUNT[4]),
.O(\TX_PACKET_STATE[1]_i_8_n_0 ));
LUT2 #(
.INIT(4'hE))
\TX_PACKET_STATE[1]_i_9
(.I0(TX_IN_COUNT[3]),
.I1(TX_IN_COUNT[2]),
.O(\TX_PACKET_STATE[1]_i_9_n_0 ));
FDRE \TX_PACKET_STATE_reg[0]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(\TX_PACKET_STATE[0]_i_1_n_0 ),
.Q(\TX_PACKET_STATE_reg_n_0_[0] ),
.R(INTERNAL_RST_reg));
FDRE \TX_PACKET_STATE_reg[1]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(\TX_PACKET_STATE[1]_i_1_n_0 ),
.Q(\TX_PACKET_STATE_reg_n_0_[1] ),
.R(INTERNAL_RST_reg));
CARRY4 \TX_PACKET_STATE_reg[1]_i_2
(.CI(\TX_PACKET_STATE_reg[1]_i_3_n_0 ),
.CO({\NLW_TX_PACKET_STATE_reg[1]_i_2_CO_UNCONNECTED [3:2],\TX_PACKET_STATE_reg[1]_i_2_n_2 ,\NLW_TX_PACKET_STATE_reg[1]_i_2_CO_UNCONNECTED [0]}),
.CYINIT(1'b0),
.DI({1'b0,1'b0,TX_IN_COUNT[10],\TX_PACKET_STATE[1]_i_4_n_0 }),
.O(\NLW_TX_PACKET_STATE_reg[1]_i_2_O_UNCONNECTED [3:0]),
.S({1'b0,1'b0,\TX_PACKET_STATE[1]_i_5_n_0 ,\TX_PACKET_STATE[1]_i_6_n_0 }));
CARRY4 \TX_PACKET_STATE_reg[1]_i_3
(.CI(1'b0),
.CO({\TX_PACKET_STATE_reg[1]_i_3_n_0 ,\NLW_TX_PACKET_STATE_reg[1]_i_3_CO_UNCONNECTED [2:0]}),
.CYINIT(1'b1),
.DI({\TX_PACKET_STATE[1]_i_7_n_0 ,\TX_PACKET_STATE[1]_i_8_n_0 ,\TX_PACKET_STATE[1]_i_9_n_0 ,TX_IN_COUNT[1]}),
.O(\NLW_TX_PACKET_STATE_reg[1]_i_3_O_UNCONNECTED [3:0]),
.S({\TX_PACKET_STATE[1]_i_10_n_0 ,\TX_PACKET_STATE[1]_i_11_n_0 ,\TX_PACKET_STATE[1]_i_12_n_0 ,\TX_PACKET_STATE[1]_i_13_n_0 }));
LUT6 #(
.INIT(64'h80000000DFFFFFFF))
\TX_PHY_STATE[0]_i_1
(.I0(\TX_PHY_STATE_reg_n_0_[2] ),
.I1(GO_SYNC),
.I2(\TX_PHY_STATE_reg_n_0_[1] ),
.I3(\TX_PHY_STATE_reg_n_0_[3] ),
.I4(\TX_PHY_STATE_reg_n_0_[4] ),
.I5(\TX_PHY_STATE_reg_n_0_[0] ),
.O(\TX_PHY_STATE[0]_i_1_n_0 ));
LUT6 #(
.INIT(64'h8000FFFFDFFF0000))
\TX_PHY_STATE[1]_i_1
(.I0(\TX_PHY_STATE_reg_n_0_[2] ),
.I1(GO_SYNC),
.I2(\TX_PHY_STATE_reg_n_0_[3] ),
.I3(\TX_PHY_STATE_reg_n_0_[4] ),
.I4(\TX_PHY_STATE_reg_n_0_[1] ),
.I5(\TX_PHY_STATE_reg_n_0_[0] ),
.O(\TX_PHY_STATE[1]_i_1_n_0 ));
LUT6 #(
.INIT(64'h8ABABA8ABA8ABA8A))
\TX_PHY_STATE[2]_i_1
(.I0(\TX_PHY_STATE[2]_i_2_n_0 ),
.I1(\TX_PHY_STATE_reg_n_0_[3] ),
.I2(\TX_PHY_STATE_reg_n_0_[4] ),
.I3(\TX_PHY_STATE_reg_n_0_[2] ),
.I4(\TX_PHY_STATE_reg_n_0_[0] ),
.I5(\TX_PHY_STATE_reg_n_0_[1] ),
.O(\TX_PHY_STATE[2]_i_1_n_0 ));
LUT6 #(
.INIT(64'hB8B8BB88BBBB8888))
\TX_PHY_STATE[2]_i_2
(.I0(\TX_PHY_STATE[2]_i_3_n_0 ),
.I1(\TX_PHY_STATE[2]_i_4_n_0 ),
.I2(GO_SYNC),
.I3(\TX_PHY_STATE_reg_n_0_[0] ),
.I4(\TX_PHY_STATE_reg_n_0_[2] ),
.I5(\TX_PHY_STATE_reg_n_0_[1] ),
.O(\TX_PHY_STATE[2]_i_2_n_0 ));
LUT5 #(
.INIT(32'h0FF0F8F0))
\TX_PHY_STATE[2]_i_3
(.I0(\TX_PHY_STATE[3]_i_5_n_0 ),
.I1(\TX_PHY_STATE_reg_n_0_[3] ),
.I2(\TX_PHY_STATE_reg_n_0_[2] ),
.I3(\TX_PHY_STATE_reg_n_0_[0] ),
.I4(\TX_PHY_STATE_reg_n_0_[1] ),
.O(\TX_PHY_STATE[2]_i_3_n_0 ));
LUT3 #(
.INIT(8'h5D))
\TX_PHY_STATE[2]_i_4
(.I0(\TX_PHY_STATE_reg_n_0_[4] ),
.I1(\TX_PHY_STATE_reg_n_0_[2] ),
.I2(\TX_PHY_STATE_reg_n_0_[3] ),
.O(\TX_PHY_STATE[2]_i_4_n_0 ));
LUT6 #(
.INIT(64'hCFAAC0AAC0AAC0AA))
\TX_PHY_STATE[3]_i_1
(.I0(\TX_PHY_STATE[3]_i_2_n_0 ),
.I1(\TX_PHY_STATE[3]_i_3_n_0 ),
.I2(\TX_PHY_STATE_reg_n_0_[3] ),
.I3(\TX_PHY_STATE_reg_n_0_[4] ),
.I4(\TX_PHY_STATE_reg_n_0_[2] ),
.I5(\TX_PHY_STATE[3]_i_4_n_0 ),
.O(\TX_PHY_STATE[3]_i_1_n_0 ));
LUT5 #(
.INIT(32'h3CCC8CCC))
\TX_PHY_STATE[3]_i_2
(.I0(\TX_PHY_STATE[3]_i_5_n_0 ),
.I1(\TX_PHY_STATE_reg_n_0_[3] ),
.I2(\TX_PHY_STATE_reg_n_0_[2] ),
.I3(\TX_PHY_STATE_reg_n_0_[0] ),
.I4(\TX_PHY_STATE_reg_n_0_[1] ),
.O(\TX_PHY_STATE[3]_i_2_n_0 ));
LUT3 #(
.INIT(8'hBF))
\TX_PHY_STATE[3]_i_3
(.I0(GO_SYNC),
.I1(\TX_PHY_STATE_reg_n_0_[2] ),
.I2(\TX_PHY_STATE_reg_n_0_[1] ),
.O(\TX_PHY_STATE[3]_i_3_n_0 ));
LUT2 #(
.INIT(4'h8))
\TX_PHY_STATE[3]_i_4
(.I0(\TX_PHY_STATE_reg_n_0_[1] ),
.I1(\TX_PHY_STATE_reg_n_0_[0] ),
.O(\TX_PHY_STATE[3]_i_4_n_0 ));
LUT6 #(
.INIT(64'h0000000000000080))
\TX_PHY_STATE[3]_i_5
(.I0(\TX_OUT_COUNT[10]_i_6_n_0 ),
.I1(\TX_OUT_COUNT[10]_i_7_n_0 ),
.I2(\TX_OUT_COUNT[10]_i_8_n_0 ),
.I3(\TX_OUT_COUNT_reg_n_0_[0] ),
.I4(\TX_OUT_COUNT_reg_n_0_[1] ),
.I5(\TX_OUT_COUNT_reg_n_0_[2] ),
.O(\TX_PHY_STATE[3]_i_5_n_0 ));
LUT5 #(
.INIT(32'hAFBEAABE))
\TX_PHY_STATE[4]_i_1
(.I0(\TX_PHY_STATE[4]_i_3_n_0 ),
.I1(GO_SYNC),
.I2(\TX_PHY_STATE_reg_n_0_[1] ),
.I3(\TX_PHY_STATE_reg_n_0_[0] ),
.I4(\TX_PHY_STATE[4]_i_4_n_0 ),
.O(\TX_PHY_STATE[4]_i_1_n_0 ));
LUT6 #(
.INIT(64'hF5FF8800FFFF0000))
\TX_PHY_STATE[4]_i_2
(.I0(\TX_PHY_STATE_reg_n_0_[1] ),
.I1(\TX_PHY_STATE_reg_n_0_[0] ),
.I2(GO_SYNC),
.I3(\TX_PHY_STATE_reg_n_0_[2] ),
.I4(\TX_PHY_STATE_reg_n_0_[4] ),
.I5(\TX_PHY_STATE_reg_n_0_[3] ),
.O(\TX_PHY_STATE[4]_i_2_n_0 ));
LUT4 #(
.INIT(16'h7FFE))
\TX_PHY_STATE[4]_i_3
(.I0(\TX_PHY_STATE_reg_n_0_[1] ),
.I1(\TX_PHY_STATE_reg_n_0_[2] ),
.I2(\TX_PHY_STATE_reg_n_0_[3] ),
.I3(\TX_PHY_STATE_reg_n_0_[4] ),
.O(\TX_PHY_STATE[4]_i_3_n_0 ));
LUT5 #(
.INIT(32'h00000001))
\TX_PHY_STATE[4]_i_4
(.I0(\PREAMBLE_COUNT_reg_n_0_[3] ),
.I1(\PREAMBLE_COUNT_reg_n_0_[1] ),
.I2(\PREAMBLE_COUNT_reg_n_0_[0] ),
.I3(\PREAMBLE_COUNT_reg_n_0_[4] ),
.I4(\PREAMBLE_COUNT_reg_n_0_[2] ),
.O(\TX_PHY_STATE[4]_i_4_n_0 ));
FDRE \TX_PHY_STATE_reg[0]
(.C(ETH_CLK_OBUF),
.CE(\TX_PHY_STATE[4]_i_1_n_0 ),
.D(\TX_PHY_STATE[0]_i_1_n_0 ),
.Q(\TX_PHY_STATE_reg_n_0_[0] ),
.R(INTERNAL_RST_reg));
FDRE \TX_PHY_STATE_reg[1]
(.C(ETH_CLK_OBUF),
.CE(\TX_PHY_STATE[4]_i_1_n_0 ),
.D(\TX_PHY_STATE[1]_i_1_n_0 ),
.Q(\TX_PHY_STATE_reg_n_0_[1] ),
.R(INTERNAL_RST_reg));
FDRE \TX_PHY_STATE_reg[2]
(.C(ETH_CLK_OBUF),
.CE(\TX_PHY_STATE[4]_i_1_n_0 ),
.D(\TX_PHY_STATE[2]_i_1_n_0 ),
.Q(\TX_PHY_STATE_reg_n_0_[2] ),
.R(INTERNAL_RST_reg));
FDRE \TX_PHY_STATE_reg[3]
(.C(ETH_CLK_OBUF),
.CE(\TX_PHY_STATE[4]_i_1_n_0 ),
.D(\TX_PHY_STATE[3]_i_1_n_0 ),
.Q(\TX_PHY_STATE_reg_n_0_[3] ),
.R(INTERNAL_RST_reg));
FDRE \TX_PHY_STATE_reg[4]
(.C(ETH_CLK_OBUF),
.CE(\TX_PHY_STATE[4]_i_1_n_0 ),
.D(\TX_PHY_STATE[4]_i_2_n_0 ),
.Q(\TX_PHY_STATE_reg_n_0_[4] ),
.R(INTERNAL_RST_reg));
FDRE \TX_READ_ADDRESS_reg_rep[0]
(.C(ETH_CLK_OBUF),
.CE(\TX_READ_ADDRESS_rep[9]_i_2_n_0 ),
.D(\TX_READ_ADDRESS_rep[0]_i_1_n_0 ),
.Q(TX_READ_ADDRESS[0]),
.R(\TX_READ_ADDRESS_rep[9]_i_1_n_0 ));
FDRE \TX_READ_ADDRESS_reg_rep[10]
(.C(ETH_CLK_OBUF),
.CE(\TX_READ_ADDRESS_rep[9]_i_2_n_0 ),
.D(TX_READ_ADDRESS0[10]),
.Q(TX_READ_ADDRESS[10]),
.R(\TX_READ_ADDRESS_rep[9]_i_1_n_0 ));
FDRE \TX_READ_ADDRESS_reg_rep[1]
(.C(ETH_CLK_OBUF),
.CE(\TX_READ_ADDRESS_rep[9]_i_2_n_0 ),
.D(TX_READ_ADDRESS0[1]),
.Q(TX_READ_ADDRESS[1]),
.R(\TX_READ_ADDRESS_rep[9]_i_1_n_0 ));
FDRE \TX_READ_ADDRESS_reg_rep[2]
(.C(ETH_CLK_OBUF),
.CE(\TX_READ_ADDRESS_rep[9]_i_2_n_0 ),
.D(TX_READ_ADDRESS0[2]),
.Q(TX_READ_ADDRESS[2]),
.R(\TX_READ_ADDRESS_rep[9]_i_1_n_0 ));
FDRE \TX_READ_ADDRESS_reg_rep[3]
(.C(ETH_CLK_OBUF),
.CE(\TX_READ_ADDRESS_rep[9]_i_2_n_0 ),
.D(TX_READ_ADDRESS0[3]),
.Q(TX_READ_ADDRESS[3]),
.R(\TX_READ_ADDRESS_rep[9]_i_1_n_0 ));
FDRE \TX_READ_ADDRESS_reg_rep[4]
(.C(ETH_CLK_OBUF),
.CE(\TX_READ_ADDRESS_rep[9]_i_2_n_0 ),
.D(TX_READ_ADDRESS0[4]),
.Q(TX_READ_ADDRESS[4]),
.R(\TX_READ_ADDRESS_rep[9]_i_1_n_0 ));
FDRE \TX_READ_ADDRESS_reg_rep[5]
(.C(ETH_CLK_OBUF),
.CE(\TX_READ_ADDRESS_rep[9]_i_2_n_0 ),
.D(TX_READ_ADDRESS0[5]),
.Q(TX_READ_ADDRESS[5]),
.R(\TX_READ_ADDRESS_rep[9]_i_1_n_0 ));
FDRE \TX_READ_ADDRESS_reg_rep[6]
(.C(ETH_CLK_OBUF),
.CE(\TX_READ_ADDRESS_rep[9]_i_2_n_0 ),
.D(TX_READ_ADDRESS0[6]),
.Q(TX_READ_ADDRESS[6]),
.R(\TX_READ_ADDRESS_rep[9]_i_1_n_0 ));
FDRE \TX_READ_ADDRESS_reg_rep[7]
(.C(ETH_CLK_OBUF),
.CE(\TX_READ_ADDRESS_rep[9]_i_2_n_0 ),
.D(TX_READ_ADDRESS0[7]),
.Q(TX_READ_ADDRESS[7]),
.R(\TX_READ_ADDRESS_rep[9]_i_1_n_0 ));
FDRE \TX_READ_ADDRESS_reg_rep[8]
(.C(ETH_CLK_OBUF),
.CE(\TX_READ_ADDRESS_rep[9]_i_2_n_0 ),
.D(TX_READ_ADDRESS0[8]),
.Q(TX_READ_ADDRESS[8]),
.R(\TX_READ_ADDRESS_rep[9]_i_1_n_0 ));
FDRE \TX_READ_ADDRESS_reg_rep[9]
(.C(ETH_CLK_OBUF),
.CE(\TX_READ_ADDRESS_rep[9]_i_2_n_0 ),
.D(TX_READ_ADDRESS0[9]),
.Q(TX_READ_ADDRESS[9]),
.R(\TX_READ_ADDRESS_rep[9]_i_1_n_0 ));
LUT1 #(
.INIT(2'h1))
\TX_READ_ADDRESS_rep[0]_i_1
(.I0(TX_READ_ADDRESS[0]),
.O(\TX_READ_ADDRESS_rep[0]_i_1_n_0 ));
LUT6 #(
.INIT(64'h7FFFFFFF80000000))
\TX_READ_ADDRESS_rep[10]_i_1
(.I0(TX_READ_ADDRESS[8]),
.I1(TX_READ_ADDRESS[6]),
.I2(\TX_READ_ADDRESS_rep[9]_i_4_n_0 ),
.I3(TX_READ_ADDRESS[7]),
.I4(TX_READ_ADDRESS[9]),
.I5(TX_READ_ADDRESS[10]),
.O(TX_READ_ADDRESS0[10]));
(* SOFT_HLUTNM = "soft_lutpair162" *)
LUT2 #(
.INIT(4'h6))
\TX_READ_ADDRESS_rep[1]_i_1
(.I0(TX_READ_ADDRESS[0]),
.I1(TX_READ_ADDRESS[1]),
.O(TX_READ_ADDRESS0[1]));
(* SOFT_HLUTNM = "soft_lutpair162" *)
LUT3 #(
.INIT(8'h78))
\TX_READ_ADDRESS_rep[2]_i_1
(.I0(TX_READ_ADDRESS[0]),
.I1(TX_READ_ADDRESS[1]),
.I2(TX_READ_ADDRESS[2]),
.O(TX_READ_ADDRESS0[2]));
(* SOFT_HLUTNM = "soft_lutpair129" *)
LUT4 #(
.INIT(16'h7F80))
\TX_READ_ADDRESS_rep[3]_i_1
(.I0(TX_READ_ADDRESS[1]),
.I1(TX_READ_ADDRESS[0]),
.I2(TX_READ_ADDRESS[2]),
.I3(TX_READ_ADDRESS[3]),
.O(TX_READ_ADDRESS0[3]));
(* SOFT_HLUTNM = "soft_lutpair129" *)
LUT5 #(
.INIT(32'h7FFF8000))
\TX_READ_ADDRESS_rep[4]_i_1
(.I0(TX_READ_ADDRESS[2]),
.I1(TX_READ_ADDRESS[0]),
.I2(TX_READ_ADDRESS[1]),
.I3(TX_READ_ADDRESS[3]),
.I4(TX_READ_ADDRESS[4]),
.O(TX_READ_ADDRESS0[4]));
LUT6 #(
.INIT(64'h7FFFFFFF80000000))
\TX_READ_ADDRESS_rep[5]_i_1
(.I0(TX_READ_ADDRESS[3]),
.I1(TX_READ_ADDRESS[1]),
.I2(TX_READ_ADDRESS[0]),
.I3(TX_READ_ADDRESS[2]),
.I4(TX_READ_ADDRESS[4]),
.I5(TX_READ_ADDRESS[5]),
.O(TX_READ_ADDRESS0[5]));
(* SOFT_HLUTNM = "soft_lutpair161" *)
LUT2 #(
.INIT(4'h6))
\TX_READ_ADDRESS_rep[6]_i_1
(.I0(\TX_READ_ADDRESS_rep[9]_i_4_n_0 ),
.I1(TX_READ_ADDRESS[6]),
.O(TX_READ_ADDRESS0[6]));
(* SOFT_HLUTNM = "soft_lutpair161" *)
LUT3 #(
.INIT(8'h78))
\TX_READ_ADDRESS_rep[7]_i_1
(.I0(\TX_READ_ADDRESS_rep[9]_i_4_n_0 ),
.I1(TX_READ_ADDRESS[6]),
.I2(TX_READ_ADDRESS[7]),
.O(TX_READ_ADDRESS0[7]));
(* SOFT_HLUTNM = "soft_lutpair127" *)
LUT4 #(
.INIT(16'h7F80))
\TX_READ_ADDRESS_rep[8]_i_1
(.I0(TX_READ_ADDRESS[6]),
.I1(\TX_READ_ADDRESS_rep[9]_i_4_n_0 ),
.I2(TX_READ_ADDRESS[7]),
.I3(TX_READ_ADDRESS[8]),
.O(TX_READ_ADDRESS0[8]));
LUT6 #(
.INIT(64'h0000000000000004))
\TX_READ_ADDRESS_rep[9]_i_1
(.I0(\TX_PHY_STATE_reg_n_0_[2] ),
.I1(GO_SYNC),
.I2(\TX_PHY_STATE_reg_n_0_[4] ),
.I3(\TX_PHY_STATE_reg_n_0_[0] ),
.I4(\TX_PHY_STATE_reg_n_0_[1] ),
.I5(\TX_PHY_STATE_reg_n_0_[3] ),
.O(\TX_READ_ADDRESS_rep[9]_i_1_n_0 ));
LUT6 #(
.INIT(64'h0100010000010000))
\TX_READ_ADDRESS_rep[9]_i_2
(.I0(\TX_PHY_STATE_reg_n_0_[1] ),
.I1(\TX_PHY_STATE_reg_n_0_[0] ),
.I2(\TX_PHY_STATE_reg_n_0_[4] ),
.I3(\TX_PHY_STATE_reg_n_0_[3] ),
.I4(GO_SYNC),
.I5(\TX_PHY_STATE_reg_n_0_[2] ),
.O(\TX_READ_ADDRESS_rep[9]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair127" *)
LUT5 #(
.INIT(32'h7FFF8000))
\TX_READ_ADDRESS_rep[9]_i_3
(.I0(TX_READ_ADDRESS[7]),
.I1(\TX_READ_ADDRESS_rep[9]_i_4_n_0 ),
.I2(TX_READ_ADDRESS[6]),
.I3(TX_READ_ADDRESS[8]),
.I4(TX_READ_ADDRESS[9]),
.O(TX_READ_ADDRESS0[9]));
LUT6 #(
.INIT(64'h8000000000000000))
\TX_READ_ADDRESS_rep[9]_i_4
(.I0(TX_READ_ADDRESS[5]),
.I1(TX_READ_ADDRESS[3]),
.I2(TX_READ_ADDRESS[1]),
.I3(TX_READ_ADDRESS[0]),
.I4(TX_READ_ADDRESS[2]),
.I5(TX_READ_ADDRESS[4]),
.O(\TX_READ_ADDRESS_rep[9]_i_4_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair144" *)
LUT2 #(
.INIT(4'h1))
\TX_WRITE_ADDRESS[0]_i_1
(.I0(\TX_PACKET_STATE_reg_n_0_[1] ),
.I1(TX_WRITE_ADDRESS[0]),
.O(\TX_WRITE_ADDRESS[0]_i_1_n_0 ));
LUT4 #(
.INIT(16'h04F0))
\TX_WRITE_ADDRESS[10]_i_1
(.I0(\TX_PACKET_STATE_reg[1]_i_2_n_2 ),
.I1(S_TX_ACK_reg_n_0),
.I2(\TX_PACKET_STATE_reg_n_0_[1] ),
.I3(\TX_PACKET_STATE_reg_n_0_[0] ),
.O(\TX_WRITE_ADDRESS[10]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair144" *)
LUT4 #(
.INIT(16'h0078))
\TX_WRITE_ADDRESS[10]_i_2
(.I0(\TX_WRITE_ADDRESS[10]_i_3_n_0 ),
.I1(TX_WRITE_ADDRESS[9]),
.I2(TX_WRITE_ADDRESS[10]),
.I3(\TX_PACKET_STATE_reg_n_0_[1] ),
.O(\TX_WRITE_ADDRESS[10]_i_2_n_0 ));
LUT4 #(
.INIT(16'h0800))
\TX_WRITE_ADDRESS[10]_i_3
(.I0(TX_WRITE_ADDRESS[8]),
.I1(TX_WRITE_ADDRESS[7]),
.I2(\TX_WRITE_ADDRESS[9]_i_2_n_0 ),
.I3(TX_WRITE_ADDRESS[6]),
.O(\TX_WRITE_ADDRESS[10]_i_3_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair154" *)
LUT3 #(
.INIT(8'h06))
\TX_WRITE_ADDRESS[1]_i_1
(.I0(TX_WRITE_ADDRESS[1]),
.I1(TX_WRITE_ADDRESS[0]),
.I2(\TX_PACKET_STATE_reg_n_0_[1] ),
.O(\TX_WRITE_ADDRESS[1]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair91" *)
LUT4 #(
.INIT(16'h1540))
\TX_WRITE_ADDRESS[2]_i_1
(.I0(\TX_PACKET_STATE_reg_n_0_[1] ),
.I1(TX_WRITE_ADDRESS[0]),
.I2(TX_WRITE_ADDRESS[1]),
.I3(TX_WRITE_ADDRESS[2]),
.O(\TX_WRITE_ADDRESS[2]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair91" *)
LUT5 #(
.INIT(32'h15554000))
\TX_WRITE_ADDRESS[3]_i_1
(.I0(\TX_PACKET_STATE_reg_n_0_[1] ),
.I1(TX_WRITE_ADDRESS[1]),
.I2(TX_WRITE_ADDRESS[0]),
.I3(TX_WRITE_ADDRESS[2]),
.I4(TX_WRITE_ADDRESS[3]),
.O(\TX_WRITE_ADDRESS[3]_i_1_n_0 ));
LUT6 #(
.INIT(64'h1555555540000000))
\TX_WRITE_ADDRESS[4]_i_1
(.I0(\TX_PACKET_STATE_reg_n_0_[1] ),
.I1(TX_WRITE_ADDRESS[2]),
.I2(TX_WRITE_ADDRESS[0]),
.I3(TX_WRITE_ADDRESS[1]),
.I4(TX_WRITE_ADDRESS[3]),
.I5(TX_WRITE_ADDRESS[4]),
.O(\TX_WRITE_ADDRESS[4]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair154" *)
LUT3 #(
.INIT(8'h41))
\TX_WRITE_ADDRESS[5]_i_1
(.I0(\TX_PACKET_STATE_reg_n_0_[1] ),
.I1(\TX_WRITE_ADDRESS[5]_i_2_n_0 ),
.I2(TX_WRITE_ADDRESS[5]),
.O(\TX_WRITE_ADDRESS[5]_i_1_n_0 ));
LUT5 #(
.INIT(32'h7FFFFFFF))
\TX_WRITE_ADDRESS[5]_i_2
(.I0(TX_WRITE_ADDRESS[3]),
.I1(TX_WRITE_ADDRESS[1]),
.I2(TX_WRITE_ADDRESS[0]),
.I3(TX_WRITE_ADDRESS[2]),
.I4(TX_WRITE_ADDRESS[4]),
.O(\TX_WRITE_ADDRESS[5]_i_2_n_0 ));
LUT3 #(
.INIT(8'h41))
\TX_WRITE_ADDRESS[6]_i_1
(.I0(\TX_PACKET_STATE_reg_n_0_[1] ),
.I1(\TX_WRITE_ADDRESS[9]_i_2_n_0 ),
.I2(TX_WRITE_ADDRESS[6]),
.O(\TX_WRITE_ADDRESS[6]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair102" *)
LUT4 #(
.INIT(16'h4510))
\TX_WRITE_ADDRESS[7]_i_1
(.I0(\TX_PACKET_STATE_reg_n_0_[1] ),
.I1(\TX_WRITE_ADDRESS[9]_i_2_n_0 ),
.I2(TX_WRITE_ADDRESS[6]),
.I3(TX_WRITE_ADDRESS[7]),
.O(\TX_WRITE_ADDRESS[7]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair102" *)
LUT5 #(
.INIT(32'h51550400))
\TX_WRITE_ADDRESS[8]_i_1
(.I0(\TX_PACKET_STATE_reg_n_0_[1] ),
.I1(TX_WRITE_ADDRESS[6]),
.I2(\TX_WRITE_ADDRESS[9]_i_2_n_0 ),
.I3(TX_WRITE_ADDRESS[7]),
.I4(TX_WRITE_ADDRESS[8]),
.O(\TX_WRITE_ADDRESS[8]_i_1_n_0 ));
LUT6 #(
.INIT(64'h5515555500400000))
\TX_WRITE_ADDRESS[9]_i_1
(.I0(\TX_PACKET_STATE_reg_n_0_[1] ),
.I1(TX_WRITE_ADDRESS[8]),
.I2(TX_WRITE_ADDRESS[7]),
.I3(\TX_WRITE_ADDRESS[9]_i_2_n_0 ),
.I4(TX_WRITE_ADDRESS[6]),
.I5(TX_WRITE_ADDRESS[9]),
.O(\TX_WRITE_ADDRESS[9]_i_1_n_0 ));
LUT6 #(
.INIT(64'h7FFFFFFFFFFFFFFF))
\TX_WRITE_ADDRESS[9]_i_2
(.I0(TX_WRITE_ADDRESS[4]),
.I1(TX_WRITE_ADDRESS[2]),
.I2(TX_WRITE_ADDRESS[0]),
.I3(TX_WRITE_ADDRESS[1]),
.I4(TX_WRITE_ADDRESS[3]),
.I5(TX_WRITE_ADDRESS[5]),
.O(\TX_WRITE_ADDRESS[9]_i_2_n_0 ));
FDRE \TX_WRITE_ADDRESS_DEL_reg[0]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(TX_WRITE_ADDRESS[0]),
.Q(TX_WRITE_ADDRESS_DEL[0]),
.R(1'b0));
FDRE \TX_WRITE_ADDRESS_DEL_reg[10]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(TX_WRITE_ADDRESS[10]),
.Q(TX_WRITE_ADDRESS_DEL[10]),
.R(1'b0));
FDRE \TX_WRITE_ADDRESS_DEL_reg[1]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(TX_WRITE_ADDRESS[1]),
.Q(TX_WRITE_ADDRESS_DEL[1]),
.R(1'b0));
FDRE \TX_WRITE_ADDRESS_DEL_reg[2]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(TX_WRITE_ADDRESS[2]),
.Q(TX_WRITE_ADDRESS_DEL[2]),
.R(1'b0));
FDRE \TX_WRITE_ADDRESS_DEL_reg[3]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(TX_WRITE_ADDRESS[3]),
.Q(TX_WRITE_ADDRESS_DEL[3]),
.R(1'b0));
FDRE \TX_WRITE_ADDRESS_DEL_reg[4]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(TX_WRITE_ADDRESS[4]),
.Q(TX_WRITE_ADDRESS_DEL[4]),
.R(1'b0));
FDRE \TX_WRITE_ADDRESS_DEL_reg[5]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(TX_WRITE_ADDRESS[5]),
.Q(TX_WRITE_ADDRESS_DEL[5]),
.R(1'b0));
FDRE \TX_WRITE_ADDRESS_DEL_reg[6]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(TX_WRITE_ADDRESS[6]),
.Q(TX_WRITE_ADDRESS_DEL[6]),
.R(1'b0));
FDRE \TX_WRITE_ADDRESS_DEL_reg[7]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(TX_WRITE_ADDRESS[7]),
.Q(TX_WRITE_ADDRESS_DEL[7]),
.R(1'b0));
FDRE \TX_WRITE_ADDRESS_DEL_reg[8]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(TX_WRITE_ADDRESS[8]),
.Q(TX_WRITE_ADDRESS_DEL[8]),
.R(1'b0));
FDRE \TX_WRITE_ADDRESS_DEL_reg[9]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(TX_WRITE_ADDRESS[9]),
.Q(TX_WRITE_ADDRESS_DEL[9]),
.R(1'b0));
FDRE \TX_WRITE_ADDRESS_reg[0]
(.C(ETH_CLK_OBUF),
.CE(\TX_WRITE_ADDRESS[10]_i_1_n_0 ),
.D(\TX_WRITE_ADDRESS[0]_i_1_n_0 ),
.Q(TX_WRITE_ADDRESS[0]),
.R(INTERNAL_RST_reg));
FDRE \TX_WRITE_ADDRESS_reg[10]
(.C(ETH_CLK_OBUF),
.CE(\TX_WRITE_ADDRESS[10]_i_1_n_0 ),
.D(\TX_WRITE_ADDRESS[10]_i_2_n_0 ),
.Q(TX_WRITE_ADDRESS[10]),
.R(INTERNAL_RST_reg));
FDRE \TX_WRITE_ADDRESS_reg[1]
(.C(ETH_CLK_OBUF),
.CE(\TX_WRITE_ADDRESS[10]_i_1_n_0 ),
.D(\TX_WRITE_ADDRESS[1]_i_1_n_0 ),
.Q(TX_WRITE_ADDRESS[1]),
.R(INTERNAL_RST_reg));
FDRE \TX_WRITE_ADDRESS_reg[2]
(.C(ETH_CLK_OBUF),
.CE(\TX_WRITE_ADDRESS[10]_i_1_n_0 ),
.D(\TX_WRITE_ADDRESS[2]_i_1_n_0 ),
.Q(TX_WRITE_ADDRESS[2]),
.R(INTERNAL_RST_reg));
FDRE \TX_WRITE_ADDRESS_reg[3]
(.C(ETH_CLK_OBUF),
.CE(\TX_WRITE_ADDRESS[10]_i_1_n_0 ),
.D(\TX_WRITE_ADDRESS[3]_i_1_n_0 ),
.Q(TX_WRITE_ADDRESS[3]),
.R(INTERNAL_RST_reg));
FDRE \TX_WRITE_ADDRESS_reg[4]
(.C(ETH_CLK_OBUF),
.CE(\TX_WRITE_ADDRESS[10]_i_1_n_0 ),
.D(\TX_WRITE_ADDRESS[4]_i_1_n_0 ),
.Q(TX_WRITE_ADDRESS[4]),
.R(INTERNAL_RST_reg));
FDRE \TX_WRITE_ADDRESS_reg[5]
(.C(ETH_CLK_OBUF),
.CE(\TX_WRITE_ADDRESS[10]_i_1_n_0 ),
.D(\TX_WRITE_ADDRESS[5]_i_1_n_0 ),
.Q(TX_WRITE_ADDRESS[5]),
.R(INTERNAL_RST_reg));
FDRE \TX_WRITE_ADDRESS_reg[6]
(.C(ETH_CLK_OBUF),
.CE(\TX_WRITE_ADDRESS[10]_i_1_n_0 ),
.D(\TX_WRITE_ADDRESS[6]_i_1_n_0 ),
.Q(TX_WRITE_ADDRESS[6]),
.R(INTERNAL_RST_reg));
FDRE \TX_WRITE_ADDRESS_reg[7]
(.C(ETH_CLK_OBUF),
.CE(\TX_WRITE_ADDRESS[10]_i_1_n_0 ),
.D(\TX_WRITE_ADDRESS[7]_i_1_n_0 ),
.Q(TX_WRITE_ADDRESS[7]),
.R(INTERNAL_RST_reg));
FDRE \TX_WRITE_ADDRESS_reg[8]
(.C(ETH_CLK_OBUF),
.CE(\TX_WRITE_ADDRESS[10]_i_1_n_0 ),
.D(\TX_WRITE_ADDRESS[8]_i_1_n_0 ),
.Q(TX_WRITE_ADDRESS[8]),
.R(INTERNAL_RST_reg));
FDRE \TX_WRITE_ADDRESS_reg[9]
(.C(ETH_CLK_OBUF),
.CE(\TX_WRITE_ADDRESS[10]_i_1_n_0 ),
.D(\TX_WRITE_ADDRESS[9]_i_1_n_0 ),
.Q(TX_WRITE_ADDRESS[9]),
.R(INTERNAL_RST_reg));
(* SOFT_HLUTNM = "soft_lutpair88" *)
LUT3 #(
.INIT(8'h20))
TX_WRITE_i_1
(.I0(S_TX_ACK_reg_n_0),
.I1(\TX_PACKET_STATE_reg_n_0_[1] ),
.I2(\TX_PACKET_STATE_reg_n_0_[0] ),
.O(TX_WRITE_i_1_n_0));
FDRE TX_WRITE_reg
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(TX_WRITE_i_1_n_0),
.Q(TX_WRITE),
.R(1'b0));
endmodule
|
module serial_output
(IN1_ACK,
RS232_TX_OBUF,
INTERNAL_RST_reg,
ETH_CLK_OBUF,
IN1_STB,
Q);
output IN1_ACK;
output RS232_TX_OBUF;
input INTERNAL_RST_reg;
input ETH_CLK_OBUF;
input IN1_STB;
input [7:0]Q;
wire [11:0]BAUD_COUNT;
wire \BAUD_COUNT[11]_i_2__0_n_0 ;
wire \BAUD_COUNT[11]_i_3_n_0 ;
wire \BAUD_COUNT_reg[4]_i_2_n_0 ;
wire \BAUD_COUNT_reg[8]_i_2_n_0 ;
wire \BAUD_COUNT_reg_n_0_[0] ;
wire \BAUD_COUNT_reg_n_0_[10] ;
wire \BAUD_COUNT_reg_n_0_[11] ;
wire \BAUD_COUNT_reg_n_0_[1] ;
wire \BAUD_COUNT_reg_n_0_[2] ;
wire \BAUD_COUNT_reg_n_0_[3] ;
wire \BAUD_COUNT_reg_n_0_[4] ;
wire \BAUD_COUNT_reg_n_0_[5] ;
wire \BAUD_COUNT_reg_n_0_[6] ;
wire \BAUD_COUNT_reg_n_0_[7] ;
wire \BAUD_COUNT_reg_n_0_[8] ;
wire \BAUD_COUNT_reg_n_0_[9] ;
wire \DATA[7]_i_1_n_0 ;
wire \DATA_reg_n_0_[0] ;
wire ETH_CLK_OBUF;
wire \FSM_sequential_STATE[0]_i_1_n_0 ;
wire \FSM_sequential_STATE[1]_i_1_n_0 ;
wire \FSM_sequential_STATE[2]_i_1_n_0 ;
wire \FSM_sequential_STATE[3]_i_1_n_0 ;
wire \FSM_sequential_STATE[3]_i_2_n_0 ;
wire IN1_ACK;
wire IN1_STB;
wire INTERNAL_RST_reg;
wire [7:0]Q;
wire RS232_TX_OBUF;
(* RTL_KEEP = "yes" *) wire [3:0]STATE;
wire S_IN1_ACK1;
wire S_IN1_ACK_i_1_n_0;
wire TX_i_1_n_0;
wire TX_i_3_n_0;
wire TX_i_4_n_0;
wire TX_i_5_n_0;
wire TX_i_6_n_0;
wire TX_reg_i_2_n_0;
wire X16CLK_EN_i_1__0_n_0;
wire X16CLK_EN_reg_n_0;
wire [11:1]data0;
wire p_0_in;
wire p_1_in;
wire p_2_in;
wire p_3_in;
wire p_4_in;
wire p_5_in;
wire p_6_in;
wire [3:0]\NLW_BAUD_COUNT_reg[11]_i_4_CO_UNCONNECTED ;
wire [3:3]\NLW_BAUD_COUNT_reg[11]_i_4_O_UNCONNECTED ;
wire [2:0]\NLW_BAUD_COUNT_reg[4]_i_2_CO_UNCONNECTED ;
wire [2:0]\NLW_BAUD_COUNT_reg[8]_i_2_CO_UNCONNECTED ;
LUT1 #(
.INIT(2'h1))
\BAUD_COUNT[0]_i_1
(.I0(\BAUD_COUNT_reg_n_0_[0] ),
.O(BAUD_COUNT[0]));
(* SOFT_HLUTNM = "soft_lutpair60" *)
LUT3 #(
.INIT(8'hE0))
\BAUD_COUNT[10]_i_1__0
(.I0(\BAUD_COUNT[11]_i_2__0_n_0 ),
.I1(\BAUD_COUNT[11]_i_3_n_0 ),
.I2(data0[10]),
.O(BAUD_COUNT[10]));
(* SOFT_HLUTNM = "soft_lutpair61" *)
LUT3 #(
.INIT(8'hE0))
\BAUD_COUNT[11]_i_1__0
(.I0(\BAUD_COUNT[11]_i_2__0_n_0 ),
.I1(\BAUD_COUNT[11]_i_3_n_0 ),
.I2(data0[11]),
.O(BAUD_COUNT[11]));
LUT6 #(
.INIT(64'hFFFFFEFFFFFFFFFF))
\BAUD_COUNT[11]_i_2__0
(.I0(\BAUD_COUNT_reg_n_0_[10] ),
.I1(\BAUD_COUNT_reg_n_0_[9] ),
.I2(\BAUD_COUNT_reg_n_0_[6] ),
.I3(\BAUD_COUNT_reg_n_0_[7] ),
.I4(\BAUD_COUNT_reg_n_0_[11] ),
.I5(\BAUD_COUNT_reg_n_0_[5] ),
.O(\BAUD_COUNT[11]_i_2__0_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFFFDFFF))
\BAUD_COUNT[11]_i_3
(.I0(\BAUD_COUNT_reg_n_0_[8] ),
.I1(\BAUD_COUNT_reg_n_0_[1] ),
.I2(\BAUD_COUNT_reg_n_0_[4] ),
.I3(\BAUD_COUNT_reg_n_0_[0] ),
.I4(\BAUD_COUNT_reg_n_0_[2] ),
.I5(\BAUD_COUNT_reg_n_0_[3] ),
.O(\BAUD_COUNT[11]_i_3_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair57" *)
LUT3 #(
.INIT(8'hE0))
\BAUD_COUNT[1]_i_1__0
(.I0(\BAUD_COUNT[11]_i_2__0_n_0 ),
.I1(\BAUD_COUNT[11]_i_3_n_0 ),
.I2(data0[1]),
.O(BAUD_COUNT[1]));
(* SOFT_HLUTNM = "soft_lutpair57" *)
LUT3 #(
.INIT(8'hE0))
\BAUD_COUNT[2]_i_1__0
(.I0(\BAUD_COUNT[11]_i_2__0_n_0 ),
.I1(\BAUD_COUNT[11]_i_3_n_0 ),
.I2(data0[2]),
.O(BAUD_COUNT[2]));
(* SOFT_HLUTNM = "soft_lutpair58" *)
LUT3 #(
.INIT(8'hE0))
\BAUD_COUNT[3]_i_1__0
(.I0(\BAUD_COUNT[11]_i_2__0_n_0 ),
.I1(\BAUD_COUNT[11]_i_3_n_0 ),
.I2(data0[3]),
.O(BAUD_COUNT[3]));
(* SOFT_HLUTNM = "soft_lutpair58" *)
LUT3 #(
.INIT(8'hE0))
\BAUD_COUNT[4]_i_1__0
(.I0(\BAUD_COUNT[11]_i_2__0_n_0 ),
.I1(\BAUD_COUNT[11]_i_3_n_0 ),
.I2(data0[4]),
.O(BAUD_COUNT[4]));
(* SOFT_HLUTNM = "soft_lutpair59" *)
LUT3 #(
.INIT(8'hE0))
\BAUD_COUNT[5]_i_1__0
(.I0(\BAUD_COUNT[11]_i_2__0_n_0 ),
.I1(\BAUD_COUNT[11]_i_3_n_0 ),
.I2(data0[5]),
.O(BAUD_COUNT[5]));
(* SOFT_HLUTNM = "soft_lutpair56" *)
LUT3 #(
.INIT(8'hE0))
\BAUD_COUNT[6]_i_1__0
(.I0(\BAUD_COUNT[11]_i_2__0_n_0 ),
.I1(\BAUD_COUNT[11]_i_3_n_0 ),
.I2(data0[6]),
.O(BAUD_COUNT[6]));
(* SOFT_HLUTNM = "soft_lutpair59" *)
LUT3 #(
.INIT(8'hE0))
\BAUD_COUNT[7]_i_1__0
(.I0(\BAUD_COUNT[11]_i_2__0_n_0 ),
.I1(\BAUD_COUNT[11]_i_3_n_0 ),
.I2(data0[7]),
.O(BAUD_COUNT[7]));
(* SOFT_HLUTNM = "soft_lutpair60" *)
LUT3 #(
.INIT(8'hE0))
\BAUD_COUNT[8]_i_1__0
(.I0(\BAUD_COUNT[11]_i_2__0_n_0 ),
.I1(\BAUD_COUNT[11]_i_3_n_0 ),
.I2(data0[8]),
.O(BAUD_COUNT[8]));
(* SOFT_HLUTNM = "soft_lutpair61" *)
LUT3 #(
.INIT(8'hE0))
\BAUD_COUNT[9]_i_1__0
(.I0(\BAUD_COUNT[11]_i_2__0_n_0 ),
.I1(\BAUD_COUNT[11]_i_3_n_0 ),
.I2(data0[9]),
.O(BAUD_COUNT[9]));
FDRE #(
.INIT(1'b0))
\BAUD_COUNT_reg[0]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(BAUD_COUNT[0]),
.Q(\BAUD_COUNT_reg_n_0_[0] ),
.R(INTERNAL_RST_reg));
FDRE #(
.INIT(1'b0))
\BAUD_COUNT_reg[10]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(BAUD_COUNT[10]),
.Q(\BAUD_COUNT_reg_n_0_[10] ),
.R(INTERNAL_RST_reg));
FDRE #(
.INIT(1'b0))
\BAUD_COUNT_reg[11]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(BAUD_COUNT[11]),
.Q(\BAUD_COUNT_reg_n_0_[11] ),
.R(INTERNAL_RST_reg));
CARRY4 \BAUD_COUNT_reg[11]_i_4
(.CI(\BAUD_COUNT_reg[8]_i_2_n_0 ),
.CO(\NLW_BAUD_COUNT_reg[11]_i_4_CO_UNCONNECTED [3:0]),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O({\NLW_BAUD_COUNT_reg[11]_i_4_O_UNCONNECTED [3],data0[11:9]}),
.S({1'b0,\BAUD_COUNT_reg_n_0_[11] ,\BAUD_COUNT_reg_n_0_[10] ,\BAUD_COUNT_reg_n_0_[9] }));
FDRE #(
.INIT(1'b0))
\BAUD_COUNT_reg[1]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(BAUD_COUNT[1]),
.Q(\BAUD_COUNT_reg_n_0_[1] ),
.R(INTERNAL_RST_reg));
FDRE #(
.INIT(1'b0))
\BAUD_COUNT_reg[2]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(BAUD_COUNT[2]),
.Q(\BAUD_COUNT_reg_n_0_[2] ),
.R(INTERNAL_RST_reg));
FDRE #(
.INIT(1'b0))
\BAUD_COUNT_reg[3]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(BAUD_COUNT[3]),
.Q(\BAUD_COUNT_reg_n_0_[3] ),
.R(INTERNAL_RST_reg));
FDRE #(
.INIT(1'b0))
\BAUD_COUNT_reg[4]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(BAUD_COUNT[4]),
.Q(\BAUD_COUNT_reg_n_0_[4] ),
.R(INTERNAL_RST_reg));
CARRY4 \BAUD_COUNT_reg[4]_i_2
(.CI(1'b0),
.CO({\BAUD_COUNT_reg[4]_i_2_n_0 ,\NLW_BAUD_COUNT_reg[4]_i_2_CO_UNCONNECTED [2:0]}),
.CYINIT(\BAUD_COUNT_reg_n_0_[0] ),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(data0[4:1]),
.S({\BAUD_COUNT_reg_n_0_[4] ,\BAUD_COUNT_reg_n_0_[3] ,\BAUD_COUNT_reg_n_0_[2] ,\BAUD_COUNT_reg_n_0_[1] }));
FDRE #(
.INIT(1'b0))
\BAUD_COUNT_reg[5]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(BAUD_COUNT[5]),
.Q(\BAUD_COUNT_reg_n_0_[5] ),
.R(INTERNAL_RST_reg));
FDRE #(
.INIT(1'b0))
\BAUD_COUNT_reg[6]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(BAUD_COUNT[6]),
.Q(\BAUD_COUNT_reg_n_0_[6] ),
.R(INTERNAL_RST_reg));
FDRE #(
.INIT(1'b0))
\BAUD_COUNT_reg[7]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(BAUD_COUNT[7]),
.Q(\BAUD_COUNT_reg_n_0_[7] ),
.R(INTERNAL_RST_reg));
FDRE #(
.INIT(1'b0))
\BAUD_COUNT_reg[8]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(BAUD_COUNT[8]),
.Q(\BAUD_COUNT_reg_n_0_[8] ),
.R(INTERNAL_RST_reg));
CARRY4 \BAUD_COUNT_reg[8]_i_2
(.CI(\BAUD_COUNT_reg[4]_i_2_n_0 ),
.CO({\BAUD_COUNT_reg[8]_i_2_n_0 ,\NLW_BAUD_COUNT_reg[8]_i_2_CO_UNCONNECTED [2:0]}),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(data0[8:5]),
.S({\BAUD_COUNT_reg_n_0_[8] ,\BAUD_COUNT_reg_n_0_[7] ,\BAUD_COUNT_reg_n_0_[6] ,\BAUD_COUNT_reg_n_0_[5] }));
FDRE #(
.INIT(1'b0))
\BAUD_COUNT_reg[9]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(BAUD_COUNT[9]),
.Q(\BAUD_COUNT_reg_n_0_[9] ),
.R(INTERNAL_RST_reg));
LUT6 #(
.INIT(64'h0000000000001000))
\DATA[7]_i_1
(.I0(STATE[1]),
.I1(STATE[3]),
.I2(IN1_ACK),
.I3(IN1_STB),
.I4(STATE[2]),
.I5(STATE[0]),
.O(\DATA[7]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\DATA_reg[0]
(.C(ETH_CLK_OBUF),
.CE(\DATA[7]_i_1_n_0 ),
.D(Q[0]),
.Q(\DATA_reg_n_0_[0] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\DATA_reg[1]
(.C(ETH_CLK_OBUF),
.CE(\DATA[7]_i_1_n_0 ),
.D(Q[1]),
.Q(p_6_in),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\DATA_reg[2]
(.C(ETH_CLK_OBUF),
.CE(\DATA[7]_i_1_n_0 ),
.D(Q[2]),
.Q(p_5_in),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\DATA_reg[3]
(.C(ETH_CLK_OBUF),
.CE(\DATA[7]_i_1_n_0 ),
.D(Q[3]),
.Q(p_4_in),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\DATA_reg[4]
(.C(ETH_CLK_OBUF),
.CE(\DATA[7]_i_1_n_0 ),
.D(Q[4]),
.Q(p_3_in),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\DATA_reg[5]
(.C(ETH_CLK_OBUF),
.CE(\DATA[7]_i_1_n_0 ),
.D(Q[5]),
.Q(p_2_in),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\DATA_reg[6]
(.C(ETH_CLK_OBUF),
.CE(\DATA[7]_i_1_n_0 ),
.D(Q[6]),
.Q(p_1_in),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\DATA_reg[7]
(.C(ETH_CLK_OBUF),
.CE(\DATA[7]_i_1_n_0 ),
.D(Q[7]),
.Q(p_0_in),
.R(1'b0));
LUT3 #(
.INIT(8'h07))
\FSM_sequential_STATE[0]_i_1
(.I0(STATE[2]),
.I1(STATE[3]),
.I2(STATE[0]),
.O(\FSM_sequential_STATE[0]_i_1_n_0 ));
LUT4 #(
.INIT(16'h152A))
\FSM_sequential_STATE[1]_i_1
(.I0(STATE[0]),
.I1(STATE[2]),
.I2(STATE[3]),
.I3(STATE[1]),
.O(\FSM_sequential_STATE[1]_i_1_n_0 ));
LUT4 #(
.INIT(16'h0078))
\FSM_sequential_STATE[2]_i_1
(.I0(STATE[1]),
.I1(STATE[0]),
.I2(STATE[2]),
.I3(STATE[3]),
.O(\FSM_sequential_STATE[2]_i_1_n_0 ));
LUT6 #(
.INIT(64'h0F00FF010F00FE00))
\FSM_sequential_STATE[3]_i_1
(.I0(STATE[0]),
.I1(STATE[1]),
.I2(STATE[2]),
.I3(X16CLK_EN_reg_n_0),
.I4(STATE[3]),
.I5(S_IN1_ACK1),
.O(\FSM_sequential_STATE[3]_i_1_n_0 ));
LUT4 #(
.INIT(16'h0870))
\FSM_sequential_STATE[3]_i_2
(.I0(STATE[1]),
.I1(STATE[0]),
.I2(STATE[3]),
.I3(STATE[2]),
.O(\FSM_sequential_STATE[3]_i_2_n_0 ));
LUT2 #(
.INIT(4'h8))
\FSM_sequential_STATE[3]_i_3
(.I0(IN1_ACK),
.I1(IN1_STB),
.O(S_IN1_ACK1));
(* KEEP = "yes" *)
FDRE \FSM_sequential_STATE_reg[0]
(.C(ETH_CLK_OBUF),
.CE(\FSM_sequential_STATE[3]_i_1_n_0 ),
.D(\FSM_sequential_STATE[0]_i_1_n_0 ),
.Q(STATE[0]),
.R(INTERNAL_RST_reg));
(* KEEP = "yes" *)
FDRE \FSM_sequential_STATE_reg[1]
(.C(ETH_CLK_OBUF),
.CE(\FSM_sequential_STATE[3]_i_1_n_0 ),
.D(\FSM_sequential_STATE[1]_i_1_n_0 ),
.Q(STATE[1]),
.R(INTERNAL_RST_reg));
(* KEEP = "yes" *)
FDRE \FSM_sequential_STATE_reg[2]
(.C(ETH_CLK_OBUF),
.CE(\FSM_sequential_STATE[3]_i_1_n_0 ),
.D(\FSM_sequential_STATE[2]_i_1_n_0 ),
.Q(STATE[2]),
.R(INTERNAL_RST_reg));
(* KEEP = "yes" *)
FDRE \FSM_sequential_STATE_reg[3]
(.C(ETH_CLK_OBUF),
.CE(\FSM_sequential_STATE[3]_i_1_n_0 ),
.D(\FSM_sequential_STATE[3]_i_2_n_0 ),
.Q(STATE[3]),
.R(INTERNAL_RST_reg));
LUT6 #(
.INIT(64'hFFFFFFFD00000003))
S_IN1_ACK_i_1
(.I0(IN1_STB),
.I1(STATE[1]),
.I2(STATE[3]),
.I3(STATE[2]),
.I4(STATE[0]),
.I5(IN1_ACK),
.O(S_IN1_ACK_i_1_n_0));
FDRE #(
.INIT(1'b0))
S_IN1_ACK_reg
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(S_IN1_ACK_i_1_n_0),
.Q(IN1_ACK),
.R(INTERNAL_RST_reg));
LUT6 #(
.INIT(64'hFFAAAABA00AAAA8A))
TX_i_1
(.I0(TX_reg_i_2_n_0),
.I1(STATE[1]),
.I2(STATE[0]),
.I3(STATE[3]),
.I4(STATE[2]),
.I5(RS232_TX_OBUF),
.O(TX_i_1_n_0));
LUT6 #(
.INIT(64'h0AC0FFFF0AC00000))
TX_i_3
(.I0(p_4_in),
.I1(p_0_in),
.I2(STATE[3]),
.I3(STATE[2]),
.I4(STATE[1]),
.I5(TX_i_5_n_0),
.O(TX_i_3_n_0));
LUT6 #(
.INIT(64'h0AFCFFFF0AFC0000))
TX_i_4
(.I0(p_3_in),
.I1(\DATA_reg_n_0_[0] ),
.I2(STATE[3]),
.I3(STATE[2]),
.I4(STATE[1]),
.I5(TX_i_6_n_0),
.O(TX_i_4_n_0));
LUT4 #(
.INIT(16'h0ACF))
TX_i_5
(.I0(p_6_in),
.I1(p_2_in),
.I2(STATE[3]),
.I3(STATE[2]),
.O(TX_i_5_n_0));
LUT4 #(
.INIT(16'h30BB))
TX_i_6
(.I0(p_5_in),
.I1(STATE[2]),
.I2(p_1_in),
.I3(STATE[3]),
.O(TX_i_6_n_0));
FDSE #(
.INIT(1'b1))
TX_reg
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(TX_i_1_n_0),
.Q(RS232_TX_OBUF),
.S(INTERNAL_RST_reg));
MUXF7 TX_reg_i_2
(.I0(TX_i_3_n_0),
.I1(TX_i_4_n_0),
.O(TX_reg_i_2_n_0),
.S(STATE[0]));
(* SOFT_HLUTNM = "soft_lutpair56" *)
LUT2 #(
.INIT(4'h1))
X16CLK_EN_i_1__0
(.I0(\BAUD_COUNT[11]_i_2__0_n_0 ),
.I1(\BAUD_COUNT[11]_i_3_n_0 ),
.O(X16CLK_EN_i_1__0_n_0));
FDRE #(
.INIT(1'b0))
X16CLK_EN_reg
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(X16CLK_EN_i_1__0_n_0),
.Q(X16CLK_EN_reg_n_0),
.R(INTERNAL_RST_reg));
endmodule
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