module_content
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1.05M
|
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module user_design
(IN1_STB,
output_rs232_tx,
IN1_ACK,
ETH_CLK_OBUF,
INTERNAL_RST_reg);
output IN1_STB;
output [7:0]output_rs232_tx;
input IN1_ACK;
input ETH_CLK_OBUF;
input INTERNAL_RST_reg;
wire ETH_CLK_OBUF;
wire IN1_ACK;
wire IN1_STB;
wire INTERNAL_RST_reg;
wire [7:0]output_rs232_tx;
main_0 main_0_139931286003792
(.ETH_CLK_OBUF(ETH_CLK_OBUF),
.IN1_ACK(IN1_ACK),
.IN1_STB(IN1_STB),
.INTERNAL_RST_reg(INTERNAL_RST_reg),
.output_rs232_tx(output_rs232_tx));
endmodule
|
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
|
module Register_ShiftOutput(
input [31:0] Rt_out,
input [1:0] Mem_addr_in,
input [31:26] IR,
output [31:0] Mem_data_shift
);
wire [2:0] Rt_out_shift_ctr;
wire [31:0] Rt_out_l,Rt_out_r,Rt_out_shift;
assign Rt_out_shift_ctr[2] = (IR[31])&(!IR[30])&(IR[29])&(((!IR[28])&(IR[27])) | ((IR[27])&(!IR[26])) );
assign Rt_out_shift_ctr[1] = (IR[31])&(!IR[30])&(IR[29])&(((!IR[28])&(!IR[27])&(IR[26])) | ((IR[28])&(IR[27])&(!IR[26])));//xor better
assign Rt_out_shift_ctr[0] = (IR[31])&(!IR[30])&(IR[29])&(!IR[28])&(IR[27])&(!IR[26]);
MUX4_1 mux4_1_0(Mem_addr_in[1:0],Rt_out[31:24],8'b0,8'b0,8'b0,Rt_out_l[31:24]);
MUX4_1 mux4_1_1(Mem_addr_in[1:0],Rt_out[23:16],Rt_out[31:24],8'b0,8'b0,Rt_out_l[23:16]);
MUX4_1 mux4_1_2(Mem_addr_in[1:0],Rt_out[15:8],Rt_out[23:16],Rt_out[31:24],8'b0,Rt_out_l[15:8]);
MUX4_1 mux4_1_3(Mem_addr_in[1:0],Rt_out[7:0],Rt_out[15:8],Rt_out[23:16],Rt_out[31:24],Rt_out_l[7:0]);
MUX4_1 mux4_1_4(Mem_addr_in[1:0],Rt_out[7:0],Rt_out[15:8],Rt_out[23:16],Rt_out[31:24],Rt_out_r[31:24]);
MUX4_1 mux4_1_5(Mem_addr_in[1:0],8'b0,Rt_out[7:0],Rt_out[15:8],Rt_out[23:16],Rt_out_r[23:16]);
MUX4_1 mux4_1_6(Mem_addr_in[1:0],8'b0,8'b0,Rt_out[7:0],Rt_out[15:8],Rt_out_r[15:8]);
MUX4_1 mux4_1_7(Mem_addr_in[1:0],8'b0,8'b0,8'b0,Rt_out[7:0],Rt_out_r[7:0]);
MUX8_1 mux8_1_0(Rt_out_shift_ctr[2:0],Rt_out[7:0],8'b0,Rt_out[15:8],8'b0,Rt_out_l[31:24],Rt_out_l[31:24],Rt_out_r[31:24],8'b0,Mem_data_shift[31:24]);
MUX8_1 mux8_1_1(Rt_out_shift_ctr[2:0],Rt_out[7:0],8'b0,Rt_out[7:0],8'b0,Rt_out_l[23:16],Rt_out_l[23:16],Rt_out_r[23:16],8'b0,Mem_data_shift[23:16]);
MUX8_1 mux8_1_2(Rt_out_shift_ctr[2:0],Rt_out[7:0],8'b0,Rt_out[15:8],8'b0,Rt_out_l[15:8],Rt_out_l[15:8],Rt_out_r[15:8],8'b0,Mem_data_shift[15:8]);
MUX8_1 mux8_1_3(Rt_out_shift_ctr[2:0],Rt_out[7:0],8'b0,Rt_out[7:0],8'b0,Rt_out_l[7:0],Rt_out_l[7:0],Rt_out_r[7:0],8'b0,Mem_data_shift[7:0]);
endmodule
|
module DataMemory
#(parameter DATA_WIDTH = 32, parameter ADDR_WIDTH = 32)
(
input [(DATA_WIDTH-1):0] data,
input [(ADDR_WIDTH-1):0] addr,
input [3:0] we,
input clk,
output [(DATA_WIDTH-1):0] q
);
//wire [31:0] RegShift;
// Declare the RAM variable
reg [DATA_WIDTH-1:0] ram[2**(ADDR_WIDTH - 22) - 1:0];
// Variable to hold the registered read address
reg [ADDR_WIDTH-1:0] addr_reg;
initial ram[64] = 32'hf0f0f0f0;
//Register_ShiftOutput regshift(data,addr[1:0],{3'b100,PC_Write[2:0]},RegShift);
//assign RegShift = data;
always @ (negedge clk)
begin
case(we)
4'b0001: ram[addr[9:2]][7:0] <= data[7:0];
4'b0010: ram[addr[9:2]][15:8] <= data[15:8];
4'b0011: ram[addr[9:2]][15:0] <= data[15:0];
4'b0100: ram[addr[9:2]][23:16] <= data[23:16];
4'b0101: begin ram[addr[9:2]][23:16] <= data[23:16]; ram[addr[9:2]][7:0] <= data[7:0];end
4'b0110: ram[addr[9:2]][23:8] <= data[23:8];
4'b0111: ram[addr[9:2]][23:0] <= data[23:0];
4'b1000: ram[addr[9:2]][31:24] <= data[31:24];
4'b1001: begin ram[addr[9:2]][31:24] <= data[31:24]; ram[addr[9:2]][7:0] <= data[7:0];end
4'b1010: begin ram[addr[9:2]][31:24] <= data[31:24]; ram[addr[9:2]][15:8] <= data[15:8];end
4'b1011: begin ram[addr[9:2]][31:24] <= data[31:24]; ram[addr[9:2]][15:0] <= data[15:0];end
4'b1100: ram[addr[9:2]][31:16] <= data[31:16];
4'b1101: begin ram[addr[9:2]][31:16] <= data[31:16]; ram[addr[9:2]][7:0] <= data[7:0];end
4'b1110: ram[addr[9:2]][31:8] <= data[31:8];
4'b1111: ram[addr[9:2]] <= data;
default:;
endcase
end
// Continuous assignment implies read returns NEW data.
// This is the natural behavior of the TriMatrix memory
// blocks in Single Port mode.
assign q = ram[addr[9:2]];
endmodule
|
module DataMemory
#(parameter DATA_WIDTH = 32, parameter ADDR_WIDTH = 32)
(
input [(DATA_WIDTH-1):0] data,
input [(ADDR_WIDTH-1):0] addr,
input [3:0] we,
input clk,
output [(DATA_WIDTH-1):0] q
);
MemorySingle DataMemory1(data[7:0],addr,we[0],clk,q[7:0]);
MemorySingle DataMemory2(data[15:8],addr,we[1],clk,q[15:8]);
MemorySingle DataMemory3(data[23:16],addr,we[2],clk,q[23:16]);
MemorySingle DataMemory4(data[31:24],addr,we[3],clk,q[31:24]);
endmodule
|
module MemorySingle
#(parameter DATA_WIDTH = 8, parameter ADDR_WIDTH = 32)
(
input [(DATA_WIDTH-1):0] data,
input [(ADDR_WIDTH-1):0] addr,
input we,
input clk,
output [(DATA_WIDTH-1):0] q
);
reg [DATA_WIDTH-1:0] ram[2**(ADDR_WIDTH - 22) - 1:0];
always @(negedge clk)
begin
if(we)
ram[addr[9:2]][7:0] <= data[7:0];
end
assign q = ram[addr[9:2]];
endmodule
|
module lsu_reg2mem(addr, lsu_op, regdata, memdata);
parameter width = `OPERAND_WIDTH;
//
// I/O
//
input [1:0] addr;
input [`LSUOP_WIDTH-1:0] lsu_op;
input [width-1:0] regdata;
output [width-1:0] memdata;
//
// big-endian memory layout
//
reg [7:0] memdata_hh; // byte address 00
reg [7:0] memdata_hl; // byte address 01
reg [7:0] memdata_lh; // byte address 10
reg [7:0] memdata_ll; // byte address 11
//
assign memdata = {memdata_hh, memdata_hl, memdata_lh, memdata_ll};
//
// Mux to memdata[31:24]
//
always @(lsu_op or addr or regdata) begin
casex({lsu_op, addr[1:0]}) // synopsys parallel_case
{`LSUOP_STB, 2'b00} : memdata_hh = regdata[7:0];
{`LSUOP_STH, 2'b00} : memdata_hh = regdata[15:8];
{`LSUOP_STHB, 2'b00} : memdata_hh = regdata[7:0];
{`LSUOP_STW, 2'b00} : memdata_hh = regdata[31:24];
{`LSUOP_STWB, 2'b00} : memdata_hh = regdata[7:0];
default : memdata_hh = regdata[31:24];
endcase
end
//
// Mux to memdata[23:16]
// [TBD] comment out unneccessary access pattern(same with default), to evaluate syn result
always @(lsu_op or addr or regdata) begin
casex({lsu_op, addr[1:0]}) // synopsys parallel_case
{`LSUOP_STB, 2'b01} : memdata_hl = regdata[7:0];
{`LSUOP_STH, 2'b00} : memdata_hl = regdata[7:0];
{`LSUOP_STHB, 2'b00} : memdata_hl = regdata[15:8];
{`LSUOP_STW, 2'b00} : memdata_hl = regdata[23:16];
{`LSUOP_STWB, 2'b00} : memdata_hl = regdata[15:8];
default : memdata_hl = regdata[7:0];
endcase
end
//
// Mux to memdata[15:8]
//
always @(lsu_op or addr or regdata) begin
casex({lsu_op, addr[1:0]}) // synopsys parallel_case
{`LSUOP_STB, 2'b10} : memdata_lh = regdata[7:0];
{`LSUOP_STH, 2'b10} : memdata_lh = regdata[15:8];
{`LSUOP_STHB, 2'b10} : memdata_lh = regdata[7:0];
{`LSUOP_STW, 2'b00} : memdata_lh = regdata[15:8];
{`LSUOP_STWB, 2'b00} : memdata_lh = regdata[23:16];
default : memdata_lh = regdata[15:8];
endcase
end
//
// Mux to memdata[7:0]
//
always @(lsu_op or addr or regdata) begin
casex({lsu_op, addr[1:0]}) // synopsys parallel_case
{`LSUOP_STB, 2'b11} : memdata_ll = regdata[7:0];
{`LSUOP_STH, 2'b10} : memdata_ll = regdata[7:0];
{`LSUOP_STHB, 2'b10} : memdata_ll = regdata[15:8];
{`LSUOP_STW, 2'b00} : memdata_ll = regdata[7:0];
{`LSUOP_STWB, 2'b00} : memdata_ll = regdata[31:25];
default : memdata_ll = regdata[7:0];
endcase
end
endmodule
|
module sky130_fd_sc_lp__xnor2 (
Y ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire xnor0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
xnor xnor0 (xnor0_out_Y , A, B );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, xnor0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
|
module header
// Internal signals
//
// Generated Signal List
//
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
//
// Generated Signal Assignments
//
//
// Generated Instances and Port Mappings
//
endmodule
|
module sirv_pmu(
input clock,
input reset,
input io_wakeup_awakeup,
input io_wakeup_dwakeup,
input io_wakeup_rtc,
input io_wakeup_reset,
output io_control_hfclkrst,
output io_control_corerst,
output io_control_reserved1,
output io_control_vddpaden,
output io_control_reserved0,
input io_regs_ie_write_valid,
input [3:0] io_regs_ie_write_bits,
output [3:0] io_regs_ie_read,
input io_regs_cause_write_valid,
input [31:0] io_regs_cause_write_bits,
output [31:0] io_regs_cause_read,
input io_regs_sleep_write_valid,
input [31:0] io_regs_sleep_write_bits,
output [31:0] io_regs_sleep_read,
input io_regs_key_write_valid,
input [31:0] io_regs_key_write_bits,
output [31:0] io_regs_key_read,
input io_regs_wakeupProgram_0_write_valid,
input [31:0] io_regs_wakeupProgram_0_write_bits,
output [31:0] io_regs_wakeupProgram_0_read,
input io_regs_wakeupProgram_1_write_valid,
input [31:0] io_regs_wakeupProgram_1_write_bits,
output [31:0] io_regs_wakeupProgram_1_read,
input io_regs_wakeupProgram_2_write_valid,
input [31:0] io_regs_wakeupProgram_2_write_bits,
output [31:0] io_regs_wakeupProgram_2_read,
input io_regs_wakeupProgram_3_write_valid,
input [31:0] io_regs_wakeupProgram_3_write_bits,
output [31:0] io_regs_wakeupProgram_3_read,
input io_regs_wakeupProgram_4_write_valid,
input [31:0] io_regs_wakeupProgram_4_write_bits,
output [31:0] io_regs_wakeupProgram_4_read,
input io_regs_wakeupProgram_5_write_valid,
input [31:0] io_regs_wakeupProgram_5_write_bits,
output [31:0] io_regs_wakeupProgram_5_read,
input io_regs_wakeupProgram_6_write_valid,
input [31:0] io_regs_wakeupProgram_6_write_bits,
output [31:0] io_regs_wakeupProgram_6_read,
input io_regs_wakeupProgram_7_write_valid,
input [31:0] io_regs_wakeupProgram_7_write_bits,
output [31:0] io_regs_wakeupProgram_7_read,
input io_regs_sleepProgram_0_write_valid,
input [31:0] io_regs_sleepProgram_0_write_bits,
output [31:0] io_regs_sleepProgram_0_read,
input io_regs_sleepProgram_1_write_valid,
input [31:0] io_regs_sleepProgram_1_write_bits,
output [31:0] io_regs_sleepProgram_1_read,
input io_regs_sleepProgram_2_write_valid,
input [31:0] io_regs_sleepProgram_2_write_bits,
output [31:0] io_regs_sleepProgram_2_read,
input io_regs_sleepProgram_3_write_valid,
input [31:0] io_regs_sleepProgram_3_write_bits,
output [31:0] io_regs_sleepProgram_3_read,
input io_regs_sleepProgram_4_write_valid,
input [31:0] io_regs_sleepProgram_4_write_bits,
output [31:0] io_regs_sleepProgram_4_read,
input io_regs_sleepProgram_5_write_valid,
input [31:0] io_regs_sleepProgram_5_write_bits,
output [31:0] io_regs_sleepProgram_5_read,
input io_regs_sleepProgram_6_write_valid,
input [31:0] io_regs_sleepProgram_6_write_bits,
output [31:0] io_regs_sleepProgram_6_read,
input io_regs_sleepProgram_7_write_valid,
input [31:0] io_regs_sleepProgram_7_write_bits,
output [31:0] io_regs_sleepProgram_7_read,
input io_resetCauses_wdogrst,
input io_resetCauses_erst,
input io_resetCauses_porrst
);
reg T_355;
reg [31:0] GEN_1;
reg T_356;
reg [31:0] GEN_2;
wire core_clock;
wire core_reset;
wire core_io_wakeup_awakeup;
wire core_io_wakeup_dwakeup;
wire core_io_wakeup_rtc;
wire core_io_wakeup_reset;
wire core_io_control_valid;
wire core_io_control_bits_hfclkrst;
wire core_io_control_bits_corerst;
wire core_io_control_bits_reserved1;
wire core_io_control_bits_vddpaden;
wire core_io_control_bits_reserved0;
wire [1:0] core_io_resetCause;
wire core_io_regs_ie_write_valid;
wire [3:0] core_io_regs_ie_write_bits;
wire [3:0] core_io_regs_ie_read;
wire core_io_regs_cause_write_valid;
wire [31:0] core_io_regs_cause_write_bits;
wire [31:0] core_io_regs_cause_read;
wire core_io_regs_sleep_write_valid;
wire [31:0] core_io_regs_sleep_write_bits;
wire [31:0] core_io_regs_sleep_read;
wire core_io_regs_key_write_valid;
wire [31:0] core_io_regs_key_write_bits;
wire [31:0] core_io_regs_key_read;
wire core_io_regs_wakeupProgram_0_write_valid;
wire [31:0] core_io_regs_wakeupProgram_0_write_bits;
wire [31:0] core_io_regs_wakeupProgram_0_read;
wire core_io_regs_wakeupProgram_1_write_valid;
wire [31:0] core_io_regs_wakeupProgram_1_write_bits;
wire [31:0] core_io_regs_wakeupProgram_1_read;
wire core_io_regs_wakeupProgram_2_write_valid;
wire [31:0] core_io_regs_wakeupProgram_2_write_bits;
wire [31:0] core_io_regs_wakeupProgram_2_read;
wire core_io_regs_wakeupProgram_3_write_valid;
wire [31:0] core_io_regs_wakeupProgram_3_write_bits;
wire [31:0] core_io_regs_wakeupProgram_3_read;
wire core_io_regs_wakeupProgram_4_write_valid;
wire [31:0] core_io_regs_wakeupProgram_4_write_bits;
wire [31:0] core_io_regs_wakeupProgram_4_read;
wire core_io_regs_wakeupProgram_5_write_valid;
wire [31:0] core_io_regs_wakeupProgram_5_write_bits;
wire [31:0] core_io_regs_wakeupProgram_5_read;
wire core_io_regs_wakeupProgram_6_write_valid;
wire [31:0] core_io_regs_wakeupProgram_6_write_bits;
wire [31:0] core_io_regs_wakeupProgram_6_read;
wire core_io_regs_wakeupProgram_7_write_valid;
wire [31:0] core_io_regs_wakeupProgram_7_write_bits;
wire [31:0] core_io_regs_wakeupProgram_7_read;
wire core_io_regs_sleepProgram_0_write_valid;
wire [31:0] core_io_regs_sleepProgram_0_write_bits;
wire [31:0] core_io_regs_sleepProgram_0_read;
wire core_io_regs_sleepProgram_1_write_valid;
wire [31:0] core_io_regs_sleepProgram_1_write_bits;
wire [31:0] core_io_regs_sleepProgram_1_read;
wire core_io_regs_sleepProgram_2_write_valid;
wire [31:0] core_io_regs_sleepProgram_2_write_bits;
wire [31:0] core_io_regs_sleepProgram_2_read;
wire core_io_regs_sleepProgram_3_write_valid;
wire [31:0] core_io_regs_sleepProgram_3_write_bits;
wire [31:0] core_io_regs_sleepProgram_3_read;
wire core_io_regs_sleepProgram_4_write_valid;
wire [31:0] core_io_regs_sleepProgram_4_write_bits;
wire [31:0] core_io_regs_sleepProgram_4_read;
wire core_io_regs_sleepProgram_5_write_valid;
wire [31:0] core_io_regs_sleepProgram_5_write_bits;
wire [31:0] core_io_regs_sleepProgram_5_read;
wire core_io_regs_sleepProgram_6_write_valid;
wire [31:0] core_io_regs_sleepProgram_6_write_bits;
wire [31:0] core_io_regs_sleepProgram_6_read;
wire core_io_regs_sleepProgram_7_write_valid;
wire [31:0] core_io_regs_sleepProgram_7_write_bits;
wire [31:0] core_io_regs_sleepProgram_7_read;
wire [1:0] T_358;
wire [1:0] T_359;
wire [2:0] T_360;
wire [4:0] T_361;
wire [4:0] T_362;
wire AsyncResetRegVec_1_1_clock;
wire AsyncResetRegVec_1_1_reset;
wire [4:0] AsyncResetRegVec_1_1_io_d;
wire [4:0] AsyncResetRegVec_1_1_io_q;
wire AsyncResetRegVec_1_1_io_en;
//wire [4:0] latch;
//Bob: the naming as latch is not good, which will introduce some confusing, so we give it renames here
wire [4:0] core_io_control_bits;
wire T_369_hfclkrst;
wire T_369_corerst;
wire T_369_reserved1;
wire T_369_vddpaden;
wire T_369_reserved0;
wire T_375;
wire T_376;
wire T_377;
wire T_378;
wire T_379;
wire [1:0] T_380;
wire [2:0] T_381;
//Bob: Name as Latch is not good, give it new name here
//wire SRLatch_3_q;
//wire SRLatch_3_reset;
//wire SRLatch_3_set;
wire T_382;
wire T_383;
wire T_384;
wire T_385;
//wire SRLatch_1_1_q;
//wire SRLatch_1_1_reset;
//wire SRLatch_1_1_set;
wire T_389;
//wire SRLatch_2_1_q;
//wire SRLatch_2_1_reset;
//wire SRLatch_2_1_set;
wire T_393;
wire [1:0] T_394;
wire [2:0] T_395;
wire T_396;
wire [1:0] T_397;
wire [1:0] GEN_0;
wire [1:0] T_400;
wire T_401;
wire [1:0] T_402;
sirv_pmu_core u_pmu_core (
.clock(core_clock),
.reset(core_reset),
.io_wakeup_awakeup(core_io_wakeup_awakeup),
.io_wakeup_dwakeup(core_io_wakeup_dwakeup),
.io_wakeup_rtc(core_io_wakeup_rtc),
.io_wakeup_reset(core_io_wakeup_reset),
.io_control_valid(core_io_control_valid),
.io_control_bits_hfclkrst(core_io_control_bits_hfclkrst),
.io_control_bits_corerst(core_io_control_bits_corerst),
.io_control_bits_reserved1(core_io_control_bits_reserved1),
.io_control_bits_vddpaden(core_io_control_bits_vddpaden),
.io_control_bits_reserved0(core_io_control_bits_reserved0),
.io_resetCause(core_io_resetCause),
.io_regs_ie_write_valid(core_io_regs_ie_write_valid),
.io_regs_ie_write_bits(core_io_regs_ie_write_bits),
.io_regs_ie_read(core_io_regs_ie_read),
.io_regs_cause_write_valid(core_io_regs_cause_write_valid),
.io_regs_cause_write_bits(core_io_regs_cause_write_bits),
.io_regs_cause_read(core_io_regs_cause_read),
.io_regs_sleep_write_valid(core_io_regs_sleep_write_valid),
.io_regs_sleep_write_bits(core_io_regs_sleep_write_bits),
.io_regs_sleep_read(core_io_regs_sleep_read),
.io_regs_key_write_valid(core_io_regs_key_write_valid),
.io_regs_key_write_bits(core_io_regs_key_write_bits),
.io_regs_key_read(core_io_regs_key_read),
.io_regs_wakeupProgram_0_write_valid(core_io_regs_wakeupProgram_0_write_valid),
.io_regs_wakeupProgram_0_write_bits(core_io_regs_wakeupProgram_0_write_bits),
.io_regs_wakeupProgram_0_read(core_io_regs_wakeupProgram_0_read),
.io_regs_wakeupProgram_1_write_valid(core_io_regs_wakeupProgram_1_write_valid),
.io_regs_wakeupProgram_1_write_bits(core_io_regs_wakeupProgram_1_write_bits),
.io_regs_wakeupProgram_1_read(core_io_regs_wakeupProgram_1_read),
.io_regs_wakeupProgram_2_write_valid(core_io_regs_wakeupProgram_2_write_valid),
.io_regs_wakeupProgram_2_write_bits(core_io_regs_wakeupProgram_2_write_bits),
.io_regs_wakeupProgram_2_read(core_io_regs_wakeupProgram_2_read),
.io_regs_wakeupProgram_3_write_valid(core_io_regs_wakeupProgram_3_write_valid),
.io_regs_wakeupProgram_3_write_bits(core_io_regs_wakeupProgram_3_write_bits),
.io_regs_wakeupProgram_3_read(core_io_regs_wakeupProgram_3_read),
.io_regs_wakeupProgram_4_write_valid(core_io_regs_wakeupProgram_4_write_valid),
.io_regs_wakeupProgram_4_write_bits(core_io_regs_wakeupProgram_4_write_bits),
.io_regs_wakeupProgram_4_read(core_io_regs_wakeupProgram_4_read),
.io_regs_wakeupProgram_5_write_valid(core_io_regs_wakeupProgram_5_write_valid),
.io_regs_wakeupProgram_5_write_bits(core_io_regs_wakeupProgram_5_write_bits),
.io_regs_wakeupProgram_5_read(core_io_regs_wakeupProgram_5_read),
.io_regs_wakeupProgram_6_write_valid(core_io_regs_wakeupProgram_6_write_valid),
.io_regs_wakeupProgram_6_write_bits(core_io_regs_wakeupProgram_6_write_bits),
.io_regs_wakeupProgram_6_read(core_io_regs_wakeupProgram_6_read),
.io_regs_wakeupProgram_7_write_valid(core_io_regs_wakeupProgram_7_write_valid),
.io_regs_wakeupProgram_7_write_bits(core_io_regs_wakeupProgram_7_write_bits),
.io_regs_wakeupProgram_7_read(core_io_regs_wakeupProgram_7_read),
.io_regs_sleepProgram_0_write_valid(core_io_regs_sleepProgram_0_write_valid),
.io_regs_sleepProgram_0_write_bits(core_io_regs_sleepProgram_0_write_bits),
.io_regs_sleepProgram_0_read(core_io_regs_sleepProgram_0_read),
.io_regs_sleepProgram_1_write_valid(core_io_regs_sleepProgram_1_write_valid),
.io_regs_sleepProgram_1_write_bits(core_io_regs_sleepProgram_1_write_bits),
.io_regs_sleepProgram_1_read(core_io_regs_sleepProgram_1_read),
.io_regs_sleepProgram_2_write_valid(core_io_regs_sleepProgram_2_write_valid),
.io_regs_sleepProgram_2_write_bits(core_io_regs_sleepProgram_2_write_bits),
.io_regs_sleepProgram_2_read(core_io_regs_sleepProgram_2_read),
.io_regs_sleepProgram_3_write_valid(core_io_regs_sleepProgram_3_write_valid),
.io_regs_sleepProgram_3_write_bits(core_io_regs_sleepProgram_3_write_bits),
.io_regs_sleepProgram_3_read(core_io_regs_sleepProgram_3_read),
.io_regs_sleepProgram_4_write_valid(core_io_regs_sleepProgram_4_write_valid),
.io_regs_sleepProgram_4_write_bits(core_io_regs_sleepProgram_4_write_bits),
.io_regs_sleepProgram_4_read(core_io_regs_sleepProgram_4_read),
.io_regs_sleepProgram_5_write_valid(core_io_regs_sleepProgram_5_write_valid),
.io_regs_sleepProgram_5_write_bits(core_io_regs_sleepProgram_5_write_bits),
.io_regs_sleepProgram_5_read(core_io_regs_sleepProgram_5_read),
.io_regs_sleepProgram_6_write_valid(core_io_regs_sleepProgram_6_write_valid),
.io_regs_sleepProgram_6_write_bits(core_io_regs_sleepProgram_6_write_bits),
.io_regs_sleepProgram_6_read(core_io_regs_sleepProgram_6_read),
.io_regs_sleepProgram_7_write_valid(core_io_regs_sleepProgram_7_write_valid),
.io_regs_sleepProgram_7_write_bits(core_io_regs_sleepProgram_7_write_bits),
.io_regs_sleepProgram_7_read(core_io_regs_sleepProgram_7_read)
);
sirv_AsyncResetRegVec_1 AsyncResetRegVec_1_1 (
.clock(AsyncResetRegVec_1_1_clock),
.reset(AsyncResetRegVec_1_1_reset),
.io_d(AsyncResetRegVec_1_1_io_d),
.io_q(AsyncResetRegVec_1_1_io_q),
.io_en(AsyncResetRegVec_1_1_io_en)
);
//Bob: Since the SR Latch is not friend to the ASIC flow, so I just replace it to the DFF
// And the name as Latch is not good, so give it a new name here
wire por_reset = T_382;// POR
wire erst_reset = T_383;// ERST
wire wdog_reset = T_384;// WDOG
// In case we lost the reset, we need to just use two-dff syncer to catch up the reset, and until the clock
// is there to clear it
reg por_reset_r;
reg por_reset_r_r;
always @(posedge clock or posedge por_reset) begin
if(por_reset) begin
por_reset_r <= 1'b1;
por_reset_r_r <= 1'b1;
end
else begin
por_reset_r <= 1'b0;
por_reset_r_r <= por_reset_r;
end
end
reg erst_reset_r;
reg erst_reset_r_r;
always @(posedge clock or posedge erst_reset) begin
if(erst_reset) begin
erst_reset_r <= 1'b1;
erst_reset_r_r <= 1'b1;
end
else begin
erst_reset_r <= 1'b0;
erst_reset_r_r <= erst_reset_r;
end
end
reg wdog_reset_r;
reg wdog_reset_r_r;
always @(posedge clock or posedge wdog_reset) begin
if(wdog_reset) begin
wdog_reset_r <= 1'b1;
wdog_reset_r_r <= 1'b1;
end
else begin
wdog_reset_r <= 1'b0;
wdog_reset_r_r <= wdog_reset_r;
end
end
// Reset cause priority if they are coming at same time:
// POR
// Erst
// Wdog
wire rstcause_por_set = por_reset_r_r;
wire rstcause_erst_set = erst_reset_r_r & (~por_reset_r_r);
wire rstcause_wdog_set = wdog_reset_r_r & (~erst_reset_r_r) & (~por_reset_r_r);
// The POR only clear if:
// there is no POR reset,
// And there are other two resets
wire rstcause_por_clr = (~por_reset_r_r) & (erst_reset_r_r | wdog_reset_r_r);
// The Erst only clear if:
// there is POR reset,
// or, there is no erst reset and there is wdog reset
wire rstcause_erst_clr = por_reset_r_r | ((~erst_reset_r_r) & wdog_reset_r_r);
// The Wdog only clear if:
// there is POR or Erst reset,
wire rstcause_wdog_clr = por_reset_r_r | erst_reset_r_r;
wire rstcause_por_ena = rstcause_por_set | rstcause_por_clr ;
wire rstcause_erst_ena = rstcause_erst_set | rstcause_erst_clr;
wire rstcause_wdog_ena = rstcause_wdog_set | rstcause_wdog_clr;
wire rstcause_por_nxt = rstcause_por_set | (~rstcause_por_clr );
wire rstcause_erst_nxt = rstcause_erst_set | (~rstcause_erst_clr);
wire rstcause_wdog_nxt = rstcause_wdog_set | (~rstcause_wdog_clr);
reg rstcause_por_r;
reg rstcause_wdog_r;
reg rstcause_erst_r;
// The reset cause itself cannot have reset signal
always @(posedge clock) begin
if(rstcause_por_ena) begin
rstcause_por_r <= rstcause_por_nxt;
end
end
always @(posedge clock) begin
if(rstcause_erst_ena) begin
rstcause_erst_r <= rstcause_erst_nxt;
end
end
always @(posedge clock) begin
if(rstcause_wdog_ena) begin
rstcause_wdog_r <= rstcause_wdog_nxt;
end
end
//sirv_SRLatch SRLatch_3 ( // POR
// .q(SRLatch_3_q),
// .reset(SRLatch_3_reset),
// .set(SRLatch_3_set)
//);
//sirv_SRLatch SRLatch_1_1 (// ERST
// .q(SRLatch_1_1_q),
// .reset(SRLatch_1_1_reset),
// .set(SRLatch_1_1_set)
//);
//sirv_SRLatch SRLatch_2_1 (//WDOG
// .q(SRLatch_2_1_q),
// .reset(SRLatch_2_1_reset),
// .set(SRLatch_2_1_set)
//);
assign io_control_hfclkrst = T_369_hfclkrst;
assign io_control_corerst = T_369_corerst;
assign io_control_reserved1 = T_369_reserved1;
assign io_control_vddpaden = T_369_vddpaden;
assign io_control_reserved0 = T_369_reserved0;
assign io_regs_ie_read = core_io_regs_ie_read;
assign io_regs_cause_read = core_io_regs_cause_read;
assign io_regs_sleep_read = core_io_regs_sleep_read;
assign io_regs_key_read = core_io_regs_key_read;
assign io_regs_wakeupProgram_0_read = core_io_regs_wakeupProgram_0_read;
assign io_regs_wakeupProgram_1_read = core_io_regs_wakeupProgram_1_read;
assign io_regs_wakeupProgram_2_read = core_io_regs_wakeupProgram_2_read;
assign io_regs_wakeupProgram_3_read = core_io_regs_wakeupProgram_3_read;
assign io_regs_wakeupProgram_4_read = core_io_regs_wakeupProgram_4_read;
assign io_regs_wakeupProgram_5_read = core_io_regs_wakeupProgram_5_read;
assign io_regs_wakeupProgram_6_read = core_io_regs_wakeupProgram_6_read;
assign io_regs_wakeupProgram_7_read = core_io_regs_wakeupProgram_7_read;
assign io_regs_sleepProgram_0_read = core_io_regs_sleepProgram_0_read;
assign io_regs_sleepProgram_1_read = core_io_regs_sleepProgram_1_read;
assign io_regs_sleepProgram_2_read = core_io_regs_sleepProgram_2_read;
assign io_regs_sleepProgram_3_read = core_io_regs_sleepProgram_3_read;
assign io_regs_sleepProgram_4_read = core_io_regs_sleepProgram_4_read;
assign io_regs_sleepProgram_5_read = core_io_regs_sleepProgram_5_read;
assign io_regs_sleepProgram_6_read = core_io_regs_sleepProgram_6_read;
assign io_regs_sleepProgram_7_read = core_io_regs_sleepProgram_7_read;
assign core_clock = clock;
assign core_reset = T_356;
assign core_io_wakeup_awakeup = io_wakeup_awakeup;
assign core_io_wakeup_dwakeup = io_wakeup_dwakeup;
assign core_io_wakeup_rtc = io_wakeup_rtc;
assign core_io_wakeup_reset = 1'h0;
assign core_io_resetCause = T_402;
assign core_io_regs_ie_write_valid = io_regs_ie_write_valid;
assign core_io_regs_ie_write_bits = io_regs_ie_write_bits;
assign core_io_regs_cause_write_valid = io_regs_cause_write_valid;
assign core_io_regs_cause_write_bits = io_regs_cause_write_bits;
assign core_io_regs_sleep_write_valid = io_regs_sleep_write_valid;
assign core_io_regs_sleep_write_bits = io_regs_sleep_write_bits;
assign core_io_regs_key_write_valid = io_regs_key_write_valid;
assign core_io_regs_key_write_bits = io_regs_key_write_bits;
assign core_io_regs_wakeupProgram_0_write_valid = io_regs_wakeupProgram_0_write_valid;
assign core_io_regs_wakeupProgram_0_write_bits = io_regs_wakeupProgram_0_write_bits;
assign core_io_regs_wakeupProgram_1_write_valid = io_regs_wakeupProgram_1_write_valid;
assign core_io_regs_wakeupProgram_1_write_bits = io_regs_wakeupProgram_1_write_bits;
assign core_io_regs_wakeupProgram_2_write_valid = io_regs_wakeupProgram_2_write_valid;
assign core_io_regs_wakeupProgram_2_write_bits = io_regs_wakeupProgram_2_write_bits;
assign core_io_regs_wakeupProgram_3_write_valid = io_regs_wakeupProgram_3_write_valid;
assign core_io_regs_wakeupProgram_3_write_bits = io_regs_wakeupProgram_3_write_bits;
assign core_io_regs_wakeupProgram_4_write_valid = io_regs_wakeupProgram_4_write_valid;
assign core_io_regs_wakeupProgram_4_write_bits = io_regs_wakeupProgram_4_write_bits;
assign core_io_regs_wakeupProgram_5_write_valid = io_regs_wakeupProgram_5_write_valid;
assign core_io_regs_wakeupProgram_5_write_bits = io_regs_wakeupProgram_5_write_bits;
assign core_io_regs_wakeupProgram_6_write_valid = io_regs_wakeupProgram_6_write_valid;
assign core_io_regs_wakeupProgram_6_write_bits = io_regs_wakeupProgram_6_write_bits;
assign core_io_regs_wakeupProgram_7_write_valid = io_regs_wakeupProgram_7_write_valid;
assign core_io_regs_wakeupProgram_7_write_bits = io_regs_wakeupProgram_7_write_bits;
assign core_io_regs_sleepProgram_0_write_valid = io_regs_sleepProgram_0_write_valid;
assign core_io_regs_sleepProgram_0_write_bits = io_regs_sleepProgram_0_write_bits;
assign core_io_regs_sleepProgram_1_write_valid = io_regs_sleepProgram_1_write_valid;
assign core_io_regs_sleepProgram_1_write_bits = io_regs_sleepProgram_1_write_bits;
assign core_io_regs_sleepProgram_2_write_valid = io_regs_sleepProgram_2_write_valid;
assign core_io_regs_sleepProgram_2_write_bits = io_regs_sleepProgram_2_write_bits;
assign core_io_regs_sleepProgram_3_write_valid = io_regs_sleepProgram_3_write_valid;
assign core_io_regs_sleepProgram_3_write_bits = io_regs_sleepProgram_3_write_bits;
assign core_io_regs_sleepProgram_4_write_valid = io_regs_sleepProgram_4_write_valid;
assign core_io_regs_sleepProgram_4_write_bits = io_regs_sleepProgram_4_write_bits;
assign core_io_regs_sleepProgram_5_write_valid = io_regs_sleepProgram_5_write_valid;
assign core_io_regs_sleepProgram_5_write_bits = io_regs_sleepProgram_5_write_bits;
assign core_io_regs_sleepProgram_6_write_valid = io_regs_sleepProgram_6_write_valid;
assign core_io_regs_sleepProgram_6_write_bits = io_regs_sleepProgram_6_write_bits;
assign core_io_regs_sleepProgram_7_write_valid = io_regs_sleepProgram_7_write_valid;
assign core_io_regs_sleepProgram_7_write_bits = io_regs_sleepProgram_7_write_bits;
assign T_358 = {core_io_control_bits_vddpaden,core_io_control_bits_reserved0};
assign T_359 = {core_io_control_bits_hfclkrst,core_io_control_bits_corerst};
assign T_360 = {T_359,core_io_control_bits_reserved1};
assign T_361 = {T_360,T_358};
assign T_362 = ~ T_361;
assign AsyncResetRegVec_1_1_clock = clock;
assign AsyncResetRegVec_1_1_reset = reset;
assign AsyncResetRegVec_1_1_io_d = T_362;
assign AsyncResetRegVec_1_1_io_en = core_io_control_valid;
assign core_io_control_bits = ~ AsyncResetRegVec_1_1_io_q;
assign T_369_hfclkrst = T_379;
assign T_369_corerst = T_378;
assign T_369_reserved1 = T_377;
assign T_369_vddpaden = T_376;
assign T_369_reserved0 = T_375;
assign T_375 = core_io_control_bits[0];
assign T_376 = core_io_control_bits[1];
assign T_377 = core_io_control_bits[2];
assign T_378 = core_io_control_bits[3];
assign T_379 = core_io_control_bits[4];
assign T_380 = {io_resetCauses_wdogrst,io_resetCauses_erst};
assign T_381 = {T_380,io_resetCauses_porrst};
//assign SRLatch_3_reset = T_385;
//assign SRLatch_3_set = T_382;// POR
assign T_382 = T_381[0];// The POR
assign T_383 = T_381[1];// The ERST
assign T_384 = T_381[2];// The WDOG
assign T_385 = T_383 | T_384;
//assign SRLatch_1_1_reset = T_389;
//assign SRLatch_1_1_set = T_383;// ERST
assign T_389 = T_382 | T_384;
//assign SRLatch_2_1_reset = T_393;
//assign SRLatch_2_1_set = T_384;// WDOG
assign T_393 = T_382 | T_383;
//assign T_394 = {SRLatch_2_1_q,SRLatch_1_1_q};
//Bob assign T_395 = {T_394,SRLatch_3_q};
assign T_394 = {rstcause_wdog_r,rstcause_erst_r};
assign T_395 = {T_394,rstcause_por_r};
assign T_396 = T_395[2];
assign T_397 = T_395[1:0];
assign GEN_0 = {{1'd0}, T_396};
assign T_400 = GEN_0 | T_397;
assign T_401 = T_400[1];
assign T_402 = {T_396,T_401};
//Bob: The original code is here
//always @(posedge clock) begin
// T_355 <= reset;
// T_356 <= T_355;
//end
//Bob: Why here need to flop the reset twice? this is not allowed in coding style so just comment it out
always @(posedge clock or posedge reset) begin
if(reset) begin
T_355 <= 1'b1;
T_356 <= 1'b1;
end
else begin
T_355 <= 1'b0;
T_356 <= T_355;
end
end
endmodule
|
module core_ras(//input
clk,
rst,
//inst fetch stage prediction
en_call_in, //in my previous version ,it equals en_ret_addr_in
en_ret_in,//in my previous version ,it equals en_ret_addr_out
ret_addr_in,// which is gened by call inst
// decode stage recover something wrong,which caused by misprediction in btb, in RAS.
recover_push,//previous inst was preded as a JR inst incorrectly.
recover_push_addr,//push back the top return addr to RAs
recover_pop,// previous inst was preded as a jal inst incorrectly.
////output
//inst fetch stage poping top addr
ret_addr_out
);
//parameter
parameter ps2=2'b00;
parameter ps1=2'b01;
parameter pp1=2'b10;
parameter pp2=2'b11;
//input
input clk;
input rst;
input en_call_in;
input en_ret_in;
input [29:0] ret_addr_in;
input recover_push;
input [29:0] recover_push_addr;
input recover_pop;
//output
output [31:0] ret_addr_out;
reg en_RAS_ret;
reg en_RAS_rec;
reg en_pointer;
reg [1:0] ret_addr_out_src;
//reg of RAS
reg [29:0] RAS_1;
reg [29:0] RAS_2;
reg [29:0] RAS_3;
reg [29:0] RAS_4;
reg [29:0] RAS_5;
reg [29:0] RAS_6;
reg [29:0] RAS_7;
reg [29:0] RAS_8;
reg [2:0] pointer;
reg [1:0] pointer_src;
always@(posedge clk)
begin
if(rst)
pointer<=3'b000;
else if(en_pointer&&(pointer_src==ps2))
pointer<=pointer-3'b010;
else if(en_pointer&&(pointer_src==ps1))
pointer<=pointer-3'b001;
else if(en_pointer&&(pointer_src==pp1))
pointer<=pointer+3'b001;
else if(en_pointer&&(pointer_src==pp2))
pointer<=pointer+3'b010;
end
// reg of en vector
reg [7:0] en_pointer_P0;
reg [7:0] en_pointer_P1;
reg [7:0] en_pointer_P2;
//en vector functions
always@(*)
begin
//en_pointer_p0 means enable of pinter
case(pointer)
3'b000:en_pointer_P0=8'b00000001;
3'b001:en_pointer_P0=8'b00000010;
3'b010:en_pointer_P0=8'b00000100;
3'b011:en_pointer_P0=8'b00001000;
3'b100:en_pointer_P0=8'b00010000;
3'b101:en_pointer_P0=8'b00100000;
3'b110:en_pointer_P0=8'b01000000;
3'b111:en_pointer_P0=8'b10000000;
default:en_pointer_P0=8'b00000000;
endcase
//en_pointer_p1 means enable of pinter+1
case(pointer)
3'b111:en_pointer_P1=8'b00000001;
3'b000:en_pointer_P1=8'b00000010;
3'b001:en_pointer_P1=8'b00000100;
3'b010:en_pointer_P1=8'b00001000;
3'b011:en_pointer_P1=8'b00010000;
3'b100:en_pointer_P1=8'b00100000;
3'b101:en_pointer_P1=8'b01000000;
3'b110:en_pointer_P1=8'b10000000;
default:en_pointer_P1=8'b00000000;
endcase
//en_pointer_p2 means enable of pinter+2
case(pointer)
3'b111:en_pointer_P2=8'b00000010;
3'b000:en_pointer_P2=8'b00000100;
3'b001:en_pointer_P2=8'b00001000;
3'b010:en_pointer_P2=8'b00010000;
3'b011:en_pointer_P2=8'b00100000;
3'b100:en_pointer_P2=8'b01000000;
3'b101:en_pointer_P2=8'b10000000;
3'b110:en_pointer_P2=8'b00000001;
default:en_pointer_P2=8'b00000000;
endcase
end
//control signals for RAS
//reg of en_RAS_ret and en_RAS_rec
always@(*)
begin
//default values
en_RAS_ret=1'b0;
en_RAS_rec=1'b0;
pointer_src=pp2;
en_pointer=1'b0;
ret_addr_out_src=2'b11;
//////////////////////////////////
// when call_in meets recover_push
if(en_call_in&&recover_push)
begin
en_RAS_ret=1'b1;
en_RAS_rec=1'b1;
pointer_src=pp2;
en_pointer=1'b1;
end
else if(en_call_in&&!recover_push&&!recover_pop) //i'm not sure there is nothing wrong
begin
en_RAS_ret=1'b1;
pointer_src=pp1;
en_pointer=1'b1;
end
else if(!en_ret_in&&!en_call_in&&recover_push)
begin
en_RAS_rec=1'b1;
pointer_src=pp1;
en_pointer=1'b1;
end
///////////////////////////////////
//when ret_in meets recover_push
if(en_ret_in&&recover_push)
begin
ret_addr_out_src=2'b00;
end
else if(en_ret_in&&!recover_push&&!recover_pop)
begin
pointer_src=ps1;
en_pointer=1'b1;
ret_addr_out_src=2'b10;
end
////////////////////////////////////
///when call_in meets recover_pop
if(en_call_in&&recover_pop)
begin
en_RAS_ret=1'b1;
end
else if(!en_ret_in&&!en_call_in&&recover_pop)
begin
pointer_src=ps1;
en_pointer=1'b1;
end
////////////////////////////////////
//when ret_in meets recover_pop
if(en_ret_in&&recover_pop)
begin
ret_addr_out_src=2'b01;
pointer_src=ps2;
en_pointer=1'b1;
end
end
///////////////////////////////////
//write RAS_num
//RAS_1
always@(posedge clk)
begin
if(rst)
RAS_1<=30'h00000000;
else if(en_RAS_ret&&(en_pointer_P0[0]||en_pointer_P1[0]||en_pointer_P2[0]))
RAS_1<=ret_addr_in;
else if(en_RAS_rec&&(en_pointer_P2[0]||en_pointer_P1[0]))
RAS_1<=recover_push_addr;
end
//RAS_2
always@(posedge clk)
begin
if(rst)
RAS_2<=30'h00000000;
else if(en_RAS_ret&&(en_pointer_P0[1]||en_pointer_P1[1]||en_pointer_P2[1]))
RAS_2<=ret_addr_in;
else if(en_RAS_rec&&(en_pointer_P2[1]||en_pointer_P1[1]))
RAS_2<=recover_push_addr;
end
//RAS_3
always@(posedge clk)
begin
if(rst)
RAS_3<=30'h00000000;
else if(en_RAS_ret&&(en_pointer_P0[2]||en_pointer_P1[2]||en_pointer_P2[2]))
RAS_3<=ret_addr_in;
else if(en_RAS_rec&&(en_pointer_P2[2]||en_pointer_P1[2]))
RAS_3<=recover_push_addr;
end
//RAS_4
always@(posedge clk)
begin
if(rst)
RAS_4<=30'h00000000;
else if(en_RAS_ret&&(en_pointer_P0[3]||en_pointer_P1[3]||en_pointer_P2[3]))
RAS_4<=ret_addr_in;
else if(en_RAS_rec&&(en_pointer_P2[3]||en_pointer_P1[3]))
RAS_4<=recover_push_addr;
end
//RAS_5
always@(posedge clk)
begin
if(rst)
RAS_5<=30'h00000000;
else if(en_RAS_ret&&(en_pointer_P0[4]||en_pointer_P1[4]||en_pointer_P2[4]))
RAS_5<=ret_addr_in;
else if(en_RAS_rec&&(en_pointer_P2[4]||en_pointer_P1[4]))
RAS_5<=recover_push_addr;
end
//RAS_6
always@(posedge clk)
begin
if(rst)
RAS_6<=30'h00000000;
else if(en_RAS_ret&&(en_pointer_P0[5]||en_pointer_P1[5]||en_pointer_P2[5]))
RAS_6<=ret_addr_in;
else if(en_RAS_rec&&(en_pointer_P2[5]||en_pointer_P1[5]))
RAS_6<=recover_push_addr;
end
//RAS_7
always@(posedge clk)
begin
if(rst)
RAS_7<=30'h00000000;
else if(en_RAS_ret&&(en_pointer_P0[6]||en_pointer_P1[6]||en_pointer_P2[6]))
RAS_7<=ret_addr_in;
else if(en_RAS_rec&&(en_pointer_P2[6]||en_pointer_P1[6]))
RAS_7<=recover_push_addr;
end
//RAS_8
always@(posedge clk)
begin
if(rst)
RAS_8<=30'h00000000;
else if(en_RAS_ret&&(en_pointer_P0[7]||en_pointer_P1[7]||en_pointer_P2[7]))
RAS_8<=ret_addr_in;
else if(en_RAS_rec&&(en_pointer_P2[7]||en_pointer_P1[7]))
RAS_8<=recover_push_addr;
end
//read RAS port of pointer
reg [29:0] pointer_rd_ras;
always@(*)
begin
case(pointer)
3'b000:pointer_rd_ras=RAS_1;
3'b001:pointer_rd_ras=RAS_2;
3'b010:pointer_rd_ras=RAS_3;
3'b011:pointer_rd_ras=RAS_4;
3'b100:pointer_rd_ras=RAS_5;
3'b101:pointer_rd_ras=RAS_6;
3'b110:pointer_rd_ras=RAS_7;
3'b111:pointer_rd_ras=RAS_8;
default:pointer_rd_ras=30'hzzzzzzzz;
endcase
end
//read RAS port of pointere+1
reg [29:0] pointerP1_rd_ras;
always@(*)
begin
case(pointer)
3'b000:pointerP1_rd_ras=RAS_2;
3'b001:pointerP1_rd_ras=RAS_3;
3'b010:pointerP1_rd_ras=RAS_4;
3'b011:pointerP1_rd_ras=RAS_5;
3'b100:pointerP1_rd_ras=RAS_6;
3'b101:pointerP1_rd_ras=RAS_7;
3'b110:pointerP1_rd_ras=RAS_8;
3'b111:pointerP1_rd_ras=RAS_1;
default:pointerP1_rd_ras=30'hzzzzzzzz;
endcase
end
wire [29:0] ret_addr_out_temp;
assign ret_addr_out_temp=(ret_addr_out_src==2'b00)?recover_push_addr:
(ret_addr_out_src==2'b01)?pointer_rd_ras:
(ret_addr_out_src==2'b10)?pointerP1_rd_ras:30'hzzzzzzzz;
assign ret_addr_out={ret_addr_out_temp,2'b00};
endmodule
|
module sky130_fd_sc_ms__o21a (
X ,
A1 ,
A2 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A1 ;
input A2 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire or0_out ;
wire and0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
or or0 (or0_out , A2, A1 );
and and0 (and0_out_X , or0_out, B1 );
sky130_fd_sc_ms__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
|
module eth_macstatus(
MRxClk, Reset, ReceivedLengthOK, ReceiveEnd, ReceivedPacketGood, RxCrcError,
MRxErr, MRxDV, RxStateSFD, RxStateData, RxStatePreamble, RxStateIdle, Transmitting,
RxByteCnt, RxByteCntEq0, RxByteCntGreat2, RxByteCntMaxFrame,
InvalidSymbol, MRxD, LatchedCrcError, Collision, CollValid, RxLateCollision,
r_RecSmall, r_MinFL, r_MaxFL, ShortFrame, DribbleNibble, ReceivedPacketTooBig, r_HugEn,
LoadRxStatus, StartTxDone, StartTxAbort, RetryCnt, RetryCntLatched, MTxClk, MaxCollisionOccured,
RetryLimit, LateCollision, LateCollLatched, DeferIndication, DeferLatched, RstDeferLatched, TxStartFrm,
StatePreamble, StateData, CarrierSense, CarrierSenseLost, TxUsedData, LatchedMRxErr, Loopback,
r_FullD
);
parameter Tp = 1;
input MRxClk;
input Reset;
input RxCrcError;
input MRxErr;
input MRxDV;
input RxStateSFD;
input [1:0] RxStateData;
input RxStatePreamble;
input RxStateIdle;
input Transmitting;
input [15:0] RxByteCnt;
input RxByteCntEq0;
input RxByteCntGreat2;
input RxByteCntMaxFrame;
input [3:0] MRxD;
input Collision;
input [5:0] CollValid;
input r_RecSmall;
input [15:0] r_MinFL;
input [15:0] r_MaxFL;
input r_HugEn;
input StartTxDone;
input StartTxAbort;
input [3:0] RetryCnt;
input MTxClk;
input MaxCollisionOccured;
input LateCollision;
input DeferIndication;
input TxStartFrm;
input StatePreamble;
input [1:0] StateData;
input CarrierSense;
input TxUsedData;
input Loopback;
input r_FullD;
output ReceivedLengthOK;
output ReceiveEnd;
output ReceivedPacketGood;
output InvalidSymbol;
output LatchedCrcError;
output RxLateCollision;
output ShortFrame;
output DribbleNibble;
output ReceivedPacketTooBig;
output LoadRxStatus;
output [3:0] RetryCntLatched;
output RetryLimit;
output LateCollLatched;
output DeferLatched;
input RstDeferLatched;
output CarrierSenseLost;
output LatchedMRxErr;
reg ReceiveEnd;
reg LatchedCrcError;
reg LatchedMRxErr;
reg LoadRxStatus;
reg InvalidSymbol;
reg [3:0] RetryCntLatched;
reg RetryLimit;
reg LateCollLatched;
reg DeferLatched;
reg CarrierSenseLost;
wire TakeSample;
wire SetInvalidSymbol; // Invalid symbol was received during reception in 100Mbps
// Crc error
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
LatchedCrcError <=#Tp 1'b0;
else
if(RxStateSFD)
LatchedCrcError <=#Tp 1'b0;
else
if(RxStateData[0])
LatchedCrcError <=#Tp RxCrcError & ~RxByteCntEq0;
end
// LatchedMRxErr
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
LatchedMRxErr <=#Tp 1'b0;
else
if(MRxErr & MRxDV & (RxStatePreamble | RxStateSFD | (|RxStateData) | RxStateIdle & ~Transmitting))
LatchedMRxErr <=#Tp 1'b1;
else
LatchedMRxErr <=#Tp 1'b0;
end
// ReceivedPacketGood
assign ReceivedPacketGood = ~LatchedCrcError;
// ReceivedLengthOK
assign ReceivedLengthOK = RxByteCnt[15:0] >= r_MinFL[15:0] & RxByteCnt[15:0] <= r_MaxFL[15:0];
// Time to take a sample
//assign TakeSample = |RxStateData & ~MRxDV & RxByteCntGreat2 |
assign TakeSample = (|RxStateData) & (~MRxDV) |
RxStateData[0] & MRxDV & RxByteCntMaxFrame;
// LoadRxStatus
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
LoadRxStatus <=#Tp 1'b0;
else
LoadRxStatus <=#Tp TakeSample;
end
// ReceiveEnd
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
ReceiveEnd <=#Tp 1'b0;
else
ReceiveEnd <=#Tp LoadRxStatus;
end
// Invalid Symbol received during 100Mbps mode
assign SetInvalidSymbol = MRxDV & MRxErr & MRxD[3:0] == 4'he;
// InvalidSymbol
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
InvalidSymbol <=#Tp 1'b0;
else
if(LoadRxStatus & ~SetInvalidSymbol)
InvalidSymbol <=#Tp 1'b0;
else
if(SetInvalidSymbol)
InvalidSymbol <=#Tp 1'b1;
end
// Late Collision
reg RxLateCollision;
reg RxColWindow;
// Collision Window
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
RxLateCollision <=#Tp 1'b0;
else
if(LoadRxStatus)
RxLateCollision <=#Tp 1'b0;
else
if(Collision & (~r_FullD) & (~RxColWindow | r_RecSmall))
RxLateCollision <=#Tp 1'b1;
end
// Collision Window
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
RxColWindow <=#Tp 1'b1;
else
if(~Collision & RxByteCnt[5:0] == CollValid[5:0] & RxStateData[1])
RxColWindow <=#Tp 1'b0;
else
if(RxStateIdle)
RxColWindow <=#Tp 1'b1;
end
// ShortFrame
reg ShortFrame;
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
ShortFrame <=#Tp 1'b0;
else
if(LoadRxStatus)
ShortFrame <=#Tp 1'b0;
else
if(TakeSample)
ShortFrame <=#Tp RxByteCnt[15:0] < r_MinFL[15:0];
end
// DribbleNibble
reg DribbleNibble;
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
DribbleNibble <=#Tp 1'b0;
else
if(RxStateSFD)
DribbleNibble <=#Tp 1'b0;
else
if(~MRxDV & RxStateData[1])
DribbleNibble <=#Tp 1'b1;
end
reg ReceivedPacketTooBig;
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
ReceivedPacketTooBig <=#Tp 1'b0;
else
if(LoadRxStatus)
ReceivedPacketTooBig <=#Tp 1'b0;
else
if(TakeSample)
ReceivedPacketTooBig <=#Tp ~r_HugEn & RxByteCnt[15:0] > r_MaxFL[15:0];
end
// Latched Retry counter for tx status
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
RetryCntLatched <=#Tp 4'h0;
else
if(StartTxDone | StartTxAbort)
RetryCntLatched <=#Tp RetryCnt;
end
// Latched Retransmission limit
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
RetryLimit <=#Tp 1'h0;
else
if(StartTxDone | StartTxAbort)
RetryLimit <=#Tp MaxCollisionOccured;
end
// Latched Late Collision
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
LateCollLatched <=#Tp 1'b0;
else
if(StartTxDone | StartTxAbort)
LateCollLatched <=#Tp LateCollision;
end
// Latched Defer state
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
DeferLatched <=#Tp 1'b0;
else
if(DeferIndication)
DeferLatched <=#Tp 1'b1;
else
if(RstDeferLatched)
DeferLatched <=#Tp 1'b0;
end
// CarrierSenseLost
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
CarrierSenseLost <=#Tp 1'b0;
else
if((StatePreamble | (|StateData)) & ~CarrierSense & ~Loopback & ~Collision & ~r_FullD)
CarrierSenseLost <=#Tp 1'b1;
else
if(TxStartFrm)
CarrierSenseLost <=#Tp 1'b0;
end
endmodule
|
module sky130_fd_sc_hvl__sdlclkp (
GCLK,
SCE ,
GATE,
CLK
);
// Module ports
output GCLK;
input SCE ;
input GATE;
input CLK ;
// Local signals
wire m0 ;
wire m0n ;
wire clkn ;
wire SCE_GATE;
// Name Output Other arguments
not not0 (m0n , m0 );
not not1 (clkn , CLK );
nor nor0 (SCE_GATE, GATE, SCE );
sky130_fd_sc_hvl__udp_dlatch$P dlatch0 (m0 , SCE_GATE, clkn );
and and0 (GCLK , m0n, CLK );
endmodule
|
module sky130_fd_sc_ls__ebufn (
Z ,
A ,
TE_B,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Z ;
input A ;
input TE_B;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire pwrgood_pp0_out_A ;
wire pwrgood_pp1_out_teb;
// Name Output Other arguments
sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_A , A, VPWR, VGND );
sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp1 (pwrgood_pp1_out_teb, TE_B, VPWR, VGND );
bufif0 bufif00 (Z , pwrgood_pp0_out_A, pwrgood_pp1_out_teb);
endmodule
|
module sky130_fd_sc_lp__xor3 (
//# {{data|Data Signals}}
input A ,
input B ,
input C ,
output X ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
|
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix
(clk,
rst,
din,
wr_en,
rd_en,
dout,
full,
empty);
(* x_interface_info = "xilinx.com:signal:clock:1.0 core_clk CLK" *) input clk;
input rst;
(* x_interface_info = "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_DATA" *) input [63:0]din;
(* x_interface_info = "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_EN" *) input wr_en;
(* x_interface_info = "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_EN" *) input rd_en;
(* x_interface_info = "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_DATA" *) output [63:0]dout;
(* x_interface_info = "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE FULL" *) output full;
(* x_interface_info = "xilinx.com:interface:fifo_read:1.0 FIFO_READ EMPTY" *) output empty;
wire clk;
wire [63:0]din;
wire [63:0]dout;
wire empty;
wire full;
wire rd_en;
wire rst;
wire wr_en;
wire NLW_U0_almost_empty_UNCONNECTED;
wire NLW_U0_almost_full_UNCONNECTED;
wire NLW_U0_axi_ar_dbiterr_UNCONNECTED;
wire NLW_U0_axi_ar_overflow_UNCONNECTED;
wire NLW_U0_axi_ar_prog_empty_UNCONNECTED;
wire NLW_U0_axi_ar_prog_full_UNCONNECTED;
wire NLW_U0_axi_ar_sbiterr_UNCONNECTED;
wire NLW_U0_axi_ar_underflow_UNCONNECTED;
wire NLW_U0_axi_aw_dbiterr_UNCONNECTED;
wire NLW_U0_axi_aw_overflow_UNCONNECTED;
wire NLW_U0_axi_aw_prog_empty_UNCONNECTED;
wire NLW_U0_axi_aw_prog_full_UNCONNECTED;
wire NLW_U0_axi_aw_sbiterr_UNCONNECTED;
wire NLW_U0_axi_aw_underflow_UNCONNECTED;
wire NLW_U0_axi_b_dbiterr_UNCONNECTED;
wire NLW_U0_axi_b_overflow_UNCONNECTED;
wire NLW_U0_axi_b_prog_empty_UNCONNECTED;
wire NLW_U0_axi_b_prog_full_UNCONNECTED;
wire NLW_U0_axi_b_sbiterr_UNCONNECTED;
wire NLW_U0_axi_b_underflow_UNCONNECTED;
wire NLW_U0_axi_r_dbiterr_UNCONNECTED;
wire NLW_U0_axi_r_overflow_UNCONNECTED;
wire NLW_U0_axi_r_prog_empty_UNCONNECTED;
wire NLW_U0_axi_r_prog_full_UNCONNECTED;
wire NLW_U0_axi_r_sbiterr_UNCONNECTED;
wire NLW_U0_axi_r_underflow_UNCONNECTED;
wire NLW_U0_axi_w_dbiterr_UNCONNECTED;
wire NLW_U0_axi_w_overflow_UNCONNECTED;
wire NLW_U0_axi_w_prog_empty_UNCONNECTED;
wire NLW_U0_axi_w_prog_full_UNCONNECTED;
wire NLW_U0_axi_w_sbiterr_UNCONNECTED;
wire NLW_U0_axi_w_underflow_UNCONNECTED;
wire NLW_U0_axis_dbiterr_UNCONNECTED;
wire NLW_U0_axis_overflow_UNCONNECTED;
wire NLW_U0_axis_prog_empty_UNCONNECTED;
wire NLW_U0_axis_prog_full_UNCONNECTED;
wire NLW_U0_axis_sbiterr_UNCONNECTED;
wire NLW_U0_axis_underflow_UNCONNECTED;
wire NLW_U0_dbiterr_UNCONNECTED;
wire NLW_U0_m_axi_arvalid_UNCONNECTED;
wire NLW_U0_m_axi_awvalid_UNCONNECTED;
wire NLW_U0_m_axi_bready_UNCONNECTED;
wire NLW_U0_m_axi_rready_UNCONNECTED;
wire NLW_U0_m_axi_wlast_UNCONNECTED;
wire NLW_U0_m_axi_wvalid_UNCONNECTED;
wire NLW_U0_m_axis_tlast_UNCONNECTED;
wire NLW_U0_m_axis_tvalid_UNCONNECTED;
wire NLW_U0_overflow_UNCONNECTED;
wire NLW_U0_prog_empty_UNCONNECTED;
wire NLW_U0_prog_full_UNCONNECTED;
wire NLW_U0_rd_rst_busy_UNCONNECTED;
wire NLW_U0_s_axi_arready_UNCONNECTED;
wire NLW_U0_s_axi_awready_UNCONNECTED;
wire NLW_U0_s_axi_bvalid_UNCONNECTED;
wire NLW_U0_s_axi_rlast_UNCONNECTED;
wire NLW_U0_s_axi_rvalid_UNCONNECTED;
wire NLW_U0_s_axi_wready_UNCONNECTED;
wire NLW_U0_s_axis_tready_UNCONNECTED;
wire NLW_U0_sbiterr_UNCONNECTED;
wire NLW_U0_underflow_UNCONNECTED;
wire NLW_U0_valid_UNCONNECTED;
wire NLW_U0_wr_ack_UNCONNECTED;
wire NLW_U0_wr_rst_busy_UNCONNECTED;
wire [4:0]NLW_U0_axi_ar_data_count_UNCONNECTED;
wire [4:0]NLW_U0_axi_ar_rd_data_count_UNCONNECTED;
wire [4:0]NLW_U0_axi_ar_wr_data_count_UNCONNECTED;
wire [4:0]NLW_U0_axi_aw_data_count_UNCONNECTED;
wire [4:0]NLW_U0_axi_aw_rd_data_count_UNCONNECTED;
wire [4:0]NLW_U0_axi_aw_wr_data_count_UNCONNECTED;
wire [4:0]NLW_U0_axi_b_data_count_UNCONNECTED;
wire [4:0]NLW_U0_axi_b_rd_data_count_UNCONNECTED;
wire [4:0]NLW_U0_axi_b_wr_data_count_UNCONNECTED;
wire [10:0]NLW_U0_axi_r_data_count_UNCONNECTED;
wire [10:0]NLW_U0_axi_r_rd_data_count_UNCONNECTED;
wire [10:0]NLW_U0_axi_r_wr_data_count_UNCONNECTED;
wire [10:0]NLW_U0_axi_w_data_count_UNCONNECTED;
wire [10:0]NLW_U0_axi_w_rd_data_count_UNCONNECTED;
wire [10:0]NLW_U0_axi_w_wr_data_count_UNCONNECTED;
wire [10:0]NLW_U0_axis_data_count_UNCONNECTED;
wire [10:0]NLW_U0_axis_rd_data_count_UNCONNECTED;
wire [10:0]NLW_U0_axis_wr_data_count_UNCONNECTED;
wire [10:0]NLW_U0_data_count_UNCONNECTED;
wire [31:0]NLW_U0_m_axi_araddr_UNCONNECTED;
wire [1:0]NLW_U0_m_axi_arburst_UNCONNECTED;
wire [3:0]NLW_U0_m_axi_arcache_UNCONNECTED;
wire [0:0]NLW_U0_m_axi_arid_UNCONNECTED;
wire [7:0]NLW_U0_m_axi_arlen_UNCONNECTED;
wire [0:0]NLW_U0_m_axi_arlock_UNCONNECTED;
wire [2:0]NLW_U0_m_axi_arprot_UNCONNECTED;
wire [3:0]NLW_U0_m_axi_arqos_UNCONNECTED;
wire [3:0]NLW_U0_m_axi_arregion_UNCONNECTED;
wire [2:0]NLW_U0_m_axi_arsize_UNCONNECTED;
wire [0:0]NLW_U0_m_axi_aruser_UNCONNECTED;
wire [31:0]NLW_U0_m_axi_awaddr_UNCONNECTED;
wire [1:0]NLW_U0_m_axi_awburst_UNCONNECTED;
wire [3:0]NLW_U0_m_axi_awcache_UNCONNECTED;
wire [0:0]NLW_U0_m_axi_awid_UNCONNECTED;
wire [7:0]NLW_U0_m_axi_awlen_UNCONNECTED;
wire [0:0]NLW_U0_m_axi_awlock_UNCONNECTED;
wire [2:0]NLW_U0_m_axi_awprot_UNCONNECTED;
wire [3:0]NLW_U0_m_axi_awqos_UNCONNECTED;
wire [3:0]NLW_U0_m_axi_awregion_UNCONNECTED;
wire [2:0]NLW_U0_m_axi_awsize_UNCONNECTED;
wire [0:0]NLW_U0_m_axi_awuser_UNCONNECTED;
wire [63:0]NLW_U0_m_axi_wdata_UNCONNECTED;
wire [0:0]NLW_U0_m_axi_wid_UNCONNECTED;
wire [7:0]NLW_U0_m_axi_wstrb_UNCONNECTED;
wire [0:0]NLW_U0_m_axi_wuser_UNCONNECTED;
wire [7:0]NLW_U0_m_axis_tdata_UNCONNECTED;
wire [0:0]NLW_U0_m_axis_tdest_UNCONNECTED;
wire [0:0]NLW_U0_m_axis_tid_UNCONNECTED;
wire [0:0]NLW_U0_m_axis_tkeep_UNCONNECTED;
wire [0:0]NLW_U0_m_axis_tstrb_UNCONNECTED;
wire [3:0]NLW_U0_m_axis_tuser_UNCONNECTED;
wire [10:0]NLW_U0_rd_data_count_UNCONNECTED;
wire [0:0]NLW_U0_s_axi_bid_UNCONNECTED;
wire [1:0]NLW_U0_s_axi_bresp_UNCONNECTED;
wire [0:0]NLW_U0_s_axi_buser_UNCONNECTED;
wire [63:0]NLW_U0_s_axi_rdata_UNCONNECTED;
wire [0:0]NLW_U0_s_axi_rid_UNCONNECTED;
wire [1:0]NLW_U0_s_axi_rresp_UNCONNECTED;
wire [0:0]NLW_U0_s_axi_ruser_UNCONNECTED;
wire [10:0]NLW_U0_wr_data_count_UNCONNECTED;
(* C_ADD_NGC_CONSTRAINT = "0" *)
(* C_APPLICATION_TYPE_AXIS = "0" *)
(* C_APPLICATION_TYPE_RACH = "0" *)
(* C_APPLICATION_TYPE_RDCH = "0" *)
(* C_APPLICATION_TYPE_WACH = "0" *)
(* C_APPLICATION_TYPE_WDCH = "0" *)
(* C_APPLICATION_TYPE_WRCH = "0" *)
(* C_AXIS_TDATA_WIDTH = "8" *)
(* C_AXIS_TDEST_WIDTH = "1" *)
(* C_AXIS_TID_WIDTH = "1" *)
(* C_AXIS_TKEEP_WIDTH = "1" *)
(* C_AXIS_TSTRB_WIDTH = "1" *)
(* C_AXIS_TUSER_WIDTH = "4" *)
(* C_AXIS_TYPE = "0" *)
(* C_AXI_ADDR_WIDTH = "32" *)
(* C_AXI_ARUSER_WIDTH = "1" *)
(* C_AXI_AWUSER_WIDTH = "1" *)
(* C_AXI_BUSER_WIDTH = "1" *)
(* C_AXI_DATA_WIDTH = "64" *)
(* C_AXI_ID_WIDTH = "1" *)
(* C_AXI_LEN_WIDTH = "8" *)
(* C_AXI_LOCK_WIDTH = "1" *)
(* C_AXI_RUSER_WIDTH = "1" *)
(* C_AXI_TYPE = "1" *)
(* C_AXI_WUSER_WIDTH = "1" *)
(* C_COMMON_CLOCK = "1" *)
(* C_COUNT_TYPE = "0" *)
(* C_DATA_COUNT_WIDTH = "11" *)
(* C_DEFAULT_VALUE = "BlankString" *)
(* C_DIN_WIDTH = "64" *)
(* C_DIN_WIDTH_AXIS = "1" *)
(* C_DIN_WIDTH_RACH = "32" *)
(* C_DIN_WIDTH_RDCH = "64" *)
(* C_DIN_WIDTH_WACH = "1" *)
(* C_DIN_WIDTH_WDCH = "64" *)
(* C_DIN_WIDTH_WRCH = "2" *)
(* C_DOUT_RST_VAL = "0" *)
(* C_DOUT_WIDTH = "64" *)
(* C_ENABLE_RLOCS = "0" *)
(* C_ENABLE_RST_SYNC = "1" *)
(* C_EN_SAFETY_CKT = "0" *)
(* C_ERROR_INJECTION_TYPE = "0" *)
(* C_ERROR_INJECTION_TYPE_AXIS = "0" *)
(* C_ERROR_INJECTION_TYPE_RACH = "0" *)
(* C_ERROR_INJECTION_TYPE_RDCH = "0" *)
(* C_ERROR_INJECTION_TYPE_WACH = "0" *)
(* C_ERROR_INJECTION_TYPE_WDCH = "0" *)
(* C_ERROR_INJECTION_TYPE_WRCH = "0" *)
(* C_FAMILY = "kintex7" *)
(* C_FULL_FLAGS_RST_VAL = "1" *)
(* C_HAS_ALMOST_EMPTY = "0" *)
(* C_HAS_ALMOST_FULL = "0" *)
(* C_HAS_AXIS_TDATA = "1" *)
(* C_HAS_AXIS_TDEST = "0" *)
(* C_HAS_AXIS_TID = "0" *)
(* C_HAS_AXIS_TKEEP = "0" *)
(* C_HAS_AXIS_TLAST = "0" *)
(* C_HAS_AXIS_TREADY = "1" *)
(* C_HAS_AXIS_TSTRB = "0" *)
(* C_HAS_AXIS_TUSER = "1" *)
(* C_HAS_AXI_ARUSER = "0" *)
(* C_HAS_AXI_AWUSER = "0" *)
(* C_HAS_AXI_BUSER = "0" *)
(* C_HAS_AXI_ID = "0" *)
(* C_HAS_AXI_RD_CHANNEL = "1" *)
(* C_HAS_AXI_RUSER = "0" *)
(* C_HAS_AXI_WR_CHANNEL = "1" *)
(* C_HAS_AXI_WUSER = "0" *)
(* C_HAS_BACKUP = "0" *)
(* C_HAS_DATA_COUNT = "0" *)
(* C_HAS_DATA_COUNTS_AXIS = "0" *)
(* C_HAS_DATA_COUNTS_RACH = "0" *)
(* C_HAS_DATA_COUNTS_RDCH = "0" *)
(* C_HAS_DATA_COUNTS_WACH = "0" *)
(* C_HAS_DATA_COUNTS_WDCH = "0" *)
(* C_HAS_DATA_COUNTS_WRCH = "0" *)
(* C_HAS_INT_CLK = "0" *)
(* C_HAS_MASTER_CE = "0" *)
(* C_HAS_MEMINIT_FILE = "0" *)
(* C_HAS_OVERFLOW = "0" *)
(* C_HAS_PROG_FLAGS_AXIS = "0" *)
(* C_HAS_PROG_FLAGS_RACH = "0" *)
(* C_HAS_PROG_FLAGS_RDCH = "0" *)
(* C_HAS_PROG_FLAGS_WACH = "0" *)
(* C_HAS_PROG_FLAGS_WDCH = "0" *)
(* C_HAS_PROG_FLAGS_WRCH = "0" *)
(* C_HAS_RD_DATA_COUNT = "0" *)
(* C_HAS_RD_RST = "0" *)
(* C_HAS_RST = "1" *)
(* C_HAS_SLAVE_CE = "0" *)
(* C_HAS_SRST = "0" *)
(* C_HAS_UNDERFLOW = "0" *)
(* C_HAS_VALID = "0" *)
(* C_HAS_WR_ACK = "0" *)
(* C_HAS_WR_DATA_COUNT = "0" *)
(* C_HAS_WR_RST = "0" *)
(* C_IMPLEMENTATION_TYPE = "0" *)
(* C_IMPLEMENTATION_TYPE_AXIS = "1" *)
(* C_IMPLEMENTATION_TYPE_RACH = "1" *)
(* C_IMPLEMENTATION_TYPE_RDCH = "1" *)
(* C_IMPLEMENTATION_TYPE_WACH = "1" *)
(* C_IMPLEMENTATION_TYPE_WDCH = "1" *)
(* C_IMPLEMENTATION_TYPE_WRCH = "1" *)
(* C_INIT_WR_PNTR_VAL = "0" *)
(* C_INTERFACE_TYPE = "0" *)
(* C_MEMORY_TYPE = "1" *)
(* C_MIF_FILE_NAME = "BlankString" *)
(* C_MSGON_VAL = "1" *)
(* C_OPTIMIZATION_MODE = "0" *)
(* C_OVERFLOW_LOW = "0" *)
(* C_POWER_SAVING_MODE = "0" *)
(* C_PRELOAD_LATENCY = "1" *)
(* C_PRELOAD_REGS = "0" *)
(* C_PRIM_FIFO_TYPE = "2kx18" *)
(* C_PRIM_FIFO_TYPE_AXIS = "1kx18" *)
(* C_PRIM_FIFO_TYPE_RACH = "512x36" *)
(* C_PRIM_FIFO_TYPE_RDCH = "1kx36" *)
(* C_PRIM_FIFO_TYPE_WACH = "512x36" *)
(* C_PRIM_FIFO_TYPE_WDCH = "1kx36" *)
(* C_PRIM_FIFO_TYPE_WRCH = "512x36" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL = "2" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS = "1022" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH = "1022" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH = "1022" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH = "1022" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH = "1022" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH = "1022" *)
(* C_PROG_EMPTY_THRESH_NEGATE_VAL = "3" *)
(* C_PROG_EMPTY_TYPE = "0" *)
(* C_PROG_EMPTY_TYPE_AXIS = "0" *)
(* C_PROG_EMPTY_TYPE_RACH = "0" *)
(* C_PROG_EMPTY_TYPE_RDCH = "0" *)
(* C_PROG_EMPTY_TYPE_WACH = "0" *)
(* C_PROG_EMPTY_TYPE_WDCH = "0" *)
(* C_PROG_EMPTY_TYPE_WRCH = "0" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL = "2046" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL_AXIS = "1023" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL_RACH = "1023" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL_RDCH = "1023" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL_WACH = "1023" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL_WDCH = "1023" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL_WRCH = "1023" *)
(* C_PROG_FULL_THRESH_NEGATE_VAL = "2045" *)
(* C_PROG_FULL_TYPE = "0" *)
(* C_PROG_FULL_TYPE_AXIS = "0" *)
(* C_PROG_FULL_TYPE_RACH = "0" *)
(* C_PROG_FULL_TYPE_RDCH = "0" *)
(* C_PROG_FULL_TYPE_WACH = "0" *)
(* C_PROG_FULL_TYPE_WDCH = "0" *)
(* C_PROG_FULL_TYPE_WRCH = "0" *)
(* C_RACH_TYPE = "0" *)
(* C_RDCH_TYPE = "0" *)
(* C_RD_DATA_COUNT_WIDTH = "11" *)
(* C_RD_DEPTH = "2048" *)
(* C_RD_FREQ = "1" *)
(* C_RD_PNTR_WIDTH = "11" *)
(* C_REG_SLICE_MODE_AXIS = "0" *)
(* C_REG_SLICE_MODE_RACH = "0" *)
(* C_REG_SLICE_MODE_RDCH = "0" *)
(* C_REG_SLICE_MODE_WACH = "0" *)
(* C_REG_SLICE_MODE_WDCH = "0" *)
(* C_REG_SLICE_MODE_WRCH = "0" *)
(* C_SELECT_XPM = "0" *)
(* C_SYNCHRONIZER_STAGE = "2" *)
(* C_UNDERFLOW_LOW = "0" *)
(* C_USE_COMMON_OVERFLOW = "0" *)
(* C_USE_COMMON_UNDERFLOW = "0" *)
(* C_USE_DEFAULT_SETTINGS = "0" *)
(* C_USE_DOUT_RST = "1" *)
(* C_USE_ECC = "0" *)
(* C_USE_ECC_AXIS = "0" *)
(* C_USE_ECC_RACH = "0" *)
(* C_USE_ECC_RDCH = "0" *)
(* C_USE_ECC_WACH = "0" *)
(* C_USE_ECC_WDCH = "0" *)
(* C_USE_ECC_WRCH = "0" *)
(* C_USE_EMBEDDED_REG = "0" *)
(* C_USE_FIFO16_FLAGS = "0" *)
(* C_USE_FWFT_DATA_COUNT = "0" *)
(* C_USE_PIPELINE_REG = "0" *)
(* C_VALID_LOW = "0" *)
(* C_WACH_TYPE = "0" *)
(* C_WDCH_TYPE = "0" *)
(* C_WRCH_TYPE = "0" *)
(* C_WR_ACK_LOW = "0" *)
(* C_WR_DATA_COUNT_WIDTH = "11" *)
(* C_WR_DEPTH = "2048" *)
(* C_WR_DEPTH_AXIS = "1024" *)
(* C_WR_DEPTH_RACH = "16" *)
(* C_WR_DEPTH_RDCH = "1024" *)
(* C_WR_DEPTH_WACH = "16" *)
(* C_WR_DEPTH_WDCH = "1024" *)
(* C_WR_DEPTH_WRCH = "16" *)
(* C_WR_FREQ = "1" *)
(* C_WR_PNTR_WIDTH = "11" *)
(* C_WR_PNTR_WIDTH_AXIS = "10" *)
(* C_WR_PNTR_WIDTH_RACH = "4" *)
(* C_WR_PNTR_WIDTH_RDCH = "10" *)
(* C_WR_PNTR_WIDTH_WACH = "4" *)
(* C_WR_PNTR_WIDTH_WDCH = "10" *)
(* C_WR_PNTR_WIDTH_WRCH = "4" *)
(* C_WR_RESPONSE_LATENCY = "1" *)
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 U0
(.almost_empty(NLW_U0_almost_empty_UNCONNECTED),
.almost_full(NLW_U0_almost_full_UNCONNECTED),
.axi_ar_data_count(NLW_U0_axi_ar_data_count_UNCONNECTED[4:0]),
.axi_ar_dbiterr(NLW_U0_axi_ar_dbiterr_UNCONNECTED),
.axi_ar_injectdbiterr(1'b0),
.axi_ar_injectsbiterr(1'b0),
.axi_ar_overflow(NLW_U0_axi_ar_overflow_UNCONNECTED),
.axi_ar_prog_empty(NLW_U0_axi_ar_prog_empty_UNCONNECTED),
.axi_ar_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0}),
.axi_ar_prog_full(NLW_U0_axi_ar_prog_full_UNCONNECTED),
.axi_ar_prog_full_thresh({1'b0,1'b0,1'b0,1'b0}),
.axi_ar_rd_data_count(NLW_U0_axi_ar_rd_data_count_UNCONNECTED[4:0]),
.axi_ar_sbiterr(NLW_U0_axi_ar_sbiterr_UNCONNECTED),
.axi_ar_underflow(NLW_U0_axi_ar_underflow_UNCONNECTED),
.axi_ar_wr_data_count(NLW_U0_axi_ar_wr_data_count_UNCONNECTED[4:0]),
.axi_aw_data_count(NLW_U0_axi_aw_data_count_UNCONNECTED[4:0]),
.axi_aw_dbiterr(NLW_U0_axi_aw_dbiterr_UNCONNECTED),
.axi_aw_injectdbiterr(1'b0),
.axi_aw_injectsbiterr(1'b0),
.axi_aw_overflow(NLW_U0_axi_aw_overflow_UNCONNECTED),
.axi_aw_prog_empty(NLW_U0_axi_aw_prog_empty_UNCONNECTED),
.axi_aw_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0}),
.axi_aw_prog_full(NLW_U0_axi_aw_prog_full_UNCONNECTED),
.axi_aw_prog_full_thresh({1'b0,1'b0,1'b0,1'b0}),
.axi_aw_rd_data_count(NLW_U0_axi_aw_rd_data_count_UNCONNECTED[4:0]),
.axi_aw_sbiterr(NLW_U0_axi_aw_sbiterr_UNCONNECTED),
.axi_aw_underflow(NLW_U0_axi_aw_underflow_UNCONNECTED),
.axi_aw_wr_data_count(NLW_U0_axi_aw_wr_data_count_UNCONNECTED[4:0]),
.axi_b_data_count(NLW_U0_axi_b_data_count_UNCONNECTED[4:0]),
.axi_b_dbiterr(NLW_U0_axi_b_dbiterr_UNCONNECTED),
.axi_b_injectdbiterr(1'b0),
.axi_b_injectsbiterr(1'b0),
.axi_b_overflow(NLW_U0_axi_b_overflow_UNCONNECTED),
.axi_b_prog_empty(NLW_U0_axi_b_prog_empty_UNCONNECTED),
.axi_b_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0}),
.axi_b_prog_full(NLW_U0_axi_b_prog_full_UNCONNECTED),
.axi_b_prog_full_thresh({1'b0,1'b0,1'b0,1'b0}),
.axi_b_rd_data_count(NLW_U0_axi_b_rd_data_count_UNCONNECTED[4:0]),
.axi_b_sbiterr(NLW_U0_axi_b_sbiterr_UNCONNECTED),
.axi_b_underflow(NLW_U0_axi_b_underflow_UNCONNECTED),
.axi_b_wr_data_count(NLW_U0_axi_b_wr_data_count_UNCONNECTED[4:0]),
.axi_r_data_count(NLW_U0_axi_r_data_count_UNCONNECTED[10:0]),
.axi_r_dbiterr(NLW_U0_axi_r_dbiterr_UNCONNECTED),
.axi_r_injectdbiterr(1'b0),
.axi_r_injectsbiterr(1'b0),
.axi_r_overflow(NLW_U0_axi_r_overflow_UNCONNECTED),
.axi_r_prog_empty(NLW_U0_axi_r_prog_empty_UNCONNECTED),
.axi_r_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.axi_r_prog_full(NLW_U0_axi_r_prog_full_UNCONNECTED),
.axi_r_prog_full_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.axi_r_rd_data_count(NLW_U0_axi_r_rd_data_count_UNCONNECTED[10:0]),
.axi_r_sbiterr(NLW_U0_axi_r_sbiterr_UNCONNECTED),
.axi_r_underflow(NLW_U0_axi_r_underflow_UNCONNECTED),
.axi_r_wr_data_count(NLW_U0_axi_r_wr_data_count_UNCONNECTED[10:0]),
.axi_w_data_count(NLW_U0_axi_w_data_count_UNCONNECTED[10:0]),
.axi_w_dbiterr(NLW_U0_axi_w_dbiterr_UNCONNECTED),
.axi_w_injectdbiterr(1'b0),
.axi_w_injectsbiterr(1'b0),
.axi_w_overflow(NLW_U0_axi_w_overflow_UNCONNECTED),
.axi_w_prog_empty(NLW_U0_axi_w_prog_empty_UNCONNECTED),
.axi_w_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.axi_w_prog_full(NLW_U0_axi_w_prog_full_UNCONNECTED),
.axi_w_prog_full_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.axi_w_rd_data_count(NLW_U0_axi_w_rd_data_count_UNCONNECTED[10:0]),
.axi_w_sbiterr(NLW_U0_axi_w_sbiterr_UNCONNECTED),
.axi_w_underflow(NLW_U0_axi_w_underflow_UNCONNECTED),
.axi_w_wr_data_count(NLW_U0_axi_w_wr_data_count_UNCONNECTED[10:0]),
.axis_data_count(NLW_U0_axis_data_count_UNCONNECTED[10:0]),
.axis_dbiterr(NLW_U0_axis_dbiterr_UNCONNECTED),
.axis_injectdbiterr(1'b0),
.axis_injectsbiterr(1'b0),
.axis_overflow(NLW_U0_axis_overflow_UNCONNECTED),
.axis_prog_empty(NLW_U0_axis_prog_empty_UNCONNECTED),
.axis_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.axis_prog_full(NLW_U0_axis_prog_full_UNCONNECTED),
.axis_prog_full_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.axis_rd_data_count(NLW_U0_axis_rd_data_count_UNCONNECTED[10:0]),
.axis_sbiterr(NLW_U0_axis_sbiterr_UNCONNECTED),
.axis_underflow(NLW_U0_axis_underflow_UNCONNECTED),
.axis_wr_data_count(NLW_U0_axis_wr_data_count_UNCONNECTED[10:0]),
.backup(1'b0),
.backup_marker(1'b0),
.clk(clk),
.data_count(NLW_U0_data_count_UNCONNECTED[10:0]),
.dbiterr(NLW_U0_dbiterr_UNCONNECTED),
.din(din),
.dout(dout),
.empty(empty),
.full(full),
.injectdbiterr(1'b0),
.injectsbiterr(1'b0),
.int_clk(1'b0),
.m_aclk(1'b0),
.m_aclk_en(1'b0),
.m_axi_araddr(NLW_U0_m_axi_araddr_UNCONNECTED[31:0]),
.m_axi_arburst(NLW_U0_m_axi_arburst_UNCONNECTED[1:0]),
.m_axi_arcache(NLW_U0_m_axi_arcache_UNCONNECTED[3:0]),
.m_axi_arid(NLW_U0_m_axi_arid_UNCONNECTED[0]),
.m_axi_arlen(NLW_U0_m_axi_arlen_UNCONNECTED[7:0]),
.m_axi_arlock(NLW_U0_m_axi_arlock_UNCONNECTED[0]),
.m_axi_arprot(NLW_U0_m_axi_arprot_UNCONNECTED[2:0]),
.m_axi_arqos(NLW_U0_m_axi_arqos_UNCONNECTED[3:0]),
.m_axi_arready(1'b0),
.m_axi_arregion(NLW_U0_m_axi_arregion_UNCONNECTED[3:0]),
.m_axi_arsize(NLW_U0_m_axi_arsize_UNCONNECTED[2:0]),
.m_axi_aruser(NLW_U0_m_axi_aruser_UNCONNECTED[0]),
.m_axi_arvalid(NLW_U0_m_axi_arvalid_UNCONNECTED),
.m_axi_awaddr(NLW_U0_m_axi_awaddr_UNCONNECTED[31:0]),
.m_axi_awburst(NLW_U0_m_axi_awburst_UNCONNECTED[1:0]),
.m_axi_awcache(NLW_U0_m_axi_awcache_UNCONNECTED[3:0]),
.m_axi_awid(NLW_U0_m_axi_awid_UNCONNECTED[0]),
.m_axi_awlen(NLW_U0_m_axi_awlen_UNCONNECTED[7:0]),
.m_axi_awlock(NLW_U0_m_axi_awlock_UNCONNECTED[0]),
.m_axi_awprot(NLW_U0_m_axi_awprot_UNCONNECTED[2:0]),
.m_axi_awqos(NLW_U0_m_axi_awqos_UNCONNECTED[3:0]),
.m_axi_awready(1'b0),
.m_axi_awregion(NLW_U0_m_axi_awregion_UNCONNECTED[3:0]),
.m_axi_awsize(NLW_U0_m_axi_awsize_UNCONNECTED[2:0]),
.m_axi_awuser(NLW_U0_m_axi_awuser_UNCONNECTED[0]),
.m_axi_awvalid(NLW_U0_m_axi_awvalid_UNCONNECTED),
.m_axi_bid(1'b0),
.m_axi_bready(NLW_U0_m_axi_bready_UNCONNECTED),
.m_axi_bresp({1'b0,1'b0}),
.m_axi_buser(1'b0),
.m_axi_bvalid(1'b0),
.m_axi_rdata({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.m_axi_rid(1'b0),
.m_axi_rlast(1'b0),
.m_axi_rready(NLW_U0_m_axi_rready_UNCONNECTED),
.m_axi_rresp({1'b0,1'b0}),
.m_axi_ruser(1'b0),
.m_axi_rvalid(1'b0),
.m_axi_wdata(NLW_U0_m_axi_wdata_UNCONNECTED[63:0]),
.m_axi_wid(NLW_U0_m_axi_wid_UNCONNECTED[0]),
.m_axi_wlast(NLW_U0_m_axi_wlast_UNCONNECTED),
.m_axi_wready(1'b0),
.m_axi_wstrb(NLW_U0_m_axi_wstrb_UNCONNECTED[7:0]),
.m_axi_wuser(NLW_U0_m_axi_wuser_UNCONNECTED[0]),
.m_axi_wvalid(NLW_U0_m_axi_wvalid_UNCONNECTED),
.m_axis_tdata(NLW_U0_m_axis_tdata_UNCONNECTED[7:0]),
.m_axis_tdest(NLW_U0_m_axis_tdest_UNCONNECTED[0]),
.m_axis_tid(NLW_U0_m_axis_tid_UNCONNECTED[0]),
.m_axis_tkeep(NLW_U0_m_axis_tkeep_UNCONNECTED[0]),
.m_axis_tlast(NLW_U0_m_axis_tlast_UNCONNECTED),
.m_axis_tready(1'b0),
.m_axis_tstrb(NLW_U0_m_axis_tstrb_UNCONNECTED[0]),
.m_axis_tuser(NLW_U0_m_axis_tuser_UNCONNECTED[3:0]),
.m_axis_tvalid(NLW_U0_m_axis_tvalid_UNCONNECTED),
.overflow(NLW_U0_overflow_UNCONNECTED),
.prog_empty(NLW_U0_prog_empty_UNCONNECTED),
.prog_empty_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.prog_empty_thresh_assert({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.prog_empty_thresh_negate({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.prog_full(NLW_U0_prog_full_UNCONNECTED),
.prog_full_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.prog_full_thresh_assert({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.prog_full_thresh_negate({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.rd_clk(1'b0),
.rd_data_count(NLW_U0_rd_data_count_UNCONNECTED[10:0]),
.rd_en(rd_en),
.rd_rst(1'b0),
.rd_rst_busy(NLW_U0_rd_rst_busy_UNCONNECTED),
.rst(rst),
.s_aclk(1'b0),
.s_aclk_en(1'b0),
.s_aresetn(1'b0),
.s_axi_araddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_arburst({1'b0,1'b0}),
.s_axi_arcache({1'b0,1'b0,1'b0,1'b0}),
.s_axi_arid(1'b0),
.s_axi_arlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_arlock(1'b0),
.s_axi_arprot({1'b0,1'b0,1'b0}),
.s_axi_arqos({1'b0,1'b0,1'b0,1'b0}),
.s_axi_arready(NLW_U0_s_axi_arready_UNCONNECTED),
.s_axi_arregion({1'b0,1'b0,1'b0,1'b0}),
.s_axi_arsize({1'b0,1'b0,1'b0}),
.s_axi_aruser(1'b0),
.s_axi_arvalid(1'b0),
.s_axi_awaddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_awburst({1'b0,1'b0}),
.s_axi_awcache({1'b0,1'b0,1'b0,1'b0}),
.s_axi_awid(1'b0),
.s_axi_awlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_awlock(1'b0),
.s_axi_awprot({1'b0,1'b0,1'b0}),
.s_axi_awqos({1'b0,1'b0,1'b0,1'b0}),
.s_axi_awready(NLW_U0_s_axi_awready_UNCONNECTED),
.s_axi_awregion({1'b0,1'b0,1'b0,1'b0}),
.s_axi_awsize({1'b0,1'b0,1'b0}),
.s_axi_awuser(1'b0),
.s_axi_awvalid(1'b0),
.s_axi_bid(NLW_U0_s_axi_bid_UNCONNECTED[0]),
.s_axi_bready(1'b0),
.s_axi_bresp(NLW_U0_s_axi_bresp_UNCONNECTED[1:0]),
.s_axi_buser(NLW_U0_s_axi_buser_UNCONNECTED[0]),
.s_axi_bvalid(NLW_U0_s_axi_bvalid_UNCONNECTED),
.s_axi_rdata(NLW_U0_s_axi_rdata_UNCONNECTED[63:0]),
.s_axi_rid(NLW_U0_s_axi_rid_UNCONNECTED[0]),
.s_axi_rlast(NLW_U0_s_axi_rlast_UNCONNECTED),
.s_axi_rready(1'b0),
.s_axi_rresp(NLW_U0_s_axi_rresp_UNCONNECTED[1:0]),
.s_axi_ruser(NLW_U0_s_axi_ruser_UNCONNECTED[0]),
.s_axi_rvalid(NLW_U0_s_axi_rvalid_UNCONNECTED),
.s_axi_wdata({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_wid(1'b0),
.s_axi_wlast(1'b0),
.s_axi_wready(NLW_U0_s_axi_wready_UNCONNECTED),
.s_axi_wstrb({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_wuser(1'b0),
.s_axi_wvalid(1'b0),
.s_axis_tdata({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axis_tdest(1'b0),
.s_axis_tid(1'b0),
.s_axis_tkeep(1'b0),
.s_axis_tlast(1'b0),
.s_axis_tready(NLW_U0_s_axis_tready_UNCONNECTED),
.s_axis_tstrb(1'b0),
.s_axis_tuser({1'b0,1'b0,1'b0,1'b0}),
.s_axis_tvalid(1'b0),
.sbiterr(NLW_U0_sbiterr_UNCONNECTED),
.sleep(1'b0),
.srst(1'b0),
.underflow(NLW_U0_underflow_UNCONNECTED),
.valid(NLW_U0_valid_UNCONNECTED),
.wr_ack(NLW_U0_wr_ack_UNCONNECTED),
.wr_clk(1'b0),
.wr_data_count(NLW_U0_wr_data_count_UNCONNECTED[10:0]),
.wr_en(wr_en),
.wr_rst(1'b0),
.wr_rst_busy(NLW_U0_wr_rst_busy_UNCONNECTED));
endmodule
|
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_generic_cstr
(dout,
clk,
ram_full_fb_i_reg,
tmp_ram_rd_en,
out,
\gcc0.gc0.count_d1_reg[10] ,
Q,
din);
output [63:0]dout;
input clk;
input ram_full_fb_i_reg;
input tmp_ram_rd_en;
input [0:0]out;
input [10:0]\gcc0.gc0.count_d1_reg[10] ;
input [10:0]Q;
input [63:0]din;
wire [10:0]Q;
wire clk;
wire [63:0]din;
wire [63:0]dout;
wire [10:0]\gcc0.gc0.count_d1_reg[10] ;
wire [0:0]out;
wire ram_full_fb_i_reg;
wire tmp_ram_rd_en;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width \ramloop[0].ram.r
(.Q(Q),
.clk(clk),
.din(din[17:0]),
.dout(dout[17:0]),
.\gcc0.gc0.count_d1_reg[10] (\gcc0.gc0.count_d1_reg[10] ),
.out(out),
.ram_full_fb_i_reg(ram_full_fb_i_reg),
.tmp_ram_rd_en(tmp_ram_rd_en));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized0 \ramloop[1].ram.r
(.Q(Q),
.clk(clk),
.din(din[35:18]),
.dout(dout[35:18]),
.\gcc0.gc0.count_d1_reg[10] (\gcc0.gc0.count_d1_reg[10] ),
.out(out),
.ram_full_fb_i_reg(ram_full_fb_i_reg),
.tmp_ram_rd_en(tmp_ram_rd_en));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized1 \ramloop[2].ram.r
(.Q(Q),
.clk(clk),
.din(din[53:36]),
.dout(dout[53:36]),
.\gcc0.gc0.count_d1_reg[10] (\gcc0.gc0.count_d1_reg[10] ),
.out(out),
.ram_full_fb_i_reg(ram_full_fb_i_reg),
.tmp_ram_rd_en(tmp_ram_rd_en));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized2 \ramloop[3].ram.r
(.Q(Q),
.clk(clk),
.din(din[63:54]),
.dout(dout[63:54]),
.\gcc0.gc0.count_d1_reg[10] (\gcc0.gc0.count_d1_reg[10] ),
.out(out),
.ram_full_fb_i_reg(ram_full_fb_i_reg),
.tmp_ram_rd_en(tmp_ram_rd_en));
endmodule
|
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width
(dout,
clk,
ram_full_fb_i_reg,
tmp_ram_rd_en,
out,
\gcc0.gc0.count_d1_reg[10] ,
Q,
din);
output [17:0]dout;
input clk;
input ram_full_fb_i_reg;
input tmp_ram_rd_en;
input [0:0]out;
input [10:0]\gcc0.gc0.count_d1_reg[10] ;
input [10:0]Q;
input [17:0]din;
wire [10:0]Q;
wire clk;
wire [17:0]din;
wire [17:0]dout;
wire [10:0]\gcc0.gc0.count_d1_reg[10] ;
wire [0:0]out;
wire ram_full_fb_i_reg;
wire tmp_ram_rd_en;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper \prim_noinit.ram
(.Q(Q),
.clk(clk),
.din(din),
.dout(dout),
.\gcc0.gc0.count_d1_reg[10] (\gcc0.gc0.count_d1_reg[10] ),
.out(out),
.ram_full_fb_i_reg(ram_full_fb_i_reg),
.tmp_ram_rd_en(tmp_ram_rd_en));
endmodule
|
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized0
(dout,
clk,
ram_full_fb_i_reg,
tmp_ram_rd_en,
out,
\gcc0.gc0.count_d1_reg[10] ,
Q,
din);
output [17:0]dout;
input clk;
input ram_full_fb_i_reg;
input tmp_ram_rd_en;
input [0:0]out;
input [10:0]\gcc0.gc0.count_d1_reg[10] ;
input [10:0]Q;
input [17:0]din;
wire [10:0]Q;
wire clk;
wire [17:0]din;
wire [17:0]dout;
wire [10:0]\gcc0.gc0.count_d1_reg[10] ;
wire [0:0]out;
wire ram_full_fb_i_reg;
wire tmp_ram_rd_en;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized0 \prim_noinit.ram
(.Q(Q),
.clk(clk),
.din(din),
.dout(dout),
.\gcc0.gc0.count_d1_reg[10] (\gcc0.gc0.count_d1_reg[10] ),
.out(out),
.ram_full_fb_i_reg(ram_full_fb_i_reg),
.tmp_ram_rd_en(tmp_ram_rd_en));
endmodule
|
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized1
(dout,
clk,
ram_full_fb_i_reg,
tmp_ram_rd_en,
out,
\gcc0.gc0.count_d1_reg[10] ,
Q,
din);
output [17:0]dout;
input clk;
input ram_full_fb_i_reg;
input tmp_ram_rd_en;
input [0:0]out;
input [10:0]\gcc0.gc0.count_d1_reg[10] ;
input [10:0]Q;
input [17:0]din;
wire [10:0]Q;
wire clk;
wire [17:0]din;
wire [17:0]dout;
wire [10:0]\gcc0.gc0.count_d1_reg[10] ;
wire [0:0]out;
wire ram_full_fb_i_reg;
wire tmp_ram_rd_en;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized1 \prim_noinit.ram
(.Q(Q),
.clk(clk),
.din(din),
.dout(dout),
.\gcc0.gc0.count_d1_reg[10] (\gcc0.gc0.count_d1_reg[10] ),
.out(out),
.ram_full_fb_i_reg(ram_full_fb_i_reg),
.tmp_ram_rd_en(tmp_ram_rd_en));
endmodule
|
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized2
(dout,
clk,
ram_full_fb_i_reg,
tmp_ram_rd_en,
out,
\gcc0.gc0.count_d1_reg[10] ,
Q,
din);
output [9:0]dout;
input clk;
input ram_full_fb_i_reg;
input tmp_ram_rd_en;
input [0:0]out;
input [10:0]\gcc0.gc0.count_d1_reg[10] ;
input [10:0]Q;
input [9:0]din;
wire [10:0]Q;
wire clk;
wire [9:0]din;
wire [9:0]dout;
wire [10:0]\gcc0.gc0.count_d1_reg[10] ;
wire [0:0]out;
wire ram_full_fb_i_reg;
wire tmp_ram_rd_en;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized2 \prim_noinit.ram
(.Q(Q),
.clk(clk),
.din(din),
.dout(dout),
.\gcc0.gc0.count_d1_reg[10] (\gcc0.gc0.count_d1_reg[10] ),
.out(out),
.ram_full_fb_i_reg(ram_full_fb_i_reg),
.tmp_ram_rd_en(tmp_ram_rd_en));
endmodule
|
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper
(dout,
clk,
ram_full_fb_i_reg,
tmp_ram_rd_en,
out,
\gcc0.gc0.count_d1_reg[10] ,
Q,
din);
output [17:0]dout;
input clk;
input ram_full_fb_i_reg;
input tmp_ram_rd_en;
input [0:0]out;
input [10:0]\gcc0.gc0.count_d1_reg[10] ;
input [10:0]Q;
input [17:0]din;
wire [10:0]Q;
wire clk;
wire [17:0]din;
wire [17:0]dout;
wire [10:0]\gcc0.gc0.count_d1_reg[10] ;
wire [0:0]out;
wire ram_full_fb_i_reg;
wire tmp_ram_rd_en;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ;
wire [31:16]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ;
wire [3:2]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* CLOCK_DOMAINS = "COMMON" *)
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(0),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(18),
.READ_WIDTH_B(18),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(18),
.WRITE_WIDTH_B(18))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,\gcc0.gc0.count_d1_reg[10] ,1'b1,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b1,Q,1'b1,1'b1,1'b1,1'b1}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(clk),
.CLKBWRCLK(clk),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,din[16:9],din[7:0]}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,din[17],din[8]}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]),
.DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:16],dout[16:9],dout[7:0]}),
.DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]),
.DOPBDOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:2],dout[17],dout[8]}),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(ram_full_fb_i_reg),
.ENBWREN(tmp_ram_rd_en),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b0),
.REGCEB(1'b0),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(out),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({ram_full_fb_i_reg,ram_full_fb_i_reg,ram_full_fb_i_reg,ram_full_fb_i_reg}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule
|
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized0
(dout,
clk,
ram_full_fb_i_reg,
tmp_ram_rd_en,
out,
\gcc0.gc0.count_d1_reg[10] ,
Q,
din);
output [17:0]dout;
input clk;
input ram_full_fb_i_reg;
input tmp_ram_rd_en;
input [0:0]out;
input [10:0]\gcc0.gc0.count_d1_reg[10] ;
input [10:0]Q;
input [17:0]din;
wire [10:0]Q;
wire clk;
wire [17:0]din;
wire [17:0]dout;
wire [10:0]\gcc0.gc0.count_d1_reg[10] ;
wire [0:0]out;
wire ram_full_fb_i_reg;
wire tmp_ram_rd_en;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ;
wire [31:16]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ;
wire [3:2]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* CLOCK_DOMAINS = "COMMON" *)
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(0),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(18),
.READ_WIDTH_B(18),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(18),
.WRITE_WIDTH_B(18))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,\gcc0.gc0.count_d1_reg[10] ,1'b1,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b1,Q,1'b1,1'b1,1'b1,1'b1}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(clk),
.CLKBWRCLK(clk),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,din[16:9],din[7:0]}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,din[17],din[8]}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]),
.DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:16],dout[16:9],dout[7:0]}),
.DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]),
.DOPBDOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:2],dout[17],dout[8]}),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(ram_full_fb_i_reg),
.ENBWREN(tmp_ram_rd_en),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b0),
.REGCEB(1'b0),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(out),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({ram_full_fb_i_reg,ram_full_fb_i_reg,ram_full_fb_i_reg,ram_full_fb_i_reg}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule
|
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized1
(dout,
clk,
ram_full_fb_i_reg,
tmp_ram_rd_en,
out,
\gcc0.gc0.count_d1_reg[10] ,
Q,
din);
output [17:0]dout;
input clk;
input ram_full_fb_i_reg;
input tmp_ram_rd_en;
input [0:0]out;
input [10:0]\gcc0.gc0.count_d1_reg[10] ;
input [10:0]Q;
input [17:0]din;
wire [10:0]Q;
wire clk;
wire [17:0]din;
wire [17:0]dout;
wire [10:0]\gcc0.gc0.count_d1_reg[10] ;
wire [0:0]out;
wire ram_full_fb_i_reg;
wire tmp_ram_rd_en;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ;
wire [31:16]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ;
wire [3:2]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* CLOCK_DOMAINS = "COMMON" *)
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(0),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(18),
.READ_WIDTH_B(18),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(18),
.WRITE_WIDTH_B(18))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,\gcc0.gc0.count_d1_reg[10] ,1'b1,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b1,Q,1'b1,1'b1,1'b1,1'b1}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(clk),
.CLKBWRCLK(clk),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,din[16:9],din[7:0]}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,din[17],din[8]}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]),
.DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:16],dout[16:9],dout[7:0]}),
.DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]),
.DOPBDOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:2],dout[17],dout[8]}),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(ram_full_fb_i_reg),
.ENBWREN(tmp_ram_rd_en),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b0),
.REGCEB(1'b0),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(out),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({ram_full_fb_i_reg,ram_full_fb_i_reg,ram_full_fb_i_reg,ram_full_fb_i_reg}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule
|
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized2
(dout,
clk,
ram_full_fb_i_reg,
tmp_ram_rd_en,
out,
\gcc0.gc0.count_d1_reg[10] ,
Q,
din);
output [9:0]dout;
input clk;
input ram_full_fb_i_reg;
input tmp_ram_rd_en;
input [0:0]out;
input [10:0]\gcc0.gc0.count_d1_reg[10] ;
input [10:0]Q;
input [9:0]din;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_69 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_70 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_71 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_77 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_78 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_79 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_91 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_92 ;
wire [10:0]Q;
wire clk;
wire [9:0]din;
wire [9:0]dout;
wire [10:0]\gcc0.gc0.count_d1_reg[10] ;
wire [0:0]out;
wire ram_full_fb_i_reg;
wire tmp_ram_rd_en;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ;
wire [31:16]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ;
wire [3:2]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* CLOCK_DOMAINS = "COMMON" *)
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(0),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(18),
.READ_WIDTH_B(18),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(18),
.WRITE_WIDTH_B(18))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,\gcc0.gc0.count_d1_reg[10] ,1'b1,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b1,Q,1'b1,1'b1,1'b1,1'b1}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(clk),
.CLKBWRCLK(clk),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,din[9:5],1'b0,1'b0,1'b0,din[4:0]}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]),
.DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:16],\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_69 ,\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_70 ,\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_71 ,dout[9:5],\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_77 ,\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_78 ,\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_79 ,dout[4:0]}),
.DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]),
.DOPBDOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:2],\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_91 ,\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_92 }),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(ram_full_fb_i_reg),
.ENBWREN(tmp_ram_rd_en),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b0),
.REGCEB(1'b0),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(out),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({ram_full_fb_i_reg,ram_full_fb_i_reg,ram_full_fb_i_reg,ram_full_fb_i_reg}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule
|
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_top
(dout,
clk,
ram_full_fb_i_reg,
tmp_ram_rd_en,
out,
\gcc0.gc0.count_d1_reg[10] ,
Q,
din);
output [63:0]dout;
input clk;
input ram_full_fb_i_reg;
input tmp_ram_rd_en;
input [0:0]out;
input [10:0]\gcc0.gc0.count_d1_reg[10] ;
input [10:0]Q;
input [63:0]din;
wire [10:0]Q;
wire clk;
wire [63:0]din;
wire [63:0]dout;
wire [10:0]\gcc0.gc0.count_d1_reg[10] ;
wire [0:0]out;
wire ram_full_fb_i_reg;
wire tmp_ram_rd_en;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_generic_cstr \valid.cstr
(.Q(Q),
.clk(clk),
.din(din),
.dout(dout),
.\gcc0.gc0.count_d1_reg[10] (\gcc0.gc0.count_d1_reg[10] ),
.out(out),
.ram_full_fb_i_reg(ram_full_fb_i_reg),
.tmp_ram_rd_en(tmp_ram_rd_en));
endmodule
|
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_4
(dout,
clk,
ram_full_fb_i_reg,
tmp_ram_rd_en,
out,
\gcc0.gc0.count_d1_reg[10] ,
Q,
din);
output [63:0]dout;
input clk;
input ram_full_fb_i_reg;
input tmp_ram_rd_en;
input [0:0]out;
input [10:0]\gcc0.gc0.count_d1_reg[10] ;
input [10:0]Q;
input [63:0]din;
wire [10:0]Q;
wire clk;
wire [63:0]din;
wire [63:0]dout;
wire [10:0]\gcc0.gc0.count_d1_reg[10] ;
wire [0:0]out;
wire ram_full_fb_i_reg;
wire tmp_ram_rd_en;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_4_synth inst_blk_mem_gen
(.Q(Q),
.clk(clk),
.din(din),
.dout(dout),
.\gcc0.gc0.count_d1_reg[10] (\gcc0.gc0.count_d1_reg[10] ),
.out(out),
.ram_full_fb_i_reg(ram_full_fb_i_reg),
.tmp_ram_rd_en(tmp_ram_rd_en));
endmodule
|
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_4_synth
(dout,
clk,
ram_full_fb_i_reg,
tmp_ram_rd_en,
out,
\gcc0.gc0.count_d1_reg[10] ,
Q,
din);
output [63:0]dout;
input clk;
input ram_full_fb_i_reg;
input tmp_ram_rd_en;
input [0:0]out;
input [10:0]\gcc0.gc0.count_d1_reg[10] ;
input [10:0]Q;
input [63:0]din;
wire [10:0]Q;
wire clk;
wire [63:0]din;
wire [63:0]dout;
wire [10:0]\gcc0.gc0.count_d1_reg[10] ;
wire [0:0]out;
wire ram_full_fb_i_reg;
wire tmp_ram_rd_en;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_top \gnbram.gnativebmg.native_blk_mem_gen
(.Q(Q),
.clk(clk),
.din(din),
.dout(dout),
.\gcc0.gc0.count_d1_reg[10] (\gcc0.gc0.count_d1_reg[10] ),
.out(out),
.ram_full_fb_i_reg(ram_full_fb_i_reg),
.tmp_ram_rd_en(tmp_ram_rd_en));
endmodule
|
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare
(ram_full_comb,
v1_reg,
\gc0.count_d1_reg[10] ,
wr_en,
comp1,
wr_rst_busy,
out,
ram_empty_fb_i_reg);
output ram_full_comb;
input [4:0]v1_reg;
input \gc0.count_d1_reg[10] ;
input wr_en;
input comp1;
input wr_rst_busy;
input out;
input [0:0]ram_empty_fb_i_reg;
wire carrynet_0;
wire carrynet_1;
wire carrynet_2;
wire carrynet_3;
wire carrynet_4;
wire comp0;
wire comp1;
wire \gc0.count_d1_reg[10] ;
wire out;
wire [0:0]ram_empty_fb_i_reg;
wire ram_full_comb;
wire [4:0]v1_reg;
wire wr_en;
wire wr_rst_busy;
wire [3:0]\NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED ;
wire [3:2]\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED ;
wire [3:2]\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED ;
wire [3:0]\NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED ;
wire [3:2]\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED ;
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
(* box_type = "PRIMITIVE" *)
CARRY4 \gmux.gm[0].gm1.m1_CARRY4
(.CI(1'b0),
.CO({carrynet_3,carrynet_2,carrynet_1,carrynet_0}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(\NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED [3:0]),
.S(v1_reg[3:0]));
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
(* box_type = "PRIMITIVE" *)
CARRY4 \gmux.gm[4].gms.ms_CARRY4
(.CI(carrynet_3),
.CO({\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED [3:2],comp0,carrynet_4}),
.CYINIT(1'b0),
.DI({\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED [3:2],1'b0,1'b0}),
.O(\NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED [3:0]),
.S({\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED [3:2],\gc0.count_d1_reg[10] ,v1_reg[4]}));
LUT6 #(
.INIT(64'h0055000000FFC0C0))
ram_full_fb_i_i_1
(.I0(comp0),
.I1(wr_en),
.I2(comp1),
.I3(wr_rst_busy),
.I4(out),
.I5(ram_empty_fb_i_reg),
.O(ram_full_comb));
endmodule
|
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_3
(comp1,
v1_reg_0,
\gc0.count_d1_reg[10] );
output comp1;
input [4:0]v1_reg_0;
input \gc0.count_d1_reg[10] ;
wire carrynet_0;
wire carrynet_1;
wire carrynet_2;
wire carrynet_3;
wire carrynet_4;
wire comp1;
wire \gc0.count_d1_reg[10] ;
wire [4:0]v1_reg_0;
wire [3:0]\NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED ;
wire [3:2]\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED ;
wire [3:2]\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED ;
wire [3:0]\NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED ;
wire [3:2]\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED ;
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
(* box_type = "PRIMITIVE" *)
CARRY4 \gmux.gm[0].gm1.m1_CARRY4
(.CI(1'b0),
.CO({carrynet_3,carrynet_2,carrynet_1,carrynet_0}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(\NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED [3:0]),
.S(v1_reg_0[3:0]));
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
(* box_type = "PRIMITIVE" *)
CARRY4 \gmux.gm[4].gms.ms_CARRY4
(.CI(carrynet_3),
.CO({\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED [3:2],comp1,carrynet_4}),
.CYINIT(1'b0),
.DI({\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED [3:2],1'b0,1'b0}),
.O(\NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED [3:0]),
.S({\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED [3:2],\gc0.count_d1_reg[10] ,v1_reg_0[4]}));
endmodule
|
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_4
(ram_empty_i_reg,
\gcc0.gc0.count_d1_reg[0] ,
\gcc0.gc0.count_d1_reg[2] ,
\gcc0.gc0.count_d1_reg[4] ,
\gcc0.gc0.count_d1_reg[6] ,
\gcc0.gc0.count_d1_reg[8] ,
\gc0.count_d1_reg[10] ,
rd_en,
out,
comp1,
wr_en,
ram_full_fb_i_reg);
output ram_empty_i_reg;
input \gcc0.gc0.count_d1_reg[0] ;
input \gcc0.gc0.count_d1_reg[2] ;
input \gcc0.gc0.count_d1_reg[4] ;
input \gcc0.gc0.count_d1_reg[6] ;
input \gcc0.gc0.count_d1_reg[8] ;
input \gc0.count_d1_reg[10] ;
input rd_en;
input out;
input comp1;
input wr_en;
input ram_full_fb_i_reg;
wire carrynet_0;
wire carrynet_1;
wire carrynet_2;
wire carrynet_3;
wire carrynet_4;
wire comp0;
wire comp1;
wire \gc0.count_d1_reg[10] ;
wire \gcc0.gc0.count_d1_reg[0] ;
wire \gcc0.gc0.count_d1_reg[2] ;
wire \gcc0.gc0.count_d1_reg[4] ;
wire \gcc0.gc0.count_d1_reg[6] ;
wire \gcc0.gc0.count_d1_reg[8] ;
wire out;
wire ram_empty_i_reg;
wire ram_full_fb_i_reg;
wire rd_en;
wire wr_en;
wire [3:0]\NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED ;
wire [3:2]\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED ;
wire [3:2]\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED ;
wire [3:0]\NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED ;
wire [3:2]\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED ;
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
(* box_type = "PRIMITIVE" *)
CARRY4 \gmux.gm[0].gm1.m1_CARRY4
(.CI(1'b0),
.CO({carrynet_3,carrynet_2,carrynet_1,carrynet_0}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(\NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED [3:0]),
.S({\gcc0.gc0.count_d1_reg[6] ,\gcc0.gc0.count_d1_reg[4] ,\gcc0.gc0.count_d1_reg[2] ,\gcc0.gc0.count_d1_reg[0] }));
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
(* box_type = "PRIMITIVE" *)
CARRY4 \gmux.gm[4].gms.ms_CARRY4
(.CI(carrynet_3),
.CO({\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED [3:2],comp0,carrynet_4}),
.CYINIT(1'b0),
.DI({\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED [3:2],1'b0,1'b0}),
.O(\NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED [3:0]),
.S({\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED [3:2],\gc0.count_d1_reg[10] ,\gcc0.gc0.count_d1_reg[8] }));
LUT6 #(
.INIT(64'hFCF0FCF05050FCF0))
ram_empty_fb_i_i_1
(.I0(comp0),
.I1(rd_en),
.I2(out),
.I3(comp1),
.I4(wr_en),
.I5(ram_full_fb_i_reg),
.O(ram_empty_i_reg));
endmodule
|
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_5
(comp1,
v1_reg,
\gc0.count_reg[10] );
output comp1;
input [4:0]v1_reg;
input \gc0.count_reg[10] ;
wire carrynet_0;
wire carrynet_1;
wire carrynet_2;
wire carrynet_3;
wire carrynet_4;
wire comp1;
wire \gc0.count_reg[10] ;
wire [4:0]v1_reg;
wire [3:0]\NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED ;
wire [3:2]\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED ;
wire [3:2]\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED ;
wire [3:0]\NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED ;
wire [3:2]\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED ;
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
(* box_type = "PRIMITIVE" *)
CARRY4 \gmux.gm[0].gm1.m1_CARRY4
(.CI(1'b0),
.CO({carrynet_3,carrynet_2,carrynet_1,carrynet_0}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(\NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED [3:0]),
.S(v1_reg[3:0]));
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
(* box_type = "PRIMITIVE" *)
CARRY4 \gmux.gm[4].gms.ms_CARRY4
(.CI(carrynet_3),
.CO({\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED [3:2],comp1,carrynet_4}),
.CYINIT(1'b0),
.DI({\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED [3:2],1'b0,1'b0}),
.O(\NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED [3:0]),
.S({\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED [3:2],\gc0.count_reg[10] ,v1_reg[4]}));
endmodule
|
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_ramfifo
(wr_rst_busy,
dout,
empty,
full,
rd_en,
wr_en,
clk,
din,
rst);
output wr_rst_busy;
output [63:0]dout;
output empty;
output full;
input rd_en;
input wr_en;
input clk;
input [63:0]din;
input rst;
wire clk;
wire [63:0]din;
wire [63:0]dout;
wire empty;
wire full;
wire \gntv_or_sync_fifo.gl0.rd_n_2 ;
wire \gntv_or_sync_fifo.gl0.rd_n_25 ;
wire \gntv_or_sync_fifo.gl0.rd_n_3 ;
wire \gntv_or_sync_fifo.gl0.wr_n_0 ;
wire \gntv_or_sync_fifo.gl0.wr_n_2 ;
wire \gntv_or_sync_fifo.gl0.wr_n_20 ;
wire \gntv_or_sync_fifo.gl0.wr_n_21 ;
wire \gntv_or_sync_fifo.gl0.wr_n_22 ;
wire \gntv_or_sync_fifo.gl0.wr_n_23 ;
wire \gntv_or_sync_fifo.gl0.wr_n_24 ;
wire [4:0]\grss.rsts/c2/v1_reg ;
wire [10:0]p_0_out;
wire [10:0]p_11_out;
wire [10:10]p_12_out;
wire p_2_out;
wire rd_en;
wire [9:0]rd_pntr_plus1;
wire [2:0]rd_rst_i;
wire rst;
wire rst_full_ff_i;
wire tmp_ram_rd_en;
wire wr_en;
wire wr_rst_busy;
wire [1:1]wr_rst_i;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_logic \gntv_or_sync_fifo.gl0.rd
(.AR(rd_rst_i[2]),
.E(\gntv_or_sync_fifo.gl0.rd_n_2 ),
.Q(p_0_out),
.clk(clk),
.empty(empty),
.\gc0.count_d1_reg[9] (rd_pntr_plus1),
.\gcc0.gc0.count_d1_reg[0] (\gntv_or_sync_fifo.gl0.wr_n_20 ),
.\gcc0.gc0.count_d1_reg[10] (p_11_out[10]),
.\gcc0.gc0.count_d1_reg[2] (\gntv_or_sync_fifo.gl0.wr_n_21 ),
.\gcc0.gc0.count_d1_reg[4] (\gntv_or_sync_fifo.gl0.wr_n_22 ),
.\gcc0.gc0.count_d1_reg[6] (\gntv_or_sync_fifo.gl0.wr_n_23 ),
.\gcc0.gc0.count_d1_reg[8] (\gntv_or_sync_fifo.gl0.wr_n_24 ),
.\gcc0.gc0.count_reg[10] (p_12_out),
.out(p_2_out),
.ram_full_fb_i_reg(\gntv_or_sync_fifo.gl0.wr_n_0 ),
.ram_full_i_reg(\gntv_or_sync_fifo.gl0.rd_n_3 ),
.ram_full_i_reg_0(\gntv_or_sync_fifo.gl0.rd_n_25 ),
.rd_en(rd_en),
.v1_reg(\grss.rsts/c2/v1_reg ),
.wr_en(wr_en));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_logic \gntv_or_sync_fifo.gl0.wr
(.AR(wr_rst_i),
.\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram (p_11_out),
.E(\gntv_or_sync_fifo.gl0.rd_n_2 ),
.Q(p_12_out),
.clk(clk),
.full(full),
.\gc0.count_d1_reg[10] (\gntv_or_sync_fifo.gl0.rd_n_3 ),
.\gc0.count_d1_reg[10]_0 (\gntv_or_sync_fifo.gl0.rd_n_25 ),
.\gc0.count_d1_reg[9] (p_0_out[9:0]),
.\gc0.count_reg[9] (rd_pntr_plus1),
.\gcc0.gc0.count_d1_reg[10] (\gntv_or_sync_fifo.gl0.wr_n_2 ),
.\grstd1.grst_full.grst_f.rst_d2_reg (rst_full_ff_i),
.out(\gntv_or_sync_fifo.gl0.wr_n_0 ),
.ram_empty_i_reg(\gntv_or_sync_fifo.gl0.wr_n_20 ),
.ram_empty_i_reg_0(\gntv_or_sync_fifo.gl0.wr_n_21 ),
.ram_empty_i_reg_1(\gntv_or_sync_fifo.gl0.wr_n_22 ),
.ram_empty_i_reg_2(\gntv_or_sync_fifo.gl0.wr_n_23 ),
.ram_empty_i_reg_3(\gntv_or_sync_fifo.gl0.wr_n_24 ),
.v1_reg(\grss.rsts/c2/v1_reg ),
.wr_en(wr_en),
.wr_rst_busy(wr_rst_busy));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_memory \gntv_or_sync_fifo.mem
(.Q(p_0_out),
.clk(clk),
.din(din),
.dout(dout),
.\gcc0.gc0.count_d1_reg[10] (p_11_out),
.out(rd_rst_i[0]),
.ram_full_fb_i_reg(\gntv_or_sync_fifo.gl0.wr_n_2 ),
.tmp_ram_rd_en(tmp_ram_rd_en));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_reset_blk_ramfifo rstblk
(.clk(clk),
.\gc0.count_reg[1] ({rd_rst_i[2],rd_rst_i[0]}),
.\grstd1.grst_full.grst_f.rst_d3_reg_0 (rst_full_ff_i),
.out(wr_rst_i),
.ram_empty_fb_i_reg(p_2_out),
.rd_en(rd_en),
.rst(rst),
.tmp_ram_rd_en(tmp_ram_rd_en),
.wr_rst_busy(wr_rst_busy));
endmodule
|
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_top
(wr_rst_busy,
dout,
empty,
full,
rd_en,
wr_en,
clk,
din,
rst);
output wr_rst_busy;
output [63:0]dout;
output empty;
output full;
input rd_en;
input wr_en;
input clk;
input [63:0]din;
input rst;
wire clk;
wire [63:0]din;
wire [63:0]dout;
wire empty;
wire full;
wire rd_en;
wire rst;
wire wr_en;
wire wr_rst_busy;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_ramfifo \grf.rf
(.clk(clk),
.din(din),
.dout(dout),
.empty(empty),
.full(full),
.rd_en(rd_en),
.rst(rst),
.wr_en(wr_en),
.wr_rst_busy(wr_rst_busy));
endmodule
|
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2
(backup,
backup_marker,
clk,
rst,
srst,
wr_clk,
wr_rst,
rd_clk,
rd_rst,
din,
wr_en,
rd_en,
prog_empty_thresh,
prog_empty_thresh_assert,
prog_empty_thresh_negate,
prog_full_thresh,
prog_full_thresh_assert,
prog_full_thresh_negate,
int_clk,
injectdbiterr,
injectsbiterr,
sleep,
dout,
full,
almost_full,
wr_ack,
overflow,
empty,
almost_empty,
valid,
underflow,
data_count,
rd_data_count,
wr_data_count,
prog_full,
prog_empty,
sbiterr,
dbiterr,
wr_rst_busy,
rd_rst_busy,
m_aclk,
s_aclk,
s_aresetn,
m_aclk_en,
s_aclk_en,
s_axi_awid,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awlock,
s_axi_awcache,
s_axi_awprot,
s_axi_awqos,
s_axi_awregion,
s_axi_awuser,
s_axi_awvalid,
s_axi_awready,
s_axi_wid,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wuser,
s_axi_wvalid,
s_axi_wready,
s_axi_bid,
s_axi_bresp,
s_axi_buser,
s_axi_bvalid,
s_axi_bready,
m_axi_awid,
m_axi_awaddr,
m_axi_awlen,
m_axi_awsize,
m_axi_awburst,
m_axi_awlock,
m_axi_awcache,
m_axi_awprot,
m_axi_awqos,
m_axi_awregion,
m_axi_awuser,
m_axi_awvalid,
m_axi_awready,
m_axi_wid,
m_axi_wdata,
m_axi_wstrb,
m_axi_wlast,
m_axi_wuser,
m_axi_wvalid,
m_axi_wready,
m_axi_bid,
m_axi_bresp,
m_axi_buser,
m_axi_bvalid,
m_axi_bready,
s_axi_arid,
s_axi_araddr,
s_axi_arlen,
s_axi_arsize,
s_axi_arburst,
s_axi_arlock,
s_axi_arcache,
s_axi_arprot,
s_axi_arqos,
s_axi_arregion,
s_axi_aruser,
s_axi_arvalid,
s_axi_arready,
s_axi_rid,
s_axi_rdata,
s_axi_rresp,
s_axi_rlast,
s_axi_ruser,
s_axi_rvalid,
s_axi_rready,
m_axi_arid,
m_axi_araddr,
m_axi_arlen,
m_axi_arsize,
m_axi_arburst,
m_axi_arlock,
m_axi_arcache,
m_axi_arprot,
m_axi_arqos,
m_axi_arregion,
m_axi_aruser,
m_axi_arvalid,
m_axi_arready,
m_axi_rid,
m_axi_rdata,
m_axi_rresp,
m_axi_rlast,
m_axi_ruser,
m_axi_rvalid,
m_axi_rready,
s_axis_tvalid,
s_axis_tready,
s_axis_tdata,
s_axis_tstrb,
s_axis_tkeep,
s_axis_tlast,
s_axis_tid,
s_axis_tdest,
s_axis_tuser,
m_axis_tvalid,
m_axis_tready,
m_axis_tdata,
m_axis_tstrb,
m_axis_tkeep,
m_axis_tlast,
m_axis_tid,
m_axis_tdest,
m_axis_tuser,
axi_aw_injectsbiterr,
axi_aw_injectdbiterr,
axi_aw_prog_full_thresh,
axi_aw_prog_empty_thresh,
axi_aw_data_count,
axi_aw_wr_data_count,
axi_aw_rd_data_count,
axi_aw_sbiterr,
axi_aw_dbiterr,
axi_aw_overflow,
axi_aw_underflow,
axi_aw_prog_full,
axi_aw_prog_empty,
axi_w_injectsbiterr,
axi_w_injectdbiterr,
axi_w_prog_full_thresh,
axi_w_prog_empty_thresh,
axi_w_data_count,
axi_w_wr_data_count,
axi_w_rd_data_count,
axi_w_sbiterr,
axi_w_dbiterr,
axi_w_overflow,
axi_w_underflow,
axi_w_prog_full,
axi_w_prog_empty,
axi_b_injectsbiterr,
axi_b_injectdbiterr,
axi_b_prog_full_thresh,
axi_b_prog_empty_thresh,
axi_b_data_count,
axi_b_wr_data_count,
axi_b_rd_data_count,
axi_b_sbiterr,
axi_b_dbiterr,
axi_b_overflow,
axi_b_underflow,
axi_b_prog_full,
axi_b_prog_empty,
axi_ar_injectsbiterr,
axi_ar_injectdbiterr,
axi_ar_prog_full_thresh,
axi_ar_prog_empty_thresh,
axi_ar_data_count,
axi_ar_wr_data_count,
axi_ar_rd_data_count,
axi_ar_sbiterr,
axi_ar_dbiterr,
axi_ar_overflow,
axi_ar_underflow,
axi_ar_prog_full,
axi_ar_prog_empty,
axi_r_injectsbiterr,
axi_r_injectdbiterr,
axi_r_prog_full_thresh,
axi_r_prog_empty_thresh,
axi_r_data_count,
axi_r_wr_data_count,
axi_r_rd_data_count,
axi_r_sbiterr,
axi_r_dbiterr,
axi_r_overflow,
axi_r_underflow,
axi_r_prog_full,
axi_r_prog_empty,
axis_injectsbiterr,
axis_injectdbiterr,
axis_prog_full_thresh,
axis_prog_empty_thresh,
axis_data_count,
axis_wr_data_count,
axis_rd_data_count,
axis_sbiterr,
axis_dbiterr,
axis_overflow,
axis_underflow,
axis_prog_full,
axis_prog_empty);
input backup;
input backup_marker;
input clk;
input rst;
input srst;
input wr_clk;
input wr_rst;
input rd_clk;
input rd_rst;
input [63:0]din;
input wr_en;
input rd_en;
input [10:0]prog_empty_thresh;
input [10:0]prog_empty_thresh_assert;
input [10:0]prog_empty_thresh_negate;
input [10:0]prog_full_thresh;
input [10:0]prog_full_thresh_assert;
input [10:0]prog_full_thresh_negate;
input int_clk;
input injectdbiterr;
input injectsbiterr;
input sleep;
output [63:0]dout;
output full;
output almost_full;
output wr_ack;
output overflow;
output empty;
output almost_empty;
output valid;
output underflow;
output [10:0]data_count;
output [10:0]rd_data_count;
output [10:0]wr_data_count;
output prog_full;
output prog_empty;
output sbiterr;
output dbiterr;
output wr_rst_busy;
output rd_rst_busy;
input m_aclk;
input s_aclk;
input s_aresetn;
input m_aclk_en;
input s_aclk_en;
input [0:0]s_axi_awid;
input [31:0]s_axi_awaddr;
input [7:0]s_axi_awlen;
input [2:0]s_axi_awsize;
input [1:0]s_axi_awburst;
input [0:0]s_axi_awlock;
input [3:0]s_axi_awcache;
input [2:0]s_axi_awprot;
input [3:0]s_axi_awqos;
input [3:0]s_axi_awregion;
input [0:0]s_axi_awuser;
input s_axi_awvalid;
output s_axi_awready;
input [0:0]s_axi_wid;
input [63:0]s_axi_wdata;
input [7:0]s_axi_wstrb;
input s_axi_wlast;
input [0:0]s_axi_wuser;
input s_axi_wvalid;
output s_axi_wready;
output [0:0]s_axi_bid;
output [1:0]s_axi_bresp;
output [0:0]s_axi_buser;
output s_axi_bvalid;
input s_axi_bready;
output [0:0]m_axi_awid;
output [31:0]m_axi_awaddr;
output [7:0]m_axi_awlen;
output [2:0]m_axi_awsize;
output [1:0]m_axi_awburst;
output [0:0]m_axi_awlock;
output [3:0]m_axi_awcache;
output [2:0]m_axi_awprot;
output [3:0]m_axi_awqos;
output [3:0]m_axi_awregion;
output [0:0]m_axi_awuser;
output m_axi_awvalid;
input m_axi_awready;
output [0:0]m_axi_wid;
output [63:0]m_axi_wdata;
output [7:0]m_axi_wstrb;
output m_axi_wlast;
output [0:0]m_axi_wuser;
output m_axi_wvalid;
input m_axi_wready;
input [0:0]m_axi_bid;
input [1:0]m_axi_bresp;
input [0:0]m_axi_buser;
input m_axi_bvalid;
output m_axi_bready;
input [0:0]s_axi_arid;
input [31:0]s_axi_araddr;
input [7:0]s_axi_arlen;
input [2:0]s_axi_arsize;
input [1:0]s_axi_arburst;
input [0:0]s_axi_arlock;
input [3:0]s_axi_arcache;
input [2:0]s_axi_arprot;
input [3:0]s_axi_arqos;
input [3:0]s_axi_arregion;
input [0:0]s_axi_aruser;
input s_axi_arvalid;
output s_axi_arready;
output [0:0]s_axi_rid;
output [63:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output s_axi_rlast;
output [0:0]s_axi_ruser;
output s_axi_rvalid;
input s_axi_rready;
output [0:0]m_axi_arid;
output [31:0]m_axi_araddr;
output [7:0]m_axi_arlen;
output [2:0]m_axi_arsize;
output [1:0]m_axi_arburst;
output [0:0]m_axi_arlock;
output [3:0]m_axi_arcache;
output [2:0]m_axi_arprot;
output [3:0]m_axi_arqos;
output [3:0]m_axi_arregion;
output [0:0]m_axi_aruser;
output m_axi_arvalid;
input m_axi_arready;
input [0:0]m_axi_rid;
input [63:0]m_axi_rdata;
input [1:0]m_axi_rresp;
input m_axi_rlast;
input [0:0]m_axi_ruser;
input m_axi_rvalid;
output m_axi_rready;
input s_axis_tvalid;
output s_axis_tready;
input [7:0]s_axis_tdata;
input [0:0]s_axis_tstrb;
input [0:0]s_axis_tkeep;
input s_axis_tlast;
input [0:0]s_axis_tid;
input [0:0]s_axis_tdest;
input [3:0]s_axis_tuser;
output m_axis_tvalid;
input m_axis_tready;
output [7:0]m_axis_tdata;
output [0:0]m_axis_tstrb;
output [0:0]m_axis_tkeep;
output m_axis_tlast;
output [0:0]m_axis_tid;
output [0:0]m_axis_tdest;
output [3:0]m_axis_tuser;
input axi_aw_injectsbiterr;
input axi_aw_injectdbiterr;
input [3:0]axi_aw_prog_full_thresh;
input [3:0]axi_aw_prog_empty_thresh;
output [4:0]axi_aw_data_count;
output [4:0]axi_aw_wr_data_count;
output [4:0]axi_aw_rd_data_count;
output axi_aw_sbiterr;
output axi_aw_dbiterr;
output axi_aw_overflow;
output axi_aw_underflow;
output axi_aw_prog_full;
output axi_aw_prog_empty;
input axi_w_injectsbiterr;
input axi_w_injectdbiterr;
input [9:0]axi_w_prog_full_thresh;
input [9:0]axi_w_prog_empty_thresh;
output [10:0]axi_w_data_count;
output [10:0]axi_w_wr_data_count;
output [10:0]axi_w_rd_data_count;
output axi_w_sbiterr;
output axi_w_dbiterr;
output axi_w_overflow;
output axi_w_underflow;
output axi_w_prog_full;
output axi_w_prog_empty;
input axi_b_injectsbiterr;
input axi_b_injectdbiterr;
input [3:0]axi_b_prog_full_thresh;
input [3:0]axi_b_prog_empty_thresh;
output [4:0]axi_b_data_count;
output [4:0]axi_b_wr_data_count;
output [4:0]axi_b_rd_data_count;
output axi_b_sbiterr;
output axi_b_dbiterr;
output axi_b_overflow;
output axi_b_underflow;
output axi_b_prog_full;
output axi_b_prog_empty;
input axi_ar_injectsbiterr;
input axi_ar_injectdbiterr;
input [3:0]axi_ar_prog_full_thresh;
input [3:0]axi_ar_prog_empty_thresh;
output [4:0]axi_ar_data_count;
output [4:0]axi_ar_wr_data_count;
output [4:0]axi_ar_rd_data_count;
output axi_ar_sbiterr;
output axi_ar_dbiterr;
output axi_ar_overflow;
output axi_ar_underflow;
output axi_ar_prog_full;
output axi_ar_prog_empty;
input axi_r_injectsbiterr;
input axi_r_injectdbiterr;
input [9:0]axi_r_prog_full_thresh;
input [9:0]axi_r_prog_empty_thresh;
output [10:0]axi_r_data_count;
output [10:0]axi_r_wr_data_count;
output [10:0]axi_r_rd_data_count;
output axi_r_sbiterr;
output axi_r_dbiterr;
output axi_r_overflow;
output axi_r_underflow;
output axi_r_prog_full;
output axi_r_prog_empty;
input axis_injectsbiterr;
input axis_injectdbiterr;
input [9:0]axis_prog_full_thresh;
input [9:0]axis_prog_empty_thresh;
output [10:0]axis_data_count;
output [10:0]axis_wr_data_count;
output [10:0]axis_rd_data_count;
output axis_sbiterr;
output axis_dbiterr;
output axis_overflow;
output axis_underflow;
output axis_prog_full;
output axis_prog_empty;
wire \<const0> ;
wire \<const1> ;
wire clk;
wire [63:0]din;
wire [63:0]dout;
wire empty;
wire full;
wire rd_en;
wire rst;
wire wr_en;
wire wr_rst_busy;
assign almost_empty = \<const0> ;
assign almost_full = \<const0> ;
assign axi_ar_data_count[4] = \<const0> ;
assign axi_ar_data_count[3] = \<const0> ;
assign axi_ar_data_count[2] = \<const0> ;
assign axi_ar_data_count[1] = \<const0> ;
assign axi_ar_data_count[0] = \<const0> ;
assign axi_ar_dbiterr = \<const0> ;
assign axi_ar_overflow = \<const0> ;
assign axi_ar_prog_empty = \<const1> ;
assign axi_ar_prog_full = \<const0> ;
assign axi_ar_rd_data_count[4] = \<const0> ;
assign axi_ar_rd_data_count[3] = \<const0> ;
assign axi_ar_rd_data_count[2] = \<const0> ;
assign axi_ar_rd_data_count[1] = \<const0> ;
assign axi_ar_rd_data_count[0] = \<const0> ;
assign axi_ar_sbiterr = \<const0> ;
assign axi_ar_underflow = \<const0> ;
assign axi_ar_wr_data_count[4] = \<const0> ;
assign axi_ar_wr_data_count[3] = \<const0> ;
assign axi_ar_wr_data_count[2] = \<const0> ;
assign axi_ar_wr_data_count[1] = \<const0> ;
assign axi_ar_wr_data_count[0] = \<const0> ;
assign axi_aw_data_count[4] = \<const0> ;
assign axi_aw_data_count[3] = \<const0> ;
assign axi_aw_data_count[2] = \<const0> ;
assign axi_aw_data_count[1] = \<const0> ;
assign axi_aw_data_count[0] = \<const0> ;
assign axi_aw_dbiterr = \<const0> ;
assign axi_aw_overflow = \<const0> ;
assign axi_aw_prog_empty = \<const1> ;
assign axi_aw_prog_full = \<const0> ;
assign axi_aw_rd_data_count[4] = \<const0> ;
assign axi_aw_rd_data_count[3] = \<const0> ;
assign axi_aw_rd_data_count[2] = \<const0> ;
assign axi_aw_rd_data_count[1] = \<const0> ;
assign axi_aw_rd_data_count[0] = \<const0> ;
assign axi_aw_sbiterr = \<const0> ;
assign axi_aw_underflow = \<const0> ;
assign axi_aw_wr_data_count[4] = \<const0> ;
assign axi_aw_wr_data_count[3] = \<const0> ;
assign axi_aw_wr_data_count[2] = \<const0> ;
assign axi_aw_wr_data_count[1] = \<const0> ;
assign axi_aw_wr_data_count[0] = \<const0> ;
assign axi_b_data_count[4] = \<const0> ;
assign axi_b_data_count[3] = \<const0> ;
assign axi_b_data_count[2] = \<const0> ;
assign axi_b_data_count[1] = \<const0> ;
assign axi_b_data_count[0] = \<const0> ;
assign axi_b_dbiterr = \<const0> ;
assign axi_b_overflow = \<const0> ;
assign axi_b_prog_empty = \<const1> ;
assign axi_b_prog_full = \<const0> ;
assign axi_b_rd_data_count[4] = \<const0> ;
assign axi_b_rd_data_count[3] = \<const0> ;
assign axi_b_rd_data_count[2] = \<const0> ;
assign axi_b_rd_data_count[1] = \<const0> ;
assign axi_b_rd_data_count[0] = \<const0> ;
assign axi_b_sbiterr = \<const0> ;
assign axi_b_underflow = \<const0> ;
assign axi_b_wr_data_count[4] = \<const0> ;
assign axi_b_wr_data_count[3] = \<const0> ;
assign axi_b_wr_data_count[2] = \<const0> ;
assign axi_b_wr_data_count[1] = \<const0> ;
assign axi_b_wr_data_count[0] = \<const0> ;
assign axi_r_data_count[10] = \<const0> ;
assign axi_r_data_count[9] = \<const0> ;
assign axi_r_data_count[8] = \<const0> ;
assign axi_r_data_count[7] = \<const0> ;
assign axi_r_data_count[6] = \<const0> ;
assign axi_r_data_count[5] = \<const0> ;
assign axi_r_data_count[4] = \<const0> ;
assign axi_r_data_count[3] = \<const0> ;
assign axi_r_data_count[2] = \<const0> ;
assign axi_r_data_count[1] = \<const0> ;
assign axi_r_data_count[0] = \<const0> ;
assign axi_r_dbiterr = \<const0> ;
assign axi_r_overflow = \<const0> ;
assign axi_r_prog_empty = \<const1> ;
assign axi_r_prog_full = \<const0> ;
assign axi_r_rd_data_count[10] = \<const0> ;
assign axi_r_rd_data_count[9] = \<const0> ;
assign axi_r_rd_data_count[8] = \<const0> ;
assign axi_r_rd_data_count[7] = \<const0> ;
assign axi_r_rd_data_count[6] = \<const0> ;
assign axi_r_rd_data_count[5] = \<const0> ;
assign axi_r_rd_data_count[4] = \<const0> ;
assign axi_r_rd_data_count[3] = \<const0> ;
assign axi_r_rd_data_count[2] = \<const0> ;
assign axi_r_rd_data_count[1] = \<const0> ;
assign axi_r_rd_data_count[0] = \<const0> ;
assign axi_r_sbiterr = \<const0> ;
assign axi_r_underflow = \<const0> ;
assign axi_r_wr_data_count[10] = \<const0> ;
assign axi_r_wr_data_count[9] = \<const0> ;
assign axi_r_wr_data_count[8] = \<const0> ;
assign axi_r_wr_data_count[7] = \<const0> ;
assign axi_r_wr_data_count[6] = \<const0> ;
assign axi_r_wr_data_count[5] = \<const0> ;
assign axi_r_wr_data_count[4] = \<const0> ;
assign axi_r_wr_data_count[3] = \<const0> ;
assign axi_r_wr_data_count[2] = \<const0> ;
assign axi_r_wr_data_count[1] = \<const0> ;
assign axi_r_wr_data_count[0] = \<const0> ;
assign axi_w_data_count[10] = \<const0> ;
assign axi_w_data_count[9] = \<const0> ;
assign axi_w_data_count[8] = \<const0> ;
assign axi_w_data_count[7] = \<const0> ;
assign axi_w_data_count[6] = \<const0> ;
assign axi_w_data_count[5] = \<const0> ;
assign axi_w_data_count[4] = \<const0> ;
assign axi_w_data_count[3] = \<const0> ;
assign axi_w_data_count[2] = \<const0> ;
assign axi_w_data_count[1] = \<const0> ;
assign axi_w_data_count[0] = \<const0> ;
assign axi_w_dbiterr = \<const0> ;
assign axi_w_overflow = \<const0> ;
assign axi_w_prog_empty = \<const1> ;
assign axi_w_prog_full = \<const0> ;
assign axi_w_rd_data_count[10] = \<const0> ;
assign axi_w_rd_data_count[9] = \<const0> ;
assign axi_w_rd_data_count[8] = \<const0> ;
assign axi_w_rd_data_count[7] = \<const0> ;
assign axi_w_rd_data_count[6] = \<const0> ;
assign axi_w_rd_data_count[5] = \<const0> ;
assign axi_w_rd_data_count[4] = \<const0> ;
assign axi_w_rd_data_count[3] = \<const0> ;
assign axi_w_rd_data_count[2] = \<const0> ;
assign axi_w_rd_data_count[1] = \<const0> ;
assign axi_w_rd_data_count[0] = \<const0> ;
assign axi_w_sbiterr = \<const0> ;
assign axi_w_underflow = \<const0> ;
assign axi_w_wr_data_count[10] = \<const0> ;
assign axi_w_wr_data_count[9] = \<const0> ;
assign axi_w_wr_data_count[8] = \<const0> ;
assign axi_w_wr_data_count[7] = \<const0> ;
assign axi_w_wr_data_count[6] = \<const0> ;
assign axi_w_wr_data_count[5] = \<const0> ;
assign axi_w_wr_data_count[4] = \<const0> ;
assign axi_w_wr_data_count[3] = \<const0> ;
assign axi_w_wr_data_count[2] = \<const0> ;
assign axi_w_wr_data_count[1] = \<const0> ;
assign axi_w_wr_data_count[0] = \<const0> ;
assign axis_data_count[10] = \<const0> ;
assign axis_data_count[9] = \<const0> ;
assign axis_data_count[8] = \<const0> ;
assign axis_data_count[7] = \<const0> ;
assign axis_data_count[6] = \<const0> ;
assign axis_data_count[5] = \<const0> ;
assign axis_data_count[4] = \<const0> ;
assign axis_data_count[3] = \<const0> ;
assign axis_data_count[2] = \<const0> ;
assign axis_data_count[1] = \<const0> ;
assign axis_data_count[0] = \<const0> ;
assign axis_dbiterr = \<const0> ;
assign axis_overflow = \<const0> ;
assign axis_prog_empty = \<const1> ;
assign axis_prog_full = \<const0> ;
assign axis_rd_data_count[10] = \<const0> ;
assign axis_rd_data_count[9] = \<const0> ;
assign axis_rd_data_count[8] = \<const0> ;
assign axis_rd_data_count[7] = \<const0> ;
assign axis_rd_data_count[6] = \<const0> ;
assign axis_rd_data_count[5] = \<const0> ;
assign axis_rd_data_count[4] = \<const0> ;
assign axis_rd_data_count[3] = \<const0> ;
assign axis_rd_data_count[2] = \<const0> ;
assign axis_rd_data_count[1] = \<const0> ;
assign axis_rd_data_count[0] = \<const0> ;
assign axis_sbiterr = \<const0> ;
assign axis_underflow = \<const0> ;
assign axis_wr_data_count[10] = \<const0> ;
assign axis_wr_data_count[9] = \<const0> ;
assign axis_wr_data_count[8] = \<const0> ;
assign axis_wr_data_count[7] = \<const0> ;
assign axis_wr_data_count[6] = \<const0> ;
assign axis_wr_data_count[5] = \<const0> ;
assign axis_wr_data_count[4] = \<const0> ;
assign axis_wr_data_count[3] = \<const0> ;
assign axis_wr_data_count[2] = \<const0> ;
assign axis_wr_data_count[1] = \<const0> ;
assign axis_wr_data_count[0] = \<const0> ;
assign data_count[10] = \<const0> ;
assign data_count[9] = \<const0> ;
assign data_count[8] = \<const0> ;
assign data_count[7] = \<const0> ;
assign data_count[6] = \<const0> ;
assign data_count[5] = \<const0> ;
assign data_count[4] = \<const0> ;
assign data_count[3] = \<const0> ;
assign data_count[2] = \<const0> ;
assign data_count[1] = \<const0> ;
assign data_count[0] = \<const0> ;
assign dbiterr = \<const0> ;
assign m_axi_araddr[31] = \<const0> ;
assign m_axi_araddr[30] = \<const0> ;
assign m_axi_araddr[29] = \<const0> ;
assign m_axi_araddr[28] = \<const0> ;
assign m_axi_araddr[27] = \<const0> ;
assign m_axi_araddr[26] = \<const0> ;
assign m_axi_araddr[25] = \<const0> ;
assign m_axi_araddr[24] = \<const0> ;
assign m_axi_araddr[23] = \<const0> ;
assign m_axi_araddr[22] = \<const0> ;
assign m_axi_araddr[21] = \<const0> ;
assign m_axi_araddr[20] = \<const0> ;
assign m_axi_araddr[19] = \<const0> ;
assign m_axi_araddr[18] = \<const0> ;
assign m_axi_araddr[17] = \<const0> ;
assign m_axi_araddr[16] = \<const0> ;
assign m_axi_araddr[15] = \<const0> ;
assign m_axi_araddr[14] = \<const0> ;
assign m_axi_araddr[13] = \<const0> ;
assign m_axi_araddr[12] = \<const0> ;
assign m_axi_araddr[11] = \<const0> ;
assign m_axi_araddr[10] = \<const0> ;
assign m_axi_araddr[9] = \<const0> ;
assign m_axi_araddr[8] = \<const0> ;
assign m_axi_araddr[7] = \<const0> ;
assign m_axi_araddr[6] = \<const0> ;
assign m_axi_araddr[5] = \<const0> ;
assign m_axi_araddr[4] = \<const0> ;
assign m_axi_araddr[3] = \<const0> ;
assign m_axi_araddr[2] = \<const0> ;
assign m_axi_araddr[1] = \<const0> ;
assign m_axi_araddr[0] = \<const0> ;
assign m_axi_arburst[1] = \<const0> ;
assign m_axi_arburst[0] = \<const0> ;
assign m_axi_arcache[3] = \<const0> ;
assign m_axi_arcache[2] = \<const0> ;
assign m_axi_arcache[1] = \<const0> ;
assign m_axi_arcache[0] = \<const0> ;
assign m_axi_arid[0] = \<const0> ;
assign m_axi_arlen[7] = \<const0> ;
assign m_axi_arlen[6] = \<const0> ;
assign m_axi_arlen[5] = \<const0> ;
assign m_axi_arlen[4] = \<const0> ;
assign m_axi_arlen[3] = \<const0> ;
assign m_axi_arlen[2] = \<const0> ;
assign m_axi_arlen[1] = \<const0> ;
assign m_axi_arlen[0] = \<const0> ;
assign m_axi_arlock[0] = \<const0> ;
assign m_axi_arprot[2] = \<const0> ;
assign m_axi_arprot[1] = \<const0> ;
assign m_axi_arprot[0] = \<const0> ;
assign m_axi_arqos[3] = \<const0> ;
assign m_axi_arqos[2] = \<const0> ;
assign m_axi_arqos[1] = \<const0> ;
assign m_axi_arqos[0] = \<const0> ;
assign m_axi_arregion[3] = \<const0> ;
assign m_axi_arregion[2] = \<const0> ;
assign m_axi_arregion[1] = \<const0> ;
assign m_axi_arregion[0] = \<const0> ;
assign m_axi_arsize[2] = \<const0> ;
assign m_axi_arsize[1] = \<const0> ;
assign m_axi_arsize[0] = \<const0> ;
assign m_axi_aruser[0] = \<const0> ;
assign m_axi_arvalid = \<const0> ;
assign m_axi_awaddr[31] = \<const0> ;
assign m_axi_awaddr[30] = \<const0> ;
assign m_axi_awaddr[29] = \<const0> ;
assign m_axi_awaddr[28] = \<const0> ;
assign m_axi_awaddr[27] = \<const0> ;
assign m_axi_awaddr[26] = \<const0> ;
assign m_axi_awaddr[25] = \<const0> ;
assign m_axi_awaddr[24] = \<const0> ;
assign m_axi_awaddr[23] = \<const0> ;
assign m_axi_awaddr[22] = \<const0> ;
assign m_axi_awaddr[21] = \<const0> ;
assign m_axi_awaddr[20] = \<const0> ;
assign m_axi_awaddr[19] = \<const0> ;
assign m_axi_awaddr[18] = \<const0> ;
assign m_axi_awaddr[17] = \<const0> ;
assign m_axi_awaddr[16] = \<const0> ;
assign m_axi_awaddr[15] = \<const0> ;
assign m_axi_awaddr[14] = \<const0> ;
assign m_axi_awaddr[13] = \<const0> ;
assign m_axi_awaddr[12] = \<const0> ;
assign m_axi_awaddr[11] = \<const0> ;
assign m_axi_awaddr[10] = \<const0> ;
assign m_axi_awaddr[9] = \<const0> ;
assign m_axi_awaddr[8] = \<const0> ;
assign m_axi_awaddr[7] = \<const0> ;
assign m_axi_awaddr[6] = \<const0> ;
assign m_axi_awaddr[5] = \<const0> ;
assign m_axi_awaddr[4] = \<const0> ;
assign m_axi_awaddr[3] = \<const0> ;
assign m_axi_awaddr[2] = \<const0> ;
assign m_axi_awaddr[1] = \<const0> ;
assign m_axi_awaddr[0] = \<const0> ;
assign m_axi_awburst[1] = \<const0> ;
assign m_axi_awburst[0] = \<const0> ;
assign m_axi_awcache[3] = \<const0> ;
assign m_axi_awcache[2] = \<const0> ;
assign m_axi_awcache[1] = \<const0> ;
assign m_axi_awcache[0] = \<const0> ;
assign m_axi_awid[0] = \<const0> ;
assign m_axi_awlen[7] = \<const0> ;
assign m_axi_awlen[6] = \<const0> ;
assign m_axi_awlen[5] = \<const0> ;
assign m_axi_awlen[4] = \<const0> ;
assign m_axi_awlen[3] = \<const0> ;
assign m_axi_awlen[2] = \<const0> ;
assign m_axi_awlen[1] = \<const0> ;
assign m_axi_awlen[0] = \<const0> ;
assign m_axi_awlock[0] = \<const0> ;
assign m_axi_awprot[2] = \<const0> ;
assign m_axi_awprot[1] = \<const0> ;
assign m_axi_awprot[0] = \<const0> ;
assign m_axi_awqos[3] = \<const0> ;
assign m_axi_awqos[2] = \<const0> ;
assign m_axi_awqos[1] = \<const0> ;
assign m_axi_awqos[0] = \<const0> ;
assign m_axi_awregion[3] = \<const0> ;
assign m_axi_awregion[2] = \<const0> ;
assign m_axi_awregion[1] = \<const0> ;
assign m_axi_awregion[0] = \<const0> ;
assign m_axi_awsize[2] = \<const0> ;
assign m_axi_awsize[1] = \<const0> ;
assign m_axi_awsize[0] = \<const0> ;
assign m_axi_awuser[0] = \<const0> ;
assign m_axi_awvalid = \<const0> ;
assign m_axi_bready = \<const0> ;
assign m_axi_rready = \<const0> ;
assign m_axi_wdata[63] = \<const0> ;
assign m_axi_wdata[62] = \<const0> ;
assign m_axi_wdata[61] = \<const0> ;
assign m_axi_wdata[60] = \<const0> ;
assign m_axi_wdata[59] = \<const0> ;
assign m_axi_wdata[58] = \<const0> ;
assign m_axi_wdata[57] = \<const0> ;
assign m_axi_wdata[56] = \<const0> ;
assign m_axi_wdata[55] = \<const0> ;
assign m_axi_wdata[54] = \<const0> ;
assign m_axi_wdata[53] = \<const0> ;
assign m_axi_wdata[52] = \<const0> ;
assign m_axi_wdata[51] = \<const0> ;
assign m_axi_wdata[50] = \<const0> ;
assign m_axi_wdata[49] = \<const0> ;
assign m_axi_wdata[48] = \<const0> ;
assign m_axi_wdata[47] = \<const0> ;
assign m_axi_wdata[46] = \<const0> ;
assign m_axi_wdata[45] = \<const0> ;
assign m_axi_wdata[44] = \<const0> ;
assign m_axi_wdata[43] = \<const0> ;
assign m_axi_wdata[42] = \<const0> ;
assign m_axi_wdata[41] = \<const0> ;
assign m_axi_wdata[40] = \<const0> ;
assign m_axi_wdata[39] = \<const0> ;
assign m_axi_wdata[38] = \<const0> ;
assign m_axi_wdata[37] = \<const0> ;
assign m_axi_wdata[36] = \<const0> ;
assign m_axi_wdata[35] = \<const0> ;
assign m_axi_wdata[34] = \<const0> ;
assign m_axi_wdata[33] = \<const0> ;
assign m_axi_wdata[32] = \<const0> ;
assign m_axi_wdata[31] = \<const0> ;
assign m_axi_wdata[30] = \<const0> ;
assign m_axi_wdata[29] = \<const0> ;
assign m_axi_wdata[28] = \<const0> ;
assign m_axi_wdata[27] = \<const0> ;
assign m_axi_wdata[26] = \<const0> ;
assign m_axi_wdata[25] = \<const0> ;
assign m_axi_wdata[24] = \<const0> ;
assign m_axi_wdata[23] = \<const0> ;
assign m_axi_wdata[22] = \<const0> ;
assign m_axi_wdata[21] = \<const0> ;
assign m_axi_wdata[20] = \<const0> ;
assign m_axi_wdata[19] = \<const0> ;
assign m_axi_wdata[18] = \<const0> ;
assign m_axi_wdata[17] = \<const0> ;
assign m_axi_wdata[16] = \<const0> ;
assign m_axi_wdata[15] = \<const0> ;
assign m_axi_wdata[14] = \<const0> ;
assign m_axi_wdata[13] = \<const0> ;
assign m_axi_wdata[12] = \<const0> ;
assign m_axi_wdata[11] = \<const0> ;
assign m_axi_wdata[10] = \<const0> ;
assign m_axi_wdata[9] = \<const0> ;
assign m_axi_wdata[8] = \<const0> ;
assign m_axi_wdata[7] = \<const0> ;
assign m_axi_wdata[6] = \<const0> ;
assign m_axi_wdata[5] = \<const0> ;
assign m_axi_wdata[4] = \<const0> ;
assign m_axi_wdata[3] = \<const0> ;
assign m_axi_wdata[2] = \<const0> ;
assign m_axi_wdata[1] = \<const0> ;
assign m_axi_wdata[0] = \<const0> ;
assign m_axi_wid[0] = \<const0> ;
assign m_axi_wlast = \<const0> ;
assign m_axi_wstrb[7] = \<const0> ;
assign m_axi_wstrb[6] = \<const0> ;
assign m_axi_wstrb[5] = \<const0> ;
assign m_axi_wstrb[4] = \<const0> ;
assign m_axi_wstrb[3] = \<const0> ;
assign m_axi_wstrb[2] = \<const0> ;
assign m_axi_wstrb[1] = \<const0> ;
assign m_axi_wstrb[0] = \<const0> ;
assign m_axi_wuser[0] = \<const0> ;
assign m_axi_wvalid = \<const0> ;
assign m_axis_tdata[7] = \<const0> ;
assign m_axis_tdata[6] = \<const0> ;
assign m_axis_tdata[5] = \<const0> ;
assign m_axis_tdata[4] = \<const0> ;
assign m_axis_tdata[3] = \<const0> ;
assign m_axis_tdata[2] = \<const0> ;
assign m_axis_tdata[1] = \<const0> ;
assign m_axis_tdata[0] = \<const0> ;
assign m_axis_tdest[0] = \<const0> ;
assign m_axis_tid[0] = \<const0> ;
assign m_axis_tkeep[0] = \<const0> ;
assign m_axis_tlast = \<const0> ;
assign m_axis_tstrb[0] = \<const0> ;
assign m_axis_tuser[3] = \<const0> ;
assign m_axis_tuser[2] = \<const0> ;
assign m_axis_tuser[1] = \<const0> ;
assign m_axis_tuser[0] = \<const0> ;
assign m_axis_tvalid = \<const0> ;
assign overflow = \<const0> ;
assign prog_empty = \<const0> ;
assign prog_full = \<const0> ;
assign rd_data_count[10] = \<const0> ;
assign rd_data_count[9] = \<const0> ;
assign rd_data_count[8] = \<const0> ;
assign rd_data_count[7] = \<const0> ;
assign rd_data_count[6] = \<const0> ;
assign rd_data_count[5] = \<const0> ;
assign rd_data_count[4] = \<const0> ;
assign rd_data_count[3] = \<const0> ;
assign rd_data_count[2] = \<const0> ;
assign rd_data_count[1] = \<const0> ;
assign rd_data_count[0] = \<const0> ;
assign rd_rst_busy = \<const0> ;
assign s_axi_arready = \<const0> ;
assign s_axi_awready = \<const0> ;
assign s_axi_bid[0] = \<const0> ;
assign s_axi_bresp[1] = \<const0> ;
assign s_axi_bresp[0] = \<const0> ;
assign s_axi_buser[0] = \<const0> ;
assign s_axi_bvalid = \<const0> ;
assign s_axi_rdata[63] = \<const0> ;
assign s_axi_rdata[62] = \<const0> ;
assign s_axi_rdata[61] = \<const0> ;
assign s_axi_rdata[60] = \<const0> ;
assign s_axi_rdata[59] = \<const0> ;
assign s_axi_rdata[58] = \<const0> ;
assign s_axi_rdata[57] = \<const0> ;
assign s_axi_rdata[56] = \<const0> ;
assign s_axi_rdata[55] = \<const0> ;
assign s_axi_rdata[54] = \<const0> ;
assign s_axi_rdata[53] = \<const0> ;
assign s_axi_rdata[52] = \<const0> ;
assign s_axi_rdata[51] = \<const0> ;
assign s_axi_rdata[50] = \<const0> ;
assign s_axi_rdata[49] = \<const0> ;
assign s_axi_rdata[48] = \<const0> ;
assign s_axi_rdata[47] = \<const0> ;
assign s_axi_rdata[46] = \<const0> ;
assign s_axi_rdata[45] = \<const0> ;
assign s_axi_rdata[44] = \<const0> ;
assign s_axi_rdata[43] = \<const0> ;
assign s_axi_rdata[42] = \<const0> ;
assign s_axi_rdata[41] = \<const0> ;
assign s_axi_rdata[40] = \<const0> ;
assign s_axi_rdata[39] = \<const0> ;
assign s_axi_rdata[38] = \<const0> ;
assign s_axi_rdata[37] = \<const0> ;
assign s_axi_rdata[36] = \<const0> ;
assign s_axi_rdata[35] = \<const0> ;
assign s_axi_rdata[34] = \<const0> ;
assign s_axi_rdata[33] = \<const0> ;
assign s_axi_rdata[32] = \<const0> ;
assign s_axi_rdata[31] = \<const0> ;
assign s_axi_rdata[30] = \<const0> ;
assign s_axi_rdata[29] = \<const0> ;
assign s_axi_rdata[28] = \<const0> ;
assign s_axi_rdata[27] = \<const0> ;
assign s_axi_rdata[26] = \<const0> ;
assign s_axi_rdata[25] = \<const0> ;
assign s_axi_rdata[24] = \<const0> ;
assign s_axi_rdata[23] = \<const0> ;
assign s_axi_rdata[22] = \<const0> ;
assign s_axi_rdata[21] = \<const0> ;
assign s_axi_rdata[20] = \<const0> ;
assign s_axi_rdata[19] = \<const0> ;
assign s_axi_rdata[18] = \<const0> ;
assign s_axi_rdata[17] = \<const0> ;
assign s_axi_rdata[16] = \<const0> ;
assign s_axi_rdata[15] = \<const0> ;
assign s_axi_rdata[14] = \<const0> ;
assign s_axi_rdata[13] = \<const0> ;
assign s_axi_rdata[12] = \<const0> ;
assign s_axi_rdata[11] = \<const0> ;
assign s_axi_rdata[10] = \<const0> ;
assign s_axi_rdata[9] = \<const0> ;
assign s_axi_rdata[8] = \<const0> ;
assign s_axi_rdata[7] = \<const0> ;
assign s_axi_rdata[6] = \<const0> ;
assign s_axi_rdata[5] = \<const0> ;
assign s_axi_rdata[4] = \<const0> ;
assign s_axi_rdata[3] = \<const0> ;
assign s_axi_rdata[2] = \<const0> ;
assign s_axi_rdata[1] = \<const0> ;
assign s_axi_rdata[0] = \<const0> ;
assign s_axi_rid[0] = \<const0> ;
assign s_axi_rlast = \<const0> ;
assign s_axi_rresp[1] = \<const0> ;
assign s_axi_rresp[0] = \<const0> ;
assign s_axi_ruser[0] = \<const0> ;
assign s_axi_rvalid = \<const0> ;
assign s_axi_wready = \<const0> ;
assign s_axis_tready = \<const0> ;
assign sbiterr = \<const0> ;
assign underflow = \<const0> ;
assign valid = \<const0> ;
assign wr_ack = \<const0> ;
assign wr_data_count[10] = \<const0> ;
assign wr_data_count[9] = \<const0> ;
assign wr_data_count[8] = \<const0> ;
assign wr_data_count[7] = \<const0> ;
assign wr_data_count[6] = \<const0> ;
assign wr_data_count[5] = \<const0> ;
assign wr_data_count[4] = \<const0> ;
assign wr_data_count[3] = \<const0> ;
assign wr_data_count[2] = \<const0> ;
assign wr_data_count[1] = \<const0> ;
assign wr_data_count[0] = \<const0> ;
GND GND
(.G(\<const0> ));
VCC VCC
(.P(\<const1> ));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2_synth inst_fifo_gen
(.clk(clk),
.din(din),
.dout(dout),
.empty(empty),
.full(full),
.rd_en(rd_en),
.rst(rst),
.wr_en(wr_en),
.wr_rst_busy(wr_rst_busy));
endmodule
|
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2_synth
(wr_rst_busy,
dout,
empty,
full,
rd_en,
wr_en,
clk,
din,
rst);
output wr_rst_busy;
output [63:0]dout;
output empty;
output full;
input rd_en;
input wr_en;
input clk;
input [63:0]din;
input rst;
wire clk;
wire [63:0]din;
wire [63:0]dout;
wire empty;
wire full;
wire rd_en;
wire rst;
wire wr_en;
wire wr_rst_busy;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_top \gconvfifo.rf
(.clk(clk),
.din(din),
.dout(dout),
.empty(empty),
.full(full),
.rd_en(rd_en),
.rst(rst),
.wr_en(wr_en),
.wr_rst_busy(wr_rst_busy));
endmodule
|
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_memory
(dout,
clk,
ram_full_fb_i_reg,
tmp_ram_rd_en,
out,
\gcc0.gc0.count_d1_reg[10] ,
Q,
din);
output [63:0]dout;
input clk;
input ram_full_fb_i_reg;
input tmp_ram_rd_en;
input [0:0]out;
input [10:0]\gcc0.gc0.count_d1_reg[10] ;
input [10:0]Q;
input [63:0]din;
wire [10:0]Q;
wire clk;
wire [63:0]din;
wire [63:0]dout;
wire [10:0]\gcc0.gc0.count_d1_reg[10] ;
wire [0:0]out;
wire ram_full_fb_i_reg;
wire tmp_ram_rd_en;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_4 \gbm.gbmg.gbmga.ngecc.bmg
(.Q(Q),
.clk(clk),
.din(din),
.dout(dout),
.\gcc0.gc0.count_d1_reg[10] (\gcc0.gc0.count_d1_reg[10] ),
.out(out),
.ram_full_fb_i_reg(ram_full_fb_i_reg),
.tmp_ram_rd_en(tmp_ram_rd_en));
endmodule
|
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_bin_cntr
(ram_full_i_reg,
Q,
ram_empty_i_reg,
ram_full_i_reg_0,
ram_empty_i_reg_0,
\gc0.count_d1_reg[9]_0 ,
\gcc0.gc0.count_d1_reg[10] ,
\gcc0.gc0.count_reg[10] ,
E,
clk,
AR);
output ram_full_i_reg;
output [10:0]Q;
output ram_empty_i_reg;
output ram_full_i_reg_0;
output ram_empty_i_reg_0;
output [9:0]\gc0.count_d1_reg[9]_0 ;
input [0:0]\gcc0.gc0.count_d1_reg[10] ;
input [0:0]\gcc0.gc0.count_reg[10] ;
input [0:0]E;
input clk;
input [0:0]AR;
wire [0:0]AR;
wire [0:0]E;
wire [10:0]Q;
wire clk;
wire \gc0.count[10]_i_2_n_0 ;
wire [9:0]\gc0.count_d1_reg[9]_0 ;
wire [0:0]\gcc0.gc0.count_d1_reg[10] ;
wire [0:0]\gcc0.gc0.count_reg[10] ;
wire [10:0]plusOp;
wire ram_empty_i_reg;
wire ram_empty_i_reg_0;
wire ram_full_i_reg;
wire ram_full_i_reg_0;
wire [10:10]rd_pntr_plus1;
LUT1 #(
.INIT(2'h1))
\gc0.count[0]_i_1
(.I0(\gc0.count_d1_reg[9]_0 [0]),
.O(plusOp[0]));
LUT6 #(
.INIT(64'h7FFFFFFF80000000))
\gc0.count[10]_i_1
(.I0(\gc0.count_d1_reg[9]_0 [8]),
.I1(\gc0.count_d1_reg[9]_0 [6]),
.I2(\gc0.count[10]_i_2_n_0 ),
.I3(\gc0.count_d1_reg[9]_0 [7]),
.I4(\gc0.count_d1_reg[9]_0 [9]),
.I5(rd_pntr_plus1),
.O(plusOp[10]));
LUT6 #(
.INIT(64'h8000000000000000))
\gc0.count[10]_i_2
(.I0(\gc0.count_d1_reg[9]_0 [5]),
.I1(\gc0.count_d1_reg[9]_0 [3]),
.I2(\gc0.count_d1_reg[9]_0 [1]),
.I3(\gc0.count_d1_reg[9]_0 [0]),
.I4(\gc0.count_d1_reg[9]_0 [2]),
.I5(\gc0.count_d1_reg[9]_0 [4]),
.O(\gc0.count[10]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT2 #(
.INIT(4'h6))
\gc0.count[1]_i_1
(.I0(\gc0.count_d1_reg[9]_0 [0]),
.I1(\gc0.count_d1_reg[9]_0 [1]),
.O(plusOp[1]));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT3 #(
.INIT(8'h78))
\gc0.count[2]_i_1
(.I0(\gc0.count_d1_reg[9]_0 [0]),
.I1(\gc0.count_d1_reg[9]_0 [1]),
.I2(\gc0.count_d1_reg[9]_0 [2]),
.O(plusOp[2]));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT4 #(
.INIT(16'h7F80))
\gc0.count[3]_i_1
(.I0(\gc0.count_d1_reg[9]_0 [1]),
.I1(\gc0.count_d1_reg[9]_0 [0]),
.I2(\gc0.count_d1_reg[9]_0 [2]),
.I3(\gc0.count_d1_reg[9]_0 [3]),
.O(plusOp[3]));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT5 #(
.INIT(32'h7FFF8000))
\gc0.count[4]_i_1
(.I0(\gc0.count_d1_reg[9]_0 [2]),
.I1(\gc0.count_d1_reg[9]_0 [0]),
.I2(\gc0.count_d1_reg[9]_0 [1]),
.I3(\gc0.count_d1_reg[9]_0 [3]),
.I4(\gc0.count_d1_reg[9]_0 [4]),
.O(plusOp[4]));
LUT6 #(
.INIT(64'h7FFFFFFF80000000))
\gc0.count[5]_i_1
(.I0(\gc0.count_d1_reg[9]_0 [3]),
.I1(\gc0.count_d1_reg[9]_0 [1]),
.I2(\gc0.count_d1_reg[9]_0 [0]),
.I3(\gc0.count_d1_reg[9]_0 [2]),
.I4(\gc0.count_d1_reg[9]_0 [4]),
.I5(\gc0.count_d1_reg[9]_0 [5]),
.O(plusOp[5]));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT2 #(
.INIT(4'h6))
\gc0.count[6]_i_1
(.I0(\gc0.count[10]_i_2_n_0 ),
.I1(\gc0.count_d1_reg[9]_0 [6]),
.O(plusOp[6]));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT3 #(
.INIT(8'h78))
\gc0.count[7]_i_1
(.I0(\gc0.count[10]_i_2_n_0 ),
.I1(\gc0.count_d1_reg[9]_0 [6]),
.I2(\gc0.count_d1_reg[9]_0 [7]),
.O(plusOp[7]));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT4 #(
.INIT(16'h7F80))
\gc0.count[8]_i_1
(.I0(\gc0.count_d1_reg[9]_0 [6]),
.I1(\gc0.count[10]_i_2_n_0 ),
.I2(\gc0.count_d1_reg[9]_0 [7]),
.I3(\gc0.count_d1_reg[9]_0 [8]),
.O(plusOp[8]));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT5 #(
.INIT(32'h7FFF8000))
\gc0.count[9]_i_1
(.I0(\gc0.count_d1_reg[9]_0 [7]),
.I1(\gc0.count[10]_i_2_n_0 ),
.I2(\gc0.count_d1_reg[9]_0 [6]),
.I3(\gc0.count_d1_reg[9]_0 [8]),
.I4(\gc0.count_d1_reg[9]_0 [9]),
.O(plusOp[9]));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[0]
(.C(clk),
.CE(E),
.CLR(AR),
.D(\gc0.count_d1_reg[9]_0 [0]),
.Q(Q[0]));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[10]
(.C(clk),
.CE(E),
.CLR(AR),
.D(rd_pntr_plus1),
.Q(Q[10]));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[1]
(.C(clk),
.CE(E),
.CLR(AR),
.D(\gc0.count_d1_reg[9]_0 [1]),
.Q(Q[1]));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[2]
(.C(clk),
.CE(E),
.CLR(AR),
.D(\gc0.count_d1_reg[9]_0 [2]),
.Q(Q[2]));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[3]
(.C(clk),
.CE(E),
.CLR(AR),
.D(\gc0.count_d1_reg[9]_0 [3]),
.Q(Q[3]));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[4]
(.C(clk),
.CE(E),
.CLR(AR),
.D(\gc0.count_d1_reg[9]_0 [4]),
.Q(Q[4]));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[5]
(.C(clk),
.CE(E),
.CLR(AR),
.D(\gc0.count_d1_reg[9]_0 [5]),
.Q(Q[5]));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[6]
(.C(clk),
.CE(E),
.CLR(AR),
.D(\gc0.count_d1_reg[9]_0 [6]),
.Q(Q[6]));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[7]
(.C(clk),
.CE(E),
.CLR(AR),
.D(\gc0.count_d1_reg[9]_0 [7]),
.Q(Q[7]));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[8]
(.C(clk),
.CE(E),
.CLR(AR),
.D(\gc0.count_d1_reg[9]_0 [8]),
.Q(Q[8]));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[9]
(.C(clk),
.CE(E),
.CLR(AR),
.D(\gc0.count_d1_reg[9]_0 [9]),
.Q(Q[9]));
FDPE #(
.INIT(1'b1))
\gc0.count_reg[0]
(.C(clk),
.CE(E),
.D(plusOp[0]),
.PRE(AR),
.Q(\gc0.count_d1_reg[9]_0 [0]));
FDCE #(
.INIT(1'b0))
\gc0.count_reg[10]
(.C(clk),
.CE(E),
.CLR(AR),
.D(plusOp[10]),
.Q(rd_pntr_plus1));
FDCE #(
.INIT(1'b0))
\gc0.count_reg[1]
(.C(clk),
.CE(E),
.CLR(AR),
.D(plusOp[1]),
.Q(\gc0.count_d1_reg[9]_0 [1]));
FDCE #(
.INIT(1'b0))
\gc0.count_reg[2]
(.C(clk),
.CE(E),
.CLR(AR),
.D(plusOp[2]),
.Q(\gc0.count_d1_reg[9]_0 [2]));
FDCE #(
.INIT(1'b0))
\gc0.count_reg[3]
(.C(clk),
.CE(E),
.CLR(AR),
.D(plusOp[3]),
.Q(\gc0.count_d1_reg[9]_0 [3]));
FDCE #(
.INIT(1'b0))
\gc0.count_reg[4]
(.C(clk),
.CE(E),
.CLR(AR),
.D(plusOp[4]),
.Q(\gc0.count_d1_reg[9]_0 [4]));
FDCE #(
.INIT(1'b0))
\gc0.count_reg[5]
(.C(clk),
.CE(E),
.CLR(AR),
.D(plusOp[5]),
.Q(\gc0.count_d1_reg[9]_0 [5]));
FDCE #(
.INIT(1'b0))
\gc0.count_reg[6]
(.C(clk),
.CE(E),
.CLR(AR),
.D(plusOp[6]),
.Q(\gc0.count_d1_reg[9]_0 [6]));
FDCE #(
.INIT(1'b0))
\gc0.count_reg[7]
(.C(clk),
.CE(E),
.CLR(AR),
.D(plusOp[7]),
.Q(\gc0.count_d1_reg[9]_0 [7]));
FDCE #(
.INIT(1'b0))
\gc0.count_reg[8]
(.C(clk),
.CE(E),
.CLR(AR),
.D(plusOp[8]),
.Q(\gc0.count_d1_reg[9]_0 [8]));
FDCE #(
.INIT(1'b0))
\gc0.count_reg[9]
(.C(clk),
.CE(E),
.CLR(AR),
.D(plusOp[9]),
.Q(\gc0.count_d1_reg[9]_0 [9]));
LUT2 #(
.INIT(4'h9))
\gmux.gm[5].gms.ms_i_1
(.I0(Q[10]),
.I1(\gcc0.gc0.count_d1_reg[10] ),
.O(ram_full_i_reg));
LUT2 #(
.INIT(4'h9))
\gmux.gm[5].gms.ms_i_1__0
(.I0(rd_pntr_plus1),
.I1(\gcc0.gc0.count_d1_reg[10] ),
.O(ram_empty_i_reg));
LUT2 #(
.INIT(4'h9))
\gmux.gm[5].gms.ms_i_1__1
(.I0(Q[10]),
.I1(\gcc0.gc0.count_reg[10] ),
.O(ram_full_i_reg_0));
LUT2 #(
.INIT(4'h9))
\gmux.gm[5].gms.ms_i_1__2
(.I0(Q[10]),
.I1(\gcc0.gc0.count_d1_reg[10] ),
.O(ram_empty_i_reg_0));
endmodule
|
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_logic
(out,
empty,
E,
ram_full_i_reg,
Q,
\gc0.count_d1_reg[9] ,
ram_full_i_reg_0,
\gcc0.gc0.count_d1_reg[0] ,
\gcc0.gc0.count_d1_reg[2] ,
\gcc0.gc0.count_d1_reg[4] ,
\gcc0.gc0.count_d1_reg[6] ,
\gcc0.gc0.count_d1_reg[8] ,
v1_reg,
clk,
AR,
rd_en,
\gcc0.gc0.count_d1_reg[10] ,
\gcc0.gc0.count_reg[10] ,
wr_en,
ram_full_fb_i_reg);
output out;
output empty;
output [0:0]E;
output ram_full_i_reg;
output [10:0]Q;
output [9:0]\gc0.count_d1_reg[9] ;
output ram_full_i_reg_0;
input \gcc0.gc0.count_d1_reg[0] ;
input \gcc0.gc0.count_d1_reg[2] ;
input \gcc0.gc0.count_d1_reg[4] ;
input \gcc0.gc0.count_d1_reg[6] ;
input \gcc0.gc0.count_d1_reg[8] ;
input [4:0]v1_reg;
input clk;
input [0:0]AR;
input rd_en;
input [0:0]\gcc0.gc0.count_d1_reg[10] ;
input [0:0]\gcc0.gc0.count_reg[10] ;
input wr_en;
input ram_full_fb_i_reg;
wire [0:0]AR;
wire [0:0]E;
wire [10:0]Q;
wire clk;
wire empty;
wire [9:0]\gc0.count_d1_reg[9] ;
wire \gcc0.gc0.count_d1_reg[0] ;
wire [0:0]\gcc0.gc0.count_d1_reg[10] ;
wire \gcc0.gc0.count_d1_reg[2] ;
wire \gcc0.gc0.count_d1_reg[4] ;
wire \gcc0.gc0.count_d1_reg[6] ;
wire \gcc0.gc0.count_d1_reg[8] ;
wire [0:0]\gcc0.gc0.count_reg[10] ;
wire out;
wire ram_full_fb_i_reg;
wire ram_full_i_reg;
wire ram_full_i_reg_0;
wire rd_en;
wire rpntr_n_12;
wire rpntr_n_14;
wire [4:0]v1_reg;
wire wr_en;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_status_flags_ss \grss.rsts
(.AR(AR),
.E(E),
.clk(clk),
.empty(empty),
.\gc0.count_d1_reg[10] (rpntr_n_14),
.\gc0.count_reg[10] (rpntr_n_12),
.\gcc0.gc0.count_d1_reg[0] (\gcc0.gc0.count_d1_reg[0] ),
.\gcc0.gc0.count_d1_reg[2] (\gcc0.gc0.count_d1_reg[2] ),
.\gcc0.gc0.count_d1_reg[4] (\gcc0.gc0.count_d1_reg[4] ),
.\gcc0.gc0.count_d1_reg[6] (\gcc0.gc0.count_d1_reg[6] ),
.\gcc0.gc0.count_d1_reg[8] (\gcc0.gc0.count_d1_reg[8] ),
.out(out),
.ram_full_fb_i_reg(ram_full_fb_i_reg),
.rd_en(rd_en),
.v1_reg(v1_reg),
.wr_en(wr_en));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_bin_cntr rpntr
(.AR(AR),
.E(E),
.Q(Q),
.clk(clk),
.\gc0.count_d1_reg[9]_0 (\gc0.count_d1_reg[9] ),
.\gcc0.gc0.count_d1_reg[10] (\gcc0.gc0.count_d1_reg[10] ),
.\gcc0.gc0.count_reg[10] (\gcc0.gc0.count_reg[10] ),
.ram_empty_i_reg(rpntr_n_12),
.ram_empty_i_reg_0(rpntr_n_14),
.ram_full_i_reg(ram_full_i_reg),
.ram_full_i_reg_0(ram_full_i_reg_0));
endmodule
|
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_status_flags_ss
(out,
empty,
E,
\gcc0.gc0.count_d1_reg[0] ,
\gcc0.gc0.count_d1_reg[2] ,
\gcc0.gc0.count_d1_reg[4] ,
\gcc0.gc0.count_d1_reg[6] ,
\gcc0.gc0.count_d1_reg[8] ,
\gc0.count_d1_reg[10] ,
v1_reg,
\gc0.count_reg[10] ,
clk,
AR,
rd_en,
wr_en,
ram_full_fb_i_reg);
output out;
output empty;
output [0:0]E;
input \gcc0.gc0.count_d1_reg[0] ;
input \gcc0.gc0.count_d1_reg[2] ;
input \gcc0.gc0.count_d1_reg[4] ;
input \gcc0.gc0.count_d1_reg[6] ;
input \gcc0.gc0.count_d1_reg[8] ;
input \gc0.count_d1_reg[10] ;
input [4:0]v1_reg;
input \gc0.count_reg[10] ;
input clk;
input [0:0]AR;
input rd_en;
input wr_en;
input ram_full_fb_i_reg;
wire [0:0]AR;
wire [0:0]E;
wire c1_n_0;
wire clk;
wire comp1;
wire \gc0.count_d1_reg[10] ;
wire \gc0.count_reg[10] ;
wire \gcc0.gc0.count_d1_reg[0] ;
wire \gcc0.gc0.count_d1_reg[2] ;
wire \gcc0.gc0.count_d1_reg[4] ;
wire \gcc0.gc0.count_d1_reg[6] ;
wire \gcc0.gc0.count_d1_reg[8] ;
(* DONT_TOUCH *) wire ram_empty_fb_i;
(* DONT_TOUCH *) wire ram_empty_i;
wire ram_full_fb_i_reg;
wire rd_en;
wire [4:0]v1_reg;
wire wr_en;
assign empty = ram_empty_i;
assign out = ram_empty_fb_i;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_4 c1
(.comp1(comp1),
.\gc0.count_d1_reg[10] (\gc0.count_d1_reg[10] ),
.\gcc0.gc0.count_d1_reg[0] (\gcc0.gc0.count_d1_reg[0] ),
.\gcc0.gc0.count_d1_reg[2] (\gcc0.gc0.count_d1_reg[2] ),
.\gcc0.gc0.count_d1_reg[4] (\gcc0.gc0.count_d1_reg[4] ),
.\gcc0.gc0.count_d1_reg[6] (\gcc0.gc0.count_d1_reg[6] ),
.\gcc0.gc0.count_d1_reg[8] (\gcc0.gc0.count_d1_reg[8] ),
.out(ram_empty_fb_i),
.ram_empty_i_reg(c1_n_0),
.ram_full_fb_i_reg(ram_full_fb_i_reg),
.rd_en(rd_en),
.wr_en(wr_en));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_5 c2
(.comp1(comp1),
.\gc0.count_reg[10] (\gc0.count_reg[10] ),
.v1_reg(v1_reg));
LUT2 #(
.INIT(4'h2))
\gc0.count_d1[10]_i_1
(.I0(rd_en),
.I1(ram_empty_fb_i),
.O(E));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
ram_empty_fb_i_reg
(.C(clk),
.CE(1'b1),
.D(c1_n_0),
.PRE(AR),
.Q(ram_empty_fb_i));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
ram_empty_i_reg
(.C(clk),
.CE(1'b1),
.D(c1_n_0),
.PRE(AR),
.Q(ram_empty_i));
endmodule
|
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_reset_blk_ramfifo
(out,
\gc0.count_reg[1] ,
\grstd1.grst_full.grst_f.rst_d3_reg_0 ,
wr_rst_busy,
tmp_ram_rd_en,
clk,
rst,
ram_empty_fb_i_reg,
rd_en);
output [0:0]out;
output [1:0]\gc0.count_reg[1] ;
output \grstd1.grst_full.grst_f.rst_d3_reg_0 ;
output wr_rst_busy;
output tmp_ram_rd_en;
input clk;
input rst;
input ram_empty_fb_i_reg;
input rd_en;
wire clk;
wire \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].rrst_inst_n_1 ;
wire \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].wrst_inst_n_1 ;
wire \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_0 ;
wire \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_0 ;
wire p_7_out;
wire p_8_out;
wire ram_empty_fb_i_reg;
wire rd_en;
wire rd_rst_asreg;
(* DONT_TOUCH *) wire [2:0]rd_rst_reg;
wire rst;
(* async_reg = "true" *) (* msgon = "true" *) wire rst_d1;
(* async_reg = "true" *) (* msgon = "true" *) wire rst_d2;
(* async_reg = "true" *) (* msgon = "true" *) wire rst_d3;
(* async_reg = "true" *) (* msgon = "true" *) wire rst_rd_reg1;
(* async_reg = "true" *) (* msgon = "true" *) wire rst_rd_reg2;
(* async_reg = "true" *) (* msgon = "true" *) wire rst_wr_reg1;
(* async_reg = "true" *) (* msgon = "true" *) wire rst_wr_reg2;
wire tmp_ram_rd_en;
wire wr_rst_asreg;
(* DONT_TOUCH *) wire [2:0]wr_rst_reg;
assign \gc0.count_reg[1] [1] = rd_rst_reg[2];
assign \gc0.count_reg[1] [0] = rd_rst_reg[0];
assign \grstd1.grst_full.grst_f.rst_d3_reg_0 = rst_d2;
assign out[0] = wr_rst_reg[1];
assign wr_rst_busy = rst_d3;
LUT3 #(
.INIT(8'hBA))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_2
(.I0(rd_rst_reg[0]),
.I1(ram_empty_fb_i_reg),
.I2(rd_en),
.O(tmp_ram_rd_en));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDPE #(
.INIT(1'b1))
\grstd1.grst_full.grst_f.rst_d1_reg
(.C(clk),
.CE(1'b1),
.D(1'b0),
.PRE(rst_wr_reg2),
.Q(rst_d1));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDPE #(
.INIT(1'b1))
\grstd1.grst_full.grst_f.rst_d2_reg
(.C(clk),
.CE(1'b1),
.D(rst_d1),
.PRE(rst_wr_reg2),
.Q(rst_d2));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDPE #(
.INIT(1'b1))
\grstd1.grst_full.grst_f.rst_d3_reg
(.C(clk),
.CE(1'b1),
.D(rst_d2),
.PRE(rst_wr_reg2),
.Q(rst_d3));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].rrst_inst
(.clk(clk),
.in0(rd_rst_asreg),
.\ngwrdrst.grst.g7serrst.rd_rst_asreg_reg (\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].rrst_inst_n_1 ),
.out(p_7_out));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_0 \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].wrst_inst
(.clk(clk),
.in0(wr_rst_asreg),
.\ngwrdrst.grst.g7serrst.wr_rst_asreg_reg (\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].wrst_inst_n_1 ),
.out(p_8_out));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_1 \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst
(.AS(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_0 ),
.clk(clk),
.in0(rd_rst_asreg),
.out(p_7_out));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_2 \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst
(.AS(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_0 ),
.clk(clk),
.in0(wr_rst_asreg),
.out(p_8_out));
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.rd_rst_asreg_reg
(.C(clk),
.CE(1'b1),
.D(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].rrst_inst_n_1 ),
.PRE(rst_rd_reg2),
.Q(rd_rst_asreg));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]
(.C(clk),
.CE(1'b1),
.D(1'b0),
.PRE(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_0 ),
.Q(rd_rst_reg[0]));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]
(.C(clk),
.CE(1'b1),
.D(1'b0),
.PRE(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_0 ),
.Q(rd_rst_reg[1]));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]
(.C(clk),
.CE(1'b1),
.D(1'b0),
.PRE(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_0 ),
.Q(rd_rst_reg[2]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDPE #(
.INIT(1'b0))
\ngwrdrst.grst.g7serrst.rst_rd_reg1_reg
(.C(clk),
.CE(1'b1),
.D(1'b0),
.PRE(rst),
.Q(rst_rd_reg1));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDPE #(
.INIT(1'b0))
\ngwrdrst.grst.g7serrst.rst_rd_reg2_reg
(.C(clk),
.CE(1'b1),
.D(rst_rd_reg1),
.PRE(rst),
.Q(rst_rd_reg2));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDPE #(
.INIT(1'b0))
\ngwrdrst.grst.g7serrst.rst_wr_reg1_reg
(.C(clk),
.CE(1'b1),
.D(1'b0),
.PRE(rst),
.Q(rst_wr_reg1));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDPE #(
.INIT(1'b0))
\ngwrdrst.grst.g7serrst.rst_wr_reg2_reg
(.C(clk),
.CE(1'b1),
.D(rst_wr_reg1),
.PRE(rst),
.Q(rst_wr_reg2));
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.wr_rst_asreg_reg
(.C(clk),
.CE(1'b1),
.D(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].wrst_inst_n_1 ),
.PRE(rst_wr_reg2),
.Q(wr_rst_asreg));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]
(.C(clk),
.CE(1'b1),
.D(1'b0),
.PRE(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_0 ),
.Q(wr_rst_reg[0]));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]
(.C(clk),
.CE(1'b1),
.D(1'b0),
.PRE(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_0 ),
.Q(wr_rst_reg[1]));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]
(.C(clk),
.CE(1'b1),
.D(1'b0),
.PRE(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_0 ),
.Q(wr_rst_reg[2]));
endmodule
|
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff
(out,
\ngwrdrst.grst.g7serrst.rd_rst_asreg_reg ,
in0,
clk);
output out;
output \ngwrdrst.grst.g7serrst.rd_rst_asreg_reg ;
input [0:0]in0;
input clk;
(* async_reg = "true" *) (* msgon = "true" *) wire Q_reg;
wire clk;
wire [0:0]in0;
wire \ngwrdrst.grst.g7serrst.rd_rst_asreg_reg ;
assign out = Q_reg;
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDRE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(clk),
.CE(1'b1),
.D(in0),
.Q(Q_reg),
.R(1'b0));
LUT2 #(
.INIT(4'h2))
\ngwrdrst.grst.g7serrst.rd_rst_asreg_i_1
(.I0(in0),
.I1(Q_reg),
.O(\ngwrdrst.grst.g7serrst.rd_rst_asreg_reg ));
endmodule
|
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_0
(out,
\ngwrdrst.grst.g7serrst.wr_rst_asreg_reg ,
in0,
clk);
output out;
output \ngwrdrst.grst.g7serrst.wr_rst_asreg_reg ;
input [0:0]in0;
input clk;
(* async_reg = "true" *) (* msgon = "true" *) wire Q_reg;
wire clk;
wire [0:0]in0;
wire \ngwrdrst.grst.g7serrst.wr_rst_asreg_reg ;
assign out = Q_reg;
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDRE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(clk),
.CE(1'b1),
.D(in0),
.Q(Q_reg),
.R(1'b0));
LUT2 #(
.INIT(4'h2))
\ngwrdrst.grst.g7serrst.wr_rst_asreg_i_1
(.I0(in0),
.I1(Q_reg),
.O(\ngwrdrst.grst.g7serrst.wr_rst_asreg_reg ));
endmodule
|
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_1
(AS,
out,
clk,
in0);
output [0:0]AS;
input out;
input clk;
input [0:0]in0;
wire [0:0]AS;
(* async_reg = "true" *) (* msgon = "true" *) wire Q_reg;
wire clk;
wire [0:0]in0;
wire out;
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDRE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(clk),
.CE(1'b1),
.D(out),
.Q(Q_reg),
.R(1'b0));
LUT2 #(
.INIT(4'h2))
\ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1
(.I0(in0),
.I1(Q_reg),
.O(AS));
endmodule
|
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_2
(AS,
out,
clk,
in0);
output [0:0]AS;
input out;
input clk;
input [0:0]in0;
wire [0:0]AS;
(* async_reg = "true" *) (* msgon = "true" *) wire Q_reg;
wire clk;
wire [0:0]in0;
wire out;
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDRE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(clk),
.CE(1'b1),
.D(out),
.Q(Q_reg),
.R(1'b0));
LUT2 #(
.INIT(4'h2))
\ngwrdrst.grst.g7serrst.wr_rst_reg[2]_i_1
(.I0(in0),
.I1(Q_reg),
.O(AS));
endmodule
|
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_bin_cntr
(Q,
v1_reg_0,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram ,
v1_reg,
v1_reg_1,
ram_empty_i_reg,
ram_empty_i_reg_0,
ram_empty_i_reg_1,
ram_empty_i_reg_2,
ram_empty_i_reg_3,
\gc0.count_d1_reg[9] ,
\gc0.count_reg[9] ,
E,
clk,
AR);
output [0:0]Q;
output [4:0]v1_reg_0;
output [10:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram ;
output [4:0]v1_reg;
output [4:0]v1_reg_1;
output ram_empty_i_reg;
output ram_empty_i_reg_0;
output ram_empty_i_reg_1;
output ram_empty_i_reg_2;
output ram_empty_i_reg_3;
input [9:0]\gc0.count_d1_reg[9] ;
input [9:0]\gc0.count_reg[9] ;
input [0:0]E;
input clk;
input [0:0]AR;
wire [0:0]AR;
wire [10:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram ;
wire [0:0]E;
wire [0:0]Q;
wire clk;
wire [9:0]\gc0.count_d1_reg[9] ;
wire [9:0]\gc0.count_reg[9] ;
wire \gcc0.gc0.count[10]_i_2_n_0 ;
wire [9:0]p_12_out;
wire [10:0]plusOp__0;
wire ram_empty_i_reg;
wire ram_empty_i_reg_0;
wire ram_empty_i_reg_1;
wire ram_empty_i_reg_2;
wire ram_empty_i_reg_3;
wire [4:0]v1_reg;
wire [4:0]v1_reg_0;
wire [4:0]v1_reg_1;
LUT1 #(
.INIT(2'h1))
\gcc0.gc0.count[0]_i_1
(.I0(p_12_out[0]),
.O(plusOp__0[0]));
LUT6 #(
.INIT(64'h7FFFFFFF80000000))
\gcc0.gc0.count[10]_i_1
(.I0(p_12_out[8]),
.I1(p_12_out[6]),
.I2(\gcc0.gc0.count[10]_i_2_n_0 ),
.I3(p_12_out[7]),
.I4(p_12_out[9]),
.I5(Q),
.O(plusOp__0[10]));
LUT6 #(
.INIT(64'h8000000000000000))
\gcc0.gc0.count[10]_i_2
(.I0(p_12_out[5]),
.I1(p_12_out[3]),
.I2(p_12_out[1]),
.I3(p_12_out[0]),
.I4(p_12_out[2]),
.I5(p_12_out[4]),
.O(\gcc0.gc0.count[10]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT2 #(
.INIT(4'h6))
\gcc0.gc0.count[1]_i_1
(.I0(p_12_out[0]),
.I1(p_12_out[1]),
.O(plusOp__0[1]));
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT3 #(
.INIT(8'h78))
\gcc0.gc0.count[2]_i_1
(.I0(p_12_out[0]),
.I1(p_12_out[1]),
.I2(p_12_out[2]),
.O(plusOp__0[2]));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT4 #(
.INIT(16'h7F80))
\gcc0.gc0.count[3]_i_1
(.I0(p_12_out[1]),
.I1(p_12_out[0]),
.I2(p_12_out[2]),
.I3(p_12_out[3]),
.O(plusOp__0[3]));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT5 #(
.INIT(32'h7FFF8000))
\gcc0.gc0.count[4]_i_1
(.I0(p_12_out[2]),
.I1(p_12_out[0]),
.I2(p_12_out[1]),
.I3(p_12_out[3]),
.I4(p_12_out[4]),
.O(plusOp__0[4]));
LUT6 #(
.INIT(64'h7FFFFFFF80000000))
\gcc0.gc0.count[5]_i_1
(.I0(p_12_out[3]),
.I1(p_12_out[1]),
.I2(p_12_out[0]),
.I3(p_12_out[2]),
.I4(p_12_out[4]),
.I5(p_12_out[5]),
.O(plusOp__0[5]));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT2 #(
.INIT(4'h6))
\gcc0.gc0.count[6]_i_1
(.I0(\gcc0.gc0.count[10]_i_2_n_0 ),
.I1(p_12_out[6]),
.O(plusOp__0[6]));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT3 #(
.INIT(8'h78))
\gcc0.gc0.count[7]_i_1
(.I0(\gcc0.gc0.count[10]_i_2_n_0 ),
.I1(p_12_out[6]),
.I2(p_12_out[7]),
.O(plusOp__0[7]));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT4 #(
.INIT(16'h7F80))
\gcc0.gc0.count[8]_i_1
(.I0(p_12_out[6]),
.I1(\gcc0.gc0.count[10]_i_2_n_0 ),
.I2(p_12_out[7]),
.I3(p_12_out[8]),
.O(plusOp__0[8]));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT5 #(
.INIT(32'h7FFF8000))
\gcc0.gc0.count[9]_i_1
(.I0(p_12_out[7]),
.I1(\gcc0.gc0.count[10]_i_2_n_0 ),
.I2(p_12_out[6]),
.I3(p_12_out[8]),
.I4(p_12_out[9]),
.O(plusOp__0[9]));
FDCE #(
.INIT(1'b0))
\gcc0.gc0.count_d1_reg[0]
(.C(clk),
.CE(E),
.CLR(AR),
.D(p_12_out[0]),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [0]));
FDCE #(
.INIT(1'b0))
\gcc0.gc0.count_d1_reg[10]
(.C(clk),
.CE(E),
.CLR(AR),
.D(Q),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [10]));
FDCE #(
.INIT(1'b0))
\gcc0.gc0.count_d1_reg[1]
(.C(clk),
.CE(E),
.CLR(AR),
.D(p_12_out[1]),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [1]));
FDCE #(
.INIT(1'b0))
\gcc0.gc0.count_d1_reg[2]
(.C(clk),
.CE(E),
.CLR(AR),
.D(p_12_out[2]),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [2]));
FDCE #(
.INIT(1'b0))
\gcc0.gc0.count_d1_reg[3]
(.C(clk),
.CE(E),
.CLR(AR),
.D(p_12_out[3]),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [3]));
FDCE #(
.INIT(1'b0))
\gcc0.gc0.count_d1_reg[4]
(.C(clk),
.CE(E),
.CLR(AR),
.D(p_12_out[4]),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [4]));
FDCE #(
.INIT(1'b0))
\gcc0.gc0.count_d1_reg[5]
(.C(clk),
.CE(E),
.CLR(AR),
.D(p_12_out[5]),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [5]));
FDCE #(
.INIT(1'b0))
\gcc0.gc0.count_d1_reg[6]
(.C(clk),
.CE(E),
.CLR(AR),
.D(p_12_out[6]),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [6]));
FDCE #(
.INIT(1'b0))
\gcc0.gc0.count_d1_reg[7]
(.C(clk),
.CE(E),
.CLR(AR),
.D(p_12_out[7]),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [7]));
FDCE #(
.INIT(1'b0))
\gcc0.gc0.count_d1_reg[8]
(.C(clk),
.CE(E),
.CLR(AR),
.D(p_12_out[8]),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [8]));
FDCE #(
.INIT(1'b0))
\gcc0.gc0.count_d1_reg[9]
(.C(clk),
.CE(E),
.CLR(AR),
.D(p_12_out[9]),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [9]));
FDPE #(
.INIT(1'b1))
\gcc0.gc0.count_reg[0]
(.C(clk),
.CE(E),
.D(plusOp__0[0]),
.PRE(AR),
.Q(p_12_out[0]));
FDCE #(
.INIT(1'b0))
\gcc0.gc0.count_reg[10]
(.C(clk),
.CE(E),
.CLR(AR),
.D(plusOp__0[10]),
.Q(Q));
FDCE #(
.INIT(1'b0))
\gcc0.gc0.count_reg[1]
(.C(clk),
.CE(E),
.CLR(AR),
.D(plusOp__0[1]),
.Q(p_12_out[1]));
FDCE #(
.INIT(1'b0))
\gcc0.gc0.count_reg[2]
(.C(clk),
.CE(E),
.CLR(AR),
.D(plusOp__0[2]),
.Q(p_12_out[2]));
FDCE #(
.INIT(1'b0))
\gcc0.gc0.count_reg[3]
(.C(clk),
.CE(E),
.CLR(AR),
.D(plusOp__0[3]),
.Q(p_12_out[3]));
FDCE #(
.INIT(1'b0))
\gcc0.gc0.count_reg[4]
(.C(clk),
.CE(E),
.CLR(AR),
.D(plusOp__0[4]),
.Q(p_12_out[4]));
FDCE #(
.INIT(1'b0))
\gcc0.gc0.count_reg[5]
(.C(clk),
.CE(E),
.CLR(AR),
.D(plusOp__0[5]),
.Q(p_12_out[5]));
FDCE #(
.INIT(1'b0))
\gcc0.gc0.count_reg[6]
(.C(clk),
.CE(E),
.CLR(AR),
.D(plusOp__0[6]),
.Q(p_12_out[6]));
FDCE #(
.INIT(1'b0))
\gcc0.gc0.count_reg[7]
(.C(clk),
.CE(E),
.CLR(AR),
.D(plusOp__0[7]),
.Q(p_12_out[7]));
FDCE #(
.INIT(1'b0))
\gcc0.gc0.count_reg[8]
(.C(clk),
.CE(E),
.CLR(AR),
.D(plusOp__0[8]),
.Q(p_12_out[8]));
FDCE #(
.INIT(1'b0))
\gcc0.gc0.count_reg[9]
(.C(clk),
.CE(E),
.CLR(AR),
.D(plusOp__0[9]),
.Q(p_12_out[9]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[0].gm1.m1_i_1
(.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [0]),
.I1(\gc0.count_d1_reg[9] [0]),
.I2(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [1]),
.I3(\gc0.count_d1_reg[9] [1]),
.O(v1_reg_0[0]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[0].gm1.m1_i_1__0
(.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [0]),
.I1(\gc0.count_reg[9] [0]),
.I2(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [1]),
.I3(\gc0.count_reg[9] [1]),
.O(v1_reg[0]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[0].gm1.m1_i_1__1
(.I0(p_12_out[0]),
.I1(\gc0.count_d1_reg[9] [0]),
.I2(p_12_out[1]),
.I3(\gc0.count_d1_reg[9] [1]),
.O(v1_reg_1[0]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[0].gm1.m1_i_1__2
(.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [0]),
.I1(\gc0.count_d1_reg[9] [0]),
.I2(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [1]),
.I3(\gc0.count_d1_reg[9] [1]),
.O(ram_empty_i_reg));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[1].gms.ms_i_1
(.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [2]),
.I1(\gc0.count_d1_reg[9] [2]),
.I2(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [3]),
.I3(\gc0.count_d1_reg[9] [3]),
.O(v1_reg_0[1]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[1].gms.ms_i_1__0
(.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [2]),
.I1(\gc0.count_reg[9] [2]),
.I2(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [3]),
.I3(\gc0.count_reg[9] [3]),
.O(v1_reg[1]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[1].gms.ms_i_1__1
(.I0(p_12_out[2]),
.I1(\gc0.count_d1_reg[9] [2]),
.I2(p_12_out[3]),
.I3(\gc0.count_d1_reg[9] [3]),
.O(v1_reg_1[1]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[1].gms.ms_i_1__2
(.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [2]),
.I1(\gc0.count_d1_reg[9] [2]),
.I2(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [3]),
.I3(\gc0.count_d1_reg[9] [3]),
.O(ram_empty_i_reg_0));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[2].gms.ms_i_1
(.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [4]),
.I1(\gc0.count_d1_reg[9] [4]),
.I2(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [5]),
.I3(\gc0.count_d1_reg[9] [5]),
.O(v1_reg_0[2]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[2].gms.ms_i_1__0
(.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [4]),
.I1(\gc0.count_reg[9] [4]),
.I2(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [5]),
.I3(\gc0.count_reg[9] [5]),
.O(v1_reg[2]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[2].gms.ms_i_1__1
(.I0(p_12_out[4]),
.I1(\gc0.count_d1_reg[9] [4]),
.I2(p_12_out[5]),
.I3(\gc0.count_d1_reg[9] [5]),
.O(v1_reg_1[2]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[2].gms.ms_i_1__2
(.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [4]),
.I1(\gc0.count_d1_reg[9] [4]),
.I2(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [5]),
.I3(\gc0.count_d1_reg[9] [5]),
.O(ram_empty_i_reg_1));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[3].gms.ms_i_1
(.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [6]),
.I1(\gc0.count_d1_reg[9] [6]),
.I2(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [7]),
.I3(\gc0.count_d1_reg[9] [7]),
.O(v1_reg_0[3]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[3].gms.ms_i_1__0
(.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [6]),
.I1(\gc0.count_reg[9] [6]),
.I2(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [7]),
.I3(\gc0.count_reg[9] [7]),
.O(v1_reg[3]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[3].gms.ms_i_1__1
(.I0(p_12_out[6]),
.I1(\gc0.count_d1_reg[9] [6]),
.I2(p_12_out[7]),
.I3(\gc0.count_d1_reg[9] [7]),
.O(v1_reg_1[3]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[3].gms.ms_i_1__2
(.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [6]),
.I1(\gc0.count_d1_reg[9] [6]),
.I2(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [7]),
.I3(\gc0.count_d1_reg[9] [7]),
.O(ram_empty_i_reg_2));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[4].gms.ms_i_1
(.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [8]),
.I1(\gc0.count_d1_reg[9] [8]),
.I2(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [9]),
.I3(\gc0.count_d1_reg[9] [9]),
.O(v1_reg_0[4]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[4].gms.ms_i_1__0
(.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [8]),
.I1(\gc0.count_reg[9] [8]),
.I2(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [9]),
.I3(\gc0.count_reg[9] [9]),
.O(v1_reg[4]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[4].gms.ms_i_1__1
(.I0(p_12_out[8]),
.I1(\gc0.count_d1_reg[9] [8]),
.I2(p_12_out[9]),
.I3(\gc0.count_d1_reg[9] [9]),
.O(v1_reg_1[4]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[4].gms.ms_i_1__2
(.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [8]),
.I1(\gc0.count_d1_reg[9] [8]),
.I2(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [9]),
.I3(\gc0.count_d1_reg[9] [9]),
.O(ram_empty_i_reg_3));
endmodule
|
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_logic
(out,
full,
\gcc0.gc0.count_d1_reg[10] ,
Q,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram ,
v1_reg,
ram_empty_i_reg,
ram_empty_i_reg_0,
ram_empty_i_reg_1,
ram_empty_i_reg_2,
ram_empty_i_reg_3,
\gc0.count_d1_reg[10] ,
\gc0.count_d1_reg[10]_0 ,
clk,
\grstd1.grst_full.grst_f.rst_d2_reg ,
wr_en,
\gc0.count_d1_reg[9] ,
\gc0.count_reg[9] ,
wr_rst_busy,
E,
AR);
output out;
output full;
output \gcc0.gc0.count_d1_reg[10] ;
output [0:0]Q;
output [10:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram ;
output [4:0]v1_reg;
output ram_empty_i_reg;
output ram_empty_i_reg_0;
output ram_empty_i_reg_1;
output ram_empty_i_reg_2;
output ram_empty_i_reg_3;
input \gc0.count_d1_reg[10] ;
input \gc0.count_d1_reg[10]_0 ;
input clk;
input \grstd1.grst_full.grst_f.rst_d2_reg ;
input wr_en;
input [9:0]\gc0.count_d1_reg[9] ;
input [9:0]\gc0.count_reg[9] ;
input wr_rst_busy;
input [0:0]E;
input [0:0]AR;
wire [0:0]AR;
wire [10:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram ;
wire [0:0]E;
wire [0:0]Q;
wire [4:0]\c0/v1_reg ;
wire [4:0]\c1/v1_reg ;
wire clk;
wire full;
wire \gc0.count_d1_reg[10] ;
wire \gc0.count_d1_reg[10]_0 ;
wire [9:0]\gc0.count_d1_reg[9] ;
wire [9:0]\gc0.count_reg[9] ;
wire \gcc0.gc0.count_d1_reg[10] ;
wire \grstd1.grst_full.grst_f.rst_d2_reg ;
wire out;
wire ram_empty_i_reg;
wire ram_empty_i_reg_0;
wire ram_empty_i_reg_1;
wire ram_empty_i_reg_2;
wire ram_empty_i_reg_3;
wire [4:0]v1_reg;
wire wr_en;
wire wr_rst_busy;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_status_flags_ss \gwss.wsts
(.E(\gcc0.gc0.count_d1_reg[10] ),
.clk(clk),
.full(full),
.\gc0.count_d1_reg[10] (\gc0.count_d1_reg[10] ),
.\gc0.count_d1_reg[10]_0 (\gc0.count_d1_reg[10]_0 ),
.\grstd1.grst_full.grst_f.rst_d2_reg (\grstd1.grst_full.grst_f.rst_d2_reg ),
.out(out),
.ram_empty_fb_i_reg(E),
.v1_reg(\c0/v1_reg ),
.v1_reg_0(\c1/v1_reg ),
.wr_en(wr_en),
.wr_rst_busy(wr_rst_busy));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_bin_cntr wpntr
(.AR(AR),
.\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram (\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram ),
.E(\gcc0.gc0.count_d1_reg[10] ),
.Q(Q),
.clk(clk),
.\gc0.count_d1_reg[9] (\gc0.count_d1_reg[9] ),
.\gc0.count_reg[9] (\gc0.count_reg[9] ),
.ram_empty_i_reg(ram_empty_i_reg),
.ram_empty_i_reg_0(ram_empty_i_reg_0),
.ram_empty_i_reg_1(ram_empty_i_reg_1),
.ram_empty_i_reg_2(ram_empty_i_reg_2),
.ram_empty_i_reg_3(ram_empty_i_reg_3),
.v1_reg(v1_reg),
.v1_reg_0(\c0/v1_reg ),
.v1_reg_1(\c1/v1_reg ));
endmodule
|
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_status_flags_ss
(out,
full,
E,
v1_reg,
\gc0.count_d1_reg[10] ,
v1_reg_0,
\gc0.count_d1_reg[10]_0 ,
clk,
\grstd1.grst_full.grst_f.rst_d2_reg ,
wr_en,
wr_rst_busy,
ram_empty_fb_i_reg);
output out;
output full;
output [0:0]E;
input [4:0]v1_reg;
input \gc0.count_d1_reg[10] ;
input [4:0]v1_reg_0;
input \gc0.count_d1_reg[10]_0 ;
input clk;
input \grstd1.grst_full.grst_f.rst_d2_reg ;
input wr_en;
input wr_rst_busy;
input [0:0]ram_empty_fb_i_reg;
wire [0:0]E;
wire clk;
wire comp1;
wire \gc0.count_d1_reg[10] ;
wire \gc0.count_d1_reg[10]_0 ;
wire \grstd1.grst_full.grst_f.rst_d2_reg ;
(* DONT_TOUCH *) wire ram_afull_fb;
(* DONT_TOUCH *) wire ram_afull_i;
wire [0:0]ram_empty_fb_i_reg;
wire ram_full_comb;
(* DONT_TOUCH *) wire ram_full_fb_i;
(* DONT_TOUCH *) wire ram_full_i;
wire [4:0]v1_reg;
wire [4:0]v1_reg_0;
wire wr_en;
wire wr_rst_busy;
assign full = ram_full_i;
assign out = ram_full_fb_i;
LUT2 #(
.INIT(4'h2))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_1
(.I0(wr_en),
.I1(ram_full_fb_i),
.O(E));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare c0
(.comp1(comp1),
.\gc0.count_d1_reg[10] (\gc0.count_d1_reg[10] ),
.out(ram_full_fb_i),
.ram_empty_fb_i_reg(ram_empty_fb_i_reg),
.ram_full_comb(ram_full_comb),
.v1_reg(v1_reg),
.wr_en(wr_en),
.wr_rst_busy(wr_rst_busy));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_3 c1
(.comp1(comp1),
.\gc0.count_d1_reg[10] (\gc0.count_d1_reg[10]_0 ),
.v1_reg_0(v1_reg_0));
LUT1 #(
.INIT(2'h2))
i_0
(.I0(1'b1),
.O(ram_afull_i));
LUT1 #(
.INIT(2'h2))
i_1
(.I0(1'b1),
.O(ram_afull_fb));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
ram_full_fb_i_reg
(.C(clk),
.CE(1'b1),
.D(ram_full_comb),
.PRE(\grstd1.grst_full.grst_f.rst_d2_reg ),
.Q(ram_full_fb_i));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
ram_full_i_reg
(.C(clk),
.CE(1'b1),
.D(ram_full_comb),
.PRE(\grstd1.grst_full.grst_f.rst_d2_reg ),
.Q(ram_full_i));
endmodule
|
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
|
module sky130_fd_sc_hdll__nand4b_4 (
Y ,
A_N ,
B ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A_N ;
input B ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__nand4b base (
.Y(Y),
.A_N(A_N),
.B(B),
.C(C),
.D(D),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
|
module sky130_fd_sc_hdll__nand4b_4 (
Y ,
A_N,
B ,
C ,
D
);
output Y ;
input A_N;
input B ;
input C ;
input D ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__nand4b base (
.Y(Y),
.A_N(A_N),
.B(B),
.C(C),
.D(D)
);
endmodule
|
module pipeline_internal_fv (
// INTERFACE BEGIN
clk, // clock
ena, // clock enable
clr, // async clear
d, // data in
piped // output
);
// INTERFACE END
//// top level parameters ////
parameter data_width = 1;
parameter latency = 1;
//// port declarations ////
// data input ports
input [data_width - 1 : 0] d;
// control signals
input clk,ena,clr;
// output ports
output [data_width - 1 : 0] piped;
wire [data_width-1 : 0] out;
wire [data_width*(latency-1) : 1] t;
wire [data_width*latency-1 : 0] d_w;
assign piped = out;
//// nets/registers ////
// IMPLEMENTATION BEGIN
generate
if(latency==0) begin
assign out = d;
end
else if(latency==1) begin
assign d_w = ena? d : out;
dff_bus #(data_width) p (.q(out), .clk(clk), .d(d_w), .clr(clr));
end
else begin
assign d_w = ena? {t,d} : {out,t};
dff_bus #(data_width) p[1:latency] (.q({out,t}), .clk(clk), .d(d_w), .clr(clr));
end
endgenerate
// IMPLEMENTATION END
endmodule
|
module dff_bus (q, clk, d, clr);
parameter data_width = 1;
input [data_width-1 : 0] d;
input clk, clr;
output [data_width-1 : 0] q;
generate
if(data_width==1) begin
dffep reg_prim_inst (q,clk,1'b1,d,1'b0,clr);
end
else begin
dffep reg_prim_inst[data_width-1:0] (q,clk,1'b1,d,1'b0,clr);
end
endgenerate
endmodule
|
module dpram (clock,
address_a, byteena_a, wrdata_a, wren_a, rddata_a,
address_b, byteena_b, wrdata_b, wren_b, rddata_b);
parameter DATA_WIDTH = 32;
parameter ADDR_WIDTH = 7;
parameter INIT_FILE = "dummy"; // This is ignored right now
input clock;
input [ADDR_WIDTH-1:0] address_a;
input [DATA_WIDTH/8-1:0] byteena_a;
input [DATA_WIDTH-1:0] wrdata_a;
input wren_a;
output [DATA_WIDTH-1:0] rddata_a;
input [ADDR_WIDTH-1:0] address_b;
input [DATA_WIDTH-1:0] wrdata_b;
input [DATA_WIDTH/8-1:0] byteena_b;
input wren_b;
output [DATA_WIDTH-1:0] rddata_b;
dpram_simple s0(clock,
address_a, wrdata_a[ 7: 0], byteena_a[0] & wren_a, rddata_a[ 7: 0],
address_b, wrdata_b[ 7: 0], byteena_b[0] & wren_b, rddata_b[ 7: 0]);
defparam s0.DATA_WIDTH = DATA_WIDTH / 4,
s0.DATA_WIDTH = DATA_WIDTH;
dpram_simple s1(clock,
address_a, wrdata_a[15: 8], byteena_a[1] & wren_a, rddata_a[15: 8],
address_b, wrdata_b[15: 8], byteena_b[1] & wren_b, rddata_b[15: 8]);
defparam s1.DATA_WIDTH = DATA_WIDTH / 4,
s1.DATA_WIDTH = DATA_WIDTH;
dpram_simple s2(clock,
address_a, wrdata_a[23:16], byteena_a[2] & wren_a, rddata_a[23:16],
address_b, wrdata_b[23:16], byteena_b[2] & wren_b, rddata_b[23:16]);
defparam s2.DATA_WIDTH = DATA_WIDTH / 4,
s2.DATA_WIDTH = DATA_WIDTH;
dpram_simple s3(clock,
address_a, wrdata_a[31:24], byteena_a[3] & wren_a, rddata_a[31:24],
address_b, wrdata_b[31:24], byteena_b[3] & wren_b, rddata_b[31:24]);
defparam s3.DATA_WIDTH = DATA_WIDTH / 4,
s3.DATA_WIDTH = DATA_WIDTH;
endmodule
|
module Convierte(
input [3:0]Ver,
output reg [6:0]Salida7seg
);
always @(Ver)begin
case(Ver)
// abc_defg
7'b0000000: Salida7seg=7'b000_0001;//0
7'b0000001: Salida7seg=7'b100_1111;//1
7'b0000010: Salida7seg=7'b001_0010;//2
7'b0000011: Salida7seg=7'b000_0110;//3
7'b0000100: Salida7seg=7'b100_1100;//4
7'b0000101: Salida7seg=7'b010_0100;//5
7'b0000110: Salida7seg=7'b010_0000;//6
7'b0000111: Salida7seg=7'b000_1111;//7
7'b0001000: Salida7seg=7'b000_0000;//8
7'b0001001: Salida7seg=7'b000_0100;//9
7'b0001010: Salida7seg=7'b000_1000;//A
7'b0001011: Salida7seg=7'b110_0000;//b
7'b0001100: Salida7seg=7'b011_0001;//C
7'b0001101: Salida7seg=7'b100_0010;//d
7'b0001110: Salida7seg=7'b011_0000;//E
7'b0001111: Salida7seg=7'b011_1000;//F
/*
8'h15: Salida7seg=7'b000_1100;//q
8'h1D: Salida7seg=7'b100_0000;//w
8'h24: Salida7seg=7'b011_0000;//E
8'h2D: Salida7seg=7'b111_1010;//r
8'h2C: Salida7seg=7'b111_0000;//t
8'h35: Salida7seg=7'b100_0100;//Y
8'h3C: Salida7seg=7'b110_0011;//u
8'h43: Salida7seg=7'b100_1111;//i
8'h44: Salida7seg=7'b110_0010;//O
8'h4D: Salida7seg=7'b001_1000;//P
8'h1C: Salida7seg=7'b000_1000;//A
8'h1B: Salida7seg=7'b010_0100;//S
8'h23: Salida7seg=7'b100_0010;//d
8'h2B: Salida7seg=7'b011_1000;//F
8'h34: Salida7seg=7'b010_0001;//G
8'h33: Salida7seg=7'b110_1000;//h
8'h3B: Salida7seg=7'b100_0011;//J
8'h42: Salida7seg=7'b010_1000;//K
8'h4B: Salida7seg=7'b111_0000;//L
8'h4C: Salida7seg=7'b010_1010;//ñ
8'h1A: Salida7seg=7'b001_0011;//Z
8'h22: Salida7seg=7'b100_1000;//X
8'h21: Salida7seg=7'b111_0010;//C
8'h2A: Salida7seg=7'b100_0001;//V
8'h32: Salida7seg=7'b110_0000;//b
8'h31: Salida7seg=7'b110_1010;//n
8'h3A: Salida7seg=7'b000_1001;//M
*/
default : Salida7seg=7'b000_0001;//0
endcase
end
endmodule
|
module sky130_fd_sc_hs__a311o (
X ,
A1 ,
A2 ,
A3 ,
B1 ,
C1 ,
VPWR,
VGND
);
// Module ports
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
// Local signals
wire B1 and0_out ;
wire or0_out_X ;
wire u_vpwr_vgnd0_out_X;
// Name Output Other arguments
and and0 (and0_out , A3, A1, A2 );
or or0 (or0_out_X , and0_out, C1, B1 );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_X, or0_out_X, VPWR, VGND);
buf buf0 (X , u_vpwr_vgnd0_out_X );
endmodule
|
module or1200_sb_fifo(
clk_i, rst_i, dat_i, wr_i, rd_i, dat_o, full_o, empty_o
);
parameter dw = 68;
parameter fw = `OR1200_SB_LOG;
parameter fl = `OR1200_SB_ENTRIES;
//
// FIFO signals
//
input clk_i; // Clock
input rst_i; // Reset
input [dw-1:0] dat_i; // Input data bus
input wr_i; // Write request
input rd_i; // Read request
output [dw-1:0] dat_o; // Output data bus
output full_o; // FIFO full
output empty_o;// FIFO empty
//
// Internal regs
//
reg [dw-1:0] mem [fl-1:0];
reg [dw-1:0] dat_o;
reg [fw+1:0] cntr;
reg [fw-1:0] wr_pntr;
reg [fw-1:0] rd_pntr;
reg empty_o;
reg full_o;
always @(posedge clk_i or posedge rst_i)
if (rst_i) begin
full_o <= #1 1'b0;
empty_o <= #1 1'b1;
wr_pntr <= #1 {fw{1'b0}};
rd_pntr <= #1 {fw{1'b0}};
cntr <= #1 {fw+2{1'b0}};
dat_o <= #1 {dw{1'b0}};
end
else if (wr_i && rd_i) begin // FIFO Read and Write
mem[wr_pntr] <= #1 dat_i;
if (wr_pntr >= fl-1)
wr_pntr <= #1 {fw{1'b0}};
else
wr_pntr <= #1 wr_pntr + 1'b1;
if (empty_o) begin
dat_o <= #1 dat_i;
end
else begin
dat_o <= #1 mem[rd_pntr];
end
if (rd_pntr >= fl-1)
rd_pntr <= #1 {fw{1'b0}};
else
rd_pntr <= #1 rd_pntr + 1'b1;
end
else if (wr_i && !full_o) begin // FIFO Write
mem[wr_pntr] <= #1 dat_i;
cntr <= #1 cntr + 1'b1;
empty_o <= #1 1'b0;
if (cntr >= (fl-1)) begin
full_o <= #1 1'b1;
cntr <= #1 fl;
end
if (wr_pntr >= fl-1)
wr_pntr <= #1 {fw{1'b0}};
else
wr_pntr <= #1 wr_pntr + 1'b1;
end
else if (rd_i && !empty_o) begin // FIFO Read
dat_o <= #1 mem[rd_pntr];
cntr <= #1 cntr - 1'b1;
full_o <= #1 1'b0;
if (cntr <= 1) begin
empty_o <= #1 1'b1;
cntr <= #1 {fw+2{1'b0}};
end
if (rd_pntr >= fl-1)
rd_pntr <= #1 {fw{1'b0}};
else
rd_pntr <= #1 rd_pntr + 1'b1;
end
endmodule
|
module controllerHdl_Inverse_Clarke_Transform
(
alpha_voltage,
beta_voltage,
phase_voltages_0,
phase_voltages_1,
phase_voltages_2
);
input signed [17:0] alpha_voltage; // sfix18_En10
input signed [17:0] beta_voltage; // sfix18_En10
output signed [17:0] phase_voltages_0; // sfix18_En13
output signed [17:0] phase_voltages_1; // sfix18_En13
output signed [17:0] phase_voltages_2; // sfix18_En13
wire signed [35:0] voltage_phase_a; // sfix36_En26
wire signed [35:0] Gain1_out1; // sfix36_En26
wire signed [35:0] Gain_out1; // sfix36_En26
wire signed [35:0] voltage_phase_b; // sfix36_En26
wire signed [37:0] Add1_cast; // sfix38_En26
wire signed [37:0] Add1_cast_1; // sfix38_En26
wire signed [37:0] Add1_sub_cast; // sfix38_En26
wire signed [37:0] Add1_sub_temp; // sfix38_En26
wire signed [35:0] voltage_phase_c; // sfix36_En26
wire signed [35:0] Mux_out1 [0:2]; // sfix36_En26 [3]
wire signed [17:0] Current_Data_Type_out1 [0:2]; // sfix18_En13 [3]
// Inverse Clarke Transform
//
// Converts direct axis (alpha) component and the quadrature axis (beta) component to balanced three-phase quantities
// The alpha and beta components are dependent on time and speed.
// <S39>/Data Type Conversion
assign voltage_phase_a = {{2{alpha_voltage[17]}}, {alpha_voltage, 16'b0000000000000000}};
// <S39>/Gain1
assign Gain1_out1 = 56756 * beta_voltage;
// <S39>/Gain
assign Gain_out1 = {{3{alpha_voltage[17]}}, {alpha_voltage, 15'b000000000000000}};
// <S39>/Add
assign voltage_phase_b = Gain1_out1 - Gain_out1;
// <S39>/Add1
assign Add1_cast = Gain_out1;
assign Add1_cast_1 = - (Add1_cast);
assign Add1_sub_cast = Gain1_out1;
assign Add1_sub_temp = Add1_cast_1 - Add1_sub_cast;
assign voltage_phase_c = Add1_sub_temp[35:0];
// <S39>/Mux
assign Mux_out1[0] = voltage_phase_a;
assign Mux_out1[1] = voltage_phase_b;
assign Mux_out1[2] = voltage_phase_c;
// <S39>/Current_Data_Type
assign Current_Data_Type_out1[0] = ((Mux_out1[0][35] == 1'b0) && (Mux_out1[0][34:30] != 5'b00000) ? 18'sb011111111111111111 :
((Mux_out1[0][35] == 1'b1) && (Mux_out1[0][34:30] != 5'b11111) ? 18'sb100000000000000000 :
$signed(Mux_out1[0][30:13])));
assign Current_Data_Type_out1[1] = ((Mux_out1[1][35] == 1'b0) && (Mux_out1[1][34:30] != 5'b00000) ? 18'sb011111111111111111 :
((Mux_out1[1][35] == 1'b1) && (Mux_out1[1][34:30] != 5'b11111) ? 18'sb100000000000000000 :
$signed(Mux_out1[1][30:13])));
assign Current_Data_Type_out1[2] = ((Mux_out1[2][35] == 1'b0) && (Mux_out1[2][34:30] != 5'b00000) ? 18'sb011111111111111111 :
((Mux_out1[2][35] == 1'b1) && (Mux_out1[2][34:30] != 5'b11111) ? 18'sb100000000000000000 :
$signed(Mux_out1[2][30:13])));
assign phase_voltages_0 = Current_Data_Type_out1[0];
assign phase_voltages_1 = Current_Data_Type_out1[1];
assign phase_voltages_2 = Current_Data_Type_out1[2];
endmodule
|
module sky130_fd_sc_ms__bufbuf (
//# {{data|Data Signals}}
input A ,
output X ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
|
module ADT7310 (
(* intersynth_port="Reset_n_i" *)
input Reset_n_i,
(* intersynth_port="Clk_i" *)
input Clk_i,
(* intersynth_port="ReconfModuleIn_s", intersynth_conntype="Bit" *)
input Enable_i,
(* intersynth_port="ReconfModuleIRQs_s", intersynth_conntype="Bit" *)
output CpuIntr_o,
(* intersynth_port="Outputs_o", intersynth_conntype="Bit" *)
output ADT7310CS_n_o,
(* intersynth_port="SPI_DataOut", intersynth_conntype="Byte" *)
input[7:0] SPI_Data_i,
(* intersynth_port="SPI_Write", intersynth_conntype="Bit" *)
output SPI_Write_o,
(* intersynth_port="SPI_ReadNext", intersynth_conntype="Bit" *)
output SPI_ReadNext_o,
(* intersynth_port="SPI_DataIn", intersynth_conntype="Byte" *)
output[7:0] SPI_Data_o,
(* intersynth_port="SPI_FIFOFull", intersynth_conntype="Bit" *)
input SPI_FIFOFull_i,
(* intersynth_port="SPI_FIFOEmpty", intersynth_conntype="Bit" *)
input SPI_FIFOEmpty_i,
(* intersynth_port="SPI_Transmission", intersynth_conntype="Bit" *)
input SPI_Transmission_i,
(* intersynth_param="SPICounterPresetH_i", intersynth_conntype="Word" *)
input[15:0] SPICounterPresetH_i,
(* intersynth_param="SPICounterPresetL_i", intersynth_conntype="Word" *)
input[15:0] SPICounterPresetL_i,
(* intersynth_param="Threshold_i", intersynth_conntype="Word" *)
input[15:0] Threshold_i,
(* intersynth_param="PeriodCounterPreset_i", intersynth_conntype="Word" *)
input[15:0] PeriodCounterPreset_i,
(* intersynth_param="SensorValue_o", intersynth_conntype="Word" *)
output[15:0] SensorValue_o,
(* intersynth_port="SPI_CPOL", intersynth_conntype="Bit" *)
output SPI_CPOL_o,
(* intersynth_port="SPI_CPHA", intersynth_conntype="Bit" *)
output SPI_CPHA_o,
(* intersynth_port="SPI_LSBFE", intersynth_conntype="Bit" *)
output SPI_LSBFE_o
);
/* constant value for dynamic signal */
assign SPI_CPOL_o = 1'b1;
/* constant value for dynamic signal */
assign SPI_CPHA_o = 1'b1;
/* constant value for dynamic signal */
assign SPI_LSBFE_o = 1'b0;
(* keep *)
wire SPIFSM_Start_s;
(* keep *)
wire SPIFSM_Done_s;
(* keep *)
wire [7:0] SPIFSM_Byte0_s;
(* keep *)
wire [7:0] SPIFSM_Byte1_s;
SPIFSM #(
.SPPRWidth (4),
.SPRWidth (4),
.DataWidth (8)
) SPIFSM_1 (
.Reset_n_i (Reset_n_i),
.Clk_i (Clk_i),
// FSM control
.Start_i (SPIFSM_Start_s),
.Done_o (SPIFSM_Done_s),
.Byte0_o (SPIFSM_Byte0_s),
.Byte1_o (SPIFSM_Byte1_s),
// to/from SPI_Master
.SPI_Transmission_i (SPI_Transmission_i),
.SPI_Write_o (SPI_Write_o),
.SPI_ReadNext_o (SPI_ReadNext_o),
.SPI_Data_o (SPI_Data_o),
.SPI_Data_i (SPI_Data_i),
.SPI_FIFOFull_i (SPI_FIFOFull_i),
.SPI_FIFOEmpty_i (SPI_FIFOEmpty_i),
// to ADT7310
.ADT7310CS_n_o (ADT7310CS_n_o),
// parameters
.ParamCounterPreset_i({SPICounterPresetH_i, SPICounterPresetL_i})
);
SensorFSM #(
.DataWidth (8)
) SensorFSM_1 (
.Reset_n_i (Reset_n_i),
.Clk_i (Clk_i),
.Enable_i (Enable_i),
.CpuIntr_o (CpuIntr_o),
.SensorValue_o (SensorValue_o),
.MeasureFSM_Start_o (SPIFSM_Start_s),
.MeasureFSM_Done_i (SPIFSM_Done_s),
.MeasureFSM_Byte0_i (SPIFSM_Byte0_s),
.MeasureFSM_Byte1_i (SPIFSM_Byte1_s),
// parameters
.ParamThreshold_i (Threshold_i),
.ParamCounterPreset_i(PeriodCounterPreset_i)
);
endmodule
|
module timer(
input CLK_I,
input RST_I,
input [31:2] ADR_I,
input CYC_I,
input STB_I,
input WE_I,
output reg RTY_O,
output reg interrupt_o
);
reg [27:0] counter;
always @(posedge CLK_I) begin
if(RST_I == 1'b1) begin
RTY_O <= 1'b0;
interrupt_o <= 1'b0;
counter <= 28'd0;
end
else if(counter == 28'h00FFFFF) begin
if(ADR_I == { 27'b1111_1111_1111_1111_1111_1111_111, 3'b001 } && CYC_I == 1'b1 && STB_I == 1'b1 && WE_I == 1'b0 && interrupt_o == 1'b1) begin
RTY_O <= 1'b1;
interrupt_o <= 1'b0;
counter <= 28'd0;
end
else begin
interrupt_o <= 1'b1;
end
end
else begin
RTY_O <= 1'b0;
counter <= counter + 28'd1;
end
end
endmodule
|
module server_io(
input wire clk,
input wire rst_n,
///////////////////////////////////// CCI Interface /////////////////////////////////////
// CCI TX read request
input wire cci_tx_rd_almostfull,
output reg spl_tx_rd_valid,
output reg [60:0] spl_tx_rd_hdr,
// CCI TX write request
input wire cci_tx_wr_almostfull,
output reg spl_tx_wr_valid,
output wire spl_tx_intr_valid,
output reg [60:0] spl_tx_wr_hdr,
output reg [511:0] spl_tx_data,
// CCI RX read response
input wire cci_rx_rd_valid,
input wire cci_rx_wr_valid0,
input wire cci_rx_cfg_valid,
input wire cci_rx_intr_valid0,
input wire cci_rx_umsg_valid,
input wire [`CCI_RX_HDR_WIDTH-1:0] cci_rx_hdr0,
input wire [511:0] cci_rx_data,
// CCI RX write response
input wire cci_rx_wr_valid1,
input wire cci_rx_intr_valid1,
input wire [`CCI_RX_HDR_WIDTH-1:0] cci_rx_hdr1,
//////////////////////////////// Server components Interfaces /////////////////////////////
// server_io <--> cmd_server: RX_RD
output reg io_rx_csr_valid,
output reg [13:0] io_rx_csr_addr,
output reg [31:0] io_rx_csr_data,
// server_io <--> cmd_server: TX_WR
output wire fc_tx_wr_ready,
input wire fc_tx_wr_valid,
input wire [31:0] fc_tx_wr_addr,
input wire [`FPGA_CORE_TAG-1:0] fc_tx_wr_tag,
input wire [511:0] fc_tx_data,
// server_io <--> cmd server: TX_RD
output wire fc_tx_rd_ready,
input wire fc_tx_rd_valid,
input wire [31:0] fc_tx_rd_addr,
input wire [`FPGA_CORE_TAG-1:0] fc_tx_rd_tag,
// server_io <--> cmd server: RX_WR
output reg fc_rx_wr_valid,
output reg [`FPGA_CORE_TAG-1:0] fc_rx_wr_tag,
// server_io <--> cmd server: RX_RD
output reg fc_rx_rd_valid,
output reg [`FPGA_CORE_TAG-1:0] fc_rx_rd_tag,
output reg [511:0] fc_rx_data,
// server_io <--> io_requester: TX_WR
output wire rq_tx_wr_ready,
input wire rq_tx_wr_valid,
input wire [48:0] rq_tx_wr_hdr,
input wire [511:0] rq_tx_data,
// server_io <--> io_requester: TX_RD
output wire rq_tx_rd_ready,
input wire rq_tx_rd_valid,
input wire [44:0] rq_tx_rd_hdr,
// server_io <--> arbiter: RX_RD
output reg io_rx_rd_valid,
output reg [511:0] io_rx_data,
output reg [12:0] io_rx_rd_tag,
// server_io <--> arbiter: RX_WR
output reg io_rx_wr_valid,
output reg [12:0] io_rx_wr_tag
);
wire wr_rp_buf_empty;
wire wr_rp_buf_valid;
wire [`CCI_RX_HDR_WIDTH-1:0] wr_rp_buf_hdr;
wire [`CCI_RX_HDR_WIDTH-1:0] wr_rp_hdr;
wire wr_rp_valid;
wire [8:0] wr_rp_buf_count;
wire [3:0] cci_tx_wr_cmd;
wire [31:0] cci_tx_wr_addr;
wire [511:0] cci_tx_data;
wire [13:0] cci_tx_wr_tag;
wire [31:0] cci_tx_rd_addr;
wire [13:0] cci_tx_rd_tag;
wire tx_wr_fifo_valid;
wire [511:0] tx_wr_fifo_data;
wire [60:0] tx_wr_fifo_hdr;
wire tx_wr_fifo_full;
wire [4:0] tx_wr_fifo_count;
wire tx_rd_fifo_valid;
wire [60:0] tx_rd_fifo_hdr;
wire tx_rd_fifo_full;
reg [31:0] idle_read_cycles;
reg [31:0] idle_write_cycles;
reg [31:0] idle_rw_cycles;
//////
always @(posedge clk) begin
if(~rst_n) begin
idle_read_cycles <= 0;
idle_write_cycles <= 0;
idle_rw_cycles <= 0;
end
else begin
if( ~cci_tx_wr_almostfull & ~spl_tx_wr_valid)
idle_write_cycles <= idle_write_cycles + 1'b1;
if( ~cci_tx_rd_almostfull & ~spl_tx_rd_valid)
idle_read_cycles <= idle_read_cycles + 1'b1;
if( ~cci_tx_wr_almostfull & ~spl_tx_wr_valid & ~cci_tx_rd_almostfull & ~spl_tx_rd_valid)
idle_rw_cycles <= idle_rw_cycles + 1'b1;
end
end
///////////////////////////////////////////////////////////////////////////////////////////////////
///////////////////////////////// ///////////////////////////////////////
///////////////////////////// TX WR Driver ////////////////////////////////////
///////////////////////////////// ///////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////////////////////////
// TW WR is used by cmd server and io_requester
// toward cci
assign cci_tx_wr_cmd = (fc_tx_wr_valid)?`CCI_REQ_WR_THRU : rq_tx_wr_hdr[48:45];
assign cci_tx_wr_addr = (fc_tx_wr_valid)?fc_tx_wr_addr : rq_tx_wr_hdr[44:13];
assign cci_tx_data = (fc_tx_wr_valid)?fc_tx_data : rq_tx_data;
assign cci_tx_wr_tag = (fc_tx_wr_valid)?{1'b0, {{`QPI_TAG-`FPGA_CORE_TAG-1}{1'b0}}, fc_tx_wr_tag} :
{1'b1, rq_tx_wr_hdr[12:0]};
assign spl_tx_intr_valid = 1'b0;
always @(posedge clk) begin
if(~rst_n) begin
spl_tx_wr_valid <= 0;
spl_tx_wr_hdr <= 0;
//spl_tx_data <= 0;
end
else if(~cci_tx_wr_almostfull) begin
spl_tx_wr_valid <= tx_wr_fifo_valid;
spl_tx_wr_hdr <= tx_wr_fifo_hdr;
spl_tx_data <= tx_wr_fifo_data;
end
else spl_tx_wr_valid <= 1'b0;
end
// toward cci TX WR users: i.e. cmd_server, io_requester
assign rq_tx_wr_ready = (fc_tx_wr_valid)? 1'b0 : ~tx_wr_fifo_full;
assign fc_tx_wr_ready = ~tx_wr_fifo_full;
quick_fifo #(.FIFO_WIDTH(512 + 61),
.FIFO_DEPTH_BITS(5),
.FIFO_ALMOSTFULL_THRESHOLD(2**5 - 8)
) tx_wr_fifo(
.clk (clk),
.reset_n (rst_n),
.din ({5'b0, cci_tx_wr_cmd, 6'b0, cci_tx_wr_addr, cci_tx_wr_tag, cci_tx_data}),
.we ((fc_tx_wr_valid | rq_tx_wr_valid)),
.re (~cci_tx_wr_almostfull),
.dout ({tx_wr_fifo_hdr, tx_wr_fifo_data}),
.empty (),
.valid (tx_wr_fifo_valid),
.full (tx_wr_fifo_full),
.count (tx_wr_fifo_count),
.almostfull ()
);
///////////////////////////////////////////////////////////////////////////////////////////////////
///////////////////////////////// ///////////////////////////////////////
///////////////////////////// TX RD Driver ////////////////////////////////////
///////////////////////////////// ///////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////////////////////////
// TX RD is used by the io_requester and the fpga core
// toward cci
assign cci_tx_rd_addr = (fc_tx_rd_valid)? fc_tx_rd_addr : rq_tx_rd_hdr[44:13];
assign cci_tx_rd_tag = (fc_tx_rd_valid)? {1'b0, {{`QPI_TAG-`FPGA_CORE_TAG-1}{1'b0}}, fc_tx_rd_tag} :
{1'b1, rq_tx_rd_hdr[12:0]};
always @(posedge clk) begin
if(~rst_n) begin
spl_tx_rd_valid <= 0;
spl_tx_rd_hdr <= 0;
end
else if(~cci_tx_rd_almostfull) begin
spl_tx_rd_valid <= tx_rd_fifo_valid;
spl_tx_rd_hdr <= tx_rd_fifo_hdr;
end
else spl_tx_rd_valid <= 0;
end
// toward cci TX RD users: i.e. cmd_server, io_requester
assign rq_tx_rd_ready = (fc_tx_rd_valid)? 1'b0 : ~tx_rd_fifo_full;
assign fc_tx_rd_ready = ~tx_rd_fifo_full;
quick_fifo #(.FIFO_WIDTH(61),
.FIFO_DEPTH_BITS(5),
.FIFO_ALMOSTFULL_THRESHOLD(2**5 - 8)
) tx_rd_fifo(
.clk (clk),
.reset_n (rst_n),
.din ({5'b0, `CCI_REQ_RD, 6'b0, cci_tx_rd_addr, cci_tx_rd_tag}),
.we ((rq_tx_rd_valid | fc_tx_rd_valid)),
.re (~cci_tx_rd_almostfull),
.dout (tx_rd_fifo_hdr),
.empty (),
.valid (tx_rd_fifo_valid),
.full (tx_rd_fifo_full),
.count (),
.almostfull ()
);
/////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////// /////////////////////////////////////////////////
////////////////////////////////////////// RX RD Distributor //////////////////////////////////////////////
///////////////////////////////////////////// /////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// RX RD is used by cmd_server, arbiter, and page table
always @(posedge clk) begin
if(~rst_n) begin
io_rx_csr_valid <= 0;
io_rx_csr_addr <= 0;
io_rx_csr_data <= 0;
//
io_rx_rd_valid <= 0;
io_rx_rd_tag <= 0;
//io_rx_data <= 0;
//
//fc_rx_data <= 512'b0;
fc_rx_rd_tag <= 0;
fc_rx_rd_valid <= 1'b0;
end
else begin
//
io_rx_csr_valid <= cci_rx_cfg_valid;
io_rx_csr_addr <= cci_rx_hdr0[13:0];
io_rx_csr_data <= cci_rx_data[31:0];
//
io_rx_rd_valid <= cci_rx_rd_valid & cci_rx_hdr0[13];
io_rx_rd_tag <= cci_rx_hdr0[12:0];
io_rx_data <= cci_rx_data;
//
fc_rx_data <= cci_rx_data;
fc_rx_rd_tag <= cci_rx_hdr0[`FPGA_CORE_TAG-1:0];
fc_rx_rd_valid <= cci_rx_rd_valid & ~cci_rx_hdr0[13];
end
end
/////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////// /////////////////////////////////////////////////
////////////////////////////////////////// RX WR Distributor //////////////////////////////////////////////
///////////////////////////////////////////// /////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// regulate RX WR multiple responses
quick_fifo #(.FIFO_WIDTH(`CCI_RX_HDR_WIDTH),
.FIFO_DEPTH_BITS(9),
.FIFO_ALMOSTFULL_THRESHOLD(8)
) wr_rp_buf(
.clk (clk),
.reset_n (rst_n),
.din (cci_rx_hdr0),
.we (cci_rx_wr_valid1 & cci_rx_wr_valid0),
.re ( ~(cci_rx_wr_valid1 | cci_rx_wr_valid0) & wr_rp_buf_valid ),
.dout (wr_rp_buf_hdr),
.empty (wr_rp_buf_empty),
.valid (wr_rp_buf_valid),
.full (),
.count (wr_rp_buf_count),
.almostfull ()
);
//
assign wr_rp_valid = cci_rx_wr_valid1 | cci_rx_wr_valid0 | wr_rp_buf_valid;
assign wr_rp_hdr = (cci_rx_wr_valid1)? cci_rx_hdr1 : ((cci_rx_wr_valid0)? cci_rx_hdr0 : wr_rp_buf_hdr);
// SOME DEBUG COUNTERS
reg [39:0] rx_wr_resp_ch1;
reg [39:0] rx_wr_resp_ch0;
reg [39:0] rx_wr_resp_tot;
reg [39:0] tx_wr_req_tot;
always @(posedge clk) begin
if(~rst_n) begin
rx_wr_resp_ch1 <= 0;
rx_wr_resp_ch0 <= 0;
rx_wr_resp_tot <= 0;
tx_wr_req_tot <= 0;
end else begin
rx_wr_resp_ch1 <= (cci_rx_wr_valid1)? rx_wr_resp_ch1 + 1'b1 : rx_wr_resp_ch1;
rx_wr_resp_ch0 <= (cci_rx_wr_valid0)? rx_wr_resp_ch0 + 1'b1 : rx_wr_resp_ch0;
rx_wr_resp_tot <= (wr_rp_valid)? rx_wr_resp_tot + 1'b1 : rx_wr_resp_tot;
tx_wr_req_tot <= (spl_tx_wr_valid)? tx_wr_req_tot + 1'b1 : tx_wr_req_tot;
end
end
// RX WR is used by arbiter and cmd_server
always @(posedge clk) begin
if(~rst_n) begin
//
fc_rx_wr_tag <= 0;
fc_rx_wr_valid <= 1'b0;
io_rx_wr_valid <= 1'b0;
io_rx_wr_tag <= 0;
end
else begin
fc_rx_wr_tag <= wr_rp_hdr[`FPGA_CORE_TAG-1:0];
fc_rx_wr_valid <= wr_rp_valid & ~wr_rp_hdr[13];
io_rx_wr_valid <= wr_rp_valid & wr_rp_hdr[13];
io_rx_wr_tag <= wr_rp_hdr[12:0];
end
end
endmodule
|
module CHARMAP (
address,
clock,
q);
input [8:0] address;
input clock;
output [17:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
endmodule
|
module regs
reg ntsc = 0;
reg a1k = 0;
reg ecs = 0;
reg aga = 0;
reg [ 9-1:1] rga_adr = 0;
reg [16-1:0] rga_dat_w = 0;
wire [ 9-1:0] hpos;
wire [11-1:0] vpos;
wire _hsync;
wire _vsync;
wire _csync;
wire blank;
wire vbl;
wire vblend;
wire eol;
wire eof;
wire vbl_int;
wire [ 9-1:1] htotal;
reg dma_bpl_ena = 0;
wire dma_bpl;
wire [ 9-1:1] bpl_rga_adr;
wire [21-1:1] bpl_adr;
// testbench
initial begin
// bench start
$display("BENCH : start");
repeat(8) @ posedge CLK28;
// default settings
repeat (4) @ (posedge CLK28);
RST = 0;
// TODO
// test 1 bpl
// TODO
end
// reg write task
task reg_wr;
input [9:0] adr;
input [15:0] dat;
begin
wait (!CLK7_EN);
@ (posedge CLK28);
rga_adr = adr;
rga_dat = dat;
wait(CLK7_EN);
@ (posedge CLK28);
rga_adr = 0;
rga_dat = 0;
end
endtask
// agnus_beamcounter
agnus_beamcounter beamcounter (
.clk (CLK28),
.clk7_en (CLK7_EN),
.reset (RST),
.cck (CCK),
.ntsc (ntsc),
.aga (aga),
.ecs (ecs),
.a1k (a1k),
.data_in (rga_dat_w),
.data_out (),
.reg_address_in (rga_adr),
.hpos (hpos),
.vpos (vpos),
._hsync (_hsync),
._vsync (_vsync),
._csync (_csync),
.blank (blank),
.vbl (vbl),
.vblend (vblend),
.eol (sol),
.eof (sof),
.vbl_int (vbl_int),
.htotal (htotal)
);
// agnus_bitplanedma
agnus_bitplanedma bitplanedma (
.clk (CLK28),
.clk7_en (CLK7_EN),
.reset (RST),
.aga (aga),
.ecs (ecs),
.a1k (a1k),
.sof (sof),
.dmaena (dma_bpl_ena),
.vpos (vpos),
.hpos (hpos),
.dma (dma_bpl),
.reg_address_in (rga_adr),
.reg_address_out(bpl_rga_adr),
.data_in (rga_dat_W),
.address_out (bpl_adr)
);
endmodule
|
module sky130_fd_sc_hd__dfxtp (
Q ,
CLK,
D
);
output Q ;
input CLK;
input D ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
|
module sky130_fd_sc_lp__invkapwr (
Y,
A
);
// Module ports
output Y;
input A;
// Local signals
wire not0_out_Y;
// Name Output Other arguments
not not0 (not0_out_Y, A );
buf buf0 (Y , not0_out_Y );
endmodule
|
module sky130_fd_sc_lp__nand2b (
//# {{data|Data Signals}}
input A_N,
input B ,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
|
module oddr #
(
// target ("SIM", "GENERIC", "XILINX", "ALTERA")
parameter TARGET = "GENERIC",
// IODDR style ("IODDR", "IODDR2")
// Use IODDR for Virtex-4, Virtex-5, Virtex-6, 7 Series, Ultrascale
// Use IODDR2 for Spartan-6
parameter IODDR_STYLE = "IODDR2",
// Width of register in bits
parameter WIDTH = 1
)
(
input wire clk,
input wire [WIDTH-1:0] d1,
input wire [WIDTH-1:0] d2,
output wire [WIDTH-1:0] q
);
/*
Provides a consistent output DDR flip flop across multiple FPGA families
_____ _____ _____ _____
clk ____/ \_____/ \_____/ \_____/ \_____
_ ___________ ___________ ___________ ___________ __
d1 _X____D0_____X____D2_____X____D4_____X____D6_____X__
_ ___________ ___________ ___________ ___________ __
d2 _X____D1_____X____D3_____X____D5_____X____D7_____X__
_____ _____ _____ _____ _____ _____ _____ _____ ____
d _____X_D0__X_D1__X_D2__X_D3__X_D4__X_D5__X_D6__X_D7_
*/
genvar n;
generate
if (TARGET == "XILINX") begin
for (n = 0; n < WIDTH; n = n + 1) begin : oddr
if (IODDR_STYLE == "IODDR") begin
ODDR #(
.DDR_CLK_EDGE("SAME_EDGE"),
.SRTYPE("ASYNC")
)
oddr_inst (
.Q(q[n]),
.C(clk),
.CE(1'b1),
.D1(d1[n]),
.D2(d2[n]),
.R(1'b0),
.S(1'b0)
);
end else if (IODDR_STYLE == "IODDR2") begin
ODDR2 #(
.DDR_ALIGNMENT("C0"),
.SRTYPE("ASYNC")
)
oddr_inst (
.Q(q[n]),
.C0(clk),
.C1(~clk),
.CE(1'b1),
.D0(d1[n]),
.D1(d2[n]),
.R(1'b0),
.S(1'b0)
);
end
end
end else if (TARGET == "ALTERA") begin
altddio_out #(
.WIDTH(WIDTH),
.POWER_UP_HIGH("OFF"),
.OE_REG("UNUSED")
)
altddio_out_inst (
.aset(1'b0),
.datain_h(d1),
.datain_l(d2),
.outclocken(1'b1),
.outclock(clk),
.aclr(1'b0),
.dataout(q)
);
end else begin
reg [WIDTH-1:0] d_reg_1 = {WIDTH{1'b0}};
reg [WIDTH-1:0] d_reg_2 = {WIDTH{1'b0}};
reg [WIDTH-1:0] q_reg = {WIDTH{1'b0}};
always @(posedge clk) begin
d_reg_1 <= d1;
d_reg_2 <= d2;
end
always @(posedge clk) begin
q_reg <= d1;
end
always @(negedge clk) begin
q_reg <= d_reg_2;
end
assign q = q_reg;
end
endgenerate
endmodule
|
module SD_host (clk_host,
reset_host,
io_enable_cmd,
CMD_PIN_IN,
CMD_PIN_OUT,
clk_SD,
data_in_register,
data_out_register,
req_register,
ack_register,
addres_register,
rw_register,
DATA_PIN_IN,
DATA_PIN_OUT,
IO_enable_Phy_SD_CARD,
pad_enable_Phy_PAD,
pad_state_Phy_PAD,
cmd_reg_write,
cmd_reg_read,
Continue,
descriptor_table,
TRAN,
STOP);
//señales del host
input wire clk_host, reset_host;
input wire DATA_PIN_IN;
output wire DATA_PIN_OUT;
output wire IO_enable_Phy_SD_CARD;
//outputs para el estado del PAD
output wire pad_enable_Phy_PAD;
output wire pad_state_Phy_PAD;
//señales del CMD
input wire CMD_PIN_IN;
output wire io_enable_cmd, CMD_PIN_OUT;
//señales del register
input wire [31:0]data_in_register;
output wire [31:0] data_out_register;
input wire req_register;
input wire ack_register;
input wire [4:0]addres_register;
input wire rw_register;
// señales de DMA
input wire cmd_reg_write;
input wire cmd_reg_read;
input wire Continue;
input wire [6:0][85:0] descriptor_table;
input wire TRAN;
input wire STOP;
//señales compartidas del SD
input wire clk_SD;
//cables de conexion entre DMA y CMD
wire new_command;
//cables de conexion entre REG y CMD
wire [31:0]cmd_argument;
wire [5:0]cmd_index;
wire [127:0]response;
wire cmd_complete, cmd_index_error;
assign cmd_argument = bloque_registers.Argument;
assign cmd_index = bloque_registers.cmd_index;
assign bloque_registers.cmd_complete = cmd_complete;
assign bloque_registers.cmd_index_error = cmd_index_error;
//wires entre REGS y DATA
wire [15:0] timeout_Reg_Regs_DATA;
wire writeRead_Regs_DATA;
wire [3:0] blockCount_Regs_DATA;
wire multipleData_Regs_DATA;
wire timeout_enable_Regs_DATA;
//wires entre DMA y DATA
wire transfer_complete_DATA_DMA;
assign timeout_Reg_Regs_DATA = bloque_registers.Timeout_Reg;
assign writeRead_Regs_DATA = bloque_registers.writeRead;
assign blockCount_Regs_DATA = bloque_registers.block_count;
assign multipleData_Regs_DATA = bloque_registers.multipleData;
assign timeout_enable_Regs_DATA = bloque_registers.timeout_enable;
// wire entre DMA y FIFO
wire FIFO_EMPTY_DMA;
wire FIFO_FULL_DMA;
wire [63:0] system_address;
wire writing_mem; // 1 if dir = 0 and TFC = 0
wire reading_mem; //
wire reading_fifo;
wire writing_fifo;
wire [5:0] next_descriptor_index;
reg [5:0] descriptor_index;
always @(posedge clk_host) begin
descriptor_index <= next_descriptor_index;
end
DMA bloqueDMA(reset,
clk_host,
transfer_complete_DATA_DMA,
cmd_reg_write,
cmd_reg_read,
Continue,
TRAN,
STOP,
FIFO_EMPTY_DMA,
FIFO_FULL_DMA,
descriptor_table [0][85:22], // data_address
descriptor_table [0][20:5], // length
descriptor_index,
descriptor_table [0][4], //act1
descriptor_table [0][3], //act2
descriptor_table [0][2], // END
descriptor_table [0][1], // valid
descriptor_table [0][0], // dir
new_command, // To CMD block
system_address,
writing_mem, // 1 if dir = 0 and TFC = 0
reading_mem, //
reading_fifo,
writing_fifo,
next_descriptor_index);
CMD bloque_CMD(clk_host, reset_host, new_command, cmd_argument, cmd_index, cmd_complete, cmd_index_error, response, CMD_PIN_OUT, IO_enable_pin, CMD_PIN_IN, clk_SD);
REG bloque_registers(clk_host, rw_register, addres_register, data_in_register, data_out_register);
//Bloque de DATA
BloqueDATA Data_Control(
.CLK(clk_host),
.SD_CLK(clk_SD),
.RESET_L(reset_host),
.timeout_Reg_Regs_DATA(timeout_Reg_Regs_DATA),
.writeRead_Regs_DATA(writeRead_Regs_DATA),
.blockCount_Regs_DATA(blockCount_Regs_DATA),
.multipleData_Regs_DATA(multipleData_Regs_DATA),
.timeout_enable_Regs_DATA(timeout_enable_Regs_DATA),
//.FIFO_OK_FIFO_DATA(),
//.[31:0] dataFromFIFO_FIFO_Phy(),
//.New_DAT_DMA_DATA(),
//.DATA_PIN_IN(DATA_PIN_IN),
//.writeFIFO_enable_Phy_FIFO(),
//.readFIFO_enable_Phy_FIFO(),
//.[31:0] dataReadToFIFO_Phy_FIFO(),
.transfer_complete_DATA_DMA(transfer_complete_DATA_DMA),
.IO_enable_Phy_SD_CARD(IO_enable_Phy_SD_CARD),
.DATA_PIN_OUT(DATA_PIN_OUT),
.pad_state_Phy_PAD(pad_state_Phy_PAD),
.pad_enable_Phy_PAD(pad_enable_Phy_PAD)
);
endmodule
|
module sky130_fd_sc_ls__nand3b (
Y ,
A_N,
B ,
C
);
// Module ports
output Y ;
input A_N;
input B ;
input C ;
// Local signals
wire not0_out ;
wire nand0_out_Y;
// Name Output Other arguments
not not0 (not0_out , A_N );
nand nand0 (nand0_out_Y, B, not0_out, C );
buf buf0 (Y , nand0_out_Y );
endmodule
|
module sky130_fd_sc_hs__diode (
//# {{power|Power}}
input DIODE,
input VPB ,
input VPWR ,
input VGND ,
input VNB
);
endmodule
|
module bsg_mul_add_unsigned #(
parameter `BSG_INV_PARAM(width_a_p)
,parameter `BSG_INV_PARAM(width_b_p)
,parameter width_c_p = width_a_p + width_b_p
,parameter width_o_p = `BSG_SAFE_CLOG2( ((1 << width_a_p) - 1) * ((1 << width_b_p) - 1) +
((1 << width_c_p)-1) + 1 )
,parameter pipeline_p = 0
) (
input clk_i
,input [width_a_p-1 : 0] a_i
,input [width_b_p-1 : 0] b_i
,input [width_c_p-1 : 0] c_i
,output [width_o_p-1 : 0] o
);
initial assert (pipeline_p > 2) else $warning ("%m: pipeline_p is set quite low; most likely frequency will be impacted")
localparam pre_pipeline_lp = pipeline_p > 2 ? 1 : 0;
localparam post_pipeline_lp = pipeline_p > 2 ? pipeline_p -1 : pipeline_p; //for excess
wire [width_a_p-1:0] a_r;
wire [width_b_p-1:0] b_r;
wire [width_c_p-1:0] c_r;
bsg_dff_chain #(width_a_p + width_b_p + width_c_p, pre_pipeline_lp)
pre_mul_add (
.clk_i(clk_i)
,.data_i({a_i, b_i, c_i})
,.data_o({a_r, b_r, c_r})
);
wire [width_o_p-1:0] o_r = a_r * b_r + c_r;
bsg_dff_chain #(width_o_p, post_pipeline_lp)
post_mul_add (
.clk_i(clk_i)
,.data_i(o_r)
,.data_o(o)
);
endmodule
|
module sky130_fd_sc_hd__or2_4 (
X ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__or2 base (
.X(X),
.A(A),
.B(B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
|
module sky130_fd_sc_hd__or2_4 (
X,
A,
B
);
output X;
input A;
input B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__or2 base (
.X(X),
.A(A),
.B(B)
);
endmodule
|
module sign_inverter #(parameter W = 32)
(
input wire [W-1:0] data,
input wire [1:0] shift_region_flag,
input wire operation,
output reg [W-1:0] data_out
);
always@*
begin
if(operation == 1'b0)//coseno
begin
if(shift_region_flag == 2'b00 || shift_region_flag == 2'b11)//no hay desplazamiento
begin
data_out = data;
end
else
begin
if((shift_region_flag == 2'b01) && (data[W-1] == 1'b0))
begin
data_out = {1'b1,data[W-2:0]};
end
else if((shift_region_flag == 2'b01) && (data[W-1] == 1'b1))
begin
data_out = {1'b0,data[W-2:0]};
end
else
begin
data_out = data;
end
end
end
else //seno
begin
if(shift_region_flag == 2'b00 || shift_region_flag == 2'b11)//no hay desplazamiento
begin
data_out = data;
end
else
begin
if((shift_region_flag == 2'b10) && (data[W-1] == 1'b0))
begin
data_out = {1'b1,data[W-2:0]};
end
else if((shift_region_flag == 2'b10) && (data[W-1] == 1'b1))
begin
data_out = {1'b0,data[W-2:0]};
end
else
begin
data_out = data;
end
end
end
end
endmodule
|
module outputs
wire [23 : 0] flash_addr;
wire [19 : 0] led_anode, led_cathode;
wire [15 : 0] hsmc_out, led;
wire [12 : 0] dram_addr;
wire [3 : 0] lcd_db, pcie_tx;
wire [2 : 0] dram_ba;
wire [1 : 0] dram_dm;
wire CLK_GATE_p125clk,
dram_cas_n,
dram_ck_n,
dram_ck_p,
dram_cke,
dram_cs_n,
dram_odt,
dram_ras_n,
dram_reset_n,
dram_we_n,
flash_adv_n,
flash_ce_n,
flash_oe_n,
flash_rst_n,
flash_we_n,
flash_wp_n,
gps_ppsSyncOut,
lcd_e,
lcd_rs,
lcd_rw,
p125clk,
p125rst;
// inlined wires
wire [127 : 0] pciw_pci0_rxDws_new_data$wget, pciw_pci0_txDws_new_data$wget;
wire [2 : 0] pciw_pci0_rxDws_delta_deq$wget,
pciw_pci0_rxDws_delta_enq$wget,
pciw_pci0_txDws_delta_deq$wget,
pciw_pci0_txDws_delta_enq$wget;
wire [1 : 0] infLed$wget;
wire pciw_pci0_avaTxEmpty$wget,
pciw_pci0_avaTxEmpty$whas,
pciw_pci0_avaTxEop$wget,
pciw_pci0_avaTxEop$whas,
pciw_pci0_avaTxErr$wget,
pciw_pci0_avaTxErr$whas,
pciw_pci0_avaTxSop$wget,
pciw_pci0_avaTxSop$whas,
pciw_pci0_avaTxValid$wget,
pciw_pci0_avaTxValid$whas,
pciw_pci0_rxDws_delta_deq$whas,
pciw_pci0_rxDws_delta_enq$whas,
pciw_pci0_rxDws_new_data$whas,
pciw_pci0_rxInF_doResetClr$whas,
pciw_pci0_rxInF_doResetDeq$whas,
pciw_pci0_rxInF_doResetEnq$whas,
pciw_pci0_rxInF_r_clr$whas,
pciw_pci0_rxInF_r_deq$whas,
pciw_pci0_rxInF_r_enq$whas,
pciw_pci0_txDws_delta_deq$whas,
pciw_pci0_txDws_delta_enq$whas,
pciw_pci0_txDws_new_data$whas,
pciw_pci0_txOutF_doResetClr$whas,
pciw_pci0_txOutF_doResetDeq$whas,
pciw_pci0_txOutF_doResetEnq$whas,
pciw_pci0_txOutF_r_clr$whas,
pciw_pci0_txOutF_r_deq$whas,
pciw_pci0_txOutF_r_enq$whas;
// register freeCnt
reg [31 : 0] freeCnt;
wire [31 : 0] freeCnt$D_IN;
wire freeCnt$EN;
// register hsmcReg
reg [15 : 0] hsmcReg;
wire [15 : 0] hsmcReg$D_IN;
wire hsmcReg$EN;
// register ledReg
reg [15 : 0] ledReg;
wire [15 : 0] ledReg$D_IN;
wire ledReg$EN;
// register needs_init
reg needs_init;
wire needs_init$D_IN, needs_init$EN;
// register pciDevice
reg [15 : 0] pciDevice;
wire [15 : 0] pciDevice$D_IN;
wire pciDevice$EN;
// register pciw_pci0_cfgDataWr
reg pciw_pci0_cfgDataWr;
wire pciw_pci0_cfgDataWr$D_IN, pciw_pci0_cfgDataWr$EN;
// register pciw_pci0_cfgSample
reg pciw_pci0_cfgSample;
wire pciw_pci0_cfgSample$D_IN, pciw_pci0_cfgSample$EN;
// register pciw_pci0_deviceReg
reg [15 : 0] pciw_pci0_deviceReg;
wire [15 : 0] pciw_pci0_deviceReg$D_IN;
wire pciw_pci0_deviceReg$EN;
// register pciw_pci0_rxDbgDeDeq
reg [15 : 0] pciw_pci0_rxDbgDeDeq;
wire [15 : 0] pciw_pci0_rxDbgDeDeq$D_IN;
wire pciw_pci0_rxDbgDeDeq$EN;
// register pciw_pci0_rxDbgDeEof
reg [15 : 0] pciw_pci0_rxDbgDeEof;
wire [15 : 0] pciw_pci0_rxDbgDeEof$D_IN;
wire pciw_pci0_rxDbgDeEof$EN;
// register pciw_pci0_rxDbgDeSof
reg [15 : 0] pciw_pci0_rxDbgDeSof;
wire [15 : 0] pciw_pci0_rxDbgDeSof$D_IN;
wire pciw_pci0_rxDbgDeSof$EN;
// register pciw_pci0_rxDbgDestage
reg [15 : 0] pciw_pci0_rxDbgDestage;
wire [15 : 0] pciw_pci0_rxDbgDestage$D_IN;
wire pciw_pci0_rxDbgDestage$EN;
// register pciw_pci0_rxDbgEnEnq
reg [15 : 0] pciw_pci0_rxDbgEnEnq;
wire [15 : 0] pciw_pci0_rxDbgEnEnq$D_IN;
wire pciw_pci0_rxDbgEnEnq$EN;
// register pciw_pci0_rxDbgEnEof
reg [15 : 0] pciw_pci0_rxDbgEnEof;
wire [15 : 0] pciw_pci0_rxDbgEnEof$D_IN;
wire pciw_pci0_rxDbgEnEof$EN;
// register pciw_pci0_rxDbgEnSof
reg [15 : 0] pciw_pci0_rxDbgEnSof;
wire [15 : 0] pciw_pci0_rxDbgEnSof$D_IN;
wire pciw_pci0_rxDbgEnSof$EN;
// register pciw_pci0_rxDbgEnstage
reg [15 : 0] pciw_pci0_rxDbgEnstage;
wire [15 : 0] pciw_pci0_rxDbgEnstage$D_IN;
wire pciw_pci0_rxDbgEnstage$EN;
// register pciw_pci0_rxDbgInstage
reg [15 : 0] pciw_pci0_rxDbgInstage;
wire [15 : 0] pciw_pci0_rxDbgInstage$D_IN;
wire pciw_pci0_rxDbgInstage$EN;
// register pciw_pci0_rxDwrDeq
reg [10 : 0] pciw_pci0_rxDwrDeq;
wire [10 : 0] pciw_pci0_rxDwrDeq$D_IN;
wire pciw_pci0_rxDwrDeq$EN;
// register pciw_pci0_rxDwrEnq
reg [10 : 0] pciw_pci0_rxDwrEnq;
wire [10 : 0] pciw_pci0_rxDwrEnq$D_IN;
wire pciw_pci0_rxDwrEnq$EN;
// register pciw_pci0_rxDws_num_empty
reg [3 : 0] pciw_pci0_rxDws_num_empty;
wire [3 : 0] pciw_pci0_rxDws_num_empty$D_IN;
wire pciw_pci0_rxDws_num_empty$EN;
// register pciw_pci0_rxDws_num_full
reg [3 : 0] pciw_pci0_rxDws_num_full;
wire [3 : 0] pciw_pci0_rxDws_num_full$D_IN;
wire pciw_pci0_rxDws_num_full$EN;
// register pciw_pci0_rxDws_vec
reg [255 : 0] pciw_pci0_rxDws_vec;
wire [255 : 0] pciw_pci0_rxDws_vec$D_IN;
wire pciw_pci0_rxDws_vec$EN;
// register pciw_pci0_rxInF_countReg
reg [5 : 0] pciw_pci0_rxInF_countReg;
wire [5 : 0] pciw_pci0_rxInF_countReg$D_IN;
wire pciw_pci0_rxInF_countReg$EN;
// register pciw_pci0_rxInF_levelsValid
reg pciw_pci0_rxInF_levelsValid;
wire pciw_pci0_rxInF_levelsValid$D_IN, pciw_pci0_rxInF_levelsValid$EN;
// register pciw_pci0_rxInFlight
reg pciw_pci0_rxInFlight;
wire pciw_pci0_rxInFlight$D_IN, pciw_pci0_rxInFlight$EN;
// register pciw_pci0_txDbgDeDeq
reg [15 : 0] pciw_pci0_txDbgDeDeq;
wire [15 : 0] pciw_pci0_txDbgDeDeq$D_IN;
wire pciw_pci0_txDbgDeDeq$EN;
// register pciw_pci0_txDbgDeEof
reg [15 : 0] pciw_pci0_txDbgDeEof;
wire [15 : 0] pciw_pci0_txDbgDeEof$D_IN;
wire pciw_pci0_txDbgDeEof$EN;
// register pciw_pci0_txDbgDeSof
reg [15 : 0] pciw_pci0_txDbgDeSof;
wire [15 : 0] pciw_pci0_txDbgDeSof$D_IN;
wire pciw_pci0_txDbgDeSof$EN;
// register pciw_pci0_txDbgDestage
reg [15 : 0] pciw_pci0_txDbgDestage;
wire [15 : 0] pciw_pci0_txDbgDestage$D_IN;
wire pciw_pci0_txDbgDestage$EN;
// register pciw_pci0_txDbgEnEnq
reg [15 : 0] pciw_pci0_txDbgEnEnq;
wire [15 : 0] pciw_pci0_txDbgEnEnq$D_IN;
wire pciw_pci0_txDbgEnEnq$EN;
// register pciw_pci0_txDbgEnEof
reg [15 : 0] pciw_pci0_txDbgEnEof;
wire [15 : 0] pciw_pci0_txDbgEnEof$D_IN;
wire pciw_pci0_txDbgEnEof$EN;
// register pciw_pci0_txDbgEnSof
reg [15 : 0] pciw_pci0_txDbgEnSof;
wire [15 : 0] pciw_pci0_txDbgEnSof$D_IN;
wire pciw_pci0_txDbgEnSof$EN;
// register pciw_pci0_txDbgEnstage
reg [15 : 0] pciw_pci0_txDbgEnstage;
wire [15 : 0] pciw_pci0_txDbgEnstage$D_IN;
wire pciw_pci0_txDbgEnstage$EN;
// register pciw_pci0_txDbgExstage
reg [15 : 0] pciw_pci0_txDbgExstage;
wire [15 : 0] pciw_pci0_txDbgExstage$D_IN;
wire pciw_pci0_txDbgExstage$EN;
// register pciw_pci0_txDwrDeq
reg [10 : 0] pciw_pci0_txDwrDeq;
wire [10 : 0] pciw_pci0_txDwrDeq$D_IN;
wire pciw_pci0_txDwrDeq$EN;
// register pciw_pci0_txDwrEnq
reg [10 : 0] pciw_pci0_txDwrEnq;
wire [10 : 0] pciw_pci0_txDwrEnq$D_IN;
wire pciw_pci0_txDwrEnq$EN;
// register pciw_pci0_txDws_num_empty
reg [3 : 0] pciw_pci0_txDws_num_empty;
wire [3 : 0] pciw_pci0_txDws_num_empty$D_IN;
wire pciw_pci0_txDws_num_empty$EN;
// register pciw_pci0_txDws_num_full
reg [3 : 0] pciw_pci0_txDws_num_full;
wire [3 : 0] pciw_pci0_txDws_num_full$D_IN;
wire pciw_pci0_txDws_num_full$EN;
// register pciw_pci0_txDws_vec
reg [255 : 0] pciw_pci0_txDws_vec;
wire [255 : 0] pciw_pci0_txDws_vec$D_IN;
wire pciw_pci0_txDws_vec$EN;
// register pciw_pci0_txInFlight
reg pciw_pci0_txInFlight;
wire pciw_pci0_txInFlight$D_IN, pciw_pci0_txInFlight$EN;
// register pciw_pci0_txOutF_countReg
reg [9 : 0] pciw_pci0_txOutF_countReg;
wire [9 : 0] pciw_pci0_txOutF_countReg$D_IN;
wire pciw_pci0_txOutF_countReg$EN;
// register pciw_pci0_txOutF_levelsValid
reg pciw_pci0_txOutF_levelsValid;
wire pciw_pci0_txOutF_levelsValid$D_IN, pciw_pci0_txOutF_levelsValid$EN;
// register pciw_pci0_txReadyD
reg pciw_pci0_txReadyD;
wire pciw_pci0_txReadyD$D_IN, pciw_pci0_txReadyD$EN;
// register pciw_pciDevice
reg [15 : 0] pciw_pciDevice;
wire [15 : 0] pciw_pciDevice$D_IN;
wire pciw_pciDevice$EN;
// register swReg
reg [7 : 0] swReg;
wire [7 : 0] swReg$D_IN;
wire swReg$EN;
// ports of submodule ctop
wire [152 : 0] ctop$server_request_put, ctop$server_response_get;
wire [127 : 0] ctop$wmemiM0_MData, ctop$wmemiM0_SData;
wire [58 : 0] ctop$cpServer_request_put;
wire [35 : 0] ctop$wmemiM0_MAddr;
wire [31 : 0] ctop$wci_m_0_SData,
ctop$wci_m_1_MAddr,
ctop$wci_m_1_MData,
ctop$wci_m_1_SData,
ctop$wci_m_2_SData,
ctop$wci_m_3_SData,
ctop$wci_m_4_MAddr,
ctop$wci_m_4_MData,
ctop$wci_m_4_SData,
ctop$wsi_s_adc_MData;
wire [15 : 0] ctop$wmemiM0_MDataByteEn;
wire [11 : 0] ctop$wmemiM0_MBurstLength, ctop$wsi_s_adc_MBurstLength;
wire [7 : 0] ctop$wsi_s_adc_MReqInfo;
wire [3 : 0] ctop$wci_m_1_MByteEn,
ctop$wci_m_4_MByteEn,
ctop$wsi_s_adc_MByteEn;
wire [2 : 0] ctop$switch_x,
ctop$wci_m_1_MCmd,
ctop$wci_m_4_MCmd,
ctop$wmemiM0_MCmd,
ctop$wsi_s_adc_MCmd;
wire [1 : 0] ctop$led,
ctop$wci_m_0_SFlag,
ctop$wci_m_0_SResp,
ctop$wci_m_1_MFlag,
ctop$wci_m_1_SFlag,
ctop$wci_m_1_SResp,
ctop$wci_m_2_SFlag,
ctop$wci_m_2_SResp,
ctop$wci_m_3_SFlag,
ctop$wci_m_3_SResp,
ctop$wci_m_4_MFlag,
ctop$wci_m_4_SFlag,
ctop$wci_m_4_SResp,
ctop$wmemiM0_SResp;
wire ctop$EN_cpServer_request_put,
ctop$EN_cpServer_response_get,
ctop$EN_server_request_put,
ctop$EN_server_response_get,
ctop$RDY_server_request_put,
ctop$RDY_server_response_get,
ctop$RST_N_wci_m_1,
ctop$RST_N_wci_m_4,
ctop$gps_ppsSyncIn_x,
ctop$gps_ppsSyncOut,
ctop$wci_m_0_SThreadBusy,
ctop$wci_m_1_MAddrSpace,
ctop$wci_m_1_SThreadBusy,
ctop$wci_m_2_SThreadBusy,
ctop$wci_m_3_SThreadBusy,
ctop$wci_m_4_MAddrSpace,
ctop$wci_m_4_SThreadBusy,
ctop$wmemiM0_MDataLast,
ctop$wmemiM0_MDataValid,
ctop$wmemiM0_MReqLast,
ctop$wmemiM0_MReset_n,
ctop$wmemiM0_SCmdAccept,
ctop$wmemiM0_SDataAccept,
ctop$wmemiM0_SRespLast,
ctop$wsi_m_dac_SReset_n,
ctop$wsi_m_dac_SThreadBusy,
ctop$wsi_s_adc_MBurstPrecise,
ctop$wsi_s_adc_MReqLast,
ctop$wsi_s_adc_MReset_n;
// ports of submodule dram0
wire [127 : 0] dram0$wmemiS0_MData, dram0$wmemiS0_SData;
wire [35 : 0] dram0$wmemiS0_MAddr;
wire [31 : 0] dram0$wciS0_MAddr, dram0$wciS0_MData, dram0$wciS0_SData;
wire [15 : 0] dram0$dram_io_dq, dram0$wmemiS0_MDataByteEn;
wire [12 : 0] dram0$dram_addr;
wire [11 : 0] dram0$wmemiS0_MBurstLength;
wire [3 : 0] dram0$wciS0_MByteEn;
wire [2 : 0] dram0$dram_ba, dram0$wciS0_MCmd, dram0$wmemiS0_MCmd;
wire [1 : 0] dram0$dram_dm,
dram0$dram_io_dqs_n,
dram0$dram_io_dqs_p,
dram0$wciS0_MFlag,
dram0$wciS0_SFlag,
dram0$wciS0_SResp,
dram0$wmemiS0_SResp;
wire dram0$dram_cas_n,
dram0$dram_ck_n,
dram0$dram_ck_p,
dram0$dram_cke,
dram0$dram_cs_n,
dram0$dram_odt,
dram0$dram_ras_n,
dram0$dram_rdn_i,
dram0$dram_reset_n,
dram0$dram_rup_i,
dram0$dram_we_n,
dram0$wciS0_MAddrSpace,
dram0$wciS0_SThreadBusy,
dram0$wmemiS0_MDataLast,
dram0$wmemiS0_MDataValid,
dram0$wmemiS0_MReqLast,
dram0$wmemiS0_MReset_n,
dram0$wmemiS0_SCmdAccept,
dram0$wmemiS0_SDataAccept,
dram0$wmemiS0_SRespLast;
// ports of submodule flash0
wire [31 : 0] flash0$wciS0_MAddr, flash0$wciS0_MData, flash0$wciS0_SData;
wire [23 : 0] flash0$flash_addr;
wire [15 : 0] flash0$flash_io_dq;
wire [3 : 0] flash0$wciS0_MByteEn;
wire [2 : 0] flash0$wciS0_MCmd;
wire [1 : 0] flash0$wciS0_MFlag, flash0$wciS0_SFlag, flash0$wciS0_SResp;
wire flash0$flash_adv_n,
flash0$flash_ce_n,
flash0$flash_fwait_i,
flash0$flash_oe_n,
flash0$flash_rst_n,
flash0$flash_we_n,
flash0$flash_wp_n,
flash0$wciS0_MAddrSpace,
flash0$wciS0_SThreadBusy;
// ports of submodule lcd_ctrl
wire [127 : 0] lcd_ctrl$setLine1_text, lcd_ctrl$setLine2_text;
wire [3 : 0] lcd_ctrl$db;
wire lcd_ctrl$EN_setLine1,
lcd_ctrl$EN_setLine2,
lcd_ctrl$e,
lcd_ctrl$rs,
lcd_ctrl$rw;
// ports of submodule pciw_aliveLed_sb
wire pciw_aliveLed_sb$dD_OUT, pciw_aliveLed_sb$sD_IN, pciw_aliveLed_sb$sEN;
// ports of submodule pciw_i2pF
wire [152 : 0] pciw_i2pF$D_IN, pciw_i2pF$D_OUT;
wire pciw_i2pF$CLR,
pciw_i2pF$DEQ,
pciw_i2pF$EMPTY_N,
pciw_i2pF$ENQ,
pciw_i2pF$FULL_N;
// ports of submodule pciw_linkLed_sb
wire pciw_linkLed_sb$dD_OUT, pciw_linkLed_sb$sD_IN, pciw_linkLed_sb$sEN;
// ports of submodule pciw_p2iF
wire [152 : 0] pciw_p2iF$D_IN, pciw_p2iF$D_OUT;
wire pciw_p2iF$CLR,
pciw_p2iF$DEQ,
pciw_p2iF$EMPTY_N,
pciw_p2iF$ENQ,
pciw_p2iF$FULL_N;
// ports of submodule pciw_pci0_pcie_ep
wire [127 : 0] pciw_pci0_pcie_ep$rx_st_data0, pciw_pci0_pcie_ep$tx_st_data0;
wire [31 : 0] pciw_pci0_pcie_ep$ava_debug, pciw_pci0_pcie_ep$tl_cfg_ctl;
wire [15 : 0] pciw_pci0_pcie_ep$rx_st_be0;
wire [7 : 0] pciw_pci0_pcie_ep$rx_st_bardec0;
wire [3 : 0] pciw_pci0_pcie_ep$pcie_rx_in,
pciw_pci0_pcie_ep$pcie_tx_out,
pciw_pci0_pcie_ep$tl_cfg_add;
wire pciw_pci0_pcie_ep$ava_alive,
pciw_pci0_pcie_ep$ava_core_clk_out,
pciw_pci0_pcie_ep$ava_lnk_up,
pciw_pci0_pcie_ep$ava_srstn,
pciw_pci0_pcie_ep$rx_st_empty0,
pciw_pci0_pcie_ep$rx_st_eop0,
pciw_pci0_pcie_ep$rx_st_mask0,
pciw_pci0_pcie_ep$rx_st_ready0,
pciw_pci0_pcie_ep$rx_st_sop0,
pciw_pci0_pcie_ep$rx_st_valid0,
pciw_pci0_pcie_ep$tl_cfg_ctl_wr,
pciw_pci0_pcie_ep$tx_st_empty0,
pciw_pci0_pcie_ep$tx_st_eop0,
pciw_pci0_pcie_ep$tx_st_err0,
pciw_pci0_pcie_ep$tx_st_ready0,
pciw_pci0_pcie_ep$tx_st_sop0,
pciw_pci0_pcie_ep$tx_st_valid0;
// ports of submodule pciw_pci0_rxEofF
wire [2 : 0] pciw_pci0_rxEofF$D_IN;
wire pciw_pci0_rxEofF$CLR,
pciw_pci0_rxEofF$DEQ,
pciw_pci0_rxEofF$EMPTY_N,
pciw_pci0_rxEofF$ENQ,
pciw_pci0_rxEofF$FULL_N;
// ports of submodule pciw_pci0_rxHeadF
wire [30 : 0] pciw_pci0_rxHeadF$D_IN, pciw_pci0_rxHeadF$D_OUT;
wire pciw_pci0_rxHeadF$CLR,
pciw_pci0_rxHeadF$DEQ,
pciw_pci0_rxHeadF$EMPTY_N,
pciw_pci0_rxHeadF$ENQ,
pciw_pci0_rxHeadF$FULL_N;
// ports of submodule pciw_pci0_rxInF
wire [154 : 0] pciw_pci0_rxInF$D_IN, pciw_pci0_rxInF$D_OUT;
wire pciw_pci0_rxInF$CLR,
pciw_pci0_rxInF$DEQ,
pciw_pci0_rxInF$EMPTY_N,
pciw_pci0_rxInF$ENQ,
pciw_pci0_rxInF$FULL_N;
// ports of submodule pciw_pci0_rxOutF
wire [152 : 0] pciw_pci0_rxOutF$D_IN, pciw_pci0_rxOutF$D_OUT;
wire pciw_pci0_rxOutF$CLR,
pciw_pci0_rxOutF$DEQ,
pciw_pci0_rxOutF$EMPTY_N,
pciw_pci0_rxOutF$ENQ,
pciw_pci0_rxOutF$FULL_N;
// ports of submodule pciw_pci0_txEofF
wire [2 : 0] pciw_pci0_txEofF$D_IN;
wire pciw_pci0_txEofF$CLR,
pciw_pci0_txEofF$DEQ,
pciw_pci0_txEofF$EMPTY_N,
pciw_pci0_txEofF$ENQ,
pciw_pci0_txEofF$FULL_N;
// ports of submodule pciw_pci0_txExF
wire pciw_pci0_txExF$CLR,
pciw_pci0_txExF$DEQ,
pciw_pci0_txExF$D_IN,
pciw_pci0_txExF$EMPTY_N,
pciw_pci0_txExF$ENQ,
pciw_pci0_txExF$FULL_N;
// ports of submodule pciw_pci0_txHeadF
wire [30 : 0] pciw_pci0_txHeadF$D_IN, pciw_pci0_txHeadF$D_OUT;
wire pciw_pci0_txHeadF$CLR,
pciw_pci0_txHeadF$DEQ,
pciw_pci0_txHeadF$EMPTY_N,
pciw_pci0_txHeadF$ENQ,
pciw_pci0_txHeadF$FULL_N;
// ports of submodule pciw_pci0_txInF
wire [152 : 0] pciw_pci0_txInF$D_IN, pciw_pci0_txInF$D_OUT;
wire pciw_pci0_txInF$CLR,
pciw_pci0_txInF$DEQ,
pciw_pci0_txInF$EMPTY_N,
pciw_pci0_txInF$ENQ,
pciw_pci0_txInF$FULL_N;
// ports of submodule pciw_pci0_txOutF
wire [154 : 0] pciw_pci0_txOutF$D_IN, pciw_pci0_txOutF$D_OUT;
wire pciw_pci0_txOutF$CLR,
pciw_pci0_txOutF$DEQ,
pciw_pci0_txOutF$EMPTY_N,
pciw_pci0_txOutF$ENQ,
pciw_pci0_txOutF$FULL_N;
// rule scheduling signals
wire WILL_FIRE_RL_pciw_pci0_rxInF_reset,
WILL_FIRE_RL_pciw_pci0_rx_destage,
WILL_FIRE_RL_pciw_pci0_rx_enstage,
WILL_FIRE_RL_pciw_pci0_txOutF_reset,
WILL_FIRE_RL_pciw_pci0_tx_destage,
WILL_FIRE_RL_pciw_pci0_tx_enstage,
WILL_FIRE_RL_pciw_pci0_tx_exstage;
// inputs to muxes for submodule ports
wire MUX_pciw_pci0_rxInF_levelsValid$write_1__SEL_3;
// remaining internal signals
reg [15 : 0] IF_IF_IF_pciw_pci0_rxInFlight_76_THEN_pciw_pci_ETC___d787;
wire [255 : 0] _0_CONCAT_pciw_pci0_rxDws_new_data_wget__2_BITS_ETC___d832,
_0_CONCAT_pciw_pci0_txDws_new_data_wget__8_BITS_ETC___d833,
pciw_pci0_rxDws_vec_3_SRL_IF_pciw_pci0_rxDws_d_ETC___d834,
pciw_pci0_txDws_vec_9_SRL_IF_pciw_pci0_txDws_d_ETC___d835;
wire [127 : 0] x__h14478, x__h4523, x_data__h27615, x_data__h46011;
wire [95 : 0] IF_pciw_pci0_txInFlight_49_THEN_pciw_pci0_txDw_ETC___d481;
wire [31 : 0] IF_pciw_pci0_txHeadF_first__59_BIT_11_60_THEN__ETC___d468,
IF_pciw_pci0_txInFlight_49_THEN_pciw_pci0_txDw_ETC___d492,
pciw_pci0_pcie_ep_ava_debug__52_OR_0_CONCAT_pc_ETC___d831,
x__h56415,
x__h56417,
x__h56419,
x__h56421,
x__h56423,
x__h56425,
x__h56427,
x__h56429,
x__h56431,
x__h56433,
x__h56435,
x__h56437,
x__h56439,
x__h56441,
x__h56443,
x__h56445,
x__h56447,
x__h56449,
x__h56451,
y__h56416,
y__h56418,
y__h56420,
y__h56422,
y__h56424,
y__h56426,
y__h56428,
y__h56430,
y__h56432,
y__h56434,
y__h56436,
y__h56438,
y__h56440,
y__h56442,
y__h56444,
y__h56446,
y__h56448,
y__h56450,
y__h56452,
y__h56454;
wire [15 : 0] x_be__h27614;
wire [10 : 0] IF_IF_NOT_pciw_pci0_txInFlight_49_57_AND_NOT_I_ETC__q1,
IF_IF_pciw_pci0_rxInFlight_76_THEN_pciw_pci0_r_ETC__q2,
IF_NOT_pciw_pci0_txInFlight_49_57_AND_NOT_IF_p_ETC___d837,
IF_pciw_pci0_rxEofF_notEmpty__62_AND_pciw_pci0_ETC___d288,
IF_pciw_pci0_rxInFlight_76_THEN_pciw_pci0_rxDw_ETC___d769,
IF_pciw_pci0_txEofF_notEmpty__52_AND_pciw_pci0_ETC___d523,
IF_pciw_pci0_txInFlight_49_THEN_pciw_pci0_txDw_ETC___d838;
wire [8 : 0] x__h15731, x__h5776;
wire [7 : 0] INV_swReg_35_BIT_0_36_XOR_swReg_35_BIT_1_37_38_ETC___d764,
bar___1__h22106,
x__h18832,
x__h8877,
x_hit__h22096;
wire [2 : 0] IF_pciw_pci0_rxDws_delta_deq_whas__3_THEN_pciw_ETC___d801,
IF_pciw_pci0_rxDws_delta_enq_whas__8_THEN_pciw_ETC___d771,
IF_pciw_pci0_txDws_delta_deq_whas__9_THEN_pciw_ETC___d804,
IF_pciw_pci0_txDws_delta_enq_whas__4_THEN_pciw_ETC___d770;
wire NOT_pciw_pci0_txEofF_notEmpty__52_53_OR_NOT_pc_ETC___d495,
pciw_pci0_rxDws_num_full_7_ULE_4___d836,
pciw_pci0_txDws_num_full_3_ULE_4___d774,
pciw_pci0_txEofF_notEmpty__52_AND_pciw_pci0_tx_ETC___d817,
pciw_pci0_txOutF_i_notFull__48_AND_pciw_pci0_t_ETC___d502,
swParity__h48492,
z__h55844,
z__h55851,
z__h55858,
z__h55865,
z__h55872,
z__h55879,
z__h56129,
z__h56136,
z__h56143,
z__h56150,
z__h56157,
z__h56164,
z__h56171,
z__h56178,
z__h56185,
z__h56192,
z__h56199,
z__h56206,
z__h56213,
z__h56220,
z__h56227,
z__h56234,
z__h56241,
z__h56248,
z__h56255,
z__h56262,
z__h56269,
z__h56276,
z__h56283,
z__h56290,
z__h56297,
z__h56304,
z__h56311,
z__h56318,
z__h56325,
z__h56332;
// oscillator and gates for output clock p125clk
assign p125clk = pciw_pci0_pcie_ep$ava_core_clk_out ;
assign CLK_GATE_p125clk = 1'b1 ;
// output resets
assign p125rst = pciw_pci0_pcie_ep$ava_srstn ;
// value method pcie_tx
assign pcie_tx = pciw_pci0_pcie_ep$pcie_tx_out ;
// value method led
assign led = ledReg ;
// value method hsmc_out
assign hsmc_out = hsmcReg ;
// value method led_cathode
assign led_cathode = 20'd0 ;
// value method led_anode
assign led_anode = { 4'h8, ledReg } ;
// value method lcd_db
assign lcd_db = lcd_ctrl$db ;
// value method lcd_e
assign lcd_e = lcd_ctrl$e ;
// value method lcd_rs
assign lcd_rs = lcd_ctrl$rs ;
// value method lcd_rw
assign lcd_rw = lcd_ctrl$rw ;
// value method gps_ppsSyncOut
assign gps_ppsSyncOut = ctop$gps_ppsSyncOut ;
// value method flash_addr
assign flash_addr = flash0$flash_addr ;
// value method flash_ce_n
assign flash_ce_n = flash0$flash_ce_n ;
// value method flash_oe_n
assign flash_oe_n = flash0$flash_oe_n ;
// value method flash_we_n
assign flash_we_n = flash0$flash_we_n ;
// value method flash_wp_n
assign flash_wp_n = flash0$flash_wp_n ;
// value method flash_rst_n
assign flash_rst_n = flash0$flash_rst_n ;
// value method flash_adv_n
assign flash_adv_n = flash0$flash_adv_n ;
// value method dram_addr
assign dram_addr = dram0$dram_addr ;
// value method dram_ba
assign dram_ba = dram0$dram_ba ;
// value method dram_ras_n
assign dram_ras_n = dram0$dram_ras_n ;
// value method dram_cas_n
assign dram_cas_n = dram0$dram_cas_n ;
// value method dram_we_n
assign dram_we_n = dram0$dram_we_n ;
// value method dram_reset_n
assign dram_reset_n = dram0$dram_reset_n ;
// value method dram_cs_n
assign dram_cs_n = dram0$dram_cs_n ;
// value method dram_odt
assign dram_odt = dram0$dram_odt ;
// value method dram_cke
assign dram_cke = dram0$dram_cke ;
// value method dram_dm
assign dram_dm = dram0$dram_dm ;
// value method dram_ck_p
assign dram_ck_p = dram0$dram_ck_p ;
// value method dram_ck_n
assign dram_ck_n = dram0$dram_ck_n ;
// submodule ctop
mkCTop4B ctop(.pciDevice(pciDevice),
.CLK_sys0_clk(sys0_clk),
.RST_N_sys0_rst(sys0_rstn),
.CLK(pciw_pci0_pcie_ep$ava_core_clk_out),
.RST_N(pciw_pci0_pcie_ep$ava_srstn),
.cpServer_request_put(ctop$cpServer_request_put),
.gps_ppsSyncIn_x(ctop$gps_ppsSyncIn_x),
.server_request_put(ctop$server_request_put),
.switch_x(ctop$switch_x),
.wci_m_0_SData(ctop$wci_m_0_SData),
.wci_m_0_SFlag(ctop$wci_m_0_SFlag),
.wci_m_0_SResp(ctop$wci_m_0_SResp),
.wci_m_1_SData(ctop$wci_m_1_SData),
.wci_m_1_SFlag(ctop$wci_m_1_SFlag),
.wci_m_1_SResp(ctop$wci_m_1_SResp),
.wci_m_2_SData(ctop$wci_m_2_SData),
.wci_m_2_SFlag(ctop$wci_m_2_SFlag),
.wci_m_2_SResp(ctop$wci_m_2_SResp),
.wci_m_3_SData(ctop$wci_m_3_SData),
.wci_m_3_SFlag(ctop$wci_m_3_SFlag),
.wci_m_3_SResp(ctop$wci_m_3_SResp),
.wci_m_4_SData(ctop$wci_m_4_SData),
.wci_m_4_SFlag(ctop$wci_m_4_SFlag),
.wci_m_4_SResp(ctop$wci_m_4_SResp),
.wmemiM0_SData(ctop$wmemiM0_SData),
.wmemiM0_SResp(ctop$wmemiM0_SResp),
.wsi_s_adc_MBurstLength(ctop$wsi_s_adc_MBurstLength),
.wsi_s_adc_MByteEn(ctop$wsi_s_adc_MByteEn),
.wsi_s_adc_MCmd(ctop$wsi_s_adc_MCmd),
.wsi_s_adc_MData(ctop$wsi_s_adc_MData),
.wsi_s_adc_MReqInfo(ctop$wsi_s_adc_MReqInfo),
.EN_server_request_put(ctop$EN_server_request_put),
.EN_server_response_get(ctop$EN_server_response_get),
.EN_cpServer_request_put(ctop$EN_cpServer_request_put),
.EN_cpServer_response_get(ctop$EN_cpServer_response_get),
.wci_m_0_SThreadBusy(ctop$wci_m_0_SThreadBusy),
.wci_m_1_SThreadBusy(ctop$wci_m_1_SThreadBusy),
.wci_m_2_SThreadBusy(ctop$wci_m_2_SThreadBusy),
.wci_m_3_SThreadBusy(ctop$wci_m_3_SThreadBusy),
.wci_m_4_SThreadBusy(ctop$wci_m_4_SThreadBusy),
.wsi_s_adc_MReqLast(ctop$wsi_s_adc_MReqLast),
.wsi_s_adc_MBurstPrecise(ctop$wsi_s_adc_MBurstPrecise),
.wsi_s_adc_MReset_n(ctop$wsi_s_adc_MReset_n),
.wsi_m_dac_SThreadBusy(ctop$wsi_m_dac_SThreadBusy),
.wsi_m_dac_SReset_n(ctop$wsi_m_dac_SReset_n),
.wmemiM0_SRespLast(ctop$wmemiM0_SRespLast),
.wmemiM0_SCmdAccept(ctop$wmemiM0_SCmdAccept),
.wmemiM0_SDataAccept(ctop$wmemiM0_SDataAccept),
.RDY_server_request_put(ctop$RDY_server_request_put),
.server_response_get(ctop$server_response_get),
.RDY_server_response_get(ctop$RDY_server_response_get),
.RDY_cpServer_request_put(),
.cpServer_response_get(),
.RDY_cpServer_response_get(),
.led(ctop$led),
.wci_m_0_MCmd(),
.wci_m_0_MAddrSpace(),
.wci_m_0_MByteEn(),
.wci_m_0_MAddr(),
.wci_m_0_MData(),
.wci_m_0_MFlag(),
.wci_m_1_MCmd(ctop$wci_m_1_MCmd),
.wci_m_1_MAddrSpace(ctop$wci_m_1_MAddrSpace),
.wci_m_1_MByteEn(ctop$wci_m_1_MByteEn),
.wci_m_1_MAddr(ctop$wci_m_1_MAddr),
.wci_m_1_MData(ctop$wci_m_1_MData),
.wci_m_1_MFlag(ctop$wci_m_1_MFlag),
.wci_m_2_MCmd(),
.wci_m_2_MAddrSpace(),
.wci_m_2_MByteEn(),
.wci_m_2_MAddr(),
.wci_m_2_MData(),
.wci_m_2_MFlag(),
.wci_m_3_MCmd(),
.wci_m_3_MAddrSpace(),
.wci_m_3_MByteEn(),
.wci_m_3_MAddr(),
.wci_m_3_MData(),
.wci_m_3_MFlag(),
.wci_m_4_MCmd(ctop$wci_m_4_MCmd),
.wci_m_4_MAddrSpace(ctop$wci_m_4_MAddrSpace),
.wci_m_4_MByteEn(ctop$wci_m_4_MByteEn),
.wci_m_4_MAddr(ctop$wci_m_4_MAddr),
.wci_m_4_MData(ctop$wci_m_4_MData),
.wci_m_4_MFlag(ctop$wci_m_4_MFlag),
.cpNow(),
.RDY_cpNow(),
.wsi_s_adc_SThreadBusy(),
.wsi_s_adc_SReset_n(),
.wsi_m_dac_MCmd(),
.wsi_m_dac_MReqLast(),
.wsi_m_dac_MBurstPrecise(),
.wsi_m_dac_MBurstLength(),
.wsi_m_dac_MData(),
.wsi_m_dac_MByteEn(),
.wsi_m_dac_MReqInfo(),
.wsi_m_dac_MReset_n(),
.wmemiM0_MCmd(ctop$wmemiM0_MCmd),
.wmemiM0_MReqLast(ctop$wmemiM0_MReqLast),
.wmemiM0_MAddr(ctop$wmemiM0_MAddr),
.wmemiM0_MBurstLength(ctop$wmemiM0_MBurstLength),
.wmemiM0_MDataValid(ctop$wmemiM0_MDataValid),
.wmemiM0_MDataLast(ctop$wmemiM0_MDataLast),
.wmemiM0_MData(ctop$wmemiM0_MData),
.wmemiM0_MDataByteEn(ctop$wmemiM0_MDataByteEn),
.wmemiM0_MReset_n(ctop$wmemiM0_MReset_n),
.gps_ppsSyncOut(ctop$gps_ppsSyncOut),
.RST_N_wci_m_0(),
.RST_N_wci_m_1(ctop$RST_N_wci_m_1),
.RST_N_wci_m_2(),
.RST_N_wci_m_3(),
.RST_N_wci_m_4(ctop$RST_N_wci_m_4));
// submodule dram0
mkDramServer_s4 #(.hasDebugLogic(1'd0)) dram0(.CLK_sys0_clk(sys0_clk),
.RST_N_sys0_rstn(sys0_rstn),
.wciS0_Clk(pciw_pci0_pcie_ep$ava_core_clk_out),
.wciS0_MReset_n(ctop$RST_N_wci_m_4),
.dram_rdn_i(dram0$dram_rdn_i),
.dram_rup_i(dram0$dram_rup_i),
.wciS0_MAddr(dram0$wciS0_MAddr),
.wciS0_MAddrSpace(dram0$wciS0_MAddrSpace),
.wciS0_MByteEn(dram0$wciS0_MByteEn),
.wciS0_MCmd(dram0$wciS0_MCmd),
.wciS0_MData(dram0$wciS0_MData),
.wciS0_MFlag(dram0$wciS0_MFlag),
.wmemiS0_MAddr(dram0$wmemiS0_MAddr),
.wmemiS0_MBurstLength(dram0$wmemiS0_MBurstLength),
.wmemiS0_MCmd(dram0$wmemiS0_MCmd),
.wmemiS0_MData(dram0$wmemiS0_MData),
.wmemiS0_MDataByteEn(dram0$wmemiS0_MDataByteEn),
.wmemiS0_MReqLast(dram0$wmemiS0_MReqLast),
.wmemiS0_MDataValid(dram0$wmemiS0_MDataValid),
.wmemiS0_MDataLast(dram0$wmemiS0_MDataLast),
.wmemiS0_MReset_n(dram0$wmemiS0_MReset_n),
.wciS0_SResp(dram0$wciS0_SResp),
.wciS0_SData(dram0$wciS0_SData),
.wciS0_SThreadBusy(dram0$wciS0_SThreadBusy),
.wciS0_SFlag(dram0$wciS0_SFlag),
.wmemiS0_SResp(dram0$wmemiS0_SResp),
.wmemiS0_SRespLast(dram0$wmemiS0_SRespLast),
.wmemiS0_SData(dram0$wmemiS0_SData),
.wmemiS0_SCmdAccept(dram0$wmemiS0_SCmdAccept),
.wmemiS0_SDataAccept(dram0$wmemiS0_SDataAccept),
.dram_addr(dram0$dram_addr),
.dram_ba(dram0$dram_ba),
.dram_ras_n(dram0$dram_ras_n),
.dram_cas_n(dram0$dram_cas_n),
.dram_we_n(dram0$dram_we_n),
.dram_reset_n(dram0$dram_reset_n),
.dram_cs_n(dram0$dram_cs_n),
.dram_odt(dram0$dram_odt),
.dram_cke(dram0$dram_cke),
.dram_dm(dram0$dram_dm),
.dram_ck_p(dram0$dram_ck_p),
.dram_ck_n(dram0$dram_ck_n),
.dram_io_dq(dram_io_dq),
.dram_io_dqs_p(dram_io_dqs_p),
.dram_io_dqs_n(dram_io_dqs_n));
// submodule flash0
mkFlashWorker #(.hasDebugLogic(1'd1)) flash0(.wciS0_Clk(pciw_pci0_pcie_ep$ava_core_clk_out),
.wciS0_MReset_n(ctop$RST_N_wci_m_1),
.flash_fwait_i(flash0$flash_fwait_i),
.wciS0_MAddr(flash0$wciS0_MAddr),
.wciS0_MAddrSpace(flash0$wciS0_MAddrSpace),
.wciS0_MByteEn(flash0$wciS0_MByteEn),
.wciS0_MCmd(flash0$wciS0_MCmd),
.wciS0_MData(flash0$wciS0_MData),
.wciS0_MFlag(flash0$wciS0_MFlag),
.wciS0_SResp(flash0$wciS0_SResp),
.wciS0_SData(flash0$wciS0_SData),
.wciS0_SThreadBusy(flash0$wciS0_SThreadBusy),
.wciS0_SFlag(flash0$wciS0_SFlag),
.flash_addr(flash0$flash_addr),
.flash_ce_n(flash0$flash_ce_n),
.flash_oe_n(flash0$flash_oe_n),
.flash_we_n(flash0$flash_we_n),
.flash_wp_n(flash0$flash_wp_n),
.flash_rst_n(flash0$flash_rst_n),
.flash_adv_n(flash0$flash_adv_n),
.flash_io_dq(flash_io_dq));
// submodule lcd_ctrl
mkLCDController lcd_ctrl(.CLK(pciw_pci0_pcie_ep$ava_core_clk_out),
.RST_N(pciw_pci0_pcie_ep$ava_srstn),
.setLine1_text(lcd_ctrl$setLine1_text),
.setLine2_text(lcd_ctrl$setLine2_text),
.EN_setLine1(lcd_ctrl$EN_setLine1),
.EN_setLine2(lcd_ctrl$EN_setLine2),
.db(lcd_ctrl$db),
.e(lcd_ctrl$e),
.rs(lcd_ctrl$rs),
.rw(lcd_ctrl$rw));
// submodule pciw_aliveLed_sb
SyncBit #(.init(1'd0)) pciw_aliveLed_sb(.sCLK(sys0_clk),
.dCLK(pciw_pci0_pcie_ep$ava_core_clk_out),
.sRST(sys0_rstn),
.sD_IN(pciw_aliveLed_sb$sD_IN),
.sEN(pciw_aliveLed_sb$sEN),
.dD_OUT(pciw_aliveLed_sb$dD_OUT));
// submodule pciw_i2pF
FIFO2 #(.width(32'd153),
.guarded(32'd1)) pciw_i2pF(.RST(pciw_pci0_pcie_ep$ava_srstn),
.CLK(pciw_pci0_pcie_ep$ava_core_clk_out),
.D_IN(pciw_i2pF$D_IN),
.ENQ(pciw_i2pF$ENQ),
.DEQ(pciw_i2pF$DEQ),
.CLR(pciw_i2pF$CLR),
.D_OUT(pciw_i2pF$D_OUT),
.FULL_N(pciw_i2pF$FULL_N),
.EMPTY_N(pciw_i2pF$EMPTY_N));
// submodule pciw_linkLed_sb
SyncBit #(.init(1'd0)) pciw_linkLed_sb(.sCLK(sys0_clk),
.dCLK(pciw_pci0_pcie_ep$ava_core_clk_out),
.sRST(sys0_rstn),
.sD_IN(pciw_linkLed_sb$sD_IN),
.sEN(pciw_linkLed_sb$sEN),
.dD_OUT(pciw_linkLed_sb$dD_OUT));
// submodule pciw_p2iF
FIFO2 #(.width(32'd153),
.guarded(32'd1)) pciw_p2iF(.RST(pciw_pci0_pcie_ep$ava_srstn),
.CLK(pciw_pci0_pcie_ep$ava_core_clk_out),
.D_IN(pciw_p2iF$D_IN),
.ENQ(pciw_p2iF$ENQ),
.DEQ(pciw_p2iF$DEQ),
.CLR(pciw_p2iF$CLR),
.D_OUT(pciw_p2iF$D_OUT),
.FULL_N(pciw_p2iF$FULL_N),
.EMPTY_N(pciw_p2iF$EMPTY_N));
// submodule pciw_pci0_pcie_ep
pcie_hip_s4gx_gen2_x4_128_wrapper pciw_pci0_pcie_ep(.sys0_clk(sys0_clk),
.sys0_rstn(sys0_rstn),
.pcie_clk(pcie_clk),
.pcie_rstn(pcie_rstn),
.pcie_rx_in(pciw_pci0_pcie_ep$pcie_rx_in),
.rx_st_mask0(pciw_pci0_pcie_ep$rx_st_mask0),
.rx_st_ready0(pciw_pci0_pcie_ep$rx_st_ready0),
.tx_st_data0(pciw_pci0_pcie_ep$tx_st_data0),
.tx_st_empty0(pciw_pci0_pcie_ep$tx_st_empty0),
.tx_st_eop0(pciw_pci0_pcie_ep$tx_st_eop0),
.tx_st_err0(pciw_pci0_pcie_ep$tx_st_err0),
.tx_st_sop0(pciw_pci0_pcie_ep$tx_st_sop0),
.tx_st_valid0(pciw_pci0_pcie_ep$tx_st_valid0),
.tl_cfg_add(pciw_pci0_pcie_ep$tl_cfg_add),
.tl_cfg_ctl(pciw_pci0_pcie_ep$tl_cfg_ctl),
.tl_cfg_ctl_wr(pciw_pci0_pcie_ep$tl_cfg_ctl_wr),
.tl_cfg_sts(),
.tl_cfg_sts_wr(),
.pcie_tx_out(pciw_pci0_pcie_ep$pcie_tx_out),
.ava_alive(pciw_pci0_pcie_ep$ava_alive),
.ava_lnk_up(pciw_pci0_pcie_ep$ava_lnk_up),
.ava_debug(pciw_pci0_pcie_ep$ava_debug),
.rx_st_valid0(pciw_pci0_pcie_ep$rx_st_valid0),
.rx_st_bardec0(pciw_pci0_pcie_ep$rx_st_bardec0),
.rx_st_be0(pciw_pci0_pcie_ep$rx_st_be0),
.rx_st_data0(pciw_pci0_pcie_ep$rx_st_data0),
.rx_st_sop0(pciw_pci0_pcie_ep$rx_st_sop0),
.rx_st_eop0(pciw_pci0_pcie_ep$rx_st_eop0),
.rx_st_empty0(pciw_pci0_pcie_ep$rx_st_empty0),
.rx_st_err0(),
.tx_st_ready0(pciw_pci0_pcie_ep$tx_st_ready0),
.tx_cred0(),
.tx_fifo_empty0(),
.ava_core_clk_out(pciw_pci0_pcie_ep$ava_core_clk_out),
.ava_srstn(pciw_pci0_pcie_ep$ava_srstn));
// submodule pciw_pci0_rxEofF
FIFO2 #(.width(32'd3),
.guarded(32'd1)) pciw_pci0_rxEofF(.RST(pciw_pci0_pcie_ep$ava_srstn),
.CLK(pciw_pci0_pcie_ep$ava_core_clk_out),
.D_IN(pciw_pci0_rxEofF$D_IN),
.ENQ(pciw_pci0_rxEofF$ENQ),
.DEQ(pciw_pci0_rxEofF$DEQ),
.CLR(pciw_pci0_rxEofF$CLR),
.D_OUT(),
.FULL_N(pciw_pci0_rxEofF$FULL_N),
.EMPTY_N(pciw_pci0_rxEofF$EMPTY_N));
// submodule pciw_pci0_rxHeadF
FIFO2 #(.width(32'd31),
.guarded(32'd1)) pciw_pci0_rxHeadF(.RST(pciw_pci0_pcie_ep$ava_srstn),
.CLK(pciw_pci0_pcie_ep$ava_core_clk_out),
.D_IN(pciw_pci0_rxHeadF$D_IN),
.ENQ(pciw_pci0_rxHeadF$ENQ),
.DEQ(pciw_pci0_rxHeadF$DEQ),
.CLR(pciw_pci0_rxHeadF$CLR),
.D_OUT(pciw_pci0_rxHeadF$D_OUT),
.FULL_N(pciw_pci0_rxHeadF$FULL_N),
.EMPTY_N(pciw_pci0_rxHeadF$EMPTY_N));
// submodule pciw_pci0_rxInF
SizedFIFO #(.p1width(32'd155),
.p2depth(32'd32),
.p3cntr_width(32'd5),
.guarded(32'd1)) pciw_pci0_rxInF(.RST(pciw_pci0_pcie_ep$ava_srstn),
.CLK(pciw_pci0_pcie_ep$ava_core_clk_out),
.D_IN(pciw_pci0_rxInF$D_IN),
.ENQ(pciw_pci0_rxInF$ENQ),
.DEQ(pciw_pci0_rxInF$DEQ),
.CLR(pciw_pci0_rxInF$CLR),
.D_OUT(pciw_pci0_rxInF$D_OUT),
.FULL_N(pciw_pci0_rxInF$FULL_N),
.EMPTY_N(pciw_pci0_rxInF$EMPTY_N));
// submodule pciw_pci0_rxOutF
FIFO2 #(.width(32'd153),
.guarded(32'd1)) pciw_pci0_rxOutF(.RST(pciw_pci0_pcie_ep$ava_srstn),
.CLK(pciw_pci0_pcie_ep$ava_core_clk_out),
.D_IN(pciw_pci0_rxOutF$D_IN),
.ENQ(pciw_pci0_rxOutF$ENQ),
.DEQ(pciw_pci0_rxOutF$DEQ),
.CLR(pciw_pci0_rxOutF$CLR),
.D_OUT(pciw_pci0_rxOutF$D_OUT),
.FULL_N(pciw_pci0_rxOutF$FULL_N),
.EMPTY_N(pciw_pci0_rxOutF$EMPTY_N));
// submodule pciw_pci0_txEofF
FIFO2 #(.width(32'd3),
.guarded(32'd1)) pciw_pci0_txEofF(.RST(pciw_pci0_pcie_ep$ava_srstn),
.CLK(pciw_pci0_pcie_ep$ava_core_clk_out),
.D_IN(pciw_pci0_txEofF$D_IN),
.ENQ(pciw_pci0_txEofF$ENQ),
.DEQ(pciw_pci0_txEofF$DEQ),
.CLR(pciw_pci0_txEofF$CLR),
.D_OUT(),
.FULL_N(pciw_pci0_txEofF$FULL_N),
.EMPTY_N(pciw_pci0_txEofF$EMPTY_N));
// submodule pciw_pci0_txExF
FIFO2 #(.width(32'd1),
.guarded(32'd1)) pciw_pci0_txExF(.RST(pciw_pci0_pcie_ep$ava_srstn),
.CLK(pciw_pci0_pcie_ep$ava_core_clk_out),
.D_IN(pciw_pci0_txExF$D_IN),
.ENQ(pciw_pci0_txExF$ENQ),
.DEQ(pciw_pci0_txExF$DEQ),
.CLR(pciw_pci0_txExF$CLR),
.D_OUT(),
.FULL_N(pciw_pci0_txExF$FULL_N),
.EMPTY_N(pciw_pci0_txExF$EMPTY_N));
// submodule pciw_pci0_txHeadF
FIFO2 #(.width(32'd31),
.guarded(32'd1)) pciw_pci0_txHeadF(.RST(pciw_pci0_pcie_ep$ava_srstn),
.CLK(pciw_pci0_pcie_ep$ava_core_clk_out),
.D_IN(pciw_pci0_txHeadF$D_IN),
.ENQ(pciw_pci0_txHeadF$ENQ),
.DEQ(pciw_pci0_txHeadF$DEQ),
.CLR(pciw_pci0_txHeadF$CLR),
.D_OUT(pciw_pci0_txHeadF$D_OUT),
.FULL_N(pciw_pci0_txHeadF$FULL_N),
.EMPTY_N(pciw_pci0_txHeadF$EMPTY_N));
// submodule pciw_pci0_txInF
FIFO2 #(.width(32'd153),
.guarded(32'd1)) pciw_pci0_txInF(.RST(pciw_pci0_pcie_ep$ava_srstn),
.CLK(pciw_pci0_pcie_ep$ava_core_clk_out),
.D_IN(pciw_pci0_txInF$D_IN),
.ENQ(pciw_pci0_txInF$ENQ),
.DEQ(pciw_pci0_txInF$DEQ),
.CLR(pciw_pci0_txInF$CLR),
.D_OUT(pciw_pci0_txInF$D_OUT),
.FULL_N(pciw_pci0_txInF$FULL_N),
.EMPTY_N(pciw_pci0_txInF$EMPTY_N));
// submodule pciw_pci0_txOutF
SizedFIFO #(.p1width(32'd155),
.p2depth(32'd515),
.p3cntr_width(32'd10),
.guarded(32'd1)) pciw_pci0_txOutF(.RST(pciw_pci0_pcie_ep$ava_srstn),
.CLK(pciw_pci0_pcie_ep$ava_core_clk_out),
.D_IN(pciw_pci0_txOutF$D_IN),
.ENQ(pciw_pci0_txOutF$ENQ),
.DEQ(pciw_pci0_txOutF$DEQ),
.CLR(pciw_pci0_txOutF$CLR),
.D_OUT(pciw_pci0_txOutF$D_OUT),
.FULL_N(pciw_pci0_txOutF$FULL_N),
.EMPTY_N(pciw_pci0_txOutF$EMPTY_N));
// rule RL_pciw_pci0_rx_destage
assign WILL_FIRE_RL_pciw_pci0_rx_destage =
pciw_pci0_rxDws_num_full != 4'd0 && pciw_pci0_rxHeadF$EMPTY_N &&
pciw_pci0_rxOutF$FULL_N &&
(pciw_pci0_rxDws_num_full >= 4'd4 || pciw_pci0_rxEofF$EMPTY_N) ;
// rule RL_pciw_pci0_rx_enstage
assign WILL_FIRE_RL_pciw_pci0_rx_enstage =
pciw_pci0_rxInF$EMPTY_N &&
(!pciw_pci0_rxInF$D_OUT[153] || pciw_pci0_rxHeadF$FULL_N) &&
(!pciw_pci0_rxInF$D_OUT[152] || pciw_pci0_rxEofF$FULL_N) &&
pciw_pci0_rxDws_num_empty >= 4'd4 ;
// rule RL_pciw_pci0_tx_exstage
assign WILL_FIRE_RL_pciw_pci0_tx_exstage =
pciw_pci0_txOutF$EMPTY_N && pciw_pci0_txReadyD &&
pciw_pci0_txExF$EMPTY_N ;
// rule RL_pciw_pci0_tx_destage
assign WILL_FIRE_RL_pciw_pci0_tx_destage =
pciw_pci0_txDws_num_full != 4'd0 &&
pciw_pci0_txOutF_i_notFull__48_AND_pciw_pci0_t_ETC___d502 &&
(pciw_pci0_txDws_num_full >= 4'd4 || pciw_pci0_txEofF$EMPTY_N) ;
// rule RL_pciw_pci0_tx_enstage
assign WILL_FIRE_RL_pciw_pci0_tx_enstage =
pciw_pci0_txInF$EMPTY_N &&
(!pciw_pci0_txInF$D_OUT[152] || pciw_pci0_txHeadF$FULL_N) &&
(!pciw_pci0_txInF$D_OUT[151] || pciw_pci0_txEofF$FULL_N) &&
pciw_pci0_txDws_num_empty >= 4'd4 ;
// rule RL_pciw_pci0_rxInF_reset
assign WILL_FIRE_RL_pciw_pci0_rxInF_reset =
MUX_pciw_pci0_rxInF_levelsValid$write_1__SEL_3 ||
WILL_FIRE_RL_pciw_pci0_rx_enstage ;
// rule RL_pciw_pci0_txOutF_reset
assign WILL_FIRE_RL_pciw_pci0_txOutF_reset =
WILL_FIRE_RL_pciw_pci0_tx_destage ||
WILL_FIRE_RL_pciw_pci0_tx_exstage ;
// inputs to muxes for submodule ports
assign MUX_pciw_pci0_rxInF_levelsValid$write_1__SEL_3 =
pciw_pci0_rxInF$FULL_N && pciw_pci0_pcie_ep$rx_st_valid0 ;
// inlined wires
assign pciw_pci0_avaTxValid$wget = 1'd1 ;
assign pciw_pci0_avaTxValid$whas = WILL_FIRE_RL_pciw_pci0_tx_exstage ;
assign pciw_pci0_avaTxErr$wget = 1'b0 ;
assign pciw_pci0_avaTxErr$whas = 1'b0 ;
assign pciw_pci0_avaTxSop$wget = pciw_pci0_txOutF$D_OUT[153] ;
assign pciw_pci0_avaTxSop$whas = WILL_FIRE_RL_pciw_pci0_tx_exstage ;
assign pciw_pci0_avaTxEop$wget = pciw_pci0_txOutF$D_OUT[152] ;
assign pciw_pci0_avaTxEop$whas = WILL_FIRE_RL_pciw_pci0_tx_exstage ;
assign pciw_pci0_avaTxEmpty$wget = pciw_pci0_txOutF$D_OUT[154] ;
assign pciw_pci0_avaTxEmpty$whas = WILL_FIRE_RL_pciw_pci0_tx_exstage ;
assign pciw_pci0_rxDws_delta_enq$wget =
(pciw_pci0_rxInF$D_OUT[153] && !pciw_pci0_rxInF$D_OUT[30] &&
!pciw_pci0_rxInF$D_OUT[29]) ?
3'd3 :
((pciw_pci0_rxInF$D_OUT[153] &&
(pciw_pci0_rxInF$D_OUT[29] ||
pciw_pci0_rxInF$D_OUT[30] && pciw_pci0_rxInF$D_OUT[66])) ?
3'd4 :
((pciw_pci0_rxInF$D_OUT[153] && pciw_pci0_rxInF$D_OUT[30] &&
!pciw_pci0_rxInF$D_OUT[29] &&
!pciw_pci0_rxInF$D_OUT[66]) ?
3'd3 :
((!pciw_pci0_rxInF$D_OUT[153] &&
!pciw_pci0_rxInF$D_OUT[154] &&
pciw_pci0_rxInF$D_OUT[143:128] == 16'hFFFF) ?
3'd4 :
((!pciw_pci0_rxInF$D_OUT[153] &&
!pciw_pci0_rxInF$D_OUT[154] &&
pciw_pci0_rxInF$D_OUT[143:128] == 16'h0FFF) ?
3'd3 :
((!pciw_pci0_rxInF$D_OUT[153] &&
pciw_pci0_rxInF$D_OUT[154] &&
pciw_pci0_rxInF$D_OUT[143:136] == 8'hFF) ?
3'd2 :
((!pciw_pci0_rxInF$D_OUT[153] &&
pciw_pci0_rxInF$D_OUT[154] &&
pciw_pci0_rxInF$D_OUT[143:136] == 8'h0F) ?
3'd1 :
3'd0)))))) ;
assign pciw_pci0_rxDws_delta_enq$whas = WILL_FIRE_RL_pciw_pci0_rx_enstage ;
assign pciw_pci0_rxDws_delta_deq$wget =
IF_IF_pciw_pci0_rxInFlight_76_THEN_pciw_pci0_r_ETC__q2[2:0] ;
assign pciw_pci0_rxDws_delta_deq$whas = WILL_FIRE_RL_pciw_pci0_rx_destage ;
assign pciw_pci0_rxDws_new_data$wget =
pciw_pci0_rxInF$D_OUT[153] ?
{ pciw_pci0_rxInF$D_OUT[29] ?
{ pciw_pci0_rxInF$D_OUT[103:96],
pciw_pci0_rxInF$D_OUT[111:104],
pciw_pci0_rxInF$D_OUT[119:112],
pciw_pci0_rxInF$D_OUT[127:120] } :
pciw_pci0_rxInF$D_OUT[127:96],
pciw_pci0_rxInF$D_OUT[71:64],
pciw_pci0_rxInF$D_OUT[79:72],
pciw_pci0_rxInF$D_OUT[87:80],
pciw_pci0_rxInF$D_OUT[95:88],
pciw_pci0_rxInF$D_OUT[39:32],
pciw_pci0_rxInF$D_OUT[47:40],
pciw_pci0_rxInF$D_OUT[55:48],
pciw_pci0_rxInF$D_OUT[63:56],
pciw_pci0_rxInF$D_OUT[7:0],
pciw_pci0_rxInF$D_OUT[15:8],
pciw_pci0_rxInF$D_OUT[23:16],
pciw_pci0_rxInF$D_OUT[31:24] } :
pciw_pci0_rxInF$D_OUT[127:0] ;
assign pciw_pci0_rxDws_new_data$whas = WILL_FIRE_RL_pciw_pci0_rx_enstage ;
assign pciw_pci0_txDws_delta_enq$wget =
(pciw_pci0_txInF$D_OUT[152] && !pciw_pci0_txInF$D_OUT[126] &&
!pciw_pci0_txInF$D_OUT[125]) ?
3'd3 :
((pciw_pci0_txInF$D_OUT[152] &&
(pciw_pci0_txInF$D_OUT[125] ||
pciw_pci0_txInF$D_OUT[126] &&
pciw_pci0_txInF$D_OUT[143:128] == 16'hFFFF)) ?
3'd4 :
((pciw_pci0_txInF$D_OUT[152] &&
pciw_pci0_txInF$D_OUT[126] &&
!pciw_pci0_txInF$D_OUT[125] &&
pciw_pci0_txInF$D_OUT[143:128] == 16'hFFF0) ?
3'd3 :
((!pciw_pci0_txInF$D_OUT[152] &&
pciw_pci0_txInF$D_OUT[143:128] == 16'hFFFF) ?
3'd4 :
((!pciw_pci0_txInF$D_OUT[152] &&
pciw_pci0_txInF$D_OUT[143:128] == 16'hFFF0) ?
3'd3 :
((!pciw_pci0_txInF$D_OUT[152] &&
pciw_pci0_txInF$D_OUT[143:128] == 16'hFF00) ?
3'd2 :
((!pciw_pci0_txInF$D_OUT[152] &&
pciw_pci0_txInF$D_OUT[143:128] == 16'hF000) ?
3'd1 :
3'd0)))))) ;
assign pciw_pci0_txDws_delta_enq$whas = WILL_FIRE_RL_pciw_pci0_tx_enstage ;
assign pciw_pci0_txDws_delta_deq$wget =
IF_IF_NOT_pciw_pci0_txInFlight_49_57_AND_NOT_I_ETC__q1[2:0] ;
assign pciw_pci0_txDws_delta_deq$whas = WILL_FIRE_RL_pciw_pci0_tx_destage ;
assign pciw_pci0_txDws_new_data$wget =
{ pciw_pci0_txInF$D_OUT[7:0],
pciw_pci0_txInF$D_OUT[15:8],
pciw_pci0_txInF$D_OUT[23:16],
pciw_pci0_txInF$D_OUT[31:24],
pciw_pci0_txInF$D_OUT[39:32],
pciw_pci0_txInF$D_OUT[47:40],
pciw_pci0_txInF$D_OUT[55:48],
pciw_pci0_txInF$D_OUT[63:56],
pciw_pci0_txInF$D_OUT[71:64],
pciw_pci0_txInF$D_OUT[79:72],
pciw_pci0_txInF$D_OUT[87:80],
pciw_pci0_txInF$D_OUT[95:88],
pciw_pci0_txInF$D_OUT[103:96],
pciw_pci0_txInF$D_OUT[111:104],
pciw_pci0_txInF$D_OUT[119:112],
pciw_pci0_txInF$D_OUT[127:120] } ;
assign pciw_pci0_txDws_new_data$whas = WILL_FIRE_RL_pciw_pci0_tx_enstage ;
assign pciw_pci0_rxInF_r_enq$whas =
MUX_pciw_pci0_rxInF_levelsValid$write_1__SEL_3 ;
assign pciw_pci0_rxInF_r_deq$whas = WILL_FIRE_RL_pciw_pci0_rx_enstage ;
assign pciw_pci0_rxInF_r_clr$whas = 1'b0 ;
assign pciw_pci0_rxInF_doResetEnq$whas =
MUX_pciw_pci0_rxInF_levelsValid$write_1__SEL_3 ;
assign pciw_pci0_rxInF_doResetDeq$whas = WILL_FIRE_RL_pciw_pci0_rx_enstage ;
assign pciw_pci0_rxInF_doResetClr$whas = 1'b0 ;
assign pciw_pci0_txOutF_r_enq$whas = WILL_FIRE_RL_pciw_pci0_tx_destage ;
assign pciw_pci0_txOutF_r_deq$whas = WILL_FIRE_RL_pciw_pci0_tx_exstage ;
assign pciw_pci0_txOutF_r_clr$whas = 1'b0 ;
assign pciw_pci0_txOutF_doResetEnq$whas =
WILL_FIRE_RL_pciw_pci0_tx_destage ;
assign pciw_pci0_txOutF_doResetDeq$whas =
WILL_FIRE_RL_pciw_pci0_tx_exstage ;
assign pciw_pci0_txOutF_doResetClr$whas = 1'b0 ;
assign infLed$wget = ctop$led ;
// register freeCnt
assign freeCnt$D_IN = freeCnt + 32'd1 ;
assign freeCnt$EN = 1'd1 ;
// register hsmcReg
assign hsmcReg$D_IN = hsmc_in_i ;
assign hsmcReg$EN = 1'd1 ;
// register ledReg
assign ledReg$D_IN =
{ 6'd31,
~ctop$led,
INV_swReg_35_BIT_0_36_XOR_swReg_35_BIT_1_37_38_ETC___d764 } ;
assign ledReg$EN = 1'd1 ;
// register needs_init
assign needs_init$D_IN = 1'd0 ;
assign needs_init$EN = needs_init ;
// register pciDevice
assign pciDevice$D_IN = pciw_pciDevice ;
assign pciDevice$EN = 1'd1 ;
// register pciw_pci0_cfgDataWr
assign pciw_pci0_cfgDataWr$D_IN = pciw_pci0_pcie_ep$tl_cfg_ctl_wr ;
assign pciw_pci0_cfgDataWr$EN = 1'd1 ;
// register pciw_pci0_cfgSample
assign pciw_pci0_cfgSample$D_IN =
pciw_pci0_cfgDataWr != pciw_pci0_pcie_ep$tl_cfg_ctl_wr ;
assign pciw_pci0_cfgSample$EN = 1'd1 ;
// register pciw_pci0_deviceReg
assign pciw_pci0_deviceReg$D_IN =
{ pciw_pci0_pcie_ep$tl_cfg_ctl[12:0], 3'd0 } ;
assign pciw_pci0_deviceReg$EN =
pciw_pci0_cfgSample && pciw_pci0_pcie_ep$tl_cfg_add == 4'hF ;
// register pciw_pci0_rxDbgDeDeq
assign pciw_pci0_rxDbgDeDeq$D_IN =
pciw_pci0_rxDbgDeDeq +
{ 13'd0,
IF_IF_pciw_pci0_rxInFlight_76_THEN_pciw_pci0_r_ETC__q2[2:0] } ;
assign pciw_pci0_rxDbgDeDeq$EN = WILL_FIRE_RL_pciw_pci0_rx_destage ;
// register pciw_pci0_rxDbgDeEof
assign pciw_pci0_rxDbgDeEof$D_IN = pciw_pci0_rxDbgDeEof + 16'd1 ;
assign pciw_pci0_rxDbgDeEof$EN =
WILL_FIRE_RL_pciw_pci0_rx_destage && pciw_pci0_rxEofF$EMPTY_N &&
pciw_pci0_rxDws_num_full_7_ULE_4___d836 ;
// register pciw_pci0_rxDbgDeSof
assign pciw_pci0_rxDbgDeSof$D_IN = pciw_pci0_rxDbgDeSof + 16'd1 ;
assign pciw_pci0_rxDbgDeSof$EN =
WILL_FIRE_RL_pciw_pci0_rx_destage && !pciw_pci0_rxInFlight ;
// register pciw_pci0_rxDbgDestage
assign pciw_pci0_rxDbgDestage$D_IN = pciw_pci0_rxDbgDestage + 16'd1 ;
assign pciw_pci0_rxDbgDestage$EN = WILL_FIRE_RL_pciw_pci0_rx_destage ;
// register pciw_pci0_rxDbgEnEnq
assign pciw_pci0_rxDbgEnEnq$D_IN =
pciw_pci0_rxDbgEnEnq +
{ 13'd0,
(pciw_pci0_rxInF$D_OUT[153] && !pciw_pci0_rxInF$D_OUT[30] &&
!pciw_pci0_rxInF$D_OUT[29]) ?
3'd3 :
((pciw_pci0_rxInF$D_OUT[153] &&
(pciw_pci0_rxInF$D_OUT[29] ||
pciw_pci0_rxInF$D_OUT[30] && pciw_pci0_rxInF$D_OUT[66])) ?
3'd4 :
((pciw_pci0_rxInF$D_OUT[153] &&
pciw_pci0_rxInF$D_OUT[30] &&
!pciw_pci0_rxInF$D_OUT[29] &&
!pciw_pci0_rxInF$D_OUT[66]) ?
3'd3 :
((!pciw_pci0_rxInF$D_OUT[153] &&
!pciw_pci0_rxInF$D_OUT[154] &&
pciw_pci0_rxInF$D_OUT[143:128] == 16'hFFFF) ?
3'd4 :
((!pciw_pci0_rxInF$D_OUT[153] &&
!pciw_pci0_rxInF$D_OUT[154] &&
pciw_pci0_rxInF$D_OUT[143:128] == 16'h0FFF) ?
3'd3 :
((!pciw_pci0_rxInF$D_OUT[153] &&
pciw_pci0_rxInF$D_OUT[154] &&
pciw_pci0_rxInF$D_OUT[143:136] == 8'hFF) ?
3'd2 :
((!pciw_pci0_rxInF$D_OUT[153] &&
pciw_pci0_rxInF$D_OUT[154] &&
pciw_pci0_rxInF$D_OUT[143:136] == 8'h0F) ?
3'd1 :
3'd0)))))) } ;
assign pciw_pci0_rxDbgEnEnq$EN = WILL_FIRE_RL_pciw_pci0_rx_enstage ;
// register pciw_pci0_rxDbgEnEof
assign pciw_pci0_rxDbgEnEof$D_IN = pciw_pci0_rxDbgEnEof + 16'd1 ;
assign pciw_pci0_rxDbgEnEof$EN =
WILL_FIRE_RL_pciw_pci0_rx_enstage && pciw_pci0_rxInF$D_OUT[152] ;
// register pciw_pci0_rxDbgEnSof
assign pciw_pci0_rxDbgEnSof$D_IN = pciw_pci0_rxDbgEnSof + 16'd1 ;
assign pciw_pci0_rxDbgEnSof$EN =
WILL_FIRE_RL_pciw_pci0_rx_enstage && pciw_pci0_rxInF$D_OUT[153] ;
// register pciw_pci0_rxDbgEnstage
assign pciw_pci0_rxDbgEnstage$D_IN = pciw_pci0_rxDbgEnstage + 16'd1 ;
assign pciw_pci0_rxDbgEnstage$EN = WILL_FIRE_RL_pciw_pci0_rx_enstage ;
// register pciw_pci0_rxDbgInstage
assign pciw_pci0_rxDbgInstage$D_IN = pciw_pci0_rxDbgInstage + 16'd1 ;
assign pciw_pci0_rxDbgInstage$EN =
MUX_pciw_pci0_rxInF_levelsValid$write_1__SEL_3 ;
// register pciw_pci0_rxDwrDeq
assign pciw_pci0_rxDwrDeq$D_IN =
pciw_pci0_rxInFlight ?
pciw_pci0_rxDwrDeq -
{ 8'd0,
IF_IF_pciw_pci0_rxInFlight_76_THEN_pciw_pci0_r_ETC__q2[2:0] } :
IF_pciw_pci0_rxEofF_notEmpty__62_AND_pciw_pci0_ETC___d288 ;
assign pciw_pci0_rxDwrDeq$EN = WILL_FIRE_RL_pciw_pci0_rx_destage ;
// register pciw_pci0_rxDwrEnq
assign pciw_pci0_rxDwrEnq$D_IN = 11'h0 ;
assign pciw_pci0_rxDwrEnq$EN = 1'b0 ;
// register pciw_pci0_rxDws_num_empty
assign pciw_pci0_rxDws_num_empty$D_IN =
pciw_pci0_rxDws_num_empty +
{ 1'd0,
IF_pciw_pci0_rxDws_delta_deq_whas__3_THEN_pciw_ETC___d801 } -
{ 1'd0,
IF_pciw_pci0_rxDws_delta_enq_whas__8_THEN_pciw_ETC___d771 } ;
assign pciw_pci0_rxDws_num_empty$EN = 1'd1 ;
// register pciw_pci0_rxDws_num_full
assign pciw_pci0_rxDws_num_full$D_IN =
pciw_pci0_rxDws_num_full +
{ 1'd0,
IF_pciw_pci0_rxDws_delta_enq_whas__8_THEN_pciw_ETC___d771 } -
{ 1'd0,
IF_pciw_pci0_rxDws_delta_deq_whas__3_THEN_pciw_ETC___d801 } ;
assign pciw_pci0_rxDws_num_full$EN = 1'd1 ;
// register pciw_pci0_rxDws_vec
assign pciw_pci0_rxDws_vec$D_IN =
{ (WILL_FIRE_RL_pciw_pci0_rx_enstage ?
_0_CONCAT_pciw_pci0_rxDws_new_data_wget__2_BITS_ETC___d832[255:32] :
224'd0) |
pciw_pci0_rxDws_vec_3_SRL_IF_pciw_pci0_rxDws_d_ETC___d834[255:32],
(WILL_FIRE_RL_pciw_pci0_rx_enstage ?
_0_CONCAT_pciw_pci0_rxDws_new_data_wget__2_BITS_ETC___d832[31:0] :
32'd0) |
pciw_pci0_rxDws_vec_3_SRL_IF_pciw_pci0_rxDws_d_ETC___d834[31:0] } ;
assign pciw_pci0_rxDws_vec$EN = 1'd1 ;
// register pciw_pci0_rxInF_countReg
assign pciw_pci0_rxInF_countReg$D_IN =
MUX_pciw_pci0_rxInF_levelsValid$write_1__SEL_3 ?
pciw_pci0_rxInF_countReg + 6'd1 :
pciw_pci0_rxInF_countReg - 6'd1 ;
assign pciw_pci0_rxInF_countReg$EN =
MUX_pciw_pci0_rxInF_levelsValid$write_1__SEL_3 !=
WILL_FIRE_RL_pciw_pci0_rx_enstage ;
// register pciw_pci0_rxInF_levelsValid
assign pciw_pci0_rxInF_levelsValid$D_IN =
WILL_FIRE_RL_pciw_pci0_rxInF_reset ;
assign pciw_pci0_rxInF_levelsValid$EN =
WILL_FIRE_RL_pciw_pci0_rx_enstage ||
pciw_pci0_rxInF$FULL_N && pciw_pci0_pcie_ep$rx_st_valid0 ||
WILL_FIRE_RL_pciw_pci0_rxInF_reset ;
// register pciw_pci0_rxInFlight
assign pciw_pci0_rxInFlight$D_IN =
!pciw_pci0_rxEofF$EMPTY_N ||
!pciw_pci0_rxDws_num_full_7_ULE_4___d836 ;
assign pciw_pci0_rxInFlight$EN = WILL_FIRE_RL_pciw_pci0_rx_destage ;
// register pciw_pci0_txDbgDeDeq
assign pciw_pci0_txDbgDeDeq$D_IN =
pciw_pci0_txDbgDeDeq +
{ 13'd0,
IF_IF_NOT_pciw_pci0_txInFlight_49_57_AND_NOT_I_ETC__q1[2:0] } ;
assign pciw_pci0_txDbgDeDeq$EN = WILL_FIRE_RL_pciw_pci0_tx_destage ;
// register pciw_pci0_txDbgDeEof
assign pciw_pci0_txDbgDeEof$D_IN = pciw_pci0_txDbgDeEof + 16'd1 ;
assign pciw_pci0_txDbgDeEof$EN =
WILL_FIRE_RL_pciw_pci0_tx_destage &&
pciw_pci0_txEofF_notEmpty__52_AND_pciw_pci0_tx_ETC___d817 ;
// register pciw_pci0_txDbgDeSof
assign pciw_pci0_txDbgDeSof$D_IN = pciw_pci0_txDbgDeSof + 16'd1 ;
assign pciw_pci0_txDbgDeSof$EN =
WILL_FIRE_RL_pciw_pci0_tx_destage && !pciw_pci0_txInFlight ;
// register pciw_pci0_txDbgDestage
assign pciw_pci0_txDbgDestage$D_IN = pciw_pci0_txDbgDestage + 16'd1 ;
assign pciw_pci0_txDbgDestage$EN = WILL_FIRE_RL_pciw_pci0_tx_destage ;
// register pciw_pci0_txDbgEnEnq
assign pciw_pci0_txDbgEnEnq$D_IN =
pciw_pci0_txDbgEnEnq +
{ 13'd0,
(pciw_pci0_txInF$D_OUT[152] && !pciw_pci0_txInF$D_OUT[126] &&
!pciw_pci0_txInF$D_OUT[125]) ?
3'd3 :
((pciw_pci0_txInF$D_OUT[152] &&
(pciw_pci0_txInF$D_OUT[125] ||
pciw_pci0_txInF$D_OUT[126] &&
pciw_pci0_txInF$D_OUT[143:128] == 16'hFFFF)) ?
3'd4 :
((pciw_pci0_txInF$D_OUT[152] &&
pciw_pci0_txInF$D_OUT[126] &&
!pciw_pci0_txInF$D_OUT[125] &&
pciw_pci0_txInF$D_OUT[143:128] == 16'hFFF0) ?
3'd3 :
((!pciw_pci0_txInF$D_OUT[152] &&
pciw_pci0_txInF$D_OUT[143:128] == 16'hFFFF) ?
3'd4 :
((!pciw_pci0_txInF$D_OUT[152] &&
pciw_pci0_txInF$D_OUT[143:128] == 16'hFFF0) ?
3'd3 :
((!pciw_pci0_txInF$D_OUT[152] &&
pciw_pci0_txInF$D_OUT[143:128] == 16'hFF00) ?
3'd2 :
((!pciw_pci0_txInF$D_OUT[152] &&
pciw_pci0_txInF$D_OUT[143:128] ==
16'hF000) ?
3'd1 :
3'd0)))))) } ;
assign pciw_pci0_txDbgEnEnq$EN = WILL_FIRE_RL_pciw_pci0_tx_enstage ;
// register pciw_pci0_txDbgEnEof
assign pciw_pci0_txDbgEnEof$D_IN = pciw_pci0_txDbgEnEof + 16'd1 ;
assign pciw_pci0_txDbgEnEof$EN =
WILL_FIRE_RL_pciw_pci0_tx_enstage && pciw_pci0_txInF$D_OUT[151] ;
// register pciw_pci0_txDbgEnSof
assign pciw_pci0_txDbgEnSof$D_IN = pciw_pci0_txDbgEnSof + 16'd1 ;
assign pciw_pci0_txDbgEnSof$EN =
WILL_FIRE_RL_pciw_pci0_tx_enstage && pciw_pci0_txInF$D_OUT[152] ;
// register pciw_pci0_txDbgEnstage
assign pciw_pci0_txDbgEnstage$D_IN = pciw_pci0_txDbgEnstage + 16'd1 ;
assign pciw_pci0_txDbgEnstage$EN = WILL_FIRE_RL_pciw_pci0_tx_enstage ;
// register pciw_pci0_txDbgExstage
assign pciw_pci0_txDbgExstage$D_IN = pciw_pci0_txDbgExstage + 16'd1 ;
assign pciw_pci0_txDbgExstage$EN = WILL_FIRE_RL_pciw_pci0_tx_exstage ;
// register pciw_pci0_txDwrDeq
assign pciw_pci0_txDwrDeq$D_IN =
pciw_pci0_txInFlight ?
pciw_pci0_txDwrDeq -
{ 8'd0,
IF_IF_NOT_pciw_pci0_txInFlight_49_57_AND_NOT_I_ETC__q1[2:0] } :
IF_pciw_pci0_txEofF_notEmpty__52_AND_pciw_pci0_ETC___d523 ;
assign pciw_pci0_txDwrDeq$EN = WILL_FIRE_RL_pciw_pci0_tx_destage ;
// register pciw_pci0_txDwrEnq
assign pciw_pci0_txDwrEnq$D_IN = 11'h0 ;
assign pciw_pci0_txDwrEnq$EN = 1'b0 ;
// register pciw_pci0_txDws_num_empty
assign pciw_pci0_txDws_num_empty$D_IN =
pciw_pci0_txDws_num_empty +
{ 1'd0,
IF_pciw_pci0_txDws_delta_deq_whas__9_THEN_pciw_ETC___d804 } -
{ 1'd0,
IF_pciw_pci0_txDws_delta_enq_whas__4_THEN_pciw_ETC___d770 } ;
assign pciw_pci0_txDws_num_empty$EN = 1'd1 ;
// register pciw_pci0_txDws_num_full
assign pciw_pci0_txDws_num_full$D_IN =
pciw_pci0_txDws_num_full +
{ 1'd0,
IF_pciw_pci0_txDws_delta_enq_whas__4_THEN_pciw_ETC___d770 } -
{ 1'd0,
IF_pciw_pci0_txDws_delta_deq_whas__9_THEN_pciw_ETC___d804 } ;
assign pciw_pci0_txDws_num_full$EN = 1'd1 ;
// register pciw_pci0_txDws_vec
assign pciw_pci0_txDws_vec$D_IN =
{ (WILL_FIRE_RL_pciw_pci0_tx_enstage ?
_0_CONCAT_pciw_pci0_txDws_new_data_wget__8_BITS_ETC___d833[255:32] :
224'd0) |
pciw_pci0_txDws_vec_9_SRL_IF_pciw_pci0_txDws_d_ETC___d835[255:32],
(WILL_FIRE_RL_pciw_pci0_tx_enstage ?
_0_CONCAT_pciw_pci0_txDws_new_data_wget__8_BITS_ETC___d833[31:0] :
32'd0) |
pciw_pci0_txDws_vec_9_SRL_IF_pciw_pci0_txDws_d_ETC___d835[31:0] } ;
assign pciw_pci0_txDws_vec$EN = 1'd1 ;
// register pciw_pci0_txInFlight
assign pciw_pci0_txInFlight$D_IN =
NOT_pciw_pci0_txEofF_notEmpty__52_53_OR_NOT_pc_ETC___d495 ;
assign pciw_pci0_txInFlight$EN = WILL_FIRE_RL_pciw_pci0_tx_destage ;
// register pciw_pci0_txOutF_countReg
assign pciw_pci0_txOutF_countReg$D_IN =
WILL_FIRE_RL_pciw_pci0_tx_destage ?
pciw_pci0_txOutF_countReg + 10'd1 :
pciw_pci0_txOutF_countReg - 10'd1 ;
assign pciw_pci0_txOutF_countReg$EN =
WILL_FIRE_RL_pciw_pci0_tx_destage !=
WILL_FIRE_RL_pciw_pci0_tx_exstage ;
// register pciw_pci0_txOutF_levelsValid
assign pciw_pci0_txOutF_levelsValid$D_IN =
WILL_FIRE_RL_pciw_pci0_txOutF_reset ;
assign pciw_pci0_txOutF_levelsValid$EN =
WILL_FIRE_RL_pciw_pci0_tx_exstage ||
WILL_FIRE_RL_pciw_pci0_tx_destage ||
WILL_FIRE_RL_pciw_pci0_txOutF_reset ;
// register pciw_pci0_txReadyD
assign pciw_pci0_txReadyD$D_IN = pciw_pci0_pcie_ep$tx_st_ready0 ;
assign pciw_pci0_txReadyD$EN = 1'd1 ;
// register pciw_pciDevice
assign pciw_pciDevice$D_IN = pciw_pci0_deviceReg ;
assign pciw_pciDevice$EN = 1'd1 ;
// register swReg
assign swReg$D_IN = usr_sw_i ;
assign swReg$EN = 1'd1 ;
// submodule ctop
assign ctop$cpServer_request_put = 59'h0 ;
assign ctop$gps_ppsSyncIn_x = gps_ppsSyncIn_x ;
assign ctop$server_request_put = pciw_p2iF$D_OUT ;
assign ctop$switch_x = 3'h0 ;
assign ctop$wci_m_0_SData = 32'h0 ;
assign ctop$wci_m_0_SFlag = 2'h0 ;
assign ctop$wci_m_0_SResp = 2'h0 ;
assign ctop$wci_m_1_SData = flash0$wciS0_SData ;
assign ctop$wci_m_1_SFlag = flash0$wciS0_SFlag ;
assign ctop$wci_m_1_SResp = flash0$wciS0_SResp ;
assign ctop$wci_m_2_SData = 32'h0 ;
assign ctop$wci_m_2_SFlag = 2'h0 ;
assign ctop$wci_m_2_SResp = 2'h0 ;
assign ctop$wci_m_3_SData = 32'h0 ;
assign ctop$wci_m_3_SFlag = 2'h0 ;
assign ctop$wci_m_3_SResp = 2'h0 ;
assign ctop$wci_m_4_SData = dram0$wciS0_SData ;
assign ctop$wci_m_4_SFlag = dram0$wciS0_SFlag ;
assign ctop$wci_m_4_SResp = dram0$wciS0_SResp ;
assign ctop$wmemiM0_SData = dram0$wmemiS0_SData ;
assign ctop$wmemiM0_SResp = dram0$wmemiS0_SResp ;
assign ctop$wsi_s_adc_MBurstLength = 12'h0 ;
assign ctop$wsi_s_adc_MByteEn = 4'h0 ;
assign ctop$wsi_s_adc_MCmd = 3'h0 ;
assign ctop$wsi_s_adc_MData = 32'h0 ;
assign ctop$wsi_s_adc_MReqInfo = 8'h0 ;
assign ctop$EN_server_request_put =
ctop$RDY_server_request_put && pciw_p2iF$EMPTY_N ;
assign ctop$EN_server_response_get =
ctop$RDY_server_response_get && pciw_i2pF$FULL_N ;
assign ctop$EN_cpServer_request_put = 1'b0 ;
assign ctop$EN_cpServer_response_get = 1'b0 ;
assign ctop$wci_m_0_SThreadBusy = 1'b0 ;
assign ctop$wci_m_1_SThreadBusy = flash0$wciS0_SThreadBusy ;
assign ctop$wci_m_2_SThreadBusy = 1'b0 ;
assign ctop$wci_m_3_SThreadBusy = 1'b0 ;
assign ctop$wci_m_4_SThreadBusy = dram0$wciS0_SThreadBusy ;
assign ctop$wsi_s_adc_MReqLast = 1'b0 ;
assign ctop$wsi_s_adc_MBurstPrecise = 1'b0 ;
assign ctop$wsi_s_adc_MReset_n = 1'b0 ;
assign ctop$wsi_m_dac_SThreadBusy = 1'b0 ;
assign ctop$wsi_m_dac_SReset_n = 1'b0 ;
assign ctop$wmemiM0_SRespLast = dram0$wmemiS0_SRespLast ;
assign ctop$wmemiM0_SCmdAccept = dram0$wmemiS0_SCmdAccept ;
assign ctop$wmemiM0_SDataAccept = dram0$wmemiS0_SDataAccept ;
// submodule dram0
assign dram0$dram_rdn_i = dram_rdn_i ;
assign dram0$dram_rup_i = dram_rup_i ;
assign dram0$wciS0_MAddr = ctop$wci_m_4_MAddr ;
assign dram0$wciS0_MAddrSpace = ctop$wci_m_4_MAddrSpace ;
assign dram0$wciS0_MByteEn = ctop$wci_m_4_MByteEn ;
assign dram0$wciS0_MCmd = ctop$wci_m_4_MCmd ;
assign dram0$wciS0_MData = ctop$wci_m_4_MData ;
assign dram0$wciS0_MFlag = ctop$wci_m_4_MFlag ;
assign dram0$wmemiS0_MAddr = ctop$wmemiM0_MAddr ;
assign dram0$wmemiS0_MBurstLength = ctop$wmemiM0_MBurstLength ;
assign dram0$wmemiS0_MCmd = ctop$wmemiM0_MCmd ;
assign dram0$wmemiS0_MData = ctop$wmemiM0_MData ;
assign dram0$wmemiS0_MDataByteEn = ctop$wmemiM0_MDataByteEn ;
assign dram0$wmemiS0_MReqLast = ctop$wmemiM0_MReqLast ;
assign dram0$wmemiS0_MDataValid = ctop$wmemiM0_MDataValid ;
assign dram0$wmemiS0_MDataLast = ctop$wmemiM0_MDataLast ;
assign dram0$wmemiS0_MReset_n = ctop$wmemiM0_MReset_n ;
// submodule flash0
assign flash0$flash_fwait_i = flash_fwait_i ;
assign flash0$wciS0_MAddr = ctop$wci_m_1_MAddr ;
assign flash0$wciS0_MAddrSpace = ctop$wci_m_1_MAddrSpace ;
assign flash0$wciS0_MByteEn = ctop$wci_m_1_MByteEn ;
assign flash0$wciS0_MCmd = ctop$wci_m_1_MCmd ;
assign flash0$wciS0_MData = ctop$wci_m_1_MData ;
assign flash0$wciS0_MFlag = ctop$wci_m_1_MFlag ;
// submodule lcd_ctrl
assign lcd_ctrl$setLine1_text = 128'h202073656C75522063696D6F74412020 ;
assign lcd_ctrl$setLine2_text = 128'h203474736C61203A204950436E65704F ;
assign lcd_ctrl$EN_setLine1 = needs_init ;
assign lcd_ctrl$EN_setLine2 = needs_init ;
// submodule pciw_aliveLed_sb
assign pciw_aliveLed_sb$sD_IN = pciw_pci0_pcie_ep$ava_alive ;
assign pciw_aliveLed_sb$sEN = 1'd1 ;
// submodule pciw_i2pF
assign pciw_i2pF$D_IN = ctop$server_response_get ;
assign pciw_i2pF$ENQ = ctop$RDY_server_response_get && pciw_i2pF$FULL_N ;
assign pciw_i2pF$DEQ = pciw_i2pF$EMPTY_N && pciw_pci0_txInF$FULL_N ;
assign pciw_i2pF$CLR = 1'b0 ;
// submodule pciw_linkLed_sb
assign pciw_linkLed_sb$sD_IN = pciw_pci0_pcie_ep$ava_lnk_up ;
assign pciw_linkLed_sb$sEN = 1'd1 ;
// submodule pciw_p2iF
assign pciw_p2iF$D_IN = pciw_pci0_rxOutF$D_OUT ;
assign pciw_p2iF$ENQ = pciw_pci0_rxOutF$EMPTY_N && pciw_p2iF$FULL_N ;
assign pciw_p2iF$DEQ = ctop$RDY_server_request_put && pciw_p2iF$EMPTY_N ;
assign pciw_p2iF$CLR = 1'b0 ;
// submodule pciw_pci0_pcie_ep
assign pciw_pci0_pcie_ep$pcie_rx_in = pcie_rx_i ;
assign pciw_pci0_pcie_ep$rx_st_mask0 = 1'd0 ;
assign pciw_pci0_pcie_ep$rx_st_ready0 = pciw_pci0_rxInF_countReg < 6'd30 ;
assign pciw_pci0_pcie_ep$tx_st_data0 = pciw_pci0_txOutF$D_OUT[127:0] ;
assign pciw_pci0_pcie_ep$tx_st_empty0 =
WILL_FIRE_RL_pciw_pci0_tx_exstage &&
pciw_pci0_txOutF$D_OUT[154] ;
assign pciw_pci0_pcie_ep$tx_st_eop0 =
WILL_FIRE_RL_pciw_pci0_tx_exstage &&
pciw_pci0_txOutF$D_OUT[152] ;
assign pciw_pci0_pcie_ep$tx_st_err0 = 1'b0 ;
assign pciw_pci0_pcie_ep$tx_st_sop0 =
WILL_FIRE_RL_pciw_pci0_tx_exstage &&
pciw_pci0_txOutF$D_OUT[153] ;
assign pciw_pci0_pcie_ep$tx_st_valid0 = WILL_FIRE_RL_pciw_pci0_tx_exstage ;
// submodule pciw_pci0_rxEofF
assign pciw_pci0_rxEofF$D_IN = 3'b010 /* unspecified value */ ;
assign pciw_pci0_rxEofF$ENQ =
WILL_FIRE_RL_pciw_pci0_rx_enstage && pciw_pci0_rxInF$D_OUT[152] ;
assign pciw_pci0_rxEofF$DEQ =
WILL_FIRE_RL_pciw_pci0_rx_destage && pciw_pci0_rxEofF$EMPTY_N &&
pciw_pci0_rxDws_num_full_7_ULE_4___d836 ;
assign pciw_pci0_rxEofF$CLR = 1'b0 ;
// submodule pciw_pci0_rxHeadF
assign pciw_pci0_rxHeadF$D_IN =
{ pciw_pci0_rxInF$D_OUT[151:144],
pciw_pci0_rxInF$D_OUT[9:0],
pciw_pci0_rxInF$D_OUT[30:29],
(pciw_pci0_rxInF$D_OUT[29] ? 11'd4 : 11'd3) +
(pciw_pci0_rxInF$D_OUT[30] ?
((pciw_pci0_rxInF$D_OUT[9:0] == 10'd0) ?
11'd1024 :
{ 1'd0, pciw_pci0_rxInF$D_OUT[9:0] }) :
11'd0) } ;
assign pciw_pci0_rxHeadF$ENQ =
WILL_FIRE_RL_pciw_pci0_rx_enstage && pciw_pci0_rxInF$D_OUT[153] ;
assign pciw_pci0_rxHeadF$DEQ =
WILL_FIRE_RL_pciw_pci0_rx_destage && pciw_pci0_rxEofF$EMPTY_N &&
pciw_pci0_rxDws_num_full_7_ULE_4___d836 ;
assign pciw_pci0_rxHeadF$CLR = 1'b0 ;
// submodule pciw_pci0_rxInF
assign pciw_pci0_rxInF$D_IN =
{ pciw_pci0_pcie_ep$rx_st_empty0,
pciw_pci0_pcie_ep$rx_st_sop0,
pciw_pci0_pcie_ep$rx_st_eop0,
x_hit__h22096,
pciw_pci0_pcie_ep$rx_st_be0,
pciw_pci0_pcie_ep$rx_st_data0 } ;
assign pciw_pci0_rxInF$ENQ =
MUX_pciw_pci0_rxInF_levelsValid$write_1__SEL_3 ;
assign pciw_pci0_rxInF$DEQ = WILL_FIRE_RL_pciw_pci0_rx_enstage ;
assign pciw_pci0_rxInF$CLR = 1'b0 ;
// submodule pciw_pci0_rxOutF
assign pciw_pci0_rxOutF$D_IN =
{ !pciw_pci0_rxInFlight,
pciw_pci0_rxEofF$EMPTY_N &&
pciw_pci0_rxDws_num_full_7_ULE_4___d836,
pciw_pci0_rxHeadF$D_OUT[29:23],
x_be__h27614,
x_data__h27615 } ;
assign pciw_pci0_rxOutF$ENQ = WILL_FIRE_RL_pciw_pci0_rx_destage ;
assign pciw_pci0_rxOutF$DEQ = pciw_pci0_rxOutF$EMPTY_N && pciw_p2iF$FULL_N ;
assign pciw_pci0_rxOutF$CLR = 1'b0 ;
// submodule pciw_pci0_txEofF
assign pciw_pci0_txEofF$D_IN = 3'b010 /* unspecified value */ ;
assign pciw_pci0_txEofF$ENQ =
WILL_FIRE_RL_pciw_pci0_tx_enstage && pciw_pci0_txInF$D_OUT[151] ;
assign pciw_pci0_txEofF$DEQ =
WILL_FIRE_RL_pciw_pci0_tx_destage &&
pciw_pci0_txEofF_notEmpty__52_AND_pciw_pci0_tx_ETC___d817 ;
assign pciw_pci0_txEofF$CLR = 1'b0 ;
// submodule pciw_pci0_txExF
assign pciw_pci0_txExF$D_IN = 1'd0 ;
assign pciw_pci0_txExF$ENQ =
WILL_FIRE_RL_pciw_pci0_tx_destage &&
pciw_pci0_txEofF_notEmpty__52_AND_pciw_pci0_tx_ETC___d817 ;
assign pciw_pci0_txExF$DEQ =
WILL_FIRE_RL_pciw_pci0_tx_exstage &&
pciw_pci0_txOutF$D_OUT[152] ;
assign pciw_pci0_txExF$CLR = 1'b0 ;
// submodule pciw_pci0_txHeadF
assign pciw_pci0_txHeadF$D_IN =
{ 8'd0,
pciw_pci0_txInF$D_OUT[105:96],
pciw_pci0_txInF$D_OUT[126:125],
(pciw_pci0_txInF$D_OUT[125] ? 11'd4 : 11'd3) +
(pciw_pci0_txInF$D_OUT[126] ?
((pciw_pci0_txInF$D_OUT[105:96] == 10'd0) ?
11'd1024 :
{ 1'd0, pciw_pci0_txInF$D_OUT[105:96] }) :
11'd0) } ;
assign pciw_pci0_txHeadF$ENQ =
WILL_FIRE_RL_pciw_pci0_tx_enstage && pciw_pci0_txInF$D_OUT[152] ;
assign pciw_pci0_txHeadF$DEQ =
WILL_FIRE_RL_pciw_pci0_tx_destage &&
pciw_pci0_txEofF_notEmpty__52_AND_pciw_pci0_tx_ETC___d817 ;
assign pciw_pci0_txHeadF$CLR = 1'b0 ;
// submodule pciw_pci0_txInF
assign pciw_pci0_txInF$D_IN = pciw_i2pF$D_OUT ;
assign pciw_pci0_txInF$ENQ = pciw_i2pF$EMPTY_N && pciw_pci0_txInF$FULL_N ;
assign pciw_pci0_txInF$DEQ = WILL_FIRE_RL_pciw_pci0_tx_enstage ;
assign pciw_pci0_txInF$CLR = 1'b0 ;
// submodule pciw_pci0_txOutF
assign pciw_pci0_txOutF$D_IN =
{ IF_IF_NOT_pciw_pci0_txInFlight_49_57_AND_NOT_I_ETC__q1[2:0] <
3'd3,
!pciw_pci0_txInFlight,
pciw_pci0_txEofF_notEmpty__52_AND_pciw_pci0_tx_ETC___d817,
24'd0,
x_data__h46011 } ;
assign pciw_pci0_txOutF$ENQ = WILL_FIRE_RL_pciw_pci0_tx_destage ;
assign pciw_pci0_txOutF$DEQ = WILL_FIRE_RL_pciw_pci0_tx_exstage ;
assign pciw_pci0_txOutF$CLR = 1'b0 ;
// remaining internal signals
assign IF_IF_NOT_pciw_pci0_txInFlight_49_57_AND_NOT_I_ETC__q1 =
(IF_NOT_pciw_pci0_txInFlight_49_57_AND_NOT_IF_p_ETC___d837 <=
IF_pciw_pci0_txInFlight_49_THEN_pciw_pci0_txDw_ETC___d838) ?
IF_NOT_pciw_pci0_txInFlight_49_57_AND_NOT_IF_p_ETC___d837 :
IF_pciw_pci0_txInFlight_49_THEN_pciw_pci0_txDw_ETC___d838 ;
assign IF_IF_pciw_pci0_rxInFlight_76_THEN_pciw_pci0_r_ETC__q2 =
(IF_pciw_pci0_rxInFlight_76_THEN_pciw_pci0_rxDw_ETC___d769 <
11'd4) ?
IF_pciw_pci0_rxInFlight_76_THEN_pciw_pci0_rxDw_ETC___d769 :
11'd4 ;
assign IF_NOT_pciw_pci0_txInFlight_49_57_AND_NOT_IF_p_ETC___d837 =
(!pciw_pci0_txInFlight &&
!IF_pciw_pci0_txInFlight_49_THEN_pciw_pci0_txDw_ETC___d481[34] &&
IF_pciw_pci0_txInFlight_49_THEN_pciw_pci0_txDw_ETC___d492[30]) ?
11'd3 :
11'd4 ;
assign IF_pciw_pci0_rxDws_delta_deq_whas__3_THEN_pciw_ETC___d801 =
WILL_FIRE_RL_pciw_pci0_rx_destage ?
IF_IF_pciw_pci0_rxInFlight_76_THEN_pciw_pci0_r_ETC__q2[2:0] :
3'd0 ;
assign IF_pciw_pci0_rxDws_delta_enq_whas__8_THEN_pciw_ETC___d771 =
WILL_FIRE_RL_pciw_pci0_rx_enstage ?
pciw_pci0_rxDws_delta_enq$wget :
3'd0 ;
assign IF_pciw_pci0_rxEofF_notEmpty__62_AND_pciw_pci0_ETC___d288 =
(pciw_pci0_rxEofF$EMPTY_N &&
pciw_pci0_rxDws_num_full_7_ULE_4___d836) ?
11'd0 :
pciw_pci0_rxHeadF$D_OUT[10:0] -
{ 8'd0,
IF_IF_pciw_pci0_rxInFlight_76_THEN_pciw_pci0_r_ETC__q2[2:0] } ;
assign IF_pciw_pci0_rxInFlight_76_THEN_pciw_pci0_rxDw_ETC___d769 =
pciw_pci0_rxInFlight ?
pciw_pci0_rxDwrDeq :
pciw_pci0_rxHeadF$D_OUT[10:0] ;
assign IF_pciw_pci0_txDws_delta_deq_whas__9_THEN_pciw_ETC___d804 =
WILL_FIRE_RL_pciw_pci0_tx_destage ?
IF_IF_NOT_pciw_pci0_txInFlight_49_57_AND_NOT_I_ETC__q1[2:0] :
3'd0 ;
assign IF_pciw_pci0_txDws_delta_enq_whas__4_THEN_pciw_ETC___d770 =
WILL_FIRE_RL_pciw_pci0_tx_enstage ?
pciw_pci0_txDws_delta_enq$wget :
3'd0 ;
assign IF_pciw_pci0_txEofF_notEmpty__52_AND_pciw_pci0_ETC___d523 =
pciw_pci0_txEofF_notEmpty__52_AND_pciw_pci0_tx_ETC___d817 ?
11'd0 :
pciw_pci0_txHeadF$D_OUT[10:0] -
{ 8'd0,
IF_IF_NOT_pciw_pci0_txInFlight_49_57_AND_NOT_I_ETC__q1[2:0] } ;
assign IF_pciw_pci0_txHeadF_first__59_BIT_11_60_THEN__ETC___d468 =
pciw_pci0_txHeadF$D_OUT[11] ?
{ pciw_pci0_txDws_vec[103:96],
pciw_pci0_txDws_vec[111:104],
pciw_pci0_txDws_vec[119:112],
pciw_pci0_txDws_vec[127:120] } :
pciw_pci0_txDws_vec[127:96] ;
assign IF_pciw_pci0_txInFlight_49_THEN_pciw_pci0_txDw_ETC___d481 =
pciw_pci0_txInFlight ?
pciw_pci0_txDws_vec[127:32] :
{ IF_pciw_pci0_txHeadF_first__59_BIT_11_60_THEN__ETC___d468,
pciw_pci0_txDws_vec[71:64],
pciw_pci0_txDws_vec[79:72],
pciw_pci0_txDws_vec[87:80],
pciw_pci0_txDws_vec[95:88],
pciw_pci0_txDws_vec[39:32],
pciw_pci0_txDws_vec[47:40],
pciw_pci0_txDws_vec[55:48],
pciw_pci0_txDws_vec[63:56] } ;
assign IF_pciw_pci0_txInFlight_49_THEN_pciw_pci0_txDw_ETC___d492 =
pciw_pci0_txInFlight ?
pciw_pci0_txDws_vec[31:0] :
{ pciw_pci0_txDws_vec[7:0],
pciw_pci0_txDws_vec[15:8],
pciw_pci0_txDws_vec[23:16],
pciw_pci0_txDws_vec[31:24] } ;
assign IF_pciw_pci0_txInFlight_49_THEN_pciw_pci0_txDw_ETC___d838 =
pciw_pci0_txInFlight ?
pciw_pci0_txDwrDeq :
pciw_pci0_txHeadF$D_OUT[10:0] ;
assign INV_swReg_35_BIT_0_36_XOR_swReg_35_BIT_1_37_38_ETC___d764 =
{ ~swParity__h48492,
~(z__h56332 ^
pciw_pci0_pcie_ep_ava_debug__52_OR_0_CONCAT_pc_ETC___d831[31]),
~pciw_aliveLed_sb$dD_OUT,
~pciw_linkLed_sb$dD_OUT,
~freeCnt[29:26] } ;
assign NOT_pciw_pci0_txEofF_notEmpty__52_53_OR_NOT_pc_ETC___d495 =
!pciw_pci0_txEofF$EMPTY_N ||
!pciw_pci0_txDws_num_full_3_ULE_4___d774 ||
!pciw_pci0_txInFlight &&
!IF_pciw_pci0_txInFlight_49_THEN_pciw_pci0_txDw_ETC___d481[34] &&
IF_pciw_pci0_txInFlight_49_THEN_pciw_pci0_txDw_ETC___d492[30] ;
assign _0_CONCAT_pciw_pci0_rxDws_new_data_wget__2_BITS_ETC___d832 =
{ 128'd0, x__h4523 } << x__h5776 ;
assign _0_CONCAT_pciw_pci0_txDws_new_data_wget__8_BITS_ETC___d833 =
{ 128'd0, x__h14478 } << x__h15731 ;
assign bar___1__h22106 =
(pciw_pci0_pcie_ep$rx_st_data0[28:24] == 5'd0) ?
pciw_pci0_pcie_ep$rx_st_bardec0 :
8'd0 ;
assign pciw_pci0_pcie_ep_ava_debug__52_OR_0_CONCAT_pc_ETC___d831 =
x__h56415 | y__h56416 ;
assign pciw_pci0_rxDws_num_full_7_ULE_4___d836 =
pciw_pci0_rxDws_num_full <= 4'd4 ;
assign pciw_pci0_rxDws_vec_3_SRL_IF_pciw_pci0_rxDws_d_ETC___d834 =
pciw_pci0_rxDws_vec >> x__h8877 ;
assign pciw_pci0_txDws_num_full_3_ULE_4___d774 =
pciw_pci0_txDws_num_full <= 4'd4 ;
assign pciw_pci0_txDws_vec_9_SRL_IF_pciw_pci0_txDws_d_ETC___d835 =
pciw_pci0_txDws_vec >> x__h18832 ;
assign pciw_pci0_txEofF_notEmpty__52_AND_pciw_pci0_tx_ETC___d817 =
pciw_pci0_txEofF$EMPTY_N &&
pciw_pci0_txDws_num_full_3_ULE_4___d774 &&
(pciw_pci0_txInFlight ||
IF_pciw_pci0_txInFlight_49_THEN_pciw_pci0_txDw_ETC___d481[34] ||
!IF_pciw_pci0_txInFlight_49_THEN_pciw_pci0_txDw_ETC___d492[30]) ;
assign pciw_pci0_txOutF_i_notFull__48_AND_pciw_pci0_t_ETC___d502 =
pciw_pci0_txOutF$FULL_N &&
(pciw_pci0_txInFlight || pciw_pci0_txHeadF$EMPTY_N) &&
(NOT_pciw_pci0_txEofF_notEmpty__52_53_OR_NOT_pc_ETC___d495 ||
pciw_pci0_txHeadF$EMPTY_N && pciw_pci0_txEofF$EMPTY_N &&
pciw_pci0_txExF$FULL_N) ;
assign swParity__h48492 = z__h55879 ^ swReg[7] ;
assign x__h14478 =
{ pciw_pci0_txDws_new_data$wget[127:32] &
{ (IF_pciw_pci0_txDws_delta_enq_whas__4_THEN_pciw_ETC___d770 <=
3'd3) ?
32'd0 :
32'hFFFFFFFF,
(IF_pciw_pci0_txDws_delta_enq_whas__4_THEN_pciw_ETC___d770 <=
3'd2) ?
32'd0 :
32'hFFFFFFFF,
(IF_pciw_pci0_txDws_delta_enq_whas__4_THEN_pciw_ETC___d770 <=
3'd1) ?
32'd0 :
32'hFFFFFFFF },
pciw_pci0_txDws_new_data$wget[31:0] &
((IF_pciw_pci0_txDws_delta_enq_whas__4_THEN_pciw_ETC___d770 ==
3'd0) ?
32'd0 :
32'hFFFFFFFF) } ;
assign x__h15731 =
{ pciw_pci0_txDws_num_full -
{ 1'd0,
IF_pciw_pci0_txDws_delta_deq_whas__9_THEN_pciw_ETC___d804 },
5'd0 } ;
assign x__h18832 =
{ IF_pciw_pci0_txDws_delta_deq_whas__9_THEN_pciw_ETC___d804,
5'd0 } ;
assign x__h4523 =
{ pciw_pci0_rxDws_new_data$wget[127:32] &
{ (IF_pciw_pci0_rxDws_delta_enq_whas__8_THEN_pciw_ETC___d771 <=
3'd3) ?
32'd0 :
32'hFFFFFFFF,
(IF_pciw_pci0_rxDws_delta_enq_whas__8_THEN_pciw_ETC___d771 <=
3'd2) ?
32'd0 :
32'hFFFFFFFF,
(IF_pciw_pci0_rxDws_delta_enq_whas__8_THEN_pciw_ETC___d771 <=
3'd1) ?
32'd0 :
32'hFFFFFFFF },
pciw_pci0_rxDws_new_data$wget[31:0] &
((IF_pciw_pci0_rxDws_delta_enq_whas__8_THEN_pciw_ETC___d771 ==
3'd0) ?
32'd0 :
32'hFFFFFFFF) } ;
assign x__h56415 = x__h56417 | y__h56418 ;
assign x__h56417 = x__h56419 | y__h56420 ;
assign x__h56419 = x__h56421 | y__h56422 ;
assign x__h56421 = x__h56423 | y__h56424 ;
assign x__h56423 = x__h56425 | y__h56426 ;
assign x__h56425 = x__h56427 | y__h56428 ;
assign x__h56427 = x__h56429 | y__h56430 ;
assign x__h56429 = x__h56431 | y__h56432 ;
assign x__h56431 = x__h56433 | y__h56434 ;
assign x__h56433 = x__h56435 | y__h56436 ;
assign x__h56435 = x__h56437 | y__h56438 ;
assign x__h56437 = x__h56439 | y__h56440 ;
assign x__h56439 = x__h56441 | y__h56442 ;
assign x__h56441 = x__h56443 | y__h56444 ;
assign x__h56443 = x__h56445 | y__h56446 ;
assign x__h56445 = x__h56447 | y__h56448 ;
assign x__h56447 = x__h56449 | y__h56450 ;
assign x__h56449 = x__h56451 | y__h56452 ;
assign x__h56451 = pciw_pci0_pcie_ep$ava_debug | y__h56454 ;
assign x__h5776 =
{ pciw_pci0_rxDws_num_full -
{ 1'd0,
IF_pciw_pci0_rxDws_delta_deq_whas__3_THEN_pciw_ETC___d801 },
5'd0 } ;
assign x__h8877 =
{ IF_pciw_pci0_rxDws_delta_deq_whas__3_THEN_pciw_ETC___d801,
5'd0 } ;
assign x_be__h27614 =
{ IF_IF_IF_pciw_pci0_rxInFlight_76_THEN_pciw_pci_ETC___d787[0],
IF_IF_IF_pciw_pci0_rxInFlight_76_THEN_pciw_pci_ETC___d787[1],
IF_IF_IF_pciw_pci0_rxInFlight_76_THEN_pciw_pci_ETC___d787[2],
IF_IF_IF_pciw_pci0_rxInFlight_76_THEN_pciw_pci_ETC___d787[3],
IF_IF_IF_pciw_pci0_rxInFlight_76_THEN_pciw_pci_ETC___d787[4],
IF_IF_IF_pciw_pci0_rxInFlight_76_THEN_pciw_pci_ETC___d787[5],
IF_IF_IF_pciw_pci0_rxInFlight_76_THEN_pciw_pci_ETC___d787[6],
IF_IF_IF_pciw_pci0_rxInFlight_76_THEN_pciw_pci_ETC___d787[7],
IF_IF_IF_pciw_pci0_rxInFlight_76_THEN_pciw_pci_ETC___d787[8],
IF_IF_IF_pciw_pci0_rxInFlight_76_THEN_pciw_pci_ETC___d787[9],
IF_IF_IF_pciw_pci0_rxInFlight_76_THEN_pciw_pci_ETC___d787[10],
IF_IF_IF_pciw_pci0_rxInFlight_76_THEN_pciw_pci_ETC___d787[11],
IF_IF_IF_pciw_pci0_rxInFlight_76_THEN_pciw_pci_ETC___d787[12],
IF_IF_IF_pciw_pci0_rxInFlight_76_THEN_pciw_pci_ETC___d787[13],
IF_IF_IF_pciw_pci0_rxInFlight_76_THEN_pciw_pci_ETC___d787[14],
IF_IF_IF_pciw_pci0_rxInFlight_76_THEN_pciw_pci_ETC___d787[15] } ;
assign x_data__h27615 =
{ pciw_pci0_rxDws_vec[7:0],
pciw_pci0_rxDws_vec[15:8],
pciw_pci0_rxDws_vec[23:16],
pciw_pci0_rxDws_vec[31:24],
pciw_pci0_rxDws_vec[39:32],
pciw_pci0_rxDws_vec[47:40],
pciw_pci0_rxDws_vec[55:48],
pciw_pci0_rxDws_vec[63:56],
pciw_pci0_rxDws_vec[71:64],
pciw_pci0_rxDws_vec[79:72],
pciw_pci0_rxDws_vec[87:80],
pciw_pci0_rxDws_vec[95:88],
pciw_pci0_rxDws_vec[103:96],
pciw_pci0_rxDws_vec[111:104],
pciw_pci0_rxDws_vec[119:112],
pciw_pci0_rxDws_vec[127:120] } ;
assign x_data__h46011 =
pciw_pci0_txInFlight ?
pciw_pci0_txDws_vec[127:0] :
{ IF_pciw_pci0_txHeadF_first__59_BIT_11_60_THEN__ETC___d468,
pciw_pci0_txDws_vec[71:64],
pciw_pci0_txDws_vec[79:72],
pciw_pci0_txDws_vec[87:80],
pciw_pci0_txDws_vec[95:88],
pciw_pci0_txDws_vec[39:32],
pciw_pci0_txDws_vec[47:40],
pciw_pci0_txDws_vec[55:48],
pciw_pci0_txDws_vec[63:56],
pciw_pci0_txDws_vec[7:0],
pciw_pci0_txDws_vec[15:8],
pciw_pci0_txDws_vec[23:16],
pciw_pci0_txDws_vec[31:24] } ;
assign x_hit__h22096 =
pciw_pci0_pcie_ep$rx_st_sop0 ? bar___1__h22106 : 8'd0 ;
assign y__h56416 = { 16'd0, pciw_pci0_txDbgDeDeq } ;
assign y__h56418 = { 16'd0, pciw_pci0_txDbgEnEnq } ;
assign y__h56420 = { 16'd0, pciw_pci0_txDbgDeEof } ;
assign y__h56422 = { 16'd0, pciw_pci0_txDbgDeSof } ;
assign y__h56424 = { 16'd0, pciw_pci0_txDbgEnEof } ;
assign y__h56426 = { 16'd0, pciw_pci0_txDbgEnSof } ;
assign y__h56428 = { 16'd0, pciw_pci0_txDbgDestage } ;
assign y__h56430 = { 16'd0, pciw_pci0_txDbgEnstage } ;
assign y__h56432 = { 16'd0, pciw_pci0_txDbgExstage } ;
assign y__h56434 = { 31'd0, pciw_pci0_txInFlight } ;
assign y__h56436 = { 16'd0, pciw_pci0_rxDbgDeDeq } ;
assign y__h56438 = { 16'd0, pciw_pci0_rxDbgEnEnq } ;
assign y__h56440 = { 16'd0, pciw_pci0_rxDbgDeEof } ;
assign y__h56442 = { 16'd0, pciw_pci0_rxDbgDeSof } ;
assign y__h56444 = { 16'd0, pciw_pci0_rxDbgEnEof } ;
assign y__h56446 = { 16'd0, pciw_pci0_rxDbgEnSof } ;
assign y__h56448 = { 16'd0, pciw_pci0_rxDbgDestage } ;
assign y__h56450 = { 16'd0, pciw_pci0_rxDbgEnstage } ;
assign y__h56452 = { 16'd0, pciw_pci0_rxDbgInstage } ;
assign y__h56454 = { 31'd0, pciw_pci0_rxInFlight } ;
assign z__h55844 = swReg[0] ^ swReg[1] ;
assign z__h55851 = z__h55844 ^ swReg[2] ;
assign z__h55858 = z__h55851 ^ swReg[3] ;
assign z__h55865 = z__h55858 ^ swReg[4] ;
assign z__h55872 = z__h55865 ^ swReg[5] ;
assign z__h55879 = z__h55872 ^ swReg[6] ;
assign z__h56129 =
pciw_pci0_pcie_ep_ava_debug__52_OR_0_CONCAT_pc_ETC___d831[0] ^
pciw_pci0_pcie_ep_ava_debug__52_OR_0_CONCAT_pc_ETC___d831[1] ;
assign z__h56136 =
z__h56129 ^
pciw_pci0_pcie_ep_ava_debug__52_OR_0_CONCAT_pc_ETC___d831[2] ;
assign z__h56143 =
z__h56136 ^
pciw_pci0_pcie_ep_ava_debug__52_OR_0_CONCAT_pc_ETC___d831[3] ;
assign z__h56150 =
z__h56143 ^
pciw_pci0_pcie_ep_ava_debug__52_OR_0_CONCAT_pc_ETC___d831[4] ;
assign z__h56157 =
z__h56150 ^
pciw_pci0_pcie_ep_ava_debug__52_OR_0_CONCAT_pc_ETC___d831[5] ;
assign z__h56164 =
z__h56157 ^
pciw_pci0_pcie_ep_ava_debug__52_OR_0_CONCAT_pc_ETC___d831[6] ;
assign z__h56171 =
z__h56164 ^
pciw_pci0_pcie_ep_ava_debug__52_OR_0_CONCAT_pc_ETC___d831[7] ;
assign z__h56178 =
z__h56171 ^
pciw_pci0_pcie_ep_ava_debug__52_OR_0_CONCAT_pc_ETC___d831[8] ;
assign z__h56185 =
z__h56178 ^
pciw_pci0_pcie_ep_ava_debug__52_OR_0_CONCAT_pc_ETC___d831[9] ;
assign z__h56192 =
z__h56185 ^
pciw_pci0_pcie_ep_ava_debug__52_OR_0_CONCAT_pc_ETC___d831[10] ;
assign z__h56199 =
z__h56192 ^
pciw_pci0_pcie_ep_ava_debug__52_OR_0_CONCAT_pc_ETC___d831[11] ;
assign z__h56206 =
z__h56199 ^
pciw_pci0_pcie_ep_ava_debug__52_OR_0_CONCAT_pc_ETC___d831[12] ;
assign z__h56213 =
z__h56206 ^
pciw_pci0_pcie_ep_ava_debug__52_OR_0_CONCAT_pc_ETC___d831[13] ;
assign z__h56220 =
z__h56213 ^
pciw_pci0_pcie_ep_ava_debug__52_OR_0_CONCAT_pc_ETC___d831[14] ;
assign z__h56227 =
z__h56220 ^
pciw_pci0_pcie_ep_ava_debug__52_OR_0_CONCAT_pc_ETC___d831[15] ;
assign z__h56234 =
z__h56227 ^
pciw_pci0_pcie_ep_ava_debug__52_OR_0_CONCAT_pc_ETC___d831[16] ;
assign z__h56241 =
z__h56234 ^
pciw_pci0_pcie_ep_ava_debug__52_OR_0_CONCAT_pc_ETC___d831[17] ;
assign z__h56248 =
z__h56241 ^
pciw_pci0_pcie_ep_ava_debug__52_OR_0_CONCAT_pc_ETC___d831[18] ;
assign z__h56255 =
z__h56248 ^
pciw_pci0_pcie_ep_ava_debug__52_OR_0_CONCAT_pc_ETC___d831[19] ;
assign z__h56262 =
z__h56255 ^
pciw_pci0_pcie_ep_ava_debug__52_OR_0_CONCAT_pc_ETC___d831[20] ;
assign z__h56269 =
z__h56262 ^
pciw_pci0_pcie_ep_ava_debug__52_OR_0_CONCAT_pc_ETC___d831[21] ;
assign z__h56276 =
z__h56269 ^
pciw_pci0_pcie_ep_ava_debug__52_OR_0_CONCAT_pc_ETC___d831[22] ;
assign z__h56283 =
z__h56276 ^
pciw_pci0_pcie_ep_ava_debug__52_OR_0_CONCAT_pc_ETC___d831[23] ;
assign z__h56290 =
z__h56283 ^
pciw_pci0_pcie_ep_ava_debug__52_OR_0_CONCAT_pc_ETC___d831[24] ;
assign z__h56297 =
z__h56290 ^
pciw_pci0_pcie_ep_ava_debug__52_OR_0_CONCAT_pc_ETC___d831[25] ;
assign z__h56304 =
z__h56297 ^
pciw_pci0_pcie_ep_ava_debug__52_OR_0_CONCAT_pc_ETC___d831[26] ;
assign z__h56311 =
z__h56304 ^
pciw_pci0_pcie_ep_ava_debug__52_OR_0_CONCAT_pc_ETC___d831[27] ;
assign z__h56318 =
z__h56311 ^
pciw_pci0_pcie_ep_ava_debug__52_OR_0_CONCAT_pc_ETC___d831[28] ;
assign z__h56325 =
z__h56318 ^
pciw_pci0_pcie_ep_ava_debug__52_OR_0_CONCAT_pc_ETC___d831[29] ;
assign z__h56332 =
z__h56325 ^
pciw_pci0_pcie_ep_ava_debug__52_OR_0_CONCAT_pc_ETC___d831[30] ;
always@(IF_IF_pciw_pci0_rxInFlight_76_THEN_pciw_pci0_r_ETC__q2)
begin
case (IF_IF_pciw_pci0_rxInFlight_76_THEN_pciw_pci0_r_ETC__q2[2:0])
3'd0: IF_IF_IF_pciw_pci0_rxInFlight_76_THEN_pciw_pci_ETC___d787 = 16'h0;
3'd1:
IF_IF_IF_pciw_pci0_rxInFlight_76_THEN_pciw_pci_ETC___d787 =
16'h000F;
3'd2:
IF_IF_IF_pciw_pci0_rxInFlight_76_THEN_pciw_pci_ETC___d787 =
16'h00FF;
3'd3:
IF_IF_IF_pciw_pci0_rxInFlight_76_THEN_pciw_pci_ETC___d787 =
16'h0FFF;
default: IF_IF_IF_pciw_pci0_rxInFlight_76_THEN_pciw_pci_ETC___d787 =
16'hFFFF;
endcase
end
// handling of inlined registers
always@(posedge pciw_pci0_pcie_ep$ava_core_clk_out)
begin
if (pciw_pci0_pcie_ep$ava_srstn == `BSV_RESET_VALUE)
begin
freeCnt <= `BSV_ASSIGNMENT_DELAY 32'd0;
hsmcReg <= `BSV_ASSIGNMENT_DELAY 16'd0;
ledReg <= `BSV_ASSIGNMENT_DELAY 16'd0;
needs_init <= `BSV_ASSIGNMENT_DELAY 1'd1;
pciDevice <= `BSV_ASSIGNMENT_DELAY 16'd0;
pciw_pci0_cfgDataWr <= `BSV_ASSIGNMENT_DELAY 1'h0;
pciw_pci0_cfgSample <= `BSV_ASSIGNMENT_DELAY 1'h0;
pciw_pci0_deviceReg <= `BSV_ASSIGNMENT_DELAY 16'hAAAA;
pciw_pci0_rxDbgDeDeq <= `BSV_ASSIGNMENT_DELAY 16'd0;
pciw_pci0_rxDbgDeEof <= `BSV_ASSIGNMENT_DELAY 16'd0;
pciw_pci0_rxDbgDeSof <= `BSV_ASSIGNMENT_DELAY 16'd0;
pciw_pci0_rxDbgDestage <= `BSV_ASSIGNMENT_DELAY 16'd0;
pciw_pci0_rxDbgEnEnq <= `BSV_ASSIGNMENT_DELAY 16'd0;
pciw_pci0_rxDbgEnEof <= `BSV_ASSIGNMENT_DELAY 16'd0;
pciw_pci0_rxDbgEnSof <= `BSV_ASSIGNMENT_DELAY 16'd0;
pciw_pci0_rxDbgEnstage <= `BSV_ASSIGNMENT_DELAY 16'd0;
pciw_pci0_rxDbgInstage <= `BSV_ASSIGNMENT_DELAY 16'd0;
pciw_pci0_rxDwrDeq <= `BSV_ASSIGNMENT_DELAY 11'd0;
pciw_pci0_rxDwrEnq <= `BSV_ASSIGNMENT_DELAY 11'd0;
pciw_pci0_rxDws_num_empty <= `BSV_ASSIGNMENT_DELAY 4'd8;
pciw_pci0_rxDws_num_full <= `BSV_ASSIGNMENT_DELAY 4'd0;
pciw_pci0_rxDws_vec <= `BSV_ASSIGNMENT_DELAY 256'd0;
pciw_pci0_rxInF_countReg <= `BSV_ASSIGNMENT_DELAY 6'd0;
pciw_pci0_rxInF_levelsValid <= `BSV_ASSIGNMENT_DELAY 1'd1;
pciw_pci0_rxInFlight <= `BSV_ASSIGNMENT_DELAY 1'd0;
pciw_pci0_txDbgDeDeq <= `BSV_ASSIGNMENT_DELAY 16'd0;
pciw_pci0_txDbgDeEof <= `BSV_ASSIGNMENT_DELAY 16'd0;
pciw_pci0_txDbgDeSof <= `BSV_ASSIGNMENT_DELAY 16'd0;
pciw_pci0_txDbgDestage <= `BSV_ASSIGNMENT_DELAY 16'd0;
pciw_pci0_txDbgEnEnq <= `BSV_ASSIGNMENT_DELAY 16'd0;
pciw_pci0_txDbgEnEof <= `BSV_ASSIGNMENT_DELAY 16'd0;
pciw_pci0_txDbgEnSof <= `BSV_ASSIGNMENT_DELAY 16'd0;
pciw_pci0_txDbgEnstage <= `BSV_ASSIGNMENT_DELAY 16'd0;
pciw_pci0_txDbgExstage <= `BSV_ASSIGNMENT_DELAY 16'd0;
pciw_pci0_txDwrDeq <= `BSV_ASSIGNMENT_DELAY 11'd0;
pciw_pci0_txDwrEnq <= `BSV_ASSIGNMENT_DELAY 11'd0;
pciw_pci0_txDws_num_empty <= `BSV_ASSIGNMENT_DELAY 4'd8;
pciw_pci0_txDws_num_full <= `BSV_ASSIGNMENT_DELAY 4'd0;
pciw_pci0_txDws_vec <= `BSV_ASSIGNMENT_DELAY 256'd0;
pciw_pci0_txInFlight <= `BSV_ASSIGNMENT_DELAY 1'd0;
pciw_pci0_txOutF_countReg <= `BSV_ASSIGNMENT_DELAY 10'd0;
pciw_pci0_txOutF_levelsValid <= `BSV_ASSIGNMENT_DELAY 1'd1;
pciw_pci0_txReadyD <= `BSV_ASSIGNMENT_DELAY 1'd0;
pciw_pciDevice <= `BSV_ASSIGNMENT_DELAY 16'd0;
swReg <= `BSV_ASSIGNMENT_DELAY 8'd0;
end
else
begin
if (freeCnt$EN) freeCnt <= `BSV_ASSIGNMENT_DELAY freeCnt$D_IN;
if (hsmcReg$EN) hsmcReg <= `BSV_ASSIGNMENT_DELAY hsmcReg$D_IN;
if (ledReg$EN) ledReg <= `BSV_ASSIGNMENT_DELAY ledReg$D_IN;
if (needs_init$EN)
needs_init <= `BSV_ASSIGNMENT_DELAY needs_init$D_IN;
if (pciDevice$EN) pciDevice <= `BSV_ASSIGNMENT_DELAY pciDevice$D_IN;
if (pciw_pci0_cfgDataWr$EN)
pciw_pci0_cfgDataWr <= `BSV_ASSIGNMENT_DELAY
pciw_pci0_cfgDataWr$D_IN;
if (pciw_pci0_cfgSample$EN)
pciw_pci0_cfgSample <= `BSV_ASSIGNMENT_DELAY
pciw_pci0_cfgSample$D_IN;
if (pciw_pci0_deviceReg$EN)
pciw_pci0_deviceReg <= `BSV_ASSIGNMENT_DELAY
pciw_pci0_deviceReg$D_IN;
if (pciw_pci0_rxDbgDeDeq$EN)
pciw_pci0_rxDbgDeDeq <= `BSV_ASSIGNMENT_DELAY
pciw_pci0_rxDbgDeDeq$D_IN;
if (pciw_pci0_rxDbgDeEof$EN)
pciw_pci0_rxDbgDeEof <= `BSV_ASSIGNMENT_DELAY
pciw_pci0_rxDbgDeEof$D_IN;
if (pciw_pci0_rxDbgDeSof$EN)
pciw_pci0_rxDbgDeSof <= `BSV_ASSIGNMENT_DELAY
pciw_pci0_rxDbgDeSof$D_IN;
if (pciw_pci0_rxDbgDestage$EN)
pciw_pci0_rxDbgDestage <= `BSV_ASSIGNMENT_DELAY
pciw_pci0_rxDbgDestage$D_IN;
if (pciw_pci0_rxDbgEnEnq$EN)
pciw_pci0_rxDbgEnEnq <= `BSV_ASSIGNMENT_DELAY
pciw_pci0_rxDbgEnEnq$D_IN;
if (pciw_pci0_rxDbgEnEof$EN)
pciw_pci0_rxDbgEnEof <= `BSV_ASSIGNMENT_DELAY
pciw_pci0_rxDbgEnEof$D_IN;
if (pciw_pci0_rxDbgEnSof$EN)
pciw_pci0_rxDbgEnSof <= `BSV_ASSIGNMENT_DELAY
pciw_pci0_rxDbgEnSof$D_IN;
if (pciw_pci0_rxDbgEnstage$EN)
pciw_pci0_rxDbgEnstage <= `BSV_ASSIGNMENT_DELAY
pciw_pci0_rxDbgEnstage$D_IN;
if (pciw_pci0_rxDbgInstage$EN)
pciw_pci0_rxDbgInstage <= `BSV_ASSIGNMENT_DELAY
pciw_pci0_rxDbgInstage$D_IN;
if (pciw_pci0_rxDwrDeq$EN)
pciw_pci0_rxDwrDeq <= `BSV_ASSIGNMENT_DELAY pciw_pci0_rxDwrDeq$D_IN;
if (pciw_pci0_rxDwrEnq$EN)
pciw_pci0_rxDwrEnq <= `BSV_ASSIGNMENT_DELAY pciw_pci0_rxDwrEnq$D_IN;
if (pciw_pci0_rxDws_num_empty$EN)
pciw_pci0_rxDws_num_empty <= `BSV_ASSIGNMENT_DELAY
pciw_pci0_rxDws_num_empty$D_IN;
if (pciw_pci0_rxDws_num_full$EN)
pciw_pci0_rxDws_num_full <= `BSV_ASSIGNMENT_DELAY
pciw_pci0_rxDws_num_full$D_IN;
if (pciw_pci0_rxDws_vec$EN)
pciw_pci0_rxDws_vec <= `BSV_ASSIGNMENT_DELAY
pciw_pci0_rxDws_vec$D_IN;
if (pciw_pci0_rxInF_countReg$EN)
pciw_pci0_rxInF_countReg <= `BSV_ASSIGNMENT_DELAY
pciw_pci0_rxInF_countReg$D_IN;
if (pciw_pci0_rxInF_levelsValid$EN)
pciw_pci0_rxInF_levelsValid <= `BSV_ASSIGNMENT_DELAY
pciw_pci0_rxInF_levelsValid$D_IN;
if (pciw_pci0_rxInFlight$EN)
pciw_pci0_rxInFlight <= `BSV_ASSIGNMENT_DELAY
pciw_pci0_rxInFlight$D_IN;
if (pciw_pci0_txDbgDeDeq$EN)
pciw_pci0_txDbgDeDeq <= `BSV_ASSIGNMENT_DELAY
pciw_pci0_txDbgDeDeq$D_IN;
if (pciw_pci0_txDbgDeEof$EN)
pciw_pci0_txDbgDeEof <= `BSV_ASSIGNMENT_DELAY
pciw_pci0_txDbgDeEof$D_IN;
if (pciw_pci0_txDbgDeSof$EN)
pciw_pci0_txDbgDeSof <= `BSV_ASSIGNMENT_DELAY
pciw_pci0_txDbgDeSof$D_IN;
if (pciw_pci0_txDbgDestage$EN)
pciw_pci0_txDbgDestage <= `BSV_ASSIGNMENT_DELAY
pciw_pci0_txDbgDestage$D_IN;
if (pciw_pci0_txDbgEnEnq$EN)
pciw_pci0_txDbgEnEnq <= `BSV_ASSIGNMENT_DELAY
pciw_pci0_txDbgEnEnq$D_IN;
if (pciw_pci0_txDbgEnEof$EN)
pciw_pci0_txDbgEnEof <= `BSV_ASSIGNMENT_DELAY
pciw_pci0_txDbgEnEof$D_IN;
if (pciw_pci0_txDbgEnSof$EN)
pciw_pci0_txDbgEnSof <= `BSV_ASSIGNMENT_DELAY
pciw_pci0_txDbgEnSof$D_IN;
if (pciw_pci0_txDbgEnstage$EN)
pciw_pci0_txDbgEnstage <= `BSV_ASSIGNMENT_DELAY
pciw_pci0_txDbgEnstage$D_IN;
if (pciw_pci0_txDbgExstage$EN)
pciw_pci0_txDbgExstage <= `BSV_ASSIGNMENT_DELAY
pciw_pci0_txDbgExstage$D_IN;
if (pciw_pci0_txDwrDeq$EN)
pciw_pci0_txDwrDeq <= `BSV_ASSIGNMENT_DELAY pciw_pci0_txDwrDeq$D_IN;
if (pciw_pci0_txDwrEnq$EN)
pciw_pci0_txDwrEnq <= `BSV_ASSIGNMENT_DELAY pciw_pci0_txDwrEnq$D_IN;
if (pciw_pci0_txDws_num_empty$EN)
pciw_pci0_txDws_num_empty <= `BSV_ASSIGNMENT_DELAY
pciw_pci0_txDws_num_empty$D_IN;
if (pciw_pci0_txDws_num_full$EN)
pciw_pci0_txDws_num_full <= `BSV_ASSIGNMENT_DELAY
pciw_pci0_txDws_num_full$D_IN;
if (pciw_pci0_txDws_vec$EN)
pciw_pci0_txDws_vec <= `BSV_ASSIGNMENT_DELAY
pciw_pci0_txDws_vec$D_IN;
if (pciw_pci0_txInFlight$EN)
pciw_pci0_txInFlight <= `BSV_ASSIGNMENT_DELAY
pciw_pci0_txInFlight$D_IN;
if (pciw_pci0_txOutF_countReg$EN)
pciw_pci0_txOutF_countReg <= `BSV_ASSIGNMENT_DELAY
pciw_pci0_txOutF_countReg$D_IN;
if (pciw_pci0_txOutF_levelsValid$EN)
pciw_pci0_txOutF_levelsValid <= `BSV_ASSIGNMENT_DELAY
pciw_pci0_txOutF_levelsValid$D_IN;
if (pciw_pci0_txReadyD$EN)
pciw_pci0_txReadyD <= `BSV_ASSIGNMENT_DELAY pciw_pci0_txReadyD$D_IN;
if (pciw_pciDevice$EN)
pciw_pciDevice <= `BSV_ASSIGNMENT_DELAY pciw_pciDevice$D_IN;
if (swReg$EN) swReg <= `BSV_ASSIGNMENT_DELAY swReg$D_IN;
end
end
// synopsys translate_off
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
initial
begin
freeCnt = 32'hAAAAAAAA;
hsmcReg = 16'hAAAA;
ledReg = 16'hAAAA;
needs_init = 1'h0;
pciDevice = 16'hAAAA;
pciw_pci0_cfgDataWr = 1'h0;
pciw_pci0_cfgSample = 1'h0;
pciw_pci0_deviceReg = 16'hAAAA;
pciw_pci0_rxDbgDeDeq = 16'hAAAA;
pciw_pci0_rxDbgDeEof = 16'hAAAA;
pciw_pci0_rxDbgDeSof = 16'hAAAA;
pciw_pci0_rxDbgDestage = 16'hAAAA;
pciw_pci0_rxDbgEnEnq = 16'hAAAA;
pciw_pci0_rxDbgEnEof = 16'hAAAA;
pciw_pci0_rxDbgEnSof = 16'hAAAA;
pciw_pci0_rxDbgEnstage = 16'hAAAA;
pciw_pci0_rxDbgInstage = 16'hAAAA;
pciw_pci0_rxDwrDeq = 11'h2AA;
pciw_pci0_rxDwrEnq = 11'h2AA;
pciw_pci0_rxDws_num_empty = 4'hA;
pciw_pci0_rxDws_num_full = 4'hA;
pciw_pci0_rxDws_vec =
256'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
pciw_pci0_rxInF_countReg = 6'h2A;
pciw_pci0_rxInF_levelsValid = 1'h0;
pciw_pci0_rxInFlight = 1'h0;
pciw_pci0_txDbgDeDeq = 16'hAAAA;
pciw_pci0_txDbgDeEof = 16'hAAAA;
pciw_pci0_txDbgDeSof = 16'hAAAA;
pciw_pci0_txDbgDestage = 16'hAAAA;
pciw_pci0_txDbgEnEnq = 16'hAAAA;
pciw_pci0_txDbgEnEof = 16'hAAAA;
pciw_pci0_txDbgEnSof = 16'hAAAA;
pciw_pci0_txDbgEnstage = 16'hAAAA;
pciw_pci0_txDbgExstage = 16'hAAAA;
pciw_pci0_txDwrDeq = 11'h2AA;
pciw_pci0_txDwrEnq = 11'h2AA;
pciw_pci0_txDws_num_empty = 4'hA;
pciw_pci0_txDws_num_full = 4'hA;
pciw_pci0_txDws_vec =
256'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
pciw_pci0_txInFlight = 1'h0;
pciw_pci0_txOutF_countReg = 10'h2AA;
pciw_pci0_txOutF_levelsValid = 1'h0;
pciw_pci0_txReadyD = 1'h0;
pciw_pciDevice = 16'hAAAA;
swReg = 8'hAA;
end
`endif // BSV_NO_INITIAL_BLOCKS
// synopsys translate_on
endmodule
|
module altera_avalon_packets_to_master (
// Interface: clk
input wire clk,
input wire reset_n,
// Interface: ST in
output wire in_ready,
input wire in_valid,
input wire [ 7: 0] in_data,
input wire in_startofpacket,
input wire in_endofpacket,
// Interface: ST out
input wire out_ready,
output wire out_valid,
output wire [ 7: 0] out_data,
output wire out_startofpacket,
output wire out_endofpacket,
// Interface: MM out
output wire [31: 0] address,
input wire [31: 0] readdata,
output wire read,
output wire write,
output wire [ 3: 0] byteenable,
output wire [31: 0] writedata,
input wire waitrequest,
input wire readdatavalid
);
wire [ 35: 0] fifo_readdata;
wire fifo_read;
wire fifo_empty;
wire [ 35: 0] fifo_writedata;
wire fifo_write;
wire fifo_write_waitrequest;
// ---------------------------------------------------------------------
//| Parameter Declarations
// ---------------------------------------------------------------------
parameter EXPORT_MASTER_SIGNALS = 0;
parameter FIFO_DEPTHS = 2;
parameter FIFO_WIDTHU = 1;
parameter FAST_VER = 0;
generate
if (FAST_VER) begin
packets_to_fifo p2f (
.clk (clk),
.reset_n (reset_n),
.in_ready (in_ready),
.in_valid (in_valid),
.in_data (in_data),
.in_startofpacket (in_startofpacket),
.in_endofpacket (in_endofpacket),
.address (address),
.readdata (readdata),
.read (read),
.write (write),
.byteenable (byteenable),
.writedata (writedata),
.waitrequest (waitrequest),
.readdatavalid (readdatavalid),
.fifo_writedata (fifo_writedata),
.fifo_write (fifo_write),
.fifo_write_waitrequest (fifo_write_waitrequest)
);
fifo_to_packet f2p (
.clk (clk),
.reset_n (reset_n),
.out_ready (out_ready),
.out_valid (out_valid),
.out_data (out_data),
.out_startofpacket (out_startofpacket),
.out_endofpacket (out_endofpacket),
.fifo_readdata (fifo_readdata),
.fifo_read (fifo_read),
.fifo_empty (fifo_empty)
);
fifo_buffer #(
.FIFO_DEPTHS(FIFO_DEPTHS),
.FIFO_WIDTHU(FIFO_WIDTHU)
) fb (
.wrclock (clk),
.reset_n (reset_n),
.avalonmm_write_slave_writedata (fifo_writedata),
.avalonmm_write_slave_write (fifo_write),
.avalonmm_write_slave_waitrequest (fifo_write_waitrequest),
.avalonmm_read_slave_readdata (fifo_readdata),
.avalonmm_read_slave_read (fifo_read),
.avalonmm_read_slave_waitrequest (fifo_empty)
);
end else begin
packets_to_master p2m (
.clk (clk),
.reset_n (reset_n),
.in_ready (in_ready),
.in_valid (in_valid),
.in_data (in_data),
.in_startofpacket (in_startofpacket),
.in_endofpacket (in_endofpacket),
.address (address),
.readdata (readdata),
.read (read),
.write (write),
.byteenable (byteenable),
.writedata (writedata),
.waitrequest (waitrequest),
.readdatavalid (readdatavalid),
.out_ready (out_ready),
.out_valid (out_valid),
.out_data (out_data),
.out_startofpacket (out_startofpacket),
.out_endofpacket (out_endofpacket)
);
end
endgenerate
endmodule
|
module packets_to_fifo (
// Interface: clk
input clk,
input reset_n,
// Interface: ST in
output reg in_ready,
input in_valid,
input [ 7: 0] in_data,
input in_startofpacket,
input in_endofpacket,
// Interface: MM out
output reg [31: 0] address,
input [31: 0] readdata,
output reg read,
output reg write,
output reg [ 3: 0] byteenable,
output reg [31: 0] writedata,
input waitrequest,
input readdatavalid,
// Interface: FIFO
// FIFO data format:
// | sop, eop, [1:0]valid, [31:0]data |
output reg [ 35: 0] fifo_writedata,
output reg fifo_write,
input wire fifo_write_waitrequest
);
// ---------------------------------------------------------------------
//| Command Declarations
// ---------------------------------------------------------------------
localparam CMD_WRITE_NON_INCR = 8'h00;
localparam CMD_WRITE_INCR = 8'h04;
localparam CMD_READ_NON_INCR = 8'h10;
localparam CMD_READ_INCR = 8'h14;
// ---------------------------------------------------------------------
//| Signal Declarations
// ---------------------------------------------------------------------
reg [ 3: 0] state;
reg [ 7: 0] command;
reg [ 1: 0] current_byte, byte_avail;
reg [ 15: 0] counter;
reg [ 31: 0] read_data_buffer;
reg [ 31: 0] fifo_data_buffer;
reg in_ready_0;
reg first_trans, last_trans, fifo_sop;
reg [ 3: 0] unshifted_byteenable;
wire enable;
localparam READY = 4'b0000,
GET_EXTRA = 4'b0001,
GET_SIZE1 = 4'b0010,
GET_SIZE2 = 4'b0011,
GET_ADDR1 = 4'b0100,
GET_ADDR2 = 4'b0101,
GET_ADDR3 = 4'b0110,
GET_ADDR4 = 4'b0111,
GET_WRITE_DATA = 4'b1000,
WRITE_WAIT = 4'b1001,
READ_ASSERT = 4'b1010,
READ_CMD_WAIT = 4'b1011,
READ_DATA_WAIT = 4'b1100,
PUSH_FIFO = 4'b1101,
PUSH_FIFO_WAIT = 4'b1110,
FIFO_CMD_WAIT = 4'b1111;
// ---------------------------------------------------------------------
//| Thingofamagick
// ---------------------------------------------------------------------
assign enable = (in_ready & in_valid);
always @* begin
in_ready = in_ready_0;
end
always @(posedge clk or negedge reset_n) begin
if (!reset_n) begin
in_ready_0 <= 1'b0;
fifo_writedata <= 'b0;
fifo_write <= 1'b0;
fifo_sop <= 1'b0;
read <= 1'b0;
write <= 1'b0;
byteenable <= 'b0;
writedata <= 'b0;
address <= 'b0;
counter <= 'b0;
command <= 'b0;
first_trans <= 1'b0;
last_trans <= 1'b0;
state <= 'b0;
current_byte <= 'b0;
read_data_buffer <= 'b0;
unshifted_byteenable <= 'b0;
byte_avail <= 'b0;
fifo_data_buffer <= 'b0;
end else begin
address[1:0] <= 'b0;
in_ready_0 <= 1'b0;
if (counter > 3) unshifted_byteenable <= 4'b1111;
else if (counter == 3) unshifted_byteenable <= 4'b0111;
else if (counter == 2) unshifted_byteenable <= 4'b0011;
else if (counter == 1) unshifted_byteenable <= 4'b0001;
case (state)
READY : begin
in_ready_0 <= !fifo_write_waitrequest;
fifo_write <= 1'b0;
end
GET_EXTRA : begin
in_ready_0 <= 1'b1;
byteenable <= 'b0;
if (enable) state <= GET_SIZE1;
end
GET_SIZE1 : begin
in_ready_0 <= 1'b1;
//load counter on reads only
counter[15:8] <= command[4]?in_data:8'b0;
if (enable) state <= GET_SIZE2;
end
GET_SIZE2 : begin
in_ready_0 <= 1'b1;
//load counter on reads only
counter[7:0] <= command[4]?in_data:8'b0;
if (enable) state <= GET_ADDR1;
end
GET_ADDR1 : begin
in_ready_0 <= 1'b1;
first_trans <= 1'b1;
last_trans <= 1'b0;
address[31:24] <= in_data;
if (enable) state <= GET_ADDR2;
end
GET_ADDR2 : begin
in_ready_0 <= 1'b1;
address[23:16] <= in_data;
if (enable) state <= GET_ADDR3;
end
GET_ADDR3 : begin
in_ready_0 <= 1'b1;
address[15:8] <= in_data;
if (enable) state <= GET_ADDR4;
end
GET_ADDR4 : begin
in_ready_0 <= 1'b1;
address[7:2] <= in_data[7:2];
current_byte <= in_data[1:0];
if (enable) begin
if (command == CMD_WRITE_NON_INCR | command == CMD_WRITE_INCR) begin
state <= GET_WRITE_DATA; //writes
in_ready_0 <= 1'b1;
end
else if (command == CMD_READ_NON_INCR | command == CMD_READ_INCR) begin
state <= READ_ASSERT; //reads
in_ready_0 <= 1'b0;
end
else begin
//nops
//treat all unrecognized commands as nops as well
in_ready_0 <= 1'b0;
state <= FIFO_CMD_WAIT;
//| sop, eop, [1:0]valid, [31:0]data |
//| 1 , 1 , 2'b11 ,{counter,reserved_byte}|
fifo_writedata[7:0] <= (8'h80 | command);
fifo_writedata[35:8]<= {4'b1111,counter[7:0],counter[15:8],8'b0};
fifo_write <= 1'b1;
counter <= 0;
end
end
end
GET_WRITE_DATA : begin
in_ready_0 <= 1'b1;
if (enable) begin
counter <= counter + 1'b1;
//2 bit, should wrap by itself
current_byte <= current_byte + 1'b1;
if (in_endofpacket || current_byte == 3)
begin
in_ready_0 <= 1'b0;
write <= 1'b1;
state <= WRITE_WAIT;
end
end
if (in_endofpacket) begin
last_trans <= 1'b1;
end
// handle byte writes properly
// drive data pins based on addresses
case (current_byte)
0: begin
writedata[7:0] <= in_data;
byteenable[0] <= 1'b1;
end
1: begin
writedata[15:8] <= in_data;
byteenable[1] <= 1'b1;
end
2: begin
writedata[23:16] <= in_data;
byteenable[2] <= 1'b1;
end
3: begin
writedata[31:24] <= in_data;
byteenable[3] <= 1'b1;
end
endcase
end
WRITE_WAIT : begin
in_ready_0 <= 1'b0;
write <= 1'b1;
if (~waitrequest) begin
write <= 1'b0;
state <= GET_WRITE_DATA;
in_ready_0 <= 1'b1;
byteenable <= 'b0;
if (command[2] == 1'b1) begin
//increment address, but word-align it
address[31:2] <= (address[31:2] + 1'b1);
end
if (last_trans) begin
in_ready_0 <= 1'b0;
state <= FIFO_CMD_WAIT;
//| sop, eop, [1:0]valid, [31:0]data |
//| 1 , 1 , 2'b11 ,{counter,reserved_byte}|
fifo_writedata[7:0] <= (8'h80 | command);
fifo_writedata[35:8]<= {4'b1111,counter[7:0],counter[15:8],8'b0};
fifo_write <= 1'b1;
counter <= 0;
end
end
end
READ_ASSERT : begin
if (current_byte == 3) byteenable <= unshifted_byteenable << 3;
if (current_byte == 2) byteenable <= unshifted_byteenable << 2;
if (current_byte == 1) byteenable <= unshifted_byteenable << 1;
if (current_byte == 0) byteenable <= unshifted_byteenable;
read <= 1'b1;
fifo_write <= 1'b0;
state <= READ_CMD_WAIT;
end
READ_CMD_WAIT : begin
// number of valid byte
case (byteenable)
4'b0000 : byte_avail <= 1'b0;
4'b0001 : byte_avail <= 1'b0;
4'b0010 : byte_avail <= 1'b0;
4'b0100 : byte_avail <= 1'b0;
4'b1000 : byte_avail <= 1'b0;
4'b0011 : byte_avail <= 1'b1;
4'b0110 : byte_avail <= 1'b1;
4'b1100 : byte_avail <= 1'b1;
4'b0111 : byte_avail <= 2'h2;
4'b1110 : byte_avail <= 2'h2;
default : byte_avail <= 2'h3;
endcase
read_data_buffer <= readdata;
read <= 1;
// if readdatavalid, take the data and
// go directly to READ_SEND_ISSUE. This is for fixed
// latency slaves. Ignore waitrequest in this case,
// since this master does not issue pipelined reads.
//
// For variable latency slaves, once waitrequest is low
// the read command is accepted, so deassert read and
// go to READ_DATA_WAIT to wait for readdatavalid
if (readdatavalid) begin
state <= PUSH_FIFO;
read <= 0;
end else begin
if (~waitrequest) begin
state <= READ_DATA_WAIT;
read <= 0;
end
end
end
READ_DATA_WAIT : begin
read_data_buffer <= readdata;
if (readdatavalid) begin
state <= PUSH_FIFO;
end
end
PUSH_FIFO : begin
fifo_write <= 1'b0;
fifo_sop <= 1'b0;
if (first_trans) begin
first_trans <= 1'b0;
fifo_sop <= 1'b1;
end
case (current_byte)
3 : begin
fifo_data_buffer <= read_data_buffer >> 24;
counter <= counter - 1'b1;
end
2 : begin
fifo_data_buffer <= read_data_buffer >> 16;
if (counter == 1) counter <= 0;
else counter <= counter - 2'h2;
end
1 : begin
fifo_data_buffer <= read_data_buffer >> 8;
if (counter < 3) counter <= 0;
else counter <= counter - 2'h3;
end
default : begin
fifo_data_buffer <= read_data_buffer;
if (counter < 4) counter <= 0;
else counter <= counter - 3'h4;
end
endcase
current_byte <= 0;
state <= PUSH_FIFO_WAIT;
end
PUSH_FIFO_WAIT : begin
// pushd return packet with data
fifo_write <= 1'b1;
fifo_writedata <= {fifo_sop,(counter == 0)?1'b1:1'b0,byte_avail,fifo_data_buffer};
// count down on the number of bytes to read
// shift current byte location within word
// if increment address, add it, so the next read
// can use it, if more reads are required
// no more bytes to send - go to READY state
if (counter == 0) begin
state <= FIFO_CMD_WAIT;
end else if (command[2]== 1'b1) begin
//increment address, but word-align it
state <= FIFO_CMD_WAIT;
address[31:2] <= (address[31:2] + 1'b1);
end
end
FIFO_CMD_WAIT : begin
// back pressure if fifo_write_waitrequest
if (!fifo_write_waitrequest) begin
if (counter == 0) begin
state <= READY;
end else begin
state <= READ_ASSERT;
end
fifo_write <= 1'b0;
end
end
endcase
if (enable & in_startofpacket) begin
state <= GET_EXTRA;
command <= in_data;
in_ready_0 <= !fifo_write_waitrequest;
end
end // end else
end // end always block
endmodule
|
module fifo_buffer_single_clock_fifo (
// inputs:
aclr,
clock,
data,
rdreq,
wrreq,
// outputs:
empty,
full,
q
)
;
parameter FIFO_DEPTHS = 2;
parameter FIFO_WIDTHU = 1;
output empty;
output full;
output [ 35: 0] q;
input aclr;
input clock;
input [ 35: 0] data;
input rdreq;
input wrreq;
wire empty;
wire full;
wire [ 35: 0] q;
scfifo single_clock_fifo
(
.aclr (aclr),
.clock (clock),
.data (data),
.empty (empty),
.full (full),
.q (q),
.rdreq (rdreq),
.wrreq (wrreq)
);
defparam single_clock_fifo.add_ram_output_register = "OFF",
single_clock_fifo.lpm_numwords = FIFO_DEPTHS,
single_clock_fifo.lpm_showahead = "OFF",
single_clock_fifo.lpm_type = "scfifo",
single_clock_fifo.lpm_width = 36,
single_clock_fifo.lpm_widthu = FIFO_WIDTHU,
single_clock_fifo.overflow_checking = "ON",
single_clock_fifo.underflow_checking = "ON",
single_clock_fifo.use_eab = "OFF";
endmodule
|
module fifo_buffer_scfifo_with_controls (
// inputs:
clock,
data,
rdreq,
reset_n,
wrreq,
// outputs:
empty,
full,
q
)
;
parameter FIFO_DEPTHS = 2;
parameter FIFO_WIDTHU = 1;
output empty;
output full;
output [ 35: 0] q;
input clock;
input [ 35: 0] data;
input rdreq;
input reset_n;
input wrreq;
wire empty;
wire full;
wire [ 35: 0] q;
wire wrreq_valid;
//the_scfifo, which is an e_instance
fifo_buffer_single_clock_fifo #(
.FIFO_DEPTHS(FIFO_DEPTHS),
.FIFO_WIDTHU(FIFO_WIDTHU)
) the_scfifo (
.aclr (~reset_n),
.clock (clock),
.data (data),
.empty (empty),
.full (full),
.q (q),
.rdreq (rdreq),
.wrreq (wrreq_valid)
);
assign wrreq_valid = wrreq & ~full;
endmodule
|
module fifo_buffer (
// inputs:
avalonmm_read_slave_read,
avalonmm_write_slave_write,
avalonmm_write_slave_writedata,
reset_n,
wrclock,
// outputs:
avalonmm_read_slave_readdata,
avalonmm_read_slave_waitrequest,
avalonmm_write_slave_waitrequest
)
;
parameter FIFO_DEPTHS = 2;
parameter FIFO_WIDTHU = 1;
output [ 35: 0] avalonmm_read_slave_readdata;
output avalonmm_read_slave_waitrequest;
output avalonmm_write_slave_waitrequest;
input avalonmm_read_slave_read;
input avalonmm_write_slave_write;
input [ 35: 0] avalonmm_write_slave_writedata;
input reset_n;
input wrclock;
wire [ 35: 0] avalonmm_read_slave_readdata;
wire avalonmm_read_slave_waitrequest;
wire avalonmm_write_slave_waitrequest;
wire clock;
wire [ 35: 0] data;
wire empty;
wire full;
wire [ 35: 0] q;
wire rdreq;
wire wrreq;
//the_scfifo_with_controls, which is an e_instance
fifo_buffer_scfifo_with_controls #(
.FIFO_DEPTHS(FIFO_DEPTHS),
.FIFO_WIDTHU(FIFO_WIDTHU)
) the_scfifo_with_controls
(
.clock (clock),
.data (data),
.empty (empty),
.full (full),
.q (q),
.rdreq (rdreq),
.reset_n (reset_n),
.wrreq (wrreq)
);
//in, which is an e_avalon_slave
//out, which is an e_avalon_slave
assign data = avalonmm_write_slave_writedata;
assign wrreq = avalonmm_write_slave_write;
assign avalonmm_read_slave_readdata = q;
assign rdreq = avalonmm_read_slave_read;
assign clock = wrclock;
assign avalonmm_write_slave_waitrequest = full;
assign avalonmm_read_slave_waitrequest = empty;
endmodule
|
module fifo_to_packet (
// Interface: clk
input clk,
input reset_n,
// Interface: ST out
input out_ready,
output reg out_valid,
output reg [ 7: 0] out_data,
output reg out_startofpacket,
output reg out_endofpacket,
// Interface: FIFO in
input [ 35: 0] fifo_readdata,
output reg fifo_read,
input fifo_empty
);
reg [ 1: 0] state;
reg enable, sent_all;
reg [ 1: 0] current_byte, byte_end;
reg first_trans, last_trans;
reg [ 23:0] fifo_data_buffer;
localparam POP_FIFO = 2'b00,
POP_FIFO_WAIT = 2'b01,
FIFO_DATA_WAIT = 2'b10,
READ_SEND_ISSUE = 2'b11;
always @* begin
enable = (!fifo_empty & sent_all);
end
always @(posedge clk or negedge reset_n) begin
if (!reset_n) begin
fifo_data_buffer <= 'b0;
out_startofpacket <= 1'b0;
out_endofpacket <= 1'b0;
out_valid <= 1'b0;
out_data <= 'b0;
state <= 'b0;
fifo_read <= 1'b0;
current_byte <= 'b0;
byte_end <= 'b0;
first_trans <= 1'b0;
last_trans <= 1'b0;
sent_all <= 1'b1;
end else begin
if (out_ready) begin
out_startofpacket <= 1'b0;
out_endofpacket <= 1'b0;
end
case (state)
POP_FIFO : begin
if (out_ready) begin
out_startofpacket <= 1'b0;
out_endofpacket <= 1'b0;
out_valid <= 1'b0;
first_trans <= 1'b0;
last_trans <= 1'b0;
byte_end <= 'b0;
fifo_read <= 1'b0;
sent_all <= 1'b1;
end
// start poping fifo after all data sent and data available
if (enable) begin
fifo_read <= 1'b1;
out_valid <= 1'b0;
state <= POP_FIFO_WAIT;
end
end
POP_FIFO_WAIT : begin
//fifo latency of 1
fifo_read <= 1'b0;
state <= FIFO_DATA_WAIT;
end
FIFO_DATA_WAIT : begin
sent_all <= 1'b0;
first_trans <= fifo_readdata[35];
last_trans <= fifo_readdata[34];
out_data <= fifo_readdata[7:0];
fifo_data_buffer <= fifo_readdata[31:8];
byte_end <= fifo_readdata[33:32];
current_byte <= 1'b1;
out_valid <= 1'b1;
// first byte sop eop handling
if (fifo_readdata[35] & fifo_readdata[34] & (fifo_readdata[33:32] == 0)) begin
first_trans <= 1'b0;
last_trans <= 1'b0;
out_startofpacket <= 1'b1;
out_endofpacket <= 1'b1;
state <= POP_FIFO;
end else if (fifo_readdata[35] & (fifo_readdata[33:32] == 0)) begin
first_trans <= 1'b0;
out_startofpacket <= 1'b1;
state <= POP_FIFO;
end else if (fifo_readdata[35]) begin
first_trans <= 1'b0;
out_startofpacket <= 1'b1;
state <= READ_SEND_ISSUE;
end else if (fifo_readdata[34] & (fifo_readdata[33:32] == 0)) begin
last_trans <= 1'b0;
out_endofpacket <= 1'b1;
state <= POP_FIFO;
end else begin
state <= READ_SEND_ISSUE;
end
end
READ_SEND_ISSUE : begin
out_valid <= 1'b1;
sent_all <= 1'b0;
if (out_ready) begin
out_startofpacket <= 1'b0;
// last byte
if (last_trans & (current_byte == byte_end)) begin
last_trans <= 1'b0;
out_endofpacket <= 1'b1;
state <= POP_FIFO;
end
case (current_byte)
3: begin
out_data <= fifo_data_buffer[23:16];
end
2: begin
out_data <= fifo_data_buffer[15:8];
end
1: begin
out_data <= fifo_data_buffer[7:0];
end
default: begin
//out_data <= fifo_readdata[7:0];
end
endcase
current_byte <= current_byte + 1'b1;
if (current_byte == byte_end) begin
state <= POP_FIFO;
end else begin
state <= READ_SEND_ISSUE;
end
end
end
endcase
end
end
endmodule
|
module packets_to_master (
// Interface: clk
input clk,
input reset_n,
// Interface: ST in
output reg in_ready,
input in_valid,
input [ 7: 0] in_data,
input in_startofpacket,
input in_endofpacket,
// Interface: ST out
input out_ready,
output reg out_valid,
output reg [ 7: 0] out_data,
output reg out_startofpacket,
output reg out_endofpacket,
// Interface: MM out
output reg [31: 0] address,
input [31: 0] readdata,
output reg read,
output reg write,
output reg [ 3: 0] byteenable,
output reg [31: 0] writedata,
input waitrequest,
input readdatavalid
);
// ---------------------------------------------------------------------
//| Parameter Declarations
// ---------------------------------------------------------------------
parameter EXPORT_MASTER_SIGNALS = 0;
// ---------------------------------------------------------------------
//| Command Declarations
// ---------------------------------------------------------------------
localparam CMD_WRITE_NON_INCR = 8'h00;
localparam CMD_WRITE_INCR = 8'h04;
localparam CMD_READ_NON_INCR = 8'h10;
localparam CMD_READ_INCR = 8'h14;
// ---------------------------------------------------------------------
//| Signal Declarations
// ---------------------------------------------------------------------
reg [ 3: 0] state;
reg [ 7: 0] command;
reg [ 1: 0] current_byte; //, result_byte;
reg [ 15: 0] counter;
reg [ 23: 0] read_data_buffer;
reg in_ready_0;
reg first_trans, last_trans;
reg [ 3: 0] unshifted_byteenable;
wire enable;
localparam READY = 4'b0000,
GET_EXTRA = 4'b0001,
GET_SIZE1 = 4'b0010,
GET_SIZE2 = 4'b0011,
GET_ADDR1 = 4'b0100,
GET_ADDR2 = 4'b0101,
GET_ADDR3 = 4'b0110,
GET_ADDR4 = 4'b0111,
GET_WRITE_DATA = 4'b1000,
WRITE_WAIT = 4'b1001,
RETURN_PACKET = 4'b1010,
READ_ASSERT = 4'b1011,
READ_CMD_WAIT = 4'b1100,
READ_DATA_WAIT = 4'b1101,
READ_SEND_ISSUE= 4'b1110,
READ_SEND_WAIT = 4'b1111;
// ---------------------------------------------------------------------
//| Thingofamagick
// ---------------------------------------------------------------------
assign enable = (in_ready & in_valid);
always @*
// in_ready = in_ready_0 & out_ready;
in_ready = in_ready_0;
always @(posedge clk or negedge reset_n) begin
if (!reset_n) begin
in_ready_0 <= 1'b0;
out_startofpacket <= 1'b0;
out_endofpacket <= 1'b0;
out_valid <= 1'b0;
out_data <= 'b0;
read <= 1'b0;
write <= 1'b0;
byteenable <= 'b0;
writedata <= 'b0;
address <= 'b0;
counter <= 'b0;
command <= 'b0;
first_trans <= 1'b0;
last_trans <= 1'b0;
state <= 'b0;
current_byte <= 'b0;
// result_byte <= 'b0;
read_data_buffer <= 'b0;
unshifted_byteenable <= 'b0;
end else begin
address[1:0] <= 'b0;
if (out_ready) begin
out_startofpacket <= 1'b0;
out_endofpacket <= 1'b0;
out_valid <= 1'b0;
end
in_ready_0 <= 1'b0;
if (counter >= 3) unshifted_byteenable <= 4'b1111;
else if (counter == 3) unshifted_byteenable <= 4'b0111;
else if (counter == 2) unshifted_byteenable <= 4'b0011;
else if (counter == 1) unshifted_byteenable <= 4'b0001;
case (state)
READY : begin
out_valid <= 1'b0;
in_ready_0 <= 1'b1;
end
GET_EXTRA : begin
in_ready_0 <= 1'b1;
byteenable <= 'b0;
if (enable) state <= GET_SIZE1;
end
GET_SIZE1 : begin
in_ready_0 <= 1'b1;
//load counter on reads only
counter[15:8] <= command[4]?in_data:8'b0;
if (enable) state <= GET_SIZE2;
end
GET_SIZE2 : begin
in_ready_0 <= 1'b1;
//load counter on reads only
counter[7:0] <= command[4]?in_data:8'b0;
if (enable) state <= GET_ADDR1;
end
GET_ADDR1 : begin
in_ready_0 <= 1'b1;
first_trans <= 1'b1;
last_trans <= 1'b0;
address[31:24] <= in_data;
if (enable) state <= GET_ADDR2;
end
GET_ADDR2 : begin
in_ready_0 <= 1'b1;
address[23:16] <= in_data;
if (enable) state <= GET_ADDR3;
end
GET_ADDR3 : begin
in_ready_0 <= 1'b1;
address[15:8] <= in_data;
if (enable) state <= GET_ADDR4;
end
GET_ADDR4 : begin
in_ready_0 <= 1'b1;
address[7:2] <= in_data[7:2];
current_byte <= in_data[1:0];
if (enable) begin
if (command == CMD_WRITE_NON_INCR | command == CMD_WRITE_INCR) begin
state <= GET_WRITE_DATA; //writes
in_ready_0 <= 1'b1;
end
else if (command == CMD_READ_NON_INCR | command == CMD_READ_INCR) begin
state <= READ_ASSERT; //reads
in_ready_0 <= 1'b0;
end
else begin
//nops
//treat all unrecognized commands as nops as well
state <= RETURN_PACKET;
out_startofpacket <= 1'b1;
out_data <= (8'h80 | command);
out_valid <= 1'b1;
current_byte <= 'h0;
in_ready_0 <= 1'b0;
end
end
end
GET_WRITE_DATA : begin
in_ready_0 <= 1;
if (enable) begin
counter <= counter + 1'b1;
//2 bit, should wrap by itself
current_byte <= current_byte + 1'b1;
if (in_endofpacket || current_byte == 3)
begin
in_ready_0 <= 0;
write <= 1'b1;
state <= WRITE_WAIT;
end
end
if (in_endofpacket) begin
last_trans <= 1'b1;
end
// handle byte writes properly
// drive data pins based on addresses
case (current_byte)
0: begin
writedata[7:0] <= in_data;
byteenable[0] <= 1;
end
1: begin
writedata[15:8] <= in_data;
byteenable[1] <= 1;
end
2: begin
writedata[23:16] <= in_data;
byteenable[2] <= 1;
end
3: begin
writedata[31:24] <= in_data;
byteenable[3] <= 1;
end
endcase
end
WRITE_WAIT : begin
in_ready_0 <= 0;
write <= 1'b1;
if (~waitrequest) begin
write <= 1'b0;
state <= GET_WRITE_DATA;
in_ready_0 <= 1;
byteenable <= 'b0;
if (command[2] == 1'b1) begin
//increment address, but word-align it
address[31:2] <= (address[31:2] + 1'b1);
end
if (last_trans) begin
state <= RETURN_PACKET;
out_startofpacket <= 1'b1;
out_data <= (8'h80 | command);
out_valid <= 1'b1;
current_byte <= 'h0;
in_ready_0 <= 1'b0;
end
end
end
RETURN_PACKET : begin
out_valid <= 1'b1;
if (out_ready) begin
case (current_byte)
// 0: begin
// out_startofpacket <= 1'b1;
// out_data <= (8'h80 | command);
// end
0: begin
out_data <= 8'b0;
end
1: begin
out_data <= counter[15:8];
end
2: begin
out_endofpacket <= 1'b1;
out_data <= counter[7:0];
end
default: begin
// out_data <= 8'b0;
// out_startofpacket <= 1'b0;
// out_endofpacket <= 1'b0;
end
endcase
current_byte <= current_byte + 1'b1;
if (current_byte == 3) begin
state <= READY;
out_valid <= 1'b0;
end
else state <= RETURN_PACKET;
end
end
READ_ASSERT : begin
if (current_byte == 3) byteenable <= unshifted_byteenable << 3;
if (current_byte == 2) byteenable <= unshifted_byteenable << 2;
if (current_byte == 1) byteenable <= unshifted_byteenable << 1;
if (current_byte == 0) byteenable <= unshifted_byteenable;
// byteenable <= unshifted_byteenable << current_byte;
read <= 1;
state <= READ_CMD_WAIT;
end
READ_CMD_WAIT : begin
read_data_buffer <= readdata[31:8];
out_data <= readdata[7:0];
read <= 1;
// if readdatavalid, take the data and
// go directly to READ_SEND_ISSUE. This is for fixed
// latency slaves. Ignore waitrequest in this case,
// since this master does not issue pipelined reads.
//
// For variable latency slaves, once waitrequest is low
// the read command is accepted, so deassert read and
// go to READ_DATA_WAIT to wait for readdatavalid
if (readdatavalid) begin
state <= READ_SEND_ISSUE;
read <= 0;
end else begin
if (~waitrequest) begin
state <= READ_DATA_WAIT;
read <= 0;
end
end
end
READ_DATA_WAIT : begin
read_data_buffer <= readdata[31:8];
out_data <= readdata[7:0];
if (readdatavalid) begin
state <= READ_SEND_ISSUE;
end
end
READ_SEND_ISSUE : begin
out_valid <= 1'b1;
out_startofpacket <= 'h0;
out_endofpacket <= 'h0;
if (counter == 1) begin
out_endofpacket <= 1'b1;
end
if (first_trans) begin
first_trans <= 1'b0;
out_startofpacket <= 1'b1;
end
case (current_byte)
3: begin
out_data <= read_data_buffer[23:16];
end
2: begin
out_data <= read_data_buffer[15:8];
end
1: begin
out_data <= read_data_buffer[7:0];
end
default: begin
out_data <= out_data;
end
endcase
state <= READ_SEND_WAIT;
end
READ_SEND_WAIT : begin
out_valid <= 1'b1;
if (out_ready) begin
counter <= counter - 1'b1;
current_byte <= current_byte + 1'b1;
out_valid <= 1'b0;
// count down on the number of bytes to read
// shift current byte location within word
// if increment address, add it, so the next read
// can use it, if more reads are required
// no more bytes to send - go to READY state
if (counter == 1) begin
state <= READY;
// end of current word, but we have more bytes to
// read - go back to READ_ASSERT
end else if (current_byte == 3) begin
if (command[2] == 1'b1) begin
//increment address, but word-align it
address[31:2] <= (address[31:2] + 1'b1);
end
state <= READ_ASSERT;
// continue sending current word
end else begin
state <= READ_SEND_ISSUE;
end
//maybe add in_ready_0 here so we are ready to go
//right away
end
end
endcase
if (enable & in_startofpacket) begin
state <= GET_EXTRA;
command <= in_data;
in_ready_0 <= 1'b1;
end
end // end else
end // end always block
endmodule
|
module sky130_fd_sc_hd__nor3b (
Y ,
A ,
B ,
C_N ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input C_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
|
module tb_top;
// DUT User defines
`include "pci_exp_params.v"
`include "pci_exp_dparams.v"
`include "pci_exp_ddefines.v"
// =============================================================================
// Regs for BFM & Test case
// =============================================================================
//---- Regs
reg clk_100;
reg error;
reg rst_n;
reg no_pcie_train; // This signal disables the training process
reg txtlpu_req ; // Request from TL for sending TLPs.
reg [63:0] txtlpu_data ; // Input data from TL.
reg txtlpu_st ; // start of TLP.
reg txtlpu_end ; // End of TLP.
reg txtlpu_nlfy ; // Nullify TLP.
reg ecrc_gen_enb ;
reg ecrc_chk_enb ;
reg rx_tlp_discard;
wire [23:0] tbtx_vc;
wire [23:0] tbrx_vc;
reg disable_mlfmd_check;
reg DISABLE_SKIP_CHECK;
wire [1:0] power_down_init;
wire [14:0] init_15_00;
wire [14:0] init_15_11;
wire [15:0] init_16_11;
reg enb_log;
//---- Wires
wire [2:0] rxdp_pmd_type;
wire [23:0] rxdp_vsd_data;
wire rxdp_vsd_val;
wire [1:0] rxdp_dllp_val;
wire dl_up;
wire sys_clk_125;
wire sys_clk_125_temp;
wire txdp_pm_sent;
wire [63:0] INIT_PH_FC; //Initial P HdrFC value
wire [63:0] INIT_NPH_FC; // For NPH
wire [63:0] INIT_CPLH_FC; // For CPLH
wire [95:0] INIT_PD_FC; // Initial P DataFC value
wire [95:0] INIT_NPD_FC; // For NPD
wire [95:0] INIT_CPLD_FC; // For CPLD
wire [71:0] tx_ca_ph;
wire [103:0] tx_ca_pd;
wire [71:0] tx_ca_nph;
wire [103:0] tx_ca_npd;
wire [71:0] tx_ca_cplh;
wire [103:0] tx_ca_cpld;
reg [7:0] tbrx_cmd_prsnt;
wire [7:0] tbrx_cmd_prsnt_int;
wire [7:0] ph_buf_status; // Indicate the Full/alm.Full status of the PH buffers
wire [7:0] pd_buf_status; // Indicate PD Buffer has got space less than Max Pkt size
wire [7:0] nph_buf_status; // For NPH
wire [7:0] npd_buf_status; // For NPD
wire [7:0] cplh_buf_status; // For CPLH
wire [7:0] cpld_buf_status; // For CPLD
wire [7:0] ph_processed; // TL has processed one TLP Header - PH Type
wire [7:0] pd_processed; // TL has processed one TLP Data - PD TYPE
wire [7:0] nph_processed; // For NPH
wire [7:0] npd_processed; // For NPD
wire [7:0] cplh_processed; // For CPLH
wire [7:0] cpld_processed; // For CPLD
//---------Outputs From Core------------
wire [7:0] tx_rdy;
wire [511:0] rx_data;
wire [7:0] rx_st;
wire [7:0] rx_end;
wire [7:0] rx_ecrc_err;
wire [7:0] rx_us_req;
wire [7:0] rx_malf_tlp;
wire [7:0] rx_pois_tlp;
wire [3:0] phy_ltssm_state;
wire [7:0] tx_req;
wire [2:0] rx_status;
wire [1:0] power_down;
wire tx_detect_rx;
wire tx_elec_idle;
wire tx_compliance;
wire rx_polarity;
wire [15:0] rx_valid;
wire [15:0] rx_elec_idle;
wire [15:0] phy_status;
wire rx_valid0; //For Debug
wire rx_elec_idle0;
wire phy_status0;
wire phy_realign_req;
//---- Integer
integer i;
//---------- TB_MUX signals
reg [3:0] tc_block_skip;
reg [3:0] tc_block_ts1;
reg [3:0] tc_mask_pad1;
reg [11:0] tc_allow_num1[0:3];
reg [3:0] tc_inv_polar;
reg [3:0] tc_change_laneid;
reg [3:0] tc_change_linkid;
reg [3:0] tc_change_nfts;
reg [31:0] tc_linkid;
reg [31:0] tc_laneid;
reg [31:0] tc_nfts;
wire [3:0] tbmux_allow_done1;
reg [3:0] tc_block_ts2;
reg [3:0] tc_mask_pad2;
reg [11:0] tc_allow_num2[0:3];
wire [3:0] tbmux_allow_done2;
reg [3:0] tc_force_ts1;
reg [3:0] tc_force_ts2;
reg [3:0] tc_linkid_en;
reg [3:0] tc_laneid_en;
reg [3:0] tc_lb;
reg [3:0] tc_dis;
reg [3:0] tc_hr;
reg [3:0] tc_force_EIos;
reg [3:0] tc_force_skip;
reg [3:0] tc_block_idle;
reg [4:0] tc_idle_cnt [0:3];
reg [3:0] tc_idle_gap;
reg [15:0] tx_lbk_data;
reg [1:0] tx_lbk_kcntl;
wire tx_lbk_rdy;
wire [15:0] rx_lbk_data;
wire [1:0] rx_lbk_kcntl;
wire [(`NUM_VC*16)-1:0] tx_data;
wire [`NUM_VC-1:0] tx_st;
wire [`NUM_VC-1:0] tx_end;
wire [`NUM_VC-1:0] tx_nlfy;
wire [`NUM_VC-1:0] tb_sys_clk;
parameter DLY1 = 1 ;
parameter DLY2 = 1 ;
// =============================================================================
// DUT Design params file
`include "pci_exp_ddefines.v"
// Include the test case
`include "test_rc.v"
// =============================================================================
//-------- For Flow Control Tasks
parameter P = 2'b00;
parameter NP = 2'b01;
parameter CPLX = 2'b10; //CPL is already used in some other paramter
parameter PH = 3'b000;
parameter PD = 3'b001;
parameter NPH = 3'b010;
parameter NPD = 3'b011;
parameter CPLH = 3'b100;
parameter CPLD = 3'b101;
//---- Wires
wire hdoutp_0 ;
wire hdoutn_0 ;
reg hdoutp_0_d ;
reg hdoutn_0_d ;
wire hdoutp_1 ;
wire hdoutn_1 ;
reg hdoutp_1_d ;
reg hdoutn_1_d ;
wire hdoutp_2 ;
wire hdoutn_2 ;
reg hdoutp_2_d ;
reg hdoutn_2_d ;
wire hdoutp_3 ;
wire hdoutn_3 ;
reg hdoutp_3_d ;
reg hdoutn_3_d ;
wire refclkp;
wire refclkn;
pullup (hdoutp_0);
pullup (hdoutn_0);
pullup (hdoutp_1);
pullup (hdoutn_1);
pullup (hdoutp_2);
pullup (hdoutn_2);
pullup (hdoutp_3);
pullup (hdoutn_3);
always @* begin
//0
if (!rst_n)
#DLY1 hdoutp_0_d <= hdoutp_0 ;
else if (hdoutp_0 == 1'b1)
#DLY1 hdoutp_0_d <= 1'b1 ;
else if (hdoutp_0 == 1'b0)
#DLY1 hdoutp_0_d <= 1'b0 ;
else if (hdoutp_0 === 1'bz)
#DLY1 hdoutp_0_d <= 1'b1 ;
else
#DLY1 hdoutp_0_d <= hdoutp_0_d ;
if (!rst_n)
#DLY1 hdoutn_0_d <= hdoutn_0 ;
else if (hdoutn_0 == 1'b1)
#DLY1 hdoutn_0_d <= 1'b1 ;
else if (hdoutn_0 == 1'b0)
#DLY1 hdoutn_0_d <= 1'b0 ;
else if (hdoutn_0 === 1'bz)
#DLY1 hdoutn_0_d <= 1'b1 ;
else
#DLY1 hdoutn_0_d <= hdoutn_0_d ;
end
always @* begin
//1
if (!rst_n)
#DLY1 hdoutp_1_d <= hdoutp_1 ;
else if (hdoutp_1 == 1'b1)
#DLY1 hdoutp_1_d <= 1'b1 ;
else if (hdoutp_1 == 1'b0)
#DLY1 hdoutp_1_d <= 1'b0 ;
else if (hdoutp_1 === 1'bz)
#DLY1 hdoutp_1_d <= 1'b1 ;
else
#DLY1 hdoutp_1_d <= hdoutp_1_d ;
if (!rst_n)
#DLY1 hdoutn_1_d <= hdoutn_1 ;
else if (hdoutn_1 == 1'b1)
#DLY1 hdoutn_1_d <= 1'b1 ;
else if (hdoutn_1 == 1'b0)
#DLY1 hdoutn_1_d <= 1'b0 ;
else if (hdoutn_1 === 1'bz)
#DLY1 hdoutn_1_d <= 1'b1 ;
else
#DLY1 hdoutn_1_d <= hdoutn_1_d ;
end
always @* begin
//2
if (!rst_n)
#DLY1 hdoutp_2_d <= hdoutp_2 ;
else if (hdoutp_2 == 1'b1)
#DLY1 hdoutp_2_d <= 1'b1 ;
else if (hdoutp_2 == 1'b0)
#DLY1 hdoutp_2_d <= 1'b0 ;
else if (hdoutp_2 === 1'bz)
#DLY1 hdoutp_2_d <= 1'b1 ;
else
#DLY1 hdoutp_2_d <= hdoutp_2_d ;
if (!rst_n)
#DLY1 hdoutn_2_d <= hdoutn_2 ;
else if (hdoutn_2 == 1'b1)
#DLY1 hdoutn_2_d <= 1'b1 ;
else if (hdoutn_2 == 1'b0)
#DLY1 hdoutn_2_d <= 1'b0 ;
else if (hdoutn_2 === 1'bz)
#DLY1 hdoutn_2_d <= 1'b1 ;
else
#DLY1 hdoutn_2_d <= hdoutn_2_d ;
end
always @* begin
//3
if (!rst_n)
#DLY1 hdoutp_3_d <= hdoutp_3 ;
else if (hdoutp_3 == 1'b1)
#DLY1 hdoutp_3_d <= 1'b1 ;
else if (hdoutp_3 == 1'b0)
#DLY1 hdoutp_3_d <= 1'b0 ;
else if (hdoutp_3 === 1'bz)
#DLY1 hdoutp_3_d <= 1'b1 ;
else
#DLY1 hdoutp_3_d <= hdoutp_3_d ;
if (!rst_n)
#DLY1 hdoutn_3_d <= hdoutn_3 ;
else if (hdoutn_3 == 1'b1)
#DLY1 hdoutn_3_d <= 1'b1 ;
else if (hdoutn_3 == 1'b0)
#DLY1 hdoutn_3_d <= 1'b0 ;
else if (hdoutn_3 === 1'bz)
#DLY1 hdoutn_3_d <= 1'b1 ;
else
#DLY1 hdoutn_3_d <= hdoutn_3_d ;
end
// =============================================================================
// PIPE_SIGNALS For Debug -- For X1
// =============================================================================
assign rx_valid0 = rx_valid[0];
assign rx_elec_idle0 = rx_elec_idle[0];
assign phy_status0 = phy_status[0];
// =============================================================================
// Generate tbrx_cmd_prsnt
// =============================================================================
always@(sys_clk_125) begin
tbrx_cmd_prsnt[7] <= (tbrx_cmd_prsnt_int[7] === 1'b1) ? 1'b1 : 1'b0;
tbrx_cmd_prsnt[6] <= (tbrx_cmd_prsnt_int[6] === 1'b1) ? 1'b1 : 1'b0;
tbrx_cmd_prsnt[5] <= (tbrx_cmd_prsnt_int[5] === 1'b1) ? 1'b1 : 1'b0;
tbrx_cmd_prsnt[4] <= (tbrx_cmd_prsnt_int[4] === 1'b1) ? 1'b1 : 1'b0;
tbrx_cmd_prsnt[3] <= (tbrx_cmd_prsnt_int[3] === 1'b1) ? 1'b1 : 1'b0;
tbrx_cmd_prsnt[2] <= (tbrx_cmd_prsnt_int[2] === 1'b1) ? 1'b1 : 1'b0;
tbrx_cmd_prsnt[1] <= (tbrx_cmd_prsnt_int[1] === 1'b1) ? 1'b1 : 1'b0;
tbrx_cmd_prsnt[0] <= (tbrx_cmd_prsnt_int[0] === 1'b1) ? 1'b1 : 1'b0;
end
assign tbrx_vc = 3'd0;
assign tbtx_vc = 3'd0;
assign power_down_init = 2'b10;
assign init_15_00 = 15'b0000_0000_0000_000;
assign init_15_11 = 15'b1111_1111_1111_111;
assign init_16_11 = 16'b1111_1111_1111_1111;
// =============================================================================
// TBTX (User Logic on TX side) Instantiations
// =============================================================================
tbtx u_tbtx [`NUM_VC-1:0] (
//----- Inputs
.sys_clk (sys_clk_125),
.rst_n (rst_n),
.tx_tc (tbtx_vc[(`NUM_VC*3)-1:0]),
.tx_ca_ph (tx_ca_ph[(9*`NUM_VC)-1:0]),
.tx_ca_pd (tx_ca_pd[(13*`NUM_VC)-1:0]),
.tx_ca_nph (tx_ca_nph[(9*`NUM_VC)-1:0]),
.tx_ca_npd (tx_ca_npd[(13*`NUM_VC)-1:0]),
.tx_ca_cplh (tx_ca_cplh[(9*`NUM_VC)-1:0]),
.tx_ca_cpld (tx_ca_cpld[(13*`NUM_VC)-1:0]),
.tx_ca_p_recheck ( 1'b0 ),
.tx_ca_cpl_recheck ( 1'b0 ),
.tx_rdy (tx_rdy[`NUM_VC-1:0]),
//------- Outputs
.tx_req (tx_req[`NUM_VC-1:0]),
.tx_data (tx_data),
.tx_st (tx_st),
.tx_end (tx_end),
.tx_nlfy (tx_nlfy)
);
// =============================================================================
// TBRX (User Logic on RX side) Instantiations
// =============================================================================
tbrx u_tbrx [`NUM_VC-1:0] (
//----- Inputs
.sys_clk (sys_clk_125),
.rst_n (rst_n),
.rx_tc (tbrx_vc[(`NUM_VC*3)-1:0]),
.rx_data ( rx_data[(`NUM_VC*16)-1:0]),
.rx_st ( rx_st[`NUM_VC -1:0]),
.rx_end ( rx_end[`NUM_VC -1:0]),
`ifdef ECRC
.rx_ecrc_err ( rx_ecrc_err[`NUM_VC -1:0] ),
`endif
.rx_us_req ( rx_us_req[`NUM_VC -1:0] ),
.rx_malf_tlp ( rx_malf_tlp[`NUM_VC -1:0] ),
//------- Outputs
.tbrx_cmd_prsnt (tbrx_cmd_prsnt_int[`NUM_VC-1:0]),
.ph_buf_status (ph_buf_status[`NUM_VC-1:0]),
.pd_buf_status (pd_buf_status[`NUM_VC-1:0]),
.nph_buf_status (nph_buf_status[`NUM_VC-1:0]),
.npd_buf_status (npd_buf_status[`NUM_VC-1:0]),
.cplh_buf_status (cplh_buf_status[`NUM_VC-1:0]),
.cpld_buf_status (cpld_buf_status[`NUM_VC-1:0]),
.ph_processed (ph_processed[`NUM_VC-1:0]),
.pd_processed (pd_processed[`NUM_VC-1:0]),
.nph_processed (nph_processed[`NUM_VC-1:0]),
.npd_processed (npd_processed[`NUM_VC-1:0]),
.cplh_processed (cplh_processed[`NUM_VC-1:0]),
.cpld_processed (cpld_processed[`NUM_VC-1:0]),
.pd_num ( ),
.npd_num ( ),
.cpld_num ( ),
.INIT_PH_FC ( ),
.INIT_NPH_FC ( ),
.INIT_CPLH_FC ( ),
.INIT_PD_FC ( ),
.INIT_NPD_FC ( ),
.INIT_CPLD_FC ( )
);
// =============================================================================
// DUT
// =============================================================================
`USERNAME_EVAL_TOP u1_top(
//------- Clock and Reset
.refclkp ( clk_100),
.refclkn ( ~clk_100),
.sys_clk_125 ( sys_clk_125_temp ),
.rst_n ( rst_n ),
.hdinp0 ( hdoutp_0_d ),
.hdinn0 ( hdoutn_0_d ),
.hdoutp0 ( hdoutp_0 ),
.hdoutn0 ( hdoutn_0 ),
// To RXFC
// Following are Advertised during Initialization
.tx_req_vc0 (tx_req[0]),
.tx_data_vc0 (tx_data[16*1-1:0]),
.tx_st_vc0 (tx_st[0]),
.tx_end_vc0 (tx_end[0]),
.tx_nlfy_vc0 (tx_nlfy[0]),
.ph_buf_status_vc0 (ph_buf_status[0]),
.pd_buf_status_vc0 (pd_buf_status[0]),
.nph_buf_status_vc0 (nph_buf_status[0]),
.npd_buf_status_vc0 (npd_buf_status[0]),
.cplh_buf_status_vc0 (cplh_buf_status[0]),
.cpld_buf_status_vc0 (cpld_buf_status[0]),
.ph_processed_vc0 (ph_processed[0]),
.pd_processed_vc0 (pd_processed[0]),
.nph_processed_vc0 (nph_processed[0]),
.npd_processed_vc0 (npd_processed[0]),
.cplh_processed_vc0 (cplh_processed[0]),
.cpld_processed_vc0 (cpld_processed[0]),
`ifdef ECRC
.ecrc_gen_enb ( ecrc_gen_enb ) ,
.ecrc_chk_enb ( ecrc_chk_enb ) ,
`endif
.tx_rdy_vc0 (tx_rdy[0]),
.tx_ca_ph_vc0 (tx_ca_ph[(9*1)-1:0]),
.tx_ca_pd_vc0 (tx_ca_pd[(13*1)-1:0]),
.tx_ca_nph_vc0 (tx_ca_nph[(9*1)-1:0]),
.tx_ca_npd_vc0 (tx_ca_npd[(13*1)-1:0]),
.tx_ca_cplh_vc0 (tx_ca_cplh[(9*1)-1:0]),
.tx_ca_cpld_vc0 (tx_ca_cpld[(13*1)-1:0]),
// Inputs/Outputs per VC
.rx_data_vc0 ( rx_data[(16*1)-1:0]),
.rx_st_vc0 ( rx_st[0]),
.rx_end_vc0 ( rx_end[0]),
`ifdef ECRC
.rx_ecrc_err_vc0 ( rx_ecrc_err[0] ),
`endif
.rx_pois_tlp_vc0 ( rx_pois_tlp[0] ),
.rx_malf_tlp_vc0 ( rx_malf_tlp[0] ),
.inta_n ( ),
.intb_n ( ),
.intc_n ( ),
.intd_n ( ),
.ftl_err_msg ( ),
.nftl_err_msg ( ),
.cor_err_msg ( )
);
// ====================================================================
// Initilize the design
// ====================================================================
initial begin
error = 1'b0;
rst_n = 1'b0;
clk_100 = 1'b0;
rx_tlp_discard = 0;
enb_log = 1'b0 ;
ecrc_gen_enb = 1'b0;
ecrc_chk_enb = 1'b0;
end
// =============================================================================
// Timeout generation to finish hung test cases.
// =============================================================================
parameter TIMEOUT_NUM = 150000;
initial begin
repeat (TIMEOUT_NUM) @(posedge sys_clk_125);
$display(" ERROR : First - Simulation Time Out, Test case Terminated at time : %0t", $time) ;
repeat (TIMEOUT_NUM) @(posedge sys_clk_125);
$display(" ERROR : Second - Simulation Time Out, Test case Terminated at time : %0t", $time) ;
//$finish ;
end
// =============================================================================
// Simulation Time Display for long test cases
initial begin
forever begin
#100000; //every 10k (add extra zero - timescale) ns just display Time value - useful for SDF sim
$display(" Displaying Sim. Time : %0t", $time) ;
end
end
// =============================================================================
initial begin
$timeformat (-9 ,1 , "ns", 10);
`ifdef REGRESS
`else
`ifdef NO_DUMP
`else
//$recordfile ("pcie_test.trn");
//$recordvars ();
//$shm_open ("pcie_test.shm");
//$shm_probe ("ACMTF");
`endif
`endif
end
// =============================================================================
// Clocks generation
// =============================================================================
// 100 Mhz clock input to PLL to generate 125MHz for PCS
always #50 clk_100 <= ~clk_100 ;
`ifdef SDF_SIM
assign sys_clk_125 = u1_top.sys_clk_125_c;
assign tb_sys_clk = u1_top.\u1_pcie_top/pclk;
`else
assign sys_clk_125 = sys_clk_125_temp;
assign tb_sys_clk = u1_top.u1_pcie_top.pclk;
`endif
// =============================================================================
// =============================================================================
initial begin
`ifdef SDF_SIM
//$sdf_annotate("../../../../par/ecp2m/config1/synplicity/top/verilog/pci_exp_x4_top.sdf", u1_top,, "pci_exp_x4_top_sdf.log");
`endif
end
// =============================================================================
// Reset Task
// =============================================================================
task RST_DUT;
begin
repeat(2) @(negedge clk_100);
#40000;
rst_n = 1'b1;
repeat (50) @ (posedge clk_100) ;
force u1_top.u1_pcie_top.core_rst_n = 1'b1; // de-assert delayed reset to core
repeat(10) @(negedge clk_100);
end
endtask
// =============================================================================
// Reset Task
// =============================================================================
task DEFAULT_CREDITS;
reg [2:0] tmp_vcid;
begin
for(i=0; i<= `NUM_VC-1; i=i+1) begin
tmp_vcid = i;
case(tmp_vcid)
`ifdef EN_VC0
0 : begin
u_tbrx[0].FC_INIT(P, 8'd127, 12'd2047);
u_tbrx[0].FC_INIT(NP, 8'd127, 12'd2047);
u_tbrx[0].FC_INIT(CPLX, 8'd127, 12'd2047);
end
`endif
`ifdef EN_VC1
1 : begin
u_tbrx[1].FC_INIT(P, 8'd127, 12'd2047);
u_tbrx[1].FC_INIT(NP, 8'd127, 12'd2047);
u_tbrx[1].FC_INIT(CPLX, 8'd127, 12'd2047);
end
`endif
`ifdef EN_VC2
2 : begin
u_tbrx[2].FC_INIT(P, 8'd127, 12'd2047);
u_tbrx[2].FC_INIT(NP, 8'd127, 12'd2047);
u_tbrx[2].FC_INIT(CPLX, 8'd127, 12'd2047);
end
`endif
`ifdef EN_VC3
3 : begin
u_tbrx[3].FC_INIT(P, 8'd127, 12'd2047);
u_tbrx[3].FC_INIT(NP, 8'd127, 12'd2047);
u_tbrx[3].FC_INIT(CPLX, 8'd127, 12'd2047);
end
`endif
`ifdef EN_VC5
4 : begin
u_tbrx[4].FC_INIT(P, 8'd127, 12'd2047);
u_tbrx[4].FC_INIT(NP, 8'd127, 12'd2047);
u_tbrx[4].FC_INIT(CPLX, 8'd127, 12'd2047);
end
`endif
`ifdef EN_VC5
5 : begin
u_tbrx[5].FC_INIT(P, 8'd127, 12'd2047);
u_tbrx[5].FC_INIT(NP, 8'd127, 12'd2047);
u_tbrx[5].FC_INIT(CPLX, 8'd127, 12'd2047);
end
`endif
`ifdef EN_VC6
6 : begin
u_tbrx[6].FC_INIT(P, 8'd127, 12'd2047);
u_tbrx[6].FC_INIT(NP, 8'd127, 12'd2047);
u_tbrx[6].FC_INIT(CPLX, 8'd127, 12'd2047);
end
`endif
`ifdef EN_VC7
7 : begin
u_tbrx[7].FC_INIT(P, 8'd127, 12'd2047);
u_tbrx[7].FC_INIT(NP, 8'd127, 12'd2047);
u_tbrx[7].FC_INIT(CPLX, 8'd127, 12'd2047);
end
`endif
endcase
end
end
endtask
// =============================================================================
// Check on error signal & stop simulation if error = 1
// =============================================================================
always @(posedge sys_clk_125) begin
if (error) begin
repeat (200) @(posedge sys_clk_125);
$finish;
end
end
// =============================================================================
// TBTX TASKS
// =============================================================================
// HEADER FORMAT FOR MEM READ
// (Fmt & Type decides what kind of Request)
// ================================================
// R Fmt Type R TC R R R R TD EP ATTR R Length
// Requester ID -- TAG -- Last DW BE -- First DW BE
// ---------- Address [63:32] -------------------
// --------- Address [31:2] ----------------- R
// ================================================
// Fixed values :
// Fmt[1] = 0
// First DW BE = 4'b0000
// Last DW BE = 4'b0000
// ATTR is always 2'b00 {Ordering, Snoop} = {0,0} -> {Strong Order, Snoop}
// Arguments :
// TC/VC, Address[31:2], Fmt[0]/hdr_Type, Length
// Registers that are used :
// TBTX_TD, TBTX_EP, First_DW_BE, TBTX_UPPER32_ADDR
// For hdr_type 4 DW TBTX_UPPER32_ADDR is used (and Fmt[0] = 1)
//
// NOTE : Length is not the LENGTH of this MEM_RD Pkt
// =============================================================================
task tbtx_mem_rd;
input [2:0] vcid;
input [31:0] addr;
input [9:0] length;
input hdr_type; //0: 3 DW Header --- 1: 4 DW (with TBTX_UPPER32_ADDR)
begin
//tbtx_vc = vcid;
case(vcid)
`ifdef EN_VC0
0 : u_tbtx[0].tbtx_mem_rd(addr,length,hdr_type);
`endif
`ifdef EN_VC1
1 : u_tbtx[1].tbtx_mem_rd(addr,length,hdr_type);
`endif
`ifdef EN_VC2
2 : u_tbtx[2].tbtx_mem_rd(addr,length,hdr_type);
`endif
`ifdef EN_VC3
3 : u_tbtx[3].tbtx_mem_rd(addr,length,hdr_type);
`endif
`ifdef EN_VC4
4 : u_tbtx[4].tbtx_mem_rd(addr,length,hdr_type);
`endif
`ifdef EN_VC5
5 : u_tbtx[5].tbtx_mem_rd(addr,length,hdr_type);
`endif
`ifdef EN_VC6
6 : u_tbtx[6].tbtx_mem_rd(addr,length,hdr_type);
`endif
`ifdef EN_VC7
7 : u_tbtx[7].tbtx_mem_rd(addr,length,hdr_type);
`endif
endcase
end
endtask
// =============================================================================
// HEADER FORMAT FOR MEM WRITE
// (Fmt & Type decides what kind of Request)
// ================================================
// R Fmt Type R TC R R R R TD EP ATTR R Length
// Requester ID -- TAG -- Last DW BE -- First DW BE
// ---------- Address [63:32] -------------------
// --------- Address [31:2] ----------------- R
// ================================================
// Arguments :
// TC/VC, Address[31:2], Fmt[0]/hdr_Type
// Registers that are used :
// TBTX_TD, TBTX_EP, First_DW_BE, Last_DW_BE, TBTX_UPPER32_ADDR
// For hdr_type 4 DW TBTX_UPPER32_ADDR is used (and Fmt[0] = 1)
// =============================================================================
task tbtx_mem_wr;
input [2:0] vcid;
input [31:0] addr;
input [9:0] length;
input hdr_type; //3 DW or 4 DW
input [9:0] nul_len;
input nullify;
begin
//tbtx_vc = vcid;
case(vcid)
`ifdef EN_VC0
0 : u_tbtx[0].tbtx_mem_wr(addr, length,hdr_type, nul_len, nullify);
`endif
`ifdef EN_VC1
1 : u_tbtx[1].tbtx_mem_wr(addr, length,hdr_type, nul_len, nullify);
`endif
`ifdef EN_VC2
2 : u_tbtx[2].tbtx_mem_wr(addr, length,hdr_type, nul_len, nullify);
`endif
`ifdef EN_VC3
3 : u_tbtx[3].tbtx_mem_wr(addr, length,hdr_type, nul_len, nullify);
`endif
`ifdef EN_VC4
4 : u_tbtx[4].tbtx_mem_wr(addr, length,hdr_type, nul_len, nullify);
`endif
`ifdef EN_VC5
5 : u_tbtx[5].tbtx_mem_wr(addr, length,hdr_type, nul_len, nullify);
`endif
`ifdef EN_VC6
6 : u_tbtx[6].tbtx_mem_wr(addr, length,hdr_type, nul_len, nullify);
`endif
`ifdef EN_VC7
7 : u_tbtx[7].tbtx_mem_wr(addr, length,hdr_type, nul_len, nullify);
`endif
endcase
end
endtask
// =============================================================================
task tbtx_msg;
input [2:0] vcid;
begin
//tbtx_vc = vcid;
case(vcid)
`ifdef EN_VC0
0 : u_tbtx[0].tbtx_msg;
`endif
`ifdef EN_VC1
1 : u_tbtx[1].tbtx_msg;
`endif
`ifdef EN_VC2
2 : u_tbtx[2].tbtx_msg;
`endif
`ifdef EN_VC3
3 : u_tbtx[3].tbtx_msg;
`endif
`ifdef EN_VC4
4 : u_tbtx[4].tbtx_msg;
`endif
`ifdef EN_VC5
5 : u_tbtx[5].tbtx_msg;
`endif
`ifdef EN_VC6
6 : u_tbtx[6].tbtx_msg;
`endif
`ifdef EN_VC7
7 : u_tbtx[7].tbtx_msg;
`endif
endcase
end
endtask
// =============================================================================
task tbtx_msg_d;
input [2:0] vcid;
input [9:0] length;
input [9:0] nul_len;
input nullify;
begin
//tbtx_vc = vcid;
case(vcid)
`ifdef EN_VC0
0 : u_tbtx[0].tbtx_msg_d(length, nul_len, nullify);
`endif
`ifdef EN_VC1
1 : u_tbtx[1].tbtx_msg_d(length, nul_len, nullify);
`endif
`ifdef EN_VC2
2 : u_tbtx[2].tbtx_msg_d(length, nul_len, nullify);
`endif
`ifdef EN_VC3
3 : u_tbtx[3].tbtx_msg_d(length, nul_len, nullify);
`endif
`ifdef EN_VC4
4 : u_tbtx[4].tbtx_msg_d(length, nul_len, nullify);
`endif
`ifdef EN_VC5
5 : u_tbtx[5].tbtx_msg_d(length, nul_len, nullify);
`endif
`ifdef EN_VC6
6 : u_tbtx[6].tbtx_msg_d(length, nul_len, nullify);
`endif
`ifdef EN_VC7
7 : u_tbtx[7].tbtx_msg_d(length, nul_len, nullify);
`endif
endcase
end
endtask
// =============================================================================
task tbtx_cfg_rd;
input cfg; //0: cfg0, 1: cfg1
input [31:0] addr; //{Bus No, Dev. No, Function No, 4'h0, Ext Reg No, Reg No, 2'b00}
begin
u_tbtx[0].tbtx_cfg_rd(cfg, addr);
end
endtask
// =============================================================================
task tbtx_cfg_wr;
input cfg; //0: cfg0, 1: cfg1
input [31:0] addr; //{Bus No, Dev. No, Function No, 4'h0, Ext Reg No, Reg No, 2'b00}
begin
u_tbtx[0].tbtx_cfg_wr(cfg, addr);
end
endtask
// =============================================================================
task tbtx_io_rd;
input [31:0] addr;
begin
u_tbtx[0].tbtx_io_rd(addr);
end
endtask
// =============================================================================
task tbtx_io_wr;
input [31:0] addr;
begin
u_tbtx[0].tbtx_io_wr(addr);
end
endtask
// =============================================================================
task tbtx_cpl;
input [2:0] vcid;
input [11:0] byte_cnt;
input [6:0] lower_addr;
input [2:0] status;
begin
//tbtx_vc = vcid;
case(vcid)
`ifdef EN_VC0
0 : u_tbtx[0].tbtx_cpl(byte_cnt, lower_addr,status);
`endif
`ifdef EN_VC1
1 : u_tbtx[1].tbtx_cpl(byte_cnt, lower_addr,status);
`endif
`ifdef EN_VC2
2 : u_tbtx[2].tbtx_cpl(byte_cnt, lower_addr,status);
`endif
`ifdef EN_VC3
3 : u_tbtx[3].tbtx_cpl(byte_cnt, lower_addr,status);
`endif
`ifdef EN_VC4
4 : u_tbtx[4].tbtx_cpl(byte_cnt, lower_addr,status);
`endif
`ifdef EN_VC5
5 : u_tbtx[5].tbtx_cpl(byte_cnt, lower_addr,status);
`endif
`ifdef EN_VC6
6 : u_tbtx[6].tbtx_cpl(byte_cnt, lower_addr,status);
`endif
`ifdef EN_VC7
7 : u_tbtx[7].tbtx_cpl(byte_cnt, lower_addr,status);
`endif
endcase
end
endtask
// =============================================================================
task tbtx_cpl_d;
input [2:0] vcid;
input [11:0] byte_cnt;
input [6:0] lower_addr;
input [2:0] status;
input [9:0] length;
input [9:0] nul_len;
input nullify;
begin
//tbtx_vc = vcid;
case(vcid)
`ifdef EN_VC0
0 : u_tbtx[0].tbtx_cpl_d(byte_cnt, lower_addr,status, length, nul_len, nullify);
`endif
`ifdef EN_VC1
1 : u_tbtx[1].tbtx_cpl_d(byte_cnt, lower_addr,status, length, nul_len, nullify);
`endif
`ifdef EN_VC2
2 : u_tbtx[2].tbtx_cpl_d(byte_cnt, lower_addr,status, length, nul_len, nullify);
`endif
`ifdef EN_VC3
3 : u_tbtx[3].tbtx_cpl_d(byte_cnt, lower_addr,status, length, nul_len, nullify);
`endif
`ifdef EN_VC4
4 : u_tbtx[4].tbtx_cpl_d(byte_cnt, lower_addr,status, length, nul_len, nullify);
`endif
`ifdef EN_VC5
5 : u_tbtx[5].tbtx_cpl_d(byte_cnt, lower_addr,status, length, nul_len, nullify);
`endif
`ifdef EN_VC6
6 : u_tbtx[6].tbtx_cpl_d(byte_cnt, lower_addr,status, length, nul_len, nullify);
`endif
`ifdef EN_VC7
7 : u_tbtx[7].tbtx_cpl_d(byte_cnt, lower_addr,status, length, nul_len, nullify);
`endif
endcase
end
endtask
// =============================================================================
// TBRX TASKS
// =============================================================================
// Error Types
// NO_TLP_ERR = 4'b0000;
// ECRC_ERR = 4'b0001;
// UNSUP_ERR = 4'b0010;
// MALF_ERR = 4'b0011;
// FMT_TYPE_ERR = 4'b1111;
// =============================================================================
// tbrx_tlp:
// This task is used when User wants create TLP manually
// For fmt_type error this should be used, no other tasks supports this error.
// =============================================================================
task tbrx_tlp; //When Giving Malformed TLP (Only fmt & Type error)
input [2:0] vcid;
input [3:0] Error_Type;
input hdr_type; //3 DW or 4 DW
input [31:0] h1_msb;
input [31:0] h1_lsb;
input [31:0] h2_msb;
input [31:0] h2_lsb;
begin
case(vcid)
`ifdef EN_VC0
0 : u_tbrx[0].tbrx_tlp(Error_Type, hdr_type, h1_msb, h1_lsb, h2_msb, h2_lsb);
`endif
`ifdef EN_VC1
1 : u_tbrx[1].tbrx_tlp(Error_Type, hdr_type, h1_msb, h1_lsb, h2_msb, h2_lsb);
`endif
`ifdef EN_VC2
2 : u_tbrx[2].tbrx_tlp(Error_Type, hdr_type, h1_msb, h1_lsb, h2_msb, h2_lsb);
`endif
`ifdef EN_VC3
3 : u_tbrx[3].tbrx_tlp(Error_Type, hdr_type, h1_msb, h1_lsb, h2_msb, h2_lsb);
`endif
`ifdef EN_VC4
4 : u_tbrx[4].tbrx_tlp(Error_Type, hdr_type, h1_msb, h1_lsb, h2_msb, h2_lsb);
`endif
`ifdef EN_VC5
5 : u_tbrx[5].tbrx_tlp(Error_Type, hdr_type, h1_msb, h1_lsb, h2_msb, h2_lsb);
`endif
`ifdef EN_VC6
6 : u_tbrx[6].tbrx_tlp(Error_Type, hdr_type, h1_msb, h1_lsb, h2_msb, h2_lsb);
`endif
`ifdef EN_VC7
7 : u_tbrx[7].tbrx_tlp(Error_Type, hdr_type, h1_msb, h1_lsb, h2_msb, h2_lsb);
`endif
endcase
end
endtask
// =============================================================================
task tbrx_mem_rd;
input [2:0] vcid;
input [31:0] addr;
input [9:0] length;
input hdr_type; //3 DW or 4 DW
input [3:0] Error_Type;
begin
case(vcid)
`ifdef EN_VC0
0 : u_tbrx[0].tbrx_mem_rd(addr,length,hdr_type,Error_Type);
`endif
`ifdef EN_VC1
1 : u_tbrx[1].tbrx_mem_rd(addr,length,hdr_type,Error_Type);
`endif
`ifdef EN_VC2
2 : u_tbrx[2].tbrx_mem_rd(addr,length,hdr_type,Error_Type);
`endif
`ifdef EN_VC3
3 : u_tbrx[3].tbrx_mem_rd(addr,length,hdr_type,Error_Type);
`endif
`ifdef EN_VC4
4 : u_tbrx[4].tbrx_mem_rd(addr,length,hdr_type,Error_Type);
`endif
`ifdef EN_VC5
5 : u_tbrx[5].tbrx_mem_rd(addr,length,hdr_type,Error_Type);
`endif
`ifdef EN_VC6
6 : u_tbrx[6].tbrx_mem_rd(addr,length,hdr_type,Error_Type);
`endif
`ifdef EN_VC7
7 : u_tbrx[7].tbrx_mem_rd(addr,length,hdr_type,Error_Type);
`endif
endcase
end
endtask
// =============================================================================
task tbrx_mem_wr;
input [2:0] vcid;
input [31:0] addr;
input [9:0] length;
input hdr_type; //3 DW or 4 DW
input [3:0] Error_Type;
begin
case(vcid)
`ifdef EN_VC0
0 : u_tbrx[0].tbrx_mem_wr(addr,length,hdr_type,Error_Type);
`endif
`ifdef EN_VC1
1 : u_tbrx[1].tbrx_mem_wr(addr,length,hdr_type,Error_Type);
`endif
`ifdef EN_VC2
2 : u_tbrx[2].tbrx_mem_wr(addr,length,hdr_type,Error_Type);
`endif
`ifdef EN_VC3
3 : u_tbrx[3].tbrx_mem_wr(addr,length,hdr_type,Error_Type);
`endif
`ifdef EN_VC4
4 : u_tbrx[4].tbrx_mem_wr(addr,length,hdr_type,Error_Type);
`endif
`ifdef EN_VC5
5 : u_tbrx[5].tbrx_mem_wr(addr,length,hdr_type,Error_Type);
`endif
`ifdef EN_VC6
6 : u_tbrx[6].tbrx_mem_wr(addr,length,hdr_type,Error_Type);
`endif
`ifdef EN_VC7
7 : u_tbrx[7].tbrx_mem_wr(addr,length,hdr_type,Error_Type);
`endif
endcase
end
endtask
// =============================================================================
task tbrx_msg;
input [2:0] vcid;
input [9:0] length;
input [3:0] Error_Type;
begin
case(vcid)
`ifdef EN_VC0
0 : u_tbrx[0].tbrx_msg(length,Error_Type);
`endif
`ifdef EN_VC1
1 : u_tbrx[1].tbrx_msg(length,Error_Type);
`endif
`ifdef EN_VC2
2 : u_tbrx[2].tbrx_msg(length,Error_Type);
`endif
`ifdef EN_VC3
3 : u_tbrx[3].tbrx_msg(length,Error_Type);
`endif
`ifdef EN_VC4
4 : u_tbrx[4].tbrx_msg(length,Error_Type);
`endif
`ifdef EN_VC5
5 : u_tbrx[5].tbrx_msg(length,Error_Type);
`endif
`ifdef EN_VC6
6 : u_tbrx[6].tbrx_msg(length,Error_Type);
`endif
`ifdef EN_VC7
7 : u_tbrx[7].tbrx_msg(length,Error_Type);
`endif
endcase
end
endtask
// =============================================================================
task tbrx_msg_d;
input [2:0] vcid;
input [9:0] length;
input [3:0] Error_Type;
begin
case(vcid)
`ifdef EN_VC0
0 : u_tbrx[0].tbrx_msg_d(length, Error_Type);
`endif
`ifdef EN_VC1
1 : u_tbrx[1].tbrx_msg_d(length, Error_Type);
`endif
`ifdef EN_VC2
2 : u_tbrx[2].tbrx_msg_d(length, Error_Type);
`endif
`ifdef EN_VC3
3 : u_tbrx[3].tbrx_msg_d(length, Error_Type);
`endif
`ifdef EN_VC4
4 : u_tbrx[4].tbrx_msg_d(length, Error_Type);
`endif
`ifdef EN_VC5
5 : u_tbrx[5].tbrx_msg_d(length, Error_Type);
`endif
`ifdef EN_VC6
6 : u_tbrx[6].tbrx_msg_d(length, Error_Type);
`endif
`ifdef EN_VC7
7 : u_tbrx[7].tbrx_msg_d(length, Error_Type);
`endif
endcase
end
endtask
// =============================================================================
task tbrx_cfg_rd;
input cfg; //0: cfg0, 1: cfg1
input [31:0] addr; //{Bus No, Dev. No, Function No, 4'h0, Ext Reg No, Reg No, 2'b00}
input [9:0] length;
input [3:0] Error_Type;
begin
u_tbrx[0].tbrx_cfg_rd(cfg, addr,length, Error_Type);
end
endtask
// =============================================================================
task tbrx_cfg_wr;
input cfg; //0: cfg0, 1: cfg1
input [31:0] addr; //{Bus No, Dev. No, Function No, 4'h0, Ext Reg No, Reg No, 2'b00}
input [9:0] length;
input [3:0] Error_Type;
begin
u_tbrx[0].tbrx_cfg_wr(cfg, addr,length, Error_Type);
end
endtask
// =============================================================================
task tbrx_io_rd;
input [31:0] addr;
input [9:0] length;
input [3:0] Error_Type;
begin
u_tbrx[0].tbrx_io_rd(addr,length, Error_Type);
end
endtask
// =============================================================================
task tbrx_io_wr;
input [31:0] addr;
input [9:0] length;
input [3:0] Error_Type;
begin
u_tbrx[0].tbrx_io_wr(addr,length, Error_Type);
end
endtask
// =============================================================================
task tbrx_cpl;
input [2:0] vcid;
input [11:0] byte_cnt;
input [6:0] lower_addr;
input [2:0] status;
input [9:0] length;
input [3:0] Error_Type;
begin
case(vcid)
`ifdef EN_VC0
0 : u_tbrx[0].tbrx_cpl(byte_cnt, lower_addr,status,length, Error_Type);
`endif
`ifdef EN_VC1
1 : u_tbrx[1].tbrx_cpl(byte_cnt, lower_addr,status,length, Error_Type);
`endif
`ifdef EN_VC2
2 : u_tbrx[2].tbrx_cpl(byte_cnt, lower_addr,status,length, Error_Type);
`endif
`ifdef EN_VC3
3 : u_tbrx[3].tbrx_cpl(byte_cnt, lower_addr,status,length, Error_Type);
`endif
`ifdef EN_VC4
4 : u_tbrx[4].tbrx_cpl(byte_cnt, lower_addr,status,length, Error_Type);
`endif
`ifdef EN_VC5
5 : u_tbrx[5].tbrx_cpl(byte_cnt, lower_addr,status,length, Error_Type);
`endif
`ifdef EN_VC6
6 : u_tbrx[6].tbrx_cpl(byte_cnt, lower_addr,status,length, Error_Type);
`endif
`ifdef EN_VC7
7 : u_tbrx[7].tbrx_cpl(byte_cnt, lower_addr,status,length, Error_Type);
`endif
endcase
end
endtask
// =============================================================================
task tbrx_cpl_d;
input [2:0] vcid;
input [11:0] byte_cnt;
input [6:0] lower_addr;
input [2:0] status;
input [9:0] length;
input [3:0] Error_Type;
begin
case(vcid)
`ifdef EN_VC0
0 : u_tbrx[0].tbrx_cpl_d(byte_cnt, lower_addr,status, length,Error_Type);
`endif
`ifdef EN_VC1
1 : u_tbrx[1].tbrx_cpl_d(byte_cnt, lower_addr,status, length,Error_Type);
`endif
`ifdef EN_VC2
2 : u_tbrx[2].tbrx_cpl_d(byte_cnt, lower_addr,status, length,Error_Type);
`endif
`ifdef EN_VC3
3 : u_tbrx[3].tbrx_cpl_d(byte_cnt, lower_addr,status, length,Error_Type);
`endif
`ifdef EN_VC4
4 : u_tbrx[4].tbrx_cpl_d(byte_cnt, lower_addr,status, length,Error_Type);
`endif
`ifdef EN_VC5
5 : u_tbrx[5].tbrx_cpl_d(byte_cnt, lower_addr,status, length,Error_Type);
`endif
`ifdef EN_VC6
6 : u_tbrx[6].tbrx_cpl_d(byte_cnt, lower_addr,status, length,Error_Type);
`endif
`ifdef EN_VC7
7 : u_tbrx[7].tbrx_cpl_d(byte_cnt, lower_addr,status, length,Error_Type);
`endif
endcase
end
endtask
// =============================================================================
// TASKS WITH TC INPUT
// =============================================================================
task tbrx_mem_rd_tc;
input [2:0] vcid;
input [2:0] tc;
input [31:0] addr;
input [9:0] length;
input hdr_type; //3 DW or 4 DW
input [3:0] Error_Type;
begin
case(vcid)
`ifdef EN_VC0
0 : u_tbrx[0].tbrx_mem_rd_tc(tc, addr,length,hdr_type,Error_Type);
`endif
`ifdef EN_VC1
1 : u_tbrx[1].tbrx_mem_rd_tc(tc, addr,length,hdr_type,Error_Type);
`endif
`ifdef EN_VC2
2 : u_tbrx[2].tbrx_mem_rd_tc(tc, addr,length,hdr_type,Error_Type);
`endif
`ifdef EN_VC3
3 : u_tbrx[3].tbrx_mem_rd_tc(tc, addr,length,hdr_type,Error_Type);
`endif
`ifdef EN_VC4
4 : u_tbrx[4].tbrx_mem_rd_tc(tc, addr,length,hdr_type,Error_Type);
`endif
`ifdef EN_VC5
5 : u_tbrx[5].tbrx_mem_rd_tc(tc, addr,length,hdr_type,Error_Type);
`endif
`ifdef EN_VC6
6 : u_tbrx[6].tbrx_mem_rd_tc(tc, addr,length,hdr_type,Error_Type);
`endif
`ifdef EN_VC7
7 : u_tbrx[7].tbrx_mem_rd_tc(tc, addr,length,hdr_type,Error_Type);
`endif
endcase
end
endtask
// =============================================================================
task tbrx_mem_wr_tc;
input [2:0] vcid;
input [2:0] tc;
input [31:0] addr;
input [9:0] length;
input hdr_type; //3 DW or 4 DW
input [3:0] Error_Type;
begin
case(vcid)
`ifdef EN_VC0
0 : u_tbrx[0].tbrx_mem_wr_tc(tc, addr,length,hdr_type,Error_Type);
`endif
`ifdef EN_VC1
1 : u_tbrx[1].tbrx_mem_wr_tc(tc, addr,length,hdr_type,Error_Type);
`endif
`ifdef EN_VC2
2 : u_tbrx[2].tbrx_mem_wr_tc(tc, addr,length,hdr_type,Error_Type);
`endif
`ifdef EN_VC3
3 : u_tbrx[3].tbrx_mem_wr_tc(tc, addr,length,hdr_type,Error_Type);
`endif
`ifdef EN_VC4
4 : u_tbrx[4].tbrx_mem_wr_tc(tc, addr,length,hdr_type,Error_Type);
`endif
`ifdef EN_VC5
5 : u_tbrx[5].tbrx_mem_wr_tc(tc, addr,length,hdr_type,Error_Type);
`endif
`ifdef EN_VC6
6 : u_tbrx[6].tbrx_mem_wr_tc(tc, addr,length,hdr_type,Error_Type);
`endif
`ifdef EN_VC7
7 : u_tbrx[7].tbrx_mem_wr_tc(tc, addr,length,hdr_type,Error_Type);
`endif
endcase
end
endtask
// =============================================================================
// FLOW CONTROL TASKS
// =============================================================================
// Setting INIT values
// =============================================================================
task FC_INIT;
input [2:0] vcid;
input [1:0] type; // p/np/cpl
input [7:0] hdr;
input [11:0] data;
begin
case(vcid)
`ifdef EN_VC0
0 : u_tbrx[0].FC_INIT(type, hdr, data);
`endif
`ifdef EN_VC1
1 : u_tbrx[1].FC_INIT(type, hdr, data);
`endif
`ifdef EN_VC2
2 : u_tbrx[2].FC_INIT(type, hdr, data);
`endif
`ifdef EN_VC3
3 : u_tbrx[3].FC_INIT(type, hdr, data);
`endif
`ifdef EN_VC4
4 : u_tbrx[4].FC_INIT(type, hdr, data);
`endif
`ifdef EN_VC5
5 : u_tbrx[5].FC_INIT(type, hdr, data);
`endif
`ifdef EN_VC6
6 : u_tbrx[6].FC_INIT(type, hdr, data);
`endif
`ifdef EN_VC7
7 : u_tbrx[7].FC_INIT(type, hdr, data);
`endif
endcase
end
endtask
// =============================================================================
// Asserion/Deassertion of buf_status signals
// =============================================================================
task FC_BUF_STATUS;
input [2:0] vcid;
input [2:0] type; // ph/pd/nph/npd/cpl/cpld
input set; // Set=1: Assert the signal , Set=0, De-assert the signal
begin
case(vcid)
`ifdef EN_VC0
0 : u_tbrx[0].FC_BUF_STATUS(type, set);
`endif
`ifdef EN_VC1
1 : u_tbrx[1].FC_BUF_STATUS(type, set);
`endif
`ifdef EN_VC2
2 : u_tbrx[2].FC_BUF_STATUS(type, set);
`endif
`ifdef EN_VC3
3 : u_tbrx[3].FC_BUF_STATUS(type, set);
`endif
`ifdef EN_VC4
4 : u_tbrx[4].FC_BUF_STATUS(type, set);
`endif
`ifdef EN_VC5
5 : u_tbrx[5].FC_BUF_STATUS(type, set);
`endif
`ifdef EN_VC6
6 : u_tbrx[6].FC_BUF_STATUS(type, set);
`endif
`ifdef EN_VC7
7 : u_tbrx[7].FC_BUF_STATUS(type, set);
`endif
endcase
end
endtask
// =============================================================================
// Asserion/Deassertion of Processed signals
// Onle pulse
// =============================================================================
task FC_PROCESSED;
input [2:0] vcid;
input [2:0] type; // ph/pd/nph/npd/cpl/cpld
input set; // Set=1: Assert the signal , Set=0, De-assert the signal
begin
case(vcid)
`ifdef EN_VC0
0 : u_tbrx[0].FC_PROCESSED(type);
`endif
`ifdef EN_VC1
1 : u_tbrx[1].FC_PROCESSED(type);
`endif
`ifdef EN_VC2
2 : u_tbrx[2].FC_PROCESSED(type);
`endif
`ifdef EN_VC3
3 : u_tbrx[3].FC_PROCESSED(type);
`endif
`ifdef EN_VC4
4 : u_tbrx[4].FC_PROCESSED(type);
`endif
`ifdef EN_VC5
5 : u_tbrx[5].FC_PROCESSED(type);
`endif
`ifdef EN_VC6
6 : u_tbrx[6].FC_PROCESSED(type);
`endif
`ifdef EN_VC7
7 : u_tbrx[7].FC_PROCESSED(type);
`endif
endcase
end
endtask
endmodule
|
module sky130_fd_sc_hd__clkinv (
Y,
A
);
// Module ports
output Y;
input A;
// Local signals
wire not0_out_Y;
// Name Output Other arguments
not not0 (not0_out_Y, A );
buf buf0 (Y , not0_out_Y );
endmodule
|
module arriaiigz_dffe ( Q, CLK, ENA, D, CLRN, PRN );
input D;
input CLK;
input CLRN;
input PRN;
input ENA;
output Q;
wire D_ipd;
wire ENA_ipd;
wire CLK_ipd;
wire PRN_ipd;
wire CLRN_ipd;
buf (D_ipd, D);
buf (ENA_ipd, ENA);
buf (CLK_ipd, CLK);
buf (PRN_ipd, PRN);
buf (CLRN_ipd, CLRN);
wire legal;
reg viol_notifier;
ARRIAIIGZ_PRIM_DFFE ( Q, ENA_ipd, D_ipd, CLK_ipd, CLRN_ipd, PRN_ipd, viol_notifier );
and(legal, ENA_ipd, CLRN_ipd, PRN_ipd);
specify
specparam TREG = 0;
specparam TREN = 0;
specparam TRSU = 0;
specparam TRH = 0;
specparam TRPR = 0;
specparam TRCL = 0;
$setup ( D, posedge CLK &&& legal, TRSU, viol_notifier ) ;
$hold ( posedge CLK &&& legal, D, TRH, viol_notifier ) ;
$setup ( ENA, posedge CLK &&& legal, TREN, viol_notifier ) ;
$hold ( posedge CLK &&& legal, ENA, 0, viol_notifier ) ;
( negedge CLRN => (Q +: 1'b0)) = ( TRCL, TRCL) ;
( negedge PRN => (Q +: 1'b1)) = ( TRPR, TRPR) ;
( posedge CLK => (Q +: D)) = ( TREG, TREG) ;
endspecify
endmodule
|
module arriaiigz_mux21 (MO, A, B, S);
input A, B, S;
output MO;
wire A_in;
wire B_in;
wire S_in;
buf(A_in, A);
buf(B_in, B);
buf(S_in, S);
wire tmp_MO;
specify
(A => MO) = (0, 0);
(B => MO) = (0, 0);
(S => MO) = (0, 0);
endspecify
assign tmp_MO = (S_in == 1) ? B_in : A_in;
buf (MO, tmp_MO);
endmodule
|
module arriaiigz_mux41 (MO, IN0, IN1, IN2, IN3, S);
input IN0;
input IN1;
input IN2;
input IN3;
input [1:0] S;
output MO;
wire IN0_in;
wire IN1_in;
wire IN2_in;
wire IN3_in;
wire S1_in;
wire S0_in;
buf(IN0_in, IN0);
buf(IN1_in, IN1);
buf(IN2_in, IN2);
buf(IN3_in, IN3);
buf(S1_in, S[1]);
buf(S0_in, S[0]);
wire tmp_MO;
specify
(IN0 => MO) = (0, 0);
(IN1 => MO) = (0, 0);
(IN2 => MO) = (0, 0);
(IN3 => MO) = (0, 0);
(S[1] => MO) = (0, 0);
(S[0] => MO) = (0, 0);
endspecify
assign tmp_MO = S1_in ? (S0_in ? IN3_in : IN2_in) : (S0_in ? IN1_in : IN0_in);
buf (MO, tmp_MO);
endmodule
|
module arriaiigz_and1 (Y, IN1);
input IN1;
output Y;
specify
(IN1 => Y) = (0, 0);
endspecify
buf (Y, IN1);
endmodule
|
module arriaiigz_and16 (Y, IN1);
input [15:0] IN1;
output [15:0] Y;
specify
(IN1 => Y) = (0, 0);
endspecify
buf (Y[0], IN1[0]);
buf (Y[1], IN1[1]);
buf (Y[2], IN1[2]);
buf (Y[3], IN1[3]);
buf (Y[4], IN1[4]);
buf (Y[5], IN1[5]);
buf (Y[6], IN1[6]);
buf (Y[7], IN1[7]);
buf (Y[8], IN1[8]);
buf (Y[9], IN1[9]);
buf (Y[10], IN1[10]);
buf (Y[11], IN1[11]);
buf (Y[12], IN1[12]);
buf (Y[13], IN1[13]);
buf (Y[14], IN1[14]);
buf (Y[15], IN1[15]);
endmodule
|
module arriaiigz_bmux21 (MO, A, B, S);
input [15:0] A, B;
input S;
output [15:0] MO;
assign MO = (S == 1) ? B : A;
endmodule
|
module arriaiigz_b17mux21 (MO, A, B, S);
input [16:0] A, B;
input S;
output [16:0] MO;
assign MO = (S == 1) ? B : A;
endmodule
|
module arriaiigz_nmux21 (MO, A, B, S);
input A, B, S;
output MO;
assign MO = (S == 1) ? ~B : ~A;
endmodule
|
module arriaiigz_b5mux21 (MO, A, B, S);
input [4:0] A, B;
input S;
output [4:0] MO;
assign MO = (S == 1) ? B : A;
endmodule
|
module arriaiigz_jtag (
tms,
tck,
tdi,
ntrst,
tdoutap,
tdouser,
tdo,
tmsutap,
tckutap,
tdiutap,
shiftuser,
clkdruser,
updateuser,
runidleuser,
usr1user);
input tms;
input tck;
input tdi;
input ntrst;
input tdoutap;
input tdouser;
output tdo;
output tmsutap;
output tckutap;
output tdiutap;
output shiftuser;
output clkdruser;
output updateuser;
output runidleuser;
output usr1user;
parameter lpm_type = "arriaiigz_jtag";
endmodule
|
module arriaiigz_crcblock (
clk,
shiftnld,
crcerror,
regout);
input clk;
input shiftnld;
output crcerror;
output regout;
assign crcerror = 1'b0;
assign regout = 1'b0;
parameter oscillator_divider = 1;
parameter lpm_type = "arriaiigz_crcblock";
parameter crc_deld_disable = "off";
parameter error_delay = 0 ;
parameter error_dra_dl_bypass = "off";
endmodule
|
module arriaiigz_lcell_comb (
dataa,
datab,
datac,
datad,
datae,
dataf,
datag,
cin,
sharein,
combout,
sumout,
cout,
shareout
);
input dataa;
input datab;
input datac;
input datad;
input datae;
input dataf;
input datag;
input cin;
input sharein;
output combout;
output sumout;
output cout;
output shareout;
parameter lut_mask = 64'hFFFFFFFFFFFFFFFF;
parameter shared_arith = "off";
parameter extended_lut = "off";
parameter dont_touch = "off";
parameter lpm_type = "arriaiigz_lcell_comb";
// sub masks
wire [15:0] f0_mask;
wire [15:0] f1_mask;
wire [15:0] f2_mask;
wire [15:0] f3_mask;
// sub lut outputs
reg f0_out;
reg f1_out;
reg f2_out;
reg f3_out;
// mux output for extended mode
reg g0_out;
reg g1_out;
// either datac or datag
reg f2_input3;
// F2 output using dataf
reg f2_f;
// second input to the adder
reg adder_input2;
// tmp output variables
reg combout_tmp;
reg sumout_tmp;
reg cout_tmp;
// integer representations for string parameters
reg ishared_arith;
reg iextended_lut;
// 4-input LUT function
function lut4;
input [15:0] mask;
input dataa;
input datab;
input datac;
input datad;
begin
lut4 = datad ? ( datac ? ( datab ? ( dataa ? mask[15] : mask[14])
: ( dataa ? mask[13] : mask[12]))
: ( datab ? ( dataa ? mask[11] : mask[10])
: ( dataa ? mask[ 9] : mask[ 8])))
: ( datac ? ( datab ? ( dataa ? mask[ 7] : mask[ 6])
: ( dataa ? mask[ 5] : mask[ 4]))
: ( datab ? ( dataa ? mask[ 3] : mask[ 2])
: ( dataa ? mask[ 1] : mask[ 0])));
end
endfunction
// 5-input LUT function
function lut5;
input [31:0] mask;
input dataa;
input datab;
input datac;
input datad;
input datae;
reg e0_lut;
reg e1_lut;
reg [15:0] e0_mask;
reg [31:16] e1_mask;
begin
e0_mask = mask[15:0];
e1_mask = mask[31:16];
begin
e0_lut = lut4(e0_mask, dataa, datab, datac, datad);
e1_lut = lut4(e1_mask, dataa, datab, datac, datad);
if (datae === 1'bX) // X propogation
begin
if (e0_lut == e1_lut)
begin
lut5 = e0_lut;
end
else
begin
lut5 = 1'bX;
end
end
else
begin
lut5 = (datae == 1'b1) ? e1_lut : e0_lut;
end
end
end
endfunction
// 6-input LUT function
function lut6;
input [63:0] mask;
input dataa;
input datab;
input datac;
input datad;
input datae;
input dataf;
reg f0_lut;
reg f1_lut;
reg [31:0] f0_mask;
reg [63:32] f1_mask ;
begin
f0_mask = mask[31:0];
f1_mask = mask[63:32];
begin
lut6 = mask[{dataf, datae, datad, datac, datab, dataa}];
if (lut6 === 1'bX)
begin
f0_lut = lut5(f0_mask, dataa, datab, datac, datad, datae);
f1_lut = lut5(f1_mask, dataa, datab, datac, datad, datae);
if (dataf === 1'bX) // X propogation
begin
if (f0_lut == f1_lut)
begin
lut6 = f0_lut;
end
else
begin
lut6 = 1'bX;
end
end
else
begin
lut6 = (dataf == 1'b1) ? f1_lut : f0_lut;
end
end
end
end
endfunction
wire dataa_in;
wire datab_in;
wire datac_in;
wire datad_in;
wire datae_in;
wire dataf_in;
wire datag_in;
wire cin_in;
wire sharein_in;
buf(dataa_in, dataa);
buf(datab_in, datab);
buf(datac_in, datac);
buf(datad_in, datad);
buf(datae_in, datae);
buf(dataf_in, dataf);
buf(datag_in, datag);
buf(cin_in, cin);
buf(sharein_in, sharein);
specify
(dataa => combout) = (0, 0);
(datab => combout) = (0, 0);
(datac => combout) = (0, 0);
(datad => combout) = (0, 0);
(datae => combout) = (0, 0);
(dataf => combout) = (0, 0);
(datag => combout) = (0, 0);
(dataa => sumout) = (0, 0);
(datab => sumout) = (0, 0);
(datac => sumout) = (0, 0);
(datad => sumout) = (0, 0);
(dataf => sumout) = (0, 0);
(cin => sumout) = (0, 0);
(sharein => sumout) = (0, 0);
(dataa => cout) = (0, 0);
(datab => cout) = (0, 0);
(datac => cout) = (0, 0);
(datad => cout) = (0, 0);
(dataf => cout) = (0, 0);
(cin => cout) = (0, 0);
(sharein => cout) = (0, 0);
(dataa => shareout) = (0, 0);
(datab => shareout) = (0, 0);
(datac => shareout) = (0, 0);
(datad => shareout) = (0, 0);
endspecify
initial
begin
if (shared_arith == "on")
ishared_arith = 1;
else
ishared_arith = 0;
if (extended_lut == "on")
iextended_lut = 1;
else
iextended_lut = 0;
f0_out = 1'b0;
f1_out = 1'b0;
f2_out = 1'b0;
f3_out = 1'b0;
g0_out = 1'b0;
g1_out = 1'b0;
f2_input3 = 1'b0;
adder_input2 = 1'b0;
f2_f = 1'b0;
combout_tmp = 1'b0;
sumout_tmp = 1'b0;
cout_tmp = 1'b0;
end
// sub masks and outputs
assign f0_mask = lut_mask[15:0];
assign f1_mask = lut_mask[31:16];
assign f2_mask = lut_mask[47:32];
assign f3_mask = lut_mask[63:48];
always @(datag_in or dataf_in or datae_in or datad_in or datac_in or
datab_in or dataa_in or cin_in or sharein_in)
begin
// check for extended LUT mode
if (iextended_lut == 1)
f2_input3 = datag_in;
else
f2_input3 = datac_in;
f0_out = lut4(f0_mask, dataa_in, datab_in, datac_in, datad_in);
f1_out = lut4(f1_mask, dataa_in, datab_in, f2_input3, datad_in);
f2_out = lut4(f2_mask, dataa_in, datab_in, datac_in, datad_in);
f3_out = lut4(f3_mask, dataa_in, datab_in, f2_input3, datad_in);
// combout is the 6-input LUT
if (iextended_lut == 1)
begin
if (datae_in == 1'b0)
begin
g0_out = f0_out;
g1_out = f2_out;
end
else if (datae_in == 1'b1)
begin
g0_out = f1_out;
g1_out = f3_out;
end
else
begin
if (f0_out == f1_out)
g0_out = f0_out;
else
g0_out = 1'bX;
if (f2_out == f3_out)
g1_out = f2_out;
else
g1_out = 1'bX;
end
if (dataf_in == 1'b0)
combout_tmp = g0_out;
else if ((dataf_in == 1'b1) || (g0_out == g1_out))
combout_tmp = g1_out;
else
combout_tmp = 1'bX;
end
else
combout_tmp = lut6(lut_mask, dataa_in, datab_in, datac_in,
datad_in, datae_in, dataf_in);
// check for shareed arithmetic mode
if (ishared_arith == 1)
adder_input2 = sharein_in;
else
begin
f2_f = lut4(f2_mask, dataa_in, datab_in, datac_in, dataf_in);
adder_input2 = !f2_f;
end
// sumout & cout
sumout_tmp = cin_in ^ f0_out ^ adder_input2;
cout_tmp = (cin_in & f0_out) | (cin_in & adder_input2) |
(f0_out & adder_input2);
end
and (combout, combout_tmp, 1'b1);
and (sumout, sumout_tmp, 1'b1);
and (cout, cout_tmp, 1'b1);
and (shareout, f2_out, 1'b1);
endmodule
|
module arriaiigz_routing_wire (
datain,
dataout
);
// INPUT PORTS
input datain;
// OUTPUT PORTS
output dataout;
// INTERNAL VARIABLES
wire dataout_tmp;
specify
(datain => dataout) = (0, 0) ;
endspecify
assign dataout_tmp = datain;
and (dataout, dataout_tmp, 1'b1);
endmodule
|
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