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module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(clka, addra, douta)
/* synthesis syn_black_box black_box_pad_pin="clka,addra[9:0],douta[31:0]" */;
input clka;
input [9:0]addra;
output [31:0]douta;
endmodule
|
module kernel_clock_0_edge_to_pulse (
// inputs:
clock,
data_in,
reset_n,
// outputs:
data_out
)
;
output data_out;
input clock;
input data_in;
input reset_n;
reg data_in_d1;
wire data_out;
always @(posedge clock or negedge reset_n)
begin
if (reset_n == 0)
data_in_d1 <= 0;
else
data_in_d1 <= data_in;
end
assign data_out = data_in ^ data_in_d1;
endmodule
|
module kernel_clock_0_slave_FSM (
// inputs:
master_read_done_token,
master_write_done_token,
slave_clk,
slave_read,
slave_reset_n,
slave_write,
// outputs:
slave_read_request,
slave_waitrequest,
slave_write_request
)
;
output slave_read_request;
output slave_waitrequest;
output slave_write_request;
input master_read_done_token;
input master_write_done_token;
input slave_clk;
input slave_read;
input slave_reset_n;
input slave_write;
reg next_slave_read_request;
reg [ 2: 0] next_slave_state;
reg next_slave_write_request;
reg slave_read_request;
reg [ 2: 0] slave_state;
reg slave_waitrequest;
reg slave_write_request;
always @(posedge slave_clk or negedge slave_reset_n)
begin
if (slave_reset_n == 0)
slave_read_request <= 0;
else if (1)
slave_read_request <= next_slave_read_request;
end
always @(posedge slave_clk or negedge slave_reset_n)
begin
if (slave_reset_n == 0)
slave_write_request <= 0;
else if (1)
slave_write_request <= next_slave_write_request;
end
always @(posedge slave_clk or negedge slave_reset_n)
begin
if (slave_reset_n == 0)
slave_state <= 3'b001;
else if (1)
slave_state <= next_slave_state;
end
always @(master_read_done_token or master_write_done_token or slave_read or slave_read_request or slave_state or slave_write or slave_write_request)
begin
case (slave_state) // synthesis parallel_case
3'b001: begin
//read request: go from IDLE state to READ_WAIT state
if (slave_read)
begin
next_slave_state = 3'b010;
slave_waitrequest = 1;
next_slave_read_request = !slave_read_request;
next_slave_write_request = slave_write_request;
end
else if (slave_write)
begin
next_slave_state = 3'b100;
slave_waitrequest = 1;
next_slave_read_request = slave_read_request;
next_slave_write_request = !slave_write_request;
end
else
begin
next_slave_state = slave_state;
slave_waitrequest = 0;
next_slave_read_request = slave_read_request;
next_slave_write_request = slave_write_request;
end
end // 3'b001
3'b010: begin
//stay in READ_WAIT state until master passes read done token
if (master_read_done_token)
begin
next_slave_state = 3'b001;
slave_waitrequest = 0;
end
else
begin
next_slave_state = 3'b010;
slave_waitrequest = 1;
end
next_slave_read_request = slave_read_request;
next_slave_write_request = slave_write_request;
end // 3'b010
3'b100: begin
//stay in WRITE_WAIT state until master passes write done token
if (master_write_done_token)
begin
next_slave_state = 3'b001;
slave_waitrequest = 0;
end
else
begin
next_slave_state = 3'b100;
slave_waitrequest = 1;
end
next_slave_read_request = slave_read_request;
next_slave_write_request = slave_write_request;
end // 3'b100
default: begin
next_slave_state = 3'b001;
slave_waitrequest = 0;
next_slave_read_request = slave_read_request;
next_slave_write_request = slave_write_request;
end // default
endcase // slave_state
end
endmodule
|
module kernel_clock_0_master_FSM (
// inputs:
master_clk,
master_reset_n,
master_waitrequest,
slave_read_request_token,
slave_write_request_token,
// outputs:
master_read,
master_read_done,
master_write,
master_write_done
)
;
output master_read;
output master_read_done;
output master_write;
output master_write_done;
input master_clk;
input master_reset_n;
input master_waitrequest;
input slave_read_request_token;
input slave_write_request_token;
reg master_read;
reg master_read_done;
reg [ 2: 0] master_state;
reg master_write;
reg master_write_done;
reg next_master_read;
reg next_master_read_done;
reg [ 2: 0] next_master_state;
reg next_master_write;
reg next_master_write_done;
always @(posedge master_clk or negedge master_reset_n)
begin
if (master_reset_n == 0)
master_read_done <= 0;
else if (1)
master_read_done <= next_master_read_done;
end
always @(posedge master_clk or negedge master_reset_n)
begin
if (master_reset_n == 0)
master_write_done <= 0;
else if (1)
master_write_done <= next_master_write_done;
end
always @(posedge master_clk or negedge master_reset_n)
begin
if (master_reset_n == 0)
master_read <= 0;
else if (1)
master_read <= next_master_read;
end
always @(posedge master_clk or negedge master_reset_n)
begin
if (master_reset_n == 0)
master_write <= 0;
else if (1)
master_write <= next_master_write;
end
always @(posedge master_clk or negedge master_reset_n)
begin
if (master_reset_n == 0)
master_state <= 3'b001;
else if (1)
master_state <= next_master_state;
end
always @(master_read or master_read_done or master_state or master_waitrequest or master_write or master_write_done or slave_read_request_token or slave_write_request_token)
begin
case (master_state) // synthesis parallel_case
3'b001: begin
//if read request token from slave then goto READ_WAIT state
if (slave_read_request_token)
begin
next_master_state = 3'b010;
next_master_read = 1;
next_master_write = 0;
end
else if (slave_write_request_token)
begin
next_master_state = 3'b100;
next_master_read = 0;
next_master_write = 1;
end
else
begin
next_master_state = master_state;
next_master_read = 0;
next_master_write = 0;
end
next_master_read_done = master_read_done;
next_master_write_done = master_write_done;
end // 3'b001
3'b010: begin
//stay in READ_WAIT state until master wait is deasserted
if (!master_waitrequest)
begin
next_master_state = 3'b001;
next_master_read_done = !master_read_done;
next_master_read = 0;
end
else
begin
next_master_state = 3'b010;
next_master_read_done = master_read_done;
next_master_read = master_read;
end
next_master_write_done = master_write_done;
next_master_write = 0;
end // 3'b010
3'b100: begin
//stay in WRITE_WAIT state until slave wait is deasserted
if (!master_waitrequest)
begin
next_master_state = 3'b001;
next_master_write = 0;
next_master_write_done = !master_write_done;
end
else
begin
next_master_state = 3'b100;
next_master_write = master_write;
next_master_write_done = master_write_done;
end
next_master_read_done = master_read_done;
next_master_read = 0;
end // 3'b100
default: begin
next_master_state = 3'b001;
next_master_write = 0;
next_master_write_done = master_write_done;
next_master_read = 0;
next_master_read_done = master_read_done;
end // default
endcase // master_state
end
endmodule
|
module kernel_clock_0_bit_pipe (
// inputs:
clk1,
clk2,
data_in,
reset_clk1_n,
reset_clk2_n,
// outputs:
data_out
)
;
output data_out;
input clk1;
input clk2;
input data_in;
input reset_clk1_n;
input reset_clk2_n;
reg data_in_d1 /* synthesis ALTERA_ATTRIBUTE = "{-to \"*\"} CUT=ON ; PRESERVE_REGISTER=ON" */;
reg data_out /* synthesis ALTERA_ATTRIBUTE = "PRESERVE_REGISTER=ON" */;
always @(posedge clk1 or negedge reset_clk1_n)
begin
if (reset_clk1_n == 0)
data_in_d1 <= 0;
else
data_in_d1 <= data_in;
end
always @(posedge clk2 or negedge reset_clk2_n)
begin
if (reset_clk2_n == 0)
data_out <= 0;
else
data_out <= data_in_d1;
end
endmodule
|
module kernel_clock_0 (
// inputs:
master_clk,
master_endofpacket,
master_readdata,
master_reset_n,
master_waitrequest,
slave_address,
slave_byteenable,
slave_clk,
slave_nativeaddress,
slave_read,
slave_reset_n,
slave_write,
slave_writedata,
// outputs:
master_address,
master_byteenable,
master_nativeaddress,
master_read,
master_write,
master_writedata,
slave_endofpacket,
slave_readdata,
slave_waitrequest
)
;
output [ 19: 0] master_address;
output [ 1: 0] master_byteenable;
output [ 18: 0] master_nativeaddress;
output master_read;
output master_write;
output [ 15: 0] master_writedata;
output slave_endofpacket;
output [ 15: 0] slave_readdata;
output slave_waitrequest;
input master_clk;
input master_endofpacket;
input [ 15: 0] master_readdata;
input master_reset_n;
input master_waitrequest;
input [ 19: 0] slave_address;
input [ 1: 0] slave_byteenable;
input slave_clk;
input [ 18: 0] slave_nativeaddress;
input slave_read;
input slave_reset_n;
input slave_write;
input [ 15: 0] slave_writedata;
reg [ 19: 0] master_address /* synthesis ALTERA_ATTRIBUTE = "PRESERVE_REGISTER=ON" */;
reg [ 1: 0] master_byteenable /* synthesis ALTERA_ATTRIBUTE = "PRESERVE_REGISTER=ON" */;
reg [ 18: 0] master_nativeaddress /* synthesis ALTERA_ATTRIBUTE = "PRESERVE_REGISTER=ON" */;
wire master_read;
wire master_read_done;
wire master_read_done_sync;
wire master_read_done_token;
wire master_write;
wire master_write_done;
wire master_write_done_sync;
wire master_write_done_token;
reg [ 15: 0] master_writedata /* synthesis ALTERA_ATTRIBUTE = "PRESERVE_REGISTER=ON" */;
reg [ 19: 0] slave_address_d1 /* synthesis ALTERA_ATTRIBUTE = "{-to \"*\"} CUT=ON ; PRESERVE_REGISTER=ON" */;
reg [ 1: 0] slave_byteenable_d1 /* synthesis ALTERA_ATTRIBUTE = "{-to \"*\"} CUT=ON ; PRESERVE_REGISTER=ON" */;
wire slave_endofpacket;
reg [ 18: 0] slave_nativeaddress_d1 /* synthesis ALTERA_ATTRIBUTE = "{-to \"*\"} CUT=ON ; PRESERVE_REGISTER=ON" */;
wire slave_read_request;
wire slave_read_request_sync;
wire slave_read_request_token;
reg [ 15: 0] slave_readdata /* synthesis ALTERA_ATTRIBUTE = "{-from \"*\"} CUT=ON" */;
reg [ 15: 0] slave_readdata_p1;
wire slave_waitrequest;
wire slave_write_request;
wire slave_write_request_sync;
wire slave_write_request_token;
reg [ 15: 0] slave_writedata_d1 /* synthesis ALTERA_ATTRIBUTE = "{-to \"*\"} CUT=ON ; PRESERVE_REGISTER=ON" */;
//in, which is an e_avalon_slave
//out, which is an e_avalon_master
altera_std_synchronizer the_altera_std_synchronizer
(
.clk (slave_clk),
.din (master_read_done),
.dout (master_read_done_sync),
.reset_n (slave_reset_n)
);
defparam the_altera_std_synchronizer.depth = 2;
altera_std_synchronizer the_altera_std_synchronizer1
(
.clk (slave_clk),
.din (master_write_done),
.dout (master_write_done_sync),
.reset_n (slave_reset_n)
);
defparam the_altera_std_synchronizer1.depth = 2;
//read_done_edge_to_pulse, which is an e_instance
kernel_clock_0_edge_to_pulse read_done_edge_to_pulse
(
.clock (slave_clk),
.data_in (master_read_done_sync),
.data_out (master_read_done_token),
.reset_n (slave_reset_n)
);
//write_done_edge_to_pulse, which is an e_instance
kernel_clock_0_edge_to_pulse write_done_edge_to_pulse
(
.clock (slave_clk),
.data_in (master_write_done_sync),
.data_out (master_write_done_token),
.reset_n (slave_reset_n)
);
//slave_FSM, which is an e_instance
kernel_clock_0_slave_FSM slave_FSM
(
.master_read_done_token (master_read_done_token),
.master_write_done_token (master_write_done_token),
.slave_clk (slave_clk),
.slave_read (slave_read),
.slave_read_request (slave_read_request),
.slave_reset_n (slave_reset_n),
.slave_waitrequest (slave_waitrequest),
.slave_write (slave_write),
.slave_write_request (slave_write_request)
);
altera_std_synchronizer the_altera_std_synchronizer2
(
.clk (master_clk),
.din (slave_read_request),
.dout (slave_read_request_sync),
.reset_n (master_reset_n)
);
defparam the_altera_std_synchronizer2.depth = 2;
altera_std_synchronizer the_altera_std_synchronizer3
(
.clk (master_clk),
.din (slave_write_request),
.dout (slave_write_request_sync),
.reset_n (master_reset_n)
);
defparam the_altera_std_synchronizer3.depth = 2;
//read_request_edge_to_pulse, which is an e_instance
kernel_clock_0_edge_to_pulse read_request_edge_to_pulse
(
.clock (master_clk),
.data_in (slave_read_request_sync),
.data_out (slave_read_request_token),
.reset_n (master_reset_n)
);
//write_request_edge_to_pulse, which is an e_instance
kernel_clock_0_edge_to_pulse write_request_edge_to_pulse
(
.clock (master_clk),
.data_in (slave_write_request_sync),
.data_out (slave_write_request_token),
.reset_n (master_reset_n)
);
//master_FSM, which is an e_instance
kernel_clock_0_master_FSM master_FSM
(
.master_clk (master_clk),
.master_read (master_read),
.master_read_done (master_read_done),
.master_reset_n (master_reset_n),
.master_waitrequest (master_waitrequest),
.master_write (master_write),
.master_write_done (master_write_done),
.slave_read_request_token (slave_read_request_token),
.slave_write_request_token (slave_write_request_token)
);
//endofpacket_bit_pipe, which is an e_instance
kernel_clock_0_bit_pipe endofpacket_bit_pipe
(
.clk1 (slave_clk),
.clk2 (master_clk),
.data_in (master_endofpacket),
.data_out (slave_endofpacket),
.reset_clk1_n (slave_reset_n),
.reset_clk2_n (master_reset_n)
);
always @(posedge master_clk or negedge master_reset_n)
begin
if (master_reset_n == 0)
slave_readdata_p1 <= 0;
else if (master_read & ~master_waitrequest)
slave_readdata_p1 <= master_readdata;
end
always @(posedge slave_clk or negedge slave_reset_n)
begin
if (slave_reset_n == 0)
slave_readdata <= 0;
else
slave_readdata <= slave_readdata_p1;
end
always @(posedge slave_clk or negedge slave_reset_n)
begin
if (slave_reset_n == 0)
slave_writedata_d1 <= 0;
else
slave_writedata_d1 <= slave_writedata;
end
always @(posedge master_clk or negedge master_reset_n)
begin
if (master_reset_n == 0)
master_writedata <= 0;
else
master_writedata <= slave_writedata_d1;
end
always @(posedge slave_clk or negedge slave_reset_n)
begin
if (slave_reset_n == 0)
slave_address_d1 <= 0;
else
slave_address_d1 <= slave_address;
end
always @(posedge master_clk or negedge master_reset_n)
begin
if (master_reset_n == 0)
master_address <= 0;
else
master_address <= slave_address_d1;
end
always @(posedge slave_clk or negedge slave_reset_n)
begin
if (slave_reset_n == 0)
slave_nativeaddress_d1 <= 0;
else
slave_nativeaddress_d1 <= slave_nativeaddress;
end
always @(posedge master_clk or negedge master_reset_n)
begin
if (master_reset_n == 0)
master_nativeaddress <= 0;
else
master_nativeaddress <= slave_nativeaddress_d1;
end
always @(posedge slave_clk or negedge slave_reset_n)
begin
if (slave_reset_n == 0)
slave_byteenable_d1 <= 0;
else
slave_byteenable_d1 <= slave_byteenable;
end
always @(posedge master_clk or negedge master_reset_n)
begin
if (master_reset_n == 0)
master_byteenable <= 0;
else
master_byteenable <= slave_byteenable_d1;
end
endmodule
|
module spw_babasu_AUTOSTART (
// inputs:
address,
chipselect,
clk,
reset_n,
write_n,
writedata,
// outputs:
out_port,
readdata
)
;
output out_port;
output [ 31: 0] readdata;
input [ 1: 0] address;
input chipselect;
input clk;
input reset_n;
input write_n;
input [ 31: 0] writedata;
wire clk_en;
reg data_out;
wire out_port;
wire read_mux_out;
wire [ 31: 0] readdata;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign read_mux_out = {1 {(address == 0)}} & data_out;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
data_out <= 0;
else if (chipselect && ~write_n && (address == 0))
data_out <= writedata;
end
assign readdata = {32'b0 | read_mux_out};
assign out_port = data_out;
endmodule
|
module sdram (
input clk,
input rst,
// these signals go directly to the IO pins
output sdram_clk,
output sdram_cle,
output sdram_cs,
output sdram_cas,
output sdram_ras,
output sdram_we,
output sdram_dqm,
output [1:0] sdram_ba,
output [12:0] sdram_a,
inout [7:0] sdram_dq,
// User interface
input [22:0] addr, // address to read/write
input rw, // 1 = write, 0 = read
input [31:0] data_in, // data from a read
output [31:0] data_out, // data for a write
output busy, // controller is busy when high
input in_valid, // pulse high to initiate a read/write
output out_valid // pulses high when data from read is valid
);
// Commands for the SDRAM
localparam CMD_UNSELECTED = 4'b1000;
localparam CMD_NOP = 4'b0111;
localparam CMD_ACTIVE = 4'b0011;
localparam CMD_READ = 4'b0101;
localparam CMD_WRITE = 4'b0100;
localparam CMD_TERMINATE = 4'b0110;
localparam CMD_PRECHARGE = 4'b0010;
localparam CMD_REFRESH = 4'b0001;
localparam CMD_LOAD_MODE_REG = 4'b0000;
localparam STATE_SIZE = 4;
localparam INIT = 0,
WAIT = 1,
PRECHARGE_INIT = 2,
REFRESH_INIT_1 = 3,
REFRESH_INIT_2 = 4,
LOAD_MODE_REG = 5,
IDLE = 6,
REFRESH = 7,
ACTIVATE = 8,
READ = 9,
READ_RES = 10,
WRITE = 11,
PRECHARGE = 12;
wire sdram_clk_ddr;
// This is used to drive the SDRAM clock
ODDR2 #(
.DDR_ALIGNMENT("NONE"),
.INIT(1'b0),
.SRTYPE("SYNC")
) ODDR2_inst (
.Q(sdram_clk_ddr), // 1-bit DDR output data
.C0(clk), // 1-bit clock input
.C1(~clk), // 1-bit clock input
.CE(1'b1), // 1-bit clock enable input
.D0(1'b0), // 1-bit data input (associated with C0)
.D1(1'b1), // 1-bit data input (associated with C1)
.R(1'b0), // 1-bit reset input
.S(1'b0) // 1-bit set input
);
IODELAY2 #(
.IDELAY_VALUE(0),
.IDELAY_MODE("NORMAL"),
.ODELAY_VALUE(50), // value of 100 seems to work at 100MHz
.IDELAY_TYPE("FIXED"),
.DELAY_SRC("ODATAIN"),
.DATA_RATE("SDR")
) IODELAY_inst (
.IDATAIN(1'b0),
.T(1'b0),
.ODATAIN(sdram_clk_ddr),
.CAL(1'b0),
.IOCLK0(1'b0),
.IOCLK1(1'b0),
.CLK(1'b0),
.INC(1'b0),
.CE(1'b0),
.RST(1'b0),
.BUSY(),
.DATAOUT(),
.DATAOUT2(),
.TOUT(),
.DOUT(sdram_clk)
);
// registers for SDRAM signals
reg cle_d, dqm_d;
reg [3:0] cmd_d;
reg [1:0] ba_d;
reg [12:0] a_d;
reg [7:0] dq_d;
reg [7:0] dqi_d;
// We want the output/input registers to be embedded in the
// IO buffers so we set IOB to "TRUE". This is to ensure all
// the signals are sent and received at the same time.
(* IOB = "TRUE" *)
reg cle_q, dqm_q;
(* IOB = "TRUE" *)
reg [3:0] cmd_q;
(* IOB = "TRUE" *)
reg [1:0] ba_q;
(* IOB = "TRUE" *)
reg [12:0] a_q;
(* IOB = "TRUE" *)
reg [7:0] dq_q;
(* IOB = "TRUE" *)
reg [7:0] dqi_q;
reg dq_en_d, dq_en_q;
// Output assignments
assign sdram_cle = cle_q;
assign sdram_cs = cmd_q[3];
assign sdram_ras = cmd_q[2];
assign sdram_cas = cmd_q[1];
assign sdram_we = cmd_q[0];
assign sdram_dqm = dqm_q;
assign sdram_ba = ba_q;
assign sdram_a = a_q;
assign sdram_dq = dq_en_q ? dq_q : 8'hZZ; // only drive when dq_en_q is 1
reg [STATE_SIZE-1:0] state_d, state_q = INIT;
reg [STATE_SIZE-1:0] next_state_d, next_state_q;
reg [22:0] addr_d, addr_q;
reg [31:0] data_d, data_q;
reg out_valid_d, out_valid_q;
assign data_out = data_q;
assign busy = !ready_q;
assign out_valid = out_valid_q;
reg [15:0] delay_ctr_d, delay_ctr_q;
reg [1:0] byte_ctr_d, byte_ctr_q;
reg [9:0] refresh_ctr_d, refresh_ctr_q;
reg refresh_flag_d, refresh_flag_q;
reg ready_d, ready_q;
reg saved_rw_d, saved_rw_q;
reg [22:0] saved_addr_d, saved_addr_q;
reg [31:0] saved_data_d, saved_data_q;
reg rw_op_d, rw_op_q;
reg [3:0] row_open_d, row_open_q;
reg [12:0] row_addr_d[3:0], row_addr_q[3:0];
reg [2:0] precharge_bank_d, precharge_bank_q;
integer i;
always @* begin
// Default values
dq_d = dq_q;
dqi_d = sdram_dq;
dq_en_d = 1'b0; // normally keep the bus in high-Z
cle_d = cle_q;
cmd_d = CMD_NOP; // default to NOP
dqm_d = 1'b0;
ba_d = 2'd0;
a_d = 25'd0;
state_d = state_q;
next_state_d = next_state_q;
delay_ctr_d = delay_ctr_q;
addr_d = addr_q;
data_d = data_q;
out_valid_d = 1'b0;
precharge_bank_d = precharge_bank_q;
rw_op_d = rw_op_q;
byte_ctr_d = 2'd0;
row_open_d = row_open_q;
// row_addr is a 2d array and must be coppied this way
for (i = 0; i < 4; i = i + 1)
row_addr_d[i] = row_addr_q[i];
// The data in the SDRAM must be refreshed periodically.
// This conter ensures that the data remains intact.
refresh_flag_d = refresh_flag_q;
refresh_ctr_d = refresh_ctr_q + 1'b1;
if (refresh_ctr_q > 10'd750) begin
refresh_ctr_d = 10'd0;
refresh_flag_d = 1'b1;
end
saved_rw_d = saved_rw_q;
saved_data_d = saved_data_q;
saved_addr_d = saved_addr_q;
ready_d = ready_q;
// This is a queue of 1 for read/write operations.
// When the queue is empty we aren't busy and can
// accept another request.
if (ready_q && in_valid) begin
saved_rw_d = rw;
saved_data_d = data_in;
saved_addr_d = addr;
ready_d = 1'b0;
end
case (state_q)
///// INITALIZATION /////
INIT: begin
ready_d = 1'b0;
row_open_d = 4'b0;
out_valid_d = 1'b0;
a_d = 13'b0;
ba_d = 2'b0;
cle_d = 1'b1;
state_d = WAIT;
delay_ctr_d = 16'd10100; // wait for 101us
next_state_d = PRECHARGE_INIT;
dq_en_d = 1'b0;
end
WAIT: begin
delay_ctr_d = delay_ctr_q - 1'b1;
if (delay_ctr_q == 13'd0) begin
state_d = next_state_q;
if (next_state_q == WRITE) begin
dq_en_d = 1'b1; // enable the bus early
dq_d = data_q[7:0];
end
end
end
PRECHARGE_INIT: begin
cmd_d = CMD_PRECHARGE;
a_d[10] = 1'b1; // all banks
ba_d = 2'd0;
state_d = WAIT;
next_state_d = REFRESH_INIT_1;
delay_ctr_d = 13'd0;
end
REFRESH_INIT_1: begin
cmd_d = CMD_REFRESH;
state_d = WAIT;
delay_ctr_d = 13'd7;
next_state_d = REFRESH_INIT_2;
end
REFRESH_INIT_2: begin
cmd_d = CMD_REFRESH;
state_d = WAIT;
delay_ctr_d = 13'd7;
next_state_d = LOAD_MODE_REG;
end
LOAD_MODE_REG: begin
cmd_d = CMD_LOAD_MODE_REG;
ba_d = 2'b0;
// Reserved, Burst Access, Standard Op, CAS = 2, Sequential, Burst = 4
a_d = {3'b000, 1'b0, 2'b00, 3'b010, 1'b0, 3'b010}; //010
state_d = WAIT;
delay_ctr_d = 13'd1;
next_state_d = IDLE;
refresh_flag_d = 1'b0;
refresh_ctr_d = 10'b1;
ready_d = 1'b1;
end
///// IDLE STATE /////
IDLE: begin
if (refresh_flag_q) begin // we need to do a refresh
state_d = PRECHARGE;
next_state_d = REFRESH;
precharge_bank_d = 3'b100; // all banks
refresh_flag_d = 1'b0; // clear the refresh flag
end else if (!ready_q) begin // operation waiting
ready_d = 1'b1; // clear the queue
rw_op_d = saved_rw_q; // save the values we'll need later
addr_d = saved_addr_q;
if (saved_rw_q) // Write
data_d = saved_data_q;
// if the row is open we don't have to activate it
if (row_open_q[saved_addr_q[9:8]]) begin
if (row_addr_q[saved_addr_q[9:8]] == saved_addr_q[22:10]) begin
// Row is already open
if (saved_rw_q)
state_d = WRITE;
else
state_d = READ;
end else begin
// A different row in the bank is open
state_d = PRECHARGE; // precharge open row
precharge_bank_d = {1'b0, saved_addr_q[9:8]};
next_state_d = ACTIVATE; // open current row
end
end else begin
// no rows open
state_d = ACTIVATE; // open the row
end
end
end
///// REFRESH /////
REFRESH: begin
cmd_d = CMD_REFRESH;
state_d = WAIT;
delay_ctr_d = 13'd6; // gotta wait 7 clocks (66ns)
next_state_d = IDLE;
end
///// ACTIVATE /////
ACTIVATE: begin
cmd_d = CMD_ACTIVE;
a_d = addr_q[22:10];
ba_d = addr_q[9:8];
delay_ctr_d = 13'd0;
state_d = WAIT;
if (rw_op_q)
next_state_d = WRITE;
else
next_state_d = READ;
row_open_d[addr_q[9:8]] = 1'b1; // row is now open
row_addr_d[addr_q[9:8]] = addr_q[22:10];
end
///// READ /////
READ: begin
cmd_d = CMD_READ;
a_d = {2'b0, 1'b0, addr_q[7:0], 2'b0};
ba_d = addr_q[9:8];
state_d = WAIT;
delay_ctr_d = 13'd2; // wait for the data to show up
next_state_d = READ_RES;
end
READ_RES: begin
byte_ctr_d = byte_ctr_q + 1'b1; // we need to read in 4 bytes
data_d = {dqi_q, data_q[31:8]}; // shift the data in
if (byte_ctr_q == 2'd3) begin
out_valid_d = 1'b1;
state_d = IDLE;
end
end
///// WRITE /////
WRITE: begin
byte_ctr_d = byte_ctr_q + 1'b1; // send out 4 bytes
if (byte_ctr_q == 2'd0) // first byte send write command
cmd_d = CMD_WRITE;
dq_d = data_q[7:0];
data_d = {8'h00, data_q[31:8]}; // shift the data out
dq_en_d = 1'b1; // enable out bus
a_d = {2'b0, 1'b0, addr_q[7:0], 2'b00};
ba_d = addr_q[9:8];
if (byte_ctr_q == 2'd3) begin
state_d = IDLE;
end
end
///// PRECHARGE /////
PRECHARGE: begin
cmd_d = CMD_PRECHARGE;
a_d[10] = precharge_bank_q[2]; // all banks
ba_d = precharge_bank_q[1:0];
state_d = WAIT;
delay_ctr_d = 13'd0;
if (precharge_bank_q[2]) begin
row_open_d = 4'b0000; // closed all rows
end else begin
row_open_d[precharge_bank_q[1:0]] = 1'b0; // closed one row
end
end
default: state_d = INIT;
endcase
end
always @(posedge clk) begin
if(rst) begin
cle_q <= 1'b0;
dq_en_q <= 1'b0;
state_q <= INIT;
ready_q <= 1'b0;
end else begin
cle_q <= cle_d;
dq_en_q <= dq_en_d;
state_q <= state_d;
ready_q <= ready_d;
end
saved_rw_q <= saved_rw_d;
saved_data_q <= saved_data_d;
saved_addr_q <= saved_addr_d;
cmd_q <= cmd_d;
dqm_q <= dqm_d;
ba_q <= ba_d;
a_q <= a_d;
dq_q <= dq_d;
dqi_q <= dqi_d;
next_state_q <= next_state_d;
refresh_flag_q <= refresh_flag_d;
refresh_ctr_q <= refresh_ctr_d;
data_q <= data_d;
addr_q <= addr_d;
out_valid_q <= out_valid_d;
row_open_q <= row_open_d;
for (i = 0; i < 4; i = i + 1)
row_addr_q[i] <= row_addr_d[i];
precharge_bank_q <= precharge_bank_d;
rw_op_q <= rw_op_d;
byte_ctr_q <= byte_ctr_d;
delay_ctr_q <= delay_ctr_d;
end
endmodule
|
module sky130_fd_sc_hd__bufbuf (
//# {{data|Data Signals}}
input A ,
output X ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
|
module Loop_loop_height_dEe_rom (
addr0, ce0, q0, addr1, ce1, q1, addr2, ce2, q2, clk);
parameter DWIDTH = 8;
parameter AWIDTH = 8;
parameter MEM_SIZE = 256;
input[AWIDTH-1:0] addr0;
input ce0;
output reg[DWIDTH-1:0] q0;
input[AWIDTH-1:0] addr1;
input ce1;
output reg[DWIDTH-1:0] q1;
input[AWIDTH-1:0] addr2;
input ce2;
output reg[DWIDTH-1:0] q2;
input clk;
(* ram_style = "block" *)reg [DWIDTH-1:0] ram0[0:MEM_SIZE-1];
(* ram_style = "block" *)reg [DWIDTH-1:0] ram1[0:MEM_SIZE-1];
initial begin
$readmemh("./Loop_loop_height_dEe_rom.dat", ram0);
$readmemh("./Loop_loop_height_dEe_rom.dat", ram1);
end
always @(posedge clk)
begin
if (ce0)
begin
q0 <= ram0[addr0];
end
end
always @(posedge clk)
begin
if (ce1)
begin
q1 <= ram0[addr1];
end
end
always @(posedge clk)
begin
if (ce2)
begin
q2 <= ram1[addr2];
end
end
endmodule
|
module Loop_loop_height_dEe(
reset,
clk,
address0,
ce0,
q0,
address1,
ce1,
q1,
address2,
ce2,
q2);
parameter DataWidth = 32'd8;
parameter AddressRange = 32'd256;
parameter AddressWidth = 32'd8;
input reset;
input clk;
input[AddressWidth - 1:0] address0;
input ce0;
output[DataWidth - 1:0] q0;
input[AddressWidth - 1:0] address1;
input ce1;
output[DataWidth - 1:0] q1;
input[AddressWidth - 1:0] address2;
input ce2;
output[DataWidth - 1:0] q2;
Loop_loop_height_dEe_rom Loop_loop_height_dEe_rom_U(
.clk( clk ),
.addr0( address0 ),
.ce0( ce0 ),
.q0( q0 ),
.addr1( address1 ),
.ce1( ce1 ),
.q1( q1 ),
.addr2( address2 ),
.ce2( ce2 ),
.q2( q2 ));
endmodule
|
module top();
// Inputs are registered
reg A;
reg B;
reg C;
reg D_N;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
B = 1'bX;
C = 1'bX;
D_N = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 B = 1'b0;
#60 C = 1'b0;
#80 D_N = 1'b0;
#100 VGND = 1'b0;
#120 VNB = 1'b0;
#140 VPB = 1'b0;
#160 VPWR = 1'b0;
#180 A = 1'b1;
#200 B = 1'b1;
#220 C = 1'b1;
#240 D_N = 1'b1;
#260 VGND = 1'b1;
#280 VNB = 1'b1;
#300 VPB = 1'b1;
#320 VPWR = 1'b1;
#340 A = 1'b0;
#360 B = 1'b0;
#380 C = 1'b0;
#400 D_N = 1'b0;
#420 VGND = 1'b0;
#440 VNB = 1'b0;
#460 VPB = 1'b0;
#480 VPWR = 1'b0;
#500 VPWR = 1'b1;
#520 VPB = 1'b1;
#540 VNB = 1'b1;
#560 VGND = 1'b1;
#580 D_N = 1'b1;
#600 C = 1'b1;
#620 B = 1'b1;
#640 A = 1'b1;
#660 VPWR = 1'bx;
#680 VPB = 1'bx;
#700 VNB = 1'bx;
#720 VGND = 1'bx;
#740 D_N = 1'bx;
#760 C = 1'bx;
#780 B = 1'bx;
#800 A = 1'bx;
end
sky130_fd_sc_hd__nor4b dut (.A(A), .B(B), .C(C), .D_N(D_N), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Y(Y));
endmodule
|
module neo_i0(
// OR, AND gate and sync inverter are kept in neogeo.v
input nRESET,
input nCOUNTOUT,
input [3:1] M68K_ADDR,
input M68K_ADDR_7,
output reg COUNTER1,
output reg COUNTER2,
output reg LOCKOUT1,
output reg LOCKOUT2,
input [15:0] PBUS,
input PCK2B,
output reg [15:0] G
);
always @(posedge PCK2B)
G <= {PBUS[11:0], PBUS[15:12]};
// A7=Counter/lockout data
// A1=1/2
// A2=Counter/lockout
always @(nCOUNTOUT, nRESET)
begin
if (!nRESET)
begin
COUNTER1 <= 1'b0;
COUNTER2 <= 1'b0;
LOCKOUT1 <= 1'b0;
LOCKOUT2 <= 1'b0;
end
else
begin
if (!nCOUNTOUT)
begin
// DEBUG
if ({M68K_ADDR_7, M68K_ADDR[3:1]} == 4'b0000)
$display("COIN COUNTER 1 RESET");
else if ({M68K_ADDR_7, M68K_ADDR[3:1]} == 4'b0001)
$display("COIN COUNTER 2 RESET");
else if ({M68K_ADDR_7, M68K_ADDR[3:1]} == 4'b0010)
$display("COIN LOCKOUT 1 RESET");
else if ({M68K_ADDR_7, M68K_ADDR[3:1]} == 4'b0011)
$display("COIN LOCKOUT 2 RESET");
else if ({M68K_ADDR_7, M68K_ADDR[3:1]} == 4'b1000)
$display("COIN COUNTER 1 SET");
else if ({M68K_ADDR_7, M68K_ADDR[3:1]} == 4'b1001)
$display("COIN COUNTER 2 SET");
else if ({M68K_ADDR_7, M68K_ADDR[3:1]} == 4'b1010)
$display("COIN LOCKOUT 1 SET");
else if ({M68K_ADDR_7, M68K_ADDR[3:1]} == 4'b1011)
$display("COIN LOCKOUT 2 SET");
if (M68K_ADDR[3:1] == 3'b000) COUNTER1 <= M68K_ADDR_7;
if (M68K_ADDR[3:1] == 3'b001) COUNTER2 <= M68K_ADDR_7;
if (M68K_ADDR[3:1] == 3'b010) LOCKOUT1 <= M68K_ADDR_7;
if (M68K_ADDR[3:1] == 3'b011) LOCKOUT2 <= M68K_ADDR_7;
end
end
end
endmodule
|
module alt_mem_ddrx_controller #
( parameter
// Local interface parameters
CFG_LOCAL_SIZE_WIDTH = 3,
CFG_LOCAL_ADDR_WIDTH = 32,
CFG_LOCAL_DATA_WIDTH = 80, // Maximum DQ width of 40
CFG_LOCAL_ID_WIDTH = 8,
CFG_LOCAL_IF_TYPE = "AVALON",
// Memory interface parameters
CFG_MEM_IF_CHIP = 2,
CFG_MEM_IF_CS_WIDTH = 1,
CFG_MEM_IF_BA_WIDTH = 3,
CFG_MEM_IF_ROW_WIDTH = 15,
CFG_MEM_IF_COL_WIDTH = 12,
CFG_MEM_IF_ADDR_WIDTH = 15,
CFG_MEM_IF_CKE_WIDTH = 2,
CFG_MEM_IF_ODT_WIDTH = 2,
CFG_MEM_IF_CLK_PAIR_COUNT = 2,
CFG_MEM_IF_DQ_WIDTH = 40,
CFG_MEM_IF_DQS_WIDTH = 5,
CFG_MEM_IF_DM_WIDTH = 5,
// Controller parameters
CFG_DWIDTH_RATIO = 2,
CFG_ODT_ENABLED = 1, // NOTICE: required?
CFG_OUTPUT_REGD = 0, // NOTICE: un-used and will be removed
CFG_CTL_TBP_NUM = 4,
CFG_LPDDR2_ENABLED = 0,
CFG_DATA_REORDERING_TYPE = "INTER_BANK",
CFG_ECC_MULTIPLES_16_24_40_72 = 1,
// Data path buffer & fifo parameters
CFG_WRBUFFER_ADDR_WIDTH = 6,
CFG_RDBUFFER_ADDR_WIDTH = 10,
CFG_MAX_PENDING_RD_CMD = 16,
CFG_MAX_PENDING_WR_CMD = 8,
// MMR port width
// cfg: general
CFG_PORT_WIDTH_TYPE = 3,
CFG_PORT_WIDTH_INTERFACE_WIDTH = 8,
CFG_PORT_WIDTH_BURST_LENGTH = 5,
CFG_PORT_WIDTH_DEVICE_WIDTH = 4,
CFG_PORT_WIDTH_OUTPUT_REGD = 2,
// cfg: address mapping signals
CFG_PORT_WIDTH_ADDR_ORDER = 2,
CFG_PORT_WIDTH_COL_ADDR_WIDTH = 5,
CFG_PORT_WIDTH_ROW_ADDR_WIDTH = 5,
CFG_PORT_WIDTH_BANK_ADDR_WIDTH = 3,
CFG_PORT_WIDTH_CS_ADDR_WIDTH = 3,
// cfg: timing parameters
CFG_PORT_WIDTH_CAS_WR_LAT = 4, // max will be 8 in DDR3
CFG_PORT_WIDTH_ADD_LAT = 3, // max will be 10 in DDR3
CFG_PORT_WIDTH_TCL = 4, // max will be 11 in DDR3
CFG_PORT_WIDTH_TRRD = 4, // 2 - 8 enough?
CFG_PORT_WIDTH_TFAW = 6, // 6 - 32 enough?
CFG_PORT_WIDTH_TRFC = 8, // 12-140 enough?
CFG_PORT_WIDTH_TREFI = 13, // 780 - 6240 enough?
CFG_PORT_WIDTH_TRCD = 4, // 2 - 11 enough?
CFG_PORT_WIDTH_TRP = 4, // 2 - 11 enough?
CFG_PORT_WIDTH_TWR = 4, // 2 - 12 enough?
CFG_PORT_WIDTH_TWTR = 4, // 1 - 10 enough?
CFG_PORT_WIDTH_TRTP = 4, // 2 - 8 enough?
CFG_PORT_WIDTH_TRAS = 5, // 4 - 29 enough?
CFG_PORT_WIDTH_TRC = 6, // 8 - 40 enough?
CFG_PORT_WIDTH_TCCD = 4, // max will be 8 in DDR3
CFG_PORT_WIDTH_TMRD = 3, // 4 - ? enough?
CFG_PORT_WIDTH_SELF_RFSH_EXIT_CYCLES = 10, // max will be 512 in DDR3
CFG_PORT_WIDTH_PDN_EXIT_CYCLES = 4, // 3 - ? enough?
CFG_PORT_WIDTH_AUTO_PD_CYCLES = 16, // enough?
CFG_PORT_WIDTH_POWER_SAVING_EXIT_CYCLES = 4, // enough?
CFG_PORT_WIDTH_MEM_CLK_ENTRY_CYCLES = 4, // enough?
// cfg: extra timing parameters
CFG_PORT_WIDTH_EXTRA_CTL_CLK_ACT_TO_RDWR = 4,
CFG_PORT_WIDTH_EXTRA_CTL_CLK_ACT_TO_PCH = 4,
CFG_PORT_WIDTH_EXTRA_CTL_CLK_ACT_TO_ACT = 4,
CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_RD = 4,
CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_RD_DIFF_CHIP = 4,
CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_WR = 4,
CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_WR_BC = 4,
CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP = 4,
CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_PCH = 4,
CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_AP_TO_VALID = 4,
CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_WR = 4,
CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_WR_DIFF_CHIP = 4,
CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_RD = 4,
CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_RD_BC = 4,
CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_RD_DIFF_CHIP = 4,
CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_PCH = 4,
CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_AP_TO_VALID = 4,
CFG_PORT_WIDTH_EXTRA_CTL_CLK_PCH_TO_VALID = 4,
CFG_PORT_WIDTH_EXTRA_CTL_CLK_PCH_ALL_TO_VALID = 4,
CFG_PORT_WIDTH_EXTRA_CTL_CLK_ACT_TO_ACT_DIFF_BANK = 4,
CFG_PORT_WIDTH_EXTRA_CTL_CLK_FOUR_ACT_TO_ACT = 4,
CFG_PORT_WIDTH_EXTRA_CTL_CLK_ARF_TO_VALID = 4,
CFG_PORT_WIDTH_EXTRA_CTL_CLK_PDN_TO_VALID = 4,
CFG_PORT_WIDTH_EXTRA_CTL_CLK_SRF_TO_VALID = 4,
CFG_PORT_WIDTH_EXTRA_CTL_CLK_SRF_TO_ZQ_CAL = 4,
CFG_PORT_WIDTH_EXTRA_CTL_CLK_ARF_PERIOD = 4,
CFG_PORT_WIDTH_EXTRA_CTL_CLK_PDN_PERIOD = 4,
// cfg: control signals
CFG_PORT_WIDTH_REORDER_DATA = 1,
CFG_PORT_WIDTH_STARVE_LIMIT = 6,
CFG_PORT_WIDTH_USER_RFSH = 1,
CFG_PORT_WIDTH_SELF_RFSH = 1,
CFG_PORT_WIDTH_REGDIMM_ENABLE = 1,
CFG_PORT_WIDTH_ENABLE_BURST_INTERRUPT = 1,
CFG_PORT_WIDTH_ENABLE_BURST_TERMINATE = 1,
CFG_ENABLE_CMD_SPLIT = 1'b1, // disable this (set to 0) when using the controller with hard MPFE
CFG_ENABLE_WDATA_PATH_LATENCY = 0,
// cfg: ecc signals
CFG_PORT_WIDTH_ENABLE_ECC = 1,
CFG_PORT_WIDTH_ENABLE_AUTO_CORR = 1,
CFG_PORT_WIDTH_GEN_SBE = 1,
CFG_PORT_WIDTH_GEN_DBE = 1,
CFG_PORT_WIDTH_ENABLE_INTR = 1,
CFG_PORT_WIDTH_MASK_SBE_INTR = 1,
CFG_PORT_WIDTH_MASK_DBE_INTR = 1,
CFG_PORT_WIDTH_MASK_CORR_DROPPED_INTR = 1,
CFG_PORT_WIDTH_CLR_INTR = 1,
CFG_PORT_WIDTH_ENABLE_ECC_CODE_OVERWRITES = 1,
CFG_PORT_WIDTH_ENABLE_NO_DM = 1,
CFG_ECC_DECODER_REG = 1,
// cfg: odt
CFG_PORT_WIDTH_WRITE_ODT_CHIP = 4,
CFG_PORT_WIDTH_READ_ODT_CHIP = 4,
// cfg: ecc signals
STS_PORT_WIDTH_SBE_ERROR = 1,
STS_PORT_WIDTH_DBE_ERROR = 1,
STS_PORT_WIDTH_CORR_DROP_ERROR = 1,
STS_PORT_WIDTH_SBE_COUNT = 8,
STS_PORT_WIDTH_DBE_COUNT = 8,
STS_PORT_WIDTH_CORR_DROP_COUNT = 8,
// PHY parameters
CFG_WLAT_BUS_WIDTH = 4,
CFG_RRANK_BUS_WIDTH = 1,
CFG_WRANK_BUS_WIDTH = 1,
CFG_USE_SHADOW_REGS = 0,
// controller read data return mode
CFG_RDATA_RETURN_MODE = "PASSTHROUGH",
CFG_ERRCMD_FIFO_REG = 0,
CFG_ENABLE_BURST_MERGE = 0
)
(
// Clock and reset
ctl_clk,
ctl_reset_n,
// Command channel
itf_cmd_ready,
itf_cmd_valid,
itf_cmd,
itf_cmd_address,
itf_cmd_burstlen,
itf_cmd_id,
itf_cmd_priority,
itf_cmd_autopercharge,
itf_cmd_multicast,
// Write data channel
itf_wr_data_ready,
itf_wr_data_valid,
itf_wr_data,
itf_wr_data_byte_en,
itf_wr_data_begin,
itf_wr_data_last,
itf_wr_data_id,
// Read data channel
itf_rd_data_ready,
itf_rd_data_valid,
itf_rd_data,
itf_rd_data_error,
itf_rd_data_begin,
itf_rd_data_last,
itf_rd_data_id,
itf_rd_data_id_early, // only valid when CFG_RDATA_RETURN_MODE == PASSTHROUGH
itf_rd_data_id_early_valid, // only valid when CFG_RDATA_RETURN_MODE == PASSTHROUGH
// Sideband signals
local_refresh_req,
local_refresh_chip,
local_zqcal_req,
local_zqcal_chip,
local_deep_powerdn_chip,
local_deep_powerdn_req,
local_self_rfsh_req,
local_self_rfsh_chip,
local_refresh_ack,
local_deep_powerdn_ack,
local_power_down_ack,
local_self_rfsh_ack,
local_init_done,
// Controller commands to the AFI interface
afi_rst_n,
afi_ba,
afi_addr,
afi_cke,
afi_cs_n,
afi_ras_n,
afi_cas_n,
afi_we_n,
afi_odt,
// Controller read and write data to the AFI interface
afi_wlat,
afi_dqs_burst,
afi_dm,
afi_wdata,
afi_wdata_valid,
afi_rdata_en,
afi_rdata_en_full,
afi_rrank,
afi_wrank,
afi_rdata,
afi_rdata_valid,
// Status and control signal to the AFI interface
ctl_cal_success,
ctl_cal_fail,
ctl_cal_req,
ctl_init_req,
ctl_mem_clk_disable,
ctl_cal_byte_lane_sel_n,
// cfg: general
cfg_type,
cfg_interface_width, // not sure where this signal is used
cfg_burst_length,
cfg_device_width, // not sure where this signal is used
cfg_output_regd,
// cfg: address mapping signals
cfg_addr_order,
cfg_col_addr_width,
cfg_row_addr_width,
cfg_bank_addr_width,
cfg_cs_addr_width,
// cfg: timing parameters
cfg_cas_wr_lat,
cfg_add_lat,
cfg_tcl,
cfg_trrd,
cfg_tfaw,
cfg_trfc,
cfg_trefi,
cfg_trcd,
cfg_trp,
cfg_twr,
cfg_twtr,
cfg_trtp,
cfg_tras,
cfg_trc,
cfg_tccd,
cfg_auto_pd_cycles,
cfg_self_rfsh_exit_cycles,
cfg_pdn_exit_cycles,
cfg_power_saving_exit_cycles,
cfg_mem_clk_entry_cycles,
cfg_tmrd,
// cfg: extra timing parameters
cfg_extra_ctl_clk_act_to_rdwr,
cfg_extra_ctl_clk_act_to_pch,
cfg_extra_ctl_clk_act_to_act,
cfg_extra_ctl_clk_rd_to_rd,
cfg_extra_ctl_clk_rd_to_rd_diff_chip,
cfg_extra_ctl_clk_rd_to_wr,
cfg_extra_ctl_clk_rd_to_wr_bc,
cfg_extra_ctl_clk_rd_to_wr_diff_chip,
cfg_extra_ctl_clk_rd_to_pch,
cfg_extra_ctl_clk_rd_ap_to_valid,
cfg_extra_ctl_clk_wr_to_wr,
cfg_extra_ctl_clk_wr_to_wr_diff_chip,
cfg_extra_ctl_clk_wr_to_rd,
cfg_extra_ctl_clk_wr_to_rd_bc,
cfg_extra_ctl_clk_wr_to_rd_diff_chip,
cfg_extra_ctl_clk_wr_to_pch,
cfg_extra_ctl_clk_wr_ap_to_valid,
cfg_extra_ctl_clk_pch_to_valid,
cfg_extra_ctl_clk_pch_all_to_valid,
cfg_extra_ctl_clk_act_to_act_diff_bank,
cfg_extra_ctl_clk_four_act_to_act,
cfg_extra_ctl_clk_arf_to_valid,
cfg_extra_ctl_clk_pdn_to_valid,
cfg_extra_ctl_clk_srf_to_valid,
cfg_extra_ctl_clk_srf_to_zq_cal,
cfg_extra_ctl_clk_arf_period,
cfg_extra_ctl_clk_pdn_period,
// cfg: control signals
cfg_reorder_data, // enable data reordering
cfg_starve_limit, // starvation counter limit
cfg_user_rfsh,
cfg_regdimm_enable,
cfg_enable_burst_interrupt,
cfg_enable_burst_terminate,
// cfg: ecc signals
cfg_enable_ecc,
cfg_enable_auto_corr,
cfg_enable_ecc_code_overwrites,
cfg_enable_no_dm,
cfg_gen_sbe,
cfg_gen_dbe,
cfg_enable_intr,
cfg_mask_sbe_intr,
cfg_mask_dbe_intr,
cfg_mask_corr_dropped_intr,
cfg_clr_intr,
// cfg: odt
cfg_write_odt_chip,
cfg_read_odt_chip,
// sts: ecc signals
ecc_interrupt,
sts_sbe_error,
sts_dbe_error,
sts_corr_dropped,
sts_sbe_count,
sts_dbe_count,
sts_corr_dropped_count,
sts_err_addr,
sts_corr_dropped_addr,
//calibration
cfg_cal_req,
sts_cal_fail,
sts_cal_success,
// DQS enable tracking
cfg_enable_dqs_tracking, //enable DQS enable tracking support in controller
afi_ctl_refresh_done, // Controller asserts this after tRFC is done, also acts as stall ack to phy
afi_seq_busy, // Sequencer busy signal to controller, also acts as stall request to ctlr
afi_ctl_long_idle, // Controller asserts this after long period of no refresh, protocol is the same as rfsh_done
// Refresh controller
tbp_empty,
cmd_gen_busy,
sideband_in_refresh
);
// General parameters
localparam CFG_ECC_BE_ALLLOW_RMW = 0;
localparam CFG_MEM_IF_DQ_PER_DQS = CFG_MEM_IF_DQ_WIDTH / CFG_MEM_IF_DQS_WIDTH;
localparam CFG_INT_SIZE_WIDTH = (CFG_DWIDTH_RATIO == 2) ? 4 : ((CFG_DWIDTH_RATIO == 4) ? 3 : ((CFG_DWIDTH_RATIO == 8) ? 2 : 4));
localparam CFG_CTL_QUEUE_DEPTH = 8;
localparam CFG_ENABLE_QUEUE = 0;
//localparam CFG_ENABLE_BURST_MERGE = 0;
localparam CFG_CMD_GEN_OUTPUT_REG = 1; // only in effect when CFG_ENABLE_QUEUE is set to '0'
localparam CFG_CTL_ARBITER_TYPE = "ROWCOL";
localparam CFG_AFI_INTF_PHASE_NUM = 2;
localparam CFG_ECC_DATA_WIDTH = CFG_MEM_IF_DQ_WIDTH * CFG_DWIDTH_RATIO;
localparam CFG_ECC_DM_WIDTH = CFG_ECC_DATA_WIDTH / CFG_MEM_IF_DQ_PER_DQS;
localparam CFG_ECC_CODE_WIDTH = 8;
localparam CFG_ECC_MULTIPLES = CFG_DWIDTH_RATIO * CFG_ECC_MULTIPLES_16_24_40_72;
localparam CFG_PARTIAL_BE_PER_WORD_ENABLE = 1;
localparam CFG_ENABLE_BURST_GEN_OUTPUT_REG = 1;
localparam CFG_DISABLE_PRIORITY = 1;
localparam CFG_REG_GRANT = (CFG_DWIDTH_RATIO == 8) ? 0 : 1; // disable grant register for better efficiency in quarter rate
localparam CFG_REG_REQ = 0;
localparam CFG_RANK_TIMER_OUTPUT_REG = 1;
localparam CFG_ECC_DEC_REG = 1;
localparam CFG_ECC_RDATA_REG = 1;
localparam CFG_ECC_ENC_REG = 1;
localparam CFG_WDATA_REG = CFG_ENABLE_WDATA_PATH_LATENCY;
localparam CFG_DISABLE_READ_REODERING = 0;
localparam CFG_ENABLE_SHADOW_TBP = 0;
localparam CFG_CTL_SHADOW_TBP_NUM = CFG_CTL_TBP_NUM; // similar to TBP number
// Datapath buffer & fifo size calculation
localparam CFG_MAX_PENDING_ERR_CMD = 8; // temporary
localparam CFG_MAX_PENDING_RD_CMD_WIDTH = log2(CFG_MAX_PENDING_RD_CMD);
localparam CFG_WRDATA_ID_WIDTH = log2(CFG_MAX_PENDING_WR_CMD);
localparam CFG_ERRCMD_FIFO_ADDR_WIDTH = log2(CFG_MAX_PENDING_ERR_CMD);
localparam CFG_RDDATA_ID_WIDTH = CFG_RDBUFFER_ADDR_WIDTH - CFG_INT_SIZE_WIDTH;
localparam CFG_DATA_ID_WIDTH = (CFG_WRDATA_ID_WIDTH >= CFG_RDDATA_ID_WIDTH) ? CFG_WRDATA_ID_WIDTH : CFG_RDDATA_ID_WIDTH;
// to avoid -1
localparam integer CFG_DATA_ID_REMAINDER = (CFG_WRDATA_ID_WIDTH < CFG_DATA_ID_WIDTH) ? 0 : 2**(CFG_WRDATA_ID_WIDTH-CFG_DATA_ID_WIDTH);
localparam CFG_WRDATA_VEC_ID_WIDTH = CFG_MAX_PENDING_WR_CMD;
// AFI
localparam CFG_ADDR_RATE_RATIO = (CFG_LPDDR2_ENABLED == 1) ? 2 : 1;
localparam CFG_AFI_IF_FR_ADDR_WIDTH = CFG_ADDR_RATE_RATIO * CFG_MEM_IF_ADDR_WIDTH;
localparam CFG_DRAM_WLAT_GROUP = (CFG_WLAT_BUS_WIDTH <= 6) ? 1 : CFG_MEM_IF_DQS_WIDTH; // Supports single / multiple DQS group of afi_wlat
localparam CFG_LOCAL_WLAT_GROUP = (CFG_WLAT_BUS_WIDTH <= 6) ? 1 : (((CFG_LOCAL_DATA_WIDTH / CFG_DWIDTH_RATIO) == CFG_MEM_IF_DQ_WIDTH) ? CFG_MEM_IF_DQS_WIDTH : CFG_MEM_IF_DQS_WIDTH - CFG_ECC_MULTIPLES_16_24_40_72); // Determine the wlat group for local data width (without ECC code)
// Derived timing parameters width
localparam T_PARAM_ACT_TO_RDWR_WIDTH = (CFG_DWIDTH_RATIO == 8) ? 3 : (CFG_DWIDTH_RATIO == 4) ? 3 : 4; //case:234203
localparam T_PARAM_ACT_TO_PCH_WIDTH = (CFG_DWIDTH_RATIO == 8) ? 4 : (CFG_DWIDTH_RATIO == 4) ? 5 : 6;
localparam T_PARAM_ACT_TO_ACT_WIDTH = (CFG_DWIDTH_RATIO == 8) ? 4 : (CFG_DWIDTH_RATIO == 4) ? 5 : 6;
localparam T_PARAM_RD_TO_RD_WIDTH = (CFG_DWIDTH_RATIO == 8) ? 4 : (CFG_DWIDTH_RATIO == 4) ? 5 : 6;
localparam T_PARAM_RD_TO_WR_WIDTH = (CFG_DWIDTH_RATIO == 8) ? 4 : (CFG_DWIDTH_RATIO == 4) ? 5 : 6;
localparam T_PARAM_RD_TO_WR_BC_WIDTH = (CFG_DWIDTH_RATIO == 8) ? 4 : (CFG_DWIDTH_RATIO == 4) ? 5 : 6;
localparam T_PARAM_RD_TO_PCH_WIDTH = (CFG_DWIDTH_RATIO == 8) ? 4 : (CFG_DWIDTH_RATIO == 4) ? 5 : 6;
localparam T_PARAM_RD_AP_TO_VALID_WIDTH = (CFG_DWIDTH_RATIO == 8) ? 4 : (CFG_DWIDTH_RATIO == 4) ? 5 : 6;
localparam T_PARAM_WR_TO_WR_WIDTH = (CFG_DWIDTH_RATIO == 8) ? 4 : (CFG_DWIDTH_RATIO == 4) ? 5 : 6;
localparam T_PARAM_WR_TO_RD_WIDTH = (CFG_DWIDTH_RATIO == 8) ? 4 : (CFG_DWIDTH_RATIO == 4) ? 5 : 6;
localparam T_PARAM_WR_TO_RD_BC_WIDTH = (CFG_DWIDTH_RATIO == 8) ? 4 : (CFG_DWIDTH_RATIO == 4) ? 5 : 6;
localparam T_PARAM_WR_TO_PCH_WIDTH = (CFG_DWIDTH_RATIO == 8) ? 4 : (CFG_DWIDTH_RATIO == 4) ? 5 : 6;
localparam T_PARAM_WR_AP_TO_VALID_WIDTH = (CFG_DWIDTH_RATIO == 8) ? 4 : (CFG_DWIDTH_RATIO == 4) ? 5 : 6;
localparam T_PARAM_PCH_TO_VALID_WIDTH = (CFG_DWIDTH_RATIO == 8) ? 3 : (CFG_DWIDTH_RATIO == 4) ? 3 : 4; //case:234203
localparam T_PARAM_PCH_ALL_TO_VALID_WIDTH = (CFG_DWIDTH_RATIO == 8) ? 3 : (CFG_DWIDTH_RATIO == 4) ? 3 : 4; //case:234203
localparam T_PARAM_RD_TO_RD_DIFF_CHIP_WIDTH = (CFG_DWIDTH_RATIO == 8) ? 2 : (CFG_DWIDTH_RATIO == 4) ? 3 : 4;
localparam T_PARAM_RD_TO_WR_DIFF_CHIP_WIDTH = (CFG_DWIDTH_RATIO == 8) ? 4 : (CFG_DWIDTH_RATIO == 4) ? 5 : 6;
localparam T_PARAM_WR_TO_WR_DIFF_CHIP_WIDTH = (CFG_DWIDTH_RATIO == 8) ? 2 : (CFG_DWIDTH_RATIO == 4) ? 3 : 4;
localparam T_PARAM_WR_TO_RD_DIFF_CHIP_WIDTH = (CFG_DWIDTH_RATIO == 8) ? 4 : (CFG_DWIDTH_RATIO == 4) ? 5 : 6;
localparam T_PARAM_ACT_TO_ACT_DIFF_BANK_WIDTH = (CFG_DWIDTH_RATIO == 8) ? 4 : (CFG_DWIDTH_RATIO == 4) ? 5 : 6;
localparam T_PARAM_FOUR_ACT_TO_ACT_WIDTH = (CFG_DWIDTH_RATIO == 8) ? 4 : (CFG_DWIDTH_RATIO == 4) ? 5 : 6;
localparam T_PARAM_ARF_TO_VALID_WIDTH = (CFG_DWIDTH_RATIO == 8) ? 7 : (CFG_DWIDTH_RATIO == 4) ? 8 : 9;
localparam T_PARAM_PDN_TO_VALID_WIDTH = (CFG_DWIDTH_RATIO == 8) ? 3 : (CFG_DWIDTH_RATIO == 4) ? 3 : 4; //case:234203
localparam T_PARAM_SRF_TO_VALID_WIDTH = (CFG_DWIDTH_RATIO == 8) ? 8 : (CFG_DWIDTH_RATIO == 4) ? 9 : 10;
localparam T_PARAM_SRF_TO_ZQ_CAL_WIDTH = (CFG_DWIDTH_RATIO == 8) ? 7 : (CFG_DWIDTH_RATIO == 4) ? 8 : 9;
localparam T_PARAM_ARF_PERIOD_WIDTH = (CFG_DWIDTH_RATIO == 8) ? 12 : (CFG_DWIDTH_RATIO == 4) ? 12 : 13; //case:234203
localparam T_PARAM_PDN_PERIOD_WIDTH = 17; //case:234203
localparam T_PARAM_POWER_SAVING_EXIT_WIDTH = (CFG_DWIDTH_RATIO == 8) ? 3 : (CFG_DWIDTH_RATIO == 4) ? 2 : 3; //case:234203
localparam T_PARAM_MEM_CLK_ENTRY_CYCLES_WIDTH = (CFG_PORT_WIDTH_MEM_CLK_ENTRY_CYCLES > 6) ? CFG_PORT_WIDTH_MEM_CLK_ENTRY_CYCLES : 5; //case:234203
localparam integer CFG_DATAID_ARRAY_DEPTH = 2**CFG_DATA_ID_WIDTH;
localparam integer CFG_WRDATA_ID_WIDTH_SQRD = 2**CFG_WRDATA_ID_WIDTH;
// Clock and reset
input ctl_clk;
input ctl_reset_n;
// Command channel
output itf_cmd_ready;
input itf_cmd_valid;
input itf_cmd;
input [CFG_LOCAL_ADDR_WIDTH - 1 : 0] itf_cmd_address;
input [CFG_LOCAL_SIZE_WIDTH - 1 : 0] itf_cmd_burstlen;
input [CFG_LOCAL_ID_WIDTH - 1 : 0] itf_cmd_id;
input itf_cmd_priority;
input itf_cmd_autopercharge;
input itf_cmd_multicast;
// Write data channel
output itf_wr_data_ready;
input itf_wr_data_valid;
input [CFG_LOCAL_DATA_WIDTH - 1 : 0] itf_wr_data;
input [CFG_LOCAL_DATA_WIDTH / 8 - 1 : 0] itf_wr_data_byte_en;
input itf_wr_data_begin;
input itf_wr_data_last;
input [CFG_LOCAL_ID_WIDTH - 1 : 0] itf_wr_data_id;
// Read data channel
input itf_rd_data_ready;
output itf_rd_data_valid;
output [CFG_LOCAL_DATA_WIDTH - 1 : 0] itf_rd_data;
output itf_rd_data_error;
output itf_rd_data_begin;
output itf_rd_data_last;
output [CFG_LOCAL_ID_WIDTH - 1 : 0] itf_rd_data_id;
output [CFG_LOCAL_ID_WIDTH - 1 : 0] itf_rd_data_id_early;
output itf_rd_data_id_early_valid;
// Sideband signals
input local_refresh_req;
input [CFG_MEM_IF_CHIP - 1 : 0] local_refresh_chip;
input local_zqcal_req;
input [CFG_MEM_IF_CHIP - 1 : 0] local_zqcal_chip;
input local_deep_powerdn_req;
input [CFG_MEM_IF_CHIP-1:0] local_deep_powerdn_chip;
input local_self_rfsh_req;
input [CFG_MEM_IF_CHIP - 1 : 0] local_self_rfsh_chip;
output local_refresh_ack;
output local_deep_powerdn_ack;
output local_power_down_ack;
output local_self_rfsh_ack;
output local_init_done;
// Controller commands to the AFI interface
output [(CFG_DWIDTH_RATIO / 2) - 1 : 0] afi_rst_n;
output [(CFG_MEM_IF_BA_WIDTH * (CFG_DWIDTH_RATIO / 2)) - 1 : 0] afi_ba;
output [(CFG_AFI_IF_FR_ADDR_WIDTH*(CFG_DWIDTH_RATIO / 2))- 1 : 0] afi_addr;
output [(CFG_MEM_IF_CKE_WIDTH * (CFG_DWIDTH_RATIO / 2)) - 1 : 0] afi_cke;
output [(CFG_MEM_IF_CHIP * (CFG_DWIDTH_RATIO / 2)) - 1 : 0] afi_cs_n;
output [(CFG_DWIDTH_RATIO / 2) - 1 : 0] afi_ras_n;
output [(CFG_DWIDTH_RATIO / 2) - 1 : 0] afi_cas_n;
output [(CFG_DWIDTH_RATIO / 2) - 1 : 0] afi_we_n;
output [(CFG_MEM_IF_ODT_WIDTH * (CFG_DWIDTH_RATIO / 2)) - 1 : 0] afi_odt;
// Controller read and write data to the AFI interface
input [CFG_WLAT_BUS_WIDTH - 1 : 0] afi_wlat;
output [CFG_MEM_IF_DQS_WIDTH * (CFG_DWIDTH_RATIO / 2) - 1 : 0] afi_dqs_burst;
output [CFG_MEM_IF_DM_WIDTH * CFG_DWIDTH_RATIO - 1 : 0] afi_dm;
output [CFG_MEM_IF_DQ_WIDTH * CFG_DWIDTH_RATIO - 1 : 0] afi_wdata;
output [CFG_MEM_IF_DQS_WIDTH * (CFG_DWIDTH_RATIO / 2) - 1 : 0] afi_wdata_valid;
output [CFG_MEM_IF_DQS_WIDTH * (CFG_DWIDTH_RATIO / 2) - 1 : 0] afi_rdata_en;
output [CFG_MEM_IF_DQS_WIDTH * (CFG_DWIDTH_RATIO / 2) - 1 : 0] afi_rdata_en_full;
output [CFG_RRANK_BUS_WIDTH - 1 : 0] afi_rrank;
output [CFG_WRANK_BUS_WIDTH - 1 : 0] afi_wrank;
input [CFG_MEM_IF_DQ_WIDTH * CFG_DWIDTH_RATIO - 1 : 0] afi_rdata;
input [CFG_DWIDTH_RATIO / 2 - 1 : 0] afi_rdata_valid;
// Status and control signal to the AFI interface
input ctl_cal_success;
input ctl_cal_fail;
output ctl_cal_req;
output ctl_init_req;
output [CFG_MEM_IF_DQS_WIDTH * CFG_MEM_IF_CHIP - 1 : 0] ctl_cal_byte_lane_sel_n ;
output [CFG_MEM_IF_CLK_PAIR_COUNT - 1 : 0] ctl_mem_clk_disable;
// cfg: general
input [CFG_PORT_WIDTH_TYPE - 1 : 0] cfg_type;
input [CFG_PORT_WIDTH_INTERFACE_WIDTH - 1 : 0] cfg_interface_width;
input [CFG_PORT_WIDTH_BURST_LENGTH - 1 : 0] cfg_burst_length;
input [CFG_PORT_WIDTH_DEVICE_WIDTH - 1 : 0] cfg_device_width;
input [CFG_PORT_WIDTH_OUTPUT_REGD - 1 : 0] cfg_output_regd;
// cfg: address mapping signals
input [CFG_PORT_WIDTH_ADDR_ORDER - 1 : 0] cfg_addr_order;
input [CFG_PORT_WIDTH_COL_ADDR_WIDTH - 1 : 0] cfg_col_addr_width;
input [CFG_PORT_WIDTH_ROW_ADDR_WIDTH - 1 : 0] cfg_row_addr_width;
input [CFG_PORT_WIDTH_BANK_ADDR_WIDTH - 1 : 0] cfg_bank_addr_width;
input [CFG_PORT_WIDTH_CS_ADDR_WIDTH - 1 : 0] cfg_cs_addr_width;
// cfg: timing parameters
input [CFG_PORT_WIDTH_CAS_WR_LAT - 1 : 0] cfg_cas_wr_lat;
input [CFG_PORT_WIDTH_ADD_LAT - 1 : 0] cfg_add_lat;
input [CFG_PORT_WIDTH_TCL - 1 : 0] cfg_tcl;
input [CFG_PORT_WIDTH_TRRD - 1 : 0] cfg_trrd;
input [CFG_PORT_WIDTH_TFAW - 1 : 0] cfg_tfaw;
input [CFG_PORT_WIDTH_TRFC - 1 : 0] cfg_trfc;
input [CFG_PORT_WIDTH_TREFI - 1 : 0] cfg_trefi;
input [CFG_PORT_WIDTH_TRCD - 1 : 0] cfg_trcd;
input [CFG_PORT_WIDTH_TRP - 1 : 0] cfg_trp;
input [CFG_PORT_WIDTH_TWR - 1 : 0] cfg_twr;
input [CFG_PORT_WIDTH_TWTR - 1 : 0] cfg_twtr;
input [CFG_PORT_WIDTH_TRTP - 1 : 0] cfg_trtp;
input [CFG_PORT_WIDTH_TRAS - 1 : 0] cfg_tras;
input [CFG_PORT_WIDTH_TRC - 1 : 0] cfg_trc;
input [CFG_PORT_WIDTH_TCCD - 1 : 0] cfg_tccd;
input [CFG_PORT_WIDTH_AUTO_PD_CYCLES - 1 : 0] cfg_auto_pd_cycles;
input [CFG_PORT_WIDTH_SELF_RFSH_EXIT_CYCLES - 1 : 0] cfg_self_rfsh_exit_cycles;
input [CFG_PORT_WIDTH_PDN_EXIT_CYCLES - 1 : 0] cfg_pdn_exit_cycles;
input [CFG_PORT_WIDTH_POWER_SAVING_EXIT_CYCLES - 1 : 0] cfg_power_saving_exit_cycles;
input [CFG_PORT_WIDTH_MEM_CLK_ENTRY_CYCLES - 1 : 0] cfg_mem_clk_entry_cycles;
input [CFG_PORT_WIDTH_TMRD - 1 : 0] cfg_tmrd;
// cfg: extra timing parameters
input [CFG_PORT_WIDTH_EXTRA_CTL_CLK_ACT_TO_RDWR - 1 : 0] cfg_extra_ctl_clk_act_to_rdwr;
input [CFG_PORT_WIDTH_EXTRA_CTL_CLK_ACT_TO_PCH - 1 : 0] cfg_extra_ctl_clk_act_to_pch;
input [CFG_PORT_WIDTH_EXTRA_CTL_CLK_ACT_TO_ACT - 1 : 0] cfg_extra_ctl_clk_act_to_act;
input [CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_RD - 1 : 0] cfg_extra_ctl_clk_rd_to_rd;
input [CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_RD_DIFF_CHIP - 1 : 0] cfg_extra_ctl_clk_rd_to_rd_diff_chip;
input [CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_WR - 1 : 0] cfg_extra_ctl_clk_rd_to_wr;
input [CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_WR_BC - 1 : 0] cfg_extra_ctl_clk_rd_to_wr_bc;
input [CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP - 1 : 0] cfg_extra_ctl_clk_rd_to_wr_diff_chip;
input [CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_PCH - 1 : 0] cfg_extra_ctl_clk_rd_to_pch;
input [CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_AP_TO_VALID - 1 : 0] cfg_extra_ctl_clk_rd_ap_to_valid;
input [CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_WR - 1 : 0] cfg_extra_ctl_clk_wr_to_wr;
input [CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_WR_DIFF_CHIP - 1 : 0] cfg_extra_ctl_clk_wr_to_wr_diff_chip;
input [CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_RD - 1 : 0] cfg_extra_ctl_clk_wr_to_rd;
input [CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_RD_BC - 1 : 0] cfg_extra_ctl_clk_wr_to_rd_bc;
input [CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_RD_DIFF_CHIP - 1 : 0] cfg_extra_ctl_clk_wr_to_rd_diff_chip;
input [CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_PCH - 1 : 0] cfg_extra_ctl_clk_wr_to_pch;
input [CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_AP_TO_VALID - 1 : 0] cfg_extra_ctl_clk_wr_ap_to_valid;
input [CFG_PORT_WIDTH_EXTRA_CTL_CLK_PCH_TO_VALID - 1 : 0] cfg_extra_ctl_clk_pch_to_valid;
input [CFG_PORT_WIDTH_EXTRA_CTL_CLK_PCH_ALL_TO_VALID - 1 : 0] cfg_extra_ctl_clk_pch_all_to_valid;
input [CFG_PORT_WIDTH_EXTRA_CTL_CLK_ACT_TO_ACT_DIFF_BANK - 1 : 0] cfg_extra_ctl_clk_act_to_act_diff_bank;
input [CFG_PORT_WIDTH_EXTRA_CTL_CLK_FOUR_ACT_TO_ACT - 1 : 0] cfg_extra_ctl_clk_four_act_to_act;
input [CFG_PORT_WIDTH_EXTRA_CTL_CLK_ARF_TO_VALID - 1 : 0] cfg_extra_ctl_clk_arf_to_valid;
input [CFG_PORT_WIDTH_EXTRA_CTL_CLK_PDN_TO_VALID - 1 : 0] cfg_extra_ctl_clk_pdn_to_valid;
input [CFG_PORT_WIDTH_EXTRA_CTL_CLK_SRF_TO_VALID - 1 : 0] cfg_extra_ctl_clk_srf_to_valid;
input [CFG_PORT_WIDTH_EXTRA_CTL_CLK_SRF_TO_ZQ_CAL - 1 : 0] cfg_extra_ctl_clk_srf_to_zq_cal;
input [CFG_PORT_WIDTH_EXTRA_CTL_CLK_ARF_PERIOD - 1 : 0] cfg_extra_ctl_clk_arf_period;
input [CFG_PORT_WIDTH_EXTRA_CTL_CLK_PDN_PERIOD - 1 : 0] cfg_extra_ctl_clk_pdn_period;
// cfg: control signals
input [CFG_PORT_WIDTH_REORDER_DATA - 1 : 0] cfg_reorder_data;
input [CFG_PORT_WIDTH_STARVE_LIMIT - 1 : 0] cfg_starve_limit;
input [CFG_PORT_WIDTH_USER_RFSH - 1 : 0] cfg_user_rfsh;
input [CFG_PORT_WIDTH_REGDIMM_ENABLE - 1 : 0] cfg_regdimm_enable;
input [CFG_PORT_WIDTH_ENABLE_BURST_INTERRUPT - 1 : 0] cfg_enable_burst_interrupt;
input [CFG_PORT_WIDTH_ENABLE_BURST_TERMINATE - 1 : 0] cfg_enable_burst_terminate;
// cfg: ecc signals
input [CFG_PORT_WIDTH_ENABLE_ECC - 1 : 0] cfg_enable_ecc;
input [CFG_PORT_WIDTH_ENABLE_AUTO_CORR - 1 : 0] cfg_enable_auto_corr;
input [CFG_PORT_WIDTH_ENABLE_NO_DM - 1 : 0] cfg_enable_no_dm;
input [CFG_PORT_WIDTH_GEN_SBE - 1 : 0] cfg_gen_sbe;
input [CFG_PORT_WIDTH_GEN_DBE - 1 : 0] cfg_gen_dbe;
input [CFG_PORT_WIDTH_ENABLE_INTR - 1 : 0] cfg_enable_intr;
input [CFG_PORT_WIDTH_MASK_SBE_INTR - 1 : 0] cfg_mask_sbe_intr;
input [CFG_PORT_WIDTH_MASK_DBE_INTR - 1 : 0] cfg_mask_dbe_intr;
input [CFG_PORT_WIDTH_MASK_CORR_DROPPED_INTR - 1 : 0] cfg_mask_corr_dropped_intr;
input [CFG_PORT_WIDTH_CLR_INTR - 1 : 0] cfg_clr_intr;
input [CFG_PORT_WIDTH_ENABLE_ECC_CODE_OVERWRITES - 1 : 0] cfg_enable_ecc_code_overwrites;
// cfg: odt
input [CFG_PORT_WIDTH_WRITE_ODT_CHIP - 1 : 0] cfg_write_odt_chip;
input [CFG_PORT_WIDTH_READ_ODT_CHIP - 1 : 0] cfg_read_odt_chip;
// sts: ecc signals
output ecc_interrupt;
output [STS_PORT_WIDTH_SBE_ERROR - 1 : 0] sts_sbe_error;
output [STS_PORT_WIDTH_DBE_ERROR - 1 : 0] sts_dbe_error;
output [STS_PORT_WIDTH_SBE_COUNT - 1 : 0] sts_sbe_count;
output [STS_PORT_WIDTH_DBE_COUNT - 1 : 0] sts_dbe_count;
output [CFG_LOCAL_ADDR_WIDTH - 1 : 0] sts_err_addr;
output [STS_PORT_WIDTH_CORR_DROP_ERROR - 1 : 0] sts_corr_dropped;
output [STS_PORT_WIDTH_CORR_DROP_COUNT - 1 : 0] sts_corr_dropped_count;
output [CFG_LOCAL_ADDR_WIDTH - 1 : 0] sts_corr_dropped_addr;
// calibration signals
input cfg_cal_req;
output sts_cal_fail;
output sts_cal_success;
// DQS enable tracking
input cfg_enable_dqs_tracking;
output [CFG_MEM_IF_CHIP - 1 : 0] afi_ctl_refresh_done;
input [CFG_MEM_IF_CHIP - 1 : 0] afi_seq_busy;
output [CFG_MEM_IF_CHIP - 1 : 0] afi_ctl_long_idle;
output tbp_empty;
output cmd_gen_busy;
output sideband_in_refresh;
//==============================================================================
//
// Wires
//
//==============================================================================
// alt_mem_ddrx_input_if
wire itf_cmd_ready;
wire itf_wr_data_ready;
wire itf_rd_data_valid;
wire [CFG_LOCAL_DATA_WIDTH - 1 : 0] itf_rd_data;
wire itf_rd_data_error;
wire itf_rd_data_begin;
wire itf_rd_data_last;
wire [CFG_LOCAL_ID_WIDTH - 1 : 0] itf_rd_data_id;
wire [CFG_LOCAL_ID_WIDTH - 1 : 0] itf_rd_data_id_early;
wire itf_rd_data_id_early_valid;
wire cmd_valid;
wire [CFG_LOCAL_ADDR_WIDTH - 1 : 0] cmd_address;
wire cmd_write;
wire cmd_read;
wire cmd_multicast;
wire [CFG_LOCAL_SIZE_WIDTH - 1 : 0] cmd_size;
wire cmd_priority;
wire cmd_autoprecharge;
wire [CFG_LOCAL_ID_WIDTH - 1 : 0] cmd_id;
wire [CFG_LOCAL_DATA_WIDTH - 1 : 0] write_data;
wire [CFG_LOCAL_DATA_WIDTH / 8 - 1 : 0] byte_en;
wire write_data_valid;
wire [CFG_LOCAL_ID_WIDTH - 1 : 0] write_data_id;
wire local_refresh_ack;
wire local_deep_powerdn_ack;
wire local_power_down_ack;
wire local_self_rfsh_ack;
wire local_init_done;
wire rfsh_req;
wire [CFG_MEM_IF_CHIP - 1 : 0] rfsh_chip;
wire zqcal_req;
wire deep_powerdn_req;
wire [CFG_MEM_IF_CHIP - 1 : 0] deep_powerdn_chip;
wire self_rfsh_req;
wire [CFG_MEM_IF_CHIP - 1 : 0] self_rfsh_chip;
// alt_mem_ddrx_cmd_gen
wire cmd_gen_load;
wire cmd_gen_waiting_to_load;
wire [CFG_MEM_IF_CS_WIDTH - 1 : 0] cmd_gen_chipsel;
wire [CFG_MEM_IF_BA_WIDTH - 1 : 0] cmd_gen_bank;
wire [CFG_MEM_IF_ROW_WIDTH - 1 : 0] cmd_gen_row;
wire [CFG_MEM_IF_COL_WIDTH - 1 : 0] cmd_gen_col;
wire cmd_gen_write;
wire cmd_gen_read;
wire cmd_gen_multicast;
wire [CFG_INT_SIZE_WIDTH - 1 : 0] cmd_gen_size;
wire [CFG_LOCAL_ID_WIDTH - 1 : 0] cmd_gen_localid;
wire [CFG_DATA_ID_WIDTH - 1 : 0] cmd_gen_dataid;
wire cmd_gen_priority;
wire cmd_gen_rmw_correct;
wire cmd_gen_rmw_partial;
wire cmd_gen_autopch;
wire cmd_gen_complete;
wire [CFG_CTL_TBP_NUM - 1 : 0] cmd_gen_same_chipsel_addr;
wire [CFG_CTL_TBP_NUM - 1 : 0] cmd_gen_same_bank_addr;
wire [CFG_CTL_TBP_NUM - 1 : 0] cmd_gen_same_row_addr;
wire [CFG_CTL_TBP_NUM - 1 : 0] cmd_gen_same_col_addr;
wire [CFG_CTL_TBP_NUM - 1 : 0] cmd_gen_same_read_cmd;
wire [CFG_CTL_TBP_NUM - 1 : 0] cmd_gen_same_write_cmd;
wire [CFG_CTL_SHADOW_TBP_NUM - 1 : 0] cmd_gen_same_shadow_chipsel_addr;
wire [CFG_CTL_SHADOW_TBP_NUM - 1 : 0] cmd_gen_same_shadow_bank_addr;
wire [CFG_CTL_SHADOW_TBP_NUM - 1 : 0] cmd_gen_same_shadow_row_addr;
wire cmd_gen_full;
// alt_mem_ddrx_tbp
wire tbp_full;
wire tbp_empty;
wire [CFG_CTL_TBP_NUM - 1 : 0] row_req;
wire [CFG_CTL_TBP_NUM - 1 : 0] act_req;
wire [CFG_CTL_TBP_NUM - 1 : 0] pch_req;
wire [CFG_CTL_TBP_NUM - 1 : 0] col_req;
wire [CFG_CTL_TBP_NUM - 1 : 0] rd_req;
wire [CFG_CTL_TBP_NUM - 1 : 0] wr_req;
wire [CFG_CTL_TBP_NUM - 1 : 0] tbp_read;
wire [CFG_CTL_TBP_NUM - 1 : 0] tbp_write;
wire [CFG_CTL_TBP_NUM - 1 : 0] tbp_precharge;
wire [CFG_CTL_TBP_NUM - 1 : 0] tbp_activate;
wire [(CFG_CTL_TBP_NUM * CFG_MEM_IF_CS_WIDTH) - 1 : 0] tbp_chipsel;
wire [(CFG_CTL_TBP_NUM * CFG_MEM_IF_BA_WIDTH) - 1 : 0] tbp_bank;
wire [(CFG_CTL_TBP_NUM * CFG_MEM_IF_ROW_WIDTH) - 1 : 0] tbp_row;
wire [(CFG_CTL_TBP_NUM * CFG_MEM_IF_COL_WIDTH) - 1 : 0] tbp_col;
wire [(CFG_CTL_SHADOW_TBP_NUM * CFG_MEM_IF_CS_WIDTH) - 1 : 0] tbp_shadow_chipsel;
wire [(CFG_CTL_SHADOW_TBP_NUM * CFG_MEM_IF_BA_WIDTH) - 1 : 0] tbp_shadow_bank;
wire [(CFG_CTL_SHADOW_TBP_NUM * CFG_MEM_IF_ROW_WIDTH) - 1 : 0] tbp_shadow_row;
wire [(CFG_CTL_TBP_NUM * CFG_INT_SIZE_WIDTH) - 1 : 0] tbp_size;
wire [(CFG_CTL_TBP_NUM * CFG_LOCAL_ID_WIDTH) - 1 : 0] tbp_localid;
wire [(CFG_CTL_TBP_NUM * CFG_DATA_ID_WIDTH) - 1 : 0] tbp_dataid;
wire [CFG_CTL_TBP_NUM - 1 : 0] tbp_ap;
wire [CFG_CTL_TBP_NUM - 1 : 0] tbp_burst_chop;
wire [(CFG_CTL_TBP_NUM * CFG_CTL_TBP_NUM) - 1 : 0] tbp_age;
wire [CFG_CTL_TBP_NUM - 1 : 0] tbp_priority;
wire [CFG_CTL_TBP_NUM - 1 : 0] tbp_rmw_correct;
wire [CFG_CTL_TBP_NUM - 1 : 0] tbp_rmw_partial;
wire [CFG_MEM_IF_CHIP - 1 : 0] tbp_bank_closed;
wire [CFG_MEM_IF_CHIP - 1 : 0] tbp_timer_ready;
wire [CFG_CTL_TBP_NUM - 1 : 0] tbp_load_index;
wire [CFG_CTL_TBP_NUM - 1 : 0] tbp_load;
wire data_rmw_fetch;
// alt_mem_ddrx_arbiter
wire [CFG_CTL_TBP_NUM - 1 : 0] row_grant;
wire [CFG_CTL_TBP_NUM - 1 : 0] col_grant;
wire [CFG_CTL_TBP_NUM - 1 : 0] act_grant;
wire [CFG_CTL_TBP_NUM - 1 : 0] pch_grant;
wire [CFG_CTL_TBP_NUM - 1 : 0] rd_grant;
wire [CFG_CTL_TBP_NUM - 1 : 0] wr_grant;
wire [log2(CFG_CTL_TBP_NUM) - 1 : 0] log2_row_grant;
wire [log2(CFG_CTL_TBP_NUM) - 1 : 0] log2_col_grant;
wire [log2(CFG_CTL_TBP_NUM) - 1 : 0] log2_act_grant;
wire [log2(CFG_CTL_TBP_NUM) - 1 : 0] log2_pch_grant;
wire [log2(CFG_CTL_TBP_NUM) - 1 : 0] log2_rd_grant;
wire [log2(CFG_CTL_TBP_NUM) - 1 : 0] log2_wr_grant;
wire or_row_grant;
wire or_col_grant;
wire [CFG_AFI_INTF_PHASE_NUM - 1 : 0] arb_do_write;
wire [CFG_AFI_INTF_PHASE_NUM - 1 : 0] arb_do_read;
wire [CFG_AFI_INTF_PHASE_NUM - 1 : 0] arb_do_burst_chop;
wire [CFG_AFI_INTF_PHASE_NUM - 1 : 0] arb_do_burst_terminate;
wire [CFG_AFI_INTF_PHASE_NUM - 1 : 0] arb_do_auto_precharge;
wire [CFG_AFI_INTF_PHASE_NUM - 1 : 0] arb_do_rmw_correct;
wire [CFG_AFI_INTF_PHASE_NUM - 1 : 0] arb_do_rmw_partial;
wire [CFG_AFI_INTF_PHASE_NUM - 1 : 0] arb_do_activate;
wire [CFG_AFI_INTF_PHASE_NUM - 1 : 0] arb_do_precharge;
wire [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] arb_do_precharge_all;
wire [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] arb_do_refresh;
wire [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] arb_do_self_refresh;
wire [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] arb_do_power_down;
wire [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] arb_do_deep_pdown;
wire [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] arb_do_zq_cal;
wire [CFG_AFI_INTF_PHASE_NUM - 1 : 0] arb_do_lmr;
wire [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CS_WIDTH) - 1 : 0] arb_to_chipsel;
wire [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] arb_to_chip;
wire [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_BA_WIDTH) - 1 : 0] arb_to_bank;
wire [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_ROW_WIDTH) - 1 : 0] arb_to_row;
wire [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_COL_WIDTH) - 1 : 0] arb_to_col;
wire [CFG_LOCAL_ID_WIDTH - 1 : 0] arb_localid;
wire [CFG_DATA_ID_WIDTH - 1 : 0] arb_dataid;
wire [CFG_INT_SIZE_WIDTH - 1 : 0] arb_size;
// alt_mem_ddrx_burst_gen
wire [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_write_combi;
wire [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_read_combi;
wire [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_burst_chop_combi;
wire [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_burst_terminate_combi;
wire [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_activate_combi;
wire [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_precharge_combi;
wire [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] bg_to_chip_combi;
wire [CFG_INT_SIZE_WIDTH - 1 : 0] bg_effective_size_combi;
wire bg_interrupt_ready_combi;
wire [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_write;
wire [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_read;
wire [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_burst_chop;
wire [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_burst_terminate;
wire [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_auto_precharge;
wire [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_rmw_correct;
wire [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_rmw_partial;
wire [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_activate;
wire [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_precharge;
wire [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] bg_do_precharge_all;
wire [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] bg_do_refresh;
wire [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] bg_do_self_refresh;
wire [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] bg_do_power_down;
wire [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] bg_do_deep_pdown;
wire [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] bg_do_zq_cal;
wire [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_lmr;
wire bg_do_lmr_read = 0;
wire bg_do_refresh_1bank = 0;
wire [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CS_WIDTH) - 1 : 0] bg_to_chipsel;
wire [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] bg_to_chip;
wire [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_BA_WIDTH) - 1 : 0] bg_to_bank;
wire [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_ROW_WIDTH) - 1 : 0] bg_to_row;
wire [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_COL_WIDTH) - 1 : 0] bg_to_col;
wire bg_doing_write;
wire bg_doing_read;
wire bg_rdwr_data_valid;
wire bg_interrupt_ready;
wire [CFG_LOCAL_ID_WIDTH - 1 : 0] bg_localid;
wire [CFG_DATA_ID_WIDTH - 1 : 0] bg_dataid;
wire [CFG_RDDATA_ID_WIDTH - 1 : 0] bg_rddataid;
wire [CFG_INT_SIZE_WIDTH - 1 : 0] bg_size;
wire [CFG_INT_SIZE_WIDTH - 1 : 0] bg_effective_size;
wire [ 2 : 0] bg_to_lmr = 0;
// alt_mem_ddrx_addr_cmd_wrap
wire [(CFG_MEM_IF_CKE_WIDTH * (CFG_DWIDTH_RATIO / 2)) - 1 : 0] afi_cke;
wire [(CFG_MEM_IF_CHIP * (CFG_DWIDTH_RATIO / 2)) - 1 : 0] afi_cs_n;
wire [(CFG_DWIDTH_RATIO / 2) - 1 : 0] afi_ras_n;
wire [(CFG_DWIDTH_RATIO / 2) - 1 : 0] afi_cas_n;
wire [(CFG_DWIDTH_RATIO / 2) - 1 : 0] afi_we_n;
wire [(CFG_MEM_IF_BA_WIDTH * (CFG_DWIDTH_RATIO / 2)) - 1 : 0] afi_ba;
wire [(CFG_AFI_IF_FR_ADDR_WIDTH*(CFG_DWIDTH_RATIO / 2))- 1 : 0] afi_addr;
wire [(CFG_DWIDTH_RATIO / 2) - 1 : 0] afi_rst_n;
wire [(CFG_MEM_IF_ODT_WIDTH * (CFG_DWIDTH_RATIO / 2)) - 1 : 0] afi_odt;
wire [CFG_AFI_IF_FR_ADDR_WIDTH - 1 : 0] lmr_opcode = 0;
// alt_mem_ddrx_rdwr_data_tmg
wire [CFG_MEM_IF_DQS_WIDTH * (CFG_DWIDTH_RATIO / 2) - 1 : 0] afi_rdata_en;
wire [CFG_MEM_IF_DQS_WIDTH * (CFG_DWIDTH_RATIO / 2) - 1 : 0] afi_rdata_en_full;
wire [CFG_PORT_WIDTH_OUTPUT_REGD - 1 : 0] cfg_output_regd_for_afi_output;
wire [CFG_DRAM_WLAT_GROUP - 1 : 0] ecc_wdata_fifo_read;
wire [CFG_DRAM_WLAT_GROUP * CFG_DATA_ID_WIDTH - 1 : 0] ecc_wdata_fifo_dataid;
wire [CFG_DRAM_WLAT_GROUP * CFG_DATAID_ARRAY_DEPTH - 1 : 0] ecc_wdata_fifo_dataid_vector;
wire [CFG_DRAM_WLAT_GROUP - 1 : 0] ecc_wdata_fifo_rmw_correct;
wire [CFG_DRAM_WLAT_GROUP - 1 : 0] ecc_wdata_fifo_rmw_partial;
wire ecc_wdata_fifo_read_first;
wire [CFG_DATA_ID_WIDTH - 1 : 0] ecc_wdata_fifo_dataid_first;
wire [CFG_DATAID_ARRAY_DEPTH - 1 : 0] ecc_wdata_fifo_dataid_vector_first;
wire ecc_wdata_fifo_rmw_correct_first;
wire ecc_wdata_fifo_rmw_partial_first;
wire [CFG_DRAM_WLAT_GROUP - 1 : 0] ecc_wdata_fifo_first_vector;
wire ecc_wdata_fifo_read_last;
wire [CFG_DATA_ID_WIDTH - 1 : 0] ecc_wdata_fifo_dataid_last;
wire [CFG_DATAID_ARRAY_DEPTH - 1 : 0] ecc_wdata_fifo_dataid_vector_last;
wire ecc_wdata_fifo_rmw_correct_last;
wire ecc_wdata_fifo_rmw_partial_last;
wire [CFG_DRAM_WLAT_GROUP * CFG_WRDATA_ID_WIDTH - 1 : 0] ecc_wdata_wrdataid;
wire [CFG_DRAM_WLAT_GROUP * CFG_WRDATA_ID_WIDTH_SQRD - 1 : 0] ecc_wdata_wrdataid_vector;
wire [CFG_WRDATA_ID_WIDTH - 1 : 0] ecc_wdata_wrdataid_first;
wire [CFG_WRDATA_ID_WIDTH_SQRD - 1 : 0] ecc_wdata_wrdataid_vector_first;
wire [CFG_WRDATA_ID_WIDTH - 1 : 0] ecc_wdata_wrdataid_last;
wire [CFG_WRDATA_ID_WIDTH_SQRD - 1 : 0] ecc_wdata_wrdataid_vector_last;
wire [CFG_MEM_IF_CHIP * (CFG_DWIDTH_RATIO / 2) * CFG_MEM_IF_DQS_WIDTH - 1 : 0] int_afi_rrank;
wire [CFG_MEM_IF_CHIP * (CFG_DWIDTH_RATIO / 2) * CFG_MEM_IF_DQS_WIDTH - 1 : 0] int_afi_wrank;
wire [CFG_MEM_IF_DQS_WIDTH * (CFG_DWIDTH_RATIO / 2) - 1 : 0] afi_dqs_burst;
wire [CFG_MEM_IF_DQS_WIDTH * (CFG_DWIDTH_RATIO / 2) - 1 : 0] afi_wdata_valid;
wire [CFG_MEM_IF_DQ_WIDTH * CFG_DWIDTH_RATIO - 1 : 0] afi_wdata;
wire [CFG_MEM_IF_DM_WIDTH * CFG_DWIDTH_RATIO - 1 : 0] afi_dm;
// alt_mem_ddrx_wdata_path
wire proc_busy;
wire proc_load;
wire proc_load_dataid;
wire proc_write;
wire proc_read;
wire [CFG_INT_SIZE_WIDTH-1:0] proc_size;
wire [CFG_LOCAL_ID_WIDTH-1:0] proc_localid;
wire wdatap_free_id_valid;
wire [CFG_DATA_ID_WIDTH - 1 : 0] wdatap_free_id_dataid;
wire [CFG_WRDATA_ID_WIDTH - 1 : 0] wdatap_free_id_wrdataid;
wire wr_data_mem_full;
wire [CFG_CTL_TBP_NUM - 1 : 0] data_complete;
wire data_rmw_complete;
wire data_partial_be;
wire [CFG_LOCAL_DATA_WIDTH - 1 : 0] wdatap_data;
wire [CFG_LOCAL_DATA_WIDTH - 1 : 0] wdatap_rmw_partial_data;
wire [CFG_LOCAL_DATA_WIDTH - 1 : 0] wdatap_rmw_correct_data;
wire wdatap_rmw_partial;
wire wdatap_rmw_correct;
wire [(CFG_LOCAL_DATA_WIDTH / CFG_MEM_IF_DQ_PER_DQS) - 1 : 0] wdatap_dm;
wire [CFG_ECC_MULTIPLES * CFG_ECC_CODE_WIDTH - 1 : 0] wdatap_ecc_code;
wire [CFG_ECC_MULTIPLES - 1 : 0] wdatap_ecc_code_overwrite;
// alt_mem_ddrx_rdata_path
wire rdatap_free_id_valid;
wire [CFG_DATA_ID_WIDTH - 1 : 0] rdatap_free_id_dataid;
wire [CFG_RDDATA_ID_WIDTH - 1 : 0] rdatap_free_id_rddataid;
wire read_data_valid;
wire [CFG_LOCAL_DATA_WIDTH - 1 : 0] read_data;
wire read_data_error;
wire [CFG_LOCAL_ID_WIDTH - 1 : 0] read_data_localid;
wire errcmd_ready;
wire errcmd_valid;
wire [CFG_MEM_IF_CS_WIDTH - 1 : 0] errcmd_chipsel;
wire [CFG_MEM_IF_BA_WIDTH - 1 : 0] errcmd_bank;
wire [CFG_MEM_IF_ROW_WIDTH - 1 : 0] errcmd_row;
wire [CFG_MEM_IF_COL_WIDTH - 1 : 0] errcmd_column;
wire [CFG_INT_SIZE_WIDTH - 1 : 0] errcmd_size;
wire [CFG_LOCAL_ID_WIDTH - 1 : 0] errcmd_localid;
wire [CFG_LOCAL_ADDR_WIDTH - 1 : 0] rdatap_rcvd_addr;
wire rdatap_rcvd_cmd;
wire rdatap_rcvd_corr_dropped;
wire rmwfifo_data_valid;
wire [CFG_LOCAL_DATA_WIDTH - 1 : 0] rmwfifo_data;
wire [CFG_ECC_MULTIPLES - 1 : 0] rmwfifo_ecc_dbe;
wire [CFG_ECC_MULTIPLES * CFG_ECC_CODE_WIDTH - 1 : 0] rmwfifo_ecc_code;
// alt_mem_ddrx_ecc_encoder_decoder_wrapper
wire [CFG_LOCAL_DATA_WIDTH - 1 : 0] ecc_rdata;
wire ecc_rdata_valid;
wire [CFG_ECC_DM_WIDTH - 1 : 0] ecc_dm;
wire [CFG_ECC_DATA_WIDTH - 1 : 0] ecc_wdata;
wire [CFG_ECC_MULTIPLES - 1 : 0] ecc_sbe;
wire [CFG_ECC_MULTIPLES - 1 : 0] ecc_dbe;
wire [CFG_ECC_MULTIPLES * CFG_ECC_CODE_WIDTH - 1 : 0] ecc_code;
wire ecc_interrupt;
wire [STS_PORT_WIDTH_SBE_ERROR - 1 : 0] sts_sbe_error;
wire [STS_PORT_WIDTH_DBE_ERROR - 1 : 0] sts_dbe_error;
wire [STS_PORT_WIDTH_SBE_COUNT - 1 : 0] sts_sbe_count;
wire [STS_PORT_WIDTH_DBE_COUNT - 1 : 0] sts_dbe_count;
wire [CFG_LOCAL_ADDR_WIDTH - 1 : 0] sts_err_addr;
wire [STS_PORT_WIDTH_CORR_DROP_ERROR - 1 : 0] sts_corr_dropped;
wire [STS_PORT_WIDTH_CORR_DROP_COUNT - 1 : 0] sts_corr_dropped_count;
wire [CFG_LOCAL_ADDR_WIDTH - 1 : 0] sts_corr_dropped_addr;
// alt_mem_ddrx_sideband
wire rfsh_ack;
wire self_rfsh_ack;
wire deep_powerdn_ack;
wire power_down_ack;
wire stall_row_arbiter;
wire stall_col_arbiter;
wire [CFG_MEM_IF_CHIP - 1 : 0] stall_chip;
wire [CFG_MEM_IF_CHIP - 1 : 0] sb_do_precharge_all;
wire [CFG_MEM_IF_CHIP - 1 : 0] sb_do_refresh;
wire [CFG_MEM_IF_CHIP - 1 : 0] sb_do_self_refresh;
wire [CFG_MEM_IF_CHIP - 1 : 0] sb_do_power_down;
wire [CFG_MEM_IF_CHIP - 1 : 0] sb_do_deep_pdown;
wire [CFG_MEM_IF_CHIP - 1 : 0] sb_do_zq_cal;
wire [CFG_CTL_TBP_NUM - 1 : 0] sb_tbp_precharge_all;
wire [CFG_MEM_IF_CLK_PAIR_COUNT - 1 : 0] ctl_sb_mem_clk_disable;
wire ctl_sb_cal_req;
wire ctl_sb_init_req;
wire [CFG_MEM_IF_CHIP - 1 : 0] afi_ctl_refresh_done;
wire [CFG_MEM_IF_CHIP - 1 : 0] afi_ctl_long_idle;
// alt_mem_ddrx_rank_timer
wire [CFG_CTL_TBP_NUM - 1 : 0] can_activate;
wire [CFG_CTL_TBP_NUM - 1 : 0] can_precharge;
wire [CFG_CTL_TBP_NUM - 1 : 0] can_read;
wire [CFG_CTL_TBP_NUM - 1 : 0] can_write;
// alt_mem_ddrx_timing_param
wire [T_PARAM_ACT_TO_RDWR_WIDTH - 1 : 0] t_param_act_to_rdwr;
wire [T_PARAM_ACT_TO_PCH_WIDTH - 1 : 0] t_param_act_to_pch;
wire [T_PARAM_ACT_TO_ACT_WIDTH - 1 : 0] t_param_act_to_act;
wire [T_PARAM_RD_TO_RD_WIDTH - 1 : 0] t_param_rd_to_rd;
wire [T_PARAM_RD_TO_RD_DIFF_CHIP_WIDTH - 1 : 0] t_param_rd_to_rd_diff_chip;
wire [T_PARAM_RD_TO_WR_WIDTH - 1 : 0] t_param_rd_to_wr;
wire [T_PARAM_RD_TO_WR_BC_WIDTH - 1 : 0] t_param_rd_to_wr_bc;
wire [T_PARAM_RD_TO_WR_DIFF_CHIP_WIDTH - 1 : 0] t_param_rd_to_wr_diff_chip;
wire [T_PARAM_RD_TO_PCH_WIDTH - 1 : 0] t_param_rd_to_pch;
wire [T_PARAM_RD_AP_TO_VALID_WIDTH - 1 : 0] t_param_rd_ap_to_valid;
wire [T_PARAM_WR_TO_WR_WIDTH - 1 : 0] t_param_wr_to_wr;
wire [T_PARAM_WR_TO_WR_DIFF_CHIP_WIDTH - 1 : 0] t_param_wr_to_wr_diff_chip;
wire [T_PARAM_WR_TO_RD_WIDTH - 1 : 0] t_param_wr_to_rd;
wire [T_PARAM_WR_TO_RD_BC_WIDTH - 1 : 0] t_param_wr_to_rd_bc;
wire [T_PARAM_WR_TO_RD_DIFF_CHIP_WIDTH - 1 : 0] t_param_wr_to_rd_diff_chip;
wire [T_PARAM_WR_TO_PCH_WIDTH - 1 : 0] t_param_wr_to_pch;
wire [T_PARAM_WR_AP_TO_VALID_WIDTH - 1 : 0] t_param_wr_ap_to_valid;
wire [T_PARAM_PCH_TO_VALID_WIDTH - 1 : 0] t_param_pch_to_valid;
wire [T_PARAM_PCH_ALL_TO_VALID_WIDTH - 1 : 0] t_param_pch_all_to_valid;
wire [T_PARAM_ACT_TO_ACT_DIFF_BANK_WIDTH - 1 : 0] t_param_act_to_act_diff_bank;
wire [T_PARAM_FOUR_ACT_TO_ACT_WIDTH - 1 : 0] t_param_four_act_to_act;
wire [T_PARAM_ARF_TO_VALID_WIDTH - 1 : 0] t_param_arf_to_valid;
wire [T_PARAM_PDN_TO_VALID_WIDTH - 1 : 0] t_param_pdn_to_valid;
wire [T_PARAM_SRF_TO_VALID_WIDTH - 1 : 0] t_param_srf_to_valid;
wire [T_PARAM_SRF_TO_ZQ_CAL_WIDTH - 1 : 0] t_param_srf_to_zq_cal;
wire [T_PARAM_ARF_PERIOD_WIDTH - 1 : 0] t_param_arf_period;
wire [T_PARAM_PDN_PERIOD_WIDTH - 1 : 0] t_param_pdn_period;
wire [T_PARAM_POWER_SAVING_EXIT_WIDTH - 1 : 0] t_param_power_saving_exit;
wire [T_PARAM_MEM_CLK_ENTRY_CYCLES_WIDTH - 1 : 0] t_param_mem_clk_entry_cycles;
// General
wire init_done = ctl_cal_success;
wire sts_cal_success = ctl_cal_success;
wire sts_cal_fail = ctl_cal_fail;
wire ctl_cal_req = cfg_cal_req | ctl_sb_cal_req;
wire ctl_init_req = ctl_sb_init_req;
wire [CFG_MEM_IF_CLK_PAIR_COUNT - 1 : 0] ctl_mem_clk_disable = ctl_sb_mem_clk_disable;
wire [CFG_MEM_IF_DQS_WIDTH*CFG_MEM_IF_CHIP - 1 : 0] ctl_cal_byte_lane_sel_n = 0;
wire [CFG_RRANK_BUS_WIDTH - 1 : 0] afi_rrank = CFG_USE_SHADOW_REGS ? int_afi_rrank[CFG_RRANK_BUS_WIDTH - 1:0] : {CFG_RRANK_BUS_WIDTH{1'b0}};
wire [CFG_WRANK_BUS_WIDTH - 1 : 0] afi_wrank = CFG_USE_SHADOW_REGS ? int_afi_wrank[CFG_WRANK_BUS_WIDTH - 1:0] : {CFG_RRANK_BUS_WIDTH{1'b0}};
// Log 2 function
function integer log2;
input [31:0] value;
integer i;
begin
log2 = 0;
for(i = 0; 2**i < value; i = i + 1)
log2 = i + 1;
end
endfunction
// register init_done signal
reg init_done_reg;
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
init_done_reg <= 0;
end
else
begin
init_done_reg <= init_done;
end
end
//==============================================================================
// alt_mem_ddrx_input_if
//------------------------------------------------------------------------------
//
// Input interface block
//
// Info: Includes cmd channel, and both read and write channels
// * Optional half-rate bridge logic
//
//==============================================================================
alt_mem_ddrx_input_if #
(
.CFG_LOCAL_DATA_WIDTH (CFG_LOCAL_DATA_WIDTH ),
.CFG_LOCAL_ID_WIDTH (CFG_LOCAL_ID_WIDTH ),
.CFG_LOCAL_ADDR_WIDTH (CFG_LOCAL_ADDR_WIDTH ),
.CFG_LOCAL_SIZE_WIDTH (CFG_LOCAL_SIZE_WIDTH ),
.CFG_MEM_IF_CHIP (CFG_MEM_IF_CHIP ),
.CFG_AFI_INTF_PHASE_NUM (CFG_AFI_INTF_PHASE_NUM ),
.CFG_CTL_ARBITER_TYPE (CFG_CTL_ARBITER_TYPE )
)
input_if_inst
(
.itf_cmd_ready (itf_cmd_ready ),
.itf_cmd_valid (itf_cmd_valid ),
.itf_cmd (itf_cmd ),
.itf_cmd_address (itf_cmd_address ),
.itf_cmd_burstlen (itf_cmd_burstlen ),
.itf_cmd_id (itf_cmd_id ),
.itf_cmd_priority (itf_cmd_priority ),
.itf_cmd_autopercharge (itf_cmd_autopercharge ),
.itf_cmd_multicast (itf_cmd_multicast ),
.itf_wr_data_ready (itf_wr_data_ready ),
.itf_wr_data_valid (itf_wr_data_valid ),
.itf_wr_data (itf_wr_data ),
.itf_wr_data_byte_en (itf_wr_data_byte_en ),
.itf_wr_data_begin (itf_wr_data_begin ),
.itf_wr_data_last (itf_wr_data_last ),
.itf_wr_data_id (itf_wr_data_id ),
.itf_rd_data_ready (itf_rd_data_ready ),
.itf_rd_data_valid (itf_rd_data_valid ),
.itf_rd_data (itf_rd_data ),
.itf_rd_data_error (itf_rd_data_error ),
.itf_rd_data_begin (itf_rd_data_begin ),
.itf_rd_data_last (itf_rd_data_last ),
.itf_rd_data_id (itf_rd_data_id ),
.itf_rd_data_id_early (itf_rd_data_id_early ),
.itf_rd_data_id_early_valid(itf_rd_data_id_early_valid ),
.cmd_gen_full (cmd_gen_full ),
.cmd_valid (cmd_valid ),
.cmd_address (cmd_address ),
.cmd_write (cmd_write ),
.cmd_read (cmd_read ),
.cmd_multicast (cmd_multicast ),
.cmd_size (cmd_size ),
.cmd_priority (cmd_priority ),
.cmd_autoprecharge (cmd_autoprecharge ),
.cmd_id (cmd_id ),
.write_data (write_data ),
.wr_data_mem_full (wr_data_mem_full ),
.write_data_id (write_data_id ),
.byte_en (byte_en ),
.write_data_valid (write_data_valid ),
.read_data (read_data ),
.read_data_valid (read_data_valid ),
.read_data_error (read_data_error ),
.read_data_localid (read_data_localid ),
.read_data_begin ( ), // NOTICE: not connected?
.read_data_last ( ), // NOTICE: not connected?
.bg_do_read (bg_do_read ),
.bg_localid (bg_localid ),
.bg_do_rmw_correct (bg_do_rmw_correct ),
.bg_do_rmw_partial (bg_do_rmw_partial ),
.local_refresh_req (local_refresh_req ),
.local_refresh_chip (local_refresh_chip ),
.local_zqcal_req (local_zqcal_req ),
// .local_zqcal_chip (local_zqcal_chip ),
.local_deep_powerdn_req (local_deep_powerdn_req ),
.local_deep_powerdn_chip (local_deep_powerdn_chip ),
.local_self_rfsh_req (local_self_rfsh_req ),
.local_self_rfsh_chip (local_self_rfsh_chip ),
.local_refresh_ack (local_refresh_ack ),
.local_deep_powerdn_ack (local_deep_powerdn_ack ),
.local_power_down_ack (local_power_down_ack ),
.local_self_rfsh_ack (local_self_rfsh_ack ),
.local_init_done (local_init_done ),
.rfsh_req (rfsh_req ),
.rfsh_chip (rfsh_chip ),
.zqcal_req (zqcal_req ),
.deep_powerdn_req (deep_powerdn_req ),
.deep_powerdn_chip (deep_powerdn_chip ),
.self_rfsh_req (self_rfsh_req ),
.self_rfsh_chip (self_rfsh_chip ),
.rfsh_ack (rfsh_ack ),
.deep_powerdn_ack (deep_powerdn_ack ),
.power_down_ack (power_down_ack ),
.self_rfsh_ack (self_rfsh_ack ),
.init_done (init_done_reg )
);
//==============================================================================
// alt_mem_ddrx_cmd_gen
//------------------------------------------------------------------------------
//
// Command generator block
//
// Info: * generates cmd from local and internal ECC block
// * splitting and merging of all commands
// * optional queue for latency reduction purpose when no merging is required
//
//==============================================================================
alt_mem_ddrx_cmd_gen #
(
.CFG_LOCAL_ADDR_WIDTH (CFG_LOCAL_ADDR_WIDTH ),
.CFG_LOCAL_SIZE_WIDTH (CFG_LOCAL_SIZE_WIDTH ),
.CFG_LOCAL_ID_WIDTH (CFG_LOCAL_ID_WIDTH ),
.CFG_INT_SIZE_WIDTH (CFG_INT_SIZE_WIDTH ),
.CFG_PORT_WIDTH_COL_ADDR_WIDTH (CFG_PORT_WIDTH_COL_ADDR_WIDTH ),
.CFG_PORT_WIDTH_ROW_ADDR_WIDTH (CFG_PORT_WIDTH_ROW_ADDR_WIDTH ),
.CFG_PORT_WIDTH_BANK_ADDR_WIDTH (CFG_PORT_WIDTH_BANK_ADDR_WIDTH ),
.CFG_PORT_WIDTH_CS_ADDR_WIDTH (CFG_PORT_WIDTH_CS_ADDR_WIDTH ),
.CFG_PORT_WIDTH_BURST_LENGTH (CFG_PORT_WIDTH_BURST_LENGTH ),
.CFG_PORT_WIDTH_ADDR_ORDER (CFG_PORT_WIDTH_ADDR_ORDER ),
.CFG_DWIDTH_RATIO (CFG_DWIDTH_RATIO ),
.CFG_CTL_QUEUE_DEPTH (CFG_CTL_QUEUE_DEPTH ),
.CFG_MEM_IF_CHIP (CFG_MEM_IF_CHIP ),
.CFG_MEM_IF_CS_WIDTH (CFG_MEM_IF_CS_WIDTH ),
.CFG_MEM_IF_BA_WIDTH (CFG_MEM_IF_BA_WIDTH ),
.CFG_MEM_IF_ROW_WIDTH (CFG_MEM_IF_ROW_WIDTH ),
.CFG_MEM_IF_COL_WIDTH (CFG_MEM_IF_COL_WIDTH ),
.CFG_DATA_ID_WIDTH (CFG_DATA_ID_WIDTH ),
.CFG_ENABLE_QUEUE (CFG_ENABLE_QUEUE ),
.CFG_ENABLE_BURST_MERGE (CFG_ENABLE_BURST_MERGE ),
.CFG_CMD_GEN_OUTPUT_REG (CFG_CMD_GEN_OUTPUT_REG ),
.CFG_CTL_TBP_NUM (CFG_CTL_TBP_NUM ),
.CFG_CTL_SHADOW_TBP_NUM (CFG_CTL_SHADOW_TBP_NUM )
)
cmd_gen_inst
(
.ctl_clk (ctl_clk ),
.ctl_reset_n (ctl_reset_n ),
.tbp_full (tbp_full ),
.tbp_load (tbp_load ),
.tbp_read (tbp_read ),
.tbp_write (tbp_write ),
.tbp_chipsel (tbp_chipsel ),
.tbp_bank (tbp_bank ),
.tbp_row (tbp_row ),
.tbp_col (tbp_col ),
.tbp_shadow_chipsel (tbp_shadow_chipsel ),
.tbp_shadow_bank (tbp_shadow_bank ),
.tbp_shadow_row (tbp_shadow_row ),
.cmd_gen_load (cmd_gen_load ),
.cmd_gen_waiting_to_load (cmd_gen_waiting_to_load ),
.cmd_gen_chipsel (cmd_gen_chipsel ),
.cmd_gen_bank (cmd_gen_bank ),
.cmd_gen_row (cmd_gen_row ),
.cmd_gen_col (cmd_gen_col ),
.cmd_gen_write (cmd_gen_write ),
.cmd_gen_read (cmd_gen_read ),
.cmd_gen_multicast (cmd_gen_multicast ),
.cmd_gen_size (cmd_gen_size ),
.cmd_gen_localid (cmd_gen_localid ),
.cmd_gen_dataid (cmd_gen_dataid ),
.cmd_gen_priority (cmd_gen_priority ),
.cmd_gen_rmw_correct (cmd_gen_rmw_correct ),
.cmd_gen_rmw_partial (cmd_gen_rmw_partial ),
.cmd_gen_autopch (cmd_gen_autopch ),
.cmd_gen_complete (cmd_gen_complete ),
.cmd_gen_same_chipsel_addr (cmd_gen_same_chipsel_addr ),
.cmd_gen_same_bank_addr (cmd_gen_same_bank_addr ),
.cmd_gen_same_row_addr (cmd_gen_same_row_addr ),
.cmd_gen_same_col_addr (cmd_gen_same_col_addr ),
.cmd_gen_same_read_cmd (cmd_gen_same_read_cmd ),
.cmd_gen_same_write_cmd (cmd_gen_same_write_cmd ),
.cmd_gen_same_shadow_chipsel_addr (cmd_gen_same_shadow_chipsel_addr ),
.cmd_gen_same_shadow_bank_addr (cmd_gen_same_shadow_bank_addr ),
.cmd_gen_same_shadow_row_addr (cmd_gen_same_shadow_row_addr ),
.cmd_gen_busy (cmd_gen_busy ),
.cmd_gen_full (cmd_gen_full ),
.cmd_valid (cmd_valid ),
.cmd_address (cmd_address ),
.cmd_write (cmd_write ),
.cmd_read (cmd_read ),
.cmd_id (cmd_id ),
.cmd_multicast (cmd_multicast ),
.cmd_size (cmd_size ),
.cmd_priority (cmd_priority ),
.cmd_autoprecharge (cmd_autoprecharge ),
.proc_busy (proc_busy ),
.proc_load (proc_load ),
.proc_load_dataid (proc_load_dataid ),
.proc_write (proc_write ),
.proc_read (proc_read ),
.proc_size (proc_size ),
.proc_localid (proc_localid ),
.wdatap_free_id_valid (wdatap_free_id_valid ),
.wdatap_free_id_dataid (wdatap_free_id_dataid ),
.rdatap_free_id_valid (rdatap_free_id_valid ),
.rdatap_free_id_dataid (rdatap_free_id_dataid ),
.tbp_load_index (tbp_load_index ),
.data_complete (data_complete ),
.data_rmw_complete (data_rmw_complete ),
.errcmd_ready (errcmd_ready ),
.errcmd_valid (errcmd_valid ),
.errcmd_chipsel (errcmd_chipsel ),
.errcmd_bank (errcmd_bank ),
.errcmd_row (errcmd_row ),
.errcmd_column (errcmd_column ),
.errcmd_size (errcmd_size ),
.errcmd_localid (errcmd_localid ),
.data_partial_be (data_partial_be ),
.cfg_enable_cmd_split (CFG_ENABLE_CMD_SPLIT ),
.cfg_burst_length (cfg_burst_length ),
.cfg_addr_order (cfg_addr_order ),
.cfg_enable_ecc (cfg_enable_ecc ),
.cfg_enable_no_dm (cfg_enable_no_dm ),
.cfg_col_addr_width (cfg_col_addr_width ),
.cfg_row_addr_width (cfg_row_addr_width ),
.cfg_bank_addr_width (cfg_bank_addr_width ),
.cfg_cs_addr_width (cfg_cs_addr_width )
);
//==============================================================================
// alt_mem_ddrx_tbp
//------------------------------------------------------------------------------
//
// Timing bank pool block
//
// Info: * parallel queue in which a cmd is present
// * tracks timer and bank status information of the command it hold
// * monitor other TBPs content to update status bit in itself such
// as the autoprecharge bit
// * pass timer value to another TBP if need arises
//
//==============================================================================
alt_mem_ddrx_tbp #
(
.CFG_CTL_TBP_NUM (CFG_CTL_TBP_NUM ),
.CFG_CTL_SHADOW_TBP_NUM (CFG_CTL_SHADOW_TBP_NUM ),
.CFG_ENABLE_SHADOW_TBP (CFG_ENABLE_SHADOW_TBP ),
.CFG_DWIDTH_RATIO (CFG_DWIDTH_RATIO ),
.CFG_CTL_ARBITER_TYPE (CFG_CTL_ARBITER_TYPE ),
.CFG_MEM_IF_CHIP (CFG_MEM_IF_CHIP ),
.CFG_MEM_IF_CS_WIDTH (CFG_MEM_IF_CS_WIDTH ),
.CFG_MEM_IF_BA_WIDTH (CFG_MEM_IF_BA_WIDTH ),
.CFG_MEM_IF_ROW_WIDTH (CFG_MEM_IF_ROW_WIDTH ),
.CFG_MEM_IF_COL_WIDTH (CFG_MEM_IF_COL_WIDTH ),
.CFG_LOCAL_ID_WIDTH (CFG_LOCAL_ID_WIDTH ),
.CFG_INT_SIZE_WIDTH (CFG_INT_SIZE_WIDTH ),
.CFG_DATA_ID_WIDTH (CFG_DATA_ID_WIDTH ),
.CFG_PORT_WIDTH_STARVE_LIMIT (CFG_PORT_WIDTH_STARVE_LIMIT ),
.CFG_PORT_WIDTH_TYPE (CFG_PORT_WIDTH_TYPE ),
.CFG_PORT_WIDTH_REORDER_DATA (CFG_PORT_WIDTH_REORDER_DATA ),
.CFG_REG_REQ (CFG_REG_REQ ),
.CFG_REG_GRANT (CFG_REG_GRANT ),
.CFG_DATA_REORDERING_TYPE (CFG_DATA_REORDERING_TYPE ),
.CFG_DISABLE_READ_REODERING (CFG_DISABLE_READ_REODERING ),
.CFG_DISABLE_PRIORITY (CFG_DISABLE_PRIORITY ),
.T_PARAM_ACT_TO_RDWR_WIDTH (T_PARAM_ACT_TO_RDWR_WIDTH ),
.T_PARAM_ACT_TO_ACT_WIDTH (T_PARAM_ACT_TO_ACT_WIDTH ),
.T_PARAM_ACT_TO_PCH_WIDTH (T_PARAM_ACT_TO_PCH_WIDTH ),
.T_PARAM_RD_TO_PCH_WIDTH (T_PARAM_RD_TO_PCH_WIDTH ),
.T_PARAM_WR_TO_PCH_WIDTH (T_PARAM_WR_TO_PCH_WIDTH ),
.T_PARAM_PCH_TO_VALID_WIDTH (T_PARAM_PCH_TO_VALID_WIDTH ),
.T_PARAM_RD_AP_TO_VALID_WIDTH (T_PARAM_RD_AP_TO_VALID_WIDTH ),
.T_PARAM_WR_AP_TO_VALID_WIDTH (T_PARAM_WR_AP_TO_VALID_WIDTH )
)
tbp_inst
(
.ctl_clk (ctl_clk ),
.ctl_reset_n (ctl_reset_n ),
.tbp_full (tbp_full ),
.tbp_empty (tbp_empty ),
.cmd_gen_load (cmd_gen_load ),
.cmd_gen_waiting_to_load (cmd_gen_waiting_to_load ),
.cmd_gen_chipsel (cmd_gen_chipsel ),
.cmd_gen_bank (cmd_gen_bank ),
.cmd_gen_row (cmd_gen_row ),
.cmd_gen_col (cmd_gen_col ),
.cmd_gen_write (cmd_gen_write ),
.cmd_gen_read (cmd_gen_read ),
.cmd_gen_size (cmd_gen_size ),
.cmd_gen_localid (cmd_gen_localid ),
.cmd_gen_dataid (cmd_gen_dataid ),
.cmd_gen_priority (cmd_gen_priority ),
.cmd_gen_rmw_correct (cmd_gen_rmw_correct ),
.cmd_gen_rmw_partial (cmd_gen_rmw_partial ),
.cmd_gen_autopch (cmd_gen_autopch ),
.cmd_gen_complete (cmd_gen_complete ),
.cmd_gen_same_chipsel_addr (cmd_gen_same_chipsel_addr ),
.cmd_gen_same_bank_addr (cmd_gen_same_bank_addr ),
.cmd_gen_same_row_addr (cmd_gen_same_row_addr ),
.cmd_gen_same_col_addr (cmd_gen_same_col_addr ),
.cmd_gen_same_read_cmd (cmd_gen_same_read_cmd ),
.cmd_gen_same_write_cmd (cmd_gen_same_write_cmd ),
.cmd_gen_same_shadow_chipsel_addr (cmd_gen_same_shadow_chipsel_addr ),
.cmd_gen_same_shadow_bank_addr (cmd_gen_same_shadow_bank_addr ),
.cmd_gen_same_shadow_row_addr (cmd_gen_same_shadow_row_addr ),
.row_req (row_req ),
.act_req (act_req ),
.pch_req (pch_req ),
.col_req (col_req ),
.rd_req (rd_req ),
.wr_req (wr_req ),
.row_grant (row_grant ),
.col_grant (col_grant ),
.act_grant (act_grant ),
.pch_grant (pch_grant ),
.rd_grant (rd_grant ),
.wr_grant (wr_grant ),
.log2_row_grant (log2_row_grant ),
.log2_col_grant (log2_col_grant ),
.log2_act_grant (log2_act_grant ),
.log2_pch_grant (log2_pch_grant ),
.log2_rd_grant (log2_rd_grant ),
.log2_wr_grant (log2_wr_grant ),
.or_row_grant (or_row_grant ),
.or_col_grant (or_col_grant ),
.tbp_read (tbp_read ),
.tbp_write (tbp_write ),
.tbp_precharge (tbp_precharge ),
.tbp_activate (tbp_activate ),
.tbp_chipsel (tbp_chipsel ),
.tbp_bank (tbp_bank ),
.tbp_row (tbp_row ),
.tbp_col (tbp_col ),
.tbp_shadow_chipsel (tbp_shadow_chipsel ),
.tbp_shadow_bank (tbp_shadow_bank ),
.tbp_shadow_row (tbp_shadow_row ),
.tbp_size (tbp_size ),
.tbp_localid (tbp_localid ),
.tbp_dataid (tbp_dataid ),
.tbp_ap (tbp_ap ),
.tbp_burst_chop (tbp_burst_chop ),
.tbp_age (tbp_age ),
.tbp_priority (tbp_priority ),
.tbp_rmw_correct (tbp_rmw_correct ),
.tbp_rmw_partial (tbp_rmw_partial ),
.sb_tbp_precharge_all (sb_tbp_precharge_all ),
.sb_do_precharge_all (sb_do_precharge_all ),
.t_param_act_to_rdwr (t_param_act_to_rdwr ),
.t_param_act_to_act (t_param_act_to_act ),
.t_param_act_to_pch (t_param_act_to_pch ),
.t_param_rd_to_pch (t_param_rd_to_pch ),
.t_param_wr_to_pch (t_param_wr_to_pch ),
.t_param_pch_to_valid (t_param_pch_to_valid ),
.t_param_rd_ap_to_valid (t_param_rd_ap_to_valid ),
.t_param_wr_ap_to_valid (t_param_wr_ap_to_valid ),
.tbp_bank_closed (tbp_bank_closed ),
.tbp_timer_ready (tbp_timer_ready ),
.cfg_reorder_data (cfg_reorder_data ),
.tbp_load (tbp_load ),
.data_complete (data_complete ),
.data_rmw_complete (data_rmw_complete ),
.data_rmw_fetch (data_rmw_fetch ),
.cfg_starve_limit (cfg_starve_limit ),
.cfg_type (cfg_type ),
.cfg_enable_ecc (cfg_enable_ecc ),
.cfg_enable_no_dm (cfg_enable_no_dm )
);
//==============================================================================
// alt_mem_ddrx_arbiter
//------------------------------------------------------------------------------
//
// Arbiter block
//
// Info: Priority command-aging arbiter, it will grant command with priority
// first, during tie-break situation, oldest command will be granted.
// Read comment in arbiter code for more information
//
//==============================================================================
alt_mem_ddrx_arbiter #
(
.CFG_DWIDTH_RATIO (CFG_DWIDTH_RATIO ),
.CFG_CTL_TBP_NUM (CFG_CTL_TBP_NUM ),
.CFG_CTL_ARBITER_TYPE (CFG_CTL_ARBITER_TYPE ),
.CFG_REG_GRANT (CFG_REG_GRANT ),
.CFG_REG_REQ (CFG_REG_REQ ),
.CFG_MEM_IF_CHIP (CFG_MEM_IF_CHIP ),
.CFG_MEM_IF_CS_WIDTH (CFG_MEM_IF_CS_WIDTH ),
.CFG_MEM_IF_BA_WIDTH (CFG_MEM_IF_BA_WIDTH ),
.CFG_MEM_IF_ROW_WIDTH (CFG_MEM_IF_ROW_WIDTH ),
.CFG_MEM_IF_COL_WIDTH (CFG_MEM_IF_COL_WIDTH ),
.CFG_LOCAL_ID_WIDTH (CFG_LOCAL_ID_WIDTH ),
.CFG_DATA_ID_WIDTH (CFG_DATA_ID_WIDTH ),
.CFG_INT_SIZE_WIDTH (CFG_INT_SIZE_WIDTH ),
.CFG_AFI_INTF_PHASE_NUM (CFG_AFI_INTF_PHASE_NUM ),
.CFG_DISABLE_PRIORITY (CFG_DISABLE_PRIORITY )
)
arbiter_inst
(
.ctl_clk (ctl_clk ),
.ctl_reset_n (ctl_reset_n ),
.stall_row_arbiter (stall_row_arbiter ),
.stall_col_arbiter (stall_col_arbiter ),
.sb_do_precharge_all (sb_do_precharge_all ),
.sb_do_refresh (sb_do_refresh ),
.sb_do_self_refresh (sb_do_self_refresh ),
.sb_do_power_down (sb_do_power_down ),
.sb_do_deep_pdown (sb_do_deep_pdown ),
.sb_do_zq_cal (sb_do_zq_cal ),
.row_req (row_req ),
.col_req (col_req ),
.act_req (act_req ),
.pch_req (pch_req ),
.rd_req (rd_req ),
.wr_req (wr_req ),
.row_grant (row_grant ),
.col_grant (col_grant ),
.act_grant (act_grant ),
.pch_grant (pch_grant ),
.rd_grant (rd_grant ),
.wr_grant (wr_grant ),
.log2_row_grant (log2_row_grant ),
.log2_col_grant (log2_col_grant ),
.log2_act_grant (log2_act_grant ),
.log2_pch_grant (log2_pch_grant ),
.log2_rd_grant (log2_rd_grant ),
.log2_wr_grant (log2_wr_grant ),
.or_row_grant (or_row_grant ),
.or_col_grant (or_col_grant ),
.tbp_activate (tbp_activate ),
.tbp_precharge (tbp_precharge ),
.tbp_read (tbp_read ),
.tbp_write (tbp_write ),
.tbp_chipsel (tbp_chipsel ),
.tbp_bank (tbp_bank ),
.tbp_row (tbp_row ),
.tbp_col (tbp_col ),
.tbp_size (tbp_size ),
.tbp_localid (tbp_localid ),
.tbp_dataid (tbp_dataid ),
.tbp_ap (tbp_ap ),
.tbp_burst_chop (tbp_burst_chop ),
.tbp_rmw_correct (tbp_rmw_correct ),
.tbp_rmw_partial (tbp_rmw_partial ),
.tbp_age (tbp_age ),
.tbp_priority (tbp_priority ),
.can_activate (can_activate ),
.can_precharge (can_precharge ),
.can_write (can_write ),
.can_read (can_read ),
.arb_do_write (arb_do_write ),
.arb_do_read (arb_do_read ),
.arb_do_burst_chop (arb_do_burst_chop ),
.arb_do_burst_terminate (arb_do_burst_terminate ),
.arb_do_auto_precharge (arb_do_auto_precharge ),
.arb_do_rmw_correct (arb_do_rmw_correct ),
.arb_do_rmw_partial (arb_do_rmw_partial ),
.arb_do_activate (arb_do_activate ),
.arb_do_precharge (arb_do_precharge ),
.arb_do_precharge_all (arb_do_precharge_all ),
.arb_do_refresh (arb_do_refresh ),
.arb_do_self_refresh (arb_do_self_refresh ),
.arb_do_power_down (arb_do_power_down ),
.arb_do_deep_pdown (arb_do_deep_pdown ),
.arb_do_zq_cal (arb_do_zq_cal ),
.arb_do_lmr (arb_do_lmr ),
.arb_to_chipsel (arb_to_chipsel ),
.arb_to_chip (arb_to_chip ),
.arb_to_bank (arb_to_bank ),
.arb_to_row (arb_to_row ),
.arb_to_col (arb_to_col ),
.arb_localid (arb_localid ),
.arb_dataid (arb_dataid ),
.arb_size (arb_size )
);
//==============================================================================
// alt_mem_ddrx_burst_gen
//------------------------------------------------------------------------------
//
// Burst generation block
//
// Info: Create DQ/DQS burst information for AFI block
//
//==============================================================================
alt_mem_ddrx_burst_gen #
(
.CFG_DWIDTH_RATIO (CFG_DWIDTH_RATIO ),
.CFG_CTL_ARBITER_TYPE (CFG_CTL_ARBITER_TYPE ),
.CFG_REG_GRANT (CFG_REG_GRANT ),
.CFG_MEM_IF_CHIP (CFG_MEM_IF_CHIP ),
.CFG_MEM_IF_CS_WIDTH (CFG_MEM_IF_CS_WIDTH ),
.CFG_MEM_IF_BA_WIDTH (CFG_MEM_IF_BA_WIDTH ),
.CFG_MEM_IF_ROW_WIDTH (CFG_MEM_IF_ROW_WIDTH ),
.CFG_MEM_IF_COL_WIDTH (CFG_MEM_IF_COL_WIDTH ),
.CFG_LOCAL_ID_WIDTH (CFG_LOCAL_ID_WIDTH ),
.CFG_DATA_ID_WIDTH (CFG_DATA_ID_WIDTH ),
.CFG_INT_SIZE_WIDTH (CFG_INT_SIZE_WIDTH ),
.CFG_AFI_INTF_PHASE_NUM (CFG_AFI_INTF_PHASE_NUM ),
.CFG_PORT_WIDTH_TYPE (CFG_PORT_WIDTH_TYPE ),
.CFG_PORT_WIDTH_BURST_LENGTH (CFG_PORT_WIDTH_BURST_LENGTH ),
.CFG_PORT_WIDTH_TCCD (CFG_PORT_WIDTH_TCCD ),
.CFG_PORT_WIDTH_ENABLE_BURST_INTERRUPT (CFG_PORT_WIDTH_ENABLE_BURST_INTERRUPT ),
.CFG_PORT_WIDTH_ENABLE_BURST_TERMINATE (CFG_PORT_WIDTH_ENABLE_BURST_TERMINATE ),
.CFG_ENABLE_BURST_GEN_OUTPUT_REG (CFG_ENABLE_BURST_GEN_OUTPUT_REG )
)
burst_gen_inst
(
.ctl_clk (ctl_clk ),
.ctl_reset_n (ctl_reset_n ),
.cfg_type (cfg_type ),
.cfg_burst_length (cfg_burst_length ),
.cfg_tccd (cfg_tccd ),
.cfg_enable_burst_interrupt (cfg_enable_burst_interrupt ),
.cfg_enable_burst_terminate (cfg_enable_burst_terminate ),
.arb_do_write (arb_do_write ),
.arb_do_read (arb_do_read ),
.arb_do_burst_chop (arb_do_burst_chop ),
.arb_do_burst_terminate (arb_do_burst_terminate ),
.arb_do_auto_precharge (arb_do_auto_precharge ),
.arb_do_rmw_correct (arb_do_rmw_correct ),
.arb_do_rmw_partial (arb_do_rmw_partial ),
.arb_do_activate (arb_do_activate ),
.arb_do_precharge (arb_do_precharge ),
.arb_do_precharge_all (arb_do_precharge_all ),
.arb_do_refresh (arb_do_refresh ),
.arb_do_self_refresh (arb_do_self_refresh ),
.arb_do_power_down (arb_do_power_down ),
.arb_do_deep_pdown (arb_do_deep_pdown ),
.arb_do_zq_cal (arb_do_zq_cal ),
.arb_do_lmr (arb_do_lmr ),
.arb_to_chipsel (arb_to_chipsel ),
.arb_to_chip (arb_to_chip ),
.arb_to_bank (arb_to_bank ),
.arb_to_row (arb_to_row ),
.arb_to_col (arb_to_col ),
.arb_localid (arb_localid ),
.arb_dataid (arb_dataid ),
.arb_size (arb_size ),
.bg_do_write_combi (bg_do_write_combi ),
.bg_do_read_combi (bg_do_read_combi ),
.bg_do_burst_chop_combi (bg_do_burst_chop_combi ),
.bg_do_burst_terminate_combi (bg_do_burst_terminate_combi ),
.bg_do_activate_combi (bg_do_activate_combi ),
.bg_do_precharge_combi (bg_do_precharge_combi ),
.bg_to_chip_combi (bg_to_chip_combi ),
.bg_effective_size_combi (bg_effective_size_combi ),
.bg_interrupt_ready_combi (bg_interrupt_ready_combi ),
.bg_do_write (bg_do_write ),
.bg_do_read (bg_do_read ),
.bg_do_burst_chop (bg_do_burst_chop ),
.bg_do_burst_terminate (bg_do_burst_terminate ),
.bg_do_auto_precharge (bg_do_auto_precharge ),
.bg_do_rmw_correct (bg_do_rmw_correct ),
.bg_do_rmw_partial (bg_do_rmw_partial ),
.bg_do_activate (bg_do_activate ),
.bg_do_precharge (bg_do_precharge ),
.bg_do_precharge_all (bg_do_precharge_all ),
.bg_do_refresh (bg_do_refresh ),
.bg_do_self_refresh (bg_do_self_refresh ),
.bg_do_power_down (bg_do_power_down ),
.bg_do_deep_pdown (bg_do_deep_pdown ),
.bg_do_zq_cal (bg_do_zq_cal ),
.bg_do_lmr (bg_do_lmr ),
.bg_to_chipsel (bg_to_chipsel ),
.bg_to_chip (bg_to_chip ),
.bg_to_bank (bg_to_bank ),
.bg_to_row (bg_to_row ),
.bg_to_col (bg_to_col ),
.bg_doing_write (bg_doing_write ),
.bg_doing_read (bg_doing_read ),
.bg_rdwr_data_valid (bg_rdwr_data_valid ),
.bg_interrupt_ready (bg_interrupt_ready ),
.bg_localid (bg_localid ),
.bg_dataid (bg_dataid ),
.bg_size (bg_size ),
.bg_effective_size (bg_effective_size )
);
//==============================================================================
// alt_mem_ddrx_addr_cmd_wrap
//------------------------------------------------------------------------------
//
// Address and command decoder block
//
// Info: Trasalate controller internal command into AFI command
//
//==============================================================================
// wire [CFG_MEM_IF_CHIP - 1 : 0] temp_to_chip = bg_to_chip [CFG_MEM_IF_CHIP - 1 : 0] | bg_to_chip [2 * CFG_MEM_IF_CHIP - 1 : CFG_MEM_IF_CHIP ];
// wire [CFG_MEM_IF_BA_WIDTH - 1 : 0] temp_to_bank = bg_to_bank [CFG_MEM_IF_BA_WIDTH - 1 : 0] | bg_to_bank [2 * CFG_MEM_IF_BA_WIDTH - 1 : CFG_MEM_IF_BA_WIDTH ];
// wire [CFG_MEM_IF_ROW_WIDTH - 1 : 0] temp_to_row = bg_to_row [CFG_MEM_IF_ROW_WIDTH - 1 : 0] | bg_to_row [2 * CFG_MEM_IF_ROW_WIDTH - 1 : CFG_MEM_IF_ROW_WIDTH];
// wire [CFG_MEM_IF_COL_WIDTH - 1 : 0] temp_to_col = bg_to_col [CFG_MEM_IF_COL_WIDTH - 1 : 0] | bg_to_col [2 * CFG_MEM_IF_COL_WIDTH - 1 : CFG_MEM_IF_COL_WIDTH];
//
// wire [CFG_MEM_IF_CHIP - 1 : 0] temp_do_refresh = bg_do_refresh [CFG_MEM_IF_CHIP - 1 : 0] | bg_do_refresh [2 * CFG_MEM_IF_CHIP - 1 : CFG_MEM_IF_CHIP];
// wire [CFG_MEM_IF_CHIP - 1 : 0] temp_do_power_down = bg_do_power_down [CFG_MEM_IF_CHIP - 1 : 0] | bg_do_power_down [2 * CFG_MEM_IF_CHIP - 1 : CFG_MEM_IF_CHIP];
// wire [CFG_MEM_IF_CHIP - 1 : 0] temp_do_self_refresh = bg_do_self_refresh [CFG_MEM_IF_CHIP - 1 : 0] | bg_do_self_refresh [2 * CFG_MEM_IF_CHIP - 1 : CFG_MEM_IF_CHIP];
// wire [CFG_MEM_IF_CHIP - 1 : 0] temp_do_precharge_all = bg_do_precharge_all [CFG_MEM_IF_CHIP - 1 : 0] | bg_do_precharge_all [2 * CFG_MEM_IF_CHIP - 1 : CFG_MEM_IF_CHIP];
// wire [CFG_MEM_IF_CHIP - 1 : 0] temp_do_deep_pdown = bg_do_deep_pdown [CFG_MEM_IF_CHIP - 1 : 0] | bg_do_deep_pdown [2 * CFG_MEM_IF_CHIP - 1 : CFG_MEM_IF_CHIP];
// wire [CFG_MEM_IF_CHIP - 1 : 0] temp_do_zq_cal = bg_do_zq_cal [CFG_MEM_IF_CHIP - 1 : 0] | bg_do_zq_cal [2 * CFG_MEM_IF_CHIP - 1 : CFG_MEM_IF_CHIP];
alt_mem_ddrx_addr_cmd_wrap #
(
.CFG_MEM_IF_CHIP (CFG_MEM_IF_CHIP ),
.CFG_MEM_IF_CKE_WIDTH (CFG_MEM_IF_CKE_WIDTH ),
.CFG_MEM_IF_ADDR_WIDTH (CFG_AFI_IF_FR_ADDR_WIDTH ),
.CFG_MEM_IF_ROW_WIDTH (CFG_MEM_IF_ROW_WIDTH ),
.CFG_MEM_IF_COL_WIDTH (CFG_MEM_IF_COL_WIDTH ),
.CFG_MEM_IF_BA_WIDTH (CFG_MEM_IF_BA_WIDTH ),
.CFG_LPDDR2_ENABLED (CFG_LPDDR2_ENABLED ),
.CFG_DWIDTH_RATIO (CFG_DWIDTH_RATIO ),
.CFG_ODT_ENABLED (CFG_ODT_ENABLED ),
.CFG_MEM_IF_ODT_WIDTH (CFG_MEM_IF_ODT_WIDTH ),
.CFG_AFI_INTF_PHASE_NUM (CFG_AFI_INTF_PHASE_NUM ),
.CFG_LOCAL_ID_WIDTH (CFG_LOCAL_ID_WIDTH ),
.CFG_DATA_ID_WIDTH (CFG_DATA_ID_WIDTH ),
.CFG_INT_SIZE_WIDTH (CFG_INT_SIZE_WIDTH ),
.CFG_PORT_WIDTH_TYPE (CFG_PORT_WIDTH_TYPE ),
.CFG_PORT_WIDTH_CAS_WR_LAT (CFG_PORT_WIDTH_CAS_WR_LAT ),
.CFG_PORT_WIDTH_TCL (CFG_PORT_WIDTH_TCL ),
.CFG_PORT_WIDTH_ADD_LAT (CFG_PORT_WIDTH_ADD_LAT ),
.CFG_PORT_WIDTH_WRITE_ODT_CHIP (CFG_PORT_WIDTH_WRITE_ODT_CHIP ),
.CFG_PORT_WIDTH_READ_ODT_CHIP (CFG_PORT_WIDTH_READ_ODT_CHIP ),
.CFG_PORT_WIDTH_OUTPUT_REGD (CFG_PORT_WIDTH_OUTPUT_REGD )
)
addr_cmd_wrap_inst
(
.ctl_clk (ctl_clk ),
.ctl_reset_n (ctl_reset_n ),
.ctl_cal_success (ctl_cal_success ),
.cfg_type (cfg_type ),
.cfg_tcl (cfg_tcl ),
.cfg_cas_wr_lat (cfg_cas_wr_lat ),
.cfg_add_lat (cfg_add_lat ),
.cfg_write_odt_chip (cfg_write_odt_chip ),
.cfg_read_odt_chip (cfg_read_odt_chip ),
.cfg_burst_length (cfg_burst_length ),
.cfg_output_regd_for_afi_output (cfg_output_regd_for_afi_output ),
.bg_do_write (bg_do_write ),
.bg_do_read (bg_do_read ),
.bg_do_auto_precharge (bg_do_auto_precharge ),
.bg_do_burst_chop (bg_do_burst_chop ),
.bg_do_activate (bg_do_activate ),
.bg_do_precharge (bg_do_precharge ),
.bg_do_refresh (bg_do_refresh ),
.bg_do_power_down (bg_do_power_down ),
.bg_do_self_refresh (bg_do_self_refresh ),
.bg_do_rmw_correct (bg_do_rmw_correct ),
.bg_do_rmw_partial (bg_do_rmw_partial ),
.bg_do_lmr (bg_do_lmr ),
.bg_do_precharge_all (bg_do_precharge_all ),
.bg_do_zq_cal (bg_do_zq_cal ),
.bg_do_lmr_read (bg_do_lmr_read ),
.bg_do_refresh_1bank (bg_do_refresh_1bank ),
.bg_do_burst_terminate (bg_do_burst_terminate ),
.bg_do_deep_pdown (bg_do_deep_pdown ),
.bg_to_chip (bg_to_chip ),
.bg_to_bank (bg_to_bank ),
.bg_to_row (bg_to_row ),
.bg_to_col (bg_to_col ),
.bg_to_lmr (bg_to_lmr ),
.bg_dataid (bg_dataid ),
.bg_localid (bg_localid ),
.bg_size (bg_size ),
.lmr_opcode (lmr_opcode ),
.afi_cke (afi_cke ),
.afi_cs_n (afi_cs_n ),
.afi_ras_n (afi_ras_n ),
.afi_cas_n (afi_cas_n ),
.afi_we_n (afi_we_n ),
.afi_ba (afi_ba ),
.afi_addr (afi_addr ),
.afi_rst_n (afi_rst_n ),
.afi_odt (afi_odt )
);
//==============================================================================
// alt_mem_ddrx_odt_gen
//------------------------------------------------------------------------------
//
// ODT generation block
//
// Info: Generate ODT information based on user configuration
//
//==============================================================================
// alt_mem_ddrx_odt_gen #
// (
// .CFG_DWIDTH_RATIO (CFG_DWIDTH_RATIO ),
// .CFG_ODT_ENABLED (CFG_ODT_ENABLED ),
// .CFG_MEM_IF_CHIP (CFG_MEM_IF_CHIP ),
// .CFG_MEM_IF_ODT_WIDTH (CFG_MEM_IF_ODT_WIDTH ),
// .CFG_OUTPUT_REGD (CFG_OUTPUT_REGD ),
// .CFG_PORT_WIDTH_CAS_WR_LAT (CFG_PORT_WIDTH_CAS_WR_LAT ),
// .CFG_PORT_WIDTH_TCL (CFG_PORT_WIDTH_TCL ),
// .CFG_PORT_WIDTH_ADD_LAT (CFG_PORT_WIDTH_ADD_LAT ),
// .CFG_PORT_WIDTH_TYPE (CFG_PORT_WIDTH_TYPE )
// )
// odt_gen_inst
// (
// .ctl_clk (ctl_clk ),
// .ctl_reset_n (ctl_reset_n ),
// .cfg_type (cfg_type ),
// .cfg_tcl (cfg_tcl ),
// .cfg_cas_wr_lat (cfg_cas_wr_lat ),
// .cfg_add_lat (cfg_add_lat ),
// .cfg_write_odt_chip (cfg_write_odt_chip ),
// .cfg_read_odt_chip (cfg_read_odt_chip ),
// .cfg_burst_length (cfg_burst_length ),
// .bg_do_read (bg_do_read ),
// .bg_do_write (bg_do_write ),
// .bg_to_chip (bg_to_chip ),
// .afi_odt (afi_odt )
// );
//==============================================================================
// alt_mem_ddrx_rdwr_data_tmg
//------------------------------------------------------------------------------
//
// Read / write data timing block
//
// Info: Adjust read and write data timing based on AFI information
//
//==============================================================================
alt_mem_ddrx_rdwr_data_tmg #
(
.CFG_DWIDTH_RATIO (CFG_DWIDTH_RATIO ),
.CFG_MEM_IF_CHIP (CFG_MEM_IF_CHIP ),
.CFG_MEM_IF_DQ_WIDTH (CFG_MEM_IF_DQ_WIDTH ),
.CFG_MEM_IF_DQS_WIDTH (CFG_MEM_IF_DQS_WIDTH ),
.CFG_MEM_IF_DM_WIDTH (CFG_MEM_IF_DM_WIDTH ),
.CFG_WLAT_BUS_WIDTH (CFG_WLAT_BUS_WIDTH ),
.CFG_DRAM_WLAT_GROUP (CFG_DRAM_WLAT_GROUP ),
.CFG_DATA_ID_WIDTH (CFG_DATA_ID_WIDTH ),
.CFG_WDATA_REG (CFG_WDATA_REG ),
.CFG_ECC_ENC_REG (CFG_ECC_ENC_REG ),
.CFG_AFI_INTF_PHASE_NUM (CFG_AFI_INTF_PHASE_NUM ),
.CFG_PORT_WIDTH_ENABLE_ECC (CFG_PORT_WIDTH_ENABLE_ECC ),
.CFG_PORT_WIDTH_OUTPUT_REGD (CFG_PORT_WIDTH_OUTPUT_REGD ),
.CFG_CTL_ARBITER_TYPE (CFG_CTL_ARBITER_TYPE ),
.CFG_USE_SHADOW_REGS (CFG_USE_SHADOW_REGS )
)
rdwr_data_tmg_inst
(
.ctl_clk (ctl_clk ),
.ctl_reset_n (ctl_reset_n ),
.cfg_enable_ecc (cfg_enable_ecc ),
.cfg_output_regd (cfg_output_regd ),
.cfg_output_regd_for_afi_output (cfg_output_regd_for_afi_output ),
.bg_do_read (bg_do_read ),
.bg_do_write (bg_do_write ),
.bg_doing_read (bg_doing_read ),
.bg_doing_write (bg_doing_write ),
.bg_rdwr_data_valid (bg_rdwr_data_valid ),
.dataid (bg_dataid ),
.bg_do_rmw_correct (bg_do_rmw_correct ),
.bg_do_rmw_partial (bg_do_rmw_partial ),
.bg_to_chip (bg_to_chip ),
.ecc_wdata (ecc_wdata ),
.ecc_dm (ecc_dm ),
.afi_wlat (afi_wlat ),
.afi_doing_read (afi_rdata_en ),
.afi_doing_read_full (afi_rdata_en_full ),
.ecc_wdata_fifo_read (ecc_wdata_fifo_read ),
.ecc_wdata_fifo_dataid (ecc_wdata_fifo_dataid ),
.ecc_wdata_fifo_dataid_vector (ecc_wdata_fifo_dataid_vector ),
.ecc_wdata_fifo_rmw_correct (ecc_wdata_fifo_rmw_correct ),
.ecc_wdata_fifo_rmw_partial (ecc_wdata_fifo_rmw_partial ),
.ecc_wdata_fifo_read_first (ecc_wdata_fifo_read_first ),
.ecc_wdata_fifo_dataid_first (ecc_wdata_fifo_dataid_first ),
.ecc_wdata_fifo_dataid_vector_first (ecc_wdata_fifo_dataid_vector_first ),
.ecc_wdata_fifo_rmw_correct_first (ecc_wdata_fifo_rmw_correct_first ),
.ecc_wdata_fifo_rmw_partial_first (ecc_wdata_fifo_rmw_partial_first ),
.ecc_wdata_fifo_first_vector (ecc_wdata_fifo_first_vector ),
.ecc_wdata_fifo_read_last (ecc_wdata_fifo_read_last ),
.ecc_wdata_fifo_dataid_last (ecc_wdata_fifo_dataid_last ),
.ecc_wdata_fifo_dataid_vector_last (ecc_wdata_fifo_dataid_vector_last ),
.ecc_wdata_fifo_rmw_correct_last (ecc_wdata_fifo_rmw_correct_last ),
.ecc_wdata_fifo_rmw_partial_last (ecc_wdata_fifo_rmw_partial_last ),
.afi_rrank (int_afi_rrank ),
.afi_wrank (int_afi_wrank ),
.afi_dqs_burst (afi_dqs_burst ),
.afi_wdata_valid (afi_wdata_valid ),
.afi_wdata (afi_wdata ),
.afi_dm (afi_dm )
);
//==============================================================================
// alt_mem_ddrx_wdata_path
//------------------------------------------------------------------------------
//
// Write data path block
//
// Info: Handles write data processing
//
//==============================================================================
// match datapath id width, with command path id width
generate
begin : gen_resolve_datap_id
genvar i;
for (i = 0;i < CFG_DRAM_WLAT_GROUP;i = i + 1)
begin : write_dataid_per_dqs_group
if (CFG_WRDATA_ID_WIDTH < CFG_DATA_ID_WIDTH)
begin
assign ecc_wdata_wrdataid [(i + 1) * CFG_WRDATA_ID_WIDTH - 1 : i * CFG_WRDATA_ID_WIDTH ] = ecc_wdata_fifo_dataid [(i * CFG_DATA_ID_WIDTH ) + CFG_WRDATA_ID_WIDTH - 1 : i * CFG_DATA_ID_WIDTH ];
assign ecc_wdata_wrdataid_vector [(i + 1) * CFG_WRDATA_VEC_ID_WIDTH - 1 : i * CFG_WRDATA_VEC_ID_WIDTH] = ecc_wdata_fifo_dataid_vector [(i * CFG_DATAID_ARRAY_DEPTH) + CFG_WRDATA_VEC_ID_WIDTH - 1 : i * CFG_DATAID_ARRAY_DEPTH];
end
else // (CFG_WRDATA_ID_WIDTH >= CFG_DATA_ID_WIDTH)
begin
assign ecc_wdata_wrdataid [(i + 1) * CFG_WRDATA_ID_WIDTH - 1 : i * CFG_WRDATA_ID_WIDTH ] = {{(CFG_WRDATA_ID_WIDTH-CFG_DATA_ID_WIDTH){1'b0}},ecc_wdata_fifo_dataid [(i * CFG_DATA_ID_WIDTH ) + CFG_WRDATA_ID_WIDTH - 1 : i * CFG_DATA_ID_WIDTH ]};
assign ecc_wdata_wrdataid_vector [(i + 1) * CFG_WRDATA_VEC_ID_WIDTH - 1 : i * CFG_WRDATA_VEC_ID_WIDTH] = {{CFG_DATA_ID_REMAINDER {1'b0}},ecc_wdata_fifo_dataid_vector [(i * CFG_DATAID_ARRAY_DEPTH) + CFG_WRDATA_VEC_ID_WIDTH - 1 : i * CFG_DATAID_ARRAY_DEPTH]};
end
end
if (CFG_WRDATA_ID_WIDTH < CFG_DATA_ID_WIDTH)
begin
assign wdatap_free_id_dataid = {{(CFG_DATA_ID_WIDTH-CFG_WRDATA_ID_WIDTH){1'b0}},wdatap_free_id_wrdataid};
assign ecc_wdata_wrdataid_first = ecc_wdata_fifo_dataid_first [CFG_WRDATA_ID_WIDTH - 1 : 0];
assign ecc_wdata_wrdataid_vector_first = ecc_wdata_fifo_dataid_vector_first [CFG_WRDATA_ID_WIDTH_SQRD -1 : 0];
assign ecc_wdata_wrdataid_last = ecc_wdata_fifo_dataid_last [CFG_WRDATA_ID_WIDTH - 1 : 0];
assign ecc_wdata_wrdataid_vector_last = ecc_wdata_fifo_dataid_vector_last [CFG_WRDATA_ID_WIDTH_SQRD - 1 : 0];
end
else // (CFG_WRDATA_ID_WIDTH >= CFG_DATA_ID_WIDTH)
begin
assign wdatap_free_id_dataid = wdatap_free_id_wrdataid[CFG_DATA_ID_WIDTH-1:0];
assign ecc_wdata_wrdataid_first = {{(CFG_WRDATA_ID_WIDTH-CFG_DATA_ID_WIDTH){1'b0}},ecc_wdata_fifo_dataid_first};
assign ecc_wdata_wrdataid_vector_first = {{CFG_DATA_ID_REMAINDER{1'b0}},ecc_wdata_fifo_dataid_vector_first};
assign ecc_wdata_wrdataid_last = {{(CFG_WRDATA_ID_WIDTH-CFG_DATA_ID_WIDTH){1'b0}},ecc_wdata_fifo_dataid_last};
assign ecc_wdata_wrdataid_vector_last = {{CFG_DATA_ID_REMAINDER{1'b0}},ecc_wdata_fifo_dataid_vector_last};
end
if (CFG_RDDATA_ID_WIDTH < CFG_DATA_ID_WIDTH)
begin
assign rdatap_free_id_dataid = {{(CFG_DATA_ID_WIDTH-CFG_RDDATA_ID_WIDTH){1'b0}},rdatap_free_id_rddataid};
assign bg_rddataid = bg_dataid[CFG_RDDATA_ID_WIDTH-1:0];
end
else if(CFG_RDDATA_ID_WIDTH > CFG_DATA_ID_WIDTH)
begin
assign rdatap_free_id_dataid = rdatap_free_id_rddataid[CFG_DATA_ID_WIDTH-1:0];
assign bg_rddataid = {{(CFG_RDDATA_ID_WIDTH-CFG_DATA_ID_WIDTH){1'b0}},bg_dataid};
end
else // CFG_RDDATA_ID_WIDTH == CFG_DATA_ID_WIDTH
begin
assign rdatap_free_id_dataid = rdatap_free_id_rddataid[CFG_DATA_ID_WIDTH-1:0];
assign bg_rddataid = bg_dataid;
end
end
endgenerate
alt_mem_ddrx_wdata_path #
(
.CFG_LOCAL_DATA_WIDTH (CFG_LOCAL_DATA_WIDTH ),
.CFG_MEM_IF_DQ_WIDTH (CFG_MEM_IF_DQ_WIDTH ),
.CFG_MEM_IF_DQS_WIDTH (CFG_MEM_IF_DQS_WIDTH ),
.CFG_INT_SIZE_WIDTH (CFG_INT_SIZE_WIDTH ),
.CFG_DATA_ID_WIDTH (CFG_WRDATA_ID_WIDTH ),
.CFG_DRAM_WLAT_GROUP (CFG_DRAM_WLAT_GROUP ),
.CFG_LOCAL_WLAT_GROUP (CFG_LOCAL_WLAT_GROUP ),
.CFG_TBP_NUM (CFG_CTL_TBP_NUM ),
.CFG_BUFFER_ADDR_WIDTH (CFG_WRBUFFER_ADDR_WIDTH ),
.CFG_DWIDTH_RATIO (CFG_DWIDTH_RATIO ),
.CFG_ECC_MULTIPLES (CFG_ECC_MULTIPLES ),
.CFG_WDATA_REG (CFG_WDATA_REG ),
.CFG_PARTIAL_BE_PER_WORD_ENABLE (CFG_PARTIAL_BE_PER_WORD_ENABLE ),
.CFG_ECC_CODE_WIDTH (CFG_ECC_CODE_WIDTH ),
.CFG_PORT_WIDTH_BURST_LENGTH (CFG_PORT_WIDTH_BURST_LENGTH ),
.CFG_PORT_WIDTH_ENABLE_ECC (CFG_PORT_WIDTH_ENABLE_ECC ),
.CFG_PORT_WIDTH_ENABLE_AUTO_CORR (CFG_PORT_WIDTH_ENABLE_AUTO_CORR),
.CFG_PORT_WIDTH_ENABLE_NO_DM (CFG_PORT_WIDTH_ENABLE_NO_DM ),
.CFG_PORT_WIDTH_ENABLE_ECC_CODE_OVERWRITES (CFG_PORT_WIDTH_ENABLE_ECC_CODE_OVERWRITES),
.CFG_PORT_WIDTH_INTERFACE_WIDTH (CFG_PORT_WIDTH_INTERFACE_WIDTH ),
.CFG_ECC_BE_ALLLOW_RMW (CFG_ECC_BE_ALLLOW_RMW)
)
wdata_path_inst
(
.ctl_clk (ctl_clk ),
.ctl_reset_n (ctl_reset_n ),
.cfg_burst_length (cfg_burst_length ),
.cfg_enable_ecc (cfg_enable_ecc ),
.cfg_enable_auto_corr (cfg_enable_auto_corr ),
.cfg_enable_no_dm (cfg_enable_no_dm ),
.cfg_enable_ecc_code_overwrites (cfg_enable_ecc_code_overwrites ),
.cfg_interface_width (cfg_interface_width ),
.wdatap_free_id_valid (wdatap_free_id_valid ),
.wdatap_free_id_dataid (wdatap_free_id_wrdataid ),
.proc_busy (proc_busy ),
.proc_load (proc_load ),
.proc_load_dataid (proc_load_dataid ),
.proc_write (proc_write ),
.tbp_load_index (tbp_load_index ),
.proc_size (proc_size ),
.wr_data_mem_full (wr_data_mem_full ),
.write_data_en (write_data_valid ),
.write_data (write_data ),
.byte_en (byte_en ),
.data_complete (data_complete ),
.data_rmw_complete (data_rmw_complete ),
.data_rmw_fetch (data_rmw_fetch ),
.data_partial_be (data_partial_be ),
.doing_write (ecc_wdata_fifo_read ),
.dataid (ecc_wdata_wrdataid ),
.dataid_vector (ecc_wdata_wrdataid_vector ),
.rdwr_data_valid (ecc_wdata_fifo_read ),
.rmw_correct (ecc_wdata_fifo_rmw_correct ),
.rmw_partial (ecc_wdata_fifo_rmw_partial ),
.doing_write_first (ecc_wdata_fifo_read_first ),
.dataid_first (ecc_wdata_wrdataid_first ),
.dataid_vector_first (ecc_wdata_wrdataid_vector_first ),
.rdwr_data_valid_first (ecc_wdata_fifo_read_first ),
.rmw_correct_first (ecc_wdata_fifo_rmw_correct_first ),
.rmw_partial_first (ecc_wdata_fifo_rmw_partial_first ),
.doing_write_first_vector (ecc_wdata_fifo_first_vector ),
.rdwr_data_valid_first_vector (ecc_wdata_fifo_first_vector ),
.doing_write_last (ecc_wdata_fifo_read_last ),
.dataid_last (ecc_wdata_wrdataid_last ),
.dataid_vector_last (ecc_wdata_wrdataid_vector_last ),
.rdwr_data_valid_last (ecc_wdata_fifo_read_last ),
.rmw_correct_last (ecc_wdata_fifo_rmw_correct_last ),
.rmw_partial_last (ecc_wdata_fifo_rmw_partial_last ),
.wdatap_data (wdatap_data ),
.wdatap_rmw_partial_data (wdatap_rmw_partial_data ),
.wdatap_rmw_correct_data (wdatap_rmw_correct_data ),
.wdatap_rmw_partial (wdatap_rmw_partial ),
.wdatap_rmw_correct (wdatap_rmw_correct ),
.wdatap_dm (wdatap_dm ),
.wdatap_ecc_code (wdatap_ecc_code ),
.wdatap_ecc_code_overwrite (wdatap_ecc_code_overwrite ),
.rmwfifo_data_valid (rmwfifo_data_valid ),
.rmwfifo_data (rmwfifo_data ),
.rmwfifo_ecc_dbe (rmwfifo_ecc_dbe ),
.rmwfifo_ecc_code (rmwfifo_ecc_code )
);
//==============================================================================
// alt_mem_ddrx_rdata_path
//------------------------------------------------------------------------------
//
// Read data path block
//
// Info: Handles read data processing
//
//==============================================================================
alt_mem_ddrx_rdata_path #
(
.CFG_LOCAL_DATA_WIDTH (CFG_LOCAL_DATA_WIDTH ),
.CFG_INT_SIZE_WIDTH (CFG_INT_SIZE_WIDTH ),
.CFG_DATA_ID_WIDTH (CFG_RDDATA_ID_WIDTH ),
.CFG_LOCAL_ID_WIDTH (CFG_LOCAL_ID_WIDTH ),
.CFG_LOCAL_ADDR_WIDTH (CFG_LOCAL_ADDR_WIDTH ),
.CFG_BUFFER_ADDR_WIDTH (CFG_RDBUFFER_ADDR_WIDTH ),
.CFG_MEM_IF_CS_WIDTH (CFG_MEM_IF_CS_WIDTH ),
.CFG_MEM_IF_BA_WIDTH (CFG_MEM_IF_BA_WIDTH ),
.CFG_MEM_IF_ROW_WIDTH (CFG_MEM_IF_ROW_WIDTH ),
.CFG_MEM_IF_COL_WIDTH (CFG_MEM_IF_COL_WIDTH ),
.CFG_MAX_READ_CMD_NUM_WIDTH (CFG_MAX_PENDING_RD_CMD_WIDTH ),
.CFG_RDATA_RETURN_MODE (CFG_RDATA_RETURN_MODE ),
.CFG_AFI_INTF_PHASE_NUM (CFG_AFI_INTF_PHASE_NUM ),
.CFG_ERRCMD_FIFO_ADDR_WIDTH (CFG_ERRCMD_FIFO_ADDR_WIDTH ),
.CFG_DWIDTH_RATIO (CFG_DWIDTH_RATIO ),
.CFG_ECC_MULTIPLES (CFG_ECC_MULTIPLES ),
.CFG_ECC_CODE_WIDTH (CFG_ECC_CODE_WIDTH ),
.CFG_PORT_WIDTH_TYPE (CFG_PORT_WIDTH_TYPE ),
.CFG_PORT_WIDTH_ENABLE_ECC (CFG_PORT_WIDTH_ENABLE_ECC ),
.CFG_PORT_WIDTH_ENABLE_AUTO_CORR (CFG_PORT_WIDTH_ENABLE_AUTO_CORR ),
.CFG_PORT_WIDTH_ENABLE_NO_DM (CFG_PORT_WIDTH_ENABLE_NO_DM ),
.CFG_PORT_WIDTH_BURST_LENGTH (CFG_PORT_WIDTH_BURST_LENGTH ),
.CFG_PORT_WIDTH_ADDR_ORDER (CFG_PORT_WIDTH_ADDR_ORDER ),
.CFG_PORT_WIDTH_COL_ADDR_WIDTH (CFG_PORT_WIDTH_COL_ADDR_WIDTH ),
.CFG_PORT_WIDTH_ROW_ADDR_WIDTH (CFG_PORT_WIDTH_ROW_ADDR_WIDTH ),
.CFG_PORT_WIDTH_BANK_ADDR_WIDTH (CFG_PORT_WIDTH_BANK_ADDR_WIDTH ),
.CFG_PORT_WIDTH_CS_ADDR_WIDTH (CFG_PORT_WIDTH_CS_ADDR_WIDTH ),
.CFG_ERRCMD_FIFO_REG (CFG_ERRCMD_FIFO_REG )
)
rdata_path_inst
(
.ctl_clk (ctl_clk ),
.ctl_reset_n (ctl_reset_n ),
.cfg_type (cfg_type ),
.cfg_enable_ecc (cfg_enable_ecc ),
.cfg_enable_auto_corr (cfg_enable_auto_corr ),
.cfg_enable_no_dm (cfg_enable_no_dm ),
.cfg_burst_length (cfg_burst_length ),
.cfg_addr_order (cfg_addr_order ),
.cfg_col_addr_width (cfg_col_addr_width ),
.cfg_row_addr_width (cfg_row_addr_width ),
.cfg_bank_addr_width (cfg_bank_addr_width ),
.cfg_cs_addr_width (cfg_cs_addr_width ),
.rdatap_free_id_valid (rdatap_free_id_valid ),
.rdatap_free_id_dataid (rdatap_free_id_rddataid ),
.proc_busy (proc_busy ),
.proc_load (proc_load ),
.proc_load_dataid (proc_load_dataid ),
.proc_read (proc_read ),
.proc_size (proc_size ),
.proc_localid (proc_localid ),
.read_data_valid (read_data_valid ),
.read_data (read_data ),
.read_data_error (read_data_error ),
.read_data_localid (read_data_localid ),
.bg_do_read (bg_do_read ),
.bg_to_chipsel (bg_to_chipsel ),
.bg_to_bank (bg_to_bank ),
.bg_to_row (bg_to_row ),
.bg_to_column (bg_to_col ),
.bg_dataid (bg_rddataid ),
.bg_localid (bg_localid ),
.bg_size (bg_size ),
.bg_do_rmw_correct (bg_do_rmw_correct ),
.bg_do_rmw_partial (bg_do_rmw_partial ),
.ecc_rdata (ecc_rdata ),
.ecc_rdatav (ecc_rdata_valid ),
.ecc_sbe (ecc_sbe ),
.ecc_dbe (ecc_dbe ),
.ecc_code (ecc_code ),
.errcmd_ready (errcmd_ready ),
.errcmd_valid (errcmd_valid ),
.errcmd_chipsel (errcmd_chipsel ),
.errcmd_bank (errcmd_bank ),
.errcmd_row (errcmd_row ),
.errcmd_column (errcmd_column ),
.errcmd_size (errcmd_size ),
.errcmd_localid (errcmd_localid ),
.rdatap_rcvd_addr (rdatap_rcvd_addr ),
.rdatap_rcvd_cmd (rdatap_rcvd_cmd ),
.rdatap_rcvd_corr_dropped (rdatap_rcvd_corr_dropped ),
.rmwfifo_data_valid (rmwfifo_data_valid ),
.rmwfifo_data (rmwfifo_data ),
.rmwfifo_ecc_dbe (rmwfifo_ecc_dbe ),
.rmwfifo_ecc_code (rmwfifo_ecc_code )
);
//==============================================================================
// alt_mem_ddrx_ecc_encoder_decoder_wrapper
//------------------------------------------------------------------------------
//
// ECC encoder/decoder block
//
// Info: Encode write data and decode read data, correct single bit error
// and detect double bit errors
//
//==============================================================================
alt_mem_ddrx_ecc_encoder_decoder_wrapper #
(
.CFG_LOCAL_ADDR_WIDTH (CFG_LOCAL_ADDR_WIDTH ),
.CFG_LOCAL_DATA_WIDTH (CFG_LOCAL_DATA_WIDTH ),
.CFG_DWIDTH_RATIO (CFG_DWIDTH_RATIO ),
.CFG_ECC_MULTIPLES (CFG_ECC_MULTIPLES ),
.CFG_MEM_IF_DQ_WIDTH (CFG_MEM_IF_DQ_WIDTH ),
.CFG_MEM_IF_DQS_WIDTH (CFG_MEM_IF_DQS_WIDTH ),
.CFG_ECC_CODE_WIDTH (CFG_ECC_CODE_WIDTH ),
.CFG_ECC_ENC_REG (CFG_ECC_ENC_REG ),
.CFG_ECC_DEC_REG (CFG_ECC_DEC_REG ),
.CFG_ECC_DECODER_REG (CFG_ECC_DECODER_REG ),
.CFG_ECC_RDATA_REG (CFG_ECC_RDATA_REG ),
.CFG_PORT_WIDTH_INTERFACE_WIDTH (CFG_PORT_WIDTH_INTERFACE_WIDTH ),
.CFG_PORT_WIDTH_ENABLE_ECC (CFG_PORT_WIDTH_ENABLE_ECC ),
.CFG_PORT_WIDTH_GEN_SBE (CFG_PORT_WIDTH_GEN_SBE ),
.CFG_PORT_WIDTH_GEN_DBE (CFG_PORT_WIDTH_GEN_DBE ),
.CFG_PORT_WIDTH_ENABLE_INTR (CFG_PORT_WIDTH_ENABLE_INTR ),
.CFG_PORT_WIDTH_MASK_SBE_INTR (CFG_PORT_WIDTH_MASK_SBE_INTR ),
.CFG_PORT_WIDTH_MASK_DBE_INTR (CFG_PORT_WIDTH_MASK_DBE_INTR ),
.CFG_PORT_WIDTH_MASK_CORR_DROPPED_INTR (CFG_PORT_WIDTH_MASK_CORR_DROPPED_INTR),
.CFG_PORT_WIDTH_CLR_INTR (CFG_PORT_WIDTH_CLR_INTR ),
.STS_PORT_WIDTH_SBE_ERROR (STS_PORT_WIDTH_SBE_ERROR ),
.STS_PORT_WIDTH_DBE_ERROR (STS_PORT_WIDTH_DBE_ERROR ),
.STS_PORT_WIDTH_SBE_COUNT (STS_PORT_WIDTH_SBE_COUNT ),
.STS_PORT_WIDTH_DBE_COUNT (STS_PORT_WIDTH_DBE_COUNT ),
.STS_PORT_WIDTH_CORR_DROP_ERROR (STS_PORT_WIDTH_CORR_DROP_ERROR ),
.STS_PORT_WIDTH_CORR_DROP_COUNT (STS_PORT_WIDTH_CORR_DROP_COUNT )
)
ecc_encoder_decoder_wrapper_inst
(
.ctl_clk (ctl_clk ),
.ctl_reset_n (ctl_reset_n ),
.cfg_interface_width (cfg_interface_width ),
.cfg_enable_ecc (cfg_enable_ecc ),
.cfg_gen_sbe (cfg_gen_sbe ),
.cfg_gen_dbe (cfg_gen_dbe ),
.cfg_enable_intr (cfg_enable_intr ),
.cfg_mask_sbe_intr (cfg_mask_sbe_intr ),
.cfg_mask_dbe_intr (cfg_mask_dbe_intr ),
.cfg_mask_corr_dropped_intr (cfg_mask_corr_dropped_intr ),
.cfg_clr_intr (cfg_clr_intr ),
.wdatap_dm (wdatap_dm ),
.wdatap_data (wdatap_data ),
.wdatap_rmw_partial_data (wdatap_rmw_partial_data ),
.wdatap_rmw_correct_data (wdatap_rmw_correct_data ),
.wdatap_rmw_partial (wdatap_rmw_partial ),
.wdatap_rmw_correct (wdatap_rmw_correct ),
.wdatap_ecc_code (wdatap_ecc_code ),
.wdatap_ecc_code_overwrite (wdatap_ecc_code_overwrite ),
.rdatap_rcvd_addr (rdatap_rcvd_addr ),
.rdatap_rcvd_cmd (rdatap_rcvd_cmd ),
.rdatap_rcvd_corr_dropped (rdatap_rcvd_corr_dropped ),
.afi_rdata (afi_rdata ),
.afi_rdata_valid (afi_rdata_valid ),
.ecc_rdata (ecc_rdata ),
.ecc_rdata_valid (ecc_rdata_valid ),
.ecc_dm (ecc_dm ),
.ecc_wdata (ecc_wdata ),
.ecc_sbe (ecc_sbe ),
.ecc_dbe (ecc_dbe ),
.ecc_code (ecc_code ),
.ecc_interrupt (ecc_interrupt ),
.sts_sbe_error (sts_sbe_error ),
.sts_dbe_error (sts_dbe_error ),
.sts_sbe_count (sts_sbe_count ),
.sts_dbe_count (sts_dbe_count ),
.sts_err_addr (sts_err_addr ),
.sts_corr_dropped (sts_corr_dropped ),
.sts_corr_dropped_count (sts_corr_dropped_count ),
.sts_corr_dropped_addr (sts_corr_dropped_addr )
);
//==============================================================================
// alt_mem_ddrx_sideband
//------------------------------------------------------------------------------
//
// Sideband block
//
// Info: Monitor and issue sideband specific commands such as user/auto
// refresh, self refresh, power down, deep power down,
// precharge all and zq calibration commands
//
//==============================================================================
alt_mem_ddrx_sideband #
(
.CFG_PORT_WIDTH_TYPE (CFG_PORT_WIDTH_TYPE ),
.CFG_DWIDTH_RATIO (CFG_DWIDTH_RATIO ),
.CFG_REG_GRANT (CFG_REG_GRANT ),
.CFG_CTL_TBP_NUM (CFG_CTL_TBP_NUM ),
.CFG_MEM_IF_CS_WIDTH (CFG_MEM_IF_CS_WIDTH ),
.CFG_MEM_IF_CHIP (CFG_MEM_IF_CHIP ),
.CFG_MEM_IF_BA_WIDTH (CFG_MEM_IF_BA_WIDTH ),
.CFG_PORT_WIDTH_TCL (CFG_PORT_WIDTH_TCL ),
.CFG_PORT_WIDTH_CS_ADDR_WIDTH (CFG_PORT_WIDTH_CS_ADDR_WIDTH ),
.CFG_MEM_IF_CLK_PAIR_COUNT (CFG_MEM_IF_CLK_PAIR_COUNT ),
.CFG_RANK_TIMER_OUTPUT_REG (CFG_RANK_TIMER_OUTPUT_REG ),
.T_PARAM_ARF_TO_VALID_WIDTH (T_PARAM_ARF_TO_VALID_WIDTH ),
.T_PARAM_ARF_PERIOD_WIDTH (T_PARAM_ARF_PERIOD_WIDTH ),
.T_PARAM_PCH_ALL_TO_VALID_WIDTH (T_PARAM_PCH_ALL_TO_VALID_WIDTH ),
.T_PARAM_SRF_TO_VALID_WIDTH (T_PARAM_SRF_TO_VALID_WIDTH ),
.T_PARAM_SRF_TO_ZQ_CAL_WIDTH (T_PARAM_SRF_TO_ZQ_CAL_WIDTH ),
.T_PARAM_PDN_TO_VALID_WIDTH (T_PARAM_PDN_TO_VALID_WIDTH ),
.T_PARAM_PDN_PERIOD_WIDTH (T_PARAM_PDN_PERIOD_WIDTH ),
.T_PARAM_POWER_SAVING_EXIT_WIDTH (T_PARAM_POWER_SAVING_EXIT_WIDTH ),
.T_PARAM_MEM_CLK_ENTRY_CYCLES_WIDTH (T_PARAM_MEM_CLK_ENTRY_CYCLES_WIDTH )
)
sideband_inst
(
.ctl_clk (ctl_clk ),
.ctl_reset_n (ctl_reset_n ),
.rfsh_req (rfsh_req ),
.rfsh_chip (rfsh_chip ),
.rfsh_ack (rfsh_ack ),
.zqcal_req (zqcal_req ),
.self_rfsh_req (self_rfsh_req ),
.self_rfsh_chip (self_rfsh_chip ),
.self_rfsh_ack (self_rfsh_ack ),
.deep_powerdn_req (deep_powerdn_req ),
.deep_powerdn_chip (deep_powerdn_chip ),
.deep_powerdn_ack (deep_powerdn_ack ),
.power_down_ack (power_down_ack ),
.stall_row_arbiter (stall_row_arbiter ),
.stall_col_arbiter (stall_col_arbiter ),
.stall_chip (stall_chip ),
.sb_do_precharge_all (sb_do_precharge_all ),
.sb_do_refresh (sb_do_refresh ),
.sb_do_self_refresh (sb_do_self_refresh ),
.sb_do_power_down (sb_do_power_down ),
.sb_do_deep_pdown (sb_do_deep_pdown ),
.sb_do_zq_cal (sb_do_zq_cal ),
.sb_tbp_precharge_all (sb_tbp_precharge_all ),
.ctl_mem_clk_disable (ctl_sb_mem_clk_disable ),
.ctl_cal_req (ctl_sb_cal_req ),
.ctl_init_req (ctl_sb_init_req ),
.ctl_cal_success (ctl_cal_success ),
.cmd_gen_chipsel (cmd_gen_chipsel ),
.tbp_chipsel (tbp_chipsel ),
.tbp_load (tbp_load ),
.t_param_arf_to_valid (t_param_arf_to_valid ),
.t_param_arf_period (t_param_arf_period ),
.t_param_pch_all_to_valid (t_param_pch_all_to_valid ),
.t_param_srf_to_valid (t_param_srf_to_valid ),
.t_param_srf_to_zq_cal (t_param_srf_to_zq_cal ),
.t_param_pdn_to_valid (t_param_pdn_to_valid ),
.t_param_pdn_period (t_param_pdn_period ),
.t_param_power_saving_exit (t_param_power_saving_exit ),
.t_param_mem_clk_entry_cycles (t_param_mem_clk_entry_cycles ),
.tbp_empty (tbp_empty ),
.tbp_bank_closed (tbp_bank_closed ),
.tbp_timer_ready (tbp_timer_ready ),
.row_grant (or_row_grant ),
.col_grant (or_col_grant ),
.afi_ctl_refresh_done (afi_ctl_refresh_done ),
.afi_seq_busy (afi_seq_busy ),
.afi_ctl_long_idle (afi_ctl_long_idle ),
.cfg_cs_addr_width (cfg_cs_addr_width ),
.cfg_enable_dqs_tracking (cfg_enable_dqs_tracking ),
.cfg_user_rfsh (cfg_user_rfsh ),
.cfg_type (cfg_type ),
.cfg_tcl (cfg_tcl ),
.cfg_regdimm_enable (cfg_regdimm_enable ),
.sideband_in_refresh (sideband_in_refresh )
);
//==============================================================================
// alt_mem_ddrx_rank_timer
//------------------------------------------------------------------------------
//
// Rank timer block
//
// Info: Monitor rank specific timing parameter for activate, precharge,
// read and write commands
//
//==============================================================================
alt_mem_ddrx_rank_timer #
(
.CFG_DWIDTH_RATIO (CFG_DWIDTH_RATIO ),
.CFG_CTL_TBP_NUM (CFG_CTL_TBP_NUM ),
.CFG_CTL_ARBITER_TYPE (CFG_CTL_ARBITER_TYPE ),
.CFG_MEM_IF_CHIP (CFG_MEM_IF_CHIP ),
.CFG_MEM_IF_CS_WIDTH (CFG_MEM_IF_CS_WIDTH ),
.CFG_INT_SIZE_WIDTH (CFG_INT_SIZE_WIDTH ),
.CFG_AFI_INTF_PHASE_NUM (CFG_AFI_INTF_PHASE_NUM ),
.CFG_REG_GRANT (CFG_REG_GRANT ),
.CFG_RANK_TIMER_OUTPUT_REG (CFG_RANK_TIMER_OUTPUT_REG ),
.CFG_PORT_WIDTH_BURST_LENGTH (CFG_PORT_WIDTH_BURST_LENGTH ),
.T_PARAM_FOUR_ACT_TO_ACT_WIDTH (T_PARAM_FOUR_ACT_TO_ACT_WIDTH ),
.T_PARAM_ACT_TO_ACT_DIFF_BANK_WIDTH (T_PARAM_ACT_TO_ACT_DIFF_BANK_WIDTH ),
.T_PARAM_WR_TO_WR_WIDTH (T_PARAM_WR_TO_WR_WIDTH ),
.T_PARAM_WR_TO_WR_DIFF_CHIP_WIDTH (T_PARAM_WR_TO_WR_DIFF_CHIP_WIDTH ),
.T_PARAM_WR_TO_RD_WIDTH (T_PARAM_WR_TO_RD_WIDTH ),
.T_PARAM_WR_TO_RD_BC_WIDTH (T_PARAM_WR_TO_RD_BC_WIDTH ),
.T_PARAM_WR_TO_RD_DIFF_CHIP_WIDTH (T_PARAM_WR_TO_RD_DIFF_CHIP_WIDTH ),
.T_PARAM_RD_TO_RD_WIDTH (T_PARAM_RD_TO_RD_WIDTH ),
.T_PARAM_RD_TO_RD_DIFF_CHIP_WIDTH (T_PARAM_RD_TO_RD_DIFF_CHIP_WIDTH ),
.T_PARAM_RD_TO_WR_WIDTH (T_PARAM_RD_TO_WR_WIDTH ),
.T_PARAM_RD_TO_WR_BC_WIDTH (T_PARAM_RD_TO_WR_BC_WIDTH ),
.T_PARAM_RD_TO_WR_DIFF_CHIP_WIDTH (T_PARAM_RD_TO_WR_DIFF_CHIP_WIDTH )
)
rank_timer_inst
(
.ctl_clk (ctl_clk ),
.ctl_reset_n (ctl_reset_n ),
.cfg_burst_length (cfg_burst_length ),
.t_param_four_act_to_act (t_param_four_act_to_act ),
.t_param_act_to_act_diff_bank (t_param_act_to_act_diff_bank ),
.t_param_wr_to_wr (t_param_wr_to_wr ),
.t_param_wr_to_wr_diff_chip (t_param_wr_to_wr_diff_chip ),
.t_param_wr_to_rd (t_param_wr_to_rd ),
.t_param_wr_to_rd_bc (t_param_wr_to_rd_bc ),
.t_param_wr_to_rd_diff_chip (t_param_wr_to_rd_diff_chip ),
.t_param_rd_to_rd (t_param_rd_to_rd ),
.t_param_rd_to_rd_diff_chip (t_param_rd_to_rd_diff_chip ),
.t_param_rd_to_wr (t_param_rd_to_wr ),
.t_param_rd_to_wr_bc (t_param_rd_to_wr_bc ),
.t_param_rd_to_wr_diff_chip (t_param_rd_to_wr_diff_chip ),
.bg_do_write (bg_do_write_combi ),
.bg_do_read (bg_do_read_combi ),
.bg_do_burst_chop (bg_do_burst_chop_combi ),
.bg_do_burst_terminate (bg_do_burst_terminate_combi ),
.bg_do_activate (bg_do_activate_combi ),
.bg_do_precharge (bg_do_precharge_combi ),
.bg_to_chip (bg_to_chip_combi ),
.bg_effective_size (bg_effective_size_combi ),
.bg_interrupt_ready (bg_interrupt_ready_combi ),
.cmd_gen_chipsel (cmd_gen_chipsel ),
.tbp_chipsel (tbp_chipsel ),
.tbp_load (tbp_load ),
.stall_chip (stall_chip ),
.can_activate (can_activate ),
.can_precharge (can_precharge ),
.can_read (can_read ),
.can_write (can_write )
);
//==============================================================================
// alt_mem_ddrx_timing_param
//------------------------------------------------------------------------------
//
// Timing parameter block
//
// Info: Pre-calculate required timing parameters for each memory commands
// based on memory type
//
//==============================================================================
alt_mem_ddrx_timing_param #
(
.CFG_DWIDTH_RATIO (CFG_DWIDTH_RATIO ),
.CFG_CTL_ARBITER_TYPE (CFG_CTL_ARBITER_TYPE ),
.CFG_PORT_WIDTH_TYPE (CFG_PORT_WIDTH_TYPE ),
.CFG_PORT_WIDTH_BURST_LENGTH (CFG_PORT_WIDTH_BURST_LENGTH ),
.CFG_PORT_WIDTH_CAS_WR_LAT (CFG_PORT_WIDTH_CAS_WR_LAT ),
.CFG_PORT_WIDTH_ADD_LAT (CFG_PORT_WIDTH_ADD_LAT ),
.CFG_PORT_WIDTH_TCL (CFG_PORT_WIDTH_TCL ),
.CFG_PORT_WIDTH_TRRD (CFG_PORT_WIDTH_TRRD ),
.CFG_PORT_WIDTH_TFAW (CFG_PORT_WIDTH_TFAW ),
.CFG_PORT_WIDTH_TRFC (CFG_PORT_WIDTH_TRFC ),
.CFG_PORT_WIDTH_TREFI (CFG_PORT_WIDTH_TREFI ),
.CFG_PORT_WIDTH_TRCD (CFG_PORT_WIDTH_TRCD ),
.CFG_PORT_WIDTH_TRP (CFG_PORT_WIDTH_TRP ),
.CFG_PORT_WIDTH_TWR (CFG_PORT_WIDTH_TWR ),
.CFG_PORT_WIDTH_TWTR (CFG_PORT_WIDTH_TWTR ),
.CFG_PORT_WIDTH_TRTP (CFG_PORT_WIDTH_TRTP ),
.CFG_PORT_WIDTH_TRAS (CFG_PORT_WIDTH_TRAS ),
.CFG_PORT_WIDTH_TRC (CFG_PORT_WIDTH_TRC ),
.CFG_PORT_WIDTH_TCCD (CFG_PORT_WIDTH_TCCD ),
.CFG_PORT_WIDTH_TMRD (CFG_PORT_WIDTH_TMRD ),
.CFG_PORT_WIDTH_SELF_RFSH_EXIT_CYCLES (CFG_PORT_WIDTH_SELF_RFSH_EXIT_CYCLES ),
.CFG_PORT_WIDTH_PDN_EXIT_CYCLES (CFG_PORT_WIDTH_PDN_EXIT_CYCLES ),
.CFG_PORT_WIDTH_AUTO_PD_CYCLES (CFG_PORT_WIDTH_AUTO_PD_CYCLES ),
.CFG_PORT_WIDTH_POWER_SAVING_EXIT_CYCLES (CFG_PORT_WIDTH_POWER_SAVING_EXIT_CYCLES ),
.CFG_PORT_WIDTH_MEM_CLK_ENTRY_CYCLES (CFG_PORT_WIDTH_MEM_CLK_ENTRY_CYCLES ),
.CFG_PORT_WIDTH_EXTRA_CTL_CLK_ACT_TO_RDWR (CFG_PORT_WIDTH_EXTRA_CTL_CLK_ACT_TO_RDWR ),
.CFG_PORT_WIDTH_EXTRA_CTL_CLK_ACT_TO_PCH (CFG_PORT_WIDTH_EXTRA_CTL_CLK_ACT_TO_PCH ),
.CFG_PORT_WIDTH_EXTRA_CTL_CLK_ACT_TO_ACT (CFG_PORT_WIDTH_EXTRA_CTL_CLK_ACT_TO_ACT ),
.CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_RD (CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_RD ),
.CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_RD_DIFF_CHIP (CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_RD_DIFF_CHIP ),
.CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_WR (CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_WR ),
.CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_WR_BC (CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_WR_BC ),
.CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP (CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP ),
.CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_PCH (CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_PCH ),
.CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_AP_TO_VALID (CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_AP_TO_VALID ),
.CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_WR (CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_WR ),
.CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_WR_DIFF_CHIP (CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_WR_DIFF_CHIP ),
.CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_RD (CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_RD ),
.CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_RD_BC (CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_RD_BC ),
.CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_RD_DIFF_CHIP (CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_RD_DIFF_CHIP ),
.CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_PCH (CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_PCH ),
.CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_AP_TO_VALID (CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_AP_TO_VALID ),
.CFG_PORT_WIDTH_EXTRA_CTL_CLK_PCH_TO_VALID (CFG_PORT_WIDTH_EXTRA_CTL_CLK_PCH_TO_VALID ),
.CFG_PORT_WIDTH_EXTRA_CTL_CLK_PCH_ALL_TO_VALID (CFG_PORT_WIDTH_EXTRA_CTL_CLK_PCH_ALL_TO_VALID ),
.CFG_PORT_WIDTH_EXTRA_CTL_CLK_ACT_TO_ACT_DIFF_BANK (CFG_PORT_WIDTH_EXTRA_CTL_CLK_ACT_TO_ACT_DIFF_BANK ),
.CFG_PORT_WIDTH_EXTRA_CTL_CLK_FOUR_ACT_TO_ACT (CFG_PORT_WIDTH_EXTRA_CTL_CLK_FOUR_ACT_TO_ACT ),
.CFG_PORT_WIDTH_EXTRA_CTL_CLK_ARF_TO_VALID (CFG_PORT_WIDTH_EXTRA_CTL_CLK_ARF_TO_VALID ),
.CFG_PORT_WIDTH_EXTRA_CTL_CLK_PDN_TO_VALID (CFG_PORT_WIDTH_EXTRA_CTL_CLK_PDN_TO_VALID ),
.CFG_PORT_WIDTH_EXTRA_CTL_CLK_SRF_TO_VALID (CFG_PORT_WIDTH_EXTRA_CTL_CLK_SRF_TO_VALID ),
.CFG_PORT_WIDTH_EXTRA_CTL_CLK_SRF_TO_ZQ_CAL (CFG_PORT_WIDTH_EXTRA_CTL_CLK_SRF_TO_ZQ_CAL ),
.CFG_PORT_WIDTH_EXTRA_CTL_CLK_ARF_PERIOD (CFG_PORT_WIDTH_EXTRA_CTL_CLK_ARF_PERIOD ),
.CFG_PORT_WIDTH_EXTRA_CTL_CLK_PDN_PERIOD (CFG_PORT_WIDTH_EXTRA_CTL_CLK_PDN_PERIOD ),
.T_PARAM_ACT_TO_RDWR_WIDTH (T_PARAM_ACT_TO_RDWR_WIDTH ),
.T_PARAM_ACT_TO_PCH_WIDTH (T_PARAM_ACT_TO_PCH_WIDTH ),
.T_PARAM_ACT_TO_ACT_WIDTH (T_PARAM_ACT_TO_ACT_WIDTH ),
.T_PARAM_RD_TO_RD_WIDTH (T_PARAM_RD_TO_RD_WIDTH ),
.T_PARAM_RD_TO_RD_DIFF_CHIP_WIDTH (T_PARAM_RD_TO_RD_DIFF_CHIP_WIDTH ),
.T_PARAM_RD_TO_WR_WIDTH (T_PARAM_RD_TO_WR_WIDTH ),
.T_PARAM_RD_TO_WR_BC_WIDTH (T_PARAM_RD_TO_WR_BC_WIDTH ),
.T_PARAM_RD_TO_WR_DIFF_CHIP_WIDTH (T_PARAM_RD_TO_WR_DIFF_CHIP_WIDTH ),
.T_PARAM_RD_TO_PCH_WIDTH (T_PARAM_RD_TO_PCH_WIDTH ),
.T_PARAM_RD_AP_TO_VALID_WIDTH (T_PARAM_RD_AP_TO_VALID_WIDTH ),
.T_PARAM_WR_TO_WR_WIDTH (T_PARAM_WR_TO_WR_WIDTH ),
.T_PARAM_WR_TO_WR_DIFF_CHIP_WIDTH (T_PARAM_WR_TO_WR_DIFF_CHIP_WIDTH ),
.T_PARAM_WR_TO_RD_WIDTH (T_PARAM_WR_TO_RD_WIDTH ),
.T_PARAM_WR_TO_RD_BC_WIDTH (T_PARAM_WR_TO_RD_BC_WIDTH ),
.T_PARAM_WR_TO_RD_DIFF_CHIP_WIDTH (T_PARAM_WR_TO_RD_DIFF_CHIP_WIDTH ),
.T_PARAM_WR_TO_PCH_WIDTH (T_PARAM_WR_TO_PCH_WIDTH ),
.T_PARAM_WR_AP_TO_VALID_WIDTH (T_PARAM_WR_AP_TO_VALID_WIDTH ),
.T_PARAM_PCH_TO_VALID_WIDTH (T_PARAM_PCH_TO_VALID_WIDTH ),
.T_PARAM_PCH_ALL_TO_VALID_WIDTH (T_PARAM_PCH_ALL_TO_VALID_WIDTH ),
.T_PARAM_ACT_TO_ACT_DIFF_BANK_WIDTH (T_PARAM_ACT_TO_ACT_DIFF_BANK_WIDTH ),
.T_PARAM_FOUR_ACT_TO_ACT_WIDTH (T_PARAM_FOUR_ACT_TO_ACT_WIDTH ),
.T_PARAM_ARF_TO_VALID_WIDTH (T_PARAM_ARF_TO_VALID_WIDTH ),
.T_PARAM_PDN_TO_VALID_WIDTH (T_PARAM_PDN_TO_VALID_WIDTH ),
.T_PARAM_SRF_TO_VALID_WIDTH (T_PARAM_SRF_TO_VALID_WIDTH ),
.T_PARAM_SRF_TO_ZQ_CAL_WIDTH (T_PARAM_SRF_TO_ZQ_CAL_WIDTH ),
.T_PARAM_ARF_PERIOD_WIDTH (T_PARAM_ARF_PERIOD_WIDTH ),
.T_PARAM_PDN_PERIOD_WIDTH (T_PARAM_PDN_PERIOD_WIDTH ),
.T_PARAM_POWER_SAVING_EXIT_WIDTH (T_PARAM_POWER_SAVING_EXIT_WIDTH ),
.T_PARAM_MEM_CLK_ENTRY_CYCLES_WIDTH (T_PARAM_MEM_CLK_ENTRY_CYCLES_WIDTH )
)
timing_param_inst
(
.ctl_clk (ctl_clk ),
.ctl_reset_n (ctl_reset_n ),
.cfg_burst_length (cfg_burst_length ),
.cfg_type (cfg_type ),
.cfg_cas_wr_lat (cfg_cas_wr_lat ),
.cfg_add_lat (cfg_add_lat ),
.cfg_tcl (cfg_tcl ),
.cfg_trrd (cfg_trrd ),
.cfg_tfaw (cfg_tfaw ),
.cfg_trfc (cfg_trfc ),
.cfg_trefi (cfg_trefi ),
.cfg_trcd (cfg_trcd ),
.cfg_trp (cfg_trp ),
.cfg_twr (cfg_twr ),
.cfg_twtr (cfg_twtr ),
.cfg_trtp (cfg_trtp ),
.cfg_tras (cfg_tras ),
.cfg_trc (cfg_trc ),
.cfg_tccd (cfg_tccd ),
.cfg_tmrd (cfg_tmrd ),
.cfg_self_rfsh_exit_cycles (cfg_self_rfsh_exit_cycles ),
.cfg_pdn_exit_cycles (cfg_pdn_exit_cycles ),
.cfg_auto_pd_cycles (cfg_auto_pd_cycles ),
.cfg_power_saving_exit_cycles (cfg_power_saving_exit_cycles ),
.cfg_mem_clk_entry_cycles (cfg_mem_clk_entry_cycles ),
.cfg_extra_ctl_clk_act_to_rdwr (cfg_extra_ctl_clk_act_to_rdwr ),
.cfg_extra_ctl_clk_act_to_pch (cfg_extra_ctl_clk_act_to_pch ),
.cfg_extra_ctl_clk_act_to_act (cfg_extra_ctl_clk_act_to_act ),
.cfg_extra_ctl_clk_rd_to_rd (cfg_extra_ctl_clk_rd_to_rd ),
.cfg_extra_ctl_clk_rd_to_rd_diff_chip (cfg_extra_ctl_clk_rd_to_rd_diff_chip ),
.cfg_extra_ctl_clk_rd_to_wr (cfg_extra_ctl_clk_rd_to_wr ),
.cfg_extra_ctl_clk_rd_to_wr_bc (cfg_extra_ctl_clk_rd_to_wr_bc ),
.cfg_extra_ctl_clk_rd_to_wr_diff_chip (cfg_extra_ctl_clk_rd_to_wr_diff_chip ),
.cfg_extra_ctl_clk_rd_to_pch (cfg_extra_ctl_clk_rd_to_pch ),
.cfg_extra_ctl_clk_rd_ap_to_valid (cfg_extra_ctl_clk_rd_ap_to_valid ),
.cfg_extra_ctl_clk_wr_to_wr (cfg_extra_ctl_clk_wr_to_wr ),
.cfg_extra_ctl_clk_wr_to_wr_diff_chip (cfg_extra_ctl_clk_wr_to_wr_diff_chip ),
.cfg_extra_ctl_clk_wr_to_rd (cfg_extra_ctl_clk_wr_to_rd ),
.cfg_extra_ctl_clk_wr_to_rd_bc (cfg_extra_ctl_clk_wr_to_rd_bc ),
.cfg_extra_ctl_clk_wr_to_rd_diff_chip (cfg_extra_ctl_clk_wr_to_rd_diff_chip ),
.cfg_extra_ctl_clk_wr_to_pch (cfg_extra_ctl_clk_wr_to_pch ),
.cfg_extra_ctl_clk_wr_ap_to_valid (cfg_extra_ctl_clk_wr_ap_to_valid ),
.cfg_extra_ctl_clk_pch_to_valid (cfg_extra_ctl_clk_pch_to_valid ),
.cfg_extra_ctl_clk_pch_all_to_valid (cfg_extra_ctl_clk_pch_all_to_valid ),
.cfg_extra_ctl_clk_act_to_act_diff_bank (cfg_extra_ctl_clk_act_to_act_diff_bank ),
.cfg_extra_ctl_clk_four_act_to_act (cfg_extra_ctl_clk_four_act_to_act ),
.cfg_extra_ctl_clk_arf_to_valid (cfg_extra_ctl_clk_arf_to_valid ),
.cfg_extra_ctl_clk_pdn_to_valid (cfg_extra_ctl_clk_pdn_to_valid ),
.cfg_extra_ctl_clk_srf_to_valid (cfg_extra_ctl_clk_srf_to_valid ),
.cfg_extra_ctl_clk_srf_to_zq_cal (cfg_extra_ctl_clk_srf_to_zq_cal ),
.cfg_extra_ctl_clk_arf_period (cfg_extra_ctl_clk_arf_period ),
.cfg_extra_ctl_clk_pdn_period (cfg_extra_ctl_clk_pdn_period ),
.t_param_act_to_rdwr (t_param_act_to_rdwr ),
.t_param_act_to_pch (t_param_act_to_pch ),
.t_param_act_to_act (t_param_act_to_act ),
.t_param_rd_to_rd (t_param_rd_to_rd ),
.t_param_rd_to_rd_diff_chip (t_param_rd_to_rd_diff_chip ),
.t_param_rd_to_wr (t_param_rd_to_wr ),
.t_param_rd_to_wr_bc (t_param_rd_to_wr_bc ),
.t_param_rd_to_wr_diff_chip (t_param_rd_to_wr_diff_chip ),
.t_param_rd_to_pch (t_param_rd_to_pch ),
.t_param_rd_ap_to_valid (t_param_rd_ap_to_valid ),
.t_param_wr_to_wr (t_param_wr_to_wr ),
.t_param_wr_to_wr_diff_chip (t_param_wr_to_wr_diff_chip ),
.t_param_wr_to_rd (t_param_wr_to_rd ),
.t_param_wr_to_rd_bc (t_param_wr_to_rd_bc ),
.t_param_wr_to_rd_diff_chip (t_param_wr_to_rd_diff_chip ),
.t_param_wr_to_pch (t_param_wr_to_pch ),
.t_param_wr_ap_to_valid (t_param_wr_ap_to_valid ),
.t_param_pch_to_valid (t_param_pch_to_valid ),
.t_param_pch_all_to_valid (t_param_pch_all_to_valid ),
.t_param_act_to_act_diff_bank (t_param_act_to_act_diff_bank ),
.t_param_four_act_to_act (t_param_four_act_to_act ),
.t_param_arf_to_valid (t_param_arf_to_valid ),
.t_param_pdn_to_valid (t_param_pdn_to_valid ),
.t_param_srf_to_valid (t_param_srf_to_valid ),
.t_param_srf_to_zq_cal (t_param_srf_to_zq_cal ),
.t_param_arf_period (t_param_arf_period ),
.t_param_pdn_period (t_param_pdn_period ),
.t_param_power_saving_exit (t_param_power_saving_exit ),
.t_param_mem_clk_entry_cycles (t_param_mem_clk_entry_cycles )
);
endmodule
|
module sky130_fd_sc_hd__a31oi (
Y ,
A1,
A2,
A3,
B1
);
// Module ports
output Y ;
input A1;
input A2;
input A3;
input B1;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire and0_out ;
wire nor0_out_Y;
// Name Output Other arguments
and and0 (and0_out , A3, A1, A2 );
nor nor0 (nor0_out_Y, B1, and0_out );
buf buf0 (Y , nor0_out_Y );
endmodule
|
module project (input wrEnable, input [4:0] wrReg, input [4:0] rdReg1, input [4:0] rdReg2, input clk, input [3:0] opCode, input [4:0] shiftAmt, output signed [31:0] result, input selCh, input [31:0] selData);
wire [31:0] selected;
wire signed [31:0] rdData1;
wire signed [31:0] rdData2;
registerFile regFile1 (wrEnable, wrReg, selected, rdReg1, rdData1, rdReg2, rdData2, clk);
alu alu1 (rdData1, rdData2, opCode, shiftAmt, result);
mux m1 (selCh, selData, result, selected);
endmodule
|
module project_tb;
reg wrEnable;
reg [4:0] wrReg;
reg [4:0] rdReg1;
reg [4:0] rdReg2;
reg clk;
reg [3:0] opCode;
reg [4:0] shiftAmt;
wire signed [31:0] result;
reg selCh;
reg [31:0] selData;
always begin #5 clk = ~clk; end
initial begin
$monitor ("Your result = %d", result);
clk = 0; selCh = 0;
#10 $display ("Register file's 1st register = 1."); wrEnable = 1; wrReg = 0; selData = 1;
#10 $display ("Register file's 2nd register = 7."); wrReg = 1; selData = 7; #10 wrEnable = 0;
#10 $display ("Choosing register file's 1st and 2nd registers as it's outputs, and adding both."); rdReg1 = 0; rdReg2 = 1; opCode = 0;
#10 $display ("Subtracting both."); opCode = 1;
#10 $display ("Changing 2nd register = 0 and subtrcating both again."); wrEnable = 1; selData = 0; #10 wrEnable = 0;
#10 $display ("Putting both registers at the terminals of an AND gate."); opCode = 2;
#10 $display ("Putting both registers at the terminals of an OR gate."); opCode = 3;
#10 $display ("Shifting 1st register's binary value 3 digits to the left."); shiftAmt = 3; opCode = 4;
#10 $display ("Register file's 1st register = last operation's answer, and shifting it's binary value 3 digits to the left."); wrEnable = 1; wrReg = 0; selCh = 1; #10 wrEnable = 0;
#10 $display ("Shifting 1st register's binary value 2 digits to the right logicaly."); shiftAmt = 2; opCode = 5;
#10 $display ("Changing 1st register = -9 and shifting it's binary value 2 digits to the right logicaly."); wrEnable = 1; wrReg = 0; selCh = 0; selData = -9; #10 wrEnable = 0; // It'll give an unrelated answer because of the negative number.
#10 $display ("Shifting 1st register's binary value 1 digits to the right arithmeticaly."); shiftAmt = 1; opCode = 6;
#10 $display ("Is 1st register's value greater than 2nd register's value?"); opCode = 7;
#10 $display ("Is 1st register's value less than 2nd register's value?"); opCode = 8;
end
project p1 (wrEnable, wrReg, rdReg1, rdReg2, clk, opCode, shiftAmt, result, selCh, selData);
endmodule
|
module aFifo_256x8
#(parameter DATA_WIDTH = 8,
ADDRESS_WIDTH = 8,
FIFO_DEPTH = (1 << ADDRESS_WIDTH))
//Reading port
(output reg [DATA_WIDTH-1:0] Data_out,
output reg Empty_out,
input wire ReadEn_in,
input wire RClk,
//Writing port.
input wire [DATA_WIDTH-1:0] Data_in,
output reg Full_out,
input wire WriteEn_in,
input wire WClk,
input wire Clear_in);
/////Internal connections & variables//////
reg [DATA_WIDTH-1:0] Mem [FIFO_DEPTH-1:0];
wire [ADDRESS_WIDTH-1:0] pNextWordToWrite, pNextWordToRead;
wire EqualAddresses;
wire NextWriteAddressEn, NextReadAddressEn;
wire Set_Status, Rst_Status;
reg Status;
wire PresetFull, PresetEmpty;
//////////////Code///////////////
//Data ports logic:
//(Uses a dual-port RAM).
//'Data_out' logic:
/* Begin Comment
always @ (posedge RClk)
if (ReadEn_in & !Empty_out)
Data_out <= Mem[pNextWordToRead];
//'Data_in' logic:
always @ (posedge WClk)
if (WriteEn_in & !Full_out)
Mem[pNextWordToWrite] <= Data_in;
End Comment */
// Synopsys SRAM memory usage A1: ReadPort , A2 : WritePort
wire [DATA_WIDTH-1:0] temp;
wire [DATA_WIDTH-1:0] Lsb_Data_out;
wire [DATA_WIDTH-1:0] Msb_Data_out;
wire read_LsbEn , read_MsbEn, write_MsbEn, write_Lsben;
assign read_LsbEn = ~pNextWordToRead[7];
assign read_MsbEn = pNextWordToRead[7];
assign write_LsbEn = ~pNextWordToWrite[7];
assign write_MsbEn = pNextWordToWrite[7];
assign Data_out = (read_LsbEn ? Lsb_Data_out : Msb_Data_out);
SRAM2RW128x8 INST_LSB_SRAM2RW128x8 (.A1(pNextWordToRead[6:0]),
.A2(pNextWordToWrite[6:0]),
.CE1(RClk & read_LsbEn),
.CE2(WClk & write_LsbEn),
.WEB1(ReadEn_in),
.WEB2(~WriteEn_in),
.OEB1(1'b0),
.OEB2(1'b1),
.CSB1(~ReadEn_in),
.CSB2(~WriteEn_in),
.I1(8'h00),
.I2(Data_in),
.O1(Lsb_Data_out),
.O2(temp));
SRAM2RW128x8 INST_MSB_SRAM2RW128x8 (.A1(pNextWordToRead[6:0]),
.A2(pNextWordToWrite[6:0]),
.CE1(RClk & read_MsbEn),
.CE2(WClk & write_MsbEn),
.WEB1(ReadEn_in),
.WEB2(~WriteEn_in),
.OEB1(1'b1),
.OEB2(1'b0),
.CSB1(~ReadEn_in),
.CSB2(~WriteEn_in),
.I1(8'h00),
.I2(Data_in),
.O1(Msb_Data_out),
.O2(temp));
//Fifo addresses support logic:
//'Next Addresses' enable logic:
assign NextWriteAddressEn = WriteEn_in & ~Full_out;
assign NextReadAddressEn = ReadEn_in & ~Empty_out;
//Addreses (Gray counters) logic:
GrayCounter #(ADDRESS_WIDTH) GrayCounter_pWr
(.GrayCount_out(pNextWordToWrite),
.Enable_in(NextWriteAddressEn),
.Clear_in(Clear_in),
.Clk(WClk)
);
GrayCounter #(ADDRESS_WIDTH) GrayCounter_pRd
(.GrayCount_out(pNextWordToRead),
.Enable_in(NextReadAddressEn),
.Clear_in(Clear_in),
.Clk(RClk)
);
//'EqualAddresses' logic:
assign EqualAddresses = (pNextWordToWrite == pNextWordToRead);
//'Quadrant selectors' logic:
assign Set_Status = (pNextWordToWrite[ADDRESS_WIDTH-2] ~^ pNextWordToRead[ADDRESS_WIDTH-1]) &
(pNextWordToWrite[ADDRESS_WIDTH-1] ^ pNextWordToRead[ADDRESS_WIDTH-2]);
assign Rst_Status = (pNextWordToWrite[ADDRESS_WIDTH-2] ^ pNextWordToRead[ADDRESS_WIDTH-1]) &
(pNextWordToWrite[ADDRESS_WIDTH-1] ~^ pNextWordToRead[ADDRESS_WIDTH-2]);
//'Status' latch logic:
always @ (Set_Status, Rst_Status, Clear_in) //D Latch w/ Asynchronous Clear & Preset.
if (Rst_Status | Clear_in)
Status = 0; //Going 'Empty'.
else if (Set_Status)
Status = 1; //Going 'Full'.
//'Full_out' logic for the writing port:
assign PresetFull = Status & EqualAddresses; //'Full' Fifo.
always @ (posedge WClk, posedge PresetFull) //D Flip-Flop w/ Asynchronous Preset.
if (PresetFull)
Full_out <= 1;
else
Full_out <= 0;
//'Empty_out' logic for the reading port:
assign PresetEmpty = ~Status & EqualAddresses; //'Empty' Fifo.
always @ (posedge RClk, posedge PresetEmpty) //D Flip-Flop w/ Asynchronous Preset.
if (PresetEmpty)
Empty_out <= 1;
else
Empty_out <= 0;
endmodule
|
module sdc_controller(
// WISHBONE common
wb_clk_i,
wb_rst_i,
// WISHBONE slave
wb_dat_i,
wb_dat_o,
wb_adr_i,
wb_sel_i,
wb_we_i,
wb_cyc_i,
wb_stb_i,
wb_ack_o,
// WISHBONE master
m_wb_dat_o,
m_wb_dat_i,
m_wb_adr_o,
m_wb_sel_o,
m_wb_we_o,
m_wb_cyc_o,
m_wb_stb_o,
m_wb_ack_i,
m_wb_cti_o,
m_wb_bte_o,
//SD BUS
sd_cmd_dat_i,
sd_cmd_out_o,
sd_cmd_oe_o,
//card_detect,
sd_dat_dat_i,
sd_dat_out_o,
sd_dat_oe_o,
sd_clk_o_pad,
sd_clk_i_pad,
int_cmd,
int_data
);
input wb_clk_i;
input wb_rst_i;
input [31:0] wb_dat_i;
output [31:0] wb_dat_o;
//input card_detect;
input [7:0] wb_adr_i;
input [3:0] wb_sel_i;
input wb_we_i;
input wb_cyc_i;
input wb_stb_i;
output wb_ack_o;
output [31:0] m_wb_adr_o;
output [3:0] m_wb_sel_o;
output m_wb_we_o;
input [31:0] m_wb_dat_i;
output [31:0] m_wb_dat_o;
output m_wb_cyc_o;
output m_wb_stb_o;
input m_wb_ack_i;
output [2:0] m_wb_cti_o;
output [1:0] m_wb_bte_o;
input wire [3:0] sd_dat_dat_i;
output wire [3:0] sd_dat_out_o;
output wire sd_dat_oe_o;
input wire sd_cmd_dat_i;
output wire sd_cmd_out_o;
output wire sd_cmd_oe_o;
output sd_clk_o_pad;
input wire sd_clk_i_pad;
output int_cmd, int_data;
//SD clock
wire sd_clk_o; //Sd_clk used in the system
wire [3:0] wr_wbm_sel;
wire [`BLKSIZE_W+`BLKCNT_W-1:0] xfersize;
wire [31:0] wbm_adr;
wire go_idle;
wire cmd_start_wb_clk;
wire cmd_start_sd_clk;
wire cmd_start;
wire [1:0] cmd_setting;
wire cmd_start_tx;
wire [39:0] cmd;
wire [119:0] cmd_response;
wire cmd_crc_ok;
wire cmd_index_ok;
wire cmd_finish;
wire d_write;
wire d_read;
wire [31:0] data_in_rx_fifo;
wire [31:0] data_out_tx_fifo;
wire start_tx_fifo;
wire start_rx_fifo;
wire tx_fifo_empty;
wire tx_fifo_full;
wire rx_fifo_full;
wire sd_data_busy;
wire data_busy;
wire data_crc_ok;
wire rd_fifo;
wire we_fifo;
wire data_start_rx;
wire data_start_tx;
wire cmd_int_rst_wb_clk;
wire cmd_int_rst_sd_clk;
wire cmd_int_rst;
wire data_int_rst_wb_clk;
wire data_int_rst_sd_clk;
wire data_int_rst;
//wb accessible registers
wire [31:0] argument_reg_wb_clk;
wire [`CMD_REG_SIZE-1:0] command_reg_wb_clk;
wire [`CMD_TIMEOUT_W-1:0] cmd_timeout_reg_wb_clk;
wire [`DATA_TIMEOUT_W-1:0] data_timeout_reg_wb_clk;
wire [0:0] software_reset_reg_wb_clk;
wire [31:0] response_0_reg_wb_clk;
wire [31:0] response_1_reg_wb_clk;
wire [31:0] response_2_reg_wb_clk;
wire [31:0] response_3_reg_wb_clk;
wire [`BLKSIZE_W-1:0] block_size_reg_wb_clk;
wire [0:0] controll_setting_reg_wb_clk;
wire [`INT_CMD_SIZE-1:0] cmd_int_status_reg_wb_clk;
wire [`INT_DATA_SIZE-1:0] data_int_status_reg_wb_clk;
wire [`INT_CMD_SIZE-1:0] cmd_int_enable_reg_wb_clk;
wire [`INT_DATA_SIZE-1:0] data_int_enable_reg_wb_clk;
wire [`BLKCNT_W-1:0] block_count_reg_wb_clk;
wire [31:0] dma_addr_reg_wb_clk;
wire [7:0] clock_divider_reg_wb_clk;
wire [31:0] argument_reg_sd_clk;
wire [`CMD_REG_SIZE-1:0] command_reg_sd_clk;
wire [`CMD_TIMEOUT_W-1:0] cmd_timeout_reg_sd_clk;
wire [`DATA_TIMEOUT_W-1:0] data_timeout_reg_sd_clk;
wire [0:0] software_reset_reg_sd_clk;
wire [31:0] response_0_reg_sd_clk;
wire [31:0] response_1_reg_sd_clk;
wire [31:0] response_2_reg_sd_clk;
wire [31:0] response_3_reg_sd_clk;
wire [`BLKSIZE_W-1:0] block_size_reg_sd_clk;
wire [0:0] controll_setting_reg_sd_clk;
wire [`INT_CMD_SIZE-1:0] cmd_int_status_reg_sd_clk;
wire [`INT_DATA_SIZE-1:0] data_int_status_reg_sd_clk;
wire [`BLKCNT_W-1:0] block_count_reg_sd_clk;
wire [1:0] dma_addr_reg_sd_clk;
wire [7:0] clock_divider_reg_sd_clk;
sd_clock_divider clock_divider0(
.CLK (sd_clk_i_pad),
.DIVIDER (clock_divider_reg_sd_clk),
.RST (wb_rst_i),
.SD_CLK (sd_clk_o)
);
assign sd_clk_o_pad = sd_clk_o ;
sd_cmd_master sd_cmd_master0(
.sd_clk (sd_clk_o),
.rst (wb_rst_i | software_reset_reg_sd_clk[0]),
.start_i (cmd_start_sd_clk),
.int_status_rst_i(cmd_int_rst_sd_clk),
.setting_o (cmd_setting),
.start_xfr_o (cmd_start_tx),
.go_idle_o (go_idle),
.cmd_o (cmd),
.response_i (cmd_response),
.crc_ok_i (cmd_crc_ok),
.index_ok_i (cmd_index_ok),
.busy_i (sd_data_busy),
.finish_i (cmd_finish),
.argument_i (argument_reg_sd_clk),
.command_i (command_reg_sd_clk),
.timeout_i (cmd_timeout_reg_sd_clk),
.int_status_o (cmd_int_status_reg_sd_clk),
.response_0_o (response_0_reg_sd_clk),
.response_1_o (response_1_reg_sd_clk),
.response_2_o (response_2_reg_sd_clk),
.response_3_o (response_3_reg_sd_clk)
);
sd_cmd_serial_host cmd_serial_host0(
.sd_clk (sd_clk_o),
.rst (wb_rst_i |
software_reset_reg_sd_clk[0] |
go_idle),
.setting_i (cmd_setting),
.cmd_i (cmd),
.start_i (cmd_start_tx),
.finish_o (cmd_finish),
.response_o (cmd_response),
.crc_ok_o (cmd_crc_ok),
.index_ok_o (cmd_index_ok),
.cmd_dat_i (sd_cmd_dat_i),
.cmd_out_o (sd_cmd_out_o),
.cmd_oe_o (sd_cmd_oe_o)
);
sd_data_master sd_data_master0(
.sd_clk (sd_clk_o),
.rst (wb_rst_i |
software_reset_reg_sd_clk[0]),
.start_tx_i (data_start_tx),
.start_rx_i (data_start_rx),
.timeout_i (data_timeout_reg_sd_clk),
.d_write_o (d_write),
.d_read_o (d_read),
.start_tx_fifo_o (start_tx_fifo),
.start_rx_fifo_o (start_rx_fifo),
.tx_fifo_empty_i (tx_fifo_empty),
.tx_fifo_full_i (tx_fifo_full),
.rx_fifo_full_i (rx_fifo_full),
.xfr_complete_i (!data_busy),
.crc_ok_i (data_crc_ok),
.int_status_o (data_int_status_reg_sd_clk),
.int_status_rst_i (data_int_rst_sd_clk)
);
sd_data_serial_host sd_data_serial_host0(
.sd_clk (sd_clk_o),
.rst (wb_rst_i | software_reset_reg_sd_clk[0]),
.data_in (data_out_tx_fifo),
.rd (rd_fifo),
.data_out (data_in_rx_fifo),
.we (we_fifo),
.DAT_oe_o (sd_dat_oe_o),
.DAT_dat_o (sd_dat_out_o),
.DAT_dat_i (sd_dat_dat_i),
.blksize (block_size_reg_sd_clk),
.bus_4bit (controll_setting_reg_sd_clk[0]),
.blkcnt (block_count_reg_sd_clk),
.start ({d_read, d_write}),
.byte_alignment (dma_addr_reg_sd_clk),
.sd_data_busy (sd_data_busy),
.busy (data_busy),
.crc_ok (data_crc_ok)
);
sd_fifo_filler sd_fifo_filler0(
.wb_clk (wb_clk_i),
.rst (wb_rst_i | software_reset_reg_sd_clk[0]),
.wbm_adr_o (wbm_adr),
.wbm_we_o (m_wb_we_o),
.wbm_dat_o (m_wb_dat_o),
.wbm_dat_i (m_wb_dat_i),
.wbm_cyc_o (m_wb_cyc_o),
.wbm_stb_o (m_wb_stb_o),
.wbm_ack_i (m_wb_ack_i),
.en_rx_i (start_rx_fifo),
.en_tx_i (start_tx_fifo),
.adr_i (dma_addr_reg_wb_clk),
.sd_clk (sd_clk_o),
.dat_i (data_in_rx_fifo),
.dat_o (data_out_tx_fifo),
.wr_i (we_fifo),
.rd_i (rd_fifo),
.sd_empty_o (tx_fifo_empty),
.sd_full_o (rx_fifo_full),
.wb_empty_o (),
.wb_full_o (tx_fifo_full)
);
assign xfersize = (block_size_reg_wb_clk + 1'b1) * (block_count_reg_wb_clk + 1'b1);
sd_wb_sel_ctrl sd_wb_sel_ctrl0(
.wb_clk (wb_clk_i),
.rst (wb_rst_i | software_reset_reg_sd_clk[0]),
.ena (start_rx_fifo),
.base_adr_i (dma_addr_reg_wb_clk),
.wbm_adr_i (wbm_adr),
.xfersize (xfersize),
.wbm_sel_o (wr_wbm_sel)
);
sd_data_xfer_trig sd_data_xfer_trig0 (
.sd_clk (sd_clk_o),
.rst (wb_rst_i | software_reset_reg_sd_clk[0]),
.cmd_with_data_start_i (cmd_start_sd_clk &
(command_reg_sd_clk[`CMD_WITH_DATA] !=
2'b00)),
.r_w_i (command_reg_sd_clk[`CMD_WITH_DATA] ==
2'b01),
.cmd_int_status_i (cmd_int_status_reg_sd_clk),
.start_tx_o (data_start_tx),
.start_rx_o (data_start_rx)
);
sd_controller_wb sd_controller_wb0(
.wb_clk_i (wb_clk_i),
.wb_rst_i (wb_rst_i),
.wb_dat_i (wb_dat_i),
.wb_dat_o (wb_dat_o),
.wb_adr_i (wb_adr_i),
.wb_sel_i (wb_sel_i),
.wb_we_i (wb_we_i),
.wb_stb_i (wb_stb_i),
.wb_cyc_i (wb_cyc_i),
.wb_ack_o (wb_ack_o),
.cmd_start (cmd_start),
.data_int_rst (data_int_rst),
.cmd_int_rst (cmd_int_rst),
.argument_reg (argument_reg_wb_clk),
.command_reg (command_reg_wb_clk),
.response_0_reg (response_0_reg_wb_clk),
.response_1_reg (response_1_reg_wb_clk),
.response_2_reg (response_2_reg_wb_clk),
.response_3_reg (response_3_reg_wb_clk),
.software_reset_reg (software_reset_reg_wb_clk),
.cmd_timeout_reg (cmd_timeout_reg_wb_clk),
.data_timeout_reg (data_timeout_reg_wb_clk),
.block_size_reg (block_size_reg_wb_clk),
.controll_setting_reg (controll_setting_reg_wb_clk),
.cmd_int_status_reg (cmd_int_status_reg_wb_clk),
.cmd_int_enable_reg (cmd_int_enable_reg_wb_clk),
.clock_divider_reg (clock_divider_reg_wb_clk),
.block_count_reg (block_count_reg_wb_clk),
.dma_addr_reg (dma_addr_reg_wb_clk),
.data_int_status_reg (data_int_status_reg_wb_clk),
.data_int_enable_reg (data_int_enable_reg_wb_clk)
);
//clock domain crossing regiters
//assign cmd_start_sd_clk = cmd_start_wb_clk;
//assign data_int_rst_sd_clk = data_int_rst_wb_clk;
//assign cmd_int_rst_sd_clk = cmd_int_rst_wb_clk;
//assign argument_reg_sd_clk = argument_reg_wb_clk;
//assign command_reg_sd_clk = command_reg_wb_clk;
//assign response_0_reg_wb_clk = response_0_reg_sd_clk;
//assign response_1_reg_wb_clk = response_1_reg_sd_clk;
//assign response_2_reg_wb_clk = response_2_reg_sd_clk;
//assign response_3_reg_wb_clk = response_3_reg_sd_clk;
//assign software_reset_reg_sd_clk = software_reset_reg_wb_clk;
//assign timeout_reg_sd_clk = timeout_reg_wb_clk;
//assign block_size_reg_sd_clk = block_size_reg_wb_clk;
//assign controll_setting_reg_sd_clk = controll_setting_reg_wb_clk;
//assign cmd_int_status_reg_wb_clk = cmd_int_status_reg_sd_clk;
//assign clock_divider_reg_sd_clk = clock_divider_reg_wb_clk;
//assign block_count_reg_sd_clk = block_count_reg_wb_clk;
//assign dma_addr_reg_sd_clk = dma_addr_reg_wb_clk;
//assign data_int_status_reg_wb_clk = data_int_status_reg_sd_clk;
edge_detect cmd_start_edge(.rst(wb_rst_i), .clk(wb_clk_i), .sig(cmd_start), .rise(cmd_start_wb_clk), .fall());
edge_detect data_int_rst_edge(.rst(wb_rst_i), .clk(wb_clk_i), .sig(data_int_rst), .rise(data_int_rst_wb_clk), .fall());
edge_detect cmd_int_rst_edge(.rst(wb_rst_i), .clk(wb_clk_i), .sig(cmd_int_rst), .rise(cmd_int_rst_wb_clk), .fall());
monostable_domain_cross cmd_start_cross(wb_rst_i, wb_clk_i, cmd_start_wb_clk, sd_clk_o, cmd_start_sd_clk);
monostable_domain_cross data_int_rst_cross(wb_rst_i, wb_clk_i, data_int_rst_wb_clk, sd_clk_o, data_int_rst_sd_clk);
monostable_domain_cross cmd_int_rst_cross(wb_rst_i, wb_clk_i, cmd_int_rst_wb_clk, sd_clk_o, cmd_int_rst_sd_clk);
bistable_domain_cross #(32) argument_reg_cross(wb_rst_i, wb_clk_i, argument_reg_wb_clk, sd_clk_o, argument_reg_sd_clk);
bistable_domain_cross #(`CMD_REG_SIZE) command_reg_cross(wb_rst_i, wb_clk_i, command_reg_wb_clk, sd_clk_o, command_reg_sd_clk);
bistable_domain_cross #(32) response_0_reg_cross(wb_rst_i, sd_clk_o, response_0_reg_sd_clk, wb_clk_i, response_0_reg_wb_clk);
bistable_domain_cross #(32) response_1_reg_cross(wb_rst_i, sd_clk_o, response_1_reg_sd_clk, wb_clk_i, response_1_reg_wb_clk);
bistable_domain_cross #(32) response_2_reg_cross(wb_rst_i, sd_clk_o, response_2_reg_sd_clk, wb_clk_i, response_2_reg_wb_clk);
bistable_domain_cross #(32) response_3_reg_cross(wb_rst_i, sd_clk_o, response_3_reg_sd_clk, wb_clk_i, response_3_reg_wb_clk);
bistable_domain_cross software_reset_reg_cross(wb_rst_i, wb_clk_i, software_reset_reg_wb_clk, sd_clk_o, software_reset_reg_sd_clk);
bistable_domain_cross #(`CMD_TIMEOUT_W) cmd_timeout_reg_cross(wb_rst_i, wb_clk_i, cmd_timeout_reg_wb_clk, sd_clk_o, cmd_timeout_reg_sd_clk);
bistable_domain_cross #(`DATA_TIMEOUT_W) data_timeout_reg_cross(wb_rst_i, wb_clk_i, data_timeout_reg_wb_clk, sd_clk_o, data_timeout_reg_sd_clk);
bistable_domain_cross #(`BLKSIZE_W) block_size_reg_cross(wb_rst_i, wb_clk_i, block_size_reg_wb_clk, sd_clk_o, block_size_reg_sd_clk);
bistable_domain_cross #(1) controll_setting_reg_cross(wb_rst_i, wb_clk_i, controll_setting_reg_wb_clk, sd_clk_o, controll_setting_reg_sd_clk);
bistable_domain_cross #(`INT_CMD_SIZE) cmd_int_status_reg_cross(wb_rst_i, sd_clk_o, cmd_int_status_reg_sd_clk, wb_clk_i, cmd_int_status_reg_wb_clk);
bistable_domain_cross #(8) clock_divider_reg_cross(wb_rst_i, wb_clk_i, clock_divider_reg_wb_clk, sd_clk_i_pad, clock_divider_reg_sd_clk);
bistable_domain_cross #(`BLKCNT_W) block_count_reg_cross(wb_rst_i, wb_clk_i, block_count_reg_wb_clk, sd_clk_o, block_count_reg_sd_clk);
bistable_domain_cross #(2) dma_addr_reg_cross(wb_rst_i, wb_clk_i, dma_addr_reg_wb_clk[1:0], sd_clk_o, dma_addr_reg_sd_clk);
bistable_domain_cross #(`INT_DATA_SIZE) data_int_status_reg_cross(wb_rst_i, sd_clk_o, data_int_status_reg_sd_clk, wb_clk_i, data_int_status_reg_wb_clk);
assign m_wb_cti_o = 3'b000;
assign m_wb_bte_o = 2'b00;
assign int_cmd = |(cmd_int_status_reg_wb_clk & cmd_int_enable_reg_wb_clk);
assign int_data = |(data_int_status_reg_wb_clk & data_int_enable_reg_wb_clk);
assign m_wb_sel_o = m_wb_cyc_o & m_wb_we_o ? wr_wbm_sel : 4'b1111;
assign m_wb_adr_o = {wbm_adr[31:2], 2'b00};
endmodule
|
module hw2_A (
input in,
input clk,
input rst_n,
output reg out
);
parameter S0 = 0;
parameter S1 = 1;
reg state, nextState;
reg tmp_out;
always @(posedge clk or negedge rst_n) begin
if (~rst_n) begin
state <= S0;
end else begin
state <= nextState;
end // end of if-else block
end // end of always
// next state
always @(*) begin
case (state)
S0: begin // previous input is 0
if (in == 0) begin // 0 -> 0 => 0
nextState <= 0;
end else begin // 0 -> 1 => 1
nextState <= 1;
end
end
S1: begin // previous input is 1
if (in == 0) begin // 1 -> 0 => 0
nextState <= 0;
end else begin // 1 -> 1 => 0;
nextState <= 1;
end
end
endcase
end
// output
always @(*) begin
case (state)
S0: begin // previous input is 0
if (in == 0) begin // 0 -> 0 => 0
tmp_out <= 0;
end else begin // 0 -> 1 => 1
tmp_out <= 1;
end
end
S1: begin // previous input is 1
tmp_out <= 0;
end
endcase
end
always @(posedge clk or negedge rst_n) begin
if(~rst_n) begin
out <= 0;
end else begin
out <= tmp_out;
end
end
endmodule
|
module sky130_fd_sc_lp__isobufsrc (
X ,
SLEEP,
A
);
// Module ports
output X ;
input SLEEP;
input A ;
// Local signals
wire not0_out ;
wire and0_out_X;
// Name Output Other arguments
not not0 (not0_out , SLEEP );
and and0 (and0_out_X, not0_out, A );
buf buf0 (X , and0_out_X );
endmodule
|
module SPI#
(
parameter integer m = 15, // Data packet size
parameter integer Tbit = 100 // Clocks for 1 bit
)
(
// External interfaces
output reg [127:0] str0 = " ",
output reg [127:0] str1 = " ",
output reg [127:0] str2 = " ",
output reg [127:0] str3 = " ",
input wire GCLK,
input wire RST,
input wire [7:0] SW,
// Transmission start switch
input wire st,
// SPI Master bus
input wire MASTER_MISO,
output wire MASTER_MOSI,
output wire MASTER_SS,
output wire MASTER_SCLK,
// SPI Slave bus
input wire SLAVE_MOSI,
output wire SLAVE_MISO,
input wire SLAVE_SS,
input wire SLAVE_SCLK
);
// I/O buffers
wire [m-1:0] MASTER_RX;
reg [m-1:0] MASTER_TX = 15'b010110000110110;
wire [m-1:0] SLAVE_RX;
reg [m-1:0] SLAVE_TX = 15'b110101100110110;
wire clk_Tbit; // Clock for bit timing
SPI_MASTER #(.m(m)) spi_master
(
.clk(GCLK),
.ce(clk_Tbit),
.st(st),
.SCLK(MASTER_SCLK),
.MISO(MASTER_MISO),
.MOSI(MASTER_MOSI),
.LOAD(MASTER_SS),
.TX_MD(MASTER_TX),
.RX_SD(MASTER_RX),
.RST(RST),
.LEFT(1'b1),
.R(1'b1)
);
SPI_SLAVE #(.m(m)) spi_slave
(
.GCLK(GCLK),
.RST(RST),
.SCLK(SLAVE_SCLK),
.MISO(SLAVE_MISO),
.MOSI(SLAVE_MOSI),
.SS(SLAVE_SS),
.DIN(SLAVE_TX),
.DOUT(SLAVE_RX)
);
CLK_DIV clk_div
(
.GCLK(GCLK),
.out(clk_Tbit),
.T(Tbit)
);
// Display
wire [127:0] str_m_tx;
wire [127:0] str_s_tx;
wire [127:0] str_m_rx;
wire [127:0] str_s_rx;
always @(posedge clk_Tbit) begin
if (SW[6] == 1'b1) begin
str0 <= "SPI Interface ";
str1 <= SW[7] ? " M-R TX/SLAVE RX" : " SLAVE TX/M-R RX";
str2 <= SW[7] ? str_m_tx : str_s_tx;
str3 <= SW[7] ? str_s_rx : str_m_rx;
end
end
D2STR_B #(.len(m)) oled_d2b_0
(
.str(str_m_tx),
.d(MASTER_TX)
);
D2STR_B #(.len(m)) oled_d2b_1
(
.str(str_s_tx),
.d(SLAVE_TX)
);
D2STR_B #(.len(m)) oled_d2b_2
(
.str(str_m_rx),
.d(MASTER_RX)
);
D2STR_B #(.len(m)) oled_d2b_3
(
.str(str_s_rx),
.d(SLAVE_RX)
);
endmodule
|
module sky130_fd_sc_hs__dlxtp (
Q ,
D ,
GATE,
VPWR,
VGND
);
// Module ports
output Q ;
input D ;
input GATE;
input VPWR;
input VGND;
// Local signals
wire buf_Q GATE_delayed;
wire buf_Q D_delayed ;
reg notifier ;
wire buf_Q ;
wire awake ;
// Name Output Other arguments
sky130_fd_sc_hs__u_dl_p_no_pg u_dl_p_no_pg0 (buf_Q , D_delayed, GATE_delayed, notifier, VPWR, VGND);
buf buf0 (Q , buf_Q );
assign awake = ( VPWR === 1'b1 );
endmodule
|
module or1200_spram_512x20(
`ifdef OR1200_BIST
// RAM BIST
mbist_si_i, mbist_so_o, mbist_ctrl_i,
`endif
// Generic synchronous single-port RAM interface
clk, rst, ce, we, oe, addr, di, doq
);
//
// Default address and data buses width
//
//aw was set to 9 which is not consistent with other parameters.
parameter aw = `OR1200_DCTAG;
//dw was set to 20 instead of using the globla settings. Not sure why
parameter dw = `OR1200_DCTAG_W;
`ifdef OR1200_BIST
//
// RAM BIST
//
input mbist_si_i;
input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
output mbist_so_o;
`endif
//
// Generic synchronous single-port RAM interface
//
input clk; // Clock
input rst; // Reset
input ce; // Chip enable input
input we; // Write enable input
input oe; // Output enable input
input [aw-1:0] addr; // address bus inputs
input [dw-1:0] di; // input data bus
output [dw-1:0] doq; // output data bus
//
// Internal wires and registers
//
`ifdef OR1200_XILINX_RAMB4
wire [3:0] unconnected;
`else
`ifdef OR1200_XILINX_RAMB16
wire [11:0] unconnected;
reg [dw-1:0] di_reg;
reg [aw-1:0] addr_reg;
reg [dw-1:0] ram [(2**aw)-1:0];
reg [dw-1:0] dout;
`endif // !OR1200_XILINX_RAMB16
`endif // !OR1200_XILINX_RAMB4
`ifdef OR1200_ARTISAN_SSP
`else
`ifdef OR1200_VIRTUALSILICON_SSP
`else
`ifdef OR1200_BIST
assign mbist_so_o = mbist_si_i;
`endif
`endif
`endif
`ifdef OR1200_ARTISAN_SSP
//
// Instantiation of ASIC memory:
//
// Artisan Synchronous Single-Port RAM (ra1sh)
//
`ifdef UNUSED
art_hssp_512x20 #(dw, 1<<aw, aw) artisan_ssp(
`else
`ifdef OR1200_BIST
art_hssp_512x20_bist artisan_ssp(
`else
art_hssp_512x20 artisan_ssp(
`endif
`endif
`ifdef OR1200_BIST
// RAM BIST
.mbist_si_i(mbist_si_i),
.mbist_so_o(mbist_so_o),
.mbist_ctrl_i(mbist_ctrl_i),
`endif
.CLK(clk),
.CEN(~ce),
.WEN(~we),
.A(addr),
.D(di),
.OEN(~oe),
.Q(doq)
);
`else
`ifdef OR1200_AVANT_ATP
//
// Instantiation of ASIC memory:
//
// Avant! Asynchronous Two-Port RAM
//
avant_atp avant_atp(
.web(~we),
.reb(),
.oeb(~oe),
.rcsb(),
.wcsb(),
.ra(addr),
.wa(addr),
.di(di),
.doq(doq)
);
`else
`ifdef OR1200_VIRAGE_SSP
//
// Instantiation of ASIC memory:
//
// Virage Synchronous 1-port R/W RAM
//
virage_ssp virage_ssp(
.clk(clk),
.adr(addr),
.d(di),
.we(we),
.oe(oe),
.me(ce),
.q(doq)
);
`else
`ifdef OR1200_VIRTUALSILICON_SSP
//
// Instantiation of ASIC memory:
//
// Virtual Silicon Single-Port Synchronous SRAM
//
`ifdef UNUSED
vs_hdsp_512x20 #(1<<aw, aw-1, dw-1) vs_ssp(
`else
`ifdef OR1200_BIST
vs_hdsp_512x20_bist vs_ssp(
`else
vs_hdsp_512x20 vs_ssp(
`endif
`endif
`ifdef OR1200_BIST
// RAM BIST
.mbist_si_i(mbist_si_i),
.mbist_so_o(mbist_so_o),
.mbist_ctrl_i(mbist_ctrl_i),
`endif
.CK(clk),
.ADR(addr),
.DI(di),
.WEN(~we),
.CEN(~ce),
.OEN(~oe),
.DOUT(doq)
);
`else
`ifdef OR1200_XILINX_RAMB4
//
// Instantiation of FPGA memory:
//
// Virtex/Spartan2
//
//
// Block 0
//
RAMB4_S8 ramb4_s8_0(
.CLK(clk),
.RST(rst),
.ADDR(addr),
.DI(di[7:0]),
.EN(ce),
.WE(we),
.DO(doq[7:0])
);
//
// Block 1
//
RAMB4_S8 ramb4_s8_1(
.CLK(clk),
.RST(rst),
.ADDR(addr),
.DI(di[15:8]),
.EN(ce),
.WE(we),
.DO(doq[15:8])
);
//
// Block 2
//
RAMB4_S8 ramb4_s8_2(
.CLK(clk),
.RST(rst),
.ADDR(addr),
.DI({4'b0000, di[19:16]}),
.EN(ce),
.WE(we),
.DO({unconnected, doq[19:16]})
);
`else
`ifdef OR1200_XILINX_RAMB16
//
// Instantiation of FPGA memory:
//
// Virtex4/Spartan3E
//
// Added By Nir Mor
//
//convert to an inferrend ram
/*
RAMB16_S36 ramb16_s36(
.CLK(clk),
.SSR(rst),
.ADDR(addr),
.DI({12'h000,di}),
.DIP(4'h0),
.EN(ce),
.WE(we),
.DO({unconnected,doq}),
.DOP()
);
*/
always @(posedge clk)
if (we)
di_reg <= di;
always @(posedge clk)
addr_reg <= addr;
assign doq = dout;
always @(posedge clk)
if (we)
ram[addr_reg] <= di_reg;
generate
begin: dist_ram
reg [dw-1:0] ram_out;
always @(posedge clk)
dout <= ram[addr_reg];
// always @*
// ram_out = ram[addr_reg];
end
endgenerate
`else
`ifdef OR1200_ALTERA_LPM
//
// Instantiation of FPGA memory:
//
// Altera LPM
//
// Added By Jamil Khatib
//
wire wr;
assign wr = ce & we;
initial $display("Using Altera LPM.");
lpm_ram_dq lpm_ram_dq_component (
.address(addr),
.inclock(clk),
.outclock(clk),
.data(di),
.we(wr),
.q(doq)
);
defparam lpm_ram_dq_component.lpm_width = dw,
lpm_ram_dq_component.lpm_widthad = aw,
lpm_ram_dq_component.lpm_indata = "REGISTERED",
lpm_ram_dq_component.lpm_address_control = "REGISTERED",
lpm_ram_dq_component.lpm_outdata = "UNREGISTERED",
lpm_ram_dq_component.lpm_hint = "USE_EAB=ON";
// examplar attribute lpm_ram_dq_component NOOPT TRUE
`else
//
// Generic single-port synchronous RAM model
//
//
// Generic RAM's registers and wires
//
reg [dw-1:0] mem [(1<<aw)-1:0]; // RAM content
reg [aw-1:0] addr_reg; // RAM address register
//
// Data output drivers
//
assign doq = (oe) ? mem[addr_reg] : {dw{1'b0}};
//
// RAM address register
//
always @(posedge clk or posedge rst)
if (rst)
addr_reg <= #1 {aw{1'b0}};
else if (ce)
addr_reg <= #1 addr;
//
// RAM write
//
always @(posedge clk)
if (ce && we)
mem[addr] <= #1 di;
`endif // !OR1200_ALTERA_LPM
`endif // !OR1200_XILINX_RAMB16
`endif // !OR1200_XILINX_RAMB4
`endif // !OR1200_VIRTUALSILICON_SSP
`endif // !OR1200_VIRAGE_SSP
`endif // !OR1200_AVANT_ATP
`endif // !OR1200_ARTISAN_SSP
endmodule
|
module sky130_fd_sc_hd__fa (
//# {{data|Data Signals}}
input A ,
input B ,
input CIN ,
output COUT,
output SUM
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
|
module serdes_1_to_n_clk_pll_s16_diff (clkin_p, clkin_n, rxioclk, rx_serdesstrobe, reset, pattern1, rx_bufg_pll_x1, rx_bufg_pll_x2, bitslip, rx_toggle, rx_bufpll_lckd, datain) ;
parameter integer S = 16 ; // Parameter to set the serdes factor 10,12,14,16
parameter integer BS = "FALSE" ; // Parameter to enable bitslip TRUE or FALSE
parameter PLLX = 2 ; // Parameter to set multiplier for PLL
parameter PLLD = 1 ; // Parameter to set divider for PLL
parameter real CLKIN_PERIOD = 6.000 ;// clock period (ns) of input clock on clkin_p
parameter DIFF_TERM = "FALSE" ; // Parameter to enable internal differential termination
input clkin_p ; // Input from LVDS receiver pin
input clkin_n ; // Input from LVDS receiver pin
output rxioclk ; // IO Clock network
output rx_serdesstrobe ; // Parallel data capture strobe
input reset ; // Reset
input [S-1:0] pattern1 ; // Data to define pattern that bitslip should search for
output rx_bufg_pll_x1 ; // Global clock
output rx_bufg_pll_x2 ; // Global clock x2
output bitslip ; // Bitslip control line
output rx_toggle ; // Control line to data receiver
output rx_bufpll_lckd ; // BUFPLL locked
output [S-1:0] datain ; // Output data
wire P_clk; // P clock out to BUFIO2
wire pll_fb_clk; // PLL feedback clock into BUFIOFB
wire ddly_m; // Master output from IODELAY1
wire ddly_s; // Slave output from IODELAY1
wire [7:0] mdataout ; //
wire busys ; //
wire busym ; //
wire feedback ; //
wire rx_clk_in ; //
reg bslip ; //
reg [S-1:0] clk_iserdes_data ; //
wire [S/2-1:0] clk_iserdes_data_int ; //
reg [3:0] state ; //
reg cal_clk ; //
reg rst_clk ; //
wire not_rx_bufpll_lckd ; //
reg [11:0] counter ;
reg [S/2-1:0] clkh ;
reg busyd ; //
reg [3:0] count ;
reg rx_toggle_int ; //
reg enable ; //
parameter RX_SWAP_CLK = 1'b0 ; // pinswap mask for input clock (0 = no swap (default), 1 = swap). Allows input to be connected the wrong way round to ease PCB routing.
assign busy_clk = busym ;
assign datain = clk_iserdes_data ;
assign rx_toggle = rx_toggle_int ;
// Bitslip and CAL state machine
assign bitslip = bslip ;
always @ (posedge rx_bufg_pll_x1)
begin
clk_iserdes_data <= {clk_iserdes_data_int, clkh} ;
end
always @ (posedge rx_bufg_pll_x2 or posedge not_rx_bufpll_lckd)
if (not_rx_bufpll_lckd == 1'b1) begin
rx_toggle_int <= 1'b0 ;
end
else begin
if (rx_toggle_int == 1'b1) begin // check gearbox is in the right phase
clkh <= clk_iserdes_data_int ;
if (clk_iserdes_data_int == pattern1[S-1 : S/2] && count == 4'hF) begin
rx_toggle_int <= rx_toggle_int ;
end
else begin
rx_toggle_int <= ~rx_toggle_int ;
end
end
else begin
rx_toggle_int <= ~rx_toggle_int ;
end
end
always @ (posedge rx_bufg_pll_x2 or posedge not_rx_bufpll_lckd)
begin
if (not_rx_bufpll_lckd == 1'b1) begin
state <= 0 ;
enable <= 1'b0 ;
cal_clk <= 1'b0 ;
rst_clk <= 1'b0 ;
bslip <= 1'b0 ;
busyd <= 1'b1 ;
counter <= 12'b000000000000 ;
end
else begin
busyd <= busy_clk ;
if (counter[5] == 1'b1) begin
enable <= 1'b1 ;
end
if (counter[11] == 1'b1) begin // re calibrate every 2^11 clocks
state <= 0 ;
cal_clk <= 1'b0 ;
rst_clk <= 1'b0 ;
bslip <= 1'b0 ;
busyd <= 1'b1 ;
counter <= 12'b000000000000 ;
end
else begin
counter <= counter + 12'b000000000001 ;
if (state == 0 && enable == 1'b1 && busyd == 1'b0) begin
state <= 1 ;
end
else if (state == 1) begin // cal high
cal_clk <= 1'b1 ; state <= 2 ;
end
else if (state == 2 && busyd == 1'b1) begin // wait for busy high
cal_clk <= 1'b0 ; state <= 3 ; // cal low
end
else if (state == 3 && busyd == 1'b0) begin // wait for busy low
rst_clk <= 1'b1 ; state <= 4 ; // rst high
end
else if (state == 4) begin // rst low
rst_clk <= 1'b0 ; state <= 5 ;
end
else if (state == 5 && busyd == 1'b0) begin // wait for busy low
state <= 6 ;
count <= 3'b000 ;
end
else if (state == 6) begin // hang around
count <= count + 3'b001 ;
if (count == 3'b111) begin
state <= 7 ;
end
end
else if (state == 7) begin
if (BS == "TRUE" && clk_iserdes_data != pattern1) begin
bslip <= 1'b1 ; // bitslip needed
state <= 8 ;
count <= 3'b000 ;
end
else begin
state <= 9 ;
end
end
else if (state == 8) begin
bslip <= 1'b0 ; // bitslip low
count <= count + 3'b001 ;
if (count == 3'b111) begin
state <= 7 ;
end
end
else if (state == 9) begin
state <= 9 ;
end
end
end
end
IBUFGDS #(
.DIFF_TERM (DIFF_TERM))
iob_clk_in (
.I (clkin_p),
.IB (clkin_n),
.O (rx_clk_in));
assign iob_data_in = rx_clk_in ^ RX_SWAP_CLK ; // Invert clock as required
genvar i ; // Limit the output data bus to the most significant 'S' number of bits
generate
for (i = 0 ; i <= (S/2 - 1) ; i = i + 1)
begin : loop0
assign clk_iserdes_data_int[i] = mdataout[8+i-S/2] ;
end
endgenerate
IODELAY2 #(
.DATA_RATE ("SDR"), // <SDR>, DDR
.SIM_TAPDELAY_VALUE (49), // nominal tap delay (sim parameter only)
.IDELAY_VALUE (0), // {0 ... 255}
.IDELAY2_VALUE (0), // {0 ... 255}
.ODELAY_VALUE (0), // {0 ... 255}
.IDELAY_MODE ("NORMAL"), // "NORMAL", "PCI"
.SERDES_MODE ("MASTER"), // <NONE>, MASTER, SLAVE
.IDELAY_TYPE ("VARIABLE_FROM_HALF_MAX"), // "DEFAULT", "DIFF_PHASE_DETECTOR", "FIXED", "VARIABLE_FROM_HALF_MAX", "VARIABLE_FROM_ZERO"
.COUNTER_WRAPAROUND ("STAY_AT_LIMIT"), // <STAY_AT_LIMIT>, WRAPAROUND
.DELAY_SRC ("IDATAIN")) // "IO", "IDATAIN", "ODATAIN"
iodelay_m (
.IDATAIN (iob_data_in), // data from master IOB
.TOUT (), // tri-state signal to IOB
.DOUT (), // output data to IOB
.T (1'b1), // tri-state control from OLOGIC/OSERDES2
.ODATAIN (1'b0), // data from OLOGIC/OSERDES2
.DATAOUT (ddly_m), // Output data 1 to ILOGIC/ISERDES2
.DATAOUT2 (), // Output data 2 to ILOGIC/ISERDES2
.IOCLK0 (rxioclk), // High speed clock for calibration
.IOCLK1 (1'b0), // High speed clock for calibration
.CLK (rx_bufg_pll_x2), // Fabric clock (GCLK) for control signals
.CAL (cal_clk), // Calibrate enable signal
.INC (1'b0), // Increment counter
.CE (1'b0), // Clock Enable
.RST (rst_clk), // Reset delay line to 1/2 max in this case
.BUSY (busym)) ; // output signal indicating sync circuit has finished / calibration has finished
IODELAY2 #(
.DATA_RATE ("SDR"), // <SDR>, DDR
.SIM_TAPDELAY_VALUE (49), // nominal tap delay (sim parameter only)
.IDELAY_VALUE (0), // {0 ... 255}
.IDELAY2_VALUE (0), // {0 ... 255}
.ODELAY_VALUE (0), // {0 ... 255}
.IDELAY_MODE ("NORMAL"), // "NORMAL", "PCI"
.SERDES_MODE ("SLAVE"), // <NONE>, MASTER, SLAVE
.IDELAY_TYPE ("FIXED"), // "DEFAULT", "DIFF_PHASE_DETECTOR", "FIXED", "VARIABLE_FROM_HALF_MAX", "VARIABLE_FROM_ZERO"
.COUNTER_WRAPAROUND ("STAY_AT_LIMIT"), // <STAY_AT_LIMIT>, WRAPAROUND
.DELAY_SRC ("IDATAIN")) // "IO", "IDATAIN", "ODATAIN"
iodelay_s (
.IDATAIN (iob_data_in), // data from slave IOB
.TOUT (), // tri-state signal to IOB
.DOUT (), // output data to IOB
.T (1'b1), // tri-state control from OLOGIC/OSERDES2
.ODATAIN (1'b0), // data from OLOGIC/OSERDES2
.DATAOUT (ddly_s), // Output data 1 to ILOGIC/ISERDES2
.DATAOUT2 (), // Output data 2 to ILOGIC/ISERDES2
.IOCLK0 (1'b0), // High speed clock for calibration
.IOCLK1 (1'b0), // High speed clock for calibration
.CLK (1'b0), // Fabric clock (GCLK) for control signals
.CAL (1'b0), // Calibrate control signal, never needed as the slave supplies the clock input to the PLL
.INC (1'b0), // Increment counter
.CE (1'b0), // Clock Enable
.RST (1'b0), // Reset delay line
.BUSY ()) ; // output signal indicating sync circuit has finished / calibration has finished
BUFIO2 #(
.DIVIDE (1), // The DIVCLK divider divide-by value; default 1
.DIVIDE_BYPASS ("TRUE")) // DIVCLK output sourced from Divider (FALSE) or from I input, by-passing Divider (TRUE); default TRUE
P_clk_bufio2_inst (
.I (P_clk), // P_clk input from IDELAY via DFB pin
.IOCLK (), // Output Clock
.DIVCLK (buf_P_clk), // Output Divided Clock
.SERDESSTROBE ()) ; // Output SERDES strobe (Clock Enable)
BUFIO2FB #(
.DIVIDE_BYPASS ("TRUE")) // DIVCLK output sourced from Divider (FALSE) or from I input, by-passing Divider (TRUE); default TRUE
P_clk_bufio2fb_inst (
.I (feedback), // PLL generated 945 MHz Clock to be fed back from IOI
.O (buf_pll_fb_clk)) ; // PLL Output Feedback Clock
ISERDES2 #(
.DATA_WIDTH (S/2), // SERDES word width. This should match the setting in BUFPLL
.DATA_RATE ("SDR"), // <SDR>, DDR
.BITSLIP_ENABLE ("TRUE"), // <FALSE>, TRUE
.SERDES_MODE ("MASTER"), // <DEFAULT>, MASTER, SLAVE
.INTERFACE_TYPE ("RETIMED")) // NETWORKING, NETWORKING_PIPELINED, <RETIMED>
iserdes_m (
.D (ddly_m),
.CE0 (1'b1),
.CLK0 (rxioclk),
.CLK1 (1'b0),
.IOCE (rx_serdesstrobe),
.RST (reset),
.CLKDIV (rx_bufg_pll_x2),
.SHIFTIN (pd_edge),
.BITSLIP (bitslip),
.FABRICOUT (),
.DFB (),
.CFB0 (),
.CFB1 (),
.Q4 (mdataout[7]),
.Q3 (mdataout[6]),
.Q2 (mdataout[5]),
.Q1 (mdataout[4]),
.VALID (),
.INCDEC (),
.SHIFTOUT (cascade));
ISERDES2 #(
.DATA_WIDTH (S/2), // SERDES word width. This should match the setting is BUFPLL
.DATA_RATE ("SDR"), // <SDR>, DDR
.BITSLIP_ENABLE ("TRUE"), // <FALSE>, TRUE
.SERDES_MODE ("SLAVE"), // <DEFAULT>, MASTER, SLAVE
.INTERFACE_TYPE ("RETIMED")) // NETWORKING, NETWORKING_PIPELINED, <RETIMED>
iserdes_s (
.D (ddly_s),
.CE0 (1'b1),
.CLK0 (rxioclk),
.CLK1 (1'b0),
.IOCE (rx_serdesstrobe),
.RST (reset),
.CLKDIV (rx_bufg_pll_x2),
.SHIFTIN (cascade),
.BITSLIP (bitslip),
.FABRICOUT (),
.DFB (P_clk),
.CFB0 (feedback),
.CFB1 (),
.Q4 (mdataout[3]),
.Q3 (mdataout[2]),
.Q2 (mdataout[1]),
.Q1 (mdataout[0]),
.VALID (),
.INCDEC (),
.SHIFTOUT (pd_edge));
PLL_ADV #(
.BANDWIDTH ("OPTIMIZED"), // "high", "low" or "optimized"
.CLKFBOUT_MULT (PLLX), // multiplication factor for all output clocks
.CLKFBOUT_PHASE (0.0), // phase shift (degrees) of all output clocks
.CLKIN1_PERIOD (CLKIN_PERIOD), // clock period (ns) of input clock on clkin1
.CLKIN2_PERIOD (CLKIN_PERIOD), // clock period (ns) of input clock on clkin2
.CLKOUT0_DIVIDE (1), // division factor for clkout0 (1 to 128)
.CLKOUT0_DUTY_CYCLE (0.5), // duty cycle for clkout0 (0.01 to 0.99)
.CLKOUT0_PHASE (0.0), // phase shift (degrees) for clkout0 (0.0 to 360.0)
.CLKOUT1_DIVIDE (S/2), // division factor for clkout1 (1 to 128)
.CLKOUT1_DUTY_CYCLE (0.5), // duty cycle for clkout1 (0.01 to 0.99)
.CLKOUT1_PHASE (0.0), // phase shift (degrees) for clkout1 (0.0 to 360.0)
.CLKOUT2_DIVIDE (S), // division factor for clkout2 (1 to 128)
.CLKOUT2_DUTY_CYCLE (0.5), // duty cycle for clkout2 (0.01 to 0.99)
.CLKOUT2_PHASE (0.0), // phase shift (degrees) for clkout2 (0.0 to 360.0)
.CLKOUT3_DIVIDE (7), // division factor for clkout3 (1 to 128)
.CLKOUT3_DUTY_CYCLE (0.5), // duty cycle for clkout3 (0.01 to 0.99)
.CLKOUT3_PHASE (0.0), // phase shift (degrees) for clkout3 (0.0 to 360.0)
.CLKOUT4_DIVIDE (7), // division factor for clkout4 (1 to 128)
.CLKOUT4_DUTY_CYCLE (0.5), // duty cycle for clkout4 (0.01 to 0.99)
.CLKOUT4_PHASE (0.0), // phase shift (degrees) for clkout4 (0.0 to 360.0)
.CLKOUT5_DIVIDE (7), // division factor for clkout5 (1 to 128)
.CLKOUT5_DUTY_CYCLE (0.5), // duty cycle for clkout5 (0.01 to 0.99)
.CLKOUT5_PHASE (0.0), // phase shift (degrees) for clkout5 (0.0 to 360.0)
.COMPENSATION ("SOURCE_SYNCHRONOUS"), // "SYSTEM_SYNCHRONOUS", "SOURCE_SYNCHRONOUS", "INTERNAL", "EXTERNAL", "DCM2PLL", "PLL2DCM"
.DIVCLK_DIVIDE (PLLD), // division factor for all clocks (1 to 52)
.CLK_FEEDBACK ("CLKOUT0"), //
.REF_JITTER (0.100)) // input reference jitter (0.000 to 0.999 ui%)
rx_pll_adv_inst (
.CLKFBDCM (), // output feedback signal used when pll feeds a dcm
.CLKFBOUT (), // general output feedback signal
.CLKOUT0 (rx_pllout_xs), // xS clock for receiver
.CLKOUT1 (rx_pllout_x2), //
.CLKOUT2 (rx_pllout_x1), // x1 clock for BUFG
.CLKOUT3 (), // one of six general clock output signals
.CLKOUT4 (), // one of six general clock output signals
.CLKOUT5 (), // one of six general clock output signals
.CLKOUTDCM0 (), // one of six clock outputs to connect to the dcm
.CLKOUTDCM1 (), // one of six clock outputs to connect to the dcm
.CLKOUTDCM2 (), // one of six clock outputs to connect to the dcm
.CLKOUTDCM3 (), // one of six clock outputs to connect to the dcm
.CLKOUTDCM4 (), // one of six clock outputs to connect to the dcm
.CLKOUTDCM5 (), // one of six clock outputs to connect to the dcm
.DO (), // dynamic reconfig data output (16-bits)
.DRDY (), // dynamic reconfig ready output
.LOCKED (rx_pll_lckd), // active high pll lock signal
.CLKFBIN (buf_pll_fb_clk), // clock feedback input
.CLKIN1 (buf_P_clk), // primary clock input
.CLKIN2 (1'b0), // secondary clock input
.CLKINSEL (1'b1), // selects '1' = clkin1, '0' = clkin2
.DADDR (5'b00000), // dynamic reconfig address input (5-bits)
.DCLK (1'b0), // dynamic reconfig clock input
.DEN (1'b0), // dynamic reconfig enable input
.DI (16'h0000), // dynamic reconfig data input (16-bits)
.DWE (1'b0), // dynamic reconfig write enable input
.RST (reset), // asynchronous pll reset
.REL (1'b0)) ; // used to force the state of the PFD outputs (test only)
BUFG bufg_pll_x1 (.I(rx_pllout_x1), .O(rx_bufg_pll_x1) ) ;
BUFG bufg_pll_x2 (.I(rx_pllout_x2), .O(rx_bufg_pll_x2) ) ;
BUFPLL #(
.DIVIDE (S/2)) // PLLIN0 divide-by value to produce SERDESSTROBE (1 to 8); default 1
rx_bufpll_inst (
.PLLIN (rx_pllout_xs), // PLL Clock input
.GCLK (rx_bufg_pll_x2), // Global Clock input
.LOCKED (rx_pll_lckd), // Clock0 locked input
.IOCLK (rxioclk), // Output PLL Clock
.LOCK (rx_bufplllckd), // BUFPLL Clock and strobe locked
.SERDESSTROBE (rx_serdesstrobe)) ; // Output SERDES strobe
assign rx_bufpll_lckd = rx_pll_lckd & rx_bufplllckd ;
assign not_rx_bufpll_lckd = ~rx_bufpll_lckd ;
endmodule
|
module sky130_fd_sc_lp__dlygate4s50 (
X,
A
);
// Module ports
output X;
input A;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire buf0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X, A );
buf buf1 (X , buf0_out_X );
endmodule
|
module sky130_fd_sc_hdll__and3_2 (
X ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__and3 base (
.X(X),
.A(A),
.B(B),
.C(C),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
|
module sky130_fd_sc_hdll__and3_2 (
X,
A,
B,
C
);
output X;
input A;
input B;
input C;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__and3 base (
.X(X),
.A(A),
.B(B),
.C(C)
);
endmodule
|
module cpx_io_grant_ff(/*AUTOARG*/
// Outputs
cpx_io_grant_cx2, so,
// Inputs
cpx_io_grant_cx, rclk, si, se
);
output [7:0] cpx_io_grant_cx2;
output so;
input [7:0] cpx_io_grant_cx;
input rclk;
input si;
input se;
dff_s #(8) dff_ccx_com_src(
.din (cpx_io_grant_cx[7:0]),
.q (cpx_io_grant_cx2[7:0]),
.clk (rclk),
.se (1'b0),
.si (8'd0),
.so ());
endmodule
|
module GeAr_N8_R1_P2 ( in1, in2, res );
input [7:0] in1;
input [7:0] in2;
output [8:0] res;
wire n24, n25, n26, n27, n28, n29, n30, n31, n32, n33, n34, n35, n36, n37,
n38, n39, n40, n41, n42, n43, n44, n45, n46, n47;
CLKAND2X2TS U31 ( .A(in1[0]), .B(in2[0]), .Y(n47) );
OAI21XLTS U32 ( .A0(in2[2]), .A1(in1[2]), .B0(n44), .Y(n46) );
NOR2XLTS U33 ( .A(in2[6]), .B(in1[6]), .Y(n37) );
NOR2X2TS U34 ( .A(in1[4]), .B(in2[4]), .Y(n34) );
OAI21XLTS U35 ( .A0(n41), .A1(n40), .B0(n39), .Y(n42) );
OAI21XLTS U36 ( .A0(n30), .A1(n40), .B0(n29), .Y(n28) );
NOR2X2TS U37 ( .A(in1[5]), .B(in2[5]), .Y(n40) );
OAI21XLTS U38 ( .A0(n27), .A1(n32), .B0(n26), .Y(n25) );
NOR2X2TS U39 ( .A(in1[3]), .B(in2[3]), .Y(n32) );
OAI211XLTS U40 ( .A0(in2[2]), .A1(in1[2]), .B0(in2[1]), .C0(in1[1]), .Y(n24)
);
OAI21XLTS U41 ( .A0(n36), .A1(n34), .B0(n35), .Y(n33) );
NAND2X1TS U42 ( .A(in1[3]), .B(in2[3]), .Y(n31) );
INVX2TS U43 ( .A(n31), .Y(n27) );
NAND2X1TS U44 ( .A(in2[2]), .B(in1[2]), .Y(n44) );
NAND2X1TS U45 ( .A(n44), .B(n24), .Y(n26) );
OAI31X1TS U46 ( .A0(n27), .A1(n26), .A2(n32), .B0(n25), .Y(res[3]) );
NAND2X1TS U47 ( .A(in1[5]), .B(in2[5]), .Y(n39) );
INVX2TS U48 ( .A(n39), .Y(n30) );
NAND2X1TS U49 ( .A(in1[4]), .B(in2[4]), .Y(n41) );
OAI21X1TS U50 ( .A0(n34), .A1(n31), .B0(n41), .Y(n29) );
OAI31X1TS U51 ( .A0(n30), .A1(n29), .A2(n40), .B0(n28), .Y(res[5]) );
INVX2TS U52 ( .A(n41), .Y(n36) );
OAI21X1TS U53 ( .A0(n32), .A1(n44), .B0(n31), .Y(n35) );
OAI31X1TS U54 ( .A0(n36), .A1(n35), .A2(n34), .B0(n33), .Y(res[4]) );
OAI2BB2XLTS U55 ( .B0(n39), .B1(n37), .A0N(in2[6]), .A1N(in1[6]), .Y(n38) );
CMPR32X2TS U56 ( .A(in1[7]), .B(in2[7]), .C(n38), .CO(res[8]), .S(res[7]) );
XNOR2X1TS U57 ( .A(n42), .B(in2[6]), .Y(n43) );
XNOR2X1TS U58 ( .A(in1[6]), .B(n43), .Y(res[6]) );
CMPR32X2TS U59 ( .A(in2[1]), .B(in1[1]), .C(n47), .CO(n45), .S(res[1]) );
XNOR2X1TS U60 ( .A(n46), .B(n45), .Y(res[2]) );
AOI2BB1XLTS U61 ( .A0N(in1[0]), .A1N(in2[0]), .B0(n47), .Y(res[0]) );
initial $sdf_annotate("GeAr_N8_R1_P2_syn.sdf");
endmodule
|
module usb_system_sdram_clk_dffpipe_l2c
(
clock,
clrn,
d,
q) /* synthesis synthesis_clearbox=1 */;
input clock;
input clrn;
input [0:0] d;
output [0:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 clock;
tri1 clrn;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
reg [0:0] dffe4a;
reg [0:0] dffe5a;
reg [0:0] dffe6a;
wire ena;
wire prn;
wire sclr;
// synopsys translate_off
initial
dffe4a = 0;
// synopsys translate_on
always @ ( posedge clock or negedge prn or negedge clrn)
if (prn == 1'b0) dffe4a <= {1{1'b1}};
else if (clrn == 1'b0) dffe4a <= 1'b0;
else if (ena == 1'b1) dffe4a <= (d & (~ sclr));
// synopsys translate_off
initial
dffe5a = 0;
// synopsys translate_on
always @ ( posedge clock or negedge prn or negedge clrn)
if (prn == 1'b0) dffe5a <= {1{1'b1}};
else if (clrn == 1'b0) dffe5a <= 1'b0;
else if (ena == 1'b1) dffe5a <= (dffe4a & (~ sclr));
// synopsys translate_off
initial
dffe6a = 0;
// synopsys translate_on
always @ ( posedge clock or negedge prn or negedge clrn)
if (prn == 1'b0) dffe6a <= {1{1'b1}};
else if (clrn == 1'b0) dffe6a <= 1'b0;
else if (ena == 1'b1) dffe6a <= (dffe5a & (~ sclr));
assign
ena = 1'b1,
prn = 1'b1,
q = dffe6a,
sclr = 1'b0;
endmodule
|
module usb_system_sdram_clk_stdsync_sv6
(
clk,
din,
dout,
reset_n) /* synthesis synthesis_clearbox=1 */;
input clk;
input din;
output dout;
input reset_n;
wire [0:0] wire_dffpipe3_q;
usb_system_sdram_clk_dffpipe_l2c dffpipe3
(
.clock(clk),
.clrn(reset_n),
.d(din),
.q(wire_dffpipe3_q));
assign
dout = wire_dffpipe3_q;
endmodule
|
module usb_system_sdram_clk_altpll_l942
(
areset,
clk,
inclk,
locked) /* synthesis synthesis_clearbox=1 */;
input areset;
output [4:0] clk;
input [1:0] inclk;
output locked;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 areset;
tri0 [1:0] inclk;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
reg pll_lock_sync;
wire [4:0] wire_pll7_clk;
wire wire_pll7_fbout;
wire wire_pll7_locked;
// synopsys translate_off
initial
pll_lock_sync = 0;
// synopsys translate_on
always @ ( posedge wire_pll7_locked or posedge areset)
if (areset == 1'b1) pll_lock_sync <= 1'b0;
else pll_lock_sync <= 1'b1;
cycloneive_pll pll7
(
.activeclock(),
.areset(areset),
.clk(wire_pll7_clk),
.clkbad(),
.fbin(wire_pll7_fbout),
.fbout(wire_pll7_fbout),
.inclk(inclk),
.locked(wire_pll7_locked),
.phasedone(),
.scandataout(),
.scandone(),
.vcooverrange(),
.vcounderrange()
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.clkswitch(1'b0),
.configupdate(1'b0),
.pfdena(1'b1),
.phasecounterselect({3{1'b0}}),
.phasestep(1'b0),
.phaseupdown(1'b0),
.scanclk(1'b0),
.scanclkena(1'b1),
.scandata(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
pll7.bandwidth_type = "auto",
pll7.clk0_divide_by = 1,
pll7.clk0_duty_cycle = 50,
pll7.clk0_multiply_by = 1,
pll7.clk0_phase_shift = "-3000",
pll7.compensate_clock = "clk0",
pll7.inclk0_input_frequency = 20000,
pll7.operation_mode = "normal",
pll7.pll_type = "auto",
pll7.lpm_type = "cycloneive_pll";
assign
clk = {wire_pll7_clk[4:0]},
locked = (wire_pll7_locked & pll_lock_sync);
endmodule
|
module usb_system_sdram_clk
(
address,
areset,
c0,
clk,
locked,
phasedone,
read,
readdata,
reset,
write,
writedata) /* synthesis synthesis_clearbox=1 */;
input [1:0] address;
input areset;
output c0;
input clk;
output locked;
output phasedone;
input read;
output [31:0] readdata;
input reset;
input write;
input [31:0] writedata;
wire wire_stdsync2_dout;
wire [4:0] wire_sd1_clk;
wire wire_sd1_locked;
(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=HIGH"} *)
reg pfdena_reg;
wire wire_pfdena_reg_ena;
reg prev_reset;
wire w_locked;
wire w_pfdena;
wire w_phasedone;
wire w_pll_areset_in;
wire w_reset;
wire w_select_control;
wire w_select_status;
usb_system_sdram_clk_stdsync_sv6 stdsync2
(
.clk(clk),
.din(wire_sd1_locked),
.dout(wire_stdsync2_dout),
.reset_n((~ reset)));
usb_system_sdram_clk_altpll_l942 sd1
(
.areset((w_pll_areset_in | areset)),
.clk(wire_sd1_clk),
.inclk({{1{1'b0}}, clk}),
.locked(wire_sd1_locked));
// synopsys translate_off
initial
pfdena_reg = {1{1'b1}};
// synopsys translate_on
always @ ( posedge clk or posedge reset)
if (reset == 1'b1) pfdena_reg <= {1{1'b1}};
else if (wire_pfdena_reg_ena == 1'b1) pfdena_reg <= writedata[1];
assign
wire_pfdena_reg_ena = (write & w_select_control);
// synopsys translate_off
initial
prev_reset = 0;
// synopsys translate_on
always @ ( posedge clk or posedge reset)
if (reset == 1'b1) prev_reset <= 1'b0;
else prev_reset <= w_reset;
assign
c0 = wire_sd1_clk[0],
locked = wire_sd1_locked,
phasedone = 1'b0,
readdata = {{30{1'b0}}, (read & ((w_select_control & w_pfdena) | (w_select_status & w_phasedone))), (read & ((w_select_control & w_pll_areset_in) | (w_select_status & w_locked)))},
w_locked = wire_stdsync2_dout,
w_pfdena = pfdena_reg,
w_phasedone = 1'b1,
w_pll_areset_in = prev_reset,
w_reset = ((write & w_select_control) & writedata[0]),
w_select_control = ((~ address[1]) & address[0]),
w_select_status = ((~ address[1]) & (~ address[0]));
endmodule
|
module test_pe;
// Inputs
reg clk;
reg reset;
reg [10:0] ctrl;
reg [197:0] d0;
reg [193:0] d1;
reg [193:0] d2;
reg [193:0] wish;
// Outputs
wire [193:0] out;
// Instantiate the Unit Under Test (UUT)
PE uut (
.clk(clk),
.reset(reset),
.ctrl(ctrl),
.d0(d0),
.d1(d1),
.d2(d2),
.out(out)
);
initial begin
// Initialize Inputs
clk = 0;
reset = 0;
ctrl = 0;
d0 = 0;
d1 = 0;
d2 = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
// test mult
d0 = 194'h15a25886512165251569195908560596a6695612620504191;
d1 = 194'h159546442405a181195655549614540592955a15a26984015;
d2 = d1;
wish = 194'h21019120440545215a1462a194a24a6019441081402410969;
@(negedge clk);
reset=1;#`P reset=0;
ctrl=11'b11111_000000; #`P;
ctrl=11'b00000_111111; #(33*`P);
check;
// test cubic
d0 = {6'b10101, 192'd0};
d1 = 194'h0894286a45940549565566512aa04a15558406850485454a4;
d2 = d1;
wish = 194'h1049480a48a0855a494855810160a90956659914560616652;
@(negedge clk);
reset=1;#`P reset=0;
ctrl=11'b11111_000000; #`P;
ctrl=1; #(33*`P);
check;
// test add
d0 = {6'b000101, 192'd0};
d1 = 194'h0994544a41588446516618a14691a545542521a4158868428;
d2 = 194'h1901269451681914415481656104980811a5a555155546949;
wish = 194'h16954a129284915a928a9916a4954141659a96092a11a2165;
@(negedge clk);
reset=1;#`P reset=0;
ctrl=11'b11111_000000; #`P;
ctrl=11'b10001; #(33*`P);
check;
// test sub
d0 = {6'b001001, 192'd0};
d1 = 194'h0994544a41588446516618a14691a545542521a4158868428;
d2 = 194'h1901269451681914415481656104980811a5a555155546949;
wish = 194'h209661a62020aa6210125a481599194946404852006625aa2;
@(negedge clk);
reset=1;#`P reset=0;
ctrl=11'b11111_000000; #`P;
ctrl=11'b10001; #(33*`P);
check;
$display("Good!");
$finish;
end
initial #100 forever #(`P/2) clk = ~clk;
task check;
begin
if (out !== wish)
begin $display("E %h %h", out, wish); $finish; end
end
endtask
endmodule
|
module axi_hdmi_tx_core #(
parameter CR_CB_N = 0,
parameter EMBEDDED_SYNC = 0) (
// hdmi interface
input hdmi_clk,
input hdmi_rst,
// 16-bit interface
output reg hdmi_16_hsync,
output reg hdmi_16_vsync,
output reg hdmi_16_data_e,
output reg [15:0] hdmi_16_data,
output reg [15:0] hdmi_16_es_data,
// 24-bit interface
output reg hdmi_24_hsync,
output reg hdmi_24_vsync,
output reg hdmi_24_data_e,
output reg [23:0] hdmi_24_data,
// 36-bit interface
output reg hdmi_36_hsync,
output reg hdmi_36_vsync,
output reg hdmi_36_data_e,
output reg [35:0] hdmi_36_data,
// control signals
output reg hdmi_fs_toggle,
output reg [ 8:0] hdmi_raddr_g,
output reg hdmi_tpm_oos,
output reg hdmi_status,
// vdma interface
input vdma_clk,
input vdma_wr,
input [ 8:0] vdma_waddr,
input [47:0] vdma_wdata,
input vdma_fs_ret_toggle,
input [ 8:0] vdma_fs_waddr,
// processor interface
input hdmi_csc_bypass,
input hdmi_ss_bypass,
input [ 1:0] hdmi_srcsel,
input [23:0] hdmi_const_rgb,
input [15:0] hdmi_hl_active,
input [15:0] hdmi_hl_width,
input [15:0] hdmi_hs_width,
input [15:0] hdmi_he_max,
input [15:0] hdmi_he_min,
input [15:0] hdmi_vf_active,
input [15:0] hdmi_vf_width,
input [15:0] hdmi_vs_width,
input [15:0] hdmi_ve_max,
input [15:0] hdmi_ve_min,
input [23:0] hdmi_clip_max,
input [23:0] hdmi_clip_min);
// internal registers
reg hdmi_enable = 'd0;
reg [15:0] hdmi_hs_count = 'd0;
reg [15:0] hdmi_vs_count = 'd0;
reg hdmi_fs = 'd0;
reg hdmi_fs_ret_toggle_m1 = 'd0;
reg hdmi_fs_ret_toggle_m2 = 'd0;
reg hdmi_fs_ret_toggle_m3 = 'd0;
reg hdmi_fs_ret = 'd0;
reg [ 8:0] hdmi_fs_waddr = 'd0;
reg hdmi_hs = 'd0;
reg hdmi_vs = 'd0;
reg hdmi_hs_de = 'd0;
reg hdmi_vs_de = 'd0;
reg [ 9:0] hdmi_raddr = 'd0;
reg hdmi_hs_d = 'd0;
reg hdmi_vs_d = 'd0;
reg hdmi_hs_de_d = 'd0;
reg hdmi_vs_de_d = 'd0;
reg hdmi_de_d = 'd0;
reg hdmi_data_sel_d = 'd0;
reg hdmi_hs_2d = 'd0;
reg hdmi_vs_2d = 'd0;
reg hdmi_hs_de_2d = 'd0;
reg hdmi_vs_de_2d = 'd0;
reg hdmi_de_2d = 'd0;
reg hdmi_data_sel_2d = 'd0;
reg [47:0] hdmi_data_2d = 'd0;
reg [23:0] hdmi_tpm_data = 'd0;
reg hdmi_hsync = 'd0;
reg hdmi_vsync = 'd0;
reg hdmi_hsync_data_e = 'd0;
reg hdmi_vsync_data_e = 'd0;
reg hdmi_data_e = 'd0;
reg [23:0] hdmi_data = 'd0;
reg hdmi_24_csc_hsync = 'd0;
reg hdmi_24_csc_vsync = 'd0;
reg hdmi_24_csc_hsync_data_e = 'd0;
reg hdmi_24_csc_vsync_data_e = 'd0;
reg hdmi_24_csc_data_e = 'd0;
reg [23:0] hdmi_24_csc_data = 'd0;
reg hdmi_16_hsync_d = 'd0;
reg hdmi_16_vsync_d = 'd0;
reg hdmi_16_hsync_data_e_d = 'd0;
reg hdmi_16_vsync_data_e_d = 'd0;
reg hdmi_16_data_e_d = 'd0;
reg [15:0] hdmi_16_data_d = 'd0;
reg hdmi_es_hs_de = 'd0;
reg hdmi_es_vs_de = 'd0;
reg [15:0] hdmi_es_data = 'd0;
reg [23:0] hdmi_clip_data = 'd0;
reg hdmi_clip_hs_de_d = 'd0;
reg hdmi_clip_vs_de_d = 'd0;
reg hdmi_clip_hs_d = 'd0;
reg hdmi_clip_vs_d = 'd0;
reg hdmi_clip_de_d = 'd0;
// internal wires
wire [15:0] hdmi_hl_width_s;
wire [15:0] hdmi_vf_width_s;
wire [15:0] hdmi_he_width_s;
wire [15:0] hdmi_ve_width_s;
wire hdmi_fs_ret_s;
wire hdmi_de_s;
wire [47:0] hdmi_rdata_s;
wire [23:0] hdmi_data_2d_s;
wire hdmi_tpm_mismatch_s;
wire [23:0] hdmi_tpg_data_s;
wire hdmi_csc_hsync_s;
wire hdmi_csc_vsync_s;
wire hdmi_csc_hsync_data_e_s;
wire hdmi_csc_vsync_data_e_s;
wire hdmi_csc_data_e_s;
wire [23:0] hdmi_csc_data_s;
wire hdmi_ss_hsync_s;
wire hdmi_ss_vsync_s;
wire hdmi_ss_hsync_data_e_s;
wire hdmi_ss_vsync_data_e_s;
wire hdmi_ss_data_e_s;
wire [15:0] hdmi_ss_data_s;
wire [15:0] hdmi_es_data_s;
// binary to grey conversion
function [8:0] b2g;
input [8:0] b;
reg [8:0] g;
begin
g[8] = b[8];
g[7] = b[8] ^ b[7];
g[6] = b[7] ^ b[6];
g[5] = b[6] ^ b[5];
g[4] = b[5] ^ b[4];
g[3] = b[4] ^ b[3];
g[2] = b[3] ^ b[2];
g[1] = b[2] ^ b[1];
g[0] = b[1] ^ b[0];
b2g = g;
end
endfunction
// status and enable
always @(posedge hdmi_clk) begin
if (hdmi_rst == 1'b1) begin
hdmi_status <= 1'b0;
hdmi_enable <= 1'b0;
end else begin
hdmi_status <= 1'b1;
hdmi_enable <= hdmi_srcsel[1] | hdmi_srcsel[0];
end
end
// calculate useful limits
assign hdmi_hl_width_s = hdmi_hl_width - 1'b1;
assign hdmi_vf_width_s = hdmi_vf_width - 1'b1;
assign hdmi_he_width_s = hdmi_hl_width - (hdmi_hl_active + 1'b1);
assign hdmi_ve_width_s = hdmi_vf_width - (hdmi_vf_active + 1'b1);
// hdmi counters
always @(posedge hdmi_clk) begin
if (hdmi_hs_count >= hdmi_hl_width_s) begin
hdmi_hs_count <= 0;
end else begin
hdmi_hs_count <= hdmi_hs_count + 1'b1;
end
if (hdmi_hs_count >= hdmi_hl_width_s) begin
if (hdmi_vs_count >= hdmi_vf_width_s) begin
hdmi_vs_count <= 0;
end else begin
hdmi_vs_count <= hdmi_vs_count + 1'b1;
end
end
end
// hdmi start of frame
always @(posedge hdmi_clk) begin
if (hdmi_rst == 1'b1) begin
hdmi_fs_toggle <= 1'b0;
hdmi_fs <= 1'b0;
end else begin
if (EMBEDDED_SYNC == 1) begin
if ((hdmi_hs_count == 1) && (hdmi_vs_count == hdmi_ve_width_s)) begin
hdmi_fs <= hdmi_enable;
end else begin
hdmi_fs <= 1'b0;
end
end else begin
if ((hdmi_hs_count == 1) && (hdmi_vs_count == hdmi_vs_width)) begin
hdmi_fs <= hdmi_enable;
end else begin
hdmi_fs <= 1'b0;
end
end
if (hdmi_fs == 1'b1) begin
hdmi_fs_toggle <= ~hdmi_fs_toggle;
end
end
end
// hdmi sof write address
assign hdmi_fs_ret_s = hdmi_fs_ret_toggle_m2 ^ hdmi_fs_ret_toggle_m3;
always @(posedge hdmi_clk or posedge hdmi_rst) begin
if (hdmi_rst == 1'b1) begin
hdmi_fs_ret_toggle_m1 <= 1'd0;
hdmi_fs_ret_toggle_m2 <= 1'd0;
hdmi_fs_ret_toggle_m3 <= 1'd0;
end else begin
hdmi_fs_ret_toggle_m1 <= vdma_fs_ret_toggle;
hdmi_fs_ret_toggle_m2 <= hdmi_fs_ret_toggle_m1;
hdmi_fs_ret_toggle_m3 <= hdmi_fs_ret_toggle_m2;
end
end
always @(posedge hdmi_clk) begin
hdmi_fs_ret <= hdmi_fs_ret_s;
hdmi_fs_waddr <= vdma_fs_waddr;
end
// hdmi sync signals
always @(posedge hdmi_clk) begin
if (EMBEDDED_SYNC == 1) begin
hdmi_hs <= 1'b0;
hdmi_vs <= 1'b0;
if (hdmi_hs_count <= hdmi_he_width_s) begin
hdmi_hs_de <= 1'b0;
end else begin
hdmi_hs_de <= hdmi_enable;
end
if (hdmi_vs_count <= hdmi_ve_width_s) begin
hdmi_vs_de <= 1'b0;
end else begin
hdmi_vs_de <= hdmi_enable;
end
end else begin
if (hdmi_hs_count < hdmi_hs_width) begin
hdmi_hs <= hdmi_enable;
end else begin
hdmi_hs <= 1'b0;
end
if (hdmi_vs_count < hdmi_vs_width) begin
hdmi_vs <= hdmi_enable;
end else begin
hdmi_vs <= 1'b0;
end
if ((hdmi_hs_count < hdmi_he_min) || (hdmi_hs_count >= hdmi_he_max)) begin
hdmi_hs_de <= 1'b0;
end else begin
hdmi_hs_de <= hdmi_enable;
end
if ((hdmi_vs_count < hdmi_ve_min) || (hdmi_vs_count >= hdmi_ve_max)) begin
hdmi_vs_de <= 1'b0;
end else begin
hdmi_vs_de <= hdmi_enable;
end
end
end
// hdmi read data
assign hdmi_de_s = hdmi_hs_de & hdmi_vs_de;
always @(posedge hdmi_clk) begin
if (hdmi_rst == 1'b1) begin
hdmi_raddr <= 10'd0;
end else if (hdmi_fs == 1'b1) begin
hdmi_raddr <= {hdmi_fs_waddr, 1'b0};
end else if (hdmi_de_s == 1'b1) begin
hdmi_raddr <= hdmi_raddr + 1'b1;
end
hdmi_raddr_g <= b2g(hdmi_raddr[9:1]);
end
// control and data pipe line
always @(posedge hdmi_clk) begin
hdmi_hs_d <= hdmi_hs;
hdmi_vs_d <= hdmi_vs;
hdmi_hs_de_d <= hdmi_hs_de;
hdmi_vs_de_d <= hdmi_vs_de;
hdmi_de_d <= hdmi_de_s;
hdmi_data_sel_d <= hdmi_raddr[0];
hdmi_hs_2d <= hdmi_hs_d;
hdmi_vs_2d <= hdmi_vs_d;
hdmi_hs_de_2d <= hdmi_hs_de_d;
hdmi_vs_de_2d <= hdmi_vs_de_d;
hdmi_de_2d <= hdmi_de_d;
hdmi_data_sel_2d <= hdmi_data_sel_d;
hdmi_data_2d <= hdmi_rdata_s;
end
// hdmi data count (may be used to monitor or insert)
assign hdmi_data_2d_s = (hdmi_data_sel_2d == 1'b1) ? hdmi_data_2d[47:24] : hdmi_data_2d[23:0];
assign hdmi_tpm_mismatch_s = (hdmi_data_2d_s == hdmi_tpm_data) ? 1'b0 : hdmi_de_2d;
assign hdmi_tpg_data_s = hdmi_tpm_data;
always @(posedge hdmi_clk) begin
if ((hdmi_rst == 1'b1) || (hdmi_fs_ret == 1'b1)) begin
hdmi_tpm_data <= 'd0;
end else if (hdmi_de_2d == 1'b1) begin
hdmi_tpm_data <= hdmi_tpm_data + 1'b1;
end
hdmi_tpm_oos <= hdmi_tpm_mismatch_s;
end
// hdmi data select
always @(posedge hdmi_clk) begin
hdmi_hsync <= hdmi_hs_2d;
hdmi_vsync <= hdmi_vs_2d;
hdmi_hsync_data_e <= hdmi_hs_de_2d;
hdmi_vsync_data_e <= hdmi_vs_de_2d;
hdmi_data_e <= hdmi_de_2d;
case (hdmi_srcsel)
2'b11: hdmi_data <= hdmi_const_rgb;
2'b10: hdmi_data <= hdmi_tpg_data_s;
2'b01: hdmi_data <= hdmi_data_2d_s;
default: hdmi_data <= 24'd0;
endcase
end
// Color space conversion bypass (RGB/YCbCr)
always @(posedge hdmi_clk) begin
if (hdmi_csc_bypass == 1'b1) begin
hdmi_24_csc_hsync <= hdmi_hsync;
hdmi_24_csc_vsync <= hdmi_vsync;
hdmi_24_csc_hsync_data_e <= hdmi_hsync_data_e;
hdmi_24_csc_vsync_data_e <= hdmi_vsync_data_e;
hdmi_24_csc_data_e <= hdmi_data_e;
hdmi_24_csc_data <= hdmi_data;
end else begin
hdmi_24_csc_hsync <= hdmi_csc_hsync_s;
hdmi_24_csc_vsync <= hdmi_csc_vsync_s;
hdmi_24_csc_hsync_data_e <= hdmi_csc_hsync_data_e_s;
hdmi_24_csc_vsync_data_e <= hdmi_csc_vsync_data_e_s;
hdmi_24_csc_data_e <= hdmi_csc_data_e_s;
hdmi_24_csc_data <= hdmi_csc_data_s;
end
end
// hdmi clipping
always @(posedge hdmi_clk) begin
hdmi_clip_hs_d <= hdmi_24_csc_hsync;
hdmi_clip_vs_d <= hdmi_24_csc_vsync;
hdmi_clip_hs_de_d <= hdmi_24_csc_hsync_data_e;
hdmi_clip_vs_de_d <= hdmi_24_csc_vsync_data_e;
hdmi_clip_de_d <= hdmi_24_csc_data_e;
// Cr (red-diff) / red
if (hdmi_24_csc_data[23:16] > hdmi_clip_max[23:16]) begin
hdmi_clip_data[23:16] <= hdmi_clip_max[23:16];
end else if (hdmi_24_csc_data[23:16] < hdmi_clip_min[23:16]) begin
hdmi_clip_data[23:16] <= hdmi_clip_min[23:16];
end else begin
hdmi_clip_data[23:16] <= hdmi_24_csc_data[23:16];
end
// Y (luma) / green
if (hdmi_24_csc_data[15:8] > hdmi_clip_max[15:8]) begin
hdmi_clip_data[15:8] <= hdmi_clip_max[15:8];
end else if (hdmi_24_csc_data[15:8] < hdmi_clip_min[15:8]) begin
hdmi_clip_data[15:8] <= hdmi_clip_min[15:8];
end else begin
hdmi_clip_data[15:8] <= hdmi_24_csc_data[15:8];
end
// Cb (blue-diff) / blue
if (hdmi_24_csc_data[7:0] > hdmi_clip_max[7:0]) begin
hdmi_clip_data[7:0] <= hdmi_clip_max[7:0];
end else if (hdmi_24_csc_data[7:0] < hdmi_clip_min[7:0]) begin
hdmi_clip_data[7:0] <= hdmi_clip_min[7:0];
end else begin
hdmi_clip_data[7:0] <= hdmi_24_csc_data[7:0];
end
end
// hdmi csc 16, 24 and 36 outputs
always @(posedge hdmi_clk) begin
hdmi_36_hsync <= hdmi_clip_hs_d;
hdmi_36_vsync <= hdmi_clip_vs_d;
hdmi_36_data_e <= hdmi_clip_de_d;
hdmi_36_data[35:24] <= {hdmi_clip_data[23:16], hdmi_clip_data[23:20]};
hdmi_36_data[23:12] <= {hdmi_clip_data[15: 8], hdmi_clip_data[15:12]};
hdmi_36_data[11: 0] <= {hdmi_clip_data[ 7: 0], hdmi_clip_data[ 7: 4]};
hdmi_24_hsync <= hdmi_clip_hs_d;
hdmi_24_vsync <= hdmi_clip_vs_d;
hdmi_24_data_e <= hdmi_clip_de_d;
hdmi_24_data <= hdmi_clip_data;
hdmi_16_hsync <= hdmi_16_hsync_d;
hdmi_16_vsync <= hdmi_16_vsync_d;
hdmi_16_data_e <= hdmi_16_data_e_d;
hdmi_16_data <= hdmi_16_data_d;
hdmi_16_es_data <= hdmi_es_data_s;
if (hdmi_ss_bypass == 1'b1) begin
hdmi_16_hsync_d <= hdmi_clip_hs_d;
hdmi_16_vsync_d <= hdmi_clip_vs_d;
hdmi_16_hsync_data_e_d <= hdmi_clip_hs_de_d;
hdmi_16_vsync_data_e_d <= hdmi_clip_vs_de_d;
hdmi_16_data_e_d <= hdmi_clip_de_d;
hdmi_16_data_d <= hdmi_clip_data[15:0]; // Ignore the upper 8 bit
end else begin
hdmi_16_hsync_d <= hdmi_ss_hsync_s;
hdmi_16_vsync_d <= hdmi_ss_vsync_s;
hdmi_16_hsync_data_e_d <= hdmi_ss_hsync_data_e_s;
hdmi_16_vsync_data_e_d <= hdmi_ss_vsync_data_e_s;
hdmi_16_data_e_d <= hdmi_ss_data_e_s;
hdmi_16_data_d <= hdmi_ss_data_s;
end
end
// hdmi embedded sync
always @(posedge hdmi_clk) begin
hdmi_es_hs_de <= hdmi_16_hsync_data_e_d;
hdmi_es_vs_de <= hdmi_16_vsync_data_e_d;
if (hdmi_16_data_e_d == 1'b0) begin
hdmi_es_data[15:8] <= 8'h80;
end else begin
hdmi_es_data[15:8] <= hdmi_16_data_d[15:8];
end
if (hdmi_16_data_e_d == 1'b0) begin
hdmi_es_data[7:0] <= 8'h80;
end else begin
hdmi_es_data[7:0] <= hdmi_16_data_d[7:0];
end
end
// data memory
ad_mem #(.DATA_WIDTH(48), .ADDRESS_WIDTH(9)) i_mem (
.clka (vdma_clk),
.wea (vdma_wr),
.addra (vdma_waddr),
.dina (vdma_wdata),
.clkb (hdmi_clk),
.reb (1'b1),
.addrb (hdmi_raddr[9:1]),
.doutb (hdmi_rdata_s));
// color space coversion, RGB to CrYCb
ad_csc_RGB2CrYCb #(.DELAY_DATA_WIDTH(5)) i_csc_RGB2CrYCb (
.clk (hdmi_clk),
.RGB_sync ({hdmi_hsync,
hdmi_vsync,
hdmi_hsync_data_e,
hdmi_vsync_data_e,
hdmi_data_e}),
.RGB_data (hdmi_data),
.CrYCb_sync ({hdmi_csc_hsync_s,
hdmi_csc_vsync_s,
hdmi_csc_hsync_data_e_s,
hdmi_csc_vsync_data_e_s,
hdmi_csc_data_e_s}),
.CrYCb_data (hdmi_csc_data_s));
// sub sampling, 444 to 422
ad_ss_444to422 #(.DELAY_DATA_WIDTH(5), .CR_CB_N(CR_CB_N)) i_ss_444to422 (
.clk (hdmi_clk),
.s444_de (hdmi_clip_de_d),
.s444_sync ({hdmi_clip_hs_d,
hdmi_clip_vs_d,
hdmi_clip_hs_de_d,
hdmi_clip_vs_de_d,
hdmi_clip_de_d}),
.s444_data (hdmi_clip_data),
.s422_sync ({hdmi_ss_hsync_s,
hdmi_ss_vsync_s,
hdmi_ss_hsync_data_e_s,
hdmi_ss_vsync_data_e_s,
hdmi_ss_data_e_s}),
.s422_data (hdmi_ss_data_s));
// embedded sync
axi_hdmi_tx_es #(.DATA_WIDTH(16)) i_es (
.hdmi_clk (hdmi_clk),
.hdmi_hs_de (hdmi_es_hs_de),
.hdmi_vs_de (hdmi_es_vs_de),
.hdmi_data_de (hdmi_es_data),
.hdmi_data (hdmi_es_data_s));
endmodule
|
module bd_350b_slot_2_b_0 (
In0,
In1,
dout
);
input wire [0 : 0] In0;
input wire [0 : 0] In1;
output wire [1 : 0] dout;
xlconcat_v2_1_1_xlconcat #(
.IN0_WIDTH(1),
.IN1_WIDTH(1),
.IN2_WIDTH(1),
.IN3_WIDTH(1),
.IN4_WIDTH(1),
.IN5_WIDTH(1),
.IN6_WIDTH(1),
.IN7_WIDTH(1),
.IN8_WIDTH(1),
.IN9_WIDTH(1),
.IN10_WIDTH(1),
.IN11_WIDTH(1),
.IN12_WIDTH(1),
.IN13_WIDTH(1),
.IN14_WIDTH(1),
.IN15_WIDTH(1),
.IN16_WIDTH(1),
.IN17_WIDTH(1),
.IN18_WIDTH(1),
.IN19_WIDTH(1),
.IN20_WIDTH(1),
.IN21_WIDTH(1),
.IN22_WIDTH(1),
.IN23_WIDTH(1),
.IN24_WIDTH(1),
.IN25_WIDTH(1),
.IN26_WIDTH(1),
.IN27_WIDTH(1),
.IN28_WIDTH(1),
.IN29_WIDTH(1),
.IN30_WIDTH(1),
.IN31_WIDTH(1),
.dout_width(2),
.NUM_PORTS(2)
) inst (
.In0(In0),
.In1(In1),
.In2(1'B0),
.In3(1'B0),
.In4(1'B0),
.In5(1'B0),
.In6(1'B0),
.In7(1'B0),
.In8(1'B0),
.In9(1'B0),
.In10(1'B0),
.In11(1'B0),
.In12(1'B0),
.In13(1'B0),
.In14(1'B0),
.In15(1'B0),
.In16(1'B0),
.In17(1'B0),
.In18(1'B0),
.In19(1'B0),
.In20(1'B0),
.In21(1'B0),
.In22(1'B0),
.In23(1'B0),
.In24(1'B0),
.In25(1'B0),
.In26(1'B0),
.In27(1'B0),
.In28(1'B0),
.In29(1'B0),
.In30(1'B0),
.In31(1'B0),
.dout(dout)
);
endmodule
|
module sky130_fd_sc_hs__o2bb2ai (
Y ,
A1_N,
A2_N,
B1 ,
B2
);
output Y ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule
|
module RegisterFileSim();
reg clk;
reg init;
reg [4:0] readReg1;
reg [4:0] readReg2;
reg [4:0] writeReg;
reg writeOp;
reg [31:0] writeData;
wire [31:0] readData1;
wire [31:0] readData2;
RegisterFile file(
.clk(clk),
.init(init),
.writeOp(writeOp),
.readReg1(readReg1),
.readReg2(readReg2),
.writeReg(writeReg),
.writeData(writeData),
.readData1(readData1),
.readData2(readData2)
);
always #50 clk = ~clk;
initial begin
clk = 0;
init = 0;
writeOp = 0;
readReg1 = 0;
readReg2 = 0;
writeReg = 0;
writeData = 0;
// write $1 = 1
#100
init = 1;
writeOp = 1;
readReg1 = 0;
readReg2 = 0;
writeReg = 1;
writeData = 1;
// write $2 = 2
#100
init = 1;
writeOp = 1;
readReg1 = 0;
readReg2 = 0;
writeReg = 2;
writeData = 2;
// write $3 = 3
#100
init = 1;
writeOp = 1;
readReg1 = 0;
readReg2 = 0;
writeReg = 3;
writeData = 3;
// read1 $1 == 1
#100
init = 1;
writeOp = 0;
readReg1 = 1;
readReg2 = 0;
writeReg = 0;
writeData = 0;
// read2 $2 == 2
#100
init = 1;
writeOp = 0;
readReg1 = 0;
readReg2 = 2;
writeReg = 0;
writeData = 0;
// read1 $1 == 1, read2 $3 == 3
#100
init = 1;
writeOp = 0;
readReg1 = 1;
readReg2 = 3;
writeReg = 0;
writeData = 0;
#200
// reset
#100
init = 0;
writeOp = 0;
readReg1 = 0;
readReg2 = 0;
writeReg = 0;
writeData = 0;
end
endmodule
|
module sky130_fd_sc_ls__sdfrbp (
//# {{data|Data Signals}}
input D ,
output Q ,
output Q_N ,
//# {{control|Control Signals}}
input RESET_B,
//# {{scanchain|Scan Chain}}
input SCD ,
input SCE ,
//# {{clocks|Clocking}}
input CLK ,
//# {{power|Power}}
input VPB ,
input VPWR ,
input VGND ,
input VNB
);
endmodule
|
module sky130_fd_sc_hdll__sdfrbp (
//# {{data|Data Signals}}
input D ,
output Q ,
output Q_N ,
//# {{control|Control Signals}}
input RESET_B,
//# {{scanchain|Scan Chain}}
input SCD ,
input SCE ,
//# {{clocks|Clocking}}
input CLK ,
//# {{power|Power}}
input VPB ,
input VPWR ,
input VGND ,
input VNB
);
endmodule
|
module sky130_fd_sc_lp__a2bb2o_2 (
X ,
A1_N,
A2_N,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__a2bb2o base (
.X(X),
.A1_N(A1_N),
.A2_N(A2_N),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
|
module sky130_fd_sc_lp__a2bb2o_2 (
X ,
A1_N,
A2_N,
B1 ,
B2
);
output X ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__a2bb2o base (
.X(X),
.A1_N(A1_N),
.A2_N(A2_N),
.B1(B1),
.B2(B2)
);
endmodule
|
module uart6_atlys (
input uart_rx,
output uart_tx,
output [7:0] led,
input [7:0] switch,
input reset_b,
input clk );
//
///////////////////////////////////////////////////////////////////////////////////////////
// Signals
///////////////////////////////////////////////////////////////////////////////////////////
//
// Signals used to connect KCPSM6
wire [11:0] address;
wire [17:0] instruction;
wire bram_enable;
reg [7:0] in_port;
wire [7:0] out_port;
wire [7:0] port_id;
wire write_strobe;
wire k_write_strobe;
wire read_strobe;
reg interrupt;
wire interrupt_ack;
wire kcpsm6_sleep;
wire kcpsm6_reset;
wire rdl;
// Signals used to connect UART_TX6
wire [7:0] uart_tx_data_in;
wire write_to_uart_tx;
wire uart_tx_data_present;
wire uart_tx_half_full;
wire uart_tx_full;
reg uart_tx_reset;
// Signals used to connect UART_RX6
wire [7:0] uart_rx_data_out;
reg read_from_uart_rx;
wire uart_rx_data_present;
wire uart_rx_half_full;
wire uart_rx_full;
reg uart_rx_reset;
// Signals used to define baud rate
reg [5:0] baud_count;
reg en_16_x_baud;
// Signals to drive LEDs
reg [7:0] led_port;
// Signals used to generate interrupt at one second intervals
reg [26:0] int_count;
reg event_1hz;
//
//
///////////////////////////////////////////////////////////////////////////////////////////
//
// Start of circuit description
//
///////////////////////////////////////////////////////////////////////////////////////////
//
/////////////////////////////////////////////////////////////////////////////////////////
// Instantiate KCPSM6 and connect to program ROM
/////////////////////////////////////////////////////////////////////////////////////////
//
// The generics can be defined as required. In this case the 'hwbuild' value is used to
// define a version using the ASCII code for the desired letter and the interrupt vector
// has been set to 3C0 to provide 64 instructions for an Interrupt Service Routine (ISR)
// before reaching the end of a 1K memory
//
kcpsm6 #(
.interrupt_vector (12'h3C0),
.scratch_pad_memory_size(64),
.hwbuild (8'h41)) // 41 hex is ASCII Character "A"
processor (
.address (address),
.instruction (instruction),
.bram_enable (bram_enable),
.port_id (port_id),
.write_strobe (write_strobe),
.k_write_strobe (k_write_strobe),
.out_port (out_port),
.read_strobe (read_strobe),
.in_port (in_port),
.interrupt (interrupt),
.interrupt_ack (interrupt_ack),
.reset (kcpsm6_reset),
.sleep (kcpsm6_sleep),
.clk (clk));
// Reset by press button (active Low) or JTAG Loader enabled Program Memory
assign kcpsm6_reset = rdl | ~reset_b;
// Unused signals tied off until required.
// Tying to other signals used to minimise warning messages.
assign kcpsm6_sleep = write_strobe & k_write_strobe; // Always '0'
// Development Program Memory
// JTAG Loader enabled for rapid code development.
atlys_real_time_clock #(
.C_FAMILY ("S6"),
.C_RAM_SIZE_KWORDS (1),
.C_JTAG_LOADER_ENABLE (1))
program_rom (
.rdl (rdl),
.enable (bram_enable),
.address (address),
.instruction (instruction),
.clk (clk));
/////////////////////////////////////////////////////////////////////////////////////////
// Interrupt control
/////////////////////////////////////////////////////////////////////////////////////////
//
// Interrupt is used to provide a 1 second time reference.
//
// A simple binary counter is used to divide the 100MHz clock and provide
// interrupt pulses that remain active until acknowledged by KCPSM6.
//
always @ (posedge clk )
begin
// divide 100MHz by 100,000,000 to form 1Hz pulses
if (int_count == 27'b101111101011110000011111111) begin
int_count <= 27'b000000000000000000000000000;
event_1hz <= 1'b1; // single cycle enable pulse
end
else begin
int_count <= int_count + 27'b000000000000000000000000001;
event_1hz <= 1'b0;
end
// Interrupt becomes active each second and remains active until acknowledged
if (interrupt_ack == 1'b1) begin
interrupt <= 1'b0;
end
else begin
if (event_1hz == 1'b1) begin
interrupt <= 1'b1;
end
else begin
interrupt <= interrupt;
end
end
end
/////////////////////////////////////////////////////////////////////////////////////////
// UART Transmitter with integral 16 byte FIFO buffer
/////////////////////////////////////////////////////////////////////////////////////////
//
// Write to buffer in UART Transmitter at port address 01 hex
//
uart_tx6 tx(
.data_in(uart_tx_data_in),
.en_16_x_baud(en_16_x_baud),
.serial_out(uart_tx),
.buffer_write(write_to_uart_tx),
.buffer_data_present(uart_tx_data_present),
.buffer_half_full(uart_tx_half_full ),
.buffer_full(uart_tx_full),
.buffer_reset(uart_tx_reset),
.clk(clk));
/////////////////////////////////////////////////////////////////////////////////////////
// UART Receiver with integral 16 byte FIFO buffer
/////////////////////////////////////////////////////////////////////////////////////////
//
// Read from buffer in UART Receiver at port address 01 hex.
//
// When KCPMS6 reads data from the receiver a pulse must be generated so that the
// FIFO buffer presents the next character to be read and updates the buffer flags.
//
uart_rx6 rx(
.serial_in(uart_rx),
.en_16_x_baud(en_16_x_baud ),
.data_out(uart_rx_data_out ),
.buffer_read(read_from_uart_rx ),
.buffer_data_present(uart_rx_data_present ),
.buffer_half_full(uart_rx_half_full ),
.buffer_full(uart_rx_full ),
.buffer_reset(uart_rx_reset ),
.clk(clk ));
//
/////////////////////////////////////////////////////////////////////////////////////////
// RS232 (UART) baud rate
/////////////////////////////////////////////////////////////////////////////////////////
//
// To set serial communication baud rate to 115,200 then en_16_x_baud must pulse
// High at 1,843,200Hz which is every 54.28 cycles at 100MHz. In this implementation
// a pulse is generated every 54 cycles resulting is a baud rate of 115,741 baud which
// is only 0.5% high and well within limits.
//
always @ (posedge clk )
begin
if (baud_count == 6'b110101) begin // counts 54 states including zero
baud_count <= 6'b000000;
en_16_x_baud <= 1'b1; // single cycle enable pulse
end
else begin
baud_count <= baud_count + 6'b000001;
en_16_x_baud <= 1'b0;
end
end
//
/////////////////////////////////////////////////////////////////////////////////////////
// General Purpose Input Ports.
/////////////////////////////////////////////////////////////////////////////////////////
//
// Two input ports are used with the UART macros. The first is used to monitor the flags
// on both the UART transmitter and receiver. The second is used to read the data from
// the UART receiver. Note that the read also requires a 'buffer_read' pulse to be
// generated.
//
// This design includes a third input port to read 8 general purpose switches.
//
always @ (posedge clk)
begin
case (port_id[1:0])
// Read UART status at port address 00 hex
2'b00 : in_port <= { 2'b00,
uart_rx_full,
uart_rx_half_full,
uart_rx_data_present,
uart_tx_full,
uart_tx_half_full,
uart_tx_data_present };
// Read UART_RX6 data at port address 01 hex
// (see 'buffer_read' pulse generation below)
2'b01 : in_port <= uart_rx_data_out;
// Read 8 general purpose switches at port address 02 hex
2'b10 : in_port <= switch;
// Don't Care for unused case(s) ensures minimum logic implementation
default : in_port <= 8'bXXXXXXXX ;
endcase;
// Generate 'buffer_read' pulse following read from port address 01
if ((read_strobe == 1'b1) && (port_id[1:0] == 2'b01)) begin
read_from_uart_rx <= 1'b1;
end
else begin
read_from_uart_rx <= 1'b0;
end
end
//
/////////////////////////////////////////////////////////////////////////////////////////
// General Purpose Output Ports
/////////////////////////////////////////////////////////////////////////////////////////
//
// In this simple example there are two output ports.
// A simple output port used to control a set of 8 general purpose LEDs.
// A port used to write data directly to the FIFO buffer within 'uart_tx6' macro.
//
// LEDs are connected to a typical KCPSM6 output port.
// i.e. A register and associated decode logic to enable data capture.
always @ (posedge clk)
begin
// 'write_strobe' is used to qualify all writes to general output ports.
if (write_strobe == 1'b1) begin
// Write to LEDs at port address 02 hex
if (port_id[1] == 1'b1) begin
led_port <= out_port;
end
end
end
// Connect KCPSM6 port to device output pins
assign led = led_port;
// Write directly to the FIFO buffer within 'uart_tx6' macro at port address 01 hex.
// Note the direct connection of 'out_port' to the UART transmitter macro and the
// way that a single clock cycle write pulse is generated to capture the data.
assign uart_tx_data_in = out_port;
assign write_to_uart_tx = write_strobe & port_id[0];
//
/////////////////////////////////////////////////////////////////////////////////////////
// Constant-Optimised Output Ports
/////////////////////////////////////////////////////////////////////////////////////////
//
// One constant-optimised output port is used to facilitate resetting of the UART macros.
//
always @ (posedge clk)
begin
if (k_write_strobe == 1'b1) begin
if (port_id[0] == 1'b1) begin
uart_tx_reset <= out_port[0];
uart_rx_reset <= out_port[1];
end
end
end
/////////////////////////////////////////////////////////////////////////////////////////
endmodule
|
module ledtest (
input wire clk_clk, // clk.clk
output wire hps_io_hps_io_emac1_inst_TX_CLK, // hps_io.hps_io_emac1_inst_TX_CLK
output wire hps_io_hps_io_emac1_inst_TXD0, // .hps_io_emac1_inst_TXD0
output wire hps_io_hps_io_emac1_inst_TXD1, // .hps_io_emac1_inst_TXD1
output wire hps_io_hps_io_emac1_inst_TXD2, // .hps_io_emac1_inst_TXD2
output wire hps_io_hps_io_emac1_inst_TXD3, // .hps_io_emac1_inst_TXD3
input wire hps_io_hps_io_emac1_inst_RXD0, // .hps_io_emac1_inst_RXD0
inout wire hps_io_hps_io_emac1_inst_MDIO, // .hps_io_emac1_inst_MDIO
output wire hps_io_hps_io_emac1_inst_MDC, // .hps_io_emac1_inst_MDC
input wire hps_io_hps_io_emac1_inst_RX_CTL, // .hps_io_emac1_inst_RX_CTL
output wire hps_io_hps_io_emac1_inst_TX_CTL, // .hps_io_emac1_inst_TX_CTL
input wire hps_io_hps_io_emac1_inst_RX_CLK, // .hps_io_emac1_inst_RX_CLK
input wire hps_io_hps_io_emac1_inst_RXD1, // .hps_io_emac1_inst_RXD1
input wire hps_io_hps_io_emac1_inst_RXD2, // .hps_io_emac1_inst_RXD2
input wire hps_io_hps_io_emac1_inst_RXD3, // .hps_io_emac1_inst_RXD3
output wire jtag_debug_master_reset_reset, // jtag_debug_master_reset.reset
output wire [7:0] led_array_io_export, // led_array_io.export
output wire [14:0] memory_mem_a, // memory.mem_a
output wire [2:0] memory_mem_ba, // .mem_ba
output wire memory_mem_ck, // .mem_ck
output wire memory_mem_ck_n, // .mem_ck_n
output wire memory_mem_cke, // .mem_cke
output wire memory_mem_cs_n, // .mem_cs_n
output wire memory_mem_ras_n, // .mem_ras_n
output wire memory_mem_cas_n, // .mem_cas_n
output wire memory_mem_we_n, // .mem_we_n
output wire memory_mem_reset_n, // .mem_reset_n
inout wire [31:0] memory_mem_dq, // .mem_dq
inout wire [3:0] memory_mem_dqs, // .mem_dqs
inout wire [3:0] memory_mem_dqs_n, // .mem_dqs_n
output wire memory_mem_odt, // .mem_odt
output wire [3:0] memory_mem_dm, // .mem_dm
input wire memory_oct_rzqin, // .oct_rzqin
input wire [3:0] switch_array_io_export // switch_array_io.export
);
wire arm_mcu_h2f_reset_reset; // ARM_MCU:h2f_rst_n -> [JTAG_DEBUG:clk_reset_reset, rst_controller:reset_in0, rst_controller_001:reset_in0]
wire [1:0] arm_mcu_h2f_lw_axi_master_awburst; // ARM_MCU:h2f_lw_AWBURST -> mm_interconnect_0:ARM_MCU_h2f_lw_axi_master_awburst
wire [3:0] arm_mcu_h2f_lw_axi_master_arlen; // ARM_MCU:h2f_lw_ARLEN -> mm_interconnect_0:ARM_MCU_h2f_lw_axi_master_arlen
wire [3:0] arm_mcu_h2f_lw_axi_master_wstrb; // ARM_MCU:h2f_lw_WSTRB -> mm_interconnect_0:ARM_MCU_h2f_lw_axi_master_wstrb
wire arm_mcu_h2f_lw_axi_master_wready; // mm_interconnect_0:ARM_MCU_h2f_lw_axi_master_wready -> ARM_MCU:h2f_lw_WREADY
wire [11:0] arm_mcu_h2f_lw_axi_master_rid; // mm_interconnect_0:ARM_MCU_h2f_lw_axi_master_rid -> ARM_MCU:h2f_lw_RID
wire arm_mcu_h2f_lw_axi_master_rready; // ARM_MCU:h2f_lw_RREADY -> mm_interconnect_0:ARM_MCU_h2f_lw_axi_master_rready
wire [3:0] arm_mcu_h2f_lw_axi_master_awlen; // ARM_MCU:h2f_lw_AWLEN -> mm_interconnect_0:ARM_MCU_h2f_lw_axi_master_awlen
wire [11:0] arm_mcu_h2f_lw_axi_master_wid; // ARM_MCU:h2f_lw_WID -> mm_interconnect_0:ARM_MCU_h2f_lw_axi_master_wid
wire [3:0] arm_mcu_h2f_lw_axi_master_arcache; // ARM_MCU:h2f_lw_ARCACHE -> mm_interconnect_0:ARM_MCU_h2f_lw_axi_master_arcache
wire arm_mcu_h2f_lw_axi_master_wvalid; // ARM_MCU:h2f_lw_WVALID -> mm_interconnect_0:ARM_MCU_h2f_lw_axi_master_wvalid
wire [20:0] arm_mcu_h2f_lw_axi_master_araddr; // ARM_MCU:h2f_lw_ARADDR -> mm_interconnect_0:ARM_MCU_h2f_lw_axi_master_araddr
wire [2:0] arm_mcu_h2f_lw_axi_master_arprot; // ARM_MCU:h2f_lw_ARPROT -> mm_interconnect_0:ARM_MCU_h2f_lw_axi_master_arprot
wire [2:0] arm_mcu_h2f_lw_axi_master_awprot; // ARM_MCU:h2f_lw_AWPROT -> mm_interconnect_0:ARM_MCU_h2f_lw_axi_master_awprot
wire [31:0] arm_mcu_h2f_lw_axi_master_wdata; // ARM_MCU:h2f_lw_WDATA -> mm_interconnect_0:ARM_MCU_h2f_lw_axi_master_wdata
wire arm_mcu_h2f_lw_axi_master_arvalid; // ARM_MCU:h2f_lw_ARVALID -> mm_interconnect_0:ARM_MCU_h2f_lw_axi_master_arvalid
wire [3:0] arm_mcu_h2f_lw_axi_master_awcache; // ARM_MCU:h2f_lw_AWCACHE -> mm_interconnect_0:ARM_MCU_h2f_lw_axi_master_awcache
wire [11:0] arm_mcu_h2f_lw_axi_master_arid; // ARM_MCU:h2f_lw_ARID -> mm_interconnect_0:ARM_MCU_h2f_lw_axi_master_arid
wire [1:0] arm_mcu_h2f_lw_axi_master_arlock; // ARM_MCU:h2f_lw_ARLOCK -> mm_interconnect_0:ARM_MCU_h2f_lw_axi_master_arlock
wire [1:0] arm_mcu_h2f_lw_axi_master_awlock; // ARM_MCU:h2f_lw_AWLOCK -> mm_interconnect_0:ARM_MCU_h2f_lw_axi_master_awlock
wire [20:0] arm_mcu_h2f_lw_axi_master_awaddr; // ARM_MCU:h2f_lw_AWADDR -> mm_interconnect_0:ARM_MCU_h2f_lw_axi_master_awaddr
wire [1:0] arm_mcu_h2f_lw_axi_master_bresp; // mm_interconnect_0:ARM_MCU_h2f_lw_axi_master_bresp -> ARM_MCU:h2f_lw_BRESP
wire arm_mcu_h2f_lw_axi_master_arready; // mm_interconnect_0:ARM_MCU_h2f_lw_axi_master_arready -> ARM_MCU:h2f_lw_ARREADY
wire [31:0] arm_mcu_h2f_lw_axi_master_rdata; // mm_interconnect_0:ARM_MCU_h2f_lw_axi_master_rdata -> ARM_MCU:h2f_lw_RDATA
wire arm_mcu_h2f_lw_axi_master_awready; // mm_interconnect_0:ARM_MCU_h2f_lw_axi_master_awready -> ARM_MCU:h2f_lw_AWREADY
wire [1:0] arm_mcu_h2f_lw_axi_master_arburst; // ARM_MCU:h2f_lw_ARBURST -> mm_interconnect_0:ARM_MCU_h2f_lw_axi_master_arburst
wire [2:0] arm_mcu_h2f_lw_axi_master_arsize; // ARM_MCU:h2f_lw_ARSIZE -> mm_interconnect_0:ARM_MCU_h2f_lw_axi_master_arsize
wire arm_mcu_h2f_lw_axi_master_bready; // ARM_MCU:h2f_lw_BREADY -> mm_interconnect_0:ARM_MCU_h2f_lw_axi_master_bready
wire arm_mcu_h2f_lw_axi_master_rlast; // mm_interconnect_0:ARM_MCU_h2f_lw_axi_master_rlast -> ARM_MCU:h2f_lw_RLAST
wire arm_mcu_h2f_lw_axi_master_wlast; // ARM_MCU:h2f_lw_WLAST -> mm_interconnect_0:ARM_MCU_h2f_lw_axi_master_wlast
wire [1:0] arm_mcu_h2f_lw_axi_master_rresp; // mm_interconnect_0:ARM_MCU_h2f_lw_axi_master_rresp -> ARM_MCU:h2f_lw_RRESP
wire [11:0] arm_mcu_h2f_lw_axi_master_awid; // ARM_MCU:h2f_lw_AWID -> mm_interconnect_0:ARM_MCU_h2f_lw_axi_master_awid
wire [11:0] arm_mcu_h2f_lw_axi_master_bid; // mm_interconnect_0:ARM_MCU_h2f_lw_axi_master_bid -> ARM_MCU:h2f_lw_BID
wire arm_mcu_h2f_lw_axi_master_bvalid; // mm_interconnect_0:ARM_MCU_h2f_lw_axi_master_bvalid -> ARM_MCU:h2f_lw_BVALID
wire [2:0] arm_mcu_h2f_lw_axi_master_awsize; // ARM_MCU:h2f_lw_AWSIZE -> mm_interconnect_0:ARM_MCU_h2f_lw_axi_master_awsize
wire arm_mcu_h2f_lw_axi_master_awvalid; // ARM_MCU:h2f_lw_AWVALID -> mm_interconnect_0:ARM_MCU_h2f_lw_axi_master_awvalid
wire arm_mcu_h2f_lw_axi_master_rvalid; // mm_interconnect_0:ARM_MCU_h2f_lw_axi_master_rvalid -> ARM_MCU:h2f_lw_RVALID
wire [31:0] mm_interconnect_0_mm_bridge_s0_readdata; // MM_BRIDGE:s0_readdata -> mm_interconnect_0:MM_BRIDGE_s0_readdata
wire mm_interconnect_0_mm_bridge_s0_waitrequest; // MM_BRIDGE:s0_waitrequest -> mm_interconnect_0:MM_BRIDGE_s0_waitrequest
wire mm_interconnect_0_mm_bridge_s0_debugaccess; // mm_interconnect_0:MM_BRIDGE_s0_debugaccess -> MM_BRIDGE:s0_debugaccess
wire [4:0] mm_interconnect_0_mm_bridge_s0_address; // mm_interconnect_0:MM_BRIDGE_s0_address -> MM_BRIDGE:s0_address
wire mm_interconnect_0_mm_bridge_s0_read; // mm_interconnect_0:MM_BRIDGE_s0_read -> MM_BRIDGE:s0_read
wire [3:0] mm_interconnect_0_mm_bridge_s0_byteenable; // mm_interconnect_0:MM_BRIDGE_s0_byteenable -> MM_BRIDGE:s0_byteenable
wire mm_interconnect_0_mm_bridge_s0_readdatavalid; // MM_BRIDGE:s0_readdatavalid -> mm_interconnect_0:MM_BRIDGE_s0_readdatavalid
wire mm_interconnect_0_mm_bridge_s0_write; // mm_interconnect_0:MM_BRIDGE_s0_write -> MM_BRIDGE:s0_write
wire [31:0] mm_interconnect_0_mm_bridge_s0_writedata; // mm_interconnect_0:MM_BRIDGE_s0_writedata -> MM_BRIDGE:s0_writedata
wire [0:0] mm_interconnect_0_mm_bridge_s0_burstcount; // mm_interconnect_0:MM_BRIDGE_s0_burstcount -> MM_BRIDGE:s0_burstcount
wire mm_bridge_m0_waitrequest; // mm_interconnect_1:MM_BRIDGE_m0_waitrequest -> MM_BRIDGE:m0_waitrequest
wire [31:0] mm_bridge_m0_readdata; // mm_interconnect_1:MM_BRIDGE_m0_readdata -> MM_BRIDGE:m0_readdata
wire mm_bridge_m0_debugaccess; // MM_BRIDGE:m0_debugaccess -> mm_interconnect_1:MM_BRIDGE_m0_debugaccess
wire [4:0] mm_bridge_m0_address; // MM_BRIDGE:m0_address -> mm_interconnect_1:MM_BRIDGE_m0_address
wire mm_bridge_m0_read; // MM_BRIDGE:m0_read -> mm_interconnect_1:MM_BRIDGE_m0_read
wire [3:0] mm_bridge_m0_byteenable; // MM_BRIDGE:m0_byteenable -> mm_interconnect_1:MM_BRIDGE_m0_byteenable
wire mm_bridge_m0_readdatavalid; // mm_interconnect_1:MM_BRIDGE_m0_readdatavalid -> MM_BRIDGE:m0_readdatavalid
wire [31:0] mm_bridge_m0_writedata; // MM_BRIDGE:m0_writedata -> mm_interconnect_1:MM_BRIDGE_m0_writedata
wire mm_bridge_m0_write; // MM_BRIDGE:m0_write -> mm_interconnect_1:MM_BRIDGE_m0_write
wire [0:0] mm_bridge_m0_burstcount; // MM_BRIDGE:m0_burstcount -> mm_interconnect_1:MM_BRIDGE_m0_burstcount
wire mm_interconnect_1_led_array_s1_chipselect; // mm_interconnect_1:LED_ARRAY_s1_chipselect -> LED_ARRAY:chipselect
wire [31:0] mm_interconnect_1_led_array_s1_readdata; // LED_ARRAY:readdata -> mm_interconnect_1:LED_ARRAY_s1_readdata
wire [1:0] mm_interconnect_1_led_array_s1_address; // mm_interconnect_1:LED_ARRAY_s1_address -> LED_ARRAY:address
wire mm_interconnect_1_led_array_s1_write; // mm_interconnect_1:LED_ARRAY_s1_write -> LED_ARRAY:write_n
wire [31:0] mm_interconnect_1_led_array_s1_writedata; // mm_interconnect_1:LED_ARRAY_s1_writedata -> LED_ARRAY:writedata
wire [31:0] mm_interconnect_1_switch_array_s1_readdata; // SWITCH_ARRAY:readdata -> mm_interconnect_1:SWITCH_ARRAY_s1_readdata
wire [1:0] mm_interconnect_1_switch_array_s1_address; // mm_interconnect_1:SWITCH_ARRAY_s1_address -> SWITCH_ARRAY:address
wire [31:0] jtag_debug_master_readdata; // mm_interconnect_2:JTAG_DEBUG_master_readdata -> JTAG_DEBUG:master_readdata
wire jtag_debug_master_waitrequest; // mm_interconnect_2:JTAG_DEBUG_master_waitrequest -> JTAG_DEBUG:master_waitrequest
wire [31:0] jtag_debug_master_address; // JTAG_DEBUG:master_address -> mm_interconnect_2:JTAG_DEBUG_master_address
wire jtag_debug_master_read; // JTAG_DEBUG:master_read -> mm_interconnect_2:JTAG_DEBUG_master_read
wire [3:0] jtag_debug_master_byteenable; // JTAG_DEBUG:master_byteenable -> mm_interconnect_2:JTAG_DEBUG_master_byteenable
wire jtag_debug_master_readdatavalid; // mm_interconnect_2:JTAG_DEBUG_master_readdatavalid -> JTAG_DEBUG:master_readdatavalid
wire jtag_debug_master_write; // JTAG_DEBUG:master_write -> mm_interconnect_2:JTAG_DEBUG_master_write
wire [31:0] jtag_debug_master_writedata; // JTAG_DEBUG:master_writedata -> mm_interconnect_2:JTAG_DEBUG_master_writedata
wire [255:0] mm_interconnect_2_arm_mcu_f2h_sdram0_data_readdata; // ARM_MCU:f2h_sdram0_READDATA -> mm_interconnect_2:ARM_MCU_f2h_sdram0_data_readdata
wire mm_interconnect_2_arm_mcu_f2h_sdram0_data_waitrequest; // ARM_MCU:f2h_sdram0_WAITREQUEST -> mm_interconnect_2:ARM_MCU_f2h_sdram0_data_waitrequest
wire [26:0] mm_interconnect_2_arm_mcu_f2h_sdram0_data_address; // mm_interconnect_2:ARM_MCU_f2h_sdram0_data_address -> ARM_MCU:f2h_sdram0_ADDRESS
wire mm_interconnect_2_arm_mcu_f2h_sdram0_data_read; // mm_interconnect_2:ARM_MCU_f2h_sdram0_data_read -> ARM_MCU:f2h_sdram0_READ
wire [31:0] mm_interconnect_2_arm_mcu_f2h_sdram0_data_byteenable; // mm_interconnect_2:ARM_MCU_f2h_sdram0_data_byteenable -> ARM_MCU:f2h_sdram0_BYTEENABLE
wire mm_interconnect_2_arm_mcu_f2h_sdram0_data_readdatavalid; // ARM_MCU:f2h_sdram0_READDATAVALID -> mm_interconnect_2:ARM_MCU_f2h_sdram0_data_readdatavalid
wire mm_interconnect_2_arm_mcu_f2h_sdram0_data_write; // mm_interconnect_2:ARM_MCU_f2h_sdram0_data_write -> ARM_MCU:f2h_sdram0_WRITE
wire [255:0] mm_interconnect_2_arm_mcu_f2h_sdram0_data_writedata; // mm_interconnect_2:ARM_MCU_f2h_sdram0_data_writedata -> ARM_MCU:f2h_sdram0_WRITEDATA
wire [7:0] mm_interconnect_2_arm_mcu_f2h_sdram0_data_burstcount; // mm_interconnect_2:ARM_MCU_f2h_sdram0_data_burstcount -> ARM_MCU:f2h_sdram0_BURSTCOUNT
wire rst_controller_reset_out_reset; // rst_controller:reset_out -> [LED_ARRAY:reset_n, MM_BRIDGE:reset, SWITCH_ARRAY:reset_n, mm_interconnect_0:MM_BRIDGE_reset_reset_bridge_in_reset_reset, mm_interconnect_1:MM_BRIDGE_reset_reset_bridge_in_reset_reset, mm_interconnect_2:JTAG_DEBUG_clk_reset_reset_bridge_in_reset_reset, mm_interconnect_2:JTAG_DEBUG_master_translator_reset_reset_bridge_in_reset_reset]
wire rst_controller_001_reset_out_reset; // rst_controller_001:reset_out -> [mm_interconnect_0:ARM_MCU_h2f_lw_axi_master_agent_clk_reset_reset_bridge_in_reset_reset, mm_interconnect_2:ARM_MCU_f2h_sdram0_data_translator_reset_reset_bridge_in_reset_reset]
ledtest_ARM_MCU #(
.F2S_Width (0),
.S2F_Width (0)
) arm_mcu (
.f2h_sdram_ref_clk (clk_clk), // f2h_sdram_ref_clock.clk
.mem_a (memory_mem_a), // memory.mem_a
.mem_ba (memory_mem_ba), // .mem_ba
.mem_ck (memory_mem_ck), // .mem_ck
.mem_ck_n (memory_mem_ck_n), // .mem_ck_n
.mem_cke (memory_mem_cke), // .mem_cke
.mem_cs_n (memory_mem_cs_n), // .mem_cs_n
.mem_ras_n (memory_mem_ras_n), // .mem_ras_n
.mem_cas_n (memory_mem_cas_n), // .mem_cas_n
.mem_we_n (memory_mem_we_n), // .mem_we_n
.mem_reset_n (memory_mem_reset_n), // .mem_reset_n
.mem_dq (memory_mem_dq), // .mem_dq
.mem_dqs (memory_mem_dqs), // .mem_dqs
.mem_dqs_n (memory_mem_dqs_n), // .mem_dqs_n
.mem_odt (memory_mem_odt), // .mem_odt
.mem_dm (memory_mem_dm), // .mem_dm
.oct_rzqin (memory_oct_rzqin), // .oct_rzqin
.hps_io_emac1_inst_TX_CLK (hps_io_hps_io_emac1_inst_TX_CLK), // hps_io.hps_io_emac1_inst_TX_CLK
.hps_io_emac1_inst_TXD0 (hps_io_hps_io_emac1_inst_TXD0), // .hps_io_emac1_inst_TXD0
.hps_io_emac1_inst_TXD1 (hps_io_hps_io_emac1_inst_TXD1), // .hps_io_emac1_inst_TXD1
.hps_io_emac1_inst_TXD2 (hps_io_hps_io_emac1_inst_TXD2), // .hps_io_emac1_inst_TXD2
.hps_io_emac1_inst_TXD3 (hps_io_hps_io_emac1_inst_TXD3), // .hps_io_emac1_inst_TXD3
.hps_io_emac1_inst_RXD0 (hps_io_hps_io_emac1_inst_RXD0), // .hps_io_emac1_inst_RXD0
.hps_io_emac1_inst_MDIO (hps_io_hps_io_emac1_inst_MDIO), // .hps_io_emac1_inst_MDIO
.hps_io_emac1_inst_MDC (hps_io_hps_io_emac1_inst_MDC), // .hps_io_emac1_inst_MDC
.hps_io_emac1_inst_RX_CTL (hps_io_hps_io_emac1_inst_RX_CTL), // .hps_io_emac1_inst_RX_CTL
.hps_io_emac1_inst_TX_CTL (hps_io_hps_io_emac1_inst_TX_CTL), // .hps_io_emac1_inst_TX_CTL
.hps_io_emac1_inst_RX_CLK (hps_io_hps_io_emac1_inst_RX_CLK), // .hps_io_emac1_inst_RX_CLK
.hps_io_emac1_inst_RXD1 (hps_io_hps_io_emac1_inst_RXD1), // .hps_io_emac1_inst_RXD1
.hps_io_emac1_inst_RXD2 (hps_io_hps_io_emac1_inst_RXD2), // .hps_io_emac1_inst_RXD2
.hps_io_emac1_inst_RXD3 (hps_io_hps_io_emac1_inst_RXD3), // .hps_io_emac1_inst_RXD3
.h2f_rst_n (arm_mcu_h2f_reset_reset), // h2f_reset.reset_n
.f2h_sdram0_clk (clk_clk), // f2h_sdram0_clock.clk
.f2h_sdram0_ADDRESS (mm_interconnect_2_arm_mcu_f2h_sdram0_data_address), // f2h_sdram0_data.address
.f2h_sdram0_BURSTCOUNT (mm_interconnect_2_arm_mcu_f2h_sdram0_data_burstcount), // .burstcount
.f2h_sdram0_WAITREQUEST (mm_interconnect_2_arm_mcu_f2h_sdram0_data_waitrequest), // .waitrequest
.f2h_sdram0_READDATA (mm_interconnect_2_arm_mcu_f2h_sdram0_data_readdata), // .readdata
.f2h_sdram0_READDATAVALID (mm_interconnect_2_arm_mcu_f2h_sdram0_data_readdatavalid), // .readdatavalid
.f2h_sdram0_READ (mm_interconnect_2_arm_mcu_f2h_sdram0_data_read), // .read
.f2h_sdram0_WRITEDATA (mm_interconnect_2_arm_mcu_f2h_sdram0_data_writedata), // .writedata
.f2h_sdram0_BYTEENABLE (mm_interconnect_2_arm_mcu_f2h_sdram0_data_byteenable), // .byteenable
.f2h_sdram0_WRITE (mm_interconnect_2_arm_mcu_f2h_sdram0_data_write), // .write
.h2f_lw_axi_clk (clk_clk), // h2f_lw_axi_clock.clk
.h2f_lw_AWID (arm_mcu_h2f_lw_axi_master_awid), // h2f_lw_axi_master.awid
.h2f_lw_AWADDR (arm_mcu_h2f_lw_axi_master_awaddr), // .awaddr
.h2f_lw_AWLEN (arm_mcu_h2f_lw_axi_master_awlen), // .awlen
.h2f_lw_AWSIZE (arm_mcu_h2f_lw_axi_master_awsize), // .awsize
.h2f_lw_AWBURST (arm_mcu_h2f_lw_axi_master_awburst), // .awburst
.h2f_lw_AWLOCK (arm_mcu_h2f_lw_axi_master_awlock), // .awlock
.h2f_lw_AWCACHE (arm_mcu_h2f_lw_axi_master_awcache), // .awcache
.h2f_lw_AWPROT (arm_mcu_h2f_lw_axi_master_awprot), // .awprot
.h2f_lw_AWVALID (arm_mcu_h2f_lw_axi_master_awvalid), // .awvalid
.h2f_lw_AWREADY (arm_mcu_h2f_lw_axi_master_awready), // .awready
.h2f_lw_WID (arm_mcu_h2f_lw_axi_master_wid), // .wid
.h2f_lw_WDATA (arm_mcu_h2f_lw_axi_master_wdata), // .wdata
.h2f_lw_WSTRB (arm_mcu_h2f_lw_axi_master_wstrb), // .wstrb
.h2f_lw_WLAST (arm_mcu_h2f_lw_axi_master_wlast), // .wlast
.h2f_lw_WVALID (arm_mcu_h2f_lw_axi_master_wvalid), // .wvalid
.h2f_lw_WREADY (arm_mcu_h2f_lw_axi_master_wready), // .wready
.h2f_lw_BID (arm_mcu_h2f_lw_axi_master_bid), // .bid
.h2f_lw_BRESP (arm_mcu_h2f_lw_axi_master_bresp), // .bresp
.h2f_lw_BVALID (arm_mcu_h2f_lw_axi_master_bvalid), // .bvalid
.h2f_lw_BREADY (arm_mcu_h2f_lw_axi_master_bready), // .bready
.h2f_lw_ARID (arm_mcu_h2f_lw_axi_master_arid), // .arid
.h2f_lw_ARADDR (arm_mcu_h2f_lw_axi_master_araddr), // .araddr
.h2f_lw_ARLEN (arm_mcu_h2f_lw_axi_master_arlen), // .arlen
.h2f_lw_ARSIZE (arm_mcu_h2f_lw_axi_master_arsize), // .arsize
.h2f_lw_ARBURST (arm_mcu_h2f_lw_axi_master_arburst), // .arburst
.h2f_lw_ARLOCK (arm_mcu_h2f_lw_axi_master_arlock), // .arlock
.h2f_lw_ARCACHE (arm_mcu_h2f_lw_axi_master_arcache), // .arcache
.h2f_lw_ARPROT (arm_mcu_h2f_lw_axi_master_arprot), // .arprot
.h2f_lw_ARVALID (arm_mcu_h2f_lw_axi_master_arvalid), // .arvalid
.h2f_lw_ARREADY (arm_mcu_h2f_lw_axi_master_arready), // .arready
.h2f_lw_RID (arm_mcu_h2f_lw_axi_master_rid), // .rid
.h2f_lw_RDATA (arm_mcu_h2f_lw_axi_master_rdata), // .rdata
.h2f_lw_RRESP (arm_mcu_h2f_lw_axi_master_rresp), // .rresp
.h2f_lw_RLAST (arm_mcu_h2f_lw_axi_master_rlast), // .rlast
.h2f_lw_RVALID (arm_mcu_h2f_lw_axi_master_rvalid), // .rvalid
.h2f_lw_RREADY (arm_mcu_h2f_lw_axi_master_rready) // .rready
);
ledtest_JTAG_DEBUG #(
.USE_PLI (0),
.PLI_PORT (50000),
.FIFO_DEPTHS (2)
) jtag_debug (
.clk_clk (clk_clk), // clk.clk
.clk_reset_reset (~arm_mcu_h2f_reset_reset), // clk_reset.reset
.master_address (jtag_debug_master_address), // master.address
.master_readdata (jtag_debug_master_readdata), // .readdata
.master_read (jtag_debug_master_read), // .read
.master_write (jtag_debug_master_write), // .write
.master_writedata (jtag_debug_master_writedata), // .writedata
.master_waitrequest (jtag_debug_master_waitrequest), // .waitrequest
.master_readdatavalid (jtag_debug_master_readdatavalid), // .readdatavalid
.master_byteenable (jtag_debug_master_byteenable), // .byteenable
.master_reset_reset (jtag_debug_master_reset_reset) // master_reset.reset
);
ledtest_LED_ARRAY led_array (
.clk (clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.address (mm_interconnect_1_led_array_s1_address), // s1.address
.write_n (~mm_interconnect_1_led_array_s1_write), // .write_n
.writedata (mm_interconnect_1_led_array_s1_writedata), // .writedata
.chipselect (mm_interconnect_1_led_array_s1_chipselect), // .chipselect
.readdata (mm_interconnect_1_led_array_s1_readdata), // .readdata
.out_port (led_array_io_export) // external_connection.export
);
altera_avalon_mm_bridge #(
.DATA_WIDTH (32),
.SYMBOL_WIDTH (8),
.HDL_ADDR_WIDTH (5),
.BURSTCOUNT_WIDTH (1),
.PIPELINE_COMMAND (1),
.PIPELINE_RESPONSE (1)
) mm_bridge (
.clk (clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // reset.reset
.s0_waitrequest (mm_interconnect_0_mm_bridge_s0_waitrequest), // s0.waitrequest
.s0_readdata (mm_interconnect_0_mm_bridge_s0_readdata), // .readdata
.s0_readdatavalid (mm_interconnect_0_mm_bridge_s0_readdatavalid), // .readdatavalid
.s0_burstcount (mm_interconnect_0_mm_bridge_s0_burstcount), // .burstcount
.s0_writedata (mm_interconnect_0_mm_bridge_s0_writedata), // .writedata
.s0_address (mm_interconnect_0_mm_bridge_s0_address), // .address
.s0_write (mm_interconnect_0_mm_bridge_s0_write), // .write
.s0_read (mm_interconnect_0_mm_bridge_s0_read), // .read
.s0_byteenable (mm_interconnect_0_mm_bridge_s0_byteenable), // .byteenable
.s0_debugaccess (mm_interconnect_0_mm_bridge_s0_debugaccess), // .debugaccess
.m0_waitrequest (mm_bridge_m0_waitrequest), // m0.waitrequest
.m0_readdata (mm_bridge_m0_readdata), // .readdata
.m0_readdatavalid (mm_bridge_m0_readdatavalid), // .readdatavalid
.m0_burstcount (mm_bridge_m0_burstcount), // .burstcount
.m0_writedata (mm_bridge_m0_writedata), // .writedata
.m0_address (mm_bridge_m0_address), // .address
.m0_write (mm_bridge_m0_write), // .write
.m0_read (mm_bridge_m0_read), // .read
.m0_byteenable (mm_bridge_m0_byteenable), // .byteenable
.m0_debugaccess (mm_bridge_m0_debugaccess), // .debugaccess
.s0_response (), // (terminated)
.m0_response (2'b00) // (terminated)
);
ledtest_SWITCH_ARRAY switch_array (
.clk (clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.address (mm_interconnect_1_switch_array_s1_address), // s1.address
.readdata (mm_interconnect_1_switch_array_s1_readdata), // .readdata
.in_port (switch_array_io_export) // external_connection.export
);
ledtest_mm_interconnect_0 mm_interconnect_0 (
.ARM_MCU_h2f_lw_axi_master_awid (arm_mcu_h2f_lw_axi_master_awid), // ARM_MCU_h2f_lw_axi_master.awid
.ARM_MCU_h2f_lw_axi_master_awaddr (arm_mcu_h2f_lw_axi_master_awaddr), // .awaddr
.ARM_MCU_h2f_lw_axi_master_awlen (arm_mcu_h2f_lw_axi_master_awlen), // .awlen
.ARM_MCU_h2f_lw_axi_master_awsize (arm_mcu_h2f_lw_axi_master_awsize), // .awsize
.ARM_MCU_h2f_lw_axi_master_awburst (arm_mcu_h2f_lw_axi_master_awburst), // .awburst
.ARM_MCU_h2f_lw_axi_master_awlock (arm_mcu_h2f_lw_axi_master_awlock), // .awlock
.ARM_MCU_h2f_lw_axi_master_awcache (arm_mcu_h2f_lw_axi_master_awcache), // .awcache
.ARM_MCU_h2f_lw_axi_master_awprot (arm_mcu_h2f_lw_axi_master_awprot), // .awprot
.ARM_MCU_h2f_lw_axi_master_awvalid (arm_mcu_h2f_lw_axi_master_awvalid), // .awvalid
.ARM_MCU_h2f_lw_axi_master_awready (arm_mcu_h2f_lw_axi_master_awready), // .awready
.ARM_MCU_h2f_lw_axi_master_wid (arm_mcu_h2f_lw_axi_master_wid), // .wid
.ARM_MCU_h2f_lw_axi_master_wdata (arm_mcu_h2f_lw_axi_master_wdata), // .wdata
.ARM_MCU_h2f_lw_axi_master_wstrb (arm_mcu_h2f_lw_axi_master_wstrb), // .wstrb
.ARM_MCU_h2f_lw_axi_master_wlast (arm_mcu_h2f_lw_axi_master_wlast), // .wlast
.ARM_MCU_h2f_lw_axi_master_wvalid (arm_mcu_h2f_lw_axi_master_wvalid), // .wvalid
.ARM_MCU_h2f_lw_axi_master_wready (arm_mcu_h2f_lw_axi_master_wready), // .wready
.ARM_MCU_h2f_lw_axi_master_bid (arm_mcu_h2f_lw_axi_master_bid), // .bid
.ARM_MCU_h2f_lw_axi_master_bresp (arm_mcu_h2f_lw_axi_master_bresp), // .bresp
.ARM_MCU_h2f_lw_axi_master_bvalid (arm_mcu_h2f_lw_axi_master_bvalid), // .bvalid
.ARM_MCU_h2f_lw_axi_master_bready (arm_mcu_h2f_lw_axi_master_bready), // .bready
.ARM_MCU_h2f_lw_axi_master_arid (arm_mcu_h2f_lw_axi_master_arid), // .arid
.ARM_MCU_h2f_lw_axi_master_araddr (arm_mcu_h2f_lw_axi_master_araddr), // .araddr
.ARM_MCU_h2f_lw_axi_master_arlen (arm_mcu_h2f_lw_axi_master_arlen), // .arlen
.ARM_MCU_h2f_lw_axi_master_arsize (arm_mcu_h2f_lw_axi_master_arsize), // .arsize
.ARM_MCU_h2f_lw_axi_master_arburst (arm_mcu_h2f_lw_axi_master_arburst), // .arburst
.ARM_MCU_h2f_lw_axi_master_arlock (arm_mcu_h2f_lw_axi_master_arlock), // .arlock
.ARM_MCU_h2f_lw_axi_master_arcache (arm_mcu_h2f_lw_axi_master_arcache), // .arcache
.ARM_MCU_h2f_lw_axi_master_arprot (arm_mcu_h2f_lw_axi_master_arprot), // .arprot
.ARM_MCU_h2f_lw_axi_master_arvalid (arm_mcu_h2f_lw_axi_master_arvalid), // .arvalid
.ARM_MCU_h2f_lw_axi_master_arready (arm_mcu_h2f_lw_axi_master_arready), // .arready
.ARM_MCU_h2f_lw_axi_master_rid (arm_mcu_h2f_lw_axi_master_rid), // .rid
.ARM_MCU_h2f_lw_axi_master_rdata (arm_mcu_h2f_lw_axi_master_rdata), // .rdata
.ARM_MCU_h2f_lw_axi_master_rresp (arm_mcu_h2f_lw_axi_master_rresp), // .rresp
.ARM_MCU_h2f_lw_axi_master_rlast (arm_mcu_h2f_lw_axi_master_rlast), // .rlast
.ARM_MCU_h2f_lw_axi_master_rvalid (arm_mcu_h2f_lw_axi_master_rvalid), // .rvalid
.ARM_MCU_h2f_lw_axi_master_rready (arm_mcu_h2f_lw_axi_master_rready), // .rready
.CLOCK_clk_clk (clk_clk), // CLOCK_clk.clk
.ARM_MCU_h2f_lw_axi_master_agent_clk_reset_reset_bridge_in_reset_reset (rst_controller_001_reset_out_reset), // ARM_MCU_h2f_lw_axi_master_agent_clk_reset_reset_bridge_in_reset.reset
.MM_BRIDGE_reset_reset_bridge_in_reset_reset (rst_controller_reset_out_reset), // MM_BRIDGE_reset_reset_bridge_in_reset.reset
.MM_BRIDGE_s0_address (mm_interconnect_0_mm_bridge_s0_address), // MM_BRIDGE_s0.address
.MM_BRIDGE_s0_write (mm_interconnect_0_mm_bridge_s0_write), // .write
.MM_BRIDGE_s0_read (mm_interconnect_0_mm_bridge_s0_read), // .read
.MM_BRIDGE_s0_readdata (mm_interconnect_0_mm_bridge_s0_readdata), // .readdata
.MM_BRIDGE_s0_writedata (mm_interconnect_0_mm_bridge_s0_writedata), // .writedata
.MM_BRIDGE_s0_burstcount (mm_interconnect_0_mm_bridge_s0_burstcount), // .burstcount
.MM_BRIDGE_s0_byteenable (mm_interconnect_0_mm_bridge_s0_byteenable), // .byteenable
.MM_BRIDGE_s0_readdatavalid (mm_interconnect_0_mm_bridge_s0_readdatavalid), // .readdatavalid
.MM_BRIDGE_s0_waitrequest (mm_interconnect_0_mm_bridge_s0_waitrequest), // .waitrequest
.MM_BRIDGE_s0_debugaccess (mm_interconnect_0_mm_bridge_s0_debugaccess) // .debugaccess
);
ledtest_mm_interconnect_1 mm_interconnect_1 (
.CLOCK_clk_clk (clk_clk), // CLOCK_clk.clk
.MM_BRIDGE_reset_reset_bridge_in_reset_reset (rst_controller_reset_out_reset), // MM_BRIDGE_reset_reset_bridge_in_reset.reset
.MM_BRIDGE_m0_address (mm_bridge_m0_address), // MM_BRIDGE_m0.address
.MM_BRIDGE_m0_waitrequest (mm_bridge_m0_waitrequest), // .waitrequest
.MM_BRIDGE_m0_burstcount (mm_bridge_m0_burstcount), // .burstcount
.MM_BRIDGE_m0_byteenable (mm_bridge_m0_byteenable), // .byteenable
.MM_BRIDGE_m0_read (mm_bridge_m0_read), // .read
.MM_BRIDGE_m0_readdata (mm_bridge_m0_readdata), // .readdata
.MM_BRIDGE_m0_readdatavalid (mm_bridge_m0_readdatavalid), // .readdatavalid
.MM_BRIDGE_m0_write (mm_bridge_m0_write), // .write
.MM_BRIDGE_m0_writedata (mm_bridge_m0_writedata), // .writedata
.MM_BRIDGE_m0_debugaccess (mm_bridge_m0_debugaccess), // .debugaccess
.LED_ARRAY_s1_address (mm_interconnect_1_led_array_s1_address), // LED_ARRAY_s1.address
.LED_ARRAY_s1_write (mm_interconnect_1_led_array_s1_write), // .write
.LED_ARRAY_s1_readdata (mm_interconnect_1_led_array_s1_readdata), // .readdata
.LED_ARRAY_s1_writedata (mm_interconnect_1_led_array_s1_writedata), // .writedata
.LED_ARRAY_s1_chipselect (mm_interconnect_1_led_array_s1_chipselect), // .chipselect
.SWITCH_ARRAY_s1_address (mm_interconnect_1_switch_array_s1_address), // SWITCH_ARRAY_s1.address
.SWITCH_ARRAY_s1_readdata (mm_interconnect_1_switch_array_s1_readdata) // .readdata
);
ledtest_mm_interconnect_2 mm_interconnect_2 (
.CLOCK_clk_clk (clk_clk), // CLOCK_clk.clk
.ARM_MCU_f2h_sdram0_data_translator_reset_reset_bridge_in_reset_reset (rst_controller_001_reset_out_reset), // ARM_MCU_f2h_sdram0_data_translator_reset_reset_bridge_in_reset.reset
.JTAG_DEBUG_clk_reset_reset_bridge_in_reset_reset (rst_controller_reset_out_reset), // JTAG_DEBUG_clk_reset_reset_bridge_in_reset.reset
.JTAG_DEBUG_master_translator_reset_reset_bridge_in_reset_reset (rst_controller_reset_out_reset), // JTAG_DEBUG_master_translator_reset_reset_bridge_in_reset.reset
.JTAG_DEBUG_master_address (jtag_debug_master_address), // JTAG_DEBUG_master.address
.JTAG_DEBUG_master_waitrequest (jtag_debug_master_waitrequest), // .waitrequest
.JTAG_DEBUG_master_byteenable (jtag_debug_master_byteenable), // .byteenable
.JTAG_DEBUG_master_read (jtag_debug_master_read), // .read
.JTAG_DEBUG_master_readdata (jtag_debug_master_readdata), // .readdata
.JTAG_DEBUG_master_readdatavalid (jtag_debug_master_readdatavalid), // .readdatavalid
.JTAG_DEBUG_master_write (jtag_debug_master_write), // .write
.JTAG_DEBUG_master_writedata (jtag_debug_master_writedata), // .writedata
.ARM_MCU_f2h_sdram0_data_address (mm_interconnect_2_arm_mcu_f2h_sdram0_data_address), // ARM_MCU_f2h_sdram0_data.address
.ARM_MCU_f2h_sdram0_data_write (mm_interconnect_2_arm_mcu_f2h_sdram0_data_write), // .write
.ARM_MCU_f2h_sdram0_data_read (mm_interconnect_2_arm_mcu_f2h_sdram0_data_read), // .read
.ARM_MCU_f2h_sdram0_data_readdata (mm_interconnect_2_arm_mcu_f2h_sdram0_data_readdata), // .readdata
.ARM_MCU_f2h_sdram0_data_writedata (mm_interconnect_2_arm_mcu_f2h_sdram0_data_writedata), // .writedata
.ARM_MCU_f2h_sdram0_data_burstcount (mm_interconnect_2_arm_mcu_f2h_sdram0_data_burstcount), // .burstcount
.ARM_MCU_f2h_sdram0_data_byteenable (mm_interconnect_2_arm_mcu_f2h_sdram0_data_byteenable), // .byteenable
.ARM_MCU_f2h_sdram0_data_readdatavalid (mm_interconnect_2_arm_mcu_f2h_sdram0_data_readdatavalid), // .readdatavalid
.ARM_MCU_f2h_sdram0_data_waitrequest (mm_interconnect_2_arm_mcu_f2h_sdram0_data_waitrequest) // .waitrequest
);
altera_reset_controller #(
.NUM_RESET_INPUTS (1),
.OUTPUT_RESET_SYNC_EDGES ("deassert"),
.SYNC_DEPTH (2),
.RESET_REQUEST_PRESENT (0),
.RESET_REQ_WAIT_TIME (1),
.MIN_RST_ASSERTION_TIME (3),
.RESET_REQ_EARLY_DSRT_TIME (1),
.USE_RESET_REQUEST_IN0 (0),
.USE_RESET_REQUEST_IN1 (0),
.USE_RESET_REQUEST_IN2 (0),
.USE_RESET_REQUEST_IN3 (0),
.USE_RESET_REQUEST_IN4 (0),
.USE_RESET_REQUEST_IN5 (0),
.USE_RESET_REQUEST_IN6 (0),
.USE_RESET_REQUEST_IN7 (0),
.USE_RESET_REQUEST_IN8 (0),
.USE_RESET_REQUEST_IN9 (0),
.USE_RESET_REQUEST_IN10 (0),
.USE_RESET_REQUEST_IN11 (0),
.USE_RESET_REQUEST_IN12 (0),
.USE_RESET_REQUEST_IN13 (0),
.USE_RESET_REQUEST_IN14 (0),
.USE_RESET_REQUEST_IN15 (0),
.ADAPT_RESET_REQUEST (0)
) rst_controller (
.reset_in0 (~arm_mcu_h2f_reset_reset), // reset_in0.reset
.clk (clk_clk), // clk.clk
.reset_out (rst_controller_reset_out_reset), // reset_out.reset
.reset_req (), // (terminated)
.reset_req_in0 (1'b0), // (terminated)
.reset_in1 (1'b0), // (terminated)
.reset_req_in1 (1'b0), // (terminated)
.reset_in2 (1'b0), // (terminated)
.reset_req_in2 (1'b0), // (terminated)
.reset_in3 (1'b0), // (terminated)
.reset_req_in3 (1'b0), // (terminated)
.reset_in4 (1'b0), // (terminated)
.reset_req_in4 (1'b0), // (terminated)
.reset_in5 (1'b0), // (terminated)
.reset_req_in5 (1'b0), // (terminated)
.reset_in6 (1'b0), // (terminated)
.reset_req_in6 (1'b0), // (terminated)
.reset_in7 (1'b0), // (terminated)
.reset_req_in7 (1'b0), // (terminated)
.reset_in8 (1'b0), // (terminated)
.reset_req_in8 (1'b0), // (terminated)
.reset_in9 (1'b0), // (terminated)
.reset_req_in9 (1'b0), // (terminated)
.reset_in10 (1'b0), // (terminated)
.reset_req_in10 (1'b0), // (terminated)
.reset_in11 (1'b0), // (terminated)
.reset_req_in11 (1'b0), // (terminated)
.reset_in12 (1'b0), // (terminated)
.reset_req_in12 (1'b0), // (terminated)
.reset_in13 (1'b0), // (terminated)
.reset_req_in13 (1'b0), // (terminated)
.reset_in14 (1'b0), // (terminated)
.reset_req_in14 (1'b0), // (terminated)
.reset_in15 (1'b0), // (terminated)
.reset_req_in15 (1'b0) // (terminated)
);
altera_reset_controller #(
.NUM_RESET_INPUTS (1),
.OUTPUT_RESET_SYNC_EDGES ("deassert"),
.SYNC_DEPTH (2),
.RESET_REQUEST_PRESENT (0),
.RESET_REQ_WAIT_TIME (1),
.MIN_RST_ASSERTION_TIME (3),
.RESET_REQ_EARLY_DSRT_TIME (1),
.USE_RESET_REQUEST_IN0 (0),
.USE_RESET_REQUEST_IN1 (0),
.USE_RESET_REQUEST_IN2 (0),
.USE_RESET_REQUEST_IN3 (0),
.USE_RESET_REQUEST_IN4 (0),
.USE_RESET_REQUEST_IN5 (0),
.USE_RESET_REQUEST_IN6 (0),
.USE_RESET_REQUEST_IN7 (0),
.USE_RESET_REQUEST_IN8 (0),
.USE_RESET_REQUEST_IN9 (0),
.USE_RESET_REQUEST_IN10 (0),
.USE_RESET_REQUEST_IN11 (0),
.USE_RESET_REQUEST_IN12 (0),
.USE_RESET_REQUEST_IN13 (0),
.USE_RESET_REQUEST_IN14 (0),
.USE_RESET_REQUEST_IN15 (0),
.ADAPT_RESET_REQUEST (0)
) rst_controller_001 (
.reset_in0 (~arm_mcu_h2f_reset_reset), // reset_in0.reset
.clk (clk_clk), // clk.clk
.reset_out (rst_controller_001_reset_out_reset), // reset_out.reset
.reset_req (), // (terminated)
.reset_req_in0 (1'b0), // (terminated)
.reset_in1 (1'b0), // (terminated)
.reset_req_in1 (1'b0), // (terminated)
.reset_in2 (1'b0), // (terminated)
.reset_req_in2 (1'b0), // (terminated)
.reset_in3 (1'b0), // (terminated)
.reset_req_in3 (1'b0), // (terminated)
.reset_in4 (1'b0), // (terminated)
.reset_req_in4 (1'b0), // (terminated)
.reset_in5 (1'b0), // (terminated)
.reset_req_in5 (1'b0), // (terminated)
.reset_in6 (1'b0), // (terminated)
.reset_req_in6 (1'b0), // (terminated)
.reset_in7 (1'b0), // (terminated)
.reset_req_in7 (1'b0), // (terminated)
.reset_in8 (1'b0), // (terminated)
.reset_req_in8 (1'b0), // (terminated)
.reset_in9 (1'b0), // (terminated)
.reset_req_in9 (1'b0), // (terminated)
.reset_in10 (1'b0), // (terminated)
.reset_req_in10 (1'b0), // (terminated)
.reset_in11 (1'b0), // (terminated)
.reset_req_in11 (1'b0), // (terminated)
.reset_in12 (1'b0), // (terminated)
.reset_req_in12 (1'b0), // (terminated)
.reset_in13 (1'b0), // (terminated)
.reset_req_in13 (1'b0), // (terminated)
.reset_in14 (1'b0), // (terminated)
.reset_req_in14 (1'b0), // (terminated)
.reset_in15 (1'b0), // (terminated)
.reset_req_in15 (1'b0) // (terminated)
);
endmodule
|
module mcpu( input CLK,
input CLK_MEM,
input RESET,
input RUN,
//External inst memory iface
output [29:0] INST_ADDR,
input [31:0] INST_RD,
//External data memory iface
output DATA_WE,
output [3:0] DATA_BE,
output [29:0] DATA_ADDR,
output [31:0] DATA_WD,
input [31:0] DATA_RD );
wire WRITE_REG, WRITE_MEM, ALUORMEM_WR, MULTIPLY,
ALU_SRC_B, BRANCH_E, BRANCH_NE, JUMP, JUMP_R,
BRANCH_LEZ, BRANCH_LTZ, BRANCH_GEZ, BRANCH_GTZ,
MEM_PARTIAL;
wire [1:0] IMMED_EXT, REG_DST, MFCOP_SEL, MEM_OPTYPE;
wire [6:0] ALU_OP;
wire [5:0] OPCODE;
wire [5:0] FCODE;
wire [4:0] RT;
controller the_controller ( .OPCODE (OPCODE ), //instruction opcode
.FCODE (FCODE ), //instruction fcode
.RT (RT ), //instruction RT
.WRITE_REG (WRITE_REG ), //write to register file
.WRITE_MEM (WRITE_MEM ), //write data memory
.MEM_PARTIAL(MEM_PARTIAL), //memory byte- or halfword access
.MEM_OPTYPE (MEM_OPTYPE ), //mem op: 00-ubyte, 01-uhalf, 10-sb, 11-sh
.ALUORMEM_WR(ALUORMEM_WR), //write regfile from alu or from memory
.MULTIPLY (MULTIPLY ), //multiply and write hi and lo
.BRANCH_E (BRANCH_E ), //branch equal
.BRANCH_NE (BRANCH_NE ), //branch not equal
.BRANCH_LEZ (BRANCH_LEZ ), //branch less than or equal zero
.BRANCH_LTZ (BRANCH_LTZ ), //branch less than zero
.BRANCH_GEZ (BRANCH_GEZ ), //branch greater than or equal zero
.BRANCH_GTZ (BRANCH_GTZ ), //branch greater than zero
.JUMP (JUMP ), //j-type jump
.JUMP_R (JUMP_R ), //r-type jump
.ALU_SRC_B (ALU_SRC_B ), //ALU Operand B 0 - reg_2, 1 - immediate
.ALU_OP (ALU_OP ), //ALU Operation select
.REG_DST (REG_DST ), //write destination in regfile (0 - rt, 1 - rd)
.IMMED_EXT (IMMED_EXT ), //immed-extension type
.MFCOP_SEL (MFCOP_SEL )); //move from coprocessor sel
datapath the_datapath ( .CLK (CLK ),
.CLK_MEM (CLK_MEM ),
.RESET (RESET ),
.RUN (RUN ),
//Controller iface
.OPCODE (OPCODE ), //instruction opcode
.FCODE (FCODE ), //instruction fcode
.RT (RT ), //instruction RT
.WRITE_REG (WRITE_REG ), //write to register file
.WRITE_MEM (WRITE_MEM ), //write data memory
.MEM_PARTIAL (MEM_PARTIAL), //memory byte- or halfword access
.MEM_OPTYPE (MEM_OPTYPE ), //mem op: 00-ubyte, 01-uhalf, 10-sb, 11-sh
.ALUORMEM_WR (ALUORMEM_WR), //write regfile from alu or from memory
.MULTIPLY (MULTIPLY ), //multiply and write hi and lo
.BRANCH_E (BRANCH_E ), //branch equal
.BRANCH_NE (BRANCH_NE ), //branch not equal
.BRANCH_LEZ (BRANCH_LEZ ), //branch less than or equal zero
.BRANCH_LTZ (BRANCH_LTZ ), //branch less than zero
.BRANCH_GEZ (BRANCH_GEZ ), //branch greater than or equal zero
.BRANCH_GTZ (BRANCH_GTZ ), //branch greater than zero
.JUMP (JUMP ), //j-type jump
.JUMP_R (JUMP_R ), //r-type jump
.ALU_SRC_B (ALU_SRC_B ), //ALU Operand B 0 - reg_2, 1 - immediate
.ALU_OP (ALU_OP ), //ALU Operation select
.REG_DST (REG_DST ), //write destination in regfile (0 - rt, 1 - rd)
.IMMED_EXT (IMMED_EXT ), //immed ext (sign, zero, swap)
.MFCOP_SEL (MFCOP_SEL ), //move from coprocessor sel
//External inst memory iface
.inst_mem_addr (INST_ADDR),
.inst_mem_data (INST_RD ),
//External data memory iface
.data_mem_we (DATA_WE ),
.data_mem_be (DATA_BE ),
.data_mem_addr (DATA_ADDR),
.data_mem_wdata (DATA_WD ),
.data_mem_rdata (DATA_RD ) );
endmodule
|
module bsg_mesh_router_decoder_dor
import bsg_noc_pkg::*;
import bsg_mesh_router_pkg::*;
#(parameter `BSG_INV_PARAM(x_cord_width_p )
, parameter `BSG_INV_PARAM(y_cord_width_p )
, parameter dims_p = 2
, parameter dirs_lp = (2*dims_p)+1
, parameter ruche_factor_X_p=0
, parameter ruche_factor_Y_p=0
// XY_order_p = 1 : X then Y
// XY_order_p = 0 : Y then X
, parameter XY_order_p = 1
, parameter from_p = {dirs_lp{1'b0}} // one-hot, indicates which direction is the input coming from.
, parameter debug_p = 0
)
(
input clk_i // debug only
, input reset_i // debug only
//, input v_i
, input [x_cord_width_p-1:0] x_dirs_i
, input [y_cord_width_p-1:0] y_dirs_i
, input [x_cord_width_p-1:0] my_x_i
, input [y_cord_width_p-1:0] my_y_i
, output [dirs_lp-1:0] req_o
);
// check parameters
// synopsys translate_off
initial begin
if (ruche_factor_X_p > 0) begin
assert(dims_p > 2) else $fatal(1, "ruche in X direction requires dims_p greater than 2.");
end
if (ruche_factor_Y_p > 0) begin
assert(dims_p > 3) else $fatal(1, "ruche in Y direction requires dims_p greater than 3.");
end
assert($countones(from_p) == 1) else $fatal(1, "Must define from_p as one-hot value.");
assert(ruche_factor_X_p < (1<<x_cord_width_p)) else $fatal(1, "ruche factor in X direction is too large");
assert(ruche_factor_Y_p < (1<<y_cord_width_p)) else $fatal(1, "ruche factor in Y direction is too large");
end
// synopsys translate_on
// compare coordinates
wire x_eq = (x_dirs_i == my_x_i);
wire y_eq = (y_dirs_i == my_y_i);
wire x_gt = x_dirs_i > my_x_i;
wire y_gt = y_dirs_i > my_y_i;
wire x_lt = ~x_gt & ~x_eq;
wire y_lt = ~y_gt & ~y_eq;
// valid signal
logic [dirs_lp-1:0] req;
assign req_o = req;
// P-port
assign req[P] = x_eq & y_eq;
if (ruche_factor_X_p > 0) begin
if (XY_order_p) begin
// make sure there is no under/overflow.
wire [x_cord_width_p:0] re_cord = (x_cord_width_p+1)'(my_x_i + ruche_factor_X_p);
wire send_rw = (my_x_i > (x_cord_width_p)'(ruche_factor_X_p)) & (x_dirs_i < (my_x_i - (x_cord_width_p)'(ruche_factor_X_p)));
wire send_re = ~re_cord[x_cord_width_p] & (x_dirs_i > re_cord[0+:x_cord_width_p]);
assign req[W] = x_lt & ~send_rw;
assign req[RW] = send_rw;
assign req[E] = x_gt & ~send_re;
assign req[RE] = send_re;
end
else begin
if (from_p[S] | from_p[N] | from_p[P]) begin
assign req[W] = y_eq & x_lt;
assign req[RW] = 1'b0;
assign req[E] = y_eq & x_gt;
assign req[RE] = 1'b0;
end
else if(from_p[W]) begin
wire [x_cord_width_p-1:0] dx = (x_cord_width_p)'((x_dirs_i - my_x_i) % ruche_factor_X_p);
assign req[RE] = y_eq & x_gt & (dx == '0);
assign req[E] = y_eq & x_gt & (dx != '0);
assign req[RW] = 1'b0;
assign req[W] = 1'b0;
end
else if (from_p[E]) begin
wire [x_cord_width_p-1:0] dx = (x_cord_width_p)'((my_x_i - x_dirs_i) % ruche_factor_X_p);
assign req[RE] = 1'b0;
assign req[E] = 1'b0;
assign req[RW] = y_eq & x_lt & (dx == '0);
assign req[W] = y_eq & x_lt & (dx != '0);
end
else if (from_p[RW]) begin
assign req[RE] = y_eq & x_gt;
assign req[E] = 1'b0;
assign req[RW] = 1'b0;
assign req[W] = 1'b0;
end
else if (from_p[RE]) begin
assign req[RE] = 1'b0;
assign req[E] = 1'b0;
assign req[RW] = y_eq & x_lt;
assign req[W] = 1'b0;
end
end
end
else begin
if (XY_order_p) begin
assign req[W] = x_lt;
assign req[E] = x_gt;
end
else begin
assign req[W] = y_eq & x_lt;
assign req[E] = y_eq & x_gt;
end
end
if (ruche_factor_Y_p > 0) begin
if (XY_order_p == 0) begin
// make sure there is no under/overflow.
wire [y_cord_width_p:0] rs_cord = (y_cord_width_p+1)'(my_y_i + ruche_factor_Y_p);
wire send_rn = (my_y_i > (y_cord_width_p)'(ruche_factor_Y_p)) & (y_dirs_i < (my_y_i - (y_cord_width_p)'(ruche_factor_Y_p)));
wire send_rs = ~rs_cord[y_cord_width_p] & (y_dirs_i > rs_cord[0+:y_cord_width_p]);
assign req[N] = y_lt & ~send_rn;
assign req[RN] = send_rn;
assign req[S] = y_gt & ~send_rs;
assign req[RS] = send_rs;
end
else begin
if (from_p[E] | from_p[W] | from_p[P]) begin
assign req[N] = x_eq & y_lt;
assign req[RN] = 1'b0;
assign req[S] = x_eq & y_gt;
assign req[RS] = 1'b0;
end
else if (from_p[N]) begin
wire [y_cord_width_p-1:0] dy = (y_cord_width_p)'((y_dirs_i - my_y_i) % ruche_factor_Y_p);
assign req[RS] = x_eq & y_gt & (dy == '0);
assign req[S] = x_eq & y_gt & (dy != '0);
assign req[RN] = 1'b0;
assign req[N] = 1'b0;
end
else if (from_p[S]) begin
wire [y_cord_width_p-1:0] dy = (y_cord_width_p)'((my_y_i - y_dirs_i) % ruche_factor_Y_p);
assign req[RS] = 1'b0;
assign req[S] = 1'b0;
assign req[RN] = x_eq & y_lt & (dy == '0);
assign req[N] = x_eq & y_lt & (dy != '0);
end
else if (from_p[RN]) begin
assign req[RS] = x_eq & y_gt;
assign req[S] = 1'b0;
assign req[RN] = 1'b0;
assign req[N] = 1'b0;
end
else if (from_p[RS]) begin
assign req[RS] = 1'b0;
assign req[S] = 1'b0;
assign req[RN] = x_eq & y_lt;
assign req[N] = 1'b0;
end
end
end
else begin
if (XY_order_p == 0) begin
assign req[N] = y_lt;
assign req[S] = y_gt;
end
else begin
assign req[N] = x_eq & y_lt;
assign req[S] = x_eq & y_gt;
end
end
// synopsys translate_off
if (debug_p) begin
always_ff @ (negedge clk_i) begin
if (~reset_i) begin
assert($countones(req_o) < 2)
else $fatal(1, "multiple req_o detected. %b", req_o);
end
end
end
else begin
wire unused0 = clk_i;
wire unused1 = reset_i;
end
// synopsys translate_on
endmodule
|
module sky130_fd_sc_lp__busdrivernovlpsleep (
//# {{data|Data Signals}}
input A ,
output Z ,
//# {{control|Control Signals}}
input TE_B ,
//# {{power|Power}}
input SLEEP
);
// Voltage supply signals
supply1 VPWR ;
supply0 VGND ;
supply1 KAPWR;
supply1 VPB ;
supply0 VNB ;
endmodule
|
module sky130_fd_sc_hd__einvp_8 (
Z ,
A ,
TE ,
VPWR,
VGND,
VPB ,
VNB
);
output Z ;
input A ;
input TE ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__einvp base (
.Z(Z),
.A(A),
.TE(TE),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
|
module sky130_fd_sc_hd__einvp_8 (
Z ,
A ,
TE
);
output Z ;
input A ;
input TE;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__einvp base (
.Z(Z),
.A(A),
.TE(TE)
);
endmodule
|
module sky130_fd_sc_lp__or3b_lp (
X ,
A ,
B ,
C_N ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input C_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__or3b base (
.X(X),
.A(A),
.B(B),
.C_N(C_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
|
module sky130_fd_sc_lp__or3b_lp (
X ,
A ,
B ,
C_N
);
output X ;
input A ;
input B ;
input C_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__or3b base (
.X(X),
.A(A),
.B(B),
.C_N(C_N)
);
endmodule
|
module cpx_dp_maca_r(/*AUTOARG*/
// Outputs
data_out_cx_l, scan_out, shiftenable_buf,
// Inputs
arb_cpxdp_qsel1_ca, arb_cpxdp_qsel0_ca, arb_cpxdp_grant_ca,
arb_cpxdp_shift_cx, arb_cpxdp_q0_hold_ca, src_cpx_data_ca, rclk,
scan_in, shiftenable
);
output [149:0] data_out_cx_l; // cpx to destination pkt
output scan_out;
output shiftenable_buf;
input arb_cpxdp_qsel1_ca; // queue write sel
input arb_cpxdp_qsel0_ca; // queue write sel
input arb_cpxdp_grant_ca;//grant signal
input arb_cpxdp_shift_cx;//grant signal
input arb_cpxdp_q0_hold_ca;//grant signal
input [149:0] src_cpx_data_ca; // scache to cpx data
input rclk;
//input tmb_l;
input scan_in;
input shiftenable;
wire grant_cx;
wire [149:0] q0_datain_ca;
wire [149:0] q1_dataout, q0_dataout;
wire clkq0, clkq1;
reg clkenq0, clkenq1;
//HEADER SECTION
// Generate gated clocks for hold function
assign shiftenable_buf = shiftenable;
/*
always @ (clk or arb_cpxdp_qsel1_ca )
begin
if (!clk) //latch opens on rclk low phase
clkenq1 = arb_cpxdp_qsel1_ca ;
end // always @ (clk or arb_cpxdp_qsel1_ca or tmb)
assign clkq1 = clkenq1 & clk;
always @ (clk or arb_cpxdp_q0_hold_ca )
begin
if (!clk) //latch opens on rclk low phase
clkenq0 = !arb_cpxdp_q0_hold_ca ;
end // always @ (clk or arb_cpxdp_q0_hold_ca or tmb)
assign clkq0 = clkenq0 & clk;
*/
//replace tmb_l w/ ~se
wire se_l ;
assign se_l = ~shiftenable ;
clken_buf ck0 (
.clk (clkq0),
.rclk (rclk),
.enb_l(~arb_cpxdp_q0_hold_ca),
.tmb_l(se_l));
clken_buf ck1 (
.clk (clkq1),
.rclk (rclk),
.enb_l(~arb_cpxdp_qsel1_ca),
.tmb_l(se_l));
dff_s #(1) dff_cpx_grin_r(
.din (arb_cpxdp_grant_ca),
.q (grant_cx),
.clk (rclk),
.se (1'b0),
.si (1'b0),
.so ());
//DATAPATH SECTION
dff_s #(150) dff_cpx_datain_q1(
.din (src_cpx_data_ca[149:0]),
.q (q1_dataout[149:0]),
.clk (clkq1),
.se (1'b0),
.si (),
.so ());
assign q0_datain_ca[149:0] =
(arb_cpxdp_qsel0_ca ? src_cpx_data_ca[149:0] : 150'd0) |
(arb_cpxdp_shift_cx ? q1_dataout[149:0] : 150'd0) ;
dff_s #(150) dff_cpx_datain_q0(
.din (q0_datain_ca[149:0]),
.q (q0_dataout[149:0]),
.clk (clkq0),
.se (1'b0),
.si (),
.so ());
assign data_out_cx_l[149:0] = ~(grant_cx ? q0_dataout[149:0] : 150'd0);
// Local Variables:
// verilog-library-directories:("." "../../../../../common/rtl")
// End:
// Code start here
//
endmodule
|
module sky130_fd_sc_ms__or3 (
X,
A,
B,
C
);
// Module ports
output X;
input A;
input B;
input C;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire or0_out_X;
// Name Output Other arguments
or or0 (or0_out_X, B, A, C );
buf buf0 (X , or0_out_X );
endmodule
|
module hps_design (
input wire clk_clk, // clk.clk
output wire [14:0] hps_ddr3_mem_a, // hps_ddr3.mem_a
output wire [2:0] hps_ddr3_mem_ba, // .mem_ba
output wire hps_ddr3_mem_ck, // .mem_ck
output wire hps_ddr3_mem_ck_n, // .mem_ck_n
output wire hps_ddr3_mem_cke, // .mem_cke
output wire hps_ddr3_mem_cs_n, // .mem_cs_n
output wire hps_ddr3_mem_ras_n, // .mem_ras_n
output wire hps_ddr3_mem_cas_n, // .mem_cas_n
output wire hps_ddr3_mem_we_n, // .mem_we_n
output wire hps_ddr3_mem_reset_n, // .mem_reset_n
inout wire [31:0] hps_ddr3_mem_dq, // .mem_dq
inout wire [3:0] hps_ddr3_mem_dqs, // .mem_dqs
inout wire [3:0] hps_ddr3_mem_dqs_n, // .mem_dqs_n
output wire hps_ddr3_mem_odt, // .mem_odt
output wire [3:0] hps_ddr3_mem_dm, // .mem_dm
input wire hps_ddr3_oct_rzqin, // .oct_rzqin
output wire ledr_export // ledr.export
);
wire pll_0_outclk0_clk; // pll_0:outclk_0 -> [SMP_HPS:h2f_lw_axi_clk, mm_interconnect_0:pll_0_outclk0_clk, pio_0:clk, rst_controller:clk, rst_controller_001:clk]
wire smp_hps_h2f_reset_reset; // SMP_HPS:h2f_rst_n -> [pll_0:rst, rst_controller:reset_in0, rst_controller_001:reset_in0]
wire [1:0] smp_hps_h2f_lw_axi_master_awburst; // SMP_HPS:h2f_lw_AWBURST -> mm_interconnect_0:SMP_HPS_h2f_lw_axi_master_awburst
wire [3:0] smp_hps_h2f_lw_axi_master_arlen; // SMP_HPS:h2f_lw_ARLEN -> mm_interconnect_0:SMP_HPS_h2f_lw_axi_master_arlen
wire [3:0] smp_hps_h2f_lw_axi_master_wstrb; // SMP_HPS:h2f_lw_WSTRB -> mm_interconnect_0:SMP_HPS_h2f_lw_axi_master_wstrb
wire smp_hps_h2f_lw_axi_master_wready; // mm_interconnect_0:SMP_HPS_h2f_lw_axi_master_wready -> SMP_HPS:h2f_lw_WREADY
wire [11:0] smp_hps_h2f_lw_axi_master_rid; // mm_interconnect_0:SMP_HPS_h2f_lw_axi_master_rid -> SMP_HPS:h2f_lw_RID
wire smp_hps_h2f_lw_axi_master_rready; // SMP_HPS:h2f_lw_RREADY -> mm_interconnect_0:SMP_HPS_h2f_lw_axi_master_rready
wire [3:0] smp_hps_h2f_lw_axi_master_awlen; // SMP_HPS:h2f_lw_AWLEN -> mm_interconnect_0:SMP_HPS_h2f_lw_axi_master_awlen
wire [11:0] smp_hps_h2f_lw_axi_master_wid; // SMP_HPS:h2f_lw_WID -> mm_interconnect_0:SMP_HPS_h2f_lw_axi_master_wid
wire [3:0] smp_hps_h2f_lw_axi_master_arcache; // SMP_HPS:h2f_lw_ARCACHE -> mm_interconnect_0:SMP_HPS_h2f_lw_axi_master_arcache
wire smp_hps_h2f_lw_axi_master_wvalid; // SMP_HPS:h2f_lw_WVALID -> mm_interconnect_0:SMP_HPS_h2f_lw_axi_master_wvalid
wire [20:0] smp_hps_h2f_lw_axi_master_araddr; // SMP_HPS:h2f_lw_ARADDR -> mm_interconnect_0:SMP_HPS_h2f_lw_axi_master_araddr
wire [2:0] smp_hps_h2f_lw_axi_master_arprot; // SMP_HPS:h2f_lw_ARPROT -> mm_interconnect_0:SMP_HPS_h2f_lw_axi_master_arprot
wire [2:0] smp_hps_h2f_lw_axi_master_awprot; // SMP_HPS:h2f_lw_AWPROT -> mm_interconnect_0:SMP_HPS_h2f_lw_axi_master_awprot
wire [31:0] smp_hps_h2f_lw_axi_master_wdata; // SMP_HPS:h2f_lw_WDATA -> mm_interconnect_0:SMP_HPS_h2f_lw_axi_master_wdata
wire smp_hps_h2f_lw_axi_master_arvalid; // SMP_HPS:h2f_lw_ARVALID -> mm_interconnect_0:SMP_HPS_h2f_lw_axi_master_arvalid
wire [3:0] smp_hps_h2f_lw_axi_master_awcache; // SMP_HPS:h2f_lw_AWCACHE -> mm_interconnect_0:SMP_HPS_h2f_lw_axi_master_awcache
wire [11:0] smp_hps_h2f_lw_axi_master_arid; // SMP_HPS:h2f_lw_ARID -> mm_interconnect_0:SMP_HPS_h2f_lw_axi_master_arid
wire [1:0] smp_hps_h2f_lw_axi_master_arlock; // SMP_HPS:h2f_lw_ARLOCK -> mm_interconnect_0:SMP_HPS_h2f_lw_axi_master_arlock
wire [1:0] smp_hps_h2f_lw_axi_master_awlock; // SMP_HPS:h2f_lw_AWLOCK -> mm_interconnect_0:SMP_HPS_h2f_lw_axi_master_awlock
wire [20:0] smp_hps_h2f_lw_axi_master_awaddr; // SMP_HPS:h2f_lw_AWADDR -> mm_interconnect_0:SMP_HPS_h2f_lw_axi_master_awaddr
wire [1:0] smp_hps_h2f_lw_axi_master_bresp; // mm_interconnect_0:SMP_HPS_h2f_lw_axi_master_bresp -> SMP_HPS:h2f_lw_BRESP
wire smp_hps_h2f_lw_axi_master_arready; // mm_interconnect_0:SMP_HPS_h2f_lw_axi_master_arready -> SMP_HPS:h2f_lw_ARREADY
wire [31:0] smp_hps_h2f_lw_axi_master_rdata; // mm_interconnect_0:SMP_HPS_h2f_lw_axi_master_rdata -> SMP_HPS:h2f_lw_RDATA
wire smp_hps_h2f_lw_axi_master_awready; // mm_interconnect_0:SMP_HPS_h2f_lw_axi_master_awready -> SMP_HPS:h2f_lw_AWREADY
wire [1:0] smp_hps_h2f_lw_axi_master_arburst; // SMP_HPS:h2f_lw_ARBURST -> mm_interconnect_0:SMP_HPS_h2f_lw_axi_master_arburst
wire [2:0] smp_hps_h2f_lw_axi_master_arsize; // SMP_HPS:h2f_lw_ARSIZE -> mm_interconnect_0:SMP_HPS_h2f_lw_axi_master_arsize
wire smp_hps_h2f_lw_axi_master_bready; // SMP_HPS:h2f_lw_BREADY -> mm_interconnect_0:SMP_HPS_h2f_lw_axi_master_bready
wire smp_hps_h2f_lw_axi_master_rlast; // mm_interconnect_0:SMP_HPS_h2f_lw_axi_master_rlast -> SMP_HPS:h2f_lw_RLAST
wire smp_hps_h2f_lw_axi_master_wlast; // SMP_HPS:h2f_lw_WLAST -> mm_interconnect_0:SMP_HPS_h2f_lw_axi_master_wlast
wire [1:0] smp_hps_h2f_lw_axi_master_rresp; // mm_interconnect_0:SMP_HPS_h2f_lw_axi_master_rresp -> SMP_HPS:h2f_lw_RRESP
wire [11:0] smp_hps_h2f_lw_axi_master_awid; // SMP_HPS:h2f_lw_AWID -> mm_interconnect_0:SMP_HPS_h2f_lw_axi_master_awid
wire [11:0] smp_hps_h2f_lw_axi_master_bid; // mm_interconnect_0:SMP_HPS_h2f_lw_axi_master_bid -> SMP_HPS:h2f_lw_BID
wire smp_hps_h2f_lw_axi_master_bvalid; // mm_interconnect_0:SMP_HPS_h2f_lw_axi_master_bvalid -> SMP_HPS:h2f_lw_BVALID
wire [2:0] smp_hps_h2f_lw_axi_master_awsize; // SMP_HPS:h2f_lw_AWSIZE -> mm_interconnect_0:SMP_HPS_h2f_lw_axi_master_awsize
wire smp_hps_h2f_lw_axi_master_awvalid; // SMP_HPS:h2f_lw_AWVALID -> mm_interconnect_0:SMP_HPS_h2f_lw_axi_master_awvalid
wire smp_hps_h2f_lw_axi_master_rvalid; // mm_interconnect_0:SMP_HPS_h2f_lw_axi_master_rvalid -> SMP_HPS:h2f_lw_RVALID
wire mm_interconnect_0_pio_0_s1_chipselect; // mm_interconnect_0:pio_0_s1_chipselect -> pio_0:chipselect
wire [31:0] mm_interconnect_0_pio_0_s1_readdata; // pio_0:readdata -> mm_interconnect_0:pio_0_s1_readdata
wire [1:0] mm_interconnect_0_pio_0_s1_address; // mm_interconnect_0:pio_0_s1_address -> pio_0:address
wire mm_interconnect_0_pio_0_s1_write; // mm_interconnect_0:pio_0_s1_write -> pio_0:write_n
wire [31:0] mm_interconnect_0_pio_0_s1_writedata; // mm_interconnect_0:pio_0_s1_writedata -> pio_0:writedata
wire rst_controller_reset_out_reset; // rst_controller:reset_out -> [mm_interconnect_0:pio_0_reset_reset_bridge_in_reset_reset, pio_0:reset_n]
wire rst_controller_001_reset_out_reset; // rst_controller_001:reset_out -> mm_interconnect_0:SMP_HPS_h2f_lw_axi_master_agent_clk_reset_reset_bridge_in_reset_reset
hps_design_SMP_HPS #(
.F2S_Width (0),
.S2F_Width (0)
) smp_hps (
.mem_a (hps_ddr3_mem_a), // memory.mem_a
.mem_ba (hps_ddr3_mem_ba), // .mem_ba
.mem_ck (hps_ddr3_mem_ck), // .mem_ck
.mem_ck_n (hps_ddr3_mem_ck_n), // .mem_ck_n
.mem_cke (hps_ddr3_mem_cke), // .mem_cke
.mem_cs_n (hps_ddr3_mem_cs_n), // .mem_cs_n
.mem_ras_n (hps_ddr3_mem_ras_n), // .mem_ras_n
.mem_cas_n (hps_ddr3_mem_cas_n), // .mem_cas_n
.mem_we_n (hps_ddr3_mem_we_n), // .mem_we_n
.mem_reset_n (hps_ddr3_mem_reset_n), // .mem_reset_n
.mem_dq (hps_ddr3_mem_dq), // .mem_dq
.mem_dqs (hps_ddr3_mem_dqs), // .mem_dqs
.mem_dqs_n (hps_ddr3_mem_dqs_n), // .mem_dqs_n
.mem_odt (hps_ddr3_mem_odt), // .mem_odt
.mem_dm (hps_ddr3_mem_dm), // .mem_dm
.oct_rzqin (hps_ddr3_oct_rzqin), // .oct_rzqin
.h2f_rst_n (smp_hps_h2f_reset_reset), // h2f_reset.reset_n
.h2f_lw_axi_clk (pll_0_outclk0_clk), // h2f_lw_axi_clock.clk
.h2f_lw_AWID (smp_hps_h2f_lw_axi_master_awid), // h2f_lw_axi_master.awid
.h2f_lw_AWADDR (smp_hps_h2f_lw_axi_master_awaddr), // .awaddr
.h2f_lw_AWLEN (smp_hps_h2f_lw_axi_master_awlen), // .awlen
.h2f_lw_AWSIZE (smp_hps_h2f_lw_axi_master_awsize), // .awsize
.h2f_lw_AWBURST (smp_hps_h2f_lw_axi_master_awburst), // .awburst
.h2f_lw_AWLOCK (smp_hps_h2f_lw_axi_master_awlock), // .awlock
.h2f_lw_AWCACHE (smp_hps_h2f_lw_axi_master_awcache), // .awcache
.h2f_lw_AWPROT (smp_hps_h2f_lw_axi_master_awprot), // .awprot
.h2f_lw_AWVALID (smp_hps_h2f_lw_axi_master_awvalid), // .awvalid
.h2f_lw_AWREADY (smp_hps_h2f_lw_axi_master_awready), // .awready
.h2f_lw_WID (smp_hps_h2f_lw_axi_master_wid), // .wid
.h2f_lw_WDATA (smp_hps_h2f_lw_axi_master_wdata), // .wdata
.h2f_lw_WSTRB (smp_hps_h2f_lw_axi_master_wstrb), // .wstrb
.h2f_lw_WLAST (smp_hps_h2f_lw_axi_master_wlast), // .wlast
.h2f_lw_WVALID (smp_hps_h2f_lw_axi_master_wvalid), // .wvalid
.h2f_lw_WREADY (smp_hps_h2f_lw_axi_master_wready), // .wready
.h2f_lw_BID (smp_hps_h2f_lw_axi_master_bid), // .bid
.h2f_lw_BRESP (smp_hps_h2f_lw_axi_master_bresp), // .bresp
.h2f_lw_BVALID (smp_hps_h2f_lw_axi_master_bvalid), // .bvalid
.h2f_lw_BREADY (smp_hps_h2f_lw_axi_master_bready), // .bready
.h2f_lw_ARID (smp_hps_h2f_lw_axi_master_arid), // .arid
.h2f_lw_ARADDR (smp_hps_h2f_lw_axi_master_araddr), // .araddr
.h2f_lw_ARLEN (smp_hps_h2f_lw_axi_master_arlen), // .arlen
.h2f_lw_ARSIZE (smp_hps_h2f_lw_axi_master_arsize), // .arsize
.h2f_lw_ARBURST (smp_hps_h2f_lw_axi_master_arburst), // .arburst
.h2f_lw_ARLOCK (smp_hps_h2f_lw_axi_master_arlock), // .arlock
.h2f_lw_ARCACHE (smp_hps_h2f_lw_axi_master_arcache), // .arcache
.h2f_lw_ARPROT (smp_hps_h2f_lw_axi_master_arprot), // .arprot
.h2f_lw_ARVALID (smp_hps_h2f_lw_axi_master_arvalid), // .arvalid
.h2f_lw_ARREADY (smp_hps_h2f_lw_axi_master_arready), // .arready
.h2f_lw_RID (smp_hps_h2f_lw_axi_master_rid), // .rid
.h2f_lw_RDATA (smp_hps_h2f_lw_axi_master_rdata), // .rdata
.h2f_lw_RRESP (smp_hps_h2f_lw_axi_master_rresp), // .rresp
.h2f_lw_RLAST (smp_hps_h2f_lw_axi_master_rlast), // .rlast
.h2f_lw_RVALID (smp_hps_h2f_lw_axi_master_rvalid), // .rvalid
.h2f_lw_RREADY (smp_hps_h2f_lw_axi_master_rready) // .rready
);
hps_design_pio_0 pio_0 (
.clk (pll_0_outclk0_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.address (mm_interconnect_0_pio_0_s1_address), // s1.address
.write_n (~mm_interconnect_0_pio_0_s1_write), // .write_n
.writedata (mm_interconnect_0_pio_0_s1_writedata), // .writedata
.chipselect (mm_interconnect_0_pio_0_s1_chipselect), // .chipselect
.readdata (mm_interconnect_0_pio_0_s1_readdata), // .readdata
.out_port (ledr_export) // external_connection.export
);
hps_design_pll_0 pll_0 (
.refclk (clk_clk), // refclk.clk
.rst (~smp_hps_h2f_reset_reset), // reset.reset
.outclk_0 (pll_0_outclk0_clk), // outclk0.clk
.locked () // (terminated)
);
hps_design_mm_interconnect_0 mm_interconnect_0 (
.SMP_HPS_h2f_lw_axi_master_awid (smp_hps_h2f_lw_axi_master_awid), // SMP_HPS_h2f_lw_axi_master.awid
.SMP_HPS_h2f_lw_axi_master_awaddr (smp_hps_h2f_lw_axi_master_awaddr), // .awaddr
.SMP_HPS_h2f_lw_axi_master_awlen (smp_hps_h2f_lw_axi_master_awlen), // .awlen
.SMP_HPS_h2f_lw_axi_master_awsize (smp_hps_h2f_lw_axi_master_awsize), // .awsize
.SMP_HPS_h2f_lw_axi_master_awburst (smp_hps_h2f_lw_axi_master_awburst), // .awburst
.SMP_HPS_h2f_lw_axi_master_awlock (smp_hps_h2f_lw_axi_master_awlock), // .awlock
.SMP_HPS_h2f_lw_axi_master_awcache (smp_hps_h2f_lw_axi_master_awcache), // .awcache
.SMP_HPS_h2f_lw_axi_master_awprot (smp_hps_h2f_lw_axi_master_awprot), // .awprot
.SMP_HPS_h2f_lw_axi_master_awvalid (smp_hps_h2f_lw_axi_master_awvalid), // .awvalid
.SMP_HPS_h2f_lw_axi_master_awready (smp_hps_h2f_lw_axi_master_awready), // .awready
.SMP_HPS_h2f_lw_axi_master_wid (smp_hps_h2f_lw_axi_master_wid), // .wid
.SMP_HPS_h2f_lw_axi_master_wdata (smp_hps_h2f_lw_axi_master_wdata), // .wdata
.SMP_HPS_h2f_lw_axi_master_wstrb (smp_hps_h2f_lw_axi_master_wstrb), // .wstrb
.SMP_HPS_h2f_lw_axi_master_wlast (smp_hps_h2f_lw_axi_master_wlast), // .wlast
.SMP_HPS_h2f_lw_axi_master_wvalid (smp_hps_h2f_lw_axi_master_wvalid), // .wvalid
.SMP_HPS_h2f_lw_axi_master_wready (smp_hps_h2f_lw_axi_master_wready), // .wready
.SMP_HPS_h2f_lw_axi_master_bid (smp_hps_h2f_lw_axi_master_bid), // .bid
.SMP_HPS_h2f_lw_axi_master_bresp (smp_hps_h2f_lw_axi_master_bresp), // .bresp
.SMP_HPS_h2f_lw_axi_master_bvalid (smp_hps_h2f_lw_axi_master_bvalid), // .bvalid
.SMP_HPS_h2f_lw_axi_master_bready (smp_hps_h2f_lw_axi_master_bready), // .bready
.SMP_HPS_h2f_lw_axi_master_arid (smp_hps_h2f_lw_axi_master_arid), // .arid
.SMP_HPS_h2f_lw_axi_master_araddr (smp_hps_h2f_lw_axi_master_araddr), // .araddr
.SMP_HPS_h2f_lw_axi_master_arlen (smp_hps_h2f_lw_axi_master_arlen), // .arlen
.SMP_HPS_h2f_lw_axi_master_arsize (smp_hps_h2f_lw_axi_master_arsize), // .arsize
.SMP_HPS_h2f_lw_axi_master_arburst (smp_hps_h2f_lw_axi_master_arburst), // .arburst
.SMP_HPS_h2f_lw_axi_master_arlock (smp_hps_h2f_lw_axi_master_arlock), // .arlock
.SMP_HPS_h2f_lw_axi_master_arcache (smp_hps_h2f_lw_axi_master_arcache), // .arcache
.SMP_HPS_h2f_lw_axi_master_arprot (smp_hps_h2f_lw_axi_master_arprot), // .arprot
.SMP_HPS_h2f_lw_axi_master_arvalid (smp_hps_h2f_lw_axi_master_arvalid), // .arvalid
.SMP_HPS_h2f_lw_axi_master_arready (smp_hps_h2f_lw_axi_master_arready), // .arready
.SMP_HPS_h2f_lw_axi_master_rid (smp_hps_h2f_lw_axi_master_rid), // .rid
.SMP_HPS_h2f_lw_axi_master_rdata (smp_hps_h2f_lw_axi_master_rdata), // .rdata
.SMP_HPS_h2f_lw_axi_master_rresp (smp_hps_h2f_lw_axi_master_rresp), // .rresp
.SMP_HPS_h2f_lw_axi_master_rlast (smp_hps_h2f_lw_axi_master_rlast), // .rlast
.SMP_HPS_h2f_lw_axi_master_rvalid (smp_hps_h2f_lw_axi_master_rvalid), // .rvalid
.SMP_HPS_h2f_lw_axi_master_rready (smp_hps_h2f_lw_axi_master_rready), // .rready
.pll_0_outclk0_clk (pll_0_outclk0_clk), // pll_0_outclk0.clk
.pio_0_reset_reset_bridge_in_reset_reset (rst_controller_reset_out_reset), // pio_0_reset_reset_bridge_in_reset.reset
.SMP_HPS_h2f_lw_axi_master_agent_clk_reset_reset_bridge_in_reset_reset (rst_controller_001_reset_out_reset), // SMP_HPS_h2f_lw_axi_master_agent_clk_reset_reset_bridge_in_reset.reset
.pio_0_s1_address (mm_interconnect_0_pio_0_s1_address), // pio_0_s1.address
.pio_0_s1_write (mm_interconnect_0_pio_0_s1_write), // .write
.pio_0_s1_readdata (mm_interconnect_0_pio_0_s1_readdata), // .readdata
.pio_0_s1_writedata (mm_interconnect_0_pio_0_s1_writedata), // .writedata
.pio_0_s1_chipselect (mm_interconnect_0_pio_0_s1_chipselect) // .chipselect
);
altera_reset_controller #(
.NUM_RESET_INPUTS (1),
.OUTPUT_RESET_SYNC_EDGES ("deassert"),
.SYNC_DEPTH (2),
.RESET_REQUEST_PRESENT (0),
.RESET_REQ_WAIT_TIME (1),
.MIN_RST_ASSERTION_TIME (3),
.RESET_REQ_EARLY_DSRT_TIME (1),
.USE_RESET_REQUEST_IN0 (0),
.USE_RESET_REQUEST_IN1 (0),
.USE_RESET_REQUEST_IN2 (0),
.USE_RESET_REQUEST_IN3 (0),
.USE_RESET_REQUEST_IN4 (0),
.USE_RESET_REQUEST_IN5 (0),
.USE_RESET_REQUEST_IN6 (0),
.USE_RESET_REQUEST_IN7 (0),
.USE_RESET_REQUEST_IN8 (0),
.USE_RESET_REQUEST_IN9 (0),
.USE_RESET_REQUEST_IN10 (0),
.USE_RESET_REQUEST_IN11 (0),
.USE_RESET_REQUEST_IN12 (0),
.USE_RESET_REQUEST_IN13 (0),
.USE_RESET_REQUEST_IN14 (0),
.USE_RESET_REQUEST_IN15 (0),
.ADAPT_RESET_REQUEST (0)
) rst_controller (
.reset_in0 (~smp_hps_h2f_reset_reset), // reset_in0.reset
.clk (pll_0_outclk0_clk), // clk.clk
.reset_out (rst_controller_reset_out_reset), // reset_out.reset
.reset_req (), // (terminated)
.reset_req_in0 (1'b0), // (terminated)
.reset_in1 (1'b0), // (terminated)
.reset_req_in1 (1'b0), // (terminated)
.reset_in2 (1'b0), // (terminated)
.reset_req_in2 (1'b0), // (terminated)
.reset_in3 (1'b0), // (terminated)
.reset_req_in3 (1'b0), // (terminated)
.reset_in4 (1'b0), // (terminated)
.reset_req_in4 (1'b0), // (terminated)
.reset_in5 (1'b0), // (terminated)
.reset_req_in5 (1'b0), // (terminated)
.reset_in6 (1'b0), // (terminated)
.reset_req_in6 (1'b0), // (terminated)
.reset_in7 (1'b0), // (terminated)
.reset_req_in7 (1'b0), // (terminated)
.reset_in8 (1'b0), // (terminated)
.reset_req_in8 (1'b0), // (terminated)
.reset_in9 (1'b0), // (terminated)
.reset_req_in9 (1'b0), // (terminated)
.reset_in10 (1'b0), // (terminated)
.reset_req_in10 (1'b0), // (terminated)
.reset_in11 (1'b0), // (terminated)
.reset_req_in11 (1'b0), // (terminated)
.reset_in12 (1'b0), // (terminated)
.reset_req_in12 (1'b0), // (terminated)
.reset_in13 (1'b0), // (terminated)
.reset_req_in13 (1'b0), // (terminated)
.reset_in14 (1'b0), // (terminated)
.reset_req_in14 (1'b0), // (terminated)
.reset_in15 (1'b0), // (terminated)
.reset_req_in15 (1'b0) // (terminated)
);
altera_reset_controller #(
.NUM_RESET_INPUTS (1),
.OUTPUT_RESET_SYNC_EDGES ("deassert"),
.SYNC_DEPTH (2),
.RESET_REQUEST_PRESENT (0),
.RESET_REQ_WAIT_TIME (1),
.MIN_RST_ASSERTION_TIME (3),
.RESET_REQ_EARLY_DSRT_TIME (1),
.USE_RESET_REQUEST_IN0 (0),
.USE_RESET_REQUEST_IN1 (0),
.USE_RESET_REQUEST_IN2 (0),
.USE_RESET_REQUEST_IN3 (0),
.USE_RESET_REQUEST_IN4 (0),
.USE_RESET_REQUEST_IN5 (0),
.USE_RESET_REQUEST_IN6 (0),
.USE_RESET_REQUEST_IN7 (0),
.USE_RESET_REQUEST_IN8 (0),
.USE_RESET_REQUEST_IN9 (0),
.USE_RESET_REQUEST_IN10 (0),
.USE_RESET_REQUEST_IN11 (0),
.USE_RESET_REQUEST_IN12 (0),
.USE_RESET_REQUEST_IN13 (0),
.USE_RESET_REQUEST_IN14 (0),
.USE_RESET_REQUEST_IN15 (0),
.ADAPT_RESET_REQUEST (0)
) rst_controller_001 (
.reset_in0 (~smp_hps_h2f_reset_reset), // reset_in0.reset
.clk (pll_0_outclk0_clk), // clk.clk
.reset_out (rst_controller_001_reset_out_reset), // reset_out.reset
.reset_req (), // (terminated)
.reset_req_in0 (1'b0), // (terminated)
.reset_in1 (1'b0), // (terminated)
.reset_req_in1 (1'b0), // (terminated)
.reset_in2 (1'b0), // (terminated)
.reset_req_in2 (1'b0), // (terminated)
.reset_in3 (1'b0), // (terminated)
.reset_req_in3 (1'b0), // (terminated)
.reset_in4 (1'b0), // (terminated)
.reset_req_in4 (1'b0), // (terminated)
.reset_in5 (1'b0), // (terminated)
.reset_req_in5 (1'b0), // (terminated)
.reset_in6 (1'b0), // (terminated)
.reset_req_in6 (1'b0), // (terminated)
.reset_in7 (1'b0), // (terminated)
.reset_req_in7 (1'b0), // (terminated)
.reset_in8 (1'b0), // (terminated)
.reset_req_in8 (1'b0), // (terminated)
.reset_in9 (1'b0), // (terminated)
.reset_req_in9 (1'b0), // (terminated)
.reset_in10 (1'b0), // (terminated)
.reset_req_in10 (1'b0), // (terminated)
.reset_in11 (1'b0), // (terminated)
.reset_req_in11 (1'b0), // (terminated)
.reset_in12 (1'b0), // (terminated)
.reset_req_in12 (1'b0), // (terminated)
.reset_in13 (1'b0), // (terminated)
.reset_req_in13 (1'b0), // (terminated)
.reset_in14 (1'b0), // (terminated)
.reset_req_in14 (1'b0), // (terminated)
.reset_in15 (1'b0), // (terminated)
.reset_req_in15 (1'b0) // (terminated)
);
endmodule
|
module sky130_fd_sc_lp__clkinvlp_2 (
Y ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__clkinvlp base (
.Y(Y),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
|
module sky130_fd_sc_lp__clkinvlp_2 (
Y,
A
);
output Y;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__clkinvlp base (
.Y(Y),
.A(A)
);
endmodule
|
module cpu_tb();
reg clk = 0;
//
// ROM
//
localparam MEM_ADDR = 4;
localparam MEM_EXTRA = 4;
reg [ MEM_ADDR :0] mem_addr;
reg [ MEM_EXTRA-1:0] mem_extra;
reg [ MEM_ADDR :0] rom_lower_bound = 0;
reg [ MEM_ADDR :0] rom_upper_bound = ~0;
wire [2**MEM_EXTRA*8-1:0] mem_data;
wire mem_error;
genrom #(
.ROMFILE("i64.reinterpret-f64.hex"),
.AW(MEM_ADDR),
.DW(8),
.EXTRA(MEM_EXTRA)
)
ROM (
.clk(clk),
.addr(mem_addr),
.extra(mem_extra),
.lower_bound(rom_lower_bound),
.upper_bound(rom_upper_bound),
.data(mem_data),
.error(mem_error)
);
//
// CPU
//
parameter HAS_FPU = 1;
parameter USE_64B = 1;
reg reset = 0;
wire [63:0] result;
wire [ 1:0] result_type;
wire result_empty;
wire [ 3:0] trap;
cpu #(
.HAS_FPU(HAS_FPU),
.USE_64B(USE_64B),
.MEM_DEPTH(MEM_ADDR)
)
dut
(
.clk(clk),
.reset(reset),
.result(result),
.result_type(result_type),
.result_empty(result_empty),
.trap(trap),
.mem_addr(mem_addr),
.mem_extra(mem_extra),
.mem_data(mem_data),
.mem_error(mem_error)
);
always #1 clk = ~clk;
initial begin
$dumpfile("i64.reinterpret-f64_tb.vcd");
$dumpvars(0, cpu_tb);
if(HAS_FPU && USE_64B) begin
#30
`assert(result, 64'hc000000000000000);
`assert(result_type, `i64);
`assert(result_empty, 0);
end
else if(HAS_FPU) begin
#12
`assert(trap, `NO_64B);
end
else begin
#12
`assert(trap, `NO_FPU);
end
$finish;
end
endmodule
|
module qa_wrapper
#(
parameter WDTH = 32
)
(
input wire clk,
input wire reset,
input wire [WDTH-1:0] in_data,
input wire in_nd,
output reg [WDTH-1:0] out_data,
output reg out_nd
);
wire rst_n;
assign rst_n = ~reset;
reg read_delete;
wire read_full;
wire [WDTH-1:0] read_data;
wire write_error;
wire read_error;
reg [`LOG_BURST_LENGTH-1:0] burst_counter;
buffer_AA #(WDTH, `BUFFER_LENGTH, `LOG_BUFFER_LENGTH)
the_buffer
(.clk(clk),
.rst_n(rst_n),
.write_strobe(in_nd),
.write_data(in_data),
.read_delete(read_delete),
.read_full(read_full),
.read_data(read_data),
.write_error(write_error),
.read_error(read_error)
);
always @ (posedge clk)
begin
if (!rst_n)
begin
read_delete <= 1'b0;
out_data <= {WDTH{1'b0}};
out_nd <= 1'b0;
burst_counter <= {`LOG_BURST_LENGTH{1'b0}};
end
else
if (write_error)
begin
out_nd <= 1'b1;
out_data <= `WRITEERRORCODE;
read_delete <= 1'b0;
end
else if (read_error)
begin
out_nd <= 1'b1;
out_data <= `READERRORCODE;
read_delete <= 1'b0;
end
else
begin
if (!read_delete && read_full && !(|burst_counter))
begin
read_delete <= 1'b1;
out_nd <= 1'b1;
out_data <= read_data;
end
else
begin
if (!read_delete && in_nd)
burst_counter <= burst_counter + 1;
read_delete <= 1'b0;
out_nd <= 1'b0;
end
end
end
endmodule
|
module sky130_fd_sc_lp__nor4_lp (
Y ,
A ,
B ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__nor4 base (
.Y(Y),
.A(A),
.B(B),
.C(C),
.D(D),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
|
module sky130_fd_sc_lp__nor4_lp (
Y,
A,
B,
C,
D
);
output Y;
input A;
input B;
input C;
input D;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__nor4 base (
.Y(Y),
.A(A),
.B(B),
.C(C),
.D(D)
);
endmodule
|
module pc_cmp(/*AUTOARG*/
// Inputs
clk,
rst_l
);
input clk;
input rst_l;
// trap register
reg [31:0] finish_mask, diag_mask;
reg [39:0] good_trap[`GOOD_TRAP_COUNTER-1:0];
reg [39:0] bad_trap [`GOOD_TRAP_COUNTER-1:0];
reg [31:0] active_thread, back_thread, good_delay;
reg [31:0] good, good_for;
reg [7:0] done;
reg dum;
reg hit_bad;
integer max, time_tmp, trap_count;
//wire spc0_inst_done;
wire [1:0] spc0_thread_id;
wire [63:0] spc0_rtl_pc;
//wire spc1_inst_done;
wire [1:0] spc1_thread_id;
wire [63:0] spc1_rtl_pc;
//wire spc2_inst_done;
wire [1:0] spc2_thread_id;
wire [63:0] spc2_rtl_pc;
//wire spc3_inst_done;
wire [1:0] spc3_thread_id;
wire [63:0] spc3_rtl_pc;
//wire spc4_inst_done;
wire [1:0] spc4_thread_id;
wire [63:0] spc4_rtl_pc;
//wire spc5_inst_done;
wire [1:0] spc5_thread_id;
wire [63:0] spc5_rtl_pc;
//wire spc6_inst_done;
wire [1:0] spc6_thread_id;
wire [63:0] spc6_rtl_pc;
//wire spc7_inst_done;
wire [1:0] spc7_thread_id;
wire [63:0] spc7_rtl_pc;
wire sas_m0, sas_m1, sas_m2, sas_m3, sas_m4, sas_m5, sas_m6, sas_m7;
reg spc0_inst_done, spc1_inst_done, spc2_inst_done, spc3_inst_done,
spc4_inst_done, spc5_inst_done, spc6_inst_done, spc7_inst_done;
reg sas_def;
reg max_cycle;
reg [4:0] thread_status[31:0];
integer good_trap_count;
integer bad_trap_count;
//argment for stub
reg [7:0] stub_mask;
reg [7:0] stub_good;
reg good_flag;
//use this for the second reset.
initial begin
back_thread = 0;
good_delay = 0;
good_for = 0;
stub_good = 0;
if($test$plusargs("use_sas_tasks"))sas_def = 1;
else sas_def = 0;
if($test$plusargs("stop_2nd_good"))good_flag= 1;
else good_flag = 0;
max_cycle = 1;
if($test$plusargs("thread_timeout_off"))max_cycle = 0;
end
//-----------------------------------------------------------
// check bad trap
task check_bad_trap;
input [39:0] pc;
input [2:0] i;
input [4:0] thread;
integer l, j;
begin
if(active_thread[thread])begin
for(l = 0; l < bad_trap_count; l = l + 1)begin
if(bad_trap[l] == pc)begin
hit_bad = 1'b1;
good[l] = 1;
`TOP_MOD.diag_done = 1;
`ifdef INCLUDE_SAS_TASKS
if(sas_def && ($bw_list(`TOP_MOD.list_handle, 1) == 0))begin//wait until drain out.
`else
if(sas_def)begin
`endif $display("%0d: Info - > Hit Bad trap. spc(%0d) thread(%0d)", $time, i, l % 4);
`MONITOR_PATH.fail("HIT BAD TRAP");
end
else begin
$display("%0d: Info - > Hit Bad trap. spc(%0d) thread(%0d)", $time, i, l % 4);
`MONITOR_PATH.fail("HIT BAD TRAP");
end
end
end
end
end // if (active_thread[thread])
endtask // endtask
`ifdef INCLUDE_SAS_TASKS
task get_thread_status;
begin
`ifdef RTL_SPARC0
thread_status[0] = `IFUPATH0.swl.thrfsm0.thr_state;
thread_status[1] = `IFUPATH0.swl.thrfsm1.thr_state;
thread_status[2] = `IFUPATH0.swl.thrfsm2.thr_state;
thread_status[3] = `IFUPATH0.swl.thrfsm3.thr_state;
`endif
`ifdef RTL_SPARC1
thread_status[4] = `IFUPATH1.swl.thrfsm0.thr_state;
thread_status[5] = `IFUPATH1.swl.thrfsm1.thr_state;
thread_status[6] = `IFUPATH1.swl.thrfsm2.thr_state;
thread_status[7] = `IFUPATH1.swl.thrfsm3.thr_state;
`endif
`ifdef RTL_SPARC2
thread_status[8] = `IFUPATH2.swl.thrfsm0.thr_state;
thread_status[9] = `IFUPATH2.swl.thrfsm1.thr_state;
thread_status[10] = `IFUPATH2.swl.thrfsm2.thr_state;
thread_status[11] = `IFUPATH2.swl.thrfsm3.thr_state;
`endif
`ifdef RTL_SPARC3
thread_status[12] = `IFUPATH3.swl.thrfsm0.thr_state;
thread_status[13] = `IFUPATH3.swl.thrfsm1.thr_state;
thread_status[14] = `IFUPATH3.swl.thrfsm2.thr_state;
thread_status[15] = `IFUPATH3.swl.thrfsm3.thr_state;
`endif
`ifdef RTL_SPARC4
thread_status[16] = `IFUPATH4.swl.thrfsm0.thr_state;
thread_status[17] = `IFUPATH4.swl.thrfsm1.thr_state;
thread_status[18] = `IFUPATH4.swl.thrfsm2.thr_state;
thread_status[19] = `IFUPATH4.swl.thrfsm3.thr_state;
`endif
`ifdef RTL_SPARC5
thread_status[20] = `IFUPATH5.swl.thrfsm0.thr_state;
thread_status[21] = `IFUPATH5.swl.thrfsm1.thr_state;
thread_status[22] = `IFUPATH5.swl.thrfsm2.thr_state;
thread_status[23] = `IFUPATH5.swl.thrfsm3.thr_state;
`endif
`ifdef RTL_SPARC6
thread_status[24] = `IFUPATH6.swl.thrfsm0.thr_state;
thread_status[25] = `IFUPATH6.swl.thrfsm1.thr_state;
thread_status[26] = `IFUPATH6.swl.thrfsm2.thr_state;
thread_status[27] = `IFUPATH6.swl.thrfsm3.thr_state;
`endif
`ifdef RTL_SPARC7
thread_status[28] = `IFUPATH7.swl.thrfsm0.thr_state;
thread_status[29] = `IFUPATH7.swl.thrfsm1.thr_state;
thread_status[30] = `IFUPATH7.swl.thrfsm2.thr_state;
thread_status[31] = `IFUPATH7.swl.thrfsm3.thr_state;
`endif
end
endtask // get_thread_status
`endif
`ifdef RTL_SPARC0
`ifdef GATE_SIM_SPARC
assign sas_m0 = `INSTPATH0.runw_ff_u_dff_0_.d &
(~`INSTPATH0.exu_ifu_ecc_ce_m | `INSTPATH0.trapm_ff_u_dff_0_.q);
assign spc0_thread_id = {`PCPATH0.ifu_fcl.thrw_reg_q_tmp_3_ | `PCPATH0.ifu_fcl.thrw_reg_q_tmp_2_,
`PCPATH0.ifu_fcl.thrw_reg_q_tmp_3_ | `PCPATH0.ifu_fcl.thrw_reg_q_tmp_1_};
assign spc0_rtl_pc = `SPCPATH0.ifu_fdp.pc_w[47:0];
`else
assign sas_m0 = `INSTPATH0.inst_vld_m & ~`INSTPATH0.kill_thread_m &
~(`INSTPATH0.exu_ifu_ecc_ce_m & `INSTPATH0.inst_vld_m & ~`INSTPATH0.trap_m);
assign spc0_thread_id = `PCPATH0.fcl.sas_thrid_w;
assign spc0_rtl_pc = `SPCPATH0.ifu.fdp.pc_w[47:0];
`endif // ifdef GATE_SIM_SPARC
`else // !ifdef RTL_SPARC0
assign spc0_rtl_pc = 'h0;
assign spc0_thread_id = 'h0;
assign sas_m0 = 0;
`endif // ifdef RTL_SPARC0
`ifdef RTL_SPARC1
`ifdef GATE_SIM_SPARC
assign sas_m1 = `INSTPATH1.runw_ff_u_dff_0_.d &
(~`INSTPATH1.exu_ifu_ecc_ce_m | `INSTPATH1.trapm_ff_u_dff_0_.q);
assign spc1_thread_id = {`PCPATH1.ifu_fcl.thrw_reg_q_tmp_3_ | `PCPATH1.ifu_fcl.thrw_reg_q_tmp_2_,
`PCPATH1.ifu_fcl.thrw_reg_q_tmp_3_ | `PCPATH1.ifu_fcl.thrw_reg_q_tmp_1_};
assign spc1_rtl_pc = `SPCPATH1.ifu_fdp.pc_w[47:0];
`else
assign spc1_thread_id = `PCPATH1.fcl.sas_thrid_w;
assign sas_m1 = `INSTPATH1.inst_vld_m & ~`INSTPATH1.kill_thread_m &
~(`INSTPATH1.exu_ifu_ecc_ce_m & `INSTPATH1.inst_vld_m & ~`INSTPATH1.trap_m);
assign spc1_rtl_pc = `SPCPATH1.ifu.fdp.pc_w[47:0];
`endif // ifdef GATE_SIM_SPARC
`else // !ifdef RTL_SPARC1
assign spc1_rtl_pc = 'h0;
assign spc1_thread_id = 'h0;
assign sas_m1 = 0;
`endif // !ifdef RTL_SPARC1
`ifdef RTL_SPARC2
`ifdef GATE_SIM_SPARC
assign sas_m2 = `INSTPATH2.runw_ff_u_dff_0_.d &
(~`INSTPATH2.exu_ifu_ecc_ce_m | `INSTPATH2.trapm_ff_u_dff_0_.q);
assign spc2_thread_id = {`PCPATH2.ifu_fcl.thrw_reg_q_tmp_3_ | `PCPATH2.ifu_fcl.thrw_reg_q_tmp_2_,
`PCPATH2.ifu_fcl.thrw_reg_q_tmp_3_ | `PCPATH2.ifu_fcl.thrw_reg_q_tmp_1_};
assign spc2_rtl_pc = `SPCPATH2.ifu_fdp.pc_w[47:0];
`else
assign spc2_thread_id = `PCPATH2.fcl.sas_thrid_w;
assign sas_m2 = `INSTPATH2.inst_vld_m & ~`INSTPATH2.kill_thread_m &
~(`INSTPATH2.exu_ifu_ecc_ce_m & `INSTPATH2.inst_vld_m & ~`INSTPATH2.trap_m);
assign spc2_rtl_pc = `SPCPATH2.ifu.fdp.pc_w[47:0];
`endif // ifdef GATE_SIM_SPARC
`else // !ifdef RTL_SPARC2
assign spc2_rtl_pc = 'h0;
assign spc2_thread_id = 'h0;
assign sas_m2 = 0;
`endif
`ifdef RTL_SPARC3
`ifdef GATE_SIM_SPARC
assign sas_m3 = `INSTPATH3.runw_ff_u_dff_0_.d &
(~`INSTPATH3.exu_ifu_ecc_ce_m | `INSTPATH3.trapm_ff_u_dff_0_.q);
assign spc3_thread_id = {`PCPATH3.ifu_fcl.thrw_reg_q_tmp_3_ | `PCPATH3.ifu_fcl.thrw_reg_q_tmp_2_,
`PCPATH3.ifu_fcl.thrw_reg_q_tmp_3_ | `PCPATH3.ifu_fcl.thrw_reg_q_tmp_1_};
assign spc3_rtl_pc = `SPCPATH3.ifu_fdp.pc_w[47:0];
`else
assign spc3_thread_id = `PCPATH3.fcl.sas_thrid_w;
assign sas_m3 = `INSTPATH3.inst_vld_m & ~`INSTPATH3.kill_thread_m &
~(`INSTPATH3.exu_ifu_ecc_ce_m & `INSTPATH3.inst_vld_m & ~`INSTPATH3.trap_m);
assign spc3_rtl_pc = `SPCPATH3.ifu.fdp.pc_w[47:0];
`endif // ifdef GATE_SIM_SPARC
`else // !ifdef RTL_SPARC3
assign spc3_rtl_pc = 'h0;
assign spc3_thread_id = 'h0;
assign sas_m3 = 0;
`endif
`ifdef RTL_SPARC4
`ifdef GATE_SIM_SPARC
assign sas_m4 = `INSTPATH4.runw_ff_u_dff_0_.d &
(~`INSTPATH4.exu_ifu_ecc_ce_m | `INSTPATH4.trapm_ff_u_dff_0_.q);
assign spc4_thread_id = {`PCPATH4.ifu_fcl.thrw_reg_q_tmp_3_ | `PCPATH4.ifu_fcl.thrw_reg_q_tmp_2_,
`PCPATH4.ifu_fcl.thrw_reg_q_tmp_3_ | `PCPATH4.ifu_fcl.thrw_reg_q_tmp_1_};
assign spc4_rtl_pc = `SPCPATH4.ifu_fdp.pc_w[47:0];
`else
assign spc4_thread_id = `PCPATH4.fcl.sas_thrid_w;
assign sas_m4 = `INSTPATH4.inst_vld_m & ~`INSTPATH4.kill_thread_m &
~(`INSTPATH4.exu_ifu_ecc_ce_m & `INSTPATH4.inst_vld_m & ~`INSTPATH4.trap_m);
assign spc4_rtl_pc = `SPCPATH4.ifu.fdp.pc_w[47:0];
`endif // ifdef GATE_SIM_SPARC
`else
//assign spc4_inst_done = 'h0;
assign spc4_rtl_pc = 'h0;
assign spc4_thread_id = 'h0;
assign sas_m4 = 0;
`endif
`ifdef RTL_SPARC5
`ifdef GATE_SIM_SPARC
assign sas_m5 = `INSTPATH5.runw_ff_u_dff_0_.d &
(~`INSTPATH5.exu_ifu_ecc_ce_m | `INSTPATH5.trapm_ff_u_dff_0_.q);
assign spc5_thread_id = {`PCPATH5.ifu_fcl.thrw_reg_q_tmp_3_ | `PCPATH5.ifu_fcl.thrw_reg_q_tmp_2_,
`PCPATH5.ifu_fcl.thrw_reg_q_tmp_3_ | `PCPATH5.ifu_fcl.thrw_reg_q_tmp_1_};
assign spc5_rtl_pc = `SPCPATH5.ifu_fdp.pc_w[47:0];
`else
assign spc5_thread_id = `PCPATH5.fcl.sas_thrid_w;
assign sas_m5 = `INSTPATH5.inst_vld_m & ~`INSTPATH5.kill_thread_m &
~(`INSTPATH5.exu_ifu_ecc_ce_m & `INSTPATH5.inst_vld_m & ~`INSTPATH5.trap_m);
assign spc5_rtl_pc = `SPCPATH5.ifu.fdp.pc_w[47:0];
`endif // ifdef GATE_SIM_SPARC
`else
assign spc5_rtl_pc = 'h0;
assign spc5_thread_id = 'h0;
assign sas_m5 = 0;
`endif
`ifdef RTL_SPARC6
`ifdef GATE_SIM_SPARC
assign sas_m6 = `INSTPATH6.runw_ff_u_dff_0_.d &
(~`INSTPATH6.exu_ifu_ecc_ce_m | `INSTPATH6.trapm_ff_u_dff_0_.q);
assign spc6_thread_id = {`PCPATH6.ifu_fcl.thrw_reg_q_tmp_3_ | `PCPATH6.ifu_fcl.thrw_reg_q_tmp_2_,
`PCPATH6.ifu_fcl.thrw_reg_q_tmp_3_ | `PCPATH6.ifu_fcl.thrw_reg_q_tmp_1_};
assign spc6_rtl_pc = `SPCPATH6.ifu_fdp.pc_w[47:0];
`else
assign spc6_thread_id = `PCPATH6.fcl.sas_thrid_w;
assign sas_m6 = `INSTPATH6.inst_vld_m & ~`INSTPATH6.kill_thread_m &
~(`INSTPATH6.exu_ifu_ecc_ce_m & `INSTPATH6.inst_vld_m & ~`INSTPATH6.trap_m);
assign spc6_rtl_pc = `SPCPATH6.ifu.fdp.pc_w[47:0];
`endif // ifdef GATE_SIM_SPARC
`else
assign spc6_rtl_pc = 'h0;
assign spc6_thread_id = 'h0;
assign sas_m6 = 0;
`endif
`ifdef RTL_SPARC7
`ifdef GATE_SIM_SPARC
assign sas_m7 = `INSTPATH7.runw_ff_u_dff_0_.d &
(~`INSTPATH7.exu_ifu_ecc_ce_m | `INSTPATH7.trapm_ff_u_dff_0_.q);
assign spc7_thread_id = {`PCPATH7.ifu_fcl.thrw_reg_q_tmp_3_ | `PCPATH7.ifu_fcl.thrw_reg_q_tmp_2_,
`PCPATH7.ifu_fcl.thrw_reg_q_tmp_3_ | `PCPATH7.ifu_fcl.thrw_reg_q_tmp_1_};
assign spc7_rtl_pc = `SPCPATH7.ifu_fdp.pc_w[47:0];
`else
assign spc7_thread_id = `PCPATH7.fcl.sas_thrid_w;
assign sas_m7 = `INSTPATH7.inst_vld_m & ~`INSTPATH7.kill_thread_m &
~(`INSTPATH7.exu_ifu_ecc_ce_m & `INSTPATH7.inst_vld_m & ~`INSTPATH7.trap_m);
assign spc7_rtl_pc = `SPCPATH7.ifu.fdp.pc_w[47:0];
`endif // ifdef GATE_SIM_SPARC
`else
assign spc7_rtl_pc = 'h0;
assign spc7_thread_id = 'h0;
assign sas_m7 = 0;
`endif // !ifdef SP7
reg [63:0] spc0_phy_pc_w, spc1_phy_pc_w, spc2_phy_pc_w, spc3_phy_pc_w,
spc4_phy_pc_w, spc5_phy_pc_w, spc6_phy_pc_w, spc7_phy_pc_w;
`ifdef RTL_SPARC0
reg [63:0] spc0_phy_pc_d, spc0_phy_pc_e, spc0_phy_pc_m,
spc0_t0pc_s, spc0_t1pc_s, spc0_t2pc_s, spc0_t3pc_s ;
reg [3:0] spc0_fcl_fdp_nextpcs_sel_pcf_f_l_e,
spc0_fcl_fdp_nextpcs_sel_pcs_f_l_e,
spc0_fcl_fdp_nextpcs_sel_pcd_f_l_e,
spc0_fcl_fdp_nextpcs_sel_pce_f_l_e;
wire [3:0] pcs0 = spc0_fcl_fdp_nextpcs_sel_pcs_f_l_e;
wire [3:0] pcf0 = spc0_fcl_fdp_nextpcs_sel_pcf_f_l_e;
wire [3:0] pcd0 = spc0_fcl_fdp_nextpcs_sel_pcd_f_l_e;
wire [3:0] pce0 = spc0_fcl_fdp_nextpcs_sel_pce_f_l_e;
wire [63:0] spc0_imiss_paddr_s ;
`ifdef GATE_SIM_SPARC
assign spc0_imiss_paddr_s = {`IFQDP0.itlb_ifq_paddr_s, `IFQDP0.lcl_paddr_s, 2'b0} ;
`else
assign spc0_imiss_paddr_s = `IFQDP0.imiss_paddr_s ;
`endif // GATE_SIM_SPARC
`endif // `ifdef RTL_SPARC0
`ifdef RTL_SPARC1
reg [63:0] spc1_phy_pc_d, spc1_phy_pc_e, spc1_phy_pc_m,
spc1_t0pc_s, spc1_t1pc_s, spc1_t2pc_s, spc1_t3pc_s;
reg [3:0] spc1_fcl_fdp_nextpcs_sel_pcf_f_l_e,
spc1_fcl_fdp_nextpcs_sel_pcs_f_l_e,
spc1_fcl_fdp_nextpcs_sel_pcd_f_l_e,
spc1_fcl_fdp_nextpcs_sel_pce_f_l_e;
wire [3:0] pcs1 = spc1_fcl_fdp_nextpcs_sel_pcs_f_l_e;
wire [3:0] pcf1 = spc1_fcl_fdp_nextpcs_sel_pcf_f_l_e;
wire [3:0] pcd1 = spc1_fcl_fdp_nextpcs_sel_pcd_f_l_e;
wire [3:0] pce1 = spc1_fcl_fdp_nextpcs_sel_pce_f_l_e;
wire [63:0] spc1_imiss_paddr_s ;
`ifdef GATE_SIM_SPARC
assign spc1_imiss_paddr_s = {`IFQDP1.itlb_ifq_paddr_s, `IFQDP1.lcl_paddr_s, 2'b0} ;
`else
assign spc1_imiss_paddr_s = `IFQDP1.imiss_paddr_s ;
`endif // GATE_SIM_SPARC
`endif
`ifdef RTL_SPARC2
reg [63:0] spc2_phy_pc_d, spc2_phy_pc_e, spc2_phy_pc_m,
spc2_t0pc_s, spc2_t1pc_s, spc2_t2pc_s, spc2_t3pc_s;
reg [3:0] spc2_fcl_fdp_nextpcs_sel_pcf_f_l_e,
spc2_fcl_fdp_nextpcs_sel_pcs_f_l_e,
spc2_fcl_fdp_nextpcs_sel_pcd_f_l_e,
spc2_fcl_fdp_nextpcs_sel_pce_f_l_e;
wire [3:0] pcs2 = spc2_fcl_fdp_nextpcs_sel_pcs_f_l_e;
wire [3:0] pcf2 = spc2_fcl_fdp_nextpcs_sel_pcf_f_l_e;
wire [3:0] pcd2 = spc2_fcl_fdp_nextpcs_sel_pcd_f_l_e;
wire [3:0] pce2 = spc2_fcl_fdp_nextpcs_sel_pce_f_l_e;
wire [63:0] spc2_imiss_paddr_s ;
`ifdef GATE_SIM_SPARC
assign spc2_imiss_paddr_s = {`IFQDP2.itlb_ifq_paddr_s, `IFQDP2.lcl_paddr_s, 2'b0} ;
`else
assign spc2_imiss_paddr_s = `IFQDP2.imiss_paddr_s ;
`endif // GATE_SIM_SPARC
`endif // `ifdef RTL_SPARC0
`ifdef RTL_SPARC3
reg [63:0] spc3_phy_pc_d, spc3_phy_pc_e, spc3_phy_pc_m,
spc3_t0pc_s, spc3_t1pc_s, spc3_t2pc_s, spc3_t3pc_s;
reg [3:0] spc3_fcl_fdp_nextpcs_sel_pcf_f_l_e,
spc3_fcl_fdp_nextpcs_sel_pcs_f_l_e,
spc3_fcl_fdp_nextpcs_sel_pcd_f_l_e,
spc3_fcl_fdp_nextpcs_sel_pce_f_l_e;
wire [3:0] pcs3 = spc3_fcl_fdp_nextpcs_sel_pcs_f_l_e;
wire [3:0] pcf3 = spc3_fcl_fdp_nextpcs_sel_pcf_f_l_e;
wire [3:0] pcd3 = spc3_fcl_fdp_nextpcs_sel_pcd_f_l_e;
wire [3:0] pce3 = spc3_fcl_fdp_nextpcs_sel_pce_f_l_e;
wire [63:0] spc3_imiss_paddr_s ;
`ifdef GATE_SIM_SPARC
assign spc3_imiss_paddr_s = {`IFQDP3.itlb_ifq_paddr_s, `IFQDP3.lcl_paddr_s, 2'b0} ;
`else
assign spc3_imiss_paddr_s = `IFQDP3.imiss_paddr_s ;
`endif // GATE_SIM_SPARC
`endif // `ifdef RTL_SPARC3
`ifdef RTL_SPARC4
reg [63:0] spc4_phy_pc_d, spc4_phy_pc_e, spc4_phy_pc_m,
spc4_t0pc_s, spc4_t1pc_s, spc4_t2pc_s, spc4_t3pc_s;
reg [3:0] spc4_fcl_fdp_nextpcs_sel_pcf_f_l_e,
spc4_fcl_fdp_nextpcs_sel_pcs_f_l_e,
spc4_fcl_fdp_nextpcs_sel_pcd_f_l_e,
spc4_fcl_fdp_nextpcs_sel_pce_f_l_e;
wire [3:0] pcs4 = spc4_fcl_fdp_nextpcs_sel_pcs_f_l_e;
wire [3:0] pcf4 = spc4_fcl_fdp_nextpcs_sel_pcf_f_l_e;
wire [3:0] pcd4 = spc4_fcl_fdp_nextpcs_sel_pcd_f_l_e;
wire [3:0] pce4 = spc4_fcl_fdp_nextpcs_sel_pce_f_l_e;
wire [63:0] spc4_imiss_paddr_s ;
`ifdef GATE_SIM_SPARC
assign spc4_imiss_paddr_s = {`IFQDP4.itlb_ifq_paddr_s, `IFQDP4.lcl_paddr_s, 2'b0} ;
`else
assign spc4_imiss_paddr_s = `IFQDP4.imiss_paddr_s ;
`endif // GATE_SIM_SPARC
`endif // `ifdef RTL_SPARC4
`ifdef RTL_SPARC5
reg [63:0] spc5_phy_pc_d, spc5_phy_pc_e, spc5_phy_pc_m,
spc5_t0pc_s, spc5_t1pc_s, spc5_t2pc_s, spc5_t3pc_s;
reg [3:0] spc5_fcl_fdp_nextpcs_sel_pcf_f_l_e,
spc5_fcl_fdp_nextpcs_sel_pcs_f_l_e,
spc5_fcl_fdp_nextpcs_sel_pcd_f_l_e,
spc5_fcl_fdp_nextpcs_sel_pce_f_l_e;
wire [3:0] pcs5 = spc5_fcl_fdp_nextpcs_sel_pcs_f_l_e;
wire [3:0] pcf5 = spc5_fcl_fdp_nextpcs_sel_pcf_f_l_e;
wire [3:0] pcd5 = spc5_fcl_fdp_nextpcs_sel_pcd_f_l_e;
wire [3:0] pce5 = spc5_fcl_fdp_nextpcs_sel_pce_f_l_e;
wire [63:0] spc5_imiss_paddr_s ;
`ifdef GATE_SIM_SPARC
assign spc5_imiss_paddr_s = {`IFQDP5.itlb_ifq_paddr_s, `IFQDP5.lcl_paddr_s, 2'b0} ;
`else
assign spc5_imiss_paddr_s = `IFQDP5.imiss_paddr_s ;
`endif // GATE_SIM_SPARC
`endif // `ifdef RTL_SPARC5
`ifdef RTL_SPARC6
reg [63:0] spc6_phy_pc_d, spc6_phy_pc_e, spc6_phy_pc_m,
spc6_t0pc_s, spc6_t1pc_s, spc6_t2pc_s, spc6_t3pc_s;
reg [3:0] spc6_fcl_fdp_nextpcs_sel_pcf_f_l_e,
spc6_fcl_fdp_nextpcs_sel_pcs_f_l_e,
spc6_fcl_fdp_nextpcs_sel_pcd_f_l_e,
spc6_fcl_fdp_nextpcs_sel_pce_f_l_e;
wire [3:0] pcs6 = spc6_fcl_fdp_nextpcs_sel_pcs_f_l_e;
wire [3:0] pcf6 = spc6_fcl_fdp_nextpcs_sel_pcf_f_l_e;
wire [3:0] pcd6 = spc6_fcl_fdp_nextpcs_sel_pcd_f_l_e;
wire [3:0] pce6 = spc6_fcl_fdp_nextpcs_sel_pce_f_l_e;
wire [63:0] spc6_imiss_paddr_s ;
`ifdef GATE_SIM_SPARC
assign spc6_imiss_paddr_s = {`IFQDP6.itlb_ifq_paddr_s, `IFQDP6.lcl_paddr_s, 2'b0} ;
`else
assign spc6_imiss_paddr_s = `IFQDP6.imiss_paddr_s ;
`endif // GATE_SIM_SPARC
`endif // `ifdef RTL_SPARC6
`ifdef RTL_SPARC7
reg [63:0] spc7_phy_pc_d, spc7_phy_pc_e, spc7_phy_pc_m,
spc7_t0pc_s, spc7_t1pc_s, spc7_t2pc_s, spc7_t3pc_s;
reg [3:0] spc7_fcl_fdp_nextpcs_sel_pcf_f_l_e,
spc7_fcl_fdp_nextpcs_sel_pcs_f_l_e,
spc7_fcl_fdp_nextpcs_sel_pcd_f_l_e,
spc7_fcl_fdp_nextpcs_sel_pce_f_l_e;
wire [3:0] pcs7 = spc7_fcl_fdp_nextpcs_sel_pcs_f_l_e;
wire [3:0] pcf7 = spc7_fcl_fdp_nextpcs_sel_pcf_f_l_e;
wire [3:0] pcd7 = spc7_fcl_fdp_nextpcs_sel_pcd_f_l_e;
wire [3:0] pce7 = spc7_fcl_fdp_nextpcs_sel_pce_f_l_e;
wire [63:0] spc7_imiss_paddr_s ;
`ifdef GATE_SIM_SPARC
assign spc7_imiss_paddr_s = {`IFQDP7.itlb_ifq_paddr_s, `IFQDP7.lcl_paddr_s, 2'b0} ;
`else
assign spc7_imiss_paddr_s = `IFQDP7.imiss_paddr_s ;
`endif // GATE_SIM_SPARC
`endif // `ifdef RTL_SPARC7
always @(posedge clk) begin
`ifdef RTL_SPARC0
//done
spc0_inst_done <= sas_m0;
//next pc select
spc0_fcl_fdp_nextpcs_sel_pcs_f_l_e <= `DTUPATH0.fcl_fdp_nextpcs_sel_pcs_f_l;
spc0_fcl_fdp_nextpcs_sel_pcf_f_l_e <= `DTUPATH0.fcl_fdp_nextpcs_sel_pcf_f_l;
spc0_fcl_fdp_nextpcs_sel_pcd_f_l_e <= `DTUPATH0.fcl_fdp_nextpcs_sel_pcd_f_l;
spc0_fcl_fdp_nextpcs_sel_pce_f_l_e <= `DTUPATH0.fcl_fdp_nextpcs_sel_pce_f_l;
//pipe physical pc
if(pcf0[0] == 0)spc0_t0pc_s <= spc0_imiss_paddr_s;
else if(pcs0[0] == 0)spc0_t0pc_s <= spc0_t0pc_s;
else if(pcd0[0] == 0)spc0_t0pc_s <= spc0_phy_pc_e;
else if(pce0[0] == 0)spc0_t0pc_s <= spc0_phy_pc_m;
if(pcf0[1] == 0)spc0_t1pc_s <= spc0_imiss_paddr_s;
else if(pcs0[1] == 0)spc0_t1pc_s <= spc0_t1pc_s;
else if(pcd0[1] == 0)spc0_t1pc_s <= spc0_phy_pc_e;
else if(pce0[1] == 0)spc0_t1pc_s <= spc0_phy_pc_m;
if(pcf0[2] == 0)spc0_t2pc_s <= spc0_imiss_paddr_s;
else if(pcs0[2] == 0)spc0_t2pc_s <= spc0_t2pc_s;
else if(pcd0[2] == 0)spc0_t2pc_s <= spc0_phy_pc_e;
else if(pce0[2] == 0)spc0_t2pc_s <= spc0_phy_pc_m;
if(pcf0[3] == 0)spc0_t3pc_s <= spc0_imiss_paddr_s;
else if(pcs0[3] == 0)spc0_t3pc_s <= spc0_t3pc_s;
else if(pcd0[3] == 0)spc0_t3pc_s <= spc0_phy_pc_e;
else if(pce0[3] == 0)spc0_t3pc_s <= spc0_phy_pc_m;
if(~`DTUPATH0.fcl_fdp_thr_s2_l[0]) spc0_phy_pc_d <= pcf0[0] ? spc0_t0pc_s : spc0_imiss_paddr_s;
else if(~`DTUPATH0.fcl_fdp_thr_s2_l[1])spc0_phy_pc_d <= pcf0[1] ? spc0_t1pc_s : spc0_imiss_paddr_s;
else if(~`DTUPATH0.fcl_fdp_thr_s2_l[2])spc0_phy_pc_d <= pcf0[2] ? spc0_t2pc_s : spc0_imiss_paddr_s;
else if(~`DTUPATH0.fcl_fdp_thr_s2_l[3])spc0_phy_pc_d <= pcf0[3] ? spc0_t3pc_s : spc0_imiss_paddr_s;
spc0_phy_pc_e <= spc0_phy_pc_d;
spc0_phy_pc_m <= spc0_phy_pc_e;
spc0_phy_pc_w <= {{8{spc0_phy_pc_m[39]}}, spc0_phy_pc_m[39:0]};
if(spc0_inst_done &&
active_thread[{3'b000,spc0_thread_id[1:0]}])begin
/*
if(0 & $x_checker(`DTUPATH0.pc_w))begin
$display("%0d: Detected unkown pc value spc(%d) thread(%x) value(%x)",
$time, 3'b000, spc0_thread_id[1:0], `DTUPATH0.pc_w);
`MONITOR_PATH.fail("Detected unkown pc");
end
*/
end
`endif // ifdef RTL_SPARC0
`ifdef RTL_SPARC1
//done
spc1_inst_done <= sas_m1;
//next pc select
spc1_fcl_fdp_nextpcs_sel_pcs_f_l_e <= `DTUPATH1.fcl_fdp_nextpcs_sel_pcs_f_l;
spc1_fcl_fdp_nextpcs_sel_pcf_f_l_e <= `DTUPATH1.fcl_fdp_nextpcs_sel_pcf_f_l;
spc1_fcl_fdp_nextpcs_sel_pcd_f_l_e <= `DTUPATH1.fcl_fdp_nextpcs_sel_pcd_f_l;
spc1_fcl_fdp_nextpcs_sel_pce_f_l_e <= `DTUPATH1.fcl_fdp_nextpcs_sel_pce_f_l;
//pipe physical pc
if( pcf1[0] == 0)spc1_t0pc_s <= spc1_imiss_paddr_s;
else if(pcs1[0] == 0)spc1_t0pc_s <= spc1_t0pc_s;
else if(pcd1[0] == 0)spc1_t0pc_s <= spc1_phy_pc_e;
else if(pce1[0] == 0)spc1_t0pc_s <= spc1_phy_pc_m;
if( pcf1[1] == 0)spc1_t1pc_s <= spc1_imiss_paddr_s;
else if(pcs1[1] == 0)spc1_t1pc_s <= spc1_t1pc_s;
else if(pcd1[1] == 0)spc1_t1pc_s <= spc1_phy_pc_e;
else if(pce1[1] == 0)spc1_t1pc_s <= spc1_phy_pc_m;
if( pcf1[2] == 0)spc1_t2pc_s <= spc1_imiss_paddr_s;
else if(pcs1[2] == 0)spc1_t2pc_s <= spc1_t2pc_s;
else if(pcd1[2] == 0)spc1_t2pc_s <= spc1_phy_pc_e;
else if(pce1[2] == 0)spc1_t2pc_s <= spc1_phy_pc_m;
if( pcf1[3] == 0)spc1_t3pc_s <= spc1_imiss_paddr_s;
else if(pcs1[3] == 0)spc1_t3pc_s <= spc1_t3pc_s;
else if(pcd1[3] == 0)spc1_t3pc_s <= spc1_phy_pc_e;
else if(pce1[3] == 0)spc1_t3pc_s <= spc1_phy_pc_m;
if( ~`DTUPATH1.fcl_fdp_thr_s2_l[0])spc1_phy_pc_d <= pcf1[0] ? spc1_t0pc_s : spc1_imiss_paddr_s;
else if(~`DTUPATH1.fcl_fdp_thr_s2_l[1])spc1_phy_pc_d <= pcf1[1] ? spc1_t1pc_s : spc1_imiss_paddr_s;
else if(~`DTUPATH1.fcl_fdp_thr_s2_l[2])spc1_phy_pc_d <= pcf1[2] ? spc1_t2pc_s : spc1_imiss_paddr_s;
else if(~`DTUPATH1.fcl_fdp_thr_s2_l[3])spc1_phy_pc_d <= pcf1[3] ? spc1_t3pc_s : spc1_imiss_paddr_s;
spc1_phy_pc_e <= spc1_phy_pc_d;
spc1_phy_pc_m <= spc1_phy_pc_e;
spc1_phy_pc_w <= {{8{spc1_phy_pc_m[39]}}, spc1_phy_pc_m[39:0]};
if(spc1_inst_done &&
active_thread[{3'b001,spc1_thread_id[1:0]}])begin
/*
if(0 & $x_checker(`DTUPATH1.pc_w))begin
$display("%0d: Detected unkown pc value spc(%d) thread(%x) value(%x)",
$time, 3'b001, spc1_thread_id[1:0], `DTUPATH1.pc_w);
`MONITOR_PATH.fail("Detected unkown pc");
end
*/
end
`endif // ifdef RTL_SPARC1
`ifdef RTL_SPARC2
//done
spc2_inst_done <= sas_m2;
//next pc select
spc2_fcl_fdp_nextpcs_sel_pcs_f_l_e <= `DTUPATH2.fcl_fdp_nextpcs_sel_pcs_f_l;
spc2_fcl_fdp_nextpcs_sel_pcf_f_l_e <= `DTUPATH2.fcl_fdp_nextpcs_sel_pcf_f_l;
spc2_fcl_fdp_nextpcs_sel_pcd_f_l_e <= `DTUPATH2.fcl_fdp_nextpcs_sel_pcd_f_l;
spc2_fcl_fdp_nextpcs_sel_pce_f_l_e <= `DTUPATH2.fcl_fdp_nextpcs_sel_pce_f_l;
//pipe physical pc
if(pcf2[0] == 0)spc2_t0pc_s <= spc2_imiss_paddr_s;
else if(pcs2[0] == 0)spc2_t0pc_s <= spc2_t0pc_s;
else if(pcd2[0] == 0)spc2_t0pc_s <= spc2_phy_pc_e;
else if(pce2[0] == 0)spc2_t0pc_s <= spc2_phy_pc_m;
if(pcf2[1] == 0)spc2_t1pc_s <= spc2_imiss_paddr_s;
else if(pcs2[1] == 0)spc2_t1pc_s <= spc2_t1pc_s;
else if(pcd2[1] == 0)spc2_t1pc_s <= spc2_phy_pc_e;
else if(pce2[1] == 0)spc2_t1pc_s <= spc2_phy_pc_m;
if(pcf2[2] == 0)spc2_t2pc_s <= spc2_imiss_paddr_s;
else if(pcs2[2] == 0)spc2_t2pc_s <= spc2_t2pc_s;
else if(pcd2[2] == 0)spc2_t2pc_s <= spc2_phy_pc_e;
else if(pce2[2] == 0)spc2_t2pc_s <= spc2_phy_pc_m;
if(pcf2[3] == 0)spc2_t3pc_s <= spc2_imiss_paddr_s;
else if(pcs2[3] == 0)spc2_t3pc_s <= spc2_t3pc_s;
else if(pcd2[3] == 0)spc2_t3pc_s <= spc2_phy_pc_e;
else if(pce2[3] == 0)spc2_t3pc_s <= spc2_phy_pc_m;
if(~`DTUPATH2.fcl_fdp_thr_s2_l[0]) spc2_phy_pc_d <= pcf2[0] ? spc2_t0pc_s : spc2_imiss_paddr_s;
else if(~`DTUPATH2.fcl_fdp_thr_s2_l[1])spc2_phy_pc_d <= pcf2[1] ? spc2_t1pc_s : spc2_imiss_paddr_s;
else if(~`DTUPATH2.fcl_fdp_thr_s2_l[2])spc2_phy_pc_d <= pcf2[2] ? spc2_t2pc_s : spc2_imiss_paddr_s;
else if(~`DTUPATH2.fcl_fdp_thr_s2_l[3])spc2_phy_pc_d <= pcf2[3] ? spc2_t3pc_s : spc2_imiss_paddr_s;
spc2_phy_pc_e <= spc2_phy_pc_d;
spc2_phy_pc_m <= spc2_phy_pc_e;
spc2_phy_pc_w <= {{8{spc2_phy_pc_m[39]}}, spc2_phy_pc_m[39:0]};
if(spc2_inst_done &&
active_thread[{3'b010,spc2_thread_id[1:0]}])begin
/*
if(0 & $x_checker(`DTUPATH2.pc_w))begin
$display("%0d: Detected unkown pc value spc(%d) thread(%x) value(%x)",
$time, 3'b010, spc2_thread_id[1:0], `DTUPATH2.pc_w);
`MONITOR_PATH.fail("Detected unkown pc");
end
*/
end
`endif // ifdef RTL_SPARC2
`ifdef RTL_SPARC3
//done
spc3_inst_done <= sas_m3;
//next pc select
spc3_fcl_fdp_nextpcs_sel_pcs_f_l_e <= `DTUPATH3.fcl_fdp_nextpcs_sel_pcs_f_l;
spc3_fcl_fdp_nextpcs_sel_pcf_f_l_e <= `DTUPATH3.fcl_fdp_nextpcs_sel_pcf_f_l;
spc3_fcl_fdp_nextpcs_sel_pcd_f_l_e <= `DTUPATH3.fcl_fdp_nextpcs_sel_pcd_f_l;
spc3_fcl_fdp_nextpcs_sel_pce_f_l_e <= `DTUPATH3.fcl_fdp_nextpcs_sel_pce_f_l;
//pipe physical pc
if(pcf3[0] == 0)spc3_t0pc_s <= spc3_imiss_paddr_s;
else if(pcs3[0] == 0)spc3_t0pc_s <= spc3_t0pc_s;
else if(pcd3[0] == 0)spc3_t0pc_s <= spc3_phy_pc_e;
else if(pce3[0] == 0)spc3_t0pc_s <= spc3_phy_pc_m;
if(pcf3[1] == 0)spc3_t1pc_s <= spc3_imiss_paddr_s;
else if(pcs3[1] == 0)spc3_t1pc_s <= spc3_t1pc_s;
else if(pcd3[1] == 0)spc3_t1pc_s <= spc3_phy_pc_e;
else if(pce3[1] == 0)spc3_t1pc_s <= spc3_phy_pc_m;
if(pcf3[2] == 0)spc3_t2pc_s <= spc3_imiss_paddr_s;
else if(pcs3[2] == 0)spc3_t2pc_s <= spc3_t2pc_s;
else if(pcd3[2] == 0)spc3_t2pc_s <= spc3_phy_pc_e;
else if(pce3[2] == 0)spc3_t2pc_s <= spc3_phy_pc_m;
if(pcf3[3] == 0)spc3_t3pc_s <= spc3_imiss_paddr_s;
else if(pcs3[3] == 0)spc3_t3pc_s <= spc3_t3pc_s;
else if(pcd3[3] == 0)spc3_t3pc_s <= spc3_phy_pc_e;
else if(pce3[3] == 0)spc3_t3pc_s <= spc3_phy_pc_m;
if(~`DTUPATH3.fcl_fdp_thr_s2_l[0]) spc3_phy_pc_d <= pcf3[0] ? spc3_t0pc_s : spc3_imiss_paddr_s;
else if(~`DTUPATH3.fcl_fdp_thr_s2_l[1])spc3_phy_pc_d <= pcf3[1] ? spc3_t1pc_s : spc3_imiss_paddr_s;
else if(~`DTUPATH3.fcl_fdp_thr_s2_l[2])spc3_phy_pc_d <= pcf3[2] ? spc3_t2pc_s : spc3_imiss_paddr_s;
else if(~`DTUPATH3.fcl_fdp_thr_s2_l[3])spc3_phy_pc_d <= pcf3[3] ? spc3_t3pc_s : spc3_imiss_paddr_s;
spc3_phy_pc_e <= spc3_phy_pc_d;
spc3_phy_pc_m <= spc3_phy_pc_e;
spc3_phy_pc_w <= {{8{spc3_phy_pc_m[39]}}, spc3_phy_pc_m[39:0]};
if(spc3_inst_done &&
active_thread[{3'b011,spc3_thread_id[1:0]}])begin
/*
if(0 & $x_checker(`DTUPATH3.pc_w))begin
$display("%0d: Detected unkown pc value spc(%d) thread(%x) value(%x)",
$time, 3'b011, spc3_thread_id[1:0], `DTUPATH3.pc_w);
`MONITOR_PATH.fail("Detected unkown pc");
end
*/
end
`endif // ifdef RTL_SPARC3
`ifdef RTL_SPARC4
//done
spc4_inst_done <= sas_m4;
//next pc select
spc4_fcl_fdp_nextpcs_sel_pcs_f_l_e <= `DTUPATH4.fcl_fdp_nextpcs_sel_pcs_f_l;
spc4_fcl_fdp_nextpcs_sel_pcf_f_l_e <= `DTUPATH4.fcl_fdp_nextpcs_sel_pcf_f_l;
spc4_fcl_fdp_nextpcs_sel_pcd_f_l_e <= `DTUPATH4.fcl_fdp_nextpcs_sel_pcd_f_l;
spc4_fcl_fdp_nextpcs_sel_pce_f_l_e <= `DTUPATH4.fcl_fdp_nextpcs_sel_pce_f_l;
//pipe physical pc
if(pcf4[0] == 0)spc4_t0pc_s <= spc4_imiss_paddr_s;
else if(pcs4[0] == 0)spc4_t0pc_s <= spc4_t0pc_s;
else if(pcd4[0] == 0)spc4_t0pc_s <= spc4_phy_pc_e;
else if(pce4[0] == 0)spc4_t0pc_s <= spc4_phy_pc_m;
if(pcf4[1] == 0)spc4_t1pc_s <= spc4_imiss_paddr_s;
else if(pcs4[1] == 0)spc4_t1pc_s <= spc4_t1pc_s;
else if(pcd4[1] == 0)spc4_t1pc_s <= spc4_phy_pc_e;
else if(pce4[1] == 0)spc4_t1pc_s <= spc4_phy_pc_m;
if(pcf4[2] == 0)spc4_t2pc_s <= spc4_imiss_paddr_s;
else if(pcs4[2] == 0)spc4_t2pc_s <= spc4_t2pc_s;
else if(pcd4[2] == 0)spc4_t2pc_s <= spc4_phy_pc_e;
else if(pce4[2] == 0)spc4_t2pc_s <= spc4_phy_pc_m;
if(pcf4[3] == 0)spc4_t3pc_s <= spc4_imiss_paddr_s;
else if(pcs4[3] == 0)spc4_t3pc_s <= spc4_t3pc_s;
else if(pcd4[3] == 0)spc4_t3pc_s <= spc4_phy_pc_e;
else if(pce4[3] == 0)spc4_t3pc_s <= spc4_phy_pc_m;
if(~`DTUPATH4.fcl_fdp_thr_s2_l[0]) spc4_phy_pc_d <= pcf4[0] ? spc4_t0pc_s : spc4_imiss_paddr_s;
else if(~`DTUPATH4.fcl_fdp_thr_s2_l[1])spc4_phy_pc_d <= pcf4[1] ? spc4_t1pc_s : spc4_imiss_paddr_s;
else if(~`DTUPATH4.fcl_fdp_thr_s2_l[2])spc4_phy_pc_d <= pcf4[2] ? spc4_t2pc_s : spc4_imiss_paddr_s;
else if(~`DTUPATH4.fcl_fdp_thr_s2_l[3])spc4_phy_pc_d <= pcf4[3] ? spc4_t3pc_s : spc4_imiss_paddr_s;
spc4_phy_pc_e <= spc4_phy_pc_d;
spc4_phy_pc_m <= spc4_phy_pc_e;
spc4_phy_pc_w <= {{8{spc4_phy_pc_m[39]}}, spc4_phy_pc_m[39:0]};
if(spc4_inst_done &&
active_thread[{3'b100,spc4_thread_id[1:0]}])begin
/*
if(0 & $x_checker(`DTUPATH4.pc_w))begin
$display("%0d: Detected unkown pc value spc(%d) thread(%x) value(%x)",
$time, 3'b100, spc4_thread_id[1:0], `DTUPATH4.pc_w);
`MONITOR_PATH.fail("Detected unkown pc");
end
*/
end
`endif // ifdef RTL_SPARC4
`ifdef RTL_SPARC5
//done
spc5_inst_done <= sas_m5;
//next pc select
spc5_fcl_fdp_nextpcs_sel_pcs_f_l_e <= `DTUPATH5.fcl_fdp_nextpcs_sel_pcs_f_l;
spc5_fcl_fdp_nextpcs_sel_pcf_f_l_e <= `DTUPATH5.fcl_fdp_nextpcs_sel_pcf_f_l;
spc5_fcl_fdp_nextpcs_sel_pcd_f_l_e <= `DTUPATH5.fcl_fdp_nextpcs_sel_pcd_f_l;
spc5_fcl_fdp_nextpcs_sel_pce_f_l_e <= `DTUPATH5.fcl_fdp_nextpcs_sel_pce_f_l;
//pipe physical pc
if(pcf5[0] == 0)spc5_t0pc_s <= spc5_imiss_paddr_s;
else if(pcs5[0] == 0)spc5_t0pc_s <= spc5_t0pc_s;
else if(pcd5[0] == 0)spc5_t0pc_s <= spc5_phy_pc_e;
else if(pce5[0] == 0)spc5_t0pc_s <= spc5_phy_pc_m;
if(pcf5[1] == 0)spc5_t1pc_s <= spc5_imiss_paddr_s;
else if(pcs5[1] == 0)spc5_t1pc_s <= spc5_t1pc_s;
else if(pcd5[1] == 0)spc5_t1pc_s <= spc5_phy_pc_e;
else if(pce5[1] == 0)spc5_t1pc_s <= spc5_phy_pc_m;
if(pcf5[2] == 0)spc5_t2pc_s <= spc5_imiss_paddr_s;
else if(pcs5[2] == 0)spc5_t2pc_s <= spc5_t2pc_s;
else if(pcd5[2] == 0)spc5_t2pc_s <= spc5_phy_pc_e;
else if(pce5[2] == 0)spc5_t2pc_s <= spc5_phy_pc_m;
if(pcf5[3] == 0)spc5_t3pc_s <= spc5_imiss_paddr_s;
else if(pcs5[3] == 0)spc5_t3pc_s <= spc5_t3pc_s;
else if(pcd5[3] == 0)spc5_t3pc_s <= spc5_phy_pc_e;
else if(pce5[3] == 0)spc5_t3pc_s <= spc5_phy_pc_m;
if(~`DTUPATH5.fcl_fdp_thr_s2_l[0]) spc5_phy_pc_d <= pcf5[0] ? spc5_t0pc_s : spc5_imiss_paddr_s;
else if(~`DTUPATH5.fcl_fdp_thr_s2_l[1])spc5_phy_pc_d <= pcf5[1] ? spc5_t1pc_s : spc5_imiss_paddr_s;
else if(~`DTUPATH5.fcl_fdp_thr_s2_l[2])spc5_phy_pc_d <= pcf5[2] ? spc5_t2pc_s : spc5_imiss_paddr_s;
else if(~`DTUPATH5.fcl_fdp_thr_s2_l[3])spc5_phy_pc_d <= pcf5[3] ? spc5_t3pc_s : spc5_imiss_paddr_s;
spc5_phy_pc_e <= spc5_phy_pc_d;
spc5_phy_pc_m <= spc5_phy_pc_e;
spc5_phy_pc_w <= {{8{spc5_phy_pc_m[39]}}, spc5_phy_pc_m[39:0]};
if(spc5_inst_done &&
active_thread[{3'b101,spc5_thread_id[1:0]}])begin
/*
if(0 & $x_checker(`DTUPATH5.pc_w))begin
$display("%0d: Detected unkown pc value spc(%d) thread(%x) value(%x)",
$time, 3'b101, spc5_thread_id[1:0], `DTUPATH5.pc_w);
`MONITOR_PATH.fail("Detected unkown pc");
end
*/
end
`endif // ifdef RTL_SPARC5
`ifdef RTL_SPARC6
//done
spc6_inst_done <= sas_m6;
//next pc select
spc6_fcl_fdp_nextpcs_sel_pcs_f_l_e <= `DTUPATH6.fcl_fdp_nextpcs_sel_pcs_f_l;
spc6_fcl_fdp_nextpcs_sel_pcf_f_l_e <= `DTUPATH6.fcl_fdp_nextpcs_sel_pcf_f_l;
spc6_fcl_fdp_nextpcs_sel_pcd_f_l_e <= `DTUPATH6.fcl_fdp_nextpcs_sel_pcd_f_l;
spc6_fcl_fdp_nextpcs_sel_pce_f_l_e <= `DTUPATH6.fcl_fdp_nextpcs_sel_pce_f_l;
//pipe physical pc
if(pcf6[0] == 0)spc6_t0pc_s <= spc6_imiss_paddr_s;
else if(pcs6[0] == 0)spc6_t0pc_s <= spc6_t0pc_s;
else if(pcd6[0] == 0)spc6_t0pc_s <= spc6_phy_pc_e;
else if(pce6[0] == 0)spc6_t0pc_s <= spc6_phy_pc_m;
if(pcf6[1] == 0)spc6_t1pc_s <= spc6_imiss_paddr_s;
else if(pcs6[1] == 0)spc6_t1pc_s <= spc6_t1pc_s;
else if(pcd6[1] == 0)spc6_t1pc_s <= spc6_phy_pc_e;
else if(pce6[1] == 0)spc6_t1pc_s <= spc6_phy_pc_m;
if(pcf6[2] == 0)spc6_t2pc_s <= spc6_imiss_paddr_s;
else if(pcs6[2] == 0)spc6_t2pc_s <= spc6_t2pc_s;
else if(pcd6[2] == 0)spc6_t2pc_s <= spc6_phy_pc_e;
else if(pce6[2] == 0)spc6_t2pc_s <= spc6_phy_pc_m;
if(pcf6[3] == 0)spc6_t3pc_s <= spc6_imiss_paddr_s;
else if(pcs6[3] == 0)spc6_t3pc_s <= spc6_t3pc_s;
else if(pcd6[3] == 0)spc6_t3pc_s <= spc6_phy_pc_e;
else if(pce6[3] == 0)spc6_t3pc_s <= spc6_phy_pc_m;
if(~`DTUPATH6.fcl_fdp_thr_s2_l[0]) spc6_phy_pc_d <= pcf6[0] ? spc6_t0pc_s : spc6_imiss_paddr_s;
else if(~`DTUPATH6.fcl_fdp_thr_s2_l[1])spc6_phy_pc_d <= pcf6[1] ? spc6_t1pc_s : spc6_imiss_paddr_s;
else if(~`DTUPATH6.fcl_fdp_thr_s2_l[2])spc6_phy_pc_d <= pcf6[2] ? spc6_t2pc_s : spc6_imiss_paddr_s;
else if(~`DTUPATH6.fcl_fdp_thr_s2_l[3])spc6_phy_pc_d <= pcf6[3] ? spc6_t3pc_s : spc6_imiss_paddr_s;
spc6_phy_pc_e <= spc6_phy_pc_d;
spc6_phy_pc_m <= spc6_phy_pc_e;
spc6_phy_pc_w <= {{8{spc6_phy_pc_m[39]}}, spc6_phy_pc_m[39:0]};
if(spc6_inst_done &&
active_thread[{3'b110,spc6_thread_id[1:0]}])begin
/*
if(0 & $x_checker(`DTUPATH6.pc_w))begin
$display("%0d: Detected unkown pc value spc(%d) thread(%x) value(%x)",
$time, 3'b110, spc6_thread_id[1:0], `DTUPATH6.pc_w);
`MONITOR_PATH.fail("Detected unkown pc");
end
*/
end
`endif // ifdef RTL_SPARC6
`ifdef RTL_SPARC7
//done
spc7_inst_done <= sas_m7;
spc7_fcl_fdp_nextpcs_sel_pcs_f_l_e <= `DTUPATH7.fcl_fdp_nextpcs_sel_pcs_f_l;
spc7_fcl_fdp_nextpcs_sel_pcf_f_l_e <= `DTUPATH7.fcl_fdp_nextpcs_sel_pcf_f_l;
spc7_fcl_fdp_nextpcs_sel_pcd_f_l_e <= `DTUPATH7.fcl_fdp_nextpcs_sel_pcd_f_l;
spc7_fcl_fdp_nextpcs_sel_pce_f_l_e <= `DTUPATH7.fcl_fdp_nextpcs_sel_pce_f_l;
//pipe physical pc
if(pcf7[0] == 0)spc7_t0pc_s <= spc7_imiss_paddr_s;
else if(pcs7[0] == 0)spc7_t0pc_s <= spc7_t0pc_s;
else if(pcd7[0] == 0)spc7_t0pc_s <= spc7_phy_pc_e;
else if(pce7[0] == 0)spc7_t0pc_s <= spc7_phy_pc_m;
if(pcf7[1] == 0)spc7_t1pc_s <= spc7_imiss_paddr_s;
else if(pcs7[1] == 0)spc7_t1pc_s <= spc7_t1pc_s;
else if(pcd7[1] == 0)spc7_t1pc_s <= spc7_phy_pc_e;
else if(pce7[1] == 0)spc7_t1pc_s <= spc7_phy_pc_m;
if(pcf7[2] == 0)spc7_t2pc_s <= spc7_imiss_paddr_s;
else if(pcs7[2] == 0)spc7_t2pc_s <= spc7_t2pc_s;
else if(pcd7[2] == 0)spc7_t2pc_s <= spc7_phy_pc_e;
else if(pce7[2] == 0)spc7_t2pc_s <= spc7_phy_pc_m;
if(pcf7[3] == 0)spc7_t3pc_s <= spc7_imiss_paddr_s;
else if(pcs7[3] == 0)spc7_t3pc_s <= spc7_t3pc_s;
else if(pcd7[3] == 0)spc7_t3pc_s <= spc7_phy_pc_e;
else if(pce7[3] == 0)spc7_t3pc_s <= spc7_phy_pc_m;
if(~`DTUPATH7.fcl_fdp_thr_s2_l[0]) spc7_phy_pc_d <= pcf7[0] ? spc7_t0pc_s : spc7_imiss_paddr_s;
else if(~`DTUPATH7.fcl_fdp_thr_s2_l[1])spc7_phy_pc_d <= pcf7[1] ? spc7_t1pc_s : spc7_imiss_paddr_s;
else if(~`DTUPATH7.fcl_fdp_thr_s2_l[2])spc7_phy_pc_d <= pcf7[2] ? spc7_t2pc_s : spc7_imiss_paddr_s;
else if(~`DTUPATH7.fcl_fdp_thr_s2_l[3])spc7_phy_pc_d <= pcf7[3] ? spc7_t3pc_s : spc7_imiss_paddr_s;
spc7_phy_pc_e <= spc7_phy_pc_d;
spc7_phy_pc_m <= spc7_phy_pc_e;
spc7_phy_pc_w <= {{8{spc7_phy_pc_m[39]}}, spc7_phy_pc_m[39:0]};
if(spc7_inst_done &&
active_thread[{3'b111,spc7_thread_id[1:0]}])begin
/*
if(0 & $x_checker(`DTUPATH7.pc_w))begin
$display("%0d: Detected unkown pc value spc(%d) thread(%x) value(%x)",
$time, 3'b111, spc7_thread_id[1:0], `DTUPATH7.pc_w);
`MONITOR_PATH.fail("Detected unkown pc");
end
*/
end
`endif // ifdef RTL_SPARC7
end
reg dummy;
task trap_extract;
reg [2048:0] pc_str;
reg [63:0] tmp_val;
integer i;
begin
bad_trap_count = 0;
finish_mask = 1;
diag_mask = 0;
stub_mask = 0;
if($value$plusargs("finish_mask=%h", finish_mask))$display ("%t: finish_mask %h", $time, finish_mask);
if($value$plusargs("good_trap=%s", pc_str)) $display ("%t: good_trap list %s", $time, pc_str);
if($value$plusargs("stub_mask=%h", stub_mask)) $display ("%t: stub_mask %h", $time, stub_mask);
for(i = 0; i < 32;i = i + 1)if(finish_mask[i] === 1'bx)finish_mask[i] = 1'b0;
if(sas_def)dummy = $bw_good_trap(1, finish_mask);
for(i = 0; i < 8;i = i + 1) if(stub_mask[i] === 1'bx)stub_mask[i] = 1'b0;
good_trap_count = 0;
while ($parse (pc_str, "%h:", tmp_val))
begin
good_trap[good_trap_count] = tmp_val;
$display ("%t: good_trap %h", $time, good_trap[good_trap_count]);
good_trap_count = good_trap_count + 1;
if (good_trap_count > `GOOD_TRAP_COUNTER)
begin
$display ("%t: good_trap_count more than max-count %d.", $time, `GOOD_TRAP_COUNTER);
`MONITOR_PATH.fail("good_trap_count more than max-count");
end
end
if($value$plusargs("bad_trap=%s", pc_str))$display ("%t: bad_trap list %s", $time, pc_str);
bad_trap_count = 0;
while ($parse (pc_str, "%h:", tmp_val))
begin
bad_trap[bad_trap_count] = tmp_val;
$display ("%t: bad_trap %h", $time, bad_trap[bad_trap_count]);
bad_trap_count = bad_trap_count + 1;
if (bad_trap_count > `GOOD_TRAP_COUNTER)
begin
$display ("%t: bad_trap_count more than max-count %d.", $time,`GOOD_TRAP_COUNTER);
`MONITOR_PATH.fail("bad_trap_count more than max-count.");
end
end // while ($parse (pc_str, "%h:", tmp_val))
trap_count = good_trap_count > bad_trap_count ? good_trap_count : bad_trap_count;
end
endtask // trap_extract
// deceide pass or fail
reg [31:0] timeout [31:0];
reg [63:0] rpc;
integer ind;
//post-silicon request
reg [63:0] last_hit [31:0];
//indicate the 2nd time hit.
reg [31:0] hitted;
initial hitted = 0;
task check_done;
input [7:0] cpu;
integer j, l;
reg [63:0]pc;
reg [4:0] i;
begin
for(i = 0; i < 8; i = i + 1)begin
if(cpu[i])begin
case(i)
0 : begin j = {i[2:0], spc0_thread_id};pc = spc0_phy_pc_w;rpc = spc0_rtl_pc;end
1 : begin j = {i[2:0], spc1_thread_id};pc = spc1_phy_pc_w;rpc = spc1_rtl_pc;end
2 : begin j = {i[2:0], spc2_thread_id};pc = spc2_phy_pc_w;rpc = spc2_rtl_pc;end
3 : begin j = {i[2:0], spc3_thread_id};pc = spc3_phy_pc_w;rpc = spc3_rtl_pc;end
4 : begin j = {i[2:0], spc4_thread_id};pc = spc4_phy_pc_w;rpc = spc4_rtl_pc;end
5 : begin j = {i[2:0], spc5_thread_id};pc = spc5_phy_pc_w;rpc = spc5_rtl_pc;end
6 : begin j = {i[2:0], spc6_thread_id};pc = spc6_phy_pc_w;rpc = spc6_rtl_pc;end
7 : begin j = {i[2:0], spc7_thread_id};pc = spc7_phy_pc_w;rpc = spc7_rtl_pc;end
endcase
timeout[j] = 0;
check_bad_trap(pc, i, j);
if(active_thread[j])begin
for(l = 0; l < good_trap_count; l = l + 1)begin
if(good_trap[l] == pc[39:0])begin
if(sas_def && (good[j] == 0))dummy = $bw_good_trap(2, j, rpc);//command thread, pc
if(good[j] == 0)$display("Info: spc(%0x) thread(%0x) Hit Good trap", j / 4, j % 4);
//post-silicon debug
if((sas_def == 0) && finish_mask[j])begin
if(good_flag)begin
if(!hitted[j])begin
last_hit[j] = pc[39:0];
hitted[j] = 1;
end
else if(last_hit[j] == pc[39:0])good[j] = 1'b1;
end
else good[j] = 1'b1;
end
if(sas_def && active_thread[j])good[j] = 1'b1;
if(sas_def && finish_mask[j])good_for[j] = 1'b1;
end
if((sas_def == 0) &&
(good == finish_mask) &&
(hit_bad == 0) &&
(stub_mask == stub_good))begin
`TOP_MOD.diag_done = 1;
@(posedge clk);
$display("%0d: Simulation -> PASS (HIT GOOD TRAP)", $time);
$finish;
end
if(sas_def && (good == active_thread))`TOP_MOD.diag_done = 1;
if(sas_def)
if($bw_good_trap(3, j) &&
(hit_bad == 0) &&
(stub_mask == stub_good))begin
`TOP_MOD.diag_done = 1;
if(`TOP_MOD.fail_flag == 1'b0)begin
repeat(2) @(posedge clk);
$display("%0d: Simulation -> PASS (HIT GOOD TRAP)", $time);
dum = $bw_sas_send(`PLI_QUIT);
$finish;
end
end
end // for (l = 0; l < good_trap_count; l = l + 1)
end // if (active_thread[j])
end // if (cpu[i])
end
end
endtask
// get done signal;
task gen_done;
begin
done[0] = spc0_inst_done;//sparc 0
done[1] = spc1_inst_done;//sparc 1
done[2] = spc2_inst_done;//sparc 2
done[3] = spc3_inst_done;//sparc 3
done[4] = spc4_inst_done;//sparc 4
done[5] = spc5_inst_done;//sparc 5
done[6] = spc6_inst_done;//sparc 6
done[7] = spc7_inst_done;//sparc 7
end
endtask // gen_done
reg first_rst;
initial begin
if($value$plusargs("TIMEOUT=%d", time_tmp))max = time_tmp;
else max = 1000;
#20//need to wait for socket initializing.
trap_extract;
done = 0;
good = 0;
active_thread = 0;
hit_bad = 0;
first_rst = 1;
for(ind = 0;ind < 32; ind = ind + 1)timeout[ind] = 0;
end // initial begin
always @(posedge rst_l)begin
if(first_rst)begin
active_thread = 0;
first_rst = 0;
done = 0;
good = 0;
hit_bad = 0;
end
end
//speed up checkeing
task check_time;
input [5:0] head;
input [5:0] tail;
integer ind;
begin
for(ind = head; ind < tail; ind = ind + 1)begin
if(timeout[ind] > max && (good[ind] == 0))begin
if((max_cycle == 0 || finish_mask[ind] == 0) && (thread_status[ind] == `THRFSM_HALT)
)begin
timeout[ind] = 0;
end
else begin
$display("Info: spc(%0d) thread(%0d) -> timeout happen", ind / 4, ind % 4);
`MONITOR_PATH.fail("TIMEOUT");
end
end
else if(active_thread[ind] != good[ind])begin
timeout[ind] = timeout[ind] + 1;
end // if (finish_mask[ind] != good[ind])
end // for (ind = head; ind < tail; ind = ind + 1)
end
endtask // check_time
//check good trap status after threads hit the good trap.
//The reason for this is that the threads stay on halt status.
task check_good;
begin
if($bw_good_trap(3, 0) && (hit_bad == 0))begin
`TOP_MOD.diag_done = 1;
if(!`TOP_MOD.fail_flag)begin
repeat(2) @(posedge clk);
$display("%0d: Simulation -> PASS (HIT GOOD TRAP)", $time);
dum = $bw_sas_send(`PLI_QUIT);
$finish;
end
end
end
endtask // check_good
//deceide whether stub done or not.
task check_stub;
reg [3:0] i;
begin
for(i = 0; i < 8; i = i + 1)begin
if(stub_mask[i] &&
`TOP_MOD.stub_done[i] &&
`TOP_MOD.stub_pass[i])stub_good[i] = 1'b1;
else if(stub_mask[i] &&
`TOP_MOD.stub_done[i] &&
`TOP_MOD.stub_pass[i] == 0)begin
$display("Info->Simulation terminated by stub.");
`MONITOR_PATH.fail("HIT BAD TRAP");
end
end
if (sas_def) begin
if(stub_mask &&
(stub_mask == stub_good) &&
(active_thread && $bw_good_trap(3, 0) ||
active_thread == 0))begin
`TOP_MOD.diag_done = 1;
@(posedge clk);
$display("Info->Simulation terminated by stub.");
$display("%0d: Simulation -> PASS (HIT GOOD TRAP)", $time);
$finish;
end
end
else if ((good == finish_mask) && (stub_mask == stub_good)) begin
`TOP_MOD.diag_done = 1;
@(posedge clk);
$display("Info->Simulation terminated by stub.");
$display("%0d: Simulation -> PASS (HIT GOOD TRAP)", $time);
$finish;
end
end
endtask // check_stub
//main routine of pc cmp to finish the simulation.
always @(posedge clk)begin
if(rst_l)begin
if(`TOP_MOD.stub_done)check_stub;
gen_done;
if(|done[7:0])check_done(done);
else if(sas_def && (good_for == finish_mask))check_good;
`ifdef INCLUDE_SAS_TASKS
get_thread_status;
`endif
if(active_thread[3:0])check_time(0, 4);
if(active_thread[7:4])check_time(4, 8);
if(active_thread[19:8])check_time(8, 20);
if(active_thread[31:20])check_time(20, 32);
end // if (rst_l)
end // always @ (posedge clk)
endmodule
|
module sky130_fd_sc_hd__bufinv (
//# {{data|Data Signals}}
input A,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
|
module side(
clka,
addra,
douta
);
input clka;
input [16 : 0] addra;
output [11 : 0] douta;
// synthesis translate_off
BLK_MEM_GEN_V7_3 #(
.C_ADDRA_WIDTH(17),
.C_ADDRB_WIDTH(17),
.C_ALGORITHM(1),
.C_AXI_ID_WIDTH(4),
.C_AXI_SLAVE_TYPE(0),
.C_AXI_TYPE(1),
.C_BYTE_SIZE(9),
.C_COMMON_CLK(0),
.C_DEFAULT_DATA("0"),
.C_DISABLE_WARN_BHV_COLL(0),
.C_DISABLE_WARN_BHV_RANGE(0),
.C_ENABLE_32BIT_ADDRESS(0),
.C_FAMILY("artix7"),
.C_HAS_AXI_ID(0),
.C_HAS_ENA(0),
.C_HAS_ENB(0),
.C_HAS_INJECTERR(0),
.C_HAS_MEM_OUTPUT_REGS_A(0),
.C_HAS_MEM_OUTPUT_REGS_B(0),
.C_HAS_MUX_OUTPUT_REGS_A(0),
.C_HAS_MUX_OUTPUT_REGS_B(0),
.C_HAS_REGCEA(0),
.C_HAS_REGCEB(0),
.C_HAS_RSTA(0),
.C_HAS_RSTB(0),
.C_HAS_SOFTECC_INPUT_REGS_A(0),
.C_HAS_SOFTECC_OUTPUT_REGS_B(0),
.C_INIT_FILE("BlankString"),
.C_INIT_FILE_NAME("side.mif"),
.C_INITA_VAL("0"),
.C_INITB_VAL("0"),
.C_INTERFACE_TYPE(0),
.C_LOAD_INIT_FILE(1),
.C_MEM_TYPE(3),
.C_MUX_PIPELINE_STAGES(0),
.C_PRIM_TYPE(1),
.C_READ_DEPTH_A(76800),
.C_READ_DEPTH_B(76800),
.C_READ_WIDTH_A(12),
.C_READ_WIDTH_B(12),
.C_RST_PRIORITY_A("CE"),
.C_RST_PRIORITY_B("CE"),
.C_RST_TYPE("SYNC"),
.C_RSTRAM_A(0),
.C_RSTRAM_B(0),
.C_SIM_COLLISION_CHECK("ALL"),
.C_USE_BRAM_BLOCK(0),
.C_USE_BYTE_WEA(0),
.C_USE_BYTE_WEB(0),
.C_USE_DEFAULT_DATA(0),
.C_USE_ECC(0),
.C_USE_SOFTECC(0),
.C_WEA_WIDTH(1),
.C_WEB_WIDTH(1),
.C_WRITE_DEPTH_A(76800),
.C_WRITE_DEPTH_B(76800),
.C_WRITE_MODE_A("WRITE_FIRST"),
.C_WRITE_MODE_B("WRITE_FIRST"),
.C_WRITE_WIDTH_A(12),
.C_WRITE_WIDTH_B(12),
.C_XDEVICEFAMILY("artix7")
)
inst (
.CLKA(clka),
.ADDRA(addra),
.DOUTA(douta),
.RSTA(),
.ENA(),
.REGCEA(),
.WEA(),
.DINA(),
.CLKB(),
.RSTB(),
.ENB(),
.REGCEB(),
.WEB(),
.ADDRB(),
.DINB(),
.DOUTB(),
.INJECTSBITERR(),
.INJECTDBITERR(),
.SBITERR(),
.DBITERR(),
.RDADDRECC(),
.S_ACLK(),
.S_ARESETN(),
.S_AXI_AWID(),
.S_AXI_AWADDR(),
.S_AXI_AWLEN(),
.S_AXI_AWSIZE(),
.S_AXI_AWBURST(),
.S_AXI_AWVALID(),
.S_AXI_AWREADY(),
.S_AXI_WDATA(),
.S_AXI_WSTRB(),
.S_AXI_WLAST(),
.S_AXI_WVALID(),
.S_AXI_WREADY(),
.S_AXI_BID(),
.S_AXI_BRESP(),
.S_AXI_BVALID(),
.S_AXI_BREADY(),
.S_AXI_ARID(),
.S_AXI_ARADDR(),
.S_AXI_ARLEN(),
.S_AXI_ARSIZE(),
.S_AXI_ARBURST(),
.S_AXI_ARVALID(),
.S_AXI_ARREADY(),
.S_AXI_RID(),
.S_AXI_RDATA(),
.S_AXI_RRESP(),
.S_AXI_RLAST(),
.S_AXI_RVALID(),
.S_AXI_RREADY(),
.S_AXI_INJECTSBITERR(),
.S_AXI_INJECTDBITERR(),
.S_AXI_SBITERR(),
.S_AXI_DBITERR(),
.S_AXI_RDADDRECC()
);
// synthesis translate_on
endmodule
|
module cdc_reset_sync (
input wire clk_in,
input wire pulse_in,
input wire clk_out,
output wire pulse_out
);
wire aq_sync;
reg [1:0] in_pre_sync;
always @(posedge clk_in) begin
in_pre_sync[0] <= pulse_in;
in_pre_sync[1] <= in_pre_sync[0];
end
reg in_sync_pulse;
initial in_sync_pulse = 0; // works only in FPGA
always @(posedge clk_in) begin
if (in_pre_sync[1])
in_sync_pulse <= 1;
else if (aq_sync)
in_sync_pulse <= 0;
end
(* ASYNC_REG = "TRUE" *) reg out_sync_ff_1;
(* ASYNC_REG = "TRUE" *) reg out_sync_ff_2;
always @(posedge clk_out) begin
out_sync_ff_1 <= in_sync_pulse;
out_sync_ff_2 <= out_sync_ff_1;
end
assign pulse_out = out_sync_ff_2;
(* ASYNC_REG = "TRUE" *) reg aq_sync_ff_1;
(* ASYNC_REG = "TRUE" *) reg aq_sync_ff_2;
always @(posedge clk_in) begin
aq_sync_ff_1 <= out_sync_ff_2;
aq_sync_ff_2 <= aq_sync_ff_1;
end
assign aq_sync = aq_sync_ff_2;
endmodule
|
module tb_m6502_alu;
reg [7 : 0] tb_operation;
reg [7 : 0] tb_op_a;
reg [7 : 0] tb_op_b;
reg tb_carry_in;
wire [7 : 0] tb_result;
wire tb_carry;
wire tb_zero;
wire tb_overflow;
reg [31 : 0] error_ctr;
reg [31 : 0] tc_ctr;
//----------------------------------------------------------------
// dut
//----------------------------------------------------------------
m6502_alu dut(
.operation(tb_operation),
.op_a(tb_op_a),
.op_b(tb_op_b),
.carry_in(tb_carry_in),
.result(tb_result),
.carry(tb_carry),
.zero(tb_zero),
.overflow(tb_overflow)
);
//----------------------------------------------------------------
// display_test_results()
//
// Display the accumulated test results.
//----------------------------------------------------------------
task display_test_results;
begin
if (error_ctr == 0)
begin
$display("*** All %02d test cases completed successfully", tc_ctr);
end
else
begin
$display("*** %02d tests completed - %02d test cases did not complete successfully.",
tc_ctr, error_ctr);
end
end
endtask // display_test_results
//----------------------------------------------------------------
// init_sim()
//----------------------------------------------------------------
task init_sim;
begin
tc_ctr = 0;
error_ctr = 0;
tb_operation = 8'h0;
tb_op_a = 8'h0;
tb_op_b = 8'h0;
tb_carry_in = 0;
end
endtask // init_sim
//----------------------------------------------------------------
// main
//----------------------------------------------------------------
initial
begin : main
$display(" -= Testbench for m6502 ALU started =-");
$display(" ====================================");
$display("");
init_sim();
display_test_results();
$display("");
$display("*** m6502 ALU simulation done. ***");
$finish;
end // main
endmodule
|
module cf_dac_if (
// dac interface
dac_clk_in_p,
dac_clk_in_n,
dac_clk_out_p,
dac_clk_out_n,
dac_data_out_a_p,
dac_data_out_a_n,
dac_data_out_b_p,
dac_data_out_b_n,
// internal interface, a low speed dac clock is used by the internal logic
// sample 0 is transmitted first
dac_div3_clk,
dds_data_00,
dds_data_01,
dds_data_02,
dds_data_03,
dds_data_04,
dds_data_05,
dds_data_06,
dds_data_07,
dds_data_08,
dds_data_09,
dds_data_10,
dds_data_11,
// processor signals
up_dds_enable);
// dac interface
input dac_clk_in_p;
input dac_clk_in_n;
output dac_clk_out_p;
output dac_clk_out_n;
output [13:0] dac_data_out_a_p;
output [13:0] dac_data_out_a_n;
output [13:0] dac_data_out_b_p;
output [13:0] dac_data_out_b_n;
// internal interface, a low speed dac clock is used by the internal logic
// sample 0 is transmitted first
output dac_div3_clk;
input [13:0] dds_data_00;
input [13:0] dds_data_01;
input [13:0] dds_data_02;
input [13:0] dds_data_03;
input [13:0] dds_data_04;
input [13:0] dds_data_05;
input [13:0] dds_data_06;
input [13:0] dds_data_07;
input [13:0] dds_data_08;
input [13:0] dds_data_09;
input [13:0] dds_data_10;
input [13:0] dds_data_11;
// processor signals
input up_dds_enable;
reg [ 5:0] dds_data_a[13:0];
reg [ 5:0] dds_data_b[13:0];
wire dac_clk_in_s;
wire dac_clk_out_s;
wire [13:0] dac_data_out_a_s;
wire [13:0] dac_data_out_b_s;
wire serdes_clk_preset_s;
wire serdes_clk_rst_s;
wire serdes_preset_s;
wire serdes_rst_s;
wire dac_clk;
wire dac_div3_clk_s;
// The OSERDES modules drive data bit-wise. That is, samples are first need to be
// bit selected, then passed to the OSERDES. The same for parity.
always @(posedge dac_div3_clk) begin
dds_data_a[13] <= {dds_data_10[13], dds_data_08[13], dds_data_06[13],
dds_data_04[13], dds_data_02[13], dds_data_00[13]};
dds_data_a[12] <= {dds_data_10[12], dds_data_08[12], dds_data_06[12],
dds_data_04[12], dds_data_02[12], dds_data_00[12]};
dds_data_a[11] <= {dds_data_10[11], dds_data_08[11], dds_data_06[11],
dds_data_04[11], dds_data_02[11], dds_data_00[11]};
dds_data_a[10] <= {dds_data_10[10], dds_data_08[10], dds_data_06[10],
dds_data_04[10], dds_data_02[10], dds_data_00[10]};
dds_data_a[ 9] <= {dds_data_10[ 9], dds_data_08[ 9], dds_data_06[ 9],
dds_data_04[ 9], dds_data_02[ 9], dds_data_00[ 9]};
dds_data_a[ 8] <= {dds_data_10[ 8], dds_data_08[ 8], dds_data_06[ 8],
dds_data_04[ 8], dds_data_02[ 8], dds_data_00[ 8]};
dds_data_a[ 7] <= {dds_data_10[ 7], dds_data_08[ 7], dds_data_06[ 7],
dds_data_04[ 7], dds_data_02[ 7], dds_data_00[ 7]};
dds_data_a[ 6] <= {dds_data_10[ 6], dds_data_08[ 6], dds_data_06[ 6],
dds_data_04[ 6], dds_data_02[ 6], dds_data_00[ 6]};
dds_data_a[ 5] <= {dds_data_10[ 5], dds_data_08[ 5], dds_data_06[ 5],
dds_data_04[ 5], dds_data_02[ 5], dds_data_00[ 5]};
dds_data_a[ 4] <= {dds_data_10[ 4], dds_data_08[ 4], dds_data_06[ 4],
dds_data_04[ 4], dds_data_02[ 4], dds_data_00[ 4]};
dds_data_a[ 3] <= {dds_data_10[ 3], dds_data_08[ 3], dds_data_06[ 3],
dds_data_04[ 3], dds_data_02[ 3], dds_data_00[ 3]};
dds_data_a[ 2] <= {dds_data_10[ 2], dds_data_08[ 2], dds_data_06[ 2],
dds_data_04[ 2], dds_data_02[ 2], dds_data_00[ 2]};
dds_data_a[ 1] <= {dds_data_10[ 1], dds_data_08[ 1], dds_data_06[ 1],
dds_data_04[ 1], dds_data_02[ 1], dds_data_00[ 1]};
dds_data_a[ 0] <= {dds_data_10[ 0], dds_data_08[ 0], dds_data_06[ 0],
dds_data_04[ 0], dds_data_02[ 0], dds_data_00[ 0]};
dds_data_b[13] <= {dds_data_11[13], dds_data_09[13], dds_data_07[13],
dds_data_05[13], dds_data_03[13], dds_data_01[13]};
dds_data_b[12] <= {dds_data_11[12], dds_data_09[12], dds_data_07[12],
dds_data_05[12], dds_data_03[12], dds_data_01[12]};
dds_data_b[11] <= {dds_data_11[11], dds_data_09[11], dds_data_07[11],
dds_data_05[11], dds_data_03[11], dds_data_01[11]};
dds_data_b[10] <= {dds_data_11[10], dds_data_09[10], dds_data_07[10],
dds_data_05[10], dds_data_03[10], dds_data_01[10]};
dds_data_b[ 9] <= {dds_data_11[ 9], dds_data_09[ 9], dds_data_07[ 9],
dds_data_05[ 9], dds_data_03[ 9], dds_data_01[ 9]};
dds_data_b[ 8] <= {dds_data_11[ 8], dds_data_09[ 8], dds_data_07[ 8],
dds_data_05[ 8], dds_data_03[ 8], dds_data_01[ 8]};
dds_data_b[ 7] <= {dds_data_11[ 7], dds_data_09[ 7], dds_data_07[ 7],
dds_data_05[ 7], dds_data_03[ 7], dds_data_01[ 7]};
dds_data_b[ 6] <= {dds_data_11[ 6], dds_data_09[ 6], dds_data_07[ 6],
dds_data_05[ 6], dds_data_03[ 6], dds_data_01[ 6]};
dds_data_b[ 5] <= {dds_data_11[ 5], dds_data_09[ 5], dds_data_07[ 5],
dds_data_05[ 5], dds_data_03[ 5], dds_data_01[ 5]};
dds_data_b[ 4] <= {dds_data_11[ 4], dds_data_09[ 4], dds_data_07[ 4],
dds_data_05[ 4], dds_data_03[ 4], dds_data_01[ 4]};
dds_data_b[ 3] <= {dds_data_11[ 3], dds_data_09[ 3], dds_data_07[ 3],
dds_data_05[ 3], dds_data_03[ 3], dds_data_01[ 3]};
dds_data_b[ 2] <= {dds_data_11[ 2], dds_data_09[ 2], dds_data_07[ 2],
dds_data_05[ 2], dds_data_03[ 2], dds_data_01[ 2]};
dds_data_b[ 1] <= {dds_data_11[ 1], dds_data_09[ 1], dds_data_07[ 1],
dds_data_05[ 1], dds_data_03[ 1], dds_data_01[ 1]};
dds_data_b[ 0] <= {dds_data_11[ 0], dds_data_09[ 0], dds_data_07[ 0],
dds_data_05[ 0], dds_data_03[ 0], dds_data_01[ 0]};
end
// The resets for SERDES data/clock are separately controlled.
// They are held in reset until software enabled.
assign serdes_clk_preset_s = 1'b0;
FDPE #(.INIT(1'b1)) i_serdes_clk_rst_reg (
.CE (1'b1),
.D (1'b0),
.PRE (serdes_clk_preset_s),
.C (dac_div3_clk),
.Q (serdes_clk_rst_s));
assign serdes_preset_s = ~up_dds_enable;
FDPE #(.INIT(1'b1)) i_serdes_rst_reg (
.CE (1'b1),
.D (1'b0),
.PRE (serdes_preset_s),
.C (dac_div3_clk),
.Q (serdes_rst_s));
// dac data output serdes(s) & buffers
// The SERDES is used here to get the lowest clock possible for the internal logic.
// Since Xilinx SERDES is 3:1 DDR, this clock is DAC-CLK/3. This may seem a bit
// challenging (being an odd number as divider) to generate samples. It is possible
// to lower the DAC clock and reduce the OSERDES to be 2:1 or even 1:1. If further
// reductions are required, it is recommended NOT to use master/slave OSERDES
// configuration (as this combination is very sensitive to the output and divided
// clocks). You can lower the clocks at the single OSERDES's divided clock.
genvar l_inst;
generate
for (l_inst = 0; l_inst <= 13; l_inst = l_inst + 1) begin: g_dac_data
OSERDESE1 #(
.DATA_RATE_OQ ("DDR"),
.DATA_RATE_TQ ("SDR"),
.DATA_WIDTH (6),
.INTERFACE_TYPE ("DEFAULT"),
.TRISTATE_WIDTH (1),
.SERDES_MODE ("MASTER"))
i_dac_data_out_a_oserdes (
.D1 (dds_data_a[l_inst][0]),
.D2 (dds_data_a[l_inst][1]),
.D3 (dds_data_a[l_inst][2]),
.D4 (dds_data_a[l_inst][3]),
.D5 (dds_data_a[l_inst][4]),
.D6 (dds_data_a[l_inst][5]),
.T1 (1'b0),
.T2 (1'b0),
.T3 (1'b0),
.T4 (1'b0),
.SHIFTIN1 (1'b0),
.SHIFTIN2 (1'b0),
.SHIFTOUT1 (),
.SHIFTOUT2 (),
.OCE (1'b1),
.CLK (dac_clk),
.CLKDIV (dac_div3_clk),
.CLKPERF (1'b0),
.CLKPERFDELAY (1'b0),
.WC (1'b0),
.ODV (1'b0),
.OQ (dac_data_out_a_s[l_inst]),
.TQ (),
.OCBEXTEND (),
.OFB (),
.TFB (),
.TCE (1'b0),
.RST (serdes_rst_s));
OBUFDS i_dac_data_out_a_buf (
.I (dac_data_out_a_s[l_inst]),
.O (dac_data_out_a_p[l_inst]),
.OB (dac_data_out_a_n[l_inst]));
OSERDESE1 #(
.DATA_RATE_OQ ("DDR"),
.DATA_RATE_TQ ("SDR"),
.DATA_WIDTH (6),
.INTERFACE_TYPE ("DEFAULT"),
.TRISTATE_WIDTH (1),
.SERDES_MODE ("MASTER"))
i_dac_data_out_b_oserdes (
.D1 (dds_data_b[l_inst][0]),
.D2 (dds_data_b[l_inst][1]),
.D3 (dds_data_b[l_inst][2]),
.D4 (dds_data_b[l_inst][3]),
.D5 (dds_data_b[l_inst][4]),
.D6 (dds_data_b[l_inst][5]),
.T1 (1'b0),
.T2 (1'b0),
.T3 (1'b0),
.T4 (1'b0),
.SHIFTIN1 (1'b0),
.SHIFTIN2 (1'b0),
.SHIFTOUT1 (),
.SHIFTOUT2 (),
.OCE (1'b1),
.CLK (dac_clk),
.CLKDIV (dac_div3_clk),
.CLKPERF (1'b0),
.CLKPERFDELAY (1'b0),
.WC (1'b0),
.ODV (1'b0),
.OQ (dac_data_out_b_s[l_inst]),
.TQ (),
.OCBEXTEND (),
.OFB (),
.TFB (),
.TCE (1'b0),
.RST (serdes_rst_s));
OBUFDS i_dac_data_out_b_buf (
.I (dac_data_out_b_s[l_inst]),
.O (dac_data_out_b_p[l_inst]),
.OB (dac_data_out_b_n[l_inst]));
end
endgenerate
// dac clock output serdes & buffer
OSERDESE1 #(
.DATA_RATE_OQ ("DDR"),
.DATA_RATE_TQ ("SDR"),
.DATA_WIDTH (6),
.INTERFACE_TYPE ("DEFAULT"),
.TRISTATE_WIDTH (1),
.SERDES_MODE ("MASTER"))
i_dac_clk_out_oserdes (
.D1 (1'b0),
.D2 (1'b1),
.D3 (1'b0),
.D4 (1'b1),
.D5 (1'b0),
.D6 (1'b1),
.T1 (1'b0),
.T2 (1'b0),
.T3 (1'b0),
.T4 (1'b0),
.SHIFTIN1 (1'b0),
.SHIFTIN2 (1'b0),
.SHIFTOUT1 (),
.SHIFTOUT2 (),
.OCE (1'b1),
.CLK (dac_clk),
.CLKDIV (dac_div3_clk),
.CLKPERF (1'b0),
.CLKPERFDELAY (1'b0),
.WC (1'b0),
.ODV (1'b0),
.OQ (dac_clk_out_s),
.TQ (),
.OCBEXTEND (),
.OFB (),
.TFB (),
.TCE (1'b0),
.RST (serdes_clk_rst_s));
OBUFDS i_dac_clk_out_obuf (
.I (dac_clk_out_s),
.O (dac_clk_out_p),
.OB (dac_clk_out_n));
// dac clock input buffers (can't use MMCM or BUFIO due to pin placements).
// It may be possible to use BUFIO/BUFR on some carriers (where the GCLK and
// data are on the same banks.
IBUFGDS i_dac_clk_in_ibuf (
.I (dac_clk_in_p),
.IB (dac_clk_in_n),
.O (dac_clk_in_s));
BUFG i_dac_clk_in_gbuf (
.I (dac_clk_in_s),
.O (dac_clk));
BUFR #(.BUFR_DIVIDE("3")) i_dac_div3_clk_rbuf (
.CLR (1'b0),
.CE (1'b1),
.I (dac_clk),
.O (dac_div3_clk_s));
BUFG i_dac_div3_clk_gbuf (
.I (dac_div3_clk_s),
.O (dac_div3_clk));
endmodule
|
module ram_controller_phy_alt_mem_phy_pll (
areset,
inclk0,
phasecounterselect,
phasestep,
phaseupdown,
scanclk,
c0,
c1,
c2,
c3,
c4,
locked,
phasedone);
input areset;
input inclk0;
input [2:0] phasecounterselect;
input phasestep;
input phaseupdown;
input scanclk;
output c0;
output c1;
output c2;
output c3;
output c4;
output locked;
output phasedone;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 areset;
tri0 [2:0] phasecounterselect;
tri0 phasestep;
tri0 phaseupdown;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [4:0] sub_wire0;
wire sub_wire6;
wire sub_wire7;
wire [0:0] sub_wire10 = 1'h0;
wire [4:4] sub_wire5 = sub_wire0[4:4];
wire [3:3] sub_wire4 = sub_wire0[3:3];
wire [2:2] sub_wire3 = sub_wire0[2:2];
wire [1:1] sub_wire2 = sub_wire0[1:1];
wire [0:0] sub_wire1 = sub_wire0[0:0];
wire c0 = sub_wire1;
wire c1 = sub_wire2;
wire c2 = sub_wire3;
wire c3 = sub_wire4;
wire c4 = sub_wire5;
wire locked = sub_wire6;
wire phasedone = sub_wire7;
wire sub_wire8 = inclk0;
wire [1:0] sub_wire9 = {sub_wire10, sub_wire8};
altpll altpll_component (
.areset (areset),
.inclk (sub_wire9),
.phasecounterselect (phasecounterselect),
.phasestep (phasestep),
.phaseupdown (phaseupdown),
.scanclk (scanclk),
.clk (sub_wire0),
.locked (sub_wire6),
.phasedone (sub_wire7),
.activeclock (),
.clkbad (),
.clkena ({6{1'b1}}),
.clkloss (),
.clkswitch (1'b0),
.configupdate (1'b0),
.enable0 (),
.enable1 (),
.extclk (),
.extclkena ({4{1'b1}}),
.fbin (1'b1),
.fbmimicbidir (),
.fbout (),
.fref (),
.icdrclk (),
.pfdena (1'b1),
.pllena (1'b1),
.scanaclr (1'b0),
.scanclkena (1'b1),
.scandata (1'b0),
.scandataout (),
.scandone (),
.scanread (1'b0),
.scanwrite (1'b0),
.sclkout0 (),
.sclkout1 (),
.vcooverrange (),
.vcounderrange ());
defparam
altpll_component.bandwidth_type = "AUTO",
altpll_component.clk0_divide_by = 100,
altpll_component.clk0_duty_cycle = 50,
altpll_component.clk0_multiply_by = 133,
altpll_component.clk0_phase_shift = "0",
altpll_component.clk1_divide_by = 50,
altpll_component.clk1_duty_cycle = 50,
altpll_component.clk1_multiply_by = 133,
altpll_component.clk1_phase_shift = "0",
altpll_component.clk2_divide_by = 50,
altpll_component.clk2_duty_cycle = 50,
altpll_component.clk2_multiply_by = 133,
altpll_component.clk2_phase_shift = "-1880",
altpll_component.clk3_divide_by = 50,
altpll_component.clk3_duty_cycle = 50,
altpll_component.clk3_multiply_by = 133,
altpll_component.clk3_phase_shift = "0",
altpll_component.clk4_divide_by = 50,
altpll_component.clk4_duty_cycle = 50,
altpll_component.clk4_multiply_by = 133,
altpll_component.clk4_phase_shift = "0",
altpll_component.compensate_clock = "CLK1",
altpll_component.inclk0_input_frequency = 20000,
altpll_component.intended_device_family = "Cyclone IV E",
altpll_component.lpm_type = "altpll",
altpll_component.operation_mode = "NORMAL",
altpll_component.pll_type = "AUTO",
altpll_component.port_activeclock = "PORT_UNUSED",
altpll_component.port_areset = "PORT_USED",
altpll_component.port_clkbad0 = "PORT_UNUSED",
altpll_component.port_clkbad1 = "PORT_UNUSED",
altpll_component.port_clkloss = "PORT_UNUSED",
altpll_component.port_clkswitch = "PORT_UNUSED",
altpll_component.port_configupdate = "PORT_UNUSED",
altpll_component.port_fbin = "PORT_UNUSED",
altpll_component.port_inclk0 = "PORT_USED",
altpll_component.port_inclk1 = "PORT_UNUSED",
altpll_component.port_locked = "PORT_USED",
altpll_component.port_pfdena = "PORT_UNUSED",
altpll_component.port_phasecounterselect = "PORT_USED",
altpll_component.port_phasedone = "PORT_USED",
altpll_component.port_phasestep = "PORT_USED",
altpll_component.port_phaseupdown = "PORT_USED",
altpll_component.port_pllena = "PORT_UNUSED",
altpll_component.port_scanaclr = "PORT_UNUSED",
altpll_component.port_scanclk = "PORT_USED",
altpll_component.port_scanclkena = "PORT_UNUSED",
altpll_component.port_scandata = "PORT_UNUSED",
altpll_component.port_scandataout = "PORT_UNUSED",
altpll_component.port_scandone = "PORT_UNUSED",
altpll_component.port_scanread = "PORT_UNUSED",
altpll_component.port_scanwrite = "PORT_UNUSED",
altpll_component.port_clk0 = "PORT_USED",
altpll_component.port_clk1 = "PORT_USED",
altpll_component.port_clk2 = "PORT_USED",
altpll_component.port_clk3 = "PORT_USED",
altpll_component.port_clk4 = "PORT_USED",
altpll_component.port_clk5 = "PORT_UNUSED",
altpll_component.port_clkena0 = "PORT_UNUSED",
altpll_component.port_clkena1 = "PORT_UNUSED",
altpll_component.port_clkena2 = "PORT_UNUSED",
altpll_component.port_clkena3 = "PORT_UNUSED",
altpll_component.port_clkena4 = "PORT_UNUSED",
altpll_component.port_clkena5 = "PORT_UNUSED",
altpll_component.port_extclk0 = "PORT_UNUSED",
altpll_component.port_extclk1 = "PORT_UNUSED",
altpll_component.port_extclk2 = "PORT_UNUSED",
altpll_component.port_extclk3 = "PORT_UNUSED",
altpll_component.self_reset_on_loss_lock = "OFF",
altpll_component.vco_frequency_control = "MANUAL_PHASE",
altpll_component.vco_phase_shift_step = 117,
altpll_component.width_clock = 5,
altpll_component.width_phasecounterselect = 3;
endmodule
|
module address(
input CLK,
input [15:0] featurebits, // peripheral enable/disable
input [2:0] MAPPER, // MCU detected mapper
input [23:0] SNES_ADDR_early, // requested address from SNES
input SNES_WRITE_early,
input [7:0] SNES_PA, // peripheral address from SNES
input SNES_ROMSEL, // ROMSEL from SNES
output [23:0] ROM_ADDR, // Address to request from SRAM0
output ROM_HIT, // enable SRAM0
output IS_SAVERAM, // address/CS mapped as SRAM?
output IS_ROM, // address mapped as ROM?
output IS_WRITABLE, // address somehow mapped as writable area?
output IS_PATCH, // linear address map (C0-FF, Ex/Fx)
input [7:0] SAVERAM_BASE,
input [23:0] SAVERAM_MASK,
input [23:0] ROM_MASK,
input map_unlock,
input map_Ex_rd_unlock,
input map_Ex_wr_unlock,
input map_Fx_rd_unlock,
input map_Fx_wr_unlock,
input snescmd_unlock,
output msu_enable,
output dma_enable,
output srtc_enable,
output use_bsx,
output bsx_tristate,
input [14:0] bsx_regs,
output r213f_enable,
output r2100_hit,
output snescmd_enable,
output nmicmd_enable,
output return_vector_enable,
output branch1_enable,
output branch2_enable,
output branch3_enable,
output exe_enable,
output map_enable,
input [8:0] bs_page_offset,
input [9:0] bs_page,
input bs_page_enable
);
/* feature bits. see src/fpga_spi.c for mapping */
parameter [3:0]
FEAT_SRTC = 2,
FEAT_MSU1 = 3,
FEAT_213F = 4,
FEAT_SNESUNLOCK = 5,
FEAT_2100 = 6,
FEAT_DMA1 = 11
;
integer i;
reg [7:0] MAPPER_DEC; always @(posedge CLK) for (i = 0; i < 8; i = i + 1) MAPPER_DEC[i] <= (MAPPER == i);
reg [23:0] SNES_ADDR; always @(posedge CLK) SNES_ADDR <= SNES_ADDR_early;
wire [23:0] SRAM_SNES_ADDR;
wire [23:0] SAVERAM_ADDR = {4'hE,1'b0,SAVERAM_BASE,11'h0};
/* currently supported mappers:
Index Mapper
000 HiROM
001 LoROM
010 ExHiROM (48-64Mbit)
011 BS-X
110 brainfuck interleaved 96MBit Star Ocean =)
111 menu (ROM in upper SRAM)
*/
/* HiROM: SRAM @ Bank 0x30-0x3f, 0xb0-0xbf
Offset 6000-7fff */
assign IS_ROM = ~SNES_ROMSEL;
// Calculate pre IS_SAVERAM to relax timing. Uses
// early SNES_ADDR from main.
assign IS_SAVERAM_pre = (~map_unlock & SAVERAM_MASK[0])
&((MAPPER_DEC[3'b000]
|| MAPPER_DEC[3'b010]
|| MAPPER_DEC[3'b110])
? (!SNES_ADDR_early[22]
& SNES_ADDR_early[21]
& &SNES_ADDR_early[14:13]
& !SNES_ADDR_early[15]
)
/* LoROM: SRAM @ Bank 0x70-0x7d, 0xf0-0xff
* Offset 0000-7fff for ROM >= 32 MBit, otherwise 0000-ffff */
:(MAPPER_DEC[3'b001])
? (&SNES_ADDR_early[22:20]
& (~SNES_ROMSEL)
& (~SNES_ADDR_early[15] | ~ROM_MASK[21])
)
/* BS-X: SRAM @ Bank 0x10-0x17 Offset 5000-5fff */
:(MAPPER_DEC[3'b011])
? ((SNES_ADDR_early[23:19] == 5'b00010)
& (SNES_ADDR_early[15:12] == 4'b0101)
)
/* Menu mapper: 8Mbit "SRAM" @ Bank 0xf0-0xff (entire banks!) */
:(MAPPER_DEC[3'b111])
? (&SNES_ADDR_early[23:20])
: 1'b0);
reg IS_SAVERAM_r; always @(posedge CLK) IS_SAVERAM_r <= IS_SAVERAM_pre;
assign IS_SAVERAM = IS_SAVERAM_r;
// give the patch free reign over $F0-$FF banks
// map_unlock: F0-FF
// map_Ex: E0-EF
// map_Fx: F0-FF
// snescmd_unlock: C0-FF
assign IS_PATCH = ( (map_unlock
| (map_Fx_rd_unlock & SNES_WRITE_early)
| (map_Fx_wr_unlock & ~SNES_WRITE_early)
) & (&SNES_ADDR[23:20])
)
| ( ((map_Ex_rd_unlock & SNES_WRITE_early)
|(map_Ex_wr_unlock & ~SNES_WRITE_early)
) & ({SNES_ADDR[23:20]} == 4'hE)
)
| (snescmd_unlock & &SNES_ADDR[23:22]); // full access to C0-FF
/* BS-X has 4 MBits of extra RAM that can be mapped to various places */
// LoROM: A23 = r03/r04 A22 = r06 A21 = r05 A20 = 0 A19 = d/c
// HiROM: A23 = r03/r04 A22 = d/c A21 = r06 A20 = r05 A19 = 0
wire [2:0] BSX_PSRAM_BANK = {bsx_regs[6], bsx_regs[5], 1'b0};
wire [2:0] SNES_PSRAM_BANK = bsx_regs[2] ? SNES_ADDR[21:19] : SNES_ADDR[22:20];
wire BSX_PSRAM_LOHI = (bsx_regs[3] & ~SNES_ADDR[23]) | (bsx_regs[4] & SNES_ADDR[23]);
reg BSX_IS_PSRAMr;
wire BSX_IS_PSRAM = BSX_IS_PSRAMr;
always @(posedge CLK) begin
BSX_IS_PSRAMr <= BSX_PSRAM_LOHI
& (( IS_ROM & (SNES_PSRAM_BANK == BSX_PSRAM_BANK)
&(SNES_ADDR[15] | bsx_regs[2])
&(~(SNES_ADDR[19] & bsx_regs[2])))
| (bsx_regs[2]
? (SNES_ADDR[22:21] == 2'b01 & SNES_ADDR[15:13] == 3'b011)
: (~SNES_ROMSEL & &SNES_ADDR[22:20] & ~SNES_ADDR[15]))
);
end
wire BSX_IS_CARTROM = ((bsx_regs[7] & (SNES_ADDR[23:22] == 2'b00))
|(bsx_regs[8] & (SNES_ADDR[23:22] == 2'b10)))
& SNES_ADDR[15];
wire BSX_HOLE_LOHI = (bsx_regs[9] & ~SNES_ADDR[23]) | (bsx_regs[10] & SNES_ADDR[23]);
wire BSX_IS_HOLE = BSX_HOLE_LOHI
& (bsx_regs[2] ? (SNES_ADDR[21:20] == {bsx_regs[11], 1'b0})
: (SNES_ADDR[22:21] == {bsx_regs[11], 1'b0}));
assign bsx_tristate = (MAPPER_DEC[3'b011]) & ~BSX_IS_CARTROM & ~BSX_IS_PSRAM & BSX_IS_HOLE;
assign IS_WRITABLE = IS_SAVERAM
|IS_PATCH // allow writing of the patch region
|((MAPPER_DEC[3'b011]) & BSX_IS_PSRAM);
wire [23:0] BSX_ADDR = bsx_regs[2] ? {1'b0, SNES_ADDR[22:0]}
: {2'b00, SNES_ADDR[22:16], SNES_ADDR[14:0]};
assign SRAM_SNES_ADDR = IS_PATCH
? SNES_ADDR
: ((MAPPER_DEC[3'b000])
?(IS_SAVERAM
? SAVERAM_ADDR + ({SNES_ADDR[20:16], SNES_ADDR[12:0]}
& SAVERAM_MASK)
: ({1'b0, SNES_ADDR[22:0]} & ROM_MASK))
:(MAPPER_DEC[3'b001])
?(IS_SAVERAM
? SAVERAM_ADDR + ({SNES_ADDR[20:16], SNES_ADDR[14:0]}
& SAVERAM_MASK)
: ({1'b0, ~SNES_ADDR[23], SNES_ADDR[22:16], SNES_ADDR[14:0]}
& ROM_MASK))
:(MAPPER_DEC[3'b010])
?(IS_SAVERAM
? SAVERAM_ADDR + ({SNES_ADDR[20:16], SNES_ADDR[12:0]}
& SAVERAM_MASK)
: ({1'b0, !SNES_ADDR[23], SNES_ADDR[21:0]}
& ROM_MASK))
:(MAPPER_DEC[3'b011])
?( IS_SAVERAM
? SAVERAM_ADDR + {SNES_ADDR[18:16], SNES_ADDR[11:0]}
: BSX_IS_CARTROM
? (24'h800000 + ({SNES_ADDR[22:16], SNES_ADDR[14:0]} & 24'h0fffff))
: BSX_IS_PSRAM
? (24'h400000 + (BSX_ADDR & 24'h07FFFF))
: bs_page_enable
? (24'h900000 + {bs_page,bs_page_offset})
: (BSX_ADDR & 24'h0fffff)
)
:(MAPPER_DEC[3'b110])
?(IS_SAVERAM
? SAVERAM_ADDR + ((SNES_ADDR[14:0] - 15'h6000)
& SAVERAM_MASK)
:(SNES_ADDR[15]
?({1'b0, SNES_ADDR[23:16], SNES_ADDR[14:0]})
:({2'b10,
SNES_ADDR[23],
SNES_ADDR[21:16],
SNES_ADDR[14:0]}
)
)
)
:(MAPPER_DEC[3'b111])
?(IS_SAVERAM
? SNES_ADDR
: (({1'b0, SNES_ADDR[22:0]} & ROM_MASK)
+ 24'hC00000)
)
: 24'b0);
assign ROM_ADDR = SRAM_SNES_ADDR;
assign ROM_HIT = IS_ROM | IS_WRITABLE | bs_page_enable;
assign msu_enable = featurebits[FEAT_MSU1] & (!SNES_ADDR[22] && ((SNES_ADDR[15:0] & 16'hfff8) == 16'h2000));
assign dma_enable = (featurebits[FEAT_DMA1] | map_unlock | snescmd_unlock) & (!SNES_ADDR[22] && ((SNES_ADDR[15:0] & 16'hfff0) == 16'h2020));
assign use_bsx = (MAPPER_DEC[3'b011]);
assign srtc_enable = featurebits[FEAT_SRTC] & (!SNES_ADDR[22] && ((SNES_ADDR[15:0] & 16'hfffe) == 16'h2800));
assign exe_enable = (!SNES_ADDR[22] && ((SNES_ADDR[15:0] & 16'hffff) == 16'h2C00));
assign map_enable = (!SNES_ADDR[22] && ((SNES_ADDR[15:0] & 16'hffff) == 16'h2BB2));
assign r213f_enable = featurebits[FEAT_213F] & (SNES_PA == 8'h3f);
assign r2100_hit = (SNES_PA == 8'h00);
// snescmd covers $2A00-$2FFF. This overlaps with at least one hardware cheat device address range.
assign snescmd_enable = ({SNES_ADDR[22], SNES_ADDR[15:11]} == 6'b0_00101) && (SNES_ADDR[10:9] != 2'b00);
assign nmicmd_enable = (SNES_ADDR == 24'h002BF2);
assign return_vector_enable = (SNES_ADDR == 24'h002A6C);
assign branch1_enable = (SNES_ADDR == 24'h002A1F);
assign branch2_enable = (SNES_ADDR == 24'h002A59);
assign branch3_enable = (SNES_ADDR == 24'h002A5E);
endmodule
|
module tx_engine_ultrascale
#(
parameter C_PCI_DATA_WIDTH = 128,
parameter C_PIPELINE_INPUT = 1,
parameter C_PIPELINE_OUTPUT = 0,
parameter C_MAX_PAYLOAD_DWORDS = 64
)
(
// Interface: Clocks
input CLK,
// Interface: Resets
input RST_IN,
// Interface: Configuration
input [`SIG_CPLID_W-1:0] CONFIG_COMPLETER_ID,
// Interface: CC
input S_AXIS_CC_TREADY,
output S_AXIS_CC_TVALID,
output S_AXIS_CC_TLAST,
output [C_PCI_DATA_WIDTH-1:0] S_AXIS_CC_TDATA,
output [(C_PCI_DATA_WIDTH/32)-1:0] S_AXIS_CC_TKEEP,
output [`SIG_CC_TUSER_W-1:0] S_AXIS_CC_TUSER,
// Interface: TXC Engine
input TXC_DATA_VALID,
input [C_PCI_DATA_WIDTH-1:0] TXC_DATA,
input TXC_DATA_START_FLAG,
input [clog2s(C_PCI_DATA_WIDTH/32)-1:0] TXC_DATA_START_OFFSET,
input TXC_DATA_END_FLAG,
input [clog2s(C_PCI_DATA_WIDTH/32)-1:0] TXC_DATA_END_OFFSET,
output TXC_DATA_READY,
input TXC_META_VALID,
input [`SIG_FBE_W-1:0] TXC_META_FDWBE,
input [`SIG_LBE_W-1:0] TXC_META_LDWBE,
input [`SIG_LOWADDR_W-1:0] TXC_META_ADDR,
input [`SIG_TYPE_W-1:0] TXC_META_TYPE,
input [`SIG_LEN_W-1:0] TXC_META_LENGTH,
input [`SIG_BYTECNT_W-1:0] TXC_META_BYTE_COUNT,
input [`SIG_TAG_W-1:0] TXC_META_TAG,
input [`SIG_REQID_W-1:0] TXC_META_REQUESTER_ID,
input [`SIG_TC_W-1:0] TXC_META_TC,
input [`SIG_ATTR_W-1:0] TXC_META_ATTR,
input TXC_META_EP,
output TXC_META_READY,
output TXC_SENT,
// Interface: RQ
input S_AXIS_RQ_TREADY,
output S_AXIS_RQ_TVALID,
output S_AXIS_RQ_TLAST,
output [C_PCI_DATA_WIDTH-1:0] S_AXIS_RQ_TDATA,
output [(C_PCI_DATA_WIDTH/32)-1:0] S_AXIS_RQ_TKEEP,
output [`SIG_RQ_TUSER_W-1:0] S_AXIS_RQ_TUSER,
// Interface: TXR Engine
input TXR_DATA_VALID,
input [C_PCI_DATA_WIDTH-1:0] TXR_DATA,
input TXR_DATA_START_FLAG,
input [clog2s(C_PCI_DATA_WIDTH/32)-1:0] TXR_DATA_START_OFFSET,
input TXR_DATA_END_FLAG,
input [clog2s(C_PCI_DATA_WIDTH/32)-1:0] TXR_DATA_END_OFFSET,
output TXR_DATA_READY,
input TXR_META_VALID,
input [`SIG_FBE_W-1:0] TXR_META_FDWBE,
input [`SIG_LBE_W-1:0] TXR_META_LDWBE,
input [`SIG_ADDR_W-1:0] TXR_META_ADDR,
input [`SIG_LEN_W-1:0] TXR_META_LENGTH,
input [`SIG_TAG_W-1:0] TXR_META_TAG,
input [`SIG_TC_W-1:0] TXR_META_TC,
input [`SIG_ATTR_W-1:0] TXR_META_ATTR,
input [`SIG_TYPE_W-1:0] TXR_META_TYPE,
input TXR_META_EP,
output TXR_META_READY,
output TXR_SENT
);
localparam C_DEPTH_PACKETS = 10;
/*AUTOWIRE*/
/*AUTOINPUT*/
/*AUTOOUTPUT*/
reg rTxcSent;
reg rTxrSent;
assign TXC_SENT = rTxcSent;
assign TXR_SENT = rTxrSent;
always @(posedge CLK) begin
rTxcSent <= S_AXIS_CC_TLAST & S_AXIS_CC_TVALID & S_AXIS_CC_TREADY;
rTxrSent <= S_AXIS_RQ_TLAST & S_AXIS_RQ_TVALID & S_AXIS_RQ_TREADY;
end
txr_engine_ultrascale
#(
/*AUTOINSTPARAM*/
// Parameters
.C_PCI_DATA_WIDTH (C_PCI_DATA_WIDTH),
.C_PIPELINE_INPUT (C_PIPELINE_INPUT),
.C_PIPELINE_OUTPUT (C_PIPELINE_OUTPUT),
.C_DEPTH_PACKETS (C_DEPTH_PACKETS),
.C_MAX_PAYLOAD_DWORDS (C_MAX_PAYLOAD_DWORDS))
txr_engine_inst
(/*AUTOINST*/
// Outputs
.S_AXIS_RQ_TVALID (S_AXIS_RQ_TVALID),
.S_AXIS_RQ_TLAST (S_AXIS_RQ_TLAST),
.S_AXIS_RQ_TDATA (S_AXIS_RQ_TDATA[C_PCI_DATA_WIDTH-1:0]),
.S_AXIS_RQ_TKEEP (S_AXIS_RQ_TKEEP[(C_PCI_DATA_WIDTH/32)-1:0]),
.S_AXIS_RQ_TUSER (S_AXIS_RQ_TUSER[`SIG_RQ_TUSER_W-1:0]),
.TXR_DATA_READY (TXR_DATA_READY),
.TXR_META_READY (TXR_META_READY),
// Inputs
.CLK (CLK),
.RST_IN (RST_IN),
.CONFIG_COMPLETER_ID (CONFIG_COMPLETER_ID[`SIG_CPLID_W-1:0]),
.S_AXIS_RQ_TREADY (S_AXIS_RQ_TREADY),
.TXR_DATA_VALID (TXR_DATA_VALID),
.TXR_DATA (TXR_DATA[C_PCI_DATA_WIDTH-1:0]),
.TXR_DATA_START_FLAG (TXR_DATA_START_FLAG),
.TXR_DATA_START_OFFSET (TXR_DATA_START_OFFSET[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.TXR_DATA_END_FLAG (TXR_DATA_END_FLAG),
.TXR_DATA_END_OFFSET (TXR_DATA_END_OFFSET[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.TXR_META_VALID (TXR_META_VALID),
.TXR_META_FDWBE (TXR_META_FDWBE[`SIG_FBE_W-1:0]),
.TXR_META_LDWBE (TXR_META_LDWBE[`SIG_LBE_W-1:0]),
.TXR_META_ADDR (TXR_META_ADDR[`SIG_ADDR_W-1:0]),
.TXR_META_LENGTH (TXR_META_LENGTH[`SIG_LEN_W-1:0]),
.TXR_META_TAG (TXR_META_TAG[`SIG_TAG_W-1:0]),
.TXR_META_TC (TXR_META_TC[`SIG_TC_W-1:0]),
.TXR_META_ATTR (TXR_META_ATTR[`SIG_ATTR_W-1:0]),
.TXR_META_TYPE (TXR_META_TYPE[`SIG_TYPE_W-1:0]),
.TXR_META_EP (TXR_META_EP));
txc_engine_ultrascale
#(
/*AUTOINSTPARAM*/
// Parameters
.C_PCI_DATA_WIDTH (C_PCI_DATA_WIDTH),
.C_PIPELINE_INPUT (C_PIPELINE_INPUT),
.C_PIPELINE_OUTPUT (C_PIPELINE_OUTPUT),
.C_DEPTH_PACKETS (C_DEPTH_PACKETS),
.C_MAX_PAYLOAD_DWORDS (C_MAX_PAYLOAD_DWORDS))
txc_engine_inst
(/*AUTOINST*/
// Outputs
.S_AXIS_CC_TVALID (S_AXIS_CC_TVALID),
.S_AXIS_CC_TLAST (S_AXIS_CC_TLAST),
.S_AXIS_CC_TDATA (S_AXIS_CC_TDATA[C_PCI_DATA_WIDTH-1:0]),
.S_AXIS_CC_TKEEP (S_AXIS_CC_TKEEP[(C_PCI_DATA_WIDTH/32)-1:0]),
.S_AXIS_CC_TUSER (S_AXIS_CC_TUSER[`SIG_CC_TUSER_W-1:0]),
.TXC_DATA_READY (TXC_DATA_READY),
.TXC_META_READY (TXC_META_READY),
// Inputs
.CLK (CLK),
.RST_IN (RST_IN),
.CONFIG_COMPLETER_ID (CONFIG_COMPLETER_ID[`SIG_CPLID_W-1:0]),
.S_AXIS_CC_TREADY (S_AXIS_CC_TREADY),
.TXC_DATA_VALID (TXC_DATA_VALID),
.TXC_DATA (TXC_DATA[C_PCI_DATA_WIDTH-1:0]),
.TXC_DATA_START_FLAG (TXC_DATA_START_FLAG),
.TXC_DATA_START_OFFSET (TXC_DATA_START_OFFSET[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.TXC_DATA_END_FLAG (TXC_DATA_END_FLAG),
.TXC_DATA_END_OFFSET (TXC_DATA_END_OFFSET[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.TXC_META_VALID (TXC_META_VALID),
.TXC_META_FDWBE (TXC_META_FDWBE[`SIG_FBE_W-1:0]),
.TXC_META_LDWBE (TXC_META_LDWBE[`SIG_LBE_W-1:0]),
.TXC_META_ADDR (TXC_META_ADDR[`SIG_LOWADDR_W-1:0]),
.TXC_META_TYPE (TXC_META_TYPE[`SIG_TYPE_W-1:0]),
.TXC_META_LENGTH (TXC_META_LENGTH[`SIG_LEN_W-1:0]),
.TXC_META_BYTE_COUNT (TXC_META_BYTE_COUNT[`SIG_BYTECNT_W-1:0]),
.TXC_META_TAG (TXC_META_TAG[`SIG_TAG_W-1:0]),
.TXC_META_REQUESTER_ID (TXC_META_REQUESTER_ID[`SIG_REQID_W-1:0]),
.TXC_META_TC (TXC_META_TC[`SIG_TC_W-1:0]),
.TXC_META_ATTR (TXC_META_ATTR[`SIG_ATTR_W-1:0]),
.TXC_META_EP (TXC_META_EP));
endmodule
|
module sky130_fd_sc_hdll__nand4bb_1 (
Y ,
A_N ,
B_N ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A_N ;
input B_N ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__nand4bb base (
.Y(Y),
.A_N(A_N),
.B_N(B_N),
.C(C),
.D(D),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
|
module sky130_fd_sc_hdll__nand4bb_1 (
Y ,
A_N,
B_N,
C ,
D
);
output Y ;
input A_N;
input B_N;
input C ;
input D ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__nand4bb base (
.Y(Y),
.A_N(A_N),
.B_N(B_N),
.C(C),
.D(D)
);
endmodule
|
module assert_win_unchange_assert (clk, reset_n, start_event, end_event, test_expr, window,
xzdetect_test_expr, xzcheck_enable);
parameter width = 8;
input clk, reset_n, start_event, end_event, window;
input [width-1:0] test_expr;
input xzdetect_test_expr, xzcheck_enable;
endmodule
|
module assert_win_unchange_assume (clk, reset_n, start_event, end_event, test_expr, window,
xzdetect_test_expr, xzcheck_enable);
parameter width = 8;
input clk, reset_n, start_event, end_event, window;
input [width-1:0] test_expr;
input xzdetect_test_expr, xzcheck_enable;
endmodule
|
module assert_win_unchange_cover (clk, reset_n, start_event, end_event, window);
parameter OVL_COVER_BASIC_ON = 1;
input clk, reset_n, start_event, end_event, window;
endmodule
|
module ptp(
input wire clk,
input wire reset,
/* IO bus */
input wire iobus_iob_poweron,
input wire iobus_iob_reset,
input wire iobus_datao_clear,
input wire iobus_datao_set,
input wire iobus_cono_clear,
input wire iobus_cono_set,
input wire iobus_iob_fm_datai,
input wire iobus_iob_fm_status,
input wire iobus_rdi_pulse, // unused on 6
input wire [3:9] iobus_ios,
input wire [0:35] iobus_iob_in,
output wire [1:7] iobus_pi_req,
output wire [0:35] iobus_iob_out,
output wire iobus_dr_split,
output wire iobus_rdi_data, // unused on 6
/* Console panel */
input wire key_tape_feed,
output wire [7:0] ptp_ind,
output wire [6:0] status_ind, // also includes motor on
/* Avalon slave */
input wire s_read,
output wire [31:0] s_readdata,
output wire fe_data_rq
);
assign iobus_dr_split = 0;
assign iobus_rdi_data = 0;
assign ptp_ind = ptp;
assign status_ind = { ptp_speed, ptp_b, ptp_busy, ptp_flag, ptp_pia };
wire ptp_sel = iobus_ios == 7'b001_000_0;
wire ptp_data_clr;
wire ptp_data_set;
wire ptp_ic_clr;
wire ptp_ic_set;
wire iob_reset;
wire ptp_datai = ptp_sel & iobus_iob_fm_datai;
wire ptp_status = ptp_sel & iobus_iob_fm_status;
wire ptp_start_clr, ptp_stop_clr;
wire ptp_busy_set;
pa ptp_pa0(clk, reset, ptp_sel & iobus_datao_clear, ptp_data_clr);
pa ptp_pa1(clk, reset, ptp_sel & iobus_datao_set, ptp_data_set);
pa ptp_pa2(clk, reset, ptp_sel & iobus_cono_clear | iob_reset, ptp_ic_clr);
pa ptp_pa3(clk, reset, ptp_sel & iobus_cono_set, ptp_ic_set);
pa ptp_pa4(clk, reset, iobus_iob_reset, iob_reset);
reg [8:1] ptp;
assign iobus_iob_out =
ptp_status ? { 30'b0, ptp_b, ptp_busy, ptp_flag, ptp_pia } :
36'b0;
wire [1:7] ptp_req = { ptp_flag, 7'b0 } >> ptp_pia;
assign iobus_pi_req = ptp_req;
reg [33:35] ptp_pia;
reg ptp_busy;
reg ptp_flag;
reg ptp_b;
`ifdef simulation
initial begin
ptp_busy <= 0;
ptp_flag <= 0;
ptp_b <= 0;
end
`endif
always @(posedge clk) begin
if(ptp_ic_clr) begin
ptp_pia <= 0;
ptp_busy <= 0;
ptp_flag <= 0;
ptp_b <= 0;
end
if(ptp_ic_set) begin
ptp_pia <= iobus_iob_in[33:35];
if(iobus_iob_in[32])
ptp_flag <= 1;
if(iobus_iob_in[31])
ptp_busy <= 1;
if(iobus_iob_in[30])
ptp_b <= 1;
end
if(ptp_data_clr) begin
ptp_busy <= 1;
ptp_flag <= 0;
end
if(ptp_done) begin
ptp_busy <= 0;
ptp_flag <= 1;
end
if(ptp_b)
ptp[8:7] <= 2'b10;
if(ptp_data_clr)
ptp <= 0;
if(ptp_data_set)
ptp <= ptp | iobus_iob_in[28:35];
end
wire ptp_go = ptp_busy | key_tape_feed;
wire start_dly;
wire motor_on, on_pulse;
wire scr_driver = motor_on; // TODO: PWR CLR
wire ptp_done;
wire ptp_speed = ~start_dly & motor_on_dly[1];
wire ptp_ready = ptp_speed & ptp_busy;
`ifdef simulation
ldly2us ptp_dly0(.clk(clk), .reset(reset), .in(ptp_go), .l(motor_on));
ldly1us ptp_dly1(.clk(clk), .reset(reset), .in(on_pulse), .l(start_dly));
`else
ldly5s ptp_dly0(.clk(clk), .reset(reset), .in(ptp_go), .l(motor_on));
ldly1s ptp_dly1(.clk(clk), .reset(reset), .in(on_pulse), .l(start_dly));
`endif
pa ptp_pa5(clk, reset, motor_on, on_pulse);
/* Have to delay the signal a bit so we don't get a glitch in ptp_speed */
reg [1:0] motor_on_dly;
always @(posedge clk)
if(reset)
motor_on_dly <= 0;
else
motor_on_dly <= { motor_on_dly[0], motor_on };
// front end interface
assign fe_data_rq = fe_req;
assign s_readdata = (ptp_busy & ptp_write_sync) ? ptp : 0;
reg fe_req;
reg fe_rs;
wire ptp_clk;
// write gates buffer to solenoid drivers, done_pulse when done
wire ptp_write;
wire ptp_done_pulse;
// want to synchronize with the FE, so we'll actually use these two
reg ptp_write_sync;
reg ptp_done_sync;
`ifdef simulation
clk50khz ptp_clk0(clk, ptp_clk);
ldly2us ptp_dly2(clk, reset, ptp_clk & ptp_ready, ptp_done_pulse, ptp_write);
`else
clk63_3hz ptp_clk0(clk, ptp_clk);
ldly5ms ptp_dly2(clk, reset, ptp_clk & ptp_ready, ptp_done_pulse, ptp_write);
`endif
pa ptp_pa6(clk, reset, fe_rs & ptp_done_sync, ptp_done);
always @(posedge clk) begin
if(reset) begin
ptp_write_sync <= 0;
ptp_done_sync <= 0;
fe_req <= 0;
fe_rs <= 0;
end else begin
if(ptp_clk & (ptp_ready | key_tape_feed & ptp_speed)) begin
fe_req <= 1;
fe_rs <= 0;
end
if(s_read) begin
fe_req <= 0;
fe_rs <= 1;
end
if(ptp_done_pulse)
ptp_done_sync <= 1;
if(ptp_done) begin
ptp_write_sync <= 0;
ptp_done_sync <= 0;
end
if(ptp_write)
ptp_write_sync <= 1;
end
end
endmodule
|
module PCIEBus_gtp_pipe_reset #
(
//---------- Global ------------------------------------
parameter PCIE_SIM_SPEEDUP = "FALSE", // PCIe sim speedup
parameter PCIE_LANE = 1, // PCIe number of lanes
//---------- Local -------------------------------------
parameter CFG_WAIT_MAX = 6'd63, // Configuration wait max
parameter BYPASS_RXCDRLOCK = 1 // Bypass RXCDRLOCK
)
(
//---------- Input -------------------------------------
input RST_CLK,
input RST_RXUSRCLK,
input RST_DCLK,
input RST_RST_N,
input [PCIE_LANE-1:0] RST_DRP_DONE,
input [PCIE_LANE-1:0] RST_RXPMARESETDONE,
input RST_PLLLOCK,
input [PCIE_LANE-1:0] RST_RATE_IDLE,
input [PCIE_LANE-1:0] RST_RXCDRLOCK,
input RST_MMCM_LOCK,
input [PCIE_LANE-1:0] RST_RESETDONE,
input [PCIE_LANE-1:0] RST_PHYSTATUS,
input [PCIE_LANE-1:0] RST_TXSYNC_DONE,
//---------- Output ------------------------------------
output RST_CPLLRESET,
output RST_CPLLPD,
output reg RST_DRP_START,
output reg RST_DRP_X16,
output RST_RXUSRCLK_RESET,
output RST_DCLK_RESET,
output RST_GTRESET,
output RST_USERRDY,
output RST_TXSYNC_START,
output RST_IDLE,
output [ 4:0] RST_FSM
);
//---------- Input Register ----------------------------
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] drp_done_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] rxpmaresetdone_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg plllock_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] rate_idle_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] rxcdrlock_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg mmcm_lock_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] resetdone_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] phystatus_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] txsync_done_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] drp_done_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] rxpmaresetdone_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg plllock_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] rate_idle_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] rxcdrlock_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg mmcm_lock_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] resetdone_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] phystatus_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] txsync_done_reg2;
//---------- Internal Signal ---------------------------
reg [ 5:0] cfg_wait_cnt = 6'd0;
//---------- Output Register ---------------------------
reg pllreset = 1'd0;
reg pllpd = 1'd0;
reg rxusrclk_rst_reg1 = 1'd0;
reg rxusrclk_rst_reg2 = 1'd0;
reg dclk_rst_reg1 = 1'd0;
reg dclk_rst_reg2 = 1'd0;
reg gtreset = 1'd0;
reg userrdy = 1'd0;
reg [ 4:0] fsm = 5'h1;
//---------- FSM ---------------------------------------
localparam FSM_IDLE = 5'h0;
localparam FSM_CFG_WAIT = 5'h1;
localparam FSM_PLLRESET = 5'h2;
localparam FSM_DRP_X16_START = 5'h3;
localparam FSM_DRP_X16_DONE = 5'h4;
localparam FSM_PLLLOCK = 5'h5;
localparam FSM_GTRESET = 5'h6;
localparam FSM_RXPMARESETDONE_1 = 5'h7;
localparam FSM_RXPMARESETDONE_2 = 5'h8;
localparam FSM_DRP_X20_START = 5'h9;
localparam FSM_DRP_X20_DONE = 5'hA;
localparam FSM_MMCM_LOCK = 5'hB;
localparam FSM_RESETDONE = 5'hC;
localparam FSM_TXSYNC_START = 5'hD;
localparam FSM_TXSYNC_DONE = 5'hE;
//---------- Input FF ----------------------------------------------------------
always @ (posedge RST_CLK)
begin
if (!RST_RST_N)
begin
//---------- 1st Stage FF --------------------------
drp_done_reg1 <= {PCIE_LANE{1'd0}};
rxpmaresetdone_reg1 <= {PCIE_LANE{1'd0}};
plllock_reg1 <= 1'd0;
rate_idle_reg1 <= {PCIE_LANE{1'd0}};
rxcdrlock_reg1 <= {PCIE_LANE{1'd0}};
mmcm_lock_reg1 <= 1'd0;
resetdone_reg1 <= {PCIE_LANE{1'd0}};
phystatus_reg1 <= {PCIE_LANE{1'd0}};
txsync_done_reg1 <= {PCIE_LANE{1'd0}};
//---------- 2nd Stage FF --------------------------
drp_done_reg2 <= {PCIE_LANE{1'd0}};
rxpmaresetdone_reg2 <= {PCIE_LANE{1'd0}};
plllock_reg2 <= 1'd0;
rate_idle_reg2 <= {PCIE_LANE{1'd0}};
rxcdrlock_reg2 <= {PCIE_LANE{1'd0}};
mmcm_lock_reg2 <= 1'd0;
resetdone_reg2 <= {PCIE_LANE{1'd0}};
phystatus_reg2 <= {PCIE_LANE{1'd0}};
txsync_done_reg2 <= {PCIE_LANE{1'd0}};
end
else
begin
//---------- 1st Stage FF --------------------------
drp_done_reg1 <= RST_DRP_DONE;
rxpmaresetdone_reg1 <= RST_RXPMARESETDONE;
plllock_reg1 <= RST_PLLLOCK;
rate_idle_reg1 <= RST_RATE_IDLE;
rxcdrlock_reg1 <= RST_RXCDRLOCK;
mmcm_lock_reg1 <= RST_MMCM_LOCK;
resetdone_reg1 <= RST_RESETDONE;
phystatus_reg1 <= RST_PHYSTATUS;
txsync_done_reg1 <= RST_TXSYNC_DONE;
//---------- 2nd Stage FF --------------------------
drp_done_reg2 <= drp_done_reg1;
rxpmaresetdone_reg2 <= rxpmaresetdone_reg1;
plllock_reg2 <= plllock_reg1;
rate_idle_reg2 <= rate_idle_reg1;
rxcdrlock_reg2 <= rxcdrlock_reg1;
mmcm_lock_reg2 <= mmcm_lock_reg1;
resetdone_reg2 <= resetdone_reg1;
phystatus_reg2 <= phystatus_reg1;
txsync_done_reg2 <= txsync_done_reg1;
end
end
//---------- Configuration Reset Wait Counter ----------------------------------
always @ (posedge RST_CLK)
begin
if (!RST_RST_N)
cfg_wait_cnt <= 6'd0;
else
//---------- Increment Configuration Reset Wait Counter
if ((fsm == FSM_CFG_WAIT) && (cfg_wait_cnt < CFG_WAIT_MAX))
cfg_wait_cnt <= cfg_wait_cnt + 6'd1;
//---------- Hold Configuration Reset Wait Counter -
else if ((fsm == FSM_CFG_WAIT) && (cfg_wait_cnt == CFG_WAIT_MAX))
cfg_wait_cnt <= cfg_wait_cnt;
//---------- Reset Configuration Reset Wait Counter
else
cfg_wait_cnt <= 6'd0;
end
//---------- PIPE Reset FSM ----------------------------------------------------
always @ (posedge RST_CLK)
begin
if (!RST_RST_N)
begin
fsm <= FSM_CFG_WAIT;
pllreset <= 1'd0;
pllpd <= 1'd0;
gtreset <= 1'd0;
userrdy <= 1'd0;
end
else
begin
case (fsm)
//---------- Idle State ----------------------------
FSM_IDLE :
begin
if (!RST_RST_N)
begin
fsm <= FSM_CFG_WAIT;
pllreset <= 1'd0;
pllpd <= 1'd0;
gtreset <= 1'd0;
userrdy <= 1'd0;
end
else
begin
fsm <= FSM_IDLE;
pllreset <= pllreset;
pllpd <= pllpd;
gtreset <= gtreset;
userrdy <= userrdy;
end
end
//---------- Wait for Configuration Reset Delay ---
FSM_CFG_WAIT :
begin
fsm <= ((cfg_wait_cnt == CFG_WAIT_MAX) ? FSM_PLLRESET : FSM_CFG_WAIT);
pllreset <= pllreset;
pllpd <= pllpd;
gtreset <= gtreset;
userrdy <= userrdy;
end
//---------- Hold PLL and GTP Channel in Reset ----
FSM_PLLRESET :
begin
fsm <= (((~plllock_reg2) && (&(~resetdone_reg2))) ? FSM_DRP_X16_START : FSM_PLLRESET);
pllreset <= 1'd1;
pllpd <= pllpd;
gtreset <= 1'd1;
userrdy <= userrdy;
end
//---------- Start DRP x16 -------------------------
FSM_DRP_X16_START :
begin
fsm <= &(~drp_done_reg2) ? FSM_DRP_X16_DONE : FSM_DRP_X16_START;
pllreset <= pllreset;
pllpd <= pllpd;
gtreset <= gtreset;
userrdy <= userrdy;
end
//---------- Wait for DRP x16 Done -----------------
FSM_DRP_X16_DONE :
begin
fsm <= (&drp_done_reg2) ? FSM_PLLLOCK : FSM_DRP_X16_DONE;
pllreset <= pllreset;
pllpd <= pllpd;
gtreset <= gtreset;
userrdy <= userrdy;
end
//---------- Wait for PLL Lock --------------------
FSM_PLLLOCK :
begin
fsm <= (plllock_reg2 ? FSM_GTRESET : FSM_PLLLOCK);
pllreset <= 1'd0;
pllpd <= pllpd;
gtreset <= gtreset;
userrdy <= userrdy;
end
//---------- Release GTRESET -----------------------
FSM_GTRESET :
begin
fsm <= FSM_RXPMARESETDONE_1;
pllreset <= pllreset;
pllpd <= pllpd;
gtreset <= 1'b0;
userrdy <= userrdy;
end
//---------- Wait for RXPMARESETDONE Assertion -----
FSM_RXPMARESETDONE_1 :
begin
fsm <= (&rxpmaresetdone_reg2 || (PCIE_SIM_SPEEDUP == "TRUE")) ? FSM_RXPMARESETDONE_2 : FSM_RXPMARESETDONE_1;
pllreset <= pllreset;
pllpd <= pllpd;
gtreset <= gtreset;
userrdy <= userrdy;
end
//---------- Wait for RXPMARESETDONE De-assertion --
FSM_RXPMARESETDONE_2 :
begin
fsm <= (&(~rxpmaresetdone_reg2) || (PCIE_SIM_SPEEDUP == "TRUE")) ? FSM_DRP_X20_START : FSM_RXPMARESETDONE_2;
pllreset <= pllreset;
pllpd <= pllpd;
gtreset <= gtreset;
userrdy <= userrdy;
end
//---------- Start DRP x20 -------------------------
FSM_DRP_X20_START :
begin
fsm <= &(~drp_done_reg2) ? FSM_DRP_X20_DONE : FSM_DRP_X20_START;
pllreset <= pllreset;
pllpd <= pllpd;
gtreset <= gtreset;
userrdy <= userrdy;
end
//---------- Wait for DRP x20 Done -----------------
FSM_DRP_X20_DONE :
begin
fsm <= (&drp_done_reg2) ? FSM_MMCM_LOCK : FSM_DRP_X20_DONE;
pllreset <= pllreset;
pllpd <= pllpd;
gtreset <= gtreset;
userrdy <= userrdy;
end
//---------- Wait for MMCM and RX CDR Lock ---------
FSM_MMCM_LOCK :
begin
if (mmcm_lock_reg2 && (&rxcdrlock_reg2 || (BYPASS_RXCDRLOCK == 1)))
begin
fsm <= FSM_RESETDONE;
pllreset <= pllreset;
pllpd <= pllpd;
gtreset <= gtreset;
userrdy <= 1'd1;
end
else
begin
fsm <= FSM_MMCM_LOCK;
pllreset <= pllreset;
pllpd <= pllpd;
gtreset <= gtreset;
userrdy <= 1'd0;
end
end
//---------- Wait for [TX/RX]RESETDONE and PHYSTATUS
FSM_RESETDONE :
begin
fsm <= (&resetdone_reg2 && (&(~phystatus_reg2)) ? FSM_TXSYNC_START : FSM_RESETDONE);
pllreset <= pllreset;
pllpd <= pllpd;
gtreset <= gtreset;
userrdy <= userrdy;
end
//---------- Start TX Sync -------------------------
FSM_TXSYNC_START :
begin
fsm <= (&(~txsync_done_reg2) ? FSM_TXSYNC_DONE : FSM_TXSYNC_START);
pllreset <= pllreset;
pllpd <= pllpd;
gtreset <= gtreset;
userrdy <= userrdy;
end
//---------- Wait for TX Sync Done -----------------
FSM_TXSYNC_DONE :
begin
fsm <= (&txsync_done_reg2 ? FSM_IDLE : FSM_TXSYNC_DONE);
pllreset <= pllreset;
pllpd <= pllpd;
gtreset <= gtreset;
userrdy <= userrdy;
end
//---------- Default State -------------------------
default :
begin
fsm <= FSM_CFG_WAIT;
pllreset <= 1'd0;
pllpd <= 1'd0;
gtreset <= 1'd0;
userrdy <= 1'd0;
end
endcase
end
end
//---------- RXUSRCLK Reset Synchronizer ---------------------------------------
always @ (posedge RST_RXUSRCLK)
begin
if (pllreset)
begin
rxusrclk_rst_reg1 <= 1'd1;
rxusrclk_rst_reg2 <= 1'd1;
end
else
begin
rxusrclk_rst_reg1 <= 1'd0;
rxusrclk_rst_reg2 <= rxusrclk_rst_reg1;
end
end
//---------- DCLK Reset Synchronizer -------------------------------------------
always @ (posedge RST_DCLK)
begin
if (fsm == FSM_CFG_WAIT)
begin
dclk_rst_reg1 <= 1'd1;
dclk_rst_reg2 <= dclk_rst_reg1;
end
else
begin
dclk_rst_reg1 <= 1'd0;
dclk_rst_reg2 <= dclk_rst_reg1;
end
end
//---------- PIPE Reset Output -------------------------------------------------
assign RST_CPLLRESET = pllreset;
assign RST_CPLLPD = pllpd;
assign RST_RXUSRCLK_RESET = rxusrclk_rst_reg2;
assign RST_DCLK_RESET = dclk_rst_reg2;
assign RST_GTRESET = gtreset;
assign RST_USERRDY = userrdy;
assign RST_TXSYNC_START = (fsm == FSM_TXSYNC_START);
assign RST_IDLE = (fsm == FSM_IDLE);
assign RST_FSM = fsm;
//--------------------------------------------------------------------------------------------------
// Register Output
//--------------------------------------------------------------------------------------------------
always @ (posedge RST_CLK)
begin
if (!RST_RST_N)
begin
RST_DRP_START <= 1'd0;
RST_DRP_X16 <= 1'd0;
end
else
begin
RST_DRP_START <= (fsm == FSM_DRP_X16_START) || (fsm == FSM_DRP_X20_START);
RST_DRP_X16 <= (fsm == FSM_DRP_X16_START) || (fsm == FSM_DRP_X16_DONE);
end
end
endmodule
|
module recibo ( input clk,
input rw,
input reset,
input Rx,
output busy,
output clk_blu,
output reg[7:0]dout
);
wire clk_f;
Divisor_frecuencia div(.clk(clk), .clk_f(clk_f), .reset(reset));
reg[1:0]estado, estado_sig;
parameter inactivo =2'b00;
parameter inicio =2'b01;
reg control;
reg done = 0;
reg[8:0]tmp=9'b000000000;
reg[3:0]contador=4'b0000;
//maquina de estados
always@(posedge clk_f, posedge reset)
if(reset)estado <= inactivo;
else estado <= estado_sig;
always@(*)
begin
case(estado)
inactivo:
if(Rx==1 && done==0)
begin
control=0;
estado_sig = inactivo;
end
else if (Rx==0 && done==0 && rw==1)
begin
control=1;
estado_sig = inicio;
end
else
begin
control=0;
estado_sig = inactivo;
end
inicio:
begin
if(done==0)
begin
control=1;
estado_sig = inicio;
end
else
begin
control=0;
estado_sig = inactivo;
end
end
default
estado_sig = inactivo;
endcase
end
//hasta aqui se describe como se pasa de un estado a otro
//ahora viene el bloque de decision que descibe de que manera capturamos la informacion
always@(posedge clk_f)
begin
if(control==1 && done==0)
begin
tmp<={Rx,tmp[8:1]};
end
end
always@(posedge clk_f)
begin
if(control)
if(contador>=10)
begin
contador=0;
done=1;
dout<=tmp[8:1];
end
else
begin
contador=contador+1;
done=0;
end
else
done=0;
end
endmodule
|
module SmallLpf2nd #(
parameter K0_SHIFT = 8, ///< K0 filter term = 2^-K0_SHIFT
parameter K1_SHIFT = 8, ///< K1 filter term = 2^-K1_SHIFT
parameter WIDTH = 16, ///< Width of data path
parameter CLAMP = 1 ///< Set to 1 to clamp the accumulators
)
(
input clk, ///< System clock
input rst, ///< Reset, synchronous & active high
input en, ///< Filter strobe
input signed [WIDTH-1:0] dataIn, ///< Filter input
output signed [WIDTH-1:0] dataOut ///< Filter input
);
reg signed [WIDTH+K0_SHIFT-1:0] acc0;
reg signed [WIDTH+K1_SHIFT-1:0] acc1;
reg signed [WIDTH+1:0] forwardIn;
wire signed [WIDTH-1:0] acc0Out;
wire signed [WIDTH+K0_SHIFT:0] acc0In;
wire signed [WIDTH+K1_SHIFT:0] acc1In;
assign acc0In = acc0 + forwardIn;
assign acc1In = acc1 + acc0Out;
always @(posedge clk) begin
if (rst) begin
forwardIn <= 'd0;
acc0 <= 'd0;
acc1 <= 'd0;
end
else if (en) begin
forwardIn <= dataIn - acc0Out - dataOut;
if (CLAMP) begin
acc0 <= (^acc0In[WIDTH+K0_SHIFT-:2])
? {acc0In[WIDTH+K0_SHIFT], {(WIDTH+K0_SHIFT-1){acc0In[WIDTH+K0_SHIFT-1]}}}
: acc0In;
acc1 <= (^acc1In[WIDTH+K1_SHIFT-:2])
? {acc1In[WIDTH+K1_SHIFT], {(WIDTH+K1_SHIFT-1){acc1In[WIDTH+K1_SHIFT-1]}}}
: acc1In;
end
else begin
acc0 <= acc0In;
acc1 <= acc1In;
end
end
end
assign acc0Out = acc0 >>> K0_SHIFT;
assign dataOut = acc1 >>> K1_SHIFT;
// Test Code: Check to see if clamping ever occurs
/*
reg clamp0;
reg clamp1;
always @(posedge clk) begin
if (rst) begin
clamp0 <= 1'b0;
clamp1 <= 1'b0;
end
else begin
clamp0 <= clamp0 | (^acc0In[WIDTH+K0_SHIFT-:2]);
clamp1 <= clamp1 | (^acc1In[WIDTH+K1_SHIFT-:2]);
end
end
*/
endmodule
|
module xlr8_xf #(
// Address mapped control and data registers
parameter STGI_XF_CTRL_ADR = 8'h10,
parameter STGI_XF_STATUS_ADR = 8'h11,
parameter STGI_XF_R0_ADR = 8'h0C, // 32b result
parameter STGI_XF_R1_ADR = 8'h0D,
parameter STGI_XF_R2_ADR = 8'h0E,
parameter STGI_XF_R3_ADR = 8'h0F,
// Functional Unit Latencies. Latency=0 means function not implemented
parameter STGI_XF_PRELOAD_DELTA = 8'h03,
parameter STGI_XF_P0_LATENCY = 8'h01, // COMPARE
parameter STGI_XF_P1_LATENCY = 8'h02, // ADD
parameter STGI_XF_P2_LATENCY = 8'h05, // SUB
parameter STGI_XF_P3_LATENCY = 8'h03, // MULT
parameter STGI_XF_P4_LATENCY = 8'h1C, // DIV
parameter STGI_XF_P5_LATENCY = 8'h06, // SQRT
parameter STGI_XF_P6_LATENCY = 8'h01, // CONVERT2FLOAT
parameter STGI_XF_P7_LATENCY = 8'h01 // CONVERT2FIXED
)
(cp2,
ireset,
adr,
dbus_in,
dbus_out,
iore,
iowe,
out_en,
core_ramadr,
core_ramre,
core_ramwe,
core_dm_sel,
gprf,
xf_dataa,
xf_datab,
xf_en,
xf_p0_result,
xf_p1_result,
xf_p2_result,
xf_p3_result,
xf_p4_result,
xf_p5_result,
xf_p6_result,
xf_p7_result
);
/*AUTOINPUT*/
/*AUTOOUTPUT*/
// clock and reset
input ireset;
input cp2;
// AVR Control
input [5:0] adr;
input [7:0] dbus_in;
output[7:0] dbus_out;
input iore;
input iowe;
output out_en;
// DM control from AVR core
input [7:0] core_ramadr;
input core_ramre;
input core_ramwe;
input core_dm_sel;
// Register file (read-only access)
input [8*32-1:0] gprf;
// Port interface
output [31:0] xf_dataa;
output [31:0] xf_datab;
output [7:0] xf_en;
input [31:0] xf_p0_result;
input [31:0] xf_p1_result;
input [31:0] xf_p2_result;
input [31:0] xf_p3_result;
input [31:0] xf_p4_result;
input [31:0] xf_p5_result;
input [31:0] xf_p6_result;
input [31:0] xf_p7_result;
// Control reg definitions
localparam STGI_XF_P0_CMD = 3'h0;
localparam STGI_XF_P1_CMD = 3'h1;
localparam STGI_XF_P2_CMD = 3'h2;
localparam STGI_XF_P3_CMD = 3'h3;
localparam STGI_XF_P4_CMD = 3'h4;
localparam STGI_XF_P5_CMD = 3'h5;
localparam STGI_XF_P6_CMD = 3'h6;
localparam STGI_XF_P7_CMD = 3'h7;
localparam CTRL_DM_LOC = (STGI_XF_CTRL_ADR >= 16'h60) ? 1 : 0;
localparam STATUS_DM_LOC = (STGI_XF_STATUS_ADR >= 16'h60) ? 1 : 0;
localparam R_DM_LOC = (STGI_XF_R0_ADR >= 16'h60) ? 1 : 0;
//***********************************************************************
//-------------------------------------------------------
// Reg/Wire Declarations
//-------------------------------------------------------
/*AUTOWIRE*/
/*AUTOREG*/
logic [31:0] result;
logic [7:0] ctrl_reg;
logic [7:0] status_reg;
logic [31:0] xf_dataa;
logic [31:0] xf_datab;
logic [7:0] xf_sel;
logic [2:0] current_cmd;
logic [7:0] port_complete;
logic fp_complete;
logic function_start;
logic function_active;
logic [7:0] result_tc;
logic ctrl_adr;
logic status_adr;
logic r0_adr;
logic r1_adr;
logic r2_adr;
logic r3_adr;
logic ctrl_re;
logic ctrl_we;
logic status_re;
logic r0_re;
logic r1_re;
logic r2_re;
logic r3_re;
logic [7:0] xf_en;
// Determine which address we are receiving
assign ctrl_adr = CTRL_DM_LOC ?
(core_dm_sel && core_ramadr == STGI_XF_CTRL_ADR) :
({2'h0,adr} == STGI_XF_CTRL_ADR);
assign status_adr = STATUS_DM_LOC ?
(core_dm_sel && core_ramadr == STGI_XF_STATUS_ADR) :
({2'h0,adr} == STGI_XF_STATUS_ADR);
assign r0_adr = R_DM_LOC ?
(core_dm_sel && core_ramadr == STGI_XF_R0_ADR) :
({2'h0,adr} == STGI_XF_R0_ADR);
assign r1_adr = R_DM_LOC ?
(core_dm_sel && core_ramadr == STGI_XF_R1_ADR) :
({2'h0,adr} == STGI_XF_R1_ADR);
assign r2_adr = R_DM_LOC ?
(core_dm_sel && core_ramadr == STGI_XF_R2_ADR) :
({2'h0,adr} == STGI_XF_R2_ADR);
assign r3_adr = R_DM_LOC ?
(core_dm_sel && core_ramadr == STGI_XF_R3_ADR) :
({2'h0,adr} == STGI_XF_R3_ADR);
// Set appropriate Read Enable and Write Enable bits
assign ctrl_re = ctrl_adr && (CTRL_DM_LOC ? core_ramre : iore);
assign ctrl_we = ctrl_adr && (CTRL_DM_LOC ? core_ramwe : iowe);
assign status_re = status_adr && (STATUS_DM_LOC ? core_ramre : iore);
//assign status_we = status_adr && (STATUS_DM_LOC ? core_ramwe : iowe);
assign r0_re = r0_adr && (R_DM_LOC ? core_ramre : iore);
//assign r0_we = r0_adr && (R_DM_LOC ? core_ramwe : iowe);
assign r1_re = r1_adr && (R_DM_LOC ? core_ramre : iore);
//assign r1_we = r1_adr && (R_DM_LOC ? core_ramwe : iowe);
assign r2_re = r2_adr && (R_DM_LOC ? core_ramre : iore);
//assign r2_we = r2_adr && (R_DM_LOC ? core_ramwe : iowe);
assign r3_re = r3_adr && (R_DM_LOC ? core_ramre : iore);
//assign r3_we = r3_adr && (R_DM_LOC ? core_ramwe : iowe);
// Latch up the appropriate reg when a read is requested
assign dbus_out = ({8{ctrl_re}} & ctrl_reg) |
({8{status_re}} & status_reg) |
({8{r0_re}} & result[7:0]) |
({8{r1_re}} & result[15:8]) |
({8{r2_re}} & result[23:16]) |
({8{r3_re}} & result[31:24]);
assign out_en = ctrl_re ||
status_re ||
r0_re ||
r1_re ||
r2_re ||
r3_re;
always@(posedge cp2 or negedge ireset) begin: ctrlreg
if (!ireset) begin
ctrl_reg <= 8'h00;
end
else begin
// We are now using ctrl_reg[7] in the C library to trick the
// compiler, so we never want bit 7 to get set. See the
// XLR8Float.cpp file for details on the compiler trick
ctrl_reg <= (ctrl_we) ? {1'b0, dbus_in[6:0]} : ctrl_reg;
end
end
assign current_cmd = (ctrl_we) ? dbus_in[2:0] : ctrl_reg[2:0];
assign function_start = ctrl_we & (dbus_in[6] == 1'b1);
always@(posedge cp2 or negedge ireset)
begin
if (!ireset) begin
function_active <= 1'h0;
end
else begin
if (function_start && ~fp_complete) begin
function_active <= 1'b1;
end else if (fp_complete) begin
function_active = 1'b0;
end
end
end
always@(posedge cp2 or negedge ireset)
begin
if (!ireset) begin
status_reg <= 8'h00;
end
else begin
// Handle the status return value. Latch up the status when
// Function is complete. Then when AVR
// reads status, latch it into the output reg, clear the
// status reg, and hold the output reg until iore goes
// away.
if (fp_complete) begin
status_reg[7] <= 1'b1;
status_reg[6] <= ~|xf_sel; // if selected unit is not enabled return failure condition
status_reg[5:0] <= 6'h0;
end else if (function_start) begin // clear when a new ctrl reg is written
status_reg <= 8'h00;
end else if (dbus_out[7] && status_re) begin // clear completion flag when status is read
status_reg[7] <= 1'b0;
end
end // else: !if(!ireset)
end // always@ (posedge cp2 or negedge ireset)
// Extract operand data from the AVR registers
always@(posedge cp2 or negedge ireset)
begin
if (!ireset) begin
xf_dataa <= 32'h00000000;
xf_datab <= 32'h00000000;
end
else begin
xf_dataa <= gprf[22*8 +: 4*8];
xf_datab <= gprf[18*8 +: 4*8];
end
end // always@ (posedge cp2 or negedge ireset)
// set enable bits based on current command. Use latency=-1 to indicate unsupported functions
always_comb begin
xf_sel[0] = (current_cmd == STGI_XF_P0_CMD) && (STGI_XF_P0_LATENCY != 8'd0);
xf_sel[1] = (current_cmd == STGI_XF_P1_CMD) && (STGI_XF_P1_LATENCY != 8'd0);
xf_sel[2] = (current_cmd == STGI_XF_P2_CMD) && (STGI_XF_P2_LATENCY != 8'd0);
xf_sel[3] = (current_cmd == STGI_XF_P3_CMD) && (STGI_XF_P3_LATENCY != 8'd0);
xf_sel[4] = (current_cmd == STGI_XF_P4_CMD) && (STGI_XF_P4_LATENCY != 8'd0);
xf_sel[5] = (current_cmd == STGI_XF_P5_CMD) && (STGI_XF_P5_LATENCY != 8'd0);
xf_sel[6] = (current_cmd == STGI_XF_P6_CMD) && (STGI_XF_P6_LATENCY != 8'd0);
xf_sel[7] = (current_cmd == STGI_XF_P7_CMD) && (STGI_XF_P7_LATENCY != 8'd0);
end
always_comb xf_en = xf_sel & {8{function_start}};
// Set complete valid bits on a per port basis
always_comb begin
port_complete[0] = (((STGI_XF_PRELOAD_DELTA >= STGI_XF_P0_LATENCY) && function_start) ||
((result_tc == STGI_XF_P0_LATENCY) && function_active)) &&
(current_cmd == STGI_XF_P0_CMD);
port_complete[1] = (((STGI_XF_PRELOAD_DELTA >= STGI_XF_P1_LATENCY) && function_start) ||
((result_tc == STGI_XF_P1_LATENCY) && function_active)) &&
(current_cmd == STGI_XF_P1_CMD);
port_complete[2] = (((STGI_XF_PRELOAD_DELTA >= STGI_XF_P2_LATENCY) && function_start) ||
((result_tc == STGI_XF_P2_LATENCY) && function_active)) &&
(current_cmd == STGI_XF_P2_CMD);
port_complete[3] = (((STGI_XF_PRELOAD_DELTA >= STGI_XF_P3_LATENCY) && function_start) ||
((result_tc == STGI_XF_P3_LATENCY) && function_active)) &&
(current_cmd == STGI_XF_P3_CMD);
port_complete[4] = (((STGI_XF_PRELOAD_DELTA >= STGI_XF_P4_LATENCY) && function_start) ||
((result_tc == STGI_XF_P4_LATENCY) && function_active)) &&
(current_cmd == STGI_XF_P4_CMD);
port_complete[5] = (((STGI_XF_PRELOAD_DELTA >= STGI_XF_P5_LATENCY) && function_start) ||
((result_tc == STGI_XF_P5_LATENCY) && function_active)) &&
(current_cmd == STGI_XF_P5_CMD);
port_complete[6] = (((STGI_XF_PRELOAD_DELTA >= STGI_XF_P6_LATENCY) && function_start) ||
((result_tc == STGI_XF_P6_LATENCY) && function_active)) &&
(current_cmd == STGI_XF_P6_CMD);
port_complete[7] = (((STGI_XF_PRELOAD_DELTA >= STGI_XF_P7_LATENCY) && function_start) ||
((result_tc == STGI_XF_P7_LATENCY) && function_active)) &&
(current_cmd == STGI_XF_P7_CMD);
end
assign fp_complete = |port_complete;
// Result timing chain. Reset whenever we launch a function start
always@(posedge cp2 or negedge ireset)
begin: resulttimingchain
if (!ireset) begin
result_tc <= STGI_XF_PRELOAD_DELTA;
result <= 32'h00000000;
end
else begin
if ((result_tc > STGI_XF_PRELOAD_DELTA) || function_start) begin
result_tc <= result_tc + 1;
end
// Capture result from FP units
if (fp_complete) begin: snagresults
result_tc <= STGI_XF_PRELOAD_DELTA;
// ASSERT: port_complete should be a one shot
case (port_complete)
8'h01: result <= xf_p0_result;
8'h02: result <= xf_p1_result;
8'h04: result <= xf_p2_result;
8'h08: result <= xf_p3_result;
8'h10: result <= xf_p4_result;
8'h20: result <= xf_p5_result;
8'h40: result <= xf_p6_result;
8'h80: result <= xf_p7_result;
default: result <= result;
endcase // case (port_complete)
end // block: snagresults
end
end // block: resulttimingchain
wire _unused_ok = &{1'b0,
gprf[255:208],gprf[143:0], // only use regs 18-25
1'b0};
endmodule
|
module test;
reg clk;
reg rst;
// IO Prototypes
wire [31:0] wb0s_data_i;
wire [31:0] wb0s_data_o;
wire [31:0] wb0_addr_i;
wire [3:0] wb0_sel_i;
wire wb0_we_i;
wire wb0_cyc_i;
wire wb0_stb_i;
wire wb0_ack_o;
wire wb0_err_o;
wire wb0_rty_o;
wire [31:0] wb0m_data_i;
wire [31:0] wb0m_data_o;
wire [31:0] wb0_addr_o;
wire [3:0] wb0_sel_o;
wire wb0_we_o;
wire wb0_cyc_o;
wire wb0_stb_o;
wire wb0_ack_i;
wire wb0_err_i;
wire wb0_rty_i;
wire [31:0] wb1s_data_i;
wire [31:0] wb1s_data_o;
wire [31:0] wb1_addr_i;
wire [3:0] wb1_sel_i;
wire wb1_we_i;
wire wb1_cyc_i;
wire wb1_stb_i;
wire wb1_ack_o;
wire wb1_err_o;
wire wb1_rty_o;
wire [31:0] wb1m_data_i;
wire [31:0] wb1m_data_o;
wire [31:0] wb1_addr_o;
wire [3:0] wb1_sel_o;
wire wb1_we_o;
wire wb1_cyc_o;
wire wb1_stb_o;
wire wb1_ack_i;
wire wb1_err_i;
wire wb1_rty_i;
reg [`CH_COUNT-1:0] req_i;
wire [`CH_COUNT-1:0] ack_o;
reg [`CH_COUNT-1:0] nd_i;
reg [`CH_COUNT-1:0] rest_i;
wire inta_o;
wire intb_o;
wire [31:0] wb0_data_o_mast;
wire [31:0] wb1_data_o_mast;
wire [31:0] wb0_data_o_slv;
wire [31:0] wb1_data_o_slv;
// Test Bench Variables
reg [31:0] wd_cnt;
integer error_cnt;
reg ack_cnt_clr;
reg [31:0] ack_cnt;
// Misc Variables
/////////////////////////////////////////////////////////////////////
//
// Defines
//
`define MEM 32'h0002_0000
`define REG_BASE 32'hb000_0000
`define COR 8'h0
`define INT_MASKA 8'h4
`define INT_MASKB 8'h8
`define INT_SRCA 8'hc
`define INT_SRCB 8'h10
`define CH0_CSR 8'h20
`define CH0_TXSZ 8'h24
`define CH0_ADR0 8'h28
`define CH0_AM0 8'h2c
`define CH0_ADR1 8'h30
`define CH0_AM1 8'h34
`define PTR0 8'h38
`define CH1_CSR 8'h40
`define CH1_TXSZ 8'h44
`define CH1_ADR0 8'h48
`define CH1_AM0 8'h4c
`define CH1_ADR1 8'h50
`define CH1_AM1 8'h54
`define PTR1 8'h58
`define CH2_CSR 8'h60
`define CH2_TXSZ 8'h64
`define CH2_ADR0 8'h68
`define CH2_AM0 8'h6c
`define CH2_ADR1 8'h70
`define CH2_AM1 8'h74
`define PTR2 8'h78
`define CH3_CSR 8'h80
`define CH3_TXSZ 8'h84
`define CH3_ADR0 8'h88
`define CH3_AM0 8'h8c
`define CH3_ADR1 8'h90
`define CH3_AM1 8'h94
`define PTR3 8'h98
/////////////////////////////////////////////////////////////////////
//
// Simulation Initialization and Start up Section
//
initial
begin
$display("\n\n");
$display("**********************************************");
$display("* WISHBONE DMA/BRIDGE Simulation started ... *");
$display("**********************************************");
$display("\n");
`ifdef WAVES
$shm_open("waves");
$shm_probe("AS",test,"AS");
$display("INFO: Signal dump enabled ...\n\n");
`endif
req_i = 0;
nd_i = 0;
wd_cnt = 0;
ack_cnt = 0;
ack_cnt_clr = 0;
error_cnt = 0;
clk = 0;
rst = 1;
rest_i = 0;
repeat(10) @(posedge clk);
rst = 0;
repeat(10) @(posedge clk);
// HERE IS WHERE THE TEST CASES GO ...
if(1) // Full Regression Run
begin
$display(" ......................................................");
$display(" : :");
$display(" : Long Regression Run ... :");
$display(" :....................................................:");
pt10_rd;
pt01_wr;
pt01_rd;
pt10_wr;
sw_dma1(0);
sw_dma2(0);
hw_dma1(0);
hw_dma2(0);
arb_test1;
sw_ext_desc1(0);
hw_dma3(0);
hw_dma4(0);
end
else
if(1) // Quick Regression Run
begin
$display(" ......................................................");
$display(" : :");
$display(" : Short Regression Run ... :");
$display(" :....................................................:");
pt10_rd;
pt01_wr;
pt01_rd;
pt10_wr;
sw_dma1(2);
sw_dma2(2);
hw_dma1(1);
hw_dma2(2);
hw_dma3(2);
hw_dma4(2);
arb_test1;
sw_ext_desc1(1);
end
else
begin
//
// TEST DEVELOPMENT AREA
//
sw_dma1(3);
//arb_test1;
repeat(100) @(posedge clk);
end
repeat(100) @(posedge clk);
$finish;
end
/////////////////////////////////////////////////////////////////////
//
// ack counter
//
always @(posedge clk)
if(ack_cnt_clr) ack_cnt <= #1 0;
else
if(wb0_ack_i | wb1_ack_i) ack_cnt <= #1 ack_cnt + 1;
/////////////////////////////////////////////////////////////////////
//
// Watchdog Counter
//
always @(posedge clk)
if(wb0_cyc_i | wb1_cyc_i | wb0_ack_i | wb1_ack_i) wd_cnt <= #1 0;
else wd_cnt <= #1 wd_cnt + 1;
always @(wd_cnt)
if(wd_cnt>5000)
begin
$display("\n\n*************************************\n");
$display("ERROR: Watch Dog Counter Expired\n");
$display("*************************************\n\n\n");
$finish;
end
always #5 clk = ~clk;
/////////////////////////////////////////////////////////////////////
//
// WISHBONE DMA IP Core
//
// Module Prototype
wb_dma_top
#( 4'hb, // register file address
2'd1, // Number of priorities (4)
`CH_COUNT, // Number of channels
4'hf,
4'hf,
4'hf,
4'hf,
4'hf,
4'hf,
4'hf,
4'hf
)
u0(
.clk_i( clk ),
.rst_i( rst ),
.wb0s_data_i( wb0s_data_i ),
.wb0s_data_o( wb0s_data_o ),
.wb0_addr_i( wb0_addr_i ),
.wb0_sel_i( wb0_sel_i ),
.wb0_we_i( wb0_we_i ),
.wb0_cyc_i( wb0_cyc_i ),
.wb0_stb_i( wb0_stb_i ),
.wb0_ack_o( wb0_ack_o ),
.wb0_err_o( wb0_err_o ),
.wb0_rty_o( wb0_rty_o ),
.wb0m_data_i( wb0m_data_i ),
.wb0m_data_o( wb0m_data_o ),
.wb0_addr_o( wb0_addr_o ),
.wb0_sel_o( wb0_sel_o ),
.wb0_we_o( wb0_we_o ),
.wb0_cyc_o( wb0_cyc_o ),
.wb0_stb_o( wb0_stb_o ),
.wb0_ack_i( wb0_ack_i ),
.wb0_err_i( wb0_err_i ),
.wb0_rty_i( wb0_rty_i ),
.wb1s_data_i( wb1s_data_i ),
.wb1s_data_o( wb1s_data_o ),
.wb1_addr_i( wb1_addr_i ),
.wb1_sel_i( wb1_sel_i ),
.wb1_we_i( wb1_we_i ),
.wb1_cyc_i( wb1_cyc_i ),
.wb1_stb_i( wb1_stb_i ),
.wb1_ack_o( wb1_ack_o ),
.wb1_err_o( wb1_err_o ),
.wb1_rty_o( wb1_rty_o ),
.wb1m_data_i( wb1m_data_i ),
.wb1m_data_o( wb1m_data_o ),
.wb1_addr_o( wb1_addr_o ),
.wb1_sel_o( wb1_sel_o ),
.wb1_we_o( wb1_we_o ),
.wb1_cyc_o( wb1_cyc_o ),
.wb1_stb_o( wb1_stb_o ),
.wb1_ack_i( wb1_ack_i ),
.wb1_err_i( wb1_err_i ),
.wb1_rty_i( wb1_rty_i ),
.dma_req_i( req_i ),
.dma_ack_o( ack_o ),
.dma_nd_i( nd_i ),
.dma_rest_i( rest_i ),
.inta_o( inta_o ),
.intb_o( intb_o )
);
wb_slv #(14) s0(
.clk( clk ),
.rst( ~rst ),
.adr( wb0_addr_o ),
.din( wb0s_data_o ),
.dout( wb0s_data_i ),
.cyc( wb0_cyc_o ),
.stb( wb0_stb_o ),
.sel( wb0_sel_o ),
.we( wb0_we_o ),
.ack( wb0_ack_i ),
.err( wb0_err_i ),
.rty( wb0_rty_i )
);
wb_slv #(14) s1(
.clk( clk ),
.rst( ~rst ),
.adr( wb1_addr_o ),
.din( wb1s_data_o ),
.dout( wb1s_data_i ),
.cyc( wb1_cyc_o ),
.stb( wb1_stb_o ),
.sel( wb1_sel_o ),
.we( wb1_we_o ),
.ack( wb1_ack_i ),
.err( wb1_err_i ),
.rty( wb1_rty_i )
);
wb_mast m0(
.clk( clk ),
.rst( ~rst ),
.adr( wb0_addr_i ),
.din( wb0m_data_o ),
.dout( wb0m_data_i ),
.cyc( wb0_cyc_i ),
.stb( wb0_stb_i ),
.sel( wb0_sel_i ),
.we( wb0_we_i ),
.ack( wb0_ack_o ),
.err( wb0_err_o ),
.rty( wb0_rty_o )
);
wb_mast m1(
.clk( clk ),
.rst( ~rst ),
.adr( wb1_addr_i ),
.din( wb1m_data_o ),
.dout( wb1m_data_i ),
.cyc( wb1_cyc_i ),
.stb( wb1_stb_i ),
.sel( wb1_sel_i ),
.we( wb1_we_i ),
.ack( wb1_ack_o ),
.err( wb1_err_o ),
.rty( wb1_rty_o )
);
`include "tests.v"
endmodule
|
module top();
// Inputs are registered
reg A_N;
reg B;
reg C;
reg D;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A_N = 1'bX;
B = 1'bX;
C = 1'bX;
D = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A_N = 1'b0;
#40 B = 1'b0;
#60 C = 1'b0;
#80 D = 1'b0;
#100 VGND = 1'b0;
#120 VNB = 1'b0;
#140 VPB = 1'b0;
#160 VPWR = 1'b0;
#180 A_N = 1'b1;
#200 B = 1'b1;
#220 C = 1'b1;
#240 D = 1'b1;
#260 VGND = 1'b1;
#280 VNB = 1'b1;
#300 VPB = 1'b1;
#320 VPWR = 1'b1;
#340 A_N = 1'b0;
#360 B = 1'b0;
#380 C = 1'b0;
#400 D = 1'b0;
#420 VGND = 1'b0;
#440 VNB = 1'b0;
#460 VPB = 1'b0;
#480 VPWR = 1'b0;
#500 VPWR = 1'b1;
#520 VPB = 1'b1;
#540 VNB = 1'b1;
#560 VGND = 1'b1;
#580 D = 1'b1;
#600 C = 1'b1;
#620 B = 1'b1;
#640 A_N = 1'b1;
#660 VPWR = 1'bx;
#680 VPB = 1'bx;
#700 VNB = 1'bx;
#720 VGND = 1'bx;
#740 D = 1'bx;
#760 C = 1'bx;
#780 B = 1'bx;
#800 A_N = 1'bx;
end
sky130_fd_sc_lp__and4b dut (.A_N(A_N), .B(B), .C(C), .D(D), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
|
module soc_system (
button_pio_external_connection_export,
clk_clk,
dipsw_pio_external_connection_export,
hps_0_h2f_reset_reset_n,
hps_0_hps_io_hps_io_emac1_inst_TX_CLK,
hps_0_hps_io_hps_io_emac1_inst_TXD0,
hps_0_hps_io_hps_io_emac1_inst_TXD1,
hps_0_hps_io_hps_io_emac1_inst_TXD2,
hps_0_hps_io_hps_io_emac1_inst_TXD3,
hps_0_hps_io_hps_io_emac1_inst_RXD0,
hps_0_hps_io_hps_io_emac1_inst_MDIO,
hps_0_hps_io_hps_io_emac1_inst_MDC,
hps_0_hps_io_hps_io_emac1_inst_RX_CTL,
hps_0_hps_io_hps_io_emac1_inst_TX_CTL,
hps_0_hps_io_hps_io_emac1_inst_RX_CLK,
hps_0_hps_io_hps_io_emac1_inst_RXD1,
hps_0_hps_io_hps_io_emac1_inst_RXD2,
hps_0_hps_io_hps_io_emac1_inst_RXD3,
hps_0_hps_io_hps_io_sdio_inst_CMD,
hps_0_hps_io_hps_io_sdio_inst_D0,
hps_0_hps_io_hps_io_sdio_inst_D1,
hps_0_hps_io_hps_io_sdio_inst_CLK,
hps_0_hps_io_hps_io_sdio_inst_D2,
hps_0_hps_io_hps_io_sdio_inst_D3,
hps_0_hps_io_hps_io_usb1_inst_D0,
hps_0_hps_io_hps_io_usb1_inst_D1,
hps_0_hps_io_hps_io_usb1_inst_D2,
hps_0_hps_io_hps_io_usb1_inst_D3,
hps_0_hps_io_hps_io_usb1_inst_D4,
hps_0_hps_io_hps_io_usb1_inst_D5,
hps_0_hps_io_hps_io_usb1_inst_D6,
hps_0_hps_io_hps_io_usb1_inst_D7,
hps_0_hps_io_hps_io_usb1_inst_CLK,
hps_0_hps_io_hps_io_usb1_inst_STP,
hps_0_hps_io_hps_io_usb1_inst_DIR,
hps_0_hps_io_hps_io_usb1_inst_NXT,
hps_0_hps_io_hps_io_spim1_inst_CLK,
hps_0_hps_io_hps_io_spim1_inst_MOSI,
hps_0_hps_io_hps_io_spim1_inst_MISO,
hps_0_hps_io_hps_io_spim1_inst_SS0,
hps_0_hps_io_hps_io_uart0_inst_RX,
hps_0_hps_io_hps_io_uart0_inst_TX,
hps_0_hps_io_hps_io_i2c0_inst_SDA,
hps_0_hps_io_hps_io_i2c0_inst_SCL,
hps_0_hps_io_hps_io_i2c1_inst_SDA,
hps_0_hps_io_hps_io_i2c1_inst_SCL,
hps_0_hps_io_hps_io_gpio_inst_GPIO09,
hps_0_hps_io_hps_io_gpio_inst_GPIO35,
hps_0_hps_io_hps_io_gpio_inst_GPIO40,
hps_0_hps_io_hps_io_gpio_inst_GPIO53,
hps_0_hps_io_hps_io_gpio_inst_GPIO54,
hps_0_hps_io_hps_io_gpio_inst_GPIO61,
led_pio_external_connection_export,
memory_mem_a,
memory_mem_ba,
memory_mem_ck,
memory_mem_ck_n,
memory_mem_cke,
memory_mem_cs_n,
memory_mem_ras_n,
memory_mem_cas_n,
memory_mem_we_n,
memory_mem_reset_n,
memory_mem_dq,
memory_mem_dqs,
memory_mem_dqs_n,
memory_mem_odt,
memory_mem_dm,
memory_oct_rzqin,
reset_reset_n);
input [3:0] button_pio_external_connection_export;
input clk_clk;
input [3:0] dipsw_pio_external_connection_export;
output hps_0_h2f_reset_reset_n;
output hps_0_hps_io_hps_io_emac1_inst_TX_CLK;
output hps_0_hps_io_hps_io_emac1_inst_TXD0;
output hps_0_hps_io_hps_io_emac1_inst_TXD1;
output hps_0_hps_io_hps_io_emac1_inst_TXD2;
output hps_0_hps_io_hps_io_emac1_inst_TXD3;
input hps_0_hps_io_hps_io_emac1_inst_RXD0;
inout hps_0_hps_io_hps_io_emac1_inst_MDIO;
output hps_0_hps_io_hps_io_emac1_inst_MDC;
input hps_0_hps_io_hps_io_emac1_inst_RX_CTL;
output hps_0_hps_io_hps_io_emac1_inst_TX_CTL;
input hps_0_hps_io_hps_io_emac1_inst_RX_CLK;
input hps_0_hps_io_hps_io_emac1_inst_RXD1;
input hps_0_hps_io_hps_io_emac1_inst_RXD2;
input hps_0_hps_io_hps_io_emac1_inst_RXD3;
inout hps_0_hps_io_hps_io_sdio_inst_CMD;
inout hps_0_hps_io_hps_io_sdio_inst_D0;
inout hps_0_hps_io_hps_io_sdio_inst_D1;
output hps_0_hps_io_hps_io_sdio_inst_CLK;
inout hps_0_hps_io_hps_io_sdio_inst_D2;
inout hps_0_hps_io_hps_io_sdio_inst_D3;
inout hps_0_hps_io_hps_io_usb1_inst_D0;
inout hps_0_hps_io_hps_io_usb1_inst_D1;
inout hps_0_hps_io_hps_io_usb1_inst_D2;
inout hps_0_hps_io_hps_io_usb1_inst_D3;
inout hps_0_hps_io_hps_io_usb1_inst_D4;
inout hps_0_hps_io_hps_io_usb1_inst_D5;
inout hps_0_hps_io_hps_io_usb1_inst_D6;
inout hps_0_hps_io_hps_io_usb1_inst_D7;
input hps_0_hps_io_hps_io_usb1_inst_CLK;
output hps_0_hps_io_hps_io_usb1_inst_STP;
input hps_0_hps_io_hps_io_usb1_inst_DIR;
input hps_0_hps_io_hps_io_usb1_inst_NXT;
output hps_0_hps_io_hps_io_spim1_inst_CLK;
output hps_0_hps_io_hps_io_spim1_inst_MOSI;
input hps_0_hps_io_hps_io_spim1_inst_MISO;
output hps_0_hps_io_hps_io_spim1_inst_SS0;
input hps_0_hps_io_hps_io_uart0_inst_RX;
output hps_0_hps_io_hps_io_uart0_inst_TX;
inout hps_0_hps_io_hps_io_i2c0_inst_SDA;
inout hps_0_hps_io_hps_io_i2c0_inst_SCL;
inout hps_0_hps_io_hps_io_i2c1_inst_SDA;
inout hps_0_hps_io_hps_io_i2c1_inst_SCL;
inout hps_0_hps_io_hps_io_gpio_inst_GPIO09;
inout hps_0_hps_io_hps_io_gpio_inst_GPIO35;
inout hps_0_hps_io_hps_io_gpio_inst_GPIO40;
inout hps_0_hps_io_hps_io_gpio_inst_GPIO53;
inout hps_0_hps_io_hps_io_gpio_inst_GPIO54;
inout hps_0_hps_io_hps_io_gpio_inst_GPIO61;
output [7:0] led_pio_external_connection_export;
output [14:0] memory_mem_a;
output [2:0] memory_mem_ba;
output memory_mem_ck;
output memory_mem_ck_n;
output memory_mem_cke;
output memory_mem_cs_n;
output memory_mem_ras_n;
output memory_mem_cas_n;
output memory_mem_we_n;
output memory_mem_reset_n;
inout [31:0] memory_mem_dq;
inout [3:0] memory_mem_dqs;
inout [3:0] memory_mem_dqs_n;
output memory_mem_odt;
output [3:0] memory_mem_dm;
input memory_oct_rzqin;
input reset_reset_n;
endmodule
|
module IDEX_Reg (
input clk,
input flush,
input stall,
input [5-1:0] EX_ctrl_i,
output [5-1:0] EX_ctrl_o,
input [2-1:0] MEM_ctrl_i,
output [2-1:0] MEM_ctrl_o,
input [2-1:0] WB_ctrl_i,
output [2-1:0] WB_ctrl_o,
input [32-1:0] Rs_data_i,
output [32-1:0] Rs_data_o,
input [32-1:0] Rt_data_i,
output [32-1:0] Rt_data_o,
input [32-1:0] imm_data_i,
output [32-1:0] imm_data_o,
input [5-1:0] Rs_i,
output [5-1:0] Rs_o,
input [5-1:0] Rt_i,
output [5-1:0] Rt_o,
input [5-1:0] Rd_i,
output [5-1:0] Rd_o
);
Latch #(.width(5)) IDEX_EX_ctrl (
.clk (clk),
.rst (~flush),
.we (~stall),
.data_i (EX_ctrl_i),
.data_o (EX_ctrl_o)
);
Latch #(.width(2)) IDEX_MEM_ctrl (
.clk (clk),
.rst (~flush),
.we (~stall),
.data_i (MEM_ctrl_i),
.data_o (MEM_ctrl_o)
);
Latch #(.width(2)) IDEX_WB_ctrl (
.clk (clk),
.rst (~flush),
.we (~stall),
.data_i (WB_ctrl_i),
.data_o (WB_ctrl_o)
);
Latch IDEX_Rs_data (
.clk (clk),
.rst (~flush),
.we (~stall),
.data_i (Rs_data_i),
.data_o (Rs_data_o)
);
Latch IDEX_Rt_data (
.clk (clk),
.rst (~flush),
.we (~stall),
.data_i (Rt_data_i),
.data_o (Rt_data_o)
);
Latch IDEX_imm_data (
.clk (clk),
.rst (~flush),
.we (~stall),
.data_i (imm_data_i),
.data_o (imm_data_o)
);
Latch #(.width(5)) IDEX_Rs (
.clk (clk),
.rst (~flush),
.we (~stall),
.data_i (Rs_i),
.data_o (Rs_o)
);
Latch #(.width(5)) IDEX_Rt (
.clk (clk),
.rst (~flush),
.we (~stall),
.data_i (Rt_i),
.data_o (Rt_o)
);
Latch #(.width(5)) IDEX_Rd (
.clk (clk),
.rst (~flush),
.we (~stall),
.data_i (Rd_i),
.data_o (Rd_o)
);
endmodule
|
module sky130_fd_sc_hvl__einvp (
//# {{data|Data Signals}}
input A ,
output Z ,
//# {{control|Control Signals}}
input TE ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
|
module softusb_sie(
input usb_clk,
input usb_rst,
input io_re,
input io_we,
input [5:0] io_a,
input [7:0] io_di,
output reg [7:0] io_do,
output usba_spd,
output usba_oe_n,
input usba_rcv,
inout usba_vp,
inout usba_vm,
output usbb_spd,
output usbb_oe_n,
input usbb_rcv,
inout usbb_vp,
inout usbb_vm
);
wire [1:0] line_state_a;
wire [1:0] line_state_b;
wire discon_a;
wire discon_b;
reg port_sel_rx;
reg [1:0] port_sel_tx;
reg [7:0] tx_data;
reg tx_valid;
wire tx_ready;
reg tx_pending;
reg [1:0] generate_reset;
wire [7:0] rx_data;
wire rx_valid;
wire rx_active;
wire tx_busy;
reg [7:0] data_in;
reg rx_pending;
reg tx_low_speed;
reg [1:0] low_speed;
reg generate_eop;
always @(posedge usb_clk) begin
if(usb_rst) begin
port_sel_rx <= 1'b0;
port_sel_tx <= 2'b00;
tx_valid <= 1'b0;
tx_pending <= 1'b0;
generate_reset <= 2'd0;
rx_pending <= 1'b0;
tx_low_speed <= 1'b0;
low_speed <= 2'b00;
generate_eop <= 1'b0;
io_do <= 8'd0;
end else begin
io_do <= 8'd0;
generate_eop <= 1'b0;
case(io_a)
6'h00: io_do <= line_state_a;
6'h01: io_do <= line_state_b;
6'h02: io_do <= discon_a;
6'h03: io_do <= discon_b;
6'h04: io_do <= port_sel_rx;
6'h05: io_do <= port_sel_tx;
6'h06: io_do <= tx_data;
6'h07: io_do <= tx_pending;
6'h08: io_do <= tx_valid;
6'h09: io_do <= tx_busy;
6'h0a: io_do <= generate_reset;
6'h0b: begin
io_do <= data_in;
if(io_re)
rx_pending <= 1'b0;
end
6'h0c: io_do <= rx_pending;
6'h0d: io_do <= rx_active;
6'h0e: io_do <= tx_low_speed;
6'h0f: io_do <= low_speed;
6'h10: io_do <= 8'hxx;
endcase
if(io_we) begin
$display("USB SIE W: a=%x dat=%x", io_a, io_di);
case(io_a)
6'h04: port_sel_rx <= io_di[0];
6'h05: port_sel_tx <= io_di[1:0];
6'h06: begin
tx_valid <= 1'b1;
tx_data <= io_di;
tx_pending <= 1'b1;
end
6'h08: tx_valid <= 1'b0;
6'h0a: generate_reset <= io_di[1:0];
6'h0e: tx_low_speed <= io_di[0];
6'h0f: low_speed <= io_di[1:0];
6'h10: generate_eop <= 1'b1;
endcase
end
if(tx_ready)
tx_pending <= 1'b0;
if(rx_valid) begin
data_in <= rx_data;
rx_pending <= 1'b1;
end
if(io_re) // must be at the end because of the delay!
#1 $display("USB SIE R: a=%x dat=%x", io_a, io_do);
end
end
softusb_phy phy(
.usb_clk(usb_clk),
.usb_rst(usb_rst),
.usba_spd(usba_spd),
.usba_oe_n(usba_oe_n),
.usba_rcv(usba_rcv),
.usba_vp(usba_vp),
.usba_vm(usba_vm),
.usbb_spd(usbb_spd),
.usbb_oe_n(usbb_oe_n),
.usbb_rcv(usbb_rcv),
.usbb_vp(usbb_vp),
.usbb_vm(usbb_vm),
.usba_discon(discon_a),
.usbb_discon(discon_b),
.line_state_a(line_state_a),
.line_state_b(line_state_b),
.port_sel_rx(port_sel_rx),
.port_sel_tx(port_sel_tx),
.tx_data(tx_data),
.tx_valid(tx_valid),
.tx_ready(tx_ready),
.tx_busy(tx_busy),
.generate_reset(generate_reset),
.rx_data(rx_data),
.rx_valid(rx_valid),
.rx_active(rx_active),
.tx_low_speed(tx_low_speed),
.low_speed(low_speed),
.generate_eop(generate_eop)
);
endmodule
|
module cf_adc_if (
// adc interface (clk, data, over-range)
adc_clk_in,
adc_data_in,
adc_or_in,
// interface outputs
adc_clk,
adc_data,
adc_or,
// processor control signals
up_delay_sel,
up_delay_rwn,
up_delay_addr,
up_delay_wdata,
// delay control signals
delay_clk,
delay_ack,
delay_rdata,
delay_locked);
// This parameter controls the buffer type based on the target device.
parameter C_CF_BUFTYPE = 0;
parameter C_CF_7SERIES = 0;
parameter C_CF_VIRTEX6 = 1;
// adc interface (clk, data, over-range)
input adc_clk_in;
input [13:0] adc_data_in;
input adc_or_in;
// interface outputs
output adc_clk;
output [13:0] adc_data;
output adc_or;
// processor control signals
input up_delay_sel;
input up_delay_rwn;
input [ 3:0] up_delay_addr;
input [ 4:0] up_delay_wdata;
// delay control signals
input delay_clk;
output delay_ack;
output [ 4:0] delay_rdata;
output delay_locked;
reg [13:0] adc_data = 'd0;
reg adc_or_d = 'd0;
reg [ 4:0] adc_or_count = 'd0;
reg adc_or = 'd0;
reg [ 7:0] delay_rst_cnt = 'd0;
reg delay_sel_m1 = 'd0;
reg delay_sel_m2 = 'd0;
reg delay_sel_m3 = 'd0;
reg delay_sel = 'd0;
reg delay_rwn = 'd0;
reg [ 3:0] delay_addr = 'd0;
reg [ 4:0] delay_wdata = 'd0;
reg [14:0] delay_ld = 'd0;
reg delay_sel_d = 'd0;
reg delay_sel_2d = 'd0;
reg delay_sel_3d = 'd0;
reg delay_ack = 'd0;
reg [ 4:0] delay_rdata = 'd0;
reg delay_locked = 'd0;
wire delay_preset_s;
wire delay_rst_s;
wire [ 4:0] delay_rdata_s[14:0];
wire delay_locked_s;
wire [13:0] adc_data_ibuf_s;
wire [13:0] adc_data_idelay_s;
wire [13:0] adc_data_s;
wire adc_or_ibuf_s;
wire adc_or_idelay_s;
wire adc_or_s;
wire adc_clk_ibuf_s;
genvar l_inst;
always @(posedge adc_clk) begin
adc_data <= adc_data_s;
adc_or_d <= adc_or_s;
if (adc_or_d == 1'b1) begin
adc_or_count <= 5'h10;
end else if (adc_or_count[4] == 1'b1) begin
adc_or_count <= adc_or_count + 1'b1;
end
adc_or <= adc_or_count[4];
end
// The delay control interface, each delay element can be individually
// addressed, and a delay value can be directly loaded (no INC/DEC stuff)
always @(posedge delay_clk) begin
if ((delay_sel == 1'b1) && (delay_rwn == 1'b0) && (delay_addr == 4'hf)) begin
delay_rst_cnt <= 'd0;
end else if (delay_rst_cnt[7] == 1'b0) begin
delay_rst_cnt <= delay_rst_cnt + 1'b1;
end
delay_sel_m1 <= up_delay_sel;
delay_sel_m2 <= delay_sel_m1;
delay_sel_m3 <= delay_sel_m2;
delay_sel <= delay_sel_m2 & ~delay_sel_m3;
if ((delay_sel_m2 == 1'b1) && (delay_sel_m3 == 1'b0)) begin
delay_rwn <= up_delay_rwn;
delay_addr <= up_delay_addr;
delay_wdata <= up_delay_wdata[4:0];
end
if ((delay_sel == 1'b1) && (delay_rwn == 1'b0)) begin
case (delay_addr)
4'b1110: delay_ld <= 15'h4000;
4'b1101: delay_ld <= 15'h2000;
4'b1100: delay_ld <= 15'h1000;
4'b1011: delay_ld <= 15'h0800;
4'b1010: delay_ld <= 15'h0400;
4'b1001: delay_ld <= 15'h0200;
4'b1000: delay_ld <= 15'h0100;
4'b0111: delay_ld <= 15'h0080;
4'b0110: delay_ld <= 15'h0040;
4'b0101: delay_ld <= 15'h0020;
4'b0100: delay_ld <= 15'h0010;
4'b0011: delay_ld <= 15'h0008;
4'b0010: delay_ld <= 15'h0004;
4'b0001: delay_ld <= 15'h0002;
4'b0000: delay_ld <= 15'h0001;
default: delay_ld <= 15'h0000;
endcase
end else begin
delay_ld <= 15'h0000;
end
delay_sel_d <= delay_sel;
delay_sel_2d <= delay_sel_d;
delay_sel_3d <= delay_sel_2d;
if (delay_sel_3d == 1'b1) begin
delay_ack <= ~delay_ack;
end
case (delay_addr)
4'b1110: delay_rdata <= delay_rdata_s[14];
4'b1101: delay_rdata <= delay_rdata_s[13];
4'b1100: delay_rdata <= delay_rdata_s[12];
4'b1011: delay_rdata <= delay_rdata_s[11];
4'b1010: delay_rdata <= delay_rdata_s[10];
4'b1001: delay_rdata <= delay_rdata_s[ 9];
4'b1000: delay_rdata <= delay_rdata_s[ 8];
4'b0111: delay_rdata <= delay_rdata_s[ 7];
4'b0110: delay_rdata <= delay_rdata_s[ 6];
4'b0101: delay_rdata <= delay_rdata_s[ 5];
4'b0100: delay_rdata <= delay_rdata_s[ 4];
4'b0011: delay_rdata <= delay_rdata_s[ 3];
4'b0010: delay_rdata <= delay_rdata_s[ 2];
4'b0001: delay_rdata <= delay_rdata_s[ 1];
4'b0000: delay_rdata <= delay_rdata_s[ 0];
default: delay_rdata <= 5'd0;
endcase
delay_locked <= delay_locked_s;
end
// The delay elements need calibration from a delay controller and it needs a
// reset (it also asserts locked after the controller is up and running).
assign delay_preset_s = ~delay_rst_cnt[7];
FDPE #(.INIT(1'b1)) i_delayctrl_rst_reg (
.CE (1'b1),
.D (1'b0),
.PRE (delay_preset_s),
.C (delay_clk),
.Q (delay_rst_s));
// The data buffers -
generate
for (l_inst = 0; l_inst <= 13; l_inst = l_inst + 1) begin : g_adc_if
IBUF i_data_ibuf (
.I (adc_data_in[l_inst]),
.O (adc_data_ibuf_s[l_inst]));
(* IODELAY_GROUP = "adc_if_delay_group" *)
IDELAYE2 #(
.CINVCTRL_SEL ("FALSE"),
.DELAY_SRC ("IDATAIN"),
.HIGH_PERFORMANCE_MODE ("FALSE"),
.IDELAY_TYPE ("VAR_LOAD"),
.IDELAY_VALUE (0),
.REFCLK_FREQUENCY (200.0),
.PIPE_SEL ("FALSE"),
.SIGNAL_PATTERN ("DATA"))
i_data_idelay (
.CE (1'b0),
.INC (1'b0),
.DATAIN (1'b0),
.LDPIPEEN (1'b0),
.CINVCTRL (1'b0),
.REGRST (1'b0),
.C (delay_clk),
.IDATAIN (adc_data_ibuf_s[l_inst]),
.DATAOUT (adc_data_idelay_s[l_inst]),
.LD (delay_ld[l_inst]),
.CNTVALUEIN (delay_wdata),
.CNTVALUEOUT (delay_rdata_s[l_inst]));
(* IOB = "true" *)
FDRE i_data_reg (
.R (1'b0),
.CE (1'b1),
.C (adc_clk),
.D (adc_data_idelay_s[l_inst]),
.Q (adc_data_s[l_inst]));
end
endgenerate
// The or buffers -
IBUF i_or_ibuf (
.I (adc_or_in),
.O (adc_or_ibuf_s));
(* IODELAY_GROUP = "adc_if_delay_group" *)
IDELAYE2 #(
.CINVCTRL_SEL ("FALSE"),
.DELAY_SRC ("IDATAIN"),
.HIGH_PERFORMANCE_MODE ("FALSE"),
.IDELAY_TYPE ("VAR_LOAD"),
.IDELAY_VALUE (0),
.REFCLK_FREQUENCY (200.0),
.PIPE_SEL ("FALSE"),
.SIGNAL_PATTERN ("DATA"))
i_or_idelay (
.CE (1'b0),
.INC (1'b0),
.DATAIN (1'b0),
.LDPIPEEN (1'b0),
.CINVCTRL (1'b0),
.REGRST (1'b0),
.C (delay_clk),
.IDATAIN (adc_or_ibuf_s),
.DATAOUT (adc_or_idelay_s),
.LD (delay_ld[14]),
.CNTVALUEIN (delay_wdata),
.CNTVALUEOUT (delay_rdata_s[14]));
(* IOB = "true" *)
FDRE i_or_reg (
.R (1'b0),
.CE (1'b1),
.C (adc_clk),
.D (adc_or_idelay_s),
.Q (adc_or_s));
// The clock buffers -
IBUFG i_clk_ibuf (
.I (adc_clk_in),
.O (adc_clk_ibuf_s));
BUFG i_clk_gbuf (
.I (adc_clk_ibuf_s),
.O (adc_clk));
// The delay controller. Refer to Xilinx doc. for details.
// The GROUP directive controls which delay elements this is associated with.
(* IODELAY_GROUP = "adc_if_delay_group" *)
IDELAYCTRL i_delay_ctrl (
.RST (delay_rst_s),
.REFCLK (delay_clk),
.RDY (delay_locked_s));
endmodule
|
module aluparam_behav
#( parameter BITSIZE = 16)
( output [BITSIZE-1:0] Y,
output [15:0] flags,
input [BITSIZE-1:0] A,
input [BITSIZE-1:0] B,
input [3:0] sel
);
reg [BITSIZE-1:0] outreg;
reg [15:0] flagreg;
reg carry;
reg overflow;
reg trash;
always @(A, B, sel) begin
flagreg = 0;
carry = 0;
trash = 0;
overflow = 0;
case(sel)
4'b0000: begin
outreg = A ^ B;
end
4'b0010: begin
outreg = A ~^ B;
end
4'b1000: begin
outreg = A & B;
end
4'b1010: begin
outreg = A | B;
end
4'b0100: begin
{carry, outreg} = A + B;
overflow = (($signed(A) >= 0 && $signed(B) >= 0 && $signed(outreg) < 0) || ($signed(A) < 0 && $signed(B) < 0 && $signed(outreg) >= 0)) ? 1 : 0;
end
4'b0101: begin
{trash, outreg} = A + ~B + 1;
overflow = (($signed(A) >= 0 && $signed(B) < 0 && $signed(outreg) < 0) || ($signed(A) < 0 && $signed(B) >= 0 && $signed(outreg) >= 0)) ? 1 : 0;
end
4'b0111: begin
outreg = ~A;
end
default: begin
outreg = 0;
flagreg = 0;
end
endcase
flagreg[0] = carry; // Carry
flagreg[2] = (A < B) && (sel == 4'b0101); // Low
flagreg[5] = overflow; // Overflow
flagreg[6] = (outreg == 16'b0); // Zero Flag
flagreg[7] = outreg[BITSIZE-1]; // Negative (Sign) Flag
end
assign Y = outreg;
assign flags = flagreg;
endmodule
|
module top();
// Inputs are registered
reg D;
reg VPWR;
reg VGND;
// Outputs are wires
wire Q;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
VGND = 1'bX;
VPWR = 1'bX;
#20 D = 1'b0;
#40 VGND = 1'b0;
#60 VPWR = 1'b0;
#80 D = 1'b1;
#100 VGND = 1'b1;
#120 VPWR = 1'b1;
#140 D = 1'b0;
#160 VGND = 1'b0;
#180 VPWR = 1'b0;
#200 VPWR = 1'b1;
#220 VGND = 1'b1;
#240 D = 1'b1;
#260 VPWR = 1'bx;
#280 VGND = 1'bx;
#300 D = 1'bx;
end
// Create a clock
reg CLK;
initial
begin
CLK = 1'b0;
end
always
begin
#5 CLK = ~CLK;
end
sky130_fd_sc_hs__dfxtp dut (.D(D), .VPWR(VPWR), .VGND(VGND), .Q(Q), .CLK(CLK));
endmodule
|
module vga_stripes(
VIDON,
HC,
VC,
R,
G,
B,
SW
);
// |--------------------|
// | Port Declarations |
// | -------------------|
input VIDON;
input [9:0] HC;
input [9:0] VC;
output [7:0] R;
output [7:0] G;
output [7:0] B;
input [17:0] SW;
// |---------------------|
// | Signal Declarations |
// | --------------------|
reg [7:0] Rr, Gg, Bb;
assign R = Rr;
assign G = Gg;
assign B = Bb;
always @ (VIDON, VC)
begin
Rr <= 8'b00000000;
Gg <= 8'b00000000;
Bb <= 8'b00000000;
if( VIDON == 1'b1 )
begin
/*if (VC > 400) begin
Bb <= 0;
Rr <= 233;
Gg <= 0;
end
else if (VC > 300 && VC < 400)begin
Bb <= 0;
Rr <= 0;
Gg <= 244;
end
else if (VC > 200 && VC < 300)begin
Bb <= 254;
Rr <= 0;
Gg <= 0;
end
else begin
Bb <= 0;
Rr <= 0;
Gg <= 0;
end*/
/*if( (VC > 250 && VC < 350) && (HC > 450 && HC < 550 ))
begin
/* Switch-Color test. Works!
Rr <= SW[17:10];
Bb <= SW[9:2];
Gg[1:0] <= {SW[1:0],1'b0,1'b0,1'b0,1'b0,1'b0,1'b0};
end*/
Gg <= VC;
Rr <= HC;
Bb <= VC;
end
end
endmodule
|
module sky130_fd_sc_hs__o2bb2a (
//# {{data|Data Signals}}
input A1_N,
input A2_N,
input B1 ,
input B2 ,
output X ,
//# {{power|Power}}
input VPWR,
input VGND
);
endmodule
|
module RAM64M #(
`ifdef XIL_TIMING
parameter LOC = "UNPLACED",
`endif
parameter [63:0] INIT_A = 64'h0000000000000000,
parameter [63:0] INIT_B = 64'h0000000000000000,
parameter [63:0] INIT_C = 64'h0000000000000000,
parameter [63:0] INIT_D = 64'h0000000000000000,
parameter [0:0] IS_WCLK_INVERTED = 1'b0
)(
output DOA,
output DOB,
output DOC,
output DOD,
input [5:0] ADDRA,
input [5:0] ADDRB,
input [5:0] ADDRC,
input [5:0] ADDRD,
input DIA,
input DIB,
input DIC,
input DID,
input WCLK,
input WE
);
// define constants
localparam MODULE_NAME = "RAM64M";
reg trig_attr = 1'b0;
`ifdef XIL_ATTR_TEST
reg attr_test = 1'b1;
`else
reg attr_test = 1'b0;
`endif
reg attr_err = 1'b0;
wire IS_WCLK_INVERTED_BIN;
wire [5:0] ADDRD_in;
wire DIA_in;
wire DIB_in;
wire DIC_in;
wire DID_in;
wire WCLK_in;
wire WE_in;
`ifdef XIL_TIMING
wire [5:0] ADDRD_dly;
wire DIA_dly;
wire DIB_dly;
wire DIC_dly;
wire DID_dly;
wire WCLK_dly;
wire WE_dly;
reg notifier;
wire sh_clk_en_p;
wire sh_clk_en_n;
wire sh_we_clk_en_p;
wire sh_we_clk_en_n;
assign ADDRD_in = ADDRD_dly;
assign DIA_in = DIA_dly;
assign DIB_in = DIB_dly;
assign DIC_in = DIC_dly;
assign DID_in = DID_dly;
assign WCLK_in = WCLK_dly ^ IS_WCLK_INVERTED_BIN;
assign WE_in = (WE === 1'bz) || WE_dly; // rv 1
`else
assign ADDRD_in = ADDRD;
assign DIA_in = DIA;
assign DIB_in = DIB;
assign DIC_in = DIC;
assign DID_in = DID;
assign WCLK_in = WCLK ^ IS_WCLK_INVERTED_BIN;
assign WE_in = (WE === 1'bz) || WE; // rv 1
`endif
assign IS_WCLK_INVERTED_BIN = IS_WCLK_INVERTED;
initial begin
#1;
trig_attr = ~trig_attr;
end
always @ (trig_attr) begin
#1;
if ((attr_test == 1'b1) ||
((INIT_A < 64'h0000000000000000) || (INIT_A > 64'hFFFFFFFFFFFFFFFF))) begin
$display("Error: [Unisim %s-101] INIT_A attribute is set to %h. Legal values for this attribute are 64'h0000000000000000 to 64'hFFFFFFFFFFFFFFFF. Instance: %m", MODULE_NAME, INIT_A);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((INIT_B < 64'h0000000000000000) || (INIT_B > 64'hFFFFFFFFFFFFFFFF))) begin
$display("Error: [Unisim %s-102] INIT_B attribute is set to %h. Legal values for this attribute are 64'h0000000000000000 to 64'hFFFFFFFFFFFFFFFF. Instance: %m", MODULE_NAME, INIT_B);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((INIT_C < 64'h0000000000000000) || (INIT_C > 64'hFFFFFFFFFFFFFFFF))) begin
$display("Error: [Unisim %s-103] INIT_C attribute is set to %h. Legal values for this attribute are 64'h0000000000000000 to 64'hFFFFFFFFFFFFFFFF. Instance: %m", MODULE_NAME, INIT_C);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((INIT_D < 64'h0000000000000000) || (INIT_D > 64'hFFFFFFFFFFFFFFFF))) begin
$display("Error: [Unisim %s-104] INIT_D attribute is set to %h. Legal values for this attribute are 64'h0000000000000000 to 64'hFFFFFFFFFFFFFFFF. Instance: %m", MODULE_NAME, INIT_D);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((IS_WCLK_INVERTED !== 1'b0) && (IS_WCLK_INVERTED !== 1'b1))) begin
$display("Error: [Unisim %s-109] IS_WCLK_INVERTED attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, IS_WCLK_INVERTED);
attr_err = 1'b1;
end
if (attr_err == 1'b1) #1 $finish;
end
reg [63:0] mem_a, mem_b, mem_c, mem_d;
initial begin
mem_a = INIT_A;
mem_b = INIT_B;
mem_c = INIT_C;
mem_d = INIT_D;
end
always @(posedge WCLK_in)
if (WE_in) begin
mem_a[ADDRD_in] <= #100 DIA_in;
mem_b[ADDRD_in] <= #100 DIB_in;
mem_c[ADDRD_in] <= #100 DIC_in;
mem_d[ADDRD_in] <= #100 DID_in;
end
assign DOA = mem_a[ADDRA];
assign DOB = mem_b[ADDRB];
assign DOC = mem_c[ADDRC];
assign DOD = mem_d[ADDRD_in];
`ifdef XIL_TIMING
always @(notifier) begin
mem_a[ADDRD_in] <= 1'bx;
mem_b[ADDRD_in] <= 1'bx;
mem_c[ADDRD_in] <= 1'bx;
mem_d[ADDRD_in] <= 1'bx;
end
assign sh_clk_en_p = ~IS_WCLK_INVERTED_BIN;
assign sh_clk_en_n = IS_WCLK_INVERTED_BIN;
assign sh_we_clk_en_p = WE_in && ~IS_WCLK_INVERTED_BIN;
assign sh_we_clk_en_n = WE_in && IS_WCLK_INVERTED_BIN;
specify
(WCLK => DOA) = (0:0:0, 0:0:0);
(WCLK => DOB) = (0:0:0, 0:0:0);
(WCLK => DOC) = (0:0:0, 0:0:0);
(WCLK => DOD) = (0:0:0, 0:0:0);
(ADDRA *> DOA) = (0:0:0, 0:0:0);
(ADDRB *> DOB) = (0:0:0, 0:0:0);
(ADDRC *> DOC) = (0:0:0, 0:0:0);
(ADDRD *> DOD) = (0:0:0, 0:0:0);
$period (negedge WCLK &&& WE, 0:0:0, notifier);
$period (posedge WCLK &&& WE, 0:0:0, notifier);
$setuphold (negedge WCLK, negedge ADDRD[0], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,ADDRD_dly[0]);
$setuphold (negedge WCLK, negedge ADDRD[1], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,ADDRD_dly[1]);
$setuphold (negedge WCLK, negedge ADDRD[2], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,ADDRD_dly[2]);
$setuphold (negedge WCLK, negedge ADDRD[3], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,ADDRD_dly[3]);
$setuphold (negedge WCLK, negedge ADDRD[4], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,ADDRD_dly[4]);
$setuphold (negedge WCLK, negedge ADDRD[5], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,ADDRD_dly[5]);
$setuphold (negedge WCLK, negedge DIA, 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,DIA_dly);
$setuphold (negedge WCLK, negedge DIB, 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,DIB_dly);
$setuphold (negedge WCLK, negedge DIC, 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,DIC_dly);
$setuphold (negedge WCLK, negedge DID, 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,DID_dly);
$setuphold (negedge WCLK, negedge WE, 0:0:0, 0:0:0, notifier,sh_clk_en_n,sh_clk_en_n,WCLK_dly,WE_dly);
$setuphold (negedge WCLK, posedge ADDRD[0], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,ADDRD_dly[0]);
$setuphold (negedge WCLK, posedge ADDRD[1], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,ADDRD_dly[1]);
$setuphold (negedge WCLK, posedge ADDRD[2], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,ADDRD_dly[2]);
$setuphold (negedge WCLK, posedge ADDRD[3], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,ADDRD_dly[3]);
$setuphold (negedge WCLK, posedge ADDRD[4], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,ADDRD_dly[4]);
$setuphold (negedge WCLK, posedge ADDRD[5], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,ADDRD_dly[5]);
$setuphold (negedge WCLK, posedge DIA, 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,DIA_dly);
$setuphold (negedge WCLK, posedge DIB, 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,DIB_dly);
$setuphold (negedge WCLK, posedge DIC, 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,DIC_dly);
$setuphold (negedge WCLK, posedge DID, 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,DID_dly);
$setuphold (negedge WCLK, posedge WE, 0:0:0, 0:0:0, notifier,sh_clk_en_n,sh_clk_en_n,WCLK_dly,WE_dly);
$setuphold (posedge WCLK, negedge ADDRD[0], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,ADDRD_dly[0]);
$setuphold (posedge WCLK, negedge ADDRD[1], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,ADDRD_dly[1]);
$setuphold (posedge WCLK, negedge ADDRD[2], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,ADDRD_dly[2]);
$setuphold (posedge WCLK, negedge ADDRD[3], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,ADDRD_dly[3]);
$setuphold (posedge WCLK, negedge ADDRD[4], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,ADDRD_dly[4]);
$setuphold (posedge WCLK, negedge ADDRD[5], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,ADDRD_dly[5]);
$setuphold (posedge WCLK, negedge DIA, 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,DIA_dly);
$setuphold (posedge WCLK, negedge DIB, 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,DIB_dly);
$setuphold (posedge WCLK, negedge DIC, 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,DIC_dly);
$setuphold (posedge WCLK, negedge DID, 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,DID_dly);
$setuphold (posedge WCLK, negedge WE, 0:0:0, 0:0:0, notifier,sh_clk_en_p,sh_clk_en_p,WCLK_dly,WE_dly);
$setuphold (posedge WCLK, posedge ADDRD[0], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,ADDRD_dly[0]);
$setuphold (posedge WCLK, posedge ADDRD[1], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,ADDRD_dly[1]);
$setuphold (posedge WCLK, posedge ADDRD[2], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,ADDRD_dly[2]);
$setuphold (posedge WCLK, posedge ADDRD[3], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,ADDRD_dly[3]);
$setuphold (posedge WCLK, posedge ADDRD[4], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,ADDRD_dly[4]);
$setuphold (posedge WCLK, posedge ADDRD[5], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,ADDRD_dly[5]);
$setuphold (posedge WCLK, posedge DIA, 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,DIA_dly);
$setuphold (posedge WCLK, posedge DIB, 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,DIB_dly);
$setuphold (posedge WCLK, posedge DIC, 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,DIC_dly);
$setuphold (posedge WCLK, posedge DID, 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,DID_dly);
$setuphold (posedge WCLK, posedge WE, 0:0:0, 0:0:0, notifier,sh_clk_en_p,sh_clk_en_p,WCLK_dly,WE_dly);
specparam PATHPULSE$ = 0;
endspecify
`endif
endmodule
|
module EtherPBI(
inout tri [15:0] SysAddr,
input wire Phi2,
// 28Mhz (phi2 times 16)
input wire CLK1,
// ignored for now
input wire CLK2,
// always 1
output wire S0,
// always 0
output wire S1,
output tri MPD,
inout tri RdWr,
output wire OE,
output wire RamCS,
output wire RomCS,
// Addr 0-9 on W5300; bank address 0-4 on RAM and 0-7 on ROM
output wire [9:0] AddrOut,
inout tri [7:0] Data,
input wire [2:0] ID,
output tri IRQ,
output tri DmaReqOut,
input wire DmaAckIn,
input wire Halt,
input wire Reset,
input wire SpiDI,
output wire SpiDO,
output wire SpiCK,
output wire SpiCS,
output wire DeviceWr,
output wire DeviceRd,
output wire DeviceCS,
output tri EXTSEL,
input wire DeviceInt
);
reg [3:0] ClkPhase;
reg [2:0] DevID;
reg [5:0] RamBank;
reg [7:0] RomBank;
reg [3:0] DeviceBank;
reg [15:0] DmaAddr;
reg [15:0] DmaCount;
reg DmaReq;
reg DmaCycle;
reg DmaRead; /* Read from device, write to RAM if 1, Write to device, read from RAM if 0 */
reg DmaOdd;
reg DmaOddPickup; /* Blank read/write to align FIFO access */
reg ReadWrite; /* 1 = read, 0 = write, latched */
reg W5300Sel; /* 1 = selected */
reg RamSel; /* 1 = selected */
reg RomSel; /* 1 = selected */
reg Selected;
reg SpiBit;
reg SpiSel;
reg SpiClkSig;
// There are three parts of the clock we care about
// 1: Start of phase 1 (negative edge phi2) - all input data should be sampled at this time
// 2: Phase 1 plus 35 nS - all latched or held output data should be dropped at this time
// 8: Start of phase 2 (positive edge phi2) - addresses should be sampled at this time, and chip selects enabled
// 15: Just before start of phase 1 (negative edge phi2) - update DmaCycle latch
always @(negedge CLK1) begin
if (Reset == 1'b0) begin
/* sync clock */
if (Phi2 == 1'b0 && ClkPhase[3] != 1'b0) begin
ClkPhase <= {Phi2,3'b0};
end
/* Reset! */
DeviceBank <= 0;
DmaAddr <= 0;
DmaCount <= 0;
DmaCycle <= 0;
RamAddr <= 0;
RomAddr <= 0;
Selected <= 0;
DmaReq <= 0;
SpiBit <= 0;
SpiSel <= 0;
DevID <= ID;
end else begin
/* next clock phase */
ClkPhase <= ClkPhase + 1;
/* test current clock phase */
if (ClkPhase == 4'b0000) begin
if (DmaCycle) begin
if (DmaRead == 1'b0) begin
if (DmaCount == 1) begin
DmaCount <= 0;
if (DmaOdd) begin
// one dummy cycle needed
DmaOdd <= 0;
end else begin
// last cycle
DmaReq <= 0;
end
end else begin
DmaOdd <= ! DmaOdd;
DmaCount <= DmaCount - 1;
DmaAddr <= DmaAddr + 1;
end
end
end else if (ReadWrite == 1'b0) begin
// sample inputs and perform write operation
if (SysAddr[15:7] == 9'b110100010 && Selected) begin // First 127 bytes
RomBank[7:0] <= SysAddr[7:0];
end else if (SysAddr[15:4] == 12'b110100011100 && Selected) begin // D1Cx
DeviceBank[3:0] <= SysAddr[3:0];
end else if (SysAddr[15:3] == 13'b1101000111010 && Selected) begin // D1D0-7
SpiBit <= Data[SysAddr[2:0]];
end else if (SysAddr[15:0] == 16'b1101000111010100 && Selected) begin // D1D8
DmaAddr[7:0] <= Data[7:0];
end else if (SysAddr[15:0] == 16'b1101000111010101 && Selected) begin // D1D9
DmaAddr[15:8] <= Data[7:0];
end else if (SysAddr[15:0] == 16'b1101000111010110 && Selected) begin // D1DA
DmaCount[7:0] <= Data[7:0];
end else if (SysAddr[15:0] == 16'b1101000111010111 && Selected) begin // D1DB
DmaCount[15:8] <= Data[7:0];
end else if (SysAddr[15:1] == 15'b110100011101100 && Selected) begin // D1DC-DD
// Start DMA
DmaReq <= 1;
DmaRead <= SysAddr[0];
DmaOdd <= DmaCount[0];
end else if (SysAddr[15:1] == 15'b110100011101101 && Selected) begin // D1DE-DF
SpiClkSig <= SysAddr[0];
end else if (SysAddr[15:0] == 16'b1101000111111111) begin
Selected <= Data == 8'b1 << DevID; // disable on conflict
end else if (SysAddr[15:5] == 11'b11010001111 && Selected) begin // D1E0-D1FE
RamBank[4:0] <= SysAddr[4:0];
end
end
end else if (ClkPhase == 4'b0001 && ReadWrite == 1'b1) begin
// clear holds from read operation
W5300Sel <= 0;
RamSel <= 0;
RomSel <= 0;
end else if (ClkPhase == 4'b1000) begin
// Sample all address info and enable read operation
ReadWrite <= RdWr;
end else if (ClkPhase == 4'b1111) begin
// Check if the next cycle will be a DMA cycle
DmaCycle <= DmaReq && DmaAckIn && Halt;
end
end
end
always @(negedge Phi2) begin
if (Reset == 1'b0) begin
DeviceBank <= 0;
DmaAddr <= 0;
DmaCount <= 0;
DmaCycle <= 0;
RamAddr <= 0;
RomAddr <= 0;
Selected <= 0;
DmaReq <= 0;
SpiBit <= 0;
SpiSel <= 0;
end else begin
if ((DmaReq & !Halt) == 1'b1) begin
/* Just *starting* a DMA cycle */
DmaCycle <= 1'b1;
if (DmaOddPickup == 1'b1 || DmaCount == 16'h1 && DmaOdd == 1'b0) begin
/* Will be the last cycle */
DmaReq <= 0;
end
end else begin
DmaCycle <= 1'b0;
end
if (DmaCycle == 1'b1) begin
/* Just *finishing* a DMA cycle */
if (DmaOddPickup == 1'b0) begin
/* actual cycle */
if (DmaCount == 16'h1) begin
/* Last DMA cycle (maybe) */
if (DmaOdd == 1'b1) begin
/* One more cycle to align */
DmaOdd <= 0;
DmaOddPickup <= 1'b1;
end else begin
/* Next cycle is the last DMA cycle */
DmaRead <= 0;
DmaReq <= 0;
end
end
DmaAddr <= DmaAddr + 1;
DmaCount <= DmaCount - 1;
end
end else if ((Selected & RdWr) == 1'b0) begin
/* Just *finishing* a non-DMA cycle */
/* register loads */
if (SysAddr[15:6] == ('hD100 >> 6)) begin
RamAddr[13:8] <= SysAddr[5:0];
end else if (SysAddr[15:6] == ('hD140 >> 6)) begin
RomAddr[15:10] <= SysAddr[5:0];
// D180..D1BF = W5300 access
end else if (SysAddr[15:4] == ('hD1E0 >> 4)) begin
DeviceBank[3:0] <= SysAddr[3:0];
end else if (SysAddr == 'hD1F7) begin
DmaAddr[7:0] <= Data[7:0];
end else if (SysAddr == 'hD1F8) begin
DmaAddr[15:8] <= Data[7:0];
end else if (SysAddr == 'hD1F9) begin
DmaCount[7:0] <= Data[7:0];
end else if (SysAddr == 'hD1FA) begin
DmaCount[15:8] <= Data[7:0];
end else if (SysAddr == 'hD1FB) begin
// initiate DMA transfer, bit 0 = R/!W
DmaRead <= Data[0];
DmaOddPickup <= 0;
DmaOdd <= DmaCount[0];
DmaReq <= 1'b1;
// D1FC = /HALT detect (read only)
end else if (SysAddr == 'hD1FD) begin
SpiSel <= Data[0]; // Write 1 to select SPI, 0 to deselect
end else if (SysAddr == 'hD1FE) begin
SpiBit <= Data[7]; // MSB first, left shift to empty register
SpiClkSig <= 1'b1;
end else if (SysAddr == 'hD1FF) begin
Selected <= Dx;
end
end
end
if (SpiBit == 1'b1) begin
SpiBit <= 0;
end
if (SpiClkSig == 1'b1) begin
SpiClkSig <= 0;
end
end
endmodule
|
module sky130_fd_sc_lp__iso1n (
X ,
A ,
SLEEP_B,
VPWR ,
KAGND ,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input SLEEP_B;
input VPWR ;
input KAGND ;
input VPB ;
input VNB ;
// Local signals
wire SLEEP ;
wire pwrgood_pp0_out_A ;
wire pwrgood_pp1_out_SLEEP;
// Name Output Other arguments
not not0 (SLEEP , SLEEP_B );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_A , A, VPWR, KAGND );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp1 (pwrgood_pp1_out_SLEEP, SLEEP, VPWR, KAGND );
or or0 (X , pwrgood_pp0_out_A, pwrgood_pp1_out_SLEEP);
endmodule
|
module
// tag
always@(posedge clk) begin
usr_arb_rx_wr_tag <= rx_wr_tag_reg[`IF_TAG-1:0];
rif_rx_wr_tag <= rx_wr_tag_reg[`IF_TAG-1:0];
end
// valid
always@(posedge clk) begin
if(~ rst_n)begin
usr_arb_rx_wr_valid <= 0;
rif_rx_wr_valid <= 0;
end
else begin
usr_arb_rx_wr_valid <= rx_wr_valid_reg & rx_wr_tag_reg[`FTHREAD_TAG-1] & run_wr_tx;
rif_rx_wr_valid <= rx_wr_valid_reg & ~rx_wr_tag_reg[`FTHREAD_TAG-1] & run_wr_tx;
end
end
//////////////////////////////////////////////////////////// TX WR FIFO
assign wr_cmd = (run_wr_tx)? `CCI_REQ_WR_LINE : `CCI_REQ_WR_THRU;
quick_fifo #(.FIFO_WIDTH(512+72),
.FIFO_DEPTH_BITS(9),
.FIFO_ALMOSTFULL_THRESHOLD(32)
) tx_wr_fifo(
.clk (clk),
.reset_n (rst_n),
.din ({ wr_cmd, ft_tx_wr_addr, ft_tx_wr_tag, ft_tx_data}),
.we (ft_tx_wr_valid),
.re (tx_wr_ready),
.dout ({tx_wr_hdr, tx_data}),
.empty (tx_wr_fifo_empty),
.valid (tx_wr_valid),
.full (tx_wr_fifo_full),
.count (),
.almostfull ()
);
/////////////////////////////////////////////////////////////////////////////////
// Track All Write requests that are finished
always@(posedge clk) begin
if( ~rst_n | (ch_status_state == CHANNEL_IDLE_STATE) )begin
writes_sent <= 0;
writes_done <= 0;
end
else begin
writes_sent <= (tx_wr_valid & tx_wr_ready)? (writes_sent + 1'b1) : writes_sent;
writes_done <= (rx_wr_valid_reg)? (writes_done + 1'b1) : writes_done;
end
end
///////////////////////////////////////////////////////////////////////////////////////////////////
////////////////////////////////// //////////////////////////////////////
////////////////////////////// Command Buffer ///////////////////////////////////
////////////////////////////////// //////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////////////////////////
// communicate with the scheduler
assign flush_cmd = (ch_status_state == CHANNEL_DONE_STATE);
// cmd_line
always@(posedge clk) begin
if(~cmd_buff_valid) begin
cmd_buff <= reserved_cmd;
end
end
// valid
always@(posedge clk) begin
if(~rst_n) begin
cmd_buff_valid <= 1'b0;
end
else if(flush_cmd) begin
cmd_buff_valid <= 1'b0;
end
else if(reserved_cmd_valid & (ch_status_state == CHANNEL_IDLE_STATE)) begin
cmd_buff_valid <= 1'b1;
end
end
// reserved cmd
// cmd_line
always@(posedge clk) begin
if(~reserved_cmd_valid) begin
reserved_cmd <= cmd_line;
end
end
// valid
always@(posedge clk) begin
if(~rst_n) begin
reserved_cmd_valid <= 1'b0;
end
else if(read_reserved_cmd) begin
reserved_cmd_valid <= 1'b0;
end
else if(cmd_valid) begin
reserved_cmd_valid <= 1'b1;
end
end
assign read_reserved_cmd = reserved_cmd_valid & (ch_status_state == CHANNEL_IDLE_STATE);
///////////////////////////////////////////////////////////////////////////////////////////////////
////////////////////////////////// //////////////////////////////////////
////////////////////////////// FThread State Machine ///////////////////////////////////
////////////////////////////////// //////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////////////////////////
always@(posedge clk) begin
if(~rst_n) begin
ch_status_state <= 3'b0;
set_wr_if_direct_pipelined <= 0;
set_wr_if_mem_pipelined <= 0;
wr_mem_pipeline_addr <= 0;
set_rd_if_direct_pipelined <= 0;
set_rd_if_mem_pipelined <= 0;
rd_mem_pipeline_addr <= 0;
rd_mem_pipeline_addr_code <= 0;
rd_direct_pipeline_addr_code <= 0;
fthread_job_done <= 0;
start_d0 <= 0;
rif_done <= 0;
wif_done <= 0;
config_param_line <= 0;
run_rd_tx <= 0;
run_wr_tx <= 0;
ft_tx_wr_valid <= 0;
ft_tx_data <= 0;
ft_tx_wr_addr <= 0;
ft_tx_wr_tag <= 0;
ft_tx_rd_valid <= 0;
ft_tx_rd_addr <= 0;
ft_tx_rd_tag <= 0;
end
else begin
case (ch_status_state)
CHANNEL_IDLE_STATE: begin
/* If a valid job request is available in the command buffer, then we issue a status update that the job is starting
and compute some necessary flags for the configuration of the FThread Controller */
ft_tx_wr_valid <= 1'b0;
fthread_job_done <= 0;
start_d0 <= 0;
ft_tx_rd_valid <= 0;
rif_done <= 0;
wif_done <= 0;
if(cmd_buff_valid) begin
// Go to start state, set some flags
ch_status_state <= CHANNEL_STARTING_STATE;
// WR IF Config
set_wr_if_direct_pipelined <= (cmd_buff[121:120] == `WR_IF_DIRECT_PIPELINE_CODE);
set_wr_if_mem_pipelined <= (cmd_buff[121:120] == `WR_IF_MEM_PIPELINE_CODE);
wr_mem_pipeline_addr <= cmd_buff[179:122];
// RD IF Config
set_rd_if_direct_pipelined <= cmd_buff[180];
set_rd_if_mem_pipelined <= cmd_buff[181];
rd_mem_pipeline_addr <= cmd_buff[239:182];
rd_mem_pipeline_addr_code <= cmd_buff[243:240];
rd_direct_pipeline_addr_code <= cmd_buff[247:244];
// write fthread status as starting to the SW to see.
ft_tx_wr_valid <= 1'b1;
ft_tx_data <= {um_state_counters[255:0], ReadyCycles, ReadCycles, finishCycles, ConfigCycles, exeCycles, WrReqCnt, RdReqCnt, 29'b0, CHANNEL_STARTING_STATE};
ft_tx_wr_addr <= cmd_buff[57:0];
ft_tx_wr_tag <= 0;
end
end
CHANNEL_STARTING_STATE: begin
/* This state is just a stopby state until the starting status update request is sent to memory*/
if(ft_tx_wr_ready) begin
ch_status_state <= CHANNEL_CONFIG_STATE;
ft_tx_wr_valid <= 1'b0;
end
end
CHANNEL_CONFIG_STATE: begin
/* During this state the Config struct reader is started to read the user AFU configuration data structure.
When the configuration is obtained we switch to the Run state and trigger the user AFU*/
if (afu_config_struct_valid) begin
ch_status_state <= CHANNEL_RUN_STATE;
start_d0 <= 1'b1;
run_rd_tx <= 1'b1;
run_wr_tx <= 1'b1;
end
config_param_line <= afu_config_struct;
//
if(ft_tx_rd_ready) begin
ft_tx_rd_valid <= cfg_tx_rd_valid;
ft_tx_rd_addr <= cfg_tx_rd_addr;
ft_tx_rd_tag <= {1'b0, cfg_tx_rd_tag};
end
end
CHANNEL_RUN_STATE: begin
/* In this state the user AFU is active, we stay in this state until the user declares it finished processing and producing
all the results. Then we move to the Drain WR FIFO state, to make sure all user generated write requests are submitted to
memory*/
start_d0 <= 1'b0;
if(um_done) begin
ch_status_state <= CHANNEL_DRAIN_WR_FIFO_STATE;
config_param_line <= 0;
wif_done <= 1'b1;
rif_done <= 1'b1;
set_rd_if_direct_pipelined <= 0;
set_rd_if_mem_pipelined <= 0;
rd_mem_pipeline_addr <= 0;
rd_mem_pipeline_addr_code <= 0;
rd_direct_pipeline_addr_code <= 0;
end
//
// TX RD
if(ft_tx_rd_ready) begin
if(wif_tx_rd_valid) begin
ft_tx_rd_valid <= 1'b1;
ft_tx_rd_addr <= wif_tx_rd_addr;
ft_tx_rd_tag <= {1'b0, wif_tx_rd_tag};
end
else begin
ft_tx_rd_valid <= usr_arb_tx_rd_valid;
ft_tx_rd_addr <= usr_arb_tx_rd_addr;
ft_tx_rd_tag <= {1'b1, usr_arb_tx_rd_tag};
end
end
// TX WR
if(ft_tx_wr_ready) begin
if(rif_tx_wr_valid) begin
ft_tx_wr_valid <= 1'b1;
ft_tx_wr_addr <= rif_tx_wr_addr;
ft_tx_wr_tag <= {1'b0, rif_tx_wr_tag};
ft_tx_data <= rif_tx_data;
end
else begin
ft_tx_wr_valid <= usr_arb_tx_wr_valid;
ft_tx_wr_addr <= usr_arb_tx_wr_addr;
ft_tx_wr_tag <= {1'b1, usr_arb_tx_wr_tag};
ft_tx_data <= usr_arb_tx_data;
end
end
end
CHANNEL_DRAIN_WR_FIFO_STATE: begin
/* In this state we make sure all the write requests in the different FIFOs are submitted to memory*/
if (user_tx_wr_if_empty & tx_wr_fifo_empty & ~ft_tx_wr_valid) begin
ch_status_state <= CHANNEL_WRFENCE_STATE;
end
if(tx_wr_fifo_empty) begin
set_wr_if_direct_pipelined <= 0;
set_wr_if_mem_pipelined <= 0;
wr_mem_pipeline_addr <= 0;
end
// TX RD
if(ft_tx_rd_ready) begin
ft_tx_rd_valid <= wif_tx_rd_valid;
ft_tx_rd_addr <= wif_tx_rd_addr;
ft_tx_rd_tag <= {1'b0, wif_tx_rd_tag};
end
// TX WR
if(ft_tx_wr_ready) begin
if(rif_tx_wr_valid) begin
ft_tx_wr_valid <= 1'b1;
ft_tx_wr_addr <= rif_tx_wr_addr;
ft_tx_wr_tag <= {1'b0, rif_tx_wr_tag};
ft_tx_data <= rif_tx_data;
end
else begin
ft_tx_wr_valid <= usr_arb_tx_wr_valid;
ft_tx_wr_addr <= usr_arb_tx_wr_addr;
ft_tx_wr_tag <= {1'b1, usr_arb_tx_wr_tag};
ft_tx_data <= usr_arb_tx_data;
end
end
end
CHANNEL_WRFENCE_STATE: begin
run_rd_tx <= 0;
run_wr_tx <= 0;
if (writes_sent == writes_done) begin
ch_status_state <= CHANNEL_DONE_STATE;
//
ft_tx_wr_valid <= 1'b1;
ft_tx_data <= {um_state_counters[255:0], ReadyCycles, ReadCycles, finishCycles, ConfigCycles, exeCycles, WrReqCnt, RdReqCnt, 29'b0, CHANNEL_DONE_STATE};
ft_tx_wr_addr <= cmd_buff[57:0];
ft_tx_wr_tag <= 0;
end
end
CHANNEL_DONE_STATE: begin
if(ft_tx_wr_ready) begin
ch_status_state <= CHANNEL_DONE_RESP_STATE;
ft_tx_wr_valid <= 1'b0;
end
end
CHANNEL_DONE_RESP_STATE: begin
if(rx_wr_valid_reg) begin
ch_status_state <= CHANNEL_IDLE_STATE;
fthread_job_done <= 1'b1;
end
end
endcase
end
end
assign ft_tx_rd_ready = ~tx_rd_fifo_full;
assign wif_tx_rd_ready = ft_tx_rd_ready & run_rd_tx;
assign usr_arb_tx_rd_ready = ft_tx_rd_ready & run_rd_tx & ~wif_tx_rd_valid;
assign cfg_tx_rd_ready = ft_tx_rd_ready;
assign ft_tx_wr_ready = ~tx_wr_fifo_full;
assign rif_tx_wr_ready = ft_tx_wr_ready & run_wr_tx;
assign usr_arb_tx_wr_ready = ft_tx_wr_ready & run_wr_tx & ~rif_tx_wr_valid;
///////////////////////////////////////////////////////////////////////////////////////////////////
////////////////////////////////// //////////////////////////////////////
////////////////////////////// Configurer ///////////////////////////////////
////////////////////////////////// //////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////////////////////////
ReadConfigStruct #(.MAX_NUM_CONFIG_CL(MAX_NUM_CONFIG_CL))
ReadConfigStruct (
.clk (clk),
.rst_n (rst_n & ~(ch_status_state == CHANNEL_DONE_RESP_STATE)),
//-------------------------------------------------//
.get_config_struct ( ch_status_state == CHANNEL_CONFIG_STATE ),
.base_addr (cmd_buff[115:58]),
.config_struct_length ( {28'b0, cmd_buff[119:116]}),
// User Module TX RD
.cs_tx_rd_addr (cfg_tx_rd_addr),
.cs_tx_rd_tag (cfg_tx_rd_tag),
.cs_tx_rd_valid (cfg_tx_rd_valid),
.cs_tx_rd_free (cfg_tx_rd_ready),
// User Module RX RD
.cs_rx_rd_tag (cfg_rx_rd_tag),
.cs_rx_rd_data (cfg_rx_data),
.cs_rx_rd_valid (cfg_rx_rd_valid),
//
.afu_config_struct (afu_config_struct),
.afu_config_struct_valid (afu_config_struct_valid)
);
///////////////////////////////////////////////////////////////////////////////////////////////////
////////////////////////////////// ///////////////////////////////////
////////////////////////////// User Module Control Interface ///////////////////////////////
////////////////////////////////// ///////////////////////////////////
///////////////////////////////////////////////////////////////////////////////////////////////////
//
always@(posedge clk) begin
um_params <= config_param_line;
end
always@(posedge clk) begin
if( ~rst_n) begin
start_um <= 0;
end
else begin
start_um <= start_d0;
end
end
//assign um_params = config_param_line;
assign reset_user_logic = (ch_status_state == CHANNEL_IDLE_STATE);
///////////////////////////////////////////////////////////////////////////////////////////////////
////////////////////////////////// //////////////////////////////////////
////////////////////////////// User Module IO Interfaces ///////////////////////////////////
////////////////////////////////// //////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////////////////////////
// RD Interface
user_tx_rd_if #(.USER_TAG(USER_RD_TAG))
user_tx_rd_if(
.clk (clk),
.rst_n (rst_n),
.reset_interface ( (ch_status_state == CHANNEL_IDLE_STATE) ),
.set_if_mem_pipelined (set_rd_if_mem_pipelined),
.set_if_direct_pipelined (set_rd_if_direct_pipelined),
.mem_pipeline_addr (rd_mem_pipeline_addr),
.mem_pipeline_addr_code (rd_mem_pipeline_addr_code),
.direct_pipeline_addr_code (rd_direct_pipeline_addr_code),
.reads_finished (rif_done),
//--------------------- User RD Request -----------------------------//
// User Module TX RD
.um_tx_rd_addr (um_tx_rd_addr),
.um_tx_rd_tag (um_tx_rd_tag),
.um_tx_rd_valid (um_tx_rd_valid),
.um_tx_rd_ready (um_tx_rd_ready),
// User Module RX RD
.um_rx_rd_tag (um_rx_rd_tag),
.um_rx_data (um_rx_data),
.um_rx_rd_valid (um_rx_rd_valid),
.um_rx_rd_ready (um_rx_rd_ready),
//-------------------- to Fthread Controller ------------------------//
.usr_arb_tx_rd_valid (usr_arb_tx_rd_valid),
.usr_arb_tx_rd_addr (usr_arb_tx_rd_addr),
.usr_arb_tx_rd_tag (usr_arb_tx_rd_tag),
.usr_arb_tx_rd_ready (usr_arb_tx_rd_ready),
.usr_arb_rx_rd_valid (usr_arb_rx_rd_valid),
.usr_arb_rx_rd_tag (usr_arb_rx_rd_tag),
.usr_arb_rx_data (usr_arb_rx_data),
.rif_tx_wr_addr (rif_tx_wr_addr),
.rif_tx_wr_tag (rif_tx_wr_tag),
.rif_tx_wr_valid (rif_tx_wr_valid),
.rif_tx_data (rif_tx_data),
.rif_tx_wr_ready (rif_tx_wr_ready),
.rif_rx_wr_tag (rif_rx_wr_tag),
.rif_rx_wr_valid (rif_rx_wr_valid),
//-------------------- to pipeline writer ---------------------------//
.usr_pipe_tx_rd_valid (left_pipe_tx_rd_valid),
.usr_pipe_tx_rd_tag (left_pipe_tx_rd_tag),
.usr_pipe_tx_rd_ready (left_pipe_tx_rd_ready),
.usr_pipe_rx_rd_valid (left_pipe_rx_rd_valid),
.usr_pipe_rx_rd_tag (left_pipe_rx_rd_tag),
.usr_pipe_rx_data (left_pipe_rx_data),
.usr_pipe_rx_rd_ready (left_pipe_rx_rd_ready)
);
// WR Interface
user_tx_wr_if #(.USER_TAG(USER_WR_TAG) )
user_tx_wr_if(
.clk (clk),
.rst_n (rst_n),
.reset_interface ( (ch_status_state == CHANNEL_IDLE_STATE) ),
.set_if_pipelined (set_wr_if_direct_pipelined),
.user_tx_wr_if_empty (user_tx_wr_if_empty),
.set_if_mem_pipelined (set_wr_if_mem_pipelined),
.mem_pipeline_addr (wr_mem_pipeline_addr),
.writes_finished (wif_done),
//--------------------- User RD Request -----------------------------//
// User Module TX WR
.um_tx_wr_addr (um_tx_wr_addr),
.um_tx_wr_tag (um_tx_wr_tag),
.um_tx_wr_valid (um_tx_wr_valid),
.um_tx_data (um_tx_data),
.um_tx_wr_ready (um_tx_wr_ready),
// User Module RX WR
.um_rx_wr_valid (um_rx_wr_valid),
.um_rx_wr_tag (um_rx_wr_tag),
//-------------------- to Fthread Controller ------------------------//
.usr_arb_tx_wr_valid (usr_arb_tx_wr_valid),
.usr_arb_tx_wr_addr (usr_arb_tx_wr_addr),
.usr_arb_tx_wr_tag (usr_arb_tx_wr_tag),
.usr_arb_tx_wr_ready (usr_arb_tx_wr_ready),
.usr_arb_tx_data (usr_arb_tx_data),
.usr_arb_rx_wr_valid (usr_arb_rx_wr_valid),
.usr_arb_rx_wr_tag (usr_arb_rx_wr_tag),
.wif_tx_rd_addr (wif_tx_rd_addr),
.wif_tx_rd_tag (wif_tx_rd_tag),
.wif_tx_rd_valid (wif_tx_rd_valid),
.wif_tx_rd_ready (wif_tx_rd_ready),
.wif_rx_rd_tag (wif_rx_rd_tag),
.wif_rx_data (wif_rx_data),
.wif_rx_rd_valid (wif_rx_rd_valid),
//-------------------- To pipeline reader
.usr_pipe_tx_rd_valid (right_pipe_tx_rd_valid),
.usr_pipe_tx_rd_tag (right_pipe_tx_rd_tag),
.usr_pipe_tx_rd_ready (right_pipe_tx_rd_ready),
.usr_pipe_rx_rd_valid (right_pipe_rx_rd_valid),
.usr_pipe_rx_rd_tag (right_pipe_rx_rd_tag),
.usr_pipe_rx_data (right_pipe_rx_data),
.usr_pipe_rx_rd_ready (right_pipe_rx_rd_ready)
);
///////////////////////////////////////////////////////////////////////////////////////////////////
////////////////////////////////// //////////////////////////////////////
////////////////////////////// Profiling Counters ///////////////////////////////////
////////////////////////////////// //////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////////////////////////
always@(posedge clk) begin
if(~rst_n | (ch_status_state == CHANNEL_IDLE_STATE)) begin
RdReqCnt <= 32'b0;
GRdReqCnt <= 32'b0;
WrReqCnt <= 32'b0;
exeCycles <= 32'b0;
finishCycles <= 32'b0;
ConfigCycles <= 32'b0;
ReadCycles <= 0;
ReadyCycles <= 0;
end
else begin
exeCycles <= exeCycles + 1'b1;
if(tx_rd_valid & tx_rd_ready) begin
GRdReqCnt <= GRdReqCnt + 1'b1;
end
if(um_tx_rd_valid & um_tx_rd_ready) begin
RdReqCnt <= RdReqCnt + 1'b1;
end
//
if(um_tx_wr_valid & um_tx_wr_ready) begin
WrReqCnt <= WrReqCnt + 1'b1;
end
//
if( ch_status_state[2] ) begin
finishCycles <= finishCycles + 1'b1;
end
//
if(ch_status_state == CHANNEL_CONFIG_STATE) begin
ConfigCycles <= ConfigCycles + 1'b1;
end
//
if(um_tx_rd_valid) begin
ReadCycles <= ReadCycles + 1'b1;
end
//
if(tx_rd_ready) begin
ReadyCycles <= ReadyCycles + 1'b1;
end
end
end
endmodule
|
module IntegerMultiplication(
input [31:0] A,
input [31:0] B,
output [63:0] product,
input start,
input clk
);
reg [65:0] accumulator;
reg [6:0] cnt;
reg oldStart;
wire [32:0] B2n,B1n,B1,B2,addend;
wire [63:0] result;
assign B1n[31:0] = -B,
B2n[31:0] = (-B)<<1,
B1[31:0] = B,
B2[31:0] = B<<1,
B1n[32] = ~B[31],
B2n[32] = ~B[31],
B1[32] = B[31],
B2[32] = B[31];
initial begin
accumulator[65:33] <= 0;
accumulator[32:1] <= A;
accumulator[0] <=0;
cnt <= 32;
end
AdderAndSubber64 adder({31'b0,accumulator[65:33]},{31'b0,addend},1'b0,result,SF,CF,OF,PF,ZF);
assign addend = {33{~accumulator[2]&~accumulator[1]&~accumulator[0]}}&33'b0|
{33{~accumulator[2]&~accumulator[1]& accumulator[0]}}&B1|
{33{~accumulator[2]& accumulator[1]&~accumulator[0]}}&B1|
{33{~accumulator[2]& accumulator[1]& accumulator[0]}}&B2|
{33{ accumulator[2]&~accumulator[1]&~accumulator[0]}}&B2n|
{33{ accumulator[2]&~accumulator[1]& accumulator[0]}}&B1n|
{33{ accumulator[2]& accumulator[1]&~accumulator[0]}}&B1n|
{33{ accumulator[2]& accumulator[1]& accumulator[0]}}&33'b0
;
always @(posedge clk) begin
if (cnt < 32) begin //accmulating
if(cnt[0]) begin
accumulator[63:0] <= accumulator>>>2;
accumulator[64] <= accumulator[65];
accumulator[65] <= accumulator[65];
end
else begin
accumulator[65:33] <= result[32:0];
end
cnt <= cnt + 1;
end
else if ( cnt == 32 && (start != old Start) ) begin //initial
accumulator[65:33] <= 0;
accumulator[32:1] <= A;
accumulator[0] <=0;
cnt <= 0;
end
else begin
accumulator <= accumulator;
cnt <= 6'd32;
end
oldStart <= start;
end
assign product = accumulator[64:1];
endmodule
|
module sky130_fd_sc_ls__a41oi (
Y ,
A1 ,
A2 ,
A3 ,
A4 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input A3 ;
input A4 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire and0_out ;
wire nor0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
and and0 (and0_out , A1, A2, A3, A4 );
nor nor0 (nor0_out_Y , B1, and0_out );
sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nor0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
|
module mul_19_12 (
clk, ce, a, b, p
)/* synthesis syn_black_box syn_noprune=1 */;
input clk;
input ce;
input [18 : 0] a;
input [11 : 0] b;
output [30 : 0] p;
// synthesis translate_off
wire \blk00000001/sig000000f7 ;
wire \blk00000001/sig000000f6 ;
wire \blk00000001/sig000000f5 ;
wire \blk00000001/sig000000f4 ;
wire \blk00000001/sig000000f3 ;
wire \blk00000001/sig000000f2 ;
wire \blk00000001/sig000000f1 ;
wire \blk00000001/sig000000f0 ;
wire \blk00000001/sig000000ef ;
wire \blk00000001/sig000000ee ;
wire \blk00000001/sig000000ed ;
wire \blk00000001/sig000000ec ;
wire \blk00000001/sig000000eb ;
wire \blk00000001/sig000000ea ;
wire \blk00000001/sig000000e9 ;
wire \blk00000001/sig000000e8 ;
wire \blk00000001/sig000000e7 ;
wire \blk00000001/sig000000e6 ;
wire \blk00000001/sig000000e5 ;
wire \blk00000001/sig000000e4 ;
wire \blk00000001/sig000000e3 ;
wire \blk00000001/sig000000e2 ;
wire \blk00000001/sig000000e1 ;
wire \blk00000001/sig000000e0 ;
wire \blk00000001/sig000000df ;
wire \blk00000001/sig000000de ;
wire \blk00000001/sig000000dd ;
wire \blk00000001/sig000000dc ;
wire \blk00000001/sig000000db ;
wire \blk00000001/sig000000da ;
wire \blk00000001/sig000000d9 ;
wire \blk00000001/sig000000d8 ;
wire \blk00000001/sig000000d7 ;
wire \blk00000001/sig000000d6 ;
wire \blk00000001/sig000000d5 ;
wire \blk00000001/sig000000d4 ;
wire \blk00000001/sig000000d3 ;
wire \blk00000001/sig000000d2 ;
wire \blk00000001/sig000000d1 ;
wire \blk00000001/sig000000d0 ;
wire \blk00000001/sig000000cf ;
wire \blk00000001/sig000000ce ;
wire \blk00000001/sig000000cd ;
wire \blk00000001/sig000000cc ;
wire \blk00000001/sig000000cb ;
wire \blk00000001/sig000000ca ;
wire \blk00000001/sig000000c9 ;
wire \blk00000001/sig000000c8 ;
wire \blk00000001/sig000000c7 ;
wire \blk00000001/sig000000c6 ;
wire \blk00000001/sig000000c5 ;
wire \blk00000001/sig000000c4 ;
wire \blk00000001/sig000000c3 ;
wire \blk00000001/sig000000c2 ;
wire \blk00000001/sig000000c1 ;
wire \blk00000001/sig000000c0 ;
wire \blk00000001/sig000000bf ;
wire \blk00000001/sig000000be ;
wire \blk00000001/sig000000bd ;
wire \blk00000001/sig000000bc ;
wire \blk00000001/sig000000bb ;
wire \blk00000001/sig000000ba ;
wire \blk00000001/sig000000b9 ;
wire \blk00000001/sig000000b8 ;
wire \blk00000001/sig000000b7 ;
wire \blk00000001/sig000000b6 ;
wire \blk00000001/sig000000b5 ;
wire \blk00000001/sig000000b4 ;
wire \blk00000001/sig000000b3 ;
wire \blk00000001/sig000000b2 ;
wire \blk00000001/sig000000b1 ;
wire \blk00000001/sig000000b0 ;
wire \blk00000001/sig000000af ;
wire \blk00000001/sig000000ae ;
wire \blk00000001/sig000000ad ;
wire \blk00000001/sig000000ac ;
wire \blk00000001/sig000000ab ;
wire \blk00000001/sig000000aa ;
wire \blk00000001/sig000000a9 ;
wire \blk00000001/sig000000a8 ;
wire \blk00000001/sig000000a7 ;
wire \blk00000001/sig000000a6 ;
wire \blk00000001/sig000000a5 ;
wire \blk00000001/sig000000a4 ;
wire \blk00000001/sig000000a3 ;
wire \blk00000001/sig000000a2 ;
wire \blk00000001/sig000000a1 ;
wire \blk00000001/sig000000a0 ;
wire \blk00000001/sig0000009f ;
wire \blk00000001/sig0000009e ;
wire \blk00000001/sig0000009d ;
wire \blk00000001/sig0000009c ;
wire \blk00000001/sig0000009b ;
wire \blk00000001/sig0000009a ;
wire \blk00000001/sig00000099 ;
wire \blk00000001/sig00000098 ;
wire \blk00000001/sig00000097 ;
wire \blk00000001/sig00000096 ;
wire \blk00000001/sig00000095 ;
wire \blk00000001/sig00000094 ;
wire \blk00000001/sig00000093 ;
wire \blk00000001/sig00000092 ;
wire \blk00000001/sig00000091 ;
wire \blk00000001/sig00000090 ;
wire \blk00000001/sig0000008f ;
wire \blk00000001/sig0000008e ;
wire \blk00000001/sig0000008d ;
wire \blk00000001/sig0000008c ;
wire \blk00000001/sig0000008b ;
wire \blk00000001/sig0000008a ;
wire \blk00000001/sig00000089 ;
wire \blk00000001/sig00000088 ;
wire \blk00000001/sig00000087 ;
wire \blk00000001/sig00000086 ;
wire \blk00000001/sig00000085 ;
wire \blk00000001/sig00000084 ;
wire \blk00000001/sig00000083 ;
wire \blk00000001/sig00000082 ;
wire \blk00000001/sig00000081 ;
wire \blk00000001/sig00000080 ;
wire \blk00000001/sig0000007f ;
wire \blk00000001/sig0000007e ;
wire \blk00000001/sig0000007d ;
wire \blk00000001/sig0000007c ;
wire \blk00000001/sig0000007b ;
wire \blk00000001/sig0000007a ;
wire \blk00000001/sig00000079 ;
wire \blk00000001/sig00000078 ;
wire \blk00000001/sig00000077 ;
wire \blk00000001/sig00000076 ;
wire \blk00000001/sig00000075 ;
wire \blk00000001/sig00000074 ;
wire \blk00000001/sig00000073 ;
wire \blk00000001/sig00000072 ;
wire \blk00000001/sig00000071 ;
wire \blk00000001/sig00000070 ;
wire \blk00000001/sig0000006f ;
wire \blk00000001/sig0000006e ;
wire \blk00000001/sig0000006d ;
wire \blk00000001/sig0000006c ;
wire \blk00000001/sig0000006b ;
wire \blk00000001/sig0000006a ;
wire \blk00000001/sig00000069 ;
wire \blk00000001/sig00000068 ;
wire \blk00000001/sig00000067 ;
wire \blk00000001/sig00000066 ;
wire \blk00000001/sig00000065 ;
wire \blk00000001/sig00000064 ;
wire \blk00000001/sig00000063 ;
wire \blk00000001/sig00000062 ;
wire \blk00000001/sig00000061 ;
wire \blk00000001/sig00000060 ;
wire \blk00000001/sig0000005f ;
wire \blk00000001/sig0000005e ;
wire \blk00000001/sig0000005d ;
wire \blk00000001/sig0000005c ;
wire \blk00000001/sig0000005b ;
wire \blk00000001/sig0000005a ;
wire \blk00000001/sig00000059 ;
wire \blk00000001/sig00000058 ;
wire \blk00000001/sig00000057 ;
wire \blk00000001/sig00000056 ;
wire \blk00000001/sig00000055 ;
wire \blk00000001/sig00000054 ;
wire \blk00000001/sig00000053 ;
wire \blk00000001/sig00000052 ;
wire \blk00000001/sig00000051 ;
wire \blk00000001/sig00000050 ;
wire \blk00000001/sig0000004f ;
wire \blk00000001/sig0000004e ;
wire \blk00000001/sig0000004d ;
wire \blk00000001/sig0000004c ;
wire \blk00000001/sig0000004b ;
wire \blk00000001/sig0000004a ;
wire \blk00000001/sig00000049 ;
wire \blk00000001/sig00000048 ;
wire \blk00000001/sig00000047 ;
wire \blk00000001/sig00000046 ;
wire \blk00000001/sig00000045 ;
wire \blk00000001/sig00000044 ;
wire \blk00000001/sig00000043 ;
wire \blk00000001/sig00000042 ;
wire \blk00000001/sig00000041 ;
wire \NLW_blk00000001/blk00000005_CARRYOUTF_UNCONNECTED ;
wire \NLW_blk00000001/blk00000005_CARRYOUT_UNCONNECTED ;
wire \NLW_blk00000001/blk00000005_C<47>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000005_C<46>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000005_C<45>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000005_C<44>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000005_C<43>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000005_C<42>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000005_C<41>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000005_C<40>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000005_C<39>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000005_C<38>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000005_C<37>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000005_C<36>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000005_C<35>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000005_C<34>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000005_C<33>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000005_C<32>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000005_C<31>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000005_C<30>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000005_C<29>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000005_C<28>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000005_C<27>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000005_C<26>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000005_C<25>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000005_C<24>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000005_C<23>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000005_C<22>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000005_C<21>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000005_C<20>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000005_C<19>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000005_C<18>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000005_C<17>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000005_C<16>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000005_C<15>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000005_C<14>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000005_C<13>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000005_C<12>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000005_C<11>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000005_C<10>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000005_C<9>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000005_C<8>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000005_C<7>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000005_C<6>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000005_C<5>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000005_C<4>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000005_C<3>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000005_C<2>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000005_C<1>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000005_C<0>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000005_M<35>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000005_M<34>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000005_M<33>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000005_M<32>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000005_M<31>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000005_M<30>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000005_M<29>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000005_M<28>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000005_M<27>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000005_M<26>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000005_M<25>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000005_M<24>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000005_M<23>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000005_M<22>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000005_M<21>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000005_M<20>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000005_M<19>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000005_M<18>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000005_M<17>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000005_M<16>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000005_M<15>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000005_M<14>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000005_M<13>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000005_M<12>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000005_M<11>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000005_M<10>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000005_M<9>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000005_M<8>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000005_M<7>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000005_M<6>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000005_M<5>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000005_M<4>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000005_M<3>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000005_M<2>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000005_M<1>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000005_M<0>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000004_CARRYOUTF_UNCONNECTED ;
wire \NLW_blk00000001/blk00000004_CARRYOUT_UNCONNECTED ;
wire \NLW_blk00000001/blk00000004_BCOUT<17>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000004_BCOUT<16>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000004_BCOUT<15>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000004_BCOUT<14>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000004_BCOUT<13>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000004_BCOUT<12>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000004_BCOUT<11>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000004_BCOUT<10>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000004_BCOUT<9>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000004_BCOUT<8>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000004_BCOUT<7>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000004_BCOUT<6>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000004_BCOUT<5>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000004_BCOUT<4>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000004_BCOUT<3>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000004_BCOUT<2>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000004_BCOUT<1>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000004_BCOUT<0>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000004_P<47>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000004_P<46>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000004_P<45>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000004_P<44>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000004_P<43>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000004_P<42>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000004_P<41>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000004_P<40>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000004_P<39>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000004_P<38>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000004_P<37>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000004_P<36>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000004_P<35>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000004_P<34>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000004_P<33>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000004_P<32>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000004_P<31>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000004_P<30>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000004_P<29>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000004_P<28>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000004_P<27>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000004_P<26>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000004_P<25>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000004_P<24>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000004_P<23>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000004_P<22>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000004_P<21>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000004_P<20>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000004_P<19>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000004_P<18>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000004_P<17>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000004_P<16>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000004_P<15>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000004_P<14>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000004_M<35>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000004_M<34>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000004_M<33>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000004_M<32>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000004_M<31>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000004_M<30>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000004_M<29>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000004_M<28>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000004_M<27>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000004_M<26>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000004_M<25>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000004_M<24>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000004_M<23>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000004_M<22>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000004_M<21>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000004_M<20>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000004_M<19>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000004_M<18>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000004_M<17>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000004_M<16>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000004_M<15>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000004_M<14>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000004_M<13>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000004_M<12>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000004_M<11>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000004_M<10>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000004_M<9>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000004_M<8>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000004_M<7>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000004_M<6>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000004_M<5>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000004_M<4>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000004_M<3>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000004_M<2>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000004_M<1>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000004_M<0>_UNCONNECTED ;
FDRE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000029 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000000f7 ),
.R(\blk00000001/sig000000e4 ),
.Q(p[0])
);
FDRE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000028 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000000f6 ),
.R(\blk00000001/sig000000e4 ),
.Q(p[1])
);
FDRE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000027 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000000f5 ),
.R(\blk00000001/sig000000e4 ),
.Q(p[2])
);
FDRE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000026 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000000f4 ),
.R(\blk00000001/sig000000e4 ),
.Q(p[3])
);
FDRE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000025 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000000f3 ),
.R(\blk00000001/sig000000e4 ),
.Q(p[4])
);
FDRE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000024 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000000f2 ),
.R(\blk00000001/sig000000e4 ),
.Q(p[5])
);
FDRE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000023 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000000f1 ),
.R(\blk00000001/sig000000e4 ),
.Q(p[6])
);
FDRE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000022 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000000f0 ),
.R(\blk00000001/sig000000e4 ),
.Q(p[7])
);
FDRE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000021 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000000ef ),
.R(\blk00000001/sig000000e4 ),
.Q(p[8])
);
FDRE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000020 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000000ee ),
.R(\blk00000001/sig000000e4 ),
.Q(p[9])
);
FDRE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000001f (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000000ed ),
.R(\blk00000001/sig000000e4 ),
.Q(p[10])
);
FDRE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000001e (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000000ec ),
.R(\blk00000001/sig000000e4 ),
.Q(p[11])
);
FDRE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000001d (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000000eb ),
.R(\blk00000001/sig000000e4 ),
.Q(p[12])
);
FDRE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000001c (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000000ea ),
.R(\blk00000001/sig000000e4 ),
.Q(p[13])
);
FDRE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000001b (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000000e9 ),
.R(\blk00000001/sig000000e4 ),
.Q(p[14])
);
FDRE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000001a (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000000e8 ),
.R(\blk00000001/sig000000e4 ),
.Q(p[15])
);
FDRE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000019 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000000e7 ),
.R(\blk00000001/sig000000e4 ),
.Q(p[16])
);
SRL16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000018 (
.A0(\blk00000001/sig000000e4 ),
.A1(\blk00000001/sig000000e4 ),
.A2(\blk00000001/sig000000e4 ),
.A3(\blk00000001/sig000000e4 ),
.CE(ce),
.CLK(clk),
.D(\blk00000001/sig000000c1 ),
.Q(\blk00000001/sig000000f7 )
);
SRL16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000017 (
.A0(\blk00000001/sig000000e4 ),
.A1(\blk00000001/sig000000e4 ),
.A2(\blk00000001/sig000000e4 ),
.A3(\blk00000001/sig000000e4 ),
.CE(ce),
.CLK(clk),
.D(\blk00000001/sig000000c2 ),
.Q(\blk00000001/sig000000f6 )
);
SRL16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000016 (
.A0(\blk00000001/sig000000e4 ),
.A1(\blk00000001/sig000000e4 ),
.A2(\blk00000001/sig000000e4 ),
.A3(\blk00000001/sig000000e4 ),
.CE(ce),
.CLK(clk),
.D(\blk00000001/sig000000c3 ),
.Q(\blk00000001/sig000000f5 )
);
SRL16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000015 (
.A0(\blk00000001/sig000000e4 ),
.A1(\blk00000001/sig000000e4 ),
.A2(\blk00000001/sig000000e4 ),
.A3(\blk00000001/sig000000e4 ),
.CE(ce),
.CLK(clk),
.D(\blk00000001/sig000000c4 ),
.Q(\blk00000001/sig000000f4 )
);
SRL16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000014 (
.A0(\blk00000001/sig000000e4 ),
.A1(\blk00000001/sig000000e4 ),
.A2(\blk00000001/sig000000e4 ),
.A3(\blk00000001/sig000000e4 ),
.CE(ce),
.CLK(clk),
.D(\blk00000001/sig000000c5 ),
.Q(\blk00000001/sig000000f3 )
);
SRL16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000013 (
.A0(\blk00000001/sig000000e4 ),
.A1(\blk00000001/sig000000e4 ),
.A2(\blk00000001/sig000000e4 ),
.A3(\blk00000001/sig000000e4 ),
.CE(ce),
.CLK(clk),
.D(\blk00000001/sig000000c6 ),
.Q(\blk00000001/sig000000f2 )
);
SRL16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000012 (
.A0(\blk00000001/sig000000e4 ),
.A1(\blk00000001/sig000000e4 ),
.A2(\blk00000001/sig000000e4 ),
.A3(\blk00000001/sig000000e4 ),
.CE(ce),
.CLK(clk),
.D(\blk00000001/sig000000c7 ),
.Q(\blk00000001/sig000000f1 )
);
SRL16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000011 (
.A0(\blk00000001/sig000000e4 ),
.A1(\blk00000001/sig000000e4 ),
.A2(\blk00000001/sig000000e4 ),
.A3(\blk00000001/sig000000e4 ),
.CE(ce),
.CLK(clk),
.D(\blk00000001/sig000000c8 ),
.Q(\blk00000001/sig000000f0 )
);
SRL16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000010 (
.A0(\blk00000001/sig000000e4 ),
.A1(\blk00000001/sig000000e4 ),
.A2(\blk00000001/sig000000e4 ),
.A3(\blk00000001/sig000000e4 ),
.CE(ce),
.CLK(clk),
.D(\blk00000001/sig000000c9 ),
.Q(\blk00000001/sig000000ef )
);
SRL16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk0000000f (
.A0(\blk00000001/sig000000e4 ),
.A1(\blk00000001/sig000000e4 ),
.A2(\blk00000001/sig000000e4 ),
.A3(\blk00000001/sig000000e4 ),
.CE(ce),
.CLK(clk),
.D(\blk00000001/sig000000ca ),
.Q(\blk00000001/sig000000ee )
);
SRL16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk0000000e (
.A0(\blk00000001/sig000000e4 ),
.A1(\blk00000001/sig000000e4 ),
.A2(\blk00000001/sig000000e4 ),
.A3(\blk00000001/sig000000e4 ),
.CE(ce),
.CLK(clk),
.D(\blk00000001/sig000000cb ),
.Q(\blk00000001/sig000000ed )
);
SRL16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk0000000d (
.A0(\blk00000001/sig000000e4 ),
.A1(\blk00000001/sig000000e4 ),
.A2(\blk00000001/sig000000e4 ),
.A3(\blk00000001/sig000000e4 ),
.CE(ce),
.CLK(clk),
.D(\blk00000001/sig000000cc ),
.Q(\blk00000001/sig000000ec )
);
SRL16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk0000000c (
.A0(\blk00000001/sig000000e4 ),
.A1(\blk00000001/sig000000e4 ),
.A2(\blk00000001/sig000000e4 ),
.A3(\blk00000001/sig000000e4 ),
.CE(ce),
.CLK(clk),
.D(\blk00000001/sig000000cd ),
.Q(\blk00000001/sig000000eb )
);
SRL16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk0000000b (
.A0(\blk00000001/sig000000e4 ),
.A1(\blk00000001/sig000000e4 ),
.A2(\blk00000001/sig000000e4 ),
.A3(\blk00000001/sig000000e4 ),
.CE(ce),
.CLK(clk),
.D(\blk00000001/sig000000ce ),
.Q(\blk00000001/sig000000ea )
);
SRL16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk0000000a (
.A0(\blk00000001/sig000000e4 ),
.A1(\blk00000001/sig000000e4 ),
.A2(\blk00000001/sig000000e4 ),
.A3(\blk00000001/sig000000e4 ),
.CE(ce),
.CLK(clk),
.D(\blk00000001/sig000000cf ),
.Q(\blk00000001/sig000000e9 )
);
SRL16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000009 (
.A0(\blk00000001/sig000000e4 ),
.A1(\blk00000001/sig000000e4 ),
.A2(\blk00000001/sig000000e4 ),
.A3(\blk00000001/sig000000e4 ),
.CE(ce),
.CLK(clk),
.D(\blk00000001/sig000000d0 ),
.Q(\blk00000001/sig000000e8 )
);
SRL16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000008 (
.A0(\blk00000001/sig000000e4 ),
.A1(\blk00000001/sig000000e4 ),
.A2(\blk00000001/sig000000e4 ),
.A3(\blk00000001/sig000000e4 ),
.CE(ce),
.CLK(clk),
.D(\blk00000001/sig000000d1 ),
.Q(\blk00000001/sig000000e7 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000007 (
.C(clk),
.CE(ce),
.D(a[17]),
.Q(\blk00000001/sig000000e5 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000006 (
.C(clk),
.CE(ce),
.D(a[18]),
.Q(\blk00000001/sig000000e6 )
);
DSP48A1 #(
.A0REG ( 0 ),
.A1REG ( 1 ),
.B0REG ( 0 ),
.B1REG ( 1 ),
.CARRYINREG ( 0 ),
.CARRYINSEL ( "OPMODE5" ),
.CREG ( 0 ),
.DREG ( 0 ),
.MREG ( 1 ),
.OPMODEREG ( 0 ),
.PREG ( 1 ),
.RSTTYPE ( "SYNC" ),
.CARRYOUTREG ( 0 ))
\blk00000001/blk00000005 (
.CECARRYIN(\blk00000001/sig000000e4 ),
.RSTC(\blk00000001/sig000000e4 ),
.RSTCARRYIN(\blk00000001/sig000000e4 ),
.CED(\blk00000001/sig000000e4 ),
.RSTD(\blk00000001/sig000000e4 ),
.CEOPMODE(\blk00000001/sig000000e4 ),
.CEC(\blk00000001/sig000000e4 ),
.CARRYOUTF(\NLW_blk00000001/blk00000005_CARRYOUTF_UNCONNECTED ),
.RSTOPMODE(\blk00000001/sig000000e4 ),
.RSTM(\blk00000001/sig000000e4 ),
.CLK(clk),
.RSTB(\blk00000001/sig000000e4 ),
.CEM(ce),
.CEB(ce),
.CARRYIN(\blk00000001/sig000000e4 ),
.CEP(ce),
.CEA(ce),
.CARRYOUT(\NLW_blk00000001/blk00000005_CARRYOUT_UNCONNECTED ),
.RSTA(\blk00000001/sig000000e4 ),
.RSTP(\blk00000001/sig000000e4 ),
.B({b[11], b[11], b[11], b[11], b[11], b[11], b[11], b[10], b[9], b[8], b[7], b[6], b[5], b[4], b[3], b[2], b[1], b[0]}),
.BCOUT({\blk00000001/sig000000e3 , \blk00000001/sig000000e2 , \blk00000001/sig000000e1 , \blk00000001/sig000000e0 , \blk00000001/sig000000df ,
\blk00000001/sig000000de , \blk00000001/sig000000dd , \blk00000001/sig000000dc , \blk00000001/sig000000db , \blk00000001/sig000000da ,
\blk00000001/sig000000d9 , \blk00000001/sig000000d8 , \blk00000001/sig000000d7 , \blk00000001/sig000000d6 , \blk00000001/sig000000d5 ,
\blk00000001/sig000000d4 , \blk00000001/sig000000d3 , \blk00000001/sig000000d2 }),
.PCIN({\blk00000001/sig000000e4 , \blk00000001/sig000000e4 , \blk00000001/sig000000e4 , \blk00000001/sig000000e4 , \blk00000001/sig000000e4 ,
\blk00000001/sig000000e4 , \blk00000001/sig000000e4 , \blk00000001/sig000000e4 , \blk00000001/sig000000e4 , \blk00000001/sig000000e4 ,
\blk00000001/sig000000e4 , \blk00000001/sig000000e4 , \blk00000001/sig000000e4 , \blk00000001/sig000000e4 , \blk00000001/sig000000e4 ,
\blk00000001/sig000000e4 , \blk00000001/sig000000e4 , \blk00000001/sig000000e4 , \blk00000001/sig000000e4 , \blk00000001/sig000000e4 ,
\blk00000001/sig000000e4 , \blk00000001/sig000000e4 , \blk00000001/sig000000e4 , \blk00000001/sig000000e4 , \blk00000001/sig000000e4 ,
\blk00000001/sig000000e4 , \blk00000001/sig000000e4 , \blk00000001/sig000000e4 , \blk00000001/sig000000e4 , \blk00000001/sig000000e4 ,
\blk00000001/sig000000e4 , \blk00000001/sig000000e4 , \blk00000001/sig000000e4 , \blk00000001/sig000000e4 , \blk00000001/sig000000e4 ,
\blk00000001/sig000000e4 , \blk00000001/sig000000e4 , \blk00000001/sig000000e4 , \blk00000001/sig000000e4 , \blk00000001/sig000000e4 ,
\blk00000001/sig000000e4 , \blk00000001/sig000000e4 , \blk00000001/sig000000e4 , \blk00000001/sig000000e4 , \blk00000001/sig000000e4 ,
\blk00000001/sig000000e4 , \blk00000001/sig000000e4 , \blk00000001/sig000000e4 }),
.C({\NLW_blk00000001/blk00000005_C<47>_UNCONNECTED , \NLW_blk00000001/blk00000005_C<46>_UNCONNECTED ,
\NLW_blk00000001/blk00000005_C<45>_UNCONNECTED , \NLW_blk00000001/blk00000005_C<44>_UNCONNECTED , \NLW_blk00000001/blk00000005_C<43>_UNCONNECTED ,
\NLW_blk00000001/blk00000005_C<42>_UNCONNECTED , \NLW_blk00000001/blk00000005_C<41>_UNCONNECTED , \NLW_blk00000001/blk00000005_C<40>_UNCONNECTED ,
\NLW_blk00000001/blk00000005_C<39>_UNCONNECTED , \NLW_blk00000001/blk00000005_C<38>_UNCONNECTED , \NLW_blk00000001/blk00000005_C<37>_UNCONNECTED ,
\NLW_blk00000001/blk00000005_C<36>_UNCONNECTED , \NLW_blk00000001/blk00000005_C<35>_UNCONNECTED , \NLW_blk00000001/blk00000005_C<34>_UNCONNECTED ,
\NLW_blk00000001/blk00000005_C<33>_UNCONNECTED , \NLW_blk00000001/blk00000005_C<32>_UNCONNECTED , \NLW_blk00000001/blk00000005_C<31>_UNCONNECTED ,
\NLW_blk00000001/blk00000005_C<30>_UNCONNECTED , \NLW_blk00000001/blk00000005_C<29>_UNCONNECTED , \NLW_blk00000001/blk00000005_C<28>_UNCONNECTED ,
\NLW_blk00000001/blk00000005_C<27>_UNCONNECTED , \NLW_blk00000001/blk00000005_C<26>_UNCONNECTED , \NLW_blk00000001/blk00000005_C<25>_UNCONNECTED ,
\NLW_blk00000001/blk00000005_C<24>_UNCONNECTED , \NLW_blk00000001/blk00000005_C<23>_UNCONNECTED , \NLW_blk00000001/blk00000005_C<22>_UNCONNECTED ,
\NLW_blk00000001/blk00000005_C<21>_UNCONNECTED , \NLW_blk00000001/blk00000005_C<20>_UNCONNECTED , \NLW_blk00000001/blk00000005_C<19>_UNCONNECTED ,
\NLW_blk00000001/blk00000005_C<18>_UNCONNECTED , \NLW_blk00000001/blk00000005_C<17>_UNCONNECTED , \NLW_blk00000001/blk00000005_C<16>_UNCONNECTED ,
\NLW_blk00000001/blk00000005_C<15>_UNCONNECTED , \NLW_blk00000001/blk00000005_C<14>_UNCONNECTED , \NLW_blk00000001/blk00000005_C<13>_UNCONNECTED ,
\NLW_blk00000001/blk00000005_C<12>_UNCONNECTED , \NLW_blk00000001/blk00000005_C<11>_UNCONNECTED , \NLW_blk00000001/blk00000005_C<10>_UNCONNECTED ,
\NLW_blk00000001/blk00000005_C<9>_UNCONNECTED , \NLW_blk00000001/blk00000005_C<8>_UNCONNECTED , \NLW_blk00000001/blk00000005_C<7>_UNCONNECTED ,
\NLW_blk00000001/blk00000005_C<6>_UNCONNECTED , \NLW_blk00000001/blk00000005_C<5>_UNCONNECTED , \NLW_blk00000001/blk00000005_C<4>_UNCONNECTED ,
\NLW_blk00000001/blk00000005_C<3>_UNCONNECTED , \NLW_blk00000001/blk00000005_C<2>_UNCONNECTED , \NLW_blk00000001/blk00000005_C<1>_UNCONNECTED ,
\NLW_blk00000001/blk00000005_C<0>_UNCONNECTED }),
.P({\blk00000001/sig000000c0 , \blk00000001/sig000000bf , \blk00000001/sig000000be , \blk00000001/sig000000bd , \blk00000001/sig000000bc ,
\blk00000001/sig000000bb , \blk00000001/sig000000ba , \blk00000001/sig000000b9 , \blk00000001/sig000000b8 , \blk00000001/sig000000b7 ,
\blk00000001/sig000000b6 , \blk00000001/sig000000b5 , \blk00000001/sig000000b4 , \blk00000001/sig000000b3 , \blk00000001/sig000000b2 ,
\blk00000001/sig000000b1 , \blk00000001/sig000000b0 , \blk00000001/sig000000af , \blk00000001/sig000000ae , \blk00000001/sig000000ad ,
\blk00000001/sig000000ac , \blk00000001/sig000000ab , \blk00000001/sig000000aa , \blk00000001/sig000000a9 , \blk00000001/sig000000a8 ,
\blk00000001/sig000000a7 , \blk00000001/sig000000a6 , \blk00000001/sig000000a5 , \blk00000001/sig000000a4 , \blk00000001/sig000000a3 ,
\blk00000001/sig000000a2 , \blk00000001/sig000000d1 , \blk00000001/sig000000d0 , \blk00000001/sig000000cf , \blk00000001/sig000000ce ,
\blk00000001/sig000000cd , \blk00000001/sig000000cc , \blk00000001/sig000000cb , \blk00000001/sig000000ca , \blk00000001/sig000000c9 ,
\blk00000001/sig000000c8 , \blk00000001/sig000000c7 , \blk00000001/sig000000c6 , \blk00000001/sig000000c5 , \blk00000001/sig000000c4 ,
\blk00000001/sig000000c3 , \blk00000001/sig000000c2 , \blk00000001/sig000000c1 }),
.OPMODE({\blk00000001/sig000000e4 , \blk00000001/sig000000e4 , \blk00000001/sig000000e4 , \blk00000001/sig000000e4 , \blk00000001/sig000000e4 ,
\blk00000001/sig000000e4 , \blk00000001/sig000000e4 , \blk00000001/sig00000071 }),
.D({\blk00000001/sig000000e4 , \blk00000001/sig000000e4 , \blk00000001/sig000000e4 , \blk00000001/sig000000e4 , \blk00000001/sig000000e4 ,
\blk00000001/sig000000e4 , \blk00000001/sig000000e4 , \blk00000001/sig000000e4 , \blk00000001/sig000000e4 , \blk00000001/sig000000e4 ,
\blk00000001/sig000000e4 , \blk00000001/sig000000e4 , \blk00000001/sig000000e4 , \blk00000001/sig000000e4 , \blk00000001/sig000000e4 ,
\blk00000001/sig000000e4 , \blk00000001/sig000000e4 , \blk00000001/sig000000e4 }),
.PCOUT({\blk00000001/sig000000a1 , \blk00000001/sig000000a0 , \blk00000001/sig0000009f , \blk00000001/sig0000009e , \blk00000001/sig0000009d ,
\blk00000001/sig0000009c , \blk00000001/sig0000009b , \blk00000001/sig0000009a , \blk00000001/sig00000099 , \blk00000001/sig00000098 ,
\blk00000001/sig00000097 , \blk00000001/sig00000096 , \blk00000001/sig00000095 , \blk00000001/sig00000094 , \blk00000001/sig00000093 ,
\blk00000001/sig00000092 , \blk00000001/sig00000091 , \blk00000001/sig00000090 , \blk00000001/sig0000008f , \blk00000001/sig0000008e ,
\blk00000001/sig0000008d , \blk00000001/sig0000008c , \blk00000001/sig0000008b , \blk00000001/sig0000008a , \blk00000001/sig00000089 ,
\blk00000001/sig00000088 , \blk00000001/sig00000087 , \blk00000001/sig00000086 , \blk00000001/sig00000085 , \blk00000001/sig00000084 ,
\blk00000001/sig00000083 , \blk00000001/sig00000082 , \blk00000001/sig00000081 , \blk00000001/sig00000080 , \blk00000001/sig0000007f ,
\blk00000001/sig0000007e , \blk00000001/sig0000007d , \blk00000001/sig0000007c , \blk00000001/sig0000007b , \blk00000001/sig0000007a ,
\blk00000001/sig00000079 , \blk00000001/sig00000078 , \blk00000001/sig00000077 , \blk00000001/sig00000076 , \blk00000001/sig00000075 ,
\blk00000001/sig00000074 , \blk00000001/sig00000073 , \blk00000001/sig00000072 }),
.A({\blk00000001/sig000000e4 , a[16], a[15], a[14], a[13], a[12], a[11], a[10], a[9], a[8], a[7], a[6], a[5], a[4], a[3], a[2], a[1], a[0]}),
.M({\NLW_blk00000001/blk00000005_M<35>_UNCONNECTED , \NLW_blk00000001/blk00000005_M<34>_UNCONNECTED ,
\NLW_blk00000001/blk00000005_M<33>_UNCONNECTED , \NLW_blk00000001/blk00000005_M<32>_UNCONNECTED , \NLW_blk00000001/blk00000005_M<31>_UNCONNECTED ,
\NLW_blk00000001/blk00000005_M<30>_UNCONNECTED , \NLW_blk00000001/blk00000005_M<29>_UNCONNECTED , \NLW_blk00000001/blk00000005_M<28>_UNCONNECTED ,
\NLW_blk00000001/blk00000005_M<27>_UNCONNECTED , \NLW_blk00000001/blk00000005_M<26>_UNCONNECTED , \NLW_blk00000001/blk00000005_M<25>_UNCONNECTED ,
\NLW_blk00000001/blk00000005_M<24>_UNCONNECTED , \NLW_blk00000001/blk00000005_M<23>_UNCONNECTED , \NLW_blk00000001/blk00000005_M<22>_UNCONNECTED ,
\NLW_blk00000001/blk00000005_M<21>_UNCONNECTED , \NLW_blk00000001/blk00000005_M<20>_UNCONNECTED , \NLW_blk00000001/blk00000005_M<19>_UNCONNECTED ,
\NLW_blk00000001/blk00000005_M<18>_UNCONNECTED , \NLW_blk00000001/blk00000005_M<17>_UNCONNECTED , \NLW_blk00000001/blk00000005_M<16>_UNCONNECTED ,
\NLW_blk00000001/blk00000005_M<15>_UNCONNECTED , \NLW_blk00000001/blk00000005_M<14>_UNCONNECTED , \NLW_blk00000001/blk00000005_M<13>_UNCONNECTED ,
\NLW_blk00000001/blk00000005_M<12>_UNCONNECTED , \NLW_blk00000001/blk00000005_M<11>_UNCONNECTED , \NLW_blk00000001/blk00000005_M<10>_UNCONNECTED ,
\NLW_blk00000001/blk00000005_M<9>_UNCONNECTED , \NLW_blk00000001/blk00000005_M<8>_UNCONNECTED , \NLW_blk00000001/blk00000005_M<7>_UNCONNECTED ,
\NLW_blk00000001/blk00000005_M<6>_UNCONNECTED , \NLW_blk00000001/blk00000005_M<5>_UNCONNECTED , \NLW_blk00000001/blk00000005_M<4>_UNCONNECTED ,
\NLW_blk00000001/blk00000005_M<3>_UNCONNECTED , \NLW_blk00000001/blk00000005_M<2>_UNCONNECTED , \NLW_blk00000001/blk00000005_M<1>_UNCONNECTED ,
\NLW_blk00000001/blk00000005_M<0>_UNCONNECTED })
);
DSP48A1 #(
.A0REG ( 1 ),
.A1REG ( 1 ),
.B0REG ( 1 ),
.B1REG ( 1 ),
.CARRYINREG ( 0 ),
.CARRYINSEL ( "OPMODE5" ),
.CREG ( 1 ),
.DREG ( 0 ),
.MREG ( 1 ),
.OPMODEREG ( 0 ),
.PREG ( 1 ),
.RSTTYPE ( "SYNC" ),
.CARRYOUTREG ( 0 ))
\blk00000001/blk00000004 (
.CECARRYIN(\blk00000001/sig000000e4 ),
.RSTC(\blk00000001/sig000000e4 ),
.RSTCARRYIN(\blk00000001/sig000000e4 ),
.CED(\blk00000001/sig000000e4 ),
.RSTD(\blk00000001/sig000000e4 ),
.CEOPMODE(\blk00000001/sig000000e4 ),
.CEC(ce),
.CARRYOUTF(\NLW_blk00000001/blk00000004_CARRYOUTF_UNCONNECTED ),
.RSTOPMODE(\blk00000001/sig000000e4 ),
.RSTM(\blk00000001/sig000000e4 ),
.CLK(clk),
.RSTB(\blk00000001/sig000000e4 ),
.CEM(ce),
.CEB(ce),
.CARRYIN(\blk00000001/sig000000e4 ),
.CEP(ce),
.CEA(ce),
.CARRYOUT(\NLW_blk00000001/blk00000004_CARRYOUT_UNCONNECTED ),
.RSTA(\blk00000001/sig000000e4 ),
.RSTP(\blk00000001/sig000000e4 ),
.B({\blk00000001/sig000000e3 , \blk00000001/sig000000e2 , \blk00000001/sig000000e1 , \blk00000001/sig000000e0 , \blk00000001/sig000000df ,
\blk00000001/sig000000de , \blk00000001/sig000000dd , \blk00000001/sig000000dc , \blk00000001/sig000000db , \blk00000001/sig000000da ,
\blk00000001/sig000000d9 , \blk00000001/sig000000d8 , \blk00000001/sig000000d7 , \blk00000001/sig000000d6 , \blk00000001/sig000000d5 ,
\blk00000001/sig000000d4 , \blk00000001/sig000000d3 , \blk00000001/sig000000d2 }),
.BCOUT({\NLW_blk00000001/blk00000004_BCOUT<17>_UNCONNECTED , \NLW_blk00000001/blk00000004_BCOUT<16>_UNCONNECTED ,
\NLW_blk00000001/blk00000004_BCOUT<15>_UNCONNECTED , \NLW_blk00000001/blk00000004_BCOUT<14>_UNCONNECTED ,
\NLW_blk00000001/blk00000004_BCOUT<13>_UNCONNECTED , \NLW_blk00000001/blk00000004_BCOUT<12>_UNCONNECTED ,
\NLW_blk00000001/blk00000004_BCOUT<11>_UNCONNECTED , \NLW_blk00000001/blk00000004_BCOUT<10>_UNCONNECTED ,
\NLW_blk00000001/blk00000004_BCOUT<9>_UNCONNECTED , \NLW_blk00000001/blk00000004_BCOUT<8>_UNCONNECTED ,
\NLW_blk00000001/blk00000004_BCOUT<7>_UNCONNECTED , \NLW_blk00000001/blk00000004_BCOUT<6>_UNCONNECTED ,
\NLW_blk00000001/blk00000004_BCOUT<5>_UNCONNECTED , \NLW_blk00000001/blk00000004_BCOUT<4>_UNCONNECTED ,
\NLW_blk00000001/blk00000004_BCOUT<3>_UNCONNECTED , \NLW_blk00000001/blk00000004_BCOUT<2>_UNCONNECTED ,
\NLW_blk00000001/blk00000004_BCOUT<1>_UNCONNECTED , \NLW_blk00000001/blk00000004_BCOUT<0>_UNCONNECTED }),
.PCIN({\blk00000001/sig000000a1 , \blk00000001/sig000000a0 , \blk00000001/sig0000009f , \blk00000001/sig0000009e , \blk00000001/sig0000009d ,
\blk00000001/sig0000009c , \blk00000001/sig0000009b , \blk00000001/sig0000009a , \blk00000001/sig00000099 , \blk00000001/sig00000098 ,
\blk00000001/sig00000097 , \blk00000001/sig00000096 , \blk00000001/sig00000095 , \blk00000001/sig00000094 , \blk00000001/sig00000093 ,
\blk00000001/sig00000092 , \blk00000001/sig00000091 , \blk00000001/sig00000090 , \blk00000001/sig0000008f , \blk00000001/sig0000008e ,
\blk00000001/sig0000008d , \blk00000001/sig0000008c , \blk00000001/sig0000008b , \blk00000001/sig0000008a , \blk00000001/sig00000089 ,
\blk00000001/sig00000088 , \blk00000001/sig00000087 , \blk00000001/sig00000086 , \blk00000001/sig00000085 , \blk00000001/sig00000084 ,
\blk00000001/sig00000083 , \blk00000001/sig00000082 , \blk00000001/sig00000081 , \blk00000001/sig00000080 , \blk00000001/sig0000007f ,
\blk00000001/sig0000007e , \blk00000001/sig0000007d , \blk00000001/sig0000007c , \blk00000001/sig0000007b , \blk00000001/sig0000007a ,
\blk00000001/sig00000079 , \blk00000001/sig00000078 , \blk00000001/sig00000077 , \blk00000001/sig00000076 , \blk00000001/sig00000075 ,
\blk00000001/sig00000074 , \blk00000001/sig00000073 , \blk00000001/sig00000072 }),
.C({\blk00000001/sig000000c0 , \blk00000001/sig000000c0 , \blk00000001/sig000000c0 , \blk00000001/sig000000c0 , \blk00000001/sig000000c0 ,
\blk00000001/sig000000c0 , \blk00000001/sig000000c0 , \blk00000001/sig000000c0 , \blk00000001/sig000000c0 , \blk00000001/sig000000c0 ,
\blk00000001/sig000000c0 , \blk00000001/sig000000c0 , \blk00000001/sig000000c0 , \blk00000001/sig000000c0 , \blk00000001/sig000000c0 ,
\blk00000001/sig000000c0 , \blk00000001/sig000000c0 , \blk00000001/sig000000c0 , \blk00000001/sig000000bf , \blk00000001/sig000000be ,
\blk00000001/sig000000bd , \blk00000001/sig000000bc , \blk00000001/sig000000bb , \blk00000001/sig000000ba , \blk00000001/sig000000b9 ,
\blk00000001/sig000000b8 , \blk00000001/sig000000b7 , \blk00000001/sig000000b6 , \blk00000001/sig000000b5 , \blk00000001/sig000000b4 ,
\blk00000001/sig000000b3 , \blk00000001/sig000000b2 , \blk00000001/sig000000b1 , \blk00000001/sig000000b0 , \blk00000001/sig000000af ,
\blk00000001/sig000000ae , \blk00000001/sig000000ad , \blk00000001/sig000000ac , \blk00000001/sig000000ab , \blk00000001/sig000000aa ,
\blk00000001/sig000000a9 , \blk00000001/sig000000a8 , \blk00000001/sig000000a7 , \blk00000001/sig000000a6 , \blk00000001/sig000000a5 ,
\blk00000001/sig000000a4 , \blk00000001/sig000000a3 , \blk00000001/sig000000a2 }),
.P({\NLW_blk00000001/blk00000004_P<47>_UNCONNECTED , \NLW_blk00000001/blk00000004_P<46>_UNCONNECTED ,
\NLW_blk00000001/blk00000004_P<45>_UNCONNECTED , \NLW_blk00000001/blk00000004_P<44>_UNCONNECTED , \NLW_blk00000001/blk00000004_P<43>_UNCONNECTED ,
\NLW_blk00000001/blk00000004_P<42>_UNCONNECTED , \NLW_blk00000001/blk00000004_P<41>_UNCONNECTED , \NLW_blk00000001/blk00000004_P<40>_UNCONNECTED ,
\NLW_blk00000001/blk00000004_P<39>_UNCONNECTED , \NLW_blk00000001/blk00000004_P<38>_UNCONNECTED , \NLW_blk00000001/blk00000004_P<37>_UNCONNECTED ,
\NLW_blk00000001/blk00000004_P<36>_UNCONNECTED , \NLW_blk00000001/blk00000004_P<35>_UNCONNECTED , \NLW_blk00000001/blk00000004_P<34>_UNCONNECTED ,
\NLW_blk00000001/blk00000004_P<33>_UNCONNECTED , \NLW_blk00000001/blk00000004_P<32>_UNCONNECTED , \NLW_blk00000001/blk00000004_P<31>_UNCONNECTED ,
\NLW_blk00000001/blk00000004_P<30>_UNCONNECTED , \NLW_blk00000001/blk00000004_P<29>_UNCONNECTED , \NLW_blk00000001/blk00000004_P<28>_UNCONNECTED ,
\NLW_blk00000001/blk00000004_P<27>_UNCONNECTED , \NLW_blk00000001/blk00000004_P<26>_UNCONNECTED , \NLW_blk00000001/blk00000004_P<25>_UNCONNECTED ,
\NLW_blk00000001/blk00000004_P<24>_UNCONNECTED , \NLW_blk00000001/blk00000004_P<23>_UNCONNECTED , \NLW_blk00000001/blk00000004_P<22>_UNCONNECTED ,
\NLW_blk00000001/blk00000004_P<21>_UNCONNECTED , \NLW_blk00000001/blk00000004_P<20>_UNCONNECTED , \NLW_blk00000001/blk00000004_P<19>_UNCONNECTED ,
\NLW_blk00000001/blk00000004_P<18>_UNCONNECTED , \NLW_blk00000001/blk00000004_P<17>_UNCONNECTED , \NLW_blk00000001/blk00000004_P<16>_UNCONNECTED ,
\NLW_blk00000001/blk00000004_P<15>_UNCONNECTED , \NLW_blk00000001/blk00000004_P<14>_UNCONNECTED , p[30], p[29], p[28], p[27], p[26], p[25], p[24],
p[23], p[22], p[21], p[20], p[19], p[18], p[17]}),
.OPMODE({\blk00000001/sig000000e4 , \blk00000001/sig000000e4 , \blk00000001/sig000000e4 , \blk00000001/sig000000e4 , \blk00000001/sig00000071 ,
\blk00000001/sig00000071 , \blk00000001/sig000000e4 , \blk00000001/sig00000071 }),
.D({\blk00000001/sig000000e4 , \blk00000001/sig000000e4 , \blk00000001/sig000000e4 , \blk00000001/sig000000e4 , \blk00000001/sig000000e4 ,
\blk00000001/sig000000e4 , \blk00000001/sig000000e4 , \blk00000001/sig000000e4 , \blk00000001/sig000000e4 , \blk00000001/sig000000e4 ,
\blk00000001/sig000000e4 , \blk00000001/sig000000e4 , \blk00000001/sig000000e4 , \blk00000001/sig000000e4 , \blk00000001/sig000000e4 ,
\blk00000001/sig000000e4 , \blk00000001/sig000000e4 , \blk00000001/sig000000e4 }),
.PCOUT({\blk00000001/sig00000041 , \blk00000001/sig00000042 , \blk00000001/sig00000043 , \blk00000001/sig00000044 , \blk00000001/sig00000045 ,
\blk00000001/sig00000046 , \blk00000001/sig00000047 , \blk00000001/sig00000048 , \blk00000001/sig00000049 , \blk00000001/sig0000004a ,
\blk00000001/sig0000004b , \blk00000001/sig0000004c , \blk00000001/sig0000004d , \blk00000001/sig0000004e , \blk00000001/sig0000004f ,
\blk00000001/sig00000050 , \blk00000001/sig00000051 , \blk00000001/sig00000052 , \blk00000001/sig00000053 , \blk00000001/sig00000054 ,
\blk00000001/sig00000055 , \blk00000001/sig00000056 , \blk00000001/sig00000057 , \blk00000001/sig00000058 , \blk00000001/sig00000059 ,
\blk00000001/sig0000005a , \blk00000001/sig0000005b , \blk00000001/sig0000005c , \blk00000001/sig0000005d , \blk00000001/sig0000005e ,
\blk00000001/sig0000005f , \blk00000001/sig00000060 , \blk00000001/sig00000061 , \blk00000001/sig00000062 , \blk00000001/sig00000063 ,
\blk00000001/sig00000064 , \blk00000001/sig00000065 , \blk00000001/sig00000066 , \blk00000001/sig00000067 , \blk00000001/sig00000068 ,
\blk00000001/sig00000069 , \blk00000001/sig0000006a , \blk00000001/sig0000006b , \blk00000001/sig0000006c , \blk00000001/sig0000006d ,
\blk00000001/sig0000006e , \blk00000001/sig0000006f , \blk00000001/sig00000070 }),
.A({\blk00000001/sig000000e6 , \blk00000001/sig000000e6 , \blk00000001/sig000000e6 , \blk00000001/sig000000e6 , \blk00000001/sig000000e6 ,
\blk00000001/sig000000e6 , \blk00000001/sig000000e6 , \blk00000001/sig000000e6 , \blk00000001/sig000000e6 , \blk00000001/sig000000e6 ,
\blk00000001/sig000000e6 , \blk00000001/sig000000e6 , \blk00000001/sig000000e6 , \blk00000001/sig000000e6 , \blk00000001/sig000000e6 ,
\blk00000001/sig000000e6 , \blk00000001/sig000000e6 , \blk00000001/sig000000e5 }),
.M({\NLW_blk00000001/blk00000004_M<35>_UNCONNECTED , \NLW_blk00000001/blk00000004_M<34>_UNCONNECTED ,
\NLW_blk00000001/blk00000004_M<33>_UNCONNECTED , \NLW_blk00000001/blk00000004_M<32>_UNCONNECTED , \NLW_blk00000001/blk00000004_M<31>_UNCONNECTED ,
\NLW_blk00000001/blk00000004_M<30>_UNCONNECTED , \NLW_blk00000001/blk00000004_M<29>_UNCONNECTED , \NLW_blk00000001/blk00000004_M<28>_UNCONNECTED ,
\NLW_blk00000001/blk00000004_M<27>_UNCONNECTED , \NLW_blk00000001/blk00000004_M<26>_UNCONNECTED , \NLW_blk00000001/blk00000004_M<25>_UNCONNECTED ,
\NLW_blk00000001/blk00000004_M<24>_UNCONNECTED , \NLW_blk00000001/blk00000004_M<23>_UNCONNECTED , \NLW_blk00000001/blk00000004_M<22>_UNCONNECTED ,
\NLW_blk00000001/blk00000004_M<21>_UNCONNECTED , \NLW_blk00000001/blk00000004_M<20>_UNCONNECTED , \NLW_blk00000001/blk00000004_M<19>_UNCONNECTED ,
\NLW_blk00000001/blk00000004_M<18>_UNCONNECTED , \NLW_blk00000001/blk00000004_M<17>_UNCONNECTED , \NLW_blk00000001/blk00000004_M<16>_UNCONNECTED ,
\NLW_blk00000001/blk00000004_M<15>_UNCONNECTED , \NLW_blk00000001/blk00000004_M<14>_UNCONNECTED , \NLW_blk00000001/blk00000004_M<13>_UNCONNECTED ,
\NLW_blk00000001/blk00000004_M<12>_UNCONNECTED , \NLW_blk00000001/blk00000004_M<11>_UNCONNECTED , \NLW_blk00000001/blk00000004_M<10>_UNCONNECTED ,
\NLW_blk00000001/blk00000004_M<9>_UNCONNECTED , \NLW_blk00000001/blk00000004_M<8>_UNCONNECTED , \NLW_blk00000001/blk00000004_M<7>_UNCONNECTED ,
\NLW_blk00000001/blk00000004_M<6>_UNCONNECTED , \NLW_blk00000001/blk00000004_M<5>_UNCONNECTED , \NLW_blk00000001/blk00000004_M<4>_UNCONNECTED ,
\NLW_blk00000001/blk00000004_M<3>_UNCONNECTED , \NLW_blk00000001/blk00000004_M<2>_UNCONNECTED , \NLW_blk00000001/blk00000004_M<1>_UNCONNECTED ,
\NLW_blk00000001/blk00000004_M<0>_UNCONNECTED })
);
GND \blk00000001/blk00000003 (
.G(\blk00000001/sig000000e4 )
);
VCC \blk00000001/blk00000002 (
.P(\blk00000001/sig00000071 )
);
// synthesis translate_on
endmodule
|
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
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