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module stratixv_pll_dll_output #( // parameter declaration and default value assignemnt parameter pll_dll_src = "vss" //Valid values: c_0_cnt|c_1_cnt|c_2_cnt|c_3_cnt|c_4_cnt|c_5_cnt|c_6_cnt|c_7_cnt|c_8_cnt|c_9_cnt|c_10_cnt|c_11_cnt|c_12_cnt|c_13_cnt|c_14_cnt|c_15_cnt|c_16_cnt|c_17_cnt|clkin_0|clkin_1|clkin_2|clkin_3|vss ) ( //input and output port declaration input [ 17:0 ] cclk, input [ 3:0 ] clkin, output [ 0:0 ] clkout ); stratixv_pll_dll_output_encrypted #( .pll_dll_src(pll_dll_src) ) stratixv_pll_dll_output_encrypted_inst ( .cclk(cclk), .clkin(clkin), .clkout(clkout) ); endmodule
module stratixv_pll_dpa_output #( // parameter declaration and default value assignemnt parameter output_clock_frequency = "", //Valid values: parameter pll_vcoph_div = 1 //Valid values: 1|2|4 ) ( //input and output port declaration input [ 0:0 ] pd, input [ 7:0 ] phin, output [ 7:0 ] phout ); stratixv_pll_dpa_output_encrypted #( .output_clock_frequency(output_clock_frequency), .pll_vcoph_div(pll_vcoph_div) ) stratixv_pll_dpa_output_encrypted_inst ( .pd(pd), .phin(phin), .phout(phout) ); endmodule
module stratixv_pll_extclk_output #( // parameter declaration and default value assignemnt parameter pll_extclk_cnt_src = "vss", //Valid values: c_0_cnt|c_1_cnt|c_2_cnt|c_3_cnt|c_4_cnt|c_5_cnt|c_6_cnt|c_7_cnt|c_8_cnt|c_9_cnt|c_10_cnt|c_11_cnt|c_12_cnt|c_13_cnt|c_14_cnt|c_15_cnt|c_16_cnt|c_17_cnt|m0_cnt|m1_cnt|clkin0|clkin1|clkin2|clkin3|vss parameter pll_extclk_enable = "true", //Valid values: false|true parameter pll_extclk_invert = "false" //Valid values: false|true ) ( //input and output port declaration input [ 17:0 ] cclk, input [ 0:0 ] clken, input [ 0:0 ] mcnt0, input [ 0:0 ] mcnt1, output [ 0:0 ] extclk ); stratixv_pll_extclk_output_encrypted #( .pll_extclk_cnt_src(pll_extclk_cnt_src), .pll_extclk_enable(pll_extclk_enable), .pll_extclk_invert(pll_extclk_invert) ) stratixv_pll_extclk_output_encrypted_inst ( .cclk(cclk), .clken(clken), .mcnt0(mcnt0), .mcnt1(mcnt1), .extclk(extclk) ); endmodule
module stratixv_pll_lvds_output #( // parameter declaration and default value assignemnt parameter pll_loaden_coarse_dly = "0 ps", //Valid values: 0 ps|200 ps|400 ps|600 ps|800 ps|1000 ps parameter pll_loaden_enable_disable = "false", //Valid values: false|true parameter pll_loaden_fine_dly = "0 ps", //Valid values: 0 ps|50 ps|100 ps|150 ps parameter pll_lvdsclk_coarse_dly = "0 ps", //Valid values: 0 ps|200 ps|400 ps|600 ps|800 ps|1000 ps parameter pll_lvdsclk_enable_disable = "false", //Valid values: false|true parameter pll_lvdsclk_fine_dly = "0 ps" //Valid values: 0 ps|50 ps|100 ps|150 ps ) ( //input and output port declaration input [ 1:0 ] ccout, output [ 0:0 ] loaden, output [ 0:0 ] lvdsclk ); stratixv_pll_lvds_output_encrypted #( .pll_loaden_coarse_dly(pll_loaden_coarse_dly), .pll_loaden_enable_disable(pll_loaden_enable_disable), .pll_loaden_fine_dly(pll_loaden_fine_dly), .pll_lvdsclk_coarse_dly(pll_lvdsclk_coarse_dly), .pll_lvdsclk_enable_disable(pll_lvdsclk_enable_disable), .pll_lvdsclk_fine_dly(pll_lvdsclk_fine_dly) ) stratixv_pll_lvds_output_encrypted_inst ( .ccout(ccout), .loaden(loaden), .lvdsclk(lvdsclk) ); endmodule
module stratixv_pll_output_counter #( // parameter declaration and default value assignemnt parameter output_clock_frequency = "", //Valid values: parameter phase_shift = "", //Valid values: parameter duty_cycle = 50, //Valid values: 1..99 parameter c_cnt_coarse_dly = "0 ps", //Valid values: 0 ps|200 ps|400 ps|600 ps|800 ps|1000 ps parameter c_cnt_fine_dly = "0 ps", //Valid values: 0 ps|50 ps|100 ps|150 ps parameter c_cnt_in_src = "test_clk0", //Valid values: ph_mux_clk|cscd_clk|test_clk0|test_clk1 parameter c_cnt_ph_mux_prst = 0, //Valid values: 0..7 parameter c_cnt_prst = 1, //Valid values: 1..256 parameter cnt_fpll_src = "fpll_0", //Valid values: fpll_0|fpll_1 parameter dprio0_cnt_bypass_en = "false", //Valid values: false|true parameter dprio0_cnt_hi_div = 1, //Valid values: 1..256 parameter dprio0_cnt_lo_div = 1, //Valid values: 1..256 parameter dprio0_cnt_odd_div_even_duty_en = "false", //Valid values: false|true parameter dprio1_cnt_bypass_en = "false", //Valid values: false|true parameter dprio1_cnt_hi_div = 1, //Valid values: 1..256 parameter dprio1_cnt_lo_div = 1, //Valid values: 1..256 parameter dprio1_cnt_odd_div_even_duty_en = "false" //Valid values: false|true ) ( //input and output port declaration input [ 0:0 ] cascadein, input [ 0:0 ] nen0, input [ 0:0 ] nen1, input [ 0:0 ] shift0, input [ 0:0 ] shift1, input [ 0:0 ] shiftdone0i, input [ 0:0 ] shiftdone1i, input [ 0:0 ] shiften, input [ 0:0 ] tclk0, input [ 0:0 ] tclk1, input [ 0:0 ] up0, input [ 0:0 ] up1, input [ 7:0 ] vco0ph, input [ 7:0 ] vco1ph, output [ 0:0 ] cascadeout, output [ 0:0 ] divclk, output [ 0:0 ] shiftdone0o, output [ 0:0 ] shiftdone1o ); stratixv_pll_output_counter_encrypted #( .output_clock_frequency(output_clock_frequency), .phase_shift(phase_shift), .duty_cycle(duty_cycle), .c_cnt_coarse_dly(c_cnt_coarse_dly), .c_cnt_fine_dly(c_cnt_fine_dly), .c_cnt_in_src(c_cnt_in_src), .c_cnt_ph_mux_prst(c_cnt_ph_mux_prst), .c_cnt_prst(c_cnt_prst), .cnt_fpll_src(cnt_fpll_src), .dprio0_cnt_bypass_en(dprio0_cnt_bypass_en), .dprio0_cnt_hi_div(dprio0_cnt_hi_div), .dprio0_cnt_lo_div(dprio0_cnt_lo_div), .dprio0_cnt_odd_div_even_duty_en(dprio0_cnt_odd_div_even_duty_en), .dprio1_cnt_bypass_en(dprio1_cnt_bypass_en), .dprio1_cnt_hi_div(dprio1_cnt_hi_div), .dprio1_cnt_lo_div(dprio1_cnt_lo_div), .dprio1_cnt_odd_div_even_duty_en(dprio1_cnt_odd_div_even_duty_en) ) stratixv_pll_output_counter_encrypted_inst ( .cascadein(cascadein), .nen0(nen0), .nen1(nen1), .shift0(shift0), .shift1(shift1), .shiftdone0i(shiftdone0i), .shiftdone1i(shiftdone1i), .shiften(shiften), .tclk0(tclk0), .tclk1(tclk1), .up0(up0), .up1(up1), .vco0ph(vco0ph), .vco1ph(vco1ph), .cascadeout(cascadeout), .divclk(divclk), .shiftdone0o(shiftdone0o), .shiftdone1o(shiftdone1o) ); endmodule
module stratixv_pll_reconfig ( //input and output port declaration input [ 5:0 ] addr, input [ 0:0 ] atpgmode, input [ 1:0 ] byteen, input [ 0:0 ] clk, input [ 0:0 ] cntnen, input [ 4:0 ] cntsel, input [ 15:0 ] din, input [ 0:0 ] fpllcsrtest, input [ 0:0 ] iocsrclkin, input [ 0:0 ] iocsrdatain, input [ 0:0 ] iocsren, input [ 0:0 ] iocsrrstn, input [ 0:0 ] mdiodis, input [ 7:0 ] mhi, input [ 0:0 ] phaseen, input [ 0:0 ] read, input [ 0:0 ] rstn, input [ 0:0 ] scanen, input [ 0:0 ] sershiftload, input [ 0:0 ] shiftdonei, input [ 0:0 ] updn, input [ 0:0 ] write, output [ 0:0 ] blockselect, output [ 15:0 ] dout, output [ 815:0 ] dprioout, output [ 0:0 ] iocsrdataout, output [ 0:0 ] iocsrenbuf, output [ 0:0 ] iocsrrstnbuf, output [ 0:0 ] phasedone, output [ 0:0 ] shift, output [ 17:0 ] shiften, output [ 0:0 ] shiftenm, output [ 0:0 ] up ); stratixv_pll_reconfig_encrypted stratixv_pll_reconfig_encrypted_inst ( .addr(addr), .atpgmode ( atpgmode ), .byteen(byteen), .clk(clk), .cntnen(cntnen), .cntsel(cntsel), .din(din), .fpllcsrtest ( fpllcsrtest ), .iocsrclkin(iocsrclkin), .iocsrdatain(iocsrdatain), .iocsren(iocsren), .iocsrrstn(iocsrrstn), .mdiodis(mdiodis), .phaseen(phaseen), .read(read), .rstn(rstn), .scanen(scanen), .sershiftload(sershiftload), .shiftdonei(shiftdonei), .updn(updn), .write(write), .blockselect(blockselect), .dout(dout), .dprioout(dprioout), .iocsrdataout(iocsrdataout), .iocsrenbuf(iocsrenbuf), .iocsrrstnbuf(iocsrrstnbuf), .phasedone(phasedone), .shift(shift), .shiften(shiften), .shiftenm(shiftenm), .up(up) ); endmodule
module stratixv_pll_refclk_select #( // parameter declaration and default value assignemnt parameter pll_auto_clk_sw_en = "false", //Valid values: false|true parameter pll_clk_loss_edge = "both_edges", //Valid values: both_edges|rising_edge parameter pll_clk_loss_sw_en = "false", //Valid values: false|true parameter pll_clk_sw_dly = 0, //Valid values: 0..7 parameter pll_clkin_0_src = "ref_clk0", //Valid values: core_ref_clk|adj_pll_clk|ref_clk0|ref_clk1|clk_0|clk_1|clk_2|clk_3|vss|cmu_iqclk|iqtxrxclk|fpll|pll_iqclk parameter pll_clkin_1_src = "ref_clk1", //Valid values: core_ref_clk|adj_pll_clk|ref_clk0|ref_clk1|clk_0|clk_1|clk_2|clk_3|vss|cmu_iqclk|iqtxrxclk|fpll|pll_iqclk parameter pll_manu_clk_sw_en = "false", //Valid values: false|true parameter pll_sw_refclk_src = "clk_0" //Valid values: clk_0|clk_1 ) ( //input and output port declaration input [ 0:0 ] adjpllin, input [ 0:0 ] cclk, input [ 3:0 ] clkin, input [ 0:0 ] coreclkin, input [ 0:0 ] extswitch, input [ 0:0 ] iqtxrxclkin, input [ 0:0 ] plliqclkin, input [ 1:0 ] refiqclk, input [ 0:0 ] rxiqclkin, output [ 0:0 ] clk0bad, output [ 0:0 ] clk1bad, output [ 0:0 ] clkout, output [ 0:0 ] extswitchbuf, output [ 0:0 ] pllclksel ); stratixv_pll_refclk_select_encrypted #( .pll_auto_clk_sw_en(pll_auto_clk_sw_en), .pll_clk_loss_edge(pll_clk_loss_edge), .pll_clk_loss_sw_en(pll_clk_loss_sw_en), .pll_clk_sw_dly(pll_clk_sw_dly), .pll_clkin_0_src(pll_clkin_0_src), .pll_clkin_1_src(pll_clkin_1_src), .pll_manu_clk_sw_en(pll_manu_clk_sw_en), .pll_sw_refclk_src(pll_sw_refclk_src) ) stratixv_pll_refclk_select_encrypted_inst ( .adjpllin(adjpllin), .cclk(cclk), .clkin(clkin), .coreclkin(coreclkin), .extswitch(extswitch), .iqtxrxclkin(iqtxrxclkin), .plliqclkin(plliqclkin), .refiqclk(refiqclk), .rxiqclkin(rxiqclkin), .clk0bad(clk0bad), .clk1bad(clk1bad), .clkout(clkout), .extswitchbuf(extswitchbuf), .pllclksel(pllclksel) ); endmodule
module stratixv_half_rate_input ( datain, directin, clk, areset, dataoutbypass, dataout, dffin); parameter power_up = "low"; parameter async_mode = "no_reset"; parameter use_dataoutbypass = "false"; input [1:0] datain; input directin; input clk; input areset; input dataoutbypass; output [3:0] dataout; output [1:0] dffin; stratixv_half_rate_input_encrypted inst ( .datain(datain), .directin(directin), .clk(clk), .areset(areset), .dataoutbypass(dataoutbypass), .dataout(dataout), .dffin(dffin) ); defparam inst.power_up = power_up; defparam inst.async_mode = async_mode; defparam inst.use_dataoutbypass = use_dataoutbypass; endmodule
module stratixv_input_phase_alignment ( datain, levelingclk, zerophaseclk, areset, enainputcycledelay, enaphasetransferreg, dataout, dffin, dff1t, dffphasetransfer); parameter power_up = "low"; parameter async_mode = "no_reset"; parameter add_input_cycle_delay = "false"; parameter bypass_output_register = "false"; parameter add_phase_transfer_reg = "false"; parameter lpm_type = "stratixv_input_phase_alignment"; input datain; input levelingclk; input zerophaseclk; input areset; input enainputcycledelay; input enaphasetransferreg; output dataout; output dffin; output dff1t; output dffphasetransfer; stratixv_input_phase_alignment_encrypted inst ( .datain(datain), .levelingclk(levelingclk), .zerophaseclk(zerophaseclk), .areset(areset), .enainputcycledelay(enainputcycledelay), .enaphasetransferreg(enaphasetransferreg), .dataout(dataout), .dffin(dffin), .dff1t(dff1t), .dffphasetransfer(dffphasetransfer) ); defparam inst.power_up = power_up; defparam inst.async_mode = async_mode; defparam inst.add_input_cycle_delay = add_input_cycle_delay; defparam inst.bypass_output_register = bypass_output_register; defparam inst.add_phase_transfer_reg = add_phase_transfer_reg; defparam inst.lpm_type = lpm_type; endmodule
module stratixv_io_clock_divider ( clk, phaseinvertctrl, masterin, clkout, slaveout); parameter power_up = "low"; parameter invert_phase = "false"; parameter use_masterin = "false"; parameter lpm_type = "stratixv_io_clock_divider"; input clk; input phaseinvertctrl; input masterin; output clkout; output slaveout; stratixv_io_clock_divider_encrypted inst ( .clk(clk), .phaseinvertctrl(phaseinvertctrl), .masterin(masterin), .clkout(clkout), .slaveout(slaveout) ); defparam inst.power_up = power_up; defparam inst.invert_phase = invert_phase; defparam inst.use_masterin = use_masterin; defparam inst.lpm_type = lpm_type; endmodule
module stratixv_io_config ( datain, clk, ena, update, outputdelaysetting1, outputdelaysetting2, padtoinputregisterdelaysetting, padtoinputregisterrisefalldelaysetting, inputclkdelaysetting, inputclkndelaysetting, dutycycledelaymode, dutycycledelaysetting, dataout); parameter lpm_type = "stratixv_io_config"; input datain; input clk; input ena; input update; output [5:0] outputdelaysetting1; output [5:0] outputdelaysetting2; output [5:0] padtoinputregisterdelaysetting; output [5:0] padtoinputregisterrisefalldelaysetting; output [1:0] inputclkdelaysetting; output [1:0] inputclkndelaysetting; output dutycycledelaymode; output [3:0] dutycycledelaysetting; output dataout; stratixv_io_config_encrypted inst ( .datain(datain), .clk(clk), .ena(ena), .update(update), .outputdelaysetting1(outputdelaysetting1), .outputdelaysetting2(outputdelaysetting2), .padtoinputregisterdelaysetting(padtoinputregisterdelaysetting), .padtoinputregisterrisefalldelaysetting(padtoinputregisterrisefalldelaysetting), .inputclkdelaysetting(inputclkdelaysetting), .inputclkndelaysetting(inputclkndelaysetting), .dutycycledelaymode(dutycycledelaymode), .dutycycledelaysetting(dutycycledelaysetting), .dataout(dataout) ); defparam inst.lpm_type = lpm_type; endmodule
module stratixv_leveling_delay_chain ( clkin, delayctrlin, clkout); parameter physical_clock_source = "dqs"; parameter sim_buffer_intrinsic_delay = 175; parameter sim_buffer_delay_increment = 10; parameter use_duty_cycle_correction = "false"; parameter test_mode = "false"; input clkin; input [6:0] delayctrlin; output [3:0] clkout; stratixv_leveling_delay_chain_encrypted inst ( .clkin(clkin), .delayctrlin(delayctrlin), .clkout(clkout) ); //defparam inst.use_duty_cycle_correction = use_duty_cycle_correction; defparam inst.physical_clock_source = physical_clock_source; defparam inst.sim_buffer_intrinsic_delay = sim_buffer_intrinsic_delay; defparam inst.sim_buffer_delay_increment = sim_buffer_delay_increment; endmodule
module stratixv_lvds_rx ( clock0, datain, enable0, dpareset, dpahold, dpaswitch, fiforeset, bitslip, bitslipreset, serialfbk, devclrn, devpor, dpaclkin, dataout, dpalock, bitslipmax, serialdataout, postdpaserialdataout, divfwdclk, dpaclkout, observableout); parameter data_align_rollover = 2; parameter enable_dpa = "false"; parameter lose_lock_on_one_change = "false"; parameter reset_fifo_at_first_lock = "true"; parameter align_to_rising_edge_only = "true"; parameter use_serial_feedback_input = "off"; parameter dpa_debug = "false"; parameter x_on_bitslip = "true"; parameter enable_soft_cdr = "false"; parameter dpa_clock_output_phase_shift = 0; parameter enable_dpa_initial_phase_selection = "false"; parameter dpa_initial_phase_value = 0; parameter enable_dpa_align_to_rising_edge_only = "false"; parameter net_ppm_variation = 0; parameter is_negative_ppm_drift = "false"; parameter rx_input_path_delay_engineering_bits = 2; parameter lpm_type = "stratixv_lvds_rx"; parameter data_width = 10; input clock0; input datain; input enable0; input dpareset; input dpahold; input dpaswitch; input fiforeset; input bitslip; input bitslipreset; input serialfbk; input devclrn; input devpor; input [7:0] dpaclkin; output [data_width-1:0] dataout; output dpalock; output bitslipmax; output serialdataout; output postdpaserialdataout; output divfwdclk; output dpaclkout; output [3:0] observableout; stratixv_lvds_rx_encrypted inst ( .clock0(clock0), .datain(datain), .enable0(enable0), .dpareset(dpareset), .dpahold(dpahold), .dpaswitch(dpaswitch), .fiforeset(fiforeset), .bitslip(bitslip), .bitslipreset(bitslipreset), .serialfbk(serialfbk), .devclrn(devclrn), .devpor(devpor), .dpaclkin(dpaclkin), .dataout(dataout), .dpalock(dpalock), .bitslipmax(bitslipmax), .serialdataout(serialdataout), .postdpaserialdataout(postdpaserialdataout), .divfwdclk(divfwdclk), .dpaclkout(dpaclkout), .observableout(observableout) ); defparam inst.data_align_rollover = data_align_rollover; defparam inst.enable_dpa = enable_dpa; defparam inst.lose_lock_on_one_change = lose_lock_on_one_change; defparam inst.reset_fifo_at_first_lock = reset_fifo_at_first_lock; defparam inst.align_to_rising_edge_only = align_to_rising_edge_only; defparam inst.use_serial_feedback_input = use_serial_feedback_input; defparam inst.dpa_debug = dpa_debug; defparam inst.x_on_bitslip = x_on_bitslip; defparam inst.enable_soft_cdr = enable_soft_cdr; defparam inst.dpa_clock_output_phase_shift = dpa_clock_output_phase_shift; defparam inst.enable_dpa_initial_phase_selection = enable_dpa_initial_phase_selection; defparam inst.dpa_initial_phase_value = dpa_initial_phase_value; defparam inst.enable_dpa_align_to_rising_edge_only = enable_dpa_align_to_rising_edge_only; defparam inst.net_ppm_variation = net_ppm_variation; defparam inst.is_negative_ppm_drift = is_negative_ppm_drift; defparam inst.rx_input_path_delay_engineering_bits = rx_input_path_delay_engineering_bits; defparam inst.lpm_type = lpm_type; defparam inst.data_width = data_width; endmodule
module stratixv_lvds_tx ( datain, clock0, enable0, serialdatain, postdpaserialdatain, devclrn, devpor, dpaclkin, dataout, serialfdbkout, observableout); parameter bypass_serializer = "false"; parameter invert_clock = "false"; parameter use_falling_clock_edge = "false"; parameter use_serial_data_input = "false"; parameter use_post_dpa_serial_data_input = "false"; parameter is_used_as_outclk = "false"; parameter tx_output_path_delay_engineering_bits = -1; parameter enable_dpaclk_to_lvdsout = "false"; parameter lpm_type = "stratixv_lvds_tx"; parameter data_width = 10; input [data_width-1:0] datain; input clock0; input enable0; input serialdatain; input postdpaserialdatain; input devclrn; input devpor; input dpaclkin; output dataout; output serialfdbkout; output [2:0] observableout; stratixv_lvds_tx_encrypted inst ( .datain(datain), .clock0(clock0), .enable0(enable0), .serialdatain(serialdatain), .postdpaserialdatain(postdpaserialdatain), .devclrn(devclrn), .devpor(devpor), .dpaclkin(dpaclkin), .dataout(dataout), .serialfdbkout(serialfdbkout), .observableout(observableout) ); defparam inst.bypass_serializer = bypass_serializer; defparam inst.invert_clock = invert_clock; defparam inst.use_falling_clock_edge = use_falling_clock_edge; defparam inst.use_serial_data_input = use_serial_data_input; defparam inst.use_post_dpa_serial_data_input = use_post_dpa_serial_data_input; defparam inst.is_used_as_outclk = is_used_as_outclk; defparam inst.tx_output_path_delay_engineering_bits = tx_output_path_delay_engineering_bits; defparam inst.enable_dpaclk_to_lvdsout = enable_dpaclk_to_lvdsout; defparam inst.lpm_type = lpm_type; defparam inst.data_width = data_width; endmodule
module stratixv_output_alignment ( datain, clk, areset, sreset, enaoutputcycledelay, enaphasetransferreg, dataout, dffin, dff1t, dff2t, dffphasetransfer); parameter power_up = "low"; parameter async_mode = "none"; parameter sync_mode = "none"; parameter add_output_cycle_delay = "false"; parameter add_phase_transfer_reg = "false"; input datain; input clk; input areset; input sreset; input [2:0] enaoutputcycledelay; input enaphasetransferreg; output dataout; output dffin; output dff1t; output dff2t; output dffphasetransfer; stratixv_output_alignment_encrypted inst ( .datain(datain), .clk(clk), .areset(areset), .sreset(sreset), .enaoutputcycledelay(enaoutputcycledelay), .enaphasetransferreg(enaphasetransferreg), .dataout(dataout), .dffin(dffin), .dff1t(dff1t), .dff2t(dff2t), .dffphasetransfer(dffphasetransfer) ); defparam inst.power_up = power_up; defparam inst.async_mode = async_mode; defparam inst.sync_mode = sync_mode; defparam inst.add_output_cycle_delay = add_output_cycle_delay; defparam inst.add_phase_transfer_reg = add_phase_transfer_reg; endmodule
module stratixv_termination_logic ( s2pload, serdata, scanenable, scanclk, enser, seriesterminationcontrol, parallelterminationcontrol ); parameter lpm_type = "stratixv_termination_logic"; parameter a_iob_oct_test = "a_iob_oct_test_off"; input s2pload; input serdata; input scanenable; input scanclk; input enser; output [15 : 0] parallelterminationcontrol; output [15 : 0] seriesterminationcontrol; stratixv_termination_logic_encrypted inst ( .s2pload(s2pload), .serdata(serdata), .scanenable(scanenable), .scanclk(scanclk), .enser(enser), .seriesterminationcontrol(seriesterminationcontrol), .parallelterminationcontrol(parallelterminationcontrol) ); defparam inst.lpm_type = lpm_type; defparam inst.a_iob_oct_test = a_iob_oct_test; endmodule
module stratixv_termination ( rzqin, enserusr, nclrusr, clkenusr, clkusr, scanen, serdatafromcore, scanclk, otherenser, serdatain, serdataout, enserout, compoutrup, compoutrdn, serdatatocore, scanin, scanout, clkusrdftout); parameter lpm_type = "stratixv_termination"; parameter a_oct_cal_mode = "a_oct_cal_mode_none"; parameter a_oct_user_oct = "a_oct_user_oct_off"; parameter a_oct_nclrusr_inv = "a_oct_nclrusr_inv_off"; parameter a_oct_pwrdn = "a_oct_pwrdn_on"; parameter a_oct_intosc = "a_oct_intosc_none"; parameter a_oct_test_0 = "a_oct_test_0_off"; parameter a_oct_test_1 = "a_oct_test_1_off"; parameter a_oct_test_4 = "a_oct_test_4_off"; parameter a_oct_test_5 = "a_oct_test_5_off"; parameter a_oct_pllbiasen = "a_oct_pllbiasen_dis"; parameter a_oct_clkenusr_inv = "a_oct_clkenusr_inv_off"; parameter a_oct_enserusr_inv = "a_oct_enserusr_inv_off"; parameter a_oct_scanen_inv = "a_oct_scanen_inv_off"; parameter a_oct_vrefl = "a_oct_vrefl_m"; parameter a_oct_vrefh = "a_oct_vrefh_m"; parameter a_oct_rsmult = "a_oct_rsmult_1"; parameter a_oct_rsadjust = "a_oct_rsadjust_none"; parameter a_oct_calclr = "a_oct_calclr_off"; parameter a_oct_rshft_rup = "a_oct_rshft_rup_enable"; parameter a_oct_rshft_rdn = "a_oct_rshft_rdn_enable"; parameter a_oct_usermode = "false"; input rzqin; input enserusr; input nclrusr; input clkenusr; input clkusr; input scanen; input serdatafromcore; input serdatain; input scanclk; input [9 : 0] otherenser; output serdataout; output enserout; output compoutrup; output compoutrdn; output serdatatocore; input scanin; output scanout; output clkusrdftout; stratixv_termination_encrypted inst ( .rzqin(rzqin), .enserusr(enserusr), .nclrusr(nclrusr), .clkenusr(clkenusr), .clkusr(clkusr), .scanen(scanen), .serdatafromcore(serdatafromcore), .scanclk(scanclk), .otherenser(otherenser), .serdataout(serdataout), .enserout(enserout), .compoutrup(compoutrup), .compoutrdn(compoutrdn), .serdatatocore(serdatatocore), .scanin(scanin), .scanout(scanout), .clkusrdftout(clkusrdftout)); defparam inst.lpm_type = lpm_type; /* defparam inst.a_oct_nclrusr_inv = a_oct_nclrusr_inv; defparam inst.a_oct_pwrdn = a_oct_pwrdn; defparam inst.a_oct_clkdiv = a_oct_clkdiv; defparam inst.a_oct_intosc = a_oct_intosc; defparam inst.a_oct_vref = a_oct_vref; defparam inst.a_oct_test_0 = a_oct_test_0; defparam inst.a_oct_test_1 = a_oct_test_1; defparam inst.a_oct_test_2 = a_oct_test_2; defparam inst.a_oct_test_3 = a_oct_test_3; defparam inst.a_oct_test_4 = a_oct_test_4; defparam inst.a_oct_test_5 = a_oct_test_5; defparam inst.a_oct_pllbiasen = a_oct_pllbiasen; defparam inst.a_oct_usermode = a_oct_usermode; */ defparam inst.a_oct_cal_mode = "a_oct_cal_mode_none"; defparam inst.a_oct_user_oct = "a_oct_user_oct_off"; defparam inst.a_oct_nclrusr_inv = "a_oct_nclrusr_inv_off"; defparam inst.a_oct_pwrdn = "a_oct_pwrdn_on"; defparam inst.a_oct_intosc = "a_oct_intosc_none"; defparam inst.a_oct_test_0 = "a_oct_test_0_off"; defparam inst.a_oct_test_1 = "a_oct_test_1_off"; defparam inst.a_oct_test_4 = "a_oct_test_4_off"; defparam inst.a_oct_test_5 = "a_oct_test_5_off"; defparam inst.a_oct_pllbiasen = "a_oct_pllbiasen_dis"; defparam inst.a_oct_clkenusr_inv = "a_oct_clkenusr_inv_off"; defparam inst.a_oct_enserusr_inv = "a_oct_enserusr_inv_off"; defparam inst.a_oct_scanen_inv = "a_oct_scanen_inv_off"; defparam inst.a_oct_vrefl = "a_oct_vrefl_m"; defparam inst.a_oct_vrefh = "a_oct_vrefh_m"; defparam inst.a_oct_rsmult = "a_oct_rsmult_1"; defparam inst.a_oct_rsadjust = "a_oct_rsadjust_none"; defparam inst.a_oct_calclr = "a_oct_calclr_off"; defparam inst.a_oct_rshft_rup = "a_oct_rshft_rup_enable"; defparam inst.a_oct_rshft_rdn = "a_oct_rshft_rdn_enable"; defparam inst.a_oct_usermode = "false"; endmodule
module stratixv_asmiblock ( dclk, sce, oe, data0out, data1out, data2out, data3out, data0oe, data1oe, data2oe, data3oe, data0in, data1in, data2in, data3in); parameter lpm_type = "stratixv_asmiblock"; input dclk; input sce; input oe; input data0out; input data1out; input data2out; input data3out; input data0oe; input data1oe; input data2oe; input data3oe; output data0in; output data1in; output data2in; output data3in; stratixv_asmiblock_encrypted inst ( .dclk(dclk), .sce(sce), .oe(oe), .data0out(data0out), .data1out(data1out), .data2out(data2out), .data3out(data3out), .data0oe(data0oe), .data1oe(data1oe), .data2oe(data2oe), .data3oe(data3oe), .data0in(data0in), .data1in(data1in), .data2in(data2in), .data3in(data3in) ); defparam inst.lpm_type = lpm_type; endmodule
module stratixv_chipidblock ( clk, shiftnld, regout); parameter lpm_type = "stratixv_chipidblock"; input clk; input shiftnld; output regout; stratixv_chipidblock_encrypted inst ( .clk(clk), .shiftnld(shiftnld), .regout(regout) ); defparam inst.lpm_type = lpm_type; endmodule
module stratixv_controller ( nceout); parameter lpm_type = "stratixv_controller"; output nceout; stratixv_controller_encrypted inst ( .nceout(nceout) ); defparam inst.lpm_type = lpm_type; endmodule
module stratixv_crcblock ( clk, shiftnld, crcerror, regout); parameter oscillator_divider = 256; parameter lpm_type = "stratixv_crcblock"; input clk; input shiftnld; output crcerror; output regout; stratixv_crcblock_encrypted inst ( .clk(clk), .shiftnld(shiftnld), .crcerror(crcerror), .regout(regout) ); defparam inst.oscillator_divider = oscillator_divider; defparam inst.lpm_type = lpm_type; endmodule
module stratixv_jtag ( tms, tck, tdi, ntrst, tdoutap, tdouser, tdo, tmsutap, tckutap, tdiutap, shiftuser, clkdruser, updateuser, runidleuser, usr1user, ntrstcore); parameter lpm_type = "stratixv_jtag"; input tms; input tck; input tdi; input ntrst; input tdoutap; input tdouser; output tdo; output tmsutap; output tckutap; output tdiutap; output shiftuser; output clkdruser; output updateuser; output runidleuser; output usr1user; input ntrstcore; stratixv_jtag_encrypted inst ( .tms(tms), .tck(tck), .tdi(tdi), .ntrst(ntrst), .tdoutap(tdoutap), .tdouser(tdouser), .tdo(tdo), .tmsutap(tmsutap), .tckutap(tckutap), .tdiutap(tdiutap), .shiftuser(shiftuser), .clkdruser(clkdruser), .updateuser(updateuser), .runidleuser(runidleuser), .usr1user(usr1user) ); defparam inst.lpm_type = lpm_type; endmodule
module stratixv_prblock ( clk, corectl, prrequest, data, externalrequest, error, ready, done); parameter lpm_type = "stratixv_prblock"; input clk; input corectl; input prrequest; input [15:0] data; output externalrequest; output error; output ready; output done; stratixv_prblock_encrypted inst ( .clk(clk), .corectl(corectl), .prrequest(prrequest), .data(data), .externalrequest(externalrequest), .error(error), .ready(ready), .done(done) ); defparam inst.lpm_type = lpm_type; endmodule
module stratixv_rublock ( clk, shiftnld, captnupdt, regin, rsttimer, rconfig, regout); parameter sim_init_watchdog_value = 0; parameter sim_init_status = 0; parameter sim_init_config_is_application = "false"; parameter sim_init_watchdog_enabled = "false"; parameter lpm_type = "stratixv_rublock"; input clk; input shiftnld; input captnupdt; input regin; input rsttimer; input rconfig; output regout; stratixv_rublock_encrypted inst ( .clk(clk), .shiftnld(shiftnld), .captnupdt(captnupdt), .regin(regin), .rsttimer(rsttimer), .rconfig(rconfig), .regout(regout) ); defparam inst.sim_init_watchdog_value = sim_init_watchdog_value; defparam inst.sim_init_status = sim_init_status; defparam inst.sim_init_config_is_application = sim_init_config_is_application; defparam inst.sim_init_watchdog_enabled = sim_init_watchdog_enabled; defparam inst.lpm_type = lpm_type; endmodule
module stratixv_tsdblock ( clk, ce, clr, tsdcalo, tsdcaldone); parameter clock_divider_enable = "on"; parameter clock_divider_value = 40; parameter sim_tsdcalo = 0; parameter lpm_type = "stratixv_tsdblock"; input clk; input ce; input clr; output [7:0] tsdcalo; output tsdcaldone; stratixv_tsdblock_encrypted inst ( .clk(clk), .ce(ce), .clr(clr), .tsdcalo(tsdcalo), .tsdcaldone(tsdcaldone) ); defparam inst.clock_divider_enable = clock_divider_enable; defparam inst.clock_divider_value = clock_divider_value; defparam inst.sim_tsdcalo = sim_tsdcalo; defparam inst.lpm_type = lpm_type; endmodule
module stratixv_read_fifo ( datain, wclk, we, rclk, re, areset, plus2, dataout ); parameter use_half_rate_read = "false"; parameter sim_wclk_pre_delay = 0; input [1:0] datain; input wclk; input we; input rclk; input re; input areset; input plus2; output [3:0]dataout; stratixv_read_fifo_encrypted inst ( .datain(datain), .wclk(wclk), .we(we), .rclk(rclk), .re(re), .areset(areset), .plus2(plus2), .dataout(dataout)); defparam inst.use_half_rate_read = use_half_rate_read; defparam inst.sim_wclk_pre_delay = sim_wclk_pre_delay; endmodule
module stratixv_read_fifo_read_enable ( re, rclk, plus2, areset, reout, plus2out ); parameter use_stalled_read_enable = "false"; input re; input rclk; input plus2; input areset; output reout; output plus2out; stratixv_read_fifo_read_enable_encrypted inst ( .re(re), .rclk(rclk), .plus2(plus2), .areset(areset), .reout(reout), .plus2out(plus2out)); defparam inst.use_stalled_read_enable = use_stalled_read_enable; endmodule
module stratixv_phy_clkbuf ( inclk, outclk ); parameter level1_mux = "VALUE_FAST"; parameter level2_mux = "VALUE_FAST"; input [3:0] inclk; output [3:0] outclk; stratixv_phy_clkbuf_encrypted inst ( .inclk(inclk), .outclk(outclk)); defparam inst.level1_mux = level1_mux; defparam inst.level2_mux = level2_mux; endmodule
module sky130_fd_sc_hd__sdfstp ( Q , CLK , D , SCD , SCE , SET_B ); output Q ; input CLK ; input D ; input SCD ; input SCE ; input SET_B; // Voltage supply signals supply1 VPWR; supply0 VGND; supply1 VPB ; supply0 VNB ; endmodule
module top(); // Inputs are registered reg A1; reg A2; reg A3; reg B1; reg VPWR; reg VGND; reg VPB; reg VNB; // Outputs are wires wire X; initial begin // Initial state is x for all inputs. A1 = 1'bX; A2 = 1'bX; A3 = 1'bX; B1 = 1'bX; VGND = 1'bX; VNB = 1'bX; VPB = 1'bX; VPWR = 1'bX; #20 A1 = 1'b0; #40 A2 = 1'b0; #60 A3 = 1'b0; #80 B1 = 1'b0; #100 VGND = 1'b0; #120 VNB = 1'b0; #140 VPB = 1'b0; #160 VPWR = 1'b0; #180 A1 = 1'b1; #200 A2 = 1'b1; #220 A3 = 1'b1; #240 B1 = 1'b1; #260 VGND = 1'b1; #280 VNB = 1'b1; #300 VPB = 1'b1; #320 VPWR = 1'b1; #340 A1 = 1'b0; #360 A2 = 1'b0; #380 A3 = 1'b0; #400 B1 = 1'b0; #420 VGND = 1'b0; #440 VNB = 1'b0; #460 VPB = 1'b0; #480 VPWR = 1'b0; #500 VPWR = 1'b1; #520 VPB = 1'b1; #540 VNB = 1'b1; #560 VGND = 1'b1; #580 B1 = 1'b1; #600 A3 = 1'b1; #620 A2 = 1'b1; #640 A1 = 1'b1; #660 VPWR = 1'bx; #680 VPB = 1'bx; #700 VNB = 1'bx; #720 VGND = 1'bx; #740 B1 = 1'bx; #760 A3 = 1'bx; #780 A2 = 1'bx; #800 A1 = 1'bx; end sky130_fd_sc_lp__a31o dut (.A1(A1), .A2(A2), .A3(A3), .B1(B1), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X)); endmodule
module Raster_Laser_Projector_Video_In_video_decoder_0 ( // Inputs clk, reset, TD_CLK27, TD_DATA, TD_HS, TD_VS, clk27_reset, stream_out_ready, // Bidirectional // Outputs TD_RESET, overflow_flag, stream_out_data, stream_out_startofpacket, stream_out_endofpacket, stream_out_empty, stream_out_valid ); /***************************************************************************** * Parameter Declarations * *****************************************************************************/ parameter IW = 7; parameter OW = 15; parameter FW = 17; parameter PIXELS = 1280; /***************************************************************************** * Port Declarations * *****************************************************************************/ // Inputs input clk; input reset; input TD_CLK27; input [ 7: 0] TD_DATA; input TD_HS; input TD_VS; input clk27_reset; input stream_out_ready; // Bidirectional // Outputs output TD_RESET; output reg overflow_flag; output [OW: 0] stream_out_data; output stream_out_startofpacket; output stream_out_endofpacket; output stream_out_empty; output stream_out_valid; /***************************************************************************** * Constant Declarations * *****************************************************************************/ /***************************************************************************** * Internal Wires and Registers Declarations * *****************************************************************************/ // Internal Wires wire video_clk; wire video_clk_reset; wire [OW: 0] decoded_pixel; wire decoded_startofpacket; wire decoded_endofpacket; wire decoded_valid; wire [FW: 0] data_from_fifo; wire [ 6: 0] fifo_used_words; wire [ 6: 0] wrusedw; wire wrfull; wire rdempty; // Internal Registers reg reached_start_of_frame; // State Machine Registers // Integers /***************************************************************************** * Finite State Machine(s) * *****************************************************************************/ /***************************************************************************** * Sequential Logic * *****************************************************************************/ // Output Registers always @(posedge video_clk) begin if (video_clk_reset) overflow_flag <= 1'b0; else if (decoded_valid & reached_start_of_frame & wrfull) overflow_flag <= 1'b1; end // Internal Registers always @(posedge video_clk) begin if (video_clk_reset) reached_start_of_frame <= 1'b0; else if (decoded_valid & decoded_startofpacket) reached_start_of_frame <= 1'b1; end /***************************************************************************** * Combinational Logic * *****************************************************************************/ // Output Assignments assign TD_RESET = 1'b1; assign stream_out_data = data_from_fifo[OW: 0]; assign stream_out_startofpacket = data_from_fifo[(FW - 1)]; assign stream_out_endofpacket = data_from_fifo[FW]; assign stream_out_empty = 1'b0; assign stream_out_valid = ~rdempty; // Internal Assignments assign video_clk = TD_CLK27; assign video_clk_reset = clk27_reset; /***************************************************************************** * Internal Modules * *****************************************************************************/ // NTSC Video In Decoding altera_up_video_itu_656_decoder ITU_R_656_Decoder ( // Inputs .clk (video_clk), .reset (video_clk_reset), .TD_DATA (TD_DATA), .ready (decoded_valid & ~wrfull), // Bidirectionals // Outputs .data (decoded_pixel), .startofpacket (decoded_startofpacket), .endofpacket (decoded_endofpacket), .valid (decoded_valid) ); altera_up_video_dual_clock_fifo Video_In_Dual_Clock_FIFO ( // Inputs .wrclk (video_clk), .wrreq (decoded_valid & reached_start_of_frame & ~wrfull), // .data ({1'b0, decoded_startofpacket, decoded_pixel}), .data ({decoded_endofpacket, decoded_startofpacket, decoded_pixel}), .rdclk (clk), .rdreq (stream_out_valid & stream_out_ready), // Bidirectionals // Outputs .wrusedw (wrusedw), .wrfull (wrfull), .q (data_from_fifo), .rdusedw (fifo_used_words), .rdempty (rdempty) ); defparam Video_In_Dual_Clock_FIFO.DW = (FW + 1); endmodule
module sky130_fd_sc_lp__inputiso0n_lp ( X , A , SLEEP_B, VPWR , VGND , VPB , VNB ); output X ; input A ; input SLEEP_B; input VPWR ; input VGND ; input VPB ; input VNB ; sky130_fd_sc_lp__inputiso0n base ( .X(X), .A(A), .SLEEP_B(SLEEP_B), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB) ); endmodule
module sky130_fd_sc_lp__inputiso0n_lp ( X , A , SLEEP_B ); output X ; input A ; input SLEEP_B; // Voltage supply signals supply1 VPWR; supply0 VGND; supply1 VPB ; supply0 VNB ; sky130_fd_sc_lp__inputiso0n base ( .X(X), .A(A), .SLEEP_B(SLEEP_B) ); endmodule
module tb_decoder4to16(); /** * Declare signal types for testbench to drive and monitor * signals during the simulation of the arbiter * * The reg data type holds a value until a new value is driven * onto it in an "initial" or "always" block. It can only be * assigned a value in an "always" or "initial" block, and is * used to apply stimulus to the inputs of the DUT. * * The wire type is a passive data type that holds a value driven * onto it by a port, assign statement or reg type. Wires cannot be * assigned values inside "always" and "initial" blocks. They can * be used to hold the values of the DUT's outputs */ // Declare "wire" signals: outputs from the DUT wire [15:1] dout; // Declare "reg" signals: inputs to the DUT reg [3:0] din; /** * Instantiate an instance of arbiter_LRU4 so that * inputs can be passed to the Device Under Test (DUT) * Given instance name is "arb" */ decoder4to16 dec4to16 ( // instance_name(signal name), // Signal name can be the same as the instance name din,dout); /** * Initial block start executing sequentially @ t=0 * If and when a delay is encountered, the execution of this block * pauses or waits until the delay time has passed, before resuming * execution * * Each intial or always block executes concurrently; that is, * multiple "always" or "initial" blocks will execute simultaneously * * E.g. * always * begin * #10 clk_50 = ~clk_50; // Invert clock signal every 10 ns * // Clock signal has a period of 20 ns or 50 MHz * end */ initial begin // "$time" indicates the current time in the simulation $display(" << Starting the simulation >>"); din = 15'd0; #1; din = 15'd1; // @ t=0, #1; din = 15'd2; #1; din = 15'd3; #1; din = 15'd4; #1; din = 15'd5; #1; din = 15'd6; #1; din = 15'd7; #1; din = 15'd8; #1; din = 15'd9; #1; din = 15'd10; #1; din = 15'd11; #1; din = 15'd12; #1; din = 15'd13; #1; din = 15'd14; #1; din = 15'd15; #20; $display(" << Finishing the simulation >>"); $finish; end endmodule
module top(); // Inputs are registered reg A1; reg A2; reg B1; reg VPWR; reg VGND; // Outputs are wires wire X; initial begin // Initial state is x for all inputs. A1 = 1'bX; A2 = 1'bX; B1 = 1'bX; VGND = 1'bX; VPWR = 1'bX; #20 A1 = 1'b0; #40 A2 = 1'b0; #60 B1 = 1'b0; #80 VGND = 1'b0; #100 VPWR = 1'b0; #120 A1 = 1'b1; #140 A2 = 1'b1; #160 B1 = 1'b1; #180 VGND = 1'b1; #200 VPWR = 1'b1; #220 A1 = 1'b0; #240 A2 = 1'b0; #260 B1 = 1'b0; #280 VGND = 1'b0; #300 VPWR = 1'b0; #320 VPWR = 1'b1; #340 VGND = 1'b1; #360 B1 = 1'b1; #380 A2 = 1'b1; #400 A1 = 1'b1; #420 VPWR = 1'bx; #440 VGND = 1'bx; #460 B1 = 1'bx; #480 A2 = 1'bx; #500 A1 = 1'bx; end sky130_fd_sc_hs__a21o dut (.A1(A1), .A2(A2), .B1(B1), .VPWR(VPWR), .VGND(VGND), .X(X)); endmodule
module Search( input clock, input reset, input [511:0] data, input [511:0] key, output reg match ); reg [511:0] data1; reg [510:0] data2; reg [509:0] data3; reg [508:0] data4; wire [63:0] key1, key2, key3, key4; reg match1, match2, match3, match4; reg max_counter = 113; reg [6:0] counter; Comparator c1 ( .clock(clock), .data(data1), .key(key1), .match(match1) ); Comparator c2 ( .clock(clock), .data(data2), .key(key2), .match(match2) ); Comparator c3 ( .clock(clock), .data(data3), .key(key3), .match(match3) ); Comparator c4 ( .clock(clock), .data(data4), .key(key4), .match(match4) ); always @(posedge clock, posedge reset) begin if (reset) begin counter <= 0; data1 <= data; data2 <= data[511:1]; data3 <= data[511:2]; data4 <= data[511:3]; end else begin if (counter == max_counter) begin counter <= 0; data1 <= data; data2 <= data[511:1]; data3 <= data[511:2]; data4 <= data[511:3]; end else begin counter <= counter + 1; data1 <= data1 << 1; data2 <= data2 << 1; data3 <= data3 << 1; data4 <= data4 << 1; end if (match1 || match2 || match3 || match4) match <= 1; else match <= 0; end end endmodule
module sky130_fd_sc_hs__and2b ( //# {{data|Data Signals}} input A_N , input B , output X , //# {{power|Power}} input VPWR, input VGND ); endmodule
module reg_file( input clk, input regWrite, //input wire regInit, input [4:0] readReg1, input [4:0] readReg2, input [4:0] writeReg, input [31:0] writeData, output reg [31:0] readData1, output reg [31:0] readData2 ); reg [31:0] regFile [31:0]; integer i; initial begin for (i=0; i<32; i=i+1) begin regFile[i] <=0; end end always@(readReg1 or readReg2 or regFile) begin readData1 <= regFile[readReg1]; readData2 <= regFile[readReg2]; end // Register only updates when regWrite control signal enabled // When regInit true, initialize all registers to 0 (avoids using for-loop) always@(posedge clk) begin if(regWrite) regFile[writeReg] <= writeData; /*if (regInit) begin regFile[31] <= 32'h00000000; regFile[30] <= 32'h00000000; regFile[29] <= 32'h00000000; regFile[28] <= 32'h00000000; regFile[27] <= 32'h00000000; regFile[26] <= 32'h00000000; regFile[25] <= 32'h00000000; regFile[24] <= 32'h00000000; regFile[23] <= 32'h00000000; regFile[22] <= 32'h00000000; regFile[21] <= 32'h00000000; regFile[20] <= 32'h00000000; regFile[19] <= 32'h00000000; regFile[18] <= 32'h00000000; regFile[17] <= 32'h00000000; regFile[16] <= 32'h00000000; regFile[15] <= 32'h00000000; regFile[14] <= 32'h00000000; regFile[13] <= 32'h00000000; regFile[12] <= 32'h00000000; regFile[11] <= 32'h00000000; regFile[10] <= 32'h00000000; regFile[9] <= 32'h00000000; regFile[8] <= 32'h00000000; regFile[7] <= 32'h00000000; regFile[6] <= 32'h00000000; regFile[5] <= 32'h00000000; regFile[4] <= 32'h00000000; regFile[3] <= 32'h00000000; regFile[2] <= 32'h00000000; regFile[1] <= 32'h00000000; regFile[0] <= 32'h00000000; end */ end endmodule
module ram0( // Read port input rdclk, input [9:0] rdaddr, output reg [35:0] do); (* ram_style = "block" *) reg [35:0] ram[0:1023]; genvar i; generate for (i=0; i<1024; i=i+1) begin initial begin ram[i] <= i | (i << 16); end end endgenerate always @ (posedge rdclk) begin do <= ram[rdaddr]; end endmodule
module top ( input wire clk, input wire rx, output wire tx, input wire [15:0] sw, output wire [15:0] led ); reg nrst = 0; wire tx_baud_edge; wire rx_baud_edge; // Data in. wire [7:0] rx_data_wire; wire rx_data_ready_wire; // Data out. wire tx_data_ready; wire tx_data_accepted; wire [7:0] tx_data; assign led[14:0] = sw[14:0]; assign led[15] = rx_data_ready_wire ^ sw[15]; UART #( .COUNTER(25), .OVERSAMPLE(8) ) uart ( .clk(clk), .rst(!nrst), .rx(rx), .tx(tx), .tx_data_ready(tx_data_ready), .tx_data(tx_data), .tx_data_accepted(tx_data_accepted), .rx_data(rx_data_wire), .rx_data_ready(rx_data_ready_wire) ); wire [9:0] read_address; wire [35:0] read_data; wire [9:0] rom_read_address; reg [35:0] rom_read_data; always @(posedge clk) rom_read_data <= {2{6'd0, rom_read_address}}; wire loop_complete; wire error_detected; wire [7:0] error_state; wire [9:0] error_address; wire [35:0] expected_data; wire [35:0] actual_data; ROM_TEST #( .ADDR_WIDTH(10), .DATA_WIDTH(36), .ADDRESS_STEP(1), .MAX_ADDRESS(1023) ) dram_test ( .rst(!nrst), .clk(clk), // Memory connection .read_data(read_data), .read_address(read_address), // INIT ROM connection .rom_read_data(rom_read_data), .rom_read_address(rom_read_address), // Reporting .loop_complete(loop_complete), .error(error_detected), .error_state(error_state), .error_address(error_address), .expected_data(expected_data), .actual_data(actual_data) ); ram0 #( ) bram ( // Read port .rdclk(clk), .rdaddr(read_address), .do(read_data) ); ERROR_OUTPUT_LOGIC #( .DATA_WIDTH(32), .ADDR_WIDTH(10) ) output_logic ( .clk(clk), .rst(!nrst), .loop_complete(loop_complete), .error_detected(error_detected), .error_state(error_state), .error_address(error_address), .expected_data(expected_data), .actual_data(actual_data), .tx_data(tx_data), .tx_data_ready(tx_data_ready), .tx_data_accepted(tx_data_accepted) ); always @(posedge clk) begin nrst <= 1; end endmodule
module AddrDecoder(reqType, ofs, base, count, lbType, addr, invalid); input [5:0] reqType; input [15:0] ofs; input [15:0] base; input [15:0] count; input [5:0] lbType; output [15:0] addr; output invalid; // assign addr = base + ofs; assign invalid = !( isValidLabelType(reqType) && reqType == lbType && ofs < count ); function isValidLabelType(input [5:0] type); case(reqType) //`LBTYPE_UNDEFINED:; `LBTYPE_VPTR: isValidLabelType = 1'd1; `LBTYPE_SINT8: isValidLabelType = 1'd1; `LBTYPE_UINT8: isValidLabelType = 1'd1; `LBTYPE_SINT16: isValidLabelType = 1'd1; `LBTYPE_UINT16: isValidLabelType = 1'd1; `LBTYPE_SINT32: isValidLabelType = 1'd1; `LBTYPE_UINT32: isValidLabelType = 1'd1; `LBTYPE_SINT4: isValidLabelType = 1'd1; `LBTYPE_UINT4: isValidLabelType = 1'd1; `LBTYPE_SINT2: isValidLabelType = 1'd1; `LBTYPE_UINT2: isValidLabelType = 1'd1; `LBTYPE_SINT1: isValidLabelType = 1'd1; `LBTYPE_UINT1: isValidLabelType = 1'd1; `LBTYPE_CODE: isValidLabelType = 1'd1; default: isValidLabelType = 1'd0; endcase endfunction endmodule
module testbench_addrdec(); reg clk; // reg [5:0] reqType; reg [15:0] ofs; reg [15:0] base; reg [15:0] count; reg [5:0] lbType; wire [15:0] addr; wire invalid; AddrDecoder addrdec(reqType, ofs, base, count, lbType, addr, invalid); initial begin $dumpfile("addrdec.vcd"); $dumpvars(0, testbench_addrdec); // all invalid reqType = `LBTYPE_UNDEFINED; ofs = 4; base = 16'hffff; count = 0; lbType = `LBTYPE_UNDEFINED; // #1; $display ("addr: %X", addr); $display ("invalid: %X", invalid); if(invalid == 1) $display("PASS"); else begin $display("FAILED"); $finish; end // valid reqType = `LBTYPE_CODE; ofs = 4; base = 16'hff00; count = 16'h00ff; lbType = `LBTYPE_CODE; // #1; $display ("addr: %X", addr); $display ("invalid: %X", invalid); if(invalid == 0 && addr == 16'hff04) $display("PASS"); else begin $display("FAILED"); $finish; end // type not matched reqType = `LBTYPE_VPTR; ofs = 4; base = 16'hff00; count = 16'h00ff; lbType = `LBTYPE_CODE; // #1; $display ("addr: %X", addr); $display ("invalid: %X", invalid); if(invalid == 1) $display("PASS"); else begin $display("FAILED"); $finish; end // out of limit reqType = `LBTYPE_CODE; ofs = 4; base = 16'hff00; count = 16'h004; lbType = `LBTYPE_CODE; // #1; $display ("addr: %X", addr); $display ("invalid: %X", invalid); if(invalid == 1) $display("PASS"); else begin $display("FAILED"); $finish; end // last element in bound reqType = `LBTYPE_CODE; ofs = 3; base = 16'hff00; count = 16'h004; lbType = `LBTYPE_CODE; // #1; $display ("addr: %X", addr); $display ("invalid: %X", invalid); if(invalid == 0 && addr == 16'hff03) $display("PASS"); else begin $display("FAILED"); $finish; end // $display ("Simulation end"); $finish; end always begin // クロックを生成する。 // #1; は、1クロック待機する。 clk <= 0; #1; clk <= 1; #1; end always @ (posedge clk) begin end endmodule
module jt12_mod6 ( input [2:0] in, // only 0 to 5 are valid entries input [2:0] sum, output reg [2:0] out // output between 0 to 5 ); reg [3:0] aux; always @(*) begin aux <= in+sum; case( aux ) 4'd6: out <= 3'd0; 4'd7: out <= 3'd1; 4'd8: out <= 3'd2; 4'd9: out <= 3'd3; 4'ha: out <= 3'd4; 4'hb: out <= 3'd5; 4'hc: out <= 3'd0; 4'he: out <= 3'd1; 4'hf: out <= 3'd2; default: out <= aux; endcase end endmodule
module {{module_name}} ( //======全局========= input wire shiz ,input wire fuw_d //======中间结点============ ,input wire [15:0] zjjd__yjd__shuj ,output reg [15:0] yjd__zjjd__shuj {% set mod_to_mod = module_name.split("_")[0] + "__" + module_name -%} {% set mod_to_mod_reverse = module_name + "__" + module_name.split("_")[0] -%} //======所在单元========== {% block io_def -%} {% for reg, parameters in data.items() -%} {% for bits, items in parameters.fields.items() -%} {% set definition = "_"+ items.definition if items.definition -%} //-----{{reg}}{{definition}}----- {% if parameters["ST/MT"] == "MT" -%} {% for i in range(2) -%} {% if 'hrw' not in items or items.hrw == 'NA' or items.hrw == 'rw' -%} ,input wire {{mod_to_mod}}__{{reg}}{{definition}}{{i}}_xsn //{{reg}}{{definition}}线程{{i}},写使能 ,input wire {{items.interval}} {{mod_to_mod}}__{{reg}}{{definition}}{{i}}_sj //{{reg}}{{definition}}线程{{i}},所在单元要写的值 ,output wire {{items.interval}} {{mod_to_mod_reverse}}__{{reg}}{{definition}}{{i}}_sj //{{reg}}{{definition}}线程{{i}},CR当前的值 {% elif items.hrw == "r" -%} ,output wire {{items.interval}} {{mod_to_mod_reverse}}__{{reg}}{{definition}}{{i}}_sj //{{reg}}{{definition}}线程{{i}},CR当前的值 {% elif items.hrw == "w" -%} ,input wire {{mod_to_mod}}__{{reg}}{{definition}}{{i}}_xsn //{{reg}}{{definition}}线程{{i}},写使能 ,input wire {{items.interval}} {{mod_to_mod}}__{{reg}}{{definition}}{{i}}_sj //{{reg}}{{definition}}线程{{i}},所在单元要写的值 {% endif -%} {% endfor %}{% else -%} {% if 'hrw' not in items or items.hrw == 'NA' or items.hrw == 'rw' -%} ,input wire {{mod_to_mod}}__{{reg}}{{definition}}_xsn //{{reg}}{{definition}},写使能 ,input wire {{items.interval}} {{mod_to_mod}}__{{reg}}{{definition}}_sj //{{reg}}{{definition}},所在单元要写的值 ,output wire {{items.interval}} {{mod_to_mod_reverse}}__{{reg}}{{definition}}_sj //{{reg}}{{definition}},CR当前的值 {% elif items.hrw == "r" -%} ,output wire {{items.interval}} {{mod_to_mod_reverse}}__{{reg}}{{definition}}_sj //{{reg}}{{definition}},CR当前的值 {% elif items.hrw == "w" -%} ,input wire {{mod_to_mod}}__{{reg}}{{definition}}_xsn //{{reg}}{{definition}},写使能 ,input wire {{items.interval}} {{mod_to_mod}}__{{reg}}{{definition}}_sj //{{reg}}{{definition}},所在单元要写的值 {% endif -%} {% endif -%} {% endfor -%} {% endfor -%} {% endblock io_def -%} ); {% set prefix = ["yjdkz", "kzjcq"] %} reg [15:0] zjjd_xie_shuj; wire [15:0] zjjd_du_sj; {% block wire_def %} {% for reg, parameters in data.items() -%} {% for bits, items in parameters.fields.items() -%} {% set definition = "_"+ items.definition if items.definition -%} wire [15:0] {{reg}}{{definition}}_du_shuj; {% if parameters["ST/MT"] == "MT" -%} {% for i in range(2) -%} wire {{prefix[0]}}__{{prefix[1]}}__{{reg}}{{definition}}{{i}}_xsn; wire {{items.interval}} {{prefix[0]}}__{{prefix[1]}}__{{reg}}{{definition}}{{i}}_sj; wire {{items.interval}} {{prefix[1]}}__{{prefix[0]}}__{{reg}}{{definition}}{{i}}_sj; {% endfor %} {% else -%} wire {{prefix[0]}}__{{prefix[1]}}__{{reg}}{{definition}}_xsn; wire {{items.interval}} {{prefix[0]}}__{{prefix[1]}}__{{reg}}{{definition}}_sj; wire {{items.interval}} {{prefix[1]}}__{{prefix[0]}}__{{reg}}{{definition}}_sj; {% endif -%} {% endfor -%} {% endfor -%} {% endblock wire_def -%} always@(posedge shiz or negedge fuw_d) begin if(~fuw_d) zjjd_xie_shuj <= 16'b0; else zjjd_xie_shuj <= zjjd__yjd__shuj; end {% block instances -%} {% for reg, parameters in data.items() -%} {% for bits, items in parameters.fields.items() -%} {% set definition = "_"+ items.definition if items.definition -%} {% set reg_def = reg + definition if definition else reg -%} {% set ds = "s" if parameters["ST/MT"] == "MT" else "d" -%} {% set bits = parameters["32bit/64bit"].replace("bit", "") if items.interval_type == "kbwk" else "" -%} //========={{reg_def}}================= {{prefix[0]}}_{{ds}}{{bits}}{{items.interval_type}}#( {% if parameters["32bit/64bit"] == "64bit" -%} .G_GDZ ({{parameters.hglobal_address}}), .G_DDZ ({{parameters.global_address}}), .L_GDZ ({{parameters.hlocal_address}}), .L_DDZ ({{parameters.local_address}}) {%- else -%} .G_DIZ ({{parameters.global_address}}), .L_DIZ ({{parameters.local_address}}) {%- endif -%} {% if items.interval_type == "kbwk"-%} , .KAISW({{items.st_ed[1]}}), .JIESW({{items.st_ed[0]}}), .SZ({{items.st_ed[0]-items.st_ed[1] +1 }}) {% endif -%} )u_{{prefix[0]}}_{{reg_def}}( .shiz (shiz ), .fuw_d (fuw_d ), .zjjd__{{prefix[0]}}__shuj (zjjd_xie_shuj ), //根结点来的数据 .{{prefix[0]}}__zjjd__shuj ({{reg_def}}_du_shuj ), //输出到根结点的数据 {% if ds == "s" -%} {% for i in range(2) -%} .{{prefix[0]}}__{{prefix[1]}}{{i}}__xsn ({{prefix[0]}}__{{prefix[1]}}__{{reg}}{{definition}}{{i}}_xsn ), //写使能 .{{prefix[0]}}__{{prefix[1]}}{{i}}__sj ({{prefix[0]}}__{{prefix[1]}}__{{reg}}{{definition}}{{i}}_sj ), //CRU要写的值 .{{prefix[1]}}{{i}}__{{prefix[0]}}__sj ({{prefix[1]}}__{{prefix[0]}}__{{reg}}{{definition}}{{i}}_sj ){%- if i==0 -%},{%- endif -%} //CR当前的值 {% endfor %}{% else -%} .{{prefix[0]}}__{{prefix[1]}}__xsn ({{prefix[0]}}__{{prefix[1]}}__{{reg_def}}_xsn ), //写使能 .{{prefix[0]}}__{{prefix[1]}}__sj ({{prefix[0]}}__{{prefix[1]}}__{{reg_def}}_sj ), //CRU要写的值 .{{prefix[1]}}__{{prefix[0]}}__sj ({{prefix[1]}}__{{prefix[0]}}__{{reg_def}}_sj ) //CR当前的值 {% endif -%} ); {% if ds == "s" -%} {% for i in range(2) -%} {{prefix[1]}}_{{items.interval_type}} #( {% if items.interval_type == "kbwk" -%} .SZ({{items.st_ed[0]-items.st_ed[1] +1 }}), {% endif -%} .MRZ ({{items.reset_value}}) )u_{{reg}}{{definition}}{{i}}( .shiz (shiz ), .fuw_d (fuw_d ), .{{prefix[0]}}__{{prefix[1]}}__xsn ({{prefix[0]}}__{{prefix[1]}}__{{reg}}{{definition}}{{i}}_xsn ), //写使能// .{{prefix[0]}}__{{prefix[1]}}__sj ({{prefix[0]}}__{{prefix[1]}}__{{reg}}{{definition}}{{i}}_sj ), //CRU要写的值// .{{prefix[1]}}__{{prefix[0]}}__sj ({{prefix[1]}}__{{prefix[0]}}__{{reg}}{{definition}}{{i}}_sj ), //CR当前的值// {% if 'hrw' not in items or items.hrw == 'NA' or items.hrw == 'rw' -%} .szdy__{{prefix[1]}}__xsn ({{mod_to_mod}}__{{reg}}{{definition}}{{i}}_xsn ), //写使能// .szdy__{{prefix[1]}}__sj ({{mod_to_mod}}__{{reg}}{{definition}}{{i}}_sj ), //所在单元要写的值// .{{prefix[1]}}__szdy__sj ({{mod_to_mod_reverse}}__{{reg}}{{definition}}{{i}}_sj ) //CR当前的值// {% elif items.hrw == "r" -%} .szdy__{{prefix[1]}}__xsn (0), //写使能// .szdy__{{prefix[1]}}__sj (0), //所在单元要写的值// .{{prefix[1]}}__szdy__sj ({{mod_to_mod_reverse}}__{{reg}}{{definition}}{{i}}_sj ) //CR当前的值// {% elif items.hrw == "w" -%} .szdy__{{prefix[1]}}__xsn ({{mod_to_mod}}__{{reg}}{{definition}}{{i}}_xsn ), //写使能// .szdy__{{prefix[1]}}__sj ({{mod_to_mod}}__{{reg}}{{definition}}{{i}}_sj ), //所在单元要写的值// .{{prefix[1]}}__szdy__sj () //CR当前的值// {% endif -%} ); {% endfor %}{% else -%} {{prefix[1]}}_{{items.interval_type}} #( {% if items.interval_type == "kbwk" -%} .SZ({{items.st_ed[0]-items.st_ed[1] +1 }}), {% endif -%} .MRZ ({{items.reset_value}}) )u_{{reg_def}}( .shiz (shiz ), .fuw_d (fuw_d ), .{{prefix[0]}}__{{prefix[1]}}__xsn ({{prefix[0]}}__{{prefix[1]}}__{{reg_def}}_xsn ), //写使能// .{{prefix[0]}}__{{prefix[1]}}__sj ({{prefix[0]}}__{{prefix[1]}}__{{reg_def}}_sj ), //CRU要写的值// .{{prefix[1]}}__{{prefix[0]}}__sj ({{prefix[1]}}__{{prefix[0]}}__{{reg_def}}_sj ), //CR当前的值// {% if 'hrw' not in items or items.hrw == 'NA' or items.hrw == 'rw' -%} .szdy__{{prefix[1]}}__xsn ({{mod_to_mod}}__{{reg_def}}_xsn ), //写使能// .szdy__{{prefix[1]}}__sj ({{mod_to_mod}}__{{reg_def}}_sj ), //所在单元要写的值// .{{prefix[1]}}__szdy__sj ({{mod_to_mod_reverse}}__{{reg_def}}_sj ) //CR当前的值// {% elif items.hrw == "r" -%} .szdy__{{prefix[1]}}__xsn (0), //写使能// .szdy__{{prefix[1]}}__sj (0), //所在单元要写的值// .{{prefix[1]}}__szdy__sj ({{mod_to_mod_reverse}}__{{reg_def}}_sj ) //CR当前的值// {% elif items.hrw == "w" -%} .szdy__{{prefix[1]}}__xsn ({{mod_to_mod}}__{{reg_def}}_xsn ), //写使能// .szdy__{{prefix[1]}}__sj ({{mod_to_mod}}__{{reg_def}}_sj ), //所在单元要写的值// .{{prefix[1]}}__szdy__sj () //CR当前的值// {% endif -%} ); {% endif -%} {% endfor -%} {% endfor -%} {% endblock instances -%} {% block assign %} {%- for reg, parameters in data.items() %} {%- if loop.first %} {%- for bits, items in parameters.fields.items() %} {%- set definition = "_"+ items.definition if items.definition %} {%- set reg_def = reg + definition if definition else reg %} {%- if loop.first %} assign zjjd_du_sj = {{reg_def}}_du_shuj {%- else %} |{{reg_def}}_du_shuj {%- endif %} {%- endfor %} {%- else %} {%- for bits, items in parameters.fields.items() %} {%- set definition = "_"+ items.definition if items.definition %} {%- set reg_def = reg + definition if definition else reg %} |{{reg_def}}_du_shuj {%- endfor %} {%- endif %} {%- endfor %} ; {% endblock %} always@(posedge shiz or negedge fuw_d) begin if(~fuw_d) yjd__zjjd__shuj <= 16'b0; else yjd__zjjd__shuj <= zjjd_du_sj; end endmodule
module top_spw_ultra_light( input pclk, input ppllclk, input resetn, input top_sin, input top_din, input top_auto_start, input top_link_start, input top_link_disable, input top_tx_write, input [8:0] top_tx_data, input top_tx_tick, input [7:0] top_tx_time, input credit_error_rx, input top_send_fct_now, output [8:0] datarx_flag, output buffer_write, output [7:0] time_out, output tick_out, output top_dout, output top_sout, output top_tx_ready, output top_tx_ready_tick, output [5:0] top_fsm ); wire resetn_rx; wire error_rx; wire got_bit_rx; wire got_null_rx; wire got_nchar_rx; wire got_time_code_rx; wire got_fct_rx; wire enable_tx; wire send_null_tx; wire send_fct_tx; wire got_fct_flag_fsm; FSM_SPW FSM( .pclk(pclk), .resetn(resetn), .auto_start(top_auto_start), .link_start(top_link_start), .link_disable(top_link_disable), .rx_error(error_rx), .rx_credit_error(credit_error_rx), .rx_got_bit(got_bit_rx), .rx_got_null(got_null_rx), .rx_got_nchar(got_nchar_rx), .rx_got_time_code(got_time_code_rx), .rx_got_fct(got_fct_flag_fsm), .rx_resetn(resetn_rx), .enable_tx(enable_tx), .send_null_tx(send_null_tx), .send_fct_tx(send_fct_tx), .fsm_state(top_fsm) ); RX_SPW RX( .rx_din(top_din), .rx_sin(top_sin), .rx_resetn(resetn_rx), .rx_error(error_rx), .rx_got_bit(got_bit_rx), .rx_got_null(got_null_rx), .rx_got_nchar(got_nchar_rx), .rx_got_time_code(got_time_code_rx), .rx_got_fct(got_fct_rx), .rx_got_fct_fsm(got_fct_flag_fsm), .rx_data_flag(datarx_flag), .rx_buffer_write(buffer_write), .rx_time_out(time_out), .rx_tick_out(tick_out) ); TX_SPW TX( .pclk_tx(ppllclk), .data_tx_i(top_tx_data), .txwrite_tx(top_tx_write), .timecode_tx_i(top_tx_time), .tickin_tx(top_tx_tick), .enable_tx(enable_tx), .send_null_tx(send_null_tx), .send_fct_tx(send_fct_tx), .gotfct_tx(got_fct_rx), .send_fct_now(top_send_fct_now), .tx_dout_e(top_dout), .tx_sout_e(top_sout), .ready_tx_data(top_tx_ready), .ready_tx_timecode(top_tx_ready_tick) ); endmodule
module will // determine the memory option). scsdpram #( .C_WIDTH(C_WIDTH), .C_DEPTH(C_POW2_DEPTH) /*AUTOINSTPARAM*/) mem ( .WR1_EN (wWrEn), .WR1_ADDR (rWrPtr[C_DEPTH_WIDTH-1:0]), .WR1_DATA (WR_DATA), .RD1_EN (wRdEn), .RD1_ADDR (rRdPtr[C_DEPTH_WIDTH-1:0]), .RD1_DATA (RD_DATA), /*AUTOINST*/ // Inputs .CLK (CLK)); shiftreg #( // Parameters .C_DEPTH (C_DELAY), .C_WIDTH (1'b1) /*AUTOINSTPARAM*/) shiftreg_wr_delay_inst ( // Outputs .RD_DATA (wDelayTaps), // Inputs .RST_IN (RST), .WR_DATA (wWrEn), /*AUTOINST*/ // Inputs .CLK (CLK)); endmodule
module dCalcPointsDistance3 ( input CLK, input [31:0] a1, input [31:0] a2, input [31:0] a3, input [31:0] b1, input [31:0] b2, input [31:0] b3, input RST, output [31:0] res, output reg out_rdy ); wire CLK2; wire [31:0] b1_neg; wire [31:0] b2_neg; wire [31:0] b3_neg; wire [31:0] out_add1; wire output_z_ack_wire; wire done_add1; wire input_a_ack_wire; wire input_b_ack_wire; wire [31:0] out_add2; wire output_z_ack_wire1; wire done_add2; wire input_a_ack_wire1; wire input_b_ack_wire1; wire [31:0] out_add3; wire output_z_ack_wire2; wire done_add3; wire input_a_ack_wire2; wire input_b_ack_wire2; wire out_rdy_calclen; reg resetlen = 1'b1; assign b1_neg = {~b1[31],b1[30:0]}; assign b2_neg = {~b2[31],b2[30:0]}; assign b3_neg = {~b3[31],b3[30:0]}; assign CLK2 = (done_add1 & done_add2 & done_add3) ? 1:0; //jtag_debug jtag8(.in_debug(debugtest1)); // //jtag_debug debug6(.in_debug(out_add2)); // //jtag_debug debug9(.in_debug(out_add3)); add_comb add1 ( .clk_en ( 1'b1 ), .clock ( CLK ), .dataa ( a1 ), .datab ( b1_neg ), .result ( out_add1 ), .reset(RST), .done(done_add1) ); add_comb add2 ( .clk_en ( 1'b1 ), .clock ( CLK ), .dataa ( a2 ), .datab ( b2_neg ), .result ( out_add2 ), .reset(RST), .done(done_add2) ); add_comb add3 ( .clk_en ( 1'b1 ), .clock ( CLK ), .dataa ( a3 ), .datab ( b3_neg ), .result ( out_add3 ), .reset(RST), .done(done_add3) ); dCalcVectorLength3 calcLen ( .CLK(CLK), .a1(out_add1), .a2(out_add2), .a3(out_add3), .b1(out_add1), .b2(out_add2), .b3(out_add3), .RST(resetlen), .res(res), .out_rdy(out_rdy_calclen) ); reg [31:0] debugtest1; reg debugtest2; always @(posedge CLK2 or negedge RST or posedge out_rdy_calclen) begin if(RST == 1'b0) begin resetlen <= 1'b0; out_rdy <= 1'b0; end else begin if(CLK2) begin resetlen <= 1'b1; end if(out_rdy_calclen) begin out_rdy <= 1'b1; debugtest1 <= res; end end end endmodule
module sky130_fd_sc_hvl__udp_dlatch$P ( //# {{data|Data Signals}} input D , output Q , //# {{clocks|Clocking}} input GATE ); endmodule
module sky130_fd_sc_hs__fill_diode_8 ( VPWR, VGND, VPB , VNB ); input VPWR; input VGND; input VPB ; input VNB ; sky130_fd_sc_hs__fill_diode base ( .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB) ); endmodule
module sky130_fd_sc_hs__fill_diode_8 (); // Voltage supply signals supply1 VPWR; supply0 VGND; supply1 VPB ; supply0 VNB ; sky130_fd_sc_hs__fill_diode base (); endmodule
module sky130_fd_sc_ms__sdfstp ( Q , CLK , D , SCD , SCE , SET_B, VPWR , VGND , VPB , VNB ); output Q ; input CLK ; input D ; input SCD ; input SCE ; input SET_B; input VPWR ; input VGND ; input VPB ; input VNB ; endmodule
module sky130_fd_sc_ls__a2bb2o_1 ( X , A1_N, A2_N, B1 , B2 , VPWR, VGND, VPB , VNB ); output X ; input A1_N; input A2_N; input B1 ; input B2 ; input VPWR; input VGND; input VPB ; input VNB ; sky130_fd_sc_ls__a2bb2o base ( .X(X), .A1_N(A1_N), .A2_N(A2_N), .B1(B1), .B2(B2), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB) ); endmodule
module sky130_fd_sc_ls__a2bb2o_1 ( X , A1_N, A2_N, B1 , B2 ); output X ; input A1_N; input A2_N; input B1 ; input B2 ; // Voltage supply signals supply1 VPWR; supply0 VGND; supply1 VPB ; supply0 VNB ; sky130_fd_sc_ls__a2bb2o base ( .X(X), .A1_N(A1_N), .A2_N(A2_N), .B1(B1), .B2(B2) ); endmodule
module system_ov7670_vga_0_0 (clk_x2, active, data, rgb); input clk_x2; (* x_interface_info = "xilinx.com:signal:clock:1.0 clk CLK" *) input active; input [7:0]data; output [15:0]rgb; wire active; wire clk_x2; wire [7:0]data; wire [15:0]rgb; system_ov7670_vga_0_0_ov7670_vga U0 (.active(active), .clk_x2(clk_x2), .data(data), .rgb(rgb)); endmodule
module system_ov7670_vga_0_0_ov7670_vga (rgb, active, clk_x2, data); output [15:0]rgb; input active; input clk_x2; input [7:0]data; wire active; wire clk_x2; wire cycle; wire [7:0]data; wire \data_pair[15]_i_1_n_0 ; wire \data_pair[7]_i_1_n_0 ; wire \data_pair_reg_n_0_[0] ; wire \data_pair_reg_n_0_[10] ; wire \data_pair_reg_n_0_[11] ; wire \data_pair_reg_n_0_[12] ; wire \data_pair_reg_n_0_[13] ; wire \data_pair_reg_n_0_[14] ; wire \data_pair_reg_n_0_[15] ; wire \data_pair_reg_n_0_[1] ; wire \data_pair_reg_n_0_[2] ; wire \data_pair_reg_n_0_[3] ; wire \data_pair_reg_n_0_[4] ; wire \data_pair_reg_n_0_[5] ; wire \data_pair_reg_n_0_[6] ; wire \data_pair_reg_n_0_[7] ; wire \data_pair_reg_n_0_[8] ; wire \data_pair_reg_n_0_[9] ; wire [15:0]rgb; wire rgb_regn_0_0; FDRE #( .INIT(1'b0)) cycle_reg (.C(clk_x2), .CE(1'b1), .D(\data_pair[7]_i_1_n_0 ), .Q(cycle), .R(1'b0)); LUT2 #( .INIT(4'h8)) \data_pair[15]_i_1 (.I0(cycle), .I1(active), .O(\data_pair[15]_i_1_n_0 )); LUT2 #( .INIT(4'h2)) \data_pair[7]_i_1 (.I0(active), .I1(cycle), .O(\data_pair[7]_i_1_n_0 )); FDRE \data_pair_reg[0] (.C(clk_x2), .CE(\data_pair[7]_i_1_n_0 ), .D(data[0]), .Q(\data_pair_reg_n_0_[0] ), .R(1'b0)); FDRE \data_pair_reg[10] (.C(clk_x2), .CE(\data_pair[15]_i_1_n_0 ), .D(data[2]), .Q(\data_pair_reg_n_0_[10] ), .R(1'b0)); FDRE \data_pair_reg[11] (.C(clk_x2), .CE(\data_pair[15]_i_1_n_0 ), .D(data[3]), .Q(\data_pair_reg_n_0_[11] ), .R(1'b0)); FDRE \data_pair_reg[12] (.C(clk_x2), .CE(\data_pair[15]_i_1_n_0 ), .D(data[4]), .Q(\data_pair_reg_n_0_[12] ), .R(1'b0)); FDRE \data_pair_reg[13] (.C(clk_x2), .CE(\data_pair[15]_i_1_n_0 ), .D(data[5]), .Q(\data_pair_reg_n_0_[13] ), .R(1'b0)); FDRE \data_pair_reg[14] (.C(clk_x2), .CE(\data_pair[15]_i_1_n_0 ), .D(data[6]), .Q(\data_pair_reg_n_0_[14] ), .R(1'b0)); FDRE \data_pair_reg[15] (.C(clk_x2), .CE(\data_pair[15]_i_1_n_0 ), .D(data[7]), .Q(\data_pair_reg_n_0_[15] ), .R(1'b0)); FDRE \data_pair_reg[1] (.C(clk_x2), .CE(\data_pair[7]_i_1_n_0 ), .D(data[1]), .Q(\data_pair_reg_n_0_[1] ), .R(1'b0)); FDRE \data_pair_reg[2] (.C(clk_x2), .CE(\data_pair[7]_i_1_n_0 ), .D(data[2]), .Q(\data_pair_reg_n_0_[2] ), .R(1'b0)); FDRE \data_pair_reg[3] (.C(clk_x2), .CE(\data_pair[7]_i_1_n_0 ), .D(data[3]), .Q(\data_pair_reg_n_0_[3] ), .R(1'b0)); FDRE \data_pair_reg[4] (.C(clk_x2), .CE(\data_pair[7]_i_1_n_0 ), .D(data[4]), .Q(\data_pair_reg_n_0_[4] ), .R(1'b0)); FDRE \data_pair_reg[5] (.C(clk_x2), .CE(\data_pair[7]_i_1_n_0 ), .D(data[5]), .Q(\data_pair_reg_n_0_[5] ), .R(1'b0)); FDRE \data_pair_reg[6] (.C(clk_x2), .CE(\data_pair[7]_i_1_n_0 ), .D(data[6]), .Q(\data_pair_reg_n_0_[6] ), .R(1'b0)); FDRE \data_pair_reg[7] (.C(clk_x2), .CE(\data_pair[7]_i_1_n_0 ), .D(data[7]), .Q(\data_pair_reg_n_0_[7] ), .R(1'b0)); FDRE \data_pair_reg[8] (.C(clk_x2), .CE(\data_pair[15]_i_1_n_0 ), .D(data[0]), .Q(\data_pair_reg_n_0_[8] ), .R(1'b0)); FDRE \data_pair_reg[9] (.C(clk_x2), .CE(\data_pair[15]_i_1_n_0 ), .D(data[1]), .Q(\data_pair_reg_n_0_[9] ), .R(1'b0)); FDRE \rgb_reg[0] (.C(rgb_regn_0_0), .CE(cycle), .D(\data_pair_reg_n_0_[0] ), .Q(rgb[0]), .R(1'b0)); FDRE \rgb_reg[10] (.C(rgb_regn_0_0), .CE(cycle), .D(\data_pair_reg_n_0_[10] ), .Q(rgb[10]), .R(1'b0)); FDRE \rgb_reg[11] (.C(rgb_regn_0_0), .CE(cycle), .D(\data_pair_reg_n_0_[11] ), .Q(rgb[11]), .R(1'b0)); FDRE \rgb_reg[12] (.C(rgb_regn_0_0), .CE(cycle), .D(\data_pair_reg_n_0_[12] ), .Q(rgb[12]), .R(1'b0)); FDRE \rgb_reg[13] (.C(rgb_regn_0_0), .CE(cycle), .D(\data_pair_reg_n_0_[13] ), .Q(rgb[13]), .R(1'b0)); FDRE \rgb_reg[14] (.C(rgb_regn_0_0), .CE(cycle), .D(\data_pair_reg_n_0_[14] ), .Q(rgb[14]), .R(1'b0)); FDRE \rgb_reg[15] (.C(rgb_regn_0_0), .CE(cycle), .D(\data_pair_reg_n_0_[15] ), .Q(rgb[15]), .R(1'b0)); FDRE \rgb_reg[1] (.C(rgb_regn_0_0), .CE(cycle), .D(\data_pair_reg_n_0_[1] ), .Q(rgb[1]), .R(1'b0)); FDRE \rgb_reg[2] (.C(rgb_regn_0_0), .CE(cycle), .D(\data_pair_reg_n_0_[2] ), .Q(rgb[2]), .R(1'b0)); FDRE \rgb_reg[3] (.C(rgb_regn_0_0), .CE(cycle), .D(\data_pair_reg_n_0_[3] ), .Q(rgb[3]), .R(1'b0)); FDRE \rgb_reg[4] (.C(rgb_regn_0_0), .CE(cycle), .D(\data_pair_reg_n_0_[4] ), .Q(rgb[4]), .R(1'b0)); FDRE \rgb_reg[5] (.C(rgb_regn_0_0), .CE(cycle), .D(\data_pair_reg_n_0_[5] ), .Q(rgb[5]), .R(1'b0)); FDRE \rgb_reg[6] (.C(rgb_regn_0_0), .CE(cycle), .D(\data_pair_reg_n_0_[6] ), .Q(rgb[6]), .R(1'b0)); FDRE \rgb_reg[7] (.C(rgb_regn_0_0), .CE(cycle), .D(\data_pair_reg_n_0_[7] ), .Q(rgb[7]), .R(1'b0)); FDRE \rgb_reg[8] (.C(rgb_regn_0_0), .CE(cycle), .D(\data_pair_reg_n_0_[8] ), .Q(rgb[8]), .R(1'b0)); FDRE \rgb_reg[9] (.C(rgb_regn_0_0), .CE(cycle), .D(\data_pair_reg_n_0_[9] ), .Q(rgb[9]), .R(1'b0)); LUT1 #( .INIT(2'h1)) rgb_regi_0 (.I0(clk_x2), .O(rgb_regn_0_0)); endmodule
module glbl (); parameter ROC_WIDTH = 100000; parameter TOC_WIDTH = 0; //-------- STARTUP Globals -------------- wire GSR; wire GTS; wire GWE; wire PRLD; tri1 p_up_tmp; tri (weak1, strong0) PLL_LOCKG = p_up_tmp; wire PROGB_GLBL; wire CCLKO_GLBL; wire FCSBO_GLBL; wire [3:0] DO_GLBL; wire [3:0] DI_GLBL; reg GSR_int; reg GTS_int; reg PRLD_int; //-------- JTAG Globals -------------- wire JTAG_TDO_GLBL; wire JTAG_TCK_GLBL; wire JTAG_TDI_GLBL; wire JTAG_TMS_GLBL; wire JTAG_TRST_GLBL; reg JTAG_CAPTURE_GLBL; reg JTAG_RESET_GLBL; reg JTAG_SHIFT_GLBL; reg JTAG_UPDATE_GLBL; reg JTAG_RUNTEST_GLBL; reg JTAG_SEL1_GLBL = 0; reg JTAG_SEL2_GLBL = 0 ; reg JTAG_SEL3_GLBL = 0; reg JTAG_SEL4_GLBL = 0; reg JTAG_USER_TDO1_GLBL = 1'bz; reg JTAG_USER_TDO2_GLBL = 1'bz; reg JTAG_USER_TDO3_GLBL = 1'bz; reg JTAG_USER_TDO4_GLBL = 1'bz; assign (weak1, weak0) GSR = GSR_int; assign (weak1, weak0) GTS = GTS_int; assign (weak1, weak0) PRLD = PRLD_int; initial begin GSR_int = 1'b1; PRLD_int = 1'b1; #(ROC_WIDTH) GSR_int = 1'b0; PRLD_int = 1'b0; end initial begin GTS_int = 1'b1; #(TOC_WIDTH) GTS_int = 1'b0; end endmodule
module sky130_fd_sc_hdll__nor4b ( Y , A , B , C , D_N , VPWR, VGND, VPB , VNB ); // Module ports output Y ; input A ; input B ; input C ; input D_N ; input VPWR; input VGND; input VPB ; input VNB ; // Local signals wire not0_out ; wire nor0_out_Y ; wire pwrgood_pp0_out_Y; // Name Output Other arguments not not0 (not0_out , D_N ); nor nor0 (nor0_out_Y , A, B, C, not0_out ); sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nor0_out_Y, VPWR, VGND); buf buf0 (Y , pwrgood_pp0_out_Y ); endmodule
module LOGIC ( input [`NUM_NODES-1:0] i, output [`NUM_NODES-1:0] o); `include "logic.inc" endmodule
module chip_6502 ( input clk, // FPGA clock input phi, // 6502 clock input res, input so, input rdy, input nmi, input irq, input [7:0] dbi, output [7:0] dbo, output rw, output sync, output [15:0] ab); // Node states wire [`NUM_NODES-1:0] no; reg [`NUM_NODES-1:0] ni, q; initial q = `NUM_NODES'b0; LOGIC logic_00 (.i(ni), .o(no)); always @ (posedge clk) q <= no; always @* begin ni = q; ni[`NODE_vcc ] = 1'b1; ni[`NODE_vss ] = 1'b0; ni[`NODE_res ] = res; ni[`NODE_clk0] = phi; ni[`NODE_so ] = so; ni[`NODE_rdy ] = rdy; ni[`NODE_nmi ] = nmi; ni[`NODE_irq ] = irq; {ni[`NODE_db7],ni[`NODE_db6],ni[`NODE_db5],ni[`NODE_db4], ni[`NODE_db3],ni[`NODE_db2],ni[`NODE_db1],ni[`NODE_db0]} = dbi[7:0]; end assign dbo[7:0] = { no[`NODE_db7],no[`NODE_db6],no[`NODE_db5],no[`NODE_db4], no[`NODE_db3],no[`NODE_db2],no[`NODE_db1],no[`NODE_db0] }; assign ab[15:0] = { no[`NODE_ab15], no[`NODE_ab14], no[`NODE_ab13], no[`NODE_ab12], no[`NODE_ab11], no[`NODE_ab10], no[`NODE_ab9], no[`NODE_ab8], no[`NODE_ab7], no[`NODE_ab6], no[`NODE_ab5], no[`NODE_ab4], no[`NODE_ab3], no[`NODE_ab2], no[`NODE_ab1], no[`NODE_ab0] }; assign rw = no[`NODE_rw]; assign sync = no[`NODE_sync]; endmodule
module tb_acs(); // Declare integers // Counter for the FOR loop enumeration integer count; // Multichannel descriptor for associated file that is opened integer md_fopen; // Randomly generated input data bit for the transmitter reg data; // Declare constants // Maximum number of data bits in the stream parameter max_amt_of_data = 8'd255; /** * Initial block start executing sequentially @ t=0 * If and when a delay is encountered, the execution of this block * pauses or waits until the delay time has passed, before resuming * execution * * Each intial or always block executes concurrently; that is, * multiple "always" or "initial" blocks will execute simultaneously * * E.g. * always * begin * #10 clk_50 = ~clk_50; // Invert clock signal every 10 ns * // Clock signal has a period of 20 ns or 50 MHz * end */ initial begin // "$time" indicates the current time in the simulation $display(" << Starting the simulation >>"); /** * $display automatically adds a newline character to * the end of its output, whereas the $write task does not. * * Any null parameter produces a single space character * in the display. (A null parameter is characterized by * two adjacent commas in the parameter list.) * * */ // Open a file channel descriptor for writing md_fopen=$fopen("testfile.bit"); /** * Assert that the file can be opened for read/write * operations; else, end the simulation/execution */ if (md_fopen == 0) $finish; // Write a stream of 256 bits to the output file for(count=0; count<max_amt_of_data; count=count+1) begin /** * Assign the input data bit to a randomly * generated number */ data = $random; //$fwrite(md_fopen,data); $fdisplay(md_fopen,data); end /** * Assign the last input data bit to a randomly * generated number */ data = $random; $fdisplay(md_fopen,data); // Close a file channel descriptor for writing $fclose(md_fopen); #20; $display(" << Finishing the simulation >>"); $finish; end endmodule
module sky130_fd_io__top_ground_hvc_wpad ( G_PAD , AMUXBUS_A, AMUXBUS_B ); inout G_PAD ; inout AMUXBUS_A; inout AMUXBUS_B; // Voltage supply signals supply1 OGC_HVC ; supply1 DRN_HVC ; supply0 SRC_BDY_HVC; supply0 G_CORE ; supply1 VDDIO ; supply1 VDDIO_Q ; supply1 VDDA ; supply1 VCCD ; supply1 VSWITCH ; supply1 VCCHIB ; supply0 VSSA ; supply0 VSSD ; supply0 VSSIO_Q ; supply0 VSSIO ; endmodule
module bit1_bit0_parity1_parity0_ez_instance__state_net(bit1, bit0, parity1, parity0, ez_instance__state); wire _00_; wire _01_; wire _02_; wire _03_; wire _04_; wire _05_; wire _06_; wire _07_; wire _08_; wire _09_; wire _10_; wire _11_; wire _12_; wire _13_; wire _14_; (* src = "/Users/tramyn/Documents/workspaces/cello_workspace/yosysRun/evenzeroes.v:7" *) input bit0; (* src = "/Users/tramyn/Documents/workspaces/cello_workspace/yosysRun/evenzeroes.v:6" *) input bit1; (* src = "/Users/tramyn/Documents/workspaces/cello_workspace/yosysRun/evenzeroes.v:10" *) output ez_instance__state; (* src = "/Users/tramyn/Documents/workspaces/cello_workspace/yosysRun/evenzeroes.v:9" *) output parity0; (* src = "/Users/tramyn/Documents/workspaces/cello_workspace/yosysRun/evenzeroes.v:8" *) output parity1; assign ez_instance__state = ~(_04_ | _10_); assign _11_ = ~(_14_ | ez_instance__state); assign _12_ = ~(parity1 | _05_); assign _13_ = ~(_00_ | _12_); assign _02_ = ~(_11_ | _13_); assign parity1 = ~_02_; assign _14_ = ~bit1; assign _00_ = ~bit0; assign _01_ = ~ez_instance__state; assign _03_ = ~(_14_ | _01_); assign _04_ = ~(parity0 | _02_); assign _05_ = ~(_01_ | parity0); assign _06_ = ~(_00_ | _05_); assign _07_ = ~_06_; assign _08_ = ~(_04_ | _07_); assign _09_ = ~(_03_ | _08_); assign parity0 = ~_09_; assign _10_ = ~(ez_instance__state | parity0); endmodule
module sky130_fd_sc_hd__nand2b_4 ( Y , A_N , B , VPWR, VGND, VPB , VNB ); output Y ; input A_N ; input B ; input VPWR; input VGND; input VPB ; input VNB ; sky130_fd_sc_hd__nand2b base ( .Y(Y), .A_N(A_N), .B(B), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB) ); endmodule
module sky130_fd_sc_hd__nand2b_4 ( Y , A_N, B ); output Y ; input A_N; input B ; // Voltage supply signals supply1 VPWR; supply0 VGND; supply1 VPB ; supply0 VNB ; sky130_fd_sc_hd__nand2b base ( .Y(Y), .A_N(A_N), .B(B) ); endmodule
module sky130_fd_sc_hdll__sdfbbp ( Q , Q_N , D , SCD , SCE , CLK , SET_B , RESET_B ); output Q ; output Q_N ; input D ; input SCD ; input SCE ; input CLK ; input SET_B ; input RESET_B; // Voltage supply signals supply1 VPWR; supply0 VGND; supply1 VPB ; supply0 VNB ; endmodule
module sky130_fd_sc_lp__nand3 ( Y, A, B, C ); // Module ports output Y; input A; input B; input C; // Local signals wire nand0_out_Y; // Name Output Other arguments nand nand0 (nand0_out_Y, B, A, C ); buf buf0 (Y , nand0_out_Y ); endmodule
module mcb_ui_top # ( /////////////////////////////////////////////////////////////////////////////// // Parameter Definitions /////////////////////////////////////////////////////////////////////////////// // Raw Wrapper Parameters parameter C_MEMCLK_PERIOD = 2500, parameter C_PORT_ENABLE = 6'b111111, parameter C_MEM_ADDR_ORDER = "BANK_ROW_COLUMN", parameter C_ARB_ALGORITHM = 0, parameter C_ARB_NUM_TIME_SLOTS = 12, parameter C_ARB_TIME_SLOT_0 = 18'o012345, parameter C_ARB_TIME_SLOT_1 = 18'o123450, parameter C_ARB_TIME_SLOT_2 = 18'o234501, parameter C_ARB_TIME_SLOT_3 = 18'o345012, parameter C_ARB_TIME_SLOT_4 = 18'o450123, parameter C_ARB_TIME_SLOT_5 = 18'o501234, parameter C_ARB_TIME_SLOT_6 = 18'o012345, parameter C_ARB_TIME_SLOT_7 = 18'o123450, parameter C_ARB_TIME_SLOT_8 = 18'o234501, parameter C_ARB_TIME_SLOT_9 = 18'o345012, parameter C_ARB_TIME_SLOT_10 = 18'o450123, parameter C_ARB_TIME_SLOT_11 = 18'o501234, parameter C_PORT_CONFIG = "B128", parameter C_MEM_TRAS = 45000, parameter C_MEM_TRCD = 12500, parameter C_MEM_TREFI = 7800, parameter C_MEM_TRFC = 127500, parameter C_MEM_TRP = 12500, parameter C_MEM_TWR = 15000, parameter C_MEM_TRTP = 7500, parameter C_MEM_TWTR = 7500, parameter C_NUM_DQ_PINS = 8, parameter C_MEM_TYPE = "DDR3", parameter C_MEM_DENSITY = "512M", parameter C_MEM_BURST_LEN = 8, parameter C_MEM_CAS_LATENCY = 4, parameter C_MEM_ADDR_WIDTH = 13, parameter C_MEM_BANKADDR_WIDTH = 3, parameter C_MEM_NUM_COL_BITS = 11, parameter C_MEM_DDR3_CAS_LATENCY = 7, parameter C_MEM_MOBILE_PA_SR = "FULL", parameter C_MEM_DDR1_2_ODS = "FULL", parameter C_MEM_DDR3_ODS = "DIV6", parameter C_MEM_DDR2_RTT = "50OHMS", parameter C_MEM_DDR3_RTT = "DIV2", parameter C_MEM_MDDR_ODS = "FULL", parameter C_MEM_DDR2_DIFF_DQS_EN = "YES", parameter C_MEM_DDR2_3_PA_SR = "OFF", parameter C_MEM_DDR3_CAS_WR_LATENCY = 5, parameter C_MEM_DDR3_AUTO_SR = "ENABLED", parameter C_MEM_DDR2_3_HIGH_TEMP_SR = "NORMAL", parameter C_MEM_DDR3_DYN_WRT_ODT = "OFF", parameter C_MEM_TZQINIT_MAXCNT = 10'd512, parameter C_MC_CALIB_BYPASS = "NO", parameter C_MC_CALIBRATION_RA = 15'h0000, parameter C_MC_CALIBRATION_BA = 3'h0, parameter C_CALIB_SOFT_IP = "TRUE", parameter C_SKIP_IN_TERM_CAL = 1'b0, parameter C_SKIP_DYNAMIC_CAL = 1'b0, parameter C_SKIP_DYN_IN_TERM = 1'b1, parameter LDQSP_TAP_DELAY_VAL = 0, parameter UDQSP_TAP_DELAY_VAL = 0, parameter LDQSN_TAP_DELAY_VAL = 0, parameter UDQSN_TAP_DELAY_VAL = 0, parameter DQ0_TAP_DELAY_VAL = 0, parameter DQ1_TAP_DELAY_VAL = 0, parameter DQ2_TAP_DELAY_VAL = 0, parameter DQ3_TAP_DELAY_VAL = 0, parameter DQ4_TAP_DELAY_VAL = 0, parameter DQ5_TAP_DELAY_VAL = 0, parameter DQ6_TAP_DELAY_VAL = 0, parameter DQ7_TAP_DELAY_VAL = 0, parameter DQ8_TAP_DELAY_VAL = 0, parameter DQ9_TAP_DELAY_VAL = 0, parameter DQ10_TAP_DELAY_VAL = 0, parameter DQ11_TAP_DELAY_VAL = 0, parameter DQ12_TAP_DELAY_VAL = 0, parameter DQ13_TAP_DELAY_VAL = 0, parameter DQ14_TAP_DELAY_VAL = 0, parameter DQ15_TAP_DELAY_VAL = 0, parameter C_MC_CALIBRATION_CA = 12'h000, parameter C_MC_CALIBRATION_CLK_DIV = 1, parameter C_MC_CALIBRATION_MODE = "CALIBRATION", parameter C_MC_CALIBRATION_DELAY = "HALF", parameter C_SIMULATION = "FALSE", parameter C_P0_MASK_SIZE = 4, parameter C_P0_DATA_PORT_SIZE = 32, parameter C_P1_MASK_SIZE = 4, parameter C_P1_DATA_PORT_SIZE = 32, parameter integer C_MCB_USE_EXTERNAL_BUFPLL = 1, // AXI Parameters parameter C_S0_AXI_BASEADDR = 32'h00000000, parameter C_S0_AXI_HIGHADDR = 32'h00000000, parameter integer C_S0_AXI_ENABLE = 0, parameter integer C_S0_AXI_ID_WIDTH = 4, parameter integer C_S0_AXI_ADDR_WIDTH = 64, parameter integer C_S0_AXI_DATA_WIDTH = 32, parameter integer C_S0_AXI_SUPPORTS_READ = 1, parameter integer C_S0_AXI_SUPPORTS_WRITE = 1, parameter integer C_S0_AXI_SUPPORTS_NARROW_BURST = 1, parameter C_S0_AXI_REG_EN0 = 20'h00000, parameter C_S0_AXI_REG_EN1 = 20'h01000, parameter integer C_S0_AXI_STRICT_COHERENCY = 1, parameter integer C_S0_AXI_ENABLE_AP = 0, parameter C_S1_AXI_BASEADDR = 32'h00000000, parameter C_S1_AXI_HIGHADDR = 32'h00000000, parameter integer C_S1_AXI_ENABLE = 0, parameter integer C_S1_AXI_ID_WIDTH = 4, parameter integer C_S1_AXI_ADDR_WIDTH = 64, parameter integer C_S1_AXI_DATA_WIDTH = 32, parameter integer C_S1_AXI_SUPPORTS_READ = 1, parameter integer C_S1_AXI_SUPPORTS_WRITE = 1, parameter integer C_S1_AXI_SUPPORTS_NARROW_BURST = 1, parameter C_S1_AXI_REG_EN0 = 20'h00000, parameter C_S1_AXI_REG_EN1 = 20'h01000, parameter integer C_S1_AXI_STRICT_COHERENCY = 1, parameter integer C_S1_AXI_ENABLE_AP = 0, parameter C_S2_AXI_BASEADDR = 32'h00000000, parameter C_S2_AXI_HIGHADDR = 32'h00000000, parameter integer C_S2_AXI_ENABLE = 0, parameter integer C_S2_AXI_ID_WIDTH = 4, parameter integer C_S2_AXI_ADDR_WIDTH = 64, parameter integer C_S2_AXI_DATA_WIDTH = 32, parameter integer C_S2_AXI_SUPPORTS_READ = 1, parameter integer C_S2_AXI_SUPPORTS_WRITE = 1, parameter integer C_S2_AXI_SUPPORTS_NARROW_BURST = 1, parameter C_S2_AXI_REG_EN0 = 20'h00000, parameter C_S2_AXI_REG_EN1 = 20'h01000, parameter integer C_S2_AXI_STRICT_COHERENCY = 1, parameter integer C_S2_AXI_ENABLE_AP = 0, parameter C_S3_AXI_BASEADDR = 32'h00000000, parameter C_S3_AXI_HIGHADDR = 32'h00000000, parameter integer C_S3_AXI_ENABLE = 0, parameter integer C_S3_AXI_ID_WIDTH = 4, parameter integer C_S3_AXI_ADDR_WIDTH = 64, parameter integer C_S3_AXI_DATA_WIDTH = 32, parameter integer C_S3_AXI_SUPPORTS_READ = 1, parameter integer C_S3_AXI_SUPPORTS_WRITE = 1, parameter integer C_S3_AXI_SUPPORTS_NARROW_BURST = 1, parameter C_S3_AXI_REG_EN0 = 20'h00000, parameter C_S3_AXI_REG_EN1 = 20'h01000, parameter integer C_S3_AXI_STRICT_COHERENCY = 1, parameter integer C_S3_AXI_ENABLE_AP = 0, parameter C_S4_AXI_BASEADDR = 32'h00000000, parameter C_S4_AXI_HIGHADDR = 32'h00000000, parameter integer C_S4_AXI_ENABLE = 0, parameter integer C_S4_AXI_ID_WIDTH = 4, parameter integer C_S4_AXI_ADDR_WIDTH = 64, parameter integer C_S4_AXI_DATA_WIDTH = 32, parameter integer C_S4_AXI_SUPPORTS_READ = 1, parameter integer C_S4_AXI_SUPPORTS_WRITE = 1, parameter integer C_S4_AXI_SUPPORTS_NARROW_BURST = 1, parameter C_S4_AXI_REG_EN0 = 20'h00000, parameter C_S4_AXI_REG_EN1 = 20'h01000, parameter integer C_S4_AXI_STRICT_COHERENCY = 1, parameter integer C_S4_AXI_ENABLE_AP = 0, parameter C_S5_AXI_BASEADDR = 32'h00000000, parameter C_S5_AXI_HIGHADDR = 32'h00000000, parameter integer C_S5_AXI_ENABLE = 0, parameter integer C_S5_AXI_ID_WIDTH = 4, parameter integer C_S5_AXI_ADDR_WIDTH = 64, parameter integer C_S5_AXI_DATA_WIDTH = 32, parameter integer C_S5_AXI_SUPPORTS_READ = 1, parameter integer C_S5_AXI_SUPPORTS_WRITE = 1, parameter integer C_S5_AXI_SUPPORTS_NARROW_BURST = 1, parameter C_S5_AXI_REG_EN0 = 20'h00000, parameter C_S5_AXI_REG_EN1 = 20'h01000, parameter integer C_S5_AXI_STRICT_COHERENCY = 1, parameter integer C_S5_AXI_ENABLE_AP = 0 ) ( /////////////////////////////////////////////////////////////////////////////// // Port Declarations /////////////////////////////////////////////////////////////////////////////// // Raw Wrapper Signals input sysclk_2x , input sysclk_2x_180 , input pll_ce_0 , input pll_ce_90 , output sysclk_2x_bufpll_o , output sysclk_2x_180_bufpll_o, output pll_ce_0_bufpll_o , output pll_ce_90_bufpll_o , output pll_lock_bufpll_o , input pll_lock , input sys_rst , input p0_arb_en , input p0_cmd_clk , input p0_cmd_en , input [2:0] p0_cmd_instr , input [5:0] p0_cmd_bl , input [29:0] p0_cmd_byte_addr , output p0_cmd_empty , output p0_cmd_full , input p0_wr_clk , input p0_wr_en , input [C_P0_MASK_SIZE-1:0] p0_wr_mask , input [C_P0_DATA_PORT_SIZE-1:0] p0_wr_data , output p0_wr_full , output p0_wr_empty , output [6:0] p0_wr_count , output p0_wr_underrun , output p0_wr_error , input p0_rd_clk , input p0_rd_en , output [C_P0_DATA_PORT_SIZE-1:0] p0_rd_data , output p0_rd_full , output p0_rd_empty , output [6:0] p0_rd_count , output p0_rd_overflow , output p0_rd_error , input p1_arb_en , input p1_cmd_clk , input p1_cmd_en , input [2:0] p1_cmd_instr , input [5:0] p1_cmd_bl , input [29:0] p1_cmd_byte_addr , output p1_cmd_empty , output p1_cmd_full , input p1_wr_clk , input p1_wr_en , input [C_P1_MASK_SIZE-1:0] p1_wr_mask , input [C_P1_DATA_PORT_SIZE-1:0] p1_wr_data , output p1_wr_full , output p1_wr_empty , output [6:0] p1_wr_count , output p1_wr_underrun , output p1_wr_error , input p1_rd_clk , input p1_rd_en , output [C_P1_DATA_PORT_SIZE-1:0] p1_rd_data , output p1_rd_full , output p1_rd_empty , output [6:0] p1_rd_count , output p1_rd_overflow , output p1_rd_error , input p2_arb_en , input p2_cmd_clk , input p2_cmd_en , input [2:0] p2_cmd_instr , input [5:0] p2_cmd_bl , input [29:0] p2_cmd_byte_addr , output p2_cmd_empty , output p2_cmd_full , input p2_wr_clk , input p2_wr_en , input [3:0] p2_wr_mask , input [31:0] p2_wr_data , output p2_wr_full , output p2_wr_empty , output [6:0] p2_wr_count , output p2_wr_underrun , output p2_wr_error , input p2_rd_clk , input p2_rd_en , output [31:0] p2_rd_data , output p2_rd_full , output p2_rd_empty , output [6:0] p2_rd_count , output p2_rd_overflow , output p2_rd_error , input p3_arb_en , input p3_cmd_clk , input p3_cmd_en , input [2:0] p3_cmd_instr , input [5:0] p3_cmd_bl , input [29:0] p3_cmd_byte_addr , output p3_cmd_empty , output p3_cmd_full , input p3_wr_clk , input p3_wr_en , input [3:0] p3_wr_mask , input [31:0] p3_wr_data , output p3_wr_full , output p3_wr_empty , output [6:0] p3_wr_count , output p3_wr_underrun , output p3_wr_error , input p3_rd_clk , input p3_rd_en , output [31:0] p3_rd_data , output p3_rd_full , output p3_rd_empty , output [6:0] p3_rd_count , output p3_rd_overflow , output p3_rd_error , input p4_arb_en , input p4_cmd_clk , input p4_cmd_en , input [2:0] p4_cmd_instr , input [5:0] p4_cmd_bl , input [29:0] p4_cmd_byte_addr , output p4_cmd_empty , output p4_cmd_full , input p4_wr_clk , input p4_wr_en , input [3:0] p4_wr_mask , input [31:0] p4_wr_data , output p4_wr_full , output p4_wr_empty , output [6:0] p4_wr_count , output p4_wr_underrun , output p4_wr_error , input p4_rd_clk , input p4_rd_en , output [31:0] p4_rd_data , output p4_rd_full , output p4_rd_empty , output [6:0] p4_rd_count , output p4_rd_overflow , output p4_rd_error , input p5_arb_en , input p5_cmd_clk , input p5_cmd_en , input [2:0] p5_cmd_instr , input [5:0] p5_cmd_bl , input [29:0] p5_cmd_byte_addr , output p5_cmd_empty , output p5_cmd_full , input p5_wr_clk , input p5_wr_en , input [3:0] p5_wr_mask , input [31:0] p5_wr_data , output p5_wr_full , output p5_wr_empty , output [6:0] p5_wr_count , output p5_wr_underrun , output p5_wr_error , input p5_rd_clk , input p5_rd_en , output [31:0] p5_rd_data , output p5_rd_full , output p5_rd_empty , output [6:0] p5_rd_count , output p5_rd_overflow , output p5_rd_error , output [C_MEM_ADDR_WIDTH-1:0] mcbx_dram_addr , output [C_MEM_BANKADDR_WIDTH-1:0] mcbx_dram_ba , output mcbx_dram_ras_n , output mcbx_dram_cas_n , output mcbx_dram_we_n , output mcbx_dram_cke , output mcbx_dram_clk , output mcbx_dram_clk_n , inout [C_NUM_DQ_PINS-1:0] mcbx_dram_dq , inout mcbx_dram_dqs , inout mcbx_dram_dqs_n , inout mcbx_dram_udqs , inout mcbx_dram_udqs_n , output mcbx_dram_udm , output mcbx_dram_ldm , output mcbx_dram_odt , output mcbx_dram_ddr3_rst , input calib_recal , inout rzq , inout zio , input ui_read , input ui_add , input ui_cs , input ui_clk , input ui_sdi , input [4:0] ui_addr , input ui_broadcast , input ui_drp_update , input ui_done_cal , input ui_cmd , input ui_cmd_in , input ui_cmd_en , input [3:0] ui_dqcount , input ui_dq_lower_dec , input ui_dq_lower_inc , input ui_dq_upper_dec , input ui_dq_upper_inc , input ui_udqs_inc , input ui_udqs_dec , input ui_ldqs_inc , input ui_ldqs_dec , output [7:0] uo_data , output uo_data_valid , output uo_done_cal , output uo_cmd_ready_in , output uo_refrsh_flag , output uo_cal_start , output uo_sdo , output [31:0] status , input selfrefresh_enter , output selfrefresh_mode , // AXI Signals input wire s0_axi_aclk , input wire s0_axi_aresetn , input wire [C_S0_AXI_ID_WIDTH-1:0] s0_axi_awid , input wire [C_S0_AXI_ADDR_WIDTH-1:0] s0_axi_awaddr , input wire [7:0] s0_axi_awlen , input wire [2:0] s0_axi_awsize , input wire [1:0] s0_axi_awburst , input wire [0:0] s0_axi_awlock , input wire [3:0] s0_axi_awcache , input wire [2:0] s0_axi_awprot , input wire [3:0] s0_axi_awqos , input wire s0_axi_awvalid , output wire s0_axi_awready , input wire [C_S0_AXI_DATA_WIDTH-1:0] s0_axi_wdata , input wire [C_S0_AXI_DATA_WIDTH/8-1:0] s0_axi_wstrb , input wire s0_axi_wlast , input wire s0_axi_wvalid , output wire s0_axi_wready , output wire [C_S0_AXI_ID_WIDTH-1:0] s0_axi_bid , output wire [1:0] s0_axi_bresp , output wire s0_axi_bvalid , input wire s0_axi_bready , input wire [C_S0_AXI_ID_WIDTH-1:0] s0_axi_arid , input wire [C_S0_AXI_ADDR_WIDTH-1:0] s0_axi_araddr , input wire [7:0] s0_axi_arlen , input wire [2:0] s0_axi_arsize , input wire [1:0] s0_axi_arburst , input wire [0:0] s0_axi_arlock , input wire [3:0] s0_axi_arcache , input wire [2:0] s0_axi_arprot , input wire [3:0] s0_axi_arqos , input wire s0_axi_arvalid , output wire s0_axi_arready , output wire [C_S0_AXI_ID_WIDTH-1:0] s0_axi_rid , output wire [C_S0_AXI_DATA_WIDTH-1:0] s0_axi_rdata , output wire [1:0] s0_axi_rresp , output wire s0_axi_rlast , output wire s0_axi_rvalid , input wire s0_axi_rready , input wire s1_axi_aclk , input wire s1_axi_aresetn , input wire [C_S1_AXI_ID_WIDTH-1:0] s1_axi_awid , input wire [C_S1_AXI_ADDR_WIDTH-1:0] s1_axi_awaddr , input wire [7:0] s1_axi_awlen , input wire [2:0] s1_axi_awsize , input wire [1:0] s1_axi_awburst , input wire [0:0] s1_axi_awlock , input wire [3:0] s1_axi_awcache , input wire [2:0] s1_axi_awprot , input wire [3:0] s1_axi_awqos , input wire s1_axi_awvalid , output wire s1_axi_awready , input wire [C_S1_AXI_DATA_WIDTH-1:0] s1_axi_wdata , input wire [C_S1_AXI_DATA_WIDTH/8-1:0] s1_axi_wstrb , input wire s1_axi_wlast , input wire s1_axi_wvalid , output wire s1_axi_wready , output wire [C_S1_AXI_ID_WIDTH-1:0] s1_axi_bid , output wire [1:0] s1_axi_bresp , output wire s1_axi_bvalid , input wire s1_axi_bready , input wire [C_S1_AXI_ID_WIDTH-1:0] s1_axi_arid , input wire [C_S1_AXI_ADDR_WIDTH-1:0] s1_axi_araddr , input wire [7:0] s1_axi_arlen , input wire [2:0] s1_axi_arsize , input wire [1:0] s1_axi_arburst , input wire [0:0] s1_axi_arlock , input wire [3:0] s1_axi_arcache , input wire [2:0] s1_axi_arprot , input wire [3:0] s1_axi_arqos , input wire s1_axi_arvalid , output wire s1_axi_arready , output wire [C_S1_AXI_ID_WIDTH-1:0] s1_axi_rid , output wire [C_S1_AXI_DATA_WIDTH-1:0] s1_axi_rdata , output wire [1:0] s1_axi_rresp , output wire s1_axi_rlast , output wire s1_axi_rvalid , input wire s1_axi_rready , input wire s2_axi_aclk , input wire s2_axi_aresetn , input wire [C_S2_AXI_ID_WIDTH-1:0] s2_axi_awid , input wire [C_S2_AXI_ADDR_WIDTH-1:0] s2_axi_awaddr , input wire [7:0] s2_axi_awlen , input wire [2:0] s2_axi_awsize , input wire [1:0] s2_axi_awburst , input wire [0:0] s2_axi_awlock , input wire [3:0] s2_axi_awcache , input wire [2:0] s2_axi_awprot , input wire [3:0] s2_axi_awqos , input wire s2_axi_awvalid , output wire s2_axi_awready , input wire [C_S2_AXI_DATA_WIDTH-1:0] s2_axi_wdata , input wire [C_S2_AXI_DATA_WIDTH/8-1:0] s2_axi_wstrb , input wire s2_axi_wlast , input wire s2_axi_wvalid , output wire s2_axi_wready , output wire [C_S2_AXI_ID_WIDTH-1:0] s2_axi_bid , output wire [1:0] s2_axi_bresp , output wire s2_axi_bvalid , input wire s2_axi_bready , input wire [C_S2_AXI_ID_WIDTH-1:0] s2_axi_arid , input wire [C_S2_AXI_ADDR_WIDTH-1:0] s2_axi_araddr , input wire [7:0] s2_axi_arlen , input wire [2:0] s2_axi_arsize , input wire [1:0] s2_axi_arburst , input wire [0:0] s2_axi_arlock , input wire [3:0] s2_axi_arcache , input wire [2:0] s2_axi_arprot , input wire [3:0] s2_axi_arqos , input wire s2_axi_arvalid , output wire s2_axi_arready , output wire [C_S2_AXI_ID_WIDTH-1:0] s2_axi_rid , output wire [C_S2_AXI_DATA_WIDTH-1:0] s2_axi_rdata , output wire [1:0] s2_axi_rresp , output wire s2_axi_rlast , output wire s2_axi_rvalid , input wire s2_axi_rready , input wire s3_axi_aclk , input wire s3_axi_aresetn , input wire [C_S3_AXI_ID_WIDTH-1:0] s3_axi_awid , input wire [C_S3_AXI_ADDR_WIDTH-1:0] s3_axi_awaddr , input wire [7:0] s3_axi_awlen , input wire [2:0] s3_axi_awsize , input wire [1:0] s3_axi_awburst , input wire [0:0] s3_axi_awlock , input wire [3:0] s3_axi_awcache , input wire [2:0] s3_axi_awprot , input wire [3:0] s3_axi_awqos , input wire s3_axi_awvalid , output wire s3_axi_awready , input wire [C_S3_AXI_DATA_WIDTH-1:0] s3_axi_wdata , input wire [C_S3_AXI_DATA_WIDTH/8-1:0] s3_axi_wstrb , input wire s3_axi_wlast , input wire s3_axi_wvalid , output wire s3_axi_wready , output wire [C_S3_AXI_ID_WIDTH-1:0] s3_axi_bid , output wire [1:0] s3_axi_bresp , output wire s3_axi_bvalid , input wire s3_axi_bready , input wire [C_S3_AXI_ID_WIDTH-1:0] s3_axi_arid , input wire [C_S3_AXI_ADDR_WIDTH-1:0] s3_axi_araddr , input wire [7:0] s3_axi_arlen , input wire [2:0] s3_axi_arsize , input wire [1:0] s3_axi_arburst , input wire [0:0] s3_axi_arlock , input wire [3:0] s3_axi_arcache , input wire [2:0] s3_axi_arprot , input wire [3:0] s3_axi_arqos , input wire s3_axi_arvalid , output wire s3_axi_arready , output wire [C_S3_AXI_ID_WIDTH-1:0] s3_axi_rid , output wire [C_S3_AXI_DATA_WIDTH-1:0] s3_axi_rdata , output wire [1:0] s3_axi_rresp , output wire s3_axi_rlast , output wire s3_axi_rvalid , input wire s3_axi_rready , input wire s4_axi_aclk , input wire s4_axi_aresetn , input wire [C_S4_AXI_ID_WIDTH-1:0] s4_axi_awid , input wire [C_S4_AXI_ADDR_WIDTH-1:0] s4_axi_awaddr , input wire [7:0] s4_axi_awlen , input wire [2:0] s4_axi_awsize , input wire [1:0] s4_axi_awburst , input wire [0:0] s4_axi_awlock , input wire [3:0] s4_axi_awcache , input wire [2:0] s4_axi_awprot , input wire [3:0] s4_axi_awqos , input wire s4_axi_awvalid , output wire s4_axi_awready , input wire [C_S4_AXI_DATA_WIDTH-1:0] s4_axi_wdata , input wire [C_S4_AXI_DATA_WIDTH/8-1:0] s4_axi_wstrb , input wire s4_axi_wlast , input wire s4_axi_wvalid , output wire s4_axi_wready , output wire [C_S4_AXI_ID_WIDTH-1:0] s4_axi_bid , output wire [1:0] s4_axi_bresp , output wire s4_axi_bvalid , input wire s4_axi_bready , input wire [C_S4_AXI_ID_WIDTH-1:0] s4_axi_arid , input wire [C_S4_AXI_ADDR_WIDTH-1:0] s4_axi_araddr , input wire [7:0] s4_axi_arlen , input wire [2:0] s4_axi_arsize , input wire [1:0] s4_axi_arburst , input wire [0:0] s4_axi_arlock , input wire [3:0] s4_axi_arcache , input wire [2:0] s4_axi_arprot , input wire [3:0] s4_axi_arqos , input wire s4_axi_arvalid , output wire s4_axi_arready , output wire [C_S4_AXI_ID_WIDTH-1:0] s4_axi_rid , output wire [C_S4_AXI_DATA_WIDTH-1:0] s4_axi_rdata , output wire [1:0] s4_axi_rresp , output wire s4_axi_rlast , output wire s4_axi_rvalid , input wire s4_axi_rready , input wire s5_axi_aclk , input wire s5_axi_aresetn , input wire [C_S5_AXI_ID_WIDTH-1:0] s5_axi_awid , input wire [C_S5_AXI_ADDR_WIDTH-1:0] s5_axi_awaddr , input wire [7:0] s5_axi_awlen , input wire [2:0] s5_axi_awsize , input wire [1:0] s5_axi_awburst , input wire [0:0] s5_axi_awlock , input wire [3:0] s5_axi_awcache , input wire [2:0] s5_axi_awprot , input wire [3:0] s5_axi_awqos , input wire s5_axi_awvalid , output wire s5_axi_awready , input wire [C_S5_AXI_DATA_WIDTH-1:0] s5_axi_wdata , input wire [C_S5_AXI_DATA_WIDTH/8-1:0] s5_axi_wstrb , input wire s5_axi_wlast , input wire s5_axi_wvalid , output wire s5_axi_wready , output wire [C_S5_AXI_ID_WIDTH-1:0] s5_axi_bid , output wire [1:0] s5_axi_bresp , output wire s5_axi_bvalid , input wire s5_axi_bready , input wire [C_S5_AXI_ID_WIDTH-1:0] s5_axi_arid , input wire [C_S5_AXI_ADDR_WIDTH-1:0] s5_axi_araddr , input wire [7:0] s5_axi_arlen , input wire [2:0] s5_axi_arsize , input wire [1:0] s5_axi_arburst , input wire [0:0] s5_axi_arlock , input wire [3:0] s5_axi_arcache , input wire [2:0] s5_axi_arprot , input wire [3:0] s5_axi_arqos , input wire s5_axi_arvalid , output wire s5_axi_arready , output wire [C_S5_AXI_ID_WIDTH-1:0] s5_axi_rid , output wire [C_S5_AXI_DATA_WIDTH-1:0] s5_axi_rdata , output wire [1:0] s5_axi_rresp , output wire s5_axi_rlast , output wire s5_axi_rvalid , input wire s5_axi_rready ); //////////////////////////////////////////////////////////////////////////////// // Functions //////////////////////////////////////////////////////////////////////////////// // Barrel Left Shift Octal function [17:0] blso ( input [17:0] a, input integer shift, input integer width ); begin : func_blso integer i; integer w; integer s; w = width*3; s = (shift*3) % w; blso = 18'o000000; for (i = 0; i < w; i = i + 1) begin blso[i] = a[(i+w-s)%w]; //bls[i] = 1'b1; end end endfunction // For a given port_config, port_enable and slot, calculate the round robin // arbitration that would be generated by the gui. function [17:0] rr ( input [5:0] port_enable, input integer port_config, input integer slot_num ); begin : func_rr integer i; integer max_ports; integer num_ports; integer port_cnt; case (port_config) 1: max_ports = 6; 2: max_ports = 4; 3: max_ports = 3; 4: max_ports = 2; 5: max_ports = 1; // synthesis translate_off default : $display("ERROR: Port Config can't be %d", port_config); // synthesis translate_on endcase num_ports = 0; for (i = 0; i < max_ports; i = i + 1) begin if (port_enable[i] == 1'b1) begin num_ports = num_ports + 1; end end rr = 18'o000000; port_cnt = 0; for (i = (num_ports-1); i >= 0; i = i - 1) begin while (port_enable[port_cnt] != 1'b1) begin port_cnt = port_cnt + 1; end rr[i*3 +: 3] = port_cnt[2:0]; port_cnt = port_cnt +1; end rr = blso(rr, slot_num, num_ports); end endfunction function [17:0] convert_arb_slot ( input [5:0] port_enable, input integer port_config, input [17:0] mig_arb_slot ); begin : func_convert_arb_slot integer i; integer num_ports; integer mig_port_num; reg [17:0] port_map; num_ports = 0; // Enumerated port configuration for ease of use case (port_config) 1: port_map = 18'o543210; 2: port_map = 18'o774210; 3: port_map = 18'o777420; 4: port_map = 18'o777720; 5: port_map = 18'o777770; // synthesis translate_off default : $display ("ERROR: Invalid Port Configuration."); // synthesis translate_on endcase // Count the number of ports for (i = 0; i < 6; i = i + 1) begin if (port_enable[i] == 1'b1) begin num_ports = num_ports + 1; end end // Map the ports from the MIG GUI to the MCB Wrapper for (i = 0; i < 6; i = i + 1) begin if (i < num_ports) begin mig_port_num = mig_arb_slot[3*(num_ports-i-1) +: 3]; convert_arb_slot[3*i +: 3] = port_map[3*mig_port_num +: 3]; end else begin convert_arb_slot[3*i +: 3] = 3'b111; end end end endfunction // Function to calculate the number of time slots automatically based on the // number of ports used. Will choose 10 if the number of valid ports is 5, // otherwise it will be 12. function integer calc_num_time_slots ( input [5:0] port_enable, input integer port_config ); begin : func_calc_num_tim_slots integer num_ports; integer i; num_ports = 0; for (i = 0; i < 6; i = i + 1) begin if (port_enable[i] == 1'b1) begin num_ports = num_ports + 1; end end calc_num_time_slots = (port_config == 1 && num_ports == 5) ? 10 : 12; end endfunction //////////////////////////////////////////////////////////////////////////////// // Local Parameters //////////////////////////////////////////////////////////////////////////////// localparam P_S0_AXI_ADDRMASK = C_S0_AXI_BASEADDR ^ C_S0_AXI_HIGHADDR; localparam P_S1_AXI_ADDRMASK = C_S1_AXI_BASEADDR ^ C_S1_AXI_HIGHADDR; localparam P_S2_AXI_ADDRMASK = C_S2_AXI_BASEADDR ^ C_S2_AXI_HIGHADDR; localparam P_S3_AXI_ADDRMASK = C_S3_AXI_BASEADDR ^ C_S3_AXI_HIGHADDR; localparam P_S4_AXI_ADDRMASK = C_S4_AXI_BASEADDR ^ C_S4_AXI_HIGHADDR; localparam P_S5_AXI_ADDRMASK = C_S5_AXI_BASEADDR ^ C_S5_AXI_HIGHADDR; localparam P_PORT_CONFIG = (C_PORT_CONFIG == "B32_B32_B32_B32") ? 2 : (C_PORT_CONFIG == "B64_B32_B32" ) ? 3 : (C_PORT_CONFIG == "B64_B64" ) ? 4 : (C_PORT_CONFIG == "B128" ) ? 5 : 1; // B32_B32_x32_x32_x32_x32 case localparam P_ARB_NUM_TIME_SLOTS = (C_ARB_ALGORITHM == 0) ? calc_num_time_slots(C_PORT_ENABLE, P_PORT_CONFIG) : C_ARB_NUM_TIME_SLOTS; localparam P_0_ARB_TIME_SLOT_0 = (C_ARB_ALGORITHM == 0) ? rr(C_PORT_ENABLE, P_PORT_CONFIG, 0 ) : C_ARB_TIME_SLOT_0 ; localparam P_0_ARB_TIME_SLOT_1 = (C_ARB_ALGORITHM == 0) ? rr(C_PORT_ENABLE, P_PORT_CONFIG, 1 ) : C_ARB_TIME_SLOT_1 ; localparam P_0_ARB_TIME_SLOT_2 = (C_ARB_ALGORITHM == 0) ? rr(C_PORT_ENABLE, P_PORT_CONFIG, 2 ) : C_ARB_TIME_SLOT_2 ; localparam P_0_ARB_TIME_SLOT_3 = (C_ARB_ALGORITHM == 0) ? rr(C_PORT_ENABLE, P_PORT_CONFIG, 3 ) : C_ARB_TIME_SLOT_3 ; localparam P_0_ARB_TIME_SLOT_4 = (C_ARB_ALGORITHM == 0) ? rr(C_PORT_ENABLE, P_PORT_CONFIG, 4 ) : C_ARB_TIME_SLOT_4 ; localparam P_0_ARB_TIME_SLOT_5 = (C_ARB_ALGORITHM == 0) ? rr(C_PORT_ENABLE, P_PORT_CONFIG, 5 ) : C_ARB_TIME_SLOT_5 ; localparam P_0_ARB_TIME_SLOT_6 = (C_ARB_ALGORITHM == 0) ? rr(C_PORT_ENABLE, P_PORT_CONFIG, 6 ) : C_ARB_TIME_SLOT_6 ; localparam P_0_ARB_TIME_SLOT_7 = (C_ARB_ALGORITHM == 0) ? rr(C_PORT_ENABLE, P_PORT_CONFIG, 7 ) : C_ARB_TIME_SLOT_7 ; localparam P_0_ARB_TIME_SLOT_8 = (C_ARB_ALGORITHM == 0) ? rr(C_PORT_ENABLE, P_PORT_CONFIG, 8 ) : C_ARB_TIME_SLOT_8 ; localparam P_0_ARB_TIME_SLOT_9 = (C_ARB_ALGORITHM == 0) ? rr(C_PORT_ENABLE, P_PORT_CONFIG, 9 ) : C_ARB_TIME_SLOT_9 ; localparam P_0_ARB_TIME_SLOT_10 = (C_ARB_ALGORITHM == 0) ? rr(C_PORT_ENABLE, P_PORT_CONFIG, 10) : C_ARB_TIME_SLOT_10; localparam P_0_ARB_TIME_SLOT_11 = (C_ARB_ALGORITHM == 0) ? rr(C_PORT_ENABLE, P_PORT_CONFIG, 11) : C_ARB_TIME_SLOT_11; localparam P_ARB_TIME_SLOT_0 = convert_arb_slot(C_PORT_ENABLE, P_PORT_CONFIG, P_0_ARB_TIME_SLOT_0); localparam P_ARB_TIME_SLOT_1 = convert_arb_slot(C_PORT_ENABLE, P_PORT_CONFIG, P_0_ARB_TIME_SLOT_1); localparam P_ARB_TIME_SLOT_2 = convert_arb_slot(C_PORT_ENABLE, P_PORT_CONFIG, P_0_ARB_TIME_SLOT_2); localparam P_ARB_TIME_SLOT_3 = convert_arb_slot(C_PORT_ENABLE, P_PORT_CONFIG, P_0_ARB_TIME_SLOT_3); localparam P_ARB_TIME_SLOT_4 = convert_arb_slot(C_PORT_ENABLE, P_PORT_CONFIG, P_0_ARB_TIME_SLOT_4); localparam P_ARB_TIME_SLOT_5 = convert_arb_slot(C_PORT_ENABLE, P_PORT_CONFIG, P_0_ARB_TIME_SLOT_5); localparam P_ARB_TIME_SLOT_6 = convert_arb_slot(C_PORT_ENABLE, P_PORT_CONFIG, P_0_ARB_TIME_SLOT_6); localparam P_ARB_TIME_SLOT_7 = convert_arb_slot(C_PORT_ENABLE, P_PORT_CONFIG, P_0_ARB_TIME_SLOT_7); localparam P_ARB_TIME_SLOT_8 = convert_arb_slot(C_PORT_ENABLE, P_PORT_CONFIG, P_0_ARB_TIME_SLOT_8); localparam P_ARB_TIME_SLOT_9 = convert_arb_slot(C_PORT_ENABLE, P_PORT_CONFIG, P_0_ARB_TIME_SLOT_9); localparam P_ARB_TIME_SLOT_10 = convert_arb_slot(C_PORT_ENABLE, P_PORT_CONFIG, P_0_ARB_TIME_SLOT_10); localparam P_ARB_TIME_SLOT_11 = convert_arb_slot(C_PORT_ENABLE, P_PORT_CONFIG, P_0_ARB_TIME_SLOT_11); //////////////////////////////////////////////////////////////////////////////// // Wires/Reg declarations //////////////////////////////////////////////////////////////////////////////// wire [C_S0_AXI_ADDR_WIDTH-1:0] s0_axi_araddr_i; wire [C_S0_AXI_ADDR_WIDTH-1:0] s0_axi_awaddr_i; wire p0_arb_en_i; wire p0_cmd_clk_i; wire p0_cmd_en_i; wire [2:0] p0_cmd_instr_i; wire [5:0] p0_cmd_bl_i; wire [29:0] p0_cmd_byte_addr_i; wire p0_cmd_empty_i; wire p0_cmd_full_i; wire p0_wr_clk_i; wire p0_wr_en_i; wire [C_P0_MASK_SIZE-1:0] p0_wr_mask_i; wire [C_P0_DATA_PORT_SIZE-1:0] p0_wr_data_i; wire p0_wr_full_i; wire p0_wr_empty_i; wire [6:0] p0_wr_count_i; wire p0_wr_underrun_i; wire p0_wr_error_i; wire p0_rd_clk_i; wire p0_rd_en_i; wire [C_P0_DATA_PORT_SIZE-1:0] p0_rd_data_i; wire p0_rd_full_i; wire p0_rd_empty_i; wire [6:0] p0_rd_count_i; wire p0_rd_overflow_i; wire p0_rd_error_i; wire [C_S1_AXI_ADDR_WIDTH-1:0] s1_axi_araddr_i; wire [C_S1_AXI_ADDR_WIDTH-1:0] s1_axi_awaddr_i; wire p1_arb_en_i; wire p1_cmd_clk_i; wire p1_cmd_en_i; wire [2:0] p1_cmd_instr_i; wire [5:0] p1_cmd_bl_i; wire [29:0] p1_cmd_byte_addr_i; wire p1_cmd_empty_i; wire p1_cmd_full_i; wire p1_wr_clk_i; wire p1_wr_en_i; wire [C_P1_MASK_SIZE-1:0] p1_wr_mask_i; wire [C_P1_DATA_PORT_SIZE-1:0] p1_wr_data_i; wire p1_wr_full_i; wire p1_wr_empty_i; wire [6:0] p1_wr_count_i; wire p1_wr_underrun_i; wire p1_wr_error_i; wire p1_rd_clk_i; wire p1_rd_en_i; wire [C_P1_DATA_PORT_SIZE-1:0] p1_rd_data_i; wire p1_rd_full_i; wire p1_rd_empty_i; wire [6:0] p1_rd_count_i; wire p1_rd_overflow_i; wire p1_rd_error_i; wire [C_S2_AXI_ADDR_WIDTH-1:0] s2_axi_araddr_i; wire [C_S2_AXI_ADDR_WIDTH-1:0] s2_axi_awaddr_i; wire p2_arb_en_i; wire p2_cmd_clk_i; wire p2_cmd_en_i; wire [2:0] p2_cmd_instr_i; wire [5:0] p2_cmd_bl_i; wire [29:0] p2_cmd_byte_addr_i; wire p2_cmd_empty_i; wire p2_cmd_full_i; wire p2_wr_clk_i; wire p2_wr_en_i; wire [3:0] p2_wr_mask_i; wire [31:0] p2_wr_data_i; wire p2_wr_full_i; wire p2_wr_empty_i; wire [6:0] p2_wr_count_i; wire p2_wr_underrun_i; wire p2_wr_error_i; wire p2_rd_clk_i; wire p2_rd_en_i; wire [31:0] p2_rd_data_i; wire p2_rd_full_i; wire p2_rd_empty_i; wire [6:0] p2_rd_count_i; wire p2_rd_overflow_i; wire p2_rd_error_i; wire [C_S3_AXI_ADDR_WIDTH-1:0] s3_axi_araddr_i; wire [C_S3_AXI_ADDR_WIDTH-1:0] s3_axi_awaddr_i; wire p3_arb_en_i; wire p3_cmd_clk_i; wire p3_cmd_en_i; wire [2:0] p3_cmd_instr_i; wire [5:0] p3_cmd_bl_i; wire [29:0] p3_cmd_byte_addr_i; wire p3_cmd_empty_i; wire p3_cmd_full_i; wire p3_wr_clk_i; wire p3_wr_en_i; wire [3:0] p3_wr_mask_i; wire [31:0] p3_wr_data_i; wire p3_wr_full_i; wire p3_wr_empty_i; wire [6:0] p3_wr_count_i; wire p3_wr_underrun_i; wire p3_wr_error_i; wire p3_rd_clk_i; wire p3_rd_en_i; wire [31:0] p3_rd_data_i; wire p3_rd_full_i; wire p3_rd_empty_i; wire [6:0] p3_rd_count_i; wire p3_rd_overflow_i; wire p3_rd_error_i; wire [C_S4_AXI_ADDR_WIDTH-1:0] s4_axi_araddr_i; wire [C_S4_AXI_ADDR_WIDTH-1:0] s4_axi_awaddr_i; wire p4_arb_en_i; wire p4_cmd_clk_i; wire p4_cmd_en_i; wire [2:0] p4_cmd_instr_i; wire [5:0] p4_cmd_bl_i; wire [29:0] p4_cmd_byte_addr_i; wire p4_cmd_empty_i; wire p4_cmd_full_i; wire p4_wr_clk_i; wire p4_wr_en_i; wire [3:0] p4_wr_mask_i; wire [31:0] p4_wr_data_i; wire p4_wr_full_i; wire p4_wr_empty_i; wire [6:0] p4_wr_count_i; wire p4_wr_underrun_i; wire p4_wr_error_i; wire p4_rd_clk_i; wire p4_rd_en_i; wire [31:0] p4_rd_data_i; wire p4_rd_full_i; wire p4_rd_empty_i; wire [6:0] p4_rd_count_i; wire p4_rd_overflow_i; wire p4_rd_error_i; wire [C_S5_AXI_ADDR_WIDTH-1:0] s5_axi_araddr_i; wire [C_S5_AXI_ADDR_WIDTH-1:0] s5_axi_awaddr_i; wire p5_arb_en_i; wire p5_cmd_clk_i; wire p5_cmd_en_i; wire [2:0] p5_cmd_instr_i; wire [5:0] p5_cmd_bl_i; wire [29:0] p5_cmd_byte_addr_i; wire p5_cmd_empty_i; wire p5_cmd_full_i; wire p5_wr_clk_i; wire p5_wr_en_i; wire [3:0] p5_wr_mask_i; wire [31:0] p5_wr_data_i; wire p5_wr_full_i; wire p5_wr_empty_i; wire [6:0] p5_wr_count_i; wire p5_wr_underrun_i; wire p5_wr_error_i; wire p5_rd_clk_i; wire p5_rd_en_i; wire [31:0] p5_rd_data_i; wire p5_rd_full_i; wire p5_rd_empty_i; wire [6:0] p5_rd_count_i; wire p5_rd_overflow_i; wire p5_rd_error_i; wire ioclk0; wire ioclk180; wire pll_ce_0_i; wire pll_ce_90_i; generate if (C_MCB_USE_EXTERNAL_BUFPLL == 0) begin : gen_spartan6_bufpll_mcb // Instantiate the PLL for MCB. BUFPLL_MCB # ( .DIVIDE (2), .LOCK_SRC ("LOCK_TO_0") ) bufpll_0 ( .IOCLK0 (ioclk0), .IOCLK1 (ioclk180), .GCLK (ui_clk), .LOCKED (pll_lock), .LOCK (pll_lock_bufpll_o), .SERDESSTROBE0(pll_ce_0_i), .SERDESSTROBE1(pll_ce_90_i), .PLLIN0 (sysclk_2x), .PLLIN1 (sysclk_2x_180) ); end else begin : gen_spartan6_no_bufpll_mcb // Use external bufpll_mcb. assign pll_ce_0_i = pll_ce_0; assign pll_ce_90_i = pll_ce_90; assign ioclk0 = sysclk_2x; assign ioclk180 = sysclk_2x_180; assign pll_lock_bufpll_o = pll_lock; end endgenerate assign sysclk_2x_bufpll_o = ioclk0; assign sysclk_2x_180_bufpll_o = ioclk180; assign pll_ce_0_bufpll_o = pll_ce_0_i; assign pll_ce_90_bufpll_o = pll_ce_90_i; mcb_raw_wrapper # ( .C_MEMCLK_PERIOD ( C_MEMCLK_PERIOD ), .C_PORT_ENABLE ( C_PORT_ENABLE ), .C_MEM_ADDR_ORDER ( C_MEM_ADDR_ORDER ), .C_ARB_NUM_TIME_SLOTS ( P_ARB_NUM_TIME_SLOTS ), .C_ARB_TIME_SLOT_0 ( P_ARB_TIME_SLOT_0 ), .C_ARB_TIME_SLOT_1 ( P_ARB_TIME_SLOT_1 ), .C_ARB_TIME_SLOT_2 ( P_ARB_TIME_SLOT_2 ), .C_ARB_TIME_SLOT_3 ( P_ARB_TIME_SLOT_3 ), .C_ARB_TIME_SLOT_4 ( P_ARB_TIME_SLOT_4 ), .C_ARB_TIME_SLOT_5 ( P_ARB_TIME_SLOT_5 ), .C_ARB_TIME_SLOT_6 ( P_ARB_TIME_SLOT_6 ), .C_ARB_TIME_SLOT_7 ( P_ARB_TIME_SLOT_7 ), .C_ARB_TIME_SLOT_8 ( P_ARB_TIME_SLOT_8 ), .C_ARB_TIME_SLOT_9 ( P_ARB_TIME_SLOT_9 ), .C_ARB_TIME_SLOT_10 ( P_ARB_TIME_SLOT_10 ), .C_ARB_TIME_SLOT_11 ( P_ARB_TIME_SLOT_11 ), .C_PORT_CONFIG ( C_PORT_CONFIG ), .C_MEM_TRAS ( C_MEM_TRAS ), .C_MEM_TRCD ( C_MEM_TRCD ), .C_MEM_TREFI ( C_MEM_TREFI ), .C_MEM_TRFC ( C_MEM_TRFC ), .C_MEM_TRP ( C_MEM_TRP ), .C_MEM_TWR ( C_MEM_TWR ), .C_MEM_TRTP ( C_MEM_TRTP ), .C_MEM_TWTR ( C_MEM_TWTR ), .C_NUM_DQ_PINS ( C_NUM_DQ_PINS ), .C_MEM_TYPE ( C_MEM_TYPE ), .C_MEM_DENSITY ( C_MEM_DENSITY ), .C_MEM_BURST_LEN ( C_MEM_BURST_LEN ), .C_MEM_CAS_LATENCY ( C_MEM_CAS_LATENCY ), .C_MEM_ADDR_WIDTH ( C_MEM_ADDR_WIDTH ), .C_MEM_BANKADDR_WIDTH ( C_MEM_BANKADDR_WIDTH ), .C_MEM_NUM_COL_BITS ( C_MEM_NUM_COL_BITS ), .C_MEM_DDR3_CAS_LATENCY ( C_MEM_DDR3_CAS_LATENCY ), .C_MEM_MOBILE_PA_SR ( C_MEM_MOBILE_PA_SR ), .C_MEM_DDR1_2_ODS ( C_MEM_DDR1_2_ODS ), .C_MEM_DDR3_ODS ( C_MEM_DDR3_ODS ), .C_MEM_DDR2_RTT ( C_MEM_DDR2_RTT ), .C_MEM_DDR3_RTT ( C_MEM_DDR3_RTT ), .C_MEM_MDDR_ODS ( C_MEM_MDDR_ODS ), .C_MEM_DDR2_DIFF_DQS_EN ( C_MEM_DDR2_DIFF_DQS_EN ), .C_MEM_DDR2_3_PA_SR ( C_MEM_DDR2_3_PA_SR ), .C_MEM_DDR3_CAS_WR_LATENCY ( C_MEM_DDR3_CAS_WR_LATENCY ), .C_MEM_DDR3_AUTO_SR ( C_MEM_DDR3_AUTO_SR ), .C_MEM_DDR2_3_HIGH_TEMP_SR ( C_MEM_DDR2_3_HIGH_TEMP_SR ), .C_MEM_DDR3_DYN_WRT_ODT ( C_MEM_DDR3_DYN_WRT_ODT ), // Subtract 16 to stop TRFC violations. .C_MEM_TZQINIT_MAXCNT ( C_MEM_TZQINIT_MAXCNT - 16 ), .C_MC_CALIB_BYPASS ( C_MC_CALIB_BYPASS ), .C_MC_CALIBRATION_RA ( C_MC_CALIBRATION_RA ), .C_MC_CALIBRATION_BA ( C_MC_CALIBRATION_BA ), .C_CALIB_SOFT_IP ( C_CALIB_SOFT_IP ), .C_SKIP_IN_TERM_CAL ( C_SKIP_IN_TERM_CAL ), .C_SKIP_DYNAMIC_CAL ( C_SKIP_DYNAMIC_CAL ), .C_SKIP_DYN_IN_TERM ( C_SKIP_DYN_IN_TERM ), .LDQSP_TAP_DELAY_VAL ( LDQSP_TAP_DELAY_VAL ), .UDQSP_TAP_DELAY_VAL ( UDQSP_TAP_DELAY_VAL ), .LDQSN_TAP_DELAY_VAL ( LDQSN_TAP_DELAY_VAL ), .UDQSN_TAP_DELAY_VAL ( UDQSN_TAP_DELAY_VAL ), .DQ0_TAP_DELAY_VAL ( DQ0_TAP_DELAY_VAL ), .DQ1_TAP_DELAY_VAL ( DQ1_TAP_DELAY_VAL ), .DQ2_TAP_DELAY_VAL ( DQ2_TAP_DELAY_VAL ), .DQ3_TAP_DELAY_VAL ( DQ3_TAP_DELAY_VAL ), .DQ4_TAP_DELAY_VAL ( DQ4_TAP_DELAY_VAL ), .DQ5_TAP_DELAY_VAL ( DQ5_TAP_DELAY_VAL ), .DQ6_TAP_DELAY_VAL ( DQ6_TAP_DELAY_VAL ), .DQ7_TAP_DELAY_VAL ( DQ7_TAP_DELAY_VAL ), .DQ8_TAP_DELAY_VAL ( DQ8_TAP_DELAY_VAL ), .DQ9_TAP_DELAY_VAL ( DQ9_TAP_DELAY_VAL ), .DQ10_TAP_DELAY_VAL ( DQ10_TAP_DELAY_VAL ), .DQ11_TAP_DELAY_VAL ( DQ11_TAP_DELAY_VAL ), .DQ12_TAP_DELAY_VAL ( DQ12_TAP_DELAY_VAL ), .DQ13_TAP_DELAY_VAL ( DQ13_TAP_DELAY_VAL ), .DQ14_TAP_DELAY_VAL ( DQ14_TAP_DELAY_VAL ), .DQ15_TAP_DELAY_VAL ( DQ15_TAP_DELAY_VAL ), .C_MC_CALIBRATION_CA ( C_MC_CALIBRATION_CA ), .C_MC_CALIBRATION_CLK_DIV ( C_MC_CALIBRATION_CLK_DIV ), .C_MC_CALIBRATION_MODE ( C_MC_CALIBRATION_MODE ), .C_MC_CALIBRATION_DELAY ( C_MC_CALIBRATION_DELAY ), // synthesis translate_off .C_SIMULATION ( C_SIMULATION ), // synthesis translate_on .C_P0_MASK_SIZE ( C_P0_MASK_SIZE ), .C_P0_DATA_PORT_SIZE ( C_P0_DATA_PORT_SIZE ), .C_P1_MASK_SIZE ( C_P1_MASK_SIZE ), .C_P1_DATA_PORT_SIZE ( C_P1_DATA_PORT_SIZE ) ) mcb_raw_wrapper_inst ( .sysclk_2x ( ioclk0 ), .sysclk_2x_180 ( ioclk180 ), .pll_ce_0 ( pll_ce_0_i ), .pll_ce_90 ( pll_ce_90_i ), .pll_lock ( pll_lock_bufpll_o ), .sys_rst ( sys_rst ), .p0_arb_en ( p0_arb_en_i ), .p0_cmd_clk ( p0_cmd_clk_i ), .p0_cmd_en ( p0_cmd_en_i ), .p0_cmd_instr ( p0_cmd_instr_i ), .p0_cmd_bl ( p0_cmd_bl_i ), .p0_cmd_byte_addr ( p0_cmd_byte_addr_i ), .p0_cmd_empty ( p0_cmd_empty_i ), .p0_cmd_full ( p0_cmd_full_i ), .p0_wr_clk ( p0_wr_clk_i ), .p0_wr_en ( p0_wr_en_i ), .p0_wr_mask ( p0_wr_mask_i ), .p0_wr_data ( p0_wr_data_i ), .p0_wr_full ( p0_wr_full_i ), .p0_wr_empty ( p0_wr_empty_i ), .p0_wr_count ( p0_wr_count_i ), .p0_wr_underrun ( p0_wr_underrun_i ), .p0_wr_error ( p0_wr_error_i ), .p0_rd_clk ( p0_rd_clk_i ), .p0_rd_en ( p0_rd_en_i ), .p0_rd_data ( p0_rd_data_i ), .p0_rd_full ( p0_rd_full_i ), .p0_rd_empty ( p0_rd_empty_i ), .p0_rd_count ( p0_rd_count_i ), .p0_rd_overflow ( p0_rd_overflow_i ), .p0_rd_error ( p0_rd_error_i ), .p1_arb_en ( p1_arb_en_i ), .p1_cmd_clk ( p1_cmd_clk_i ), .p1_cmd_en ( p1_cmd_en_i ), .p1_cmd_instr ( p1_cmd_instr_i ), .p1_cmd_bl ( p1_cmd_bl_i ), .p1_cmd_byte_addr ( p1_cmd_byte_addr_i ), .p1_cmd_empty ( p1_cmd_empty_i ), .p1_cmd_full ( p1_cmd_full_i ), .p1_wr_clk ( p1_wr_clk_i ), .p1_wr_en ( p1_wr_en_i ), .p1_wr_mask ( p1_wr_mask_i ), .p1_wr_data ( p1_wr_data_i ), .p1_wr_full ( p1_wr_full_i ), .p1_wr_empty ( p1_wr_empty_i ), .p1_wr_count ( p1_wr_count_i ), .p1_wr_underrun ( p1_wr_underrun_i ), .p1_wr_error ( p1_wr_error_i ), .p1_rd_clk ( p1_rd_clk_i ), .p1_rd_en ( p1_rd_en_i ), .p1_rd_data ( p1_rd_data_i ), .p1_rd_full ( p1_rd_full_i ), .p1_rd_empty ( p1_rd_empty_i ), .p1_rd_count ( p1_rd_count_i ), .p1_rd_overflow ( p1_rd_overflow_i ), .p1_rd_error ( p1_rd_error_i ), .p2_arb_en ( p2_arb_en_i ), .p2_cmd_clk ( p2_cmd_clk_i ), .p2_cmd_en ( p2_cmd_en_i ), .p2_cmd_instr ( p2_cmd_instr_i ), .p2_cmd_bl ( p2_cmd_bl_i ), .p2_cmd_byte_addr ( p2_cmd_byte_addr_i ), .p2_cmd_empty ( p2_cmd_empty_i ), .p2_cmd_full ( p2_cmd_full_i ), .p2_wr_clk ( p2_wr_clk_i ), .p2_wr_en ( p2_wr_en_i ), .p2_wr_mask ( p2_wr_mask_i ), .p2_wr_data ( p2_wr_data_i ), .p2_wr_full ( p2_wr_full_i ), .p2_wr_empty ( p2_wr_empty_i ), .p2_wr_count ( p2_wr_count_i ), .p2_wr_underrun ( p2_wr_underrun_i ), .p2_wr_error ( p2_wr_error_i ), .p2_rd_clk ( p2_rd_clk_i ), .p2_rd_en ( p2_rd_en_i ), .p2_rd_data ( p2_rd_data_i ), .p2_rd_full ( p2_rd_full_i ), .p2_rd_empty ( p2_rd_empty_i ), .p2_rd_count ( p2_rd_count_i ), .p2_rd_overflow ( p2_rd_overflow_i ), .p2_rd_error ( p2_rd_error_i ), .p3_arb_en ( p3_arb_en_i ), .p3_cmd_clk ( p3_cmd_clk_i ), .p3_cmd_en ( p3_cmd_en_i ), .p3_cmd_instr ( p3_cmd_instr_i ), .p3_cmd_bl ( p3_cmd_bl_i ), .p3_cmd_byte_addr ( p3_cmd_byte_addr_i ), .p3_cmd_empty ( p3_cmd_empty_i ), .p3_cmd_full ( p3_cmd_full_i ), .p3_wr_clk ( p3_wr_clk_i ), .p3_wr_en ( p3_wr_en_i ), .p3_wr_mask ( p3_wr_mask_i ), .p3_wr_data ( p3_wr_data_i ), .p3_wr_full ( p3_wr_full_i ), .p3_wr_empty ( p3_wr_empty_i ), .p3_wr_count ( p3_wr_count_i ), .p3_wr_underrun ( p3_wr_underrun_i ), .p3_wr_error ( p3_wr_error_i ), .p3_rd_clk ( p3_rd_clk_i ), .p3_rd_en ( p3_rd_en_i ), .p3_rd_data ( p3_rd_data_i ), .p3_rd_full ( p3_rd_full_i ), .p3_rd_empty ( p3_rd_empty_i ), .p3_rd_count ( p3_rd_count_i ), .p3_rd_overflow ( p3_rd_overflow_i ), .p3_rd_error ( p3_rd_error_i ), .p4_arb_en ( p4_arb_en_i ), .p4_cmd_clk ( p4_cmd_clk_i ), .p4_cmd_en ( p4_cmd_en_i ), .p4_cmd_instr ( p4_cmd_instr_i ), .p4_cmd_bl ( p4_cmd_bl_i ), .p4_cmd_byte_addr ( p4_cmd_byte_addr_i ), .p4_cmd_empty ( p4_cmd_empty_i ), .p4_cmd_full ( p4_cmd_full_i ), .p4_wr_clk ( p4_wr_clk_i ), .p4_wr_en ( p4_wr_en_i ), .p4_wr_mask ( p4_wr_mask_i ), .p4_wr_data ( p4_wr_data_i ), .p4_wr_full ( p4_wr_full_i ), .p4_wr_empty ( p4_wr_empty_i ), .p4_wr_count ( p4_wr_count_i ), .p4_wr_underrun ( p4_wr_underrun_i ), .p4_wr_error ( p4_wr_error_i ), .p4_rd_clk ( p4_rd_clk_i ), .p4_rd_en ( p4_rd_en_i ), .p4_rd_data ( p4_rd_data_i ), .p4_rd_full ( p4_rd_full_i ), .p4_rd_empty ( p4_rd_empty_i ), .p4_rd_count ( p4_rd_count_i ), .p4_rd_overflow ( p4_rd_overflow_i ), .p4_rd_error ( p4_rd_error_i ), .p5_arb_en ( p5_arb_en_i ), .p5_cmd_clk ( p5_cmd_clk_i ), .p5_cmd_en ( p5_cmd_en_i ), .p5_cmd_instr ( p5_cmd_instr_i ), .p5_cmd_bl ( p5_cmd_bl_i ), .p5_cmd_byte_addr ( p5_cmd_byte_addr_i ), .p5_cmd_empty ( p5_cmd_empty_i ), .p5_cmd_full ( p5_cmd_full_i ), .p5_wr_clk ( p5_wr_clk_i ), .p5_wr_en ( p5_wr_en_i ), .p5_wr_mask ( p5_wr_mask_i ), .p5_wr_data ( p5_wr_data_i ), .p5_wr_full ( p5_wr_full_i ), .p5_wr_empty ( p5_wr_empty_i ), .p5_wr_count ( p5_wr_count_i ), .p5_wr_underrun ( p5_wr_underrun_i ), .p5_wr_error ( p5_wr_error_i ), .p5_rd_clk ( p5_rd_clk_i ), .p5_rd_en ( p5_rd_en_i ), .p5_rd_data ( p5_rd_data_i ), .p5_rd_full ( p5_rd_full_i ), .p5_rd_empty ( p5_rd_empty_i ), .p5_rd_count ( p5_rd_count_i ), .p5_rd_overflow ( p5_rd_overflow_i ), .p5_rd_error ( p5_rd_error_i ), .mcbx_dram_addr ( mcbx_dram_addr ), .mcbx_dram_ba ( mcbx_dram_ba ), .mcbx_dram_ras_n ( mcbx_dram_ras_n ), .mcbx_dram_cas_n ( mcbx_dram_cas_n ), .mcbx_dram_we_n ( mcbx_dram_we_n ), .mcbx_dram_cke ( mcbx_dram_cke ), .mcbx_dram_clk ( mcbx_dram_clk ), .mcbx_dram_clk_n ( mcbx_dram_clk_n ), .mcbx_dram_dq ( mcbx_dram_dq ), .mcbx_dram_dqs ( mcbx_dram_dqs ), .mcbx_dram_dqs_n ( mcbx_dram_dqs_n ), .mcbx_dram_udqs ( mcbx_dram_udqs ), .mcbx_dram_udqs_n ( mcbx_dram_udqs_n ), .mcbx_dram_udm ( mcbx_dram_udm ), .mcbx_dram_ldm ( mcbx_dram_ldm ), .mcbx_dram_odt ( mcbx_dram_odt ), .mcbx_dram_ddr3_rst ( mcbx_dram_ddr3_rst ), .calib_recal ( calib_recal ), .rzq ( rzq ), .zio ( zio ), .ui_read ( ui_read ), .ui_add ( ui_add ), .ui_cs ( ui_cs ), .ui_clk ( ui_clk ), .ui_sdi ( ui_sdi ), .ui_addr ( ui_addr ), .ui_broadcast ( ui_broadcast ), .ui_drp_update ( ui_drp_update ), .ui_done_cal ( ui_done_cal ), .ui_cmd ( ui_cmd ), .ui_cmd_in ( ui_cmd_in ), .ui_cmd_en ( ui_cmd_en ), .ui_dqcount ( ui_dqcount ), .ui_dq_lower_dec ( ui_dq_lower_dec ), .ui_dq_lower_inc ( ui_dq_lower_inc ), .ui_dq_upper_dec ( ui_dq_upper_dec ), .ui_dq_upper_inc ( ui_dq_upper_inc ), .ui_udqs_inc ( ui_udqs_inc ), .ui_udqs_dec ( ui_udqs_dec ), .ui_ldqs_inc ( ui_ldqs_inc ), .ui_ldqs_dec ( ui_ldqs_dec ), .uo_data ( uo_data ), .uo_data_valid ( uo_data_valid ), .uo_done_cal ( uo_done_cal ), .uo_cmd_ready_in ( uo_cmd_ready_in ), .uo_refrsh_flag ( uo_refrsh_flag ), .uo_cal_start ( uo_cal_start ), .uo_sdo ( uo_sdo ), .status ( status ), .selfrefresh_enter ( selfrefresh_enter ), .selfrefresh_mode ( selfrefresh_mode ) ); // P0 AXI Bridge Mux generate if (C_S0_AXI_ENABLE == 0) begin : P0_UI_MCB assign p0_arb_en_i = p0_arb_en ; // assign p0_cmd_clk_i = p0_cmd_clk ; // assign p0_cmd_en_i = p0_cmd_en ; // assign p0_cmd_instr_i = p0_cmd_instr ; // [2:0] assign p0_cmd_bl_i = p0_cmd_bl ; // [5:0] assign p0_cmd_byte_addr_i = p0_cmd_byte_addr ; // [29:0] assign p0_cmd_empty = p0_cmd_empty_i ; // assign p0_cmd_full = p0_cmd_full_i ; // assign p0_wr_clk_i = p0_wr_clk ; // assign p0_wr_en_i = p0_wr_en ; // assign p0_wr_mask_i = p0_wr_mask ; // [C_P0_MASK_SIZE-1:0] assign p0_wr_data_i = p0_wr_data ; // [C_P0_DATA_PORT_SIZE-1:0] assign p0_wr_full = p0_wr_full_i ; // assign p0_wr_empty = p0_wr_empty_i ; // assign p0_wr_count = p0_wr_count_i ; // [6:0] assign p0_wr_underrun = p0_wr_underrun_i ; // assign p0_wr_error = p0_wr_error_i ; // assign p0_rd_clk_i = p0_rd_clk ; // assign p0_rd_en_i = p0_rd_en ; // assign p0_rd_data = p0_rd_data_i ; // [C_P0_DATA_PORT_SIZE-1:0] assign p0_rd_full = p0_rd_full_i ; // assign p0_rd_empty = p0_rd_empty_i ; // assign p0_rd_count = p0_rd_count_i ; // [6:0] assign p0_rd_overflow = p0_rd_overflow_i ; // assign p0_rd_error = p0_rd_error_i ; // end else begin : P0_UI_AXI assign p0_arb_en_i = p0_arb_en; assign s0_axi_araddr_i = s0_axi_araddr & P_S0_AXI_ADDRMASK; assign s0_axi_awaddr_i = s0_axi_awaddr & P_S0_AXI_ADDRMASK; wire calib_done_synch; mcb_ui_top_synch #( .C_SYNCH_WIDTH ( 1 ) ) axi_mcb_synch ( .clk ( s0_axi_aclk ) , .synch_in ( uo_done_cal ) , .synch_out ( calib_done_synch ) ); axi_mcb # ( .C_FAMILY ( "spartan6" ) , .C_S_AXI_ID_WIDTH ( C_S0_AXI_ID_WIDTH ) , .C_S_AXI_ADDR_WIDTH ( C_S0_AXI_ADDR_WIDTH ) , .C_S_AXI_DATA_WIDTH ( C_S0_AXI_DATA_WIDTH ) , .C_S_AXI_SUPPORTS_READ ( C_S0_AXI_SUPPORTS_READ ) , .C_S_AXI_SUPPORTS_WRITE ( C_S0_AXI_SUPPORTS_WRITE ) , .C_S_AXI_REG_EN0 ( C_S0_AXI_REG_EN0 ) , .C_S_AXI_REG_EN1 ( C_S0_AXI_REG_EN1 ) , .C_S_AXI_SUPPORTS_NARROW_BURST ( C_S0_AXI_SUPPORTS_NARROW_BURST ) , .C_MCB_ADDR_WIDTH ( 30 ) , .C_MCB_DATA_WIDTH ( C_P0_DATA_PORT_SIZE ) , .C_STRICT_COHERENCY ( C_S0_AXI_STRICT_COHERENCY ) , .C_ENABLE_AP ( C_S0_AXI_ENABLE_AP ) ) p0_axi_mcb ( .aclk ( s0_axi_aclk ), .aresetn ( s0_axi_aresetn ), .s_axi_awid ( s0_axi_awid ), .s_axi_awaddr ( s0_axi_awaddr_i ), .s_axi_awlen ( s0_axi_awlen ), .s_axi_awsize ( s0_axi_awsize ), .s_axi_awburst ( s0_axi_awburst ), .s_axi_awlock ( s0_axi_awlock ), .s_axi_awcache ( s0_axi_awcache ), .s_axi_awprot ( s0_axi_awprot ), .s_axi_awqos ( s0_axi_awqos ), .s_axi_awvalid ( s0_axi_awvalid ), .s_axi_awready ( s0_axi_awready ), .s_axi_wdata ( s0_axi_wdata ), .s_axi_wstrb ( s0_axi_wstrb ), .s_axi_wlast ( s0_axi_wlast ), .s_axi_wvalid ( s0_axi_wvalid ), .s_axi_wready ( s0_axi_wready ), .s_axi_bid ( s0_axi_bid ), .s_axi_bresp ( s0_axi_bresp ), .s_axi_bvalid ( s0_axi_bvalid ), .s_axi_bready ( s0_axi_bready ), .s_axi_arid ( s0_axi_arid ), .s_axi_araddr ( s0_axi_araddr_i ), .s_axi_arlen ( s0_axi_arlen ), .s_axi_arsize ( s0_axi_arsize ), .s_axi_arburst ( s0_axi_arburst ), .s_axi_arlock ( s0_axi_arlock ), .s_axi_arcache ( s0_axi_arcache ), .s_axi_arprot ( s0_axi_arprot ), .s_axi_arqos ( s0_axi_arqos ), .s_axi_arvalid ( s0_axi_arvalid ), .s_axi_arready ( s0_axi_arready ), .s_axi_rid ( s0_axi_rid ), .s_axi_rdata ( s0_axi_rdata ), .s_axi_rresp ( s0_axi_rresp ), .s_axi_rlast ( s0_axi_rlast ), .s_axi_rvalid ( s0_axi_rvalid ), .s_axi_rready ( s0_axi_rready ), .mcb_cmd_clk ( p0_cmd_clk_i ), .mcb_cmd_en ( p0_cmd_en_i ), .mcb_cmd_instr ( p0_cmd_instr_i ), .mcb_cmd_bl ( p0_cmd_bl_i ), .mcb_cmd_byte_addr ( p0_cmd_byte_addr_i ), .mcb_cmd_empty ( p0_cmd_empty_i ), .mcb_cmd_full ( p0_cmd_full_i ), .mcb_wr_clk ( p0_wr_clk_i ), .mcb_wr_en ( p0_wr_en_i ), .mcb_wr_mask ( p0_wr_mask_i ), .mcb_wr_data ( p0_wr_data_i ), .mcb_wr_full ( p0_wr_full_i ), .mcb_wr_empty ( p0_wr_empty_i ), .mcb_wr_count ( p0_wr_count_i ), .mcb_wr_underrun ( p0_wr_underrun_i ), .mcb_wr_error ( p0_wr_error_i ), .mcb_rd_clk ( p0_rd_clk_i ), .mcb_rd_en ( p0_rd_en_i ), .mcb_rd_data ( p0_rd_data_i ), .mcb_rd_full ( p0_rd_full_i ), .mcb_rd_empty ( p0_rd_empty_i ), .mcb_rd_count ( p0_rd_count_i ), .mcb_rd_overflow ( p0_rd_overflow_i ), .mcb_rd_error ( p0_rd_error_i ), .mcb_calib_done ( calib_done_synch ) ); end endgenerate // P1 AXI Bridge Mux generate if (C_S1_AXI_ENABLE == 0) begin : P1_UI_MCB assign p1_arb_en_i = p1_arb_en ; // assign p1_cmd_clk_i = p1_cmd_clk ; // assign p1_cmd_en_i = p1_cmd_en ; // assign p1_cmd_instr_i = p1_cmd_instr ; // [2:0] assign p1_cmd_bl_i = p1_cmd_bl ; // [5:0] assign p1_cmd_byte_addr_i = p1_cmd_byte_addr ; // [29:0] assign p1_cmd_empty = p1_cmd_empty_i ; // assign p1_cmd_full = p1_cmd_full_i ; // assign p1_wr_clk_i = p1_wr_clk ; // assign p1_wr_en_i = p1_wr_en ; // assign p1_wr_mask_i = p1_wr_mask ; // [C_P1_MASK_SIZE-1:0] assign p1_wr_data_i = p1_wr_data ; // [C_P1_DATA_PORT_SIZE-1:0] assign p1_wr_full = p1_wr_full_i ; // assign p1_wr_empty = p1_wr_empty_i ; // assign p1_wr_count = p1_wr_count_i ; // [6:0] assign p1_wr_underrun = p1_wr_underrun_i ; // assign p1_wr_error = p1_wr_error_i ; // assign p1_rd_clk_i = p1_rd_clk ; // assign p1_rd_en_i = p1_rd_en ; // assign p1_rd_data = p1_rd_data_i ; // [C_P1_DATA_PORT_SIZE-1:0] assign p1_rd_full = p1_rd_full_i ; // assign p1_rd_empty = p1_rd_empty_i ; // assign p1_rd_count = p1_rd_count_i ; // [6:0] assign p1_rd_overflow = p1_rd_overflow_i ; // assign p1_rd_error = p1_rd_error_i ; // end else begin : P1_UI_AXI assign p1_arb_en_i = p1_arb_en; assign s1_axi_araddr_i = s1_axi_araddr & P_S1_AXI_ADDRMASK; assign s1_axi_awaddr_i = s1_axi_awaddr & P_S1_AXI_ADDRMASK; wire calib_done_synch; mcb_ui_top_synch #( .C_SYNCH_WIDTH ( 1 ) ) axi_mcb_synch ( .clk ( s1_axi_aclk ), .synch_in ( uo_done_cal ), .synch_out ( calib_done_synch ) ); axi_mcb # ( .C_FAMILY ( "spartan6" ) , .C_S_AXI_ID_WIDTH ( C_S1_AXI_ID_WIDTH ) , .C_S_AXI_ADDR_WIDTH ( C_S1_AXI_ADDR_WIDTH ) , .C_S_AXI_DATA_WIDTH ( C_S1_AXI_DATA_WIDTH ) , .C_S_AXI_SUPPORTS_READ ( C_S1_AXI_SUPPORTS_READ ) , .C_S_AXI_SUPPORTS_WRITE ( C_S1_AXI_SUPPORTS_WRITE ) , .C_S_AXI_REG_EN0 ( C_S1_AXI_REG_EN0 ) , .C_S_AXI_REG_EN1 ( C_S1_AXI_REG_EN1 ) , .C_S_AXI_SUPPORTS_NARROW_BURST ( C_S1_AXI_SUPPORTS_NARROW_BURST ) , .C_MCB_ADDR_WIDTH ( 30 ) , .C_MCB_DATA_WIDTH ( C_P1_DATA_PORT_SIZE ) , .C_STRICT_COHERENCY ( C_S1_AXI_STRICT_COHERENCY ) , .C_ENABLE_AP ( C_S1_AXI_ENABLE_AP ) ) p1_axi_mcb ( .aclk ( s1_axi_aclk ), .aresetn ( s1_axi_aresetn ), .s_axi_awid ( s1_axi_awid ), .s_axi_awaddr ( s1_axi_awaddr_i ), .s_axi_awlen ( s1_axi_awlen ), .s_axi_awsize ( s1_axi_awsize ), .s_axi_awburst ( s1_axi_awburst ), .s_axi_awlock ( s1_axi_awlock ), .s_axi_awcache ( s1_axi_awcache ), .s_axi_awprot ( s1_axi_awprot ), .s_axi_awqos ( s1_axi_awqos ), .s_axi_awvalid ( s1_axi_awvalid ), .s_axi_awready ( s1_axi_awready ), .s_axi_wdata ( s1_axi_wdata ), .s_axi_wstrb ( s1_axi_wstrb ), .s_axi_wlast ( s1_axi_wlast ), .s_axi_wvalid ( s1_axi_wvalid ), .s_axi_wready ( s1_axi_wready ), .s_axi_bid ( s1_axi_bid ), .s_axi_bresp ( s1_axi_bresp ), .s_axi_bvalid ( s1_axi_bvalid ), .s_axi_bready ( s1_axi_bready ), .s_axi_arid ( s1_axi_arid ), .s_axi_araddr ( s1_axi_araddr_i ), .s_axi_arlen ( s1_axi_arlen ), .s_axi_arsize ( s1_axi_arsize ), .s_axi_arburst ( s1_axi_arburst ), .s_axi_arlock ( s1_axi_arlock ), .s_axi_arcache ( s1_axi_arcache ), .s_axi_arprot ( s1_axi_arprot ), .s_axi_arqos ( s1_axi_arqos ), .s_axi_arvalid ( s1_axi_arvalid ), .s_axi_arready ( s1_axi_arready ), .s_axi_rid ( s1_axi_rid ), .s_axi_rdata ( s1_axi_rdata ), .s_axi_rresp ( s1_axi_rresp ), .s_axi_rlast ( s1_axi_rlast ), .s_axi_rvalid ( s1_axi_rvalid ), .s_axi_rready ( s1_axi_rready ), .mcb_cmd_clk ( p1_cmd_clk_i ), .mcb_cmd_en ( p1_cmd_en_i ), .mcb_cmd_instr ( p1_cmd_instr_i ), .mcb_cmd_bl ( p1_cmd_bl_i ), .mcb_cmd_byte_addr ( p1_cmd_byte_addr_i ), .mcb_cmd_empty ( p1_cmd_empty_i ), .mcb_cmd_full ( p1_cmd_full_i ), .mcb_wr_clk ( p1_wr_clk_i ), .mcb_wr_en ( p1_wr_en_i ), .mcb_wr_mask ( p1_wr_mask_i ), .mcb_wr_data ( p1_wr_data_i ), .mcb_wr_full ( p1_wr_full_i ), .mcb_wr_empty ( p1_wr_empty_i ), .mcb_wr_count ( p1_wr_count_i ), .mcb_wr_underrun ( p1_wr_underrun_i ), .mcb_wr_error ( p1_wr_error_i ), .mcb_rd_clk ( p1_rd_clk_i ), .mcb_rd_en ( p1_rd_en_i ), .mcb_rd_data ( p1_rd_data_i ), .mcb_rd_full ( p1_rd_full_i ), .mcb_rd_empty ( p1_rd_empty_i ), .mcb_rd_count ( p1_rd_count_i ), .mcb_rd_overflow ( p1_rd_overflow_i ), .mcb_rd_error ( p1_rd_error_i ), .mcb_calib_done ( calib_done_synch ) ); end endgenerate // P2 AXI Bridge Mux generate if (C_S2_AXI_ENABLE == 0) begin : P2_UI_MCB assign p2_arb_en_i = p2_arb_en ; // assign p2_cmd_clk_i = p2_cmd_clk ; // assign p2_cmd_en_i = p2_cmd_en ; // assign p2_cmd_instr_i = p2_cmd_instr ; // [2:0] assign p2_cmd_bl_i = p2_cmd_bl ; // [5:0] assign p2_cmd_byte_addr_i = p2_cmd_byte_addr ; // [29:0] assign p2_cmd_empty = p2_cmd_empty_i ; // assign p2_cmd_full = p2_cmd_full_i ; // assign p2_wr_clk_i = p2_wr_clk ; // assign p2_wr_en_i = p2_wr_en ; // assign p2_wr_mask_i = p2_wr_mask ; // [3:0] assign p2_wr_data_i = p2_wr_data ; // [31:0] assign p2_wr_full = p2_wr_full_i ; // assign p2_wr_empty = p2_wr_empty_i ; // assign p2_wr_count = p2_wr_count_i ; // [6:0] assign p2_wr_underrun = p2_wr_underrun_i ; // assign p2_wr_error = p2_wr_error_i ; // assign p2_rd_clk_i = p2_rd_clk ; // assign p2_rd_en_i = p2_rd_en ; // assign p2_rd_data = p2_rd_data_i ; // [31:0] assign p2_rd_full = p2_rd_full_i ; // assign p2_rd_empty = p2_rd_empty_i ; // assign p2_rd_count = p2_rd_count_i ; // [6:0] assign p2_rd_overflow = p2_rd_overflow_i ; // assign p2_rd_error = p2_rd_error_i ; // end else begin : P2_UI_AXI assign p2_arb_en_i = p2_arb_en; assign s2_axi_araddr_i = s2_axi_araddr & P_S2_AXI_ADDRMASK; assign s2_axi_awaddr_i = s2_axi_awaddr & P_S2_AXI_ADDRMASK; wire calib_done_synch; mcb_ui_top_synch #( .C_SYNCH_WIDTH ( 1 ) ) axi_mcb_synch ( .clk ( s2_axi_aclk ), .synch_in ( uo_done_cal ), .synch_out ( calib_done_synch ) ); axi_mcb # ( .C_FAMILY ( "spartan6" ) , .C_S_AXI_ID_WIDTH ( C_S2_AXI_ID_WIDTH ) , .C_S_AXI_ADDR_WIDTH ( C_S2_AXI_ADDR_WIDTH ) , .C_S_AXI_DATA_WIDTH ( 32 ) , .C_S_AXI_SUPPORTS_READ ( C_S2_AXI_SUPPORTS_READ ) , .C_S_AXI_SUPPORTS_WRITE ( C_S2_AXI_SUPPORTS_WRITE ) , .C_S_AXI_REG_EN0 ( C_S2_AXI_REG_EN0 ) , .C_S_AXI_REG_EN1 ( C_S2_AXI_REG_EN1 ) , .C_S_AXI_SUPPORTS_NARROW_BURST ( C_S2_AXI_SUPPORTS_NARROW_BURST ) , .C_MCB_ADDR_WIDTH ( 30 ) , .C_MCB_DATA_WIDTH ( 32 ) , .C_STRICT_COHERENCY ( C_S2_AXI_STRICT_COHERENCY ) , .C_ENABLE_AP ( C_S2_AXI_ENABLE_AP ) ) p2_axi_mcb ( .aclk ( s2_axi_aclk ), .aresetn ( s2_axi_aresetn ), .s_axi_awid ( s2_axi_awid ), .s_axi_awaddr ( s2_axi_awaddr_i ), .s_axi_awlen ( s2_axi_awlen ), .s_axi_awsize ( s2_axi_awsize ), .s_axi_awburst ( s2_axi_awburst ), .s_axi_awlock ( s2_axi_awlock ), .s_axi_awcache ( s2_axi_awcache ), .s_axi_awprot ( s2_axi_awprot ), .s_axi_awqos ( s2_axi_awqos ), .s_axi_awvalid ( s2_axi_awvalid ), .s_axi_awready ( s2_axi_awready ), .s_axi_wdata ( s2_axi_wdata ), .s_axi_wstrb ( s2_axi_wstrb ), .s_axi_wlast ( s2_axi_wlast ), .s_axi_wvalid ( s2_axi_wvalid ), .s_axi_wready ( s2_axi_wready ), .s_axi_bid ( s2_axi_bid ), .s_axi_bresp ( s2_axi_bresp ), .s_axi_bvalid ( s2_axi_bvalid ), .s_axi_bready ( s2_axi_bready ), .s_axi_arid ( s2_axi_arid ), .s_axi_araddr ( s2_axi_araddr_i ), .s_axi_arlen ( s2_axi_arlen ), .s_axi_arsize ( s2_axi_arsize ), .s_axi_arburst ( s2_axi_arburst ), .s_axi_arlock ( s2_axi_arlock ), .s_axi_arcache ( s2_axi_arcache ), .s_axi_arprot ( s2_axi_arprot ), .s_axi_arqos ( s2_axi_arqos ), .s_axi_arvalid ( s2_axi_arvalid ), .s_axi_arready ( s2_axi_arready ), .s_axi_rid ( s2_axi_rid ), .s_axi_rdata ( s2_axi_rdata ), .s_axi_rresp ( s2_axi_rresp ), .s_axi_rlast ( s2_axi_rlast ), .s_axi_rvalid ( s2_axi_rvalid ), .s_axi_rready ( s2_axi_rready ), .mcb_cmd_clk ( p2_cmd_clk_i ), .mcb_cmd_en ( p2_cmd_en_i ), .mcb_cmd_instr ( p2_cmd_instr_i ), .mcb_cmd_bl ( p2_cmd_bl_i ), .mcb_cmd_byte_addr ( p2_cmd_byte_addr_i ), .mcb_cmd_empty ( p2_cmd_empty_i ), .mcb_cmd_full ( p2_cmd_full_i ), .mcb_wr_clk ( p2_wr_clk_i ), .mcb_wr_en ( p2_wr_en_i ), .mcb_wr_mask ( p2_wr_mask_i ), .mcb_wr_data ( p2_wr_data_i ), .mcb_wr_full ( p2_wr_full_i ), .mcb_wr_empty ( p2_wr_empty_i ), .mcb_wr_count ( p2_wr_count_i ), .mcb_wr_underrun ( p2_wr_underrun_i ), .mcb_wr_error ( p2_wr_error_i ), .mcb_rd_clk ( p2_rd_clk_i ), .mcb_rd_en ( p2_rd_en_i ), .mcb_rd_data ( p2_rd_data_i ), .mcb_rd_full ( p2_rd_full_i ), .mcb_rd_empty ( p2_rd_empty_i ), .mcb_rd_count ( p2_rd_count_i ), .mcb_rd_overflow ( p2_rd_overflow_i ), .mcb_rd_error ( p2_rd_error_i ), .mcb_calib_done ( calib_done_synch ) ); end endgenerate // P3 AXI Bridge Mux generate if (C_S3_AXI_ENABLE == 0) begin : P3_UI_MCB assign p3_arb_en_i = p3_arb_en ; // assign p3_cmd_clk_i = p3_cmd_clk ; // assign p3_cmd_en_i = p3_cmd_en ; // assign p3_cmd_instr_i = p3_cmd_instr ; // [2:0] assign p3_cmd_bl_i = p3_cmd_bl ; // [5:0] assign p3_cmd_byte_addr_i = p3_cmd_byte_addr ; // [29:0] assign p3_cmd_empty = p3_cmd_empty_i ; // assign p3_cmd_full = p3_cmd_full_i ; // assign p3_wr_clk_i = p3_wr_clk ; // assign p3_wr_en_i = p3_wr_en ; // assign p3_wr_mask_i = p3_wr_mask ; // [3:0] assign p3_wr_data_i = p3_wr_data ; // [31:0] assign p3_wr_full = p3_wr_full_i ; // assign p3_wr_empty = p3_wr_empty_i ; // assign p3_wr_count = p3_wr_count_i ; // [6:0] assign p3_wr_underrun = p3_wr_underrun_i ; // assign p3_wr_error = p3_wr_error_i ; // assign p3_rd_clk_i = p3_rd_clk ; // assign p3_rd_en_i = p3_rd_en ; // assign p3_rd_data = p3_rd_data_i ; // [31:0] assign p3_rd_full = p3_rd_full_i ; // assign p3_rd_empty = p3_rd_empty_i ; // assign p3_rd_count = p3_rd_count_i ; // [6:0] assign p3_rd_overflow = p3_rd_overflow_i ; // assign p3_rd_error = p3_rd_error_i ; // end else begin : P3_UI_AXI assign p3_arb_en_i = p3_arb_en; assign s3_axi_araddr_i = s3_axi_araddr & P_S3_AXI_ADDRMASK; assign s3_axi_awaddr_i = s3_axi_awaddr & P_S3_AXI_ADDRMASK; wire calib_done_synch; mcb_ui_top_synch #( .C_SYNCH_WIDTH ( 1 ) ) axi_mcb_synch ( .clk ( s3_axi_aclk ), .synch_in ( uo_done_cal ), .synch_out ( calib_done_synch ) ); axi_mcb # ( .C_FAMILY ( "spartan6" ) , .C_S_AXI_ID_WIDTH ( C_S3_AXI_ID_WIDTH ) , .C_S_AXI_ADDR_WIDTH ( C_S3_AXI_ADDR_WIDTH ) , .C_S_AXI_DATA_WIDTH ( 32 ) , .C_S_AXI_SUPPORTS_READ ( C_S3_AXI_SUPPORTS_READ ) , .C_S_AXI_SUPPORTS_WRITE ( C_S3_AXI_SUPPORTS_WRITE ) , .C_S_AXI_REG_EN0 ( C_S3_AXI_REG_EN0 ) , .C_S_AXI_REG_EN1 ( C_S3_AXI_REG_EN1 ) , .C_S_AXI_SUPPORTS_NARROW_BURST ( C_S3_AXI_SUPPORTS_NARROW_BURST ) , .C_MCB_ADDR_WIDTH ( 30 ) , .C_MCB_DATA_WIDTH ( 32 ) , .C_STRICT_COHERENCY ( C_S3_AXI_STRICT_COHERENCY ) , .C_ENABLE_AP ( C_S3_AXI_ENABLE_AP ) ) p3_axi_mcb ( .aclk ( s3_axi_aclk ), .aresetn ( s3_axi_aresetn ), .s_axi_awid ( s3_axi_awid ), .s_axi_awaddr ( s3_axi_awaddr_i ), .s_axi_awlen ( s3_axi_awlen ), .s_axi_awsize ( s3_axi_awsize ), .s_axi_awburst ( s3_axi_awburst ), .s_axi_awlock ( s3_axi_awlock ), .s_axi_awcache ( s3_axi_awcache ), .s_axi_awprot ( s3_axi_awprot ), .s_axi_awqos ( s3_axi_awqos ), .s_axi_awvalid ( s3_axi_awvalid ), .s_axi_awready ( s3_axi_awready ), .s_axi_wdata ( s3_axi_wdata ), .s_axi_wstrb ( s3_axi_wstrb ), .s_axi_wlast ( s3_axi_wlast ), .s_axi_wvalid ( s3_axi_wvalid ), .s_axi_wready ( s3_axi_wready ), .s_axi_bid ( s3_axi_bid ), .s_axi_bresp ( s3_axi_bresp ), .s_axi_bvalid ( s3_axi_bvalid ), .s_axi_bready ( s3_axi_bready ), .s_axi_arid ( s3_axi_arid ), .s_axi_araddr ( s3_axi_araddr_i ), .s_axi_arlen ( s3_axi_arlen ), .s_axi_arsize ( s3_axi_arsize ), .s_axi_arburst ( s3_axi_arburst ), .s_axi_arlock ( s3_axi_arlock ), .s_axi_arcache ( s3_axi_arcache ), .s_axi_arprot ( s3_axi_arprot ), .s_axi_arqos ( s3_axi_arqos ), .s_axi_arvalid ( s3_axi_arvalid ), .s_axi_arready ( s3_axi_arready ), .s_axi_rid ( s3_axi_rid ), .s_axi_rdata ( s3_axi_rdata ), .s_axi_rresp ( s3_axi_rresp ), .s_axi_rlast ( s3_axi_rlast ), .s_axi_rvalid ( s3_axi_rvalid ), .s_axi_rready ( s3_axi_rready ), .mcb_cmd_clk ( p3_cmd_clk_i ), .mcb_cmd_en ( p3_cmd_en_i ), .mcb_cmd_instr ( p3_cmd_instr_i ), .mcb_cmd_bl ( p3_cmd_bl_i ), .mcb_cmd_byte_addr ( p3_cmd_byte_addr_i ), .mcb_cmd_empty ( p3_cmd_empty_i ), .mcb_cmd_full ( p3_cmd_full_i ), .mcb_wr_clk ( p3_wr_clk_i ), .mcb_wr_en ( p3_wr_en_i ), .mcb_wr_mask ( p3_wr_mask_i ), .mcb_wr_data ( p3_wr_data_i ), .mcb_wr_full ( p3_wr_full_i ), .mcb_wr_empty ( p3_wr_empty_i ), .mcb_wr_count ( p3_wr_count_i ), .mcb_wr_underrun ( p3_wr_underrun_i ), .mcb_wr_error ( p3_wr_error_i ), .mcb_rd_clk ( p3_rd_clk_i ), .mcb_rd_en ( p3_rd_en_i ), .mcb_rd_data ( p3_rd_data_i ), .mcb_rd_full ( p3_rd_full_i ), .mcb_rd_empty ( p3_rd_empty_i ), .mcb_rd_count ( p3_rd_count_i ), .mcb_rd_overflow ( p3_rd_overflow_i ), .mcb_rd_error ( p3_rd_error_i ), .mcb_calib_done ( calib_done_synch ) ); end endgenerate // P4 AXI Bridge Mux generate if (C_S4_AXI_ENABLE == 0) begin : P4_UI_MCB assign p4_arb_en_i = p4_arb_en ; // assign p4_cmd_clk_i = p4_cmd_clk ; // assign p4_cmd_en_i = p4_cmd_en ; // assign p4_cmd_instr_i = p4_cmd_instr ; // [2:0] assign p4_cmd_bl_i = p4_cmd_bl ; // [5:0] assign p4_cmd_byte_addr_i = p4_cmd_byte_addr ; // [29:0] assign p4_cmd_empty = p4_cmd_empty_i ; // assign p4_cmd_full = p4_cmd_full_i ; // assign p4_wr_clk_i = p4_wr_clk ; // assign p4_wr_en_i = p4_wr_en ; // assign p4_wr_mask_i = p4_wr_mask ; // [3:0] assign p4_wr_data_i = p4_wr_data ; // [31:0] assign p4_wr_full = p4_wr_full_i ; // assign p4_wr_empty = p4_wr_empty_i ; // assign p4_wr_count = p4_wr_count_i ; // [6:0] assign p4_wr_underrun = p4_wr_underrun_i ; // assign p4_wr_error = p4_wr_error_i ; // assign p4_rd_clk_i = p4_rd_clk ; // assign p4_rd_en_i = p4_rd_en ; // assign p4_rd_data = p4_rd_data_i ; // [31:0] assign p4_rd_full = p4_rd_full_i ; // assign p4_rd_empty = p4_rd_empty_i ; // assign p4_rd_count = p4_rd_count_i ; // [6:0] assign p4_rd_overflow = p4_rd_overflow_i ; // assign p4_rd_error = p4_rd_error_i ; // end else begin : P4_UI_AXI assign p4_arb_en_i = p4_arb_en; assign s4_axi_araddr_i = s4_axi_araddr & P_S4_AXI_ADDRMASK; assign s4_axi_awaddr_i = s4_axi_awaddr & P_S4_AXI_ADDRMASK; wire calib_done_synch; mcb_ui_top_synch #( .C_SYNCH_WIDTH ( 1 ) ) axi_mcb_synch ( .clk ( s4_axi_aclk ), .synch_in ( uo_done_cal ), .synch_out ( calib_done_synch ) ); axi_mcb # ( .C_FAMILY ( "spartan6" ) , .C_S_AXI_ID_WIDTH ( C_S4_AXI_ID_WIDTH ) , .C_S_AXI_ADDR_WIDTH ( C_S4_AXI_ADDR_WIDTH ) , .C_S_AXI_DATA_WIDTH ( 32 ) , .C_S_AXI_SUPPORTS_READ ( C_S4_AXI_SUPPORTS_READ ) , .C_S_AXI_SUPPORTS_WRITE ( C_S4_AXI_SUPPORTS_WRITE ) , .C_S_AXI_REG_EN0 ( C_S4_AXI_REG_EN0 ) , .C_S_AXI_REG_EN1 ( C_S4_AXI_REG_EN1 ) , .C_S_AXI_SUPPORTS_NARROW_BURST ( C_S4_AXI_SUPPORTS_NARROW_BURST ) , .C_MCB_ADDR_WIDTH ( 30 ) , .C_MCB_DATA_WIDTH ( 32 ) , .C_STRICT_COHERENCY ( C_S4_AXI_STRICT_COHERENCY ) , .C_ENABLE_AP ( C_S4_AXI_ENABLE_AP ) ) p4_axi_mcb ( .aclk ( s4_axi_aclk ), .aresetn ( s4_axi_aresetn ), .s_axi_awid ( s4_axi_awid ), .s_axi_awaddr ( s4_axi_awaddr_i ), .s_axi_awlen ( s4_axi_awlen ), .s_axi_awsize ( s4_axi_awsize ), .s_axi_awburst ( s4_axi_awburst ), .s_axi_awlock ( s4_axi_awlock ), .s_axi_awcache ( s4_axi_awcache ), .s_axi_awprot ( s4_axi_awprot ), .s_axi_awqos ( s4_axi_awqos ), .s_axi_awvalid ( s4_axi_awvalid ), .s_axi_awready ( s4_axi_awready ), .s_axi_wdata ( s4_axi_wdata ), .s_axi_wstrb ( s4_axi_wstrb ), .s_axi_wlast ( s4_axi_wlast ), .s_axi_wvalid ( s4_axi_wvalid ), .s_axi_wready ( s4_axi_wready ), .s_axi_bid ( s4_axi_bid ), .s_axi_bresp ( s4_axi_bresp ), .s_axi_bvalid ( s4_axi_bvalid ), .s_axi_bready ( s4_axi_bready ), .s_axi_arid ( s4_axi_arid ), .s_axi_araddr ( s4_axi_araddr_i ), .s_axi_arlen ( s4_axi_arlen ), .s_axi_arsize ( s4_axi_arsize ), .s_axi_arburst ( s4_axi_arburst ), .s_axi_arlock ( s4_axi_arlock ), .s_axi_arcache ( s4_axi_arcache ), .s_axi_arprot ( s4_axi_arprot ), .s_axi_arqos ( s4_axi_arqos ), .s_axi_arvalid ( s4_axi_arvalid ), .s_axi_arready ( s4_axi_arready ), .s_axi_rid ( s4_axi_rid ), .s_axi_rdata ( s4_axi_rdata ), .s_axi_rresp ( s4_axi_rresp ), .s_axi_rlast ( s4_axi_rlast ), .s_axi_rvalid ( s4_axi_rvalid ), .s_axi_rready ( s4_axi_rready ), .mcb_cmd_clk ( p4_cmd_clk_i ), .mcb_cmd_en ( p4_cmd_en_i ), .mcb_cmd_instr ( p4_cmd_instr_i ), .mcb_cmd_bl ( p4_cmd_bl_i ), .mcb_cmd_byte_addr ( p4_cmd_byte_addr_i ), .mcb_cmd_empty ( p4_cmd_empty_i ), .mcb_cmd_full ( p4_cmd_full_i ), .mcb_wr_clk ( p4_wr_clk_i ), .mcb_wr_en ( p4_wr_en_i ), .mcb_wr_mask ( p4_wr_mask_i ), .mcb_wr_data ( p4_wr_data_i ), .mcb_wr_full ( p4_wr_full_i ), .mcb_wr_empty ( p4_wr_empty_i ), .mcb_wr_count ( p4_wr_count_i ), .mcb_wr_underrun ( p4_wr_underrun_i ), .mcb_wr_error ( p4_wr_error_i ), .mcb_rd_clk ( p4_rd_clk_i ), .mcb_rd_en ( p4_rd_en_i ), .mcb_rd_data ( p4_rd_data_i ), .mcb_rd_full ( p4_rd_full_i ), .mcb_rd_empty ( p4_rd_empty_i ), .mcb_rd_count ( p4_rd_count_i ), .mcb_rd_overflow ( p4_rd_overflow_i ), .mcb_rd_error ( p4_rd_error_i ), .mcb_calib_done ( calib_done_synch ) ); end endgenerate // P5 AXI Bridge Mux generate if (C_S5_AXI_ENABLE == 0) begin : P5_UI_MCB assign p5_arb_en_i = p5_arb_en ; // assign p5_cmd_clk_i = p5_cmd_clk ; // assign p5_cmd_en_i = p5_cmd_en ; // assign p5_cmd_instr_i = p5_cmd_instr ; // [2:0] assign p5_cmd_bl_i = p5_cmd_bl ; // [5:0] assign p5_cmd_byte_addr_i = p5_cmd_byte_addr ; // [29:0] assign p5_cmd_empty = p5_cmd_empty_i ; // assign p5_cmd_full = p5_cmd_full_i ; // assign p5_wr_clk_i = p5_wr_clk ; // assign p5_wr_en_i = p5_wr_en ; // assign p5_wr_mask_i = p5_wr_mask ; // [3:0] assign p5_wr_data_i = p5_wr_data ; // [31:0] assign p5_wr_full = p5_wr_full_i ; // assign p5_wr_empty = p5_wr_empty_i ; // assign p5_wr_count = p5_wr_count_i ; // [6:0] assign p5_wr_underrun = p5_wr_underrun_i ; // assign p5_wr_error = p5_wr_error_i ; // assign p5_rd_clk_i = p5_rd_clk ; // assign p5_rd_en_i = p5_rd_en ; // assign p5_rd_data = p5_rd_data_i ; // [31:0] assign p5_rd_full = p5_rd_full_i ; // assign p5_rd_empty = p5_rd_empty_i ; // assign p5_rd_count = p5_rd_count_i ; // [6:0] assign p5_rd_overflow = p5_rd_overflow_i ; // assign p5_rd_error = p5_rd_error_i ; // end else begin : P5_UI_AXI assign p5_arb_en_i = p5_arb_en; assign s5_axi_araddr_i = s5_axi_araddr & P_S5_AXI_ADDRMASK; assign s5_axi_awaddr_i = s5_axi_awaddr & P_S5_AXI_ADDRMASK; wire calib_done_synch; mcb_ui_top_synch #( .C_SYNCH_WIDTH ( 1 ) ) axi_mcb_synch ( .clk ( s5_axi_aclk ), .synch_in ( uo_done_cal ), .synch_out ( calib_done_synch ) ); axi_mcb # ( .C_FAMILY ( "spartan6" ) , .C_S_AXI_ID_WIDTH ( C_S5_AXI_ID_WIDTH ) , .C_S_AXI_ADDR_WIDTH ( C_S5_AXI_ADDR_WIDTH ) , .C_S_AXI_DATA_WIDTH ( 32 ) , .C_S_AXI_SUPPORTS_READ ( C_S5_AXI_SUPPORTS_READ ) , .C_S_AXI_SUPPORTS_WRITE ( C_S5_AXI_SUPPORTS_WRITE ) , .C_S_AXI_REG_EN0 ( C_S5_AXI_REG_EN0 ) , .C_S_AXI_REG_EN1 ( C_S5_AXI_REG_EN1 ) , .C_S_AXI_SUPPORTS_NARROW_BURST ( C_S5_AXI_SUPPORTS_NARROW_BURST ) , .C_MCB_ADDR_WIDTH ( 30 ) , .C_MCB_DATA_WIDTH ( 32 ) , .C_STRICT_COHERENCY ( C_S5_AXI_STRICT_COHERENCY ) , .C_ENABLE_AP ( C_S5_AXI_ENABLE_AP ) ) p5_axi_mcb ( .aclk ( s5_axi_aclk ), .aresetn ( s5_axi_aresetn ), .s_axi_awid ( s5_axi_awid ), .s_axi_awaddr ( s5_axi_awaddr_i ), .s_axi_awlen ( s5_axi_awlen ), .s_axi_awsize ( s5_axi_awsize ), .s_axi_awburst ( s5_axi_awburst ), .s_axi_awlock ( s5_axi_awlock ), .s_axi_awcache ( s5_axi_awcache ), .s_axi_awprot ( s5_axi_awprot ), .s_axi_awqos ( s5_axi_awqos ), .s_axi_awvalid ( s5_axi_awvalid ), .s_axi_awready ( s5_axi_awready ), .s_axi_wdata ( s5_axi_wdata ), .s_axi_wstrb ( s5_axi_wstrb ), .s_axi_wlast ( s5_axi_wlast ), .s_axi_wvalid ( s5_axi_wvalid ), .s_axi_wready ( s5_axi_wready ), .s_axi_bid ( s5_axi_bid ), .s_axi_bresp ( s5_axi_bresp ), .s_axi_bvalid ( s5_axi_bvalid ), .s_axi_bready ( s5_axi_bready ), .s_axi_arid ( s5_axi_arid ), .s_axi_araddr ( s5_axi_araddr_i ), .s_axi_arlen ( s5_axi_arlen ), .s_axi_arsize ( s5_axi_arsize ), .s_axi_arburst ( s5_axi_arburst ), .s_axi_arlock ( s5_axi_arlock ), .s_axi_arcache ( s5_axi_arcache ), .s_axi_arprot ( s5_axi_arprot ), .s_axi_arqos ( s5_axi_arqos ), .s_axi_arvalid ( s5_axi_arvalid ), .s_axi_arready ( s5_axi_arready ), .s_axi_rid ( s5_axi_rid ), .s_axi_rdata ( s5_axi_rdata ), .s_axi_rresp ( s5_axi_rresp ), .s_axi_rlast ( s5_axi_rlast ), .s_axi_rvalid ( s5_axi_rvalid ), .s_axi_rready ( s5_axi_rready ), .mcb_cmd_clk ( p5_cmd_clk_i ), .mcb_cmd_en ( p5_cmd_en_i ), .mcb_cmd_instr ( p5_cmd_instr_i ), .mcb_cmd_bl ( p5_cmd_bl_i ), .mcb_cmd_byte_addr ( p5_cmd_byte_addr_i ), .mcb_cmd_empty ( p5_cmd_empty_i ), .mcb_cmd_full ( p5_cmd_full_i ), .mcb_wr_clk ( p5_wr_clk_i ), .mcb_wr_en ( p5_wr_en_i ), .mcb_wr_mask ( p5_wr_mask_i ), .mcb_wr_data ( p5_wr_data_i ), .mcb_wr_full ( p5_wr_full_i ), .mcb_wr_empty ( p5_wr_empty_i ), .mcb_wr_count ( p5_wr_count_i ), .mcb_wr_underrun ( p5_wr_underrun_i ), .mcb_wr_error ( p5_wr_error_i ), .mcb_rd_clk ( p5_rd_clk_i ), .mcb_rd_en ( p5_rd_en_i ), .mcb_rd_data ( p5_rd_data_i ), .mcb_rd_full ( p5_rd_full_i ), .mcb_rd_empty ( p5_rd_empty_i ), .mcb_rd_count ( p5_rd_count_i ), .mcb_rd_overflow ( p5_rd_overflow_i ), .mcb_rd_error ( p5_rd_error_i ), .mcb_calib_done ( calib_done_synch ) ); end endgenerate endmodule
module axis_pipeline_register # ( // Width of AXI stream interfaces in bits parameter DATA_WIDTH = 8, // Propagate tkeep signal parameter KEEP_ENABLE = (DATA_WIDTH>8), // tkeep signal width (words per cycle) parameter KEEP_WIDTH = (DATA_WIDTH/8), // Propagate tlast signal parameter LAST_ENABLE = 1, // Propagate tid signal parameter ID_ENABLE = 0, // tid signal width parameter ID_WIDTH = 8, // Propagate tdest signal parameter DEST_ENABLE = 0, // tdest signal width parameter DEST_WIDTH = 8, // Propagate tuser signal parameter USER_ENABLE = 1, // tuser signal width parameter USER_WIDTH = 1, // Register type // 0 to bypass, 1 for simple buffer, 2 for skid buffer parameter REG_TYPE = 2, // Number of registers in pipeline parameter LENGTH = 2 ) ( input wire clk, input wire rst, /* * AXI input */ input wire [DATA_WIDTH-1:0] s_axis_tdata, input wire [KEEP_WIDTH-1:0] s_axis_tkeep, input wire s_axis_tvalid, output wire s_axis_tready, input wire s_axis_tlast, input wire [ID_WIDTH-1:0] s_axis_tid, input wire [DEST_WIDTH-1:0] s_axis_tdest, input wire [USER_WIDTH-1:0] s_axis_tuser, /* * AXI output */ output wire [DATA_WIDTH-1:0] m_axis_tdata, output wire [KEEP_WIDTH-1:0] m_axis_tkeep, output wire m_axis_tvalid, input wire m_axis_tready, output wire m_axis_tlast, output wire [ID_WIDTH-1:0] m_axis_tid, output wire [DEST_WIDTH-1:0] m_axis_tdest, output wire [USER_WIDTH-1:0] m_axis_tuser ); wire [DATA_WIDTH-1:0] axis_tdata[0:LENGTH]; wire [KEEP_WIDTH-1:0] axis_tkeep[0:LENGTH]; wire axis_tvalid[0:LENGTH]; wire axis_tready[0:LENGTH]; wire axis_tlast[0:LENGTH]; wire [ID_WIDTH-1:0] axis_tid[0:LENGTH]; wire [DEST_WIDTH-1:0] axis_tdest[0:LENGTH]; wire [USER_WIDTH-1:0] axis_tuser[0:LENGTH]; assign axis_tdata[0] = s_axis_tdata; assign axis_tkeep[0] = s_axis_tkeep; assign axis_tvalid[0] = s_axis_tvalid; assign s_axis_tready = axis_tready[0]; assign axis_tlast[0] = s_axis_tlast; assign axis_tid[0] = s_axis_tid; assign axis_tdest[0] = s_axis_tdest; assign axis_tuser[0] = s_axis_tuser; assign m_axis_tdata = axis_tdata[LENGTH]; assign m_axis_tkeep = axis_tkeep[LENGTH]; assign m_axis_tvalid = axis_tvalid[LENGTH]; assign axis_tready[LENGTH] = m_axis_tready; assign m_axis_tlast = axis_tlast[LENGTH]; assign m_axis_tid = axis_tid[LENGTH]; assign m_axis_tdest = axis_tdest[LENGTH]; assign m_axis_tuser = axis_tuser[LENGTH]; generate genvar i; for (i = 0; i < LENGTH; i = i + 1) begin : pipe_reg axis_register #( .DATA_WIDTH(DATA_WIDTH), .KEEP_ENABLE(KEEP_ENABLE), .KEEP_WIDTH(KEEP_WIDTH), .LAST_ENABLE(LAST_ENABLE), .ID_ENABLE(ID_ENABLE), .ID_WIDTH(ID_WIDTH), .DEST_ENABLE(DEST_ENABLE), .DEST_WIDTH(DEST_WIDTH), .USER_ENABLE(USER_ENABLE), .USER_WIDTH(USER_WIDTH), .REG_TYPE(REG_TYPE) ) reg_inst ( .clk(clk), .rst(rst), // AXI input .s_axis_tdata(axis_tdata[i]), .s_axis_tkeep(axis_tkeep[i]), .s_axis_tvalid(axis_tvalid[i]), .s_axis_tready(axis_tready[i]), .s_axis_tlast(axis_tlast[i]), .s_axis_tid(axis_tid[i]), .s_axis_tdest(axis_tdest[i]), .s_axis_tuser(axis_tuser[i]), // AXI output .m_axis_tdata(axis_tdata[i+1]), .m_axis_tkeep(axis_tkeep[i+1]), .m_axis_tvalid(axis_tvalid[i+1]), .m_axis_tready(axis_tready[i+1]), .m_axis_tlast(axis_tlast[i+1]), .m_axis_tid(axis_tid[i+1]), .m_axis_tdest(axis_tdest[i+1]), .m_axis_tuser(axis_tuser[i+1]) ); end endgenerate endmodule
module testbench; parameter NO_OF_MSGS=128, MSG_WIDTH=4, B=3, PATTERN_WIDTH=74, SIGN_DEPTH=128, SHIFT_WIDTH=$clog2(PATTERN_WIDTH-B+1),DATA_WIDTH=MSG_WIDTH*NO_OF_MSGS, NOS_SHIFTER=2*NO_OF_MSGS, POINTER_WIDTH=$clog2(NOS_SHIFTER), NOS_KEY=4, NOS_CMPS=SIGN_DEPTH/NOS_KEY,NOS_STGS=$clog2(SIGN_DEPTH/NOS_KEY),SFT_DEL_WDH=$clog2(NOS_STGS+NOS_KEY+2),MAX_PAT_SZ=78; localparam clk_prd = 2, nos_inputs=80; reg clk; reg reset; reg datInReady; reg [DATA_WIDTH-1:0] DataIn; wire getDATA; wire [NOS_STGS:1] fullCompare; wire [POINTER_WIDTH-1:0] shift_pnt; wire [6:0]dout; reg [DATA_WIDTH-1:0] ram [nos_inputs-1:0]; integer i=0; Wu_Manber_shiftPE #(NO_OF_MSGS,MSG_WIDTH,B,PATTERN_WIDTH, SIGN_DEPTH,SHIFT_WIDTH,DATA_WIDTH,NOS_SHIFTER,POINTER_WIDTH,NOS_KEY,NOS_CMPS,NOS_STGS,SFT_DEL_WDH,MAX_PAT_SZ) uut (.clk(clk), .reset(reset), .datInReady(datInReady), .DataIn(DataIn), .getDATA(getDATA), .fullCompare(fullCompare), .shift_pnt(shift_pnt), .dout(dout) ); initial begin $readmemh("/home/ashikpoojari/Desktop/xilinx_codes/codes100/input.txt", ram); // memory_list is memory file end initial begin clk <= 1'b1; reset <= 1'b0; datInReady <= 1'b0; #(2*clk_prd) reset <= 1'b1; #(4*clk_prd) reset <= 1'b0; #(5*clk_prd) datInReady <= 1'b1; #(1*clk_prd) datInReady <= 1'b0; end always #(clk_prd/2) clk <= ~clk; always@(getDATA)begin if(getDATA)begin DataIn=ram[i]; i=i+1; end end endmodule
module wallace(x,y,p); input [7:0] x,y; output [15:0] p; wire [6:0] ip1; wire [7:0] ip2,ip3,ip4,ip5,ip6,ip7,ip8,si,iip; wire [6:0] s1,s2,s3,s4,s5,s6; wire [7:0] c1,c2,c3,c4,c5,c6,c7; wire c; // first AND array and fi1(p[0],y[0],x[0]); and fi2(ip1[0],y[0],x[1]); and fi3(ip1[1],y[0],x[2]); and fi4(ip1[2],y[0],x[3]); and fi5(ip1[3],y[0],x[4]); and fi6(ip1[4],y[0],x[5]); and fi7(ip1[5],y[0],x[6]); and fi8(ip1[6],y[0],x[7]); not n1(si[0],ip1[6]); // second AND array and NOT GATES and se1(ip2[0],y[1],x[0]); and se2(ip2[1],y[1],x[1]); and se3(ip2[2],y[1],x[2]); and se4(ip2[3],y[1],x[3]); and se5(ip2[4],y[1],x[4]); and se6(ip2[5],y[1],x[5]); and se7(ip2[6],y[1],x[6]); and se8(ip2[7],y[1],x[7]); not n2(si[1],ip2[7]); //third and th1(ip3[0],y[2],x[0]); and th2(ip3[1],y[2],x[1]); and th3(ip3[2],y[2],x[2]); and th4(ip3[3],y[2],x[3]); and th5(ip3[4],y[2],x[4]); and th6(ip3[5],y[2],x[5]); and th7(ip3[6],y[2],x[6]); and th8(ip3[7],y[2],x[7]); not n3(si[2],ip3[7]); //fourth and fo1(ip4[0],y[3],x[0]); and fo2(ip4[1],y[3],x[1]); and fo3(ip4[2],y[3],x[2]); and fo4(ip4[3],y[3],x[3]); and fo5(ip4[4],y[3],x[4]); and fo6(ip4[5],y[3],x[5]); and fo7(ip4[6],y[3],x[6]); and fo8(ip4[7],y[3],x[7]); not n4(si[3],ip4[7]); //fifth and fif1(ip5[0],y[4],x[0]); and fif2(ip5[1],y[4],x[1]); and fif3(ip5[2],y[4],x[2]); and fif4(ip5[3],y[4],x[3]); and fif5(ip5[4],y[4],x[4]); and fif6(ip5[5],y[4],x[5]); and fif7(ip5[6],y[4],x[6]); and fif8(ip5[7],y[4],x[7]); not n5(si[4],ip5[7]); //sixth and si1(ip6[0],y[5],x[0]); and si2(ip6[1],y[5],x[1]); and si3(ip6[2],y[5],x[2]); and si4(ip6[3],y[5],x[3]); and si5(ip6[4],y[5],x[4]); and si6(ip6[5],y[5],x[5]); and si7(ip6[6],y[5],x[6]); and si8(ip6[7],y[5],x[7]); not n6(si[5],ip6[7]); //seventh and sev1(ip7[0],y[6],x[0]); and sev2(ip7[1],y[6],x[1]); and sev3(ip7[2],y[6],x[2]); and sev4(ip7[3],y[6],x[3]); and sev5(ip7[4],y[6],x[4]); and sev6(ip7[5],y[6],x[5]); and sev7(ip7[6],y[6],x[6]); and sev8(ip7[7],y[6],x[7]); not n7(si[6],ip7[7]); //eight and eii1(iip[0],y[7],x[0]); and eii2(iip[1],y[7],x[1]); and eii3(iip[2],y[7],x[2]); and eii4(iip[3],y[7],x[3]); and eii5(iip[4],y[7],x[4]); and eii6(iip[5],y[7],x[5]); and eii7(iip[6],y[7],x[6]); and eii8(iip[7],y[7],x[7]); xor ei1(ip8[0],y[7],iip[0]); xor ei2(ip8[1],y[7],iip[1]); xor ei3(ip8[2],y[7],iip[2]); xor ei4(ip8[3],y[7],iip[3]); xor ei5(ip8[4],y[7],iip[4]); xor ei6(ip8[5],y[7],iip[5]); xor ei7(ip8[6],y[7],iip[6]); xor ei8(ip8[7],y[7],iip[7]); not n8(si[7],ip8[7]); //first adder array HA ha1(ip1[0],ip2[0],c1[0],p[1]); FA fa1(ip1[1],ip2[1],ip3[0],c1[1],s1[0]); FA fa2(ip1[2],ip2[2],ip3[1],c1[2],s1[1]); FA fa3(ip1[3],ip2[3],ip3[2],c1[3],s1[2]); FA fa4(ip1[4],ip2[4],ip3[3],c1[4],s1[3]); FA fa5(ip1[5],ip2[5],ip3[4],c1[5],s1[4]); FA fa6(ip1[6],ip2[6],ip3[5],c1[6],s1[5]); FA fa7(si[0],si[1],ip3[6],c1[7],s1[6]); //second adder array HA ha2(s1[0],c1[0],c2[0],p[2]); FA sa1(s1[1],c1[1],ip4[0],c2[1],s2[0]); FA sa2(s1[2],c1[2],ip4[1],c2[2],s2[1]); FA sa3(s1[3],c1[3],ip4[2],c2[3],s2[2]); FA sa4(s1[4],c1[4],ip4[3],c2[4],s2[3]); FA sa5(s1[5],c1[5],ip4[4],c2[5],s2[4]); FA sa6(s1[6],c1[6],ip4[5],c2[6],s2[5]); FA sa7(si[2],c1[7],ip4[6],c2[7],s2[6]); //third adder HA ha3(s2[0],c2[0],c3[0],p[3]); FA ta1(s2[1],ip5[0],c2[1],c3[1],s3[0]); FA ta2(s2[2],ip5[1],c2[2],c3[2],s3[1]); FA ta3(s2[3],ip5[2],c2[3],c3[3],s3[2]); FA ta4(s2[4],ip5[3],c2[4],c3[4],s3[3]); FA ta5(s2[5],ip5[4],c2[5],c3[5],s3[4]); FA ta6(s2[6],ip5[5],c2[6],c3[6],s3[5]); FA ta7(si[3],ip5[6],c2[7],c3[7],s3[6]); //fourth adder HA ha4(s3[0],c3[0],c4[0],p[4]); FA foa1(s3[1],ip6[0],c3[1],c4[1],s4[0]); FA foa2(s3[2],ip6[1],c3[2],c4[2],s4[1]); FA foa3(s3[3],ip6[2],c3[3],c4[3],s4[2]); FA foa4(s3[4],ip6[3],c3[4],c4[4],s4[3]); FA foa5(s3[5],ip6[4],c3[5],c4[5],s4[4]); FA foa6(s3[6],ip6[5],c3[6],c4[6],s4[5]); FA foa7(si[4],ip6[6],c3[7],c4[7],s4[6]); //fifth adder HA ha5(s4[0],c4[0],c5[0],p[5]); FA fia1(s4[1],ip7[0],c4[1],c5[1],s5[0]); FA fia2(s4[2],ip7[1],c4[2],c5[2],s5[1]); FA fia3(s4[3],ip7[2],c4[3],c5[3],s5[2]); FA fia4(s4[4],ip7[3],c4[4],c5[4],s5[3]); FA fia5(s4[5],ip7[4],c4[5],c5[5],s5[4]); FA fia6(s4[6],ip7[5],c4[6],c5[6],s5[5]); FA fia7(si[5],ip7[6],c4[7],c5[7],s5[6]); //sixth adder HA ha6(s5[0],c5[0],c6[0],p[6]); FA sia1(s5[1],ip8[0],c5[1],c6[1],s6[0]); FA sia2(s5[2],ip8[1],c5[2],c6[2],s6[1]); FA sia3(s5[3],ip8[2],c5[3],c6[3],s6[2]); FA sia4(s5[4],ip8[3],c5[4],c6[4],s6[3]); FA sia5(s5[5],ip8[4],c5[5],c6[5],s6[4]); FA sia6(s5[6],ip8[5],c5[6],c6[6],s6[5]); FA sia7(si[6],ip8[6],c5[7],c6[7],s6[6]); //seventh adder FAd sea0(s6[0],c6[0],y[7],c7[0],p[7]); FAd sea1(s6[1],c6[1],c7[0],c7[1],p[8]); FAd sea2(s6[2],c6[2],c7[1],c7[2],p[9]); FAd sea3(s6[3],c6[3],c7[2],c7[3],p[10]); FAd sea4(s6[4],c6[4],c7[3],c7[4],p[11]); FAd sea5(s6[5],c6[5],c7[4],c7[5],p[12]); FAd sea6(s6[6],c6[6],c7[5],c7[6],p[13]); FAd sea7(si[7],c6[7],c7[6],c7[7],p[14]); HA ha8(c7[7],1'b1,c,p[15]); endmodule
module HA(a,b,c,s); input a,b; output c,s; xor x1(s,a,b); and a1(c,a,b); endmodule
module FA(a,b,c,cy,sm); input a,b,c; output cy,sm; wire x,y; xor x1(x,a,b); xnor x2(y,a,b); MUX m1(x,y,c,sm); MUX m2(a,c,x,cy); endmodule
module MUX(i0,i1,s,o); input i0,i1,s; output o; wire t,p,q; and a1(t,s,i1); not n0(p,s); and a2(q,p,i0); or a3(o,t,q); endmodule
module FAd(a,b,c,cy,sm); input a,b,c; output cy,sm; wire x,y,z; xor x1(x,a,b); xor x2(sm,x,c); and a1(y,a,b); and a2(z,x,c); or o1(cy,y,z); endmodule
module sky130_fd_sc_ls__decaphe (); // No contents. endmodule
module alu( input clk, input reset, input [31:0] i_a, // 1st operand input [31:0] i_b, // 2nd operand input [1:0] i_cmd, // command output [31:0] o_result, output o_valid, // result is valid output o_ready // ready to take input ); reg [31:0] reg_result; reg reg_valid = 1'b0; // ALU state machine macros `define ST_RESET 2'h0 `define ST_READY 2'h1 `define ST_BUSY 2'h2 // begin in reset state reg [1:0] reg_status = `ST_RESET; // Synchronous reset always @(posedge clk && reset) begin reg_status <= `ST_READY; end // Assign outputs assign o_ready = ((reg_status == `ST_READY) && !reset); assign o_valid = (reg_valid && (reg_status == `ST_READY)); assign o_result = o_valid ? reg_result : 32'hx; // Ternary operator // Main processing loop always @(posedge clk && !reset) begin case (reg_status) `ST_READY: begin reg_status <= `ST_BUSY; if (i_cmd == `OP_ADD) begin reg_result = i_a + i_b; end // TODO: add OP_SUB end `ST_BUSY: begin reg_valid <= 1'b1; reg_status <= `ST_READY; end default: begin $display("should not happen"); $finish; end endcase end endmodule
module SerialHandler( input wire clk100MHz, input wire clk1MHz, input wire rst, input wire ext_clk, input wire ext_flush, input wire serial, input wire [CHANNEL_WIDTH-1:0] channel, output reg [CHANNEL_WIDTH-1:0] ser_channel, output reg [POSITION_WIDTH-1:0] ser_pos ); parameter POSITION_WIDTH = 11; parameter CHANNEL_WIDTH = 5; parameter BUFFER_LENGTH = 16; reg [BUFFER_LENGTH-1:0] buffer; reg [CHANNEL_WIDTH-1:0] channel_select; reg [POSITION_WIDTH-1:0] position; wire clk; wire flush; ExtToIntSync U0( .clk(clk100MHz), .rst(rst), .ext_signal(ext_clk), .int_signal(clk) ); ExtToIntSync U1( .clk(clk100MHz), .rst(rst), .ext_signal(ext_flush), .int_signal(flush) ); integer ptr; always @(posedge clk or posedge rst) begin if(rst) begin position = 0; buffer = 0; ptr = 0; end else if(!flush) begin if(ptr < 15) begin buffer[(BUFFER_LENGTH-1)-ptr] = serial; ptr = ptr + 1; end else begin // Channel Select: 15th-11th bit (5 bit width) channel_select = buffer[BUFFER_LENGTH-1:BUFFER_LENGTH-5]; // Position: 11th-0th bit (11 bit width) position = buffer[BUFFER_LENGTH-6:0]; // Write to position file @ channel select point // Make position a 11 bit signal and OR a 1 with it. //position_file[channel_select] = (position << 1) | 1'b1; if(channel_select == channel) begin ser_pos = position; end //ser_pos = position; ser_channel = channel_select; // Reset buffer and ptr buffer = 0; ptr = 0; end end else begin position = 0; buffer = 0; ptr = 0; end end endmodule
module ghrd( ///////// ADC ///////// output ADC_CONVST, output ADC_SCK, output ADC_SDI, input ADC_SDO, ///////// ARDUINO ///////// inout [15:0] ARDUINO_IO, inout ARDUINO_RESET_N, `ifdef ENABLE_CLK ///////// CLK ///////// output CLK_I2C_SCL, inout CLK_I2C_SDA, `endif /*ENABLE_CLK*/ ///////// FPGA ///////// input FPGA_CLK1_50, input FPGA_CLK2_50, input FPGA_CLK3_50, ///////// GPIO ///////// inout [35:0] GPIO_0, inout [35:0] GPIO_1, `ifdef ENABLE_HPS ///////// HPS ///////// inout HPS_CONV_USB_N, output [14:0] HPS_DDR3_ADDR, output [2:0] HPS_DDR3_BA, output HPS_DDR3_CAS_N, output HPS_DDR3_CKE, output HPS_DDR3_CK_N, output HPS_DDR3_CK_P, output HPS_DDR3_CS_N, output [3:0] HPS_DDR3_DM, inout [31:0] HPS_DDR3_DQ, inout [3:0] HPS_DDR3_DQS_N, inout [3:0] HPS_DDR3_DQS_P, output HPS_DDR3_ODT, output HPS_DDR3_RAS_N, output HPS_DDR3_RESET_N, input HPS_DDR3_RZQ, output HPS_DDR3_WE_N, output HPS_ENET_GTX_CLK, inout HPS_ENET_INT_N, output HPS_ENET_MDC, inout HPS_ENET_MDIO, input HPS_ENET_RX_CLK, input [3:0] HPS_ENET_RX_DATA, input HPS_ENET_RX_DV, output [3:0] HPS_ENET_TX_DATA, output HPS_ENET_TX_EN, inout HPS_GSENSOR_INT, inout HPS_I2C0_SCLK, inout HPS_I2C0_SDAT, inout HPS_I2C1_SCLK, inout HPS_I2C1_SDAT, inout HPS_KEY, inout HPS_LED, inout HPS_LTC_GPIO, output HPS_SD_CLK, inout HPS_SD_CMD, inout [3:0] HPS_SD_DATA, output HPS_SPIM_CLK, input HPS_SPIM_MISO, output HPS_SPIM_MOSI, inout HPS_SPIM_SS, input HPS_UART_RX, output HPS_UART_TX, input HPS_USB_CLKOUT, inout [7:0] HPS_USB_DATA, input HPS_USB_DIR, input HPS_USB_NXT, output HPS_USB_STP, `endif /*ENABLE_HPS*/ ///////// KEY ///////// input [1:0] KEY, ///////// LED ///////// output [7:0] LED, ///////// SW ///////// input [3:0] SW ); //======================================================= // REG/WIRE declarations //======================================================= // internal wires and registers declaration wire [1:0] fpga_debounced_buttons; wire [7:0] fpga_led_internal; wire hps_fpga_reset_n; wire [2:0] hps_reset_req; wire hps_cold_reset; wire hps_warm_reset; wire hps_debug_reset; wire [27:0] stm_hw_events; // connection of internal logics assign stm_hw_events = {{13{1'b0}},SW, fpga_led_internal, fpga_debounced_buttons}; //======================================================= // Structural coding //======================================================= soc_system u0 ( //Clock&Reset .clk_clk (FPGA_CLK1_50 ), // clk.clk .reset_reset_n (1'b1 ), // reset.reset_n //HPS ddr3 .memory_mem_a ( HPS_DDR3_ADDR), // memory.mem_a .memory_mem_ba ( HPS_DDR3_BA), // .mem_ba .memory_mem_ck ( HPS_DDR3_CK_P), // .mem_ck .memory_mem_ck_n ( HPS_DDR3_CK_N), // .mem_ck_n .memory_mem_cke ( HPS_DDR3_CKE), // .mem_cke .memory_mem_cs_n ( HPS_DDR3_CS_N), // .mem_cs_n .memory_mem_ras_n ( HPS_DDR3_RAS_N), // .mem_ras_n .memory_mem_cas_n ( HPS_DDR3_CAS_N), // .mem_cas_n .memory_mem_we_n ( HPS_DDR3_WE_N), // .mem_we_n .memory_mem_reset_n ( HPS_DDR3_RESET_N), // .mem_reset_n .memory_mem_dq ( HPS_DDR3_DQ), // .mem_dq .memory_mem_dqs ( HPS_DDR3_DQS_P), // .mem_dqs .memory_mem_dqs_n ( HPS_DDR3_DQS_N), // .mem_dqs_n .memory_mem_odt ( HPS_DDR3_ODT), // .mem_odt .memory_mem_dm ( HPS_DDR3_DM), // .mem_dm .memory_oct_rzqin ( HPS_DDR3_RZQ), // .oct_rzqin //HPS ethernet .hps_0_hps_io_hps_io_emac1_inst_TX_CLK ( HPS_ENET_GTX_CLK), // hps_0_hps_io.hps_io_emac1_inst_TX_CLK .hps_0_hps_io_hps_io_emac1_inst_TXD0 ( HPS_ENET_TX_DATA[0] ), // .hps_io_emac1_inst_TXD0 .hps_0_hps_io_hps_io_emac1_inst_TXD1 ( HPS_ENET_TX_DATA[1] ), // .hps_io_emac1_inst_TXD1 .hps_0_hps_io_hps_io_emac1_inst_TXD2 ( HPS_ENET_TX_DATA[2] ), // .hps_io_emac1_inst_TXD2 .hps_0_hps_io_hps_io_emac1_inst_TXD3 ( HPS_ENET_TX_DATA[3] ), // .hps_io_emac1_inst_TXD3 .hps_0_hps_io_hps_io_emac1_inst_RXD0 ( HPS_ENET_RX_DATA[0] ), // .hps_io_emac1_inst_RXD0 .hps_0_hps_io_hps_io_emac1_inst_MDIO ( HPS_ENET_MDIO ), // .hps_io_emac1_inst_MDIO .hps_0_hps_io_hps_io_emac1_inst_MDC ( HPS_ENET_MDC ), // .hps_io_emac1_inst_MDC .hps_0_hps_io_hps_io_emac1_inst_RX_CTL ( HPS_ENET_RX_DV), // .hps_io_emac1_inst_RX_CTL .hps_0_hps_io_hps_io_emac1_inst_TX_CTL ( HPS_ENET_TX_EN), // .hps_io_emac1_inst_TX_CTL .hps_0_hps_io_hps_io_emac1_inst_RX_CLK ( HPS_ENET_RX_CLK), // .hps_io_emac1_inst_RX_CLK .hps_0_hps_io_hps_io_emac1_inst_RXD1 ( HPS_ENET_RX_DATA[1] ), // .hps_io_emac1_inst_RXD1 .hps_0_hps_io_hps_io_emac1_inst_RXD2 ( HPS_ENET_RX_DATA[2] ), // .hps_io_emac1_inst_RXD2 .hps_0_hps_io_hps_io_emac1_inst_RXD3 ( HPS_ENET_RX_DATA[3] ), // .hps_io_emac1_inst_RXD3 //HPS SD card .hps_0_hps_io_hps_io_sdio_inst_CMD ( HPS_SD_CMD ), // .hps_io_sdio_inst_CMD .hps_0_hps_io_hps_io_sdio_inst_D0 ( HPS_SD_DATA[0] ), // .hps_io_sdio_inst_D0 .hps_0_hps_io_hps_io_sdio_inst_D1 ( HPS_SD_DATA[1] ), // .hps_io_sdio_inst_D1 .hps_0_hps_io_hps_io_sdio_inst_CLK ( HPS_SD_CLK ), // .hps_io_sdio_inst_CLK .hps_0_hps_io_hps_io_sdio_inst_D2 ( HPS_SD_DATA[2] ), // .hps_io_sdio_inst_D2 .hps_0_hps_io_hps_io_sdio_inst_D3 ( HPS_SD_DATA[3] ), // .hps_io_sdio_inst_D3 //HPS USB .hps_0_hps_io_hps_io_usb1_inst_D0 ( HPS_USB_DATA[0] ), // .hps_io_usb1_inst_D0 .hps_0_hps_io_hps_io_usb1_inst_D1 ( HPS_USB_DATA[1] ), // .hps_io_usb1_inst_D1 .hps_0_hps_io_hps_io_usb1_inst_D2 ( HPS_USB_DATA[2] ), // .hps_io_usb1_inst_D2 .hps_0_hps_io_hps_io_usb1_inst_D3 ( HPS_USB_DATA[3] ), // .hps_io_usb1_inst_D3 .hps_0_hps_io_hps_io_usb1_inst_D4 ( HPS_USB_DATA[4] ), // .hps_io_usb1_inst_D4 .hps_0_hps_io_hps_io_usb1_inst_D5 ( HPS_USB_DATA[5] ), // .hps_io_usb1_inst_D5 .hps_0_hps_io_hps_io_usb1_inst_D6 ( HPS_USB_DATA[6] ), // .hps_io_usb1_inst_D6 .hps_0_hps_io_hps_io_usb1_inst_D7 ( HPS_USB_DATA[7] ), // .hps_io_usb1_inst_D7 .hps_0_hps_io_hps_io_usb1_inst_CLK ( HPS_USB_CLKOUT ), // .hps_io_usb1_inst_CLK .hps_0_hps_io_hps_io_usb1_inst_STP ( HPS_USB_STP ), // .hps_io_usb1_inst_STP .hps_0_hps_io_hps_io_usb1_inst_DIR ( HPS_USB_DIR ), // .hps_io_usb1_inst_DIR .hps_0_hps_io_hps_io_usb1_inst_NXT ( HPS_USB_NXT ), // .hps_io_usb1_inst_NXT //HPS SPI .hps_0_hps_io_hps_io_spim1_inst_CLK ( HPS_SPIM_CLK ), // .hps_io_spim1_inst_CLK .hps_0_hps_io_hps_io_spim1_inst_MOSI ( HPS_SPIM_MOSI ), // .hps_io_spim1_inst_MOSI .hps_0_hps_io_hps_io_spim1_inst_MISO ( HPS_SPIM_MISO ), // .hps_io_spim1_inst_MISO .hps_0_hps_io_hps_io_spim1_inst_SS0 ( HPS_SPIM_SS ), // .hps_io_spim1_inst_SS0 //HPS UART .hps_0_hps_io_hps_io_uart0_inst_RX ( HPS_UART_RX ), // .hps_io_uart0_inst_RX .hps_0_hps_io_hps_io_uart0_inst_TX ( HPS_UART_TX ), // .hps_io_uart0_inst_TX //HPS I2C1 .hps_0_hps_io_hps_io_i2c0_inst_SDA ( HPS_I2C0_SDAT ), // .hps_io_i2c0_inst_SDA .hps_0_hps_io_hps_io_i2c0_inst_SCL ( HPS_I2C0_SCLK ), // .hps_io_i2c0_inst_SCL //HPS I2C2 .hps_0_hps_io_hps_io_i2c1_inst_SDA ( HPS_I2C1_SDAT ), // .hps_io_i2c1_inst_SDA .hps_0_hps_io_hps_io_i2c1_inst_SCL ( HPS_I2C1_SCLK ), // .hps_io_i2c1_inst_SCL //GPIO .hps_0_hps_io_hps_io_gpio_inst_GPIO09 ( HPS_CONV_USB_N ), // .hps_io_gpio_inst_GPIO09 .hps_0_hps_io_hps_io_gpio_inst_GPIO35 ( HPS_ENET_INT_N ), // .hps_io_gpio_inst_GPIO35 .hps_0_hps_io_hps_io_gpio_inst_GPIO40 ( HPS_LTC_GPIO ), // .hps_io_gpio_inst_GPIO40 .hps_0_hps_io_hps_io_gpio_inst_GPIO53 ( HPS_LED ), // .hps_io_gpio_inst_GPIO53 .hps_0_hps_io_hps_io_gpio_inst_GPIO54 ( HPS_KEY ), // .hps_io_gpio_inst_GPIO54 .hps_0_hps_io_hps_io_gpio_inst_GPIO61 ( HPS_GSENSOR_INT ), // .hps_io_gpio_inst_GPIO61 .hps_0_f2h_stm_hw_events_stm_hwevents (stm_hw_events), // hps_0_f2h_stm_hw_events.stm_hwevents .hps_0_h2f_reset_reset_n (hps_fpga_reset_n), // hps_0_h2f_reset.reset_n .hps_0_f2h_warm_reset_req_reset_n (~hps_warm_reset), // hps_0_f2h_warm_reset_req.reset_n .hps_0_f2h_debug_reset_req_reset_n (~hps_debug_reset), // hps_0_f2h_debug_reset_req.reset_n .hps_0_f2h_cold_reset_req_reset_n (~hps_cold_reset) // hps_0_f2h_cold_reset_req.reset_n ); // Source/Probe megawizard instance hps_reset hps_reset_inst ( .source_clk (FPGA_CLK1_50), .source (hps_reset_req) ); altera_edge_detector pulse_cold_reset ( .clk (FPGA_CLK1_50), .rst_n (hps_fpga_reset_n), .signal_in (hps_reset_req[0]), .pulse_out (hps_cold_reset) ); defparam pulse_cold_reset.PULSE_EXT = 6; defparam pulse_cold_reset.EDGE_TYPE = 1; defparam pulse_cold_reset.IGNORE_RST_WHILE_BUSY = 1; altera_edge_detector pulse_warm_reset ( .clk (FPGA_CLK1_50), .rst_n (hps_fpga_reset_n), .signal_in (hps_reset_req[1]), .pulse_out (hps_warm_reset) ); defparam pulse_warm_reset.PULSE_EXT = 2; defparam pulse_warm_reset.EDGE_TYPE = 1; defparam pulse_warm_reset.IGNORE_RST_WHILE_BUSY = 1; altera_edge_detector pulse_debug_reset ( .clk (FPGA_CLK1_50), .rst_n (hps_fpga_reset_n), .signal_in (hps_reset_req[2]), .pulse_out (hps_debug_reset) ); defparam pulse_debug_reset.PULSE_EXT = 32; defparam pulse_debug_reset.EDGE_TYPE = 1; defparam pulse_debug_reset.IGNORE_RST_WHILE_BUSY = 1; endmodule
module mig_7series_v2_0_mc # ( parameter TCQ = 100, // clk->out delay(sim only) parameter ADDR_CMD_MODE = "1T", // registered or // 1Tfered mem? parameter BANK_WIDTH = 3, // bank address width parameter BM_CNT_WIDTH = 2, // # BM counter width // i.e., log2(nBANK_MACHS) parameter BURST_MODE = "8", // Burst length parameter CL = 5, // Read CAS latency // (in clk cyc) parameter CMD_PIPE_PLUS1 = "ON", // add register stage // between MC and PHY parameter COL_WIDTH = 12, // column address width parameter CS_WIDTH = 4, // # of unique CS outputs parameter CWL = 5, // Write CAS latency // (in clk cyc) parameter DATA_BUF_ADDR_WIDTH = 8, // User request tag (e.g. // user src/dest buf addr) parameter DATA_BUF_OFFSET_WIDTH = 1, // User buffer offset width parameter DATA_WIDTH = 64, // Data bus width parameter DQ_WIDTH = 64, // # of DQ (data) parameter DQS_WIDTH = 8, // # of DQS (strobe) parameter DRAM_TYPE = "DDR3", // Memory I/F type: // "DDR3", "DDR2" parameter ECC = "OFF", // ECC ON/OFF? parameter ECC_WIDTH = 8, // # of ECC bits parameter MAINT_PRESCALER_PERIOD= 200000, // maintenance period (ps) parameter MC_ERR_ADDR_WIDTH = 31, // # of error address bits parameter nBANK_MACHS = 4, // # of bank machines (BM) parameter nCK_PER_CLK = 4, // DRAM clock : MC clock // frequency ratio parameter nCS_PER_RANK = 1, // # of unique CS outputs // per rank parameter nREFRESH_BANK = 1, // # of REF cmds to pull-in parameter nSLOTS = 1, // # DIMM slots in system parameter ORDERING = "NORM", // request ordering mode parameter PAYLOAD_WIDTH = 64, // Width of data payload // from PHY parameter RANK_WIDTH = 2, // # of bits to count ranks parameter RANKS = 4, // # of ranks of DRAM parameter REG_CTRL = "ON", // "ON" for registered DIMM parameter ROW_WIDTH = 16, // row address width parameter RTT_NOM = "40", // Nominal ODT value parameter RTT_WR = "120", // Write ODT value parameter SLOT_0_CONFIG = 8'b0000_0101, // ranks allowed in slot 0 parameter SLOT_1_CONFIG = 8'b0000_1010, // ranks allowed in slot 1 parameter STARVE_LIMIT = 2, // max # of times a user // request is allowed to // lose arbitration when // reordering is enabled parameter tCK = 2500, // memory clk period(ps) parameter tCKE = 10000, // CKE minimum pulse (ps) parameter tFAW = 40000, // four activate window(ps) parameter tRAS = 37500, // ACT->PRE cmd period (ps) parameter tRCD = 12500, // ACT->R/W delay (ps) parameter tREFI = 7800000, // average periodic // refresh interval(ps) parameter CKE_ODT_AUX = "FALSE", //Parameter to turn on/off the aux_out signal parameter tRFC = 110000, // REF->ACT/REF delay (ps) parameter tRP = 12500, // PRE cmd period (ps) parameter tRRD = 10000, // ACT->ACT period (ps) parameter tRTP = 7500, // Read->PRE cmd delay (ps) parameter tWTR = 7500, // Internal write->read // delay (ps) // requiring DLL lock (CKs) parameter tZQCS = 64, // ZQCS cmd period (CKs) parameter tZQI = 128_000_000, // ZQCS interval (ps) parameter tPRDI = 1_000_000, // pS parameter USER_REFRESH = "OFF" // Whether user manages REF ) ( // System inputs input clk, input rst, // Physical memory slot presence input [7:0] slot_0_present, input [7:0] slot_1_present, // Native Interface input [2:0] cmd, input [DATA_BUF_ADDR_WIDTH-1:0] data_buf_addr, input hi_priority, input size, input [BANK_WIDTH-1:0] bank, input [COL_WIDTH-1:0] col, input [RANK_WIDTH-1:0] rank, input [ROW_WIDTH-1:0] row, input use_addr, input [2*nCK_PER_CLK*PAYLOAD_WIDTH-1:0] wr_data, input [2*nCK_PER_CLK*DATA_WIDTH/8-1:0] wr_data_mask, output accept, output accept_ns, output [BM_CNT_WIDTH-1:0] bank_mach_next, output wire [2*nCK_PER_CLK*PAYLOAD_WIDTH-1:0] rd_data, output [DATA_BUF_ADDR_WIDTH-1:0] rd_data_addr, output rd_data_en, output rd_data_end, output [DATA_BUF_OFFSET_WIDTH-1:0] rd_data_offset, output reg [DATA_BUF_ADDR_WIDTH-1:0] wr_data_addr /* synthesis syn_maxfan = 30 */, output reg wr_data_en, output reg [DATA_BUF_OFFSET_WIDTH-1:0] wr_data_offset /* synthesis syn_maxfan = 30 */, output mc_read_idle, output mc_ref_zq_wip, // ECC interface input correct_en, input [2*nCK_PER_CLK-1:0] raw_not_ecc, input [DQS_WIDTH - 1:0] fi_xor_we, input [DQ_WIDTH -1 :0 ] fi_xor_wrdata, output [MC_ERR_ADDR_WIDTH-1:0] ecc_err_addr, output [2*nCK_PER_CLK-1:0] ecc_single, output [2*nCK_PER_CLK-1:0] ecc_multiple, // User maintenance requests input app_periodic_rd_req, input app_ref_req, input app_zq_req, input app_sr_req, output app_sr_active, output app_ref_ack, output app_zq_ack, // MC <==> PHY Interface output reg [nCK_PER_CLK-1:0] mc_ras_n, output reg [nCK_PER_CLK-1:0] mc_cas_n, output reg [nCK_PER_CLK-1:0] mc_we_n, output reg [nCK_PER_CLK*ROW_WIDTH-1:0] mc_address, output reg [nCK_PER_CLK*BANK_WIDTH-1:0] mc_bank, output reg [CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK-1:0] mc_cs_n, output reg [1:0] mc_odt, output reg [nCK_PER_CLK-1:0] mc_cke, output wire mc_reset_n, output wire [2*nCK_PER_CLK*DQ_WIDTH-1:0] mc_wrdata, output wire [2*nCK_PER_CLK*DQ_WIDTH/8-1:0]mc_wrdata_mask, output reg mc_wrdata_en, output wire mc_cmd_wren, output wire mc_ctl_wren, output reg [2:0] mc_cmd, output reg [5:0] mc_data_offset, output reg [5:0] mc_data_offset_1, output reg [5:0] mc_data_offset_2, output reg [1:0] mc_cas_slot, output reg [3:0] mc_aux_out0, output reg [3:0] mc_aux_out1, output reg [1:0] mc_rank_cnt, input phy_mc_ctl_full, input phy_mc_cmd_full, input phy_mc_data_full, input [2*nCK_PER_CLK*DQ_WIDTH-1:0] phy_rd_data, input phy_rddata_valid, input init_calib_complete, input [6*RANKS-1:0] calib_rd_data_offset, input [6*RANKS-1:0] calib_rd_data_offset_1, input [6*RANKS-1:0] calib_rd_data_offset_2 ); assign mc_reset_n = 1'b1; // never reset memory assign mc_cmd_wren = 1'b1; // always write CMD FIFO(issue DSEL when idle) assign mc_ctl_wren = 1'b1; // always write CTL FIFO(issue nondata when idle) // Ensure there is always at least one rank present during operation `ifdef MC_SVA ranks_present: assert property (@(posedge clk) (rst || (|(slot_0_present | slot_1_present)))); `endif // Reserved. Do not change. localparam nPHY_WRLAT = 2; // always delay write data control unless ECC mode is enabled localparam DELAY_WR_DATA_CNTRL = ECC == "ON" ? 0 : 1; // Ensure that write control is delayed for appropriate CWL /*`ifdef MC_SVA delay_wr_data_zero_CWL_le_6: assert property (@(posedge clk) ((CWL > 6) || (DELAY_WR_DATA_CNTRL == 0))); `endif*/ // Never retrieve WR_DATA_ADDR early localparam EARLY_WR_DATA_ADDR = "OFF"; //*************************************************************************** // Convert timing parameters from time to clock cycles //*************************************************************************** localparam nCKE = cdiv(tCKE, tCK); localparam nRP = cdiv(tRP, tCK); localparam nRCD = cdiv(tRCD, tCK); localparam nRAS = cdiv(tRAS, tCK); localparam nFAW = cdiv(tFAW, tCK); localparam nRFC = cdiv(tRFC, tCK); // Convert tWR. As per specification, write recover for autoprecharge // cycles doesn't support values of 9 and 11. Round up 9 to 10 and 11 to 12 localparam nWR_CK = cdiv(15000, tCK) ; localparam nWR = (nWR_CK == 9) ? 10 : (nWR_CK == 11) ? 12 : nWR_CK; // tRRD, tWTR at tRTP have a 4 cycle floor in DDR3 and 2 cycle floor in DDR2 localparam nRRD_CK = cdiv(tRRD, tCK); localparam nRRD = (DRAM_TYPE == "DDR3") ? (nRRD_CK < 4) ? 4 : nRRD_CK : (nRRD_CK < 2) ? 2 : nRRD_CK; localparam nWTR_CK = cdiv(tWTR, tCK); localparam nWTR = (DRAM_TYPE == "DDR3") ? (nWTR_CK < 4) ? 4 : nWTR_CK : (nWTR_CK < 2) ? 2 : nWTR_CK; localparam nRTP_CK = cdiv(tRTP, tCK); localparam nRTP = (DRAM_TYPE == "DDR3") ? (nRTP_CK < 4) ? 4 : nRTP_CK : (nRTP_CK < 2) ? 2 : nRTP_CK; // Add a cycle to CL/CWL for the register in RDIMM devices localparam CWL_M = (REG_CTRL == "ON") ? CWL + 1 : CWL; localparam CL_M = (REG_CTRL == "ON") ? CL + 1 : CL; // Tuneable delay between read and write data on the DQ bus localparam DQRD2DQWR_DLY = 4; // CKE minimum pulse width for self-refresh (SRE->SRX minimum time) localparam nCKESR = nCKE + 1; // Delay from SRE to command requiring locked DLL. Currently fixed at 512 for // all devices per JEDEC spec. localparam tXSDLL = 512; //*************************************************************************** // Set up maintenance counter dividers //*************************************************************************** // CK clock divisor to generate maintenance prescaler period (round down) localparam MAINT_PRESCALER_DIV = MAINT_PRESCALER_PERIOD / (tCK*nCK_PER_CLK); // Maintenance prescaler divisor for refresh timer. Essentially, this is // just (tREFI / MAINT_PRESCALER_PERIOD), but we must account for the worst // case delay from the time we get a tick from the refresh counter to the // time that we can actually issue the REF command. Thus, subtract tRCD, CL, // data burst time and tRP for each implemented bank machine to ensure that // all transactions can complete before tREFI expires localparam REFRESH_TIMER_DIV = USER_REFRESH == "ON" ? 0 : (tREFI-((tRCD+((CL+4)*tCK)+tRP)*nBANK_MACHS)) / MAINT_PRESCALER_PERIOD; // Periodic read (RESERVED - not currently required or supported in 7 series) // tPRDI should only be set to 0 // localparam tPRDI = 0; // Do NOT change. localparam PERIODIC_RD_TIMER_DIV = tPRDI / MAINT_PRESCALER_PERIOD; // Convert maintenance prescaler from ps to ns localparam MAINT_PRESCALER_PERIOD_NS = MAINT_PRESCALER_PERIOD / 1000; // Maintenance prescaler divisor for ZQ calibration (ZQCS) timer localparam ZQ_TIMER_DIV = tZQI / MAINT_PRESCALER_PERIOD_NS; // Bus width required to broadcast a single bit rank signal among all the // bank machines - 1 bit per rank, per bank localparam RANK_BM_BV_WIDTH = nBANK_MACHS * RANKS; //*************************************************************************** // Define 2T, CWL-even mode to enable multi-fabric-cycle 2T commands //*************************************************************************** localparam EVEN_CWL_2T_MODE = ((ADDR_CMD_MODE == "2T") && (!(CWL % 2))) ? "ON" : "OFF"; //*************************************************************************** // Reserved feature control. //*************************************************************************** // Open page wait mode is reserved. // nOP_WAIT is the number of states a bank machine will park itself // on an otherwise inactive open page before closing the page. If // nOP_WAIT == 0, open page wait mode is disabled. If nOP_WAIT == -1, // the bank machine will remain parked until the pool of idle bank machines // are less than LOW_IDLE_CNT. At which point parked bank machines // are selected to exit until the number of idle bank machines exceeds the // LOW_IDLE_CNT. localparam nOP_WAIT = 0; // Open page mode localparam LOW_IDLE_CNT = 0; // Low idle bank machine threshold //*************************************************************************** // Internal wires //*************************************************************************** wire [RANK_BM_BV_WIDTH-1:0] act_this_rank_r; wire [ROW_WIDTH-1:0] col_a; wire [BANK_WIDTH-1:0] col_ba; wire [DATA_BUF_ADDR_WIDTH-1:0] col_data_buf_addr; wire col_periodic_rd; wire [RANK_WIDTH-1:0] col_ra; wire col_rmw; wire col_rd_wr; wire [ROW_WIDTH-1:0] col_row; wire col_size; wire [DATA_BUF_ADDR_WIDTH-1:0] col_wr_data_buf_addr; wire dq_busy_data; wire ecc_status_valid; wire [RANKS-1:0] inhbt_act_faw_r; wire [RANKS-1:0] inhbt_rd; wire [RANKS-1:0] inhbt_wr; wire insert_maint_r1; wire [RANK_WIDTH-1:0] maint_rank_r; wire maint_req_r; wire maint_wip_r; wire maint_zq_r; wire maint_sre_r; wire maint_srx_r; wire periodic_rd_ack_r; wire periodic_rd_r; wire [RANK_WIDTH-1:0] periodic_rd_rank_r; wire [(RANKS*nBANK_MACHS)-1:0] rank_busy_r; wire rd_rmw; wire [RANK_BM_BV_WIDTH-1:0] rd_this_rank_r; wire [nBANK_MACHS-1:0] sending_col; wire [nBANK_MACHS-1:0] sending_row; wire sent_col; wire sent_col_r; wire wr_ecc_buf; wire [RANK_BM_BV_WIDTH-1:0] wr_this_rank_r; // MC/PHY optional pipeline stage support wire [nCK_PER_CLK-1:0] mc_ras_n_ns; wire [nCK_PER_CLK-1:0] mc_cas_n_ns; wire [nCK_PER_CLK-1:0] mc_we_n_ns; wire [nCK_PER_CLK*ROW_WIDTH-1:0] mc_address_ns; wire [nCK_PER_CLK*BANK_WIDTH-1:0] mc_bank_ns; wire [CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK-1:0] mc_cs_n_ns; wire [1:0] mc_odt_ns; wire [nCK_PER_CLK-1:0] mc_cke_ns; wire [3:0] mc_aux_out0_ns; wire [3:0] mc_aux_out1_ns; wire [1:0] mc_rank_cnt_ns = col_ra; wire [2:0] mc_cmd_ns; wire [5:0] mc_data_offset_ns; wire [5:0] mc_data_offset_1_ns; wire [5:0] mc_data_offset_2_ns; wire [1:0] mc_cas_slot_ns; wire mc_wrdata_en_ns; wire [DATA_BUF_ADDR_WIDTH-1:0] wr_data_addr_ns; wire wr_data_en_ns; wire [DATA_BUF_OFFSET_WIDTH-1:0] wr_data_offset_ns; integer i; // MC Read idle support wire col_read_fifo_empty; wire mc_read_idle_ns; reg mc_read_idle_r; // MC Maintenance in progress with bus idle indication wire maint_ref_zq_wip; wire mc_ref_zq_wip_ns; reg mc_ref_zq_wip_r; //*************************************************************************** // Function cdiv // Description: // This function performs ceiling division (divide and round-up) // Inputs: // num: integer to be divided // div: divisor // Outputs: // cdiv: result of ceiling division (num/div, rounded up) //*************************************************************************** function integer cdiv (input integer num, input integer div); begin // perform division, then add 1 if and only if remainder is non-zero cdiv = (num/div) + (((num%div)>0) ? 1 : 0); end endfunction // cdiv //*************************************************************************** // Optional pipeline register stage on MC/PHY interface //*************************************************************************** generate if (CMD_PIPE_PLUS1 == "ON") begin : cmd_pipe_plus // register interface always @(posedge clk) begin mc_address <= #TCQ mc_address_ns; mc_bank <= #TCQ mc_bank_ns; mc_cas_n <= #TCQ mc_cas_n_ns; mc_cs_n <= #TCQ mc_cs_n_ns; mc_odt <= #TCQ mc_odt_ns; mc_cke <= #TCQ mc_cke_ns; mc_aux_out0 <= #TCQ mc_aux_out0_ns; mc_aux_out1 <= #TCQ mc_aux_out1_ns; mc_cmd <= #TCQ mc_cmd_ns; mc_ras_n <= #TCQ mc_ras_n_ns; mc_we_n <= #TCQ mc_we_n_ns; mc_data_offset <= #TCQ mc_data_offset_ns; mc_data_offset_1 <= #TCQ mc_data_offset_1_ns; mc_data_offset_2 <= #TCQ mc_data_offset_2_ns; mc_cas_slot <= #TCQ mc_cas_slot_ns; mc_wrdata_en <= #TCQ mc_wrdata_en_ns; mc_rank_cnt <= #TCQ mc_rank_cnt_ns; wr_data_addr <= #TCQ wr_data_addr_ns; wr_data_en <= #TCQ wr_data_en_ns; wr_data_offset <= #TCQ wr_data_offset_ns; end // always @ (posedge clk) end // block: cmd_pipe_plus else begin : cmd_pipe_plus0 // don't register interface always @( mc_address_ns or mc_aux_out0_ns or mc_aux_out1_ns or mc_bank_ns or mc_cas_n_ns or mc_cmd_ns or mc_cs_n_ns or mc_odt_ns or mc_cke_ns or mc_data_offset_ns or mc_data_offset_1_ns or mc_data_offset_2_ns or mc_rank_cnt_ns or mc_ras_n_ns or mc_we_n_ns or mc_wrdata_en_ns or wr_data_addr_ns or wr_data_en_ns or wr_data_offset_ns or mc_cas_slot_ns) begin mc_address = #TCQ mc_address_ns; mc_bank = #TCQ mc_bank_ns; mc_cas_n = #TCQ mc_cas_n_ns; mc_cs_n = #TCQ mc_cs_n_ns; mc_odt = #TCQ mc_odt_ns; mc_cke = #TCQ mc_cke_ns; mc_aux_out0 = #TCQ mc_aux_out0_ns; mc_aux_out1 = #TCQ mc_aux_out1_ns; mc_cmd = #TCQ mc_cmd_ns; mc_ras_n = #TCQ mc_ras_n_ns; mc_we_n = #TCQ mc_we_n_ns; mc_data_offset = #TCQ mc_data_offset_ns; mc_data_offset_1 = #TCQ mc_data_offset_1_ns; mc_data_offset_2 = #TCQ mc_data_offset_2_ns; mc_cas_slot = #TCQ mc_cas_slot_ns; mc_wrdata_en = #TCQ mc_wrdata_en_ns; mc_rank_cnt = #TCQ mc_rank_cnt_ns; wr_data_addr = #TCQ wr_data_addr_ns; wr_data_en = #TCQ wr_data_en_ns; wr_data_offset = #TCQ wr_data_offset_ns; end // always @ (... end // block: cmd_pipe_plus0 endgenerate //*************************************************************************** // Indicate when there are no pending reads so that input features can be // powered down //*************************************************************************** assign mc_read_idle_ns = col_read_fifo_empty & init_calib_complete; always @(posedge clk) mc_read_idle_r <= #TCQ mc_read_idle_ns; assign mc_read_idle = mc_read_idle_r; //*************************************************************************** // Indicate when there is a refresh in progress and the bus is idle so that // tap adjustments can be made //*************************************************************************** assign mc_ref_zq_wip_ns = maint_ref_zq_wip && col_read_fifo_empty; always @(posedge clk) mc_ref_zq_wip_r <= mc_ref_zq_wip_ns; assign mc_ref_zq_wip = mc_ref_zq_wip_r; //*************************************************************************** // Manage rank-level timing and maintanence //*************************************************************************** mig_7series_v2_0_rank_mach # ( // Parameters .BURST_MODE (BURST_MODE), .CL (CL), .CWL (CWL), .CS_WIDTH (CS_WIDTH), .DQRD2DQWR_DLY (DQRD2DQWR_DLY), .DRAM_TYPE (DRAM_TYPE), .MAINT_PRESCALER_DIV (MAINT_PRESCALER_DIV), .nBANK_MACHS (nBANK_MACHS), .nCKESR (nCKESR), .nCK_PER_CLK (nCK_PER_CLK), .nFAW (nFAW), .nREFRESH_BANK (nREFRESH_BANK), .nRRD (nRRD), .nWTR (nWTR), .PERIODIC_RD_TIMER_DIV (PERIODIC_RD_TIMER_DIV), .RANK_BM_BV_WIDTH (RANK_BM_BV_WIDTH), .RANK_WIDTH (RANK_WIDTH), .RANKS (RANKS), .REFRESH_TIMER_DIV (REFRESH_TIMER_DIV), .ZQ_TIMER_DIV (ZQ_TIMER_DIV) ) rank_mach0 ( // Outputs .inhbt_act_faw_r (inhbt_act_faw_r[RANKS-1:0]), .inhbt_rd (inhbt_rd[RANKS-1:0]), .inhbt_wr (inhbt_wr[RANKS-1:0]), .maint_rank_r (maint_rank_r[RANK_WIDTH-1:0]), .maint_req_r (maint_req_r), .maint_zq_r (maint_zq_r), .maint_sre_r (maint_sre_r), .maint_srx_r (maint_srx_r), .maint_ref_zq_wip (maint_ref_zq_wip), .periodic_rd_r (periodic_rd_r), .periodic_rd_rank_r (periodic_rd_rank_r[RANK_WIDTH-1:0]), // Inputs .act_this_rank_r (act_this_rank_r[RANK_BM_BV_WIDTH-1:0]), .app_periodic_rd_req (app_periodic_rd_req), .app_ref_req (app_ref_req), .app_ref_ack (app_ref_ack), .app_zq_req (app_zq_req), .app_zq_ack (app_zq_ack), .app_sr_req (app_sr_req), .app_sr_active (app_sr_active), .col_rd_wr (col_rd_wr), .clk (clk), .init_calib_complete (init_calib_complete), .insert_maint_r1 (insert_maint_r1), .maint_wip_r (maint_wip_r), .periodic_rd_ack_r (periodic_rd_ack_r), .rank_busy_r (rank_busy_r[(RANKS*nBANK_MACHS)-1:0]), .rd_this_rank_r (rd_this_rank_r[RANK_BM_BV_WIDTH-1:0]), .rst (rst), .sending_col (sending_col[nBANK_MACHS-1:0]), .sending_row (sending_row[nBANK_MACHS-1:0]), .slot_0_present (slot_0_present[7:0]), .slot_1_present (slot_1_present[7:0]), .wr_this_rank_r (wr_this_rank_r[RANK_BM_BV_WIDTH-1:0]) ); //*************************************************************************** // Manage requests, reordering and bank timing //*************************************************************************** mig_7series_v2_0_bank_mach # ( // Parameters .TCQ (TCQ), .EVEN_CWL_2T_MODE (EVEN_CWL_2T_MODE), .ADDR_CMD_MODE (ADDR_CMD_MODE), .BANK_WIDTH (BANK_WIDTH), .BM_CNT_WIDTH (BM_CNT_WIDTH), .BURST_MODE (BURST_MODE), .COL_WIDTH (COL_WIDTH), .CS_WIDTH (CS_WIDTH), .CL (CL_M), .CWL (CWL_M), .CKE_ODT_AUX (CKE_ODT_AUX), .DATA_BUF_ADDR_WIDTH (DATA_BUF_ADDR_WIDTH), .DRAM_TYPE (DRAM_TYPE), .EARLY_WR_DATA_ADDR (EARLY_WR_DATA_ADDR), .ECC (ECC), .LOW_IDLE_CNT (LOW_IDLE_CNT), .nBANK_MACHS (nBANK_MACHS), .nCK_PER_CLK (nCK_PER_CLK), .nCS_PER_RANK (nCS_PER_RANK), .nOP_WAIT (nOP_WAIT), .nRAS (nRAS), .nRCD (nRCD), .nRFC (nRFC), .nRP (nRP), .nRTP (nRTP), .nSLOTS (nSLOTS), .nWR (nWR), .nXSDLL (tXSDLL), .ORDERING (ORDERING), .RANK_BM_BV_WIDTH (RANK_BM_BV_WIDTH), .RANK_WIDTH (RANK_WIDTH), .RANKS (RANKS), .ROW_WIDTH (ROW_WIDTH), .RTT_NOM (RTT_NOM), .RTT_WR (RTT_WR), .SLOT_0_CONFIG (SLOT_0_CONFIG), .SLOT_1_CONFIG (SLOT_1_CONFIG), .STARVE_LIMIT (STARVE_LIMIT), .tZQCS (tZQCS) ) bank_mach0 ( // Outputs .accept (accept), .accept_ns (accept_ns), .act_this_rank_r (act_this_rank_r[RANK_BM_BV_WIDTH-1:0]), .bank_mach_next (bank_mach_next[BM_CNT_WIDTH-1:0]), .col_a (col_a[ROW_WIDTH-1:0]), .col_ba (col_ba[BANK_WIDTH-1:0]), .col_data_buf_addr (col_data_buf_addr[DATA_BUF_ADDR_WIDTH-1:0]), .col_periodic_rd (col_periodic_rd), .col_ra (col_ra[RANK_WIDTH-1:0]), .col_rmw (col_rmw), .col_rd_wr (col_rd_wr), .col_row (col_row[ROW_WIDTH-1:0]), .col_size (col_size), .col_wr_data_buf_addr (col_wr_data_buf_addr[DATA_BUF_ADDR_WIDTH-1:0]), .mc_bank (mc_bank_ns), .mc_address (mc_address_ns), .mc_ras_n (mc_ras_n_ns), .mc_cas_n (mc_cas_n_ns), .mc_we_n (mc_we_n_ns), .mc_cs_n (mc_cs_n_ns), .mc_odt (mc_odt_ns), .mc_cke (mc_cke_ns), .mc_aux_out0 (mc_aux_out0_ns), .mc_aux_out1 (mc_aux_out1_ns), .mc_cmd (mc_cmd_ns), .mc_data_offset (mc_data_offset_ns), .mc_data_offset_1 (mc_data_offset_1_ns), .mc_data_offset_2 (mc_data_offset_2_ns), .mc_cas_slot (mc_cas_slot_ns), .insert_maint_r1 (insert_maint_r1), .maint_wip_r (maint_wip_r), .periodic_rd_ack_r (periodic_rd_ack_r), .rank_busy_r (rank_busy_r[(RANKS*nBANK_MACHS)-1:0]), .rd_this_rank_r (rd_this_rank_r[RANK_BM_BV_WIDTH-1:0]), .sending_row (sending_row[nBANK_MACHS-1:0]), .sending_col (sending_col[nBANK_MACHS-1:0]), .sent_col (sent_col), .sent_col_r (sent_col_r), .wr_this_rank_r (wr_this_rank_r[RANK_BM_BV_WIDTH-1:0]), // Inputs .bank (bank[BANK_WIDTH-1:0]), .calib_rddata_offset (calib_rd_data_offset), .calib_rddata_offset_1 (calib_rd_data_offset_1), .calib_rddata_offset_2 (calib_rd_data_offset_2), .clk (clk), .cmd (cmd[2:0]), .col (col[COL_WIDTH-1:0]), .data_buf_addr (data_buf_addr[DATA_BUF_ADDR_WIDTH-1:0]), .init_calib_complete (init_calib_complete), .phy_rddata_valid (phy_rddata_valid), .dq_busy_data (dq_busy_data), .hi_priority (hi_priority), .inhbt_act_faw_r (inhbt_act_faw_r[RANKS-1:0]), .inhbt_rd (inhbt_rd[RANKS-1:0]), .inhbt_wr (inhbt_wr[RANKS-1:0]), .maint_rank_r (maint_rank_r[RANK_WIDTH-1:0]), .maint_req_r (maint_req_r), .maint_zq_r (maint_zq_r), .maint_sre_r (maint_sre_r), .maint_srx_r (maint_srx_r), .periodic_rd_r (periodic_rd_r), .periodic_rd_rank_r (periodic_rd_rank_r[RANK_WIDTH-1:0]), .phy_mc_cmd_full (phy_mc_cmd_full), .phy_mc_ctl_full (phy_mc_ctl_full), .phy_mc_data_full (phy_mc_data_full), .rank (rank[RANK_WIDTH-1:0]), .rd_data_addr (rd_data_addr[DATA_BUF_ADDR_WIDTH-1:0]), .rd_rmw (rd_rmw), .row (row[ROW_WIDTH-1:0]), .rst (rst), .size (size), .slot_0_present (slot_0_present[7:0]), .slot_1_present (slot_1_present[7:0]), .use_addr (use_addr) ); //*************************************************************************** // Manage DQ bus //*************************************************************************** mig_7series_v2_0_col_mach # ( // Parameters .TCQ (TCQ), .BANK_WIDTH (BANK_WIDTH), .BURST_MODE (BURST_MODE), .COL_WIDTH (COL_WIDTH), .CS_WIDTH (CS_WIDTH), .DATA_BUF_ADDR_WIDTH (DATA_BUF_ADDR_WIDTH), .DATA_BUF_OFFSET_WIDTH (DATA_BUF_OFFSET_WIDTH), .DELAY_WR_DATA_CNTRL (DELAY_WR_DATA_CNTRL), .DQS_WIDTH (DQS_WIDTH), .DRAM_TYPE (DRAM_TYPE), .EARLY_WR_DATA_ADDR (EARLY_WR_DATA_ADDR), .ECC (ECC), .MC_ERR_ADDR_WIDTH (MC_ERR_ADDR_WIDTH), .nCK_PER_CLK (nCK_PER_CLK), .nPHY_WRLAT (nPHY_WRLAT), .RANK_WIDTH (RANK_WIDTH), .ROW_WIDTH (ROW_WIDTH) ) col_mach0 ( // Outputs .mc_wrdata_en (mc_wrdata_en_ns), .dq_busy_data (dq_busy_data), .ecc_err_addr (ecc_err_addr[MC_ERR_ADDR_WIDTH-1:0]), .ecc_status_valid (ecc_status_valid), .rd_data_addr (rd_data_addr[DATA_BUF_ADDR_WIDTH-1:0]), .rd_data_en (rd_data_en), .rd_data_end (rd_data_end), .rd_data_offset (rd_data_offset), .rd_rmw (rd_rmw), .wr_data_addr (wr_data_addr_ns), .wr_data_en (wr_data_en_ns), .wr_data_offset (wr_data_offset_ns), .wr_ecc_buf (wr_ecc_buf), .col_read_fifo_empty (col_read_fifo_empty), // Inputs .clk (clk), .rst (rst), .col_a (col_a[ROW_WIDTH-1:0]), .col_ba (col_ba[BANK_WIDTH-1:0]), .col_data_buf_addr (col_data_buf_addr[DATA_BUF_ADDR_WIDTH-1:0]), .col_periodic_rd (col_periodic_rd), .col_ra (col_ra[RANK_WIDTH-1:0]), .col_rmw (col_rmw), .col_rd_wr (col_rd_wr), .col_row (col_row[ROW_WIDTH-1:0]), .col_size (col_size), .col_wr_data_buf_addr (col_wr_data_buf_addr[DATA_BUF_ADDR_WIDTH-1:0]), .phy_rddata_valid (phy_rddata_valid), .sent_col (EVEN_CWL_2T_MODE == "ON" ? sent_col_r : sent_col) ); //*************************************************************************** // Implement ECC //*************************************************************************** // Total ECC word length = ECC code width + Data width localparam CODE_WIDTH = DATA_WIDTH + ECC_WIDTH; generate if (ECC == "OFF") begin : ecc_off assign rd_data = phy_rd_data; assign mc_wrdata = wr_data; assign mc_wrdata_mask = wr_data_mask; assign ecc_single = 4'b0; assign ecc_multiple = 4'b0; end else begin : ecc_on wire [CODE_WIDTH*ECC_WIDTH-1:0] h_rows; wire [2*nCK_PER_CLK*DATA_WIDTH-1:0] rd_merge_data; wire [2*nCK_PER_CLK*DQ_WIDTH-1:0] mc_wrdata_i; // Merge and encode mig_7series_v2_0_ecc_merge_enc # ( // Parameters .TCQ (TCQ), .CODE_WIDTH (CODE_WIDTH), .DATA_BUF_ADDR_WIDTH (DATA_BUF_ADDR_WIDTH), .DATA_WIDTH (DATA_WIDTH), .DQ_WIDTH (DQ_WIDTH), .ECC_WIDTH (ECC_WIDTH), .PAYLOAD_WIDTH (PAYLOAD_WIDTH), .nCK_PER_CLK (nCK_PER_CLK) ) ecc_merge_enc0 ( // Outputs .mc_wrdata (mc_wrdata_i), .mc_wrdata_mask (mc_wrdata_mask), // Inputs .clk (clk), .rst (rst), .h_rows (h_rows), .rd_merge_data (rd_merge_data), .raw_not_ecc (raw_not_ecc), .wr_data (wr_data), .wr_data_mask (wr_data_mask) ); // Decode and fix mig_7series_v2_0_ecc_dec_fix # ( // Parameters .TCQ (TCQ), .CODE_WIDTH (CODE_WIDTH), .DATA_WIDTH (DATA_WIDTH), .DQ_WIDTH (DQ_WIDTH), .ECC_WIDTH (ECC_WIDTH), .PAYLOAD_WIDTH (PAYLOAD_WIDTH), .nCK_PER_CLK (nCK_PER_CLK) ) ecc_dec_fix0 ( // Outputs .ecc_multiple (ecc_multiple), .ecc_single (ecc_single), .rd_data (rd_data), // Inputs .clk (clk), .rst (rst), .correct_en (correct_en), .phy_rddata (phy_rd_data), .ecc_status_valid (ecc_status_valid), .h_rows (h_rows) ); // ECC Buffer mig_7series_v2_0_ecc_buf # ( // Parameters .TCQ (TCQ), .DATA_BUF_ADDR_WIDTH (DATA_BUF_ADDR_WIDTH), .DATA_BUF_OFFSET_WIDTH (DATA_BUF_OFFSET_WIDTH), .DATA_WIDTH (DATA_WIDTH), .PAYLOAD_WIDTH (PAYLOAD_WIDTH), .nCK_PER_CLK (nCK_PER_CLK) ) ecc_buf0 ( // Outputs .rd_merge_data (rd_merge_data), // Inputs .clk (clk), .rst (rst), .rd_data (rd_data), .rd_data_addr (rd_data_addr), .rd_data_offset (rd_data_offset), .wr_data_addr (wr_data_addr), .wr_data_offset (wr_data_offset), .wr_ecc_buf (wr_ecc_buf) ); // Generate ECC table mig_7series_v2_0_ecc_gen # ( // Parameters .CODE_WIDTH (CODE_WIDTH), .DATA_WIDTH (DATA_WIDTH), .ECC_WIDTH (ECC_WIDTH) ) ecc_gen0 ( // Outputs .h_rows (h_rows) ); if (ECC == "ON") begin : gen_fi_xor_inst reg mc_wrdata_en_r; wire mc_wrdata_en_i; always @(posedge clk) begin mc_wrdata_en_r <= mc_wrdata_en; end assign mc_wrdata_en_i = mc_wrdata_en_r; mig_7series_v2_0_fi_xor #( .DQ_WIDTH (DQ_WIDTH), .DQS_WIDTH (DQS_WIDTH), .nCK_PER_CLK (nCK_PER_CLK) ) fi_xor0 ( .clk (clk), .wrdata_in (mc_wrdata_i), .wrdata_out (mc_wrdata), .wrdata_en (mc_wrdata_en_i), .fi_xor_we (fi_xor_we), .fi_xor_wrdata (fi_xor_wrdata) ); end else begin : gen_wrdata_passthru assign mc_wrdata = mc_wrdata_i; end `ifdef DISPLAY_H_MATRIX integer i; always @(negedge rst) begin $display ("**********************************************"); $display ("H Matrix:"); for (i=0; i<ECC_WIDTH; i=i+1) $display ("%b", h_rows[i*CODE_WIDTH+:CODE_WIDTH]); $display ("**********************************************"); end `endif end endgenerate endmodule
module sky130_fd_sc_hs__dfbbp ( Q , Q_N , D , CLK , SET_B , RESET_B ); output Q ; output Q_N ; input D ; input CLK ; input SET_B ; input RESET_B; // Voltage supply signals supply1 VPWR; supply0 VGND; endmodule
module controllerHdl_MATLAB_Function ( u, y ); input [35:0] u; // ufix36 output [17:0] y; // ufix18 //MATLAB Function 'Encoder_To_Position_And_Velocity/Rotor_To_Electrical_Position/Mod_2pi_Scale_And_Bit_Slice/Mark_Extract_Bits/MATLAB Function': '<S13>:1' // Non-tunable mask parameter //'<S13>:1:8' //'<S13>:1:10' assign y = u[17:0]; //'<S13>:1:14' endmodule
module AFU #(parameter AFU_OPERATOR = `UNDEF_AFU, // AFU Common parameters parameter MAX_AFU_CONFIG_WIDTH = 1536, parameter USER_RD_TAG = `AFU_TAG, parameter USER_WR_TAG = `AFU_TAG, //------ AFU Specific Paramters ----// parameter DATA_WIDTH_IN = 4, parameter DATA_WIDTH_OUT = 4, parameter USER_AFU_PARAMETER1 = 1, parameter USER_AFU_PARAMETER2 = 1 ) ( input wire clk, input wire Clk_400, input wire rst_n, //-------------------------------------------------// input wire start_um, input wire [MAX_AFU_CONFIG_WIDTH-1:0] um_params, output wire um_done, output wire [`NUM_USER_STATE_COUNTERS*32-1:0] um_state_counters, output wire um_state_counters_valid, // TX RD output wire [57:0] um_tx_rd_addr, output wire [USER_RD_TAG-1:0] um_tx_rd_tag, output wire um_tx_rd_valid, input wire um_tx_rd_ready, // TX WR output wire [57:0] um_tx_wr_addr, output wire [USER_WR_TAG-1:0] um_tx_wr_tag, output wire um_tx_wr_valid, output wire [511:0] um_tx_data, input wire um_tx_wr_ready, // RX RD input wire [USER_RD_TAG-1:0] um_rx_rd_tag, input wire [511:0] um_rx_data, input wire um_rx_rd_valid, output wire um_rx_rd_ready, // RX WR input wire um_rx_wr_valid, input wire [USER_WR_TAG-1:0] um_rx_wr_tag ); generate if (AFU_OPERATOR == `REGEX_AFU) begin regex_mdb regex_mdb( .clk (clk), .Clk_400 (Clk_400), .rst_n (rst_n), //-------------------------------------------------// .start_um (start_um), .um_params (um_params[1023:0]), .um_done (um_done), .um_state_counters (um_state_counters), .um_state_counters_valid (um_state_counters_valid), // User Module TX RD .um_tx_rd_addr (um_tx_rd_addr), .um_tx_rd_tag (um_tx_rd_tag), .um_tx_rd_valid (um_tx_rd_valid), .um_tx_rd_ready (um_tx_rd_ready), // User Module TX WR .um_tx_wr_addr (um_tx_wr_addr), .um_tx_wr_tag (um_tx_wr_tag), .um_tx_wr_valid (um_tx_wr_valid), .um_tx_data (um_tx_data), .um_tx_wr_ready (um_tx_wr_ready), // User Module RX RD .um_rx_rd_tag (um_rx_rd_tag), .um_rx_data (um_rx_data), .um_rx_rd_valid (um_rx_rd_valid), .um_rx_rd_ready (um_rx_rd_ready), // User Module RX WR .um_rx_wr_valid (um_rx_wr_valid), .um_rx_wr_tag (um_rx_wr_tag) ); end else if ((AFU_OPERATOR == `SKYLINE256_AFU) | (AFU_OPERATOR == `SKYLINE128_AFU) | (AFU_OPERATOR == `SKYLINE64_AFU) ) begin skyline #(.NUM_CORES(USER_AFU_PARAMETER1), .NUM_DIMENSIONS(USER_AFU_PARAMETER2)) skyline_0( .clk (clk), .rst_n (rst_n), //-------------------------------------------------// .start_um (start_um), .um_params (um_params[1535:0]), .um_done (um_done), .um_state_counters (um_state_counters), .um_state_counters_valid (um_state_counters_valid), // User Module TX RD .um_tx_rd_addr (um_tx_rd_addr), .um_tx_rd_tag (um_tx_rd_tag), .um_tx_rd_valid (um_tx_rd_valid), .um_tx_rd_ready (um_tx_rd_ready), // User Module TX WR .um_tx_wr_addr (um_tx_wr_addr), .um_tx_wr_tag (um_tx_wr_tag), .um_tx_wr_valid (um_tx_wr_valid), .um_tx_data (um_tx_data), .um_tx_wr_ready (um_tx_wr_ready), // User Module RX RD .um_rx_rd_tag (um_rx_rd_tag), .um_rx_data (um_rx_data), .um_rx_rd_valid (um_rx_rd_valid), .um_rx_rd_ready (um_rx_rd_ready), // User Module RX WR .um_rx_wr_valid (um_rx_wr_valid), .um_rx_wr_tag (um_rx_wr_tag) ); end else if (AFU_OPERATOR == `COPY32_AFU) begin copy copy ( .clk (clk), .rst_n (rst_n), //-------------------------------------------------// .start_um (start_um), .um_params (um_params[511:0]), .um_done (um_done), // User Module TX RD .um_tx_rd_addr (um_tx_rd_addr), .um_tx_rd_tag (um_tx_rd_tag), .um_tx_rd_valid (um_tx_rd_valid), .um_tx_rd_ready (um_tx_rd_ready), // User Module TX WR .um_tx_wr_addr (um_tx_wr_addr), .um_tx_wr_tag (um_tx_wr_tag), .um_tx_wr_valid (um_tx_wr_valid), .um_tx_data (um_tx_data), .um_tx_wr_ready (um_tx_wr_ready), // User Module RX RD .um_rx_rd_tag (um_rx_rd_tag), .um_rx_data (um_rx_data), .um_rx_rd_valid (um_rx_rd_valid), .um_rx_rd_ready (um_rx_rd_ready), // User Module RX WR .um_rx_wr_valid (um_rx_wr_valid), .um_rx_wr_tag (um_rx_wr_tag) ); assign um_state_counters_valid = 1'b0; end else if (AFU_OPERATOR == `TEST_AND_COUNT_AFU) begin test_count test_count ( .clk (clk), .rst_n (rst_n), //-------------------------------------------------// .start_um (start_um), .um_params (um_params[511:0]), .um_done (um_done), // User Module TX RD .um_tx_rd_addr (um_tx_rd_addr), .um_tx_rd_tag (um_tx_rd_tag), .um_tx_rd_valid (um_tx_rd_valid), .um_tx_rd_ready (um_tx_rd_ready), // User Module TX WR .um_tx_wr_addr (um_tx_wr_addr), .um_tx_wr_tag (um_tx_wr_tag), .um_tx_wr_valid (um_tx_wr_valid), .um_tx_data (um_tx_data), .um_tx_wr_ready (um_tx_wr_ready), // User Module RX RD .um_rx_rd_tag (um_rx_rd_tag), .um_rx_data (um_rx_data), .um_rx_rd_valid (um_rx_rd_valid), .um_rx_rd_ready (um_rx_rd_ready), // User Module RX WR .um_rx_wr_valid (um_rx_wr_valid), .um_rx_wr_tag (um_rx_wr_tag) ); assign um_state_counters_valid = 1'b0; end else if (AFU_OPERATOR == `SELECTION) begin selection selection ( .clk (clk), .rst_n (rst_n), //-------------------------------------------------// .start_um (start_um), .um_params (um_params[511:0]), .um_done (um_done), // User Module TX RD .um_tx_rd_addr (um_tx_rd_addr), .um_tx_rd_tag (um_tx_rd_tag), .um_tx_rd_valid (um_tx_rd_valid), .um_tx_rd_ready (um_tx_rd_ready), // User Module TX WR .um_tx_wr_addr (um_tx_wr_addr), .um_tx_wr_tag (um_tx_wr_tag), .um_tx_wr_valid (um_tx_wr_valid), .um_tx_data (um_tx_data), .um_tx_wr_ready (um_tx_wr_ready), // User Module RX RD .um_rx_rd_tag (um_rx_rd_tag), .um_rx_data (um_rx_data), .um_rx_rd_valid (um_rx_rd_valid), .um_rx_rd_ready (um_rx_rd_ready), // User Module RX WR .um_rx_wr_valid (um_rx_wr_valid), .um_rx_wr_tag (um_rx_wr_tag) ); assign um_state_counters_valid = 1'b0; end else if (AFU_OPERATOR == `SGD_AFU) begin sgd sgd ( .clk (clk), .rst_n (rst_n), //-------------------------------------------------// .start_um (start_um), .um_params (um_params[1535:0]), .um_done (um_done), // User Module TX RD .um_tx_rd_addr (um_tx_rd_addr), .um_tx_rd_tag (um_tx_rd_tag), .um_tx_rd_valid (um_tx_rd_valid), .um_tx_rd_ready (um_tx_rd_ready), // User Module TX WR .um_tx_wr_addr (um_tx_wr_addr), .um_tx_wr_tag (um_tx_wr_tag), .um_tx_wr_valid (um_tx_wr_valid), .um_tx_data (um_tx_data), .um_tx_wr_ready (um_tx_wr_ready), // User Module RX RD .um_rx_rd_tag (um_rx_rd_tag), .um_rx_data (um_rx_data), .um_rx_rd_valid (um_rx_rd_valid), .um_rx_rd_ready (um_rx_rd_ready), // User Module RX WR .um_rx_wr_valid (um_rx_wr_valid), .um_rx_wr_tag (um_rx_wr_tag) ); assign um_state_counters_valid = 1'b0; end else if (AFU_OPERATOR == `MAX_MIN_SUM_AFU) begin minmaxsum minmaxsum ( .clk (clk), .rst_n (rst_n), //-------------------------------------------------// .start_um (start_um), .um_params (um_params[511:0]), .um_done (um_done), // User Module TX RD .um_tx_rd_addr (um_tx_rd_addr), .um_tx_rd_tag (um_tx_rd_tag), .um_tx_rd_valid (um_tx_rd_valid), .um_tx_rd_ready (um_tx_rd_ready), // User Module TX WR .um_tx_wr_addr (um_tx_wr_addr), .um_tx_wr_tag (um_tx_wr_tag), .um_tx_wr_valid (um_tx_wr_valid), .um_tx_data (um_tx_data), .um_tx_wr_ready (um_tx_wr_ready), // User Module RX RD .um_rx_rd_tag (um_rx_rd_tag), .um_rx_data (um_rx_data), .um_rx_rd_valid (um_rx_rd_valid), .um_rx_rd_ready (um_rx_rd_ready), // User Module RX WR .um_rx_wr_valid (um_rx_wr_valid), .um_rx_wr_tag (um_rx_wr_tag) ); assign um_state_counters_valid = 1'b0; end else if (AFU_OPERATOR == `PERCENTAGE_AFU) begin precentage_um precentage_um ( .clk (clk), .rst_n (rst_n), //-------------------------------------------------// .start_um (start_um), .um_params (um_params[511:0]), .um_done (um_done), // User Module TX RD .um_tx_rd_addr (um_tx_rd_addr), .um_tx_rd_tag (um_tx_rd_tag), .um_tx_rd_valid (um_tx_rd_valid), .um_tx_rd_ready (um_tx_rd_ready), // User Module TX WR .um_tx_wr_addr (um_tx_wr_addr), .um_tx_wr_tag (um_tx_wr_tag), .um_tx_wr_valid (um_tx_wr_valid), .um_tx_data (um_tx_data), .um_tx_wr_ready (um_tx_wr_ready), // User Module RX RD .um_rx_rd_tag (um_rx_rd_tag), .um_rx_data (um_rx_data), .um_rx_rd_valid (um_rx_rd_valid), .um_rx_rd_ready (um_rx_rd_ready), // User Module RX WR .um_rx_wr_valid (um_rx_wr_valid), .um_rx_wr_tag (um_rx_wr_tag) ); assign um_state_counters_valid = 1'b0; end else if (AFU_OPERATOR == `MAC_AFU) begin addmul addmul ( .clk (clk), .rst_n (rst_n), //-------------------------------------------------// .start_um (start_um), .um_params (um_params[511:0]), .um_done (um_done), // User Module TX RD .um_tx_rd_addr (um_tx_rd_addr), .um_tx_rd_tag (um_tx_rd_tag), .um_tx_rd_valid (um_tx_rd_valid), .um_tx_rd_ready (um_tx_rd_ready), // User Module TX WR .um_tx_wr_addr (um_tx_wr_addr), .um_tx_wr_tag (um_tx_wr_tag), .um_tx_wr_valid (um_tx_wr_valid), .um_tx_data (um_tx_data), .um_tx_wr_ready (um_tx_wr_ready), // User Module RX RD .um_rx_rd_tag (um_rx_rd_tag), .um_rx_data (um_rx_data), .um_rx_rd_valid (um_rx_rd_valid), .um_rx_rd_ready (um_rx_rd_ready), // User Module RX WR .um_rx_wr_valid (um_rx_wr_valid), .um_rx_wr_tag (um_rx_wr_tag) ); assign um_state_counters_valid = 1'b0; end else begin assign um_tx_rd_valid = 1'b0; assign um_tx_wr_valid = 1'b0; assign um_rd_done = 1'b0; assign um_wr_done = 1'b0; assign um_state_counters_valid = 1'b0; end endgenerate endmodule
module sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell ( X, A ); // Module ports output X; input A; // Module supplies supply1 VPWR; supply0 VGND; supply1 VPB ; supply0 VNB ; // Name Output Other arguments buf buf0 (X , A ); endmodule
module tbrx ( //---------Inputs------------ input wire sys_clk, input wire rst_n, input wire [2:0] rx_tc, input wire rx_st, input wire rx_end, input wire [15:0] rx_data, `ifdef ECRC input wire rx_ecrc_err, `endif input wire rx_malf_tlp, input wire rx_us_req, //---------Outputs------------ output wire tbrx_cmd_prsnt, output reg ph_buf_status, output reg pd_buf_status, output reg nph_buf_status, output reg npd_buf_status, output reg cplh_buf_status, output reg cpld_buf_status, output reg ph_processed, output reg pd_processed, output reg nph_processed, output reg npd_processed, output reg cplh_processed, output reg cpld_processed, output reg [7:0] pd_num, output reg [7:0] npd_num, output reg [7:0] cpld_num, output reg [7:0] INIT_PH_FC, output reg [7:0] INIT_NPH_FC, output reg [7:0] INIT_CPLH_FC, output reg [11:0] INIT_PD_FC, output reg [11:0] INIT_NPD_FC, output reg [11:0] INIT_CPLD_FC ); // ============================================================================= //`define DEBUG 1 // ============================================================================= `define TBRX_UPPER32_ADDR 32'h1000_0000 `define TBRX_REQ_ID 16'hAAAA `define TBRX_CPL_ID 16'hBBBB parameter R = 1'b0; parameter HEAD_4DW = 1'b1; parameter HEAD_3DW = 1'b0; parameter MEM_TYPE = 5'b0_0000; parameter IO_TYPE = 5'b0_0010; parameter CFG0_TYPE = 5'b0_0100; parameter CFG1_TYPE = 5'b0_0101; parameter MSG_TYPE = 5'b1_0xxx; //parameter MSG_TYPE = 5'b1_0000; //Chosen "Routed to Root Complex" parameter CPL_TYPE = 5'b0_1010; parameter MEM_RD = 4'b0000; parameter MEM_WR = 4'b0001; parameter IO_RD = 4'b0010; parameter IO_WR = 4'b0011; parameter CFG_RD = 4'b0100; parameter CFG_WR = 4'b0101; parameter MSG = 4'b0110; parameter MSG_D = 4'b0111; parameter CPL = 4'b1000; parameter CPL_D = 4'b1001; parameter TLP = 4'b1010; // Error Code Parameters for display Error parameter TYPE_C = 5'd0; parameter FMT_C = 5'd1; parameter TC_C = 5'd2; parameter TD_C = 5'd3; parameter EP_C = 5'd4; parameter ATTR_C = 5'd5; parameter LEN_C = 5'd6; parameter RSRV_C = 5'd7; parameter REQ_ID_C = 5'd8; parameter TAG_C = 5'd9; parameter LastDW_BE_C = 5'd10; parameter FirstDW_BE_C = 5'd11; parameter ADDR_C = 5'd12; parameter DATA_C = 5'd13; parameter MSG_C = 5'd14; parameter MSGCODE_C = 5'd15; parameter CPL_ID_C = 5'd16; parameter STATUS_C = 5'd17; parameter BCM_C = 5'd18; parameter BYTECNT_C = 5'd19; parameter LOWERADDR_C = 5'd20; parameter TBRX_IDLE = 2'b00; parameter TBRX_SOP = 2'b01; parameter TBRX_DATA = 2'b10; parameter CHECK_LSW = 2'b01; parameter CHECK_MSW = 2'b10; parameter CHECK_BOTH = 2'b11; //-------- ERROR Types parameter NO_TLP_ERR = 4'b0000; parameter ECRC_ERR = 4'b0001; parameter UNSUP_ERR = 4'b0010; parameter MALF_ERR = 4'b0011; parameter FMT_TYPE_ERR = 4'b1111; //-------- For Flow Control Tasks parameter P = 2'b00; parameter NP = 2'b01; parameter CPLX = 2'b10; //CPL is already used in some other paramter parameter PH = 3'b000; parameter PD = 3'b001; parameter NPH = 3'b010; parameter NPD = 3'b011; parameter CPLH = 3'b100; parameter CPLD = 3'b101; // ============================================================================= // Define all inputs / outputs // ============================================================================= // ============================================================================= // Define Wire & Registers // ============================================================================= //---- Registers reg [71:0] TBRX_WAIT_FIFO [1023:0]; reg [3:0] TBRX_FIFO_TC [1023:0]; reg [9:0] got_cnt; reg [9:0] wt_cnt; reg pkt_inprogress; reg rx_st_del1, rx_st_del2, rx_st_del3, rx_st_del4; reg rx_st_del5, rx_st_del6, rx_st_del7, rx_st_del8; reg [1:0] tbrx_state; reg TBRX_Error; reg [10:0] di, dj; reg [63:0] H1_got; reg [63:0] H2_got; reg [31:0] H1_ms_exp; reg [31:0] H1_ls_exp; reg [31:0] H2_ms_exp; reg [31:0] H2_ls_exp; reg [15:0] data0, data1; reg [31:0] D [9:0]; //For User Manual Data reg short_pkt; reg exp_dwen; reg fmt_type_err; reg man_tlp_pkt; reg [1:0] stored_fmt; reg [4:0] stored_type; reg [9:0] stored_len; reg [3:0] stored_error; reg [3:0] stored_kind; reg [4:0] Error_code; reg toggle; reg [15:0] d1, d2, d3, d4, d5, d6, d7, d8, rx_data_del; //---- Wires wire [71:0] wt_info; wire [71:0] wt_info2; wire [3:0] tc_info; wire wt_cfg; wire [7:0] wt_be; wire wt_hdr; wire wt_td; wire wt_ep; wire [9:0] wt_len; wire [31:0] wt_addr; wire [3:0] wt_type; wire [3:0] wt_et; wire [11:0] wt_bytecnt; wire [6:0] wt_loweraddr; wire [2:0] wt_status; wire [2:0] wt_tc; wire wt_tc_set; wire rx_st_x4, rx_st_x4_del; // ============================================================================= // The following signals are task CHECK_HEADER internal signals // Kept them outside so that ERROR_TASK can access these signals for display // ============================================================================= reg TD, EP; reg [7:0] TAG; reg [1:0] ATTR; reg [2:0] TC; reg [1:0] fmt; reg [4:0] type; reg [9:0] len; reg [3:0] LastDW_BE; reg [3:0] FirstDW_BE; reg [3:0] Error_Type; reg R1,R2,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12; reg TDx, EPx; reg [7:0] TAGx; reg [1:0] ATTRx; reg [2:0] TCx; reg [1:0] fmtx; reg [4:0] typex; reg [9:0] lenx; reg [3:0] LastDW_BEx; reg [3:0] FirstDW_BEx; reg [31:0] TBRX_UPPER32_ADDRx; reg [15:0] TBRX_REQ_IDx; reg [7:0] TBRX_MSG_CODEx; reg [15:0] TBRX_CPL_IDx; reg [63:0] TBRX_MSG_TYPEx; reg TBRX_BCMx; reg [31:0] wt_addrx; reg [11:0] wt_bytecntx; reg [6:0] wt_loweraddrx; reg [2:0] wt_statusx; reg [31:0] FirstDatax; // ============================================================================= // -------- GLOBAL REGISTERS THAT CAN BE SET BY THE USER IN THE TEST ---------- // TD : Set indicates Presence of TLP Digest (ECRC) // EP : Set indicates data Poisoned // First DW BE : // Last DW BE : // REQUESTER ID : 16 bits // Tag :8 bits // Attr : 2 bits {Ordering, Snoop} = {0,0} -> {Strong Order, Snoop} // ============================================================================= reg [31:0] TBRX_UPPER32_ADDR; reg [15:0] TBRX_REQ_ID; reg [15:0] TBRX_CPL_ID; reg [7:0] TBRX_TAG; reg TBRX_TD; reg TBRX_EP; reg TBRX_BCM; //For CPL Header reg [2:0] TBRX_TC; reg [1:0] TBRX_ATTR; reg [9:0] TBRX_LEN; reg [3:0] TBRX_LastDW_BE; reg [2:0] TBRX_MSG_ROUTE; reg [7:0] TBRX_MSG_CODE; reg [63:0] TBRX_MSG_TYPE; reg [3:0] First_DW_BE; reg [3:0] Last_DW_BE; reg TBRX_MANUAL_DATA; reg TBRX_FIXED_PATTERN; // ============================================================================= // TX Request Fifo // ============================================================================= assign tbrx_cmd_prsnt = (wt_cnt == got_cnt) ? 1'b0 : 1'b1; initial begin TBRX_UPPER32_ADDR = `TBRX_UPPER32_ADDR; TBRX_REQ_ID = `TBRX_REQ_ID; TBRX_CPL_ID = `TBRX_CPL_ID; TBRX_TAG = 8'h00; TBRX_TD = 1'b0; TBRX_EP = 1'b0; TBRX_BCM = 1'b0; //For IO & CFG Pkts TBRX_TC = 3'b000; TBRX_ATTR = 2'b00; TBRX_LEN = 10'd1; TBRX_LastDW_BE = 4'b0000; TBRX_MSG_ROUTE = 3'b000; // Refer PNo 63 TBRX_MSG_CODE = 8'h00; //Refer Page No 64-69 TBRX_MSG_TYPE = 64'h0000_0000_0000_0000; First_DW_BE = 4'b1111; Last_DW_BE = 4'b1111; D[0] = 0; D[1] = 0; D[2] = 0; D[3] = 0; D[4] = 0; D[5] = 0; D[6] = 0; D[7] = 0; D[8] = 0; D[9] = 0; end initial begin wt_cnt = 'd0; man_tlp_pkt = 0; end // ============================================================================= // 4 + 4 + 32 + 10 + 1 + 1 + 1 + 4 + 4 + 11 = 72 // Error Type + kind + addr + len + 3dw/4dw + TD + EP + FirstDwBE + LastDwBE + // Extra bits 11 // For Manual TLP type: 4 + 4 + 64 bit header = 72 bits // ============================================================================= assign wt_info = TBRX_WAIT_FIFO[got_cnt]; assign wt_info2 = TBRX_WAIT_FIFO[got_cnt+1]; assign tc_info = TBRX_FIFO_TC[got_cnt]; //10:0 is not used for Normal Pkt, but for Manula TLP pkt assign wt_cfg = wt_info[11]; //For Config (Config0 or Config1) assign wt_be = wt_info[18:11]; assign wt_ep = wt_info[19]; assign wt_td = wt_info[20]; assign wt_hdr = wt_info[21]; assign wt_len = wt_info[31:22]; // Len21h of Pkt assign wt_addr = wt_info[63:32]; // Addr assign wt_type = wt_info[67:64]; // Type of pkt assign wt_et = wt_info[71:68]; // Error Type assign wt_bytecnt = wt_addr[31:20]; assign wt_loweraddr = wt_addr[19:13]; assign wt_status = wt_addr[12:10]; assign wt_tc = tc_info[2:0]; assign wt_tc_set = tc_info[3]; reg [1:0] NEW_fmt; always @(*) begin case (wt_type) MEM_RD : NEW_fmt = {1'b0, wt_hdr}; MEM_WR : NEW_fmt = {1'b1, wt_hdr}; CFG_RD : NEW_fmt = {1'b0, 1'b0}; CFG_WR : NEW_fmt = {1'b1, 1'b0}; IO_RD : NEW_fmt = {1'b0, 1'b0}; IO_WR : NEW_fmt = {1'b1, 1'b0}; MSG : NEW_fmt = {1'b0, 1'b1}; MSG_D : NEW_fmt = {1'b1, 1'b1}; CPL : NEW_fmt = {1'b0, 1'b0}; CPL_D : NEW_fmt = {1'b1, 1'b0}; TLP : NEW_fmt = wt_info[62:61]; endcase end reg [39:0] HEADER_s; always @(*) begin case (NEW_fmt) 2'b00 : HEADER_s = "3DW "; //3DW with No data 2'b01 : HEADER_s = "4DW "; //4DW with No data 2'b10 : HEADER_s = "3DW_D"; //3DW with data (may be 1 or more) 2'b11 : HEADER_s = "4DW_D"; //4DW with data (may be 1 or more) endcase end reg [47:0] TYPE_EXP_s; always @(*) begin case (wt_type) MEM_RD : TYPE_EXP_s = "MEM_RD"; MEM_WR : TYPE_EXP_s = "MEM_WR"; CFG_RD : TYPE_EXP_s = "CFG_RD"; CFG_WR : TYPE_EXP_s = "CFG_WR"; IO_RD : TYPE_EXP_s = "IO_RD"; IO_WR : TYPE_EXP_s = "IO_WR"; MSG : TYPE_EXP_s = "MSG"; MSG_D : TYPE_EXP_s = "MSG_D"; CPL : TYPE_EXP_s = "CPL"; CPL_D : TYPE_EXP_s = "CPL_D"; TLP : TYPE_EXP_s = "TLP"; endcase end reg [31:0] TBRX_STATE_s; always @(*) begin case(tbrx_state) TBRX_IDLE : TBRX_STATE_s = "IDLE"; TBRX_SOP : TBRX_STATE_s = "SOP "; TBRX_DATA : TBRX_STATE_s = "DATA"; endcase end // ============================================================================= // Unsupported TLP : fmt & Type field errors (? Undefined) + Locked transactions // Malfunction TLP : Max len err + length error + undefined TLP + IO & CFG VCID err // ============================================================================= assign rx_st_x4 = (rx_st | rx_st_del1 | rx_st_del2 | rx_st_del3); assign rx_st_x4_del = (rx_st_del4 | rx_st_del5 | rx_st_del6 | rx_st_del7); always @(posedge sys_clk or negedge rst_n) begin if (!rst_n) begin pkt_inprogress <= 1'b0; rx_st_del1 <= 1'b0; rx_st_del2 <= 1'b0; rx_st_del3 <= 1'b0; rx_st_del4 <= 1'b0; rx_st_del5 <= 1'b0; rx_st_del6 <= 1'b0; rx_st_del7 <= 1'b0; rx_st_del8 <= 1'b0; tbrx_state <= TBRX_IDLE; got_cnt = 0; H1_got = 0; H2_got = 0; di = 0; data0 = 0; data1 = 0; end else begin rx_st_del1 <= rx_st; rx_st_del2 <= rx_st_del1; rx_st_del3 <= rx_st_del2; rx_st_del4 <= rx_st_del3; rx_st_del5 <= rx_st_del4; rx_st_del6 <= rx_st_del5; rx_st_del7 <= rx_st_del6; rx_st_del8 <= rx_st_del7; if(rx_st) pkt_inprogress <= 1'b1; else if(rx_end) pkt_inprogress <= 1'b0; //State Machine for Header & Data check //d1 = d2; d2 = d3 ; d3 = d4 ; d4 = rx_data; d1 = (rx_st) ? rx_data : d1; d2 = (rx_st_del1) ? rx_data : d2; d3 = (rx_st_del2) ? rx_data : d3; d4 = (rx_st_del3) ? rx_data : d4; d5 = (rx_st_del4) ? rx_data : d5; d6 = (rx_st_del5) ? rx_data : d6; d7 = (rx_st_del6) ? rx_data : d7; d8 = (rx_st_del7) ? rx_data : d8; rx_data_del <= rx_data; case(tbrx_state) TBRX_IDLE : begin if(wt_cnt != got_cnt) begin tbrx_state <= TBRX_SOP; end end TBRX_SOP : begin //Wait for SOP, Header & check the Header //------------Header check --------------- if(rx_st_x4) H1_got = {d1, d2, d3, d4}; if(rx_st_x4_del) H2_got = {d5, d6, d7, d8}; //H2_got = {d1, d2, d3, d4}; //if(rx_st_del1) begin if(rx_st_del7 || (rx_st_del5 && (NEW_fmt == 2'b00))) begin //3dw with no data or Others CHECK_HEADER; if(!fmt_type_err) begin if(stored_fmt == 2'b10) //3dw with data CHECK_DATA(0); end else begin if(rx_end) if(!rx_malf_tlp && !rx_us_req) begin //FMT/TYPE error found //if(!rx_malf_tlp && (stored_error != NO_TLP_ERR)) begin $display ("TBRX-TC%d: **** ERROR **** : MALF PKT - rx_malf_tlp is not Asserted at time %0t", rx_tc, $time); TBRX_Error = 1'b1; end end end //------------Error Signal check --------------- di = stored_fmt[0] ? 0 : 1; //3dw or 4dw header toggle = 0; //if(rx_st_del1) begin if(rx_st_del7 || (rx_st_del5 && (NEW_fmt == 2'b00))) begin //3dw with no data or Others if(rx_end) begin EOP_TASK; tbrx_state <= TBRX_IDLE; got_cnt = (man_tlp_pkt) ? (got_cnt + 2) : (got_cnt + 1); rx_st_del6 <= 0; rx_st_del7 <= 0; rx_st_del8 <= 0; end else tbrx_state <= TBRX_DATA; end end TBRX_DATA : begin if(!fmt_type_err) begin if(toggle) begin //------------Data check --------------- CHECK_DATA(di); //------------Len check --------------- di = di+1; if(rx_end) begin if((di > stored_len) || (di < stored_len)) begin if(!rx_malf_tlp) begin $display ("TBRX-TC%d: **** ERROR **** : Length & Actual Data Length Mismatch at time %0t", rx_tc, $time); TBRX_Error = 1'b1; end else begin if (`DEBUG) $display ("TBRX-TC%d: INFO: RECEIVED MALFORMED TLP at time %0t", rx_tc, $time); end end else begin `ifdef ECRC if(!rx_ecrc_err && !rx_malf_tlp && !rx_us_req && (stored_error != NO_TLP_ERR)) begin `else if(!rx_malf_tlp && !rx_us_req && (stored_error != NO_TLP_ERR)) begin `endif $display ("TBRX-TC%d: **** ERROR **** : MALF PKT - rx_malf_tlp is not Asserted at time %0t", rx_tc, $time); TBRX_Error = 1'b1; end end //rx_end check end end //toggle check else if(rx_end) begin $display ("TBRX-TC%d: **** ERROR **** : Non-Dword aligned pkt at time %0t", rx_tc, $time); TBRX_Error = 1'b1; end end //fmt_type_err else begin if(rx_end) if(!rx_malf_tlp && !rx_us_req) begin //FMT/TYPE error found //if(!rx_malf_tlp && (stored_error != NO_TLP_ERR)) begin $display ("TBRX-TC%d: **** ERROR **** : MALF PKT - rx_malf_tlp is not Asserted at time %0t", rx_tc, $time); TBRX_Error = 1'b1; end end //------------Error Signal check --------------- if(rx_end) begin EOP_TASK; tbrx_state <= TBRX_IDLE; got_cnt = (man_tlp_pkt) ? (got_cnt + 2) : (got_cnt + 1); end toggle = ~toggle; end endcase //SOP & EOP checking case(tbrx_state) TBRX_IDLE : begin if((wt_cnt == got_cnt) && (rx_st || rx_end)) begin $display ("TBRX-TC%d: **** ERROR **** : Unexpected SOP/EOP signals at time %0t", rx_tc, $time); TBRX_Error = 1'b1; end end TBRX_SOP : begin if(rx_st && rx_end) begin TBRX_Error = 1'b1; $display ("TBRX-TC%d: **** ERROR **** : SOP & EOP at the same time at time %0t", rx_tc, $time); end /***** if(rx_st_del5 && short_pkt && !rx_end) begin TBRX_Error = 1'b1; $display ("TBRX-TC%d: **** ERROR **** : Short Pkt, but EOP missing at time %0t", rx_tc, $time); end *****/ if(!fmt_type_err) begin /***** if((rx_st_x4 || rx_st_del4 || rx_st_del5) && !short_pkt && rx_end) begin TBRX_Error = 1'b1; $display ("TBRX-TC%d: **** ERROR **** : Not a Short Pkt, but EOP has come at time %0t", rx_tc, $time); end *****/ if((rx_st_x4 || rx_st_del4) && rx_end) begin TBRX_Error = 1'b1; $display ("TBRX-TC%d: **** ERROR **** : PKT smaller than 3 Dwords at time %0t", rx_tc, $time); end end end TBRX_DATA : begin if(!fmt_type_err) begin if(rx_st) begin $display ("TBRX-TC%d: **** ERROR **** : SOP before the end of current PKT at time %0t", rx_tc, $time); TBRX_Error = 1'b1; end end end endcase end end // ============================================================================= // HEADER Check for the Received Pkt // ============================================================================= // Input is H1_got & H2_got task CHECK_HEADER; begin TAG = TBRX_TAG + 1; TBRX_TAG = TAG; TAG = {3'b000, TBRX_TAG[4:0]}; TD = wt_td; EP = wt_ep; Error_Type = wt_et; //Reset First {R1,R2,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12} = 12'd0; TBRX_UPPER32_ADDRx = TBRX_UPPER32_ADDR; FirstDatax = 32'd0; short_pkt = 0; //no data OR 3 DW with 1 data exp_dwen = 0; fmt_type_err = 0; man_tlp_pkt = 0; case (wt_type) MEM_RD, MEM_WR : begin //TC = rx_tc; TC = (wt_tc_set) ? wt_tc : rx_tc; ATTR = 2'b00; // Attr : 2 bits {Ordering, Snoop} = {0,0} -> {Strong Order, Snoop} fmt[1] = (wt_type == MEM_RD) ? 1'b0 : 1'b1; fmt[0] = (wt_hdr) ? 1'b1 : 1'b0; //32-bit /64-bit addressing (3 DW /4 DW) type = MEM_TYPE; len = wt_len; FirstDW_BE = wt_be[7:4]; LastDW_BE = wt_be[3:0]; {R1, fmtx, typex, R2, TCx, R3,R4,R5,R6, TDx, EPx, ATTRx, R7,R8, lenx} = H1_got[63:32]; {TBRX_REQ_IDx, TAGx, LastDW_BEx, FirstDW_BEx} = H1_got[31:0]; if(wt_hdr) //64-bit Addr / 4 DW header {TBRX_UPPER32_ADDRx, wt_addrx[31:2], R9, R10} = H2_got; //else if(wt_type == MEM_RD) //3DW with No data -- 03.17.06 //{wt_addrx[31:2], R11, R12} = H2_got[31:0]; else //3 DW with data {wt_addrx[31:2], R11, R12, FirstDatax} = H2_got; `ifdef DIS_TAG_CHK TAG = TAGx; `endif //First 8 bytes of Header H1_ms_exp = {R, fmt, type, R, TC, R,R,R,R, TD, EP, ATTR, R,R, len}; H1_ls_exp = {TBRX_REQ_ID, TAG, LastDW_BE, FirstDW_BE}; //Second 4 bytes of Header if(wt_hdr) begin //64-bit Addr / 4 DW header H2_ms_exp = TBRX_UPPER32_ADDR; H2_ls_exp = {wt_addr[31:2], R, R}; end else begin H2_ms_exp = {wt_addr[31:2], R, R}; H2_ls_exp = H2_got[31:0]; //This is not header , but may be first data end Error_code = (typex != type) ? TYPE_C : Error_code; //_C : Code Error_code = (fmtx != fmt) ? FMT_C : Error_code; Error_code = (TCx != TC) ? TC_C : Error_code; Error_code = (TDx != TD) ? TD_C : Error_code; Error_code = (EPx != EP) ? EP_C : Error_code; Error_code = (ATTRx != ATTR) ? ATTR_C : Error_code; Error_code = (lenx != len) ? LEN_C : Error_code; Error_code = (TBRX_REQ_IDx != TBRX_REQ_ID) ? REQ_ID_C : Error_code; Error_code = (TAGx != TAG) ? TAG_C : Error_code; Error_code = (LastDW_BEx != LastDW_BE) ? LastDW_BE_C : Error_code; Error_code = (FirstDW_BEx != FirstDW_BE) ? FirstDW_BE_C : Error_code; Error_code = (wt_addrx[31:2] != wt_addr[31:2]) ? ADDR_C : Error_code; //Error_code = (FirstDatax != 32'd0) ? DATA_C : Error_code; Error_code = ({R1,R2,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12} != 12'd0) ? RSRV_C : Error_code; //MEM_RD with 3DW/4DW, MEM_WR with 3DW Header & 1 data if((wt_type == MEM_RD) || ((wt_type == MEM_WR) && (wt_hdr == 0) && (len == 1))) begin short_pkt = 1; exp_dwen = ((wt_type == MEM_RD) && (!wt_hdr)) ? 1'b0 : 1'b1; end if((H1_got != {H1_ms_exp, H1_ls_exp}) || (H2_got != {H2_ms_exp, H2_ls_exp})) begin if(wt_type == MEM_RD) $display ("TBRX-TC%d: **** ERROR in Mem RD Header **** : at time %0t", rx_tc, $time); else $display ("TBRX-TC%d: **** ERROR in Mem WR Header **** : at time %0t", rx_tc, $time); TBRX_Error = 1; ERROR_TASK; end end CFG_RD, CFG_WR : begin //TC = 3'b000; //Always //ATTR = 2'b00; //Always //len = 10'd1; //Always //LastDW_BE = 4'b0000; //Always TC = TBRX_TC; ATTR = TBRX_ATTR; LastDW_BE = TBRX_LastDW_BE; len = TBRX_LEN; fmt[1] = (wt_type == CFG_RD) ? 1'b0 : 1'b1; fmt[0] = 1'b0; //Always 3 DW type = (wt_cfg) ? CFG1_TYPE : CFG0_TYPE; FirstDW_BE = wt_be[7:4]; {R1, fmtx, typex, R2, TCx, R3,R4,R5,R6, TDx, EPx, ATTRx, R7,R8, lenx} = H1_got[63:32]; {TBRX_REQ_IDx, TAGx, LastDW_BEx, FirstDW_BEx} = H1_got[31:0]; wt_addrx = H2_got[63:32]; `ifdef DIS_TAG_CHK TAG = TAGx; `endif //First 8 bytes of Header H1_ms_exp = {R, fmt, type, R, TC, R,R,R,R, TD, EP, ATTR, R,R, len}; H1_ls_exp = {TBRX_REQ_ID, TAG, LastDW_BE, FirstDW_BE}; //Second 4 bytes of Header H2_ms_exp = wt_addr; H2_ls_exp = 32'd0; Error_code = (typex != type) ? TYPE_C : Error_code; //_C : Code Error_code = (fmtx != fmt) ? FMT_C : Error_code; Error_code = (TCx != TC) ? TC_C : Error_code; Error_code = (TDx != TD) ? TD_C : Error_code; Error_code = (EPx != EP) ? EP_C : Error_code; Error_code = (ATTRx != ATTR) ? ATTR_C : Error_code; Error_code = (lenx != len) ? LEN_C : Error_code; Error_code = (TBRX_REQ_IDx != TBRX_REQ_ID) ? REQ_ID_C : Error_code; Error_code = (TAGx != TAG) ? TAG_C : Error_code; Error_code = (LastDW_BEx != LastDW_BE) ? LastDW_BE_C : Error_code; Error_code = (FirstDW_BEx != FirstDW_BE) ? FirstDW_BE_C : Error_code; Error_code = (wt_addrx[31:2] != wt_addr[31:2]) ? ADDR_C : Error_code; Error_code = ({R1,R2,R3,R4,R5,R6,R7,R8} != 8'd0) ? RSRV_C : Error_code; short_pkt = 1; exp_dwen = (wt_type == CFG_RD) ? 1'b0 : 1'b1; if((H1_got != {H1_ms_exp, H1_ls_exp}) || (H2_got[63:32] != H2_ms_exp)) begin case({wt_cfg, fmt[1]}) //or wt_type 2'b00 : $display ("TBRX-TC%d: **** ERROR in CFG0 RD Header **** : at time %0t", rx_tc, $time); 2'b01 : $display ("TBRX-TC%d: **** ERROR in CFG0 WR Header **** : at time %0t", rx_tc, $time); 2'b10 : $display ("TBRX-TC%d: **** ERROR in CFG1 RD Header **** : at time %0t", rx_tc, $time); 2'b11 : $display ("TBRX-TC%d: **** ERROR in CFG1 WR Header **** : at time %0t", rx_tc, $time); endcase TBRX_Error = 1; ERROR_TASK; end end IO_RD, IO_WR : begin //TC = 3'b000; //Always //ATTR = 2'b00; //Always //len = 10'd1; //Always //LastDW_BE = 4'b0000; //Always TC = TBRX_TC; ATTR = TBRX_ATTR; LastDW_BE = TBRX_LastDW_BE; len = TBRX_LEN; fmt[1] = (wt_type == IO_RD) ? 1'b0 : 1'b1; //fmt[0] = (wt_hdr) ? 1'b1 : 1'b0; //32-bit /64-bit addressing (3 DW /4 DW) fmt[0] = 1'b0; //Always 3 DW type = IO_TYPE; FirstDW_BE = wt_be[7:4]; //Second 4/8 bytes of Header /**** if(wt_hdr) begin //64-bit Addr / 4 DW header H2_ms_exp = TBRX_UPPER32_ADDR; H2_ls_exp = {wt_addr[31:2], R, R}; end else begin H2_ms_exp = {wt_addr[31:2], R, R}; H2_ls_exp = H2_got[31:0]; //This is not header , but may be first data end ****/ {R1, fmtx, typex, R2, TCx, R3,R4,R5,R6, TDx, EPx, ATTRx, R7,R8, lenx} = H1_got[63:32]; {TBRX_REQ_IDx, TAGx, LastDW_BEx, FirstDW_BEx} = H1_got[31:0]; if(wt_hdr) //64-bit Addr / 4 DW header {TBRX_UPPER32_ADDRx, wt_addrx[31:2], R9, R10} = H2_got; else {wt_addrx[31:2], R11, R12, FirstDatax} = H2_got; `ifdef DIS_TAG_CHK TAG = TAGx; `endif //First 8 bytes of Header H1_ms_exp = {R, fmt, type, R, TC, R,R,R,R, TD, EP, ATTR, R,R, len}; H1_ls_exp = {TBRX_REQ_ID, TAG, LastDW_BE, FirstDW_BE}; //Second 4/8 bytes of Header H2_ms_exp = {wt_addr[31:2], R, R}; H2_ls_exp = H2_got[31:0]; //This is not header , but may be first data Error_code = (typex != type) ? TYPE_C : Error_code; //_C : Code Error_code = (fmtx != fmt) ? FMT_C : Error_code; Error_code = (TCx != TC) ? TC_C : Error_code; Error_code = (TDx != TD) ? TD_C : Error_code; Error_code = (EPx != EP) ? EP_C : Error_code; Error_code = (ATTRx != ATTR) ? ATTR_C : Error_code; Error_code = (lenx != len) ? LEN_C : Error_code; Error_code = (TBRX_REQ_IDx != TBRX_REQ_ID) ? REQ_ID_C : Error_code; Error_code = (TAGx != TAG) ? TAG_C : Error_code; Error_code = (LastDW_BEx != LastDW_BE) ? LastDW_BE_C : Error_code; Error_code = (FirstDW_BEx != FirstDW_BE) ? FirstDW_BE_C : Error_code; Error_code = (wt_addrx[31:2] != wt_addr[31:2]) ? ADDR_C : Error_code; //Error_code = (FirstDatax != 32'd0) ? DATA_C : Error_code; Error_code = ({R1,R2,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12} != 12'd0) ? RSRV_C : Error_code; //IO_RD with 3DW/4DW, IO_WR with 3DW Header & 1 data //if((wt_type == IO_RD) || ((wt_type == IO_WR) && (wt_hdr == 0) && (len == 1))) begin short_pkt = 1; exp_dwen = (wt_type == IO_RD) ? 1'b0 : 1'b1; //end if((H1_got != {H1_ms_exp, H1_ls_exp}) || (H2_got != {H2_ms_exp, H2_ls_exp})) begin if(wt_type == IO_RD) $display ("TBRX-TC%d: **** ERROR in IO RD Header **** : at time %0t", rx_tc, $time); else $display ("TBRX-TC%d: **** ERROR in IO WR Header **** : at time %0t", rx_tc, $time); TBRX_Error = 1; ERROR_TASK; end end MSG, MSG_D : begin //TC = rx_tc; TC = (wt_tc_set) ? wt_tc : rx_tc; //ATTR = 2'b00; // Attr : 2 bits {Ordering, Snoop} = {0,0} -> {Strong Order, Snoop} ATTR = TBRX_ATTR; fmt[1] = (wt_type == MSG) ? 1'b0 : 1'b1; fmt[0] = 1'b1; //Always 4 DW type = {MSG_TYPE[4:3], TBRX_MSG_ROUTE}; len = wt_len; {R1, fmtx, typex, R2, TCx, R3,R4,R5,R6, TDx, EPx, ATTRx, R7,R8, lenx} = H1_got[63:32]; {TBRX_REQ_IDx, TAGx, TBRX_MSG_CODEx} = H1_got[31:0]; TBRX_MSG_TYPEx = H2_got; `ifdef DIS_TAG_CHK TAG = TAGx; `endif `ifdef DIS_TC_CHK TC = TCx; `endif //First 8 bytes of Header H1_ms_exp = {R, fmt, type, R, TC, R,R,R,R, TD, EP, ATTR, R,R, len}; H1_ls_exp = {TBRX_REQ_ID, TAG, TBRX_MSG_CODE}; //Second 8 bytes of Header {H2_ms_exp, H2_ls_exp} = TBRX_MSG_TYPE; Error_code = (typex != type) ? TYPE_C : Error_code; //_C : Code Error_code = (fmtx != fmt) ? FMT_C : Error_code; Error_code = (TCx != TC) ? TC_C : Error_code; Error_code = (TDx != TD) ? TD_C : Error_code; Error_code = (EPx != EP) ? EP_C : Error_code; Error_code = (ATTRx != ATTR) ? ATTR_C : Error_code; Error_code = (lenx != len) ? LEN_C : Error_code; Error_code = (TBRX_REQ_IDx != TBRX_REQ_ID) ? REQ_ID_C : Error_code; Error_code = (TAGx != TAG) ? TAG_C : Error_code; Error_code = (TBRX_MSG_CODEx != TBRX_MSG_CODE) ? MSGCODE_C : Error_code; Error_code = (TBRX_MSG_TYPEx != TBRX_MSG_TYPE) ? MSG_C : Error_code; Error_code = ({R1,R2,R3,R4,R5,R6,R7,R8} != 8'd0) ? RSRV_C : Error_code; if(wt_type == MSG) begin short_pkt = 1; exp_dwen = 1; end if((H1_got != {H1_ms_exp, H1_ls_exp}) || (H2_got != {H2_ms_exp, H2_ls_exp})) begin TBRX_Error = 1; ERROR_TASK; end end CPL, CPL_D : begin //TC = rx_tc; TC = (wt_tc_set) ? wt_tc : rx_tc; ATTR = 2'b00; // Attr : 2 bits {Ordering, Snoop} = {0,0} -> {Strong Order, Snoop} fmt[1] = (wt_type == CPL) ? 1'b0 : 1'b1; fmt[0] = 1'b0; //Always 3 DW type = CPL_TYPE; len = wt_len; {R1, fmtx, typex, R2, TCx, R3,R4,R5,R6, TDx, EPx, ATTRx, R7,R8, lenx} = H1_got[63:32]; {TBRX_CPL_IDx, wt_statusx, TBRX_BCMx, wt_bytecntx} = H1_got[31:0]; {TBRX_REQ_IDx, TAGx, R9, wt_loweraddrx} = H2_got[63:32]; `ifdef DIS_TAG_CHK TAG = TAGx; `endif //First 8 bytes of Header H1_ms_exp = {R, fmt, type, R, TC, R,R,R,R, TD, EP, ATTR, R,R, len}; H1_ls_exp = {TBRX_CPL_ID, wt_status, TBRX_BCM, wt_bytecnt}; //Second 4 bytes of Header H2_ms_exp = {TBRX_REQ_ID, TAG, R, wt_loweraddr}; H2_ls_exp = 32'd0; Error_code = (typex != type) ? TYPE_C : Error_code; //_C : Code Error_code = (fmtx != fmt) ? FMT_C : Error_code; Error_code = (TCx != TC) ? TC_C : Error_code; Error_code = (TDx != TD) ? TD_C : Error_code; Error_code = (EPx != EP) ? EP_C : Error_code; Error_code = (ATTRx != ATTR) ? ATTR_C : Error_code; Error_code = (lenx != len) ? LEN_C : Error_code; Error_code = (TBRX_CPL_IDx != TBRX_CPL_ID) ? CPL_ID_C : Error_code; Error_code = (wt_statusx != wt_status) ? STATUS_C : Error_code; Error_code = (TBRX_BCMx != TBRX_BCM) ? BCM_C : Error_code; Error_code = (wt_bytecntx != wt_bytecnt) ? BYTECNT_C : Error_code; Error_code = (TBRX_REQ_IDx != TBRX_REQ_ID) ? REQ_ID_C : Error_code; Error_code = (TAGx != TAG) ? TAG_C : Error_code; Error_code = (wt_loweraddrx != wt_loweraddr) ? LOWERADDR_C : Error_code; Error_code = ({R1,R2,R3,R4,R5,R6,R7,R8,R9} != 9'd0) ? RSRV_C : Error_code; if((wt_type == CPL) || ((wt_type == CPL_D) && len == 1)) begin short_pkt = 1; exp_dwen = (wt_type == CPL) ? 1'b0 : 1'b1; end if((H1_got != {H1_ms_exp, H1_ls_exp}) || (H2_got[63:32] != H2_ms_exp)) begin TBRX_Error = 1; ERROR_TASK; end end TLP : begin fmt_type_err = (Error_Type == FMT_TYPE_ERR) ? 1'b1 : 1'b0; man_tlp_pkt = 1; H1_ms_exp = wt_info[63:32]; H1_ls_exp = wt_info[31:0]; H2_ms_exp = wt_info2[63:32]; H2_ls_exp = (wt_info2[64]) ? wt_info2[31:0] : H2_got[31:0]; //For 3DW header dont check [31:0] fmt = wt_info[62:61]; type = wt_info[60:56]; TC = wt_info[54:52]; TD = wt_info[47]; EP = wt_info[46]; ATTR = wt_info[45:44]; len = wt_info[41:32]; //{R, fmt, type, R, TC, R,R,R,R, TD, EP, ATTR, R,R, len} = wt_info[63:32]; {R1, fmtx, typex, R2, TCx, R3,R4,R5,R6, TDx, EPx, ATTRx, R7,R8, lenx} = H1_got[63:32]; Error_code = (typex != type) ? TYPE_C : Error_code; //_C : Code Error_code = (fmtx != fmt) ? FMT_C : Error_code; Error_code = (TCx != TC) ? TC_C : Error_code; Error_code = (TDx != TD) ? TD_C : Error_code; Error_code = (EPx != EP) ? EP_C : Error_code; Error_code = (ATTRx != ATTR) ? ATTR_C : Error_code; Error_code = (lenx != len) ? LEN_C : Error_code; Error_code = ({R1,R2,R3,R4,R5,R6,R7,R8} != 8'd0) ? RSRV_C : Error_code; if((H1_got != {H1_ms_exp, H1_ls_exp}) || (H2_got != {H2_ms_exp, H2_ls_exp})) begin TBRX_Error = 1; ERROR_TASK; end end endcase stored_type = type; stored_fmt = fmt; stored_len = len; stored_error = Error_Type; stored_kind = wt_type; //Mem or cfg or IO or TLP (rd or wr) end endtask // ============================================================================= // TD : Set indicates Presence of TLP Digest (ECRC) // EP : Set indicates data Poisoned // First DW BE : // Last DW BE : // REQUESTER ID : 16 bits // Tag :8 bits // Attr : 2 bits {Ordering, Snoop} = {0,0} -> {Strong Order, Snoop} // ============================================================================= // ============================================================================= // 4 + 4 + 32 + 10 + 1 + 1 + 1 + 4 + 4 = 61 // Error Type + kind + addr + len + 3dw/4dw + TD + EP + FirstDwBE + LastDwBE // For TLP type: 4 + 4 + 64 bit header = 72 bits // ============================================================================= // ============================================================================= task tbrx_mem_rd; input [31:0] addr; input [9:0] length; input hdr_type; //3 DW or 4 DW input [3:0] Error_Type; begin TBRX_WAIT_FIFO[wt_cnt] = {Error_Type, MEM_RD, addr, length, hdr_type, TBRX_TD, TBRX_EP, First_DW_BE, 4'h0, 11'd0}; TBRX_FIFO_TC[wt_cnt] = 0; wt_cnt = wt_cnt + 1; end endtask // ============================================================================= // ============================================================================= task tbrx_mem_wr; input [31:0] addr; input [9:0] length; input hdr_type; //3 DW or 4 DW input [3:0] Error_Type; begin if(length == 1) TBRX_WAIT_FIFO[wt_cnt] = {Error_Type, MEM_WR, addr, length, hdr_type, TBRX_TD, TBRX_EP, First_DW_BE, 4'h0, 11'd0}; else TBRX_WAIT_FIFO[wt_cnt] = {Error_Type, MEM_WR, addr, length, hdr_type, TBRX_TD, TBRX_EP, First_DW_BE, Last_DW_BE, 11'd0}; TBRX_FIFO_TC[wt_cnt] = 0; wt_cnt = wt_cnt + 1; end endtask // ============================================================================= // ============================================================================= task tbrx_msg; input [9:0] length; input [3:0] Error_Type; begin //Meassge Route & Meassge Code are default values TBRX_WAIT_FIFO[wt_cnt] = {Error_Type, MSG, 32'd0, length, HEAD_4DW, TBRX_TD, TBRX_EP, 4'b0, 4'b0, 11'd0}; TBRX_FIFO_TC[wt_cnt] = 0; wt_cnt = wt_cnt + 1; end endtask // ============================================================================= // ============================================================================= task tbrx_msg_d; input [9:0] length; input [3:0] Error_Type; begin //Meaasge Route & Meassge Code are default values TBRX_WAIT_FIFO[wt_cnt] = {Error_Type, MSG_D, 32'd0, length, HEAD_4DW, TBRX_TD, TBRX_EP, 4'b0, 4'b0, 11'd0}; TBRX_FIFO_TC[wt_cnt] = 0; wt_cnt = wt_cnt + 1; end endtask // ============================================================================= // ============================================================================= task tbrx_cfg_rd; input cfg; //0: cfg0, 1: cfg1 input [31:0] addr; //{Bus No, Dev. No, Function No, 4'h0, Ext Reg No, Reg No, 2'b00} input [9:0] length; input [3:0] Error_Type; begin TBRX_WAIT_FIFO[wt_cnt] = {Error_Type, CFG_RD, addr, length, HEAD_3DW, TBRX_TD, TBRX_EP, First_DW_BE, 3'h0, cfg, 11'd0}; TBRX_FIFO_TC[wt_cnt] = 0; wt_cnt = wt_cnt + 1; end endtask // ============================================================================= // ============================================================================= task tbrx_cfg_wr; input cfg; //0: cfg0, 1: cfg1 input [31:0] addr; //{Bus No, Dev. No, Function No, 4'h0, Ext Reg No, Reg No, 2'b00} input [9:0] length; input [3:0] Error_Type; begin //addr = {Bus No, Dev. No, Function No, 4'h0, Ext Reg No, Reg No, 2'b00} TBRX_WAIT_FIFO[wt_cnt] = {Error_Type, CFG_WR, addr, length, HEAD_3DW, TBRX_TD, TBRX_EP, First_DW_BE, 3'h0, cfg, 11'd0}; TBRX_FIFO_TC[wt_cnt] = 0; wt_cnt = wt_cnt + 1; end endtask // ============================================================================= // ============================================================================= task tbrx_io_rd; input [31:0] addr; input [9:0] length; input [3:0] Error_Type; begin TBRX_WAIT_FIFO[wt_cnt] = {Error_Type, IO_RD, addr, length, HEAD_3DW, TBRX_TD, TBRX_EP, First_DW_BE, 4'h0, 11'd0}; TBRX_FIFO_TC[wt_cnt] = 0; wt_cnt = wt_cnt + 1; end endtask // ============================================================================= // ============================================================================= task tbrx_io_wr; input [31:0] addr; input [9:0] length; input [3:0] Error_Type; begin TBRX_WAIT_FIFO[wt_cnt] = {Error_Type, IO_WR, addr, length, HEAD_3DW, TBRX_TD, TBRX_EP, First_DW_BE, 4'h0, 11'd0}; TBRX_FIFO_TC[wt_cnt] = 0; wt_cnt = wt_cnt + 1; end endtask // ============================================================================= // ============================================================================= task tbrx_cpl; input [11:0] byte_cnt; input [6:0] lower_addr; input [2:0] status; input [9:0] length; input [3:0] Error_Type; begin TBRX_WAIT_FIFO[wt_cnt] = {Error_Type, CPL, byte_cnt, lower_addr, status, 10'd0, length, HEAD_3DW, TBRX_TD, TBRX_EP, 8'h0, 11'd0}; TBRX_FIFO_TC[wt_cnt] = 0; wt_cnt = wt_cnt + 1; end endtask // ============================================================================= // ============================================================================= task tbrx_cpl_d; input [11:0] byte_cnt; input [6:0] lower_addr; input [2:0] status; input [9:0] length; input [3:0] Error_Type; begin TBRX_WAIT_FIFO[wt_cnt] = {Error_Type, CPL_D, byte_cnt, lower_addr, status, 10'd0, length, HEAD_3DW, TBRX_TD, TBRX_EP, 8'h0, 11'd0}; TBRX_FIFO_TC[wt_cnt] = 0; wt_cnt = wt_cnt + 1; end endtask // ============================================================================= // Good Pkt : User has to form the Header // Malformed Pkt : For sending a pkt with fmt & Type Error Only // ============================================================================= task tbrx_tlp; //When Giving Malformed TLP (Only fmt & Type error) input [3:0] Error_Type; input hdr_type; //3 DW or 4 DW input [31:0] h1_msb; input [31:0] h1_lsb; input [31:0] h2_msb; input [31:0] h2_lsb; begin TBRX_WAIT_FIFO[wt_cnt] = {Error_Type, TLP, h1_msb, h1_lsb}; TBRX_FIFO_TC[wt_cnt] = 0; wt_cnt = wt_cnt + 1; TBRX_WAIT_FIFO[wt_cnt] = {7'b0, hdr_type, h2_msb, h2_lsb}; TBRX_FIFO_TC[wt_cnt] = 0; wt_cnt = wt_cnt + 1; end endtask // ============================================================================= // TASKS that require TC change // ============================================================================= task tbrx_mem_rd_tc; input [2:0] tc; input [31:0] addr; input [9:0] length; input hdr_type; //3 DW or 4 DW input [3:0] Error_Type; begin TBRX_WAIT_FIFO[wt_cnt] = {Error_Type, MEM_RD, addr, length, hdr_type, TBRX_TD, TBRX_EP, First_DW_BE, 4'h0, 11'd0}; TBRX_FIFO_TC[wt_cnt] = {1'b1, tc}; wt_cnt = wt_cnt + 1; end endtask // ============================================================================= // ============================================================================= task tbrx_mem_wr_tc; input [2:0] tc; input [31:0] addr; input [9:0] length; input hdr_type; //3 DW or 4 DW input [3:0] Error_Type; begin if(length == 1) TBRX_WAIT_FIFO[wt_cnt] = {Error_Type, MEM_WR, addr, length, hdr_type, TBRX_TD, TBRX_EP, First_DW_BE, 4'h0, 11'd0}; else TBRX_WAIT_FIFO[wt_cnt] = {Error_Type, MEM_WR, addr, length, hdr_type, TBRX_TD, TBRX_EP, First_DW_BE, Last_DW_BE, 11'd0}; TBRX_FIFO_TC[wt_cnt] = {1'b1, tc}; wt_cnt = wt_cnt + 1; end endtask // ============================================================================= // FLOW CONTROL Tasks // ============================================================================= initial begin //Init Flow Control Credits ph_buf_status <= 1'b0; pd_buf_status <= 1'b0; nph_buf_status <= 1'b0; npd_buf_status <= 1'b0; cplh_buf_status <= 1'b0; cpld_buf_status <= 1'b0; ph_processed <= 1'b0; pd_processed <= 1'b0; nph_processed <= 1'b0; npd_processed <= 1'b0; cplh_processed <= 1'b0; cpld_processed <= 1'b0; pd_num <= 8'd1; npd_num <= 8'd1; cpld_num <= 8'd1; INIT_PH_FC <= 0; // Inifinite INIT_PD_FC <= 0; INIT_NPH_FC <= 0; INIT_NPD_FC <= 0; INIT_CPLH_FC <= 0; INIT_CPLD_FC <= 0; end // ============================================================================= // Setting INIT values // ============================================================================= task FC_INIT; input [1:0] type; // p/np/cpl input [7:0] hdr; input [11:0] data; begin case(type) P : begin INIT_PH_FC <= hdr; INIT_PD_FC <= data; end NP : begin INIT_NPH_FC <= hdr; INIT_NPD_FC <= data; end CPLX : begin INIT_CPLH_FC <= hdr; INIT_CPLD_FC <= data; end endcase end endtask // ============================================================================= // Asserion/Deassertion of buf_status signals // ============================================================================= task FC_BUF_STATUS; input [2:0] type; // ph/pd/nph/npd/cpl/cpld input set; // Set=1: Assert the signal , Set=0, De-assert the signal begin case(type) PH : ph_buf_status <= set; PD : pd_buf_status <= set; NPH : nph_buf_status <= set; NPD : npd_buf_status <= set; CPLH : cplh_buf_status <= set; CPLD : cpld_buf_status <= set; endcase end endtask // ============================================================================= // Asserion/Deassertion of Processed signals // Onle pulse // ============================================================================= task FC_PROCESSED; input [2:0] type; // ph/pd/nph/npd/cpl/cpld begin case(type) PH : begin ph_processed <= 1'b1; end PD : begin pd_processed <= 1'b1; pd_num <= 8'd1; end NPH : begin nph_processed <= 1'b1; end NPD : begin npd_processed <= 1'b1; npd_num <= 8'd1; end CPLH : begin cplh_processed <= 1'b1; end CPLD : begin cpld_processed <= 1'b1; cpld_num <= 8'd1; end endcase @( posedge sys_clk) case(type) PH : begin ph_processed <= 1'b0; end PD : begin pd_processed <= 1'b0; pd_num <= 8'd0; end NPH : begin nph_processed <= 1'b0; end NPD : begin npd_processed <= 1'b0; npd_num <= 8'd0; end CPLH : begin cplh_processed <= 1'b0; end CPLD : begin cpld_processed <= 1'b0; cpld_num <= 8'd0; end endcase end endtask task FC_PROCESSED_NUM; input [2:0] type; // ph/pd/nph/npd/cpl/cpld input [7:0] num; // no. of data pd/npd/cpld (no. of credits : 4DW is 1 credit) begin case(type) PH : begin ph_processed <= 1'b1; end PD : begin pd_processed <= 1'b1; pd_num <= num; end NPH : begin nph_processed <= 1'b1; end NPD : begin npd_processed <= 1'b1; npd_num <= num; end CPLH : begin cplh_processed <= 1'b1; end CPLD : begin cpld_processed <= 1'b1; cpld_num <= num; end endcase @( posedge sys_clk) case(type) PH : begin ph_processed <= 1'b0; end PD : begin pd_processed <= 1'b0; pd_num <= 8'd0; end NPH : begin nph_processed <= 1'b0; end NPD : begin npd_processed <= 1'b0; npd_num <= 8'd0; end CPLH : begin cplh_processed <= 1'b0; end CPLD : begin cpld_processed <= 1'b0; cpld_num <= 8'd0; end endcase end endtask // ============================================================================= // 1) Error Signal Assertion Check during EOP // 2) Length check for IO, CFG (length == 1) // ============================================================================= task EOP_TASK; begin // Length check for IO & CFG /* case(stored_type) IO_RD, IO_WR, CFG_RD, CFG_WR : begin if((stored_len != TBRX_LEN) && (!rx_malf_tlp)) begin //length should be 1 TBRX_Error = 1; $display ("TBRX-TC%d: **** ERROR **** : length error for IO/CFG pkt at time %0t", rx_tc, $time); end end endcase */ // Checking the Error Signal Assertion case(stored_error) ECRC_ERR : begin `ifdef ECRC if(!rx_ecrc_err) begin TBRX_Error = 1; $display ("TBRX-TC%d: **** ERROR **** : Expecting ERROR PKT", rx_tc); $display ("TBRX-TC%d: **** ERROR **** : rx_ecrc_err is NOT ASSERTED at time %0t", rx_tc, $time); end `endif end UNSUP_ERR : begin if(!rx_us_req) begin TBRX_Error = 1; $display ("TBRX-TC%d: **** ERROR **** : Expecting ERROR PKT", rx_tc); $display ("TBRX-TC%d: **** ERROR **** : rx_us_req is NOT ASSERTED at time %0t", rx_tc, $time); end end MALF_ERR : begin if(!rx_malf_tlp) begin TBRX_Error = 1; $display ("TBRX-TC%d: **** ERROR **** : Expecting ERROR PKT", rx_tc); $display ("TBRX-TC%d: **** ERROR **** : rx_malf_tlp is NOT ASSERTED at time %0t", rx_tc, $time); end end FMT_TYPE_ERR : begin if(!rx_malf_tlp && !rx_us_req) begin TBRX_Error = 1; $display ("TBRX-TC%d: **** ERROR **** : Expecting ERROR PKT", rx_tc); $display ("TBRX-TC%d: **** ERROR **** : rx_malf_tlp/rx_us_req is NOT ASSERTED at time %0t", rx_tc, $time); end end default : begin `ifdef ECRC if(rx_ecrc_err || rx_malf_tlp || rx_us_req) begin `else if(rx_malf_tlp || rx_us_req) begin `endif TBRX_Error = 1; $display ("TBRX-TC%d: **** ERROR **** : Unexpected error signal assertion for a good PKT at time %0t", rx_tc, $time); end end endcase if(!TBRX_Error && (`DEBUG==1)) begin $display ("TBRX-TC%d: SUCCESSFUL PKT TRANSFER (Pkt no:%0d) at time %0t", rx_tc, got_cnt,$time); end end endtask // ============================================================================= // Data Generation & Checking // ============================================================================= task CHECK_DATA; input [10:0] data_no; reg [31:0] data32; integer i,j; begin i = data_no*2; j = i + 1; if(TBRX_MANUAL_DATA) begin {data0, data1} = D[i]; end else if(TBRX_FIXED_PATTERN) begin case(data_no[4:0]) 0 : {data0, data1} = 32'h0000_1111; 1 : {data0, data1} = 32'h2222_3333; 2 : {data0, data1} = 32'h4444_5555; 3 : {data0, data1} = 32'h6666_7777; 4 : {data0, data1} = 32'h8888_9999; 5 : {data0, data1} = 32'hAAAA_BBBB; 6 : {data0, data1} = 32'hCCCC_DDDD; 7 : {data0, data1} = 32'hEEEE_FFFF; 8 : {data0, data1} = 32'h1010_1111; 9 : {data0, data1} = 32'h1212_1313; 10 : {data0, data1} = 32'h1414_1515; 11 : {data0, data1} = 32'h1616_1717; 12 : {data0, data1} = 32'h1818_1919; 13 : {data0, data1} = 32'h1A1A_1B1B; 14 : {data0, data1} = 32'h1C1C_1D1D; 15 : {data0, data1} = 32'h1E1E_1F1F; 16 : {data0, data1} = 32'h2020_2121; 17 : {data0, data1} = 32'h2222_2323; 18 : {data0, data1} = 32'h2424_2525; 19 : {data0, data1} = 32'h2626_2727; 20 : {data0, data1} = 32'h2828_2929; 21 : {data0, data1} = 32'h2A2A_2B2B; 22 : {data0, data1} = 32'h2C2C_2D2D; 23 : {data0, data1} = 32'h2E2E_2F2F; 24 : {data0, data1} = 32'h3030_3131; 25 : {data0, data1} = 32'h3232_3333; 26 : {data0, data1} = 32'h3434_3535; 27 : {data0, data1} = 32'h3636_3737; 28 : {data0, data1} = 32'h3838_3939; 29 : {data0, data1} = 32'h3A3A_3B3B; 30 : {data0, data1} = 32'h3C3C_3D3D; 31 : {data0, data1} = 32'h3E3E_3F3F; endcase end else begin //Default - Incremental Data data0 = i; data1 = j; end data32 = {data0, data1}; if(data32 != {rx_data_del, rx_data}) TBRX_Error = 1'b1; if(TBRX_Error) begin $display ("TBRX-TC%d: **** ERROR **** : Data Mismatch at time %0t", rx_tc, $time); $display (" DataNo=%0d, Exp data=%h, Rcvd Data=%h_%h", data_no, data32, rx_data_del, rx_data); end /****** for DEBUG $display ("TBRX-TC%d: --------- CHECK --------- at time %0t", rx_tc, $time); $display (" DataNo=%0d, Exp data=%h, Rcvd Data=%h_%h", data_no, data32, rx_data_del, rx_data); ******/ end endtask // ============================================================================= // ERROR Conditions : Simulation stopped // ============================================================================= always @(TBRX_Error) begin if(TBRX_Error) begin repeat (100) @(posedge sys_clk); $display ("TBRX: -- Sim stopped by TBRX -- at time %0t", $time); $finish; end end // ============================================================================= task ERROR_TASK; begin $display ("TBRX-TC%d: **** ERROR **** : HEADER Mismatch at time %0t", rx_tc, $time); case(Error_code) TYPE_C : $display (" TYPE error: Exp TYPE=%b, Rcvd TYPE=%b",type, typex); FMT_C : $display (" FMT error: Exp FMT=%b, Rcvd FMT=%b", fmt, fmtx); TC_C : $display (" TC/VC error: Exp TC=%d, Rcvd TC=%d", TC,TCx); TD_C : $display (" TD error: Exp TD=%b, Rcvd TD=%b", TD,TDx); EP_C : $display (" EP error: Exp EP=%b, Rcvd EP=%b", EP,EPx); ATTR_C : $display (" ATTR error: Exp ATTR=%b, Rcvd ATTR=%b", ATTR, ATTRx); LEN_C : $display (" Length error: Exp Length=%d, Rcvd Length=%d", len,lenx); RSRV_C : $display (" RESERVED Bits error"); REQ_ID_C : $display (" REQ_ID error: Exp REQ_ID=%h, Rcvd REQ_ID=%h", TBRX_REQ_ID, TBRX_REQ_IDx); TAG_C : $display (" TAG error: Exp TAG=%h, Rcvd TAG=%h", TAG,TAGx); LastDW_BE_C : $display (" LastDW_BE error: Exp LastDW_BE=%h, Rcvd LastDW_BE=%h", LastDW_BE, LastDW_BEx); FirstDW_BE_C : $display (" FirstDW_BE error: Exp FirstDW_BE=%h, Rcvd FirstDW_BE=%h", FirstDW_BE, FirstDW_BEx); ADDR_C : $display (" Addr error: Exp Addr=%h, Rcvd Addr=%h", wt_addr, wt_addrx); //DATA_C : $display (" Data error: Exp Data=%h, Rcvd Data=%h", FirstData, FirstDatax); MSG_C : $display (" MSG Type error: Exp MSG Type=%h, Rcvd MSG Type=%h", TBRX_MSG_TYPE,TBRX_MSG_TYPEx); MSGCODE_C : $display (" MSG CODE error: Exp MSG Code=%h, Rcvd MSG Code=%h", TBRX_MSG_CODE,TBRX_MSG_CODEx); CPL_ID_C : $display (" CPL ID error: Exp CPL ID=%h, Rcvd CPL ID=%h", TBRX_CPL_ID, TBRX_CPL_IDx); STATUS_C : $display (" CPL Status Field error: Exp Status Field=%h, Rcvd Status Field=%h", wt_status,wt_statusx); BCM_C : $display (" CPL BCM error: Exp BCM=%h, Rcvd BCM=%h", TBRX_BCM, TBRX_BCMx); BYTECNT_C : $display (" CPL ByteCount error: Exp ByteCount=%h, Rcvd ByteCount=%h", wt_bytecnt, wt_bytecntx); LOWERADDR_C : $display (" CPL LowerAddr error: Exp LowerAddr=%h, Rcvd LowerAddr=%h", wt_loweraddr, wt_loweraddrx); endcase $display ("\n"); end endtask endmodule
module tracking_camera_system ( output wire altpll_0_c0_clk, // altpll_0_c0.clk inout wire [7:0] character_lcd_0_external_interface_DATA, // character_lcd_0_external_interface.DATA output wire character_lcd_0_external_interface_ON, // .ON output wire character_lcd_0_external_interface_BLON, // .BLON output wire character_lcd_0_external_interface_EN, // .EN output wire character_lcd_0_external_interface_RS, // .RS output wire character_lcd_0_external_interface_RW, // .RW input wire switch_0_external_connection_export, // switch_0_external_connection.export output wire servo_pwm_0_conduit_end_0_export, // servo_pwm_0_conduit_end_0.export input wire reset_reset_n, // reset.reset_n input wire switch_external_connection_export, // switch_external_connection.export input wire clk_clk, // clk.clk output wire [11:0] sdram_0_wire_addr, // sdram_0_wire.addr output wire [1:0] sdram_0_wire_ba, // .ba output wire sdram_0_wire_cas_n, // .cas_n output wire sdram_0_wire_cke, // .cke output wire sdram_0_wire_cs_n, // .cs_n inout wire [15:0] sdram_0_wire_dq, // .dq output wire [1:0] sdram_0_wire_dqm, // .dqm output wire sdram_0_wire_ras_n, // .ras_n output wire sdram_0_wire_we_n, // .we_n output wire [7:0] green_leds_external_connection_export, // green_leds_external_connection.export inout wire [15:0] sram_0_external_interface_DQ, // sram_0_external_interface.DQ output wire [17:0] sram_0_external_interface_ADDR, // .ADDR output wire sram_0_external_interface_LB_N, // .LB_N output wire sram_0_external_interface_UB_N, // .UB_N output wire sram_0_external_interface_CE_N, // .CE_N output wire sram_0_external_interface_OE_N, // .OE_N output wire sram_0_external_interface_WE_N // .WE_N ); wire altpll_0_c1_clk; // altpll_0:c1 -> [addr_router:clk, addr_router_001:clk, burst_adapter:clk, burst_adapter_001:clk, burst_adapter_002:clk, character_lcd_0:clk, character_lcd_0_avalon_lcd_slave_translator:clk, character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent:clk, character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:clk, cmd_xbar_demux:clk, cmd_xbar_demux_001:clk, cmd_xbar_mux:clk, cmd_xbar_mux_001:clk, cmd_xbar_mux_002:clk, cmd_xbar_mux_003:clk, crosser:in_clk, crosser_001:out_clk, green_leds:clk, green_leds_s1_translator:clk, green_leds_s1_translator_avalon_universal_slave_0_agent:clk, green_leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:clk, id_router:clk, id_router_001:clk, id_router_002:clk, id_router_003:clk, id_router_005:clk, id_router_006:clk, id_router_007:clk, id_router_008:clk, id_router_009:clk, id_router_010:clk, id_router_011:clk, id_router_012:clk, irq_mapper:clk, jtag_uart_0:clk, jtag_uart_0_avalon_jtag_slave_translator:clk, jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:clk, jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:clk, limiter:clk, limiter_001:clk, nios2_qsys_0:clk, nios2_qsys_0_data_master_translator:clk, nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent:clk, nios2_qsys_0_instruction_master_translator:clk, nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent:clk, nios2_qsys_0_jtag_debug_module_translator:clk, nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:clk, nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:clk, onchip_memory2_0:clk, onchip_memory2_0_s1_translator:clk, onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:clk, onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:clk, rsp_xbar_demux:clk, rsp_xbar_demux_001:clk, rsp_xbar_demux_002:clk, rsp_xbar_demux_003:clk, rsp_xbar_demux_005:clk, rsp_xbar_demux_006:clk, rsp_xbar_demux_007:clk, rsp_xbar_demux_008:clk, rsp_xbar_demux_009:clk, rsp_xbar_demux_010:clk, rsp_xbar_demux_011:clk, rsp_xbar_demux_012:clk, rsp_xbar_mux:clk, rsp_xbar_mux_001:clk, rst_controller:clk, sdram_0:clk, sdram_0_s1_translator:clk, sdram_0_s1_translator_avalon_universal_slave_0_agent:clk, sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:clk, servo_pwm_0:clk, servo_pwm_0_s0_translator:clk, servo_pwm_0_s0_translator_avalon_universal_slave_0_agent:clk, servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_rsp_fifo:clk, sram_0:clk, sram_0_avalon_sram_slave_translator:clk, sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:clk, sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:clk, switch:clk, switch_0:clk, switch_0_s1_translator:clk, switch_0_s1_translator_avalon_universal_slave_0_agent:clk, switch_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:clk, switch_s1_translator:clk, switch_s1_translator_avalon_universal_slave_0_agent:clk, switch_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:clk, sysid_qsys_0:clock, sysid_qsys_0_control_slave_translator:clk, sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:clk, sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:clk, timer_0:clk, timer_0_s1_translator:clk, timer_0_s1_translator_avalon_universal_slave_0_agent:clk, timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:clk, width_adapter:clk, width_adapter_001:clk, width_adapter_002:clk, width_adapter_003:clk, width_adapter_004:clk, width_adapter_005:clk] wire nios2_qsys_0_instruction_master_waitrequest; // nios2_qsys_0_instruction_master_translator:av_waitrequest -> nios2_qsys_0:i_waitrequest wire [24:0] nios2_qsys_0_instruction_master_address; // nios2_qsys_0:i_address -> nios2_qsys_0_instruction_master_translator:av_address wire nios2_qsys_0_instruction_master_read; // nios2_qsys_0:i_read -> nios2_qsys_0_instruction_master_translator:av_read wire [31:0] nios2_qsys_0_instruction_master_readdata; // nios2_qsys_0_instruction_master_translator:av_readdata -> nios2_qsys_0:i_readdata wire nios2_qsys_0_instruction_master_readdatavalid; // nios2_qsys_0_instruction_master_translator:av_readdatavalid -> nios2_qsys_0:i_readdatavalid wire nios2_qsys_0_data_master_waitrequest; // nios2_qsys_0_data_master_translator:av_waitrequest -> nios2_qsys_0:d_waitrequest wire [31:0] nios2_qsys_0_data_master_writedata; // nios2_qsys_0:d_writedata -> nios2_qsys_0_data_master_translator:av_writedata wire [24:0] nios2_qsys_0_data_master_address; // nios2_qsys_0:d_address -> nios2_qsys_0_data_master_translator:av_address wire nios2_qsys_0_data_master_write; // nios2_qsys_0:d_write -> nios2_qsys_0_data_master_translator:av_write wire nios2_qsys_0_data_master_read; // nios2_qsys_0:d_read -> nios2_qsys_0_data_master_translator:av_read wire [31:0] nios2_qsys_0_data_master_readdata; // nios2_qsys_0_data_master_translator:av_readdata -> nios2_qsys_0:d_readdata wire nios2_qsys_0_data_master_debugaccess; // nios2_qsys_0:jtag_debug_module_debugaccess_to_roms -> nios2_qsys_0_data_master_translator:av_debugaccess wire nios2_qsys_0_data_master_readdatavalid; // nios2_qsys_0_data_master_translator:av_readdatavalid -> nios2_qsys_0:d_readdatavalid wire [3:0] nios2_qsys_0_data_master_byteenable; // nios2_qsys_0:d_byteenable -> nios2_qsys_0_data_master_translator:av_byteenable wire [31:0] nios2_qsys_0_jtag_debug_module_translator_avalon_anti_slave_0_writedata; // nios2_qsys_0_jtag_debug_module_translator:av_writedata -> nios2_qsys_0:jtag_debug_module_writedata wire [8:0] nios2_qsys_0_jtag_debug_module_translator_avalon_anti_slave_0_address; // nios2_qsys_0_jtag_debug_module_translator:av_address -> nios2_qsys_0:jtag_debug_module_address wire nios2_qsys_0_jtag_debug_module_translator_avalon_anti_slave_0_chipselect; // nios2_qsys_0_jtag_debug_module_translator:av_chipselect -> nios2_qsys_0:jtag_debug_module_select wire nios2_qsys_0_jtag_debug_module_translator_avalon_anti_slave_0_write; // nios2_qsys_0_jtag_debug_module_translator:av_write -> nios2_qsys_0:jtag_debug_module_write wire [31:0] nios2_qsys_0_jtag_debug_module_translator_avalon_anti_slave_0_readdata; // nios2_qsys_0:jtag_debug_module_readdata -> nios2_qsys_0_jtag_debug_module_translator:av_readdata wire nios2_qsys_0_jtag_debug_module_translator_avalon_anti_slave_0_begintransfer; // nios2_qsys_0_jtag_debug_module_translator:av_begintransfer -> nios2_qsys_0:jtag_debug_module_begintransfer wire nios2_qsys_0_jtag_debug_module_translator_avalon_anti_slave_0_debugaccess; // nios2_qsys_0_jtag_debug_module_translator:av_debugaccess -> nios2_qsys_0:jtag_debug_module_debugaccess wire [3:0] nios2_qsys_0_jtag_debug_module_translator_avalon_anti_slave_0_byteenable; // nios2_qsys_0_jtag_debug_module_translator:av_byteenable -> nios2_qsys_0:jtag_debug_module_byteenable wire [31:0] onchip_memory2_0_s1_translator_avalon_anti_slave_0_writedata; // onchip_memory2_0_s1_translator:av_writedata -> onchip_memory2_0:writedata wire [11:0] onchip_memory2_0_s1_translator_avalon_anti_slave_0_address; // onchip_memory2_0_s1_translator:av_address -> onchip_memory2_0:address wire onchip_memory2_0_s1_translator_avalon_anti_slave_0_chipselect; // onchip_memory2_0_s1_translator:av_chipselect -> onchip_memory2_0:chipselect wire onchip_memory2_0_s1_translator_avalon_anti_slave_0_clken; // onchip_memory2_0_s1_translator:av_clken -> onchip_memory2_0:clken wire onchip_memory2_0_s1_translator_avalon_anti_slave_0_write; // onchip_memory2_0_s1_translator:av_write -> onchip_memory2_0:write wire [31:0] onchip_memory2_0_s1_translator_avalon_anti_slave_0_readdata; // onchip_memory2_0:readdata -> onchip_memory2_0_s1_translator:av_readdata wire [3:0] onchip_memory2_0_s1_translator_avalon_anti_slave_0_byteenable; // onchip_memory2_0_s1_translator:av_byteenable -> onchip_memory2_0:byteenable wire sdram_0_s1_translator_avalon_anti_slave_0_waitrequest; // sdram_0:za_waitrequest -> sdram_0_s1_translator:av_waitrequest wire [15:0] sdram_0_s1_translator_avalon_anti_slave_0_writedata; // sdram_0_s1_translator:av_writedata -> sdram_0:az_data wire [21:0] sdram_0_s1_translator_avalon_anti_slave_0_address; // sdram_0_s1_translator:av_address -> sdram_0:az_addr wire sdram_0_s1_translator_avalon_anti_slave_0_chipselect; // sdram_0_s1_translator:av_chipselect -> sdram_0:az_cs wire sdram_0_s1_translator_avalon_anti_slave_0_write; // sdram_0_s1_translator:av_write -> sdram_0:az_wr_n wire sdram_0_s1_translator_avalon_anti_slave_0_read; // sdram_0_s1_translator:av_read -> sdram_0:az_rd_n wire [15:0] sdram_0_s1_translator_avalon_anti_slave_0_readdata; // sdram_0:za_data -> sdram_0_s1_translator:av_readdata wire sdram_0_s1_translator_avalon_anti_slave_0_readdatavalid; // sdram_0:za_valid -> sdram_0_s1_translator:av_readdatavalid wire [1:0] sdram_0_s1_translator_avalon_anti_slave_0_byteenable; // sdram_0_s1_translator:av_byteenable -> sdram_0:az_be_n wire [15:0] sram_0_avalon_sram_slave_translator_avalon_anti_slave_0_writedata; // sram_0_avalon_sram_slave_translator:av_writedata -> sram_0:writedata wire [17:0] sram_0_avalon_sram_slave_translator_avalon_anti_slave_0_address; // sram_0_avalon_sram_slave_translator:av_address -> sram_0:address wire sram_0_avalon_sram_slave_translator_avalon_anti_slave_0_write; // sram_0_avalon_sram_slave_translator:av_write -> sram_0:write wire sram_0_avalon_sram_slave_translator_avalon_anti_slave_0_read; // sram_0_avalon_sram_slave_translator:av_read -> sram_0:read wire [15:0] sram_0_avalon_sram_slave_translator_avalon_anti_slave_0_readdata; // sram_0:readdata -> sram_0_avalon_sram_slave_translator:av_readdata wire sram_0_avalon_sram_slave_translator_avalon_anti_slave_0_readdatavalid; // sram_0:readdatavalid -> sram_0_avalon_sram_slave_translator:av_readdatavalid wire [1:0] sram_0_avalon_sram_slave_translator_avalon_anti_slave_0_byteenable; // sram_0_avalon_sram_slave_translator:av_byteenable -> sram_0:byteenable wire [31:0] altpll_0_pll_slave_translator_avalon_anti_slave_0_writedata; // altpll_0_pll_slave_translator:av_writedata -> altpll_0:writedata wire [1:0] altpll_0_pll_slave_translator_avalon_anti_slave_0_address; // altpll_0_pll_slave_translator:av_address -> altpll_0:address wire altpll_0_pll_slave_translator_avalon_anti_slave_0_write; // altpll_0_pll_slave_translator:av_write -> altpll_0:write wire altpll_0_pll_slave_translator_avalon_anti_slave_0_read; // altpll_0_pll_slave_translator:av_read -> altpll_0:read wire [31:0] altpll_0_pll_slave_translator_avalon_anti_slave_0_readdata; // altpll_0:readdata -> altpll_0_pll_slave_translator:av_readdata wire [0:0] sysid_qsys_0_control_slave_translator_avalon_anti_slave_0_address; // sysid_qsys_0_control_slave_translator:av_address -> sysid_qsys_0:address wire [31:0] sysid_qsys_0_control_slave_translator_avalon_anti_slave_0_readdata; // sysid_qsys_0:readdata -> sysid_qsys_0_control_slave_translator:av_readdata wire [15:0] timer_0_s1_translator_avalon_anti_slave_0_writedata; // timer_0_s1_translator:av_writedata -> timer_0:writedata wire [2:0] timer_0_s1_translator_avalon_anti_slave_0_address; // timer_0_s1_translator:av_address -> timer_0:address wire timer_0_s1_translator_avalon_anti_slave_0_chipselect; // timer_0_s1_translator:av_chipselect -> timer_0:chipselect wire timer_0_s1_translator_avalon_anti_slave_0_write; // timer_0_s1_translator:av_write -> timer_0:write_n wire [15:0] timer_0_s1_translator_avalon_anti_slave_0_readdata; // timer_0:readdata -> timer_0_s1_translator:av_readdata wire jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_waitrequest; // jtag_uart_0:av_waitrequest -> jtag_uart_0_avalon_jtag_slave_translator:av_waitrequest wire [31:0] jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_writedata; // jtag_uart_0_avalon_jtag_slave_translator:av_writedata -> jtag_uart_0:av_writedata wire [0:0] jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_address; // jtag_uart_0_avalon_jtag_slave_translator:av_address -> jtag_uart_0:av_address wire jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_chipselect; // jtag_uart_0_avalon_jtag_slave_translator:av_chipselect -> jtag_uart_0:av_chipselect wire jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_write; // jtag_uart_0_avalon_jtag_slave_translator:av_write -> jtag_uart_0:av_write_n wire jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_read; // jtag_uart_0_avalon_jtag_slave_translator:av_read -> jtag_uart_0:av_read_n wire [31:0] jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_readdata; // jtag_uart_0:av_readdata -> jtag_uart_0_avalon_jtag_slave_translator:av_readdata wire character_lcd_0_avalon_lcd_slave_translator_avalon_anti_slave_0_waitrequest; // character_lcd_0:waitrequest -> character_lcd_0_avalon_lcd_slave_translator:av_waitrequest wire [7:0] character_lcd_0_avalon_lcd_slave_translator_avalon_anti_slave_0_writedata; // character_lcd_0_avalon_lcd_slave_translator:av_writedata -> character_lcd_0:writedata wire [0:0] character_lcd_0_avalon_lcd_slave_translator_avalon_anti_slave_0_address; // character_lcd_0_avalon_lcd_slave_translator:av_address -> character_lcd_0:address wire character_lcd_0_avalon_lcd_slave_translator_avalon_anti_slave_0_chipselect; // character_lcd_0_avalon_lcd_slave_translator:av_chipselect -> character_lcd_0:chipselect wire character_lcd_0_avalon_lcd_slave_translator_avalon_anti_slave_0_write; // character_lcd_0_avalon_lcd_slave_translator:av_write -> character_lcd_0:write wire character_lcd_0_avalon_lcd_slave_translator_avalon_anti_slave_0_read; // character_lcd_0_avalon_lcd_slave_translator:av_read -> character_lcd_0:read wire [7:0] character_lcd_0_avalon_lcd_slave_translator_avalon_anti_slave_0_readdata; // character_lcd_0:readdata -> character_lcd_0_avalon_lcd_slave_translator:av_readdata wire [31:0] green_leds_s1_translator_avalon_anti_slave_0_writedata; // green_leds_s1_translator:av_writedata -> green_leds:writedata wire [1:0] green_leds_s1_translator_avalon_anti_slave_0_address; // green_leds_s1_translator:av_address -> green_leds:address wire green_leds_s1_translator_avalon_anti_slave_0_chipselect; // green_leds_s1_translator:av_chipselect -> green_leds:chipselect wire green_leds_s1_translator_avalon_anti_slave_0_write; // green_leds_s1_translator:av_write -> green_leds:write_n wire [31:0] green_leds_s1_translator_avalon_anti_slave_0_readdata; // green_leds:readdata -> green_leds_s1_translator:av_readdata wire [1:0] switch_s1_translator_avalon_anti_slave_0_address; // switch_s1_translator:av_address -> switch:address wire [31:0] switch_s1_translator_avalon_anti_slave_0_readdata; // switch:readdata -> switch_s1_translator:av_readdata wire [1:0] switch_0_s1_translator_avalon_anti_slave_0_address; // switch_0_s1_translator:av_address -> switch_0:address wire [31:0] switch_0_s1_translator_avalon_anti_slave_0_readdata; // switch_0:readdata -> switch_0_s1_translator:av_readdata wire [31:0] servo_pwm_0_s0_translator_avalon_anti_slave_0_writedata; // servo_pwm_0_s0_translator:av_writedata -> servo_pwm_0:avs_s0_writedata wire servo_pwm_0_s0_translator_avalon_anti_slave_0_write; // servo_pwm_0_s0_translator:av_write -> servo_pwm_0:avs_s0_write_n wire servo_pwm_0_s0_translator_avalon_anti_slave_0_read; // servo_pwm_0_s0_translator:av_read -> servo_pwm_0:avs_s0_read_n wire [31:0] servo_pwm_0_s0_translator_avalon_anti_slave_0_readdata; // servo_pwm_0:avs_s0_readdata -> servo_pwm_0_s0_translator:av_readdata wire nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_waitrequest; // nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent:av_waitrequest -> nios2_qsys_0_instruction_master_translator:uav_waitrequest wire [2:0] nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_burstcount; // nios2_qsys_0_instruction_master_translator:uav_burstcount -> nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent:av_burstcount wire [31:0] nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_writedata; // nios2_qsys_0_instruction_master_translator:uav_writedata -> nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent:av_writedata wire [24:0] nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_address; // nios2_qsys_0_instruction_master_translator:uav_address -> nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent:av_address wire nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_lock; // nios2_qsys_0_instruction_master_translator:uav_lock -> nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent:av_lock wire nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_write; // nios2_qsys_0_instruction_master_translator:uav_write -> nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent:av_write wire nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_read; // nios2_qsys_0_instruction_master_translator:uav_read -> nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent:av_read wire [31:0] nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_readdata; // nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent:av_readdata -> nios2_qsys_0_instruction_master_translator:uav_readdata wire nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_debugaccess; // nios2_qsys_0_instruction_master_translator:uav_debugaccess -> nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent:av_debugaccess wire [3:0] nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_byteenable; // nios2_qsys_0_instruction_master_translator:uav_byteenable -> nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent:av_byteenable wire nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_readdatavalid; // nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent:av_readdatavalid -> nios2_qsys_0_instruction_master_translator:uav_readdatavalid wire nios2_qsys_0_data_master_translator_avalon_universal_master_0_waitrequest; // nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent:av_waitrequest -> nios2_qsys_0_data_master_translator:uav_waitrequest wire [2:0] nios2_qsys_0_data_master_translator_avalon_universal_master_0_burstcount; // nios2_qsys_0_data_master_translator:uav_burstcount -> nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent:av_burstcount wire [31:0] nios2_qsys_0_data_master_translator_avalon_universal_master_0_writedata; // nios2_qsys_0_data_master_translator:uav_writedata -> nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent:av_writedata wire [24:0] nios2_qsys_0_data_master_translator_avalon_universal_master_0_address; // nios2_qsys_0_data_master_translator:uav_address -> nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent:av_address wire nios2_qsys_0_data_master_translator_avalon_universal_master_0_lock; // nios2_qsys_0_data_master_translator:uav_lock -> nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent:av_lock wire nios2_qsys_0_data_master_translator_avalon_universal_master_0_write; // nios2_qsys_0_data_master_translator:uav_write -> nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent:av_write wire nios2_qsys_0_data_master_translator_avalon_universal_master_0_read; // nios2_qsys_0_data_master_translator:uav_read -> nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent:av_read wire [31:0] nios2_qsys_0_data_master_translator_avalon_universal_master_0_readdata; // nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent:av_readdata -> nios2_qsys_0_data_master_translator:uav_readdata wire nios2_qsys_0_data_master_translator_avalon_universal_master_0_debugaccess; // nios2_qsys_0_data_master_translator:uav_debugaccess -> nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent:av_debugaccess wire [3:0] nios2_qsys_0_data_master_translator_avalon_universal_master_0_byteenable; // nios2_qsys_0_data_master_translator:uav_byteenable -> nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent:av_byteenable wire nios2_qsys_0_data_master_translator_avalon_universal_master_0_readdatavalid; // nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent:av_readdatavalid -> nios2_qsys_0_data_master_translator:uav_readdatavalid wire nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_waitrequest; // nios2_qsys_0_jtag_debug_module_translator:uav_waitrequest -> nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_waitrequest wire [2:0] nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_burstcount; // nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_burstcount -> nios2_qsys_0_jtag_debug_module_translator:uav_burstcount wire [31:0] nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_writedata; // nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_writedata -> nios2_qsys_0_jtag_debug_module_translator:uav_writedata wire [24:0] nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_address; // nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_address -> nios2_qsys_0_jtag_debug_module_translator:uav_address wire nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_write; // nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_write -> nios2_qsys_0_jtag_debug_module_translator:uav_write wire nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_lock; // nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_lock -> nios2_qsys_0_jtag_debug_module_translator:uav_lock wire nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_read; // nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_read -> nios2_qsys_0_jtag_debug_module_translator:uav_read wire [31:0] nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_readdata; // nios2_qsys_0_jtag_debug_module_translator:uav_readdata -> nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_readdata wire nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // nios2_qsys_0_jtag_debug_module_translator:uav_readdatavalid -> nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_readdatavalid wire nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_debugaccess; // nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_debugaccess -> nios2_qsys_0_jtag_debug_module_translator:uav_debugaccess wire [3:0] nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_byteenable; // nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_byteenable -> nios2_qsys_0_jtag_debug_module_translator:uav_byteenable wire nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket wire nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_valid; // nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_source_valid -> nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid wire nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket wire [100:0] nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_data; // nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_source_data -> nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data wire nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_ready; // nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_source_ready wire nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket wire nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_sink_valid wire nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket wire [100:0] nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_sink_data wire nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_sink_ready -> nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready wire nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid wire [31:0] nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data wire nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready wire onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest; // onchip_memory2_0_s1_translator:uav_waitrequest -> onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:m0_waitrequest wire [2:0] onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_burstcount; // onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:m0_burstcount -> onchip_memory2_0_s1_translator:uav_burstcount wire [31:0] onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_writedata; // onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:m0_writedata -> onchip_memory2_0_s1_translator:uav_writedata wire [24:0] onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_address; // onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:m0_address -> onchip_memory2_0_s1_translator:uav_address wire onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_write; // onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:m0_write -> onchip_memory2_0_s1_translator:uav_write wire onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_lock; // onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:m0_lock -> onchip_memory2_0_s1_translator:uav_lock wire onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_read; // onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:m0_read -> onchip_memory2_0_s1_translator:uav_read wire [31:0] onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_readdata; // onchip_memory2_0_s1_translator:uav_readdata -> onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:m0_readdata wire onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // onchip_memory2_0_s1_translator:uav_readdatavalid -> onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:m0_readdatavalid wire onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess; // onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:m0_debugaccess -> onchip_memory2_0_s1_translator:uav_debugaccess wire [3:0] onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_byteenable; // onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:m0_byteenable -> onchip_memory2_0_s1_translator:uav_byteenable wire onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket wire onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rf_source_valid; // onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:rf_source_valid -> onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid wire onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket wire [100:0] onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rf_source_data; // onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:rf_source_data -> onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data wire onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rf_source_ready; // onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:rf_source_ready wire onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket wire onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:rf_sink_valid wire onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket wire [100:0] onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:rf_sink_data wire onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:rf_sink_ready -> onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready wire onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid wire [31:0] onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data wire onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready wire sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest; // sdram_0_s1_translator:uav_waitrequest -> sdram_0_s1_translator_avalon_universal_slave_0_agent:m0_waitrequest wire [1:0] sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_burstcount; // sdram_0_s1_translator_avalon_universal_slave_0_agent:m0_burstcount -> sdram_0_s1_translator:uav_burstcount wire [15:0] sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_writedata; // sdram_0_s1_translator_avalon_universal_slave_0_agent:m0_writedata -> sdram_0_s1_translator:uav_writedata wire [24:0] sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_address; // sdram_0_s1_translator_avalon_universal_slave_0_agent:m0_address -> sdram_0_s1_translator:uav_address wire sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_write; // sdram_0_s1_translator_avalon_universal_slave_0_agent:m0_write -> sdram_0_s1_translator:uav_write wire sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_lock; // sdram_0_s1_translator_avalon_universal_slave_0_agent:m0_lock -> sdram_0_s1_translator:uav_lock wire sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_read; // sdram_0_s1_translator_avalon_universal_slave_0_agent:m0_read -> sdram_0_s1_translator:uav_read wire [15:0] sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_readdata; // sdram_0_s1_translator:uav_readdata -> sdram_0_s1_translator_avalon_universal_slave_0_agent:m0_readdata wire sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // sdram_0_s1_translator:uav_readdatavalid -> sdram_0_s1_translator_avalon_universal_slave_0_agent:m0_readdatavalid wire sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess; // sdram_0_s1_translator_avalon_universal_slave_0_agent:m0_debugaccess -> sdram_0_s1_translator:uav_debugaccess wire [1:0] sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_byteenable; // sdram_0_s1_translator_avalon_universal_slave_0_agent:m0_byteenable -> sdram_0_s1_translator:uav_byteenable wire sdram_0_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // sdram_0_s1_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket wire sdram_0_s1_translator_avalon_universal_slave_0_agent_rf_source_valid; // sdram_0_s1_translator_avalon_universal_slave_0_agent:rf_source_valid -> sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid wire sdram_0_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // sdram_0_s1_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket wire [82:0] sdram_0_s1_translator_avalon_universal_slave_0_agent_rf_source_data; // sdram_0_s1_translator_avalon_universal_slave_0_agent:rf_source_data -> sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data wire sdram_0_s1_translator_avalon_universal_slave_0_agent_rf_source_ready; // sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> sdram_0_s1_translator_avalon_universal_slave_0_agent:rf_source_ready wire sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> sdram_0_s1_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket wire sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> sdram_0_s1_translator_avalon_universal_slave_0_agent:rf_sink_valid wire sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> sdram_0_s1_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket wire [82:0] sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> sdram_0_s1_translator_avalon_universal_slave_0_agent:rf_sink_data wire sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // sdram_0_s1_translator_avalon_universal_slave_0_agent:rf_sink_ready -> sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready wire sdram_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // sdram_0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> sdram_0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid wire [15:0] sdram_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // sdram_0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> sdram_0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data wire sdram_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // sdram_0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> sdram_0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready wire sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest; // sram_0_avalon_sram_slave_translator:uav_waitrequest -> sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:m0_waitrequest wire [1:0] sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_burstcount; // sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:m0_burstcount -> sram_0_avalon_sram_slave_translator:uav_burstcount wire [15:0] sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_writedata; // sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:m0_writedata -> sram_0_avalon_sram_slave_translator:uav_writedata wire [24:0] sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_address; // sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:m0_address -> sram_0_avalon_sram_slave_translator:uav_address wire sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_write; // sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:m0_write -> sram_0_avalon_sram_slave_translator:uav_write wire sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_lock; // sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:m0_lock -> sram_0_avalon_sram_slave_translator:uav_lock wire sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_read; // sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:m0_read -> sram_0_avalon_sram_slave_translator:uav_read wire [15:0] sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_readdata; // sram_0_avalon_sram_slave_translator:uav_readdata -> sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:m0_readdata wire sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // sram_0_avalon_sram_slave_translator:uav_readdatavalid -> sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:m0_readdatavalid wire sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess; // sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:m0_debugaccess -> sram_0_avalon_sram_slave_translator:uav_debugaccess wire [1:0] sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_byteenable; // sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:m0_byteenable -> sram_0_avalon_sram_slave_translator:uav_byteenable wire sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket wire sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rf_source_valid; // sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:rf_source_valid -> sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid wire sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket wire [82:0] sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rf_source_data; // sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:rf_source_data -> sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data wire sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rf_source_ready; // sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:rf_source_ready wire sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket wire sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:rf_sink_valid wire sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket wire [82:0] sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:rf_sink_data wire sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:rf_sink_ready -> sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready wire sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid wire [15:0] sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data wire sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready wire altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest; // altpll_0_pll_slave_translator:uav_waitrequest -> altpll_0_pll_slave_translator_avalon_universal_slave_0_agent:m0_waitrequest wire [2:0] altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_m0_burstcount; // altpll_0_pll_slave_translator_avalon_universal_slave_0_agent:m0_burstcount -> altpll_0_pll_slave_translator:uav_burstcount wire [31:0] altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_m0_writedata; // altpll_0_pll_slave_translator_avalon_universal_slave_0_agent:m0_writedata -> altpll_0_pll_slave_translator:uav_writedata wire [24:0] altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_m0_address; // altpll_0_pll_slave_translator_avalon_universal_slave_0_agent:m0_address -> altpll_0_pll_slave_translator:uav_address wire altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_m0_write; // altpll_0_pll_slave_translator_avalon_universal_slave_0_agent:m0_write -> altpll_0_pll_slave_translator:uav_write wire altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_m0_lock; // altpll_0_pll_slave_translator_avalon_universal_slave_0_agent:m0_lock -> altpll_0_pll_slave_translator:uav_lock wire altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_m0_read; // altpll_0_pll_slave_translator_avalon_universal_slave_0_agent:m0_read -> altpll_0_pll_slave_translator:uav_read wire [31:0] altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_m0_readdata; // altpll_0_pll_slave_translator:uav_readdata -> altpll_0_pll_slave_translator_avalon_universal_slave_0_agent:m0_readdata wire altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // altpll_0_pll_slave_translator:uav_readdatavalid -> altpll_0_pll_slave_translator_avalon_universal_slave_0_agent:m0_readdatavalid wire altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess; // altpll_0_pll_slave_translator_avalon_universal_slave_0_agent:m0_debugaccess -> altpll_0_pll_slave_translator:uav_debugaccess wire [3:0] altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_m0_byteenable; // altpll_0_pll_slave_translator_avalon_universal_slave_0_agent:m0_byteenable -> altpll_0_pll_slave_translator:uav_byteenable wire altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // altpll_0_pll_slave_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket wire altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rf_source_valid; // altpll_0_pll_slave_translator_avalon_universal_slave_0_agent:rf_source_valid -> altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid wire altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // altpll_0_pll_slave_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket wire [100:0] altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rf_source_data; // altpll_0_pll_slave_translator_avalon_universal_slave_0_agent:rf_source_data -> altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data wire altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rf_source_ready; // altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> altpll_0_pll_slave_translator_avalon_universal_slave_0_agent:rf_source_ready wire altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> altpll_0_pll_slave_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket wire altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> altpll_0_pll_slave_translator_avalon_universal_slave_0_agent:rf_sink_valid wire altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> altpll_0_pll_slave_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket wire [100:0] altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> altpll_0_pll_slave_translator_avalon_universal_slave_0_agent:rf_sink_data wire altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // altpll_0_pll_slave_translator_avalon_universal_slave_0_agent:rf_sink_ready -> altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready wire altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // altpll_0_pll_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo:in_valid wire [31:0] altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // altpll_0_pll_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo:in_data wire altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo:in_ready -> altpll_0_pll_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready wire altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_out_valid; // altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo:out_valid -> altpll_0_pll_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid wire [31:0] altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_out_data; // altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo:out_data -> altpll_0_pll_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data wire altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_out_ready; // altpll_0_pll_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo:out_ready wire sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest; // sysid_qsys_0_control_slave_translator:uav_waitrequest -> sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:m0_waitrequest wire [2:0] sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_burstcount; // sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:m0_burstcount -> sysid_qsys_0_control_slave_translator:uav_burstcount wire [31:0] sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_writedata; // sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:m0_writedata -> sysid_qsys_0_control_slave_translator:uav_writedata wire [24:0] sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_address; // sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:m0_address -> sysid_qsys_0_control_slave_translator:uav_address wire sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_write; // sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:m0_write -> sysid_qsys_0_control_slave_translator:uav_write wire sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_lock; // sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:m0_lock -> sysid_qsys_0_control_slave_translator:uav_lock wire sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_read; // sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:m0_read -> sysid_qsys_0_control_slave_translator:uav_read wire [31:0] sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_readdata; // sysid_qsys_0_control_slave_translator:uav_readdata -> sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:m0_readdata wire sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // sysid_qsys_0_control_slave_translator:uav_readdatavalid -> sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:m0_readdatavalid wire sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess; // sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:m0_debugaccess -> sysid_qsys_0_control_slave_translator:uav_debugaccess wire [3:0] sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_byteenable; // sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:m0_byteenable -> sysid_qsys_0_control_slave_translator:uav_byteenable wire sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket wire sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rf_source_valid; // sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:rf_source_valid -> sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid wire sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket wire [100:0] sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rf_source_data; // sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:rf_source_data -> sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data wire sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rf_source_ready; // sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:rf_source_ready wire sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket wire sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:rf_sink_valid wire sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket wire [100:0] sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:rf_sink_data wire sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:rf_sink_ready -> sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready wire sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid wire [31:0] sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data wire sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready wire timer_0_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest; // timer_0_s1_translator:uav_waitrequest -> timer_0_s1_translator_avalon_universal_slave_0_agent:m0_waitrequest wire [2:0] timer_0_s1_translator_avalon_universal_slave_0_agent_m0_burstcount; // timer_0_s1_translator_avalon_universal_slave_0_agent:m0_burstcount -> timer_0_s1_translator:uav_burstcount wire [31:0] timer_0_s1_translator_avalon_universal_slave_0_agent_m0_writedata; // timer_0_s1_translator_avalon_universal_slave_0_agent:m0_writedata -> timer_0_s1_translator:uav_writedata wire [24:0] timer_0_s1_translator_avalon_universal_slave_0_agent_m0_address; // timer_0_s1_translator_avalon_universal_slave_0_agent:m0_address -> timer_0_s1_translator:uav_address wire timer_0_s1_translator_avalon_universal_slave_0_agent_m0_write; // timer_0_s1_translator_avalon_universal_slave_0_agent:m0_write -> timer_0_s1_translator:uav_write wire timer_0_s1_translator_avalon_universal_slave_0_agent_m0_lock; // timer_0_s1_translator_avalon_universal_slave_0_agent:m0_lock -> timer_0_s1_translator:uav_lock wire timer_0_s1_translator_avalon_universal_slave_0_agent_m0_read; // timer_0_s1_translator_avalon_universal_slave_0_agent:m0_read -> timer_0_s1_translator:uav_read wire [31:0] timer_0_s1_translator_avalon_universal_slave_0_agent_m0_readdata; // timer_0_s1_translator:uav_readdata -> timer_0_s1_translator_avalon_universal_slave_0_agent:m0_readdata wire timer_0_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // timer_0_s1_translator:uav_readdatavalid -> timer_0_s1_translator_avalon_universal_slave_0_agent:m0_readdatavalid wire timer_0_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess; // timer_0_s1_translator_avalon_universal_slave_0_agent:m0_debugaccess -> timer_0_s1_translator:uav_debugaccess wire [3:0] timer_0_s1_translator_avalon_universal_slave_0_agent_m0_byteenable; // timer_0_s1_translator_avalon_universal_slave_0_agent:m0_byteenable -> timer_0_s1_translator:uav_byteenable wire timer_0_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // timer_0_s1_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket wire timer_0_s1_translator_avalon_universal_slave_0_agent_rf_source_valid; // timer_0_s1_translator_avalon_universal_slave_0_agent:rf_source_valid -> timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid wire timer_0_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // timer_0_s1_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket wire [100:0] timer_0_s1_translator_avalon_universal_slave_0_agent_rf_source_data; // timer_0_s1_translator_avalon_universal_slave_0_agent:rf_source_data -> timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data wire timer_0_s1_translator_avalon_universal_slave_0_agent_rf_source_ready; // timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> timer_0_s1_translator_avalon_universal_slave_0_agent:rf_source_ready wire timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> timer_0_s1_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket wire timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> timer_0_s1_translator_avalon_universal_slave_0_agent:rf_sink_valid wire timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> timer_0_s1_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket wire [100:0] timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> timer_0_s1_translator_avalon_universal_slave_0_agent:rf_sink_data wire timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // timer_0_s1_translator_avalon_universal_slave_0_agent:rf_sink_ready -> timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready wire timer_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // timer_0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> timer_0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid wire [31:0] timer_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // timer_0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> timer_0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data wire timer_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // timer_0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> timer_0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready wire jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest; // jtag_uart_0_avalon_jtag_slave_translator:uav_waitrequest -> jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_waitrequest wire [2:0] jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_burstcount; // jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_burstcount -> jtag_uart_0_avalon_jtag_slave_translator:uav_burstcount wire [31:0] jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_writedata; // jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_writedata -> jtag_uart_0_avalon_jtag_slave_translator:uav_writedata wire [24:0] jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_address; // jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_address -> jtag_uart_0_avalon_jtag_slave_translator:uav_address wire jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_write; // jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_write -> jtag_uart_0_avalon_jtag_slave_translator:uav_write wire jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_lock; // jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_lock -> jtag_uart_0_avalon_jtag_slave_translator:uav_lock wire jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_read; // jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_read -> jtag_uart_0_avalon_jtag_slave_translator:uav_read wire [31:0] jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_readdata; // jtag_uart_0_avalon_jtag_slave_translator:uav_readdata -> jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_readdata wire jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // jtag_uart_0_avalon_jtag_slave_translator:uav_readdatavalid -> jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_readdatavalid wire jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess; // jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_debugaccess -> jtag_uart_0_avalon_jtag_slave_translator:uav_debugaccess wire [3:0] jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_byteenable; // jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_byteenable -> jtag_uart_0_avalon_jtag_slave_translator:uav_byteenable wire jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket wire jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_valid; // jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rf_source_valid -> jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid wire jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket wire [100:0] jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_data; // jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rf_source_data -> jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data wire jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_ready; // jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rf_source_ready wire jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket wire jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rf_sink_valid wire jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket wire [100:0] jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rf_sink_data wire jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rf_sink_ready -> jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready wire jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid wire [31:0] jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data wire jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready wire character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest; // character_lcd_0_avalon_lcd_slave_translator:uav_waitrequest -> character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent:m0_waitrequest wire character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_m0_burstcount; // character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent:m0_burstcount -> character_lcd_0_avalon_lcd_slave_translator:uav_burstcount wire [7:0] character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_m0_writedata; // character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent:m0_writedata -> character_lcd_0_avalon_lcd_slave_translator:uav_writedata wire [24:0] character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_m0_address; // character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent:m0_address -> character_lcd_0_avalon_lcd_slave_translator:uav_address wire character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_m0_write; // character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent:m0_write -> character_lcd_0_avalon_lcd_slave_translator:uav_write wire character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_m0_lock; // character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent:m0_lock -> character_lcd_0_avalon_lcd_slave_translator:uav_lock wire character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_m0_read; // character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent:m0_read -> character_lcd_0_avalon_lcd_slave_translator:uav_read wire [7:0] character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_m0_readdata; // character_lcd_0_avalon_lcd_slave_translator:uav_readdata -> character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent:m0_readdata wire character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // character_lcd_0_avalon_lcd_slave_translator:uav_readdatavalid -> character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent:m0_readdatavalid wire character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess; // character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent:m0_debugaccess -> character_lcd_0_avalon_lcd_slave_translator:uav_debugaccess wire character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_m0_byteenable; // character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent:m0_byteenable -> character_lcd_0_avalon_lcd_slave_translator:uav_byteenable wire character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket wire character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_rf_source_valid; // character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent:rf_source_valid -> character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid wire character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket wire [73:0] character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_rf_source_data; // character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent:rf_source_data -> character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data wire character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_rf_source_ready; // character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent:rf_source_ready wire character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket wire character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent:rf_sink_valid wire character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket wire [73:0] character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent:rf_sink_data wire character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent:rf_sink_ready -> character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready wire character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid wire [7:0] character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data wire character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready wire green_leds_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest; // green_leds_s1_translator:uav_waitrequest -> green_leds_s1_translator_avalon_universal_slave_0_agent:m0_waitrequest wire [2:0] green_leds_s1_translator_avalon_universal_slave_0_agent_m0_burstcount; // green_leds_s1_translator_avalon_universal_slave_0_agent:m0_burstcount -> green_leds_s1_translator:uav_burstcount wire [31:0] green_leds_s1_translator_avalon_universal_slave_0_agent_m0_writedata; // green_leds_s1_translator_avalon_universal_slave_0_agent:m0_writedata -> green_leds_s1_translator:uav_writedata wire [24:0] green_leds_s1_translator_avalon_universal_slave_0_agent_m0_address; // green_leds_s1_translator_avalon_universal_slave_0_agent:m0_address -> green_leds_s1_translator:uav_address wire green_leds_s1_translator_avalon_universal_slave_0_agent_m0_write; // green_leds_s1_translator_avalon_universal_slave_0_agent:m0_write -> green_leds_s1_translator:uav_write wire green_leds_s1_translator_avalon_universal_slave_0_agent_m0_lock; // green_leds_s1_translator_avalon_universal_slave_0_agent:m0_lock -> green_leds_s1_translator:uav_lock wire green_leds_s1_translator_avalon_universal_slave_0_agent_m0_read; // green_leds_s1_translator_avalon_universal_slave_0_agent:m0_read -> green_leds_s1_translator:uav_read wire [31:0] green_leds_s1_translator_avalon_universal_slave_0_agent_m0_readdata; // green_leds_s1_translator:uav_readdata -> green_leds_s1_translator_avalon_universal_slave_0_agent:m0_readdata wire green_leds_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // green_leds_s1_translator:uav_readdatavalid -> green_leds_s1_translator_avalon_universal_slave_0_agent:m0_readdatavalid wire green_leds_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess; // green_leds_s1_translator_avalon_universal_slave_0_agent:m0_debugaccess -> green_leds_s1_translator:uav_debugaccess wire [3:0] green_leds_s1_translator_avalon_universal_slave_0_agent_m0_byteenable; // green_leds_s1_translator_avalon_universal_slave_0_agent:m0_byteenable -> green_leds_s1_translator:uav_byteenable wire green_leds_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // green_leds_s1_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> green_leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket wire green_leds_s1_translator_avalon_universal_slave_0_agent_rf_source_valid; // green_leds_s1_translator_avalon_universal_slave_0_agent:rf_source_valid -> green_leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid wire green_leds_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // green_leds_s1_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> green_leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket wire [100:0] green_leds_s1_translator_avalon_universal_slave_0_agent_rf_source_data; // green_leds_s1_translator_avalon_universal_slave_0_agent:rf_source_data -> green_leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data wire green_leds_s1_translator_avalon_universal_slave_0_agent_rf_source_ready; // green_leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> green_leds_s1_translator_avalon_universal_slave_0_agent:rf_source_ready wire green_leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // green_leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> green_leds_s1_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket wire green_leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // green_leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> green_leds_s1_translator_avalon_universal_slave_0_agent:rf_sink_valid wire green_leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // green_leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> green_leds_s1_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket wire [100:0] green_leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // green_leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> green_leds_s1_translator_avalon_universal_slave_0_agent:rf_sink_data wire green_leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // green_leds_s1_translator_avalon_universal_slave_0_agent:rf_sink_ready -> green_leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready wire green_leds_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // green_leds_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> green_leds_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid wire [31:0] green_leds_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // green_leds_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> green_leds_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data wire green_leds_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // green_leds_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> green_leds_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready wire switch_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest; // switch_s1_translator:uav_waitrequest -> switch_s1_translator_avalon_universal_slave_0_agent:m0_waitrequest wire [2:0] switch_s1_translator_avalon_universal_slave_0_agent_m0_burstcount; // switch_s1_translator_avalon_universal_slave_0_agent:m0_burstcount -> switch_s1_translator:uav_burstcount wire [31:0] switch_s1_translator_avalon_universal_slave_0_agent_m0_writedata; // switch_s1_translator_avalon_universal_slave_0_agent:m0_writedata -> switch_s1_translator:uav_writedata wire [24:0] switch_s1_translator_avalon_universal_slave_0_agent_m0_address; // switch_s1_translator_avalon_universal_slave_0_agent:m0_address -> switch_s1_translator:uav_address wire switch_s1_translator_avalon_universal_slave_0_agent_m0_write; // switch_s1_translator_avalon_universal_slave_0_agent:m0_write -> switch_s1_translator:uav_write wire switch_s1_translator_avalon_universal_slave_0_agent_m0_lock; // switch_s1_translator_avalon_universal_slave_0_agent:m0_lock -> switch_s1_translator:uav_lock wire switch_s1_translator_avalon_universal_slave_0_agent_m0_read; // switch_s1_translator_avalon_universal_slave_0_agent:m0_read -> switch_s1_translator:uav_read wire [31:0] switch_s1_translator_avalon_universal_slave_0_agent_m0_readdata; // switch_s1_translator:uav_readdata -> switch_s1_translator_avalon_universal_slave_0_agent:m0_readdata wire switch_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // switch_s1_translator:uav_readdatavalid -> switch_s1_translator_avalon_universal_slave_0_agent:m0_readdatavalid wire switch_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess; // switch_s1_translator_avalon_universal_slave_0_agent:m0_debugaccess -> switch_s1_translator:uav_debugaccess wire [3:0] switch_s1_translator_avalon_universal_slave_0_agent_m0_byteenable; // switch_s1_translator_avalon_universal_slave_0_agent:m0_byteenable -> switch_s1_translator:uav_byteenable wire switch_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // switch_s1_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> switch_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket wire switch_s1_translator_avalon_universal_slave_0_agent_rf_source_valid; // switch_s1_translator_avalon_universal_slave_0_agent:rf_source_valid -> switch_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid wire switch_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // switch_s1_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> switch_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket wire [100:0] switch_s1_translator_avalon_universal_slave_0_agent_rf_source_data; // switch_s1_translator_avalon_universal_slave_0_agent:rf_source_data -> switch_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data wire switch_s1_translator_avalon_universal_slave_0_agent_rf_source_ready; // switch_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> switch_s1_translator_avalon_universal_slave_0_agent:rf_source_ready wire switch_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // switch_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> switch_s1_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket wire switch_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // switch_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> switch_s1_translator_avalon_universal_slave_0_agent:rf_sink_valid wire switch_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // switch_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> switch_s1_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket wire [100:0] switch_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // switch_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> switch_s1_translator_avalon_universal_slave_0_agent:rf_sink_data wire switch_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // switch_s1_translator_avalon_universal_slave_0_agent:rf_sink_ready -> switch_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready wire switch_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // switch_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> switch_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid wire [31:0] switch_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // switch_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> switch_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data wire switch_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // switch_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> switch_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready wire switch_0_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest; // switch_0_s1_translator:uav_waitrequest -> switch_0_s1_translator_avalon_universal_slave_0_agent:m0_waitrequest wire [2:0] switch_0_s1_translator_avalon_universal_slave_0_agent_m0_burstcount; // switch_0_s1_translator_avalon_universal_slave_0_agent:m0_burstcount -> switch_0_s1_translator:uav_burstcount wire [31:0] switch_0_s1_translator_avalon_universal_slave_0_agent_m0_writedata; // switch_0_s1_translator_avalon_universal_slave_0_agent:m0_writedata -> switch_0_s1_translator:uav_writedata wire [24:0] switch_0_s1_translator_avalon_universal_slave_0_agent_m0_address; // switch_0_s1_translator_avalon_universal_slave_0_agent:m0_address -> switch_0_s1_translator:uav_address wire switch_0_s1_translator_avalon_universal_slave_0_agent_m0_write; // switch_0_s1_translator_avalon_universal_slave_0_agent:m0_write -> switch_0_s1_translator:uav_write wire switch_0_s1_translator_avalon_universal_slave_0_agent_m0_lock; // switch_0_s1_translator_avalon_universal_slave_0_agent:m0_lock -> switch_0_s1_translator:uav_lock wire switch_0_s1_translator_avalon_universal_slave_0_agent_m0_read; // switch_0_s1_translator_avalon_universal_slave_0_agent:m0_read -> switch_0_s1_translator:uav_read wire [31:0] switch_0_s1_translator_avalon_universal_slave_0_agent_m0_readdata; // switch_0_s1_translator:uav_readdata -> switch_0_s1_translator_avalon_universal_slave_0_agent:m0_readdata wire switch_0_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // switch_0_s1_translator:uav_readdatavalid -> switch_0_s1_translator_avalon_universal_slave_0_agent:m0_readdatavalid wire switch_0_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess; // switch_0_s1_translator_avalon_universal_slave_0_agent:m0_debugaccess -> switch_0_s1_translator:uav_debugaccess wire [3:0] switch_0_s1_translator_avalon_universal_slave_0_agent_m0_byteenable; // switch_0_s1_translator_avalon_universal_slave_0_agent:m0_byteenable -> switch_0_s1_translator:uav_byteenable wire switch_0_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // switch_0_s1_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> switch_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket wire switch_0_s1_translator_avalon_universal_slave_0_agent_rf_source_valid; // switch_0_s1_translator_avalon_universal_slave_0_agent:rf_source_valid -> switch_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid wire switch_0_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // switch_0_s1_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> switch_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket wire [100:0] switch_0_s1_translator_avalon_universal_slave_0_agent_rf_source_data; // switch_0_s1_translator_avalon_universal_slave_0_agent:rf_source_data -> switch_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data wire switch_0_s1_translator_avalon_universal_slave_0_agent_rf_source_ready; // switch_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> switch_0_s1_translator_avalon_universal_slave_0_agent:rf_source_ready wire switch_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // switch_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> switch_0_s1_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket wire switch_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // switch_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> switch_0_s1_translator_avalon_universal_slave_0_agent:rf_sink_valid wire switch_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // switch_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> switch_0_s1_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket wire [100:0] switch_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // switch_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> switch_0_s1_translator_avalon_universal_slave_0_agent:rf_sink_data wire switch_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // switch_0_s1_translator_avalon_universal_slave_0_agent:rf_sink_ready -> switch_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready wire switch_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // switch_0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> switch_0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid wire [31:0] switch_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // switch_0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> switch_0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data wire switch_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // switch_0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> switch_0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready wire servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_m0_waitrequest; // servo_pwm_0_s0_translator:uav_waitrequest -> servo_pwm_0_s0_translator_avalon_universal_slave_0_agent:m0_waitrequest wire [2:0] servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_m0_burstcount; // servo_pwm_0_s0_translator_avalon_universal_slave_0_agent:m0_burstcount -> servo_pwm_0_s0_translator:uav_burstcount wire [31:0] servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_m0_writedata; // servo_pwm_0_s0_translator_avalon_universal_slave_0_agent:m0_writedata -> servo_pwm_0_s0_translator:uav_writedata wire [24:0] servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_m0_address; // servo_pwm_0_s0_translator_avalon_universal_slave_0_agent:m0_address -> servo_pwm_0_s0_translator:uav_address wire servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_m0_write; // servo_pwm_0_s0_translator_avalon_universal_slave_0_agent:m0_write -> servo_pwm_0_s0_translator:uav_write wire servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_m0_lock; // servo_pwm_0_s0_translator_avalon_universal_slave_0_agent:m0_lock -> servo_pwm_0_s0_translator:uav_lock wire servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_m0_read; // servo_pwm_0_s0_translator_avalon_universal_slave_0_agent:m0_read -> servo_pwm_0_s0_translator:uav_read wire [31:0] servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_m0_readdata; // servo_pwm_0_s0_translator:uav_readdata -> servo_pwm_0_s0_translator_avalon_universal_slave_0_agent:m0_readdata wire servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // servo_pwm_0_s0_translator:uav_readdatavalid -> servo_pwm_0_s0_translator_avalon_universal_slave_0_agent:m0_readdatavalid wire servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_m0_debugaccess; // servo_pwm_0_s0_translator_avalon_universal_slave_0_agent:m0_debugaccess -> servo_pwm_0_s0_translator:uav_debugaccess wire [3:0] servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_m0_byteenable; // servo_pwm_0_s0_translator_avalon_universal_slave_0_agent:m0_byteenable -> servo_pwm_0_s0_translator:uav_byteenable wire servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // servo_pwm_0_s0_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket wire servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_rf_source_valid; // servo_pwm_0_s0_translator_avalon_universal_slave_0_agent:rf_source_valid -> servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid wire servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // servo_pwm_0_s0_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket wire [100:0] servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_rf_source_data; // servo_pwm_0_s0_translator_avalon_universal_slave_0_agent:rf_source_data -> servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data wire servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_rf_source_ready; // servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> servo_pwm_0_s0_translator_avalon_universal_slave_0_agent:rf_source_ready wire servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> servo_pwm_0_s0_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket wire servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> servo_pwm_0_s0_translator_avalon_universal_slave_0_agent:rf_sink_valid wire servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> servo_pwm_0_s0_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket wire [100:0] servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> servo_pwm_0_s0_translator_avalon_universal_slave_0_agent:rf_sink_data wire servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // servo_pwm_0_s0_translator_avalon_universal_slave_0_agent:rf_sink_ready -> servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready wire servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // servo_pwm_0_s0_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> servo_pwm_0_s0_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid wire [31:0] servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // servo_pwm_0_s0_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> servo_pwm_0_s0_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data wire servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // servo_pwm_0_s0_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> servo_pwm_0_s0_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready wire nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent_cp_endofpacket; // nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent:cp_endofpacket -> addr_router:sink_endofpacket wire nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent_cp_valid; // nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent:cp_valid -> addr_router:sink_valid wire nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent_cp_startofpacket; // nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent:cp_startofpacket -> addr_router:sink_startofpacket wire [99:0] nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent_cp_data; // nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent:cp_data -> addr_router:sink_data wire nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent_cp_ready; // addr_router:sink_ready -> nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent:cp_ready wire nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent_cp_endofpacket; // nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent:cp_endofpacket -> addr_router_001:sink_endofpacket wire nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent_cp_valid; // nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent:cp_valid -> addr_router_001:sink_valid wire nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent_cp_startofpacket; // nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent:cp_startofpacket -> addr_router_001:sink_startofpacket wire [99:0] nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent_cp_data; // nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent:cp_data -> addr_router_001:sink_data wire nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent_cp_ready; // addr_router_001:sink_ready -> nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent:cp_ready wire nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_endofpacket; // nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router:sink_endofpacket wire nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_valid; // nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:rp_valid -> id_router:sink_valid wire nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_startofpacket; // nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router:sink_startofpacket wire [99:0] nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_data; // nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:rp_data -> id_router:sink_data wire nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_ready; // id_router:sink_ready -> nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:rp_ready wire onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket; // onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_001:sink_endofpacket wire onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rp_valid; // onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_001:sink_valid wire onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket; // onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_001:sink_startofpacket wire [99:0] onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rp_data; // onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:rp_data -> id_router_001:sink_data wire onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_001:sink_ready -> onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:rp_ready wire sdram_0_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket; // sdram_0_s1_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_002:sink_endofpacket wire sdram_0_s1_translator_avalon_universal_slave_0_agent_rp_valid; // sdram_0_s1_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_002:sink_valid wire sdram_0_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket; // sdram_0_s1_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_002:sink_startofpacket wire [81:0] sdram_0_s1_translator_avalon_universal_slave_0_agent_rp_data; // sdram_0_s1_translator_avalon_universal_slave_0_agent:rp_data -> id_router_002:sink_data wire sdram_0_s1_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_002:sink_ready -> sdram_0_s1_translator_avalon_universal_slave_0_agent:rp_ready wire sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket; // sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_003:sink_endofpacket wire sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rp_valid; // sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_003:sink_valid wire sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket; // sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_003:sink_startofpacket wire [81:0] sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rp_data; // sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:rp_data -> id_router_003:sink_data wire sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_003:sink_ready -> sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:rp_ready wire altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket; // altpll_0_pll_slave_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_004:sink_endofpacket wire altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rp_valid; // altpll_0_pll_slave_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_004:sink_valid wire altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket; // altpll_0_pll_slave_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_004:sink_startofpacket wire [99:0] altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rp_data; // altpll_0_pll_slave_translator_avalon_universal_slave_0_agent:rp_data -> id_router_004:sink_data wire altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_004:sink_ready -> altpll_0_pll_slave_translator_avalon_universal_slave_0_agent:rp_ready wire sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket; // sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_005:sink_endofpacket wire sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rp_valid; // sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_005:sink_valid wire sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket; // sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_005:sink_startofpacket wire [99:0] sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rp_data; // sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:rp_data -> id_router_005:sink_data wire sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_005:sink_ready -> sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:rp_ready wire timer_0_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket; // timer_0_s1_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_006:sink_endofpacket wire timer_0_s1_translator_avalon_universal_slave_0_agent_rp_valid; // timer_0_s1_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_006:sink_valid wire timer_0_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket; // timer_0_s1_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_006:sink_startofpacket wire [99:0] timer_0_s1_translator_avalon_universal_slave_0_agent_rp_data; // timer_0_s1_translator_avalon_universal_slave_0_agent:rp_data -> id_router_006:sink_data wire timer_0_s1_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_006:sink_ready -> timer_0_s1_translator_avalon_universal_slave_0_agent:rp_ready wire jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket; // jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_007:sink_endofpacket wire jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_valid; // jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_007:sink_valid wire jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket; // jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_007:sink_startofpacket wire [99:0] jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_data; // jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rp_data -> id_router_007:sink_data wire jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_007:sink_ready -> jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rp_ready wire character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket; // character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_008:sink_endofpacket wire character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_rp_valid; // character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_008:sink_valid wire character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket; // character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_008:sink_startofpacket wire [72:0] character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_rp_data; // character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent:rp_data -> id_router_008:sink_data wire character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_008:sink_ready -> character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent:rp_ready wire green_leds_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket; // green_leds_s1_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_009:sink_endofpacket wire green_leds_s1_translator_avalon_universal_slave_0_agent_rp_valid; // green_leds_s1_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_009:sink_valid wire green_leds_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket; // green_leds_s1_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_009:sink_startofpacket wire [99:0] green_leds_s1_translator_avalon_universal_slave_0_agent_rp_data; // green_leds_s1_translator_avalon_universal_slave_0_agent:rp_data -> id_router_009:sink_data wire green_leds_s1_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_009:sink_ready -> green_leds_s1_translator_avalon_universal_slave_0_agent:rp_ready wire switch_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket; // switch_s1_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_010:sink_endofpacket wire switch_s1_translator_avalon_universal_slave_0_agent_rp_valid; // switch_s1_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_010:sink_valid wire switch_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket; // switch_s1_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_010:sink_startofpacket wire [99:0] switch_s1_translator_avalon_universal_slave_0_agent_rp_data; // switch_s1_translator_avalon_universal_slave_0_agent:rp_data -> id_router_010:sink_data wire switch_s1_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_010:sink_ready -> switch_s1_translator_avalon_universal_slave_0_agent:rp_ready wire switch_0_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket; // switch_0_s1_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_011:sink_endofpacket wire switch_0_s1_translator_avalon_universal_slave_0_agent_rp_valid; // switch_0_s1_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_011:sink_valid wire switch_0_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket; // switch_0_s1_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_011:sink_startofpacket wire [99:0] switch_0_s1_translator_avalon_universal_slave_0_agent_rp_data; // switch_0_s1_translator_avalon_universal_slave_0_agent:rp_data -> id_router_011:sink_data wire switch_0_s1_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_011:sink_ready -> switch_0_s1_translator_avalon_universal_slave_0_agent:rp_ready wire servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_rp_endofpacket; // servo_pwm_0_s0_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_012:sink_endofpacket wire servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_rp_valid; // servo_pwm_0_s0_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_012:sink_valid wire servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_rp_startofpacket; // servo_pwm_0_s0_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_012:sink_startofpacket wire [99:0] servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_rp_data; // servo_pwm_0_s0_translator_avalon_universal_slave_0_agent:rp_data -> id_router_012:sink_data wire servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_012:sink_ready -> servo_pwm_0_s0_translator_avalon_universal_slave_0_agent:rp_ready wire addr_router_src_endofpacket; // addr_router:src_endofpacket -> limiter:cmd_sink_endofpacket wire addr_router_src_valid; // addr_router:src_valid -> limiter:cmd_sink_valid wire addr_router_src_startofpacket; // addr_router:src_startofpacket -> limiter:cmd_sink_startofpacket wire [99:0] addr_router_src_data; // addr_router:src_data -> limiter:cmd_sink_data wire [12:0] addr_router_src_channel; // addr_router:src_channel -> limiter:cmd_sink_channel wire addr_router_src_ready; // limiter:cmd_sink_ready -> addr_router:src_ready wire limiter_rsp_src_endofpacket; // limiter:rsp_src_endofpacket -> nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent:rp_endofpacket wire limiter_rsp_src_valid; // limiter:rsp_src_valid -> nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent:rp_valid wire limiter_rsp_src_startofpacket; // limiter:rsp_src_startofpacket -> nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent:rp_startofpacket wire [99:0] limiter_rsp_src_data; // limiter:rsp_src_data -> nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent:rp_data wire [12:0] limiter_rsp_src_channel; // limiter:rsp_src_channel -> nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent:rp_channel wire limiter_rsp_src_ready; // nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent:rp_ready -> limiter:rsp_src_ready wire addr_router_001_src_endofpacket; // addr_router_001:src_endofpacket -> limiter_001:cmd_sink_endofpacket wire addr_router_001_src_valid; // addr_router_001:src_valid -> limiter_001:cmd_sink_valid wire addr_router_001_src_startofpacket; // addr_router_001:src_startofpacket -> limiter_001:cmd_sink_startofpacket wire [99:0] addr_router_001_src_data; // addr_router_001:src_data -> limiter_001:cmd_sink_data wire [12:0] addr_router_001_src_channel; // addr_router_001:src_channel -> limiter_001:cmd_sink_channel wire addr_router_001_src_ready; // limiter_001:cmd_sink_ready -> addr_router_001:src_ready wire limiter_001_rsp_src_endofpacket; // limiter_001:rsp_src_endofpacket -> nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent:rp_endofpacket wire limiter_001_rsp_src_valid; // limiter_001:rsp_src_valid -> nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent:rp_valid wire limiter_001_rsp_src_startofpacket; // limiter_001:rsp_src_startofpacket -> nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent:rp_startofpacket wire [99:0] limiter_001_rsp_src_data; // limiter_001:rsp_src_data -> nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent:rp_data wire [12:0] limiter_001_rsp_src_channel; // limiter_001:rsp_src_channel -> nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent:rp_channel wire limiter_001_rsp_src_ready; // nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent:rp_ready -> limiter_001:rsp_src_ready wire burst_adapter_source0_endofpacket; // burst_adapter:source0_endofpacket -> sdram_0_s1_translator_avalon_universal_slave_0_agent:cp_endofpacket wire burst_adapter_source0_valid; // burst_adapter:source0_valid -> sdram_0_s1_translator_avalon_universal_slave_0_agent:cp_valid wire burst_adapter_source0_startofpacket; // burst_adapter:source0_startofpacket -> sdram_0_s1_translator_avalon_universal_slave_0_agent:cp_startofpacket wire [81:0] burst_adapter_source0_data; // burst_adapter:source0_data -> sdram_0_s1_translator_avalon_universal_slave_0_agent:cp_data wire burst_adapter_source0_ready; // sdram_0_s1_translator_avalon_universal_slave_0_agent:cp_ready -> burst_adapter:source0_ready wire [12:0] burst_adapter_source0_channel; // burst_adapter:source0_channel -> sdram_0_s1_translator_avalon_universal_slave_0_agent:cp_channel wire burst_adapter_001_source0_endofpacket; // burst_adapter_001:source0_endofpacket -> sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:cp_endofpacket wire burst_adapter_001_source0_valid; // burst_adapter_001:source0_valid -> sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:cp_valid wire burst_adapter_001_source0_startofpacket; // burst_adapter_001:source0_startofpacket -> sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:cp_startofpacket wire [81:0] burst_adapter_001_source0_data; // burst_adapter_001:source0_data -> sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:cp_data wire burst_adapter_001_source0_ready; // sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:cp_ready -> burst_adapter_001:source0_ready wire [12:0] burst_adapter_001_source0_channel; // burst_adapter_001:source0_channel -> sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:cp_channel wire burst_adapter_002_source0_endofpacket; // burst_adapter_002:source0_endofpacket -> character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent:cp_endofpacket wire burst_adapter_002_source0_valid; // burst_adapter_002:source0_valid -> character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent:cp_valid wire burst_adapter_002_source0_startofpacket; // burst_adapter_002:source0_startofpacket -> character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent:cp_startofpacket wire [72:0] burst_adapter_002_source0_data; // burst_adapter_002:source0_data -> character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent:cp_data wire burst_adapter_002_source0_ready; // character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent:cp_ready -> burst_adapter_002:source0_ready wire [12:0] burst_adapter_002_source0_channel; // burst_adapter_002:source0_channel -> character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent:cp_channel wire rst_controller_reset_out_reset; // rst_controller:reset_out -> [addr_router:reset, addr_router_001:reset, burst_adapter:reset, burst_adapter_001:reset, burst_adapter_002:reset, character_lcd_0:reset, character_lcd_0_avalon_lcd_slave_translator:reset, character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent:reset, character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, cmd_xbar_demux:reset, cmd_xbar_demux_001:reset, cmd_xbar_mux:reset, cmd_xbar_mux_001:reset, cmd_xbar_mux_002:reset, cmd_xbar_mux_003:reset, crosser:in_reset, crosser_001:out_reset, green_leds:reset_n, green_leds_s1_translator:reset, green_leds_s1_translator_avalon_universal_slave_0_agent:reset, green_leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, id_router:reset, id_router_001:reset, id_router_002:reset, id_router_003:reset, id_router_005:reset, id_router_006:reset, id_router_007:reset, id_router_008:reset, id_router_009:reset, id_router_010:reset, id_router_011:reset, id_router_012:reset, irq_mapper:reset, jtag_uart_0:rst_n, jtag_uart_0_avalon_jtag_slave_translator:reset, jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:reset, jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, limiter:reset, limiter_001:reset, nios2_qsys_0:reset_n, nios2_qsys_0_data_master_translator:reset, nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent:reset, nios2_qsys_0_instruction_master_translator:reset, nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent:reset, nios2_qsys_0_jtag_debug_module_translator:reset, nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:reset, nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, onchip_memory2_0:reset, onchip_memory2_0_s1_translator:reset, onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:reset, onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, rsp_xbar_demux:reset, rsp_xbar_demux_001:reset, rsp_xbar_demux_002:reset, rsp_xbar_demux_003:reset, rsp_xbar_demux_005:reset, rsp_xbar_demux_006:reset, rsp_xbar_demux_007:reset, rsp_xbar_demux_008:reset, rsp_xbar_demux_009:reset, rsp_xbar_demux_010:reset, rsp_xbar_demux_011:reset, rsp_xbar_demux_012:reset, rsp_xbar_mux:reset, rsp_xbar_mux_001:reset, sdram_0:reset_n, sdram_0_s1_translator:reset, sdram_0_s1_translator_avalon_universal_slave_0_agent:reset, sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, servo_pwm_0:reset_n, servo_pwm_0_s0_translator:reset, servo_pwm_0_s0_translator_avalon_universal_slave_0_agent:reset, servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, sram_0:reset, sram_0_avalon_sram_slave_translator:reset, sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:reset, sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, switch:reset_n, switch_0:reset_n, switch_0_s1_translator:reset, switch_0_s1_translator_avalon_universal_slave_0_agent:reset, switch_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, switch_s1_translator:reset, switch_s1_translator_avalon_universal_slave_0_agent:reset, switch_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, sysid_qsys_0:reset_n, sysid_qsys_0_control_slave_translator:reset, sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:reset, sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, timer_0:reset_n, timer_0_s1_translator:reset, timer_0_s1_translator_avalon_universal_slave_0_agent:reset, timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, width_adapter:reset, width_adapter_001:reset, width_adapter_002:reset, width_adapter_003:reset, width_adapter_004:reset, width_adapter_005:reset] wire nios2_qsys_0_jtag_debug_module_reset_reset; // nios2_qsys_0:jtag_debug_module_resetrequest -> [rst_controller:reset_in1, rst_controller_001:reset_in1] wire rst_controller_001_reset_out_reset; // rst_controller_001:reset_out -> [altpll_0:reset, altpll_0_pll_slave_translator:reset, altpll_0_pll_slave_translator_avalon_universal_slave_0_agent:reset, altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo:reset, altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, crosser:out_reset, crosser_001:in_reset, id_router_004:reset, rsp_xbar_demux_004:reset] wire cmd_xbar_demux_src0_endofpacket; // cmd_xbar_demux:src0_endofpacket -> cmd_xbar_mux:sink0_endofpacket wire cmd_xbar_demux_src0_valid; // cmd_xbar_demux:src0_valid -> cmd_xbar_mux:sink0_valid wire cmd_xbar_demux_src0_startofpacket; // cmd_xbar_demux:src0_startofpacket -> cmd_xbar_mux:sink0_startofpacket wire [99:0] cmd_xbar_demux_src0_data; // cmd_xbar_demux:src0_data -> cmd_xbar_mux:sink0_data wire [12:0] cmd_xbar_demux_src0_channel; // cmd_xbar_demux:src0_channel -> cmd_xbar_mux:sink0_channel wire cmd_xbar_demux_src0_ready; // cmd_xbar_mux:sink0_ready -> cmd_xbar_demux:src0_ready wire cmd_xbar_demux_src1_endofpacket; // cmd_xbar_demux:src1_endofpacket -> cmd_xbar_mux_001:sink0_endofpacket wire cmd_xbar_demux_src1_valid; // cmd_xbar_demux:src1_valid -> cmd_xbar_mux_001:sink0_valid wire cmd_xbar_demux_src1_startofpacket; // cmd_xbar_demux:src1_startofpacket -> cmd_xbar_mux_001:sink0_startofpacket wire [99:0] cmd_xbar_demux_src1_data; // cmd_xbar_demux:src1_data -> cmd_xbar_mux_001:sink0_data wire [12:0] cmd_xbar_demux_src1_channel; // cmd_xbar_demux:src1_channel -> cmd_xbar_mux_001:sink0_channel wire cmd_xbar_demux_src1_ready; // cmd_xbar_mux_001:sink0_ready -> cmd_xbar_demux:src1_ready wire cmd_xbar_demux_src2_endofpacket; // cmd_xbar_demux:src2_endofpacket -> cmd_xbar_mux_002:sink0_endofpacket wire cmd_xbar_demux_src2_valid; // cmd_xbar_demux:src2_valid -> cmd_xbar_mux_002:sink0_valid wire cmd_xbar_demux_src2_startofpacket; // cmd_xbar_demux:src2_startofpacket -> cmd_xbar_mux_002:sink0_startofpacket wire [99:0] cmd_xbar_demux_src2_data; // cmd_xbar_demux:src2_data -> cmd_xbar_mux_002:sink0_data wire [12:0] cmd_xbar_demux_src2_channel; // cmd_xbar_demux:src2_channel -> cmd_xbar_mux_002:sink0_channel wire cmd_xbar_demux_src2_ready; // cmd_xbar_mux_002:sink0_ready -> cmd_xbar_demux:src2_ready wire cmd_xbar_demux_src3_endofpacket; // cmd_xbar_demux:src3_endofpacket -> cmd_xbar_mux_003:sink0_endofpacket wire cmd_xbar_demux_src3_valid; // cmd_xbar_demux:src3_valid -> cmd_xbar_mux_003:sink0_valid wire cmd_xbar_demux_src3_startofpacket; // cmd_xbar_demux:src3_startofpacket -> cmd_xbar_mux_003:sink0_startofpacket wire [99:0] cmd_xbar_demux_src3_data; // cmd_xbar_demux:src3_data -> cmd_xbar_mux_003:sink0_data wire [12:0] cmd_xbar_demux_src3_channel; // cmd_xbar_demux:src3_channel -> cmd_xbar_mux_003:sink0_channel wire cmd_xbar_demux_src3_ready; // cmd_xbar_mux_003:sink0_ready -> cmd_xbar_demux:src3_ready wire cmd_xbar_demux_001_src0_endofpacket; // cmd_xbar_demux_001:src0_endofpacket -> cmd_xbar_mux:sink1_endofpacket wire cmd_xbar_demux_001_src0_valid; // cmd_xbar_demux_001:src0_valid -> cmd_xbar_mux:sink1_valid wire cmd_xbar_demux_001_src0_startofpacket; // cmd_xbar_demux_001:src0_startofpacket -> cmd_xbar_mux:sink1_startofpacket wire [99:0] cmd_xbar_demux_001_src0_data; // cmd_xbar_demux_001:src0_data -> cmd_xbar_mux:sink1_data wire [12:0] cmd_xbar_demux_001_src0_channel; // cmd_xbar_demux_001:src0_channel -> cmd_xbar_mux:sink1_channel wire cmd_xbar_demux_001_src0_ready; // cmd_xbar_mux:sink1_ready -> cmd_xbar_demux_001:src0_ready wire cmd_xbar_demux_001_src1_endofpacket; // cmd_xbar_demux_001:src1_endofpacket -> cmd_xbar_mux_001:sink1_endofpacket wire cmd_xbar_demux_001_src1_valid; // cmd_xbar_demux_001:src1_valid -> cmd_xbar_mux_001:sink1_valid wire cmd_xbar_demux_001_src1_startofpacket; // cmd_xbar_demux_001:src1_startofpacket -> cmd_xbar_mux_001:sink1_startofpacket wire [99:0] cmd_xbar_demux_001_src1_data; // cmd_xbar_demux_001:src1_data -> cmd_xbar_mux_001:sink1_data wire [12:0] cmd_xbar_demux_001_src1_channel; // cmd_xbar_demux_001:src1_channel -> cmd_xbar_mux_001:sink1_channel wire cmd_xbar_demux_001_src1_ready; // cmd_xbar_mux_001:sink1_ready -> cmd_xbar_demux_001:src1_ready wire cmd_xbar_demux_001_src2_endofpacket; // cmd_xbar_demux_001:src2_endofpacket -> cmd_xbar_mux_002:sink1_endofpacket wire cmd_xbar_demux_001_src2_valid; // cmd_xbar_demux_001:src2_valid -> cmd_xbar_mux_002:sink1_valid wire cmd_xbar_demux_001_src2_startofpacket; // cmd_xbar_demux_001:src2_startofpacket -> cmd_xbar_mux_002:sink1_startofpacket wire [99:0] cmd_xbar_demux_001_src2_data; // cmd_xbar_demux_001:src2_data -> cmd_xbar_mux_002:sink1_data wire [12:0] cmd_xbar_demux_001_src2_channel; // cmd_xbar_demux_001:src2_channel -> cmd_xbar_mux_002:sink1_channel wire cmd_xbar_demux_001_src2_ready; // cmd_xbar_mux_002:sink1_ready -> cmd_xbar_demux_001:src2_ready wire cmd_xbar_demux_001_src3_endofpacket; // cmd_xbar_demux_001:src3_endofpacket -> cmd_xbar_mux_003:sink1_endofpacket wire cmd_xbar_demux_001_src3_valid; // cmd_xbar_demux_001:src3_valid -> cmd_xbar_mux_003:sink1_valid wire cmd_xbar_demux_001_src3_startofpacket; // cmd_xbar_demux_001:src3_startofpacket -> cmd_xbar_mux_003:sink1_startofpacket wire [99:0] cmd_xbar_demux_001_src3_data; // cmd_xbar_demux_001:src3_data -> cmd_xbar_mux_003:sink1_data wire [12:0] cmd_xbar_demux_001_src3_channel; // cmd_xbar_demux_001:src3_channel -> cmd_xbar_mux_003:sink1_channel wire cmd_xbar_demux_001_src3_ready; // cmd_xbar_mux_003:sink1_ready -> cmd_xbar_demux_001:src3_ready wire cmd_xbar_demux_001_src5_endofpacket; // cmd_xbar_demux_001:src5_endofpacket -> sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:cp_endofpacket wire cmd_xbar_demux_001_src5_valid; // cmd_xbar_demux_001:src5_valid -> sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:cp_valid wire cmd_xbar_demux_001_src5_startofpacket; // cmd_xbar_demux_001:src5_startofpacket -> sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:cp_startofpacket wire [99:0] cmd_xbar_demux_001_src5_data; // cmd_xbar_demux_001:src5_data -> sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:cp_data wire [12:0] cmd_xbar_demux_001_src5_channel; // cmd_xbar_demux_001:src5_channel -> sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:cp_channel wire cmd_xbar_demux_001_src6_endofpacket; // cmd_xbar_demux_001:src6_endofpacket -> timer_0_s1_translator_avalon_universal_slave_0_agent:cp_endofpacket wire cmd_xbar_demux_001_src6_valid; // cmd_xbar_demux_001:src6_valid -> timer_0_s1_translator_avalon_universal_slave_0_agent:cp_valid wire cmd_xbar_demux_001_src6_startofpacket; // cmd_xbar_demux_001:src6_startofpacket -> timer_0_s1_translator_avalon_universal_slave_0_agent:cp_startofpacket wire [99:0] cmd_xbar_demux_001_src6_data; // cmd_xbar_demux_001:src6_data -> timer_0_s1_translator_avalon_universal_slave_0_agent:cp_data wire [12:0] cmd_xbar_demux_001_src6_channel; // cmd_xbar_demux_001:src6_channel -> timer_0_s1_translator_avalon_universal_slave_0_agent:cp_channel wire cmd_xbar_demux_001_src7_endofpacket; // cmd_xbar_demux_001:src7_endofpacket -> jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:cp_endofpacket wire cmd_xbar_demux_001_src7_valid; // cmd_xbar_demux_001:src7_valid -> jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:cp_valid wire cmd_xbar_demux_001_src7_startofpacket; // cmd_xbar_demux_001:src7_startofpacket -> jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:cp_startofpacket wire [99:0] cmd_xbar_demux_001_src7_data; // cmd_xbar_demux_001:src7_data -> jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:cp_data wire [12:0] cmd_xbar_demux_001_src7_channel; // cmd_xbar_demux_001:src7_channel -> jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:cp_channel wire cmd_xbar_demux_001_src8_endofpacket; // cmd_xbar_demux_001:src8_endofpacket -> width_adapter_004:in_endofpacket wire cmd_xbar_demux_001_src8_valid; // cmd_xbar_demux_001:src8_valid -> width_adapter_004:in_valid wire cmd_xbar_demux_001_src8_startofpacket; // cmd_xbar_demux_001:src8_startofpacket -> width_adapter_004:in_startofpacket wire [99:0] cmd_xbar_demux_001_src8_data; // cmd_xbar_demux_001:src8_data -> width_adapter_004:in_data wire [12:0] cmd_xbar_demux_001_src8_channel; // cmd_xbar_demux_001:src8_channel -> width_adapter_004:in_channel wire cmd_xbar_demux_001_src9_endofpacket; // cmd_xbar_demux_001:src9_endofpacket -> green_leds_s1_translator_avalon_universal_slave_0_agent:cp_endofpacket wire cmd_xbar_demux_001_src9_valid; // cmd_xbar_demux_001:src9_valid -> green_leds_s1_translator_avalon_universal_slave_0_agent:cp_valid wire cmd_xbar_demux_001_src9_startofpacket; // cmd_xbar_demux_001:src9_startofpacket -> green_leds_s1_translator_avalon_universal_slave_0_agent:cp_startofpacket wire [99:0] cmd_xbar_demux_001_src9_data; // cmd_xbar_demux_001:src9_data -> green_leds_s1_translator_avalon_universal_slave_0_agent:cp_data wire [12:0] cmd_xbar_demux_001_src9_channel; // cmd_xbar_demux_001:src9_channel -> green_leds_s1_translator_avalon_universal_slave_0_agent:cp_channel wire cmd_xbar_demux_001_src10_endofpacket; // cmd_xbar_demux_001:src10_endofpacket -> switch_s1_translator_avalon_universal_slave_0_agent:cp_endofpacket wire cmd_xbar_demux_001_src10_valid; // cmd_xbar_demux_001:src10_valid -> switch_s1_translator_avalon_universal_slave_0_agent:cp_valid wire cmd_xbar_demux_001_src10_startofpacket; // cmd_xbar_demux_001:src10_startofpacket -> switch_s1_translator_avalon_universal_slave_0_agent:cp_startofpacket wire [99:0] cmd_xbar_demux_001_src10_data; // cmd_xbar_demux_001:src10_data -> switch_s1_translator_avalon_universal_slave_0_agent:cp_data wire [12:0] cmd_xbar_demux_001_src10_channel; // cmd_xbar_demux_001:src10_channel -> switch_s1_translator_avalon_universal_slave_0_agent:cp_channel wire cmd_xbar_demux_001_src11_endofpacket; // cmd_xbar_demux_001:src11_endofpacket -> switch_0_s1_translator_avalon_universal_slave_0_agent:cp_endofpacket wire cmd_xbar_demux_001_src11_valid; // cmd_xbar_demux_001:src11_valid -> switch_0_s1_translator_avalon_universal_slave_0_agent:cp_valid wire cmd_xbar_demux_001_src11_startofpacket; // cmd_xbar_demux_001:src11_startofpacket -> switch_0_s1_translator_avalon_universal_slave_0_agent:cp_startofpacket wire [99:0] cmd_xbar_demux_001_src11_data; // cmd_xbar_demux_001:src11_data -> switch_0_s1_translator_avalon_universal_slave_0_agent:cp_data wire [12:0] cmd_xbar_demux_001_src11_channel; // cmd_xbar_demux_001:src11_channel -> switch_0_s1_translator_avalon_universal_slave_0_agent:cp_channel wire cmd_xbar_demux_001_src12_endofpacket; // cmd_xbar_demux_001:src12_endofpacket -> servo_pwm_0_s0_translator_avalon_universal_slave_0_agent:cp_endofpacket wire cmd_xbar_demux_001_src12_valid; // cmd_xbar_demux_001:src12_valid -> servo_pwm_0_s0_translator_avalon_universal_slave_0_agent:cp_valid wire cmd_xbar_demux_001_src12_startofpacket; // cmd_xbar_demux_001:src12_startofpacket -> servo_pwm_0_s0_translator_avalon_universal_slave_0_agent:cp_startofpacket wire [99:0] cmd_xbar_demux_001_src12_data; // cmd_xbar_demux_001:src12_data -> servo_pwm_0_s0_translator_avalon_universal_slave_0_agent:cp_data wire [12:0] cmd_xbar_demux_001_src12_channel; // cmd_xbar_demux_001:src12_channel -> servo_pwm_0_s0_translator_avalon_universal_slave_0_agent:cp_channel wire rsp_xbar_demux_src0_endofpacket; // rsp_xbar_demux:src0_endofpacket -> rsp_xbar_mux:sink0_endofpacket wire rsp_xbar_demux_src0_valid; // rsp_xbar_demux:src0_valid -> rsp_xbar_mux:sink0_valid wire rsp_xbar_demux_src0_startofpacket; // rsp_xbar_demux:src0_startofpacket -> rsp_xbar_mux:sink0_startofpacket wire [99:0] rsp_xbar_demux_src0_data; // rsp_xbar_demux:src0_data -> rsp_xbar_mux:sink0_data wire [12:0] rsp_xbar_demux_src0_channel; // rsp_xbar_demux:src0_channel -> rsp_xbar_mux:sink0_channel wire rsp_xbar_demux_src0_ready; // rsp_xbar_mux:sink0_ready -> rsp_xbar_demux:src0_ready wire rsp_xbar_demux_src1_endofpacket; // rsp_xbar_demux:src1_endofpacket -> rsp_xbar_mux_001:sink0_endofpacket wire rsp_xbar_demux_src1_valid; // rsp_xbar_demux:src1_valid -> rsp_xbar_mux_001:sink0_valid wire rsp_xbar_demux_src1_startofpacket; // rsp_xbar_demux:src1_startofpacket -> rsp_xbar_mux_001:sink0_startofpacket wire [99:0] rsp_xbar_demux_src1_data; // rsp_xbar_demux:src1_data -> rsp_xbar_mux_001:sink0_data wire [12:0] rsp_xbar_demux_src1_channel; // rsp_xbar_demux:src1_channel -> rsp_xbar_mux_001:sink0_channel wire rsp_xbar_demux_src1_ready; // rsp_xbar_mux_001:sink0_ready -> rsp_xbar_demux:src1_ready wire rsp_xbar_demux_001_src0_endofpacket; // rsp_xbar_demux_001:src0_endofpacket -> rsp_xbar_mux:sink1_endofpacket wire rsp_xbar_demux_001_src0_valid; // rsp_xbar_demux_001:src0_valid -> rsp_xbar_mux:sink1_valid wire rsp_xbar_demux_001_src0_startofpacket; // rsp_xbar_demux_001:src0_startofpacket -> rsp_xbar_mux:sink1_startofpacket wire [99:0] rsp_xbar_demux_001_src0_data; // rsp_xbar_demux_001:src0_data -> rsp_xbar_mux:sink1_data wire [12:0] rsp_xbar_demux_001_src0_channel; // rsp_xbar_demux_001:src0_channel -> rsp_xbar_mux:sink1_channel wire rsp_xbar_demux_001_src0_ready; // rsp_xbar_mux:sink1_ready -> rsp_xbar_demux_001:src0_ready wire rsp_xbar_demux_001_src1_endofpacket; // rsp_xbar_demux_001:src1_endofpacket -> rsp_xbar_mux_001:sink1_endofpacket wire rsp_xbar_demux_001_src1_valid; // rsp_xbar_demux_001:src1_valid -> rsp_xbar_mux_001:sink1_valid wire rsp_xbar_demux_001_src1_startofpacket; // rsp_xbar_demux_001:src1_startofpacket -> rsp_xbar_mux_001:sink1_startofpacket wire [99:0] rsp_xbar_demux_001_src1_data; // rsp_xbar_demux_001:src1_data -> rsp_xbar_mux_001:sink1_data wire [12:0] rsp_xbar_demux_001_src1_channel; // rsp_xbar_demux_001:src1_channel -> rsp_xbar_mux_001:sink1_channel wire rsp_xbar_demux_001_src1_ready; // rsp_xbar_mux_001:sink1_ready -> rsp_xbar_demux_001:src1_ready wire rsp_xbar_demux_002_src0_endofpacket; // rsp_xbar_demux_002:src0_endofpacket -> rsp_xbar_mux:sink2_endofpacket wire rsp_xbar_demux_002_src0_valid; // rsp_xbar_demux_002:src0_valid -> rsp_xbar_mux:sink2_valid wire rsp_xbar_demux_002_src0_startofpacket; // rsp_xbar_demux_002:src0_startofpacket -> rsp_xbar_mux:sink2_startofpacket wire [99:0] rsp_xbar_demux_002_src0_data; // rsp_xbar_demux_002:src0_data -> rsp_xbar_mux:sink2_data wire [12:0] rsp_xbar_demux_002_src0_channel; // rsp_xbar_demux_002:src0_channel -> rsp_xbar_mux:sink2_channel wire rsp_xbar_demux_002_src0_ready; // rsp_xbar_mux:sink2_ready -> rsp_xbar_demux_002:src0_ready wire rsp_xbar_demux_002_src1_endofpacket; // rsp_xbar_demux_002:src1_endofpacket -> rsp_xbar_mux_001:sink2_endofpacket wire rsp_xbar_demux_002_src1_valid; // rsp_xbar_demux_002:src1_valid -> rsp_xbar_mux_001:sink2_valid wire rsp_xbar_demux_002_src1_startofpacket; // rsp_xbar_demux_002:src1_startofpacket -> rsp_xbar_mux_001:sink2_startofpacket wire [99:0] rsp_xbar_demux_002_src1_data; // rsp_xbar_demux_002:src1_data -> rsp_xbar_mux_001:sink2_data wire [12:0] rsp_xbar_demux_002_src1_channel; // rsp_xbar_demux_002:src1_channel -> rsp_xbar_mux_001:sink2_channel wire rsp_xbar_demux_002_src1_ready; // rsp_xbar_mux_001:sink2_ready -> rsp_xbar_demux_002:src1_ready wire rsp_xbar_demux_003_src0_endofpacket; // rsp_xbar_demux_003:src0_endofpacket -> rsp_xbar_mux:sink3_endofpacket wire rsp_xbar_demux_003_src0_valid; // rsp_xbar_demux_003:src0_valid -> rsp_xbar_mux:sink3_valid wire rsp_xbar_demux_003_src0_startofpacket; // rsp_xbar_demux_003:src0_startofpacket -> rsp_xbar_mux:sink3_startofpacket wire [99:0] rsp_xbar_demux_003_src0_data; // rsp_xbar_demux_003:src0_data -> rsp_xbar_mux:sink3_data wire [12:0] rsp_xbar_demux_003_src0_channel; // rsp_xbar_demux_003:src0_channel -> rsp_xbar_mux:sink3_channel wire rsp_xbar_demux_003_src0_ready; // rsp_xbar_mux:sink3_ready -> rsp_xbar_demux_003:src0_ready wire rsp_xbar_demux_003_src1_endofpacket; // rsp_xbar_demux_003:src1_endofpacket -> rsp_xbar_mux_001:sink3_endofpacket wire rsp_xbar_demux_003_src1_valid; // rsp_xbar_demux_003:src1_valid -> rsp_xbar_mux_001:sink3_valid wire rsp_xbar_demux_003_src1_startofpacket; // rsp_xbar_demux_003:src1_startofpacket -> rsp_xbar_mux_001:sink3_startofpacket wire [99:0] rsp_xbar_demux_003_src1_data; // rsp_xbar_demux_003:src1_data -> rsp_xbar_mux_001:sink3_data wire [12:0] rsp_xbar_demux_003_src1_channel; // rsp_xbar_demux_003:src1_channel -> rsp_xbar_mux_001:sink3_channel wire rsp_xbar_demux_003_src1_ready; // rsp_xbar_mux_001:sink3_ready -> rsp_xbar_demux_003:src1_ready wire rsp_xbar_demux_005_src0_endofpacket; // rsp_xbar_demux_005:src0_endofpacket -> rsp_xbar_mux_001:sink5_endofpacket wire rsp_xbar_demux_005_src0_valid; // rsp_xbar_demux_005:src0_valid -> rsp_xbar_mux_001:sink5_valid wire rsp_xbar_demux_005_src0_startofpacket; // rsp_xbar_demux_005:src0_startofpacket -> rsp_xbar_mux_001:sink5_startofpacket wire [99:0] rsp_xbar_demux_005_src0_data; // rsp_xbar_demux_005:src0_data -> rsp_xbar_mux_001:sink5_data wire [12:0] rsp_xbar_demux_005_src0_channel; // rsp_xbar_demux_005:src0_channel -> rsp_xbar_mux_001:sink5_channel wire rsp_xbar_demux_005_src0_ready; // rsp_xbar_mux_001:sink5_ready -> rsp_xbar_demux_005:src0_ready wire rsp_xbar_demux_006_src0_endofpacket; // rsp_xbar_demux_006:src0_endofpacket -> rsp_xbar_mux_001:sink6_endofpacket wire rsp_xbar_demux_006_src0_valid; // rsp_xbar_demux_006:src0_valid -> rsp_xbar_mux_001:sink6_valid wire rsp_xbar_demux_006_src0_startofpacket; // rsp_xbar_demux_006:src0_startofpacket -> rsp_xbar_mux_001:sink6_startofpacket wire [99:0] rsp_xbar_demux_006_src0_data; // rsp_xbar_demux_006:src0_data -> rsp_xbar_mux_001:sink6_data wire [12:0] rsp_xbar_demux_006_src0_channel; // rsp_xbar_demux_006:src0_channel -> rsp_xbar_mux_001:sink6_channel wire rsp_xbar_demux_006_src0_ready; // rsp_xbar_mux_001:sink6_ready -> rsp_xbar_demux_006:src0_ready wire rsp_xbar_demux_007_src0_endofpacket; // rsp_xbar_demux_007:src0_endofpacket -> rsp_xbar_mux_001:sink7_endofpacket wire rsp_xbar_demux_007_src0_valid; // rsp_xbar_demux_007:src0_valid -> rsp_xbar_mux_001:sink7_valid wire rsp_xbar_demux_007_src0_startofpacket; // rsp_xbar_demux_007:src0_startofpacket -> rsp_xbar_mux_001:sink7_startofpacket wire [99:0] rsp_xbar_demux_007_src0_data; // rsp_xbar_demux_007:src0_data -> rsp_xbar_mux_001:sink7_data wire [12:0] rsp_xbar_demux_007_src0_channel; // rsp_xbar_demux_007:src0_channel -> rsp_xbar_mux_001:sink7_channel wire rsp_xbar_demux_007_src0_ready; // rsp_xbar_mux_001:sink7_ready -> rsp_xbar_demux_007:src0_ready wire rsp_xbar_demux_008_src0_endofpacket; // rsp_xbar_demux_008:src0_endofpacket -> rsp_xbar_mux_001:sink8_endofpacket wire rsp_xbar_demux_008_src0_valid; // rsp_xbar_demux_008:src0_valid -> rsp_xbar_mux_001:sink8_valid wire rsp_xbar_demux_008_src0_startofpacket; // rsp_xbar_demux_008:src0_startofpacket -> rsp_xbar_mux_001:sink8_startofpacket wire [99:0] rsp_xbar_demux_008_src0_data; // rsp_xbar_demux_008:src0_data -> rsp_xbar_mux_001:sink8_data wire [12:0] rsp_xbar_demux_008_src0_channel; // rsp_xbar_demux_008:src0_channel -> rsp_xbar_mux_001:sink8_channel wire rsp_xbar_demux_008_src0_ready; // rsp_xbar_mux_001:sink8_ready -> rsp_xbar_demux_008:src0_ready wire rsp_xbar_demux_009_src0_endofpacket; // rsp_xbar_demux_009:src0_endofpacket -> rsp_xbar_mux_001:sink9_endofpacket wire rsp_xbar_demux_009_src0_valid; // rsp_xbar_demux_009:src0_valid -> rsp_xbar_mux_001:sink9_valid wire rsp_xbar_demux_009_src0_startofpacket; // rsp_xbar_demux_009:src0_startofpacket -> rsp_xbar_mux_001:sink9_startofpacket wire [99:0] rsp_xbar_demux_009_src0_data; // rsp_xbar_demux_009:src0_data -> rsp_xbar_mux_001:sink9_data wire [12:0] rsp_xbar_demux_009_src0_channel; // rsp_xbar_demux_009:src0_channel -> rsp_xbar_mux_001:sink9_channel wire rsp_xbar_demux_009_src0_ready; // rsp_xbar_mux_001:sink9_ready -> rsp_xbar_demux_009:src0_ready wire rsp_xbar_demux_010_src0_endofpacket; // rsp_xbar_demux_010:src0_endofpacket -> rsp_xbar_mux_001:sink10_endofpacket wire rsp_xbar_demux_010_src0_valid; // rsp_xbar_demux_010:src0_valid -> rsp_xbar_mux_001:sink10_valid wire rsp_xbar_demux_010_src0_startofpacket; // rsp_xbar_demux_010:src0_startofpacket -> rsp_xbar_mux_001:sink10_startofpacket wire [99:0] rsp_xbar_demux_010_src0_data; // rsp_xbar_demux_010:src0_data -> rsp_xbar_mux_001:sink10_data wire [12:0] rsp_xbar_demux_010_src0_channel; // rsp_xbar_demux_010:src0_channel -> rsp_xbar_mux_001:sink10_channel wire rsp_xbar_demux_010_src0_ready; // rsp_xbar_mux_001:sink10_ready -> rsp_xbar_demux_010:src0_ready wire rsp_xbar_demux_011_src0_endofpacket; // rsp_xbar_demux_011:src0_endofpacket -> rsp_xbar_mux_001:sink11_endofpacket wire rsp_xbar_demux_011_src0_valid; // rsp_xbar_demux_011:src0_valid -> rsp_xbar_mux_001:sink11_valid wire rsp_xbar_demux_011_src0_startofpacket; // rsp_xbar_demux_011:src0_startofpacket -> rsp_xbar_mux_001:sink11_startofpacket wire [99:0] rsp_xbar_demux_011_src0_data; // rsp_xbar_demux_011:src0_data -> rsp_xbar_mux_001:sink11_data wire [12:0] rsp_xbar_demux_011_src0_channel; // rsp_xbar_demux_011:src0_channel -> rsp_xbar_mux_001:sink11_channel wire rsp_xbar_demux_011_src0_ready; // rsp_xbar_mux_001:sink11_ready -> rsp_xbar_demux_011:src0_ready wire rsp_xbar_demux_012_src0_endofpacket; // rsp_xbar_demux_012:src0_endofpacket -> rsp_xbar_mux_001:sink12_endofpacket wire rsp_xbar_demux_012_src0_valid; // rsp_xbar_demux_012:src0_valid -> rsp_xbar_mux_001:sink12_valid wire rsp_xbar_demux_012_src0_startofpacket; // rsp_xbar_demux_012:src0_startofpacket -> rsp_xbar_mux_001:sink12_startofpacket wire [99:0] rsp_xbar_demux_012_src0_data; // rsp_xbar_demux_012:src0_data -> rsp_xbar_mux_001:sink12_data wire [12:0] rsp_xbar_demux_012_src0_channel; // rsp_xbar_demux_012:src0_channel -> rsp_xbar_mux_001:sink12_channel wire rsp_xbar_demux_012_src0_ready; // rsp_xbar_mux_001:sink12_ready -> rsp_xbar_demux_012:src0_ready wire limiter_cmd_src_endofpacket; // limiter:cmd_src_endofpacket -> cmd_xbar_demux:sink_endofpacket wire limiter_cmd_src_startofpacket; // limiter:cmd_src_startofpacket -> cmd_xbar_demux:sink_startofpacket wire [99:0] limiter_cmd_src_data; // limiter:cmd_src_data -> cmd_xbar_demux:sink_data wire [12:0] limiter_cmd_src_channel; // limiter:cmd_src_channel -> cmd_xbar_demux:sink_channel wire limiter_cmd_src_ready; // cmd_xbar_demux:sink_ready -> limiter:cmd_src_ready wire rsp_xbar_mux_src_endofpacket; // rsp_xbar_mux:src_endofpacket -> limiter:rsp_sink_endofpacket wire rsp_xbar_mux_src_valid; // rsp_xbar_mux:src_valid -> limiter:rsp_sink_valid wire rsp_xbar_mux_src_startofpacket; // rsp_xbar_mux:src_startofpacket -> limiter:rsp_sink_startofpacket wire [99:0] rsp_xbar_mux_src_data; // rsp_xbar_mux:src_data -> limiter:rsp_sink_data wire [12:0] rsp_xbar_mux_src_channel; // rsp_xbar_mux:src_channel -> limiter:rsp_sink_channel wire rsp_xbar_mux_src_ready; // limiter:rsp_sink_ready -> rsp_xbar_mux:src_ready wire limiter_001_cmd_src_endofpacket; // limiter_001:cmd_src_endofpacket -> cmd_xbar_demux_001:sink_endofpacket wire limiter_001_cmd_src_startofpacket; // limiter_001:cmd_src_startofpacket -> cmd_xbar_demux_001:sink_startofpacket wire [99:0] limiter_001_cmd_src_data; // limiter_001:cmd_src_data -> cmd_xbar_demux_001:sink_data wire [12:0] limiter_001_cmd_src_channel; // limiter_001:cmd_src_channel -> cmd_xbar_demux_001:sink_channel wire limiter_001_cmd_src_ready; // cmd_xbar_demux_001:sink_ready -> limiter_001:cmd_src_ready wire rsp_xbar_mux_001_src_endofpacket; // rsp_xbar_mux_001:src_endofpacket -> limiter_001:rsp_sink_endofpacket wire rsp_xbar_mux_001_src_valid; // rsp_xbar_mux_001:src_valid -> limiter_001:rsp_sink_valid wire rsp_xbar_mux_001_src_startofpacket; // rsp_xbar_mux_001:src_startofpacket -> limiter_001:rsp_sink_startofpacket wire [99:0] rsp_xbar_mux_001_src_data; // rsp_xbar_mux_001:src_data -> limiter_001:rsp_sink_data wire [12:0] rsp_xbar_mux_001_src_channel; // rsp_xbar_mux_001:src_channel -> limiter_001:rsp_sink_channel wire rsp_xbar_mux_001_src_ready; // limiter_001:rsp_sink_ready -> rsp_xbar_mux_001:src_ready wire cmd_xbar_mux_src_endofpacket; // cmd_xbar_mux:src_endofpacket -> nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:cp_endofpacket wire cmd_xbar_mux_src_valid; // cmd_xbar_mux:src_valid -> nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:cp_valid wire cmd_xbar_mux_src_startofpacket; // cmd_xbar_mux:src_startofpacket -> nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:cp_startofpacket wire [99:0] cmd_xbar_mux_src_data; // cmd_xbar_mux:src_data -> nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:cp_data wire [12:0] cmd_xbar_mux_src_channel; // cmd_xbar_mux:src_channel -> nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:cp_channel wire cmd_xbar_mux_src_ready; // nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_mux:src_ready wire id_router_src_endofpacket; // id_router:src_endofpacket -> rsp_xbar_demux:sink_endofpacket wire id_router_src_valid; // id_router:src_valid -> rsp_xbar_demux:sink_valid wire id_router_src_startofpacket; // id_router:src_startofpacket -> rsp_xbar_demux:sink_startofpacket wire [99:0] id_router_src_data; // id_router:src_data -> rsp_xbar_demux:sink_data wire [12:0] id_router_src_channel; // id_router:src_channel -> rsp_xbar_demux:sink_channel wire id_router_src_ready; // rsp_xbar_demux:sink_ready -> id_router:src_ready wire cmd_xbar_mux_001_src_endofpacket; // cmd_xbar_mux_001:src_endofpacket -> onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:cp_endofpacket wire cmd_xbar_mux_001_src_valid; // cmd_xbar_mux_001:src_valid -> onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:cp_valid wire cmd_xbar_mux_001_src_startofpacket; // cmd_xbar_mux_001:src_startofpacket -> onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:cp_startofpacket wire [99:0] cmd_xbar_mux_001_src_data; // cmd_xbar_mux_001:src_data -> onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:cp_data wire [12:0] cmd_xbar_mux_001_src_channel; // cmd_xbar_mux_001:src_channel -> onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:cp_channel wire cmd_xbar_mux_001_src_ready; // onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_mux_001:src_ready wire id_router_001_src_endofpacket; // id_router_001:src_endofpacket -> rsp_xbar_demux_001:sink_endofpacket wire id_router_001_src_valid; // id_router_001:src_valid -> rsp_xbar_demux_001:sink_valid wire id_router_001_src_startofpacket; // id_router_001:src_startofpacket -> rsp_xbar_demux_001:sink_startofpacket wire [99:0] id_router_001_src_data; // id_router_001:src_data -> rsp_xbar_demux_001:sink_data wire [12:0] id_router_001_src_channel; // id_router_001:src_channel -> rsp_xbar_demux_001:sink_channel wire id_router_001_src_ready; // rsp_xbar_demux_001:sink_ready -> id_router_001:src_ready wire crosser_out_ready; // altpll_0_pll_slave_translator_avalon_universal_slave_0_agent:cp_ready -> crosser:out_ready wire id_router_004_src_endofpacket; // id_router_004:src_endofpacket -> rsp_xbar_demux_004:sink_endofpacket wire id_router_004_src_valid; // id_router_004:src_valid -> rsp_xbar_demux_004:sink_valid wire id_router_004_src_startofpacket; // id_router_004:src_startofpacket -> rsp_xbar_demux_004:sink_startofpacket wire [99:0] id_router_004_src_data; // id_router_004:src_data -> rsp_xbar_demux_004:sink_data wire [12:0] id_router_004_src_channel; // id_router_004:src_channel -> rsp_xbar_demux_004:sink_channel wire id_router_004_src_ready; // rsp_xbar_demux_004:sink_ready -> id_router_004:src_ready wire cmd_xbar_demux_001_src5_ready; // sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_001:src5_ready wire id_router_005_src_endofpacket; // id_router_005:src_endofpacket -> rsp_xbar_demux_005:sink_endofpacket wire id_router_005_src_valid; // id_router_005:src_valid -> rsp_xbar_demux_005:sink_valid wire id_router_005_src_startofpacket; // id_router_005:src_startofpacket -> rsp_xbar_demux_005:sink_startofpacket wire [99:0] id_router_005_src_data; // id_router_005:src_data -> rsp_xbar_demux_005:sink_data wire [12:0] id_router_005_src_channel; // id_router_005:src_channel -> rsp_xbar_demux_005:sink_channel wire id_router_005_src_ready; // rsp_xbar_demux_005:sink_ready -> id_router_005:src_ready wire cmd_xbar_demux_001_src6_ready; // timer_0_s1_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_001:src6_ready wire id_router_006_src_endofpacket; // id_router_006:src_endofpacket -> rsp_xbar_demux_006:sink_endofpacket wire id_router_006_src_valid; // id_router_006:src_valid -> rsp_xbar_demux_006:sink_valid wire id_router_006_src_startofpacket; // id_router_006:src_startofpacket -> rsp_xbar_demux_006:sink_startofpacket wire [99:0] id_router_006_src_data; // id_router_006:src_data -> rsp_xbar_demux_006:sink_data wire [12:0] id_router_006_src_channel; // id_router_006:src_channel -> rsp_xbar_demux_006:sink_channel wire id_router_006_src_ready; // rsp_xbar_demux_006:sink_ready -> id_router_006:src_ready wire cmd_xbar_demux_001_src7_ready; // jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_001:src7_ready wire id_router_007_src_endofpacket; // id_router_007:src_endofpacket -> rsp_xbar_demux_007:sink_endofpacket wire id_router_007_src_valid; // id_router_007:src_valid -> rsp_xbar_demux_007:sink_valid wire id_router_007_src_startofpacket; // id_router_007:src_startofpacket -> rsp_xbar_demux_007:sink_startofpacket wire [99:0] id_router_007_src_data; // id_router_007:src_data -> rsp_xbar_demux_007:sink_data wire [12:0] id_router_007_src_channel; // id_router_007:src_channel -> rsp_xbar_demux_007:sink_channel wire id_router_007_src_ready; // rsp_xbar_demux_007:sink_ready -> id_router_007:src_ready wire cmd_xbar_demux_001_src9_ready; // green_leds_s1_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_001:src9_ready wire id_router_009_src_endofpacket; // id_router_009:src_endofpacket -> rsp_xbar_demux_009:sink_endofpacket wire id_router_009_src_valid; // id_router_009:src_valid -> rsp_xbar_demux_009:sink_valid wire id_router_009_src_startofpacket; // id_router_009:src_startofpacket -> rsp_xbar_demux_009:sink_startofpacket wire [99:0] id_router_009_src_data; // id_router_009:src_data -> rsp_xbar_demux_009:sink_data wire [12:0] id_router_009_src_channel; // id_router_009:src_channel -> rsp_xbar_demux_009:sink_channel wire id_router_009_src_ready; // rsp_xbar_demux_009:sink_ready -> id_router_009:src_ready wire cmd_xbar_demux_001_src10_ready; // switch_s1_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_001:src10_ready wire id_router_010_src_endofpacket; // id_router_010:src_endofpacket -> rsp_xbar_demux_010:sink_endofpacket wire id_router_010_src_valid; // id_router_010:src_valid -> rsp_xbar_demux_010:sink_valid wire id_router_010_src_startofpacket; // id_router_010:src_startofpacket -> rsp_xbar_demux_010:sink_startofpacket wire [99:0] id_router_010_src_data; // id_router_010:src_data -> rsp_xbar_demux_010:sink_data wire [12:0] id_router_010_src_channel; // id_router_010:src_channel -> rsp_xbar_demux_010:sink_channel wire id_router_010_src_ready; // rsp_xbar_demux_010:sink_ready -> id_router_010:src_ready wire cmd_xbar_demux_001_src11_ready; // switch_0_s1_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_001:src11_ready wire id_router_011_src_endofpacket; // id_router_011:src_endofpacket -> rsp_xbar_demux_011:sink_endofpacket wire id_router_011_src_valid; // id_router_011:src_valid -> rsp_xbar_demux_011:sink_valid wire id_router_011_src_startofpacket; // id_router_011:src_startofpacket -> rsp_xbar_demux_011:sink_startofpacket wire [99:0] id_router_011_src_data; // id_router_011:src_data -> rsp_xbar_demux_011:sink_data wire [12:0] id_router_011_src_channel; // id_router_011:src_channel -> rsp_xbar_demux_011:sink_channel wire id_router_011_src_ready; // rsp_xbar_demux_011:sink_ready -> id_router_011:src_ready wire cmd_xbar_demux_001_src12_ready; // servo_pwm_0_s0_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_001:src12_ready wire id_router_012_src_endofpacket; // id_router_012:src_endofpacket -> rsp_xbar_demux_012:sink_endofpacket wire id_router_012_src_valid; // id_router_012:src_valid -> rsp_xbar_demux_012:sink_valid wire id_router_012_src_startofpacket; // id_router_012:src_startofpacket -> rsp_xbar_demux_012:sink_startofpacket wire [99:0] id_router_012_src_data; // id_router_012:src_data -> rsp_xbar_demux_012:sink_data wire [12:0] id_router_012_src_channel; // id_router_012:src_channel -> rsp_xbar_demux_012:sink_channel wire id_router_012_src_ready; // rsp_xbar_demux_012:sink_ready -> id_router_012:src_ready wire cmd_xbar_mux_002_src_endofpacket; // cmd_xbar_mux_002:src_endofpacket -> width_adapter:in_endofpacket wire cmd_xbar_mux_002_src_valid; // cmd_xbar_mux_002:src_valid -> width_adapter:in_valid wire cmd_xbar_mux_002_src_startofpacket; // cmd_xbar_mux_002:src_startofpacket -> width_adapter:in_startofpacket wire [99:0] cmd_xbar_mux_002_src_data; // cmd_xbar_mux_002:src_data -> width_adapter:in_data wire [12:0] cmd_xbar_mux_002_src_channel; // cmd_xbar_mux_002:src_channel -> width_adapter:in_channel wire cmd_xbar_mux_002_src_ready; // width_adapter:in_ready -> cmd_xbar_mux_002:src_ready wire width_adapter_src_endofpacket; // width_adapter:out_endofpacket -> burst_adapter:sink0_endofpacket wire width_adapter_src_valid; // width_adapter:out_valid -> burst_adapter:sink0_valid wire width_adapter_src_startofpacket; // width_adapter:out_startofpacket -> burst_adapter:sink0_startofpacket wire [81:0] width_adapter_src_data; // width_adapter:out_data -> burst_adapter:sink0_data wire width_adapter_src_ready; // burst_adapter:sink0_ready -> width_adapter:out_ready wire [12:0] width_adapter_src_channel; // width_adapter:out_channel -> burst_adapter:sink0_channel wire id_router_002_src_endofpacket; // id_router_002:src_endofpacket -> width_adapter_001:in_endofpacket wire id_router_002_src_valid; // id_router_002:src_valid -> width_adapter_001:in_valid wire id_router_002_src_startofpacket; // id_router_002:src_startofpacket -> width_adapter_001:in_startofpacket wire [81:0] id_router_002_src_data; // id_router_002:src_data -> width_adapter_001:in_data wire [12:0] id_router_002_src_channel; // id_router_002:src_channel -> width_adapter_001:in_channel wire id_router_002_src_ready; // width_adapter_001:in_ready -> id_router_002:src_ready wire width_adapter_001_src_endofpacket; // width_adapter_001:out_endofpacket -> rsp_xbar_demux_002:sink_endofpacket wire width_adapter_001_src_valid; // width_adapter_001:out_valid -> rsp_xbar_demux_002:sink_valid wire width_adapter_001_src_startofpacket; // width_adapter_001:out_startofpacket -> rsp_xbar_demux_002:sink_startofpacket wire [99:0] width_adapter_001_src_data; // width_adapter_001:out_data -> rsp_xbar_demux_002:sink_data wire width_adapter_001_src_ready; // rsp_xbar_demux_002:sink_ready -> width_adapter_001:out_ready wire [12:0] width_adapter_001_src_channel; // width_adapter_001:out_channel -> rsp_xbar_demux_002:sink_channel wire cmd_xbar_mux_003_src_endofpacket; // cmd_xbar_mux_003:src_endofpacket -> width_adapter_002:in_endofpacket wire cmd_xbar_mux_003_src_valid; // cmd_xbar_mux_003:src_valid -> width_adapter_002:in_valid wire cmd_xbar_mux_003_src_startofpacket; // cmd_xbar_mux_003:src_startofpacket -> width_adapter_002:in_startofpacket wire [99:0] cmd_xbar_mux_003_src_data; // cmd_xbar_mux_003:src_data -> width_adapter_002:in_data wire [12:0] cmd_xbar_mux_003_src_channel; // cmd_xbar_mux_003:src_channel -> width_adapter_002:in_channel wire cmd_xbar_mux_003_src_ready; // width_adapter_002:in_ready -> cmd_xbar_mux_003:src_ready wire width_adapter_002_src_endofpacket; // width_adapter_002:out_endofpacket -> burst_adapter_001:sink0_endofpacket wire width_adapter_002_src_valid; // width_adapter_002:out_valid -> burst_adapter_001:sink0_valid wire width_adapter_002_src_startofpacket; // width_adapter_002:out_startofpacket -> burst_adapter_001:sink0_startofpacket wire [81:0] width_adapter_002_src_data; // width_adapter_002:out_data -> burst_adapter_001:sink0_data wire width_adapter_002_src_ready; // burst_adapter_001:sink0_ready -> width_adapter_002:out_ready wire [12:0] width_adapter_002_src_channel; // width_adapter_002:out_channel -> burst_adapter_001:sink0_channel wire id_router_003_src_endofpacket; // id_router_003:src_endofpacket -> width_adapter_003:in_endofpacket wire id_router_003_src_valid; // id_router_003:src_valid -> width_adapter_003:in_valid wire id_router_003_src_startofpacket; // id_router_003:src_startofpacket -> width_adapter_003:in_startofpacket wire [81:0] id_router_003_src_data; // id_router_003:src_data -> width_adapter_003:in_data wire [12:0] id_router_003_src_channel; // id_router_003:src_channel -> width_adapter_003:in_channel wire id_router_003_src_ready; // width_adapter_003:in_ready -> id_router_003:src_ready wire width_adapter_003_src_endofpacket; // width_adapter_003:out_endofpacket -> rsp_xbar_demux_003:sink_endofpacket wire width_adapter_003_src_valid; // width_adapter_003:out_valid -> rsp_xbar_demux_003:sink_valid wire width_adapter_003_src_startofpacket; // width_adapter_003:out_startofpacket -> rsp_xbar_demux_003:sink_startofpacket wire [99:0] width_adapter_003_src_data; // width_adapter_003:out_data -> rsp_xbar_demux_003:sink_data wire width_adapter_003_src_ready; // rsp_xbar_demux_003:sink_ready -> width_adapter_003:out_ready wire [12:0] width_adapter_003_src_channel; // width_adapter_003:out_channel -> rsp_xbar_demux_003:sink_channel wire cmd_xbar_demux_001_src8_ready; // width_adapter_004:in_ready -> cmd_xbar_demux_001:src8_ready wire width_adapter_004_src_endofpacket; // width_adapter_004:out_endofpacket -> burst_adapter_002:sink0_endofpacket wire width_adapter_004_src_valid; // width_adapter_004:out_valid -> burst_adapter_002:sink0_valid wire width_adapter_004_src_startofpacket; // width_adapter_004:out_startofpacket -> burst_adapter_002:sink0_startofpacket wire [72:0] width_adapter_004_src_data; // width_adapter_004:out_data -> burst_adapter_002:sink0_data wire width_adapter_004_src_ready; // burst_adapter_002:sink0_ready -> width_adapter_004:out_ready wire [12:0] width_adapter_004_src_channel; // width_adapter_004:out_channel -> burst_adapter_002:sink0_channel wire id_router_008_src_endofpacket; // id_router_008:src_endofpacket -> width_adapter_005:in_endofpacket wire id_router_008_src_valid; // id_router_008:src_valid -> width_adapter_005:in_valid wire id_router_008_src_startofpacket; // id_router_008:src_startofpacket -> width_adapter_005:in_startofpacket wire [72:0] id_router_008_src_data; // id_router_008:src_data -> width_adapter_005:in_data wire [12:0] id_router_008_src_channel; // id_router_008:src_channel -> width_adapter_005:in_channel wire id_router_008_src_ready; // width_adapter_005:in_ready -> id_router_008:src_ready wire width_adapter_005_src_endofpacket; // width_adapter_005:out_endofpacket -> rsp_xbar_demux_008:sink_endofpacket wire width_adapter_005_src_valid; // width_adapter_005:out_valid -> rsp_xbar_demux_008:sink_valid wire width_adapter_005_src_startofpacket; // width_adapter_005:out_startofpacket -> rsp_xbar_demux_008:sink_startofpacket wire [99:0] width_adapter_005_src_data; // width_adapter_005:out_data -> rsp_xbar_demux_008:sink_data wire width_adapter_005_src_ready; // rsp_xbar_demux_008:sink_ready -> width_adapter_005:out_ready wire [12:0] width_adapter_005_src_channel; // width_adapter_005:out_channel -> rsp_xbar_demux_008:sink_channel wire crosser_out_endofpacket; // crosser:out_endofpacket -> altpll_0_pll_slave_translator_avalon_universal_slave_0_agent:cp_endofpacket wire crosser_out_valid; // crosser:out_valid -> altpll_0_pll_slave_translator_avalon_universal_slave_0_agent:cp_valid wire crosser_out_startofpacket; // crosser:out_startofpacket -> altpll_0_pll_slave_translator_avalon_universal_slave_0_agent:cp_startofpacket wire [99:0] crosser_out_data; // crosser:out_data -> altpll_0_pll_slave_translator_avalon_universal_slave_0_agent:cp_data wire [12:0] crosser_out_channel; // crosser:out_channel -> altpll_0_pll_slave_translator_avalon_universal_slave_0_agent:cp_channel wire cmd_xbar_demux_001_src4_endofpacket; // cmd_xbar_demux_001:src4_endofpacket -> crosser:in_endofpacket wire cmd_xbar_demux_001_src4_valid; // cmd_xbar_demux_001:src4_valid -> crosser:in_valid wire cmd_xbar_demux_001_src4_startofpacket; // cmd_xbar_demux_001:src4_startofpacket -> crosser:in_startofpacket wire [99:0] cmd_xbar_demux_001_src4_data; // cmd_xbar_demux_001:src4_data -> crosser:in_data wire [12:0] cmd_xbar_demux_001_src4_channel; // cmd_xbar_demux_001:src4_channel -> crosser:in_channel wire cmd_xbar_demux_001_src4_ready; // crosser:in_ready -> cmd_xbar_demux_001:src4_ready wire crosser_001_out_endofpacket; // crosser_001:out_endofpacket -> rsp_xbar_mux_001:sink4_endofpacket wire crosser_001_out_valid; // crosser_001:out_valid -> rsp_xbar_mux_001:sink4_valid wire crosser_001_out_startofpacket; // crosser_001:out_startofpacket -> rsp_xbar_mux_001:sink4_startofpacket wire [99:0] crosser_001_out_data; // crosser_001:out_data -> rsp_xbar_mux_001:sink4_data wire [12:0] crosser_001_out_channel; // crosser_001:out_channel -> rsp_xbar_mux_001:sink4_channel wire crosser_001_out_ready; // rsp_xbar_mux_001:sink4_ready -> crosser_001:out_ready wire rsp_xbar_demux_004_src0_endofpacket; // rsp_xbar_demux_004:src0_endofpacket -> crosser_001:in_endofpacket wire rsp_xbar_demux_004_src0_valid; // rsp_xbar_demux_004:src0_valid -> crosser_001:in_valid wire rsp_xbar_demux_004_src0_startofpacket; // rsp_xbar_demux_004:src0_startofpacket -> crosser_001:in_startofpacket wire [99:0] rsp_xbar_demux_004_src0_data; // rsp_xbar_demux_004:src0_data -> crosser_001:in_data wire [12:0] rsp_xbar_demux_004_src0_channel; // rsp_xbar_demux_004:src0_channel -> crosser_001:in_channel wire rsp_xbar_demux_004_src0_ready; // crosser_001:in_ready -> rsp_xbar_demux_004:src0_ready wire [12:0] limiter_cmd_valid_data; // limiter:cmd_src_valid -> cmd_xbar_demux:sink_valid wire [12:0] limiter_001_cmd_valid_data; // limiter_001:cmd_src_valid -> cmd_xbar_demux_001:sink_valid wire irq_mapper_receiver0_irq; // timer_0:irq -> irq_mapper:receiver0_irq wire irq_mapper_receiver1_irq; // jtag_uart_0:av_irq -> irq_mapper:receiver1_irq wire [31:0] nios2_qsys_0_d_irq_irq; // irq_mapper:sender_irq -> nios2_qsys_0:d_irq tracking_camera_system_nios2_qsys_0 nios2_qsys_0 ( .clk (altpll_0_c1_clk), // clk.clk .reset_n (~rst_controller_reset_out_reset), // reset_n.reset_n .d_address (nios2_qsys_0_data_master_address), // data_master.address .d_byteenable (nios2_qsys_0_data_master_byteenable), // .byteenable .d_read (nios2_qsys_0_data_master_read), // .read .d_readdata (nios2_qsys_0_data_master_readdata), // .readdata .d_waitrequest (nios2_qsys_0_data_master_waitrequest), // .waitrequest .d_write (nios2_qsys_0_data_master_write), // .write .d_writedata (nios2_qsys_0_data_master_writedata), // .writedata .d_readdatavalid (nios2_qsys_0_data_master_readdatavalid), // .readdatavalid .jtag_debug_module_debugaccess_to_roms (nios2_qsys_0_data_master_debugaccess), // .debugaccess .i_address (nios2_qsys_0_instruction_master_address), // instruction_master.address .i_read (nios2_qsys_0_instruction_master_read), // .read .i_readdata (nios2_qsys_0_instruction_master_readdata), // .readdata .i_waitrequest (nios2_qsys_0_instruction_master_waitrequest), // .waitrequest .i_readdatavalid (nios2_qsys_0_instruction_master_readdatavalid), // .readdatavalid .d_irq (nios2_qsys_0_d_irq_irq), // d_irq.irq .jtag_debug_module_resetrequest (nios2_qsys_0_jtag_debug_module_reset_reset), // jtag_debug_module_reset.reset .jtag_debug_module_address (nios2_qsys_0_jtag_debug_module_translator_avalon_anti_slave_0_address), // jtag_debug_module.address .jtag_debug_module_begintransfer (nios2_qsys_0_jtag_debug_module_translator_avalon_anti_slave_0_begintransfer), // .begintransfer .jtag_debug_module_byteenable (nios2_qsys_0_jtag_debug_module_translator_avalon_anti_slave_0_byteenable), // .byteenable .jtag_debug_module_debugaccess (nios2_qsys_0_jtag_debug_module_translator_avalon_anti_slave_0_debugaccess), // .debugaccess .jtag_debug_module_readdata (nios2_qsys_0_jtag_debug_module_translator_avalon_anti_slave_0_readdata), // .readdata .jtag_debug_module_select (nios2_qsys_0_jtag_debug_module_translator_avalon_anti_slave_0_chipselect), // .chipselect .jtag_debug_module_write (nios2_qsys_0_jtag_debug_module_translator_avalon_anti_slave_0_write), // .write .jtag_debug_module_writedata (nios2_qsys_0_jtag_debug_module_translator_avalon_anti_slave_0_writedata), // .writedata .no_ci_readra () // custom_instruction_master.readra ); tracking_camera_system_onchip_memory2_0 onchip_memory2_0 ( .clk (altpll_0_c1_clk), // clk1.clk .address (onchip_memory2_0_s1_translator_avalon_anti_slave_0_address), // s1.address .chipselect (onchip_memory2_0_s1_translator_avalon_anti_slave_0_chipselect), // .chipselect .clken (onchip_memory2_0_s1_translator_avalon_anti_slave_0_clken), // .clken .readdata (onchip_memory2_0_s1_translator_avalon_anti_slave_0_readdata), // .readdata .write (onchip_memory2_0_s1_translator_avalon_anti_slave_0_write), // .write .writedata (onchip_memory2_0_s1_translator_avalon_anti_slave_0_writedata), // .writedata .byteenable (onchip_memory2_0_s1_translator_avalon_anti_slave_0_byteenable), // .byteenable .reset (rst_controller_reset_out_reset) // reset1.reset ); tracking_camera_system_sysid_qsys_0 sysid_qsys_0 ( .clock (altpll_0_c1_clk), // clk.clk .reset_n (~rst_controller_reset_out_reset), // reset.reset_n .readdata (sysid_qsys_0_control_slave_translator_avalon_anti_slave_0_readdata), // control_slave.readdata .address (sysid_qsys_0_control_slave_translator_avalon_anti_slave_0_address) // .address ); tracking_camera_system_timer_0 timer_0 ( .clk (altpll_0_c1_clk), // clk.clk .reset_n (~rst_controller_reset_out_reset), // reset.reset_n .address (timer_0_s1_translator_avalon_anti_slave_0_address), // s1.address .writedata (timer_0_s1_translator_avalon_anti_slave_0_writedata), // .writedata .readdata (timer_0_s1_translator_avalon_anti_slave_0_readdata), // .readdata .chipselect (timer_0_s1_translator_avalon_anti_slave_0_chipselect), // .chipselect .write_n (~timer_0_s1_translator_avalon_anti_slave_0_write), // .write_n .irq (irq_mapper_receiver0_irq) // irq.irq ); tracking_camera_system_jtag_uart_0 jtag_uart_0 ( .clk (altpll_0_c1_clk), // clk.clk .rst_n (~rst_controller_reset_out_reset), // reset.reset_n .av_chipselect (jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_chipselect), // avalon_jtag_slave.chipselect .av_address (jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_address), // .address .av_read_n (~jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_read), // .read_n .av_readdata (jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_readdata), // .readdata .av_write_n (~jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_write), // .write_n .av_writedata (jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_writedata), // .writedata .av_waitrequest (jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_waitrequest), // .waitrequest .av_irq (irq_mapper_receiver1_irq) // irq.irq ); tracking_camera_system_character_lcd_0 character_lcd_0 ( .clk (altpll_0_c1_clk), // clock_reset.clk .reset (rst_controller_reset_out_reset), // clock_reset_reset.reset .address (character_lcd_0_avalon_lcd_slave_translator_avalon_anti_slave_0_address), // avalon_lcd_slave.address .chipselect (character_lcd_0_avalon_lcd_slave_translator_avalon_anti_slave_0_chipselect), // .chipselect .read (character_lcd_0_avalon_lcd_slave_translator_avalon_anti_slave_0_read), // .read .write (character_lcd_0_avalon_lcd_slave_translator_avalon_anti_slave_0_write), // .write .writedata (character_lcd_0_avalon_lcd_slave_translator_avalon_anti_slave_0_writedata), // .writedata .readdata (character_lcd_0_avalon_lcd_slave_translator_avalon_anti_slave_0_readdata), // .readdata .waitrequest (character_lcd_0_avalon_lcd_slave_translator_avalon_anti_slave_0_waitrequest), // .waitrequest .LCD_DATA (character_lcd_0_external_interface_DATA), // external_interface.export .LCD_ON (character_lcd_0_external_interface_ON), // .export .LCD_BLON (character_lcd_0_external_interface_BLON), // .export .LCD_EN (character_lcd_0_external_interface_EN), // .export .LCD_RS (character_lcd_0_external_interface_RS), // .export .LCD_RW (character_lcd_0_external_interface_RW) // .export ); tracking_camera_system_green_leds green_leds ( .clk (altpll_0_c1_clk), // clk.clk .reset_n (~rst_controller_reset_out_reset), // reset.reset_n .address (green_leds_s1_translator_avalon_anti_slave_0_address), // s1.address .write_n (~green_leds_s1_translator_avalon_anti_slave_0_write), // .write_n .writedata (green_leds_s1_translator_avalon_anti_slave_0_writedata), // .writedata .chipselect (green_leds_s1_translator_avalon_anti_slave_0_chipselect), // .chipselect .readdata (green_leds_s1_translator_avalon_anti_slave_0_readdata), // .readdata .out_port (green_leds_external_connection_export) // external_connection.export ); tracking_camera_system_switch switch ( .clk (altpll_0_c1_clk), // clk.clk .reset_n (~rst_controller_reset_out_reset), // reset.reset_n .address (switch_s1_translator_avalon_anti_slave_0_address), // s1.address .readdata (switch_s1_translator_avalon_anti_slave_0_readdata), // .readdata .in_port (switch_external_connection_export) // external_connection.export ); tracking_camera_system_altpll_0 altpll_0 ( .clk (clk_clk), // inclk_interface.clk .reset (rst_controller_001_reset_out_reset), // inclk_interface_reset.reset .read (altpll_0_pll_slave_translator_avalon_anti_slave_0_read), // pll_slave.read .write (altpll_0_pll_slave_translator_avalon_anti_slave_0_write), // .write .address (altpll_0_pll_slave_translator_avalon_anti_slave_0_address), // .address .readdata (altpll_0_pll_slave_translator_avalon_anti_slave_0_readdata), // .readdata .writedata (altpll_0_pll_slave_translator_avalon_anti_slave_0_writedata), // .writedata .c0 (altpll_0_c0_clk), // c0.clk .c1 (altpll_0_c1_clk), // c1.clk .areset (), // areset_conduit.export .locked (), // locked_conduit.export .phasedone () // phasedone_conduit.export ); tracking_camera_system_sdram_0 sdram_0 ( .clk (altpll_0_c1_clk), // clk.clk .reset_n (~rst_controller_reset_out_reset), // reset.reset_n .az_addr (sdram_0_s1_translator_avalon_anti_slave_0_address), // s1.address .az_be_n (~sdram_0_s1_translator_avalon_anti_slave_0_byteenable), // .byteenable_n .az_cs (sdram_0_s1_translator_avalon_anti_slave_0_chipselect), // .chipselect .az_data (sdram_0_s1_translator_avalon_anti_slave_0_writedata), // .writedata .az_rd_n (~sdram_0_s1_translator_avalon_anti_slave_0_read), // .read_n .az_wr_n (~sdram_0_s1_translator_avalon_anti_slave_0_write), // .write_n .za_data (sdram_0_s1_translator_avalon_anti_slave_0_readdata), // .readdata .za_valid (sdram_0_s1_translator_avalon_anti_slave_0_readdatavalid), // .readdatavalid .za_waitrequest (sdram_0_s1_translator_avalon_anti_slave_0_waitrequest), // .waitrequest .zs_addr (sdram_0_wire_addr), // wire.export .zs_ba (sdram_0_wire_ba), // .export .zs_cas_n (sdram_0_wire_cas_n), // .export .zs_cke (sdram_0_wire_cke), // .export .zs_cs_n (sdram_0_wire_cs_n), // .export .zs_dq (sdram_0_wire_dq), // .export .zs_dqm (sdram_0_wire_dqm), // .export .zs_ras_n (sdram_0_wire_ras_n), // .export .zs_we_n (sdram_0_wire_we_n) // .export ); tracking_camera_system_sram_0 sram_0 ( .clk (altpll_0_c1_clk), // clock_reset.clk .reset (rst_controller_reset_out_reset), // clock_reset_reset.reset .SRAM_DQ (sram_0_external_interface_DQ), // external_interface.export .SRAM_ADDR (sram_0_external_interface_ADDR), // .export .SRAM_LB_N (sram_0_external_interface_LB_N), // .export .SRAM_UB_N (sram_0_external_interface_UB_N), // .export .SRAM_CE_N (sram_0_external_interface_CE_N), // .export .SRAM_OE_N (sram_0_external_interface_OE_N), // .export .SRAM_WE_N (sram_0_external_interface_WE_N), // .export .address (sram_0_avalon_sram_slave_translator_avalon_anti_slave_0_address), // avalon_sram_slave.address .byteenable (sram_0_avalon_sram_slave_translator_avalon_anti_slave_0_byteenable), // .byteenable .read (sram_0_avalon_sram_slave_translator_avalon_anti_slave_0_read), // .read .write (sram_0_avalon_sram_slave_translator_avalon_anti_slave_0_write), // .write .writedata (sram_0_avalon_sram_slave_translator_avalon_anti_slave_0_writedata), // .writedata .readdata (sram_0_avalon_sram_slave_translator_avalon_anti_slave_0_readdata), // .readdata .readdatavalid (sram_0_avalon_sram_slave_translator_avalon_anti_slave_0_readdatavalid) // .readdatavalid ); tracking_camera_system_switch switch_0 ( .clk (altpll_0_c1_clk), // clk.clk .reset_n (~rst_controller_reset_out_reset), // reset.reset_n .address (switch_0_s1_translator_avalon_anti_slave_0_address), // s1.address .readdata (switch_0_s1_translator_avalon_anti_slave_0_readdata), // .readdata .in_port (switch_0_external_connection_export) // external_connection.export ); servo_pwm servo_pwm_0 ( .clk (altpll_0_c1_clk), // clock.clk .reset_n (~rst_controller_reset_out_reset), // reset.reset_n .coe_servo (servo_pwm_0_conduit_end_0_export), // conduit_end_0.export .avs_s0_write_n (~servo_pwm_0_s0_translator_avalon_anti_slave_0_write), // s0.write_n .avs_s0_writedata (servo_pwm_0_s0_translator_avalon_anti_slave_0_writedata), // .writedata .avs_s0_read_n (~servo_pwm_0_s0_translator_avalon_anti_slave_0_read), // .read_n .avs_s0_readdata (servo_pwm_0_s0_translator_avalon_anti_slave_0_readdata) // .readdata ); altera_merlin_master_translator #( .AV_ADDRESS_W (25), .AV_DATA_W (32), .AV_BURSTCOUNT_W (1), .AV_BYTEENABLE_W (4), .UAV_ADDRESS_W (25), .UAV_BURSTCOUNT_W (3), .USE_READ (1), .USE_WRITE (0), .USE_BEGINBURSTTRANSFER (0), .USE_BEGINTRANSFER (0), .USE_CHIPSELECT (0), .USE_BURSTCOUNT (0), .USE_READDATAVALID (1), .USE_WAITREQUEST (1), .AV_SYMBOLS_PER_WORD (4), .AV_ADDRESS_SYMBOLS (1), .AV_BURSTCOUNT_SYMBOLS (0), .AV_CONSTANT_BURST_BEHAVIOR (0), .UAV_CONSTANT_BURST_BEHAVIOR (0), .AV_LINEWRAPBURSTS (1), .AV_REGISTERINCOMINGSIGNALS (0) ) nios2_qsys_0_instruction_master_translator ( .clk (altpll_0_c1_clk), // clk.clk .reset (rst_controller_reset_out_reset), // reset.reset .uav_address (nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_address), // avalon_universal_master_0.address .uav_burstcount (nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_burstcount), // .burstcount .uav_read (nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_read), // .read .uav_write (nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_write), // .write .uav_waitrequest (nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest .uav_readdatavalid (nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid .uav_byteenable (nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_byteenable), // .byteenable .uav_readdata (nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_readdata), // .readdata .uav_writedata (nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_writedata), // .writedata .uav_lock (nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_lock), // .lock .uav_debugaccess (nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess .av_address (nios2_qsys_0_instruction_master_address), // avalon_anti_master_0.address .av_waitrequest (nios2_qsys_0_instruction_master_waitrequest), // .waitrequest .av_read (nios2_qsys_0_instruction_master_read), // .read .av_readdata (nios2_qsys_0_instruction_master_readdata), // .readdata .av_readdatavalid (nios2_qsys_0_instruction_master_readdatavalid), // .readdatavalid .av_burstcount (1'b1), // (terminated) .av_byteenable (4'b1111), // (terminated) .av_beginbursttransfer (1'b0), // (terminated) .av_begintransfer (1'b0), // (terminated) .av_chipselect (1'b0), // (terminated) .av_write (1'b0), // (terminated) .av_writedata (32'b00000000000000000000000000000000), // (terminated) .av_lock (1'b0), // (terminated) .av_debugaccess (1'b0), // (terminated) .uav_clken (), // (terminated) .av_clken (1'b1) // (terminated) ); altera_merlin_master_translator #( .AV_ADDRESS_W (25), .AV_DATA_W (32), .AV_BURSTCOUNT_W (1), .AV_BYTEENABLE_W (4), .UAV_ADDRESS_W (25), .UAV_BURSTCOUNT_W (3), .USE_READ (1), .USE_WRITE (1), .USE_BEGINBURSTTRANSFER (0), .USE_BEGINTRANSFER (0), .USE_CHIPSELECT (0), .USE_BURSTCOUNT (0), .USE_READDATAVALID (1), .USE_WAITREQUEST (1), .AV_SYMBOLS_PER_WORD (4), .AV_ADDRESS_SYMBOLS (1), .AV_BURSTCOUNT_SYMBOLS (0), .AV_CONSTANT_BURST_BEHAVIOR (0), .UAV_CONSTANT_BURST_BEHAVIOR (0), .AV_LINEWRAPBURSTS (0), .AV_REGISTERINCOMINGSIGNALS (0) ) nios2_qsys_0_data_master_translator ( .clk (altpll_0_c1_clk), // clk.clk .reset (rst_controller_reset_out_reset), // reset.reset .uav_address (nios2_qsys_0_data_master_translator_avalon_universal_master_0_address), // avalon_universal_master_0.address .uav_burstcount (nios2_qsys_0_data_master_translator_avalon_universal_master_0_burstcount), // .burstcount .uav_read (nios2_qsys_0_data_master_translator_avalon_universal_master_0_read), // .read .uav_write (nios2_qsys_0_data_master_translator_avalon_universal_master_0_write), // .write .uav_waitrequest (nios2_qsys_0_data_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest .uav_readdatavalid (nios2_qsys_0_data_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid .uav_byteenable (nios2_qsys_0_data_master_translator_avalon_universal_master_0_byteenable), // .byteenable .uav_readdata (nios2_qsys_0_data_master_translator_avalon_universal_master_0_readdata), // .readdata .uav_writedata (nios2_qsys_0_data_master_translator_avalon_universal_master_0_writedata), // .writedata .uav_lock (nios2_qsys_0_data_master_translator_avalon_universal_master_0_lock), // .lock .uav_debugaccess (nios2_qsys_0_data_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess .av_address (nios2_qsys_0_data_master_address), // avalon_anti_master_0.address .av_waitrequest (nios2_qsys_0_data_master_waitrequest), // .waitrequest .av_byteenable (nios2_qsys_0_data_master_byteenable), // .byteenable .av_read (nios2_qsys_0_data_master_read), // .read .av_readdata (nios2_qsys_0_data_master_readdata), // .readdata .av_readdatavalid (nios2_qsys_0_data_master_readdatavalid), // .readdatavalid .av_write (nios2_qsys_0_data_master_write), // .write .av_writedata (nios2_qsys_0_data_master_writedata), // .writedata .av_debugaccess (nios2_qsys_0_data_master_debugaccess), // .debugaccess .av_burstcount (1'b1), // (terminated) .av_beginbursttransfer (1'b0), // (terminated) .av_begintransfer (1'b0), // (terminated) .av_chipselect (1'b0), // (terminated) .av_lock (1'b0), // (terminated) .uav_clken (), // (terminated) .av_clken (1'b1) // (terminated) ); altera_merlin_slave_translator #( .AV_ADDRESS_W (9), .AV_DATA_W (32), .UAV_DATA_W (32), .AV_BURSTCOUNT_W (1), .AV_BYTEENABLE_W (4), .UAV_BYTEENABLE_W (4), .UAV_ADDRESS_W (25), .UAV_BURSTCOUNT_W (3), .AV_READLATENCY (0), .USE_READDATAVALID (0), .USE_WAITREQUEST (0), .USE_UAV_CLKEN (0), .AV_SYMBOLS_PER_WORD (4), .AV_ADDRESS_SYMBOLS (0), .AV_BURSTCOUNT_SYMBOLS (0), .AV_CONSTANT_BURST_BEHAVIOR (0), .UAV_CONSTANT_BURST_BEHAVIOR (0), .AV_REQUIRE_UNALIGNED_ADDRESSES (0), .CHIPSELECT_THROUGH_READLATENCY (0), .AV_READ_WAIT_CYCLES (1), .AV_WRITE_WAIT_CYCLES (0), .AV_SETUP_WAIT_CYCLES (0), .AV_DATA_HOLD_CYCLES (0) ) nios2_qsys_0_jtag_debug_module_translator ( .clk (altpll_0_c1_clk), // clk.clk .reset (rst_controller_reset_out_reset), // reset.reset .uav_address (nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_address), // avalon_universal_slave_0.address .uav_burstcount (nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount .uav_read (nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_read), // .read .uav_write (nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_write), // .write .uav_waitrequest (nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest .uav_readdatavalid (nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid .uav_byteenable (nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable .uav_readdata (nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata .uav_writedata (nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata .uav_lock (nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_lock), // .lock .uav_debugaccess (nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess .av_address (nios2_qsys_0_jtag_debug_module_translator_avalon_anti_slave_0_address), // avalon_anti_slave_0.address .av_write (nios2_qsys_0_jtag_debug_module_translator_avalon_anti_slave_0_write), // .write .av_readdata (nios2_qsys_0_jtag_debug_module_translator_avalon_anti_slave_0_readdata), // .readdata .av_writedata (nios2_qsys_0_jtag_debug_module_translator_avalon_anti_slave_0_writedata), // .writedata .av_begintransfer (nios2_qsys_0_jtag_debug_module_translator_avalon_anti_slave_0_begintransfer), // .begintransfer .av_byteenable (nios2_qsys_0_jtag_debug_module_translator_avalon_anti_slave_0_byteenable), // .byteenable .av_chipselect (nios2_qsys_0_jtag_debug_module_translator_avalon_anti_slave_0_chipselect), // .chipselect .av_debugaccess (nios2_qsys_0_jtag_debug_module_translator_avalon_anti_slave_0_debugaccess), // .debugaccess .av_read (), // (terminated) .av_beginbursttransfer (), // (terminated) .av_burstcount (), // (terminated) .av_readdatavalid (1'b0), // (terminated) .av_waitrequest (1'b0), // (terminated) .av_writebyteenable (), // (terminated) .av_lock (), // (terminated) .av_clken (), // (terminated) .uav_clken (1'b0), // (terminated) .av_outputenable () // (terminated) ); altera_merlin_slave_translator #( .AV_ADDRESS_W (12), .AV_DATA_W (32), .UAV_DATA_W (32), .AV_BURSTCOUNT_W (1), .AV_BYTEENABLE_W (4), .UAV_BYTEENABLE_W (4), .UAV_ADDRESS_W (25), .UAV_BURSTCOUNT_W (3), .AV_READLATENCY (1), .USE_READDATAVALID (0), .USE_WAITREQUEST (0), .USE_UAV_CLKEN (0), .AV_SYMBOLS_PER_WORD (4), .AV_ADDRESS_SYMBOLS (0), .AV_BURSTCOUNT_SYMBOLS (0), .AV_CONSTANT_BURST_BEHAVIOR (0), .UAV_CONSTANT_BURST_BEHAVIOR (0), .AV_REQUIRE_UNALIGNED_ADDRESSES (0), .CHIPSELECT_THROUGH_READLATENCY (0), .AV_READ_WAIT_CYCLES (0), .AV_WRITE_WAIT_CYCLES (0), .AV_SETUP_WAIT_CYCLES (0), .AV_DATA_HOLD_CYCLES (0) ) onchip_memory2_0_s1_translator ( .clk (altpll_0_c1_clk), // clk.clk .reset (rst_controller_reset_out_reset), // reset.reset .uav_address (onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_address), // avalon_universal_slave_0.address .uav_burstcount (onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount .uav_read (onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_read), // .read .uav_write (onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_write), // .write .uav_waitrequest (onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest .uav_readdatavalid (onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid .uav_byteenable (onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable .uav_readdata (onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata .uav_writedata (onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata .uav_lock (onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_lock), // .lock .uav_debugaccess (onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess .av_address (onchip_memory2_0_s1_translator_avalon_anti_slave_0_address), // avalon_anti_slave_0.address .av_write (onchip_memory2_0_s1_translator_avalon_anti_slave_0_write), // .write .av_readdata (onchip_memory2_0_s1_translator_avalon_anti_slave_0_readdata), // .readdata .av_writedata (onchip_memory2_0_s1_translator_avalon_anti_slave_0_writedata), // .writedata .av_byteenable (onchip_memory2_0_s1_translator_avalon_anti_slave_0_byteenable), // .byteenable .av_chipselect (onchip_memory2_0_s1_translator_avalon_anti_slave_0_chipselect), // .chipselect .av_clken (onchip_memory2_0_s1_translator_avalon_anti_slave_0_clken), // .clken .av_read (), // (terminated) .av_begintransfer (), // (terminated) .av_beginbursttransfer (), // (terminated) .av_burstcount (), // (terminated) .av_readdatavalid (1'b0), // (terminated) .av_waitrequest (1'b0), // (terminated) .av_writebyteenable (), // (terminated) .av_lock (), // (terminated) .uav_clken (1'b0), // (terminated) .av_debugaccess (), // (terminated) .av_outputenable () // (terminated) ); altera_merlin_slave_translator #( .AV_ADDRESS_W (22), .AV_DATA_W (16), .UAV_DATA_W (16), .AV_BURSTCOUNT_W (1), .AV_BYTEENABLE_W (2), .UAV_BYTEENABLE_W (2), .UAV_ADDRESS_W (25), .UAV_BURSTCOUNT_W (2), .AV_READLATENCY (0), .USE_READDATAVALID (1), .USE_WAITREQUEST (1), .USE_UAV_CLKEN (0), .AV_SYMBOLS_PER_WORD (2), .AV_ADDRESS_SYMBOLS (0), .AV_BURSTCOUNT_SYMBOLS (0), .AV_CONSTANT_BURST_BEHAVIOR (0), .UAV_CONSTANT_BURST_BEHAVIOR (0), .AV_REQUIRE_UNALIGNED_ADDRESSES (0), .CHIPSELECT_THROUGH_READLATENCY (0), .AV_READ_WAIT_CYCLES (1), .AV_WRITE_WAIT_CYCLES (0), .AV_SETUP_WAIT_CYCLES (0), .AV_DATA_HOLD_CYCLES (0) ) sdram_0_s1_translator ( .clk (altpll_0_c1_clk), // clk.clk .reset (rst_controller_reset_out_reset), // reset.reset .uav_address (sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_address), // avalon_universal_slave_0.address .uav_burstcount (sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount .uav_read (sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_read), // .read .uav_write (sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_write), // .write .uav_waitrequest (sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest .uav_readdatavalid (sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid .uav_byteenable (sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable .uav_readdata (sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata .uav_writedata (sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata .uav_lock (sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_lock), // .lock .uav_debugaccess (sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess .av_address (sdram_0_s1_translator_avalon_anti_slave_0_address), // avalon_anti_slave_0.address .av_write (sdram_0_s1_translator_avalon_anti_slave_0_write), // .write .av_read (sdram_0_s1_translator_avalon_anti_slave_0_read), // .read .av_readdata (sdram_0_s1_translator_avalon_anti_slave_0_readdata), // .readdata .av_writedata (sdram_0_s1_translator_avalon_anti_slave_0_writedata), // .writedata .av_byteenable (sdram_0_s1_translator_avalon_anti_slave_0_byteenable), // .byteenable .av_readdatavalid (sdram_0_s1_translator_avalon_anti_slave_0_readdatavalid), // .readdatavalid .av_waitrequest (sdram_0_s1_translator_avalon_anti_slave_0_waitrequest), // .waitrequest .av_chipselect (sdram_0_s1_translator_avalon_anti_slave_0_chipselect), // .chipselect .av_begintransfer (), // (terminated) .av_beginbursttransfer (), // (terminated) .av_burstcount (), // (terminated) .av_writebyteenable (), // (terminated) .av_lock (), // (terminated) .av_clken (), // (terminated) .uav_clken (1'b0), // (terminated) .av_debugaccess (), // (terminated) .av_outputenable () // (terminated) ); altera_merlin_slave_translator #( .AV_ADDRESS_W (18), .AV_DATA_W (16), .UAV_DATA_W (16), .AV_BURSTCOUNT_W (1), .AV_BYTEENABLE_W (2), .UAV_BYTEENABLE_W (2), .UAV_ADDRESS_W (25), .UAV_BURSTCOUNT_W (2), .AV_READLATENCY (0), .USE_READDATAVALID (1), .USE_WAITREQUEST (0), .USE_UAV_CLKEN (0), .AV_SYMBOLS_PER_WORD (2), .AV_ADDRESS_SYMBOLS (0), .AV_BURSTCOUNT_SYMBOLS (0), .AV_CONSTANT_BURST_BEHAVIOR (0), .UAV_CONSTANT_BURST_BEHAVIOR (0), .AV_REQUIRE_UNALIGNED_ADDRESSES (0), .CHIPSELECT_THROUGH_READLATENCY (0), .AV_READ_WAIT_CYCLES (0), .AV_WRITE_WAIT_CYCLES (0), .AV_SETUP_WAIT_CYCLES (0), .AV_DATA_HOLD_CYCLES (0) ) sram_0_avalon_sram_slave_translator ( .clk (altpll_0_c1_clk), // clk.clk .reset (rst_controller_reset_out_reset), // reset.reset .uav_address (sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_address), // avalon_universal_slave_0.address .uav_burstcount (sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount .uav_read (sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_read), // .read .uav_write (sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_write), // .write .uav_waitrequest (sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest .uav_readdatavalid (sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid .uav_byteenable (sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable .uav_readdata (sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata .uav_writedata (sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata .uav_lock (sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_lock), // .lock .uav_debugaccess (sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess .av_address (sram_0_avalon_sram_slave_translator_avalon_anti_slave_0_address), // avalon_anti_slave_0.address .av_write (sram_0_avalon_sram_slave_translator_avalon_anti_slave_0_write), // .write .av_read (sram_0_avalon_sram_slave_translator_avalon_anti_slave_0_read), // .read .av_readdata (sram_0_avalon_sram_slave_translator_avalon_anti_slave_0_readdata), // .readdata .av_writedata (sram_0_avalon_sram_slave_translator_avalon_anti_slave_0_writedata), // .writedata .av_byteenable (sram_0_avalon_sram_slave_translator_avalon_anti_slave_0_byteenable), // .byteenable .av_readdatavalid (sram_0_avalon_sram_slave_translator_avalon_anti_slave_0_readdatavalid), // .readdatavalid .av_begintransfer (), // (terminated) .av_beginbursttransfer (), // (terminated) .av_burstcount (), // (terminated) .av_waitrequest (1'b0), // (terminated) .av_writebyteenable (), // (terminated) .av_lock (), // (terminated) .av_chipselect (), // (terminated) .av_clken (), // (terminated) .uav_clken (1'b0), // (terminated) .av_debugaccess (), // (terminated) .av_outputenable () // (terminated) ); altera_merlin_slave_translator #( .AV_ADDRESS_W (2), .AV_DATA_W (32), .UAV_DATA_W (32), .AV_BURSTCOUNT_W (1), .AV_BYTEENABLE_W (4), .UAV_BYTEENABLE_W (4), .UAV_ADDRESS_W (25), .UAV_BURSTCOUNT_W (3), .AV_READLATENCY (0), .USE_READDATAVALID (0), .USE_WAITREQUEST (0), .USE_UAV_CLKEN (0), .AV_SYMBOLS_PER_WORD (4), .AV_ADDRESS_SYMBOLS (0), .AV_BURSTCOUNT_SYMBOLS (0), .AV_CONSTANT_BURST_BEHAVIOR (0), .UAV_CONSTANT_BURST_BEHAVIOR (0), .AV_REQUIRE_UNALIGNED_ADDRESSES (0), .CHIPSELECT_THROUGH_READLATENCY (0), .AV_READ_WAIT_CYCLES (0), .AV_WRITE_WAIT_CYCLES (0), .AV_SETUP_WAIT_CYCLES (0), .AV_DATA_HOLD_CYCLES (0) ) altpll_0_pll_slave_translator ( .clk (clk_clk), // clk.clk .reset (rst_controller_001_reset_out_reset), // reset.reset .uav_address (altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_m0_address), // avalon_universal_slave_0.address .uav_burstcount (altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount .uav_read (altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_m0_read), // .read .uav_write (altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_m0_write), // .write .uav_waitrequest (altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest .uav_readdatavalid (altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid .uav_byteenable (altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable .uav_readdata (altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata .uav_writedata (altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata .uav_lock (altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_m0_lock), // .lock .uav_debugaccess (altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess .av_address (altpll_0_pll_slave_translator_avalon_anti_slave_0_address), // avalon_anti_slave_0.address .av_write (altpll_0_pll_slave_translator_avalon_anti_slave_0_write), // .write .av_read (altpll_0_pll_slave_translator_avalon_anti_slave_0_read), // .read .av_readdata (altpll_0_pll_slave_translator_avalon_anti_slave_0_readdata), // .readdata .av_writedata (altpll_0_pll_slave_translator_avalon_anti_slave_0_writedata), // .writedata .av_begintransfer (), // (terminated) .av_beginbursttransfer (), // (terminated) .av_burstcount (), // (terminated) .av_byteenable (), // (terminated) .av_readdatavalid (1'b0), // (terminated) .av_waitrequest (1'b0), // (terminated) .av_writebyteenable (), // (terminated) .av_lock (), // (terminated) .av_chipselect (), // (terminated) .av_clken (), // (terminated) .uav_clken (1'b0), // (terminated) .av_debugaccess (), // (terminated) .av_outputenable () // (terminated) ); altera_merlin_slave_translator #( .AV_ADDRESS_W (1), .AV_DATA_W (32), .UAV_DATA_W (32), .AV_BURSTCOUNT_W (1), .AV_BYTEENABLE_W (4), .UAV_BYTEENABLE_W (4), .UAV_ADDRESS_W (25), .UAV_BURSTCOUNT_W (3), .AV_READLATENCY (0), .USE_READDATAVALID (0), .USE_WAITREQUEST (0), .USE_UAV_CLKEN (0), .AV_SYMBOLS_PER_WORD (4), .AV_ADDRESS_SYMBOLS (0), .AV_BURSTCOUNT_SYMBOLS (0), .AV_CONSTANT_BURST_BEHAVIOR (0), .UAV_CONSTANT_BURST_BEHAVIOR (0), .AV_REQUIRE_UNALIGNED_ADDRESSES (0), .CHIPSELECT_THROUGH_READLATENCY (0), .AV_READ_WAIT_CYCLES (1), .AV_WRITE_WAIT_CYCLES (0), .AV_SETUP_WAIT_CYCLES (0), .AV_DATA_HOLD_CYCLES (0) ) sysid_qsys_0_control_slave_translator ( .clk (altpll_0_c1_clk), // clk.clk .reset (rst_controller_reset_out_reset), // reset.reset .uav_address (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_address), // avalon_universal_slave_0.address .uav_burstcount (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount .uav_read (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_read), // .read .uav_write (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_write), // .write .uav_waitrequest (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest .uav_readdatavalid (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid .uav_byteenable (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable .uav_readdata (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata .uav_writedata (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata .uav_lock (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_lock), // .lock .uav_debugaccess (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess .av_address (sysid_qsys_0_control_slave_translator_avalon_anti_slave_0_address), // avalon_anti_slave_0.address .av_readdata (sysid_qsys_0_control_slave_translator_avalon_anti_slave_0_readdata), // .readdata .av_write (), // (terminated) .av_read (), // (terminated) .av_writedata (), // (terminated) .av_begintransfer (), // (terminated) .av_beginbursttransfer (), // (terminated) .av_burstcount (), // (terminated) .av_byteenable (), // (terminated) .av_readdatavalid (1'b0), // (terminated) .av_waitrequest (1'b0), // (terminated) .av_writebyteenable (), // (terminated) .av_lock (), // (terminated) .av_chipselect (), // (terminated) .av_clken (), // (terminated) .uav_clken (1'b0), // (terminated) .av_debugaccess (), // (terminated) .av_outputenable () // (terminated) ); altera_merlin_slave_translator #( .AV_ADDRESS_W (3), .AV_DATA_W (16), .UAV_DATA_W (32), .AV_BURSTCOUNT_W (1), .AV_BYTEENABLE_W (1), .UAV_BYTEENABLE_W (4), .UAV_ADDRESS_W (25), .UAV_BURSTCOUNT_W (3), .AV_READLATENCY (0), .USE_READDATAVALID (0), .USE_WAITREQUEST (0), .USE_UAV_CLKEN (0), .AV_SYMBOLS_PER_WORD (4), .AV_ADDRESS_SYMBOLS (0), .AV_BURSTCOUNT_SYMBOLS (0), .AV_CONSTANT_BURST_BEHAVIOR (0), .UAV_CONSTANT_BURST_BEHAVIOR (0), .AV_REQUIRE_UNALIGNED_ADDRESSES (0), .CHIPSELECT_THROUGH_READLATENCY (0), .AV_READ_WAIT_CYCLES (1), .AV_WRITE_WAIT_CYCLES (0), .AV_SETUP_WAIT_CYCLES (0), .AV_DATA_HOLD_CYCLES (0) ) timer_0_s1_translator ( .clk (altpll_0_c1_clk), // clk.clk .reset (rst_controller_reset_out_reset), // reset.reset .uav_address (timer_0_s1_translator_avalon_universal_slave_0_agent_m0_address), // avalon_universal_slave_0.address .uav_burstcount (timer_0_s1_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount .uav_read (timer_0_s1_translator_avalon_universal_slave_0_agent_m0_read), // .read .uav_write (timer_0_s1_translator_avalon_universal_slave_0_agent_m0_write), // .write .uav_waitrequest (timer_0_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest .uav_readdatavalid (timer_0_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid .uav_byteenable (timer_0_s1_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable .uav_readdata (timer_0_s1_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata .uav_writedata (timer_0_s1_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata .uav_lock (timer_0_s1_translator_avalon_universal_slave_0_agent_m0_lock), // .lock .uav_debugaccess (timer_0_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess .av_address (timer_0_s1_translator_avalon_anti_slave_0_address), // avalon_anti_slave_0.address .av_write (timer_0_s1_translator_avalon_anti_slave_0_write), // .write .av_readdata (timer_0_s1_translator_avalon_anti_slave_0_readdata), // .readdata .av_writedata (timer_0_s1_translator_avalon_anti_slave_0_writedata), // .writedata .av_chipselect (timer_0_s1_translator_avalon_anti_slave_0_chipselect), // .chipselect .av_read (), // (terminated) .av_begintransfer (), // (terminated) .av_beginbursttransfer (), // (terminated) .av_burstcount (), // (terminated) .av_byteenable (), // (terminated) .av_readdatavalid (1'b0), // (terminated) .av_waitrequest (1'b0), // (terminated) .av_writebyteenable (), // (terminated) .av_lock (), // (terminated) .av_clken (), // (terminated) .uav_clken (1'b0), // (terminated) .av_debugaccess (), // (terminated) .av_outputenable () // (terminated) ); altera_merlin_slave_translator #( .AV_ADDRESS_W (1), .AV_DATA_W (32), .UAV_DATA_W (32), .AV_BURSTCOUNT_W (1), .AV_BYTEENABLE_W (1), .UAV_BYTEENABLE_W (4), .UAV_ADDRESS_W (25), .UAV_BURSTCOUNT_W (3), .AV_READLATENCY (0), .USE_READDATAVALID (0), .USE_WAITREQUEST (1), .USE_UAV_CLKEN (0), .AV_SYMBOLS_PER_WORD (4), .AV_ADDRESS_SYMBOLS (0), .AV_BURSTCOUNT_SYMBOLS (0), .AV_CONSTANT_BURST_BEHAVIOR (0), .UAV_CONSTANT_BURST_BEHAVIOR (0), .AV_REQUIRE_UNALIGNED_ADDRESSES (0), .CHIPSELECT_THROUGH_READLATENCY (0), .AV_READ_WAIT_CYCLES (1), .AV_WRITE_WAIT_CYCLES (0), .AV_SETUP_WAIT_CYCLES (0), .AV_DATA_HOLD_CYCLES (0) ) jtag_uart_0_avalon_jtag_slave_translator ( .clk (altpll_0_c1_clk), // clk.clk .reset (rst_controller_reset_out_reset), // reset.reset .uav_address (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_address), // avalon_universal_slave_0.address .uav_burstcount (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount .uav_read (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_read), // .read .uav_write (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_write), // .write .uav_waitrequest (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest .uav_readdatavalid (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid .uav_byteenable (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable .uav_readdata (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata .uav_writedata (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata .uav_lock (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_lock), // .lock .uav_debugaccess (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess .av_address (jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_address), // avalon_anti_slave_0.address .av_write (jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_write), // .write .av_read (jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_read), // .read .av_readdata (jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_readdata), // .readdata .av_writedata (jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_writedata), // .writedata .av_waitrequest (jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_waitrequest), // .waitrequest .av_chipselect (jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_chipselect), // .chipselect .av_begintransfer (), // (terminated) .av_beginbursttransfer (), // (terminated) .av_burstcount (), // (terminated) .av_byteenable (), // (terminated) .av_readdatavalid (1'b0), // (terminated) .av_writebyteenable (), // (terminated) .av_lock (), // (terminated) .av_clken (), // (terminated) .uav_clken (1'b0), // (terminated) .av_debugaccess (), // (terminated) .av_outputenable () // (terminated) ); altera_merlin_slave_translator #( .AV_ADDRESS_W (1), .AV_DATA_W (8), .UAV_DATA_W (8), .AV_BURSTCOUNT_W (1), .AV_BYTEENABLE_W (1), .UAV_BYTEENABLE_W (1), .UAV_ADDRESS_W (25), .UAV_BURSTCOUNT_W (1), .AV_READLATENCY (0), .USE_READDATAVALID (0), .USE_WAITREQUEST (1), .USE_UAV_CLKEN (0), .AV_SYMBOLS_PER_WORD (1), .AV_ADDRESS_SYMBOLS (0), .AV_BURSTCOUNT_SYMBOLS (0), .AV_CONSTANT_BURST_BEHAVIOR (0), .UAV_CONSTANT_BURST_BEHAVIOR (0), .AV_REQUIRE_UNALIGNED_ADDRESSES (0), .CHIPSELECT_THROUGH_READLATENCY (0), .AV_READ_WAIT_CYCLES (1), .AV_WRITE_WAIT_CYCLES (0), .AV_SETUP_WAIT_CYCLES (0), .AV_DATA_HOLD_CYCLES (0) ) character_lcd_0_avalon_lcd_slave_translator ( .clk (altpll_0_c1_clk), // clk.clk .reset (rst_controller_reset_out_reset), // reset.reset .uav_address (character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_m0_address), // avalon_universal_slave_0.address .uav_burstcount (character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount .uav_read (character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_m0_read), // .read .uav_write (character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_m0_write), // .write .uav_waitrequest (character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest .uav_readdatavalid (character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid .uav_byteenable (character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable .uav_readdata (character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata .uav_writedata (character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata .uav_lock (character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_m0_lock), // .lock .uav_debugaccess (character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess .av_address (character_lcd_0_avalon_lcd_slave_translator_avalon_anti_slave_0_address), // avalon_anti_slave_0.address .av_write (character_lcd_0_avalon_lcd_slave_translator_avalon_anti_slave_0_write), // .write .av_read (character_lcd_0_avalon_lcd_slave_translator_avalon_anti_slave_0_read), // .read .av_readdata (character_lcd_0_avalon_lcd_slave_translator_avalon_anti_slave_0_readdata), // .readdata .av_writedata (character_lcd_0_avalon_lcd_slave_translator_avalon_anti_slave_0_writedata), // .writedata .av_waitrequest (character_lcd_0_avalon_lcd_slave_translator_avalon_anti_slave_0_waitrequest), // .waitrequest .av_chipselect (character_lcd_0_avalon_lcd_slave_translator_avalon_anti_slave_0_chipselect), // .chipselect .av_begintransfer (), // (terminated) .av_beginbursttransfer (), // (terminated) .av_burstcount (), // (terminated) .av_byteenable (), // (terminated) .av_readdatavalid (1'b0), // (terminated) .av_writebyteenable (), // (terminated) .av_lock (), // (terminated) .av_clken (), // (terminated) .uav_clken (1'b0), // (terminated) .av_debugaccess (), // (terminated) .av_outputenable () // (terminated) ); altera_merlin_slave_translator #( .AV_ADDRESS_W (2), .AV_DATA_W (32), .UAV_DATA_W (32), .AV_BURSTCOUNT_W (1), .AV_BYTEENABLE_W (1), .UAV_BYTEENABLE_W (4), .UAV_ADDRESS_W (25), .UAV_BURSTCOUNT_W (3), .AV_READLATENCY (0), .USE_READDATAVALID (0), .USE_WAITREQUEST (0), .USE_UAV_CLKEN (0), .AV_SYMBOLS_PER_WORD (4), .AV_ADDRESS_SYMBOLS (0), .AV_BURSTCOUNT_SYMBOLS (0), .AV_CONSTANT_BURST_BEHAVIOR (0), .UAV_CONSTANT_BURST_BEHAVIOR (0), .AV_REQUIRE_UNALIGNED_ADDRESSES (0), .CHIPSELECT_THROUGH_READLATENCY (0), .AV_READ_WAIT_CYCLES (1), .AV_WRITE_WAIT_CYCLES (0), .AV_SETUP_WAIT_CYCLES (0), .AV_DATA_HOLD_CYCLES (0) ) green_leds_s1_translator ( .clk (altpll_0_c1_clk), // clk.clk .reset (rst_controller_reset_out_reset), // reset.reset .uav_address (green_leds_s1_translator_avalon_universal_slave_0_agent_m0_address), // avalon_universal_slave_0.address .uav_burstcount (green_leds_s1_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount .uav_read (green_leds_s1_translator_avalon_universal_slave_0_agent_m0_read), // .read .uav_write (green_leds_s1_translator_avalon_universal_slave_0_agent_m0_write), // .write .uav_waitrequest (green_leds_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest .uav_readdatavalid (green_leds_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid .uav_byteenable (green_leds_s1_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable .uav_readdata (green_leds_s1_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata .uav_writedata (green_leds_s1_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata .uav_lock (green_leds_s1_translator_avalon_universal_slave_0_agent_m0_lock), // .lock .uav_debugaccess (green_leds_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess .av_address (green_leds_s1_translator_avalon_anti_slave_0_address), // avalon_anti_slave_0.address .av_write (green_leds_s1_translator_avalon_anti_slave_0_write), // .write .av_readdata (green_leds_s1_translator_avalon_anti_slave_0_readdata), // .readdata .av_writedata (green_leds_s1_translator_avalon_anti_slave_0_writedata), // .writedata .av_chipselect (green_leds_s1_translator_avalon_anti_slave_0_chipselect), // .chipselect .av_read (), // (terminated) .av_begintransfer (), // (terminated) .av_beginbursttransfer (), // (terminated) .av_burstcount (), // (terminated) .av_byteenable (), // (terminated) .av_readdatavalid (1'b0), // (terminated) .av_waitrequest (1'b0), // (terminated) .av_writebyteenable (), // (terminated) .av_lock (), // (terminated) .av_clken (), // (terminated) .uav_clken (1'b0), // (terminated) .av_debugaccess (), // (terminated) .av_outputenable () // (terminated) ); altera_merlin_slave_translator #( .AV_ADDRESS_W (2), .AV_DATA_W (32), .UAV_DATA_W (32), .AV_BURSTCOUNT_W (1), .AV_BYTEENABLE_W (1), .UAV_BYTEENABLE_W (4), .UAV_ADDRESS_W (25), .UAV_BURSTCOUNT_W (3), .AV_READLATENCY (0), .USE_READDATAVALID (0), .USE_WAITREQUEST (0), .USE_UAV_CLKEN (0), .AV_SYMBOLS_PER_WORD (4), .AV_ADDRESS_SYMBOLS (0), .AV_BURSTCOUNT_SYMBOLS (0), .AV_CONSTANT_BURST_BEHAVIOR (0), .UAV_CONSTANT_BURST_BEHAVIOR (0), .AV_REQUIRE_UNALIGNED_ADDRESSES (0), .CHIPSELECT_THROUGH_READLATENCY (0), .AV_READ_WAIT_CYCLES (1), .AV_WRITE_WAIT_CYCLES (0), .AV_SETUP_WAIT_CYCLES (0), .AV_DATA_HOLD_CYCLES (0) ) switch_s1_translator ( .clk (altpll_0_c1_clk), // clk.clk .reset (rst_controller_reset_out_reset), // reset.reset .uav_address (switch_s1_translator_avalon_universal_slave_0_agent_m0_address), // avalon_universal_slave_0.address .uav_burstcount (switch_s1_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount .uav_read (switch_s1_translator_avalon_universal_slave_0_agent_m0_read), // .read .uav_write (switch_s1_translator_avalon_universal_slave_0_agent_m0_write), // .write .uav_waitrequest (switch_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest .uav_readdatavalid (switch_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid .uav_byteenable (switch_s1_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable .uav_readdata (switch_s1_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata .uav_writedata (switch_s1_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata .uav_lock (switch_s1_translator_avalon_universal_slave_0_agent_m0_lock), // .lock .uav_debugaccess (switch_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess .av_address (switch_s1_translator_avalon_anti_slave_0_address), // avalon_anti_slave_0.address .av_readdata (switch_s1_translator_avalon_anti_slave_0_readdata), // .readdata .av_write (), // (terminated) .av_read (), // (terminated) .av_writedata (), // (terminated) .av_begintransfer (), // (terminated) .av_beginbursttransfer (), // (terminated) .av_burstcount (), // (terminated) .av_byteenable (), // (terminated) .av_readdatavalid (1'b0), // (terminated) .av_waitrequest (1'b0), // (terminated) .av_writebyteenable (), // (terminated) .av_lock (), // (terminated) .av_chipselect (), // (terminated) .av_clken (), // (terminated) .uav_clken (1'b0), // (terminated) .av_debugaccess (), // (terminated) .av_outputenable () // (terminated) ); altera_merlin_slave_translator #( .AV_ADDRESS_W (2), .AV_DATA_W (32), .UAV_DATA_W (32), .AV_BURSTCOUNT_W (1), .AV_BYTEENABLE_W (1), .UAV_BYTEENABLE_W (4), .UAV_ADDRESS_W (25), .UAV_BURSTCOUNT_W (3), .AV_READLATENCY (0), .USE_READDATAVALID (0), .USE_WAITREQUEST (0), .USE_UAV_CLKEN (0), .AV_SYMBOLS_PER_WORD (4), .AV_ADDRESS_SYMBOLS (0), .AV_BURSTCOUNT_SYMBOLS (0), .AV_CONSTANT_BURST_BEHAVIOR (0), .UAV_CONSTANT_BURST_BEHAVIOR (0), .AV_REQUIRE_UNALIGNED_ADDRESSES (0), .CHIPSELECT_THROUGH_READLATENCY (0), .AV_READ_WAIT_CYCLES (1), .AV_WRITE_WAIT_CYCLES (0), .AV_SETUP_WAIT_CYCLES (0), .AV_DATA_HOLD_CYCLES (0) ) switch_0_s1_translator ( .clk (altpll_0_c1_clk), // clk.clk .reset (rst_controller_reset_out_reset), // reset.reset .uav_address (switch_0_s1_translator_avalon_universal_slave_0_agent_m0_address), // avalon_universal_slave_0.address .uav_burstcount (switch_0_s1_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount .uav_read (switch_0_s1_translator_avalon_universal_slave_0_agent_m0_read), // .read .uav_write (switch_0_s1_translator_avalon_universal_slave_0_agent_m0_write), // .write .uav_waitrequest (switch_0_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest .uav_readdatavalid (switch_0_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid .uav_byteenable (switch_0_s1_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable .uav_readdata (switch_0_s1_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata .uav_writedata (switch_0_s1_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata .uav_lock (switch_0_s1_translator_avalon_universal_slave_0_agent_m0_lock), // .lock .uav_debugaccess (switch_0_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess .av_address (switch_0_s1_translator_avalon_anti_slave_0_address), // avalon_anti_slave_0.address .av_readdata (switch_0_s1_translator_avalon_anti_slave_0_readdata), // .readdata .av_write (), // (terminated) .av_read (), // (terminated) .av_writedata (), // (terminated) .av_begintransfer (), // (terminated) .av_beginbursttransfer (), // (terminated) .av_burstcount (), // (terminated) .av_byteenable (), // (terminated) .av_readdatavalid (1'b0), // (terminated) .av_waitrequest (1'b0), // (terminated) .av_writebyteenable (), // (terminated) .av_lock (), // (terminated) .av_chipselect (), // (terminated) .av_clken (), // (terminated) .uav_clken (1'b0), // (terminated) .av_debugaccess (), // (terminated) .av_outputenable () // (terminated) ); altera_merlin_slave_translator #( .AV_ADDRESS_W (1), .AV_DATA_W (32), .UAV_DATA_W (32), .AV_BURSTCOUNT_W (1), .AV_BYTEENABLE_W (4), .UAV_BYTEENABLE_W (4), .UAV_ADDRESS_W (25), .UAV_BURSTCOUNT_W (3), .AV_READLATENCY (0), .USE_READDATAVALID (0), .USE_WAITREQUEST (0), .USE_UAV_CLKEN (0), .AV_SYMBOLS_PER_WORD (4), .AV_ADDRESS_SYMBOLS (0), .AV_BURSTCOUNT_SYMBOLS (0), .AV_CONSTANT_BURST_BEHAVIOR (0), .UAV_CONSTANT_BURST_BEHAVIOR (0), .AV_REQUIRE_UNALIGNED_ADDRESSES (0), .CHIPSELECT_THROUGH_READLATENCY (0), .AV_READ_WAIT_CYCLES (1), .AV_WRITE_WAIT_CYCLES (0), .AV_SETUP_WAIT_CYCLES (0), .AV_DATA_HOLD_CYCLES (0) ) servo_pwm_0_s0_translator ( .clk (altpll_0_c1_clk), // clk.clk .reset (rst_controller_reset_out_reset), // reset.reset .uav_address (servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_m0_address), // avalon_universal_slave_0.address .uav_burstcount (servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount .uav_read (servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_m0_read), // .read .uav_write (servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_m0_write), // .write .uav_waitrequest (servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest .uav_readdatavalid (servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid .uav_byteenable (servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable .uav_readdata (servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata .uav_writedata (servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata .uav_lock (servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_m0_lock), // .lock .uav_debugaccess (servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess .av_write (servo_pwm_0_s0_translator_avalon_anti_slave_0_write), // avalon_anti_slave_0.write .av_read (servo_pwm_0_s0_translator_avalon_anti_slave_0_read), // .read .av_readdata (servo_pwm_0_s0_translator_avalon_anti_slave_0_readdata), // .readdata .av_writedata (servo_pwm_0_s0_translator_avalon_anti_slave_0_writedata), // .writedata .av_address (), // (terminated) .av_begintransfer (), // (terminated) .av_beginbursttransfer (), // (terminated) .av_burstcount (), // (terminated) .av_byteenable (), // (terminated) .av_readdatavalid (1'b0), // (terminated) .av_waitrequest (1'b0), // (terminated) .av_writebyteenable (), // (terminated) .av_lock (), // (terminated) .av_chipselect (), // (terminated) .av_clken (), // (terminated) .uav_clken (1'b0), // (terminated) .av_debugaccess (), // (terminated) .av_outputenable () // (terminated) ); altera_merlin_master_agent #( .PKT_PROTECTION_H (93), .PKT_PROTECTION_L (91), .PKT_BEGIN_BURST (80), .PKT_BURSTWRAP_H (72), .PKT_BURSTWRAP_L (70), .PKT_BURST_SIZE_H (75), .PKT_BURST_SIZE_L (73), .PKT_BURST_TYPE_H (77), .PKT_BURST_TYPE_L (76), .PKT_BYTE_CNT_H (69), .PKT_BYTE_CNT_L (67), .PKT_ADDR_H (60), .PKT_ADDR_L (36), .PKT_TRANS_COMPRESSED_READ (61), .PKT_TRANS_POSTED (62), .PKT_TRANS_WRITE (63), .PKT_TRANS_READ (64), .PKT_TRANS_LOCK (65), .PKT_TRANS_EXCLUSIVE (66), .PKT_DATA_H (31), .PKT_DATA_L (0), .PKT_BYTEEN_H (35), .PKT_BYTEEN_L (32), .PKT_SRC_ID_H (85), .PKT_SRC_ID_L (82), .PKT_DEST_ID_H (89), .PKT_DEST_ID_L (86), .PKT_THREAD_ID_H (90), .PKT_THREAD_ID_L (90), .PKT_CACHE_H (97), .PKT_CACHE_L (94), .PKT_DATA_SIDEBAND_H (79), .PKT_DATA_SIDEBAND_L (79), .PKT_QOS_H (81), .PKT_QOS_L (81), .PKT_ADDR_SIDEBAND_H (78), .PKT_ADDR_SIDEBAND_L (78), .ST_DATA_W (100), .ST_CHANNEL_W (13), .AV_BURSTCOUNT_W (3), .SUPPRESS_0_BYTEEN_RSP (0), .ID (0), .BURSTWRAP_VALUE (3), .CACHE_VALUE (4'b0000) ) nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent ( .clk (altpll_0_c1_clk), // clk.clk .reset (rst_controller_reset_out_reset), // clk_reset.reset .av_address (nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_address), // av.address .av_write (nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_write), // .write .av_read (nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_read), // .read .av_writedata (nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_writedata), // .writedata .av_readdata (nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_readdata), // .readdata .av_waitrequest (nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest .av_readdatavalid (nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid .av_byteenable (nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_byteenable), // .byteenable .av_burstcount (nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_burstcount), // .burstcount .av_debugaccess (nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess .av_lock (nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_lock), // .lock .cp_valid (nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent_cp_valid), // cp.valid .cp_data (nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent_cp_data), // .data .cp_startofpacket (nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent_cp_startofpacket), // .startofpacket .cp_endofpacket (nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent_cp_endofpacket), // .endofpacket .cp_ready (nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent_cp_ready), // .ready .rp_valid (limiter_rsp_src_valid), // rp.valid .rp_data (limiter_rsp_src_data), // .data .rp_channel (limiter_rsp_src_channel), // .channel .rp_startofpacket (limiter_rsp_src_startofpacket), // .startofpacket .rp_endofpacket (limiter_rsp_src_endofpacket), // .endofpacket .rp_ready (limiter_rsp_src_ready) // .ready ); altera_merlin_master_agent #( .PKT_PROTECTION_H (93), .PKT_PROTECTION_L (91), .PKT_BEGIN_BURST (80), .PKT_BURSTWRAP_H (72), .PKT_BURSTWRAP_L (70), .PKT_BURST_SIZE_H (75), .PKT_BURST_SIZE_L (73), .PKT_BURST_TYPE_H (77), .PKT_BURST_TYPE_L (76), .PKT_BYTE_CNT_H (69), .PKT_BYTE_CNT_L (67), .PKT_ADDR_H (60), .PKT_ADDR_L (36), .PKT_TRANS_COMPRESSED_READ (61), .PKT_TRANS_POSTED (62), .PKT_TRANS_WRITE (63), .PKT_TRANS_READ (64), .PKT_TRANS_LOCK (65), .PKT_TRANS_EXCLUSIVE (66), .PKT_DATA_H (31), .PKT_DATA_L (0), .PKT_BYTEEN_H (35), .PKT_BYTEEN_L (32), .PKT_SRC_ID_H (85), .PKT_SRC_ID_L (82), .PKT_DEST_ID_H (89), .PKT_DEST_ID_L (86), .PKT_THREAD_ID_H (90), .PKT_THREAD_ID_L (90), .PKT_CACHE_H (97), .PKT_CACHE_L (94), .PKT_DATA_SIDEBAND_H (79), .PKT_DATA_SIDEBAND_L (79), .PKT_QOS_H (81), .PKT_QOS_L (81), .PKT_ADDR_SIDEBAND_H (78), .PKT_ADDR_SIDEBAND_L (78), .ST_DATA_W (100), .ST_CHANNEL_W (13), .AV_BURSTCOUNT_W (3), .SUPPRESS_0_BYTEEN_RSP (0), .ID (1), .BURSTWRAP_VALUE (7), .CACHE_VALUE (4'b0000) ) nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent ( .clk (altpll_0_c1_clk), // clk.clk .reset (rst_controller_reset_out_reset), // clk_reset.reset .av_address (nios2_qsys_0_data_master_translator_avalon_universal_master_0_address), // av.address .av_write (nios2_qsys_0_data_master_translator_avalon_universal_master_0_write), // .write .av_read (nios2_qsys_0_data_master_translator_avalon_universal_master_0_read), // .read .av_writedata (nios2_qsys_0_data_master_translator_avalon_universal_master_0_writedata), // .writedata .av_readdata (nios2_qsys_0_data_master_translator_avalon_universal_master_0_readdata), // .readdata .av_waitrequest (nios2_qsys_0_data_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest .av_readdatavalid (nios2_qsys_0_data_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid .av_byteenable (nios2_qsys_0_data_master_translator_avalon_universal_master_0_byteenable), // .byteenable .av_burstcount (nios2_qsys_0_data_master_translator_avalon_universal_master_0_burstcount), // .burstcount .av_debugaccess (nios2_qsys_0_data_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess .av_lock (nios2_qsys_0_data_master_translator_avalon_universal_master_0_lock), // .lock .cp_valid (nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent_cp_valid), // cp.valid .cp_data (nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent_cp_data), // .data .cp_startofpacket (nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent_cp_startofpacket), // .startofpacket .cp_endofpacket (nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent_cp_endofpacket), // .endofpacket .cp_ready (nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent_cp_ready), // .ready .rp_valid (limiter_001_rsp_src_valid), // rp.valid .rp_data (limiter_001_rsp_src_data), // .data .rp_channel (limiter_001_rsp_src_channel), // .channel .rp_startofpacket (limiter_001_rsp_src_startofpacket), // .startofpacket .rp_endofpacket (limiter_001_rsp_src_endofpacket), // .endofpacket .rp_ready (limiter_001_rsp_src_ready) // .ready ); altera_merlin_slave_agent #( .PKT_DATA_H (31), .PKT_DATA_L (0), .PKT_BEGIN_BURST (80), .PKT_SYMBOL_W (8), .PKT_BYTEEN_H (35), .PKT_BYTEEN_L (32), .PKT_ADDR_H (60), .PKT_ADDR_L (36), .PKT_TRANS_COMPRESSED_READ (61), .PKT_TRANS_POSTED (62), .PKT_TRANS_WRITE (63), .PKT_TRANS_READ (64), .PKT_TRANS_LOCK (65), .PKT_SRC_ID_H (85), .PKT_SRC_ID_L (82), .PKT_DEST_ID_H (89), .PKT_DEST_ID_L (86), .PKT_BURSTWRAP_H (72), .PKT_BURSTWRAP_L (70), .PKT_BYTE_CNT_H (69), .PKT_BYTE_CNT_L (67), .PKT_PROTECTION_H (93), .PKT_PROTECTION_L (91), .PKT_RESPONSE_STATUS_H (99), .PKT_RESPONSE_STATUS_L (98), .PKT_BURST_SIZE_H (75), .PKT_BURST_SIZE_L (73), .ST_CHANNEL_W (13), .ST_DATA_W (100), .AVS_BURSTCOUNT_W (3), .SUPPRESS_0_BYTEEN_CMD (0), .PREVENT_FIFO_OVERFLOW (1) ) nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent ( .clk (altpll_0_c1_clk), // clk.clk .reset (rst_controller_reset_out_reset), // clk_reset.reset .m0_address (nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_address), // m0.address .m0_burstcount (nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount .m0_byteenable (nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable .m0_debugaccess (nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess .m0_lock (nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_lock), // .lock .m0_readdata (nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata .m0_readdatavalid (nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid .m0_read (nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_read), // .read .m0_waitrequest (nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest .m0_writedata (nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata .m0_write (nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_write), // .write .rp_endofpacket (nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_endofpacket), // rp.endofpacket .rp_ready (nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_ready), // .ready .rp_valid (nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_valid), // .valid .rp_data (nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_data), // .data .rp_startofpacket (nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket .cp_ready (cmd_xbar_mux_src_ready), // cp.ready .cp_valid (cmd_xbar_mux_src_valid), // .valid .cp_data (cmd_xbar_mux_src_data), // .data .cp_startofpacket (cmd_xbar_mux_src_startofpacket), // .startofpacket .cp_endofpacket (cmd_xbar_mux_src_endofpacket), // .endofpacket .cp_channel (cmd_xbar_mux_src_channel), // .channel .rf_sink_ready (nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // rf_sink.ready .rf_sink_valid (nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid .rf_sink_startofpacket (nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket .rf_sink_endofpacket (nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket .rf_sink_data (nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // .data .rf_source_ready (nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_ready), // rf_source.ready .rf_source_valid (nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid .rf_source_startofpacket (nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket .rf_source_endofpacket (nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket .rf_source_data (nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_data), // .data .rdata_fifo_sink_ready (nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready .rdata_fifo_sink_valid (nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid .rdata_fifo_sink_data (nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data .rdata_fifo_src_ready (nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready .rdata_fifo_src_valid (nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid .rdata_fifo_src_data (nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data) // .data ); altera_avalon_sc_fifo #( .SYMBOLS_PER_BEAT (1), .BITS_PER_SYMBOL (101), .FIFO_DEPTH (2), .CHANNEL_WIDTH (0), .ERROR_WIDTH (0), .USE_PACKETS (1), .USE_FILL_LEVEL (0), .EMPTY_LATENCY (1), .USE_MEMORY_BLOCKS (0), .USE_STORE_FORWARD (0), .USE_ALMOST_FULL_IF (0), .USE_ALMOST_EMPTY_IF (0) ) nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo ( .clk (altpll_0_c1_clk), // clk.clk .reset (rst_controller_reset_out_reset), // clk_reset.reset .in_data (nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_data), // in.data .in_valid (nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid .in_ready (nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_ready), // .ready .in_startofpacket (nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket .in_endofpacket (nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket .out_data (nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // out.data .out_valid (nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid .out_ready (nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // .ready .out_startofpacket (nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket .out_endofpacket (nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket .csr_address (2'b00), // (terminated) .csr_read (1'b0), // (terminated) .csr_write (1'b0), // (terminated) .csr_readdata (), // (terminated) .csr_writedata (32'b00000000000000000000000000000000), // (terminated) .almost_full_data (), // (terminated) .almost_empty_data (), // (terminated) .in_empty (1'b0), // (terminated) .out_empty (), // (terminated) .in_error (1'b0), // (terminated) .out_error (), // (terminated) .in_channel (1'b0), // (terminated) .out_channel () // (terminated) ); altera_merlin_slave_agent #( .PKT_DATA_H (31), .PKT_DATA_L (0), .PKT_BEGIN_BURST (80), .PKT_SYMBOL_W (8), .PKT_BYTEEN_H (35), .PKT_BYTEEN_L (32), .PKT_ADDR_H (60), .PKT_ADDR_L (36), .PKT_TRANS_COMPRESSED_READ (61), .PKT_TRANS_POSTED (62), .PKT_TRANS_WRITE (63), .PKT_TRANS_READ (64), .PKT_TRANS_LOCK (65), .PKT_SRC_ID_H (85), .PKT_SRC_ID_L (82), .PKT_DEST_ID_H (89), .PKT_DEST_ID_L (86), .PKT_BURSTWRAP_H (72), .PKT_BURSTWRAP_L (70), .PKT_BYTE_CNT_H (69), .PKT_BYTE_CNT_L (67), .PKT_PROTECTION_H (93), .PKT_PROTECTION_L (91), .PKT_RESPONSE_STATUS_H (99), .PKT_RESPONSE_STATUS_L (98), .PKT_BURST_SIZE_H (75), .PKT_BURST_SIZE_L (73), .ST_CHANNEL_W (13), .ST_DATA_W (100), .AVS_BURSTCOUNT_W (3), .SUPPRESS_0_BYTEEN_CMD (0), .PREVENT_FIFO_OVERFLOW (1) ) onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent ( .clk (altpll_0_c1_clk), // clk.clk .reset (rst_controller_reset_out_reset), // clk_reset.reset .m0_address (onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_address), // m0.address .m0_burstcount (onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount .m0_byteenable (onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable .m0_debugaccess (onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess .m0_lock (onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_lock), // .lock .m0_readdata (onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata .m0_readdatavalid (onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid .m0_read (onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_read), // .read .m0_waitrequest (onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest .m0_writedata (onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata .m0_write (onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_write), // .write .rp_endofpacket (onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket), // rp.endofpacket .rp_ready (onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rp_ready), // .ready .rp_valid (onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rp_valid), // .valid .rp_data (onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rp_data), // .data .rp_startofpacket (onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket .cp_ready (cmd_xbar_mux_001_src_ready), // cp.ready .cp_valid (cmd_xbar_mux_001_src_valid), // .valid .cp_data (cmd_xbar_mux_001_src_data), // .data .cp_startofpacket (cmd_xbar_mux_001_src_startofpacket), // .startofpacket .cp_endofpacket (cmd_xbar_mux_001_src_endofpacket), // .endofpacket .cp_channel (cmd_xbar_mux_001_src_channel), // .channel .rf_sink_ready (onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // rf_sink.ready .rf_sink_valid (onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid .rf_sink_startofpacket (onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket .rf_sink_endofpacket (onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket .rf_sink_data (onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // .data .rf_source_ready (onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rf_source_ready), // rf_source.ready .rf_source_valid (onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid .rf_source_startofpacket (onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket .rf_source_endofpacket (onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket .rf_source_data (onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rf_source_data), // .data .rdata_fifo_sink_ready (onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready .rdata_fifo_sink_valid (onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid .rdata_fifo_sink_data (onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data .rdata_fifo_src_ready (onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready .rdata_fifo_src_valid (onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid .rdata_fifo_src_data (onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data) // .data ); altera_avalon_sc_fifo #( .SYMBOLS_PER_BEAT (1), .BITS_PER_SYMBOL (101), .FIFO_DEPTH (2), .CHANNEL_WIDTH (0), .ERROR_WIDTH (0), .USE_PACKETS (1), .USE_FILL_LEVEL (0), .EMPTY_LATENCY (1), .USE_MEMORY_BLOCKS (0), .USE_STORE_FORWARD (0), .USE_ALMOST_FULL_IF (0), .USE_ALMOST_EMPTY_IF (0) ) onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ( .clk (altpll_0_c1_clk), // clk.clk .reset (rst_controller_reset_out_reset), // clk_reset.reset .in_data (onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rf_source_data), // in.data .in_valid (onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid .in_ready (onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rf_source_ready), // .ready .in_startofpacket (onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket .in_endofpacket (onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket .out_data (onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // out.data .out_valid (onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid .out_ready (onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // .ready .out_startofpacket (onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket .out_endofpacket (onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket .csr_address (2'b00), // (terminated) .csr_read (1'b0), // (terminated) .csr_write (1'b0), // (terminated) .csr_readdata (), // (terminated) .csr_writedata (32'b00000000000000000000000000000000), // (terminated) .almost_full_data (), // (terminated) .almost_empty_data (), // (terminated) .in_empty (1'b0), // (terminated) .out_empty (), // (terminated) .in_error (1'b0), // (terminated) .out_error (), // (terminated) .in_channel (1'b0), // (terminated) .out_channel () // (terminated) ); altera_merlin_slave_agent #( .PKT_DATA_H (15), .PKT_DATA_L (0), .PKT_BEGIN_BURST (62), .PKT_SYMBOL_W (8), .PKT_BYTEEN_H (17), .PKT_BYTEEN_L (16), .PKT_ADDR_H (42), .PKT_ADDR_L (18), .PKT_TRANS_COMPRESSED_READ (43), .PKT_TRANS_POSTED (44), .PKT_TRANS_WRITE (45), .PKT_TRANS_READ (46), .PKT_TRANS_LOCK (47), .PKT_SRC_ID_H (67), .PKT_SRC_ID_L (64), .PKT_DEST_ID_H (71), .PKT_DEST_ID_L (68), .PKT_BURSTWRAP_H (54), .PKT_BURSTWRAP_L (52), .PKT_BYTE_CNT_H (51), .PKT_BYTE_CNT_L (49), .PKT_PROTECTION_H (75), .PKT_PROTECTION_L (73), .PKT_RESPONSE_STATUS_H (81), .PKT_RESPONSE_STATUS_L (80), .PKT_BURST_SIZE_H (57), .PKT_BURST_SIZE_L (55), .ST_CHANNEL_W (13), .ST_DATA_W (82), .AVS_BURSTCOUNT_W (2), .SUPPRESS_0_BYTEEN_CMD (1), .PREVENT_FIFO_OVERFLOW (1) ) sdram_0_s1_translator_avalon_universal_slave_0_agent ( .clk (altpll_0_c1_clk), // clk.clk .reset (rst_controller_reset_out_reset), // clk_reset.reset .m0_address (sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_address), // m0.address .m0_burstcount (sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount .m0_byteenable (sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable .m0_debugaccess (sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess .m0_lock (sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_lock), // .lock .m0_readdata (sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata .m0_readdatavalid (sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid .m0_read (sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_read), // .read .m0_waitrequest (sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest .m0_writedata (sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata .m0_write (sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_write), // .write .rp_endofpacket (sdram_0_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket), // rp.endofpacket .rp_ready (sdram_0_s1_translator_avalon_universal_slave_0_agent_rp_ready), // .ready .rp_valid (sdram_0_s1_translator_avalon_universal_slave_0_agent_rp_valid), // .valid .rp_data (sdram_0_s1_translator_avalon_universal_slave_0_agent_rp_data), // .data .rp_startofpacket (sdram_0_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket .cp_ready (burst_adapter_source0_ready), // cp.ready .cp_valid (burst_adapter_source0_valid), // .valid .cp_data (burst_adapter_source0_data), // .data .cp_startofpacket (burst_adapter_source0_startofpacket), // .startofpacket .cp_endofpacket (burst_adapter_source0_endofpacket), // .endofpacket .cp_channel (burst_adapter_source0_channel), // .channel .rf_sink_ready (sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // rf_sink.ready .rf_sink_valid (sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid .rf_sink_startofpacket (sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket .rf_sink_endofpacket (sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket .rf_sink_data (sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // .data .rf_source_ready (sdram_0_s1_translator_avalon_universal_slave_0_agent_rf_source_ready), // rf_source.ready .rf_source_valid (sdram_0_s1_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid .rf_source_startofpacket (sdram_0_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket .rf_source_endofpacket (sdram_0_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket .rf_source_data (sdram_0_s1_translator_avalon_universal_slave_0_agent_rf_source_data), // .data .rdata_fifo_sink_ready (sdram_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready .rdata_fifo_sink_valid (sdram_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid .rdata_fifo_sink_data (sdram_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data .rdata_fifo_src_ready (sdram_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready .rdata_fifo_src_valid (sdram_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid .rdata_fifo_src_data (sdram_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data) // .data ); altera_avalon_sc_fifo #( .SYMBOLS_PER_BEAT (1), .BITS_PER_SYMBOL (83), .FIFO_DEPTH (8), .CHANNEL_WIDTH (0), .ERROR_WIDTH (0), .USE_PACKETS (1), .USE_FILL_LEVEL (0), .EMPTY_LATENCY (1), .USE_MEMORY_BLOCKS (0), .USE_STORE_FORWARD (0), .USE_ALMOST_FULL_IF (0), .USE_ALMOST_EMPTY_IF (0) ) sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ( .clk (altpll_0_c1_clk), // clk.clk .reset (rst_controller_reset_out_reset), // clk_reset.reset .in_data (sdram_0_s1_translator_avalon_universal_slave_0_agent_rf_source_data), // in.data .in_valid (sdram_0_s1_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid .in_ready (sdram_0_s1_translator_avalon_universal_slave_0_agent_rf_source_ready), // .ready .in_startofpacket (sdram_0_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket .in_endofpacket (sdram_0_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket .out_data (sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // out.data .out_valid (sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid .out_ready (sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // .ready .out_startofpacket (sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket .out_endofpacket (sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket .csr_address (2'b00), // (terminated) .csr_read (1'b0), // (terminated) .csr_write (1'b0), // (terminated) .csr_readdata (), // (terminated) .csr_writedata (32'b00000000000000000000000000000000), // (terminated) .almost_full_data (), // (terminated) .almost_empty_data (), // (terminated) .in_empty (1'b0), // (terminated) .out_empty (), // (terminated) .in_error (1'b0), // (terminated) .out_error (), // (terminated) .in_channel (1'b0), // (terminated) .out_channel () // (terminated) ); altera_merlin_slave_agent #( .PKT_DATA_H (15), .PKT_DATA_L (0), .PKT_BEGIN_BURST (62), .PKT_SYMBOL_W (8), .PKT_BYTEEN_H (17), .PKT_BYTEEN_L (16), .PKT_ADDR_H (42), .PKT_ADDR_L (18), .PKT_TRANS_COMPRESSED_READ (43), .PKT_TRANS_POSTED (44), .PKT_TRANS_WRITE (45), .PKT_TRANS_READ (46), .PKT_TRANS_LOCK (47), .PKT_SRC_ID_H (67), .PKT_SRC_ID_L (64), .PKT_DEST_ID_H (71), .PKT_DEST_ID_L (68), .PKT_BURSTWRAP_H (54), .PKT_BURSTWRAP_L (52), .PKT_BYTE_CNT_H (51), .PKT_BYTE_CNT_L (49), .PKT_PROTECTION_H (75), .PKT_PROTECTION_L (73), .PKT_RESPONSE_STATUS_H (81), .PKT_RESPONSE_STATUS_L (80), .PKT_BURST_SIZE_H (57), .PKT_BURST_SIZE_L (55), .ST_CHANNEL_W (13), .ST_DATA_W (82), .AVS_BURSTCOUNT_W (2), .SUPPRESS_0_BYTEEN_CMD (1), .PREVENT_FIFO_OVERFLOW (1) ) sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent ( .clk (altpll_0_c1_clk), // clk.clk .reset (rst_controller_reset_out_reset), // clk_reset.reset .m0_address (sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_address), // m0.address .m0_burstcount (sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount .m0_byteenable (sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable .m0_debugaccess (sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess .m0_lock (sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_lock), // .lock .m0_readdata (sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata .m0_readdatavalid (sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid .m0_read (sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_read), // .read .m0_waitrequest (sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest .m0_writedata (sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata .m0_write (sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_write), // .write .rp_endofpacket (sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket), // rp.endofpacket .rp_ready (sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rp_ready), // .ready .rp_valid (sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rp_valid), // .valid .rp_data (sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rp_data), // .data .rp_startofpacket (sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket .cp_ready (burst_adapter_001_source0_ready), // cp.ready .cp_valid (burst_adapter_001_source0_valid), // .valid .cp_data (burst_adapter_001_source0_data), // .data .cp_startofpacket (burst_adapter_001_source0_startofpacket), // .startofpacket .cp_endofpacket (burst_adapter_001_source0_endofpacket), // .endofpacket .cp_channel (burst_adapter_001_source0_channel), // .channel .rf_sink_ready (sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // rf_sink.ready .rf_sink_valid (sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid .rf_sink_startofpacket (sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket .rf_sink_endofpacket (sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket .rf_sink_data (sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // .data .rf_source_ready (sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rf_source_ready), // rf_source.ready .rf_source_valid (sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid .rf_source_startofpacket (sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket .rf_source_endofpacket (sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket .rf_source_data (sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rf_source_data), // .data .rdata_fifo_sink_ready (sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready .rdata_fifo_sink_valid (sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid .rdata_fifo_sink_data (sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data .rdata_fifo_src_ready (sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready .rdata_fifo_src_valid (sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid .rdata_fifo_src_data (sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data) // .data ); altera_avalon_sc_fifo #( .SYMBOLS_PER_BEAT (1), .BITS_PER_SYMBOL (83), .FIFO_DEPTH (3), .CHANNEL_WIDTH (0), .ERROR_WIDTH (0), .USE_PACKETS (1), .USE_FILL_LEVEL (0), .EMPTY_LATENCY (1), .USE_MEMORY_BLOCKS (0), .USE_STORE_FORWARD (0), .USE_ALMOST_FULL_IF (0), .USE_ALMOST_EMPTY_IF (0) ) sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo ( .clk (altpll_0_c1_clk), // clk.clk .reset (rst_controller_reset_out_reset), // clk_reset.reset .in_data (sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rf_source_data), // in.data .in_valid (sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid .in_ready (sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rf_source_ready), // .ready .in_startofpacket (sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket .in_endofpacket (sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket .out_data (sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // out.data .out_valid (sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid .out_ready (sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // .ready .out_startofpacket (sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket .out_endofpacket (sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket .csr_address (2'b00), // (terminated) .csr_read (1'b0), // (terminated) .csr_write (1'b0), // (terminated) .csr_readdata (), // (terminated) .csr_writedata (32'b00000000000000000000000000000000), // (terminated) .almost_full_data (), // (terminated) .almost_empty_data (), // (terminated) .in_empty (1'b0), // (terminated) .out_empty (), // (terminated) .in_error (1'b0), // (terminated) .out_error (), // (terminated) .in_channel (1'b0), // (terminated) .out_channel () // (terminated) ); altera_merlin_slave_agent #( .PKT_DATA_H (31), .PKT_DATA_L (0), .PKT_BEGIN_BURST (80), .PKT_SYMBOL_W (8), .PKT_BYTEEN_H (35), .PKT_BYTEEN_L (32), .PKT_ADDR_H (60), .PKT_ADDR_L (36), .PKT_TRANS_COMPRESSED_READ (61), .PKT_TRANS_POSTED (62), .PKT_TRANS_WRITE (63), .PKT_TRANS_READ (64), .PKT_TRANS_LOCK (65), .PKT_SRC_ID_H (85), .PKT_SRC_ID_L (82), .PKT_DEST_ID_H (89), .PKT_DEST_ID_L (86), .PKT_BURSTWRAP_H (72), .PKT_BURSTWRAP_L (70), .PKT_BYTE_CNT_H (69), .PKT_BYTE_CNT_L (67), .PKT_PROTECTION_H (93), .PKT_PROTECTION_L (91), .PKT_RESPONSE_STATUS_H (99), .PKT_RESPONSE_STATUS_L (98), .PKT_BURST_SIZE_H (75), .PKT_BURST_SIZE_L (73), .ST_CHANNEL_W (13), .ST_DATA_W (100), .AVS_BURSTCOUNT_W (3), .SUPPRESS_0_BYTEEN_CMD (0), .PREVENT_FIFO_OVERFLOW (1) ) altpll_0_pll_slave_translator_avalon_universal_slave_0_agent ( .clk (clk_clk), // clk.clk .reset (rst_controller_001_reset_out_reset), // clk_reset.reset .m0_address (altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_m0_address), // m0.address .m0_burstcount (altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount .m0_byteenable (altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable .m0_debugaccess (altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess .m0_lock (altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_m0_lock), // .lock .m0_readdata (altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata .m0_readdatavalid (altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid .m0_read (altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_m0_read), // .read .m0_waitrequest (altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest .m0_writedata (altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata .m0_write (altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_m0_write), // .write .rp_endofpacket (altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket), // rp.endofpacket .rp_ready (altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rp_ready), // .ready .rp_valid (altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rp_valid), // .valid .rp_data (altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rp_data), // .data .rp_startofpacket (altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket .cp_ready (crosser_out_ready), // cp.ready .cp_valid (crosser_out_valid), // .valid .cp_data (crosser_out_data), // .data .cp_startofpacket (crosser_out_startofpacket), // .startofpacket .cp_endofpacket (crosser_out_endofpacket), // .endofpacket .cp_channel (crosser_out_channel), // .channel .rf_sink_ready (altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // rf_sink.ready .rf_sink_valid (altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid .rf_sink_startofpacket (altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket .rf_sink_endofpacket (altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket .rf_sink_data (altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // .data .rf_source_ready (altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rf_source_ready), // rf_source.ready .rf_source_valid (altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid .rf_source_startofpacket (altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket .rf_source_endofpacket (altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket .rf_source_data (altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rf_source_data), // .data .rdata_fifo_sink_ready (altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_out_ready), // rdata_fifo_sink.ready .rdata_fifo_sink_valid (altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_out_valid), // .valid .rdata_fifo_sink_data (altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_out_data), // .data .rdata_fifo_src_ready (altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready .rdata_fifo_src_valid (altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid .rdata_fifo_src_data (altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data) // .data ); altera_avalon_sc_fifo #( .SYMBOLS_PER_BEAT (1), .BITS_PER_SYMBOL (101), .FIFO_DEPTH (2), .CHANNEL_WIDTH (0), .ERROR_WIDTH (0), .USE_PACKETS (1), .USE_FILL_LEVEL (0), .EMPTY_LATENCY (1), .USE_MEMORY_BLOCKS (0), .USE_STORE_FORWARD (0), .USE_ALMOST_FULL_IF (0), .USE_ALMOST_EMPTY_IF (0) ) altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rsp_fifo ( .clk (clk_clk), // clk.clk .reset (rst_controller_001_reset_out_reset), // clk_reset.reset .in_data (altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rf_source_data), // in.data .in_valid (altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid .in_ready (altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rf_source_ready), // .ready .in_startofpacket (altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket .in_endofpacket (altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket .out_data (altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // out.data .out_valid (altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid .out_ready (altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // .ready .out_startofpacket (altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket .out_endofpacket (altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket .csr_address (2'b00), // (terminated) .csr_read (1'b0), // (terminated) .csr_write (1'b0), // (terminated) .csr_readdata (), // (terminated) .csr_writedata (32'b00000000000000000000000000000000), // (terminated) .almost_full_data (), // (terminated) .almost_empty_data (), // (terminated) .in_empty (1'b0), // (terminated) .out_empty (), // (terminated) .in_error (1'b0), // (terminated) .out_error (), // (terminated) .in_channel (1'b0), // (terminated) .out_channel () // (terminated) ); altera_avalon_sc_fifo #( .SYMBOLS_PER_BEAT (1), .BITS_PER_SYMBOL (32), .FIFO_DEPTH (2), .CHANNEL_WIDTH (0), .ERROR_WIDTH (0), .USE_PACKETS (0), .USE_FILL_LEVEL (0), .EMPTY_LATENCY (0), .USE_MEMORY_BLOCKS (0), .USE_STORE_FORWARD (0), .USE_ALMOST_FULL_IF (0), .USE_ALMOST_EMPTY_IF (0) ) altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo ( .clk (clk_clk), // clk.clk .reset (rst_controller_001_reset_out_reset), // clk_reset.reset .in_data (altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // in.data .in_valid (altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid .in_ready (altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // .ready .out_data (altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_out_data), // out.data .out_valid (altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_out_valid), // .valid .out_ready (altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_out_ready), // .ready .csr_address (2'b00), // (terminated) .csr_read (1'b0), // (terminated) .csr_write (1'b0), // (terminated) .csr_readdata (), // (terminated) .csr_writedata (32'b00000000000000000000000000000000), // (terminated) .almost_full_data (), // (terminated) .almost_empty_data (), // (terminated) .in_startofpacket (1'b0), // (terminated) .in_endofpacket (1'b0), // (terminated) .out_startofpacket (), // (terminated) .out_endofpacket (), // (terminated) .in_empty (1'b0), // (terminated) .out_empty (), // (terminated) .in_error (1'b0), // (terminated) .out_error (), // (terminated) .in_channel (1'b0), // (terminated) .out_channel () // (terminated) ); altera_merlin_slave_agent #( .PKT_DATA_H (31), .PKT_DATA_L (0), .PKT_BEGIN_BURST (80), .PKT_SYMBOL_W (8), .PKT_BYTEEN_H (35), .PKT_BYTEEN_L (32), .PKT_ADDR_H (60), .PKT_ADDR_L (36), .PKT_TRANS_COMPRESSED_READ (61), .PKT_TRANS_POSTED (62), .PKT_TRANS_WRITE (63), .PKT_TRANS_READ (64), .PKT_TRANS_LOCK (65), .PKT_SRC_ID_H (85), .PKT_SRC_ID_L (82), .PKT_DEST_ID_H (89), .PKT_DEST_ID_L (86), .PKT_BURSTWRAP_H (72), .PKT_BURSTWRAP_L (70), .PKT_BYTE_CNT_H (69), .PKT_BYTE_CNT_L (67), .PKT_PROTECTION_H (93), .PKT_PROTECTION_L (91), .PKT_RESPONSE_STATUS_H (99), .PKT_RESPONSE_STATUS_L (98), .PKT_BURST_SIZE_H (75), .PKT_BURST_SIZE_L (73), .ST_CHANNEL_W (13), .ST_DATA_W (100), .AVS_BURSTCOUNT_W (3), .SUPPRESS_0_BYTEEN_CMD (0), .PREVENT_FIFO_OVERFLOW (1) ) sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent ( .clk (altpll_0_c1_clk), // clk.clk .reset (rst_controller_reset_out_reset), // clk_reset.reset .m0_address (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_address), // m0.address .m0_burstcount (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount .m0_byteenable (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable .m0_debugaccess (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess .m0_lock (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_lock), // .lock .m0_readdata (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata .m0_readdatavalid (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid .m0_read (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_read), // .read .m0_waitrequest (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest .m0_writedata (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata .m0_write (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_write), // .write .rp_endofpacket (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket), // rp.endofpacket .rp_ready (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rp_ready), // .ready .rp_valid (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rp_valid), // .valid .rp_data (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rp_data), // .data .rp_startofpacket (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket .cp_ready (cmd_xbar_demux_001_src5_ready), // cp.ready .cp_valid (cmd_xbar_demux_001_src5_valid), // .valid .cp_data (cmd_xbar_demux_001_src5_data), // .data .cp_startofpacket (cmd_xbar_demux_001_src5_startofpacket), // .startofpacket .cp_endofpacket (cmd_xbar_demux_001_src5_endofpacket), // .endofpacket .cp_channel (cmd_xbar_demux_001_src5_channel), // .channel .rf_sink_ready (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // rf_sink.ready .rf_sink_valid (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid .rf_sink_startofpacket (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket .rf_sink_endofpacket (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket .rf_sink_data (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // .data .rf_source_ready (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rf_source_ready), // rf_source.ready .rf_source_valid (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid .rf_source_startofpacket (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket .rf_source_endofpacket (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket .rf_source_data (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rf_source_data), // .data .rdata_fifo_sink_ready (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready .rdata_fifo_sink_valid (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid .rdata_fifo_sink_data (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data .rdata_fifo_src_ready (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready .rdata_fifo_src_valid (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid .rdata_fifo_src_data (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data) // .data ); altera_avalon_sc_fifo #( .SYMBOLS_PER_BEAT (1), .BITS_PER_SYMBOL (101), .FIFO_DEPTH (2), .CHANNEL_WIDTH (0), .ERROR_WIDTH (0), .USE_PACKETS (1), .USE_FILL_LEVEL (0), .EMPTY_LATENCY (1), .USE_MEMORY_BLOCKS (0), .USE_STORE_FORWARD (0), .USE_ALMOST_FULL_IF (0), .USE_ALMOST_EMPTY_IF (0) ) sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo ( .clk (altpll_0_c1_clk), // clk.clk .reset (rst_controller_reset_out_reset), // clk_reset.reset .in_data (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rf_source_data), // in.data .in_valid (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid .in_ready (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rf_source_ready), // .ready .in_startofpacket (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket .in_endofpacket (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket .out_data (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // out.data .out_valid (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid .out_ready (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // .ready .out_startofpacket (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket .out_endofpacket (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket .csr_address (2'b00), // (terminated) .csr_read (1'b0), // (terminated) .csr_write (1'b0), // (terminated) .csr_readdata (), // (terminated) .csr_writedata (32'b00000000000000000000000000000000), // (terminated) .almost_full_data (), // (terminated) .almost_empty_data (), // (terminated) .in_empty (1'b0), // (terminated) .out_empty (), // (terminated) .in_error (1'b0), // (terminated) .out_error (), // (terminated) .in_channel (1'b0), // (terminated) .out_channel () // (terminated) ); altera_merlin_slave_agent #( .PKT_DATA_H (31), .PKT_DATA_L (0), .PKT_BEGIN_BURST (80), .PKT_SYMBOL_W (8), .PKT_BYTEEN_H (35), .PKT_BYTEEN_L (32), .PKT_ADDR_H (60), .PKT_ADDR_L (36), .PKT_TRANS_COMPRESSED_READ (61), .PKT_TRANS_POSTED (62), .PKT_TRANS_WRITE (63), .PKT_TRANS_READ (64), .PKT_TRANS_LOCK (65), .PKT_SRC_ID_H (85), .PKT_SRC_ID_L (82), .PKT_DEST_ID_H (89), .PKT_DEST_ID_L (86), .PKT_BURSTWRAP_H (72), .PKT_BURSTWRAP_L (70), .PKT_BYTE_CNT_H (69), .PKT_BYTE_CNT_L (67), .PKT_PROTECTION_H (93), .PKT_PROTECTION_L (91), .PKT_RESPONSE_STATUS_H (99), .PKT_RESPONSE_STATUS_L (98), .PKT_BURST_SIZE_H (75), .PKT_BURST_SIZE_L (73), .ST_CHANNEL_W (13), .ST_DATA_W (100), .AVS_BURSTCOUNT_W (3), .SUPPRESS_0_BYTEEN_CMD (0), .PREVENT_FIFO_OVERFLOW (1) ) timer_0_s1_translator_avalon_universal_slave_0_agent ( .clk (altpll_0_c1_clk), // clk.clk .reset (rst_controller_reset_out_reset), // clk_reset.reset .m0_address (timer_0_s1_translator_avalon_universal_slave_0_agent_m0_address), // m0.address .m0_burstcount (timer_0_s1_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount .m0_byteenable (timer_0_s1_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable .m0_debugaccess (timer_0_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess .m0_lock (timer_0_s1_translator_avalon_universal_slave_0_agent_m0_lock), // .lock .m0_readdata (timer_0_s1_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata .m0_readdatavalid (timer_0_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid .m0_read (timer_0_s1_translator_avalon_universal_slave_0_agent_m0_read), // .read .m0_waitrequest (timer_0_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest .m0_writedata (timer_0_s1_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata .m0_write (timer_0_s1_translator_avalon_universal_slave_0_agent_m0_write), // .write .rp_endofpacket (timer_0_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket), // rp.endofpacket .rp_ready (timer_0_s1_translator_avalon_universal_slave_0_agent_rp_ready), // .ready .rp_valid (timer_0_s1_translator_avalon_universal_slave_0_agent_rp_valid), // .valid .rp_data (timer_0_s1_translator_avalon_universal_slave_0_agent_rp_data), // .data .rp_startofpacket (timer_0_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket .cp_ready (cmd_xbar_demux_001_src6_ready), // cp.ready .cp_valid (cmd_xbar_demux_001_src6_valid), // .valid .cp_data (cmd_xbar_demux_001_src6_data), // .data .cp_startofpacket (cmd_xbar_demux_001_src6_startofpacket), // .startofpacket .cp_endofpacket (cmd_xbar_demux_001_src6_endofpacket), // .endofpacket .cp_channel (cmd_xbar_demux_001_src6_channel), // .channel .rf_sink_ready (timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // rf_sink.ready .rf_sink_valid (timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid .rf_sink_startofpacket (timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket .rf_sink_endofpacket (timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket .rf_sink_data (timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // .data .rf_source_ready (timer_0_s1_translator_avalon_universal_slave_0_agent_rf_source_ready), // rf_source.ready .rf_source_valid (timer_0_s1_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid .rf_source_startofpacket (timer_0_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket .rf_source_endofpacket (timer_0_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket .rf_source_data (timer_0_s1_translator_avalon_universal_slave_0_agent_rf_source_data), // .data .rdata_fifo_sink_ready (timer_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready .rdata_fifo_sink_valid (timer_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid .rdata_fifo_sink_data (timer_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data .rdata_fifo_src_ready (timer_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready .rdata_fifo_src_valid (timer_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid .rdata_fifo_src_data (timer_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data) // .data ); altera_avalon_sc_fifo #( .SYMBOLS_PER_BEAT (1), .BITS_PER_SYMBOL (101), .FIFO_DEPTH (2), .CHANNEL_WIDTH (0), .ERROR_WIDTH (0), .USE_PACKETS (1), .USE_FILL_LEVEL (0), .EMPTY_LATENCY (1), .USE_MEMORY_BLOCKS (0), .USE_STORE_FORWARD (0), .USE_ALMOST_FULL_IF (0), .USE_ALMOST_EMPTY_IF (0) ) timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ( .clk (altpll_0_c1_clk), // clk.clk .reset (rst_controller_reset_out_reset), // clk_reset.reset .in_data (timer_0_s1_translator_avalon_universal_slave_0_agent_rf_source_data), // in.data .in_valid (timer_0_s1_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid .in_ready (timer_0_s1_translator_avalon_universal_slave_0_agent_rf_source_ready), // .ready .in_startofpacket (timer_0_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket .in_endofpacket (timer_0_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket .out_data (timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // out.data .out_valid (timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid .out_ready (timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // .ready .out_startofpacket (timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket .out_endofpacket (timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket .csr_address (2'b00), // (terminated) .csr_read (1'b0), // (terminated) .csr_write (1'b0), // (terminated) .csr_readdata (), // (terminated) .csr_writedata (32'b00000000000000000000000000000000), // (terminated) .almost_full_data (), // (terminated) .almost_empty_data (), // (terminated) .in_empty (1'b0), // (terminated) .out_empty (), // (terminated) .in_error (1'b0), // (terminated) .out_error (), // (terminated) .in_channel (1'b0), // (terminated) .out_channel () // (terminated) ); altera_merlin_slave_agent #( .PKT_DATA_H (31), .PKT_DATA_L (0), .PKT_BEGIN_BURST (80), .PKT_SYMBOL_W (8), .PKT_BYTEEN_H (35), .PKT_BYTEEN_L (32), .PKT_ADDR_H (60), .PKT_ADDR_L (36), .PKT_TRANS_COMPRESSED_READ (61), .PKT_TRANS_POSTED (62), .PKT_TRANS_WRITE (63), .PKT_TRANS_READ (64), .PKT_TRANS_LOCK (65), .PKT_SRC_ID_H (85), .PKT_SRC_ID_L (82), .PKT_DEST_ID_H (89), .PKT_DEST_ID_L (86), .PKT_BURSTWRAP_H (72), .PKT_BURSTWRAP_L (70), .PKT_BYTE_CNT_H (69), .PKT_BYTE_CNT_L (67), .PKT_PROTECTION_H (93), .PKT_PROTECTION_L (91), .PKT_RESPONSE_STATUS_H (99), .PKT_RESPONSE_STATUS_L (98), .PKT_BURST_SIZE_H (75), .PKT_BURST_SIZE_L (73), .ST_CHANNEL_W (13), .ST_DATA_W (100), .AVS_BURSTCOUNT_W (3), .SUPPRESS_0_BYTEEN_CMD (0), .PREVENT_FIFO_OVERFLOW (1) ) jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent ( .clk (altpll_0_c1_clk), // clk.clk .reset (rst_controller_reset_out_reset), // clk_reset.reset .m0_address (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_address), // m0.address .m0_burstcount (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount .m0_byteenable (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable .m0_debugaccess (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess .m0_lock (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_lock), // .lock .m0_readdata (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata .m0_readdatavalid (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid .m0_read (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_read), // .read .m0_waitrequest (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest .m0_writedata (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata .m0_write (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_write), // .write .rp_endofpacket (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket), // rp.endofpacket .rp_ready (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_ready), // .ready .rp_valid (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_valid), // .valid .rp_data (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_data), // .data .rp_startofpacket (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket .cp_ready (cmd_xbar_demux_001_src7_ready), // cp.ready .cp_valid (cmd_xbar_demux_001_src7_valid), // .valid .cp_data (cmd_xbar_demux_001_src7_data), // .data .cp_startofpacket (cmd_xbar_demux_001_src7_startofpacket), // .startofpacket .cp_endofpacket (cmd_xbar_demux_001_src7_endofpacket), // .endofpacket .cp_channel (cmd_xbar_demux_001_src7_channel), // .channel .rf_sink_ready (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // rf_sink.ready .rf_sink_valid (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid .rf_sink_startofpacket (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket .rf_sink_endofpacket (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket .rf_sink_data (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // .data .rf_source_ready (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_ready), // rf_source.ready .rf_source_valid (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid .rf_source_startofpacket (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket .rf_source_endofpacket (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket .rf_source_data (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_data), // .data .rdata_fifo_sink_ready (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready .rdata_fifo_sink_valid (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid .rdata_fifo_sink_data (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data .rdata_fifo_src_ready (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready .rdata_fifo_src_valid (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid .rdata_fifo_src_data (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data) // .data ); altera_avalon_sc_fifo #( .SYMBOLS_PER_BEAT (1), .BITS_PER_SYMBOL (101), .FIFO_DEPTH (2), .CHANNEL_WIDTH (0), .ERROR_WIDTH (0), .USE_PACKETS (1), .USE_FILL_LEVEL (0), .EMPTY_LATENCY (1), .USE_MEMORY_BLOCKS (0), .USE_STORE_FORWARD (0), .USE_ALMOST_FULL_IF (0), .USE_ALMOST_EMPTY_IF (0) ) jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo ( .clk (altpll_0_c1_clk), // clk.clk .reset (rst_controller_reset_out_reset), // clk_reset.reset .in_data (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_data), // in.data .in_valid (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid .in_ready (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_ready), // .ready .in_startofpacket (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket .in_endofpacket (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket .out_data (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // out.data .out_valid (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid .out_ready (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // .ready .out_startofpacket (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket .out_endofpacket (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket .csr_address (2'b00), // (terminated) .csr_read (1'b0), // (terminated) .csr_write (1'b0), // (terminated) .csr_readdata (), // (terminated) .csr_writedata (32'b00000000000000000000000000000000), // (terminated) .almost_full_data (), // (terminated) .almost_empty_data (), // (terminated) .in_empty (1'b0), // (terminated) .out_empty (), // (terminated) .in_error (1'b0), // (terminated) .out_error (), // (terminated) .in_channel (1'b0), // (terminated) .out_channel () // (terminated) ); altera_merlin_slave_agent #( .PKT_DATA_H (7), .PKT_DATA_L (0), .PKT_BEGIN_BURST (53), .PKT_SYMBOL_W (8), .PKT_BYTEEN_H (8), .PKT_BYTEEN_L (8), .PKT_ADDR_H (33), .PKT_ADDR_L (9), .PKT_TRANS_COMPRESSED_READ (34), .PKT_TRANS_POSTED (35), .PKT_TRANS_WRITE (36), .PKT_TRANS_READ (37), .PKT_TRANS_LOCK (38), .PKT_SRC_ID_H (58), .PKT_SRC_ID_L (55), .PKT_DEST_ID_H (62), .PKT_DEST_ID_L (59), .PKT_BURSTWRAP_H (45), .PKT_BURSTWRAP_L (43), .PKT_BYTE_CNT_H (42), .PKT_BYTE_CNT_L (40), .PKT_PROTECTION_H (66), .PKT_PROTECTION_L (64), .PKT_RESPONSE_STATUS_H (72), .PKT_RESPONSE_STATUS_L (71), .PKT_BURST_SIZE_H (48), .PKT_BURST_SIZE_L (46), .ST_CHANNEL_W (13), .ST_DATA_W (73), .AVS_BURSTCOUNT_W (1), .SUPPRESS_0_BYTEEN_CMD (1), .PREVENT_FIFO_OVERFLOW (1) ) character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent ( .clk (altpll_0_c1_clk), // clk.clk .reset (rst_controller_reset_out_reset), // clk_reset.reset .m0_address (character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_m0_address), // m0.address .m0_burstcount (character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount .m0_byteenable (character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable .m0_debugaccess (character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess .m0_lock (character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_m0_lock), // .lock .m0_readdata (character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata .m0_readdatavalid (character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid .m0_read (character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_m0_read), // .read .m0_waitrequest (character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest .m0_writedata (character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata .m0_write (character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_m0_write), // .write .rp_endofpacket (character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket), // rp.endofpacket .rp_ready (character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_rp_ready), // .ready .rp_valid (character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_rp_valid), // .valid .rp_data (character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_rp_data), // .data .rp_startofpacket (character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket .cp_ready (burst_adapter_002_source0_ready), // cp.ready .cp_valid (burst_adapter_002_source0_valid), // .valid .cp_data (burst_adapter_002_source0_data), // .data .cp_startofpacket (burst_adapter_002_source0_startofpacket), // .startofpacket .cp_endofpacket (burst_adapter_002_source0_endofpacket), // .endofpacket .cp_channel (burst_adapter_002_source0_channel), // .channel .rf_sink_ready (character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // rf_sink.ready .rf_sink_valid (character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid .rf_sink_startofpacket (character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket .rf_sink_endofpacket (character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket .rf_sink_data (character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // .data .rf_source_ready (character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_rf_source_ready), // rf_source.ready .rf_source_valid (character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid .rf_source_startofpacket (character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket .rf_source_endofpacket (character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket .rf_source_data (character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_rf_source_data), // .data .rdata_fifo_sink_ready (character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready .rdata_fifo_sink_valid (character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid .rdata_fifo_sink_data (character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data .rdata_fifo_src_ready (character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready .rdata_fifo_src_valid (character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid .rdata_fifo_src_data (character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data) // .data ); altera_avalon_sc_fifo #( .SYMBOLS_PER_BEAT (1), .BITS_PER_SYMBOL (74), .FIFO_DEPTH (2), .CHANNEL_WIDTH (0), .ERROR_WIDTH (0), .USE_PACKETS (1), .USE_FILL_LEVEL (0), .EMPTY_LATENCY (1), .USE_MEMORY_BLOCKS (0), .USE_STORE_FORWARD (0), .USE_ALMOST_FULL_IF (0), .USE_ALMOST_EMPTY_IF (0) ) character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_rsp_fifo ( .clk (altpll_0_c1_clk), // clk.clk .reset (rst_controller_reset_out_reset), // clk_reset.reset .in_data (character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_rf_source_data), // in.data .in_valid (character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid .in_ready (character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_rf_source_ready), // .ready .in_startofpacket (character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket .in_endofpacket (character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket .out_data (character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // out.data .out_valid (character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid .out_ready (character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // .ready .out_startofpacket (character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket .out_endofpacket (character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket .csr_address (2'b00), // (terminated) .csr_read (1'b0), // (terminated) .csr_write (1'b0), // (terminated) .csr_readdata (), // (terminated) .csr_writedata (32'b00000000000000000000000000000000), // (terminated) .almost_full_data (), // (terminated) .almost_empty_data (), // (terminated) .in_empty (1'b0), // (terminated) .out_empty (), // (terminated) .in_error (1'b0), // (terminated) .out_error (), // (terminated) .in_channel (1'b0), // (terminated) .out_channel () // (terminated) ); altera_merlin_slave_agent #( .PKT_DATA_H (31), .PKT_DATA_L (0), .PKT_BEGIN_BURST (80), .PKT_SYMBOL_W (8), .PKT_BYTEEN_H (35), .PKT_BYTEEN_L (32), .PKT_ADDR_H (60), .PKT_ADDR_L (36), .PKT_TRANS_COMPRESSED_READ (61), .PKT_TRANS_POSTED (62), .PKT_TRANS_WRITE (63), .PKT_TRANS_READ (64), .PKT_TRANS_LOCK (65), .PKT_SRC_ID_H (85), .PKT_SRC_ID_L (82), .PKT_DEST_ID_H (89), .PKT_DEST_ID_L (86), .PKT_BURSTWRAP_H (72), .PKT_BURSTWRAP_L (70), .PKT_BYTE_CNT_H (69), .PKT_BYTE_CNT_L (67), .PKT_PROTECTION_H (93), .PKT_PROTECTION_L (91), .PKT_RESPONSE_STATUS_H (99), .PKT_RESPONSE_STATUS_L (98), .PKT_BURST_SIZE_H (75), .PKT_BURST_SIZE_L (73), .ST_CHANNEL_W (13), .ST_DATA_W (100), .AVS_BURSTCOUNT_W (3), .SUPPRESS_0_BYTEEN_CMD (0), .PREVENT_FIFO_OVERFLOW (1) ) green_leds_s1_translator_avalon_universal_slave_0_agent ( .clk (altpll_0_c1_clk), // clk.clk .reset (rst_controller_reset_out_reset), // clk_reset.reset .m0_address (green_leds_s1_translator_avalon_universal_slave_0_agent_m0_address), // m0.address .m0_burstcount (green_leds_s1_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount .m0_byteenable (green_leds_s1_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable .m0_debugaccess (green_leds_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess .m0_lock (green_leds_s1_translator_avalon_universal_slave_0_agent_m0_lock), // .lock .m0_readdata (green_leds_s1_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata .m0_readdatavalid (green_leds_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid .m0_read (green_leds_s1_translator_avalon_universal_slave_0_agent_m0_read), // .read .m0_waitrequest (green_leds_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest .m0_writedata (green_leds_s1_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata .m0_write (green_leds_s1_translator_avalon_universal_slave_0_agent_m0_write), // .write .rp_endofpacket (green_leds_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket), // rp.endofpacket .rp_ready (green_leds_s1_translator_avalon_universal_slave_0_agent_rp_ready), // .ready .rp_valid (green_leds_s1_translator_avalon_universal_slave_0_agent_rp_valid), // .valid .rp_data (green_leds_s1_translator_avalon_universal_slave_0_agent_rp_data), // .data .rp_startofpacket (green_leds_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket .cp_ready (cmd_xbar_demux_001_src9_ready), // cp.ready .cp_valid (cmd_xbar_demux_001_src9_valid), // .valid .cp_data (cmd_xbar_demux_001_src9_data), // .data .cp_startofpacket (cmd_xbar_demux_001_src9_startofpacket), // .startofpacket .cp_endofpacket (cmd_xbar_demux_001_src9_endofpacket), // .endofpacket .cp_channel (cmd_xbar_demux_001_src9_channel), // .channel .rf_sink_ready (green_leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // rf_sink.ready .rf_sink_valid (green_leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid .rf_sink_startofpacket (green_leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket .rf_sink_endofpacket (green_leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket .rf_sink_data (green_leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // .data .rf_source_ready (green_leds_s1_translator_avalon_universal_slave_0_agent_rf_source_ready), // rf_source.ready .rf_source_valid (green_leds_s1_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid .rf_source_startofpacket (green_leds_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket .rf_source_endofpacket (green_leds_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket .rf_source_data (green_leds_s1_translator_avalon_universal_slave_0_agent_rf_source_data), // .data .rdata_fifo_sink_ready (green_leds_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready .rdata_fifo_sink_valid (green_leds_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid .rdata_fifo_sink_data (green_leds_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data .rdata_fifo_src_ready (green_leds_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready .rdata_fifo_src_valid (green_leds_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid .rdata_fifo_src_data (green_leds_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data) // .data ); altera_avalon_sc_fifo #( .SYMBOLS_PER_BEAT (1), .BITS_PER_SYMBOL (101), .FIFO_DEPTH (2), .CHANNEL_WIDTH (0), .ERROR_WIDTH (0), .USE_PACKETS (1), .USE_FILL_LEVEL (0), .EMPTY_LATENCY (1), .USE_MEMORY_BLOCKS (0), .USE_STORE_FORWARD (0), .USE_ALMOST_FULL_IF (0), .USE_ALMOST_EMPTY_IF (0) ) green_leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ( .clk (altpll_0_c1_clk), // clk.clk .reset (rst_controller_reset_out_reset), // clk_reset.reset .in_data (green_leds_s1_translator_avalon_universal_slave_0_agent_rf_source_data), // in.data .in_valid (green_leds_s1_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid .in_ready (green_leds_s1_translator_avalon_universal_slave_0_agent_rf_source_ready), // .ready .in_startofpacket (green_leds_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket .in_endofpacket (green_leds_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket .out_data (green_leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // out.data .out_valid (green_leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid .out_ready (green_leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // .ready .out_startofpacket (green_leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket .out_endofpacket (green_leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket .csr_address (2'b00), // (terminated) .csr_read (1'b0), // (terminated) .csr_write (1'b0), // (terminated) .csr_readdata (), // (terminated) .csr_writedata (32'b00000000000000000000000000000000), // (terminated) .almost_full_data (), // (terminated) .almost_empty_data (), // (terminated) .in_empty (1'b0), // (terminated) .out_empty (), // (terminated) .in_error (1'b0), // (terminated) .out_error (), // (terminated) .in_channel (1'b0), // (terminated) .out_channel () // (terminated) ); altera_merlin_slave_agent #( .PKT_DATA_H (31), .PKT_DATA_L (0), .PKT_BEGIN_BURST (80), .PKT_SYMBOL_W (8), .PKT_BYTEEN_H (35), .PKT_BYTEEN_L (32), .PKT_ADDR_H (60), .PKT_ADDR_L (36), .PKT_TRANS_COMPRESSED_READ (61), .PKT_TRANS_POSTED (62), .PKT_TRANS_WRITE (63), .PKT_TRANS_READ (64), .PKT_TRANS_LOCK (65), .PKT_SRC_ID_H (85), .PKT_SRC_ID_L (82), .PKT_DEST_ID_H (89), .PKT_DEST_ID_L (86), .PKT_BURSTWRAP_H (72), .PKT_BURSTWRAP_L (70), .PKT_BYTE_CNT_H (69), .PKT_BYTE_CNT_L (67), .PKT_PROTECTION_H (93), .PKT_PROTECTION_L (91), .PKT_RESPONSE_STATUS_H (99), .PKT_RESPONSE_STATUS_L (98), .PKT_BURST_SIZE_H (75), .PKT_BURST_SIZE_L (73), .ST_CHANNEL_W (13), .ST_DATA_W (100), .AVS_BURSTCOUNT_W (3), .SUPPRESS_0_BYTEEN_CMD (0), .PREVENT_FIFO_OVERFLOW (1) ) switch_s1_translator_avalon_universal_slave_0_agent ( .clk (altpll_0_c1_clk), // clk.clk .reset (rst_controller_reset_out_reset), // clk_reset.reset .m0_address (switch_s1_translator_avalon_universal_slave_0_agent_m0_address), // m0.address .m0_burstcount (switch_s1_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount .m0_byteenable (switch_s1_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable .m0_debugaccess (switch_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess .m0_lock (switch_s1_translator_avalon_universal_slave_0_agent_m0_lock), // .lock .m0_readdata (switch_s1_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata .m0_readdatavalid (switch_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid .m0_read (switch_s1_translator_avalon_universal_slave_0_agent_m0_read), // .read .m0_waitrequest (switch_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest .m0_writedata (switch_s1_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata .m0_write (switch_s1_translator_avalon_universal_slave_0_agent_m0_write), // .write .rp_endofpacket (switch_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket), // rp.endofpacket .rp_ready (switch_s1_translator_avalon_universal_slave_0_agent_rp_ready), // .ready .rp_valid (switch_s1_translator_avalon_universal_slave_0_agent_rp_valid), // .valid .rp_data (switch_s1_translator_avalon_universal_slave_0_agent_rp_data), // .data .rp_startofpacket (switch_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket .cp_ready (cmd_xbar_demux_001_src10_ready), // cp.ready .cp_valid (cmd_xbar_demux_001_src10_valid), // .valid .cp_data (cmd_xbar_demux_001_src10_data), // .data .cp_startofpacket (cmd_xbar_demux_001_src10_startofpacket), // .startofpacket .cp_endofpacket (cmd_xbar_demux_001_src10_endofpacket), // .endofpacket .cp_channel (cmd_xbar_demux_001_src10_channel), // .channel .rf_sink_ready (switch_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // rf_sink.ready .rf_sink_valid (switch_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid .rf_sink_startofpacket (switch_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket .rf_sink_endofpacket (switch_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket .rf_sink_data (switch_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // .data .rf_source_ready (switch_s1_translator_avalon_universal_slave_0_agent_rf_source_ready), // rf_source.ready .rf_source_valid (switch_s1_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid .rf_source_startofpacket (switch_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket .rf_source_endofpacket (switch_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket .rf_source_data (switch_s1_translator_avalon_universal_slave_0_agent_rf_source_data), // .data .rdata_fifo_sink_ready (switch_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready .rdata_fifo_sink_valid (switch_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid .rdata_fifo_sink_data (switch_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data .rdata_fifo_src_ready (switch_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready .rdata_fifo_src_valid (switch_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid .rdata_fifo_src_data (switch_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data) // .data ); altera_avalon_sc_fifo #( .SYMBOLS_PER_BEAT (1), .BITS_PER_SYMBOL (101), .FIFO_DEPTH (2), .CHANNEL_WIDTH (0), .ERROR_WIDTH (0), .USE_PACKETS (1), .USE_FILL_LEVEL (0), .EMPTY_LATENCY (1), .USE_MEMORY_BLOCKS (0), .USE_STORE_FORWARD (0), .USE_ALMOST_FULL_IF (0), .USE_ALMOST_EMPTY_IF (0) ) switch_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ( .clk (altpll_0_c1_clk), // clk.clk .reset (rst_controller_reset_out_reset), // clk_reset.reset .in_data (switch_s1_translator_avalon_universal_slave_0_agent_rf_source_data), // in.data .in_valid (switch_s1_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid .in_ready (switch_s1_translator_avalon_universal_slave_0_agent_rf_source_ready), // .ready .in_startofpacket (switch_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket .in_endofpacket (switch_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket .out_data (switch_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // out.data .out_valid (switch_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid .out_ready (switch_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // .ready .out_startofpacket (switch_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket .out_endofpacket (switch_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket .csr_address (2'b00), // (terminated) .csr_read (1'b0), // (terminated) .csr_write (1'b0), // (terminated) .csr_readdata (), // (terminated) .csr_writedata (32'b00000000000000000000000000000000), // (terminated) .almost_full_data (), // (terminated) .almost_empty_data (), // (terminated) .in_empty (1'b0), // (terminated) .out_empty (), // (terminated) .in_error (1'b0), // (terminated) .out_error (), // (terminated) .in_channel (1'b0), // (terminated) .out_channel () // (terminated) ); altera_merlin_slave_agent #( .PKT_DATA_H (31), .PKT_DATA_L (0), .PKT_BEGIN_BURST (80), .PKT_SYMBOL_W (8), .PKT_BYTEEN_H (35), .PKT_BYTEEN_L (32), .PKT_ADDR_H (60), .PKT_ADDR_L (36), .PKT_TRANS_COMPRESSED_READ (61), .PKT_TRANS_POSTED (62), .PKT_TRANS_WRITE (63), .PKT_TRANS_READ (64), .PKT_TRANS_LOCK (65), .PKT_SRC_ID_H (85), .PKT_SRC_ID_L (82), .PKT_DEST_ID_H (89), .PKT_DEST_ID_L (86), .PKT_BURSTWRAP_H (72), .PKT_BURSTWRAP_L (70), .PKT_BYTE_CNT_H (69), .PKT_BYTE_CNT_L (67), .PKT_PROTECTION_H (93), .PKT_PROTECTION_L (91), .PKT_RESPONSE_STATUS_H (99), .PKT_RESPONSE_STATUS_L (98), .PKT_BURST_SIZE_H (75), .PKT_BURST_SIZE_L (73), .ST_CHANNEL_W (13), .ST_DATA_W (100), .AVS_BURSTCOUNT_W (3), .SUPPRESS_0_BYTEEN_CMD (0), .PREVENT_FIFO_OVERFLOW (1) ) switch_0_s1_translator_avalon_universal_slave_0_agent ( .clk (altpll_0_c1_clk), // clk.clk .reset (rst_controller_reset_out_reset), // clk_reset.reset .m0_address (switch_0_s1_translator_avalon_universal_slave_0_agent_m0_address), // m0.address .m0_burstcount (switch_0_s1_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount .m0_byteenable (switch_0_s1_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable .m0_debugaccess (switch_0_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess .m0_lock (switch_0_s1_translator_avalon_universal_slave_0_agent_m0_lock), // .lock .m0_readdata (switch_0_s1_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata .m0_readdatavalid (switch_0_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid .m0_read (switch_0_s1_translator_avalon_universal_slave_0_agent_m0_read), // .read .m0_waitrequest (switch_0_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest .m0_writedata (switch_0_s1_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata .m0_write (switch_0_s1_translator_avalon_universal_slave_0_agent_m0_write), // .write .rp_endofpacket (switch_0_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket), // rp.endofpacket .rp_ready (switch_0_s1_translator_avalon_universal_slave_0_agent_rp_ready), // .ready .rp_valid (switch_0_s1_translator_avalon_universal_slave_0_agent_rp_valid), // .valid .rp_data (switch_0_s1_translator_avalon_universal_slave_0_agent_rp_data), // .data .rp_startofpacket (switch_0_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket .cp_ready (cmd_xbar_demux_001_src11_ready), // cp.ready .cp_valid (cmd_xbar_demux_001_src11_valid), // .valid .cp_data (cmd_xbar_demux_001_src11_data), // .data .cp_startofpacket (cmd_xbar_demux_001_src11_startofpacket), // .startofpacket .cp_endofpacket (cmd_xbar_demux_001_src11_endofpacket), // .endofpacket .cp_channel (cmd_xbar_demux_001_src11_channel), // .channel .rf_sink_ready (switch_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // rf_sink.ready .rf_sink_valid (switch_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid .rf_sink_startofpacket (switch_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket .rf_sink_endofpacket (switch_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket .rf_sink_data (switch_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // .data .rf_source_ready (switch_0_s1_translator_avalon_universal_slave_0_agent_rf_source_ready), // rf_source.ready .rf_source_valid (switch_0_s1_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid .rf_source_startofpacket (switch_0_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket .rf_source_endofpacket (switch_0_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket .rf_source_data (switch_0_s1_translator_avalon_universal_slave_0_agent_rf_source_data), // .data .rdata_fifo_sink_ready (switch_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready .rdata_fifo_sink_valid (switch_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid .rdata_fifo_sink_data (switch_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data .rdata_fifo_src_ready (switch_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready .rdata_fifo_src_valid (switch_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid .rdata_fifo_src_data (switch_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data) // .data ); altera_avalon_sc_fifo #( .SYMBOLS_PER_BEAT (1), .BITS_PER_SYMBOL (101), .FIFO_DEPTH (2), .CHANNEL_WIDTH (0), .ERROR_WIDTH (0), .USE_PACKETS (1), .USE_FILL_LEVEL (0), .EMPTY_LATENCY (1), .USE_MEMORY_BLOCKS (0), .USE_STORE_FORWARD (0), .USE_ALMOST_FULL_IF (0), .USE_ALMOST_EMPTY_IF (0) ) switch_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ( .clk (altpll_0_c1_clk), // clk.clk .reset (rst_controller_reset_out_reset), // clk_reset.reset .in_data (switch_0_s1_translator_avalon_universal_slave_0_agent_rf_source_data), // in.data .in_valid (switch_0_s1_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid .in_ready (switch_0_s1_translator_avalon_universal_slave_0_agent_rf_source_ready), // .ready .in_startofpacket (switch_0_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket .in_endofpacket (switch_0_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket .out_data (switch_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // out.data .out_valid (switch_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid .out_ready (switch_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // .ready .out_startofpacket (switch_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket .out_endofpacket (switch_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket .csr_address (2'b00), // (terminated) .csr_read (1'b0), // (terminated) .csr_write (1'b0), // (terminated) .csr_readdata (), // (terminated) .csr_writedata (32'b00000000000000000000000000000000), // (terminated) .almost_full_data (), // (terminated) .almost_empty_data (), // (terminated) .in_empty (1'b0), // (terminated) .out_empty (), // (terminated) .in_error (1'b0), // (terminated) .out_error (), // (terminated) .in_channel (1'b0), // (terminated) .out_channel () // (terminated) ); altera_merlin_slave_agent #( .PKT_DATA_H (31), .PKT_DATA_L (0), .PKT_BEGIN_BURST (80), .PKT_SYMBOL_W (8), .PKT_BYTEEN_H (35), .PKT_BYTEEN_L (32), .PKT_ADDR_H (60), .PKT_ADDR_L (36), .PKT_TRANS_COMPRESSED_READ (61), .PKT_TRANS_POSTED (62), .PKT_TRANS_WRITE (63), .PKT_TRANS_READ (64), .PKT_TRANS_LOCK (65), .PKT_SRC_ID_H (85), .PKT_SRC_ID_L (82), .PKT_DEST_ID_H (89), .PKT_DEST_ID_L (86), .PKT_BURSTWRAP_H (72), .PKT_BURSTWRAP_L (70), .PKT_BYTE_CNT_H (69), .PKT_BYTE_CNT_L (67), .PKT_PROTECTION_H (93), .PKT_PROTECTION_L (91), .PKT_RESPONSE_STATUS_H (99), .PKT_RESPONSE_STATUS_L (98), .PKT_BURST_SIZE_H (75), .PKT_BURST_SIZE_L (73), .ST_CHANNEL_W (13), .ST_DATA_W (100), .AVS_BURSTCOUNT_W (3), .SUPPRESS_0_BYTEEN_CMD (0), .PREVENT_FIFO_OVERFLOW (1) ) servo_pwm_0_s0_translator_avalon_universal_slave_0_agent ( .clk (altpll_0_c1_clk), // clk.clk .reset (rst_controller_reset_out_reset), // clk_reset.reset .m0_address (servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_m0_address), // m0.address .m0_burstcount (servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount .m0_byteenable (servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable .m0_debugaccess (servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess .m0_lock (servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_m0_lock), // .lock .m0_readdata (servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata .m0_readdatavalid (servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid .m0_read (servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_m0_read), // .read .m0_waitrequest (servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest .m0_writedata (servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata .m0_write (servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_m0_write), // .write .rp_endofpacket (servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_rp_endofpacket), // rp.endofpacket .rp_ready (servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_rp_ready), // .ready .rp_valid (servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_rp_valid), // .valid .rp_data (servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_rp_data), // .data .rp_startofpacket (servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket .cp_ready (cmd_xbar_demux_001_src12_ready), // cp.ready .cp_valid (cmd_xbar_demux_001_src12_valid), // .valid .cp_data (cmd_xbar_demux_001_src12_data), // .data .cp_startofpacket (cmd_xbar_demux_001_src12_startofpacket), // .startofpacket .cp_endofpacket (cmd_xbar_demux_001_src12_endofpacket), // .endofpacket .cp_channel (cmd_xbar_demux_001_src12_channel), // .channel .rf_sink_ready (servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // rf_sink.ready .rf_sink_valid (servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid .rf_sink_startofpacket (servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket .rf_sink_endofpacket (servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket .rf_sink_data (servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // .data .rf_source_ready (servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_rf_source_ready), // rf_source.ready .rf_source_valid (servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid .rf_source_startofpacket (servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket .rf_source_endofpacket (servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket .rf_source_data (servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_rf_source_data), // .data .rdata_fifo_sink_ready (servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready .rdata_fifo_sink_valid (servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid .rdata_fifo_sink_data (servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data .rdata_fifo_src_ready (servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready .rdata_fifo_src_valid (servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid .rdata_fifo_src_data (servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data) // .data ); altera_avalon_sc_fifo #( .SYMBOLS_PER_BEAT (1), .BITS_PER_SYMBOL (101), .FIFO_DEPTH (2), .CHANNEL_WIDTH (0), .ERROR_WIDTH (0), .USE_PACKETS (1), .USE_FILL_LEVEL (0), .EMPTY_LATENCY (1), .USE_MEMORY_BLOCKS (0), .USE_STORE_FORWARD (0), .USE_ALMOST_FULL_IF (0), .USE_ALMOST_EMPTY_IF (0) ) servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_rsp_fifo ( .clk (altpll_0_c1_clk), // clk.clk .reset (rst_controller_reset_out_reset), // clk_reset.reset .in_data (servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_rf_source_data), // in.data .in_valid (servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid .in_ready (servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_rf_source_ready), // .ready .in_startofpacket (servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket .in_endofpacket (servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket .out_data (servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // out.data .out_valid (servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid .out_ready (servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // .ready .out_startofpacket (servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket .out_endofpacket (servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket .csr_address (2'b00), // (terminated) .csr_read (1'b0), // (terminated) .csr_write (1'b0), // (terminated) .csr_readdata (), // (terminated) .csr_writedata (32'b00000000000000000000000000000000), // (terminated) .almost_full_data (), // (terminated) .almost_empty_data (), // (terminated) .in_empty (1'b0), // (terminated) .out_empty (), // (terminated) .in_error (1'b0), // (terminated) .out_error (), // (terminated) .in_channel (1'b0), // (terminated) .out_channel () // (terminated) ); tracking_camera_system_addr_router addr_router ( .sink_ready (nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent_cp_ready), // sink.ready .sink_valid (nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent_cp_valid), // .valid .sink_data (nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent_cp_data), // .data .sink_startofpacket (nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent_cp_startofpacket), // .startofpacket .sink_endofpacket (nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent_cp_endofpacket), // .endofpacket .clk (altpll_0_c1_clk), // clk.clk .reset (rst_controller_reset_out_reset), // clk_reset.reset .src_ready (addr_router_src_ready), // src.ready .src_valid (addr_router_src_valid), // .valid .src_data (addr_router_src_data), // .data .src_channel (addr_router_src_channel), // .channel .src_startofpacket (addr_router_src_startofpacket), // .startofpacket .src_endofpacket (addr_router_src_endofpacket) // .endofpacket ); tracking_camera_system_addr_router_001 addr_router_001 ( .sink_ready (nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent_cp_ready), // sink.ready .sink_valid (nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent_cp_valid), // .valid .sink_data (nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent_cp_data), // .data .sink_startofpacket (nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent_cp_startofpacket), // .startofpacket .sink_endofpacket (nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent_cp_endofpacket), // .endofpacket .clk (altpll_0_c1_clk), // clk.clk .reset (rst_controller_reset_out_reset), // clk_reset.reset .src_ready (addr_router_001_src_ready), // src.ready .src_valid (addr_router_001_src_valid), // .valid .src_data (addr_router_001_src_data), // .data .src_channel (addr_router_001_src_channel), // .channel .src_startofpacket (addr_router_001_src_startofpacket), // .startofpacket .src_endofpacket (addr_router_001_src_endofpacket) // .endofpacket ); tracking_camera_system_id_router id_router ( .sink_ready (nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready .sink_valid (nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_valid), // .valid .sink_data (nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_data), // .data .sink_startofpacket (nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket .sink_endofpacket (nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_endofpacket), // .endofpacket .clk (altpll_0_c1_clk), // clk.clk .reset (rst_controller_reset_out_reset), // clk_reset.reset .src_ready (id_router_src_ready), // src.ready .src_valid (id_router_src_valid), // .valid .src_data (id_router_src_data), // .data .src_channel (id_router_src_channel), // .channel .src_startofpacket (id_router_src_startofpacket), // .startofpacket .src_endofpacket (id_router_src_endofpacket) // .endofpacket ); tracking_camera_system_id_router id_router_001 ( .sink_ready (onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready .sink_valid (onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rp_valid), // .valid .sink_data (onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rp_data), // .data .sink_startofpacket (onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket .sink_endofpacket (onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket), // .endofpacket .clk (altpll_0_c1_clk), // clk.clk .reset (rst_controller_reset_out_reset), // clk_reset.reset .src_ready (id_router_001_src_ready), // src.ready .src_valid (id_router_001_src_valid), // .valid .src_data (id_router_001_src_data), // .data .src_channel (id_router_001_src_channel), // .channel .src_startofpacket (id_router_001_src_startofpacket), // .startofpacket .src_endofpacket (id_router_001_src_endofpacket) // .endofpacket ); tracking_camera_system_id_router_002 id_router_002 ( .sink_ready (sdram_0_s1_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready .sink_valid (sdram_0_s1_translator_avalon_universal_slave_0_agent_rp_valid), // .valid .sink_data (sdram_0_s1_translator_avalon_universal_slave_0_agent_rp_data), // .data .sink_startofpacket (sdram_0_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket .sink_endofpacket (sdram_0_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket), // .endofpacket .clk (altpll_0_c1_clk), // clk.clk .reset (rst_controller_reset_out_reset), // clk_reset.reset .src_ready (id_router_002_src_ready), // src.ready .src_valid (id_router_002_src_valid), // .valid .src_data (id_router_002_src_data), // .data .src_channel (id_router_002_src_channel), // .channel .src_startofpacket (id_router_002_src_startofpacket), // .startofpacket .src_endofpacket (id_router_002_src_endofpacket) // .endofpacket ); tracking_camera_system_id_router_002 id_router_003 ( .sink_ready (sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready .sink_valid (sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rp_valid), // .valid .sink_data (sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rp_data), // .data .sink_startofpacket (sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket .sink_endofpacket (sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket), // .endofpacket .clk (altpll_0_c1_clk), // clk.clk .reset (rst_controller_reset_out_reset), // clk_reset.reset .src_ready (id_router_003_src_ready), // src.ready .src_valid (id_router_003_src_valid), // .valid .src_data (id_router_003_src_data), // .data .src_channel (id_router_003_src_channel), // .channel .src_startofpacket (id_router_003_src_startofpacket), // .startofpacket .src_endofpacket (id_router_003_src_endofpacket) // .endofpacket ); tracking_camera_system_id_router_004 id_router_004 ( .sink_ready (altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready .sink_valid (altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rp_valid), // .valid .sink_data (altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rp_data), // .data .sink_startofpacket (altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket .sink_endofpacket (altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket), // .endofpacket .clk (clk_clk), // clk.clk .reset (rst_controller_001_reset_out_reset), // clk_reset.reset .src_ready (id_router_004_src_ready), // src.ready .src_valid (id_router_004_src_valid), // .valid .src_data (id_router_004_src_data), // .data .src_channel (id_router_004_src_channel), // .channel .src_startofpacket (id_router_004_src_startofpacket), // .startofpacket .src_endofpacket (id_router_004_src_endofpacket) // .endofpacket ); tracking_camera_system_id_router_004 id_router_005 ( .sink_ready (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready .sink_valid (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rp_valid), // .valid .sink_data (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rp_data), // .data .sink_startofpacket (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket .sink_endofpacket (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket), // .endofpacket .clk (altpll_0_c1_clk), // clk.clk .reset (rst_controller_reset_out_reset), // clk_reset.reset .src_ready (id_router_005_src_ready), // src.ready .src_valid (id_router_005_src_valid), // .valid .src_data (id_router_005_src_data), // .data .src_channel (id_router_005_src_channel), // .channel .src_startofpacket (id_router_005_src_startofpacket), // .startofpacket .src_endofpacket (id_router_005_src_endofpacket) // .endofpacket ); tracking_camera_system_id_router_004 id_router_006 ( .sink_ready (timer_0_s1_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready .sink_valid (timer_0_s1_translator_avalon_universal_slave_0_agent_rp_valid), // .valid .sink_data (timer_0_s1_translator_avalon_universal_slave_0_agent_rp_data), // .data .sink_startofpacket (timer_0_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket .sink_endofpacket (timer_0_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket), // .endofpacket .clk (altpll_0_c1_clk), // clk.clk .reset (rst_controller_reset_out_reset), // clk_reset.reset .src_ready (id_router_006_src_ready), // src.ready .src_valid (id_router_006_src_valid), // .valid .src_data (id_router_006_src_data), // .data .src_channel (id_router_006_src_channel), // .channel .src_startofpacket (id_router_006_src_startofpacket), // .startofpacket .src_endofpacket (id_router_006_src_endofpacket) // .endofpacket ); tracking_camera_system_id_router_004 id_router_007 ( .sink_ready (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready .sink_valid (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_valid), // .valid .sink_data (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_data), // .data .sink_startofpacket (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket .sink_endofpacket (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket), // .endofpacket .clk (altpll_0_c1_clk), // clk.clk .reset (rst_controller_reset_out_reset), // clk_reset.reset .src_ready (id_router_007_src_ready), // src.ready .src_valid (id_router_007_src_valid), // .valid .src_data (id_router_007_src_data), // .data .src_channel (id_router_007_src_channel), // .channel .src_startofpacket (id_router_007_src_startofpacket), // .startofpacket .src_endofpacket (id_router_007_src_endofpacket) // .endofpacket ); tracking_camera_system_id_router_008 id_router_008 ( .sink_ready (character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready .sink_valid (character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_rp_valid), // .valid .sink_data (character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_rp_data), // .data .sink_startofpacket (character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket .sink_endofpacket (character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket), // .endofpacket .clk (altpll_0_c1_clk), // clk.clk .reset (rst_controller_reset_out_reset), // clk_reset.reset .src_ready (id_router_008_src_ready), // src.ready .src_valid (id_router_008_src_valid), // .valid .src_data (id_router_008_src_data), // .data .src_channel (id_router_008_src_channel), // .channel .src_startofpacket (id_router_008_src_startofpacket), // .startofpacket .src_endofpacket (id_router_008_src_endofpacket) // .endofpacket ); tracking_camera_system_id_router_004 id_router_009 ( .sink_ready (green_leds_s1_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready .sink_valid (green_leds_s1_translator_avalon_universal_slave_0_agent_rp_valid), // .valid .sink_data (green_leds_s1_translator_avalon_universal_slave_0_agent_rp_data), // .data .sink_startofpacket (green_leds_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket .sink_endofpacket (green_leds_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket), // .endofpacket .clk (altpll_0_c1_clk), // clk.clk .reset (rst_controller_reset_out_reset), // clk_reset.reset .src_ready (id_router_009_src_ready), // src.ready .src_valid (id_router_009_src_valid), // .valid .src_data (id_router_009_src_data), // .data .src_channel (id_router_009_src_channel), // .channel .src_startofpacket (id_router_009_src_startofpacket), // .startofpacket .src_endofpacket (id_router_009_src_endofpacket) // .endofpacket ); tracking_camera_system_id_router_004 id_router_010 ( .sink_ready (switch_s1_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready .sink_valid (switch_s1_translator_avalon_universal_slave_0_agent_rp_valid), // .valid .sink_data (switch_s1_translator_avalon_universal_slave_0_agent_rp_data), // .data .sink_startofpacket (switch_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket .sink_endofpacket (switch_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket), // .endofpacket .clk (altpll_0_c1_clk), // clk.clk .reset (rst_controller_reset_out_reset), // clk_reset.reset .src_ready (id_router_010_src_ready), // src.ready .src_valid (id_router_010_src_valid), // .valid .src_data (id_router_010_src_data), // .data .src_channel (id_router_010_src_channel), // .channel .src_startofpacket (id_router_010_src_startofpacket), // .startofpacket .src_endofpacket (id_router_010_src_endofpacket) // .endofpacket ); tracking_camera_system_id_router_004 id_router_011 ( .sink_ready (switch_0_s1_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready .sink_valid (switch_0_s1_translator_avalon_universal_slave_0_agent_rp_valid), // .valid .sink_data (switch_0_s1_translator_avalon_universal_slave_0_agent_rp_data), // .data .sink_startofpacket (switch_0_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket .sink_endofpacket (switch_0_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket), // .endofpacket .clk (altpll_0_c1_clk), // clk.clk .reset (rst_controller_reset_out_reset), // clk_reset.reset .src_ready (id_router_011_src_ready), // src.ready .src_valid (id_router_011_src_valid), // .valid .src_data (id_router_011_src_data), // .data .src_channel (id_router_011_src_channel), // .channel .src_startofpacket (id_router_011_src_startofpacket), // .startofpacket .src_endofpacket (id_router_011_src_endofpacket) // .endofpacket ); tracking_camera_system_id_router_004 id_router_012 ( .sink_ready (servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready .sink_valid (servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_rp_valid), // .valid .sink_data (servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_rp_data), // .data .sink_startofpacket (servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket .sink_endofpacket (servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_rp_endofpacket), // .endofpacket .clk (altpll_0_c1_clk), // clk.clk .reset (rst_controller_reset_out_reset), // clk_reset.reset .src_ready (id_router_012_src_ready), // src.ready .src_valid (id_router_012_src_valid), // .valid .src_data (id_router_012_src_data), // .data .src_channel (id_router_012_src_channel), // .channel .src_startofpacket (id_router_012_src_startofpacket), // .startofpacket .src_endofpacket (id_router_012_src_endofpacket) // .endofpacket ); altera_merlin_traffic_limiter #( .PKT_DEST_ID_H (89), .PKT_DEST_ID_L (86), .PKT_TRANS_POSTED (62), .PKT_TRANS_WRITE (63), .MAX_OUTSTANDING_RESPONSES (9), .PIPELINED (0), .ST_DATA_W (100), .ST_CHANNEL_W (13), .VALID_WIDTH (13), .ENFORCE_ORDER (1), .PREVENT_HAZARDS (0), .PKT_BYTE_CNT_H (69), .PKT_BYTE_CNT_L (67), .PKT_BYTEEN_H (35), .PKT_BYTEEN_L (32) ) limiter ( .clk (altpll_0_c1_clk), // clk.clk .reset (rst_controller_reset_out_reset), // clk_reset.reset .cmd_sink_ready (addr_router_src_ready), // cmd_sink.ready .cmd_sink_valid (addr_router_src_valid), // .valid .cmd_sink_data (addr_router_src_data), // .data .cmd_sink_channel (addr_router_src_channel), // .channel .cmd_sink_startofpacket (addr_router_src_startofpacket), // .startofpacket .cmd_sink_endofpacket (addr_router_src_endofpacket), // .endofpacket .cmd_src_ready (limiter_cmd_src_ready), // cmd_src.ready .cmd_src_data (limiter_cmd_src_data), // .data .cmd_src_channel (limiter_cmd_src_channel), // .channel .cmd_src_startofpacket (limiter_cmd_src_startofpacket), // .startofpacket .cmd_src_endofpacket (limiter_cmd_src_endofpacket), // .endofpacket .rsp_sink_ready (rsp_xbar_mux_src_ready), // rsp_sink.ready .rsp_sink_valid (rsp_xbar_mux_src_valid), // .valid .rsp_sink_channel (rsp_xbar_mux_src_channel), // .channel .rsp_sink_data (rsp_xbar_mux_src_data), // .data .rsp_sink_startofpacket (rsp_xbar_mux_src_startofpacket), // .startofpacket .rsp_sink_endofpacket (rsp_xbar_mux_src_endofpacket), // .endofpacket .rsp_src_ready (limiter_rsp_src_ready), // rsp_src.ready .rsp_src_valid (limiter_rsp_src_valid), // .valid .rsp_src_data (limiter_rsp_src_data), // .data .rsp_src_channel (limiter_rsp_src_channel), // .channel .rsp_src_startofpacket (limiter_rsp_src_startofpacket), // .startofpacket .rsp_src_endofpacket (limiter_rsp_src_endofpacket), // .endofpacket .cmd_src_valid (limiter_cmd_valid_data) // cmd_valid.data ); altera_merlin_traffic_limiter #( .PKT_DEST_ID_H (89), .PKT_DEST_ID_L (86), .PKT_TRANS_POSTED (62), .PKT_TRANS_WRITE (63), .MAX_OUTSTANDING_RESPONSES (9), .PIPELINED (0), .ST_DATA_W (100), .ST_CHANNEL_W (13), .VALID_WIDTH (13), .ENFORCE_ORDER (1), .PREVENT_HAZARDS (0), .PKT_BYTE_CNT_H (69), .PKT_BYTE_CNT_L (67), .PKT_BYTEEN_H (35), .PKT_BYTEEN_L (32) ) limiter_001 ( .clk (altpll_0_c1_clk), // clk.clk .reset (rst_controller_reset_out_reset), // clk_reset.reset .cmd_sink_ready (addr_router_001_src_ready), // cmd_sink.ready .cmd_sink_valid (addr_router_001_src_valid), // .valid .cmd_sink_data (addr_router_001_src_data), // .data .cmd_sink_channel (addr_router_001_src_channel), // .channel .cmd_sink_startofpacket (addr_router_001_src_startofpacket), // .startofpacket .cmd_sink_endofpacket (addr_router_001_src_endofpacket), // .endofpacket .cmd_src_ready (limiter_001_cmd_src_ready), // cmd_src.ready .cmd_src_data (limiter_001_cmd_src_data), // .data .cmd_src_channel (limiter_001_cmd_src_channel), // .channel .cmd_src_startofpacket (limiter_001_cmd_src_startofpacket), // .startofpacket .cmd_src_endofpacket (limiter_001_cmd_src_endofpacket), // .endofpacket .rsp_sink_ready (rsp_xbar_mux_001_src_ready), // rsp_sink.ready .rsp_sink_valid (rsp_xbar_mux_001_src_valid), // .valid .rsp_sink_channel (rsp_xbar_mux_001_src_channel), // .channel .rsp_sink_data (rsp_xbar_mux_001_src_data), // .data .rsp_sink_startofpacket (rsp_xbar_mux_001_src_startofpacket), // .startofpacket .rsp_sink_endofpacket (rsp_xbar_mux_001_src_endofpacket), // .endofpacket .rsp_src_ready (limiter_001_rsp_src_ready), // rsp_src.ready .rsp_src_valid (limiter_001_rsp_src_valid), // .valid .rsp_src_data (limiter_001_rsp_src_data), // .data .rsp_src_channel (limiter_001_rsp_src_channel), // .channel .rsp_src_startofpacket (limiter_001_rsp_src_startofpacket), // .startofpacket .rsp_src_endofpacket (limiter_001_rsp_src_endofpacket), // .endofpacket .cmd_src_valid (limiter_001_cmd_valid_data) // cmd_valid.data ); altera_merlin_burst_adapter #( .PKT_ADDR_H (42), .PKT_ADDR_L (18), .PKT_BEGIN_BURST (62), .PKT_BYTE_CNT_H (51), .PKT_BYTE_CNT_L (49), .PKT_BYTEEN_H (17), .PKT_BYTEEN_L (16), .PKT_BURST_SIZE_H (57), .PKT_BURST_SIZE_L (55), .PKT_BURST_TYPE_H (59), .PKT_BURST_TYPE_L (58), .PKT_BURSTWRAP_H (54), .PKT_BURSTWRAP_L (52), .PKT_TRANS_COMPRESSED_READ (43), .PKT_TRANS_WRITE (45), .PKT_TRANS_READ (46), .OUT_NARROW_SIZE (0), .IN_NARROW_SIZE (0), .OUT_FIXED (0), .OUT_COMPLETE_WRAP (0), .ST_DATA_W (82), .ST_CHANNEL_W (13), .OUT_BYTE_CNT_H (50), .OUT_BURSTWRAP_H (54), .COMPRESSED_READ_SUPPORT (0), .BYTEENABLE_SYNTHESIS (0), .PIPE_INPUTS (0), .NO_WRAP_SUPPORT (0), .BURSTWRAP_CONST_MASK (3), .BURSTWRAP_CONST_VALUE (3) ) burst_adapter ( .clk (altpll_0_c1_clk), // cr0.clk .reset (rst_controller_reset_out_reset), // cr0_reset.reset .sink0_valid (width_adapter_src_valid), // sink0.valid .sink0_data (width_adapter_src_data), // .data .sink0_channel (width_adapter_src_channel), // .channel .sink0_startofpacket (width_adapter_src_startofpacket), // .startofpacket .sink0_endofpacket (width_adapter_src_endofpacket), // .endofpacket .sink0_ready (width_adapter_src_ready), // .ready .source0_valid (burst_adapter_source0_valid), // source0.valid .source0_data (burst_adapter_source0_data), // .data .source0_channel (burst_adapter_source0_channel), // .channel .source0_startofpacket (burst_adapter_source0_startofpacket), // .startofpacket .source0_endofpacket (burst_adapter_source0_endofpacket), // .endofpacket .source0_ready (burst_adapter_source0_ready) // .ready ); altera_merlin_burst_adapter #( .PKT_ADDR_H (42), .PKT_ADDR_L (18), .PKT_BEGIN_BURST (62), .PKT_BYTE_CNT_H (51), .PKT_BYTE_CNT_L (49), .PKT_BYTEEN_H (17), .PKT_BYTEEN_L (16), .PKT_BURST_SIZE_H (57), .PKT_BURST_SIZE_L (55), .PKT_BURST_TYPE_H (59), .PKT_BURST_TYPE_L (58), .PKT_BURSTWRAP_H (54), .PKT_BURSTWRAP_L (52), .PKT_TRANS_COMPRESSED_READ (43), .PKT_TRANS_WRITE (45), .PKT_TRANS_READ (46), .OUT_NARROW_SIZE (0), .IN_NARROW_SIZE (0), .OUT_FIXED (0), .OUT_COMPLETE_WRAP (0), .ST_DATA_W (82), .ST_CHANNEL_W (13), .OUT_BYTE_CNT_H (50), .OUT_BURSTWRAP_H (54), .COMPRESSED_READ_SUPPORT (0), .BYTEENABLE_SYNTHESIS (0), .PIPE_INPUTS (0), .NO_WRAP_SUPPORT (0), .BURSTWRAP_CONST_MASK (3), .BURSTWRAP_CONST_VALUE (3) ) burst_adapter_001 ( .clk (altpll_0_c1_clk), // cr0.clk .reset (rst_controller_reset_out_reset), // cr0_reset.reset .sink0_valid (width_adapter_002_src_valid), // sink0.valid .sink0_data (width_adapter_002_src_data), // .data .sink0_channel (width_adapter_002_src_channel), // .channel .sink0_startofpacket (width_adapter_002_src_startofpacket), // .startofpacket .sink0_endofpacket (width_adapter_002_src_endofpacket), // .endofpacket .sink0_ready (width_adapter_002_src_ready), // .ready .source0_valid (burst_adapter_001_source0_valid), // source0.valid .source0_data (burst_adapter_001_source0_data), // .data .source0_channel (burst_adapter_001_source0_channel), // .channel .source0_startofpacket (burst_adapter_001_source0_startofpacket), // .startofpacket .source0_endofpacket (burst_adapter_001_source0_endofpacket), // .endofpacket .source0_ready (burst_adapter_001_source0_ready) // .ready ); altera_merlin_burst_adapter #( .PKT_ADDR_H (33), .PKT_ADDR_L (9), .PKT_BEGIN_BURST (53), .PKT_BYTE_CNT_H (42), .PKT_BYTE_CNT_L (40), .PKT_BYTEEN_H (8), .PKT_BYTEEN_L (8), .PKT_BURST_SIZE_H (48), .PKT_BURST_SIZE_L (46), .PKT_BURST_TYPE_H (50), .PKT_BURST_TYPE_L (49), .PKT_BURSTWRAP_H (45), .PKT_BURSTWRAP_L (43), .PKT_TRANS_COMPRESSED_READ (34), .PKT_TRANS_WRITE (36), .PKT_TRANS_READ (37), .OUT_NARROW_SIZE (0), .IN_NARROW_SIZE (0), .OUT_FIXED (0), .OUT_COMPLETE_WRAP (0), .ST_DATA_W (73), .ST_CHANNEL_W (13), .OUT_BYTE_CNT_H (40), .OUT_BURSTWRAP_H (45), .COMPRESSED_READ_SUPPORT (0), .BYTEENABLE_SYNTHESIS (0), .PIPE_INPUTS (0), .NO_WRAP_SUPPORT (0), .BURSTWRAP_CONST_MASK (7), .BURSTWRAP_CONST_VALUE (7) ) burst_adapter_002 ( .clk (altpll_0_c1_clk), // cr0.clk .reset (rst_controller_reset_out_reset), // cr0_reset.reset .sink0_valid (width_adapter_004_src_valid), // sink0.valid .sink0_data (width_adapter_004_src_data), // .data .sink0_channel (width_adapter_004_src_channel), // .channel .sink0_startofpacket (width_adapter_004_src_startofpacket), // .startofpacket .sink0_endofpacket (width_adapter_004_src_endofpacket), // .endofpacket .sink0_ready (width_adapter_004_src_ready), // .ready .source0_valid (burst_adapter_002_source0_valid), // source0.valid .source0_data (burst_adapter_002_source0_data), // .data .source0_channel (burst_adapter_002_source0_channel), // .channel .source0_startofpacket (burst_adapter_002_source0_startofpacket), // .startofpacket .source0_endofpacket (burst_adapter_002_source0_endofpacket), // .endofpacket .source0_ready (burst_adapter_002_source0_ready) // .ready ); altera_reset_controller #( .NUM_RESET_INPUTS (2), .OUTPUT_RESET_SYNC_EDGES ("deassert"), .SYNC_DEPTH (2) ) rst_controller ( .reset_in0 (~reset_reset_n), // reset_in0.reset .reset_in1 (nios2_qsys_0_jtag_debug_module_reset_reset), // reset_in1.reset .clk (altpll_0_c1_clk), // clk.clk .reset_out (rst_controller_reset_out_reset), // reset_out.reset .reset_in2 (1'b0), // (terminated) .reset_in3 (1'b0), // (terminated) .reset_in4 (1'b0), // (terminated) .reset_in5 (1'b0), // (terminated) .reset_in6 (1'b0), // (terminated) .reset_in7 (1'b0), // (terminated) .reset_in8 (1'b0), // (terminated) .reset_in9 (1'b0), // (terminated) .reset_in10 (1'b0), // (terminated) .reset_in11 (1'b0), // (terminated) .reset_in12 (1'b0), // (terminated) .reset_in13 (1'b0), // (terminated) .reset_in14 (1'b0), // (terminated) .reset_in15 (1'b0) // (terminated) ); altera_reset_controller #( .NUM_RESET_INPUTS (2), .OUTPUT_RESET_SYNC_EDGES ("deassert"), .SYNC_DEPTH (2) ) rst_controller_001 ( .reset_in0 (~reset_reset_n), // reset_in0.reset .reset_in1 (nios2_qsys_0_jtag_debug_module_reset_reset), // reset_in1.reset .clk (clk_clk), // clk.clk .reset_out (rst_controller_001_reset_out_reset), // reset_out.reset .reset_in2 (1'b0), // (terminated) .reset_in3 (1'b0), // (terminated) .reset_in4 (1'b0), // (terminated) .reset_in5 (1'b0), // (terminated) .reset_in6 (1'b0), // (terminated) .reset_in7 (1'b0), // (terminated) .reset_in8 (1'b0), // (terminated) .reset_in9 (1'b0), // (terminated) .reset_in10 (1'b0), // (terminated) .reset_in11 (1'b0), // (terminated) .reset_in12 (1'b0), // (terminated) .reset_in13 (1'b0), // (terminated) .reset_in14 (1'b0), // (terminated) .reset_in15 (1'b0) // (terminated) ); tracking_camera_system_cmd_xbar_demux cmd_xbar_demux ( .clk (altpll_0_c1_clk), // clk.clk .reset (rst_controller_reset_out_reset), // clk_reset.reset .sink_ready (limiter_cmd_src_ready), // sink.ready .sink_channel (limiter_cmd_src_channel), // .channel .sink_data (limiter_cmd_src_data), // .data .sink_startofpacket (limiter_cmd_src_startofpacket), // .startofpacket .sink_endofpacket (limiter_cmd_src_endofpacket), // .endofpacket .sink_valid (limiter_cmd_valid_data), // sink_valid.data .src0_ready (cmd_xbar_demux_src0_ready), // src0.ready .src0_valid (cmd_xbar_demux_src0_valid), // .valid .src0_data (cmd_xbar_demux_src0_data), // .data .src0_channel (cmd_xbar_demux_src0_channel), // .channel .src0_startofpacket (cmd_xbar_demux_src0_startofpacket), // .startofpacket .src0_endofpacket (cmd_xbar_demux_src0_endofpacket), // .endofpacket .src1_ready (cmd_xbar_demux_src1_ready), // src1.ready .src1_valid (cmd_xbar_demux_src1_valid), // .valid .src1_data (cmd_xbar_demux_src1_data), // .data .src1_channel (cmd_xbar_demux_src1_channel), // .channel .src1_startofpacket (cmd_xbar_demux_src1_startofpacket), // .startofpacket .src1_endofpacket (cmd_xbar_demux_src1_endofpacket), // .endofpacket .src2_ready (cmd_xbar_demux_src2_ready), // src2.ready .src2_valid (cmd_xbar_demux_src2_valid), // .valid .src2_data (cmd_xbar_demux_src2_data), // .data .src2_channel (cmd_xbar_demux_src2_channel), // .channel .src2_startofpacket (cmd_xbar_demux_src2_startofpacket), // .startofpacket .src2_endofpacket (cmd_xbar_demux_src2_endofpacket), // .endofpacket .src3_ready (cmd_xbar_demux_src3_ready), // src3.ready .src3_valid (cmd_xbar_demux_src3_valid), // .valid .src3_data (cmd_xbar_demux_src3_data), // .data .src3_channel (cmd_xbar_demux_src3_channel), // .channel .src3_startofpacket (cmd_xbar_demux_src3_startofpacket), // .startofpacket .src3_endofpacket (cmd_xbar_demux_src3_endofpacket) // .endofpacket ); tracking_camera_system_cmd_xbar_demux_001 cmd_xbar_demux_001 ( .clk (altpll_0_c1_clk), // clk.clk .reset (rst_controller_reset_out_reset), // clk_reset.reset .sink_ready (limiter_001_cmd_src_ready), // sink.ready .sink_channel (limiter_001_cmd_src_channel), // .channel .sink_data (limiter_001_cmd_src_data), // .data .sink_startofpacket (limiter_001_cmd_src_startofpacket), // .startofpacket .sink_endofpacket (limiter_001_cmd_src_endofpacket), // .endofpacket .sink_valid (limiter_001_cmd_valid_data), // sink_valid.data .src0_ready (cmd_xbar_demux_001_src0_ready), // src0.ready .src0_valid (cmd_xbar_demux_001_src0_valid), // .valid .src0_data (cmd_xbar_demux_001_src0_data), // .data .src0_channel (cmd_xbar_demux_001_src0_channel), // .channel .src0_startofpacket (cmd_xbar_demux_001_src0_startofpacket), // .startofpacket .src0_endofpacket (cmd_xbar_demux_001_src0_endofpacket), // .endofpacket .src1_ready (cmd_xbar_demux_001_src1_ready), // src1.ready .src1_valid (cmd_xbar_demux_001_src1_valid), // .valid .src1_data (cmd_xbar_demux_001_src1_data), // .data .src1_channel (cmd_xbar_demux_001_src1_channel), // .channel .src1_startofpacket (cmd_xbar_demux_001_src1_startofpacket), // .startofpacket .src1_endofpacket (cmd_xbar_demux_001_src1_endofpacket), // .endofpacket .src2_ready (cmd_xbar_demux_001_src2_ready), // src2.ready .src2_valid (cmd_xbar_demux_001_src2_valid), // .valid .src2_data (cmd_xbar_demux_001_src2_data), // .data .src2_channel (cmd_xbar_demux_001_src2_channel), // .channel .src2_startofpacket (cmd_xbar_demux_001_src2_startofpacket), // .startofpacket .src2_endofpacket (cmd_xbar_demux_001_src2_endofpacket), // .endofpacket .src3_ready (cmd_xbar_demux_001_src3_ready), // src3.ready .src3_valid (cmd_xbar_demux_001_src3_valid), // .valid .src3_data (cmd_xbar_demux_001_src3_data), // .data .src3_channel (cmd_xbar_demux_001_src3_channel), // .channel .src3_startofpacket (cmd_xbar_demux_001_src3_startofpacket), // .startofpacket .src3_endofpacket (cmd_xbar_demux_001_src3_endofpacket), // .endofpacket .src4_ready (cmd_xbar_demux_001_src4_ready), // src4.ready .src4_valid (cmd_xbar_demux_001_src4_valid), // .valid .src4_data (cmd_xbar_demux_001_src4_data), // .data .src4_channel (cmd_xbar_demux_001_src4_channel), // .channel .src4_startofpacket (cmd_xbar_demux_001_src4_startofpacket), // .startofpacket .src4_endofpacket (cmd_xbar_demux_001_src4_endofpacket), // .endofpacket .src5_ready (cmd_xbar_demux_001_src5_ready), // src5.ready .src5_valid (cmd_xbar_demux_001_src5_valid), // .valid .src5_data (cmd_xbar_demux_001_src5_data), // .data .src5_channel (cmd_xbar_demux_001_src5_channel), // .channel .src5_startofpacket (cmd_xbar_demux_001_src5_startofpacket), // .startofpacket .src5_endofpacket (cmd_xbar_demux_001_src5_endofpacket), // .endofpacket .src6_ready (cmd_xbar_demux_001_src6_ready), // src6.ready .src6_valid (cmd_xbar_demux_001_src6_valid), // .valid .src6_data (cmd_xbar_demux_001_src6_data), // .data .src6_channel (cmd_xbar_demux_001_src6_channel), // .channel .src6_startofpacket (cmd_xbar_demux_001_src6_startofpacket), // .startofpacket .src6_endofpacket (cmd_xbar_demux_001_src6_endofpacket), // .endofpacket .src7_ready (cmd_xbar_demux_001_src7_ready), // src7.ready .src7_valid (cmd_xbar_demux_001_src7_valid), // .valid .src7_data (cmd_xbar_demux_001_src7_data), // .data .src7_channel (cmd_xbar_demux_001_src7_channel), // .channel .src7_startofpacket (cmd_xbar_demux_001_src7_startofpacket), // .startofpacket .src7_endofpacket (cmd_xbar_demux_001_src7_endofpacket), // .endofpacket .src8_ready (cmd_xbar_demux_001_src8_ready), // src8.ready .src8_valid (cmd_xbar_demux_001_src8_valid), // .valid .src8_data (cmd_xbar_demux_001_src8_data), // .data .src8_channel (cmd_xbar_demux_001_src8_channel), // .channel .src8_startofpacket (cmd_xbar_demux_001_src8_startofpacket), // .startofpacket .src8_endofpacket (cmd_xbar_demux_001_src8_endofpacket), // .endofpacket .src9_ready (cmd_xbar_demux_001_src9_ready), // src9.ready .src9_valid (cmd_xbar_demux_001_src9_valid), // .valid .src9_data (cmd_xbar_demux_001_src9_data), // .data .src9_channel (cmd_xbar_demux_001_src9_channel), // .channel .src9_startofpacket (cmd_xbar_demux_001_src9_startofpacket), // .startofpacket .src9_endofpacket (cmd_xbar_demux_001_src9_endofpacket), // .endofpacket .src10_ready (cmd_xbar_demux_001_src10_ready), // src10.ready .src10_valid (cmd_xbar_demux_001_src10_valid), // .valid .src10_data (cmd_xbar_demux_001_src10_data), // .data .src10_channel (cmd_xbar_demux_001_src10_channel), // .channel .src10_startofpacket (cmd_xbar_demux_001_src10_startofpacket), // .startofpacket .src10_endofpacket (cmd_xbar_demux_001_src10_endofpacket), // .endofpacket .src11_ready (cmd_xbar_demux_001_src11_ready), // src11.ready .src11_valid (cmd_xbar_demux_001_src11_valid), // .valid .src11_data (cmd_xbar_demux_001_src11_data), // .data .src11_channel (cmd_xbar_demux_001_src11_channel), // .channel .src11_startofpacket (cmd_xbar_demux_001_src11_startofpacket), // .startofpacket .src11_endofpacket (cmd_xbar_demux_001_src11_endofpacket), // .endofpacket .src12_ready (cmd_xbar_demux_001_src12_ready), // src12.ready .src12_valid (cmd_xbar_demux_001_src12_valid), // .valid .src12_data (cmd_xbar_demux_001_src12_data), // .data .src12_channel (cmd_xbar_demux_001_src12_channel), // .channel .src12_startofpacket (cmd_xbar_demux_001_src12_startofpacket), // .startofpacket .src12_endofpacket (cmd_xbar_demux_001_src12_endofpacket) // .endofpacket ); tracking_camera_system_cmd_xbar_mux cmd_xbar_mux ( .clk (altpll_0_c1_clk), // clk.clk .reset (rst_controller_reset_out_reset), // clk_reset.reset .src_ready (cmd_xbar_mux_src_ready), // src.ready .src_valid (cmd_xbar_mux_src_valid), // .valid .src_data (cmd_xbar_mux_src_data), // .data .src_channel (cmd_xbar_mux_src_channel), // .channel .src_startofpacket (cmd_xbar_mux_src_startofpacket), // .startofpacket .src_endofpacket (cmd_xbar_mux_src_endofpacket), // .endofpacket .sink0_ready (cmd_xbar_demux_src0_ready), // sink0.ready .sink0_valid (cmd_xbar_demux_src0_valid), // .valid .sink0_channel (cmd_xbar_demux_src0_channel), // .channel .sink0_data (cmd_xbar_demux_src0_data), // .data .sink0_startofpacket (cmd_xbar_demux_src0_startofpacket), // .startofpacket .sink0_endofpacket (cmd_xbar_demux_src0_endofpacket), // .endofpacket .sink1_ready (cmd_xbar_demux_001_src0_ready), // sink1.ready .sink1_valid (cmd_xbar_demux_001_src0_valid), // .valid .sink1_channel (cmd_xbar_demux_001_src0_channel), // .channel .sink1_data (cmd_xbar_demux_001_src0_data), // .data .sink1_startofpacket (cmd_xbar_demux_001_src0_startofpacket), // .startofpacket .sink1_endofpacket (cmd_xbar_demux_001_src0_endofpacket) // .endofpacket ); tracking_camera_system_cmd_xbar_mux cmd_xbar_mux_001 ( .clk (altpll_0_c1_clk), // clk.clk .reset (rst_controller_reset_out_reset), // clk_reset.reset .src_ready (cmd_xbar_mux_001_src_ready), // src.ready .src_valid (cmd_xbar_mux_001_src_valid), // .valid .src_data (cmd_xbar_mux_001_src_data), // .data .src_channel (cmd_xbar_mux_001_src_channel), // .channel .src_startofpacket (cmd_xbar_mux_001_src_startofpacket), // .startofpacket .src_endofpacket (cmd_xbar_mux_001_src_endofpacket), // .endofpacket .sink0_ready (cmd_xbar_demux_src1_ready), // sink0.ready .sink0_valid (cmd_xbar_demux_src1_valid), // .valid .sink0_channel (cmd_xbar_demux_src1_channel), // .channel .sink0_data (cmd_xbar_demux_src1_data), // .data .sink0_startofpacket (cmd_xbar_demux_src1_startofpacket), // .startofpacket .sink0_endofpacket (cmd_xbar_demux_src1_endofpacket), // .endofpacket .sink1_ready (cmd_xbar_demux_001_src1_ready), // sink1.ready .sink1_valid (cmd_xbar_demux_001_src1_valid), // .valid .sink1_channel (cmd_xbar_demux_001_src1_channel), // .channel .sink1_data (cmd_xbar_demux_001_src1_data), // .data .sink1_startofpacket (cmd_xbar_demux_001_src1_startofpacket), // .startofpacket .sink1_endofpacket (cmd_xbar_demux_001_src1_endofpacket) // .endofpacket ); tracking_camera_system_cmd_xbar_mux cmd_xbar_mux_002 ( .clk (altpll_0_c1_clk), // clk.clk .reset (rst_controller_reset_out_reset), // clk_reset.reset .src_ready (cmd_xbar_mux_002_src_ready), // src.ready .src_valid (cmd_xbar_mux_002_src_valid), // .valid .src_data (cmd_xbar_mux_002_src_data), // .data .src_channel (cmd_xbar_mux_002_src_channel), // .channel .src_startofpacket (cmd_xbar_mux_002_src_startofpacket), // .startofpacket .src_endofpacket (cmd_xbar_mux_002_src_endofpacket), // .endofpacket .sink0_ready (cmd_xbar_demux_src2_ready), // sink0.ready .sink0_valid (cmd_xbar_demux_src2_valid), // .valid .sink0_channel (cmd_xbar_demux_src2_channel), // .channel .sink0_data (cmd_xbar_demux_src2_data), // .data .sink0_startofpacket (cmd_xbar_demux_src2_startofpacket), // .startofpacket .sink0_endofpacket (cmd_xbar_demux_src2_endofpacket), // .endofpacket .sink1_ready (cmd_xbar_demux_001_src2_ready), // sink1.ready .sink1_valid (cmd_xbar_demux_001_src2_valid), // .valid .sink1_channel (cmd_xbar_demux_001_src2_channel), // .channel .sink1_data (cmd_xbar_demux_001_src2_data), // .data .sink1_startofpacket (cmd_xbar_demux_001_src2_startofpacket), // .startofpacket .sink1_endofpacket (cmd_xbar_demux_001_src2_endofpacket) // .endofpacket ); tracking_camera_system_cmd_xbar_mux cmd_xbar_mux_003 ( .clk (altpll_0_c1_clk), // clk.clk .reset (rst_controller_reset_out_reset), // clk_reset.reset .src_ready (cmd_xbar_mux_003_src_ready), // src.ready .src_valid (cmd_xbar_mux_003_src_valid), // .valid .src_data (cmd_xbar_mux_003_src_data), // .data .src_channel (cmd_xbar_mux_003_src_channel), // .channel .src_startofpacket (cmd_xbar_mux_003_src_startofpacket), // .startofpacket .src_endofpacket (cmd_xbar_mux_003_src_endofpacket), // .endofpacket .sink0_ready (cmd_xbar_demux_src3_ready), // sink0.ready .sink0_valid (cmd_xbar_demux_src3_valid), // .valid .sink0_channel (cmd_xbar_demux_src3_channel), // .channel .sink0_data (cmd_xbar_demux_src3_data), // .data .sink0_startofpacket (cmd_xbar_demux_src3_startofpacket), // .startofpacket .sink0_endofpacket (cmd_xbar_demux_src3_endofpacket), // .endofpacket .sink1_ready (cmd_xbar_demux_001_src3_ready), // sink1.ready .sink1_valid (cmd_xbar_demux_001_src3_valid), // .valid .sink1_channel (cmd_xbar_demux_001_src3_channel), // .channel .sink1_data (cmd_xbar_demux_001_src3_data), // .data .sink1_startofpacket (cmd_xbar_demux_001_src3_startofpacket), // .startofpacket .sink1_endofpacket (cmd_xbar_demux_001_src3_endofpacket) // .endofpacket ); tracking_camera_system_rsp_xbar_demux rsp_xbar_demux ( .clk (altpll_0_c1_clk), // clk.clk .reset (rst_controller_reset_out_reset), // clk_reset.reset .sink_ready (id_router_src_ready), // sink.ready .sink_channel (id_router_src_channel), // .channel .sink_data (id_router_src_data), // .data .sink_startofpacket (id_router_src_startofpacket), // .startofpacket .sink_endofpacket (id_router_src_endofpacket), // .endofpacket .sink_valid (id_router_src_valid), // .valid .src0_ready (rsp_xbar_demux_src0_ready), // src0.ready .src0_valid (rsp_xbar_demux_src0_valid), // .valid .src0_data (rsp_xbar_demux_src0_data), // .data .src0_channel (rsp_xbar_demux_src0_channel), // .channel .src0_startofpacket (rsp_xbar_demux_src0_startofpacket), // .startofpacket .src0_endofpacket (rsp_xbar_demux_src0_endofpacket), // .endofpacket .src1_ready (rsp_xbar_demux_src1_ready), // src1.ready .src1_valid (rsp_xbar_demux_src1_valid), // .valid .src1_data (rsp_xbar_demux_src1_data), // .data .src1_channel (rsp_xbar_demux_src1_channel), // .channel .src1_startofpacket (rsp_xbar_demux_src1_startofpacket), // .startofpacket .src1_endofpacket (rsp_xbar_demux_src1_endofpacket) // .endofpacket ); tracking_camera_system_rsp_xbar_demux rsp_xbar_demux_001 ( .clk (altpll_0_c1_clk), // clk.clk .reset (rst_controller_reset_out_reset), // clk_reset.reset .sink_ready (id_router_001_src_ready), // sink.ready .sink_channel (id_router_001_src_channel), // .channel .sink_data (id_router_001_src_data), // .data .sink_startofpacket (id_router_001_src_startofpacket), // .startofpacket .sink_endofpacket (id_router_001_src_endofpacket), // .endofpacket .sink_valid (id_router_001_src_valid), // .valid .src0_ready (rsp_xbar_demux_001_src0_ready), // src0.ready .src0_valid (rsp_xbar_demux_001_src0_valid), // .valid .src0_data (rsp_xbar_demux_001_src0_data), // .data .src0_channel (rsp_xbar_demux_001_src0_channel), // .channel .src0_startofpacket (rsp_xbar_demux_001_src0_startofpacket), // .startofpacket .src0_endofpacket (rsp_xbar_demux_001_src0_endofpacket), // .endofpacket .src1_ready (rsp_xbar_demux_001_src1_ready), // src1.ready .src1_valid (rsp_xbar_demux_001_src1_valid), // .valid .src1_data (rsp_xbar_demux_001_src1_data), // .data .src1_channel (rsp_xbar_demux_001_src1_channel), // .channel .src1_startofpacket (rsp_xbar_demux_001_src1_startofpacket), // .startofpacket .src1_endofpacket (rsp_xbar_demux_001_src1_endofpacket) // .endofpacket ); tracking_camera_system_rsp_xbar_demux rsp_xbar_demux_002 ( .clk (altpll_0_c1_clk), // clk.clk .reset (rst_controller_reset_out_reset), // clk_reset.reset .sink_ready (width_adapter_001_src_ready), // sink.ready .sink_channel (width_adapter_001_src_channel), // .channel .sink_data (width_adapter_001_src_data), // .data .sink_startofpacket (width_adapter_001_src_startofpacket), // .startofpacket .sink_endofpacket (width_adapter_001_src_endofpacket), // .endofpacket .sink_valid (width_adapter_001_src_valid), // .valid .src0_ready (rsp_xbar_demux_002_src0_ready), // src0.ready .src0_valid (rsp_xbar_demux_002_src0_valid), // .valid .src0_data (rsp_xbar_demux_002_src0_data), // .data .src0_channel (rsp_xbar_demux_002_src0_channel), // .channel .src0_startofpacket (rsp_xbar_demux_002_src0_startofpacket), // .startofpacket .src0_endofpacket (rsp_xbar_demux_002_src0_endofpacket), // .endofpacket .src1_ready (rsp_xbar_demux_002_src1_ready), // src1.ready .src1_valid (rsp_xbar_demux_002_src1_valid), // .valid .src1_data (rsp_xbar_demux_002_src1_data), // .data .src1_channel (rsp_xbar_demux_002_src1_channel), // .channel .src1_startofpacket (rsp_xbar_demux_002_src1_startofpacket), // .startofpacket .src1_endofpacket (rsp_xbar_demux_002_src1_endofpacket) // .endofpacket ); tracking_camera_system_rsp_xbar_demux rsp_xbar_demux_003 ( .clk (altpll_0_c1_clk), // clk.clk .reset (rst_controller_reset_out_reset), // clk_reset.reset .sink_ready (width_adapter_003_src_ready), // sink.ready .sink_channel (width_adapter_003_src_channel), // .channel .sink_data (width_adapter_003_src_data), // .data .sink_startofpacket (width_adapter_003_src_startofpacket), // .startofpacket .sink_endofpacket (width_adapter_003_src_endofpacket), // .endofpacket .sink_valid (width_adapter_003_src_valid), // .valid .src0_ready (rsp_xbar_demux_003_src0_ready), // src0.ready .src0_valid (rsp_xbar_demux_003_src0_valid), // .valid .src0_data (rsp_xbar_demux_003_src0_data), // .data .src0_channel (rsp_xbar_demux_003_src0_channel), // .channel .src0_startofpacket (rsp_xbar_demux_003_src0_startofpacket), // .startofpacket .src0_endofpacket (rsp_xbar_demux_003_src0_endofpacket), // .endofpacket .src1_ready (rsp_xbar_demux_003_src1_ready), // src1.ready .src1_valid (rsp_xbar_demux_003_src1_valid), // .valid .src1_data (rsp_xbar_demux_003_src1_data), // .data .src1_channel (rsp_xbar_demux_003_src1_channel), // .channel .src1_startofpacket (rsp_xbar_demux_003_src1_startofpacket), // .startofpacket .src1_endofpacket (rsp_xbar_demux_003_src1_endofpacket) // .endofpacket ); tracking_camera_system_rsp_xbar_demux_004 rsp_xbar_demux_004 ( .clk (clk_clk), // clk.clk .reset (rst_controller_001_reset_out_reset), // clk_reset.reset .sink_ready (id_router_004_src_ready), // sink.ready .sink_channel (id_router_004_src_channel), // .channel .sink_data (id_router_004_src_data), // .data .sink_startofpacket (id_router_004_src_startofpacket), // .startofpacket .sink_endofpacket (id_router_004_src_endofpacket), // .endofpacket .sink_valid (id_router_004_src_valid), // .valid .src0_ready (rsp_xbar_demux_004_src0_ready), // src0.ready .src0_valid (rsp_xbar_demux_004_src0_valid), // .valid .src0_data (rsp_xbar_demux_004_src0_data), // .data .src0_channel (rsp_xbar_demux_004_src0_channel), // .channel .src0_startofpacket (rsp_xbar_demux_004_src0_startofpacket), // .startofpacket .src0_endofpacket (rsp_xbar_demux_004_src0_endofpacket) // .endofpacket ); tracking_camera_system_rsp_xbar_demux_004 rsp_xbar_demux_005 ( .clk (altpll_0_c1_clk), // clk.clk .reset (rst_controller_reset_out_reset), // clk_reset.reset .sink_ready (id_router_005_src_ready), // sink.ready .sink_channel (id_router_005_src_channel), // .channel .sink_data (id_router_005_src_data), // .data .sink_startofpacket (id_router_005_src_startofpacket), // .startofpacket .sink_endofpacket (id_router_005_src_endofpacket), // .endofpacket .sink_valid (id_router_005_src_valid), // .valid .src0_ready (rsp_xbar_demux_005_src0_ready), // src0.ready .src0_valid (rsp_xbar_demux_005_src0_valid), // .valid .src0_data (rsp_xbar_demux_005_src0_data), // .data .src0_channel (rsp_xbar_demux_005_src0_channel), // .channel .src0_startofpacket (rsp_xbar_demux_005_src0_startofpacket), // .startofpacket .src0_endofpacket (rsp_xbar_demux_005_src0_endofpacket) // .endofpacket ); tracking_camera_system_rsp_xbar_demux_004 rsp_xbar_demux_006 ( .clk (altpll_0_c1_clk), // clk.clk .reset (rst_controller_reset_out_reset), // clk_reset.reset .sink_ready (id_router_006_src_ready), // sink.ready .sink_channel (id_router_006_src_channel), // .channel .sink_data (id_router_006_src_data), // .data .sink_startofpacket (id_router_006_src_startofpacket), // .startofpacket .sink_endofpacket (id_router_006_src_endofpacket), // .endofpacket .sink_valid (id_router_006_src_valid), // .valid .src0_ready (rsp_xbar_demux_006_src0_ready), // src0.ready .src0_valid (rsp_xbar_demux_006_src0_valid), // .valid .src0_data (rsp_xbar_demux_006_src0_data), // .data .src0_channel (rsp_xbar_demux_006_src0_channel), // .channel .src0_startofpacket (rsp_xbar_demux_006_src0_startofpacket), // .startofpacket .src0_endofpacket (rsp_xbar_demux_006_src0_endofpacket) // .endofpacket ); tracking_camera_system_rsp_xbar_demux_004 rsp_xbar_demux_007 ( .clk (altpll_0_c1_clk), // clk.clk .reset (rst_controller_reset_out_reset), // clk_reset.reset .sink_ready (id_router_007_src_ready), // sink.ready .sink_channel (id_router_007_src_channel), // .channel .sink_data (id_router_007_src_data), // .data .sink_startofpacket (id_router_007_src_startofpacket), // .startofpacket .sink_endofpacket (id_router_007_src_endofpacket), // .endofpacket .sink_valid (id_router_007_src_valid), // .valid .src0_ready (rsp_xbar_demux_007_src0_ready), // src0.ready .src0_valid (rsp_xbar_demux_007_src0_valid), // .valid .src0_data (rsp_xbar_demux_007_src0_data), // .data .src0_channel (rsp_xbar_demux_007_src0_channel), // .channel .src0_startofpacket (rsp_xbar_demux_007_src0_startofpacket), // .startofpacket .src0_endofpacket (rsp_xbar_demux_007_src0_endofpacket) // .endofpacket ); tracking_camera_system_rsp_xbar_demux_004 rsp_xbar_demux_008 ( .clk (altpll_0_c1_clk), // clk.clk .reset (rst_controller_reset_out_reset), // clk_reset.reset .sink_ready (width_adapter_005_src_ready), // sink.ready .sink_channel (width_adapter_005_src_channel), // .channel .sink_data (width_adapter_005_src_data), // .data .sink_startofpacket (width_adapter_005_src_startofpacket), // .startofpacket .sink_endofpacket (width_adapter_005_src_endofpacket), // .endofpacket .sink_valid (width_adapter_005_src_valid), // .valid .src0_ready (rsp_xbar_demux_008_src0_ready), // src0.ready .src0_valid (rsp_xbar_demux_008_src0_valid), // .valid .src0_data (rsp_xbar_demux_008_src0_data), // .data .src0_channel (rsp_xbar_demux_008_src0_channel), // .channel .src0_startofpacket (rsp_xbar_demux_008_src0_startofpacket), // .startofpacket .src0_endofpacket (rsp_xbar_demux_008_src0_endofpacket) // .endofpacket ); tracking_camera_system_rsp_xbar_demux_004 rsp_xbar_demux_009 ( .clk (altpll_0_c1_clk), // clk.clk .reset (rst_controller_reset_out_reset), // clk_reset.reset .sink_ready (id_router_009_src_ready), // sink.ready .sink_channel (id_router_009_src_channel), // .channel .sink_data (id_router_009_src_data), // .data .sink_startofpacket (id_router_009_src_startofpacket), // .startofpacket .sink_endofpacket (id_router_009_src_endofpacket), // .endofpacket .sink_valid (id_router_009_src_valid), // .valid .src0_ready (rsp_xbar_demux_009_src0_ready), // src0.ready .src0_valid (rsp_xbar_demux_009_src0_valid), // .valid .src0_data (rsp_xbar_demux_009_src0_data), // .data .src0_channel (rsp_xbar_demux_009_src0_channel), // .channel .src0_startofpacket (rsp_xbar_demux_009_src0_startofpacket), // .startofpacket .src0_endofpacket (rsp_xbar_demux_009_src0_endofpacket) // .endofpacket ); tracking_camera_system_rsp_xbar_demux_004 rsp_xbar_demux_010 ( .clk (altpll_0_c1_clk), // clk.clk .reset (rst_controller_reset_out_reset), // clk_reset.reset .sink_ready (id_router_010_src_ready), // sink.ready .sink_channel (id_router_010_src_channel), // .channel .sink_data (id_router_010_src_data), // .data .sink_startofpacket (id_router_010_src_startofpacket), // .startofpacket .sink_endofpacket (id_router_010_src_endofpacket), // .endofpacket .sink_valid (id_router_010_src_valid), // .valid .src0_ready (rsp_xbar_demux_010_src0_ready), // src0.ready .src0_valid (rsp_xbar_demux_010_src0_valid), // .valid .src0_data (rsp_xbar_demux_010_src0_data), // .data .src0_channel (rsp_xbar_demux_010_src0_channel), // .channel .src0_startofpacket (rsp_xbar_demux_010_src0_startofpacket), // .startofpacket .src0_endofpacket (rsp_xbar_demux_010_src0_endofpacket) // .endofpacket ); tracking_camera_system_rsp_xbar_demux_004 rsp_xbar_demux_011 ( .clk (altpll_0_c1_clk), // clk.clk .reset (rst_controller_reset_out_reset), // clk_reset.reset .sink_ready (id_router_011_src_ready), // sink.ready .sink_channel (id_router_011_src_channel), // .channel .sink_data (id_router_011_src_data), // .data .sink_startofpacket (id_router_011_src_startofpacket), // .startofpacket .sink_endofpacket (id_router_011_src_endofpacket), // .endofpacket .sink_valid (id_router_011_src_valid), // .valid .src0_ready (rsp_xbar_demux_011_src0_ready), // src0.ready .src0_valid (rsp_xbar_demux_011_src0_valid), // .valid .src0_data (rsp_xbar_demux_011_src0_data), // .data .src0_channel (rsp_xbar_demux_011_src0_channel), // .channel .src0_startofpacket (rsp_xbar_demux_011_src0_startofpacket), // .startofpacket .src0_endofpacket (rsp_xbar_demux_011_src0_endofpacket) // .endofpacket ); tracking_camera_system_rsp_xbar_demux_004 rsp_xbar_demux_012 ( .clk (altpll_0_c1_clk), // clk.clk .reset (rst_controller_reset_out_reset), // clk_reset.reset .sink_ready (id_router_012_src_ready), // sink.ready .sink_channel (id_router_012_src_channel), // .channel .sink_data (id_router_012_src_data), // .data .sink_startofpacket (id_router_012_src_startofpacket), // .startofpacket .sink_endofpacket (id_router_012_src_endofpacket), // .endofpacket .sink_valid (id_router_012_src_valid), // .valid .src0_ready (rsp_xbar_demux_012_src0_ready), // src0.ready .src0_valid (rsp_xbar_demux_012_src0_valid), // .valid .src0_data (rsp_xbar_demux_012_src0_data), // .data .src0_channel (rsp_xbar_demux_012_src0_channel), // .channel .src0_startofpacket (rsp_xbar_demux_012_src0_startofpacket), // .startofpacket .src0_endofpacket (rsp_xbar_demux_012_src0_endofpacket) // .endofpacket ); tracking_camera_system_rsp_xbar_mux rsp_xbar_mux ( .clk (altpll_0_c1_clk), // clk.clk .reset (rst_controller_reset_out_reset), // clk_reset.reset .src_ready (rsp_xbar_mux_src_ready), // src.ready .src_valid (rsp_xbar_mux_src_valid), // .valid .src_data (rsp_xbar_mux_src_data), // .data .src_channel (rsp_xbar_mux_src_channel), // .channel .src_startofpacket (rsp_xbar_mux_src_startofpacket), // .startofpacket .src_endofpacket (rsp_xbar_mux_src_endofpacket), // .endofpacket .sink0_ready (rsp_xbar_demux_src0_ready), // sink0.ready .sink0_valid (rsp_xbar_demux_src0_valid), // .valid .sink0_channel (rsp_xbar_demux_src0_channel), // .channel .sink0_data (rsp_xbar_demux_src0_data), // .data .sink0_startofpacket (rsp_xbar_demux_src0_startofpacket), // .startofpacket .sink0_endofpacket (rsp_xbar_demux_src0_endofpacket), // .endofpacket .sink1_ready (rsp_xbar_demux_001_src0_ready), // sink1.ready .sink1_valid (rsp_xbar_demux_001_src0_valid), // .valid .sink1_channel (rsp_xbar_demux_001_src0_channel), // .channel .sink1_data (rsp_xbar_demux_001_src0_data), // .data .sink1_startofpacket (rsp_xbar_demux_001_src0_startofpacket), // .startofpacket .sink1_endofpacket (rsp_xbar_demux_001_src0_endofpacket), // .endofpacket .sink2_ready (rsp_xbar_demux_002_src0_ready), // sink2.ready .sink2_valid (rsp_xbar_demux_002_src0_valid), // .valid .sink2_channel (rsp_xbar_demux_002_src0_channel), // .channel .sink2_data (rsp_xbar_demux_002_src0_data), // .data .sink2_startofpacket (rsp_xbar_demux_002_src0_startofpacket), // .startofpacket .sink2_endofpacket (rsp_xbar_demux_002_src0_endofpacket), // .endofpacket .sink3_ready (rsp_xbar_demux_003_src0_ready), // sink3.ready .sink3_valid (rsp_xbar_demux_003_src0_valid), // .valid .sink3_channel (rsp_xbar_demux_003_src0_channel), // .channel .sink3_data (rsp_xbar_demux_003_src0_data), // .data .sink3_startofpacket (rsp_xbar_demux_003_src0_startofpacket), // .startofpacket .sink3_endofpacket (rsp_xbar_demux_003_src0_endofpacket) // .endofpacket ); tracking_camera_system_rsp_xbar_mux_001 rsp_xbar_mux_001 ( .clk (altpll_0_c1_clk), // clk.clk .reset (rst_controller_reset_out_reset), // clk_reset.reset .src_ready (rsp_xbar_mux_001_src_ready), // src.ready .src_valid (rsp_xbar_mux_001_src_valid), // .valid .src_data (rsp_xbar_mux_001_src_data), // .data .src_channel (rsp_xbar_mux_001_src_channel), // .channel .src_startofpacket (rsp_xbar_mux_001_src_startofpacket), // .startofpacket .src_endofpacket (rsp_xbar_mux_001_src_endofpacket), // .endofpacket .sink0_ready (rsp_xbar_demux_src1_ready), // sink0.ready .sink0_valid (rsp_xbar_demux_src1_valid), // .valid .sink0_channel (rsp_xbar_demux_src1_channel), // .channel .sink0_data (rsp_xbar_demux_src1_data), // .data .sink0_startofpacket (rsp_xbar_demux_src1_startofpacket), // .startofpacket .sink0_endofpacket (rsp_xbar_demux_src1_endofpacket), // .endofpacket .sink1_ready (rsp_xbar_demux_001_src1_ready), // sink1.ready .sink1_valid (rsp_xbar_demux_001_src1_valid), // .valid .sink1_channel (rsp_xbar_demux_001_src1_channel), // .channel .sink1_data (rsp_xbar_demux_001_src1_data), // .data .sink1_startofpacket (rsp_xbar_demux_001_src1_startofpacket), // .startofpacket .sink1_endofpacket (rsp_xbar_demux_001_src1_endofpacket), // .endofpacket .sink2_ready (rsp_xbar_demux_002_src1_ready), // sink2.ready .sink2_valid (rsp_xbar_demux_002_src1_valid), // .valid .sink2_channel (rsp_xbar_demux_002_src1_channel), // .channel .sink2_data (rsp_xbar_demux_002_src1_data), // .data .sink2_startofpacket (rsp_xbar_demux_002_src1_startofpacket), // .startofpacket .sink2_endofpacket (rsp_xbar_demux_002_src1_endofpacket), // .endofpacket .sink3_ready (rsp_xbar_demux_003_src1_ready), // sink3.ready .sink3_valid (rsp_xbar_demux_003_src1_valid), // .valid .sink3_channel (rsp_xbar_demux_003_src1_channel), // .channel .sink3_data (rsp_xbar_demux_003_src1_data), // .data .sink3_startofpacket (rsp_xbar_demux_003_src1_startofpacket), // .startofpacket .sink3_endofpacket (rsp_xbar_demux_003_src1_endofpacket), // .endofpacket .sink4_ready (crosser_001_out_ready), // sink4.ready .sink4_valid (crosser_001_out_valid), // .valid .sink4_channel (crosser_001_out_channel), // .channel .sink4_data (crosser_001_out_data), // .data .sink4_startofpacket (crosser_001_out_startofpacket), // .startofpacket .sink4_endofpacket (crosser_001_out_endofpacket), // .endofpacket .sink5_ready (rsp_xbar_demux_005_src0_ready), // sink5.ready .sink5_valid (rsp_xbar_demux_005_src0_valid), // .valid .sink5_channel (rsp_xbar_demux_005_src0_channel), // .channel .sink5_data (rsp_xbar_demux_005_src0_data), // .data .sink5_startofpacket (rsp_xbar_demux_005_src0_startofpacket), // .startofpacket .sink5_endofpacket (rsp_xbar_demux_005_src0_endofpacket), // .endofpacket .sink6_ready (rsp_xbar_demux_006_src0_ready), // sink6.ready .sink6_valid (rsp_xbar_demux_006_src0_valid), // .valid .sink6_channel (rsp_xbar_demux_006_src0_channel), // .channel .sink6_data (rsp_xbar_demux_006_src0_data), // .data .sink6_startofpacket (rsp_xbar_demux_006_src0_startofpacket), // .startofpacket .sink6_endofpacket (rsp_xbar_demux_006_src0_endofpacket), // .endofpacket .sink7_ready (rsp_xbar_demux_007_src0_ready), // sink7.ready .sink7_valid (rsp_xbar_demux_007_src0_valid), // .valid .sink7_channel (rsp_xbar_demux_007_src0_channel), // .channel .sink7_data (rsp_xbar_demux_007_src0_data), // .data .sink7_startofpacket (rsp_xbar_demux_007_src0_startofpacket), // .startofpacket .sink7_endofpacket (rsp_xbar_demux_007_src0_endofpacket), // .endofpacket .sink8_ready (rsp_xbar_demux_008_src0_ready), // sink8.ready .sink8_valid (rsp_xbar_demux_008_src0_valid), // .valid .sink8_channel (rsp_xbar_demux_008_src0_channel), // .channel .sink8_data (rsp_xbar_demux_008_src0_data), // .data .sink8_startofpacket (rsp_xbar_demux_008_src0_startofpacket), // .startofpacket .sink8_endofpacket (rsp_xbar_demux_008_src0_endofpacket), // .endofpacket .sink9_ready (rsp_xbar_demux_009_src0_ready), // sink9.ready .sink9_valid (rsp_xbar_demux_009_src0_valid), // .valid .sink9_channel (rsp_xbar_demux_009_src0_channel), // .channel .sink9_data (rsp_xbar_demux_009_src0_data), // .data .sink9_startofpacket (rsp_xbar_demux_009_src0_startofpacket), // .startofpacket .sink9_endofpacket (rsp_xbar_demux_009_src0_endofpacket), // .endofpacket .sink10_ready (rsp_xbar_demux_010_src0_ready), // sink10.ready .sink10_valid (rsp_xbar_demux_010_src0_valid), // .valid .sink10_channel (rsp_xbar_demux_010_src0_channel), // .channel .sink10_data (rsp_xbar_demux_010_src0_data), // .data .sink10_startofpacket (rsp_xbar_demux_010_src0_startofpacket), // .startofpacket .sink10_endofpacket (rsp_xbar_demux_010_src0_endofpacket), // .endofpacket .sink11_ready (rsp_xbar_demux_011_src0_ready), // sink11.ready .sink11_valid (rsp_xbar_demux_011_src0_valid), // .valid .sink11_channel (rsp_xbar_demux_011_src0_channel), // .channel .sink11_data (rsp_xbar_demux_011_src0_data), // .data .sink11_startofpacket (rsp_xbar_demux_011_src0_startofpacket), // .startofpacket .sink11_endofpacket (rsp_xbar_demux_011_src0_endofpacket), // .endofpacket .sink12_ready (rsp_xbar_demux_012_src0_ready), // sink12.ready .sink12_valid (rsp_xbar_demux_012_src0_valid), // .valid .sink12_channel (rsp_xbar_demux_012_src0_channel), // .channel .sink12_data (rsp_xbar_demux_012_src0_data), // .data .sink12_startofpacket (rsp_xbar_demux_012_src0_startofpacket), // .startofpacket .sink12_endofpacket (rsp_xbar_demux_012_src0_endofpacket) // .endofpacket ); altera_merlin_width_adapter #( .IN_PKT_ADDR_H (60), .IN_PKT_ADDR_L (36), .IN_PKT_DATA_H (31), .IN_PKT_DATA_L (0), .IN_PKT_BYTEEN_H (35), .IN_PKT_BYTEEN_L (32), .IN_PKT_BYTE_CNT_H (69), .IN_PKT_BYTE_CNT_L (67), .IN_PKT_TRANS_COMPRESSED_READ (61), .IN_PKT_BURSTWRAP_H (72), .IN_PKT_BURSTWRAP_L (70), .IN_PKT_BURST_SIZE_H (75), .IN_PKT_BURST_SIZE_L (73), .IN_PKT_RESPONSE_STATUS_H (99), .IN_PKT_RESPONSE_STATUS_L (98), .IN_PKT_TRANS_EXCLUSIVE (66), .IN_PKT_BURST_TYPE_H (77), .IN_PKT_BURST_TYPE_L (76), .IN_ST_DATA_W (100), .OUT_PKT_ADDR_H (42), .OUT_PKT_ADDR_L (18), .OUT_PKT_DATA_H (15), .OUT_PKT_DATA_L (0), .OUT_PKT_BYTEEN_H (17), .OUT_PKT_BYTEEN_L (16), .OUT_PKT_BYTE_CNT_H (51), .OUT_PKT_BYTE_CNT_L (49), .OUT_PKT_TRANS_COMPRESSED_READ (43), .OUT_PKT_BURST_SIZE_H (57), .OUT_PKT_BURST_SIZE_L (55), .OUT_PKT_RESPONSE_STATUS_H (81), .OUT_PKT_RESPONSE_STATUS_L (80), .OUT_PKT_TRANS_EXCLUSIVE (48), .OUT_PKT_BURST_TYPE_H (59), .OUT_PKT_BURST_TYPE_L (58), .OUT_ST_DATA_W (82), .ST_CHANNEL_W (13), .OPTIMIZE_FOR_RSP (0) ) width_adapter ( .clk (altpll_0_c1_clk), // clk.clk .reset (rst_controller_reset_out_reset), // clk_reset.reset .in_valid (cmd_xbar_mux_002_src_valid), // sink.valid .in_channel (cmd_xbar_mux_002_src_channel), // .channel .in_startofpacket (cmd_xbar_mux_002_src_startofpacket), // .startofpacket .in_endofpacket (cmd_xbar_mux_002_src_endofpacket), // .endofpacket .in_ready (cmd_xbar_mux_002_src_ready), // .ready .in_data (cmd_xbar_mux_002_src_data), // .data .out_endofpacket (width_adapter_src_endofpacket), // src.endofpacket .out_data (width_adapter_src_data), // .data .out_channel (width_adapter_src_channel), // .channel .out_valid (width_adapter_src_valid), // .valid .out_ready (width_adapter_src_ready), // .ready .out_startofpacket (width_adapter_src_startofpacket), // .startofpacket .in_command_size_data (3'b000) // (terminated) ); altera_merlin_width_adapter #( .IN_PKT_ADDR_H (42), .IN_PKT_ADDR_L (18), .IN_PKT_DATA_H (15), .IN_PKT_DATA_L (0), .IN_PKT_BYTEEN_H (17), .IN_PKT_BYTEEN_L (16), .IN_PKT_BYTE_CNT_H (51), .IN_PKT_BYTE_CNT_L (49), .IN_PKT_TRANS_COMPRESSED_READ (43), .IN_PKT_BURSTWRAP_H (54), .IN_PKT_BURSTWRAP_L (52), .IN_PKT_BURST_SIZE_H (57), .IN_PKT_BURST_SIZE_L (55), .IN_PKT_RESPONSE_STATUS_H (81), .IN_PKT_RESPONSE_STATUS_L (80), .IN_PKT_TRANS_EXCLUSIVE (48), .IN_PKT_BURST_TYPE_H (59), .IN_PKT_BURST_TYPE_L (58), .IN_ST_DATA_W (82), .OUT_PKT_ADDR_H (60), .OUT_PKT_ADDR_L (36), .OUT_PKT_DATA_H (31), .OUT_PKT_DATA_L (0), .OUT_PKT_BYTEEN_H (35), .OUT_PKT_BYTEEN_L (32), .OUT_PKT_BYTE_CNT_H (69), .OUT_PKT_BYTE_CNT_L (67), .OUT_PKT_TRANS_COMPRESSED_READ (61), .OUT_PKT_BURST_SIZE_H (75), .OUT_PKT_BURST_SIZE_L (73), .OUT_PKT_RESPONSE_STATUS_H (99), .OUT_PKT_RESPONSE_STATUS_L (98), .OUT_PKT_TRANS_EXCLUSIVE (66), .OUT_PKT_BURST_TYPE_H (77), .OUT_PKT_BURST_TYPE_L (76), .OUT_ST_DATA_W (100), .ST_CHANNEL_W (13), .OPTIMIZE_FOR_RSP (1) ) width_adapter_001 ( .clk (altpll_0_c1_clk), // clk.clk .reset (rst_controller_reset_out_reset), // clk_reset.reset .in_valid (id_router_002_src_valid), // sink.valid .in_channel (id_router_002_src_channel), // .channel .in_startofpacket (id_router_002_src_startofpacket), // .startofpacket .in_endofpacket (id_router_002_src_endofpacket), // .endofpacket .in_ready (id_router_002_src_ready), // .ready .in_data (id_router_002_src_data), // .data .out_endofpacket (width_adapter_001_src_endofpacket), // src.endofpacket .out_data (width_adapter_001_src_data), // .data .out_channel (width_adapter_001_src_channel), // .channel .out_valid (width_adapter_001_src_valid), // .valid .out_ready (width_adapter_001_src_ready), // .ready .out_startofpacket (width_adapter_001_src_startofpacket), // .startofpacket .in_command_size_data (3'b000) // (terminated) ); altera_merlin_width_adapter #( .IN_PKT_ADDR_H (60), .IN_PKT_ADDR_L (36), .IN_PKT_DATA_H (31), .IN_PKT_DATA_L (0), .IN_PKT_BYTEEN_H (35), .IN_PKT_BYTEEN_L (32), .IN_PKT_BYTE_CNT_H (69), .IN_PKT_BYTE_CNT_L (67), .IN_PKT_TRANS_COMPRESSED_READ (61), .IN_PKT_BURSTWRAP_H (72), .IN_PKT_BURSTWRAP_L (70), .IN_PKT_BURST_SIZE_H (75), .IN_PKT_BURST_SIZE_L (73), .IN_PKT_RESPONSE_STATUS_H (99), .IN_PKT_RESPONSE_STATUS_L (98), .IN_PKT_TRANS_EXCLUSIVE (66), .IN_PKT_BURST_TYPE_H (77), .IN_PKT_BURST_TYPE_L (76), .IN_ST_DATA_W (100), .OUT_PKT_ADDR_H (42), .OUT_PKT_ADDR_L (18), .OUT_PKT_DATA_H (15), .OUT_PKT_DATA_L (0), .OUT_PKT_BYTEEN_H (17), .OUT_PKT_BYTEEN_L (16), .OUT_PKT_BYTE_CNT_H (51), .OUT_PKT_BYTE_CNT_L (49), .OUT_PKT_TRANS_COMPRESSED_READ (43), .OUT_PKT_BURST_SIZE_H (57), .OUT_PKT_BURST_SIZE_L (55), .OUT_PKT_RESPONSE_STATUS_H (81), .OUT_PKT_RESPONSE_STATUS_L (80), .OUT_PKT_TRANS_EXCLUSIVE (48), .OUT_PKT_BURST_TYPE_H (59), .OUT_PKT_BURST_TYPE_L (58), .OUT_ST_DATA_W (82), .ST_CHANNEL_W (13), .OPTIMIZE_FOR_RSP (0) ) width_adapter_002 ( .clk (altpll_0_c1_clk), // clk.clk .reset (rst_controller_reset_out_reset), // clk_reset.reset .in_valid (cmd_xbar_mux_003_src_valid), // sink.valid .in_channel (cmd_xbar_mux_003_src_channel), // .channel .in_startofpacket (cmd_xbar_mux_003_src_startofpacket), // .startofpacket .in_endofpacket (cmd_xbar_mux_003_src_endofpacket), // .endofpacket .in_ready (cmd_xbar_mux_003_src_ready), // .ready .in_data (cmd_xbar_mux_003_src_data), // .data .out_endofpacket (width_adapter_002_src_endofpacket), // src.endofpacket .out_data (width_adapter_002_src_data), // .data .out_channel (width_adapter_002_src_channel), // .channel .out_valid (width_adapter_002_src_valid), // .valid .out_ready (width_adapter_002_src_ready), // .ready .out_startofpacket (width_adapter_002_src_startofpacket), // .startofpacket .in_command_size_data (3'b000) // (terminated) ); altera_merlin_width_adapter #( .IN_PKT_ADDR_H (42), .IN_PKT_ADDR_L (18), .IN_PKT_DATA_H (15), .IN_PKT_DATA_L (0), .IN_PKT_BYTEEN_H (17), .IN_PKT_BYTEEN_L (16), .IN_PKT_BYTE_CNT_H (51), .IN_PKT_BYTE_CNT_L (49), .IN_PKT_TRANS_COMPRESSED_READ (43), .IN_PKT_BURSTWRAP_H (54), .IN_PKT_BURSTWRAP_L (52), .IN_PKT_BURST_SIZE_H (57), .IN_PKT_BURST_SIZE_L (55), .IN_PKT_RESPONSE_STATUS_H (81), .IN_PKT_RESPONSE_STATUS_L (80), .IN_PKT_TRANS_EXCLUSIVE (48), .IN_PKT_BURST_TYPE_H (59), .IN_PKT_BURST_TYPE_L (58), .IN_ST_DATA_W (82), .OUT_PKT_ADDR_H (60), .OUT_PKT_ADDR_L (36), .OUT_PKT_DATA_H (31), .OUT_PKT_DATA_L (0), .OUT_PKT_BYTEEN_H (35), .OUT_PKT_BYTEEN_L (32), .OUT_PKT_BYTE_CNT_H (69), .OUT_PKT_BYTE_CNT_L (67), .OUT_PKT_TRANS_COMPRESSED_READ (61), .OUT_PKT_BURST_SIZE_H (75), .OUT_PKT_BURST_SIZE_L (73), .OUT_PKT_RESPONSE_STATUS_H (99), .OUT_PKT_RESPONSE_STATUS_L (98), .OUT_PKT_TRANS_EXCLUSIVE (66), .OUT_PKT_BURST_TYPE_H (77), .OUT_PKT_BURST_TYPE_L (76), .OUT_ST_DATA_W (100), .ST_CHANNEL_W (13), .OPTIMIZE_FOR_RSP (1) ) width_adapter_003 ( .clk (altpll_0_c1_clk), // clk.clk .reset (rst_controller_reset_out_reset), // clk_reset.reset .in_valid (id_router_003_src_valid), // sink.valid .in_channel (id_router_003_src_channel), // .channel .in_startofpacket (id_router_003_src_startofpacket), // .startofpacket .in_endofpacket (id_router_003_src_endofpacket), // .endofpacket .in_ready (id_router_003_src_ready), // .ready .in_data (id_router_003_src_data), // .data .out_endofpacket (width_adapter_003_src_endofpacket), // src.endofpacket .out_data (width_adapter_003_src_data), // .data .out_channel (width_adapter_003_src_channel), // .channel .out_valid (width_adapter_003_src_valid), // .valid .out_ready (width_adapter_003_src_ready), // .ready .out_startofpacket (width_adapter_003_src_startofpacket), // .startofpacket .in_command_size_data (3'b000) // (terminated) ); altera_merlin_width_adapter #( .IN_PKT_ADDR_H (60), .IN_PKT_ADDR_L (36), .IN_PKT_DATA_H (31), .IN_PKT_DATA_L (0), .IN_PKT_BYTEEN_H (35), .IN_PKT_BYTEEN_L (32), .IN_PKT_BYTE_CNT_H (69), .IN_PKT_BYTE_CNT_L (67), .IN_PKT_TRANS_COMPRESSED_READ (61), .IN_PKT_BURSTWRAP_H (72), .IN_PKT_BURSTWRAP_L (70), .IN_PKT_BURST_SIZE_H (75), .IN_PKT_BURST_SIZE_L (73), .IN_PKT_RESPONSE_STATUS_H (99), .IN_PKT_RESPONSE_STATUS_L (98), .IN_PKT_TRANS_EXCLUSIVE (66), .IN_PKT_BURST_TYPE_H (77), .IN_PKT_BURST_TYPE_L (76), .IN_ST_DATA_W (100), .OUT_PKT_ADDR_H (33), .OUT_PKT_ADDR_L (9), .OUT_PKT_DATA_H (7), .OUT_PKT_DATA_L (0), .OUT_PKT_BYTEEN_H (8), .OUT_PKT_BYTEEN_L (8), .OUT_PKT_BYTE_CNT_H (42), .OUT_PKT_BYTE_CNT_L (40), .OUT_PKT_TRANS_COMPRESSED_READ (34), .OUT_PKT_BURST_SIZE_H (48), .OUT_PKT_BURST_SIZE_L (46), .OUT_PKT_RESPONSE_STATUS_H (72), .OUT_PKT_RESPONSE_STATUS_L (71), .OUT_PKT_TRANS_EXCLUSIVE (39), .OUT_PKT_BURST_TYPE_H (50), .OUT_PKT_BURST_TYPE_L (49), .OUT_ST_DATA_W (73), .ST_CHANNEL_W (13), .OPTIMIZE_FOR_RSP (0) ) width_adapter_004 ( .clk (altpll_0_c1_clk), // clk.clk .reset (rst_controller_reset_out_reset), // clk_reset.reset .in_valid (cmd_xbar_demux_001_src8_valid), // sink.valid .in_channel (cmd_xbar_demux_001_src8_channel), // .channel .in_startofpacket (cmd_xbar_demux_001_src8_startofpacket), // .startofpacket .in_endofpacket (cmd_xbar_demux_001_src8_endofpacket), // .endofpacket .in_ready (cmd_xbar_demux_001_src8_ready), // .ready .in_data (cmd_xbar_demux_001_src8_data), // .data .out_endofpacket (width_adapter_004_src_endofpacket), // src.endofpacket .out_data (width_adapter_004_src_data), // .data .out_channel (width_adapter_004_src_channel), // .channel .out_valid (width_adapter_004_src_valid), // .valid .out_ready (width_adapter_004_src_ready), // .ready .out_startofpacket (width_adapter_004_src_startofpacket), // .startofpacket .in_command_size_data (3'b000) // (terminated) ); altera_merlin_width_adapter #( .IN_PKT_ADDR_H (33), .IN_PKT_ADDR_L (9), .IN_PKT_DATA_H (7), .IN_PKT_DATA_L (0), .IN_PKT_BYTEEN_H (8), .IN_PKT_BYTEEN_L (8), .IN_PKT_BYTE_CNT_H (42), .IN_PKT_BYTE_CNT_L (40), .IN_PKT_TRANS_COMPRESSED_READ (34), .IN_PKT_BURSTWRAP_H (45), .IN_PKT_BURSTWRAP_L (43), .IN_PKT_BURST_SIZE_H (48), .IN_PKT_BURST_SIZE_L (46), .IN_PKT_RESPONSE_STATUS_H (72), .IN_PKT_RESPONSE_STATUS_L (71), .IN_PKT_TRANS_EXCLUSIVE (39), .IN_PKT_BURST_TYPE_H (50), .IN_PKT_BURST_TYPE_L (49), .IN_ST_DATA_W (73), .OUT_PKT_ADDR_H (60), .OUT_PKT_ADDR_L (36), .OUT_PKT_DATA_H (31), .OUT_PKT_DATA_L (0), .OUT_PKT_BYTEEN_H (35), .OUT_PKT_BYTEEN_L (32), .OUT_PKT_BYTE_CNT_H (69), .OUT_PKT_BYTE_CNT_L (67), .OUT_PKT_TRANS_COMPRESSED_READ (61), .OUT_PKT_BURST_SIZE_H (75), .OUT_PKT_BURST_SIZE_L (73), .OUT_PKT_RESPONSE_STATUS_H (99), .OUT_PKT_RESPONSE_STATUS_L (98), .OUT_PKT_TRANS_EXCLUSIVE (66), .OUT_PKT_BURST_TYPE_H (77), .OUT_PKT_BURST_TYPE_L (76), .OUT_ST_DATA_W (100), .ST_CHANNEL_W (13), .OPTIMIZE_FOR_RSP (1) ) width_adapter_005 ( .clk (altpll_0_c1_clk), // clk.clk .reset (rst_controller_reset_out_reset), // clk_reset.reset .in_valid (id_router_008_src_valid), // sink.valid .in_channel (id_router_008_src_channel), // .channel .in_startofpacket (id_router_008_src_startofpacket), // .startofpacket .in_endofpacket (id_router_008_src_endofpacket), // .endofpacket .in_ready (id_router_008_src_ready), // .ready .in_data (id_router_008_src_data), // .data .out_endofpacket (width_adapter_005_src_endofpacket), // src.endofpacket .out_data (width_adapter_005_src_data), // .data .out_channel (width_adapter_005_src_channel), // .channel .out_valid (width_adapter_005_src_valid), // .valid .out_ready (width_adapter_005_src_ready), // .ready .out_startofpacket (width_adapter_005_src_startofpacket), // .startofpacket .in_command_size_data (3'b000) // (terminated) ); altera_avalon_st_handshake_clock_crosser #( .DATA_WIDTH (100), .BITS_PER_SYMBOL (100), .USE_PACKETS (1), .USE_CHANNEL (1), .CHANNEL_WIDTH (13), .USE_ERROR (0), .ERROR_WIDTH (1), .VALID_SYNC_DEPTH (2), .READY_SYNC_DEPTH (2), .USE_OUTPUT_PIPELINE (0) ) crosser ( .in_clk (altpll_0_c1_clk), // in_clk.clk .in_reset (rst_controller_reset_out_reset), // in_clk_reset.reset .out_clk (clk_clk), // out_clk.clk .out_reset (rst_controller_001_reset_out_reset), // out_clk_reset.reset .in_ready (cmd_xbar_demux_001_src4_ready), // in.ready .in_valid (cmd_xbar_demux_001_src4_valid), // .valid .in_startofpacket (cmd_xbar_demux_001_src4_startofpacket), // .startofpacket .in_endofpacket (cmd_xbar_demux_001_src4_endofpacket), // .endofpacket .in_channel (cmd_xbar_demux_001_src4_channel), // .channel .in_data (cmd_xbar_demux_001_src4_data), // .data .out_ready (crosser_out_ready), // out.ready .out_valid (crosser_out_valid), // .valid .out_startofpacket (crosser_out_startofpacket), // .startofpacket .out_endofpacket (crosser_out_endofpacket), // .endofpacket .out_channel (crosser_out_channel), // .channel .out_data (crosser_out_data), // .data .in_empty (1'b0), // (terminated) .in_error (1'b0), // (terminated) .out_empty (), // (terminated) .out_error () // (terminated) ); altera_avalon_st_handshake_clock_crosser #( .DATA_WIDTH (100), .BITS_PER_SYMBOL (100), .USE_PACKETS (1), .USE_CHANNEL (1), .CHANNEL_WIDTH (13), .USE_ERROR (0), .ERROR_WIDTH (1), .VALID_SYNC_DEPTH (2), .READY_SYNC_DEPTH (2), .USE_OUTPUT_PIPELINE (0) ) crosser_001 ( .in_clk (clk_clk), // in_clk.clk .in_reset (rst_controller_001_reset_out_reset), // in_clk_reset.reset .out_clk (altpll_0_c1_clk), // out_clk.clk .out_reset (rst_controller_reset_out_reset), // out_clk_reset.reset .in_ready (rsp_xbar_demux_004_src0_ready), // in.ready .in_valid (rsp_xbar_demux_004_src0_valid), // .valid .in_startofpacket (rsp_xbar_demux_004_src0_startofpacket), // .startofpacket .in_endofpacket (rsp_xbar_demux_004_src0_endofpacket), // .endofpacket .in_channel (rsp_xbar_demux_004_src0_channel), // .channel .in_data (rsp_xbar_demux_004_src0_data), // .data .out_ready (crosser_001_out_ready), // out.ready .out_valid (crosser_001_out_valid), // .valid .out_startofpacket (crosser_001_out_startofpacket), // .startofpacket .out_endofpacket (crosser_001_out_endofpacket), // .endofpacket .out_channel (crosser_001_out_channel), // .channel .out_data (crosser_001_out_data), // .data .in_empty (1'b0), // (terminated) .in_error (1'b0), // (terminated) .out_empty (), // (terminated) .out_error () // (terminated) ); tracking_camera_system_irq_mapper irq_mapper ( .clk (altpll_0_c1_clk), // clk.clk .reset (rst_controller_reset_out_reset), // clk_reset.reset .receiver0_irq (irq_mapper_receiver0_irq), // receiver0.irq .receiver1_irq (irq_mapper_receiver1_irq), // receiver1.irq .sender_irq (nios2_qsys_0_d_irq_irq) // sender.irq ); endmodule
module sky130_fd_sc_hvl__mux2 ( //# {{data|Data Signals}} input A0 , input A1 , output X , //# {{control|Control Signals}} input S , //# {{power|Power}} input VPB , input VPWR, input VGND, input VNB ); endmodule
module sky130_fd_sc_hd__a2111oi ( //# {{data|Data Signals}} input A1 , input A2 , input B1 , input C1 , input D1 , output Y , //# {{power|Power}} input VPB , input VPWR, input VGND, input VNB ); endmodule
module MMCME2_ADV #( `ifdef XIL_TIMING parameter LOC = "UNPLACED", `endif parameter BANDWIDTH = "OPTIMIZED", parameter real CLKFBOUT_MULT_F = 5.000, parameter real CLKFBOUT_PHASE = 0.000, parameter CLKFBOUT_USE_FINE_PS = "FALSE", parameter real CLKIN1_PERIOD = 0.000, parameter real CLKIN2_PERIOD = 0.000, `ifdef XIL_TIMING parameter real CLKIN_FREQ_MAX = 1066.000, parameter real CLKIN_FREQ_MIN = 10.000, `endif parameter real CLKOUT0_DIVIDE_F = 1.000, parameter real CLKOUT0_DUTY_CYCLE = 0.500, parameter real CLKOUT0_PHASE = 0.000, parameter CLKOUT0_USE_FINE_PS = "FALSE", parameter integer CLKOUT1_DIVIDE = 1, parameter real CLKOUT1_DUTY_CYCLE = 0.500, parameter real CLKOUT1_PHASE = 0.000, parameter CLKOUT1_USE_FINE_PS = "FALSE", parameter integer CLKOUT2_DIVIDE = 1, parameter real CLKOUT2_DUTY_CYCLE = 0.500, parameter real CLKOUT2_PHASE = 0.000, parameter CLKOUT2_USE_FINE_PS = "FALSE", parameter integer CLKOUT3_DIVIDE = 1, parameter real CLKOUT3_DUTY_CYCLE = 0.500, parameter real CLKOUT3_PHASE = 0.000, parameter CLKOUT3_USE_FINE_PS = "FALSE", parameter CLKOUT4_CASCADE = "FALSE", parameter integer CLKOUT4_DIVIDE = 1, parameter real CLKOUT4_DUTY_CYCLE = 0.500, parameter real CLKOUT4_PHASE = 0.000, parameter CLKOUT4_USE_FINE_PS = "FALSE", parameter integer CLKOUT5_DIVIDE = 1, parameter real CLKOUT5_DUTY_CYCLE = 0.500, parameter real CLKOUT5_PHASE = 0.000, parameter CLKOUT5_USE_FINE_PS = "FALSE", parameter integer CLKOUT6_DIVIDE = 1, parameter real CLKOUT6_DUTY_CYCLE = 0.500, parameter real CLKOUT6_PHASE = 0.000, parameter CLKOUT6_USE_FINE_PS = "FALSE", `ifdef XIL_TIMING parameter real CLKPFD_FREQ_MAX = 550.000, parameter real CLKPFD_FREQ_MIN = 10.000, `endif parameter COMPENSATION = "ZHOLD", parameter integer DIVCLK_DIVIDE = 1, parameter [0:0] IS_CLKINSEL_INVERTED = 1'b0, parameter [0:0] IS_PSEN_INVERTED = 1'b0, parameter [0:0] IS_PSINCDEC_INVERTED = 1'b0, parameter [0:0] IS_PWRDWN_INVERTED = 1'b0, parameter [0:0] IS_RST_INVERTED = 1'b0, parameter real REF_JITTER1 = 0.010, parameter real REF_JITTER2 = 0.010, parameter SS_EN = "FALSE", parameter SS_MODE = "CENTER_HIGH", parameter integer SS_MOD_PERIOD = 10000, `ifdef XIL_TIMING parameter STARTUP_WAIT = "FALSE", parameter real VCOCLK_FREQ_MAX = 1600.000, parameter real VCOCLK_FREQ_MIN = 600.000 `else parameter STARTUP_WAIT = "FALSE" `endif )( output CLKFBOUT, output CLKFBOUTB, output CLKFBSTOPPED, output CLKINSTOPPED, output CLKOUT0, output CLKOUT0B, output CLKOUT1, output CLKOUT1B, output CLKOUT2, output CLKOUT2B, output CLKOUT3, output CLKOUT3B, output CLKOUT4, output CLKOUT5, output CLKOUT6, output [15:0] DO, output DRDY, output LOCKED, output PSDONE, input CLKFBIN, input CLKIN1, input CLKIN2, input CLKINSEL, input [6:0] DADDR, input DCLK, input DEN, input [15:0] DI, input DWE, input PSCLK, input PSEN, input PSINCDEC, input PWRDWN, input RST ); // define constants localparam MODULE_NAME = "MMCME2_ADV"; // Parameter encodings and registers localparam BANDWIDTH_HIGH = 1; localparam BANDWIDTH_LOW = 2; localparam BANDWIDTH_OPTIMIZED = 0; localparam CLKFBOUT_USE_FINE_PS_FALSE = 0; localparam CLKFBOUT_USE_FINE_PS_TRUE = 1; localparam CLKOUT0_USE_FINE_PS_FALSE = 0; localparam CLKOUT0_USE_FINE_PS_TRUE = 1; localparam CLKOUT1_USE_FINE_PS_FALSE = 0; localparam CLKOUT1_USE_FINE_PS_TRUE = 1; localparam CLKOUT2_USE_FINE_PS_FALSE = 0; localparam CLKOUT2_USE_FINE_PS_TRUE = 1; localparam CLKOUT3_USE_FINE_PS_FALSE = 0; localparam CLKOUT3_USE_FINE_PS_TRUE = 1; localparam CLKOUT4_CASCADE_FALSE = 0; localparam CLKOUT4_CASCADE_TRUE = 1; localparam CLKOUT4_USE_FINE_PS_FALSE = 0; localparam CLKOUT4_USE_FINE_PS_TRUE = 1; localparam CLKOUT5_USE_FINE_PS_FALSE = 0; localparam CLKOUT5_USE_FINE_PS_TRUE = 1; localparam CLKOUT6_USE_FINE_PS_FALSE = 0; localparam CLKOUT6_USE_FINE_PS_TRUE = 1; localparam COMPENSATION_BUF_IN = 1; localparam COMPENSATION_EXTERNAL = 2; localparam COMPENSATION_INTERNAL = 3; localparam COMPENSATION_ZHOLD = 4; localparam SS_EN_FALSE = 0; localparam SS_EN_TRUE = 1; localparam SS_MODE_CENTER_HIGH = 0; localparam SS_MODE_CENTER_LOW = 1; localparam SS_MODE_DOWN_HIGH = 2; localparam SS_MODE_DOWN_LOW = 3; localparam STARTUP_WAIT_FALSE = 0; localparam STARTUP_WAIT_TRUE = 1; `ifndef XIL_TIMING localparam real CLKIN_FREQ_MAX = 1066.0; localparam real CLKIN_FREQ_MIN = 10.0; localparam real CLKPFD_FREQ_MAX = 550.0; localparam real CLKPFD_FREQ_MIN = 10.0; localparam real VCOCLK_FREQ_MAX = 1600.0; localparam real VCOCLK_FREQ_MIN = 600.0; `endif reg trig_attr = 1'b0; localparam [72:1] BANDWIDTH_REG = BANDWIDTH; localparam real CLKFBOUT_MULT_F_REG = CLKFBOUT_MULT_F; localparam real CLKFBOUT_PHASE_REG = CLKFBOUT_PHASE; localparam [40:1] CLKFBOUT_USE_FINE_PS_REG = CLKFBOUT_USE_FINE_PS; localparam real CLKIN1_PERIOD_REG = CLKIN1_PERIOD; localparam real CLKIN2_PERIOD_REG = CLKIN2_PERIOD; localparam real CLKIN_FREQ_MAX_REG = CLKIN_FREQ_MAX; localparam real CLKIN_FREQ_MIN_REG = CLKIN_FREQ_MIN; localparam real CLKOUT0_DIVIDE_F_REG = CLKOUT0_DIVIDE_F; localparam real CLKOUT0_DUTY_CYCLE_REG = CLKOUT0_DUTY_CYCLE; localparam real CLKOUT0_PHASE_REG = CLKOUT0_PHASE; localparam [40:1] CLKOUT0_USE_FINE_PS_REG = CLKOUT0_USE_FINE_PS; localparam [7:0] CLKOUT1_DIVIDE_REG = CLKOUT1_DIVIDE; localparam real CLKOUT1_DUTY_CYCLE_REG = CLKOUT1_DUTY_CYCLE; localparam real CLKOUT1_PHASE_REG = CLKOUT1_PHASE; localparam [40:1] CLKOUT1_USE_FINE_PS_REG = CLKOUT1_USE_FINE_PS; localparam [7:0] CLKOUT2_DIVIDE_REG = CLKOUT2_DIVIDE; localparam real CLKOUT2_DUTY_CYCLE_REG = CLKOUT2_DUTY_CYCLE; localparam real CLKOUT2_PHASE_REG = CLKOUT2_PHASE; localparam [40:1] CLKOUT2_USE_FINE_PS_REG = CLKOUT2_USE_FINE_PS; localparam [7:0] CLKOUT3_DIVIDE_REG = CLKOUT3_DIVIDE; localparam real CLKOUT3_DUTY_CYCLE_REG = CLKOUT3_DUTY_CYCLE; localparam real CLKOUT3_PHASE_REG = CLKOUT3_PHASE; localparam [40:1] CLKOUT3_USE_FINE_PS_REG = CLKOUT3_USE_FINE_PS; localparam [40:1] CLKOUT4_CASCADE_REG = CLKOUT4_CASCADE; localparam [7:0] CLKOUT4_DIVIDE_REG = CLKOUT4_DIVIDE; localparam real CLKOUT4_DUTY_CYCLE_REG = CLKOUT4_DUTY_CYCLE; localparam real CLKOUT4_PHASE_REG = CLKOUT4_PHASE; localparam [40:1] CLKOUT4_USE_FINE_PS_REG = CLKOUT4_USE_FINE_PS; localparam [7:0] CLKOUT5_DIVIDE_REG = CLKOUT5_DIVIDE; localparam real CLKOUT5_DUTY_CYCLE_REG = CLKOUT5_DUTY_CYCLE; localparam real CLKOUT5_PHASE_REG = CLKOUT5_PHASE; localparam [40:1] CLKOUT5_USE_FINE_PS_REG = CLKOUT5_USE_FINE_PS; localparam [7:0] CLKOUT6_DIVIDE_REG = CLKOUT6_DIVIDE; localparam real CLKOUT6_DUTY_CYCLE_REG = CLKOUT6_DUTY_CYCLE; localparam real CLKOUT6_PHASE_REG = CLKOUT6_PHASE; localparam [40:1] CLKOUT6_USE_FINE_PS_REG = CLKOUT6_USE_FINE_PS; localparam real CLKPFD_FREQ_MAX_REG = CLKPFD_FREQ_MAX; localparam real CLKPFD_FREQ_MIN_REG = CLKPFD_FREQ_MIN; localparam [64:1] COMPENSATION_REG = COMPENSATION; localparam [6:0] DIVCLK_DIVIDE_REG = DIVCLK_DIVIDE; localparam [0:0] IS_CLKINSEL_INVERTED_REG = IS_CLKINSEL_INVERTED; localparam [0:0] IS_PSEN_INVERTED_REG = IS_PSEN_INVERTED; localparam [0:0] IS_PSINCDEC_INVERTED_REG = IS_PSINCDEC_INVERTED; localparam [0:0] IS_PWRDWN_INVERTED_REG = IS_PWRDWN_INVERTED; localparam [0:0] IS_RST_INVERTED_REG = IS_RST_INVERTED; localparam real REF_JITTER1_REG = REF_JITTER1; localparam real REF_JITTER2_REG = REF_JITTER2; localparam [40:1] SS_EN_REG = SS_EN; localparam [88:1] SS_MODE_REG = SS_MODE; localparam [15:0] SS_MOD_PERIOD_REG = SS_MOD_PERIOD; localparam [40:1] STARTUP_WAIT_REG = STARTUP_WAIT; localparam real VCOCLK_FREQ_MAX_REG = VCOCLK_FREQ_MAX; localparam real VCOCLK_FREQ_MIN_REG = VCOCLK_FREQ_MIN; wire [1:0] BANDWIDTH_BIN; wire [63:0] CLKFBOUT_MULT_F_BIN; wire [63:0] CLKFBOUT_PHASE_BIN; wire CLKFBOUT_USE_FINE_PS_BIN; wire [63:0] CLKIN1_PERIOD_BIN; wire [63:0] CLKIN2_PERIOD_BIN; wire [63:0] CLKIN_FREQ_MAX_BIN; wire [63:0] CLKIN_FREQ_MIN_BIN; wire [63:0] CLKOUT0_DIVIDE_F_BIN; wire [63:0] CLKOUT0_DUTY_CYCLE_BIN; wire [63:0] CLKOUT0_PHASE_BIN; wire CLKOUT0_USE_FINE_PS_BIN; wire [7:0] CLKOUT1_DIVIDE_BIN; wire [63:0] CLKOUT1_DUTY_CYCLE_BIN; wire [63:0] CLKOUT1_PHASE_BIN; wire CLKOUT1_USE_FINE_PS_BIN; wire [7:0] CLKOUT2_DIVIDE_BIN; wire [63:0] CLKOUT2_DUTY_CYCLE_BIN; wire [63:0] CLKOUT2_PHASE_BIN; wire CLKOUT2_USE_FINE_PS_BIN; wire [7:0] CLKOUT3_DIVIDE_BIN; wire [63:0] CLKOUT3_DUTY_CYCLE_BIN; wire [63:0] CLKOUT3_PHASE_BIN; wire CLKOUT3_USE_FINE_PS_BIN; wire CLKOUT4_CASCADE_BIN; wire [7:0] CLKOUT4_DIVIDE_BIN; wire [63:0] CLKOUT4_DUTY_CYCLE_BIN; wire [63:0] CLKOUT4_PHASE_BIN; wire CLKOUT4_USE_FINE_PS_BIN; wire [7:0] CLKOUT5_DIVIDE_BIN; wire [63:0] CLKOUT5_DUTY_CYCLE_BIN; wire [63:0] CLKOUT5_PHASE_BIN; wire CLKOUT5_USE_FINE_PS_BIN; wire [7:0] CLKOUT6_DIVIDE_BIN; wire [63:0] CLKOUT6_DUTY_CYCLE_BIN; wire [63:0] CLKOUT6_PHASE_BIN; wire CLKOUT6_USE_FINE_PS_BIN; wire [63:0] CLKPFD_FREQ_MAX_BIN; wire [63:0] CLKPFD_FREQ_MIN_BIN; wire [2:0] COMPENSATION_BIN; wire [6:0] DIVCLK_DIVIDE_BIN; wire IS_CLKINSEL_INVERTED_BIN; wire IS_PSEN_INVERTED_BIN; wire IS_PSINCDEC_INVERTED_BIN; wire IS_PWRDWN_INVERTED_BIN; wire IS_RST_INVERTED_BIN; wire [63:0] REF_JITTER1_BIN; wire [63:0] REF_JITTER2_BIN; wire SS_EN_BIN; wire [1:0] SS_MODE_BIN; wire [15:0] SS_MOD_PERIOD_BIN; wire STARTUP_WAIT_BIN; wire [63:0] VCOCLK_FREQ_MAX_BIN; wire [63:0] VCOCLK_FREQ_MIN_BIN; `ifdef XIL_ATTR_TEST reg attr_test = 1'b1; `else reg attr_test = 1'b0; `endif reg attr_err = 1'b0; tri0 glblGSR = glbl.GSR; wire CLKFBOUTB_out; reg CLKFBOUT_out; reg CLKFBSTOPPED_out = 0; reg CLKINSTOPPED_out = 0; wire CLKOUT0B_out; reg CLKOUT0_out; wire CLKOUT1B_out; reg CLKOUT1_out; wire CLKOUT2B_out; reg CLKOUT2_out; wire CLKOUT3B_out; reg CLKOUT3_out; reg CLKOUT4_out; reg CLKOUT5_out; reg CLKOUT6_out; reg DRDY_out; reg LOCKED_out = 1'b0; reg PSDONE_out; reg [15:0] DO_out; wire CLKFBIN_in; wire CLKIN1_in; wire CLKIN2_in; wire CLKINSEL_in; wire DCLK_in; wire DEN_in; wire DWE_in; wire PSCLK_in; wire PSEN_in; wire PSINCDEC_in; wire PWRDWN_in; wire RST_in; wire [15:0] DI_in; wire [6:0] DADDR_in; `ifdef XIL_TIMING wire DCLK_delay; wire DEN_delay; wire DWE_delay; wire PSCLK_delay; wire PSEN_delay; wire PSINCDEC_delay; wire [15:0] DI_delay; wire [6:0] DADDR_delay; `endif assign CLKFBOUT = CLKFBOUT_out; assign CLKFBOUTB = ~CLKFBOUT_out; assign CLKFBSTOPPED = CLKFBSTOPPED_out; assign CLKINSTOPPED = CLKINSTOPPED_out; assign CLKOUT0 = CLKOUT0_out; assign CLKOUT0B = ~CLKOUT0_out; assign CLKOUT1 = CLKOUT1_out; assign CLKOUT1B = ~CLKOUT1_out; assign CLKOUT2 = CLKOUT2_out; assign CLKOUT2B = ~CLKOUT2_out; assign CLKOUT3 = CLKOUT3_out; assign CLKOUT3B = ~CLKOUT3_out; assign CLKOUT4 = CLKOUT4_out; assign CLKOUT5 = CLKOUT5_out; assign CLKOUT6 = CLKOUT6_out; assign DO = DO_out; assign DRDY = DRDY_out; assign LOCKED = LOCKED_out; assign PSDONE = PSDONE_out; //inputs with timing `ifdef XIL_TIMING assign DADDR_in[0] = (DADDR[0] !== 1'bz) && DADDR_delay[0]; // rv 0 assign DADDR_in[1] = (DADDR[1] !== 1'bz) && DADDR_delay[1]; // rv 0 assign DADDR_in[2] = (DADDR[2] !== 1'bz) && DADDR_delay[2]; // rv 0 assign DADDR_in[3] = (DADDR[3] !== 1'bz) && DADDR_delay[3]; // rv 0 assign DADDR_in[4] = (DADDR[4] !== 1'bz) && DADDR_delay[4]; // rv 0 assign DADDR_in[5] = (DADDR[5] !== 1'bz) && DADDR_delay[5]; // rv 0 assign DADDR_in[6] = (DADDR[6] !== 1'bz) && DADDR_delay[6]; // rv 0 assign DCLK_in = (DCLK !== 1'bz) && DCLK_delay; // rv 0 assign DEN_in = (DEN !== 1'bz) && DEN_delay; // rv 0 assign DI_in[0] = (DI[0] !== 1'bz) && DI_delay[0]; // rv 0 assign DI_in[10] = (DI[10] !== 1'bz) && DI_delay[10]; // rv 0 assign DI_in[11] = (DI[11] !== 1'bz) && DI_delay[11]; // rv 0 assign DI_in[12] = (DI[12] !== 1'bz) && DI_delay[12]; // rv 0 assign DI_in[13] = (DI[13] !== 1'bz) && DI_delay[13]; // rv 0 assign DI_in[14] = (DI[14] !== 1'bz) && DI_delay[14]; // rv 0 assign DI_in[15] = (DI[15] !== 1'bz) && DI_delay[15]; // rv 0 assign DI_in[1] = (DI[1] !== 1'bz) && DI_delay[1]; // rv 0 assign DI_in[2] = (DI[2] !== 1'bz) && DI_delay[2]; // rv 0 assign DI_in[3] = (DI[3] !== 1'bz) && DI_delay[3]; // rv 0 assign DI_in[4] = (DI[4] !== 1'bz) && DI_delay[4]; // rv 0 assign DI_in[5] = (DI[5] !== 1'bz) && DI_delay[5]; // rv 0 assign DI_in[6] = (DI[6] !== 1'bz) && DI_delay[6]; // rv 0 assign DI_in[7] = (DI[7] !== 1'bz) && DI_delay[7]; // rv 0 assign DI_in[8] = (DI[8] !== 1'bz) && DI_delay[8]; // rv 0 assign DI_in[9] = (DI[9] !== 1'bz) && DI_delay[9]; // rv 0 assign DWE_in = (DWE !== 1'bz) && DWE_delay; // rv 0 assign PSCLK_in = (PSCLK !== 1'bz) && PSCLK_delay; // rv 0 assign PSEN_in = (PSEN !== 1'bz) && (PSEN_delay ^ IS_PSEN_INVERTED_BIN); // rv 0 assign PSINCDEC_in = (PSINCDEC !== 1'bz) && (PSINCDEC_delay ^ IS_PSINCDEC_INVERTED_BIN); // rv 0 `else assign DADDR_in[0] = (DADDR[0] !== 1'bz) && DADDR[0]; // rv 0 assign DADDR_in[1] = (DADDR[1] !== 1'bz) && DADDR[1]; // rv 0 assign DADDR_in[2] = (DADDR[2] !== 1'bz) && DADDR[2]; // rv 0 assign DADDR_in[3] = (DADDR[3] !== 1'bz) && DADDR[3]; // rv 0 assign DADDR_in[4] = (DADDR[4] !== 1'bz) && DADDR[4]; // rv 0 assign DADDR_in[5] = (DADDR[5] !== 1'bz) && DADDR[5]; // rv 0 assign DADDR_in[6] = (DADDR[6] !== 1'bz) && DADDR[6]; // rv 0 assign DCLK_in = (DCLK !== 1'bz) && DCLK; // rv 0 assign DEN_in = (DEN !== 1'bz) && DEN; // rv 0 assign DI_in[0] = (DI[0] !== 1'bz) && DI[0]; // rv 0 assign DI_in[10] = (DI[10] !== 1'bz) && DI[10]; // rv 0 assign DI_in[11] = (DI[11] !== 1'bz) && DI[11]; // rv 0 assign DI_in[12] = (DI[12] !== 1'bz) && DI[12]; // rv 0 assign DI_in[13] = (DI[13] !== 1'bz) && DI[13]; // rv 0 assign DI_in[14] = (DI[14] !== 1'bz) && DI[14]; // rv 0 assign DI_in[15] = (DI[15] !== 1'bz) && DI[15]; // rv 0 assign DI_in[1] = (DI[1] !== 1'bz) && DI[1]; // rv 0 assign DI_in[2] = (DI[2] !== 1'bz) && DI[2]; // rv 0 assign DI_in[3] = (DI[3] !== 1'bz) && DI[3]; // rv 0 assign DI_in[4] = (DI[4] !== 1'bz) && DI[4]; // rv 0 assign DI_in[5] = (DI[5] !== 1'bz) && DI[5]; // rv 0 assign DI_in[6] = (DI[6] !== 1'bz) && DI[6]; // rv 0 assign DI_in[7] = (DI[7] !== 1'bz) && DI[7]; // rv 0 assign DI_in[8] = (DI[8] !== 1'bz) && DI[8]; // rv 0 assign DI_in[9] = (DI[9] !== 1'bz) && DI[9]; // rv 0 assign DWE_in = (DWE !== 1'bz) && DWE; // rv 0 assign PSCLK_in = (PSCLK !== 1'bz) && PSCLK; // rv 0 assign PSEN_in = (PSEN !== 1'bz) && (PSEN ^ IS_PSEN_INVERTED_BIN); // rv 0 assign PSINCDEC_in = (PSINCDEC !== 1'bz) && (PSINCDEC ^ IS_PSINCDEC_INVERTED_BIN); // rv 0 `endif assign CLKFBIN_in = (CLKFBIN !== 1'bz) && CLKFBIN; // rv 0 assign CLKIN1_in = (CLKIN1 !== 1'bz) && CLKIN1; // rv 0 assign CLKIN2_in = (CLKIN2 !== 1'bz) && CLKIN2; // rv 0 assign CLKINSEL_in = (CLKINSEL === 1'bz) || (CLKINSEL ^ IS_CLKINSEL_INVERTED_BIN); // rv 1 assign PWRDWN_in = (PWRDWN !== 1'bz) && (PWRDWN ^ IS_PWRDWN_INVERTED_BIN); // rv 0 assign RST_in = (RST !== 1'bz) && (RST ^ IS_RST_INVERTED_BIN); // rv 0 localparam VCOCLK_FREQ_TARGET = 1000; localparam M_MIN = 2.000; localparam M_MAX = 64.000; localparam VF_MIN = 600.000; localparam D_MIN = 1; localparam D_MAX = 106; localparam O_MIN = 1; localparam O_MAX = 128; localparam O_MAX_HT_LT = 64; localparam REF_CLK_JITTER_MAX = 1000; localparam REF_CLK_JITTER_SCALE = 0.1; localparam MAX_FEEDBACK_DELAY = 10.0; localparam MAX_FEEDBACK_DELAY_SCALE = 1.0; localparam ps_max = 55; real CLKOUT0_DIVIDE_F_RND; real CLKFBOUT_MULT_F_RND; tri1 p_up; wire glock; integer pchk_tmp1, pchk_tmp2; integer clkvco_div_fint; real clkvco_div_frac; reg clk0_out; reg clkfbout_out; integer clkvco_frac_en; integer ps_in_init; reg psdone_out1; integer clk0_fps_en, clk1_fps_en, clk2_fps_en, clk3_fps_en, clk4_fps_en; integer clk5_fps_en, clk6_fps_en, clkfbout_fps_en; integer fps_en=0, fps_clk_en=0; reg clkinstopped_out1; reg clkin_hold_f = 0; reg clkinstopped_out_dly2 = 0, clkin_stop_f = 0; integer period_avg_stpi = 0, period_avg_stp = 0; real tmp_stp1, tmp_stp2; reg pd_stp_p = 0; reg vco_stp_f = 0; reg psen_w = 0; reg clkinstopped_out_dly = 0; reg clkfbin_stop_tmp, clkfbstopped_out1, clkin_stop_tmp; reg rst_clkinstopped = 0, rst_clkfbstopped = 0, rst_clkinstopped_tm = 0; reg rst_clkinstopped_rc = 0; reg rst_clkinstopped_lk, rst_clkfbstopped_lk; integer clkin_lost_cnt, clkfbin_lost_cnt; reg clkinstopped_hold = 0; integer ps_in_ps, ps_cnt; integer ps_in_ps_neg, ps_cnt_neg; reg clkout4_cascade_int; reg [6:0] daddr_lat; reg valid_daddr; reg drdy_out1; reg drp_lock; integer drp_lock_lat = 4; integer drp_lock_lat_cnt; reg [15:0] dr_sram [127:0]; reg [160:0] tmp_string; reg rst_int; reg pwron_int; wire rst_in_o; wire locked_out1; reg locked_out_tmp; reg clk1_out, clk2_out, clk3_out, clk4_out, clk5_out, clk6_out; reg clkout_en, clkout_en1, clkout_en0, clkout_en0_tmp, clkout_en0_tmp1; integer clkout_en_val, clkout_en_t; integer clkin_lock_cnt; integer clkout_en_time, locked_en_time, lock_cnt_max; integer pll_lock_time, lock_period_time; reg clkvco; reg clkvco_lk_dly_tmp; reg clkvco_lk_en; reg clkvco_lk; reg fbclk_tmp; reg clkin_osc, clkin_p, clkfbin_osc, clkfbin_p; reg clkinstopped_vco_f; time rst_edge, rst_ht; reg fb_delay_found=1'b0, fb_delay_found_tmp=1'b0; reg clkfbout_tst=1'b0; real fb_delay_max; time fb_delay, clkvco_delay, val_tmp, dly_tmp, fb_comp_delay; time dly_tmp1, tmp_ps_val2; integer dly_tmp_int, tmp_ps_val1; time clkin_edge, delay_edge; real period_clkin, clkin_period_tmp; integer clkin_period_tmp_t; integer clkin_period [4:0]; integer period_vco, period_vco_half, period_vco_half1, period_vco_half_rm; real period_vco_rl, period_vco_rl_half; integer period_vco_half_rm1, period_vco_half_rm2; real cmpvco = 0.0; real clkvco_pdrm; integer period_vco_mf; integer period_vco_tmp; integer period_vco_rm, period_vco_cmp_cnt, clkvco_rm_cnt; integer period_vco_cmp_flag; integer period_vco_max, period_vco_min; integer period_vco1, period_vco2, period_vco3, period_vco4; integer period_vco5, period_vco6, period_vco7; integer period_vco_target, period_vco_target_half; integer period_fb=100000, period_avg=100000; integer clk0_frac_lt, clk0_frac_ht; integer clkfbout_frac_lt, clkfbout_frac_ht; integer period_ps, period_ps_old; reg ps_lock, ps_lock_dly; real clkvco_freq_init_chk, clkfbout_pm_rl; real tmp_real; integer ik0, ik1, ik2, ik3, ik4, ib, i, j; integer md_product, m_product, m_product2; integer mf_product, clk0f_product; // integer clkin_lost_val, clkfbin_lost_val, clkin_lost_val_lk; integer clkin_lost_val, clkfbin_lost_val; time pll_locked_delay, clkin_dly_t, clkfbin_dly_t; wire pll_unlock, pll_unlock1; reg pll_locked_tmp1, pll_locked_tmp2; reg lock_period; reg pll_locked_tm, unlock_recover; reg clkpll_jitter_unlock; integer clkin_jit, REF_CLK_JITTER_MAX_tmp; wire init_trig, clkpll_r; reg clk0in=1'b0,clk1in=1'b0,clk2in=1'b0,clk3in=1'b0,clk4in=1'b0,clk5in=1'b0,clk6in=1'b0; reg clkpll_tmp1, clkpll; reg clkfboutin=1'b0; wire clkfbps_en; reg chk_ok; wire clk0ps_en, clk1ps_en, clk2ps_en, clk3ps_en, clk4ps_en, clk5ps_en, clk6ps_en; reg [3:0] d_rsel, clkfbout_rsel, clk0_rsel; reg [3:0] d_fsel, clkfbout_fsel, clk0_fsel; reg [6:0] d_fht, clkfbout_fht, clk0_fht; reg [6:0] d_flt, clkfbout_flt, clk0_flt; reg [5:0] clk0_dly_cnt; reg [5:0] clk1_dly_cnt; reg [5:0] clk2_dly_cnt; reg [5:0] clk3_dly_cnt; reg [5:0] clk4_dly_cnt; reg [5:0] clk5_dly_cnt; reg [5:0] clk6_dly_cnt; real clk0_phase, clk0_duty; real clk1_phase, clk1_duty; real clk2_phase, clk2_duty; real clk3_phase, clk3_duty; real clk4_phase, clk4_duty; real clk5_phase, clk5_duty; real clk6_phase, clk6_duty; real divclk_phase=0.000, divclk_duty=0.500; real clkfbout_phase, clkfbout_duty=0.500; // mem cells reg [2:0] d_frac, clkfbout_frac, clk0_frac; reg d_frac_en, clkfbout_frac_en, clk0_frac_en; reg d_wf_f, clkfbout_wf_f, clk0_wf_f; reg d_wf_r, clkfbout_wf_r, clk0_wf_r; reg [2:0] d_mx, clkfbout_mx, clk0_mx, clk1_mx, clk2_mx, clk3_mx, clk4_mx, clk5_mx, clk6_mx; reg divclk_e, clkfbin_e; reg clkfbout_e, clk0_e, clk1_e, clk2_e, clk3_e, clk4_e, clk5_e, clk6_e; reg divclk_nc, clkfbin_nc; reg clkfbout_nc, clk0_nc, clk1_nc, clk2_nc, clk3_nc, clk4_nc, clk5_nc, clk6_nc; reg [5:0] d_dt, clkfbout_dt, clk0_dt, clk1_dt, clk2_dt, clk3_dt, clk4_dt, clk5_dt, clk6_dt; reg [2:0] d_pm_f, clkfbout_pm_f, clk0_pm_f; reg [2:0] clkfbout_pm_r, clk0_pm_r; reg [2:0] d_pm, clk1_pm, clk2_pm, clk3_pm, clk4_pm, clk5_pm, clk6_pm; reg divclk_en, clkfbout_en, clk0_en, clk1_en, clk2_en, clk3_en, clk4_en, clk5_en, clk6_en; reg [5:0] clkfbin_ht; reg [7:0] divclk_ht; reg [5:0] clkfbout_ht, clk0_ht, clk1_ht, clk2_ht, clk3_ht, clk4_ht, clk5_ht, clk6_ht; reg [5:0] clkfbin_lt; reg [7:0] divclk_lt; reg [6:0] clkfbout_lt, clk0_lt, clk1_lt, clk2_lt, clk3_lt, clk4_lt, clk5_lt, clk6_lt; // real clkfbout_f_div=1.0; real clk0_f_div; integer d_div, clkfbout_div, clk0_div; reg [5:0] clkfbout_dly_cnt; reg [7:0] clkfbout_cnt; reg [7:0] clk0_cnt; reg [7:0] clk1_cnt, clk1_div; reg [7:0] clk2_cnt, clk2_div; reg [7:0] clk3_cnt, clk3_div; reg [7:0] clk4_cnt, clk4_div; reg [7:0] clk5_cnt, clk5_div; reg [7:0] clk6_cnt, clk6_div; integer divclk_cnt_max, clkfbout_cnt_max, clk0_cnt_max; integer clk1_cnt_max, clk2_cnt_max, clk3_cnt_max, clk4_cnt_max, clk5_cnt_max, clk6_cnt_max; integer divclk_cnt_ht, clkfbout_cnt_ht, clk0_cnt_ht; integer clk1_cnt_ht, clk2_cnt_ht, clk3_cnt_ht, clk4_cnt_ht, clk5_cnt_ht, clk6_cnt_ht; reg [7:0] divclk_div=8'b1, divclk_cnt=8'b0; reg divclk_out, divclk_out_tmp; reg [3:0] pll_cp, pll_res; reg [1:0] pll_lfhf; reg [1:0] pll_cpres = 2'b01; reg [4:0] drp_lock_ref_dly; reg [4:0] drp_lock_fb_dly; reg [9:0] drp_lock_cnt; reg [9:0] drp_unlock_cnt; reg [9:0] drp_lock_sat_high; wire clkinsel_tmp; real clkin_chk_t1, clkin_chk_t2; real clkin_chk_t1_r, clkin_chk_t2_r; integer clkin_chk_t1_i, clkin_chk_t2_i; reg init_chk; reg rst_clkinsel_flag = 0; wire [15:0] do_out1; wire pwrdwn_in1; reg pwrdwn_in1_h = 0; reg rst_input_r_h = 0; reg pchk_clr = 0; reg psincdec_chg = 0; reg psincdec_chg_tmp = 0; wire rst_input; reg startup_wait_sig; reg vcoflag = 0; reg drp_updt = 1'b0; real halfperiod_sum = 0.0; integer halfperiod = 0; reg clkvco_free = 1'b0; integer ik10, ik11; //drp monitor reg den_r1 = 1'b0; reg den_r2 = 1'b0; reg dwe_r1 = 1'b0; reg dwe_r2 = 1'b0; reg [1:0] sfsm = 2'b01; localparam FSM_IDLE = 2'b01; localparam FSM_WAIT = 2'b10; always @(posedge DCLK_in) begin // pipeline the DEN and DWE den_r1 <= DEN_in; dwe_r1 <= DWE_in; den_r2 <= den_r1; dwe_r2 <= dwe_r1; // Check - if DEN or DWE is more than 1 DCLK if ((den_r1 == 1'b1) && (den_r2 == 1'b1)) begin $display("DRC Error : DEN is high for more than 1 DCLK. Instance %m"); $finish; end if ((dwe_r1 == 1'b1) && (dwe_r2 == 1'b1)) begin $display("DRC Error : DWE is high for more than 1 DCLK. Instance %m"); $finish; end //After the 1st DEN pulse, check the DEN and DRDY. case (sfsm) FSM_IDLE: begin if(DEN_in == 1'b1) sfsm <= FSM_WAIT; end FSM_WAIT: begin // After the 1st DEN, 4 cases can happen // DEN DRDY NEXT STATE // 0 0 FSM_WAIT - wait for DRDY // 0 1 FSM_IDLE - normal operation // 1 0 FSM_WAIT - display error and wait for DRDY // 1 1 FSM_WAIT - normal operation. Per UG470, DEN and DRDY can be at the same cycle. //Add the check for another DPREN pulse if(DEN_in === 1'b1 && DRDY_out === 1'b0) begin $display("DRC Error : DEN is enabled before DRDY returns. Instance %m"); $finish; end //Add the check for another DWE pulse if ((DWE_in === 1'b1) && (DEN_in === 1'b0)) begin $display("DRC Error : DWE is enabled before DRDY returns. Instance %m"); $finish; end if ((DRDY_out === 1'b1) && (DEN_in === 1'b0)) begin sfsm <= FSM_IDLE; end if ((DRDY_out === 1'b1) && (DEN_in === 1'b1)) begin sfsm <= FSM_WAIT; end end default: begin $display("DRC Error : Default state in DRP FSM. Instance %m"); $finish; end endcase end // always @ (posedge DCLK) //end drp monitor always @(locked_out_tmp) LOCKED_out = locked_out_tmp; always @(drdy_out1) DRDY_out = drdy_out1; always @(do_out1) DO_out = do_out1; always @(psdone_out1) PSDONE_out = psdone_out1; assign IS_CLKINSEL_INVERTED_BIN = IS_CLKINSEL_INVERTED_REG; assign IS_PSEN_INVERTED_BIN = IS_PSEN_INVERTED_REG; assign IS_PSINCDEC_INVERTED_BIN = IS_PSINCDEC_INVERTED_REG; assign IS_PWRDWN_INVERTED_BIN = IS_PWRDWN_INVERTED_REG; assign IS_RST_INVERTED_BIN = IS_RST_INVERTED_REG; initial begin #1; if ($realtime == 0) begin $display ("Error: [Unisim %s-1] Simulator resolution is set to a value greater than 1 ps. ", MODULE_NAME); $display ("The simulator resolution must be set to 1ps or smaller. Instance %m"); #1 $finish; end end initial begin #1; if ((attr_test == 1'b1) || ((BANDWIDTH_REG != "OPTIMIZED") && (BANDWIDTH_REG != "HIGH") && (BANDWIDTH_REG != "LOW"))) begin $display("Error: [Unisim %s-101] BANDWIDTH attribute is set to %s. Legal values for this attribute are OPTIMIZED, HIGH or LOW. Instance: %m", MODULE_NAME, BANDWIDTH_REG); attr_err = 1'b1; end if ((attr_test == 1'b1) || (CLKFBOUT_MULT_F_REG < 2.000 || CLKFBOUT_MULT_F_REG > M_MAX)) begin $display("Error: [Unisim %s-102] CLKFBOUT_MULT_F attribute is set to %f. Legal values for this attribute are 2.000 to %3.3f. Instance: %m", MODULE_NAME, CLKFBOUT_MULT_F_REG, M_MAX); attr_err = 1'b1; end if ((attr_test == 1'b1) || (CLKFBOUT_PHASE_REG < -360.000 || CLKFBOUT_PHASE_REG > 360.000)) begin $display("Error: [Unisim %s-103] CLKFBOUT_PHASE attribute is set to %f. Legal values for this attribute are -360.000 to 360.000. Instance: %m", MODULE_NAME, CLKFBOUT_PHASE_REG); attr_err = 1'b1; end if ((attr_test == 1'b1) || ((CLKFBOUT_USE_FINE_PS_REG != "TRUE") && (CLKFBOUT_USE_FINE_PS_REG != "FALSE"))) begin $display("Error: [Unisim %s-104] CLKFBOUT_USE_FINE_PS attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, CLKFBOUT_USE_FINE_PS_REG); attr_err = 1'b1; end if ((attr_test == 1'b1) || (CLKIN1_PERIOD_REG < 0.000 || CLKIN1_PERIOD_REG > 100.000)) begin $display("Error: [Unisim %s-105] CLKIN1_PERIOD attribute is set to %f. Legal values for this attribute are 0.000 to 100.000. Instance: %m", MODULE_NAME, CLKIN1_PERIOD_REG); attr_err = 1'b1; end if ((attr_test == 1'b1) || (CLKIN2_PERIOD_REG < 0.000 || CLKIN2_PERIOD_REG > 100.000)) begin $display("Error: [Unisim %s-106] CLKIN2_PERIOD attribute is set to %f. Legal values for this attribute are 0.000 to 100.000. Instance: %m", MODULE_NAME, CLKIN2_PERIOD_REG); attr_err = 1'b1; end `ifdef XIL_TIMING if ((attr_test == 1'b1) || (CLKIN_FREQ_MAX_REG < 800.000 || CLKIN_FREQ_MAX_REG > 1066.000)) begin $display("Error: [Unisim %s-107] CLKIN_FREQ_MAX attribute is set to %f. Legal values for this attribute are 800.000 to 1066.000. Instance: %m", MODULE_NAME, CLKIN_FREQ_MAX_REG); attr_err = 1'b1; end if ((attr_test == 1'b1) || (CLKIN_FREQ_MIN_REG < 10.000 || CLKIN_FREQ_MIN_REG > 10.000)) begin $display("Error: [Unisim %s-108] CLKIN_FREQ_MIN attribute is set to %f. Legal values for this attribute are 10.000 to 10.000. Instance: %m", MODULE_NAME, CLKIN_FREQ_MIN_REG); attr_err = 1'b1; end `endif if ((attr_test == 1'b1) || (CLKOUT0_DIVIDE_F_REG < 1.000 || CLKOUT0_DIVIDE_F_REG > 128.000)) begin $display("Error: [Unisim %s-109] CLKOUT0_DIVIDE_F attribute is set to %f. Legal values for this attribute are 1.000 to 128.000. Instance: %m", MODULE_NAME, CLKOUT0_DIVIDE_F_REG); attr_err = 1'b1; end if ((attr_test == 1'b1) || (CLKOUT0_DUTY_CYCLE_REG < 0.001 || CLKOUT0_DUTY_CYCLE_REG > 0.999)) begin $display("Error: [Unisim %s-110] CLKOUT0_DUTY_CYCLE attribute is set to %f. Legal values for this attribute are 0.001 to 0.999. Instance: %m", MODULE_NAME, CLKOUT0_DUTY_CYCLE_REG); attr_err = 1'b1; end if ((attr_test == 1'b1) || (CLKOUT0_PHASE_REG < -360.000 || CLKOUT0_PHASE_REG > 360.000)) begin $display("Error: [Unisim %s-111] CLKOUT0_PHASE attribute is set to %f. Legal values for this attribute are -360.000 to 360.000. Instance: %m", MODULE_NAME, CLKOUT0_PHASE_REG); attr_err = 1'b1; end if ((attr_test == 1'b1) || ((CLKOUT0_USE_FINE_PS_REG != "TRUE") && (CLKOUT0_USE_FINE_PS_REG != "FALSE"))) begin $display("Error: [Unisim %s-112] CLKOUT0_USE_FINE_PS attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, CLKOUT0_USE_FINE_PS_REG); attr_err = 1'b1; end if ((attr_test == 1'b1) || ((CLKOUT1_DIVIDE_REG < 1) || (CLKOUT1_DIVIDE_REG > 128))) begin $display("Error: [Unisim %s-113] CLKOUT1_DIVIDE attribute is set to %d. Legal values for this attribute are 1 to 128. Instance: %m", MODULE_NAME, CLKOUT1_DIVIDE_REG); attr_err = 1'b1; end if ((attr_test == 1'b1) || (CLKOUT1_DUTY_CYCLE_REG < 0.001 || CLKOUT1_DUTY_CYCLE_REG > 0.999)) begin $display("Error: [Unisim %s-114] CLKOUT1_DUTY_CYCLE attribute is set to %f. Legal values for this attribute are 0.001 to 0.999. Instance: %m", MODULE_NAME, CLKOUT1_DUTY_CYCLE_REG); attr_err = 1'b1; end if ((attr_test == 1'b1) || (CLKOUT1_PHASE_REG < -360.000 || CLKOUT1_PHASE_REG > 360.000)) begin $display("Error: [Unisim %s-115] CLKOUT1_PHASE attribute is set to %f. Legal values for this attribute are -360.000 to 360.000. Instance: %m", MODULE_NAME, CLKOUT1_PHASE_REG); attr_err = 1'b1; end if ((attr_test == 1'b1) || ((CLKOUT1_USE_FINE_PS_REG != "TRUE") && (CLKOUT1_USE_FINE_PS_REG != "FALSE"))) begin $display("Error: [Unisim %s-116] CLKOUT1_USE_FINE_PS attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, CLKOUT1_USE_FINE_PS_REG); attr_err = 1'b1; end if ((attr_test == 1'b1) || ((CLKOUT2_DIVIDE_REG < 1) || (CLKOUT2_DIVIDE_REG > 128))) begin $display("Error: [Unisim %s-117] CLKOUT2_DIVIDE attribute is set to %d. Legal values for this attribute are 1 to 128. Instance: %m", MODULE_NAME, CLKOUT2_DIVIDE_REG); attr_err = 1'b1; end if ((attr_test == 1'b1) || (CLKOUT2_DUTY_CYCLE_REG < 0.001 || CLKOUT2_DUTY_CYCLE_REG > 0.999)) begin $display("Error: [Unisim %s-118] CLKOUT2_DUTY_CYCLE attribute is set to %f. Legal values for this attribute are 0.001 to 0.999. Instance: %m", MODULE_NAME, CLKOUT2_DUTY_CYCLE_REG); attr_err = 1'b1; end if ((attr_test == 1'b1) || (CLKOUT2_PHASE_REG < -360.000 || CLKOUT2_PHASE_REG > 360.000)) begin $display("Error: [Unisim %s-119] CLKOUT2_PHASE attribute is set to %f. Legal values for this attribute are -360.000 to 360.000. Instance: %m", MODULE_NAME, CLKOUT2_PHASE_REG); attr_err = 1'b1; end if ((attr_test == 1'b1) || ((CLKOUT2_USE_FINE_PS_REG != "TRUE") && (CLKOUT2_USE_FINE_PS_REG != "FALSE"))) begin $display("Error: [Unisim %s-120] CLKOUT2_USE_FINE_PS attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, CLKOUT2_USE_FINE_PS_REG); attr_err = 1'b1; end if ((attr_test == 1'b1) || ((CLKOUT3_DIVIDE_REG < 1) || (CLKOUT3_DIVIDE_REG > 128))) begin $display("Error: [Unisim %s-121] CLKOUT3_DIVIDE attribute is set to %d. Legal values for this attribute are 1 to 128. Instance: %m", MODULE_NAME, CLKOUT3_DIVIDE_REG); attr_err = 1'b1; end if ((attr_test == 1'b1) || (CLKOUT3_DUTY_CYCLE_REG < 0.001 || CLKOUT3_DUTY_CYCLE_REG > 0.999)) begin $display("Error: [Unisim %s-122] CLKOUT3_DUTY_CYCLE attribute is set to %f. Legal values for this attribute are 0.001 to 0.999. Instance: %m", MODULE_NAME, CLKOUT3_DUTY_CYCLE_REG); attr_err = 1'b1; end if ((attr_test == 1'b1) || (CLKOUT3_PHASE_REG < -360.000 || CLKOUT3_PHASE_REG > 360.000)) begin $display("Error: [Unisim %s-123] CLKOUT3_PHASE attribute is set to %f. Legal values for this attribute are -360.000 to 360.000. Instance: %m", MODULE_NAME, CLKOUT3_PHASE_REG); attr_err = 1'b1; end if ((attr_test == 1'b1) || ((CLKOUT3_USE_FINE_PS_REG != "TRUE") && (CLKOUT3_USE_FINE_PS_REG != "FALSE"))) begin $display("Error: [Unisim %s-124] CLKOUT3_USE_FINE_PS attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, CLKOUT3_USE_FINE_PS_REG); attr_err = 1'b1; end if ((attr_test == 1'b1) || ((CLKOUT4_CASCADE_REG != "FALSE") && (CLKOUT4_CASCADE_REG != "TRUE"))) begin $display("Error: [Unisim %s-125] CLKOUT4_CASCADE attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, CLKOUT4_CASCADE_REG); attr_err = 1'b1; end clkout4_cascade_int = (CLKOUT4_CASCADE_REG == "TRUE") ? 1'b1 : 1'b0; if ((attr_test == 1'b1) || ((CLKOUT4_DIVIDE_REG < 1) || (CLKOUT4_DIVIDE_REG > 128))) begin $display("Error: [Unisim %s-126] CLKOUT4_DIVIDE attribute is set to %d. Legal values for this attribute are 1 to 128. Instance: %m", MODULE_NAME, CLKOUT4_DIVIDE_REG); attr_err = 1'b1; end if ((attr_test == 1'b1) || (CLKOUT4_DUTY_CYCLE_REG < 0.001 || CLKOUT4_DUTY_CYCLE_REG > 0.999)) begin $display("Error: [Unisim %s-127] CLKOUT4_DUTY_CYCLE attribute is set to %f. Legal values for this attribute are 0.001 to 0.999. Instance: %m", MODULE_NAME, CLKOUT4_DUTY_CYCLE_REG); attr_err = 1'b1; end if ((attr_test == 1'b1) || (CLKOUT4_PHASE_REG < -360.000 || CLKOUT4_PHASE_REG > 360.000)) begin $display("Error: [Unisim %s-128] CLKOUT4_PHASE attribute is set to %f. Legal values for this attribute are -360.000 to 360.000. Instance: %m", MODULE_NAME, CLKOUT4_PHASE_REG); attr_err = 1'b1; end if ((attr_test == 1'b1) || ((CLKOUT4_USE_FINE_PS_REG != "TRUE") && (CLKOUT4_USE_FINE_PS_REG != "FALSE"))) begin $display("Error: [Unisim %s-129] CLKOUT4_USE_FINE_PS attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, CLKOUT4_USE_FINE_PS_REG); attr_err = 1'b1; end if ((attr_test == 1'b1) || ((CLKOUT5_DIVIDE_REG < 1) || (CLKOUT5_DIVIDE_REG > 128))) begin $display("Error: [Unisim %s-130] CLKOUT5_DIVIDE attribute is set to %d. Legal values for this attribute are 1 to 128. Instance: %m", MODULE_NAME, CLKOUT5_DIVIDE_REG); attr_err = 1'b1; end if ((attr_test == 1'b1) || (CLKOUT5_DUTY_CYCLE_REG < 0.001 || CLKOUT5_DUTY_CYCLE_REG > 0.999)) begin $display("Error: [Unisim %s-131] CLKOUT5_DUTY_CYCLE attribute is set to %f. Legal values for this attribute are 0.001 to 0.999. Instance: %m", MODULE_NAME, CLKOUT5_DUTY_CYCLE_REG); attr_err = 1'b1; end if ((attr_test == 1'b1) || (CLKOUT5_PHASE_REG < -360.000 || CLKOUT5_PHASE_REG > 360.000)) begin $display("Error: [Unisim %s-132] CLKOUT5_PHASE attribute is set to %f. Legal values for this attribute are -360.000 to 360.000. Instance: %m", MODULE_NAME, CLKOUT5_PHASE_REG); attr_err = 1'b1; end if ((attr_test == 1'b1) || ((CLKOUT5_USE_FINE_PS_REG != "TRUE") && (CLKOUT5_USE_FINE_PS_REG != "FALSE"))) begin $display("Error: [Unisim %s-133] CLKOUT5_USE_FINE_PS attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, CLKOUT5_USE_FINE_PS_REG); attr_err = 1'b1; end if ((attr_test == 1'b1) || ((CLKOUT6_DIVIDE_REG < 1) || (CLKOUT6_DIVIDE_REG > 128))) begin $display("Error: [Unisim %s-134] CLKOUT6_DIVIDE attribute is set to %d. Legal values for this attribute are 1 to 128. Instance: %m", MODULE_NAME, CLKOUT6_DIVIDE_REG); attr_err = 1'b1; end if ((attr_test == 1'b1) || (CLKOUT6_DUTY_CYCLE_REG < 0.001 || CLKOUT6_DUTY_CYCLE_REG > 0.999)) begin $display("Error: [Unisim %s-135] CLKOUT6_DUTY_CYCLE attribute is set to %f. Legal values for this attribute are 0.001 to 0.999. Instance: %m", MODULE_NAME, CLKOUT6_DUTY_CYCLE_REG); attr_err = 1'b1; end if ((attr_test == 1'b1) || (CLKOUT6_PHASE_REG < -360.000 || CLKOUT6_PHASE_REG > 360.000)) begin $display("Error: [Unisim %s-136] CLKOUT6_PHASE attribute is set to %f. Legal values for this attribute are -360.000 to 360.000. Instance: %m", MODULE_NAME, CLKOUT6_PHASE_REG); attr_err = 1'b1; end if ((attr_test == 1'b1) || ((CLKOUT6_USE_FINE_PS_REG != "TRUE") && (CLKOUT6_USE_FINE_PS_REG != "FALSE"))) begin $display("Error: [Unisim %s-137] CLKOUT6_USE_FINE_PS attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, CLKOUT6_USE_FINE_PS_REG); attr_err = 1'b1; end `ifdef XIL_TIMING if ((attr_test == 1'b1) || (CLKPFD_FREQ_MAX_REG < 450.000 || CLKPFD_FREQ_MAX_REG > 550.000)) begin $display("Error: [Unisim %s-138] CLKPFD_FREQ_MAX attribute is set to %f. Legal values for this attribute are 450.000 to 550.000. Instance: %m", MODULE_NAME, CLKPFD_FREQ_MAX_REG); attr_err = 1'b1; end if ((attr_test == 1'b1) || (CLKPFD_FREQ_MIN_REG < 10.000 || CLKPFD_FREQ_MIN_REG > 10.000)) begin $display("Error: [Unisim %s-139] CLKPFD_FREQ_MIN attribute is set to %f. Legal values for this attribute are 10.000 to 10.000. Instance: %m", MODULE_NAME, CLKPFD_FREQ_MIN_REG); attr_err = 1'b1; end `endif if ((attr_test == 1'b1) || ((COMPENSATION_REG != "ZHOLD") && (COMPENSATION_REG != "BUF_IN") && (COMPENSATION_REG != "EXTERNAL") && (COMPENSATION_REG != "INTERNAL"))) begin $display("Error: [Unisim %s-140] COMPENSATION attribute is set to %s. Legal values for this attribute are ZHOLD, BUF_IN, EXTERNAL or INTERNAL. Instance: %m", MODULE_NAME, COMPENSATION_REG); attr_err = 1'b1; end if ((attr_test == 1'b1) || ((DIVCLK_DIVIDE_REG < 1) || (DIVCLK_DIVIDE_REG > 106))) begin $display("Error: [Unisim %s-141] DIVCLK_DIVIDE attribute is set to %d. Legal values for this attribute are 1 to 106. Instance: %m", MODULE_NAME, DIVCLK_DIVIDE_REG); attr_err = 1'b1; end if ((attr_test == 1'b1) || ((IS_CLKINSEL_INVERTED_REG !== 1'b0) && (IS_CLKINSEL_INVERTED_REG !== 1'b1))) begin $display("Error: [Unisim %s-145] IS_CLKINSEL_INVERTED attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, IS_CLKINSEL_INVERTED_REG); attr_err = 1'b1; end if ((attr_test == 1'b1) || ((IS_PSEN_INVERTED_REG !== 1'b0) && (IS_PSEN_INVERTED_REG !== 1'b1))) begin $display("Error: [Unisim %s-146] IS_PSEN_INVERTED attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, IS_PSEN_INVERTED_REG); attr_err = 1'b1; end if ((attr_test == 1'b1) || ((IS_PSINCDEC_INVERTED_REG !== 1'b0) && (IS_PSINCDEC_INVERTED_REG !== 1'b1))) begin $display("Error: [Unisim %s-147] IS_PSINCDEC_INVERTED attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, IS_PSINCDEC_INVERTED_REG); attr_err = 1'b1; end if ((attr_test == 1'b1) || ((IS_PWRDWN_INVERTED_REG !== 1'b0) && (IS_PWRDWN_INVERTED_REG !== 1'b1))) begin $display("Error: [Unisim %s-148] IS_PWRDWN_INVERTED attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, IS_PWRDWN_INVERTED_REG); attr_err = 1'b1; end if ((attr_test == 1'b1) || ((IS_RST_INVERTED_REG !== 1'b0) && (IS_RST_INVERTED_REG !== 1'b1))) begin $display("Error: [Unisim %s-149] IS_RST_INVERTED attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, IS_RST_INVERTED_REG); attr_err = 1'b1; end if ((attr_test == 1'b1) || (REF_JITTER1_REG < 0.000 || REF_JITTER1_REG > 0.999)) begin $display("Error: [Unisim %s-150] REF_JITTER1 attribute is set to %f. Legal values for this attribute are 0.000 to 0.999. Instance: %m", MODULE_NAME, REF_JITTER1_REG); attr_err = 1'b1; end if ((attr_test == 1'b1) || (REF_JITTER2_REG < 0.000 || REF_JITTER2_REG > 0.999)) begin $display("Error: [Unisim %s-151] REF_JITTER2 attribute is set to %f. Legal values for this attribute are 0.000 to 0.999. Instance: %m", MODULE_NAME, REF_JITTER2_REG); attr_err = 1'b1; end if ((attr_test == 1'b1) || ((SS_EN_REG != "FALSE") && (SS_EN_REG != "TRUE"))) begin $display("Error: [Unisim %s-152] SS_EN attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, SS_EN_REG); attr_err = 1'b1; end if ((attr_test == 1'b1) || ((SS_MODE_REG != "CENTER_HIGH") && (SS_MODE_REG != "CENTER_LOW") && (SS_MODE_REG != "DOWN_HIGH") && (SS_MODE_REG != "DOWN_LOW"))) begin $display("Error: [Unisim %s-153] SS_MODE attribute is set to %s. Legal values for this attribute are CENTER_HIGH, CENTER_LOW, DOWN_HIGH or DOWN_LOW. Instance: %m", MODULE_NAME, SS_MODE_REG); attr_err = 1'b1; end if ((attr_test == 1'b1) || ((SS_MOD_PERIOD_REG < 4000) || (SS_MOD_PERIOD_REG > 40000))) begin $display("Error: [Unisim %s-154] SS_MOD_PERIOD attribute is set to %d. Legal values for this attribute are 4000 to 40000. Instance: %m", MODULE_NAME, SS_MOD_PERIOD_REG); attr_err = 1'b1; end if ((attr_test == 1'b1) || ((STARTUP_WAIT_REG != "TRUE") && (STARTUP_WAIT_REG != "FALSE"))) begin $display("Error: [Unisim %s-155] STARTUP_WAIT attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, STARTUP_WAIT_REG); attr_err = 1'b1; end startup_wait_sig = (STARTUP_WAIT_REG == "TRUE") ? 1'b1 : 1'b0; `ifdef XIL_TIMING if ((attr_test == 1'b1) || (VCOCLK_FREQ_MAX_REG < 1200.000 || VCOCLK_FREQ_MAX_REG > 1600.000)) begin $display("Error: [Unisim %s-156] VCOCLK_FREQ_MAX attribute is set to %f. Legal values for this attribute are 1200.000 to 1600.000. Instance: %m", MODULE_NAME, VCOCLK_FREQ_MAX_REG); attr_err = 1'b1; end if ((attr_test == 1'b1) || (VCOCLK_FREQ_MIN_REG < VF_MIN || VCOCLK_FREQ_MIN_REG > VF_MIN)) begin $display("Error: [Unisim %s-157] VCOCLK_FREQ_MIN attribute is set to %f. Legal values for this attribute are %3.3f. Instance: %m", MODULE_NAME, VCOCLK_FREQ_MIN_REG, VF_MIN); attr_err = 1'b1; end `endif if (attr_err == 1'b1) #1 $finish; if (CLKOUT0_DIVIDE_F_REG > 1.0000 && CLKOUT0_DIVIDE_F_REG < 2.0000) begin $display("Error: [Unisim %s-2] The Attribute CLKOUT0_DIVIDE_F is set to %f. Values in range of greater than 1 and less than 2 are not allowed. Instance %m", MODULE_NAME, CLKOUT0_DIVIDE_F_REG); #1 $finish; end CLKOUT0_DIVIDE_F_RND = $itor($rtoi((CLKOUT0_DIVIDE_F_REG + 0.0625) * 8.0)) / 8.0; CLKFBOUT_MULT_F_RND = $itor($rtoi((CLKFBOUT_MULT_F_REG + 0.0625) * 8.0)) / 8.0; if (CLKFBOUT_MULT_F_RND < CLKFBOUT_MULT_F_REG) begin $display(" Warning [Unisim %s-35]: CLKFBOUT_MULT_F is not set to a resolution of .125 (%f) and is being rounded down to (%f). Instance %m ", MODULE_NAME, CLKFBOUT_MULT_F_REG, CLKFBOUT_MULT_F_RND); end else if (CLKFBOUT_MULT_F_RND > CLKFBOUT_MULT_F_REG) begin $display(" Warning: [Unisim %s-36]: CLKFBOUT_MULT_F is not set to a resolution of .125 (%f) and is being rounded up to (%f). Instance %m ", MODULE_NAME, CLKFBOUT_MULT_F_REG, CLKFBOUT_MULT_F_RND); end if (CLKOUT0_DIVIDE_F_RND < CLKOUT0_DIVIDE_F_REG) begin $display(" Warning: [Unisim %s-37]: CLKOUT0_DIVIDE_F is not set to a resolution of .125 (%f) and is being rounded down to (%f). Instance %m ", MODULE_NAME, CLKOUT0_DIVIDE_F_REG, CLKOUT0_DIVIDE_F_RND); end else if (CLKOUT0_DIVIDE_F_RND > CLKOUT0_DIVIDE_F_REG) begin $display(" Warning: [Unisim %s-38]: CLKOUT0_DIVIDE_F is not set to a resolution of .125 (%f) and is being rounded up to (%f). Instance %m ", MODULE_NAME, CLKOUT0_DIVIDE_F_REG, CLKOUT0_DIVIDE_F_RND); end clkfbout_f_div = CLKFBOUT_MULT_F_RND; attr_to_mc(clkfbout_pm_f, clkfbout_wf_f, clkfbout_frac, clkfbout_frac_en, clkfbout_wf_r, clkfbout_mx, clkfbout_e, clkfbout_nc, clkfbout_dt, clkfbout_pm_r, clkfbout_en, clkfbout_ht, clkfbout_lt, CLKFBOUT_MULT_F_REG, CLKFBOUT_PHASE_REG, clkfbout_duty); ht_calc(clkfbout_frac, clkfbout_frac_en, clkfbout_e, clkfbout_ht, clkfbout_lt, clkfbout_f_div, clkfbout_rsel, clkfbout_fsel, clkfbout_fht, clkfbout_flt, clkfbout_cnt_max, clkfbout_cnt_ht, clkfbout_div); clk0_f_div = CLKOUT0_DIVIDE_F_RND; attr_to_mc(clk0_pm_f, clk0_wf_f, clk0_frac, clk0_frac_en, clk0_wf_r, clk0_mx, clk0_e, clk0_nc, clk0_dt, clk0_pm_r, clk0_en, clk0_ht, clk0_lt, CLKOUT0_DIVIDE_F_REG, CLKOUT0_PHASE_REG, CLKOUT0_DUTY_CYCLE_REG); ht_calc(clk0_frac, clk0_frac_en, clk0_e, clk0_ht, clk0_lt, clk0_f_div, clk0_rsel, clk0_fsel, clk0_fht, clk0_flt, clk0_cnt_max, clk0_cnt_ht, clk0_div); clk1_div = CLKOUT1_DIVIDE_REG; attr_to_mc(d_pm_f, d_wf_f, d_frac, d_frac_en, d_wf_r, clk1_mx, clk1_e, clk1_nc, clk1_dt, clk1_pm, clk1_en, clk1_ht, clk1_lt, CLKOUT1_DIVIDE_REG, CLKOUT1_PHASE_REG, CLKOUT1_DUTY_CYCLE_REG); ht_calc(3'b0, 1'b0, clk1_e, clk1_ht, clk1_lt, clk1_div, d_rsel, d_fsel, d_fht, d_flt, clk1_cnt_max, clk1_cnt_ht, d_div); clk2_div = CLKOUT2_DIVIDE_REG; attr_to_mc(d_pm_f, d_wf_f, d_frac, d_frac_en, d_wf_r, clk2_mx, clk2_e, clk2_nc, clk2_dt, clk2_pm, clk2_en, clk2_ht, clk2_lt, CLKOUT2_DIVIDE_REG, CLKOUT2_PHASE_REG, CLKOUT2_DUTY_CYCLE_REG); ht_calc(3'b0, 1'b0, clk2_e, clk2_ht, clk2_lt, clk2_div, d_rsel, d_fsel, d_fht, d_flt, clk2_cnt_max, clk2_cnt_ht, d_div); clk3_div = CLKOUT3_DIVIDE_REG; attr_to_mc(d_pm_f, d_wf_f, d_frac, d_frac_en, d_wf_r, clk3_mx, clk3_e, clk3_nc, clk3_dt, clk3_pm, clk3_en, clk3_ht, clk3_lt, CLKOUT3_DIVIDE_REG, CLKOUT3_PHASE_REG, CLKOUT3_DUTY_CYCLE_REG); ht_calc(3'b0, 1'b0, clk3_e, clk3_ht, clk3_lt, clk3_div, d_rsel, d_fsel, d_fht, d_flt, clk3_cnt_max, clk3_cnt_ht, d_div); clk4_div = CLKOUT4_DIVIDE_REG; attr_to_mc(d_pm_f, d_wf_f, d_frac, d_frac_en, d_wf_r, clk4_mx, clk4_e, clk4_nc, clk4_dt, clk4_pm, clk4_en, clk4_ht, clk4_lt, CLKOUT4_DIVIDE_REG, CLKOUT4_PHASE_REG, CLKOUT4_DUTY_CYCLE_REG); ht_calc(3'b0, 1'b0, clk4_e, clk4_ht, clk4_lt, clk4_div, d_rsel, d_fsel, d_fht, d_flt, clk4_cnt_max, clk4_cnt_ht, d_div); clk5_div = CLKOUT5_DIVIDE_REG; attr_to_mc(d_pm_f, d_wf_f, d_frac, d_frac_en, d_wf_r, clk5_mx, clk5_e, clk5_nc, clk5_dt, clk5_pm, clk5_en, clk5_ht, clk5_lt, CLKOUT5_DIVIDE_REG, CLKOUT5_PHASE_REG, CLKOUT5_DUTY_CYCLE_REG); ht_calc(3'b0, 1'b0, clk5_e, clk5_ht, clk5_lt, clk5_div, d_rsel, d_fsel, d_fht, d_flt, clk5_cnt_max, clk5_cnt_ht, d_div); clk6_div = CLKOUT6_DIVIDE_REG; attr_to_mc(d_pm_f, d_wf_f, d_frac, d_frac_en, d_wf_r, clk6_mx, clk6_e, clk6_nc, clk6_dt, clk6_pm, clk6_en, clk6_ht, clk6_lt, CLKOUT6_DIVIDE_REG, CLKOUT6_PHASE_REG, CLKOUT6_DUTY_CYCLE_REG); ht_calc(3'b0, 1'b0, clk6_e, clk6_ht, clk6_lt, clk6_div, d_rsel, d_fsel, d_fht, d_flt, clk6_cnt_max, clk6_cnt_ht, d_div); divclk_div = DIVCLK_DIVIDE_REG; attr_to_mc(d_pm_f, d_wf_f, d_frac, d_frac_en, d_wf_r, d_mx, divclk_e, divclk_nc, d_dt, d_pm, divclk_en, divclk_ht, divclk_lt, DIVCLK_DIVIDE_REG, 0.000, 0.500); ht_calc(3'b0, 1'b0, divclk_e, divclk_ht, divclk_lt, divclk_div, d_rsel, d_fsel, d_fht, d_flt, divclk_cnt_max, divclk_cnt_ht, d_div); ps_in_init = 0; ps_in_ps = ps_in_init; ps_cnt = 0; if (CLKFBOUT_USE_FINE_PS_REG == "TRUE") begin // if (clkfbout_frac_en == 1) begin // $display("Attribute Syntax Error : The Attribute CLKFBOUT_USE_FINE_PS on %s instance %m is set to %s. This attribute should be set to FALSE when CLKFBOUT_MULT_F has fraction part.", MODULE_NAME, CLKFBOUT_USE_FINE_PS_REG); // $finish; // end // else clkfbout_fps_en = 1; end else clkfbout_fps_en = 0; if (CLKOUT0_USE_FINE_PS_REG == "TRUE") begin // if (clk0_frac_en == 1'b1) begin // $display("Attribute Syntax Error : The Attribute CLKOUT0_USE_FINE_PS on %s instance %m is set to %s. This attribute should be set to FALSE when CLKOUT0_DIVIDE has fraction part.", MODULE_NAME, CLKOUT0_USE_FINE_PS_REG); // $finish; // end // else clk0_fps_en = 1; end else clk0_fps_en = 0; if (CLKOUT1_USE_FINE_PS_REG == "TRUE") clk1_fps_en = 1; else clk1_fps_en = 0; if (CLKOUT2_USE_FINE_PS_REG == "TRUE") clk2_fps_en = 1; else clk2_fps_en = 0; if (CLKOUT3_USE_FINE_PS_REG == "TRUE") clk3_fps_en = 1; else clk3_fps_en = 0; if (CLKOUT4_USE_FINE_PS_REG == "TRUE") clk4_fps_en = 1; else clk4_fps_en = 0; if (CLKOUT5_USE_FINE_PS_REG == "TRUE") clk5_fps_en = 1; else clk5_fps_en = 0; if (CLKOUT6_USE_FINE_PS_REG == "TRUE") clk6_fps_en = 1; else clk6_fps_en = 0; fps_en = clk0_fps_en || clk1_fps_en || clk2_fps_en || clk3_fps_en || clk4_fps_en || clk5_fps_en || clk6_fps_en || clkfbout_fps_en; if (clk0_frac_en == 1'b1) begin if (CLKOUT0_DUTY_CYCLE_REG != 0.5) begin $display("Error: [Unisim %s-3] The Attribute CLKOUT0_DUTY_CYCLE is set to %f. This attribute should be set to 0.5 when CLKOUT0_DIVIDE_F has fraction part. Instance %m", MODULE_NAME, CLKOUT0_DUTY_CYCLE_REG); #100 $finish; end end pll_lfhf = 2'b00; if (BANDWIDTH_REG === "LOW") case (clkfbout_div) 1 : begin pll_cp = 4'b0010; pll_res = 4'b1111; end 2 : begin pll_cp = 4'b0010 ; pll_res = 4'b1111 ; end 3 : begin pll_cp = 4'b0010 ; pll_res = 4'b1111 ; end 4 : begin pll_cp = 4'b0010 ; pll_res = 4'b1111 ; end 5 : begin pll_cp = 4'b0010 ; pll_res = 4'b0111 ; end 6 : begin pll_cp = 4'b0010 ; pll_res = 4'b1011 ; end 7 : begin pll_cp = 4'b0010 ; pll_res = 4'b1101 ; end 8 : begin pll_cp = 4'b0010 ; pll_res = 4'b0011 ; end 9 : begin pll_cp = 4'b0010 ; pll_res = 4'b0101 ; end 10 : begin pll_cp = 4'b0010 ; pll_res = 4'b0101 ; end 11 : begin pll_cp = 4'b0010 ; pll_res = 4'b1001 ; end 12 : begin pll_cp = 4'b0010 ; pll_res = 4'b1110 ; end 13 : begin pll_cp = 4'b0010 ; pll_res = 4'b1110 ; end 14 : begin pll_cp = 4'b0010 ; pll_res = 4'b1110 ; end 15 : begin pll_cp = 4'b0010 ; pll_res = 4'b1110 ; end 16 : begin pll_cp = 4'b0010 ; pll_res = 4'b0001 ; end 17 : begin pll_cp = 4'b0010 ; pll_res = 4'b0001 ; end 18 : begin pll_cp = 4'b0010 ; pll_res = 4'b0001 ; end 19 : begin pll_cp = 4'b0010 ; pll_res = 4'b0110 ; end 20 : begin pll_cp = 4'b0010 ; pll_res = 4'b0110 ; end 21 : begin pll_cp = 4'b0010 ; pll_res = 4'b0110 ; end 22 : begin pll_cp = 4'b0010 ; pll_res = 4'b0110 ; end 23 : begin pll_cp = 4'b0010 ; pll_res = 4'b0110 ; end 24 : begin pll_cp = 4'b0010 ; pll_res = 4'b0110 ; end 25 : begin pll_cp = 4'b0010 ; pll_res = 4'b0110 ; end 26 : begin pll_cp = 4'b0010 ; pll_res = 4'b1010 ; end 27 : begin pll_cp = 4'b0010 ; pll_res = 4'b1010 ; end 28 : begin pll_cp = 4'b0010 ; pll_res = 4'b1010 ; end 29 : begin pll_cp = 4'b0010 ; pll_res = 4'b1010 ; end 30 : begin pll_cp = 4'b0010 ; pll_res = 4'b1010 ; end 31 : begin pll_cp = 4'b0010 ; pll_res = 4'b1100 ; end 32 : begin pll_cp = 4'b0010 ; pll_res = 4'b1100 ; end 33 : begin pll_cp = 4'b0010 ; pll_res = 4'b1100 ; end 34 : begin pll_cp = 4'b0010 ; pll_res = 4'b1100 ; end 35 : begin pll_cp = 4'b0010 ; pll_res = 4'b1100 ; end 36 : begin pll_cp = 4'b0010 ; pll_res = 4'b1100 ; end 37 : begin pll_cp = 4'b0010 ; pll_res = 4'b1100 ; end 38 : begin pll_cp = 4'b0010 ; pll_res = 4'b1100 ; end 39 : begin pll_cp = 4'b0010 ; pll_res = 4'b1100 ; end 40 : begin pll_cp = 4'b0010 ; pll_res = 4'b1100 ; end 41 : begin pll_cp = 4'b0010 ; pll_res = 4'b1100 ; end 42 : begin pll_cp = 4'b0010 ; pll_res = 4'b1100 ; end 43 : begin pll_cp = 4'b0010 ; pll_res = 4'b1100 ; end 44 : begin pll_cp = 4'b0010 ; pll_res = 4'b1100 ; end 45 : begin pll_cp = 4'b0010 ; pll_res = 4'b1100 ; end 46 : begin pll_cp = 4'b0010 ; pll_res = 4'b1100 ; end 47 : begin pll_cp = 4'b0010 ; pll_res = 4'b1100 ; end 48 : begin pll_cp = 4'b0010 ; pll_res = 4'b0010 ; end 49 : begin pll_cp = 4'b0010 ; pll_res = 4'b0010 ; end 50 : begin pll_cp = 4'b0010 ; pll_res = 4'b0010 ; end 51 : begin pll_cp = 4'b0010 ; pll_res = 4'b0010 ; end 52 : begin pll_cp = 4'b0010 ; pll_res = 4'b0010 ; end 53 : begin pll_cp = 4'b0010 ; pll_res = 4'b0010 ; end 54 : begin pll_cp = 4'b0010 ; pll_res = 4'b0010 ; end 55 : begin pll_cp = 4'b0010 ; pll_res = 4'b0010 ; end 56 : begin pll_cp = 4'b0010 ; pll_res = 4'b0010 ; end 57 : begin pll_cp = 4'b0010 ; pll_res = 4'b0010 ; end 58 : begin pll_cp = 4'b0010 ; pll_res = 4'b0010 ; end 59 : begin pll_cp = 4'b0010 ; pll_res = 4'b0010 ; end 60 : begin pll_cp = 4'b0010 ; pll_res = 4'b0010 ; end 61 : begin pll_cp = 4'b0010 ; pll_res = 4'b0010 ; end 62 : begin pll_cp = 4'b0010 ; pll_res = 4'b0010 ; end 63 : begin pll_cp = 4'b0010 ; pll_res = 4'b0010 ; end 64 : begin pll_cp = 4'b0010 ; pll_res = 4'b0010 ; end endcase else if (BANDWIDTH_REG === "HIGH") case (clkfbout_div) 1 : begin pll_cp = 4'b0010; pll_res = 4'b1111; end 2 : begin pll_cp = 4'b0100 ; pll_res = 4'b1111 ; end 3 : begin pll_cp = 4'b0101 ; pll_res = 4'b1011 ; end 4 : begin pll_cp = 4'b0111 ; pll_res = 4'b0111 ; end 5 : begin pll_cp = 4'b1101 ; pll_res = 4'b0111 ; end 6 : begin pll_cp = 4'b1110 ; pll_res = 4'b1011 ; end 7 : begin pll_cp = 4'b1110 ; pll_res = 4'b1101 ; end 8 : begin pll_cp = 4'b1111 ; pll_res = 4'b0011 ; end 9 : begin pll_cp = 4'b1110 ; pll_res = 4'b0101 ; end 10 : begin pll_cp = 4'b1111 ; pll_res = 4'b0101 ; end 11 : begin pll_cp = 4'b1111 ; pll_res = 4'b1001 ; end 12 : begin pll_cp = 4'b1101 ; pll_res = 4'b0001 ; end 13 : begin pll_cp = 4'b1111; pll_res = 4'b1001; end 14 : begin pll_cp = 4'b1111; pll_res = 4'b1001; end 15 : begin pll_cp = 4'b1111; pll_res = 4'b1001; end 16 : begin pll_cp = 4'b1111; pll_res = 4'b1001; end 17 : begin pll_cp = 4'b1111; pll_res = 4'b0101; end 18 : begin pll_cp = 4'b1111; pll_res = 4'b0101; end 19 : begin pll_cp = 4'b1100; pll_res = 4'b0001; end 20 : begin pll_cp = 4'b1100; pll_res = 4'b0001; end 21 : begin pll_cp = 4'b1100; pll_res = 4'b0001; end 22 : begin pll_cp = 4'b0101; pll_res = 4'b1100; end 23 : begin pll_cp = 4'b0101; pll_res = 4'b1100; end 24 : begin pll_cp = 4'b0101; pll_res = 4'b1100; end 25 : begin pll_cp = 4'b0101; pll_res = 4'b1100; end 26 : begin pll_cp = 4'b0011; pll_res = 4'b0100; end 27 : begin pll_cp = 4'b0011; pll_res = 4'b0100; end 28 : begin pll_cp = 4'b0011; pll_res = 4'b0100; end 29 : begin pll_cp = 4'b0011; pll_res = 4'b0100; end 30 : begin pll_cp = 4'b0011; pll_res = 4'b0100; end 31 : begin pll_cp = 4'b0011; pll_res = 4'b0100; end 32 : begin pll_cp = 4'b0011; pll_res = 4'b0100; end 33 : begin pll_cp = 4'b0011; pll_res = 4'b0100; end 34 : begin pll_cp = 4'b0011; pll_res = 4'b0100; end 35 : begin pll_cp = 4'b0011; pll_res = 4'b0100; end 36 : begin pll_cp = 4'b0011; pll_res = 4'b0100; end 37 : begin pll_cp = 4'b0011 ; pll_res = 4'b0100 ; end 38 : begin pll_cp = 4'b0011 ; pll_res = 4'b0100 ; end 39 : begin pll_cp = 4'b0011 ; pll_res = 4'b0100 ; end 40 : begin pll_cp = 4'b0011 ; pll_res = 4'b0100 ; end 41 : begin pll_cp = 4'b0011 ; pll_res = 4'b0100 ; end 42 : begin pll_cp = 4'b0010 ; pll_res = 4'b1000 ; end 43 : begin pll_cp = 4'b0010 ; pll_res = 4'b1000 ; end 44 : begin pll_cp = 4'b0010 ; pll_res = 4'b1000 ; end 45 : begin pll_cp = 4'b0010 ; pll_res = 4'b1000 ; end 46 : begin pll_cp = 4'b0010 ; pll_res = 4'b1000 ; end 47 : begin pll_cp = 4'b0111 ; pll_res = 4'b0001 ; end 48 : begin pll_cp = 4'b0111 ; pll_res = 4'b0001 ; end 49 : begin pll_cp = 4'b0100 ; pll_res = 4'b1100 ; end 50 : begin pll_cp = 4'b0100 ; pll_res = 4'b1100 ; end 51 : begin pll_cp = 4'b0100 ; pll_res = 4'b1100 ; end 52 : begin pll_cp = 4'b0100 ; pll_res = 4'b1100 ; end 53 : begin pll_cp = 4'b0110 ; pll_res = 4'b0001 ; end 54 : begin pll_cp = 4'b0110 ; pll_res = 4'b0001 ; end 55 : begin pll_cp = 4'b0101 ; pll_res = 4'b0110 ; end 56 : begin pll_cp = 4'b0101 ; pll_res = 4'b0110 ; end 57 : begin pll_cp = 4'b0101 ; pll_res = 4'b0110 ; end 58 : begin pll_cp = 4'b0010 ; pll_res = 4'b0100 ; end 59 : begin pll_cp = 4'b0010 ; pll_res = 4'b0100 ; end 60 : begin pll_cp = 4'b0010 ; pll_res = 4'b0100 ; end 61 : begin pll_cp = 4'b0010 ; pll_res = 4'b0100 ; end 62 : begin pll_cp = 4'b0100 ; pll_res = 4'b1010 ; end 63 : begin pll_cp = 4'b0011 ; pll_res = 4'b1100 ; end 64 : begin pll_cp = 4'b0011 ; pll_res = 4'b1100 ; end endcase else if (BANDWIDTH_REG === "OPTIMIZED") case (clkfbout_div) 1 : begin pll_cp = 4'b0010; pll_res = 4'b1111; end 2 : begin pll_cp = 4'b0100 ; pll_res = 4'b1111 ; end 3 : begin pll_cp = 4'b0101 ; pll_res = 4'b1011 ; end 4 : begin pll_cp = 4'b0111 ; pll_res = 4'b0111 ; end 5 : begin pll_cp = 4'b1101 ; pll_res = 4'b0111 ; end 6 : begin pll_cp = 4'b1110 ; pll_res = 4'b1011 ; end 7 : begin pll_cp = 4'b1110 ; pll_res = 4'b1101 ; end 8 : begin pll_cp = 4'b1111 ; pll_res = 4'b0011 ; end 9 : begin pll_cp = 4'b1110 ; pll_res = 4'b0101 ; end 10 : begin pll_cp = 4'b1111 ; pll_res = 4'b0101 ; end 11 : begin pll_cp = 4'b1111 ; pll_res = 4'b1001 ; end 12 : begin pll_cp = 4'b1101 ; pll_res = 4'b0001 ; end 13 : begin pll_cp = 4'b1111; pll_res = 4'b1001; end 14 : begin pll_cp = 4'b1111; pll_res = 4'b1001; end 15 : begin pll_cp = 4'b1111; pll_res = 4'b1001; end 16 : begin pll_cp = 4'b1111; pll_res = 4'b1001; end 17 : begin pll_cp = 4'b1111; pll_res = 4'b0101; end 18 : begin pll_cp = 4'b1111; pll_res = 4'b0101; end 19 : begin pll_cp = 4'b1100; pll_res = 4'b0001; end 20 : begin pll_cp = 4'b1100; pll_res = 4'b0001; end 21 : begin pll_cp = 4'b1100; pll_res = 4'b0001; end 22 : begin pll_cp = 4'b0101; pll_res = 4'b1100; end 23 : begin pll_cp = 4'b0101; pll_res = 4'b1100; end 24 : begin pll_cp = 4'b0101; pll_res = 4'b1100; end 25 : begin pll_cp = 4'b0101; pll_res = 4'b1100; end 26 : begin pll_cp = 4'b0011; pll_res = 4'b0100; end 27 : begin pll_cp = 4'b0011; pll_res = 4'b0100; end 28 : begin pll_cp = 4'b0011; pll_res = 4'b0100; end 29 : begin pll_cp = 4'b0011; pll_res = 4'b0100; end 30 : begin pll_cp = 4'b0011; pll_res = 4'b0100; end 31 : begin pll_cp = 4'b0011; pll_res = 4'b0100; end 32 : begin pll_cp = 4'b0011; pll_res = 4'b0100; end 33 : begin pll_cp = 4'b0011; pll_res = 4'b0100; end 34 : begin pll_cp = 4'b0011; pll_res = 4'b0100; end 35 : begin pll_cp = 4'b0011; pll_res = 4'b0100; end 36 : begin pll_cp = 4'b0011; pll_res = 4'b0100; end 37 : begin pll_cp = 4'b0011 ; pll_res = 4'b0100 ; end 38 : begin pll_cp = 4'b0011 ; pll_res = 4'b0100 ; end 39 : begin pll_cp = 4'b0011 ; pll_res = 4'b0100 ; end 40 : begin pll_cp = 4'b0011 ; pll_res = 4'b0100 ; end 41 : begin pll_cp = 4'b0011 ; pll_res = 4'b0100 ; end 42 : begin pll_cp = 4'b0010 ; pll_res = 4'b1000 ; end 43 : begin pll_cp = 4'b0010 ; pll_res = 4'b1000 ; end 44 : begin pll_cp = 4'b0010 ; pll_res = 4'b1000 ; end 45 : begin pll_cp = 4'b0010 ; pll_res = 4'b1000 ; end 46 : begin pll_cp = 4'b0010 ; pll_res = 4'b1000 ; end 47 : begin pll_cp = 4'b0111 ; pll_res = 4'b0001 ; end 48 : begin pll_cp = 4'b0111 ; pll_res = 4'b0001 ; end 49 : begin pll_cp = 4'b0100 ; pll_res = 4'b1100 ; end 50 : begin pll_cp = 4'b0100 ; pll_res = 4'b1100 ; end 51 : begin pll_cp = 4'b0100 ; pll_res = 4'b1100 ; end 52 : begin pll_cp = 4'b0100 ; pll_res = 4'b1100 ; end 53 : begin pll_cp = 4'b0110 ; pll_res = 4'b0001 ; end 54 : begin pll_cp = 4'b0110 ; pll_res = 4'b0001 ; end 55 : begin pll_cp = 4'b0101 ; pll_res = 4'b0110 ; end 56 : begin pll_cp = 4'b0101 ; pll_res = 4'b0110 ; end 57 : begin pll_cp = 4'b0101 ; pll_res = 4'b0110 ; end 58 : begin pll_cp = 4'b0010 ; pll_res = 4'b0100 ; end 59 : begin pll_cp = 4'b0010 ; pll_res = 4'b0100 ; end 60 : begin pll_cp = 4'b0010 ; pll_res = 4'b0100 ; end 61 : begin pll_cp = 4'b0010 ; pll_res = 4'b0100 ; end 62 : begin pll_cp = 4'b0100 ; pll_res = 4'b1010 ; end 63 : begin pll_cp = 4'b0011 ; pll_res = 4'b1100 ; end 64 : begin pll_cp = 4'b0011 ; pll_res = 4'b1100 ; end endcase case (clkfbout_div) 1 : begin drp_lock_ref_dly = 5'd6; drp_lock_fb_dly = 5'd6; drp_lock_cnt = 10'd1000; drp_lock_sat_high = 10'd1001; drp_unlock_cnt = 10'd1; end 2 : begin drp_lock_ref_dly = 5'd6; drp_lock_fb_dly = 5'd6; drp_lock_cnt = 10'd1000; drp_lock_sat_high = 10'd1001; drp_unlock_cnt = 10'd1; end 3 : begin drp_lock_ref_dly = 5'd8; drp_lock_fb_dly = 5'd8; drp_lock_cnt = 10'd1000; drp_lock_sat_high = 10'd1001; drp_unlock_cnt = 10'd1; end 4 : begin drp_lock_ref_dly = 5'd11; drp_lock_fb_dly = 5'd11; drp_lock_cnt = 10'd1000; drp_lock_sat_high = 10'd1001; drp_unlock_cnt = 10'd1; end 5 : begin drp_lock_ref_dly = 5'd14; drp_lock_fb_dly = 5'd14; drp_lock_cnt = 10'd1000; drp_lock_sat_high = 10'd1001; drp_unlock_cnt = 10'd1; end 6 : begin drp_lock_ref_dly = 5'd17; drp_lock_fb_dly = 5'd17; drp_lock_cnt = 10'd1000; drp_lock_sat_high = 10'd1001; drp_unlock_cnt = 10'd1; end 7 : begin drp_lock_ref_dly = 5'd19; drp_lock_fb_dly = 5'd19; drp_lock_cnt = 10'd1000; drp_lock_sat_high = 10'd1001; drp_unlock_cnt = 10'd1; end 8 : begin drp_lock_ref_dly = 5'd22; drp_lock_fb_dly = 5'd22; drp_lock_cnt = 10'd1000; drp_lock_sat_high = 10'd1001; drp_unlock_cnt = 10'd1; end 9 : begin drp_lock_ref_dly = 5'd25; drp_lock_fb_dly = 5'd25; drp_lock_cnt = 10'd1000; drp_lock_sat_high = 10'd1001; drp_unlock_cnt = 10'd1; end 10 : begin drp_lock_ref_dly = 5'd28; drp_lock_fb_dly = 5'd28; drp_lock_cnt = 10'd1000; drp_lock_sat_high = 10'd1001; drp_unlock_cnt = 10'd1; end 11 : begin drp_lock_ref_dly = 5'd31; drp_lock_fb_dly = 5'd31; drp_lock_cnt = 10'd900; drp_lock_sat_high = 10'd1001; drp_unlock_cnt = 10'd1; end 12 : begin drp_lock_ref_dly = 5'd31; drp_lock_fb_dly = 5'd31; drp_lock_cnt = 10'd825; drp_lock_sat_high = 10'd1001; drp_unlock_cnt = 10'd1; end 13 : begin drp_lock_ref_dly = 5'd31; drp_lock_fb_dly = 5'd31; drp_lock_cnt = 10'd750; drp_lock_sat_high = 10'd1001; drp_unlock_cnt = 10'd1; end 14 : begin drp_lock_ref_dly = 5'd31; drp_lock_fb_dly = 5'd31; drp_lock_cnt = 10'd700; drp_lock_sat_high = 10'd1001; drp_unlock_cnt = 10'd1; end 15 : begin drp_lock_ref_dly = 5'd31; drp_lock_fb_dly = 5'd31; drp_lock_cnt = 10'd650; drp_lock_sat_high = 10'd1001; drp_unlock_cnt = 10'd1; end 16 : begin drp_lock_ref_dly = 5'd31; drp_lock_fb_dly = 5'd31; drp_lock_cnt = 10'd625; drp_lock_sat_high = 10'd1001; drp_unlock_cnt = 10'd1; end 17 : begin drp_lock_ref_dly = 5'd31; drp_lock_fb_dly = 5'd31; drp_lock_cnt = 10'd575; drp_lock_sat_high = 10'd1001; drp_unlock_cnt = 10'd1; end 18 : begin drp_lock_ref_dly = 5'd31; drp_lock_fb_dly = 5'd31; drp_lock_cnt = 10'd550; drp_lock_sat_high = 10'd1001; drp_unlock_cnt = 10'd1; end 19 : begin drp_lock_ref_dly = 5'd31; drp_lock_fb_dly = 5'd31; drp_lock_cnt = 10'd525; drp_lock_sat_high = 10'd1001; drp_unlock_cnt = 10'd1; end 20 : begin drp_lock_ref_dly = 5'd31; drp_lock_fb_dly = 5'd31; drp_lock_cnt = 10'd500; drp_lock_sat_high = 10'd1001; drp_unlock_cnt = 10'd1; end 21 : begin drp_lock_ref_dly = 5'd31; drp_lock_fb_dly = 5'd31; drp_lock_cnt = 10'd475; drp_lock_sat_high = 10'd1001; drp_unlock_cnt = 10'd1; end 22 : begin drp_lock_ref_dly = 5'd31; drp_lock_fb_dly = 5'd31; drp_lock_cnt = 10'd450; drp_lock_sat_high = 10'd1001; drp_unlock_cnt = 10'd1; end 23 : begin drp_lock_ref_dly = 5'd31; drp_lock_fb_dly = 5'd31; drp_lock_cnt = 10'd425; drp_lock_sat_high = 10'd1001; drp_unlock_cnt = 10'd1; end 24 : begin drp_lock_ref_dly = 5'd31; drp_lock_fb_dly = 5'd31; drp_lock_cnt = 10'd400; drp_lock_sat_high = 10'd1001; drp_unlock_cnt = 10'd1; end 25 : begin drp_lock_ref_dly = 5'd31; drp_lock_fb_dly = 5'd31; drp_lock_cnt = 10'd400; drp_lock_sat_high = 10'd1001; drp_unlock_cnt = 10'd1; end 26 : begin drp_lock_ref_dly = 5'd31; drp_lock_fb_dly = 5'd31; drp_lock_cnt = 10'd375; drp_lock_sat_high = 10'd1001; drp_unlock_cnt = 10'd1; end 27 : begin drp_lock_ref_dly = 5'd31; drp_lock_fb_dly = 5'd31; drp_lock_cnt = 10'd350; drp_lock_sat_high = 10'd1001; drp_unlock_cnt = 10'd1; end 28 : begin drp_lock_ref_dly = 5'd31; drp_lock_fb_dly = 5'd31; drp_lock_cnt = 10'd350; drp_lock_sat_high = 10'd1001; drp_unlock_cnt = 10'd1; end 29 : begin drp_lock_ref_dly = 5'd31; drp_lock_fb_dly = 5'd31; drp_lock_cnt = 10'd325; drp_lock_sat_high = 10'd1001; drp_unlock_cnt = 10'd1; end 30 : begin drp_lock_ref_dly = 5'd31; drp_lock_fb_dly = 5'd31; drp_lock_cnt = 10'd325; drp_lock_sat_high = 10'd1001; drp_unlock_cnt = 10'd1; end 31 : begin drp_lock_ref_dly = 5'd31; drp_lock_fb_dly = 5'd31; drp_lock_cnt = 10'd300; drp_lock_sat_high = 10'd1001; drp_unlock_cnt = 10'd1; end 32 : begin drp_lock_ref_dly = 5'd31; drp_lock_fb_dly = 5'd31; drp_lock_cnt = 10'd300; drp_lock_sat_high = 10'd1001; drp_unlock_cnt = 10'd1; end 33 : begin drp_lock_ref_dly = 5'd31; drp_lock_fb_dly = 5'd31; drp_lock_cnt = 10'd300; drp_lock_sat_high = 10'd1001; drp_unlock_cnt = 10'd1; end 34 : begin drp_lock_ref_dly = 5'd31; drp_lock_fb_dly = 5'd31; drp_lock_cnt = 10'd275; drp_lock_sat_high = 10'd1001; drp_unlock_cnt = 10'd1; end 35 : begin drp_lock_ref_dly = 5'd31; drp_lock_fb_dly = 5'd31; drp_lock_cnt = 10'd275; drp_lock_sat_high = 10'd1001; drp_unlock_cnt = 10'd1; end 36 : begin drp_lock_ref_dly = 5'd31; drp_lock_fb_dly = 5'd31; drp_lock_cnt = 10'd275; drp_lock_sat_high = 10'd1001; drp_unlock_cnt = 10'd1; end 37 : begin drp_lock_ref_dly = 5'd31; drp_lock_fb_dly = 5'd31; drp_lock_cnt = 10'd250; drp_lock_sat_high = 10'd1001; drp_unlock_cnt = 10'd1; end 38 : begin drp_lock_ref_dly = 5'd31; drp_lock_fb_dly = 5'd31; drp_lock_cnt = 10'd250; drp_lock_sat_high = 10'd1001; drp_unlock_cnt = 10'd1; end 39 : begin drp_lock_ref_dly = 5'd31; drp_lock_fb_dly = 5'd31; drp_lock_cnt = 10'd250; drp_lock_sat_high = 10'd1001; drp_unlock_cnt = 10'd1; end 40 : begin drp_lock_ref_dly = 5'd31; drp_lock_fb_dly = 5'd31; drp_lock_cnt = 10'd250; drp_lock_sat_high = 10'd1001; drp_unlock_cnt = 10'd1; end 41 : begin drp_lock_ref_dly = 5'd31; drp_lock_fb_dly = 5'd31; drp_lock_cnt = 10'd250; drp_lock_sat_high = 10'd1001; drp_unlock_cnt = 10'd1; end 42 : begin drp_lock_ref_dly = 5'd31; drp_lock_fb_dly = 5'd31; drp_lock_cnt = 10'd250; drp_lock_sat_high = 10'd1001; drp_unlock_cnt = 10'd1; end 43 : begin drp_lock_ref_dly = 5'd31; drp_lock_fb_dly = 5'd31; drp_lock_cnt = 10'd250; drp_lock_sat_high = 10'd1001; drp_unlock_cnt = 10'd1; end 44 : begin drp_lock_ref_dly = 5'd31; drp_lock_fb_dly = 5'd31; drp_lock_cnt = 10'd250; drp_lock_sat_high = 10'd1001; drp_unlock_cnt = 10'd1; end 45 : begin drp_lock_ref_dly = 5'd31; drp_lock_fb_dly = 5'd31; drp_lock_cnt = 10'd250; drp_lock_sat_high = 10'd1001; drp_unlock_cnt = 10'd1; end 46 : begin drp_lock_ref_dly = 5'd31; drp_lock_fb_dly = 5'd31; drp_lock_cnt = 10'd250; drp_lock_sat_high = 10'd1001; drp_unlock_cnt = 10'd1; end 47 : begin drp_lock_ref_dly = 5'd31; drp_lock_fb_dly = 5'd31; drp_lock_cnt = 10'd250; drp_lock_sat_high = 10'd1001; drp_unlock_cnt = 10'd1; end 48 : begin drp_lock_ref_dly = 5'd31; drp_lock_fb_dly = 5'd31; drp_lock_cnt = 10'd250; drp_lock_sat_high = 10'd1001; drp_unlock_cnt = 10'd1; end 49 : begin drp_lock_ref_dly = 5'd31; drp_lock_fb_dly = 5'd31; drp_lock_cnt = 10'd250; drp_lock_sat_high = 10'd1001; drp_unlock_cnt = 10'd1; end 50 : begin drp_lock_ref_dly = 5'd31; drp_lock_fb_dly = 5'd31; drp_lock_cnt = 10'd250; drp_lock_sat_high = 10'd1001; drp_unlock_cnt = 10'd1; end 51 : begin drp_lock_ref_dly = 5'd31; drp_lock_fb_dly = 5'd31; drp_lock_cnt = 10'd250; drp_lock_sat_high = 10'd1001; drp_unlock_cnt = 10'd1; end 52 : begin drp_lock_ref_dly = 5'd31; drp_lock_fb_dly = 5'd31; drp_lock_cnt = 10'd250; drp_lock_sat_high = 10'd1001; drp_unlock_cnt = 10'd1; end 53 : begin drp_lock_ref_dly = 5'd31; drp_lock_fb_dly = 5'd31; drp_lock_cnt = 10'd250; drp_lock_sat_high = 10'd1001; drp_unlock_cnt = 10'd1; end 54 : begin drp_lock_ref_dly = 5'd31; drp_lock_fb_dly = 5'd31; drp_lock_cnt = 10'd250; drp_lock_sat_high = 10'd1001; drp_unlock_cnt = 10'd1; end 55 : begin drp_lock_ref_dly = 5'd31; drp_lock_fb_dly = 5'd31; drp_lock_cnt = 10'd250; drp_lock_sat_high = 10'd1001; drp_unlock_cnt = 10'd1; end 56 : begin drp_lock_ref_dly = 5'd31; drp_lock_fb_dly = 5'd31; drp_lock_cnt = 10'd250; drp_lock_sat_high = 10'd1001; drp_unlock_cnt = 10'd1; end 57 : begin drp_lock_ref_dly = 5'd31; drp_lock_fb_dly = 5'd31; drp_lock_cnt = 10'd250; drp_lock_sat_high = 10'd1001; drp_unlock_cnt = 10'd1; end 58 : begin drp_lock_ref_dly = 5'd31; drp_lock_fb_dly = 5'd31; drp_lock_cnt = 10'd250; drp_lock_sat_high = 10'd1001; drp_unlock_cnt = 10'd1; end 59 : begin drp_lock_ref_dly = 5'd31; drp_lock_fb_dly = 5'd31; drp_lock_cnt = 10'd250; drp_lock_sat_high = 10'd1001; drp_unlock_cnt = 10'd1; end 60 : begin drp_lock_ref_dly = 5'd31; drp_lock_fb_dly = 5'd31; drp_lock_cnt = 10'd250; drp_lock_sat_high = 10'd1001; drp_unlock_cnt = 10'd1; end 61 : begin drp_lock_ref_dly = 5'd31; drp_lock_fb_dly = 5'd31; drp_lock_cnt = 10'd250; drp_lock_sat_high = 10'd1001; drp_unlock_cnt = 10'd1; end 62 : begin drp_lock_ref_dly = 5'd31; drp_lock_fb_dly = 5'd31; drp_lock_cnt = 10'd250; drp_lock_sat_high = 10'd1001; drp_unlock_cnt = 10'd1; end 63 : begin drp_lock_ref_dly = 5'd31; drp_lock_fb_dly = 5'd31; drp_lock_cnt = 10'd250; drp_lock_sat_high = 10'd1001; drp_unlock_cnt = 10'd1; end 64 : begin drp_lock_ref_dly = 5'd31; drp_lock_fb_dly = 5'd31; drp_lock_cnt = 10'd250; drp_lock_sat_high = 10'd1001; drp_unlock_cnt = 10'd1; end endcase tmp_string = "DIVCLK_DIVIDE"; chk_ok = para_int_range_chk (DIVCLK_DIVIDE_REG, tmp_string, D_MIN, D_MAX); tmp_string = "CLKFBOUT_MULT_F"; chk_ok = para_real_range_chk (CLKFBOUT_MULT_F_RND, tmp_string, M_MIN, M_MAX); tmp_string = "CLKOUT6_DUTY_CYCLE"; chk_ok = clkout_duty_chk (CLKOUT6_DIVIDE_REG, CLKOUT6_DUTY_CYCLE_REG, tmp_string); if(clk0_frac_en == 1'b0) begin tmp_string = "CLKOUT0_DUTY_CYCLE"; chk_ok = clkout_duty_chk (CLKOUT0_DIVIDE_F_RND, CLKOUT0_DUTY_CYCLE_REG, tmp_string); end tmp_string = "CLKOUT5_DUTY_CYCLE"; chk_ok = clkout_duty_chk (CLKOUT5_DIVIDE_REG, CLKOUT5_DUTY_CYCLE_REG, tmp_string); tmp_string = "CLKOUT1_DUTY_CYCLE"; chk_ok = clkout_duty_chk (CLKOUT1_DIVIDE_REG, CLKOUT1_DUTY_CYCLE_REG, tmp_string); tmp_string = "CLKOUT2_DUTY_CYCLE"; chk_ok = clkout_duty_chk (CLKOUT2_DIVIDE_REG, CLKOUT2_DUTY_CYCLE_REG, tmp_string); tmp_string = "CLKOUT3_DUTY_CYCLE"; chk_ok = clkout_duty_chk (CLKOUT3_DIVIDE_REG, CLKOUT3_DUTY_CYCLE_REG, tmp_string); tmp_string = "CLKOUT4_DUTY_CYCLE"; chk_ok = clkout_duty_chk (CLKOUT4_DIVIDE_REG, CLKOUT4_DUTY_CYCLE_REG, tmp_string); period_vco_max = 1000000 / VCOCLK_FREQ_MIN_REG; period_vco_min = 1000000 / VCOCLK_FREQ_MAX_REG; period_vco_target = 1000000 / VCOCLK_FREQ_TARGET; period_vco_target_half = period_vco_target / 2; fb_delay_max = MAX_FEEDBACK_DELAY * MAX_FEEDBACK_DELAY_SCALE; clk0f_product = CLKOUT0_DIVIDE_F_RND * 8; pll_lock_time = 12; lock_period_time = 10; if (clkfbout_frac_en == 1'b1) begin md_product = clkfbout_div * DIVCLK_DIVIDE_REG; m_product = clkfbout_div; mf_product = CLKFBOUT_MULT_F_RND * 8; clkout_en_val = mf_product - 1; m_product2 = clkfbout_div / 2; clkout_en_time = mf_product + 4 + pll_lock_time; locked_en_time = md_product + clkout_en_time + 2; lock_cnt_max = locked_en_time + 16; end else begin md_product = clkfbout_div * DIVCLK_DIVIDE_REG; m_product = clkfbout_div; mf_product = CLKFBOUT_MULT_F_RND * 8; m_product2 = clkfbout_div / 2; clkout_en_val = m_product; clkout_en_time = md_product + pll_lock_time; locked_en_time = md_product + clkout_en_time + 2; lock_cnt_max = locked_en_time + 16; end REF_CLK_JITTER_MAX_tmp = REF_CLK_JITTER_MAX; ht_calc(clkfbout_frac, clkfbout_frac_en, clkfbout_e, clkfbout_ht, clkfbout_lt, clkfbout_f_div, clkfbout_rsel, clkfbout_fsel, clkfbout_fht, clkfbout_flt, clkfbout_cnt_max, clkfbout_cnt_ht, clkfbout_div); ht_calc(clk0_frac, clk0_frac_en, clk0_e, clk0_ht, clk0_lt, clk0_f_div, clk0_rsel, clk0_fsel, clk0_fht, clk0_flt, clk0_cnt_max, clk0_cnt_ht, clk0_div); divclk_div = DIVCLK_DIVIDE_REG; dr_sram[6] = {clk5_pm[2:0], clk5_en, clk5_ht[5:0], clk5_lt[5:0]}; dr_sram[7] = {2'bx, clk0_pm_f[2:0], clk0_wf_f, 2'b0, clk5_e, clk5_nc, clk5_dt[5:0]}; dr_sram[8] = {clk0_pm_r[2:0], clk0_en, clk0_ht[5:0], clk0_lt[5:0]}; dr_sram[9] = {1'bx, clk0_frac[2:0], clk0_frac_en, clk0_wf_r, 2'b0, clk0_e, clk0_nc, clk0_dt[5:0]}; dr_sram[10] = {clk1_pm[2:0], clk1_en, clk1_ht[5:0], clk1_lt[5:0]}; dr_sram[11] = {6'bx, 2'b0, clk1_e, clk1_nc, clk1_dt[5:0]}; dr_sram[12] = {clk2_pm[2:0], clk2_en, clk2_ht[5:0], clk2_lt[5:0]}; dr_sram[13] = {6'bx, 2'b0, clk2_e, clk2_nc, clk2_dt[5:0]}; dr_sram[14] = {clk3_pm[2:0], clk3_en, clk3_ht[5:0], clk3_lt[5:0]}; dr_sram[15] = {6'bx, 2'b0, clk3_e, clk3_nc, clk3_dt[5:0]}; dr_sram[16] = {clk4_pm[2:0], clk4_en, clk4_ht[5:0], clk4_lt[5:0]}; dr_sram[17] = {6'bx, 2'b0, clk4_e, clk4_nc, clk4_dt[5:0]}; dr_sram[18] = {clk6_pm[2:0], clk6_en, clk6_ht[5:0], clk6_lt[5:0]}; dr_sram[19] = {2'bx, clkfbout_pm_f[2:0], clkfbout_wf_f, 2'b0, clk6_e, clk6_nc, clk6_dt[5:0]}; dr_sram[20] = {clkfbout_pm_r[2:0], clkfbout_en, clkfbout_ht[5:0], clkfbout_lt[5:0]}; dr_sram[21] = {1'bx, clkfbout_frac[2:0], clkfbout_frac_en, clkfbout_wf_r, 2'b0, clkfbout_e, clkfbout_nc, clkfbout_dt[5:0]}; dr_sram[22] = {2'bx, divclk_e, divclk_nc, divclk_ht[5:0], divclk_lt[5:0]}; dr_sram[23] = {2'bx, clkfbin_e, clkfbin_nc, clkfbin_ht[5:0], clkfbin_lt[5:0]}; dr_sram[24] = {6'bx, drp_lock_cnt}; dr_sram[25] = {1'bx, drp_lock_fb_dly, drp_unlock_cnt}; dr_sram[26] = {1'bx, drp_lock_ref_dly, drp_lock_sat_high}; dr_sram[40] = {1'b1, 2'bx, 2'b11, 2'bx, 2'b11, 2'bx, 2'b11, 2'bx, 1'b1}; dr_sram[78] = {pll_cp[3], 2'bx, pll_cp[2:1], 2'bx, pll_cp[0], 1'b0, 2'bx, pll_cpres, 3'bx}; dr_sram[79] = {pll_res[3], 2'bx, pll_res[2:1], 2'bx, pll_res[0], pll_lfhf[1], 2'bx, pll_lfhf[0], 4'bx}; dr_sram[116] = {5'bx, 6'b0, 5'b00001}; end initial begin clkpll_jitter_unlock = 0; clkinstopped_vco_f = 0; rst_clkfbstopped = 0; rst_clkinstopped = 0; rst_clkfbstopped_lk = 0; rst_clkinstopped_lk = 0; clkfbin_stop_tmp = 0; clkin_stop_tmp = 0; clkvco_lk_en = 0; clkvco_lk_dly_tmp = 0; clkin_osc = 0; clkfbin_osc = 0; clkin_p = 0; clkfbin_p = 0; divclk_div = DIVCLK_DIVIDE_REG; ps_lock = 0; ps_lock_dly = 0; PSDONE_out = 0; psdone_out1 = 0; rst_int = 0; clkinstopped_out1 = 0; clkfbstopped_out1 = 0; clkin_period[0] = 0; clkin_period[1] = 0; clkin_period[2] = 0; clkin_period[3] = 0; clkin_period[4] = 0; clkin_period_tmp_t = 0; period_avg = 100000; period_fb = 100000; clkin_lost_val = 2; clkfbin_lost_val = 2; fb_delay = 0; clkvco_delay = 0; val_tmp = 0; dly_tmp = 0; fb_comp_delay = 0; clkfbout_pm_rl = 0; period_vco = 0; period_vco1 = 0; period_vco2 = 0; period_vco3 = 0; period_vco4 = 0; period_vco5 = 0; period_vco6 = 0; period_vco7 = 0; period_vco_half = 0; period_vco_half1 = 0; period_vco_half_rm = 0; period_vco_half_rm1 = 0; period_vco_half_rm2 = 0; period_vco_rm = 0; period_vco_cmp_cnt = 0; period_vco_cmp_flag = 0; period_ps = 0; period_ps_old = 0; clkfbout_frac_ht = 0; clkfbout_frac_lt = 0; clk0_frac_ht = 0; clk0_frac_lt = 0; clkvco_rm_cnt = 0; fb_delay_found = 1'b0; fb_delay_found_tmp = 1'b0; clkin_edge = 0; delay_edge = 0; fbclk_tmp = 0; clkfbout_tst = 1'b0; clkout_en = 0; clkout_en0 = 0; clkout_en_t = 0; clkout_en0_tmp = 0; clkout_en1 = 0; pll_locked_tmp1 = 0; pll_locked_tmp2 = 0; pll_locked_tm = 0; pll_locked_delay = 0; unlock_recover = 0; clkin_jit = 0; clkin_lock_cnt = 0; lock_period = 0; rst_edge = 0; rst_ht = 0; DRDY_out = 0; drdy_out1 = 0; LOCKED_out = 0; locked_out_tmp = 0; DO_out = 16'b0; drp_lock = 0; drp_lock_lat_cnt = 0; clk0_dly_cnt = 6'b0; clk1_dly_cnt = 6'b0; clk2_dly_cnt = 6'b0; clk3_dly_cnt = 6'b0; clk4_dly_cnt = 6'b0; clk5_dly_cnt = 6'b0; clk6_dly_cnt = 6'b0; clkfbout_dly_cnt = 6'b0; clk0_cnt = 8'b0; clk1_cnt = 8'b0; clk2_cnt = 8'b0; clk3_cnt = 8'b0; clk4_cnt = 8'b0; clk5_cnt = 8'b0; clk6_cnt = 8'b0; clkfbout_cnt = 8'b0; divclk_cnt = 8'b0; CLKOUT0_out = 0; CLKOUT1_out = 0; CLKOUT2_out = 0; CLKOUT3_out = 0; CLKOUT4_out = 0; CLKOUT5_out = 0; CLKOUT6_out = 0; clk1_out = 0; clk2_out = 0; clk3_out = 0; clk4_out = 0; clk5_out = 0; clk6_out = 0; CLKFBOUT_out = 0; divclk_out = 0; divclk_out_tmp = 0; clkin_osc = 0; clkfbin_osc = 0; clkin_p = 0; clkfbin_p = 0; pwron_int = 1; #100000 pwron_int = 0; end assign #2 clkinsel_tmp = CLKINSEL_in; assign glock = (startup_wait_sig) ? locked_out_tmp : 1; assign (weak1, strong0) glbl.PLL_LOCKG = (glock == 0) ? 0 : p_up; initial begin init_chk = 0; #2; init_chk = 1; #1; init_chk = 0; end always @(CLKINSEL_in or posedge init_chk ) begin if (init_chk == 0 && $time > 2 && rst_int === 0 && (clkinsel_tmp === 0 || clkinsel_tmp === 1)) begin $display("Error: [Unisim %s-4] Input clock can only be switched when RST=1. CLKINSEL at time %t changed when RST=0. Instance %m", MODULE_NAME, $time); $finish; end clkin_chk_t1_r = 1000.000 / CLKIN_FREQ_MIN_REG; clkin_chk_t1_i = $rtoi(1000.0 * clkin_chk_t1_r); clkin_chk_t1 = 0.001 * clkin_chk_t1_i; clkin_chk_t2_r = 1000.000 / CLKIN_FREQ_MAX_REG; clkin_chk_t2_i = $rtoi(1000.0 * clkin_chk_t2_r); clkin_chk_t2 = 0.001 * clkin_chk_t2_i; if (CLKINSEL_in === 1 && $time > 1 || CLKINSEL_in !== 0 && init_chk == 1) begin if (CLKIN1_PERIOD_REG > clkin_chk_t1 || CLKIN1_PERIOD_REG < clkin_chk_t2) begin $display ("Error: [Unisim %s-5] The attribute CLKIN1_PERIOD is set to %f ns and out the allowed range %f ns to %f ns set by CLKIN_FREQ_MIN/MAX. Instance %m", MODULE_NAME, CLKIN1_PERIOD_REG, clkin_chk_t2, clkin_chk_t1); $finish; end end else if (CLKINSEL_in ===0 && $time > 1 || init_chk == 1 && clkinsel_tmp === 0 ) begin if (CLKIN2_PERIOD_REG > clkin_chk_t1 || CLKIN2_PERIOD_REG < clkin_chk_t2) begin $display ("Error: [Unisim %s-6] The attribute CLKIN2_PERIOD is set to %f ns and out the allowed range %f ns to %f ns set by CLKIN_FREQ_MIN/MAX. Instance %m", MODULE_NAME, CLKIN2_PERIOD_REG, clkin_chk_t2, clkin_chk_t1); $finish; end end period_clkin = (CLKINSEL_in === 0) ? CLKIN2_PERIOD_REG : CLKIN1_PERIOD_REG; if (period_clkin < MAX_FEEDBACK_DELAY) fb_delay_max = period_clkin * MAX_FEEDBACK_DELAY_SCALE; else fb_delay_max = MAX_FEEDBACK_DELAY * MAX_FEEDBACK_DELAY_SCALE; clkvco_freq_init_chk = (1000.0 * CLKFBOUT_MULT_F_RND) / (period_clkin * DIVCLK_DIVIDE_REG); if (clkvco_freq_init_chk > VCOCLK_FREQ_MAX_REG || clkvco_freq_init_chk < VCOCLK_FREQ_MIN_REG) begin if (clkinsel_tmp === 0 && $time > 1 || clkinsel_tmp === 0 && init_chk === 1) begin $display ("Error: [Unisim %s-7] The calculated VCO frequency=%f Mhz. This exceeds the permitted VCO frequency range of %f Mhz to %f Mhz set by VCOCLK_FREQ_MIN/MAX. The VCO frequency is calculated with formula: VCO frequency = CLKFBOUT_MULT_F / (DIVCLK_DIVIDE * CLKIN2_PERIOD). Please adjust the attributes to the permitted VCO frequency range. Instance %m", MODULE_NAME, clkvco_freq_init_chk, VCOCLK_FREQ_MIN_REG, VCOCLK_FREQ_MAX_REG); $finish; end else if (clkinsel_tmp === 1 && $time > 1 || clkinsel_tmp !== 0 && init_chk === 1) begin $display ("Error: [Unisim %s-8] The calculated VCO frequency=%f Mhz. This exceeds the permitted VCO frequency range of %f Mhz to %f Mhz set by VCOCLK_FREQ_MIN/MAX. The VCO frequency is calculated with formula: VCO frequency = CLKFBOUT_MULT_F / (DIVCLK_DIVIDE * CLKIN1_PERIOD). Please adjust the attributes to the permitted VCO frequency range. Instance %m", MODULE_NAME, clkvco_freq_init_chk, VCOCLK_FREQ_MIN_REG, VCOCLK_FREQ_MAX_REG); $finish; end end end assign init_trig = 1; assign clkpll_r = (CLKINSEL_in) ? CLKIN1_in : CLKIN2_in; assign pwrdwn_in1 = (PWRDWN_in === 1) ? 1 : 0; assign rst_input = (RST_in === 1 | pwrdwn_in1 === 1) ? 1 : 0; always @(posedge clkpll_r or posedge rst_input) if (rst_input) rst_int <= 1; else rst_int <= rst_input ; assign rst_in_o = (rst_int || rst_clkfbstopped || rst_clkinstopped); //simprim_rst_h always @(posedge pwrdwn_in1 or posedge pchk_clr) if (pwrdwn_in1) pwrdwn_in1_h <= 1; else if (pchk_clr) pwrdwn_in1_h <= 0; always @(posedge RST_in or posedge pchk_clr) if (RST_in) rst_input_r_h <= 1; else if (pchk_clr) rst_input_r_h <= 0; always @(rst_input ) if (rst_input==1) begin rst_edge = $time; pchk_clr = 0; end else if (rst_input==0 && rst_edge > 1) begin rst_ht = $time - rst_edge; if (rst_ht < 1500) begin if (rst_input_r_h == 1 && pwrdwn_in1_h == 1) $display("Error: [Unisim %s-11] RST and PWRDWN at time %t must be asserted at least for 1.5 ns. Instance %m ", MODULE_NAME, $time); else if (rst_input_r_h == 1 && pwrdwn_in1_h == 0) $display("Error: [Unisim %s-12] RST at time %t must be asserted at least for 1.5 ns. Instance %m", MODULE_NAME, $time); else if (rst_input_r_h == 0 && pwrdwn_in1_h == 1) $display("Error: [Unisim %s-13] PWRDWN at time %t must be asserted at least for 1.5 ns. Instance %m", MODULE_NAME, $time); end pchk_clr = 1; end //endsimprim_rst_h // // DRP port read and write // assign do_out1 = dr_sram[daddr_lat]; always @(posedge DCLK_in or posedge glblGSR) if (glblGSR == 1) begin drp_lock <= 0; drp_lock_lat_cnt <= 0; drp_updt <= 1'b0; end else begin if (~RST_in && drp_updt) drp_updt <= 1'b0; if (DEN_in == 1) begin valid_daddr = addr_is_valid(DADDR_in); if (drp_lock == 1) begin $display("Error: [Unisim %s-14] DEN is high at time %t. Need wait for DRDY signal before next read/write operation through DRP. Instance %m ", MODULE_NAME, $time); end else begin drp_lock <= 1; drp_lock_lat_cnt <= drp_lock_lat_cnt + 1; daddr_lat <= DADDR_in; end if (~valid_daddr) $display("Warning: [Unisim %s-15] Address DADDR=%b is unsupported at time %t. Instance %m ", MODULE_NAME, DADDR_in, $time); if (DWE_in == 1) begin // write process if (rst_input == 1) begin if (valid_daddr) dr_sram[DADDR_in] <= DI_in; if (valid_daddr || drp_updt) drp_updt <= 1'b1; if (DADDR_in == 7'd6) lower_drp(clk5_pm, clk5_en, clk5_ht, clk5_lt, DI_in); else if (DADDR_in == 7'd7) upper_mix_drp(clk0_pm_f, clk0_wf_f, clk5_mx, clk5_e, clk5_nc, clk5_dt, DI_in); else if (DADDR_in == 7'd8) lower_drp(clk0_pm_r, clk0_en, clk0_ht, clk0_lt, DI_in); else if (DADDR_in == 7'd9) upper_frac_drp(clk0_frac, clk0_frac_en, clk0_wf_r, clk0_mx, clk0_e, clk0_nc, clk0_dt, DI_in); else if (DADDR_in == 7'd10) lower_drp(clk1_pm, clk1_en, clk1_ht, clk1_lt, DI_in); else if (DADDR_in == 7'd11) upper_drp(clk1_mx, clk1_e, clk1_nc, clk1_dt, DI_in); else if (DADDR_in == 7'd12) lower_drp(clk2_pm, clk2_en, clk2_ht, clk2_lt, DI_in); else if (DADDR_in == 7'd13) upper_drp(clk2_mx, clk2_e, clk2_nc, clk2_dt, DI_in); else if (DADDR_in == 7'd14) lower_drp(clk3_pm, clk3_en, clk3_ht, clk3_lt, DI_in); else if (DADDR_in == 7'd15) upper_drp(clk3_mx, clk3_e, clk3_nc, clk3_dt, DI_in); else if (DADDR_in == 7'd16) lower_drp(clk4_pm, clk4_en, clk4_ht, clk4_lt, DI_in); else if (DADDR_in == 7'd17) upper_drp(clk4_mx, clk4_e, clk4_nc, clk4_dt, DI_in); else if (DADDR_in == 7'd18) lower_drp(clk3_pm, clk6_en, clk6_ht, clk6_lt, DI_in); else if (DADDR_in == 7'd19) upper_mix_drp(clkfbout_pm_f, clkfbout_wf_f, clk6_mx, clk6_e, clk6_nc, clk6_dt, DI_in); else if (DADDR_in == 7'd20) lower_drp(clkfbout_pm_r, clkfbout_en, clkfbout_ht, clkfbout_lt, DI_in); else if (DADDR_in == 7'd21) upper_frac_drp(clkfbout_frac, clkfbout_frac_en, clkfbout_wf_r, clkfbout_mx, clkfbout_e, clkfbout_nc, clkfbout_dt, DI_in); else if (DADDR_in == 7'd22) begin divclk_e = DI_in[13]; divclk_nc = DI_in[12]; divclk_ht = DI_in[11:6]; divclk_lt = DI_in[5:0]; end end else begin $display("Error: [Unisim %s-18] RST is low at time %t. RST need to be high when changing paramters through DRP. Instance %m", MODULE_NAME, $time); end end //DWE end //DEN if ( drp_lock == 1) begin if (drp_lock_lat_cnt < drp_lock_lat) begin drp_lock_lat_cnt <= drp_lock_lat_cnt + 1; end else begin drp_lock <= 0; drdy_out1 <= 1; drp_lock_lat_cnt <= 0; end end if (drdy_out1 == 1) drdy_out1 <= 0; end function addr_is_valid; input [6:0] daddr_in; begin addr_is_valid = 1'b1; for (i=0; i<=6; i=i+1) if (daddr_in[i] != 0 && daddr_in[i] != 1) addr_is_valid = 1'b0; if ((addr_is_valid) && ((daddr_in >= 7'd06 && daddr_in <= 7'd22) || (daddr_in >= 7'd24 && daddr_in <= 7'd26) || (daddr_in == 7'd40) || (daddr_in == 7'd78) || (daddr_in == 7'd79) || (daddr_in == 7'd116))) addr_is_valid = 1'b1; else addr_is_valid = 1'b0; end endfunction // end process drp; // // determine clock period // always @(posedge clkpll_r or posedge rst_int or posedge rst_clkinsel_flag) if (rst_int || rst_clkinsel_flag) begin clkin_period[0] <= 1000 * period_clkin; clkin_period[1] <= 1000 * period_clkin; clkin_period[2] <= 1000 * period_clkin; clkin_period[3] <= 1000 * period_clkin; clkin_period[4] <= 1000 * period_clkin; clkin_jit <= 0; clkin_lock_cnt <= 0; pll_locked_tm <= 0; lock_period <= 0; pll_locked_tmp1 <= 0; clkout_en0_tmp <= 0; unlock_recover <= 0; clkin_edge <= 0; end else begin clkin_edge <= $time; if (clkin_edge != 0 && clkinstopped_out1 == 0 && rst_clkinsel_flag == 0) begin clkin_period[4] <= clkin_period[3]; clkin_period[3] <= clkin_period[2]; clkin_period[2] <= clkin_period[1]; clkin_period[1] <= clkin_period[0]; clkin_period[0] <= $time - clkin_edge; end if (pll_unlock == 0 && clkin_edge != 0 && clkinstopped_out1 == 0) clkin_jit <= $time - clkin_edge - clkin_period[0]; else clkin_jit <= 0; if ( (clkin_lock_cnt < lock_cnt_max) && fb_delay_found && pll_unlock1 == 0) clkin_lock_cnt <= clkin_lock_cnt + 1; else if (pll_unlock1 == 1 && pll_locked_tmp1 ==1 ) begin clkin_lock_cnt <= lock_cnt_max - 6; unlock_recover <= 1; end if ( clkin_lock_cnt >= pll_lock_time && pll_unlock1 == 0) pll_locked_tm <= #1 1; if ( clkin_lock_cnt == lock_period_time ) lock_period <= 1; if (clkin_lock_cnt >= clkout_en_time && pll_locked_tm == 1) begin clkout_en0_tmp <= 1; end if (clkin_lock_cnt >= locked_en_time && clkout_en == 1) pll_locked_tmp1 <= 1; if (unlock_recover ==1 && clkin_lock_cnt >= lock_cnt_max) unlock_recover <= 0; end always @(posedge pll_locked_tmp1) if (CLKINSEL_in === 0) begin pchk_tmp1 = CLKIN2_PERIOD_REG * 1100; pchk_tmp2 = CLKIN2_PERIOD_REG * 900; if (period_avg > pchk_tmp1 || period_avg < pchk_tmp2) begin $display("Warning: [Unisim %s-19] Input CLKIN2 period and attribute CLKIN2_PERIOD are not same. Instance %m ", MODULE_NAME); end end else begin pchk_tmp1 = CLKIN1_PERIOD_REG * 1100; pchk_tmp2 = CLKIN1_PERIOD_REG * 900; if (period_avg > pchk_tmp1 || period_avg < pchk_tmp2) begin $display("Warning: [Unisim %s-20] Input CLKIN1 period and attribute CLKIN1_PERIOD are not same. Instance %m ", MODULE_NAME); end end always @(*) if (rst_int == 0) begin if (clkfbout_frac_en == 1'b0) begin clkout_en_val = m_product; clkout_en_time = md_product + pll_lock_time; locked_en_time = md_product + clkout_en_time + 2; lock_cnt_max = locked_en_time + 16; end else begin clkout_en_val = mf_product - 1; clkout_en_time = mf_product + 4 + pll_lock_time; locked_en_time = md_product + clkout_en_time + 2; lock_cnt_max = locked_en_time + 16; end end always @(clkout_en0_tmp) clkout_en0_tmp1 <= #1 clkout_en0_tmp; always @(clkout_en0_tmp1 or clkout_en_t or clkout_en0_tmp ) if (clkout_en0_tmp==0 ) clkout_en0 = 0; else begin if (clkfbout_frac_en == 1'b1) begin if (clkout_en_t > clkout_en_val && clkout_en0_tmp1 == 1) clkout_en0 <= #period_vco6 clkout_en0_tmp1; end else begin if (clkout_en_t == clkout_en_val && clkout_en0_tmp1 == 1) clkout_en0 <= #period_vco6 clkout_en0_tmp1; end end always @(clkout_en0 ) clkout_en1 <= #(clkvco_delay) clkout_en0; always @(clkout_en1 or rst_in_o ) if (rst_in_o) clkout_en = 0; else clkout_en = clkout_en1; always @(pll_locked_tmp1 ) if (pll_locked_tmp1==0) pll_locked_tmp2 = pll_locked_tmp1; else begin pll_locked_tmp2 <= #pll_locked_delay pll_locked_tmp1; end always @(rst_int) if (rst_int) begin assign pll_locked_tmp2 = 0; assign clkout_en0 = 0; assign clkout_en1 = 0; end else begin deassign pll_locked_tmp2; deassign clkout_en0; deassign clkout_en1; end assign locked_out1 = (pll_locked_tm && pll_locked_tmp2 && ~pll_unlock && !unlock_recover) ? 1 : 0; always @(rst_int or locked_out1) if (rst_int == 1) locked_out_tmp <= #1000 0; else locked_out_tmp <= locked_out1; always @(clkin_period[0] or clkin_period[1] or clkin_period[2] or clkin_period[3] or clkin_period[4]) begin if (clkin_period[0] > clkin_period[1]) clkin_period_tmp_t = clkin_period[0] - clkin_period[1]; else clkin_period_tmp_t = clkin_period[1] - clkin_period[0]; if ( ((clkin_period[0] > 0) && (clkin_period[0] != period_avg)) && (clkin_period[0] < 1.5 * period_avg || clkin_period_tmp_t <= 300) ) period_avg = (clkin_period[0] + clkin_period[1] + clkin_period[2] + clkin_period[3] + clkin_period[4])/5; end always @(clkinstopped_out_dly or rst_int) if (rst_int) clkinstopped_hold = 0; else begin if (clkinstopped_out1) clkinstopped_hold <= #1 1; else begin if (clkin_hold_f) clkinstopped_hold = 0; end end always @(posedge clkinstopped_out1) begin period_avg_stpi <= period_avg; pd_stp_p <= #1 1; @(negedge clkvco) pd_stp_p <= #1 0; end always @(negedge clkvco or posedge rst_int or posedge pd_stp_p) if (rst_int) begin period_avg_stp <= 1000; vco_stp_f <= 0; end else if (pd_stp_p) period_avg_stp <= period_avg_stpi; else begin if (clkinstopped_out_dly2 == 1 && clkin_hold_f == 0) begin if (period_vco > 1739) vco_stp_f <= 1; else begin period_avg_stp <= period_avg_stp + 1; end end end always @(period_avg or divclk_div or clkfbout_f_div or clkinstopped_hold or period_avg_stp or posedge rst_clkinstopped_rc) if (period_avg > 0 ) begin md_product = divclk_div * clkfbout_f_div; m_product = clkfbout_f_div; m_product2 = clkfbout_f_div / 2; clkvco_div_fint = $rtoi(clkfbout_f_div/divclk_div); clkvco_div_frac = (clkfbout_f_div/divclk_div) - clkvco_div_fint; if (clkvco_div_frac > 0.000) clkvco_frac_en = 1; else clkvco_frac_en = 0; period_fb = period_avg * divclk_div; period_vco_tmp = period_fb / clkfbout_f_div; period_vco_rl = 1.0 * period_fb / clkfbout_f_div; period_vco_rl_half = period_vco_rl / 2.0; clkvco_pdrm = (period_avg * divclk_div / clkfbout_f_div) - period_vco_tmp; period_vco_mf = period_avg * 8; if (clkinstopped_hold == 1) begin if (clkin_hold_f) begin period_vco = (20000 * period_vco_tmp) / (20000 - period_vco_tmp); period_vco_rl = (20000 * period_vco_tmp) / (20000 - period_vco_tmp); period_vco_rl_half = period_vco_rl / 2.0; end else begin period_vco = period_avg_stp * divclk_div /clkfbout_f_div; period_vco_rl = period_avg_stp * divclk_div /clkfbout_f_div; period_vco_rl_half = period_vco_rl / 2.0; end end else period_vco = period_vco_tmp; period_vco_rm = period_fb % clkfbout_div; if (period_vco_rm > 1) begin if (period_vco_rm > m_product2) begin period_vco_cmp_cnt = m_product / (m_product - period_vco_rm) - 1; period_vco_cmp_flag = 2; end else begin period_vco_cmp_cnt = (m_product / period_vco_rm) - 1; period_vco_cmp_flag = 1; end end else begin period_vco_cmp_cnt = 0; period_vco_cmp_flag = 0; end period_vco_half = period_vco /2; period_vco_half_rm = period_vco - period_vco_half; period_vco_half_rm1 = period_vco_half_rm + 1; if (period_vco_half_rm < 1) period_vco_half_rm2 = 0; else period_vco_half_rm2 = period_vco_half_rm - 1; period_vco_half1 = period_vco - period_vco_half + 1; pll_locked_delay = period_fb * clkfbout_f_div; clkin_dly_t = period_avg * (divclk_div + 1.25); clkfbin_dly_t = period_fb * 2.25 ; period_vco1 = period_vco / 8; period_vco2 = period_vco / 4; period_vco3 = period_vco * 3/ 8; period_vco4 = period_vco / 2; period_vco5 = period_vco * 5 / 8; period_vco6 = period_vco *3 / 4; period_vco7 = period_vco * 7 / 8; end always @ (negedge RST_in) begin if (drp_updt) begin mc_to_attr(clkfbout_pm_f, clkfbout_wf_f, clkfbout_frac, clkfbout_frac_en, clkfbout_wf_r, clkfbout_mx, clkfbout_e, clkfbout_nc, clkfbout_dt, clkfbout_pm_r, clkfbout_en, clkfbout_ht, clkfbout_lt, clkfbout_f_div, clkfbout_phase, clkfbout_duty); if (((clkfbout_f_div > M_MAX) || (clkfbout_f_div < M_MIN)) && ~clkfbout_nc) $display(" Input Error : %s CLKFBOUT_MULT_F has been programmed through DRP to %f which is over the range of %f to %f. Instance %m at time %t.", MODULE_NAME, clkfbout_f_div, M_MIN, M_MAX, $time); mc_to_attr(clk0_pm_f, clk0_wf_f, clk0_frac, clk0_frac_en, clk0_wf_r, clk0_mx, clk0_e, clk0_nc, clk0_dt, clk0_pm_r, clk0_en, clk0_ht, clk0_lt, clk0_f_div, clk0_phase, clk0_duty); if (((clk0_f_div > O_MAX) || (clk0_f_div < O_MIN)) && ~clk0_nc) $display(" Input Error : %s CLKOUT0_DIVIDE_F has been programmed through DRP to %f which is over the range of %d to %d. Instance %m at time %t.", MODULE_NAME, clk0_f_div, O_MIN, O_MAX, $time); mc_to_attr(3'b0, 1'b0, 3'b0, 1'b0, 1'b0, clk1_mx, clk1_e, clk1_nc, clk1_dt, clk1_pm, clk1_en, clk1_ht, clk1_lt, clk1_div, clk1_phase, clk1_duty); mc_to_attr(3'b0, 1'b0, 3'b0, 1'b0, 1'b0, clk2_mx, clk2_e, clk2_nc, clk2_dt, clk2_pm, clk2_en, clk2_ht, clk2_lt, clk2_div, clk2_phase, clk2_duty); mc_to_attr(3'b0, 1'b0, 3'b0, 1'b0, 1'b0, clk3_mx, clk3_e, clk3_nc, clk3_dt, clk3_pm, clk3_en, clk3_ht, clk3_lt, clk3_div, clk3_phase, clk3_duty); mc_to_attr(3'b0, 1'b0, 3'b0, 1'b0, 1'b0, clk4_mx, clk4_e, clk4_nc, clk4_dt, clk4_pm, clk4_en, clk4_ht, clk4_lt, clk4_div, clk4_phase, clk4_duty); mc_to_attr(3'b0, 1'b0, 3'b0, 1'b0, 1'b0, clk5_mx, clk5_e, clk5_nc, clk5_dt, clk5_pm, clk5_en, clk5_ht, clk5_lt, clk5_div, clk5_phase, clk5_duty); mc_to_attr(3'b0, 1'b0, 3'b0, 1'b0, 1'b0, clk6_mx, clk6_e, clk6_nc, clk6_dt, clk6_pm, clk6_en, clk6_ht, clk6_lt, clk6_div, clk6_phase, clk6_duty); mc_to_attr(3'b0, 1'b0, 3'b0, 1'b0, 1'b0, 2'b0, divclk_e, divclk_nc, 6'b0, 3'b0, divclk_en, divclk_ht, divclk_lt, divclk_div, divclk_phase, divclk_duty); if (((divclk_div > D_MAX) || (divclk_div < D_MIN)) && ~divclk_nc) $display(" Error : [Unisim %s-34] DIVCLK_DIVIDE has been programmed through DRP to %f which is over the range of %d to %d at time %t. Instance %m", MODULE_NAME, divclk_div, D_MIN, D_MAX, $time); ht_calc(clkfbout_frac, clkfbout_frac_en, clkfbout_e, clkfbout_ht, clkfbout_lt, clkfbout_f_div, clkfbout_rsel, clkfbout_fsel, clkfbout_fht, clkfbout_flt, clkfbout_cnt_max, clkfbout_cnt_ht, clkfbout_div); ht_calc(clk0_frac, clk0_frac_en, clk0_e, clk0_ht, clk0_lt, clk0_f_div, clk0_rsel, clk0_fsel, clk0_fht, clk0_flt, clk0_cnt_max, clk0_cnt_ht, clk0_div); ht_calc(3'b0, 1'b0, clk1_e, clk1_ht, clk1_lt, clk1_div, d_rsel, d_fsel, d_fht, d_flt, clk1_cnt_max, clk1_cnt_ht, d_div); ht_calc(3'b0, 1'b0, clk2_e, clk2_ht, clk2_lt, clk2_div, d_rsel, d_fsel, d_fht, d_flt, clk2_cnt_max, clk2_cnt_ht, d_div); ht_calc(3'b0, 1'b0, clk3_e, clk3_ht, clk3_lt, clk3_div, d_rsel, d_fsel, d_fht, d_flt, clk3_cnt_max, clk3_cnt_ht, d_div); ht_calc(3'b0, 1'b0, clk4_e, clk4_ht, clk4_lt, clk4_div, d_rsel, d_fsel, d_fht, d_flt, clk4_cnt_max, clk4_cnt_ht, d_div); ht_calc(3'b0, 1'b0, clk5_e, clk5_ht, clk5_lt, clk5_div, d_rsel, d_fsel, d_fht, d_flt, clk5_cnt_max, clk5_cnt_ht, d_div); ht_calc(3'b0, 1'b0, clk6_e, clk6_ht, clk6_lt, clk6_div, d_rsel, d_fsel, d_fht, d_flt, clk6_cnt_max, clk6_cnt_ht, d_div); ht_calc(3'b0, 1'b0, divclk_e, divclk_ht, divclk_lt, divclk_div, d_rsel, d_fsel, d_fht, d_flt, divclk_cnt_max, divclk_cnt_ht, d_div); end end always @(clkfbout_f_div) begin mf_product = clkfbout_f_div * 8; end always @(*) begin if (clkfbout_frac_en) begin clkfbout_frac_ht = period_vco_rl * clkfbout_fht + (period_vco_rl * clkfbout_fsel) / 8; clkfbout_frac_lt = period_vco_rl * clkfbout_flt + (period_vco_rl * clkfbout_rsel) / 8; end end always @(*) begin if (clk0_frac_en) begin clk0_frac_ht = period_vco_rl * clk0_fht + (period_vco_rl * clk0_fsel) / 8; clk0_frac_lt = period_vco_rl * clk0_flt + (period_vco_rl * clk0_rsel) / 8; end end reg ps_wr_to_max = 1'b0; always @(period_vco or ps_in_ps) if (fps_en == 1) begin if (ps_in_ps < 0) period_ps = period_vco + ps_in_ps * period_vco / 56.0; else if ((ps_in_ps == 0) && PSINCDEC_in == 0) period_ps = 0; else period_ps = ps_in_ps * period_vco / 56.0; end always @( clkpll_r ) clkpll_tmp1 <= #(period_avg) clkpll_r; always @(clkpll_tmp1) clkpll <= #(period_avg) clkpll_tmp1; always @(posedge clkinstopped_out1 or posedge rst_int) if ( rst_int) clkinstopped_vco_f <= 0; else begin clkinstopped_vco_f <= 1; @(negedge clkinstopped_out1 or posedge rst_int ) if (rst_int) clkinstopped_vco_f <= 0; else begin @(posedge clkpll); @(posedge clkpll) clkinstopped_vco_f <= 0; end end always @(posedge clkinstopped_out1 or posedge rst_int) if (rst_int) CLKINSTOPPED_out <= 0; else begin CLKINSTOPPED_out <= 1; if (clkin_hold_f == 1) begin @(posedge locked_out1 or posedge rst_int) CLKINSTOPPED_out <= 0; end else begin if (CLKINSEL_in == 1) $display("Warning: [Unisim %s-21] Input CLKIN1 is stopped. Reset is required when input clock returns. Instance %m ", MODULE_NAME); else $display("Warning: [Unisim %s-22] Input CLKIN2 is stopped. Reset is required when input clock returns. Instance %m ", MODULE_NAME); end end always @(posedge clkfbstopped_out1 or posedge rst_int) if (rst_int) CLKFBSTOPPED_out <= 0; else begin CLKFBSTOPPED_out <= 1; @(posedge locked_out1) CLKFBSTOPPED_out <= 0; end always @(clkout_en_t) if (clkout_en_t >= clkout_en_val -3 && clkout_en_t < clkout_en_val) rst_clkinstopped_tm = 1; else rst_clkinstopped_tm = 0; always @(negedge clkinstopped_out1 or posedge rst_int) if (rst_int) rst_clkinstopped <= 0; else if (rst_clkinstopped_lk == 0 && clkin_hold_f == 1) begin @(posedge rst_clkinstopped_tm) rst_clkinstopped <= #period_vco4 1; @(negedge rst_clkinstopped_tm ) begin rst_clkinstopped <= #period_vco5 0; rst_clkinstopped_rc <= #period_vco6 1; rst_clkinstopped_rc <= #period_vco7 0; end end always @(posedge clkinstopped_out1 or posedge rst_int) if (rst_int) clkinstopped_out_dly <= 0; else begin clkinstopped_out_dly <= 1; if (clkin_hold_f == 1) begin @(negedge rst_clkinstopped_rc or posedge rst_int) clkinstopped_out_dly <= 0; end end always @(clkinstopped_out1 or posedge rst_int) if (rst_int) clkinstopped_out_dly2 <= 0; else clkinstopped_out_dly2 <= #2 clkinstopped_out1; always @(negedge rst_clkinstopped or posedge rst_int) if (rst_int) rst_clkinstopped_lk <= 0; else begin rst_clkinstopped_lk <= 1; @(posedge locked_out1) rst_clkinstopped_lk <= 0; end always @(clkinstopped_vco_f or CLKINSTOPPED_out or clkvco_lk or clkvco_free or rst_int) if (rst_int) clkvco_lk = 0; else begin if (CLKINSTOPPED_out == 1 && clkin_stop_f == 0) clkvco_lk <= #(period_vco_half) !clkvco_lk; else if (clkinstopped_vco_f == 1 && period_vco_half > 0) clkvco_lk <= #(period_vco_half) !clkvco_lk; else clkvco_lk = clkvco_free; end // free run vco comp always @(posedge clkpll) if (pll_locked_tm == 1 ) begin clkvco_free = 1'b1; halfperiod_sum = 0.0; halfperiod = 0; if (clkfbout_frac_en == 1'b1 || clkvco_frac_en == 1) begin for (ik10=1; ik10 < mf_product; ik10=ik10+1) begin clkout_en_t <= ik10; halfperiod_sum = halfperiod_sum + period_vco_rl_half - halfperiod; halfperiod = $rtoi(halfperiod_sum); #halfperiod clkvco_free = 1'b0; halfperiod_sum = halfperiod_sum + period_vco_rl_half - halfperiod; halfperiod = $rtoi(halfperiod_sum); #halfperiod clkvco_free = 1'b1; end clkout_en_t <= ik10; end else begin for (ik11=1; ik11 < m_product; ik11=ik11+1) begin clkout_en_t <= ik11; halfperiod_sum = halfperiod_sum + period_vco_rl_half - halfperiod; halfperiod = $rtoi(halfperiod_sum); #halfperiod clkvco_free = 1'b0; halfperiod_sum = halfperiod_sum + period_vco_rl_half - halfperiod; halfperiod = $rtoi(halfperiod_sum); #halfperiod clkvco_free = 1'b1; end clkout_en_t <= ik11; end halfperiod_sum = halfperiod_sum + period_vco_rl_half - halfperiod; halfperiod = $rtoi(halfperiod_sum); #halfperiod clkvco_free = 1'b0; end always @(fb_delay or period_vco or period_vco_mf or clkfbout_dt or clkfbout_pm_rl or lock_period or ps_in_ps ) if (lock_period == 1) begin if (clkfbout_frac_en == 1'b1) begin val_tmp = period_avg * DIVCLK_DIVIDE_REG; fb_comp_delay = period_vco * (clkfbout_dt + clkfbout_pm_rl); end else begin val_tmp = period_avg * DIVCLK_DIVIDE_REG; fb_comp_delay = period_vco * (clkfbout_dt + clkfbout_pm_rl); end dly_tmp1 = fb_delay + fb_comp_delay; dly_tmp_int = 1; if (clkfbout_fps_en == 1) begin if (ps_in_ps < 0) begin tmp_ps_val1 = -1 * ps_in_ps; tmp_ps_val2 = tmp_ps_val1 * period_vco / 56.0; if (tmp_ps_val2 > dly_tmp1 ) begin dly_tmp_int = -1; dly_tmp = tmp_ps_val2 - dly_tmp1; end else if (tmp_ps_val2 == dly_tmp1 ) begin dly_tmp_int = 0; dly_tmp = 0; end else begin dly_tmp_int = 1; dly_tmp = dly_tmp1 - tmp_ps_val2; end end else dly_tmp = dly_tmp1 + ps_in_ps * period_vco / 56.0; end else dly_tmp = dly_tmp1; if (dly_tmp_int < 0) clkvco_delay = dly_tmp; else begin if (clkfbout_frac_en == 1'b1 && dly_tmp == 0) clkvco_delay = 0; else if ( dly_tmp < val_tmp) clkvco_delay = val_tmp - dly_tmp; else clkvco_delay = val_tmp - dly_tmp % val_tmp ; end end always @(clkfbout_pm_r) case (clkfbout_pm_r) 3'b000 : clkfbout_pm_rl = 0.0; 3'b001 : clkfbout_pm_rl = 0.125; 3'b010 : clkfbout_pm_rl = 0.25; 3'b011 : clkfbout_pm_rl = 0.375; 3'b100 : clkfbout_pm_rl = 0.50; 3'b101 : clkfbout_pm_rl = 0.625; 3'b110 : clkfbout_pm_rl = 0.75; 3'b111 : clkfbout_pm_rl = 0.875; endcase always @(clkvco_lk) clkvco_lk_dly_tmp <= #clkvco_delay clkvco_lk; always @(clkvco_lk_dly_tmp or clkvco_lk or pll_locked_tm) if ( pll_locked_tm && vco_stp_f == 0) begin if (dly_tmp == 0) clkvco = clkvco_lk; else clkvco = clkvco_lk_dly_tmp; end else clkvco = 0; always @(posedge PSCLK_in or posedge rst_int) if (rst_int) begin ps_in_ps <= ps_in_init; ps_cnt <= 0; psen_w <= 0; fps_clk_en <= 0; end else if (fps_en == 1) begin fps_clk_en <= 1; if (PSEN_in) begin if (psen_w == 1) $display("Error: [Unisim %s-23] PSEN is active more than 1 PSCLK period at time %t. PSEN must be active for only one PSCLK period. Instance %m ", MODULE_NAME, $time); psen_w <= 1; if (ps_lock == 1) $display("Warning: [Unisim %s-24] Please wait for PSDONE signal at time %t before adjusting the Phase Shift. Instance %m ", MODULE_NAME, $time); else if (PSINCDEC_in == 1) begin if (ps_cnt < ps_max) ps_cnt <= ps_cnt + 1; else ps_cnt <= 0; if (ps_in_ps < ps_max) ps_in_ps <= ps_in_ps + 1; else ps_in_ps <= 0; ps_lock <= 1; end else if (PSINCDEC_in == 0) begin ps_cnt_neg = (-1) * ps_cnt; ps_in_ps_neg = (-1) * ps_in_ps; if (ps_cnt_neg < ps_max) ps_cnt <= ps_cnt - 1; else ps_cnt <= 0; if (ps_in_ps_neg < ps_max) ps_in_ps <= ps_in_ps - 1; else ps_in_ps <= 0; ps_lock <= 1; end end else psen_w <= 0; if ( psdone_out1 == 1) ps_lock <= 0; end always @(posedge ps_lock ) if (fps_en == 1) begin @(posedge PSCLK_in) @(posedge PSCLK_in) @(posedge PSCLK_in) @(posedge PSCLK_in) @(posedge PSCLK_in) @(posedge PSCLK_in) @(posedge PSCLK_in) @(posedge PSCLK_in) @(posedge PSCLK_in) @(posedge PSCLK_in) @(posedge PSCLK_in) begin psdone_out1 = 1; @(posedge PSCLK_in); psdone_out1 = 0; end end always @(rst_clkinstopped) if (rst_clkinstopped) begin assign clkfbout_frac_ht = 50; assign clkfbout_frac_lt = 50; end else begin deassign clkfbout_frac_ht; deassign clkfbout_frac_lt; end integer clk0_delay=0, clk1_delay=0, clk2_delay=0, clk3_delay=0, clk4_delay=0, clk5_delay=0, clk6_delay=0, clkfbout_delay=0; integer clk0_delay_next, clk1_delay_next, clk2_delay_next, clk3_delay_next, clk4_delay_next, clk5_delay_next, clk6_delay_next, clkfbout_delay_next; always @(*) clk0_delay_next = clk0_pm_r*period_vco/8 + (clk0_fps_en*period_ps); always @(*) clk1_delay_next = clk1_pm*period_vco/8 + (clk1_fps_en*period_ps); always @(*) clk2_delay_next = clk2_pm*period_vco/8 + (clk2_fps_en*period_ps); always @(*) clk3_delay_next = clk3_pm*period_vco/8 + (clk3_fps_en*period_ps); always @(*) clk4_delay_next = clk4_pm*period_vco/8 + (clk4_fps_en*period_ps); always @(*) clk5_delay_next = clk5_pm*period_vco/8 + (clk5_fps_en*period_ps); always @(*) clk6_delay_next = clk6_pm*period_vco/8 + (clk6_fps_en*period_ps); always @(*) clkfbout_delay_next = clkfbout_pm_r*period_vco/8 + (clkfbout_fps_en*period_ps); always @ (posedge clkvco) begin if (ps_lock) begin if ((period_ps - period_ps_old) > period_vco/2) ps_wr_to_max = 1'b1; else ps_wr_to_max <= 1'b0; end period_ps_old = period_ps; clk0_delay <= clk0_delay_next; clk1_delay <= clk1_delay_next; clk2_delay <= clk2_delay_next; clk3_delay <= clk3_delay_next; clk4_delay <= clk4_delay_next; clk5_delay <= clk5_delay_next; clk6_delay <= clk6_delay_next; clkfbout_delay <= clkfbout_delay_next; end always @ (clkvco) begin if (clkout_en && clk0_en) if (clk0_delay == 0) clk0in <= clkvco; else if (clk0_fps_en && ps_wr_to_max && ~clkvco) begin clk0in <= #(clk0_delay - period_ps) 1'b0; clk0in <= #((2 * clk0_delay - period_ps)/2) 1'b1; clk0in <= #(clk0_delay) 1'b0; end else begin clk0in <= #clk0_delay clkvco; end else clk0in <= 1'b0; end always @ (clkvco) begin if (clkout_en && clk1_en) if (clk1_delay == 0) clk1in <= clkvco; else if (clk1_fps_en && ps_wr_to_max && ~clkvco) begin clk1in <= #(clk1_delay - period_ps) 1'b0; clk1in <= #((2 * clk1_delay - period_ps)/2) 1'b1; clk1in <= #(clk1_delay) 1'b0; end else begin clk1in <= #clk1_delay clkvco; end else clk1in <= 1'b0; end always @ (clkvco) begin if (clkout_en && clk2_en) if (clk2_delay == 0) clk2in <= clkvco; else if (clk2_fps_en && ps_wr_to_max && ~clkvco) begin clk2in <= #(clk2_delay - period_ps) 1'b0; clk2in <= #((2 * clk2_delay - period_ps)/2) 1'b1; clk2in <= #(clk2_delay) 1'b0; end else begin clk2in <= #clk2_delay clkvco; end else clk2in <= 1'b0; end always @ (clkvco) begin if (clkout_en && clk3_en) if (clk3_delay == 0) clk3in <= clkvco; else if (clk3_fps_en && ps_wr_to_max && ~clkvco) begin clk3in <= #(clk3_delay - period_ps) 1'b0; clk3in <= #((2 * clk3_delay - period_ps)/2) 1'b1; clk3in <= #(clk3_delay) 1'b0; end else begin clk3in <= #clk3_delay clkvco; end else clk3in <= 1'b0; end always @ (clkvco) begin if (clkout_en && clk4_en) if (clkout4_cascade_int) clk4in <= clk6_out; else if (clk4_delay == 0) clk4in <= clkvco; else if (clk4_fps_en && ps_wr_to_max && ~clkvco) begin clk4in <= #(clk4_delay - period_ps) 1'b0; clk4in <= #((2 * clk4_delay - period_ps)/2) 1'b1; clk4in <= #(clk4_delay) 1'b0; end else begin clk4in <= #clk4_delay clkvco; end else clk4in <= 1'b0; end always @ (clkvco) begin if (clkout_en && clk5_en) if (clk5_delay == 0) clk5in <= clkvco; else if (clk5_fps_en && ps_wr_to_max && ~clkvco) begin clk5in <= #(clk5_delay - period_ps) 1'b0; clk5in <= #((2 * clk5_delay - period_ps)/2) 1'b1; clk5in <= #(clk5_delay) 1'b0; end else begin clk5in <= #clk5_delay clkvco; end else clk5in <= 1'b0; end always @ (clkvco) begin if (clkout_en && clk6_en) if (clk6_delay == 0) clk6in <= clkvco; else if (clk6_fps_en && ps_wr_to_max && ~clkvco) begin clk6in <= #(clk6_delay - period_ps) 1'b0; clk6in <= #((2 * clk6_delay - period_ps)/2) 1'b1; clk6in <= #(clk6_delay) 1'b0; end else begin clk6in <= #clk6_delay clkvco; end else clk6in <= 1'b0; end always @ (clkvco) begin if (clkout_en && clkfbout_en) if (clkfbout_delay == 0) clkfboutin <= clkvco; else if (clkfbout_fps_en && ps_wr_to_max && ~clkvco) begin clkfboutin <= #(clkfbout_delay - period_ps) 1'b0; clkfboutin <= #((2 * clkfbout_delay - period_ps)/2) 1'b1; clkfboutin <= #(clkfbout_delay) 1'b0; end else begin clkfboutin <= #clkfbout_delay clkvco; end else clkfboutin <= 1'b0; end assign clk0ps_en = (clk0_dly_cnt == clk0_dt) & clkout_en; assign clk1ps_en = (clk1_dly_cnt == clk1_dt) & clkout_en; assign clk2ps_en = (clk2_dly_cnt == clk2_dt) & clkout_en; assign clk3ps_en = (clk3_dly_cnt == clk3_dt) & clkout_en; assign clk4ps_en = (clk4_dly_cnt == clk4_dt) & clkout_en; assign clk5ps_en = (clk5_dly_cnt == clk5_dt) & clkout_en; assign clk6ps_en = (clk6_dly_cnt == clk6_dt) & clkout_en; assign clkfbps_en = (clkfbout_dly_cnt == clkfbout_dt) & clkout_en; always @(negedge clk0in or posedge rst_in_o) if (rst_in_o) clk0_dly_cnt <= 6'b0; else if (clkout_en == 1 ) begin if (clk0_dly_cnt < clk0_dt) clk0_dly_cnt <= clk0_dly_cnt + 1; end always @(negedge clk1in or posedge rst_in_o) if (rst_in_o) clk1_dly_cnt <= 6'b0; else if (clk1_dly_cnt < clk1_dt && clkout_en ==1) clk1_dly_cnt <= clk1_dly_cnt + 1; always @(negedge clk2in or posedge rst_in_o) if (rst_in_o) clk2_dly_cnt <= 6'b0; else if (clk2_dly_cnt < clk2_dt && clkout_en ==1) clk2_dly_cnt <= clk2_dly_cnt + 1; always @(negedge clk3in or posedge rst_in_o) if (rst_in_o) clk3_dly_cnt <= 6'b0; else if (clk3_dly_cnt < clk3_dt && clkout_en ==1) clk3_dly_cnt <= clk3_dly_cnt + 1; always @(negedge clk4in or posedge rst_in_o) if (rst_in_o) clk4_dly_cnt <= 6'b0; else if (clk4_dly_cnt < clk4_dt && clkout_en ==1) clk4_dly_cnt <= clk4_dly_cnt + 1; always @(negedge clk5in or posedge rst_in_o) if (rst_in_o) clk5_dly_cnt <= 6'b0; else if (clkout_en == 1 ) begin if (clk5_dly_cnt < clk5_dt) clk5_dly_cnt <= clk5_dly_cnt + 1; end always @(negedge clk6in or posedge rst_in_o) if (rst_in_o) clk6_dly_cnt <= 6'b0; else if (clkout_en == 1 ) begin if (clk6_dly_cnt < clk6_dt) clk6_dly_cnt <= clk6_dly_cnt + 1; end always @(negedge clkfboutin or posedge rst_in_o) if (rst_in_o) clkfbout_dly_cnt <= 6'b0; else if (clkout_en == 1 ) begin if (clkfbout_dly_cnt < clkfbout_dt) clkfbout_dly_cnt <= clkfbout_dly_cnt + 1; end always @(posedge clkfboutin or negedge clkfboutin or posedge rst_in_o) if (rst_in_o || ~clkfbps_en) begin clkfbout_cnt <= 8'b0; clkfbout_out <= 0; end else if (clkfbout_nc) clkfbout_out <= ~clkfbout_out; else if (~clkfbout_frac_en) begin if (clkfbout_cnt < clkfbout_cnt_max) clkfbout_cnt <= clkfbout_cnt + 1; else clkfbout_cnt <= 8'b0; if (clkfbout_cnt < clkfbout_cnt_ht) clkfbout_out <= 1; else clkfbout_out <= 0; end else if (clkfbout_frac_en && clkfboutin) begin clkfbout_out <= 1; for (ib=1; ib < 8; ib=ib+1) begin #(clkfbout_frac_ht) clkfbout_out <= 0; #(clkfbout_frac_lt) clkfbout_out <= 1; end #(clkfbout_frac_ht) clkfbout_out <= 0; #(clkfbout_frac_lt - period_vco1); end always @(posedge clk0in or negedge clk0in or posedge rst_in_o) if (rst_in_o || ~clk0ps_en) begin clk0_cnt <= 8'b0; clk0_out <= 0; end else if (clk0_nc) clk0_out <= ~clk0_out; else if (~clk0_frac_en) begin if (clk0_cnt < clk0_cnt_max) clk0_cnt <= clk0_cnt + 1; else clk0_cnt <= 8'b0; if (clk0_cnt < clk0_cnt_ht) clk0_out <= 1; else clk0_out <= 0; end else if (clk0_frac_en && clk0in) begin clk0_out <= 1; for (ik0=1; ik0 < 8; ik0=ik0+1) begin #(clk0_frac_ht) clk0_out <= 0; #(clk0_frac_lt) clk0_out <= 1; end #(clk0_frac_ht) clk0_out <= 0; #(clk0_frac_lt - period_vco1); end always @(posedge clk1in or negedge clk1in or posedge rst_in_o) if (rst_in_o || ~clk1ps_en) begin clk1_cnt <= 8'b0; clk1_out <= 0; end else if (clk1_nc) clk1_out <= ~clk1_out; else begin if (clk1_cnt < clk1_cnt_max) clk1_cnt <= clk1_cnt + 1; else clk1_cnt <= 8'b0; if (clk1_cnt < clk1_cnt_ht) clk1_out <= 1; else clk1_out <= 0; end always @(posedge clk2in or negedge clk2in or posedge rst_in_o) if (rst_in_o || ~clk2ps_en) begin clk2_cnt <= 8'b0; clk2_out <= 0; end else if (clk2_nc) clk2_out <= ~clk2_out; else begin if (clk2_cnt < clk2_cnt_max) clk2_cnt <= clk2_cnt + 1; else clk2_cnt <= 8'b0; if (clk2_cnt < clk2_cnt_ht) clk2_out <= 1; else clk2_out <= 0; end always @(posedge clk3in or negedge clk3in or posedge rst_in_o) if (rst_in_o || ~clk3ps_en) begin clk3_cnt <= 8'b0; clk3_out <= 0; end else if (clk3_nc) clk3_out <= ~clk3_out; else begin if (clk3_cnt < clk3_cnt_max) clk3_cnt <= clk3_cnt + 1; else clk3_cnt <= 8'b0; if (clk3_cnt < clk3_cnt_ht) clk3_out <= 1; else clk3_out <= 0; end always @(posedge clk4in or negedge clk4in or posedge rst_in_o) if (rst_in_o || ~clk4ps_en) begin clk4_cnt <= 8'b0; clk4_out <= 0; end else if (clk4_nc) clk4_out <= ~clk4_out; else begin if (clk4_cnt < clk4_cnt_max) clk4_cnt <= clk4_cnt + 1; else clk4_cnt <= 8'b0; if (clk4_cnt < clk4_cnt_ht) clk4_out <= 1; else clk4_out <= 0; end always @(posedge clk5in or negedge clk5in or posedge rst_in_o) if (rst_in_o || ~clk5ps_en) begin clk5_cnt <= 8'b0; clk5_out <= 0; end else if (clk5_nc) clk5_out <= ~clk5_out; else begin if (clk5_cnt < clk5_cnt_max) clk5_cnt <= clk5_cnt + 1; else clk5_cnt <= 8'b0; if (clk5_cnt < clk5_cnt_ht) clk5_out <= 1; else clk5_out <= 0; end always @(posedge clk6in or negedge clk6in or posedge rst_in_o) if (rst_in_o || ~clk6ps_en) begin clk6_cnt <= 8'b0; clk6_out <= 0; end else if (clk6_nc) clk6_out <= ~clk6_out; else begin if (clk6_cnt < clk6_cnt_max) clk6_cnt <= clk6_cnt + 1; else clk6_cnt <= 8'b0; if (clk6_cnt < clk6_cnt_ht) clk6_out <= 1; else clk6_out <= 0; end // assign CLKOUT0_out = clk0_out || clkfbout_tst; // faster? always @(clk0_out or clkfbout_tst or fb_delay_found) if (fb_delay_found == 1'b1) CLKOUT0_out = clk0_out; else CLKOUT0_out = clkfbout_tst; always @(clk1_out or clkfbout_tst or fb_delay_found) if (fb_delay_found == 1'b1) CLKOUT1_out = clk1_out; else CLKOUT1_out = clkfbout_tst; always @(clk2_out or clkfbout_tst or fb_delay_found) if (fb_delay_found == 1'b1) CLKOUT2_out = clk2_out; else CLKOUT2_out = clkfbout_tst; always @(clk3_out or clkfbout_tst or fb_delay_found) if (fb_delay_found == 1'b1) CLKOUT3_out = clk3_out; else CLKOUT3_out = clkfbout_tst; always @(clk4_out or clkfbout_tst or fb_delay_found) if (fb_delay_found == 1'b1) CLKOUT4_out = clk4_out; else CLKOUT4_out = clkfbout_tst; always @(clk5_out or clkfbout_tst or fb_delay_found) if (fb_delay_found == 1'b1) CLKOUT5_out = clk5_out; else CLKOUT5_out = clkfbout_tst; always @(clk6_out or clkfbout_tst or fb_delay_found) if (fb_delay_found == 1'b1) CLKOUT6_out = clk6_out; else CLKOUT6_out = clkfbout_tst; always @(clkfbout_out or clkfbout_tst or fb_delay_found) if (fb_delay_found == 1'b1) CLKFBOUT_out = clkfbout_out; else CLKFBOUT_out = clkfbout_tst; // // determine feedback delay // always @(posedge clkpll_r ) if (pwron_int || rst_int || fb_delay_found) clkfbout_tst <= 1'b0; else clkfbout_tst <= ~clkfbout_tst; always @( posedge clkfbout_tst or posedge rst_int ) if (rst_int) delay_edge <= 0; else delay_edge <= $time; always @(posedge CLKFBIN_in or posedge rst_int ) if (rst_int) begin fb_delay <= 0; fb_delay_found_tmp <= 0; end else if (fb_delay_found_tmp ==0 ) begin if ( delay_edge != 0) fb_delay <= ($time - delay_edge); else fb_delay <= 0; fb_delay_found_tmp <= 1; end always @(rst_int) if (rst_int) assign fb_delay_found = 1'b0; else deassign fb_delay_found; // always @(fb_delay_found_tmp or clkvco_delay ) // if (clkvco_delay == 0) // fb_delay_found <= #1000 fb_delay_found_tmp; // else // fb_delay_found <= #(clkvco_delay) fb_delay_found_tmp; always @(negedge clkfbout_tst) fb_delay_found <= fb_delay_found_tmp; always @(fb_delay or fb_delay_found) if (rst_int==0 && fb_delay_found==1'b1 && (fb_delay/1000.0 > fb_delay_max)) begin $display("Warning: [Unisim %s-25] The feedback delay at time %t is %f ns. It is over the maximum value %f ns. Instance %m ", MODULE_NAME, $time, fb_delay / 1000.0, fb_delay_max); end // // generate unlock signal // always #(2*period_avg/3+250) clkin_osc = ~rst_int && ~clkin_osc; always #(2*period_avg*divclk_div/3+250) clkfbin_osc = ~rst_int && ~clkfbin_osc; always @(posedge clkpll_r or negedge clkpll_r) begin clkin_p <= 1; clkin_p <= #100 0; end always @(posedge CLKFBIN_in or negedge CLKFBIN_in) begin clkfbin_p <= 1; clkfbin_p <= #100 0; end always @(posedge clkin_osc or posedge rst_int or posedge clkin_p) if (rst_int == 1) begin clkinstopped_out1 <= 0; clkin_lost_cnt <= 0; end else if (clkin_p == 1) begin if (clkinstopped_out1 == 1) begin @(posedge clkpll_r) begin clkinstopped_out1 <= 0; clkin_lost_cnt <= 0; end end else begin clkinstopped_out1 <= 0; clkin_lost_cnt <= 0; end end else if (lock_period) begin if (clkin_lost_cnt < clkin_lost_val) begin clkin_lost_cnt <= clkin_lost_cnt + 1; clkinstopped_out1 <= 0; end else clkinstopped_out1 <= 1; end always @(posedge clkfbin_osc or posedge rst_int or posedge clkfbin_p) if (rst_int == 1 || clkfbin_p == 1) begin clkfbstopped_out1 <= 0; clkfbin_lost_cnt <= 0; end else if (clkout_en) begin if (clkfbin_lost_cnt < clkfbin_lost_val) begin clkfbin_lost_cnt <= clkfbin_lost_cnt + 1; clkfbstopped_out1 <= 0; end else clkfbstopped_out1 <= 1; end always @(clkin_jit or rst_int ) if (rst_int) clkpll_jitter_unlock = 0; else if (pll_locked_tmp2 && clkfbstopped_out1 == 0 && clkinstopped_out1 == 0) begin if ((clkin_jit > REF_CLK_JITTER_MAX_tmp && clkin_jit < period_avg) || (clkin_jit < -REF_CLK_JITTER_MAX_tmp && clkin_jit > -period_avg )) clkpll_jitter_unlock = 1; else clkpll_jitter_unlock = 0; end else clkpll_jitter_unlock = 0; assign pll_unlock1 = (clkinstopped_out_dly ==1 || clkfbstopped_out1==1 || clkpll_jitter_unlock == 1) ? 1 : 0; assign pll_unlock = (clkinstopped_out_dly ==1 || clkfbstopped_out1==1 || clkpll_jitter_unlock == 1 || unlock_recover == 1) ? 1 : 0; // tasks task mc_to_attr; input [2:0] pm_f; input wf_f; input [2:0] frac; input frac_en; input wf_r; input [1:0] mx; input e; input nc; input [5:0] dt; input [2:0] pm_r; input en; input [5:0] ht; input [5:0] lt; output real div; output real phase; output real duty; integer odd_frac; reg odd; real frac_r; integer div_2; integer pm_f_c; real duty_step; real phase_step; begin if (nc == 1'b1) begin div = 1.0; phase = 0.0; duty = 0.5; end else if (frac_en == 1'b1) begin duty =0.50; if (dt == 6'b0 && pm_r == 3'b0) pm_f_c = pm_f; else if (pm_f >= pm_r) pm_f_c = pm_f - pm_r; else pm_f_c = 8 + pm_f - pm_r; if (pm_f_c < 4) begin odd = 1'b0; odd_frac = frac; end else begin odd = 1'b1; odd_frac = frac + 8; end frac_r = frac * 0.125; if (odd_frac > 9) div_2 = lt; else div_2 = lt + 1; div = 2 * div_2 + odd + frac_r; phase_step = 360.0 / (div * 8); phase = phase_step * (dt*8.0 + pm_r); end else begin if (ht == 6'b0 && lt == 6'b0) div = 128.0; else if (ht == 6'b0) div = 64.0 + lt * 1.0; else if (lt == 6'b0) div = ht * 1.0 + 64.0; else div = ht * 1.0 + lt * 1.0; duty_step = 0.5 / div; duty = (2.0 * ht + e) * duty_step; phase_step = 360.0 / div; phase = dt * phase_step; end end endtask task upper_mix_drp; output reg [2:0] pm_f; output reg wf_f; output reg [1:0] mx; output reg e; output reg nc; output reg [5:0] dt; input [15:0] DI; begin pm_f = DI[13:11]; wf_f = DI[10]; mx = DI[9:8]; e = DI[7]; nc = DI[6]; dt = DI[5:0]; end endtask task upper_frac_drp; output reg [2:0] frac; output reg frac_en; output reg wf_r; output reg [1:0] mx; output reg e; output reg nc; output reg [5:0] dt; input [15:0] DI; begin frac = DI[14:12]; frac_en = DI[11]; wf_r = DI[10]; mx = DI[9:8]; e = DI[7]; nc = DI[6]; dt = DI[5:0]; end endtask task upper_drp; output reg [1:0] mx; output reg e; output reg nc; output reg [5:0] dt; input [15:0] DI; begin mx = DI[9:8]; e = DI[7]; nc = DI[6]; dt = DI[5:0]; end endtask task lower_drp; output reg [2:0] pm_r; output reg en; output reg [5:0] ht; output reg [5:0] lt; input [15:0] DI; begin pm_r = DI[15:13]; en = DI[12]; ht = DI[11:6]; lt = DI[5:0]; end endtask //ht_calc( frac, frac_en, e, ht, lt, div_f, clk_rsel, clk_fsel, clk_fht, clk_flt, clk_cnt_max, clk_cnt_ht, clk_div) task ht_calc; input [2:0] frac; input frac_en; input e; input [5:0] ht; input [6:0] lt; input real f_div; output [3:0] clk_rsel; output [3:0] clk_fsel; output [6:0] clk_fht; output [6:0] clk_flt; output integer clk_cnt_max; output integer clk_cnt_ht; output integer clk_div_fint; integer clk_div_fint_odd; begin clk_div_fint = $rtoi(f_div); if (frac_en) begin clk_fht = clk_div_fint / 2; clk_flt = clk_div_fint / 2; clk_div_fint_odd = clk_div_fint - clk_fht - clk_flt; if (clk_div_fint_odd > 0) begin clk_rsel = (8 + frac) / 2; clk_fsel = 8 + frac - clk_rsel; end else begin clk_rsel = frac / 2; clk_fsel = frac - clk_rsel; end end else begin if (ht == 6'b0) clk_fht = 64; else clk_fht = ht; if (lt == 7'b0) clk_flt = 64; else clk_flt = lt; clk_cnt_max = 2 * (clk_fht + clk_flt) - 1; clk_cnt_ht = 2 * clk_fht + e; end end endtask task attr_to_mc; output reg [2:0] pm_f; output reg wf_f; output reg [2:0] frac; output reg frac_en; output reg wf_r; output reg [1:0] mx; output reg e; output reg nc; output reg [5:0] dt; output reg [2:0] pm_r; output reg en; output reg [5:0] ht; output reg [5:0] lt; input real div; input real phase; input real duty; integer div_int; real div_frac; real div_rnd; reg [37:0] vector; begin // determine frac_en div_int = $rtoi(div); div_frac = div - $itor(div_int); if (div_frac > 0.000) frac_en = 1'b1; else frac_en = 1'b0; // rnd frac to nearest 0.125 - may become .000 div_rnd = $itor($rtoi((div + 0.0625) * 8.0)) / 8.0; // determine int and frac part div_int = $rtoi(div_rnd); div_frac = div_rnd - $itor(div_int); if (div_int == 1) begin // nc = 1, rest are dummy pm_f = 3'b0; wf_f = 1'b0; frac = 3'b0; frac_en = 1'b0; wf_r = 1'b0; mx = 2'b0; e = 1'b0; nc = 1'b1; dt = 6'b0; pm_r = 3'b0; en = 1'b1; ht = 6'b1; lt = 6'b1; end else begin if (frac_en == 1'b1) vector = mmcm_frac_calc(div_int,phase*1000,duty*1000,div_frac*1000); else vector = mmcm_calc(div_int,phase*1000,duty*100000); if (frac_en == 1'b1) begin pm_f = vector[35:33]; wf_f = vector[32]; frac = vector[30:28]; frac_en = vector[27]; wf_r = vector[26]; end else begin pm_f = 3'b0; wf_f = 1'b0; frac = 3'b0; frac_en = 1'b0; wf_r = 1'b0; end mx = vector[25:24]; e = vector[23]; nc = vector[22]; dt = vector[21:16]; pm_r = vector[15:13]; en = 1'b1; ht = vector[11:6]; lt = vector[5:0]; end end endtask `define MMCME2_ADV_FRAC_PRECISION 10 `define MMCME2_ADV_FIXED_WIDTH 32 // This function takes a fixed point number and rounds it to the nearest // fractional precision bit. function [`MMCME2_ADV_FIXED_WIDTH:1] round_frac ( // Input is (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point number input [`MMCME2_ADV_FIXED_WIDTH:1] decimal, // This describes the precision of the fraction, for example a value // of 1 would modify the fractional so that instead of being a .16 // fractional, it would be a .1 (rounded to the nearest 0.5 in turn) input [`MMCME2_ADV_FIXED_WIDTH:1] precision ); begin // If the fractional precision bit is high then round up if( decimal[(`MMCME2_ADV_FRAC_PRECISION-precision)] == 1'b1) begin round_frac = decimal + (1'b1 << (`MMCME2_ADV_FRAC_PRECISION-precision)); end else begin round_frac = decimal; end end endfunction // This function calculates high_time, low_time, w_edge, and no_count // of a non-fractional counter based on the divide and duty cycle // // NOTE: high_time and low_time are returned as integers between 0 and 63 // inclusive. 64 should equal 6'b000000 (in other words it is okay to // ignore the overflow) function [13:0] mmcm_divider ( input [7:0] divide, // Max divide is 128 input [31:0] duty_cycle // Duty cycle is multiplied by 100,000 ); reg [`MMCME2_ADV_FIXED_WIDTH:1] duty_cycle_fix; // High/Low time is initially calculated with a wider integer to prevent a // calculation error when it overflows to 64. reg [6:0] high_time; reg [6:0] low_time; reg w_edge; reg no_count; reg [`MMCME2_ADV_FIXED_WIDTH:1] temp; begin // Duty Cycle must be between 0 and 1,000 if(duty_cycle <=0 || duty_cycle >= 100000) begin $display("ERROR: duty_cycle: %d is invalid", duty_cycle); $finish; end // Convert to FIXED_WIDTH-FRAC_PRECISION.FRAC_PRECISION fixed point duty_cycle_fix = (duty_cycle << `MMCME2_ADV_FRAC_PRECISION) / 100_000; // If the divide is 1 nothing needs to be set except the no_count bit. // Other values are dummies if(divide == 7'h01) begin high_time = 7'h01; w_edge = 1'b0; low_time = 7'h01; no_count = 1'b1; end else begin temp = round_frac(duty_cycle_fix*divide, 1); // comes from above round_frac high_time = temp[`MMCME2_ADV_FRAC_PRECISION+7:`MMCME2_ADV_FRAC_PRECISION+1]; // If the duty cycle * divide rounded is .5 or greater then this bit // is set. w_edge = temp[`MMCME2_ADV_FRAC_PRECISION]; // comes from round_frac // If the high time comes out to 0, it needs to be set to at least 1 // and w_edge set to 0 if(high_time == 7'h00) begin high_time = 7'h01; w_edge = 1'b0; end if(high_time == divide) begin high_time = divide - 1; w_edge = 1'b1; end // Calculate low_time based on the divide setting and set no_count to // 0 as it is only used when divide is 1. low_time = divide - high_time; no_count = 1'b0; end // Set the return value. mmcm_divider = {w_edge,no_count,high_time[5:0],low_time[5:0]}; end endfunction // This function calculates mx, delay_time, and phase_mux // of a non-fractional counter based on the divide and phase // // NOTE: The only valid value for the MX bits is 2'b00 to ensure the coarse mux // is used. function [10:0] mmcm_phase ( // divide must be an integer (use fractional if not) // assumed that divide already checked to be valid input [7:0] divide, // Max divide is 128 // Phase is given in degrees (-360,000 to 360,000) input signed [31:0] phase ); reg [`MMCME2_ADV_FIXED_WIDTH:1] phase_in_cycles; reg [`MMCME2_ADV_FIXED_WIDTH:1] phase_fixed; reg [1:0] mx; reg [5:0] delay_time; reg [2:0] phase_mux; reg [`MMCME2_ADV_FIXED_WIDTH:1] temp; begin if ((phase < -360000) || (phase > 360000)) begin $display("ERROR: phase of (%d) is not between -360000 and 360000. Instance %m",phase); $finish; end // If phase is less than 0, convert it to a positive phase shift // Convert to (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point if(phase < 0) begin phase_fixed = ( (phase + 360000) << `MMCME2_ADV_FRAC_PRECISION ) / 1000; end else begin phase_fixed = ( phase << `MMCME2_ADV_FRAC_PRECISION ) / 1000; end // Put phase in terms of decimal number of vco clock cycles phase_in_cycles = ( phase_fixed * divide ) / 360; temp = round_frac(phase_in_cycles, 3); // set mx to 2'b00 that the phase mux from the VCO is enabled mx = 2'b00; phase_mux = temp[`MMCME2_ADV_FRAC_PRECISION:`MMCME2_ADV_FRAC_PRECISION-2]; delay_time = temp[`MMCME2_ADV_FRAC_PRECISION+6:`MMCME2_ADV_FRAC_PRECISION+1]; // Setup the return value mmcm_phase={mx, phase_mux, delay_time}; end endfunction // This function takes in the divide, phase, and duty cycle // setting to calculate the upper and lower counter registers. function [37:0] mmcm_calc ( input [7:0] divide, // Max divide is 128 input signed [31:0] phase, input [31:0] duty_cycle // Multiplied by 100,000 ); reg [13:0] div_calc; reg [16:0] phase_calc; begin // w_edge[13], no_count[12], high_time[11:6], low_time[5:0] div_calc = mmcm_divider(divide, duty_cycle); // mx[10:9], pm[8:6], dt[5:0] phase_calc = mmcm_phase(divide, phase); // Return value is the upper and lower address of counter // Upper address is: // RESERVED [31:26] // MX [25:24] // EDGE [23] // NOCOUNT [22] // DELAY_TIME [21:16] // Lower Address is: // PHASE_MUX [15:13] // RESERVED [12] // HIGH_TIME [11:6] // LOW_TIME [5:0] mmcm_calc = { // Upper Address 6'h00, phase_calc[10:9], div_calc[13:12], phase_calc[5:0], // Lower Address phase_calc[8:6], 1'b0, div_calc[11:0] }; end endfunction // This function takes in the divide, phase, and duty cycle // setting to calculate the upper and lower counter registers. // for fractional multiply/divide functions. // // function [37:0] mmcm_frac_calc ( input [7:0] divide, // Max divide is 128 input signed [31:0] phase, input [31:0] duty_cycle, // Multiplied by 1,000 input [9:0] frac // Multiplied by 1000 ); //Required for fractional divide calculations reg [7:0] lt_frac; reg [7:0] ht_frac; reg /*[7:0]*/ wf_fall_frac; reg /*[7:0]*/ wf_rise_frac; reg [31:0] a; reg [7:0] pm_rise_frac_filtered ; reg [7:0] pm_fall_frac_filtered ; reg [7:0] clkout0_divide_int; reg [2:0] clkout0_divide_frac; reg [7:0] even_part_high; reg [7:0] even_part_low; reg [7:0] odd; reg [7:0] odd_and_frac; reg [7:0] pm_fall; reg [7:0] pm_rise; reg [7:0] dt; reg [7:0] dt_int; reg [63:0] dt_calc; reg [7:0] pm_rise_frac; reg [7:0] pm_fall_frac; reg [31:0] a_per_in_octets; reg [31:0] a_phase_in_cycles; parameter precision = 0.125; reg [31:0] phase_fixed; // changed to 31:0 from 32:1 jt 5/2/11 reg [31: 0] phase_pos; reg [31: 0] phase_vco; reg [31:0] temp;// changed to 31:0 from 32:1 jt 5/2/11 reg [13:0] div_calc; reg [16:0] phase_calc; begin //convert phase to fixed if ((phase < -360000) || (phase > 360000)) begin $display("ERROR: phase of (%d) is not between -360000 and 360000. Instance %m",phase); // $display("ERROR: phase of $phase is not between -360000 and 360000"); $finish; end // Return value is // Transfer data // RESERVED [37:36] // FRAC_TIME [35:33] // FRAC_WF_FALL [32] // Upper address is: // RESERVED [31:26] // MX [25:24] // EDGE [23] // NOCOUNT [22] // DELAY_TIME [21:16] // Lower Address is: // PHASE_MUX [15:13] // RESERVED [12] // HIGH_TIME [11:6] // LOW_TIME [5:0] clkout0_divide_frac = frac / 125; clkout0_divide_int = divide; even_part_high = clkout0_divide_int >> 1;//$rtoi(clkout0_divide_int / 2); even_part_low = even_part_high; odd = clkout0_divide_int - even_part_high - even_part_low; odd_and_frac = (8*odd) + clkout0_divide_frac; lt_frac = even_part_high - (odd_and_frac <= 9);//IF(odd_and_frac>9,even_part_high, even_part_high - 1) ht_frac = even_part_low - (odd_and_frac <= 8);//IF(odd_and_frac>8,even_part_low, even_part_low- 1) pm_fall = {odd[6:0],2'b00} + {6'h00, clkout0_divide_frac[2:1]}; // using >> instead of clkout0_divide_frac / 2 pm_rise = 0; //0 wf_fall_frac = ((odd_and_frac >=2) && (odd_and_frac <=9)) || ((clkout0_divide_frac == 1) && (clkout0_divide_int == 2));//CRS610807 wf_rise_frac = (odd_and_frac >=1) && (odd_and_frac <=8);//IF(odd_and_frac>=1,IF(odd_and_frac <= 8,1,0),0) //Calculate phase in fractional cycles a_per_in_octets = (8 * divide) + (frac / 125) ; a_phase_in_cycles = (phase+10) * a_per_in_octets / 360000 ;//Adding 1 due to rounding errors pm_rise_frac = (a_phase_in_cycles[7:0] ==8'h00)?8'h00:a_phase_in_cycles[7:0] - {a_phase_in_cycles[7:3],3'b000}; dt_calc = ((phase+10) * a_per_in_octets / 8 )/360000 ;//TRUNC(phase* divide / 360); //or_simply (a_per_in_octets / 8) dt = dt_calc[7:0]; pm_rise_frac_filtered = (pm_rise_frac >=8) ? (pm_rise_frac ) - 8: pm_rise_frac ; //((phase_fixed * (divide + frac / 1000)) / 360) - {pm_rise_frac[7:3],3'b000};//$rtoi(clkout0_phase * clkout0_divide / 45);//a; dt_int = dt + (& pm_rise_frac[7:4]); //IF(pm_rise_overwriting>7,dt+1,dt) pm_fall_frac = pm_fall + pm_rise_frac; pm_fall_frac_filtered = pm_fall + pm_rise_frac - {pm_fall_frac[7:3], 3'b000}; div_calc = mmcm_divider(divide, duty_cycle); //Use to determine edge[7], no count[6] phase_calc = mmcm_phase(divide, phase);// returns{mx[1:0], phase_mux[2:0], delay_time[5:0]} mmcm_frac_calc[37:0] = { 2'b00, pm_fall_frac_filtered[2:0], wf_fall_frac, 1'b0, clkout0_divide_frac[2:0], 1'b1, wf_rise_frac, phase_calc[10:9], div_calc[13:12], dt[5:0], pm_rise_frac_filtered[2], pm_rise_frac_filtered[1], pm_rise_frac_filtered[0], 1'b0, ht_frac[5:0], lt_frac[5:0] } ; end endfunction function clkout_duty_chk; input CLKOUT_DIVIDE; input CLKOUT_DUTY_CYCLE; input reg [160:0] CLKOUT_DUTY_CYCLE_N; integer CLKOUT_DIVIDE, step_tmp; real CLKOUT_DUTY_CYCLE; real CLK_DUTY_CYCLE_MIN, CLK_DUTY_CYCLE_MAX, CLK_DUTY_CYCLE_CHK, CLK_DUTY_CYCLE_STEP; real CLK_DUTY_CYCLE_MIN_rnd; reg clk_duty_tmp_int; begin if (CLKOUT_DIVIDE > O_MAX_HT_LT) begin CLK_DUTY_CYCLE_MIN = 1.0 * (CLKOUT_DIVIDE - O_MAX_HT_LT)/CLKOUT_DIVIDE; CLK_DUTY_CYCLE_MAX = (O_MAX_HT_LT )/CLKOUT_DIVIDE; CLK_DUTY_CYCLE_CHK = (O_MAX_HT_LT + 0.5)/CLKOUT_DIVIDE; CLK_DUTY_CYCLE_MIN_rnd = CLK_DUTY_CYCLE_MIN; end else begin if (CLKOUT_DIVIDE == 1) begin CLK_DUTY_CYCLE_MIN = 0.0; CLK_DUTY_CYCLE_MIN_rnd = 0.0; end else begin step_tmp = 1000 / CLKOUT_DIVIDE; CLK_DUTY_CYCLE_MIN_rnd = step_tmp / 1000.0; CLK_DUTY_CYCLE_MIN = 1.0 /CLKOUT_DIVIDE; end CLK_DUTY_CYCLE_CHK = 1.0; CLK_DUTY_CYCLE_MAX = 1.0; end if (CLKOUT_DUTY_CYCLE > CLK_DUTY_CYCLE_CHK || CLKOUT_DUTY_CYCLE < CLK_DUTY_CYCLE_MIN_rnd) begin $display("Warning: [Unisim %s-30] %s is set to %f and is not in the allowed range %f to %f. Instance %m ", MODULE_NAME, CLKOUT_DUTY_CYCLE_N, CLKOUT_DUTY_CYCLE, CLK_DUTY_CYCLE_MIN, CLK_DUTY_CYCLE_MAX ); end clk_duty_tmp_int = 0; CLK_DUTY_CYCLE_STEP = 0.5 / CLKOUT_DIVIDE; for (j = 0; j < (2 * CLKOUT_DIVIDE - CLK_DUTY_CYCLE_MIN/CLK_DUTY_CYCLE_STEP); j = j + 1) if (((CLK_DUTY_CYCLE_MIN + CLK_DUTY_CYCLE_STEP * j) - CLKOUT_DUTY_CYCLE) > -0.001 && ((CLK_DUTY_CYCLE_MIN + CLK_DUTY_CYCLE_STEP * j) - CLKOUT_DUTY_CYCLE) < 0.001) clk_duty_tmp_int = 1; if ( clk_duty_tmp_int != 1) begin $display("Warning: [Unisim %s-31] %s is set to %f and is not an allowed value. Allowed values are:", MODULE_NAME, CLKOUT_DUTY_CYCLE_N, CLKOUT_DUTY_CYCLE); for (j = 0; j < (2 * CLKOUT_DIVIDE - CLK_DUTY_CYCLE_MIN/CLK_DUTY_CYCLE_STEP); j = j + 1) $display("%f", CLK_DUTY_CYCLE_MIN + CLK_DUTY_CYCLE_STEP * j); $display(" Instance %m "); end clkout_duty_chk = 1'b1; end endfunction function para_int_range_chk; input para_in; input reg [160:0] para_name; input range_low; input range_high; integer para_in; integer range_low; integer range_high; begin if ( para_in < range_low || para_in > range_high) begin $display("Error: [Unisim %s-32] The Attribute %s is set to %d. Legal values for this attribute are %d to %d. Instance %m ", MODULE_NAME, para_name, para_in, range_low, range_high); $finish; end para_int_range_chk = 1'b1; end endfunction function para_real_range_chk; input para_in; input reg [160:0] para_name; input range_low; input range_high; real para_in; real range_low; real range_high; begin if ( para_in < range_low || para_in > range_high) begin $display("Error : [Unisim %s-33] The Attribute %s is set to %f. Legal values for this attribute are %f to %f. Instance %m ", MODULE_NAME, para_name, para_in, range_low, range_high); $finish; end para_real_range_chk = 1'b0; end endfunction `ifdef XIL_TIMING reg notifier; `endif specify (CLKIN1 => LOCKED) = (100:100:100, 100:100:100); (CLKIN2 => LOCKED) = (100:100:100, 100:100:100); (DCLK *> DO) = (100:100:100, 100:100:100); (DCLK => DRDY) = (100:100:100, 100:100:100); (PSCLK => PSDONE) = (100:100:100, 100:100:100); (negedge RST => (CLKFBSTOPPED +: 0)) = (100:100:100, 100:100:100); (negedge RST => (CLKINSTOPPED +: 0)) = (100:100:100, 100:100:100); (negedge RST => (LOCKED +: 0)) = (100:100:100, 100:100:100); (posedge RST => (CLKFBSTOPPED +: 0)) = (100:100:100, 100:100:100); (posedge RST => (CLKINSTOPPED +: 0)) = (100:100:100, 100:100:100); (posedge RST => (LOCKED +: 0)) = (100:100:100, 100:100:100); `ifdef XIL_TIMING $period (negedge CLKFBIN, 0:0:0, notifier); $period (negedge CLKFBOUT, 0:0:0, notifier); $period (negedge CLKFBOUTB, 0:0:0, notifier); $period (negedge CLKIN1, 0:0:0, notifier); $period (negedge CLKIN2, 0:0:0, notifier); $period (negedge CLKOUT0, 0:0:0, notifier); $period (negedge CLKOUT0B, 0:0:0, notifier); $period (negedge CLKOUT1, 0:0:0, notifier); $period (negedge CLKOUT1B, 0:0:0, notifier); $period (negedge CLKOUT2, 0:0:0, notifier); $period (negedge CLKOUT2B, 0:0:0, notifier); $period (negedge CLKOUT3, 0:0:0, notifier); $period (negedge CLKOUT3B, 0:0:0, notifier); $period (negedge CLKOUT4, 0:0:0, notifier); $period (negedge CLKOUT5, 0:0:0, notifier); $period (negedge CLKOUT6, 0:0:0, notifier); $period (negedge DCLK, 0:0:0, notifier); $period (negedge PSCLK, 0:0:0, notifier); $period (posedge CLKFBIN, 0:0:0, notifier); $period (posedge CLKFBOUT, 0:0:0, notifier); $period (posedge CLKFBOUTB, 0:0:0, notifier); $period (posedge CLKIN1, 0:0:0, notifier); $period (posedge CLKIN2, 0:0:0, notifier); $period (posedge CLKOUT0, 0:0:0, notifier); $period (posedge CLKOUT0B, 0:0:0, notifier); $period (posedge CLKOUT1, 0:0:0, notifier); $period (posedge CLKOUT1B, 0:0:0, notifier); $period (posedge CLKOUT2, 0:0:0, notifier); $period (posedge CLKOUT2B, 0:0:0, notifier); $period (posedge CLKOUT3, 0:0:0, notifier); $period (posedge CLKOUT3B, 0:0:0, notifier); $period (posedge CLKOUT4, 0:0:0, notifier); $period (posedge CLKOUT5, 0:0:0, notifier); $period (posedge CLKOUT6, 0:0:0, notifier); $period (posedge DCLK, 0:0:0, notifier); $period (posedge PSCLK, 0:0:0, notifier); $setuphold (posedge DCLK, negedge DADDR, 0:0:0, 0:0:0, notifier,,, DCLK_delay, DADDR_delay); $setuphold (posedge DCLK, negedge DEN, 0:0:0, 0:0:0, notifier,,, DCLK_delay, DEN_delay); $setuphold (posedge DCLK, negedge DI, 0:0:0, 0:0:0, notifier,,, DCLK_delay, DI_delay); $setuphold (posedge DCLK, negedge DWE, 0:0:0, 0:0:0, notifier,,, DCLK_delay, DWE_delay); $setuphold (posedge DCLK, posedge DADDR, 0:0:0, 0:0:0, notifier,,, DCLK_delay, DADDR_delay); $setuphold (posedge DCLK, posedge DEN, 0:0:0, 0:0:0, notifier,,, DCLK_delay, DEN_delay); $setuphold (posedge DCLK, posedge DI, 0:0:0, 0:0:0, notifier,,, DCLK_delay, DI_delay); $setuphold (posedge DCLK, posedge DWE, 0:0:0, 0:0:0, notifier,,, DCLK_delay, DWE_delay); $setuphold (posedge PSCLK, negedge PSEN, 0:0:0, 0:0:0, notifier,,, PSCLK_delay, PSEN_delay); $setuphold (posedge PSCLK, negedge PSINCDEC, 0:0:0, 0:0:0, notifier,,, PSCLK_delay, PSINCDEC_delay); $setuphold (posedge PSCLK, posedge PSEN, 0:0:0, 0:0:0, notifier,,, PSCLK_delay, PSEN_delay); $setuphold (posedge PSCLK, posedge PSINCDEC, 0:0:0, 0:0:0, notifier,,, PSCLK_delay, PSINCDEC_delay); $width (negedge CLKIN1, 0:0:0, 0, notifier); $width (negedge CLKIN2, 0:0:0, 0, notifier); $width (negedge DCLK, 0:0:0, 0, notifier); $width (negedge PSCLK, 0:0:0, 0, notifier); $width (negedge PWRDWN, 0:0:0, 0, notifier); $width (negedge RST, 0:0:0, 0, notifier); $width (posedge CLKIN1, 0:0:0, 0, notifier); $width (posedge CLKIN2, 0:0:0, 0, notifier); $width (posedge DCLK, 0:0:0, 0, notifier); $width (posedge PSCLK, 0:0:0, 0, notifier); $width (posedge PWRDWN, 0:0:0, 0, notifier); $width (posedge RST, 0:0:0, 0, notifier); `endif specparam PATHPULSE$ = 0; endspecify endmodule
module system1_input0 ( // inputs: address, clk, in_port, reset_n, // outputs: readdata ) ; output [ 31: 0] readdata; input [ 1: 0] address; input clk; input [ 31: 0] in_port; input reset_n; wire clk_en; wire [ 31: 0] data_in; wire [ 31: 0] read_mux_out; reg [ 31: 0] readdata; assign clk_en = 1; //s1, which is an e_avalon_slave assign read_mux_out = {32 {(address == 0)}} & data_in; always @(posedge clk or negedge reset_n) begin if (reset_n == 0) readdata <= 0; else if (clk_en) readdata <= {32'b0 | read_mux_out}; end assign data_in = in_port; endmodule
module. Any csc conversions must be disabled on info frame assign hdmi_tpm_mismatch_s = (hdmi_data_422 == hdmi_tpm_data_s) ? 1'b0 : hdmi_de_422; assign hdmi_tpm_data_s = {hdmi_tpm_data[3:2], 6'h20, hdmi_tpm_data[1:0], 6'h20}; always @(posedge hdmi_clk) begin if (hdmi_fs_422 == 1'b1) begin hdmi_tpm_data <= 'd0; end else if (hdmi_de_422 == 1'b1) begin hdmi_tpm_data <= hdmi_tpm_data + 1'b1; end if (hdmi_tpm_mismatch_s == 1'b1) begin hdmi_tpm_mismatch_count <= 5'h10; end else if (hdmi_tpm_mismatch_count[4] == 1'b1) begin hdmi_tpm_mismatch_count <= hdmi_tpm_mismatch_count + 1'b1; end hdmi_tpm_oos <= hdmi_tpm_mismatch_count[4]; end // fs, enable and data on 422 and 444 domains always @(posedge hdmi_clk) begin hdmi_fs_422 <= hdmi_sof & hdmi_enable; hdmi_de_422 <= hdmi_hs_de & hdmi_vs_de & hdmi_enable; hdmi_data_422 <= hdmi_data_de; if (hdmi_up_csc_bypass == 1'b1) begin hdmi_fs_444 <= hdmi_fs_422; hdmi_de_444 <= hdmi_de_422; end else begin hdmi_fs_444 <= hdmi_fs_444_s; hdmi_de_444 <= hdmi_de_444_s; end if (hdmi_up_tpg_enable == 1'b1) begin hdmi_data_444 <= hdmi_tpm_data; end else if (hdmi_up_csc_bypass == 1'b1) begin hdmi_data_444 <= {8'd0, hdmi_data_422}; end else begin hdmi_data_444 <= hdmi_data_444_s; end hdmi_fs_444_d <= hdmi_fs_444; hdmi_de_444_d <= hdmi_de_444; hdmi_data_444_d <= hdmi_data_444; end // start of frame assign hdmi_sof_s = hdmi_vs_de & ~hdmi_vs_de_d; assign hdmi_count_mismatch_s = hdmi_hs_count_mismatch | hdmi_vs_count_mismatch; assign hdmi_oos_s = ((hdmi_hs_count == hdmi_up_hs_count) && (hdmi_vs_count == hdmi_up_vs_count)) ? hdmi_count_mismatch_s : 1'b1; // hdmi side of the interface, horizontal and vertical sync counters. // capture active video size and report mismatch always @(posedge hdmi_clk) begin hdmi_oos <= hdmi_oos_s; hdmi_sof <= hdmi_sof_s; hdmi_hs_de_d <= hdmi_hs_de; hdmi_vs_de_d <= hdmi_vs_de; if ((hdmi_hs_de == 1'b1) && (hdmi_hs_de_d == 1'b0)) begin hdmi_hs_run_count <= 'd1; end else if (hdmi_hs_de == 1'b1) begin hdmi_hs_run_count <= hdmi_hs_run_count + 1'b1; end if ((hdmi_vs_de == 1'b1) && (hdmi_vs_de_d == 1'b0)) begin hdmi_vs_run_count <= 'd0; end else if ((hdmi_vs_de == 1'b1) && (hdmi_hs_de == 1'b1) && (hdmi_hs_de_d == 1'b0)) begin hdmi_vs_run_count <= hdmi_vs_run_count + 1'b1; end if ((hdmi_hs_de == 1'b0) && (hdmi_hs_de_d == 1'b1)) begin hdmi_hs_count_mismatch <= (hdmi_hs_count == hdmi_hs_run_count) ? 1'b0 : 1'b1; hdmi_hs_count_toggle <= ~hdmi_hs_count_toggle; hdmi_hs_count <= hdmi_hs_run_count; end if ((hdmi_vs_de == 1'b0) && (hdmi_vs_de_d == 1'b1)) begin hdmi_vs_count_mismatch <= (hdmi_vs_count == hdmi_vs_run_count) ? 1'b0 : 1'b1; hdmi_vs_count_toggle <= ~hdmi_vs_count_toggle; hdmi_vs_count <= hdmi_vs_run_count; end if (hdmi_sof_s == 1'b1) begin hdmi_enable <= hdmi_up_enable & ~hdmi_oos_s; end end // delay to get rid of eav's 4 bytes always @(posedge hdmi_clk) begin hdmi_data_d <= hdmi_data_p; hdmi_hs_de_rcv_d <= hdmi_hs_de_rcv; hdmi_vs_de_rcv_d <= hdmi_vs_de_rcv; hdmi_data_2d <= hdmi_data_d; hdmi_hs_de_rcv_2d <= hdmi_hs_de_rcv_d; hdmi_vs_de_rcv_2d <= hdmi_vs_de_rcv_d; hdmi_data_3d <= hdmi_data_2d; hdmi_hs_de_rcv_3d <= hdmi_hs_de_rcv_2d; hdmi_vs_de_rcv_3d <= hdmi_vs_de_rcv_2d; hdmi_data_4d <= hdmi_data_3d; hdmi_hs_de_rcv_4d <= hdmi_hs_de_rcv_3d; hdmi_vs_de_rcv_4d <= hdmi_vs_de_rcv_3d; hdmi_data_de <= hdmi_data_4d; hdmi_hs_de <= hdmi_hs_de_rcv & hdmi_hs_de_rcv_4d; hdmi_vs_de <= hdmi_vs_de_rcv & hdmi_vs_de_rcv_4d; end // check for sav and eav and generate the corresponding enables always @(posedge hdmi_clk) begin if ((hdmi_data_p == 16'hffff) || (hdmi_data_p == 16'h0000)) begin hdmi_preamble_cnt <= hdmi_preamble_cnt + 1'b1; end else begin hdmi_preamble_cnt <= 'd0; end if (hdmi_preamble_cnt == 3'b11) begin if ((hdmi_data_p == 16'hb6b6) || (hdmi_data_p == 16'h9d9d)) begin hdmi_hs_de_rcv <= 1'b0; end else if ((hdmi_data_p == 16'habab) || (hdmi_data_p == 16'h8080)) begin hdmi_hs_de_rcv <= 1'b1; end if (hdmi_data_p == 16'hb6b6) begin hdmi_vs_de_rcv <= 1'b0; end else if (hdmi_data_p == 16'h9d9d) begin hdmi_vs_de_rcv <= 1'b1; end end end // hdmi input data registers always @(posedge hdmi_clk) begin hdmi_data_neg_p <= hdmi_data_neg; hdmi_data_pos_p <= hdmi_data; if (hdmi_up_edge_sel == 1'b1) begin hdmi_data_p <= hdmi_data_neg_p; end else begin hdmi_data_p <= hdmi_data_pos_p; end end always @(negedge hdmi_clk) begin hdmi_data_neg <= hdmi_data; end // microprocessor signals on the hdmi side reg [2:0] hdmi_up_toggle; assign hdmi_up_toggle_ret = hdmi_up_toggle[2]; always @(posedge hdmi_clk) begin hdmi_up_toggle[0] <= up_toggle; hdmi_up_toggle[2:1] <= hdmi_up_toggle[1:0]; if (hdmi_up_toggle[2] ^ hdmi_up_toggle[1]) begin hdmi_up_enable <= up_enable; hdmi_up_crcb_init <= up_crcb_init; hdmi_up_edge_sel <= up_edge_sel; hdmi_up_hs_count <= up_hs_count; hdmi_up_vs_count <= up_vs_count; hdmi_up_csc_bypass <= up_csc_bypass; hdmi_up_tpg_enable <= up_tpg_enable; end end // super sampling, 422 to 444 cf_ss_422to444 i_ss ( .clk (hdmi_clk), .s422_vs (1'b0), .s422_hs (hdmi_fs_422), .s422_de (hdmi_de_422), .s422_data (hdmi_data_422), .s444_vs (), .s444_hs (ss_fs_s), .s444_de (ss_de_s), .s444_data (ss_data_s), .Cr_Cb_sel_init (hdmi_up_crcb_init)); // color space conversion, CrYCb to RGB cf_csc_CrYCb2RGB i_csc ( .clk (hdmi_clk), .CrYCb_vs (1'b0), .CrYCb_hs (ss_fs_s), .CrYCb_de (ss_de_s), .CrYCb_data (ss_data_s), .RGB_vs (), .RGB_hs (hdmi_fs_444_s), .RGB_de (hdmi_de_444_s), .RGB_data (hdmi_data_444_s)); endmodule
module stack( reset, clock, nip, dup, we, data_in, tos_out, nos_out); input reset; input clock; input nip; input dup; input we; input [`BITS-1:0] data_in; output [`BITS-1:0] tos_out; output [`BITS-1:0] nos_out; reg [`BITS-1:0] nos; reg [`BITS-1:0] tos; reg [`PTR-1:0] sp; reg [`PTR-1:0] nsp; reg [`BITS-1:0] cells[`DEPTH-1:0]; always @* begin nsp = sp - 1; end assign tos_out = cells[sp]; assign nos_out = cells[nsp]; always @(posedge clock) begin if (reset) begin sp = `PTR 'b0000; cells[sp] = `BITS 'b0; tos = `BITS 'b0; nos = `BITS 'b0; end tos = cells[sp]; nos = cells[nsp]; if (nip & !dup) begin // nip sp = sp - 1; end if (dup & !nip) begin // dup sp = sp + 1; end if (dup & nip) begin // swap cells[nsp] = tos; tos = nos; end if (we) begin tos = data_in; end cells[sp] = tos; end endmodule
module sky130_fd_sc_lp__dlygate4s18 ( X, A ); // Module ports output X; input A; // Module supplies supply1 VPWR; supply0 VGND; supply1 VPB ; supply0 VNB ; // Local signals wire buf0_out_X; // Name Output Other arguments buf buf0 (buf0_out_X, A ); buf buf1 (X , buf0_out_X ); endmodule
module at the start * of the simulation */ always begin /** * Clock frequency is arbitrarily chosen; * Period = 5ns <==> 200 MHz clock */ #5 clock = 0; #5 clock = 1; end // ============================================================ /** * Instantiate an instance of regfile() so that * inputs can be passed to the Device Under Test (DUT) * Given instance name is "rg" */ program_counter pc ( // instance_name(signal name), // Signal name can be the same as the instance name // next_pc,cur_pc,rst,clk n_pc,c_pc,reset,clock); // ============================================================ /** * Initial block start executing sequentially @ t=0 * If and when a delay is encountered, the execution of this block * pauses or waits until the delay time has passed, before resuming * execution * * Each intial or always block executes concurrently; that is, * multiple "always" or "initial" blocks will execute simultaneously * * E.g. * always * begin * #10 clk_50 = ~clk_50; // Invert clock signal every 10 ns * // Clock signal has a period of 20 ns or 50 MHz * end */ initial begin // "$time" indicates the current time in the simulation $display($time, " << Starting the simulation >>"); c_pc=$random; reset=1'b1; #10 c_pc=200; reset=1'b0; // Write to 8 data locations for(count=200; count<216; count=count+1) begin #20 //c_pc=count; c_pc=n_pc; reset=1'b0; end // end simulation #30 $display($time, " << Finishing the simulation >>"); $finish; end endmodule
module sky130_fd_sc_lp__and2b ( X , A_N , B , VPWR, VGND, VPB , VNB ); // Module ports output X ; input A_N ; input B ; input VPWR; input VGND; input VPB ; input VNB ; // Local signals wire not0_out ; wire and0_out_X ; wire pwrgood_pp0_out_X; // Name Output Other arguments not not0 (not0_out , A_N ); and and0 (and0_out_X , not0_out, B ); sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND); buf buf0 (X , pwrgood_pp0_out_X ); endmodule
module sky130_fd_sc_hs__a21bo_2 ( X , A1 , A2 , B1_N, VPWR, VGND ); output X ; input A1 ; input A2 ; input B1_N; input VPWR; input VGND; sky130_fd_sc_hs__a21bo base ( .X(X), .A1(A1), .A2(A2), .B1_N(B1_N), .VPWR(VPWR), .VGND(VGND) ); endmodule
module sky130_fd_sc_hs__a21bo_2 ( X , A1 , A2 , B1_N ); output X ; input A1 ; input A2 ; input B1_N; // Voltage supply signals supply1 VPWR; supply0 VGND; sky130_fd_sc_hs__a21bo base ( .X(X), .A1(A1), .A2(A2), .B1_N(B1_N) ); endmodule
module // wire alu_req_alu = alu_op & i_rdwen;// Regular ALU only req datapath when it need to write-back `ifdef E203_SUPPORT_SHARE_MULDIV //{ wire muldiv_req_alu = mdv_op;// Since MULDIV have no point to let rd=0, so always need ALU datapath `endif//E203_SUPPORT_SHARE_MULDIV} wire bjp_req_alu = bjp_op;// Since BJP may not write-back, but still need ALU datapath wire agu_req_alu = agu_op;// Since AGU may have some other features, so always need ALU datapath e203_exu_alu_dpath u_e203_exu_alu_dpath( .alu_req_alu (alu_req_alu ), .alu_req_alu_add (alu_req_alu_add ), .alu_req_alu_sub (alu_req_alu_sub ), .alu_req_alu_xor (alu_req_alu_xor ), .alu_req_alu_sll (alu_req_alu_sll ), .alu_req_alu_srl (alu_req_alu_srl ), .alu_req_alu_sra (alu_req_alu_sra ), .alu_req_alu_or (alu_req_alu_or ), .alu_req_alu_and (alu_req_alu_and ), .alu_req_alu_slt (alu_req_alu_slt ), .alu_req_alu_sltu (alu_req_alu_sltu ), .alu_req_alu_lui (alu_req_alu_lui ), .alu_req_alu_op1 (alu_req_alu_op1 ), .alu_req_alu_op2 (alu_req_alu_op2 ), .alu_req_alu_res (alu_req_alu_res ), .bjp_req_alu (bjp_req_alu ), .bjp_req_alu_op1 (bjp_req_alu_op1 ), .bjp_req_alu_op2 (bjp_req_alu_op2 ), .bjp_req_alu_cmp_eq (bjp_req_alu_cmp_eq ), .bjp_req_alu_cmp_ne (bjp_req_alu_cmp_ne ), .bjp_req_alu_cmp_lt (bjp_req_alu_cmp_lt ), .bjp_req_alu_cmp_gt (bjp_req_alu_cmp_gt ), .bjp_req_alu_cmp_ltu (bjp_req_alu_cmp_ltu ), .bjp_req_alu_cmp_gtu (bjp_req_alu_cmp_gtu ), .bjp_req_alu_add (bjp_req_alu_add ), .bjp_req_alu_cmp_res (bjp_req_alu_cmp_res ), .bjp_req_alu_add_res (bjp_req_alu_add_res ), .agu_req_alu (agu_req_alu ), .agu_req_alu_op1 (agu_req_alu_op1 ), .agu_req_alu_op2 (agu_req_alu_op2 ), .agu_req_alu_swap (agu_req_alu_swap ), .agu_req_alu_add (agu_req_alu_add ), .agu_req_alu_and (agu_req_alu_and ), .agu_req_alu_or (agu_req_alu_or ), .agu_req_alu_xor (agu_req_alu_xor ), .agu_req_alu_max (agu_req_alu_max ), .agu_req_alu_min (agu_req_alu_min ), .agu_req_alu_maxu (agu_req_alu_maxu ), .agu_req_alu_minu (agu_req_alu_minu ), .agu_req_alu_res (agu_req_alu_res ), .agu_sbf_0_ena (agu_sbf_0_ena ), .agu_sbf_0_nxt (agu_sbf_0_nxt ), .agu_sbf_0_r (agu_sbf_0_r ), .agu_sbf_1_ena (agu_sbf_1_ena ), .agu_sbf_1_nxt (agu_sbf_1_nxt ), .agu_sbf_1_r (agu_sbf_1_r ), `ifdef E203_SUPPORT_SHARE_MULDIV //{ .muldiv_req_alu (muldiv_req_alu ), .muldiv_req_alu_op1 (muldiv_req_alu_op1), .muldiv_req_alu_op2 (muldiv_req_alu_op2), .muldiv_req_alu_add (muldiv_req_alu_add), .muldiv_req_alu_sub (muldiv_req_alu_sub), .muldiv_req_alu_res (muldiv_req_alu_res), .muldiv_sbf_0_ena (muldiv_sbf_0_ena ), .muldiv_sbf_0_nxt (muldiv_sbf_0_nxt ), .muldiv_sbf_0_r (muldiv_sbf_0_r ), .muldiv_sbf_1_ena (muldiv_sbf_1_ena ), .muldiv_sbf_1_nxt (muldiv_sbf_1_nxt ), .muldiv_sbf_1_r (muldiv_sbf_1_r ), `endif//E203_SUPPORT_SHARE_MULDIV} .clk (clk ), .rst_n (rst_n ) ); wire ifu_excp_o_valid; wire ifu_excp_o_ready; wire [`E203_XLEN-1:0] ifu_excp_o_wbck_wdat; wire ifu_excp_o_wbck_err; assign ifu_excp_i_ready = ifu_excp_o_ready; assign ifu_excp_o_valid = ifu_excp_i_valid; assign ifu_excp_o_wbck_wdat = `E203_XLEN'b0; assign ifu_excp_o_wbck_err = 1'b1;// IFU illegal instruction always treat as error ////////////////////////////////////////////////////////////// // Aribtrate the Result and generate output interfaces // wire o_valid; wire o_ready; wire o_sel_ifu_excp = ifu_excp_op; wire o_sel_alu = alu_op; wire o_sel_bjp = bjp_op; wire o_sel_csr = csr_op; wire o_sel_agu = agu_op; `ifdef E203_SUPPORT_SHARE_MULDIV //{ wire o_sel_mdv = mdv_op; `endif//E203_SUPPORT_SHARE_MULDIV} assign o_valid = (o_sel_alu & alu_o_valid ) | (o_sel_bjp & bjp_o_valid ) | (o_sel_csr & csr_o_valid ) | (o_sel_agu & agu_o_valid ) | (o_sel_ifu_excp & ifu_excp_o_valid) `ifdef E203_SUPPORT_SHARE_MULDIV //{ | (o_sel_mdv & mdv_o_valid ) `endif//E203_SUPPORT_SHARE_MULDIV} ; assign ifu_excp_o_ready = o_sel_ifu_excp & o_ready; assign alu_o_ready = o_sel_alu & o_ready; assign agu_o_ready = o_sel_agu & o_ready; `ifdef E203_SUPPORT_SHARE_MULDIV //{ assign mdv_o_ready = o_sel_mdv & o_ready; `endif//E203_SUPPORT_SHARE_MULDIV} assign bjp_o_ready = o_sel_bjp & o_ready; assign csr_o_ready = o_sel_csr & o_ready; assign wbck_o_wdat = ({`E203_XLEN{o_sel_alu}} & alu_o_wbck_wdat) | ({`E203_XLEN{o_sel_bjp}} & bjp_o_wbck_wdat) | ({`E203_XLEN{o_sel_csr}} & csr_o_wbck_wdat) | ({`E203_XLEN{o_sel_agu}} & agu_o_wbck_wdat) `ifdef E203_SUPPORT_SHARE_MULDIV //{ | ({`E203_XLEN{o_sel_mdv}} & mdv_o_wbck_wdat) `endif//E203_SUPPORT_SHARE_MULDIV} | ({`E203_XLEN{o_sel_ifu_excp}} & ifu_excp_o_wbck_wdat) ; assign wbck_o_rdidx = i_rdidx; wire wbck_o_rdwen = i_rdwen; wire wbck_o_err = ({1{o_sel_alu}} & alu_o_wbck_err) | ({1{o_sel_bjp}} & bjp_o_wbck_err) | ({1{o_sel_csr}} & csr_o_wbck_err) | ({1{o_sel_agu}} & agu_o_wbck_err) `ifdef E203_SUPPORT_SHARE_MULDIV //{ | ({1{o_sel_mdv}} & mdv_o_wbck_err) `endif//E203_SUPPORT_SHARE_MULDIV} | ({1{o_sel_ifu_excp}} & ifu_excp_o_wbck_err) ; // Each Instruction need to commit or write-back // * The write-back only needed when the unit need to write-back // the result (need to write RD), and it is not a long-pipe uop // (need to be write back by its long-pipe write-back, not here) // * Each instruction need to be commited wire o_need_wbck = wbck_o_rdwen & (~i_longpipe) & (~wbck_o_err); wire o_need_cmt = 1'b1; assign o_ready = (o_need_cmt ? cmt_o_ready : 1'b1) & (o_need_wbck ? wbck_o_ready : 1'b1); assign wbck_o_valid = o_need_wbck & o_valid & (o_need_cmt ? cmt_o_ready : 1'b1); assign cmt_o_valid = o_need_cmt & o_valid & (o_need_wbck ? wbck_o_ready : 1'b1); // // The commint interface have some special signals assign cmt_o_instr = i_instr; assign cmt_o_pc = i_pc; assign cmt_o_imm = i_imm; assign cmt_o_rv32 = i_info[`E203_DECINFO_RV32]; // The cmt_o_pc_vld is used by the commit stage to check // if current instruction is outputing a valid current PC // to guarante the commit to flush pipeline safely, this // vld only be asserted when: // * There is a valid instruction here // --- otherwise, the commit stage may use wrong PC // value to stored in DPC or EPC assign cmt_o_pc_vld = // Otherwise, just use the i_pc_vld i_pc_vld; assign cmt_o_misalgn = (o_sel_agu & agu_o_cmt_misalgn) ; assign cmt_o_ld = (o_sel_agu & agu_o_cmt_ld) ; assign cmt_o_badaddr = ({`E203_ADDR_SIZE{o_sel_agu}} & agu_o_cmt_badaddr) ; assign cmt_o_buserr = o_sel_agu & agu_o_cmt_buserr; assign cmt_o_stamo = o_sel_agu & agu_o_cmt_stamo ; assign cmt_o_bjp = o_sel_bjp & bjp_o_cmt_bjp; assign cmt_o_mret = o_sel_bjp & bjp_o_cmt_mret; assign cmt_o_dret = o_sel_bjp & bjp_o_cmt_dret; assign cmt_o_bjp_prdt = o_sel_bjp & bjp_o_cmt_prdt; assign cmt_o_bjp_rslv = o_sel_bjp & bjp_o_cmt_rslv; assign cmt_o_fencei = o_sel_bjp & bjp_o_cmt_fencei; assign cmt_o_ecall = o_sel_alu & alu_o_cmt_ecall; assign cmt_o_ebreak = o_sel_alu & alu_o_cmt_ebreak; assign cmt_o_wfi = o_sel_alu & alu_o_cmt_wfi; assign cmt_o_ifu_misalgn = i_misalgn; assign cmt_o_ifu_buserr = i_buserr; assign cmt_o_ifu_ilegl = i_ilegl | (o_sel_csr & csr_access_ilgl) ; endmodule
module pcie3_7x_0_pcie_init_ctrl_7vx # ( parameter TCQ = 100, parameter PL_UPSTREAM_FACING = "TRUE" ) ( input clk_i, // User Clock output reset_n_o, // Fundamental reset, active low output pipe_reset_n_o, // Resets the PIPE clock domain logic, active low output mgmt_reset_n_o, // Resets management and configuration registers, active low output mgmt_sticky_reset_n_o, // Resets sticky management and configuration register bits, active low input mmcm_lock_i, // MMCM Locked : 1b = MMCM Locked input phy_rdy_i, // GT is ready : 1b = GT Ready input cfg_input_update_done_i, // Configuration Input update Complete output cfg_input_update_request_o, // Configuration Input Update Request input cfg_mc_update_done_i, // Configuration Memory Cell Update Complete output cfg_mc_update_request_o, // Configuration Memory Cell Update Request input user_cfg_input_update_i, // User driven Configuration Input Update Request output [2:0] state_o // Debug state ); // Local Params localparam STATE_RESET = 3'b000; localparam STATE_MGMT_RESET_DEASSERT = 3'b001; localparam STATE_MC_TRANSFER_REQ = 3'b010; localparam STATE_INPUT_UPDATE_REQ = 3'b011; localparam STATE_PHY_RDY = 3'b100; localparam STATE_RESET_DEASSERT = 3'b101; localparam STATE_INPUT_UPDATE_REQ_REDO = 3'b110; localparam STATE_MGMT_RESET_ASSERT = 3'b111; // Local Registers reg [2:0] reg_state /* synthesis syn_state_machine=1 */; reg [2:0] reg_next_state; reg [1:0] reg_clock_locked; reg [1:0] reg_phy_rdy; reg reg_cold_reset = 1'b1 ; reg reg_reset_n_o; reg reg_pipe_reset_n_o; reg reg_mgmt_reset_n_o; reg reg_mgmt_sticky_reset_n_o; reg reg_cfg_input_update_request_o; reg reg_cfg_mc_update_request_o; reg [1:0] reg_reset_timer; reg [4:0] reg_mgmt_reset_timer; reg regff_mgmt_reset_n_o = 1'b0; reg regff_mgmt_sticky_reset_n_o = 1'b0; reg regff_reset_n_o = 1'b0; reg regff_pipe_reset_n_o = 1'b0; // Local Wires wire [2:0] state_w; wire [2:0] next_state_w; wire clock_locked; wire phy_rdy; wire cold_reset; wire [1:0] reset_timer_w; // Synchronize MMCM lock output always @ (posedge clk_i or negedge mmcm_lock_i) begin if (!mmcm_lock_i) begin reg_clock_locked[1:0] <= #TCQ 2'b11; end else begin reg_clock_locked[1:0] <= #TCQ {reg_clock_locked[0], 1'b0}; end end assign clock_locked = !reg_clock_locked[1]; // Synchronize PHY Ready always @ (posedge clk_i or negedge phy_rdy_i) begin if (!phy_rdy_i) begin reg_phy_rdy[1:0] <= #TCQ 2'b11; end else begin reg_phy_rdy[1:0] <= #TCQ {reg_phy_rdy[0], 1'b0}; end end assign phy_rdy = !reg_phy_rdy[1]; // Controller FSM always @ (posedge clk_i or negedge clock_locked) begin if (!clock_locked) begin reg_state <= #(TCQ) STATE_RESET; reg_reset_timer <= #(TCQ) 2'b00; end else begin reg_state <= #(TCQ) reg_next_state; if ((state_w == STATE_MGMT_RESET_DEASSERT) && (reset_timer_w != 2'b11)) reg_reset_timer <= #(TCQ) reset_timer_w + 1'b1; end end always @ (posedge clk_i) begin // reset the cold reset flag if ((state_w == STATE_PHY_RDY) && (next_state_w == STATE_RESET_DEASSERT) && (cold_reset == 1'b1)) reg_cold_reset <= #(TCQ) 1'b0; end always @ (posedge clk_i) begin // mgmt reset timer if (state_w == STATE_MGMT_RESET_ASSERT) reg_mgmt_reset_timer <= #(TCQ) reg_mgmt_reset_timer + 1'b1; else if (state_w == STATE_MGMT_RESET_DEASSERT) reg_mgmt_reset_timer <= #(TCQ) 5'h00; else reg_mgmt_reset_timer <= #(TCQ) reg_mgmt_reset_timer; end generate // Resets for EP and Downstream Port begin: generate_resets if( PL_UPSTREAM_FACING == "TRUE") // DUT is a EP begin always @ (*) begin reg_next_state = STATE_RESET; reg_mgmt_reset_n_o = 1'b1; reg_mgmt_sticky_reset_n_o = 1'b1; reg_cfg_input_update_request_o = 1'b0; reg_cfg_mc_update_request_o = 1'b0; reg_reset_n_o = 1'b0; reg_pipe_reset_n_o = 1'b0; case(state_w) STATE_RESET : begin reg_mgmt_reset_n_o = 1'b0; reg_mgmt_sticky_reset_n_o = 1'b0; if (clock_locked) begin reg_next_state = STATE_MGMT_RESET_DEASSERT; end else begin reg_next_state = STATE_RESET; end end STATE_MGMT_RESET_DEASSERT : begin if (reset_timer_w == 2'b11) begin reg_next_state = STATE_MC_TRANSFER_REQ; end else begin reg_next_state = STATE_MGMT_RESET_DEASSERT; end end STATE_MC_TRANSFER_REQ : begin reg_cfg_mc_update_request_o = 1'b1; if (cfg_mc_update_done_i) begin reg_next_state = STATE_INPUT_UPDATE_REQ; end else begin reg_next_state = STATE_MC_TRANSFER_REQ; end end STATE_INPUT_UPDATE_REQ : begin reg_cfg_input_update_request_o = 1'b1; if (cfg_input_update_done_i) begin reg_next_state = STATE_PHY_RDY; end else begin reg_next_state = STATE_INPUT_UPDATE_REQ; end end STATE_PHY_RDY : begin // Check warm reset flag if (!cold_reset) begin reg_pipe_reset_n_o = 1'b1; end if (phy_rdy) begin reg_next_state = STATE_RESET_DEASSERT; end else begin reg_next_state = STATE_PHY_RDY; end end STATE_RESET_DEASSERT : begin reg_reset_n_o = 1'b1; reg_pipe_reset_n_o = 1'b1; if (!phy_rdy) begin reg_next_state = STATE_MGMT_RESET_ASSERT; end else if (user_cfg_input_update_i) begin reg_next_state = STATE_INPUT_UPDATE_REQ_REDO; end else begin reg_next_state = STATE_RESET_DEASSERT; end end STATE_INPUT_UPDATE_REQ_REDO : begin reg_reset_n_o = 1'b1; reg_pipe_reset_n_o = 1'b1; reg_cfg_input_update_request_o = 1'b1; if (cfg_input_update_done_i) begin reg_next_state = STATE_RESET_DEASSERT; end else begin reg_next_state = STATE_INPUT_UPDATE_REQ_REDO; end end STATE_MGMT_RESET_ASSERT : begin if (reg_mgmt_reset_timer == 5'h1f) begin reg_next_state = STATE_MGMT_RESET_DEASSERT; reg_mgmt_reset_n_o = 1'b1; end else begin reg_next_state = STATE_MGMT_RESET_ASSERT; reg_mgmt_reset_n_o = 1'b0; end end endcase end //always end else begin // DUT is a Downstream port always @ (*) begin reg_next_state = STATE_RESET; reg_mgmt_reset_n_o = 1'b1; reg_mgmt_sticky_reset_n_o = 1'b1; reg_cfg_input_update_request_o = 1'b0; reg_cfg_mc_update_request_o = 1'b0; reg_reset_n_o = 1'b0; reg_pipe_reset_n_o = 1'b0; case(state_w) STATE_RESET : begin reg_mgmt_reset_n_o = 1'b0; reg_mgmt_sticky_reset_n_o = 1'b0; if (clock_locked) begin reg_next_state = STATE_MGMT_RESET_DEASSERT; end else begin reg_next_state = STATE_RESET; end end STATE_MGMT_RESET_DEASSERT : begin if (reset_timer_w == 2'b11) begin reg_next_state = STATE_MC_TRANSFER_REQ; end else begin reg_next_state = STATE_MGMT_RESET_DEASSERT; end end STATE_MC_TRANSFER_REQ : begin reg_cfg_mc_update_request_o = 1'b1; if (cfg_mc_update_done_i) begin reg_next_state = STATE_INPUT_UPDATE_REQ; end else begin reg_next_state = STATE_MC_TRANSFER_REQ; end end STATE_INPUT_UPDATE_REQ : begin reg_cfg_input_update_request_o = 1'b1; if (cfg_input_update_done_i) begin reg_next_state = STATE_PHY_RDY; end else begin reg_next_state = STATE_INPUT_UPDATE_REQ; end end STATE_PHY_RDY : begin // Check warm reset flag if (!cold_reset) begin reg_pipe_reset_n_o = 1'b1; end if (phy_rdy) begin reg_next_state = STATE_RESET_DEASSERT; end else begin reg_next_state = STATE_PHY_RDY; end end STATE_RESET_DEASSERT : begin reg_reset_n_o = 1'b1; reg_pipe_reset_n_o = 1'b1; if (!phy_rdy) begin reg_next_state = STATE_PHY_RDY; end else if (user_cfg_input_update_i) begin reg_next_state = STATE_INPUT_UPDATE_REQ_REDO; end else begin reg_next_state = STATE_RESET_DEASSERT; end end STATE_INPUT_UPDATE_REQ_REDO : begin reg_reset_n_o = 1'b1; reg_pipe_reset_n_o = 1'b1; reg_cfg_input_update_request_o = 1'b1; if (cfg_input_update_done_i) begin reg_next_state = STATE_RESET_DEASSERT; end else begin reg_next_state = STATE_INPUT_UPDATE_REQ_REDO; end end endcase end //always end // else // DUT is a Downstream port end // generate resets endgenerate // Register signals always @(posedge clk_i) begin regff_mgmt_reset_n_o <= reg_mgmt_reset_n_o; regff_mgmt_sticky_reset_n_o <= reg_mgmt_sticky_reset_n_o; regff_pipe_reset_n_o <= reg_pipe_reset_n_o; regff_reset_n_o <= reg_reset_n_o; end // Assigns assign state_w = reg_state; assign next_state_w = reg_next_state; //assign reset_n_o = reg_reset_n_o; //assign pipe_reset_n_o = reg_pipe_reset_n_o; //assign mgmt_reset_n_o = reg_mgmt_reset_n_o; //assign mgmt_sticky_reset_n_o = reg_mgmt_sticky_reset_n_o; assign reset_n_o = regff_reset_n_o; assign pipe_reset_n_o = regff_pipe_reset_n_o; assign mgmt_reset_n_o = regff_mgmt_reset_n_o; assign mgmt_sticky_reset_n_o = regff_mgmt_sticky_reset_n_o; assign cfg_input_update_request_o = reg_cfg_input_update_request_o; assign cfg_mc_update_request_o = reg_cfg_mc_update_request_o; assign cold_reset = reg_cold_reset; assign state_o = reg_state; assign reset_timer_w = reg_reset_timer; endmodule
module Combiner( input clk, input signed [15:0] din, //input mode, input integ, input bypass, //input [9:0] gateEnd, //(* equivalent_register_removal = "no" *) output reg signed [15:0] dout = 16'h0000 output signed [15:0] dout ); `include "bits_to_fit.v" //parameter real CLK_FREQ = 192e6; // SiS digitisers - 192 MHz parameter real CLK_FREQ = 357e6; // FONT5A board - 357 MHz parameter real SUB_PULSE_LENGTH = 280e-9; // Factor 4 - 280 ns sub-pulse length //localparam integer COMB_FACT = 4; // Factor 4 combination localparam integer SUB_PULSE_CNT_SIZE = bits_to_fit(CLK_FREQ * SUB_PULSE_LENGTH); //localparam SUB_PULSE_CNT_SIZE = $clog2(CLK_FREQ * SUB_PULSE_LENGTH + 1); //NB: Icarus verilog understand the clog2 system CUF but not user functions!!! //localparam [SUB_PULSE_CNT_SIZE-1:0] SUB_PULSE_CNT = CLK_FREQ * SUB_PULSE_LENGTH; //reg [SUB_PULSE_CNT_SIZE-1:0] subPulseCtr = {SUB_PULSE_CNT_SIZE{1'b0}}; //parameter SRL_SIZE = 64; localparam [SUB_PULSE_CNT_SIZE-1:0] SRL_SIZE = (CLK_FREQ * SUB_PULSE_LENGTH); reg signed [17:0] dsh [0:SRL_SIZE-1]; // 18-bits necessary for Factor 4 combination // integer i, n; initial for (i=0; i < SRL_SIZE; i=i+1) dsh[i] = 18'h00000; //MUXY for uncombined beam wire signed [17:0] din_mux = (bypass) ? {din, 2'b00} : {{2{din[15]}}, din} + dsh[SRL_SIZE-1]; always @(posedge clk) begin /* if (intergrating) begin //ACC/CLR !! dsh[0] <= din + dsh[SRL_SIZE-1]; for (n=SRL_SIZE-1; n > 0; n=n-1) dsh[n] <= dsh[n-1]; end else begin for (n=SRL_SIZE-1; n > 0; n=n-1) dsh[n] <= 20'h0; // not synthesisible, must shift-in the zero dout <= dsh[SRL_SIZE-1]; */ //Begin combiner unit /* dout <= (bypass) ? din : dsh[SRL_SIZE-1]; dsh[0] <= (integ) ? din + dsh[SRL_SIZE-1] : 20'h0; //control (integ) must be set to correct sample range for (n=SRL_SIZE-1; n > 0; n=n-1) dsh[n] <= dsh[n-1]; */ //End combiner //NO THIS iS WRONG, output needs to be din + dsh //dout <= (bypass) ? din : din + dsh[SRL_SIZE-1]; dsh[0] <= (integ) ? din_mux : 18'h00000; // MUXY to clear SR when not interleaving //dsh[0] <= (bypass) ? {din, 2'b00} : {{2{din[15]}}, din} + dsh[SRL_SIZE-1]; //MUXY for uncombined beam for (n=SRL_SIZE-1; n > 0; n=n-1) dsh[n] <= dsh[n-1]; // Implement Shift Rgegister //dout <= dsh[0][17:2]; // Bit-select top 16 bits and present on output end assign dout = dsh[1][17:2]; endmodule
module router_op_lut_regs_cntr #( parameter UDP_REG_SRC_WIDTH = 2 ) ( input reg_req_in, input reg_ack_in, input reg_rd_wr_L_in, input [`UDP_REG_ADDR_WIDTH-1:0] reg_addr_in, input [`CPCI_NF2_DATA_WIDTH-1:0] reg_data_in, input [UDP_REG_SRC_WIDTH-1:0] reg_src_in, output reg_req_out, output reg_ack_out, output reg_rd_wr_L_out, output [`UDP_REG_ADDR_WIDTH-1:0] reg_addr_out, output [`CPCI_NF2_DATA_WIDTH-1:0] reg_data_out, output [UDP_REG_SRC_WIDTH-1:0] reg_src_out, // --- interface to op_lut_process_sm input pkt_sent_from_cpu, // pulsed: we've sent a pkt from the CPU input pkt_sent_to_cpu_options_ver, // pulsed: we've sent a pkt to the CPU coz it has options/bad version input pkt_sent_to_cpu_bad_ttl, // pulsed: sent a pkt to the CPU coz the TTL is 1 or 0 input pkt_sent_to_cpu_dest_ip_hit, // pulsed: sent a pkt to the CPU coz it has hit in the destination ip filter list input pkt_forwarded, // pulsed: forwarded pkt to the destination port input pkt_dropped_checksum, // pulsed: dropped pkt coz bad checksum input pkt_sent_to_cpu_non_ip, // pulsed: sent pkt to cpu coz it's not IP input pkt_sent_to_cpu_arp_miss, // pulsed: sent pkt to cpu coz we didn't find arp entry for next hop ip input pkt_sent_to_cpu_lpm_miss, // pulsed: sent pkt to cpu coz we didn't find lpm entry for destination ip input pkt_dropped_wrong_dst_mac, // pulsed: dropped pkt not destined to us input clk, input reset ); // ------------- Internal parameters -------------- localparam NUM_REGS_USED = 10; // ------------- Wires/reg ------------------ wire [NUM_REGS_USED-1:0] updates; // -------------- Logic -------------------- generic_cntr_regs #( .UDP_REG_SRC_WIDTH (UDP_REG_SRC_WIDTH), .TAG (`ROUTER_OP_LUT_BLOCK_ADDR), // Tag to match against .REG_ADDR_WIDTH (`ROUTER_OP_LUT_REG_ADDR_WIDTH),// Width of block addresses .NUM_REGS_USED (NUM_REGS_USED), // How many registers .INPUT_WIDTH (1), // Width of each update request .MIN_UPDATE_INTERVAL (8), // Clocks between successive inputs .REG_WIDTH (`CPCI_NF2_DATA_WIDTH), // How wide should each counter be? .RESET_ON_READ (0) ) generic_cntr_regs ( .reg_req_in (reg_req_in), .reg_ack_in (reg_ack_in), .reg_rd_wr_L_in (reg_rd_wr_L_in), .reg_addr_in (reg_addr_in), .reg_data_in (reg_data_in), .reg_src_in (reg_src_in), .reg_req_out (reg_req_out), .reg_ack_out (reg_ack_out), .reg_rd_wr_L_out (reg_rd_wr_L_out), .reg_addr_out (reg_addr_out), .reg_data_out (reg_data_out), .reg_src_out (reg_src_out), // --- update interface .updates (updates), .decrement ('h0), .clk (clk), .reset (reset) ); assign updates[`ROUTER_OP_LUT_ARP_NUM_MISSES] = pkt_sent_to_cpu_arp_miss; assign updates[`ROUTER_OP_LUT_LPM_NUM_MISSES] = pkt_sent_to_cpu_lpm_miss; assign updates[`ROUTER_OP_LUT_NUM_CPU_PKTS_SENT] = pkt_sent_from_cpu; assign updates[`ROUTER_OP_LUT_NUM_BAD_OPTS_VER] = pkt_sent_to_cpu_options_ver; assign updates[`ROUTER_OP_LUT_NUM_BAD_CHKSUMS] = pkt_dropped_checksum; assign updates[`ROUTER_OP_LUT_NUM_BAD_TTLS] = pkt_sent_to_cpu_bad_ttl; assign updates[`ROUTER_OP_LUT_NUM_NON_IP_RCVD] = pkt_sent_to_cpu_non_ip; assign updates[`ROUTER_OP_LUT_NUM_PKTS_FORWARDED] = pkt_forwarded; assign updates[`ROUTER_OP_LUT_NUM_WRONG_DEST] = pkt_dropped_wrong_dst_mac; assign updates[`ROUTER_OP_LUT_NUM_FILTERED_PKTS] = pkt_sent_to_cpu_dest_ip_hit; endmodule