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module altera_tse_lvds_reset_sequencer (
clk,
reset,
rx_locked,
rx_channel_data_align,
pll_areset,
rx_reset,
rx_cda_reset
);
input clk;
input reset;
input rx_locked;
output rx_channel_data_align;
output pll_areset;
output rx_reset;
output rx_cda_reset;
reg rx_channel_data_align;
reg pll_areset;
reg rx_reset;
reg rx_cda_reset;
wire rx_locked_sync;
reg rx_locked_sync_d1;
reg rx_locked_sync_d2;
reg rx_locked_sync_d3;
reg rx_locked_stable;
reg [2:0] pulse_count;
reg [2:0] state;
reg [2:0] nextstate;
// State Definitions
parameter [2:0] stm_idle = 3'b000; //0
parameter [2:0] stm_pll_areset = 3'b001; //1
parameter [2:0] stm_rx_reset = 3'b010; //2
parameter [2:0] stm_rx_cda_reset = 3'b011; //3
parameter [2:0] stm_word_alignment = 3'b100; //4
altera_std_synchronizer #(2) rx_locked_altera_std_synchronizer (
.clk ( clk ),
.reset_n ( ~reset ),
.din ( rx_locked ),
.dout ( rx_locked_sync )
);
always @ (posedge clk or posedge reset)
begin
if (reset == 1'b1) begin
rx_locked_sync_d1 <= 1'b0;
rx_locked_sync_d2 <= 1'b0;
rx_locked_sync_d3 <= 1'b0;
end
else begin
rx_locked_sync_d1 <= rx_locked_sync;
rx_locked_sync_d2 <= rx_locked_sync_d1;
rx_locked_sync_d3 <= rx_locked_sync_d2;
end
end
always @ (posedge clk or posedge reset)
begin
if (reset == 1'b1) begin
rx_locked_stable <= 1'b0;
end
else begin
rx_locked_stable <= rx_locked_sync & rx_locked_sync_d1 & rx_locked_sync_d2 & rx_locked_sync_d3;
end
end
// FSM
always @ (posedge clk or posedge reset)
begin
if (reset == 1'b1) begin
state <= stm_pll_areset;
end
else begin
state <= nextstate;
end
end
always @ (*)
begin
case (state)
stm_idle:
if (reset == 1'b1) begin
nextstate = stm_pll_areset;
end
else begin
nextstate = stm_idle;
end
stm_pll_areset:
begin
nextstate = stm_rx_reset;
end
stm_rx_reset:
if (rx_locked_stable == 1'b0) begin
nextstate = stm_rx_reset;
end
else begin
nextstate = stm_rx_cda_reset;
end
stm_rx_cda_reset:
begin
nextstate = stm_word_alignment;
end
stm_word_alignment:
if (pulse_count == 4) begin
nextstate = stm_idle;
end
else begin
nextstate = stm_word_alignment;
end
default:
begin
nextstate = stm_idle;
end
endcase
end
always @ (posedge clk or posedge reset)
begin
if (reset == 1'b1) begin
pll_areset <= 1'b1;
rx_reset <= 1'b1;
rx_cda_reset <= 1'b0;
rx_channel_data_align <= 1'b0;
pulse_count <= 3'b000;
end
else begin
case (nextstate)
stm_idle:
begin
pll_areset <= 1'b0;
rx_reset <= 1'b0;
rx_cda_reset <= 1'b0;
rx_channel_data_align <= 1'b0;
pulse_count <= 3'b000;
end
stm_pll_areset:
begin
pll_areset <= 1'b1;
rx_reset <= 1'b1;
rx_cda_reset <= 1'b0;
rx_channel_data_align <= 1'b0;
pulse_count <= 3'b000;
end
stm_rx_reset:
begin
pll_areset <= 1'b0;
rx_cda_reset <= 1'b0;
rx_channel_data_align <= 1'b0;
pulse_count <= 3'b000;
end
stm_rx_cda_reset:
begin
pll_areset <= 1'b0;
rx_reset <= 1'b0;
rx_cda_reset <= 1'b1;
rx_channel_data_align <= 1'b0;
pulse_count <= 3'b000;
end
stm_word_alignment:
begin
pll_areset <= 1'b0;
rx_reset <= 1'b0;
rx_cda_reset <= 1'b0;
rx_channel_data_align <= ~rx_channel_data_align;
pulse_count <= pulse_count +1'b1;
end
default:
begin
pll_areset <= 1'b0;
rx_reset <= 1'b0;
rx_cda_reset <= 1'b0;
rx_channel_data_align <= 1'b0;
pulse_count <= 3'b000;
end
endcase
end
end
endmodule |
module bin_to_gray7 (
input wire [7:0] gray_input,
output reg [7:0] bin_out
);
always@(*) begin
bin_out[7] <= gray_input[7];
bin_out[6] <= bin_out[7] ^ gray_input[6];
bin_out[5] <= bin_out[6] ^ gray_input[5];
bin_out[4] <= bin_out[5] ^ gray_input[4];
bin_out[3] <= bin_out[4] ^ gray_input[3];
bin_out[2] <= bin_out[3] ^ gray_input[2];
bin_out[1] <= bin_out[2] ^ gray_input[1];
bin_out[0] <= bin_out[1] ^ gray_input[0];
end
endmodule |
module mono_data_rx_core
#(
parameter ABUSWIDTH = 16,
parameter IDENTYFIER = 2'b00
)(
input wire CLK_BX,
input wire RX_TOKEN, RX_DATA, RX_CLK,
output reg RX_READ, RX_FREEZE,
output wire READY,
input wire [63:0] TIMESTAMP,
input wire FIFO_READ,
output wire FIFO_EMPTY,
output wire [31:0] FIFO_DATA,
input wire BUS_CLK,
input wire [ABUSWIDTH-1:0] BUS_ADD,
input wire [7:0] BUS_DATA_IN,
output reg [7:0] BUS_DATA_OUT,
input wire BUS_RST,
input wire BUS_WR,
input wire BUS_RD,
output wire LOST_ERROR
);
localparam VERSION = 2;
wire SOFT_RST;
assign SOFT_RST = (BUS_ADD==0 && BUS_WR);
wire RST;
assign RST = BUS_RST | SOFT_RST;
reg CONF_EN;
reg CONF_DISSABLE_GRAY_DEC;
reg [7:0] CONF_START_FREEZE;
reg [7:0] CONF_STOP_FREEZE;
reg [7:0] CONF_START_READ;
reg [7:0] CONF_STOP_READ;
reg [7:0] CONF_STOP;
reg [7:0] CONF_READ_SHIFT;
always @(posedge BUS_CLK) begin
if(RST) begin
CONF_EN <= 0;
CONF_DISSABLE_GRAY_DEC <= 0;
CONF_START_FREEZE <= 3;
CONF_START_READ <= 6;
CONF_STOP_READ <= 7;
CONF_STOP_FREEZE <= 15;
CONF_STOP <= 45;
CONF_READ_SHIFT <=59; // (29<<2+1)
end
else if(BUS_WR) begin
if(BUS_ADD == 2) begin
CONF_EN <= BUS_DATA_IN[0];
CONF_DISSABLE_GRAY_DEC <= BUS_DATA_IN[1];
end
else if(BUS_ADD == 4)
CONF_START_FREEZE <= BUS_DATA_IN;
else if(BUS_ADD == 5)
CONF_STOP_FREEZE <= BUS_DATA_IN;
else if(BUS_ADD == 6)
CONF_START_READ <= BUS_DATA_IN;
else if(BUS_ADD == 7)
CONF_STOP_READ <= BUS_DATA_IN;
else if(BUS_ADD == 8)
CONF_STOP <= BUS_DATA_IN;
else if(BUS_ADD == 9)
CONF_READ_SHIFT <= BUS_DATA_IN;
end
end
reg [7:0] LOST_DATA_CNT;
reg[51:0] token_timestamp;
reg[27:0] token_cnt;
always @(posedge BUS_CLK) begin
if(BUS_RD) begin
if(BUS_ADD == 0)
BUS_DATA_OUT <= VERSION;
else if(BUS_ADD == 2)
BUS_DATA_OUT <= {6'b0, CONF_DISSABLE_GRAY_DEC, CONF_EN};
else if(BUS_ADD == 3)
BUS_DATA_OUT <= LOST_DATA_CNT;
else if(BUS_ADD == 4)
BUS_DATA_OUT <= CONF_START_FREEZE;
else if(BUS_ADD == 5)
BUS_DATA_OUT <= CONF_STOP_FREEZE;
else if(BUS_ADD == 6)
BUS_DATA_OUT <= CONF_START_READ;
else if(BUS_ADD == 7)
BUS_DATA_OUT <= CONF_STOP_READ;
else if(BUS_ADD == 8)
BUS_DATA_OUT <= CONF_STOP;
else if(BUS_ADD == 9)
BUS_DATA_OUT <= CONF_READ_SHIFT[7:0];
else if(BUS_ADD == 17)
BUS_DATA_OUT <= {7'b0,READY};
else if (BUS_ADD ==18) ///debug
BUS_DATA_OUT <= TIMESTAMP[8:0];
else
BUS_DATA_OUT <= 8'b0;
end
end
wire RST_SYNC;
wire RST_SOFT_SYNC;
cdc_reset_sync rst_pulse_sync (.clk_in(BUS_CLK), .pulse_in(RST), .clk_out(RX_CLK), .pulse_out(RST_SOFT_SYNC));
assign RST_SYNC = RST_SOFT_SYNC;
wire CONF_EN_SYNC;
assign CONF_EN_SYNC = CONF_EN;
assign READY = ~RX_FREEZE & CONF_EN;
reg [3:0] TOKEN_FF;
always@(posedge RX_CLK)
if (RST_SYNC)
TOKEN_FF <= 4'b0;
else
TOKEN_FF <= {TOKEN_FF[2:0],RX_TOKEN};
wire TOKEN_SYNC;
assign TOKEN_SYNC = ~TOKEN_FF[1] & TOKEN_FF[0];
reg TOKEN_NEXT;
always@(posedge RX_CLK)
if (RST_SYNC) begin
token_timestamp <= 52'b0;
token_cnt <= 28'b0;
end
else if ( TOKEN_SYNC ) begin
token_timestamp <= TIMESTAMP[51:0];
token_cnt <= token_cnt+1;
end
parameter NOP=5'd0, WAIT_ONE = 5'd1, NOP_NEXT=5'd2, WAIT_NEXT = 5'd3, WAIT_TWO = 5'd4, WAIT_TWO_NEXT = 5'd5;
reg [4:0] state, next_state;
always@(posedge CLK_BX)
if(RST_SYNC)
state <= NOP;
else
state <= next_state;
reg [7:0] DelayCnt;
always@(*) begin : set_next_state
next_state = state; //default
case (state)
NOP:
if(TOKEN_FF[0] & CONF_EN)
next_state = WAIT_ONE;
WAIT_ONE:
if ( (DelayCnt == CONF_STOP_FREEZE - 2 ) & TOKEN_FF[0])
next_state = WAIT_TWO;
else if (DelayCnt == CONF_STOP) begin
if(!RX_FREEZE & TOKEN_FF[0])
next_state = NOP_NEXT;
else
next_state = NOP;
end
WAIT_TWO:
next_state =WAIT_ONE;
NOP_NEXT:
if(TOKEN_FF[0] & CONF_EN)
next_state = WAIT_NEXT;
WAIT_NEXT:
if ( (DelayCnt == CONF_STOP_FREEZE - 2 ) & TOKEN_FF[0])
next_state = WAIT_TWO_NEXT;
else if(DelayCnt == CONF_STOP) begin
if(TOKEN_FF[0])
next_state = NOP_NEXT;
else
next_state = NOP;
end
WAIT_TWO_NEXT:
next_state =WAIT_NEXT;
endcase
end
always@(posedge CLK_BX)
if(RST_SYNC || state == NOP || state == NOP_NEXT)
DelayCnt <= 0;
else if (state == WAIT_TWO || state == WAIT_TWO_NEXT )
DelayCnt <= CONF_START_READ - 2;
else if(DelayCnt != 8'hff)
DelayCnt <= DelayCnt + 1;
always@(posedge CLK_BX)
if(RST_SYNC)
TOKEN_NEXT <= 1'b0;
else if(DelayCnt == CONF_STOP_READ + 4) //should be +1
TOKEN_NEXT <= TOKEN_FF[0];
always@(posedge CLK_BX)
//always@(negedge CLK_BX)
RX_READ <= (DelayCnt >= CONF_START_READ && DelayCnt < CONF_STOP_READ);
always@(posedge CLK_BX) begin
if(RST_SYNC)
RX_FREEZE <= 1'b0;
else if(DelayCnt == CONF_START_FREEZE)
RX_FREEZE <= 1'b1;
else if(DelayCnt == CONF_STOP_FREEZE && !TOKEN_FF[0])
RX_FREEZE <= 1'b0;
end
reg [1:0] read_dly;
always@(posedge CLK_BX)
read_dly[1:0] <= {read_dly[0], RX_READ};
reg [1:0] read_out_dly;
always@(posedge RX_CLK)
read_out_dly <= {read_out_dly[0], read_dly[1]};
reg load;
always@(posedge RX_CLK)
load <= read_out_dly[0] & !read_out_dly[1];
reg [6:0] cnt;
always@(posedge RX_CLK)
if(RST_SYNC)
cnt <= -1;
else if(load)
cnt <= 0;
else if(cnt != 7'hff)
cnt <= cnt + 1;
reg [29:0] ser_neg;
always@(negedge RX_CLK)
ser_neg <= {ser_neg[28:0], RX_DATA};
reg [29:0] ser;
always@(posedge RX_CLK)
ser <= {ser[28:0], RX_DATA};
wire store_data;
assign store_data = (cnt == CONF_READ_SHIFT[7:1]);
reg [29:0] data_out;
wire [110:0] data_to_cdc; // [82:0] data_to_cdc;
always@(posedge RX_CLK) begin
if(RST_SYNC)
data_out <= 0;
else if(store_data) begin
if (CONF_READ_SHIFT[0]==1)
data_out <= ser_neg;
else
data_out <= ser;
end
end
reg data_out_strobe;
always@(posedge RX_CLK) begin
if(store_data)
data_out_strobe <= 1;
else
data_out_strobe <= 0;
end
//
wire cdc_fifo_write;
assign cdc_fifo_write = data_out_strobe;
wire wfull;
always@(posedge RX_CLK) begin
if(RST_SYNC)
LOST_DATA_CNT <= 0;
else if (wfull && cdc_fifo_write && LOST_DATA_CNT != -1)
LOST_DATA_CNT <= LOST_DATA_CNT +1;
end
wire posssible_noise;
assign posssible_noise = (state == WAIT_NEXT || state == WAIT_TWO_NEXT);
wire [5:0] col;
wire [7:0] row, te_gray, le_gray, te, le;
assign {le_gray, te_gray, row, col} = data_out;
bin_to_gray7 bin_to_gray_te(.gray_input(te_gray), .bin_out(te) );
bin_to_gray7 bin_to_gray_le(.gray_input(le_gray), .bin_out(le) );
assign data_to_cdc = CONF_DISSABLE_GRAY_DEC ? {token_cnt,token_timestamp,posssible_noise, data_out} : {token_cnt,token_timestamp,posssible_noise, le, te, row, col};
wire [110:0] cdc_data_out; //[82:0] cdc_data_out;
wire cdc_fifo_empty, fifo_full, fifo_write;
wire cdc_fifo_read;
//cdc_syncfifo #(.DSIZE(83), .ASIZE(8)) cdc_syncfifo_i
cdc_syncfifo #(.DSIZE(111), .ASIZE(8)) cdc_syncfifo_i
(
.rdata(cdc_data_out),
.wfull(wfull),
.rempty(cdc_fifo_empty),
.wdata(data_to_cdc),
.winc(cdc_fifo_write), .wclk(RX_CLK), .wrst(RST_SYNC),
.rinc(cdc_fifo_read), .rclk(BUS_CLK), .rrst(RST)
);
reg [2:0] byte2_cnt, byte2_cnt_prev;
always@(posedge BUS_CLK)
byte2_cnt_prev <= byte2_cnt;
assign cdc_fifo_read = (byte2_cnt_prev==0 & byte2_cnt!=0);
assign fifo_write = byte2_cnt_prev != 0;
always@(posedge BUS_CLK)
if(RST)
byte2_cnt <= 0;
else if(!cdc_fifo_empty && !fifo_full && byte2_cnt == 0 )
//byte2_cnt <= 3;
byte2_cnt <= 4;
else if (!fifo_full & byte2_cnt != 0)
byte2_cnt <= byte2_cnt - 1;
//reg [82:0] data_buf;
reg [110:0] data_buf;
always@(posedge BUS_CLK)
if(cdc_fifo_read)
data_buf <= cdc_data_out;
wire [29:0] fifo_write_data_byte [4:0];
assign fifo_write_data_byte[4]=29'b0;
assign fifo_write_data_byte[3]={2'b01,data_buf[42:31],data_buf[13:6],1'b0,data_buf[30],data_buf[5:0]};
assign fifo_write_data_byte[2]={2'b10,data_buf[54:43],data_buf[29:22],data_buf[21:14]};
assign fifo_write_data_byte[1]={2'b11,data_buf[82:55]};
assign fifo_write_data_byte[0]={2'b00,data_buf[110:83]}; //last data is dummy
wire [31:0] fifo_data_in;
assign fifo_data_in = fifo_write_data_byte[byte2_cnt];
gerneric_fifo #(.DATA_SIZE(30), .DEPTH(1023)) fifo_i
( .clk(BUS_CLK), .reset(RST),
.write(fifo_write),
.read(FIFO_READ),
.data_in(fifo_data_in),
.full(fifo_full),
.empty(FIFO_EMPTY),
.data_out(FIFO_DATA[29:0]), .size()
);
assign FIFO_DATA[31:30] = IDENTYFIER;
assign LOST_ERROR = LOST_DATA_CNT != 0;
endmodule |
module sky130_fd_sc_ms__sdfrtp (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{control|Control Signals}}
input RESET_B,
//# {{scanchain|Scan Chain}}
input SCD ,
input SCE ,
//# {{clocks|Clocking}}
input CLK ,
//# {{power|Power}}
input VPB ,
input VPWR ,
input VGND ,
input VNB
);
endmodule |
module alt_mem_ddrx_odt_gen
#( parameter
CFG_DWIDTH_RATIO = 2,
CFG_ODT_ENABLED = 1,
CFG_MEM_IF_CHIP = 2, //one_hot
CFG_MEM_IF_ODT_WIDTH = 2,
CFG_PORT_WIDTH_OUTPUT_REGD = 1,
CFG_PORT_WIDTH_CAS_WR_LAT = 4,
CFG_PORT_WIDTH_TCL = 4,
CFG_PORT_WIDTH_ADD_LAT = 3,
CFG_PORT_WIDTH_TYPE = 3,
CFG_PORT_WIDTH_WRITE_ODT_CHIP = 4,
CFG_PORT_WIDTH_READ_ODT_CHIP = 4
)
(
ctl_clk,
ctl_reset_n,
//Configuration Interface
cfg_type,
cfg_tcl,
cfg_cas_wr_lat,
cfg_add_lat,
cfg_write_odt_chip,
cfg_read_odt_chip,
cfg_burst_length,
cfg_output_regd,
//Arbiter Interface
bg_do_read,
bg_do_write,
bg_do_burst_chop,
bg_to_chip, //one_hot
//AFI Interface
afi_odt
);
//=================================================================================================//
// input/output declaration //
//=================================================================================================//
input ctl_clk;
input ctl_reset_n;
//Input from Configuration Interface
input [CFG_PORT_WIDTH_TYPE -1:0] cfg_type;
input [CFG_PORT_WIDTH_TCL -1:0] cfg_tcl;
input [CFG_PORT_WIDTH_CAS_WR_LAT -1:0] cfg_cas_wr_lat;
input [CFG_PORT_WIDTH_ADD_LAT -1:0] cfg_add_lat;
input [CFG_PORT_WIDTH_WRITE_ODT_CHIP -1:0] cfg_write_odt_chip;
input [CFG_PORT_WIDTH_READ_ODT_CHIP -1:0] cfg_read_odt_chip;
input [4:0] cfg_burst_length;
input [CFG_PORT_WIDTH_OUTPUT_REGD -1:0] cfg_output_regd;
//Inputs from Arbiter Interface
input bg_do_read;
input bg_do_write;
input bg_do_burst_chop;
input [CFG_MEM_IF_CHIP -1:0] bg_to_chip;
//Output to AFI Interface
output [(CFG_MEM_IF_ODT_WIDTH*(CFG_DWIDTH_RATIO/2))-1:0] afi_odt;
//=================================================================================================//
// reg/wire declaration //
//=================================================================================================//
wire [CFG_MEM_IF_ODT_WIDTH-1:0] write_odt_chip [CFG_MEM_IF_CHIP-1:0];
wire [CFG_MEM_IF_ODT_WIDTH-1:0] read_odt_chip [CFG_MEM_IF_CHIP-1:0];
wire [CFG_MEM_IF_ODT_WIDTH-1:0] ddr2_odt_l;
wire [CFG_MEM_IF_ODT_WIDTH-1:0] ddr2_odt_h;
wire [CFG_MEM_IF_ODT_WIDTH-1:0] ddr3_odt_l;
wire [CFG_MEM_IF_ODT_WIDTH-1:0] ddr3_odt_h;
wire [CFG_MEM_IF_ODT_WIDTH-1:0] ddr3_odt_i;
reg [CFG_MEM_IF_ODT_WIDTH-1:0] int_odt_l;
reg [CFG_MEM_IF_ODT_WIDTH-1:0] int_odt_h;
reg [CFG_MEM_IF_ODT_WIDTH-1:0] int_odt_i;
reg [CFG_MEM_IF_ODT_WIDTH-1:0] int_write_odt_chip;
reg [CFG_MEM_IF_ODT_WIDTH-1:0] int_read_odt_chip;
integer i;
//=================================================================================================//
// cfg_write_odt_chip & cfg_read_odt_chip definition //
//=================================================================================================//
/*
DDR3
four chip selects odt scheme, for two ranks per dimm configuration
.---------------------------------------++---------------------------------------.
| write to || odt to |
+---------+---------+---------+---------++---------+---------+---------+---------+
| chip 0 | chip 1 | chip 2 | chip 3 || chip 0 | chip 1 | chip 2 | chip 3 |
|=--------+---------+---------+---------++---------+---------+---------+--------=|
| 1 | | | || 1 | | 1 | | //cfg_write_odt_chip[0] = 4'b0101; //chip[3] -> chip[0]
+---------+---------+---------+---------++---------+---------+---------+---------+
| | 1 | | || | 1 | | 1 | //cfg_write_odt_chip[1] = 4'b1010; //chip[3] -> chip[0]
+---------+---------+---------+---------++---------+---------+---------+---------+
| | | 1 | || 1 | | 1 | | //cfg_write_odt_chip[2] = 4'b0101; //chip[3] -> chip[0]
+---------+---------+---------+---------++---------+---------+---------+---------+
| | | | 1 || | 1 | | 1 | //cfg_write_odt_chip[3] = 4'b1010; //chip[3] -> chip[0]
'---------+---------+---------+---------++---------+---------+---------+---------'
.---------------------------------------++---------------------------------------.
| read to || odt to |
+---------+---------+---------+---------++---------+---------+---------+---------+
| chip 0 | chip 1 | chip 2 | chip 3 || chip 0 | chip 1 | chip 2 | chip 3 |
|=--------+---------+---------+---------++---------+---------+---------+--------=|
| 1 | | | || | | 1 | | //cfg_read_odt_chip[0] = 4'b0100; //chip[3] -> chip[0]
+---------+---------+---------+---------++---------+---------+---------+---------+
| | 1 | | || | | | 1 | //cfg_read_odt_chip[1] = 4'b1000; //chip[3] -> chip[0]
+---------+---------+---------+---------++---------+---------+---------+---------+
| | | 1 | || 1 | | | | //cfg_read_odt_chip[2] = 4'b0001; //chip[3] -> chip[0]
+---------+---------+---------+---------++---------+---------+---------+---------+
| | | | 1 || | 1 | | | //cfg_read_odt_chip[3] = 4'b0010; //chip[3] -> chip[0]
'---------+---------+---------+---------++---------+---------+---------+---------'
*/
/*
DDR2
four or more chip selects odt scheme, assumes two ranks per dimm
.---------------------------------------++---------------------------------------.
| write/read to || odt to |
+---------+---------+---------+---------++---------+---------+---------+---------+
| chipJ+0 | chipJ+1 | chipJ+2 | chipJ+3 || chipJ+0 | chipJ+1 | chipJ+2 | chipJ+3 |
|=--------+---------+---------+---------++---------+---------+---------+--------=|
| 1 | | | || | | 1 | |
+---------+---------+---------+---------++---------+---------+---------+---------+
| | 1 | | || | | | 1 |
+---------+---------+---------+---------++---------+---------+---------+---------+
| | | 1 | || 1 | | | |
+---------+---------+---------+---------++---------+---------+---------+---------+
| | | | 1 || | 1 | | |
'---------+---------+---------+---------++---------+---------+---------+---------'
*/
//Unpack read/write_odt_chip array into per chip array
generate
genvar a;
begin : unpack_odt_config
for (a=0; a<CFG_MEM_IF_CHIP; a=a+1)
begin : unpack_odt_config_per_chip
assign write_odt_chip[a] = cfg_write_odt_chip [(a*CFG_MEM_IF_ODT_WIDTH)+CFG_MEM_IF_ODT_WIDTH-1:a*CFG_MEM_IF_ODT_WIDTH];
assign read_odt_chip[a] = cfg_read_odt_chip [(a*CFG_MEM_IF_ODT_WIDTH)+CFG_MEM_IF_ODT_WIDTH-1:a*CFG_MEM_IF_ODT_WIDTH];
end
end
endgenerate
always @(*)
begin
int_write_odt_chip = {(CFG_MEM_IF_ODT_WIDTH){1'b0}};
int_read_odt_chip = {(CFG_MEM_IF_ODT_WIDTH){1'b0}};
for (i=0; i<CFG_MEM_IF_CHIP; i=i+1)
begin
if (bg_to_chip[i])
begin
int_write_odt_chip = write_odt_chip[i];
int_read_odt_chip = read_odt_chip[i];
end
end
end
//=================================================================================================//
// Instantiate DDR2 ODT generation Block //
//=================================================================================================//
generate
genvar b;
for (b=0; b<CFG_MEM_IF_ODT_WIDTH; b=b+1)
begin : ddr2_odt_gen
alt_mem_ddrx_ddr2_odt_gen
# (
.CFG_DWIDTH_RATIO (CFG_DWIDTH_RATIO),
.CFG_PORT_WIDTH_ADD_LAT (CFG_PORT_WIDTH_ADD_LAT),
.CFG_PORT_WIDTH_OUTPUT_REGD (CFG_PORT_WIDTH_OUTPUT_REGD),
.CFG_PORT_WIDTH_TCL (CFG_PORT_WIDTH_TCL)
)
alt_mem_ddrx_ddr2_odt_gen_inst
(
.ctl_clk (ctl_clk),
.ctl_reset_n (ctl_reset_n),
.cfg_tcl (cfg_tcl),
.cfg_add_lat (cfg_add_lat),
.cfg_burst_length (cfg_burst_length),
.cfg_output_regd (cfg_output_regd),
.bg_do_write (bg_do_write & int_write_odt_chip[b]),
.bg_do_read (bg_do_read & int_read_odt_chip[b]),
.int_odt_l (ddr2_odt_l[b]),
.int_odt_h (ddr2_odt_h[b])
);
end
endgenerate
//=================================================================================================//
// Instantiate DDR3 ODT generation Block //
//=================================================================================================//
generate
genvar c;
for (c=0; c<CFG_MEM_IF_ODT_WIDTH; c=c+1)
begin : ddr3_odt_gen
alt_mem_ddrx_ddr3_odt_gen
# (
.CFG_DWIDTH_RATIO (CFG_DWIDTH_RATIO),
.CFG_PORT_WIDTH_OUTPUT_REGD (CFG_PORT_WIDTH_OUTPUT_REGD),
.CFG_PORT_WIDTH_TCL (CFG_PORT_WIDTH_TCL),
.CFG_PORT_WIDTH_CAS_WR_LAT (CFG_PORT_WIDTH_CAS_WR_LAT)
)
alt_mem_ddrx_ddr3_odt_gen_inst
(
.ctl_clk (ctl_clk),
.ctl_reset_n (ctl_reset_n),
.cfg_tcl (cfg_tcl),
.cfg_cas_wr_lat (cfg_cas_wr_lat),
.cfg_output_regd (cfg_output_regd),
.bg_do_write (bg_do_write & int_write_odt_chip[c]),
.bg_do_read (bg_do_read & int_read_odt_chip[c]),
.bg_do_burst_chop (bg_do_burst_chop),
.int_odt_l (ddr3_odt_l[c]),
.int_odt_h (ddr3_odt_h[c]),
.int_odt_i (ddr3_odt_i[c])
);
end
endgenerate
//=================================================================================================//
// ODT Output generation based on memory type and ODT feature turned ON or not //
//=================================================================================================//
always @(*)
begin
if (cfg_type == `MMR_TYPE_DDR2)
begin
int_odt_l = ddr2_odt_l;
int_odt_h = ddr2_odt_h;
int_odt_i = {(CFG_MEM_IF_ODT_WIDTH){1'b0}};
end
else if (cfg_type == `MMR_TYPE_DDR3)
begin
int_odt_l = ddr3_odt_l;
int_odt_h = ddr3_odt_h;
int_odt_i = ddr3_odt_i;
end
else
begin
int_odt_l = {(CFG_MEM_IF_ODT_WIDTH){1'b0}};
int_odt_h = {(CFG_MEM_IF_ODT_WIDTH){1'b0}};
int_odt_i = {(CFG_MEM_IF_ODT_WIDTH){1'b0}};
end
end
generate
if (CFG_ODT_ENABLED == 1)
begin
if (CFG_DWIDTH_RATIO == 2) // quarter rate
assign afi_odt = int_odt_l;
else if (CFG_DWIDTH_RATIO == 4) // half rate
assign afi_odt = {int_odt_h,int_odt_l};
else if (CFG_DWIDTH_RATIO == 8) // quarter rate
assign afi_odt = {int_odt_h,int_odt_i, int_odt_i, int_odt_l};
end
else
assign afi_odt = {(CFG_MEM_IF_ODT_WIDTH * (CFG_DWIDTH_RATIO/2)){1'b0}};
endgenerate
endmodule |
module uart_1wire
(
input c, // clock
input w, // write enable
input [1:0] a, // address
input [31:0] wd, // write data
output reg [31:0] rd = 0, // read data
inout uart // IO pin
);
reg [3:0] rx_state = 0;
reg [6:0] rx_cur_time = 0;
reg [6:0] rx_next_event = 0;
reg [6:0] cpb = 100; // clocks per bit
reg ireg = 1;
reg oe = 0;
reg od = 0;
reg [5:0] tx_bits = 0; // tx bits remaining
reg [6:0] tx_cur_time = 0;
reg [6:0] tx_next_event = 0;
reg [38:0] tx_sr = 39'h7FFFFFFFF;
assign uart = oe ? od : 1'bz;
always @ (posedge c)
begin
// receive
ireg <= uart;
if(rx_state == 0)
begin
rx_cur_time <= 1'b0;
if (!ireg)
begin
rx_state <= 1'b1;
rx_next_event <= cpb[6:1];
end
end
else
begin
rx_cur_time <= rx_cur_time + 1'b1;
if(rx_next_event == rx_cur_time)
begin
rx_next_event <= rx_next_event + cpb;
rx_state <= rx_state == 10 ? 1'b0 : rx_state + 1'b1;
if((rx_state > 1) && (rx_state < 10))
rd <= {ireg, rd[31:1]};
end
end
// transmit
od <= tx_sr[0];
oe <= tx_bits != 0;
if(w)
begin
if((a == 0) && wd[31])
cpb <= wd[6:0];
oe <= 1'b1;
tx_bits <= 6'd40;
tx_cur_time <= 1'b0;
tx_next_event <= cpb;
tx_sr[38:30] <= a > 2 ? {wd[31:24], 1'b0} : 9'h1FF;
tx_sr[29:20] <= a > 1 ? {1'b1, wd[23:16], 1'b0} : 10'h3FF;
tx_sr[19:10] <= a > 0 ? {1'b1, wd[15: 8], 1'b0} : 10'h3FF;
tx_sr[ 9: 0] <= (a > 0) || (wd[31:30] == 0) ? {1'b1, wd[ 7: 0], 1'b0} :
wd[30] == 1 ? 10'h000 : 10'h3FF;
end
else
begin
tx_cur_time <= tx_cur_time + 1'b1;
if(tx_next_event == tx_cur_time)
begin
tx_next_event <= tx_next_event + cpb;
tx_sr <= {1'b1, tx_sr[38:1]};
tx_bits <= tx_bits == 0 ? 1'b0 : tx_bits - 1'b1;
end
end
end
endmodule |
module tb (input c);
reg w = 0;
reg [2:0] a = 0;
reg [31:0] wd = 0;
wand uart = 1;
wire [31:0] rd0, rd1;
uart_1wire uart0 (.c(c), .w(w & ~a[2]), .a(a[1:0]), .wd(wd), .rd(rd0), .uart(uart));
uart_1wire uart1 (.c(c), .w(w & a[2]), .a(a[1:0]), .wd(wd), .rd(rd1), .uart(uart));
initial
begin
$dumpfile("dump.vcd");
$dumpvars(0);
end
endmodule |
module sky130_fd_sc_hs__or3 (
X ,
A ,
B ,
C ,
VPWR,
VGND
);
output X ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
endmodule |
module sky130_fd_sc_lp__bufbuf (
X,
A
);
// Module ports
output X;
input A;
// Local signals
wire buf0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X, A );
buf buf1 (X , buf0_out_X );
endmodule |
module top();
// Inputs are registered
reg A;
reg TE_B;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Z;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
TE_B = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 TE_B = 1'b0;
#60 VGND = 1'b0;
#80 VNB = 1'b0;
#100 VPB = 1'b0;
#120 VPWR = 1'b0;
#140 A = 1'b1;
#160 TE_B = 1'b1;
#180 VGND = 1'b1;
#200 VNB = 1'b1;
#220 VPB = 1'b1;
#240 VPWR = 1'b1;
#260 A = 1'b0;
#280 TE_B = 1'b0;
#300 VGND = 1'b0;
#320 VNB = 1'b0;
#340 VPB = 1'b0;
#360 VPWR = 1'b0;
#380 VPWR = 1'b1;
#400 VPB = 1'b1;
#420 VNB = 1'b1;
#440 VGND = 1'b1;
#460 TE_B = 1'b1;
#480 A = 1'b1;
#500 VPWR = 1'bx;
#520 VPB = 1'bx;
#540 VNB = 1'bx;
#560 VGND = 1'bx;
#580 TE_B = 1'bx;
#600 A = 1'bx;
end
sky130_fd_sc_lp__ebufn dut (.A(A), .TE_B(TE_B), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Z(Z));
endmodule |
module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outreadylatency_check ( .error(1'b1) );
end
endgenerate
soc_system_mm_interconnect_0_avalon_st_adapter_001_error_adapter_0 error_adapter_0 (
.clk (in_clk_0_clk), // clk.clk
.reset_n (~in_rst_0_reset), // reset.reset_n
.in_data (in_0_data), // in.data
.in_valid (in_0_valid), // .valid
.in_ready (in_0_ready), // .ready
.out_data (out_0_data), // out.data
.out_valid (out_0_valid), // .valid
.out_ready (out_0_ready), // .ready
.out_error (out_0_error) // .error
);
endmodule |
module outputs)
wire [1:0] out; // From test of Test.v
// End of automatics
Test test (/*AUTOINST*/
// Outputs
.out (out[1:0]),
// Inputs
.in (in[1:0]));
// Aggregate outputs into a single result vector
wire [63:0] result = {62'h0, out};
// What checksum will we end up with
`define EXPECTED_SUM 64'hbb2d9709592f64bd
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
end
else if (cyc<10) begin
sum <= 64'h0;
end
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule |
module Test (/*AUTOARG*/
// Outputs
out,
// Inputs
in
);
input [1:0] in;
output reg [1:0] out;
always @* begin
// bug99: Internal Error: ../V3Ast.cpp:495: New node already linked?
case (in[1:0])
2'd0, 2'd1, 2'd2, 2'd3: begin
out = in;
end
endcase
end
endmodule |
module ccx_arb_atomq(/*AUTOARG*/
// Outputs
q0_dataout, scan_out,
// Inputs
ctl_qsel1_a_l, ctl_qsel0_a, ctl_shift_a, atom_a, rclk, reset_d1
);
output q0_dataout; // pcx to destination pkt
output scan_out;
input ctl_qsel1_a_l; // queue write sel
input ctl_qsel0_a; // queue write sel
input ctl_shift_a;//grant signal
input atom_a; // spache to pcx data
input rclk;
//input tmb_l;
input reset_d1;
wire q0_datain_pa;
wire q1_datain_pa;
wire q1_dataout;
wire q1_data_out;
wire q0_data_out;
//HEADER SECTION
//DATAPATH SECTION
assign q1_datain_pa = ~ctl_qsel1_a_l ? atom_a : q1_dataout;
dff_s #(1) dff_pcx_atomin_q1(
.din (q1_datain_pa),
.q (q1_data_out),
.clk (rclk),
.se (1'b0),
.si (),
.so ());
assign q1_dataout = ~reset_d1 ? q1_data_out : 1'b0;
assign q0_datain_pa =
ctl_qsel0_a ? atom_a :
ctl_shift_a ? q1_dataout :
q0_dataout;
dff_s #(1) dff_pcx_atomin_q0(
.din (q0_datain_pa),
.q (q0_data_out),
.clk (rclk),
.se (1'b0),
.si (),
.so ());
assign q0_dataout = ~reset_d1 ? q0_data_out : 1'b0;
// Global Variables:
// verilog-library-directories:("." "../../../../../common/rtl" "../rtl")
// End:
// Code start here
//
endmodule |
module altera_tse_pma_lvds_tx (
pll_areset,
tx_in,
tx_inclock,
tx_out);
input pll_areset;
input [9:0] tx_in;
input tx_inclock;
output [0:0] tx_out;
wire [0:0] sub_wire0;
wire [0:0] tx_out = sub_wire0[0:0];
altlvds_tx ALTLVDS_TX_component (
.pll_areset (pll_areset),
.tx_in (tx_in),
.tx_inclock (tx_inclock),
.tx_out (sub_wire0),
.sync_inclock (1'b0),
.tx_coreclock (),
.tx_data_reset (1'b0),
.tx_enable (1'b1),
.tx_locked (),
.tx_outclock (),
.tx_pll_enable (1'b1),
.tx_syncclock (1'b0));
defparam
ALTLVDS_TX_component.center_align_msb = "UNUSED",
ALTLVDS_TX_component.common_rx_tx_pll = "ON",
ALTLVDS_TX_component.coreclock_divide_by = 1,
ALTLVDS_TX_component.data_rate = "1250.0 Mbps",
ALTLVDS_TX_component.deserialization_factor = 10,
ALTLVDS_TX_component.differential_drive = 0,
ALTLVDS_TX_component.implement_in_les = "OFF",
ALTLVDS_TX_component.inclock_boost = 0,
ALTLVDS_TX_component.inclock_data_alignment = "EDGE_ALIGNED",
ALTLVDS_TX_component.inclock_period = 8000,
ALTLVDS_TX_component.inclock_phase_shift = 0,
ALTLVDS_TX_component.intended_device_family = "Stratix III",
ALTLVDS_TX_component.lpm_hint = "UNUSED",
ALTLVDS_TX_component.lpm_type = "altlvds_tx",
ALTLVDS_TX_component.multi_clock = "OFF",
ALTLVDS_TX_component.number_of_channels = 1,
ALTLVDS_TX_component.outclock_alignment = "EDGE_ALIGNED",
ALTLVDS_TX_component.outclock_divide_by = 10,
ALTLVDS_TX_component.outclock_duty_cycle = 50,
ALTLVDS_TX_component.outclock_multiply_by = 1,
ALTLVDS_TX_component.outclock_phase_shift = 0,
ALTLVDS_TX_component.outclock_resource = "AUTO",
ALTLVDS_TX_component.output_data_rate = 1250,
ALTLVDS_TX_component.pll_self_reset_on_loss_lock = "OFF",
ALTLVDS_TX_component.preemphasis_setting = 0,
ALTLVDS_TX_component.refclk_frequency = "125.00 MHz",
ALTLVDS_TX_component.registered_input = "TX_CLKIN",
ALTLVDS_TX_component.use_external_pll = "OFF",
ALTLVDS_TX_component.use_no_phase_shift = "ON",
ALTLVDS_TX_component.vod_setting = 0,
ALTLVDS_TX_component.clk_src_is_pll = "off";
endmodule |
module start_for_Mat2AXIlbW_shiftReg (
clk,
data,
ce,
a,
q);
parameter DATA_WIDTH = 32'd1;
parameter ADDR_WIDTH = 32'd3;
parameter DEPTH = 32'd6;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output [DATA_WIDTH-1:0] q;
reg[DATA_WIDTH-1:0] SRL_SIG [0:DEPTH-1];
integer i;
always @ (posedge clk)
begin
if (ce)
begin
for (i=0;i<DEPTH-1;i=i+1)
SRL_SIG[i+1] <= SRL_SIG[i];
SRL_SIG[0] <= data;
end
end
assign q = SRL_SIG[a];
endmodule |
module start_for_Mat2AXIlbW (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din);
parameter MEM_STYLE = "shiftreg";
parameter DATA_WIDTH = 32'd1;
parameter ADDR_WIDTH = 32'd3;
parameter DEPTH = 32'd6;
input clk;
input reset;
output if_empty_n;
input if_read_ce;
input if_read;
output[DATA_WIDTH - 1:0] if_dout;
output if_full_n;
input if_write_ce;
input if_write;
input[DATA_WIDTH - 1:0] if_din;
wire[ADDR_WIDTH - 1:0] shiftReg_addr ;
wire[DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q;
wire shiftReg_ce;
reg[ADDR_WIDTH:0] mOutPtr = {(ADDR_WIDTH+1){1'b1}};
reg internal_empty_n = 0, internal_full_n = 1;
assign if_empty_n = internal_empty_n;
assign if_full_n = internal_full_n;
assign shiftReg_data = if_din;
assign if_dout = shiftReg_q;
always @ (posedge clk) begin
if (reset == 1'b1)
begin
mOutPtr <= ~{ADDR_WIDTH+1{1'b0}};
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else begin
if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) &&
((if_write & if_write_ce) == 0 | internal_full_n == 0))
begin
mOutPtr <= mOutPtr - 1;
if (mOutPtr == 0)
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) &&
((if_write & if_write_ce) == 1 & internal_full_n == 1))
begin
mOutPtr <= mOutPtr + 1;
internal_empty_n <= 1'b1;
if (mOutPtr == DEPTH - 2)
internal_full_n <= 1'b0;
end
end
end
assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0]:{ADDR_WIDTH{1'b0}};
assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n;
start_for_Mat2AXIlbW_shiftReg
#(
.DATA_WIDTH(DATA_WIDTH),
.ADDR_WIDTH(ADDR_WIDTH),
.DEPTH(DEPTH))
U_start_for_Mat2AXIlbW_ram (
.clk(clk),
.data(shiftReg_data),
.ce(shiftReg_ce),
.a(shiftReg_addr),
.q(shiftReg_q));
endmodule |
module bram_fifo_core
#(
parameter DEPTH = 32'h8000,
parameter FIFO_ALMOST_FULL_THRESHOLD = 95, // in percent
parameter FIFO_ALMOST_EMPTY_THRESHOLD = 5, // in percent
parameter ABUSWIDTH = 32
) (
input wire BUS_CLK,
input wire BUS_RST,
input wire [ABUSWIDTH-1:0] BUS_ADD,
input wire [7:0] BUS_DATA_IN,
input wire BUS_RD,
input wire BUS_WR,
output reg [7:0] BUS_DATA_OUT,
input wire BUS_RD_DATA,
output reg [31:0] BUS_DATA_OUT_DATA,
input wire BUS_WR_DATA,
input wire [31:0] BUS_DATA_IN_DATA,
output wire FIFO_READ_NEXT_OUT,
input wire FIFO_EMPTY_IN,
input wire [31:0] FIFO_DATA,
output wire FIFO_NOT_EMPTY,
output wire FIFO_FULL,
output reg FIFO_NEAR_FULL,
output wire FIFO_READ_ERROR
);
localparam VERSION = 2;
wire SOFT_RST; //0
assign SOFT_RST = (BUS_ADD==0 && BUS_WR);
wire RST;
assign RST = BUS_RST | SOFT_RST;
reg [7:0] status_regs[7:0];
// reg 0 for SOFT_RST
wire [7:0] FIFO_ALMOST_FULL_VALUE;
assign FIFO_ALMOST_FULL_VALUE = status_regs[1];
wire [7:0] FIFO_ALMOST_EMPTY_VALUE;
assign FIFO_ALMOST_EMPTY_VALUE = status_regs[2];
always @(posedge BUS_CLK)
begin
if(RST)
begin
status_regs[0] <= 8'b0;
status_regs[1] <= 255*FIFO_ALMOST_FULL_THRESHOLD/100;
status_regs[2] <= 255*FIFO_ALMOST_EMPTY_THRESHOLD/100;
status_regs[3] <= 8'b0;
status_regs[4] <= 8'b0;
status_regs[5] <= 8'b0;
status_regs[6] <= 8'b0;
status_regs[7] <= 8'b0;
end
else if(BUS_WR && BUS_ADD < 8)
begin
status_regs[BUS_ADD[2:0]] <= BUS_DATA_IN;
end
end
// read reg
wire [31:0] CONF_SIZE_BYTE; // write data count, 1 - 2 - 3, in units of byte
reg [31:0] CONF_SIZE_BYTE_BUF;
reg [7:0] CONF_READ_ERROR; // read error count (read attempts when FIFO is empty), 4
wire [31:0] CONF_SIZE; // in units of int
assign CONF_SIZE_BYTE = CONF_SIZE * 4;
always @ (posedge BUS_CLK) begin
if(BUS_RD) begin
if(BUS_ADD == 0)
BUS_DATA_OUT <= VERSION;
else if(BUS_ADD == 1)
BUS_DATA_OUT <= FIFO_ALMOST_FULL_VALUE;
else if(BUS_ADD == 2)
BUS_DATA_OUT <= FIFO_ALMOST_EMPTY_VALUE;
else if(BUS_ADD == 3)
BUS_DATA_OUT <= CONF_READ_ERROR;
else if(BUS_ADD == 4)
BUS_DATA_OUT <= CONF_SIZE_BYTE[7:0]; // in units of bytes
else if(BUS_ADD == 5)
BUS_DATA_OUT <= CONF_SIZE_BYTE_BUF[15:8];
else if(BUS_ADD == 6)
BUS_DATA_OUT <= CONF_SIZE_BYTE_BUF[23:16];
else if(BUS_ADD == 7)
BUS_DATA_OUT <= CONF_SIZE_BYTE_BUF[31:24];
else
BUS_DATA_OUT <= 8'b0;
end
end
always @ (posedge BUS_CLK)
begin
if (BUS_ADD == 4 && BUS_RD)
CONF_SIZE_BYTE_BUF <= CONF_SIZE_BYTE;
end
//reg FIFO_READ_NEXT_OUT_BUF;
wire FIFO_EMPTY_IN_BUF;
wire [31:0] FIFO_DATA_BUF;
wire FULL_BUF;
assign FIFO_READ_NEXT_OUT = !FULL_BUF;
`include "../includes/log2func.v"
localparam POINTER_SIZE = `CLOG2(DEPTH);
gerneric_fifo #(.DATA_SIZE(32), .DEPTH(DEPTH)) i_buf_fifo
( .clk(BUS_CLK), .reset(RST),
.write(!FIFO_EMPTY_IN || BUS_WR_DATA),
.read(BUS_RD_DATA),
.data_in(BUS_WR_DATA ? BUS_DATA_IN_DATA : FIFO_DATA),
.full(FULL_BUF),
.empty(FIFO_EMPTY_IN_BUF),
.data_out(FIFO_DATA_BUF[31:0]), .size(CONF_SIZE[POINTER_SIZE-1:0])
);
assign CONF_SIZE[31:POINTER_SIZE] = 0;
always@(posedge BUS_CLK)
BUS_DATA_OUT_DATA <= FIFO_DATA_BUF;
assign FIFO_NOT_EMPTY = !FIFO_EMPTY_IN_BUF;
assign FIFO_FULL = FULL_BUF;
assign FIFO_READ_ERROR = (CONF_READ_ERROR != 0);
always@(posedge BUS_CLK) begin
if(RST)
CONF_READ_ERROR <= 0;
else if(FIFO_EMPTY_IN_BUF && BUS_RD_DATA && CONF_READ_ERROR != 8'hff)
CONF_READ_ERROR <= CONF_READ_ERROR +1;
end
always @(posedge BUS_CLK) begin
if(RST)
FIFO_NEAR_FULL <= 1'b0;
else if (((((FIFO_ALMOST_FULL_VALUE+1)*DEPTH)>>8) <= CONF_SIZE) || (FIFO_ALMOST_FULL_VALUE == 8'b0 && CONF_SIZE >= 0))
FIFO_NEAR_FULL <= 1'b1;
else if (((((FIFO_ALMOST_EMPTY_VALUE+1)*DEPTH)>>8) >= CONF_SIZE && FIFO_ALMOST_EMPTY_VALUE != 8'b0) || CONF_SIZE == 0)
FIFO_NEAR_FULL <= 1'b0;
end
endmodule |
module sky130_fd_sc_ms__sdfbbn (
Q ,
Q_N ,
D ,
SCD ,
SCE ,
CLK_N ,
SET_B ,
RESET_B
);
output Q ;
output Q_N ;
input D ;
input SCD ;
input SCE ;
input CLK_N ;
input SET_B ;
input RESET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule |
module sky130_fd_sc_ls__a2111oi (
Y ,
A1,
A2,
B1,
C1,
D1
);
// Module ports
output Y ;
input A1;
input A2;
input B1;
input C1;
input D1;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire and0_out ;
wire nor0_out_Y;
// Name Output Other arguments
and and0 (and0_out , A1, A2 );
nor nor0 (nor0_out_Y, B1, C1, D1, and0_out);
buf buf0 (Y , nor0_out_Y );
endmodule |
module cache_wb(clk,we,we_2,we2,we2_2,we3,we3_2,re,re2,address,address2,writedata,writedata2,writeback,hit,hit2,miss,miss2,readdatacache,readdatacache2,readdatamemory,writetag,readmisswritetomemory,readmisswritetocache,dirty);
input clk, we,we_2,we2,we2_2,we3,we3_2,re,re2;
input [31:0] address, address2, writedata,writedata2;
input [127:0] readdatamemory; // data from Main Memory
input [127:0] readmisswritetocache;
output reg hit,hit2, miss,miss2, dirty; // hit is for read, miss is for write
output reg [31:0] readdatacache,readdatacache2;
output reg [127:0] writeback; // Miss is called and sends out old data
output reg [19:0] writetag;
output reg [127:0] readmisswritetomemory;
//2-way associative, 2048 4-word block, 8192 slots, 1024 sets, in total 32KB Bytes
//address: 20 bits tag, 10bits index, 2 bits offset
// Each set in cache contains:
// 2 dirty bit(change only if written to save 20-cycle time) (first one is way 1, second is way 2), 1 least recently used bit
// Way 1: 1 valid bit, 18 tag bits, 128 bits data (4 blocks of 32 bits)
// Way 2: 1 valid bit, 18 tag bits, 128 bits data (4 blocks of 32 bits)
reg [300:0] set[1023:0];
reg [300:0] index;
reg [300:0] index2;
reg valid1,valid2,comparator1,comparator2, and1, and2, used;
reg [19:0] tag1,tag2;
reg [31:0] data1_0,data1_1, data1_2, data1_3, data2_0,data2_1, data2_2, data2_3;
reg [31:0] mux_in0,mux_in1,mux_in2,mux_in3;
integer i;
initial begin
hit = 1'b0;
miss = 1'b0;
hit2 = 1'b0;
miss2= 1'b0;
dirty = 1'b0;
for (i=0; i<1024; i=i+1) begin
set[i] = 301'b0;
end
end
always @(*) begin
index = set[address[11:2]];
index2 = set[address2[11:2]];
end
//read
always @(posedge clk) begin
if (re) begin
//dirty1 = index[300];
//dirty2 = index[299];
//used = index[298];
valid1 = index[297];
valid2 = index[148];
tag1 = index[296:277];
tag2 = index[147:128];
data1_0 = index[276:245];
data1_1 = index[244:213];
data1_2 = index[212:181];
data1_3 = index[180:149];
data2_0 = index[127:96];
data2_1 = index[95:64];
data2_2 = index[63:32];
data2_3 = index[31:0];
comparator1 = (tag1 == address[31:12]) ? 1:0;
comparator2 = (tag2 == address[31:12]) ? 1:0;
and1 = comparator1 & valid1;
and2 = comparator2 & valid2;
if (and1) begin
mux_in0 = data1_0;
mux_in1 = data1_1;
mux_in2 = data1_2;
mux_in3 = data1_3;
end
if (and2) begin
mux_in0 = data2_0;
mux_in1 = data2_1;
mux_in2 = data2_2;
mux_in3 = data2_3;
end
case(address[1:0])
2'b00: readdatacache <= mux_in0;
2'b01: readdatacache <= mux_in1;
2'b10: readdatacache <= mux_in2;
2'b11: readdatacache <= mux_in3;
endcase
hit = and1 | and2;
// if hit, change used bit accordingly
if (hit) begin
if (comparator1 == 1'b1)
set[address[11:2]][298] = 1'b1;
else if (comparator2 == 1'b1)
set[address[11:2]][298] = 1'b0;
end
// if not hit, ask data from memory
if (!hit) begin
dirty = set[address[11:2]][299] | set[address[11:2]][300];
if (index[298]==1'b1) begin
readmisswritetomemory=set[address[11:2]][127:0];
end
else begin
readmisswritetomemory=set[address[11:2]][276:149];
end
end
end
if (re2) begin
//dirty1 = index[300];
//dirty2 = index[299];
//used = index[298];
valid1 = index2[297];
valid2 = index2[148];
tag1 = index2[296:277];
tag2 = index2[147:128];
data1_0 = index2[276:245];
data1_1 = index2[244:213];
data1_2 = index2[212:181];
data1_3 = index2[180:149];
data2_0 = index2[127:96];
data2_1 = index2[95:64];
data2_2 = index2[63:32];
data2_3 = index2[31:0];
comparator1 = (tag1 == address2[31:12]) ? 1:0;
comparator2 = (tag2 == address2[31:12]) ? 1:0;
and1 = comparator1 & valid1;
and2 = comparator2 & valid2;
if (and1) begin
mux_in0 = data1_0;
mux_in1 = data1_1;
mux_in2 = data1_2;
mux_in3 = data1_3;
end
if (and2) begin
mux_in0 = data2_0;
mux_in1 = data2_1;
mux_in2 = data2_2;
mux_in3 = data2_3;
end
case(address2[1:0])
2'b00: readdatacache2 <= mux_in0;
2'b01: readdatacache2 <= mux_in1;
2'b10: readdatacache2 <= mux_in2;
2'b11: readdatacache2 <= mux_in3;
endcase
hit2 = and1 | and2;
// if hit, change used bit accordingly
if (hit2) begin
if (comparator1 == 1'b1)
set[address2[11:2]][298] = 1'b1;
else if (comparator2 == 1'b1)
set[address2[11:2]][298] = 1'b0;
end
// if not hit, ask data from memory
if (!hit2) begin
dirty = set[address2[11:2]][299] | set[address2[11:2]][300];
if (index[298]==1'b1) begin
readmisswritetomemory=set[address2[11:2]][127:0];
end
else begin
readmisswritetomemory=set[address2[11:2]][276:149];
end
end
end
end
//write
always @(negedge clk) begin
miss = 1'b0;
tag1 = index[296:277];
tag2 = index[147:128];
if (we) begin
if (tag1==address[31:12]) begin
set[address[11:2]][300] = 1'b1;
set[address[11:2]][298] = 1'b1;
set[address[11:2]][297] = 1'b1;
case(address[1:0])
2'b00 : set[address[11:2]][276:245] = writedata;
2'b01 : set[address[11:2]][244:213] = writedata;
2'b10 : set[address[11:2]][212:181] = writedata;
2'b11 : set[address[11:2]][180:149] = writedata;
endcase
end
else if (tag2==address[31:12]) begin
set[address[11:2]][299] = 1'b1;
set[address[11:2]][298] = 1'b0;
set[address[11:2]][148] = 1'b1;
case(address[1:0])
2'b00 : set[address[11:2]][127:96] = writedata;
2'b01 : set[address[11:2]][95:64] = writedata;
2'b10 : set[address[11:2]][63:32] = writedata;
2'b11 : set[address[11:2]][31:0] = writedata;
endcase
end
else begin
dirty = set[address[11:2]][299] | set[address[11:2]][300];
if (index[298]==1'b0) begin // Change way 1
miss = 1'b1;
writeback = set[address[11:2]][276:149];
writetag = set[address[11:2]][296:277];
end
else begin // Change way 2
miss = 1'b1;
writeback = set[address[11:2]][127:0];
writetag = set[address[11:2]][147:128];
end
end
end
if (we_2) begin
if (tag1==address2[31:12]) begin
set[address2[11:2]][300] = 1'b1;
set[address2[11:2]][298] = 1'b1;
set[address2[11:2]][297] = 1'b1;
case(address2[1:0])
2'b00 : set[address2[11:2]][276:245] = writedata2;
2'b01 : set[address2[11:2]][244:213] = writedata2;
2'b10 : set[address2[11:2]][212:181] = writedata2;
2'b11 : set[address2[11:2]][180:149] = writedata2;
endcase
end
else if (tag2==address2[31:12]) begin
set[address2[11:2]][299] = 1'b1;
set[address2[11:2]][298] = 1'b0;
set[address2[11:2]][148] = 1'b1;
case(address2[1:0])
2'b00 : set[address2[11:2]][127:96] = writedata2;
2'b01 : set[address2[11:2]][95:64] = writedata2;
2'b10 : set[address2[11:2]][63:32] = writedata2;
2'b11 : set[address2[11:2]][31:0] = writedata2;
endcase
end
else begin
dirty = set[address2[11:2]][299] | set[address2[11:2]][300];
if (index[298]==1'b0) begin // Change way 1
miss2 = 1'b1;
writeback = set[address2[11:2]][276:149];
writetag = set[address2[11:2]][296:277];
end
else begin // Change way 2
miss2 = 1'b1;
writeback = set[address2[11:2]][127:0];
writetag = set[address2[11:2]][147:128];
end
end
end
end
//writeback
always @(posedge we2) begin
if (index[294]==0) begin
set[address[11:2]][300] = 1'b1;
set[address[11:2]][298] = 1'b1;
set[address[11:2]][297] = 1'b1;
set[address[11:2]][276:149] = readdatamemory;
set[address[11:2]][296:277] = address[31:12];
case(address[1:0])
2'b00 : set[address[11:2]][276:245] = writedata;
2'b01 : set[address[11:2]][244:213] = writedata;
2'b10 : set[address[11:2]][212:181] = writedata;
2'b11 : set[address[11:2]][180:149] = writedata;
endcase
end
else begin
set[address[11:2]][299] = 1'b1;
set[address[11:2]][298] = 1'b0;
set[address[11:2]][148] = 1'b1;
set[address[11:2]][127:0] = readdatamemory;
set[address[11:2]][147:128] = address[31:12];
case(address[1:0])
2'b00 : set[address[11:2]][127:96] = writedata;
2'b01 : set[address[11:2]][95:64] = writedata;
2'b10 : set[address[11:2]][63:32] = writedata;
2'b11 : set[address[11:2]][31:0] = writedata;
endcase
end
end
always @(posedge we2_2) begin
if (index[294]==0) begin
set[address2[11:2]][300] = 1'b1;
set[address2[11:2]][298] = 1'b1;
set[address2[11:2]][297] = 1'b1;
set[address2[11:2]][276:149] = readdatamemory;
set[address2[11:2]][296:277] = address[31:12];
case(address2[1:0])
2'b00 : set[address2[11:2]][276:245] = writedata2;
2'b01 : set[address2[11:2]][244:213] = writedata2;
2'b10 : set[address2[11:2]][212:181] = writedata2;
2'b11 : set[address2[11:2]][180:149] = writedata2;
endcase
end
else begin
set[address2[11:2]][299] = 1'b1;
set[address2[11:2]][298] = 1'b0;
set[address2[11:2]][148] = 1'b1;
set[address2[11:2]][127:0] = readdatamemory;
set[address2[11:2]][147:128] = address2[31:12];
case(address2[1:0])
2'b00 : set[address2[11:2]][127:96] = writedata2;
2'b01 : set[address2[11:2]][95:64] = writedata2;
2'b10 : set[address2[11:2]][63:32] = writedata2;
2'b11 : set[address2[11:2]][31:0] = writedata2;
endcase
end
end
// readmissdata
always @(posedge we3) begin
if (index[294]==1'b0) begin
set[address[11:2]][299] = 1'b0;
set[address[11:2]][298] = 1'b0;
set[address[11:2]][148] = 1'b1;
set[address[11:2]][127:0]=readmisswritetocache;
set[address[11:2]][147:128]=address[31:12];
end
else begin
set[address[11:2]][300] = 1'b0;
set[address[11:2]][298] = 1'b1;
set[address[11:2]][297] = 1'b1;
set[address[11:2]][276:149]=readmisswritetocache;
set[address[11:2]][296:277]=address[31:12];
end
end
always @(posedge we3_2) begin
if (index[294]==1'b0) begin
set[address2[11:2]][299] = 1'b0;
set[address2[11:2]][298] = 1'b0;
set[address2[11:2]][148] = 1'b1;
set[address2[11:2]][127:0]=readmisswritetocache;
set[address2[11:2]][147:128]=address2[31:12];
end
else begin
set[address2[11:2]][300] = 1'b0;
set[address2[11:2]][298] = 1'b1;
set[address2[11:2]][297] = 1'b1;
set[address2[11:2]][276:149]=readmisswritetocache;
set[address2[11:2]][296:277]=address2[31:12];
end
end
always @(negedge we3) begin
case(address[1:0])
2'b00 : #5 readdatacache= readmisswritetocache[127:96];
2'b01 : #5 readdatacache= readmisswritetocache[95:64];
2'b10 : #5 readdatacache= readmisswritetocache[63:32];
2'b11 : #5 readdatacache= readmisswritetocache[31:0];
endcase
end
always @(negedge we3_2) begin
case(address2[1:0])
2'b00 : #5 readdatacache2= readmisswritetocache[127:96];
2'b01 : #5 readdatacache2= readmisswritetocache[95:64];
2'b10 : #5 readdatacache2= readmisswritetocache[63:32];
2'b11 : #5 readdatacache2= readmisswritetocache[31:0];
endcase
end
endmodule |
module sky130_fd_sc_ms__dlrtn (
Q ,
RESET_B,
D ,
GATE_N ,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
input RESET_B;
input D ;
input GATE_N ;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
endmodule |
module eth_xcvr_phy_wrapper #
(
parameter HAS_COMMON = 1,
parameter DATA_WIDTH = 64,
parameter CTRL_WIDTH = (DATA_WIDTH/8),
parameter HDR_WIDTH = 2,
parameter PRBS31_ENABLE = 0,
parameter TX_SERDES_PIPELINE = 0,
parameter RX_SERDES_PIPELINE = 0,
parameter BITSLIP_HIGH_CYCLES = 1,
parameter BITSLIP_LOW_CYCLES = 8,
parameter COUNT_125US = 125000/6.4
)
(
input wire xcvr_ctrl_clk,
input wire xcvr_ctrl_rst,
/*
* Common
*/
output wire xcvr_gtpowergood_out,
/*
* PLL out
*/
input wire xcvr_gtrefclk00_in,
output wire xcvr_qpll0lock_out,
output wire xcvr_qpll0outclk_out,
output wire xcvr_qpll0outrefclk_out,
/*
* PLL in
*/
input wire xcvr_qpll0lock_in,
output wire xcvr_qpll0reset_out,
input wire xcvr_qpll0clk_in,
input wire xcvr_qpll0refclk_in,
/*
* Serial data
*/
output wire xcvr_txp,
output wire xcvr_txn,
input wire xcvr_rxp,
input wire xcvr_rxn,
/*
* PHY connections
*/
output wire phy_tx_clk,
output wire phy_tx_rst,
input wire [DATA_WIDTH-1:0] phy_xgmii_txd,
input wire [CTRL_WIDTH-1:0] phy_xgmii_txc,
output wire phy_rx_clk,
output wire phy_rx_rst,
output wire [DATA_WIDTH-1:0] phy_xgmii_rxd,
output wire [CTRL_WIDTH-1:0] phy_xgmii_rxc,
output wire phy_tx_bad_block,
output wire [6:0] phy_rx_error_count,
output wire phy_rx_bad_block,
output wire phy_rx_sequence_error,
output wire phy_rx_block_lock,
output wire phy_rx_high_ber,
input wire phy_tx_prbs31_enable,
input wire phy_rx_prbs31_enable
);
wire phy_rx_reset_req;
wire gt_reset_tx_datapath = 1'b0;
wire gt_reset_rx_datapath = phy_rx_reset_req;
wire gt_reset_tx_done;
wire gt_reset_rx_done;
wire [5:0] gt_txheader;
wire [63:0] gt_txdata;
wire gt_rxgearboxslip;
wire [5:0] gt_rxheader;
wire [1:0] gt_rxheadervalid;
wire [63:0] gt_rxdata;
wire [1:0] gt_rxdatavalid;
generate
if (HAS_COMMON) begin : xcvr
eth_xcvr_gt_full
eth_xcvr_gt_full_inst (
// Common
.gtwiz_reset_clk_freerun_in(xcvr_ctrl_clk),
.gtwiz_reset_all_in(xcvr_ctrl_rst),
.gtpowergood_out(xcvr_gtpowergood_out),
// PLL
.gtrefclk00_in(xcvr_gtrefclk00_in),
.qpll0lock_out(xcvr_qpll0lock_out),
.qpll0outclk_out(xcvr_qpll0outclk_out),
.qpll0outrefclk_out(xcvr_qpll0outrefclk_out),
// Serial data
.gthtxp_out(xcvr_txp),
.gthtxn_out(xcvr_txn),
.gthrxp_in(xcvr_rxp),
.gthrxn_in(xcvr_rxn),
// Transmit
.gtwiz_userclk_tx_reset_in(1'b0),
.gtwiz_userclk_tx_srcclk_out(),
.gtwiz_userclk_tx_usrclk_out(),
.gtwiz_userclk_tx_usrclk2_out(phy_tx_clk),
.gtwiz_userclk_tx_active_out(),
.gtwiz_reset_tx_pll_and_datapath_in(1'b0),
.gtwiz_reset_tx_datapath_in(gt_reset_tx_datapath),
.gtwiz_reset_tx_done_out(gt_reset_tx_done),
.txpmaresetdone_out(),
.txprgdivresetdone_out(),
.txpolarity_in(1'b1),
.gtwiz_userdata_tx_in(gt_txdata),
.txheader_in(gt_txheader),
.txsequence_in(7'b0),
// Receive
.gtwiz_userclk_rx_reset_in(1'b0),
.gtwiz_userclk_rx_srcclk_out(),
.gtwiz_userclk_rx_usrclk_out(),
.gtwiz_userclk_rx_usrclk2_out(phy_rx_clk),
.gtwiz_userclk_rx_active_out(),
.gtwiz_reset_rx_pll_and_datapath_in(1'b0),
.gtwiz_reset_rx_datapath_in(gt_reset_rx_datapath),
.gtwiz_reset_rx_cdr_stable_out(),
.gtwiz_reset_rx_done_out(gt_reset_rx_done),
.rxpmaresetdone_out(),
.rxprgdivresetdone_out(),
.rxpolarity_in(1'b0),
.rxgearboxslip_in(gt_rxgearboxslip),
.gtwiz_userdata_rx_out(gt_rxdata),
.rxdatavalid_out(gt_rxdatavalid),
.rxheader_out(gt_rxheader),
.rxheadervalid_out(gt_rxheadervalid),
.rxstartofseq_out()
);
end else begin : xcvr
eth_xcvr_gt_channel
eth_xcvr_gt_channel_inst (
// Common
.gtwiz_reset_clk_freerun_in(xcvr_ctrl_clk),
.gtwiz_reset_all_in(xcvr_ctrl_rst),
.gtpowergood_out(xcvr_gtpowergood_out),
// PLL
.gtwiz_reset_qpll0lock_in(xcvr_qpll0lock_in),
.gtwiz_reset_qpll0reset_out(xcvr_qpll0reset_out),
.qpll0clk_in(xcvr_qpll0clk_in),
.qpll0refclk_in(xcvr_qpll0refclk_in),
.qpll1clk_in(1'b0),
.qpll1refclk_in(1'b0),
// Serial data
.gthtxp_out(xcvr_txp),
.gthtxn_out(xcvr_txn),
.gthrxp_in(xcvr_rxp),
.gthrxn_in(xcvr_rxn),
// Transmit
.gtwiz_userclk_tx_reset_in(1'b0),
.gtwiz_userclk_tx_srcclk_out(),
.gtwiz_userclk_tx_usrclk_out(),
.gtwiz_userclk_tx_usrclk2_out(phy_tx_clk),
.gtwiz_userclk_tx_active_out(),
.gtwiz_reset_tx_pll_and_datapath_in(1'b0),
.gtwiz_reset_tx_datapath_in(gt_reset_tx_datapath),
.gtwiz_reset_tx_done_out(gt_reset_tx_done),
.txpmaresetdone_out(),
.txprgdivresetdone_out(),
.txpolarity_in(1'b1),
.gtwiz_userdata_tx_in(gt_txdata),
.txheader_in(gt_txheader),
.txsequence_in(7'b0),
// Receive
.gtwiz_userclk_rx_reset_in(1'b0),
.gtwiz_userclk_rx_srcclk_out(),
.gtwiz_userclk_rx_usrclk_out(),
.gtwiz_userclk_rx_usrclk2_out(phy_rx_clk),
.gtwiz_userclk_rx_active_out(),
.gtwiz_reset_rx_pll_and_datapath_in(1'b0),
.gtwiz_reset_rx_datapath_in(gt_reset_rx_datapath),
.gtwiz_reset_rx_cdr_stable_out(),
.gtwiz_reset_rx_done_out(gt_reset_rx_done),
.rxpmaresetdone_out(),
.rxprgdivresetdone_out(),
.rxpolarity_in(1'b0),
.rxgearboxslip_in(gt_rxgearboxslip),
.gtwiz_userdata_rx_out(gt_rxdata),
.rxdatavalid_out(gt_rxdatavalid),
.rxheader_out(gt_rxheader),
.rxheadervalid_out(gt_rxheadervalid),
.rxstartofseq_out()
);
end
endgenerate
sync_reset #(
.N(4)
)
tx_reset_sync_inst (
.clk(phy_tx_clk),
.rst(!gt_reset_tx_done),
.out(phy_tx_rst)
);
sync_reset #(
.N(4)
)
rx_reset_sync_inst (
.clk(phy_rx_clk),
.rst(!gt_reset_rx_done),
.out(phy_rx_rst)
);
eth_phy_10g #(
.DATA_WIDTH(DATA_WIDTH),
.CTRL_WIDTH(CTRL_WIDTH),
.HDR_WIDTH(HDR_WIDTH),
.BIT_REVERSE(1),
.SCRAMBLER_DISABLE(0),
.PRBS31_ENABLE(PRBS31_ENABLE),
.TX_SERDES_PIPELINE(TX_SERDES_PIPELINE),
.RX_SERDES_PIPELINE(RX_SERDES_PIPELINE),
.BITSLIP_HIGH_CYCLES(BITSLIP_HIGH_CYCLES),
.BITSLIP_LOW_CYCLES(BITSLIP_LOW_CYCLES),
.COUNT_125US(COUNT_125US)
)
phy_inst (
.tx_clk(phy_tx_clk),
.tx_rst(phy_tx_rst),
.rx_clk(phy_rx_clk),
.rx_rst(phy_rx_rst),
.xgmii_txd(phy_xgmii_txd),
.xgmii_txc(phy_xgmii_txc),
.xgmii_rxd(phy_xgmii_rxd),
.xgmii_rxc(phy_xgmii_rxc),
.serdes_tx_data(gt_txdata),
.serdes_tx_hdr(gt_txheader),
.serdes_rx_data(gt_rxdata),
.serdes_rx_hdr(gt_rxheader),
.serdes_rx_bitslip(gt_rxgearboxslip),
.serdes_rx_reset_req(phy_rx_reset_req),
.tx_bad_block(phy_tx_bad_block),
.rx_error_count(phy_rx_error_count),
.rx_bad_block(phy_rx_bad_block),
.rx_sequence_error(phy_rx_sequence_error),
.rx_block_lock(phy_rx_block_lock),
.rx_high_ber(phy_rx_high_ber),
.tx_prbs31_enable(phy_tx_prbs31_enable),
.rx_prbs31_enable(phy_rx_prbs31_enable)
);
endmodule |
module sky130_fd_sc_hdll__a2bb2o (
X ,
A1_N,
A2_N,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule |
module i2c_slave (
// external host interface
input wire SCL, // the SCL pin state
input wire SDA,
output reg SDA_pd,
input wire clk, // internal FPGA clock
input wire glbl_reset, // internal FPGA reset
// i2c configuration
input wire [7:0] i2c_device_addr,
output reg reg_46_trig,
// internal slave interface
output wire [7:0] reg_0, // 00-3F are write-only (from the host perspective)
output wire [7:0] reg_2,
output wire [7:0] reg_4,
output wire [7:0] reg_5,
output wire [7:0] reg_6,
output wire [7:0] reg_7,
input wire [7:0] reg_40, // 40-7F are read-only (from the host perspective)
input wire [7:0] reg_41,
input wire [7:0] reg_42,
input wire [7:0] reg_44,
input wire [7:0] reg_45,
input wire [7:0] reg_46, // special case with read trigger
input wire [7:0] reg_fc, // this is for version coding
input wire [7:0] reg_fd,
input wire [7:0] reg_fe,
input wire [7:0] reg_ff
);
// internal reset
wire reset;
sync_reset i2c_slave_reset(
.clk(clk),
.glbl_reset(glbl_reset),
.reset(reset) );
/////// I2C physical layer components
/// SDA is stable when SCL is high.
/// If SDA moves while SCL is high, this is considered a start or stop condition.
///
/// Otherwise, SDA can move around when SCL is low (this is where we suppress bits or
/// overdrive as needed). SDA is a wired-AND bus, so you only "drive" zero.
///
/// In an oversampled implementation, a rising and falling edge de-glitcher is needed
/// for SCL and SDA.
///
// rise fall time cycles computation:
// At 400kHz operation, 2.5us is a cycle. "chatter" from transition should be about
// 5% of total cycle time max (just rule of thumb), so 0.125us should be the equiv
// number of cycles.
// For the demo board, a 25 MHz clock is provided, and 0.125us ~ 4 cycles
// At 100kHz operation, 10us is a cycle, so 0.5us ~ 12 cycles
parameter TRF_CYCLES = 5'd4; // number of cycles for rise/fall time
////////////////
///// protocol-level state machine
////////////////
parameter I2C_START = 14'b1 << 0; // should only pass through this state for one cycle
parameter I2C_RESTART = 14'b1 << 1;
parameter I2C_DADDR = 14'b1 << 2;
parameter I2C_ACK_DADDR = 14'b1 << 3;
parameter I2C_ADDR = 14'b1 << 4;
parameter I2C_ACK_ADDR = 14'b1 << 5;
parameter I2C_WR_DATA = 14'b1 << 6;
parameter I2C_ACK_WR = 14'b1 << 7;
parameter I2C_END_WR = 14'b1 << 8;
parameter I2C_RD_DATA = 14'b1 << 9;
parameter I2C_ACK_RD = 14'b1 << 10;
parameter I2C_END_RD = 14'b1 << 11;
parameter I2C_END_RD2 = 14'b1 << 12;
parameter I2C_WAITSTOP = 14'b1 << 13;
parameter I2C_nSTATES = 14;
reg [(I2C_nSTATES-1):0] I2C_cstate = {{(I2C_nSTATES-1){1'b0}}, 1'b1}; //current and next states
reg [(I2C_nSTATES-1):0] I2C_nstate;
//`define SIMULATION
`ifdef SIMULATION
// synthesis translate_off
reg [8*20:1] I2C_state_ascii = "I2C_START ";
always @(I2C_cstate) begin
if (I2C_cstate == I2C_START) I2C_state_ascii <= "I2C_START ";
else if (I2C_cstate == I2C_RESTART) I2C_state_ascii <= "I2C_RESTART ";
else if (I2C_cstate == I2C_DADDR) I2C_state_ascii <= "I2C_DADDR ";
else if (I2C_cstate == I2C_ACK_DADDR) I2C_state_ascii <= "I2C_ACK_DADDR ";
else if (I2C_cstate == I2C_ADDR) I2C_state_ascii <= "I2C_ADDR ";
else if (I2C_cstate == I2C_ACK_ADDR) I2C_state_ascii <= "I2C_ACK_ADDR ";
else if (I2C_cstate == I2C_WR_DATA) I2C_state_ascii <= "I2C_WR_DATA ";
else if (I2C_cstate == I2C_ACK_WR) I2C_state_ascii <= "I2C_ACK_WR ";
else if (I2C_cstate == I2C_END_WR) I2C_state_ascii <= "I2C_END_WR ";
else if (I2C_cstate == I2C_RD_DATA) I2C_state_ascii <= "I2C_RD_DATA ";
else if (I2C_cstate == I2C_ACK_RD) I2C_state_ascii <= "I2C_ACK_RD ";
else if (I2C_cstate == I2C_END_RD) I2C_state_ascii <= "I2C_END_RD ";
else if (I2C_cstate == I2C_END_RD2) I2C_state_ascii <= "I2C_END_RD2 ";
else if (I2C_cstate == I2C_WAITSTOP) I2C_state_ascii <= "I2C_WAITSTOP ";
else I2C_state_ascii <= "WTF ";
end
// synthesis translate_on
`endif
reg [3:0] I2C_bitcnt;
reg [7:0] I2C_addr;
reg [7:0] I2C_daddr;
reg [7:0] I2C_wdata;
reg [7:0] I2C_rdata;
reg I2C_reg_update;
///// register block definitions
parameter RAM_WIDTH = 8;
parameter RAM_ADDR_BITS = 6; // note parameter width exception in reg_a* assign block below
reg [RAM_WIDTH-1:0] I2C_regblock [(2**RAM_ADDR_BITS)-1:0];
reg [RAM_WIDTH-1:0] I2C_regread_async;
wire [RAM_ADDR_BITS-1:0] I2C_ramaddr;
////////// code begins here
always @ (posedge clk) begin
if (reset || ((SCL_cstate == SCL_HIGH) && (SDA_cstate == SDA_RISE))) // stop condition always resets
I2C_cstate <= I2C_START;
else
I2C_cstate <= I2C_nstate;
end
always @ (*) begin
case (I2C_cstate) //synthesis parallel_case full_case
I2C_START: begin // wait for the start condition
I2C_nstate = ((SDA_cstate == SDA_FALL) && (SCL_cstate == SCL_HIGH)) ? I2C_DADDR : I2C_START;
end
I2C_RESTART: begin // repeated start moves immediately to DADDR
I2C_nstate = I2C_DADDR;
end
I2C_DADDR: begin // 8 bits to get the address
I2C_nstate = ((I2C_bitcnt > 4'h7) && (SCL_cstate == SCL_FALL)) ? I2C_ACK_DADDR : I2C_DADDR;
end
I2C_ACK_DADDR: begin // depending upon W/R bit state, go to one of two branches
I2C_nstate = (SCL_cstate == SCL_FALL) ?
(I2C_daddr[7:1] == i2c_device_addr[7:1]) ?
(I2C_daddr[0] == 1'b0 ? I2C_ADDR : I2C_RD_DATA) :
I2C_WAITSTOP : // !I2C_daddr match
I2C_ACK_DADDR; // !SCL_FALL
end
// device address branch
I2C_ADDR: begin
I2C_nstate = ((I2C_bitcnt > 4'h7) && (SCL_cstate == SCL_FALL)) ? I2C_ACK_ADDR : I2C_ADDR;
end
I2C_ACK_ADDR: begin
I2C_nstate = (SCL_cstate == SCL_FALL) ? I2C_WR_DATA : I2C_ACK_ADDR;
end
// write branch
I2C_WR_DATA: begin // 8 bits to get the write data
I2C_nstate = ((SDA_cstate == SDA_FALL) && (SCL_cstate == SCL_HIGH)) ? I2C_RESTART : // repeated start
((I2C_bitcnt > 4'h7) && (SCL_cstate == SCL_FALL)) ? I2C_ACK_WR : I2C_WR_DATA;
end
I2C_ACK_WR: begin // trigger the ack response (pull SDA low until next falling edge)
// and stay in this state until the next falling edge of SCL
I2C_nstate = (SCL_cstate == SCL_FALL) ? I2C_END_WR : I2C_ACK_WR;
end
I2C_END_WR: begin // one-cycle state to update address+1, reset SDA pulldown
I2C_nstate = I2C_WR_DATA; // SCL is now low
end
// read branch
I2C_RD_DATA: begin // 8 bits to get the read data
I2C_nstate = ((SDA_cstate == SDA_FALL) && (SCL_cstate == SCL_HIGH)) ? I2C_RESTART : // repeated start
((I2C_bitcnt > 4'h7) && (SCL_cstate == SCL_FALL)) ? I2C_ACK_RD : I2C_RD_DATA;
end
I2C_ACK_RD: begin // wait for an (n)ack response
// need to sample (n)ack on a rising edge
I2C_nstate = (SCL_cstate == SCL_RISE) ? I2C_END_RD : I2C_ACK_RD;
end
I2C_END_RD: begin // if nack, just go to start state (don't explicitly check stop event)
// single cycle state for adr+1 update
I2C_nstate = (SDA_cstate == SDA_LOW) ? I2C_END_RD2 : I2C_START;
end
I2C_END_RD2: begin // before entering I2C_RD_DATA, we need to have seen a falling edge.
I2C_nstate = (SCL_cstate == SCL_FALL) ? I2C_RD_DATA : I2C_END_RD2;
end
// we're not the addressed device, so we just idle until we see a stop
I2C_WAITSTOP: begin
I2C_nstate = (((SCL_cstate == SCL_HIGH) && (SDA_cstate == SDA_RISE))) ? // stop
I2C_START :
(((SCL_cstate == SCL_HIGH) && (SDA_cstate == SDA_FALL))) ? // or start
I2C_RESTART :
I2C_WAITSTOP;
end
endcase // case (cstate)
end
always @ (posedge clk) begin
if( reset ) begin
I2C_bitcnt <= 4'b0;
I2C_daddr <= 8'b0;
I2C_wdata <= 8'b0;
SDA_pd <= 1'b0;
I2C_reg_update <= 1'b0;
I2C_rdata <= 8'b0;
I2C_addr <= 8'b0; // this persists across transactions
end else begin
case (I2C_cstate) // synthesis parallel_case full_case
I2C_START: begin // everything in reset
I2C_bitcnt <= 4'b0;
I2C_daddr <= 8'b0;
I2C_wdata <= 8'b0;
I2C_rdata <= 8'b0;
SDA_pd <= 1'b0;
I2C_reg_update <= 1'b0;
I2C_addr <= I2C_addr;
end
I2C_RESTART: begin
I2C_bitcnt <= 4'b0;
I2C_daddr <= 8'b0;
I2C_wdata <= 8'b0;
I2C_rdata <= 8'b0;
SDA_pd <= 1'b0;
I2C_reg_update <= 1'b0;
I2C_addr <= I2C_addr;
end
// get my i2c device address (am I being talked to?)
I2C_DADDR: begin // shift in the address on rising edges of clock
if( SCL_cstate == SCL_RISE ) begin
I2C_bitcnt <= I2C_bitcnt + 4'b1;
I2C_daddr[7] <= I2C_daddr[6];
I2C_daddr[6] <= I2C_daddr[5];
I2C_daddr[5] <= I2C_daddr[4];
I2C_daddr[4] <= I2C_daddr[3];
I2C_daddr[3] <= I2C_daddr[2];
I2C_daddr[2] <= I2C_daddr[1];
I2C_daddr[1] <= I2C_daddr[0];
I2C_daddr[0] <= (SDA_cstate == SDA_HIGH) ? 1'b1 : 1'b0;
end else begin // we're oversampled so we need a hold-state gutter
I2C_bitcnt <= I2C_bitcnt;
I2C_daddr <= I2C_daddr;
end // else: !if( SCL_cstate == SCL_RISE )
SDA_pd <= 1'b0;
I2C_wdata <= 8'b0;
I2C_rdata <= 8'b0;
I2C_reg_update <= 1'b0;
I2C_addr <= I2C_addr;
end // case: I2C_DADDR
I2C_ACK_DADDR: begin
SDA_pd <= 1'b1; // active pull down ACK
I2C_daddr <= I2C_daddr;
I2C_bitcnt <= 4'b0;
I2C_wdata <= 8'b0;
I2C_rdata <= I2C_regread_async;
I2C_reg_update <= 1'b0;
I2C_addr <= I2C_addr;
end
// get my i2c "write" address (what we want to access inside me)
I2C_ADDR: begin
if( SCL_cstate == SCL_RISE ) begin
I2C_bitcnt <= I2C_bitcnt + 4'b1;
I2C_addr[7] <= I2C_addr[6];
I2C_addr[6] <= I2C_addr[5];
I2C_addr[5] <= I2C_addr[4];
I2C_addr[4] <= I2C_addr[3];
I2C_addr[3] <= I2C_addr[2];
I2C_addr[2] <= I2C_addr[1];
I2C_addr[1] <= I2C_addr[0];
I2C_addr[0] <= (SDA_cstate == SDA_HIGH) ? 1'b1 : 1'b0;
end else begin // we're oversampled so we need a hold-state gutter
I2C_bitcnt <= I2C_bitcnt;
I2C_addr <= I2C_addr;
end // else: !if( SCL_cstate == SCL_RISE )
SDA_pd <= 1'b0;
I2C_wdata <= 8'b0;
I2C_rdata <= 8'b0;
I2C_reg_update <= 1'b0;
I2C_daddr <= I2C_daddr;
end // case: I2C_ADDR
I2C_ACK_ADDR: begin
SDA_pd <= 1'b1; // active pull down ACK
I2C_daddr <= I2C_daddr;
I2C_bitcnt <= 4'b0;
I2C_wdata <= 8'b0;
I2C_rdata <= I2C_regread_async; // update my read data here
I2C_reg_update <= 1'b0;
I2C_addr <= I2C_addr;
end
// write branch
I2C_WR_DATA: begin // shift in data on rising edges of clock
if( SCL_cstate == SCL_RISE ) begin
I2C_bitcnt <= I2C_bitcnt + 4'b1;
I2C_wdata[7] <= I2C_wdata[6];
I2C_wdata[6] <= I2C_wdata[5];
I2C_wdata[5] <= I2C_wdata[4];
I2C_wdata[4] <= I2C_wdata[3];
I2C_wdata[3] <= I2C_wdata[2];
I2C_wdata[2] <= I2C_wdata[1];
I2C_wdata[1] <= I2C_wdata[0];
I2C_wdata[0] <= (SDA_cstate == SDA_HIGH) ? 1'b1 : 1'b0;
end else begin
I2C_bitcnt <= I2C_bitcnt; // hold state gutter
I2C_wdata <= I2C_wdata;
end // else: !if( SCL_cstate == SCL_RISE )
SDA_pd <= 1'b0;
I2C_daddr <= I2C_daddr;
I2C_reg_update <= 1'b0;
I2C_rdata <= I2C_rdata;
I2C_addr <= I2C_addr;
end // case: I2C_WR_DATA
I2C_ACK_WR: begin
SDA_pd <= 1'b1; // active pull down ACK
I2C_daddr <= I2C_daddr;
I2C_bitcnt <= 4'b0;
I2C_wdata <= I2C_wdata;
I2C_reg_update <= 1'b1; // write the data now (over and over again while in state)
I2C_rdata <= I2C_rdata;
I2C_addr <= I2C_addr;
end
I2C_END_WR: begin
SDA_pd <= 1'b0; // let SDA rise (host may look for this to know ack is done
I2C_addr <= I2C_addr + 8'b1; // this is a one-cycle state so this is safe
I2C_bitcnt <= 4'b0;
I2C_wdata <= 8'b0;
I2C_rdata <= I2C_rdata;
I2C_reg_update <= 1'b0;
I2C_daddr <= I2C_daddr;
end
// read branch
I2C_RD_DATA: begin // shift out data on falling edges of clock
SDA_pd <= I2C_rdata[7] ? 1'b0 : 1'b1;
if( SCL_cstate == SCL_RISE ) begin
I2C_bitcnt <= I2C_bitcnt + 4'b1;
end else begin
I2C_bitcnt <= I2C_bitcnt; // hold state gutter
end
if( SCL_cstate == SCL_FALL ) begin
I2C_rdata[7] <= I2C_rdata[6];
I2C_rdata[6] <= I2C_rdata[5];
I2C_rdata[5] <= I2C_rdata[4];
I2C_rdata[4] <= I2C_rdata[3];
I2C_rdata[3] <= I2C_rdata[2];
I2C_rdata[2] <= I2C_rdata[1];
I2C_rdata[1] <= I2C_rdata[0];
I2C_rdata[0] <= 1'b0;
end else begin
I2C_rdata <= I2C_rdata;
end // else: !if( SCL_cstate == SCL_RISE )
I2C_daddr <= I2C_daddr;
I2C_reg_update <= 1'b0;
I2C_wdata <= I2C_wdata;
I2C_addr <= I2C_addr;
end // case: I2C_RD_DATA
I2C_ACK_RD: begin
SDA_pd <= 1'b0; // in ack state don't pull down, we are listening to host
I2C_daddr <= I2C_daddr;
I2C_bitcnt <= 4'b0;
I2C_rdata <= I2C_rdata;
I2C_reg_update <= 1'b0;
I2C_wdata <= I2C_wdata;
I2C_addr <= I2C_addr;
end
I2C_END_RD: begin
SDA_pd <= 1'b0; // let SDA rise (host may look for this to know ack is done
I2C_addr <= I2C_addr + 8'b1; // this is a one-cycle state so this is safe
I2C_bitcnt <= 4'b0;
I2C_rdata <= I2C_rdata;
I2C_reg_update <= 1'b0;
I2C_wdata <= I2C_wdata;
I2C_daddr <= I2C_daddr;
end
I2C_END_RD2: begin
SDA_pd <= 1'b0;
I2C_daddr <= 8'b0;
I2C_bitcnt <= 4'b0;
I2C_rdata <= I2C_regread_async; // update my read data here
I2C_reg_update <= 1'b0;
I2C_wdata <= I2C_wdata;
I2C_addr <= I2C_addr;
end
I2C_WAITSTOP: begin
SDA_pd <= 1'b0;
I2C_daddr <= 8'b0;
I2C_bitcnt <= 4'b0;
I2C_rdata <= I2C_rdata;
I2C_reg_update <= 1'b0;
I2C_wdata <= I2C_wdata;
I2C_addr <= I2C_addr;
end
endcase // case (cstate)
end // else: !if( reset )
end // always @ (posedge clk or posedge reset)
////////////////////////////////////
///// register bank management /////
////////////////////////////////////
// main block update (write from I2C)
always @(posedge clk) begin
if (I2C_reg_update && ((I2C_addr[6] == 1'b0) && (I2C_addr[7] == 1'b0))) begin // I2C_addr < 8'h40
I2C_regblock[I2C_ramaddr] <= I2C_wdata;
end
end
assign I2C_ramaddr = I2C_addr[RAM_ADDR_BITS-1:0];
///////// ick, had to hard-code the width against RAM_ADDR_BITS which is parameterized
assign reg_0 = I2C_regblock[6'h0];
assign reg_2 = I2C_regblock[6'h2];
assign reg_4 = I2C_regblock[6'h4];
assign reg_5 = I2C_regblock[6'h5];
assign reg_6 = I2C_regblock[6'h6];
assign reg_7 = I2C_regblock[6'h7];
always @(posedge clk) begin
if( (I2C_addr[7:0] == 8'h46) & ((I2C_cstate == I2C_ACK_ADDR) ||
(I2C_cstate == I2C_END_RD2)) ) begin
reg_46_trig <= 1'b1;
end else begin
reg_46_trig <= 1'b0;
end
end
always @(*) begin
case (I2C_addr[7:0])
8'h40: begin
I2C_regread_async = reg_40;
end
8'h41: begin
I2C_regread_async = reg_41;
end
8'h42: begin
I2C_regread_async = reg_42;
end
8'h44: begin
I2C_regread_async = reg_44;
end
8'h45: begin
I2C_regread_async = reg_45;
end
8'h46: begin
I2C_regread_async = reg_46;
end
8'hfc: begin
I2C_regread_async = reg_fc;
end
8'hfd: begin
I2C_regread_async = reg_fd;
end
8'hfe: begin
I2C_regread_async = reg_fe;
end
8'hff: begin
I2C_regread_async = reg_ff;
end
default: begin
I2C_regread_async = I2C_regblock[I2C_ramaddr];
end
endcase // case I2C_ramaddr
end // always @ (*)
///////////////////////////////////////////////////////////////
/////////// low level state machines //////////////////////////
///////////////////////////////////////////////////////////////
////////////////
///// SCL low-level sampling state machine
////////////////
parameter SCL_HIGH = 4'b1 << 0; // should only pass through this state for one cycle
parameter SCL_FALL = 4'b1 << 1;
parameter SCL_LOW = 4'b1 << 2;
parameter SCL_RISE = 4'b1 << 3;
parameter SCL_nSTATES = 4;
reg [(SCL_nSTATES-1):0] SCL_cstate = {{(SCL_nSTATES-1){1'b0}}, 1'b1}; //current and next states
reg [(SCL_nSTATES-1):0] SCL_nstate;
//`define SIMULATION
`ifdef SIMULATION
// synthesis translate_off
reg [8*20:1] SCL_state_ascii = "SCL_HIGH ";
always @(SCL_cstate) begin
if (SCL_cstate == SCL_HIGH) SCL_state_ascii <= "SCL_HIGH ";
else if (SCL_cstate == SCL_FALL) SCL_state_ascii <= "SCL_FALL ";
else if (SCL_cstate == SCL_LOW ) SCL_state_ascii <= "SCL_LOW ";
else if (SCL_cstate == SCL_RISE) SCL_state_ascii <= "SCL_RISE ";
else SCL_state_ascii <= "WTF ";
end
// synthesis translate_on
`endif
reg [4:0] SCL_rfcnt;
reg SCL_s, SCL_sync;
reg SDA_s, SDA_sync;
always @ (posedge clk) begin
if (reset)
SCL_cstate <= SCL_HIGH; // always start here even if it's wrong -- easier to test
else
SCL_cstate <= SCL_nstate;
end
always @ (*) begin
case (SCL_cstate) //synthesis parallel_case full_case
SCL_HIGH: begin
SCL_nstate = ((SCL_rfcnt > TRF_CYCLES) && (SCL_sync == 1'b0)) ? SCL_FALL : SCL_HIGH;
end
SCL_FALL: begin
SCL_nstate = SCL_LOW;
end
SCL_LOW: begin
SCL_nstate = ((SCL_rfcnt > TRF_CYCLES) && (SCL_sync == 1'b1)) ? SCL_RISE : SCL_LOW;
end
SCL_RISE: begin
SCL_nstate = SCL_HIGH;
end
endcase // case (cstate)
end // always @ (*)
always @ (posedge clk) begin
if( reset ) begin
SCL_rfcnt <= 5'b0;
end else begin
case (SCL_cstate) // synthesis parallel_case full_case
SCL_HIGH: begin
if( SCL_sync == 1'b1 ) begin
SCL_rfcnt <= 5'b0;
end else begin
SCL_rfcnt <= SCL_rfcnt + 5'b1;
end
end
SCL_FALL: begin
SCL_rfcnt <= 5'b0;
end
SCL_LOW: begin
if( SCL_sync == 1'b0 ) begin
SCL_rfcnt <= 5'b0;
end else begin
SCL_rfcnt <= SCL_rfcnt + 5'b1;
end
end
SCL_RISE: begin
SCL_rfcnt <= 5'b0;
end
endcase // case (cstate)
end // else: !if( reset )
end // always @ (posedge clk or posedge reset)
////////////////
///// SDA low-level sampling state machine
////////////////
parameter SDA_HIGH = 4'b1 << 0; // should only pass through this state for one cycle
parameter SDA_FALL = 4'b1 << 1;
parameter SDA_LOW = 4'b1 << 2;
parameter SDA_RISE = 4'b1 << 3;
parameter SDA_nSTATES = 4;
reg [(SDA_nSTATES-1):0] SDA_cstate = {{(SDA_nSTATES-1){1'b0}}, 1'b1}; //current and next states
reg [(SDA_nSTATES-1):0] SDA_nstate;
//`define SIMULATION
`ifdef SIMULATION
// synthesis translate_off
reg [8*20:1] SDA_state_ascii = "SDA_HIGH ";
always @(SDA_cstate) begin
if (SDA_cstate == SDA_HIGH) SDA_state_ascii <= "SDA_HIGH ";
else if (SDA_cstate == SDA_FALL) SDA_state_ascii <= "SDA_FALL ";
else if (SDA_cstate == SDA_LOW ) SDA_state_ascii <= "SDA_LOW ";
else if (SDA_cstate == SDA_RISE) SDA_state_ascii <= "SDA_RISE ";
else SDA_state_ascii <= "WTF ";
end
// synthesis translate_on
`endif
reg [4:0] SDA_rfcnt;
always @ (posedge clk) begin
if (reset)
SDA_cstate <= SDA_HIGH; // always start here even if it's wrong -- easier to test
else
SDA_cstate <= SDA_nstate;
end
always @ (*) begin
case (SDA_cstate) //synthesis parallel_case full_case
SDA_HIGH: begin
SDA_nstate = ((SDA_rfcnt > TRF_CYCLES) && (SDA_sync == 1'b0)) ? SDA_FALL : SDA_HIGH;
end
SDA_FALL: begin
SDA_nstate = SDA_LOW;
end
SDA_LOW: begin
SDA_nstate = ((SDA_rfcnt > TRF_CYCLES) && (SDA_sync == 1'b1)) ? SDA_RISE : SDA_LOW;
end
SDA_RISE: begin
SDA_nstate = SDA_HIGH;
end
endcase // case (cstate)
end // always @ (*)
always @ (posedge clk) begin
if( reset ) begin
SDA_rfcnt <= 5'b0;
end else begin
case (SDA_cstate) // synthesis parallel_case full_case
SDA_HIGH: begin
if( SDA_sync == 1'b1 ) begin
SDA_rfcnt <= 5'b0;
end else begin
SDA_rfcnt <= SDA_rfcnt + 5'b1;
end
end
SDA_FALL: begin
SDA_rfcnt <= 5'b0;
end
SDA_LOW: begin
if( SDA_sync == 1'b0 ) begin
SDA_rfcnt <= 5'b0;
end else begin
SDA_rfcnt <= SDA_rfcnt + 5'b1;
end
end
SDA_RISE: begin
SDA_rfcnt <= 5'b0;
end
endcase // case (cstate)
end // else: !if( reset )
end // always @ (posedge clk or posedge reset)
/////////////////////
/////// synchronizers
/////////////////////
always @ (posedge clk) begin
SCL_s <= SCL;
SCL_sync <= SCL_s;
SDA_s <= SDA;
SDA_sync <= SDA_s;
end // always @ (posedge clk or posedge reset)
endmodule |
module avalon_camera (
// Avalon clock interface signals
input clk,
input reset_n,
// Signals for Avalon-MM slave port
input [4:0] avs_s1_address,
input avs_s1_read,
output reg [31:0] avs_s1_readdata,
input avs_s1_write,
input [31:0] avs_s1_writedata,
// Control signals to export to the image_capture
output avs_export_start_capture,
output [15:0] avs_export_capture_width,
output [15:0] avs_export_capture_height,
output [31:0] avs_export_buff0,
output [31:0] avs_export_buff1,
input avs_export_buff0full,
input avs_export_buff1full,
input avs_export_capture_standby,
// Registers to export to the camera_config
output [15:0] avs_export_width,
output [15:0] avs_export_height,
output [15:0] avs_export_start_row,
output [15:0] avs_export_start_column,
output [15:0] avs_export_row_size,
output [15:0] avs_export_column_size,
output [15:0] avs_export_row_mode,
output [15:0] avs_export_column_mode,
output [15:0] avs_export_exposure,
//soft reset
output avs_export_cam_soft_reset_n
);
// Addresses of the registers to control image_capture
`define ADDR_START_CAPTURE 5'h00
`define ADDR_CAPTURE_WIDTH 5'h01
`define ADDR_CAPTURE_HEIGHT 5'h02
`define ADDR_BUFF0 5'h03
`define ADDR_BUFF1 5'h04
`define ADDR_BUFF0FULL 5'h05
`define ADDR_BUFF1FULL 5'h06
`define ADDR_CAPTURE_STANDBY 5'h07
// Addresses of the registers to control camera_config
`define ADDR_WIDTH 5'h09
`define ADDR_HEIGHT 5'h0a
`define ADDR_START_ROW 5'h0b
`define ADDR_START_COLUMN 5'h0c
`define ADDR_ROW_SIZE 5'h0d
`define ADDR_COLUMN_SIZE 5'h0e
`define ADDR_ROW_MODE 5'h0f
`define ADDR_COLUMN_MODE 5'h10
`define ADDR_EXPOSURE 5'h11
// Address of the soft reset
`define SOFT_RESET_N 5'h1F //last address
// Camera config registers default values
parameter WIDTH = 16'd320;
parameter HEIGHT = 16'd240;
parameter START_ROW = 16'h0036;
parameter START_COLUMN = 16'h0010;
parameter ROW_SIZE = 16'h059f;
parameter COLUMN_SIZE = 16'h077f;
parameter ROW_MODE = 16'h0002;
parameter COLUMN_MODE = 16'h0002;
parameter EXPOSURE = 16'h07c0;
// image_capture regs
reg start_capture;
reg [15:0] capture_width;
reg [15:0] capture_height;
reg [31:0] buff0;
reg [31:0] buff1;
reg buff0full;
reg buff1full;
wire standby;
// camera_config regs
reg [15:0] data_width;
reg [15:0] data_height;
reg [15:0] data_start_row;
reg [15:0] data_start_column;
reg [15:0] data_row_size;
reg [15:0] data_column_size;
reg [15:0] data_row_mode;
reg [15:0] data_column_mode;
reg [15:0] data_exposure;
//soft_reset reg
reg cam_soft_reset_n;
// Read/Write registers
always @(posedge clk or negedge reset_n)
begin
if (!reset_n) begin
start_capture <= 1'b0;
capture_width <= 16'd0;
capture_height <= 16'd0;
buff0[31:0] <= 32'd0;
buff1[31:0] <= 32'd0;
data_width[15:0] <= WIDTH[15:0];
data_height[15:0] <= HEIGHT[15:0];
data_start_row[15:0] <= START_ROW[15:0];
data_start_column[15:0] <= START_COLUMN[15:0];
data_row_size[15:0] <= ROW_SIZE[15:0];
data_column_size[15:0] <= COLUMN_SIZE[15:0];
data_row_mode[15:0] <= ROW_MODE[15:0];
data_column_mode[15:0] <= COLUMN_MODE[15:0];
data_exposure[15:0] <= EXPOSURE[15:0];
cam_soft_reset_n <= 1;
end
else begin
if (avs_s1_read) begin
case (avs_s1_address)
//image_capture
`ADDR_START_CAPTURE:
avs_s1_readdata[31:0] <= {31'b0, start_capture};
`ADDR_CAPTURE_WIDTH:
avs_s1_readdata[31:0] <= {16'b0, capture_width};
`ADDR_CAPTURE_HEIGHT:
avs_s1_readdata[31:0] <= {16'b0, capture_height};
`ADDR_BUFF0:
avs_s1_readdata[31:0] <= buff0;
`ADDR_BUFF1:
avs_s1_readdata[31:0] <= buff1;
`ADDR_BUFF0FULL:
avs_s1_readdata[31:0] <= {31'b0, buff0full};
`ADDR_BUFF1FULL:
avs_s1_readdata[31:0] <= {31'b0, buff1full};
`ADDR_CAPTURE_STANDBY:
avs_s1_readdata[31:0] <= {31'b0, standby};
//camera_config
`ADDR_WIDTH:
avs_s1_readdata[15:0] <= data_width[15:0];
`ADDR_HEIGHT:
avs_s1_readdata[15:0] <= data_height[15:0];
`ADDR_START_ROW:
avs_s1_readdata[15:0] <= data_start_row[15:0];
`ADDR_START_COLUMN:
avs_s1_readdata[15:0] <= data_start_column[15:0];
`ADDR_ROW_SIZE:
avs_s1_readdata[15:0] <= data_row_size[15:0];
`ADDR_COLUMN_SIZE:
avs_s1_readdata[15:0] <= data_column_size[15:0];
`ADDR_ROW_MODE:
avs_s1_readdata[15:0] <= data_row_mode[15:0];
`ADDR_COLUMN_MODE:
avs_s1_readdata[15:0] <= data_column_mode[15:0];
`ADDR_EXPOSURE:
avs_s1_readdata[15:0] <= data_exposure[15:0];
//soft reset
`SOFT_RESET_N:
avs_s1_readdata[31:0] <= {31'b0, cam_soft_reset_n};
default:
avs_s1_readdata <= {32'd0};
endcase
end
// if avs_s1_read is FALSE...
else begin
if (avs_s1_write) begin
case (avs_s1_address)
//image_capture
`ADDR_START_CAPTURE:
start_capture <= avs_s1_writedata[0];
`ADDR_CAPTURE_WIDTH:
capture_width <= avs_s1_writedata[16:0];
`ADDR_CAPTURE_HEIGHT:
capture_height <= avs_s1_writedata[16:0];
`ADDR_BUFF0:
buff0 <= avs_s1_writedata[31:0];
`ADDR_BUFF1:
buff1 <= avs_s1_writedata[31:0];
//`ADDR_CAPTURE_STANDBY://not writable
`ADDR_WIDTH:
data_width[15:0] <= avs_s1_writedata[15:0];
`ADDR_HEIGHT:
data_height[15:0] <= avs_s1_writedata[15:0];
`ADDR_START_ROW:
data_start_row[15:0] <= avs_s1_writedata[15:0];
`ADDR_START_COLUMN:
data_start_column[15:0] <= avs_s1_writedata[15:0];
`ADDR_ROW_SIZE:
data_row_size[15:0] <= avs_s1_writedata[15:0];
`ADDR_COLUMN_SIZE:
data_column_size[15:0] <= avs_s1_writedata[15:0];
`ADDR_ROW_MODE:
data_row_mode[15:0] <= avs_s1_writedata[15:0];
`ADDR_COLUMN_MODE:
data_column_mode[15:0] <= avs_s1_writedata[15:0];
`ADDR_EXPOSURE:
data_exposure[15:0] <= avs_s1_writedata[15:0];
`SOFT_RESET_N:
cam_soft_reset_n <= avs_s1_writedata[0];
endcase
end
end
end
end
//buff0full and buff1full registers
//this signals are coming from the capture_image and may be clocked
//by a different clock. Thats why asynchronous set is done here
//to set this signals. The processor uses this signals to know that
//one line has finished and can read the buffer. The processor is
//in charge of erase this signals through the avalon bus.
always @(posedge clk or negedge reset_n or posedge avs_export_buff0full)
begin
if (avs_export_buff0full) buff0full <= 1'b1;
else if (!reset_n) buff0full <= 1'b0;
else begin
if (avs_s1_write == 1) begin
case (avs_s1_address)
`ADDR_BUFF0FULL: buff0full <= avs_s1_writedata[0];
endcase
end
end
end
always @(posedge clk or negedge reset_n or posedge avs_export_buff1full)
begin
if (avs_export_buff1full) buff1full <= 1'b1;
else if (!reset_n) buff1full <= 1'b0;
else begin
if (avs_s1_write == 1) begin
case (avs_s1_address)
`ADDR_BUFF1FULL: buff1full <= avs_s1_writedata[0];
endcase
end
end
end
// Control signals to export to the image capture
assign avs_export_capture_width = capture_width;
assign avs_export_capture_height = capture_height;
assign avs_export_start_capture = start_capture;
assign avs_export_buff0 = buff0;
assign avs_export_buff1 = buff1;
assign standby = avs_export_capture_standby;
// Registers to export to the camera_config
assign avs_export_start_row[15:0] = data_start_row[15:0];
assign avs_export_start_column[15:0] = data_start_column[15:0];
assign avs_export_row_size[15:0] = data_row_size[15:0];
assign avs_export_column_size[15:0] = data_column_size[15:0];
assign avs_export_row_mode[15:0] = data_row_mode[15:0];
assign avs_export_column_mode[15:0] = data_column_mode[15:0];
assign avs_export_exposure[15:0] = data_exposure[15:0];
// Registers to export to the camera_config an
assign avs_export_width[15:0] = data_width[15:0];
assign avs_export_height[15:0] = data_height[15:0];
//soft reset
assign avs_export_cam_soft_reset_n = cam_soft_reset_n;
endmodule |
module system_vga_hessian_1_0
(clk_x16,
active,
rst,
x_addr,
y_addr,
g_in,
hessian_out);
input clk_x16;
input active;
(* x_interface_info = "xilinx.com:signal:reset:1.0 rst RST" *) input rst;
input [9:0]x_addr;
input [9:0]y_addr;
input [7:0]g_in;
output [31:0]hessian_out;
wire active;
wire clk_x16;
wire [7:0]g_in;
wire [31:0]hessian_out;
wire rst;
wire [9:0]x_addr;
wire [9:0]y_addr;
system_vga_hessian_1_0_vga_hessian U0
(.active(active),
.clk_x16(clk_x16),
.g_in(g_in),
.hessian_out(hessian_out),
.rst(rst),
.x_addr(x_addr),
.y_addr(y_addr));
endmodule |
module system_vga_hessian_1_0_blk_mem_gen_0
(clka,
ena,
wea,
addra,
dina,
douta,
clkb,
enb,
web,
addrb,
dinb,
doutb);
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK" *) input clka;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA EN" *) input ena;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA WE" *) input [0:0]wea;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR" *) input [13:0]addra;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN" *) input [15:0]dina;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT" *) output [15:0]douta;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTB CLK" *) input clkb;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTB EN" *) input enb;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTB WE" *) input [0:0]web;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTB ADDR" *) input [13:0]addrb;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTB DIN" *) input [15:0]dinb;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTB DOUT" *) output [15:0]doutb;
wire [13:0]addra;
wire [13:0]addrb;
wire clka;
wire clkb;
wire [15:0]dina;
wire [15:0]dinb;
wire [15:0]douta;
wire [15:0]doutb;
wire ena;
wire enb;
wire [0:0]wea;
wire [0:0]web;
wire NLW_U0_dbiterr_UNCONNECTED;
wire NLW_U0_rsta_busy_UNCONNECTED;
wire NLW_U0_rstb_busy_UNCONNECTED;
wire NLW_U0_s_axi_arready_UNCONNECTED;
wire NLW_U0_s_axi_awready_UNCONNECTED;
wire NLW_U0_s_axi_bvalid_UNCONNECTED;
wire NLW_U0_s_axi_dbiterr_UNCONNECTED;
wire NLW_U0_s_axi_rlast_UNCONNECTED;
wire NLW_U0_s_axi_rvalid_UNCONNECTED;
wire NLW_U0_s_axi_sbiterr_UNCONNECTED;
wire NLW_U0_s_axi_wready_UNCONNECTED;
wire NLW_U0_sbiterr_UNCONNECTED;
wire [13:0]NLW_U0_rdaddrecc_UNCONNECTED;
wire [3:0]NLW_U0_s_axi_bid_UNCONNECTED;
wire [1:0]NLW_U0_s_axi_bresp_UNCONNECTED;
wire [13:0]NLW_U0_s_axi_rdaddrecc_UNCONNECTED;
wire [15:0]NLW_U0_s_axi_rdata_UNCONNECTED;
wire [3:0]NLW_U0_s_axi_rid_UNCONNECTED;
wire [1:0]NLW_U0_s_axi_rresp_UNCONNECTED;
(* C_ADDRA_WIDTH = "14" *)
(* C_ADDRB_WIDTH = "14" *)
(* C_ALGORITHM = "1" *)
(* C_AXI_ID_WIDTH = "4" *)
(* C_AXI_SLAVE_TYPE = "0" *)
(* C_AXI_TYPE = "1" *)
(* C_BYTE_SIZE = "9" *)
(* C_COMMON_CLK = "0" *)
(* C_COUNT_18K_BRAM = "1" *)
(* C_COUNT_36K_BRAM = "7" *)
(* C_CTRL_ECC_ALGO = "NONE" *)
(* C_DEFAULT_DATA = "0" *)
(* C_DISABLE_WARN_BHV_COLL = "0" *)
(* C_DISABLE_WARN_BHV_RANGE = "0" *)
(* C_ELABORATION_DIR = "./" *)
(* C_ENABLE_32BIT_ADDRESS = "0" *)
(* C_EN_DEEPSLEEP_PIN = "0" *)
(* C_EN_ECC_PIPE = "0" *)
(* C_EN_RDADDRA_CHG = "0" *)
(* C_EN_RDADDRB_CHG = "0" *)
(* C_EN_SAFETY_CKT = "0" *)
(* C_EN_SHUTDOWN_PIN = "0" *)
(* C_EN_SLEEP_PIN = "0" *)
(* C_EST_POWER_SUMMARY = "Estimated Power for IP : 22.148499999999999 mW" *)
(* C_FAMILY = "zynq" *)
(* C_HAS_AXI_ID = "0" *)
(* C_HAS_ENA = "1" *)
(* C_HAS_ENB = "1" *)
(* C_HAS_INJECTERR = "0" *)
(* C_HAS_MEM_OUTPUT_REGS_A = "1" *)
(* C_HAS_MEM_OUTPUT_REGS_B = "1" *)
(* C_HAS_MUX_OUTPUT_REGS_A = "0" *)
(* C_HAS_MUX_OUTPUT_REGS_B = "0" *)
(* C_HAS_REGCEA = "0" *)
(* C_HAS_REGCEB = "0" *)
(* C_HAS_RSTA = "0" *)
(* C_HAS_RSTB = "0" *)
(* C_HAS_SOFTECC_INPUT_REGS_A = "0" *)
(* C_HAS_SOFTECC_OUTPUT_REGS_B = "0" *)
(* C_INITA_VAL = "0" *)
(* C_INITB_VAL = "0" *)
(* C_INIT_FILE = "blk_mem_gen_0.mem" *)
(* C_INIT_FILE_NAME = "no_coe_file_loaded" *)
(* C_INTERFACE_TYPE = "0" *)
(* C_LOAD_INIT_FILE = "0" *)
(* C_MEM_TYPE = "2" *)
(* C_MUX_PIPELINE_STAGES = "0" *)
(* C_PRIM_TYPE = "1" *)
(* C_READ_DEPTH_A = "16384" *)
(* C_READ_DEPTH_B = "16384" *)
(* C_READ_WIDTH_A = "16" *)
(* C_READ_WIDTH_B = "16" *)
(* C_RSTRAM_A = "0" *)
(* C_RSTRAM_B = "0" *)
(* C_RST_PRIORITY_A = "CE" *)
(* C_RST_PRIORITY_B = "CE" *)
(* C_SIM_COLLISION_CHECK = "ALL" *)
(* C_USE_BRAM_BLOCK = "0" *)
(* C_USE_BYTE_WEA = "0" *)
(* C_USE_BYTE_WEB = "0" *)
(* C_USE_DEFAULT_DATA = "0" *)
(* C_USE_ECC = "0" *)
(* C_USE_SOFTECC = "0" *)
(* C_USE_URAM = "0" *)
(* C_WEA_WIDTH = "1" *)
(* C_WEB_WIDTH = "1" *)
(* C_WRITE_DEPTH_A = "16384" *)
(* C_WRITE_DEPTH_B = "16384" *)
(* C_WRITE_MODE_A = "WRITE_FIRST" *)
(* C_WRITE_MODE_B = "WRITE_FIRST" *)
(* C_WRITE_WIDTH_A = "16" *)
(* C_WRITE_WIDTH_B = "16" *)
(* C_XDEVICEFAMILY = "zynq" *)
(* downgradeipidentifiedwarnings = "yes" *)
system_vga_hessian_1_0_blk_mem_gen_v8_3_5 U0
(.addra(addra),
.addrb(addrb),
.clka(clka),
.clkb(clkb),
.dbiterr(NLW_U0_dbiterr_UNCONNECTED),
.deepsleep(1'b0),
.dina(dina),
.dinb(dinb),
.douta(douta),
.doutb(doutb),
.eccpipece(1'b0),
.ena(ena),
.enb(enb),
.injectdbiterr(1'b0),
.injectsbiterr(1'b0),
.rdaddrecc(NLW_U0_rdaddrecc_UNCONNECTED[13:0]),
.regcea(1'b0),
.regceb(1'b0),
.rsta(1'b0),
.rsta_busy(NLW_U0_rsta_busy_UNCONNECTED),
.rstb(1'b0),
.rstb_busy(NLW_U0_rstb_busy_UNCONNECTED),
.s_aclk(1'b0),
.s_aresetn(1'b0),
.s_axi_araddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_arburst({1'b0,1'b0}),
.s_axi_arid({1'b0,1'b0,1'b0,1'b0}),
.s_axi_arlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_arready(NLW_U0_s_axi_arready_UNCONNECTED),
.s_axi_arsize({1'b0,1'b0,1'b0}),
.s_axi_arvalid(1'b0),
.s_axi_awaddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_awburst({1'b0,1'b0}),
.s_axi_awid({1'b0,1'b0,1'b0,1'b0}),
.s_axi_awlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_awready(NLW_U0_s_axi_awready_UNCONNECTED),
.s_axi_awsize({1'b0,1'b0,1'b0}),
.s_axi_awvalid(1'b0),
.s_axi_bid(NLW_U0_s_axi_bid_UNCONNECTED[3:0]),
.s_axi_bready(1'b0),
.s_axi_bresp(NLW_U0_s_axi_bresp_UNCONNECTED[1:0]),
.s_axi_bvalid(NLW_U0_s_axi_bvalid_UNCONNECTED),
.s_axi_dbiterr(NLW_U0_s_axi_dbiterr_UNCONNECTED),
.s_axi_injectdbiterr(1'b0),
.s_axi_injectsbiterr(1'b0),
.s_axi_rdaddrecc(NLW_U0_s_axi_rdaddrecc_UNCONNECTED[13:0]),
.s_axi_rdata(NLW_U0_s_axi_rdata_UNCONNECTED[15:0]),
.s_axi_rid(NLW_U0_s_axi_rid_UNCONNECTED[3:0]),
.s_axi_rlast(NLW_U0_s_axi_rlast_UNCONNECTED),
.s_axi_rready(1'b0),
.s_axi_rresp(NLW_U0_s_axi_rresp_UNCONNECTED[1:0]),
.s_axi_rvalid(NLW_U0_s_axi_rvalid_UNCONNECTED),
.s_axi_sbiterr(NLW_U0_s_axi_sbiterr_UNCONNECTED),
.s_axi_wdata({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_wlast(1'b0),
.s_axi_wready(NLW_U0_s_axi_wready_UNCONNECTED),
.s_axi_wstrb(1'b0),
.s_axi_wvalid(1'b0),
.sbiterr(NLW_U0_sbiterr_UNCONNECTED),
.shutdown(1'b0),
.sleep(1'b0),
.wea(wea),
.web(web));
endmodule |
module system_vga_hessian_1_0_vga_hessian
(hessian_out,
clk_x16,
rst,
active,
x_addr,
y_addr,
g_in);
output [31:0]hessian_out;
input clk_x16;
input rst;
input active;
input [9:0]x_addr;
input [9:0]y_addr;
input [7:0]g_in;
wire [15:0]A;
wire [15:0]B;
wire Lxx;
wire Lxx0_carry__0_i_1_n_0;
wire Lxx0_carry__0_i_2_n_0;
wire Lxx0_carry__0_i_3_n_0;
wire Lxx0_carry__0_i_4_n_0;
wire Lxx0_carry__0_i_5_n_0;
wire Lxx0_carry__0_i_6_n_0;
wire Lxx0_carry__0_i_7_n_0;
wire Lxx0_carry__0_i_8_n_0;
wire Lxx0_carry__0_n_0;
wire Lxx0_carry__0_n_1;
wire Lxx0_carry__0_n_2;
wire Lxx0_carry__0_n_3;
wire Lxx0_carry__1_i_1_n_0;
wire Lxx0_carry__1_i_2_n_0;
wire Lxx0_carry__1_i_3_n_0;
wire Lxx0_carry__1_i_4_n_0;
wire Lxx0_carry__1_i_5_n_0;
wire Lxx0_carry__1_i_6_n_0;
wire Lxx0_carry__1_i_7_n_0;
wire Lxx0_carry__1_i_8_n_0;
wire Lxx0_carry__1_n_0;
wire Lxx0_carry__1_n_1;
wire Lxx0_carry__1_n_2;
wire Lxx0_carry__1_n_3;
wire Lxx0_carry__2_i_1_n_0;
wire Lxx0_carry__2_i_2_n_0;
wire Lxx0_carry__2_i_3_n_0;
wire Lxx0_carry__2_i_4_n_0;
wire Lxx0_carry__2_i_5_n_0;
wire Lxx0_carry__2_i_6_n_0;
wire Lxx0_carry__2_i_7_n_0;
wire Lxx0_carry__2_n_1;
wire Lxx0_carry__2_n_2;
wire Lxx0_carry__2_n_3;
wire Lxx0_carry_i_1_n_0;
wire Lxx0_carry_i_2_n_0;
wire Lxx0_carry_i_3_n_0;
wire Lxx0_carry_i_4_n_0;
wire Lxx0_carry_i_5_n_0;
wire Lxx0_carry_i_6_n_0;
wire Lxx0_carry_n_0;
wire Lxx0_carry_n_1;
wire Lxx0_carry_n_2;
wire Lxx0_carry_n_3;
wire [15:0]Lxx_0;
wire [15:0]Lxx_00;
wire Lxx_00__1_carry__0_i_10_n_0;
wire Lxx_00__1_carry__0_i_11_n_0;
wire Lxx_00__1_carry__0_i_12_n_0;
wire Lxx_00__1_carry__0_i_1_n_0;
wire Lxx_00__1_carry__0_i_2_n_0;
wire Lxx_00__1_carry__0_i_3_n_0;
wire Lxx_00__1_carry__0_i_4_n_0;
wire Lxx_00__1_carry__0_i_5_n_0;
wire Lxx_00__1_carry__0_i_6_n_0;
wire Lxx_00__1_carry__0_i_7_n_0;
wire Lxx_00__1_carry__0_i_8_n_0;
wire Lxx_00__1_carry__0_i_9_n_0;
wire Lxx_00__1_carry__0_n_0;
wire Lxx_00__1_carry__0_n_1;
wire Lxx_00__1_carry__0_n_2;
wire Lxx_00__1_carry__0_n_3;
wire Lxx_00__1_carry__1_i_10_n_0;
wire Lxx_00__1_carry__1_i_11_n_0;
wire Lxx_00__1_carry__1_i_12_n_0;
wire Lxx_00__1_carry__1_i_1_n_0;
wire Lxx_00__1_carry__1_i_2_n_0;
wire Lxx_00__1_carry__1_i_3_n_0;
wire Lxx_00__1_carry__1_i_4_n_0;
wire Lxx_00__1_carry__1_i_5_n_0;
wire Lxx_00__1_carry__1_i_6_n_0;
wire Lxx_00__1_carry__1_i_7_n_0;
wire Lxx_00__1_carry__1_i_8_n_0;
wire Lxx_00__1_carry__1_i_9_n_0;
wire Lxx_00__1_carry__1_n_0;
wire Lxx_00__1_carry__1_n_1;
wire Lxx_00__1_carry__1_n_2;
wire Lxx_00__1_carry__1_n_3;
wire Lxx_00__1_carry__2_i_10_n_0;
wire Lxx_00__1_carry__2_i_11_n_0;
wire Lxx_00__1_carry__2_i_12_n_0;
wire Lxx_00__1_carry__2_i_1_n_0;
wire Lxx_00__1_carry__2_i_2_n_0;
wire Lxx_00__1_carry__2_i_3_n_0;
wire Lxx_00__1_carry__2_i_4_n_0;
wire Lxx_00__1_carry__2_i_5_n_0;
wire Lxx_00__1_carry__2_i_6_n_0;
wire Lxx_00__1_carry__2_i_7_n_0;
wire Lxx_00__1_carry__2_i_8_n_0;
wire Lxx_00__1_carry__2_i_9_n_0;
wire Lxx_00__1_carry__2_n_1;
wire Lxx_00__1_carry__2_n_2;
wire Lxx_00__1_carry__2_n_3;
wire Lxx_00__1_carry_i_1_n_0;
wire Lxx_00__1_carry_i_2_n_0;
wire Lxx_00__1_carry_i_3_n_0;
wire Lxx_00__1_carry_i_4_n_0;
wire Lxx_00__1_carry_i_5_n_0;
wire Lxx_00__1_carry_i_6_n_0;
wire Lxx_00__1_carry_i_7_n_0;
wire Lxx_00__1_carry_i_8_n_0;
wire Lxx_00__1_carry_i_9_n_0;
wire Lxx_00__1_carry_n_0;
wire Lxx_00__1_carry_n_1;
wire Lxx_00__1_carry_n_2;
wire Lxx_00__1_carry_n_3;
wire [15:1]Lxx_1;
wire [15:0]Lxx_11;
wire Lxx_11__1_carry__0_i_10_n_0;
wire Lxx_11__1_carry__0_i_11_n_0;
wire Lxx_11__1_carry__0_i_12_n_0;
wire Lxx_11__1_carry__0_i_1_n_0;
wire Lxx_11__1_carry__0_i_2_n_0;
wire Lxx_11__1_carry__0_i_3_n_0;
wire Lxx_11__1_carry__0_i_4_n_0;
wire Lxx_11__1_carry__0_i_5_n_0;
wire Lxx_11__1_carry__0_i_6_n_0;
wire Lxx_11__1_carry__0_i_7_n_0;
wire Lxx_11__1_carry__0_i_8_n_0;
wire Lxx_11__1_carry__0_i_9_n_0;
wire Lxx_11__1_carry__0_n_0;
wire Lxx_11__1_carry__0_n_1;
wire Lxx_11__1_carry__0_n_2;
wire Lxx_11__1_carry__0_n_3;
wire Lxx_11__1_carry__1_i_10_n_0;
wire Lxx_11__1_carry__1_i_11_n_0;
wire Lxx_11__1_carry__1_i_12_n_0;
wire Lxx_11__1_carry__1_i_1_n_0;
wire Lxx_11__1_carry__1_i_2_n_0;
wire Lxx_11__1_carry__1_i_3_n_0;
wire Lxx_11__1_carry__1_i_4_n_0;
wire Lxx_11__1_carry__1_i_5_n_0;
wire Lxx_11__1_carry__1_i_6_n_0;
wire Lxx_11__1_carry__1_i_7_n_0;
wire Lxx_11__1_carry__1_i_8_n_0;
wire Lxx_11__1_carry__1_i_9_n_0;
wire Lxx_11__1_carry__1_n_0;
wire Lxx_11__1_carry__1_n_1;
wire Lxx_11__1_carry__1_n_2;
wire Lxx_11__1_carry__1_n_3;
wire Lxx_11__1_carry__2_i_10_n_0;
wire Lxx_11__1_carry__2_i_11_n_0;
wire Lxx_11__1_carry__2_i_12_n_0;
wire Lxx_11__1_carry__2_i_1_n_0;
wire Lxx_11__1_carry__2_i_2_n_0;
wire Lxx_11__1_carry__2_i_3_n_0;
wire Lxx_11__1_carry__2_i_4_n_0;
wire Lxx_11__1_carry__2_i_5_n_0;
wire Lxx_11__1_carry__2_i_6_n_0;
wire Lxx_11__1_carry__2_i_7_n_0;
wire Lxx_11__1_carry__2_i_8_n_0;
wire Lxx_11__1_carry__2_i_9_n_0;
wire Lxx_11__1_carry__2_n_1;
wire Lxx_11__1_carry__2_n_2;
wire Lxx_11__1_carry__2_n_3;
wire Lxx_11__1_carry_i_1_n_0;
wire Lxx_11__1_carry_i_2_n_0;
wire Lxx_11__1_carry_i_3_n_0;
wire Lxx_11__1_carry_i_4_n_0;
wire Lxx_11__1_carry_i_5_n_0;
wire Lxx_11__1_carry_i_6_n_0;
wire Lxx_11__1_carry_i_7_n_0;
wire Lxx_11__1_carry_i_8_n_0;
wire Lxx_11__1_carry_i_9_n_0;
wire Lxx_11__1_carry_n_0;
wire Lxx_11__1_carry_n_1;
wire Lxx_11__1_carry_n_2;
wire Lxx_11__1_carry_n_3;
wire \Lxx_2[15]_i_1_n_0 ;
wire \Lxx_2_reg_n_0_[0] ;
wire \Lxx_2_reg_n_0_[10] ;
wire \Lxx_2_reg_n_0_[11] ;
wire \Lxx_2_reg_n_0_[12] ;
wire \Lxx_2_reg_n_0_[13] ;
wire \Lxx_2_reg_n_0_[14] ;
wire \Lxx_2_reg_n_0_[15] ;
wire \Lxx_2_reg_n_0_[1] ;
wire \Lxx_2_reg_n_0_[2] ;
wire \Lxx_2_reg_n_0_[3] ;
wire \Lxx_2_reg_n_0_[4] ;
wire \Lxx_2_reg_n_0_[5] ;
wire \Lxx_2_reg_n_0_[6] ;
wire \Lxx_2_reg_n_0_[7] ;
wire \Lxx_2_reg_n_0_[8] ;
wire \Lxx_2_reg_n_0_[9] ;
wire Lxy0__1_carry__0_i_10_n_0;
wire Lxy0__1_carry__0_i_11_n_0;
wire Lxy0__1_carry__0_i_12_n_0;
wire Lxy0__1_carry__0_i_1_n_0;
wire Lxy0__1_carry__0_i_2_n_0;
wire Lxy0__1_carry__0_i_3_n_0;
wire Lxy0__1_carry__0_i_4_n_0;
wire Lxy0__1_carry__0_i_5_n_0;
wire Lxy0__1_carry__0_i_6_n_0;
wire Lxy0__1_carry__0_i_7_n_0;
wire Lxy0__1_carry__0_i_8_n_0;
wire Lxy0__1_carry__0_i_9_n_0;
wire Lxy0__1_carry__0_n_0;
wire Lxy0__1_carry__0_n_1;
wire Lxy0__1_carry__0_n_2;
wire Lxy0__1_carry__0_n_3;
wire Lxy0__1_carry__0_n_4;
wire Lxy0__1_carry__0_n_5;
wire Lxy0__1_carry__0_n_6;
wire Lxy0__1_carry__0_n_7;
wire Lxy0__1_carry__1_i_10_n_0;
wire Lxy0__1_carry__1_i_11_n_0;
wire Lxy0__1_carry__1_i_12_n_0;
wire Lxy0__1_carry__1_i_1_n_0;
wire Lxy0__1_carry__1_i_2_n_0;
wire Lxy0__1_carry__1_i_3_n_0;
wire Lxy0__1_carry__1_i_4_n_0;
wire Lxy0__1_carry__1_i_5_n_0;
wire Lxy0__1_carry__1_i_6_n_0;
wire Lxy0__1_carry__1_i_7_n_0;
wire Lxy0__1_carry__1_i_8_n_0;
wire Lxy0__1_carry__1_i_9_n_0;
wire Lxy0__1_carry__1_n_0;
wire Lxy0__1_carry__1_n_1;
wire Lxy0__1_carry__1_n_2;
wire Lxy0__1_carry__1_n_3;
wire Lxy0__1_carry__1_n_4;
wire Lxy0__1_carry__1_n_5;
wire Lxy0__1_carry__1_n_6;
wire Lxy0__1_carry__1_n_7;
wire Lxy0__1_carry__2_i_10_n_0;
wire Lxy0__1_carry__2_i_11_n_0;
wire Lxy0__1_carry__2_i_12_n_0;
wire Lxy0__1_carry__2_i_1_n_0;
wire Lxy0__1_carry__2_i_2_n_0;
wire Lxy0__1_carry__2_i_3_n_0;
wire Lxy0__1_carry__2_i_4_n_0;
wire Lxy0__1_carry__2_i_5_n_0;
wire Lxy0__1_carry__2_i_6_n_0;
wire Lxy0__1_carry__2_i_7_n_0;
wire Lxy0__1_carry__2_i_8_n_0;
wire Lxy0__1_carry__2_i_9_n_0;
wire Lxy0__1_carry__2_n_1;
wire Lxy0__1_carry__2_n_2;
wire Lxy0__1_carry__2_n_3;
wire Lxy0__1_carry__2_n_4;
wire Lxy0__1_carry__2_n_5;
wire Lxy0__1_carry__2_n_6;
wire Lxy0__1_carry__2_n_7;
wire Lxy0__1_carry_i_10_n_0;
wire Lxy0__1_carry_i_1_n_0;
wire Lxy0__1_carry_i_2_n_0;
wire Lxy0__1_carry_i_3_n_0;
wire Lxy0__1_carry_i_4_n_0;
wire Lxy0__1_carry_i_5_n_0;
wire Lxy0__1_carry_i_6_n_0;
wire Lxy0__1_carry_i_7_n_0;
wire Lxy0__1_carry_i_8_n_0;
wire Lxy0__1_carry_i_9_n_0;
wire Lxy0__1_carry_n_0;
wire Lxy0__1_carry_n_1;
wire Lxy0__1_carry_n_2;
wire Lxy0__1_carry_n_3;
wire Lxy0__1_carry_n_4;
wire Lxy0__1_carry_n_5;
wire Lxy0__1_carry_n_6;
wire Lxy0__1_carry_n_7;
wire \Lxy_0[15]_i_1_n_0 ;
wire \Lxy_0_reg_n_0_[0] ;
wire \Lxy_0_reg_n_0_[10] ;
wire \Lxy_0_reg_n_0_[11] ;
wire \Lxy_0_reg_n_0_[12] ;
wire \Lxy_0_reg_n_0_[13] ;
wire \Lxy_0_reg_n_0_[14] ;
wire \Lxy_0_reg_n_0_[15] ;
wire \Lxy_0_reg_n_0_[1] ;
wire \Lxy_0_reg_n_0_[2] ;
wire \Lxy_0_reg_n_0_[3] ;
wire \Lxy_0_reg_n_0_[4] ;
wire \Lxy_0_reg_n_0_[5] ;
wire \Lxy_0_reg_n_0_[6] ;
wire \Lxy_0_reg_n_0_[7] ;
wire \Lxy_0_reg_n_0_[8] ;
wire \Lxy_0_reg_n_0_[9] ;
wire Lxy_1;
wire \Lxy_1_reg_n_0_[0] ;
wire \Lxy_1_reg_n_0_[10] ;
wire \Lxy_1_reg_n_0_[11] ;
wire \Lxy_1_reg_n_0_[12] ;
wire \Lxy_1_reg_n_0_[13] ;
wire \Lxy_1_reg_n_0_[14] ;
wire \Lxy_1_reg_n_0_[15] ;
wire \Lxy_1_reg_n_0_[1] ;
wire \Lxy_1_reg_n_0_[2] ;
wire \Lxy_1_reg_n_0_[3] ;
wire \Lxy_1_reg_n_0_[4] ;
wire \Lxy_1_reg_n_0_[5] ;
wire \Lxy_1_reg_n_0_[6] ;
wire \Lxy_1_reg_n_0_[7] ;
wire \Lxy_1_reg_n_0_[8] ;
wire \Lxy_1_reg_n_0_[9] ;
wire [15:0]Lxy_2;
wire [15:0]Lxy_3;
wire Lyy0_carry__0_i_1_n_0;
wire Lyy0_carry__0_i_2_n_0;
wire Lyy0_carry__0_i_3_n_0;
wire Lyy0_carry__0_i_4_n_0;
wire Lyy0_carry__0_i_5_n_0;
wire Lyy0_carry__0_i_6_n_0;
wire Lyy0_carry__0_i_7_n_0;
wire Lyy0_carry__0_i_8_n_0;
wire Lyy0_carry__0_n_0;
wire Lyy0_carry__0_n_1;
wire Lyy0_carry__0_n_2;
wire Lyy0_carry__0_n_3;
wire Lyy0_carry__1_i_1_n_0;
wire Lyy0_carry__1_i_2_n_0;
wire Lyy0_carry__1_i_3_n_0;
wire Lyy0_carry__1_i_4_n_0;
wire Lyy0_carry__1_i_5_n_0;
wire Lyy0_carry__1_i_6_n_0;
wire Lyy0_carry__1_i_7_n_0;
wire Lyy0_carry__1_i_8_n_0;
wire Lyy0_carry__1_n_0;
wire Lyy0_carry__1_n_1;
wire Lyy0_carry__1_n_2;
wire Lyy0_carry__1_n_3;
wire Lyy0_carry__2_i_1_n_0;
wire Lyy0_carry__2_i_2_n_0;
wire Lyy0_carry__2_i_3_n_0;
wire Lyy0_carry__2_i_4_n_0;
wire Lyy0_carry__2_i_5_n_0;
wire Lyy0_carry__2_i_6_n_0;
wire Lyy0_carry__2_i_7_n_0;
wire Lyy0_carry__2_n_1;
wire Lyy0_carry__2_n_2;
wire Lyy0_carry__2_n_3;
wire Lyy0_carry_i_1_n_0;
wire Lyy0_carry_i_2_n_0;
wire Lyy0_carry_i_3_n_0;
wire Lyy0_carry_i_4_n_0;
wire Lyy0_carry_i_5_n_0;
wire Lyy0_carry_i_6_n_0;
wire Lyy0_carry_n_0;
wire Lyy0_carry_n_1;
wire Lyy0_carry_n_2;
wire Lyy0_carry_n_3;
wire Lyy_0;
wire \Lyy_0_reg_n_0_[0] ;
wire \Lyy_0_reg_n_0_[10] ;
wire \Lyy_0_reg_n_0_[11] ;
wire \Lyy_0_reg_n_0_[12] ;
wire \Lyy_0_reg_n_0_[13] ;
wire \Lyy_0_reg_n_0_[14] ;
wire \Lyy_0_reg_n_0_[15] ;
wire \Lyy_0_reg_n_0_[1] ;
wire \Lyy_0_reg_n_0_[2] ;
wire \Lyy_0_reg_n_0_[3] ;
wire \Lyy_0_reg_n_0_[4] ;
wire \Lyy_0_reg_n_0_[5] ;
wire \Lyy_0_reg_n_0_[6] ;
wire \Lyy_0_reg_n_0_[7] ;
wire \Lyy_0_reg_n_0_[8] ;
wire \Lyy_0_reg_n_0_[9] ;
wire [15:1]Lyy_1;
wire [15:0]Lyy_20;
wire Lyy_20__1_carry__0_i_10_n_0;
wire Lyy_20__1_carry__0_i_11_n_0;
wire Lyy_20__1_carry__0_i_12_n_0;
wire Lyy_20__1_carry__0_i_1_n_0;
wire Lyy_20__1_carry__0_i_2_n_0;
wire Lyy_20__1_carry__0_i_3_n_0;
wire Lyy_20__1_carry__0_i_4_n_0;
wire Lyy_20__1_carry__0_i_5_n_0;
wire Lyy_20__1_carry__0_i_6_n_0;
wire Lyy_20__1_carry__0_i_7_n_0;
wire Lyy_20__1_carry__0_i_8_n_0;
wire Lyy_20__1_carry__0_i_9_n_0;
wire Lyy_20__1_carry__0_n_0;
wire Lyy_20__1_carry__0_n_1;
wire Lyy_20__1_carry__0_n_2;
wire Lyy_20__1_carry__0_n_3;
wire Lyy_20__1_carry__1_i_10_n_0;
wire Lyy_20__1_carry__1_i_11_n_0;
wire Lyy_20__1_carry__1_i_12_n_0;
wire Lyy_20__1_carry__1_i_1_n_0;
wire Lyy_20__1_carry__1_i_2_n_0;
wire Lyy_20__1_carry__1_i_3_n_0;
wire Lyy_20__1_carry__1_i_4_n_0;
wire Lyy_20__1_carry__1_i_5_n_0;
wire Lyy_20__1_carry__1_i_6_n_0;
wire Lyy_20__1_carry__1_i_7_n_0;
wire Lyy_20__1_carry__1_i_8_n_0;
wire Lyy_20__1_carry__1_i_9_n_0;
wire Lyy_20__1_carry__1_n_0;
wire Lyy_20__1_carry__1_n_1;
wire Lyy_20__1_carry__1_n_2;
wire Lyy_20__1_carry__1_n_3;
wire Lyy_20__1_carry__2_i_10_n_0;
wire Lyy_20__1_carry__2_i_11_n_0;
wire Lyy_20__1_carry__2_i_1_n_0;
wire Lyy_20__1_carry__2_i_2_n_0;
wire Lyy_20__1_carry__2_i_3_n_0;
wire Lyy_20__1_carry__2_i_4_n_0;
wire Lyy_20__1_carry__2_i_5_n_0;
wire Lyy_20__1_carry__2_i_6_n_0;
wire Lyy_20__1_carry__2_i_7_n_0;
wire Lyy_20__1_carry__2_i_8_n_0;
wire Lyy_20__1_carry__2_i_9_n_0;
wire Lyy_20__1_carry__2_n_1;
wire Lyy_20__1_carry__2_n_2;
wire Lyy_20__1_carry__2_n_3;
wire Lyy_20__1_carry_i_1_n_0;
wire Lyy_20__1_carry_i_2_n_0;
wire Lyy_20__1_carry_i_3_n_0;
wire Lyy_20__1_carry_i_4_n_0;
wire Lyy_20__1_carry_i_5_n_0;
wire Lyy_20__1_carry_i_6_n_0;
wire Lyy_20__1_carry_i_7_n_0;
wire Lyy_20__1_carry_i_8_n_0;
wire Lyy_20__1_carry_i_9_n_0;
wire Lyy_20__1_carry_n_0;
wire Lyy_20__1_carry_n_1;
wire Lyy_20__1_carry_n_2;
wire Lyy_20__1_carry_n_3;
wire \Lyy_2[15]_i_1_n_0 ;
wire [15:0]Lyy_2_bottom_left;
wire [15:0]Lyy_2_bottom_right;
wire [15:0]Lyy_2_bottom_right01_out;
wire Lyy_2_bottom_right0__0_carry__0_i_10_n_0;
wire Lyy_2_bottom_right0__0_carry__0_i_11_n_0;
wire Lyy_2_bottom_right0__0_carry__0_i_12_n_0;
wire Lyy_2_bottom_right0__0_carry__0_i_1_n_0;
wire Lyy_2_bottom_right0__0_carry__0_i_2_n_0;
wire Lyy_2_bottom_right0__0_carry__0_i_3_n_0;
wire Lyy_2_bottom_right0__0_carry__0_i_4_n_0;
wire Lyy_2_bottom_right0__0_carry__0_i_5_n_0;
wire Lyy_2_bottom_right0__0_carry__0_i_6_n_0;
wire Lyy_2_bottom_right0__0_carry__0_i_7_n_0;
wire Lyy_2_bottom_right0__0_carry__0_i_8_n_0;
wire Lyy_2_bottom_right0__0_carry__0_i_9_n_0;
wire Lyy_2_bottom_right0__0_carry__0_n_0;
wire Lyy_2_bottom_right0__0_carry__0_n_1;
wire Lyy_2_bottom_right0__0_carry__0_n_2;
wire Lyy_2_bottom_right0__0_carry__0_n_3;
wire Lyy_2_bottom_right0__0_carry__1_i_10_n_0;
wire Lyy_2_bottom_right0__0_carry__1_i_11_n_0;
wire Lyy_2_bottom_right0__0_carry__1_i_12_n_0;
wire Lyy_2_bottom_right0__0_carry__1_i_1_n_0;
wire Lyy_2_bottom_right0__0_carry__1_i_2_n_0;
wire Lyy_2_bottom_right0__0_carry__1_i_3_n_0;
wire Lyy_2_bottom_right0__0_carry__1_i_4_n_0;
wire Lyy_2_bottom_right0__0_carry__1_i_5_n_0;
wire Lyy_2_bottom_right0__0_carry__1_i_6_n_0;
wire Lyy_2_bottom_right0__0_carry__1_i_7_n_0;
wire Lyy_2_bottom_right0__0_carry__1_i_8_n_0;
wire Lyy_2_bottom_right0__0_carry__1_i_9_n_0;
wire Lyy_2_bottom_right0__0_carry__1_n_0;
wire Lyy_2_bottom_right0__0_carry__1_n_1;
wire Lyy_2_bottom_right0__0_carry__1_n_2;
wire Lyy_2_bottom_right0__0_carry__1_n_3;
wire Lyy_2_bottom_right0__0_carry__2_i_10_n_0;
wire Lyy_2_bottom_right0__0_carry__2_i_11_n_0;
wire Lyy_2_bottom_right0__0_carry__2_i_12_n_0;
wire Lyy_2_bottom_right0__0_carry__2_i_1_n_0;
wire Lyy_2_bottom_right0__0_carry__2_i_2_n_0;
wire Lyy_2_bottom_right0__0_carry__2_i_3_n_0;
wire Lyy_2_bottom_right0__0_carry__2_i_4_n_0;
wire Lyy_2_bottom_right0__0_carry__2_i_5_n_0;
wire Lyy_2_bottom_right0__0_carry__2_i_6_n_0;
wire Lyy_2_bottom_right0__0_carry__2_i_7_n_0;
wire Lyy_2_bottom_right0__0_carry__2_i_8_n_0;
wire Lyy_2_bottom_right0__0_carry__2_i_9_n_0;
wire Lyy_2_bottom_right0__0_carry__2_n_1;
wire Lyy_2_bottom_right0__0_carry__2_n_2;
wire Lyy_2_bottom_right0__0_carry__2_n_3;
wire Lyy_2_bottom_right0__0_carry_i_10_n_0;
wire Lyy_2_bottom_right0__0_carry_i_11_n_0;
wire Lyy_2_bottom_right0__0_carry_i_1_n_0;
wire Lyy_2_bottom_right0__0_carry_i_2_n_0;
wire Lyy_2_bottom_right0__0_carry_i_3_n_0;
wire Lyy_2_bottom_right0__0_carry_i_4_n_0;
wire Lyy_2_bottom_right0__0_carry_i_5_n_0;
wire Lyy_2_bottom_right0__0_carry_i_6_n_0;
wire Lyy_2_bottom_right0__0_carry_i_7_n_0;
wire Lyy_2_bottom_right0__0_carry_i_8_n_0;
wire Lyy_2_bottom_right0__0_carry_i_9_n_0;
wire Lyy_2_bottom_right0__0_carry_n_0;
wire Lyy_2_bottom_right0__0_carry_n_1;
wire Lyy_2_bottom_right0__0_carry_n_2;
wire Lyy_2_bottom_right0__0_carry_n_3;
wire \Lyy_2_reg_n_0_[0] ;
wire \Lyy_2_reg_n_0_[10] ;
wire \Lyy_2_reg_n_0_[11] ;
wire \Lyy_2_reg_n_0_[12] ;
wire \Lyy_2_reg_n_0_[13] ;
wire \Lyy_2_reg_n_0_[14] ;
wire \Lyy_2_reg_n_0_[15] ;
wire \Lyy_2_reg_n_0_[1] ;
wire \Lyy_2_reg_n_0_[2] ;
wire \Lyy_2_reg_n_0_[3] ;
wire \Lyy_2_reg_n_0_[4] ;
wire \Lyy_2_reg_n_0_[5] ;
wire \Lyy_2_reg_n_0_[6] ;
wire \Lyy_2_reg_n_0_[7] ;
wire \Lyy_2_reg_n_0_[8] ;
wire \Lyy_2_reg_n_0_[9] ;
wire [15:0]Lyy_2_top_left;
wire [15:0]Lyy_2_top_right;
wire active;
wire addr_0;
wire \addr_0[0]_i_1_n_0 ;
wire \addr_0[10]_i_1_n_0 ;
wire \addr_0[11]_i_1_n_0 ;
wire \addr_0[12]_i_1_n_0 ;
wire \addr_0[13]_i_2_n_0 ;
wire \addr_0[1]_i_1_n_0 ;
wire \addr_0[2]_i_1_n_0 ;
wire \addr_0[3]_i_1_n_0 ;
wire \addr_0[4]_i_1_n_0 ;
wire \addr_0[5]_i_1_n_0 ;
wire \addr_0[6]_i_1_n_0 ;
wire \addr_0[7]_i_1_n_0 ;
wire \addr_0[8]_i_1_n_0 ;
wire \addr_0[9]_i_1_n_0 ;
wire \addr_0_reg_n_0_[0] ;
wire \addr_0_reg_n_0_[10] ;
wire \addr_0_reg_n_0_[11] ;
wire \addr_0_reg_n_0_[12] ;
wire \addr_0_reg_n_0_[13] ;
wire \addr_0_reg_n_0_[1] ;
wire \addr_0_reg_n_0_[2] ;
wire \addr_0_reg_n_0_[3] ;
wire \addr_0_reg_n_0_[4] ;
wire \addr_0_reg_n_0_[5] ;
wire \addr_0_reg_n_0_[6] ;
wire \addr_0_reg_n_0_[7] ;
wire \addr_0_reg_n_0_[8] ;
wire \addr_0_reg_n_0_[9] ;
wire [13:0]addr_1;
wire \addr_1[0]_i_1_n_0 ;
wire \addr_1[10]_i_1_n_0 ;
wire \addr_1[11]_i_1_n_0 ;
wire \addr_1[12]_i_1_n_0 ;
wire \addr_1[13]_i_1_n_0 ;
wire \addr_1[1]_i_1_n_0 ;
wire \addr_1[2]_i_1_n_0 ;
wire \addr_1[3]_i_1_n_0 ;
wire \addr_1[4]_i_1_n_0 ;
wire \addr_1[5]_i_1_n_0 ;
wire \addr_1[6]_i_1_n_0 ;
wire \addr_1[7]_i_1_n_0 ;
wire \addr_1[8]_i_1_n_0 ;
wire \addr_1[9]_i_1_n_0 ;
wire bottom_left_0;
wire \bottom_left_0_reg_n_0_[0] ;
wire \bottom_left_0_reg_n_0_[10] ;
wire \bottom_left_0_reg_n_0_[11] ;
wire \bottom_left_0_reg_n_0_[12] ;
wire \bottom_left_0_reg_n_0_[13] ;
wire \bottom_left_0_reg_n_0_[14] ;
wire \bottom_left_0_reg_n_0_[15] ;
wire \bottom_left_0_reg_n_0_[1] ;
wire \bottom_left_0_reg_n_0_[2] ;
wire \bottom_left_0_reg_n_0_[3] ;
wire \bottom_left_0_reg_n_0_[4] ;
wire \bottom_left_0_reg_n_0_[5] ;
wire \bottom_left_0_reg_n_0_[6] ;
wire \bottom_left_0_reg_n_0_[7] ;
wire \bottom_left_0_reg_n_0_[8] ;
wire \bottom_left_0_reg_n_0_[9] ;
wire [15:0]bottom_left_1;
wire \bottom_right_0[0]_i_2_n_0 ;
wire \bottom_right_0[10]_i_2_n_0 ;
wire \bottom_right_0[11]_i_2_n_0 ;
wire \bottom_right_0[12]_i_2_n_0 ;
wire \bottom_right_0[13]_i_2_n_0 ;
wire \bottom_right_0[14]_i_2_n_0 ;
wire \bottom_right_0[15]_i_1_n_0 ;
wire \bottom_right_0[15]_i_3_n_0 ;
wire \bottom_right_0[15]_i_4_n_0 ;
wire \bottom_right_0[15]_i_5_n_0 ;
wire \bottom_right_0[1]_i_2_n_0 ;
wire \bottom_right_0[2]_i_2_n_0 ;
wire \bottom_right_0[3]_i_2_n_0 ;
wire \bottom_right_0[4]_i_2_n_0 ;
wire \bottom_right_0[5]_i_2_n_0 ;
wire \bottom_right_0[6]_i_2_n_0 ;
wire \bottom_right_0[7]_i_2_n_0 ;
wire \bottom_right_0[8]_i_2_n_0 ;
wire \bottom_right_0[9]_i_2_n_0 ;
wire \bottom_right_0_reg_n_0_[0] ;
wire \bottom_right_0_reg_n_0_[10] ;
wire \bottom_right_0_reg_n_0_[11] ;
wire \bottom_right_0_reg_n_0_[12] ;
wire \bottom_right_0_reg_n_0_[13] ;
wire \bottom_right_0_reg_n_0_[14] ;
wire \bottom_right_0_reg_n_0_[15] ;
wire \bottom_right_0_reg_n_0_[1] ;
wire \bottom_right_0_reg_n_0_[2] ;
wire \bottom_right_0_reg_n_0_[3] ;
wire \bottom_right_0_reg_n_0_[4] ;
wire \bottom_right_0_reg_n_0_[5] ;
wire \bottom_right_0_reg_n_0_[6] ;
wire \bottom_right_0_reg_n_0_[7] ;
wire \bottom_right_0_reg_n_0_[8] ;
wire \bottom_right_0_reg_n_0_[9] ;
wire bottom_right_1;
wire \bottom_right_1[0]_i_1_n_0 ;
wire \bottom_right_1[10]_i_1_n_0 ;
wire \bottom_right_1[11]_i_1_n_0 ;
wire \bottom_right_1[12]_i_1_n_0 ;
wire \bottom_right_1[13]_i_1_n_0 ;
wire \bottom_right_1[14]_i_1_n_0 ;
wire \bottom_right_1[15]_i_1_n_0 ;
wire \bottom_right_1[1]_i_1_n_0 ;
wire \bottom_right_1[2]_i_1_n_0 ;
wire \bottom_right_1[3]_i_1_n_0 ;
wire \bottom_right_1[4]_i_1_n_0 ;
wire \bottom_right_1[5]_i_1_n_0 ;
wire \bottom_right_1[6]_i_1_n_0 ;
wire \bottom_right_1[7]_i_1_n_0 ;
wire \bottom_right_1[8]_i_1_n_0 ;
wire \bottom_right_1[9]_i_1_n_0 ;
wire \bottom_right_1_reg_n_0_[0] ;
wire \bottom_right_1_reg_n_0_[10] ;
wire \bottom_right_1_reg_n_0_[11] ;
wire \bottom_right_1_reg_n_0_[12] ;
wire \bottom_right_1_reg_n_0_[13] ;
wire \bottom_right_1_reg_n_0_[14] ;
wire \bottom_right_1_reg_n_0_[15] ;
wire \bottom_right_1_reg_n_0_[1] ;
wire \bottom_right_1_reg_n_0_[2] ;
wire \bottom_right_1_reg_n_0_[3] ;
wire \bottom_right_1_reg_n_0_[4] ;
wire \bottom_right_1_reg_n_0_[5] ;
wire \bottom_right_1_reg_n_0_[6] ;
wire \bottom_right_1_reg_n_0_[7] ;
wire \bottom_right_1_reg_n_0_[8] ;
wire \bottom_right_1_reg_n_0_[9] ;
wire \cache[10]_5 ;
wire \cache[9][15]_i_1_n_0 ;
wire [15:0]\cache_reg[0]_4 ;
wire [15:0]\cache_reg[10]_3 ;
wire \cache_reg[2][0]_srl2___U0_cache_reg_r_0_n_0 ;
wire \cache_reg[2][10]_srl2___U0_cache_reg_r_0_n_0 ;
wire \cache_reg[2][11]_srl2___U0_cache_reg_r_0_n_0 ;
wire \cache_reg[2][12]_srl2___U0_cache_reg_r_0_n_0 ;
wire \cache_reg[2][13]_srl2___U0_cache_reg_r_0_n_0 ;
wire \cache_reg[2][14]_srl2___U0_cache_reg_r_0_n_0 ;
wire \cache_reg[2][15]_srl2___U0_cache_reg_r_0_n_0 ;
wire \cache_reg[2][1]_srl2___U0_cache_reg_r_0_n_0 ;
wire \cache_reg[2][2]_srl2___U0_cache_reg_r_0_n_0 ;
wire \cache_reg[2][3]_srl2___U0_cache_reg_r_0_n_0 ;
wire \cache_reg[2][4]_srl2___U0_cache_reg_r_0_n_0 ;
wire \cache_reg[2][5]_srl2___U0_cache_reg_r_0_n_0 ;
wire \cache_reg[2][6]_srl2___U0_cache_reg_r_0_n_0 ;
wire \cache_reg[2][7]_srl2___U0_cache_reg_r_0_n_0 ;
wire \cache_reg[2][8]_srl2___U0_cache_reg_r_0_n_0 ;
wire \cache_reg[2][9]_srl2___U0_cache_reg_r_0_n_0 ;
wire \cache_reg[3][0]_U0_cache_reg_r_1_n_0 ;
wire \cache_reg[3][10]_U0_cache_reg_r_1_n_0 ;
wire \cache_reg[3][11]_U0_cache_reg_r_1_n_0 ;
wire \cache_reg[3][12]_U0_cache_reg_r_1_n_0 ;
wire \cache_reg[3][13]_U0_cache_reg_r_1_n_0 ;
wire \cache_reg[3][14]_U0_cache_reg_r_1_n_0 ;
wire \cache_reg[3][15]_U0_cache_reg_r_1_n_0 ;
wire \cache_reg[3][1]_U0_cache_reg_r_1_n_0 ;
wire \cache_reg[3][2]_U0_cache_reg_r_1_n_0 ;
wire \cache_reg[3][3]_U0_cache_reg_r_1_n_0 ;
wire \cache_reg[3][4]_U0_cache_reg_r_1_n_0 ;
wire \cache_reg[3][5]_U0_cache_reg_r_1_n_0 ;
wire \cache_reg[3][6]_U0_cache_reg_r_1_n_0 ;
wire \cache_reg[3][7]_U0_cache_reg_r_1_n_0 ;
wire \cache_reg[3][8]_U0_cache_reg_r_1_n_0 ;
wire \cache_reg[3][9]_U0_cache_reg_r_1_n_0 ;
wire [15:0]\cache_reg[4]_0 ;
wire \cache_reg[6][0]_srl2___U0_cache_reg_r_0_n_0 ;
wire \cache_reg[6][10]_srl2___U0_cache_reg_r_0_n_0 ;
wire \cache_reg[6][11]_srl2___U0_cache_reg_r_0_n_0 ;
wire \cache_reg[6][12]_srl2___U0_cache_reg_r_0_n_0 ;
wire \cache_reg[6][13]_srl2___U0_cache_reg_r_0_n_0 ;
wire \cache_reg[6][14]_srl2___U0_cache_reg_r_0_n_0 ;
wire \cache_reg[6][15]_srl2___U0_cache_reg_r_0_n_0 ;
wire \cache_reg[6][1]_srl2___U0_cache_reg_r_0_n_0 ;
wire \cache_reg[6][2]_srl2___U0_cache_reg_r_0_n_0 ;
wire \cache_reg[6][3]_srl2___U0_cache_reg_r_0_n_0 ;
wire \cache_reg[6][4]_srl2___U0_cache_reg_r_0_n_0 ;
wire \cache_reg[6][5]_srl2___U0_cache_reg_r_0_n_0 ;
wire \cache_reg[6][6]_srl2___U0_cache_reg_r_0_n_0 ;
wire \cache_reg[6][7]_srl2___U0_cache_reg_r_0_n_0 ;
wire \cache_reg[6][8]_srl2___U0_cache_reg_r_0_n_0 ;
wire \cache_reg[6][9]_srl2___U0_cache_reg_r_0_n_0 ;
wire \cache_reg[7][0]_U0_cache_reg_r_1_n_0 ;
wire \cache_reg[7][10]_U0_cache_reg_r_1_n_0 ;
wire \cache_reg[7][11]_U0_cache_reg_r_1_n_0 ;
wire \cache_reg[7][12]_U0_cache_reg_r_1_n_0 ;
wire \cache_reg[7][13]_U0_cache_reg_r_1_n_0 ;
wire \cache_reg[7][14]_U0_cache_reg_r_1_n_0 ;
wire \cache_reg[7][15]_U0_cache_reg_r_1_n_0 ;
wire \cache_reg[7][1]_U0_cache_reg_r_1_n_0 ;
wire \cache_reg[7][2]_U0_cache_reg_r_1_n_0 ;
wire \cache_reg[7][3]_U0_cache_reg_r_1_n_0 ;
wire \cache_reg[7][4]_U0_cache_reg_r_1_n_0 ;
wire \cache_reg[7][5]_U0_cache_reg_r_1_n_0 ;
wire \cache_reg[7][6]_U0_cache_reg_r_1_n_0 ;
wire \cache_reg[7][7]_U0_cache_reg_r_1_n_0 ;
wire \cache_reg[7][8]_U0_cache_reg_r_1_n_0 ;
wire \cache_reg[7][9]_U0_cache_reg_r_1_n_0 ;
wire [15:0]\cache_reg[8]_1 ;
wire [15:0]\cache_reg[9]_2 ;
wire cache_reg_gate__0_n_0;
wire cache_reg_gate__10_n_0;
wire cache_reg_gate__11_n_0;
wire cache_reg_gate__12_n_0;
wire cache_reg_gate__13_n_0;
wire cache_reg_gate__14_n_0;
wire cache_reg_gate__15_n_0;
wire cache_reg_gate__16_n_0;
wire cache_reg_gate__17_n_0;
wire cache_reg_gate__18_n_0;
wire cache_reg_gate__19_n_0;
wire cache_reg_gate__1_n_0;
wire cache_reg_gate__20_n_0;
wire cache_reg_gate__21_n_0;
wire cache_reg_gate__22_n_0;
wire cache_reg_gate__23_n_0;
wire cache_reg_gate__24_n_0;
wire cache_reg_gate__25_n_0;
wire cache_reg_gate__26_n_0;
wire cache_reg_gate__27_n_0;
wire cache_reg_gate__28_n_0;
wire cache_reg_gate__29_n_0;
wire cache_reg_gate__2_n_0;
wire cache_reg_gate__30_n_0;
wire cache_reg_gate__3_n_0;
wire cache_reg_gate__4_n_0;
wire cache_reg_gate__5_n_0;
wire cache_reg_gate__6_n_0;
wire cache_reg_gate__7_n_0;
wire cache_reg_gate__8_n_0;
wire cache_reg_gate__9_n_0;
wire cache_reg_gate_n_0;
wire cache_reg_r_0_n_0;
wire cache_reg_r_1_n_0;
wire cache_reg_r_n_0;
wire clk_x16;
wire compute_addr_0;
wire \compute_addr_0[0]_i_1_n_0 ;
wire \compute_addr_0[10]_i_1_n_0 ;
wire \compute_addr_0[10]_i_2_n_0 ;
wire \compute_addr_0[11]_i_1_n_0 ;
wire \compute_addr_0[11]_i_2_n_0 ;
wire \compute_addr_0[11]_i_3_n_0 ;
wire \compute_addr_0[12]_i_1_n_0 ;
wire \compute_addr_0[12]_i_2_n_0 ;
wire \compute_addr_0[13]_i_2_n_0 ;
wire \compute_addr_0[13]_i_3_n_0 ;
wire \compute_addr_0[1]_i_1_n_0 ;
wire \compute_addr_0[2]_i_1_n_0 ;
wire \compute_addr_0[3]_i_1_n_0 ;
wire \compute_addr_0[4]_i_1_n_0 ;
wire \compute_addr_0[5]_i_1_n_0 ;
wire \compute_addr_0[6]_i_1_n_0 ;
wire \compute_addr_0[7]_i_1_n_0 ;
wire \compute_addr_0[8]_i_1_n_0 ;
wire \compute_addr_0[9]_i_1_n_0 ;
wire \compute_addr_0_reg_n_0_[0] ;
wire \compute_addr_0_reg_n_0_[10] ;
wire \compute_addr_0_reg_n_0_[11] ;
wire \compute_addr_0_reg_n_0_[12] ;
wire \compute_addr_0_reg_n_0_[13] ;
wire \compute_addr_0_reg_n_0_[1] ;
wire \compute_addr_0_reg_n_0_[2] ;
wire \compute_addr_0_reg_n_0_[3] ;
wire \compute_addr_0_reg_n_0_[4] ;
wire \compute_addr_0_reg_n_0_[5] ;
wire \compute_addr_0_reg_n_0_[6] ;
wire \compute_addr_0_reg_n_0_[7] ;
wire \compute_addr_0_reg_n_0_[8] ;
wire \compute_addr_0_reg_n_0_[9] ;
wire [13:0]compute_addr_1;
wire \compute_addr_1[0]_i_1_n_0 ;
wire \compute_addr_1[10]_i_1_n_0 ;
wire \compute_addr_1[10]_i_2_n_0 ;
wire \compute_addr_1[11]_i_1_n_0 ;
wire \compute_addr_1[11]_i_2_n_0 ;
wire \compute_addr_1[12]_i_1_n_0 ;
wire \compute_addr_1[12]_i_2_n_0 ;
wire \compute_addr_1[13]_i_1_n_0 ;
wire \compute_addr_1[13]_i_2_n_0 ;
wire \compute_addr_1[1]_i_1_n_0 ;
wire \compute_addr_1[2]_i_1_n_0 ;
wire \compute_addr_1[3]_i_1_n_0 ;
wire \compute_addr_1[4]_i_1_n_0 ;
wire \compute_addr_1[5]_i_1_n_0 ;
wire \compute_addr_1[6]_i_1_n_0 ;
wire \compute_addr_1[7]_i_1_n_0 ;
wire \compute_addr_1[8]_i_1_n_0 ;
wire \compute_addr_1[9]_i_1_n_0 ;
wire compute_addr_2;
wire \compute_addr_2[10]_i_1_n_0 ;
wire \compute_addr_2[10]_i_2_n_0 ;
wire \compute_addr_2[11]_i_1_n_0 ;
wire \compute_addr_2[11]_i_2_n_0 ;
wire \compute_addr_2[12]_i_1_n_0 ;
wire \compute_addr_2[12]_i_2_n_0 ;
wire \compute_addr_2[13]_i_2_n_0 ;
wire \compute_addr_2[13]_i_3_n_0 ;
wire \compute_addr_2[13]_i_4_n_0 ;
wire \compute_addr_2_reg_n_0_[0] ;
wire \compute_addr_2_reg_n_0_[10] ;
wire \compute_addr_2_reg_n_0_[11] ;
wire \compute_addr_2_reg_n_0_[12] ;
wire \compute_addr_2_reg_n_0_[13] ;
wire \compute_addr_2_reg_n_0_[1] ;
wire \compute_addr_2_reg_n_0_[2] ;
wire \compute_addr_2_reg_n_0_[3] ;
wire \compute_addr_2_reg_n_0_[4] ;
wire \compute_addr_2_reg_n_0_[5] ;
wire \compute_addr_2_reg_n_0_[6] ;
wire \compute_addr_2_reg_n_0_[7] ;
wire \compute_addr_2_reg_n_0_[8] ;
wire \compute_addr_2_reg_n_0_[9] ;
wire [13:0]compute_addr_3;
wire \compute_addr_3[0]_i_1_n_0 ;
wire \compute_addr_3[10]_i_1_n_0 ;
wire \compute_addr_3[10]_i_2_n_0 ;
wire \compute_addr_3[11]_i_1_n_0 ;
wire \compute_addr_3[11]_i_2_n_0 ;
wire \compute_addr_3[12]_i_1_n_0 ;
wire \compute_addr_3[12]_i_2_n_0 ;
wire \compute_addr_3[13]_i_1_n_0 ;
wire \compute_addr_3[13]_i_2_n_0 ;
wire \compute_addr_3[1]_i_1_n_0 ;
wire \compute_addr_3[2]_i_1_n_0 ;
wire \compute_addr_3[3]_i_1_n_0 ;
wire \compute_addr_3[4]_i_1_n_0 ;
wire \compute_addr_3[5]_i_1_n_0 ;
wire \compute_addr_3[6]_i_1_n_0 ;
wire \compute_addr_3[7]_i_1_n_0 ;
wire \compute_addr_3[8]_i_1_n_0 ;
wire \compute_addr_3[9]_i_1_n_0 ;
wire corner;
wire \corner_reg_n_0_[0] ;
wire \corner_reg_n_0_[10] ;
wire \corner_reg_n_0_[11] ;
wire \corner_reg_n_0_[12] ;
wire \corner_reg_n_0_[13] ;
wire \corner_reg_n_0_[14] ;
wire \corner_reg_n_0_[15] ;
wire \corner_reg_n_0_[1] ;
wire \corner_reg_n_0_[2] ;
wire \corner_reg_n_0_[3] ;
wire \corner_reg_n_0_[4] ;
wire \corner_reg_n_0_[5] ;
wire \corner_reg_n_0_[6] ;
wire \corner_reg_n_0_[7] ;
wire \corner_reg_n_0_[8] ;
wire \corner_reg_n_0_[9] ;
wire [3:0]cycle;
wire \cycle[0]_i_1_n_0 ;
wire \cycle[0]_rep_i_1_n_0 ;
wire \cycle[1]_i_1_n_0 ;
wire \cycle[1]_rep_i_1__0_n_0 ;
wire \cycle[1]_rep_i_1_n_0 ;
wire \cycle[2]_i_1_n_0 ;
wire \cycle[2]_rep_i_1_n_0 ;
wire \cycle[3]_i_1_n_0 ;
wire \cycle[3]_i_2_n_0 ;
wire \cycle_reg[0]_rep_n_0 ;
wire \cycle_reg[1]_rep__0_n_0 ;
wire \cycle_reg[1]_rep_n_0 ;
wire \cycle_reg[2]_rep_n_0 ;
wire [13:0]data1;
wire [13:0]data2;
wire [13:10]data5;
wire det_0;
wire det_0_reg_i_2_n_0;
wire det_0_reg_n_106;
wire det_0_reg_n_107;
wire det_0_reg_n_108;
wire det_0_reg_n_109;
wire det_0_reg_n_110;
wire det_0_reg_n_111;
wire det_0_reg_n_112;
wire det_0_reg_n_113;
wire det_0_reg_n_114;
wire det_0_reg_n_115;
wire det_0_reg_n_116;
wire det_0_reg_n_117;
wire det_0_reg_n_118;
wire det_0_reg_n_119;
wire det_0_reg_n_120;
wire det_0_reg_n_121;
wire det_0_reg_n_122;
wire det_0_reg_n_123;
wire det_0_reg_n_124;
wire det_0_reg_n_125;
wire det_0_reg_n_126;
wire det_0_reg_n_127;
wire det_0_reg_n_128;
wire det_0_reg_n_129;
wire det_0_reg_n_130;
wire det_0_reg_n_131;
wire det_0_reg_n_132;
wire det_0_reg_n_133;
wire det_0_reg_n_134;
wire det_0_reg_n_135;
wire det_0_reg_n_136;
wire det_0_reg_n_137;
wire det_0_reg_n_138;
wire det_0_reg_n_139;
wire det_0_reg_n_140;
wire det_0_reg_n_141;
wire det_0_reg_n_142;
wire det_0_reg_n_143;
wire det_0_reg_n_144;
wire det_0_reg_n_145;
wire det_0_reg_n_146;
wire det_0_reg_n_147;
wire det_0_reg_n_148;
wire det_0_reg_n_149;
wire det_0_reg_n_150;
wire det_0_reg_n_151;
wire det_0_reg_n_152;
wire det_0_reg_n_153;
wire [31:0]det_abs;
wire [31:1]det_abs0;
wire \det_abs[10]_i_1_n_0 ;
wire \det_abs[11]_i_1_n_0 ;
wire \det_abs[12]_i_1_n_0 ;
wire \det_abs[12]_i_3_n_0 ;
wire \det_abs[12]_i_4_n_0 ;
wire \det_abs[12]_i_5_n_0 ;
wire \det_abs[12]_i_6_n_0 ;
wire \det_abs[13]_i_1_n_0 ;
wire \det_abs[14]_i_1_n_0 ;
wire \det_abs[15]_i_1_n_0 ;
wire \det_abs[16]_i_1_n_0 ;
wire \det_abs[16]_i_3_n_0 ;
wire \det_abs[16]_i_4_n_0 ;
wire \det_abs[16]_i_5_n_0 ;
wire \det_abs[16]_i_6_n_0 ;
wire \det_abs[17]_i_1_n_0 ;
wire \det_abs[18]_i_1_n_0 ;
wire \det_abs[19]_i_1_n_0 ;
wire \det_abs[1]_i_1_n_0 ;
wire \det_abs[20]_i_1_n_0 ;
wire \det_abs[20]_i_3_n_0 ;
wire \det_abs[20]_i_4_n_0 ;
wire \det_abs[20]_i_5_n_0 ;
wire \det_abs[20]_i_6_n_0 ;
wire \det_abs[21]_i_1_n_0 ;
wire \det_abs[22]_i_1_n_0 ;
wire \det_abs[23]_i_1_n_0 ;
wire \det_abs[24]_i_1_n_0 ;
wire \det_abs[24]_i_3_n_0 ;
wire \det_abs[24]_i_4_n_0 ;
wire \det_abs[24]_i_5_n_0 ;
wire \det_abs[24]_i_6_n_0 ;
wire \det_abs[25]_i_1_n_0 ;
wire \det_abs[26]_i_1_n_0 ;
wire \det_abs[27]_i_1_n_0 ;
wire \det_abs[28]_i_1_n_0 ;
wire \det_abs[28]_i_3_n_0 ;
wire \det_abs[28]_i_4_n_0 ;
wire \det_abs[28]_i_5_n_0 ;
wire \det_abs[28]_i_6_n_0 ;
wire \det_abs[29]_i_1_n_0 ;
wire \det_abs[2]_i_1_n_0 ;
wire \det_abs[30]_i_1_n_0 ;
wire \det_abs[31]_i_1_n_0 ;
wire \det_abs[31]_i_3_n_0 ;
wire \det_abs[31]_i_4_n_0 ;
wire \det_abs[31]_i_5_n_0 ;
wire \det_abs[3]_i_1_n_0 ;
wire \det_abs[4]_i_1_n_0 ;
wire \det_abs[4]_i_3_n_0 ;
wire \det_abs[4]_i_4_n_0 ;
wire \det_abs[4]_i_5_n_0 ;
wire \det_abs[4]_i_6_n_0 ;
wire \det_abs[4]_i_7_n_0 ;
wire \det_abs[5]_i_1_n_0 ;
wire \det_abs[6]_i_1_n_0 ;
wire \det_abs[7]_i_1_n_0 ;
wire \det_abs[8]_i_1_n_0 ;
wire \det_abs[8]_i_3_n_0 ;
wire \det_abs[8]_i_4_n_0 ;
wire \det_abs[8]_i_5_n_0 ;
wire \det_abs[8]_i_6_n_0 ;
wire \det_abs[9]_i_1_n_0 ;
wire \det_abs_reg[12]_i_2_n_0 ;
wire \det_abs_reg[12]_i_2_n_1 ;
wire \det_abs_reg[12]_i_2_n_2 ;
wire \det_abs_reg[12]_i_2_n_3 ;
wire \det_abs_reg[16]_i_2_n_0 ;
wire \det_abs_reg[16]_i_2_n_1 ;
wire \det_abs_reg[16]_i_2_n_2 ;
wire \det_abs_reg[16]_i_2_n_3 ;
wire \det_abs_reg[20]_i_2_n_0 ;
wire \det_abs_reg[20]_i_2_n_1 ;
wire \det_abs_reg[20]_i_2_n_2 ;
wire \det_abs_reg[20]_i_2_n_3 ;
wire \det_abs_reg[24]_i_2_n_0 ;
wire \det_abs_reg[24]_i_2_n_1 ;
wire \det_abs_reg[24]_i_2_n_2 ;
wire \det_abs_reg[24]_i_2_n_3 ;
wire \det_abs_reg[28]_i_2_n_0 ;
wire \det_abs_reg[28]_i_2_n_1 ;
wire \det_abs_reg[28]_i_2_n_2 ;
wire \det_abs_reg[28]_i_2_n_3 ;
wire \det_abs_reg[31]_i_2_n_2 ;
wire \det_abs_reg[31]_i_2_n_3 ;
wire \det_abs_reg[4]_i_2_n_0 ;
wire \det_abs_reg[4]_i_2_n_1 ;
wire \det_abs_reg[4]_i_2_n_2 ;
wire \det_abs_reg[4]_i_2_n_3 ;
wire \det_abs_reg[8]_i_2_n_0 ;
wire \det_abs_reg[8]_i_2_n_1 ;
wire \det_abs_reg[8]_i_2_n_2 ;
wire \det_abs_reg[8]_i_2_n_3 ;
wire det_reg_n_100;
wire det_reg_n_101;
wire det_reg_n_102;
wire det_reg_n_103;
wire det_reg_n_104;
wire det_reg_n_105;
wire det_reg_n_74;
wire det_reg_n_75;
wire det_reg_n_76;
wire det_reg_n_77;
wire det_reg_n_78;
wire det_reg_n_79;
wire det_reg_n_80;
wire det_reg_n_81;
wire det_reg_n_82;
wire det_reg_n_83;
wire det_reg_n_84;
wire det_reg_n_85;
wire det_reg_n_86;
wire det_reg_n_87;
wire det_reg_n_88;
wire det_reg_n_89;
wire det_reg_n_90;
wire det_reg_n_91;
wire det_reg_n_92;
wire det_reg_n_93;
wire det_reg_n_94;
wire det_reg_n_95;
wire det_reg_n_96;
wire det_reg_n_97;
wire det_reg_n_98;
wire det_reg_n_99;
wire \din_reg_n_0_[0] ;
wire \din_reg_n_0_[10] ;
wire \din_reg_n_0_[11] ;
wire \din_reg_n_0_[12] ;
wire \din_reg_n_0_[13] ;
wire \din_reg_n_0_[14] ;
wire \din_reg_n_0_[15] ;
wire \din_reg_n_0_[1] ;
wire \din_reg_n_0_[2] ;
wire \din_reg_n_0_[3] ;
wire \din_reg_n_0_[4] ;
wire \din_reg_n_0_[5] ;
wire \din_reg_n_0_[6] ;
wire \din_reg_n_0_[7] ;
wire \din_reg_n_0_[8] ;
wire \din_reg_n_0_[9] ;
wire [15:0]dout_0;
wire [15:0]dout_1;
wire [7:0]g_in;
wire [31:0]hessian_out;
wire i__carry__0_i_1_n_0;
wire i__carry__0_i_2_n_0;
wire i__carry__0_i_3_n_0;
wire i__carry__0_i_4_n_0;
wire i__carry__0_i_5_n_0;
wire i__carry__1_i_1_n_0;
wire i__carry__1_i_2_n_0;
wire i__carry_i_1_n_0;
wire i__carry_i_2_n_0;
wire i__carry_i_3_n_0;
wire i__carry_i_4_n_0;
wire [7:0]last_value;
wire left;
wire \left[15]_i_2_n_0 ;
wire \left[15]_i_3_n_0 ;
wire \left_reg_n_0_[0] ;
wire \left_reg_n_0_[10] ;
wire \left_reg_n_0_[11] ;
wire \left_reg_n_0_[12] ;
wire \left_reg_n_0_[13] ;
wire \left_reg_n_0_[14] ;
wire \left_reg_n_0_[15] ;
wire \left_reg_n_0_[1] ;
wire \left_reg_n_0_[2] ;
wire \left_reg_n_0_[3] ;
wire \left_reg_n_0_[4] ;
wire \left_reg_n_0_[5] ;
wire \left_reg_n_0_[6] ;
wire \left_reg_n_0_[7] ;
wire \left_reg_n_0_[8] ;
wire \left_reg_n_0_[9] ;
wire [15:0]p_0_out;
wire \plusOp_inferred__0/i__carry__0_n_0 ;
wire \plusOp_inferred__0/i__carry__0_n_1 ;
wire \plusOp_inferred__0/i__carry__0_n_2 ;
wire \plusOp_inferred__0/i__carry__0_n_3 ;
wire \plusOp_inferred__0/i__carry__0_n_4 ;
wire \plusOp_inferred__0/i__carry__0_n_5 ;
wire \plusOp_inferred__0/i__carry__0_n_6 ;
wire \plusOp_inferred__0/i__carry__0_n_7 ;
wire \plusOp_inferred__0/i__carry__1_n_3 ;
wire \plusOp_inferred__0/i__carry__1_n_6 ;
wire \plusOp_inferred__0/i__carry__1_n_7 ;
wire \plusOp_inferred__0/i__carry_n_0 ;
wire \plusOp_inferred__0/i__carry_n_1 ;
wire \plusOp_inferred__0/i__carry_n_2 ;
wire \plusOp_inferred__0/i__carry_n_3 ;
wire \plusOp_inferred__0/i__carry_n_4 ;
wire \plusOp_inferred__0/i__carry_n_5 ;
wire \plusOp_inferred__0/i__carry_n_6 ;
wire \plusOp_inferred__0/i__carry_n_7 ;
wire rst;
wire top;
wire \top[15]_i_2_n_0 ;
wire top_left_0;
wire \top_left_0[0]_i_1_n_0 ;
wire \top_left_0[10]_i_1_n_0 ;
wire \top_left_0[11]_i_1_n_0 ;
wire \top_left_0[12]_i_1_n_0 ;
wire \top_left_0[13]_i_1_n_0 ;
wire \top_left_0[14]_i_1_n_0 ;
wire \top_left_0[15]_i_2_n_0 ;
wire \top_left_0[1]_i_1_n_0 ;
wire \top_left_0[2]_i_1_n_0 ;
wire \top_left_0[3]_i_1_n_0 ;
wire \top_left_0[4]_i_1_n_0 ;
wire \top_left_0[5]_i_1_n_0 ;
wire \top_left_0[6]_i_1_n_0 ;
wire \top_left_0[7]_i_1_n_0 ;
wire \top_left_0[8]_i_1_n_0 ;
wire \top_left_0[9]_i_1_n_0 ;
wire \top_left_0_reg_n_0_[0] ;
wire \top_left_0_reg_n_0_[10] ;
wire \top_left_0_reg_n_0_[11] ;
wire \top_left_0_reg_n_0_[12] ;
wire \top_left_0_reg_n_0_[13] ;
wire \top_left_0_reg_n_0_[14] ;
wire \top_left_0_reg_n_0_[15] ;
wire \top_left_0_reg_n_0_[1] ;
wire \top_left_0_reg_n_0_[2] ;
wire \top_left_0_reg_n_0_[3] ;
wire \top_left_0_reg_n_0_[4] ;
wire \top_left_0_reg_n_0_[5] ;
wire \top_left_0_reg_n_0_[6] ;
wire \top_left_0_reg_n_0_[7] ;
wire \top_left_0_reg_n_0_[8] ;
wire \top_left_0_reg_n_0_[9] ;
wire [15:0]top_left_1;
wire \top_left_1[0]_i_1_n_0 ;
wire \top_left_1[10]_i_1_n_0 ;
wire \top_left_1[11]_i_1_n_0 ;
wire \top_left_1[12]_i_1_n_0 ;
wire \top_left_1[13]_i_1_n_0 ;
wire \top_left_1[14]_i_1_n_0 ;
wire \top_left_1[15]_i_2_n_0 ;
wire \top_left_1[1]_i_1_n_0 ;
wire \top_left_1[2]_i_1_n_0 ;
wire \top_left_1[3]_i_1_n_0 ;
wire \top_left_1[4]_i_1_n_0 ;
wire \top_left_1[5]_i_1_n_0 ;
wire \top_left_1[6]_i_1_n_0 ;
wire \top_left_1[7]_i_1_n_0 ;
wire \top_left_1[8]_i_1_n_0 ;
wire \top_left_1[9]_i_1_n_0 ;
wire \top_reg_n_0_[0] ;
wire \top_reg_n_0_[10] ;
wire \top_reg_n_0_[11] ;
wire \top_reg_n_0_[12] ;
wire \top_reg_n_0_[13] ;
wire \top_reg_n_0_[14] ;
wire \top_reg_n_0_[15] ;
wire \top_reg_n_0_[1] ;
wire \top_reg_n_0_[2] ;
wire \top_reg_n_0_[3] ;
wire \top_reg_n_0_[4] ;
wire \top_reg_n_0_[5] ;
wire \top_reg_n_0_[6] ;
wire \top_reg_n_0_[7] ;
wire \top_reg_n_0_[8] ;
wire \top_reg_n_0_[9] ;
wire top_right_0;
wire \top_right_0[0]_i_1_n_0 ;
wire \top_right_0[10]_i_1_n_0 ;
wire \top_right_0[11]_i_1_n_0 ;
wire \top_right_0[12]_i_1_n_0 ;
wire \top_right_0[13]_i_1_n_0 ;
wire \top_right_0[14]_i_1_n_0 ;
wire \top_right_0[15]_i_2_n_0 ;
wire \top_right_0[1]_i_1_n_0 ;
wire \top_right_0[2]_i_1_n_0 ;
wire \top_right_0[3]_i_1_n_0 ;
wire \top_right_0[4]_i_1_n_0 ;
wire \top_right_0[5]_i_1_n_0 ;
wire \top_right_0[6]_i_1_n_0 ;
wire \top_right_0[7]_i_1_n_0 ;
wire \top_right_0[8]_i_1_n_0 ;
wire \top_right_0[9]_i_1_n_0 ;
wire \top_right_0_reg_n_0_[0] ;
wire \top_right_0_reg_n_0_[10] ;
wire \top_right_0_reg_n_0_[11] ;
wire \top_right_0_reg_n_0_[12] ;
wire \top_right_0_reg_n_0_[13] ;
wire \top_right_0_reg_n_0_[14] ;
wire \top_right_0_reg_n_0_[15] ;
wire \top_right_0_reg_n_0_[1] ;
wire \top_right_0_reg_n_0_[2] ;
wire \top_right_0_reg_n_0_[3] ;
wire \top_right_0_reg_n_0_[4] ;
wire \top_right_0_reg_n_0_[5] ;
wire \top_right_0_reg_n_0_[6] ;
wire \top_right_0_reg_n_0_[7] ;
wire \top_right_0_reg_n_0_[8] ;
wire \top_right_0_reg_n_0_[9] ;
wire top_right_1;
wire \top_right_1[0]_i_1_n_0 ;
wire \top_right_1[10]_i_1_n_0 ;
wire \top_right_1[11]_i_1_n_0 ;
wire \top_right_1[12]_i_1_n_0 ;
wire \top_right_1[13]_i_1_n_0 ;
wire \top_right_1[14]_i_1_n_0 ;
wire \top_right_1[15]_i_1_n_0 ;
wire \top_right_1[15]_i_2_n_0 ;
wire \top_right_1[1]_i_1_n_0 ;
wire \top_right_1[2]_i_1_n_0 ;
wire \top_right_1[3]_i_1_n_0 ;
wire \top_right_1[4]_i_1_n_0 ;
wire \top_right_1[5]_i_1_n_0 ;
wire \top_right_1[6]_i_1_n_0 ;
wire \top_right_1[7]_i_1_n_0 ;
wire \top_right_1[8]_i_1_n_0 ;
wire \top_right_1[9]_i_1_n_0 ;
wire \top_right_1_reg_n_0_[0] ;
wire \top_right_1_reg_n_0_[10] ;
wire \top_right_1_reg_n_0_[11] ;
wire \top_right_1_reg_n_0_[12] ;
wire \top_right_1_reg_n_0_[13] ;
wire \top_right_1_reg_n_0_[14] ;
wire \top_right_1_reg_n_0_[15] ;
wire \top_right_1_reg_n_0_[1] ;
wire \top_right_1_reg_n_0_[2] ;
wire \top_right_1_reg_n_0_[3] ;
wire \top_right_1_reg_n_0_[4] ;
wire \top_right_1_reg_n_0_[5] ;
wire \top_right_1_reg_n_0_[6] ;
wire \top_right_1_reg_n_0_[7] ;
wire \top_right_1_reg_n_0_[8] ;
wire \top_right_1_reg_n_0_[9] ;
wire \value_reg_n_0_[0] ;
wire \value_reg_n_0_[1] ;
wire \value_reg_n_0_[2] ;
wire \value_reg_n_0_[3] ;
wire \value_reg_n_0_[4] ;
wire \value_reg_n_0_[5] ;
wire \value_reg_n_0_[6] ;
wire \value_reg_n_0_[7] ;
wire wen_i_1_n_0;
wire wen_i_2_n_0;
wire wen_reg_n_0;
wire x;
wire \x0[0]_i_2_n_0 ;
wire \x0[0]_i_3_n_0 ;
wire \x0[1]_i_2_n_0 ;
wire \x0[1]_i_3_n_0 ;
wire \x0[1]_i_4_n_0 ;
wire \x0[2]_i_1_n_0 ;
wire \x0[2]_i_2_n_0 ;
wire \x0[2]_i_3_n_0 ;
wire \x0[2]_i_4_n_0 ;
wire \x0[2]_i_5_n_0 ;
wire \x0[3]_i_1_n_0 ;
wire \x0[3]_i_2_n_0 ;
wire \x0[3]_i_3_n_0 ;
wire \x0[3]_i_4_n_0 ;
wire \x0[3]_i_5_n_0 ;
wire \x0[3]_i_6_n_0 ;
wire \x0[4]_i_1_n_0 ;
wire \x0[4]_i_2_n_0 ;
wire \x0[4]_i_3_n_0 ;
wire \x0[4]_i_4_n_0 ;
wire \x0[4]_i_5_n_0 ;
wire \x0[5]_i_1_n_0 ;
wire \x0[5]_i_2_n_0 ;
wire \x0[5]_i_3_n_0 ;
wire \x0[5]_i_4_n_0 ;
wire \x0[5]_i_5_n_0 ;
wire \x0[6]_i_1_n_0 ;
wire \x0[6]_i_2_n_0 ;
wire \x0[6]_i_3_n_0 ;
wire \x0[6]_i_4_n_0 ;
wire \x0[6]_i_5_n_0 ;
wire \x0[7]_i_1_n_0 ;
wire \x0[7]_i_2_n_0 ;
wire \x0[7]_i_3_n_0 ;
wire \x0[7]_i_4_n_0 ;
wire \x0[7]_i_5_n_0 ;
wire \x0[7]_i_6_n_0 ;
wire \x0[7]_i_7_n_0 ;
wire \x0[8]_i_1_n_0 ;
wire \x0[8]_i_2_n_0 ;
wire \x0[8]_i_3_n_0 ;
wire \x0[8]_i_4_n_0 ;
wire \x0[8]_i_5_n_0 ;
wire \x0[8]_i_6_n_0 ;
wire \x0[8]_i_7_n_0 ;
wire \x0[9]_i_1_n_0 ;
wire \x0[9]_i_2_n_0 ;
wire \x0[9]_i_3_n_0 ;
wire \x0[9]_i_4_n_0 ;
wire \x0[9]_i_5_n_0 ;
wire \x0[9]_i_6_n_0 ;
wire \x0[9]_i_7_n_0 ;
wire \x0_reg[0]_i_1_n_0 ;
wire \x0_reg[1]_i_1_n_0 ;
wire x1;
wire \x1[0]_i_1_n_0 ;
wire \x1[1]_i_1_n_0 ;
wire \x1[2]_i_1_n_0 ;
wire \x1[2]_i_2_n_0 ;
wire \x1[2]_i_3_n_0 ;
wire \x1[3]_i_1_n_0 ;
wire \x1[3]_i_2_n_0 ;
wire \x1[3]_i_3_n_0 ;
wire \x1[3]_i_4_n_0 ;
wire \x1[4]_i_1_n_0 ;
wire \x1[4]_i_2_n_0 ;
wire \x1[4]_i_3_n_0 ;
wire \x1[4]_i_4_n_0 ;
wire \x1[4]_i_5_n_0 ;
wire \x1[5]_i_1_n_0 ;
wire \x1[5]_i_2_n_0 ;
wire \x1[5]_i_3_n_0 ;
wire \x1[5]_i_4_n_0 ;
wire \x1[5]_i_5_n_0 ;
wire \x1[6]_i_1_n_0 ;
wire \x1[6]_i_2_n_0 ;
wire \x1[6]_i_3_n_0 ;
wire \x1[6]_i_4_n_0 ;
wire \x1[6]_i_5_n_0 ;
wire \x1[6]_i_6_n_0 ;
wire \x1[6]_i_7_n_0 ;
wire \x1[6]_i_8_n_0 ;
wire \x1[7]_i_1_n_0 ;
wire \x1[7]_i_2_n_0 ;
wire \x1[7]_i_3_n_0 ;
wire \x1[7]_i_4_n_0 ;
wire \x1[7]_i_5_n_0 ;
wire \x1[8]_i_1_n_0 ;
wire \x1[8]_i_2_n_0 ;
wire \x1[8]_i_3_n_0 ;
wire \x1[8]_i_4_n_0 ;
wire \x1[8]_i_5_n_0 ;
wire \x1[8]_i_6_n_0 ;
wire \x1[9]_i_2_n_0 ;
wire \x1[9]_i_3_n_0 ;
wire \x1[9]_i_4_n_0 ;
wire \x1[9]_i_5_n_0 ;
wire \x1[9]_i_6_n_0 ;
wire \x1[9]_i_7_n_0 ;
wire \x1[9]_i_8_n_0 ;
wire [9:0]x_addr;
wire \x_reg_n_0_[0] ;
wire \x_reg_n_0_[1] ;
wire \x_reg_n_0_[2] ;
wire \x_reg_n_0_[3] ;
wire \x_reg_n_0_[4] ;
wire \x_reg_n_0_[5] ;
wire \x_reg_n_0_[6] ;
wire \x_reg_n_0_[7] ;
wire \x_reg_n_0_[8] ;
wire \x_reg_n_0_[9] ;
wire y1;
wire \y1[2]_i_1_n_0 ;
wire \y1[3]_i_1_n_0 ;
wire \y1_reg_n_0_[0] ;
wire \y1_reg_n_0_[1] ;
wire \y1_reg_n_0_[2] ;
wire \y1_reg_n_0_[3] ;
wire y2;
wire \y2[1]_i_1_n_0 ;
wire \y2[2]_i_1_n_0 ;
wire \y2[3]_i_1_n_0 ;
wire \y2_reg_n_0_[0] ;
wire \y2_reg_n_0_[1] ;
wire \y2_reg_n_0_[2] ;
wire \y2_reg_n_0_[3] ;
wire y3;
wire \y3[1]_i_1_n_0 ;
wire \y3[2]_i_1_n_0 ;
wire \y3[3]_i_1_n_0 ;
wire \y3_reg_n_0_[0] ;
wire \y3_reg_n_0_[1] ;
wire \y3_reg_n_0_[2] ;
wire \y3_reg_n_0_[3] ;
wire \y4[2]_i_1_n_0 ;
wire \y4[3]_i_1_n_0 ;
wire y5;
wire \y5[0]_i_1_n_0 ;
wire \y5[1]_i_1_n_0 ;
wire \y5[2]_i_1_n_0 ;
wire \y5[3]_i_1_n_0 ;
wire y6;
wire \y6[2]_i_1_n_0 ;
wire \y6[3]_i_1_n_0 ;
wire \y6_reg_n_0_[0] ;
wire \y6_reg_n_0_[1] ;
wire \y6_reg_n_0_[2] ;
wire \y6_reg_n_0_[3] ;
wire [3:0]y7;
wire \y7[2]_i_1_n_0 ;
wire \y7[3]_i_1_n_0 ;
wire [3:0]y8;
wire \y8[3]_i_1_n_0 ;
wire y9;
wire \y9[3]_i_1_n_0 ;
wire \y_actual_reg_n_0_[0] ;
wire \y_actual_reg_n_0_[1] ;
wire \y_actual_reg_n_0_[2] ;
wire \y_actual_reg_n_0_[3] ;
wire \y_actual_reg_n_0_[4] ;
wire \y_actual_reg_n_0_[5] ;
wire \y_actual_reg_n_0_[6] ;
wire \y_actual_reg_n_0_[7] ;
wire \y_actual_reg_n_0_[8] ;
wire \y_actual_reg_n_0_[9] ;
wire [9:0]y_addr;
wire [3:3]NLW_Lxx0_carry__2_CO_UNCONNECTED;
wire [3:3]NLW_Lxx_00__1_carry__2_CO_UNCONNECTED;
wire [3:3]NLW_Lxx_11__1_carry__2_CO_UNCONNECTED;
wire [3:3]NLW_Lxy0__1_carry__2_CO_UNCONNECTED;
wire [3:3]NLW_Lyy0_carry__2_CO_UNCONNECTED;
wire [3:3]NLW_Lyy_20__1_carry__2_CO_UNCONNECTED;
wire [3:3]NLW_Lyy_2_bottom_right0__0_carry__2_CO_UNCONNECTED;
wire NLW_det_0_reg_CARRYCASCOUT_UNCONNECTED;
wire NLW_det_0_reg_MULTSIGNOUT_UNCONNECTED;
wire NLW_det_0_reg_OVERFLOW_UNCONNECTED;
wire NLW_det_0_reg_PATTERNBDETECT_UNCONNECTED;
wire NLW_det_0_reg_PATTERNDETECT_UNCONNECTED;
wire NLW_det_0_reg_UNDERFLOW_UNCONNECTED;
wire [29:0]NLW_det_0_reg_ACOUT_UNCONNECTED;
wire [17:0]NLW_det_0_reg_BCOUT_UNCONNECTED;
wire [3:0]NLW_det_0_reg_CARRYOUT_UNCONNECTED;
wire [47:0]NLW_det_0_reg_P_UNCONNECTED;
wire [3:2]\NLW_det_abs_reg[31]_i_2_CO_UNCONNECTED ;
wire [3:3]\NLW_det_abs_reg[31]_i_2_O_UNCONNECTED ;
wire NLW_det_reg_CARRYCASCOUT_UNCONNECTED;
wire NLW_det_reg_MULTSIGNOUT_UNCONNECTED;
wire NLW_det_reg_OVERFLOW_UNCONNECTED;
wire NLW_det_reg_PATTERNBDETECT_UNCONNECTED;
wire NLW_det_reg_PATTERNDETECT_UNCONNECTED;
wire NLW_det_reg_UNDERFLOW_UNCONNECTED;
wire [29:0]NLW_det_reg_ACOUT_UNCONNECTED;
wire [17:0]NLW_det_reg_BCOUT_UNCONNECTED;
wire [3:0]NLW_det_reg_CARRYOUT_UNCONNECTED;
wire [47:32]NLW_det_reg_P_UNCONNECTED;
wire [47:0]NLW_det_reg_PCOUT_UNCONNECTED;
wire [3:1]\NLW_plusOp_inferred__0/i__carry__1_CO_UNCONNECTED ;
wire [3:2]\NLW_plusOp_inferred__0/i__carry__1_O_UNCONNECTED ;
CARRY4 Lxx0_carry
(.CI(1'b0),
.CO({Lxx0_carry_n_0,Lxx0_carry_n_1,Lxx0_carry_n_2,Lxx0_carry_n_3}),
.CYINIT(1'b0),
.DI({Lxx0_carry_i_1_n_0,Lxx0_carry_i_2_n_0,1'b1,\Lxx_2_reg_n_0_[0] }),
.O(A[3:0]),
.S({Lxx0_carry_i_3_n_0,Lxx0_carry_i_4_n_0,Lxx0_carry_i_5_n_0,Lxx0_carry_i_6_n_0}));
CARRY4 Lxx0_carry__0
(.CI(Lxx0_carry_n_0),
.CO({Lxx0_carry__0_n_0,Lxx0_carry__0_n_1,Lxx0_carry__0_n_2,Lxx0_carry__0_n_3}),
.CYINIT(1'b0),
.DI({Lxx0_carry__0_i_1_n_0,Lxx0_carry__0_i_2_n_0,Lxx0_carry__0_i_3_n_0,Lxx0_carry__0_i_4_n_0}),
.O(A[7:4]),
.S({Lxx0_carry__0_i_5_n_0,Lxx0_carry__0_i_6_n_0,Lxx0_carry__0_i_7_n_0,Lxx0_carry__0_i_8_n_0}));
(* HLUTNM = "lutpair4" *)
LUT3 #(
.INIT(8'hD4))
Lxx0_carry__0_i_1
(.I0(Lxx_1[6]),
.I1(\Lxx_2_reg_n_0_[6] ),
.I2(Lxx_0[6]),
.O(Lxx0_carry__0_i_1_n_0));
(* HLUTNM = "lutpair3" *)
LUT3 #(
.INIT(8'hD4))
Lxx0_carry__0_i_2
(.I0(Lxx_1[5]),
.I1(\Lxx_2_reg_n_0_[5] ),
.I2(Lxx_0[5]),
.O(Lxx0_carry__0_i_2_n_0));
(* HLUTNM = "lutpair2" *)
LUT3 #(
.INIT(8'hD4))
Lxx0_carry__0_i_3
(.I0(Lxx_1[4]),
.I1(\Lxx_2_reg_n_0_[4] ),
.I2(Lxx_0[4]),
.O(Lxx0_carry__0_i_3_n_0));
(* HLUTNM = "lutpair1" *)
LUT3 #(
.INIT(8'hD4))
Lxx0_carry__0_i_4
(.I0(Lxx_1[3]),
.I1(\Lxx_2_reg_n_0_[3] ),
.I2(Lxx_0[3]),
.O(Lxx0_carry__0_i_4_n_0));
(* HLUTNM = "lutpair5" *)
LUT4 #(
.INIT(16'h9669))
Lxx0_carry__0_i_5
(.I0(Lxx_1[7]),
.I1(\Lxx_2_reg_n_0_[7] ),
.I2(Lxx_0[7]),
.I3(Lxx0_carry__0_i_1_n_0),
.O(Lxx0_carry__0_i_5_n_0));
(* HLUTNM = "lutpair4" *)
LUT4 #(
.INIT(16'h9669))
Lxx0_carry__0_i_6
(.I0(Lxx_1[6]),
.I1(\Lxx_2_reg_n_0_[6] ),
.I2(Lxx_0[6]),
.I3(Lxx0_carry__0_i_2_n_0),
.O(Lxx0_carry__0_i_6_n_0));
(* HLUTNM = "lutpair3" *)
LUT4 #(
.INIT(16'h9669))
Lxx0_carry__0_i_7
(.I0(Lxx_1[5]),
.I1(\Lxx_2_reg_n_0_[5] ),
.I2(Lxx_0[5]),
.I3(Lxx0_carry__0_i_3_n_0),
.O(Lxx0_carry__0_i_7_n_0));
(* HLUTNM = "lutpair2" *)
LUT4 #(
.INIT(16'h9669))
Lxx0_carry__0_i_8
(.I0(Lxx_1[4]),
.I1(\Lxx_2_reg_n_0_[4] ),
.I2(Lxx_0[4]),
.I3(Lxx0_carry__0_i_4_n_0),
.O(Lxx0_carry__0_i_8_n_0));
CARRY4 Lxx0_carry__1
(.CI(Lxx0_carry__0_n_0),
.CO({Lxx0_carry__1_n_0,Lxx0_carry__1_n_1,Lxx0_carry__1_n_2,Lxx0_carry__1_n_3}),
.CYINIT(1'b0),
.DI({Lxx0_carry__1_i_1_n_0,Lxx0_carry__1_i_2_n_0,Lxx0_carry__1_i_3_n_0,Lxx0_carry__1_i_4_n_0}),
.O(A[11:8]),
.S({Lxx0_carry__1_i_5_n_0,Lxx0_carry__1_i_6_n_0,Lxx0_carry__1_i_7_n_0,Lxx0_carry__1_i_8_n_0}));
(* HLUTNM = "lutpair8" *)
LUT3 #(
.INIT(8'hD4))
Lxx0_carry__1_i_1
(.I0(Lxx_1[10]),
.I1(\Lxx_2_reg_n_0_[10] ),
.I2(Lxx_0[10]),
.O(Lxx0_carry__1_i_1_n_0));
(* HLUTNM = "lutpair7" *)
LUT3 #(
.INIT(8'hD4))
Lxx0_carry__1_i_2
(.I0(Lxx_1[9]),
.I1(\Lxx_2_reg_n_0_[9] ),
.I2(Lxx_0[9]),
.O(Lxx0_carry__1_i_2_n_0));
(* HLUTNM = "lutpair6" *)
LUT3 #(
.INIT(8'hD4))
Lxx0_carry__1_i_3
(.I0(Lxx_1[8]),
.I1(\Lxx_2_reg_n_0_[8] ),
.I2(Lxx_0[8]),
.O(Lxx0_carry__1_i_3_n_0));
(* HLUTNM = "lutpair5" *)
LUT3 #(
.INIT(8'hD4))
Lxx0_carry__1_i_4
(.I0(Lxx_1[7]),
.I1(\Lxx_2_reg_n_0_[7] ),
.I2(Lxx_0[7]),
.O(Lxx0_carry__1_i_4_n_0));
(* HLUTNM = "lutpair9" *)
LUT4 #(
.INIT(16'h9669))
Lxx0_carry__1_i_5
(.I0(Lxx_1[11]),
.I1(\Lxx_2_reg_n_0_[11] ),
.I2(Lxx_0[11]),
.I3(Lxx0_carry__1_i_1_n_0),
.O(Lxx0_carry__1_i_5_n_0));
(* HLUTNM = "lutpair8" *)
LUT4 #(
.INIT(16'h9669))
Lxx0_carry__1_i_6
(.I0(Lxx_1[10]),
.I1(\Lxx_2_reg_n_0_[10] ),
.I2(Lxx_0[10]),
.I3(Lxx0_carry__1_i_2_n_0),
.O(Lxx0_carry__1_i_6_n_0));
(* HLUTNM = "lutpair7" *)
LUT4 #(
.INIT(16'h9669))
Lxx0_carry__1_i_7
(.I0(Lxx_1[9]),
.I1(\Lxx_2_reg_n_0_[9] ),
.I2(Lxx_0[9]),
.I3(Lxx0_carry__1_i_3_n_0),
.O(Lxx0_carry__1_i_7_n_0));
(* HLUTNM = "lutpair6" *)
LUT4 #(
.INIT(16'h9669))
Lxx0_carry__1_i_8
(.I0(Lxx_1[8]),
.I1(\Lxx_2_reg_n_0_[8] ),
.I2(Lxx_0[8]),
.I3(Lxx0_carry__1_i_4_n_0),
.O(Lxx0_carry__1_i_8_n_0));
CARRY4 Lxx0_carry__2
(.CI(Lxx0_carry__1_n_0),
.CO({NLW_Lxx0_carry__2_CO_UNCONNECTED[3],Lxx0_carry__2_n_1,Lxx0_carry__2_n_2,Lxx0_carry__2_n_3}),
.CYINIT(1'b0),
.DI({1'b0,Lxx0_carry__2_i_1_n_0,Lxx0_carry__2_i_2_n_0,Lxx0_carry__2_i_3_n_0}),
.O(A[15:12]),
.S({Lxx0_carry__2_i_4_n_0,Lxx0_carry__2_i_5_n_0,Lxx0_carry__2_i_6_n_0,Lxx0_carry__2_i_7_n_0}));
(* HLUTNM = "lutpair11" *)
LUT3 #(
.INIT(8'hD4))
Lxx0_carry__2_i_1
(.I0(Lxx_1[13]),
.I1(\Lxx_2_reg_n_0_[13] ),
.I2(Lxx_0[13]),
.O(Lxx0_carry__2_i_1_n_0));
(* HLUTNM = "lutpair10" *)
LUT3 #(
.INIT(8'hD4))
Lxx0_carry__2_i_2
(.I0(Lxx_1[12]),
.I1(\Lxx_2_reg_n_0_[12] ),
.I2(Lxx_0[12]),
.O(Lxx0_carry__2_i_2_n_0));
(* HLUTNM = "lutpair9" *)
LUT3 #(
.INIT(8'hD4))
Lxx0_carry__2_i_3
(.I0(Lxx_1[11]),
.I1(\Lxx_2_reg_n_0_[11] ),
.I2(Lxx_0[11]),
.O(Lxx0_carry__2_i_3_n_0));
LUT6 #(
.INIT(64'h8E71718E718E8E71))
Lxx0_carry__2_i_4
(.I0(Lxx_0[14]),
.I1(\Lxx_2_reg_n_0_[14] ),
.I2(Lxx_1[14]),
.I3(\Lxx_2_reg_n_0_[15] ),
.I4(Lxx_1[15]),
.I5(Lxx_0[15]),
.O(Lxx0_carry__2_i_4_n_0));
LUT4 #(
.INIT(16'h9669))
Lxx0_carry__2_i_5
(.I0(Lxx0_carry__2_i_1_n_0),
.I1(\Lxx_2_reg_n_0_[14] ),
.I2(Lxx_1[14]),
.I3(Lxx_0[14]),
.O(Lxx0_carry__2_i_5_n_0));
(* HLUTNM = "lutpair11" *)
LUT4 #(
.INIT(16'h9669))
Lxx0_carry__2_i_6
(.I0(Lxx_1[13]),
.I1(\Lxx_2_reg_n_0_[13] ),
.I2(Lxx_0[13]),
.I3(Lxx0_carry__2_i_2_n_0),
.O(Lxx0_carry__2_i_6_n_0));
(* HLUTNM = "lutpair10" *)
LUT4 #(
.INIT(16'h9669))
Lxx0_carry__2_i_7
(.I0(Lxx_1[12]),
.I1(\Lxx_2_reg_n_0_[12] ),
.I2(Lxx_0[12]),
.I3(Lxx0_carry__2_i_3_n_0),
.O(Lxx0_carry__2_i_7_n_0));
(* HLUTNM = "lutpair0" *)
LUT3 #(
.INIT(8'hD4))
Lxx0_carry_i_1
(.I0(Lxx_1[2]),
.I1(\Lxx_2_reg_n_0_[2] ),
.I2(Lxx_0[2]),
.O(Lxx0_carry_i_1_n_0));
(* HLUTNM = "lutpair24" *)
LUT3 #(
.INIT(8'hD4))
Lxx0_carry_i_2
(.I0(Lxx_1[1]),
.I1(\Lxx_2_reg_n_0_[1] ),
.I2(Lxx_0[1]),
.O(Lxx0_carry_i_2_n_0));
(* HLUTNM = "lutpair1" *)
LUT4 #(
.INIT(16'h9669))
Lxx0_carry_i_3
(.I0(Lxx_1[3]),
.I1(\Lxx_2_reg_n_0_[3] ),
.I2(Lxx_0[3]),
.I3(Lxx0_carry_i_1_n_0),
.O(Lxx0_carry_i_3_n_0));
(* HLUTNM = "lutpair0" *)
LUT4 #(
.INIT(16'h9669))
Lxx0_carry_i_4
(.I0(Lxx_1[2]),
.I1(\Lxx_2_reg_n_0_[2] ),
.I2(Lxx_0[2]),
.I3(Lxx0_carry_i_2_n_0),
.O(Lxx0_carry_i_4_n_0));
(* HLUTNM = "lutpair24" *)
LUT3 #(
.INIT(8'h96))
Lxx0_carry_i_5
(.I0(Lxx_1[1]),
.I1(\Lxx_2_reg_n_0_[1] ),
.I2(Lxx_0[1]),
.O(Lxx0_carry_i_5_n_0));
LUT2 #(
.INIT(4'h6))
Lxx0_carry_i_6
(.I0(\Lxx_2_reg_n_0_[0] ),
.I1(Lxx_0[0]),
.O(Lxx0_carry_i_6_n_0));
CARRY4 Lxx_00__1_carry
(.CI(1'b0),
.CO({Lxx_00__1_carry_n_0,Lxx_00__1_carry_n_1,Lxx_00__1_carry_n_2,Lxx_00__1_carry_n_3}),
.CYINIT(1'b0),
.DI({Lxx_00__1_carry_i_1_n_0,Lxx_00__1_carry_i_2_n_0,Lxx_00__1_carry_i_3_n_0,\bottom_right_0_reg_n_0_[0] }),
.O(Lxx_00[3:0]),
.S({Lxx_00__1_carry_i_4_n_0,Lxx_00__1_carry_i_5_n_0,Lxx_00__1_carry_i_6_n_0,Lxx_00__1_carry_i_7_n_0}));
CARRY4 Lxx_00__1_carry__0
(.CI(Lxx_00__1_carry_n_0),
.CO({Lxx_00__1_carry__0_n_0,Lxx_00__1_carry__0_n_1,Lxx_00__1_carry__0_n_2,Lxx_00__1_carry__0_n_3}),
.CYINIT(1'b0),
.DI({Lxx_00__1_carry__0_i_1_n_0,Lxx_00__1_carry__0_i_2_n_0,Lxx_00__1_carry__0_i_3_n_0,Lxx_00__1_carry__0_i_4_n_0}),
.O(Lxx_00[7:4]),
.S({Lxx_00__1_carry__0_i_5_n_0,Lxx_00__1_carry__0_i_6_n_0,Lxx_00__1_carry__0_i_7_n_0,Lxx_00__1_carry__0_i_8_n_0}));
LUT5 #(
.INIT(32'h88E8E8EE))
Lxx_00__1_carry__0_i_1
(.I0(\bottom_right_0_reg_n_0_[6] ),
.I1(Lxx_00__1_carry__0_i_9_n_0),
.I2(\top_left_0_reg_n_0_[5] ),
.I3(\top_right_0_reg_n_0_[5] ),
.I4(\bottom_left_0_reg_n_0_[5] ),
.O(Lxx_00__1_carry__0_i_1_n_0));
LUT3 #(
.INIT(8'h96))
Lxx_00__1_carry__0_i_10
(.I0(\bottom_left_0_reg_n_0_[5] ),
.I1(\top_right_0_reg_n_0_[5] ),
.I2(\top_left_0_reg_n_0_[5] ),
.O(Lxx_00__1_carry__0_i_10_n_0));
LUT3 #(
.INIT(8'h96))
Lxx_00__1_carry__0_i_11
(.I0(\bottom_left_0_reg_n_0_[4] ),
.I1(\top_right_0_reg_n_0_[4] ),
.I2(\top_left_0_reg_n_0_[4] ),
.O(Lxx_00__1_carry__0_i_11_n_0));
LUT3 #(
.INIT(8'h96))
Lxx_00__1_carry__0_i_12
(.I0(\bottom_left_0_reg_n_0_[7] ),
.I1(\top_right_0_reg_n_0_[7] ),
.I2(\top_left_0_reg_n_0_[7] ),
.O(Lxx_00__1_carry__0_i_12_n_0));
LUT5 #(
.INIT(32'h88E8E8EE))
Lxx_00__1_carry__0_i_2
(.I0(\bottom_right_0_reg_n_0_[5] ),
.I1(Lxx_00__1_carry__0_i_10_n_0),
.I2(\top_left_0_reg_n_0_[4] ),
.I3(\top_right_0_reg_n_0_[4] ),
.I4(\bottom_left_0_reg_n_0_[4] ),
.O(Lxx_00__1_carry__0_i_2_n_0));
LUT5 #(
.INIT(32'h88E8E8EE))
Lxx_00__1_carry__0_i_3
(.I0(\bottom_right_0_reg_n_0_[4] ),
.I1(Lxx_00__1_carry__0_i_11_n_0),
.I2(\top_left_0_reg_n_0_[3] ),
.I3(\top_right_0_reg_n_0_[3] ),
.I4(\bottom_left_0_reg_n_0_[3] ),
.O(Lxx_00__1_carry__0_i_3_n_0));
LUT5 #(
.INIT(32'h88E8E8EE))
Lxx_00__1_carry__0_i_4
(.I0(\bottom_right_0_reg_n_0_[3] ),
.I1(Lxx_00__1_carry_i_8_n_0),
.I2(\top_left_0_reg_n_0_[2] ),
.I3(\top_right_0_reg_n_0_[2] ),
.I4(\bottom_left_0_reg_n_0_[2] ),
.O(Lxx_00__1_carry__0_i_4_n_0));
LUT6 #(
.INIT(64'hA665599A599AA665))
Lxx_00__1_carry__0_i_5
(.I0(Lxx_00__1_carry__0_i_1_n_0),
.I1(\top_left_0_reg_n_0_[6] ),
.I2(\top_right_0_reg_n_0_[6] ),
.I3(\bottom_left_0_reg_n_0_[6] ),
.I4(\bottom_right_0_reg_n_0_[7] ),
.I5(Lxx_00__1_carry__0_i_12_n_0),
.O(Lxx_00__1_carry__0_i_5_n_0));
LUT6 #(
.INIT(64'hA665599A599AA665))
Lxx_00__1_carry__0_i_6
(.I0(Lxx_00__1_carry__0_i_2_n_0),
.I1(\top_left_0_reg_n_0_[5] ),
.I2(\top_right_0_reg_n_0_[5] ),
.I3(\bottom_left_0_reg_n_0_[5] ),
.I4(\bottom_right_0_reg_n_0_[6] ),
.I5(Lxx_00__1_carry__0_i_9_n_0),
.O(Lxx_00__1_carry__0_i_6_n_0));
LUT6 #(
.INIT(64'hA665599A599AA665))
Lxx_00__1_carry__0_i_7
(.I0(Lxx_00__1_carry__0_i_3_n_0),
.I1(\top_left_0_reg_n_0_[4] ),
.I2(\top_right_0_reg_n_0_[4] ),
.I3(\bottom_left_0_reg_n_0_[4] ),
.I4(\bottom_right_0_reg_n_0_[5] ),
.I5(Lxx_00__1_carry__0_i_10_n_0),
.O(Lxx_00__1_carry__0_i_7_n_0));
LUT6 #(
.INIT(64'hA665599A599AA665))
Lxx_00__1_carry__0_i_8
(.I0(Lxx_00__1_carry__0_i_4_n_0),
.I1(\top_left_0_reg_n_0_[3] ),
.I2(\top_right_0_reg_n_0_[3] ),
.I3(\bottom_left_0_reg_n_0_[3] ),
.I4(\bottom_right_0_reg_n_0_[4] ),
.I5(Lxx_00__1_carry__0_i_11_n_0),
.O(Lxx_00__1_carry__0_i_8_n_0));
LUT3 #(
.INIT(8'h96))
Lxx_00__1_carry__0_i_9
(.I0(\bottom_left_0_reg_n_0_[6] ),
.I1(\top_right_0_reg_n_0_[6] ),
.I2(\top_left_0_reg_n_0_[6] ),
.O(Lxx_00__1_carry__0_i_9_n_0));
CARRY4 Lxx_00__1_carry__1
(.CI(Lxx_00__1_carry__0_n_0),
.CO({Lxx_00__1_carry__1_n_0,Lxx_00__1_carry__1_n_1,Lxx_00__1_carry__1_n_2,Lxx_00__1_carry__1_n_3}),
.CYINIT(1'b0),
.DI({Lxx_00__1_carry__1_i_1_n_0,Lxx_00__1_carry__1_i_2_n_0,Lxx_00__1_carry__1_i_3_n_0,Lxx_00__1_carry__1_i_4_n_0}),
.O(Lxx_00[11:8]),
.S({Lxx_00__1_carry__1_i_5_n_0,Lxx_00__1_carry__1_i_6_n_0,Lxx_00__1_carry__1_i_7_n_0,Lxx_00__1_carry__1_i_8_n_0}));
LUT5 #(
.INIT(32'h88E8E8EE))
Lxx_00__1_carry__1_i_1
(.I0(\bottom_right_0_reg_n_0_[10] ),
.I1(Lxx_00__1_carry__1_i_9_n_0),
.I2(\top_left_0_reg_n_0_[9] ),
.I3(\top_right_0_reg_n_0_[9] ),
.I4(\bottom_left_0_reg_n_0_[9] ),
.O(Lxx_00__1_carry__1_i_1_n_0));
LUT3 #(
.INIT(8'h96))
Lxx_00__1_carry__1_i_10
(.I0(\bottom_left_0_reg_n_0_[9] ),
.I1(\top_right_0_reg_n_0_[9] ),
.I2(\top_left_0_reg_n_0_[9] ),
.O(Lxx_00__1_carry__1_i_10_n_0));
LUT3 #(
.INIT(8'h96))
Lxx_00__1_carry__1_i_11
(.I0(\bottom_left_0_reg_n_0_[8] ),
.I1(\top_right_0_reg_n_0_[8] ),
.I2(\top_left_0_reg_n_0_[8] ),
.O(Lxx_00__1_carry__1_i_11_n_0));
LUT3 #(
.INIT(8'h96))
Lxx_00__1_carry__1_i_12
(.I0(\bottom_left_0_reg_n_0_[11] ),
.I1(\top_right_0_reg_n_0_[11] ),
.I2(\top_left_0_reg_n_0_[11] ),
.O(Lxx_00__1_carry__1_i_12_n_0));
LUT5 #(
.INIT(32'h88E8E8EE))
Lxx_00__1_carry__1_i_2
(.I0(\bottom_right_0_reg_n_0_[9] ),
.I1(Lxx_00__1_carry__1_i_10_n_0),
.I2(\top_left_0_reg_n_0_[8] ),
.I3(\top_right_0_reg_n_0_[8] ),
.I4(\bottom_left_0_reg_n_0_[8] ),
.O(Lxx_00__1_carry__1_i_2_n_0));
LUT5 #(
.INIT(32'h88E8E8EE))
Lxx_00__1_carry__1_i_3
(.I0(\bottom_right_0_reg_n_0_[8] ),
.I1(Lxx_00__1_carry__1_i_11_n_0),
.I2(\top_left_0_reg_n_0_[7] ),
.I3(\top_right_0_reg_n_0_[7] ),
.I4(\bottom_left_0_reg_n_0_[7] ),
.O(Lxx_00__1_carry__1_i_3_n_0));
LUT5 #(
.INIT(32'h88E8E8EE))
Lxx_00__1_carry__1_i_4
(.I0(\bottom_right_0_reg_n_0_[7] ),
.I1(Lxx_00__1_carry__0_i_12_n_0),
.I2(\top_left_0_reg_n_0_[6] ),
.I3(\top_right_0_reg_n_0_[6] ),
.I4(\bottom_left_0_reg_n_0_[6] ),
.O(Lxx_00__1_carry__1_i_4_n_0));
LUT6 #(
.INIT(64'hA665599A599AA665))
Lxx_00__1_carry__1_i_5
(.I0(Lxx_00__1_carry__1_i_1_n_0),
.I1(\top_left_0_reg_n_0_[10] ),
.I2(\top_right_0_reg_n_0_[10] ),
.I3(\bottom_left_0_reg_n_0_[10] ),
.I4(\bottom_right_0_reg_n_0_[11] ),
.I5(Lxx_00__1_carry__1_i_12_n_0),
.O(Lxx_00__1_carry__1_i_5_n_0));
LUT6 #(
.INIT(64'hA665599A599AA665))
Lxx_00__1_carry__1_i_6
(.I0(Lxx_00__1_carry__1_i_2_n_0),
.I1(\top_left_0_reg_n_0_[9] ),
.I2(\top_right_0_reg_n_0_[9] ),
.I3(\bottom_left_0_reg_n_0_[9] ),
.I4(\bottom_right_0_reg_n_0_[10] ),
.I5(Lxx_00__1_carry__1_i_9_n_0),
.O(Lxx_00__1_carry__1_i_6_n_0));
LUT6 #(
.INIT(64'hA665599A599AA665))
Lxx_00__1_carry__1_i_7
(.I0(Lxx_00__1_carry__1_i_3_n_0),
.I1(\top_left_0_reg_n_0_[8] ),
.I2(\top_right_0_reg_n_0_[8] ),
.I3(\bottom_left_0_reg_n_0_[8] ),
.I4(\bottom_right_0_reg_n_0_[9] ),
.I5(Lxx_00__1_carry__1_i_10_n_0),
.O(Lxx_00__1_carry__1_i_7_n_0));
LUT6 #(
.INIT(64'hA665599A599AA665))
Lxx_00__1_carry__1_i_8
(.I0(Lxx_00__1_carry__1_i_4_n_0),
.I1(\top_left_0_reg_n_0_[7] ),
.I2(\top_right_0_reg_n_0_[7] ),
.I3(\bottom_left_0_reg_n_0_[7] ),
.I4(\bottom_right_0_reg_n_0_[8] ),
.I5(Lxx_00__1_carry__1_i_11_n_0),
.O(Lxx_00__1_carry__1_i_8_n_0));
LUT3 #(
.INIT(8'h96))
Lxx_00__1_carry__1_i_9
(.I0(\bottom_left_0_reg_n_0_[10] ),
.I1(\top_right_0_reg_n_0_[10] ),
.I2(\top_left_0_reg_n_0_[10] ),
.O(Lxx_00__1_carry__1_i_9_n_0));
CARRY4 Lxx_00__1_carry__2
(.CI(Lxx_00__1_carry__1_n_0),
.CO({NLW_Lxx_00__1_carry__2_CO_UNCONNECTED[3],Lxx_00__1_carry__2_n_1,Lxx_00__1_carry__2_n_2,Lxx_00__1_carry__2_n_3}),
.CYINIT(1'b0),
.DI({1'b0,Lxx_00__1_carry__2_i_1_n_0,Lxx_00__1_carry__2_i_2_n_0,Lxx_00__1_carry__2_i_3_n_0}),
.O(Lxx_00[15:12]),
.S({Lxx_00__1_carry__2_i_4_n_0,Lxx_00__1_carry__2_i_5_n_0,Lxx_00__1_carry__2_i_6_n_0,Lxx_00__1_carry__2_i_7_n_0}));
LUT5 #(
.INIT(32'h88E8E8EE))
Lxx_00__1_carry__2_i_1
(.I0(\bottom_right_0_reg_n_0_[13] ),
.I1(Lxx_00__1_carry__2_i_8_n_0),
.I2(\top_left_0_reg_n_0_[12] ),
.I3(\top_right_0_reg_n_0_[12] ),
.I4(\bottom_left_0_reg_n_0_[12] ),
.O(Lxx_00__1_carry__2_i_1_n_0));
(* SOFT_HLUTNM = "soft_lutpair24" *)
LUT3 #(
.INIT(8'h2B))
Lxx_00__1_carry__2_i_10
(.I0(\top_left_0_reg_n_0_[13] ),
.I1(\top_right_0_reg_n_0_[13] ),
.I2(\bottom_left_0_reg_n_0_[13] ),
.O(Lxx_00__1_carry__2_i_10_n_0));
LUT4 #(
.INIT(16'h6996))
Lxx_00__1_carry__2_i_11
(.I0(\top_right_0_reg_n_0_[15] ),
.I1(\bottom_left_0_reg_n_0_[15] ),
.I2(\bottom_right_0_reg_n_0_[15] ),
.I3(\top_left_0_reg_n_0_[15] ),
.O(Lxx_00__1_carry__2_i_11_n_0));
LUT3 #(
.INIT(8'h96))
Lxx_00__1_carry__2_i_12
(.I0(\bottom_left_0_reg_n_0_[14] ),
.I1(\top_right_0_reg_n_0_[14] ),
.I2(\top_left_0_reg_n_0_[14] ),
.O(Lxx_00__1_carry__2_i_12_n_0));
LUT5 #(
.INIT(32'h88E8E8EE))
Lxx_00__1_carry__2_i_2
(.I0(\bottom_right_0_reg_n_0_[12] ),
.I1(Lxx_00__1_carry__2_i_9_n_0),
.I2(\top_left_0_reg_n_0_[11] ),
.I3(\top_right_0_reg_n_0_[11] ),
.I4(\bottom_left_0_reg_n_0_[11] ),
.O(Lxx_00__1_carry__2_i_2_n_0));
LUT5 #(
.INIT(32'h88E8E8EE))
Lxx_00__1_carry__2_i_3
(.I0(\bottom_right_0_reg_n_0_[11] ),
.I1(Lxx_00__1_carry__1_i_12_n_0),
.I2(\top_left_0_reg_n_0_[10] ),
.I3(\top_right_0_reg_n_0_[10] ),
.I4(\bottom_left_0_reg_n_0_[10] ),
.O(Lxx_00__1_carry__2_i_3_n_0));
LUT6 #(
.INIT(64'h178181E8E87E7E17))
Lxx_00__1_carry__2_i_4
(.I0(Lxx_00__1_carry__2_i_10_n_0),
.I1(\bottom_right_0_reg_n_0_[14] ),
.I2(\top_left_0_reg_n_0_[14] ),
.I3(\top_right_0_reg_n_0_[14] ),
.I4(\bottom_left_0_reg_n_0_[14] ),
.I5(Lxx_00__1_carry__2_i_11_n_0),
.O(Lxx_00__1_carry__2_i_4_n_0));
LUT6 #(
.INIT(64'hA665599A599AA665))
Lxx_00__1_carry__2_i_5
(.I0(Lxx_00__1_carry__2_i_1_n_0),
.I1(\top_left_0_reg_n_0_[13] ),
.I2(\top_right_0_reg_n_0_[13] ),
.I3(\bottom_left_0_reg_n_0_[13] ),
.I4(\bottom_right_0_reg_n_0_[14] ),
.I5(Lxx_00__1_carry__2_i_12_n_0),
.O(Lxx_00__1_carry__2_i_5_n_0));
LUT6 #(
.INIT(64'hA665599A599AA665))
Lxx_00__1_carry__2_i_6
(.I0(Lxx_00__1_carry__2_i_2_n_0),
.I1(\top_left_0_reg_n_0_[12] ),
.I2(\top_right_0_reg_n_0_[12] ),
.I3(\bottom_left_0_reg_n_0_[12] ),
.I4(\bottom_right_0_reg_n_0_[13] ),
.I5(Lxx_00__1_carry__2_i_8_n_0),
.O(Lxx_00__1_carry__2_i_6_n_0));
LUT6 #(
.INIT(64'hA665599A599AA665))
Lxx_00__1_carry__2_i_7
(.I0(Lxx_00__1_carry__2_i_3_n_0),
.I1(\top_left_0_reg_n_0_[11] ),
.I2(\top_right_0_reg_n_0_[11] ),
.I3(\bottom_left_0_reg_n_0_[11] ),
.I4(\bottom_right_0_reg_n_0_[12] ),
.I5(Lxx_00__1_carry__2_i_9_n_0),
.O(Lxx_00__1_carry__2_i_7_n_0));
(* SOFT_HLUTNM = "soft_lutpair24" *)
LUT3 #(
.INIT(8'h96))
Lxx_00__1_carry__2_i_8
(.I0(\bottom_left_0_reg_n_0_[13] ),
.I1(\top_right_0_reg_n_0_[13] ),
.I2(\top_left_0_reg_n_0_[13] ),
.O(Lxx_00__1_carry__2_i_8_n_0));
LUT3 #(
.INIT(8'h96))
Lxx_00__1_carry__2_i_9
(.I0(\bottom_left_0_reg_n_0_[12] ),
.I1(\top_right_0_reg_n_0_[12] ),
.I2(\top_left_0_reg_n_0_[12] ),
.O(Lxx_00__1_carry__2_i_9_n_0));
LUT6 #(
.INIT(64'h8228EBBEEBBEEBBE))
Lxx_00__1_carry_i_1
(.I0(\bottom_right_0_reg_n_0_[2] ),
.I1(\top_left_0_reg_n_0_[2] ),
.I2(\top_right_0_reg_n_0_[2] ),
.I3(\bottom_left_0_reg_n_0_[2] ),
.I4(\bottom_left_0_reg_n_0_[1] ),
.I5(\top_right_0_reg_n_0_[1] ),
.O(Lxx_00__1_carry_i_1_n_0));
LUT4 #(
.INIT(16'hF990))
Lxx_00__1_carry_i_2
(.I0(\bottom_left_0_reg_n_0_[1] ),
.I1(\top_right_0_reg_n_0_[1] ),
.I2(\top_left_0_reg_n_0_[1] ),
.I3(\bottom_right_0_reg_n_0_[1] ),
.O(Lxx_00__1_carry_i_2_n_0));
LUT4 #(
.INIT(16'h9669))
Lxx_00__1_carry_i_3
(.I0(\top_right_0_reg_n_0_[1] ),
.I1(\bottom_left_0_reg_n_0_[1] ),
.I2(\bottom_right_0_reg_n_0_[1] ),
.I3(\top_left_0_reg_n_0_[1] ),
.O(Lxx_00__1_carry_i_3_n_0));
LUT6 #(
.INIT(64'hA665599A599AA665))
Lxx_00__1_carry_i_4
(.I0(Lxx_00__1_carry_i_1_n_0),
.I1(\top_left_0_reg_n_0_[2] ),
.I2(\top_right_0_reg_n_0_[2] ),
.I3(\bottom_left_0_reg_n_0_[2] ),
.I4(\bottom_right_0_reg_n_0_[3] ),
.I5(Lxx_00__1_carry_i_8_n_0),
.O(Lxx_00__1_carry_i_4_n_0));
LUT5 #(
.INIT(32'h96696969))
Lxx_00__1_carry_i_5
(.I0(Lxx_00__1_carry_i_2_n_0),
.I1(\bottom_right_0_reg_n_0_[2] ),
.I2(Lxx_00__1_carry_i_9_n_0),
.I3(\bottom_left_0_reg_n_0_[1] ),
.I4(\top_right_0_reg_n_0_[1] ),
.O(Lxx_00__1_carry_i_5_n_0));
LUT4 #(
.INIT(16'hA665))
Lxx_00__1_carry_i_6
(.I0(Lxx_00__1_carry_i_3_n_0),
.I1(\top_left_0_reg_n_0_[0] ),
.I2(\top_right_0_reg_n_0_[0] ),
.I3(\bottom_left_0_reg_n_0_[0] ),
.O(Lxx_00__1_carry_i_6_n_0));
LUT4 #(
.INIT(16'h6996))
Lxx_00__1_carry_i_7
(.I0(\bottom_left_0_reg_n_0_[0] ),
.I1(\top_right_0_reg_n_0_[0] ),
.I2(\top_left_0_reg_n_0_[0] ),
.I3(\bottom_right_0_reg_n_0_[0] ),
.O(Lxx_00__1_carry_i_7_n_0));
LUT3 #(
.INIT(8'h96))
Lxx_00__1_carry_i_8
(.I0(\bottom_left_0_reg_n_0_[3] ),
.I1(\top_right_0_reg_n_0_[3] ),
.I2(\top_left_0_reg_n_0_[3] ),
.O(Lxx_00__1_carry_i_8_n_0));
LUT3 #(
.INIT(8'h96))
Lxx_00__1_carry_i_9
(.I0(\bottom_left_0_reg_n_0_[2] ),
.I1(\top_right_0_reg_n_0_[2] ),
.I2(\top_left_0_reg_n_0_[2] ),
.O(Lxx_00__1_carry_i_9_n_0));
FDRE #(
.INIT(1'b0))
\Lxx_0_reg[0]
(.C(clk_x16),
.CE(x),
.D(Lxx_00[0]),
.Q(Lxx_0[0]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxx_0_reg[10]
(.C(clk_x16),
.CE(x),
.D(Lxx_00[10]),
.Q(Lxx_0[10]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxx_0_reg[11]
(.C(clk_x16),
.CE(x),
.D(Lxx_00[11]),
.Q(Lxx_0[11]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxx_0_reg[12]
(.C(clk_x16),
.CE(x),
.D(Lxx_00[12]),
.Q(Lxx_0[12]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxx_0_reg[13]
(.C(clk_x16),
.CE(x),
.D(Lxx_00[13]),
.Q(Lxx_0[13]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxx_0_reg[14]
(.C(clk_x16),
.CE(x),
.D(Lxx_00[14]),
.Q(Lxx_0[14]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxx_0_reg[15]
(.C(clk_x16),
.CE(x),
.D(Lxx_00[15]),
.Q(Lxx_0[15]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxx_0_reg[1]
(.C(clk_x16),
.CE(x),
.D(Lxx_00[1]),
.Q(Lxx_0[1]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxx_0_reg[2]
(.C(clk_x16),
.CE(x),
.D(Lxx_00[2]),
.Q(Lxx_0[2]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxx_0_reg[3]
(.C(clk_x16),
.CE(x),
.D(Lxx_00[3]),
.Q(Lxx_0[3]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxx_0_reg[4]
(.C(clk_x16),
.CE(x),
.D(Lxx_00[4]),
.Q(Lxx_0[4]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxx_0_reg[5]
(.C(clk_x16),
.CE(x),
.D(Lxx_00[5]),
.Q(Lxx_0[5]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxx_0_reg[6]
(.C(clk_x16),
.CE(x),
.D(Lxx_00[6]),
.Q(Lxx_0[6]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxx_0_reg[7]
(.C(clk_x16),
.CE(x),
.D(Lxx_00[7]),
.Q(Lxx_0[7]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxx_0_reg[8]
(.C(clk_x16),
.CE(x),
.D(Lxx_00[8]),
.Q(Lxx_0[8]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxx_0_reg[9]
(.C(clk_x16),
.CE(x),
.D(Lxx_00[9]),
.Q(Lxx_0[9]),
.R(1'b0));
CARRY4 Lxx_11__1_carry
(.CI(1'b0),
.CO({Lxx_11__1_carry_n_0,Lxx_11__1_carry_n_1,Lxx_11__1_carry_n_2,Lxx_11__1_carry_n_3}),
.CYINIT(1'b0),
.DI({Lxx_11__1_carry_i_1_n_0,Lxx_11__1_carry_i_2_n_0,Lxx_11__1_carry_i_3_n_0,\bottom_right_1_reg_n_0_[0] }),
.O(Lxx_11[3:0]),
.S({Lxx_11__1_carry_i_4_n_0,Lxx_11__1_carry_i_5_n_0,Lxx_11__1_carry_i_6_n_0,Lxx_11__1_carry_i_7_n_0}));
CARRY4 Lxx_11__1_carry__0
(.CI(Lxx_11__1_carry_n_0),
.CO({Lxx_11__1_carry__0_n_0,Lxx_11__1_carry__0_n_1,Lxx_11__1_carry__0_n_2,Lxx_11__1_carry__0_n_3}),
.CYINIT(1'b0),
.DI({Lxx_11__1_carry__0_i_1_n_0,Lxx_11__1_carry__0_i_2_n_0,Lxx_11__1_carry__0_i_3_n_0,Lxx_11__1_carry__0_i_4_n_0}),
.O(Lxx_11[7:4]),
.S({Lxx_11__1_carry__0_i_5_n_0,Lxx_11__1_carry__0_i_6_n_0,Lxx_11__1_carry__0_i_7_n_0,Lxx_11__1_carry__0_i_8_n_0}));
LUT5 #(
.INIT(32'h88E8E8EE))
Lxx_11__1_carry__0_i_1
(.I0(\bottom_right_1_reg_n_0_[6] ),
.I1(Lxx_11__1_carry__0_i_9_n_0),
.I2(top_left_1[5]),
.I3(\top_right_1_reg_n_0_[5] ),
.I4(bottom_left_1[5]),
.O(Lxx_11__1_carry__0_i_1_n_0));
LUT3 #(
.INIT(8'h96))
Lxx_11__1_carry__0_i_10
(.I0(bottom_left_1[5]),
.I1(\top_right_1_reg_n_0_[5] ),
.I2(top_left_1[5]),
.O(Lxx_11__1_carry__0_i_10_n_0));
LUT3 #(
.INIT(8'h96))
Lxx_11__1_carry__0_i_11
(.I0(bottom_left_1[4]),
.I1(\top_right_1_reg_n_0_[4] ),
.I2(top_left_1[4]),
.O(Lxx_11__1_carry__0_i_11_n_0));
LUT3 #(
.INIT(8'h96))
Lxx_11__1_carry__0_i_12
(.I0(bottom_left_1[7]),
.I1(\top_right_1_reg_n_0_[7] ),
.I2(top_left_1[7]),
.O(Lxx_11__1_carry__0_i_12_n_0));
LUT5 #(
.INIT(32'h88E8E8EE))
Lxx_11__1_carry__0_i_2
(.I0(\bottom_right_1_reg_n_0_[5] ),
.I1(Lxx_11__1_carry__0_i_10_n_0),
.I2(top_left_1[4]),
.I3(\top_right_1_reg_n_0_[4] ),
.I4(bottom_left_1[4]),
.O(Lxx_11__1_carry__0_i_2_n_0));
LUT5 #(
.INIT(32'h88E8E8EE))
Lxx_11__1_carry__0_i_3
(.I0(\bottom_right_1_reg_n_0_[4] ),
.I1(Lxx_11__1_carry__0_i_11_n_0),
.I2(top_left_1[3]),
.I3(\top_right_1_reg_n_0_[3] ),
.I4(bottom_left_1[3]),
.O(Lxx_11__1_carry__0_i_3_n_0));
LUT5 #(
.INIT(32'h88E8E8EE))
Lxx_11__1_carry__0_i_4
(.I0(\bottom_right_1_reg_n_0_[3] ),
.I1(Lxx_11__1_carry_i_8_n_0),
.I2(top_left_1[2]),
.I3(\top_right_1_reg_n_0_[2] ),
.I4(bottom_left_1[2]),
.O(Lxx_11__1_carry__0_i_4_n_0));
LUT6 #(
.INIT(64'hA665599A599AA665))
Lxx_11__1_carry__0_i_5
(.I0(Lxx_11__1_carry__0_i_1_n_0),
.I1(top_left_1[6]),
.I2(\top_right_1_reg_n_0_[6] ),
.I3(bottom_left_1[6]),
.I4(\bottom_right_1_reg_n_0_[7] ),
.I5(Lxx_11__1_carry__0_i_12_n_0),
.O(Lxx_11__1_carry__0_i_5_n_0));
LUT6 #(
.INIT(64'hA665599A599AA665))
Lxx_11__1_carry__0_i_6
(.I0(Lxx_11__1_carry__0_i_2_n_0),
.I1(top_left_1[5]),
.I2(\top_right_1_reg_n_0_[5] ),
.I3(bottom_left_1[5]),
.I4(\bottom_right_1_reg_n_0_[6] ),
.I5(Lxx_11__1_carry__0_i_9_n_0),
.O(Lxx_11__1_carry__0_i_6_n_0));
LUT6 #(
.INIT(64'hA665599A599AA665))
Lxx_11__1_carry__0_i_7
(.I0(Lxx_11__1_carry__0_i_3_n_0),
.I1(top_left_1[4]),
.I2(\top_right_1_reg_n_0_[4] ),
.I3(bottom_left_1[4]),
.I4(\bottom_right_1_reg_n_0_[5] ),
.I5(Lxx_11__1_carry__0_i_10_n_0),
.O(Lxx_11__1_carry__0_i_7_n_0));
LUT6 #(
.INIT(64'hA665599A599AA665))
Lxx_11__1_carry__0_i_8
(.I0(Lxx_11__1_carry__0_i_4_n_0),
.I1(top_left_1[3]),
.I2(\top_right_1_reg_n_0_[3] ),
.I3(bottom_left_1[3]),
.I4(\bottom_right_1_reg_n_0_[4] ),
.I5(Lxx_11__1_carry__0_i_11_n_0),
.O(Lxx_11__1_carry__0_i_8_n_0));
LUT3 #(
.INIT(8'h96))
Lxx_11__1_carry__0_i_9
(.I0(bottom_left_1[6]),
.I1(\top_right_1_reg_n_0_[6] ),
.I2(top_left_1[6]),
.O(Lxx_11__1_carry__0_i_9_n_0));
CARRY4 Lxx_11__1_carry__1
(.CI(Lxx_11__1_carry__0_n_0),
.CO({Lxx_11__1_carry__1_n_0,Lxx_11__1_carry__1_n_1,Lxx_11__1_carry__1_n_2,Lxx_11__1_carry__1_n_3}),
.CYINIT(1'b0),
.DI({Lxx_11__1_carry__1_i_1_n_0,Lxx_11__1_carry__1_i_2_n_0,Lxx_11__1_carry__1_i_3_n_0,Lxx_11__1_carry__1_i_4_n_0}),
.O(Lxx_11[11:8]),
.S({Lxx_11__1_carry__1_i_5_n_0,Lxx_11__1_carry__1_i_6_n_0,Lxx_11__1_carry__1_i_7_n_0,Lxx_11__1_carry__1_i_8_n_0}));
LUT5 #(
.INIT(32'h88E8E8EE))
Lxx_11__1_carry__1_i_1
(.I0(\bottom_right_1_reg_n_0_[10] ),
.I1(Lxx_11__1_carry__1_i_9_n_0),
.I2(top_left_1[9]),
.I3(\top_right_1_reg_n_0_[9] ),
.I4(bottom_left_1[9]),
.O(Lxx_11__1_carry__1_i_1_n_0));
LUT3 #(
.INIT(8'h96))
Lxx_11__1_carry__1_i_10
(.I0(bottom_left_1[9]),
.I1(\top_right_1_reg_n_0_[9] ),
.I2(top_left_1[9]),
.O(Lxx_11__1_carry__1_i_10_n_0));
LUT3 #(
.INIT(8'h96))
Lxx_11__1_carry__1_i_11
(.I0(bottom_left_1[8]),
.I1(\top_right_1_reg_n_0_[8] ),
.I2(top_left_1[8]),
.O(Lxx_11__1_carry__1_i_11_n_0));
LUT3 #(
.INIT(8'h96))
Lxx_11__1_carry__1_i_12
(.I0(bottom_left_1[11]),
.I1(\top_right_1_reg_n_0_[11] ),
.I2(top_left_1[11]),
.O(Lxx_11__1_carry__1_i_12_n_0));
LUT5 #(
.INIT(32'h88E8E8EE))
Lxx_11__1_carry__1_i_2
(.I0(\bottom_right_1_reg_n_0_[9] ),
.I1(Lxx_11__1_carry__1_i_10_n_0),
.I2(top_left_1[8]),
.I3(\top_right_1_reg_n_0_[8] ),
.I4(bottom_left_1[8]),
.O(Lxx_11__1_carry__1_i_2_n_0));
LUT5 #(
.INIT(32'h88E8E8EE))
Lxx_11__1_carry__1_i_3
(.I0(\bottom_right_1_reg_n_0_[8] ),
.I1(Lxx_11__1_carry__1_i_11_n_0),
.I2(top_left_1[7]),
.I3(\top_right_1_reg_n_0_[7] ),
.I4(bottom_left_1[7]),
.O(Lxx_11__1_carry__1_i_3_n_0));
LUT5 #(
.INIT(32'h88E8E8EE))
Lxx_11__1_carry__1_i_4
(.I0(\bottom_right_1_reg_n_0_[7] ),
.I1(Lxx_11__1_carry__0_i_12_n_0),
.I2(top_left_1[6]),
.I3(\top_right_1_reg_n_0_[6] ),
.I4(bottom_left_1[6]),
.O(Lxx_11__1_carry__1_i_4_n_0));
LUT6 #(
.INIT(64'hA665599A599AA665))
Lxx_11__1_carry__1_i_5
(.I0(Lxx_11__1_carry__1_i_1_n_0),
.I1(top_left_1[10]),
.I2(\top_right_1_reg_n_0_[10] ),
.I3(bottom_left_1[10]),
.I4(\bottom_right_1_reg_n_0_[11] ),
.I5(Lxx_11__1_carry__1_i_12_n_0),
.O(Lxx_11__1_carry__1_i_5_n_0));
LUT6 #(
.INIT(64'hA665599A599AA665))
Lxx_11__1_carry__1_i_6
(.I0(Lxx_11__1_carry__1_i_2_n_0),
.I1(top_left_1[9]),
.I2(\top_right_1_reg_n_0_[9] ),
.I3(bottom_left_1[9]),
.I4(\bottom_right_1_reg_n_0_[10] ),
.I5(Lxx_11__1_carry__1_i_9_n_0),
.O(Lxx_11__1_carry__1_i_6_n_0));
LUT6 #(
.INIT(64'hA665599A599AA665))
Lxx_11__1_carry__1_i_7
(.I0(Lxx_11__1_carry__1_i_3_n_0),
.I1(top_left_1[8]),
.I2(\top_right_1_reg_n_0_[8] ),
.I3(bottom_left_1[8]),
.I4(\bottom_right_1_reg_n_0_[9] ),
.I5(Lxx_11__1_carry__1_i_10_n_0),
.O(Lxx_11__1_carry__1_i_7_n_0));
LUT6 #(
.INIT(64'hA665599A599AA665))
Lxx_11__1_carry__1_i_8
(.I0(Lxx_11__1_carry__1_i_4_n_0),
.I1(top_left_1[7]),
.I2(\top_right_1_reg_n_0_[7] ),
.I3(bottom_left_1[7]),
.I4(\bottom_right_1_reg_n_0_[8] ),
.I5(Lxx_11__1_carry__1_i_11_n_0),
.O(Lxx_11__1_carry__1_i_8_n_0));
LUT3 #(
.INIT(8'h96))
Lxx_11__1_carry__1_i_9
(.I0(bottom_left_1[10]),
.I1(\top_right_1_reg_n_0_[10] ),
.I2(top_left_1[10]),
.O(Lxx_11__1_carry__1_i_9_n_0));
CARRY4 Lxx_11__1_carry__2
(.CI(Lxx_11__1_carry__1_n_0),
.CO({NLW_Lxx_11__1_carry__2_CO_UNCONNECTED[3],Lxx_11__1_carry__2_n_1,Lxx_11__1_carry__2_n_2,Lxx_11__1_carry__2_n_3}),
.CYINIT(1'b0),
.DI({1'b0,Lxx_11__1_carry__2_i_1_n_0,Lxx_11__1_carry__2_i_2_n_0,Lxx_11__1_carry__2_i_3_n_0}),
.O(Lxx_11[15:12]),
.S({Lxx_11__1_carry__2_i_4_n_0,Lxx_11__1_carry__2_i_5_n_0,Lxx_11__1_carry__2_i_6_n_0,Lxx_11__1_carry__2_i_7_n_0}));
LUT5 #(
.INIT(32'h88E8E8EE))
Lxx_11__1_carry__2_i_1
(.I0(\bottom_right_1_reg_n_0_[13] ),
.I1(Lxx_11__1_carry__2_i_8_n_0),
.I2(top_left_1[12]),
.I3(\top_right_1_reg_n_0_[12] ),
.I4(bottom_left_1[12]),
.O(Lxx_11__1_carry__2_i_1_n_0));
(* SOFT_HLUTNM = "soft_lutpair25" *)
LUT3 #(
.INIT(8'h2B))
Lxx_11__1_carry__2_i_10
(.I0(top_left_1[13]),
.I1(\top_right_1_reg_n_0_[13] ),
.I2(bottom_left_1[13]),
.O(Lxx_11__1_carry__2_i_10_n_0));
LUT4 #(
.INIT(16'h6996))
Lxx_11__1_carry__2_i_11
(.I0(\top_right_1_reg_n_0_[15] ),
.I1(bottom_left_1[15]),
.I2(\bottom_right_1_reg_n_0_[15] ),
.I3(top_left_1[15]),
.O(Lxx_11__1_carry__2_i_11_n_0));
LUT3 #(
.INIT(8'h96))
Lxx_11__1_carry__2_i_12
(.I0(bottom_left_1[14]),
.I1(\top_right_1_reg_n_0_[14] ),
.I2(top_left_1[14]),
.O(Lxx_11__1_carry__2_i_12_n_0));
LUT5 #(
.INIT(32'h88E8E8EE))
Lxx_11__1_carry__2_i_2
(.I0(\bottom_right_1_reg_n_0_[12] ),
.I1(Lxx_11__1_carry__2_i_9_n_0),
.I2(top_left_1[11]),
.I3(\top_right_1_reg_n_0_[11] ),
.I4(bottom_left_1[11]),
.O(Lxx_11__1_carry__2_i_2_n_0));
LUT5 #(
.INIT(32'h88E8E8EE))
Lxx_11__1_carry__2_i_3
(.I0(\bottom_right_1_reg_n_0_[11] ),
.I1(Lxx_11__1_carry__1_i_12_n_0),
.I2(top_left_1[10]),
.I3(\top_right_1_reg_n_0_[10] ),
.I4(bottom_left_1[10]),
.O(Lxx_11__1_carry__2_i_3_n_0));
LUT6 #(
.INIT(64'h178181E8E87E7E17))
Lxx_11__1_carry__2_i_4
(.I0(Lxx_11__1_carry__2_i_10_n_0),
.I1(\bottom_right_1_reg_n_0_[14] ),
.I2(top_left_1[14]),
.I3(\top_right_1_reg_n_0_[14] ),
.I4(bottom_left_1[14]),
.I5(Lxx_11__1_carry__2_i_11_n_0),
.O(Lxx_11__1_carry__2_i_4_n_0));
LUT6 #(
.INIT(64'hA665599A599AA665))
Lxx_11__1_carry__2_i_5
(.I0(Lxx_11__1_carry__2_i_1_n_0),
.I1(top_left_1[13]),
.I2(\top_right_1_reg_n_0_[13] ),
.I3(bottom_left_1[13]),
.I4(\bottom_right_1_reg_n_0_[14] ),
.I5(Lxx_11__1_carry__2_i_12_n_0),
.O(Lxx_11__1_carry__2_i_5_n_0));
LUT6 #(
.INIT(64'hA665599A599AA665))
Lxx_11__1_carry__2_i_6
(.I0(Lxx_11__1_carry__2_i_2_n_0),
.I1(top_left_1[12]),
.I2(\top_right_1_reg_n_0_[12] ),
.I3(bottom_left_1[12]),
.I4(\bottom_right_1_reg_n_0_[13] ),
.I5(Lxx_11__1_carry__2_i_8_n_0),
.O(Lxx_11__1_carry__2_i_6_n_0));
LUT6 #(
.INIT(64'hA665599A599AA665))
Lxx_11__1_carry__2_i_7
(.I0(Lxx_11__1_carry__2_i_3_n_0),
.I1(top_left_1[11]),
.I2(\top_right_1_reg_n_0_[11] ),
.I3(bottom_left_1[11]),
.I4(\bottom_right_1_reg_n_0_[12] ),
.I5(Lxx_11__1_carry__2_i_9_n_0),
.O(Lxx_11__1_carry__2_i_7_n_0));
(* SOFT_HLUTNM = "soft_lutpair25" *)
LUT3 #(
.INIT(8'h96))
Lxx_11__1_carry__2_i_8
(.I0(bottom_left_1[13]),
.I1(\top_right_1_reg_n_0_[13] ),
.I2(top_left_1[13]),
.O(Lxx_11__1_carry__2_i_8_n_0));
LUT3 #(
.INIT(8'h96))
Lxx_11__1_carry__2_i_9
(.I0(bottom_left_1[12]),
.I1(\top_right_1_reg_n_0_[12] ),
.I2(top_left_1[12]),
.O(Lxx_11__1_carry__2_i_9_n_0));
LUT6 #(
.INIT(64'h8228EBBEEBBEEBBE))
Lxx_11__1_carry_i_1
(.I0(\bottom_right_1_reg_n_0_[2] ),
.I1(top_left_1[2]),
.I2(\top_right_1_reg_n_0_[2] ),
.I3(bottom_left_1[2]),
.I4(bottom_left_1[1]),
.I5(\top_right_1_reg_n_0_[1] ),
.O(Lxx_11__1_carry_i_1_n_0));
LUT4 #(
.INIT(16'hF990))
Lxx_11__1_carry_i_2
(.I0(bottom_left_1[1]),
.I1(\top_right_1_reg_n_0_[1] ),
.I2(top_left_1[1]),
.I3(\bottom_right_1_reg_n_0_[1] ),
.O(Lxx_11__1_carry_i_2_n_0));
LUT4 #(
.INIT(16'h9669))
Lxx_11__1_carry_i_3
(.I0(\top_right_1_reg_n_0_[1] ),
.I1(bottom_left_1[1]),
.I2(\bottom_right_1_reg_n_0_[1] ),
.I3(top_left_1[1]),
.O(Lxx_11__1_carry_i_3_n_0));
LUT6 #(
.INIT(64'hA665599A599AA665))
Lxx_11__1_carry_i_4
(.I0(Lxx_11__1_carry_i_1_n_0),
.I1(top_left_1[2]),
.I2(\top_right_1_reg_n_0_[2] ),
.I3(bottom_left_1[2]),
.I4(\bottom_right_1_reg_n_0_[3] ),
.I5(Lxx_11__1_carry_i_8_n_0),
.O(Lxx_11__1_carry_i_4_n_0));
LUT5 #(
.INIT(32'h96696969))
Lxx_11__1_carry_i_5
(.I0(Lxx_11__1_carry_i_2_n_0),
.I1(\bottom_right_1_reg_n_0_[2] ),
.I2(Lxx_11__1_carry_i_9_n_0),
.I3(bottom_left_1[1]),
.I4(\top_right_1_reg_n_0_[1] ),
.O(Lxx_11__1_carry_i_5_n_0));
LUT4 #(
.INIT(16'hA665))
Lxx_11__1_carry_i_6
(.I0(Lxx_11__1_carry_i_3_n_0),
.I1(top_left_1[0]),
.I2(\top_right_1_reg_n_0_[0] ),
.I3(bottom_left_1[0]),
.O(Lxx_11__1_carry_i_6_n_0));
LUT4 #(
.INIT(16'h6996))
Lxx_11__1_carry_i_7
(.I0(bottom_left_1[0]),
.I1(\top_right_1_reg_n_0_[0] ),
.I2(top_left_1[0]),
.I3(\bottom_right_1_reg_n_0_[0] ),
.O(Lxx_11__1_carry_i_7_n_0));
LUT3 #(
.INIT(8'h96))
Lxx_11__1_carry_i_8
(.I0(bottom_left_1[3]),
.I1(\top_right_1_reg_n_0_[3] ),
.I2(top_left_1[3]),
.O(Lxx_11__1_carry_i_8_n_0));
LUT3 #(
.INIT(8'h96))
Lxx_11__1_carry_i_9
(.I0(bottom_left_1[2]),
.I1(\top_right_1_reg_n_0_[2] ),
.I2(top_left_1[2]),
.O(Lxx_11__1_carry_i_9_n_0));
FDRE #(
.INIT(1'b0))
\Lxx_1_reg[10]
(.C(clk_x16),
.CE(y5),
.D(Lxx_11[9]),
.Q(Lxx_1[10]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxx_1_reg[11]
(.C(clk_x16),
.CE(y5),
.D(Lxx_11[10]),
.Q(Lxx_1[11]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxx_1_reg[12]
(.C(clk_x16),
.CE(y5),
.D(Lxx_11[11]),
.Q(Lxx_1[12]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxx_1_reg[13]
(.C(clk_x16),
.CE(y5),
.D(Lxx_11[12]),
.Q(Lxx_1[13]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxx_1_reg[14]
(.C(clk_x16),
.CE(y5),
.D(Lxx_11[13]),
.Q(Lxx_1[14]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxx_1_reg[15]
(.C(clk_x16),
.CE(y5),
.D(Lxx_11[14]),
.Q(Lxx_1[15]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxx_1_reg[1]
(.C(clk_x16),
.CE(y5),
.D(Lxx_11[0]),
.Q(Lxx_1[1]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxx_1_reg[2]
(.C(clk_x16),
.CE(y5),
.D(Lxx_11[1]),
.Q(Lxx_1[2]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxx_1_reg[3]
(.C(clk_x16),
.CE(y5),
.D(Lxx_11[2]),
.Q(Lxx_1[3]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxx_1_reg[4]
(.C(clk_x16),
.CE(y5),
.D(Lxx_11[3]),
.Q(Lxx_1[4]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxx_1_reg[5]
(.C(clk_x16),
.CE(y5),
.D(Lxx_11[4]),
.Q(Lxx_1[5]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxx_1_reg[6]
(.C(clk_x16),
.CE(y5),
.D(Lxx_11[5]),
.Q(Lxx_1[6]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxx_1_reg[7]
(.C(clk_x16),
.CE(y5),
.D(Lxx_11[6]),
.Q(Lxx_1[7]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxx_1_reg[8]
(.C(clk_x16),
.CE(y5),
.D(Lxx_11[7]),
.Q(Lxx_1[8]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxx_1_reg[9]
(.C(clk_x16),
.CE(y5),
.D(Lxx_11[8]),
.Q(Lxx_1[9]),
.R(1'b0));
LUT6 #(
.INIT(64'h0010000000000000))
\Lxx_2[15]_i_1
(.I0(cycle[3]),
.I1(\cycle_reg[0]_rep_n_0 ),
.I2(\cycle_reg[1]_rep_n_0 ),
.I3(cycle[2]),
.I4(rst),
.I5(active),
.O(\Lxx_2[15]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\Lxx_2_reg[0]
(.C(clk_x16),
.CE(\Lxx_2[15]_i_1_n_0 ),
.D(Lxx_00[0]),
.Q(\Lxx_2_reg_n_0_[0] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxx_2_reg[10]
(.C(clk_x16),
.CE(\Lxx_2[15]_i_1_n_0 ),
.D(Lxx_00[10]),
.Q(\Lxx_2_reg_n_0_[10] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxx_2_reg[11]
(.C(clk_x16),
.CE(\Lxx_2[15]_i_1_n_0 ),
.D(Lxx_00[11]),
.Q(\Lxx_2_reg_n_0_[11] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxx_2_reg[12]
(.C(clk_x16),
.CE(\Lxx_2[15]_i_1_n_0 ),
.D(Lxx_00[12]),
.Q(\Lxx_2_reg_n_0_[12] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxx_2_reg[13]
(.C(clk_x16),
.CE(\Lxx_2[15]_i_1_n_0 ),
.D(Lxx_00[13]),
.Q(\Lxx_2_reg_n_0_[13] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxx_2_reg[14]
(.C(clk_x16),
.CE(\Lxx_2[15]_i_1_n_0 ),
.D(Lxx_00[14]),
.Q(\Lxx_2_reg_n_0_[14] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxx_2_reg[15]
(.C(clk_x16),
.CE(\Lxx_2[15]_i_1_n_0 ),
.D(Lxx_00[15]),
.Q(\Lxx_2_reg_n_0_[15] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxx_2_reg[1]
(.C(clk_x16),
.CE(\Lxx_2[15]_i_1_n_0 ),
.D(Lxx_00[1]),
.Q(\Lxx_2_reg_n_0_[1] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxx_2_reg[2]
(.C(clk_x16),
.CE(\Lxx_2[15]_i_1_n_0 ),
.D(Lxx_00[2]),
.Q(\Lxx_2_reg_n_0_[2] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxx_2_reg[3]
(.C(clk_x16),
.CE(\Lxx_2[15]_i_1_n_0 ),
.D(Lxx_00[3]),
.Q(\Lxx_2_reg_n_0_[3] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxx_2_reg[4]
(.C(clk_x16),
.CE(\Lxx_2[15]_i_1_n_0 ),
.D(Lxx_00[4]),
.Q(\Lxx_2_reg_n_0_[4] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxx_2_reg[5]
(.C(clk_x16),
.CE(\Lxx_2[15]_i_1_n_0 ),
.D(Lxx_00[5]),
.Q(\Lxx_2_reg_n_0_[5] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxx_2_reg[6]
(.C(clk_x16),
.CE(\Lxx_2[15]_i_1_n_0 ),
.D(Lxx_00[6]),
.Q(\Lxx_2_reg_n_0_[6] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxx_2_reg[7]
(.C(clk_x16),
.CE(\Lxx_2[15]_i_1_n_0 ),
.D(Lxx_00[7]),
.Q(\Lxx_2_reg_n_0_[7] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxx_2_reg[8]
(.C(clk_x16),
.CE(\Lxx_2[15]_i_1_n_0 ),
.D(Lxx_00[8]),
.Q(\Lxx_2_reg_n_0_[8] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxx_2_reg[9]
(.C(clk_x16),
.CE(\Lxx_2[15]_i_1_n_0 ),
.D(Lxx_00[9]),
.Q(\Lxx_2_reg_n_0_[9] ),
.R(1'b0));
CARRY4 Lxy0__1_carry
(.CI(1'b0),
.CO({Lxy0__1_carry_n_0,Lxy0__1_carry_n_1,Lxy0__1_carry_n_2,Lxy0__1_carry_n_3}),
.CYINIT(1'b0),
.DI({Lxy0__1_carry_i_1_n_0,Lxy0__1_carry_i_2_n_0,Lxy0__1_carry_i_3_n_0,\Lxy_0_reg_n_0_[0] }),
.O({Lxy0__1_carry_n_4,Lxy0__1_carry_n_5,Lxy0__1_carry_n_6,Lxy0__1_carry_n_7}),
.S({Lxy0__1_carry_i_4_n_0,Lxy0__1_carry_i_5_n_0,Lxy0__1_carry_i_6_n_0,Lxy0__1_carry_i_7_n_0}));
CARRY4 Lxy0__1_carry__0
(.CI(Lxy0__1_carry_n_0),
.CO({Lxy0__1_carry__0_n_0,Lxy0__1_carry__0_n_1,Lxy0__1_carry__0_n_2,Lxy0__1_carry__0_n_3}),
.CYINIT(1'b0),
.DI({Lxy0__1_carry__0_i_1_n_0,Lxy0__1_carry__0_i_2_n_0,Lxy0__1_carry__0_i_3_n_0,Lxy0__1_carry__0_i_4_n_0}),
.O({Lxy0__1_carry__0_n_4,Lxy0__1_carry__0_n_5,Lxy0__1_carry__0_n_6,Lxy0__1_carry__0_n_7}),
.S({Lxy0__1_carry__0_i_5_n_0,Lxy0__1_carry__0_i_6_n_0,Lxy0__1_carry__0_i_7_n_0,Lxy0__1_carry__0_i_8_n_0}));
LUT5 #(
.INIT(32'h8E88EE8E))
Lxy0__1_carry__0_i_1
(.I0(\Lxy_0_reg_n_0_[6] ),
.I1(Lxy0__1_carry__0_i_9_n_0),
.I2(Lxy_3[5]),
.I3(Lxy_2[5]),
.I4(\Lxy_1_reg_n_0_[5] ),
.O(Lxy0__1_carry__0_i_1_n_0));
LUT3 #(
.INIT(8'h96))
Lxy0__1_carry__0_i_10
(.I0(Lxy_3[5]),
.I1(\Lxy_1_reg_n_0_[5] ),
.I2(Lxy_2[5]),
.O(Lxy0__1_carry__0_i_10_n_0));
LUT3 #(
.INIT(8'h96))
Lxy0__1_carry__0_i_11
(.I0(Lxy_3[4]),
.I1(\Lxy_1_reg_n_0_[4] ),
.I2(Lxy_2[4]),
.O(Lxy0__1_carry__0_i_11_n_0));
LUT3 #(
.INIT(8'h96))
Lxy0__1_carry__0_i_12
(.I0(Lxy_3[7]),
.I1(\Lxy_1_reg_n_0_[7] ),
.I2(Lxy_2[7]),
.O(Lxy0__1_carry__0_i_12_n_0));
LUT5 #(
.INIT(32'h8E88EE8E))
Lxy0__1_carry__0_i_2
(.I0(\Lxy_0_reg_n_0_[5] ),
.I1(Lxy0__1_carry__0_i_10_n_0),
.I2(Lxy_3[4]),
.I3(Lxy_2[4]),
.I4(\Lxy_1_reg_n_0_[4] ),
.O(Lxy0__1_carry__0_i_2_n_0));
LUT5 #(
.INIT(32'h8E88EE8E))
Lxy0__1_carry__0_i_3
(.I0(\Lxy_0_reg_n_0_[4] ),
.I1(Lxy0__1_carry__0_i_11_n_0),
.I2(Lxy_3[3]),
.I3(Lxy_2[3]),
.I4(\Lxy_1_reg_n_0_[3] ),
.O(Lxy0__1_carry__0_i_3_n_0));
LUT5 #(
.INIT(32'h8E88EE8E))
Lxy0__1_carry__0_i_4
(.I0(\Lxy_0_reg_n_0_[3] ),
.I1(Lxy0__1_carry_i_8_n_0),
.I2(Lxy_3[2]),
.I3(Lxy_2[2]),
.I4(\Lxy_1_reg_n_0_[2] ),
.O(Lxy0__1_carry__0_i_4_n_0));
LUT6 #(
.INIT(64'h9669969669699669))
Lxy0__1_carry__0_i_5
(.I0(Lxy0__1_carry__0_i_1_n_0),
.I1(Lxy0__1_carry__0_i_12_n_0),
.I2(\Lxy_0_reg_n_0_[7] ),
.I3(\Lxy_1_reg_n_0_[6] ),
.I4(Lxy_2[6]),
.I5(Lxy_3[6]),
.O(Lxy0__1_carry__0_i_5_n_0));
LUT6 #(
.INIT(64'h9669969669699669))
Lxy0__1_carry__0_i_6
(.I0(Lxy0__1_carry__0_i_2_n_0),
.I1(Lxy0__1_carry__0_i_9_n_0),
.I2(\Lxy_0_reg_n_0_[6] ),
.I3(\Lxy_1_reg_n_0_[5] ),
.I4(Lxy_2[5]),
.I5(Lxy_3[5]),
.O(Lxy0__1_carry__0_i_6_n_0));
LUT6 #(
.INIT(64'h9669969669699669))
Lxy0__1_carry__0_i_7
(.I0(Lxy0__1_carry__0_i_3_n_0),
.I1(Lxy0__1_carry__0_i_10_n_0),
.I2(\Lxy_0_reg_n_0_[5] ),
.I3(\Lxy_1_reg_n_0_[4] ),
.I4(Lxy_2[4]),
.I5(Lxy_3[4]),
.O(Lxy0__1_carry__0_i_7_n_0));
LUT6 #(
.INIT(64'h9669969669699669))
Lxy0__1_carry__0_i_8
(.I0(Lxy0__1_carry__0_i_4_n_0),
.I1(Lxy0__1_carry__0_i_11_n_0),
.I2(\Lxy_0_reg_n_0_[4] ),
.I3(\Lxy_1_reg_n_0_[3] ),
.I4(Lxy_2[3]),
.I5(Lxy_3[3]),
.O(Lxy0__1_carry__0_i_8_n_0));
LUT3 #(
.INIT(8'h96))
Lxy0__1_carry__0_i_9
(.I0(Lxy_3[6]),
.I1(\Lxy_1_reg_n_0_[6] ),
.I2(Lxy_2[6]),
.O(Lxy0__1_carry__0_i_9_n_0));
CARRY4 Lxy0__1_carry__1
(.CI(Lxy0__1_carry__0_n_0),
.CO({Lxy0__1_carry__1_n_0,Lxy0__1_carry__1_n_1,Lxy0__1_carry__1_n_2,Lxy0__1_carry__1_n_3}),
.CYINIT(1'b0),
.DI({Lxy0__1_carry__1_i_1_n_0,Lxy0__1_carry__1_i_2_n_0,Lxy0__1_carry__1_i_3_n_0,Lxy0__1_carry__1_i_4_n_0}),
.O({Lxy0__1_carry__1_n_4,Lxy0__1_carry__1_n_5,Lxy0__1_carry__1_n_6,Lxy0__1_carry__1_n_7}),
.S({Lxy0__1_carry__1_i_5_n_0,Lxy0__1_carry__1_i_6_n_0,Lxy0__1_carry__1_i_7_n_0,Lxy0__1_carry__1_i_8_n_0}));
LUT5 #(
.INIT(32'h8E88EE8E))
Lxy0__1_carry__1_i_1
(.I0(\Lxy_0_reg_n_0_[10] ),
.I1(Lxy0__1_carry__1_i_9_n_0),
.I2(Lxy_3[9]),
.I3(Lxy_2[9]),
.I4(\Lxy_1_reg_n_0_[9] ),
.O(Lxy0__1_carry__1_i_1_n_0));
LUT3 #(
.INIT(8'h96))
Lxy0__1_carry__1_i_10
(.I0(Lxy_3[9]),
.I1(\Lxy_1_reg_n_0_[9] ),
.I2(Lxy_2[9]),
.O(Lxy0__1_carry__1_i_10_n_0));
LUT3 #(
.INIT(8'h96))
Lxy0__1_carry__1_i_11
(.I0(Lxy_3[8]),
.I1(\Lxy_1_reg_n_0_[8] ),
.I2(Lxy_2[8]),
.O(Lxy0__1_carry__1_i_11_n_0));
LUT3 #(
.INIT(8'h96))
Lxy0__1_carry__1_i_12
(.I0(Lxy_3[11]),
.I1(\Lxy_1_reg_n_0_[11] ),
.I2(Lxy_2[11]),
.O(Lxy0__1_carry__1_i_12_n_0));
LUT5 #(
.INIT(32'h8E88EE8E))
Lxy0__1_carry__1_i_2
(.I0(\Lxy_0_reg_n_0_[9] ),
.I1(Lxy0__1_carry__1_i_10_n_0),
.I2(Lxy_3[8]),
.I3(Lxy_2[8]),
.I4(\Lxy_1_reg_n_0_[8] ),
.O(Lxy0__1_carry__1_i_2_n_0));
LUT5 #(
.INIT(32'h8E88EE8E))
Lxy0__1_carry__1_i_3
(.I0(\Lxy_0_reg_n_0_[8] ),
.I1(Lxy0__1_carry__1_i_11_n_0),
.I2(Lxy_3[7]),
.I3(Lxy_2[7]),
.I4(\Lxy_1_reg_n_0_[7] ),
.O(Lxy0__1_carry__1_i_3_n_0));
LUT5 #(
.INIT(32'h8E88EE8E))
Lxy0__1_carry__1_i_4
(.I0(\Lxy_0_reg_n_0_[7] ),
.I1(Lxy0__1_carry__0_i_12_n_0),
.I2(Lxy_3[6]),
.I3(Lxy_2[6]),
.I4(\Lxy_1_reg_n_0_[6] ),
.O(Lxy0__1_carry__1_i_4_n_0));
LUT6 #(
.INIT(64'h9669969669699669))
Lxy0__1_carry__1_i_5
(.I0(Lxy0__1_carry__1_i_1_n_0),
.I1(Lxy0__1_carry__1_i_12_n_0),
.I2(\Lxy_0_reg_n_0_[11] ),
.I3(\Lxy_1_reg_n_0_[10] ),
.I4(Lxy_2[10]),
.I5(Lxy_3[10]),
.O(Lxy0__1_carry__1_i_5_n_0));
LUT6 #(
.INIT(64'h9669969669699669))
Lxy0__1_carry__1_i_6
(.I0(Lxy0__1_carry__1_i_2_n_0),
.I1(Lxy0__1_carry__1_i_9_n_0),
.I2(\Lxy_0_reg_n_0_[10] ),
.I3(\Lxy_1_reg_n_0_[9] ),
.I4(Lxy_2[9]),
.I5(Lxy_3[9]),
.O(Lxy0__1_carry__1_i_6_n_0));
LUT6 #(
.INIT(64'h9669969669699669))
Lxy0__1_carry__1_i_7
(.I0(Lxy0__1_carry__1_i_3_n_0),
.I1(Lxy0__1_carry__1_i_10_n_0),
.I2(\Lxy_0_reg_n_0_[9] ),
.I3(\Lxy_1_reg_n_0_[8] ),
.I4(Lxy_2[8]),
.I5(Lxy_3[8]),
.O(Lxy0__1_carry__1_i_7_n_0));
LUT6 #(
.INIT(64'h9669969669699669))
Lxy0__1_carry__1_i_8
(.I0(Lxy0__1_carry__1_i_4_n_0),
.I1(Lxy0__1_carry__1_i_11_n_0),
.I2(\Lxy_0_reg_n_0_[8] ),
.I3(\Lxy_1_reg_n_0_[7] ),
.I4(Lxy_2[7]),
.I5(Lxy_3[7]),
.O(Lxy0__1_carry__1_i_8_n_0));
LUT3 #(
.INIT(8'h96))
Lxy0__1_carry__1_i_9
(.I0(Lxy_3[10]),
.I1(\Lxy_1_reg_n_0_[10] ),
.I2(Lxy_2[10]),
.O(Lxy0__1_carry__1_i_9_n_0));
CARRY4 Lxy0__1_carry__2
(.CI(Lxy0__1_carry__1_n_0),
.CO({NLW_Lxy0__1_carry__2_CO_UNCONNECTED[3],Lxy0__1_carry__2_n_1,Lxy0__1_carry__2_n_2,Lxy0__1_carry__2_n_3}),
.CYINIT(1'b0),
.DI({1'b0,Lxy0__1_carry__2_i_1_n_0,Lxy0__1_carry__2_i_2_n_0,Lxy0__1_carry__2_i_3_n_0}),
.O({Lxy0__1_carry__2_n_4,Lxy0__1_carry__2_n_5,Lxy0__1_carry__2_n_6,Lxy0__1_carry__2_n_7}),
.S({Lxy0__1_carry__2_i_4_n_0,Lxy0__1_carry__2_i_5_n_0,Lxy0__1_carry__2_i_6_n_0,Lxy0__1_carry__2_i_7_n_0}));
LUT5 #(
.INIT(32'h8E88EE8E))
Lxy0__1_carry__2_i_1
(.I0(\Lxy_0_reg_n_0_[13] ),
.I1(Lxy0__1_carry__2_i_8_n_0),
.I2(Lxy_3[12]),
.I3(Lxy_2[12]),
.I4(\Lxy_1_reg_n_0_[12] ),
.O(Lxy0__1_carry__2_i_1_n_0));
(* SOFT_HLUTNM = "soft_lutpair32" *)
LUT3 #(
.INIT(8'h4D))
Lxy0__1_carry__2_i_10
(.I0(\Lxy_1_reg_n_0_[13] ),
.I1(Lxy_2[13]),
.I2(Lxy_3[13]),
.O(Lxy0__1_carry__2_i_10_n_0));
LUT4 #(
.INIT(16'h6996))
Lxy0__1_carry__2_i_11
(.I0(Lxy_2[15]),
.I1(\Lxy_1_reg_n_0_[15] ),
.I2(Lxy_3[15]),
.I3(\Lxy_0_reg_n_0_[15] ),
.O(Lxy0__1_carry__2_i_11_n_0));
LUT3 #(
.INIT(8'h96))
Lxy0__1_carry__2_i_12
(.I0(Lxy_3[14]),
.I1(\Lxy_1_reg_n_0_[14] ),
.I2(Lxy_2[14]),
.O(Lxy0__1_carry__2_i_12_n_0));
LUT5 #(
.INIT(32'h8E88EE8E))
Lxy0__1_carry__2_i_2
(.I0(\Lxy_0_reg_n_0_[12] ),
.I1(Lxy0__1_carry__2_i_9_n_0),
.I2(Lxy_3[11]),
.I3(Lxy_2[11]),
.I4(\Lxy_1_reg_n_0_[11] ),
.O(Lxy0__1_carry__2_i_2_n_0));
LUT5 #(
.INIT(32'h8E88EE8E))
Lxy0__1_carry__2_i_3
(.I0(\Lxy_0_reg_n_0_[11] ),
.I1(Lxy0__1_carry__1_i_12_n_0),
.I2(Lxy_3[10]),
.I3(Lxy_2[10]),
.I4(\Lxy_1_reg_n_0_[10] ),
.O(Lxy0__1_carry__2_i_3_n_0));
LUT6 #(
.INIT(64'h1E87781E87E11E87))
Lxy0__1_carry__2_i_4
(.I0(Lxy0__1_carry__2_i_10_n_0),
.I1(\Lxy_0_reg_n_0_[14] ),
.I2(Lxy0__1_carry__2_i_11_n_0),
.I3(\Lxy_1_reg_n_0_[14] ),
.I4(Lxy_2[14]),
.I5(Lxy_3[14]),
.O(Lxy0__1_carry__2_i_4_n_0));
LUT6 #(
.INIT(64'h9669969669699669))
Lxy0__1_carry__2_i_5
(.I0(Lxy0__1_carry__2_i_1_n_0),
.I1(Lxy0__1_carry__2_i_12_n_0),
.I2(\Lxy_0_reg_n_0_[14] ),
.I3(\Lxy_1_reg_n_0_[13] ),
.I4(Lxy_2[13]),
.I5(Lxy_3[13]),
.O(Lxy0__1_carry__2_i_5_n_0));
LUT6 #(
.INIT(64'h9669969669699669))
Lxy0__1_carry__2_i_6
(.I0(Lxy0__1_carry__2_i_2_n_0),
.I1(Lxy0__1_carry__2_i_8_n_0),
.I2(\Lxy_0_reg_n_0_[13] ),
.I3(\Lxy_1_reg_n_0_[12] ),
.I4(Lxy_2[12]),
.I5(Lxy_3[12]),
.O(Lxy0__1_carry__2_i_6_n_0));
LUT6 #(
.INIT(64'h9669969669699669))
Lxy0__1_carry__2_i_7
(.I0(Lxy0__1_carry__2_i_3_n_0),
.I1(Lxy0__1_carry__2_i_9_n_0),
.I2(\Lxy_0_reg_n_0_[12] ),
.I3(\Lxy_1_reg_n_0_[11] ),
.I4(Lxy_2[11]),
.I5(Lxy_3[11]),
.O(Lxy0__1_carry__2_i_7_n_0));
(* SOFT_HLUTNM = "soft_lutpair32" *)
LUT3 #(
.INIT(8'h96))
Lxy0__1_carry__2_i_8
(.I0(Lxy_3[13]),
.I1(\Lxy_1_reg_n_0_[13] ),
.I2(Lxy_2[13]),
.O(Lxy0__1_carry__2_i_8_n_0));
LUT3 #(
.INIT(8'h96))
Lxy0__1_carry__2_i_9
(.I0(Lxy_3[12]),
.I1(\Lxy_1_reg_n_0_[12] ),
.I2(Lxy_2[12]),
.O(Lxy0__1_carry__2_i_9_n_0));
LUT6 #(
.INIT(64'hEBBEEBBE8228EBBE))
Lxy0__1_carry_i_1
(.I0(\Lxy_0_reg_n_0_[2] ),
.I1(Lxy_2[2]),
.I2(\Lxy_1_reg_n_0_[2] ),
.I3(Lxy_3[2]),
.I4(\Lxy_1_reg_n_0_[1] ),
.I5(Lxy_2[1]),
.O(Lxy0__1_carry_i_1_n_0));
LUT2 #(
.INIT(4'h9))
Lxy0__1_carry_i_10
(.I0(Lxy_2[1]),
.I1(\Lxy_1_reg_n_0_[1] ),
.O(Lxy0__1_carry_i_10_n_0));
LUT4 #(
.INIT(16'h4DD4))
Lxy0__1_carry_i_2
(.I0(Lxy_3[1]),
.I1(\Lxy_0_reg_n_0_[1] ),
.I2(\Lxy_1_reg_n_0_[1] ),
.I3(Lxy_2[1]),
.O(Lxy0__1_carry_i_2_n_0));
LUT4 #(
.INIT(16'h9669))
Lxy0__1_carry_i_3
(.I0(\Lxy_1_reg_n_0_[1] ),
.I1(Lxy_2[1]),
.I2(Lxy_3[1]),
.I3(\Lxy_0_reg_n_0_[1] ),
.O(Lxy0__1_carry_i_3_n_0));
LUT6 #(
.INIT(64'h9669969669699669))
Lxy0__1_carry_i_4
(.I0(Lxy0__1_carry_i_1_n_0),
.I1(Lxy0__1_carry_i_8_n_0),
.I2(\Lxy_0_reg_n_0_[3] ),
.I3(\Lxy_1_reg_n_0_[2] ),
.I4(Lxy_2[2]),
.I5(Lxy_3[2]),
.O(Lxy0__1_carry_i_4_n_0));
LUT5 #(
.INIT(32'h69966969))
Lxy0__1_carry_i_5
(.I0(Lxy0__1_carry_i_2_n_0),
.I1(Lxy0__1_carry_i_9_n_0),
.I2(\Lxy_0_reg_n_0_[2] ),
.I3(Lxy_2[1]),
.I4(\Lxy_1_reg_n_0_[1] ),
.O(Lxy0__1_carry_i_5_n_0));
LUT6 #(
.INIT(64'h9669969669699669))
Lxy0__1_carry_i_6
(.I0(\Lxy_0_reg_n_0_[1] ),
.I1(Lxy_3[1]),
.I2(Lxy0__1_carry_i_10_n_0),
.I3(Lxy_3[0]),
.I4(Lxy_2[0]),
.I5(\Lxy_1_reg_n_0_[0] ),
.O(Lxy0__1_carry_i_6_n_0));
LUT4 #(
.INIT(16'h6996))
Lxy0__1_carry_i_7
(.I0(Lxy_2[0]),
.I1(\Lxy_1_reg_n_0_[0] ),
.I2(Lxy_3[0]),
.I3(\Lxy_0_reg_n_0_[0] ),
.O(Lxy0__1_carry_i_7_n_0));
LUT3 #(
.INIT(8'h96))
Lxy0__1_carry_i_8
(.I0(Lxy_3[3]),
.I1(\Lxy_1_reg_n_0_[3] ),
.I2(Lxy_2[3]),
.O(Lxy0__1_carry_i_8_n_0));
LUT3 #(
.INIT(8'h96))
Lxy0__1_carry_i_9
(.I0(Lxy_3[2]),
.I1(\Lxy_1_reg_n_0_[2] ),
.I2(Lxy_2[2]),
.O(Lxy0__1_carry_i_9_n_0));
LUT6 #(
.INIT(64'h0000000000004000))
\Lxy_0[15]_i_1
(.I0(\cycle_reg[0]_rep_n_0 ),
.I1(cycle[3]),
.I2(active),
.I3(rst),
.I4(\cycle_reg[1]_rep_n_0 ),
.I5(cycle[2]),
.O(\Lxy_0[15]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\Lxy_0_reg[0]
(.C(clk_x16),
.CE(\Lxy_0[15]_i_1_n_0 ),
.D(Lxx_00[0]),
.Q(\Lxy_0_reg_n_0_[0] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxy_0_reg[10]
(.C(clk_x16),
.CE(\Lxy_0[15]_i_1_n_0 ),
.D(Lxx_00[10]),
.Q(\Lxy_0_reg_n_0_[10] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxy_0_reg[11]
(.C(clk_x16),
.CE(\Lxy_0[15]_i_1_n_0 ),
.D(Lxx_00[11]),
.Q(\Lxy_0_reg_n_0_[11] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxy_0_reg[12]
(.C(clk_x16),
.CE(\Lxy_0[15]_i_1_n_0 ),
.D(Lxx_00[12]),
.Q(\Lxy_0_reg_n_0_[12] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxy_0_reg[13]
(.C(clk_x16),
.CE(\Lxy_0[15]_i_1_n_0 ),
.D(Lxx_00[13]),
.Q(\Lxy_0_reg_n_0_[13] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxy_0_reg[14]
(.C(clk_x16),
.CE(\Lxy_0[15]_i_1_n_0 ),
.D(Lxx_00[14]),
.Q(\Lxy_0_reg_n_0_[14] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxy_0_reg[15]
(.C(clk_x16),
.CE(\Lxy_0[15]_i_1_n_0 ),
.D(Lxx_00[15]),
.Q(\Lxy_0_reg_n_0_[15] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxy_0_reg[1]
(.C(clk_x16),
.CE(\Lxy_0[15]_i_1_n_0 ),
.D(Lxx_00[1]),
.Q(\Lxy_0_reg_n_0_[1] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxy_0_reg[2]
(.C(clk_x16),
.CE(\Lxy_0[15]_i_1_n_0 ),
.D(Lxx_00[2]),
.Q(\Lxy_0_reg_n_0_[2] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxy_0_reg[3]
(.C(clk_x16),
.CE(\Lxy_0[15]_i_1_n_0 ),
.D(Lxx_00[3]),
.Q(\Lxy_0_reg_n_0_[3] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxy_0_reg[4]
(.C(clk_x16),
.CE(\Lxy_0[15]_i_1_n_0 ),
.D(Lxx_00[4]),
.Q(\Lxy_0_reg_n_0_[4] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxy_0_reg[5]
(.C(clk_x16),
.CE(\Lxy_0[15]_i_1_n_0 ),
.D(Lxx_00[5]),
.Q(\Lxy_0_reg_n_0_[5] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxy_0_reg[6]
(.C(clk_x16),
.CE(\Lxy_0[15]_i_1_n_0 ),
.D(Lxx_00[6]),
.Q(\Lxy_0_reg_n_0_[6] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxy_0_reg[7]
(.C(clk_x16),
.CE(\Lxy_0[15]_i_1_n_0 ),
.D(Lxx_00[7]),
.Q(\Lxy_0_reg_n_0_[7] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxy_0_reg[8]
(.C(clk_x16),
.CE(\Lxy_0[15]_i_1_n_0 ),
.D(Lxx_00[8]),
.Q(\Lxy_0_reg_n_0_[8] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxy_0_reg[9]
(.C(clk_x16),
.CE(\Lxy_0[15]_i_1_n_0 ),
.D(Lxx_00[9]),
.Q(\Lxy_0_reg_n_0_[9] ),
.R(1'b0));
LUT6 #(
.INIT(64'h0000400000000000))
\Lxy_1[15]_i_1
(.I0(\cycle_reg[0]_rep_n_0 ),
.I1(cycle[3]),
.I2(active),
.I3(rst),
.I4(cycle[2]),
.I5(\cycle_reg[1]_rep_n_0 ),
.O(Lxy_1));
FDRE #(
.INIT(1'b0))
\Lxy_1_reg[0]
(.C(clk_x16),
.CE(Lxy_1),
.D(Lxx_11[0]),
.Q(\Lxy_1_reg_n_0_[0] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxy_1_reg[10]
(.C(clk_x16),
.CE(Lxy_1),
.D(Lxx_11[10]),
.Q(\Lxy_1_reg_n_0_[10] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxy_1_reg[11]
(.C(clk_x16),
.CE(Lxy_1),
.D(Lxx_11[11]),
.Q(\Lxy_1_reg_n_0_[11] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxy_1_reg[12]
(.C(clk_x16),
.CE(Lxy_1),
.D(Lxx_11[12]),
.Q(\Lxy_1_reg_n_0_[12] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxy_1_reg[13]
(.C(clk_x16),
.CE(Lxy_1),
.D(Lxx_11[13]),
.Q(\Lxy_1_reg_n_0_[13] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxy_1_reg[14]
(.C(clk_x16),
.CE(Lxy_1),
.D(Lxx_11[14]),
.Q(\Lxy_1_reg_n_0_[14] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxy_1_reg[15]
(.C(clk_x16),
.CE(Lxy_1),
.D(Lxx_11[15]),
.Q(\Lxy_1_reg_n_0_[15] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxy_1_reg[1]
(.C(clk_x16),
.CE(Lxy_1),
.D(Lxx_11[1]),
.Q(\Lxy_1_reg_n_0_[1] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxy_1_reg[2]
(.C(clk_x16),
.CE(Lxy_1),
.D(Lxx_11[2]),
.Q(\Lxy_1_reg_n_0_[2] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxy_1_reg[3]
(.C(clk_x16),
.CE(Lxy_1),
.D(Lxx_11[3]),
.Q(\Lxy_1_reg_n_0_[3] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxy_1_reg[4]
(.C(clk_x16),
.CE(Lxy_1),
.D(Lxx_11[4]),
.Q(\Lxy_1_reg_n_0_[4] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxy_1_reg[5]
(.C(clk_x16),
.CE(Lxy_1),
.D(Lxx_11[5]),
.Q(\Lxy_1_reg_n_0_[5] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxy_1_reg[6]
(.C(clk_x16),
.CE(Lxy_1),
.D(Lxx_11[6]),
.Q(\Lxy_1_reg_n_0_[6] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxy_1_reg[7]
(.C(clk_x16),
.CE(Lxy_1),
.D(Lxx_11[7]),
.Q(\Lxy_1_reg_n_0_[7] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxy_1_reg[8]
(.C(clk_x16),
.CE(Lxy_1),
.D(Lxx_11[8]),
.Q(\Lxy_1_reg_n_0_[8] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxy_1_reg[9]
(.C(clk_x16),
.CE(Lxy_1),
.D(Lxx_11[9]),
.Q(\Lxy_1_reg_n_0_[9] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxy_2_reg[0]
(.C(clk_x16),
.CE(det_0),
.D(Lxx_00[0]),
.Q(Lxy_2[0]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxy_2_reg[10]
(.C(clk_x16),
.CE(det_0),
.D(Lxx_00[10]),
.Q(Lxy_2[10]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxy_2_reg[11]
(.C(clk_x16),
.CE(det_0),
.D(Lxx_00[11]),
.Q(Lxy_2[11]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxy_2_reg[12]
(.C(clk_x16),
.CE(det_0),
.D(Lxx_00[12]),
.Q(Lxy_2[12]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxy_2_reg[13]
(.C(clk_x16),
.CE(det_0),
.D(Lxx_00[13]),
.Q(Lxy_2[13]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxy_2_reg[14]
(.C(clk_x16),
.CE(det_0),
.D(Lxx_00[14]),
.Q(Lxy_2[14]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxy_2_reg[15]
(.C(clk_x16),
.CE(det_0),
.D(Lxx_00[15]),
.Q(Lxy_2[15]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxy_2_reg[1]
(.C(clk_x16),
.CE(det_0),
.D(Lxx_00[1]),
.Q(Lxy_2[1]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxy_2_reg[2]
(.C(clk_x16),
.CE(det_0),
.D(Lxx_00[2]),
.Q(Lxy_2[2]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxy_2_reg[3]
(.C(clk_x16),
.CE(det_0),
.D(Lxx_00[3]),
.Q(Lxy_2[3]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxy_2_reg[4]
(.C(clk_x16),
.CE(det_0),
.D(Lxx_00[4]),
.Q(Lxy_2[4]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxy_2_reg[5]
(.C(clk_x16),
.CE(det_0),
.D(Lxx_00[5]),
.Q(Lxy_2[5]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxy_2_reg[6]
(.C(clk_x16),
.CE(det_0),
.D(Lxx_00[6]),
.Q(Lxy_2[6]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxy_2_reg[7]
(.C(clk_x16),
.CE(det_0),
.D(Lxx_00[7]),
.Q(Lxy_2[7]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxy_2_reg[8]
(.C(clk_x16),
.CE(det_0),
.D(Lxx_00[8]),
.Q(Lxy_2[8]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxy_2_reg[9]
(.C(clk_x16),
.CE(det_0),
.D(Lxx_00[9]),
.Q(Lxy_2[9]),
.R(1'b0));
LUT6 #(
.INIT(64'h4000000000000000))
\Lxy_3[15]_i_1
(.I0(cycle[0]),
.I1(active),
.I2(rst),
.I3(\cycle_reg[2]_rep_n_0 ),
.I4(\cycle_reg[1]_rep__0_n_0 ),
.I5(cycle[3]),
.O(y6));
FDRE #(
.INIT(1'b0))
\Lxy_3_reg[0]
(.C(clk_x16),
.CE(y6),
.D(Lxx_11[0]),
.Q(Lxy_3[0]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxy_3_reg[10]
(.C(clk_x16),
.CE(y6),
.D(Lxx_11[10]),
.Q(Lxy_3[10]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxy_3_reg[11]
(.C(clk_x16),
.CE(y6),
.D(Lxx_11[11]),
.Q(Lxy_3[11]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxy_3_reg[12]
(.C(clk_x16),
.CE(y6),
.D(Lxx_11[12]),
.Q(Lxy_3[12]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxy_3_reg[13]
(.C(clk_x16),
.CE(y6),
.D(Lxx_11[13]),
.Q(Lxy_3[13]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxy_3_reg[14]
(.C(clk_x16),
.CE(y6),
.D(Lxx_11[14]),
.Q(Lxy_3[14]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxy_3_reg[15]
(.C(clk_x16),
.CE(y6),
.D(Lxx_11[15]),
.Q(Lxy_3[15]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxy_3_reg[1]
(.C(clk_x16),
.CE(y6),
.D(Lxx_11[1]),
.Q(Lxy_3[1]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxy_3_reg[2]
(.C(clk_x16),
.CE(y6),
.D(Lxx_11[2]),
.Q(Lxy_3[2]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxy_3_reg[3]
(.C(clk_x16),
.CE(y6),
.D(Lxx_11[3]),
.Q(Lxy_3[3]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxy_3_reg[4]
(.C(clk_x16),
.CE(y6),
.D(Lxx_11[4]),
.Q(Lxy_3[4]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxy_3_reg[5]
(.C(clk_x16),
.CE(y6),
.D(Lxx_11[5]),
.Q(Lxy_3[5]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxy_3_reg[6]
(.C(clk_x16),
.CE(y6),
.D(Lxx_11[6]),
.Q(Lxy_3[6]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxy_3_reg[7]
(.C(clk_x16),
.CE(y6),
.D(Lxx_11[7]),
.Q(Lxy_3[7]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxy_3_reg[8]
(.C(clk_x16),
.CE(y6),
.D(Lxx_11[8]),
.Q(Lxy_3[8]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxy_3_reg[9]
(.C(clk_x16),
.CE(y6),
.D(Lxx_11[9]),
.Q(Lxy_3[9]),
.R(1'b0));
CARRY4 Lyy0_carry
(.CI(1'b0),
.CO({Lyy0_carry_n_0,Lyy0_carry_n_1,Lyy0_carry_n_2,Lyy0_carry_n_3}),
.CYINIT(1'b0),
.DI({Lyy0_carry_i_1_n_0,Lyy0_carry_i_2_n_0,1'b1,\Lyy_2_reg_n_0_[0] }),
.O(B[3:0]),
.S({Lyy0_carry_i_3_n_0,Lyy0_carry_i_4_n_0,Lyy0_carry_i_5_n_0,Lyy0_carry_i_6_n_0}));
CARRY4 Lyy0_carry__0
(.CI(Lyy0_carry_n_0),
.CO({Lyy0_carry__0_n_0,Lyy0_carry__0_n_1,Lyy0_carry__0_n_2,Lyy0_carry__0_n_3}),
.CYINIT(1'b0),
.DI({Lyy0_carry__0_i_1_n_0,Lyy0_carry__0_i_2_n_0,Lyy0_carry__0_i_3_n_0,Lyy0_carry__0_i_4_n_0}),
.O(B[7:4]),
.S({Lyy0_carry__0_i_5_n_0,Lyy0_carry__0_i_6_n_0,Lyy0_carry__0_i_7_n_0,Lyy0_carry__0_i_8_n_0}));
(* HLUTNM = "lutpair16" *)
LUT3 #(
.INIT(8'hD4))
Lyy0_carry__0_i_1
(.I0(Lyy_1[6]),
.I1(\Lyy_2_reg_n_0_[6] ),
.I2(\Lyy_0_reg_n_0_[6] ),
.O(Lyy0_carry__0_i_1_n_0));
(* HLUTNM = "lutpair15" *)
LUT3 #(
.INIT(8'hD4))
Lyy0_carry__0_i_2
(.I0(Lyy_1[5]),
.I1(\Lyy_2_reg_n_0_[5] ),
.I2(\Lyy_0_reg_n_0_[5] ),
.O(Lyy0_carry__0_i_2_n_0));
(* HLUTNM = "lutpair14" *)
LUT3 #(
.INIT(8'hD4))
Lyy0_carry__0_i_3
(.I0(Lyy_1[4]),
.I1(\Lyy_2_reg_n_0_[4] ),
.I2(\Lyy_0_reg_n_0_[4] ),
.O(Lyy0_carry__0_i_3_n_0));
(* HLUTNM = "lutpair13" *)
LUT3 #(
.INIT(8'hD4))
Lyy0_carry__0_i_4
(.I0(Lyy_1[3]),
.I1(\Lyy_2_reg_n_0_[3] ),
.I2(\Lyy_0_reg_n_0_[3] ),
.O(Lyy0_carry__0_i_4_n_0));
(* HLUTNM = "lutpair17" *)
LUT4 #(
.INIT(16'h9669))
Lyy0_carry__0_i_5
(.I0(Lyy_1[7]),
.I1(\Lyy_2_reg_n_0_[7] ),
.I2(\Lyy_0_reg_n_0_[7] ),
.I3(Lyy0_carry__0_i_1_n_0),
.O(Lyy0_carry__0_i_5_n_0));
(* HLUTNM = "lutpair16" *)
LUT4 #(
.INIT(16'h9669))
Lyy0_carry__0_i_6
(.I0(Lyy_1[6]),
.I1(\Lyy_2_reg_n_0_[6] ),
.I2(\Lyy_0_reg_n_0_[6] ),
.I3(Lyy0_carry__0_i_2_n_0),
.O(Lyy0_carry__0_i_6_n_0));
(* HLUTNM = "lutpair15" *)
LUT4 #(
.INIT(16'h9669))
Lyy0_carry__0_i_7
(.I0(Lyy_1[5]),
.I1(\Lyy_2_reg_n_0_[5] ),
.I2(\Lyy_0_reg_n_0_[5] ),
.I3(Lyy0_carry__0_i_3_n_0),
.O(Lyy0_carry__0_i_7_n_0));
(* HLUTNM = "lutpair14" *)
LUT4 #(
.INIT(16'h9669))
Lyy0_carry__0_i_8
(.I0(Lyy_1[4]),
.I1(\Lyy_2_reg_n_0_[4] ),
.I2(\Lyy_0_reg_n_0_[4] ),
.I3(Lyy0_carry__0_i_4_n_0),
.O(Lyy0_carry__0_i_8_n_0));
CARRY4 Lyy0_carry__1
(.CI(Lyy0_carry__0_n_0),
.CO({Lyy0_carry__1_n_0,Lyy0_carry__1_n_1,Lyy0_carry__1_n_2,Lyy0_carry__1_n_3}),
.CYINIT(1'b0),
.DI({Lyy0_carry__1_i_1_n_0,Lyy0_carry__1_i_2_n_0,Lyy0_carry__1_i_3_n_0,Lyy0_carry__1_i_4_n_0}),
.O(B[11:8]),
.S({Lyy0_carry__1_i_5_n_0,Lyy0_carry__1_i_6_n_0,Lyy0_carry__1_i_7_n_0,Lyy0_carry__1_i_8_n_0}));
(* HLUTNM = "lutpair20" *)
LUT3 #(
.INIT(8'hD4))
Lyy0_carry__1_i_1
(.I0(Lyy_1[10]),
.I1(\Lyy_2_reg_n_0_[10] ),
.I2(\Lyy_0_reg_n_0_[10] ),
.O(Lyy0_carry__1_i_1_n_0));
(* HLUTNM = "lutpair19" *)
LUT3 #(
.INIT(8'hD4))
Lyy0_carry__1_i_2
(.I0(Lyy_1[9]),
.I1(\Lyy_2_reg_n_0_[9] ),
.I2(\Lyy_0_reg_n_0_[9] ),
.O(Lyy0_carry__1_i_2_n_0));
(* HLUTNM = "lutpair18" *)
LUT3 #(
.INIT(8'hD4))
Lyy0_carry__1_i_3
(.I0(Lyy_1[8]),
.I1(\Lyy_2_reg_n_0_[8] ),
.I2(\Lyy_0_reg_n_0_[8] ),
.O(Lyy0_carry__1_i_3_n_0));
(* HLUTNM = "lutpair17" *)
LUT3 #(
.INIT(8'hD4))
Lyy0_carry__1_i_4
(.I0(Lyy_1[7]),
.I1(\Lyy_2_reg_n_0_[7] ),
.I2(\Lyy_0_reg_n_0_[7] ),
.O(Lyy0_carry__1_i_4_n_0));
(* HLUTNM = "lutpair21" *)
LUT4 #(
.INIT(16'h9669))
Lyy0_carry__1_i_5
(.I0(Lyy_1[11]),
.I1(\Lyy_2_reg_n_0_[11] ),
.I2(\Lyy_0_reg_n_0_[11] ),
.I3(Lyy0_carry__1_i_1_n_0),
.O(Lyy0_carry__1_i_5_n_0));
(* HLUTNM = "lutpair20" *)
LUT4 #(
.INIT(16'h9669))
Lyy0_carry__1_i_6
(.I0(Lyy_1[10]),
.I1(\Lyy_2_reg_n_0_[10] ),
.I2(\Lyy_0_reg_n_0_[10] ),
.I3(Lyy0_carry__1_i_2_n_0),
.O(Lyy0_carry__1_i_6_n_0));
(* HLUTNM = "lutpair19" *)
LUT4 #(
.INIT(16'h9669))
Lyy0_carry__1_i_7
(.I0(Lyy_1[9]),
.I1(\Lyy_2_reg_n_0_[9] ),
.I2(\Lyy_0_reg_n_0_[9] ),
.I3(Lyy0_carry__1_i_3_n_0),
.O(Lyy0_carry__1_i_7_n_0));
(* HLUTNM = "lutpair18" *)
LUT4 #(
.INIT(16'h9669))
Lyy0_carry__1_i_8
(.I0(Lyy_1[8]),
.I1(\Lyy_2_reg_n_0_[8] ),
.I2(\Lyy_0_reg_n_0_[8] ),
.I3(Lyy0_carry__1_i_4_n_0),
.O(Lyy0_carry__1_i_8_n_0));
CARRY4 Lyy0_carry__2
(.CI(Lyy0_carry__1_n_0),
.CO({NLW_Lyy0_carry__2_CO_UNCONNECTED[3],Lyy0_carry__2_n_1,Lyy0_carry__2_n_2,Lyy0_carry__2_n_3}),
.CYINIT(1'b0),
.DI({1'b0,Lyy0_carry__2_i_1_n_0,Lyy0_carry__2_i_2_n_0,Lyy0_carry__2_i_3_n_0}),
.O(B[15:12]),
.S({Lyy0_carry__2_i_4_n_0,Lyy0_carry__2_i_5_n_0,Lyy0_carry__2_i_6_n_0,Lyy0_carry__2_i_7_n_0}));
(* HLUTNM = "lutpair23" *)
LUT3 #(
.INIT(8'hD4))
Lyy0_carry__2_i_1
(.I0(Lyy_1[13]),
.I1(\Lyy_2_reg_n_0_[13] ),
.I2(\Lyy_0_reg_n_0_[13] ),
.O(Lyy0_carry__2_i_1_n_0));
(* HLUTNM = "lutpair22" *)
LUT3 #(
.INIT(8'hD4))
Lyy0_carry__2_i_2
(.I0(Lyy_1[12]),
.I1(\Lyy_2_reg_n_0_[12] ),
.I2(\Lyy_0_reg_n_0_[12] ),
.O(Lyy0_carry__2_i_2_n_0));
(* HLUTNM = "lutpair21" *)
LUT3 #(
.INIT(8'hD4))
Lyy0_carry__2_i_3
(.I0(Lyy_1[11]),
.I1(\Lyy_2_reg_n_0_[11] ),
.I2(\Lyy_0_reg_n_0_[11] ),
.O(Lyy0_carry__2_i_3_n_0));
LUT6 #(
.INIT(64'h8E71718E718E8E71))
Lyy0_carry__2_i_4
(.I0(\Lyy_0_reg_n_0_[14] ),
.I1(\Lyy_2_reg_n_0_[14] ),
.I2(Lyy_1[14]),
.I3(\Lyy_2_reg_n_0_[15] ),
.I4(Lyy_1[15]),
.I5(\Lyy_0_reg_n_0_[15] ),
.O(Lyy0_carry__2_i_4_n_0));
LUT4 #(
.INIT(16'h9669))
Lyy0_carry__2_i_5
(.I0(Lyy0_carry__2_i_1_n_0),
.I1(\Lyy_2_reg_n_0_[14] ),
.I2(Lyy_1[14]),
.I3(\Lyy_0_reg_n_0_[14] ),
.O(Lyy0_carry__2_i_5_n_0));
(* HLUTNM = "lutpair23" *)
LUT4 #(
.INIT(16'h9669))
Lyy0_carry__2_i_6
(.I0(Lyy_1[13]),
.I1(\Lyy_2_reg_n_0_[13] ),
.I2(\Lyy_0_reg_n_0_[13] ),
.I3(Lyy0_carry__2_i_2_n_0),
.O(Lyy0_carry__2_i_6_n_0));
(* HLUTNM = "lutpair22" *)
LUT4 #(
.INIT(16'h9669))
Lyy0_carry__2_i_7
(.I0(Lyy_1[12]),
.I1(\Lyy_2_reg_n_0_[12] ),
.I2(\Lyy_0_reg_n_0_[12] ),
.I3(Lyy0_carry__2_i_3_n_0),
.O(Lyy0_carry__2_i_7_n_0));
(* HLUTNM = "lutpair12" *)
LUT3 #(
.INIT(8'hD4))
Lyy0_carry_i_1
(.I0(Lyy_1[2]),
.I1(\Lyy_2_reg_n_0_[2] ),
.I2(\Lyy_0_reg_n_0_[2] ),
.O(Lyy0_carry_i_1_n_0));
(* HLUTNM = "lutpair25" *)
LUT3 #(
.INIT(8'hD4))
Lyy0_carry_i_2
(.I0(Lyy_1[1]),
.I1(\Lyy_2_reg_n_0_[1] ),
.I2(\Lyy_0_reg_n_0_[1] ),
.O(Lyy0_carry_i_2_n_0));
(* HLUTNM = "lutpair13" *)
LUT4 #(
.INIT(16'h9669))
Lyy0_carry_i_3
(.I0(Lyy_1[3]),
.I1(\Lyy_2_reg_n_0_[3] ),
.I2(\Lyy_0_reg_n_0_[3] ),
.I3(Lyy0_carry_i_1_n_0),
.O(Lyy0_carry_i_3_n_0));
(* HLUTNM = "lutpair12" *)
LUT4 #(
.INIT(16'h9669))
Lyy0_carry_i_4
(.I0(Lyy_1[2]),
.I1(\Lyy_2_reg_n_0_[2] ),
.I2(\Lyy_0_reg_n_0_[2] ),
.I3(Lyy0_carry_i_2_n_0),
.O(Lyy0_carry_i_4_n_0));
(* HLUTNM = "lutpair25" *)
LUT3 #(
.INIT(8'h96))
Lyy0_carry_i_5
(.I0(Lyy_1[1]),
.I1(\Lyy_2_reg_n_0_[1] ),
.I2(\Lyy_0_reg_n_0_[1] ),
.O(Lyy0_carry_i_5_n_0));
LUT2 #(
.INIT(4'h6))
Lyy0_carry_i_6
(.I0(\Lyy_2_reg_n_0_[0] ),
.I1(\Lyy_0_reg_n_0_[0] ),
.O(Lyy0_carry_i_6_n_0));
LUT6 #(
.INIT(64'h0000000000000080))
\Lyy_0[15]_i_1
(.I0(rst),
.I1(active),
.I2(cycle[2]),
.I3(\cycle_reg[1]_rep_n_0 ),
.I4(cycle[3]),
.I5(\cycle_reg[0]_rep_n_0 ),
.O(Lyy_0));
FDRE #(
.INIT(1'b0))
\Lyy_0_reg[0]
(.C(clk_x16),
.CE(Lyy_0),
.D(Lxx_00[0]),
.Q(\Lyy_0_reg_n_0_[0] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_0_reg[10]
(.C(clk_x16),
.CE(Lyy_0),
.D(Lxx_00[10]),
.Q(\Lyy_0_reg_n_0_[10] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_0_reg[11]
(.C(clk_x16),
.CE(Lyy_0),
.D(Lxx_00[11]),
.Q(\Lyy_0_reg_n_0_[11] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_0_reg[12]
(.C(clk_x16),
.CE(Lyy_0),
.D(Lxx_00[12]),
.Q(\Lyy_0_reg_n_0_[12] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_0_reg[13]
(.C(clk_x16),
.CE(Lyy_0),
.D(Lxx_00[13]),
.Q(\Lyy_0_reg_n_0_[13] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_0_reg[14]
(.C(clk_x16),
.CE(Lyy_0),
.D(Lxx_00[14]),
.Q(\Lyy_0_reg_n_0_[14] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_0_reg[15]
(.C(clk_x16),
.CE(Lyy_0),
.D(Lxx_00[15]),
.Q(\Lyy_0_reg_n_0_[15] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_0_reg[1]
(.C(clk_x16),
.CE(Lyy_0),
.D(Lxx_00[1]),
.Q(\Lyy_0_reg_n_0_[1] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_0_reg[2]
(.C(clk_x16),
.CE(Lyy_0),
.D(Lxx_00[2]),
.Q(\Lyy_0_reg_n_0_[2] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_0_reg[3]
(.C(clk_x16),
.CE(Lyy_0),
.D(Lxx_00[3]),
.Q(\Lyy_0_reg_n_0_[3] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_0_reg[4]
(.C(clk_x16),
.CE(Lyy_0),
.D(Lxx_00[4]),
.Q(\Lyy_0_reg_n_0_[4] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_0_reg[5]
(.C(clk_x16),
.CE(Lyy_0),
.D(Lxx_00[5]),
.Q(\Lyy_0_reg_n_0_[5] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_0_reg[6]
(.C(clk_x16),
.CE(Lyy_0),
.D(Lxx_00[6]),
.Q(\Lyy_0_reg_n_0_[6] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_0_reg[7]
(.C(clk_x16),
.CE(Lyy_0),
.D(Lxx_00[7]),
.Q(\Lyy_0_reg_n_0_[7] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_0_reg[8]
(.C(clk_x16),
.CE(Lyy_0),
.D(Lxx_00[8]),
.Q(\Lyy_0_reg_n_0_[8] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_0_reg[9]
(.C(clk_x16),
.CE(Lyy_0),
.D(Lxx_00[9]),
.Q(\Lyy_0_reg_n_0_[9] ),
.R(1'b0));
LUT6 #(
.INIT(64'h0000000040000000))
\Lyy_1[15]_i_1
(.I0(cycle[3]),
.I1(\cycle_reg[2]_rep_n_0 ),
.I2(rst),
.I3(active),
.I4(cycle[0]),
.I5(\cycle_reg[1]_rep__0_n_0 ),
.O(y1));
FDRE #(
.INIT(1'b0))
\Lyy_1_reg[10]
(.C(clk_x16),
.CE(y1),
.D(Lxx_11[9]),
.Q(Lyy_1[10]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_1_reg[11]
(.C(clk_x16),
.CE(y1),
.D(Lxx_11[10]),
.Q(Lyy_1[11]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_1_reg[12]
(.C(clk_x16),
.CE(y1),
.D(Lxx_11[11]),
.Q(Lyy_1[12]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_1_reg[13]
(.C(clk_x16),
.CE(y1),
.D(Lxx_11[12]),
.Q(Lyy_1[13]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_1_reg[14]
(.C(clk_x16),
.CE(y1),
.D(Lxx_11[13]),
.Q(Lyy_1[14]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_1_reg[15]
(.C(clk_x16),
.CE(y1),
.D(Lxx_11[14]),
.Q(Lyy_1[15]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_1_reg[1]
(.C(clk_x16),
.CE(y1),
.D(Lxx_11[0]),
.Q(Lyy_1[1]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_1_reg[2]
(.C(clk_x16),
.CE(y1),
.D(Lxx_11[1]),
.Q(Lyy_1[2]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_1_reg[3]
(.C(clk_x16),
.CE(y1),
.D(Lxx_11[2]),
.Q(Lyy_1[3]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_1_reg[4]
(.C(clk_x16),
.CE(y1),
.D(Lxx_11[3]),
.Q(Lyy_1[4]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_1_reg[5]
(.C(clk_x16),
.CE(y1),
.D(Lxx_11[4]),
.Q(Lyy_1[5]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_1_reg[6]
(.C(clk_x16),
.CE(y1),
.D(Lxx_11[5]),
.Q(Lyy_1[6]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_1_reg[7]
(.C(clk_x16),
.CE(y1),
.D(Lxx_11[6]),
.Q(Lyy_1[7]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_1_reg[8]
(.C(clk_x16),
.CE(y1),
.D(Lxx_11[7]),
.Q(Lyy_1[8]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_1_reg[9]
(.C(clk_x16),
.CE(y1),
.D(Lxx_11[8]),
.Q(Lyy_1[9]),
.R(1'b0));
CARRY4 Lyy_20__1_carry
(.CI(1'b0),
.CO({Lyy_20__1_carry_n_0,Lyy_20__1_carry_n_1,Lyy_20__1_carry_n_2,Lyy_20__1_carry_n_3}),
.CYINIT(1'b0),
.DI({Lyy_20__1_carry_i_1_n_0,Lyy_20__1_carry_i_2_n_0,Lyy_20__1_carry_i_3_n_0,Lyy_2_bottom_right[0]}),
.O(Lyy_20[3:0]),
.S({Lyy_20__1_carry_i_4_n_0,Lyy_20__1_carry_i_5_n_0,Lyy_20__1_carry_i_6_n_0,Lyy_20__1_carry_i_7_n_0}));
CARRY4 Lyy_20__1_carry__0
(.CI(Lyy_20__1_carry_n_0),
.CO({Lyy_20__1_carry__0_n_0,Lyy_20__1_carry__0_n_1,Lyy_20__1_carry__0_n_2,Lyy_20__1_carry__0_n_3}),
.CYINIT(1'b0),
.DI({Lyy_20__1_carry__0_i_1_n_0,Lyy_20__1_carry__0_i_2_n_0,Lyy_20__1_carry__0_i_3_n_0,Lyy_20__1_carry__0_i_4_n_0}),
.O(Lyy_20[7:4]),
.S({Lyy_20__1_carry__0_i_5_n_0,Lyy_20__1_carry__0_i_6_n_0,Lyy_20__1_carry__0_i_7_n_0,Lyy_20__1_carry__0_i_8_n_0}));
LUT5 #(
.INIT(32'hFF969600))
Lyy_20__1_carry__0_i_1
(.I0(Lyy_2_top_left[6]),
.I1(Lyy_2_bottom_left[6]),
.I2(Lyy_2_top_right[6]),
.I3(Lyy_20__1_carry__0_i_9_n_0),
.I4(Lyy_2_bottom_right[6]),
.O(Lyy_20__1_carry__0_i_1_n_0));
(* SOFT_HLUTNM = "soft_lutpair51" *)
LUT3 #(
.INIT(8'h96))
Lyy_20__1_carry__0_i_10
(.I0(Lyy_2_top_left[5]),
.I1(Lyy_2_bottom_left[5]),
.I2(Lyy_2_top_right[5]),
.O(Lyy_20__1_carry__0_i_10_n_0));
(* SOFT_HLUTNM = "soft_lutpair52" *)
LUT3 #(
.INIT(8'h4D))
Lyy_20__1_carry__0_i_11
(.I0(Lyy_2_top_right[3]),
.I1(Lyy_2_top_left[3]),
.I2(Lyy_2_bottom_left[3]),
.O(Lyy_20__1_carry__0_i_11_n_0));
LUT3 #(
.INIT(8'h96))
Lyy_20__1_carry__0_i_12
(.I0(Lyy_2_top_left[7]),
.I1(Lyy_2_bottom_left[7]),
.I2(Lyy_2_top_right[7]),
.O(Lyy_20__1_carry__0_i_12_n_0));
LUT5 #(
.INIT(32'hBAFB20A2))
Lyy_20__1_carry__0_i_2
(.I0(Lyy_2_bottom_right[5]),
.I1(Lyy_2_bottom_left[4]),
.I2(Lyy_2_top_left[4]),
.I3(Lyy_2_top_right[4]),
.I4(Lyy_20__1_carry__0_i_10_n_0),
.O(Lyy_20__1_carry__0_i_2_n_0));
LUT5 #(
.INIT(32'hFF969600))
Lyy_20__1_carry__0_i_3
(.I0(Lyy_2_top_left[4]),
.I1(Lyy_2_bottom_left[4]),
.I2(Lyy_2_top_right[4]),
.I3(Lyy_20__1_carry__0_i_11_n_0),
.I4(Lyy_2_bottom_right[4]),
.O(Lyy_20__1_carry__0_i_3_n_0));
LUT5 #(
.INIT(32'hBAFB20A2))
Lyy_20__1_carry__0_i_4
(.I0(Lyy_2_bottom_right[3]),
.I1(Lyy_2_bottom_left[2]),
.I2(Lyy_2_top_left[2]),
.I3(Lyy_2_top_right[2]),
.I4(Lyy_20__1_carry_i_8_n_0),
.O(Lyy_20__1_carry__0_i_4_n_0));
LUT6 #(
.INIT(64'h9669969669699669))
Lyy_20__1_carry__0_i_5
(.I0(Lyy_20__1_carry__0_i_1_n_0),
.I1(Lyy_20__1_carry__0_i_12_n_0),
.I2(Lyy_2_bottom_right[7]),
.I3(Lyy_2_top_right[6]),
.I4(Lyy_2_top_left[6]),
.I5(Lyy_2_bottom_left[6]),
.O(Lyy_20__1_carry__0_i_5_n_0));
LUT6 #(
.INIT(64'h6996966996696996))
Lyy_20__1_carry__0_i_6
(.I0(Lyy_20__1_carry__0_i_2_n_0),
.I1(Lyy_2_top_right[6]),
.I2(Lyy_2_bottom_left[6]),
.I3(Lyy_2_top_left[6]),
.I4(Lyy_2_bottom_right[6]),
.I5(Lyy_20__1_carry__0_i_9_n_0),
.O(Lyy_20__1_carry__0_i_6_n_0));
LUT6 #(
.INIT(64'h9669969669699669))
Lyy_20__1_carry__0_i_7
(.I0(Lyy_20__1_carry__0_i_3_n_0),
.I1(Lyy_20__1_carry__0_i_10_n_0),
.I2(Lyy_2_bottom_right[5]),
.I3(Lyy_2_top_right[4]),
.I4(Lyy_2_top_left[4]),
.I5(Lyy_2_bottom_left[4]),
.O(Lyy_20__1_carry__0_i_7_n_0));
LUT6 #(
.INIT(64'h6996966996696996))
Lyy_20__1_carry__0_i_8
(.I0(Lyy_20__1_carry__0_i_4_n_0),
.I1(Lyy_2_top_right[4]),
.I2(Lyy_2_bottom_left[4]),
.I3(Lyy_2_top_left[4]),
.I4(Lyy_2_bottom_right[4]),
.I5(Lyy_20__1_carry__0_i_11_n_0),
.O(Lyy_20__1_carry__0_i_8_n_0));
(* SOFT_HLUTNM = "soft_lutpair51" *)
LUT3 #(
.INIT(8'h4D))
Lyy_20__1_carry__0_i_9
(.I0(Lyy_2_top_right[5]),
.I1(Lyy_2_top_left[5]),
.I2(Lyy_2_bottom_left[5]),
.O(Lyy_20__1_carry__0_i_9_n_0));
CARRY4 Lyy_20__1_carry__1
(.CI(Lyy_20__1_carry__0_n_0),
.CO({Lyy_20__1_carry__1_n_0,Lyy_20__1_carry__1_n_1,Lyy_20__1_carry__1_n_2,Lyy_20__1_carry__1_n_3}),
.CYINIT(1'b0),
.DI({Lyy_20__1_carry__1_i_1_n_0,Lyy_20__1_carry__1_i_2_n_0,Lyy_20__1_carry__1_i_3_n_0,Lyy_20__1_carry__1_i_4_n_0}),
.O(Lyy_20[11:8]),
.S({Lyy_20__1_carry__1_i_5_n_0,Lyy_20__1_carry__1_i_6_n_0,Lyy_20__1_carry__1_i_7_n_0,Lyy_20__1_carry__1_i_8_n_0}));
LUT5 #(
.INIT(32'hFF969600))
Lyy_20__1_carry__1_i_1
(.I0(Lyy_2_top_left[10]),
.I1(Lyy_2_bottom_left[10]),
.I2(Lyy_2_top_right[10]),
.I3(Lyy_20__1_carry__1_i_9_n_0),
.I4(Lyy_2_bottom_right[10]),
.O(Lyy_20__1_carry__1_i_1_n_0));
(* SOFT_HLUTNM = "soft_lutpair50" *)
LUT3 #(
.INIT(8'h96))
Lyy_20__1_carry__1_i_10
(.I0(Lyy_2_top_left[9]),
.I1(Lyy_2_bottom_left[9]),
.I2(Lyy_2_top_right[9]),
.O(Lyy_20__1_carry__1_i_10_n_0));
LUT3 #(
.INIT(8'h96))
Lyy_20__1_carry__1_i_11
(.I0(Lyy_2_top_left[8]),
.I1(Lyy_2_bottom_left[8]),
.I2(Lyy_2_top_right[8]),
.O(Lyy_20__1_carry__1_i_11_n_0));
LUT3 #(
.INIT(8'h4D))
Lyy_20__1_carry__1_i_12
(.I0(Lyy_2_top_right[10]),
.I1(Lyy_2_top_left[10]),
.I2(Lyy_2_bottom_left[10]),
.O(Lyy_20__1_carry__1_i_12_n_0));
LUT5 #(
.INIT(32'hBAFB20A2))
Lyy_20__1_carry__1_i_2
(.I0(Lyy_2_bottom_right[9]),
.I1(Lyy_2_bottom_left[8]),
.I2(Lyy_2_top_left[8]),
.I3(Lyy_2_top_right[8]),
.I4(Lyy_20__1_carry__1_i_10_n_0),
.O(Lyy_20__1_carry__1_i_2_n_0));
LUT5 #(
.INIT(32'hBAFB20A2))
Lyy_20__1_carry__1_i_3
(.I0(Lyy_2_bottom_right[8]),
.I1(Lyy_2_bottom_left[7]),
.I2(Lyy_2_top_left[7]),
.I3(Lyy_2_top_right[7]),
.I4(Lyy_20__1_carry__1_i_11_n_0),
.O(Lyy_20__1_carry__1_i_3_n_0));
LUT5 #(
.INIT(32'hBAFB20A2))
Lyy_20__1_carry__1_i_4
(.I0(Lyy_2_bottom_right[7]),
.I1(Lyy_2_bottom_left[6]),
.I2(Lyy_2_top_left[6]),
.I3(Lyy_2_top_right[6]),
.I4(Lyy_20__1_carry__0_i_12_n_0),
.O(Lyy_20__1_carry__1_i_4_n_0));
LUT6 #(
.INIT(64'h6996966996696996))
Lyy_20__1_carry__1_i_5
(.I0(Lyy_20__1_carry__1_i_1_n_0),
.I1(Lyy_2_top_right[11]),
.I2(Lyy_2_bottom_left[11]),
.I3(Lyy_2_top_left[11]),
.I4(Lyy_2_bottom_right[11]),
.I5(Lyy_20__1_carry__1_i_12_n_0),
.O(Lyy_20__1_carry__1_i_5_n_0));
LUT6 #(
.INIT(64'h6996966996696996))
Lyy_20__1_carry__1_i_6
(.I0(Lyy_20__1_carry__1_i_2_n_0),
.I1(Lyy_2_top_right[10]),
.I2(Lyy_2_bottom_left[10]),
.I3(Lyy_2_top_left[10]),
.I4(Lyy_2_bottom_right[10]),
.I5(Lyy_20__1_carry__1_i_9_n_0),
.O(Lyy_20__1_carry__1_i_6_n_0));
LUT6 #(
.INIT(64'h9669969669699669))
Lyy_20__1_carry__1_i_7
(.I0(Lyy_20__1_carry__1_i_3_n_0),
.I1(Lyy_20__1_carry__1_i_10_n_0),
.I2(Lyy_2_bottom_right[9]),
.I3(Lyy_2_top_right[8]),
.I4(Lyy_2_top_left[8]),
.I5(Lyy_2_bottom_left[8]),
.O(Lyy_20__1_carry__1_i_7_n_0));
LUT6 #(
.INIT(64'h9669969669699669))
Lyy_20__1_carry__1_i_8
(.I0(Lyy_20__1_carry__1_i_4_n_0),
.I1(Lyy_20__1_carry__1_i_11_n_0),
.I2(Lyy_2_bottom_right[8]),
.I3(Lyy_2_top_right[7]),
.I4(Lyy_2_top_left[7]),
.I5(Lyy_2_bottom_left[7]),
.O(Lyy_20__1_carry__1_i_8_n_0));
(* SOFT_HLUTNM = "soft_lutpair50" *)
LUT3 #(
.INIT(8'h4D))
Lyy_20__1_carry__1_i_9
(.I0(Lyy_2_top_right[9]),
.I1(Lyy_2_top_left[9]),
.I2(Lyy_2_bottom_left[9]),
.O(Lyy_20__1_carry__1_i_9_n_0));
CARRY4 Lyy_20__1_carry__2
(.CI(Lyy_20__1_carry__1_n_0),
.CO({NLW_Lyy_20__1_carry__2_CO_UNCONNECTED[3],Lyy_20__1_carry__2_n_1,Lyy_20__1_carry__2_n_2,Lyy_20__1_carry__2_n_3}),
.CYINIT(1'b0),
.DI({1'b0,Lyy_20__1_carry__2_i_1_n_0,Lyy_20__1_carry__2_i_2_n_0,Lyy_20__1_carry__2_i_3_n_0}),
.O(Lyy_20[15:12]),
.S({Lyy_20__1_carry__2_i_4_n_0,Lyy_20__1_carry__2_i_5_n_0,Lyy_20__1_carry__2_i_6_n_0,Lyy_20__1_carry__2_i_7_n_0}));
LUT5 #(
.INIT(32'hBAFB20A2))
Lyy_20__1_carry__2_i_1
(.I0(Lyy_2_bottom_right[13]),
.I1(Lyy_2_top_right[12]),
.I2(Lyy_2_top_left[12]),
.I3(Lyy_2_bottom_left[12]),
.I4(Lyy_20__1_carry__2_i_8_n_0),
.O(Lyy_20__1_carry__2_i_1_n_0));
(* SOFT_HLUTNM = "soft_lutpair49" *)
LUT3 #(
.INIT(8'h2B))
Lyy_20__1_carry__2_i_10
(.I0(Lyy_2_top_left[13]),
.I1(Lyy_2_bottom_left[13]),
.I2(Lyy_2_top_right[13]),
.O(Lyy_20__1_carry__2_i_10_n_0));
LUT4 #(
.INIT(16'h6996))
Lyy_20__1_carry__2_i_11
(.I0(Lyy_2_top_right[15]),
.I1(Lyy_2_bottom_left[15]),
.I2(Lyy_2_top_left[15]),
.I3(Lyy_2_bottom_right[15]),
.O(Lyy_20__1_carry__2_i_11_n_0));
LUT5 #(
.INIT(32'hBAFB20A2))
Lyy_20__1_carry__2_i_2
(.I0(Lyy_2_bottom_right[12]),
.I1(Lyy_2_bottom_left[11]),
.I2(Lyy_2_top_left[11]),
.I3(Lyy_2_top_right[11]),
.I4(Lyy_20__1_carry__2_i_9_n_0),
.O(Lyy_20__1_carry__2_i_2_n_0));
LUT5 #(
.INIT(32'hFF969600))
Lyy_20__1_carry__2_i_3
(.I0(Lyy_2_top_left[11]),
.I1(Lyy_2_bottom_left[11]),
.I2(Lyy_2_top_right[11]),
.I3(Lyy_20__1_carry__1_i_12_n_0),
.I4(Lyy_2_bottom_right[11]),
.O(Lyy_20__1_carry__2_i_3_n_0));
LUT6 #(
.INIT(64'h1E78871E871EE187))
Lyy_20__1_carry__2_i_4
(.I0(Lyy_2_bottom_right[14]),
.I1(Lyy_20__1_carry__2_i_10_n_0),
.I2(Lyy_20__1_carry__2_i_11_n_0),
.I3(Lyy_2_top_left[14]),
.I4(Lyy_2_bottom_left[14]),
.I5(Lyy_2_top_right[14]),
.O(Lyy_20__1_carry__2_i_4_n_0));
LUT6 #(
.INIT(64'h6996966996696996))
Lyy_20__1_carry__2_i_5
(.I0(Lyy_20__1_carry__2_i_1_n_0),
.I1(Lyy_2_top_right[14]),
.I2(Lyy_2_bottom_left[14]),
.I3(Lyy_2_top_left[14]),
.I4(Lyy_2_bottom_right[14]),
.I5(Lyy_20__1_carry__2_i_10_n_0),
.O(Lyy_20__1_carry__2_i_5_n_0));
LUT6 #(
.INIT(64'h9669969669699669))
Lyy_20__1_carry__2_i_6
(.I0(Lyy_20__1_carry__2_i_2_n_0),
.I1(Lyy_20__1_carry__2_i_8_n_0),
.I2(Lyy_2_bottom_right[13]),
.I3(Lyy_2_bottom_left[12]),
.I4(Lyy_2_top_left[12]),
.I5(Lyy_2_top_right[12]),
.O(Lyy_20__1_carry__2_i_6_n_0));
LUT6 #(
.INIT(64'h9669969669699669))
Lyy_20__1_carry__2_i_7
(.I0(Lyy_20__1_carry__2_i_3_n_0),
.I1(Lyy_20__1_carry__2_i_9_n_0),
.I2(Lyy_2_bottom_right[12]),
.I3(Lyy_2_top_right[11]),
.I4(Lyy_2_top_left[11]),
.I5(Lyy_2_bottom_left[11]),
.O(Lyy_20__1_carry__2_i_7_n_0));
(* SOFT_HLUTNM = "soft_lutpair49" *)
LUT3 #(
.INIT(8'h96))
Lyy_20__1_carry__2_i_8
(.I0(Lyy_2_top_left[13]),
.I1(Lyy_2_bottom_left[13]),
.I2(Lyy_2_top_right[13]),
.O(Lyy_20__1_carry__2_i_8_n_0));
LUT3 #(
.INIT(8'h96))
Lyy_20__1_carry__2_i_9
(.I0(Lyy_2_top_left[12]),
.I1(Lyy_2_bottom_left[12]),
.I2(Lyy_2_top_right[12]),
.O(Lyy_20__1_carry__2_i_9_n_0));
LUT6 #(
.INIT(64'h96FFFFFF00969696))
Lyy_20__1_carry_i_1
(.I0(Lyy_2_top_left[2]),
.I1(Lyy_2_bottom_left[2]),
.I2(Lyy_2_top_right[2]),
.I3(Lyy_2_top_right[1]),
.I4(Lyy_2_bottom_left[1]),
.I5(Lyy_2_bottom_right[2]),
.O(Lyy_20__1_carry_i_1_n_0));
LUT4 #(
.INIT(16'hF990))
Lyy_20__1_carry_i_2
(.I0(Lyy_2_top_right[1]),
.I1(Lyy_2_bottom_left[1]),
.I2(Lyy_2_top_left[1]),
.I3(Lyy_2_bottom_right[1]),
.O(Lyy_20__1_carry_i_2_n_0));
LUT4 #(
.INIT(16'h9669))
Lyy_20__1_carry_i_3
(.I0(Lyy_2_bottom_left[1]),
.I1(Lyy_2_top_right[1]),
.I2(Lyy_2_top_left[1]),
.I3(Lyy_2_bottom_right[1]),
.O(Lyy_20__1_carry_i_3_n_0));
LUT6 #(
.INIT(64'h9669969669699669))
Lyy_20__1_carry_i_4
(.I0(Lyy_20__1_carry_i_1_n_0),
.I1(Lyy_20__1_carry_i_8_n_0),
.I2(Lyy_2_bottom_right[3]),
.I3(Lyy_2_top_right[2]),
.I4(Lyy_2_top_left[2]),
.I5(Lyy_2_bottom_left[2]),
.O(Lyy_20__1_carry_i_4_n_0));
LUT6 #(
.INIT(64'h6996966996696996))
Lyy_20__1_carry_i_5
(.I0(Lyy_20__1_carry_i_2_n_0),
.I1(Lyy_2_top_right[2]),
.I2(Lyy_2_bottom_left[2]),
.I3(Lyy_2_top_left[2]),
.I4(Lyy_2_bottom_right[2]),
.I5(Lyy_20__1_carry_i_9_n_0),
.O(Lyy_20__1_carry_i_5_n_0));
LUT4 #(
.INIT(16'h9A59))
Lyy_20__1_carry_i_6
(.I0(Lyy_20__1_carry_i_3_n_0),
.I1(Lyy_2_bottom_left[0]),
.I2(Lyy_2_top_left[0]),
.I3(Lyy_2_top_right[0]),
.O(Lyy_20__1_carry_i_6_n_0));
LUT4 #(
.INIT(16'h6996))
Lyy_20__1_carry_i_7
(.I0(Lyy_2_top_right[0]),
.I1(Lyy_2_bottom_left[0]),
.I2(Lyy_2_top_left[0]),
.I3(Lyy_2_bottom_right[0]),
.O(Lyy_20__1_carry_i_7_n_0));
(* SOFT_HLUTNM = "soft_lutpair52" *)
LUT3 #(
.INIT(8'h96))
Lyy_20__1_carry_i_8
(.I0(Lyy_2_top_left[3]),
.I1(Lyy_2_bottom_left[3]),
.I2(Lyy_2_top_right[3]),
.O(Lyy_20__1_carry_i_8_n_0));
LUT2 #(
.INIT(4'h7))
Lyy_20__1_carry_i_9
(.I0(Lyy_2_bottom_left[1]),
.I1(Lyy_2_top_right[1]),
.O(Lyy_20__1_carry_i_9_n_0));
LUT6 #(
.INIT(64'h0020000000000000))
\Lyy_2[15]_i_1
(.I0(\cycle_reg[1]_rep_n_0 ),
.I1(\cycle_reg[0]_rep_n_0 ),
.I2(cycle[2]),
.I3(cycle[3]),
.I4(rst),
.I5(active),
.O(\Lyy_2[15]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\Lyy_2_bottom_left_reg[0]
(.C(clk_x16),
.CE(y5),
.D(\cache_reg[4]_0 [0]),
.Q(Lyy_2_bottom_left[0]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_2_bottom_left_reg[10]
(.C(clk_x16),
.CE(y5),
.D(\cache_reg[4]_0 [10]),
.Q(Lyy_2_bottom_left[10]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_2_bottom_left_reg[11]
(.C(clk_x16),
.CE(y5),
.D(\cache_reg[4]_0 [11]),
.Q(Lyy_2_bottom_left[11]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_2_bottom_left_reg[12]
(.C(clk_x16),
.CE(y5),
.D(\cache_reg[4]_0 [12]),
.Q(Lyy_2_bottom_left[12]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_2_bottom_left_reg[13]
(.C(clk_x16),
.CE(y5),
.D(\cache_reg[4]_0 [13]),
.Q(Lyy_2_bottom_left[13]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_2_bottom_left_reg[14]
(.C(clk_x16),
.CE(y5),
.D(\cache_reg[4]_0 [14]),
.Q(Lyy_2_bottom_left[14]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_2_bottom_left_reg[15]
(.C(clk_x16),
.CE(y5),
.D(\cache_reg[4]_0 [15]),
.Q(Lyy_2_bottom_left[15]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_2_bottom_left_reg[1]
(.C(clk_x16),
.CE(y5),
.D(\cache_reg[4]_0 [1]),
.Q(Lyy_2_bottom_left[1]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_2_bottom_left_reg[2]
(.C(clk_x16),
.CE(y5),
.D(\cache_reg[4]_0 [2]),
.Q(Lyy_2_bottom_left[2]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_2_bottom_left_reg[3]
(.C(clk_x16),
.CE(y5),
.D(\cache_reg[4]_0 [3]),
.Q(Lyy_2_bottom_left[3]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_2_bottom_left_reg[4]
(.C(clk_x16),
.CE(y5),
.D(\cache_reg[4]_0 [4]),
.Q(Lyy_2_bottom_left[4]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_2_bottom_left_reg[5]
(.C(clk_x16),
.CE(y5),
.D(\cache_reg[4]_0 [5]),
.Q(Lyy_2_bottom_left[5]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_2_bottom_left_reg[6]
(.C(clk_x16),
.CE(y5),
.D(\cache_reg[4]_0 [6]),
.Q(Lyy_2_bottom_left[6]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_2_bottom_left_reg[7]
(.C(clk_x16),
.CE(y5),
.D(\cache_reg[4]_0 [7]),
.Q(Lyy_2_bottom_left[7]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_2_bottom_left_reg[8]
(.C(clk_x16),
.CE(y5),
.D(\cache_reg[4]_0 [8]),
.Q(Lyy_2_bottom_left[8]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_2_bottom_left_reg[9]
(.C(clk_x16),
.CE(y5),
.D(\cache_reg[4]_0 [9]),
.Q(Lyy_2_bottom_left[9]),
.R(1'b0));
CARRY4 Lyy_2_bottom_right0__0_carry
(.CI(1'b0),
.CO({Lyy_2_bottom_right0__0_carry_n_0,Lyy_2_bottom_right0__0_carry_n_1,Lyy_2_bottom_right0__0_carry_n_2,Lyy_2_bottom_right0__0_carry_n_3}),
.CYINIT(1'b0),
.DI({Lyy_2_bottom_right0__0_carry_i_1_n_0,Lyy_2_bottom_right0__0_carry_i_2_n_0,Lyy_2_bottom_right0__0_carry_i_3_n_0,Lyy_2_bottom_right0__0_carry_i_4_n_0}),
.O(Lyy_2_bottom_right01_out[3:0]),
.S({Lyy_2_bottom_right0__0_carry_i_5_n_0,Lyy_2_bottom_right0__0_carry_i_6_n_0,Lyy_2_bottom_right0__0_carry_i_7_n_0,Lyy_2_bottom_right0__0_carry_i_8_n_0}));
CARRY4 Lyy_2_bottom_right0__0_carry__0
(.CI(Lyy_2_bottom_right0__0_carry_n_0),
.CO({Lyy_2_bottom_right0__0_carry__0_n_0,Lyy_2_bottom_right0__0_carry__0_n_1,Lyy_2_bottom_right0__0_carry__0_n_2,Lyy_2_bottom_right0__0_carry__0_n_3}),
.CYINIT(1'b0),
.DI({Lyy_2_bottom_right0__0_carry__0_i_1_n_0,Lyy_2_bottom_right0__0_carry__0_i_2_n_0,Lyy_2_bottom_right0__0_carry__0_i_3_n_0,Lyy_2_bottom_right0__0_carry__0_i_4_n_0}),
.O(Lyy_2_bottom_right01_out[7:4]),
.S({Lyy_2_bottom_right0__0_carry__0_i_5_n_0,Lyy_2_bottom_right0__0_carry__0_i_6_n_0,Lyy_2_bottom_right0__0_carry__0_i_7_n_0,Lyy_2_bottom_right0__0_carry__0_i_8_n_0}));
LUT5 #(
.INIT(32'hEE8E8E88))
Lyy_2_bottom_right0__0_carry__0_i_1
(.I0(last_value[6]),
.I1(Lyy_2_bottom_right0__0_carry__0_i_9_n_0),
.I2(\corner_reg_n_0_[5] ),
.I3(\top_reg_n_0_[5] ),
.I4(\left_reg_n_0_[5] ),
.O(Lyy_2_bottom_right0__0_carry__0_i_1_n_0));
LUT3 #(
.INIT(8'h69))
Lyy_2_bottom_right0__0_carry__0_i_10
(.I0(\corner_reg_n_0_[5] ),
.I1(\left_reg_n_0_[5] ),
.I2(\top_reg_n_0_[5] ),
.O(Lyy_2_bottom_right0__0_carry__0_i_10_n_0));
LUT3 #(
.INIT(8'h69))
Lyy_2_bottom_right0__0_carry__0_i_11
(.I0(\corner_reg_n_0_[4] ),
.I1(\left_reg_n_0_[4] ),
.I2(\top_reg_n_0_[4] ),
.O(Lyy_2_bottom_right0__0_carry__0_i_11_n_0));
LUT3 #(
.INIT(8'h69))
Lyy_2_bottom_right0__0_carry__0_i_12
(.I0(\corner_reg_n_0_[7] ),
.I1(\left_reg_n_0_[7] ),
.I2(\top_reg_n_0_[7] ),
.O(Lyy_2_bottom_right0__0_carry__0_i_12_n_0));
LUT5 #(
.INIT(32'hEE8E8E88))
Lyy_2_bottom_right0__0_carry__0_i_2
(.I0(last_value[5]),
.I1(Lyy_2_bottom_right0__0_carry__0_i_10_n_0),
.I2(\corner_reg_n_0_[4] ),
.I3(\top_reg_n_0_[4] ),
.I4(\left_reg_n_0_[4] ),
.O(Lyy_2_bottom_right0__0_carry__0_i_2_n_0));
LUT5 #(
.INIT(32'hEE8E8E88))
Lyy_2_bottom_right0__0_carry__0_i_3
(.I0(last_value[4]),
.I1(Lyy_2_bottom_right0__0_carry__0_i_11_n_0),
.I2(\corner_reg_n_0_[3] ),
.I3(\top_reg_n_0_[3] ),
.I4(\left_reg_n_0_[3] ),
.O(Lyy_2_bottom_right0__0_carry__0_i_3_n_0));
LUT5 #(
.INIT(32'hEE8E8E88))
Lyy_2_bottom_right0__0_carry__0_i_4
(.I0(last_value[3]),
.I1(Lyy_2_bottom_right0__0_carry_i_10_n_0),
.I2(\corner_reg_n_0_[2] ),
.I3(\top_reg_n_0_[2] ),
.I4(\left_reg_n_0_[2] ),
.O(Lyy_2_bottom_right0__0_carry__0_i_4_n_0));
LUT6 #(
.INIT(64'h6996969669696996))
Lyy_2_bottom_right0__0_carry__0_i_5
(.I0(Lyy_2_bottom_right0__0_carry__0_i_1_n_0),
.I1(Lyy_2_bottom_right0__0_carry__0_i_12_n_0),
.I2(last_value[7]),
.I3(\left_reg_n_0_[6] ),
.I4(\top_reg_n_0_[6] ),
.I5(\corner_reg_n_0_[6] ),
.O(Lyy_2_bottom_right0__0_carry__0_i_5_n_0));
LUT6 #(
.INIT(64'h6996969669696996))
Lyy_2_bottom_right0__0_carry__0_i_6
(.I0(Lyy_2_bottom_right0__0_carry__0_i_2_n_0),
.I1(Lyy_2_bottom_right0__0_carry__0_i_9_n_0),
.I2(last_value[6]),
.I3(\left_reg_n_0_[5] ),
.I4(\top_reg_n_0_[5] ),
.I5(\corner_reg_n_0_[5] ),
.O(Lyy_2_bottom_right0__0_carry__0_i_6_n_0));
LUT6 #(
.INIT(64'h6996969669696996))
Lyy_2_bottom_right0__0_carry__0_i_7
(.I0(Lyy_2_bottom_right0__0_carry__0_i_3_n_0),
.I1(Lyy_2_bottom_right0__0_carry__0_i_10_n_0),
.I2(last_value[5]),
.I3(\left_reg_n_0_[4] ),
.I4(\top_reg_n_0_[4] ),
.I5(\corner_reg_n_0_[4] ),
.O(Lyy_2_bottom_right0__0_carry__0_i_7_n_0));
LUT6 #(
.INIT(64'h6996969669696996))
Lyy_2_bottom_right0__0_carry__0_i_8
(.I0(Lyy_2_bottom_right0__0_carry__0_i_4_n_0),
.I1(Lyy_2_bottom_right0__0_carry__0_i_11_n_0),
.I2(last_value[4]),
.I3(\left_reg_n_0_[3] ),
.I4(\top_reg_n_0_[3] ),
.I5(\corner_reg_n_0_[3] ),
.O(Lyy_2_bottom_right0__0_carry__0_i_8_n_0));
LUT3 #(
.INIT(8'h69))
Lyy_2_bottom_right0__0_carry__0_i_9
(.I0(\corner_reg_n_0_[6] ),
.I1(\left_reg_n_0_[6] ),
.I2(\top_reg_n_0_[6] ),
.O(Lyy_2_bottom_right0__0_carry__0_i_9_n_0));
CARRY4 Lyy_2_bottom_right0__0_carry__1
(.CI(Lyy_2_bottom_right0__0_carry__0_n_0),
.CO({Lyy_2_bottom_right0__0_carry__1_n_0,Lyy_2_bottom_right0__0_carry__1_n_1,Lyy_2_bottom_right0__0_carry__1_n_2,Lyy_2_bottom_right0__0_carry__1_n_3}),
.CYINIT(1'b0),
.DI({Lyy_2_bottom_right0__0_carry__1_i_1_n_0,Lyy_2_bottom_right0__0_carry__1_i_2_n_0,Lyy_2_bottom_right0__0_carry__1_i_3_n_0,Lyy_2_bottom_right0__0_carry__1_i_4_n_0}),
.O(Lyy_2_bottom_right01_out[11:8]),
.S({Lyy_2_bottom_right0__0_carry__1_i_5_n_0,Lyy_2_bottom_right0__0_carry__1_i_6_n_0,Lyy_2_bottom_right0__0_carry__1_i_7_n_0,Lyy_2_bottom_right0__0_carry__1_i_8_n_0}));
LUT6 #(
.INIT(64'h6969006900690000))
Lyy_2_bottom_right0__0_carry__1_i_1
(.I0(\top_reg_n_0_[10] ),
.I1(\left_reg_n_0_[10] ),
.I2(\corner_reg_n_0_[10] ),
.I3(\corner_reg_n_0_[9] ),
.I4(\top_reg_n_0_[9] ),
.I5(\left_reg_n_0_[9] ),
.O(Lyy_2_bottom_right0__0_carry__1_i_1_n_0));
LUT3 #(
.INIT(8'h69))
Lyy_2_bottom_right0__0_carry__1_i_10
(.I0(\corner_reg_n_0_[10] ),
.I1(\left_reg_n_0_[10] ),
.I2(\top_reg_n_0_[10] ),
.O(Lyy_2_bottom_right0__0_carry__1_i_10_n_0));
LUT3 #(
.INIT(8'h69))
Lyy_2_bottom_right0__0_carry__1_i_11
(.I0(\corner_reg_n_0_[9] ),
.I1(\left_reg_n_0_[9] ),
.I2(\top_reg_n_0_[9] ),
.O(Lyy_2_bottom_right0__0_carry__1_i_11_n_0));
LUT3 #(
.INIT(8'h69))
Lyy_2_bottom_right0__0_carry__1_i_12
(.I0(\corner_reg_n_0_[8] ),
.I1(\left_reg_n_0_[8] ),
.I2(\top_reg_n_0_[8] ),
.O(Lyy_2_bottom_right0__0_carry__1_i_12_n_0));
LUT6 #(
.INIT(64'h6969006900690000))
Lyy_2_bottom_right0__0_carry__1_i_2
(.I0(\top_reg_n_0_[9] ),
.I1(\left_reg_n_0_[9] ),
.I2(\corner_reg_n_0_[9] ),
.I3(\corner_reg_n_0_[8] ),
.I4(\top_reg_n_0_[8] ),
.I5(\left_reg_n_0_[8] ),
.O(Lyy_2_bottom_right0__0_carry__1_i_2_n_0));
LUT6 #(
.INIT(64'h6969006900690000))
Lyy_2_bottom_right0__0_carry__1_i_3
(.I0(\top_reg_n_0_[8] ),
.I1(\left_reg_n_0_[8] ),
.I2(\corner_reg_n_0_[8] ),
.I3(\corner_reg_n_0_[7] ),
.I4(\top_reg_n_0_[7] ),
.I5(\left_reg_n_0_[7] ),
.O(Lyy_2_bottom_right0__0_carry__1_i_3_n_0));
LUT5 #(
.INIT(32'hEE8E8E88))
Lyy_2_bottom_right0__0_carry__1_i_4
(.I0(last_value[7]),
.I1(Lyy_2_bottom_right0__0_carry__0_i_12_n_0),
.I2(\corner_reg_n_0_[6] ),
.I3(\top_reg_n_0_[6] ),
.I4(\left_reg_n_0_[6] ),
.O(Lyy_2_bottom_right0__0_carry__1_i_4_n_0));
LUT5 #(
.INIT(32'h96669996))
Lyy_2_bottom_right0__0_carry__1_i_5
(.I0(Lyy_2_bottom_right0__0_carry__1_i_1_n_0),
.I1(Lyy_2_bottom_right0__0_carry__1_i_9_n_0),
.I2(\left_reg_n_0_[10] ),
.I3(\top_reg_n_0_[10] ),
.I4(\corner_reg_n_0_[10] ),
.O(Lyy_2_bottom_right0__0_carry__1_i_5_n_0));
LUT5 #(
.INIT(32'h96669996))
Lyy_2_bottom_right0__0_carry__1_i_6
(.I0(Lyy_2_bottom_right0__0_carry__1_i_2_n_0),
.I1(Lyy_2_bottom_right0__0_carry__1_i_10_n_0),
.I2(\left_reg_n_0_[9] ),
.I3(\top_reg_n_0_[9] ),
.I4(\corner_reg_n_0_[9] ),
.O(Lyy_2_bottom_right0__0_carry__1_i_6_n_0));
LUT5 #(
.INIT(32'h96669996))
Lyy_2_bottom_right0__0_carry__1_i_7
(.I0(Lyy_2_bottom_right0__0_carry__1_i_3_n_0),
.I1(Lyy_2_bottom_right0__0_carry__1_i_11_n_0),
.I2(\left_reg_n_0_[8] ),
.I3(\top_reg_n_0_[8] ),
.I4(\corner_reg_n_0_[8] ),
.O(Lyy_2_bottom_right0__0_carry__1_i_7_n_0));
LUT5 #(
.INIT(32'h96669996))
Lyy_2_bottom_right0__0_carry__1_i_8
(.I0(Lyy_2_bottom_right0__0_carry__1_i_4_n_0),
.I1(Lyy_2_bottom_right0__0_carry__1_i_12_n_0),
.I2(\left_reg_n_0_[7] ),
.I3(\top_reg_n_0_[7] ),
.I4(\corner_reg_n_0_[7] ),
.O(Lyy_2_bottom_right0__0_carry__1_i_8_n_0));
LUT3 #(
.INIT(8'h69))
Lyy_2_bottom_right0__0_carry__1_i_9
(.I0(\corner_reg_n_0_[11] ),
.I1(\left_reg_n_0_[11] ),
.I2(\top_reg_n_0_[11] ),
.O(Lyy_2_bottom_right0__0_carry__1_i_9_n_0));
CARRY4 Lyy_2_bottom_right0__0_carry__2
(.CI(Lyy_2_bottom_right0__0_carry__1_n_0),
.CO({NLW_Lyy_2_bottom_right0__0_carry__2_CO_UNCONNECTED[3],Lyy_2_bottom_right0__0_carry__2_n_1,Lyy_2_bottom_right0__0_carry__2_n_2,Lyy_2_bottom_right0__0_carry__2_n_3}),
.CYINIT(1'b0),
.DI({1'b0,Lyy_2_bottom_right0__0_carry__2_i_1_n_0,Lyy_2_bottom_right0__0_carry__2_i_2_n_0,Lyy_2_bottom_right0__0_carry__2_i_3_n_0}),
.O(Lyy_2_bottom_right01_out[15:12]),
.S({Lyy_2_bottom_right0__0_carry__2_i_4_n_0,Lyy_2_bottom_right0__0_carry__2_i_5_n_0,Lyy_2_bottom_right0__0_carry__2_i_6_n_0,Lyy_2_bottom_right0__0_carry__2_i_7_n_0}));
LUT6 #(
.INIT(64'h6969006900690000))
Lyy_2_bottom_right0__0_carry__2_i_1
(.I0(\top_reg_n_0_[13] ),
.I1(\left_reg_n_0_[13] ),
.I2(\corner_reg_n_0_[13] ),
.I3(\corner_reg_n_0_[12] ),
.I4(\top_reg_n_0_[12] ),
.I5(\left_reg_n_0_[12] ),
.O(Lyy_2_bottom_right0__0_carry__2_i_1_n_0));
LUT3 #(
.INIT(8'h69))
Lyy_2_bottom_right0__0_carry__2_i_10
(.I0(\corner_reg_n_0_[14] ),
.I1(\left_reg_n_0_[14] ),
.I2(\top_reg_n_0_[14] ),
.O(Lyy_2_bottom_right0__0_carry__2_i_10_n_0));
(* SOFT_HLUTNM = "soft_lutpair33" *)
LUT3 #(
.INIT(8'h69))
Lyy_2_bottom_right0__0_carry__2_i_11
(.I0(\corner_reg_n_0_[13] ),
.I1(\left_reg_n_0_[13] ),
.I2(\top_reg_n_0_[13] ),
.O(Lyy_2_bottom_right0__0_carry__2_i_11_n_0));
LUT3 #(
.INIT(8'h69))
Lyy_2_bottom_right0__0_carry__2_i_12
(.I0(\corner_reg_n_0_[12] ),
.I1(\left_reg_n_0_[12] ),
.I2(\top_reg_n_0_[12] ),
.O(Lyy_2_bottom_right0__0_carry__2_i_12_n_0));
LUT6 #(
.INIT(64'h6969006900690000))
Lyy_2_bottom_right0__0_carry__2_i_2
(.I0(\top_reg_n_0_[12] ),
.I1(\left_reg_n_0_[12] ),
.I2(\corner_reg_n_0_[12] ),
.I3(\corner_reg_n_0_[11] ),
.I4(\top_reg_n_0_[11] ),
.I5(\left_reg_n_0_[11] ),
.O(Lyy_2_bottom_right0__0_carry__2_i_2_n_0));
LUT6 #(
.INIT(64'h6969006900690000))
Lyy_2_bottom_right0__0_carry__2_i_3
(.I0(\top_reg_n_0_[11] ),
.I1(\left_reg_n_0_[11] ),
.I2(\corner_reg_n_0_[11] ),
.I3(\corner_reg_n_0_[10] ),
.I4(\top_reg_n_0_[10] ),
.I5(\left_reg_n_0_[10] ),
.O(Lyy_2_bottom_right0__0_carry__2_i_3_n_0));
LUT5 #(
.INIT(32'hD77D2882))
Lyy_2_bottom_right0__0_carry__2_i_4
(.I0(Lyy_2_bottom_right0__0_carry__2_i_8_n_0),
.I1(\corner_reg_n_0_[14] ),
.I2(\left_reg_n_0_[14] ),
.I3(\top_reg_n_0_[14] ),
.I4(Lyy_2_bottom_right0__0_carry__2_i_9_n_0),
.O(Lyy_2_bottom_right0__0_carry__2_i_4_n_0));
LUT5 #(
.INIT(32'h96669996))
Lyy_2_bottom_right0__0_carry__2_i_5
(.I0(Lyy_2_bottom_right0__0_carry__2_i_1_n_0),
.I1(Lyy_2_bottom_right0__0_carry__2_i_10_n_0),
.I2(\left_reg_n_0_[13] ),
.I3(\top_reg_n_0_[13] ),
.I4(\corner_reg_n_0_[13] ),
.O(Lyy_2_bottom_right0__0_carry__2_i_5_n_0));
LUT5 #(
.INIT(32'h96669996))
Lyy_2_bottom_right0__0_carry__2_i_6
(.I0(Lyy_2_bottom_right0__0_carry__2_i_2_n_0),
.I1(Lyy_2_bottom_right0__0_carry__2_i_11_n_0),
.I2(\left_reg_n_0_[12] ),
.I3(\top_reg_n_0_[12] ),
.I4(\corner_reg_n_0_[12] ),
.O(Lyy_2_bottom_right0__0_carry__2_i_6_n_0));
LUT5 #(
.INIT(32'h96669996))
Lyy_2_bottom_right0__0_carry__2_i_7
(.I0(Lyy_2_bottom_right0__0_carry__2_i_3_n_0),
.I1(Lyy_2_bottom_right0__0_carry__2_i_12_n_0),
.I2(\left_reg_n_0_[11] ),
.I3(\top_reg_n_0_[11] ),
.I4(\corner_reg_n_0_[11] ),
.O(Lyy_2_bottom_right0__0_carry__2_i_7_n_0));
(* SOFT_HLUTNM = "soft_lutpair33" *)
LUT3 #(
.INIT(8'h8E))
Lyy_2_bottom_right0__0_carry__2_i_8
(.I0(\left_reg_n_0_[13] ),
.I1(\top_reg_n_0_[13] ),
.I2(\corner_reg_n_0_[13] ),
.O(Lyy_2_bottom_right0__0_carry__2_i_8_n_0));
LUT6 #(
.INIT(64'hD42B2BD42BD4D42B))
Lyy_2_bottom_right0__0_carry__2_i_9
(.I0(\corner_reg_n_0_[14] ),
.I1(\top_reg_n_0_[14] ),
.I2(\left_reg_n_0_[14] ),
.I3(\top_reg_n_0_[15] ),
.I4(\left_reg_n_0_[15] ),
.I5(\corner_reg_n_0_[15] ),
.O(Lyy_2_bottom_right0__0_carry__2_i_9_n_0));
LUT5 #(
.INIT(32'hEE8E8E88))
Lyy_2_bottom_right0__0_carry_i_1
(.I0(last_value[2]),
.I1(Lyy_2_bottom_right0__0_carry_i_9_n_0),
.I2(\corner_reg_n_0_[1] ),
.I3(\top_reg_n_0_[1] ),
.I4(\left_reg_n_0_[1] ),
.O(Lyy_2_bottom_right0__0_carry_i_1_n_0));
LUT3 #(
.INIT(8'h69))
Lyy_2_bottom_right0__0_carry_i_10
(.I0(\corner_reg_n_0_[3] ),
.I1(\left_reg_n_0_[3] ),
.I2(\top_reg_n_0_[3] ),
.O(Lyy_2_bottom_right0__0_carry_i_10_n_0));
LUT3 #(
.INIT(8'h69))
Lyy_2_bottom_right0__0_carry_i_11
(.I0(\corner_reg_n_0_[1] ),
.I1(\left_reg_n_0_[1] ),
.I2(\top_reg_n_0_[1] ),
.O(Lyy_2_bottom_right0__0_carry_i_11_n_0));
LUT6 #(
.INIT(64'h20BABA20BA2020BA))
Lyy_2_bottom_right0__0_carry_i_2
(.I0(last_value[1]),
.I1(\corner_reg_n_0_[0] ),
.I2(last_value[0]),
.I3(\top_reg_n_0_[1] ),
.I4(\left_reg_n_0_[1] ),
.I5(\corner_reg_n_0_[1] ),
.O(Lyy_2_bottom_right0__0_carry_i_2_n_0));
LUT6 #(
.INIT(64'h9669966969969669))
Lyy_2_bottom_right0__0_carry_i_3
(.I0(\top_reg_n_0_[1] ),
.I1(\left_reg_n_0_[1] ),
.I2(\corner_reg_n_0_[1] ),
.I3(last_value[1]),
.I4(last_value[0]),
.I5(\corner_reg_n_0_[0] ),
.O(Lyy_2_bottom_right0__0_carry_i_3_n_0));
LUT2 #(
.INIT(4'h9))
Lyy_2_bottom_right0__0_carry_i_4
(.I0(\left_reg_n_0_[0] ),
.I1(\top_reg_n_0_[0] ),
.O(Lyy_2_bottom_right0__0_carry_i_4_n_0));
LUT6 #(
.INIT(64'h6996969669696996))
Lyy_2_bottom_right0__0_carry_i_5
(.I0(Lyy_2_bottom_right0__0_carry_i_1_n_0),
.I1(Lyy_2_bottom_right0__0_carry_i_10_n_0),
.I2(last_value[3]),
.I3(\left_reg_n_0_[2] ),
.I4(\top_reg_n_0_[2] ),
.I5(\corner_reg_n_0_[2] ),
.O(Lyy_2_bottom_right0__0_carry_i_5_n_0));
LUT6 #(
.INIT(64'h6996969669696996))
Lyy_2_bottom_right0__0_carry_i_6
(.I0(Lyy_2_bottom_right0__0_carry_i_2_n_0),
.I1(Lyy_2_bottom_right0__0_carry_i_9_n_0),
.I2(last_value[2]),
.I3(\left_reg_n_0_[1] ),
.I4(\top_reg_n_0_[1] ),
.I5(\corner_reg_n_0_[1] ),
.O(Lyy_2_bottom_right0__0_carry_i_6_n_0));
LUT6 #(
.INIT(64'hB44BB44BB44B4BB4))
Lyy_2_bottom_right0__0_carry_i_7
(.I0(\corner_reg_n_0_[0] ),
.I1(last_value[0]),
.I2(last_value[1]),
.I3(Lyy_2_bottom_right0__0_carry_i_11_n_0),
.I4(\left_reg_n_0_[0] ),
.I5(\top_reg_n_0_[0] ),
.O(Lyy_2_bottom_right0__0_carry_i_7_n_0));
LUT4 #(
.INIT(16'h6996))
Lyy_2_bottom_right0__0_carry_i_8
(.I0(\left_reg_n_0_[0] ),
.I1(\top_reg_n_0_[0] ),
.I2(\corner_reg_n_0_[0] ),
.I3(last_value[0]),
.O(Lyy_2_bottom_right0__0_carry_i_8_n_0));
LUT3 #(
.INIT(8'h69))
Lyy_2_bottom_right0__0_carry_i_9
(.I0(\corner_reg_n_0_[2] ),
.I1(\left_reg_n_0_[2] ),
.I2(\top_reg_n_0_[2] ),
.O(Lyy_2_bottom_right0__0_carry_i_9_n_0));
LUT6 #(
.INIT(64'h0000000000000080))
\Lyy_2_bottom_right[15]_i_1
(.I0(cycle[0]),
.I1(active),
.I2(rst),
.I3(\cycle_reg[1]_rep_n_0 ),
.I4(cycle[3]),
.I5(cycle[2]),
.O(y5));
FDRE #(
.INIT(1'b0))
\Lyy_2_bottom_right_reg[0]
(.C(clk_x16),
.CE(y5),
.D(Lyy_2_bottom_right01_out[0]),
.Q(Lyy_2_bottom_right[0]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_2_bottom_right_reg[10]
(.C(clk_x16),
.CE(y5),
.D(Lyy_2_bottom_right01_out[10]),
.Q(Lyy_2_bottom_right[10]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_2_bottom_right_reg[11]
(.C(clk_x16),
.CE(y5),
.D(Lyy_2_bottom_right01_out[11]),
.Q(Lyy_2_bottom_right[11]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_2_bottom_right_reg[12]
(.C(clk_x16),
.CE(y5),
.D(Lyy_2_bottom_right01_out[12]),
.Q(Lyy_2_bottom_right[12]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_2_bottom_right_reg[13]
(.C(clk_x16),
.CE(y5),
.D(Lyy_2_bottom_right01_out[13]),
.Q(Lyy_2_bottom_right[13]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_2_bottom_right_reg[14]
(.C(clk_x16),
.CE(y5),
.D(Lyy_2_bottom_right01_out[14]),
.Q(Lyy_2_bottom_right[14]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_2_bottom_right_reg[15]
(.C(clk_x16),
.CE(y5),
.D(Lyy_2_bottom_right01_out[15]),
.Q(Lyy_2_bottom_right[15]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_2_bottom_right_reg[1]
(.C(clk_x16),
.CE(y5),
.D(Lyy_2_bottom_right01_out[1]),
.Q(Lyy_2_bottom_right[1]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_2_bottom_right_reg[2]
(.C(clk_x16),
.CE(y5),
.D(Lyy_2_bottom_right01_out[2]),
.Q(Lyy_2_bottom_right[2]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_2_bottom_right_reg[3]
(.C(clk_x16),
.CE(y5),
.D(Lyy_2_bottom_right01_out[3]),
.Q(Lyy_2_bottom_right[3]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_2_bottom_right_reg[4]
(.C(clk_x16),
.CE(y5),
.D(Lyy_2_bottom_right01_out[4]),
.Q(Lyy_2_bottom_right[4]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_2_bottom_right_reg[5]
(.C(clk_x16),
.CE(y5),
.D(Lyy_2_bottom_right01_out[5]),
.Q(Lyy_2_bottom_right[5]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_2_bottom_right_reg[6]
(.C(clk_x16),
.CE(y5),
.D(Lyy_2_bottom_right01_out[6]),
.Q(Lyy_2_bottom_right[6]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_2_bottom_right_reg[7]
(.C(clk_x16),
.CE(y5),
.D(Lyy_2_bottom_right01_out[7]),
.Q(Lyy_2_bottom_right[7]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_2_bottom_right_reg[8]
(.C(clk_x16),
.CE(y5),
.D(Lyy_2_bottom_right01_out[8]),
.Q(Lyy_2_bottom_right[8]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_2_bottom_right_reg[9]
(.C(clk_x16),
.CE(y5),
.D(Lyy_2_bottom_right01_out[9]),
.Q(Lyy_2_bottom_right[9]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_2_reg[0]
(.C(clk_x16),
.CE(\Lyy_2[15]_i_1_n_0 ),
.D(Lyy_20[0]),
.Q(\Lyy_2_reg_n_0_[0] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_2_reg[10]
(.C(clk_x16),
.CE(\Lyy_2[15]_i_1_n_0 ),
.D(Lyy_20[10]),
.Q(\Lyy_2_reg_n_0_[10] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_2_reg[11]
(.C(clk_x16),
.CE(\Lyy_2[15]_i_1_n_0 ),
.D(Lyy_20[11]),
.Q(\Lyy_2_reg_n_0_[11] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_2_reg[12]
(.C(clk_x16),
.CE(\Lyy_2[15]_i_1_n_0 ),
.D(Lyy_20[12]),
.Q(\Lyy_2_reg_n_0_[12] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_2_reg[13]
(.C(clk_x16),
.CE(\Lyy_2[15]_i_1_n_0 ),
.D(Lyy_20[13]),
.Q(\Lyy_2_reg_n_0_[13] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_2_reg[14]
(.C(clk_x16),
.CE(\Lyy_2[15]_i_1_n_0 ),
.D(Lyy_20[14]),
.Q(\Lyy_2_reg_n_0_[14] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_2_reg[15]
(.C(clk_x16),
.CE(\Lyy_2[15]_i_1_n_0 ),
.D(Lyy_20[15]),
.Q(\Lyy_2_reg_n_0_[15] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_2_reg[1]
(.C(clk_x16),
.CE(\Lyy_2[15]_i_1_n_0 ),
.D(Lyy_20[1]),
.Q(\Lyy_2_reg_n_0_[1] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_2_reg[2]
(.C(clk_x16),
.CE(\Lyy_2[15]_i_1_n_0 ),
.D(Lyy_20[2]),
.Q(\Lyy_2_reg_n_0_[2] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_2_reg[3]
(.C(clk_x16),
.CE(\Lyy_2[15]_i_1_n_0 ),
.D(Lyy_20[3]),
.Q(\Lyy_2_reg_n_0_[3] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_2_reg[4]
(.C(clk_x16),
.CE(\Lyy_2[15]_i_1_n_0 ),
.D(Lyy_20[4]),
.Q(\Lyy_2_reg_n_0_[4] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_2_reg[5]
(.C(clk_x16),
.CE(\Lyy_2[15]_i_1_n_0 ),
.D(Lyy_20[5]),
.Q(\Lyy_2_reg_n_0_[5] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_2_reg[6]
(.C(clk_x16),
.CE(\Lyy_2[15]_i_1_n_0 ),
.D(Lyy_20[6]),
.Q(\Lyy_2_reg_n_0_[6] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_2_reg[7]
(.C(clk_x16),
.CE(\Lyy_2[15]_i_1_n_0 ),
.D(Lyy_20[7]),
.Q(\Lyy_2_reg_n_0_[7] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_2_reg[8]
(.C(clk_x16),
.CE(\Lyy_2[15]_i_1_n_0 ),
.D(Lyy_20[8]),
.Q(\Lyy_2_reg_n_0_[8] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_2_reg[9]
(.C(clk_x16),
.CE(\Lyy_2[15]_i_1_n_0 ),
.D(Lyy_20[9]),
.Q(\Lyy_2_reg_n_0_[9] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_2_top_left_reg[0]
(.C(clk_x16),
.CE(y1),
.D(bottom_left_1[0]),
.Q(Lyy_2_top_left[0]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_2_top_left_reg[10]
(.C(clk_x16),
.CE(y1),
.D(bottom_left_1[10]),
.Q(Lyy_2_top_left[10]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_2_top_left_reg[11]
(.C(clk_x16),
.CE(y1),
.D(bottom_left_1[11]),
.Q(Lyy_2_top_left[11]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_2_top_left_reg[12]
(.C(clk_x16),
.CE(y1),
.D(bottom_left_1[12]),
.Q(Lyy_2_top_left[12]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_2_top_left_reg[13]
(.C(clk_x16),
.CE(y1),
.D(bottom_left_1[13]),
.Q(Lyy_2_top_left[13]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_2_top_left_reg[14]
(.C(clk_x16),
.CE(y1),
.D(bottom_left_1[14]),
.Q(Lyy_2_top_left[14]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_2_top_left_reg[15]
(.C(clk_x16),
.CE(y1),
.D(bottom_left_1[15]),
.Q(Lyy_2_top_left[15]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_2_top_left_reg[1]
(.C(clk_x16),
.CE(y1),
.D(bottom_left_1[1]),
.Q(Lyy_2_top_left[1]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_2_top_left_reg[2]
(.C(clk_x16),
.CE(y1),
.D(bottom_left_1[2]),
.Q(Lyy_2_top_left[2]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_2_top_left_reg[3]
(.C(clk_x16),
.CE(y1),
.D(bottom_left_1[3]),
.Q(Lyy_2_top_left[3]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_2_top_left_reg[4]
(.C(clk_x16),
.CE(y1),
.D(bottom_left_1[4]),
.Q(Lyy_2_top_left[4]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_2_top_left_reg[5]
(.C(clk_x16),
.CE(y1),
.D(bottom_left_1[5]),
.Q(Lyy_2_top_left[5]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_2_top_left_reg[6]
(.C(clk_x16),
.CE(y1),
.D(bottom_left_1[6]),
.Q(Lyy_2_top_left[6]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_2_top_left_reg[7]
(.C(clk_x16),
.CE(y1),
.D(bottom_left_1[7]),
.Q(Lyy_2_top_left[7]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_2_top_left_reg[8]
(.C(clk_x16),
.CE(y1),
.D(bottom_left_1[8]),
.Q(Lyy_2_top_left[8]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_2_top_left_reg[9]
(.C(clk_x16),
.CE(y1),
.D(bottom_left_1[9]),
.Q(Lyy_2_top_left[9]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_2_top_right_reg[0]
(.C(clk_x16),
.CE(y1),
.D(\bottom_right_1_reg_n_0_[0] ),
.Q(Lyy_2_top_right[0]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_2_top_right_reg[10]
(.C(clk_x16),
.CE(y1),
.D(\bottom_right_1_reg_n_0_[10] ),
.Q(Lyy_2_top_right[10]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_2_top_right_reg[11]
(.C(clk_x16),
.CE(y1),
.D(\bottom_right_1_reg_n_0_[11] ),
.Q(Lyy_2_top_right[11]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_2_top_right_reg[12]
(.C(clk_x16),
.CE(y1),
.D(\bottom_right_1_reg_n_0_[12] ),
.Q(Lyy_2_top_right[12]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_2_top_right_reg[13]
(.C(clk_x16),
.CE(y1),
.D(\bottom_right_1_reg_n_0_[13] ),
.Q(Lyy_2_top_right[13]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_2_top_right_reg[14]
(.C(clk_x16),
.CE(y1),
.D(\bottom_right_1_reg_n_0_[14] ),
.Q(Lyy_2_top_right[14]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_2_top_right_reg[15]
(.C(clk_x16),
.CE(y1),
.D(\bottom_right_1_reg_n_0_[15] ),
.Q(Lyy_2_top_right[15]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_2_top_right_reg[1]
(.C(clk_x16),
.CE(y1),
.D(\bottom_right_1_reg_n_0_[1] ),
.Q(Lyy_2_top_right[1]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_2_top_right_reg[2]
(.C(clk_x16),
.CE(y1),
.D(\bottom_right_1_reg_n_0_[2] ),
.Q(Lyy_2_top_right[2]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_2_top_right_reg[3]
(.C(clk_x16),
.CE(y1),
.D(\bottom_right_1_reg_n_0_[3] ),
.Q(Lyy_2_top_right[3]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_2_top_right_reg[4]
(.C(clk_x16),
.CE(y1),
.D(\bottom_right_1_reg_n_0_[4] ),
.Q(Lyy_2_top_right[4]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_2_top_right_reg[5]
(.C(clk_x16),
.CE(y1),
.D(\bottom_right_1_reg_n_0_[5] ),
.Q(Lyy_2_top_right[5]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_2_top_right_reg[6]
(.C(clk_x16),
.CE(y1),
.D(\bottom_right_1_reg_n_0_[6] ),
.Q(Lyy_2_top_right[6]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_2_top_right_reg[7]
(.C(clk_x16),
.CE(y1),
.D(\bottom_right_1_reg_n_0_[7] ),
.Q(Lyy_2_top_right[7]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_2_top_right_reg[8]
(.C(clk_x16),
.CE(y1),
.D(\bottom_right_1_reg_n_0_[8] ),
.Q(Lyy_2_top_right[8]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_2_top_right_reg[9]
(.C(clk_x16),
.CE(y1),
.D(\bottom_right_1_reg_n_0_[9] ),
.Q(Lyy_2_top_right[9]),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair60" *)
LUT3 #(
.INIT(8'hB8))
\addr_0[0]_i_1
(.I0(\compute_addr_0_reg_n_0_[0] ),
.I1(\cycle_reg[0]_rep_n_0 ),
.I2(\compute_addr_2_reg_n_0_[0] ),
.O(\addr_0[0]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair53" *)
LUT3 #(
.INIT(8'hB8))
\addr_0[10]_i_1
(.I0(\compute_addr_0_reg_n_0_[10] ),
.I1(\cycle_reg[0]_rep_n_0 ),
.I2(\compute_addr_2_reg_n_0_[10] ),
.O(\addr_0[10]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair39" *)
LUT3 #(
.INIT(8'hB8))
\addr_0[11]_i_1
(.I0(\compute_addr_0_reg_n_0_[11] ),
.I1(\cycle_reg[0]_rep_n_0 ),
.I2(\compute_addr_2_reg_n_0_[11] ),
.O(\addr_0[11]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair37" *)
LUT3 #(
.INIT(8'hB8))
\addr_0[12]_i_1
(.I0(\compute_addr_0_reg_n_0_[12] ),
.I1(\cycle_reg[0]_rep_n_0 ),
.I2(\compute_addr_2_reg_n_0_[12] ),
.O(\addr_0[12]_i_1_n_0 ));
LUT6 #(
.INIT(64'h8888888888808888))
\addr_0[13]_i_1
(.I0(rst),
.I1(active),
.I2(cycle[3]),
.I3(\cycle_reg[0]_rep_n_0 ),
.I4(\cycle_reg[1]_rep_n_0 ),
.I5(cycle[2]),
.O(addr_0));
(* SOFT_HLUTNM = "soft_lutpair36" *)
LUT3 #(
.INIT(8'hB8))
\addr_0[13]_i_2
(.I0(\compute_addr_0_reg_n_0_[13] ),
.I1(\cycle_reg[0]_rep_n_0 ),
.I2(\compute_addr_2_reg_n_0_[13] ),
.O(\addr_0[13]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair56" *)
LUT3 #(
.INIT(8'hB8))
\addr_0[1]_i_1
(.I0(\compute_addr_0_reg_n_0_[1] ),
.I1(\cycle_reg[0]_rep_n_0 ),
.I2(\compute_addr_2_reg_n_0_[1] ),
.O(\addr_0[1]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair39" *)
LUT3 #(
.INIT(8'hB8))
\addr_0[2]_i_1
(.I0(\compute_addr_0_reg_n_0_[2] ),
.I1(\cycle_reg[0]_rep_n_0 ),
.I2(\compute_addr_2_reg_n_0_[2] ),
.O(\addr_0[2]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair36" *)
LUT3 #(
.INIT(8'hB8))
\addr_0[3]_i_1
(.I0(\compute_addr_0_reg_n_0_[3] ),
.I1(\cycle_reg[0]_rep_n_0 ),
.I2(\compute_addr_2_reg_n_0_[3] ),
.O(\addr_0[3]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair37" *)
LUT3 #(
.INIT(8'hB8))
\addr_0[4]_i_1
(.I0(\compute_addr_0_reg_n_0_[4] ),
.I1(\cycle_reg[0]_rep_n_0 ),
.I2(\compute_addr_2_reg_n_0_[4] ),
.O(\addr_0[4]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair53" *)
LUT3 #(
.INIT(8'hB8))
\addr_0[5]_i_1
(.I0(\compute_addr_0_reg_n_0_[5] ),
.I1(\cycle_reg[0]_rep_n_0 ),
.I2(\compute_addr_2_reg_n_0_[5] ),
.O(\addr_0[5]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair60" *)
LUT3 #(
.INIT(8'hB8))
\addr_0[6]_i_1
(.I0(\compute_addr_0_reg_n_0_[6] ),
.I1(\cycle_reg[0]_rep_n_0 ),
.I2(\compute_addr_2_reg_n_0_[6] ),
.O(\addr_0[6]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair59" *)
LUT3 #(
.INIT(8'hB8))
\addr_0[7]_i_1
(.I0(\compute_addr_0_reg_n_0_[7] ),
.I1(\cycle_reg[0]_rep_n_0 ),
.I2(\compute_addr_2_reg_n_0_[7] ),
.O(\addr_0[7]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair59" *)
LUT3 #(
.INIT(8'hB8))
\addr_0[8]_i_1
(.I0(\compute_addr_0_reg_n_0_[8] ),
.I1(\cycle_reg[0]_rep_n_0 ),
.I2(\compute_addr_2_reg_n_0_[8] ),
.O(\addr_0[8]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair56" *)
LUT3 #(
.INIT(8'hB8))
\addr_0[9]_i_1
(.I0(\compute_addr_0_reg_n_0_[9] ),
.I1(\cycle_reg[0]_rep_n_0 ),
.I2(\compute_addr_2_reg_n_0_[9] ),
.O(\addr_0[9]_i_1_n_0 ));
FDRE \addr_0_reg[0]
(.C(clk_x16),
.CE(addr_0),
.D(\addr_0[0]_i_1_n_0 ),
.Q(\addr_0_reg_n_0_[0] ),
.R(1'b0));
FDRE \addr_0_reg[10]
(.C(clk_x16),
.CE(addr_0),
.D(\addr_0[10]_i_1_n_0 ),
.Q(\addr_0_reg_n_0_[10] ),
.R(1'b0));
FDRE \addr_0_reg[11]
(.C(clk_x16),
.CE(addr_0),
.D(\addr_0[11]_i_1_n_0 ),
.Q(\addr_0_reg_n_0_[11] ),
.R(1'b0));
FDRE \addr_0_reg[12]
(.C(clk_x16),
.CE(addr_0),
.D(\addr_0[12]_i_1_n_0 ),
.Q(\addr_0_reg_n_0_[12] ),
.R(1'b0));
FDRE \addr_0_reg[13]
(.C(clk_x16),
.CE(addr_0),
.D(\addr_0[13]_i_2_n_0 ),
.Q(\addr_0_reg_n_0_[13] ),
.R(1'b0));
FDRE \addr_0_reg[1]
(.C(clk_x16),
.CE(addr_0),
.D(\addr_0[1]_i_1_n_0 ),
.Q(\addr_0_reg_n_0_[1] ),
.R(1'b0));
FDRE \addr_0_reg[2]
(.C(clk_x16),
.CE(addr_0),
.D(\addr_0[2]_i_1_n_0 ),
.Q(\addr_0_reg_n_0_[2] ),
.R(1'b0));
FDRE \addr_0_reg[3]
(.C(clk_x16),
.CE(addr_0),
.D(\addr_0[3]_i_1_n_0 ),
.Q(\addr_0_reg_n_0_[3] ),
.R(1'b0));
FDRE \addr_0_reg[4]
(.C(clk_x16),
.CE(addr_0),
.D(\addr_0[4]_i_1_n_0 ),
.Q(\addr_0_reg_n_0_[4] ),
.R(1'b0));
FDRE \addr_0_reg[5]
(.C(clk_x16),
.CE(addr_0),
.D(\addr_0[5]_i_1_n_0 ),
.Q(\addr_0_reg_n_0_[5] ),
.R(1'b0));
FDRE \addr_0_reg[6]
(.C(clk_x16),
.CE(addr_0),
.D(\addr_0[6]_i_1_n_0 ),
.Q(\addr_0_reg_n_0_[6] ),
.R(1'b0));
FDRE \addr_0_reg[7]
(.C(clk_x16),
.CE(addr_0),
.D(\addr_0[7]_i_1_n_0 ),
.Q(\addr_0_reg_n_0_[7] ),
.R(1'b0));
FDRE \addr_0_reg[8]
(.C(clk_x16),
.CE(addr_0),
.D(\addr_0[8]_i_1_n_0 ),
.Q(\addr_0_reg_n_0_[8] ),
.R(1'b0));
FDRE \addr_0_reg[9]
(.C(clk_x16),
.CE(addr_0),
.D(\addr_0[9]_i_1_n_0 ),
.Q(\addr_0_reg_n_0_[9] ),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair63" *)
LUT3 #(
.INIT(8'hB8))
\addr_1[0]_i_1
(.I0(compute_addr_1[0]),
.I1(\cycle_reg[0]_rep_n_0 ),
.I2(compute_addr_3[0]),
.O(\addr_1[0]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair62" *)
LUT3 #(
.INIT(8'hB8))
\addr_1[10]_i_1
(.I0(compute_addr_1[10]),
.I1(\cycle_reg[0]_rep_n_0 ),
.I2(compute_addr_3[10]),
.O(\addr_1[10]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair61" *)
LUT3 #(
.INIT(8'hB8))
\addr_1[11]_i_1
(.I0(compute_addr_1[11]),
.I1(\cycle_reg[0]_rep_n_0 ),
.I2(compute_addr_3[11]),
.O(\addr_1[11]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair62" *)
LUT3 #(
.INIT(8'hB8))
\addr_1[12]_i_1
(.I0(compute_addr_1[12]),
.I1(\cycle_reg[0]_rep_n_0 ),
.I2(compute_addr_3[12]),
.O(\addr_1[12]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair61" *)
LUT3 #(
.INIT(8'hB8))
\addr_1[13]_i_1
(.I0(compute_addr_1[13]),
.I1(\cycle_reg[0]_rep_n_0 ),
.I2(compute_addr_3[13]),
.O(\addr_1[13]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair64" *)
LUT3 #(
.INIT(8'hB8))
\addr_1[1]_i_1
(.I0(compute_addr_1[1]),
.I1(\cycle_reg[0]_rep_n_0 ),
.I2(compute_addr_3[1]),
.O(\addr_1[1]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair65" *)
LUT3 #(
.INIT(8'hB8))
\addr_1[2]_i_1
(.I0(compute_addr_1[2]),
.I1(\cycle_reg[0]_rep_n_0 ),
.I2(compute_addr_3[2]),
.O(\addr_1[2]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair69" *)
LUT3 #(
.INIT(8'hB8))
\addr_1[3]_i_1
(.I0(compute_addr_1[3]),
.I1(\cycle_reg[0]_rep_n_0 ),
.I2(compute_addr_3[3]),
.O(\addr_1[3]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair69" *)
LUT3 #(
.INIT(8'hB8))
\addr_1[4]_i_1
(.I0(compute_addr_1[4]),
.I1(\cycle_reg[0]_rep_n_0 ),
.I2(compute_addr_3[4]),
.O(\addr_1[4]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair68" *)
LUT3 #(
.INIT(8'hB8))
\addr_1[5]_i_1
(.I0(compute_addr_1[5]),
.I1(\cycle_reg[0]_rep_n_0 ),
.I2(compute_addr_3[5]),
.O(\addr_1[5]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair68" *)
LUT3 #(
.INIT(8'hB8))
\addr_1[6]_i_1
(.I0(compute_addr_1[6]),
.I1(\cycle_reg[0]_rep_n_0 ),
.I2(compute_addr_3[6]),
.O(\addr_1[6]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair65" *)
LUT3 #(
.INIT(8'hB8))
\addr_1[7]_i_1
(.I0(compute_addr_1[7]),
.I1(\cycle_reg[0]_rep_n_0 ),
.I2(compute_addr_3[7]),
.O(\addr_1[7]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair64" *)
LUT3 #(
.INIT(8'hB8))
\addr_1[8]_i_1
(.I0(compute_addr_1[8]),
.I1(\cycle_reg[0]_rep_n_0 ),
.I2(compute_addr_3[8]),
.O(\addr_1[8]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair63" *)
LUT3 #(
.INIT(8'hB8))
\addr_1[9]_i_1
(.I0(compute_addr_1[9]),
.I1(\cycle_reg[0]_rep_n_0 ),
.I2(compute_addr_3[9]),
.O(\addr_1[9]_i_1_n_0 ));
FDRE \addr_1_reg[0]
(.C(clk_x16),
.CE(addr_0),
.D(\addr_1[0]_i_1_n_0 ),
.Q(addr_1[0]),
.R(1'b0));
FDRE \addr_1_reg[10]
(.C(clk_x16),
.CE(addr_0),
.D(\addr_1[10]_i_1_n_0 ),
.Q(addr_1[10]),
.R(1'b0));
FDRE \addr_1_reg[11]
(.C(clk_x16),
.CE(addr_0),
.D(\addr_1[11]_i_1_n_0 ),
.Q(addr_1[11]),
.R(1'b0));
FDRE \addr_1_reg[12]
(.C(clk_x16),
.CE(addr_0),
.D(\addr_1[12]_i_1_n_0 ),
.Q(addr_1[12]),
.R(1'b0));
FDRE \addr_1_reg[13]
(.C(clk_x16),
.CE(addr_0),
.D(\addr_1[13]_i_1_n_0 ),
.Q(addr_1[13]),
.R(1'b0));
FDRE \addr_1_reg[1]
(.C(clk_x16),
.CE(addr_0),
.D(\addr_1[1]_i_1_n_0 ),
.Q(addr_1[1]),
.R(1'b0));
FDRE \addr_1_reg[2]
(.C(clk_x16),
.CE(addr_0),
.D(\addr_1[2]_i_1_n_0 ),
.Q(addr_1[2]),
.R(1'b0));
FDRE \addr_1_reg[3]
(.C(clk_x16),
.CE(addr_0),
.D(\addr_1[3]_i_1_n_0 ),
.Q(addr_1[3]),
.R(1'b0));
FDRE \addr_1_reg[4]
(.C(clk_x16),
.CE(addr_0),
.D(\addr_1[4]_i_1_n_0 ),
.Q(addr_1[4]),
.R(1'b0));
FDRE \addr_1_reg[5]
(.C(clk_x16),
.CE(addr_0),
.D(\addr_1[5]_i_1_n_0 ),
.Q(addr_1[5]),
.R(1'b0));
FDRE \addr_1_reg[6]
(.C(clk_x16),
.CE(addr_0),
.D(\addr_1[6]_i_1_n_0 ),
.Q(addr_1[6]),
.R(1'b0));
FDRE \addr_1_reg[7]
(.C(clk_x16),
.CE(addr_0),
.D(\addr_1[7]_i_1_n_0 ),
.Q(addr_1[7]),
.R(1'b0));
FDRE \addr_1_reg[8]
(.C(clk_x16),
.CE(addr_0),
.D(\addr_1[8]_i_1_n_0 ),
.Q(addr_1[8]),
.R(1'b0));
FDRE \addr_1_reg[9]
(.C(clk_x16),
.CE(addr_0),
.D(\addr_1[9]_i_1_n_0 ),
.Q(addr_1[9]),
.R(1'b0));
LUT6 #(
.INIT(64'h8800880000000800))
\bottom_left_0[15]_i_1
(.I0(rst),
.I1(active),
.I2(cycle[2]),
.I3(\cycle_reg[0]_rep_n_0 ),
.I4(cycle[3]),
.I5(\cycle_reg[1]_rep_n_0 ),
.O(bottom_left_0));
FDRE #(
.INIT(1'b0))
\bottom_left_0_reg[0]
(.C(clk_x16),
.CE(bottom_left_0),
.D(dout_0[0]),
.Q(\bottom_left_0_reg_n_0_[0] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\bottom_left_0_reg[10]
(.C(clk_x16),
.CE(bottom_left_0),
.D(dout_0[10]),
.Q(\bottom_left_0_reg_n_0_[10] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\bottom_left_0_reg[11]
(.C(clk_x16),
.CE(bottom_left_0),
.D(dout_0[11]),
.Q(\bottom_left_0_reg_n_0_[11] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\bottom_left_0_reg[12]
(.C(clk_x16),
.CE(bottom_left_0),
.D(dout_0[12]),
.Q(\bottom_left_0_reg_n_0_[12] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\bottom_left_0_reg[13]
(.C(clk_x16),
.CE(bottom_left_0),
.D(dout_0[13]),
.Q(\bottom_left_0_reg_n_0_[13] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\bottom_left_0_reg[14]
(.C(clk_x16),
.CE(bottom_left_0),
.D(dout_0[14]),
.Q(\bottom_left_0_reg_n_0_[14] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\bottom_left_0_reg[15]
(.C(clk_x16),
.CE(bottom_left_0),
.D(dout_0[15]),
.Q(\bottom_left_0_reg_n_0_[15] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\bottom_left_0_reg[1]
(.C(clk_x16),
.CE(bottom_left_0),
.D(dout_0[1]),
.Q(\bottom_left_0_reg_n_0_[1] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\bottom_left_0_reg[2]
(.C(clk_x16),
.CE(bottom_left_0),
.D(dout_0[2]),
.Q(\bottom_left_0_reg_n_0_[2] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\bottom_left_0_reg[3]
(.C(clk_x16),
.CE(bottom_left_0),
.D(dout_0[3]),
.Q(\bottom_left_0_reg_n_0_[3] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\bottom_left_0_reg[4]
(.C(clk_x16),
.CE(bottom_left_0),
.D(dout_0[4]),
.Q(\bottom_left_0_reg_n_0_[4] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\bottom_left_0_reg[5]
(.C(clk_x16),
.CE(bottom_left_0),
.D(dout_0[5]),
.Q(\bottom_left_0_reg_n_0_[5] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\bottom_left_0_reg[6]
(.C(clk_x16),
.CE(bottom_left_0),
.D(dout_0[6]),
.Q(\bottom_left_0_reg_n_0_[6] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\bottom_left_0_reg[7]
(.C(clk_x16),
.CE(bottom_left_0),
.D(dout_0[7]),
.Q(\bottom_left_0_reg_n_0_[7] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\bottom_left_0_reg[8]
(.C(clk_x16),
.CE(bottom_left_0),
.D(dout_0[8]),
.Q(\bottom_left_0_reg_n_0_[8] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\bottom_left_0_reg[9]
(.C(clk_x16),
.CE(bottom_left_0),
.D(dout_0[9]),
.Q(\bottom_left_0_reg_n_0_[9] ),
.R(1'b0));
LUT5 #(
.INIT(32'h40000040))
\bottom_left_1[15]_i_1
(.I0(\cycle_reg[1]_rep_n_0 ),
.I1(active),
.I2(rst),
.I3(\cycle_reg[0]_rep_n_0 ),
.I4(cycle[3]),
.O(top_right_1));
FDRE #(
.INIT(1'b0))
\bottom_left_1_reg[0]
(.C(clk_x16),
.CE(top_right_1),
.D(dout_0[0]),
.Q(bottom_left_1[0]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\bottom_left_1_reg[10]
(.C(clk_x16),
.CE(top_right_1),
.D(dout_0[10]),
.Q(bottom_left_1[10]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\bottom_left_1_reg[11]
(.C(clk_x16),
.CE(top_right_1),
.D(dout_0[11]),
.Q(bottom_left_1[11]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\bottom_left_1_reg[12]
(.C(clk_x16),
.CE(top_right_1),
.D(dout_0[12]),
.Q(bottom_left_1[12]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\bottom_left_1_reg[13]
(.C(clk_x16),
.CE(top_right_1),
.D(dout_0[13]),
.Q(bottom_left_1[13]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\bottom_left_1_reg[14]
(.C(clk_x16),
.CE(top_right_1),
.D(dout_0[14]),
.Q(bottom_left_1[14]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\bottom_left_1_reg[15]
(.C(clk_x16),
.CE(top_right_1),
.D(dout_0[15]),
.Q(bottom_left_1[15]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\bottom_left_1_reg[1]
(.C(clk_x16),
.CE(top_right_1),
.D(dout_0[1]),
.Q(bottom_left_1[1]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\bottom_left_1_reg[2]
(.C(clk_x16),
.CE(top_right_1),
.D(dout_0[2]),
.Q(bottom_left_1[2]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\bottom_left_1_reg[3]
(.C(clk_x16),
.CE(top_right_1),
.D(dout_0[3]),
.Q(bottom_left_1[3]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\bottom_left_1_reg[4]
(.C(clk_x16),
.CE(top_right_1),
.D(dout_0[4]),
.Q(bottom_left_1[4]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\bottom_left_1_reg[5]
(.C(clk_x16),
.CE(top_right_1),
.D(dout_0[5]),
.Q(bottom_left_1[5]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\bottom_left_1_reg[6]
(.C(clk_x16),
.CE(top_right_1),
.D(dout_0[6]),
.Q(bottom_left_1[6]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\bottom_left_1_reg[7]
(.C(clk_x16),
.CE(top_right_1),
.D(dout_0[7]),
.Q(bottom_left_1[7]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\bottom_left_1_reg[8]
(.C(clk_x16),
.CE(top_right_1),
.D(dout_0[8]),
.Q(bottom_left_1[8]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\bottom_left_1_reg[9]
(.C(clk_x16),
.CE(top_right_1),
.D(dout_0[9]),
.Q(bottom_left_1[9]),
.R(1'b0));
LUT6 #(
.INIT(64'hFFF0CC880F00CC88))
\bottom_right_0[0]_i_1
(.I0(\bottom_right_0[15]_i_3_n_0 ),
.I1(\bottom_right_0[0]_i_2_n_0 ),
.I2(\bottom_right_0[15]_i_5_n_0 ),
.I3(dout_0[0]),
.I4(cycle[3]),
.I5(\cache_reg[8]_1 [0]),
.O(p_0_out[0]));
(* SOFT_HLUTNM = "soft_lutpair12" *)
LUT5 #(
.INIT(32'hFFE2FFFF))
\bottom_right_0[0]_i_2
(.I0(bottom_left_1[0]),
.I1(\cycle_reg[1]_rep_n_0 ),
.I2(dout_1[0]),
.I3(cycle[2]),
.I4(cycle[0]),
.O(\bottom_right_0[0]_i_2_n_0 ));
LUT6 #(
.INIT(64'hFFF0CC880F00CC88))
\bottom_right_0[10]_i_1
(.I0(\bottom_right_0[15]_i_3_n_0 ),
.I1(\bottom_right_0[10]_i_2_n_0 ),
.I2(\bottom_right_0[15]_i_5_n_0 ),
.I3(dout_0[10]),
.I4(cycle[3]),
.I5(\cache_reg[8]_1 [10]),
.O(p_0_out[10]));
LUT5 #(
.INIT(32'hFFE2FFFF))
\bottom_right_0[10]_i_2
(.I0(bottom_left_1[10]),
.I1(\cycle_reg[1]_rep_n_0 ),
.I2(dout_1[10]),
.I3(cycle[2]),
.I4(\cycle_reg[0]_rep_n_0 ),
.O(\bottom_right_0[10]_i_2_n_0 ));
LUT6 #(
.INIT(64'hFFF0CC880F00CC88))
\bottom_right_0[11]_i_1
(.I0(\bottom_right_0[15]_i_3_n_0 ),
.I1(\bottom_right_0[11]_i_2_n_0 ),
.I2(\bottom_right_0[15]_i_5_n_0 ),
.I3(dout_0[11]),
.I4(cycle[3]),
.I5(\cache_reg[8]_1 [11]),
.O(p_0_out[11]));
LUT5 #(
.INIT(32'hFFE2FFFF))
\bottom_right_0[11]_i_2
(.I0(bottom_left_1[11]),
.I1(\cycle_reg[1]_rep_n_0 ),
.I2(dout_1[11]),
.I3(cycle[2]),
.I4(\cycle_reg[0]_rep_n_0 ),
.O(\bottom_right_0[11]_i_2_n_0 ));
LUT6 #(
.INIT(64'hFFF0CC880F00CC88))
\bottom_right_0[12]_i_1
(.I0(\bottom_right_0[15]_i_3_n_0 ),
.I1(\bottom_right_0[12]_i_2_n_0 ),
.I2(\bottom_right_0[15]_i_5_n_0 ),
.I3(dout_0[12]),
.I4(cycle[3]),
.I5(\cache_reg[8]_1 [12]),
.O(p_0_out[12]));
LUT5 #(
.INIT(32'hFFE2FFFF))
\bottom_right_0[12]_i_2
(.I0(bottom_left_1[12]),
.I1(\cycle_reg[1]_rep_n_0 ),
.I2(dout_1[12]),
.I3(cycle[2]),
.I4(\cycle_reg[0]_rep_n_0 ),
.O(\bottom_right_0[12]_i_2_n_0 ));
LUT6 #(
.INIT(64'hFFF0CC880F00CC88))
\bottom_right_0[13]_i_1
(.I0(\bottom_right_0[15]_i_3_n_0 ),
.I1(\bottom_right_0[13]_i_2_n_0 ),
.I2(\bottom_right_0[15]_i_5_n_0 ),
.I3(dout_0[13]),
.I4(cycle[3]),
.I5(\cache_reg[8]_1 [13]),
.O(p_0_out[13]));
LUT5 #(
.INIT(32'hFFE2FFFF))
\bottom_right_0[13]_i_2
(.I0(bottom_left_1[13]),
.I1(\cycle_reg[1]_rep_n_0 ),
.I2(dout_1[13]),
.I3(cycle[2]),
.I4(\cycle_reg[0]_rep_n_0 ),
.O(\bottom_right_0[13]_i_2_n_0 ));
LUT6 #(
.INIT(64'hFFF0CC880F00CC88))
\bottom_right_0[14]_i_1
(.I0(\bottom_right_0[15]_i_3_n_0 ),
.I1(\bottom_right_0[14]_i_2_n_0 ),
.I2(\bottom_right_0[15]_i_5_n_0 ),
.I3(dout_0[14]),
.I4(cycle[3]),
.I5(\cache_reg[8]_1 [14]),
.O(p_0_out[14]));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT5 #(
.INIT(32'hFFE2FFFF))
\bottom_right_0[14]_i_2
(.I0(bottom_left_1[14]),
.I1(\cycle_reg[1]_rep_n_0 ),
.I2(dout_1[14]),
.I3(cycle[2]),
.I4(\cycle_reg[0]_rep_n_0 ),
.O(\bottom_right_0[14]_i_2_n_0 ));
LUT6 #(
.INIT(64'h444A000000000000))
\bottom_right_0[15]_i_1
(.I0(cycle[0]),
.I1(\cycle_reg[1]_rep_n_0 ),
.I2(cycle[2]),
.I3(cycle[3]),
.I4(rst),
.I5(active),
.O(\bottom_right_0[15]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFF0CC880F00CC88))
\bottom_right_0[15]_i_2
(.I0(\bottom_right_0[15]_i_3_n_0 ),
.I1(\bottom_right_0[15]_i_4_n_0 ),
.I2(\bottom_right_0[15]_i_5_n_0 ),
.I3(dout_0[15]),
.I4(cycle[3]),
.I5(\cache_reg[8]_1 [15]),
.O(p_0_out[15]));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT2 #(
.INIT(4'h2))
\bottom_right_0[15]_i_3
(.I0(\cycle_reg[0]_rep_n_0 ),
.I1(cycle[2]),
.O(\bottom_right_0[15]_i_3_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT5 #(
.INIT(32'hFFE2FFFF))
\bottom_right_0[15]_i_4
(.I0(bottom_left_1[15]),
.I1(\cycle_reg[1]_rep_n_0 ),
.I2(dout_1[15]),
.I3(cycle[2]),
.I4(\cycle_reg[0]_rep_n_0 ),
.O(\bottom_right_0[15]_i_4_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair12" *)
LUT3 #(
.INIT(8'h04))
\bottom_right_0[15]_i_5
(.I0(cycle[2]),
.I1(\cycle_reg[1]_rep_n_0 ),
.I2(cycle[0]),
.O(\bottom_right_0[15]_i_5_n_0 ));
LUT6 #(
.INIT(64'hFFF0CC880F00CC88))
\bottom_right_0[1]_i_1
(.I0(\bottom_right_0[15]_i_3_n_0 ),
.I1(\bottom_right_0[1]_i_2_n_0 ),
.I2(\bottom_right_0[15]_i_5_n_0 ),
.I3(dout_0[1]),
.I4(cycle[3]),
.I5(\cache_reg[8]_1 [1]),
.O(p_0_out[1]));
LUT5 #(
.INIT(32'hFFE2FFFF))
\bottom_right_0[1]_i_2
(.I0(bottom_left_1[1]),
.I1(\cycle_reg[1]_rep_n_0 ),
.I2(dout_1[1]),
.I3(cycle[2]),
.I4(cycle[0]),
.O(\bottom_right_0[1]_i_2_n_0 ));
LUT6 #(
.INIT(64'hFFF0CC880F00CC88))
\bottom_right_0[2]_i_1
(.I0(\bottom_right_0[15]_i_3_n_0 ),
.I1(\bottom_right_0[2]_i_2_n_0 ),
.I2(\bottom_right_0[15]_i_5_n_0 ),
.I3(dout_0[2]),
.I4(cycle[3]),
.I5(\cache_reg[8]_1 [2]),
.O(p_0_out[2]));
LUT5 #(
.INIT(32'hFFE2FFFF))
\bottom_right_0[2]_i_2
(.I0(bottom_left_1[2]),
.I1(\cycle_reg[1]_rep_n_0 ),
.I2(dout_1[2]),
.I3(cycle[2]),
.I4(cycle[0]),
.O(\bottom_right_0[2]_i_2_n_0 ));
LUT6 #(
.INIT(64'hFFF0CC880F00CC88))
\bottom_right_0[3]_i_1
(.I0(\bottom_right_0[15]_i_3_n_0 ),
.I1(\bottom_right_0[3]_i_2_n_0 ),
.I2(\bottom_right_0[15]_i_5_n_0 ),
.I3(dout_0[3]),
.I4(cycle[3]),
.I5(\cache_reg[8]_1 [3]),
.O(p_0_out[3]));
LUT5 #(
.INIT(32'hFFE2FFFF))
\bottom_right_0[3]_i_2
(.I0(bottom_left_1[3]),
.I1(\cycle_reg[1]_rep_n_0 ),
.I2(dout_1[3]),
.I3(cycle[2]),
.I4(\cycle_reg[0]_rep_n_0 ),
.O(\bottom_right_0[3]_i_2_n_0 ));
LUT6 #(
.INIT(64'hFFF0CC880F00CC88))
\bottom_right_0[4]_i_1
(.I0(\bottom_right_0[15]_i_3_n_0 ),
.I1(\bottom_right_0[4]_i_2_n_0 ),
.I2(\bottom_right_0[15]_i_5_n_0 ),
.I3(dout_0[4]),
.I4(cycle[3]),
.I5(\cache_reg[8]_1 [4]),
.O(p_0_out[4]));
LUT5 #(
.INIT(32'hFFE2FFFF))
\bottom_right_0[4]_i_2
(.I0(bottom_left_1[4]),
.I1(\cycle_reg[1]_rep_n_0 ),
.I2(dout_1[4]),
.I3(cycle[2]),
.I4(\cycle_reg[0]_rep_n_0 ),
.O(\bottom_right_0[4]_i_2_n_0 ));
LUT6 #(
.INIT(64'hFFF0CC880F00CC88))
\bottom_right_0[5]_i_1
(.I0(\bottom_right_0[15]_i_3_n_0 ),
.I1(\bottom_right_0[5]_i_2_n_0 ),
.I2(\bottom_right_0[15]_i_5_n_0 ),
.I3(dout_0[5]),
.I4(cycle[3]),
.I5(\cache_reg[8]_1 [5]),
.O(p_0_out[5]));
LUT5 #(
.INIT(32'hFFE2FFFF))
\bottom_right_0[5]_i_2
(.I0(bottom_left_1[5]),
.I1(\cycle_reg[1]_rep_n_0 ),
.I2(dout_1[5]),
.I3(cycle[2]),
.I4(\cycle_reg[0]_rep_n_0 ),
.O(\bottom_right_0[5]_i_2_n_0 ));
LUT6 #(
.INIT(64'hFFF0CC880F00CC88))
\bottom_right_0[6]_i_1
(.I0(\bottom_right_0[15]_i_3_n_0 ),
.I1(\bottom_right_0[6]_i_2_n_0 ),
.I2(\bottom_right_0[15]_i_5_n_0 ),
.I3(dout_0[6]),
.I4(cycle[3]),
.I5(\cache_reg[8]_1 [6]),
.O(p_0_out[6]));
LUT5 #(
.INIT(32'hFFE2FFFF))
\bottom_right_0[6]_i_2
(.I0(bottom_left_1[6]),
.I1(\cycle_reg[1]_rep_n_0 ),
.I2(dout_1[6]),
.I3(cycle[2]),
.I4(\cycle_reg[0]_rep_n_0 ),
.O(\bottom_right_0[6]_i_2_n_0 ));
LUT6 #(
.INIT(64'hFFF0CC880F00CC88))
\bottom_right_0[7]_i_1
(.I0(\bottom_right_0[15]_i_3_n_0 ),
.I1(\bottom_right_0[7]_i_2_n_0 ),
.I2(\bottom_right_0[15]_i_5_n_0 ),
.I3(dout_0[7]),
.I4(cycle[3]),
.I5(\cache_reg[8]_1 [7]),
.O(p_0_out[7]));
LUT5 #(
.INIT(32'hFFE2FFFF))
\bottom_right_0[7]_i_2
(.I0(bottom_left_1[7]),
.I1(\cycle_reg[1]_rep_n_0 ),
.I2(dout_1[7]),
.I3(cycle[2]),
.I4(\cycle_reg[0]_rep_n_0 ),
.O(\bottom_right_0[7]_i_2_n_0 ));
LUT6 #(
.INIT(64'hFFF0CC880F00CC88))
\bottom_right_0[8]_i_1
(.I0(\bottom_right_0[15]_i_3_n_0 ),
.I1(\bottom_right_0[8]_i_2_n_0 ),
.I2(\bottom_right_0[15]_i_5_n_0 ),
.I3(dout_0[8]),
.I4(cycle[3]),
.I5(\cache_reg[8]_1 [8]),
.O(p_0_out[8]));
LUT5 #(
.INIT(32'hFFE2FFFF))
\bottom_right_0[8]_i_2
(.I0(bottom_left_1[8]),
.I1(\cycle_reg[1]_rep_n_0 ),
.I2(dout_1[8]),
.I3(cycle[2]),
.I4(\cycle_reg[0]_rep_n_0 ),
.O(\bottom_right_0[8]_i_2_n_0 ));
LUT6 #(
.INIT(64'hFFF0CC880F00CC88))
\bottom_right_0[9]_i_1
(.I0(\bottom_right_0[15]_i_3_n_0 ),
.I1(\bottom_right_0[9]_i_2_n_0 ),
.I2(\bottom_right_0[15]_i_5_n_0 ),
.I3(dout_0[9]),
.I4(cycle[3]),
.I5(\cache_reg[8]_1 [9]),
.O(p_0_out[9]));
LUT5 #(
.INIT(32'hFFE2FFFF))
\bottom_right_0[9]_i_2
(.I0(bottom_left_1[9]),
.I1(\cycle_reg[1]_rep_n_0 ),
.I2(dout_1[9]),
.I3(cycle[2]),
.I4(\cycle_reg[0]_rep_n_0 ),
.O(\bottom_right_0[9]_i_2_n_0 ));
FDRE #(
.INIT(1'b0))
\bottom_right_0_reg[0]
(.C(clk_x16),
.CE(\bottom_right_0[15]_i_1_n_0 ),
.D(p_0_out[0]),
.Q(\bottom_right_0_reg_n_0_[0] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\bottom_right_0_reg[10]
(.C(clk_x16),
.CE(\bottom_right_0[15]_i_1_n_0 ),
.D(p_0_out[10]),
.Q(\bottom_right_0_reg_n_0_[10] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\bottom_right_0_reg[11]
(.C(clk_x16),
.CE(\bottom_right_0[15]_i_1_n_0 ),
.D(p_0_out[11]),
.Q(\bottom_right_0_reg_n_0_[11] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\bottom_right_0_reg[12]
(.C(clk_x16),
.CE(\bottom_right_0[15]_i_1_n_0 ),
.D(p_0_out[12]),
.Q(\bottom_right_0_reg_n_0_[12] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\bottom_right_0_reg[13]
(.C(clk_x16),
.CE(\bottom_right_0[15]_i_1_n_0 ),
.D(p_0_out[13]),
.Q(\bottom_right_0_reg_n_0_[13] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\bottom_right_0_reg[14]
(.C(clk_x16),
.CE(\bottom_right_0[15]_i_1_n_0 ),
.D(p_0_out[14]),
.Q(\bottom_right_0_reg_n_0_[14] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\bottom_right_0_reg[15]
(.C(clk_x16),
.CE(\bottom_right_0[15]_i_1_n_0 ),
.D(p_0_out[15]),
.Q(\bottom_right_0_reg_n_0_[15] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\bottom_right_0_reg[1]
(.C(clk_x16),
.CE(\bottom_right_0[15]_i_1_n_0 ),
.D(p_0_out[1]),
.Q(\bottom_right_0_reg_n_0_[1] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\bottom_right_0_reg[2]
(.C(clk_x16),
.CE(\bottom_right_0[15]_i_1_n_0 ),
.D(p_0_out[2]),
.Q(\bottom_right_0_reg_n_0_[2] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\bottom_right_0_reg[3]
(.C(clk_x16),
.CE(\bottom_right_0[15]_i_1_n_0 ),
.D(p_0_out[3]),
.Q(\bottom_right_0_reg_n_0_[3] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\bottom_right_0_reg[4]
(.C(clk_x16),
.CE(\bottom_right_0[15]_i_1_n_0 ),
.D(p_0_out[4]),
.Q(\bottom_right_0_reg_n_0_[4] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\bottom_right_0_reg[5]
(.C(clk_x16),
.CE(\bottom_right_0[15]_i_1_n_0 ),
.D(p_0_out[5]),
.Q(\bottom_right_0_reg_n_0_[5] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\bottom_right_0_reg[6]
(.C(clk_x16),
.CE(\bottom_right_0[15]_i_1_n_0 ),
.D(p_0_out[6]),
.Q(\bottom_right_0_reg_n_0_[6] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\bottom_right_0_reg[7]
(.C(clk_x16),
.CE(\bottom_right_0[15]_i_1_n_0 ),
.D(p_0_out[7]),
.Q(\bottom_right_0_reg_n_0_[7] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\bottom_right_0_reg[8]
(.C(clk_x16),
.CE(\bottom_right_0[15]_i_1_n_0 ),
.D(p_0_out[8]),
.Q(\bottom_right_0_reg_n_0_[8] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\bottom_right_0_reg[9]
(.C(clk_x16),
.CE(\bottom_right_0[15]_i_1_n_0 ),
.D(p_0_out[9]),
.Q(\bottom_right_0_reg_n_0_[9] ),
.R(1'b0));
LUT5 #(
.INIT(32'hB8BBB888))
\bottom_right_1[0]_i_1
(.I0(dout_0[0]),
.I1(\top_right_1[15]_i_2_n_0 ),
.I2(dout_1[0]),
.I3(\cycle_reg[2]_rep_n_0 ),
.I4(\bottom_left_0_reg_n_0_[0] ),
.O(\bottom_right_1[0]_i_1_n_0 ));
LUT5 #(
.INIT(32'hB8BBB888))
\bottom_right_1[10]_i_1
(.I0(dout_0[10]),
.I1(\top_right_1[15]_i_2_n_0 ),
.I2(dout_1[10]),
.I3(\cycle_reg[2]_rep_n_0 ),
.I4(\bottom_left_0_reg_n_0_[10] ),
.O(\bottom_right_1[10]_i_1_n_0 ));
LUT5 #(
.INIT(32'hB8BBB888))
\bottom_right_1[11]_i_1
(.I0(dout_0[11]),
.I1(\top_right_1[15]_i_2_n_0 ),
.I2(dout_1[11]),
.I3(\cycle_reg[2]_rep_n_0 ),
.I4(\bottom_left_0_reg_n_0_[11] ),
.O(\bottom_right_1[11]_i_1_n_0 ));
LUT5 #(
.INIT(32'hB8BBB888))
\bottom_right_1[12]_i_1
(.I0(dout_0[12]),
.I1(\top_right_1[15]_i_2_n_0 ),
.I2(dout_1[12]),
.I3(\cycle_reg[2]_rep_n_0 ),
.I4(\bottom_left_0_reg_n_0_[12] ),
.O(\bottom_right_1[12]_i_1_n_0 ));
LUT5 #(
.INIT(32'hB8BBB888))
\bottom_right_1[13]_i_1
(.I0(dout_0[13]),
.I1(\top_right_1[15]_i_2_n_0 ),
.I2(dout_1[13]),
.I3(\cycle_reg[2]_rep_n_0 ),
.I4(\bottom_left_0_reg_n_0_[13] ),
.O(\bottom_right_1[13]_i_1_n_0 ));
LUT5 #(
.INIT(32'hB8BBB888))
\bottom_right_1[14]_i_1
(.I0(dout_0[14]),
.I1(\top_right_1[15]_i_2_n_0 ),
.I2(dout_1[14]),
.I3(\cycle_reg[2]_rep_n_0 ),
.I4(\bottom_left_0_reg_n_0_[14] ),
.O(\bottom_right_1[14]_i_1_n_0 ));
LUT5 #(
.INIT(32'hB8BBB888))
\bottom_right_1[15]_i_1
(.I0(dout_0[15]),
.I1(\top_right_1[15]_i_2_n_0 ),
.I2(dout_1[15]),
.I3(\cycle_reg[2]_rep_n_0 ),
.I4(\bottom_left_0_reg_n_0_[15] ),
.O(\bottom_right_1[15]_i_1_n_0 ));
LUT5 #(
.INIT(32'hB8BBB888))
\bottom_right_1[1]_i_1
(.I0(dout_0[1]),
.I1(\top_right_1[15]_i_2_n_0 ),
.I2(dout_1[1]),
.I3(\cycle_reg[2]_rep_n_0 ),
.I4(\bottom_left_0_reg_n_0_[1] ),
.O(\bottom_right_1[1]_i_1_n_0 ));
LUT5 #(
.INIT(32'hB8BBB888))
\bottom_right_1[2]_i_1
(.I0(dout_0[2]),
.I1(\top_right_1[15]_i_2_n_0 ),
.I2(dout_1[2]),
.I3(\cycle_reg[2]_rep_n_0 ),
.I4(\bottom_left_0_reg_n_0_[2] ),
.O(\bottom_right_1[2]_i_1_n_0 ));
LUT5 #(
.INIT(32'hB8BBB888))
\bottom_right_1[3]_i_1
(.I0(dout_0[3]),
.I1(\top_right_1[15]_i_2_n_0 ),
.I2(dout_1[3]),
.I3(\cycle_reg[2]_rep_n_0 ),
.I4(\bottom_left_0_reg_n_0_[3] ),
.O(\bottom_right_1[3]_i_1_n_0 ));
LUT5 #(
.INIT(32'hB8BBB888))
\bottom_right_1[4]_i_1
(.I0(dout_0[4]),
.I1(\top_right_1[15]_i_2_n_0 ),
.I2(dout_1[4]),
.I3(\cycle_reg[2]_rep_n_0 ),
.I4(\bottom_left_0_reg_n_0_[4] ),
.O(\bottom_right_1[4]_i_1_n_0 ));
LUT5 #(
.INIT(32'hB8BBB888))
\bottom_right_1[5]_i_1
(.I0(dout_0[5]),
.I1(\top_right_1[15]_i_2_n_0 ),
.I2(dout_1[5]),
.I3(\cycle_reg[2]_rep_n_0 ),
.I4(\bottom_left_0_reg_n_0_[5] ),
.O(\bottom_right_1[5]_i_1_n_0 ));
LUT5 #(
.INIT(32'hB8BBB888))
\bottom_right_1[6]_i_1
(.I0(dout_0[6]),
.I1(\top_right_1[15]_i_2_n_0 ),
.I2(dout_1[6]),
.I3(\cycle_reg[2]_rep_n_0 ),
.I4(\bottom_left_0_reg_n_0_[6] ),
.O(\bottom_right_1[6]_i_1_n_0 ));
LUT5 #(
.INIT(32'hB8BBB888))
\bottom_right_1[7]_i_1
(.I0(dout_0[7]),
.I1(\top_right_1[15]_i_2_n_0 ),
.I2(dout_1[7]),
.I3(\cycle_reg[2]_rep_n_0 ),
.I4(\bottom_left_0_reg_n_0_[7] ),
.O(\bottom_right_1[7]_i_1_n_0 ));
LUT5 #(
.INIT(32'hB8BBB888))
\bottom_right_1[8]_i_1
(.I0(dout_0[8]),
.I1(\top_right_1[15]_i_2_n_0 ),
.I2(dout_1[8]),
.I3(\cycle_reg[2]_rep_n_0 ),
.I4(\bottom_left_0_reg_n_0_[8] ),
.O(\bottom_right_1[8]_i_1_n_0 ));
LUT5 #(
.INIT(32'hB8BBB888))
\bottom_right_1[9]_i_1
(.I0(dout_0[9]),
.I1(\top_right_1[15]_i_2_n_0 ),
.I2(dout_1[9]),
.I3(\cycle_reg[2]_rep_n_0 ),
.I4(\bottom_left_0_reg_n_0_[9] ),
.O(\bottom_right_1[9]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\bottom_right_1_reg[0]
(.C(clk_x16),
.CE(bottom_right_1),
.D(\bottom_right_1[0]_i_1_n_0 ),
.Q(\bottom_right_1_reg_n_0_[0] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\bottom_right_1_reg[10]
(.C(clk_x16),
.CE(bottom_right_1),
.D(\bottom_right_1[10]_i_1_n_0 ),
.Q(\bottom_right_1_reg_n_0_[10] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\bottom_right_1_reg[11]
(.C(clk_x16),
.CE(bottom_right_1),
.D(\bottom_right_1[11]_i_1_n_0 ),
.Q(\bottom_right_1_reg_n_0_[11] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\bottom_right_1_reg[12]
(.C(clk_x16),
.CE(bottom_right_1),
.D(\bottom_right_1[12]_i_1_n_0 ),
.Q(\bottom_right_1_reg_n_0_[12] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\bottom_right_1_reg[13]
(.C(clk_x16),
.CE(bottom_right_1),
.D(\bottom_right_1[13]_i_1_n_0 ),
.Q(\bottom_right_1_reg_n_0_[13] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\bottom_right_1_reg[14]
(.C(clk_x16),
.CE(bottom_right_1),
.D(\bottom_right_1[14]_i_1_n_0 ),
.Q(\bottom_right_1_reg_n_0_[14] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\bottom_right_1_reg[15]
(.C(clk_x16),
.CE(bottom_right_1),
.D(\bottom_right_1[15]_i_1_n_0 ),
.Q(\bottom_right_1_reg_n_0_[15] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\bottom_right_1_reg[1]
(.C(clk_x16),
.CE(bottom_right_1),
.D(\bottom_right_1[1]_i_1_n_0 ),
.Q(\bottom_right_1_reg_n_0_[1] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\bottom_right_1_reg[2]
(.C(clk_x16),
.CE(bottom_right_1),
.D(\bottom_right_1[2]_i_1_n_0 ),
.Q(\bottom_right_1_reg_n_0_[2] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\bottom_right_1_reg[3]
(.C(clk_x16),
.CE(bottom_right_1),
.D(\bottom_right_1[3]_i_1_n_0 ),
.Q(\bottom_right_1_reg_n_0_[3] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\bottom_right_1_reg[4]
(.C(clk_x16),
.CE(bottom_right_1),
.D(\bottom_right_1[4]_i_1_n_0 ),
.Q(\bottom_right_1_reg_n_0_[4] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\bottom_right_1_reg[5]
(.C(clk_x16),
.CE(bottom_right_1),
.D(\bottom_right_1[5]_i_1_n_0 ),
.Q(\bottom_right_1_reg_n_0_[5] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\bottom_right_1_reg[6]
(.C(clk_x16),
.CE(bottom_right_1),
.D(\bottom_right_1[6]_i_1_n_0 ),
.Q(\bottom_right_1_reg_n_0_[6] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\bottom_right_1_reg[7]
(.C(clk_x16),
.CE(bottom_right_1),
.D(\bottom_right_1[7]_i_1_n_0 ),
.Q(\bottom_right_1_reg_n_0_[7] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\bottom_right_1_reg[8]
(.C(clk_x16),
.CE(bottom_right_1),
.D(\bottom_right_1[8]_i_1_n_0 ),
.Q(\bottom_right_1_reg_n_0_[8] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\bottom_right_1_reg[9]
(.C(clk_x16),
.CE(bottom_right_1),
.D(\bottom_right_1[9]_i_1_n_0 ),
.Q(\bottom_right_1_reg_n_0_[9] ),
.R(1'b0));
(* CHECK_LICENSE_TYPE = "blk_mem_gen_0,blk_mem_gen_v8_3_5,{}" *)
(* downgradeipidentifiedwarnings = "yes" *)
(* x_core_info = "blk_mem_gen_v8_3_5,Vivado 2016.4" *)
system_vga_hessian_1_0_blk_mem_gen_0 bram_0
(.addra({\addr_0_reg_n_0_[13] ,\addr_0_reg_n_0_[12] ,\addr_0_reg_n_0_[11] ,\addr_0_reg_n_0_[10] ,\addr_0_reg_n_0_[9] ,\addr_0_reg_n_0_[8] ,\addr_0_reg_n_0_[7] ,\addr_0_reg_n_0_[6] ,\addr_0_reg_n_0_[5] ,\addr_0_reg_n_0_[4] ,\addr_0_reg_n_0_[3] ,\addr_0_reg_n_0_[2] ,\addr_0_reg_n_0_[1] ,\addr_0_reg_n_0_[0] }),
.addrb(addr_1),
.clka(clk_x16),
.clkb(clk_x16),
.dina({\din_reg_n_0_[15] ,\din_reg_n_0_[14] ,\din_reg_n_0_[13] ,\din_reg_n_0_[12] ,\din_reg_n_0_[11] ,\din_reg_n_0_[10] ,\din_reg_n_0_[9] ,\din_reg_n_0_[8] ,\din_reg_n_0_[7] ,\din_reg_n_0_[6] ,\din_reg_n_0_[5] ,\din_reg_n_0_[4] ,\din_reg_n_0_[3] ,\din_reg_n_0_[2] ,\din_reg_n_0_[1] ,\din_reg_n_0_[0] }),
.dinb({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.douta(dout_0),
.doutb(dout_1),
.ena(1'b1),
.enb(1'b1),
.wea(wen_reg_n_0),
.web(1'b0));
LUT1 #(
.INIT(2'h1))
\cache[9][15]_i_1
(.I0(rst),
.O(\cache[9][15]_i_1_n_0 ));
LUT5 #(
.INIT(32'h08000000))
\cache[9][15]_i_2
(.I0(active),
.I1(cycle[2]),
.I2(cycle[3]),
.I3(\cycle_reg[1]_rep_n_0 ),
.I4(\cycle_reg[0]_rep_n_0 ),
.O(\cache[10]_5 ));
FDRE #(
.INIT(1'b0))
\cache_reg[0][0]
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(Lyy_2_bottom_right[0]),
.Q(\cache_reg[0]_4 [0]),
.R(\cache[9][15]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\cache_reg[0][10]
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(Lyy_2_bottom_right[10]),
.Q(\cache_reg[0]_4 [10]),
.R(\cache[9][15]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\cache_reg[0][11]
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(Lyy_2_bottom_right[11]),
.Q(\cache_reg[0]_4 [11]),
.R(\cache[9][15]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\cache_reg[0][12]
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(Lyy_2_bottom_right[12]),
.Q(\cache_reg[0]_4 [12]),
.R(\cache[9][15]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\cache_reg[0][13]
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(Lyy_2_bottom_right[13]),
.Q(\cache_reg[0]_4 [13]),
.R(\cache[9][15]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\cache_reg[0][14]
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(Lyy_2_bottom_right[14]),
.Q(\cache_reg[0]_4 [14]),
.R(\cache[9][15]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\cache_reg[0][15]
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(Lyy_2_bottom_right[15]),
.Q(\cache_reg[0]_4 [15]),
.R(\cache[9][15]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\cache_reg[0][1]
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(Lyy_2_bottom_right[1]),
.Q(\cache_reg[0]_4 [1]),
.R(\cache[9][15]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\cache_reg[0][2]
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(Lyy_2_bottom_right[2]),
.Q(\cache_reg[0]_4 [2]),
.R(\cache[9][15]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\cache_reg[0][3]
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(Lyy_2_bottom_right[3]),
.Q(\cache_reg[0]_4 [3]),
.R(\cache[9][15]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\cache_reg[0][4]
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(Lyy_2_bottom_right[4]),
.Q(\cache_reg[0]_4 [4]),
.R(\cache[9][15]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\cache_reg[0][5]
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(Lyy_2_bottom_right[5]),
.Q(\cache_reg[0]_4 [5]),
.R(\cache[9][15]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\cache_reg[0][6]
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(Lyy_2_bottom_right[6]),
.Q(\cache_reg[0]_4 [6]),
.R(\cache[9][15]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\cache_reg[0][7]
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(Lyy_2_bottom_right[7]),
.Q(\cache_reg[0]_4 [7]),
.R(\cache[9][15]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\cache_reg[0][8]
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(Lyy_2_bottom_right[8]),
.Q(\cache_reg[0]_4 [8]),
.R(\cache[9][15]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\cache_reg[0][9]
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(Lyy_2_bottom_right[9]),
.Q(\cache_reg[0]_4 [9]),
.R(\cache[9][15]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\cache_reg[10][0]
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(\cache_reg[9]_2 [0]),
.Q(\cache_reg[10]_3 [0]),
.R(\cache[9][15]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\cache_reg[10][10]
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(\cache_reg[9]_2 [10]),
.Q(\cache_reg[10]_3 [10]),
.R(\cache[9][15]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\cache_reg[10][11]
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(\cache_reg[9]_2 [11]),
.Q(\cache_reg[10]_3 [11]),
.R(\cache[9][15]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\cache_reg[10][12]
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(\cache_reg[9]_2 [12]),
.Q(\cache_reg[10]_3 [12]),
.R(\cache[9][15]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\cache_reg[10][13]
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(\cache_reg[9]_2 [13]),
.Q(\cache_reg[10]_3 [13]),
.R(\cache[9][15]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\cache_reg[10][14]
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(\cache_reg[9]_2 [14]),
.Q(\cache_reg[10]_3 [14]),
.R(\cache[9][15]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\cache_reg[10][15]
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(\cache_reg[9]_2 [15]),
.Q(\cache_reg[10]_3 [15]),
.R(\cache[9][15]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\cache_reg[10][1]
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(\cache_reg[9]_2 [1]),
.Q(\cache_reg[10]_3 [1]),
.R(\cache[9][15]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\cache_reg[10][2]
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(\cache_reg[9]_2 [2]),
.Q(\cache_reg[10]_3 [2]),
.R(\cache[9][15]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\cache_reg[10][3]
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(\cache_reg[9]_2 [3]),
.Q(\cache_reg[10]_3 [3]),
.R(\cache[9][15]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\cache_reg[10][4]
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(\cache_reg[9]_2 [4]),
.Q(\cache_reg[10]_3 [4]),
.R(\cache[9][15]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\cache_reg[10][5]
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(\cache_reg[9]_2 [5]),
.Q(\cache_reg[10]_3 [5]),
.R(\cache[9][15]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\cache_reg[10][6]
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(\cache_reg[9]_2 [6]),
.Q(\cache_reg[10]_3 [6]),
.R(\cache[9][15]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\cache_reg[10][7]
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(\cache_reg[9]_2 [7]),
.Q(\cache_reg[10]_3 [7]),
.R(\cache[9][15]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\cache_reg[10][8]
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(\cache_reg[9]_2 [8]),
.Q(\cache_reg[10]_3 [8]),
.R(\cache[9][15]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\cache_reg[10][9]
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(\cache_reg[9]_2 [9]),
.Q(\cache_reg[10]_3 [9]),
.R(\cache[9][15]_i_1_n_0 ));
(* srl_bus_name = "\U0/cache_reg[2] " *)
(* srl_name = "\U0/cache_reg[2][0]_srl2___U0_cache_reg_r_0 " *)
SRL16E #(
.INIT(16'h0000))
\cache_reg[2][0]_srl2___U0_cache_reg_r_0
(.A0(1'b1),
.A1(1'b0),
.A2(1'b0),
.A3(1'b0),
.CE(\cache[10]_5 ),
.CLK(clk_x16),
.D(\cache_reg[0]_4 [0]),
.Q(\cache_reg[2][0]_srl2___U0_cache_reg_r_0_n_0 ));
(* srl_bus_name = "\U0/cache_reg[2] " *)
(* srl_name = "\U0/cache_reg[2][10]_srl2___U0_cache_reg_r_0 " *)
SRL16E #(
.INIT(16'h0000))
\cache_reg[2][10]_srl2___U0_cache_reg_r_0
(.A0(1'b1),
.A1(1'b0),
.A2(1'b0),
.A3(1'b0),
.CE(\cache[10]_5 ),
.CLK(clk_x16),
.D(\cache_reg[0]_4 [10]),
.Q(\cache_reg[2][10]_srl2___U0_cache_reg_r_0_n_0 ));
(* srl_bus_name = "\U0/cache_reg[2] " *)
(* srl_name = "\U0/cache_reg[2][11]_srl2___U0_cache_reg_r_0 " *)
SRL16E #(
.INIT(16'h0000))
\cache_reg[2][11]_srl2___U0_cache_reg_r_0
(.A0(1'b1),
.A1(1'b0),
.A2(1'b0),
.A3(1'b0),
.CE(\cache[10]_5 ),
.CLK(clk_x16),
.D(\cache_reg[0]_4 [11]),
.Q(\cache_reg[2][11]_srl2___U0_cache_reg_r_0_n_0 ));
(* srl_bus_name = "\U0/cache_reg[2] " *)
(* srl_name = "\U0/cache_reg[2][12]_srl2___U0_cache_reg_r_0 " *)
SRL16E #(
.INIT(16'h0000))
\cache_reg[2][12]_srl2___U0_cache_reg_r_0
(.A0(1'b1),
.A1(1'b0),
.A2(1'b0),
.A3(1'b0),
.CE(\cache[10]_5 ),
.CLK(clk_x16),
.D(\cache_reg[0]_4 [12]),
.Q(\cache_reg[2][12]_srl2___U0_cache_reg_r_0_n_0 ));
(* srl_bus_name = "\U0/cache_reg[2] " *)
(* srl_name = "\U0/cache_reg[2][13]_srl2___U0_cache_reg_r_0 " *)
SRL16E #(
.INIT(16'h0000))
\cache_reg[2][13]_srl2___U0_cache_reg_r_0
(.A0(1'b1),
.A1(1'b0),
.A2(1'b0),
.A3(1'b0),
.CE(\cache[10]_5 ),
.CLK(clk_x16),
.D(\cache_reg[0]_4 [13]),
.Q(\cache_reg[2][13]_srl2___U0_cache_reg_r_0_n_0 ));
(* srl_bus_name = "\U0/cache_reg[2] " *)
(* srl_name = "\U0/cache_reg[2][14]_srl2___U0_cache_reg_r_0 " *)
SRL16E #(
.INIT(16'h0000))
\cache_reg[2][14]_srl2___U0_cache_reg_r_0
(.A0(1'b1),
.A1(1'b0),
.A2(1'b0),
.A3(1'b0),
.CE(\cache[10]_5 ),
.CLK(clk_x16),
.D(\cache_reg[0]_4 [14]),
.Q(\cache_reg[2][14]_srl2___U0_cache_reg_r_0_n_0 ));
(* srl_bus_name = "\U0/cache_reg[2] " *)
(* srl_name = "\U0/cache_reg[2][15]_srl2___U0_cache_reg_r_0 " *)
SRL16E #(
.INIT(16'h0000))
\cache_reg[2][15]_srl2___U0_cache_reg_r_0
(.A0(1'b1),
.A1(1'b0),
.A2(1'b0),
.A3(1'b0),
.CE(\cache[10]_5 ),
.CLK(clk_x16),
.D(\cache_reg[0]_4 [15]),
.Q(\cache_reg[2][15]_srl2___U0_cache_reg_r_0_n_0 ));
(* srl_bus_name = "\U0/cache_reg[2] " *)
(* srl_name = "\U0/cache_reg[2][1]_srl2___U0_cache_reg_r_0 " *)
SRL16E #(
.INIT(16'h0000))
\cache_reg[2][1]_srl2___U0_cache_reg_r_0
(.A0(1'b1),
.A1(1'b0),
.A2(1'b0),
.A3(1'b0),
.CE(\cache[10]_5 ),
.CLK(clk_x16),
.D(\cache_reg[0]_4 [1]),
.Q(\cache_reg[2][1]_srl2___U0_cache_reg_r_0_n_0 ));
(* srl_bus_name = "\U0/cache_reg[2] " *)
(* srl_name = "\U0/cache_reg[2][2]_srl2___U0_cache_reg_r_0 " *)
SRL16E #(
.INIT(16'h0000))
\cache_reg[2][2]_srl2___U0_cache_reg_r_0
(.A0(1'b1),
.A1(1'b0),
.A2(1'b0),
.A3(1'b0),
.CE(\cache[10]_5 ),
.CLK(clk_x16),
.D(\cache_reg[0]_4 [2]),
.Q(\cache_reg[2][2]_srl2___U0_cache_reg_r_0_n_0 ));
(* srl_bus_name = "\U0/cache_reg[2] " *)
(* srl_name = "\U0/cache_reg[2][3]_srl2___U0_cache_reg_r_0 " *)
SRL16E #(
.INIT(16'h0000))
\cache_reg[2][3]_srl2___U0_cache_reg_r_0
(.A0(1'b1),
.A1(1'b0),
.A2(1'b0),
.A3(1'b0),
.CE(\cache[10]_5 ),
.CLK(clk_x16),
.D(\cache_reg[0]_4 [3]),
.Q(\cache_reg[2][3]_srl2___U0_cache_reg_r_0_n_0 ));
(* srl_bus_name = "\U0/cache_reg[2] " *)
(* srl_name = "\U0/cache_reg[2][4]_srl2___U0_cache_reg_r_0 " *)
SRL16E #(
.INIT(16'h0000))
\cache_reg[2][4]_srl2___U0_cache_reg_r_0
(.A0(1'b1),
.A1(1'b0),
.A2(1'b0),
.A3(1'b0),
.CE(\cache[10]_5 ),
.CLK(clk_x16),
.D(\cache_reg[0]_4 [4]),
.Q(\cache_reg[2][4]_srl2___U0_cache_reg_r_0_n_0 ));
(* srl_bus_name = "\U0/cache_reg[2] " *)
(* srl_name = "\U0/cache_reg[2][5]_srl2___U0_cache_reg_r_0 " *)
SRL16E #(
.INIT(16'h0000))
\cache_reg[2][5]_srl2___U0_cache_reg_r_0
(.A0(1'b1),
.A1(1'b0),
.A2(1'b0),
.A3(1'b0),
.CE(\cache[10]_5 ),
.CLK(clk_x16),
.D(\cache_reg[0]_4 [5]),
.Q(\cache_reg[2][5]_srl2___U0_cache_reg_r_0_n_0 ));
(* srl_bus_name = "\U0/cache_reg[2] " *)
(* srl_name = "\U0/cache_reg[2][6]_srl2___U0_cache_reg_r_0 " *)
SRL16E #(
.INIT(16'h0000))
\cache_reg[2][6]_srl2___U0_cache_reg_r_0
(.A0(1'b1),
.A1(1'b0),
.A2(1'b0),
.A3(1'b0),
.CE(\cache[10]_5 ),
.CLK(clk_x16),
.D(\cache_reg[0]_4 [6]),
.Q(\cache_reg[2][6]_srl2___U0_cache_reg_r_0_n_0 ));
(* srl_bus_name = "\U0/cache_reg[2] " *)
(* srl_name = "\U0/cache_reg[2][7]_srl2___U0_cache_reg_r_0 " *)
SRL16E #(
.INIT(16'h0000))
\cache_reg[2][7]_srl2___U0_cache_reg_r_0
(.A0(1'b1),
.A1(1'b0),
.A2(1'b0),
.A3(1'b0),
.CE(\cache[10]_5 ),
.CLK(clk_x16),
.D(\cache_reg[0]_4 [7]),
.Q(\cache_reg[2][7]_srl2___U0_cache_reg_r_0_n_0 ));
(* srl_bus_name = "\U0/cache_reg[2] " *)
(* srl_name = "\U0/cache_reg[2][8]_srl2___U0_cache_reg_r_0 " *)
SRL16E #(
.INIT(16'h0000))
\cache_reg[2][8]_srl2___U0_cache_reg_r_0
(.A0(1'b1),
.A1(1'b0),
.A2(1'b0),
.A3(1'b0),
.CE(\cache[10]_5 ),
.CLK(clk_x16),
.D(\cache_reg[0]_4 [8]),
.Q(\cache_reg[2][8]_srl2___U0_cache_reg_r_0_n_0 ));
(* srl_bus_name = "\U0/cache_reg[2] " *)
(* srl_name = "\U0/cache_reg[2][9]_srl2___U0_cache_reg_r_0 " *)
SRL16E #(
.INIT(16'h0000))
\cache_reg[2][9]_srl2___U0_cache_reg_r_0
(.A0(1'b1),
.A1(1'b0),
.A2(1'b0),
.A3(1'b0),
.CE(\cache[10]_5 ),
.CLK(clk_x16),
.D(\cache_reg[0]_4 [9]),
.Q(\cache_reg[2][9]_srl2___U0_cache_reg_r_0_n_0 ));
FDRE \cache_reg[3][0]_U0_cache_reg_r_1
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(\cache_reg[2][0]_srl2___U0_cache_reg_r_0_n_0 ),
.Q(\cache_reg[3][0]_U0_cache_reg_r_1_n_0 ),
.R(1'b0));
FDRE \cache_reg[3][10]_U0_cache_reg_r_1
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(\cache_reg[2][10]_srl2___U0_cache_reg_r_0_n_0 ),
.Q(\cache_reg[3][10]_U0_cache_reg_r_1_n_0 ),
.R(1'b0));
FDRE \cache_reg[3][11]_U0_cache_reg_r_1
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(\cache_reg[2][11]_srl2___U0_cache_reg_r_0_n_0 ),
.Q(\cache_reg[3][11]_U0_cache_reg_r_1_n_0 ),
.R(1'b0));
FDRE \cache_reg[3][12]_U0_cache_reg_r_1
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(\cache_reg[2][12]_srl2___U0_cache_reg_r_0_n_0 ),
.Q(\cache_reg[3][12]_U0_cache_reg_r_1_n_0 ),
.R(1'b0));
FDRE \cache_reg[3][13]_U0_cache_reg_r_1
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(\cache_reg[2][13]_srl2___U0_cache_reg_r_0_n_0 ),
.Q(\cache_reg[3][13]_U0_cache_reg_r_1_n_0 ),
.R(1'b0));
FDRE \cache_reg[3][14]_U0_cache_reg_r_1
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(\cache_reg[2][14]_srl2___U0_cache_reg_r_0_n_0 ),
.Q(\cache_reg[3][14]_U0_cache_reg_r_1_n_0 ),
.R(1'b0));
FDRE \cache_reg[3][15]_U0_cache_reg_r_1
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(\cache_reg[2][15]_srl2___U0_cache_reg_r_0_n_0 ),
.Q(\cache_reg[3][15]_U0_cache_reg_r_1_n_0 ),
.R(1'b0));
FDRE \cache_reg[3][1]_U0_cache_reg_r_1
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(\cache_reg[2][1]_srl2___U0_cache_reg_r_0_n_0 ),
.Q(\cache_reg[3][1]_U0_cache_reg_r_1_n_0 ),
.R(1'b0));
FDRE \cache_reg[3][2]_U0_cache_reg_r_1
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(\cache_reg[2][2]_srl2___U0_cache_reg_r_0_n_0 ),
.Q(\cache_reg[3][2]_U0_cache_reg_r_1_n_0 ),
.R(1'b0));
FDRE \cache_reg[3][3]_U0_cache_reg_r_1
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(\cache_reg[2][3]_srl2___U0_cache_reg_r_0_n_0 ),
.Q(\cache_reg[3][3]_U0_cache_reg_r_1_n_0 ),
.R(1'b0));
FDRE \cache_reg[3][4]_U0_cache_reg_r_1
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(\cache_reg[2][4]_srl2___U0_cache_reg_r_0_n_0 ),
.Q(\cache_reg[3][4]_U0_cache_reg_r_1_n_0 ),
.R(1'b0));
FDRE \cache_reg[3][5]_U0_cache_reg_r_1
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(\cache_reg[2][5]_srl2___U0_cache_reg_r_0_n_0 ),
.Q(\cache_reg[3][5]_U0_cache_reg_r_1_n_0 ),
.R(1'b0));
FDRE \cache_reg[3][6]_U0_cache_reg_r_1
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(\cache_reg[2][6]_srl2___U0_cache_reg_r_0_n_0 ),
.Q(\cache_reg[3][6]_U0_cache_reg_r_1_n_0 ),
.R(1'b0));
FDRE \cache_reg[3][7]_U0_cache_reg_r_1
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(\cache_reg[2][7]_srl2___U0_cache_reg_r_0_n_0 ),
.Q(\cache_reg[3][7]_U0_cache_reg_r_1_n_0 ),
.R(1'b0));
FDRE \cache_reg[3][8]_U0_cache_reg_r_1
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(\cache_reg[2][8]_srl2___U0_cache_reg_r_0_n_0 ),
.Q(\cache_reg[3][8]_U0_cache_reg_r_1_n_0 ),
.R(1'b0));
FDRE \cache_reg[3][9]_U0_cache_reg_r_1
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(\cache_reg[2][9]_srl2___U0_cache_reg_r_0_n_0 ),
.Q(\cache_reg[3][9]_U0_cache_reg_r_1_n_0 ),
.R(1'b0));
FDRE \cache_reg[4][0]
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(cache_reg_gate__14_n_0),
.Q(\cache_reg[4]_0 [0]),
.R(\cache[9][15]_i_1_n_0 ));
FDRE \cache_reg[4][10]
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(cache_reg_gate__4_n_0),
.Q(\cache_reg[4]_0 [10]),
.R(\cache[9][15]_i_1_n_0 ));
FDRE \cache_reg[4][11]
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(cache_reg_gate__3_n_0),
.Q(\cache_reg[4]_0 [11]),
.R(\cache[9][15]_i_1_n_0 ));
FDRE \cache_reg[4][12]
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(cache_reg_gate__2_n_0),
.Q(\cache_reg[4]_0 [12]),
.R(\cache[9][15]_i_1_n_0 ));
FDRE \cache_reg[4][13]
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(cache_reg_gate__1_n_0),
.Q(\cache_reg[4]_0 [13]),
.R(\cache[9][15]_i_1_n_0 ));
FDRE \cache_reg[4][14]
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(cache_reg_gate__0_n_0),
.Q(\cache_reg[4]_0 [14]),
.R(\cache[9][15]_i_1_n_0 ));
FDRE \cache_reg[4][15]
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(cache_reg_gate_n_0),
.Q(\cache_reg[4]_0 [15]),
.R(\cache[9][15]_i_1_n_0 ));
FDRE \cache_reg[4][1]
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(cache_reg_gate__13_n_0),
.Q(\cache_reg[4]_0 [1]),
.R(\cache[9][15]_i_1_n_0 ));
FDRE \cache_reg[4][2]
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(cache_reg_gate__12_n_0),
.Q(\cache_reg[4]_0 [2]),
.R(\cache[9][15]_i_1_n_0 ));
FDRE \cache_reg[4][3]
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(cache_reg_gate__11_n_0),
.Q(\cache_reg[4]_0 [3]),
.R(\cache[9][15]_i_1_n_0 ));
FDRE \cache_reg[4][4]
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(cache_reg_gate__10_n_0),
.Q(\cache_reg[4]_0 [4]),
.R(\cache[9][15]_i_1_n_0 ));
FDRE \cache_reg[4][5]
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(cache_reg_gate__9_n_0),
.Q(\cache_reg[4]_0 [5]),
.R(\cache[9][15]_i_1_n_0 ));
FDRE \cache_reg[4][6]
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(cache_reg_gate__8_n_0),
.Q(\cache_reg[4]_0 [6]),
.R(\cache[9][15]_i_1_n_0 ));
FDRE \cache_reg[4][7]
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(cache_reg_gate__7_n_0),
.Q(\cache_reg[4]_0 [7]),
.R(\cache[9][15]_i_1_n_0 ));
FDRE \cache_reg[4][8]
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(cache_reg_gate__6_n_0),
.Q(\cache_reg[4]_0 [8]),
.R(\cache[9][15]_i_1_n_0 ));
FDRE \cache_reg[4][9]
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(cache_reg_gate__5_n_0),
.Q(\cache_reg[4]_0 [9]),
.R(\cache[9][15]_i_1_n_0 ));
(* srl_bus_name = "\U0/cache_reg[6] " *)
(* srl_name = "\U0/cache_reg[6][0]_srl2___U0_cache_reg_r_0 " *)
SRL16E #(
.INIT(16'h0000))
\cache_reg[6][0]_srl2___U0_cache_reg_r_0
(.A0(1'b1),
.A1(1'b0),
.A2(1'b0),
.A3(1'b0),
.CE(\cache[10]_5 ),
.CLK(clk_x16),
.D(\cache_reg[4]_0 [0]),
.Q(\cache_reg[6][0]_srl2___U0_cache_reg_r_0_n_0 ));
(* srl_bus_name = "\U0/cache_reg[6] " *)
(* srl_name = "\U0/cache_reg[6][10]_srl2___U0_cache_reg_r_0 " *)
SRL16E #(
.INIT(16'h0000))
\cache_reg[6][10]_srl2___U0_cache_reg_r_0
(.A0(1'b1),
.A1(1'b0),
.A2(1'b0),
.A3(1'b0),
.CE(\cache[10]_5 ),
.CLK(clk_x16),
.D(\cache_reg[4]_0 [10]),
.Q(\cache_reg[6][10]_srl2___U0_cache_reg_r_0_n_0 ));
(* srl_bus_name = "\U0/cache_reg[6] " *)
(* srl_name = "\U0/cache_reg[6][11]_srl2___U0_cache_reg_r_0 " *)
SRL16E #(
.INIT(16'h0000))
\cache_reg[6][11]_srl2___U0_cache_reg_r_0
(.A0(1'b1),
.A1(1'b0),
.A2(1'b0),
.A3(1'b0),
.CE(\cache[10]_5 ),
.CLK(clk_x16),
.D(\cache_reg[4]_0 [11]),
.Q(\cache_reg[6][11]_srl2___U0_cache_reg_r_0_n_0 ));
(* srl_bus_name = "\U0/cache_reg[6] " *)
(* srl_name = "\U0/cache_reg[6][12]_srl2___U0_cache_reg_r_0 " *)
SRL16E #(
.INIT(16'h0000))
\cache_reg[6][12]_srl2___U0_cache_reg_r_0
(.A0(1'b1),
.A1(1'b0),
.A2(1'b0),
.A3(1'b0),
.CE(\cache[10]_5 ),
.CLK(clk_x16),
.D(\cache_reg[4]_0 [12]),
.Q(\cache_reg[6][12]_srl2___U0_cache_reg_r_0_n_0 ));
(* srl_bus_name = "\U0/cache_reg[6] " *)
(* srl_name = "\U0/cache_reg[6][13]_srl2___U0_cache_reg_r_0 " *)
SRL16E #(
.INIT(16'h0000))
\cache_reg[6][13]_srl2___U0_cache_reg_r_0
(.A0(1'b1),
.A1(1'b0),
.A2(1'b0),
.A3(1'b0),
.CE(\cache[10]_5 ),
.CLK(clk_x16),
.D(\cache_reg[4]_0 [13]),
.Q(\cache_reg[6][13]_srl2___U0_cache_reg_r_0_n_0 ));
(* srl_bus_name = "\U0/cache_reg[6] " *)
(* srl_name = "\U0/cache_reg[6][14]_srl2___U0_cache_reg_r_0 " *)
SRL16E #(
.INIT(16'h0000))
\cache_reg[6][14]_srl2___U0_cache_reg_r_0
(.A0(1'b1),
.A1(1'b0),
.A2(1'b0),
.A3(1'b0),
.CE(\cache[10]_5 ),
.CLK(clk_x16),
.D(\cache_reg[4]_0 [14]),
.Q(\cache_reg[6][14]_srl2___U0_cache_reg_r_0_n_0 ));
(* srl_bus_name = "\U0/cache_reg[6] " *)
(* srl_name = "\U0/cache_reg[6][15]_srl2___U0_cache_reg_r_0 " *)
SRL16E #(
.INIT(16'h0000))
\cache_reg[6][15]_srl2___U0_cache_reg_r_0
(.A0(1'b1),
.A1(1'b0),
.A2(1'b0),
.A3(1'b0),
.CE(\cache[10]_5 ),
.CLK(clk_x16),
.D(\cache_reg[4]_0 [15]),
.Q(\cache_reg[6][15]_srl2___U0_cache_reg_r_0_n_0 ));
(* srl_bus_name = "\U0/cache_reg[6] " *)
(* srl_name = "\U0/cache_reg[6][1]_srl2___U0_cache_reg_r_0 " *)
SRL16E #(
.INIT(16'h0000))
\cache_reg[6][1]_srl2___U0_cache_reg_r_0
(.A0(1'b1),
.A1(1'b0),
.A2(1'b0),
.A3(1'b0),
.CE(\cache[10]_5 ),
.CLK(clk_x16),
.D(\cache_reg[4]_0 [1]),
.Q(\cache_reg[6][1]_srl2___U0_cache_reg_r_0_n_0 ));
(* srl_bus_name = "\U0/cache_reg[6] " *)
(* srl_name = "\U0/cache_reg[6][2]_srl2___U0_cache_reg_r_0 " *)
SRL16E #(
.INIT(16'h0000))
\cache_reg[6][2]_srl2___U0_cache_reg_r_0
(.A0(1'b1),
.A1(1'b0),
.A2(1'b0),
.A3(1'b0),
.CE(\cache[10]_5 ),
.CLK(clk_x16),
.D(\cache_reg[4]_0 [2]),
.Q(\cache_reg[6][2]_srl2___U0_cache_reg_r_0_n_0 ));
(* srl_bus_name = "\U0/cache_reg[6] " *)
(* srl_name = "\U0/cache_reg[6][3]_srl2___U0_cache_reg_r_0 " *)
SRL16E #(
.INIT(16'h0000))
\cache_reg[6][3]_srl2___U0_cache_reg_r_0
(.A0(1'b1),
.A1(1'b0),
.A2(1'b0),
.A3(1'b0),
.CE(\cache[10]_5 ),
.CLK(clk_x16),
.D(\cache_reg[4]_0 [3]),
.Q(\cache_reg[6][3]_srl2___U0_cache_reg_r_0_n_0 ));
(* srl_bus_name = "\U0/cache_reg[6] " *)
(* srl_name = "\U0/cache_reg[6][4]_srl2___U0_cache_reg_r_0 " *)
SRL16E #(
.INIT(16'h0000))
\cache_reg[6][4]_srl2___U0_cache_reg_r_0
(.A0(1'b1),
.A1(1'b0),
.A2(1'b0),
.A3(1'b0),
.CE(\cache[10]_5 ),
.CLK(clk_x16),
.D(\cache_reg[4]_0 [4]),
.Q(\cache_reg[6][4]_srl2___U0_cache_reg_r_0_n_0 ));
(* srl_bus_name = "\U0/cache_reg[6] " *)
(* srl_name = "\U0/cache_reg[6][5]_srl2___U0_cache_reg_r_0 " *)
SRL16E #(
.INIT(16'h0000))
\cache_reg[6][5]_srl2___U0_cache_reg_r_0
(.A0(1'b1),
.A1(1'b0),
.A2(1'b0),
.A3(1'b0),
.CE(\cache[10]_5 ),
.CLK(clk_x16),
.D(\cache_reg[4]_0 [5]),
.Q(\cache_reg[6][5]_srl2___U0_cache_reg_r_0_n_0 ));
(* srl_bus_name = "\U0/cache_reg[6] " *)
(* srl_name = "\U0/cache_reg[6][6]_srl2___U0_cache_reg_r_0 " *)
SRL16E #(
.INIT(16'h0000))
\cache_reg[6][6]_srl2___U0_cache_reg_r_0
(.A0(1'b1),
.A1(1'b0),
.A2(1'b0),
.A3(1'b0),
.CE(\cache[10]_5 ),
.CLK(clk_x16),
.D(\cache_reg[4]_0 [6]),
.Q(\cache_reg[6][6]_srl2___U0_cache_reg_r_0_n_0 ));
(* srl_bus_name = "\U0/cache_reg[6] " *)
(* srl_name = "\U0/cache_reg[6][7]_srl2___U0_cache_reg_r_0 " *)
SRL16E #(
.INIT(16'h0000))
\cache_reg[6][7]_srl2___U0_cache_reg_r_0
(.A0(1'b1),
.A1(1'b0),
.A2(1'b0),
.A3(1'b0),
.CE(\cache[10]_5 ),
.CLK(clk_x16),
.D(\cache_reg[4]_0 [7]),
.Q(\cache_reg[6][7]_srl2___U0_cache_reg_r_0_n_0 ));
(* srl_bus_name = "\U0/cache_reg[6] " *)
(* srl_name = "\U0/cache_reg[6][8]_srl2___U0_cache_reg_r_0 " *)
SRL16E #(
.INIT(16'h0000))
\cache_reg[6][8]_srl2___U0_cache_reg_r_0
(.A0(1'b1),
.A1(1'b0),
.A2(1'b0),
.A3(1'b0),
.CE(\cache[10]_5 ),
.CLK(clk_x16),
.D(\cache_reg[4]_0 [8]),
.Q(\cache_reg[6][8]_srl2___U0_cache_reg_r_0_n_0 ));
(* srl_bus_name = "\U0/cache_reg[6] " *)
(* srl_name = "\U0/cache_reg[6][9]_srl2___U0_cache_reg_r_0 " *)
SRL16E #(
.INIT(16'h0000))
\cache_reg[6][9]_srl2___U0_cache_reg_r_0
(.A0(1'b1),
.A1(1'b0),
.A2(1'b0),
.A3(1'b0),
.CE(\cache[10]_5 ),
.CLK(clk_x16),
.D(\cache_reg[4]_0 [9]),
.Q(\cache_reg[6][9]_srl2___U0_cache_reg_r_0_n_0 ));
FDRE \cache_reg[7][0]_U0_cache_reg_r_1
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(\cache_reg[6][0]_srl2___U0_cache_reg_r_0_n_0 ),
.Q(\cache_reg[7][0]_U0_cache_reg_r_1_n_0 ),
.R(1'b0));
FDRE \cache_reg[7][10]_U0_cache_reg_r_1
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(\cache_reg[6][10]_srl2___U0_cache_reg_r_0_n_0 ),
.Q(\cache_reg[7][10]_U0_cache_reg_r_1_n_0 ),
.R(1'b0));
FDRE \cache_reg[7][11]_U0_cache_reg_r_1
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(\cache_reg[6][11]_srl2___U0_cache_reg_r_0_n_0 ),
.Q(\cache_reg[7][11]_U0_cache_reg_r_1_n_0 ),
.R(1'b0));
FDRE \cache_reg[7][12]_U0_cache_reg_r_1
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(\cache_reg[6][12]_srl2___U0_cache_reg_r_0_n_0 ),
.Q(\cache_reg[7][12]_U0_cache_reg_r_1_n_0 ),
.R(1'b0));
FDRE \cache_reg[7][13]_U0_cache_reg_r_1
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(\cache_reg[6][13]_srl2___U0_cache_reg_r_0_n_0 ),
.Q(\cache_reg[7][13]_U0_cache_reg_r_1_n_0 ),
.R(1'b0));
FDRE \cache_reg[7][14]_U0_cache_reg_r_1
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(\cache_reg[6][14]_srl2___U0_cache_reg_r_0_n_0 ),
.Q(\cache_reg[7][14]_U0_cache_reg_r_1_n_0 ),
.R(1'b0));
FDRE \cache_reg[7][15]_U0_cache_reg_r_1
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(\cache_reg[6][15]_srl2___U0_cache_reg_r_0_n_0 ),
.Q(\cache_reg[7][15]_U0_cache_reg_r_1_n_0 ),
.R(1'b0));
FDRE \cache_reg[7][1]_U0_cache_reg_r_1
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(\cache_reg[6][1]_srl2___U0_cache_reg_r_0_n_0 ),
.Q(\cache_reg[7][1]_U0_cache_reg_r_1_n_0 ),
.R(1'b0));
FDRE \cache_reg[7][2]_U0_cache_reg_r_1
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(\cache_reg[6][2]_srl2___U0_cache_reg_r_0_n_0 ),
.Q(\cache_reg[7][2]_U0_cache_reg_r_1_n_0 ),
.R(1'b0));
FDRE \cache_reg[7][3]_U0_cache_reg_r_1
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(\cache_reg[6][3]_srl2___U0_cache_reg_r_0_n_0 ),
.Q(\cache_reg[7][3]_U0_cache_reg_r_1_n_0 ),
.R(1'b0));
FDRE \cache_reg[7][4]_U0_cache_reg_r_1
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(\cache_reg[6][4]_srl2___U0_cache_reg_r_0_n_0 ),
.Q(\cache_reg[7][4]_U0_cache_reg_r_1_n_0 ),
.R(1'b0));
FDRE \cache_reg[7][5]_U0_cache_reg_r_1
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(\cache_reg[6][5]_srl2___U0_cache_reg_r_0_n_0 ),
.Q(\cache_reg[7][5]_U0_cache_reg_r_1_n_0 ),
.R(1'b0));
FDRE \cache_reg[7][6]_U0_cache_reg_r_1
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(\cache_reg[6][6]_srl2___U0_cache_reg_r_0_n_0 ),
.Q(\cache_reg[7][6]_U0_cache_reg_r_1_n_0 ),
.R(1'b0));
FDRE \cache_reg[7][7]_U0_cache_reg_r_1
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(\cache_reg[6][7]_srl2___U0_cache_reg_r_0_n_0 ),
.Q(\cache_reg[7][7]_U0_cache_reg_r_1_n_0 ),
.R(1'b0));
FDRE \cache_reg[7][8]_U0_cache_reg_r_1
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(\cache_reg[6][8]_srl2___U0_cache_reg_r_0_n_0 ),
.Q(\cache_reg[7][8]_U0_cache_reg_r_1_n_0 ),
.R(1'b0));
FDRE \cache_reg[7][9]_U0_cache_reg_r_1
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(\cache_reg[6][9]_srl2___U0_cache_reg_r_0_n_0 ),
.Q(\cache_reg[7][9]_U0_cache_reg_r_1_n_0 ),
.R(1'b0));
FDRE \cache_reg[8][0]
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(cache_reg_gate__30_n_0),
.Q(\cache_reg[8]_1 [0]),
.R(\cache[9][15]_i_1_n_0 ));
FDRE \cache_reg[8][10]
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(cache_reg_gate__20_n_0),
.Q(\cache_reg[8]_1 [10]),
.R(\cache[9][15]_i_1_n_0 ));
FDRE \cache_reg[8][11]
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(cache_reg_gate__19_n_0),
.Q(\cache_reg[8]_1 [11]),
.R(\cache[9][15]_i_1_n_0 ));
FDRE \cache_reg[8][12]
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(cache_reg_gate__18_n_0),
.Q(\cache_reg[8]_1 [12]),
.R(\cache[9][15]_i_1_n_0 ));
FDRE \cache_reg[8][13]
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(cache_reg_gate__17_n_0),
.Q(\cache_reg[8]_1 [13]),
.R(\cache[9][15]_i_1_n_0 ));
FDRE \cache_reg[8][14]
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(cache_reg_gate__16_n_0),
.Q(\cache_reg[8]_1 [14]),
.R(\cache[9][15]_i_1_n_0 ));
FDRE \cache_reg[8][15]
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(cache_reg_gate__15_n_0),
.Q(\cache_reg[8]_1 [15]),
.R(\cache[9][15]_i_1_n_0 ));
FDRE \cache_reg[8][1]
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(cache_reg_gate__29_n_0),
.Q(\cache_reg[8]_1 [1]),
.R(\cache[9][15]_i_1_n_0 ));
FDRE \cache_reg[8][2]
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(cache_reg_gate__28_n_0),
.Q(\cache_reg[8]_1 [2]),
.R(\cache[9][15]_i_1_n_0 ));
FDRE \cache_reg[8][3]
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(cache_reg_gate__27_n_0),
.Q(\cache_reg[8]_1 [3]),
.R(\cache[9][15]_i_1_n_0 ));
FDRE \cache_reg[8][4]
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(cache_reg_gate__26_n_0),
.Q(\cache_reg[8]_1 [4]),
.R(\cache[9][15]_i_1_n_0 ));
FDRE \cache_reg[8][5]
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(cache_reg_gate__25_n_0),
.Q(\cache_reg[8]_1 [5]),
.R(\cache[9][15]_i_1_n_0 ));
FDRE \cache_reg[8][6]
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(cache_reg_gate__24_n_0),
.Q(\cache_reg[8]_1 [6]),
.R(\cache[9][15]_i_1_n_0 ));
FDRE \cache_reg[8][7]
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(cache_reg_gate__23_n_0),
.Q(\cache_reg[8]_1 [7]),
.R(\cache[9][15]_i_1_n_0 ));
FDRE \cache_reg[8][8]
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(cache_reg_gate__22_n_0),
.Q(\cache_reg[8]_1 [8]),
.R(\cache[9][15]_i_1_n_0 ));
FDRE \cache_reg[8][9]
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(cache_reg_gate__21_n_0),
.Q(\cache_reg[8]_1 [9]),
.R(\cache[9][15]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\cache_reg[9][0]
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(\cache_reg[8]_1 [0]),
.Q(\cache_reg[9]_2 [0]),
.R(\cache[9][15]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\cache_reg[9][10]
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(\cache_reg[8]_1 [10]),
.Q(\cache_reg[9]_2 [10]),
.R(\cache[9][15]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\cache_reg[9][11]
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(\cache_reg[8]_1 [11]),
.Q(\cache_reg[9]_2 [11]),
.R(\cache[9][15]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\cache_reg[9][12]
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(\cache_reg[8]_1 [12]),
.Q(\cache_reg[9]_2 [12]),
.R(\cache[9][15]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\cache_reg[9][13]
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(\cache_reg[8]_1 [13]),
.Q(\cache_reg[9]_2 [13]),
.R(\cache[9][15]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\cache_reg[9][14]
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(\cache_reg[8]_1 [14]),
.Q(\cache_reg[9]_2 [14]),
.R(\cache[9][15]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\cache_reg[9][15]
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(\cache_reg[8]_1 [15]),
.Q(\cache_reg[9]_2 [15]),
.R(\cache[9][15]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\cache_reg[9][1]
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(\cache_reg[8]_1 [1]),
.Q(\cache_reg[9]_2 [1]),
.R(\cache[9][15]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\cache_reg[9][2]
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(\cache_reg[8]_1 [2]),
.Q(\cache_reg[9]_2 [2]),
.R(\cache[9][15]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\cache_reg[9][3]
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(\cache_reg[8]_1 [3]),
.Q(\cache_reg[9]_2 [3]),
.R(\cache[9][15]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\cache_reg[9][4]
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(\cache_reg[8]_1 [4]),
.Q(\cache_reg[9]_2 [4]),
.R(\cache[9][15]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\cache_reg[9][5]
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(\cache_reg[8]_1 [5]),
.Q(\cache_reg[9]_2 [5]),
.R(\cache[9][15]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\cache_reg[9][6]
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(\cache_reg[8]_1 [6]),
.Q(\cache_reg[9]_2 [6]),
.R(\cache[9][15]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\cache_reg[9][7]
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(\cache_reg[8]_1 [7]),
.Q(\cache_reg[9]_2 [7]),
.R(\cache[9][15]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\cache_reg[9][8]
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(\cache_reg[8]_1 [8]),
.Q(\cache_reg[9]_2 [8]),
.R(\cache[9][15]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\cache_reg[9][9]
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(\cache_reg[8]_1 [9]),
.Q(\cache_reg[9]_2 [9]),
.R(\cache[9][15]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair70" *)
LUT2 #(
.INIT(4'h8))
cache_reg_gate
(.I0(\cache_reg[3][15]_U0_cache_reg_r_1_n_0 ),
.I1(cache_reg_r_1_n_0),
.O(cache_reg_gate_n_0));
(* SOFT_HLUTNM = "soft_lutpair71" *)
LUT2 #(
.INIT(4'h8))
cache_reg_gate__0
(.I0(\cache_reg[3][14]_U0_cache_reg_r_1_n_0 ),
.I1(cache_reg_r_1_n_0),
.O(cache_reg_gate__0_n_0));
(* SOFT_HLUTNM = "soft_lutpair72" *)
LUT2 #(
.INIT(4'h8))
cache_reg_gate__1
(.I0(\cache_reg[3][13]_U0_cache_reg_r_1_n_0 ),
.I1(cache_reg_r_1_n_0),
.O(cache_reg_gate__1_n_0));
(* SOFT_HLUTNM = "soft_lutpair75" *)
LUT2 #(
.INIT(4'h8))
cache_reg_gate__10
(.I0(\cache_reg[3][4]_U0_cache_reg_r_1_n_0 ),
.I1(cache_reg_r_1_n_0),
.O(cache_reg_gate__10_n_0));
(* SOFT_HLUTNM = "soft_lutpair76" *)
LUT2 #(
.INIT(4'h8))
cache_reg_gate__11
(.I0(\cache_reg[3][3]_U0_cache_reg_r_1_n_0 ),
.I1(cache_reg_r_1_n_0),
.O(cache_reg_gate__11_n_0));
(* SOFT_HLUTNM = "soft_lutpair76" *)
LUT2 #(
.INIT(4'h8))
cache_reg_gate__12
(.I0(\cache_reg[3][2]_U0_cache_reg_r_1_n_0 ),
.I1(cache_reg_r_1_n_0),
.O(cache_reg_gate__12_n_0));
(* SOFT_HLUTNM = "soft_lutpair77" *)
LUT2 #(
.INIT(4'h8))
cache_reg_gate__13
(.I0(\cache_reg[3][1]_U0_cache_reg_r_1_n_0 ),
.I1(cache_reg_r_1_n_0),
.O(cache_reg_gate__13_n_0));
(* SOFT_HLUTNM = "soft_lutpair77" *)
LUT2 #(
.INIT(4'h8))
cache_reg_gate__14
(.I0(\cache_reg[3][0]_U0_cache_reg_r_1_n_0 ),
.I1(cache_reg_r_1_n_0),
.O(cache_reg_gate__14_n_0));
(* SOFT_HLUTNM = "soft_lutpair78" *)
LUT2 #(
.INIT(4'h8))
cache_reg_gate__15
(.I0(\cache_reg[7][15]_U0_cache_reg_r_1_n_0 ),
.I1(cache_reg_r_1_n_0),
.O(cache_reg_gate__15_n_0));
(* SOFT_HLUTNM = "soft_lutpair78" *)
LUT2 #(
.INIT(4'h8))
cache_reg_gate__16
(.I0(\cache_reg[7][14]_U0_cache_reg_r_1_n_0 ),
.I1(cache_reg_r_1_n_0),
.O(cache_reg_gate__16_n_0));
(* SOFT_HLUTNM = "soft_lutpair79" *)
LUT2 #(
.INIT(4'h8))
cache_reg_gate__17
(.I0(\cache_reg[7][13]_U0_cache_reg_r_1_n_0 ),
.I1(cache_reg_r_1_n_0),
.O(cache_reg_gate__17_n_0));
(* SOFT_HLUTNM = "soft_lutpair79" *)
LUT2 #(
.INIT(4'h8))
cache_reg_gate__18
(.I0(\cache_reg[7][12]_U0_cache_reg_r_1_n_0 ),
.I1(cache_reg_r_1_n_0),
.O(cache_reg_gate__18_n_0));
(* SOFT_HLUTNM = "soft_lutpair80" *)
LUT2 #(
.INIT(4'h8))
cache_reg_gate__19
(.I0(\cache_reg[7][11]_U0_cache_reg_r_1_n_0 ),
.I1(cache_reg_r_1_n_0),
.O(cache_reg_gate__19_n_0));
(* SOFT_HLUTNM = "soft_lutpair73" *)
LUT2 #(
.INIT(4'h8))
cache_reg_gate__2
(.I0(\cache_reg[3][12]_U0_cache_reg_r_1_n_0 ),
.I1(cache_reg_r_1_n_0),
.O(cache_reg_gate__2_n_0));
(* SOFT_HLUTNM = "soft_lutpair80" *)
LUT2 #(
.INIT(4'h8))
cache_reg_gate__20
(.I0(\cache_reg[7][10]_U0_cache_reg_r_1_n_0 ),
.I1(cache_reg_r_1_n_0),
.O(cache_reg_gate__20_n_0));
(* SOFT_HLUTNM = "soft_lutpair81" *)
LUT2 #(
.INIT(4'h8))
cache_reg_gate__21
(.I0(\cache_reg[7][9]_U0_cache_reg_r_1_n_0 ),
.I1(cache_reg_r_1_n_0),
.O(cache_reg_gate__21_n_0));
(* SOFT_HLUTNM = "soft_lutpair81" *)
LUT2 #(
.INIT(4'h8))
cache_reg_gate__22
(.I0(\cache_reg[7][8]_U0_cache_reg_r_1_n_0 ),
.I1(cache_reg_r_1_n_0),
.O(cache_reg_gate__22_n_0));
(* SOFT_HLUTNM = "soft_lutpair82" *)
LUT2 #(
.INIT(4'h8))
cache_reg_gate__23
(.I0(\cache_reg[7][7]_U0_cache_reg_r_1_n_0 ),
.I1(cache_reg_r_1_n_0),
.O(cache_reg_gate__23_n_0));
(* SOFT_HLUTNM = "soft_lutpair82" *)
LUT2 #(
.INIT(4'h8))
cache_reg_gate__24
(.I0(\cache_reg[7][6]_U0_cache_reg_r_1_n_0 ),
.I1(cache_reg_r_1_n_0),
.O(cache_reg_gate__24_n_0));
(* SOFT_HLUTNM = "soft_lutpair83" *)
LUT2 #(
.INIT(4'h8))
cache_reg_gate__25
(.I0(\cache_reg[7][5]_U0_cache_reg_r_1_n_0 ),
.I1(cache_reg_r_1_n_0),
.O(cache_reg_gate__25_n_0));
(* SOFT_HLUTNM = "soft_lutpair83" *)
LUT2 #(
.INIT(4'h8))
cache_reg_gate__26
(.I0(\cache_reg[7][4]_U0_cache_reg_r_1_n_0 ),
.I1(cache_reg_r_1_n_0),
.O(cache_reg_gate__26_n_0));
(* SOFT_HLUTNM = "soft_lutpair84" *)
LUT2 #(
.INIT(4'h8))
cache_reg_gate__27
(.I0(\cache_reg[7][3]_U0_cache_reg_r_1_n_0 ),
.I1(cache_reg_r_1_n_0),
.O(cache_reg_gate__27_n_0));
(* SOFT_HLUTNM = "soft_lutpair84" *)
LUT2 #(
.INIT(4'h8))
cache_reg_gate__28
(.I0(\cache_reg[7][2]_U0_cache_reg_r_1_n_0 ),
.I1(cache_reg_r_1_n_0),
.O(cache_reg_gate__28_n_0));
(* SOFT_HLUTNM = "soft_lutpair85" *)
LUT2 #(
.INIT(4'h8))
cache_reg_gate__29
(.I0(\cache_reg[7][1]_U0_cache_reg_r_1_n_0 ),
.I1(cache_reg_r_1_n_0),
.O(cache_reg_gate__29_n_0));
(* SOFT_HLUTNM = "soft_lutpair74" *)
LUT2 #(
.INIT(4'h8))
cache_reg_gate__3
(.I0(\cache_reg[3][11]_U0_cache_reg_r_1_n_0 ),
.I1(cache_reg_r_1_n_0),
.O(cache_reg_gate__3_n_0));
(* SOFT_HLUTNM = "soft_lutpair85" *)
LUT2 #(
.INIT(4'h8))
cache_reg_gate__30
(.I0(\cache_reg[7][0]_U0_cache_reg_r_1_n_0 ),
.I1(cache_reg_r_1_n_0),
.O(cache_reg_gate__30_n_0));
(* SOFT_HLUTNM = "soft_lutpair73" *)
LUT2 #(
.INIT(4'h8))
cache_reg_gate__4
(.I0(\cache_reg[3][10]_U0_cache_reg_r_1_n_0 ),
.I1(cache_reg_r_1_n_0),
.O(cache_reg_gate__4_n_0));
(* SOFT_HLUTNM = "soft_lutpair74" *)
LUT2 #(
.INIT(4'h8))
cache_reg_gate__5
(.I0(\cache_reg[3][9]_U0_cache_reg_r_1_n_0 ),
.I1(cache_reg_r_1_n_0),
.O(cache_reg_gate__5_n_0));
(* SOFT_HLUTNM = "soft_lutpair70" *)
LUT2 #(
.INIT(4'h8))
cache_reg_gate__6
(.I0(\cache_reg[3][8]_U0_cache_reg_r_1_n_0 ),
.I1(cache_reg_r_1_n_0),
.O(cache_reg_gate__6_n_0));
(* SOFT_HLUTNM = "soft_lutpair71" *)
LUT2 #(
.INIT(4'h8))
cache_reg_gate__7
(.I0(\cache_reg[3][7]_U0_cache_reg_r_1_n_0 ),
.I1(cache_reg_r_1_n_0),
.O(cache_reg_gate__7_n_0));
(* SOFT_HLUTNM = "soft_lutpair72" *)
LUT2 #(
.INIT(4'h8))
cache_reg_gate__8
(.I0(\cache_reg[3][6]_U0_cache_reg_r_1_n_0 ),
.I1(cache_reg_r_1_n_0),
.O(cache_reg_gate__8_n_0));
(* SOFT_HLUTNM = "soft_lutpair75" *)
LUT2 #(
.INIT(4'h8))
cache_reg_gate__9
(.I0(\cache_reg[3][5]_U0_cache_reg_r_1_n_0 ),
.I1(cache_reg_r_1_n_0),
.O(cache_reg_gate__9_n_0));
FDRE cache_reg_r
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(1'b1),
.Q(cache_reg_r_n_0),
.R(\cache[9][15]_i_1_n_0 ));
FDRE cache_reg_r_0
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(cache_reg_r_n_0),
.Q(cache_reg_r_0_n_0),
.R(\cache[9][15]_i_1_n_0 ));
FDRE cache_reg_r_1
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(cache_reg_r_0_n_0),
.Q(cache_reg_r_1_n_0),
.R(\cache[9][15]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFEFFFFF00200000))
\compute_addr_0[0]_i_1
(.I0(\x_reg_n_0_[0] ),
.I1(cycle[3]),
.I2(\cycle_reg[2]_rep_n_0 ),
.I3(cycle[0]),
.I4(\cycle_reg[1]_rep__0_n_0 ),
.I5(data1[0]),
.O(\compute_addr_0[0]_i_1_n_0 ));
LUT6 #(
.INIT(64'hBBBBBBBB88B8B888))
\compute_addr_0[10]_i_1
(.I0(data5[10]),
.I1(cycle[0]),
.I2(\compute_addr_2[10]_i_2_n_0 ),
.I3(cycle[2]),
.I4(\cycle_reg[1]_rep_n_0 ),
.I5(\compute_addr_0[10]_i_2_n_0 ),
.O(\compute_addr_0[10]_i_1_n_0 ));
LUT6 #(
.INIT(64'hCFC000000000FA0A))
\compute_addr_0[10]_i_2
(.I0(\y3_reg_n_0_[0] ),
.I1(data5[10]),
.I2(cycle[3]),
.I3(\y1_reg_n_0_[0] ),
.I4(cycle[2]),
.I5(\cycle_reg[1]_rep_n_0 ),
.O(\compute_addr_0[10]_i_2_n_0 ));
LUT6 #(
.INIT(64'hDDDDDDDDCDC88888))
\compute_addr_0[11]_i_1
(.I0(cycle[0]),
.I1(data5[11]),
.I2(cycle[3]),
.I3(\y1_reg_n_0_[1] ),
.I4(\compute_addr_0[11]_i_2_n_0 ),
.I5(\compute_addr_0[11]_i_3_n_0 ),
.O(\compute_addr_0[11]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT2 #(
.INIT(4'h8))
\compute_addr_0[11]_i_2
(.I0(cycle[2]),
.I1(\cycle_reg[1]_rep_n_0 ),
.O(\compute_addr_0[11]_i_2_n_0 ));
LUT6 #(
.INIT(64'h0000AAAAAAAACFC0))
\compute_addr_0[11]_i_3
(.I0(\compute_addr_2[11]_i_2_n_0 ),
.I1(\y1_reg_n_0_[1] ),
.I2(cycle[3]),
.I3(\y3_reg_n_0_[1] ),
.I4(cycle[2]),
.I5(\cycle_reg[1]_rep_n_0 ),
.O(\compute_addr_0[11]_i_3_n_0 ));
LUT6 #(
.INIT(64'hBBBBBBBB88B8B888))
\compute_addr_0[12]_i_1
(.I0(data5[12]),
.I1(cycle[0]),
.I2(\compute_addr_2[12]_i_2_n_0 ),
.I3(cycle[2]),
.I4(\cycle_reg[1]_rep_n_0 ),
.I5(\compute_addr_0[12]_i_2_n_0 ),
.O(\compute_addr_0[12]_i_1_n_0 ));
LUT6 #(
.INIT(64'hCFC000000000FA0A))
\compute_addr_0[12]_i_2
(.I0(\y3_reg_n_0_[2] ),
.I1(data5[12]),
.I2(cycle[3]),
.I3(\y1_reg_n_0_[2] ),
.I4(cycle[2]),
.I5(\cycle_reg[1]_rep_n_0 ),
.O(\compute_addr_0[12]_i_2_n_0 ));
LUT3 #(
.INIT(8'h08))
\compute_addr_0[13]_i_1
(.I0(rst),
.I1(active),
.I2(cycle[0]),
.O(compute_addr_0));
LUT6 #(
.INIT(64'hBBBBBBBB88B8B888))
\compute_addr_0[13]_i_2
(.I0(data5[13]),
.I1(cycle[0]),
.I2(\compute_addr_2[13]_i_4_n_0 ),
.I3(cycle[2]),
.I4(\cycle_reg[1]_rep_n_0 ),
.I5(\compute_addr_0[13]_i_3_n_0 ),
.O(\compute_addr_0[13]_i_2_n_0 ));
LUT6 #(
.INIT(64'hCFC000000000FA0A))
\compute_addr_0[13]_i_3
(.I0(\y3_reg_n_0_[3] ),
.I1(data5[13]),
.I2(cycle[3]),
.I3(\y1_reg_n_0_[3] ),
.I4(cycle[2]),
.I5(\cycle_reg[1]_rep_n_0 ),
.O(\compute_addr_0[13]_i_3_n_0 ));
LUT6 #(
.INIT(64'hFFEFFFFF00200000))
\compute_addr_0[1]_i_1
(.I0(\x_reg_n_0_[1] ),
.I1(cycle[3]),
.I2(\cycle_reg[2]_rep_n_0 ),
.I3(cycle[0]),
.I4(\cycle_reg[1]_rep__0_n_0 ),
.I5(data1[1]),
.O(\compute_addr_0[1]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFEFFFFF00200000))
\compute_addr_0[2]_i_1
(.I0(\x_reg_n_0_[2] ),
.I1(cycle[3]),
.I2(\cycle_reg[2]_rep_n_0 ),
.I3(cycle[0]),
.I4(\cycle_reg[1]_rep__0_n_0 ),
.I5(data1[2]),
.O(\compute_addr_0[2]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFEFFFFF00200000))
\compute_addr_0[3]_i_1
(.I0(\x_reg_n_0_[3] ),
.I1(cycle[3]),
.I2(\cycle_reg[2]_rep_n_0 ),
.I3(cycle[0]),
.I4(\cycle_reg[1]_rep__0_n_0 ),
.I5(data1[3]),
.O(\compute_addr_0[3]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFEFFFFF00200000))
\compute_addr_0[4]_i_1
(.I0(\x_reg_n_0_[4] ),
.I1(cycle[3]),
.I2(\cycle_reg[2]_rep_n_0 ),
.I3(cycle[0]),
.I4(\cycle_reg[1]_rep__0_n_0 ),
.I5(data1[4]),
.O(\compute_addr_0[4]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFEFFFFF00200000))
\compute_addr_0[5]_i_1
(.I0(\x_reg_n_0_[5] ),
.I1(cycle[3]),
.I2(\cycle_reg[2]_rep_n_0 ),
.I3(cycle[0]),
.I4(\cycle_reg[1]_rep__0_n_0 ),
.I5(data1[5]),
.O(\compute_addr_0[5]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFEFFFFF00200000))
\compute_addr_0[6]_i_1
(.I0(\x_reg_n_0_[6] ),
.I1(cycle[3]),
.I2(\cycle_reg[2]_rep_n_0 ),
.I3(cycle[0]),
.I4(\cycle_reg[1]_rep__0_n_0 ),
.I5(data1[6]),
.O(\compute_addr_0[6]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFEFFFFF00200000))
\compute_addr_0[7]_i_1
(.I0(\x_reg_n_0_[7] ),
.I1(cycle[3]),
.I2(\cycle_reg[2]_rep_n_0 ),
.I3(cycle[0]),
.I4(\cycle_reg[1]_rep__0_n_0 ),
.I5(data1[7]),
.O(\compute_addr_0[7]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFEFFFFF00200000))
\compute_addr_0[8]_i_1
(.I0(\x_reg_n_0_[8] ),
.I1(cycle[3]),
.I2(\cycle_reg[2]_rep_n_0 ),
.I3(cycle[0]),
.I4(\cycle_reg[1]_rep__0_n_0 ),
.I5(data1[8]),
.O(\compute_addr_0[8]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFEFFFFF00200000))
\compute_addr_0[9]_i_1
(.I0(\x_reg_n_0_[9] ),
.I1(cycle[3]),
.I2(\cycle_reg[2]_rep_n_0 ),
.I3(cycle[0]),
.I4(\cycle_reg[1]_rep_n_0 ),
.I5(data1[9]),
.O(\compute_addr_0[9]_i_1_n_0 ));
FDRE \compute_addr_0_reg[0]
(.C(clk_x16),
.CE(compute_addr_0),
.D(\compute_addr_0[0]_i_1_n_0 ),
.Q(\compute_addr_0_reg_n_0_[0] ),
.R(1'b0));
FDRE \compute_addr_0_reg[10]
(.C(clk_x16),
.CE(compute_addr_0),
.D(\compute_addr_0[10]_i_1_n_0 ),
.Q(\compute_addr_0_reg_n_0_[10] ),
.R(1'b0));
FDRE \compute_addr_0_reg[11]
(.C(clk_x16),
.CE(compute_addr_0),
.D(\compute_addr_0[11]_i_1_n_0 ),
.Q(\compute_addr_0_reg_n_0_[11] ),
.R(1'b0));
FDRE \compute_addr_0_reg[12]
(.C(clk_x16),
.CE(compute_addr_0),
.D(\compute_addr_0[12]_i_1_n_0 ),
.Q(\compute_addr_0_reg_n_0_[12] ),
.R(1'b0));
FDRE \compute_addr_0_reg[13]
(.C(clk_x16),
.CE(compute_addr_0),
.D(\compute_addr_0[13]_i_2_n_0 ),
.Q(\compute_addr_0_reg_n_0_[13] ),
.R(1'b0));
FDRE \compute_addr_0_reg[1]
(.C(clk_x16),
.CE(compute_addr_0),
.D(\compute_addr_0[1]_i_1_n_0 ),
.Q(\compute_addr_0_reg_n_0_[1] ),
.R(1'b0));
FDRE \compute_addr_0_reg[2]
(.C(clk_x16),
.CE(compute_addr_0),
.D(\compute_addr_0[2]_i_1_n_0 ),
.Q(\compute_addr_0_reg_n_0_[2] ),
.R(1'b0));
FDRE \compute_addr_0_reg[3]
(.C(clk_x16),
.CE(compute_addr_0),
.D(\compute_addr_0[3]_i_1_n_0 ),
.Q(\compute_addr_0_reg_n_0_[3] ),
.R(1'b0));
FDRE \compute_addr_0_reg[4]
(.C(clk_x16),
.CE(compute_addr_0),
.D(\compute_addr_0[4]_i_1_n_0 ),
.Q(\compute_addr_0_reg_n_0_[4] ),
.R(1'b0));
FDRE \compute_addr_0_reg[5]
(.C(clk_x16),
.CE(compute_addr_0),
.D(\compute_addr_0[5]_i_1_n_0 ),
.Q(\compute_addr_0_reg_n_0_[5] ),
.R(1'b0));
FDRE \compute_addr_0_reg[6]
(.C(clk_x16),
.CE(compute_addr_0),
.D(\compute_addr_0[6]_i_1_n_0 ),
.Q(\compute_addr_0_reg_n_0_[6] ),
.R(1'b0));
FDRE \compute_addr_0_reg[7]
(.C(clk_x16),
.CE(compute_addr_0),
.D(\compute_addr_0[7]_i_1_n_0 ),
.Q(\compute_addr_0_reg_n_0_[7] ),
.R(1'b0));
FDRE \compute_addr_0_reg[8]
(.C(clk_x16),
.CE(compute_addr_0),
.D(\compute_addr_0[8]_i_1_n_0 ),
.Q(\compute_addr_0_reg_n_0_[8] ),
.R(1'b0));
FDRE \compute_addr_0_reg[9]
(.C(clk_x16),
.CE(compute_addr_0),
.D(\compute_addr_0[9]_i_1_n_0 ),
.Q(\compute_addr_0_reg_n_0_[9] ),
.R(1'b0));
LUT6 #(
.INIT(64'hFFFFEBFF00002800))
\compute_addr_1[0]_i_1
(.I0(data1[0]),
.I1(\cycle_reg[1]_rep_n_0 ),
.I2(cycle[2]),
.I3(cycle[3]),
.I4(cycle[0]),
.I5(data2[0]),
.O(\compute_addr_1[0]_i_1_n_0 ));
LUT6 #(
.INIT(64'hBBBBBBBB88B8B888))
\compute_addr_1[10]_i_1
(.I0(data5[10]),
.I1(cycle[0]),
.I2(\compute_addr_3[10]_i_2_n_0 ),
.I3(cycle[2]),
.I4(\cycle_reg[1]_rep_n_0 ),
.I5(\compute_addr_1[10]_i_2_n_0 ),
.O(\compute_addr_1[10]_i_1_n_0 ));
LUT6 #(
.INIT(64'hACAC00000000CFC0))
\compute_addr_1[10]_i_2
(.I0(data5[10]),
.I1(data2[10]),
.I2(cycle[3]),
.I3(\y3_reg_n_0_[0] ),
.I4(cycle[2]),
.I5(\cycle_reg[1]_rep_n_0 ),
.O(\compute_addr_1[10]_i_2_n_0 ));
LUT6 #(
.INIT(64'hBBBBBBBB88B8B888))
\compute_addr_1[11]_i_1
(.I0(data5[11]),
.I1(cycle[0]),
.I2(\compute_addr_3[11]_i_2_n_0 ),
.I3(cycle[2]),
.I4(\cycle_reg[1]_rep_n_0 ),
.I5(\compute_addr_1[11]_i_2_n_0 ),
.O(\compute_addr_1[11]_i_1_n_0 ));
LUT6 #(
.INIT(64'hACAC00000000CFC0))
\compute_addr_1[11]_i_2
(.I0(data5[11]),
.I1(data2[11]),
.I2(cycle[3]),
.I3(\y3_reg_n_0_[1] ),
.I4(cycle[2]),
.I5(\cycle_reg[1]_rep_n_0 ),
.O(\compute_addr_1[11]_i_2_n_0 ));
LUT6 #(
.INIT(64'hBBBBBBBB88B8B888))
\compute_addr_1[12]_i_1
(.I0(data5[12]),
.I1(cycle[0]),
.I2(\compute_addr_3[12]_i_2_n_0 ),
.I3(cycle[2]),
.I4(\cycle_reg[1]_rep_n_0 ),
.I5(\compute_addr_1[12]_i_2_n_0 ),
.O(\compute_addr_1[12]_i_1_n_0 ));
LUT6 #(
.INIT(64'hACAC00000000CFC0))
\compute_addr_1[12]_i_2
(.I0(data5[12]),
.I1(data2[12]),
.I2(cycle[3]),
.I3(\y3_reg_n_0_[2] ),
.I4(cycle[2]),
.I5(\cycle_reg[1]_rep_n_0 ),
.O(\compute_addr_1[12]_i_2_n_0 ));
LUT6 #(
.INIT(64'hBBBBBBBB88B8B888))
\compute_addr_1[13]_i_1
(.I0(data5[13]),
.I1(cycle[0]),
.I2(\compute_addr_3[13]_i_2_n_0 ),
.I3(cycle[2]),
.I4(\cycle_reg[1]_rep_n_0 ),
.I5(\compute_addr_1[13]_i_2_n_0 ),
.O(\compute_addr_1[13]_i_1_n_0 ));
LUT6 #(
.INIT(64'hCFC000000000FA0A))
\compute_addr_1[13]_i_2
(.I0(\y3_reg_n_0_[3] ),
.I1(data5[13]),
.I2(cycle[3]),
.I3(data2[13]),
.I4(cycle[2]),
.I5(\cycle_reg[1]_rep_n_0 ),
.O(\compute_addr_1[13]_i_2_n_0 ));
LUT6 #(
.INIT(64'hFFFFEBFF00002800))
\compute_addr_1[1]_i_1
(.I0(data1[1]),
.I1(\cycle_reg[1]_rep_n_0 ),
.I2(cycle[2]),
.I3(cycle[3]),
.I4(cycle[0]),
.I5(data2[1]),
.O(\compute_addr_1[1]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFFFEBFF00002800))
\compute_addr_1[2]_i_1
(.I0(data1[2]),
.I1(\cycle_reg[1]_rep_n_0 ),
.I2(cycle[2]),
.I3(cycle[3]),
.I4(cycle[0]),
.I5(data2[2]),
.O(\compute_addr_1[2]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFFFEBFF00002800))
\compute_addr_1[3]_i_1
(.I0(data1[3]),
.I1(\cycle_reg[1]_rep_n_0 ),
.I2(cycle[2]),
.I3(cycle[3]),
.I4(cycle[0]),
.I5(data2[3]),
.O(\compute_addr_1[3]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFFFEBFF00002800))
\compute_addr_1[4]_i_1
(.I0(data1[4]),
.I1(\cycle_reg[1]_rep_n_0 ),
.I2(cycle[2]),
.I3(cycle[3]),
.I4(cycle[0]),
.I5(data2[4]),
.O(\compute_addr_1[4]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFFFEBFF00002800))
\compute_addr_1[5]_i_1
(.I0(data1[5]),
.I1(\cycle_reg[1]_rep_n_0 ),
.I2(cycle[2]),
.I3(cycle[3]),
.I4(cycle[0]),
.I5(data2[5]),
.O(\compute_addr_1[5]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFFFEBFF00002800))
\compute_addr_1[6]_i_1
(.I0(data1[6]),
.I1(\cycle_reg[1]_rep_n_0 ),
.I2(cycle[2]),
.I3(cycle[3]),
.I4(cycle[0]),
.I5(data2[6]),
.O(\compute_addr_1[6]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFFFEBFF00002800))
\compute_addr_1[7]_i_1
(.I0(data1[7]),
.I1(\cycle_reg[1]_rep_n_0 ),
.I2(cycle[2]),
.I3(cycle[3]),
.I4(cycle[0]),
.I5(data2[7]),
.O(\compute_addr_1[7]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFFFEBFF00002800))
\compute_addr_1[8]_i_1
(.I0(data1[8]),
.I1(\cycle_reg[1]_rep_n_0 ),
.I2(cycle[2]),
.I3(cycle[3]),
.I4(cycle[0]),
.I5(data2[8]),
.O(\compute_addr_1[8]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFFFEBFF00002800))
\compute_addr_1[9]_i_1
(.I0(data1[9]),
.I1(\cycle_reg[1]_rep_n_0 ),
.I2(cycle[2]),
.I3(cycle[3]),
.I4(cycle[0]),
.I5(data2[9]),
.O(\compute_addr_1[9]_i_1_n_0 ));
FDRE \compute_addr_1_reg[0]
(.C(clk_x16),
.CE(compute_addr_0),
.D(\compute_addr_1[0]_i_1_n_0 ),
.Q(compute_addr_1[0]),
.R(1'b0));
FDRE \compute_addr_1_reg[10]
(.C(clk_x16),
.CE(compute_addr_0),
.D(\compute_addr_1[10]_i_1_n_0 ),
.Q(compute_addr_1[10]),
.R(1'b0));
FDRE \compute_addr_1_reg[11]
(.C(clk_x16),
.CE(compute_addr_0),
.D(\compute_addr_1[11]_i_1_n_0 ),
.Q(compute_addr_1[11]),
.R(1'b0));
FDRE \compute_addr_1_reg[12]
(.C(clk_x16),
.CE(compute_addr_0),
.D(\compute_addr_1[12]_i_1_n_0 ),
.Q(compute_addr_1[12]),
.R(1'b0));
FDRE \compute_addr_1_reg[13]
(.C(clk_x16),
.CE(compute_addr_0),
.D(\compute_addr_1[13]_i_1_n_0 ),
.Q(compute_addr_1[13]),
.R(1'b0));
FDRE \compute_addr_1_reg[1]
(.C(clk_x16),
.CE(compute_addr_0),
.D(\compute_addr_1[1]_i_1_n_0 ),
.Q(compute_addr_1[1]),
.R(1'b0));
FDRE \compute_addr_1_reg[2]
(.C(clk_x16),
.CE(compute_addr_0),
.D(\compute_addr_1[2]_i_1_n_0 ),
.Q(compute_addr_1[2]),
.R(1'b0));
FDRE \compute_addr_1_reg[3]
(.C(clk_x16),
.CE(compute_addr_0),
.D(\compute_addr_1[3]_i_1_n_0 ),
.Q(compute_addr_1[3]),
.R(1'b0));
FDRE \compute_addr_1_reg[4]
(.C(clk_x16),
.CE(compute_addr_0),
.D(\compute_addr_1[4]_i_1_n_0 ),
.Q(compute_addr_1[4]),
.R(1'b0));
FDRE \compute_addr_1_reg[5]
(.C(clk_x16),
.CE(compute_addr_0),
.D(\compute_addr_1[5]_i_1_n_0 ),
.Q(compute_addr_1[5]),
.R(1'b0));
FDRE \compute_addr_1_reg[6]
(.C(clk_x16),
.CE(compute_addr_0),
.D(\compute_addr_1[6]_i_1_n_0 ),
.Q(compute_addr_1[6]),
.R(1'b0));
FDRE \compute_addr_1_reg[7]
(.C(clk_x16),
.CE(compute_addr_0),
.D(\compute_addr_1[7]_i_1_n_0 ),
.Q(compute_addr_1[7]),
.R(1'b0));
FDRE \compute_addr_1_reg[8]
(.C(clk_x16),
.CE(compute_addr_0),
.D(\compute_addr_1[8]_i_1_n_0 ),
.Q(compute_addr_1[8]),
.R(1'b0));
FDRE \compute_addr_1_reg[9]
(.C(clk_x16),
.CE(compute_addr_0),
.D(\compute_addr_1[9]_i_1_n_0 ),
.Q(compute_addr_1[9]),
.R(1'b0));
LUT6 #(
.INIT(64'hBBB8B8BB88B8B888))
\compute_addr_2[10]_i_1
(.I0(\y6_reg_n_0_[0] ),
.I1(\compute_addr_2[13]_i_3_n_0 ),
.I2(\compute_addr_2[10]_i_2_n_0 ),
.I3(cycle[2]),
.I4(\cycle_reg[1]_rep_n_0 ),
.I5(\y1_reg_n_0_[0] ),
.O(\compute_addr_2[10]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair58" *)
LUT3 #(
.INIT(8'hB8))
\compute_addr_2[10]_i_2
(.I0(\y2_reg_n_0_[0] ),
.I1(cycle[3]),
.I2(data1[10]),
.O(\compute_addr_2[10]_i_2_n_0 ));
LUT6 #(
.INIT(64'hBBB8B8BB88B8B888))
\compute_addr_2[11]_i_1
(.I0(\y6_reg_n_0_[1] ),
.I1(\compute_addr_2[13]_i_3_n_0 ),
.I2(\compute_addr_2[11]_i_2_n_0 ),
.I3(cycle[2]),
.I4(\cycle_reg[1]_rep_n_0 ),
.I5(\y1_reg_n_0_[1] ),
.O(\compute_addr_2[11]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair58" *)
LUT3 #(
.INIT(8'hB8))
\compute_addr_2[11]_i_2
(.I0(\y2_reg_n_0_[1] ),
.I1(cycle[3]),
.I2(data1[11]),
.O(\compute_addr_2[11]_i_2_n_0 ));
LUT6 #(
.INIT(64'hBBB8B8BB88B8B888))
\compute_addr_2[12]_i_1
(.I0(\y6_reg_n_0_[2] ),
.I1(\compute_addr_2[13]_i_3_n_0 ),
.I2(\compute_addr_2[12]_i_2_n_0 ),
.I3(cycle[2]),
.I4(\cycle_reg[1]_rep_n_0 ),
.I5(\y1_reg_n_0_[2] ),
.O(\compute_addr_2[12]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair57" *)
LUT3 #(
.INIT(8'hB8))
\compute_addr_2[12]_i_2
(.I0(\y2_reg_n_0_[2] ),
.I1(cycle[3]),
.I2(data1[12]),
.O(\compute_addr_2[12]_i_2_n_0 ));
LUT6 #(
.INIT(64'h8080808080808000))
\compute_addr_2[13]_i_1
(.I0(\cycle_reg[0]_rep_n_0 ),
.I1(active),
.I2(rst),
.I3(\cycle_reg[1]_rep_n_0 ),
.I4(cycle[3]),
.I5(cycle[2]),
.O(compute_addr_2));
LUT6 #(
.INIT(64'hBBB8B8BB88B8B888))
\compute_addr_2[13]_i_2
(.I0(\y6_reg_n_0_[3] ),
.I1(\compute_addr_2[13]_i_3_n_0 ),
.I2(\compute_addr_2[13]_i_4_n_0 ),
.I3(cycle[2]),
.I4(\cycle_reg[1]_rep_n_0 ),
.I5(\y1_reg_n_0_[3] ),
.O(\compute_addr_2[13]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair15" *)
LUT4 #(
.INIT(16'h81FF))
\compute_addr_2[13]_i_3
(.I0(cycle[3]),
.I1(cycle[2]),
.I2(\cycle_reg[1]_rep_n_0 ),
.I3(\cycle_reg[0]_rep_n_0 ),
.O(\compute_addr_2[13]_i_3_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair57" *)
LUT3 #(
.INIT(8'hB8))
\compute_addr_2[13]_i_4
(.I0(\y2_reg_n_0_[3] ),
.I1(cycle[3]),
.I2(data1[13]),
.O(\compute_addr_2[13]_i_4_n_0 ));
FDRE \compute_addr_2_reg[0]
(.C(clk_x16),
.CE(compute_addr_2),
.D(data1[0]),
.Q(\compute_addr_2_reg_n_0_[0] ),
.R(1'b0));
FDRE \compute_addr_2_reg[10]
(.C(clk_x16),
.CE(compute_addr_2),
.D(\compute_addr_2[10]_i_1_n_0 ),
.Q(\compute_addr_2_reg_n_0_[10] ),
.R(1'b0));
FDRE \compute_addr_2_reg[11]
(.C(clk_x16),
.CE(compute_addr_2),
.D(\compute_addr_2[11]_i_1_n_0 ),
.Q(\compute_addr_2_reg_n_0_[11] ),
.R(1'b0));
FDRE \compute_addr_2_reg[12]
(.C(clk_x16),
.CE(compute_addr_2),
.D(\compute_addr_2[12]_i_1_n_0 ),
.Q(\compute_addr_2_reg_n_0_[12] ),
.R(1'b0));
FDRE \compute_addr_2_reg[13]
(.C(clk_x16),
.CE(compute_addr_2),
.D(\compute_addr_2[13]_i_2_n_0 ),
.Q(\compute_addr_2_reg_n_0_[13] ),
.R(1'b0));
FDRE \compute_addr_2_reg[1]
(.C(clk_x16),
.CE(compute_addr_2),
.D(data1[1]),
.Q(\compute_addr_2_reg_n_0_[1] ),
.R(1'b0));
FDRE \compute_addr_2_reg[2]
(.C(clk_x16),
.CE(compute_addr_2),
.D(data1[2]),
.Q(\compute_addr_2_reg_n_0_[2] ),
.R(1'b0));
FDRE \compute_addr_2_reg[3]
(.C(clk_x16),
.CE(compute_addr_2),
.D(data1[3]),
.Q(\compute_addr_2_reg_n_0_[3] ),
.R(1'b0));
FDRE \compute_addr_2_reg[4]
(.C(clk_x16),
.CE(compute_addr_2),
.D(data1[4]),
.Q(\compute_addr_2_reg_n_0_[4] ),
.R(1'b0));
FDRE \compute_addr_2_reg[5]
(.C(clk_x16),
.CE(compute_addr_2),
.D(data1[5]),
.Q(\compute_addr_2_reg_n_0_[5] ),
.R(1'b0));
FDRE \compute_addr_2_reg[6]
(.C(clk_x16),
.CE(compute_addr_2),
.D(data1[6]),
.Q(\compute_addr_2_reg_n_0_[6] ),
.R(1'b0));
FDRE \compute_addr_2_reg[7]
(.C(clk_x16),
.CE(compute_addr_2),
.D(data1[7]),
.Q(\compute_addr_2_reg_n_0_[7] ),
.R(1'b0));
FDRE \compute_addr_2_reg[8]
(.C(clk_x16),
.CE(compute_addr_2),
.D(data1[8]),
.Q(\compute_addr_2_reg_n_0_[8] ),
.R(1'b0));
FDRE \compute_addr_2_reg[9]
(.C(clk_x16),
.CE(compute_addr_2),
.D(data1[9]),
.Q(\compute_addr_2_reg_n_0_[9] ),
.R(1'b0));
LUT6 #(
.INIT(64'hFFBFBFFF00808000))
\compute_addr_3[0]_i_1
(.I0(data1[0]),
.I1(\cycle_reg[0]_rep_n_0 ),
.I2(cycle[3]),
.I3(\cycle_reg[1]_rep_n_0 ),
.I4(cycle[2]),
.I5(data2[0]),
.O(\compute_addr_3[0]_i_1_n_0 ));
LUT6 #(
.INIT(64'hBBB8B8BB88B8B888))
\compute_addr_3[10]_i_1
(.I0(\y6_reg_n_0_[0] ),
.I1(\compute_addr_2[13]_i_3_n_0 ),
.I2(\compute_addr_3[10]_i_2_n_0 ),
.I3(cycle[2]),
.I4(\cycle_reg[1]_rep_n_0 ),
.I5(data2[10]),
.O(\compute_addr_3[10]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair67" *)
LUT3 #(
.INIT(8'hB8))
\compute_addr_3[10]_i_2
(.I0(y7[0]),
.I1(cycle[3]),
.I2(y8[0]),
.O(\compute_addr_3[10]_i_2_n_0 ));
LUT6 #(
.INIT(64'hBBB8B8BB88B8B888))
\compute_addr_3[11]_i_1
(.I0(\y6_reg_n_0_[1] ),
.I1(\compute_addr_2[13]_i_3_n_0 ),
.I2(\compute_addr_3[11]_i_2_n_0 ),
.I3(cycle[2]),
.I4(\cycle_reg[1]_rep_n_0 ),
.I5(data2[11]),
.O(\compute_addr_3[11]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair67" *)
LUT3 #(
.INIT(8'hB8))
\compute_addr_3[11]_i_2
(.I0(y7[1]),
.I1(cycle[3]),
.I2(y8[1]),
.O(\compute_addr_3[11]_i_2_n_0 ));
LUT6 #(
.INIT(64'hBBB8B8BB88B8B888))
\compute_addr_3[12]_i_1
(.I0(\y6_reg_n_0_[2] ),
.I1(\compute_addr_2[13]_i_3_n_0 ),
.I2(\compute_addr_3[12]_i_2_n_0 ),
.I3(cycle[2]),
.I4(\cycle_reg[1]_rep_n_0 ),
.I5(data2[12]),
.O(\compute_addr_3[12]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair66" *)
LUT3 #(
.INIT(8'hB8))
\compute_addr_3[12]_i_2
(.I0(y7[2]),
.I1(cycle[3]),
.I2(y8[2]),
.O(\compute_addr_3[12]_i_2_n_0 ));
LUT6 #(
.INIT(64'hBBB8B8BB88B8B888))
\compute_addr_3[13]_i_1
(.I0(\y6_reg_n_0_[3] ),
.I1(\compute_addr_2[13]_i_3_n_0 ),
.I2(\compute_addr_3[13]_i_2_n_0 ),
.I3(cycle[2]),
.I4(\cycle_reg[1]_rep_n_0 ),
.I5(data2[13]),
.O(\compute_addr_3[13]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair66" *)
LUT3 #(
.INIT(8'hB8))
\compute_addr_3[13]_i_2
(.I0(y7[3]),
.I1(cycle[3]),
.I2(y8[3]),
.O(\compute_addr_3[13]_i_2_n_0 ));
LUT6 #(
.INIT(64'hFFBFBFFF00808000))
\compute_addr_3[1]_i_1
(.I0(data1[1]),
.I1(\cycle_reg[0]_rep_n_0 ),
.I2(cycle[3]),
.I3(\cycle_reg[1]_rep_n_0 ),
.I4(cycle[2]),
.I5(data2[1]),
.O(\compute_addr_3[1]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFBFBFFF00808000))
\compute_addr_3[2]_i_1
(.I0(data1[2]),
.I1(\cycle_reg[0]_rep_n_0 ),
.I2(cycle[3]),
.I3(\cycle_reg[1]_rep_n_0 ),
.I4(cycle[2]),
.I5(data2[2]),
.O(\compute_addr_3[2]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFBFBFFF00808000))
\compute_addr_3[3]_i_1
(.I0(data1[3]),
.I1(\cycle_reg[0]_rep_n_0 ),
.I2(cycle[3]),
.I3(\cycle_reg[1]_rep_n_0 ),
.I4(cycle[2]),
.I5(data2[3]),
.O(\compute_addr_3[3]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFBFBFFF00808000))
\compute_addr_3[4]_i_1
(.I0(data1[4]),
.I1(\cycle_reg[0]_rep_n_0 ),
.I2(cycle[3]),
.I3(\cycle_reg[1]_rep_n_0 ),
.I4(cycle[2]),
.I5(data2[4]),
.O(\compute_addr_3[4]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFBFBFFF00808000))
\compute_addr_3[5]_i_1
(.I0(data1[5]),
.I1(\cycle_reg[0]_rep_n_0 ),
.I2(cycle[3]),
.I3(\cycle_reg[1]_rep_n_0 ),
.I4(cycle[2]),
.I5(data2[5]),
.O(\compute_addr_3[5]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFBFBFFF00808000))
\compute_addr_3[6]_i_1
(.I0(data1[6]),
.I1(\cycle_reg[0]_rep_n_0 ),
.I2(cycle[3]),
.I3(\cycle_reg[1]_rep_n_0 ),
.I4(cycle[2]),
.I5(data2[6]),
.O(\compute_addr_3[6]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFBFBFFF00808000))
\compute_addr_3[7]_i_1
(.I0(data1[7]),
.I1(\cycle_reg[0]_rep_n_0 ),
.I2(cycle[3]),
.I3(\cycle_reg[1]_rep_n_0 ),
.I4(cycle[2]),
.I5(data2[7]),
.O(\compute_addr_3[7]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFBFBFFF00808000))
\compute_addr_3[8]_i_1
(.I0(data1[8]),
.I1(\cycle_reg[0]_rep_n_0 ),
.I2(cycle[3]),
.I3(\cycle_reg[1]_rep_n_0 ),
.I4(cycle[2]),
.I5(data2[8]),
.O(\compute_addr_3[8]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFBFBFFF00808000))
\compute_addr_3[9]_i_1
(.I0(data1[9]),
.I1(\cycle_reg[0]_rep_n_0 ),
.I2(cycle[3]),
.I3(\cycle_reg[1]_rep_n_0 ),
.I4(cycle[2]),
.I5(data2[9]),
.O(\compute_addr_3[9]_i_1_n_0 ));
FDRE \compute_addr_3_reg[0]
(.C(clk_x16),
.CE(compute_addr_2),
.D(\compute_addr_3[0]_i_1_n_0 ),
.Q(compute_addr_3[0]),
.R(1'b0));
FDRE \compute_addr_3_reg[10]
(.C(clk_x16),
.CE(compute_addr_2),
.D(\compute_addr_3[10]_i_1_n_0 ),
.Q(compute_addr_3[10]),
.R(1'b0));
FDRE \compute_addr_3_reg[11]
(.C(clk_x16),
.CE(compute_addr_2),
.D(\compute_addr_3[11]_i_1_n_0 ),
.Q(compute_addr_3[11]),
.R(1'b0));
FDRE \compute_addr_3_reg[12]
(.C(clk_x16),
.CE(compute_addr_2),
.D(\compute_addr_3[12]_i_1_n_0 ),
.Q(compute_addr_3[12]),
.R(1'b0));
FDRE \compute_addr_3_reg[13]
(.C(clk_x16),
.CE(compute_addr_2),
.D(\compute_addr_3[13]_i_1_n_0 ),
.Q(compute_addr_3[13]),
.R(1'b0));
FDRE \compute_addr_3_reg[1]
(.C(clk_x16),
.CE(compute_addr_2),
.D(\compute_addr_3[1]_i_1_n_0 ),
.Q(compute_addr_3[1]),
.R(1'b0));
FDRE \compute_addr_3_reg[2]
(.C(clk_x16),
.CE(compute_addr_2),
.D(\compute_addr_3[2]_i_1_n_0 ),
.Q(compute_addr_3[2]),
.R(1'b0));
FDRE \compute_addr_3_reg[3]
(.C(clk_x16),
.CE(compute_addr_2),
.D(\compute_addr_3[3]_i_1_n_0 ),
.Q(compute_addr_3[3]),
.R(1'b0));
FDRE \compute_addr_3_reg[4]
(.C(clk_x16),
.CE(compute_addr_2),
.D(\compute_addr_3[4]_i_1_n_0 ),
.Q(compute_addr_3[4]),
.R(1'b0));
FDRE \compute_addr_3_reg[5]
(.C(clk_x16),
.CE(compute_addr_2),
.D(\compute_addr_3[5]_i_1_n_0 ),
.Q(compute_addr_3[5]),
.R(1'b0));
FDRE \compute_addr_3_reg[6]
(.C(clk_x16),
.CE(compute_addr_2),
.D(\compute_addr_3[6]_i_1_n_0 ),
.Q(compute_addr_3[6]),
.R(1'b0));
FDRE \compute_addr_3_reg[7]
(.C(clk_x16),
.CE(compute_addr_2),
.D(\compute_addr_3[7]_i_1_n_0 ),
.Q(compute_addr_3[7]),
.R(1'b0));
FDRE \compute_addr_3_reg[8]
(.C(clk_x16),
.CE(compute_addr_2),
.D(\compute_addr_3[8]_i_1_n_0 ),
.Q(compute_addr_3[8]),
.R(1'b0));
FDRE \compute_addr_3_reg[9]
(.C(clk_x16),
.CE(compute_addr_2),
.D(\compute_addr_3[9]_i_1_n_0 ),
.Q(compute_addr_3[9]),
.R(1'b0));
LUT6 #(
.INIT(64'hFFFFFFFF00000008))
\corner[15]_i_1
(.I0(\left[15]_i_2_n_0 ),
.I1(x),
.I2(\x_reg_n_0_[0] ),
.I3(\x_reg_n_0_[9] ),
.I4(\x_reg_n_0_[8] ),
.I5(top),
.O(corner));
FDRE #(
.INIT(1'b0))
\corner_reg[0]
(.C(clk_x16),
.CE(x),
.D(\cache_reg[10]_3 [0]),
.Q(\corner_reg_n_0_[0] ),
.R(corner));
FDRE #(
.INIT(1'b0))
\corner_reg[10]
(.C(clk_x16),
.CE(x),
.D(\cache_reg[10]_3 [10]),
.Q(\corner_reg_n_0_[10] ),
.R(corner));
FDRE #(
.INIT(1'b0))
\corner_reg[11]
(.C(clk_x16),
.CE(x),
.D(\cache_reg[10]_3 [11]),
.Q(\corner_reg_n_0_[11] ),
.R(corner));
FDRE #(
.INIT(1'b0))
\corner_reg[12]
(.C(clk_x16),
.CE(x),
.D(\cache_reg[10]_3 [12]),
.Q(\corner_reg_n_0_[12] ),
.R(corner));
FDRE #(
.INIT(1'b0))
\corner_reg[13]
(.C(clk_x16),
.CE(x),
.D(\cache_reg[10]_3 [13]),
.Q(\corner_reg_n_0_[13] ),
.R(corner));
FDRE #(
.INIT(1'b0))
\corner_reg[14]
(.C(clk_x16),
.CE(x),
.D(\cache_reg[10]_3 [14]),
.Q(\corner_reg_n_0_[14] ),
.R(corner));
FDRE #(
.INIT(1'b0))
\corner_reg[15]
(.C(clk_x16),
.CE(x),
.D(\cache_reg[10]_3 [15]),
.Q(\corner_reg_n_0_[15] ),
.R(corner));
FDRE #(
.INIT(1'b0))
\corner_reg[1]
(.C(clk_x16),
.CE(x),
.D(\cache_reg[10]_3 [1]),
.Q(\corner_reg_n_0_[1] ),
.R(corner));
FDRE #(
.INIT(1'b0))
\corner_reg[2]
(.C(clk_x16),
.CE(x),
.D(\cache_reg[10]_3 [2]),
.Q(\corner_reg_n_0_[2] ),
.R(corner));
FDRE #(
.INIT(1'b0))
\corner_reg[3]
(.C(clk_x16),
.CE(x),
.D(\cache_reg[10]_3 [3]),
.Q(\corner_reg_n_0_[3] ),
.R(corner));
FDRE #(
.INIT(1'b0))
\corner_reg[4]
(.C(clk_x16),
.CE(x),
.D(\cache_reg[10]_3 [4]),
.Q(\corner_reg_n_0_[4] ),
.R(corner));
FDRE #(
.INIT(1'b0))
\corner_reg[5]
(.C(clk_x16),
.CE(x),
.D(\cache_reg[10]_3 [5]),
.Q(\corner_reg_n_0_[5] ),
.R(corner));
FDRE #(
.INIT(1'b0))
\corner_reg[6]
(.C(clk_x16),
.CE(x),
.D(\cache_reg[10]_3 [6]),
.Q(\corner_reg_n_0_[6] ),
.R(corner));
FDRE #(
.INIT(1'b0))
\corner_reg[7]
(.C(clk_x16),
.CE(x),
.D(\cache_reg[10]_3 [7]),
.Q(\corner_reg_n_0_[7] ),
.R(corner));
FDRE #(
.INIT(1'b0))
\corner_reg[8]
(.C(clk_x16),
.CE(x),
.D(\cache_reg[10]_3 [8]),
.Q(\corner_reg_n_0_[8] ),
.R(corner));
FDRE #(
.INIT(1'b0))
\corner_reg[9]
(.C(clk_x16),
.CE(x),
.D(\cache_reg[10]_3 [9]),
.Q(\corner_reg_n_0_[9] ),
.R(corner));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT1 #(
.INIT(2'h1))
\cycle[0]_i_1
(.I0(cycle[0]),
.O(\cycle[0]_i_1_n_0 ));
LUT1 #(
.INIT(2'h1))
\cycle[0]_rep_i_1
(.I0(cycle[0]),
.O(\cycle[0]_rep_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair31" *)
LUT2 #(
.INIT(4'h6))
\cycle[1]_i_1
(.I0(cycle[1]),
.I1(cycle[0]),
.O(\cycle[1]_i_1_n_0 ));
LUT2 #(
.INIT(4'h6))
\cycle[1]_rep_i_1
(.I0(cycle[1]),
.I1(cycle[0]),
.O(\cycle[1]_rep_i_1_n_0 ));
LUT2 #(
.INIT(4'h6))
\cycle[1]_rep_i_1__0
(.I0(cycle[1]),
.I1(cycle[0]),
.O(\cycle[1]_rep_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair31" *)
LUT3 #(
.INIT(8'h78))
\cycle[2]_i_1
(.I0(cycle[1]),
.I1(\cycle_reg[0]_rep_n_0 ),
.I2(cycle[2]),
.O(\cycle[2]_i_1_n_0 ));
LUT3 #(
.INIT(8'h78))
\cycle[2]_rep_i_1
(.I0(\cycle_reg[1]_rep_n_0 ),
.I1(cycle[0]),
.I2(cycle[2]),
.O(\cycle[2]_rep_i_1_n_0 ));
LUT2 #(
.INIT(4'h7))
\cycle[3]_i_1
(.I0(rst),
.I1(active),
.O(\cycle[3]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair15" *)
LUT4 #(
.INIT(16'h6AAA))
\cycle[3]_i_2
(.I0(cycle[3]),
.I1(cycle[2]),
.I2(cycle[1]),
.I3(\cycle_reg[0]_rep_n_0 ),
.O(\cycle[3]_i_2_n_0 ));
(* ORIG_CELL_NAME = "cycle_reg[0]" *)
FDRE #(
.INIT(1'b0))
\cycle_reg[0]
(.C(clk_x16),
.CE(1'b1),
.D(\cycle[0]_i_1_n_0 ),
.Q(cycle[0]),
.R(\cycle[3]_i_1_n_0 ));
(* ORIG_CELL_NAME = "cycle_reg[0]" *)
FDRE #(
.INIT(1'b0))
\cycle_reg[0]_rep
(.C(clk_x16),
.CE(1'b1),
.D(\cycle[0]_rep_i_1_n_0 ),
.Q(\cycle_reg[0]_rep_n_0 ),
.R(\cycle[3]_i_1_n_0 ));
(* ORIG_CELL_NAME = "cycle_reg[1]" *)
FDRE #(
.INIT(1'b0))
\cycle_reg[1]
(.C(clk_x16),
.CE(1'b1),
.D(\cycle[1]_i_1_n_0 ),
.Q(cycle[1]),
.R(\cycle[3]_i_1_n_0 ));
(* ORIG_CELL_NAME = "cycle_reg[1]" *)
FDRE #(
.INIT(1'b0))
\cycle_reg[1]_rep
(.C(clk_x16),
.CE(1'b1),
.D(\cycle[1]_rep_i_1_n_0 ),
.Q(\cycle_reg[1]_rep_n_0 ),
.R(\cycle[3]_i_1_n_0 ));
(* ORIG_CELL_NAME = "cycle_reg[1]" *)
FDRE #(
.INIT(1'b0))
\cycle_reg[1]_rep__0
(.C(clk_x16),
.CE(1'b1),
.D(\cycle[1]_rep_i_1__0_n_0 ),
.Q(\cycle_reg[1]_rep__0_n_0 ),
.R(\cycle[3]_i_1_n_0 ));
(* ORIG_CELL_NAME = "cycle_reg[2]" *)
FDRE #(
.INIT(1'b0))
\cycle_reg[2]
(.C(clk_x16),
.CE(1'b1),
.D(\cycle[2]_i_1_n_0 ),
.Q(cycle[2]),
.R(\cycle[3]_i_1_n_0 ));
(* ORIG_CELL_NAME = "cycle_reg[2]" *)
FDRE #(
.INIT(1'b0))
\cycle_reg[2]_rep
(.C(clk_x16),
.CE(1'b1),
.D(\cycle[2]_rep_i_1_n_0 ),
.Q(\cycle_reg[2]_rep_n_0 ),
.R(\cycle[3]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\cycle_reg[3]
(.C(clk_x16),
.CE(1'b1),
.D(\cycle[3]_i_2_n_0 ),
.Q(cycle[3]),
.R(\cycle[3]_i_1_n_0 ));
DSP48E1 #(
.ACASCREG(1),
.ADREG(1),
.ALUMODEREG(0),
.AREG(1),
.AUTORESET_PATDET("NO_RESET"),
.A_INPUT("DIRECT"),
.BCASCREG(1),
.BREG(1),
.B_INPUT("DIRECT"),
.CARRYINREG(0),
.CARRYINSELREG(0),
.CREG(1),
.DREG(1),
.INMODEREG(0),
.MASK(48'h3FFFFFFFFFFF),
.MREG(1),
.OPMODEREG(0),
.PATTERN(48'h000000000000),
.PREG(0),
.SEL_MASK("MASK"),
.SEL_PATTERN("PATTERN"),
.USE_DPORT("FALSE"),
.USE_MULT("MULTIPLY"),
.USE_PATTERN_DETECT("NO_PATDET"),
.USE_SIMD("ONE48"))
det_0_reg
(.A({A[15],A[15],A[15],A[15],A[15],A[15],A[15],A[15],A[15],A[15],A[15],A[15],A[15],A[15],A}),
.ACIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.ACOUT(NLW_det_0_reg_ACOUT_UNCONNECTED[29:0]),
.ALUMODE({1'b0,1'b0,1'b0,1'b0}),
.B({B[15],B[15],B}),
.BCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.BCOUT(NLW_det_0_reg_BCOUT_UNCONNECTED[17:0]),
.C({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
.CARRYCASCIN(1'b0),
.CARRYCASCOUT(NLW_det_0_reg_CARRYCASCOUT_UNCONNECTED),
.CARRYIN(1'b0),
.CARRYINSEL({1'b0,1'b0,1'b0}),
.CARRYOUT(NLW_det_0_reg_CARRYOUT_UNCONNECTED[3:0]),
.CEA1(1'b0),
.CEA2(Lxx),
.CEAD(1'b0),
.CEALUMODE(1'b0),
.CEB1(1'b0),
.CEB2(det_0_reg_i_2_n_0),
.CEC(1'b0),
.CECARRYIN(1'b0),
.CECTRL(1'b0),
.CED(1'b0),
.CEINMODE(1'b0),
.CEM(det_0),
.CEP(1'b0),
.CLK(clk_x16),
.D({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.INMODE({1'b0,1'b0,1'b0,1'b0,1'b0}),
.MULTSIGNIN(1'b0),
.MULTSIGNOUT(NLW_det_0_reg_MULTSIGNOUT_UNCONNECTED),
.OPMODE({1'b0,1'b0,1'b0,1'b0,1'b1,1'b0,1'b1}),
.OVERFLOW(NLW_det_0_reg_OVERFLOW_UNCONNECTED),
.P(NLW_det_0_reg_P_UNCONNECTED[47:0]),
.PATTERNBDETECT(NLW_det_0_reg_PATTERNBDETECT_UNCONNECTED),
.PATTERNDETECT(NLW_det_0_reg_PATTERNDETECT_UNCONNECTED),
.PCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.PCOUT({det_0_reg_n_106,det_0_reg_n_107,det_0_reg_n_108,det_0_reg_n_109,det_0_reg_n_110,det_0_reg_n_111,det_0_reg_n_112,det_0_reg_n_113,det_0_reg_n_114,det_0_reg_n_115,det_0_reg_n_116,det_0_reg_n_117,det_0_reg_n_118,det_0_reg_n_119,det_0_reg_n_120,det_0_reg_n_121,det_0_reg_n_122,det_0_reg_n_123,det_0_reg_n_124,det_0_reg_n_125,det_0_reg_n_126,det_0_reg_n_127,det_0_reg_n_128,det_0_reg_n_129,det_0_reg_n_130,det_0_reg_n_131,det_0_reg_n_132,det_0_reg_n_133,det_0_reg_n_134,det_0_reg_n_135,det_0_reg_n_136,det_0_reg_n_137,det_0_reg_n_138,det_0_reg_n_139,det_0_reg_n_140,det_0_reg_n_141,det_0_reg_n_142,det_0_reg_n_143,det_0_reg_n_144,det_0_reg_n_145,det_0_reg_n_146,det_0_reg_n_147,det_0_reg_n_148,det_0_reg_n_149,det_0_reg_n_150,det_0_reg_n_151,det_0_reg_n_152,det_0_reg_n_153}),
.RSTA(1'b0),
.RSTALLCARRYIN(1'b0),
.RSTALUMODE(1'b0),
.RSTB(1'b0),
.RSTC(1'b0),
.RSTCTRL(1'b0),
.RSTD(1'b0),
.RSTINMODE(1'b0),
.RSTM(1'b0),
.RSTP(1'b0),
.UNDERFLOW(NLW_det_0_reg_UNDERFLOW_UNCONNECTED));
LUT6 #(
.INIT(64'h0000000000008000))
det_0_reg_i_1
(.I0(\cycle_reg[0]_rep_n_0 ),
.I1(active),
.I2(rst),
.I3(\cycle_reg[1]_rep__0_n_0 ),
.I4(cycle[2]),
.I5(cycle[3]),
.O(Lxx));
LUT6 #(
.INIT(64'h2000000000000000))
det_0_reg_i_2
(.I0(cycle[2]),
.I1(cycle[3]),
.I2(\cycle_reg[1]_rep__0_n_0 ),
.I3(\cycle_reg[0]_rep_n_0 ),
.I4(rst),
.I5(active),
.O(det_0_reg_i_2_n_0));
LUT6 #(
.INIT(64'h0000000008000000))
det_0_reg_i_3
(.I0(cycle[2]),
.I1(cycle[3]),
.I2(cycle[1]),
.I3(rst),
.I4(active),
.I5(\cycle_reg[0]_rep_n_0 ),
.O(det_0));
(* SOFT_HLUTNM = "soft_lutpair44" *)
LUT3 #(
.INIT(8'hAC))
\det_abs[10]_i_1
(.I0(det_abs0[10]),
.I1(det_reg_n_95),
.I2(det_reg_n_74),
.O(\det_abs[10]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair45" *)
LUT3 #(
.INIT(8'hAC))
\det_abs[11]_i_1
(.I0(det_abs0[11]),
.I1(det_reg_n_94),
.I2(det_reg_n_74),
.O(\det_abs[11]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair46" *)
LUT3 #(
.INIT(8'hAC))
\det_abs[12]_i_1
(.I0(det_abs0[12]),
.I1(det_reg_n_93),
.I2(det_reg_n_74),
.O(\det_abs[12]_i_1_n_0 ));
LUT1 #(
.INIT(2'h1))
\det_abs[12]_i_3
(.I0(det_reg_n_93),
.O(\det_abs[12]_i_3_n_0 ));
LUT1 #(
.INIT(2'h1))
\det_abs[12]_i_4
(.I0(det_reg_n_94),
.O(\det_abs[12]_i_4_n_0 ));
LUT1 #(
.INIT(2'h1))
\det_abs[12]_i_5
(.I0(det_reg_n_95),
.O(\det_abs[12]_i_5_n_0 ));
LUT1 #(
.INIT(2'h1))
\det_abs[12]_i_6
(.I0(det_reg_n_96),
.O(\det_abs[12]_i_6_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair47" *)
LUT3 #(
.INIT(8'hAC))
\det_abs[13]_i_1
(.I0(det_abs0[13]),
.I1(det_reg_n_92),
.I2(det_reg_n_74),
.O(\det_abs[13]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair48" *)
LUT3 #(
.INIT(8'hAC))
\det_abs[14]_i_1
(.I0(det_abs0[14]),
.I1(det_reg_n_91),
.I2(det_reg_n_74),
.O(\det_abs[14]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair47" *)
LUT3 #(
.INIT(8'hAC))
\det_abs[15]_i_1
(.I0(det_abs0[15]),
.I1(det_reg_n_90),
.I2(det_reg_n_74),
.O(\det_abs[15]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair46" *)
LUT3 #(
.INIT(8'hAC))
\det_abs[16]_i_1
(.I0(det_abs0[16]),
.I1(det_reg_n_89),
.I2(det_reg_n_74),
.O(\det_abs[16]_i_1_n_0 ));
LUT1 #(
.INIT(2'h1))
\det_abs[16]_i_3
(.I0(det_reg_n_89),
.O(\det_abs[16]_i_3_n_0 ));
LUT1 #(
.INIT(2'h1))
\det_abs[16]_i_4
(.I0(det_reg_n_90),
.O(\det_abs[16]_i_4_n_0 ));
LUT1 #(
.INIT(2'h1))
\det_abs[16]_i_5
(.I0(det_reg_n_91),
.O(\det_abs[16]_i_5_n_0 ));
LUT1 #(
.INIT(2'h1))
\det_abs[16]_i_6
(.I0(det_reg_n_92),
.O(\det_abs[16]_i_6_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair45" *)
LUT3 #(
.INIT(8'hAC))
\det_abs[17]_i_1
(.I0(det_abs0[17]),
.I1(det_reg_n_88),
.I2(det_reg_n_74),
.O(\det_abs[17]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair44" *)
LUT3 #(
.INIT(8'hAC))
\det_abs[18]_i_1
(.I0(det_abs0[18]),
.I1(det_reg_n_87),
.I2(det_reg_n_74),
.O(\det_abs[18]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair43" *)
LUT3 #(
.INIT(8'hAC))
\det_abs[19]_i_1
(.I0(det_abs0[19]),
.I1(det_reg_n_86),
.I2(det_reg_n_74),
.O(\det_abs[19]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair27" *)
LUT3 #(
.INIT(8'hAC))
\det_abs[1]_i_1
(.I0(det_abs0[1]),
.I1(det_reg_n_104),
.I2(det_reg_n_74),
.O(\det_abs[1]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair42" *)
LUT3 #(
.INIT(8'hAC))
\det_abs[20]_i_1
(.I0(det_abs0[20]),
.I1(det_reg_n_85),
.I2(det_reg_n_74),
.O(\det_abs[20]_i_1_n_0 ));
LUT1 #(
.INIT(2'h1))
\det_abs[20]_i_3
(.I0(det_reg_n_85),
.O(\det_abs[20]_i_3_n_0 ));
LUT1 #(
.INIT(2'h1))
\det_abs[20]_i_4
(.I0(det_reg_n_86),
.O(\det_abs[20]_i_4_n_0 ));
LUT1 #(
.INIT(2'h1))
\det_abs[20]_i_5
(.I0(det_reg_n_87),
.O(\det_abs[20]_i_5_n_0 ));
LUT1 #(
.INIT(2'h1))
\det_abs[20]_i_6
(.I0(det_reg_n_88),
.O(\det_abs[20]_i_6_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair41" *)
LUT3 #(
.INIT(8'hAC))
\det_abs[21]_i_1
(.I0(det_abs0[21]),
.I1(det_reg_n_84),
.I2(det_reg_n_74),
.O(\det_abs[21]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair40" *)
LUT3 #(
.INIT(8'hAC))
\det_abs[22]_i_1
(.I0(det_abs0[22]),
.I1(det_reg_n_83),
.I2(det_reg_n_74),
.O(\det_abs[22]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair38" *)
LUT3 #(
.INIT(8'hAC))
\det_abs[23]_i_1
(.I0(det_abs0[23]),
.I1(det_reg_n_82),
.I2(det_reg_n_74),
.O(\det_abs[23]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair35" *)
LUT3 #(
.INIT(8'hAC))
\det_abs[24]_i_1
(.I0(det_abs0[24]),
.I1(det_reg_n_81),
.I2(det_reg_n_74),
.O(\det_abs[24]_i_1_n_0 ));
LUT1 #(
.INIT(2'h1))
\det_abs[24]_i_3
(.I0(det_reg_n_81),
.O(\det_abs[24]_i_3_n_0 ));
LUT1 #(
.INIT(2'h1))
\det_abs[24]_i_4
(.I0(det_reg_n_82),
.O(\det_abs[24]_i_4_n_0 ));
LUT1 #(
.INIT(2'h1))
\det_abs[24]_i_5
(.I0(det_reg_n_83),
.O(\det_abs[24]_i_5_n_0 ));
LUT1 #(
.INIT(2'h1))
\det_abs[24]_i_6
(.I0(det_reg_n_84),
.O(\det_abs[24]_i_6_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair48" *)
LUT3 #(
.INIT(8'hAC))
\det_abs[25]_i_1
(.I0(det_abs0[25]),
.I1(det_reg_n_80),
.I2(det_reg_n_74),
.O(\det_abs[25]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair29" *)
LUT3 #(
.INIT(8'hAC))
\det_abs[26]_i_1
(.I0(det_abs0[26]),
.I1(det_reg_n_79),
.I2(det_reg_n_74),
.O(\det_abs[26]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair27" *)
LUT3 #(
.INIT(8'hAC))
\det_abs[27]_i_1
(.I0(det_abs0[27]),
.I1(det_reg_n_78),
.I2(det_reg_n_74),
.O(\det_abs[27]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair26" *)
LUT3 #(
.INIT(8'hAC))
\det_abs[28]_i_1
(.I0(det_abs0[28]),
.I1(det_reg_n_77),
.I2(det_reg_n_74),
.O(\det_abs[28]_i_1_n_0 ));
LUT1 #(
.INIT(2'h1))
\det_abs[28]_i_3
(.I0(det_reg_n_77),
.O(\det_abs[28]_i_3_n_0 ));
LUT1 #(
.INIT(2'h1))
\det_abs[28]_i_4
(.I0(det_reg_n_78),
.O(\det_abs[28]_i_4_n_0 ));
LUT1 #(
.INIT(2'h1))
\det_abs[28]_i_5
(.I0(det_reg_n_79),
.O(\det_abs[28]_i_5_n_0 ));
LUT1 #(
.INIT(2'h1))
\det_abs[28]_i_6
(.I0(det_reg_n_80),
.O(\det_abs[28]_i_6_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair30" *)
LUT3 #(
.INIT(8'hAC))
\det_abs[29]_i_1
(.I0(det_abs0[29]),
.I1(det_reg_n_76),
.I2(det_reg_n_74),
.O(\det_abs[29]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair29" *)
LUT3 #(
.INIT(8'hAC))
\det_abs[2]_i_1
(.I0(det_abs0[2]),
.I1(det_reg_n_103),
.I2(det_reg_n_74),
.O(\det_abs[2]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair26" *)
LUT3 #(
.INIT(8'hAC))
\det_abs[30]_i_1
(.I0(det_abs0[30]),
.I1(det_reg_n_75),
.I2(det_reg_n_74),
.O(\det_abs[30]_i_1_n_0 ));
LUT2 #(
.INIT(4'h8))
\det_abs[31]_i_1
(.I0(det_abs0[31]),
.I1(det_reg_n_74),
.O(\det_abs[31]_i_1_n_0 ));
LUT1 #(
.INIT(2'h1))
\det_abs[31]_i_3
(.I0(det_reg_n_74),
.O(\det_abs[31]_i_3_n_0 ));
LUT1 #(
.INIT(2'h1))
\det_abs[31]_i_4
(.I0(det_reg_n_75),
.O(\det_abs[31]_i_4_n_0 ));
LUT1 #(
.INIT(2'h1))
\det_abs[31]_i_5
(.I0(det_reg_n_76),
.O(\det_abs[31]_i_5_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair30" *)
LUT3 #(
.INIT(8'hAC))
\det_abs[3]_i_1
(.I0(det_abs0[3]),
.I1(det_reg_n_102),
.I2(det_reg_n_74),
.O(\det_abs[3]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair35" *)
LUT3 #(
.INIT(8'hAC))
\det_abs[4]_i_1
(.I0(det_abs0[4]),
.I1(det_reg_n_101),
.I2(det_reg_n_74),
.O(\det_abs[4]_i_1_n_0 ));
LUT1 #(
.INIT(2'h1))
\det_abs[4]_i_3
(.I0(det_reg_n_105),
.O(\det_abs[4]_i_3_n_0 ));
LUT1 #(
.INIT(2'h1))
\det_abs[4]_i_4
(.I0(det_reg_n_101),
.O(\det_abs[4]_i_4_n_0 ));
LUT1 #(
.INIT(2'h1))
\det_abs[4]_i_5
(.I0(det_reg_n_102),
.O(\det_abs[4]_i_5_n_0 ));
LUT1 #(
.INIT(2'h1))
\det_abs[4]_i_6
(.I0(det_reg_n_103),
.O(\det_abs[4]_i_6_n_0 ));
LUT1 #(
.INIT(2'h1))
\det_abs[4]_i_7
(.I0(det_reg_n_104),
.O(\det_abs[4]_i_7_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair38" *)
LUT3 #(
.INIT(8'hAC))
\det_abs[5]_i_1
(.I0(det_abs0[5]),
.I1(det_reg_n_100),
.I2(det_reg_n_74),
.O(\det_abs[5]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair40" *)
LUT3 #(
.INIT(8'hAC))
\det_abs[6]_i_1
(.I0(det_abs0[6]),
.I1(det_reg_n_99),
.I2(det_reg_n_74),
.O(\det_abs[6]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair41" *)
LUT3 #(
.INIT(8'hAC))
\det_abs[7]_i_1
(.I0(det_abs0[7]),
.I1(det_reg_n_98),
.I2(det_reg_n_74),
.O(\det_abs[7]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair42" *)
LUT3 #(
.INIT(8'hAC))
\det_abs[8]_i_1
(.I0(det_abs0[8]),
.I1(det_reg_n_97),
.I2(det_reg_n_74),
.O(\det_abs[8]_i_1_n_0 ));
LUT1 #(
.INIT(2'h1))
\det_abs[8]_i_3
(.I0(det_reg_n_97),
.O(\det_abs[8]_i_3_n_0 ));
LUT1 #(
.INIT(2'h1))
\det_abs[8]_i_4
(.I0(det_reg_n_98),
.O(\det_abs[8]_i_4_n_0 ));
LUT1 #(
.INIT(2'h1))
\det_abs[8]_i_5
(.I0(det_reg_n_99),
.O(\det_abs[8]_i_5_n_0 ));
LUT1 #(
.INIT(2'h1))
\det_abs[8]_i_6
(.I0(det_reg_n_100),
.O(\det_abs[8]_i_6_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair43" *)
LUT3 #(
.INIT(8'hAC))
\det_abs[9]_i_1
(.I0(det_abs0[9]),
.I1(det_reg_n_96),
.I2(det_reg_n_74),
.O(\det_abs[9]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\det_abs_reg[0]
(.C(clk_x16),
.CE(y6),
.D(det_reg_n_105),
.Q(det_abs[0]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\det_abs_reg[10]
(.C(clk_x16),
.CE(y6),
.D(\det_abs[10]_i_1_n_0 ),
.Q(det_abs[10]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\det_abs_reg[11]
(.C(clk_x16),
.CE(y6),
.D(\det_abs[11]_i_1_n_0 ),
.Q(det_abs[11]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\det_abs_reg[12]
(.C(clk_x16),
.CE(y6),
.D(\det_abs[12]_i_1_n_0 ),
.Q(det_abs[12]),
.R(1'b0));
CARRY4 \det_abs_reg[12]_i_2
(.CI(\det_abs_reg[8]_i_2_n_0 ),
.CO({\det_abs_reg[12]_i_2_n_0 ,\det_abs_reg[12]_i_2_n_1 ,\det_abs_reg[12]_i_2_n_2 ,\det_abs_reg[12]_i_2_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(det_abs0[12:9]),
.S({\det_abs[12]_i_3_n_0 ,\det_abs[12]_i_4_n_0 ,\det_abs[12]_i_5_n_0 ,\det_abs[12]_i_6_n_0 }));
FDRE #(
.INIT(1'b0))
\det_abs_reg[13]
(.C(clk_x16),
.CE(y6),
.D(\det_abs[13]_i_1_n_0 ),
.Q(det_abs[13]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\det_abs_reg[14]
(.C(clk_x16),
.CE(y6),
.D(\det_abs[14]_i_1_n_0 ),
.Q(det_abs[14]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\det_abs_reg[15]
(.C(clk_x16),
.CE(y6),
.D(\det_abs[15]_i_1_n_0 ),
.Q(det_abs[15]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\det_abs_reg[16]
(.C(clk_x16),
.CE(y6),
.D(\det_abs[16]_i_1_n_0 ),
.Q(det_abs[16]),
.R(1'b0));
CARRY4 \det_abs_reg[16]_i_2
(.CI(\det_abs_reg[12]_i_2_n_0 ),
.CO({\det_abs_reg[16]_i_2_n_0 ,\det_abs_reg[16]_i_2_n_1 ,\det_abs_reg[16]_i_2_n_2 ,\det_abs_reg[16]_i_2_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(det_abs0[16:13]),
.S({\det_abs[16]_i_3_n_0 ,\det_abs[16]_i_4_n_0 ,\det_abs[16]_i_5_n_0 ,\det_abs[16]_i_6_n_0 }));
FDRE #(
.INIT(1'b0))
\det_abs_reg[17]
(.C(clk_x16),
.CE(y6),
.D(\det_abs[17]_i_1_n_0 ),
.Q(det_abs[17]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\det_abs_reg[18]
(.C(clk_x16),
.CE(y6),
.D(\det_abs[18]_i_1_n_0 ),
.Q(det_abs[18]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\det_abs_reg[19]
(.C(clk_x16),
.CE(y6),
.D(\det_abs[19]_i_1_n_0 ),
.Q(det_abs[19]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\det_abs_reg[1]
(.C(clk_x16),
.CE(y6),
.D(\det_abs[1]_i_1_n_0 ),
.Q(det_abs[1]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\det_abs_reg[20]
(.C(clk_x16),
.CE(y6),
.D(\det_abs[20]_i_1_n_0 ),
.Q(det_abs[20]),
.R(1'b0));
CARRY4 \det_abs_reg[20]_i_2
(.CI(\det_abs_reg[16]_i_2_n_0 ),
.CO({\det_abs_reg[20]_i_2_n_0 ,\det_abs_reg[20]_i_2_n_1 ,\det_abs_reg[20]_i_2_n_2 ,\det_abs_reg[20]_i_2_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(det_abs0[20:17]),
.S({\det_abs[20]_i_3_n_0 ,\det_abs[20]_i_4_n_0 ,\det_abs[20]_i_5_n_0 ,\det_abs[20]_i_6_n_0 }));
FDRE #(
.INIT(1'b0))
\det_abs_reg[21]
(.C(clk_x16),
.CE(y6),
.D(\det_abs[21]_i_1_n_0 ),
.Q(det_abs[21]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\det_abs_reg[22]
(.C(clk_x16),
.CE(y6),
.D(\det_abs[22]_i_1_n_0 ),
.Q(det_abs[22]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\det_abs_reg[23]
(.C(clk_x16),
.CE(y6),
.D(\det_abs[23]_i_1_n_0 ),
.Q(det_abs[23]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\det_abs_reg[24]
(.C(clk_x16),
.CE(y6),
.D(\det_abs[24]_i_1_n_0 ),
.Q(det_abs[24]),
.R(1'b0));
CARRY4 \det_abs_reg[24]_i_2
(.CI(\det_abs_reg[20]_i_2_n_0 ),
.CO({\det_abs_reg[24]_i_2_n_0 ,\det_abs_reg[24]_i_2_n_1 ,\det_abs_reg[24]_i_2_n_2 ,\det_abs_reg[24]_i_2_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(det_abs0[24:21]),
.S({\det_abs[24]_i_3_n_0 ,\det_abs[24]_i_4_n_0 ,\det_abs[24]_i_5_n_0 ,\det_abs[24]_i_6_n_0 }));
FDRE #(
.INIT(1'b0))
\det_abs_reg[25]
(.C(clk_x16),
.CE(y6),
.D(\det_abs[25]_i_1_n_0 ),
.Q(det_abs[25]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\det_abs_reg[26]
(.C(clk_x16),
.CE(y6),
.D(\det_abs[26]_i_1_n_0 ),
.Q(det_abs[26]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\det_abs_reg[27]
(.C(clk_x16),
.CE(y6),
.D(\det_abs[27]_i_1_n_0 ),
.Q(det_abs[27]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\det_abs_reg[28]
(.C(clk_x16),
.CE(y6),
.D(\det_abs[28]_i_1_n_0 ),
.Q(det_abs[28]),
.R(1'b0));
CARRY4 \det_abs_reg[28]_i_2
(.CI(\det_abs_reg[24]_i_2_n_0 ),
.CO({\det_abs_reg[28]_i_2_n_0 ,\det_abs_reg[28]_i_2_n_1 ,\det_abs_reg[28]_i_2_n_2 ,\det_abs_reg[28]_i_2_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(det_abs0[28:25]),
.S({\det_abs[28]_i_3_n_0 ,\det_abs[28]_i_4_n_0 ,\det_abs[28]_i_5_n_0 ,\det_abs[28]_i_6_n_0 }));
FDRE #(
.INIT(1'b0))
\det_abs_reg[29]
(.C(clk_x16),
.CE(y6),
.D(\det_abs[29]_i_1_n_0 ),
.Q(det_abs[29]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\det_abs_reg[2]
(.C(clk_x16),
.CE(y6),
.D(\det_abs[2]_i_1_n_0 ),
.Q(det_abs[2]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\det_abs_reg[30]
(.C(clk_x16),
.CE(y6),
.D(\det_abs[30]_i_1_n_0 ),
.Q(det_abs[30]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\det_abs_reg[31]
(.C(clk_x16),
.CE(y6),
.D(\det_abs[31]_i_1_n_0 ),
.Q(det_abs[31]),
.R(1'b0));
CARRY4 \det_abs_reg[31]_i_2
(.CI(\det_abs_reg[28]_i_2_n_0 ),
.CO({\NLW_det_abs_reg[31]_i_2_CO_UNCONNECTED [3:2],\det_abs_reg[31]_i_2_n_2 ,\det_abs_reg[31]_i_2_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O({\NLW_det_abs_reg[31]_i_2_O_UNCONNECTED [3],det_abs0[31:29]}),
.S({1'b0,\det_abs[31]_i_3_n_0 ,\det_abs[31]_i_4_n_0 ,\det_abs[31]_i_5_n_0 }));
FDRE #(
.INIT(1'b0))
\det_abs_reg[3]
(.C(clk_x16),
.CE(y6),
.D(\det_abs[3]_i_1_n_0 ),
.Q(det_abs[3]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\det_abs_reg[4]
(.C(clk_x16),
.CE(y6),
.D(\det_abs[4]_i_1_n_0 ),
.Q(det_abs[4]),
.R(1'b0));
CARRY4 \det_abs_reg[4]_i_2
(.CI(1'b0),
.CO({\det_abs_reg[4]_i_2_n_0 ,\det_abs_reg[4]_i_2_n_1 ,\det_abs_reg[4]_i_2_n_2 ,\det_abs_reg[4]_i_2_n_3 }),
.CYINIT(\det_abs[4]_i_3_n_0 ),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(det_abs0[4:1]),
.S({\det_abs[4]_i_4_n_0 ,\det_abs[4]_i_5_n_0 ,\det_abs[4]_i_6_n_0 ,\det_abs[4]_i_7_n_0 }));
FDRE #(
.INIT(1'b0))
\det_abs_reg[5]
(.C(clk_x16),
.CE(y6),
.D(\det_abs[5]_i_1_n_0 ),
.Q(det_abs[5]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\det_abs_reg[6]
(.C(clk_x16),
.CE(y6),
.D(\det_abs[6]_i_1_n_0 ),
.Q(det_abs[6]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\det_abs_reg[7]
(.C(clk_x16),
.CE(y6),
.D(\det_abs[7]_i_1_n_0 ),
.Q(det_abs[7]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\det_abs_reg[8]
(.C(clk_x16),
.CE(y6),
.D(\det_abs[8]_i_1_n_0 ),
.Q(det_abs[8]),
.R(1'b0));
CARRY4 \det_abs_reg[8]_i_2
(.CI(\det_abs_reg[4]_i_2_n_0 ),
.CO({\det_abs_reg[8]_i_2_n_0 ,\det_abs_reg[8]_i_2_n_1 ,\det_abs_reg[8]_i_2_n_2 ,\det_abs_reg[8]_i_2_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(det_abs0[8:5]),
.S({\det_abs[8]_i_3_n_0 ,\det_abs[8]_i_4_n_0 ,\det_abs[8]_i_5_n_0 ,\det_abs[8]_i_6_n_0 }));
FDRE #(
.INIT(1'b0))
\det_abs_reg[9]
(.C(clk_x16),
.CE(y6),
.D(\det_abs[9]_i_1_n_0 ),
.Q(det_abs[9]),
.R(1'b0));
DSP48E1 #(
.ACASCREG(1),
.ADREG(1),
.ALUMODEREG(0),
.AREG(1),
.AUTORESET_PATDET("NO_RESET"),
.A_INPUT("DIRECT"),
.BCASCREG(1),
.BREG(1),
.B_INPUT("DIRECT"),
.CARRYINREG(0),
.CARRYINSELREG(0),
.CREG(1),
.DREG(1),
.INMODEREG(0),
.MASK(48'h3FFFFFFFFFFF),
.MREG(1),
.OPMODEREG(0),
.PATTERN(48'h000000000000),
.PREG(1),
.SEL_MASK("MASK"),
.SEL_PATTERN("PATTERN"),
.USE_DPORT("FALSE"),
.USE_MULT("MULTIPLY"),
.USE_PATTERN_DETECT("NO_PATDET"),
.USE_SIMD("ONE48"))
det_reg
(.A({Lxy0__1_carry__2_n_4,Lxy0__1_carry__2_n_4,Lxy0__1_carry__2_n_4,Lxy0__1_carry__2_n_4,Lxy0__1_carry__2_n_4,Lxy0__1_carry__2_n_4,Lxy0__1_carry__2_n_4,Lxy0__1_carry__2_n_4,Lxy0__1_carry__2_n_4,Lxy0__1_carry__2_n_4,Lxy0__1_carry__2_n_4,Lxy0__1_carry__2_n_4,Lxy0__1_carry__2_n_4,Lxy0__1_carry__2_n_4,Lxy0__1_carry__2_n_4,Lxy0__1_carry__2_n_5,Lxy0__1_carry__2_n_6,Lxy0__1_carry__2_n_7,Lxy0__1_carry__1_n_4,Lxy0__1_carry__1_n_5,Lxy0__1_carry__1_n_6,Lxy0__1_carry__1_n_7,Lxy0__1_carry__0_n_4,Lxy0__1_carry__0_n_5,Lxy0__1_carry__0_n_6,Lxy0__1_carry__0_n_7,Lxy0__1_carry_n_4,Lxy0__1_carry_n_5,Lxy0__1_carry_n_6,Lxy0__1_carry_n_7}),
.ACIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.ACOUT(NLW_det_reg_ACOUT_UNCONNECTED[29:0]),
.ALUMODE({1'b0,1'b0,1'b1,1'b1}),
.B({Lxy0__1_carry__2_n_4,Lxy0__1_carry__2_n_4,Lxy0__1_carry__2_n_4,Lxy0__1_carry__2_n_5,Lxy0__1_carry__2_n_6,Lxy0__1_carry__2_n_7,Lxy0__1_carry__1_n_4,Lxy0__1_carry__1_n_5,Lxy0__1_carry__1_n_6,Lxy0__1_carry__1_n_7,Lxy0__1_carry__0_n_4,Lxy0__1_carry__0_n_5,Lxy0__1_carry__0_n_6,Lxy0__1_carry__0_n_7,Lxy0__1_carry_n_4,Lxy0__1_carry_n_5,Lxy0__1_carry_n_6,Lxy0__1_carry_n_7}),
.BCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.BCOUT(NLW_det_reg_BCOUT_UNCONNECTED[17:0]),
.C({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
.CARRYCASCIN(1'b0),
.CARRYCASCOUT(NLW_det_reg_CARRYCASCOUT_UNCONNECTED),
.CARRYIN(1'b0),
.CARRYINSEL({1'b0,1'b0,1'b0}),
.CARRYOUT(NLW_det_reg_CARRYOUT_UNCONNECTED[3:0]),
.CEA1(1'b0),
.CEA2(y3),
.CEAD(1'b0),
.CEALUMODE(1'b0),
.CEB1(1'b0),
.CEB2(y3),
.CEC(1'b0),
.CECARRYIN(1'b0),
.CECTRL(1'b0),
.CED(1'b0),
.CEINMODE(1'b0),
.CEM(y2),
.CEP(y9),
.CLK(clk_x16),
.D({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.INMODE({1'b0,1'b0,1'b0,1'b0,1'b0}),
.MULTSIGNIN(1'b0),
.MULTSIGNOUT(NLW_det_reg_MULTSIGNOUT_UNCONNECTED),
.OPMODE({1'b0,1'b0,1'b1,1'b0,1'b1,1'b0,1'b1}),
.OVERFLOW(NLW_det_reg_OVERFLOW_UNCONNECTED),
.P({NLW_det_reg_P_UNCONNECTED[47:32],det_reg_n_74,det_reg_n_75,det_reg_n_76,det_reg_n_77,det_reg_n_78,det_reg_n_79,det_reg_n_80,det_reg_n_81,det_reg_n_82,det_reg_n_83,det_reg_n_84,det_reg_n_85,det_reg_n_86,det_reg_n_87,det_reg_n_88,det_reg_n_89,det_reg_n_90,det_reg_n_91,det_reg_n_92,det_reg_n_93,det_reg_n_94,det_reg_n_95,det_reg_n_96,det_reg_n_97,det_reg_n_98,det_reg_n_99,det_reg_n_100,det_reg_n_101,det_reg_n_102,det_reg_n_103,det_reg_n_104,det_reg_n_105}),
.PATTERNBDETECT(NLW_det_reg_PATTERNBDETECT_UNCONNECTED),
.PATTERNDETECT(NLW_det_reg_PATTERNDETECT_UNCONNECTED),
.PCIN({det_0_reg_n_106,det_0_reg_n_107,det_0_reg_n_108,det_0_reg_n_109,det_0_reg_n_110,det_0_reg_n_111,det_0_reg_n_112,det_0_reg_n_113,det_0_reg_n_114,det_0_reg_n_115,det_0_reg_n_116,det_0_reg_n_117,det_0_reg_n_118,det_0_reg_n_119,det_0_reg_n_120,det_0_reg_n_121,det_0_reg_n_122,det_0_reg_n_123,det_0_reg_n_124,det_0_reg_n_125,det_0_reg_n_126,det_0_reg_n_127,det_0_reg_n_128,det_0_reg_n_129,det_0_reg_n_130,det_0_reg_n_131,det_0_reg_n_132,det_0_reg_n_133,det_0_reg_n_134,det_0_reg_n_135,det_0_reg_n_136,det_0_reg_n_137,det_0_reg_n_138,det_0_reg_n_139,det_0_reg_n_140,det_0_reg_n_141,det_0_reg_n_142,det_0_reg_n_143,det_0_reg_n_144,det_0_reg_n_145,det_0_reg_n_146,det_0_reg_n_147,det_0_reg_n_148,det_0_reg_n_149,det_0_reg_n_150,det_0_reg_n_151,det_0_reg_n_152,det_0_reg_n_153}),
.PCOUT(NLW_det_reg_PCOUT_UNCONNECTED[47:0]),
.RSTA(1'b0),
.RSTALLCARRYIN(1'b0),
.RSTALUMODE(1'b0),
.RSTB(1'b0),
.RSTC(1'b0),
.RSTCTRL(1'b0),
.RSTD(1'b0),
.RSTINMODE(1'b0),
.RSTM(1'b0),
.RSTP(1'b0),
.UNDERFLOW(NLW_det_reg_UNDERFLOW_UNCONNECTED));
LUT6 #(
.INIT(64'h0000000040000000))
det_reg_i_1
(.I0(\cycle_reg[2]_rep_n_0 ),
.I1(cycle[3]),
.I2(rst),
.I3(active),
.I4(\cycle_reg[0]_rep_n_0 ),
.I5(\cycle_reg[1]_rep__0_n_0 ),
.O(y2));
LUT6 #(
.INIT(64'h0000000080000000))
det_reg_i_2
(.I0(\cycle_reg[2]_rep_n_0 ),
.I1(cycle[3]),
.I2(rst),
.I3(active),
.I4(\cycle_reg[0]_rep_n_0 ),
.I5(\cycle_reg[1]_rep__0_n_0 ),
.O(y9));
FDRE #(
.INIT(1'b0))
\din_reg[0]
(.C(clk_x16),
.CE(det_0_reg_i_2_n_0),
.D(\cache_reg[8]_1 [0]),
.Q(\din_reg_n_0_[0] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\din_reg[10]
(.C(clk_x16),
.CE(det_0_reg_i_2_n_0),
.D(\cache_reg[8]_1 [10]),
.Q(\din_reg_n_0_[10] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\din_reg[11]
(.C(clk_x16),
.CE(det_0_reg_i_2_n_0),
.D(\cache_reg[8]_1 [11]),
.Q(\din_reg_n_0_[11] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\din_reg[12]
(.C(clk_x16),
.CE(det_0_reg_i_2_n_0),
.D(\cache_reg[8]_1 [12]),
.Q(\din_reg_n_0_[12] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\din_reg[13]
(.C(clk_x16),
.CE(det_0_reg_i_2_n_0),
.D(\cache_reg[8]_1 [13]),
.Q(\din_reg_n_0_[13] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\din_reg[14]
(.C(clk_x16),
.CE(det_0_reg_i_2_n_0),
.D(\cache_reg[8]_1 [14]),
.Q(\din_reg_n_0_[14] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\din_reg[15]
(.C(clk_x16),
.CE(det_0_reg_i_2_n_0),
.D(\cache_reg[8]_1 [15]),
.Q(\din_reg_n_0_[15] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\din_reg[1]
(.C(clk_x16),
.CE(det_0_reg_i_2_n_0),
.D(\cache_reg[8]_1 [1]),
.Q(\din_reg_n_0_[1] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\din_reg[2]
(.C(clk_x16),
.CE(det_0_reg_i_2_n_0),
.D(\cache_reg[8]_1 [2]),
.Q(\din_reg_n_0_[2] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\din_reg[3]
(.C(clk_x16),
.CE(det_0_reg_i_2_n_0),
.D(\cache_reg[8]_1 [3]),
.Q(\din_reg_n_0_[3] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\din_reg[4]
(.C(clk_x16),
.CE(det_0_reg_i_2_n_0),
.D(\cache_reg[8]_1 [4]),
.Q(\din_reg_n_0_[4] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\din_reg[5]
(.C(clk_x16),
.CE(det_0_reg_i_2_n_0),
.D(\cache_reg[8]_1 [5]),
.Q(\din_reg_n_0_[5] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\din_reg[6]
(.C(clk_x16),
.CE(det_0_reg_i_2_n_0),
.D(\cache_reg[8]_1 [6]),
.Q(\din_reg_n_0_[6] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\din_reg[7]
(.C(clk_x16),
.CE(det_0_reg_i_2_n_0),
.D(\cache_reg[8]_1 [7]),
.Q(\din_reg_n_0_[7] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\din_reg[8]
(.C(clk_x16),
.CE(det_0_reg_i_2_n_0),
.D(\cache_reg[8]_1 [8]),
.Q(\din_reg_n_0_[8] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\din_reg[9]
(.C(clk_x16),
.CE(det_0_reg_i_2_n_0),
.D(\cache_reg[8]_1 [9]),
.Q(\din_reg_n_0_[9] ),
.R(1'b0));
LUT6 #(
.INIT(64'h8000000000000000))
\hessian_out[31]_i_1
(.I0(rst),
.I1(active),
.I2(cycle[3]),
.I3(cycle[0]),
.I4(\cycle_reg[2]_rep_n_0 ),
.I5(\cycle_reg[1]_rep__0_n_0 ),
.O(y3));
FDRE \hessian_out_reg[0]
(.C(clk_x16),
.CE(y3),
.D(det_abs[0]),
.Q(hessian_out[0]),
.R(1'b0));
FDRE \hessian_out_reg[10]
(.C(clk_x16),
.CE(y3),
.D(det_abs[10]),
.Q(hessian_out[10]),
.R(1'b0));
FDRE \hessian_out_reg[11]
(.C(clk_x16),
.CE(y3),
.D(det_abs[11]),
.Q(hessian_out[11]),
.R(1'b0));
FDRE \hessian_out_reg[12]
(.C(clk_x16),
.CE(y3),
.D(det_abs[12]),
.Q(hessian_out[12]),
.R(1'b0));
FDRE \hessian_out_reg[13]
(.C(clk_x16),
.CE(y3),
.D(det_abs[13]),
.Q(hessian_out[13]),
.R(1'b0));
FDRE \hessian_out_reg[14]
(.C(clk_x16),
.CE(y3),
.D(det_abs[14]),
.Q(hessian_out[14]),
.R(1'b0));
FDRE \hessian_out_reg[15]
(.C(clk_x16),
.CE(y3),
.D(det_abs[15]),
.Q(hessian_out[15]),
.R(1'b0));
FDRE \hessian_out_reg[16]
(.C(clk_x16),
.CE(y3),
.D(det_abs[16]),
.Q(hessian_out[16]),
.R(1'b0));
FDRE \hessian_out_reg[17]
(.C(clk_x16),
.CE(y3),
.D(det_abs[17]),
.Q(hessian_out[17]),
.R(1'b0));
FDRE \hessian_out_reg[18]
(.C(clk_x16),
.CE(y3),
.D(det_abs[18]),
.Q(hessian_out[18]),
.R(1'b0));
FDRE \hessian_out_reg[19]
(.C(clk_x16),
.CE(y3),
.D(det_abs[19]),
.Q(hessian_out[19]),
.R(1'b0));
FDRE \hessian_out_reg[1]
(.C(clk_x16),
.CE(y3),
.D(det_abs[1]),
.Q(hessian_out[1]),
.R(1'b0));
FDRE \hessian_out_reg[20]
(.C(clk_x16),
.CE(y3),
.D(det_abs[20]),
.Q(hessian_out[20]),
.R(1'b0));
FDRE \hessian_out_reg[21]
(.C(clk_x16),
.CE(y3),
.D(det_abs[21]),
.Q(hessian_out[21]),
.R(1'b0));
FDRE \hessian_out_reg[22]
(.C(clk_x16),
.CE(y3),
.D(det_abs[22]),
.Q(hessian_out[22]),
.R(1'b0));
FDRE \hessian_out_reg[23]
(.C(clk_x16),
.CE(y3),
.D(det_abs[23]),
.Q(hessian_out[23]),
.R(1'b0));
FDRE \hessian_out_reg[24]
(.C(clk_x16),
.CE(y3),
.D(det_abs[24]),
.Q(hessian_out[24]),
.R(1'b0));
FDRE \hessian_out_reg[25]
(.C(clk_x16),
.CE(y3),
.D(det_abs[25]),
.Q(hessian_out[25]),
.R(1'b0));
FDRE \hessian_out_reg[26]
(.C(clk_x16),
.CE(y3),
.D(det_abs[26]),
.Q(hessian_out[26]),
.R(1'b0));
FDRE \hessian_out_reg[27]
(.C(clk_x16),
.CE(y3),
.D(det_abs[27]),
.Q(hessian_out[27]),
.R(1'b0));
FDRE \hessian_out_reg[28]
(.C(clk_x16),
.CE(y3),
.D(det_abs[28]),
.Q(hessian_out[28]),
.R(1'b0));
FDRE \hessian_out_reg[29]
(.C(clk_x16),
.CE(y3),
.D(det_abs[29]),
.Q(hessian_out[29]),
.R(1'b0));
FDRE \hessian_out_reg[2]
(.C(clk_x16),
.CE(y3),
.D(det_abs[2]),
.Q(hessian_out[2]),
.R(1'b0));
FDRE \hessian_out_reg[30]
(.C(clk_x16),
.CE(y3),
.D(det_abs[30]),
.Q(hessian_out[30]),
.R(1'b0));
FDRE \hessian_out_reg[31]
(.C(clk_x16),
.CE(y3),
.D(det_abs[31]),
.Q(hessian_out[31]),
.R(1'b0));
FDRE \hessian_out_reg[3]
(.C(clk_x16),
.CE(y3),
.D(det_abs[3]),
.Q(hessian_out[3]),
.R(1'b0));
FDRE \hessian_out_reg[4]
(.C(clk_x16),
.CE(y3),
.D(det_abs[4]),
.Q(hessian_out[4]),
.R(1'b0));
FDRE \hessian_out_reg[5]
(.C(clk_x16),
.CE(y3),
.D(det_abs[5]),
.Q(hessian_out[5]),
.R(1'b0));
FDRE \hessian_out_reg[6]
(.C(clk_x16),
.CE(y3),
.D(det_abs[6]),
.Q(hessian_out[6]),
.R(1'b0));
FDRE \hessian_out_reg[7]
(.C(clk_x16),
.CE(y3),
.D(det_abs[7]),
.Q(hessian_out[7]),
.R(1'b0));
FDRE \hessian_out_reg[8]
(.C(clk_x16),
.CE(y3),
.D(det_abs[8]),
.Q(hessian_out[8]),
.R(1'b0));
FDRE \hessian_out_reg[9]
(.C(clk_x16),
.CE(y3),
.D(det_abs[9]),
.Q(hessian_out[9]),
.R(1'b0));
LUT4 #(
.INIT(16'h0400))
i__carry__0_i_1
(.I0(\cycle_reg[1]_rep__0_n_0 ),
.I1(cycle[0]),
.I2(\cycle_reg[2]_rep_n_0 ),
.I3(cycle[3]),
.O(i__carry__0_i_1_n_0));
LUT2 #(
.INIT(4'h9))
i__carry__0_i_2
(.I0(\x_reg_n_0_[6] ),
.I1(\x_reg_n_0_[7] ),
.O(i__carry__0_i_2_n_0));
LUT2 #(
.INIT(4'h9))
i__carry__0_i_3
(.I0(\x_reg_n_0_[5] ),
.I1(\x_reg_n_0_[6] ),
.O(i__carry__0_i_3_n_0));
LUT2 #(
.INIT(4'h9))
i__carry__0_i_4
(.I0(\x_reg_n_0_[4] ),
.I1(\x_reg_n_0_[5] ),
.O(i__carry__0_i_4_n_0));
LUT5 #(
.INIT(32'h0020FFDF))
i__carry__0_i_5
(.I0(cycle[3]),
.I1(\cycle_reg[2]_rep_n_0 ),
.I2(cycle[0]),
.I3(\cycle_reg[1]_rep__0_n_0 ),
.I4(\x_reg_n_0_[4] ),
.O(i__carry__0_i_5_n_0));
LUT2 #(
.INIT(4'h9))
i__carry__1_i_1
(.I0(\x_reg_n_0_[8] ),
.I1(\x_reg_n_0_[9] ),
.O(i__carry__1_i_1_n_0));
LUT2 #(
.INIT(4'h9))
i__carry__1_i_2
(.I0(\x_reg_n_0_[7] ),
.I1(\x_reg_n_0_[8] ),
.O(i__carry__1_i_2_n_0));
LUT5 #(
.INIT(32'h0020FFDF))
i__carry_i_1
(.I0(cycle[3]),
.I1(\cycle_reg[2]_rep_n_0 ),
.I2(cycle[0]),
.I3(\cycle_reg[1]_rep__0_n_0 ),
.I4(\x_reg_n_0_[3] ),
.O(i__carry_i_1_n_0));
LUT4 #(
.INIT(16'hAA6A))
i__carry_i_2
(.I0(\x_reg_n_0_[2] ),
.I1(cycle[3]),
.I2(\cycle_reg[1]_rep__0_n_0 ),
.I3(\cycle_reg[2]_rep_n_0 ),
.O(i__carry_i_2_n_0));
LUT5 #(
.INIT(32'h55599555))
i__carry_i_3
(.I0(\x_reg_n_0_[1] ),
.I1(cycle[3]),
.I2(cycle[0]),
.I3(\cycle_reg[1]_rep__0_n_0 ),
.I4(\cycle_reg[2]_rep_n_0 ),
.O(i__carry_i_3_n_0));
LUT4 #(
.INIT(16'h5595))
i__carry_i_4
(.I0(\x_reg_n_0_[0] ),
.I1(cycle[3]),
.I2(cycle[0]),
.I3(\cycle_reg[2]_rep_n_0 ),
.O(i__carry_i_4_n_0));
FDRE #(
.INIT(1'b0))
\last_value_reg[0]
(.C(clk_x16),
.CE(x),
.D(\value_reg_n_0_[0] ),
.Q(last_value[0]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\last_value_reg[1]
(.C(clk_x16),
.CE(x),
.D(\value_reg_n_0_[1] ),
.Q(last_value[1]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\last_value_reg[2]
(.C(clk_x16),
.CE(x),
.D(\value_reg_n_0_[2] ),
.Q(last_value[2]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\last_value_reg[3]
(.C(clk_x16),
.CE(x),
.D(\value_reg_n_0_[3] ),
.Q(last_value[3]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\last_value_reg[4]
(.C(clk_x16),
.CE(x),
.D(\value_reg_n_0_[4] ),
.Q(last_value[4]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\last_value_reg[5]
(.C(clk_x16),
.CE(x),
.D(\value_reg_n_0_[5] ),
.Q(last_value[5]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\last_value_reg[6]
(.C(clk_x16),
.CE(x),
.D(\value_reg_n_0_[6] ),
.Q(last_value[6]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\last_value_reg[7]
(.C(clk_x16),
.CE(x),
.D(\value_reg_n_0_[7] ),
.Q(last_value[7]),
.R(1'b0));
LUT5 #(
.INIT(32'h00000008))
\left[15]_i_1
(.I0(\left[15]_i_2_n_0 ),
.I1(x),
.I2(\x_reg_n_0_[0] ),
.I3(\x_reg_n_0_[9] ),
.I4(\x_reg_n_0_[8] ),
.O(left));
(* SOFT_HLUTNM = "soft_lutpair17" *)
LUT4 #(
.INIT(16'h0001))
\left[15]_i_2
(.I0(\x_reg_n_0_[7] ),
.I1(\x_reg_n_0_[5] ),
.I2(\x_reg_n_0_[6] ),
.I3(\left[15]_i_3_n_0 ),
.O(\left[15]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair13" *)
LUT4 #(
.INIT(16'hFFFE))
\left[15]_i_3
(.I0(\x_reg_n_0_[4] ),
.I1(\x_reg_n_0_[1] ),
.I2(\x_reg_n_0_[2] ),
.I3(\x_reg_n_0_[3] ),
.O(\left[15]_i_3_n_0 ));
FDRE #(
.INIT(1'b0))
\left_reg[0]
(.C(clk_x16),
.CE(x),
.D(\cache_reg[0]_4 [0]),
.Q(\left_reg_n_0_[0] ),
.R(left));
FDRE #(
.INIT(1'b0))
\left_reg[10]
(.C(clk_x16),
.CE(x),
.D(\cache_reg[0]_4 [10]),
.Q(\left_reg_n_0_[10] ),
.R(left));
FDRE #(
.INIT(1'b0))
\left_reg[11]
(.C(clk_x16),
.CE(x),
.D(\cache_reg[0]_4 [11]),
.Q(\left_reg_n_0_[11] ),
.R(left));
FDRE #(
.INIT(1'b0))
\left_reg[12]
(.C(clk_x16),
.CE(x),
.D(\cache_reg[0]_4 [12]),
.Q(\left_reg_n_0_[12] ),
.R(left));
FDRE #(
.INIT(1'b0))
\left_reg[13]
(.C(clk_x16),
.CE(x),
.D(\cache_reg[0]_4 [13]),
.Q(\left_reg_n_0_[13] ),
.R(left));
FDRE #(
.INIT(1'b0))
\left_reg[14]
(.C(clk_x16),
.CE(x),
.D(\cache_reg[0]_4 [14]),
.Q(\left_reg_n_0_[14] ),
.R(left));
FDRE #(
.INIT(1'b0))
\left_reg[15]
(.C(clk_x16),
.CE(x),
.D(\cache_reg[0]_4 [15]),
.Q(\left_reg_n_0_[15] ),
.R(left));
FDRE #(
.INIT(1'b0))
\left_reg[1]
(.C(clk_x16),
.CE(x),
.D(\cache_reg[0]_4 [1]),
.Q(\left_reg_n_0_[1] ),
.R(left));
FDRE #(
.INIT(1'b0))
\left_reg[2]
(.C(clk_x16),
.CE(x),
.D(\cache_reg[0]_4 [2]),
.Q(\left_reg_n_0_[2] ),
.R(left));
FDRE #(
.INIT(1'b0))
\left_reg[3]
(.C(clk_x16),
.CE(x),
.D(\cache_reg[0]_4 [3]),
.Q(\left_reg_n_0_[3] ),
.R(left));
FDRE #(
.INIT(1'b0))
\left_reg[4]
(.C(clk_x16),
.CE(x),
.D(\cache_reg[0]_4 [4]),
.Q(\left_reg_n_0_[4] ),
.R(left));
FDRE #(
.INIT(1'b0))
\left_reg[5]
(.C(clk_x16),
.CE(x),
.D(\cache_reg[0]_4 [5]),
.Q(\left_reg_n_0_[5] ),
.R(left));
FDRE #(
.INIT(1'b0))
\left_reg[6]
(.C(clk_x16),
.CE(x),
.D(\cache_reg[0]_4 [6]),
.Q(\left_reg_n_0_[6] ),
.R(left));
FDRE #(
.INIT(1'b0))
\left_reg[7]
(.C(clk_x16),
.CE(x),
.D(\cache_reg[0]_4 [7]),
.Q(\left_reg_n_0_[7] ),
.R(left));
FDRE #(
.INIT(1'b0))
\left_reg[8]
(.C(clk_x16),
.CE(x),
.D(\cache_reg[0]_4 [8]),
.Q(\left_reg_n_0_[8] ),
.R(left));
FDRE #(
.INIT(1'b0))
\left_reg[9]
(.C(clk_x16),
.CE(x),
.D(\cache_reg[0]_4 [9]),
.Q(\left_reg_n_0_[9] ),
.R(left));
CARRY4 \plusOp_inferred__0/i__carry
(.CI(1'b0),
.CO({\plusOp_inferred__0/i__carry_n_0 ,\plusOp_inferred__0/i__carry_n_1 ,\plusOp_inferred__0/i__carry_n_2 ,\plusOp_inferred__0/i__carry_n_3 }),
.CYINIT(1'b0),
.DI({\x_reg_n_0_[3] ,\x_reg_n_0_[2] ,\x_reg_n_0_[1] ,\x_reg_n_0_[0] }),
.O({\plusOp_inferred__0/i__carry_n_4 ,\plusOp_inferred__0/i__carry_n_5 ,\plusOp_inferred__0/i__carry_n_6 ,\plusOp_inferred__0/i__carry_n_7 }),
.S({i__carry_i_1_n_0,i__carry_i_2_n_0,i__carry_i_3_n_0,i__carry_i_4_n_0}));
CARRY4 \plusOp_inferred__0/i__carry__0
(.CI(\plusOp_inferred__0/i__carry_n_0 ),
.CO({\plusOp_inferred__0/i__carry__0_n_0 ,\plusOp_inferred__0/i__carry__0_n_1 ,\plusOp_inferred__0/i__carry__0_n_2 ,\plusOp_inferred__0/i__carry__0_n_3 }),
.CYINIT(1'b0),
.DI({\x_reg_n_0_[6] ,\x_reg_n_0_[5] ,\x_reg_n_0_[4] ,i__carry__0_i_1_n_0}),
.O({\plusOp_inferred__0/i__carry__0_n_4 ,\plusOp_inferred__0/i__carry__0_n_5 ,\plusOp_inferred__0/i__carry__0_n_6 ,\plusOp_inferred__0/i__carry__0_n_7 }),
.S({i__carry__0_i_2_n_0,i__carry__0_i_3_n_0,i__carry__0_i_4_n_0,i__carry__0_i_5_n_0}));
CARRY4 \plusOp_inferred__0/i__carry__1
(.CI(\plusOp_inferred__0/i__carry__0_n_0 ),
.CO({\NLW_plusOp_inferred__0/i__carry__1_CO_UNCONNECTED [3:1],\plusOp_inferred__0/i__carry__1_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,\x_reg_n_0_[7] }),
.O({\NLW_plusOp_inferred__0/i__carry__1_O_UNCONNECTED [3:2],\plusOp_inferred__0/i__carry__1_n_6 ,\plusOp_inferred__0/i__carry__1_n_7 }),
.S({1'b0,1'b0,i__carry__1_i_1_n_0,i__carry__1_i_2_n_0}));
LUT6 #(
.INIT(64'h0000000000000002))
\top[15]_i_1
(.I0(x),
.I1(\top[15]_i_2_n_0 ),
.I2(\y_actual_reg_n_0_[3] ),
.I3(\y_actual_reg_n_0_[0] ),
.I4(\y_actual_reg_n_0_[1] ),
.I5(\y_actual_reg_n_0_[2] ),
.O(top));
LUT6 #(
.INIT(64'hFFFFFFFFFFFFFFFE))
\top[15]_i_2
(.I0(\y_actual_reg_n_0_[8] ),
.I1(\y_actual_reg_n_0_[9] ),
.I2(\y_actual_reg_n_0_[6] ),
.I3(\y_actual_reg_n_0_[7] ),
.I4(\y_actual_reg_n_0_[4] ),
.I5(\y_actual_reg_n_0_[5] ),
.O(\top[15]_i_2_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFEF00000020))
\top_left_0[0]_i_1
(.I0(dout_0[0]),
.I1(cycle[2]),
.I2(\cycle_reg[1]_rep_n_0 ),
.I3(\cycle_reg[0]_rep_n_0 ),
.I4(cycle[3]),
.I5(dout_1[0]),
.O(\top_left_0[0]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFEF00000020))
\top_left_0[10]_i_1
(.I0(dout_0[10]),
.I1(cycle[2]),
.I2(\cycle_reg[1]_rep_n_0 ),
.I3(\cycle_reg[0]_rep_n_0 ),
.I4(cycle[3]),
.I5(dout_1[10]),
.O(\top_left_0[10]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFEF00000020))
\top_left_0[11]_i_1
(.I0(dout_0[11]),
.I1(cycle[2]),
.I2(\cycle_reg[1]_rep_n_0 ),
.I3(\cycle_reg[0]_rep_n_0 ),
.I4(cycle[3]),
.I5(dout_1[11]),
.O(\top_left_0[11]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFEF00000020))
\top_left_0[12]_i_1
(.I0(dout_0[12]),
.I1(cycle[2]),
.I2(\cycle_reg[1]_rep_n_0 ),
.I3(\cycle_reg[0]_rep_n_0 ),
.I4(cycle[3]),
.I5(dout_1[12]),
.O(\top_left_0[12]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFEF00000020))
\top_left_0[13]_i_1
(.I0(dout_0[13]),
.I1(cycle[2]),
.I2(\cycle_reg[1]_rep_n_0 ),
.I3(\cycle_reg[0]_rep_n_0 ),
.I4(cycle[3]),
.I5(dout_1[13]),
.O(\top_left_0[13]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFEF00000020))
\top_left_0[14]_i_1
(.I0(dout_0[14]),
.I1(cycle[2]),
.I2(\cycle_reg[1]_rep_n_0 ),
.I3(\cycle_reg[0]_rep_n_0 ),
.I4(cycle[3]),
.I5(dout_1[14]),
.O(\top_left_0[14]_i_1_n_0 ));
LUT6 #(
.INIT(64'h8000700010000000))
\top_left_0[15]_i_1
(.I0(cycle[2]),
.I1(cycle[3]),
.I2(rst),
.I3(active),
.I4(\cycle_reg[0]_rep_n_0 ),
.I5(\cycle_reg[1]_rep_n_0 ),
.O(top_left_0));
LUT6 #(
.INIT(64'hFFFFFFEF00000020))
\top_left_0[15]_i_2
(.I0(dout_0[15]),
.I1(cycle[2]),
.I2(\cycle_reg[1]_rep_n_0 ),
.I3(\cycle_reg[0]_rep_n_0 ),
.I4(cycle[3]),
.I5(dout_1[15]),
.O(\top_left_0[15]_i_2_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFEF00000020))
\top_left_0[1]_i_1
(.I0(dout_0[1]),
.I1(cycle[2]),
.I2(\cycle_reg[1]_rep_n_0 ),
.I3(\cycle_reg[0]_rep_n_0 ),
.I4(cycle[3]),
.I5(dout_1[1]),
.O(\top_left_0[1]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFEF00000020))
\top_left_0[2]_i_1
(.I0(dout_0[2]),
.I1(cycle[2]),
.I2(\cycle_reg[1]_rep_n_0 ),
.I3(\cycle_reg[0]_rep_n_0 ),
.I4(cycle[3]),
.I5(dout_1[2]),
.O(\top_left_0[2]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFEF00000020))
\top_left_0[3]_i_1
(.I0(dout_0[3]),
.I1(cycle[2]),
.I2(\cycle_reg[1]_rep_n_0 ),
.I3(\cycle_reg[0]_rep_n_0 ),
.I4(cycle[3]),
.I5(dout_1[3]),
.O(\top_left_0[3]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFEF00000020))
\top_left_0[4]_i_1
(.I0(dout_0[4]),
.I1(cycle[2]),
.I2(\cycle_reg[1]_rep_n_0 ),
.I3(\cycle_reg[0]_rep_n_0 ),
.I4(cycle[3]),
.I5(dout_1[4]),
.O(\top_left_0[4]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFEF00000020))
\top_left_0[5]_i_1
(.I0(dout_0[5]),
.I1(cycle[2]),
.I2(\cycle_reg[1]_rep_n_0 ),
.I3(\cycle_reg[0]_rep_n_0 ),
.I4(cycle[3]),
.I5(dout_1[5]),
.O(\top_left_0[5]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFEF00000020))
\top_left_0[6]_i_1
(.I0(dout_0[6]),
.I1(cycle[2]),
.I2(\cycle_reg[1]_rep_n_0 ),
.I3(\cycle_reg[0]_rep_n_0 ),
.I4(cycle[3]),
.I5(dout_1[6]),
.O(\top_left_0[6]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFEF00000020))
\top_left_0[7]_i_1
(.I0(dout_0[7]),
.I1(cycle[2]),
.I2(\cycle_reg[1]_rep_n_0 ),
.I3(\cycle_reg[0]_rep_n_0 ),
.I4(cycle[3]),
.I5(dout_1[7]),
.O(\top_left_0[7]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFEF00000020))
\top_left_0[8]_i_1
(.I0(dout_0[8]),
.I1(cycle[2]),
.I2(\cycle_reg[1]_rep_n_0 ),
.I3(\cycle_reg[0]_rep_n_0 ),
.I4(cycle[3]),
.I5(dout_1[8]),
.O(\top_left_0[8]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFEF00000020))
\top_left_0[9]_i_1
(.I0(dout_0[9]),
.I1(cycle[2]),
.I2(\cycle_reg[1]_rep_n_0 ),
.I3(\cycle_reg[0]_rep_n_0 ),
.I4(cycle[3]),
.I5(dout_1[9]),
.O(\top_left_0[9]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\top_left_0_reg[0]
(.C(clk_x16),
.CE(top_left_0),
.D(\top_left_0[0]_i_1_n_0 ),
.Q(\top_left_0_reg_n_0_[0] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\top_left_0_reg[10]
(.C(clk_x16),
.CE(top_left_0),
.D(\top_left_0[10]_i_1_n_0 ),
.Q(\top_left_0_reg_n_0_[10] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\top_left_0_reg[11]
(.C(clk_x16),
.CE(top_left_0),
.D(\top_left_0[11]_i_1_n_0 ),
.Q(\top_left_0_reg_n_0_[11] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\top_left_0_reg[12]
(.C(clk_x16),
.CE(top_left_0),
.D(\top_left_0[12]_i_1_n_0 ),
.Q(\top_left_0_reg_n_0_[12] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\top_left_0_reg[13]
(.C(clk_x16),
.CE(top_left_0),
.D(\top_left_0[13]_i_1_n_0 ),
.Q(\top_left_0_reg_n_0_[13] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\top_left_0_reg[14]
(.C(clk_x16),
.CE(top_left_0),
.D(\top_left_0[14]_i_1_n_0 ),
.Q(\top_left_0_reg_n_0_[14] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\top_left_0_reg[15]
(.C(clk_x16),
.CE(top_left_0),
.D(\top_left_0[15]_i_2_n_0 ),
.Q(\top_left_0_reg_n_0_[15] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\top_left_0_reg[1]
(.C(clk_x16),
.CE(top_left_0),
.D(\top_left_0[1]_i_1_n_0 ),
.Q(\top_left_0_reg_n_0_[1] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\top_left_0_reg[2]
(.C(clk_x16),
.CE(top_left_0),
.D(\top_left_0[2]_i_1_n_0 ),
.Q(\top_left_0_reg_n_0_[2] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\top_left_0_reg[3]
(.C(clk_x16),
.CE(top_left_0),
.D(\top_left_0[3]_i_1_n_0 ),
.Q(\top_left_0_reg_n_0_[3] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\top_left_0_reg[4]
(.C(clk_x16),
.CE(top_left_0),
.D(\top_left_0[4]_i_1_n_0 ),
.Q(\top_left_0_reg_n_0_[4] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\top_left_0_reg[5]
(.C(clk_x16),
.CE(top_left_0),
.D(\top_left_0[5]_i_1_n_0 ),
.Q(\top_left_0_reg_n_0_[5] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\top_left_0_reg[6]
(.C(clk_x16),
.CE(top_left_0),
.D(\top_left_0[6]_i_1_n_0 ),
.Q(\top_left_0_reg_n_0_[6] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\top_left_0_reg[7]
(.C(clk_x16),
.CE(top_left_0),
.D(\top_left_0[7]_i_1_n_0 ),
.Q(\top_left_0_reg_n_0_[7] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\top_left_0_reg[8]
(.C(clk_x16),
.CE(top_left_0),
.D(\top_left_0[8]_i_1_n_0 ),
.Q(\top_left_0_reg_n_0_[8] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\top_left_0_reg[9]
(.C(clk_x16),
.CE(top_left_0),
.D(\top_left_0[9]_i_1_n_0 ),
.Q(\top_left_0_reg_n_0_[9] ),
.R(1'b0));
LUT6 #(
.INIT(64'hAAABAAAAAAA8AAAA))
\top_left_1[0]_i_1
(.I0(dout_1[0]),
.I1(\cycle_reg[0]_rep_n_0 ),
.I2(cycle[3]),
.I3(\cycle_reg[1]_rep__0_n_0 ),
.I4(cycle[2]),
.I5(\bottom_left_0_reg_n_0_[0] ),
.O(\top_left_1[0]_i_1_n_0 ));
LUT6 #(
.INIT(64'hAAABAAAAAAA8AAAA))
\top_left_1[10]_i_1
(.I0(dout_1[10]),
.I1(\cycle_reg[0]_rep_n_0 ),
.I2(cycle[3]),
.I3(\cycle_reg[1]_rep__0_n_0 ),
.I4(cycle[2]),
.I5(\bottom_left_0_reg_n_0_[10] ),
.O(\top_left_1[10]_i_1_n_0 ));
LUT6 #(
.INIT(64'hAAABAAAAAAA8AAAA))
\top_left_1[11]_i_1
(.I0(dout_1[11]),
.I1(\cycle_reg[0]_rep_n_0 ),
.I2(cycle[3]),
.I3(\cycle_reg[1]_rep__0_n_0 ),
.I4(cycle[2]),
.I5(\bottom_left_0_reg_n_0_[11] ),
.O(\top_left_1[11]_i_1_n_0 ));
LUT6 #(
.INIT(64'hAAABAAAAAAA8AAAA))
\top_left_1[12]_i_1
(.I0(dout_1[12]),
.I1(\cycle_reg[0]_rep_n_0 ),
.I2(cycle[3]),
.I3(\cycle_reg[1]_rep__0_n_0 ),
.I4(\cycle_reg[2]_rep_n_0 ),
.I5(\bottom_left_0_reg_n_0_[12] ),
.O(\top_left_1[12]_i_1_n_0 ));
LUT6 #(
.INIT(64'hAAABAAAAAAA8AAAA))
\top_left_1[13]_i_1
(.I0(dout_1[13]),
.I1(\cycle_reg[0]_rep_n_0 ),
.I2(cycle[3]),
.I3(\cycle_reg[1]_rep__0_n_0 ),
.I4(\cycle_reg[2]_rep_n_0 ),
.I5(\bottom_left_0_reg_n_0_[13] ),
.O(\top_left_1[13]_i_1_n_0 ));
LUT6 #(
.INIT(64'hAAABAAAAAAA8AAAA))
\top_left_1[14]_i_1
(.I0(dout_1[14]),
.I1(\cycle_reg[0]_rep_n_0 ),
.I2(cycle[3]),
.I3(\cycle_reg[1]_rep__0_n_0 ),
.I4(\cycle_reg[2]_rep_n_0 ),
.I5(\bottom_left_0_reg_n_0_[14] ),
.O(\top_left_1[14]_i_1_n_0 ));
LUT4 #(
.INIT(16'h0040))
\top_left_1[15]_i_1
(.I0(\cycle_reg[0]_rep_n_0 ),
.I1(active),
.I2(rst),
.I3(\cycle_reg[1]_rep__0_n_0 ),
.O(bottom_right_1));
LUT6 #(
.INIT(64'hAAABAAAAAAA8AAAA))
\top_left_1[15]_i_2
(.I0(dout_1[15]),
.I1(\cycle_reg[0]_rep_n_0 ),
.I2(cycle[3]),
.I3(\cycle_reg[1]_rep__0_n_0 ),
.I4(\cycle_reg[2]_rep_n_0 ),
.I5(\bottom_left_0_reg_n_0_[15] ),
.O(\top_left_1[15]_i_2_n_0 ));
LUT6 #(
.INIT(64'hAAABAAAAAAA8AAAA))
\top_left_1[1]_i_1
(.I0(dout_1[1]),
.I1(\cycle_reg[0]_rep_n_0 ),
.I2(cycle[3]),
.I3(\cycle_reg[1]_rep__0_n_0 ),
.I4(cycle[2]),
.I5(\bottom_left_0_reg_n_0_[1] ),
.O(\top_left_1[1]_i_1_n_0 ));
LUT6 #(
.INIT(64'hAAABAAAAAAA8AAAA))
\top_left_1[2]_i_1
(.I0(dout_1[2]),
.I1(\cycle_reg[0]_rep_n_0 ),
.I2(cycle[3]),
.I3(\cycle_reg[1]_rep__0_n_0 ),
.I4(cycle[2]),
.I5(\bottom_left_0_reg_n_0_[2] ),
.O(\top_left_1[2]_i_1_n_0 ));
LUT6 #(
.INIT(64'hAAABAAAAAAA8AAAA))
\top_left_1[3]_i_1
(.I0(dout_1[3]),
.I1(\cycle_reg[0]_rep_n_0 ),
.I2(cycle[3]),
.I3(\cycle_reg[1]_rep__0_n_0 ),
.I4(cycle[2]),
.I5(\bottom_left_0_reg_n_0_[3] ),
.O(\top_left_1[3]_i_1_n_0 ));
LUT6 #(
.INIT(64'hAAABAAAAAAA8AAAA))
\top_left_1[4]_i_1
(.I0(dout_1[4]),
.I1(\cycle_reg[0]_rep_n_0 ),
.I2(cycle[3]),
.I3(\cycle_reg[1]_rep__0_n_0 ),
.I4(cycle[2]),
.I5(\bottom_left_0_reg_n_0_[4] ),
.O(\top_left_1[4]_i_1_n_0 ));
LUT6 #(
.INIT(64'hAAABAAAAAAA8AAAA))
\top_left_1[5]_i_1
(.I0(dout_1[5]),
.I1(\cycle_reg[0]_rep_n_0 ),
.I2(cycle[3]),
.I3(\cycle_reg[1]_rep__0_n_0 ),
.I4(cycle[2]),
.I5(\bottom_left_0_reg_n_0_[5] ),
.O(\top_left_1[5]_i_1_n_0 ));
LUT6 #(
.INIT(64'hAAABAAAAAAA8AAAA))
\top_left_1[6]_i_1
(.I0(dout_1[6]),
.I1(\cycle_reg[0]_rep_n_0 ),
.I2(cycle[3]),
.I3(\cycle_reg[1]_rep__0_n_0 ),
.I4(cycle[2]),
.I5(\bottom_left_0_reg_n_0_[6] ),
.O(\top_left_1[6]_i_1_n_0 ));
LUT6 #(
.INIT(64'hAAABAAAAAAA8AAAA))
\top_left_1[7]_i_1
(.I0(dout_1[7]),
.I1(\cycle_reg[0]_rep_n_0 ),
.I2(cycle[3]),
.I3(\cycle_reg[1]_rep__0_n_0 ),
.I4(cycle[2]),
.I5(\bottom_left_0_reg_n_0_[7] ),
.O(\top_left_1[7]_i_1_n_0 ));
LUT6 #(
.INIT(64'hAAABAAAAAAA8AAAA))
\top_left_1[8]_i_1
(.I0(dout_1[8]),
.I1(\cycle_reg[0]_rep_n_0 ),
.I2(cycle[3]),
.I3(\cycle_reg[1]_rep__0_n_0 ),
.I4(cycle[2]),
.I5(\bottom_left_0_reg_n_0_[8] ),
.O(\top_left_1[8]_i_1_n_0 ));
LUT6 #(
.INIT(64'hAAABAAAAAAA8AAAA))
\top_left_1[9]_i_1
(.I0(dout_1[9]),
.I1(\cycle_reg[0]_rep_n_0 ),
.I2(cycle[3]),
.I3(\cycle_reg[1]_rep__0_n_0 ),
.I4(cycle[2]),
.I5(\bottom_left_0_reg_n_0_[9] ),
.O(\top_left_1[9]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\top_left_1_reg[0]
(.C(clk_x16),
.CE(bottom_right_1),
.D(\top_left_1[0]_i_1_n_0 ),
.Q(top_left_1[0]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\top_left_1_reg[10]
(.C(clk_x16),
.CE(bottom_right_1),
.D(\top_left_1[10]_i_1_n_0 ),
.Q(top_left_1[10]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\top_left_1_reg[11]
(.C(clk_x16),
.CE(bottom_right_1),
.D(\top_left_1[11]_i_1_n_0 ),
.Q(top_left_1[11]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\top_left_1_reg[12]
(.C(clk_x16),
.CE(bottom_right_1),
.D(\top_left_1[12]_i_1_n_0 ),
.Q(top_left_1[12]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\top_left_1_reg[13]
(.C(clk_x16),
.CE(bottom_right_1),
.D(\top_left_1[13]_i_1_n_0 ),
.Q(top_left_1[13]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\top_left_1_reg[14]
(.C(clk_x16),
.CE(bottom_right_1),
.D(\top_left_1[14]_i_1_n_0 ),
.Q(top_left_1[14]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\top_left_1_reg[15]
(.C(clk_x16),
.CE(bottom_right_1),
.D(\top_left_1[15]_i_2_n_0 ),
.Q(top_left_1[15]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\top_left_1_reg[1]
(.C(clk_x16),
.CE(bottom_right_1),
.D(\top_left_1[1]_i_1_n_0 ),
.Q(top_left_1[1]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\top_left_1_reg[2]
(.C(clk_x16),
.CE(bottom_right_1),
.D(\top_left_1[2]_i_1_n_0 ),
.Q(top_left_1[2]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\top_left_1_reg[3]
(.C(clk_x16),
.CE(bottom_right_1),
.D(\top_left_1[3]_i_1_n_0 ),
.Q(top_left_1[3]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\top_left_1_reg[4]
(.C(clk_x16),
.CE(bottom_right_1),
.D(\top_left_1[4]_i_1_n_0 ),
.Q(top_left_1[4]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\top_left_1_reg[5]
(.C(clk_x16),
.CE(bottom_right_1),
.D(\top_left_1[5]_i_1_n_0 ),
.Q(top_left_1[5]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\top_left_1_reg[6]
(.C(clk_x16),
.CE(bottom_right_1),
.D(\top_left_1[6]_i_1_n_0 ),
.Q(top_left_1[6]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\top_left_1_reg[7]
(.C(clk_x16),
.CE(bottom_right_1),
.D(\top_left_1[7]_i_1_n_0 ),
.Q(top_left_1[7]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\top_left_1_reg[8]
(.C(clk_x16),
.CE(bottom_right_1),
.D(\top_left_1[8]_i_1_n_0 ),
.Q(top_left_1[8]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\top_left_1_reg[9]
(.C(clk_x16),
.CE(bottom_right_1),
.D(\top_left_1[9]_i_1_n_0 ),
.Q(top_left_1[9]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\top_reg[0]
(.C(clk_x16),
.CE(x),
.D(\cache_reg[9]_2 [0]),
.Q(\top_reg_n_0_[0] ),
.R(top));
FDRE #(
.INIT(1'b0))
\top_reg[10]
(.C(clk_x16),
.CE(x),
.D(\cache_reg[9]_2 [10]),
.Q(\top_reg_n_0_[10] ),
.R(top));
FDRE #(
.INIT(1'b0))
\top_reg[11]
(.C(clk_x16),
.CE(x),
.D(\cache_reg[9]_2 [11]),
.Q(\top_reg_n_0_[11] ),
.R(top));
FDRE #(
.INIT(1'b0))
\top_reg[12]
(.C(clk_x16),
.CE(x),
.D(\cache_reg[9]_2 [12]),
.Q(\top_reg_n_0_[12] ),
.R(top));
FDRE #(
.INIT(1'b0))
\top_reg[13]
(.C(clk_x16),
.CE(x),
.D(\cache_reg[9]_2 [13]),
.Q(\top_reg_n_0_[13] ),
.R(top));
FDRE #(
.INIT(1'b0))
\top_reg[14]
(.C(clk_x16),
.CE(x),
.D(\cache_reg[9]_2 [14]),
.Q(\top_reg_n_0_[14] ),
.R(top));
FDRE #(
.INIT(1'b0))
\top_reg[15]
(.C(clk_x16),
.CE(x),
.D(\cache_reg[9]_2 [15]),
.Q(\top_reg_n_0_[15] ),
.R(top));
FDRE #(
.INIT(1'b0))
\top_reg[1]
(.C(clk_x16),
.CE(x),
.D(\cache_reg[9]_2 [1]),
.Q(\top_reg_n_0_[1] ),
.R(top));
FDRE #(
.INIT(1'b0))
\top_reg[2]
(.C(clk_x16),
.CE(x),
.D(\cache_reg[9]_2 [2]),
.Q(\top_reg_n_0_[2] ),
.R(top));
FDRE #(
.INIT(1'b0))
\top_reg[3]
(.C(clk_x16),
.CE(x),
.D(\cache_reg[9]_2 [3]),
.Q(\top_reg_n_0_[3] ),
.R(top));
FDRE #(
.INIT(1'b0))
\top_reg[4]
(.C(clk_x16),
.CE(x),
.D(\cache_reg[9]_2 [4]),
.Q(\top_reg_n_0_[4] ),
.R(top));
FDRE #(
.INIT(1'b0))
\top_reg[5]
(.C(clk_x16),
.CE(x),
.D(\cache_reg[9]_2 [5]),
.Q(\top_reg_n_0_[5] ),
.R(top));
FDRE #(
.INIT(1'b0))
\top_reg[6]
(.C(clk_x16),
.CE(x),
.D(\cache_reg[9]_2 [6]),
.Q(\top_reg_n_0_[6] ),
.R(top));
FDRE #(
.INIT(1'b0))
\top_reg[7]
(.C(clk_x16),
.CE(x),
.D(\cache_reg[9]_2 [7]),
.Q(\top_reg_n_0_[7] ),
.R(top));
FDRE #(
.INIT(1'b0))
\top_reg[8]
(.C(clk_x16),
.CE(x),
.D(\cache_reg[9]_2 [8]),
.Q(\top_reg_n_0_[8] ),
.R(top));
FDRE #(
.INIT(1'b0))
\top_reg[9]
(.C(clk_x16),
.CE(x),
.D(\cache_reg[9]_2 [9]),
.Q(\top_reg_n_0_[9] ),
.R(top));
LUT6 #(
.INIT(64'hFFFFFFEF00000020))
\top_right_0[0]_i_1
(.I0(top_left_1[0]),
.I1(\cycle_reg[1]_rep__0_n_0 ),
.I2(cycle[0]),
.I3(\cycle_reg[2]_rep_n_0 ),
.I4(cycle[3]),
.I5(dout_1[0]),
.O(\top_right_0[0]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFEF00000020))
\top_right_0[10]_i_1
(.I0(top_left_1[10]),
.I1(\cycle_reg[1]_rep__0_n_0 ),
.I2(cycle[0]),
.I3(\cycle_reg[2]_rep_n_0 ),
.I4(cycle[3]),
.I5(dout_1[10]),
.O(\top_right_0[10]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFEF00000020))
\top_right_0[11]_i_1
(.I0(top_left_1[11]),
.I1(\cycle_reg[1]_rep__0_n_0 ),
.I2(cycle[0]),
.I3(\cycle_reg[2]_rep_n_0 ),
.I4(cycle[3]),
.I5(dout_1[11]),
.O(\top_right_0[11]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFEF00000020))
\top_right_0[12]_i_1
(.I0(top_left_1[12]),
.I1(\cycle_reg[1]_rep__0_n_0 ),
.I2(cycle[0]),
.I3(\cycle_reg[2]_rep_n_0 ),
.I4(cycle[3]),
.I5(dout_1[12]),
.O(\top_right_0[12]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFEF00000020))
\top_right_0[13]_i_1
(.I0(top_left_1[13]),
.I1(\cycle_reg[1]_rep__0_n_0 ),
.I2(cycle[0]),
.I3(\cycle_reg[2]_rep_n_0 ),
.I4(cycle[3]),
.I5(dout_1[13]),
.O(\top_right_0[13]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFEF00000020))
\top_right_0[14]_i_1
(.I0(top_left_1[14]),
.I1(\cycle_reg[1]_rep__0_n_0 ),
.I2(cycle[0]),
.I3(\cycle_reg[2]_rep_n_0 ),
.I4(cycle[3]),
.I5(dout_1[14]),
.O(\top_right_0[14]_i_1_n_0 ));
LUT6 #(
.INIT(64'h0880000080080800))
\top_right_0[15]_i_1
(.I0(rst),
.I1(active),
.I2(cycle[3]),
.I3(cycle[0]),
.I4(\cycle_reg[1]_rep__0_n_0 ),
.I5(\cycle_reg[2]_rep_n_0 ),
.O(top_right_0));
LUT6 #(
.INIT(64'hFFFFFFEF00000020))
\top_right_0[15]_i_2
(.I0(top_left_1[15]),
.I1(\cycle_reg[1]_rep__0_n_0 ),
.I2(cycle[0]),
.I3(\cycle_reg[2]_rep_n_0 ),
.I4(cycle[3]),
.I5(dout_1[15]),
.O(\top_right_0[15]_i_2_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFEF00000020))
\top_right_0[1]_i_1
(.I0(top_left_1[1]),
.I1(\cycle_reg[1]_rep__0_n_0 ),
.I2(cycle[0]),
.I3(\cycle_reg[2]_rep_n_0 ),
.I4(cycle[3]),
.I5(dout_1[1]),
.O(\top_right_0[1]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFEF00000020))
\top_right_0[2]_i_1
(.I0(top_left_1[2]),
.I1(\cycle_reg[1]_rep__0_n_0 ),
.I2(cycle[0]),
.I3(\cycle_reg[2]_rep_n_0 ),
.I4(cycle[3]),
.I5(dout_1[2]),
.O(\top_right_0[2]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFEF00000020))
\top_right_0[3]_i_1
(.I0(top_left_1[3]),
.I1(\cycle_reg[1]_rep__0_n_0 ),
.I2(cycle[0]),
.I3(\cycle_reg[2]_rep_n_0 ),
.I4(cycle[3]),
.I5(dout_1[3]),
.O(\top_right_0[3]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFEF00000020))
\top_right_0[4]_i_1
(.I0(top_left_1[4]),
.I1(\cycle_reg[1]_rep__0_n_0 ),
.I2(cycle[0]),
.I3(\cycle_reg[2]_rep_n_0 ),
.I4(cycle[3]),
.I5(dout_1[4]),
.O(\top_right_0[4]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFEF00000020))
\top_right_0[5]_i_1
(.I0(top_left_1[5]),
.I1(\cycle_reg[1]_rep__0_n_0 ),
.I2(cycle[0]),
.I3(\cycle_reg[2]_rep_n_0 ),
.I4(cycle[3]),
.I5(dout_1[5]),
.O(\top_right_0[5]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFEF00000020))
\top_right_0[6]_i_1
(.I0(top_left_1[6]),
.I1(\cycle_reg[1]_rep__0_n_0 ),
.I2(cycle[0]),
.I3(\cycle_reg[2]_rep_n_0 ),
.I4(cycle[3]),
.I5(dout_1[6]),
.O(\top_right_0[6]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFEF00000020))
\top_right_0[7]_i_1
(.I0(top_left_1[7]),
.I1(\cycle_reg[1]_rep__0_n_0 ),
.I2(cycle[0]),
.I3(\cycle_reg[2]_rep_n_0 ),
.I4(cycle[3]),
.I5(dout_1[7]),
.O(\top_right_0[7]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFEF00000020))
\top_right_0[8]_i_1
(.I0(top_left_1[8]),
.I1(\cycle_reg[1]_rep__0_n_0 ),
.I2(cycle[0]),
.I3(\cycle_reg[2]_rep_n_0 ),
.I4(cycle[3]),
.I5(dout_1[8]),
.O(\top_right_0[8]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFEF00000020))
\top_right_0[9]_i_1
(.I0(top_left_1[9]),
.I1(\cycle_reg[1]_rep__0_n_0 ),
.I2(cycle[0]),
.I3(\cycle_reg[2]_rep_n_0 ),
.I4(cycle[3]),
.I5(dout_1[9]),
.O(\top_right_0[9]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\top_right_0_reg[0]
(.C(clk_x16),
.CE(top_right_0),
.D(\top_right_0[0]_i_1_n_0 ),
.Q(\top_right_0_reg_n_0_[0] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\top_right_0_reg[10]
(.C(clk_x16),
.CE(top_right_0),
.D(\top_right_0[10]_i_1_n_0 ),
.Q(\top_right_0_reg_n_0_[10] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\top_right_0_reg[11]
(.C(clk_x16),
.CE(top_right_0),
.D(\top_right_0[11]_i_1_n_0 ),
.Q(\top_right_0_reg_n_0_[11] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\top_right_0_reg[12]
(.C(clk_x16),
.CE(top_right_0),
.D(\top_right_0[12]_i_1_n_0 ),
.Q(\top_right_0_reg_n_0_[12] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\top_right_0_reg[13]
(.C(clk_x16),
.CE(top_right_0),
.D(\top_right_0[13]_i_1_n_0 ),
.Q(\top_right_0_reg_n_0_[13] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\top_right_0_reg[14]
(.C(clk_x16),
.CE(top_right_0),
.D(\top_right_0[14]_i_1_n_0 ),
.Q(\top_right_0_reg_n_0_[14] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\top_right_0_reg[15]
(.C(clk_x16),
.CE(top_right_0),
.D(\top_right_0[15]_i_2_n_0 ),
.Q(\top_right_0_reg_n_0_[15] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\top_right_0_reg[1]
(.C(clk_x16),
.CE(top_right_0),
.D(\top_right_0[1]_i_1_n_0 ),
.Q(\top_right_0_reg_n_0_[1] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\top_right_0_reg[2]
(.C(clk_x16),
.CE(top_right_0),
.D(\top_right_0[2]_i_1_n_0 ),
.Q(\top_right_0_reg_n_0_[2] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\top_right_0_reg[3]
(.C(clk_x16),
.CE(top_right_0),
.D(\top_right_0[3]_i_1_n_0 ),
.Q(\top_right_0_reg_n_0_[3] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\top_right_0_reg[4]
(.C(clk_x16),
.CE(top_right_0),
.D(\top_right_0[4]_i_1_n_0 ),
.Q(\top_right_0_reg_n_0_[4] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\top_right_0_reg[5]
(.C(clk_x16),
.CE(top_right_0),
.D(\top_right_0[5]_i_1_n_0 ),
.Q(\top_right_0_reg_n_0_[5] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\top_right_0_reg[6]
(.C(clk_x16),
.CE(top_right_0),
.D(\top_right_0[6]_i_1_n_0 ),
.Q(\top_right_0_reg_n_0_[6] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\top_right_0_reg[7]
(.C(clk_x16),
.CE(top_right_0),
.D(\top_right_0[7]_i_1_n_0 ),
.Q(\top_right_0_reg_n_0_[7] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\top_right_0_reg[8]
(.C(clk_x16),
.CE(top_right_0),
.D(\top_right_0[8]_i_1_n_0 ),
.Q(\top_right_0_reg_n_0_[8] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\top_right_0_reg[9]
(.C(clk_x16),
.CE(top_right_0),
.D(\top_right_0[9]_i_1_n_0 ),
.Q(\top_right_0_reg_n_0_[9] ),
.R(1'b0));
LUT5 #(
.INIT(32'hB8BBB888))
\top_right_1[0]_i_1
(.I0(dout_1[0]),
.I1(\top_right_1[15]_i_2_n_0 ),
.I2(\bottom_right_0_reg_n_0_[0] ),
.I3(\cycle_reg[2]_rep_n_0 ),
.I4(\top_left_0_reg_n_0_[0] ),
.O(\top_right_1[0]_i_1_n_0 ));
LUT5 #(
.INIT(32'hB8BBB888))
\top_right_1[10]_i_1
(.I0(dout_1[10]),
.I1(\top_right_1[15]_i_2_n_0 ),
.I2(\bottom_right_0_reg_n_0_[10] ),
.I3(\cycle_reg[2]_rep_n_0 ),
.I4(\top_left_0_reg_n_0_[10] ),
.O(\top_right_1[10]_i_1_n_0 ));
LUT5 #(
.INIT(32'hB8BBB888))
\top_right_1[11]_i_1
(.I0(dout_1[11]),
.I1(\top_right_1[15]_i_2_n_0 ),
.I2(\bottom_right_0_reg_n_0_[11] ),
.I3(\cycle_reg[2]_rep_n_0 ),
.I4(\top_left_0_reg_n_0_[11] ),
.O(\top_right_1[11]_i_1_n_0 ));
LUT5 #(
.INIT(32'hB8BBB888))
\top_right_1[12]_i_1
(.I0(dout_1[12]),
.I1(\top_right_1[15]_i_2_n_0 ),
.I2(\bottom_right_0_reg_n_0_[12] ),
.I3(\cycle_reg[2]_rep_n_0 ),
.I4(\top_left_0_reg_n_0_[12] ),
.O(\top_right_1[12]_i_1_n_0 ));
LUT5 #(
.INIT(32'hB8BBB888))
\top_right_1[13]_i_1
(.I0(dout_1[13]),
.I1(\top_right_1[15]_i_2_n_0 ),
.I2(\bottom_right_0_reg_n_0_[13] ),
.I3(\cycle_reg[2]_rep_n_0 ),
.I4(\top_left_0_reg_n_0_[13] ),
.O(\top_right_1[13]_i_1_n_0 ));
LUT5 #(
.INIT(32'hB8BBB888))
\top_right_1[14]_i_1
(.I0(dout_1[14]),
.I1(\top_right_1[15]_i_2_n_0 ),
.I2(\bottom_right_0_reg_n_0_[14] ),
.I3(\cycle_reg[2]_rep_n_0 ),
.I4(\top_left_0_reg_n_0_[14] ),
.O(\top_right_1[14]_i_1_n_0 ));
LUT5 #(
.INIT(32'hB8BBB888))
\top_right_1[15]_i_1
(.I0(dout_1[15]),
.I1(\top_right_1[15]_i_2_n_0 ),
.I2(\bottom_right_0_reg_n_0_[15] ),
.I3(\cycle_reg[2]_rep_n_0 ),
.I4(\top_left_0_reg_n_0_[15] ),
.O(\top_right_1[15]_i_1_n_0 ));
LUT3 #(
.INIT(8'hFE))
\top_right_1[15]_i_2
(.I0(cycle[3]),
.I1(cycle[0]),
.I2(\cycle_reg[1]_rep__0_n_0 ),
.O(\top_right_1[15]_i_2_n_0 ));
LUT5 #(
.INIT(32'hB8BBB888))
\top_right_1[1]_i_1
(.I0(dout_1[1]),
.I1(\top_right_1[15]_i_2_n_0 ),
.I2(\bottom_right_0_reg_n_0_[1] ),
.I3(\cycle_reg[2]_rep_n_0 ),
.I4(\top_left_0_reg_n_0_[1] ),
.O(\top_right_1[1]_i_1_n_0 ));
LUT5 #(
.INIT(32'hB8BBB888))
\top_right_1[2]_i_1
(.I0(dout_1[2]),
.I1(\top_right_1[15]_i_2_n_0 ),
.I2(\bottom_right_0_reg_n_0_[2] ),
.I3(\cycle_reg[2]_rep_n_0 ),
.I4(\top_left_0_reg_n_0_[2] ),
.O(\top_right_1[2]_i_1_n_0 ));
LUT5 #(
.INIT(32'hB8BBB888))
\top_right_1[3]_i_1
(.I0(dout_1[3]),
.I1(\top_right_1[15]_i_2_n_0 ),
.I2(\bottom_right_0_reg_n_0_[3] ),
.I3(\cycle_reg[2]_rep_n_0 ),
.I4(\top_left_0_reg_n_0_[3] ),
.O(\top_right_1[3]_i_1_n_0 ));
LUT5 #(
.INIT(32'hB8BBB888))
\top_right_1[4]_i_1
(.I0(dout_1[4]),
.I1(\top_right_1[15]_i_2_n_0 ),
.I2(\bottom_right_0_reg_n_0_[4] ),
.I3(\cycle_reg[2]_rep_n_0 ),
.I4(\top_left_0_reg_n_0_[4] ),
.O(\top_right_1[4]_i_1_n_0 ));
LUT5 #(
.INIT(32'hB8BBB888))
\top_right_1[5]_i_1
(.I0(dout_1[5]),
.I1(\top_right_1[15]_i_2_n_0 ),
.I2(\bottom_right_0_reg_n_0_[5] ),
.I3(\cycle_reg[2]_rep_n_0 ),
.I4(\top_left_0_reg_n_0_[5] ),
.O(\top_right_1[5]_i_1_n_0 ));
LUT5 #(
.INIT(32'hB8BBB888))
\top_right_1[6]_i_1
(.I0(dout_1[6]),
.I1(\top_right_1[15]_i_2_n_0 ),
.I2(\bottom_right_0_reg_n_0_[6] ),
.I3(\cycle_reg[2]_rep_n_0 ),
.I4(\top_left_0_reg_n_0_[6] ),
.O(\top_right_1[6]_i_1_n_0 ));
LUT5 #(
.INIT(32'hB8BBB888))
\top_right_1[7]_i_1
(.I0(dout_1[7]),
.I1(\top_right_1[15]_i_2_n_0 ),
.I2(\bottom_right_0_reg_n_0_[7] ),
.I3(\cycle_reg[2]_rep_n_0 ),
.I4(\top_left_0_reg_n_0_[7] ),
.O(\top_right_1[7]_i_1_n_0 ));
LUT5 #(
.INIT(32'hB8BBB888))
\top_right_1[8]_i_1
(.I0(dout_1[8]),
.I1(\top_right_1[15]_i_2_n_0 ),
.I2(\bottom_right_0_reg_n_0_[8] ),
.I3(\cycle_reg[2]_rep_n_0 ),
.I4(\top_left_0_reg_n_0_[8] ),
.O(\top_right_1[8]_i_1_n_0 ));
LUT5 #(
.INIT(32'hB8BBB888))
\top_right_1[9]_i_1
(.I0(dout_1[9]),
.I1(\top_right_1[15]_i_2_n_0 ),
.I2(\bottom_right_0_reg_n_0_[9] ),
.I3(\cycle_reg[2]_rep_n_0 ),
.I4(\top_left_0_reg_n_0_[9] ),
.O(\top_right_1[9]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\top_right_1_reg[0]
(.C(clk_x16),
.CE(top_right_1),
.D(\top_right_1[0]_i_1_n_0 ),
.Q(\top_right_1_reg_n_0_[0] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\top_right_1_reg[10]
(.C(clk_x16),
.CE(top_right_1),
.D(\top_right_1[10]_i_1_n_0 ),
.Q(\top_right_1_reg_n_0_[10] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\top_right_1_reg[11]
(.C(clk_x16),
.CE(top_right_1),
.D(\top_right_1[11]_i_1_n_0 ),
.Q(\top_right_1_reg_n_0_[11] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\top_right_1_reg[12]
(.C(clk_x16),
.CE(top_right_1),
.D(\top_right_1[12]_i_1_n_0 ),
.Q(\top_right_1_reg_n_0_[12] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\top_right_1_reg[13]
(.C(clk_x16),
.CE(top_right_1),
.D(\top_right_1[13]_i_1_n_0 ),
.Q(\top_right_1_reg_n_0_[13] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\top_right_1_reg[14]
(.C(clk_x16),
.CE(top_right_1),
.D(\top_right_1[14]_i_1_n_0 ),
.Q(\top_right_1_reg_n_0_[14] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\top_right_1_reg[15]
(.C(clk_x16),
.CE(top_right_1),
.D(\top_right_1[15]_i_1_n_0 ),
.Q(\top_right_1_reg_n_0_[15] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\top_right_1_reg[1]
(.C(clk_x16),
.CE(top_right_1),
.D(\top_right_1[1]_i_1_n_0 ),
.Q(\top_right_1_reg_n_0_[1] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\top_right_1_reg[2]
(.C(clk_x16),
.CE(top_right_1),
.D(\top_right_1[2]_i_1_n_0 ),
.Q(\top_right_1_reg_n_0_[2] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\top_right_1_reg[3]
(.C(clk_x16),
.CE(top_right_1),
.D(\top_right_1[3]_i_1_n_0 ),
.Q(\top_right_1_reg_n_0_[3] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\top_right_1_reg[4]
(.C(clk_x16),
.CE(top_right_1),
.D(\top_right_1[4]_i_1_n_0 ),
.Q(\top_right_1_reg_n_0_[4] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\top_right_1_reg[5]
(.C(clk_x16),
.CE(top_right_1),
.D(\top_right_1[5]_i_1_n_0 ),
.Q(\top_right_1_reg_n_0_[5] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\top_right_1_reg[6]
(.C(clk_x16),
.CE(top_right_1),
.D(\top_right_1[6]_i_1_n_0 ),
.Q(\top_right_1_reg_n_0_[6] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\top_right_1_reg[7]
(.C(clk_x16),
.CE(top_right_1),
.D(\top_right_1[7]_i_1_n_0 ),
.Q(\top_right_1_reg_n_0_[7] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\top_right_1_reg[8]
(.C(clk_x16),
.CE(top_right_1),
.D(\top_right_1[8]_i_1_n_0 ),
.Q(\top_right_1_reg_n_0_[8] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\top_right_1_reg[9]
(.C(clk_x16),
.CE(top_right_1),
.D(\top_right_1[9]_i_1_n_0 ),
.Q(\top_right_1_reg_n_0_[9] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\value_reg[0]
(.C(clk_x16),
.CE(x),
.D(g_in[0]),
.Q(\value_reg_n_0_[0] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\value_reg[1]
(.C(clk_x16),
.CE(x),
.D(g_in[1]),
.Q(\value_reg_n_0_[1] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\value_reg[2]
(.C(clk_x16),
.CE(x),
.D(g_in[2]),
.Q(\value_reg_n_0_[2] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\value_reg[3]
(.C(clk_x16),
.CE(x),
.D(g_in[3]),
.Q(\value_reg_n_0_[3] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\value_reg[4]
(.C(clk_x16),
.CE(x),
.D(g_in[4]),
.Q(\value_reg_n_0_[4] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\value_reg[5]
(.C(clk_x16),
.CE(x),
.D(g_in[5]),
.Q(\value_reg_n_0_[5] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\value_reg[6]
(.C(clk_x16),
.CE(x),
.D(g_in[6]),
.Q(\value_reg_n_0_[6] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\value_reg[7]
(.C(clk_x16),
.CE(x),
.D(g_in[7]),
.Q(\value_reg_n_0_[7] ),
.R(1'b0));
LUT6 #(
.INIT(64'hAAAAEAAAAAA2AAAA))
wen_i_1
(.I0(wen_reg_n_0),
.I1(wen_i_2_n_0),
.I2(\cycle_reg[0]_rep_n_0 ),
.I3(\cycle_reg[1]_rep_n_0 ),
.I4(cycle[3]),
.I5(cycle[2]),
.O(wen_i_1_n_0));
LUT2 #(
.INIT(4'h8))
wen_i_2
(.I0(active),
.I1(rst),
.O(wen_i_2_n_0));
FDRE #(
.INIT(1'b0))
wen_reg
(.C(clk_x16),
.CE(1'b1),
.D(wen_i_1_n_0),
.Q(wen_reg_n_0),
.R(1'b0));
LUT6 #(
.INIT(64'h3B01FFC53A00FEC4))
\x0[0]_i_2
(.I0(\cycle_reg[2]_rep_n_0 ),
.I1(cycle[0]),
.I2(\cycle_reg[1]_rep__0_n_0 ),
.I3(data2[0]),
.I4(\x_reg_n_0_[0] ),
.I5(\plusOp_inferred__0/i__carry_n_7 ),
.O(\x0[0]_i_2_n_0 ));
LUT5 #(
.INIT(32'hFFFE0002))
\x0[0]_i_3
(.I0(data2[0]),
.I1(cycle[0]),
.I2(\cycle_reg[2]_rep_n_0 ),
.I3(\cycle_reg[1]_rep__0_n_0 ),
.I4(\plusOp_inferred__0/i__carry_n_7 ),
.O(\x0[0]_i_3_n_0 ));
LUT6 #(
.INIT(64'hCCEECCEEEEEECCFC))
\x0[1]_i_2
(.I0(data2[1]),
.I1(\x0[1]_i_4_n_0 ),
.I2(\plusOp_inferred__0/i__carry_n_6 ),
.I3(cycle[0]),
.I4(\cycle_reg[2]_rep_n_0 ),
.I5(\cycle_reg[1]_rep__0_n_0 ),
.O(\x0[1]_i_2_n_0 ));
LUT5 #(
.INIT(32'hFFFE0002))
\x0[1]_i_3
(.I0(data2[1]),
.I1(cycle[0]),
.I2(\cycle_reg[2]_rep_n_0 ),
.I3(\cycle_reg[1]_rep__0_n_0 ),
.I4(\plusOp_inferred__0/i__carry_n_6 ),
.O(\x0[1]_i_3_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT5 #(
.INIT(32'h60600060))
\x0[1]_i_4
(.I0(\x_reg_n_0_[1] ),
.I1(\x_reg_n_0_[0] ),
.I2(cycle[0]),
.I3(\cycle_reg[2]_rep_n_0 ),
.I4(\cycle_reg[1]_rep__0_n_0 ),
.O(\x0[1]_i_4_n_0 ));
LUT6 #(
.INIT(64'hFBBBFBBBFFBBBBBB))
\x0[2]_i_1
(.I0(\x0[2]_i_2_n_0 ),
.I1(\x0[2]_i_3_n_0 ),
.I2(data2[2]),
.I3(cycle[3]),
.I4(\plusOp_inferred__0/i__carry_n_5 ),
.I5(\x1[5]_i_3_n_0 ),
.O(\x0[2]_i_1_n_0 ));
LUT6 #(
.INIT(64'h88AA22A0880022A0))
\x0[2]_i_2
(.I0(\x0[7]_i_4_n_0 ),
.I1(\x0[2]_i_4_n_0 ),
.I2(\plusOp_inferred__0/i__carry_n_5 ),
.I3(cycle[0]),
.I4(\cycle_reg[1]_rep__0_n_0 ),
.I5(data2[2]),
.O(\x0[2]_i_2_n_0 ));
LUT6 #(
.INIT(64'h3FF3F3F377777777))
\x0[2]_i_3
(.I0(data2[2]),
.I1(\x0[2]_i_5_n_0 ),
.I2(\x_reg_n_0_[2] ),
.I3(\x_reg_n_0_[1] ),
.I4(\x_reg_n_0_[0] ),
.I5(\x1[6]_i_8_n_0 ),
.O(\x0[2]_i_3_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair55" *)
LUT3 #(
.INIT(8'h6A))
\x0[2]_i_4
(.I0(\x_reg_n_0_[2] ),
.I1(\x_reg_n_0_[1] ),
.I2(\x_reg_n_0_[0] ),
.O(\x0[2]_i_4_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT2 #(
.INIT(4'h2))
\x0[2]_i_5
(.I0(\cycle_reg[2]_rep_n_0 ),
.I1(cycle[3]),
.O(\x0[2]_i_5_n_0 ));
LUT5 #(
.INIT(32'hFFF100F1))
\x0[3]_i_1
(.I0(\x0[3]_i_2_n_0 ),
.I1(\cycle_reg[2]_rep_n_0 ),
.I2(\x0[3]_i_3_n_0 ),
.I3(cycle[3]),
.I4(\x0[3]_i_4_n_0 ),
.O(\x0[3]_i_1_n_0 ));
LUT6 #(
.INIT(64'h660FFF00660FFFFF))
\x0[3]_i_2
(.I0(\x_reg_n_0_[3] ),
.I1(\x0[3]_i_5_n_0 ),
.I2(data2[3]),
.I3(cycle[0]),
.I4(\cycle_reg[1]_rep__0_n_0 ),
.I5(\plusOp_inferred__0/i__carry_n_4 ),
.O(\x0[3]_i_2_n_0 ));
LUT6 #(
.INIT(64'h90F0F9F090000900))
\x0[3]_i_3
(.I0(\x_reg_n_0_[3] ),
.I1(\x0[3]_i_6_n_0 ),
.I2(\cycle_reg[2]_rep_n_0 ),
.I3(cycle[0]),
.I4(\cycle_reg[1]_rep__0_n_0 ),
.I5(data2[3]),
.O(\x0[3]_i_3_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair9" *)
LUT5 #(
.INIT(32'hFFFE0002))
\x0[3]_i_4
(.I0(data2[3]),
.I1(cycle[0]),
.I2(\cycle_reg[2]_rep_n_0 ),
.I3(\cycle_reg[1]_rep__0_n_0 ),
.I4(\plusOp_inferred__0/i__carry_n_4 ),
.O(\x0[3]_i_4_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair55" *)
LUT3 #(
.INIT(8'h7F))
\x0[3]_i_5
(.I0(\x_reg_n_0_[2] ),
.I1(\x_reg_n_0_[1] ),
.I2(\x_reg_n_0_[0] ),
.O(\x0[3]_i_5_n_0 ));
LUT3 #(
.INIT(8'hEA))
\x0[3]_i_6
(.I0(\x_reg_n_0_[2] ),
.I1(\x_reg_n_0_[1] ),
.I2(\x_reg_n_0_[0] ),
.O(\x0[3]_i_6_n_0 ));
LUT6 #(
.INIT(64'hFCDDFCDDFFDDCCDD))
\x0[4]_i_1
(.I0(\x0[4]_i_2_n_0 ),
.I1(\x0[4]_i_3_n_0 ),
.I2(data2[4]),
.I3(cycle[3]),
.I4(\plusOp_inferred__0/i__carry__0_n_7 ),
.I5(\x1[5]_i_3_n_0 ),
.O(\x0[4]_i_1_n_0 ));
LUT6 #(
.INIT(64'h3C555555FFFF3CFF))
\x0[4]_i_2
(.I0(data2[4]),
.I1(\x_reg_n_0_[4] ),
.I2(\x0[4]_i_4_n_0 ),
.I3(cycle[0]),
.I4(\cycle_reg[1]_rep__0_n_0 ),
.I5(\cycle_reg[2]_rep_n_0 ),
.O(\x0[4]_i_2_n_0 ));
LUT6 #(
.INIT(64'h008A0080A08AA080))
\x0[4]_i_3
(.I0(\x0[7]_i_4_n_0 ),
.I1(data2[4]),
.I2(\cycle_reg[1]_rep__0_n_0 ),
.I3(cycle[0]),
.I4(\plusOp_inferred__0/i__carry__0_n_7 ),
.I5(\x0[4]_i_5_n_0 ),
.O(\x0[4]_i_3_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair16" *)
LUT4 #(
.INIT(16'hFFEA))
\x0[4]_i_4
(.I0(\x_reg_n_0_[3] ),
.I1(\x_reg_n_0_[0] ),
.I2(\x_reg_n_0_[1] ),
.I3(\x_reg_n_0_[2] ),
.O(\x0[4]_i_4_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT5 #(
.INIT(32'h95555555))
\x0[4]_i_5
(.I0(\x_reg_n_0_[4] ),
.I1(\x_reg_n_0_[3] ),
.I2(\x_reg_n_0_[2] ),
.I3(\x_reg_n_0_[1] ),
.I4(\x_reg_n_0_[0] ),
.O(\x0[4]_i_5_n_0 ));
LUT6 #(
.INIT(64'hFCDDFCDDFFDDCCDD))
\x0[5]_i_1
(.I0(\x0[5]_i_2_n_0 ),
.I1(\x0[5]_i_3_n_0 ),
.I2(data2[5]),
.I3(cycle[3]),
.I4(\plusOp_inferred__0/i__carry__0_n_6 ),
.I5(\x1[5]_i_3_n_0 ),
.O(\x0[5]_i_1_n_0 ));
LUT6 #(
.INIT(64'h3C555555FFFF3CFF))
\x0[5]_i_2
(.I0(data2[5]),
.I1(\x_reg_n_0_[5] ),
.I2(\x0[8]_i_7_n_0 ),
.I3(cycle[0]),
.I4(\cycle_reg[1]_rep__0_n_0 ),
.I5(\cycle_reg[2]_rep_n_0 ),
.O(\x0[5]_i_2_n_0 ));
LUT6 #(
.INIT(64'h00A80008AAAAAAAA))
\x0[5]_i_3
(.I0(\x0[7]_i_4_n_0 ),
.I1(\plusOp_inferred__0/i__carry__0_n_6 ),
.I2(\cycle_reg[1]_rep__0_n_0 ),
.I3(cycle[0]),
.I4(data2[5]),
.I5(\x0[5]_i_4_n_0 ),
.O(\x0[5]_i_3_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair14" *)
LUT5 #(
.INIT(32'h2DFFFFFF))
\x0[5]_i_4
(.I0(\x_reg_n_0_[4] ),
.I1(\x0[5]_i_5_n_0 ),
.I2(\x_reg_n_0_[5] ),
.I3(\cycle_reg[1]_rep__0_n_0 ),
.I4(cycle[0]),
.O(\x0[5]_i_4_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair16" *)
LUT4 #(
.INIT(16'h7FFF))
\x0[5]_i_5
(.I0(\x_reg_n_0_[0] ),
.I1(\x_reg_n_0_[1] ),
.I2(\x_reg_n_0_[2] ),
.I3(\x_reg_n_0_[3] ),
.O(\x0[5]_i_5_n_0 ));
LUT5 #(
.INIT(32'hFFFF0507))
\x0[6]_i_1
(.I0(\x0[6]_i_2_n_0 ),
.I1(\cycle_reg[2]_rep_n_0 ),
.I2(cycle[3]),
.I3(\x0[6]_i_3_n_0 ),
.I4(\x0[6]_i_4_n_0 ),
.O(\x0[6]_i_1_n_0 ));
LUT6 #(
.INIT(64'h0707077077777777))
\x0[6]_i_2
(.I0(\x1[9]_i_7_n_0 ),
.I1(data2[6]),
.I2(\x_reg_n_0_[6] ),
.I3(\x0[8]_i_7_n_0 ),
.I4(\x_reg_n_0_[5] ),
.I5(\x0[8]_i_5_n_0 ),
.O(\x0[6]_i_2_n_0 ));
LUT6 #(
.INIT(64'h6600FF0F66FFFF0F))
\x0[6]_i_3
(.I0(\x_reg_n_0_[6] ),
.I1(\x0[6]_i_5_n_0 ),
.I2(\plusOp_inferred__0/i__carry__0_n_5 ),
.I3(cycle[0]),
.I4(\cycle_reg[1]_rep__0_n_0 ),
.I5(data2[6]),
.O(\x0[6]_i_3_n_0 ));
LUT6 #(
.INIT(64'hC0C0C0C0C0C0C088))
\x0[6]_i_4
(.I0(data2[6]),
.I1(cycle[3]),
.I2(\plusOp_inferred__0/i__carry__0_n_5 ),
.I3(cycle[0]),
.I4(\cycle_reg[2]_rep_n_0 ),
.I5(\cycle_reg[1]_rep__0_n_0 ),
.O(\x0[6]_i_4_n_0 ));
LUT6 #(
.INIT(64'h7FFFFFFFFFFFFFFF))
\x0[6]_i_5
(.I0(\x_reg_n_0_[4] ),
.I1(\x_reg_n_0_[0] ),
.I2(\x_reg_n_0_[1] ),
.I3(\x_reg_n_0_[2] ),
.I4(\x_reg_n_0_[3] ),
.I5(\x_reg_n_0_[5] ),
.O(\x0[6]_i_5_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFF020000))
\x0[7]_i_1
(.I0(cycle[0]),
.I1(\cycle_reg[1]_rep__0_n_0 ),
.I2(\x0[7]_i_2_n_0 ),
.I3(\x0[7]_i_3_n_0 ),
.I4(\x0[7]_i_4_n_0 ),
.I5(\x0[7]_i_5_n_0 ),
.O(\x0[7]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT4 #(
.INIT(16'h5556))
\x0[7]_i_2
(.I0(\x_reg_n_0_[7] ),
.I1(\x0[8]_i_7_n_0 ),
.I2(\x_reg_n_0_[5] ),
.I3(\x_reg_n_0_[6] ),
.O(\x0[7]_i_2_n_0 ));
LUT6 #(
.INIT(64'h99F000FF99F00000))
\x0[7]_i_3
(.I0(\x_reg_n_0_[7] ),
.I1(\x0[7]_i_6_n_0 ),
.I2(data2[7]),
.I3(cycle[0]),
.I4(\cycle_reg[1]_rep__0_n_0 ),
.I5(\plusOp_inferred__0/i__carry__0_n_4 ),
.O(\x0[7]_i_3_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair8" *)
LUT2 #(
.INIT(4'h1))
\x0[7]_i_4
(.I0(cycle[3]),
.I1(\cycle_reg[2]_rep_n_0 ),
.O(\x0[7]_i_4_n_0 ));
LUT6 #(
.INIT(64'hFF0FEECCF000EECC))
\x0[7]_i_5
(.I0(\x1[9]_i_7_n_0 ),
.I1(\x0[7]_i_7_n_0 ),
.I2(\x1[5]_i_3_n_0 ),
.I3(data2[7]),
.I4(cycle[3]),
.I5(\plusOp_inferred__0/i__carry__0_n_4 ),
.O(\x0[7]_i_5_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair17" *)
LUT2 #(
.INIT(4'hB))
\x0[7]_i_6
(.I0(\x0[6]_i_5_n_0 ),
.I1(\x_reg_n_0_[6] ),
.O(\x0[7]_i_6_n_0 ));
LUT6 #(
.INIT(64'h8888888000000008))
\x0[7]_i_7
(.I0(\cycle_reg[2]_rep_n_0 ),
.I1(\x1[6]_i_8_n_0 ),
.I2(\x_reg_n_0_[6] ),
.I3(\x_reg_n_0_[5] ),
.I4(\x0[8]_i_7_n_0 ),
.I5(\x_reg_n_0_[7] ),
.O(\x0[7]_i_7_n_0 ));
LUT6 #(
.INIT(64'hF0F0F0F0FFF1F1F1))
\x0[8]_i_1
(.I0(\x0[8]_i_2_n_0 ),
.I1(\cycle_reg[2]_rep_n_0 ),
.I2(\x0[8]_i_3_n_0 ),
.I3(\x0[8]_i_4_n_0 ),
.I4(\x0[8]_i_5_n_0 ),
.I5(cycle[3]),
.O(\x0[8]_i_1_n_0 ));
LUT6 #(
.INIT(64'h990FFF00990FFFFF))
\x0[8]_i_2
(.I0(\x_reg_n_0_[8] ),
.I1(\x0[8]_i_6_n_0 ),
.I2(data2[8]),
.I3(cycle[0]),
.I4(\cycle_reg[1]_rep__0_n_0 ),
.I5(\plusOp_inferred__0/i__carry__1_n_7 ),
.O(\x0[8]_i_2_n_0 ));
LUT6 #(
.INIT(64'h8888B888B888B8C0))
\x0[8]_i_3
(.I0(\plusOp_inferred__0/i__carry__1_n_7 ),
.I1(cycle[3]),
.I2(data2[8]),
.I3(\cycle_reg[2]_rep_n_0 ),
.I4(cycle[0]),
.I5(\cycle_reg[1]_rep__0_n_0 ),
.O(\x0[8]_i_3_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT5 #(
.INIT(32'hAAAAAAA9))
\x0[8]_i_4
(.I0(\x_reg_n_0_[8] ),
.I1(\x_reg_n_0_[6] ),
.I2(\x_reg_n_0_[5] ),
.I3(\x0[8]_i_7_n_0 ),
.I4(\x_reg_n_0_[7] ),
.O(\x0[8]_i_4_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair11" *)
LUT3 #(
.INIT(8'h82))
\x0[8]_i_5
(.I0(cycle[0]),
.I1(\cycle_reg[1]_rep__0_n_0 ),
.I2(\cycle_reg[2]_rep_n_0 ),
.O(\x0[8]_i_5_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT3 #(
.INIT(8'h08))
\x0[8]_i_6
(.I0(\x_reg_n_0_[7] ),
.I1(\x_reg_n_0_[6] ),
.I2(\x0[6]_i_5_n_0 ),
.O(\x0[8]_i_6_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT5 #(
.INIT(32'hFFFFFEEE))
\x0[8]_i_7
(.I0(\x_reg_n_0_[4] ),
.I1(\x_reg_n_0_[2] ),
.I2(\x_reg_n_0_[1] ),
.I3(\x_reg_n_0_[0] ),
.I4(\x_reg_n_0_[3] ),
.O(\x0[8]_i_7_n_0 ));
LUT6 #(
.INIT(64'h77FE000000000000))
\x0[9]_i_1
(.I0(\cycle_reg[2]_rep_n_0 ),
.I1(cycle[3]),
.I2(cycle[0]),
.I3(\cycle_reg[1]_rep__0_n_0 ),
.I4(active),
.I5(rst),
.O(\x0[9]_i_1_n_0 ));
LUT5 #(
.INIT(32'h01FF0101))
\x0[9]_i_2
(.I0(\x0[9]_i_3_n_0 ),
.I1(cycle[3]),
.I2(cycle[2]),
.I3(\x0[9]_i_4_n_0 ),
.I4(\x0[9]_i_5_n_0 ),
.O(\x0[9]_i_2_n_0 ));
LUT6 #(
.INIT(64'hAF03AFF3A003A0F3))
\x0[9]_i_3
(.I0(\x0[9]_i_6_n_0 ),
.I1(\plusOp_inferred__0/i__carry__1_n_6 ),
.I2(\cycle_reg[1]_rep_n_0 ),
.I3(\cycle_reg[0]_rep_n_0 ),
.I4(data2[9]),
.I5(\x0[9]_i_7_n_0 ),
.O(\x0[9]_i_3_n_0 ));
LUT6 #(
.INIT(64'h0C0C0C0C0C0C0C44))
\x0[9]_i_4
(.I0(data2[9]),
.I1(cycle[3]),
.I2(\plusOp_inferred__0/i__carry__1_n_6 ),
.I3(\cycle_reg[0]_rep_n_0 ),
.I4(cycle[2]),
.I5(\cycle_reg[1]_rep_n_0 ),
.O(\x0[9]_i_4_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFF5CCC0000))
\x0[9]_i_5
(.I0(\x0[9]_i_7_n_0 ),
.I1(data2[9]),
.I2(\cycle_reg[1]_rep_n_0 ),
.I3(\cycle_reg[0]_rep_n_0 ),
.I4(cycle[2]),
.I5(cycle[3]),
.O(\x0[9]_i_5_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT5 #(
.INIT(32'h55559555))
\x0[9]_i_6
(.I0(\x_reg_n_0_[9] ),
.I1(\x_reg_n_0_[8] ),
.I2(\x_reg_n_0_[7] ),
.I3(\x_reg_n_0_[6] ),
.I4(\x0[6]_i_5_n_0 ),
.O(\x0[9]_i_6_n_0 ));
LUT6 #(
.INIT(64'h5555555555555556))
\x0[9]_i_7
(.I0(\x_reg_n_0_[9] ),
.I1(\x_reg_n_0_[8] ),
.I2(\x_reg_n_0_[7] ),
.I3(\x0[8]_i_7_n_0 ),
.I4(\x_reg_n_0_[5] ),
.I5(\x_reg_n_0_[6] ),
.O(\x0[9]_i_7_n_0 ));
FDRE \x0_reg[0]
(.C(clk_x16),
.CE(\x0[9]_i_1_n_0 ),
.D(\x0_reg[0]_i_1_n_0 ),
.Q(data1[0]),
.R(1'b0));
MUXF7 \x0_reg[0]_i_1
(.I0(\x0[0]_i_2_n_0 ),
.I1(\x0[0]_i_3_n_0 ),
.O(\x0_reg[0]_i_1_n_0 ),
.S(cycle[3]));
FDRE \x0_reg[1]
(.C(clk_x16),
.CE(\x0[9]_i_1_n_0 ),
.D(\x0_reg[1]_i_1_n_0 ),
.Q(data1[1]),
.R(1'b0));
MUXF7 \x0_reg[1]_i_1
(.I0(\x0[1]_i_2_n_0 ),
.I1(\x0[1]_i_3_n_0 ),
.O(\x0_reg[1]_i_1_n_0 ),
.S(cycle[3]));
FDRE \x0_reg[2]
(.C(clk_x16),
.CE(\x0[9]_i_1_n_0 ),
.D(\x0[2]_i_1_n_0 ),
.Q(data1[2]),
.R(1'b0));
FDRE \x0_reg[3]
(.C(clk_x16),
.CE(\x0[9]_i_1_n_0 ),
.D(\x0[3]_i_1_n_0 ),
.Q(data1[3]),
.R(1'b0));
FDRE \x0_reg[4]
(.C(clk_x16),
.CE(\x0[9]_i_1_n_0 ),
.D(\x0[4]_i_1_n_0 ),
.Q(data1[4]),
.R(1'b0));
FDRE \x0_reg[5]
(.C(clk_x16),
.CE(\x0[9]_i_1_n_0 ),
.D(\x0[5]_i_1_n_0 ),
.Q(data1[5]),
.R(1'b0));
FDRE \x0_reg[6]
(.C(clk_x16),
.CE(\x0[9]_i_1_n_0 ),
.D(\x0[6]_i_1_n_0 ),
.Q(data1[6]),
.R(1'b0));
FDRE \x0_reg[7]
(.C(clk_x16),
.CE(\x0[9]_i_1_n_0 ),
.D(\x0[7]_i_1_n_0 ),
.Q(data1[7]),
.R(1'b0));
FDRE \x0_reg[8]
(.C(clk_x16),
.CE(\x0[9]_i_1_n_0 ),
.D(\x0[8]_i_1_n_0 ),
.Q(data1[8]),
.R(1'b0));
FDRE \x0_reg[9]
(.C(clk_x16),
.CE(\x0[9]_i_1_n_0 ),
.D(\x0[9]_i_2_n_0 ),
.Q(data1[9]),
.R(1'b0));
LUT6 #(
.INIT(64'hFF01FF4EFE00B100))
\x1[0]_i_1
(.I0(\cycle_reg[1]_rep__0_n_0 ),
.I1(\cycle_reg[2]_rep_n_0 ),
.I2(cycle[0]),
.I3(\x_reg_n_0_[0] ),
.I4(cycle[3]),
.I5(data1[0]),
.O(\x1[0]_i_1_n_0 ));
LUT6 #(
.INIT(64'hAFEFAAA955565010))
\x1[1]_i_1
(.I0(cycle[3]),
.I1(\cycle_reg[2]_rep_n_0 ),
.I2(cycle[0]),
.I3(\cycle_reg[1]_rep__0_n_0 ),
.I4(data1[1]),
.I5(\x_reg_n_0_[1] ),
.O(\x1[1]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFEFEFEAEAEAEFEAE))
\x1[2]_i_1
(.I0(\x1[2]_i_2_n_0 ),
.I1(\x1[2]_i_3_n_0 ),
.I2(cycle[3]),
.I3(\x_reg_n_0_[2] ),
.I4(\x1[5]_i_3_n_0 ),
.I5(data1[2]),
.O(\x1[2]_i_1_n_0 ));
LUT6 #(
.INIT(64'h8A2A288880202888))
\x1[2]_i_2
(.I0(\x0[7]_i_4_n_0 ),
.I1(\x_reg_n_0_[2] ),
.I2(cycle[0]),
.I3(\x_reg_n_0_[1] ),
.I4(\cycle_reg[1]_rep__0_n_0 ),
.I5(data1[2]),
.O(\x1[2]_i_2_n_0 ));
LUT6 #(
.INIT(64'h3CAAAAAA00000000))
\x1[2]_i_3
(.I0(data1[2]),
.I1(\x_reg_n_0_[1] ),
.I2(\x_reg_n_0_[2] ),
.I3(cycle[0]),
.I4(\cycle_reg[1]_rep__0_n_0 ),
.I5(\cycle_reg[2]_rep_n_0 ),
.O(\x1[2]_i_3_n_0 ));
LUT6 #(
.INIT(64'hFCDDFCDDFFDDCCDD))
\x1[3]_i_1
(.I0(\x1[3]_i_2_n_0 ),
.I1(\x1[3]_i_3_n_0 ),
.I2(data1[3]),
.I3(cycle[3]),
.I4(\x_reg_n_0_[3] ),
.I5(\x1[5]_i_3_n_0 ),
.O(\x1[3]_i_1_n_0 ));
LUT6 #(
.INIT(64'h0770707077777777))
\x1[3]_i_2
(.I0(\x1[9]_i_7_n_0 ),
.I1(data1[3]),
.I2(\x_reg_n_0_[3] ),
.I3(\x_reg_n_0_[2] ),
.I4(\x_reg_n_0_[1] ),
.I5(\x0[8]_i_5_n_0 ),
.O(\x1[3]_i_2_n_0 ));
LUT6 #(
.INIT(64'hA08A0080008AA080))
\x1[3]_i_3
(.I0(\x0[7]_i_4_n_0 ),
.I1(data1[3]),
.I2(\cycle_reg[1]_rep__0_n_0 ),
.I3(cycle[0]),
.I4(\x_reg_n_0_[3] ),
.I5(\x1[3]_i_4_n_0 ),
.O(\x1[3]_i_3_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair54" *)
LUT2 #(
.INIT(4'hE))
\x1[3]_i_4
(.I0(\x_reg_n_0_[1] ),
.I1(\x_reg_n_0_[2] ),
.O(\x1[3]_i_4_n_0 ));
LUT6 #(
.INIT(64'hFCDDFCDDFFDDCCDD))
\x1[4]_i_1
(.I0(\x1[4]_i_2_n_0 ),
.I1(\x1[4]_i_3_n_0 ),
.I2(data1[4]),
.I3(cycle[3]),
.I4(\x_reg_n_0_[4] ),
.I5(\x1[5]_i_3_n_0 ),
.O(\x1[4]_i_1_n_0 ));
LUT6 #(
.INIT(64'h3C555555FFFF3CFF))
\x1[4]_i_2
(.I0(data1[4]),
.I1(\x_reg_n_0_[4] ),
.I2(\x1[4]_i_4_n_0 ),
.I3(cycle[0]),
.I4(\cycle_reg[1]_rep__0_n_0 ),
.I5(\cycle_reg[2]_rep_n_0 ),
.O(\x1[4]_i_2_n_0 ));
LUT6 #(
.INIT(64'hA08A0080008AA080))
\x1[4]_i_3
(.I0(\x0[7]_i_4_n_0 ),
.I1(data1[4]),
.I2(\cycle_reg[1]_rep__0_n_0 ),
.I3(cycle[0]),
.I4(\x_reg_n_0_[4] ),
.I5(\x1[4]_i_5_n_0 ),
.O(\x1[4]_i_3_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair54" *)
LUT3 #(
.INIT(8'hEA))
\x1[4]_i_4
(.I0(\x_reg_n_0_[3] ),
.I1(\x_reg_n_0_[2] ),
.I2(\x_reg_n_0_[1] ),
.O(\x1[4]_i_4_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair21" *)
LUT3 #(
.INIT(8'hFE))
\x1[4]_i_5
(.I0(\x_reg_n_0_[3] ),
.I1(\x_reg_n_0_[2] ),
.I2(\x_reg_n_0_[1] ),
.O(\x1[4]_i_5_n_0 ));
LUT5 #(
.INIT(32'h8A80AAAA))
\x1[5]_i_1
(.I0(\x1[5]_i_2_n_0 ),
.I1(data1[5]),
.I2(\x1[5]_i_3_n_0 ),
.I3(\x_reg_n_0_[5] ),
.I4(cycle[3]),
.O(\x1[5]_i_1_n_0 ));
LUT6 #(
.INIT(64'hCDFDCDCDFDFDFDCD))
\x1[5]_i_2
(.I0(\x1[5]_i_4_n_0 ),
.I1(cycle[3]),
.I2(\cycle_reg[2]_rep_n_0 ),
.I3(\x1[6]_i_8_n_0 ),
.I4(data1[5]),
.I5(\x1[5]_i_5_n_0 ),
.O(\x1[5]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair10" *)
LUT3 #(
.INIT(8'h01))
\x1[5]_i_3
(.I0(\cycle_reg[1]_rep__0_n_0 ),
.I1(\cycle_reg[2]_rep_n_0 ),
.I2(cycle[0]),
.O(\x1[5]_i_3_n_0 ));
LUT6 #(
.INIT(64'h0530FA3FF5300A3F))
\x1[5]_i_4
(.I0(\x1[6]_i_7_n_0 ),
.I1(data1[5]),
.I2(\cycle_reg[1]_rep__0_n_0 ),
.I3(cycle[0]),
.I4(\x_reg_n_0_[5] ),
.I5(\left[15]_i_3_n_0 ),
.O(\x1[5]_i_4_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair13" *)
LUT5 #(
.INIT(32'h55555666))
\x1[5]_i_5
(.I0(\x_reg_n_0_[5] ),
.I1(\x_reg_n_0_[3] ),
.I2(\x_reg_n_0_[2] ),
.I3(\x_reg_n_0_[1] ),
.I4(\x_reg_n_0_[4] ),
.O(\x1[5]_i_5_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT5 #(
.INIT(32'hFFF100F1))
\x1[6]_i_1
(.I0(\x1[6]_i_2_n_0 ),
.I1(\cycle_reg[2]_rep_n_0 ),
.I2(\x1[6]_i_3_n_0 ),
.I3(cycle[3]),
.I4(\x1[6]_i_4_n_0 ),
.O(\x1[6]_i_1_n_0 ));
LUT6 #(
.INIT(64'hCFC05050CFC05F5F))
\x1[6]_i_2
(.I0(data1[6]),
.I1(\x1[6]_i_5_n_0 ),
.I2(\cycle_reg[1]_rep__0_n_0 ),
.I3(\x1[6]_i_6_n_0 ),
.I4(cycle[0]),
.I5(\x_reg_n_0_[6] ),
.O(\x1[6]_i_2_n_0 ));
LUT6 #(
.INIT(64'hA900FF00A9000000))
\x1[6]_i_3
(.I0(\x_reg_n_0_[6] ),
.I1(\x1[6]_i_7_n_0 ),
.I2(\x_reg_n_0_[5] ),
.I3(\cycle_reg[2]_rep_n_0 ),
.I4(\x1[6]_i_8_n_0 ),
.I5(data1[6]),
.O(\x1[6]_i_3_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair10" *)
LUT5 #(
.INIT(32'hFFFE0002))
\x1[6]_i_4
(.I0(data1[6]),
.I1(cycle[0]),
.I2(\cycle_reg[2]_rep_n_0 ),
.I3(\cycle_reg[1]_rep__0_n_0 ),
.I4(\x_reg_n_0_[6] ),
.O(\x1[6]_i_4_n_0 ));
LUT6 #(
.INIT(64'h5555555555555556))
\x1[6]_i_5
(.I0(\x_reg_n_0_[6] ),
.I1(\x_reg_n_0_[4] ),
.I2(\x_reg_n_0_[1] ),
.I3(\x_reg_n_0_[2] ),
.I4(\x_reg_n_0_[3] ),
.I5(\x_reg_n_0_[5] ),
.O(\x1[6]_i_5_n_0 ));
LUT6 #(
.INIT(64'h5555555555555666))
\x1[6]_i_6
(.I0(\x_reg_n_0_[6] ),
.I1(\x_reg_n_0_[4] ),
.I2(\x_reg_n_0_[1] ),
.I3(\x_reg_n_0_[2] ),
.I4(\x_reg_n_0_[3] ),
.I5(\x_reg_n_0_[5] ),
.O(\x1[6]_i_6_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair21" *)
LUT4 #(
.INIT(16'hFFEA))
\x1[6]_i_7
(.I0(\x_reg_n_0_[4] ),
.I1(\x_reg_n_0_[1] ),
.I2(\x_reg_n_0_[2] ),
.I3(\x_reg_n_0_[3] ),
.O(\x1[6]_i_7_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair14" *)
LUT2 #(
.INIT(4'h8))
\x1[6]_i_8
(.I0(\cycle_reg[1]_rep__0_n_0 ),
.I1(cycle[0]),
.O(\x1[6]_i_8_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair8" *)
LUT5 #(
.INIT(32'hFFF100F1))
\x1[7]_i_1
(.I0(\x1[7]_i_2_n_0 ),
.I1(\cycle_reg[2]_rep_n_0 ),
.I2(\x1[7]_i_3_n_0 ),
.I3(cycle[3]),
.I4(\x1[7]_i_4_n_0 ),
.O(\x1[7]_i_1_n_0 ));
LUT6 #(
.INIT(64'h303F5050CFC05F5F))
\x1[7]_i_2
(.I0(data1[7]),
.I1(\x1[7]_i_5_n_0 ),
.I2(\cycle_reg[1]_rep__0_n_0 ),
.I3(\x1[9]_i_6_n_0 ),
.I4(cycle[0]),
.I5(\x_reg_n_0_[7] ),
.O(\x1[7]_i_2_n_0 ));
LUT6 #(
.INIT(64'h90F0F0F090000000))
\x1[7]_i_3
(.I0(\x_reg_n_0_[7] ),
.I1(\x1[9]_i_6_n_0 ),
.I2(\cycle_reg[2]_rep_n_0 ),
.I3(cycle[0]),
.I4(\cycle_reg[1]_rep__0_n_0 ),
.I5(data1[7]),
.O(\x1[7]_i_3_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair11" *)
LUT5 #(
.INIT(32'hFFFE0002))
\x1[7]_i_4
(.I0(data1[7]),
.I1(cycle[0]),
.I2(\cycle_reg[2]_rep_n_0 ),
.I3(\cycle_reg[1]_rep__0_n_0 ),
.I4(\x_reg_n_0_[7] ),
.O(\x1[7]_i_4_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFFFFFFE))
\x1[7]_i_5
(.I0(\x_reg_n_0_[3] ),
.I1(\x_reg_n_0_[2] ),
.I2(\x_reg_n_0_[1] ),
.I3(\x_reg_n_0_[4] ),
.I4(\x_reg_n_0_[6] ),
.I5(\x_reg_n_0_[5] ),
.O(\x1[7]_i_5_n_0 ));
LUT4 #(
.INIT(16'hFF01))
\x1[8]_i_1
(.I0(\x1[8]_i_2_n_0 ),
.I1(cycle[3]),
.I2(\cycle_reg[2]_rep_n_0 ),
.I3(\x1[8]_i_3_n_0 ),
.O(\x1[8]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFA300A3F0A30FA3F))
\x1[8]_i_2
(.I0(\x1[8]_i_4_n_0 ),
.I1(data1[8]),
.I2(\cycle_reg[1]_rep__0_n_0 ),
.I3(cycle[0]),
.I4(\x_reg_n_0_[8] ),
.I5(\left[15]_i_2_n_0 ),
.O(\x1[8]_i_2_n_0 ));
LUT6 #(
.INIT(64'hFF0FEECCF000EECC))
\x1[8]_i_3
(.I0(\x1[9]_i_7_n_0 ),
.I1(\x1[8]_i_5_n_0 ),
.I2(\x1[5]_i_3_n_0 ),
.I3(data1[8]),
.I4(cycle[3]),
.I5(\x_reg_n_0_[8] ),
.O(\x1[8]_i_3_n_0 ));
LUT5 #(
.INIT(32'h55555556))
\x1[8]_i_4
(.I0(\x_reg_n_0_[8] ),
.I1(\x_reg_n_0_[6] ),
.I2(\x_reg_n_0_[5] ),
.I3(\x1[6]_i_7_n_0 ),
.I4(\x_reg_n_0_[7] ),
.O(\x1[8]_i_4_n_0 ));
LUT6 #(
.INIT(64'hAAAAAAA800000002))
\x1[8]_i_5
(.I0(\x1[8]_i_6_n_0 ),
.I1(\x_reg_n_0_[7] ),
.I2(\x1[6]_i_7_n_0 ),
.I3(\x_reg_n_0_[5] ),
.I4(\x_reg_n_0_[6] ),
.I5(\x_reg_n_0_[8] ),
.O(\x1[8]_i_5_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT3 #(
.INIT(8'h80))
\x1[8]_i_6
(.I0(cycle[0]),
.I1(\cycle_reg[1]_rep__0_n_0 ),
.I2(\cycle_reg[2]_rep_n_0 ),
.O(\x1[8]_i_6_n_0 ));
LUT6 #(
.INIT(64'h0088008880880880))
\x1[9]_i_1
(.I0(active),
.I1(rst),
.I2(cycle[0]),
.I3(cycle[3]),
.I4(\cycle_reg[2]_rep_n_0 ),
.I5(\cycle_reg[1]_rep__0_n_0 ),
.O(x1));
LUT6 #(
.INIT(64'hFFFFFFFF00000047))
\x1[9]_i_2
(.I0(\x1[9]_i_3_n_0 ),
.I1(\cycle_reg[1]_rep__0_n_0 ),
.I2(\x1[9]_i_4_n_0 ),
.I3(cycle[3]),
.I4(\cycle_reg[2]_rep_n_0 ),
.I5(\x1[9]_i_5_n_0 ),
.O(\x1[9]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT5 #(
.INIT(32'h3C335555))
\x1[9]_i_3
(.I0(data1[9]),
.I1(\x_reg_n_0_[9] ),
.I2(\x_reg_n_0_[8] ),
.I3(\left[15]_i_2_n_0 ),
.I4(cycle[0]),
.O(\x1[9]_i_3_n_0 ));
LUT5 #(
.INIT(32'h0100FEFF))
\x1[9]_i_4
(.I0(\x_reg_n_0_[8] ),
.I1(\x_reg_n_0_[7] ),
.I2(\x1[9]_i_6_n_0 ),
.I3(cycle[0]),
.I4(\x_reg_n_0_[9] ),
.O(\x1[9]_i_4_n_0 ));
LUT6 #(
.INIT(64'hFF0FEECCF000EECC))
\x1[9]_i_5
(.I0(\x1[9]_i_7_n_0 ),
.I1(\x1[9]_i_8_n_0 ),
.I2(\x1[5]_i_3_n_0 ),
.I3(data1[9]),
.I4(cycle[3]),
.I5(\x_reg_n_0_[9] ),
.O(\x1[9]_i_5_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFFEFEFE))
\x1[9]_i_6
(.I0(\x_reg_n_0_[6] ),
.I1(\x_reg_n_0_[5] ),
.I2(\x_reg_n_0_[3] ),
.I3(\x_reg_n_0_[2] ),
.I4(\x_reg_n_0_[1] ),
.I5(\x_reg_n_0_[4] ),
.O(\x1[9]_i_6_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair9" *)
LUT3 #(
.INIT(8'h2A))
\x1[9]_i_7
(.I0(\cycle_reg[2]_rep_n_0 ),
.I1(cycle[0]),
.I2(\cycle_reg[1]_rep__0_n_0 ),
.O(\x1[9]_i_7_n_0 ));
LUT6 #(
.INIT(64'h8888888000000008))
\x1[9]_i_8
(.I0(\cycle_reg[2]_rep_n_0 ),
.I1(\x1[6]_i_8_n_0 ),
.I2(\x1[9]_i_6_n_0 ),
.I3(\x_reg_n_0_[7] ),
.I4(\x_reg_n_0_[8] ),
.I5(\x_reg_n_0_[9] ),
.O(\x1[9]_i_8_n_0 ));
FDRE \x1_reg[0]
(.C(clk_x16),
.CE(x1),
.D(\x1[0]_i_1_n_0 ),
.Q(data2[0]),
.R(1'b0));
FDRE \x1_reg[1]
(.C(clk_x16),
.CE(x1),
.D(\x1[1]_i_1_n_0 ),
.Q(data2[1]),
.R(1'b0));
FDRE \x1_reg[2]
(.C(clk_x16),
.CE(x1),
.D(\x1[2]_i_1_n_0 ),
.Q(data2[2]),
.R(1'b0));
FDRE \x1_reg[3]
(.C(clk_x16),
.CE(x1),
.D(\x1[3]_i_1_n_0 ),
.Q(data2[3]),
.R(1'b0));
FDRE \x1_reg[4]
(.C(clk_x16),
.CE(x1),
.D(\x1[4]_i_1_n_0 ),
.Q(data2[4]),
.R(1'b0));
FDRE \x1_reg[5]
(.C(clk_x16),
.CE(x1),
.D(\x1[5]_i_1_n_0 ),
.Q(data2[5]),
.R(1'b0));
FDRE \x1_reg[6]
(.C(clk_x16),
.CE(x1),
.D(\x1[6]_i_1_n_0 ),
.Q(data2[6]),
.R(1'b0));
FDRE \x1_reg[7]
(.C(clk_x16),
.CE(x1),
.D(\x1[7]_i_1_n_0 ),
.Q(data2[7]),
.R(1'b0));
FDRE \x1_reg[8]
(.C(clk_x16),
.CE(x1),
.D(\x1[8]_i_1_n_0 ),
.Q(data2[8]),
.R(1'b0));
FDRE \x1_reg[9]
(.C(clk_x16),
.CE(x1),
.D(\x1[9]_i_2_n_0 ),
.Q(data2[9]),
.R(1'b0));
LUT6 #(
.INIT(64'h0000000000000040))
\x[9]_i_1
(.I0(cycle[0]),
.I1(active),
.I2(rst),
.I3(\cycle_reg[1]_rep_n_0 ),
.I4(cycle[3]),
.I5(cycle[2]),
.O(x));
FDRE \x_reg[0]
(.C(clk_x16),
.CE(x),
.D(x_addr[0]),
.Q(\x_reg_n_0_[0] ),
.R(1'b0));
FDRE \x_reg[1]
(.C(clk_x16),
.CE(x),
.D(x_addr[1]),
.Q(\x_reg_n_0_[1] ),
.R(1'b0));
FDRE \x_reg[2]
(.C(clk_x16),
.CE(x),
.D(x_addr[2]),
.Q(\x_reg_n_0_[2] ),
.R(1'b0));
FDRE \x_reg[3]
(.C(clk_x16),
.CE(x),
.D(x_addr[3]),
.Q(\x_reg_n_0_[3] ),
.R(1'b0));
FDRE \x_reg[4]
(.C(clk_x16),
.CE(x),
.D(x_addr[4]),
.Q(\x_reg_n_0_[4] ),
.R(1'b0));
FDRE \x_reg[5]
(.C(clk_x16),
.CE(x),
.D(x_addr[5]),
.Q(\x_reg_n_0_[5] ),
.R(1'b0));
FDRE \x_reg[6]
(.C(clk_x16),
.CE(x),
.D(x_addr[6]),
.Q(\x_reg_n_0_[6] ),
.R(1'b0));
FDRE \x_reg[7]
(.C(clk_x16),
.CE(x),
.D(x_addr[7]),
.Q(\x_reg_n_0_[7] ),
.R(1'b0));
FDRE \x_reg[8]
(.C(clk_x16),
.CE(x),
.D(x_addr[8]),
.Q(\x_reg_n_0_[8] ),
.R(1'b0));
FDRE \x_reg[9]
(.C(clk_x16),
.CE(x),
.D(x_addr[9]),
.Q(\x_reg_n_0_[9] ),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair20" *)
LUT3 #(
.INIT(8'hE1))
\y1[2]_i_1
(.I0(\y_actual_reg_n_0_[0] ),
.I1(\y_actual_reg_n_0_[1] ),
.I2(\y_actual_reg_n_0_[2] ),
.O(\y1[2]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair23" *)
LUT4 #(
.INIT(16'hFE01))
\y1[3]_i_1
(.I0(\y_actual_reg_n_0_[2] ),
.I1(\y_actual_reg_n_0_[1] ),
.I2(\y_actual_reg_n_0_[0] ),
.I3(\y_actual_reg_n_0_[3] ),
.O(\y1[3]_i_1_n_0 ));
FDRE \y1_reg[0]
(.C(clk_x16),
.CE(y1),
.D(\y5[0]_i_1_n_0 ),
.Q(\y1_reg_n_0_[0] ),
.R(1'b0));
FDRE \y1_reg[1]
(.C(clk_x16),
.CE(y1),
.D(\y5[1]_i_1_n_0 ),
.Q(\y1_reg_n_0_[1] ),
.R(1'b0));
FDRE \y1_reg[2]
(.C(clk_x16),
.CE(y1),
.D(\y1[2]_i_1_n_0 ),
.Q(\y1_reg_n_0_[2] ),
.R(1'b0));
FDRE \y1_reg[3]
(.C(clk_x16),
.CE(y1),
.D(\y1[3]_i_1_n_0 ),
.Q(\y1_reg_n_0_[3] ),
.R(1'b0));
LUT1 #(
.INIT(2'h1))
\y2[1]_i_1
(.I0(\y_actual_reg_n_0_[1] ),
.O(\y2[1]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair28" *)
LUT2 #(
.INIT(4'h9))
\y2[2]_i_1
(.I0(\y_actual_reg_n_0_[2] ),
.I1(\y_actual_reg_n_0_[1] ),
.O(\y2[2]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair19" *)
LUT3 #(
.INIT(8'hA9))
\y2[3]_i_1
(.I0(\y_actual_reg_n_0_[3] ),
.I1(\y_actual_reg_n_0_[2] ),
.I2(\y_actual_reg_n_0_[1] ),
.O(\y2[3]_i_1_n_0 ));
FDRE \y2_reg[0]
(.C(clk_x16),
.CE(y2),
.D(\y_actual_reg_n_0_[0] ),
.Q(\y2_reg_n_0_[0] ),
.R(1'b0));
FDRE \y2_reg[1]
(.C(clk_x16),
.CE(y2),
.D(\y2[1]_i_1_n_0 ),
.Q(\y2_reg_n_0_[1] ),
.R(1'b0));
FDRE \y2_reg[2]
(.C(clk_x16),
.CE(y2),
.D(\y2[2]_i_1_n_0 ),
.Q(\y2_reg_n_0_[2] ),
.R(1'b0));
FDRE \y2_reg[3]
(.C(clk_x16),
.CE(y2),
.D(\y2[3]_i_1_n_0 ),
.Q(\y2_reg_n_0_[3] ),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair87" *)
LUT2 #(
.INIT(4'h6))
\y3[1]_i_1
(.I0(\y_actual_reg_n_0_[0] ),
.I1(\y_actual_reg_n_0_[1] ),
.O(\y3[1]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair22" *)
LUT3 #(
.INIT(8'h87))
\y3[2]_i_1
(.I0(\y_actual_reg_n_0_[0] ),
.I1(\y_actual_reg_n_0_[1] ),
.I2(\y_actual_reg_n_0_[2] ),
.O(\y3[2]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair22" *)
LUT4 #(
.INIT(16'hAA95))
\y3[3]_i_1
(.I0(\y_actual_reg_n_0_[3] ),
.I1(\y_actual_reg_n_0_[0] ),
.I2(\y_actual_reg_n_0_[1] ),
.I3(\y_actual_reg_n_0_[2] ),
.O(\y3[3]_i_1_n_0 ));
FDRE \y3_reg[0]
(.C(clk_x16),
.CE(y3),
.D(\y5[0]_i_1_n_0 ),
.Q(\y3_reg_n_0_[0] ),
.R(1'b0));
FDRE \y3_reg[1]
(.C(clk_x16),
.CE(y3),
.D(\y3[1]_i_1_n_0 ),
.Q(\y3_reg_n_0_[1] ),
.R(1'b0));
FDRE \y3_reg[2]
(.C(clk_x16),
.CE(y3),
.D(\y3[2]_i_1_n_0 ),
.Q(\y3_reg_n_0_[2] ),
.R(1'b0));
FDRE \y3_reg[3]
(.C(clk_x16),
.CE(y3),
.D(\y3[3]_i_1_n_0 ),
.Q(\y3_reg_n_0_[3] ),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair86" *)
LUT1 #(
.INIT(2'h1))
\y4[2]_i_1
(.I0(\y_actual_reg_n_0_[2] ),
.O(\y4[2]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair86" *)
LUT2 #(
.INIT(4'h9))
\y4[3]_i_1
(.I0(\y_actual_reg_n_0_[3] ),
.I1(\y_actual_reg_n_0_[2] ),
.O(\y4[3]_i_1_n_0 ));
FDRE \y4_reg[0]
(.C(clk_x16),
.CE(y1),
.D(\y_actual_reg_n_0_[0] ),
.Q(data2[10]),
.R(1'b0));
FDRE \y4_reg[1]
(.C(clk_x16),
.CE(y1),
.D(\y_actual_reg_n_0_[1] ),
.Q(data2[11]),
.R(1'b0));
FDRE \y4_reg[2]
(.C(clk_x16),
.CE(y1),
.D(\y4[2]_i_1_n_0 ),
.Q(data2[12]),
.R(1'b0));
FDRE \y4_reg[3]
(.C(clk_x16),
.CE(y1),
.D(\y4[3]_i_1_n_0 ),
.Q(data2[13]),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair87" *)
LUT1 #(
.INIT(2'h1))
\y5[0]_i_1
(.I0(\y_actual_reg_n_0_[0] ),
.O(\y5[0]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair23" *)
LUT2 #(
.INIT(4'h9))
\y5[1]_i_1
(.I0(\y_actual_reg_n_0_[1] ),
.I1(\y_actual_reg_n_0_[0] ),
.O(\y5[1]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair18" *)
LUT3 #(
.INIT(8'h56))
\y5[2]_i_1
(.I0(\y_actual_reg_n_0_[2] ),
.I1(\y_actual_reg_n_0_[1] ),
.I2(\y_actual_reg_n_0_[0] ),
.O(\y5[2]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair18" *)
LUT4 #(
.INIT(16'hA955))
\y5[3]_i_1
(.I0(\y_actual_reg_n_0_[3] ),
.I1(\y_actual_reg_n_0_[0] ),
.I2(\y_actual_reg_n_0_[1] ),
.I3(\y_actual_reg_n_0_[2] ),
.O(\y5[3]_i_1_n_0 ));
FDRE \y5_reg[0]
(.C(clk_x16),
.CE(y5),
.D(\y5[0]_i_1_n_0 ),
.Q(data1[10]),
.R(1'b0));
FDRE \y5_reg[1]
(.C(clk_x16),
.CE(y5),
.D(\y5[1]_i_1_n_0 ),
.Q(data1[11]),
.R(1'b0));
FDRE \y5_reg[2]
(.C(clk_x16),
.CE(y5),
.D(\y5[2]_i_1_n_0 ),
.Q(data1[12]),
.R(1'b0));
FDRE \y5_reg[3]
(.C(clk_x16),
.CE(y5),
.D(\y5[3]_i_1_n_0 ),
.Q(data1[13]),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair34" *)
LUT2 #(
.INIT(4'h6))
\y6[2]_i_1
(.I0(\y_actual_reg_n_0_[1] ),
.I1(\y_actual_reg_n_0_[2] ),
.O(\y6[2]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair34" *)
LUT3 #(
.INIT(8'h95))
\y6[3]_i_1
(.I0(\y_actual_reg_n_0_[3] ),
.I1(\y_actual_reg_n_0_[2] ),
.I2(\y_actual_reg_n_0_[1] ),
.O(\y6[3]_i_1_n_0 ));
FDRE \y6_reg[0]
(.C(clk_x16),
.CE(y6),
.D(\y_actual_reg_n_0_[0] ),
.Q(\y6_reg_n_0_[0] ),
.R(1'b0));
FDRE \y6_reg[1]
(.C(clk_x16),
.CE(y6),
.D(\y2[1]_i_1_n_0 ),
.Q(\y6_reg_n_0_[1] ),
.R(1'b0));
FDRE \y6_reg[2]
(.C(clk_x16),
.CE(y6),
.D(\y6[2]_i_1_n_0 ),
.Q(\y6_reg_n_0_[2] ),
.R(1'b0));
FDRE \y6_reg[3]
(.C(clk_x16),
.CE(y6),
.D(\y6[3]_i_1_n_0 ),
.Q(\y6_reg_n_0_[3] ),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair28" *)
LUT3 #(
.INIT(8'h6A))
\y7[2]_i_1
(.I0(\y_actual_reg_n_0_[2] ),
.I1(\y_actual_reg_n_0_[1] ),
.I2(\y_actual_reg_n_0_[0] ),
.O(\y7[2]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair19" *)
LUT4 #(
.INIT(16'h9555))
\y7[3]_i_1
(.I0(\y_actual_reg_n_0_[3] ),
.I1(\y_actual_reg_n_0_[0] ),
.I2(\y_actual_reg_n_0_[1] ),
.I3(\y_actual_reg_n_0_[2] ),
.O(\y7[3]_i_1_n_0 ));
FDRE \y7_reg[0]
(.C(clk_x16),
.CE(y2),
.D(\y5[0]_i_1_n_0 ),
.Q(y7[0]),
.R(1'b0));
FDRE \y7_reg[1]
(.C(clk_x16),
.CE(y2),
.D(\y3[1]_i_1_n_0 ),
.Q(y7[1]),
.R(1'b0));
FDRE \y7_reg[2]
(.C(clk_x16),
.CE(y2),
.D(\y7[2]_i_1_n_0 ),
.Q(y7[2]),
.R(1'b0));
FDRE \y7_reg[3]
(.C(clk_x16),
.CE(y2),
.D(\y7[3]_i_1_n_0 ),
.Q(y7[3]),
.R(1'b0));
LUT1 #(
.INIT(2'h1))
\y8[3]_i_1
(.I0(\y_actual_reg_n_0_[3] ),
.O(\y8[3]_i_1_n_0 ));
FDRE \y8_reg[0]
(.C(clk_x16),
.CE(y5),
.D(\y_actual_reg_n_0_[0] ),
.Q(y8[0]),
.R(1'b0));
FDRE \y8_reg[1]
(.C(clk_x16),
.CE(y5),
.D(\y_actual_reg_n_0_[1] ),
.Q(y8[1]),
.R(1'b0));
FDRE \y8_reg[2]
(.C(clk_x16),
.CE(y5),
.D(\y_actual_reg_n_0_[2] ),
.Q(y8[2]),
.R(1'b0));
FDRE \y8_reg[3]
(.C(clk_x16),
.CE(y5),
.D(\y8[3]_i_1_n_0 ),
.Q(y8[3]),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair20" *)
LUT4 #(
.INIT(16'h5556))
\y9[3]_i_1
(.I0(\y_actual_reg_n_0_[3] ),
.I1(\y_actual_reg_n_0_[0] ),
.I2(\y_actual_reg_n_0_[1] ),
.I3(\y_actual_reg_n_0_[2] ),
.O(\y9[3]_i_1_n_0 ));
FDRE \y9_reg[0]
(.C(clk_x16),
.CE(y9),
.D(\y5[0]_i_1_n_0 ),
.Q(data5[10]),
.R(1'b0));
FDRE \y9_reg[1]
(.C(clk_x16),
.CE(y9),
.D(\y5[1]_i_1_n_0 ),
.Q(data5[11]),
.R(1'b0));
FDRE \y9_reg[2]
(.C(clk_x16),
.CE(y9),
.D(\y1[2]_i_1_n_0 ),
.Q(data5[12]),
.R(1'b0));
FDRE \y9_reg[3]
(.C(clk_x16),
.CE(y9),
.D(\y9[3]_i_1_n_0 ),
.Q(data5[13]),
.R(1'b0));
FDRE \y_actual_reg[0]
(.C(clk_x16),
.CE(x),
.D(y_addr[0]),
.Q(\y_actual_reg_n_0_[0] ),
.R(1'b0));
FDRE \y_actual_reg[1]
(.C(clk_x16),
.CE(x),
.D(y_addr[1]),
.Q(\y_actual_reg_n_0_[1] ),
.R(1'b0));
FDRE \y_actual_reg[2]
(.C(clk_x16),
.CE(x),
.D(y_addr[2]),
.Q(\y_actual_reg_n_0_[2] ),
.R(1'b0));
FDRE \y_actual_reg[3]
(.C(clk_x16),
.CE(x),
.D(y_addr[3]),
.Q(\y_actual_reg_n_0_[3] ),
.R(1'b0));
FDRE \y_actual_reg[4]
(.C(clk_x16),
.CE(x),
.D(y_addr[4]),
.Q(\y_actual_reg_n_0_[4] ),
.R(1'b0));
FDRE \y_actual_reg[5]
(.C(clk_x16),
.CE(x),
.D(y_addr[5]),
.Q(\y_actual_reg_n_0_[5] ),
.R(1'b0));
FDRE \y_actual_reg[6]
(.C(clk_x16),
.CE(x),
.D(y_addr[6]),
.Q(\y_actual_reg_n_0_[6] ),
.R(1'b0));
FDRE \y_actual_reg[7]
(.C(clk_x16),
.CE(x),
.D(y_addr[7]),
.Q(\y_actual_reg_n_0_[7] ),
.R(1'b0));
FDRE \y_actual_reg[8]
(.C(clk_x16),
.CE(x),
.D(y_addr[8]),
.Q(\y_actual_reg_n_0_[8] ),
.R(1'b0));
FDRE \y_actual_reg[9]
(.C(clk_x16),
.CE(x),
.D(y_addr[9]),
.Q(\y_actual_reg_n_0_[9] ),
.R(1'b0));
endmodule |
module system_vga_hessian_1_0_bindec
(ena_array,
ena,
addra);
output [2:0]ena_array;
input ena;
input [1:0]addra;
wire [1:0]addra;
wire ena;
wire [2:0]ena_array;
LUT3 #(
.INIT(8'h02))
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_i_1
(.I0(ena),
.I1(addra[0]),
.I2(addra[1]),
.O(ena_array[0]));
LUT3 #(
.INIT(8'h40))
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_i_1__0
(.I0(addra[1]),
.I1(addra[0]),
.I2(ena),
.O(ena_array[1]));
LUT3 #(
.INIT(8'h40))
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_i_1__1
(.I0(addra[0]),
.I1(ena),
.I2(addra[1]),
.O(ena_array[2]));
endmodule |
module system_vga_hessian_1_0_bindec_0
(enb_array,
enb,
addrb);
output [2:0]enb_array;
input enb;
input [1:0]addrb;
wire [1:0]addrb;
wire enb;
wire [2:0]enb_array;
LUT3 #(
.INIT(8'h02))
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_i_2
(.I0(enb),
.I1(addrb[0]),
.I2(addrb[1]),
.O(enb_array[0]));
LUT3 #(
.INIT(8'h40))
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_i_2__0
(.I0(addrb[1]),
.I1(addrb[0]),
.I2(enb),
.O(enb_array[1]));
LUT3 #(
.INIT(8'h40))
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_i_2__1
(.I0(addrb[0]),
.I1(enb),
.I2(addrb[1]),
.O(enb_array[2]));
endmodule |
module system_vga_hessian_1_0_blk_mem_gen_generic_cstr
(douta,
doutb,
addra,
ena,
addrb,
enb,
clka,
clkb,
dina,
dinb,
wea,
web);
output [15:0]douta;
output [15:0]doutb;
input [13:0]addra;
input ena;
input [13:0]addrb;
input enb;
input clka;
input clkb;
input [15:0]dina;
input [15:0]dinb;
input [0:0]wea;
input [0:0]web;
wire [13:0]addra;
wire [13:0]addrb;
wire clka;
wire clkb;
wire [15:0]dina;
wire [15:0]dinb;
wire [15:0]douta;
wire [15:0]doutb;
wire ena;
wire [2:0]ena_array;
wire enb;
wire [2:0]enb_array;
wire \ramloop[4].ram.r_n_0 ;
wire \ramloop[4].ram.r_n_1 ;
wire \ramloop[4].ram.r_n_10 ;
wire \ramloop[4].ram.r_n_11 ;
wire \ramloop[4].ram.r_n_12 ;
wire \ramloop[4].ram.r_n_13 ;
wire \ramloop[4].ram.r_n_14 ;
wire \ramloop[4].ram.r_n_15 ;
wire \ramloop[4].ram.r_n_16 ;
wire \ramloop[4].ram.r_n_17 ;
wire \ramloop[4].ram.r_n_2 ;
wire \ramloop[4].ram.r_n_3 ;
wire \ramloop[4].ram.r_n_4 ;
wire \ramloop[4].ram.r_n_5 ;
wire \ramloop[4].ram.r_n_6 ;
wire \ramloop[4].ram.r_n_7 ;
wire \ramloop[4].ram.r_n_8 ;
wire \ramloop[4].ram.r_n_9 ;
wire \ramloop[5].ram.r_n_0 ;
wire \ramloop[5].ram.r_n_1 ;
wire \ramloop[5].ram.r_n_10 ;
wire \ramloop[5].ram.r_n_11 ;
wire \ramloop[5].ram.r_n_12 ;
wire \ramloop[5].ram.r_n_13 ;
wire \ramloop[5].ram.r_n_14 ;
wire \ramloop[5].ram.r_n_15 ;
wire \ramloop[5].ram.r_n_16 ;
wire \ramloop[5].ram.r_n_17 ;
wire \ramloop[5].ram.r_n_2 ;
wire \ramloop[5].ram.r_n_3 ;
wire \ramloop[5].ram.r_n_4 ;
wire \ramloop[5].ram.r_n_5 ;
wire \ramloop[5].ram.r_n_6 ;
wire \ramloop[5].ram.r_n_7 ;
wire \ramloop[5].ram.r_n_8 ;
wire \ramloop[5].ram.r_n_9 ;
wire \ramloop[6].ram.r_n_0 ;
wire \ramloop[6].ram.r_n_1 ;
wire \ramloop[6].ram.r_n_10 ;
wire \ramloop[6].ram.r_n_11 ;
wire \ramloop[6].ram.r_n_12 ;
wire \ramloop[6].ram.r_n_13 ;
wire \ramloop[6].ram.r_n_14 ;
wire \ramloop[6].ram.r_n_15 ;
wire \ramloop[6].ram.r_n_16 ;
wire \ramloop[6].ram.r_n_17 ;
wire \ramloop[6].ram.r_n_2 ;
wire \ramloop[6].ram.r_n_3 ;
wire \ramloop[6].ram.r_n_4 ;
wire \ramloop[6].ram.r_n_5 ;
wire \ramloop[6].ram.r_n_6 ;
wire \ramloop[6].ram.r_n_7 ;
wire \ramloop[6].ram.r_n_8 ;
wire \ramloop[6].ram.r_n_9 ;
wire \ramloop[7].ram.r_n_0 ;
wire \ramloop[7].ram.r_n_1 ;
wire \ramloop[7].ram.r_n_10 ;
wire \ramloop[7].ram.r_n_11 ;
wire \ramloop[7].ram.r_n_12 ;
wire \ramloop[7].ram.r_n_13 ;
wire \ramloop[7].ram.r_n_14 ;
wire \ramloop[7].ram.r_n_15 ;
wire \ramloop[7].ram.r_n_16 ;
wire \ramloop[7].ram.r_n_17 ;
wire \ramloop[7].ram.r_n_2 ;
wire \ramloop[7].ram.r_n_3 ;
wire \ramloop[7].ram.r_n_4 ;
wire \ramloop[7].ram.r_n_5 ;
wire \ramloop[7].ram.r_n_6 ;
wire \ramloop[7].ram.r_n_7 ;
wire \ramloop[7].ram.r_n_8 ;
wire \ramloop[7].ram.r_n_9 ;
wire [0:0]wea;
wire [0:0]web;
system_vga_hessian_1_0_bindec \bindec_a.bindec_inst_a
(.addra(addra[13:12]),
.ena(ena),
.ena_array(ena_array));
system_vga_hessian_1_0_bindec_0 \bindec_b.bindec_inst_b
(.addrb(addrb[13:12]),
.enb(enb),
.enb_array(enb_array));
system_vga_hessian_1_0_blk_mem_gen_mux \has_mux_a.A
(.\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram ({\ramloop[5].ram.r_n_0 ,\ramloop[5].ram.r_n_1 ,\ramloop[5].ram.r_n_2 ,\ramloop[5].ram.r_n_3 ,\ramloop[5].ram.r_n_4 ,\ramloop[5].ram.r_n_5 ,\ramloop[5].ram.r_n_6 ,\ramloop[5].ram.r_n_7 }),
.\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0 ({\ramloop[6].ram.r_n_0 ,\ramloop[6].ram.r_n_1 ,\ramloop[6].ram.r_n_2 ,\ramloop[6].ram.r_n_3 ,\ramloop[6].ram.r_n_4 ,\ramloop[6].ram.r_n_5 ,\ramloop[6].ram.r_n_6 ,\ramloop[6].ram.r_n_7 }),
.\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1 ({\ramloop[4].ram.r_n_0 ,\ramloop[4].ram.r_n_1 ,\ramloop[4].ram.r_n_2 ,\ramloop[4].ram.r_n_3 ,\ramloop[4].ram.r_n_4 ,\ramloop[4].ram.r_n_5 ,\ramloop[4].ram.r_n_6 ,\ramloop[4].ram.r_n_7 }),
.\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_2 (\ramloop[5].ram.r_n_16 ),
.\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_3 (\ramloop[6].ram.r_n_16 ),
.\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_4 (\ramloop[4].ram.r_n_16 ),
.DOADO({\ramloop[7].ram.r_n_0 ,\ramloop[7].ram.r_n_1 ,\ramloop[7].ram.r_n_2 ,\ramloop[7].ram.r_n_3 ,\ramloop[7].ram.r_n_4 ,\ramloop[7].ram.r_n_5 ,\ramloop[7].ram.r_n_6 ,\ramloop[7].ram.r_n_7 }),
.DOPADOP(\ramloop[7].ram.r_n_16 ),
.addra(addra[13:12]),
.clka(clka),
.douta(douta[15:7]),
.ena(ena));
system_vga_hessian_1_0_blk_mem_gen_mux__parameterized0 \has_mux_b.B
(.\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram ({\ramloop[5].ram.r_n_8 ,\ramloop[5].ram.r_n_9 ,\ramloop[5].ram.r_n_10 ,\ramloop[5].ram.r_n_11 ,\ramloop[5].ram.r_n_12 ,\ramloop[5].ram.r_n_13 ,\ramloop[5].ram.r_n_14 ,\ramloop[5].ram.r_n_15 }),
.\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0 ({\ramloop[6].ram.r_n_8 ,\ramloop[6].ram.r_n_9 ,\ramloop[6].ram.r_n_10 ,\ramloop[6].ram.r_n_11 ,\ramloop[6].ram.r_n_12 ,\ramloop[6].ram.r_n_13 ,\ramloop[6].ram.r_n_14 ,\ramloop[6].ram.r_n_15 }),
.\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1 ({\ramloop[4].ram.r_n_8 ,\ramloop[4].ram.r_n_9 ,\ramloop[4].ram.r_n_10 ,\ramloop[4].ram.r_n_11 ,\ramloop[4].ram.r_n_12 ,\ramloop[4].ram.r_n_13 ,\ramloop[4].ram.r_n_14 ,\ramloop[4].ram.r_n_15 }),
.\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_2 (\ramloop[5].ram.r_n_17 ),
.\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_3 (\ramloop[6].ram.r_n_17 ),
.\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_4 (\ramloop[4].ram.r_n_17 ),
.DOBDO({\ramloop[7].ram.r_n_8 ,\ramloop[7].ram.r_n_9 ,\ramloop[7].ram.r_n_10 ,\ramloop[7].ram.r_n_11 ,\ramloop[7].ram.r_n_12 ,\ramloop[7].ram.r_n_13 ,\ramloop[7].ram.r_n_14 ,\ramloop[7].ram.r_n_15 }),
.DOPBDOP(\ramloop[7].ram.r_n_17 ),
.addrb(addrb[13:12]),
.clkb(clkb),
.doutb(doutb[15:7]),
.enb(enb));
system_vga_hessian_1_0_blk_mem_gen_prim_width \ramloop[0].ram.r
(.addra(addra),
.addrb(addrb),
.clka(clka),
.clkb(clkb),
.dina(dina[0]),
.dinb(dinb[0]),
.douta(douta[0]),
.doutb(doutb[0]),
.ena(ena),
.enb(enb),
.wea(wea),
.web(web));
system_vga_hessian_1_0_blk_mem_gen_prim_width__parameterized0 \ramloop[1].ram.r
(.addra(addra),
.addrb(addrb),
.clka(clka),
.clkb(clkb),
.dina(dina[2:1]),
.dinb(dinb[2:1]),
.douta(douta[2:1]),
.doutb(doutb[2:1]),
.ena(ena),
.enb(enb),
.wea(wea),
.web(web));
system_vga_hessian_1_0_blk_mem_gen_prim_width__parameterized1 \ramloop[2].ram.r
(.addra(addra),
.addrb(addrb),
.clka(clka),
.clkb(clkb),
.dina(dina[4:3]),
.dinb(dinb[4:3]),
.douta(douta[4:3]),
.doutb(doutb[4:3]),
.ena(ena),
.enb(enb),
.wea(wea),
.web(web));
system_vga_hessian_1_0_blk_mem_gen_prim_width__parameterized2 \ramloop[3].ram.r
(.addra(addra),
.addrb(addrb),
.clka(clka),
.clkb(clkb),
.dina(dina[6:5]),
.dinb(dinb[6:5]),
.douta(douta[6:5]),
.doutb(doutb[6:5]),
.ena(ena),
.enb(enb),
.wea(wea),
.web(web));
system_vga_hessian_1_0_blk_mem_gen_prim_width__parameterized3 \ramloop[4].ram.r
(.addra(addra[11:0]),
.addrb(addrb[11:0]),
.\bottom_left_0_reg[14] ({\ramloop[4].ram.r_n_0 ,\ramloop[4].ram.r_n_1 ,\ramloop[4].ram.r_n_2 ,\ramloop[4].ram.r_n_3 ,\ramloop[4].ram.r_n_4 ,\ramloop[4].ram.r_n_5 ,\ramloop[4].ram.r_n_6 ,\ramloop[4].ram.r_n_7 }),
.\bottom_left_0_reg[15] (\ramloop[4].ram.r_n_16 ),
.clka(clka),
.clkb(clkb),
.dina(dina[15:7]),
.dinb(dinb[15:7]),
.ena(ena),
.ena_array(ena_array[0]),
.enb(enb),
.enb_array(enb_array[0]),
.\top_right_1_reg[14] ({\ramloop[4].ram.r_n_8 ,\ramloop[4].ram.r_n_9 ,\ramloop[4].ram.r_n_10 ,\ramloop[4].ram.r_n_11 ,\ramloop[4].ram.r_n_12 ,\ramloop[4].ram.r_n_13 ,\ramloop[4].ram.r_n_14 ,\ramloop[4].ram.r_n_15 }),
.\top_right_1_reg[15] (\ramloop[4].ram.r_n_17 ),
.wea(wea),
.web(web));
system_vga_hessian_1_0_blk_mem_gen_prim_width__parameterized4 \ramloop[5].ram.r
(.addra(addra[11:0]),
.addrb(addrb[11:0]),
.\bottom_left_0_reg[14] ({\ramloop[5].ram.r_n_0 ,\ramloop[5].ram.r_n_1 ,\ramloop[5].ram.r_n_2 ,\ramloop[5].ram.r_n_3 ,\ramloop[5].ram.r_n_4 ,\ramloop[5].ram.r_n_5 ,\ramloop[5].ram.r_n_6 ,\ramloop[5].ram.r_n_7 }),
.\bottom_left_0_reg[15] (\ramloop[5].ram.r_n_16 ),
.clka(clka),
.clkb(clkb),
.dina(dina[15:7]),
.dinb(dinb[15:7]),
.ena(ena),
.ena_array(ena_array[1]),
.enb(enb),
.enb_array(enb_array[1]),
.\top_right_1_reg[14] ({\ramloop[5].ram.r_n_8 ,\ramloop[5].ram.r_n_9 ,\ramloop[5].ram.r_n_10 ,\ramloop[5].ram.r_n_11 ,\ramloop[5].ram.r_n_12 ,\ramloop[5].ram.r_n_13 ,\ramloop[5].ram.r_n_14 ,\ramloop[5].ram.r_n_15 }),
.\top_right_1_reg[15] (\ramloop[5].ram.r_n_17 ),
.wea(wea),
.web(web));
system_vga_hessian_1_0_blk_mem_gen_prim_width__parameterized5 \ramloop[6].ram.r
(.addra(addra[11:0]),
.addrb(addrb[11:0]),
.\bottom_left_0_reg[14] ({\ramloop[6].ram.r_n_0 ,\ramloop[6].ram.r_n_1 ,\ramloop[6].ram.r_n_2 ,\ramloop[6].ram.r_n_3 ,\ramloop[6].ram.r_n_4 ,\ramloop[6].ram.r_n_5 ,\ramloop[6].ram.r_n_6 ,\ramloop[6].ram.r_n_7 }),
.\bottom_left_0_reg[15] (\ramloop[6].ram.r_n_16 ),
.clka(clka),
.clkb(clkb),
.dina(dina[15:7]),
.dinb(dinb[15:7]),
.ena(ena),
.ena_array(ena_array[2]),
.enb(enb),
.enb_array(enb_array[2]),
.\top_right_1_reg[14] ({\ramloop[6].ram.r_n_8 ,\ramloop[6].ram.r_n_9 ,\ramloop[6].ram.r_n_10 ,\ramloop[6].ram.r_n_11 ,\ramloop[6].ram.r_n_12 ,\ramloop[6].ram.r_n_13 ,\ramloop[6].ram.r_n_14 ,\ramloop[6].ram.r_n_15 }),
.\top_right_1_reg[15] (\ramloop[6].ram.r_n_17 ),
.wea(wea),
.web(web));
system_vga_hessian_1_0_blk_mem_gen_prim_width__parameterized6 \ramloop[7].ram.r
(.DOADO({\ramloop[7].ram.r_n_0 ,\ramloop[7].ram.r_n_1 ,\ramloop[7].ram.r_n_2 ,\ramloop[7].ram.r_n_3 ,\ramloop[7].ram.r_n_4 ,\ramloop[7].ram.r_n_5 ,\ramloop[7].ram.r_n_6 ,\ramloop[7].ram.r_n_7 }),
.DOBDO({\ramloop[7].ram.r_n_8 ,\ramloop[7].ram.r_n_9 ,\ramloop[7].ram.r_n_10 ,\ramloop[7].ram.r_n_11 ,\ramloop[7].ram.r_n_12 ,\ramloop[7].ram.r_n_13 ,\ramloop[7].ram.r_n_14 ,\ramloop[7].ram.r_n_15 }),
.DOPADOP(\ramloop[7].ram.r_n_16 ),
.DOPBDOP(\ramloop[7].ram.r_n_17 ),
.addra(addra),
.addrb(addrb),
.clka(clka),
.clkb(clkb),
.dina(dina[15:7]),
.dinb(dinb[15:7]),
.ena(ena),
.enb(enb),
.wea(wea),
.web(web));
endmodule |
module system_vga_hessian_1_0_blk_mem_gen_mux
(douta,
ena,
addra,
clka,
DOADO,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram ,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0 ,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1 ,
DOPADOP,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_2 ,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_3 ,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_4 );
output [8:0]douta;
input ena;
input [1:0]addra;
input clka;
input [7:0]DOADO;
input [7:0]\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram ;
input [7:0]\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0 ;
input [7:0]\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1 ;
input [0:0]DOPADOP;
input [0:0]\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_2 ;
input [0:0]\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_3 ;
input [0:0]\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_4 ;
wire [7:0]\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram ;
wire [7:0]\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0 ;
wire [7:0]\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1 ;
wire [0:0]\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_2 ;
wire [0:0]\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_3 ;
wire [0:0]\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_4 ;
wire [7:0]DOADO;
wire [0:0]DOPADOP;
wire [1:0]addra;
wire clka;
wire [8:0]douta;
wire ena;
wire [1:0]sel_pipe;
wire [1:0]sel_pipe_d1;
LUT6 #(
.INIT(64'hAACCAACCF0FFF000))
\douta[10]_INST_0
(.I0(DOADO[3]),
.I1(\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram [3]),
.I2(\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0 [3]),
.I3(sel_pipe_d1[1]),
.I4(\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1 [3]),
.I5(sel_pipe_d1[0]),
.O(douta[3]));
LUT6 #(
.INIT(64'hAACCAACCF0FFF000))
\douta[11]_INST_0
(.I0(DOADO[4]),
.I1(\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram [4]),
.I2(\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0 [4]),
.I3(sel_pipe_d1[1]),
.I4(\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1 [4]),
.I5(sel_pipe_d1[0]),
.O(douta[4]));
LUT6 #(
.INIT(64'hAACCAACCF0FFF000))
\douta[12]_INST_0
(.I0(DOADO[5]),
.I1(\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram [5]),
.I2(\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0 [5]),
.I3(sel_pipe_d1[1]),
.I4(\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1 [5]),
.I5(sel_pipe_d1[0]),
.O(douta[5]));
LUT6 #(
.INIT(64'hAACCAACCF0FFF000))
\douta[13]_INST_0
(.I0(DOADO[6]),
.I1(\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram [6]),
.I2(\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0 [6]),
.I3(sel_pipe_d1[1]),
.I4(\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1 [6]),
.I5(sel_pipe_d1[0]),
.O(douta[6]));
LUT6 #(
.INIT(64'hAACCAACCF0FFF000))
\douta[14]_INST_0
(.I0(DOADO[7]),
.I1(\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram [7]),
.I2(\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0 [7]),
.I3(sel_pipe_d1[1]),
.I4(\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1 [7]),
.I5(sel_pipe_d1[0]),
.O(douta[7]));
LUT6 #(
.INIT(64'hAACCAACCF0FFF000))
\douta[15]_INST_0
(.I0(DOPADOP),
.I1(\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_2 ),
.I2(\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_3 ),
.I3(sel_pipe_d1[1]),
.I4(\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_4 ),
.I5(sel_pipe_d1[0]),
.O(douta[8]));
LUT6 #(
.INIT(64'hAACCAACCF0FFF000))
\douta[7]_INST_0
(.I0(DOADO[0]),
.I1(\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram [0]),
.I2(\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0 [0]),
.I3(sel_pipe_d1[1]),
.I4(\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1 [0]),
.I5(sel_pipe_d1[0]),
.O(douta[0]));
LUT6 #(
.INIT(64'hAACCAACCF0FFF000))
\douta[8]_INST_0
(.I0(DOADO[1]),
.I1(\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram [1]),
.I2(\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0 [1]),
.I3(sel_pipe_d1[1]),
.I4(\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1 [1]),
.I5(sel_pipe_d1[0]),
.O(douta[1]));
LUT6 #(
.INIT(64'hAACCAACCF0FFF000))
\douta[9]_INST_0
(.I0(DOADO[2]),
.I1(\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram [2]),
.I2(\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0 [2]),
.I3(sel_pipe_d1[1]),
.I4(\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1 [2]),
.I5(sel_pipe_d1[0]),
.O(douta[2]));
FDRE #(
.INIT(1'b0))
\no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg[0]
(.C(clka),
.CE(ena),
.D(sel_pipe[0]),
.Q(sel_pipe_d1[0]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg[1]
(.C(clka),
.CE(ena),
.D(sel_pipe[1]),
.Q(sel_pipe_d1[1]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\no_softecc_sel_reg.ce_pri.sel_pipe_reg[0]
(.C(clka),
.CE(ena),
.D(addra[0]),
.Q(sel_pipe[0]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\no_softecc_sel_reg.ce_pri.sel_pipe_reg[1]
(.C(clka),
.CE(ena),
.D(addra[1]),
.Q(sel_pipe[1]),
.R(1'b0));
endmodule |
module system_vga_hessian_1_0_blk_mem_gen_mux__parameterized0
(doutb,
enb,
addrb,
clkb,
DOBDO,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram ,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0 ,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1 ,
DOPBDOP,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_2 ,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_3 ,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_4 );
output [8:0]doutb;
input enb;
input [1:0]addrb;
input clkb;
input [7:0]DOBDO;
input [7:0]\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram ;
input [7:0]\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0 ;
input [7:0]\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1 ;
input [0:0]DOPBDOP;
input [0:0]\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_2 ;
input [0:0]\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_3 ;
input [0:0]\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_4 ;
wire [7:0]\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram ;
wire [7:0]\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0 ;
wire [7:0]\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1 ;
wire [0:0]\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_2 ;
wire [0:0]\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_3 ;
wire [0:0]\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_4 ;
wire [7:0]DOBDO;
wire [0:0]DOPBDOP;
wire [1:0]addrb;
wire clkb;
wire [8:0]doutb;
wire enb;
wire \no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg_n_0_[0] ;
wire \no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg_n_0_[1] ;
wire \no_softecc_sel_reg.ce_pri.sel_pipe_reg_n_0_[0] ;
wire \no_softecc_sel_reg.ce_pri.sel_pipe_reg_n_0_[1] ;
LUT6 #(
.INIT(64'hAACCAACCF0FFF000))
\doutb[10]_INST_0
(.I0(DOBDO[3]),
.I1(\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram [3]),
.I2(\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0 [3]),
.I3(\no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg_n_0_[1] ),
.I4(\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1 [3]),
.I5(\no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg_n_0_[0] ),
.O(doutb[3]));
LUT6 #(
.INIT(64'hAACCAACCF0FFF000))
\doutb[11]_INST_0
(.I0(DOBDO[4]),
.I1(\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram [4]),
.I2(\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0 [4]),
.I3(\no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg_n_0_[1] ),
.I4(\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1 [4]),
.I5(\no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg_n_0_[0] ),
.O(doutb[4]));
LUT6 #(
.INIT(64'hAACCAACCF0FFF000))
\doutb[12]_INST_0
(.I0(DOBDO[5]),
.I1(\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram [5]),
.I2(\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0 [5]),
.I3(\no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg_n_0_[1] ),
.I4(\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1 [5]),
.I5(\no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg_n_0_[0] ),
.O(doutb[5]));
LUT6 #(
.INIT(64'hAACCAACCF0FFF000))
\doutb[13]_INST_0
(.I0(DOBDO[6]),
.I1(\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram [6]),
.I2(\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0 [6]),
.I3(\no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg_n_0_[1] ),
.I4(\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1 [6]),
.I5(\no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg_n_0_[0] ),
.O(doutb[6]));
LUT6 #(
.INIT(64'hAACCAACCF0FFF000))
\doutb[14]_INST_0
(.I0(DOBDO[7]),
.I1(\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram [7]),
.I2(\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0 [7]),
.I3(\no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg_n_0_[1] ),
.I4(\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1 [7]),
.I5(\no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg_n_0_[0] ),
.O(doutb[7]));
LUT6 #(
.INIT(64'hAACCAACCF0FFF000))
\doutb[15]_INST_0
(.I0(DOPBDOP),
.I1(\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_2 ),
.I2(\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_3 ),
.I3(\no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg_n_0_[1] ),
.I4(\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_4 ),
.I5(\no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg_n_0_[0] ),
.O(doutb[8]));
LUT6 #(
.INIT(64'hAACCAACCF0FFF000))
\doutb[7]_INST_0
(.I0(DOBDO[0]),
.I1(\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram [0]),
.I2(\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0 [0]),
.I3(\no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg_n_0_[1] ),
.I4(\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1 [0]),
.I5(\no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg_n_0_[0] ),
.O(doutb[0]));
LUT6 #(
.INIT(64'hAACCAACCF0FFF000))
\doutb[8]_INST_0
(.I0(DOBDO[1]),
.I1(\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram [1]),
.I2(\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0 [1]),
.I3(\no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg_n_0_[1] ),
.I4(\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1 [1]),
.I5(\no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg_n_0_[0] ),
.O(doutb[1]));
LUT6 #(
.INIT(64'hAACCAACCF0FFF000))
\doutb[9]_INST_0
(.I0(DOBDO[2]),
.I1(\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram [2]),
.I2(\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0 [2]),
.I3(\no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg_n_0_[1] ),
.I4(\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1 [2]),
.I5(\no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg_n_0_[0] ),
.O(doutb[2]));
FDRE #(
.INIT(1'b0))
\no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg[0]
(.C(clkb),
.CE(enb),
.D(\no_softecc_sel_reg.ce_pri.sel_pipe_reg_n_0_[0] ),
.Q(\no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg_n_0_[0] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg[1]
(.C(clkb),
.CE(enb),
.D(\no_softecc_sel_reg.ce_pri.sel_pipe_reg_n_0_[1] ),
.Q(\no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg_n_0_[1] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\no_softecc_sel_reg.ce_pri.sel_pipe_reg[0]
(.C(clkb),
.CE(enb),
.D(addrb[0]),
.Q(\no_softecc_sel_reg.ce_pri.sel_pipe_reg_n_0_[0] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\no_softecc_sel_reg.ce_pri.sel_pipe_reg[1]
(.C(clkb),
.CE(enb),
.D(addrb[1]),
.Q(\no_softecc_sel_reg.ce_pri.sel_pipe_reg_n_0_[1] ),
.R(1'b0));
endmodule |
module system_vga_hessian_1_0_blk_mem_gen_prim_width
(douta,
doutb,
clka,
clkb,
ena,
enb,
addra,
addrb,
dina,
dinb,
wea,
web);
output [0:0]douta;
output [0:0]doutb;
input clka;
input clkb;
input ena;
input enb;
input [13:0]addra;
input [13:0]addrb;
input [0:0]dina;
input [0:0]dinb;
input [0:0]wea;
input [0:0]web;
wire [13:0]addra;
wire [13:0]addrb;
wire clka;
wire clkb;
wire [0:0]dina;
wire [0:0]dinb;
wire [0:0]douta;
wire [0:0]doutb;
wire ena;
wire enb;
wire [0:0]wea;
wire [0:0]web;
system_vga_hessian_1_0_blk_mem_gen_prim_wrapper \prim_noinit.ram
(.addra(addra),
.addrb(addrb),
.clka(clka),
.clkb(clkb),
.dina(dina),
.dinb(dinb),
.douta(douta),
.doutb(doutb),
.ena(ena),
.enb(enb),
.wea(wea),
.web(web));
endmodule |
module system_vga_hessian_1_0_blk_mem_gen_prim_width__parameterized0
(douta,
doutb,
clka,
clkb,
ena,
enb,
addra,
addrb,
dina,
dinb,
wea,
web);
output [1:0]douta;
output [1:0]doutb;
input clka;
input clkb;
input ena;
input enb;
input [13:0]addra;
input [13:0]addrb;
input [1:0]dina;
input [1:0]dinb;
input [0:0]wea;
input [0:0]web;
wire [13:0]addra;
wire [13:0]addrb;
wire clka;
wire clkb;
wire [1:0]dina;
wire [1:0]dinb;
wire [1:0]douta;
wire [1:0]doutb;
wire ena;
wire enb;
wire [0:0]wea;
wire [0:0]web;
system_vga_hessian_1_0_blk_mem_gen_prim_wrapper__parameterized0 \prim_noinit.ram
(.addra(addra),
.addrb(addrb),
.clka(clka),
.clkb(clkb),
.dina(dina),
.dinb(dinb),
.douta(douta),
.doutb(doutb),
.ena(ena),
.enb(enb),
.wea(wea),
.web(web));
endmodule |
module system_vga_hessian_1_0_blk_mem_gen_prim_width__parameterized1
(douta,
doutb,
clka,
clkb,
ena,
enb,
addra,
addrb,
dina,
dinb,
wea,
web);
output [1:0]douta;
output [1:0]doutb;
input clka;
input clkb;
input ena;
input enb;
input [13:0]addra;
input [13:0]addrb;
input [1:0]dina;
input [1:0]dinb;
input [0:0]wea;
input [0:0]web;
wire [13:0]addra;
wire [13:0]addrb;
wire clka;
wire clkb;
wire [1:0]dina;
wire [1:0]dinb;
wire [1:0]douta;
wire [1:0]doutb;
wire ena;
wire enb;
wire [0:0]wea;
wire [0:0]web;
system_vga_hessian_1_0_blk_mem_gen_prim_wrapper__parameterized1 \prim_noinit.ram
(.addra(addra),
.addrb(addrb),
.clka(clka),
.clkb(clkb),
.dina(dina),
.dinb(dinb),
.douta(douta),
.doutb(doutb),
.ena(ena),
.enb(enb),
.wea(wea),
.web(web));
endmodule |
module system_vga_hessian_1_0_blk_mem_gen_prim_width__parameterized2
(douta,
doutb,
clka,
clkb,
ena,
enb,
addra,
addrb,
dina,
dinb,
wea,
web);
output [1:0]douta;
output [1:0]doutb;
input clka;
input clkb;
input ena;
input enb;
input [13:0]addra;
input [13:0]addrb;
input [1:0]dina;
input [1:0]dinb;
input [0:0]wea;
input [0:0]web;
wire [13:0]addra;
wire [13:0]addrb;
wire clka;
wire clkb;
wire [1:0]dina;
wire [1:0]dinb;
wire [1:0]douta;
wire [1:0]doutb;
wire ena;
wire enb;
wire [0:0]wea;
wire [0:0]web;
system_vga_hessian_1_0_blk_mem_gen_prim_wrapper__parameterized2 \prim_noinit.ram
(.addra(addra),
.addrb(addrb),
.clka(clka),
.clkb(clkb),
.dina(dina),
.dinb(dinb),
.douta(douta),
.doutb(doutb),
.ena(ena),
.enb(enb),
.wea(wea),
.web(web));
endmodule |
module system_vga_hessian_1_0_blk_mem_gen_prim_width__parameterized3
(\bottom_left_0_reg[14] ,
\top_right_1_reg[14] ,
\bottom_left_0_reg[15] ,
\top_right_1_reg[15] ,
clka,
clkb,
ena_array,
enb_array,
ena,
enb,
addra,
addrb,
dina,
dinb,
wea,
web);
output [7:0]\bottom_left_0_reg[14] ;
output [7:0]\top_right_1_reg[14] ;
output [0:0]\bottom_left_0_reg[15] ;
output [0:0]\top_right_1_reg[15] ;
input clka;
input clkb;
input [0:0]ena_array;
input [0:0]enb_array;
input ena;
input enb;
input [11:0]addra;
input [11:0]addrb;
input [8:0]dina;
input [8:0]dinb;
input [0:0]wea;
input [0:0]web;
wire [11:0]addra;
wire [11:0]addrb;
wire [7:0]\bottom_left_0_reg[14] ;
wire [0:0]\bottom_left_0_reg[15] ;
wire clka;
wire clkb;
wire [8:0]dina;
wire [8:0]dinb;
wire ena;
wire [0:0]ena_array;
wire enb;
wire [0:0]enb_array;
wire [7:0]\top_right_1_reg[14] ;
wire [0:0]\top_right_1_reg[15] ;
wire [0:0]wea;
wire [0:0]web;
system_vga_hessian_1_0_blk_mem_gen_prim_wrapper__parameterized3 \prim_noinit.ram
(.addra(addra),
.addrb(addrb),
.\bottom_left_0_reg[14] (\bottom_left_0_reg[14] ),
.\bottom_left_0_reg[15] (\bottom_left_0_reg[15] ),
.clka(clka),
.clkb(clkb),
.dina(dina),
.dinb(dinb),
.ena(ena),
.ena_array(ena_array),
.enb(enb),
.enb_array(enb_array),
.\top_right_1_reg[14] (\top_right_1_reg[14] ),
.\top_right_1_reg[15] (\top_right_1_reg[15] ),
.wea(wea),
.web(web));
endmodule |
module system_vga_hessian_1_0_blk_mem_gen_prim_width__parameterized4
(\bottom_left_0_reg[14] ,
\top_right_1_reg[14] ,
\bottom_left_0_reg[15] ,
\top_right_1_reg[15] ,
clka,
clkb,
ena_array,
enb_array,
ena,
enb,
addra,
addrb,
dina,
dinb,
wea,
web);
output [7:0]\bottom_left_0_reg[14] ;
output [7:0]\top_right_1_reg[14] ;
output [0:0]\bottom_left_0_reg[15] ;
output [0:0]\top_right_1_reg[15] ;
input clka;
input clkb;
input [0:0]ena_array;
input [0:0]enb_array;
input ena;
input enb;
input [11:0]addra;
input [11:0]addrb;
input [8:0]dina;
input [8:0]dinb;
input [0:0]wea;
input [0:0]web;
wire [11:0]addra;
wire [11:0]addrb;
wire [7:0]\bottom_left_0_reg[14] ;
wire [0:0]\bottom_left_0_reg[15] ;
wire clka;
wire clkb;
wire [8:0]dina;
wire [8:0]dinb;
wire ena;
wire [0:0]ena_array;
wire enb;
wire [0:0]enb_array;
wire [7:0]\top_right_1_reg[14] ;
wire [0:0]\top_right_1_reg[15] ;
wire [0:0]wea;
wire [0:0]web;
system_vga_hessian_1_0_blk_mem_gen_prim_wrapper__parameterized4 \prim_noinit.ram
(.addra(addra),
.addrb(addrb),
.\bottom_left_0_reg[14] (\bottom_left_0_reg[14] ),
.\bottom_left_0_reg[15] (\bottom_left_0_reg[15] ),
.clka(clka),
.clkb(clkb),
.dina(dina),
.dinb(dinb),
.ena(ena),
.ena_array(ena_array),
.enb(enb),
.enb_array(enb_array),
.\top_right_1_reg[14] (\top_right_1_reg[14] ),
.\top_right_1_reg[15] (\top_right_1_reg[15] ),
.wea(wea),
.web(web));
endmodule |
module system_vga_hessian_1_0_blk_mem_gen_prim_width__parameterized5
(\bottom_left_0_reg[14] ,
\top_right_1_reg[14] ,
\bottom_left_0_reg[15] ,
\top_right_1_reg[15] ,
clka,
clkb,
ena_array,
enb_array,
ena,
enb,
addra,
addrb,
dina,
dinb,
wea,
web);
output [7:0]\bottom_left_0_reg[14] ;
output [7:0]\top_right_1_reg[14] ;
output [0:0]\bottom_left_0_reg[15] ;
output [0:0]\top_right_1_reg[15] ;
input clka;
input clkb;
input [0:0]ena_array;
input [0:0]enb_array;
input ena;
input enb;
input [11:0]addra;
input [11:0]addrb;
input [8:0]dina;
input [8:0]dinb;
input [0:0]wea;
input [0:0]web;
wire [11:0]addra;
wire [11:0]addrb;
wire [7:0]\bottom_left_0_reg[14] ;
wire [0:0]\bottom_left_0_reg[15] ;
wire clka;
wire clkb;
wire [8:0]dina;
wire [8:0]dinb;
wire ena;
wire [0:0]ena_array;
wire enb;
wire [0:0]enb_array;
wire [7:0]\top_right_1_reg[14] ;
wire [0:0]\top_right_1_reg[15] ;
wire [0:0]wea;
wire [0:0]web;
system_vga_hessian_1_0_blk_mem_gen_prim_wrapper__parameterized5 \prim_noinit.ram
(.addra(addra),
.addrb(addrb),
.\bottom_left_0_reg[14] (\bottom_left_0_reg[14] ),
.\bottom_left_0_reg[15] (\bottom_left_0_reg[15] ),
.clka(clka),
.clkb(clkb),
.dina(dina),
.dinb(dinb),
.ena(ena),
.ena_array(ena_array),
.enb(enb),
.enb_array(enb_array),
.\top_right_1_reg[14] (\top_right_1_reg[14] ),
.\top_right_1_reg[15] (\top_right_1_reg[15] ),
.wea(wea),
.web(web));
endmodule |
module system_vga_hessian_1_0_blk_mem_gen_prim_width__parameterized6
(DOADO,
DOBDO,
DOPADOP,
DOPBDOP,
clka,
clkb,
ena,
enb,
addra,
addrb,
dina,
dinb,
wea,
web);
output [7:0]DOADO;
output [7:0]DOBDO;
output [0:0]DOPADOP;
output [0:0]DOPBDOP;
input clka;
input clkb;
input ena;
input enb;
input [13:0]addra;
input [13:0]addrb;
input [8:0]dina;
input [8:0]dinb;
input [0:0]wea;
input [0:0]web;
wire [7:0]DOADO;
wire [7:0]DOBDO;
wire [0:0]DOPADOP;
wire [0:0]DOPBDOP;
wire [13:0]addra;
wire [13:0]addrb;
wire clka;
wire clkb;
wire [8:0]dina;
wire [8:0]dinb;
wire ena;
wire enb;
wire [0:0]wea;
wire [0:0]web;
system_vga_hessian_1_0_blk_mem_gen_prim_wrapper__parameterized6 \prim_noinit.ram
(.DOADO(DOADO),
.DOBDO(DOBDO),
.DOPADOP(DOPADOP),
.DOPBDOP(DOPBDOP),
.addra(addra),
.addrb(addrb),
.clka(clka),
.clkb(clkb),
.dina(dina),
.dinb(dinb),
.ena(ena),
.enb(enb),
.wea(wea),
.web(web));
endmodule |
module system_vga_hessian_1_0_blk_mem_gen_prim_wrapper
(douta,
doutb,
clka,
clkb,
ena,
enb,
addra,
addrb,
dina,
dinb,
wea,
web);
output [0:0]douta;
output [0:0]doutb;
input clka;
input clkb;
input ena;
input enb;
input [13:0]addra;
input [13:0]addrb;
input [0:0]dina;
input [0:0]dinb;
input [0:0]wea;
input [0:0]web;
wire [13:0]addra;
wire [13:0]addrb;
wire clka;
wire clkb;
wire [0:0]dina;
wire [0:0]dinb;
wire [0:0]douta;
wire [0:0]doutb;
wire ena;
wire enb;
wire [0:0]wea;
wire [0:0]web;
wire [15:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_DOADO_UNCONNECTED ;
wire [15:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_DOBDO_UNCONNECTED ;
wire [1:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_DOPADOP_UNCONNECTED ;
wire [1:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_DOPBDOP_UNCONNECTED ;
(* CLOCK_DOMAINS = "COMMON" *)
(* box_type = "PRIMITIVE" *)
RAMB18E1 #(
.DOA_REG(1),
.DOB_REG(1),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(18'h00000),
.INIT_B(18'h00000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(1),
.READ_WIDTH_B(1),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(18'h00000),
.SRVAL_B(18'h00000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(1),
.WRITE_WIDTH_B(1))
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram
(.ADDRARDADDR(addra),
.ADDRBWRADDR(addrb),
.CLKARDCLK(clka),
.CLKBWRCLK(clkb),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dina}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dinb}),
.DIPADIP({1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0}),
.DOADO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_DOADO_UNCONNECTED [15:1],douta}),
.DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_DOBDO_UNCONNECTED [15:1],doutb}),
.DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_DOPADOP_UNCONNECTED [1:0]),
.DOPBDOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_DOPBDOP_UNCONNECTED [1:0]),
.ENARDEN(ena),
.ENBWREN(enb),
.REGCEAREGCE(ena),
.REGCEB(enb),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.WEA({wea,wea}),
.WEBWE({1'b0,1'b0,web,web}));
endmodule |
module system_vga_hessian_1_0_blk_mem_gen_prim_wrapper__parameterized0
(douta,
doutb,
clka,
clkb,
ena,
enb,
addra,
addrb,
dina,
dinb,
wea,
web);
output [1:0]douta;
output [1:0]doutb;
input clka;
input clkb;
input ena;
input enb;
input [13:0]addra;
input [13:0]addrb;
input [1:0]dina;
input [1:0]dinb;
input [0:0]wea;
input [0:0]web;
wire [13:0]addra;
wire [13:0]addrb;
wire clka;
wire clkb;
wire [1:0]dina;
wire [1:0]dinb;
wire [1:0]douta;
wire [1:0]doutb;
wire ena;
wire enb;
wire [0:0]wea;
wire [0:0]web;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:2]\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ;
wire [31:2]\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* CLOCK_DOMAINS = "COMMON" *)
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(1),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(2),
.READ_WIDTH_B(2),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(2),
.WRITE_WIDTH_B(2))
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,addra,1'b1}),
.ADDRBWRADDR({1'b1,addrb,1'b1}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(clka),
.CLKBWRCLK(clkb),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dina}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dinb}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:2],douta}),
.DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:2],doutb}),
.DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]),
.DOPBDOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:0]),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(ena),
.ENBWREN(enb),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(ena),
.REGCEB(enb),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({wea,wea,wea,wea}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,web,web,web,web}));
endmodule |
module system_vga_hessian_1_0_blk_mem_gen_prim_wrapper__parameterized1
(douta,
doutb,
clka,
clkb,
ena,
enb,
addra,
addrb,
dina,
dinb,
wea,
web);
output [1:0]douta;
output [1:0]doutb;
input clka;
input clkb;
input ena;
input enb;
input [13:0]addra;
input [13:0]addrb;
input [1:0]dina;
input [1:0]dinb;
input [0:0]wea;
input [0:0]web;
wire [13:0]addra;
wire [13:0]addrb;
wire clka;
wire clkb;
wire [1:0]dina;
wire [1:0]dinb;
wire [1:0]douta;
wire [1:0]doutb;
wire ena;
wire enb;
wire [0:0]wea;
wire [0:0]web;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:2]\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ;
wire [31:2]\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* CLOCK_DOMAINS = "COMMON" *)
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(1),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(2),
.READ_WIDTH_B(2),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(2),
.WRITE_WIDTH_B(2))
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,addra,1'b1}),
.ADDRBWRADDR({1'b1,addrb,1'b1}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(clka),
.CLKBWRCLK(clkb),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dina}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dinb}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:2],douta}),
.DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:2],doutb}),
.DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]),
.DOPBDOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:0]),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(ena),
.ENBWREN(enb),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(ena),
.REGCEB(enb),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({wea,wea,wea,wea}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,web,web,web,web}));
endmodule |
module system_vga_hessian_1_0_blk_mem_gen_prim_wrapper__parameterized2
(douta,
doutb,
clka,
clkb,
ena,
enb,
addra,
addrb,
dina,
dinb,
wea,
web);
output [1:0]douta;
output [1:0]doutb;
input clka;
input clkb;
input ena;
input enb;
input [13:0]addra;
input [13:0]addrb;
input [1:0]dina;
input [1:0]dinb;
input [0:0]wea;
input [0:0]web;
wire [13:0]addra;
wire [13:0]addrb;
wire clka;
wire clkb;
wire [1:0]dina;
wire [1:0]dinb;
wire [1:0]douta;
wire [1:0]doutb;
wire ena;
wire enb;
wire [0:0]wea;
wire [0:0]web;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:2]\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ;
wire [31:2]\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* CLOCK_DOMAINS = "COMMON" *)
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(1),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(2),
.READ_WIDTH_B(2),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(2),
.WRITE_WIDTH_B(2))
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,addra,1'b1}),
.ADDRBWRADDR({1'b1,addrb,1'b1}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(clka),
.CLKBWRCLK(clkb),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dina}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dinb}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:2],douta}),
.DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:2],doutb}),
.DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]),
.DOPBDOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:0]),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(ena),
.ENBWREN(enb),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(ena),
.REGCEB(enb),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({wea,wea,wea,wea}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,web,web,web,web}));
endmodule |
module system_vga_hessian_1_0_blk_mem_gen_prim_wrapper__parameterized3
(\bottom_left_0_reg[14] ,
\top_right_1_reg[14] ,
\bottom_left_0_reg[15] ,
\top_right_1_reg[15] ,
clka,
clkb,
ena_array,
enb_array,
ena,
enb,
addra,
addrb,
dina,
dinb,
wea,
web);
output [7:0]\bottom_left_0_reg[14] ;
output [7:0]\top_right_1_reg[14] ;
output [0:0]\bottom_left_0_reg[15] ;
output [0:0]\top_right_1_reg[15] ;
input clka;
input clkb;
input [0:0]ena_array;
input [0:0]enb_array;
input ena;
input enb;
input [11:0]addra;
input [11:0]addrb;
input [8:0]dina;
input [8:0]dinb;
input [0:0]wea;
input [0:0]web;
wire [11:0]addra;
wire [11:0]addrb;
wire [7:0]\bottom_left_0_reg[14] ;
wire [0:0]\bottom_left_0_reg[15] ;
wire clka;
wire clkb;
wire [8:0]dina;
wire [8:0]dinb;
wire ena;
wire [0:0]ena_array;
wire enb;
wire [0:0]enb_array;
wire [7:0]\top_right_1_reg[14] ;
wire [0:0]\top_right_1_reg[15] ;
wire [0:0]wea;
wire [0:0]web;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ;
wire [31:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ;
wire [3:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* CLOCK_DOMAINS = "COMMON" *)
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(1),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(9),
.READ_WIDTH_B(9),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(9),
.WRITE_WIDTH_B(9))
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,addra,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b1,addrb,1'b1,1'b1,1'b1}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(clka),
.CLKBWRCLK(clkb),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dina[7:0]}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dinb[7:0]}),
.DIPADIP({1'b0,1'b0,1'b0,dina[8]}),
.DIPBDIP({1'b0,1'b0,1'b0,dinb[8]}),
.DOADO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:8],\bottom_left_0_reg[14] }),
.DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:8],\top_right_1_reg[14] }),
.DOPADOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:1],\bottom_left_0_reg[15] }),
.DOPBDOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:1],\top_right_1_reg[15] }),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(ena_array),
.ENBWREN(enb_array),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(ena),
.REGCEB(enb),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({wea,wea,wea,wea}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,web,web,web,web}));
endmodule |
module system_vga_hessian_1_0_blk_mem_gen_prim_wrapper__parameterized4
(\bottom_left_0_reg[14] ,
\top_right_1_reg[14] ,
\bottom_left_0_reg[15] ,
\top_right_1_reg[15] ,
clka,
clkb,
ena_array,
enb_array,
ena,
enb,
addra,
addrb,
dina,
dinb,
wea,
web);
output [7:0]\bottom_left_0_reg[14] ;
output [7:0]\top_right_1_reg[14] ;
output [0:0]\bottom_left_0_reg[15] ;
output [0:0]\top_right_1_reg[15] ;
input clka;
input clkb;
input [0:0]ena_array;
input [0:0]enb_array;
input ena;
input enb;
input [11:0]addra;
input [11:0]addrb;
input [8:0]dina;
input [8:0]dinb;
input [0:0]wea;
input [0:0]web;
wire [11:0]addra;
wire [11:0]addrb;
wire [7:0]\bottom_left_0_reg[14] ;
wire [0:0]\bottom_left_0_reg[15] ;
wire clka;
wire clkb;
wire [8:0]dina;
wire [8:0]dinb;
wire ena;
wire [0:0]ena_array;
wire enb;
wire [0:0]enb_array;
wire [7:0]\top_right_1_reg[14] ;
wire [0:0]\top_right_1_reg[15] ;
wire [0:0]wea;
wire [0:0]web;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ;
wire [31:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ;
wire [3:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* CLOCK_DOMAINS = "COMMON" *)
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(1),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(9),
.READ_WIDTH_B(9),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(9),
.WRITE_WIDTH_B(9))
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,addra,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b1,addrb,1'b1,1'b1,1'b1}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(clka),
.CLKBWRCLK(clkb),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dina[7:0]}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dinb[7:0]}),
.DIPADIP({1'b0,1'b0,1'b0,dina[8]}),
.DIPBDIP({1'b0,1'b0,1'b0,dinb[8]}),
.DOADO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:8],\bottom_left_0_reg[14] }),
.DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:8],\top_right_1_reg[14] }),
.DOPADOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:1],\bottom_left_0_reg[15] }),
.DOPBDOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:1],\top_right_1_reg[15] }),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(ena_array),
.ENBWREN(enb_array),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(ena),
.REGCEB(enb),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({wea,wea,wea,wea}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,web,web,web,web}));
endmodule |
module system_vga_hessian_1_0_blk_mem_gen_prim_wrapper__parameterized5
(\bottom_left_0_reg[14] ,
\top_right_1_reg[14] ,
\bottom_left_0_reg[15] ,
\top_right_1_reg[15] ,
clka,
clkb,
ena_array,
enb_array,
ena,
enb,
addra,
addrb,
dina,
dinb,
wea,
web);
output [7:0]\bottom_left_0_reg[14] ;
output [7:0]\top_right_1_reg[14] ;
output [0:0]\bottom_left_0_reg[15] ;
output [0:0]\top_right_1_reg[15] ;
input clka;
input clkb;
input [0:0]ena_array;
input [0:0]enb_array;
input ena;
input enb;
input [11:0]addra;
input [11:0]addrb;
input [8:0]dina;
input [8:0]dinb;
input [0:0]wea;
input [0:0]web;
wire [11:0]addra;
wire [11:0]addrb;
wire [7:0]\bottom_left_0_reg[14] ;
wire [0:0]\bottom_left_0_reg[15] ;
wire clka;
wire clkb;
wire [8:0]dina;
wire [8:0]dinb;
wire ena;
wire [0:0]ena_array;
wire enb;
wire [0:0]enb_array;
wire [7:0]\top_right_1_reg[14] ;
wire [0:0]\top_right_1_reg[15] ;
wire [0:0]wea;
wire [0:0]web;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ;
wire [31:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ;
wire [3:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* CLOCK_DOMAINS = "COMMON" *)
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(1),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(9),
.READ_WIDTH_B(9),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(9),
.WRITE_WIDTH_B(9))
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,addra,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b1,addrb,1'b1,1'b1,1'b1}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(clka),
.CLKBWRCLK(clkb),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dina[7:0]}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dinb[7:0]}),
.DIPADIP({1'b0,1'b0,1'b0,dina[8]}),
.DIPBDIP({1'b0,1'b0,1'b0,dinb[8]}),
.DOADO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:8],\bottom_left_0_reg[14] }),
.DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:8],\top_right_1_reg[14] }),
.DOPADOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:1],\bottom_left_0_reg[15] }),
.DOPBDOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:1],\top_right_1_reg[15] }),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(ena_array),
.ENBWREN(enb_array),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(ena),
.REGCEB(enb),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({wea,wea,wea,wea}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,web,web,web,web}));
endmodule |
module system_vga_hessian_1_0_blk_mem_gen_prim_wrapper__parameterized6
(DOADO,
DOBDO,
DOPADOP,
DOPBDOP,
clka,
clkb,
ena,
enb,
addra,
addrb,
dina,
dinb,
wea,
web);
output [7:0]DOADO;
output [7:0]DOBDO;
output [0:0]DOPADOP;
output [0:0]DOPBDOP;
input clka;
input clkb;
input ena;
input enb;
input [13:0]addra;
input [13:0]addrb;
input [8:0]dina;
input [8:0]dinb;
input [0:0]wea;
input [0:0]web;
wire \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_i_1_n_0 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_i_2_n_0 ;
wire [7:0]DOADO;
wire [7:0]DOBDO;
wire [0:0]DOPADOP;
wire [0:0]DOPBDOP;
wire [13:0]addra;
wire [13:0]addrb;
wire clka;
wire clkb;
wire [8:0]dina;
wire [8:0]dinb;
wire ena;
wire enb;
wire [0:0]wea;
wire [0:0]web;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ;
wire [31:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ;
wire [3:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* CLOCK_DOMAINS = "COMMON" *)
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(1),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(9),
.READ_WIDTH_B(9),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(9),
.WRITE_WIDTH_B(9))
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,addra[11:0],1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b1,addrb[11:0],1'b1,1'b1,1'b1}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(clka),
.CLKBWRCLK(clkb),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dina[7:0]}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dinb[7:0]}),
.DIPADIP({1'b0,1'b0,1'b0,dina[8]}),
.DIPBDIP({1'b0,1'b0,1'b0,dinb[8]}),
.DOADO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:8],DOADO}),
.DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:8],DOBDO}),
.DOPADOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:1],DOPADOP}),
.DOPBDOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:1],DOPBDOP}),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_i_1_n_0 ),
.ENBWREN(\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_i_2_n_0 ),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(ena),
.REGCEB(enb),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({wea,wea,wea,wea}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,web,web,web,web}));
LUT3 #(
.INIT(8'h80))
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_i_1
(.I0(addra[13]),
.I1(addra[12]),
.I2(ena),
.O(\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_i_1_n_0 ));
LUT3 #(
.INIT(8'h80))
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_i_2
(.I0(addrb[13]),
.I1(addrb[12]),
.I2(enb),
.O(\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_i_2_n_0 ));
endmodule |
module system_vga_hessian_1_0_blk_mem_gen_top
(douta,
doutb,
addra,
ena,
addrb,
enb,
clka,
clkb,
dina,
dinb,
wea,
web);
output [15:0]douta;
output [15:0]doutb;
input [13:0]addra;
input ena;
input [13:0]addrb;
input enb;
input clka;
input clkb;
input [15:0]dina;
input [15:0]dinb;
input [0:0]wea;
input [0:0]web;
wire [13:0]addra;
wire [13:0]addrb;
wire clka;
wire clkb;
wire [15:0]dina;
wire [15:0]dinb;
wire [15:0]douta;
wire [15:0]doutb;
wire ena;
wire enb;
wire [0:0]wea;
wire [0:0]web;
system_vga_hessian_1_0_blk_mem_gen_generic_cstr \valid.cstr
(.addra(addra),
.addrb(addrb),
.clka(clka),
.clkb(clkb),
.dina(dina),
.dinb(dinb),
.douta(douta),
.doutb(doutb),
.ena(ena),
.enb(enb),
.wea(wea),
.web(web));
endmodule |
module system_vga_hessian_1_0_blk_mem_gen_v8_3_5
(clka,
rsta,
ena,
regcea,
wea,
addra,
dina,
douta,
clkb,
rstb,
enb,
regceb,
web,
addrb,
dinb,
doutb,
injectsbiterr,
injectdbiterr,
eccpipece,
sbiterr,
dbiterr,
rdaddrecc,
sleep,
deepsleep,
shutdown,
rsta_busy,
rstb_busy,
s_aclk,
s_aresetn,
s_axi_awid,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awvalid,
s_axi_awready,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wvalid,
s_axi_wready,
s_axi_bid,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_arid,
s_axi_araddr,
s_axi_arlen,
s_axi_arsize,
s_axi_arburst,
s_axi_arvalid,
s_axi_arready,
s_axi_rid,
s_axi_rdata,
s_axi_rresp,
s_axi_rlast,
s_axi_rvalid,
s_axi_rready,
s_axi_injectsbiterr,
s_axi_injectdbiterr,
s_axi_sbiterr,
s_axi_dbiterr,
s_axi_rdaddrecc);
input clka;
input rsta;
input ena;
input regcea;
input [0:0]wea;
input [13:0]addra;
input [15:0]dina;
output [15:0]douta;
input clkb;
input rstb;
input enb;
input regceb;
input [0:0]web;
input [13:0]addrb;
input [15:0]dinb;
output [15:0]doutb;
input injectsbiterr;
input injectdbiterr;
input eccpipece;
output sbiterr;
output dbiterr;
output [13:0]rdaddrecc;
input sleep;
input deepsleep;
input shutdown;
output rsta_busy;
output rstb_busy;
input s_aclk;
input s_aresetn;
input [3:0]s_axi_awid;
input [31:0]s_axi_awaddr;
input [7:0]s_axi_awlen;
input [2:0]s_axi_awsize;
input [1:0]s_axi_awburst;
input s_axi_awvalid;
output s_axi_awready;
input [15:0]s_axi_wdata;
input [0:0]s_axi_wstrb;
input s_axi_wlast;
input s_axi_wvalid;
output s_axi_wready;
output [3:0]s_axi_bid;
output [1:0]s_axi_bresp;
output s_axi_bvalid;
input s_axi_bready;
input [3:0]s_axi_arid;
input [31:0]s_axi_araddr;
input [7:0]s_axi_arlen;
input [2:0]s_axi_arsize;
input [1:0]s_axi_arburst;
input s_axi_arvalid;
output s_axi_arready;
output [3:0]s_axi_rid;
output [15:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output s_axi_rlast;
output s_axi_rvalid;
input s_axi_rready;
input s_axi_injectsbiterr;
input s_axi_injectdbiterr;
output s_axi_sbiterr;
output s_axi_dbiterr;
output [13:0]s_axi_rdaddrecc;
wire \<const0> ;
wire [13:0]addra;
wire [13:0]addrb;
wire clka;
wire clkb;
wire [15:0]dina;
wire [15:0]dinb;
wire [15:0]douta;
wire [15:0]doutb;
wire ena;
wire enb;
wire [0:0]wea;
wire [0:0]web;
assign dbiterr = \<const0> ;
assign rdaddrecc[13] = \<const0> ;
assign rdaddrecc[12] = \<const0> ;
assign rdaddrecc[11] = \<const0> ;
assign rdaddrecc[10] = \<const0> ;
assign rdaddrecc[9] = \<const0> ;
assign rdaddrecc[8] = \<const0> ;
assign rdaddrecc[7] = \<const0> ;
assign rdaddrecc[6] = \<const0> ;
assign rdaddrecc[5] = \<const0> ;
assign rdaddrecc[4] = \<const0> ;
assign rdaddrecc[3] = \<const0> ;
assign rdaddrecc[2] = \<const0> ;
assign rdaddrecc[1] = \<const0> ;
assign rdaddrecc[0] = \<const0> ;
assign rsta_busy = \<const0> ;
assign rstb_busy = \<const0> ;
assign s_axi_arready = \<const0> ;
assign s_axi_awready = \<const0> ;
assign s_axi_bid[3] = \<const0> ;
assign s_axi_bid[2] = \<const0> ;
assign s_axi_bid[1] = \<const0> ;
assign s_axi_bid[0] = \<const0> ;
assign s_axi_bresp[1] = \<const0> ;
assign s_axi_bresp[0] = \<const0> ;
assign s_axi_bvalid = \<const0> ;
assign s_axi_dbiterr = \<const0> ;
assign s_axi_rdaddrecc[13] = \<const0> ;
assign s_axi_rdaddrecc[12] = \<const0> ;
assign s_axi_rdaddrecc[11] = \<const0> ;
assign s_axi_rdaddrecc[10] = \<const0> ;
assign s_axi_rdaddrecc[9] = \<const0> ;
assign s_axi_rdaddrecc[8] = \<const0> ;
assign s_axi_rdaddrecc[7] = \<const0> ;
assign s_axi_rdaddrecc[6] = \<const0> ;
assign s_axi_rdaddrecc[5] = \<const0> ;
assign s_axi_rdaddrecc[4] = \<const0> ;
assign s_axi_rdaddrecc[3] = \<const0> ;
assign s_axi_rdaddrecc[2] = \<const0> ;
assign s_axi_rdaddrecc[1] = \<const0> ;
assign s_axi_rdaddrecc[0] = \<const0> ;
assign s_axi_rdata[15] = \<const0> ;
assign s_axi_rdata[14] = \<const0> ;
assign s_axi_rdata[13] = \<const0> ;
assign s_axi_rdata[12] = \<const0> ;
assign s_axi_rdata[11] = \<const0> ;
assign s_axi_rdata[10] = \<const0> ;
assign s_axi_rdata[9] = \<const0> ;
assign s_axi_rdata[8] = \<const0> ;
assign s_axi_rdata[7] = \<const0> ;
assign s_axi_rdata[6] = \<const0> ;
assign s_axi_rdata[5] = \<const0> ;
assign s_axi_rdata[4] = \<const0> ;
assign s_axi_rdata[3] = \<const0> ;
assign s_axi_rdata[2] = \<const0> ;
assign s_axi_rdata[1] = \<const0> ;
assign s_axi_rdata[0] = \<const0> ;
assign s_axi_rid[3] = \<const0> ;
assign s_axi_rid[2] = \<const0> ;
assign s_axi_rid[1] = \<const0> ;
assign s_axi_rid[0] = \<const0> ;
assign s_axi_rlast = \<const0> ;
assign s_axi_rresp[1] = \<const0> ;
assign s_axi_rresp[0] = \<const0> ;
assign s_axi_rvalid = \<const0> ;
assign s_axi_sbiterr = \<const0> ;
assign s_axi_wready = \<const0> ;
assign sbiterr = \<const0> ;
GND GND
(.G(\<const0> ));
system_vga_hessian_1_0_blk_mem_gen_v8_3_5_synth inst_blk_mem_gen
(.addra(addra),
.addrb(addrb),
.clka(clka),
.clkb(clkb),
.dina(dina),
.dinb(dinb),
.douta(douta),
.doutb(doutb),
.ena(ena),
.enb(enb),
.wea(wea),
.web(web));
endmodule |
module system_vga_hessian_1_0_blk_mem_gen_v8_3_5_synth
(douta,
doutb,
addra,
ena,
addrb,
enb,
clka,
clkb,
dina,
dinb,
wea,
web);
output [15:0]douta;
output [15:0]doutb;
input [13:0]addra;
input ena;
input [13:0]addrb;
input enb;
input clka;
input clkb;
input [15:0]dina;
input [15:0]dinb;
input [0:0]wea;
input [0:0]web;
wire [13:0]addra;
wire [13:0]addrb;
wire clka;
wire clkb;
wire [15:0]dina;
wire [15:0]dinb;
wire [15:0]douta;
wire [15:0]doutb;
wire ena;
wire enb;
wire [0:0]wea;
wire [0:0]web;
system_vga_hessian_1_0_blk_mem_gen_top \gnbram.gnativebmg.native_blk_mem_gen
(.addra(addra),
.addrb(addrb),
.clka(clka),
.clkb(clkb),
.dina(dina),
.dinb(dinb),
.douta(douta),
.doutb(doutb),
.ena(ena),
.enb(enb),
.wea(wea),
.web(web));
endmodule |
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule |
module pixel(clk, pixclk, attcode,
pixel, blank, hsync_in, vsync_in, blink,
hsync, vsync, r, g, b);
input clk;
input pixclk;
input [7:0] attcode;
input pixel;
input blank;
input hsync_in;
input vsync_in;
input blink;
output reg hsync;
output reg vsync;
output reg [2:0] r;
output reg [2:0] g;
output reg [2:0] b;
wire blink_bit;
wire bg_red;
wire bg_green;
wire bg_blue;
wire inten_bit;
wire fg_red;
wire fg_green;
wire fg_blue;
wire foreground;
wire intensify;
wire red;
wire green;
wire blue;
assign blink_bit = attcode[7];
assign bg_red = attcode[6];
assign bg_green = attcode[5];
assign bg_blue = attcode[4];
assign inten_bit = attcode[3];
assign fg_red = attcode[2];
assign fg_green = attcode[1];
assign fg_blue = attcode[0];
assign foreground = pixel & ~(blink_bit & blink);
assign intensify = foreground & inten_bit;
assign red = (foreground ? fg_red : bg_red);
assign green = (foreground ? fg_green : bg_green);
assign blue = (foreground ? fg_blue : bg_blue);
always @(posedge clk) begin
if (pixclk == 1) begin
hsync <= hsync_in;
vsync <= vsync_in;
r[2] <= blank & red;
r[1] <= blank & intensify;
r[0] <= blank & red & intensify;
g[2] <= blank & green;
g[1] <= blank & intensify;
g[0] <= blank & green & intensify;
b[2] <= blank & blue;
b[1] <= blank & intensify;
b[0] <= blank & blue & intensify;
end
end
endmodule |
module flt_add_sub
(
input clk,
input sub,
input [31:0] afl,
input [31:0] bfl,
output reg [31:0] fl
);
reg [24:0] ai_0; // Mantisa of the Float
reg [24:0] bi_0; // Mantisa of the Float
reg sub_0;
reg [7:0] aefl_0; // Exponent of the Float
reg [24:0] n_ai_0; // Mantisa of the Float
reg [24:0] n_bi_0; // Mantisa of the Float
reg [24:0] n_mfl_0; // Mantisa of the Float
reg sfl_0; // Sign of the Float
reg [24:0] nn_mfl_0; // Mantisa of the Float
reg [31:0] afl_0;
reg [31:0] bfl_0;
reg afl_eq_bfl_0;
reg afl_eqz_0;
reg bfl_eqz_0;
reg [24:0] nn_mfl_1; // Mantisa of the Float
reg [7:0] nom_shft_1; // Mantisa of the Float
reg [24:0] nmfl_1; // Mantisa of the Float
reg [7:0] n_efl_1; // Exponent of the Float
reg sub_1;
reg afl_eqz_1;
reg bfl_eqz_1;
reg afl_eq_bfl_1;
reg [7:0] aefl_1; // Exponent of the Float
reg sfl_1; // Sign of the Float
reg [31:0] afl_1;
reg [31:0] bfl_1;
reg [8:0] agb; // Exponent difference.
reg [8:0] bga; // Exponent difference.
always @* agb = bfl[30:23] - afl[30:23];
always @* bga = afl[30:23] - bfl[30:23];
// Pipe 0
always @(posedge clk) begin
sub_0 <= sub;
afl_0 <= afl;
bfl_0 <= bfl;
afl_eq_bfl_0 <= (afl[30:0] == bfl[30:0]) &
((~sub & (afl[31] ^ bfl[31])) | (sub & (afl[31] ~^ bfl[31])));
afl_eqz_0 <= ~|afl[30:0];
bfl_eqz_0 <= ~|bfl[30:0];
if(agb[8]) // A exponant is greater than B exponant.
begin
bi_0 <= {(sub ^ bfl[31]), ({1'b1,bfl[22:0]} >> (bga[7:0]))};
ai_0 <= {afl[31], {1'b1,afl[22:0]}};
aefl_0 <= afl[30:23];
end
else // B exponant is greater than A exponant.
begin
ai_0 <= {afl[31], ({1'b1,afl[22:0]} >> (agb[7:0]))};
aefl_0 <= bfl[30:23];
bi_0 <= {(sub ^ bfl[31]), {1'b1,bfl[22:0]}};
end
end
always @*
begin
case({ai_0[24],bi_0[24]})
2'b00:begin
n_ai_0 = ai_0;
n_bi_0 = bi_0;
end
2'b11:begin
n_ai_0 = {1'b0,ai_0[23:0]};
n_bi_0 = {1'b0,bi_0[23:0]};
end
2'b10:begin
n_ai_0 = {ai_0[24],~ai_0[23:0]};
n_bi_0 = bi_0;
end
2'b01:begin
n_ai_0 = ai_0;
n_bi_0 = {bi_0[24],~bi_0[23:0]};
end
endcase
end
always @* n_mfl_0 = n_ai_0 + n_bi_0;
always @* // Calculate the sign bit.
begin
casex({ai_0[24],bi_0[24],n_mfl_0[24]})
3'b00x:sfl_0 = 1'b0;
3'b11x:sfl_0 = 1'b1;
3'b100:sfl_0 = 1'b0;
3'b101:sfl_0 = 1'b1;
3'b010:sfl_0 = 1'b0;
3'b011:sfl_0 = 1'b1;
endcase
end
always @* // Calculate the end result.
begin
casex({ai_0[24],bi_0[24],n_mfl_0[24]})
3'b00x:nn_mfl_0 = n_mfl_0[24:0];
3'b11x:nn_mfl_0 = n_mfl_0[24:0];
3'b100:begin
nn_mfl_0[23:0] = n_mfl_0[23:0]+24'h1;
nn_mfl_0[24] = 1'b0;
end
3'b101:begin
nn_mfl_0[23:0] = ~n_mfl_0[23:0];
nn_mfl_0[24] = 1'b0;
end
3'b010:begin
nn_mfl_0[23:0] = n_mfl_0[23:0]+24'h1;
nn_mfl_0[24] = 1'b0;
end
3'b011:begin
nn_mfl_0[23:0] = ~n_mfl_0[23:0];
nn_mfl_0[24] = 1'b0;
end
endcase
end
always @(posedge clk)
begin
sub_1 <= sub_0;
sfl_1 <= sfl_0;
afl_eqz_1 <= afl_eqz_0;
bfl_eqz_1 <= bfl_eqz_0;
afl_eq_bfl_1 <= afl_eq_bfl_0;
aefl_1 <= aefl_0;
afl_1 <= afl_0;
bfl_1 <= bfl_0;
nn_mfl_1 <= nn_mfl_0;
nom_shft_1 <=0;
casex(nn_mfl_0) /* synopsys parallel_case */
25'b1xxxxxxxxxxxxxxxxxxxxxxxx: nom_shft_1 <=24;
25'b01xxxxxxxxxxxxxxxxxxxxxxx: nom_shft_1 <=0;
25'b001xxxxxxxxxxxxxxxxxxxxxx: nom_shft_1 <=1;
25'b0001xxxxxxxxxxxxxxxxxxxxx: nom_shft_1 <=2;
25'b00001xxxxxxxxxxxxxxxxxxxx: nom_shft_1 <=3;
25'b000001xxxxxxxxxxxxxxxxxxx: nom_shft_1 <=4;
25'b0000001xxxxxxxxxxxxxxxxxx: nom_shft_1 <=5;
25'b00000001xxxxxxxxxxxxxxxxx: nom_shft_1 <=6;
25'b000000001xxxxxxxxxxxxxxxx: nom_shft_1 <=7;
25'b0000000001xxxxxxxxxxxxxxx: nom_shft_1 <=8;
25'b00000000001xxxxxxxxxxxxxx: nom_shft_1 <=9;
25'b000000000001xxxxxxxxxxxxx: nom_shft_1 <=10;
25'b0000000000001xxxxxxxxxxxx: nom_shft_1 <=11;
25'b00000000000001xxxxxxxxxxx: nom_shft_1 <=12;
25'b000000000000001xxxxxxxxxx: nom_shft_1 <=13;
25'b0000000000000001xxxxxxxxx: nom_shft_1 <=14;
25'b00000000000000001xxxxxxxx: nom_shft_1 <=15;
25'b000000000000000001xxxxxxx: nom_shft_1 <=16;
25'b0000000000000000001xxxxxx: nom_shft_1 <=17;
25'b00000000000000000001xxxxx: nom_shft_1 <=18;
25'b000000000000000000001xxxx: nom_shft_1 <=19;
25'b0000000000000000000001xxx: nom_shft_1 <=20;
25'b00000000000000000000001xx: nom_shft_1 <=21;
25'b000000000000000000000001x: nom_shft_1 <=22;
25'b0000000000000000000000001: nom_shft_1 <=23;
default: nom_shft_1 <=0;
endcase
end
always @(nn_mfl_1 or nom_shft_1)
begin
if(nom_shft_1[4] & nom_shft_1[3])nmfl_1 = nn_mfl_1 >> 1;
else nmfl_1 = nn_mfl_1 << nom_shft_1;
end
always @* // Calculate the sign bit.
begin
if(nom_shft_1[4] & nom_shft_1[3])n_efl_1 = aefl_1+8'h1;
else n_efl_1 = aefl_1 - nom_shft_1;
end
// Final Answer.
always @(posedge clk)
begin
casex({sub_1, afl_eqz_1, bfl_eqz_1, afl_eq_bfl_1})
4'b0000: fl <= {sfl_1,n_efl_1,nmfl_1[22:0]}; // Normal Add, afl + bfl.
4'b0010: fl <= afl_1; // Add, (afl != 0), (bfl = 0), fl = afl;
4'b0100: fl <= bfl_1; // Add, (afl = 0), (bfl != 0), fl = bfl;
4'b011x: fl <= 0; // Add, (afl = 0), (bfl = 0), fl = 0;
4'b1xx1: fl <= 0; // afl = bfl, subtract, fl = 0;
4'b1xx0: fl <= {sfl_1,n_efl_1,nmfl_1[22:0]}; // Normal Subtract.
endcase
end
endmodule |
module main (
output ve5dac7,
output v22cf82,
output v2120a4
);
wire w0;
wire w1;
wire w2;
assign ve5dac7 = w0;
assign v22cf82 = w1;
assign v2120a4 = w2;
vfebcfe v7dc4a3 (
.v9fb85f(w1)
);
vfebcfe va834d8 (
.v9fb85f(w0)
);
vd30ca9 v9ceafe (
.v9fb85f(w2)
);
endmodule |
module vfebcfe (
output v9fb85f
);
wire w0;
assign v9fb85f = w0;
vfebcfe_vb2eccd vb2eccd (
.q(w0)
);
endmodule |
module vfebcfe_vb2eccd (
output q
);
//-- Constant bit-1
assign q = 1'b1;
endmodule |
module vd30ca9 (
output v9fb85f
);
wire w0;
assign v9fb85f = w0;
vd30ca9_vb2eccd vb2eccd (
.q(w0)
);
endmodule |
module vd30ca9_vb2eccd (
output q
);
//-- Constant bit-0
assign q = 1'b0;
endmodule |
module uart_tx
(
input wire clk,
input wire reset,
input wire tx_start,
input wire s_tick,
input wire [7:0] din,
output reg tx_done_tick,
output wire tx
);
parameter DBIT = 8;
parameter SB_TICK = 16;
localparam IDLE = 0;
localparam START = 1;
localparam DATA = 2;
localparam STOP = 3;
reg [1:0] state_reg, state_next;
reg [3:0] s_reg, s_next;
reg [2:0] n_reg, n_next;
reg [7:0] b_reg, b_next;
reg tx_reg, tx_next;
always @ (posedge clk, posedge reset) begin
if (reset) begin
state_reg <= IDLE;
s_reg <= 0;
n_reg <= 0;
b_reg <= 0;
tx_reg <= 1;
end
else begin
state_reg <= state_next;
s_reg <= s_next;
n_reg <= n_next;
b_reg <= b_next;
tx_reg <= tx_next;
end
end
// state machine works as follows:
// if it is in idle mode, it waits for a start
// signal to begin, otherwise it continues to send 0s to UART (meaning there is nothing available yet)
// then it goes into start mode once some data has been inputted, it does the write
// starting at START for 8 bits before moving back to idle
always @ (state_reg, s_reg, n_reg, b_reg, s_tick, tx_reg, tx_start, din) begin
state_next <= state_reg;
s_next <= s_reg;
n_next <= n_reg;
b_next <= b_reg;
tx_next <= tx_reg;
tx_done_tick <= 0;
case (state_reg)
IDLE: begin
tx_next <= 1;
if (tx_start) begin
state_next <= START;
s_next <= 0;
b_next <= din;
end
end
START: begin
tx_next <= 0;
if (s_tick) begin
if (s_reg == 15) begin
state_next <= DATA;
s_next <= 0;
n_next <= 0;
end
else
s_next <= s_reg + 1;
end
end
DATA: begin
tx_next <= b_reg[0];
if (s_tick) begin
if (s_reg == 15) begin
s_next <= 0;
b_next <= {1'b0, b_reg[7:1]};
if (n_reg == DBIT-1)
state_next <= STOP;
else
n_next <= n_reg + 1;
end
else
s_next <= s_reg + 1;
end
end
STOP: begin
tx_next <= 1;
if (s_tick) begin
if (s_reg == SB_TICK-1) begin
state_next <= IDLE;
tx_done_tick <= 1;
end
else
s_next <= s_reg + 1;
end
end
endcase
end
assign tx = tx_reg;
endmodule |
module sky130_fd_sc_hs__dfxbp (
//# {{data|Data Signals}}
input D ,
output Q ,
output Q_N ,
//# {{clocks|Clocking}}
input CLK ,
//# {{power|Power}}
input VPWR,
input VGND
);
endmodule |
module Computer_ControlUnit_InstructionMemory(
output reg [WORD_WIDTH-1:0] INSTR_out,
input [WORD_WIDTH-1:0] COUNTER_in
);
parameter WORD_WIDTH = 16;
parameter DR_WIDTH = 3;
parameter SB_WIDTH = DR_WIDTH;
parameter SA_WIDTH = DR_WIDTH;
parameter OPCODE_WIDTH = 7;
parameter CNTRL_WIDTH = DR_WIDTH+SB_WIDTH+SA_WIDTH+11;
parameter COUNTER_WIDTH = 4;
always@(COUNTER_in)
begin
case(COUNTER_in)
//16'h0000: INSTR_out = 16'b000_0000_000_000_000; //
16'h0000: INSTR_out = 16'b100_1100_000_000_011; // LDI R0 <- 3
16'h0001: INSTR_out = 16'b100_1100_001_000_111; // LDI R1 <- 7
16'h0002: INSTR_out = 16'b000_0000_010_000_XXX; // MOVA R2 <- R0
16'h0003: INSTR_out = 16'b000_1100_011_XXX_001; // MOVB R3 <- R1
16'h0004: INSTR_out = 16'b000_0010_100_000_001; // ADD R4 <- R0;R1
16'h0005: INSTR_out = 16'b000_0101_101_011_100; // SUB R5 <- R3;R4
16'h0006: INSTR_out = 16'b110_0000_000_101_011; // BRZ R5;3
16'h0007: INSTR_out = 16'b110_0001_000_101_011; // BRN R5;3
16'h000A: INSTR_out = 16'b111_0000_110_000_001; // JMP R0;
default: INSTR_out = 16'b0;
endcase
end
endmodule |
module stratixv_dffe ( Q, CLK, ENA, D, CLRN, PRN );
input D;
input CLK;
input CLRN;
input PRN;
input ENA;
output Q;
wire D_ipd;
wire ENA_ipd;
wire CLK_ipd;
wire PRN_ipd;
wire CLRN_ipd;
buf (D_ipd, D);
buf (ENA_ipd, ENA);
buf (CLK_ipd, CLK);
buf (PRN_ipd, PRN);
buf (CLRN_ipd, CLRN);
wire legal;
reg viol_notifier;
STRATIXV_PRIM_DFFE ( Q, ENA_ipd, D_ipd, CLK_ipd, CLRN_ipd, PRN_ipd, viol_notifier );
and(legal, ENA_ipd, CLRN_ipd, PRN_ipd);
specify
specparam TREG = 0;
specparam TREN = 0;
specparam TRSU = 0;
specparam TRH = 0;
specparam TRPR = 0;
specparam TRCL = 0;
$setup ( D, posedge CLK &&& legal, TRSU, viol_notifier ) ;
$hold ( posedge CLK &&& legal, D, TRH, viol_notifier ) ;
$setup ( ENA, posedge CLK &&& legal, TREN, viol_notifier ) ;
$hold ( posedge CLK &&& legal, ENA, 0, viol_notifier ) ;
( negedge CLRN => (Q +: 1'b0)) = ( TRCL, TRCL) ;
( negedge PRN => (Q +: 1'b1)) = ( TRPR, TRPR) ;
( posedge CLK => (Q +: D)) = ( TREG, TREG) ;
endspecify
endmodule |
module stratixv_mux21 (MO, A, B, S);
input A, B, S;
output MO;
wire A_in;
wire B_in;
wire S_in;
buf(A_in, A);
buf(B_in, B);
buf(S_in, S);
wire tmp_MO;
specify
(A => MO) = (0, 0);
(B => MO) = (0, 0);
(S => MO) = (0, 0);
endspecify
assign tmp_MO = (S_in == 1) ? B_in : A_in;
buf (MO, tmp_MO);
endmodule |
module stratixv_mux41 (MO, IN0, IN1, IN2, IN3, S);
input IN0;
input IN1;
input IN2;
input IN3;
input [1:0] S;
output MO;
wire IN0_in;
wire IN1_in;
wire IN2_in;
wire IN3_in;
wire S1_in;
wire S0_in;
buf(IN0_in, IN0);
buf(IN1_in, IN1);
buf(IN2_in, IN2);
buf(IN3_in, IN3);
buf(S1_in, S[1]);
buf(S0_in, S[0]);
wire tmp_MO;
specify
(IN0 => MO) = (0, 0);
(IN1 => MO) = (0, 0);
(IN2 => MO) = (0, 0);
(IN3 => MO) = (0, 0);
(S[1] => MO) = (0, 0);
(S[0] => MO) = (0, 0);
endspecify
assign tmp_MO = S1_in ? (S0_in ? IN3_in : IN2_in) : (S0_in ? IN1_in : IN0_in);
buf (MO, tmp_MO);
endmodule |
module stratixv_and1 (Y, IN1);
input IN1;
output Y;
specify
(IN1 => Y) = (0, 0);
endspecify
buf (Y, IN1);
endmodule |
module stratixv_and16 (Y, IN1);
input [15:0] IN1;
output [15:0] Y;
specify
(IN1 => Y) = (0, 0);
endspecify
buf (Y[0], IN1[0]);
buf (Y[1], IN1[1]);
buf (Y[2], IN1[2]);
buf (Y[3], IN1[3]);
buf (Y[4], IN1[4]);
buf (Y[5], IN1[5]);
buf (Y[6], IN1[6]);
buf (Y[7], IN1[7]);
buf (Y[8], IN1[8]);
buf (Y[9], IN1[9]);
buf (Y[10], IN1[10]);
buf (Y[11], IN1[11]);
buf (Y[12], IN1[12]);
buf (Y[13], IN1[13]);
buf (Y[14], IN1[14]);
buf (Y[15], IN1[15]);
endmodule |
module stratixv_bmux21 (MO, A, B, S);
input [15:0] A, B;
input S;
output [15:0] MO;
assign MO = (S == 1) ? B : A;
endmodule |
module stratixv_b17mux21 (MO, A, B, S);
input [16:0] A, B;
input S;
output [16:0] MO;
assign MO = (S == 1) ? B : A;
endmodule |
module stratixv_nmux21 (MO, A, B, S);
input A, B, S;
output MO;
assign MO = (S == 1) ? ~B : ~A;
endmodule |
module stratixv_b5mux21 (MO, A, B, S);
input [4:0] A, B;
input S;
output [4:0] MO;
assign MO = (S == 1) ? B : A;
endmodule |
module stratixv_ff (
d,
clk,
clrn,
aload,
sclr,
sload,
asdata,
ena,
devclrn,
devpor,
q
);
parameter power_up = "low";
parameter x_on_violation = "on";
parameter lpm_type = "stratixv_ff";
input d;
input clk;
input clrn;
input aload;
input sclr;
input sload;
input asdata;
input ena;
input devclrn;
input devpor;
output q;
tri1 devclrn;
tri1 devpor;
reg q_tmp;
wire reset;
reg d_viol;
reg sclr_viol;
reg sload_viol;
reg asdata_viol;
reg ena_viol;
reg violation;
reg clk_last_value;
reg ix_on_violation;
wire d_in;
wire clk_in;
wire clrn_in;
wire aload_in;
wire sclr_in;
wire sload_in;
wire asdata_in;
wire ena_in;
wire nosloadsclr;
wire sloaddata;
buf (d_in, d);
buf (clk_in, clk);
buf (clrn_in, clrn);
buf (aload_in, aload);
buf (sclr_in, sclr);
buf (sload_in, sload);
buf (asdata_in, asdata);
buf (ena_in, ena);
assign reset = devpor && devclrn && clrn_in && ena_in;
assign nosloadsclr = reset && (!sload_in && !sclr_in);
assign sloaddata = reset && sload_in;
specify
$setuphold (posedge clk &&& nosloadsclr, d, 0, 0, d_viol) ;
$setuphold (posedge clk &&& reset, sclr, 0, 0, sclr_viol) ;
$setuphold (posedge clk &&& reset, sload, 0, 0, sload_viol) ;
$setuphold (posedge clk &&& sloaddata, asdata, 0, 0, asdata_viol) ;
$setuphold (posedge clk &&& reset, ena, 0, 0, ena_viol) ;
(posedge clk => (q +: q_tmp)) = 0 ;
(posedge clrn => (q +: 1'b0)) = (0, 0) ;
(posedge aload => (q +: q_tmp)) = (0, 0) ;
(asdata => q) = (0, 0) ;
endspecify
initial
begin
violation = 'b0;
clk_last_value = 'b0;
if (power_up == "low")
q_tmp = 'b0;
else if (power_up == "high")
q_tmp = 'b1;
if (x_on_violation == "on")
ix_on_violation = 1;
else
ix_on_violation = 0;
end
always @ (d_viol or sclr_viol or sload_viol or ena_viol or asdata_viol)
begin
if (ix_on_violation == 1)
violation = 'b1;
end
always @ (asdata_in or clrn_in or posedge aload_in or
devclrn or devpor)
begin
if (devpor == 'b0)
q_tmp <= 'b0;
else if (devclrn == 'b0)
q_tmp <= 'b0;
else if (clrn_in == 'b0)
q_tmp <= 'b0;
else if (aload_in == 'b1)
q_tmp <= asdata_in;
end
always @ (clk_in or posedge clrn_in or posedge aload_in or
devclrn or devpor or posedge violation)
begin
if (violation == 1'b1)
begin
violation = 'b0;
q_tmp <= 'bX;
end
else
begin
if (devpor == 'b0 || devclrn == 'b0 || clrn_in === 'b0)
q_tmp <= 'b0;
else if (aload_in === 'b1)
q_tmp <= asdata_in;
else if (ena_in === 'b1 && clk_in === 'b1 && clk_last_value === 'b0)
begin
if (sclr_in === 'b1)
q_tmp <= 'b0 ;
else if (sload_in === 'b1)
q_tmp <= asdata_in;
else
q_tmp <= d_in;
end
end
clk_last_value = clk_in;
end
and (q, q_tmp, 1'b1);
endmodule |
module stratixv_lcell_comb (
dataa,
datab,
datac,
datad,
datae,
dataf,
datag,
cin,
sharein,
combout,
sumout,
cout,
shareout
);
input dataa;
input datab;
input datac;
input datad;
input datae;
input dataf;
input datag;
input cin;
input sharein;
output combout;
output sumout;
output cout;
output shareout;
parameter lut_mask = 64'hFFFFFFFFFFFFFFFF;
parameter shared_arith = "off";
parameter extended_lut = "off";
parameter dont_touch = "off";
parameter lpm_type = "stratixv_lcell_comb";
// sub masks
wire [15:0] f0_mask;
wire [15:0] f1_mask;
wire [15:0] f2_mask;
wire [15:0] f3_mask;
// sub lut outputs
reg f0_out;
reg f1_out;
reg f2_out;
reg f3_out;
// mux output for extended mode
reg g0_out;
reg g1_out;
// either datac or datag
reg f2_input3;
// F2 output using dataf
reg f2_f;
// second input to the adder
reg adder_input2;
// tmp output variables
reg combout_tmp;
reg sumout_tmp;
reg cout_tmp;
// integer representations for string parameters
reg ishared_arith;
reg iextended_lut;
// 4-input LUT function
function lut4;
input [15:0] mask;
input dataa;
input datab;
input datac;
input datad;
begin
lut4 = datad ? ( datac ? ( datab ? ( dataa ? mask[15] : mask[14])
: ( dataa ? mask[13] : mask[12]))
: ( datab ? ( dataa ? mask[11] : mask[10])
: ( dataa ? mask[ 9] : mask[ 8])))
: ( datac ? ( datab ? ( dataa ? mask[ 7] : mask[ 6])
: ( dataa ? mask[ 5] : mask[ 4]))
: ( datab ? ( dataa ? mask[ 3] : mask[ 2])
: ( dataa ? mask[ 1] : mask[ 0])));
end
endfunction
// 5-input LUT function
function lut5;
input [31:0] mask;
input dataa;
input datab;
input datac;
input datad;
input datae;
reg e0_lut;
reg e1_lut;
reg [15:0] e0_mask;
reg [31:16] e1_mask;
begin
e0_mask = mask[15:0];
e1_mask = mask[31:16];
begin
e0_lut = lut4(e0_mask, dataa, datab, datac, datad);
e1_lut = lut4(e1_mask, dataa, datab, datac, datad);
if (datae === 1'bX) // X propogation
begin
if (e0_lut == e1_lut)
begin
lut5 = e0_lut;
end
else
begin
lut5 = 1'bX;
end
end
else
begin
lut5 = (datae == 1'b1) ? e1_lut : e0_lut;
end
end
end
endfunction
// 6-input LUT function
function lut6;
input [63:0] mask;
input dataa;
input datab;
input datac;
input datad;
input datae;
input dataf;
reg f0_lut;
reg f1_lut;
reg [31:0] f0_mask;
reg [63:32] f1_mask ;
begin
f0_mask = mask[31:0];
f1_mask = mask[63:32];
begin
lut6 = mask[{dataf, datae, datad, datac, datab, dataa}];
if (lut6 === 1'bX)
begin
f0_lut = lut5(f0_mask, dataa, datab, datac, datad, datae);
f1_lut = lut5(f1_mask, dataa, datab, datac, datad, datae);
if (dataf === 1'bX) // X propogation
begin
if (f0_lut == f1_lut)
begin
lut6 = f0_lut;
end
else
begin
lut6 = 1'bX;
end
end
else
begin
lut6 = (dataf == 1'b1) ? f1_lut : f0_lut;
end
end
end
end
endfunction
wire dataa_in;
wire datab_in;
wire datac_in;
wire datad_in;
wire datae_in;
wire dataf_in;
wire datag_in;
wire cin_in;
wire sharein_in;
buf(dataa_in, dataa);
buf(datab_in, datab);
buf(datac_in, datac);
buf(datad_in, datad);
buf(datae_in, datae);
buf(dataf_in, dataf);
buf(datag_in, datag);
buf(cin_in, cin);
buf(sharein_in, sharein);
specify
(dataa => combout) = (0, 0);
(datab => combout) = (0, 0);
(datac => combout) = (0, 0);
(datad => combout) = (0, 0);
(datae => combout) = (0, 0);
(dataf => combout) = (0, 0);
(datag => combout) = (0, 0);
(dataa => sumout) = (0, 0);
(datab => sumout) = (0, 0);
(datac => sumout) = (0, 0);
(datad => sumout) = (0, 0);
(dataf => sumout) = (0, 0);
(cin => sumout) = (0, 0);
(sharein => sumout) = (0, 0);
(dataa => cout) = (0, 0);
(datab => cout) = (0, 0);
(datac => cout) = (0, 0);
(datad => cout) = (0, 0);
(dataf => cout) = (0, 0);
(cin => cout) = (0, 0);
(sharein => cout) = (0, 0);
(dataa => shareout) = (0, 0);
(datab => shareout) = (0, 0);
(datac => shareout) = (0, 0);
(datad => shareout) = (0, 0);
endspecify
initial
begin
if (shared_arith == "on")
ishared_arith = 1;
else
ishared_arith = 0;
if (extended_lut == "on")
iextended_lut = 1;
else
iextended_lut = 0;
f0_out = 1'b0;
f1_out = 1'b0;
f2_out = 1'b0;
f3_out = 1'b0;
g0_out = 1'b0;
g1_out = 1'b0;
f2_input3 = 1'b0;
adder_input2 = 1'b0;
f2_f = 1'b0;
combout_tmp = 1'b0;
sumout_tmp = 1'b0;
cout_tmp = 1'b0;
end
// sub masks and outputs
assign f0_mask = lut_mask[15:0];
assign f1_mask = lut_mask[31:16];
assign f2_mask = lut_mask[47:32];
assign f3_mask = lut_mask[63:48];
always @(datag_in or dataf_in or datae_in or datad_in or datac_in or
datab_in or dataa_in or cin_in or sharein_in)
begin
// check for extended LUT mode
if (iextended_lut == 1)
f2_input3 = datag_in;
else
f2_input3 = datac_in;
f0_out = lut4(f0_mask, dataa_in, datab_in, datac_in, datad_in);
f1_out = lut4(f1_mask, dataa_in, datab_in, f2_input3, datad_in);
f2_out = lut4(f2_mask, dataa_in, datab_in, datac_in, datad_in);
f3_out = lut4(f3_mask, dataa_in, datab_in, f2_input3, datad_in);
// combout is the 6-input LUT
if (iextended_lut == 1)
begin
if (datae_in == 1'b0)
begin
g0_out = f0_out;
g1_out = f2_out;
end
else if (datae_in == 1'b1)
begin
g0_out = f1_out;
g1_out = f3_out;
end
else
begin
if (f0_out == f1_out)
g0_out = f0_out;
else
g0_out = 1'bX;
if (f2_out == f3_out)
g1_out = f2_out;
else
g1_out = 1'bX;
end
if (dataf_in == 1'b0)
combout_tmp = g0_out;
else if ((dataf_in == 1'b1) || (g0_out == g1_out))
combout_tmp = g1_out;
else
combout_tmp = 1'bX;
end
else
combout_tmp = lut6(lut_mask, dataa_in, datab_in, datac_in,
datad_in, datae_in, dataf_in);
// check for shareed arithmetic mode
if (ishared_arith == 1)
adder_input2 = sharein_in;
else
begin
f2_f = lut4(f2_mask, dataa_in, datab_in, datac_in, dataf_in);
adder_input2 = !f2_f;
end
// sumout & cout
sumout_tmp = cin_in ^ f0_out ^ adder_input2;
cout_tmp = (cin_in & f0_out) | (cin_in & adder_input2) |
(f0_out & adder_input2);
end
and (combout, combout_tmp, 1'b1);
and (sumout, sumout_tmp, 1'b1);
and (cout, cout_tmp, 1'b1);
and (shareout, f2_out, 1'b1);
endmodule |
module stratixv_routing_wire (
datain,
dataout
);
// INPUT PORTS
input datain;
// OUTPUT PORTS
output dataout;
// INTERNAL VARIABLES
wire dataout_tmp;
specify
(datain => dataout) = (0, 0) ;
endspecify
assign dataout_tmp = datain;
and (dataout, dataout_tmp, 1'b1);
endmodule |
module stratixv_ram_block
(
portadatain,
portaaddr,
portawe,
portare,
portbdatain,
portbaddr,
portbwe,
portbre,
clk0, clk1,
ena0, ena1,
ena2, ena3,
clr0, clr1,
nerror,
portabyteenamasks,
portbbyteenamasks,
portaaddrstall,
portbaddrstall,
devclrn,
devpor,
eccstatus,
portadataout,
portbdataout
,dftout
);
// -------- GLOBAL PARAMETERS ---------
parameter operation_mode = "single_port";
parameter mixed_port_feed_through_mode = "dont_care";
parameter ram_block_type = "auto";
parameter logical_ram_name = "ram_name";
parameter init_file = "init_file.hex";
parameter init_file_layout = "none";
parameter ecc_pipeline_stage_enabled = "false";
parameter enable_ecc = "false";
parameter width_eccstatus = 2;
parameter data_interleave_width_in_bits = 1;
parameter data_interleave_offset_in_bits = 1;
parameter port_a_logical_ram_depth = 0;
parameter port_a_logical_ram_width = 0;
parameter port_a_first_address = 0;
parameter port_a_last_address = 0;
parameter port_a_first_bit_number = 0;
parameter port_a_data_out_clear = "none";
parameter port_a_data_out_clock = "none";
parameter port_a_data_width = 1;
parameter port_a_address_width = 1;
parameter port_a_byte_enable_mask_width = 1;
parameter port_b_logical_ram_depth = 0;
parameter port_b_logical_ram_width = 0;
parameter port_b_first_address = 0;
parameter port_b_last_address = 0;
parameter port_b_first_bit_number = 0;
parameter port_b_address_clear = "none";
parameter port_b_data_out_clear = "none";
parameter port_b_data_in_clock = "clock1";
parameter port_b_address_clock = "clock1";
parameter port_b_write_enable_clock = "clock1";
parameter port_b_read_enable_clock = "clock1";
parameter port_b_byte_enable_clock = "clock1";
parameter port_b_data_out_clock = "none";
parameter port_b_data_width = 1;
parameter port_b_address_width = 1;
parameter port_b_byte_enable_mask_width = 1;
parameter port_a_read_during_write_mode = "new_data_no_nbe_read";
parameter port_b_read_during_write_mode = "new_data_no_nbe_read";
parameter power_up_uninitialized = "false";
parameter lpm_type = "stratixv_ram_block";
parameter lpm_hint = "true";
parameter connectivity_checking = "off";
parameter mem_init0 = "";
parameter mem_init1 = "";
parameter mem_init2 = "";
parameter mem_init3 = "";
parameter mem_init4 = "";
parameter mem_init5 = "";
parameter mem_init6 = "";
parameter mem_init7 = "";
parameter mem_init8 = "";
parameter mem_init9 = "";
parameter port_a_byte_size = 0;
parameter port_b_byte_size = 0;
parameter clk0_input_clock_enable = "none"; // ena0,ena2,none
parameter clk0_core_clock_enable = "none"; // ena0,ena2,none
parameter clk0_output_clock_enable = "none"; // ena0,none
parameter clk1_input_clock_enable = "none"; // ena1,ena3,none
parameter clk1_core_clock_enable = "none"; // ena1,ena3,none
parameter clk1_output_clock_enable = "none"; // ena1,none
parameter bist_ena = "false"; //false, true
// SIMULATION_ONLY_PARAMETERS_BEGIN
parameter port_a_address_clear = "none";
parameter port_a_data_in_clock = "clock0";
parameter port_a_address_clock = "clock0";
parameter port_a_write_enable_clock = "clock0";
parameter port_a_byte_enable_clock = "clock0";
parameter port_a_read_enable_clock = "clock0";
// SIMULATION_ONLY_PARAMETERS_END
// -------- PORT DECLARATIONS ---------
input portawe;
input portare;
input [port_a_data_width - 1:0] portadatain;
input [port_a_address_width - 1:0] portaaddr;
input [port_a_byte_enable_mask_width - 1:0] portabyteenamasks;
input portbwe, portbre;
input [port_b_data_width - 1:0] portbdatain;
input [port_b_address_width - 1:0] portbaddr;
input [port_b_byte_enable_mask_width - 1:0] portbbyteenamasks;
input clr0,clr1;
input clk0,clk1;
input ena0,ena1;
input ena2,ena3;
input nerror;
input devclrn,devpor;
input portaaddrstall;
input portbaddrstall;
output [port_a_data_width - 1:0] portadataout;
output [port_b_data_width - 1:0] portbdataout;
output [width_eccstatus - 1:0] eccstatus;
output [8:0] dftout;
// -------- RAM BLOCK INSTANTIATION ---
generic_m20k ram_core0
(
.portawe(portawe),
.portare(portare),
.portadatain(portadatain),
.portaaddr(portaaddr),
.portabyteenamasks(portabyteenamasks),
.portbwe(portbwe),
.portbre(portbre),
.portbdatain(portbdatain),
.portbaddr(portbaddr),
.portbbyteenamasks(portbbyteenamasks),
.clr0(clr0),
.clr1(clr1),
.clk0(clk0),
.clk1(clk1),
.ena0(ena0),
.ena1(ena1),
.ena2(ena2),
.ena3(ena3),
.nerror(nerror),
.devclrn(devclrn),
.devpor(devpor),
.portaaddrstall(portaaddrstall),
.portbaddrstall(portbaddrstall),
.portadataout(portadataout),
.portbdataout(portbdataout),
.eccstatus(eccstatus),
.dftout(dftout)
);
defparam ram_core0.operation_mode = operation_mode;
defparam ram_core0.mixed_port_feed_through_mode = mixed_port_feed_through_mode;
defparam ram_core0.ram_block_type = ram_block_type;
defparam ram_core0.logical_ram_name = logical_ram_name;
defparam ram_core0.init_file = init_file;
defparam ram_core0.init_file_layout = init_file_layout;
defparam ram_core0.ecc_pipeline_stage_enabled = ecc_pipeline_stage_enabled;
defparam ram_core0.enable_ecc = enable_ecc;
defparam ram_core0.width_eccstatus = width_eccstatus;
defparam ram_core0.data_interleave_width_in_bits = data_interleave_width_in_bits;
defparam ram_core0.data_interleave_offset_in_bits = data_interleave_offset_in_bits;
defparam ram_core0.port_a_logical_ram_depth = port_a_logical_ram_depth;
defparam ram_core0.port_a_logical_ram_width = port_a_logical_ram_width;
defparam ram_core0.port_a_first_address = port_a_first_address;
defparam ram_core0.port_a_last_address = port_a_last_address;
defparam ram_core0.port_a_first_bit_number = port_a_first_bit_number;
defparam ram_core0.port_a_data_out_clear = port_a_data_out_clear;
defparam ram_core0.port_a_data_out_clock = port_a_data_out_clock;
defparam ram_core0.port_a_data_width = port_a_data_width;
defparam ram_core0.port_a_address_width = port_a_address_width;
defparam ram_core0.port_a_byte_enable_mask_width = port_a_byte_enable_mask_width;
defparam ram_core0.port_b_logical_ram_depth = port_b_logical_ram_depth;
defparam ram_core0.port_b_logical_ram_width = port_b_logical_ram_width;
defparam ram_core0.port_b_first_address = port_b_first_address;
defparam ram_core0.port_b_last_address = port_b_last_address;
defparam ram_core0.port_b_first_bit_number = port_b_first_bit_number;
defparam ram_core0.port_b_address_clear = port_b_address_clear;
defparam ram_core0.port_b_data_out_clear = port_b_data_out_clear;
defparam ram_core0.port_b_data_in_clock = port_b_data_in_clock;
defparam ram_core0.port_b_address_clock = port_b_address_clock;
defparam ram_core0.port_b_write_enable_clock = port_b_write_enable_clock;
defparam ram_core0.port_b_read_enable_clock = port_b_read_enable_clock;
defparam ram_core0.port_b_byte_enable_clock = port_b_byte_enable_clock;
defparam ram_core0.port_b_data_out_clock = port_b_data_out_clock;
defparam ram_core0.port_b_data_width = port_b_data_width;
defparam ram_core0.port_b_address_width = port_b_address_width;
defparam ram_core0.port_b_byte_enable_mask_width = port_b_byte_enable_mask_width;
defparam ram_core0.port_a_read_during_write_mode = port_a_read_during_write_mode;
defparam ram_core0.port_b_read_during_write_mode = port_b_read_during_write_mode;
defparam ram_core0.power_up_uninitialized = power_up_uninitialized;
defparam ram_core0.lpm_type = lpm_type;
defparam ram_core0.lpm_hint = lpm_hint;
defparam ram_core0.connectivity_checking = connectivity_checking;
defparam ram_core0.mem_init0 = mem_init0;
defparam ram_core0.mem_init1 = mem_init1;
defparam ram_core0.mem_init2 = mem_init2;
defparam ram_core0.mem_init3 = mem_init3;
defparam ram_core0.mem_init4 = mem_init4;
defparam ram_core0.mem_init5 = mem_init5;
defparam ram_core0.mem_init6 = mem_init6;
defparam ram_core0.mem_init7 = mem_init7;
defparam ram_core0.mem_init8 = mem_init8;
defparam ram_core0.mem_init9 = mem_init9;
defparam ram_core0.port_a_byte_size = port_a_byte_size;
defparam ram_core0.port_b_byte_size = port_b_byte_size;
defparam ram_core0.clk0_input_clock_enable = clk0_input_clock_enable;
defparam ram_core0.clk0_core_clock_enable = clk0_core_clock_enable ;
defparam ram_core0.clk0_output_clock_enable = clk0_output_clock_enable;
defparam ram_core0.clk1_input_clock_enable = clk1_input_clock_enable;
defparam ram_core0.clk1_core_clock_enable = clk1_core_clock_enable;
defparam ram_core0.clk1_output_clock_enable = clk1_output_clock_enable;
defparam ram_core0.bist_ena = bist_ena;
defparam ram_core0.port_a_address_clear = port_a_address_clear;
defparam ram_core0.port_a_data_in_clock = port_a_data_in_clock;
defparam ram_core0.port_a_address_clock = port_a_address_clock;
defparam ram_core0.port_a_write_enable_clock = port_a_write_enable_clock;
defparam ram_core0.port_a_byte_enable_clock = port_a_byte_enable_clock;
defparam ram_core0.port_a_read_enable_clock = port_a_read_enable_clock;
endmodule |
module stratixv_mlab_cell
(
portadatain,
portaaddr,
portabyteenamasks,
portbaddr,
clk0, clk1,
ena0, ena1,
ena2,
clr,
devclrn,
devpor,
portbdataout
);
// -------- GLOBAL PARAMETERS ---------
parameter logical_ram_name = "lutram";
parameter logical_ram_depth = 0;
parameter logical_ram_width = 0;
parameter first_address = 0;
parameter last_address = 0;
parameter first_bit_number = 0;
parameter mixed_port_feed_through_mode = "new";
parameter init_file = "NONE";
parameter data_width = 20;
parameter address_width = 6;
parameter byte_enable_mask_width = 1;
parameter byte_size = 1;
parameter port_b_data_out_clock = "none";
parameter port_b_data_out_clear = "none";
parameter lpm_type = "stratixv_mlab_cell";
parameter lpm_hint = "true";
parameter mem_init0 = "";
// -------- PORT DECLARATIONS ---------
input [data_width - 1:0] portadatain;
input [address_width - 1:0] portaaddr;
input [byte_enable_mask_width - 1:0] portabyteenamasks;
input [address_width - 1:0] portbaddr;
input clk0;
input clk1;
input ena0;
input ena1;
input ena2;
input clr;
input devclrn;
input devpor;
output [data_width - 1:0] portbdataout;
generic_mlab_cell my_lutram0
(
.portadatain(portadatain),
.portaaddr(portaaddr),
.portabyteenamasks(portabyteenamasks),
.portbaddr(portbaddr),
.clk0(clk0),
.clk1(clk1),
.ena0(ena0),
.ena1(ena1),
.ena2(ena2),
.clr(clr),
.devclrn(devclrn),
.devpor(devpor),
.portbdataout(portbdataout)
);
defparam my_lutram0.logical_ram_name = logical_ram_name;
defparam my_lutram0.logical_ram_depth = logical_ram_depth;
defparam my_lutram0.logical_ram_width = logical_ram_width;
defparam my_lutram0.first_address = first_address;
defparam my_lutram0.last_address = last_address;
defparam my_lutram0.first_bit_number = first_bit_number;
defparam my_lutram0.mixed_port_feed_through_mode = mixed_port_feed_through_mode;
defparam my_lutram0.init_file = init_file;
defparam my_lutram0.data_width = data_width;
defparam my_lutram0.address_width = address_width;
defparam my_lutram0.byte_enable_mask_width = byte_enable_mask_width;
defparam my_lutram0.byte_size = byte_size;
defparam my_lutram0.port_b_data_out_clock = port_b_data_out_clock;
defparam my_lutram0.port_b_data_out_clear = port_b_data_out_clear;
defparam my_lutram0.lpm_type = lpm_type;
defparam my_lutram0.lpm_hint = lpm_hint;
defparam my_lutram0.mem_init0 = mem_init0;
endmodule |
module stratixv_io_ibuf (
i,
ibar,
dynamicterminationcontrol,
o
);
// SIMULATION_ONLY_PARAMETERS_BEGIN
parameter differential_mode = "false";
parameter bus_hold = "false";
parameter simulate_z_as = "Z";
parameter lpm_type = "stratixv_io_ibuf";
// SIMULATION_ONLY_PARAMETERS_END
//Input Ports Declaration
input i;
input ibar;
input dynamicterminationcontrol;
//Output Ports Declaration
output o;
// Internal signals
reg out_tmp;
reg o_tmp;
wire out_val ;
reg prev_value;
specify
(i => o) = (0, 0);
(ibar => o) = (0, 0);
endspecify
initial
begin
prev_value = 1'b0;
end
always@(i or ibar)
begin
if(differential_mode == "false")
begin
if(i == 1'b1)
begin
o_tmp = 1'b1;
prev_value = 1'b1;
end
else if(i == 1'b0)
begin
o_tmp = 1'b0;
prev_value = 1'b0;
end
else if( i === 1'bz)
o_tmp = out_val;
else
o_tmp = i;
if( bus_hold == "true")
out_tmp = prev_value;
else
out_tmp = o_tmp;
end
else
begin
case({i,ibar})
2'b00: out_tmp = 1'bX;
2'b01: out_tmp = 1'b0;
2'b10: out_tmp = 1'b1;
2'b11: out_tmp = 1'bX;
default: out_tmp = 1'bX;
endcase
end
end
assign out_val = (simulate_z_as == "Z") ? 1'bz :
(simulate_z_as == "X") ? 1'bx :
(simulate_z_as == "vcc")? 1'b1 :
(simulate_z_as == "gnd") ? 1'b0 : 1'bz;
pmos (o, out_tmp, 1'b0);
endmodule |
module stratixv_io_obuf (
i,
oe,
dynamicterminationcontrol,
seriesterminationcontrol,
parallelterminationcontrol,
devoe,
o,
obar
);
//Parameter Declaration
parameter open_drain_output = "false";
parameter bus_hold = "false";
parameter shift_series_termination_control = "false";
parameter sim_dynamic_termination_control_is_connected = "false";
parameter lpm_type = "stratixv_io_obuf";
//Input Ports Declaration
input i;
input oe;
input devoe;
input dynamicterminationcontrol;
input [15:0] seriesterminationcontrol;
input [15:0] parallelterminationcontrol;
//Outout Ports Declaration
output o;
output obar;
//INTERNAL Signals
reg out_tmp;
reg out_tmp_bar;
reg prev_value;
wire tmp;
wire tmp_bar;
wire tmp1;
wire tmp1_bar;
tri1 devoe;
specify
(i => o) = (0, 0);
(i => obar) = (0, 0);
(oe => o) = (0, 0);
(oe => obar) = (0, 0);
endspecify
initial
begin
prev_value = 'b0;
out_tmp = 'bz;
end
always@(i or oe)
begin
if(oe == 1'b1)
begin
if(open_drain_output == "true")
begin
if(i == 'b0)
begin
out_tmp = 'b0;
out_tmp_bar = 'b1;
prev_value = 'b0;
end
else
begin
out_tmp = 'bz;
out_tmp_bar = 'bz;
end
end
else
begin
if( i == 'b0)
begin
out_tmp = 'b0;
out_tmp_bar = 'b1;
prev_value = 'b0;
end
else if( i == 'b1)
begin
out_tmp = 'b1;
out_tmp_bar = 'b0;
prev_value = 'b1;
end
else
begin
out_tmp = i;
out_tmp_bar = i;
end
end
end
else if(oe == 1'b0)
begin
out_tmp = 'bz;
out_tmp_bar = 'bz;
end
else
begin
out_tmp = 'bx;
out_tmp_bar = 'bx;
end
end
assign tmp = (bus_hold == "true") ? prev_value : out_tmp;
assign tmp_bar = (bus_hold == "true") ? !prev_value : out_tmp_bar;
assign tmp1 = ((oe == 1'b1) && (dynamicterminationcontrol == 1'b1) && (sim_dynamic_termination_control_is_connected == "true")) ? 1'bx :(devoe == 1'b1) ? tmp : 1'bz;
assign tmp1_bar =((oe == 1'b1) && (dynamicterminationcontrol == 1'b1)&& (sim_dynamic_termination_control_is_connected == "true")) ? 1'bx : (devoe == 1'b1) ? tmp_bar : 1'bz;
pmos (o, tmp1, 1'b0);
pmos (obar, tmp1_bar, 1'b0);
endmodule |
module stratixv_ddio_out (
datainlo,
datainhi,
clk,
clkhi,
clklo,
muxsel,
ena,
areset,
sreset,
dataout,
dfflo,
dffhi,
devpor,
devclrn
);
//Parameters Declaration
parameter power_up = "low";
parameter async_mode = "none";
parameter sync_mode = "none";
parameter half_rate_mode = "false";
parameter use_new_clocking_model = "false";
parameter lpm_type = "stratixv_ddio_out";
//Input Ports Declaration
input datainlo;
input datainhi;
input clk;
input clkhi;
input clklo;
input muxsel;
input ena;
input areset;
input sreset;
input devpor;
input devclrn;
//Output Ports Declaration
output dataout;
//Buried Ports Declaration
output dfflo;
output [1:0] dffhi;
tri1 devclrn;
tri1 devpor;
//Internal Signals
reg ddioreg_aclr;
reg ddioreg_adatasdata;
reg ddioreg_sclr;
reg ddioreg_sload;
reg ddioreg_prn;
reg viol_notifier;
wire dfflo_tmp;
wire dffhi_tmp;
wire mux_sel;
wire dffhi1_tmp;
wire sel_mux_hi_in;
wire clk_hi;
wire clk_lo;
wire datainlo_tmp;
wire datainhi_tmp;
reg dinhi_tmp;
reg dinlo_tmp;
wire clk_hr;
reg clk1;
reg clk2;
reg muxsel1;
reg muxsel2;
reg muxsel_tmp;
reg sel_mux_lo_in_tmp;
wire muxsel3;
wire clk3;
wire sel_mux_lo_in;
initial
begin
ddioreg_aclr = 1'b1;
ddioreg_prn = 1'b1;
ddioreg_adatasdata = (sync_mode == "preset") ? 1'b1: 1'b0;
ddioreg_sclr = 1'b0;
ddioreg_sload = 1'b0;
end
assign dfflo = dfflo_tmp;
assign dffhi[0] = dffhi_tmp;
assign dffhi[1] = dffhi1_tmp;
always@(clk)
begin
clk1 = clk;
clk2 <= clk1;
end
always@(muxsel)
begin
muxsel1 = muxsel;
muxsel2 <= muxsel1;
end
always@(dfflo_tmp)
begin
sel_mux_lo_in_tmp <= dfflo_tmp;
end
always@(datainlo)
begin
dinlo_tmp <= datainlo;
end
always@(datainhi)
begin
dinhi_tmp <= datainhi;
end
always @(mux_sel) begin
if (half_rate_mode == "true")
muxsel_tmp <= mux_sel;
else
muxsel_tmp <= !mux_sel;
end
always@(areset)
begin
if(async_mode == "clear")
begin
ddioreg_aclr = !areset;
end
else if(async_mode == "preset")
begin
ddioreg_prn = !areset;
end
end
always@(sreset )
begin
if(sync_mode == "clear")
begin
ddioreg_sclr = sreset;
end
else if(sync_mode == "preset")
begin
ddioreg_sload = sreset;
end
end
//DDIO HIGH Register
dffeas ddioreg_hi(
.d(datainhi_tmp),
.clk(clk_hi),
.clrn(ddioreg_aclr),
.aload(1'b0),
.sclr(ddioreg_sclr),
.sload(ddioreg_sload),
.asdata(ddioreg_adatasdata),
.ena(ena),
.prn(ddioreg_prn),
.q(dffhi_tmp),
.devpor(devpor),
.devclrn(devclrn)
);
defparam ddioreg_hi.power_up = power_up;
assign clk_hi = (use_new_clocking_model == "true") ? clkhi : clk;
assign datainhi_tmp = dinhi_tmp;
//DDIO Low Register
dffeas ddioreg_lo(
.d(datainlo_tmp),
.clk(clk_lo),
.clrn(ddioreg_aclr),
.aload(1'b0),
.sclr(ddioreg_sclr),
.sload(ddioreg_sload),
.asdata(ddioreg_adatasdata),
.ena(ena),
.prn(ddioreg_prn),
.q(dfflo_tmp),
.devpor(devpor),
.devclrn(devclrn)
);
defparam ddioreg_lo.power_up = power_up;
assign clk_lo = (use_new_clocking_model == "true") ? clklo : clk;
assign datainlo_tmp = dinlo_tmp;
//DDIO High Register
dffeas ddioreg_hi1(
.d(dffhi_tmp),
.clk(!clk_hr),
.clrn(ddioreg_aclr),
.aload(1'b0),
.sclr(ddioreg_sclr),
.sload(ddioreg_sload),
.asdata(ddioreg_adatasdata),
.ena(ena),
.prn(ddioreg_prn),
.q(dffhi1_tmp),
.devpor(devpor),
.devclrn(devclrn)
);
defparam ddioreg_hi1.power_up = power_up;
assign clk_hr = (use_new_clocking_model == "true") ? clkhi : clk;
//registered output selection
stratixv_mux21 sel_mux(
.MO(dataout),
.A(sel_mux_lo_in),
.B(sel_mux_hi_in),
.S(muxsel_tmp)
);
assign muxsel3 = muxsel2;
assign clk3 = clk2;
assign mux_sel = (use_new_clocking_model == "true")? muxsel3 : clk3;
assign sel_mux_lo_in = sel_mux_lo_in_tmp;
assign sel_mux_hi_in = dffhi_tmp;
endmodule |
module stratixv_ddio_oe (
oe,
clk,
ena,
areset,
sreset,
dataout,
dfflo,
dffhi,
devpor,
devclrn
);
//Parameters Declaration
parameter power_up = "low";
parameter async_mode = "none";
parameter sync_mode = "none";
parameter lpm_type = "stratixv_ddio_oe";
//Input Ports Declaration
input oe;
input clk;
input ena;
input areset;
input sreset;
input devpor;
input devclrn;
//Output Ports Declaration
output dataout;
//Buried Ports Declaration
output dfflo;
output dffhi;
tri1 devclrn;
tri1 devpor;
//Internal Signals
reg ddioreg_aclr;
reg ddioreg_prn;
reg ddioreg_adatasdata;
reg ddioreg_sclr;
reg ddioreg_sload;
reg viol_notifier;
initial
begin
ddioreg_aclr = 1'b1;
ddioreg_prn = 1'b1;
ddioreg_adatasdata = 1'b0;
ddioreg_sclr = 1'b0;
ddioreg_sload = 1'b0;
end
wire dfflo_tmp;
wire dffhi_tmp;
always@(areset or sreset )
begin
if(async_mode == "clear")
begin
ddioreg_aclr = !areset;
ddioreg_prn = 1'b1;
end
else if(async_mode == "preset")
begin
ddioreg_aclr = 'b1;
ddioreg_prn = !areset;
end
else
begin
ddioreg_aclr = 'b1;
ddioreg_prn = 'b1;
end
if(sync_mode == "clear")
begin
ddioreg_adatasdata = 'b0;
ddioreg_sclr = sreset;
ddioreg_sload = 'b0;
end
else if(sync_mode == "preset")
begin
ddioreg_adatasdata = 'b1;
ddioreg_sclr = 'b0;
ddioreg_sload = sreset;
end
else
begin
ddioreg_adatasdata = 'b0;
ddioreg_sclr = 'b0;
ddioreg_sload = 'b0;
end
end
//DDIO OE Register
dffeas ddioreg_hi(
.d(oe),
.clk(clk),
.clrn(ddioreg_aclr),
.aload(1'b0),
.sclr(ddioreg_sclr),
.sload(ddioreg_sload),
.asdata(ddioreg_adatasdata),
.ena(ena),
.prn(ddioreg_prn),
.q(dffhi_tmp),
.devpor(devpor),
.devclrn(devclrn)
);
defparam ddioreg_hi.power_up = power_up;
//DDIO Low Register
dffeas ddioreg_lo(
.d(dffhi_tmp),
.clk(!clk),
.clrn(ddioreg_aclr),
.aload(1'b0),
.sclr(ddioreg_sclr),
.sload(ddioreg_sload),
.asdata(ddioreg_adatasdata),
.ena(ena),
.prn(ddioreg_prn),
.q(dfflo_tmp),
.devpor(devpor),
.devclrn(devclrn)
);
defparam ddioreg_lo.power_up = power_up;
//registered output
stratixv_mux21 or_gate(
.MO(dataout),
.A(dffhi_tmp),
.B(dfflo_tmp),
.S(dfflo_tmp)
);
assign dfflo = dfflo_tmp;
assign dffhi = dffhi_tmp;
endmodule |
module stratixv_ddio_in (
datain,
clk,
clkn,
ena,
areset,
sreset,
regoutlo,
regouthi,
dfflo,
devpor,
devclrn
);
//Parameters Declaration
parameter power_up = "low";
parameter async_mode = "none";
parameter sync_mode = "none";
parameter use_clkn = "false";
parameter lpm_type = "stratixv_ddio_in";
//Input Ports Declaration
input datain;
input clk;
input clkn;
input ena;
input areset;
input sreset;
input devpor;
input devclrn;
//Output Ports Declaration
output regoutlo;
output regouthi;
//burried port;
output dfflo;
tri1 devclrn;
tri1 devpor;
//Internal Signals
reg ddioreg_aclr;
reg ddioreg_prn;
reg ddioreg_adatasdata;
reg ddioreg_sclr;
reg ddioreg_sload;
reg viol_notifier;
wire ddioreg_clk;
wire dfflo_tmp;
wire regout_tmp_hi;
wire regout_tmp_lo;
wire dff_ena;
initial
begin
ddioreg_aclr = 1'b1;
ddioreg_prn = 1'b1;
ddioreg_adatasdata = 1'b0;
ddioreg_sclr = 1'b0;
ddioreg_sload = 1'b0;
end
assign ddioreg_clk = (use_clkn == "false") ? !clk : clkn;
//Decode the control values for the DDIO registers
always@(areset or sreset )
begin
if(async_mode == "clear")
begin
ddioreg_aclr = !areset;
ddioreg_prn = 1'b1;
end
else if(async_mode == "preset")
begin
ddioreg_aclr = 'b1;
ddioreg_prn = !areset;
end
else
begin
ddioreg_aclr = 'b1;
ddioreg_prn = 'b1;
end
if(sync_mode == "clear")
begin
ddioreg_adatasdata = 'b0;
ddioreg_sclr = sreset;
ddioreg_sload = 'b0;
end
else if(sync_mode == "preset")
begin
ddioreg_adatasdata = 'b1;
ddioreg_sclr = 'b0;
ddioreg_sload = sreset;
end
else
begin
ddioreg_adatasdata = 'b0;
ddioreg_sclr = 'b0;
ddioreg_sload = 'b0;
end
end
//DDIO high Register
dffeas ddioreg_hi(
.d(datain),
.clk(clk),
.clrn(ddioreg_aclr),
.aload(1'b0),
.sclr(ddioreg_sclr),
.sload(ddioreg_sload),
.asdata(ddioreg_adatasdata),
.ena(ena),
.prn(ddioreg_prn),
.q(regout_tmp_hi),
.devpor(devpor),
.devclrn(devclrn)
);
defparam ddioreg_hi.power_up = power_up;
//DDIO Low Register
dffeas ddioreg_lo(
.d(datain),
.clk(ddioreg_clk),
.clrn(ddioreg_aclr),
.aload(1'b0),
.sclr(ddioreg_sclr),
.sload(ddioreg_sload),
.asdata(ddioreg_adatasdata),
.ena(ena),
.prn(ddioreg_prn),
.q(dfflo_tmp),
.devpor(devpor),
.devclrn(devclrn)
);
defparam ddioreg_lo.power_up = power_up;
dffeas ddioreg_lo1(
.d(dfflo_tmp),
.clk(clk),
.clrn(ddioreg_aclr),
.aload(1'b0),
.sclr(ddioreg_sclr),
.sload(ddioreg_sload),
.asdata(ddioreg_adatasdata),
.ena(ena),
.prn(ddioreg_prn),
.q(regout_tmp_lo),
.devpor(devpor),
.devclrn(devclrn)
);
defparam ddioreg_lo1.power_up = power_up;
assign regouthi = regout_tmp_hi;
assign regoutlo = regout_tmp_lo;
assign dfflo = dfflo_tmp;
endmodule |
module stratixv_io_pad (
padin,
padout
);
parameter lpm_type = "stratixv_io_pad";
//INPUT PORTS
input padin; //Input Pad
//OUTPUT PORTS
output padout;//Output Pad
//INTERNAL SIGNALS
wire padin_ipd;
wire padout_opd;
//INPUT BUFFER INSERTION FOR VERILOG-XL
buf padin_buf (padin_ipd,padin);
assign padout_opd = padin_ipd;
//OUTPUT BUFFER INSERTION FOR VERILOG-XL
buf padout_buf (padout, padout_opd);
endmodule |
module stratixv_pseudo_diff_out(
i,
o,
obar,
// ports new for StratixV
dtcin,
dtc,
dtcbar,
oein,
oeout,
oebout
);
parameter lpm_type = "stratixv_pseudo_diff_out";
input i;
output o;
output obar;
// ports new for StratixV
input dtcin, oein;
output dtc, dtcbar, oeout, oebout;
reg o_tmp;
reg obar_tmp;
reg dtc_tmp, dtcbar_tmp, oeout_tmp, oebout_tmp;
assign dtc = dtcin;
assign dtcbar = dtcin;
assign oeout = oein;
assign oebout = oein;
assign o = o_tmp;
assign obar = obar_tmp;
always@(i)
begin
if( i == 1'b1)
begin
o_tmp = 1'b1;
obar_tmp = 1'b0;
end
else if( i == 1'b0)
begin
o_tmp = 1'b0;
obar_tmp = 1'b1;
end
else
begin
o_tmp = i;
obar_tmp = i;
end
end // always@ (i)
endmodule |
module stratixv_bias_logic (
clk,
shiftnld,
captnupdt,
mainclk,
updateclk,
capture,
update
);
// INPUT PORTS
input clk;
input shiftnld;
input captnupdt;
// OUTPUTPUT PORTS
output mainclk;
output updateclk;
output capture;
output update;
// INTERNAL VARIABLES
reg mainclk_tmp;
reg updateclk_tmp;
reg capture_tmp;
reg update_tmp;
initial
begin
mainclk_tmp <= 'b0;
updateclk_tmp <= 'b0;
capture_tmp <= 'b0;
update_tmp <= 'b0;
end
always @(captnupdt or shiftnld or clk)
begin
case ({captnupdt, shiftnld})
2'b10, 2'b11 :
begin
mainclk_tmp <= 'b0;
updateclk_tmp <= clk;
capture_tmp <= 'b1;
update_tmp <= 'b0;
end
2'b01 :
begin
mainclk_tmp <= 'b0;
updateclk_tmp <= clk;
capture_tmp <= 'b0;
update_tmp <= 'b0;
end
2'b00 :
begin
mainclk_tmp <= clk;
updateclk_tmp <= 'b0;
capture_tmp <= 'b0;
update_tmp <= 'b1;
end
default :
begin
mainclk_tmp <= 'b0;
updateclk_tmp <= 'b0;
capture_tmp <= 'b0;
update_tmp <= 'b0;
end
endcase
end
and (mainclk, mainclk_tmp, 1'b1);
and (updateclk, updateclk_tmp, 1'b1);
and (capture, capture_tmp, 1'b1);
and (update, update_tmp, 1'b1);
endmodule |
module stratixv_bias_generator (
din,
mainclk,
updateclk,
capture,
update,
dout
);
// INPUT PORTS
input din;
input mainclk;
input updateclk;
input capture;
input update;
// OUTPUTPUT PORTS
output dout;
parameter TOTAL_REG = 202;
// INTERNAL VARIABLES
reg dout_tmp;
reg generator_reg [TOTAL_REG - 1:0];
reg update_reg [TOTAL_REG - 1:0];
integer i;
initial
begin
dout_tmp <= 'b0;
for (i = 0; i < TOTAL_REG; i = i + 1)
begin
generator_reg [i] <= 'b0;
update_reg [i] <= 'b0;
end
end
// main generator registers
always @(posedge mainclk)
begin
if ((capture == 'b0) && (update == 'b1)) //update main registers
begin
for (i = 0; i < TOTAL_REG; i = i + 1)
begin
generator_reg[i] <= update_reg[i];
end
end
end
// update registers
always @(posedge updateclk)
begin
dout_tmp <= update_reg[TOTAL_REG - 1];
if ((capture == 'b0) && (update == 'b0)) //shift update registers
begin
for (i = (TOTAL_REG - 1); i > 0; i = i - 1)
begin
update_reg[i] <= update_reg[i - 1];
end
update_reg[0] <= din;
end
else if ((capture == 'b1) && (update == 'b0)) //load update registers
begin
for (i = 0; i < TOTAL_REG; i = i + 1)
begin
update_reg[i] <= generator_reg[i];
end
end
end
and (dout, dout_tmp, 1'b1);
endmodule |
module stratixv_bias_block(
clk,
shiftnld,
captnupdt,
din,
dout
);
// INPUT PORTS
input clk;
input shiftnld;
input captnupdt;
input din;
// OUTPUTPUT PORTS
output dout;
parameter lpm_type = "stratixv_bias_block";
// INTERNAL VARIABLES
reg din_viol;
reg shiftnld_viol;
reg captnupdt_viol;
wire mainclk_wire;
wire updateclk_wire;
wire capture_wire;
wire update_wire;
wire dout_tmp;
specify
$setuphold (posedge clk, din, 0, 0, din_viol) ;
$setuphold (posedge clk, shiftnld, 0, 0, shiftnld_viol) ;
$setuphold (posedge clk, captnupdt, 0, 0, captnupdt_viol) ;
(posedge clk => (dout +: dout_tmp)) = 0 ;
endspecify
stratixv_bias_logic logic_block (
.clk(clk),
.shiftnld(shiftnld),
.captnupdt(captnupdt),
.mainclk(mainclk_wire),
.updateclk(updateclk_wire),
.capture(capture_wire),
.update(update_wire)
);
stratixv_bias_generator bias_generator (
.din(din),
.mainclk(mainclk_wire),
.updateclk(updateclk_wire),
.capture(capture_wire),
.update(update_wire),
.dout(dout_tmp)
);
and (dout, dout_tmp, 1'b1);
endmodule |
module stratixv_mac(
accumulate,
aclr,
ax,
ay,
az,
bx,
by,
chainin,
cin,
clk,
coefsela,
coefselb,
complex,
ena,
loadconst,
negate,
scanin,
sub,
chainout,
cout,
dftout,
resulta,
resultb,
scanout
);
//PARAMETERS
parameter lpm_type = "stratixv_mac";
parameter ax_width = 16;
parameter ay_scan_in_width = 16;
parameter az_width = 1;
parameter bx_width = 16;
parameter by_width = 16;
parameter scan_out_width = 1;
parameter result_a_width = 33;
parameter result_b_width = 1;
parameter operation_mode = "m18x18_sumof2";
parameter mode_sub_location = 0;
parameter operand_source_max = "input";
parameter operand_source_may = "input";
parameter operand_source_mbx = "input";
parameter operand_source_mby = "input";
parameter preadder_subtract_a = "false";
parameter preadder_subtract_b = "false";
parameter signed_max = "false";
parameter signed_may = "false";
parameter signed_mbx = "false";
parameter signed_mby = "false";
parameter ay_use_scan_in = "false";
parameter by_use_scan_in = "false";
parameter delay_scan_out_ay = "false";
parameter delay_scan_out_by = "false";
parameter use_chainadder = "false";
parameter [5:0] load_const_value = 6'b0;
parameter signed [26:0] coef_a_0 = 0;
parameter signed [26:0] coef_a_1 = 0;
parameter signed [26:0] coef_a_2 = 0;
parameter signed [26:0] coef_a_3 = 0;
parameter signed [26:0] coef_a_4 = 0;
parameter signed [26:0] coef_a_5 = 0;
parameter signed [26:0] coef_a_6 = 0;
parameter signed [26:0] coef_a_7 = 0;
parameter signed [17:0] coef_b_0 = 0;
parameter signed [17:0] coef_b_1 = 0;
parameter signed [17:0] coef_b_2 = 0;
parameter signed [17:0] coef_b_3 = 0;
parameter signed [17:0] coef_b_4 = 0;
parameter signed [17:0] coef_b_5 = 0;
parameter signed [17:0] coef_b_6 = 0;
parameter signed [17:0] coef_b_7 = 0;
parameter ax_clock = "none";
parameter ay_scan_in_clock = "none";
parameter az_clock = "none";
parameter bx_clock = "none";
parameter by_clock = "none";
parameter coef_sel_a_clock = "none";
parameter coef_sel_b_clock = "none";
parameter sub_clock = "none";
parameter negate_clock = "none";
parameter accumulate_clock = "none";
parameter load_const_clock = "none";
parameter complex_clock = "none";
parameter output_clock = "none";
//INPUT PORTS
input sub;
input negate;
input accumulate;
input loadconst;
input complex;
input cin;
input [ax_width-1 : 0] ax;
input [ay_scan_in_width-1 : 0] ay;
input [ay_scan_in_width-1 : 0] scanin;
input [az_width-1 : 0] az;
input [bx_width-1 : 0] bx;
input [by_width-1 : 0] by;
input [2:0] coefsela;
input [2:0] coefselb;
input [2:0] clk;
input [1:0] aclr;
input [2:0] ena;
input [63 : 0] chainin;
//OUTPUT PORTS
output cout;
output dftout;
output [result_a_width-1 : 0] resulta;
output [result_b_width-1 : 0] resultb;
output [scan_out_width-1 : 0] scanout;
output [63 : 0] chainout;
stratixv_mac_encrypted mac_core0
(
.sub(sub),
.negate(negate),
.accumulate(accumulate),
.loadconst(loadconst),
.complex(complex),
.cin(cin),
.ax(ax),
.ay(ay),
.az(az),
.bx(bx),
.by(by),
.scanin(scanin),
.coefsela(coefsela),
.coefselb(coefselb),
.clk(clk),
.aclr(aclr),
.ena(ena),
.chainin(chainin),
.dftout(dftout),
.cout(cout),
.resulta(resulta),
.resultb(resultb),
.scanout(scanout),
.chainout(chainout)
);
defparam mac_core0.ax_width = ax_width;
defparam mac_core0.ay_scan_in_width = ay_scan_in_width;
defparam mac_core0.az_width = az_width;
defparam mac_core0.bx_width = bx_width;
defparam mac_core0.by_width = by_width;
defparam mac_core0.scan_out_width = scan_out_width;
defparam mac_core0.result_a_width = result_a_width;
defparam mac_core0.result_b_width = result_b_width;
defparam mac_core0.operation_mode = operation_mode;
defparam mac_core0.mode_sub_location = mode_sub_location;
defparam mac_core0.operand_source_max = operand_source_max;
defparam mac_core0.operand_source_may = operand_source_may;
defparam mac_core0.operand_source_mbx = operand_source_mbx;
defparam mac_core0.operand_source_mby = operand_source_mby;
defparam mac_core0.preadder_subtract_a = preadder_subtract_a;
defparam mac_core0.preadder_subtract_b = preadder_subtract_b;
defparam mac_core0.signed_max = signed_max;
defparam mac_core0.signed_may = signed_may;
defparam mac_core0.signed_mbx = signed_mbx;
defparam mac_core0.signed_mby = signed_mby;
defparam mac_core0.ay_use_scan_in = ay_use_scan_in;
defparam mac_core0.by_use_scan_in = by_use_scan_in;
defparam mac_core0.delay_scan_out_ay = delay_scan_out_ay;
defparam mac_core0.delay_scan_out_by = delay_scan_out_by;
defparam mac_core0.use_chainadder = use_chainadder;
defparam mac_core0.load_const_value = load_const_value;
defparam mac_core0.coef_a_0 = coef_a_0;
defparam mac_core0.coef_a_1 = coef_a_1;
defparam mac_core0.coef_a_2 = coef_a_2;
defparam mac_core0.coef_a_3 = coef_a_3;
defparam mac_core0.coef_a_4 = coef_a_4;
defparam mac_core0.coef_a_5 = coef_a_5;
defparam mac_core0.coef_a_6 = coef_a_6;
defparam mac_core0.coef_a_7 = coef_a_7;
defparam mac_core0.coef_b_0 = coef_b_0;
defparam mac_core0.coef_b_1 = coef_b_1;
defparam mac_core0.coef_b_2 = coef_b_2;
defparam mac_core0.coef_b_3 = coef_b_3;
defparam mac_core0.coef_b_4 = coef_b_4;
defparam mac_core0.coef_b_5 = coef_b_5;
defparam mac_core0.coef_b_6 = coef_b_6;
defparam mac_core0.coef_b_7 = coef_b_7;
defparam mac_core0.ax_clock = ax_clock;
defparam mac_core0.ay_scan_in_clock = ay_scan_in_clock;
defparam mac_core0.az_clock = az_clock;
defparam mac_core0.bx_clock = bx_clock;
defparam mac_core0.by_clock = by_clock;
defparam mac_core0.coef_sel_a_clock = coef_sel_a_clock;
defparam mac_core0.coef_sel_b_clock = coef_sel_b_clock;
defparam mac_core0.sub_clock = sub_clock;
defparam mac_core0.negate_clock = negate_clock;
defparam mac_core0.accumulate_clock = accumulate_clock;
defparam mac_core0.load_const_clock = load_const_clock;
defparam mac_core0.complex_clock = complex_clock;
defparam mac_core0.output_clock = output_clock;
endmodule |
module stratixv_clk_phase_select (
clkin,
phasectrlin,
phaseinvertctrl,
powerdown,
clkout);
parameter use_phasectrlin = "true";
parameter phase_setting = 0;
parameter invert_phase = "false";
parameter physical_clock_source = "auto";
input [3:0] clkin;
input [1:0] phasectrlin;
input phaseinvertctrl;
input powerdown;
output clkout;
stratixv_clk_phase_select_encrypted inst (
.clkin(clkin),
.phasectrlin(phasectrlin),
.phaseinvertctrl(phaseinvertctrl),
.powerdown(powerdown),
.clkout(clkout) );
defparam inst.use_phasectrlin = use_phasectrlin;
defparam inst.phase_setting = phase_setting;
defparam inst.invert_phase = invert_phase;
defparam inst.physical_clock_source = physical_clock_source;
endmodule |
module stratixv_clkena (
inclk,
ena,
enaout,
outclk);
// leda G_521_3_B off
parameter clock_type = "auto";
parameter ena_register_mode = "always enabled";
parameter lpm_type = "stratixv_clkena";
parameter ena_register_power_up = "high";
parameter disable_mode = "low";
parameter test_syn = "high";
// leda G_521_3_B on
input inclk;
input ena;
output enaout;
output outclk;
stratixv_clkena_encrypted inst (
.inclk(inclk),
.ena(ena),
.enaout(enaout),
.outclk(outclk) );
defparam inst.clock_type = clock_type;
defparam inst.ena_register_mode = ena_register_mode;
defparam inst.lpm_type = lpm_type;
defparam inst.ena_register_power_up = ena_register_power_up;
defparam inst.disable_mode = disable_mode;
defparam inst.test_syn = test_syn;
endmodule |
module stratixv_clkselect (
inclk,
clkselect,
outclk);
// leda G_521_3_B off
parameter lpm_type = "stratixv_clkselect";
parameter test_cff = "low";
// leda G_521_3_B on
input [3:0] inclk;
input [1:0] clkselect;
output outclk;
stratixv_clkselect_encrypted inst (
.inclk(inclk),
.clkselect(clkselect),
.outclk(outclk) );
defparam inst.lpm_type = lpm_type;
defparam inst.test_cff = test_cff;
endmodule |
module stratixv_delay_chain (
datain,
delayctrlin,
dataout);
parameter sim_intrinsic_rising_delay = 200;
parameter sim_intrinsic_falling_delay = 200;
parameter sim_rising_delay_increment = 10;
parameter sim_falling_delay_increment = 10;
parameter lpm_type = "stratixv_delay_chain";
input datain;
input [7:0] delayctrlin;
output dataout;
stratixv_delay_chain_encrypted inst (
.datain(datain),
.delayctrlin(delayctrlin),
.dataout(dataout) );
defparam inst.sim_intrinsic_rising_delay = sim_intrinsic_rising_delay;
defparam inst.sim_intrinsic_falling_delay = sim_intrinsic_falling_delay;
defparam inst.sim_rising_delay_increment = sim_rising_delay_increment;
defparam inst.sim_falling_delay_increment = sim_falling_delay_increment;
defparam inst.lpm_type = lpm_type;
endmodule |
module stratixv_dll_offset_ctrl (
clk,
offsetdelayctrlin,
offset,
addnsub,
aload,
offsetctrlout,
offsettestout);
parameter use_offset = "false";
parameter static_offset = 0;
parameter use_pvt_compensation = "false";
input clk;
input [6:0] offsetdelayctrlin;
input [6:0] offset;
input addnsub;
input aload;
output [6:0] offsetctrlout;
output [6:0] offsettestout;
stratixv_dll_offset_ctrl_encrypted inst (
.clk(clk),
.offsetdelayctrlin(offsetdelayctrlin),
.offset(offset),
.addnsub(addnsub),
.aload(aload),
.offsetctrlout(offsetctrlout),
.offsettestout(offsettestout) );
defparam inst.use_offset = use_offset;
defparam inst.static_offset = static_offset;
defparam inst.use_pvt_compensation = use_pvt_compensation;
endmodule |
module stratixv_dll (
aload,
clk,
upndnin,
upndninclkena,
delayctrlout,
dqsupdate,
offsetdelayctrlout,
offsetdelayctrlclkout,
upndnout,
dffin,
locked);
parameter input_frequency = "0 MHz";
parameter delayctrlout_mode = "normal";
parameter jitter_reduction = "false";
parameter use_upndnin = "false";
parameter use_upndninclkena = "false";
parameter dual_phase_comparators = "true";
parameter sim_valid_lock = 16;
parameter sim_valid_lockcount = 0;
parameter sim_buffer_intrinsic_delay = 175;
parameter sim_buffer_delay_increment = 10;
parameter static_delay_ctrl = 0;
parameter lpm_type = "stratixv_dll";
parameter delay_chain_length = 8;
input aload;
input clk;
input upndnin;
input upndninclkena;
output [6:0] delayctrlout;
output dqsupdate;
output [6:0] offsetdelayctrlout;
output offsetdelayctrlclkout;
output upndnout;
output dffin;
output locked;
stratixv_dll_encrypted inst (
.aload(aload),
.clk(clk),
.upndnin(upndnin),
.upndninclkena(upndninclkena),
.delayctrlout(delayctrlout),
.dqsupdate(dqsupdate),
.offsetdelayctrlout(offsetdelayctrlout),
.offsetdelayctrlclkout(offsetdelayctrlclkout),
.upndnout(upndnout),
.dffin(dffin),
.locked(locked));
defparam inst.input_frequency = input_frequency;
defparam inst.delayctrlout_mode = delayctrlout_mode;
defparam inst.jitter_reduction = jitter_reduction;
defparam inst.use_upndnin = use_upndnin;
defparam inst.use_upndninclkena = use_upndninclkena;
defparam inst.dual_phase_comparators = dual_phase_comparators;
defparam inst.sim_valid_lock = sim_valid_lock;
defparam inst.sim_valid_lockcount = sim_valid_lockcount;
defparam inst.sim_buffer_intrinsic_delay = sim_buffer_intrinsic_delay;
defparam inst.sim_buffer_delay_increment = sim_buffer_delay_increment;
defparam inst.static_delay_ctrl = static_delay_ctrl;
defparam inst.lpm_type = lpm_type;
defparam inst.delay_chain_length = delay_chain_length;
endmodule |
module stratixv_dqs_config (
datain,
clk,
ena,
update,
postamblepowerdown,
dqsbusoutdelaysetting,
dqsbusoutdelaysetting2,
dqsinputphasesetting,
dqsoutputphasesetting,
dqoutputphasesetting,
resyncinputphasesetting,
enaoctcycledelaysetting,
enainputcycledelaysetting,
enaoutputcycledelaysetting,
dqsenabledelaysetting,
octdelaysetting1,
octdelaysetting2,
enadqsenablephasetransferreg,
enaoctphasetransferreg,
enaoutputphasetransferreg,
enainputphasetransferreg,
enadqscycledelaysetting,
enadqsphasetransferreg,
resyncinputphaseinvert,
dqoutputphaseinvert,
dqsoutputphaseinvert,
dataout,
resyncinputzerophaseinvert,
dqs2xoutputphasesetting,
dqs2xoutputphaseinvert,
ck2xoutputphasesetting,
ck2xoutputphaseinvert,
dq2xoutputphasesetting,
dq2xoutputphaseinvert,
postamblephasesetting,
postamblephaseinvert,
dividerphaseinvert,
addrphasesetting,
addrphaseinvert,
dqoutputzerophasesetting,
postamblezerophasesetting,
dividerioehratephaseinvert,
dqsdisablendelaysetting,
addrpowerdown,
dqsoutputpowerdown,
dqoutputpowerdown,
resyncinputpowerdown,
dqs2xoutputpowerdown,
ck2xoutputpowerdown,
dq2xoutputpowerdown);
parameter lpm_type = "stratixv_dqs_config";
// INPUT PORTS
input datain;
input clk;
input ena;
input update;
// OUTPUT PORTS
output dqoutputpowerdown;
output dqsoutputpowerdown;
output resyncinputpowerdown;
output postamblepowerdown;
output [5:0] dqsbusoutdelaysetting;
output [5:0] dqsbusoutdelaysetting2; // SPR 362735
output [1:0] dqsinputphasesetting; // SPR 362735
output [1:0] dqsoutputphasesetting; // SPR 362735
output [1:0] dqoutputphasesetting; // SPR 362735
output [1:0] resyncinputphasesetting; // SPR 362735
output [2:0] enaoctcycledelaysetting; // SPR 362735
output enainputcycledelaysetting;
output [2:0] enaoutputcycledelaysetting; // SPR 362735
output [7:0] dqsenabledelaysetting; // SPR 362735
output [4:0] octdelaysetting1; // SPR 362735
output [4:0] octdelaysetting2; // SPR 362735
output enadqsenablephasetransferreg;
output enaoctphasetransferreg;
output enaoutputphasetransferreg;
output enainputphasetransferreg;
output [2:0] enadqscycledelaysetting; // SPR 362735
output enadqsphasetransferreg;
output resyncinputphaseinvert;
output dqoutputphaseinvert;
output dqsoutputphaseinvert;
output dataout;
output resyncinputzerophaseinvert;
output [1:0] dqs2xoutputphasesetting; // SPR 362735
output dqs2xoutputphaseinvert;
output [1:0] ck2xoutputphasesetting; // SPR 362735
output ck2xoutputphaseinvert;
output [1:0] dq2xoutputphasesetting; // SPR 362735
output dq2xoutputphaseinvert;
output [1:0] postamblephasesetting; // SPR 362735
output postamblephaseinvert;
output [1:0] addrphasesetting; // SPR 362735
output addrphaseinvert;
output [1:0] dqoutputzerophasesetting; //SPR 362735
output [2:0] postamblezerophasesetting; //SPR 362735
output dividerioehratephaseinvert; // SPR 362735
output dividerphaseinvert; // SPR 362735
output [7:0] dqsdisablendelaysetting; // SPR 362735
output addrpowerdown;
output dqs2xoutputpowerdown;
output ck2xoutputpowerdown;
output dq2xoutputpowerdown;
stratixv_dqs_config_encrypted inst (
.datain(datain),
.clk(clk),
.ena(ena),
.update(update),
.dqsbusoutdelaysetting(dqsbusoutdelaysetting),
.dqsbusoutdelaysetting2(dqsbusoutdelaysetting2),
.dqsinputphasesetting(dqsinputphasesetting),
.dqsoutputphasesetting(dqsoutputphasesetting),
.dqoutputphasesetting(dqoutputphasesetting),
.resyncinputphasesetting(resyncinputphasesetting),
.enaoctcycledelaysetting(enaoctcycledelaysetting),
.enainputcycledelaysetting(enainputcycledelaysetting),
.enaoutputcycledelaysetting(enaoutputcycledelaysetting),
.dqsenabledelaysetting(dqsenabledelaysetting),
.octdelaysetting1(octdelaysetting1),
.octdelaysetting2(octdelaysetting2),
.enadqsenablephasetransferreg(enadqsenablephasetransferreg),
.enaoctphasetransferreg(enaoctphasetransferreg),
.enaoutputphasetransferreg(enaoutputphasetransferreg),
.enainputphasetransferreg(enainputphasetransferreg),
.enadqscycledelaysetting(enadqscycledelaysetting),
.enadqsphasetransferreg(enadqsphasetransferreg),
.resyncinputphaseinvert(resyncinputphaseinvert),
.dqoutputphaseinvert(dqoutputphaseinvert),
.dqsoutputphaseinvert(dqsoutputphaseinvert),
.dataout(dataout),
.resyncinputzerophaseinvert(resyncinputzerophaseinvert),
.dqs2xoutputphasesetting(dqs2xoutputphasesetting),
.dqs2xoutputphaseinvert(dqs2xoutputphaseinvert),
.ck2xoutputphasesetting(ck2xoutputphasesetting),
.ck2xoutputphaseinvert(ck2xoutputphaseinvert),
.dq2xoutputphasesetting(dq2xoutputphasesetting),
.dq2xoutputphaseinvert(dq2xoutputphaseinvert),
.postamblephasesetting(postamblephasesetting),
.postamblephaseinvert(postamblephaseinvert),
.dividerphaseinvert(dividerphaseinvert),
.addrphasesetting(addrphasesetting),
.addrphaseinvert(addrphaseinvert),
.dqoutputzerophasesetting(dqoutputzerophasesetting),
.postamblezerophasesetting(postamblezerophasesetting),
.dividerioehratephaseinvert(dividerioehratephaseinvert),
.dqsdisablendelaysetting(dqsdisablendelaysetting),
.addrpowerdown(addrpowerdown),
.dqsoutputpowerdown(dqsoutputpowerdown),
.dqoutputpowerdown(dqoutputpowerdown),
.resyncinputpowerdown(resyncinputpowerdown),
.dqs2xoutputpowerdown(dqs2xoutputpowerdown),
.ck2xoutputpowerdown(ck2xoutputpowerdown),
.dq2xoutputpowerdown(dq2xoutputpowerdown),
.postamblepowerdown(postamblepowerdown));
defparam inst.lpm_type = lpm_type;
endmodule |
module stratixv_dqs_delay_chain (
dqsin,
dqsenable,
dqsdisablen,
delayctrlin,
offsetctrlin,
dqsupdateen,
phasectrlin,
testin,
dffin,
dqsbusout);
parameter dqs_input_frequency = "unused";
parameter dqs_phase_shift = 0;
parameter use_phasectrlin = "false";
parameter phase_setting = 0;
parameter dqs_offsetctrl_enable = "false";
parameter dqs_ctrl_latches_enable = "false";
parameter use_alternate_input_for_first_stage_delayctrl = "false";
parameter sim_buffer_intrinsic_delay = 175;
parameter sim_buffer_delay_increment = 10;
parameter test_enable = "false";
input dqsin;
input dqsenable;
input [6:0] delayctrlin;
input [6:0] offsetctrlin;
input dqsupdateen;
input [1:0] phasectrlin;
input testin;
input dqsdisablen;
output dffin;
output dqsbusout;
stratixv_dqs_delay_chain_encrypted inst (
.dqsin(dqsin),
.dqsenable(dqsenable),
.delayctrlin(delayctrlin),
.offsetctrlin(offsetctrlin),
.dqsupdateen(dqsupdateen),
.phasectrlin(phasectrlin),
.testin(testin),
.dqsdisablen(dqsdisablen),
.dffin(dffin),
.dqsbusout(dqsbusout) );
defparam inst.dqs_input_frequency = dqs_input_frequency;
defparam inst.dqs_phase_shift = dqs_phase_shift;
defparam inst.use_phasectrlin = use_phasectrlin;
defparam inst.phase_setting = phase_setting;
defparam inst.dqs_offsetctrl_enable = dqs_offsetctrl_enable;
defparam inst.dqs_ctrl_latches_enable = dqs_ctrl_latches_enable;
defparam inst.use_alternate_input_for_first_stage_delayctrl = use_alternate_input_for_first_stage_delayctrl;
defparam inst.sim_buffer_intrinsic_delay = sim_buffer_intrinsic_delay;
defparam inst.sim_buffer_delay_increment = sim_buffer_delay_increment;
defparam inst.test_enable = test_enable;
endmodule |
module stratixv_dqs_enable_ctrl (
dqsenablein,
zerophaseclk,
enaphasetransferreg,
levelingclk,
dffin,
dffphasetransfer,
dffextenddqsenable,
dqsenableout,
prevphasevalid,
enatrackingreset,
enatrackingevent,
enatrackingupdwn,
nextphasealign,
prevphasealign,
prevphasedelaysetting);
parameter bypass_output_register = "false";
parameter delay_dqs_enable_by_half_cycle = "false";
parameter add_phase_transfer_reg = "false";
parameter ext_delay_chain_setting = 0;
parameter int_delay_chain_setting = 0;
parameter use_enable_tracking = "false";
parameter use_on_die_variation_tracking = "false";
parameter use_pvt_compensation = "false";
parameter sim_dqsenablein_pre_delay = 0;
input dqsenablein;
input zerophaseclk;
input enaphasetransferreg;
input levelingclk;
input enatrackingreset;
output dffin;
output dffphasetransfer;
output dffextenddqsenable;
output dqsenableout;
output prevphasevalid;
output enatrackingevent;
output enatrackingupdwn;
output nextphasealign;
output prevphasealign;
output [5:0] prevphasedelaysetting;
stratixv_dqs_enable_ctrl_encrypted inst (
.dqsenablein(dqsenablein),
.zerophaseclk(zerophaseclk),
.enaphasetransferreg(enaphasetransferreg),
.levelingclk(levelingclk),
.dffin(dffin),
.dffphasetransfer(dffphasetransfer),
.dffextenddqsenable(dffextenddqsenable),
.dqsenableout(dqsenableout),
.prevphasevalid(prevphasevalid),
.enatrackingreset(enatrackingreset),
.enatrackingevent(enatrackingevent),
.enatrackingupdwn(enatrackingupdwn),
.nextphasealign(nextphasealign),
.prevphasealign(prevphasealign),
.prevphasedelaysetting(prevphasedelaysetting));
defparam inst.bypass_output_register = bypass_output_register;
defparam inst.delay_dqs_enable_by_half_cycle = delay_dqs_enable_by_half_cycle;
defparam inst.add_phase_transfer_reg = add_phase_transfer_reg;
defparam inst.sim_dqsenablein_pre_delay = sim_dqsenablein_pre_delay;
defparam inst.ext_delay_chain_setting = ext_delay_chain_setting;
defparam inst.int_delay_chain_setting = int_delay_chain_setting;
defparam inst.use_enable_tracking = use_enable_tracking;
defparam inst.use_on_die_variation_tracking = use_on_die_variation_tracking;
defparam inst.use_pvt_compensation = use_pvt_compensation;
endmodule |
module stratixv_duty_cycle_adjustment (
clkin,
delaymode,
delayctrlin,
clkout);
parameter duty_cycle_delay_mode = "none";
parameter lpm_type = "stratixv_duty_cycle_adjustment";
input clkin;
input delaymode;
input [3:0] delayctrlin;
output clkout;
stratixv_duty_cycle_adjustment_encrypted inst (
.clkin(clkin),
.delaymode(delaymode),
.delayctrlin(delayctrlin),
.clkout(clkout) );
defparam inst.duty_cycle_delay_mode = duty_cycle_delay_mode;
defparam inst.lpm_type = lpm_type;
endmodule |
module stratixv_fractional_pll
#(
// parameter declaration and default value assignemnt
parameter output_clock_frequency = "", //Valid values:
parameter reference_clock_frequency = "", //Valid values:
parameter mimic_fbclk_type = "cdb_pll_mimic_fbclk_gclk", //Valid values: gclk|qclk|none
parameter dsm_accumulator_reset_value = 0, //Valid values: 0|1
parameter forcelock = "false", //Valid values: false|true
parameter nreset_invert = "false", //Valid values: false|true
parameter pll_atb = 0, //Valid values: 0..15
parameter pll_bwctrl = 10000, //Valid values: 18000|16000|14000|12000|10000|8000|6000|4000|2000|1000|500
parameter pll_cmp_buf_dly = "0 ps", //Valid values: 0 ps|1000 ps|2000 ps|3000 ps|4000 ps|5000 ps
parameter pll_cp_comp = "true", //Valid values: false|true
parameter pll_cp_current = 20, //Valid values: 5|10|20|30|40
parameter pll_ctrl_override_setting = "false", //Valid values: false|true
parameter pll_dsm_dither = "disable", //Valid values: disable|pattern1|pattern2|pattern3
parameter pll_dsm_out_sel = "disable", //Valid values: disable|1st_order|2nd_order|3rd_order
parameter pll_dsm_reset = "false", //Valid values: false|true
parameter pll_ecn_bypass = "false", //Valid values: false|true
parameter pll_ecn_test_en = "false", //Valid values: false|true
parameter pll_enable = "true", //Valid values: false|true
parameter pll_fbclk_mux_1 = "glb", //Valid values: glb|zbd|lvds|fbclk_fpll
parameter pll_fbclk_mux_2 = "fb_1", //Valid values: fb_1|m_cnt
parameter pll_fractional_carry_out = 24, //Valid values: 8|16|24|32
parameter pll_fractional_division = 1, //Valid values: 1..
parameter pll_fractional_value_ready = "true", //Valid values:
parameter pll_lf_testen = "false", //Valid values: false|true
parameter pll_lock_fltr_cfg = 0, //Valid values: 0..4095
parameter pll_lock_fltr_test = "false", //Valid values: false|true
parameter pll_m_cnt_bypass_en = "false", //Valid values: false|true
parameter pll_m_cnt_coarse_dly = "0 ps", //Valid values: 0 ps|200 ps|400 ps|600 ps|800 ps|1000 ps
parameter pll_m_cnt_fine_dly = "0 ps", //Valid values: 0 ps|50 ps|100 ps|150 ps
parameter pll_m_cnt_hi_div = 1, //Valid values: 1..256
parameter pll_m_cnt_in_src = "ph_mux_clk", //Valid values: ph_mux_clk|fblvds|test_clk|vss
parameter pll_m_cnt_lo_div = 1, //Valid values: 1..256
parameter pll_m_cnt_odd_div_duty_en = "false", //Valid values: false|true
parameter pll_m_cnt_ph_mux_prst = 0, //Valid values: 0..7
parameter pll_m_cnt_prst = 1, //Valid values: 1..256
parameter pll_n_cnt_bypass_en = "false", //Valid values: false|true
parameter pll_n_cnt_coarse_dly = "0 ps", //Valid values: 0 ps|200 ps|400 ps|600 ps|800 ps|1000 ps
parameter pll_n_cnt_fine_dly = "0 ps", //Valid values: 0 ps|50 ps|100 ps|150 ps
parameter pll_n_cnt_hi_div = 1, //Valid values: 1..256
parameter pll_n_cnt_lo_div = 1, //Valid values: 1..256
parameter pll_n_cnt_odd_div_duty_en = "false", //Valid values: false|true
parameter pll_ref_buf_dly = "0 ps", //Valid values: 0 ps|1000 ps|2000 ps|3000 ps|4000 ps|5000 ps
parameter pll_reg_boost = 0, //Valid values: 0|10|15|20|30|40|50|60
parameter pll_regulator_bypass = "false", //Valid values: false|true
parameter pll_ripplecap_ctrl = 0, //Valid values: 0|2
parameter pll_slf_rst = "false", //Valid values: false|true
parameter pll_tclk_mux_en = "false", //Valid values:
parameter pll_tclk_sel = "cdb_pll_tclk_sel_m_src", //Valid values: n_src|m_src
parameter pll_test_enable = "false", //Valid values: false|true
parameter pll_testdn_enable = "false", //Valid values: false|true
parameter pll_testup_enable = "false", //Valid values: false|true
parameter pll_unlock_fltr_cfg = 0, //Valid values: 0..7
parameter pll_vco_div = 2, //Valid values: 1|2
parameter pll_vco_ph0_en = "false", //Valid values: false|true
parameter pll_vco_ph1_en = "false", //Valid values: false|true
parameter pll_vco_ph2_en = "false", //Valid values: false|true
parameter pll_vco_ph3_en = "false", //Valid values: false|true
parameter pll_vco_ph4_en = "false", //Valid values: false|true
parameter pll_vco_ph5_en = "false", //Valid values: false|true
parameter pll_vco_ph6_en = "false", //Valid values: false|true
parameter pll_vco_ph7_en = "false", //Valid values: false|true
parameter pll_vctrl_test_voltage = 750, //Valid values: 0|450|600|750|900|1050|1350|1500
parameter vccd0g_atb = "disable", //Valid values: disable|vccregx_vregb|vregs_vregc
parameter vccd0g_output = 0, //Valid values: 0|4|8|13|16|-8|-14|-19
parameter vccd1g_atb = "disable", //Valid values: disable|vccregx_vregb|vregs_vregc
parameter vccd1g_output = 0, //Valid values: 0|4|8|13|16|-8|-14|-19
parameter vccm1g_tap = 2, //Valid values: 0..3
parameter vccr_pd = "false", //Valid values: false|true
parameter vcodiv_override = "false" //Valid values: false|true
)
(
//input and output port declaration
input [ 0:0 ] coreclkfb,
input [ 0:0 ] ecnc1test,
input [ 0:0 ] ecnc2test,
input [ 0:0 ] fbclkfpll,
input [ 0:0 ] lvdsfbin,
input [ 0:0 ] nresync,
input [ 0:0 ] pfden,
input [ 0:0 ] refclkin,
input [ 0:0 ] shift,
input [ 0:0 ] shiftdonein,
input [ 0:0 ] shiften,
input [ 0:0 ] up,
input [ 0:0 ] vsspl,
input [ 0:0 ] zdb,
output [ 0:0 ] cntnen,
output [ 0:0 ] fbclk,
output [ 0:0 ] fblvdsout,
output [ 0:0 ] lock,
output [ 7:0 ] mhi,
output [ 0:0 ] mcntout,
output [ 0:0 ] plniotribuf,
output [ 0:0 ] shiftdoneout,
output [ 0:0 ] tclk,
output [ 7:0 ] vcoph
);
stratixv_fractional_pll_encrypted
#(
.output_clock_frequency(output_clock_frequency),
.reference_clock_frequency(reference_clock_frequency),
.mimic_fbclk_type(mimic_fbclk_type),
.dsm_accumulator_reset_value(dsm_accumulator_reset_value),
.forcelock(forcelock),
.nreset_invert(nreset_invert),
.pll_atb(pll_atb),
.pll_bwctrl(pll_bwctrl),
.pll_cmp_buf_dly(pll_cmp_buf_dly),
.pll_cp_comp(pll_cp_comp),
.pll_cp_current(pll_cp_current),
.pll_ctrl_override_setting(pll_ctrl_override_setting),
.pll_dsm_dither(pll_dsm_dither),
.pll_dsm_out_sel(pll_dsm_out_sel),
.pll_dsm_reset(pll_dsm_reset),
.pll_ecn_bypass(pll_ecn_bypass),
.pll_ecn_test_en(pll_ecn_test_en),
.pll_enable(pll_enable),
.pll_fbclk_mux_1(pll_fbclk_mux_1),
.pll_fbclk_mux_2(pll_fbclk_mux_2),
.pll_fractional_carry_out(pll_fractional_carry_out),
.pll_fractional_division(pll_fractional_division),
.pll_fractional_value_ready(pll_fractional_value_ready),
.pll_lf_testen(pll_lf_testen),
.pll_lock_fltr_cfg(pll_lock_fltr_cfg),
.pll_lock_fltr_test(pll_lock_fltr_test),
.pll_m_cnt_bypass_en(pll_m_cnt_bypass_en),
.pll_m_cnt_coarse_dly(pll_m_cnt_coarse_dly),
.pll_m_cnt_fine_dly(pll_m_cnt_fine_dly),
.pll_m_cnt_hi_div(pll_m_cnt_hi_div),
.pll_m_cnt_in_src(pll_m_cnt_in_src),
.pll_m_cnt_lo_div(pll_m_cnt_lo_div),
.pll_m_cnt_odd_div_duty_en(pll_m_cnt_odd_div_duty_en),
.pll_m_cnt_ph_mux_prst(pll_m_cnt_ph_mux_prst),
.pll_m_cnt_prst(pll_m_cnt_prst),
.pll_n_cnt_bypass_en(pll_n_cnt_bypass_en),
.pll_n_cnt_coarse_dly(pll_n_cnt_coarse_dly),
.pll_n_cnt_fine_dly(pll_n_cnt_fine_dly),
.pll_n_cnt_hi_div(pll_n_cnt_hi_div),
.pll_n_cnt_lo_div(pll_n_cnt_lo_div),
.pll_n_cnt_odd_div_duty_en(pll_n_cnt_odd_div_duty_en),
.pll_ref_buf_dly(pll_ref_buf_dly),
.pll_reg_boost(pll_reg_boost),
.pll_regulator_bypass(pll_regulator_bypass),
.pll_ripplecap_ctrl(pll_ripplecap_ctrl),
.pll_slf_rst(pll_slf_rst),
.pll_tclk_mux_en(pll_tclk_mux_en),
.pll_tclk_sel(pll_tclk_sel),
.pll_test_enable(pll_test_enable),
.pll_testdn_enable(pll_testdn_enable),
.pll_testup_enable(pll_testup_enable),
.pll_unlock_fltr_cfg(pll_unlock_fltr_cfg),
.pll_vco_div(pll_vco_div),
.pll_vco_ph0_en(pll_vco_ph0_en),
.pll_vco_ph1_en(pll_vco_ph1_en),
.pll_vco_ph2_en(pll_vco_ph2_en),
.pll_vco_ph3_en(pll_vco_ph3_en),
.pll_vco_ph4_en(pll_vco_ph4_en),
.pll_vco_ph5_en(pll_vco_ph5_en),
.pll_vco_ph6_en(pll_vco_ph6_en),
.pll_vco_ph7_en(pll_vco_ph7_en),
.pll_vctrl_test_voltage(pll_vctrl_test_voltage),
.vccd0g_atb(vccd0g_atb),
.vccd0g_output(vccd0g_output),
.vccd1g_atb(vccd1g_atb),
.vccd1g_output(vccd1g_output),
.vccm1g_tap(vccm1g_tap),
.vccr_pd(vccr_pd),
.vcodiv_override(vcodiv_override)
)
stratixv_fractional_pll_encrypted_inst (
.cntnen(cntnen),
.coreclkfb(coreclkfb),
.ecnc1test(ecnc1test),
.ecnc2test(ecnc2test),
.fbclkfpll(fbclkfpll),
.lvdsfbin(lvdsfbin),
.nresync(nresync),
.pfden(pfden),
.refclkin(refclkin),
.shift(shift),
.shiftdonein(shiftdonein),
.shiften(shiften),
.up(up),
.vsspl(vsspl),
.zdb(zdb),
.fbclk(fbclk),
.fblvdsout(fblvdsout),
.lock(lock),
.mhi(mhi),
.mcntout(mcntout),
.plniotribuf(plniotribuf),
.shiftdoneout(shiftdoneout),
.tclk(tclk),
.vcoph(vcoph)
);
endmodule |
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