module_content
stringlengths 18
1.05M
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module pcie_recv_fifo_blk_mem_gen_prim_width
(D,
clk,
tmp_ram_rd_en,
ram_full_fb_i_reg,
srst,
\gc0.count_d1_reg[8] ,
\gcc0.gc0.count_d1_reg[8] ,
din);
output [71:0]D;
input clk;
input tmp_ram_rd_en;
input [0:0]ram_full_fb_i_reg;
input srst;
input [8:0]\gc0.count_d1_reg[8] ;
input [8:0]\gcc0.gc0.count_d1_reg[8] ;
input [71:0]din;
wire [71:0]D;
wire clk;
wire [71:0]din;
wire [8:0]\gc0.count_d1_reg[8] ;
wire [8:0]\gcc0.gc0.count_d1_reg[8] ;
wire [0:0]ram_full_fb_i_reg;
wire srst;
wire tmp_ram_rd_en;
pcie_recv_fifo_blk_mem_gen_prim_wrapper \prim_noinit.ram
(.D(D),
.clk(clk),
.din(din),
.\gc0.count_d1_reg[8] (\gc0.count_d1_reg[8] ),
.\gcc0.gc0.count_d1_reg[8] (\gcc0.gc0.count_d1_reg[8] ),
.ram_full_fb_i_reg(ram_full_fb_i_reg),
.srst(srst),
.tmp_ram_rd_en(tmp_ram_rd_en));
endmodule |
module pcie_recv_fifo_blk_mem_gen_prim_width__parameterized0
(D,
clk,
tmp_ram_rd_en,
ram_full_fb_i_reg,
srst,
\gc0.count_d1_reg[8] ,
\gcc0.gc0.count_d1_reg[8] ,
din);
output [55:0]D;
input clk;
input tmp_ram_rd_en;
input [0:0]ram_full_fb_i_reg;
input srst;
input [8:0]\gc0.count_d1_reg[8] ;
input [8:0]\gcc0.gc0.count_d1_reg[8] ;
input [55:0]din;
wire [55:0]D;
wire clk;
wire [55:0]din;
wire [8:0]\gc0.count_d1_reg[8] ;
wire [8:0]\gcc0.gc0.count_d1_reg[8] ;
wire [0:0]ram_full_fb_i_reg;
wire srst;
wire tmp_ram_rd_en;
pcie_recv_fifo_blk_mem_gen_prim_wrapper__parameterized0 \prim_noinit.ram
(.D(D),
.clk(clk),
.din(din),
.\gc0.count_d1_reg[8] (\gc0.count_d1_reg[8] ),
.\gcc0.gc0.count_d1_reg[8] (\gcc0.gc0.count_d1_reg[8] ),
.ram_full_fb_i_reg(ram_full_fb_i_reg),
.srst(srst),
.tmp_ram_rd_en(tmp_ram_rd_en));
endmodule |
module pcie_recv_fifo_blk_mem_gen_prim_wrapper
(D,
clk,
tmp_ram_rd_en,
ram_full_fb_i_reg,
srst,
\gc0.count_d1_reg[8] ,
\gcc0.gc0.count_d1_reg[8] ,
din);
output [71:0]D;
input clk;
input tmp_ram_rd_en;
input [0:0]ram_full_fb_i_reg;
input srst;
input [8:0]\gc0.count_d1_reg[8] ;
input [8:0]\gcc0.gc0.count_d1_reg[8] ;
input [71:0]din;
wire [71:0]D;
wire clk;
wire [71:0]din;
wire [8:0]\gc0.count_d1_reg[8] ;
wire [8:0]\gcc0.gc0.count_d1_reg[8] ;
wire [0:0]ram_full_fb_i_reg;
wire srst;
wire tmp_ram_rd_en;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_SBITERR_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_RDADDRECC_UNCONNECTED ;
(* CLOCK_DOMAINS = "COMMON" *)
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(0),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("SDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(72),
.READ_WIDTH_B(0),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("READ_FIRST"),
.WRITE_MODE_B("READ_FIRST"),
.WRITE_WIDTH_A(0),
.WRITE_WIDTH_B(72))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram
(.ADDRARDADDR({1'b1,\gc0.count_d1_reg[8] ,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b1,\gcc0.gc0.count_d1_reg[8] ,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(clk),
.CLKBWRCLK(clk),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_DBITERR_UNCONNECTED ),
.DIADI({din[34:27],din[25:18],din[16:9],din[7:0]}),
.DIBDI({din[70:63],din[61:54],din[52:45],din[43:36]}),
.DIPADIP({din[35],din[26],din[17],din[8]}),
.DIPBDIP({din[71],din[62],din[53],din[44]}),
.DOADO({D[34:27],D[25:18],D[16:9],D[7:0]}),
.DOBDO({D[70:63],D[61:54],D[52:45],D[43:36]}),
.DOPADOP({D[35],D[26],D[17],D[8]}),
.DOPBDOP({D[71],D[62],D[53],D[44]}),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(tmp_ram_rd_en),
.ENBWREN(ram_full_fb_i_reg),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b0),
.REGCEB(1'b0),
.RSTRAMARSTRAM(srst),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_SBITERR_UNCONNECTED ),
.WEA({1'b0,1'b0,1'b0,1'b0}),
.WEBWE({ram_full_fb_i_reg,ram_full_fb_i_reg,ram_full_fb_i_reg,ram_full_fb_i_reg,ram_full_fb_i_reg,ram_full_fb_i_reg,ram_full_fb_i_reg,ram_full_fb_i_reg}));
endmodule |
module pcie_recv_fifo_blk_mem_gen_prim_wrapper__parameterized0
(D,
clk,
tmp_ram_rd_en,
ram_full_fb_i_reg,
srst,
\gc0.count_d1_reg[8] ,
\gcc0.gc0.count_d1_reg[8] ,
din);
output [55:0]D;
input clk;
input tmp_ram_rd_en;
input [0:0]ram_full_fb_i_reg;
input srst;
input [8:0]\gc0.count_d1_reg[8] ;
input [8:0]\gcc0.gc0.count_d1_reg[8] ;
input [55:0]din;
wire [55:0]D;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_21 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_29 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_37 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_45 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_53 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_61 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_69 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_77 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_85 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_86 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_87 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_88 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_89 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_90 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_91 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_92 ;
wire clk;
wire [55:0]din;
wire [8:0]\gc0.count_d1_reg[8] ;
wire [8:0]\gcc0.gc0.count_d1_reg[8] ;
wire [0:0]ram_full_fb_i_reg;
wire srst;
wire tmp_ram_rd_en;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_SBITERR_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_RDADDRECC_UNCONNECTED ;
(* CLOCK_DOMAINS = "COMMON" *)
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(0),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("SDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(72),
.READ_WIDTH_B(0),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("READ_FIRST"),
.WRITE_MODE_B("READ_FIRST"),
.WRITE_WIDTH_A(0),
.WRITE_WIDTH_B(72))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram
(.ADDRARDADDR({1'b1,\gc0.count_d1_reg[8] ,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b1,\gcc0.gc0.count_d1_reg[8] ,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(clk),
.CLKBWRCLK(clk),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,din[27:21],1'b0,din[20:14],1'b0,din[13:7],1'b0,din[6:0]}),
.DIBDI({1'b0,din[55:49],1'b0,din[48:42],1'b0,din[41:35],1'b0,din[34:28]}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO({\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_21 ,D[27:21],\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_29 ,D[20:14],\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_37 ,D[13:7],\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_45 ,D[6:0]}),
.DOBDO({\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_53 ,D[55:49],\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_61 ,D[48:42],\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_69 ,D[41:35],\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_77 ,D[34:28]}),
.DOPADOP({\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_85 ,\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_86 ,\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_87 ,\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_88 }),
.DOPBDOP({\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_89 ,\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_90 ,\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_91 ,\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_92 }),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(tmp_ram_rd_en),
.ENBWREN(ram_full_fb_i_reg),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b0),
.REGCEB(1'b0),
.RSTRAMARSTRAM(srst),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_SBITERR_UNCONNECTED ),
.WEA({1'b0,1'b0,1'b0,1'b0}),
.WEBWE({ram_full_fb_i_reg,ram_full_fb_i_reg,ram_full_fb_i_reg,ram_full_fb_i_reg,ram_full_fb_i_reg,ram_full_fb_i_reg,ram_full_fb_i_reg,ram_full_fb_i_reg}));
endmodule |
module pcie_recv_fifo_blk_mem_gen_top
(D,
clk,
tmp_ram_rd_en,
ram_full_fb_i_reg,
srst,
\gc0.count_d1_reg[8] ,
\gcc0.gc0.count_d1_reg[8] ,
din);
output [127:0]D;
input clk;
input tmp_ram_rd_en;
input [0:0]ram_full_fb_i_reg;
input srst;
input [8:0]\gc0.count_d1_reg[8] ;
input [8:0]\gcc0.gc0.count_d1_reg[8] ;
input [127:0]din;
wire [127:0]D;
wire clk;
wire [127:0]din;
wire [8:0]\gc0.count_d1_reg[8] ;
wire [8:0]\gcc0.gc0.count_d1_reg[8] ;
wire [0:0]ram_full_fb_i_reg;
wire srst;
wire tmp_ram_rd_en;
pcie_recv_fifo_blk_mem_gen_generic_cstr \valid.cstr
(.D(D),
.clk(clk),
.din(din),
.\gc0.count_d1_reg[8] (\gc0.count_d1_reg[8] ),
.\gcc0.gc0.count_d1_reg[8] (\gcc0.gc0.count_d1_reg[8] ),
.ram_full_fb_i_reg(ram_full_fb_i_reg),
.srst(srst),
.tmp_ram_rd_en(tmp_ram_rd_en));
endmodule |
module pcie_recv_fifo_blk_mem_gen_v8_3_1
(D,
clk,
tmp_ram_rd_en,
ram_full_fb_i_reg,
srst,
\gc0.count_d1_reg[8] ,
\gcc0.gc0.count_d1_reg[8] ,
din);
output [127:0]D;
input clk;
input tmp_ram_rd_en;
input [0:0]ram_full_fb_i_reg;
input srst;
input [8:0]\gc0.count_d1_reg[8] ;
input [8:0]\gcc0.gc0.count_d1_reg[8] ;
input [127:0]din;
wire [127:0]D;
wire clk;
wire [127:0]din;
wire [8:0]\gc0.count_d1_reg[8] ;
wire [8:0]\gcc0.gc0.count_d1_reg[8] ;
wire [0:0]ram_full_fb_i_reg;
wire srst;
wire tmp_ram_rd_en;
pcie_recv_fifo_blk_mem_gen_v8_3_1_synth inst_blk_mem_gen
(.D(D),
.clk(clk),
.din(din),
.\gc0.count_d1_reg[8] (\gc0.count_d1_reg[8] ),
.\gcc0.gc0.count_d1_reg[8] (\gcc0.gc0.count_d1_reg[8] ),
.ram_full_fb_i_reg(ram_full_fb_i_reg),
.srst(srst),
.tmp_ram_rd_en(tmp_ram_rd_en));
endmodule |
module pcie_recv_fifo_blk_mem_gen_v8_3_1_synth
(D,
clk,
tmp_ram_rd_en,
ram_full_fb_i_reg,
srst,
\gc0.count_d1_reg[8] ,
\gcc0.gc0.count_d1_reg[8] ,
din);
output [127:0]D;
input clk;
input tmp_ram_rd_en;
input [0:0]ram_full_fb_i_reg;
input srst;
input [8:0]\gc0.count_d1_reg[8] ;
input [8:0]\gcc0.gc0.count_d1_reg[8] ;
input [127:0]din;
wire [127:0]D;
wire clk;
wire [127:0]din;
wire [8:0]\gc0.count_d1_reg[8] ;
wire [8:0]\gcc0.gc0.count_d1_reg[8] ;
wire [0:0]ram_full_fb_i_reg;
wire srst;
wire tmp_ram_rd_en;
pcie_recv_fifo_blk_mem_gen_top \gnativebmg.native_blk_mem_gen
(.D(D),
.clk(clk),
.din(din),
.\gc0.count_d1_reg[8] (\gc0.count_d1_reg[8] ),
.\gcc0.gc0.count_d1_reg[8] (\gcc0.gc0.count_d1_reg[8] ),
.ram_full_fb_i_reg(ram_full_fb_i_reg),
.srst(srst),
.tmp_ram_rd_en(tmp_ram_rd_en));
endmodule |
module pcie_recv_fifo_compare
(ram_full_i,
v1_reg,
\gc0.count_d1_reg[8] ,
E,
srst,
comp1,
wr_en,
p_1_out);
output ram_full_i;
input [3:0]v1_reg;
input [0:0]\gc0.count_d1_reg[8] ;
input [0:0]E;
input srst;
input comp1;
input wr_en;
input p_1_out;
wire [0:0]E;
wire comp0;
wire comp1;
wire [0:0]\gc0.count_d1_reg[8] ;
wire \gmux.gm[3].gms.ms_n_0 ;
wire p_1_out;
wire ram_full_i;
wire srst;
wire [3:0]v1_reg;
wire wr_en;
wire [2:0]\NLW_gmux.gm[0].gm1.m1_CARRY4_CO_UNCONNECTED ;
wire [3:0]\NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED ;
wire [3:1]\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED ;
wire [3:1]\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED ;
wire [3:0]\NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED ;
wire [3:1]\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED ;
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
(* box_type = "PRIMITIVE" *)
CARRY4 \gmux.gm[0].gm1.m1_CARRY4
(.CI(1'b0),
.CO({\gmux.gm[3].gms.ms_n_0 ,\NLW_gmux.gm[0].gm1.m1_CARRY4_CO_UNCONNECTED [2:0]}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(\NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED [3:0]),
.S(v1_reg));
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
(* box_type = "PRIMITIVE" *)
CARRY4 \gmux.gm[4].gms.ms_CARRY4
(.CI(\gmux.gm[3].gms.ms_n_0 ),
.CO({\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED [3:1],comp0}),
.CYINIT(1'b0),
.DI({\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED [3:1],1'b0}),
.O(\NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED [3:0]),
.S({\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED [3:1],\gc0.count_d1_reg[8] }));
LUT6 #(
.INIT(64'h0707070703000000))
ram_full_i_i_1
(.I0(comp0),
.I1(E),
.I2(srst),
.I3(comp1),
.I4(wr_en),
.I5(p_1_out),
.O(ram_full_i));
endmodule |
module pcie_recv_fifo_compare_0
(comp1,
v1_reg_0);
output comp1;
input [4:0]v1_reg_0;
wire comp1;
wire \gmux.gm[3].gms.ms_n_0 ;
wire [4:0]v1_reg_0;
wire [2:0]\NLW_gmux.gm[0].gm1.m1_CARRY4_CO_UNCONNECTED ;
wire [3:0]\NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED ;
wire [3:1]\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED ;
wire [3:1]\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED ;
wire [3:0]\NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED ;
wire [3:1]\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED ;
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
(* box_type = "PRIMITIVE" *)
CARRY4 \gmux.gm[0].gm1.m1_CARRY4
(.CI(1'b0),
.CO({\gmux.gm[3].gms.ms_n_0 ,\NLW_gmux.gm[0].gm1.m1_CARRY4_CO_UNCONNECTED [2:0]}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(\NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED [3:0]),
.S(v1_reg_0[3:0]));
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
(* box_type = "PRIMITIVE" *)
CARRY4 \gmux.gm[4].gms.ms_CARRY4
(.CI(\gmux.gm[3].gms.ms_n_0 ),
.CO({\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED [3:1],comp1}),
.CYINIT(1'b0),
.DI({\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED [3:1],1'b0}),
.O(\NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED [3:0]),
.S({\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED [3:1],v1_reg_0[4]}));
endmodule |
module pcie_recv_fifo_compare_1
(ram_empty_fb_i,
v1_reg_0,
\gc0.count_d1_reg[8] ,
p_2_out,
srst,
E,
ram_full_fb_i_reg,
comp1);
output ram_empty_fb_i;
input [3:0]v1_reg_0;
input \gc0.count_d1_reg[8] ;
input p_2_out;
input srst;
input [0:0]E;
input ram_full_fb_i_reg;
input comp1;
wire [0:0]E;
wire comp0;
wire comp1;
wire \gc0.count_d1_reg[8] ;
wire \gmux.gm[3].gms.ms_n_0 ;
wire p_2_out;
wire ram_empty_fb_i;
wire ram_full_fb_i_reg;
wire srst;
wire [3:0]v1_reg_0;
wire [2:0]\NLW_gmux.gm[0].gm1.m1_CARRY4_CO_UNCONNECTED ;
wire [3:0]\NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED ;
wire [3:1]\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED ;
wire [3:1]\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED ;
wire [3:0]\NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED ;
wire [3:1]\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED ;
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
(* box_type = "PRIMITIVE" *)
CARRY4 \gmux.gm[0].gm1.m1_CARRY4
(.CI(1'b0),
.CO({\gmux.gm[3].gms.ms_n_0 ,\NLW_gmux.gm[0].gm1.m1_CARRY4_CO_UNCONNECTED [2:0]}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(\NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED [3:0]),
.S(v1_reg_0));
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
(* box_type = "PRIMITIVE" *)
CARRY4 \gmux.gm[4].gms.ms_CARRY4
(.CI(\gmux.gm[3].gms.ms_n_0 ),
.CO({\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED [3:1],comp0}),
.CYINIT(1'b0),
.DI({\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED [3:1],1'b0}),
.O(\NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED [3:0]),
.S({\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED [3:1],\gc0.count_d1_reg[8] }));
LUT6 #(
.INIT(64'hFFFAF2F2FAFAF2F2))
ram_empty_fb_i_i_1
(.I0(p_2_out),
.I1(comp0),
.I2(srst),
.I3(E),
.I4(ram_full_fb_i_reg),
.I5(comp1),
.O(ram_empty_fb_i));
endmodule |
module pcie_recv_fifo_compare_2
(comp1,
\gcc0.gc0.count_d1_reg[6] ,
v1_reg);
output comp1;
input [3:0]\gcc0.gc0.count_d1_reg[6] ;
input [0:0]v1_reg;
wire comp1;
wire [3:0]\gcc0.gc0.count_d1_reg[6] ;
wire \gmux.gm[3].gms.ms_n_0 ;
wire [0:0]v1_reg;
wire [2:0]\NLW_gmux.gm[0].gm1.m1_CARRY4_CO_UNCONNECTED ;
wire [3:0]\NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED ;
wire [3:1]\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED ;
wire [3:1]\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED ;
wire [3:0]\NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED ;
wire [3:1]\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED ;
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
(* box_type = "PRIMITIVE" *)
CARRY4 \gmux.gm[0].gm1.m1_CARRY4
(.CI(1'b0),
.CO({\gmux.gm[3].gms.ms_n_0 ,\NLW_gmux.gm[0].gm1.m1_CARRY4_CO_UNCONNECTED [2:0]}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(\NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED [3:0]),
.S(\gcc0.gc0.count_d1_reg[6] ));
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
(* box_type = "PRIMITIVE" *)
CARRY4 \gmux.gm[4].gms.ms_CARRY4
(.CI(\gmux.gm[3].gms.ms_n_0 ),
.CO({\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED [3:1],comp1}),
.CYINIT(1'b0),
.DI({\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED [3:1],1'b0}),
.O(\NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED [3:0]),
.S({\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED [3:1],v1_reg}));
endmodule |
module pcie_recv_fifo_fifo_generator_ramfifo
(empty,
full,
dout,
clk,
srst,
din,
rd_en,
wr_en);
output empty;
output full;
output [127:0]dout;
input clk;
input srst;
input [127:0]din;
input rd_en;
input wr_en;
wire clk;
wire [127:0]din;
wire [127:0]dout;
wire empty;
wire full;
wire \gntv_or_sync_fifo.gl0.wr_n_2 ;
wire [4:0]\grss.rsts/c1/v1_reg ;
wire [3:0]\grss.rsts/c2/v1_reg ;
wire [4:0]\gwss.wsts/c1/v1_reg ;
wire [8:0]p_0_out;
wire [8:0]p_10_out;
wire [8:0]p_11_out;
wire p_16_out;
wire p_5_out;
wire p_6_out;
wire rd_en;
wire [7:0]rd_pntr_plus1;
wire srst;
wire tmp_ram_rd_en;
wire wr_en;
pcie_recv_fifo_rd_logic \gntv_or_sync_fifo.gl0.rd
(.\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram (p_0_out),
.E(p_6_out),
.Q(rd_pntr_plus1),
.clk(clk),
.empty(empty),
.\gcc0.gc0.count_d1_reg[6] (\grss.rsts/c2/v1_reg ),
.\gcc0.gc0.count_d1_reg[8] (p_10_out[8]),
.\gcc0.gc0.count_reg[8] (p_11_out),
.\goreg_bm.dout_i_reg[127] (p_5_out),
.ram_full_fb_i_reg(\gntv_or_sync_fifo.gl0.wr_n_2 ),
.ram_full_i_reg(\grss.rsts/c1/v1_reg [4]),
.rd_en(rd_en),
.srst(srst),
.tmp_ram_rd_en(tmp_ram_rd_en),
.v1_reg(\gwss.wsts/c1/v1_reg ),
.v1_reg_0(\grss.rsts/c1/v1_reg [3:0]));
pcie_recv_fifo_wr_logic \gntv_or_sync_fifo.gl0.wr
(.\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram (p_10_out),
.E(p_6_out),
.Q(p_11_out),
.clk(clk),
.full(full),
.\gc0.count_d1_reg[7] (p_0_out[7:0]),
.\gc0.count_d1_reg[8] (\grss.rsts/c1/v1_reg [4]),
.\gc0.count_reg[7] (rd_pntr_plus1),
.\gcc0.gc0.count_reg[0] (p_16_out),
.ram_empty_fb_i_reg(\gntv_or_sync_fifo.gl0.wr_n_2 ),
.ram_empty_fb_i_reg_0(\grss.rsts/c2/v1_reg ),
.srst(srst),
.v1_reg(\grss.rsts/c1/v1_reg [3:0]),
.v1_reg_0(\gwss.wsts/c1/v1_reg ),
.wr_en(wr_en));
pcie_recv_fifo_memory \gntv_or_sync_fifo.mem
(.E(p_5_out),
.clk(clk),
.din(din),
.dout(dout),
.\gc0.count_d1_reg[8] (p_0_out),
.\gcc0.gc0.count_d1_reg[8] (p_10_out),
.ram_full_fb_i_reg(p_16_out),
.srst(srst),
.tmp_ram_rd_en(tmp_ram_rd_en));
endmodule |
module pcie_recv_fifo_fifo_generator_top
(empty,
full,
dout,
clk,
srst,
din,
rd_en,
wr_en);
output empty;
output full;
output [127:0]dout;
input clk;
input srst;
input [127:0]din;
input rd_en;
input wr_en;
wire clk;
wire [127:0]din;
wire [127:0]dout;
wire empty;
wire full;
wire rd_en;
wire srst;
wire wr_en;
pcie_recv_fifo_fifo_generator_ramfifo \grf.rf
(.clk(clk),
.din(din),
.dout(dout),
.empty(empty),
.full(full),
.rd_en(rd_en),
.srst(srst),
.wr_en(wr_en));
endmodule |
module pcie_recv_fifo_fifo_generator_v13_0_1
(backup,
backup_marker,
clk,
rst,
srst,
wr_clk,
wr_rst,
rd_clk,
rd_rst,
din,
wr_en,
rd_en,
prog_empty_thresh,
prog_empty_thresh_assert,
prog_empty_thresh_negate,
prog_full_thresh,
prog_full_thresh_assert,
prog_full_thresh_negate,
int_clk,
injectdbiterr,
injectsbiterr,
sleep,
dout,
full,
almost_full,
wr_ack,
overflow,
empty,
almost_empty,
valid,
underflow,
data_count,
rd_data_count,
wr_data_count,
prog_full,
prog_empty,
sbiterr,
dbiterr,
wr_rst_busy,
rd_rst_busy,
m_aclk,
s_aclk,
s_aresetn,
m_aclk_en,
s_aclk_en,
s_axi_awid,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awlock,
s_axi_awcache,
s_axi_awprot,
s_axi_awqos,
s_axi_awregion,
s_axi_awuser,
s_axi_awvalid,
s_axi_awready,
s_axi_wid,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wuser,
s_axi_wvalid,
s_axi_wready,
s_axi_bid,
s_axi_bresp,
s_axi_buser,
s_axi_bvalid,
s_axi_bready,
m_axi_awid,
m_axi_awaddr,
m_axi_awlen,
m_axi_awsize,
m_axi_awburst,
m_axi_awlock,
m_axi_awcache,
m_axi_awprot,
m_axi_awqos,
m_axi_awregion,
m_axi_awuser,
m_axi_awvalid,
m_axi_awready,
m_axi_wid,
m_axi_wdata,
m_axi_wstrb,
m_axi_wlast,
m_axi_wuser,
m_axi_wvalid,
m_axi_wready,
m_axi_bid,
m_axi_bresp,
m_axi_buser,
m_axi_bvalid,
m_axi_bready,
s_axi_arid,
s_axi_araddr,
s_axi_arlen,
s_axi_arsize,
s_axi_arburst,
s_axi_arlock,
s_axi_arcache,
s_axi_arprot,
s_axi_arqos,
s_axi_arregion,
s_axi_aruser,
s_axi_arvalid,
s_axi_arready,
s_axi_rid,
s_axi_rdata,
s_axi_rresp,
s_axi_rlast,
s_axi_ruser,
s_axi_rvalid,
s_axi_rready,
m_axi_arid,
m_axi_araddr,
m_axi_arlen,
m_axi_arsize,
m_axi_arburst,
m_axi_arlock,
m_axi_arcache,
m_axi_arprot,
m_axi_arqos,
m_axi_arregion,
m_axi_aruser,
m_axi_arvalid,
m_axi_arready,
m_axi_rid,
m_axi_rdata,
m_axi_rresp,
m_axi_rlast,
m_axi_ruser,
m_axi_rvalid,
m_axi_rready,
s_axis_tvalid,
s_axis_tready,
s_axis_tdata,
s_axis_tstrb,
s_axis_tkeep,
s_axis_tlast,
s_axis_tid,
s_axis_tdest,
s_axis_tuser,
m_axis_tvalid,
m_axis_tready,
m_axis_tdata,
m_axis_tstrb,
m_axis_tkeep,
m_axis_tlast,
m_axis_tid,
m_axis_tdest,
m_axis_tuser,
axi_aw_injectsbiterr,
axi_aw_injectdbiterr,
axi_aw_prog_full_thresh,
axi_aw_prog_empty_thresh,
axi_aw_data_count,
axi_aw_wr_data_count,
axi_aw_rd_data_count,
axi_aw_sbiterr,
axi_aw_dbiterr,
axi_aw_overflow,
axi_aw_underflow,
axi_aw_prog_full,
axi_aw_prog_empty,
axi_w_injectsbiterr,
axi_w_injectdbiterr,
axi_w_prog_full_thresh,
axi_w_prog_empty_thresh,
axi_w_data_count,
axi_w_wr_data_count,
axi_w_rd_data_count,
axi_w_sbiterr,
axi_w_dbiterr,
axi_w_overflow,
axi_w_underflow,
axi_w_prog_full,
axi_w_prog_empty,
axi_b_injectsbiterr,
axi_b_injectdbiterr,
axi_b_prog_full_thresh,
axi_b_prog_empty_thresh,
axi_b_data_count,
axi_b_wr_data_count,
axi_b_rd_data_count,
axi_b_sbiterr,
axi_b_dbiterr,
axi_b_overflow,
axi_b_underflow,
axi_b_prog_full,
axi_b_prog_empty,
axi_ar_injectsbiterr,
axi_ar_injectdbiterr,
axi_ar_prog_full_thresh,
axi_ar_prog_empty_thresh,
axi_ar_data_count,
axi_ar_wr_data_count,
axi_ar_rd_data_count,
axi_ar_sbiterr,
axi_ar_dbiterr,
axi_ar_overflow,
axi_ar_underflow,
axi_ar_prog_full,
axi_ar_prog_empty,
axi_r_injectsbiterr,
axi_r_injectdbiterr,
axi_r_prog_full_thresh,
axi_r_prog_empty_thresh,
axi_r_data_count,
axi_r_wr_data_count,
axi_r_rd_data_count,
axi_r_sbiterr,
axi_r_dbiterr,
axi_r_overflow,
axi_r_underflow,
axi_r_prog_full,
axi_r_prog_empty,
axis_injectsbiterr,
axis_injectdbiterr,
axis_prog_full_thresh,
axis_prog_empty_thresh,
axis_data_count,
axis_wr_data_count,
axis_rd_data_count,
axis_sbiterr,
axis_dbiterr,
axis_overflow,
axis_underflow,
axis_prog_full,
axis_prog_empty);
input backup;
input backup_marker;
input clk;
input rst;
input srst;
input wr_clk;
input wr_rst;
input rd_clk;
input rd_rst;
input [127:0]din;
input wr_en;
input rd_en;
input [8:0]prog_empty_thresh;
input [8:0]prog_empty_thresh_assert;
input [8:0]prog_empty_thresh_negate;
input [8:0]prog_full_thresh;
input [8:0]prog_full_thresh_assert;
input [8:0]prog_full_thresh_negate;
input int_clk;
input injectdbiterr;
input injectsbiterr;
input sleep;
output [127:0]dout;
output full;
output almost_full;
output wr_ack;
output overflow;
output empty;
output almost_empty;
output valid;
output underflow;
output [9:0]data_count;
output [9:0]rd_data_count;
output [9:0]wr_data_count;
output prog_full;
output prog_empty;
output sbiterr;
output dbiterr;
output wr_rst_busy;
output rd_rst_busy;
input m_aclk;
input s_aclk;
input s_aresetn;
input m_aclk_en;
input s_aclk_en;
input [0:0]s_axi_awid;
input [31:0]s_axi_awaddr;
input [7:0]s_axi_awlen;
input [2:0]s_axi_awsize;
input [1:0]s_axi_awburst;
input [0:0]s_axi_awlock;
input [3:0]s_axi_awcache;
input [2:0]s_axi_awprot;
input [3:0]s_axi_awqos;
input [3:0]s_axi_awregion;
input [0:0]s_axi_awuser;
input s_axi_awvalid;
output s_axi_awready;
input [0:0]s_axi_wid;
input [63:0]s_axi_wdata;
input [7:0]s_axi_wstrb;
input s_axi_wlast;
input [0:0]s_axi_wuser;
input s_axi_wvalid;
output s_axi_wready;
output [0:0]s_axi_bid;
output [1:0]s_axi_bresp;
output [0:0]s_axi_buser;
output s_axi_bvalid;
input s_axi_bready;
output [0:0]m_axi_awid;
output [31:0]m_axi_awaddr;
output [7:0]m_axi_awlen;
output [2:0]m_axi_awsize;
output [1:0]m_axi_awburst;
output [0:0]m_axi_awlock;
output [3:0]m_axi_awcache;
output [2:0]m_axi_awprot;
output [3:0]m_axi_awqos;
output [3:0]m_axi_awregion;
output [0:0]m_axi_awuser;
output m_axi_awvalid;
input m_axi_awready;
output [0:0]m_axi_wid;
output [63:0]m_axi_wdata;
output [7:0]m_axi_wstrb;
output m_axi_wlast;
output [0:0]m_axi_wuser;
output m_axi_wvalid;
input m_axi_wready;
input [0:0]m_axi_bid;
input [1:0]m_axi_bresp;
input [0:0]m_axi_buser;
input m_axi_bvalid;
output m_axi_bready;
input [0:0]s_axi_arid;
input [31:0]s_axi_araddr;
input [7:0]s_axi_arlen;
input [2:0]s_axi_arsize;
input [1:0]s_axi_arburst;
input [0:0]s_axi_arlock;
input [3:0]s_axi_arcache;
input [2:0]s_axi_arprot;
input [3:0]s_axi_arqos;
input [3:0]s_axi_arregion;
input [0:0]s_axi_aruser;
input s_axi_arvalid;
output s_axi_arready;
output [0:0]s_axi_rid;
output [63:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output s_axi_rlast;
output [0:0]s_axi_ruser;
output s_axi_rvalid;
input s_axi_rready;
output [0:0]m_axi_arid;
output [31:0]m_axi_araddr;
output [7:0]m_axi_arlen;
output [2:0]m_axi_arsize;
output [1:0]m_axi_arburst;
output [0:0]m_axi_arlock;
output [3:0]m_axi_arcache;
output [2:0]m_axi_arprot;
output [3:0]m_axi_arqos;
output [3:0]m_axi_arregion;
output [0:0]m_axi_aruser;
output m_axi_arvalid;
input m_axi_arready;
input [0:0]m_axi_rid;
input [63:0]m_axi_rdata;
input [1:0]m_axi_rresp;
input m_axi_rlast;
input [0:0]m_axi_ruser;
input m_axi_rvalid;
output m_axi_rready;
input s_axis_tvalid;
output s_axis_tready;
input [7:0]s_axis_tdata;
input [0:0]s_axis_tstrb;
input [0:0]s_axis_tkeep;
input s_axis_tlast;
input [0:0]s_axis_tid;
input [0:0]s_axis_tdest;
input [3:0]s_axis_tuser;
output m_axis_tvalid;
input m_axis_tready;
output [7:0]m_axis_tdata;
output [0:0]m_axis_tstrb;
output [0:0]m_axis_tkeep;
output m_axis_tlast;
output [0:0]m_axis_tid;
output [0:0]m_axis_tdest;
output [3:0]m_axis_tuser;
input axi_aw_injectsbiterr;
input axi_aw_injectdbiterr;
input [3:0]axi_aw_prog_full_thresh;
input [3:0]axi_aw_prog_empty_thresh;
output [4:0]axi_aw_data_count;
output [4:0]axi_aw_wr_data_count;
output [4:0]axi_aw_rd_data_count;
output axi_aw_sbiterr;
output axi_aw_dbiterr;
output axi_aw_overflow;
output axi_aw_underflow;
output axi_aw_prog_full;
output axi_aw_prog_empty;
input axi_w_injectsbiterr;
input axi_w_injectdbiterr;
input [9:0]axi_w_prog_full_thresh;
input [9:0]axi_w_prog_empty_thresh;
output [10:0]axi_w_data_count;
output [10:0]axi_w_wr_data_count;
output [10:0]axi_w_rd_data_count;
output axi_w_sbiterr;
output axi_w_dbiterr;
output axi_w_overflow;
output axi_w_underflow;
output axi_w_prog_full;
output axi_w_prog_empty;
input axi_b_injectsbiterr;
input axi_b_injectdbiterr;
input [3:0]axi_b_prog_full_thresh;
input [3:0]axi_b_prog_empty_thresh;
output [4:0]axi_b_data_count;
output [4:0]axi_b_wr_data_count;
output [4:0]axi_b_rd_data_count;
output axi_b_sbiterr;
output axi_b_dbiterr;
output axi_b_overflow;
output axi_b_underflow;
output axi_b_prog_full;
output axi_b_prog_empty;
input axi_ar_injectsbiterr;
input axi_ar_injectdbiterr;
input [3:0]axi_ar_prog_full_thresh;
input [3:0]axi_ar_prog_empty_thresh;
output [4:0]axi_ar_data_count;
output [4:0]axi_ar_wr_data_count;
output [4:0]axi_ar_rd_data_count;
output axi_ar_sbiterr;
output axi_ar_dbiterr;
output axi_ar_overflow;
output axi_ar_underflow;
output axi_ar_prog_full;
output axi_ar_prog_empty;
input axi_r_injectsbiterr;
input axi_r_injectdbiterr;
input [9:0]axi_r_prog_full_thresh;
input [9:0]axi_r_prog_empty_thresh;
output [10:0]axi_r_data_count;
output [10:0]axi_r_wr_data_count;
output [10:0]axi_r_rd_data_count;
output axi_r_sbiterr;
output axi_r_dbiterr;
output axi_r_overflow;
output axi_r_underflow;
output axi_r_prog_full;
output axi_r_prog_empty;
input axis_injectsbiterr;
input axis_injectdbiterr;
input [9:0]axis_prog_full_thresh;
input [9:0]axis_prog_empty_thresh;
output [10:0]axis_data_count;
output [10:0]axis_wr_data_count;
output [10:0]axis_rd_data_count;
output axis_sbiterr;
output axis_dbiterr;
output axis_overflow;
output axis_underflow;
output axis_prog_full;
output axis_prog_empty;
wire \<const0> ;
wire \<const1> ;
wire axi_ar_injectdbiterr;
wire axi_ar_injectsbiterr;
wire [3:0]axi_ar_prog_empty_thresh;
wire [3:0]axi_ar_prog_full_thresh;
wire axi_aw_injectdbiterr;
wire axi_aw_injectsbiterr;
wire [3:0]axi_aw_prog_empty_thresh;
wire [3:0]axi_aw_prog_full_thresh;
wire axi_b_injectdbiterr;
wire axi_b_injectsbiterr;
wire [3:0]axi_b_prog_empty_thresh;
wire [3:0]axi_b_prog_full_thresh;
wire axi_r_injectdbiterr;
wire axi_r_injectsbiterr;
wire [9:0]axi_r_prog_empty_thresh;
wire [9:0]axi_r_prog_full_thresh;
wire axi_w_injectdbiterr;
wire axi_w_injectsbiterr;
wire [9:0]axi_w_prog_empty_thresh;
wire [9:0]axi_w_prog_full_thresh;
wire axis_injectdbiterr;
wire axis_injectsbiterr;
wire [9:0]axis_prog_empty_thresh;
wire [9:0]axis_prog_full_thresh;
wire backup;
wire backup_marker;
wire clk;
wire [127:0]din;
wire [127:0]dout;
wire empty;
wire full;
wire injectdbiterr;
wire injectsbiterr;
wire int_clk;
wire m_aclk;
wire m_aclk_en;
wire m_axi_arready;
wire m_axi_awready;
wire [0:0]m_axi_bid;
wire [1:0]m_axi_bresp;
wire [0:0]m_axi_buser;
wire m_axi_bvalid;
wire [63:0]m_axi_rdata;
wire [0:0]m_axi_rid;
wire m_axi_rlast;
wire [1:0]m_axi_rresp;
wire [0:0]m_axi_ruser;
wire m_axi_rvalid;
wire m_axi_wready;
wire m_axis_tready;
wire [8:0]prog_empty_thresh;
wire [8:0]prog_empty_thresh_assert;
wire [8:0]prog_empty_thresh_negate;
wire [8:0]prog_full_thresh;
wire [8:0]prog_full_thresh_assert;
wire [8:0]prog_full_thresh_negate;
wire rd_clk;
wire rd_en;
wire rd_rst;
wire rst;
wire s_aclk;
wire s_aclk_en;
wire s_aresetn;
wire [31:0]s_axi_araddr;
wire [1:0]s_axi_arburst;
wire [3:0]s_axi_arcache;
wire [0:0]s_axi_arid;
wire [7:0]s_axi_arlen;
wire [0:0]s_axi_arlock;
wire [2:0]s_axi_arprot;
wire [3:0]s_axi_arqos;
wire [3:0]s_axi_arregion;
wire [2:0]s_axi_arsize;
wire [0:0]s_axi_aruser;
wire s_axi_arvalid;
wire [31:0]s_axi_awaddr;
wire [1:0]s_axi_awburst;
wire [3:0]s_axi_awcache;
wire [0:0]s_axi_awid;
wire [7:0]s_axi_awlen;
wire [0:0]s_axi_awlock;
wire [2:0]s_axi_awprot;
wire [3:0]s_axi_awqos;
wire [3:0]s_axi_awregion;
wire [2:0]s_axi_awsize;
wire [0:0]s_axi_awuser;
wire s_axi_awvalid;
wire s_axi_bready;
wire s_axi_rready;
wire [63:0]s_axi_wdata;
wire [0:0]s_axi_wid;
wire s_axi_wlast;
wire [7:0]s_axi_wstrb;
wire [0:0]s_axi_wuser;
wire s_axi_wvalid;
wire [7:0]s_axis_tdata;
wire [0:0]s_axis_tdest;
wire [0:0]s_axis_tid;
wire [0:0]s_axis_tkeep;
wire s_axis_tlast;
wire [0:0]s_axis_tstrb;
wire [3:0]s_axis_tuser;
wire s_axis_tvalid;
wire srst;
wire wr_clk;
wire wr_en;
wire wr_rst;
assign almost_empty = \<const0> ;
assign almost_full = \<const0> ;
assign axi_ar_data_count[4] = \<const0> ;
assign axi_ar_data_count[3] = \<const0> ;
assign axi_ar_data_count[2] = \<const0> ;
assign axi_ar_data_count[1] = \<const0> ;
assign axi_ar_data_count[0] = \<const0> ;
assign axi_ar_dbiterr = \<const0> ;
assign axi_ar_overflow = \<const0> ;
assign axi_ar_prog_empty = \<const1> ;
assign axi_ar_prog_full = \<const0> ;
assign axi_ar_rd_data_count[4] = \<const0> ;
assign axi_ar_rd_data_count[3] = \<const0> ;
assign axi_ar_rd_data_count[2] = \<const0> ;
assign axi_ar_rd_data_count[1] = \<const0> ;
assign axi_ar_rd_data_count[0] = \<const0> ;
assign axi_ar_sbiterr = \<const0> ;
assign axi_ar_underflow = \<const0> ;
assign axi_ar_wr_data_count[4] = \<const0> ;
assign axi_ar_wr_data_count[3] = \<const0> ;
assign axi_ar_wr_data_count[2] = \<const0> ;
assign axi_ar_wr_data_count[1] = \<const0> ;
assign axi_ar_wr_data_count[0] = \<const0> ;
assign axi_aw_data_count[4] = \<const0> ;
assign axi_aw_data_count[3] = \<const0> ;
assign axi_aw_data_count[2] = \<const0> ;
assign axi_aw_data_count[1] = \<const0> ;
assign axi_aw_data_count[0] = \<const0> ;
assign axi_aw_dbiterr = \<const0> ;
assign axi_aw_overflow = \<const0> ;
assign axi_aw_prog_empty = \<const1> ;
assign axi_aw_prog_full = \<const0> ;
assign axi_aw_rd_data_count[4] = \<const0> ;
assign axi_aw_rd_data_count[3] = \<const0> ;
assign axi_aw_rd_data_count[2] = \<const0> ;
assign axi_aw_rd_data_count[1] = \<const0> ;
assign axi_aw_rd_data_count[0] = \<const0> ;
assign axi_aw_sbiterr = \<const0> ;
assign axi_aw_underflow = \<const0> ;
assign axi_aw_wr_data_count[4] = \<const0> ;
assign axi_aw_wr_data_count[3] = \<const0> ;
assign axi_aw_wr_data_count[2] = \<const0> ;
assign axi_aw_wr_data_count[1] = \<const0> ;
assign axi_aw_wr_data_count[0] = \<const0> ;
assign axi_b_data_count[4] = \<const0> ;
assign axi_b_data_count[3] = \<const0> ;
assign axi_b_data_count[2] = \<const0> ;
assign axi_b_data_count[1] = \<const0> ;
assign axi_b_data_count[0] = \<const0> ;
assign axi_b_dbiterr = \<const0> ;
assign axi_b_overflow = \<const0> ;
assign axi_b_prog_empty = \<const1> ;
assign axi_b_prog_full = \<const0> ;
assign axi_b_rd_data_count[4] = \<const0> ;
assign axi_b_rd_data_count[3] = \<const0> ;
assign axi_b_rd_data_count[2] = \<const0> ;
assign axi_b_rd_data_count[1] = \<const0> ;
assign axi_b_rd_data_count[0] = \<const0> ;
assign axi_b_sbiterr = \<const0> ;
assign axi_b_underflow = \<const0> ;
assign axi_b_wr_data_count[4] = \<const0> ;
assign axi_b_wr_data_count[3] = \<const0> ;
assign axi_b_wr_data_count[2] = \<const0> ;
assign axi_b_wr_data_count[1] = \<const0> ;
assign axi_b_wr_data_count[0] = \<const0> ;
assign axi_r_data_count[10] = \<const0> ;
assign axi_r_data_count[9] = \<const0> ;
assign axi_r_data_count[8] = \<const0> ;
assign axi_r_data_count[7] = \<const0> ;
assign axi_r_data_count[6] = \<const0> ;
assign axi_r_data_count[5] = \<const0> ;
assign axi_r_data_count[4] = \<const0> ;
assign axi_r_data_count[3] = \<const0> ;
assign axi_r_data_count[2] = \<const0> ;
assign axi_r_data_count[1] = \<const0> ;
assign axi_r_data_count[0] = \<const0> ;
assign axi_r_dbiterr = \<const0> ;
assign axi_r_overflow = \<const0> ;
assign axi_r_prog_empty = \<const1> ;
assign axi_r_prog_full = \<const0> ;
assign axi_r_rd_data_count[10] = \<const0> ;
assign axi_r_rd_data_count[9] = \<const0> ;
assign axi_r_rd_data_count[8] = \<const0> ;
assign axi_r_rd_data_count[7] = \<const0> ;
assign axi_r_rd_data_count[6] = \<const0> ;
assign axi_r_rd_data_count[5] = \<const0> ;
assign axi_r_rd_data_count[4] = \<const0> ;
assign axi_r_rd_data_count[3] = \<const0> ;
assign axi_r_rd_data_count[2] = \<const0> ;
assign axi_r_rd_data_count[1] = \<const0> ;
assign axi_r_rd_data_count[0] = \<const0> ;
assign axi_r_sbiterr = \<const0> ;
assign axi_r_underflow = \<const0> ;
assign axi_r_wr_data_count[10] = \<const0> ;
assign axi_r_wr_data_count[9] = \<const0> ;
assign axi_r_wr_data_count[8] = \<const0> ;
assign axi_r_wr_data_count[7] = \<const0> ;
assign axi_r_wr_data_count[6] = \<const0> ;
assign axi_r_wr_data_count[5] = \<const0> ;
assign axi_r_wr_data_count[4] = \<const0> ;
assign axi_r_wr_data_count[3] = \<const0> ;
assign axi_r_wr_data_count[2] = \<const0> ;
assign axi_r_wr_data_count[1] = \<const0> ;
assign axi_r_wr_data_count[0] = \<const0> ;
assign axi_w_data_count[10] = \<const0> ;
assign axi_w_data_count[9] = \<const0> ;
assign axi_w_data_count[8] = \<const0> ;
assign axi_w_data_count[7] = \<const0> ;
assign axi_w_data_count[6] = \<const0> ;
assign axi_w_data_count[5] = \<const0> ;
assign axi_w_data_count[4] = \<const0> ;
assign axi_w_data_count[3] = \<const0> ;
assign axi_w_data_count[2] = \<const0> ;
assign axi_w_data_count[1] = \<const0> ;
assign axi_w_data_count[0] = \<const0> ;
assign axi_w_dbiterr = \<const0> ;
assign axi_w_overflow = \<const0> ;
assign axi_w_prog_empty = \<const1> ;
assign axi_w_prog_full = \<const0> ;
assign axi_w_rd_data_count[10] = \<const0> ;
assign axi_w_rd_data_count[9] = \<const0> ;
assign axi_w_rd_data_count[8] = \<const0> ;
assign axi_w_rd_data_count[7] = \<const0> ;
assign axi_w_rd_data_count[6] = \<const0> ;
assign axi_w_rd_data_count[5] = \<const0> ;
assign axi_w_rd_data_count[4] = \<const0> ;
assign axi_w_rd_data_count[3] = \<const0> ;
assign axi_w_rd_data_count[2] = \<const0> ;
assign axi_w_rd_data_count[1] = \<const0> ;
assign axi_w_rd_data_count[0] = \<const0> ;
assign axi_w_sbiterr = \<const0> ;
assign axi_w_underflow = \<const0> ;
assign axi_w_wr_data_count[10] = \<const0> ;
assign axi_w_wr_data_count[9] = \<const0> ;
assign axi_w_wr_data_count[8] = \<const0> ;
assign axi_w_wr_data_count[7] = \<const0> ;
assign axi_w_wr_data_count[6] = \<const0> ;
assign axi_w_wr_data_count[5] = \<const0> ;
assign axi_w_wr_data_count[4] = \<const0> ;
assign axi_w_wr_data_count[3] = \<const0> ;
assign axi_w_wr_data_count[2] = \<const0> ;
assign axi_w_wr_data_count[1] = \<const0> ;
assign axi_w_wr_data_count[0] = \<const0> ;
assign axis_data_count[10] = \<const0> ;
assign axis_data_count[9] = \<const0> ;
assign axis_data_count[8] = \<const0> ;
assign axis_data_count[7] = \<const0> ;
assign axis_data_count[6] = \<const0> ;
assign axis_data_count[5] = \<const0> ;
assign axis_data_count[4] = \<const0> ;
assign axis_data_count[3] = \<const0> ;
assign axis_data_count[2] = \<const0> ;
assign axis_data_count[1] = \<const0> ;
assign axis_data_count[0] = \<const0> ;
assign axis_dbiterr = \<const0> ;
assign axis_overflow = \<const0> ;
assign axis_prog_empty = \<const1> ;
assign axis_prog_full = \<const0> ;
assign axis_rd_data_count[10] = \<const0> ;
assign axis_rd_data_count[9] = \<const0> ;
assign axis_rd_data_count[8] = \<const0> ;
assign axis_rd_data_count[7] = \<const0> ;
assign axis_rd_data_count[6] = \<const0> ;
assign axis_rd_data_count[5] = \<const0> ;
assign axis_rd_data_count[4] = \<const0> ;
assign axis_rd_data_count[3] = \<const0> ;
assign axis_rd_data_count[2] = \<const0> ;
assign axis_rd_data_count[1] = \<const0> ;
assign axis_rd_data_count[0] = \<const0> ;
assign axis_sbiterr = \<const0> ;
assign axis_underflow = \<const0> ;
assign axis_wr_data_count[10] = \<const0> ;
assign axis_wr_data_count[9] = \<const0> ;
assign axis_wr_data_count[8] = \<const0> ;
assign axis_wr_data_count[7] = \<const0> ;
assign axis_wr_data_count[6] = \<const0> ;
assign axis_wr_data_count[5] = \<const0> ;
assign axis_wr_data_count[4] = \<const0> ;
assign axis_wr_data_count[3] = \<const0> ;
assign axis_wr_data_count[2] = \<const0> ;
assign axis_wr_data_count[1] = \<const0> ;
assign axis_wr_data_count[0] = \<const0> ;
assign data_count[9] = \<const0> ;
assign data_count[8] = \<const0> ;
assign data_count[7] = \<const0> ;
assign data_count[6] = \<const0> ;
assign data_count[5] = \<const0> ;
assign data_count[4] = \<const0> ;
assign data_count[3] = \<const0> ;
assign data_count[2] = \<const0> ;
assign data_count[1] = \<const0> ;
assign data_count[0] = \<const0> ;
assign dbiterr = \<const0> ;
assign m_axi_araddr[31] = \<const0> ;
assign m_axi_araddr[30] = \<const0> ;
assign m_axi_araddr[29] = \<const0> ;
assign m_axi_araddr[28] = \<const0> ;
assign m_axi_araddr[27] = \<const0> ;
assign m_axi_araddr[26] = \<const0> ;
assign m_axi_araddr[25] = \<const0> ;
assign m_axi_araddr[24] = \<const0> ;
assign m_axi_araddr[23] = \<const0> ;
assign m_axi_araddr[22] = \<const0> ;
assign m_axi_araddr[21] = \<const0> ;
assign m_axi_araddr[20] = \<const0> ;
assign m_axi_araddr[19] = \<const0> ;
assign m_axi_araddr[18] = \<const0> ;
assign m_axi_araddr[17] = \<const0> ;
assign m_axi_araddr[16] = \<const0> ;
assign m_axi_araddr[15] = \<const0> ;
assign m_axi_araddr[14] = \<const0> ;
assign m_axi_araddr[13] = \<const0> ;
assign m_axi_araddr[12] = \<const0> ;
assign m_axi_araddr[11] = \<const0> ;
assign m_axi_araddr[10] = \<const0> ;
assign m_axi_araddr[9] = \<const0> ;
assign m_axi_araddr[8] = \<const0> ;
assign m_axi_araddr[7] = \<const0> ;
assign m_axi_araddr[6] = \<const0> ;
assign m_axi_araddr[5] = \<const0> ;
assign m_axi_araddr[4] = \<const0> ;
assign m_axi_araddr[3] = \<const0> ;
assign m_axi_araddr[2] = \<const0> ;
assign m_axi_araddr[1] = \<const0> ;
assign m_axi_araddr[0] = \<const0> ;
assign m_axi_arburst[1] = \<const0> ;
assign m_axi_arburst[0] = \<const0> ;
assign m_axi_arcache[3] = \<const0> ;
assign m_axi_arcache[2] = \<const0> ;
assign m_axi_arcache[1] = \<const0> ;
assign m_axi_arcache[0] = \<const0> ;
assign m_axi_arid[0] = \<const0> ;
assign m_axi_arlen[7] = \<const0> ;
assign m_axi_arlen[6] = \<const0> ;
assign m_axi_arlen[5] = \<const0> ;
assign m_axi_arlen[4] = \<const0> ;
assign m_axi_arlen[3] = \<const0> ;
assign m_axi_arlen[2] = \<const0> ;
assign m_axi_arlen[1] = \<const0> ;
assign m_axi_arlen[0] = \<const0> ;
assign m_axi_arlock[0] = \<const0> ;
assign m_axi_arprot[2] = \<const0> ;
assign m_axi_arprot[1] = \<const0> ;
assign m_axi_arprot[0] = \<const0> ;
assign m_axi_arqos[3] = \<const0> ;
assign m_axi_arqos[2] = \<const0> ;
assign m_axi_arqos[1] = \<const0> ;
assign m_axi_arqos[0] = \<const0> ;
assign m_axi_arregion[3] = \<const0> ;
assign m_axi_arregion[2] = \<const0> ;
assign m_axi_arregion[1] = \<const0> ;
assign m_axi_arregion[0] = \<const0> ;
assign m_axi_arsize[2] = \<const0> ;
assign m_axi_arsize[1] = \<const0> ;
assign m_axi_arsize[0] = \<const0> ;
assign m_axi_aruser[0] = \<const0> ;
assign m_axi_arvalid = \<const0> ;
assign m_axi_awaddr[31] = \<const0> ;
assign m_axi_awaddr[30] = \<const0> ;
assign m_axi_awaddr[29] = \<const0> ;
assign m_axi_awaddr[28] = \<const0> ;
assign m_axi_awaddr[27] = \<const0> ;
assign m_axi_awaddr[26] = \<const0> ;
assign m_axi_awaddr[25] = \<const0> ;
assign m_axi_awaddr[24] = \<const0> ;
assign m_axi_awaddr[23] = \<const0> ;
assign m_axi_awaddr[22] = \<const0> ;
assign m_axi_awaddr[21] = \<const0> ;
assign m_axi_awaddr[20] = \<const0> ;
assign m_axi_awaddr[19] = \<const0> ;
assign m_axi_awaddr[18] = \<const0> ;
assign m_axi_awaddr[17] = \<const0> ;
assign m_axi_awaddr[16] = \<const0> ;
assign m_axi_awaddr[15] = \<const0> ;
assign m_axi_awaddr[14] = \<const0> ;
assign m_axi_awaddr[13] = \<const0> ;
assign m_axi_awaddr[12] = \<const0> ;
assign m_axi_awaddr[11] = \<const0> ;
assign m_axi_awaddr[10] = \<const0> ;
assign m_axi_awaddr[9] = \<const0> ;
assign m_axi_awaddr[8] = \<const0> ;
assign m_axi_awaddr[7] = \<const0> ;
assign m_axi_awaddr[6] = \<const0> ;
assign m_axi_awaddr[5] = \<const0> ;
assign m_axi_awaddr[4] = \<const0> ;
assign m_axi_awaddr[3] = \<const0> ;
assign m_axi_awaddr[2] = \<const0> ;
assign m_axi_awaddr[1] = \<const0> ;
assign m_axi_awaddr[0] = \<const0> ;
assign m_axi_awburst[1] = \<const0> ;
assign m_axi_awburst[0] = \<const0> ;
assign m_axi_awcache[3] = \<const0> ;
assign m_axi_awcache[2] = \<const0> ;
assign m_axi_awcache[1] = \<const0> ;
assign m_axi_awcache[0] = \<const0> ;
assign m_axi_awid[0] = \<const0> ;
assign m_axi_awlen[7] = \<const0> ;
assign m_axi_awlen[6] = \<const0> ;
assign m_axi_awlen[5] = \<const0> ;
assign m_axi_awlen[4] = \<const0> ;
assign m_axi_awlen[3] = \<const0> ;
assign m_axi_awlen[2] = \<const0> ;
assign m_axi_awlen[1] = \<const0> ;
assign m_axi_awlen[0] = \<const0> ;
assign m_axi_awlock[0] = \<const0> ;
assign m_axi_awprot[2] = \<const0> ;
assign m_axi_awprot[1] = \<const0> ;
assign m_axi_awprot[0] = \<const0> ;
assign m_axi_awqos[3] = \<const0> ;
assign m_axi_awqos[2] = \<const0> ;
assign m_axi_awqos[1] = \<const0> ;
assign m_axi_awqos[0] = \<const0> ;
assign m_axi_awregion[3] = \<const0> ;
assign m_axi_awregion[2] = \<const0> ;
assign m_axi_awregion[1] = \<const0> ;
assign m_axi_awregion[0] = \<const0> ;
assign m_axi_awsize[2] = \<const0> ;
assign m_axi_awsize[1] = \<const0> ;
assign m_axi_awsize[0] = \<const0> ;
assign m_axi_awuser[0] = \<const0> ;
assign m_axi_awvalid = \<const0> ;
assign m_axi_bready = \<const0> ;
assign m_axi_rready = \<const0> ;
assign m_axi_wdata[63] = \<const0> ;
assign m_axi_wdata[62] = \<const0> ;
assign m_axi_wdata[61] = \<const0> ;
assign m_axi_wdata[60] = \<const0> ;
assign m_axi_wdata[59] = \<const0> ;
assign m_axi_wdata[58] = \<const0> ;
assign m_axi_wdata[57] = \<const0> ;
assign m_axi_wdata[56] = \<const0> ;
assign m_axi_wdata[55] = \<const0> ;
assign m_axi_wdata[54] = \<const0> ;
assign m_axi_wdata[53] = \<const0> ;
assign m_axi_wdata[52] = \<const0> ;
assign m_axi_wdata[51] = \<const0> ;
assign m_axi_wdata[50] = \<const0> ;
assign m_axi_wdata[49] = \<const0> ;
assign m_axi_wdata[48] = \<const0> ;
assign m_axi_wdata[47] = \<const0> ;
assign m_axi_wdata[46] = \<const0> ;
assign m_axi_wdata[45] = \<const0> ;
assign m_axi_wdata[44] = \<const0> ;
assign m_axi_wdata[43] = \<const0> ;
assign m_axi_wdata[42] = \<const0> ;
assign m_axi_wdata[41] = \<const0> ;
assign m_axi_wdata[40] = \<const0> ;
assign m_axi_wdata[39] = \<const0> ;
assign m_axi_wdata[38] = \<const0> ;
assign m_axi_wdata[37] = \<const0> ;
assign m_axi_wdata[36] = \<const0> ;
assign m_axi_wdata[35] = \<const0> ;
assign m_axi_wdata[34] = \<const0> ;
assign m_axi_wdata[33] = \<const0> ;
assign m_axi_wdata[32] = \<const0> ;
assign m_axi_wdata[31] = \<const0> ;
assign m_axi_wdata[30] = \<const0> ;
assign m_axi_wdata[29] = \<const0> ;
assign m_axi_wdata[28] = \<const0> ;
assign m_axi_wdata[27] = \<const0> ;
assign m_axi_wdata[26] = \<const0> ;
assign m_axi_wdata[25] = \<const0> ;
assign m_axi_wdata[24] = \<const0> ;
assign m_axi_wdata[23] = \<const0> ;
assign m_axi_wdata[22] = \<const0> ;
assign m_axi_wdata[21] = \<const0> ;
assign m_axi_wdata[20] = \<const0> ;
assign m_axi_wdata[19] = \<const0> ;
assign m_axi_wdata[18] = \<const0> ;
assign m_axi_wdata[17] = \<const0> ;
assign m_axi_wdata[16] = \<const0> ;
assign m_axi_wdata[15] = \<const0> ;
assign m_axi_wdata[14] = \<const0> ;
assign m_axi_wdata[13] = \<const0> ;
assign m_axi_wdata[12] = \<const0> ;
assign m_axi_wdata[11] = \<const0> ;
assign m_axi_wdata[10] = \<const0> ;
assign m_axi_wdata[9] = \<const0> ;
assign m_axi_wdata[8] = \<const0> ;
assign m_axi_wdata[7] = \<const0> ;
assign m_axi_wdata[6] = \<const0> ;
assign m_axi_wdata[5] = \<const0> ;
assign m_axi_wdata[4] = \<const0> ;
assign m_axi_wdata[3] = \<const0> ;
assign m_axi_wdata[2] = \<const0> ;
assign m_axi_wdata[1] = \<const0> ;
assign m_axi_wdata[0] = \<const0> ;
assign m_axi_wid[0] = \<const0> ;
assign m_axi_wlast = \<const0> ;
assign m_axi_wstrb[7] = \<const0> ;
assign m_axi_wstrb[6] = \<const0> ;
assign m_axi_wstrb[5] = \<const0> ;
assign m_axi_wstrb[4] = \<const0> ;
assign m_axi_wstrb[3] = \<const0> ;
assign m_axi_wstrb[2] = \<const0> ;
assign m_axi_wstrb[1] = \<const0> ;
assign m_axi_wstrb[0] = \<const0> ;
assign m_axi_wuser[0] = \<const0> ;
assign m_axi_wvalid = \<const0> ;
assign m_axis_tdata[7] = \<const0> ;
assign m_axis_tdata[6] = \<const0> ;
assign m_axis_tdata[5] = \<const0> ;
assign m_axis_tdata[4] = \<const0> ;
assign m_axis_tdata[3] = \<const0> ;
assign m_axis_tdata[2] = \<const0> ;
assign m_axis_tdata[1] = \<const0> ;
assign m_axis_tdata[0] = \<const0> ;
assign m_axis_tdest[0] = \<const0> ;
assign m_axis_tid[0] = \<const0> ;
assign m_axis_tkeep[0] = \<const0> ;
assign m_axis_tlast = \<const0> ;
assign m_axis_tstrb[0] = \<const0> ;
assign m_axis_tuser[3] = \<const0> ;
assign m_axis_tuser[2] = \<const0> ;
assign m_axis_tuser[1] = \<const0> ;
assign m_axis_tuser[0] = \<const0> ;
assign m_axis_tvalid = \<const0> ;
assign overflow = \<const0> ;
assign prog_empty = \<const0> ;
assign prog_full = \<const0> ;
assign rd_data_count[9] = \<const0> ;
assign rd_data_count[8] = \<const0> ;
assign rd_data_count[7] = \<const0> ;
assign rd_data_count[6] = \<const0> ;
assign rd_data_count[5] = \<const0> ;
assign rd_data_count[4] = \<const0> ;
assign rd_data_count[3] = \<const0> ;
assign rd_data_count[2] = \<const0> ;
assign rd_data_count[1] = \<const0> ;
assign rd_data_count[0] = \<const0> ;
assign rd_rst_busy = \<const0> ;
assign s_axi_arready = \<const0> ;
assign s_axi_awready = \<const0> ;
assign s_axi_bid[0] = \<const0> ;
assign s_axi_bresp[1] = \<const0> ;
assign s_axi_bresp[0] = \<const0> ;
assign s_axi_buser[0] = \<const0> ;
assign s_axi_bvalid = \<const0> ;
assign s_axi_rdata[63] = \<const0> ;
assign s_axi_rdata[62] = \<const0> ;
assign s_axi_rdata[61] = \<const0> ;
assign s_axi_rdata[60] = \<const0> ;
assign s_axi_rdata[59] = \<const0> ;
assign s_axi_rdata[58] = \<const0> ;
assign s_axi_rdata[57] = \<const0> ;
assign s_axi_rdata[56] = \<const0> ;
assign s_axi_rdata[55] = \<const0> ;
assign s_axi_rdata[54] = \<const0> ;
assign s_axi_rdata[53] = \<const0> ;
assign s_axi_rdata[52] = \<const0> ;
assign s_axi_rdata[51] = \<const0> ;
assign s_axi_rdata[50] = \<const0> ;
assign s_axi_rdata[49] = \<const0> ;
assign s_axi_rdata[48] = \<const0> ;
assign s_axi_rdata[47] = \<const0> ;
assign s_axi_rdata[46] = \<const0> ;
assign s_axi_rdata[45] = \<const0> ;
assign s_axi_rdata[44] = \<const0> ;
assign s_axi_rdata[43] = \<const0> ;
assign s_axi_rdata[42] = \<const0> ;
assign s_axi_rdata[41] = \<const0> ;
assign s_axi_rdata[40] = \<const0> ;
assign s_axi_rdata[39] = \<const0> ;
assign s_axi_rdata[38] = \<const0> ;
assign s_axi_rdata[37] = \<const0> ;
assign s_axi_rdata[36] = \<const0> ;
assign s_axi_rdata[35] = \<const0> ;
assign s_axi_rdata[34] = \<const0> ;
assign s_axi_rdata[33] = \<const0> ;
assign s_axi_rdata[32] = \<const0> ;
assign s_axi_rdata[31] = \<const0> ;
assign s_axi_rdata[30] = \<const0> ;
assign s_axi_rdata[29] = \<const0> ;
assign s_axi_rdata[28] = \<const0> ;
assign s_axi_rdata[27] = \<const0> ;
assign s_axi_rdata[26] = \<const0> ;
assign s_axi_rdata[25] = \<const0> ;
assign s_axi_rdata[24] = \<const0> ;
assign s_axi_rdata[23] = \<const0> ;
assign s_axi_rdata[22] = \<const0> ;
assign s_axi_rdata[21] = \<const0> ;
assign s_axi_rdata[20] = \<const0> ;
assign s_axi_rdata[19] = \<const0> ;
assign s_axi_rdata[18] = \<const0> ;
assign s_axi_rdata[17] = \<const0> ;
assign s_axi_rdata[16] = \<const0> ;
assign s_axi_rdata[15] = \<const0> ;
assign s_axi_rdata[14] = \<const0> ;
assign s_axi_rdata[13] = \<const0> ;
assign s_axi_rdata[12] = \<const0> ;
assign s_axi_rdata[11] = \<const0> ;
assign s_axi_rdata[10] = \<const0> ;
assign s_axi_rdata[9] = \<const0> ;
assign s_axi_rdata[8] = \<const0> ;
assign s_axi_rdata[7] = \<const0> ;
assign s_axi_rdata[6] = \<const0> ;
assign s_axi_rdata[5] = \<const0> ;
assign s_axi_rdata[4] = \<const0> ;
assign s_axi_rdata[3] = \<const0> ;
assign s_axi_rdata[2] = \<const0> ;
assign s_axi_rdata[1] = \<const0> ;
assign s_axi_rdata[0] = \<const0> ;
assign s_axi_rid[0] = \<const0> ;
assign s_axi_rlast = \<const0> ;
assign s_axi_rresp[1] = \<const0> ;
assign s_axi_rresp[0] = \<const0> ;
assign s_axi_ruser[0] = \<const0> ;
assign s_axi_rvalid = \<const0> ;
assign s_axi_wready = \<const0> ;
assign s_axis_tready = \<const0> ;
assign sbiterr = \<const0> ;
assign underflow = \<const0> ;
assign valid = \<const0> ;
assign wr_ack = \<const0> ;
assign wr_data_count[9] = \<const0> ;
assign wr_data_count[8] = \<const0> ;
assign wr_data_count[7] = \<const0> ;
assign wr_data_count[6] = \<const0> ;
assign wr_data_count[5] = \<const0> ;
assign wr_data_count[4] = \<const0> ;
assign wr_data_count[3] = \<const0> ;
assign wr_data_count[2] = \<const0> ;
assign wr_data_count[1] = \<const0> ;
assign wr_data_count[0] = \<const0> ;
assign wr_rst_busy = \<const0> ;
GND GND
(.G(\<const0> ));
VCC VCC
(.P(\<const1> ));
pcie_recv_fifo_fifo_generator_v13_0_1_synth inst_fifo_gen
(.clk(clk),
.din(din),
.dout(dout),
.empty(empty),
.full(full),
.rd_en(rd_en),
.s_aclk(s_aclk),
.s_aresetn(s_aresetn),
.srst(srst),
.wr_en(wr_en));
endmodule |
module pcie_recv_fifo_fifo_generator_v13_0_1_synth
(dout,
empty,
full,
clk,
srst,
din,
s_aclk,
rd_en,
wr_en,
s_aresetn);
output [127:0]dout;
output empty;
output full;
input clk;
input srst;
input [127:0]din;
input s_aclk;
input rd_en;
input wr_en;
input s_aresetn;
wire clk;
wire [127:0]din;
wire [127:0]dout;
wire empty;
wire full;
wire rd_en;
wire s_aclk;
wire s_aresetn;
wire srst;
wire wr_en;
pcie_recv_fifo_fifo_generator_top \gconvfifo.rf
(.clk(clk),
.din(din),
.dout(dout),
.empty(empty),
.full(full),
.rd_en(rd_en),
.srst(srst),
.wr_en(wr_en));
pcie_recv_fifo_reset_blk_ramfifo \reset_gen_cc.rstblk_cc
(.s_aclk(s_aclk),
.s_aresetn(s_aresetn));
endmodule |
module pcie_recv_fifo_memory
(dout,
clk,
tmp_ram_rd_en,
ram_full_fb_i_reg,
srst,
\gc0.count_d1_reg[8] ,
\gcc0.gc0.count_d1_reg[8] ,
din,
E);
output [127:0]dout;
input clk;
input tmp_ram_rd_en;
input [0:0]ram_full_fb_i_reg;
input srst;
input [8:0]\gc0.count_d1_reg[8] ;
input [8:0]\gcc0.gc0.count_d1_reg[8] ;
input [127:0]din;
input [0:0]E;
wire [0:0]E;
wire clk;
wire [127:0]din;
wire [127:0]dout;
wire [127:0]doutb;
wire [8:0]\gc0.count_d1_reg[8] ;
wire [8:0]\gcc0.gc0.count_d1_reg[8] ;
wire [0:0]ram_full_fb_i_reg;
wire srst;
wire tmp_ram_rd_en;
pcie_recv_fifo_blk_mem_gen_v8_3_1 \gbm.gbmg.gbmga.ngecc.bmg
(.D(doutb),
.clk(clk),
.din(din),
.\gc0.count_d1_reg[8] (\gc0.count_d1_reg[8] ),
.\gcc0.gc0.count_d1_reg[8] (\gcc0.gc0.count_d1_reg[8] ),
.ram_full_fb_i_reg(ram_full_fb_i_reg),
.srst(srst),
.tmp_ram_rd_en(tmp_ram_rd_en));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[0]
(.C(clk),
.CE(E),
.D(doutb[0]),
.Q(dout[0]),
.R(srst));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[100]
(.C(clk),
.CE(E),
.D(doutb[100]),
.Q(dout[100]),
.R(srst));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[101]
(.C(clk),
.CE(E),
.D(doutb[101]),
.Q(dout[101]),
.R(srst));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[102]
(.C(clk),
.CE(E),
.D(doutb[102]),
.Q(dout[102]),
.R(srst));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[103]
(.C(clk),
.CE(E),
.D(doutb[103]),
.Q(dout[103]),
.R(srst));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[104]
(.C(clk),
.CE(E),
.D(doutb[104]),
.Q(dout[104]),
.R(srst));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[105]
(.C(clk),
.CE(E),
.D(doutb[105]),
.Q(dout[105]),
.R(srst));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[106]
(.C(clk),
.CE(E),
.D(doutb[106]),
.Q(dout[106]),
.R(srst));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[107]
(.C(clk),
.CE(E),
.D(doutb[107]),
.Q(dout[107]),
.R(srst));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[108]
(.C(clk),
.CE(E),
.D(doutb[108]),
.Q(dout[108]),
.R(srst));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[109]
(.C(clk),
.CE(E),
.D(doutb[109]),
.Q(dout[109]),
.R(srst));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[10]
(.C(clk),
.CE(E),
.D(doutb[10]),
.Q(dout[10]),
.R(srst));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[110]
(.C(clk),
.CE(E),
.D(doutb[110]),
.Q(dout[110]),
.R(srst));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[111]
(.C(clk),
.CE(E),
.D(doutb[111]),
.Q(dout[111]),
.R(srst));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[112]
(.C(clk),
.CE(E),
.D(doutb[112]),
.Q(dout[112]),
.R(srst));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[113]
(.C(clk),
.CE(E),
.D(doutb[113]),
.Q(dout[113]),
.R(srst));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[114]
(.C(clk),
.CE(E),
.D(doutb[114]),
.Q(dout[114]),
.R(srst));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[115]
(.C(clk),
.CE(E),
.D(doutb[115]),
.Q(dout[115]),
.R(srst));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[116]
(.C(clk),
.CE(E),
.D(doutb[116]),
.Q(dout[116]),
.R(srst));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[117]
(.C(clk),
.CE(E),
.D(doutb[117]),
.Q(dout[117]),
.R(srst));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[118]
(.C(clk),
.CE(E),
.D(doutb[118]),
.Q(dout[118]),
.R(srst));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[119]
(.C(clk),
.CE(E),
.D(doutb[119]),
.Q(dout[119]),
.R(srst));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[11]
(.C(clk),
.CE(E),
.D(doutb[11]),
.Q(dout[11]),
.R(srst));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[120]
(.C(clk),
.CE(E),
.D(doutb[120]),
.Q(dout[120]),
.R(srst));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[121]
(.C(clk),
.CE(E),
.D(doutb[121]),
.Q(dout[121]),
.R(srst));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[122]
(.C(clk),
.CE(E),
.D(doutb[122]),
.Q(dout[122]),
.R(srst));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[123]
(.C(clk),
.CE(E),
.D(doutb[123]),
.Q(dout[123]),
.R(srst));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[124]
(.C(clk),
.CE(E),
.D(doutb[124]),
.Q(dout[124]),
.R(srst));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[125]
(.C(clk),
.CE(E),
.D(doutb[125]),
.Q(dout[125]),
.R(srst));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[126]
(.C(clk),
.CE(E),
.D(doutb[126]),
.Q(dout[126]),
.R(srst));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[127]
(.C(clk),
.CE(E),
.D(doutb[127]),
.Q(dout[127]),
.R(srst));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[12]
(.C(clk),
.CE(E),
.D(doutb[12]),
.Q(dout[12]),
.R(srst));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[13]
(.C(clk),
.CE(E),
.D(doutb[13]),
.Q(dout[13]),
.R(srst));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[14]
(.C(clk),
.CE(E),
.D(doutb[14]),
.Q(dout[14]),
.R(srst));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[15]
(.C(clk),
.CE(E),
.D(doutb[15]),
.Q(dout[15]),
.R(srst));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[16]
(.C(clk),
.CE(E),
.D(doutb[16]),
.Q(dout[16]),
.R(srst));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[17]
(.C(clk),
.CE(E),
.D(doutb[17]),
.Q(dout[17]),
.R(srst));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[18]
(.C(clk),
.CE(E),
.D(doutb[18]),
.Q(dout[18]),
.R(srst));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[19]
(.C(clk),
.CE(E),
.D(doutb[19]),
.Q(dout[19]),
.R(srst));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[1]
(.C(clk),
.CE(E),
.D(doutb[1]),
.Q(dout[1]),
.R(srst));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[20]
(.C(clk),
.CE(E),
.D(doutb[20]),
.Q(dout[20]),
.R(srst));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[21]
(.C(clk),
.CE(E),
.D(doutb[21]),
.Q(dout[21]),
.R(srst));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[22]
(.C(clk),
.CE(E),
.D(doutb[22]),
.Q(dout[22]),
.R(srst));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[23]
(.C(clk),
.CE(E),
.D(doutb[23]),
.Q(dout[23]),
.R(srst));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[24]
(.C(clk),
.CE(E),
.D(doutb[24]),
.Q(dout[24]),
.R(srst));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[25]
(.C(clk),
.CE(E),
.D(doutb[25]),
.Q(dout[25]),
.R(srst));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[26]
(.C(clk),
.CE(E),
.D(doutb[26]),
.Q(dout[26]),
.R(srst));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[27]
(.C(clk),
.CE(E),
.D(doutb[27]),
.Q(dout[27]),
.R(srst));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[28]
(.C(clk),
.CE(E),
.D(doutb[28]),
.Q(dout[28]),
.R(srst));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[29]
(.C(clk),
.CE(E),
.D(doutb[29]),
.Q(dout[29]),
.R(srst));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[2]
(.C(clk),
.CE(E),
.D(doutb[2]),
.Q(dout[2]),
.R(srst));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[30]
(.C(clk),
.CE(E),
.D(doutb[30]),
.Q(dout[30]),
.R(srst));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[31]
(.C(clk),
.CE(E),
.D(doutb[31]),
.Q(dout[31]),
.R(srst));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[32]
(.C(clk),
.CE(E),
.D(doutb[32]),
.Q(dout[32]),
.R(srst));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[33]
(.C(clk),
.CE(E),
.D(doutb[33]),
.Q(dout[33]),
.R(srst));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[34]
(.C(clk),
.CE(E),
.D(doutb[34]),
.Q(dout[34]),
.R(srst));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[35]
(.C(clk),
.CE(E),
.D(doutb[35]),
.Q(dout[35]),
.R(srst));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[36]
(.C(clk),
.CE(E),
.D(doutb[36]),
.Q(dout[36]),
.R(srst));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[37]
(.C(clk),
.CE(E),
.D(doutb[37]),
.Q(dout[37]),
.R(srst));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[38]
(.C(clk),
.CE(E),
.D(doutb[38]),
.Q(dout[38]),
.R(srst));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[39]
(.C(clk),
.CE(E),
.D(doutb[39]),
.Q(dout[39]),
.R(srst));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[3]
(.C(clk),
.CE(E),
.D(doutb[3]),
.Q(dout[3]),
.R(srst));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[40]
(.C(clk),
.CE(E),
.D(doutb[40]),
.Q(dout[40]),
.R(srst));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[41]
(.C(clk),
.CE(E),
.D(doutb[41]),
.Q(dout[41]),
.R(srst));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[42]
(.C(clk),
.CE(E),
.D(doutb[42]),
.Q(dout[42]),
.R(srst));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[43]
(.C(clk),
.CE(E),
.D(doutb[43]),
.Q(dout[43]),
.R(srst));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[44]
(.C(clk),
.CE(E),
.D(doutb[44]),
.Q(dout[44]),
.R(srst));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[45]
(.C(clk),
.CE(E),
.D(doutb[45]),
.Q(dout[45]),
.R(srst));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[46]
(.C(clk),
.CE(E),
.D(doutb[46]),
.Q(dout[46]),
.R(srst));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[47]
(.C(clk),
.CE(E),
.D(doutb[47]),
.Q(dout[47]),
.R(srst));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[48]
(.C(clk),
.CE(E),
.D(doutb[48]),
.Q(dout[48]),
.R(srst));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[49]
(.C(clk),
.CE(E),
.D(doutb[49]),
.Q(dout[49]),
.R(srst));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[4]
(.C(clk),
.CE(E),
.D(doutb[4]),
.Q(dout[4]),
.R(srst));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[50]
(.C(clk),
.CE(E),
.D(doutb[50]),
.Q(dout[50]),
.R(srst));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[51]
(.C(clk),
.CE(E),
.D(doutb[51]),
.Q(dout[51]),
.R(srst));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[52]
(.C(clk),
.CE(E),
.D(doutb[52]),
.Q(dout[52]),
.R(srst));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[53]
(.C(clk),
.CE(E),
.D(doutb[53]),
.Q(dout[53]),
.R(srst));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[54]
(.C(clk),
.CE(E),
.D(doutb[54]),
.Q(dout[54]),
.R(srst));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[55]
(.C(clk),
.CE(E),
.D(doutb[55]),
.Q(dout[55]),
.R(srst));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[56]
(.C(clk),
.CE(E),
.D(doutb[56]),
.Q(dout[56]),
.R(srst));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[57]
(.C(clk),
.CE(E),
.D(doutb[57]),
.Q(dout[57]),
.R(srst));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[58]
(.C(clk),
.CE(E),
.D(doutb[58]),
.Q(dout[58]),
.R(srst));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[59]
(.C(clk),
.CE(E),
.D(doutb[59]),
.Q(dout[59]),
.R(srst));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[5]
(.C(clk),
.CE(E),
.D(doutb[5]),
.Q(dout[5]),
.R(srst));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[60]
(.C(clk),
.CE(E),
.D(doutb[60]),
.Q(dout[60]),
.R(srst));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[61]
(.C(clk),
.CE(E),
.D(doutb[61]),
.Q(dout[61]),
.R(srst));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[62]
(.C(clk),
.CE(E),
.D(doutb[62]),
.Q(dout[62]),
.R(srst));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[63]
(.C(clk),
.CE(E),
.D(doutb[63]),
.Q(dout[63]),
.R(srst));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[64]
(.C(clk),
.CE(E),
.D(doutb[64]),
.Q(dout[64]),
.R(srst));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[65]
(.C(clk),
.CE(E),
.D(doutb[65]),
.Q(dout[65]),
.R(srst));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[66]
(.C(clk),
.CE(E),
.D(doutb[66]),
.Q(dout[66]),
.R(srst));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[67]
(.C(clk),
.CE(E),
.D(doutb[67]),
.Q(dout[67]),
.R(srst));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[68]
(.C(clk),
.CE(E),
.D(doutb[68]),
.Q(dout[68]),
.R(srst));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[69]
(.C(clk),
.CE(E),
.D(doutb[69]),
.Q(dout[69]),
.R(srst));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[6]
(.C(clk),
.CE(E),
.D(doutb[6]),
.Q(dout[6]),
.R(srst));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[70]
(.C(clk),
.CE(E),
.D(doutb[70]),
.Q(dout[70]),
.R(srst));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[71]
(.C(clk),
.CE(E),
.D(doutb[71]),
.Q(dout[71]),
.R(srst));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[72]
(.C(clk),
.CE(E),
.D(doutb[72]),
.Q(dout[72]),
.R(srst));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[73]
(.C(clk),
.CE(E),
.D(doutb[73]),
.Q(dout[73]),
.R(srst));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[74]
(.C(clk),
.CE(E),
.D(doutb[74]),
.Q(dout[74]),
.R(srst));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[75]
(.C(clk),
.CE(E),
.D(doutb[75]),
.Q(dout[75]),
.R(srst));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[76]
(.C(clk),
.CE(E),
.D(doutb[76]),
.Q(dout[76]),
.R(srst));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[77]
(.C(clk),
.CE(E),
.D(doutb[77]),
.Q(dout[77]),
.R(srst));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[78]
(.C(clk),
.CE(E),
.D(doutb[78]),
.Q(dout[78]),
.R(srst));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[79]
(.C(clk),
.CE(E),
.D(doutb[79]),
.Q(dout[79]),
.R(srst));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[7]
(.C(clk),
.CE(E),
.D(doutb[7]),
.Q(dout[7]),
.R(srst));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[80]
(.C(clk),
.CE(E),
.D(doutb[80]),
.Q(dout[80]),
.R(srst));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[81]
(.C(clk),
.CE(E),
.D(doutb[81]),
.Q(dout[81]),
.R(srst));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[82]
(.C(clk),
.CE(E),
.D(doutb[82]),
.Q(dout[82]),
.R(srst));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[83]
(.C(clk),
.CE(E),
.D(doutb[83]),
.Q(dout[83]),
.R(srst));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[84]
(.C(clk),
.CE(E),
.D(doutb[84]),
.Q(dout[84]),
.R(srst));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[85]
(.C(clk),
.CE(E),
.D(doutb[85]),
.Q(dout[85]),
.R(srst));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[86]
(.C(clk),
.CE(E),
.D(doutb[86]),
.Q(dout[86]),
.R(srst));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[87]
(.C(clk),
.CE(E),
.D(doutb[87]),
.Q(dout[87]),
.R(srst));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[88]
(.C(clk),
.CE(E),
.D(doutb[88]),
.Q(dout[88]),
.R(srst));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[89]
(.C(clk),
.CE(E),
.D(doutb[89]),
.Q(dout[89]),
.R(srst));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[8]
(.C(clk),
.CE(E),
.D(doutb[8]),
.Q(dout[8]),
.R(srst));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[90]
(.C(clk),
.CE(E),
.D(doutb[90]),
.Q(dout[90]),
.R(srst));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[91]
(.C(clk),
.CE(E),
.D(doutb[91]),
.Q(dout[91]),
.R(srst));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[92]
(.C(clk),
.CE(E),
.D(doutb[92]),
.Q(dout[92]),
.R(srst));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[93]
(.C(clk),
.CE(E),
.D(doutb[93]),
.Q(dout[93]),
.R(srst));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[94]
(.C(clk),
.CE(E),
.D(doutb[94]),
.Q(dout[94]),
.R(srst));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[95]
(.C(clk),
.CE(E),
.D(doutb[95]),
.Q(dout[95]),
.R(srst));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[96]
(.C(clk),
.CE(E),
.D(doutb[96]),
.Q(dout[96]),
.R(srst));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[97]
(.C(clk),
.CE(E),
.D(doutb[97]),
.Q(dout[97]),
.R(srst));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[98]
(.C(clk),
.CE(E),
.D(doutb[98]),
.Q(dout[98]),
.R(srst));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[99]
(.C(clk),
.CE(E),
.D(doutb[99]),
.Q(dout[99]),
.R(srst));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[9]
(.C(clk),
.CE(E),
.D(doutb[9]),
.Q(dout[9]),
.R(srst));
endmodule |
module pcie_recv_fifo_rd_bin_cntr
(Q,
ram_full_i_reg,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram ,
v1_reg_0,
v1_reg,
ram_empty_fb_i_reg,
\gcc0.gc0.count_d1_reg[8] ,
\gcc0.gc0.count_reg[8] ,
srst,
E,
clk);
output [7:0]Q;
output [0:0]ram_full_i_reg;
output [8:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram ;
output [0:0]v1_reg_0;
output [4:0]v1_reg;
output ram_empty_fb_i_reg;
input [0:0]\gcc0.gc0.count_d1_reg[8] ;
input [8:0]\gcc0.gc0.count_reg[8] ;
input srst;
input [0:0]E;
input clk;
wire [8:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram ;
wire [0:0]E;
wire [7:0]Q;
wire clk;
wire \gc0.count[8]_i_2_n_0 ;
wire [0:0]\gcc0.gc0.count_d1_reg[8] ;
wire [8:0]\gcc0.gc0.count_reg[8] ;
wire [8:0]plusOp;
wire ram_empty_fb_i_reg;
wire [0:0]ram_full_i_reg;
wire [8:8]rd_pntr_plus1;
wire srst;
wire [4:0]v1_reg;
wire [0:0]v1_reg_0;
LUT1 #(
.INIT(2'h1))
\gc0.count[0]_i_1
(.I0(Q[0]),
.O(plusOp[0]));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT2 #(
.INIT(4'h6))
\gc0.count[1]_i_1
(.I0(Q[0]),
.I1(Q[1]),
.O(plusOp[1]));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT3 #(
.INIT(8'h78))
\gc0.count[2]_i_1
(.I0(Q[0]),
.I1(Q[1]),
.I2(Q[2]),
.O(plusOp[2]));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT4 #(
.INIT(16'h7F80))
\gc0.count[3]_i_1
(.I0(Q[1]),
.I1(Q[0]),
.I2(Q[2]),
.I3(Q[3]),
.O(plusOp[3]));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT5 #(
.INIT(32'h7FFF8000))
\gc0.count[4]_i_1
(.I0(Q[2]),
.I1(Q[0]),
.I2(Q[1]),
.I3(Q[3]),
.I4(Q[4]),
.O(plusOp[4]));
LUT6 #(
.INIT(64'h7FFFFFFF80000000))
\gc0.count[5]_i_1
(.I0(Q[3]),
.I1(Q[1]),
.I2(Q[0]),
.I3(Q[2]),
.I4(Q[4]),
.I5(Q[5]),
.O(plusOp[5]));
LUT2 #(
.INIT(4'h9))
\gc0.count[6]_i_1
(.I0(\gc0.count[8]_i_2_n_0 ),
.I1(Q[6]),
.O(plusOp[6]));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT3 #(
.INIT(8'hD2))
\gc0.count[7]_i_1
(.I0(Q[6]),
.I1(\gc0.count[8]_i_2_n_0 ),
.I2(Q[7]),
.O(plusOp[7]));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT4 #(
.INIT(16'hDF20))
\gc0.count[8]_i_1
(.I0(Q[7]),
.I1(\gc0.count[8]_i_2_n_0 ),
.I2(Q[6]),
.I3(rd_pntr_plus1),
.O(plusOp[8]));
LUT6 #(
.INIT(64'h7FFFFFFFFFFFFFFF))
\gc0.count[8]_i_2
(.I0(Q[5]),
.I1(Q[3]),
.I2(Q[1]),
.I3(Q[0]),
.I4(Q[2]),
.I5(Q[4]),
.O(\gc0.count[8]_i_2_n_0 ));
FDRE #(
.INIT(1'b0))
\gc0.count_d1_reg[0]
(.C(clk),
.CE(E),
.D(Q[0]),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram [0]),
.R(srst));
FDRE #(
.INIT(1'b0))
\gc0.count_d1_reg[1]
(.C(clk),
.CE(E),
.D(Q[1]),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram [1]),
.R(srst));
FDRE #(
.INIT(1'b0))
\gc0.count_d1_reg[2]
(.C(clk),
.CE(E),
.D(Q[2]),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram [2]),
.R(srst));
FDRE #(
.INIT(1'b0))
\gc0.count_d1_reg[3]
(.C(clk),
.CE(E),
.D(Q[3]),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram [3]),
.R(srst));
FDRE #(
.INIT(1'b0))
\gc0.count_d1_reg[4]
(.C(clk),
.CE(E),
.D(Q[4]),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram [4]),
.R(srst));
FDRE #(
.INIT(1'b0))
\gc0.count_d1_reg[5]
(.C(clk),
.CE(E),
.D(Q[5]),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram [5]),
.R(srst));
FDRE #(
.INIT(1'b0))
\gc0.count_d1_reg[6]
(.C(clk),
.CE(E),
.D(Q[6]),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram [6]),
.R(srst));
FDRE #(
.INIT(1'b0))
\gc0.count_d1_reg[7]
(.C(clk),
.CE(E),
.D(Q[7]),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram [7]),
.R(srst));
FDRE #(
.INIT(1'b0))
\gc0.count_d1_reg[8]
(.C(clk),
.CE(E),
.D(rd_pntr_plus1),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram [8]),
.R(srst));
FDSE #(
.INIT(1'b1))
\gc0.count_reg[0]
(.C(clk),
.CE(E),
.D(plusOp[0]),
.Q(Q[0]),
.S(srst));
FDRE #(
.INIT(1'b0))
\gc0.count_reg[1]
(.C(clk),
.CE(E),
.D(plusOp[1]),
.Q(Q[1]),
.R(srst));
FDRE #(
.INIT(1'b0))
\gc0.count_reg[2]
(.C(clk),
.CE(E),
.D(plusOp[2]),
.Q(Q[2]),
.R(srst));
FDRE #(
.INIT(1'b0))
\gc0.count_reg[3]
(.C(clk),
.CE(E),
.D(plusOp[3]),
.Q(Q[3]),
.R(srst));
FDRE #(
.INIT(1'b0))
\gc0.count_reg[4]
(.C(clk),
.CE(E),
.D(plusOp[4]),
.Q(Q[4]),
.R(srst));
FDRE #(
.INIT(1'b0))
\gc0.count_reg[5]
(.C(clk),
.CE(E),
.D(plusOp[5]),
.Q(Q[5]),
.R(srst));
FDRE #(
.INIT(1'b0))
\gc0.count_reg[6]
(.C(clk),
.CE(E),
.D(plusOp[6]),
.Q(Q[6]),
.R(srst));
FDRE #(
.INIT(1'b0))
\gc0.count_reg[7]
(.C(clk),
.CE(E),
.D(plusOp[7]),
.Q(Q[7]),
.R(srst));
FDRE #(
.INIT(1'b0))
\gc0.count_reg[8]
(.C(clk),
.CE(E),
.D(plusOp[8]),
.Q(rd_pntr_plus1),
.R(srst));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[0].gm1.m1_i_1__2
(.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram [0]),
.I1(\gcc0.gc0.count_reg[8] [0]),
.I2(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram [1]),
.I3(\gcc0.gc0.count_reg[8] [1]),
.O(v1_reg[0]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[1].gms.ms_i_1__2
(.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram [2]),
.I1(\gcc0.gc0.count_reg[8] [2]),
.I2(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram [3]),
.I3(\gcc0.gc0.count_reg[8] [3]),
.O(v1_reg[1]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[2].gms.ms_i_1__2
(.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram [4]),
.I1(\gcc0.gc0.count_reg[8] [4]),
.I2(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram [5]),
.I3(\gcc0.gc0.count_reg[8] [5]),
.O(v1_reg[2]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[3].gms.ms_i_1__2
(.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram [6]),
.I1(\gcc0.gc0.count_reg[8] [6]),
.I2(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram [7]),
.I3(\gcc0.gc0.count_reg[8] [7]),
.O(v1_reg[3]));
LUT2 #(
.INIT(4'h9))
\gmux.gm[4].gms.ms_i_1
(.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram [8]),
.I1(\gcc0.gc0.count_d1_reg[8] ),
.O(ram_full_i_reg));
LUT2 #(
.INIT(4'h9))
\gmux.gm[4].gms.ms_i_1__0
(.I0(rd_pntr_plus1),
.I1(\gcc0.gc0.count_d1_reg[8] ),
.O(v1_reg_0));
LUT2 #(
.INIT(4'h9))
\gmux.gm[4].gms.ms_i_1__1
(.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram [8]),
.I1(\gcc0.gc0.count_reg[8] [8]),
.O(v1_reg[4]));
LUT2 #(
.INIT(4'h9))
\gmux.gm[4].gms.ms_i_1__2
(.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram [8]),
.I1(\gcc0.gc0.count_d1_reg[8] ),
.O(ram_empty_fb_i_reg));
endmodule |
module pcie_recv_fifo_rd_fwft
(empty,
tmp_ram_rd_en,
E,
\goreg_bm.dout_i_reg[127] ,
clk,
p_2_out,
rd_en,
srst);
output empty;
output tmp_ram_rd_en;
output [0:0]E;
output [0:0]\goreg_bm.dout_i_reg[127] ;
input clk;
input p_2_out;
input rd_en;
input srst;
wire [0:0]E;
wire clk;
wire [0:0]curr_fwft_state;
wire empty;
wire empty_fwft_fb;
wire empty_fwft_fb_reg_n_0;
wire [0:0]\goreg_bm.dout_i_reg[127] ;
wire \gpregsm1.curr_fwft_state[0]_i_1_n_0 ;
wire \gpregsm1.curr_fwft_state[1]_i_1_n_0 ;
wire \gpregsm1.curr_fwft_state_reg_n_0_[1] ;
wire p_2_out;
wire rd_en;
wire srst;
wire tmp_ram_rd_en;
LUT5 #(
.INIT(32'hFFFF4555))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_i_1
(.I0(p_2_out),
.I1(rd_en),
.I2(curr_fwft_state),
.I3(\gpregsm1.curr_fwft_state_reg_n_0_[1] ),
.I4(srst),
.O(tmp_ram_rd_en));
(* equivalent_register_removal = "no" *)
FDRE #(
.INIT(1'b1))
empty_fwft_fb_reg
(.C(clk),
.CE(1'b1),
.D(empty_fwft_fb),
.Q(empty_fwft_fb_reg_n_0),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT5 #(
.INIT(32'hFAF0FFF8))
empty_fwft_i_i_1
(.I0(curr_fwft_state),
.I1(rd_en),
.I2(srst),
.I3(empty_fwft_fb_reg_n_0),
.I4(\gpregsm1.curr_fwft_state_reg_n_0_[1] ),
.O(empty_fwft_fb));
(* equivalent_register_removal = "no" *)
FDRE #(
.INIT(1'b1))
empty_fwft_i_reg
(.C(clk),
.CE(1'b1),
.D(empty_fwft_fb),
.Q(empty),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT4 #(
.INIT(16'h0B0F))
\gc0.count_d1[8]_i_1
(.I0(rd_en),
.I1(curr_fwft_state),
.I2(p_2_out),
.I3(\gpregsm1.curr_fwft_state_reg_n_0_[1] ),
.O(E));
LUT3 #(
.INIT(8'hD0))
\goreg_bm.dout_i[127]_i_1
(.I0(curr_fwft_state),
.I1(rd_en),
.I2(\gpregsm1.curr_fwft_state_reg_n_0_[1] ),
.O(\goreg_bm.dout_i_reg[127] ));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT4 #(
.INIT(16'h00F2))
\gpregsm1.curr_fwft_state[0]_i_1
(.I0(curr_fwft_state),
.I1(rd_en),
.I2(\gpregsm1.curr_fwft_state_reg_n_0_[1] ),
.I3(srst),
.O(\gpregsm1.curr_fwft_state[0]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT5 #(
.INIT(32'h00002F0F))
\gpregsm1.curr_fwft_state[1]_i_1
(.I0(curr_fwft_state),
.I1(rd_en),
.I2(p_2_out),
.I3(\gpregsm1.curr_fwft_state_reg_n_0_[1] ),
.I4(srst),
.O(\gpregsm1.curr_fwft_state[1]_i_1_n_0 ));
(* equivalent_register_removal = "no" *)
FDRE #(
.INIT(1'b0))
\gpregsm1.curr_fwft_state_reg[0]
(.C(clk),
.CE(1'b1),
.D(\gpregsm1.curr_fwft_state[0]_i_1_n_0 ),
.Q(curr_fwft_state),
.R(1'b0));
(* equivalent_register_removal = "no" *)
FDRE #(
.INIT(1'b0))
\gpregsm1.curr_fwft_state_reg[1]
(.C(clk),
.CE(1'b1),
.D(\gpregsm1.curr_fwft_state[1]_i_1_n_0 ),
.Q(\gpregsm1.curr_fwft_state_reg_n_0_[1] ),
.R(1'b0));
endmodule |
module pcie_recv_fifo_rd_logic
(empty,
E,
tmp_ram_rd_en,
\goreg_bm.dout_i_reg[127] ,
Q,
ram_full_i_reg,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram ,
v1_reg,
v1_reg_0,
\gcc0.gc0.count_d1_reg[6] ,
clk,
srst,
ram_full_fb_i_reg,
rd_en,
\gcc0.gc0.count_d1_reg[8] ,
\gcc0.gc0.count_reg[8] );
output empty;
output [0:0]E;
output tmp_ram_rd_en;
output [0:0]\goreg_bm.dout_i_reg[127] ;
output [7:0]Q;
output [0:0]ram_full_i_reg;
output [8:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram ;
output [4:0]v1_reg;
input [3:0]v1_reg_0;
input [3:0]\gcc0.gc0.count_d1_reg[6] ;
input clk;
input srst;
input ram_full_fb_i_reg;
input rd_en;
input [0:0]\gcc0.gc0.count_d1_reg[8] ;
input [8:0]\gcc0.gc0.count_reg[8] ;
wire [8:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram ;
wire [0:0]E;
wire [7:0]Q;
wire [4:4]\c2/v1_reg ;
wire clk;
wire empty;
wire [3:0]\gcc0.gc0.count_d1_reg[6] ;
wire [0:0]\gcc0.gc0.count_d1_reg[8] ;
wire [8:0]\gcc0.gc0.count_reg[8] ;
wire [0:0]\goreg_bm.dout_i_reg[127] ;
wire p_2_out;
wire ram_full_fb_i_reg;
wire [0:0]ram_full_i_reg;
wire rd_en;
wire rpntr_n_24;
wire srst;
wire tmp_ram_rd_en;
wire [4:0]v1_reg;
wire [3:0]v1_reg_0;
pcie_recv_fifo_rd_fwft \gr1.rfwft
(.E(E),
.clk(clk),
.empty(empty),
.\goreg_bm.dout_i_reg[127] (\goreg_bm.dout_i_reg[127] ),
.p_2_out(p_2_out),
.rd_en(rd_en),
.srst(srst),
.tmp_ram_rd_en(tmp_ram_rd_en));
pcie_recv_fifo_rd_status_flags_ss \grss.rsts
(.E(E),
.clk(clk),
.\gc0.count_d1_reg[8] (rpntr_n_24),
.\gcc0.gc0.count_d1_reg[6] (\gcc0.gc0.count_d1_reg[6] ),
.p_2_out(p_2_out),
.ram_full_fb_i_reg(ram_full_fb_i_reg),
.srst(srst),
.v1_reg(\c2/v1_reg ),
.v1_reg_0(v1_reg_0));
pcie_recv_fifo_rd_bin_cntr rpntr
(.\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram (\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram ),
.E(E),
.Q(Q),
.clk(clk),
.\gcc0.gc0.count_d1_reg[8] (\gcc0.gc0.count_d1_reg[8] ),
.\gcc0.gc0.count_reg[8] (\gcc0.gc0.count_reg[8] ),
.ram_empty_fb_i_reg(rpntr_n_24),
.ram_full_i_reg(ram_full_i_reg),
.srst(srst),
.v1_reg(v1_reg),
.v1_reg_0(\c2/v1_reg ));
endmodule |
module pcie_recv_fifo_rd_status_flags_ss
(p_2_out,
v1_reg_0,
\gc0.count_d1_reg[8] ,
\gcc0.gc0.count_d1_reg[6] ,
v1_reg,
clk,
srst,
E,
ram_full_fb_i_reg);
output p_2_out;
input [3:0]v1_reg_0;
input \gc0.count_d1_reg[8] ;
input [3:0]\gcc0.gc0.count_d1_reg[6] ;
input [0:0]v1_reg;
input clk;
input srst;
input [0:0]E;
input ram_full_fb_i_reg;
wire [0:0]E;
wire clk;
wire comp1;
wire \gc0.count_d1_reg[8] ;
wire [3:0]\gcc0.gc0.count_d1_reg[6] ;
wire p_2_out;
wire ram_empty_fb_i;
wire ram_full_fb_i_reg;
wire srst;
wire [0:0]v1_reg;
wire [3:0]v1_reg_0;
pcie_recv_fifo_compare_1 c1
(.E(E),
.comp1(comp1),
.\gc0.count_d1_reg[8] (\gc0.count_d1_reg[8] ),
.p_2_out(p_2_out),
.ram_empty_fb_i(ram_empty_fb_i),
.ram_full_fb_i_reg(ram_full_fb_i_reg),
.srst(srst),
.v1_reg_0(v1_reg_0));
pcie_recv_fifo_compare_2 c2
(.comp1(comp1),
.\gcc0.gc0.count_d1_reg[6] (\gcc0.gc0.count_d1_reg[6] ),
.v1_reg(v1_reg));
(* equivalent_register_removal = "no" *)
FDRE #(
.INIT(1'b1))
ram_empty_fb_i_reg
(.C(clk),
.CE(1'b1),
.D(ram_empty_fb_i),
.Q(p_2_out),
.R(1'b0));
endmodule |
module pcie_recv_fifo_reset_blk_ramfifo
(s_aclk,
s_aresetn);
input s_aclk;
input s_aresetn;
wire inverted_reset;
(* async_reg = "true" *) (* msgon = "true" *) wire rst_d1;
(* async_reg = "true" *) (* msgon = "true" *) wire rst_d2;
(* async_reg = "true" *) (* msgon = "true" *) wire rst_d3;
(* async_reg = "true" *) (* msgon = "true" *) wire rst_rd_reg1;
(* async_reg = "true" *) (* msgon = "true" *) wire rst_rd_reg2;
(* async_reg = "true" *) (* msgon = "true" *) wire rst_wr_reg1;
(* async_reg = "true" *) (* msgon = "true" *) wire rst_wr_reg2;
wire s_aclk;
wire s_aresetn;
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDPE #(
.INIT(1'b1))
\grstd1.grst_full.grst_f.rst_d1_reg
(.C(s_aclk),
.CE(1'b1),
.D(1'b0),
.PRE(inverted_reset),
.Q(rst_d1));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDPE #(
.INIT(1'b1))
\grstd1.grst_full.grst_f.rst_d2_reg
(.C(s_aclk),
.CE(1'b1),
.D(rst_d1),
.PRE(inverted_reset),
.Q(rst_d2));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDPE #(
.INIT(1'b1))
\grstd1.grst_full.grst_f.rst_d3_reg
(.C(s_aclk),
.CE(1'b1),
.D(rst_d2),
.PRE(inverted_reset),
.Q(rst_d3));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDPE #(
.INIT(1'b0))
\ngwrdrst.grst.g7serrst.rst_rd_reg1_reg
(.C(s_aclk),
.CE(1'b1),
.D(1'b0),
.PRE(inverted_reset),
.Q(rst_rd_reg1));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDPE #(
.INIT(1'b0))
\ngwrdrst.grst.g7serrst.rst_rd_reg2_reg
(.C(s_aclk),
.CE(1'b1),
.D(rst_rd_reg1),
.PRE(inverted_reset),
.Q(rst_rd_reg2));
LUT1 #(
.INIT(2'h1))
\ngwrdrst.grst.g7serrst.rst_wr_reg1_i_1
(.I0(s_aresetn),
.O(inverted_reset));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDPE #(
.INIT(1'b0))
\ngwrdrst.grst.g7serrst.rst_wr_reg1_reg
(.C(s_aclk),
.CE(1'b1),
.D(1'b0),
.PRE(inverted_reset),
.Q(rst_wr_reg1));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDPE #(
.INIT(1'b0))
\ngwrdrst.grst.g7serrst.rst_wr_reg2_reg
(.C(s_aclk),
.CE(1'b1),
.D(rst_wr_reg1),
.PRE(inverted_reset),
.Q(rst_wr_reg2));
endmodule |
module pcie_recv_fifo_wr_bin_cntr
(Q,
v1_reg_0,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram ,
v1_reg,
ram_empty_fb_i_reg,
\gc0.count_d1_reg[7] ,
\gc0.count_reg[7] ,
srst,
E,
clk);
output [8:0]Q;
output [3:0]v1_reg_0;
output [8:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram ;
output [3:0]v1_reg;
output [3:0]ram_empty_fb_i_reg;
input [7:0]\gc0.count_d1_reg[7] ;
input [7:0]\gc0.count_reg[7] ;
input srst;
input [0:0]E;
input clk;
wire [8:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram ;
wire [0:0]E;
wire [8:0]Q;
wire clk;
wire [7:0]\gc0.count_d1_reg[7] ;
wire [7:0]\gc0.count_reg[7] ;
wire \gcc0.gc0.count[8]_i_2_n_0 ;
wire [8:0]plusOp__0;
wire [3:0]ram_empty_fb_i_reg;
wire srst;
wire [3:0]v1_reg;
wire [3:0]v1_reg_0;
LUT1 #(
.INIT(2'h1))
\gcc0.gc0.count[0]_i_1
(.I0(Q[0]),
.O(plusOp__0[0]));
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT2 #(
.INIT(4'h6))
\gcc0.gc0.count[1]_i_1
(.I0(Q[0]),
.I1(Q[1]),
.O(plusOp__0[1]));
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT3 #(
.INIT(8'h78))
\gcc0.gc0.count[2]_i_1
(.I0(Q[0]),
.I1(Q[1]),
.I2(Q[2]),
.O(plusOp__0[2]));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT4 #(
.INIT(16'h7F80))
\gcc0.gc0.count[3]_i_1
(.I0(Q[1]),
.I1(Q[0]),
.I2(Q[2]),
.I3(Q[3]),
.O(plusOp__0[3]));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT5 #(
.INIT(32'h7FFF8000))
\gcc0.gc0.count[4]_i_1
(.I0(Q[2]),
.I1(Q[0]),
.I2(Q[1]),
.I3(Q[3]),
.I4(Q[4]),
.O(plusOp__0[4]));
LUT6 #(
.INIT(64'h7FFFFFFF80000000))
\gcc0.gc0.count[5]_i_1
(.I0(Q[3]),
.I1(Q[1]),
.I2(Q[0]),
.I3(Q[2]),
.I4(Q[4]),
.I5(Q[5]),
.O(plusOp__0[5]));
LUT2 #(
.INIT(4'h9))
\gcc0.gc0.count[6]_i_1
(.I0(\gcc0.gc0.count[8]_i_2_n_0 ),
.I1(Q[6]),
.O(plusOp__0[6]));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT3 #(
.INIT(8'hD2))
\gcc0.gc0.count[7]_i_1
(.I0(Q[6]),
.I1(\gcc0.gc0.count[8]_i_2_n_0 ),
.I2(Q[7]),
.O(plusOp__0[7]));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT4 #(
.INIT(16'hDF20))
\gcc0.gc0.count[8]_i_1
(.I0(Q[7]),
.I1(\gcc0.gc0.count[8]_i_2_n_0 ),
.I2(Q[6]),
.I3(Q[8]),
.O(plusOp__0[8]));
LUT6 #(
.INIT(64'h7FFFFFFFFFFFFFFF))
\gcc0.gc0.count[8]_i_2
(.I0(Q[5]),
.I1(Q[3]),
.I2(Q[1]),
.I3(Q[0]),
.I4(Q[2]),
.I5(Q[4]),
.O(\gcc0.gc0.count[8]_i_2_n_0 ));
FDRE #(
.INIT(1'b0))
\gcc0.gc0.count_d1_reg[0]
(.C(clk),
.CE(E),
.D(Q[0]),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram [0]),
.R(srst));
FDRE #(
.INIT(1'b0))
\gcc0.gc0.count_d1_reg[1]
(.C(clk),
.CE(E),
.D(Q[1]),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram [1]),
.R(srst));
FDRE #(
.INIT(1'b0))
\gcc0.gc0.count_d1_reg[2]
(.C(clk),
.CE(E),
.D(Q[2]),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram [2]),
.R(srst));
FDRE #(
.INIT(1'b0))
\gcc0.gc0.count_d1_reg[3]
(.C(clk),
.CE(E),
.D(Q[3]),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram [3]),
.R(srst));
FDRE #(
.INIT(1'b0))
\gcc0.gc0.count_d1_reg[4]
(.C(clk),
.CE(E),
.D(Q[4]),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram [4]),
.R(srst));
FDRE #(
.INIT(1'b0))
\gcc0.gc0.count_d1_reg[5]
(.C(clk),
.CE(E),
.D(Q[5]),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram [5]),
.R(srst));
FDRE #(
.INIT(1'b0))
\gcc0.gc0.count_d1_reg[6]
(.C(clk),
.CE(E),
.D(Q[6]),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram [6]),
.R(srst));
FDRE #(
.INIT(1'b0))
\gcc0.gc0.count_d1_reg[7]
(.C(clk),
.CE(E),
.D(Q[7]),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram [7]),
.R(srst));
FDRE #(
.INIT(1'b0))
\gcc0.gc0.count_d1_reg[8]
(.C(clk),
.CE(E),
.D(Q[8]),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram [8]),
.R(srst));
FDSE #(
.INIT(1'b1))
\gcc0.gc0.count_reg[0]
(.C(clk),
.CE(E),
.D(plusOp__0[0]),
.Q(Q[0]),
.S(srst));
FDRE #(
.INIT(1'b0))
\gcc0.gc0.count_reg[1]
(.C(clk),
.CE(E),
.D(plusOp__0[1]),
.Q(Q[1]),
.R(srst));
FDRE #(
.INIT(1'b0))
\gcc0.gc0.count_reg[2]
(.C(clk),
.CE(E),
.D(plusOp__0[2]),
.Q(Q[2]),
.R(srst));
FDRE #(
.INIT(1'b0))
\gcc0.gc0.count_reg[3]
(.C(clk),
.CE(E),
.D(plusOp__0[3]),
.Q(Q[3]),
.R(srst));
FDRE #(
.INIT(1'b0))
\gcc0.gc0.count_reg[4]
(.C(clk),
.CE(E),
.D(plusOp__0[4]),
.Q(Q[4]),
.R(srst));
FDRE #(
.INIT(1'b0))
\gcc0.gc0.count_reg[5]
(.C(clk),
.CE(E),
.D(plusOp__0[5]),
.Q(Q[5]),
.R(srst));
FDRE #(
.INIT(1'b0))
\gcc0.gc0.count_reg[6]
(.C(clk),
.CE(E),
.D(plusOp__0[6]),
.Q(Q[6]),
.R(srst));
FDRE #(
.INIT(1'b0))
\gcc0.gc0.count_reg[7]
(.C(clk),
.CE(E),
.D(plusOp__0[7]),
.Q(Q[7]),
.R(srst));
FDRE #(
.INIT(1'b0))
\gcc0.gc0.count_reg[8]
(.C(clk),
.CE(E),
.D(plusOp__0[8]),
.Q(Q[8]),
.R(srst));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[0].gm1.m1_i_1
(.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram [1]),
.I1(\gc0.count_d1_reg[7] [1]),
.I2(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram [0]),
.I3(\gc0.count_d1_reg[7] [0]),
.O(v1_reg_0[0]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[0].gm1.m1_i_1__0
(.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram [1]),
.I1(\gc0.count_d1_reg[7] [1]),
.I2(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram [0]),
.I3(\gc0.count_d1_reg[7] [0]),
.O(v1_reg[0]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[0].gm1.m1_i_1__1
(.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram [0]),
.I1(\gc0.count_reg[7] [0]),
.I2(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram [1]),
.I3(\gc0.count_reg[7] [1]),
.O(ram_empty_fb_i_reg[0]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[1].gms.ms_i_1
(.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram [3]),
.I1(\gc0.count_d1_reg[7] [3]),
.I2(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram [2]),
.I3(\gc0.count_d1_reg[7] [2]),
.O(v1_reg_0[1]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[1].gms.ms_i_1__0
(.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram [3]),
.I1(\gc0.count_d1_reg[7] [3]),
.I2(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram [2]),
.I3(\gc0.count_d1_reg[7] [2]),
.O(v1_reg[1]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[1].gms.ms_i_1__1
(.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram [2]),
.I1(\gc0.count_reg[7] [2]),
.I2(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram [3]),
.I3(\gc0.count_reg[7] [3]),
.O(ram_empty_fb_i_reg[1]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[2].gms.ms_i_1
(.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram [5]),
.I1(\gc0.count_d1_reg[7] [5]),
.I2(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram [4]),
.I3(\gc0.count_d1_reg[7] [4]),
.O(v1_reg_0[2]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[2].gms.ms_i_1__0
(.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram [5]),
.I1(\gc0.count_d1_reg[7] [5]),
.I2(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram [4]),
.I3(\gc0.count_d1_reg[7] [4]),
.O(v1_reg[2]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[2].gms.ms_i_1__1
(.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram [4]),
.I1(\gc0.count_reg[7] [4]),
.I2(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram [5]),
.I3(\gc0.count_reg[7] [5]),
.O(ram_empty_fb_i_reg[2]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[3].gms.ms_i_1
(.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram [7]),
.I1(\gc0.count_d1_reg[7] [7]),
.I2(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram [6]),
.I3(\gc0.count_d1_reg[7] [6]),
.O(v1_reg_0[3]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[3].gms.ms_i_1__0
(.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram [7]),
.I1(\gc0.count_d1_reg[7] [7]),
.I2(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram [6]),
.I3(\gc0.count_d1_reg[7] [6]),
.O(v1_reg[3]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[3].gms.ms_i_1__1
(.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram [6]),
.I1(\gc0.count_reg[7] [6]),
.I2(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram [7]),
.I3(\gc0.count_reg[7] [7]),
.O(ram_empty_fb_i_reg[3]));
endmodule |
module pcie_recv_fifo_wr_logic
(full,
\gcc0.gc0.count_reg[0] ,
ram_empty_fb_i_reg,
Q,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram ,
v1_reg,
ram_empty_fb_i_reg_0,
\gc0.count_d1_reg[8] ,
v1_reg_0,
clk,
E,
srst,
wr_en,
\gc0.count_d1_reg[7] ,
\gc0.count_reg[7] );
output full;
output [0:0]\gcc0.gc0.count_reg[0] ;
output ram_empty_fb_i_reg;
output [8:0]Q;
output [8:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram ;
output [3:0]v1_reg;
output [3:0]ram_empty_fb_i_reg_0;
input [0:0]\gc0.count_d1_reg[8] ;
input [4:0]v1_reg_0;
input clk;
input [0:0]E;
input srst;
input wr_en;
input [7:0]\gc0.count_d1_reg[7] ;
input [7:0]\gc0.count_reg[7] ;
wire [8:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram ;
wire [0:0]E;
wire [8:0]Q;
wire [3:0]\c0/v1_reg ;
wire clk;
wire full;
wire [7:0]\gc0.count_d1_reg[7] ;
wire [0:0]\gc0.count_d1_reg[8] ;
wire [7:0]\gc0.count_reg[7] ;
wire [0:0]\gcc0.gc0.count_reg[0] ;
wire ram_empty_fb_i_reg;
wire [3:0]ram_empty_fb_i_reg_0;
wire srst;
wire [3:0]v1_reg;
wire [4:0]v1_reg_0;
wire wr_en;
pcie_recv_fifo_wr_status_flags_ss \gwss.wsts
(.E(E),
.clk(clk),
.full(full),
.\gc0.count_d1_reg[8] (\gc0.count_d1_reg[8] ),
.\gcc0.gc0.count_reg[0] (\gcc0.gc0.count_reg[0] ),
.ram_empty_fb_i_reg(ram_empty_fb_i_reg),
.srst(srst),
.v1_reg(\c0/v1_reg ),
.v1_reg_0(v1_reg_0),
.wr_en(wr_en));
pcie_recv_fifo_wr_bin_cntr wpntr
(.\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram (\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram ),
.E(\gcc0.gc0.count_reg[0] ),
.Q(Q),
.clk(clk),
.\gc0.count_d1_reg[7] (\gc0.count_d1_reg[7] ),
.\gc0.count_reg[7] (\gc0.count_reg[7] ),
.ram_empty_fb_i_reg(ram_empty_fb_i_reg_0),
.srst(srst),
.v1_reg(v1_reg),
.v1_reg_0(\c0/v1_reg ));
endmodule |
module pcie_recv_fifo_wr_status_flags_ss
(full,
\gcc0.gc0.count_reg[0] ,
ram_empty_fb_i_reg,
v1_reg,
\gc0.count_d1_reg[8] ,
v1_reg_0,
clk,
E,
srst,
wr_en);
output full;
output [0:0]\gcc0.gc0.count_reg[0] ;
output ram_empty_fb_i_reg;
input [3:0]v1_reg;
input [0:0]\gc0.count_d1_reg[8] ;
input [4:0]v1_reg_0;
input clk;
input [0:0]E;
input srst;
input wr_en;
wire [0:0]E;
wire clk;
wire comp1;
wire full;
wire [0:0]\gc0.count_d1_reg[8] ;
wire [0:0]\gcc0.gc0.count_reg[0] ;
wire p_1_out;
wire ram_empty_fb_i_reg;
wire ram_full_i;
wire srst;
wire [3:0]v1_reg;
wire [4:0]v1_reg_0;
wire wr_en;
LUT2 #(
.INIT(4'h2))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_i_2
(.I0(wr_en),
.I1(p_1_out),
.O(\gcc0.gc0.count_reg[0] ));
pcie_recv_fifo_compare c0
(.E(E),
.comp1(comp1),
.\gc0.count_d1_reg[8] (\gc0.count_d1_reg[8] ),
.p_1_out(p_1_out),
.ram_full_i(ram_full_i),
.srst(srst),
.v1_reg(v1_reg),
.wr_en(wr_en));
pcie_recv_fifo_compare_0 c1
(.comp1(comp1),
.v1_reg_0(v1_reg_0));
LUT2 #(
.INIT(4'hB))
ram_empty_fb_i_i_2
(.I0(p_1_out),
.I1(wr_en),
.O(ram_empty_fb_i_reg));
(* equivalent_register_removal = "no" *)
FDRE #(
.INIT(1'b0))
ram_full_fb_i_reg
(.C(clk),
.CE(1'b1),
.D(ram_full_i),
.Q(p_1_out),
.R(1'b0));
(* equivalent_register_removal = "no" *)
FDRE #(
.INIT(1'b0))
ram_full_i_reg
(.C(clk),
.CE(1'b1),
.D(ram_full_i),
.Q(full),
.R(1'b0));
endmodule |
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule |
module minimac_rx(
input sys_clk,
input sys_rst,
input rx_rst,
output [31:0] wbm_adr_o,
output wbm_cyc_o,
output wbm_stb_o,
input wbm_ack_i,
output reg [31:0] wbm_dat_o,
input rx_valid,
input [29:0] rx_adr,
output rx_resetcount,
output rx_incrcount,
output rx_endframe,
output fifo_full,
input phy_rx_clk,
input [3:0] phy_rx_data,
input phy_dv,
input phy_rx_er
);
reg rx_resetcount_r;
reg rx_endframe_r;
assign rx_resetcount = rx_resetcount_r;
assign rx_endframe = rx_endframe_r;
reg bus_stb;
assign wbm_cyc_o = bus_stb;
assign wbm_stb_o = bus_stb;
wire fifo_empty;
reg fifo_ack;
wire fifo_eof;
wire [7:0] fifo_data;
minimac_rxfifo rxfifo(
.sys_clk(sys_clk),
.rx_rst(rx_rst),
.phy_rx_clk(phy_rx_clk),
.phy_rx_data(phy_rx_data),
.phy_dv(phy_dv),
.phy_rx_er(phy_rx_er),
.empty(fifo_empty),
.ack(fifo_ack),
.eof(fifo_eof),
.data(fifo_data),
.fifo_full(fifo_full)
);
reg start_of_frame;
reg end_of_frame;
reg in_frame;
always @(posedge sys_clk) begin
if(sys_rst|rx_rst)
in_frame <= 1'b0;
else begin
if(start_of_frame)
in_frame <= 1'b1;
if(end_of_frame)
in_frame <= 1'b0;
end
end
reg loadbyte_en;
reg [1:0] loadbyte_counter;
always @(posedge sys_clk) begin
if(sys_rst|rx_rst)
loadbyte_counter <= 1'b0;
else begin
if(start_of_frame)
loadbyte_counter <= 1'b0;
else if(loadbyte_en)
loadbyte_counter <= loadbyte_counter + 2'd1;
if(loadbyte_en) begin
case(loadbyte_counter)
2'd0: wbm_dat_o[31:24] <= fifo_data;
2'd1: wbm_dat_o[23:16] <= fifo_data;
2'd2: wbm_dat_o[15: 8] <= fifo_data;
2'd3: wbm_dat_o[ 7: 0] <= fifo_data;
endcase
end
end
end
wire full_word = &loadbyte_counter;
wire empty_word = loadbyte_counter == 2'd0;
parameter MTU = 11'd1530;
reg [10:0] maxcount;
always @(posedge sys_clk) begin
if(sys_rst|rx_rst)
maxcount <= MTU;
else begin
if(start_of_frame)
maxcount <= MTU;
else if(loadbyte_en)
maxcount <= maxcount - 11'd1;
end
end
wire still_place = |maxcount;
assign rx_incrcount = loadbyte_en;
reg next_wb_adr;
reg [29:0] adr;
always @(posedge sys_clk) begin
if(sys_rst)
adr <= 30'd0;
else begin
if(start_of_frame)
adr <= rx_adr;
if(next_wb_adr)
adr <= adr + 30'd1;
end
end
assign wbm_adr_o = {adr, 2'd0};
reg [2:0] state;
reg [2:0] next_state;
parameter IDLE = 3'd0;
parameter LOADBYTE = 3'd1;
parameter WBSTROBE = 3'd2;
parameter SENDLAST = 3'd3;
parameter NOMORE = 3'd3;
always @(posedge sys_clk) begin
if(sys_rst)
state <= IDLE;
else
state <= next_state;
end
always @(*) begin
next_state = state;
fifo_ack = 1'b0;
rx_resetcount_r = 1'b0;
rx_endframe_r = 1'b0;
start_of_frame = 1'b0;
end_of_frame = 1'b0;
loadbyte_en = 1'b0;
bus_stb = 1'b0;
next_wb_adr = 1'b0;
case(state)
IDLE: begin
if(~fifo_empty & rx_valid) begin
if(fifo_eof) begin
fifo_ack = 1'b1;
if(in_frame) begin
if(fifo_data[0])
rx_resetcount_r = 1'b1;
else begin
if(empty_word)
rx_endframe_r = 1'b1;
else
next_state = SENDLAST;
end
end_of_frame = 1'b1;
end
end else begin
if(~in_frame)
start_of_frame = 1'b1;
next_state = LOADBYTE;
end
end
end
LOADBYTE: begin
loadbyte_en = 1'b1;
fifo_ack = 1'b1;
if(full_word & rx_valid)
next_state = WBSTROBE;
else
next_state = IDLE;
end
WBSTROBE: begin
bus_stb = 1'b1;
if(wbm_ack_i) begin
if(still_place)
next_state = IDLE;
else
next_state = NOMORE;
next_wb_adr = 1'b1;
end
end
SENDLAST: begin
bus_stb = 1'b1;
if(wbm_ack_i) begin
rx_endframe_r = 1'b1;
next_state = IDLE;
end
end
NOMORE: begin
fifo_ack = 1'b1;
if(~fifo_empty & rx_valid) begin
if(fifo_eof) begin
rx_resetcount_r = 1'b1;
end_of_frame = 1'b1;
next_state = IDLE;
end
end
end
endcase
end
endmodule |
module emesh_monitor(/*AUTOARG*/
// Inputs
clk, reset, itrace, etime, emesh_access, emesh_write,
emesh_datamode, emesh_ctrlmode, emesh_dstaddr, emesh_data,
emesh_srcaddr, emesh_wait
);
parameter AW = 32;
parameter DW = 32;
parameter NAME = "cpu";
//BASIC INTERFACE
input clk;
input reset;
input itrace;
input [31:0] etime;
//MESH TRANSCTION
input emesh_access;
input emesh_write;
input [1:0] emesh_datamode;
input [3:0] emesh_ctrlmode;
input [AW-1:0] emesh_dstaddr;
input [DW-1:0] emesh_data;
input [AW-1:0] emesh_srcaddr;
input emesh_wait;
//core name for trace
reg [63:0] name=NAME;
reg [31:0] ftrace;
initial
begin
ftrace = $fopen({NAME,".trace"}, "w");
end
always @ (posedge clk)
if(itrace & ~reset & emesh_access & ~emesh_wait)
begin
//$fwrite(ftrace, "TIME=%h\n",etime[31:0]);
$fwrite(ftrace, "%h_%h_%h_%h\n",emesh_srcaddr[AW-1:0], emesh_data[DW-1:0],emesh_dstaddr[DW-1:0],{emesh_ctrlmode[3:0],emesh_datamode[1:0],emesh_write,emesh_access});
end
endmodule |
module MIO_BUS(
//cpu_read_write
//wb_input
dat_i,
adr_i,
we_i,
stb_i,
//wb_output
dat_o,
ack_o,
clk,
rst,
BTN,
SW,
//vga_rdn,
//ps2_ready,
//mem_w,
//key,
//Cpu_data2bus, // Data from CPU
//adr_i,
//vga_addr,
//ram_data_out,
//vram_out,
led_out,
counter_out,
counter0_out,
counter1_out,
counter2_out,
//CPU_wait,
//Cpu_data4bus, // Data write to CPU
//ram_data_in, // From CPU write to Memory
//ram_addr, // Memory Address signals
//vram_data_in, // From CPU write to Vram Memory
//vram_addr, // Vram Address signals
//data_ram_we,
//vram_we,
GPIOffffff00_we,
GPIOfffffe00_we,
counter_we,
//ps2_rd,
Peripheral_in
);
//cpu_read_write
//wb interface
input wire [31:0] dat_i;
input wire [31:0] adr_i;
input wire we_i;
input wire stb_i;
output reg [31:0] dat_o = 0;
output ack_o;
//input wire clk, rst, ps2_ready, mem_w, vga_rdn;
input wire clk, rst;
input wire counter0_out, counter1_out, counter2_out;
input wire [ 3: 0] BTN;
//input wire [ 7: 0] SW, led_out, key;
input wire [ 7: 0] SW, led_out;
//input wire [10: 0] vram_out;
//input wire [12: 0] vga_addr;
//input wire [31: 0] Cpu_data2bus, ram_data_out, adr_i, counter_out;
input wire [31: 0] counter_out;
//output wire [12: 0] vram_addr;
//output wire CPU_wait, vram_we;
//output reg data_ram_we, GPIOfffffe00_we, GPIOffffff00_we, counter_we, ps2_rd;
output reg GPIOfffffe00_we, GPIOffffff00_we, counter_we;
//output reg [31: 0] Cpu_data4bus, ram_data_in, Peripheral_in;
output reg [31: 0] Peripheral_in;
//output reg [11: 0] ram_addr;
//output reg [10: 0] vram_data_in;
wire counter_over;
reg [31: 0] Cpu_data2bus, Cpu_data4bus;
wire wea;
//reg vram_write,vram;
//reg ready;
//reg [12: 0] cpu_vram_addr;
//assign CPU_wait = vram ? vga_rdn && ready : 1'b1; // ~vram &&
//always@(posedge clk or posedge rst)
// if( rst )
// ready <= 1;
// else
// ready <= vga_rdn;
//assign vram_we = vga_rdn && vram_write; //CPU_wait &
//assign vram_addr = ~vga_rdn? vga_addr : cpu_vram_addr;
assign ack_o = stb_i;
//wire MIO_wr;
//assign MIO_wr = stb_i && ack_o;
assign wea = stb_i & ack_o & we_i;
always @(posedge clk) begin
if(stb_i & ack_o) begin
if(we_i) begin //write
Cpu_data2bus <= dat_i;
end
else begin //read
dat_o <= Cpu_data4bus;
end
end
end
//RAM & IO decode signals:
always @* begin
//vram = 0;
//data_ram_we = 0;
//vram_write = 0;
counter_we = 0;
GPIOffffff00_we = 0;
GPIOfffffe00_we = 0;
//ps2_rd = 0;
//ram_addr = 12'h0;
//cpu_vram_addr = 13'h0;
//ram_data_in = 32'h0;
//vram_data_in = 31'h0;
Peripheral_in = 32'h0;
Cpu_data4bus = 32'h0;
casex(adr_i[31:8])
//24'h0000xx: begin // data_ram (00000000 - 0000ffff(00000ffc), actually lower 4KB RAM)
// data_ram_we = mem_w;
// ram_addr = adr_i[13:2];
// ram_data_in = Cpu_data2bus;
// Cpu_data4bus = ram_data_out;
//end
//24'h000cxx: begin // Vram (000c0000 - 000cffff(000012c0), actually lower 4800 * 11bit VRAM)
// vram_write = mem_w;
// vram = 1;
// cpu_vram_addr = adr_i[14:2];
// vram_data_in = Cpu_data2bus[31:0];
// Cpu_data4bus = vga_rdn? {21'h0, vram_out[10:0]} : 32'hx;
//end
//24'hffffdx: begin // PS2 (ffffd000 ~ ffffdfff)
// ps2_rd = ~mem_w;
// Peripheral_in = Cpu_data2bus; //write NU
// Cpu_data4bus = {23'h0, ps2_ready, key}; //read from PS2;
//end
24'hfffffe: begin // 7 Segement LEDs (fffffe00 - fffffeff, 4 7-seg display)
GPIOfffffe00_we = wea;
Peripheral_in = Cpu_data2bus;
Cpu_data4bus = counter_out; //read from Counter
end
24'hffffff: begin // LED (ffffff00-ffffffff0,8 LEDs & counter, ffffff04-fffffff4)
if( adr_i[2] ) begin //ffffff04 for addr of counter
counter_we = wea;
Peripheral_in = Cpu_data2bus; //write Counter Value
Cpu_data4bus = counter_out; //read from Counter;
end
else begin // ffffff00
GPIOffffff00_we = wea;
Peripheral_in = Cpu_data2bus; //write Counter set & Initialization and light LED
Cpu_data4bus = {counter0_out, counter1_out, counter2_out, 9'h000, led_out, BTN, SW};
end
end
endcase
end // always end
endmodule |
module sky130_fd_sc_ms__o41ai (
Y ,
A1 ,
A2 ,
A3 ,
A4 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input A3 ;
input A4 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule |
module sky130_fd_sc_hvl__sdlclkp (
GCLK,
SCE ,
GATE,
CLK ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output GCLK;
input SCE ;
input GATE;
input CLK ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire m0 ;
wire m0n ;
wire clkn ;
wire SCE_GATE;
wire GCLK_b ;
// Name Output Other arguments
not not0 (m0n , m0 );
not not1 (clkn , CLK );
nor nor0 (SCE_GATE, GATE, SCE );
sky130_fd_sc_hvl__udp_dlatch$P_pp$PG$N dlatch0 (m0 , SCE_GATE, clkn, , VPWR, VGND);
and and0 (GCLK_b , m0n, CLK );
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (GCLK , GCLK_b, VPWR, VGND );
endmodule |
module do?
//133 times, read in word from FIFO
//16 times inside that, process each bit in the word
//16 times inside that, shift out the current bit with whatever compensation it requires
//writeGate <= 1; //TODO Testing to ensure no writes occure
if(curSPIBit == 15) begin
FIFOReadEnable <= 1;//We are going to be reading from the FIFO next clock
end
compensatedWriteDataToDriveCount <= compensatedWriteDataToDriveCount + 1;
writeData <= compensatedWriteDataToDrive[15];
if(compensatedWriteDataToDriveCount == 0) begin
SPIWriteWordCounter <= SPIWriteWordCounter + 1;
writeDataPipeline <= {writeDataPipeline[2:0], SPICommandWord[curSPIBit]};
curSPIBit <= curSPIBit + 1;
casez (writeDataPipeline)//Bits [3] and [2] were previously written, bit [1] is the current bit to write and bit [0] is the next bit
//The [1] bit is expanded to the full 65MHz clock time via compensatedWriteDataToDrive to simplify writing and accomplish peak shifting (see RL02 Theory Of Operation)
4'b0000:
if(SPICommandWord[curSPIBit]) begin //If our next bit is a one
compensatedWriteDataToDrive <= 16'b0000111111111110;//0111 (becomes 10) with Write Early
end else begin
compensatedWriteDataToDrive <= 16'b0000111111111111;//0111 (becomes 10)
end
4'b0001:
compensatedWriteDataToDrive <= 16'b0000111111111111;//0111 (becomes 10) (NOTE: This is a data pattern requiring shifting, but we accomplish it via the 0000 and 1000 conditionals because you can't go back in time (not even you DEC)
4'bz010:
compensatedWriteDataToDrive <= 16'b1111111100001111;//1101 (becomes 01)
4'bz011:
compensatedWriteDataToDrive <= 16'b1111111110000111;//1101 (becomes 01) with Write Late
4'bz10z:
compensatedWriteDataToDrive <= 16'b1111111111111111;//1111 (becomes 00)
4'bz110:
compensatedWriteDataToDrive <= 16'b1111111000011111;//1101 (becomes 01) with Write Early
4'bz111:
compensatedWriteDataToDrive <= 16'b1111111100001111;//1101 (becomes 01)
4'b1000:
if(SPICommandWord[curSPIBit]) begin //If our next bit is a one
compensatedWriteDataToDrive <= 16'b1000011111111110;//0111 (becomes 10) with Write Late and Write Early
end else begin
compensatedWriteDataToDrive <= 16'b1000011111111111;//0111 (becomes 10) with Write Late
end
4'b1001:
compensatedWriteDataToDrive <= 16'b0000111111111111;//0111 (becomes 10)
endcase
end else begin
compensatedWriteDataToDrive <= compensatedWriteDataToDrive<<1;
end
if(SPIWriteWordCounter > 133) begin
SPIWriteWordCounter <= 8'b0;
FIFOReadEnable <= 0;
curSPIBit <= 4'b0;
writeGate <= 0;
compensatedWriteDataToDrive <= 16'b1111111111111111;
inhibit_read <= 0;
cnc_state <= CNC_IDLE;
end
end
default:
cnc_state <= CNC_IDLE;
endcase
end
end
endmodule |
module top();
// Inputs are registered
reg A;
reg B;
reg C;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
B = 1'bX;
C = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 B = 1'b0;
#60 C = 1'b0;
#80 VGND = 1'b0;
#100 VNB = 1'b0;
#120 VPB = 1'b0;
#140 VPWR = 1'b0;
#160 A = 1'b1;
#180 B = 1'b1;
#200 C = 1'b1;
#220 VGND = 1'b1;
#240 VNB = 1'b1;
#260 VPB = 1'b1;
#280 VPWR = 1'b1;
#300 A = 1'b0;
#320 B = 1'b0;
#340 C = 1'b0;
#360 VGND = 1'b0;
#380 VNB = 1'b0;
#400 VPB = 1'b0;
#420 VPWR = 1'b0;
#440 VPWR = 1'b1;
#460 VPB = 1'b1;
#480 VNB = 1'b1;
#500 VGND = 1'b1;
#520 C = 1'b1;
#540 B = 1'b1;
#560 A = 1'b1;
#580 VPWR = 1'bx;
#600 VPB = 1'bx;
#620 VNB = 1'bx;
#640 VGND = 1'bx;
#660 C = 1'bx;
#680 B = 1'bx;
#700 A = 1'bx;
end
sky130_fd_sc_ms__nand3 dut (.A(A), .B(B), .C(C), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Y(Y));
endmodule |
module ad_datafmt #(
// data bus width
parameter DATA_WIDTH = 16,
parameter DISABLE = 0) (
// data path
input clk,
input valid,
input [(DATA_WIDTH-1):0] data,
output valid_out,
output [15:0] data_out,
// control signals
input dfmt_enable,
input dfmt_type,
input dfmt_se);
// internal registers
reg valid_int = 'd0;
reg [15:0] data_int = 'd0;
// internal signals
wire type_s;
wire [15:0] data_out_s;
// data-path disable
generate
if (DISABLE == 1) begin
assign valid_out = valid;
assign data_out = data;
end else begin
assign valid_out = valid_int;
assign data_out = data_int;
end
endgenerate
// if offset-binary convert to 2's complement first
assign type_s = dfmt_enable & dfmt_type;
generate
if (DATA_WIDTH < 16) begin
wire signext_s;
wire sign_s;
assign signext_s = dfmt_enable & dfmt_se;
assign sign_s = signext_s & (type_s ^ data[(DATA_WIDTH-1)]);
assign data_out_s[15:DATA_WIDTH] = {(16-DATA_WIDTH){sign_s}};
end
endgenerate
assign data_out_s[(DATA_WIDTH-1)] = type_s ^ data[(DATA_WIDTH-1)];
assign data_out_s[(DATA_WIDTH-2):0] = data[(DATA_WIDTH-2):0];
always @(posedge clk) begin
valid_int <= valid;
data_int <= data_out_s[15:0];
end
endmodule |
module GTX_TX_SYNC_RATE_V6
#(
parameter TCQ = 1,
parameter C_SIMULATION = 0 // Set to 1 for simulation
)
(
output reg ENPMAPHASEALIGN = 1'b0,
output reg PMASETPHASE = 1'b0,
output reg SYNC_DONE = 1'b0,
output reg OUT_DIV_RESET = 1'b0,
output reg PCS_RESET = 1'b0,
output reg USER_PHYSTATUS = 1'b0,
output reg TXALIGNDISABLE = 1'b0,
output reg DELAYALIGNRESET = 1'b0,
input USER_CLK,
input RESET,
input RATE,
input RATEDONE,
input GT_PHYSTATUS,
input RESETDONE
);
reg ENPMAPHASEALIGN_c;
reg PMASETPHASE_c;
reg SYNC_DONE_c;
reg OUT_DIV_RESET_c;
reg PCS_RESET_c;
reg USER_PHYSTATUS_c;
reg DELAYALIGNRESET_c;
reg TXALIGNDISABLE_c;
reg [7:0] waitcounter2;
reg [7:0] nextwaitcounter2;
reg [7:0] waitcounter;
reg [7:0] nextwaitcounter;
reg [24:0] state;
reg [24:0] nextstate;
reg ratedone_r, ratedone_r2;
wire ratedone_pulse_i;
reg gt_phystatus_q;
localparam IDLE = 25'b0000000000000000000000001;
localparam PHASEALIGN = 25'b0000000000000000000000010;
localparam RATECHANGE_DIVRESET = 25'b0000000000000000000000100;
localparam RATECHANGE_DIVRESET_POST = 25'b0000000000000000000001000;
localparam RATECHANGE_ENPMADISABLE = 25'b0000000000000000000010000;
localparam RATECHANGE_ENPMADISABLE_POST = 25'b0000000000000000000100000;
localparam RATECHANGE_PMARESET = 25'b0000000000000000001000000;
localparam RATECHANGE_IDLE = 25'b0000000000000000010000000;
localparam RATECHANGE_PCSRESET = 25'b0000000000000000100000000;
localparam RATECHANGE_PCSRESET_POST = 25'b0000000000000001000000000;
localparam RATECHANGE_ASSERTPHY = 25'b0000000000000010000000000;
localparam RESET_STATE = 25'b0000000000000100000000000;
localparam WAIT_PHYSTATUS = 25'b0000000000010000000000000;
localparam RATECHANGE_PMARESET_POST = 25'b0000000000100000000000000;
localparam RATECHANGE_DISABLEPHASE = 25'b0000000001000000000000000;
localparam DELAYALIGNRST = 25'b0000000010000000000000000;
localparam SETENPMAPHASEALIGN = 25'b0000000100000000000000000;
localparam TXALIGNDISABLEDEASSERT = 25'b0000001000000000000000000;
localparam RATECHANGE_TXDLYALIGNDISABLE = 25'b0000010000000000000000000;
localparam GTXTEST_PULSE_1 = 25'b0000100000000000000000000;
localparam RATECHANGE_DISABLE_TXALIGNDISABLE = 25'b0001000000000000000000000;
localparam BEFORE_GTXTEST_PULSE1_1024CLKS = 25'b0010000000000000000000000;
localparam BETWEEN_GTXTEST_PULSES = 25'b0100000000000000000000000;
localparam GTXTEST_PULSE_2 = 25'b1000000000000000000000000;
localparam SYNC_IDX = C_SIMULATION ? 0 : 2;
localparam PMARESET_IDX = C_SIMULATION ? 0: 7;
always @(posedge USER_CLK) begin
if(RESET) begin
state <= #(TCQ) RESET_STATE;
waitcounter2 <= #(TCQ) 1'b0;
waitcounter <= #(TCQ) 1'b0;
USER_PHYSTATUS <= #(TCQ) GT_PHYSTATUS;
SYNC_DONE <= #(TCQ) 1'b0;
ENPMAPHASEALIGN <= #(TCQ) 1'b1;
PMASETPHASE <= #(TCQ) 1'b0;
OUT_DIV_RESET <= #(TCQ) 1'b0;
PCS_RESET <= #(TCQ) 1'b0;
DELAYALIGNRESET <= #(TCQ) 1'b0;
TXALIGNDISABLE <= #(TCQ) 1'b1;
end else begin
state <= #(TCQ) nextstate;
waitcounter2 <= #(TCQ) nextwaitcounter2;
waitcounter <= #(TCQ) nextwaitcounter;
USER_PHYSTATUS <= #(TCQ) USER_PHYSTATUS_c;
SYNC_DONE <= #(TCQ) SYNC_DONE_c;
ENPMAPHASEALIGN <= #(TCQ) ENPMAPHASEALIGN_c;
PMASETPHASE <= #(TCQ) PMASETPHASE_c;
OUT_DIV_RESET <= #(TCQ) OUT_DIV_RESET_c;
PCS_RESET <= #(TCQ) PCS_RESET_c;
DELAYALIGNRESET <= #(TCQ) DELAYALIGNRESET_c;
TXALIGNDISABLE <= #(TCQ) TXALIGNDISABLE_c;
end
end
always @(*) begin
// DEFAULT CONDITIONS
DELAYALIGNRESET_c=0;
SYNC_DONE_c=0;
ENPMAPHASEALIGN_c=1;
PMASETPHASE_c=0;
OUT_DIV_RESET_c=0;
PCS_RESET_c=0;
TXALIGNDISABLE_c=0;
nextstate=state;
USER_PHYSTATUS_c=GT_PHYSTATUS;
nextwaitcounter=waitcounter+1'b1;
nextwaitcounter2= (waitcounter ==8'hff)? waitcounter2 + 1'b1 : waitcounter2 ;
case(state)
// START IN RESET
RESET_STATE : begin
TXALIGNDISABLE_c=1;
ENPMAPHASEALIGN_c=0;
nextstate=BEFORE_GTXTEST_PULSE1_1024CLKS;
nextwaitcounter=0;
nextwaitcounter2=0;
end
// Have to hold for 1024 clocks before asserting GTXTEST[1]
BEFORE_GTXTEST_PULSE1_1024CLKS : begin
OUT_DIV_RESET_c=0;
TXALIGNDISABLE_c=1;
ENPMAPHASEALIGN_c=0;
if(waitcounter2[1]) begin
nextstate=GTXTEST_PULSE_1;
nextwaitcounter=0;
nextwaitcounter2=0;
end
end
// Assert GTXTEST[1] for 256 clocks. Figure 3-9 UG366
GTXTEST_PULSE_1: begin
OUT_DIV_RESET_c=1;
TXALIGNDISABLE_c=1;
ENPMAPHASEALIGN_c=0;
if(waitcounter[7]) begin
nextstate=BETWEEN_GTXTEST_PULSES;
nextwaitcounter=0;
nextwaitcounter2=0;
end
end
// De-assert GTXTEST[1] for 256 clocks. Figure 3-9 UG366
BETWEEN_GTXTEST_PULSES: begin
OUT_DIV_RESET_c=0;
TXALIGNDISABLE_c=1;
ENPMAPHASEALIGN_c=0;
if(waitcounter[7]) begin
nextstate=GTXTEST_PULSE_2;
nextwaitcounter=0;
nextwaitcounter2=0;
end
end
// Assert GTXTEST[1] for 256 clocks a second time. Figure 3-9 UG366
GTXTEST_PULSE_2: begin
OUT_DIV_RESET_c=1;
TXALIGNDISABLE_c=1;
ENPMAPHASEALIGN_c=0;
if(waitcounter[7]) begin
nextstate=DELAYALIGNRST;
nextwaitcounter=0;
nextwaitcounter2=0;
end
end
// ASSERT TXDLYALIGNRESET FOR 16 CLOCK CYCLES
DELAYALIGNRST : begin
DELAYALIGNRESET_c=1;
ENPMAPHASEALIGN_c=0;
TXALIGNDISABLE_c=1;
if(waitcounter[4]) begin
nextstate=SETENPMAPHASEALIGN;
nextwaitcounter=0;
nextwaitcounter2=0;
end
end
// ASSERT ENPMAPHASEALIGN FOR 32 CLOCK CYCLES
SETENPMAPHASEALIGN : begin
TXALIGNDISABLE_c=1;
if(waitcounter[5]) begin
nextstate=PHASEALIGN;
nextwaitcounter=0;
nextwaitcounter2=0;
end
end
// ASSERT PMASETPHASE OUT OF RESET for 32K CYCLES
PHASEALIGN : begin
PMASETPHASE_c=1;
TXALIGNDISABLE_c=1;
if(waitcounter2[PMARESET_IDX]) begin
nextstate=TXALIGNDISABLEDEASSERT;
nextwaitcounter=0;
nextwaitcounter2=0;
end
end
// KEEP TXALIGNDISABLE ASSERTED for 64 CYCLES
TXALIGNDISABLEDEASSERT : begin
TXALIGNDISABLE_c=1;
if(waitcounter[6]) begin
nextwaitcounter=0;
nextstate=IDLE;
nextwaitcounter2=0;
end
end
// NOW IN IDLE, ASSERT SYNC DONE, WAIT FOR RATECHANGE
IDLE : begin
SYNC_DONE_c=1;
if(ratedone_pulse_i) begin
USER_PHYSTATUS_c=0;
nextstate=WAIT_PHYSTATUS;
nextwaitcounter=0;
nextwaitcounter2=0;
end
end
// WAIT FOR PHYSTATUS
WAIT_PHYSTATUS : begin
USER_PHYSTATUS_c=0;
if(gt_phystatus_q) begin
nextstate=RATECHANGE_IDLE;
nextwaitcounter=0;
nextwaitcounter2=0;
end
end
// WAIT 64 CYCLES BEFORE WE START THE RATE CHANGE
RATECHANGE_IDLE : begin
USER_PHYSTATUS_c=0;
if(waitcounter[6]) begin
nextstate=RATECHANGE_TXDLYALIGNDISABLE;
nextwaitcounter=0;
nextwaitcounter2=0;
end
end
// ASSERT TXALIGNDISABLE FOR 32 CYCLES
RATECHANGE_TXDLYALIGNDISABLE : begin
USER_PHYSTATUS_c=0;
TXALIGNDISABLE_c=1;
if(waitcounter[5]) begin
nextstate=RATECHANGE_DIVRESET;
nextwaitcounter=0;
nextwaitcounter2=0;
end
end
// ASSERT DIV RESET FOR 16 CLOCK CYCLES
RATECHANGE_DIVRESET : begin
OUT_DIV_RESET_c=1;
USER_PHYSTATUS_c=0;
TXALIGNDISABLE_c=1;
if(waitcounter[4]) begin
nextstate=RATECHANGE_DIVRESET_POST;
nextwaitcounter=0;
nextwaitcounter2=0;
end
end
// WAIT FOR 32 CLOCK CYCLES BEFORE NEXT STEP
RATECHANGE_DIVRESET_POST : begin
USER_PHYSTATUS_c=0;
TXALIGNDISABLE_c=1;
if(waitcounter[5]) begin
nextstate=RATECHANGE_PMARESET;
nextwaitcounter=0;
nextwaitcounter2=0;
end
end
// ASSERT PMA RESET FOR 32K CYCLES
RATECHANGE_PMARESET : begin
PMASETPHASE_c=1;
USER_PHYSTATUS_c=0;
TXALIGNDISABLE_c=1;
if(waitcounter2[PMARESET_IDX]) begin
nextstate=RATECHANGE_PMARESET_POST;
nextwaitcounter=0;
nextwaitcounter2=0;
end
end
// WAIT FOR 32 CYCLES BEFORE DISABLING TXALIGNDISABLE
RATECHANGE_PMARESET_POST : begin
USER_PHYSTATUS_c=0;
TXALIGNDISABLE_c=1;
if(waitcounter[5]) begin
nextstate=RATECHANGE_DISABLE_TXALIGNDISABLE;
nextwaitcounter=0;
nextwaitcounter2=0;
end
end
// DISABLE TXALIGNDISABLE FOR 32 CYCLES
RATECHANGE_DISABLE_TXALIGNDISABLE : begin
USER_PHYSTATUS_c=0;
if(waitcounter[5]) begin
nextstate=RATECHANGE_PCSRESET;
nextwaitcounter=0;
nextwaitcounter2=0;
end
end
// NOW ASSERT PCS RESET FOR 32 CYCLES
RATECHANGE_PCSRESET : begin
PCS_RESET_c=1;
USER_PHYSTATUS_c=0;
if(waitcounter[5]) begin
nextstate=RATECHANGE_PCSRESET_POST;
nextwaitcounter=0;
nextwaitcounter2=0;
end
end
// WAIT FOR RESETDONE BEFORE ASSERTING PHY_STATUS_OUT
RATECHANGE_PCSRESET_POST : begin
USER_PHYSTATUS_c=0;
if(RESETDONE) begin
nextstate=RATECHANGE_ASSERTPHY;
end
end
// ASSERT PHYSTATUSOUT MEANING RATECHANGE IS DONE AND GO BACK TO IDLE
RATECHANGE_ASSERTPHY : begin
USER_PHYSTATUS_c=1;
nextstate=IDLE;
end
endcase
end
// Generate Ratechange Pulse
always @(posedge USER_CLK) begin
if (RESET) begin
ratedone_r <= #(TCQ) 1'b0;
ratedone_r2 <= #(TCQ) 1'b0;
gt_phystatus_q <= #(TCQ) 1'b0;
end else begin
ratedone_r <= #(TCQ) RATE;
ratedone_r2 <= #(TCQ) ratedone_r;
gt_phystatus_q <= #(TCQ) GT_PHYSTATUS;
end
end
assign ratedone_pulse_i = (ratedone_r != ratedone_r2);
endmodule |
module CvtColor (
ap_clk,
ap_rst,
ap_start,
ap_done,
ap_continue,
ap_idle,
ap_ready,
p_src_rows_V_dout,
p_src_rows_V_empty_n,
p_src_rows_V_read,
p_src_cols_V_dout,
p_src_cols_V_empty_n,
p_src_cols_V_read,
p_src_data_stream_0_V_dout,
p_src_data_stream_0_V_empty_n,
p_src_data_stream_0_V_read,
p_src_data_stream_1_V_dout,
p_src_data_stream_1_V_empty_n,
p_src_data_stream_1_V_read,
p_src_data_stream_2_V_dout,
p_src_data_stream_2_V_empty_n,
p_src_data_stream_2_V_read,
p_dst_data_stream_0_V_din,
p_dst_data_stream_0_V_full_n,
p_dst_data_stream_0_V_write,
p_dst_data_stream_1_V_din,
p_dst_data_stream_1_V_full_n,
p_dst_data_stream_1_V_write,
p_dst_data_stream_2_V_din,
p_dst_data_stream_2_V_full_n,
p_dst_data_stream_2_V_write
);
parameter ap_ST_fsm_state1 = 4'd1;
parameter ap_ST_fsm_state2 = 4'd2;
parameter ap_ST_fsm_pp0_stage0 = 4'd4;
parameter ap_ST_fsm_state9 = 4'd8;
input ap_clk;
input ap_rst;
input ap_start;
output ap_done;
input ap_continue;
output ap_idle;
output ap_ready;
input [15:0] p_src_rows_V_dout;
input p_src_rows_V_empty_n;
output p_src_rows_V_read;
input [15:0] p_src_cols_V_dout;
input p_src_cols_V_empty_n;
output p_src_cols_V_read;
input [7:0] p_src_data_stream_0_V_dout;
input p_src_data_stream_0_V_empty_n;
output p_src_data_stream_0_V_read;
input [7:0] p_src_data_stream_1_V_dout;
input p_src_data_stream_1_V_empty_n;
output p_src_data_stream_1_V_read;
input [7:0] p_src_data_stream_2_V_dout;
input p_src_data_stream_2_V_empty_n;
output p_src_data_stream_2_V_read;
output [7:0] p_dst_data_stream_0_V_din;
input p_dst_data_stream_0_V_full_n;
output p_dst_data_stream_0_V_write;
output [7:0] p_dst_data_stream_1_V_din;
input p_dst_data_stream_1_V_full_n;
output p_dst_data_stream_1_V_write;
output [7:0] p_dst_data_stream_2_V_din;
input p_dst_data_stream_2_V_full_n;
output p_dst_data_stream_2_V_write;
reg ap_done;
reg ap_idle;
reg ap_ready;
reg p_src_rows_V_read;
reg p_src_cols_V_read;
reg p_src_data_stream_0_V_read;
reg p_src_data_stream_1_V_read;
reg p_src_data_stream_2_V_read;
reg p_dst_data_stream_0_V_write;
reg p_dst_data_stream_1_V_write;
reg p_dst_data_stream_2_V_write;
reg ap_done_reg;
(* fsm_encoding = "none" *) reg [3:0] ap_CS_fsm;
wire ap_CS_fsm_state1;
reg p_src_rows_V_blk_n;
reg p_src_cols_V_blk_n;
reg p_src_data_stream_0_V_blk_n;
wire ap_CS_fsm_pp0_stage0;
reg ap_enable_reg_pp0_iter1;
wire ap_block_pp0_stage0;
reg [0:0] tmp_35_i_reg_775;
reg p_src_data_stream_1_V_blk_n;
reg p_src_data_stream_2_V_blk_n;
reg p_dst_data_stream_0_V_blk_n;
reg ap_enable_reg_pp0_iter5;
reg [0:0] ap_reg_pp0_iter4_tmp_35_i_reg_775;
reg p_dst_data_stream_1_V_blk_n;
reg p_dst_data_stream_2_V_blk_n;
reg [10:0] j_i_reg_174;
reg [15:0] p_src_cols_V_read_reg_756;
reg ap_block_state1;
reg [15:0] p_src_rows_V_read_reg_761;
wire [0:0] tmp_i_fu_189_p2;
wire ap_CS_fsm_state2;
wire [10:0] i_fu_194_p2;
reg [10:0] i_reg_770;
wire [0:0] tmp_35_i_fu_204_p2;
wire ap_block_state3_pp0_stage0_iter0;
reg ap_block_state4_pp0_stage0_iter1;
wire ap_block_state5_pp0_stage0_iter2;
wire ap_block_state6_pp0_stage0_iter3;
wire ap_block_state7_pp0_stage0_iter4;
reg ap_block_state8_pp0_stage0_iter5;
reg ap_block_pp0_stage0_11001;
reg [0:0] ap_reg_pp0_iter1_tmp_35_i_reg_775;
reg [0:0] ap_reg_pp0_iter2_tmp_35_i_reg_775;
reg [0:0] ap_reg_pp0_iter3_tmp_35_i_reg_775;
wire [10:0] j_fu_209_p2;
reg ap_enable_reg_pp0_iter0;
reg [7:0] tmp_39_reg_784;
wire [7:0] i_op_assign_fu_215_p2;
reg signed [7:0] i_op_assign_reg_789;
reg signed [7:0] ap_reg_pp0_iter2_i_op_assign_reg_789;
wire [7:0] i_op_assign_2_fu_221_p2;
reg signed [7:0] i_op_assign_2_reg_795;
wire signed [31:0] grp_fu_713_p3;
reg signed [31:0] r_V_reg_801;
reg ap_enable_reg_pp0_iter2;
reg [0:0] signbit_reg_806;
reg [0:0] ap_reg_pp0_iter3_signbit_reg_806;
reg [7:0] p_Val2_2_reg_813;
reg [0:0] tmp_reg_818;
reg [1:0] tmp_3_reg_823;
wire signed [31:0] grp_fu_725_p3;
reg signed [31:0] tmp2_reg_829;
wire signed [31:0] grp_fu_733_p3;
reg signed [31:0] r_V_5_reg_834;
reg [0:0] signbit_3_reg_839;
reg [0:0] ap_reg_pp0_iter3_signbit_3_reg_839;
reg [7:0] p_Val2_30_reg_846;
reg [0:0] tmp_33_reg_851;
reg [1:0] tmp_7_reg_856;
wire [7:0] p_Val2_3_fu_324_p2;
reg [7:0] p_Val2_3_reg_862;
wire [0:0] p_38_i_i_i1_i_fu_367_p2;
reg [0:0] p_38_i_i_i1_i_reg_868;
wire [0:0] p_39_demorgan_i_i_i2_s_fu_373_p2;
reg [0:0] p_39_demorgan_i_i_i2_s_reg_874;
wire signed [31:0] grp_fu_745_p3;
reg signed [31:0] r_V_4_reg_880;
reg ap_enable_reg_pp0_iter3;
reg [0:0] signbit_2_reg_885;
reg [0:0] ap_reg_pp0_iter4_signbit_2_reg_885;
reg [7:0] p_Val2_7_reg_892;
reg [0:0] tmp_29_reg_897;
reg [1:0] tmp_5_reg_902;
wire [7:0] p_Val2_31_fu_420_p2;
reg [7:0] p_Val2_31_reg_908;
wire [0:0] p_38_i_i_i21_i_fu_463_p2;
reg [0:0] p_38_i_i_i21_i_reg_914;
wire [0:0] p_39_demorgan_i_i_i_fu_469_p2;
reg [0:0] p_39_demorgan_i_i_i_reg_920;
wire [7:0] p_Val2_33_fu_524_p3;
reg [7:0] p_Val2_33_reg_926;
wire [7:0] p_Val2_8_fu_542_p2;
reg [7:0] p_Val2_8_reg_931;
wire [0:0] p_38_i_i_i_i_fu_585_p2;
reg [0:0] p_38_i_i_i_i_reg_937;
wire [0:0] p_39_demorgan_i_i_i_i_fu_591_p2;
reg [0:0] p_39_demorgan_i_i_i_i_reg_943;
wire [7:0] p_Val2_s_fu_646_p3;
reg [7:0] p_Val2_s_reg_949;
reg ap_block_pp0_stage0_subdone;
reg ap_condition_pp0_exit_iter0_state3;
reg ap_enable_reg_pp0_iter4;
reg [10:0] i_i_reg_163;
wire ap_CS_fsm_state9;
reg ap_block_pp0_stage0_01001;
wire [15:0] i_cast_i_cast_fu_185_p1;
wire [15:0] j_cast_i_cast_fu_200_p1;
wire [29:0] tmp_i1_fu_230_p3;
wire [7:0] tmp_16_i_i_i_fu_314_p1;
wire [0:0] tmp_27_fu_329_p3;
wire [0:0] tmp_26_fu_317_p3;
wire [0:0] tmp_17_i_i_i_fu_337_p2;
wire [0:0] carry_fu_343_p2;
wire [0:0] Range1_all_ones_fu_349_p2;
wire [0:0] Range1_all_zeros_fu_354_p2;
wire [0:0] deleted_zeros_fu_359_p3;
wire [7:0] tmp_16_i_i12_i_fu_410_p1;
wire [0:0] tmp_35_fu_425_p3;
wire [0:0] tmp_34_fu_413_p3;
wire [0:0] tmp_17_i_i16_i_fu_433_p2;
wire [0:0] carry_2_fu_439_p2;
wire [0:0] Range1_all_ones_2_fu_445_p2;
wire [0:0] Range1_all_zeros_2_fu_450_p2;
wire [0:0] deleted_zeros_2_fu_455_p3;
wire [0:0] tmp_18_i_i_i_fu_474_p2;
wire [0:0] signbit_not_i_i_fu_484_p2;
wire [0:0] neg_src_not_i_i3_i_fu_489_p2;
wire [0:0] p_39_demorgan_i_not_i_fu_499_p2;
wire [0:0] brmerge_i_i_not_i_i4_fu_494_p2;
wire [0:0] neg_src_9_fu_479_p2;
wire [0:0] brmerge_i_i6_i_fu_504_p2;
wire [7:0] p_mux_i_i7_i_fu_510_p3;
wire [7:0] p_i_i8_i_fu_517_p3;
wire [7:0] tmp_13_i_i_i_fu_532_p1;
wire [0:0] tmp_31_fu_547_p3;
wire [0:0] tmp_30_fu_535_p3;
wire [0:0] tmp_14_i_i_i_fu_555_p2;
wire [0:0] carry_1_fu_561_p2;
wire [0:0] Range1_all_ones_1_fu_567_p2;
wire [0:0] Range1_all_zeros_1_fu_572_p2;
wire [0:0] deleted_zeros_1_fu_577_p3;
wire [0:0] tmp_18_i_i22_i_fu_596_p2;
wire [0:0] signbit_not_i25_i_fu_606_p2;
wire [0:0] neg_src_not_i_i26_i_fu_611_p2;
wire [0:0] p_39_demorgan_i_not_i_3_fu_621_p2;
wire [0:0] brmerge_i_i_not_i_i2_fu_616_p2;
wire [0:0] neg_src_fu_601_p2;
wire [0:0] brmerge_i_i29_i_fu_626_p2;
wire [7:0] p_mux_i_i30_i_fu_632_p3;
wire [7:0] p_i_i31_i_fu_639_p3;
wire [0:0] tmp_15_i_i_i_fu_654_p2;
wire [0:0] signbit_not_i_fu_664_p2;
wire [0:0] neg_src_not_i_i_i_fu_669_p2;
wire [0:0] p_39_demorgan_i_not_i_2_fu_679_p2;
wire [0:0] brmerge_i_i_not_i_i_s_fu_674_p2;
wire [0:0] neg_src_10_fu_659_p2;
wire [0:0] brmerge_i_i_i_fu_684_p2;
wire [7:0] p_mux_i_i_i_fu_690_p3;
wire [7:0] p_i_i_i_fu_697_p3;
wire [23:0] grp_fu_713_p1;
wire [29:0] grp_fu_713_p2;
wire [31:0] tmp_22_cast_i_fu_237_p1;
wire signed [21:0] grp_fu_725_p1;
wire [29:0] grp_fu_725_p2;
wire [23:0] grp_fu_733_p1;
wire [29:0] grp_fu_733_p2;
wire signed [22:0] grp_fu_745_p1;
reg [3:0] ap_NS_fsm;
reg ap_idle_pp0;
wire ap_enable_pp0;
// power-on initialization
initial begin
#0 ap_done_reg = 1'b0;
#0 ap_CS_fsm = 4'd1;
#0 ap_enable_reg_pp0_iter1 = 1'b0;
#0 ap_enable_reg_pp0_iter5 = 1'b0;
#0 ap_enable_reg_pp0_iter0 = 1'b0;
#0 ap_enable_reg_pp0_iter2 = 1'b0;
#0 ap_enable_reg_pp0_iter3 = 1'b0;
#0 ap_enable_reg_pp0_iter4 = 1'b0;
end
hls_contrast_streg8j #(
.ID( 1 ),
.NUM_STAGE( 1 ),
.din0_WIDTH( 8 ),
.din1_WIDTH( 24 ),
.din2_WIDTH( 30 ),
.dout_WIDTH( 32 ))
hls_contrast_streg8j_U60(
.din0(i_op_assign_reg_789),
.din1(grp_fu_713_p1),
.din2(grp_fu_713_p2),
.dout(grp_fu_713_p3)
);
hls_contrast_strehbi #(
.ID( 1 ),
.NUM_STAGE( 1 ),
.din0_WIDTH( 8 ),
.din1_WIDTH( 22 ),
.din2_WIDTH( 30 ),
.dout_WIDTH( 32 ))
hls_contrast_strehbi_U61(
.din0(i_op_assign_2_reg_795),
.din1(grp_fu_725_p1),
.din2(grp_fu_725_p2),
.dout(grp_fu_725_p3)
);
hls_contrast_streg8j #(
.ID( 1 ),
.NUM_STAGE( 1 ),
.din0_WIDTH( 8 ),
.din1_WIDTH( 24 ),
.din2_WIDTH( 30 ),
.dout_WIDTH( 32 ))
hls_contrast_streg8j_U62(
.din0(i_op_assign_2_reg_795),
.din1(grp_fu_733_p1),
.din2(grp_fu_733_p2),
.dout(grp_fu_733_p3)
);
hls_contrast_streibs #(
.ID( 1 ),
.NUM_STAGE( 1 ),
.din0_WIDTH( 8 ),
.din1_WIDTH( 23 ),
.din2_WIDTH( 32 ),
.dout_WIDTH( 32 ))
hls_contrast_streibs_U63(
.din0(ap_reg_pp0_iter2_i_op_assign_reg_789),
.din1(grp_fu_745_p1),
.din2(tmp2_reg_829),
.dout(grp_fu_745_p3)
);
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_CS_fsm <= ap_ST_fsm_state1;
end else begin
ap_CS_fsm <= ap_NS_fsm;
end
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_done_reg <= 1'b0;
end else begin
if ((ap_continue == 1'b1)) begin
ap_done_reg <= 1'b0;
end else if (((1'b1 == ap_CS_fsm_state2) & (tmp_i_fu_189_p2 == 1'd0))) begin
ap_done_reg <= 1'b1;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_enable_reg_pp0_iter0 <= 1'b0;
end else begin
if (((1'b0 == ap_block_pp0_stage0_subdone) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_condition_pp0_exit_iter0_state3))) begin
ap_enable_reg_pp0_iter0 <= 1'b0;
end else if (((tmp_i_fu_189_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin
ap_enable_reg_pp0_iter0 <= 1'b1;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_enable_reg_pp0_iter1 <= 1'b0;
end else begin
if ((1'b0 == ap_block_pp0_stage0_subdone)) begin
if ((1'b1 == ap_condition_pp0_exit_iter0_state3)) begin
ap_enable_reg_pp0_iter1 <= (1'b1 ^ ap_condition_pp0_exit_iter0_state3);
end else if ((1'b1 == 1'b1)) begin
ap_enable_reg_pp0_iter1 <= ap_enable_reg_pp0_iter0;
end
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_enable_reg_pp0_iter2 <= 1'b0;
end else begin
if ((1'b0 == ap_block_pp0_stage0_subdone)) begin
ap_enable_reg_pp0_iter2 <= ap_enable_reg_pp0_iter1;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_enable_reg_pp0_iter3 <= 1'b0;
end else begin
if ((1'b0 == ap_block_pp0_stage0_subdone)) begin
ap_enable_reg_pp0_iter3 <= ap_enable_reg_pp0_iter2;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_enable_reg_pp0_iter4 <= 1'b0;
end else begin
if ((1'b0 == ap_block_pp0_stage0_subdone)) begin
ap_enable_reg_pp0_iter4 <= ap_enable_reg_pp0_iter3;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_enable_reg_pp0_iter5 <= 1'b0;
end else begin
if ((1'b0 == ap_block_pp0_stage0_subdone)) begin
ap_enable_reg_pp0_iter5 <= ap_enable_reg_pp0_iter4;
end else if (((tmp_i_fu_189_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin
ap_enable_reg_pp0_iter5 <= 1'b0;
end
end
end
always @ (posedge ap_clk) begin
if ((1'b1 == ap_CS_fsm_state9)) begin
i_i_reg_163 <= i_reg_770;
end else if ((~((ap_start == 1'b0) | (p_src_cols_V_empty_n == 1'b0) | (p_src_rows_V_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
i_i_reg_163 <= 11'd0;
end
end
always @ (posedge ap_clk) begin
if (((tmp_35_i_fu_204_p2 == 1'd1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin
j_i_reg_174 <= j_fu_209_p2;
end else if (((tmp_i_fu_189_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin
j_i_reg_174 <= 11'd0;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0_11001))) begin
ap_reg_pp0_iter1_tmp_35_i_reg_775 <= tmp_35_i_reg_775;
tmp_35_i_reg_775 <= tmp_35_i_fu_204_p2;
end
end
always @ (posedge ap_clk) begin
if ((1'b0 == ap_block_pp0_stage0_11001)) begin
ap_reg_pp0_iter2_i_op_assign_reg_789 <= i_op_assign_reg_789;
ap_reg_pp0_iter2_tmp_35_i_reg_775 <= ap_reg_pp0_iter1_tmp_35_i_reg_775;
ap_reg_pp0_iter3_signbit_3_reg_839 <= signbit_3_reg_839;
ap_reg_pp0_iter3_signbit_reg_806 <= signbit_reg_806;
ap_reg_pp0_iter3_tmp_35_i_reg_775 <= ap_reg_pp0_iter2_tmp_35_i_reg_775;
ap_reg_pp0_iter4_signbit_2_reg_885 <= signbit_2_reg_885;
ap_reg_pp0_iter4_tmp_35_i_reg_775 <= ap_reg_pp0_iter3_tmp_35_i_reg_775;
end
end
always @ (posedge ap_clk) begin
if (((tmp_35_i_reg_775 == 1'd1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0_11001))) begin
i_op_assign_2_reg_795 <= i_op_assign_2_fu_221_p2;
i_op_assign_reg_789 <= i_op_assign_fu_215_p2;
tmp_39_reg_784 <= p_src_data_stream_0_V_dout;
end
end
always @ (posedge ap_clk) begin
if ((1'b1 == ap_CS_fsm_state2)) begin
i_reg_770 <= i_fu_194_p2;
end
end
always @ (posedge ap_clk) begin
if (((ap_reg_pp0_iter2_tmp_35_i_reg_775 == 1'd1) & (1'b0 == ap_block_pp0_stage0_11001))) begin
p_38_i_i_i1_i_reg_868 <= p_38_i_i_i1_i_fu_367_p2;
p_38_i_i_i21_i_reg_914 <= p_38_i_i_i21_i_fu_463_p2;
p_39_demorgan_i_i_i2_s_reg_874 <= p_39_demorgan_i_i_i2_s_fu_373_p2;
p_39_demorgan_i_i_i_reg_920 <= p_39_demorgan_i_i_i_fu_469_p2;
p_Val2_31_reg_908 <= p_Val2_31_fu_420_p2;
p_Val2_3_reg_862 <= p_Val2_3_fu_324_p2;
p_Val2_7_reg_892 <= {{grp_fu_745_p3[29:22]}};
signbit_2_reg_885 <= grp_fu_745_p3[32'd31];
tmp_29_reg_897 <= grp_fu_745_p3[32'd21];
tmp_5_reg_902 <= {{grp_fu_745_p3[31:30]}};
end
end
always @ (posedge ap_clk) begin
if (((ap_reg_pp0_iter3_tmp_35_i_reg_775 == 1'd1) & (1'b0 == ap_block_pp0_stage0_11001))) begin
p_38_i_i_i_i_reg_937 <= p_38_i_i_i_i_fu_585_p2;
p_39_demorgan_i_i_i_i_reg_943 <= p_39_demorgan_i_i_i_i_fu_591_p2;
p_Val2_33_reg_926 <= p_Val2_33_fu_524_p3;
p_Val2_8_reg_931 <= p_Val2_8_fu_542_p2;
p_Val2_s_reg_949 <= p_Val2_s_fu_646_p3;
end
end
always @ (posedge ap_clk) begin
if (((ap_reg_pp0_iter1_tmp_35_i_reg_775 == 1'd1) & (1'b0 == ap_block_pp0_stage0_11001))) begin
p_Val2_2_reg_813 <= {{grp_fu_713_p3[29:22]}};
p_Val2_30_reg_846 <= {{grp_fu_733_p3[29:22]}};
signbit_3_reg_839 <= grp_fu_733_p3[32'd31];
signbit_reg_806 <= grp_fu_713_p3[32'd31];
tmp_33_reg_851 <= grp_fu_733_p3[32'd21];
tmp_3_reg_823 <= {{grp_fu_713_p3[31:30]}};
tmp_7_reg_856 <= {{grp_fu_733_p3[31:30]}};
tmp_reg_818 <= grp_fu_713_p3[32'd21];
end
end
always @ (posedge ap_clk) begin
if ((~((ap_start == 1'b0) | (p_src_cols_V_empty_n == 1'b0) | (p_src_rows_V_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
p_src_cols_V_read_reg_756 <= p_src_cols_V_dout;
p_src_rows_V_read_reg_761 <= p_src_rows_V_dout;
end
end
always @ (posedge ap_clk) begin
if (((ap_reg_pp0_iter2_tmp_35_i_reg_775 == 1'd1) & (ap_enable_reg_pp0_iter3 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin
r_V_4_reg_880 <= grp_fu_745_p3;
end
end
always @ (posedge ap_clk) begin
if (((ap_reg_pp0_iter1_tmp_35_i_reg_775 == 1'd1) & (ap_enable_reg_pp0_iter2 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin
r_V_5_reg_834 <= grp_fu_733_p3;
r_V_reg_801 <= grp_fu_713_p3;
tmp2_reg_829 <= grp_fu_725_p3;
end
end
always @ (*) begin
if ((tmp_35_i_fu_204_p2 == 1'd0)) begin
ap_condition_pp0_exit_iter0_state3 = 1'b1;
end else begin
ap_condition_pp0_exit_iter0_state3 = 1'b0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state2) & (tmp_i_fu_189_p2 == 1'd0))) begin
ap_done = 1'b1;
end else begin
ap_done = ap_done_reg;
end
end
always @ (*) begin
if (((ap_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin
ap_idle = 1'b1;
end else begin
ap_idle = 1'b0;
end
end
always @ (*) begin
if (((ap_enable_reg_pp0_iter5 == 1'b0) & (ap_enable_reg_pp0_iter1 == 1'b0) & (ap_enable_reg_pp0_iter4 == 1'b0) & (ap_enable_reg_pp0_iter3 == 1'b0) & (ap_enable_reg_pp0_iter2 == 1'b0) & (ap_enable_reg_pp0_iter0 == 1'b0))) begin
ap_idle_pp0 = 1'b1;
end else begin
ap_idle_pp0 = 1'b0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state2) & (tmp_i_fu_189_p2 == 1'd0))) begin
ap_ready = 1'b1;
end else begin
ap_ready = 1'b0;
end
end
always @ (*) begin
if (((ap_reg_pp0_iter4_tmp_35_i_reg_775 == 1'd1) & (1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter5 == 1'b1))) begin
p_dst_data_stream_0_V_blk_n = p_dst_data_stream_0_V_full_n;
end else begin
p_dst_data_stream_0_V_blk_n = 1'b1;
end
end
always @ (*) begin
if (((ap_reg_pp0_iter4_tmp_35_i_reg_775 == 1'd1) & (ap_enable_reg_pp0_iter5 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin
p_dst_data_stream_0_V_write = 1'b1;
end else begin
p_dst_data_stream_0_V_write = 1'b0;
end
end
always @ (*) begin
if (((ap_reg_pp0_iter4_tmp_35_i_reg_775 == 1'd1) & (1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter5 == 1'b1))) begin
p_dst_data_stream_1_V_blk_n = p_dst_data_stream_1_V_full_n;
end else begin
p_dst_data_stream_1_V_blk_n = 1'b1;
end
end
always @ (*) begin
if (((ap_reg_pp0_iter4_tmp_35_i_reg_775 == 1'd1) & (ap_enable_reg_pp0_iter5 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin
p_dst_data_stream_1_V_write = 1'b1;
end else begin
p_dst_data_stream_1_V_write = 1'b0;
end
end
always @ (*) begin
if (((ap_reg_pp0_iter4_tmp_35_i_reg_775 == 1'd1) & (1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter5 == 1'b1))) begin
p_dst_data_stream_2_V_blk_n = p_dst_data_stream_2_V_full_n;
end else begin
p_dst_data_stream_2_V_blk_n = 1'b1;
end
end
always @ (*) begin
if (((ap_reg_pp0_iter4_tmp_35_i_reg_775 == 1'd1) & (ap_enable_reg_pp0_iter5 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin
p_dst_data_stream_2_V_write = 1'b1;
end else begin
p_dst_data_stream_2_V_write = 1'b0;
end
end
always @ (*) begin
if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
p_src_cols_V_blk_n = p_src_cols_V_empty_n;
end else begin
p_src_cols_V_blk_n = 1'b1;
end
end
always @ (*) begin
if ((~((ap_start == 1'b0) | (p_src_cols_V_empty_n == 1'b0) | (p_src_rows_V_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
p_src_cols_V_read = 1'b1;
end else begin
p_src_cols_V_read = 1'b0;
end
end
always @ (*) begin
if (((tmp_35_i_reg_775 == 1'd1) & (1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin
p_src_data_stream_0_V_blk_n = p_src_data_stream_0_V_empty_n;
end else begin
p_src_data_stream_0_V_blk_n = 1'b1;
end
end
always @ (*) begin
if (((tmp_35_i_reg_775 == 1'd1) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0_11001))) begin
p_src_data_stream_0_V_read = 1'b1;
end else begin
p_src_data_stream_0_V_read = 1'b0;
end
end
always @ (*) begin
if (((tmp_35_i_reg_775 == 1'd1) & (1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin
p_src_data_stream_1_V_blk_n = p_src_data_stream_1_V_empty_n;
end else begin
p_src_data_stream_1_V_blk_n = 1'b1;
end
end
always @ (*) begin
if (((tmp_35_i_reg_775 == 1'd1) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0_11001))) begin
p_src_data_stream_1_V_read = 1'b1;
end else begin
p_src_data_stream_1_V_read = 1'b0;
end
end
always @ (*) begin
if (((tmp_35_i_reg_775 == 1'd1) & (1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin
p_src_data_stream_2_V_blk_n = p_src_data_stream_2_V_empty_n;
end else begin
p_src_data_stream_2_V_blk_n = 1'b1;
end
end
always @ (*) begin
if (((tmp_35_i_reg_775 == 1'd1) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0_11001))) begin
p_src_data_stream_2_V_read = 1'b1;
end else begin
p_src_data_stream_2_V_read = 1'b0;
end
end
always @ (*) begin
if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
p_src_rows_V_blk_n = p_src_rows_V_empty_n;
end else begin
p_src_rows_V_blk_n = 1'b1;
end
end
always @ (*) begin
if ((~((ap_start == 1'b0) | (p_src_cols_V_empty_n == 1'b0) | (p_src_rows_V_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
p_src_rows_V_read = 1'b1;
end else begin
p_src_rows_V_read = 1'b0;
end
end
always @ (*) begin
case (ap_CS_fsm)
ap_ST_fsm_state1 : begin
if ((~((ap_start == 1'b0) | (p_src_cols_V_empty_n == 1'b0) | (p_src_rows_V_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
ap_NS_fsm = ap_ST_fsm_state2;
end else begin
ap_NS_fsm = ap_ST_fsm_state1;
end
end
ap_ST_fsm_state2 : begin
if (((1'b1 == ap_CS_fsm_state2) & (tmp_i_fu_189_p2 == 1'd0))) begin
ap_NS_fsm = ap_ST_fsm_state1;
end else begin
ap_NS_fsm = ap_ST_fsm_pp0_stage0;
end
end
ap_ST_fsm_pp0_stage0 : begin
if ((~((ap_enable_reg_pp0_iter1 == 1'b0) & (1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter0 == 1'b1) & (tmp_35_i_fu_204_p2 == 1'd0)) & ~((ap_enable_reg_pp0_iter4 == 1'b0) & (1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter5 == 1'b1)))) begin
ap_NS_fsm = ap_ST_fsm_pp0_stage0;
end else if ((((ap_enable_reg_pp0_iter4 == 1'b0) & (1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter5 == 1'b1)) | ((ap_enable_reg_pp0_iter1 == 1'b0) & (1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter0 == 1'b1) & (tmp_35_i_fu_204_p2 == 1'd0)))) begin
ap_NS_fsm = ap_ST_fsm_state9;
end else begin
ap_NS_fsm = ap_ST_fsm_pp0_stage0;
end
end
ap_ST_fsm_state9 : begin
ap_NS_fsm = ap_ST_fsm_state2;
end
default : begin
ap_NS_fsm = 'bx;
end
endcase
end
assign Range1_all_ones_1_fu_567_p2 = ((tmp_5_reg_902 == 2'd3) ? 1'b1 : 1'b0);
assign Range1_all_ones_2_fu_445_p2 = ((tmp_7_reg_856 == 2'd3) ? 1'b1 : 1'b0);
assign Range1_all_ones_fu_349_p2 = ((tmp_3_reg_823 == 2'd3) ? 1'b1 : 1'b0);
assign Range1_all_zeros_1_fu_572_p2 = ((tmp_5_reg_902 == 2'd0) ? 1'b1 : 1'b0);
assign Range1_all_zeros_2_fu_450_p2 = ((tmp_7_reg_856 == 2'd0) ? 1'b1 : 1'b0);
assign Range1_all_zeros_fu_354_p2 = ((tmp_3_reg_823 == 2'd0) ? 1'b1 : 1'b0);
assign ap_CS_fsm_pp0_stage0 = ap_CS_fsm[32'd2];
assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0];
assign ap_CS_fsm_state2 = ap_CS_fsm[32'd1];
assign ap_CS_fsm_state9 = ap_CS_fsm[32'd3];
assign ap_block_pp0_stage0 = ~(1'b1 == 1'b1);
always @ (*) begin
ap_block_pp0_stage0_01001 = (((ap_enable_reg_pp0_iter5 == 1'b1) & (((ap_reg_pp0_iter4_tmp_35_i_reg_775 == 1'd1) & (p_dst_data_stream_2_V_full_n == 1'b0)) | ((ap_reg_pp0_iter4_tmp_35_i_reg_775 == 1'd1) & (p_dst_data_stream_1_V_full_n == 1'b0)) | ((ap_reg_pp0_iter4_tmp_35_i_reg_775 == 1'd1) & (p_dst_data_stream_0_V_full_n == 1'b0)))) | ((ap_enable_reg_pp0_iter1 == 1'b1) & (((tmp_35_i_reg_775 == 1'd1) & (p_src_data_stream_2_V_empty_n == 1'b0)) | ((tmp_35_i_reg_775 == 1'd1) & (p_src_data_stream_1_V_empty_n == 1'b0)) | ((tmp_35_i_reg_775 == 1'd1) & (p_src_data_stream_0_V_empty_n == 1'b0)))));
end
always @ (*) begin
ap_block_pp0_stage0_11001 = (((ap_enable_reg_pp0_iter5 == 1'b1) & (((ap_reg_pp0_iter4_tmp_35_i_reg_775 == 1'd1) & (p_dst_data_stream_2_V_full_n == 1'b0)) | ((ap_reg_pp0_iter4_tmp_35_i_reg_775 == 1'd1) & (p_dst_data_stream_1_V_full_n == 1'b0)) | ((ap_reg_pp0_iter4_tmp_35_i_reg_775 == 1'd1) & (p_dst_data_stream_0_V_full_n == 1'b0)))) | ((ap_enable_reg_pp0_iter1 == 1'b1) & (((tmp_35_i_reg_775 == 1'd1) & (p_src_data_stream_2_V_empty_n == 1'b0)) | ((tmp_35_i_reg_775 == 1'd1) & (p_src_data_stream_1_V_empty_n == 1'b0)) | ((tmp_35_i_reg_775 == 1'd1) & (p_src_data_stream_0_V_empty_n == 1'b0)))));
end
always @ (*) begin
ap_block_pp0_stage0_subdone = (((ap_enable_reg_pp0_iter5 == 1'b1) & (((ap_reg_pp0_iter4_tmp_35_i_reg_775 == 1'd1) & (p_dst_data_stream_2_V_full_n == 1'b0)) | ((ap_reg_pp0_iter4_tmp_35_i_reg_775 == 1'd1) & (p_dst_data_stream_1_V_full_n == 1'b0)) | ((ap_reg_pp0_iter4_tmp_35_i_reg_775 == 1'd1) & (p_dst_data_stream_0_V_full_n == 1'b0)))) | ((ap_enable_reg_pp0_iter1 == 1'b1) & (((tmp_35_i_reg_775 == 1'd1) & (p_src_data_stream_2_V_empty_n == 1'b0)) | ((tmp_35_i_reg_775 == 1'd1) & (p_src_data_stream_1_V_empty_n == 1'b0)) | ((tmp_35_i_reg_775 == 1'd1) & (p_src_data_stream_0_V_empty_n == 1'b0)))));
end
always @ (*) begin
ap_block_state1 = ((ap_start == 1'b0) | (p_src_cols_V_empty_n == 1'b0) | (p_src_rows_V_empty_n == 1'b0) | (ap_done_reg == 1'b1));
end
assign ap_block_state3_pp0_stage0_iter0 = ~(1'b1 == 1'b1);
always @ (*) begin
ap_block_state4_pp0_stage0_iter1 = (((tmp_35_i_reg_775 == 1'd1) & (p_src_data_stream_2_V_empty_n == 1'b0)) | ((tmp_35_i_reg_775 == 1'd1) & (p_src_data_stream_1_V_empty_n == 1'b0)) | ((tmp_35_i_reg_775 == 1'd1) & (p_src_data_stream_0_V_empty_n == 1'b0)));
end
assign ap_block_state5_pp0_stage0_iter2 = ~(1'b1 == 1'b1);
assign ap_block_state6_pp0_stage0_iter3 = ~(1'b1 == 1'b1);
assign ap_block_state7_pp0_stage0_iter4 = ~(1'b1 == 1'b1);
always @ (*) begin
ap_block_state8_pp0_stage0_iter5 = (((ap_reg_pp0_iter4_tmp_35_i_reg_775 == 1'd1) & (p_dst_data_stream_2_V_full_n == 1'b0)) | ((ap_reg_pp0_iter4_tmp_35_i_reg_775 == 1'd1) & (p_dst_data_stream_1_V_full_n == 1'b0)) | ((ap_reg_pp0_iter4_tmp_35_i_reg_775 == 1'd1) & (p_dst_data_stream_0_V_full_n == 1'b0)));
end
assign ap_enable_pp0 = (ap_idle_pp0 ^ 1'b1);
assign brmerge_i_i29_i_fu_626_p2 = (p_39_demorgan_i_not_i_3_fu_621_p2 | neg_src_not_i_i26_i_fu_611_p2);
assign brmerge_i_i6_i_fu_504_p2 = (p_39_demorgan_i_not_i_fu_499_p2 | neg_src_not_i_i3_i_fu_489_p2);
assign brmerge_i_i_i_fu_684_p2 = (p_39_demorgan_i_not_i_2_fu_679_p2 | neg_src_not_i_i_i_fu_669_p2);
assign brmerge_i_i_not_i_i2_fu_616_p2 = (p_39_demorgan_i_i_i_reg_920 & neg_src_not_i_i26_i_fu_611_p2);
assign brmerge_i_i_not_i_i4_fu_494_p2 = (p_39_demorgan_i_i_i2_s_reg_874 & neg_src_not_i_i3_i_fu_489_p2);
assign brmerge_i_i_not_i_i_s_fu_674_p2 = (p_39_demorgan_i_i_i_i_reg_943 & neg_src_not_i_i_i_fu_669_p2);
assign carry_1_fu_561_p2 = (tmp_30_fu_535_p3 & tmp_14_i_i_i_fu_555_p2);
assign carry_2_fu_439_p2 = (tmp_34_fu_413_p3 & tmp_17_i_i16_i_fu_433_p2);
assign carry_fu_343_p2 = (tmp_26_fu_317_p3 & tmp_17_i_i_i_fu_337_p2);
assign deleted_zeros_1_fu_577_p3 = ((carry_1_fu_561_p2[0:0] === 1'b1) ? Range1_all_ones_1_fu_567_p2 : Range1_all_zeros_1_fu_572_p2);
assign deleted_zeros_2_fu_455_p3 = ((carry_2_fu_439_p2[0:0] === 1'b1) ? Range1_all_ones_2_fu_445_p2 : Range1_all_zeros_2_fu_450_p2);
assign deleted_zeros_fu_359_p3 = ((carry_fu_343_p2[0:0] === 1'b1) ? Range1_all_ones_fu_349_p2 : Range1_all_zeros_fu_354_p2);
assign grp_fu_713_p1 = 32'd5884608;
assign grp_fu_713_p2 = tmp_22_cast_i_fu_237_p1;
assign grp_fu_725_p1 = 30'd1072298983;
assign grp_fu_725_p2 = tmp_22_cast_i_fu_237_p1;
assign grp_fu_733_p1 = 32'd7436500;
assign grp_fu_733_p2 = tmp_22_cast_i_fu_237_p1;
assign grp_fu_745_p1 = 31'd2144488914;
assign i_cast_i_cast_fu_185_p1 = i_i_reg_163;
assign i_fu_194_p2 = (i_i_reg_163 + 11'd1);
assign i_op_assign_2_fu_221_p2 = (p_src_data_stream_2_V_dout ^ 8'd128);
assign i_op_assign_fu_215_p2 = (p_src_data_stream_1_V_dout ^ 8'd128);
assign j_cast_i_cast_fu_200_p1 = j_i_reg_174;
assign j_fu_209_p2 = (j_i_reg_174 + 11'd1);
assign neg_src_10_fu_659_p2 = (tmp_15_i_i_i_fu_654_p2 & ap_reg_pp0_iter4_signbit_2_reg_885);
assign neg_src_9_fu_479_p2 = (tmp_18_i_i_i_fu_474_p2 & ap_reg_pp0_iter3_signbit_reg_806);
assign neg_src_fu_601_p2 = (tmp_18_i_i22_i_fu_596_p2 & ap_reg_pp0_iter3_signbit_3_reg_839);
assign neg_src_not_i_i26_i_fu_611_p2 = (signbit_not_i25_i_fu_606_p2 | p_38_i_i_i21_i_reg_914);
assign neg_src_not_i_i3_i_fu_489_p2 = (signbit_not_i_i_fu_484_p2 | p_38_i_i_i1_i_reg_868);
assign neg_src_not_i_i_i_fu_669_p2 = (signbit_not_i_fu_664_p2 | p_38_i_i_i_i_reg_937);
assign p_38_i_i_i1_i_fu_367_p2 = (carry_fu_343_p2 & Range1_all_ones_fu_349_p2);
assign p_38_i_i_i21_i_fu_463_p2 = (carry_2_fu_439_p2 & Range1_all_ones_2_fu_445_p2);
assign p_38_i_i_i_i_fu_585_p2 = (carry_1_fu_561_p2 & Range1_all_ones_1_fu_567_p2);
assign p_39_demorgan_i_i_i2_s_fu_373_p2 = (signbit_reg_806 | deleted_zeros_fu_359_p3);
assign p_39_demorgan_i_i_i_fu_469_p2 = (signbit_3_reg_839 | deleted_zeros_2_fu_455_p3);
assign p_39_demorgan_i_i_i_i_fu_591_p2 = (signbit_2_reg_885 | deleted_zeros_1_fu_577_p3);
assign p_39_demorgan_i_not_i_2_fu_679_p2 = (p_39_demorgan_i_i_i_i_reg_943 ^ 1'd1);
assign p_39_demorgan_i_not_i_3_fu_621_p2 = (p_39_demorgan_i_i_i_reg_920 ^ 1'd1);
assign p_39_demorgan_i_not_i_fu_499_p2 = (p_39_demorgan_i_i_i2_s_reg_874 ^ 1'd1);
assign p_Val2_31_fu_420_p2 = (tmp_16_i_i12_i_fu_410_p1 + p_Val2_30_reg_846);
assign p_Val2_33_fu_524_p3 = ((brmerge_i_i6_i_fu_504_p2[0:0] === 1'b1) ? p_mux_i_i7_i_fu_510_p3 : p_i_i8_i_fu_517_p3);
assign p_Val2_3_fu_324_p2 = (tmp_16_i_i_i_fu_314_p1 + p_Val2_2_reg_813);
assign p_Val2_8_fu_542_p2 = (tmp_13_i_i_i_fu_532_p1 + p_Val2_7_reg_892);
assign p_Val2_s_fu_646_p3 = ((brmerge_i_i29_i_fu_626_p2[0:0] === 1'b1) ? p_mux_i_i30_i_fu_632_p3 : p_i_i31_i_fu_639_p3);
assign p_dst_data_stream_0_V_din = p_Val2_33_reg_926;
assign p_dst_data_stream_1_V_din = ((brmerge_i_i_i_fu_684_p2[0:0] === 1'b1) ? p_mux_i_i_i_fu_690_p3 : p_i_i_i_fu_697_p3);
assign p_dst_data_stream_2_V_din = p_Val2_s_reg_949;
assign p_i_i31_i_fu_639_p3 = ((neg_src_fu_601_p2[0:0] === 1'b1) ? 8'd0 : p_Val2_31_reg_908);
assign p_i_i8_i_fu_517_p3 = ((neg_src_9_fu_479_p2[0:0] === 1'b1) ? 8'd0 : p_Val2_3_reg_862);
assign p_i_i_i_fu_697_p3 = ((neg_src_10_fu_659_p2[0:0] === 1'b1) ? 8'd0 : p_Val2_8_reg_931);
assign p_mux_i_i30_i_fu_632_p3 = ((brmerge_i_i_not_i_i2_fu_616_p2[0:0] === 1'b1) ? p_Val2_31_reg_908 : 8'd255);
assign p_mux_i_i7_i_fu_510_p3 = ((brmerge_i_i_not_i_i4_fu_494_p2[0:0] === 1'b1) ? p_Val2_3_reg_862 : 8'd255);
assign p_mux_i_i_i_fu_690_p3 = ((brmerge_i_i_not_i_i_s_fu_674_p2[0:0] === 1'b1) ? p_Val2_8_reg_931 : 8'd255);
assign signbit_not_i25_i_fu_606_p2 = (ap_reg_pp0_iter3_signbit_3_reg_839 ^ 1'd1);
assign signbit_not_i_fu_664_p2 = (ap_reg_pp0_iter4_signbit_2_reg_885 ^ 1'd1);
assign signbit_not_i_i_fu_484_p2 = (ap_reg_pp0_iter3_signbit_reg_806 ^ 1'd1);
assign tmp_13_i_i_i_fu_532_p1 = tmp_29_reg_897;
assign tmp_14_i_i_i_fu_555_p2 = (tmp_31_fu_547_p3 ^ 1'd1);
assign tmp_15_i_i_i_fu_654_p2 = (p_38_i_i_i_i_reg_937 ^ 1'd1);
assign tmp_16_i_i12_i_fu_410_p1 = tmp_33_reg_851;
assign tmp_16_i_i_i_fu_314_p1 = tmp_reg_818;
assign tmp_17_i_i16_i_fu_433_p2 = (tmp_35_fu_425_p3 ^ 1'd1);
assign tmp_17_i_i_i_fu_337_p2 = (tmp_27_fu_329_p3 ^ 1'd1);
assign tmp_18_i_i22_i_fu_596_p2 = (p_38_i_i_i21_i_reg_914 ^ 1'd1);
assign tmp_18_i_i_i_fu_474_p2 = (p_38_i_i_i1_i_reg_868 ^ 1'd1);
assign tmp_22_cast_i_fu_237_p1 = tmp_i1_fu_230_p3;
assign tmp_26_fu_317_p3 = r_V_reg_801[32'd29];
assign tmp_27_fu_329_p3 = p_Val2_3_fu_324_p2[32'd7];
assign tmp_30_fu_535_p3 = r_V_4_reg_880[32'd29];
assign tmp_31_fu_547_p3 = p_Val2_8_fu_542_p2[32'd7];
assign tmp_34_fu_413_p3 = r_V_5_reg_834[32'd29];
assign tmp_35_fu_425_p3 = p_Val2_31_fu_420_p2[32'd7];
assign tmp_35_i_fu_204_p2 = ((j_cast_i_cast_fu_200_p1 < p_src_cols_V_read_reg_756) ? 1'b1 : 1'b0);
assign tmp_i1_fu_230_p3 = {{tmp_39_reg_784}, {22'd0}};
assign tmp_i_fu_189_p2 = ((i_cast_i_cast_fu_185_p1 < p_src_rows_V_read_reg_761) ? 1'b1 : 1'b0);
endmodule |
module tb_n();
reg clk;
reg reset_n;
reg [15:0] in_data;
reg in_dv;
reg in_fv;
wire out_fv;
wire out_dv;
wire [15:0] out_data;
reg [15:0] out_data_s;
integer fp_out;
integer fp_in;
integer fp_norm;
integer dummy;
reg [31:0] counter;
reg [31:0] toto;
initial begin
$dumpfile("/tmp/tb_n.vcd");
$dumpvars;
fp_out = $fopen("data_out.txt", "w");
fp_norm = $fopen("data_norm.txt", "w");
fp_in = $fopen("input.txt", "r");
clk = 0;
reset_n = 1;
in_dv =0;
in_data =0;
counter = 0;
toto = 0;
#1 reset_n = 1'd0;
#4 reset_n = 1'd1;
end
always #1 clk = ~clk;
always@(posedge clk)
if (reset_n == 0)
in_dv <= 0;
else
if (counter < 15 || toto > 1)
in_dv <= $random;
else
in_dv <= 0;
always@(posedge clk)
if (reset_n == 0)
in_fv <= 0;
else
if (counter < 15 || toto > 1)
in_fv <= 1;
else
in_fv <= 0;
always@(posedge clk)
if (reset_n == 0)
toto <= 0;
else
if(counter >= 15)
toto <= toto + 1;
always@(posedge clk)
if (reset_n == 0)
in_data <= 0;
else
if (counter < 15 || toto > 1)
//in_data <= $random;
dummy = $fscanf(fp_in,"%d\n",in_data);
else
in_data <= 0;
always@(posedge clk)
if (reset_n == 0)
counter <= 0;
else
if (in_dv)
counter <= counter + 1;
always@(posedge clk)
if (in_fv & in_dv)
$fwrite(fp_out, "%d\n", in_data);
always@(*)
out_data_s = out_data;
always@(posedge clk)
if (out_fv & out_dv)
$fwrite(fp_norm, "%d\n", out_data_s);
norm norm_inst(
.clk_proc(clk),
.reset_n(reset_n),
.in_fv(in_fv),
.in_dv(in_dv),
.in_data(in_data),
.out_fv(out_fv),
.out_dv(out_dv),
.out_data(out_data),
.addr_rel_i(),
.wr_i(),
.datawr_i(),
.rd_i(),
.datard_o()
);
endmodule |
module sky130_fd_sc_hdll__sdlclkp (
GCLK,
SCE ,
GATE,
CLK ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output GCLK;
input SCE ;
input GATE;
input CLK ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire m0 ;
wire m0n ;
wire clkn ;
wire CLK_delayed ;
wire SCE_delayed ;
wire GATE_delayed ;
wire SCE_gate_delayed;
reg notifier ;
wire awake ;
wire SCE_awake ;
wire GATE_awake ;
// Name Output Other arguments
not not0 (m0n , m0 );
not not1 (clkn , CLK_delayed );
nor nor0 (SCE_gate_delayed, GATE_delayed, SCE_delayed );
sky130_fd_sc_hdll__udp_dlatch$P_pp$PG$N dlatch0 (m0 , SCE_gate_delayed, clkn, notifier, VPWR, VGND);
and and0 (GCLK , m0n, CLK_delayed );
assign awake = ( VPWR === 1'b1 );
assign SCE_awake = ( awake & ( GATE_delayed === 1'b0 ) );
assign GATE_awake = ( awake & ( SCE_delayed === 1'b0 ) );
endmodule |
module tb_lab4dpath;
// Inputs
reg [9:0] x1;
reg [9:0] x2;
reg [9:0] x3;
// Outputs
wire [9:0] y;
reg clock;
reg[8*100:1] aline;
`define FSIZE 1024
`define LATENCY 3
integer infifo[(`FSIZE-1):0];
integer head,tail;
integer fd;
integer count,status;
integer i_a, i_b, i_c, i_result;
integer o_a, o_b, o_c, o_result;
integer errors;
integer clock_count;
// Instantiate the Unit Under Test (UUT)
lab4dpath uut (
.x1(x1),
.x2(x2),
.x3(x3),
.clk(clock),
.y(y)
);
initial begin
clock = 0;
#100 //reset delay
forever #25 clock = ~clock;
end
initial begin
// Initialize Inputs
x1 = 0;
x2 = 0;
x3 = 0;
head = 0;
tail = 0;
clock_count = 0;
fd = $fopen("multadd_vectors.txt","r");
count = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
// Add stimulus here
errors = 0;
while ($fgets(aline,fd)) begin
status = $sscanf(aline,"%x %x %x %x",i_a, i_b, i_c, i_result);
@(negedge clock);
x1 = i_a;
x2 = i_b;
x3 = i_c;
infifo[head]=i_a;inc_head;
infifo[head]=i_b;inc_head;
infifo[head]=i_c;inc_head;
infifo[head]=i_result;inc_head;
end //end while
end
task inc_head;
begin
head = head + 1;
if (head == `FSIZE) head = 0;
end
endtask
task inc_tail;
begin
tail = tail + 1;
if (tail == `FSIZE) tail = 0;
end
endtask
always @(negedge clock) begin
clock_count = clock_count + 1;
if (clock_count > `LATENCY+1) begin
o_a = infifo[tail];inc_tail;
o_b = infifo[tail];inc_tail;
o_c = infifo[tail];inc_tail;
o_result = infifo[tail];inc_tail;
if (o_result == y) begin
$display("%d PASS, x1: %x, x2: %x, x3: %x, y: %x\n",count,o_a,o_b,o_c,y);
end else begin
$display("%d FAIL, x1: %x, x2: %x, x3: %x, y (actual): %x, y (expected): %x\n",count,o_a,o_b,o_c,y,o_result);
errors = errors + 1;
end
end //end if
end
endmodule |
module ALU4_LA(a, b, c_in, c_out, less, sel, out, P, G);
input less;
input [3:0] a, b;
input [2:0] sel;
input c_in;
output [3:0] out;
output P,G;
output c_out;
wire [2:0] c;
wire [3:0] p, g;
alu_slice_LA a1(a[0], b[0], c_in, less, sel, out[0], p[0], g[0]);
alu_slice_LA a2(a[1], b[1], c[0], 1'b0, sel, out[1], p[1], g[1]);
alu_slice_LA a3(a[2], b[2], c[1], 1'b0, sel, out[2], p[2], g[2]);
alu_slice_LA a4(a[3], b[3], c[2], 1'b0, sel, out[3], p[3], g[3]);
lookahead l1(c_in, c_out, c, p, g, P, G);
endmodule |
module uart_tfifo (clk,
wb_rst_i, data_in, data_out,
// Control signals
push, // push strobe, active high
pop, // pop strobe, active high
// status signals
overrun,
count,
fifo_reset,
reset_status
);
// FIFO parameters
parameter fifo_width = `UART_FIFO_WIDTH;
parameter fifo_depth = `UART_FIFO_DEPTH;
parameter fifo_pointer_w = `UART_FIFO_POINTER_W;
parameter fifo_counter_w = `UART_FIFO_COUNTER_W;
input clk;
input wb_rst_i;
input push;
input pop;
input [fifo_width-1:0] data_in;
input fifo_reset;
input reset_status;
output [fifo_width-1:0] data_out;
output overrun;
output [fifo_counter_w-1:0] count;
wire [fifo_width-1:0] data_out;
// FIFO pointers
reg [fifo_pointer_w-1:0] top;
reg [fifo_pointer_w-1:0] bottom;
reg [fifo_counter_w-1:0] count;
reg overrun;
wire [fifo_pointer_w-1:0] top_plus_1 = top + 1'b1;
raminfr #(fifo_pointer_w,fifo_width,fifo_depth) tfifo
(.clk(clk),
.we(push),
.a(top),
.dpra(bottom),
.di(data_in),
.dpo(data_out)
);
always @(posedge clk or posedge wb_rst_i) // synchronous FIFO
begin
if (wb_rst_i)
begin
top <= #1 0;
bottom <= #1 1'b0;
count <= #1 0;
end
else
if (fifo_reset) begin
top <= #1 0;
bottom <= #1 1'b0;
count <= #1 0;
end
else
begin
case ({push, pop})
2'b10 : if (count<fifo_depth) // overrun condition
begin
top <= #1 top_plus_1;
count <= #1 count + 1'b1;
end
2'b01 : if(count>0)
begin
bottom <= #1 bottom + 1'b1;
count <= #1 count - 1'b1;
end
2'b11 : begin
bottom <= #1 bottom + 1'b1;
top <= #1 top_plus_1;
end
default: ;
endcase
end
end // always
always @(posedge clk or posedge wb_rst_i) // synchronous FIFO
begin
if (wb_rst_i)
overrun <= #1 1'b0;
else
if(fifo_reset | reset_status)
overrun <= #1 1'b0;
else
if(push & (count==fifo_depth))
overrun <= #1 1'b1;
end // always
endmodule |
module sky130_fd_sc_hd__dlxbp (
Q ,
Q_N ,
D ,
GATE,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Q ;
output Q_N ;
input D ;
input GATE;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire buf_Q;
// Delay Name Output Other arguments
sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N `UNIT_DELAY dlatch0 (buf_Q , D, GATE, , VPWR, VGND);
buf buf0 (Q , buf_Q );
not not0 (Q_N , buf_Q );
endmodule |
module io_1to2
#(parameter
MIN_ADDR=1,
MAX_ADDR=1,
OPER_1=`NS_GT_OP,
REF_VAL_1=0,
IS_RANGE=`NS_FALSE,
OPER_2=`NS_GT_OP,
REF_VAL_2=0,
ASZ=`NS_ADDRESS_SIZE,
DSZ=`NS_DATA_SIZE,
RSZ=`NS_REDUN_SIZE
)(
input wire src0_clk,
input wire snk0_clk,
input wire snk1_clk,
input wire reset,
// SRC
`NS_DECLARE_OUT_CHNL(o0),
// SNK_0
`NS_DECLARE_IN_CHNL(i0),
// SNK_1
`NS_DECLARE_IN_CHNL(i1),
`NS_DECLARE_DBG_CHNL(dbg)
);
parameter RCV_REQ_CKS = `NS_REQ_CKS;
parameter SND_ACK_CKS = `NS_ACK_CKS;
`NS_DEBOUNCER_ACK(src0_clk, reset, o0)
`NS_DEBOUNCER_REQ(snk0_clk, reset, i0)
`NS_DEBOUNCER_REQ(snk1_clk, reset, i1)
`NS_DECLARE_REG_DBG(rg_dbg)
reg [RSZ-1:0] err_mg_redun = 0;
reg [3:0] cnt_0 = 0;
reg [3:0] cnt_1 = 0;
reg [DSZ-1:0] r_dat1 = 0;
// SRC regs
reg [0:0] ro0_has_dst = `NS_OFF;
reg [0:0] ro0_has_dat = `NS_OFF;
reg [0:0] ro0_has_red = `NS_OFF;
reg [0:0] ro0_busy = `NS_OFF;
reg [ASZ-1:0] ro0_src = `NS_DBG_SRC;
reg [DSZ-1:0] ro0_dat = 0;
reg [ASZ-1:0] ro0_dst = MIN_ADDR;
reg [RSZ-1:0] ro0_red = 0;
reg [0:0] ro0_req = `NS_OFF;
reg [0:0] ro0_err = `NS_OFF;
// SNK_0 regs
reg [0:0] has_inp0 = `NS_OFF;
reg [0:0] inp0_has_redun = `NS_OFF;
reg [0:0] inp0_done_cks = `NS_OFF;
`NS_DECLARE_REG_MSG(inp0)
wire [RSZ-1:0] inp0_calc_redun;
reg [RSZ-1:0] inp0_redun = 0;
calc_redun #(.ASZ(ASZ), .DSZ(DSZ), .RSZ(RSZ))
md_calc_red0 (inp0_src, inp0_dst, inp0_dat, inp0_calc_redun);
reg [0:0] inp0_ack = `NS_OFF;
reg [DSZ-1:0] inp0_back_dat = 15;
//reg [ASZ-1:0] inp0_back_dst = 0;
reg [0:0] inp0_err = `NS_OFF;
// SNK_1 regs
reg [3:0] err1_case = 0;
reg [0:0] has_inp1 = `NS_OFF;
reg [0:0] inp1_has_redun = `NS_OFF;
reg [0:0] inp1_done_cks = `NS_OFF;
`NS_DECLARE_REG_MSG(inp1)
wire [RSZ-1:0] inp1_calc_redun;
reg [RSZ-1:0] inp1_redun = 0;
calc_redun #(.ASZ(ASZ), .DSZ(DSZ), .RSZ(RSZ))
md_calc_red1 (inp1_src, inp1_dst, inp1_dat, inp1_calc_redun);
reg [0:0] inp1_ack = `NS_OFF;
reg [DSZ-1:0] inp1_back_dat = 15;
reg [0:0] inp1_err = `NS_OFF;
//reg r_curr_src = 0;
wire [RSZ-1:0] ro0_redun;
calc_redun #(.ASZ(ASZ), .DSZ(DSZ), .RSZ(RSZ))
r1 (ro0_src, ro0_dst, ro0_dat, ro0_redun);
//SRC
always @(posedge src0_clk)
begin
if((! ro0_req) && (! o0_ckd_ack)) begin
if(! ro0_has_dst) begin
ro0_has_dst <= `NS_ON;
ro0_dst <= `NS_DBG_NXT_ADDR(ro0_dst);
end
else
if(! ro0_has_dat) begin
ro0_has_dat <= `NS_ON;
/*if(ro0_dat > 15) begin
ro0_err <= `NS_ON;
end
if(ro0_dat < 0) begin
ro0_err <= `NS_ON;
end*/
if(! `NS_RANGE_CMP_OP(IS_RANGE, OPER_1, REF_VAL_1, ro0_dst, OPER_2, REF_VAL_2, ro0_dst)) begin
ro0_dat[3:0] <= cnt_0;
cnt_0 <= cnt_0 + 1;
end else begin
ro0_dat[3:0] <= cnt_1;
cnt_1 <= cnt_1 + 1;
end
end
else
if(! ro0_has_red) begin
ro0_has_red <= `NS_ON;
ro0_red <= ro0_redun;
end
if(ro0_has_red) begin
ro0_req <= `NS_ON;
end
end
if(ro0_req && o0_ckd_ack) begin
ro0_has_dst <= `NS_OFF;
ro0_has_dat <= `NS_OFF;
ro0_has_red <= `NS_OFF;
ro0_req <= `NS_OFF;
end
end
//SNK_0
always @(posedge snk0_clk)
begin
if(i0_ckd_req && (! inp0_ack)) begin
if(! has_inp0) begin
has_inp0 <= `NS_ON;
`NS_MOV_REG_MSG(inp0, i0)
end
else
if(! inp0_has_redun) begin
inp0_has_redun <= `NS_ON;
inp0_redun <= inp0_calc_redun;
end
else
if(! inp0_done_cks) begin
inp0_done_cks <= `NS_ON;
if(! inp0_err) begin
if(! `NS_RANGE_CMP_OP(IS_RANGE, OPER_1, REF_VAL_1, inp0_dst, OPER_2, REF_VAL_2, inp0_dst)) begin
inp0_err <= `NS_ON;
end
else
if(inp0_src != `NS_DBG_SRC) begin
inp0_err <= `NS_ON;
end
/*else
if(inp0_dat > 15) begin
inp0_err <= `NS_ON;
end
else
if(inp0_dat < 0) begin
inp0_err <= `NS_ON;
end*/
else
if(inp0_red != inp0_redun) begin
inp0_err <= `NS_ON;
end
//else
if((inp0_back_dat <= 14) && ((inp0_back_dat + 1) != inp0_dat)) begin
inp0_err <= `NS_ON;
//rg_dbg_disp0 <= inp0_back_dat[3:0];
//rg_dbg_disp1 <= inp0_dat[3:0];
end
else
begin
inp0_back_dat <= inp0_dat;
end
end
end
if(inp0_done_cks) begin
rg_dbg_disp0 <= inp0_dat[3:0];
has_inp0 <= `NS_OFF;
inp0_has_redun <= `NS_OFF;
inp0_done_cks <= `NS_OFF;
inp0_ack <= `NS_ON;
end
end
else
if((! i0_ckd_req) && inp0_ack) begin
inp0_ack <= `NS_OFF;
end
end
//SNK_1
always @(posedge snk1_clk)
begin
if(i1_ckd_req && (! inp1_ack)) begin
if(! has_inp1) begin
has_inp1 <= `NS_ON;
`NS_MOV_REG_MSG(inp1, i1)
end
else
if(! inp1_has_redun) begin
inp1_has_redun <= `NS_ON;
inp1_redun <= inp1_calc_redun;
end
else
if(! inp1_done_cks) begin
inp1_done_cks <= `NS_ON;
if(! inp1_err) begin
if(`NS_RANGE_CMP_OP(IS_RANGE, OPER_1, REF_VAL_1, inp1_dst, OPER_2, REF_VAL_2, inp1_dst)) begin
inp1_err <= `NS_ON;
end
else
if(inp1_src != `NS_DBG_SRC) begin
inp1_err <= `NS_ON;
end
/*else
if(inp1_dat > 15) begin
inp1_err <= `NS_ON;
end
else
if(inp1_dat < 0) begin
inp1_err <= `NS_ON;
end*/
else
if(inp1_red != inp1_redun) begin
inp1_err <= `NS_ON;
end
//else
if((inp1_back_dat <= 14) && ((inp1_back_dat + 1) != inp1_dat)) begin
inp1_err <= `NS_ON;
end
else
begin
inp1_back_dat <= inp1_dat;
end
end
end
if(inp1_done_cks) begin
rg_dbg_disp1 <= inp1_dat[3:0];
has_inp1 <= `NS_OFF;
inp1_has_redun <= `NS_OFF;
inp1_done_cks <= `NS_OFF;
inp1_ack <= `NS_ON;
end
end
else
if((! i1_ckd_req) && inp1_ack) begin
inp1_ack <= `NS_OFF;
end
end
//DBG
/*
always @(posedge dbg_clk)
begin
case(dbg_case)
8'h30 :
begin
end
endcase
end
*/
//SRC
`NS_ASSIGN_MSG(o0, ro0)
assign o0_req_out = ro0_req;
//SNK_0
assign i0_ack_out = inp0_ack;
//SNK_1
assign i1_ack_out = inp1_ack;
//`NS_ASSIGN_OUT_DBG(dbg, rg_dbg)
assign dbg_leds[0:0] = inp0_err;
assign dbg_leds[1:1] = inp1_err;
assign dbg_leds[2:2] = ro0_err;
assign dbg_leds[3:3] = 0;
assign dbg_disp0 = rg_dbg_disp0;
assign dbg_disp1 = rg_dbg_disp1;
endmodule |
module rom32(address, data_out);
input [31:0] address;
output [31:0] data_out;
reg [31:0] data_out;
parameter BASE_ADDRESS = 25'd0; // address that applies to this memory
wire [5:0] mem_offset;
wire address_select;
assign mem_offset = address[7:2]; // drop 2 LSBs to get word offset
assign address_select = (address[31:8] == BASE_ADDRESS); // address decoding
always @(address_select or mem_offset)
begin
if ((address % 4) != 0) $display($time, " rom32 error: unaligned address %d", address);
if (address_select == 1)
begin
case (mem_offset)
5'd0 : data_out = { 6'd35, 5'd0, 5'd2, 16'd4 };//lw $2, 4($0) r2=1
5'd1 : data_out = { 6'd0, 5'd2, 5'd2, 5'd3, 5'd0, 6'd32 }; //add $3, $2, $2
5'd2 : data_out = { 6'd2, 26'd0 }; //J 0
// add more cases here as desired
default data_out = 32'hxxxx;
endcase
$display($time, " reading data: rom32[%h] => %h", address, data_out);
end
end
endmodule |
module tv80_reg (/*AUTOARG*/
// Outputs
DOBH, DOAL, DOCL, DOBL, DOCH, DOAH,
// Inputs
AddrC, AddrA, AddrB, DIH, DIL, clk, CEN, WEH, WEL
);
input [2:0] AddrC;
output [7:0] DOBH;
input [2:0] AddrA;
input [2:0] AddrB;
input [7:0] DIH;
output [7:0] DOAL;
output [7:0] DOCL;
input [7:0] DIL;
output [7:0] DOBL;
output [7:0] DOCH;
output [7:0] DOAH;
input clk, CEN, WEH, WEL;
reg [7:0] RegsH [0:7];
reg [7:0] RegsL [0:7];
always @(posedge clk)
begin
if (CEN)
begin
if (WEH) RegsH[AddrA] <= DIH;
if (WEL) RegsL[AddrA] <= DIL;
end
end
assign DOAH = RegsH[AddrA];
assign DOAL = RegsL[AddrA];
assign DOBH = RegsH[AddrB];
assign DOBL = RegsL[AddrB];
assign DOCH = RegsH[AddrC];
assign DOCL = RegsL[AddrC];
// break out ram bits for waveform debug
wire [7:0] H = RegsH[2];
wire [7:0] L = RegsL[2];
// synopsys dc_script_begin
// set_attribute current_design "revision" "$Id: tv80_reg.v,v 1.1 2004/05/16 17:39:57 ghutchis Exp $" -type string -quiet
// synopsys dc_script_end
endmodule |
module branch(
input branch_d,
input [3:0] branch_condition_d,
input Z,
input N,
input V,
input C,
output reg PC_source
);
reg branch_taken;
always @(*) begin
case (branch_condition_d)
4'h0: branch_taken <= Z;
4'h1: branch_taken <= ~Z;
4'h2: branch_taken <= C;
4'h3: branch_taken <= ~C;
4'h4: branch_taken <= N;
4'h5: branch_taken <= ~N;
4'h6: branch_taken <= V;
4'h7: branch_taken <= ~V;
4'h8: branch_taken <= C & ~Z;
4'h9: branch_taken <= Z | ~C;
4'ha: branch_taken <= ~(N ^ V);
4'hb: branch_taken <= N ^ V;
4'hc: branch_taken <= (N & ~Z & V ) | (~N & ~Z & ~V);
4'hd: branch_taken <= (N ^ V) & Z;
4'hf: branch_taken <= 1;
endcase
PC_source <= branch_taken & branch_d;
end
endmodule |
module mkmif_core(
input wire clk,
input wire reset_n,
output wire spi_sclk,
output wire spi_cs_n,
input wire spi_do,
output wire spi_di,
input wire read_op,
input wire write_op,
input wire init_op,
output wire ready,
output wire valid,
input wire [15 : 0] sclk_div,
input wire [15 : 0] addr,
input wire [31 : 0] write_data,
output wire [31 : 0] read_data
);
//----------------------------------------------------------------
// Internal constant and parameter definitions.
//----------------------------------------------------------------
localparam SPI_READ_DATA_CMD = 8'h03;
localparam SPI_WRITE_DATA_CMD = 8'h02;
localparam SPI_READ_STATUS_CMD = 8'h05;
localparam SPI_WRITE_STATUS_CMD = 8'h01;
localparam SEQ_MODE_NO_HOLD = 8'b01000001;
localparam CTRL_IDLE = 0;
localparam CTRL_READY = 1;
localparam CTRL_READ = 2;
localparam CTRL_WRITE = 3;
localparam CTRL_INIT = 4;
localparam CTRL_OP_START = 5;
localparam CTRL_OP_WAIT = 6;
//----------------------------------------------------------------
// Registers including update variables and write enable.
//----------------------------------------------------------------
reg ready_reg;
reg ready_new;
reg ready_we;
reg valid_reg;
reg valid_new;
reg valid_we;
reg [31 : 0] read_data_reg;
reg read_data_we;
reg [3 : 0] mkmif_ctrl_reg;
reg [3 : 0] mkmif_ctrl_new;
reg mkmif_ctrl_we;
//----------------------------------------------------------------
// Wires.
//----------------------------------------------------------------
wire [31 : 0] spi_read_data;
reg [55 : 0] spi_write_data;
reg spi_set;
reg spi_start;
wire spi_ready;
reg [2 : 0] spi_length;
//----------------------------------------------------------------
// Concurrent connectivity for ports etc.
//----------------------------------------------------------------
assign ready = ready_reg;
assign valid = valid_reg;
assign read_data = read_data_reg;
//----------------------------------------------------------------
// spi
// The actual spi interfacce
//----------------------------------------------------------------
mkmif_spi spi(
.clk(clk),
.reset_n(reset_n),
.spi_sclk(spi_sclk),
.spi_cs_n(spi_cs_n),
.spi_do(spi_do),
.spi_di(spi_di),
.set(spi_set),
.start(spi_start),
.length(spi_length),
.divisor(sclk_div),
.ready(spi_ready),
.wr_data(spi_write_data),
.rd_data(spi_read_data)
);
//----------------------------------------------------------------
// reg_update
// Update functionality for all registers in the core.
// All registers are positive edge triggered with asynchronous
// active low reset.
//----------------------------------------------------------------
always @ (posedge clk or negedge reset_n)
begin
if (!reset_n)
begin
ready_reg <= 0;
valid_reg <= 0;
read_data_reg <= 32'h0;
mkmif_ctrl_reg <= CTRL_IDLE;
end
else
begin
if (ready_we)
ready_reg <= ready_new;
if (valid_we)
valid_reg <= valid_new;
if (read_data_we)
read_data_reg <= spi_read_data;
if (mkmif_ctrl_we)
mkmif_ctrl_reg <= mkmif_ctrl_new;
end
end // reg_update
//----------------------------------------------------------------
// mkmif_ctrl
// Main control FSM.
//----------------------------------------------------------------
always @*
begin : mkmif_ctrl
spi_set = 0;
spi_start = 0;
spi_length = 3'h0;
spi_write_data = 56'h0;
read_data_we = 0;
ready_new = 0;
ready_we = 0;
valid_new = 0;
valid_we = 0;
mkmif_ctrl_new = CTRL_IDLE;
mkmif_ctrl_we = 0;
case (mkmif_ctrl_reg)
CTRL_IDLE:
begin
mkmif_ctrl_new = CTRL_INIT;
mkmif_ctrl_we = 1;
end
CTRL_READY:
begin
ready_new = 1;
ready_we = 1;
if (read_op)
begin
ready_new = 0;
ready_we = 1;
valid_new = 0;
valid_we = 1;
mkmif_ctrl_new = CTRL_READ;
mkmif_ctrl_we = 1;
end
if (write_op)
begin
ready_new = 0;
ready_we = 1;
mkmif_ctrl_new = CTRL_WRITE;
mkmif_ctrl_we = 1;
end
if (init_op)
begin
ready_new = 0;
ready_we = 1;
mkmif_ctrl_new = CTRL_INIT;
mkmif_ctrl_we = 1;
end
end
CTRL_READ:
begin
spi_set = 1;
spi_write_data = {SPI_READ_DATA_CMD, addr, 32'h0};
spi_length = 3'h7;
mkmif_ctrl_new = CTRL_OP_START;
mkmif_ctrl_we = 1;
end
CTRL_WRITE:
begin
spi_set = 1;
spi_write_data = {SPI_WRITE_DATA_CMD, addr, write_data};
spi_length = 3'h7;
mkmif_ctrl_new = CTRL_OP_START;
mkmif_ctrl_we = 1;
end
CTRL_INIT:
begin
if (spi_ready)
begin
spi_set = 1;
spi_write_data = {SPI_WRITE_STATUS_CMD, SEQ_MODE_NO_HOLD, 40'h0};
spi_length = 3'h2;
mkmif_ctrl_new = CTRL_OP_START;
mkmif_ctrl_we = 1;
end
end
CTRL_OP_START:
begin
spi_start = 1;
mkmif_ctrl_new = CTRL_OP_WAIT;
mkmif_ctrl_we = 1;
end
CTRL_OP_WAIT:
begin
if (spi_ready)
begin
read_data_we = 1;
valid_new = 1;
valid_we = 1;
mkmif_ctrl_new = CTRL_READY;
mkmif_ctrl_we = 1;
end
end
default:
begin
end
endcase // case (mkmif_ctrl_reg)
end // mkmif_ctrl
endmodule |
module CORDIC_Arch2v1_W32_EW8_SW23_SWR26_EWR5 ( clk, rst, beg_fsm_cordic,
ack_cordic, operation, data_in, shift_region_flag, ready_cordic,
data_output, beg_add_subt, ack_add_subt, add_subt_dataA,
add_subt_dataB, result_add_subt, op_add_subt, ready_add_subt );
input [31:0] data_in;
input [1:0] shift_region_flag;
output [31:0] data_output;
output [31:0] add_subt_dataA;
output [31:0] add_subt_dataB;
input [31:0] result_add_subt;
input clk, rst, beg_fsm_cordic, ack_cordic, operation, ready_add_subt;
output ready_cordic, beg_add_subt, ack_add_subt, op_add_subt;
wire d_ff1_operation_out, sel_mux_1_reg, d_ff3_sign_out, sel_mux_3_reg,
data_output2_31_, cordic_FSM_state_next_1_, n331, n336, n337, n338,
n339, n340, n341, n342, n343, n344, n345, n346, n347, n348, n349,
n350, n351, n352, n353, n354, n355, n356, n357, n358, n359, n360,
n361, n362, n363, n364, n365, n366, n367, n368, n369, n370, n371,
n372, n373, n374, n375, n376, n377, n378, n379, n380, n381, n382,
n383, n384, n385, n386, n387, n388, n389, n390, n391, n392, n393,
n394, n395, n396, n397, n398, n399, n400, n401, n402, n403, n404,
n405, n406, n407, n408, n409, n410, n411, n412, n413, n414, n415,
n416, n417, n418, n419, n420, n421, n422, n423, n424, n425, n426,
n427, n428, n429, n430, n431, n432, n433, n434, n435, n436, n437,
n438, n439, n440, n441, n442, n443, n444, n445, n446, n447, n448,
n449, n450, n451, n452, n453, n454, n455, n456, n457, n458, n459,
n460, n461, n462, n463, n464, n465, n466, n467, n468, n469, n470,
n471, n472, n473, n474, n475, n476, n477, n478, n479, n480, n481,
n482, n483, n484, n485, n486, n487, n488, n489, n490, n491, n492,
n493, n494, n495, n496, n497, n498, n499, n500, n501, n502, n503,
n504, n505, n506, n507, n508, n509, n510, n511, n512, n513, n514,
n515, n516, n517, n518, n519, n520, n521, n522, n523, n524, n525,
n526, n527, n528, n529, n530, n531, n532, n533, n534, n535, n536,
n537, n538, n539, n540, n541, n542, n543, n544, n545, n546, n547,
n548, n549, n550, n551, n552, n553, n554, n555, n556, n557, n558,
n559, n560, n561, n562, n563, n564, n565, n566, n567, n568, n569,
n570, n571, n572, n573, n574, n575, n576, n577, n578, n579, n580,
n581, n582, n583, n584, n585, n586, n587, n588, n589, n590, n591,
n592, n593, n594, n595, n596, n597, n598, n599, n600, n601, n602,
n603, n604, n605, n606, n607, n608, n609, n610, n611, n612, n613,
n614, n615, n616, n617, n618, n619, n620, n621, n622, n623, n624,
n625, n626, n627, n628, n629, n630, n631, n632, n633, n634, n635,
n636, n637, n638, n639, n640, n641, n642, n643, n644, n645, n646,
n647, n648, n649, n650, n651, n652, n653, n654, n655, n656, n657,
n658, n659, n660, n661, n662, n663, n664, n665, n666, n667, n668,
n669, n670, n671, n672, n673, n674, n675, n676, n677, n678, n679,
n680, n681, n682, n683, n684, n685, n686, n687, n688, n689, n690,
n691, n692, n693, n694, n695, n696, n697, n698, n699, n700, n701,
n702, n703, n704, n705, n706, n707, n708, n709, n710, n711, n712,
n713, n714, n715, n716, n717, n718, n719, n720, n721, n722, n723,
n724, n725, n726, n727, n728, n729, n730, n731, n732, n798, n799,
n800, n801, n802, n803, n804, n805, n806, n807, n808, n809, n810,
n811, n812, n813, n814, n815, n816, n817, n818, n819, n820, n821,
n822, n823, n824, n825, n826, n827, n828, n829, n830, n831, n832,
n833, n834, n835, n836, n837, n838, n839, n840, n841, n842, n843,
n844, n845, n846, n847, n848, n849, n850, n851, n852, n853, n854,
n855, n856, n857, n858, n859, n860, n861, n862, n863, n864, n865,
n866, n867, n868, n869, n870, n871, n872, n873, n874, n875, n876,
n877, n878, n879, n880, n881, n882, n883, n884, n885, n886, n887,
n888, n889, n890, n891, n892, n893, n894, n895, n896, n897, n898,
n899, n900, n901, n902, n903, n904, n905, n906, n907, n908, n909,
n910, n911, n912, n913, n914, n915, n916, n917, n918, n919, n920,
n921, n922, n923, n924, n925, n926, n927, n928, n929, n930, n931,
n932, n933, n934, n935, n936, n937, n938, n939, n940, n941, n942,
n943, n944, n945, n946, n947, n948, n949, n950, n951, n952, n953,
n954, n955, n956, n957, n958, n959, n960, n961, n962, n963, n964,
n965, n966, n967, n968, n969, n970, n971, n972, n973, n974, n975,
n976, n977, n978, n979, n980, n981, n982, n983, n984, n985, n986,
n987, n988, n989, n990, n991, n992, n993, n994, n995, n996, n997,
n998, n999, n1000, n1001, n1002, n1003, n1004, n1005, n1006, n1007,
n1008, n1009, n1010, n1011, n1012, n1013, n1014, n1015, n1016, n1017,
n1018, n1019, n1020, n1021, n1022, n1023, n1024, n1025, n1026, n1027,
n1028, n1029, n1030, n1031, n1032, n1033, n1034, n1035, n1036, n1037,
n1038, n1039, n1040, n1041, n1042, n1043, n1044, n1045, n1046, n1047,
n1048, n1049, n1050, n1051, n1052, n1053, n1054, n1055, n1056, n1057,
n1058, n1059, n1060, n1061, n1062, n1063, n1064, n1065, n1066, n1067,
n1068, n1069, n1070, n1071, n1072, n1073, n1074, n1075, n1076, n1077,
n1078, n1079, n1080, n1081, n1082, n1083, n1084, n1085, n1086, n1087,
n1088, n1089, n1090, n1091, n1092, n1093, n1094, n1095, n1096, n1097,
n1098, n1099, n1100, n1101, n1102, n1103, n1104, n1105, n1106, n1107,
n1108, n1109, n1110, n1111, n1112, n1113, n1114, n1115, n1116, n1117,
n1118, n1119, n1120, n1121, n1122, n1123, n1124, n1125, n1126, n1127,
n1128, n1129, n1130, n1131, n1132, n1133, n1134, n1135, n1136, n1137,
n1138, n1139, n1140, n1141, n1142, n1143, n1144, n1145, n1146, n1147,
n1148, n1149, n1150, n1151, n1152, n1153, n1154, n1155, n1156, n1157,
n1158, n1159, n1160, n1161, n1162, n1163, n1164, n1165, n1166, n1167,
n1168, n1169, n1170, n1171, n1172, n1173, n1174, n1175, n1176, n1177,
n1178, n1179, n1180, n1181, n1182, n1183, n1184, n1185, n1186, n1187,
n1188, n1189, n1190, n1191, n1192, n1193, n1194, n1195, n1196, n1197,
n1198, n1199, n1200, n1201, n1202, n1203, n1204, n1205, n1206, n1207,
n1208, n1209, n1210, n1211, n1212, n1213, n1214, n1215, n1216, n1217,
n1218, n1219, n1220, n1221, n1222, n1223, n1224, n1225, n1226, n1227,
n1228, n1229, n1230, n1231, n1232, n1233, n1234, n1235, n1236, n1237,
n1238, n1239, n1240, n1241, n1242, n1243, n1244, n1245, n1246, n1247,
n1248, n1249, n1250, n1251, n1252, n1253, n1254, n1255, n1256, n1257,
n1258, n1259, n1260, n1261, n1262, n1263, n1264, n1265, n1266, n1267,
n1268, n1269, n1270, n1271, n1272, n1273, n1274, n1275, n1276, n1277,
n1278, n1279, n1280, n1281, n1282, n1283, n1284, n1285, n1286, n1287,
n1288, n1289, n1290, n1291, n1292, n1293, n1294, n1295, n1296, n1297,
n1298, n1299, n1300, n1301, n1302, n1303, n1304, n1305, n1306, n1307,
n1308, n1309, n1310, n1311, n1312, n1313, n1314, n1315, n1316, n1317,
n1318, n1319, n1320, n1321, n1322, n1323, n1324, n1325, n1326, n1327,
n1328, n1329, n1330, n1331, n1332, n1333, n1334, n1335, n1336, n1337,
n1338;
wire [1:0] d_ff1_shift_region_flag_out;
wire [1:0] cont_var_out;
wire [3:0] cont_iter_out;
wire [31:0] d_ff1_Z;
wire [31:0] d_ff_Xn;
wire [31:0] d_ff_Yn;
wire [31:0] d_ff_Zn;
wire [31:0] d_ff2_X;
wire [31:0] d_ff2_Y;
wire [31:0] d_ff2_Z;
wire [31:0] d_ff3_sh_x_out;
wire [31:0] d_ff3_sh_y_out;
wire [27:0] d_ff3_LUT_out;
wire [1:0] sel_mux_2_reg;
wire [30:0] sign_inv_out;
wire [3:0] cordic_FSM_state_reg;
DFFRX1TS reg_operation_Q_reg_0_ ( .D(n723), .CK(n811), .RN(n1285), .Q(
d_ff1_operation_out), .QN(n1260) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_23_ ( .D(n353), .CK(n1302), .RN(n1280),
.Q(d_ff2_X[23]), .QN(n1259) );
DFFRXLTS d_ff4_Yn_Q_reg_31_ ( .D(n621), .CK(n1326), .RN(n1286), .Q(
d_ff_Yn[31]), .QN(n1258) );
DFFRXLTS d_ff4_Yn_Q_reg_19_ ( .D(n633), .CK(n1324), .RN(n1300), .Q(
d_ff_Yn[19]), .QN(n1257) );
DFFRXLTS d_ff4_Yn_Q_reg_18_ ( .D(n634), .CK(n1326), .RN(n1291), .Q(
d_ff_Yn[18]), .QN(n1256) );
DFFRXLTS d_ff4_Yn_Q_reg_17_ ( .D(n635), .CK(n1329), .RN(n1287), .Q(
d_ff_Yn[17]), .QN(n1255) );
DFFRXLTS d_ff4_Yn_Q_reg_16_ ( .D(n636), .CK(n1331), .RN(n1290), .Q(
d_ff_Yn[16]), .QN(n1254) );
DFFRXLTS d_ff4_Yn_Q_reg_15_ ( .D(n637), .CK(n1334), .RN(n1289), .Q(
d_ff_Yn[15]), .QN(n1253) );
DFFRXLTS d_ff4_Yn_Q_reg_14_ ( .D(n638), .CK(n809), .RN(n1300), .Q(
d_ff_Yn[14]), .QN(n1252) );
DFFRXLTS d_ff4_Yn_Q_reg_13_ ( .D(n639), .CK(n1330), .RN(n1291), .Q(
d_ff_Yn[13]), .QN(n1251) );
DFFRXLTS d_ff4_Yn_Q_reg_12_ ( .D(n640), .CK(n1334), .RN(n1290), .Q(
d_ff_Yn[12]), .QN(n1250) );
DFFRXLTS d_ff4_Yn_Q_reg_11_ ( .D(n641), .CK(n809), .RN(n1287), .Q(
d_ff_Yn[11]), .QN(n1249) );
DFFRXLTS d_ff4_Yn_Q_reg_10_ ( .D(n642), .CK(n1333), .RN(n1289), .Q(
d_ff_Yn[10]), .QN(n1248) );
DFFRXLTS d_ff4_Yn_Q_reg_9_ ( .D(n643), .CK(n809), .RN(n1300), .Q(d_ff_Yn[9]),
.QN(n1247) );
DFFRXLTS d_ff4_Yn_Q_reg_8_ ( .D(n644), .CK(n1330), .RN(n1291), .Q(d_ff_Yn[8]), .QN(n1246) );
DFFRXLTS d_ff4_Yn_Q_reg_7_ ( .D(n645), .CK(n1334), .RN(n1287), .Q(d_ff_Yn[7]), .QN(n1245) );
DFFRXLTS d_ff4_Yn_Q_reg_6_ ( .D(n646), .CK(n1329), .RN(n1290), .Q(d_ff_Yn[6]), .QN(n1244) );
DFFRXLTS d_ff4_Yn_Q_reg_5_ ( .D(n647), .CK(n1330), .RN(n1289), .Q(d_ff_Yn[5]), .QN(n1243) );
DFFRXLTS d_ff4_Yn_Q_reg_4_ ( .D(n648), .CK(n1330), .RN(n1288), .Q(d_ff_Yn[4]), .QN(n1242) );
DFFRXLTS d_ff4_Yn_Q_reg_3_ ( .D(n649), .CK(n1334), .RN(n1288), .Q(d_ff_Yn[3]), .QN(n1241) );
DFFRXLTS d_ff4_Yn_Q_reg_2_ ( .D(n650), .CK(n1333), .RN(n1299), .Q(d_ff_Yn[2]), .QN(n1240) );
DFFRXLTS d_ff4_Yn_Q_reg_1_ ( .D(n651), .CK(n1334), .RN(n1298), .Q(d_ff_Yn[1]), .QN(n1239) );
DFFRXLTS d_ff4_Yn_Q_reg_0_ ( .D(n652), .CK(n1329), .RN(n1293), .Q(d_ff_Yn[0]), .QN(n1238) );
DFFRXLTS reg_shift_x_Q_reg_28_ ( .D(n340), .CK(n1307), .RN(n1265), .QN(n1237) );
DFFRX1TS reg_shift_x_Q_reg_29_ ( .D(n339), .CK(n1315), .RN(n1263), .QN(n1236) );
DFFRX1TS reg_LUT_Q_reg_12_ ( .D(n512), .CK(n1313), .RN(n1263), .QN(n1235) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_29_ ( .D(n411), .CK(n805), .RN(n1272),
.Q(d_ff2_Y[29]), .QN(n1234) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_27_ ( .D(n413), .CK(n1310), .RN(n1274),
.Q(d_ff2_Y[27]), .QN(n1233) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_30_ ( .D(n410), .CK(n1301), .RN(n1276),
.Q(d_ff2_Y[30]), .QN(n1232) );
DFFRX1TS reg_ch_mux_2_Q_reg_0_ ( .D(n686), .CK(n1334), .RN(n1285), .Q(
sel_mux_2_reg[0]), .QN(n1231) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_28_ ( .D(n412), .CK(n1307), .RN(n1275),
.Q(d_ff2_Y[28]), .QN(n1230) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_23_ ( .D(n417), .CK(n1309), .RN(n1272),
.Q(d_ff2_Y[23]), .QN(n1229) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_25_ ( .D(n351), .CK(n1305), .RN(n1283),
.Q(d_ff2_X[25]), .QN(n1228) );
DFFRX1TS cont_var_count_reg_0_ ( .D(n724), .CK(n811), .RN(n1281), .Q(
cont_var_out[0]), .QN(n1227) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_24_ ( .D(n416), .CK(n1308), .RN(n1275),
.Q(d_ff2_Y[24]), .QN(n1226) );
DFFRX2TS cordic_FSM_state_reg_reg_0_ ( .D(n730), .CK(n1338), .RN(n331), .Q(
cordic_FSM_state_reg[0]), .QN(n1225) );
DFFRX2TS cont_iter_count_reg_3_ ( .D(n725), .CK(n1338), .RN(n1281), .Q(
cont_iter_out[3]), .QN(n1223) );
DFFRX1TS reg_region_flag_Q_reg_0_ ( .D(n722), .CK(n811), .RN(n1281), .Q(
d_ff1_shift_region_flag_out[0]), .QN(n1222) );
DFFRXLTS d_ff4_Yn_Q_reg_22_ ( .D(n630), .CK(n806), .RN(n1300), .Q(
d_ff_Yn[22]), .QN(n1221) );
DFFRXLTS d_ff4_Yn_Q_reg_20_ ( .D(n632), .CK(n1328), .RN(n1300), .Q(
d_ff_Yn[20]), .QN(n1220) );
DFFRX1TS d_ff4_Yn_Q_reg_30_ ( .D(n622), .CK(n806), .RN(n1299), .QN(n1219) );
DFFRX2TS cont_var_count_reg_1_ ( .D(n729), .CK(n1305), .RN(n1281), .Q(
cont_var_out[1]), .QN(n1218) );
DFFRX2TS cont_iter_count_reg_1_ ( .D(n727), .CK(n1338), .RN(n1281), .Q(
cont_iter_out[1]), .QN(n1217) );
DFFRX2TS cont_iter_count_reg_0_ ( .D(n728), .CK(n1338), .RN(n1281), .Q(
cont_iter_out[0]), .QN(n1216) );
DFFRX1TS reg_region_flag_Q_reg_1_ ( .D(n721), .CK(n811), .RN(n1281), .Q(
d_ff1_shift_region_flag_out[1]), .QN(n1214) );
DFFRXLTS d_ff4_Yn_Q_reg_26_ ( .D(n626), .CK(n1323), .RN(n1286), .Q(
d_ff_Yn[26]), .QN(n1213) );
DFFRXLTS d_ff4_Yn_Q_reg_25_ ( .D(n627), .CK(n1325), .RN(n1291), .Q(
d_ff_Yn[25]), .QN(n1212) );
DFFRXLTS d_ff4_Yn_Q_reg_21_ ( .D(n631), .CK(n1326), .RN(n1287), .Q(
d_ff_Yn[21]), .QN(n1211) );
DFFRX1TS d_ff4_Yn_Q_reg_29_ ( .D(n623), .CK(n1324), .RN(n1292), .QN(n1210)
);
DFFRX1TS d_ff4_Yn_Q_reg_28_ ( .D(n624), .CK(n1325), .RN(n1292), .QN(n1209)
);
DFFRX1TS d_ff4_Yn_Q_reg_27_ ( .D(n625), .CK(n1328), .RN(n1292), .QN(n1208)
);
DFFRX1TS d_ff4_Yn_Q_reg_24_ ( .D(n628), .CK(n1323), .RN(n1294), .QN(n1207)
);
DFFRX1TS d_ff4_Yn_Q_reg_23_ ( .D(n629), .CK(n1323), .RN(n1292), .QN(n1206)
);
DFFRXLTS d_ff5_data_out_Q_reg_0_ ( .D(n587), .CK(n806), .RN(n1299), .Q(
data_output[0]) );
DFFRXLTS d_ff5_data_out_Q_reg_1_ ( .D(n585), .CK(n1327), .RN(n1286), .Q(
data_output[1]) );
DFFRXLTS d_ff5_data_out_Q_reg_2_ ( .D(n583), .CK(n1323), .RN(n1293), .Q(
data_output[2]) );
DFFRXLTS d_ff5_data_out_Q_reg_3_ ( .D(n581), .CK(n1327), .RN(n1262), .Q(
data_output[3]) );
DFFRXLTS d_ff5_data_out_Q_reg_4_ ( .D(n579), .CK(n806), .RN(n1271), .Q(
data_output[4]) );
DFFRXLTS d_ff5_data_out_Q_reg_5_ ( .D(n577), .CK(n1325), .RN(n1295), .Q(
data_output[5]) );
DFFRXLTS d_ff5_data_out_Q_reg_6_ ( .D(n575), .CK(n1324), .RN(n1296), .Q(
data_output[6]) );
DFFRXLTS d_ff5_data_out_Q_reg_7_ ( .D(n573), .CK(n1323), .RN(n1296), .Q(
data_output[7]) );
DFFRXLTS d_ff5_data_out_Q_reg_8_ ( .D(n571), .CK(n1323), .RN(n1262), .Q(
data_output[8]) );
DFFRXLTS d_ff5_data_out_Q_reg_9_ ( .D(n569), .CK(n1324), .RN(n1271), .Q(
data_output[9]) );
DFFRXLTS d_ff5_data_out_Q_reg_10_ ( .D(n567), .CK(n1325), .RN(n1295), .Q(
data_output[10]) );
DFFRXLTS d_ff5_data_out_Q_reg_11_ ( .D(n565), .CK(n1326), .RN(n1271), .Q(
data_output[11]) );
DFFRXLTS d_ff5_data_out_Q_reg_12_ ( .D(n563), .CK(n806), .RN(n1295), .Q(
data_output[12]) );
DFFRXLTS d_ff5_data_out_Q_reg_13_ ( .D(n561), .CK(n1328), .RN(n1297), .Q(
data_output[13]) );
DFFRXLTS d_ff5_data_out_Q_reg_14_ ( .D(n559), .CK(n1323), .RN(n1290), .Q(
data_output[14]) );
DFFRXLTS d_ff5_data_out_Q_reg_15_ ( .D(n557), .CK(n1318), .RN(n1289), .Q(
data_output[15]) );
DFFRXLTS d_ff5_data_out_Q_reg_16_ ( .D(n555), .CK(n1320), .RN(n1300), .Q(
data_output[16]) );
DFFRXLTS d_ff5_data_out_Q_reg_17_ ( .D(n553), .CK(n1322), .RN(n1286), .Q(
data_output[17]) );
DFFRXLTS d_ff5_data_out_Q_reg_18_ ( .D(n551), .CK(n1321), .RN(n1293), .Q(
data_output[18]) );
DFFRXLTS d_ff5_data_out_Q_reg_19_ ( .D(n549), .CK(n807), .RN(n1299), .Q(
data_output[19]) );
DFFRXLTS d_ff5_data_out_Q_reg_20_ ( .D(n547), .CK(n1318), .RN(n1299), .Q(
data_output[20]) );
DFFRXLTS d_ff5_data_out_Q_reg_21_ ( .D(n545), .CK(n1319), .RN(n1288), .Q(
data_output[21]) );
DFFRXLTS d_ff5_data_out_Q_reg_22_ ( .D(n543), .CK(n1322), .RN(n1293), .Q(
data_output[22]) );
DFFRXLTS d_ff5_data_out_Q_reg_23_ ( .D(n541), .CK(n1318), .RN(n1288), .Q(
data_output[23]) );
DFFRXLTS d_ff5_data_out_Q_reg_24_ ( .D(n539), .CK(n1318), .RN(n1289), .Q(
data_output[24]) );
DFFRXLTS d_ff5_data_out_Q_reg_25_ ( .D(n537), .CK(n1322), .RN(n1300), .Q(
data_output[25]) );
DFFRXLTS d_ff5_data_out_Q_reg_26_ ( .D(n535), .CK(n1319), .RN(n1291), .Q(
data_output[26]) );
DFFRXLTS d_ff5_data_out_Q_reg_27_ ( .D(n533), .CK(n1321), .RN(n1291), .Q(
data_output[27]) );
DFFRXLTS d_ff5_data_out_Q_reg_28_ ( .D(n531), .CK(n1321), .RN(n1283), .Q(
data_output[28]) );
DFFRXLTS d_ff5_data_out_Q_reg_29_ ( .D(n529), .CK(n1318), .RN(n1261), .Q(
data_output[29]) );
DFFRXLTS d_ff5_data_out_Q_reg_30_ ( .D(n527), .CK(n1318), .RN(n1261), .Q(
data_output[30]) );
DFFRXLTS d_ff5_data_out_Q_reg_31_ ( .D(n525), .CK(n807), .RN(n1261), .Q(
data_output[31]) );
DFFRXLTS reg_shift_y_Q_reg_31_ ( .D(n400), .CK(n1306), .RN(n1274), .Q(
d_ff3_sh_y_out[31]) );
DFFRXLTS reg_shift_x_Q_reg_31_ ( .D(n336), .CK(n1305), .RN(n1280), .Q(
d_ff3_sh_x_out[31]) );
DFFRXLTS reg_shift_x_Q_reg_30_ ( .D(n338), .CK(n1313), .RN(n1273), .Q(
d_ff3_sh_x_out[30]) );
DFFRXLTS reg_shift_y_Q_reg_30_ ( .D(n402), .CK(n808), .RN(n1263), .Q(
d_ff3_sh_y_out[30]) );
DFFRXLTS reg_LUT_Q_reg_19_ ( .D(n505), .CK(n1316), .RN(n1263), .Q(
d_ff3_LUT_out[19]) );
DFFRXLTS reg_LUT_Q_reg_22_ ( .D(n502), .CK(n1315), .RN(n1278), .Q(
d_ff3_LUT_out[22]) );
DFFRXLTS reg_Z0_Q_reg_0_ ( .D(n720), .CK(n811), .RN(n1270), .Q(d_ff1_Z[0])
);
DFFRXLTS reg_shift_y_Q_reg_25_ ( .D(n407), .CK(n1314), .RN(n1263), .Q(
d_ff3_sh_y_out[25]) );
DFFRXLTS reg_shift_y_Q_reg_26_ ( .D(n406), .CK(n1313), .RN(n1265), .Q(
d_ff3_sh_y_out[26]) );
DFFRXLTS reg_shift_y_Q_reg_0_ ( .D(n462), .CK(n1307), .RN(n1295), .Q(
d_ff3_sh_y_out[0]) );
DFFRXLTS reg_shift_y_Q_reg_1_ ( .D(n460), .CK(n1310), .RN(n1282), .Q(
d_ff3_sh_y_out[1]) );
DFFRXLTS reg_shift_y_Q_reg_2_ ( .D(n458), .CK(n1312), .RN(n1285), .Q(
d_ff3_sh_y_out[2]) );
DFFRXLTS reg_shift_y_Q_reg_3_ ( .D(n456), .CK(n805), .RN(n1270), .Q(
d_ff3_sh_y_out[3]) );
DFFRXLTS reg_shift_y_Q_reg_4_ ( .D(n454), .CK(n1309), .RN(n1280), .Q(
d_ff3_sh_y_out[4]) );
DFFRXLTS reg_shift_y_Q_reg_5_ ( .D(n452), .CK(n1308), .RN(n1283), .Q(
d_ff3_sh_y_out[5]) );
DFFRXLTS reg_shift_y_Q_reg_6_ ( .D(n450), .CK(n1309), .RN(n1271), .Q(
d_ff3_sh_y_out[6]) );
DFFRXLTS reg_shift_y_Q_reg_7_ ( .D(n448), .CK(n1312), .RN(n1295), .Q(
d_ff3_sh_y_out[7]) );
DFFRXLTS reg_shift_y_Q_reg_9_ ( .D(n444), .CK(n1310), .RN(n1296), .Q(
d_ff3_sh_y_out[9]) );
DFFRXLTS reg_shift_y_Q_reg_10_ ( .D(n442), .CK(n1311), .RN(n1262), .Q(
d_ff3_sh_y_out[10]) );
DFFRXLTS reg_shift_y_Q_reg_11_ ( .D(n440), .CK(n1308), .RN(n1272), .Q(
d_ff3_sh_y_out[11]) );
DFFRXLTS reg_shift_y_Q_reg_13_ ( .D(n436), .CK(n1312), .RN(n1275), .Q(
d_ff3_sh_y_out[13]) );
DFFRXLTS reg_shift_y_Q_reg_14_ ( .D(n434), .CK(n805), .RN(n1272), .Q(
d_ff3_sh_y_out[14]) );
DFFRXLTS reg_shift_y_Q_reg_15_ ( .D(n432), .CK(n1312), .RN(n1276), .Q(
d_ff3_sh_y_out[15]) );
DFFRXLTS reg_shift_y_Q_reg_16_ ( .D(n430), .CK(n1311), .RN(n1263), .Q(
d_ff3_sh_y_out[16]) );
DFFRXLTS reg_shift_y_Q_reg_17_ ( .D(n428), .CK(n1308), .RN(n1273), .Q(
d_ff3_sh_y_out[17]) );
DFFRXLTS reg_shift_y_Q_reg_18_ ( .D(n426), .CK(n1309), .RN(n1284), .Q(
d_ff3_sh_y_out[18]) );
DFFRXLTS reg_shift_y_Q_reg_19_ ( .D(n424), .CK(n1310), .RN(n1267), .Q(
d_ff3_sh_y_out[19]) );
DFFRXLTS reg_shift_y_Q_reg_20_ ( .D(n422), .CK(n1311), .RN(n1267), .Q(
d_ff3_sh_y_out[20]) );
DFFRXLTS reg_shift_y_Q_reg_21_ ( .D(n420), .CK(n1308), .RN(n1272), .Q(
d_ff3_sh_y_out[21]) );
DFFRXLTS reg_shift_y_Q_reg_22_ ( .D(n418), .CK(n1312), .RN(n1276), .Q(
d_ff3_sh_y_out[22]) );
DFFRXLTS reg_Z0_Q_reg_1_ ( .D(n719), .CK(n811), .RN(n1285), .Q(d_ff1_Z[1])
);
DFFRXLTS reg_Z0_Q_reg_2_ ( .D(n718), .CK(n811), .RN(n1283), .Q(d_ff1_Z[2])
);
DFFRXLTS reg_Z0_Q_reg_3_ ( .D(n717), .CK(n811), .RN(n1282), .Q(d_ff1_Z[3])
);
DFFRXLTS reg_Z0_Q_reg_4_ ( .D(n716), .CK(n811), .RN(n1285), .Q(d_ff1_Z[4])
);
DFFRXLTS reg_Z0_Q_reg_5_ ( .D(n715), .CK(n811), .RN(n1270), .Q(d_ff1_Z[5])
);
DFFRXLTS reg_Z0_Q_reg_6_ ( .D(n714), .CK(n813), .RN(n1280), .Q(d_ff1_Z[6])
);
DFFRXLTS reg_Z0_Q_reg_7_ ( .D(n713), .CK(n813), .RN(n1283), .Q(d_ff1_Z[7])
);
DFFRXLTS reg_Z0_Q_reg_8_ ( .D(n712), .CK(n813), .RN(n1282), .Q(d_ff1_Z[8])
);
DFFRXLTS reg_Z0_Q_reg_9_ ( .D(n711), .CK(n813), .RN(n1285), .Q(d_ff1_Z[9])
);
DFFRXLTS reg_Z0_Q_reg_10_ ( .D(n710), .CK(n813), .RN(n1270), .Q(d_ff1_Z[10])
);
DFFRXLTS reg_Z0_Q_reg_11_ ( .D(n709), .CK(n813), .RN(n1280), .Q(d_ff1_Z[11])
);
DFFRXLTS reg_Z0_Q_reg_12_ ( .D(n708), .CK(n813), .RN(n1283), .Q(d_ff1_Z[12])
);
DFFRXLTS reg_Z0_Q_reg_13_ ( .D(n707), .CK(n813), .RN(n1282), .Q(d_ff1_Z[13])
);
DFFRXLTS reg_Z0_Q_reg_14_ ( .D(n706), .CK(n813), .RN(n1285), .Q(d_ff1_Z[14])
);
DFFRXLTS reg_Z0_Q_reg_15_ ( .D(n705), .CK(n813), .RN(n1270), .Q(d_ff1_Z[15])
);
DFFRXLTS reg_Z0_Q_reg_16_ ( .D(n704), .CK(n1335), .RN(n1280), .Q(d_ff1_Z[16]) );
DFFRXLTS reg_Z0_Q_reg_17_ ( .D(n703), .CK(n1335), .RN(n1283), .Q(d_ff1_Z[17]) );
DFFRXLTS reg_Z0_Q_reg_18_ ( .D(n702), .CK(n1335), .RN(n1282), .Q(d_ff1_Z[18]) );
DFFRXLTS reg_Z0_Q_reg_19_ ( .D(n701), .CK(n1335), .RN(n1285), .Q(d_ff1_Z[19]) );
DFFRXLTS reg_Z0_Q_reg_20_ ( .D(n700), .CK(n1335), .RN(n1270), .Q(d_ff1_Z[20]) );
DFFRXLTS reg_Z0_Q_reg_21_ ( .D(n699), .CK(n1335), .RN(n1280), .Q(d_ff1_Z[21]) );
DFFRXLTS reg_Z0_Q_reg_22_ ( .D(n698), .CK(n1335), .RN(n1265), .Q(d_ff1_Z[22]) );
DFFRXLTS reg_Z0_Q_reg_23_ ( .D(n697), .CK(n1335), .RN(n1267), .Q(d_ff1_Z[23]) );
DFFRXLTS reg_Z0_Q_reg_24_ ( .D(n696), .CK(n1335), .RN(n1273), .Q(d_ff1_Z[24]) );
DFFRXLTS reg_Z0_Q_reg_25_ ( .D(n695), .CK(n1338), .RN(n1265), .Q(d_ff1_Z[25]) );
DFFRXLTS reg_Z0_Q_reg_26_ ( .D(n694), .CK(n1331), .RN(n1265), .Q(d_ff1_Z[26]) );
DFFRXLTS reg_Z0_Q_reg_27_ ( .D(n693), .CK(n1334), .RN(n1284), .Q(d_ff1_Z[27]) );
DFFRXLTS reg_Z0_Q_reg_28_ ( .D(n692), .CK(n809), .RN(n1284), .Q(d_ff1_Z[28])
);
DFFRXLTS reg_Z0_Q_reg_29_ ( .D(n691), .CK(n809), .RN(n1267), .Q(d_ff1_Z[29])
);
DFFRXLTS reg_Z0_Q_reg_30_ ( .D(n690), .CK(n1330), .RN(n1267), .Q(d_ff1_Z[30]) );
DFFRXLTS reg_Z0_Q_reg_31_ ( .D(n689), .CK(n809), .RN(n1284), .Q(d_ff1_Z[31])
);
DFFRXLTS d_ff4_Zn_Q_reg_0_ ( .D(n684), .CK(n1333), .RN(n1287), .Q(d_ff_Zn[0]) );
DFFRXLTS reg_shift_x_Q_reg_26_ ( .D(n342), .CK(n1316), .RN(n1273), .Q(
d_ff3_sh_x_out[26]) );
DFFRXLTS reg_shift_x_Q_reg_0_ ( .D(n398), .CK(n1306), .RN(n1276), .Q(
d_ff3_sh_x_out[0]) );
DFFRXLTS reg_shift_x_Q_reg_1_ ( .D(n396), .CK(n1305), .RN(n1274), .Q(
d_ff3_sh_x_out[1]) );
DFFRXLTS reg_shift_x_Q_reg_2_ ( .D(n394), .CK(n1304), .RN(n1275), .Q(
d_ff3_sh_x_out[2]) );
DFFRXLTS reg_shift_x_Q_reg_3_ ( .D(n392), .CK(n1301), .RN(n1275), .Q(
d_ff3_sh_x_out[3]) );
DFFRXLTS reg_shift_x_Q_reg_4_ ( .D(n390), .CK(n1305), .RN(n1272), .Q(
d_ff3_sh_x_out[4]) );
DFFRXLTS reg_shift_x_Q_reg_5_ ( .D(n388), .CK(n1303), .RN(n1276), .Q(
d_ff3_sh_x_out[5]) );
DFFRXLTS reg_shift_x_Q_reg_6_ ( .D(n386), .CK(n1302), .RN(n1274), .Q(
d_ff3_sh_x_out[6]) );
DFFRXLTS reg_shift_x_Q_reg_7_ ( .D(n384), .CK(n1301), .RN(n1275), .Q(
d_ff3_sh_x_out[7]) );
DFFRXLTS reg_shift_x_Q_reg_8_ ( .D(n382), .CK(n1302), .RN(n1279), .Q(
d_ff3_sh_x_out[8]) );
DFFRXLTS reg_shift_x_Q_reg_9_ ( .D(n380), .CK(n1301), .RN(n1277), .Q(
d_ff3_sh_x_out[9]) );
DFFRXLTS reg_shift_x_Q_reg_10_ ( .D(n378), .CK(n1304), .RN(n1278), .Q(
d_ff3_sh_x_out[10]) );
DFFRXLTS reg_shift_x_Q_reg_11_ ( .D(n376), .CK(n804), .RN(n1279), .Q(
d_ff3_sh_x_out[11]) );
DFFRXLTS reg_shift_x_Q_reg_13_ ( .D(n372), .CK(n1301), .RN(n1278), .Q(
d_ff3_sh_x_out[13]) );
DFFRXLTS reg_shift_x_Q_reg_14_ ( .D(n370), .CK(n1302), .RN(n1279), .Q(
d_ff3_sh_x_out[14]) );
DFFRXLTS reg_shift_x_Q_reg_15_ ( .D(n368), .CK(n1304), .RN(n1277), .Q(
d_ff3_sh_x_out[15]) );
DFFRXLTS reg_shift_x_Q_reg_16_ ( .D(n366), .CK(n804), .RN(n1278), .Q(
d_ff3_sh_x_out[16]) );
DFFRXLTS reg_shift_x_Q_reg_17_ ( .D(n364), .CK(n1303), .RN(n1279), .Q(
d_ff3_sh_x_out[17]) );
DFFRXLTS reg_shift_x_Q_reg_18_ ( .D(n362), .CK(n1303), .RN(n1277), .Q(
d_ff3_sh_x_out[18]) );
DFFRXLTS reg_shift_x_Q_reg_19_ ( .D(n360), .CK(n1305), .RN(n1278), .Q(
d_ff3_sh_x_out[19]) );
DFFRXLTS reg_shift_x_Q_reg_20_ ( .D(n358), .CK(n1304), .RN(n1279), .Q(
d_ff3_sh_x_out[20]) );
DFFRXLTS reg_shift_x_Q_reg_21_ ( .D(n356), .CK(n804), .RN(n1277), .Q(
d_ff3_sh_x_out[21]) );
DFFRXLTS reg_shift_x_Q_reg_22_ ( .D(n354), .CK(n1302), .RN(n1278), .Q(
d_ff3_sh_x_out[22]) );
DFFRXLTS d_ff4_Zn_Q_reg_1_ ( .D(n683), .CK(n809), .RN(n1282), .Q(d_ff_Zn[1])
);
DFFRXLTS d_ff4_Zn_Q_reg_2_ ( .D(n682), .CK(n809), .RN(n1285), .Q(d_ff_Zn[2])
);
DFFRXLTS d_ff4_Zn_Q_reg_3_ ( .D(n681), .CK(n1330), .RN(n1270), .Q(d_ff_Zn[3]) );
DFFRXLTS d_ff4_Zn_Q_reg_4_ ( .D(n680), .CK(n1333), .RN(n1280), .Q(d_ff_Zn[4]) );
DFFRXLTS d_ff4_Zn_Q_reg_5_ ( .D(n679), .CK(n809), .RN(n1283), .Q(d_ff_Zn[5])
);
DFFRXLTS d_ff4_Zn_Q_reg_6_ ( .D(n678), .CK(n1333), .RN(n1282), .Q(d_ff_Zn[6]) );
DFFRXLTS d_ff4_Zn_Q_reg_7_ ( .D(n677), .CK(n1331), .RN(n1298), .Q(d_ff_Zn[7]) );
DFFRXLTS d_ff4_Zn_Q_reg_8_ ( .D(n676), .CK(n1330), .RN(n1288), .Q(d_ff_Zn[8]) );
DFFRXLTS d_ff4_Zn_Q_reg_9_ ( .D(n675), .CK(n809), .RN(n1298), .Q(d_ff_Zn[9])
);
DFFRXLTS d_ff4_Zn_Q_reg_10_ ( .D(n674), .CK(n1331), .RN(n1286), .Q(
d_ff_Zn[10]) );
DFFRXLTS d_ff4_Zn_Q_reg_11_ ( .D(n673), .CK(n1329), .RN(n1288), .Q(
d_ff_Zn[11]) );
DFFRXLTS d_ff4_Zn_Q_reg_12_ ( .D(n672), .CK(n1333), .RN(n1288), .Q(
d_ff_Zn[12]) );
DFFRXLTS d_ff4_Zn_Q_reg_13_ ( .D(n671), .CK(n1330), .RN(n1298), .Q(
d_ff_Zn[13]) );
DFFRXLTS d_ff4_Zn_Q_reg_14_ ( .D(n670), .CK(n1331), .RN(n1293), .Q(
d_ff_Zn[14]) );
DFFRXLTS d_ff4_Zn_Q_reg_15_ ( .D(n669), .CK(n1329), .RN(n1288), .Q(
d_ff_Zn[15]) );
DFFRXLTS d_ff4_Zn_Q_reg_16_ ( .D(n668), .CK(n1331), .RN(n1298), .Q(
d_ff_Zn[16]) );
DFFRXLTS d_ff4_Zn_Q_reg_17_ ( .D(n667), .CK(n1334), .RN(n1300), .Q(
d_ff_Zn[17]) );
DFFRXLTS d_ff4_Zn_Q_reg_18_ ( .D(n666), .CK(n1330), .RN(n1291), .Q(
d_ff_Zn[18]) );
DFFRXLTS d_ff4_Zn_Q_reg_19_ ( .D(n665), .CK(n1329), .RN(n1290), .Q(
d_ff_Zn[19]) );
DFFRXLTS d_ff4_Zn_Q_reg_20_ ( .D(n664), .CK(n1329), .RN(n1287), .Q(
d_ff_Zn[20]) );
DFFRXLTS d_ff4_Zn_Q_reg_21_ ( .D(n663), .CK(n1331), .RN(n1289), .Q(
d_ff_Zn[21]) );
DFFRXLTS d_ff4_Zn_Q_reg_22_ ( .D(n662), .CK(n1333), .RN(n1300), .Q(
d_ff_Zn[22]) );
DFFRXLTS d_ff4_Zn_Q_reg_23_ ( .D(n661), .CK(n1334), .RN(n1291), .Q(
d_ff_Zn[23]) );
DFFRXLTS d_ff4_Zn_Q_reg_24_ ( .D(n660), .CK(n1329), .RN(n1287), .Q(
d_ff_Zn[24]) );
DFFRXLTS d_ff4_Zn_Q_reg_25_ ( .D(n659), .CK(n1331), .RN(n1290), .Q(
d_ff_Zn[25]) );
DFFRXLTS d_ff4_Zn_Q_reg_26_ ( .D(n658), .CK(n1333), .RN(n1289), .Q(
d_ff_Zn[26]) );
DFFRXLTS d_ff4_Zn_Q_reg_27_ ( .D(n657), .CK(n1334), .RN(n1299), .Q(
d_ff_Zn[27]) );
DFFRXLTS d_ff4_Zn_Q_reg_28_ ( .D(n656), .CK(n1329), .RN(n1286), .Q(
d_ff_Zn[28]) );
DFFRXLTS d_ff4_Zn_Q_reg_29_ ( .D(n655), .CK(n1331), .RN(n1286), .Q(
d_ff_Zn[29]) );
DFFRXLTS d_ff4_Zn_Q_reg_30_ ( .D(n654), .CK(n1330), .RN(n1293), .Q(
d_ff_Zn[30]) );
DFFRXLTS d_ff4_Zn_Q_reg_31_ ( .D(n653), .CK(n1333), .RN(n1299), .Q(
d_ff_Zn[31]) );
DFFRXLTS reg_shift_x_Q_reg_24_ ( .D(n344), .CK(n1315), .RN(n1267), .Q(
d_ff3_sh_x_out[24]) );
DFFRXLTS reg_LUT_Q_reg_8_ ( .D(n516), .CK(n807), .RN(n1262), .Q(
d_ff3_LUT_out[8]) );
DFFRXLTS reg_shift_y_Q_reg_24_ ( .D(n408), .CK(n808), .RN(n1279), .Q(
d_ff3_sh_y_out[24]) );
DFFRXLTS reg_LUT_Q_reg_3_ ( .D(n521), .CK(n1320), .RN(n1271), .Q(
d_ff3_LUT_out[3]) );
DFFRXLTS reg_LUT_Q_reg_10_ ( .D(n514), .CK(n1314), .RN(n1284), .Q(
d_ff3_LUT_out[10]) );
DFFRXLTS reg_LUT_Q_reg_15_ ( .D(n509), .CK(n1313), .RN(n1263), .Q(
d_ff3_LUT_out[15]) );
DFFRXLTS reg_LUT_Q_reg_16_ ( .D(n508), .CK(n1314), .RN(n1263), .Q(
d_ff3_LUT_out[16]) );
DFFRXLTS reg_LUT_Q_reg_17_ ( .D(n507), .CK(n1313), .RN(n1263), .Q(
d_ff3_LUT_out[17]) );
DFFRXLTS reg_LUT_Q_reg_20_ ( .D(n504), .CK(n1315), .RN(n1277), .Q(
d_ff3_LUT_out[20]) );
DFFRXLTS reg_LUT_Q_reg_9_ ( .D(n515), .CK(n807), .RN(n1295), .Q(
d_ff3_LUT_out[9]) );
DFFRXLTS reg_LUT_Q_reg_21_ ( .D(n503), .CK(n808), .RN(n1278), .Q(
d_ff3_LUT_out[21]) );
DFFRXLTS reg_LUT_Q_reg_7_ ( .D(n517), .CK(n1322), .RN(n1296), .Q(
d_ff3_LUT_out[7]) );
DFFRXLTS reg_LUT_Q_reg_13_ ( .D(n511), .CK(n1315), .RN(n1273), .Q(
d_ff3_LUT_out[13]) );
DFFRXLTS reg_LUT_Q_reg_14_ ( .D(n510), .CK(n1316), .RN(n1265), .Q(
d_ff3_LUT_out[14]) );
DFFRXLTS reg_LUT_Q_reg_18_ ( .D(n506), .CK(n1314), .RN(n1273), .Q(
d_ff3_LUT_out[18]) );
DFFRXLTS reg_shift_x_Q_reg_25_ ( .D(n343), .CK(n808), .RN(n1273), .Q(
d_ff3_sh_x_out[25]) );
DFFRXLTS reg_shift_y_Q_reg_12_ ( .D(n438), .CK(n1307), .RN(n1274), .Q(
d_ff3_sh_y_out[12]) );
DFFRXLTS reg_shift_y_Q_reg_27_ ( .D(n405), .CK(n1332), .RN(n1284), .Q(
d_ff3_sh_y_out[27]) );
DFFRXLTS d_ff5_Q_reg_0_ ( .D(n588), .CK(n1325), .RN(n1298), .Q(
sign_inv_out[0]) );
DFFRXLTS d_ff5_Q_reg_1_ ( .D(n586), .CK(n1328), .RN(n1286), .Q(
sign_inv_out[1]) );
DFFRXLTS d_ff5_Q_reg_2_ ( .D(n584), .CK(n1325), .RN(n1299), .Q(
sign_inv_out[2]) );
DFFRXLTS d_ff5_Q_reg_3_ ( .D(n582), .CK(n1328), .RN(n1286), .Q(
sign_inv_out[3]) );
DFFRXLTS d_ff5_Q_reg_4_ ( .D(n580), .CK(n1324), .RN(n1298), .Q(
sign_inv_out[4]) );
DFFRXLTS d_ff5_Q_reg_5_ ( .D(n578), .CK(n1328), .RN(n1297), .Q(
sign_inv_out[5]) );
DFFRXLTS d_ff5_Q_reg_6_ ( .D(n576), .CK(n1325), .RN(n1262), .Q(
sign_inv_out[6]) );
DFFRXLTS d_ff5_Q_reg_7_ ( .D(n574), .CK(n1324), .RN(n1271), .Q(
sign_inv_out[7]) );
DFFRXLTS d_ff5_Q_reg_8_ ( .D(n572), .CK(n1323), .RN(n1296), .Q(
sign_inv_out[8]) );
DFFRXLTS d_ff5_Q_reg_9_ ( .D(n570), .CK(n806), .RN(n1297), .Q(
sign_inv_out[9]) );
DFFRXLTS d_ff5_Q_reg_10_ ( .D(n568), .CK(n1324), .RN(n1296), .Q(
sign_inv_out[10]) );
DFFRXLTS d_ff5_Q_reg_11_ ( .D(n566), .CK(n1325), .RN(n1262), .Q(
sign_inv_out[11]) );
DFFRXLTS d_ff5_Q_reg_12_ ( .D(n564), .CK(n1328), .RN(n1271), .Q(
sign_inv_out[12]) );
DFFRXLTS d_ff5_Q_reg_13_ ( .D(n562), .CK(n1326), .RN(n1295), .Q(
sign_inv_out[13]) );
DFFRXLTS d_ff5_Q_reg_14_ ( .D(n560), .CK(n806), .RN(n1291), .Q(
sign_inv_out[14]) );
DFFRXLTS d_ff5_Q_reg_15_ ( .D(n558), .CK(n1319), .RN(n1287), .Q(
sign_inv_out[15]) );
DFFRXLTS d_ff5_Q_reg_16_ ( .D(n556), .CK(n1318), .RN(n1290), .Q(
sign_inv_out[16]) );
DFFRXLTS d_ff5_Q_reg_17_ ( .D(n554), .CK(n1318), .RN(n1299), .Q(
sign_inv_out[17]) );
DFFRXLTS d_ff5_Q_reg_18_ ( .D(n552), .CK(n1321), .RN(n1293), .Q(
sign_inv_out[18]) );
DFFRXLTS d_ff5_Q_reg_19_ ( .D(n550), .CK(n1320), .RN(n1288), .Q(
sign_inv_out[19]) );
DFFRXLTS d_ff5_Q_reg_20_ ( .D(n548), .CK(n807), .RN(n1298), .Q(
sign_inv_out[20]) );
DFFRXLTS d_ff5_Q_reg_21_ ( .D(n546), .CK(n1318), .RN(n1293), .Q(
sign_inv_out[21]) );
DFFRXLTS d_ff5_Q_reg_22_ ( .D(n544), .CK(n1319), .RN(n1293), .Q(
sign_inv_out[22]) );
DFFRXLTS d_ff5_Q_reg_23_ ( .D(n542), .CK(n1321), .RN(n1298), .Q(
sign_inv_out[23]) );
DFFRXLTS d_ff5_Q_reg_24_ ( .D(n540), .CK(n1320), .RN(n1287), .Q(
sign_inv_out[24]) );
DFFRXLTS d_ff5_Q_reg_25_ ( .D(n538), .CK(n1320), .RN(n1290), .Q(
sign_inv_out[25]) );
DFFRXLTS d_ff5_Q_reg_26_ ( .D(n536), .CK(n1322), .RN(n1289), .Q(
sign_inv_out[26]) );
DFFRXLTS d_ff5_Q_reg_27_ ( .D(n534), .CK(n1321), .RN(n1290), .Q(
sign_inv_out[27]) );
DFFRXLTS d_ff5_Q_reg_28_ ( .D(n532), .CK(n1320), .RN(n1297), .Q(
sign_inv_out[28]) );
DFFRXLTS d_ff5_Q_reg_29_ ( .D(n530), .CK(n807), .RN(n1261), .Q(
sign_inv_out[29]) );
DFFRXLTS reg_shift_x_Q_reg_12_ ( .D(n374), .CK(n1304), .RN(n1277), .Q(
d_ff3_sh_x_out[12]) );
DFFRXLTS reg_shift_y_Q_reg_28_ ( .D(n404), .CK(n1317), .RN(n1284), .Q(
d_ff3_sh_y_out[28]) );
DFFRXLTS reg_LUT_Q_reg_4_ ( .D(n520), .CK(n1319), .RN(n1262), .Q(
d_ff3_LUT_out[4]) );
DFFRXLTS reg_shift_x_Q_reg_27_ ( .D(n341), .CK(n1316), .RN(n1265), .Q(
d_ff3_sh_x_out[27]) );
DFFRXLTS reg_shift_y_Q_reg_29_ ( .D(n403), .CK(n1327), .RN(n1267), .Q(
d_ff3_sh_y_out[29]) );
DFFRXLTS reg_LUT_Q_reg_24_ ( .D(n500), .CK(n1306), .RN(n1279), .Q(
d_ff3_LUT_out[24]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_0_ ( .D(n496), .CK(n1316), .RN(n1266),
.Q(d_ff2_Z[0]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_1_ ( .D(n495), .CK(n1314), .RN(n1273),
.Q(d_ff2_Z[1]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_2_ ( .D(n494), .CK(n1315), .RN(n1284),
.Q(d_ff2_Z[2]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_3_ ( .D(n493), .CK(n1314), .RN(n1265),
.Q(d_ff2_Z[3]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_4_ ( .D(n492), .CK(n1316), .RN(n1266),
.Q(d_ff2_Z[4]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_5_ ( .D(n491), .CK(n1316), .RN(n1273),
.Q(d_ff2_Z[5]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_6_ ( .D(n490), .CK(n808), .RN(n1284), .Q(
d_ff2_Z[6]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_7_ ( .D(n489), .CK(n1314), .RN(n1265),
.Q(d_ff2_Z[7]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_8_ ( .D(n488), .CK(n1316), .RN(n1267),
.Q(d_ff2_Z[8]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_9_ ( .D(n487), .CK(n1314), .RN(n1266),
.Q(d_ff2_Z[9]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_10_ ( .D(n486), .CK(n1316), .RN(n1266),
.Q(d_ff2_Z[10]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_11_ ( .D(n485), .CK(n1314), .RN(n1266),
.Q(d_ff2_Z[11]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_12_ ( .D(n484), .CK(n808), .RN(n1266),
.Q(d_ff2_Z[12]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_13_ ( .D(n483), .CK(n1313), .RN(n1266),
.Q(d_ff2_Z[13]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_14_ ( .D(n482), .CK(n1336), .RN(n1266),
.Q(d_ff2_Z[14]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_15_ ( .D(n481), .CK(n1313), .RN(n1266),
.Q(d_ff2_Z[15]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_16_ ( .D(n480), .CK(n1337), .RN(n1268),
.Q(d_ff2_Z[16]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_17_ ( .D(n479), .CK(n1316), .RN(n1268),
.Q(d_ff2_Z[17]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_18_ ( .D(n478), .CK(n808), .RN(n1268),
.Q(d_ff2_Z[18]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_19_ ( .D(n477), .CK(n1314), .RN(n1268),
.Q(d_ff2_Z[19]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_20_ ( .D(n476), .CK(n1332), .RN(n1268),
.Q(d_ff2_Z[20]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_21_ ( .D(n475), .CK(n1315), .RN(n1268),
.Q(d_ff2_Z[21]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_22_ ( .D(n474), .CK(n1313), .RN(n1268),
.Q(d_ff2_Z[22]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_26_ ( .D(n470), .CK(n1308), .RN(n1269),
.Q(d_ff2_Z[26]) );
DFFRX1TS reg_shift_x_Q_reg_23_ ( .D(n345), .CK(n1315), .RN(n1273), .Q(
d_ff3_sh_x_out[23]) );
DFFRX1TS reg_LUT_Q_reg_23_ ( .D(n501), .CK(n1336), .RN(n1264), .Q(
d_ff3_LUT_out[23]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_23_ ( .D(n473), .CK(n1337), .RN(n1268),
.Q(d_ff2_Z[23]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_24_ ( .D(n472), .CK(n1313), .RN(n1268),
.Q(d_ff2_Z[24]) );
DFFRX1TS reg_shift_y_Q_reg_23_ ( .D(n409), .CK(n1317), .RN(n1264), .Q(
d_ff3_sh_y_out[23]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_25_ ( .D(n471), .CK(n1315), .RN(n1268),
.Q(d_ff2_Z[25]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_27_ ( .D(n469), .CK(n1310), .RN(n1269),
.Q(d_ff2_Z[27]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_28_ ( .D(n468), .CK(n1311), .RN(n1269),
.Q(d_ff2_Z[28]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_29_ ( .D(n467), .CK(n1309), .RN(n1269),
.Q(d_ff2_Z[29]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_30_ ( .D(n466), .CK(n805), .RN(n1269),
.Q(d_ff2_Z[30]) );
DFFRX1TS reg_LUT_Q_reg_25_ ( .D(n499), .CK(n808), .RN(n1264), .Q(
d_ff3_LUT_out[25]) );
DFFRX1TS d_ff5_Q_reg_31_ ( .D(n526), .CK(n1320), .RN(n1261), .Q(
data_output2_31_) );
DFFRX1TS reg_LUT_Q_reg_1_ ( .D(n523), .CK(n1321), .RN(n1296), .Q(
d_ff3_LUT_out[1]) );
DFFRX1TS reg_LUT_Q_reg_2_ ( .D(n522), .CK(n1322), .RN(n1297), .Q(
d_ff3_LUT_out[2]) );
DFFRX1TS reg_LUT_Q_reg_0_ ( .D(n524), .CK(n1321), .RN(n1262), .Q(
d_ff3_LUT_out[0]) );
DFFRX1TS reg_LUT_Q_reg_6_ ( .D(n518), .CK(n1319), .RN(n1271), .Q(
d_ff3_LUT_out[6]) );
DFFRX1TS reg_sign_Q_reg_0_ ( .D(n464), .CK(n1311), .RN(n1269), .Q(
d_ff3_sign_out) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_0_ ( .D(n399), .CK(n1303), .RN(n1274),
.Q(d_ff2_X[0]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_4_ ( .D(n391), .CK(n1306), .RN(n1276),
.Q(d_ff2_X[4]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_8_ ( .D(n383), .CK(n1301), .RN(n1264),
.Q(d_ff2_X[8]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_9_ ( .D(n381), .CK(n1306), .RN(n1264),
.Q(d_ff2_X[9]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_11_ ( .D(n377), .CK(n1302), .RN(n1264),
.Q(d_ff2_X[11]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_15_ ( .D(n369), .CK(n1303), .RN(n1277),
.Q(d_ff2_X[15]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_18_ ( .D(n363), .CK(n1305), .RN(n1279),
.Q(d_ff2_X[18]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_21_ ( .D(n357), .CK(n1303), .RN(n1277),
.Q(d_ff2_X[21]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_22_ ( .D(n355), .CK(n1306), .RN(n1278),
.Q(d_ff2_X[22]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_31_ ( .D(n337), .CK(n1301), .RN(n1261),
.Q(d_ff2_X[31]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_0_ ( .D(n463), .CK(n1309), .RN(n1269),
.Q(d_ff2_Y[0]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_1_ ( .D(n461), .CK(n1310), .RN(n1269),
.Q(d_ff2_Y[1]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_2_ ( .D(n459), .CK(n1309), .RN(n1280),
.Q(d_ff2_Y[2]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_3_ ( .D(n457), .CK(n1308), .RN(n1283),
.Q(d_ff2_Y[3]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_4_ ( .D(n455), .CK(n1307), .RN(n1282),
.Q(d_ff2_Y[4]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_5_ ( .D(n453), .CK(n1311), .RN(n1270),
.Q(d_ff2_Y[5]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_6_ ( .D(n451), .CK(n805), .RN(n1295), .Q(
d_ff2_Y[6]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_7_ ( .D(n449), .CK(n1310), .RN(n1296),
.Q(d_ff2_Y[7]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_8_ ( .D(n447), .CK(n1309), .RN(n1297),
.Q(d_ff2_Y[8]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_9_ ( .D(n445), .CK(n1308), .RN(n1262),
.Q(d_ff2_Y[9]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_10_ ( .D(n443), .CK(n1310), .RN(n1271),
.Q(d_ff2_Y[10]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_11_ ( .D(n441), .CK(n805), .RN(n1272),
.Q(d_ff2_Y[11]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_12_ ( .D(n439), .CK(n1309), .RN(n1276),
.Q(d_ff2_Y[12]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_13_ ( .D(n437), .CK(n1311), .RN(n1274),
.Q(d_ff2_Y[13]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_14_ ( .D(n435), .CK(n1308), .RN(n1275),
.Q(d_ff2_Y[14]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_15_ ( .D(n433), .CK(n1309), .RN(n1272),
.Q(d_ff2_Y[15]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_16_ ( .D(n431), .CK(n805), .RN(n1267),
.Q(d_ff2_Y[16]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_17_ ( .D(n429), .CK(n1307), .RN(n1263),
.Q(d_ff2_Y[17]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_18_ ( .D(n427), .CK(n1311), .RN(n1284),
.Q(d_ff2_Y[18]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_19_ ( .D(n425), .CK(n805), .RN(n1266),
.Q(d_ff2_Y[19]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_20_ ( .D(n423), .CK(n1311), .RN(n1267),
.Q(d_ff2_Y[20]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_21_ ( .D(n421), .CK(n1310), .RN(n1272),
.Q(d_ff2_Y[21]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_22_ ( .D(n419), .CK(n805), .RN(n1276),
.Q(d_ff2_Y[22]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_31_ ( .D(n401), .CK(n1305), .RN(n1276),
.Q(d_ff2_Y[31]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_1_ ( .D(n397), .CK(n804), .RN(n1274), .Q(
d_ff2_X[1]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_2_ ( .D(n395), .CK(n1303), .RN(n1275),
.Q(d_ff2_X[2]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_3_ ( .D(n393), .CK(n1302), .RN(n1274),
.Q(d_ff2_X[3]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_5_ ( .D(n389), .CK(n804), .RN(n1275), .Q(
d_ff2_X[5]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_6_ ( .D(n387), .CK(n1305), .RN(n1272),
.Q(d_ff2_X[6]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_7_ ( .D(n385), .CK(n1303), .RN(n1276),
.Q(d_ff2_X[7]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_10_ ( .D(n379), .CK(n1302), .RN(n1264),
.Q(d_ff2_X[10]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_12_ ( .D(n375), .CK(n804), .RN(n1264),
.Q(d_ff2_X[12]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_13_ ( .D(n373), .CK(n1302), .RN(n1278),
.Q(d_ff2_X[13]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_14_ ( .D(n371), .CK(n1303), .RN(n1279),
.Q(d_ff2_X[14]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_16_ ( .D(n367), .CK(n804), .RN(n1277),
.Q(d_ff2_X[16]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_17_ ( .D(n365), .CK(n1301), .RN(n1278),
.Q(d_ff2_X[17]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_19_ ( .D(n361), .CK(n804), .RN(n1279),
.Q(d_ff2_X[19]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_20_ ( .D(n359), .CK(n1305), .RN(n1277),
.Q(d_ff2_X[20]) );
DFFRX1TS reg_ch_mux_1_Q_reg_0_ ( .D(n687), .CK(n1333), .RN(n1283), .Q(
sel_mux_1_reg) );
DFFRX1TS d_ff4_Xn_Q_reg_23_ ( .D(n597), .CK(n1320), .RN(n1292), .Q(
d_ff_Xn[23]) );
DFFRX1TS d_ff4_Xn_Q_reg_25_ ( .D(n595), .CK(n1321), .RN(n1294), .Q(
d_ff_Xn[25]) );
DFFRX1TS d_ff4_Xn_Q_reg_0_ ( .D(n620), .CK(n1325), .RN(n1292), .Q(d_ff_Xn[0]) );
DFFRX1TS d_ff4_Xn_Q_reg_4_ ( .D(n616), .CK(n1323), .RN(n1293), .Q(d_ff_Xn[4]) );
DFFRX1TS d_ff4_Xn_Q_reg_8_ ( .D(n612), .CK(n806), .RN(n1297), .Q(d_ff_Xn[8])
);
DFFRX1TS d_ff4_Xn_Q_reg_9_ ( .D(n611), .CK(n1327), .RN(n1262), .Q(d_ff_Xn[9]) );
DFFRX1TS d_ff4_Xn_Q_reg_11_ ( .D(n609), .CK(n1323), .RN(n1271), .Q(
d_ff_Xn[11]) );
DFFRX1TS d_ff4_Xn_Q_reg_15_ ( .D(n605), .CK(n1328), .RN(n1294), .Q(
d_ff_Xn[15]) );
DFFRX1TS d_ff4_Xn_Q_reg_18_ ( .D(n602), .CK(n1319), .RN(n1292), .Q(
d_ff_Xn[18]) );
DFFRX1TS d_ff4_Xn_Q_reg_21_ ( .D(n599), .CK(n1322), .RN(n1299), .Q(
d_ff_Xn[21]) );
DFFRX1TS d_ff4_Xn_Q_reg_22_ ( .D(n598), .CK(n1320), .RN(n1292), .Q(
d_ff_Xn[22]) );
DFFRX1TS d_ff4_Xn_Q_reg_30_ ( .D(n590), .CK(n1322), .RN(n1261), .Q(
d_ff_Xn[30]) );
DFFRX1TS d_ff4_Xn_Q_reg_31_ ( .D(n589), .CK(n1319), .RN(n1261), .Q(
d_ff_Xn[31]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_31_ ( .D(n465), .CK(n1310), .RN(n1269),
.Q(d_ff2_Z[31]) );
DFFRX1TS d_ff4_Xn_Q_reg_1_ ( .D(n619), .CK(n1324), .RN(n1286), .Q(d_ff_Xn[1]) );
DFFRX1TS d_ff4_Xn_Q_reg_2_ ( .D(n618), .CK(n1324), .RN(n1288), .Q(d_ff_Xn[2]) );
DFFRX1TS d_ff4_Xn_Q_reg_3_ ( .D(n617), .CK(n1324), .RN(n1298), .Q(d_ff_Xn[3]) );
DFFRX1TS d_ff4_Xn_Q_reg_5_ ( .D(n615), .CK(n1325), .RN(n1297), .Q(d_ff_Xn[5]) );
DFFRX1TS d_ff4_Xn_Q_reg_6_ ( .D(n614), .CK(n1327), .RN(n1296), .Q(d_ff_Xn[6]) );
DFFRX1TS d_ff4_Xn_Q_reg_7_ ( .D(n613), .CK(n1327), .RN(n1269), .Q(d_ff_Xn[7]) );
DFFRX1TS d_ff4_Xn_Q_reg_10_ ( .D(n610), .CK(n806), .RN(n1295), .Q(
d_ff_Xn[10]) );
DFFRX1TS d_ff4_Xn_Q_reg_12_ ( .D(n608), .CK(n806), .RN(n1295), .Q(
d_ff_Xn[12]) );
DFFRX1TS d_ff4_Xn_Q_reg_13_ ( .D(n607), .CK(n1328), .RN(n1296), .Q(
d_ff_Xn[13]) );
DFFRX1TS d_ff4_Xn_Q_reg_14_ ( .D(n606), .CK(n1328), .RN(n1294), .Q(
d_ff_Xn[14]) );
DFFRX1TS d_ff4_Xn_Q_reg_16_ ( .D(n604), .CK(n1321), .RN(n1294), .Q(
d_ff_Xn[16]) );
DFFRX1TS d_ff4_Xn_Q_reg_17_ ( .D(n603), .CK(n807), .RN(n1294), .Q(
d_ff_Xn[17]) );
DFFRX1TS d_ff4_Xn_Q_reg_19_ ( .D(n601), .CK(n1320), .RN(n1292), .Q(
d_ff_Xn[19]) );
DFFRX1TS d_ff4_Xn_Q_reg_20_ ( .D(n600), .CK(n807), .RN(n1292), .Q(
d_ff_Xn[20]) );
DFFRX1TS d_ff4_Xn_Q_reg_24_ ( .D(n596), .CK(n1322), .RN(n1294), .Q(
d_ff_Xn[24]) );
DFFRX1TS d_ff4_Xn_Q_reg_26_ ( .D(n594), .CK(n807), .RN(n1294), .Q(
d_ff_Xn[26]) );
DFFRX1TS d_ff4_Xn_Q_reg_27_ ( .D(n593), .CK(n1319), .RN(n1294), .Q(
d_ff_Xn[27]) );
DFFRX1TS d_ff4_Xn_Q_reg_28_ ( .D(n592), .CK(n807), .RN(n1289), .Q(
d_ff_Xn[28]) );
DFFRX1TS d_ff4_Xn_Q_reg_29_ ( .D(n591), .CK(n1322), .RN(n1261), .Q(
d_ff_Xn[29]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_30_ ( .D(n346), .CK(n1301), .RN(n1282),
.Q(d_ff2_X[30]) );
DFFRX1TS reg_ch_mux_3_Q_reg_0_ ( .D(n688), .CK(n1329), .RN(n1282), .Q(
sel_mux_3_reg) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_26_ ( .D(n414), .CK(n1308), .RN(n1274),
.Q(d_ff2_Y[26]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_26_ ( .D(n350), .CK(n1302), .RN(n1285),
.Q(d_ff2_X[26]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_25_ ( .D(n415), .CK(n1311), .RN(n1275),
.Q(d_ff2_Y[25]) );
DFFRX1TS reg_ch_mux_2_Q_reg_1_ ( .D(n685), .CK(n1331), .RN(n1270), .Q(
sel_mux_2_reg[1]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_28_ ( .D(n348), .CK(n804), .RN(n1270),
.Q(d_ff2_X[28]) );
DFFRX1TS reg_LUT_Q_reg_27_ ( .D(n497), .CK(n1313), .RN(n1264), .Q(
d_ff3_LUT_out[27]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_29_ ( .D(n347), .CK(n1301), .RN(n1280),
.Q(d_ff2_X[29]) );
DFFRX2TS reg_val_muxX_2stage_Q_reg_24_ ( .D(n352), .CK(n1303), .RN(n1281),
.Q(d_ff2_X[24]) );
DFFRX2TS reg_val_muxX_2stage_Q_reg_27_ ( .D(n349), .CK(n804), .RN(n1281),
.Q(d_ff2_X[27]) );
DFFRX2TS cont_iter_count_reg_2_ ( .D(n726), .CK(n1338), .RN(n1281), .Q(
cont_iter_out[2]), .QN(n1224) );
DFFRX1TS reg_LUT_Q_reg_26_ ( .D(n498), .CK(n1315), .RN(n1264), .Q(
d_ff3_LUT_out[26]) );
DFFRX1TS reg_LUT_Q_reg_11_ ( .D(n513), .CK(n808), .RN(n1265), .Q(
d_ff3_LUT_out[11]) );
DFFRX1TS reg_LUT_Q_reg_5_ ( .D(n519), .CK(n1318), .RN(n1297), .Q(
d_ff3_LUT_out[5]) );
DFFRX4TS cordic_FSM_state_reg_reg_1_ ( .D(cordic_FSM_state_next_1_), .CK(
n1338), .RN(n331), .Q(cordic_FSM_state_reg[1]) );
DFFRX2TS cordic_FSM_state_reg_reg_3_ ( .D(n732), .CK(n1338), .RN(n331), .Q(
cordic_FSM_state_reg[3]), .QN(n799) );
DFFRXLTS d_ff5_Q_reg_30_ ( .D(n528), .CK(n1319), .RN(n1261), .Q(
sign_inv_out[30]) );
DFFRXLTS reg_shift_y_Q_reg_8_ ( .D(n446), .CK(n805), .RN(n1297), .Q(
d_ff3_sh_y_out[8]) );
DFFRX2TS cordic_FSM_state_reg_reg_2_ ( .D(n731), .CK(n1338), .RN(n331), .Q(
cordic_FSM_state_reg[2]), .QN(n1215) );
CLKBUFX3TS U795 ( .A(n985), .Y(n998) );
OAI32X1TS U796 ( .A0(cont_iter_out[2]), .A1(n1112), .A2(n1166), .B0(n831),
.B1(n1224), .Y(n726) );
AO22XLTS U797 ( .A0(d_ff_Yn[20]), .A1(n1100), .B0(d_ff2_Y[20]), .B1(n1133),
.Y(n423) );
AO22XLTS U798 ( .A0(d_ff_Yn[19]), .A1(n1100), .B0(d_ff2_Y[19]), .B1(n1133),
.Y(n425) );
AO22XLTS U799 ( .A0(n1053), .A1(data_in[0]), .B0(n1167), .B1(d_ff1_Z[0]),
.Y(n720) );
OR3X1TS U800 ( .A(n1215), .B(n799), .C(n821), .Y(n798) );
CLKBUFX3TS U801 ( .A(n983), .Y(n980) );
CLKBUFX3TS U802 ( .A(n1199), .Y(n1195) );
CLKBUFX2TS U803 ( .A(clk), .Y(n836) );
CLKBUFX3TS U804 ( .A(n818), .Y(n817) );
CLKBUFX3TS U805 ( .A(n1172), .Y(n818) );
BUFX3TS U806 ( .A(n818), .Y(n816) );
BUFX3TS U807 ( .A(n816), .Y(n830) );
INVX2TS U808 ( .A(n1193), .Y(n1099) );
CLKBUFX3TS U809 ( .A(n1090), .Y(n1193) );
INVX2TS U810 ( .A(cordic_FSM_state_reg[3]), .Y(n800) );
INVX2TS U811 ( .A(n1193), .Y(n801) );
INVX2TS U812 ( .A(n1193), .Y(n802) );
AOI222X1TS U813 ( .A0(n1010), .A1(d_ff3_LUT_out[8]), .B0(n1151), .B1(
d_ff3_sh_x_out[8]), .C0(n1017), .C1(d_ff3_sh_y_out[8]), .Y(n1011) );
CLKBUFX3TS U814 ( .A(n983), .Y(n1010) );
NOR4X1TS U815 ( .A(cordic_FSM_state_reg[1]), .B(n1215), .C(n1225), .D(n799),
.Y(ready_cordic) );
INVX2TS U816 ( .A(n798), .Y(n803) );
CLKBUFX3TS U817 ( .A(n980), .Y(n988) );
OAI2BB2X2TS U818 ( .B0(n1217), .B1(d_ff2_X[24]), .A0N(n1146), .A1N(n1144),
.Y(n1103) );
NOR2X2TS U819 ( .A(d_ff2_X[23]), .B(n1216), .Y(n1146) );
NOR2X2TS U820 ( .A(cordic_FSM_state_reg[0]), .B(cordic_FSM_state_reg[3]),
.Y(n1044) );
CLKINVX3TS U821 ( .A(n1108), .Y(n1205) );
CLKBUFX3TS U822 ( .A(n1132), .Y(n1108) );
AOI222X4TS U823 ( .A0(n882), .A1(d_ff2_Z[6]), .B0(n870), .B1(d_ff1_Z[6]),
.C0(d_ff_Zn[6]), .C1(n894), .Y(n864) );
AOI222X1TS U824 ( .A0(n899), .A1(d_ff2_Z[21]), .B0(n885), .B1(d_ff1_Z[21]),
.C0(d_ff_Zn[21]), .C1(n894), .Y(n886) );
AOI222X1TS U825 ( .A0(n899), .A1(d_ff2_Z[25]), .B0(n902), .B1(d_ff1_Z[25]),
.C0(d_ff_Zn[25]), .C1(n894), .Y(n895) );
CLKINVX3TS U826 ( .A(n1194), .Y(n894) );
CLKINVX3TS U827 ( .A(n1195), .Y(n901) );
CLKINVX3TS U828 ( .A(n998), .Y(n1154) );
AOI222X1TS U829 ( .A0(n1067), .A1(d_ff2_Z[9]), .B0(n874), .B1(d_ff1_Z[9]),
.C0(d_ff_Zn[9]), .C1(n894), .Y(n867) );
AOI222X4TS U830 ( .A0(n1067), .A1(d_ff2_Z[8]), .B0(n870), .B1(d_ff1_Z[8]),
.C0(d_ff_Zn[8]), .C1(n898), .Y(n866) );
AOI222X1TS U831 ( .A0(n1067), .A1(d_ff2_Z[7]), .B0(n874), .B1(d_ff1_Z[7]),
.C0(d_ff_Zn[7]), .C1(n894), .Y(n865) );
AOI222X1TS U832 ( .A0(n1067), .A1(d_ff2_Z[5]), .B0(n874), .B1(d_ff1_Z[5]),
.C0(d_ff_Zn[5]), .C1(n894), .Y(n863) );
AOI222X4TS U833 ( .A0(n1067), .A1(d_ff2_Z[4]), .B0(n870), .B1(d_ff1_Z[4]),
.C0(d_ff_Zn[4]), .C1(n894), .Y(n862) );
AOI222X1TS U834 ( .A0(n1067), .A1(d_ff2_Z[3]), .B0(n874), .B1(d_ff1_Z[3]),
.C0(d_ff_Zn[3]), .C1(n894), .Y(n861) );
AOI222X4TS U835 ( .A0(n1067), .A1(d_ff2_Z[2]), .B0(n870), .B1(d_ff1_Z[2]),
.C0(d_ff_Zn[2]), .C1(n1092), .Y(n860) );
AOI222X1TS U836 ( .A0(n1067), .A1(d_ff2_Z[1]), .B0(n870), .B1(d_ff1_Z[1]),
.C0(d_ff_Zn[1]), .C1(n1092), .Y(n859) );
AOI222X1TS U837 ( .A0(n801), .A1(d_ff2_Z[0]), .B0(n901), .B1(d_ff_Zn[0]),
.C0(n870), .C1(d_ff1_Z[0]), .Y(n858) );
NAND2X2TS U838 ( .A(cont_iter_out[2]), .B(n1189), .Y(n1105) );
CLKINVX3TS U839 ( .A(n1108), .Y(n1189) );
NAND2X2TS U840 ( .A(n1217), .B(n1223), .Y(n1094) );
NOR2X2TS U841 ( .A(cordic_FSM_state_reg[1]), .B(cordic_FSM_state_reg[3]),
.Y(n1135) );
CLKBUFX3TS U842 ( .A(n937), .Y(n928) );
NAND3X2TS U843 ( .A(n1157), .B(cordic_FSM_state_reg[0]), .C(
cordic_FSM_state_reg[3]), .Y(n937) );
CLKINVX3TS U844 ( .A(n830), .Y(n1290) );
CLKINVX3TS U845 ( .A(n830), .Y(n1289) );
CLKINVX3TS U846 ( .A(n830), .Y(n1287) );
CLKINVX3TS U847 ( .A(n830), .Y(n1291) );
CLKINVX3TS U848 ( .A(n830), .Y(n1300) );
CLKINVX3TS U849 ( .A(n816), .Y(n1292) );
CLKINVX3TS U850 ( .A(n816), .Y(n1298) );
CLKINVX3TS U851 ( .A(n816), .Y(n1288) );
CLKINVX3TS U852 ( .A(n816), .Y(n1293) );
CLKINVX3TS U853 ( .A(n830), .Y(n1270) );
CLKINVX3TS U854 ( .A(n816), .Y(n1285) );
CLKINVX3TS U855 ( .A(n816), .Y(n1266) );
CLKINVX3TS U856 ( .A(n817), .Y(n1263) );
CLKINVX3TS U857 ( .A(n830), .Y(n1284) );
CLKINVX3TS U858 ( .A(n818), .Y(n1273) );
CLKINVX3TS U859 ( .A(n817), .Y(n1297) );
CLKINVX3TS U860 ( .A(n830), .Y(n1294) );
CLKINVX3TS U861 ( .A(n817), .Y(n1296) );
CLKINVX3TS U862 ( .A(n1172), .Y(n1261) );
CLKINVX3TS U863 ( .A(n815), .Y(n1264) );
CLKINVX3TS U864 ( .A(n815), .Y(n1278) );
CLKINVX3TS U865 ( .A(n815), .Y(n1279) );
CLKINVX3TS U866 ( .A(n815), .Y(n1277) );
CLKINVX3TS U867 ( .A(n816), .Y(n1299) );
CLKINVX3TS U868 ( .A(n816), .Y(n1286) );
CLKINVX3TS U869 ( .A(n818), .Y(n1272) );
CLKINVX3TS U870 ( .A(n817), .Y(n1269) );
CLKINVX3TS U871 ( .A(n817), .Y(n1262) );
CLKINVX3TS U872 ( .A(n817), .Y(n1271) );
CLKINVX3TS U873 ( .A(n817), .Y(n1295) );
CLKINVX3TS U874 ( .A(n817), .Y(n1267) );
CLKINVX3TS U875 ( .A(n815), .Y(n1265) );
CLKINVX3TS U876 ( .A(n818), .Y(n1268) );
CLKINVX3TS U877 ( .A(n818), .Y(n1276) );
CLKINVX3TS U878 ( .A(n818), .Y(n1274) );
CLKINVX3TS U879 ( .A(n818), .Y(n1275) );
INVX3TS U880 ( .A(n830), .Y(n1281) );
CLKINVX3TS U881 ( .A(n817), .Y(n1283) );
CLKINVX3TS U882 ( .A(n818), .Y(n1282) );
BUFX3TS U883 ( .A(n833), .Y(n1306) );
CLKINVX6TS U884 ( .A(n812), .Y(n804) );
BUFX6TS U885 ( .A(n833), .Y(n1305) );
BUFX6TS U886 ( .A(n833), .Y(n1301) );
BUFX6TS U887 ( .A(n833), .Y(n1302) );
BUFX6TS U888 ( .A(n833), .Y(n1303) );
BUFX3TS U889 ( .A(n835), .Y(n1307) );
CLKINVX6TS U890 ( .A(n810), .Y(n805) );
BUFX6TS U891 ( .A(n835), .Y(n1308) );
BUFX6TS U892 ( .A(n835), .Y(n1311) );
BUFX6TS U893 ( .A(n835), .Y(n1310) );
BUFX6TS U894 ( .A(n835), .Y(n1309) );
BUFX3TS U895 ( .A(n832), .Y(n1327) );
CLKINVX6TS U896 ( .A(n812), .Y(n806) );
BUFX6TS U897 ( .A(n832), .Y(n1325) );
BUFX6TS U898 ( .A(n832), .Y(n1328) );
BUFX6TS U899 ( .A(n832), .Y(n1323) );
BUFX6TS U900 ( .A(n832), .Y(n1324) );
CLKINVX6TS U901 ( .A(n810), .Y(n807) );
CLKBUFX2TS U902 ( .A(n834), .Y(n1317) );
BUFX6TS U903 ( .A(n834), .Y(n1318) );
BUFX6TS U904 ( .A(n834), .Y(n1319) );
BUFX6TS U905 ( .A(n834), .Y(n1320) );
BUFX6TS U906 ( .A(n834), .Y(n1321) );
BUFX6TS U907 ( .A(n834), .Y(n1322) );
BUFX4TS U908 ( .A(n836), .Y(n808) );
BUFX6TS U909 ( .A(n836), .Y(n1315) );
BUFX6TS U910 ( .A(n836), .Y(n1316) );
BUFX6TS U911 ( .A(n836), .Y(n1313) );
BUFX6TS U912 ( .A(n836), .Y(n1314) );
CLKINVX6TS U913 ( .A(n810), .Y(n809) );
CLKBUFX2TS U914 ( .A(clk), .Y(n1332) );
BUFX6TS U915 ( .A(n1317), .Y(n1330) );
BUFX6TS U916 ( .A(n836), .Y(n1331) );
BUFX6TS U917 ( .A(n1312), .Y(n1329) );
BUFX6TS U918 ( .A(n1304), .Y(n1334) );
BUFX6TS U919 ( .A(n1326), .Y(n1333) );
INVX2TS U920 ( .A(n1337), .Y(n810) );
CLKINVX6TS U921 ( .A(n810), .Y(n811) );
CLKBUFX2TS U922 ( .A(clk), .Y(n1337) );
INVX2TS U923 ( .A(n1336), .Y(n812) );
CLKINVX6TS U924 ( .A(n812), .Y(n813) );
CLKBUFX2TS U925 ( .A(clk), .Y(n1336) );
NAND3X2TS U926 ( .A(cordic_FSM_state_reg[2]), .B(n1158), .C(n799), .Y(n1133)
);
NOR2X4TS U927 ( .A(cordic_FSM_state_reg[1]), .B(cordic_FSM_state_reg[0]),
.Y(n1158) );
AOI222X4TS U928 ( .A0(d_ff3_LUT_out[24]), .A1(n1005), .B0(d_ff3_sh_y_out[24]), .B1(n1021), .C0(d_ff3_sh_x_out[24]), .C1(n975), .Y(n990) );
AOI221X4TS U929 ( .A0(n1087), .A1(n1205), .B0(d_ff3_LUT_out[24]), .B1(n1203),
.C0(n1082), .Y(n1084) );
NOR2BX2TS U930 ( .AN(n1027), .B(n1026), .Y(n1028) );
NOR3X1TS U931 ( .A(n1159), .B(cont_var_out[0]), .C(n1218), .Y(n1027) );
NOR2X2TS U932 ( .A(d_ff2_Y[23]), .B(n1216), .Y(n1125) );
CLKBUFX3TS U933 ( .A(n1062), .Y(n1052) );
CLKBUFX3TS U934 ( .A(n1149), .Y(n1129) );
CLKBUFX3TS U935 ( .A(n1049), .Y(n1042) );
CLKINVX3TS U936 ( .A(n998), .Y(n1012) );
CLKINVX3TS U937 ( .A(n1194), .Y(n898) );
CLKBUFX3TS U938 ( .A(n1195), .Y(n1194) );
CLKBUFX3TS U939 ( .A(n837), .Y(n983) );
CLKBUFX3TS U940 ( .A(n1101), .Y(n1192) );
CLKINVX3TS U941 ( .A(n1193), .Y(n882) );
CLKINVX3TS U942 ( .A(n1193), .Y(n899) );
CLKINVX3TS U943 ( .A(n830), .Y(n1280) );
BUFX4TS U944 ( .A(clk), .Y(n1335) );
BUFX4TS U945 ( .A(clk), .Y(n1338) );
INVX2TS U946 ( .A(n1224), .Y(n814) );
AOI222X1TS U947 ( .A0(cont_iter_out[2]), .A1(n1103), .B0(n814), .B1(n1228),
.C0(n1103), .C1(n1228), .Y(n1063) );
AOI222X4TS U948 ( .A0(n1114), .A1(cont_iter_out[2]), .B0(n1114), .B1(n1216),
.C0(cont_iter_out[3]), .C1(n1224), .Y(n1186) );
OAI211X2TS U949 ( .A0(n814), .A1(n1094), .B0(n1205), .C0(n1188), .Y(n1190)
);
NOR4X4TS U950 ( .A(cordic_FSM_state_reg[2]), .B(cordic_FSM_state_reg[1]),
.C(n1225), .D(n799), .Y(ack_add_subt) );
OAI21XLTS U951 ( .A0(n1085), .A1(n1229), .B0(n893), .Y(n409) );
OAI21XLTS U952 ( .A0(n1209), .A1(n918), .B0(n853), .Y(n532) );
OAI21XLTS U953 ( .A0(n1251), .A1(n944), .B0(n943), .Y(n562) );
OAI21XLTS U954 ( .A0(n1235), .A1(n840), .B0(n839), .Y(add_subt_dataB[12]) );
OAI21XLTS U955 ( .A0(n1237), .A1(n985), .B0(n984), .Y(add_subt_dataB[28]) );
OAI21XLTS U956 ( .A0(n1229), .A1(n985), .B0(n951), .Y(add_subt_dataA[23]) );
OAI21XLTS U957 ( .A0(n1230), .A1(n985), .B0(n954), .Y(add_subt_dataA[28]) );
AND3X1TS U958 ( .A(n1158), .B(n1215), .C(n800), .Y(n1172) );
CLKBUFX2TS U959 ( .A(n816), .Y(n815) );
NAND2X2TS U960 ( .A(cont_iter_out[0]), .B(cont_iter_out[1]), .Y(n1112) );
NAND2X2TS U961 ( .A(cont_iter_out[2]), .B(cont_iter_out[3]), .Y(n1188) );
NOR2X2TS U962 ( .A(n1112), .B(n1188), .Y(n1159) );
INVX2TS U963 ( .A(n1159), .Y(n1065) );
XNOR2X1TS U964 ( .A(d_ff1_shift_region_flag_out[1]), .B(d_ff1_operation_out),
.Y(n819) );
XOR2X1TS U965 ( .A(d_ff1_shift_region_flag_out[0]), .B(n819), .Y(n916) );
NOR2X1TS U966 ( .A(n916), .B(n1065), .Y(n828) );
AOI21X1TS U967 ( .A0(cont_var_out[0]), .A1(n1065), .B0(n828), .Y(n1171) );
NAND4X1TS U968 ( .A(cordic_FSM_state_reg[3]), .B(n1158), .C(ready_add_subt),
.D(n1215), .Y(n1026) );
NOR2XLTS U969 ( .A(n1171), .B(n1026), .Y(n820) );
CLKBUFX2TS U970 ( .A(n820), .Y(n824) );
CLKBUFX2TS U971 ( .A(n824), .Y(n1174) );
CLKBUFX3TS U972 ( .A(n1174), .Y(n1176) );
OAI2BB2XLTS U973 ( .B0(n1176), .B1(n1240), .A0N(n824), .A1N(
result_add_subt[2]), .Y(n650) );
CLKBUFX2TS U974 ( .A(n1174), .Y(n826) );
OAI2BB2XLTS U975 ( .B0(n1176), .B1(n1238), .A0N(n826), .A1N(
result_add_subt[0]), .Y(n652) );
CLKBUFX3TS U976 ( .A(n826), .Y(n1175) );
OAI2BB2XLTS U977 ( .B0(n1175), .B1(n1241), .A0N(n824), .A1N(
result_add_subt[3]), .Y(n649) );
OAI2BB2XLTS U978 ( .B0(n1175), .B1(n1239), .A0N(n826), .A1N(
result_add_subt[1]), .Y(n651) );
OAI2BB2XLTS U979 ( .B0(n1175), .B1(n1242), .A0N(n824), .A1N(
result_add_subt[4]), .Y(n648) );
INVX2TS U980 ( .A(n1158), .Y(n821) );
INVX2TS U981 ( .A(n803), .Y(n1062) );
CLKBUFX2TS U982 ( .A(n1062), .Y(n1068) );
INVX2TS U983 ( .A(n1068), .Y(n1038) );
OAI33X1TS U984 ( .A0(d_ff1_shift_region_flag_out[1]), .A1(
d_ff1_operation_out), .A2(n1222), .B0(n1214), .B1(n1260), .B2(
d_ff1_shift_region_flag_out[0]), .Y(n822) );
XOR2XLTS U985 ( .A(data_output2_31_), .B(n822), .Y(n823) );
AO22XLTS U986 ( .A0(n1038), .A1(n823), .B0(n798), .B1(data_output[31]), .Y(
n525) );
CLKBUFX3TS U987 ( .A(n1174), .Y(n1177) );
OAI2BB2XLTS U988 ( .B0(n1177), .B1(n1258), .A0N(n826), .A1N(
result_add_subt[31]), .Y(n621) );
CLKBUFX3TS U989 ( .A(n824), .Y(n1179) );
OAI2BB2XLTS U990 ( .B0(n1179), .B1(n1207), .A0N(n1174), .A1N(
result_add_subt[24]), .Y(n628) );
OAI2BB2XLTS U991 ( .B0(n1179), .B1(n1208), .A0N(n826), .A1N(
result_add_subt[27]), .Y(n625) );
OAI2BB2XLTS U992 ( .B0(n1179), .B1(n1209), .A0N(n824), .A1N(
result_add_subt[28]), .Y(n624) );
OAI2BB2XLTS U993 ( .B0(n1179), .B1(n1210), .A0N(n1174), .A1N(
result_add_subt[29]), .Y(n623) );
OAI2BB2XLTS U994 ( .B0(n1179), .B1(n1211), .A0N(n1174), .A1N(
result_add_subt[21]), .Y(n631) );
OAI2BB2XLTS U995 ( .B0(n1179), .B1(n1212), .A0N(n826), .A1N(
result_add_subt[25]), .Y(n627) );
OAI2BB2XLTS U996 ( .B0(n1179), .B1(n1213), .A0N(n824), .A1N(
result_add_subt[26]), .Y(n626) );
NAND2X1TS U997 ( .A(n1215), .B(cordic_FSM_state_reg[1]), .Y(n1048) );
INVX2TS U998 ( .A(n1048), .Y(n1157) );
NAND2X1TS U999 ( .A(n1157), .B(n1044), .Y(n825) );
INVX2TS U1000 ( .A(n825), .Y(n1050) );
CLKBUFX2TS U1001 ( .A(n1050), .Y(n1049) );
INVX2TS U1002 ( .A(n1050), .Y(n1055) );
AO22XLTS U1003 ( .A0(n1049), .A1(data_in[21]), .B0(n1055), .B1(d_ff1_Z[21]),
.Y(n699) );
AO22XLTS U1004 ( .A0(n1049), .A1(data_in[22]), .B0(n1055), .B1(d_ff1_Z[22]),
.Y(n698) );
OAI2BB2XLTS U1005 ( .B0(n1179), .B1(n1219), .A0N(n826), .A1N(
result_add_subt[30]), .Y(n622) );
AOI21X1TS U1006 ( .A0(n1227), .A1(n1218), .B0(n1159), .Y(n827) );
OR3X2TS U1007 ( .A(n828), .B(n827), .C(n1026), .Y(n1149) );
CLKBUFX2TS U1008 ( .A(n1149), .Y(n1139) );
INVX2TS U1009 ( .A(n1139), .Y(n829) );
CLKBUFX2TS U1010 ( .A(n1149), .Y(n1141) );
AO22XLTS U1011 ( .A0(n829), .A1(result_add_subt[31]), .B0(n1141), .B1(
d_ff_Xn[31]), .Y(n589) );
AO22XLTS U1012 ( .A0(n829), .A1(result_add_subt[30]), .B0(n1141), .B1(
d_ff_Xn[30]), .Y(n590) );
INVX2TS U1013 ( .A(n1133), .Y(n1198) );
CLKBUFX3TS U1014 ( .A(n1198), .Y(n1090) );
CLKBUFX3TS U1015 ( .A(n1090), .Y(n1200) );
NAND2X1TS U1016 ( .A(n1198), .B(sel_mux_1_reg), .Y(n1199) );
CLKBUFX3TS U1017 ( .A(n1195), .Y(n1197) );
OA22X1TS U1018 ( .A0(n1200), .A1(d_ff2_X[20]), .B0(d_ff_Xn[20]), .B1(n1197),
.Y(n359) );
OA22X1TS U1019 ( .A0(n1200), .A1(d_ff2_X[19]), .B0(d_ff_Xn[19]), .B1(n1197),
.Y(n361) );
OA22X1TS U1020 ( .A0(n1200), .A1(d_ff2_X[17]), .B0(d_ff_Xn[17]), .B1(n1197),
.Y(n365) );
OA22X1TS U1021 ( .A0(n1200), .A1(d_ff2_X[16]), .B0(d_ff_Xn[16]), .B1(n1197),
.Y(n367) );
OA22X1TS U1022 ( .A0(n1200), .A1(d_ff2_X[14]), .B0(d_ff_Xn[14]), .B1(n1197),
.Y(n371) );
OA22X1TS U1023 ( .A0(n1090), .A1(d_ff2_X[13]), .B0(d_ff_Xn[13]), .B1(n1197),
.Y(n373) );
CLKBUFX2TS U1024 ( .A(n1195), .Y(n1196) );
OA22X1TS U1025 ( .A0(n1090), .A1(d_ff2_X[6]), .B0(d_ff_Xn[6]), .B1(n1196),
.Y(n387) );
OA22X1TS U1026 ( .A0(n1090), .A1(d_ff2_X[3]), .B0(d_ff_Xn[3]), .B1(n1196),
.Y(n393) );
OA22X1TS U1027 ( .A0(n1193), .A1(d_ff2_X[2]), .B0(d_ff_Xn[2]), .B1(n1196),
.Y(n395) );
OA22X1TS U1028 ( .A0(n1090), .A1(d_ff2_X[1]), .B0(d_ff_Xn[1]), .B1(n1195),
.Y(n397) );
OA22X1TS U1029 ( .A0(n1200), .A1(d_ff2_X[26]), .B0(d_ff_Xn[26]), .B1(n1197),
.Y(n350) );
OA22X1TS U1030 ( .A0(n1193), .A1(d_ff2_X[28]), .B0(d_ff_Xn[28]), .B1(n1194),
.Y(n348) );
OA22X1TS U1031 ( .A0(n1193), .A1(d_ff2_X[29]), .B0(d_ff_Xn[29]), .B1(n1197),
.Y(n347) );
OA22X1TS U1032 ( .A0(d_ff2_X[24]), .A1(n1090), .B0(d_ff_Xn[24]), .B1(n1197),
.Y(n352) );
NAND2X2TS U1033 ( .A(ack_add_subt), .B(n1027), .Y(n1166) );
INVX2TS U1034 ( .A(n1053), .Y(n1167) );
OAI21XLTS U1035 ( .A0(n1112), .A1(n1166), .B0(n1167), .Y(n831) );
CLKBUFX2TS U1036 ( .A(clk), .Y(n832) );
CLKBUFX2TS U1037 ( .A(clk), .Y(n834) );
BUFX3TS U1038 ( .A(n832), .Y(n1326) );
CLKBUFX2TS U1039 ( .A(clk), .Y(n833) );
BUFX3TS U1040 ( .A(n833), .Y(n1304) );
CLKBUFX2TS U1041 ( .A(clk), .Y(n835) );
BUFX3TS U1042 ( .A(n835), .Y(n1312) );
NOR2X1TS U1043 ( .A(sel_mux_2_reg[0]), .B(sel_mux_2_reg[1]), .Y(n986) );
CLKBUFX2TS U1044 ( .A(n986), .Y(n1003) );
CLKBUFX2TS U1045 ( .A(n1003), .Y(n979) );
CLKBUFX2TS U1046 ( .A(n979), .Y(n1152) );
NAND2X1TS U1047 ( .A(n1231), .B(sel_mux_2_reg[1]), .Y(n840) );
INVX2TS U1048 ( .A(n840), .Y(n837) );
OR2X2TS U1049 ( .A(n1231), .B(sel_mux_2_reg[1]), .Y(n985) );
AOI22X1TS U1050 ( .A0(d_ff2_Z[25]), .A1(n983), .B0(d_ff2_Y[25]), .B1(n1151),
.Y(n838) );
OAI2BB1X1TS U1051 ( .A0N(d_ff2_X[25]), .A1N(n1152), .B0(n838), .Y(
add_subt_dataA[25]) );
CLKBUFX3TS U1052 ( .A(n979), .Y(n1153) );
AOI22X1TS U1053 ( .A0(n1154), .A1(d_ff3_sh_x_out[12]), .B0(n1153), .B1(
d_ff3_sh_y_out[12]), .Y(n839) );
INVX2TS U1054 ( .A(rst), .Y(n331) );
NAND3X1TS U1055 ( .A(cont_iter_out[1]), .B(cont_iter_out[0]), .C(n1223), .Y(
n1081) );
NAND2X1TS U1056 ( .A(cont_iter_out[3]), .B(n1167), .Y(n841) );
OAI31X1TS U1057 ( .A0(n1166), .A1(n1224), .A2(n1081), .B0(n841), .Y(n725) );
NAND2BX1TS U1058 ( .AN(n928), .B(sel_mux_3_reg), .Y(n856) );
CLKBUFX2TS U1059 ( .A(n856), .Y(n918) );
CLKBUFX3TS U1060 ( .A(n918), .Y(n944) );
NOR2X2TS U1061 ( .A(sel_mux_3_reg), .B(n937), .Y(n919) );
CLKBUFX2TS U1062 ( .A(n919), .Y(n854) );
CLKBUFX3TS U1063 ( .A(n854), .Y(n942) );
CLKBUFX3TS U1064 ( .A(n928), .Y(n941) );
AOI22X1TS U1065 ( .A0(d_ff_Xn[18]), .A1(n942), .B0(sign_inv_out[18]), .B1(
n941), .Y(n842) );
OAI21XLTS U1066 ( .A0(n1256), .A1(n944), .B0(n842), .Y(n552) );
AOI22X1TS U1067 ( .A0(d_ff_Xn[19]), .A1(n942), .B0(sign_inv_out[19]), .B1(
n941), .Y(n843) );
OAI21XLTS U1068 ( .A0(n1257), .A1(n944), .B0(n843), .Y(n550) );
AOI22X1TS U1069 ( .A0(d_ff_Xn[20]), .A1(n919), .B0(sign_inv_out[20]), .B1(
n941), .Y(n844) );
OAI21XLTS U1070 ( .A0(n1220), .A1(n918), .B0(n844), .Y(n548) );
CLKBUFX2TS U1071 ( .A(n856), .Y(n908) );
AOI22X1TS U1072 ( .A0(d_ff_Xn[21]), .A1(n919), .B0(sign_inv_out[21]), .B1(
n941), .Y(n845) );
OAI21XLTS U1073 ( .A0(n1211), .A1(n908), .B0(n845), .Y(n546) );
CLKBUFX2TS U1074 ( .A(n854), .Y(n906) );
CLKBUFX3TS U1075 ( .A(n928), .Y(n905) );
AOI22X1TS U1076 ( .A0(d_ff_Xn[22]), .A1(n906), .B0(sign_inv_out[22]), .B1(
n905), .Y(n846) );
OAI21XLTS U1077 ( .A0(n1221), .A1(n918), .B0(n846), .Y(n544) );
AOI22X1TS U1078 ( .A0(d_ff_Xn[23]), .A1(n854), .B0(sign_inv_out[23]), .B1(
n905), .Y(n847) );
OAI21XLTS U1079 ( .A0(n1206), .A1(n908), .B0(n847), .Y(n542) );
AOI22X1TS U1080 ( .A0(d_ff_Xn[24]), .A1(n906), .B0(sign_inv_out[24]), .B1(
n905), .Y(n848) );
OAI21XLTS U1081 ( .A0(n1207), .A1(n918), .B0(n848), .Y(n540) );
AOI22X1TS U1082 ( .A0(d_ff_Xn[25]), .A1(n854), .B0(sign_inv_out[25]), .B1(
n905), .Y(n849) );
OAI21XLTS U1083 ( .A0(n1212), .A1(n908), .B0(n849), .Y(n538) );
NOR2X1TS U1084 ( .A(sel_mux_1_reg), .B(n801), .Y(n872) );
CLKBUFX2TS U1085 ( .A(n872), .Y(n874) );
CLKBUFX3TS U1086 ( .A(n874), .Y(n902) );
AOI222X1TS U1087 ( .A0(n801), .A1(d_ff2_Z[31]), .B0(n902), .B1(d_ff1_Z[31]),
.C0(d_ff_Zn[31]), .C1(n901), .Y(n850) );
INVX2TS U1088 ( .A(n850), .Y(n465) );
AOI22X1TS U1089 ( .A0(d_ff_Xn[26]), .A1(n906), .B0(sign_inv_out[26]), .B1(
n905), .Y(n851) );
OAI21XLTS U1090 ( .A0(n1213), .A1(n918), .B0(n851), .Y(n536) );
AOI22X1TS U1091 ( .A0(d_ff_Xn[27]), .A1(n854), .B0(sign_inv_out[27]), .B1(
n905), .Y(n852) );
OAI21XLTS U1092 ( .A0(n1208), .A1(n908), .B0(n852), .Y(n534) );
AOI22X1TS U1093 ( .A0(d_ff_Xn[28]), .A1(n906), .B0(sign_inv_out[28]), .B1(
n905), .Y(n853) );
AOI22X1TS U1094 ( .A0(d_ff_Xn[29]), .A1(n854), .B0(sign_inv_out[29]), .B1(
n905), .Y(n855) );
OAI21XLTS U1095 ( .A0(n1210), .A1(n856), .B0(n855), .Y(n530) );
AOI22X1TS U1096 ( .A0(d_ff_Xn[30]), .A1(n906), .B0(sign_inv_out[30]), .B1(
n905), .Y(n857) );
OAI21XLTS U1097 ( .A0(n1219), .A1(n908), .B0(n857), .Y(n528) );
INVX2TS U1098 ( .A(n1090), .Y(n1067) );
CLKBUFX2TS U1099 ( .A(n874), .Y(n870) );
INVX2TS U1100 ( .A(n858), .Y(n496) );
INVX2TS U1101 ( .A(n1194), .Y(n1092) );
INVX2TS U1102 ( .A(n859), .Y(n495) );
INVX2TS U1103 ( .A(n860), .Y(n494) );
INVX2TS U1104 ( .A(n861), .Y(n493) );
INVX2TS U1105 ( .A(n862), .Y(n492) );
INVX2TS U1106 ( .A(n863), .Y(n491) );
INVX2TS U1107 ( .A(n864), .Y(n490) );
INVX2TS U1108 ( .A(n865), .Y(n489) );
INVX2TS U1109 ( .A(n866), .Y(n488) );
INVX2TS U1110 ( .A(n867), .Y(n487) );
NOR3X1TS U1111 ( .A(cont_iter_out[0]), .B(cont_iter_out[2]), .C(n1094), .Y(
n909) );
NAND3XLTS U1112 ( .A(cordic_FSM_state_reg[0]), .B(n1157), .C(n800), .Y(n869)
);
NAND3XLTS U1113 ( .A(n869), .B(sel_mux_1_reg), .C(n1287), .Y(n868) );
OAI21XLTS U1114 ( .A0(n909), .A1(n869), .B0(n868), .Y(n687) );
AOI222X1TS U1115 ( .A0(n882), .A1(d_ff2_Z[10]), .B0(n870), .B1(d_ff1_Z[10]),
.C0(d_ff_Zn[10]), .C1(n901), .Y(n871) );
INVX2TS U1116 ( .A(n871), .Y(n486) );
AOI222X1TS U1117 ( .A0(n882), .A1(d_ff2_Z[11]), .B0(n872), .B1(d_ff1_Z[11]),
.C0(d_ff_Zn[11]), .C1(n898), .Y(n873) );
INVX2TS U1118 ( .A(n873), .Y(n485) );
CLKBUFX3TS U1119 ( .A(n874), .Y(n885) );
AOI222X1TS U1120 ( .A0(n882), .A1(d_ff2_Z[12]), .B0(n885), .B1(d_ff1_Z[12]),
.C0(d_ff_Zn[12]), .C1(n898), .Y(n875) );
INVX2TS U1121 ( .A(n875), .Y(n484) );
AOI222X1TS U1122 ( .A0(n882), .A1(d_ff2_Z[13]), .B0(n885), .B1(d_ff1_Z[13]),
.C0(d_ff_Zn[13]), .C1(n898), .Y(n876) );
INVX2TS U1123 ( .A(n876), .Y(n483) );
AOI222X1TS U1124 ( .A0(n882), .A1(d_ff2_Z[14]), .B0(n885), .B1(d_ff1_Z[14]),
.C0(d_ff_Zn[14]), .C1(n901), .Y(n877) );
INVX2TS U1125 ( .A(n877), .Y(n482) );
AOI222X1TS U1126 ( .A0(n882), .A1(d_ff2_Z[15]), .B0(n885), .B1(d_ff1_Z[15]),
.C0(d_ff_Zn[15]), .C1(n898), .Y(n878) );
INVX2TS U1127 ( .A(n878), .Y(n481) );
AOI222X1TS U1128 ( .A0(n882), .A1(d_ff2_Z[16]), .B0(n885), .B1(d_ff1_Z[16]),
.C0(d_ff_Zn[16]), .C1(n898), .Y(n879) );
INVX2TS U1129 ( .A(n879), .Y(n480) );
AOI222X1TS U1130 ( .A0(n882), .A1(d_ff2_Z[17]), .B0(n885), .B1(d_ff1_Z[17]),
.C0(d_ff_Zn[17]), .C1(n901), .Y(n880) );
INVX2TS U1131 ( .A(n880), .Y(n479) );
AOI222X1TS U1132 ( .A0(n899), .A1(d_ff2_Z[18]), .B0(n885), .B1(d_ff1_Z[18]),
.C0(d_ff_Zn[18]), .C1(n901), .Y(n881) );
INVX2TS U1133 ( .A(n881), .Y(n478) );
AOI222X1TS U1134 ( .A0(n882), .A1(d_ff2_Z[19]), .B0(n885), .B1(d_ff1_Z[19]),
.C0(d_ff_Zn[19]), .C1(n901), .Y(n883) );
INVX2TS U1135 ( .A(n883), .Y(n477) );
AOI222X1TS U1136 ( .A0(n899), .A1(d_ff2_Z[20]), .B0(n885), .B1(d_ff1_Z[20]),
.C0(d_ff_Zn[20]), .C1(n901), .Y(n884) );
INVX2TS U1137 ( .A(n884), .Y(n476) );
INVX2TS U1138 ( .A(n886), .Y(n475) );
AOI222X1TS U1139 ( .A0(n899), .A1(d_ff2_Z[22]), .B0(n902), .B1(d_ff1_Z[22]),
.C0(d_ff_Zn[22]), .C1(n898), .Y(n887) );
INVX2TS U1140 ( .A(n887), .Y(n474) );
AOI222X1TS U1141 ( .A0(n801), .A1(d_ff2_Z[26]), .B0(n902), .B1(d_ff1_Z[26]),
.C0(d_ff_Zn[26]), .C1(n901), .Y(n888) );
INVX2TS U1142 ( .A(n888), .Y(n470) );
NAND3XLTS U1143 ( .A(cordic_FSM_state_reg[2]), .B(cordic_FSM_state_reg[0]),
.C(n1135), .Y(n1025) );
CLKBUFX2TS U1144 ( .A(n1025), .Y(n1096) );
CLKBUFX2TS U1145 ( .A(n1096), .Y(n1132) );
NAND2X1TS U1146 ( .A(n1189), .B(n1216), .Y(n1085) );
CLKBUFX2TS U1147 ( .A(n1096), .Y(n1101) );
CLKBUFX3TS U1148 ( .A(n1101), .Y(n1185) );
AOI22X1TS U1149 ( .A0(n1205), .A1(n1146), .B0(d_ff3_sh_x_out[23]), .B1(n1185), .Y(n889) );
OAI21XLTS U1150 ( .A0(n1259), .A1(n1085), .B0(n889), .Y(n345) );
INVX2TS U1151 ( .A(n1105), .Y(n1088) );
NAND2X1TS U1152 ( .A(cont_iter_out[3]), .B(n1088), .Y(n1083) );
CLKBUFX3TS U1153 ( .A(n1101), .Y(n1203) );
AOI32X1TS U1154 ( .A0(cont_iter_out[0]), .A1(n1205), .A2(n1188), .B0(
d_ff3_LUT_out[23]), .B1(n1203), .Y(n890) );
OAI21XLTS U1155 ( .A0(cont_iter_out[0]), .A1(n1083), .B0(n890), .Y(n501) );
AOI222X1TS U1156 ( .A0(n899), .A1(d_ff2_Z[23]), .B0(n902), .B1(d_ff1_Z[23]),
.C0(d_ff_Zn[23]), .C1(n894), .Y(n891) );
INVX2TS U1157 ( .A(n891), .Y(n473) );
AOI222X1TS U1158 ( .A0(n899), .A1(d_ff2_Z[24]), .B0(n902), .B1(d_ff1_Z[24]),
.C0(d_ff_Zn[24]), .C1(n894), .Y(n892) );
INVX2TS U1159 ( .A(n892), .Y(n472) );
AOI22X1TS U1160 ( .A0(n1205), .A1(n1125), .B0(d_ff3_sh_y_out[23]), .B1(n1185), .Y(n893) );
INVX2TS U1161 ( .A(n895), .Y(n471) );
AOI222X1TS U1162 ( .A0(n899), .A1(d_ff2_Z[27]), .B0(n902), .B1(d_ff1_Z[27]),
.C0(d_ff_Zn[27]), .C1(n898), .Y(n896) );
INVX2TS U1163 ( .A(n896), .Y(n469) );
AOI222X1TS U1164 ( .A0(n899), .A1(d_ff2_Z[28]), .B0(n902), .B1(d_ff1_Z[28]),
.C0(d_ff_Zn[28]), .C1(n898), .Y(n897) );
INVX2TS U1165 ( .A(n897), .Y(n468) );
AOI222X1TS U1166 ( .A0(n899), .A1(d_ff2_Z[29]), .B0(n902), .B1(d_ff1_Z[29]),
.C0(d_ff_Zn[29]), .C1(n898), .Y(n900) );
INVX2TS U1167 ( .A(n900), .Y(n467) );
AOI222X1TS U1168 ( .A0(n801), .A1(d_ff2_Z[30]), .B0(n902), .B1(d_ff1_Z[30]),
.C0(d_ff_Zn[30]), .C1(n901), .Y(n903) );
INVX2TS U1169 ( .A(n903), .Y(n466) );
INVX2TS U1170 ( .A(n1108), .Y(n1183) );
NAND2X2TS U1171 ( .A(n1183), .B(n1224), .Y(n1106) );
INVX2TS U1172 ( .A(n1106), .Y(n1131) );
AOI22X1TS U1173 ( .A0(d_ff3_LUT_out[25]), .A1(n1203), .B0(n1131), .B1(n1112),
.Y(n904) );
OAI21XLTS U1174 ( .A0(n1081), .A1(n1105), .B0(n904), .Y(n499) );
AOI22X1TS U1175 ( .A0(d_ff_Xn[31]), .A1(n906), .B0(data_output2_31_), .B1(
n905), .Y(n907) );
OAI21XLTS U1176 ( .A0(n1258), .A1(n908), .B0(n907), .Y(n526) );
NAND2X1TS U1177 ( .A(n1189), .B(n909), .Y(n1093) );
OAI21X1TS U1178 ( .A0(n1106), .A1(n1223), .B0(n1093), .Y(n1086) );
AOI21X1TS U1179 ( .A0(d_ff3_LUT_out[1]), .A1(n1185), .B0(n1086), .Y(n910) );
OAI21XLTS U1180 ( .A0(cont_iter_out[3]), .A1(n1105), .B0(n910), .Y(n523) );
NOR2X1TS U1181 ( .A(n1112), .B(n1106), .Y(n1082) );
AOI21X1TS U1182 ( .A0(d_ff3_LUT_out[2]), .A1(n1185), .B0(n1082), .Y(n911) );
OAI21XLTS U1183 ( .A0(n1094), .A1(n1105), .B0(n911), .Y(n522) );
OAI211XLTS U1184 ( .A0(cont_iter_out[0]), .A1(cont_iter_out[3]), .B0(
cont_iter_out[1]), .C0(n1224), .Y(n912) );
OAI21X1TS U1185 ( .A0(cont_iter_out[0]), .A1(n1094), .B0(n912), .Y(n1181) );
AOI22X1TS U1186 ( .A0(n1205), .A1(n1181), .B0(d_ff3_LUT_out[6]), .B1(n1203),
.Y(n913) );
OAI31X1TS U1187 ( .A0(n1216), .A1(n1223), .A2(n1106), .B0(n913), .Y(n518) );
NAND3XLTS U1188 ( .A(n1157), .B(cordic_FSM_state_reg[3]), .C(n1225), .Y(n915) );
NAND3XLTS U1189 ( .A(n915), .B(sel_mux_3_reg), .C(n1290), .Y(n914) );
OAI21XLTS U1190 ( .A0(n916), .A1(n915), .B0(n914), .Y(n688) );
NAND3X1TS U1191 ( .A(cordic_FSM_state_reg[2]), .B(cordic_FSM_state_reg[1]),
.C(n1044), .Y(n1170) );
INVX2TS U1192 ( .A(n1170), .Y(n1173) );
NAND2X1TS U1193 ( .A(sel_mux_2_reg[1]), .B(n1289), .Y(n917) );
OAI32X1TS U1194 ( .A0(n1170), .A1(n1159), .A2(n1218), .B0(n1173), .B1(n917),
.Y(n685) );
CLKBUFX3TS U1195 ( .A(n918), .Y(n932) );
CLKBUFX3TS U1196 ( .A(n919), .Y(n930) );
AOI22X1TS U1197 ( .A0(d_ff_Xn[0]), .A1(n930), .B0(sign_inv_out[0]), .B1(n928), .Y(n920) );
OAI21XLTS U1198 ( .A0(n1238), .A1(n932), .B0(n920), .Y(n588) );
AOI22X1TS U1199 ( .A0(d_ff_Xn[1]), .A1(n930), .B0(sign_inv_out[1]), .B1(n937), .Y(n921) );
OAI21XLTS U1200 ( .A0(n1239), .A1(n932), .B0(n921), .Y(n586) );
AOI22X1TS U1201 ( .A0(d_ff_Xn[2]), .A1(n930), .B0(sign_inv_out[2]), .B1(n937), .Y(n922) );
OAI21XLTS U1202 ( .A0(n1240), .A1(n932), .B0(n922), .Y(n584) );
AOI22X1TS U1203 ( .A0(d_ff_Xn[3]), .A1(n930), .B0(sign_inv_out[3]), .B1(n928), .Y(n923) );
OAI21XLTS U1204 ( .A0(n1241), .A1(n932), .B0(n923), .Y(n582) );
AOI22X1TS U1205 ( .A0(d_ff_Xn[4]), .A1(n930), .B0(sign_inv_out[4]), .B1(n928), .Y(n924) );
OAI21XLTS U1206 ( .A0(n1242), .A1(n932), .B0(n924), .Y(n580) );
AOI22X1TS U1207 ( .A0(d_ff_Xn[5]), .A1(n930), .B0(sign_inv_out[5]), .B1(n928), .Y(n925) );
OAI21XLTS U1208 ( .A0(n1243), .A1(n932), .B0(n925), .Y(n578) );
AOI22X1TS U1209 ( .A0(d_ff_Xn[6]), .A1(n930), .B0(sign_inv_out[6]), .B1(n928), .Y(n926) );
OAI21XLTS U1210 ( .A0(n1244), .A1(n932), .B0(n926), .Y(n576) );
AOI22X1TS U1211 ( .A0(d_ff_Xn[7]), .A1(n930), .B0(sign_inv_out[7]), .B1(n928), .Y(n927) );
OAI21XLTS U1212 ( .A0(n1245), .A1(n932), .B0(n927), .Y(n574) );
AOI22X1TS U1213 ( .A0(d_ff_Xn[8]), .A1(n930), .B0(sign_inv_out[8]), .B1(n928), .Y(n929) );
OAI21XLTS U1214 ( .A0(n1246), .A1(n932), .B0(n929), .Y(n572) );
AOI22X1TS U1215 ( .A0(d_ff_Xn[9]), .A1(n930), .B0(sign_inv_out[9]), .B1(n937), .Y(n931) );
OAI21XLTS U1216 ( .A0(n1247), .A1(n932), .B0(n931), .Y(n570) );
AOI22X1TS U1217 ( .A0(d_ff_Xn[10]), .A1(n942), .B0(sign_inv_out[10]), .B1(
n937), .Y(n933) );
OAI21XLTS U1218 ( .A0(n1248), .A1(n944), .B0(n933), .Y(n568) );
AOI22X1TS U1219 ( .A0(d_ff_Xn[17]), .A1(n942), .B0(sign_inv_out[17]), .B1(
n941), .Y(n934) );
OAI21XLTS U1220 ( .A0(n1255), .A1(n944), .B0(n934), .Y(n554) );
AOI22X1TS U1221 ( .A0(d_ff_Xn[14]), .A1(n942), .B0(sign_inv_out[14]), .B1(
n941), .Y(n935) );
OAI21XLTS U1222 ( .A0(n1252), .A1(n944), .B0(n935), .Y(n560) );
AOI22X1TS U1223 ( .A0(d_ff_Xn[15]), .A1(n942), .B0(sign_inv_out[15]), .B1(
n941), .Y(n936) );
OAI21XLTS U1224 ( .A0(n1253), .A1(n944), .B0(n936), .Y(n558) );
AOI22X1TS U1225 ( .A0(d_ff_Xn[11]), .A1(n942), .B0(sign_inv_out[11]), .B1(
n937), .Y(n938) );
OAI21XLTS U1226 ( .A0(n1249), .A1(n944), .B0(n938), .Y(n566) );
AOI22X1TS U1227 ( .A0(d_ff_Xn[12]), .A1(n942), .B0(sign_inv_out[12]), .B1(
n941), .Y(n939) );
OAI21XLTS U1228 ( .A0(n1250), .A1(n944), .B0(n939), .Y(n564) );
AOI22X1TS U1229 ( .A0(d_ff_Xn[16]), .A1(n942), .B0(sign_inv_out[16]), .B1(
n941), .Y(n940) );
OAI21XLTS U1230 ( .A0(n1254), .A1(n944), .B0(n940), .Y(n556) );
AOI22X1TS U1231 ( .A0(d_ff_Xn[13]), .A1(n942), .B0(sign_inv_out[13]), .B1(
n941), .Y(n943) );
NAND4XLTS U1232 ( .A(n799), .B(cordic_FSM_state_reg[1]), .C(
cordic_FSM_state_reg[2]), .D(cordic_FSM_state_reg[0]), .Y(n1160) );
INVX2TS U1233 ( .A(n1160), .Y(beg_add_subt) );
AOI22X1TS U1234 ( .A0(d_ff2_Z[30]), .A1(n1010), .B0(d_ff2_X[30]), .B1(n1153),
.Y(n945) );
OAI21XLTS U1235 ( .A0(n1232), .A1(n998), .B0(n945), .Y(add_subt_dataA[30])
);
AOI22X1TS U1236 ( .A0(d_ff2_Z[29]), .A1(n983), .B0(d_ff2_X[29]), .B1(n1153),
.Y(n946) );
OAI21XLTS U1237 ( .A0(n1234), .A1(n985), .B0(n946), .Y(add_subt_dataA[29])
);
INVX2TS U1238 ( .A(n998), .Y(n996) );
CLKBUFX3TS U1239 ( .A(n1003), .Y(n1021) );
AOI222X1TS U1240 ( .A0(d_ff2_Z[31]), .A1(n837), .B0(d_ff2_Y[31]), .B1(n1154),
.C0(d_ff2_X[31]), .C1(n1021), .Y(n947) );
INVX2TS U1241 ( .A(n947), .Y(add_subt_dataA[31]) );
AOI22X1TS U1242 ( .A0(d_ff2_Z[27]), .A1(n1010), .B0(d_ff2_X[27]), .B1(n1153),
.Y(n948) );
OAI21XLTS U1243 ( .A0(n1233), .A1(n985), .B0(n948), .Y(add_subt_dataA[27])
);
CLKBUFX3TS U1244 ( .A(n1010), .Y(n1005) );
INVX2TS U1245 ( .A(n998), .Y(n975) );
AOI222X1TS U1246 ( .A0(d_ff2_Z[26]), .A1(n1005), .B0(d_ff2_Y[26]), .B1(n1154), .C0(d_ff2_X[26]), .C1(n1021), .Y(n949) );
INVX2TS U1247 ( .A(n949), .Y(add_subt_dataA[26]) );
AOI22X1TS U1248 ( .A0(d_ff2_X[24]), .A1(n1153), .B0(d_ff2_Z[24]), .B1(n983),
.Y(n950) );
OAI21XLTS U1249 ( .A0(n1226), .A1(n985), .B0(n950), .Y(add_subt_dataA[24])
);
AOI22X1TS U1250 ( .A0(d_ff2_X[23]), .A1(n1153), .B0(d_ff2_Z[23]), .B1(n1010),
.Y(n951) );
CLKBUFX3TS U1251 ( .A(n979), .Y(n964) );
AOI222X1TS U1252 ( .A0(d_ff2_Z[22]), .A1(n988), .B0(d_ff2_Y[22]), .B1(n973),
.C0(d_ff2_X[22]), .C1(n964), .Y(n952) );
INVX2TS U1253 ( .A(n952), .Y(add_subt_dataA[22]) );
AOI222X1TS U1254 ( .A0(d_ff2_Z[21]), .A1(n1005), .B0(d_ff2_Y[21]), .B1(n973),
.C0(d_ff2_X[21]), .C1(n964), .Y(n953) );
INVX2TS U1255 ( .A(n953), .Y(add_subt_dataA[21]) );
AOI22X1TS U1256 ( .A0(d_ff2_Z[28]), .A1(n1010), .B0(d_ff2_X[28]), .B1(n1153),
.Y(n954) );
CLKBUFX3TS U1257 ( .A(n983), .Y(n967) );
AOI222X1TS U1258 ( .A0(d_ff2_Z[19]), .A1(n967), .B0(d_ff2_Y[19]), .B1(n1151),
.C0(d_ff2_X[19]), .C1(n964), .Y(n955) );
INVX2TS U1259 ( .A(n955), .Y(add_subt_dataA[19]) );
AOI222X1TS U1260 ( .A0(d_ff2_Z[18]), .A1(n967), .B0(d_ff2_Y[18]), .B1(n975),
.C0(d_ff2_X[18]), .C1(n964), .Y(n956) );
INVX2TS U1261 ( .A(n956), .Y(add_subt_dataA[18]) );
AOI222X1TS U1262 ( .A0(d_ff2_Z[17]), .A1(n967), .B0(d_ff2_Y[17]), .B1(n1012),
.C0(d_ff2_X[17]), .C1(n964), .Y(n957) );
INVX2TS U1263 ( .A(n957), .Y(add_subt_dataA[17]) );
AOI222X1TS U1264 ( .A0(d_ff2_Z[16]), .A1(n967), .B0(d_ff2_Y[16]), .B1(n1154),
.C0(d_ff2_X[16]), .C1(n964), .Y(n958) );
INVX2TS U1265 ( .A(n958), .Y(add_subt_dataA[16]) );
AOI222X1TS U1266 ( .A0(d_ff2_Z[15]), .A1(n967), .B0(d_ff2_Y[15]), .B1(n973),
.C0(d_ff2_X[15]), .C1(n964), .Y(n959) );
INVX2TS U1267 ( .A(n959), .Y(add_subt_dataA[15]) );
AOI222X1TS U1268 ( .A0(d_ff2_Z[14]), .A1(n967), .B0(d_ff2_Y[14]), .B1(n1151),
.C0(d_ff2_X[14]), .C1(n964), .Y(n960) );
INVX2TS U1269 ( .A(n960), .Y(add_subt_dataA[14]) );
INVX2TS U1270 ( .A(n998), .Y(n973) );
AOI222X1TS U1271 ( .A0(d_ff2_Z[13]), .A1(n967), .B0(d_ff2_Y[13]), .B1(n1154),
.C0(d_ff2_X[13]), .C1(n964), .Y(n961) );
INVX2TS U1272 ( .A(n961), .Y(add_subt_dataA[13]) );
AOI222X1TS U1273 ( .A0(d_ff2_Z[12]), .A1(n967), .B0(d_ff2_Y[12]), .B1(n973),
.C0(d_ff2_X[12]), .C1(n1003), .Y(n962) );
INVX2TS U1274 ( .A(n962), .Y(add_subt_dataA[12]) );
AOI222X1TS U1275 ( .A0(d_ff2_Z[11]), .A1(n967), .B0(d_ff2_Y[11]), .B1(n1151),
.C0(d_ff2_X[11]), .C1(n1152), .Y(n963) );
INVX2TS U1276 ( .A(n963), .Y(add_subt_dataA[11]) );
AOI222X1TS U1277 ( .A0(d_ff2_Z[10]), .A1(n988), .B0(d_ff2_Y[10]), .B1(n975),
.C0(d_ff2_X[10]), .C1(n964), .Y(n965) );
INVX2TS U1278 ( .A(n965), .Y(add_subt_dataA[10]) );
AOI222X1TS U1279 ( .A0(d_ff2_Z[9]), .A1(n980), .B0(d_ff2_Y[9]), .B1(n1012),
.C0(d_ff2_X[9]), .C1(n1003), .Y(n966) );
INVX2TS U1280 ( .A(n966), .Y(add_subt_dataA[9]) );
AOI222X1TS U1281 ( .A0(d_ff2_Z[8]), .A1(n967), .B0(d_ff2_Y[8]), .B1(n1154),
.C0(d_ff2_X[8]), .C1(n1003), .Y(n968) );
INVX2TS U1282 ( .A(n968), .Y(add_subt_dataA[8]) );
AOI222X1TS U1283 ( .A0(d_ff2_Z[7]), .A1(n988), .B0(d_ff2_Y[7]), .B1(n975),
.C0(d_ff2_X[7]), .C1(n1152), .Y(n969) );
INVX2TS U1284 ( .A(n969), .Y(add_subt_dataA[7]) );
AOI222X1TS U1285 ( .A0(d_ff2_Z[6]), .A1(n988), .B0(d_ff2_Y[6]), .B1(n973),
.C0(d_ff2_X[6]), .C1(n979), .Y(n970) );
INVX2TS U1286 ( .A(n970), .Y(add_subt_dataA[6]) );
AOI222X1TS U1287 ( .A0(d_ff2_Z[5]), .A1(n980), .B0(d_ff2_Y[5]), .B1(n1151),
.C0(d_ff2_X[5]), .C1(n979), .Y(n971) );
INVX2TS U1288 ( .A(n971), .Y(add_subt_dataA[5]) );
AOI222X1TS U1289 ( .A0(d_ff2_Z[4]), .A1(n980), .B0(d_ff2_Y[4]), .B1(n975),
.C0(d_ff2_X[4]), .C1(n1003), .Y(n972) );
INVX2TS U1290 ( .A(n972), .Y(add_subt_dataA[4]) );
AOI222X1TS U1291 ( .A0(d_ff2_Z[3]), .A1(n980), .B0(d_ff2_Y[3]), .B1(n1012),
.C0(d_ff2_X[3]), .C1(n979), .Y(n974) );
INVX2TS U1292 ( .A(n974), .Y(add_subt_dataA[3]) );
AOI222X1TS U1293 ( .A0(d_ff2_Z[20]), .A1(n1005), .B0(d_ff2_Y[20]), .B1(n1012), .C0(d_ff2_X[20]), .C1(n1021), .Y(n976) );
INVX2TS U1294 ( .A(n976), .Y(add_subt_dataA[20]) );
INVX2TS U1295 ( .A(n998), .Y(n1151) );
AOI222X1TS U1296 ( .A0(d_ff2_Z[1]), .A1(n988), .B0(d_ff2_Y[1]), .B1(n975),
.C0(d_ff2_X[1]), .C1(n1152), .Y(n977) );
INVX2TS U1297 ( .A(n977), .Y(add_subt_dataA[1]) );
AOI222X1TS U1298 ( .A0(d_ff2_Z[0]), .A1(n1005), .B0(d_ff2_Y[0]), .B1(n1151),
.C0(d_ff2_X[0]), .C1(n1021), .Y(n978) );
INVX2TS U1299 ( .A(n978), .Y(add_subt_dataA[0]) );
AOI222X1TS U1300 ( .A0(d_ff2_Z[2]), .A1(n980), .B0(d_ff2_Y[2]), .B1(n1012),
.C0(d_ff2_X[2]), .C1(n979), .Y(n981) );
INVX2TS U1301 ( .A(n981), .Y(add_subt_dataA[2]) );
AOI22X1TS U1302 ( .A0(d_ff3_sh_y_out[29]), .A1(n1153), .B0(d_ff3_LUT_out[27]), .B1(n983), .Y(n982) );
OAI21XLTS U1303 ( .A0(n1236), .A1(n985), .B0(n982), .Y(add_subt_dataB[29])
);
AOI22X1TS U1304 ( .A0(d_ff3_sh_y_out[28]), .A1(n1153), .B0(d_ff3_LUT_out[27]), .B1(n983), .Y(n984) );
CLKBUFX3TS U1305 ( .A(n986), .Y(n1001) );
AOI222X1TS U1306 ( .A0(d_ff3_LUT_out[26]), .A1(n1005), .B0(n996), .B1(
d_ff3_sh_x_out[26]), .C0(n1001), .C1(d_ff3_sh_y_out[26]), .Y(n987) );
INVX2TS U1307 ( .A(n987), .Y(add_subt_dataB[26]) );
AOI222X1TS U1308 ( .A0(d_ff3_sh_x_out[25]), .A1(n1012), .B0(
d_ff3_LUT_out[25]), .B1(n988), .C0(n1001), .C1(d_ff3_sh_y_out[25]),
.Y(n989) );
INVX2TS U1309 ( .A(n989), .Y(add_subt_dataB[25]) );
INVX2TS U1310 ( .A(n990), .Y(add_subt_dataB[24]) );
AOI222X1TS U1311 ( .A0(d_ff3_LUT_out[23]), .A1(n1005), .B0(
d_ff3_sh_y_out[23]), .B1(n1021), .C0(d_ff3_sh_x_out[23]), .C1(n996),
.Y(n991) );
INVX2TS U1312 ( .A(n991), .Y(add_subt_dataB[23]) );
AOI222X1TS U1313 ( .A0(n1010), .A1(d_ff3_LUT_out[22]), .B0(n996), .B1(
d_ff3_sh_x_out[22]), .C0(n1001), .C1(d_ff3_sh_y_out[22]), .Y(n992) );
INVX2TS U1314 ( .A(n992), .Y(add_subt_dataB[22]) );
AOI222X1TS U1315 ( .A0(d_ff3_LUT_out[21]), .A1(n1005), .B0(n996), .B1(
d_ff3_sh_x_out[21]), .C0(n1001), .C1(d_ff3_sh_y_out[21]), .Y(n993) );
INVX2TS U1316 ( .A(n993), .Y(add_subt_dataB[21]) );
AOI222X1TS U1317 ( .A0(d_ff3_LUT_out[20]), .A1(n1005), .B0(n996), .B1(
d_ff3_sh_x_out[20]), .C0(n1001), .C1(d_ff3_sh_y_out[20]), .Y(n994) );
INVX2TS U1318 ( .A(n994), .Y(add_subt_dataB[20]) );
AOI222X1TS U1319 ( .A0(n1010), .A1(d_ff3_LUT_out[19]), .B0(n996), .B1(
d_ff3_sh_x_out[19]), .C0(n1001), .C1(d_ff3_sh_y_out[19]), .Y(n995) );
INVX2TS U1320 ( .A(n995), .Y(add_subt_dataB[19]) );
AOI222X1TS U1321 ( .A0(d_ff3_LUT_out[18]), .A1(n980), .B0(n996), .B1(
d_ff3_sh_x_out[18]), .C0(n1001), .C1(d_ff3_sh_y_out[18]), .Y(n997) );
INVX2TS U1322 ( .A(n997), .Y(add_subt_dataB[18]) );
AOI222X1TS U1323 ( .A0(d_ff3_LUT_out[17]), .A1(n988), .B0(n1012), .B1(
d_ff3_sh_x_out[17]), .C0(n1001), .C1(d_ff3_sh_y_out[17]), .Y(n999) );
INVX2TS U1324 ( .A(n999), .Y(add_subt_dataB[17]) );
AOI222X1TS U1325 ( .A0(d_ff3_LUT_out[16]), .A1(n988), .B0(n1154), .B1(
d_ff3_sh_x_out[16]), .C0(n1001), .C1(d_ff3_sh_y_out[16]), .Y(n1000) );
INVX2TS U1326 ( .A(n1000), .Y(add_subt_dataB[16]) );
AOI222X1TS U1327 ( .A0(d_ff3_LUT_out[15]), .A1(n1010), .B0(n973), .B1(
d_ff3_sh_x_out[15]), .C0(n1001), .C1(d_ff3_sh_y_out[15]), .Y(n1002) );
INVX2TS U1328 ( .A(n1002), .Y(add_subt_dataB[15]) );
CLKBUFX3TS U1329 ( .A(n1003), .Y(n1017) );
AOI222X1TS U1330 ( .A0(d_ff3_LUT_out[14]), .A1(n983), .B0(n1151), .B1(
d_ff3_sh_x_out[14]), .C0(n1017), .C1(d_ff3_sh_y_out[14]), .Y(n1004) );
INVX2TS U1331 ( .A(n1004), .Y(add_subt_dataB[14]) );
AOI222X1TS U1332 ( .A0(d_ff3_LUT_out[13]), .A1(n1005), .B0(n975), .B1(
d_ff3_sh_x_out[13]), .C0(n1021), .C1(d_ff3_sh_y_out[13]), .Y(n1006) );
INVX2TS U1333 ( .A(n1006), .Y(add_subt_dataB[13]) );
AOI222X1TS U1334 ( .A0(d_ff3_LUT_out[11]), .A1(n980), .B0(n1012), .B1(
d_ff3_sh_x_out[11]), .C0(n1017), .C1(d_ff3_sh_y_out[11]), .Y(n1007) );
INVX2TS U1335 ( .A(n1007), .Y(add_subt_dataB[11]) );
AOI222X1TS U1336 ( .A0(d_ff3_LUT_out[10]), .A1(n988), .B0(n1154), .B1(
d_ff3_sh_x_out[10]), .C0(n1017), .C1(d_ff3_sh_y_out[10]), .Y(n1008) );
INVX2TS U1337 ( .A(n1008), .Y(add_subt_dataB[10]) );
AOI222X1TS U1338 ( .A0(d_ff3_LUT_out[9]), .A1(n1010), .B0(n973), .B1(
d_ff3_sh_x_out[9]), .C0(n1017), .C1(d_ff3_sh_y_out[9]), .Y(n1009) );
INVX2TS U1339 ( .A(n1009), .Y(add_subt_dataB[9]) );
INVX2TS U1340 ( .A(n1011), .Y(add_subt_dataB[8]) );
AOI222X1TS U1341 ( .A0(d_ff3_LUT_out[7]), .A1(n837), .B0(n975), .B1(
d_ff3_sh_x_out[7]), .C0(n1017), .C1(d_ff3_sh_y_out[7]), .Y(n1013) );
INVX2TS U1342 ( .A(n1013), .Y(add_subt_dataB[7]) );
AOI222X1TS U1343 ( .A0(d_ff3_LUT_out[6]), .A1(n837), .B0(n996), .B1(
d_ff3_sh_x_out[6]), .C0(n1017), .C1(d_ff3_sh_y_out[6]), .Y(n1014) );
INVX2TS U1344 ( .A(n1014), .Y(add_subt_dataB[6]) );
AOI222X1TS U1345 ( .A0(d_ff3_LUT_out[5]), .A1(n837), .B0(n996), .B1(
d_ff3_sh_x_out[5]), .C0(n1017), .C1(d_ff3_sh_y_out[5]), .Y(n1015) );
INVX2TS U1346 ( .A(n1015), .Y(add_subt_dataB[5]) );
AOI222X1TS U1347 ( .A0(d_ff3_LUT_out[4]), .A1(n837), .B0(n1154), .B1(
d_ff3_sh_x_out[4]), .C0(n1017), .C1(d_ff3_sh_y_out[4]), .Y(n1016) );
INVX2TS U1348 ( .A(n1016), .Y(add_subt_dataB[4]) );
AOI222X1TS U1349 ( .A0(d_ff3_LUT_out[3]), .A1(n980), .B0(n1012), .B1(
d_ff3_sh_x_out[3]), .C0(n1017), .C1(d_ff3_sh_y_out[3]), .Y(n1018) );
INVX2TS U1350 ( .A(n1018), .Y(add_subt_dataB[3]) );
AOI222X1TS U1351 ( .A0(d_ff3_LUT_out[2]), .A1(n837), .B0(n973), .B1(
d_ff3_sh_x_out[2]), .C0(n1021), .C1(d_ff3_sh_y_out[2]), .Y(n1019) );
INVX2TS U1352 ( .A(n1019), .Y(add_subt_dataB[2]) );
AOI222X1TS U1353 ( .A0(d_ff3_LUT_out[1]), .A1(n837), .B0(n1151), .B1(
d_ff3_sh_x_out[1]), .C0(n1021), .C1(d_ff3_sh_y_out[1]), .Y(n1020) );
INVX2TS U1354 ( .A(n1020), .Y(add_subt_dataB[1]) );
AOI222X1TS U1355 ( .A0(d_ff3_LUT_out[0]), .A1(n837), .B0(n975), .B1(
d_ff3_sh_x_out[0]), .C0(n1021), .C1(d_ff3_sh_y_out[0]), .Y(n1022) );
INVX2TS U1356 ( .A(n1022), .Y(add_subt_dataB[0]) );
INVX2TS U1357 ( .A(n1132), .Y(n1128) );
NAND2X1TS U1358 ( .A(d_ff2_Y[24]), .B(n1217), .Y(n1023) );
AOI22X1TS U1359 ( .A0(cont_iter_out[1]), .A1(n1226), .B0(n1125), .B1(n1023),
.Y(n1029) );
CLKBUFX3TS U1360 ( .A(n1101), .Y(n1126) );
AO22XLTS U1361 ( .A0(n1128), .A1(n1024), .B0(n1126), .B1(d_ff3_sh_y_out[25]),
.Y(n407) );
CLKBUFX2TS U1362 ( .A(n1025), .Y(n1098) );
INVX2TS U1363 ( .A(n1098), .Y(n1072) );
CLKBUFX3TS U1364 ( .A(n1096), .Y(n1071) );
AO22XLTS U1365 ( .A0(n1072), .A1(d_ff2_X[15]), .B0(n1071), .B1(
d_ff3_sh_x_out[15]), .Y(n368) );
AO22XLTS U1366 ( .A0(n1072), .A1(d_ff2_X[20]), .B0(n1071), .B1(
d_ff3_sh_x_out[20]), .Y(n358) );
INVX2TS U1367 ( .A(n1068), .Y(n1070) );
AO22XLTS U1368 ( .A0(n1070), .A1(sign_inv_out[15]), .B0(n1062), .B1(
data_output[15]), .Y(n557) );
INVX2TS U1369 ( .A(n1132), .Y(n1111) );
AO22XLTS U1370 ( .A0(n1111), .A1(d_ff2_Y[0]), .B0(n1096), .B1(
d_ff3_sh_y_out[0]), .Y(n462) );
INVX2TS U1371 ( .A(n1050), .Y(n1041) );
AO22XLTS U1372 ( .A0(n1050), .A1(data_in[1]), .B0(n1041), .B1(d_ff1_Z[1]),
.Y(n719) );
AO22XLTS U1373 ( .A0(n1070), .A1(sign_inv_out[16]), .B0(n1062), .B1(
data_output[16]), .Y(n555) );
INVX2TS U1374 ( .A(n1132), .Y(n1069) );
AO22XLTS U1375 ( .A0(n1069), .A1(d_ff2_X[22]), .B0(n1071), .B1(
d_ff3_sh_x_out[22]), .Y(n354) );
INVX2TS U1376 ( .A(n1098), .Y(n1148) );
AO22XLTS U1377 ( .A0(n1148), .A1(d_ff2_X[17]), .B0(n1071), .B1(
d_ff3_sh_x_out[17]), .Y(n364) );
INVX2TS U1378 ( .A(n1098), .Y(n1119) );
AO22XLTS U1379 ( .A0(n1119), .A1(d_ff2_X[16]), .B0(n1071), .B1(
d_ff3_sh_x_out[16]), .Y(n366) );
AO22XLTS U1380 ( .A0(n1148), .A1(d_ff2_X[21]), .B0(n1071), .B1(
d_ff3_sh_x_out[21]), .Y(n356) );
INVX2TS U1381 ( .A(n1028), .Y(n1036) );
CLKBUFX2TS U1382 ( .A(n1036), .Y(n1032) );
AO22XLTS U1383 ( .A0(n1028), .A1(result_add_subt[2]), .B0(n1032), .B1(
d_ff_Zn[2]), .Y(n682) );
AO22XLTS U1384 ( .A0(n1072), .A1(d_ff2_X[18]), .B0(n1071), .B1(
d_ff3_sh_x_out[18]), .Y(n362) );
AO22XLTS U1385 ( .A0(n1143), .A1(result_add_subt[3]), .B0(n1032), .B1(
d_ff_Zn[3]), .Y(n681) );
AO22XLTS U1386 ( .A0(n1070), .A1(sign_inv_out[17]), .B0(n1062), .B1(
data_output[17]), .Y(n553) );
CMPR32X2TS U1387 ( .A(d_ff2_Y[25]), .B(n1224), .C(n1029), .CO(n1033), .S(
n1024) );
AO22XLTS U1388 ( .A0(n1128), .A1(n1030), .B0(n1126), .B1(d_ff3_sh_y_out[26]),
.Y(n406) );
AO22XLTS U1389 ( .A0(n1072), .A1(d_ff2_X[19]), .B0(n1071), .B1(
d_ff3_sh_x_out[19]), .Y(n360) );
NAND2X1TS U1390 ( .A(d_ff2_X[24]), .B(n1217), .Y(n1144) );
OR3X1TS U1391 ( .A(d_ff2_X[28]), .B(d_ff2_X[27]), .C(n1076), .Y(n1202) );
OAI21XLTS U1392 ( .A0(d_ff2_X[27]), .A1(n1076), .B0(d_ff2_X[28]), .Y(n1031)
);
AOI32X1TS U1393 ( .A0(n1202), .A1(n1205), .A2(n1031), .B0(n1237), .B1(n1203),
.Y(n340) );
AO22XLTS U1394 ( .A0(n1143), .A1(result_add_subt[1]), .B0(n1032), .B1(
d_ff_Zn[1]), .Y(n683) );
AO22XLTS U1395 ( .A0(n1143), .A1(result_add_subt[4]), .B0(n1032), .B1(
d_ff_Zn[4]), .Y(n680) );
CLKBUFX3TS U1396 ( .A(n1062), .Y(n1040) );
AO22XLTS U1397 ( .A0(n1070), .A1(sign_inv_out[18]), .B0(n1040), .B1(
data_output[18]), .Y(n551) );
AO22XLTS U1398 ( .A0(n1072), .A1(d_ff2_X[14]), .B0(n1071), .B1(
d_ff3_sh_x_out[14]), .Y(n370) );
AO22XLTS U1399 ( .A0(n1069), .A1(d_ff2_Y[1]), .B0(n1108), .B1(
d_ff3_sh_y_out[1]), .Y(n460) );
AO22XLTS U1400 ( .A0(n1143), .A1(result_add_subt[5]), .B0(n1032), .B1(
d_ff_Zn[5]), .Y(n679) );
AO22XLTS U1401 ( .A0(n1143), .A1(result_add_subt[6]), .B0(n1032), .B1(
d_ff_Zn[6]), .Y(n678) );
AO22XLTS U1402 ( .A0(n1143), .A1(result_add_subt[7]), .B0(n1032), .B1(
d_ff_Zn[7]), .Y(n677) );
AO22XLTS U1403 ( .A0(n1070), .A1(sign_inv_out[19]), .B0(n1040), .B1(
data_output[19]), .Y(n549) );
CMPR32X2TS U1404 ( .A(d_ff2_Y[26]), .B(n1223), .C(n1033), .CO(n1118), .S(
n1030) );
OR3X1TS U1405 ( .A(n1118), .B(d_ff2_Y[28]), .C(d_ff2_Y[27]), .Y(n1079) );
NOR2X1TS U1406 ( .A(d_ff2_Y[29]), .B(n1079), .Y(n1078) );
XOR2XLTS U1407 ( .A(d_ff2_Y[30]), .B(n1078), .Y(n1034) );
AO22XLTS U1408 ( .A0(n1128), .A1(n1034), .B0(n1126), .B1(d_ff3_sh_y_out[30]),
.Y(n402) );
CLKBUFX2TS U1409 ( .A(n1036), .Y(n1142) );
AO22XLTS U1410 ( .A0(n1143), .A1(result_add_subt[8]), .B0(n1142), .B1(
d_ff_Zn[8]), .Y(n676) );
CLKBUFX2TS U1411 ( .A(n1036), .Y(n1140) );
AO22XLTS U1412 ( .A0(n1143), .A1(result_add_subt[9]), .B0(n1140), .B1(
d_ff_Zn[9]), .Y(n675) );
INVX2TS U1413 ( .A(n1140), .Y(n1037) );
AO22XLTS U1414 ( .A0(n1037), .A1(result_add_subt[10]), .B0(n1036), .B1(
d_ff_Zn[10]), .Y(n674) );
NOR2X1TS U1415 ( .A(d_ff2_X[29]), .B(n1202), .Y(n1201) );
XOR2XLTS U1416 ( .A(d_ff2_X[30]), .B(n1201), .Y(n1035) );
AO22XLTS U1417 ( .A0(n1069), .A1(n1035), .B0(n1132), .B1(d_ff3_sh_x_out[30]),
.Y(n338) );
AO22XLTS U1418 ( .A0(n803), .A1(sign_inv_out[20]), .B0(n1040), .B1(
data_output[20]), .Y(n547) );
AO22XLTS U1419 ( .A0(n1037), .A1(result_add_subt[11]), .B0(n1142), .B1(
d_ff_Zn[11]), .Y(n673) );
AO22XLTS U1420 ( .A0(n1037), .A1(result_add_subt[12]), .B0(n1140), .B1(
d_ff_Zn[12]), .Y(n672) );
CLKBUFX3TS U1421 ( .A(n1101), .Y(n1051) );
AO22XLTS U1422 ( .A0(n1111), .A1(d_ff2_X[31]), .B0(n1051), .B1(
d_ff3_sh_x_out[31]), .Y(n336) );
AO22XLTS U1423 ( .A0(n1037), .A1(result_add_subt[13]), .B0(n1140), .B1(
d_ff_Zn[13]), .Y(n671) );
AO22XLTS U1424 ( .A0(n1038), .A1(sign_inv_out[21]), .B0(n1040), .B1(
data_output[21]), .Y(n545) );
AO22XLTS U1425 ( .A0(n1037), .A1(result_add_subt[14]), .B0(n1142), .B1(
d_ff_Zn[14]), .Y(n670) );
AO22XLTS U1426 ( .A0(n1128), .A1(d_ff2_Y[31]), .B0(n1126), .B1(
d_ff3_sh_y_out[31]), .Y(n400) );
AO22XLTS U1427 ( .A0(n1037), .A1(result_add_subt[15]), .B0(n1036), .B1(
d_ff_Zn[15]), .Y(n669) );
AO22XLTS U1428 ( .A0(n1037), .A1(result_add_subt[16]), .B0(n1036), .B1(
d_ff_Zn[16]), .Y(n668) );
AO22XLTS U1429 ( .A0(n1037), .A1(result_add_subt[17]), .B0(n1036), .B1(
d_ff_Zn[17]), .Y(n667) );
AO22XLTS U1430 ( .A0(n803), .A1(sign_inv_out[22]), .B0(n1040), .B1(
data_output[22]), .Y(n543) );
CLKBUFX3TS U1431 ( .A(n1036), .Y(n1039) );
AO22XLTS U1432 ( .A0(n1037), .A1(result_add_subt[18]), .B0(n1039), .B1(
d_ff_Zn[18]), .Y(n666) );
AO22XLTS U1433 ( .A0(n1037), .A1(result_add_subt[19]), .B0(n1039), .B1(
d_ff_Zn[19]), .Y(n665) );
AO22XLTS U1434 ( .A0(n1038), .A1(sign_inv_out[30]), .B0(n798), .B1(
data_output[30]), .Y(n527) );
INVX2TS U1435 ( .A(n1140), .Y(n1138) );
AO22XLTS U1436 ( .A0(n1138), .A1(result_add_subt[20]), .B0(n1039), .B1(
d_ff_Zn[20]), .Y(n664) );
AO22XLTS U1437 ( .A0(n1038), .A1(sign_inv_out[23]), .B0(n1040), .B1(
data_output[23]), .Y(n541) );
AO22XLTS U1438 ( .A0(n1138), .A1(result_add_subt[21]), .B0(n1039), .B1(
d_ff_Zn[21]), .Y(n663) );
AO22XLTS U1439 ( .A0(n803), .A1(sign_inv_out[29]), .B0(n1068), .B1(
data_output[29]), .Y(n529) );
AO22XLTS U1440 ( .A0(n1138), .A1(result_add_subt[22]), .B0(n1039), .B1(
d_ff_Zn[22]), .Y(n662) );
AO22XLTS U1441 ( .A0(n1138), .A1(result_add_subt[23]), .B0(n1039), .B1(
d_ff_Zn[23]), .Y(n661) );
AO22XLTS U1442 ( .A0(n1038), .A1(sign_inv_out[24]), .B0(n1040), .B1(
data_output[24]), .Y(n539) );
AO22XLTS U1443 ( .A0(n1138), .A1(result_add_subt[24]), .B0(n1039), .B1(
d_ff_Zn[24]), .Y(n660) );
AO22XLTS U1444 ( .A0(n803), .A1(sign_inv_out[27]), .B0(n1040), .B1(
data_output[27]), .Y(n533) );
AO22XLTS U1445 ( .A0(n1138), .A1(result_add_subt[25]), .B0(n1039), .B1(
d_ff_Zn[25]), .Y(n659) );
AO22XLTS U1446 ( .A0(n1138), .A1(result_add_subt[26]), .B0(n1039), .B1(
d_ff_Zn[26]), .Y(n658) );
INVX2TS U1447 ( .A(n1199), .Y(n1100) );
AO22XLTS U1448 ( .A0(d_ff2_X[23]), .A1(n802), .B0(d_ff_Xn[23]), .B1(n1100),
.Y(n353) );
AO22XLTS U1449 ( .A0(n1038), .A1(sign_inv_out[26]), .B0(n1040), .B1(
data_output[26]), .Y(n535) );
AO22XLTS U1450 ( .A0(n1138), .A1(result_add_subt[27]), .B0(n1039), .B1(
d_ff_Zn[27]), .Y(n657) );
AO22XLTS U1451 ( .A0(n803), .A1(sign_inv_out[25]), .B0(n1040), .B1(
data_output[25]), .Y(n537) );
CLKBUFX2TS U1452 ( .A(n1049), .Y(n1053) );
AO22XLTS U1453 ( .A0(n1167), .A1(d_ff1_operation_out), .B0(n1061), .B1(
operation), .Y(n723) );
INVX2TS U1454 ( .A(n1052), .Y(n1054) );
AO22XLTS U1455 ( .A0(n1054), .A1(sign_inv_out[0]), .B0(n1068), .B1(
data_output[0]), .Y(n587) );
AO22XLTS U1456 ( .A0(n1050), .A1(data_in[2]), .B0(n1041), .B1(d_ff1_Z[2]),
.Y(n718) );
AO22XLTS U1457 ( .A0(n1128), .A1(d_ff2_Y[22]), .B0(n1126), .B1(
d_ff3_sh_y_out[22]), .Y(n418) );
AO22XLTS U1458 ( .A0(n1050), .A1(data_in[3]), .B0(n1041), .B1(d_ff1_Z[3]),
.Y(n717) );
AO22XLTS U1459 ( .A0(n1050), .A1(data_in[4]), .B0(n1041), .B1(d_ff1_Z[4]),
.Y(n716) );
AO22XLTS U1460 ( .A0(n1183), .A1(d_ff2_Y[21]), .B0(n1051), .B1(
d_ff3_sh_y_out[21]), .Y(n420) );
AO22XLTS U1461 ( .A0(n1053), .A1(data_in[5]), .B0(n1041), .B1(d_ff1_Z[5]),
.Y(n715) );
AO22XLTS U1462 ( .A0(n1054), .A1(sign_inv_out[2]), .B0(n1052), .B1(
data_output[2]), .Y(n583) );
AO22XLTS U1463 ( .A0(n1061), .A1(data_in[6]), .B0(n1041), .B1(d_ff1_Z[6]),
.Y(n714) );
AO22XLTS U1464 ( .A0(n1128), .A1(d_ff2_Y[20]), .B0(n1051), .B1(
d_ff3_sh_y_out[20]), .Y(n422) );
AO22XLTS U1465 ( .A0(n1042), .A1(data_in[7]), .B0(n1041), .B1(d_ff1_Z[7]),
.Y(n713) );
AO22XLTS U1466 ( .A0(n1061), .A1(data_in[8]), .B0(n1041), .B1(d_ff1_Z[8]),
.Y(n712) );
AO22XLTS U1467 ( .A0(n1054), .A1(sign_inv_out[3]), .B0(n1052), .B1(
data_output[3]), .Y(n581) );
AO22XLTS U1468 ( .A0(n1183), .A1(d_ff2_Y[19]), .B0(n1051), .B1(
d_ff3_sh_y_out[19]), .Y(n424) );
AO22XLTS U1469 ( .A0(n1042), .A1(data_in[9]), .B0(n1041), .B1(d_ff1_Z[9]),
.Y(n711) );
AO22XLTS U1470 ( .A0(n1061), .A1(data_in[10]), .B0(n1041), .B1(d_ff1_Z[10]),
.Y(n710) );
INVX2TS U1471 ( .A(n1049), .Y(n1060) );
AO22XLTS U1472 ( .A0(n1042), .A1(data_in[11]), .B0(n1060), .B1(d_ff1_Z[11]),
.Y(n709) );
AO22XLTS U1473 ( .A0(n1111), .A1(d_ff2_Y[18]), .B0(n1051), .B1(
d_ff3_sh_y_out[18]), .Y(n426) );
AO22XLTS U1474 ( .A0(n1054), .A1(sign_inv_out[4]), .B0(n1052), .B1(
data_output[4]), .Y(n579) );
CLKBUFX3TS U1475 ( .A(n1049), .Y(n1061) );
AO22XLTS U1476 ( .A0(n1061), .A1(data_in[12]), .B0(n1060), .B1(d_ff1_Z[12]),
.Y(n708) );
AO22XLTS U1477 ( .A0(n1042), .A1(data_in[13]), .B0(n1060), .B1(d_ff1_Z[13]),
.Y(n707) );
AO22XLTS U1478 ( .A0(n1183), .A1(d_ff2_Y[17]), .B0(n1051), .B1(
d_ff3_sh_y_out[17]), .Y(n428) );
AO22XLTS U1479 ( .A0(n1061), .A1(data_in[14]), .B0(n1060), .B1(d_ff1_Z[14]),
.Y(n706) );
AO22XLTS U1480 ( .A0(n1054), .A1(sign_inv_out[5]), .B0(n1052), .B1(
data_output[5]), .Y(n577) );
AO22XLTS U1481 ( .A0(n1042), .A1(data_in[15]), .B0(n1060), .B1(d_ff1_Z[15]),
.Y(n705) );
AO22XLTS U1482 ( .A0(n1167), .A1(d_ff1_shift_region_flag_out[1]), .B0(n1042),
.B1(shift_region_flag[1]), .Y(n721) );
AO22XLTS U1483 ( .A0(n1069), .A1(d_ff2_Y[16]), .B0(n1051), .B1(
d_ff3_sh_y_out[16]), .Y(n430) );
AO22XLTS U1484 ( .A0(n1061), .A1(data_in[16]), .B0(n1060), .B1(d_ff1_Z[16]),
.Y(n704) );
AOI31XLTS U1485 ( .A0(cordic_FSM_state_reg[3]), .A1(cordic_FSM_state_reg[0]),
.A2(ack_cordic), .B0(cordic_FSM_state_reg[1]), .Y(n1043) );
OAI21X1TS U1486 ( .A0(n1044), .A1(n1043), .B0(cordic_FSM_state_reg[2]), .Y(
n1047) );
NAND2X1TS U1487 ( .A(cont_var_out[1]), .B(n1227), .Y(n1045) );
NAND4XLTS U1488 ( .A(cordic_FSM_state_reg[3]), .B(n1215), .C(n1065), .D(
n1045), .Y(n1046) );
AOI32X1TS U1489 ( .A0(n1048), .A1(n1047), .A2(n1046), .B0(n1225), .B1(n1047),
.Y(n731) );
AO22XLTS U1490 ( .A0(n1050), .A1(data_in[17]), .B0(n1060), .B1(d_ff1_Z[17]),
.Y(n703) );
AO22XLTS U1491 ( .A0(n1183), .A1(d_ff2_Y[15]), .B0(n1051), .B1(
d_ff3_sh_y_out[15]), .Y(n432) );
AO22XLTS U1492 ( .A0(n1050), .A1(data_in[18]), .B0(n1060), .B1(d_ff1_Z[18]),
.Y(n702) );
AO22XLTS U1493 ( .A0(n1054), .A1(sign_inv_out[6]), .B0(n1052), .B1(
data_output[6]), .Y(n575) );
AO22XLTS U1494 ( .A0(n1049), .A1(data_in[19]), .B0(n1060), .B1(d_ff1_Z[19]),
.Y(n701) );
AO22XLTS U1495 ( .A0(n1050), .A1(data_in[20]), .B0(n1055), .B1(d_ff1_Z[20]),
.Y(n700) );
AO22XLTS U1496 ( .A0(n1111), .A1(d_ff2_Y[14]), .B0(n1051), .B1(
d_ff3_sh_y_out[14]), .Y(n434) );
AO22XLTS U1497 ( .A0(n1054), .A1(sign_inv_out[7]), .B0(n1052), .B1(
data_output[7]), .Y(n573) );
AO22XLTS U1498 ( .A0(n1183), .A1(d_ff2_Y[13]), .B0(n1051), .B1(
d_ff3_sh_y_out[13]), .Y(n436) );
AO22XLTS U1499 ( .A0(n1053), .A1(data_in[23]), .B0(n1055), .B1(d_ff1_Z[23]),
.Y(n697) );
AO22XLTS U1500 ( .A0(n1053), .A1(data_in[24]), .B0(n1055), .B1(d_ff1_Z[24]),
.Y(n696) );
AO22XLTS U1501 ( .A0(n1054), .A1(sign_inv_out[1]), .B0(n1052), .B1(
data_output[1]), .Y(n585) );
CLKBUFX3TS U1502 ( .A(n1096), .Y(n1110) );
AO22XLTS U1503 ( .A0(n1111), .A1(d_ff2_Y[11]), .B0(n1110), .B1(
d_ff3_sh_y_out[11]), .Y(n440) );
AO22XLTS U1504 ( .A0(n1053), .A1(data_in[25]), .B0(n1055), .B1(d_ff1_Z[25]),
.Y(n695) );
AO22XLTS U1505 ( .A0(n1054), .A1(sign_inv_out[8]), .B0(n1062), .B1(
data_output[8]), .Y(n571) );
AO22XLTS U1506 ( .A0(n1053), .A1(data_in[26]), .B0(n1055), .B1(d_ff1_Z[26]),
.Y(n694) );
AO22XLTS U1507 ( .A0(n1128), .A1(d_ff2_Y[10]), .B0(n1110), .B1(
d_ff3_sh_y_out[10]), .Y(n442) );
AO22XLTS U1508 ( .A0(n1042), .A1(data_in[27]), .B0(n1055), .B1(d_ff1_Z[27]),
.Y(n693) );
AO22XLTS U1509 ( .A0(n1167), .A1(d_ff1_shift_region_flag_out[0]), .B0(n1061),
.B1(shift_region_flag[0]), .Y(n722) );
AO22XLTS U1510 ( .A0(n1061), .A1(data_in[28]), .B0(n1055), .B1(d_ff1_Z[28]),
.Y(n692) );
AO22XLTS U1511 ( .A0(n1054), .A1(sign_inv_out[9]), .B0(n1068), .B1(
data_output[9]), .Y(n569) );
AO22XLTS U1512 ( .A0(n1042), .A1(data_in[29]), .B0(n1055), .B1(d_ff1_Z[29]),
.Y(n691) );
AO22XLTS U1513 ( .A0(n1111), .A1(d_ff2_Y[9]), .B0(n1110), .B1(
d_ff3_sh_y_out[9]), .Y(n444) );
AO22XLTS U1514 ( .A0(n1061), .A1(data_in[30]), .B0(n1167), .B1(d_ff1_Z[30]),
.Y(n690) );
INVX2TS U1515 ( .A(beg_fsm_cordic), .Y(n1056) );
AOI32X1TS U1516 ( .A0(n1135), .A1(n1215), .A2(n1056), .B0(n1158), .B1(
cordic_FSM_state_reg[2]), .Y(n1059) );
OR4X2TS U1517 ( .A(ack_cordic), .B(n1215), .C(n800), .D(
cordic_FSM_state_reg[1]), .Y(n1161) );
NOR2BX1TS U1518 ( .AN(ready_add_subt), .B(cordic_FSM_state_reg[2]), .Y(n1057) );
OAI31X1TS U1519 ( .A0(n1157), .A1(n1057), .A2(n800), .B0(n1225), .Y(n1058)
);
NAND4XLTS U1520 ( .A(n1059), .B(n1166), .C(n1161), .D(n1058), .Y(n730) );
AO22XLTS U1521 ( .A0(n1042), .A1(data_in[31]), .B0(n1060), .B1(d_ff1_Z[31]),
.Y(n689) );
AO22XLTS U1522 ( .A0(n1111), .A1(d_ff2_Y[8]), .B0(n1110), .B1(
d_ff3_sh_y_out[8]), .Y(n446) );
AO22XLTS U1523 ( .A0(n1028), .A1(result_add_subt[0]), .B0(n1140), .B1(
d_ff_Zn[0]), .Y(n684) );
AO22XLTS U1524 ( .A0(n1070), .A1(sign_inv_out[10]), .B0(n1062), .B1(
data_output[10]), .Y(n567) );
CMPR32X2TS U1525 ( .A(n1223), .B(d_ff2_X[26]), .C(n1063), .CO(n1076), .S(
n1064) );
AO22XLTS U1526 ( .A0(n1069), .A1(n1064), .B0(n1108), .B1(d_ff3_sh_x_out[26]),
.Y(n342) );
NAND3X1TS U1527 ( .A(cont_var_out[0]), .B(ack_add_subt), .C(n1065), .Y(n1164) );
AOI31XLTS U1528 ( .A0(ack_add_subt), .A1(n1065), .A2(n1218), .B0(
cont_var_out[0]), .Y(n1066) );
NOR3BXLTS U1529 ( .AN(n1164), .B(n1205), .C(n1066), .Y(n724) );
AO22XLTS U1530 ( .A0(n1069), .A1(d_ff2_Y[7]), .B0(n1110), .B1(
d_ff3_sh_y_out[7]), .Y(n448) );
AO22XLTS U1531 ( .A0(n1128), .A1(d_ff2_X[0]), .B0(n1126), .B1(
d_ff3_sh_x_out[0]), .Y(n398) );
AOI2BB2XLTS U1532 ( .B0(n1228), .B1(n1067), .A0N(d_ff_Xn[25]), .A1N(n1196),
.Y(n351) );
AO22XLTS U1533 ( .A0(n1072), .A1(d_ff2_X[1]), .B0(n1126), .B1(
d_ff3_sh_x_out[1]), .Y(n396) );
AO22XLTS U1534 ( .A0(n1070), .A1(sign_inv_out[11]), .B0(n1062), .B1(
data_output[11]), .Y(n565) );
AO22XLTS U1535 ( .A0(n1069), .A1(d_ff2_Y[6]), .B0(n1110), .B1(
d_ff3_sh_y_out[6]), .Y(n450) );
AO22XLTS U1536 ( .A0(n1072), .A1(d_ff2_X[2]), .B0(n1126), .B1(
d_ff3_sh_x_out[2]), .Y(n394) );
CLKBUFX3TS U1537 ( .A(n1101), .Y(n1073) );
AO22XLTS U1538 ( .A0(n1148), .A1(d_ff2_X[3]), .B0(n1073), .B1(
d_ff3_sh_x_out[3]), .Y(n392) );
AO22XLTS U1539 ( .A0(n1148), .A1(d_ff2_X[4]), .B0(n1073), .B1(
d_ff3_sh_x_out[4]), .Y(n390) );
AO22XLTS U1540 ( .A0(n1069), .A1(d_ff2_Y[5]), .B0(n1110), .B1(
d_ff3_sh_y_out[5]), .Y(n452) );
AO22XLTS U1541 ( .A0(n1070), .A1(sign_inv_out[12]), .B0(n1068), .B1(
data_output[12]), .Y(n563) );
AO22XLTS U1542 ( .A0(n1072), .A1(d_ff2_X[5]), .B0(n1073), .B1(
d_ff3_sh_x_out[5]), .Y(n388) );
AO22XLTS U1543 ( .A0(n1148), .A1(d_ff2_X[6]), .B0(n1073), .B1(
d_ff3_sh_x_out[6]), .Y(n386) );
AO22XLTS U1544 ( .A0(n1111), .A1(d_ff2_Y[4]), .B0(n1110), .B1(
d_ff3_sh_y_out[4]), .Y(n454) );
AO22XLTS U1545 ( .A0(n1148), .A1(d_ff2_X[7]), .B0(n1073), .B1(
d_ff3_sh_x_out[7]), .Y(n384) );
AO22XLTS U1546 ( .A0(n1070), .A1(sign_inv_out[13]), .B0(n1068), .B1(
data_output[13]), .Y(n561) );
AO22XLTS U1547 ( .A0(n1148), .A1(d_ff2_X[8]), .B0(n1073), .B1(
d_ff3_sh_x_out[8]), .Y(n382) );
AO22XLTS U1548 ( .A0(n1069), .A1(d_ff2_Y[3]), .B0(n1110), .B1(
d_ff3_sh_y_out[3]), .Y(n456) );
AO22XLTS U1549 ( .A0(n1148), .A1(d_ff2_X[9]), .B0(n1073), .B1(
d_ff3_sh_x_out[9]), .Y(n380) );
AO22XLTS U1550 ( .A0(n1111), .A1(d_ff2_X[10]), .B0(n1073), .B1(
d_ff3_sh_x_out[10]), .Y(n378) );
AO22XLTS U1551 ( .A0(n1069), .A1(d_ff2_Y[2]), .B0(n1098), .B1(
d_ff3_sh_y_out[2]), .Y(n458) );
AO22XLTS U1552 ( .A0(n1072), .A1(d_ff2_X[11]), .B0(n1073), .B1(
d_ff3_sh_x_out[11]), .Y(n376) );
AO22XLTS U1553 ( .A0(n1070), .A1(sign_inv_out[14]), .B0(n1052), .B1(
data_output[14]), .Y(n559) );
AO22XLTS U1554 ( .A0(n1072), .A1(d_ff2_X[13]), .B0(n1071), .B1(
d_ff3_sh_x_out[13]), .Y(n372) );
AO22XLTS U1555 ( .A0(n1138), .A1(result_add_subt[28]), .B0(n1142), .B1(
d_ff_Zn[28]), .Y(n656) );
INVX2TS U1556 ( .A(n1129), .Y(n1130) );
AO22XLTS U1557 ( .A0(n1130), .A1(result_add_subt[5]), .B0(n1129), .B1(
d_ff_Xn[5]), .Y(n615) );
AO22XLTS U1558 ( .A0(n1130), .A1(result_add_subt[3]), .B0(n1129), .B1(
d_ff_Xn[3]), .Y(n617) );
AO22XLTS U1559 ( .A0(n1130), .A1(result_add_subt[2]), .B0(n1129), .B1(
d_ff_Xn[2]), .Y(n618) );
AO22XLTS U1560 ( .A0(n1130), .A1(result_add_subt[1]), .B0(n1129), .B1(
d_ff_Xn[1]), .Y(n619) );
INVX2TS U1561 ( .A(n1139), .Y(n1121) );
CLKBUFX3TS U1562 ( .A(n1149), .Y(n1122) );
AO22XLTS U1563 ( .A0(n1121), .A1(result_add_subt[22]), .B0(n1122), .B1(
d_ff_Xn[22]), .Y(n598) );
AO22XLTS U1564 ( .A0(n1148), .A1(d_ff2_X[12]), .B0(n1073), .B1(
d_ff3_sh_x_out[12]), .Y(n374) );
AO22XLTS U1565 ( .A0(n1121), .A1(result_add_subt[21]), .B0(n1122), .B1(
d_ff_Xn[21]), .Y(n599) );
NOR2X1TS U1566 ( .A(d_ff2_Y[27]), .B(n1118), .Y(n1117) );
OAI21XLTS U1567 ( .A0(n1117), .A1(n1230), .B0(n1079), .Y(n1074) );
AO22XLTS U1568 ( .A0(n1128), .A1(n1074), .B0(n1126), .B1(d_ff3_sh_y_out[28]),
.Y(n404) );
INVX2TS U1569 ( .A(n1139), .Y(n1150) );
AO22XLTS U1570 ( .A0(n1150), .A1(result_add_subt[18]), .B0(n1122), .B1(
d_ff_Xn[18]), .Y(n602) );
NOR2XLTS U1571 ( .A(d_ff2_X[27]), .B(n1076), .Y(n1075) );
AOI21X1TS U1572 ( .A0(n1076), .A1(d_ff2_X[27]), .B0(n1075), .Y(n1077) );
AOI2BB2XLTS U1573 ( .B0(n1189), .B1(n1077), .A0N(d_ff3_sh_x_out[27]), .A1N(
n1119), .Y(n341) );
AO22XLTS U1574 ( .A0(n1150), .A1(result_add_subt[15]), .B0(n1149), .B1(
d_ff_Xn[15]), .Y(n605) );
AOI21X1TS U1575 ( .A0(d_ff2_Y[29]), .A1(n1079), .B0(n1078), .Y(n1080) );
AOI2BB2XLTS U1576 ( .B0(n1189), .B1(n1080), .A0N(d_ff3_sh_y_out[29]), .A1N(
n1119), .Y(n403) );
AO22XLTS U1577 ( .A0(n1150), .A1(result_add_subt[11]), .B0(n1141), .B1(
d_ff_Xn[11]), .Y(n609) );
INVX2TS U1578 ( .A(n1081), .Y(n1087) );
AOI32X1TS U1579 ( .A0(n1085), .A1(n1084), .A2(n1083), .B0(cont_iter_out[1]),
.B1(n1084), .Y(n500) );
AO22XLTS U1580 ( .A0(n1130), .A1(result_add_subt[9]), .B0(n1139), .B1(
d_ff_Xn[9]), .Y(n611) );
AO22XLTS U1581 ( .A0(n1130), .A1(result_add_subt[8]), .B0(n1141), .B1(
d_ff_Xn[8]), .Y(n612) );
AO22XLTS U1582 ( .A0(n1130), .A1(result_add_subt[4]), .B0(n1129), .B1(
d_ff_Xn[4]), .Y(n616) );
AO22XLTS U1583 ( .A0(n1130), .A1(result_add_subt[0]), .B0(n1139), .B1(
d_ff_Xn[0]), .Y(n620) );
AO22XLTS U1584 ( .A0(n1121), .A1(result_add_subt[25]), .B0(n1122), .B1(
d_ff_Xn[25]), .Y(n595) );
AO22XLTS U1585 ( .A0(n1121), .A1(result_add_subt[23]), .B0(n1122), .B1(
d_ff_Xn[23]), .Y(n597) );
AO22XLTS U1586 ( .A0(n1130), .A1(result_add_subt[6]), .B0(n1129), .B1(
d_ff_Xn[6]), .Y(n614) );
INVX2TS U1587 ( .A(n1195), .Y(n1123) );
AO22XLTS U1588 ( .A0(d_ff_Yn[31]), .A1(n1123), .B0(d_ff2_Y[31]), .B1(n1099),
.Y(n401) );
AO22XLTS U1589 ( .A0(d_ff_Yn[22]), .A1(n1123), .B0(d_ff2_Y[22]), .B1(n1099),
.Y(n419) );
AO22XLTS U1590 ( .A0(d_ff_Yn[21]), .A1(n1123), .B0(d_ff2_Y[21]), .B1(n1099),
.Y(n421) );
AOI21X1TS U1591 ( .A0(n1087), .A1(n1189), .B0(n1086), .Y(n1184) );
NOR2X2TS U1592 ( .A(cont_iter_out[3]), .B(n1217), .Y(n1114) );
AOI22X1TS U1593 ( .A0(n1114), .A1(n1088), .B0(d_ff3_LUT_out[0]), .B1(n1203),
.Y(n1089) );
NAND2X1TS U1594 ( .A(n1184), .B(n1089), .Y(n524) );
INVX2TS U1595 ( .A(n1194), .Y(n1134) );
AO22XLTS U1596 ( .A0(d_ff_Yn[18]), .A1(n1134), .B0(d_ff2_Y[18]), .B1(n1099),
.Y(n427) );
AO22XLTS U1597 ( .A0(n1098), .A1(d_ff3_sign_out), .B0(n1119), .B1(
d_ff2_Z[31]), .Y(n464) );
AO22XLTS U1598 ( .A0(d_ff_Yn[17]), .A1(n1134), .B0(d_ff2_Y[17]), .B1(n1133),
.Y(n429) );
AO22XLTS U1599 ( .A0(d_ff_Xn[0]), .A1(n1123), .B0(d_ff2_X[0]), .B1(n1099),
.Y(n399) );
AO22XLTS U1600 ( .A0(d_ff_Xn[4]), .A1(n1123), .B0(d_ff2_X[4]), .B1(n1099),
.Y(n391) );
INVX2TS U1601 ( .A(n1090), .Y(n1091) );
AO22XLTS U1602 ( .A0(d_ff_Yn[6]), .A1(n1092), .B0(d_ff2_Y[6]), .B1(n1091),
.Y(n451) );
AO22XLTS U1603 ( .A0(d_ff_Xn[8]), .A1(n1123), .B0(d_ff2_X[8]), .B1(n1099),
.Y(n383) );
AO22XLTS U1604 ( .A0(d_ff_Yn[15]), .A1(n1134), .B0(d_ff2_Y[15]), .B1(n802),
.Y(n433) );
AO22XLTS U1605 ( .A0(d_ff_Xn[9]), .A1(n1092), .B0(d_ff2_X[9]), .B1(n801),
.Y(n381) );
AO22XLTS U1606 ( .A0(d_ff_Xn[11]), .A1(n1100), .B0(d_ff2_X[11]), .B1(n802),
.Y(n377) );
AO22XLTS U1607 ( .A0(d_ff_Yn[14]), .A1(n1134), .B0(d_ff2_Y[14]), .B1(n1133),
.Y(n435) );
AO22XLTS U1608 ( .A0(d_ff_Xn[15]), .A1(n1100), .B0(d_ff2_X[15]), .B1(n1133),
.Y(n369) );
AO22XLTS U1609 ( .A0(d_ff_Yn[13]), .A1(n1134), .B0(d_ff2_Y[13]), .B1(n1133),
.Y(n437) );
AO22XLTS U1610 ( .A0(d_ff_Xn[18]), .A1(n1100), .B0(d_ff2_X[18]), .B1(n802),
.Y(n363) );
AO22XLTS U1611 ( .A0(d_ff_Xn[21]), .A1(n1100), .B0(d_ff2_X[21]), .B1(n802),
.Y(n357) );
AO22XLTS U1612 ( .A0(d_ff_Yn[12]), .A1(n1134), .B0(d_ff2_Y[12]), .B1(n1091),
.Y(n439) );
AO22XLTS U1613 ( .A0(d_ff_Xn[22]), .A1(n1100), .B0(d_ff2_X[22]), .B1(n802),
.Y(n355) );
AO22XLTS U1614 ( .A0(d_ff_Yn[11]), .A1(n1134), .B0(d_ff2_Y[11]), .B1(n1091),
.Y(n441) );
AO22XLTS U1615 ( .A0(d_ff_Xn[31]), .A1(n1092), .B0(d_ff2_X[31]), .B1(n801),
.Y(n337) );
AO22XLTS U1616 ( .A0(d_ff_Yn[0]), .A1(n1100), .B0(d_ff2_Y[0]), .B1(n802),
.Y(n463) );
AO22XLTS U1617 ( .A0(d_ff_Yn[10]), .A1(n1123), .B0(d_ff2_Y[10]), .B1(n1091),
.Y(n443) );
AO22XLTS U1618 ( .A0(d_ff_Yn[1]), .A1(n1092), .B0(d_ff2_Y[1]), .B1(n1099),
.Y(n461) );
AO22XLTS U1619 ( .A0(d_ff_Yn[9]), .A1(n1123), .B0(d_ff2_Y[9]), .B1(n1091),
.Y(n445) );
AO22XLTS U1620 ( .A0(d_ff_Yn[2]), .A1(n1092), .B0(d_ff2_Y[2]), .B1(n802),
.Y(n459) );
AO22XLTS U1621 ( .A0(d_ff_Yn[3]), .A1(n1092), .B0(d_ff2_Y[3]), .B1(n1091),
.Y(n457) );
AO22XLTS U1622 ( .A0(d_ff_Yn[8]), .A1(n1134), .B0(d_ff2_Y[8]), .B1(n1091),
.Y(n447) );
AO22XLTS U1623 ( .A0(d_ff_Yn[7]), .A1(n1092), .B0(d_ff2_Y[7]), .B1(n1091),
.Y(n449) );
AO22XLTS U1624 ( .A0(d_ff_Yn[4]), .A1(n1134), .B0(d_ff2_Y[4]), .B1(n1091),
.Y(n455) );
AO22XLTS U1625 ( .A0(d_ff_Yn[5]), .A1(n1092), .B0(d_ff2_Y[5]), .B1(n1091),
.Y(n453) );
NAND2X1TS U1626 ( .A(n1093), .B(n1190), .Y(n1095) );
AO21XLTS U1627 ( .A0(d_ff3_LUT_out[11]), .A1(n1096), .B0(n1095), .Y(n513) );
OAI31X1TS U1628 ( .A0(cont_iter_out[0]), .A1(cont_iter_out[2]), .A2(
cont_iter_out[3]), .B0(n1188), .Y(n1109) );
NOR2X1TS U1629 ( .A(n1203), .B(n1109), .Y(n1097) );
AO21XLTS U1630 ( .A0(d_ff3_LUT_out[13]), .A1(n1108), .B0(n1097), .Y(n511) );
OAI32X1TS U1631 ( .A0(n1203), .A1(n1216), .A2(n1094), .B0(n1186), .B1(n1203),
.Y(n1102) );
AO21XLTS U1632 ( .A0(d_ff3_LUT_out[14]), .A1(n1098), .B0(n1102), .Y(n510) );
AO21XLTS U1633 ( .A0(d_ff3_LUT_out[7]), .A1(n1096), .B0(n1095), .Y(n517) );
AO21XLTS U1634 ( .A0(d_ff3_LUT_out[18]), .A1(n1098), .B0(n1097), .Y(n506) );
AO22XLTS U1635 ( .A0(d_ff_Xn[30]), .A1(n1100), .B0(d_ff2_X[30]), .B1(n802),
.Y(n346) );
AO21XLTS U1636 ( .A0(d_ff3_LUT_out[5]), .A1(n1192), .B0(n1102), .Y(n519) );
XOR2X1TS U1637 ( .A(n1103), .B(n1228), .Y(n1104) );
MXI2X1TS U1638 ( .A(n1106), .B(n1105), .S0(n1104), .Y(n1107) );
AO21XLTS U1639 ( .A0(d_ff3_sh_x_out[25]), .A1(n1108), .B0(n1107), .Y(n343)
);
AO22XLTS U1640 ( .A0(d_ff_Yn[25]), .A1(n1123), .B0(d_ff2_Y[25]), .B1(n1099),
.Y(n415) );
AO22XLTS U1641 ( .A0(n1121), .A1(result_add_subt[29]), .B0(n1141), .B1(
d_ff_Xn[29]), .Y(n591) );
AOI21X1TS U1642 ( .A0(n1114), .A1(n1216), .B0(n1185), .Y(n1116) );
AOI2BB2XLTS U1643 ( .B0(n1116), .B1(n1109), .A0N(n1183), .A1N(
d_ff3_LUT_out[21]), .Y(n503) );
AO22XLTS U1644 ( .A0(n1111), .A1(d_ff2_Y[12]), .B0(n1110), .B1(
d_ff3_sh_y_out[12]), .Y(n438) );
OAI21X1TS U1645 ( .A0(cont_iter_out[2]), .A1(cont_iter_out[3]), .B0(n1189),
.Y(n1182) );
AOI21X1TS U1646 ( .A0(n1112), .A1(n1223), .B0(n1182), .Y(n1113) );
AOI2BB1XLTS U1647 ( .A0N(n1183), .A1N(d_ff3_LUT_out[26]), .B0(n1113), .Y(
n498) );
AO22XLTS U1648 ( .A0(n1121), .A1(result_add_subt[28]), .B0(n1141), .B1(
d_ff_Xn[28]), .Y(n592) );
INVX2TS U1649 ( .A(n1114), .Y(n1180) );
OAI21XLTS U1650 ( .A0(n814), .A1(n1180), .B0(n1188), .Y(n1115) );
AOI2BB2XLTS U1651 ( .B0(n1116), .B1(n1115), .A0N(n1183), .A1N(
d_ff3_LUT_out[9]), .Y(n515) );
AOI21X1TS U1652 ( .A0(n1118), .A1(d_ff2_Y[27]), .B0(n1117), .Y(n1120) );
AOI2BB2XLTS U1653 ( .B0(n1189), .B1(n1120), .A0N(d_ff3_sh_y_out[27]), .A1N(
n1119), .Y(n405) );
AO22XLTS U1654 ( .A0(n1121), .A1(result_add_subt[27]), .B0(n1122), .B1(
d_ff_Xn[27]), .Y(n593) );
AO22XLTS U1655 ( .A0(n1121), .A1(result_add_subt[26]), .B0(n1122), .B1(
d_ff_Xn[26]), .Y(n594) );
AO22XLTS U1656 ( .A0(n1038), .A1(sign_inv_out[28]), .B0(n1062), .B1(
data_output[28]), .Y(n531) );
AO22XLTS U1657 ( .A0(n1121), .A1(result_add_subt[24]), .B0(n1122), .B1(
d_ff_Xn[24]), .Y(n596) );
NAND2BXLTS U1658 ( .AN(d_ff3_LUT_out[27]), .B(n1185), .Y(n497) );
AO22XLTS U1659 ( .A0(n1121), .A1(result_add_subt[20]), .B0(n1122), .B1(
d_ff_Xn[20]), .Y(n600) );
AO22XLTS U1660 ( .A0(n1150), .A1(result_add_subt[19]), .B0(n1122), .B1(
d_ff_Xn[19]), .Y(n601) );
AO22XLTS U1661 ( .A0(n1150), .A1(result_add_subt[17]), .B0(n1149), .B1(
d_ff_Xn[17]), .Y(n603) );
AO22XLTS U1662 ( .A0(d_ff_Yn[26]), .A1(n1123), .B0(d_ff2_Y[26]), .B1(n801),
.Y(n414) );
AOI22X1TS U1663 ( .A0(cont_iter_out[1]), .A1(n1226), .B0(d_ff2_Y[24]), .B1(
n1217), .Y(n1124) );
XNOR2X1TS U1664 ( .A(n1125), .B(n1124), .Y(n1127) );
AO22XLTS U1665 ( .A0(n1128), .A1(n1127), .B0(n1126), .B1(d_ff3_sh_y_out[24]),
.Y(n408) );
AO22XLTS U1666 ( .A0(n1150), .A1(result_add_subt[16]), .B0(n1149), .B1(
d_ff_Xn[16]), .Y(n604) );
AO22XLTS U1667 ( .A0(n1130), .A1(result_add_subt[7]), .B0(n1129), .B1(
d_ff_Xn[7]), .Y(n613) );
AO22XLTS U1668 ( .A0(n1150), .A1(result_add_subt[12]), .B0(n1139), .B1(
d_ff_Xn[12]), .Y(n608) );
AO21XLTS U1669 ( .A0(d_ff3_LUT_out[8]), .A1(n1132), .B0(n1131), .Y(n516) );
AO22XLTS U1670 ( .A0(d_ff_Yn[16]), .A1(n1134), .B0(d_ff2_Y[16]), .B1(n1133),
.Y(n431) );
AOI31XLTS U1671 ( .A0(cordic_FSM_state_reg[0]), .A1(n1135), .A2(
beg_fsm_cordic), .B0(ack_add_subt), .Y(n1137) );
OAI211XLTS U1672 ( .A0(n1215), .A1(n800), .B0(cordic_FSM_state_reg[1]), .C0(
n1225), .Y(n1136) );
NAND3XLTS U1673 ( .A(n1137), .B(n1185), .C(n1136), .Y(
cordic_FSM_state_next_1_) );
AO22XLTS U1674 ( .A0(n1138), .A1(result_add_subt[29]), .B0(n1142), .B1(
d_ff_Zn[29]), .Y(n655) );
AO22XLTS U1675 ( .A0(n1150), .A1(result_add_subt[13]), .B0(n1139), .B1(
d_ff_Xn[13]), .Y(n607) );
INVX2TS U1676 ( .A(n1140), .Y(n1143) );
AO22XLTS U1677 ( .A0(n1143), .A1(result_add_subt[30]), .B0(n1142), .B1(
d_ff_Zn[30]), .Y(n654) );
AO22XLTS U1678 ( .A0(n1150), .A1(result_add_subt[14]), .B0(n1141), .B1(
d_ff_Xn[14]), .Y(n606) );
AO22XLTS U1679 ( .A0(n1143), .A1(result_add_subt[31]), .B0(n1142), .B1(
d_ff_Zn[31]), .Y(n653) );
OAI21XLTS U1680 ( .A0(d_ff2_X[24]), .A1(n1217), .B0(n1144), .Y(n1145) );
XOR2XLTS U1681 ( .A(n1146), .B(n1145), .Y(n1147) );
AO22XLTS U1682 ( .A0(n1148), .A1(n1147), .B0(n1185), .B1(d_ff3_sh_x_out[24]),
.Y(n344) );
AO22XLTS U1683 ( .A0(n1150), .A1(result_add_subt[10]), .B0(n1149), .B1(
d_ff_Xn[10]), .Y(n610) );
AO22XLTS U1684 ( .A0(n1012), .A1(d_ff3_sh_x_out[31]), .B0(n1152), .B1(
d_ff3_sh_y_out[31]), .Y(add_subt_dataB[31]) );
AO22XLTS U1685 ( .A0(d_ff3_sh_y_out[30]), .A1(n1152), .B0(d_ff3_sh_x_out[30]), .B1(n1154), .Y(add_subt_dataB[30]) );
AOI22X1TS U1686 ( .A0(n973), .A1(d_ff3_sh_x_out[27]), .B0(n1153), .B1(
d_ff3_sh_y_out[27]), .Y(n1156) );
NAND2X1TS U1687 ( .A(d_ff3_LUT_out[27]), .B(n983), .Y(n1155) );
NAND2X1TS U1688 ( .A(n1156), .B(n1155), .Y(add_subt_dataB[27]) );
AOI2BB2XLTS U1689 ( .B0(d_ff3_sign_out), .B1(n1227), .A0N(n1227), .A1N(
d_ff3_sign_out), .Y(op_add_subt) );
AOI211XLTS U1690 ( .A0(n1159), .A1(n1215), .B0(n1158), .C0(n1157), .Y(n1162)
);
OAI211XLTS U1691 ( .A0(n1162), .A1(n800), .B0(n1161), .C0(n1160), .Y(n732)
);
OAI21XLTS U1692 ( .A0(n1218), .A1(n1164), .B0(n1185), .Y(n1163) );
AOI21X1TS U1693 ( .A0(n1218), .A1(n1164), .B0(n1163), .Y(n729) );
NAND2X1TS U1694 ( .A(n1167), .B(n1166), .Y(n1165) );
AOI22X1TS U1695 ( .A0(cont_iter_out[0]), .A1(n1165), .B0(n1166), .B1(n1216),
.Y(n728) );
NOR2X1TS U1696 ( .A(n1216), .B(n1166), .Y(n1169) );
OAI21XLTS U1697 ( .A0(cont_iter_out[1]), .A1(n1169), .B0(n1167), .Y(n1168)
);
AOI21X1TS U1698 ( .A0(cont_iter_out[1]), .A1(n1169), .B0(n1168), .Y(n727) );
OAI32X1TS U1699 ( .A0(n1173), .A1(n1172), .A2(n1231), .B0(n1171), .B1(n1170),
.Y(n686) );
CLKBUFX3TS U1700 ( .A(n1174), .Y(n1178) );
OAI2BB2XLTS U1701 ( .B0(n1175), .B1(n1243), .A0N(n1178), .A1N(
result_add_subt[5]), .Y(n647) );
OAI2BB2XLTS U1702 ( .B0(n1175), .B1(n1244), .A0N(n1178), .A1N(
result_add_subt[6]), .Y(n646) );
OAI2BB2XLTS U1703 ( .B0(n1175), .B1(n1245), .A0N(n1178), .A1N(
result_add_subt[7]), .Y(n645) );
OAI2BB2XLTS U1704 ( .B0(n1175), .B1(n1246), .A0N(n1176), .A1N(
result_add_subt[8]), .Y(n644) );
OAI2BB2XLTS U1705 ( .B0(n1175), .B1(n1247), .A0N(n1178), .A1N(
result_add_subt[9]), .Y(n643) );
OAI2BB2XLTS U1706 ( .B0(n1175), .B1(n1248), .A0N(n1176), .A1N(
result_add_subt[10]), .Y(n642) );
OAI2BB2XLTS U1707 ( .B0(n1177), .B1(n1249), .A0N(n1176), .A1N(
result_add_subt[11]), .Y(n641) );
OAI2BB2XLTS U1708 ( .B0(n1177), .B1(n1250), .A0N(n1176), .A1N(
result_add_subt[12]), .Y(n640) );
OAI2BB2XLTS U1709 ( .B0(n1177), .B1(n1251), .A0N(n1176), .A1N(
result_add_subt[13]), .Y(n639) );
OAI2BB2XLTS U1710 ( .B0(n1177), .B1(n1252), .A0N(n1176), .A1N(
result_add_subt[14]), .Y(n638) );
OAI2BB2XLTS U1711 ( .B0(n1175), .B1(n1253), .A0N(n1178), .A1N(
result_add_subt[15]), .Y(n637) );
OAI2BB2XLTS U1712 ( .B0(n1177), .B1(n1254), .A0N(n1176), .A1N(
result_add_subt[16]), .Y(n636) );
OAI2BB2XLTS U1713 ( .B0(n1177), .B1(n1255), .A0N(n1176), .A1N(
result_add_subt[17]), .Y(n635) );
OAI2BB2XLTS U1714 ( .B0(n1177), .B1(n1256), .A0N(n1178), .A1N(
result_add_subt[18]), .Y(n634) );
OAI2BB2XLTS U1715 ( .B0(n1177), .B1(n1257), .A0N(n1178), .A1N(
result_add_subt[19]), .Y(n633) );
OAI2BB2XLTS U1716 ( .B0(n1177), .B1(n1220), .A0N(n1178), .A1N(
result_add_subt[20]), .Y(n632) );
OAI2BB2XLTS U1717 ( .B0(n1179), .B1(n1221), .A0N(n1178), .A1N(
result_add_subt[22]), .Y(n630) );
OAI2BB2XLTS U1718 ( .B0(n1179), .B1(n1206), .A0N(n1178), .A1N(
result_add_subt[23]), .Y(n629) );
OAI211X1TS U1719 ( .A0(n1180), .A1(cont_iter_out[2]), .B0(n1188), .C0(n1189),
.Y(n1187) );
OAI2BB1X1TS U1720 ( .A0N(d_ff3_LUT_out[3]), .A1N(n1192), .B0(n1187), .Y(n521) );
OA22X1TS U1721 ( .A0(n1183), .A1(d_ff3_LUT_out[4]), .B0(n1182), .B1(n1181),
.Y(n520) );
OAI2BB1X1TS U1722 ( .A0N(d_ff3_LUT_out[10]), .A1N(n1192), .B0(n1184), .Y(
n514) );
AOI22X1TS U1723 ( .A0(n1205), .A1(n1186), .B0(n1235), .B1(n1185), .Y(n512)
);
OAI2BB1X1TS U1724 ( .A0N(d_ff3_LUT_out[15]), .A1N(n1192), .B0(n1190), .Y(
n509) );
OAI2BB1X1TS U1725 ( .A0N(d_ff3_LUT_out[16]), .A1N(n1192), .B0(n1187), .Y(
n508) );
OAI2BB1X1TS U1726 ( .A0N(d_ff3_LUT_out[17]), .A1N(n1192), .B0(n1190), .Y(
n507) );
NAND2X1TS U1727 ( .A(n1189), .B(n1188), .Y(n1191) );
OAI2BB1X1TS U1728 ( .A0N(d_ff3_LUT_out[19]), .A1N(n1192), .B0(n1191), .Y(
n505) );
OAI2BB1X1TS U1729 ( .A0N(d_ff3_LUT_out[20]), .A1N(n1192), .B0(n1190), .Y(
n504) );
OAI2BB1X1TS U1730 ( .A0N(d_ff3_LUT_out[22]), .A1N(n1192), .B0(n1191), .Y(
n502) );
OAI22X1TS U1731 ( .A0(n1198), .A1(n1229), .B0(n1206), .B1(n1194), .Y(n417)
);
OAI22X1TS U1732 ( .A0(n1193), .A1(n1226), .B0(n1207), .B1(n1195), .Y(n416)
);
OAI22X1TS U1733 ( .A0(n1198), .A1(n1233), .B0(n1208), .B1(n1194), .Y(n413)
);
OAI22X1TS U1734 ( .A0(n1200), .A1(n1230), .B0(n1209), .B1(n1195), .Y(n412)
);
OAI22X1TS U1735 ( .A0(n1200), .A1(n1234), .B0(n1210), .B1(n1194), .Y(n411)
);
OAI22X1TS U1736 ( .A0(n1200), .A1(n1232), .B0(n1219), .B1(n1195), .Y(n410)
);
OA22X1TS U1737 ( .A0(n1198), .A1(d_ff2_X[5]), .B0(d_ff_Xn[5]), .B1(n1196),
.Y(n389) );
OA22X1TS U1738 ( .A0(n1198), .A1(d_ff2_X[7]), .B0(d_ff_Xn[7]), .B1(n1196),
.Y(n385) );
OA22X1TS U1739 ( .A0(n1198), .A1(d_ff2_X[10]), .B0(d_ff_Xn[10]), .B1(n1196),
.Y(n379) );
OA22X1TS U1740 ( .A0(n1198), .A1(d_ff2_X[12]), .B0(d_ff_Xn[12]), .B1(n1197),
.Y(n375) );
OA22X1TS U1741 ( .A0(n1200), .A1(d_ff2_X[27]), .B0(d_ff_Xn[27]), .B1(n1199),
.Y(n349) );
AOI21X1TS U1742 ( .A0(d_ff2_X[29]), .A1(n1202), .B0(n1201), .Y(n1204) );
AOI22X1TS U1743 ( .A0(n1205), .A1(n1204), .B0(n1236), .B1(n1203), .Y(n339)
);
initial $sdf_annotate("CORDIC_Arch2v1_ASIC_fpu_syn_constraints_noclk.tcl_syn.sdf");
endmodule |
module pcie3_7x_0_gtx_cpllpd_ovrd (
input i_ibufds_gte2,
output o_cpllpd_ovrd,
output o_cpllreset_ovrd
);
(* equivalent_register_removal="no" *) reg [95:0] cpllpd_wait = 96'hFFFFFFFFFFFFFFFFFFFFFFFF;
(* equivalent_register_removal="no" *) reg [127:0] cpllreset_wait = 128'h000000000000000000000000000000FF;
always @(posedge i_ibufds_gte2)
begin
cpllpd_wait <= {cpllpd_wait[94:0], 1'b0};
cpllreset_wait <= {cpllreset_wait[126:0], 1'b0};
end
assign o_cpllpd_ovrd = cpllpd_wait[95];
assign o_cpllreset_ovrd = cpllreset_wait[127];
endmodule |
module sky130_fd_sc_lp__a22oi (
Y ,
A1 ,
A2 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire nand0_out ;
wire nand1_out ;
wire and0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
nand nand0 (nand0_out , A2, A1 );
nand nand1 (nand1_out , B2, B1 );
and and0 (and0_out_Y , nand0_out, nand1_out );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, and0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule |
module sky130_fd_sc_hs__bufinv (
Y,
A
);
output Y;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule |
module alu(
output reg [31:0] Z,
input [31:0] A,
input [31:0] B,
input [5:0] ALUFun,
input Sign
);
wire zero, overflow, negative;
wire [31:0] adder_out, comparer_out, logicer_out, shifter_out;
adder adder1(.Z (zero),
.V (overflow),
.N (negative),
.dout(adder_out),
.A (A),
.B (B),
.ctrl(ALUFun[0]),
.Sign(Sign));
comparer comparer1(.dout(comparer_out),
.Z (zero),
.V (overflow),
.N (negative),
.ctrl(ALUFun[3:1]));
logicer logicer1(.dout(logicer_out),
.A (A),
.B (B),
.ctrl(ALUFun[3:0]));
shifter shifter1(.dout(shifter_out),
.A (A),
.B (B),
.ctrl(ALUFun[1:0]));
always @(*) begin
case (ALUFun[5:4])
2'b00: Z = adder_out;
2'b11: Z = comparer_out;
2'b01: Z = logicer_out;
2'b10: Z = shifter_out;
default: Z = 0;
endcase
end
endmodule |
module sky130_fd_sc_ms__o22ai (
//# {{data|Data Signals}}
input A1 ,
input A2 ,
input B1 ,
input B2 ,
output Y ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule |
module FuncionActivacion #(parameter Width = 32, ConLimitador=0,Magnitud = 7, Precision = 24, Signo = 1, A00= 0,
A01= 1, A02 = 2, A03 = 3, A04 = 4, A05 = 5, A06 = 6, A07 = 7, A08 = 8, A09 = 9,
A10= 10, A11= 11, A12 = 12, A13 = 13, A14 = 14, A15 = 15, A16 = 16, A17 = 17, A18 = 18, A19 = 19,
A20= 20, A21= 21,A22 = 22, A23 = 23, A24 = 24, A25 = 25, A26 = 26, A27 = 27, A28 = 28, A29 = 29,
A30 = 30, M01= 1,
M02 = 2, M03 = 3, M04 = 4, M05 = 5, M06 = 6, M07 = 7, M08 = 8, M09 = 9,
M10= 10, M11= 11, M12 = 12, M13 = 13, M14 = 14, M15 = 15, M16 = 16, M17 = 17, M18 = 18, M19 = 19,
M20= 20, M21= 21,M22 = 22, M23 = 23, M24 = 24, M25 = 25, M26 = 26, M27 = 27, M28 = 28, M29 = 29,
M30 = 30,B01= 1,
B02 = 2, B03 = 3, B04 = 4, B05 = 5, B06 = 6, B07 = 7, B08 = 8, B09 = 9,
B10= 10, B11= 11, B12 = 12, B13 = 13, B14 = 14, B15 = 15, B16 = 16, B17 = 17, B18 = 18, B19 = 19,
B20= 20, B21= 21,B22 = 22, B23 = 23, B24 = 24, B25 = 25, B26 = 26, B27 = 27, B28 = 28, B29 = 29,
B30 = 30)
(Entrada,Enable,Error,Salida);
input signed [Width-1:0] Entrada;
input Enable;
output Error;
output signed [Width-1:0] Salida;
wire [4:0] SELMUX;
wire signed [Width-1:0] M,B,OutALU;
Comparador #( .Width(Width) , .A00(A00), .A01(A01),.A02(A02), .A03(A03), .A04(A04), .A05(A05),
.A06(A06), .A07(A07), .A08(A08), .A09(A09),.A10(A10), .A11(A11), .A12(A12), .A13(A13), .A14(A14),
.A15(A15), .A16(A16), .A17(A17), .A18(A18), .A19(A19),.A20(A20), .A21(A21),.A22(A22), .A23(A23),
.A24(A24), .A25(A25), .A26(A26), .A27(A27), .A28(A28), .A29(A29), .A30(A30))
COmparadorcopia (
.A(Entrada),
.OutComp(SELMUX)
);
multiplexor32a1 #(.Width(Width)) multiplexor32a1coeffPendientes (
.coeff00(32'sb00000000000000000000000000000000),
.coeff01(M01),
.coeff02(M02),
.coeff03(M03),
.coeff04(M04),
.coeff05(M05),
.coeff06(M06),
.coeff07(M07),
.coeff08(M08),
.coeff09(M09),
.coeff10(M10),
.coeff11(M11),
.coeff12(M12),
.coeff13(M13),
.coeff14(M14),
.coeff15(M15),
.coeff16(M16),
.coeff17(M17),
.coeff18(M18),
.coeff19(M19),
.coeff20(M20),
.coeff21(M21),
.coeff22(M22),
.coeff23(M23),
.coeff24(M24),
.coeff25(M25),
.coeff26(M26),
.coeff27(M27),
.coeff28(M28),
.coeff29(M29),
.coeff30(M30),
.coeff31(32'sb00000000000000000000000000000000),
.SEL(SELMUX),
.outMUX(M)
);
multiplexor32a1 #(.Width(Width)) multiplexor32a1coeffInterseccion (
.coeff00(32'sb00000000000000000000000000000000),
.coeff01(B01),
.coeff02(B02),
.coeff03(B03),
.coeff04(B04),
.coeff05(B05),
.coeff06(B06),
.coeff07(B07),
.coeff08(B08),
.coeff09(B09),
.coeff10(B10),
.coeff11(B11),
.coeff12(B12),
.coeff13(B13),
.coeff14(B14),
.coeff15(B15),
.coeff16(B16),
.coeff17(B17),
.coeff18(B18),
.coeff19(B19),
.coeff20(B20),
.coeff21(B21),
.coeff22(B22),
.coeff23(B23),
.coeff24(B24),
.coeff25(B25),
.coeff26(B26),
.coeff27(B27),
.coeff28(B28),
.coeff29(B29),
.coeff30(B30),
.coeff31(32'sb00000001000000000000000000000000),
.SEL(SELMUX),
.outMUX(B)
);
ALUfuncionActivacion #(.Width(Width), .Magnitud(Magnitud), .Precision(Precision),.Signo(Signo))
ALUfuncionActivacioncopia (
.SELMUX(SELMUX),
.Enable(Enable),
.M(M),
.B(B),
.In(Entrada),
.Out(OutALU),
.Error(Error)
);
generate
if (ConLimitador) begin: CodigoConLimitadoralaSalidaEntre0y1
LimitadorSalidaFuctActivacion #(.Width(Width)) LimitadorSalidaFuctActivacion1 (
.inData(OutALU),
.OutData(Salida)
);
end else begin: CodigoSinLimitadoralaSalidaEntre0y1
assign Salida = OutALU;
end
endgenerate
endmodule |
module wasca_nios2_gen2_0_cpu_test_bench (
// inputs:
D_iw,
D_iw_op,
D_iw_opx,
D_valid,
E_valid,
F_pcb,
F_valid,
R_ctrl_ld,
R_ctrl_ld_non_io,
R_dst_regnum,
R_wr_dst_reg,
W_valid,
W_vinst,
W_wr_data,
av_ld_data_aligned_unfiltered,
clk,
d_address,
d_byteenable,
d_read,
d_write,
i_address,
i_read,
i_readdata,
i_waitrequest,
reset_n,
// outputs:
av_ld_data_aligned_filtered,
test_has_ended
)
;
output [ 31: 0] av_ld_data_aligned_filtered;
output test_has_ended;
input [ 31: 0] D_iw;
input [ 5: 0] D_iw_op;
input [ 5: 0] D_iw_opx;
input D_valid;
input E_valid;
input [ 21: 0] F_pcb;
input F_valid;
input R_ctrl_ld;
input R_ctrl_ld_non_io;
input [ 4: 0] R_dst_regnum;
input R_wr_dst_reg;
input W_valid;
input [ 71: 0] W_vinst;
input [ 31: 0] W_wr_data;
input [ 31: 0] av_ld_data_aligned_unfiltered;
input clk;
input [ 26: 0] d_address;
input [ 3: 0] d_byteenable;
input d_read;
input d_write;
input [ 21: 0] i_address;
input i_read;
input [ 31: 0] i_readdata;
input i_waitrequest;
input reset_n;
wire D_is_opx_inst;
wire D_op_add;
wire D_op_addi;
wire D_op_and;
wire D_op_andhi;
wire D_op_andi;
wire D_op_beq;
wire D_op_bge;
wire D_op_bgeu;
wire D_op_blt;
wire D_op_bltu;
wire D_op_bne;
wire D_op_br;
wire D_op_break;
wire D_op_bret;
wire D_op_call;
wire D_op_callr;
wire D_op_cmpeq;
wire D_op_cmpeqi;
wire D_op_cmpge;
wire D_op_cmpgei;
wire D_op_cmpgeu;
wire D_op_cmpgeui;
wire D_op_cmplt;
wire D_op_cmplti;
wire D_op_cmpltu;
wire D_op_cmpltui;
wire D_op_cmpne;
wire D_op_cmpnei;
wire D_op_crst;
wire D_op_custom;
wire D_op_div;
wire D_op_divu;
wire D_op_eret;
wire D_op_flushd;
wire D_op_flushda;
wire D_op_flushi;
wire D_op_flushp;
wire D_op_hbreak;
wire D_op_initd;
wire D_op_initda;
wire D_op_initi;
wire D_op_intr;
wire D_op_jmp;
wire D_op_jmpi;
wire D_op_ldb;
wire D_op_ldbio;
wire D_op_ldbu;
wire D_op_ldbuio;
wire D_op_ldh;
wire D_op_ldhio;
wire D_op_ldhu;
wire D_op_ldhuio;
wire D_op_ldl;
wire D_op_ldw;
wire D_op_ldwio;
wire D_op_mul;
wire D_op_muli;
wire D_op_mulxss;
wire D_op_mulxsu;
wire D_op_mulxuu;
wire D_op_nextpc;
wire D_op_nor;
wire D_op_op_rsv02;
wire D_op_op_rsv09;
wire D_op_op_rsv10;
wire D_op_op_rsv17;
wire D_op_op_rsv18;
wire D_op_op_rsv25;
wire D_op_op_rsv26;
wire D_op_op_rsv33;
wire D_op_op_rsv34;
wire D_op_op_rsv41;
wire D_op_op_rsv42;
wire D_op_op_rsv49;
wire D_op_op_rsv57;
wire D_op_op_rsv61;
wire D_op_op_rsv62;
wire D_op_op_rsv63;
wire D_op_opx_rsv00;
wire D_op_opx_rsv10;
wire D_op_opx_rsv15;
wire D_op_opx_rsv17;
wire D_op_opx_rsv21;
wire D_op_opx_rsv25;
wire D_op_opx_rsv33;
wire D_op_opx_rsv34;
wire D_op_opx_rsv35;
wire D_op_opx_rsv42;
wire D_op_opx_rsv43;
wire D_op_opx_rsv44;
wire D_op_opx_rsv47;
wire D_op_opx_rsv50;
wire D_op_opx_rsv51;
wire D_op_opx_rsv55;
wire D_op_opx_rsv56;
wire D_op_opx_rsv60;
wire D_op_opx_rsv63;
wire D_op_or;
wire D_op_orhi;
wire D_op_ori;
wire D_op_rdctl;
wire D_op_rdprs;
wire D_op_ret;
wire D_op_rol;
wire D_op_roli;
wire D_op_ror;
wire D_op_sll;
wire D_op_slli;
wire D_op_sra;
wire D_op_srai;
wire D_op_srl;
wire D_op_srli;
wire D_op_stb;
wire D_op_stbio;
wire D_op_stc;
wire D_op_sth;
wire D_op_sthio;
wire D_op_stw;
wire D_op_stwio;
wire D_op_sub;
wire D_op_sync;
wire D_op_trap;
wire D_op_wrctl;
wire D_op_wrprs;
wire D_op_xor;
wire D_op_xorhi;
wire D_op_xori;
wire [ 31: 0] av_ld_data_aligned_filtered;
wire av_ld_data_aligned_unfiltered_0_is_x;
wire av_ld_data_aligned_unfiltered_10_is_x;
wire av_ld_data_aligned_unfiltered_11_is_x;
wire av_ld_data_aligned_unfiltered_12_is_x;
wire av_ld_data_aligned_unfiltered_13_is_x;
wire av_ld_data_aligned_unfiltered_14_is_x;
wire av_ld_data_aligned_unfiltered_15_is_x;
wire av_ld_data_aligned_unfiltered_16_is_x;
wire av_ld_data_aligned_unfiltered_17_is_x;
wire av_ld_data_aligned_unfiltered_18_is_x;
wire av_ld_data_aligned_unfiltered_19_is_x;
wire av_ld_data_aligned_unfiltered_1_is_x;
wire av_ld_data_aligned_unfiltered_20_is_x;
wire av_ld_data_aligned_unfiltered_21_is_x;
wire av_ld_data_aligned_unfiltered_22_is_x;
wire av_ld_data_aligned_unfiltered_23_is_x;
wire av_ld_data_aligned_unfiltered_24_is_x;
wire av_ld_data_aligned_unfiltered_25_is_x;
wire av_ld_data_aligned_unfiltered_26_is_x;
wire av_ld_data_aligned_unfiltered_27_is_x;
wire av_ld_data_aligned_unfiltered_28_is_x;
wire av_ld_data_aligned_unfiltered_29_is_x;
wire av_ld_data_aligned_unfiltered_2_is_x;
wire av_ld_data_aligned_unfiltered_30_is_x;
wire av_ld_data_aligned_unfiltered_31_is_x;
wire av_ld_data_aligned_unfiltered_3_is_x;
wire av_ld_data_aligned_unfiltered_4_is_x;
wire av_ld_data_aligned_unfiltered_5_is_x;
wire av_ld_data_aligned_unfiltered_6_is_x;
wire av_ld_data_aligned_unfiltered_7_is_x;
wire av_ld_data_aligned_unfiltered_8_is_x;
wire av_ld_data_aligned_unfiltered_9_is_x;
wire test_has_ended;
assign D_op_call = D_iw_op == 0;
assign D_op_jmpi = D_iw_op == 1;
assign D_op_op_rsv02 = D_iw_op == 2;
assign D_op_ldbu = D_iw_op == 3;
assign D_op_addi = D_iw_op == 4;
assign D_op_stb = D_iw_op == 5;
assign D_op_br = D_iw_op == 6;
assign D_op_ldb = D_iw_op == 7;
assign D_op_cmpgei = D_iw_op == 8;
assign D_op_op_rsv09 = D_iw_op == 9;
assign D_op_op_rsv10 = D_iw_op == 10;
assign D_op_ldhu = D_iw_op == 11;
assign D_op_andi = D_iw_op == 12;
assign D_op_sth = D_iw_op == 13;
assign D_op_bge = D_iw_op == 14;
assign D_op_ldh = D_iw_op == 15;
assign D_op_cmplti = D_iw_op == 16;
assign D_op_op_rsv17 = D_iw_op == 17;
assign D_op_op_rsv18 = D_iw_op == 18;
assign D_op_initda = D_iw_op == 19;
assign D_op_ori = D_iw_op == 20;
assign D_op_stw = D_iw_op == 21;
assign D_op_blt = D_iw_op == 22;
assign D_op_ldw = D_iw_op == 23;
assign D_op_cmpnei = D_iw_op == 24;
assign D_op_op_rsv25 = D_iw_op == 25;
assign D_op_op_rsv26 = D_iw_op == 26;
assign D_op_flushda = D_iw_op == 27;
assign D_op_xori = D_iw_op == 28;
assign D_op_stc = D_iw_op == 29;
assign D_op_bne = D_iw_op == 30;
assign D_op_ldl = D_iw_op == 31;
assign D_op_cmpeqi = D_iw_op == 32;
assign D_op_op_rsv33 = D_iw_op == 33;
assign D_op_op_rsv34 = D_iw_op == 34;
assign D_op_ldbuio = D_iw_op == 35;
assign D_op_muli = D_iw_op == 36;
assign D_op_stbio = D_iw_op == 37;
assign D_op_beq = D_iw_op == 38;
assign D_op_ldbio = D_iw_op == 39;
assign D_op_cmpgeui = D_iw_op == 40;
assign D_op_op_rsv41 = D_iw_op == 41;
assign D_op_op_rsv42 = D_iw_op == 42;
assign D_op_ldhuio = D_iw_op == 43;
assign D_op_andhi = D_iw_op == 44;
assign D_op_sthio = D_iw_op == 45;
assign D_op_bgeu = D_iw_op == 46;
assign D_op_ldhio = D_iw_op == 47;
assign D_op_cmpltui = D_iw_op == 48;
assign D_op_op_rsv49 = D_iw_op == 49;
assign D_op_custom = D_iw_op == 50;
assign D_op_initd = D_iw_op == 51;
assign D_op_orhi = D_iw_op == 52;
assign D_op_stwio = D_iw_op == 53;
assign D_op_bltu = D_iw_op == 54;
assign D_op_ldwio = D_iw_op == 55;
assign D_op_rdprs = D_iw_op == 56;
assign D_op_op_rsv57 = D_iw_op == 57;
assign D_op_flushd = D_iw_op == 59;
assign D_op_xorhi = D_iw_op == 60;
assign D_op_op_rsv61 = D_iw_op == 61;
assign D_op_op_rsv62 = D_iw_op == 62;
assign D_op_op_rsv63 = D_iw_op == 63;
assign D_op_opx_rsv00 = (D_iw_opx == 0) & D_is_opx_inst;
assign D_op_eret = (D_iw_opx == 1) & D_is_opx_inst;
assign D_op_roli = (D_iw_opx == 2) & D_is_opx_inst;
assign D_op_rol = (D_iw_opx == 3) & D_is_opx_inst;
assign D_op_flushp = (D_iw_opx == 4) & D_is_opx_inst;
assign D_op_ret = (D_iw_opx == 5) & D_is_opx_inst;
assign D_op_nor = (D_iw_opx == 6) & D_is_opx_inst;
assign D_op_mulxuu = (D_iw_opx == 7) & D_is_opx_inst;
assign D_op_cmpge = (D_iw_opx == 8) & D_is_opx_inst;
assign D_op_bret = (D_iw_opx == 9) & D_is_opx_inst;
assign D_op_opx_rsv10 = (D_iw_opx == 10) & D_is_opx_inst;
assign D_op_ror = (D_iw_opx == 11) & D_is_opx_inst;
assign D_op_flushi = (D_iw_opx == 12) & D_is_opx_inst;
assign D_op_jmp = (D_iw_opx == 13) & D_is_opx_inst;
assign D_op_and = (D_iw_opx == 14) & D_is_opx_inst;
assign D_op_opx_rsv15 = (D_iw_opx == 15) & D_is_opx_inst;
assign D_op_cmplt = (D_iw_opx == 16) & D_is_opx_inst;
assign D_op_opx_rsv17 = (D_iw_opx == 17) & D_is_opx_inst;
assign D_op_slli = (D_iw_opx == 18) & D_is_opx_inst;
assign D_op_sll = (D_iw_opx == 19) & D_is_opx_inst;
assign D_op_wrprs = (D_iw_opx == 20) & D_is_opx_inst;
assign D_op_opx_rsv21 = (D_iw_opx == 21) & D_is_opx_inst;
assign D_op_or = (D_iw_opx == 22) & D_is_opx_inst;
assign D_op_mulxsu = (D_iw_opx == 23) & D_is_opx_inst;
assign D_op_cmpne = (D_iw_opx == 24) & D_is_opx_inst;
assign D_op_opx_rsv25 = (D_iw_opx == 25) & D_is_opx_inst;
assign D_op_srli = (D_iw_opx == 26) & D_is_opx_inst;
assign D_op_srl = (D_iw_opx == 27) & D_is_opx_inst;
assign D_op_nextpc = (D_iw_opx == 28) & D_is_opx_inst;
assign D_op_callr = (D_iw_opx == 29) & D_is_opx_inst;
assign D_op_xor = (D_iw_opx == 30) & D_is_opx_inst;
assign D_op_mulxss = (D_iw_opx == 31) & D_is_opx_inst;
assign D_op_cmpeq = (D_iw_opx == 32) & D_is_opx_inst;
assign D_op_opx_rsv33 = (D_iw_opx == 33) & D_is_opx_inst;
assign D_op_opx_rsv34 = (D_iw_opx == 34) & D_is_opx_inst;
assign D_op_opx_rsv35 = (D_iw_opx == 35) & D_is_opx_inst;
assign D_op_divu = (D_iw_opx == 36) & D_is_opx_inst;
assign D_op_div = (D_iw_opx == 37) & D_is_opx_inst;
assign D_op_rdctl = (D_iw_opx == 38) & D_is_opx_inst;
assign D_op_mul = (D_iw_opx == 39) & D_is_opx_inst;
assign D_op_cmpgeu = (D_iw_opx == 40) & D_is_opx_inst;
assign D_op_initi = (D_iw_opx == 41) & D_is_opx_inst;
assign D_op_opx_rsv42 = (D_iw_opx == 42) & D_is_opx_inst;
assign D_op_opx_rsv43 = (D_iw_opx == 43) & D_is_opx_inst;
assign D_op_opx_rsv44 = (D_iw_opx == 44) & D_is_opx_inst;
assign D_op_trap = (D_iw_opx == 45) & D_is_opx_inst;
assign D_op_wrctl = (D_iw_opx == 46) & D_is_opx_inst;
assign D_op_opx_rsv47 = (D_iw_opx == 47) & D_is_opx_inst;
assign D_op_cmpltu = (D_iw_opx == 48) & D_is_opx_inst;
assign D_op_add = (D_iw_opx == 49) & D_is_opx_inst;
assign D_op_opx_rsv50 = (D_iw_opx == 50) & D_is_opx_inst;
assign D_op_opx_rsv51 = (D_iw_opx == 51) & D_is_opx_inst;
assign D_op_break = (D_iw_opx == 52) & D_is_opx_inst;
assign D_op_hbreak = (D_iw_opx == 53) & D_is_opx_inst;
assign D_op_sync = (D_iw_opx == 54) & D_is_opx_inst;
assign D_op_opx_rsv55 = (D_iw_opx == 55) & D_is_opx_inst;
assign D_op_opx_rsv56 = (D_iw_opx == 56) & D_is_opx_inst;
assign D_op_sub = (D_iw_opx == 57) & D_is_opx_inst;
assign D_op_srai = (D_iw_opx == 58) & D_is_opx_inst;
assign D_op_sra = (D_iw_opx == 59) & D_is_opx_inst;
assign D_op_opx_rsv60 = (D_iw_opx == 60) & D_is_opx_inst;
assign D_op_intr = (D_iw_opx == 61) & D_is_opx_inst;
assign D_op_crst = (D_iw_opx == 62) & D_is_opx_inst;
assign D_op_opx_rsv63 = (D_iw_opx == 63) & D_is_opx_inst;
assign D_is_opx_inst = D_iw_op == 58;
assign test_has_ended = 1'b0;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
//Clearing 'X' data bits
assign av_ld_data_aligned_unfiltered_0_is_x = ^(av_ld_data_aligned_unfiltered[0]) === 1'bx;
assign av_ld_data_aligned_filtered[0] = (av_ld_data_aligned_unfiltered_0_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[0];
assign av_ld_data_aligned_unfiltered_1_is_x = ^(av_ld_data_aligned_unfiltered[1]) === 1'bx;
assign av_ld_data_aligned_filtered[1] = (av_ld_data_aligned_unfiltered_1_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[1];
assign av_ld_data_aligned_unfiltered_2_is_x = ^(av_ld_data_aligned_unfiltered[2]) === 1'bx;
assign av_ld_data_aligned_filtered[2] = (av_ld_data_aligned_unfiltered_2_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[2];
assign av_ld_data_aligned_unfiltered_3_is_x = ^(av_ld_data_aligned_unfiltered[3]) === 1'bx;
assign av_ld_data_aligned_filtered[3] = (av_ld_data_aligned_unfiltered_3_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[3];
assign av_ld_data_aligned_unfiltered_4_is_x = ^(av_ld_data_aligned_unfiltered[4]) === 1'bx;
assign av_ld_data_aligned_filtered[4] = (av_ld_data_aligned_unfiltered_4_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[4];
assign av_ld_data_aligned_unfiltered_5_is_x = ^(av_ld_data_aligned_unfiltered[5]) === 1'bx;
assign av_ld_data_aligned_filtered[5] = (av_ld_data_aligned_unfiltered_5_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[5];
assign av_ld_data_aligned_unfiltered_6_is_x = ^(av_ld_data_aligned_unfiltered[6]) === 1'bx;
assign av_ld_data_aligned_filtered[6] = (av_ld_data_aligned_unfiltered_6_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[6];
assign av_ld_data_aligned_unfiltered_7_is_x = ^(av_ld_data_aligned_unfiltered[7]) === 1'bx;
assign av_ld_data_aligned_filtered[7] = (av_ld_data_aligned_unfiltered_7_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[7];
assign av_ld_data_aligned_unfiltered_8_is_x = ^(av_ld_data_aligned_unfiltered[8]) === 1'bx;
assign av_ld_data_aligned_filtered[8] = (av_ld_data_aligned_unfiltered_8_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[8];
assign av_ld_data_aligned_unfiltered_9_is_x = ^(av_ld_data_aligned_unfiltered[9]) === 1'bx;
assign av_ld_data_aligned_filtered[9] = (av_ld_data_aligned_unfiltered_9_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[9];
assign av_ld_data_aligned_unfiltered_10_is_x = ^(av_ld_data_aligned_unfiltered[10]) === 1'bx;
assign av_ld_data_aligned_filtered[10] = (av_ld_data_aligned_unfiltered_10_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[10];
assign av_ld_data_aligned_unfiltered_11_is_x = ^(av_ld_data_aligned_unfiltered[11]) === 1'bx;
assign av_ld_data_aligned_filtered[11] = (av_ld_data_aligned_unfiltered_11_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[11];
assign av_ld_data_aligned_unfiltered_12_is_x = ^(av_ld_data_aligned_unfiltered[12]) === 1'bx;
assign av_ld_data_aligned_filtered[12] = (av_ld_data_aligned_unfiltered_12_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[12];
assign av_ld_data_aligned_unfiltered_13_is_x = ^(av_ld_data_aligned_unfiltered[13]) === 1'bx;
assign av_ld_data_aligned_filtered[13] = (av_ld_data_aligned_unfiltered_13_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[13];
assign av_ld_data_aligned_unfiltered_14_is_x = ^(av_ld_data_aligned_unfiltered[14]) === 1'bx;
assign av_ld_data_aligned_filtered[14] = (av_ld_data_aligned_unfiltered_14_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[14];
assign av_ld_data_aligned_unfiltered_15_is_x = ^(av_ld_data_aligned_unfiltered[15]) === 1'bx;
assign av_ld_data_aligned_filtered[15] = (av_ld_data_aligned_unfiltered_15_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[15];
assign av_ld_data_aligned_unfiltered_16_is_x = ^(av_ld_data_aligned_unfiltered[16]) === 1'bx;
assign av_ld_data_aligned_filtered[16] = (av_ld_data_aligned_unfiltered_16_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[16];
assign av_ld_data_aligned_unfiltered_17_is_x = ^(av_ld_data_aligned_unfiltered[17]) === 1'bx;
assign av_ld_data_aligned_filtered[17] = (av_ld_data_aligned_unfiltered_17_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[17];
assign av_ld_data_aligned_unfiltered_18_is_x = ^(av_ld_data_aligned_unfiltered[18]) === 1'bx;
assign av_ld_data_aligned_filtered[18] = (av_ld_data_aligned_unfiltered_18_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[18];
assign av_ld_data_aligned_unfiltered_19_is_x = ^(av_ld_data_aligned_unfiltered[19]) === 1'bx;
assign av_ld_data_aligned_filtered[19] = (av_ld_data_aligned_unfiltered_19_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[19];
assign av_ld_data_aligned_unfiltered_20_is_x = ^(av_ld_data_aligned_unfiltered[20]) === 1'bx;
assign av_ld_data_aligned_filtered[20] = (av_ld_data_aligned_unfiltered_20_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[20];
assign av_ld_data_aligned_unfiltered_21_is_x = ^(av_ld_data_aligned_unfiltered[21]) === 1'bx;
assign av_ld_data_aligned_filtered[21] = (av_ld_data_aligned_unfiltered_21_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[21];
assign av_ld_data_aligned_unfiltered_22_is_x = ^(av_ld_data_aligned_unfiltered[22]) === 1'bx;
assign av_ld_data_aligned_filtered[22] = (av_ld_data_aligned_unfiltered_22_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[22];
assign av_ld_data_aligned_unfiltered_23_is_x = ^(av_ld_data_aligned_unfiltered[23]) === 1'bx;
assign av_ld_data_aligned_filtered[23] = (av_ld_data_aligned_unfiltered_23_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[23];
assign av_ld_data_aligned_unfiltered_24_is_x = ^(av_ld_data_aligned_unfiltered[24]) === 1'bx;
assign av_ld_data_aligned_filtered[24] = (av_ld_data_aligned_unfiltered_24_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[24];
assign av_ld_data_aligned_unfiltered_25_is_x = ^(av_ld_data_aligned_unfiltered[25]) === 1'bx;
assign av_ld_data_aligned_filtered[25] = (av_ld_data_aligned_unfiltered_25_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[25];
assign av_ld_data_aligned_unfiltered_26_is_x = ^(av_ld_data_aligned_unfiltered[26]) === 1'bx;
assign av_ld_data_aligned_filtered[26] = (av_ld_data_aligned_unfiltered_26_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[26];
assign av_ld_data_aligned_unfiltered_27_is_x = ^(av_ld_data_aligned_unfiltered[27]) === 1'bx;
assign av_ld_data_aligned_filtered[27] = (av_ld_data_aligned_unfiltered_27_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[27];
assign av_ld_data_aligned_unfiltered_28_is_x = ^(av_ld_data_aligned_unfiltered[28]) === 1'bx;
assign av_ld_data_aligned_filtered[28] = (av_ld_data_aligned_unfiltered_28_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[28];
assign av_ld_data_aligned_unfiltered_29_is_x = ^(av_ld_data_aligned_unfiltered[29]) === 1'bx;
assign av_ld_data_aligned_filtered[29] = (av_ld_data_aligned_unfiltered_29_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[29];
assign av_ld_data_aligned_unfiltered_30_is_x = ^(av_ld_data_aligned_unfiltered[30]) === 1'bx;
assign av_ld_data_aligned_filtered[30] = (av_ld_data_aligned_unfiltered_30_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[30];
assign av_ld_data_aligned_unfiltered_31_is_x = ^(av_ld_data_aligned_unfiltered[31]) === 1'bx;
assign av_ld_data_aligned_filtered[31] = (av_ld_data_aligned_unfiltered_31_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[31];
always @(posedge clk)
begin
if (reset_n)
if (^(F_valid) === 1'bx)
begin
$write("%0d ns: ERROR: wasca_nios2_gen2_0_cpu_test_bench/F_valid is 'x'\n", $time);
$stop;
end
end
always @(posedge clk)
begin
if (reset_n)
if (^(D_valid) === 1'bx)
begin
$write("%0d ns: ERROR: wasca_nios2_gen2_0_cpu_test_bench/D_valid is 'x'\n", $time);
$stop;
end
end
always @(posedge clk)
begin
if (reset_n)
if (^(E_valid) === 1'bx)
begin
$write("%0d ns: ERROR: wasca_nios2_gen2_0_cpu_test_bench/E_valid is 'x'\n", $time);
$stop;
end
end
always @(posedge clk)
begin
if (reset_n)
if (^(W_valid) === 1'bx)
begin
$write("%0d ns: ERROR: wasca_nios2_gen2_0_cpu_test_bench/W_valid is 'x'\n", $time);
$stop;
end
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
end
else if (W_valid)
if (^(R_wr_dst_reg) === 1'bx)
begin
$write("%0d ns: ERROR: wasca_nios2_gen2_0_cpu_test_bench/R_wr_dst_reg is 'x'\n", $time);
$stop;
end
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
end
else if (W_valid & R_wr_dst_reg)
if (^(W_wr_data) === 1'bx)
begin
$write("%0d ns: ERROR: wasca_nios2_gen2_0_cpu_test_bench/W_wr_data is 'x'\n", $time);
$stop;
end
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
end
else if (W_valid & R_wr_dst_reg)
if (^(R_dst_regnum) === 1'bx)
begin
$write("%0d ns: ERROR: wasca_nios2_gen2_0_cpu_test_bench/R_dst_regnum is 'x'\n", $time);
$stop;
end
end
always @(posedge clk)
begin
if (reset_n)
if (^(d_write) === 1'bx)
begin
$write("%0d ns: ERROR: wasca_nios2_gen2_0_cpu_test_bench/d_write is 'x'\n", $time);
$stop;
end
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
end
else if (d_write)
if (^(d_byteenable) === 1'bx)
begin
$write("%0d ns: ERROR: wasca_nios2_gen2_0_cpu_test_bench/d_byteenable is 'x'\n", $time);
$stop;
end
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
end
else if (d_write | d_read)
if (^(d_address) === 1'bx)
begin
$write("%0d ns: ERROR: wasca_nios2_gen2_0_cpu_test_bench/d_address is 'x'\n", $time);
$stop;
end
end
always @(posedge clk)
begin
if (reset_n)
if (^(d_read) === 1'bx)
begin
$write("%0d ns: ERROR: wasca_nios2_gen2_0_cpu_test_bench/d_read is 'x'\n", $time);
$stop;
end
end
always @(posedge clk)
begin
if (reset_n)
if (^(i_read) === 1'bx)
begin
$write("%0d ns: ERROR: wasca_nios2_gen2_0_cpu_test_bench/i_read is 'x'\n", $time);
$stop;
end
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
end
else if (i_read)
if (^(i_address) === 1'bx)
begin
$write("%0d ns: ERROR: wasca_nios2_gen2_0_cpu_test_bench/i_address is 'x'\n", $time);
$stop;
end
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
end
else if (i_read & ~i_waitrequest)
if (^(i_readdata) === 1'bx)
begin
$write("%0d ns: ERROR: wasca_nios2_gen2_0_cpu_test_bench/i_readdata is 'x'\n", $time);
$stop;
end
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
end
else if (W_valid & R_ctrl_ld)
if (^(av_ld_data_aligned_unfiltered) === 1'bx)
begin
$write("%0d ns: WARNING: wasca_nios2_gen2_0_cpu_test_bench/av_ld_data_aligned_unfiltered is 'x'\n", $time);
end
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
end
else if (W_valid & R_wr_dst_reg)
if (^(W_wr_data) === 1'bx)
begin
$write("%0d ns: WARNING: wasca_nios2_gen2_0_cpu_test_bench/W_wr_data is 'x'\n", $time);
end
end
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
//
// assign av_ld_data_aligned_filtered = av_ld_data_aligned_unfiltered;
//
//synthesis read_comments_as_HDL off
endmodule |
module eth_random (MTxClk, Reset, StateJam, StateJam_q, RetryCnt, NibCnt, ByteCnt,
RandomEq0, RandomEqByteCnt);
parameter Tp = 1;
input MTxClk;
input Reset;
input StateJam;
input StateJam_q;
input [3:0] RetryCnt;
input [15:0] NibCnt;
input [9:0] ByteCnt;
output RandomEq0;
output RandomEqByteCnt;
wire Feedback;
reg [9:0] x;
wire [9:0] Random;
reg [9:0] RandomLatched;
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
x[9:0] <= #Tp 0;
else
x[9:0] <= #Tp {x[8:0], Feedback};
end
assign Feedback = ~(x[2] ^ x[9]);
assign Random [0] = x[0];
assign Random [1] = (RetryCnt > 1) ? x[1] : 1'b0;
assign Random [2] = (RetryCnt > 2) ? x[2] : 1'b0;
assign Random [3] = (RetryCnt > 3) ? x[3] : 1'b0;
assign Random [4] = (RetryCnt > 4) ? x[4] : 1'b0;
assign Random [5] = (RetryCnt > 5) ? x[5] : 1'b0;
assign Random [6] = (RetryCnt > 6) ? x[6] : 1'b0;
assign Random [7] = (RetryCnt > 7) ? x[7] : 1'b0;
assign Random [8] = (RetryCnt > 8) ? x[8] : 1'b0;
assign Random [9] = (RetryCnt > 9) ? x[9] : 1'b0;
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
RandomLatched <= #Tp 10'h000;
else
begin
if(StateJam & StateJam_q)
RandomLatched <= #Tp Random;
end
end
// Random Number == 0 IEEE 802.3 page 68. If 0 we go to defer and not to backoff.
assign RandomEq0 = RandomLatched == 10'h0;
assign RandomEqByteCnt = ByteCnt[9:0] == RandomLatched & (&NibCnt[6:0]);
endmodule |
module top();
// Inputs are registered
reg D;
reg RESET;
reg SLEEP_B;
reg KAPWR;
reg VGND;
reg VPWR;
// Outputs are wires
wire Q;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
KAPWR = 1'bX;
RESET = 1'bX;
SLEEP_B = 1'bX;
VGND = 1'bX;
VPWR = 1'bX;
#20 D = 1'b0;
#40 KAPWR = 1'b0;
#60 RESET = 1'b0;
#80 SLEEP_B = 1'b0;
#100 VGND = 1'b0;
#120 VPWR = 1'b0;
#140 D = 1'b1;
#160 KAPWR = 1'b1;
#180 RESET = 1'b1;
#200 SLEEP_B = 1'b1;
#220 VGND = 1'b1;
#240 VPWR = 1'b1;
#260 D = 1'b0;
#280 KAPWR = 1'b0;
#300 RESET = 1'b0;
#320 SLEEP_B = 1'b0;
#340 VGND = 1'b0;
#360 VPWR = 1'b0;
#380 VPWR = 1'b1;
#400 VGND = 1'b1;
#420 SLEEP_B = 1'b1;
#440 RESET = 1'b1;
#460 KAPWR = 1'b1;
#480 D = 1'b1;
#500 VPWR = 1'bx;
#520 VGND = 1'bx;
#540 SLEEP_B = 1'bx;
#560 RESET = 1'bx;
#580 KAPWR = 1'bx;
#600 D = 1'bx;
end
// Create a clock
reg CLK_N;
initial
begin
CLK_N = 1'b0;
end
always
begin
#5 CLK_N = ~CLK_N;
end
sky130_fd_sc_hs__udp_dff$NR_pp$PKG$s dut (.D(D), .RESET(RESET), .SLEEP_B(SLEEP_B), .KAPWR(KAPWR), .VGND(VGND), .VPWR(VPWR), .Q(Q), .CLK_N(CLK_N));
endmodule |
module sky130_fd_sc_hs__o2bb2a (
X ,
A1_N,
A2_N,
B1 ,
B2 ,
VPWR,
VGND
);
// Module ports
output X ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
input VPWR;
input VGND;
// Local signals
wire B2 nand0_out ;
wire B2 or0_out ;
wire and0_out_X ;
wire u_vpwr_vgnd0_out_X;
// Name Output Other arguments
nand nand0 (nand0_out , A2_N, A1_N );
or or0 (or0_out , B2, B1 );
and and0 (and0_out_X , nand0_out, or0_out );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_X, and0_out_X, VPWR, VGND);
buf buf0 (X , u_vpwr_vgnd0_out_X );
endmodule |
module sky130_fd_sc_hdll__and2 (
//# {{data|Data Signals}}
input A,
input B,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule |
module or DMA consumes DWORD
// communication with transport/link/phys layers
// wire phy_rst; // frome phy, as a response to hba_arst || port_arst. It is deasserted when clock is stable
wire [ 1:0] phy_speed; // 0 - not ready, 1..3 - negotiated speed
wire xmit_ok; // FIS transmission acknowledged OK
wire xmit_err; // Error during sending of a FIS
wire syncesc_recv; // These two inputs interrupt transmit
wire pcmd_st_cleared; // bit was cleared by software
wire syncesc_send; // Send sync escape
wire syncesc_send_done; // "SYNC escape until the interface is quiescent..."
wire comreset_send; // Not possible yet?
wire cominit_got;
wire set_offline; // electrically idle
wire x_rdy_collision; // X_RDY/X_RDY collision on interface
wire send_R_OK; // Should it be originated in this layer SM?
wire send_R_ERR;
// additional errors from SATA layers (single-clock pulses):
wire serr_DT; // RWC: Transport state transition error
wire serr_DS; // RWC: Link sequence error
wire serr_DH; // RWC: Handshake Error (i.e. Device got CRC error)
wire serr_DC; // RWC: CRC error in Link layer
wire serr_DB; // RWC: 10B to 8B decode error
wire serr_DW; // RWC: COMMWAKE signal was detected
wire serr_DI; // RWC: PHY Internal Error
// sirq_PRC,
wire serr_EE; // RWC: Internal error (such as elastic buffer overflow or primitive mis-alignment)
wire serr_EP; // RWC: Protocol Error - a violation of SATA protocol detected
wire serr_EC; // RWC: Persistent Communication or Data Integrity Error
wire serr_ET; // RWC: Transient Data Integrity Error (error not recovered by the interface)
wire serr_EM; // RWC: Communication between the device and host was lost but re-established
wire serr_EI; // RWC: Recovered Data integrity Error
// additional control signals for SATA layers
wire [3:0] sctl_ipm; // Interface power management transitions allowed
wire [3:0] sctl_spd; // Interface maximal speed
reg [2:0] nhrst_r;
wire hrst = !nhrst_r[2];
wire debug_link_send_data; // @sata clk - last symbol was data output
wire debug_link_dmatp; // @clk (sata clk) - received CODE_DMATP
wire [FREQ_METER_WIDTH-1:0] xclk_period;
`ifdef USE_DATASCOPE
// Datascope interface (write to memory that can be software-read)
wire datascope_clk;
wire [ADDRESS_BITS-1:0] datascope_waddr;
wire datascope_we;
wire [31:0] datascope_di;
`endif
`ifdef USE_DRP
wire drp_en;
wire drp_we;
wire [14:0] drp_addr;
wire [15:0] drp_di;
wire drp_rdy;
wire [15:0] drp_do;
`endif
wire [31:0] debug_phy;
wire [31:0] debug_link;
always @ (posedge hclk or posedge arst) begin
if (arst) nhrst_r <= 0;
else nhrst_r <= (nhrst_r << 1) | 1;
end
ahci_top #(
.PREFETCH_ALWAYS (PREFETCH_ALWAYS),
// .READ_REG_LATENCY (READ_REG_LATENCY),
// .READ_CT_LATENCY (READ_CT_LATENCY),
.ADDRESS_BITS (ADDRESS_BITS),
.HBA_RESET_BITS (HBA_RESET_BITS),
.RESET_TO_FIRST_ACCESS (RESET_TO_FIRST_ACCESS),
.FREQ_METER_WIDTH (FREQ_METER_WIDTH)
) ahci_top_i (
.aclk (ACLK), // input
.arst (arst), // input
.mclk (sata_clk), // input
.mrst (sata_rst), // input
.hba_arst (hba_arst), // output
.port_arst (port_arst), // output
.port_arst_any (port_arst_any), // port0 async set by software and by arst
.hclk (hclk), // input
.hrst (hrst), // input
.awaddr (AWADDR), // input[31:0]
.awvalid (AWVALID), // input
.awready (AWREADY), // output
.awid (AWID), // input[11:0]
.awlen (AWLEN), // input[3:0]
.awsize (AWSIZE), // input[1:0]
.awburst (AWBURST), // input[1:0]
.wdata (WDATA), // input[31:0]
.wvalid (WVALID), // input
.wready (WREADY), // output
.wid (WID), // input[11:0]
.wlast (WLAST), // input
.wstb (WSTRB), // input[3:0]
.bvalid (BVALID), // output
.bready (BREADY), // input
.bid (BID), // output[11:0]
.bresp (BRESP), // output[1:0]
.araddr (ARADDR), // input[31:0]
.arvalid (ARVALID), // input
.arready (ARREADY), // output
.arid (ARID), // input[11:0]
.arlen (ARLEN), // input[3:0]
.arsize (ARSIZE), // input[1:0]
.arburst (ARBURST), // input[1:0]
.rdata (RDATA), // output[31:0]
.rvalid (RVALID), // output
.rready (RREADY), // input
.rid (RID), // output[11:0]
.rlast (RLAST), // output
.rresp (RRESP), // output[1:0]
.afi_awaddr (afi_awaddr), // output[31:0]
.afi_awvalid (afi_awvalid), // output
.afi_awready (afi_awready), // input
.afi_awid (afi_awid), // output[5:0]
.afi_awlock (afi_awlock), // output[1:0]
.afi_awcache (afi_awcache), // output[3:0]
.afi_awprot (afi_awprot), // output[2:0]
.afi_awlen (afi_awlen), // output[3:0]
.afi_awsize (afi_awsize), // output[1:0]
.afi_awburst (afi_awburst), // output[1:0]
.afi_awqos (afi_awqos), // output[3:0]
.afi_wdata (afi_wdata), // output[63:0]
.afi_wvalid (afi_wvalid), // output
.afi_wready (afi_wready), // input
.afi_wid (afi_wid), // output[5:0]
.afi_wlast (afi_wlast), // output
.afi_wstrb (afi_wstrb), // output[7:0]
.afi_bvalid (afi_bvalid), // input
.afi_bready (afi_bready), // output
.afi_bid (afi_bid), // input[5:0]
.afi_bresp (afi_bresp), // input[1:0]
.afi_wcount (afi_wcount), // input[7:0]
.afi_wacount (afi_wacount), // input[5:0]
.afi_wrissuecap1en (afi_wrissuecap1en), // output
.afi_araddr (afi_araddr), // output[31:0]
.afi_arvalid (afi_arvalid), // output
.afi_arready (afi_arready), // input
.afi_arid (afi_arid), // output[5:0]
.afi_arlock (afi_arlock), // output[1:0]
.afi_arcache (afi_arcache), // output[3:0]
.afi_arprot (afi_arprot), // output[2:0]
.afi_arlen (afi_arlen), // output[3:0]
.afi_arsize (afi_arsize), // output[1:0]
.afi_arburst (afi_arburst), // output[1:0]
.afi_arqos (afi_arqos), // output[3:0]
.afi_rdata (afi_rdata), // input[63:0]
.afi_rvalid (afi_rvalid), // input
.afi_rready (afi_rready), // output
.afi_rid (afi_rid), // input[5:0]
.afi_rlast (afi_rlast), // input
.afi_rresp (afi_rresp), // input[1:0]
.afi_rcount (afi_rcount), // input[7:0]
.afi_racount (afi_racount), // input[2:0]
.afi_rdissuecap1en (afi_rdissuecap1en), // output
.h2d_data (h2d_data), // output[31:0]
.h2d_type (h2d_type), // output[1:0]
.h2d_valid (h2d_valid), // output
.h2d_ready (h2d_ready), // input
.d2h_data (d2h_data), // input[31:0]
.d2h_type (d2h_type), // input[1:0]
.d2h_valid (d2h_valid), // input
.d2h_many (d2h_many), // input
.d2h_ready (d2h_ready), // output
.phy_ready (phy_speed), // input[1:0]
.xmit_ok (xmit_ok), // input
.xmit_err (xmit_err), // input
.syncesc_recv (syncesc_recv), // input
.pcmd_st_cleared (pcmd_st_cleared), // output
.syncesc_send (syncesc_send), // output
.syncesc_send_done (syncesc_send_done), // input
.comreset_send (comreset_send), // output
.cominit_got (cominit_got), // input
.set_offline (set_offline), // output
.x_rdy_collision (x_rdy_collision), // input
.send_R_OK (send_R_OK), // output
.send_R_ERR (send_R_ERR), // output
.serr_DT (serr_DT), // input
.serr_DS (serr_DS), // input
.serr_DH (serr_DH), // input
.serr_DC (serr_DC), // input
.serr_DB (serr_DB), // input
.serr_DW (serr_DW), // input
.serr_DI (serr_DI), // input
.serr_EE (serr_EE), // input
.serr_EP (serr_EP), // input
.serr_EC (serr_EC), // input
.serr_ET (serr_ET), // input
.serr_EM (serr_EM), // input
.serr_EI (serr_EI), // input
.sctl_ipm (sctl_ipm), // output[3:0]
.sctl_spd (sctl_spd), // output[3:0]
.irq (irq), // output
.debug_link_send_data (debug_link_send_data), // input @posedge sata_clk - last symbol was data output (to count sent out)
.debug_link_dmatp (debug_link_dmatp), // link received DMATp from device
`ifdef USE_DATASCOPE
.datascope1_clk (datascope_clk), // input
.datascope1_waddr (datascope_waddr), // input[9:0]
.datascope1_we (datascope_we), // input
.datascope1_di (datascope_di), // input[31:0]
`endif
`ifdef USE_DRP
.drp_en (drp_en), // output reg
.drp_we (drp_we), // output reg
.drp_addr (drp_addr), // output[14:0] reg
.drp_di (drp_di), // output[15:0] reg
.drp_rdy (drp_rdy), // input
.drp_do (drp_do), // input[15:0]
`endif
.xclk_period (xclk_period), // input[11:0]
.debug_in_phy (debug_phy), // input[31:0]
.debug_in_link (debug_link) // input[31:0]
);
ahci_sata_layers #(
`ifdef USE_DATASCOPE
.ADDRESS_BITS (ADDRESS_BITS), // for datascope
.DATASCOPE_START_BIT (DATASCOPE_START_BIT), // bit of DRP "other_control" to start recording after 0->1 (needs DRP)
.DATASCOPE_POST_MEAS (DATASCOPE_POST_MEAS), // number of measurements to perform after event
`endif
.BITS_TO_START_XMIT (BITS_TO_START_XMIT),
.DATA_BYTE_WIDTH (DATA_BYTE_WIDTH),
.ELASTIC_DEPTH (ELASTIC_DEPTH),
.ELASTIC_OFFSET (ELASTIC_OFFSET),
.FREQ_METER_WIDTH (FREQ_METER_WIDTH)
) ahci_sata_layers_i (
.exrst (exrst), // input
.reliable_clk (reliable_clk), // input
.rst (sata_rst), // output
.clk (sata_clk), // output
.h2d_data (h2d_data), // input[31:0]
.h2d_mask (2'h3), //h2d_mask), // input[1:0]
.h2d_type (h2d_type), // input[1:0]
.h2d_valid (h2d_valid), // input
.h2d_ready (h2d_ready), // output
.d2h_data (d2h_data), // output[31:0]
.d2h_mask (), // 2h_mask), // output[1:0]
.d2h_type (d2h_type), // output[1:0]
.d2h_valid (d2h_valid), // output
.d2h_many (d2h_many), // output
.d2h_ready (d2h_ready), // input
.phy_speed (phy_speed), // output[1:0]
.gtx_ready(), // output
.xmit_ok (xmit_ok), // output
.xmit_err (xmit_err), // output
.x_rdy_collision (x_rdy_collision), // output
.syncesc_recv (syncesc_recv), // output
.pcmd_st_cleared (pcmd_st_cleared), // input
.syncesc_send (syncesc_send), // input
.syncesc_send_done (syncesc_send_done), // output
.comreset_send (comreset_send), // input
.cominit_got (cominit_got), // output
.set_offline (set_offline), // input
.send_R_OK (send_R_OK), // input
.send_R_ERR (send_R_ERR), // input
.serr_DT (serr_DT), // output
.serr_DS (serr_DS), // output
.serr_DH (serr_DH), // output
.serr_DC (serr_DC), // output
.serr_DB (serr_DB), // output
.serr_DW (serr_DW), // output
.serr_DI (serr_DI), // output
.serr_EE (serr_EE), // output
.serr_EP (serr_EP), // output
.serr_EC (serr_EC), // output
.serr_ET (serr_ET), // output
.serr_EM (serr_EM), // output
.serr_EI (serr_EI), // output
.sctl_ipm (sctl_ipm), // input[3:0]
.sctl_spd (sctl_spd), // input[3:0]
.extclk_p (EXTCLK_P), // input wire
.extclk_n (EXTCLK_N), // input wire
.txp_out (TXP), // output wire
.txn_out (TXN), // output wire
.rxp_in (RXP), // input wire
.rxn_in (RXN), // input wire
.debug_is_data (debug_link_send_data), //output @clk (sata clk) - last symbol was data output
.debug_dmatp (debug_link_dmatp), // @clk (sata clk) - received CODE_DMATP
`ifdef USE_DATASCOPE
.datascope_clk (datascope_clk), // output
.datascope_waddr (datascope_waddr), // output[9:0]
.datascope_we (datascope_we), // output
.datascope_di (datascope_di), // output[31:0]
`endif
`ifdef USE_DRP
.drp_rst (arst), // input
.drp_clk (ACLK), // input
.drp_en (drp_en), // input
.drp_we (drp_we), // input
.drp_addr (drp_addr), // input[14:0]
.drp_di (drp_di), // input[15:0]
.drp_rdy (drp_rdy), // output
.drp_do (drp_do), // output[15:0]
`endif
.xclk_period (xclk_period), // output[11:0]
.debug_phy (debug_phy), // output[31:0]
.debug_link (debug_link) // output[31:0]
,.hclk(hclk)
);
endmodule |
module fmlarb #(
parameter fml_depth = 26,
parameter fml_width = 32
) (
input sys_clk,
input sys_rst,
/* Interface 0 has higher priority than the others */
input [fml_depth-1:0] m0_adr,
input m0_stb,
input m0_we,
output m0_ack,
input [fml_width/8-1:0] m0_sel,
input [fml_width-1:0] m0_di,
output [fml_width-1:0] m0_do,
input [fml_depth-1:0] m1_adr,
input m1_stb,
input m1_we,
output m1_ack,
input [fml_width/8-1:0] m1_sel,
input [fml_width-1:0] m1_di,
output [fml_width-1:0] m1_do,
input [fml_depth-1:0] m2_adr,
input m2_stb,
input m2_we,
output m2_ack,
input [fml_width/8-1:0] m2_sel,
input [fml_width-1:0] m2_di,
output [fml_width-1:0] m2_do,
input [fml_depth-1:0] m3_adr,
input m3_stb,
input m3_we,
output m3_ack,
input [fml_width/8-1:0] m3_sel,
input [fml_width-1:0] m3_di,
output [fml_width-1:0] m3_do,
input [fml_depth-1:0] m4_adr,
input m4_stb,
input m4_we,
output m4_ack,
input [fml_width/8-1:0] m4_sel,
input [fml_width-1:0] m4_di,
output [fml_width-1:0] m4_do,
input [fml_depth-1:0] m5_adr,
input m5_stb,
input m5_we,
output m5_ack,
input [fml_width/8-1:0] m5_sel,
input [fml_width-1:0] m5_di,
output [fml_width-1:0] m5_do,
output reg [fml_depth-1:0] s_adr,
output reg s_stb,
output reg s_we,
input s_eack,
output reg [fml_width/8-1:0] s_sel,
input [fml_width-1:0] s_di,
output reg [fml_width-1:0] s_do
);
assign m0_do = s_di;
assign m1_do = s_di;
assign m2_do = s_di;
assign m3_do = s_di;
assign m4_do = s_di;
assign m5_do = s_di;
wire m0_stbm;
wire m1_stbm;
wire m2_stbm;
wire m3_stbm;
wire m4_stbm;
wire m5_stbm;
reg [2:0] master;
reg [2:0] next_master;
always @(posedge sys_clk) begin
if(sys_rst)
master <= 3'd0;
else
master <= next_master;
end
/* Decide the next master */
always @(*) begin
/* By default keep our current master */
next_master = master;
case(master)
3'd0: if(~m0_stbm | s_eack) begin
if(m0_stbm | m0_stb) next_master = 3'd0;
else if(m1_stbm) next_master = 3'd1;
else if(m2_stbm) next_master = 3'd2;
else if(m3_stbm) next_master = 3'd3;
else if(m4_stbm) next_master = 3'd4;
else if(m5_stbm) next_master = 3'd5;
end
3'd1: if(~m1_stbm | s_eack) begin
if(m0_stbm) next_master = 3'd0;
else if(m3_stbm) next_master = 3'd3;
else if(m4_stbm) next_master = 3'd4;
else if(m5_stbm) next_master = 3'd5;
else if(m2_stbm) next_master = 3'd2;
end
3'd2: if(~m2_stbm | s_eack) begin
if(m0_stbm) next_master = 3'd0;
else if(m3_stbm) next_master = 3'd3;
else if(m4_stbm) next_master = 3'd4;
else if(m5_stbm) next_master = 3'd5;
else if(m1_stbm) next_master = 3'd1;
end
3'd3: if(~m3_stbm | s_eack) begin
if(m0_stbm) next_master = 3'd0;
else if(m4_stbm) next_master = 3'd4;
else if(m5_stbm) next_master = 3'd5;
else if(m1_stbm) next_master = 3'd1;
else if(m2_stbm) next_master = 3'd2;
end
3'd4: if(~m4_stbm | s_eack) begin
if(m0_stbm) next_master = 3'd0;
else if(m5_stbm) next_master = 3'd5;
else if(m1_stbm) next_master = 3'd1;
else if(m2_stbm) next_master = 3'd2;
else if(m3_stbm) next_master = 3'd3;
end
default: if(~m5_stbm | s_eack) begin // 3'd5
if(m0_stbm) next_master = 3'd0;
else if(m1_stbm) next_master = 3'd1;
else if(m2_stbm) next_master = 3'd2;
else if(m3_stbm) next_master = 3'd3;
else if(m4_stbm) next_master = 3'd4;
end
endcase
end
/* Mux control signals */
always @(*) begin
case(master)
3'd0: begin
s_adr = m0_adr;
s_stb = m0_stbm;
s_we = m0_we;
end
3'd1: begin
s_adr = m1_adr;
s_stb = m1_stbm;
s_we = m1_we;
end
3'd2: begin
s_adr = m2_adr;
s_stb = m2_stbm;
s_we = m2_we;
end
3'd3: begin
s_adr = m3_adr;
s_stb = m3_stbm;
s_we = m3_we;
end
3'd4: begin
s_adr = m4_adr;
s_stb = m4_stbm;
s_we = m4_we;
end
default: begin // 3'd5
s_adr = m5_adr;
s_stb = m5_stbm;
s_we = m5_we;
end
endcase
end
/* Generate delayed ack signals and masked strobes */
fmlarb_dack dack0(.sys_clk(sys_clk), .sys_rst(sys_rst),
.stb(m0_stb), .eack((master == 3'd0) & s_eack), .we(m0_we),
.stbm(m0_stbm), .ack(m0_ack));
fmlarb_dack dack1(.sys_clk(sys_clk), .sys_rst(sys_rst),
.stb(m1_stb), .eack((master == 3'd1) & s_eack), .we(m1_we),
.stbm(m1_stbm), .ack(m1_ack));
fmlarb_dack dack2(.sys_clk(sys_clk), .sys_rst(sys_rst),
.stb(m2_stb), .eack((master == 3'd2) & s_eack), .we(m2_we),
.stbm(m2_stbm), .ack(m2_ack));
fmlarb_dack dack3(.sys_clk(sys_clk), .sys_rst(sys_rst),
.stb(m3_stb), .eack((master == 3'd3) & s_eack), .we(m3_we),
.stbm(m3_stbm), .ack(m3_ack));
fmlarb_dack dack4(.sys_clk(sys_clk), .sys_rst(sys_rst),
.stb(m4_stb), .eack((master == 3'd4) & s_eack), .we(m4_we),
.stbm(m4_stbm), .ack(m4_ack));
fmlarb_dack dack5(.sys_clk(sys_clk), .sys_rst(sys_rst),
.stb(m5_stb), .eack((master == 3'd5) & s_eack), .we(m5_we),
.stbm(m5_stbm), .ack(m5_ack));
/* Mux data write signals */
reg [2:0] wmaster;
always @(posedge sys_clk) begin
if(sys_rst)
wmaster <= 3'd0;
else if(s_we & s_eack)
wmaster <= master;
end
always @(*) begin
case(wmaster)
3'd0: begin
s_do = m0_di;
s_sel = m0_sel;
end
3'd1: begin
s_do = m1_di;
s_sel = m1_sel;
end
3'd2: begin
s_do = m2_di;
s_sel = m2_sel;
end
3'd3: begin
s_do = m3_di;
s_sel = m3_sel;
end
3'd4: begin
s_do = m4_di;
s_sel = m4_sel;
end
default: begin // 3'd5
s_do = m5_di;
s_sel = m5_sel;
end
endcase
end
endmodule |
module user_io(
input SPI_CLK,
input SPI_SS_IO,
output reg SPI_MISO,
input SPI_MOSI,
input [7:0] CORE_TYPE,
output [7:0] JOY0,
output [7:0] JOY1,
output [2:0] MOUSE_BUTTONS,
output KBD_MOUSE_STROBE,
output KMS_LEVEL,
output [1:0] KBD_MOUSE_TYPE,
output [7:0] KBD_MOUSE_DATA,
output [1:0] BUTTONS,
output [1:0] SWITCHES,
output [3:0] CONF
);
reg [6:0] sbuf;
reg [7:0] cmd;
reg [5:0] cnt;
reg [7:0] joystick0;
reg [7:0] joystick1;
reg [7:0] but_sw;
reg kbd_mouse_strobe;
reg kbd_mouse_strobe_level;
reg [1:0] kbd_mouse_type;
reg [7:0] kbd_mouse_data;
reg [2:0] mouse_buttons;
assign JOY0 = joystick0;
assign JOY1 = joystick1;
assign KBD_MOUSE_DATA = kbd_mouse_data; // 8 bit movement data
assign KBD_MOUSE_TYPE = kbd_mouse_type; // 0=mouse x,1=mouse y, 2=keycode, 3=OSD kbd
assign KBD_MOUSE_STROBE = kbd_mouse_strobe; // strobe, data valid on rising edge
assign KMS_LEVEL = kbd_mouse_strobe_level; // level change of kbd_mouse_strobe
assign MOUSE_BUTTONS = mouse_buttons; // state of the two mouse buttons
assign BUTTONS = but_sw[1:0];
assign SWITCHES = but_sw[3:2];
assign CONF = but_sw[7:4];
always@(negedge SPI_CLK) begin
if(cnt < 8)
SPI_MISO <= CORE_TYPE[7-cnt];
end
always@(posedge SPI_CLK) begin
kbd_mouse_strobe_level <= #1 kbd_mouse_strobe_level ^ kbd_mouse_strobe;
if(SPI_SS_IO == 1) begin
cnt <= 0;
end else begin
sbuf[6:1] <= sbuf[5:0];
sbuf[0] <= SPI_MOSI;
cnt <= cnt + 1;
if(cnt == 7) begin
cmd[7:1] <= sbuf;
cmd[0] <= SPI_MOSI;
end
if(cnt == 8) begin
if(cmd == 4)
kbd_mouse_type <= 2'b00; // first mouse axis
else if(cmd == 5)
kbd_mouse_type <= 2'b10; // keyboard
else if(cmd == 6)
kbd_mouse_type <= 2'b11; // OSD keyboard
end
// strobe is set whenever a valid byte has been received
kbd_mouse_strobe <= 0;
// first payload byte
if(cnt == 15) begin
if(cmd == 1) begin
but_sw[7:1] <= sbuf[6:0];
but_sw[0] <= SPI_MOSI;
end
if(cmd == 2) begin
joystick0[7:1] <= sbuf[6:0];
joystick0[0] <= SPI_MOSI;
end
if(cmd == 3) begin
joystick1[7:1] <= sbuf[6:0];
joystick1[0] <= SPI_MOSI;
end
// mouse, keyboard or OSD
if((cmd == 4)||(cmd == 5)||(cmd == 6)) begin
kbd_mouse_data[7:1] <= sbuf[6:0];
kbd_mouse_data[0] <= SPI_MOSI;
kbd_mouse_strobe <= 1;
end
end
// mouse handling
if(cmd == 4) begin
// second byte contains movement data
if(cnt == 23) begin
kbd_mouse_data[7:1] <= sbuf[6:0];
kbd_mouse_data[0] <= SPI_MOSI;
kbd_mouse_strobe <= 1;
kbd_mouse_type <= 2'b01;
end
// third byte contains the buttons
if(cnt == 31) begin
mouse_buttons[2:1] <= sbuf[1:0];
mouse_buttons[0] <= SPI_MOSI;
end
end
end
end
endmodule |
module delay_stage(in, trim, out);
input in;
input [1:0] trim;
output out;
wire d0, d1, d2;
sky130_fd_sc_hd__clkbuf_2 delaybuf0 (
.A(in),
.X(ts)
);
sky130_fd_sc_hd__clkbuf_1 delaybuf1 (
.A(ts),
.X(d0)
);
sky130_fd_sc_hd__einvp_2 delayen1 (
.A(d0),
.TE(trim[1]),
.Z(d1)
);
sky130_fd_sc_hd__einvn_4 delayenb1 (
.A(ts),
.TE_B(trim[1]),
.Z(d1)
);
sky130_fd_sc_hd__clkinv_1 delayint0 (
.A(d1),
.Y(d2)
);
sky130_fd_sc_hd__einvp_2 delayen0 (
.A(d2),
.TE(trim[0]),
.Z(out)
);
sky130_fd_sc_hd__einvn_8 delayenb0 (
.A(ts),
.TE_B(trim[0]),
.Z(out)
);
endmodule |
module start_stage(in, trim, reset, out);
input in;
input [1:0] trim;
input reset;
output out;
wire d0, d1, d2, ctrl0, one;
sky130_fd_sc_hd__clkbuf_1 delaybuf0 (
.A(in),
.X(d0)
);
sky130_fd_sc_hd__einvp_2 delayen1 (
.A(d0),
.TE(trim[1]),
.Z(d1)
);
sky130_fd_sc_hd__einvn_4 delayenb1 (
.A(in),
.TE_B(trim[1]),
.Z(d1)
);
sky130_fd_sc_hd__clkinv_1 delayint0 (
.A(d1),
.Y(d2)
);
sky130_fd_sc_hd__einvp_2 delayen0 (
.A(d2),
.TE(trim[0]),
.Z(out)
);
sky130_fd_sc_hd__einvn_8 delayenb0 (
.A(in),
.TE_B(ctrl0),
.Z(out)
);
sky130_fd_sc_hd__einvp_1 reseten0 (
.A(one),
.TE(reset),
.Z(out)
);
sky130_fd_sc_hd__or2_2 ctrlen0 (
.A(reset),
.B(trim[0]),
.X(ctrl0)
);
sky130_fd_sc_hd__conb_1 const1 (
.HI(one),
.LO()
);
endmodule |
module ring_osc2x13(reset, trim, clockp);
input reset;
input [25:0] trim;
output[1:0] clockp;
wire [12:0] d;
wire [1:0] clockp;
wire [1:0] c;
// Main oscillator loop stages
genvar i;
generate
for (i = 0; i < 12; i = i + 1) begin : dstage
delay_stage id (
.in(d[i]),
.trim({trim[i+13], trim[i]}),
.out(d[i+1])
);
end
endgenerate
// Reset/startup stage
start_stage iss (
.in(d[12]),
.trim({trim[25], trim[12]}),
.reset(reset),
.out(d[0])
);
// Buffered outputs a 0 and 90 degrees phase (approximately)
sky130_fd_sc_hd__clkinv_2 ibufp00 (
.A(d[0]),
.Y(c[0])
);
sky130_fd_sc_hd__clkinv_8 ibufp01 (
.A(c[0]),
.Y(clockp[0])
);
sky130_fd_sc_hd__clkinv_2 ibufp10 (
.A(d[6]),
.Y(c[1])
);
sky130_fd_sc_hd__clkinv_8 ibufp11 (
.A(c[1]),
.Y(clockp[1])
);
endmodule |
module rx_engine_ultrascale
#(parameter C_PCI_DATA_WIDTH = 128
)
(
// Interface: Clocks
input CLK,
// Interface: Resets
input RST_IN,
// Interface: CQ
input M_AXIS_CQ_TVALID,
input M_AXIS_CQ_TLAST,
input [C_PCI_DATA_WIDTH-1:0] M_AXIS_CQ_TDATA,
input [(C_PCI_DATA_WIDTH/32)-1:0] M_AXIS_CQ_TKEEP,
input [`SIG_CQ_TUSER_W-1:0] M_AXIS_CQ_TUSER,
output M_AXIS_CQ_TREADY,
// Interface: RC
input M_AXIS_RC_TVALID,
input M_AXIS_RC_TLAST,
input [C_PCI_DATA_WIDTH-1:0] M_AXIS_RC_TDATA,
input [(C_PCI_DATA_WIDTH/32)-1:0] M_AXIS_RC_TKEEP,
input [`SIG_RC_TUSER_W-1:0] M_AXIS_RC_TUSER,
output M_AXIS_RC_TREADY,
// Interface: RXC Engine
output [C_PCI_DATA_WIDTH-1:0] RXC_DATA,
output RXC_DATA_VALID,
output [(C_PCI_DATA_WIDTH/32)-1:0] RXC_DATA_WORD_ENABLE,
output RXC_DATA_START_FLAG,
output [clog2s(C_PCI_DATA_WIDTH/32)-1:0] RXC_DATA_START_OFFSET,
output RXC_DATA_END_FLAG,
output [clog2s(C_PCI_DATA_WIDTH/32)-1:0] RXC_DATA_END_OFFSET,
output [`SIG_LBE_W-1:0] RXC_META_LDWBE,
output [`SIG_FBE_W-1:0] RXC_META_FDWBE,
output [`SIG_TAG_W-1:0] RXC_META_TAG,
output [`SIG_LOWADDR_W-1:0] RXC_META_ADDR,
output [`SIG_TYPE_W-1:0] RXC_META_TYPE,
output [`SIG_LEN_W-1:0] RXC_META_LENGTH,
output [`SIG_BYTECNT_W-1:0] RXC_META_BYTES_REMAINING,
output [`SIG_CPLID_W-1:0] RXC_META_COMPLETER_ID,
output RXC_META_EP,
// Interface: RXR Engine
output [C_PCI_DATA_WIDTH-1:0] RXR_DATA,
output RXR_DATA_VALID,
output [(C_PCI_DATA_WIDTH/32)-1:0] RXR_DATA_WORD_ENABLE,
output RXR_DATA_START_FLAG,
output [clog2s(C_PCI_DATA_WIDTH/32)-1:0] RXR_DATA_START_OFFSET,
output RXR_DATA_END_FLAG,
output [clog2s(C_PCI_DATA_WIDTH/32)-1:0] RXR_DATA_END_OFFSET,
output [`SIG_FBE_W-1:0] RXR_META_FDWBE,
output [`SIG_LBE_W-1:0] RXR_META_LDWBE,
output [`SIG_TC_W-1:0] RXR_META_TC,
output [`SIG_ATTR_W-1:0] RXR_META_ATTR,
output [`SIG_TAG_W-1:0] RXR_META_TAG,
output [`SIG_TYPE_W-1:0] RXR_META_TYPE,
output [`SIG_ADDR_W-1:0] RXR_META_ADDR,
output [`SIG_BARDECODE_W-1:0] RXR_META_BAR_DECODED,
output [`SIG_REQID_W-1:0] RXR_META_REQUESTER_ID,
output [`SIG_LEN_W-1:0] RXR_META_LENGTH,
output RXR_META_EP
);
localparam C_RX_PIPELINE_DEPTH = 3;
rxc_engine_ultrascale
#(///*AUTOINSTPARAM*/
// Parameters
.C_PCI_DATA_WIDTH (C_PCI_DATA_WIDTH),
.C_RX_PIPELINE_DEPTH (C_RX_PIPELINE_DEPTH))
rxc_engine_inst
(/*AUTOINST*/
// Outputs
.M_AXIS_RC_TREADY (M_AXIS_RC_TREADY),
.RXC_DATA (RXC_DATA[C_PCI_DATA_WIDTH-1:0]),
.RXC_DATA_VALID (RXC_DATA_VALID),
.RXC_DATA_WORD_ENABLE (RXC_DATA_WORD_ENABLE[(C_PCI_DATA_WIDTH/32)-1:0]),
.RXC_DATA_START_FLAG (RXC_DATA_START_FLAG),
.RXC_DATA_START_OFFSET (RXC_DATA_START_OFFSET[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.RXC_DATA_END_FLAG (RXC_DATA_END_FLAG),
.RXC_DATA_END_OFFSET (RXC_DATA_END_OFFSET[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.RXC_META_LDWBE (RXC_META_LDWBE[`SIG_LBE_W-1:0]),
.RXC_META_FDWBE (RXC_META_FDWBE[`SIG_FBE_W-1:0]),
.RXC_META_TAG (RXC_META_TAG[`SIG_TAG_W-1:0]),
.RXC_META_ADDR (RXC_META_ADDR[`SIG_LOWADDR_W-1:0]),
.RXC_META_TYPE (RXC_META_TYPE[`SIG_TYPE_W-1:0]),
.RXC_META_LENGTH (RXC_META_LENGTH[`SIG_LEN_W-1:0]),
.RXC_META_BYTES_REMAINING (RXC_META_BYTES_REMAINING[`SIG_BYTECNT_W-1:0]),
.RXC_META_COMPLETER_ID (RXC_META_COMPLETER_ID[`SIG_CPLID_W-1:0]),
.RXC_META_EP (RXC_META_EP),
// Inputs
.CLK (CLK),
.RST_IN (RST_IN),
.M_AXIS_RC_TVALID (M_AXIS_RC_TVALID),
.M_AXIS_RC_TLAST (M_AXIS_RC_TLAST),
.M_AXIS_RC_TDATA (M_AXIS_RC_TDATA[C_PCI_DATA_WIDTH-1:0]),
.M_AXIS_RC_TKEEP (M_AXIS_RC_TKEEP[(C_PCI_DATA_WIDTH/32)-1:0]),
.M_AXIS_RC_TUSER (M_AXIS_RC_TUSER[`SIG_RC_TUSER_W-1:0]));
rxr_engine_ultrascale
#(/*AUTOINSTPARAM*/
// Parameters
.C_PCI_DATA_WIDTH (C_PCI_DATA_WIDTH),
.C_RX_PIPELINE_DEPTH (C_RX_PIPELINE_DEPTH))
rxr_engine_inst
(/*AUTOINST*/
// Outputs
.M_AXIS_CQ_TREADY (M_AXIS_CQ_TREADY),
.RXR_DATA (RXR_DATA[C_PCI_DATA_WIDTH-1:0]),
.RXR_DATA_VALID (RXR_DATA_VALID),
.RXR_DATA_WORD_ENABLE (RXR_DATA_WORD_ENABLE[(C_PCI_DATA_WIDTH/32)-1:0]),
.RXR_DATA_START_FLAG (RXR_DATA_START_FLAG),
.RXR_DATA_START_OFFSET (RXR_DATA_START_OFFSET[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.RXR_DATA_END_FLAG (RXR_DATA_END_FLAG),
.RXR_DATA_END_OFFSET (RXR_DATA_END_OFFSET[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.RXR_META_FDWBE (RXR_META_FDWBE[`SIG_FBE_W-1:0]),
.RXR_META_LDWBE (RXR_META_LDWBE[`SIG_LBE_W-1:0]),
.RXR_META_TC (RXR_META_TC[`SIG_TC_W-1:0]),
.RXR_META_ATTR (RXR_META_ATTR[`SIG_ATTR_W-1:0]),
.RXR_META_TAG (RXR_META_TAG[`SIG_TAG_W-1:0]),
.RXR_META_TYPE (RXR_META_TYPE[`SIG_TYPE_W-1:0]),
.RXR_META_ADDR (RXR_META_ADDR[`SIG_ADDR_W-1:0]),
.RXR_META_BAR_DECODED (RXR_META_BAR_DECODED[`SIG_BARDECODE_W-1:0]),
.RXR_META_REQUESTER_ID (RXR_META_REQUESTER_ID[`SIG_REQID_W-1:0]),
.RXR_META_LENGTH (RXR_META_LENGTH[`SIG_LEN_W-1:0]),
.RXR_META_EP (RXR_META_EP),
// Inputs
.CLK (CLK),
.RST_IN (RST_IN),
.M_AXIS_CQ_TVALID (M_AXIS_CQ_TVALID),
.M_AXIS_CQ_TLAST (M_AXIS_CQ_TLAST),
.M_AXIS_CQ_TDATA (M_AXIS_CQ_TDATA[C_PCI_DATA_WIDTH-1:0]),
.M_AXIS_CQ_TKEEP (M_AXIS_CQ_TKEEP[(C_PCI_DATA_WIDTH/32)-1:0]),
.M_AXIS_CQ_TUSER (M_AXIS_CQ_TUSER[`SIG_CQ_TUSER_W-1:0]));
endmodule |
module sky130_fd_sc_hd__diode (
DIODE,
VPWR ,
VGND ,
VPB ,
VNB
);
input DIODE;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
endmodule |
module ClockDivider
(clk,
clk_vga,
clk_cpu,
clk_2cpu);
input clk;
output clk_vga;
output clk_cpu;
output clk_2cpu;
(* IBUF_LOW_PWR *) wire clk;
wire clk_2cpu;
wire clk_cpu;
wire clk_vga;
ClockDivider_ClockDivider_clk_wiz inst
(.clk(clk),
.clk_2cpu(clk_2cpu),
.clk_cpu(clk_cpu),
.clk_vga(clk_vga));
endmodule |
module ClockDivider_ClockDivider_clk_wiz
(clk,
clk_vga,
clk_cpu,
clk_2cpu);
input clk;
output clk_vga;
output clk_cpu;
output clk_2cpu;
wire clk;
wire clk_2cpu;
wire clk_2cpu_ClockDivider;
wire clk_ClockDivider;
wire clk_cpu;
wire clk_cpu_ClockDivider;
wire clk_vga;
wire clk_vga_ClockDivider;
wire clkfbout_ClockDivider;
wire clkfbout_buf_ClockDivider;
wire NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED;
wire NLW_mmcm_adv_inst_DRDY_UNCONNECTED;
wire NLW_mmcm_adv_inst_LOCKED_UNCONNECTED;
wire NLW_mmcm_adv_inst_PSDONE_UNCONNECTED;
wire [15:0]NLW_mmcm_adv_inst_DO_UNCONNECTED;
(* BOX_TYPE = "PRIMITIVE" *)
BUFG clkf_buf
(.I(clkfbout_ClockDivider),
.O(clkfbout_buf_ClockDivider));
(* BOX_TYPE = "PRIMITIVE" *)
(* CAPACITANCE = "DONT_CARE" *)
(* IBUF_DELAY_VALUE = "0" *)
(* IFD_DELAY_VALUE = "AUTO" *)
IBUF #(
.IOSTANDARD("DEFAULT"))
clkin1_ibufg
(.I(clk),
.O(clk_ClockDivider));
(* BOX_TYPE = "PRIMITIVE" *)
BUFG clkout1_buf
(.I(clk_vga_ClockDivider),
.O(clk_vga));
(* BOX_TYPE = "PRIMITIVE" *)
BUFG clkout2_buf
(.I(clk_cpu_ClockDivider),
.O(clk_cpu));
(* BOX_TYPE = "PRIMITIVE" *)
BUFG clkout3_buf
(.I(clk_2cpu_ClockDivider),
.O(clk_2cpu));
(* BOX_TYPE = "PRIMITIVE" *)
MMCME2_ADV #(
.BANDWIDTH("OPTIMIZED"),
.CLKFBOUT_MULT_F(54.000000),
.CLKFBOUT_PHASE(0.000000),
.CLKFBOUT_USE_FINE_PS("FALSE"),
.CLKIN1_PERIOD(10.000000),
.CLKIN2_PERIOD(0.000000),
.CLKOUT0_DIVIDE_F(10.000000),
.CLKOUT0_DUTY_CYCLE(0.500000),
.CLKOUT0_PHASE(0.000000),
.CLKOUT0_USE_FINE_PS("FALSE"),
.CLKOUT1_DIVIDE(120),
.CLKOUT1_DUTY_CYCLE(0.500000),
.CLKOUT1_PHASE(0.000000),
.CLKOUT1_USE_FINE_PS("FALSE"),
.CLKOUT2_DIVIDE(60),
.CLKOUT2_DUTY_CYCLE(0.500000),
.CLKOUT2_PHASE(0.000000),
.CLKOUT2_USE_FINE_PS("FALSE"),
.CLKOUT3_DIVIDE(1),
.CLKOUT3_DUTY_CYCLE(0.500000),
.CLKOUT3_PHASE(0.000000),
.CLKOUT3_USE_FINE_PS("FALSE"),
.CLKOUT4_CASCADE("FALSE"),
.CLKOUT4_DIVIDE(1),
.CLKOUT4_DUTY_CYCLE(0.500000),
.CLKOUT4_PHASE(0.000000),
.CLKOUT4_USE_FINE_PS("FALSE"),
.CLKOUT5_DIVIDE(1),
.CLKOUT5_DUTY_CYCLE(0.500000),
.CLKOUT5_PHASE(0.000000),
.CLKOUT5_USE_FINE_PS("FALSE"),
.CLKOUT6_DIVIDE(1),
.CLKOUT6_DUTY_CYCLE(0.500000),
.CLKOUT6_PHASE(0.000000),
.CLKOUT6_USE_FINE_PS("FALSE"),
.COMPENSATION("ZHOLD"),
.DIVCLK_DIVIDE(5),
.IS_CLKINSEL_INVERTED(1'b0),
.IS_PSEN_INVERTED(1'b0),
.IS_PSINCDEC_INVERTED(1'b0),
.IS_PWRDWN_INVERTED(1'b0),
.IS_RST_INVERTED(1'b0),
.REF_JITTER1(0.010000),
.REF_JITTER2(0.010000),
.SS_EN("FALSE"),
.SS_MODE("CENTER_HIGH"),
.SS_MOD_PERIOD(10000),
.STARTUP_WAIT("FALSE"))
mmcm_adv_inst
(.CLKFBIN(clkfbout_buf_ClockDivider),
.CLKFBOUT(clkfbout_ClockDivider),
.CLKFBOUTB(NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED),
.CLKFBSTOPPED(NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED),
.CLKIN1(clk_ClockDivider),
.CLKIN2(1'b0),
.CLKINSEL(1'b1),
.CLKINSTOPPED(NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED),
.CLKOUT0(clk_vga_ClockDivider),
.CLKOUT0B(NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED),
.CLKOUT1(clk_cpu_ClockDivider),
.CLKOUT1B(NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED),
.CLKOUT2(clk_2cpu_ClockDivider),
.CLKOUT2B(NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED),
.CLKOUT3(NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED),
.CLKOUT3B(NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED),
.CLKOUT4(NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED),
.CLKOUT5(NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED),
.CLKOUT6(NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED),
.DADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DCLK(1'b0),
.DEN(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DO(NLW_mmcm_adv_inst_DO_UNCONNECTED[15:0]),
.DRDY(NLW_mmcm_adv_inst_DRDY_UNCONNECTED),
.DWE(1'b0),
.LOCKED(NLW_mmcm_adv_inst_LOCKED_UNCONNECTED),
.PSCLK(1'b0),
.PSDONE(NLW_mmcm_adv_inst_PSDONE_UNCONNECTED),
.PSEN(1'b0),
.PSINCDEC(1'b0),
.PWRDWN(1'b0),
.RST(1'b0));
endmodule |
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule |
module sky130_fd_sc_hdll__dlrtp (
Q ,
RESET_B,
D ,
GATE ,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
input RESET_B;
input D ;
input GATE ;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire RESET ;
reg notifier ;
wire D_delayed ;
wire GATE_delayed ;
wire RESET_delayed ;
wire RESET_B_delayed;
wire buf_Q ;
wire awake ;
wire cond0 ;
wire cond1 ;
// Name Output Other arguments
not not0 (RESET , RESET_B_delayed );
sky130_fd_sc_hdll__udp_dlatch$PR_pp$PG$N dlatch0 (buf_Q , D_delayed, GATE_delayed, RESET, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond0 = ( awake && ( RESET_B_delayed === 1'b1 ) );
assign cond1 = ( awake && ( RESET_B === 1'b1 ) );
buf buf0 (Q , buf_Q );
endmodule |
module sky130_fd_sc_ls__or3b (
//# {{data|Data Signals}}
input A ,
input B ,
input C_N ,
output X ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule |
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(sys_clkp, sys_clkn, sys_rst, log_clk_out,
phy_clk_out, gt_clk_out, gt_pcs_clk_out, drpclk_out, refclk_out, clk_lock_out, cfg_rst_out,
log_rst_out, buf_rst_out, phy_rst_out, gt_pcs_rst_out, gt0_qpll_clk_out,
gt0_qpll_out_refclk_out, srio_rxn0, srio_rxp0, srio_txn0, srio_txp0, s_axis_iotx_tvalid,
s_axis_iotx_tready, s_axis_iotx_tlast, s_axis_iotx_tdata, s_axis_iotx_tkeep,
s_axis_iotx_tuser, m_axis_iorx_tvalid, m_axis_iorx_tready, m_axis_iorx_tlast,
m_axis_iorx_tdata, m_axis_iorx_tkeep, m_axis_iorx_tuser, s_axi_maintr_rst,
s_axi_maintr_awvalid, s_axi_maintr_awready, s_axi_maintr_awaddr, s_axi_maintr_wvalid,
s_axi_maintr_wready, s_axi_maintr_wdata, s_axi_maintr_bvalid, s_axi_maintr_bready,
s_axi_maintr_bresp, s_axi_maintr_arvalid, s_axi_maintr_arready, s_axi_maintr_araddr,
s_axi_maintr_rvalid, s_axi_maintr_rready, s_axi_maintr_rdata, s_axi_maintr_rresp,
sim_train_en, force_reinit, phy_mce, phy_link_reset, phy_rcvd_mce, phy_rcvd_link_reset,
phy_debug, gtrx_disperr_or, gtrx_notintable_or, port_error, port_timeout, srio_host,
port_decode_error, deviceid, idle2_selected, phy_lcl_master_enable_out,
buf_lcl_response_only_out, buf_lcl_tx_flow_control_out, buf_lcl_phy_buf_stat_out,
phy_lcl_phy_next_fm_out, phy_lcl_phy_last_ack_out, phy_lcl_phy_rewind_out,
phy_lcl_phy_rcvd_buf_stat_out, phy_lcl_maint_only_out, port_initialized,
link_initialized, idle_selected, mode_1x)
/* synthesis syn_black_box black_box_pad_pin="sys_clkp,sys_clkn,sys_rst,log_clk_out,phy_clk_out,gt_clk_out,gt_pcs_clk_out,drpclk_out,refclk_out,clk_lock_out,cfg_rst_out,log_rst_out,buf_rst_out,phy_rst_out,gt_pcs_rst_out,gt0_qpll_clk_out,gt0_qpll_out_refclk_out,srio_rxn0,srio_rxp0,srio_txn0,srio_txp0,s_axis_iotx_tvalid,s_axis_iotx_tready,s_axis_iotx_tlast,s_axis_iotx_tdata[63:0],s_axis_iotx_tkeep[7:0],s_axis_iotx_tuser[31:0],m_axis_iorx_tvalid,m_axis_iorx_tready,m_axis_iorx_tlast,m_axis_iorx_tdata[63:0],m_axis_iorx_tkeep[7:0],m_axis_iorx_tuser[31:0],s_axi_maintr_rst,s_axi_maintr_awvalid,s_axi_maintr_awready,s_axi_maintr_awaddr[31:0],s_axi_maintr_wvalid,s_axi_maintr_wready,s_axi_maintr_wdata[31:0],s_axi_maintr_bvalid,s_axi_maintr_bready,s_axi_maintr_bresp[1:0],s_axi_maintr_arvalid,s_axi_maintr_arready,s_axi_maintr_araddr[31:0],s_axi_maintr_rvalid,s_axi_maintr_rready,s_axi_maintr_rdata[31:0],s_axi_maintr_rresp[1:0],sim_train_en,force_reinit,phy_mce,phy_link_reset,phy_rcvd_mce,phy_rcvd_link_reset,phy_debug[223:0],gtrx_disperr_or,gtrx_notintable_or,port_error,port_timeout[23:0],srio_host,port_decode_error,deviceid[15:0],idle2_selected,phy_lcl_master_enable_out,buf_lcl_response_only_out,buf_lcl_tx_flow_control_out,buf_lcl_phy_buf_stat_out[5:0],phy_lcl_phy_next_fm_out[5:0],phy_lcl_phy_last_ack_out[5:0],phy_lcl_phy_rewind_out,phy_lcl_phy_rcvd_buf_stat_out[5:0],phy_lcl_maint_only_out,port_initialized,link_initialized,idle_selected,mode_1x" */;
input sys_clkp;
input sys_clkn;
input sys_rst;
output log_clk_out;
output phy_clk_out;
output gt_clk_out;
output gt_pcs_clk_out;
output drpclk_out;
output refclk_out;
output clk_lock_out;
output cfg_rst_out;
output log_rst_out;
output buf_rst_out;
output phy_rst_out;
output gt_pcs_rst_out;
output gt0_qpll_clk_out;
output gt0_qpll_out_refclk_out;
input srio_rxn0;
input srio_rxp0;
output srio_txn0;
output srio_txp0;
input s_axis_iotx_tvalid;
output s_axis_iotx_tready;
input s_axis_iotx_tlast;
input [63:0]s_axis_iotx_tdata;
input [7:0]s_axis_iotx_tkeep;
input [31:0]s_axis_iotx_tuser;
output m_axis_iorx_tvalid;
input m_axis_iorx_tready;
output m_axis_iorx_tlast;
output [63:0]m_axis_iorx_tdata;
output [7:0]m_axis_iorx_tkeep;
output [31:0]m_axis_iorx_tuser;
input s_axi_maintr_rst;
input s_axi_maintr_awvalid;
output s_axi_maintr_awready;
input [31:0]s_axi_maintr_awaddr;
input s_axi_maintr_wvalid;
output s_axi_maintr_wready;
input [31:0]s_axi_maintr_wdata;
output s_axi_maintr_bvalid;
input s_axi_maintr_bready;
output [1:0]s_axi_maintr_bresp;
input s_axi_maintr_arvalid;
output s_axi_maintr_arready;
input [31:0]s_axi_maintr_araddr;
output s_axi_maintr_rvalid;
input s_axi_maintr_rready;
output [31:0]s_axi_maintr_rdata;
output [1:0]s_axi_maintr_rresp;
input sim_train_en;
input force_reinit;
input phy_mce;
input phy_link_reset;
output phy_rcvd_mce;
output phy_rcvd_link_reset;
output [223:0]phy_debug;
output gtrx_disperr_or;
output gtrx_notintable_or;
output port_error;
output [23:0]port_timeout;
output srio_host;
output port_decode_error;
output [15:0]deviceid;
output idle2_selected;
output phy_lcl_master_enable_out;
output buf_lcl_response_only_out;
output buf_lcl_tx_flow_control_out;
output [5:0]buf_lcl_phy_buf_stat_out;
output [5:0]phy_lcl_phy_next_fm_out;
output [5:0]phy_lcl_phy_last_ack_out;
output phy_lcl_phy_rewind_out;
output [5:0]phy_lcl_phy_rcvd_buf_stat_out;
output phy_lcl_maint_only_out;
output port_initialized;
output link_initialized;
output idle_selected;
output mode_1x;
endmodule |
module FPU_Multiplication_Function_W32_EW8_SW23 ( clk, rst, beg_FSM, ack_FSM,
Data_MX, Data_MY, round_mode, overflow_flag, underflow_flag, ready,
final_result_ieee );
input [31:0] Data_MX;
input [31:0] Data_MY;
input [1:0] round_mode;
output [31:0] final_result_ieee;
input clk, rst, beg_FSM, ack_FSM;
output overflow_flag, underflow_flag, ready;
wire zero_flag, FSM_add_overflow_flag, FSM_selector_A, FSM_selector_C,
Exp_module_Overflow_flag_A, n167, n168, n170, n171, n172, n173, n174,
n175, n176, n177, n178, n179, n180, n181, n182, n183, n184, n185,
n186, n187, n188, n189, n190, n191, n192, n193, n194, n195, n196,
n197, n198, n199, n200, n201, n202, n203, n204, n205, n206, n207,
n208, n209, n210, n211, n212, n213, n214, n215, n216, n217, n218,
n219, n220, n221, n222, n223, n224, n225, n226, n227, n228, n229,
n230, n231, n232, n233, n234, n235, n236, n237, n238, n239, n240,
n241, n242, n243, n244, n245, n246, n247, n248, n249, n250, n251,
n252, n253, n254, n255, n256, n257, n258, n259, n260, n261, n262,
n263, n264, n265, n266, n267, n268, n269, n270, n271, n272, n273,
n274, n275, n276, n277, n278, n279, n280, n281, n282, n283, n284,
n285, n286, n287, n288, n289, n290, n291, n292, n293, n294, n295,
n296, n297, n298, n299, n300, n301, n302, n303, n304, n305, n306,
n307, n308, n309, n310, n311, n312, n313, n314, n315, n316, n317,
n318, n319, n320, n321, n322, n323, n324, n325, n326, n327, n328,
n329, n330, n331, n332, n333, n334, n335, n336, n337, n338, n339,
n340, n341, n342, n343, n344, n345, n346, n347, n348, n349, n350,
n351, n352, n353, n354, n355, n356, n357, n358, n359, n360, n361,
n362, n363, n364, n365, n366, n367, n368, n369, n370, n371, n372,
n373, n374, n375, n376, n377, n378, n379, n380, n381,
DP_OP_36J10_126_4699_n33, DP_OP_36J10_126_4699_n22,
DP_OP_36J10_126_4699_n21, DP_OP_36J10_126_4699_n20,
DP_OP_36J10_126_4699_n19, DP_OP_36J10_126_4699_n18,
DP_OP_36J10_126_4699_n17, DP_OP_36J10_126_4699_n16,
DP_OP_36J10_126_4699_n15, DP_OP_36J10_126_4699_n9,
DP_OP_36J10_126_4699_n8, DP_OP_36J10_126_4699_n7,
DP_OP_36J10_126_4699_n6, DP_OP_36J10_126_4699_n5,
DP_OP_36J10_126_4699_n4, DP_OP_36J10_126_4699_n3,
DP_OP_36J10_126_4699_n2, DP_OP_36J10_126_4699_n1,
DP_OP_156J10_125_3370_n133, DP_OP_156J10_125_3370_n132,
DP_OP_156J10_125_3370_n131, DP_OP_156J10_125_3370_n130,
DP_OP_156J10_125_3370_n129, DP_OP_156J10_125_3370_n128,
DP_OP_156J10_125_3370_n127, DP_OP_156J10_125_3370_n126,
DP_OP_156J10_125_3370_n125, DP_OP_156J10_125_3370_n124,
DP_OP_156J10_125_3370_n123, DP_OP_156J10_125_3370_n122,
DP_OP_156J10_125_3370_n121, DP_OP_156J10_125_3370_n120,
DP_OP_156J10_125_3370_n119, DP_OP_156J10_125_3370_n118,
DP_OP_156J10_125_3370_n110, DP_OP_156J10_125_3370_n109,
DP_OP_156J10_125_3370_n108, DP_OP_156J10_125_3370_n107,
DP_OP_156J10_125_3370_n106, DP_OP_156J10_125_3370_n105,
DP_OP_156J10_125_3370_n104, DP_OP_156J10_125_3370_n103,
DP_OP_156J10_125_3370_n102, DP_OP_156J10_125_3370_n101,
DP_OP_156J10_125_3370_n100, DP_OP_156J10_125_3370_n99,
DP_OP_156J10_125_3370_n98, DP_OP_156J10_125_3370_n97,
DP_OP_156J10_125_3370_n96, DP_OP_156J10_125_3370_n95,
DP_OP_156J10_125_3370_n81, DP_OP_156J10_125_3370_n78,
DP_OP_156J10_125_3370_n77, DP_OP_156J10_125_3370_n76,
DP_OP_156J10_125_3370_n75, DP_OP_156J10_125_3370_n74,
DP_OP_156J10_125_3370_n73, DP_OP_156J10_125_3370_n72,
DP_OP_156J10_125_3370_n71, DP_OP_156J10_125_3370_n70,
DP_OP_156J10_125_3370_n69, DP_OP_156J10_125_3370_n68,
DP_OP_156J10_125_3370_n67, DP_OP_156J10_125_3370_n66,
DP_OP_156J10_125_3370_n65, DP_OP_156J10_125_3370_n64,
DP_OP_156J10_125_3370_n63, DP_OP_156J10_125_3370_n62,
DP_OP_156J10_125_3370_n61, DP_OP_156J10_125_3370_n60,
DP_OP_156J10_125_3370_n59, DP_OP_156J10_125_3370_n58,
DP_OP_156J10_125_3370_n57, DP_OP_156J10_125_3370_n56,
DP_OP_156J10_125_3370_n55, DP_OP_156J10_125_3370_n54,
DP_OP_156J10_125_3370_n53, DP_OP_156J10_125_3370_n52,
DP_OP_156J10_125_3370_n51, DP_OP_156J10_125_3370_n50,
DP_OP_156J10_125_3370_n49, DP_OP_156J10_125_3370_n48,
DP_OP_156J10_125_3370_n47, DP_OP_156J10_125_3370_n46,
DP_OP_156J10_125_3370_n45, DP_OP_156J10_125_3370_n44,
DP_OP_156J10_125_3370_n43, DP_OP_156J10_125_3370_n42,
DP_OP_156J10_125_3370_n41, DP_OP_156J10_125_3370_n40,
DP_OP_156J10_125_3370_n39, DP_OP_156J10_125_3370_n38,
DP_OP_156J10_125_3370_n37, DP_OP_156J10_125_3370_n36,
DP_OP_156J10_125_3370_n35, DP_OP_156J10_125_3370_n34,
DP_OP_156J10_125_3370_n33, DP_OP_156J10_125_3370_n32,
DP_OP_156J10_125_3370_n31, DP_OP_155J10_124_2038_n370,
DP_OP_155J10_124_2038_n365, DP_OP_155J10_124_2038_n364,
DP_OP_155J10_124_2038_n360, DP_OP_155J10_124_2038_n352,
DP_OP_155J10_124_2038_n351, DP_OP_155J10_124_2038_n346,
DP_OP_155J10_124_2038_n341, DP_OP_155J10_124_2038_n335,
DP_OP_155J10_124_2038_n332, DP_OP_155J10_124_2038_n331,
DP_OP_155J10_124_2038_n330, DP_OP_155J10_124_2038_n329,
DP_OP_155J10_124_2038_n328, DP_OP_155J10_124_2038_n327,
DP_OP_155J10_124_2038_n326, DP_OP_155J10_124_2038_n325,
DP_OP_155J10_124_2038_n324, DP_OP_155J10_124_2038_n323,
DP_OP_155J10_124_2038_n322, DP_OP_155J10_124_2038_n321,
DP_OP_155J10_124_2038_n320, DP_OP_155J10_124_2038_n319,
DP_OP_155J10_124_2038_n318, DP_OP_155J10_124_2038_n317,
DP_OP_155J10_124_2038_n316, DP_OP_155J10_124_2038_n315,
DP_OP_155J10_124_2038_n314, DP_OP_155J10_124_2038_n313,
DP_OP_155J10_124_2038_n312, DP_OP_155J10_124_2038_n311,
DP_OP_155J10_124_2038_n310, DP_OP_155J10_124_2038_n309,
DP_OP_155J10_124_2038_n308, DP_OP_155J10_124_2038_n307,
DP_OP_155J10_124_2038_n306, DP_OP_155J10_124_2038_n279,
DP_OP_155J10_124_2038_n274, DP_OP_155J10_124_2038_n273,
DP_OP_155J10_124_2038_n269, DP_OP_155J10_124_2038_n261,
DP_OP_155J10_124_2038_n260, DP_OP_155J10_124_2038_n255,
DP_OP_155J10_124_2038_n250, DP_OP_155J10_124_2038_n244,
DP_OP_155J10_124_2038_n241, DP_OP_155J10_124_2038_n240,
DP_OP_155J10_124_2038_n239, DP_OP_155J10_124_2038_n238,
DP_OP_155J10_124_2038_n237, DP_OP_155J10_124_2038_n236,
DP_OP_155J10_124_2038_n235, DP_OP_155J10_124_2038_n234,
DP_OP_155J10_124_2038_n233, DP_OP_155J10_124_2038_n232,
DP_OP_155J10_124_2038_n231, DP_OP_155J10_124_2038_n230,
DP_OP_155J10_124_2038_n229, DP_OP_155J10_124_2038_n228,
DP_OP_155J10_124_2038_n227, DP_OP_155J10_124_2038_n226,
DP_OP_155J10_124_2038_n225, DP_OP_155J10_124_2038_n224,
DP_OP_155J10_124_2038_n223, DP_OP_155J10_124_2038_n222,
DP_OP_155J10_124_2038_n221, DP_OP_155J10_124_2038_n220,
DP_OP_155J10_124_2038_n219, DP_OP_155J10_124_2038_n218,
DP_OP_155J10_124_2038_n217, DP_OP_155J10_124_2038_n216,
DP_OP_155J10_124_2038_n215, DP_OP_155J10_124_2038_n202,
DP_OP_155J10_124_2038_n201, DP_OP_155J10_124_2038_n197,
DP_OP_155J10_124_2038_n196, DP_OP_155J10_124_2038_n195,
DP_OP_155J10_124_2038_n194, DP_OP_155J10_124_2038_n193,
DP_OP_155J10_124_2038_n192, DP_OP_155J10_124_2038_n125,
DP_OP_155J10_124_2038_n124, DP_OP_155J10_124_2038_n123,
DP_OP_155J10_124_2038_n122, DP_OP_155J10_124_2038_n121,
DP_OP_155J10_124_2038_n120, DP_OP_155J10_124_2038_n119,
DP_OP_155J10_124_2038_n118, DP_OP_155J10_124_2038_n117,
DP_OP_155J10_124_2038_n116, DP_OP_155J10_124_2038_n114,
DP_OP_155J10_124_2038_n113, DP_OP_155J10_124_2038_n112,
DP_OP_155J10_124_2038_n111, DP_OP_155J10_124_2038_n110,
DP_OP_155J10_124_2038_n109, DP_OP_155J10_124_2038_n108,
DP_OP_155J10_124_2038_n107, DP_OP_155J10_124_2038_n106,
DP_OP_155J10_124_2038_n105, DP_OP_155J10_124_2038_n104,
DP_OP_155J10_124_2038_n103, DP_OP_155J10_124_2038_n101,
DP_OP_155J10_124_2038_n100, DP_OP_155J10_124_2038_n99,
DP_OP_155J10_124_2038_n98, DP_OP_155J10_124_2038_n97,
DP_OP_155J10_124_2038_n96, DP_OP_155J10_124_2038_n94,
DP_OP_155J10_124_2038_n91, DP_OP_155J10_124_2038_n90,
DP_OP_155J10_124_2038_n87, DP_OP_155J10_124_2038_n86,
DP_OP_155J10_124_2038_n83, DP_OP_155J10_124_2038_n82,
DP_OP_155J10_124_2038_n81, DP_OP_155J10_124_2038_n80,
DP_OP_155J10_124_2038_n79, DP_OP_155J10_124_2038_n78,
DP_OP_155J10_124_2038_n75, DP_OP_155J10_124_2038_n74,
DP_OP_155J10_124_2038_n73, DP_OP_155J10_124_2038_n72,
DP_OP_155J10_124_2038_n70, DP_OP_155J10_124_2038_n69,
DP_OP_155J10_124_2038_n68, DP_OP_155J10_124_2038_n67,
DP_OP_155J10_124_2038_n65, DP_OP_155J10_124_2038_n64,
DP_OP_155J10_124_2038_n63, DP_OP_155J10_124_2038_n62,
DP_OP_155J10_124_2038_n61, DP_OP_155J10_124_2038_n60,
DP_OP_155J10_124_2038_n59, DP_OP_155J10_124_2038_n58,
DP_OP_155J10_124_2038_n57, DP_OP_155J10_124_2038_n56,
DP_OP_155J10_124_2038_n55, DP_OP_155J10_124_2038_n54,
DP_OP_155J10_124_2038_n53, DP_OP_155J10_124_2038_n52,
DP_OP_155J10_124_2038_n51, DP_OP_155J10_124_2038_n50,
DP_OP_155J10_124_2038_n49, DP_OP_155J10_124_2038_n48,
DP_OP_155J10_124_2038_n47, DP_OP_155J10_124_2038_n46,
DP_OP_155J10_124_2038_n45, DP_OP_155J10_124_2038_n44,
DP_OP_155J10_124_2038_n43, DP_OP_155J10_124_2038_n42,
DP_OP_155J10_124_2038_n41, DP_OP_155J10_124_2038_n40,
DP_OP_155J10_124_2038_n39, DP_OP_155J10_124_2038_n38,
DP_OP_155J10_124_2038_n37, DP_OP_155J10_124_2038_n36,
DP_OP_155J10_124_2038_n35, DP_OP_155J10_124_2038_n34,
DP_OP_155J10_124_2038_n33, DP_OP_155J10_124_2038_n32,
DP_OP_155J10_124_2038_n31, DP_OP_155J10_124_2038_n30,
DP_OP_155J10_124_2038_n29, DP_OP_155J10_124_2038_n28,
DP_OP_155J10_124_2038_n27, DP_OP_155J10_124_2038_n26,
DP_OP_155J10_124_2038_n25, DP_OP_155J10_124_2038_n24,
DP_OP_155J10_124_2038_n23, DP_OP_155J10_124_2038_n22,
DP_OP_155J10_124_2038_n21, DP_OP_155J10_124_2038_n20,
DP_OP_155J10_124_2038_n19, DP_OP_155J10_124_2038_n18,
DP_OP_154J10_123_2038_n369, DP_OP_154J10_123_2038_n364,
DP_OP_154J10_123_2038_n359, DP_OP_154J10_123_2038_n358,
DP_OP_154J10_123_2038_n351, DP_OP_154J10_123_2038_n345,
DP_OP_154J10_123_2038_n335, DP_OP_154J10_123_2038_n332,
DP_OP_154J10_123_2038_n331, DP_OP_154J10_123_2038_n330,
DP_OP_154J10_123_2038_n329, DP_OP_154J10_123_2038_n328,
DP_OP_154J10_123_2038_n327, DP_OP_154J10_123_2038_n326,
DP_OP_154J10_123_2038_n325, DP_OP_154J10_123_2038_n324,
DP_OP_154J10_123_2038_n323, DP_OP_154J10_123_2038_n322,
DP_OP_154J10_123_2038_n321, DP_OP_154J10_123_2038_n320,
DP_OP_154J10_123_2038_n319, DP_OP_154J10_123_2038_n318,
DP_OP_154J10_123_2038_n317, DP_OP_154J10_123_2038_n316,
DP_OP_154J10_123_2038_n315, DP_OP_154J10_123_2038_n314,
DP_OP_154J10_123_2038_n313, DP_OP_154J10_123_2038_n312,
DP_OP_154J10_123_2038_n311, DP_OP_154J10_123_2038_n310,
DP_OP_154J10_123_2038_n309, DP_OP_154J10_123_2038_n308,
DP_OP_154J10_123_2038_n307, DP_OP_154J10_123_2038_n306,
DP_OP_154J10_123_2038_n279, DP_OP_154J10_123_2038_n274,
DP_OP_154J10_123_2038_n273, DP_OP_154J10_123_2038_n269,
DP_OP_154J10_123_2038_n261, DP_OP_154J10_123_2038_n260,
DP_OP_154J10_123_2038_n255, DP_OP_154J10_123_2038_n250,
DP_OP_154J10_123_2038_n244, DP_OP_154J10_123_2038_n241,
DP_OP_154J10_123_2038_n240, DP_OP_154J10_123_2038_n239,
DP_OP_154J10_123_2038_n238, DP_OP_154J10_123_2038_n237,
DP_OP_154J10_123_2038_n236, DP_OP_154J10_123_2038_n235,
DP_OP_154J10_123_2038_n234, DP_OP_154J10_123_2038_n233,
DP_OP_154J10_123_2038_n232, DP_OP_154J10_123_2038_n231,
DP_OP_154J10_123_2038_n230, DP_OP_154J10_123_2038_n229,
DP_OP_154J10_123_2038_n228, DP_OP_154J10_123_2038_n227,
DP_OP_154J10_123_2038_n226, DP_OP_154J10_123_2038_n225,
DP_OP_154J10_123_2038_n224, DP_OP_154J10_123_2038_n223,
DP_OP_154J10_123_2038_n222, DP_OP_154J10_123_2038_n221,
DP_OP_154J10_123_2038_n220, DP_OP_154J10_123_2038_n219,
DP_OP_154J10_123_2038_n218, DP_OP_154J10_123_2038_n217,
DP_OP_154J10_123_2038_n216, DP_OP_154J10_123_2038_n215,
DP_OP_154J10_123_2038_n202, DP_OP_154J10_123_2038_n201,
DP_OP_154J10_123_2038_n197, DP_OP_154J10_123_2038_n196,
DP_OP_154J10_123_2038_n195, DP_OP_154J10_123_2038_n194,
DP_OP_154J10_123_2038_n193, DP_OP_154J10_123_2038_n192,
DP_OP_154J10_123_2038_n125, DP_OP_154J10_123_2038_n124,
DP_OP_154J10_123_2038_n123, DP_OP_154J10_123_2038_n122,
DP_OP_154J10_123_2038_n121, DP_OP_154J10_123_2038_n120,
DP_OP_154J10_123_2038_n119, DP_OP_154J10_123_2038_n118,
DP_OP_154J10_123_2038_n117, DP_OP_154J10_123_2038_n116,
DP_OP_154J10_123_2038_n114, DP_OP_154J10_123_2038_n113,
DP_OP_154J10_123_2038_n112, DP_OP_154J10_123_2038_n111,
DP_OP_154J10_123_2038_n110, DP_OP_154J10_123_2038_n109,
DP_OP_154J10_123_2038_n108, DP_OP_154J10_123_2038_n107,
DP_OP_154J10_123_2038_n106, DP_OP_154J10_123_2038_n105,
DP_OP_154J10_123_2038_n104, DP_OP_154J10_123_2038_n103,
DP_OP_154J10_123_2038_n101, DP_OP_154J10_123_2038_n100,
DP_OP_154J10_123_2038_n99, DP_OP_154J10_123_2038_n98,
DP_OP_154J10_123_2038_n97, DP_OP_154J10_123_2038_n96,
DP_OP_154J10_123_2038_n94, DP_OP_154J10_123_2038_n91,
DP_OP_154J10_123_2038_n87, DP_OP_154J10_123_2038_n86,
DP_OP_154J10_123_2038_n83, DP_OP_154J10_123_2038_n82,
DP_OP_154J10_123_2038_n81, DP_OP_154J10_123_2038_n80,
DP_OP_154J10_123_2038_n79, DP_OP_154J10_123_2038_n78,
DP_OP_154J10_123_2038_n75, DP_OP_154J10_123_2038_n74,
DP_OP_154J10_123_2038_n73, DP_OP_154J10_123_2038_n72,
DP_OP_154J10_123_2038_n70, DP_OP_154J10_123_2038_n69,
DP_OP_154J10_123_2038_n68, DP_OP_154J10_123_2038_n67,
DP_OP_154J10_123_2038_n65, DP_OP_154J10_123_2038_n64,
DP_OP_154J10_123_2038_n63, DP_OP_154J10_123_2038_n62,
DP_OP_154J10_123_2038_n61, DP_OP_154J10_123_2038_n60,
DP_OP_154J10_123_2038_n59, DP_OP_154J10_123_2038_n58,
DP_OP_154J10_123_2038_n57, DP_OP_154J10_123_2038_n56,
DP_OP_154J10_123_2038_n55, DP_OP_154J10_123_2038_n54,
DP_OP_154J10_123_2038_n53, DP_OP_154J10_123_2038_n52,
DP_OP_154J10_123_2038_n51, DP_OP_154J10_123_2038_n50,
DP_OP_154J10_123_2038_n49, DP_OP_154J10_123_2038_n48,
DP_OP_154J10_123_2038_n47, DP_OP_154J10_123_2038_n46,
DP_OP_154J10_123_2038_n45, DP_OP_154J10_123_2038_n44,
DP_OP_154J10_123_2038_n43, DP_OP_154J10_123_2038_n42,
DP_OP_154J10_123_2038_n41, DP_OP_154J10_123_2038_n40,
DP_OP_154J10_123_2038_n39, DP_OP_154J10_123_2038_n38,
DP_OP_154J10_123_2038_n37, DP_OP_154J10_123_2038_n36,
DP_OP_154J10_123_2038_n35, DP_OP_154J10_123_2038_n34,
DP_OP_154J10_123_2038_n33, DP_OP_154J10_123_2038_n32,
DP_OP_154J10_123_2038_n31, DP_OP_154J10_123_2038_n30,
DP_OP_154J10_123_2038_n29, DP_OP_154J10_123_2038_n28,
DP_OP_154J10_123_2038_n27, DP_OP_154J10_123_2038_n26,
DP_OP_154J10_123_2038_n25, DP_OP_154J10_123_2038_n24,
DP_OP_154J10_123_2038_n23, DP_OP_154J10_123_2038_n22,
DP_OP_154J10_123_2038_n21, DP_OP_154J10_123_2038_n20,
DP_OP_154J10_123_2038_n19, DP_OP_154J10_123_2038_n18,
DP_OP_153J10_122_5442_n414, DP_OP_153J10_122_5442_n413,
DP_OP_153J10_122_5442_n412, DP_OP_153J10_122_5442_n407,
DP_OP_153J10_122_5442_n406, DP_OP_153J10_122_5442_n405,
DP_OP_153J10_122_5442_n404, DP_OP_153J10_122_5442_n403,
DP_OP_153J10_122_5442_n400, DP_OP_153J10_122_5442_n399,
DP_OP_153J10_122_5442_n398, DP_OP_153J10_122_5442_n397,
DP_OP_153J10_122_5442_n396, DP_OP_153J10_122_5442_n394,
DP_OP_153J10_122_5442_n393, DP_OP_153J10_122_5442_n392,
DP_OP_153J10_122_5442_n380, DP_OP_153J10_122_5442_n377,
DP_OP_153J10_122_5442_n376, DP_OP_153J10_122_5442_n375,
DP_OP_153J10_122_5442_n374, DP_OP_153J10_122_5442_n373,
DP_OP_153J10_122_5442_n372, DP_OP_153J10_122_5442_n371,
DP_OP_153J10_122_5442_n370, DP_OP_153J10_122_5442_n369,
DP_OP_153J10_122_5442_n368, DP_OP_153J10_122_5442_n367,
DP_OP_153J10_122_5442_n366, DP_OP_153J10_122_5442_n365,
DP_OP_153J10_122_5442_n364, DP_OP_153J10_122_5442_n363,
DP_OP_153J10_122_5442_n362, DP_OP_153J10_122_5442_n361,
DP_OP_153J10_122_5442_n360, DP_OP_153J10_122_5442_n359,
DP_OP_153J10_122_5442_n311, DP_OP_153J10_122_5442_n306,
DP_OP_153J10_122_5442_n305, DP_OP_153J10_122_5442_n296,
DP_OP_153J10_122_5442_n293, DP_OP_153J10_122_5442_n292,
DP_OP_153J10_122_5442_n290, DP_OP_153J10_122_5442_n289,
DP_OP_153J10_122_5442_n288, DP_OP_153J10_122_5442_n287,
DP_OP_153J10_122_5442_n282, DP_OP_153J10_122_5442_n274,
DP_OP_153J10_122_5442_n273, DP_OP_153J10_122_5442_n271,
DP_OP_153J10_122_5442_n270, DP_OP_153J10_122_5442_n269,
DP_OP_153J10_122_5442_n268, DP_OP_153J10_122_5442_n266,
DP_OP_153J10_122_5442_n265, DP_OP_153J10_122_5442_n264,
DP_OP_153J10_122_5442_n263, DP_OP_153J10_122_5442_n262,
DP_OP_153J10_122_5442_n261, DP_OP_153J10_122_5442_n259,
DP_OP_153J10_122_5442_n258, DP_OP_153J10_122_5442_n257,
DP_OP_153J10_122_5442_n256, DP_OP_153J10_122_5442_n255,
DP_OP_153J10_122_5442_n254, DP_OP_153J10_122_5442_n253,
DP_OP_153J10_122_5442_n252, DP_OP_153J10_122_5442_n251,
DP_OP_153J10_122_5442_n250, DP_OP_153J10_122_5442_n249,
DP_OP_153J10_122_5442_n248, DP_OP_153J10_122_5442_n247,
DP_OP_153J10_122_5442_n234, DP_OP_153J10_122_5442_n229,
DP_OP_153J10_122_5442_n228, DP_OP_153J10_122_5442_n227,
DP_OP_153J10_122_5442_n224, DP_OP_153J10_122_5442_n205,
DP_OP_153J10_122_5442_n204, DP_OP_153J10_122_5442_n203,
DP_OP_153J10_122_5442_n202, DP_OP_153J10_122_5442_n201,
DP_OP_153J10_122_5442_n200, DP_OP_153J10_122_5442_n196,
DP_OP_153J10_122_5442_n195, DP_OP_153J10_122_5442_n194,
DP_OP_153J10_122_5442_n193, DP_OP_153J10_122_5442_n192,
DP_OP_153J10_122_5442_n191, DP_OP_153J10_122_5442_n187,
DP_OP_153J10_122_5442_n186, DP_OP_153J10_122_5442_n185,
DP_OP_153J10_122_5442_n184, DP_OP_153J10_122_5442_n183,
DP_OP_153J10_122_5442_n182, DP_OP_153J10_122_5442_n177,
DP_OP_153J10_122_5442_n176, DP_OP_153J10_122_5442_n175,
DP_OP_153J10_122_5442_n174, DP_OP_153J10_122_5442_n173,
DP_OP_153J10_122_5442_n169, DP_OP_153J10_122_5442_n167,
DP_OP_153J10_122_5442_n166, DP_OP_153J10_122_5442_n165,
DP_OP_153J10_122_5442_n162, DP_OP_153J10_122_5442_n161,
DP_OP_153J10_122_5442_n159, DP_OP_153J10_122_5442_n158,
DP_OP_153J10_122_5442_n157, DP_OP_153J10_122_5442_n156,
DP_OP_153J10_122_5442_n155, DP_OP_153J10_122_5442_n154,
DP_OP_153J10_122_5442_n151, DP_OP_153J10_122_5442_n150,
DP_OP_153J10_122_5442_n149, DP_OP_153J10_122_5442_n148,
DP_OP_153J10_122_5442_n145, DP_OP_153J10_122_5442_n133,
DP_OP_153J10_122_5442_n128, DP_OP_153J10_122_5442_n127,
DP_OP_153J10_122_5442_n125, DP_OP_153J10_122_5442_n124,
DP_OP_153J10_122_5442_n123, DP_OP_153J10_122_5442_n122,
DP_OP_153J10_122_5442_n121, DP_OP_153J10_122_5442_n120,
DP_OP_153J10_122_5442_n119, DP_OP_153J10_122_5442_n118,
DP_OP_153J10_122_5442_n117, DP_OP_153J10_122_5442_n116,
DP_OP_153J10_122_5442_n115, DP_OP_153J10_122_5442_n113,
DP_OP_153J10_122_5442_n112, DP_OP_153J10_122_5442_n111,
DP_OP_153J10_122_5442_n110, DP_OP_153J10_122_5442_n109,
DP_OP_153J10_122_5442_n108, DP_OP_153J10_122_5442_n107,
DP_OP_153J10_122_5442_n106, DP_OP_153J10_122_5442_n105,
DP_OP_153J10_122_5442_n104, DP_OP_153J10_122_5442_n103,
DP_OP_153J10_122_5442_n102, DP_OP_153J10_122_5442_n101,
DP_OP_153J10_122_5442_n100, DP_OP_153J10_122_5442_n99,
DP_OP_153J10_122_5442_n98, DP_OP_153J10_122_5442_n97,
DP_OP_153J10_122_5442_n95, DP_OP_153J10_122_5442_n94,
DP_OP_153J10_122_5442_n93, DP_OP_153J10_122_5442_n92,
DP_OP_153J10_122_5442_n91, DP_OP_153J10_122_5442_n90,
DP_OP_153J10_122_5442_n89, DP_OP_153J10_122_5442_n88,
DP_OP_153J10_122_5442_n87, DP_OP_153J10_122_5442_n84,
DP_OP_153J10_122_5442_n83, DP_OP_153J10_122_5442_n82,
DP_OP_153J10_122_5442_n81, DP_OP_153J10_122_5442_n80,
DP_OP_153J10_122_5442_n79, DP_OP_153J10_122_5442_n78,
DP_OP_153J10_122_5442_n77, DP_OP_153J10_122_5442_n76,
DP_OP_153J10_122_5442_n75, DP_OP_153J10_122_5442_n74,
DP_OP_153J10_122_5442_n73, DP_OP_153J10_122_5442_n72,
DP_OP_153J10_122_5442_n71, DP_OP_153J10_122_5442_n70,
DP_OP_153J10_122_5442_n69, DP_OP_153J10_122_5442_n68,
DP_OP_153J10_122_5442_n67, DP_OP_153J10_122_5442_n66,
DP_OP_153J10_122_5442_n65, DP_OP_153J10_122_5442_n64,
DP_OP_153J10_122_5442_n63, DP_OP_153J10_122_5442_n62,
DP_OP_153J10_122_5442_n61, DP_OP_153J10_122_5442_n60,
DP_OP_153J10_122_5442_n59, DP_OP_153J10_122_5442_n58,
DP_OP_153J10_122_5442_n57, DP_OP_153J10_122_5442_n56,
DP_OP_153J10_122_5442_n55, DP_OP_153J10_122_5442_n54,
DP_OP_153J10_122_5442_n53, DP_OP_153J10_122_5442_n52,
DP_OP_153J10_122_5442_n51, DP_OP_153J10_122_5442_n50,
DP_OP_153J10_122_5442_n49, DP_OP_153J10_122_5442_n48,
DP_OP_153J10_122_5442_n47, DP_OP_153J10_122_5442_n46,
DP_OP_153J10_122_5442_n45, DP_OP_153J10_122_5442_n44,
DP_OP_153J10_122_5442_n43, DP_OP_153J10_122_5442_n42,
DP_OP_153J10_122_5442_n41, DP_OP_153J10_122_5442_n40,
DP_OP_153J10_122_5442_n38, DP_OP_153J10_122_5442_n37,
DP_OP_153J10_122_5442_n36, DP_OP_153J10_122_5442_n35,
DP_OP_153J10_122_5442_n34, DP_OP_153J10_122_5442_n33,
DP_OP_153J10_122_5442_n32, DP_OP_153J10_122_5442_n31,
DP_OP_153J10_122_5442_n30, DP_OP_153J10_122_5442_n29,
DP_OP_153J10_122_5442_n28, DP_OP_153J10_122_5442_n27,
DP_OP_153J10_122_5442_n26, DP_OP_153J10_122_5442_n25,
DP_OP_153J10_122_5442_n23, DP_OP_153J10_122_5442_n22,
DP_OP_153J10_122_5442_n21, n391, n392, n393, n394, n395, n396, n397,
n398, n399, n400, n401, n402, n403, n404, n405, n406, n407, n408,
n409, n410, n411, n412, n413, n416, n417, n418, n419, n420, n421,
n422, n423, n424, n425, n426, n427, n428, n429, n430, n431, n432,
n433, n434, n435, n436, n437, n438, n439, n440, n441, n442, n443,
n444, n445, n446, n447, n448, n449, n450, n451, n452, n453, n454,
n455, n456, n457, n458, n459, n460, n461, n462, n463, n464, n465,
n466, n467, n468, n469, n470, n471, n472, n473, n474, n475, n476,
n477, n478, n479, n480, n481, n482, n483, n484, n485, n486, n487,
n488, n489, n490, n491, n492, n493, n495, n496, n498, n499, n500,
n501, n502, n503, n504, n505, n506, n507, n508, n509, n510, n511,
n512, n513, n514, n515, n516, n517, n518, n519, n520, n521, n522,
n523, n524, n525, n526, n527, n528, n529, n530, n531, n532, n533,
n534, n535, n536, n537, n538, n539, n540, n541, n542, n543, n544,
n545, n546, n547, n548, n549, n550, n551, n552, n553, n554, n555,
n556, n557, n558, n559, n560, n561, n562, n563, n564, n565, n566,
n567, n568, n569, n570, n571, n572, n573, n574, n575, n576, n577,
n578, n579, n580, n581, n582, n583, n584, n585, n586, n587, n588,
n589, n590, n591, n592, n593, n594, n595, n596, n597, n598, n599,
n600, n601, n602, n603, n604, n605, n606, n607, n608, n609, n610,
n611, n612, n613, n614, n615, n616, n617, n618, n619, n620, n621,
n622, n623, n624, n625, n626, n627, n628, n629, n630, n631, n632,
n633, n634, n635, n636, n637, n638, n639, n640, n641, n642, n643,
n644, n645, n646, n647, n648, n649, n650, n651, n652, n653, n654,
n655, n656, n657, n658, n659, n660, n661, n662, n663, n664, n665,
n666, n667, n668, n669, n670, n671, n672, n673, n674, n675, n676,
n677, n678, n679, n680, n681, n682, n683, n684, n685, n686, n687,
n688, n689, n690, n691, n692, n693, n694, n695, n696, n697, n698,
n699, n700, n701, n702, n703, n704, n705, n706, n707, n708, n709,
n710, n711, n712, n713, n714, n715, n716, n717, n718, n719, n720,
n722, n723, n724, n725, n726, n727, n728, n729, n730, n731, n732,
n733, n734, n735, n736, n737, n738, n739, n740, n741, n742, n743,
n744, n745, n746, n747, n748, n750, n751, n752, n753, n754, n755,
n756, n757, n758, n759, n760, n761, n762, n763, n764, n765, n766,
n767, n768, n769, n770, n771, n772, n773, n775, n776, n777, n778,
n779, n780, n781, n782, n783, n784, n785, n786, n787, n788, n789,
n790, n791, n792, n793, n794, n795, n796, n797, n798, n799, n800,
n801, n802, n803, n804, n805, n806, n807, n808, n809, n810, n811,
n812, n813, n814, n815, n816, n817, n818, n819, n820, n821, n822,
n823, n824, n825, n826, n827, n828, n829, n830, n831, n832, n833,
n834, n835, n836, n837, n838, n839, n840, n841, n842, n843, n844,
n845, n846, n847, n848, n849, n850, n851, n852, n853, n854, n855,
n856, n857, n858, n859, n860, n861, n862, n863, n864, n865, n866,
n867, n868, n869, n870, n871, n872, n873, n874, n875, n876, n877,
n878, n879, n880, n881, n882, n883, n884, n885, n886, n887, n888,
n889, n890, n891, n892, n893, n894, n895, n896, n897, n898, n899,
n900, n901, n902, n903, n904, n905, n906, n907, n908, n909, n910,
n911, n912, n913, n914, n915, n916, n917, n918, n919, n920, n921,
n922, n923, n924, n925, n926, n927, n928, n929, n930, n931, n932,
n933, n934, n935, n936, n937, n938, n939, n940, n941, n942, n943,
n944, n945, n946, n947, n948, n949, n950, n951, n952, n953, n954,
n955, n956, n957, n958, n959, n960, n961, n962, n963, n964, n965,
n966, n967, n968, n969, n970, n971, n972, n973, n974, n975, n976,
n977, n978, n979, n980, n981, n982, n983, n984, n985, n986, n987,
n988, n989, n990, n991, n992, n993, n994, n995, n996, n997, n998,
n999, n1000, n1001, n1002, n1003, n1004, n1005, n1006, n1007, n1008,
n1009, n1010, n1011, n1012, n1013, n1014, n1015, n1016, n1017, n1018,
n1019, n1020, n1021, n1022, n1023, n1024, n1025, n1026, n1027, n1028,
n1029, n1030, n1031, n1032, n1033, n1034, n1035, n1036, n1037, n1038,
n1039, n1040, n1041, n1042, n1043, n1044, n1045, n1046, n1047, n1048,
n1049, n1050, n1051, n1052, n1053, n1054, n1055, n1056, n1057, n1058,
n1059, n1060, n1061, n1062, n1063, n1064, n1065, n1066, n1067, n1068,
n1069, n1070, n1071, n1072, n1073, n1074, n1075, n1076, n1077, n1078,
n1079, n1080, n1081, n1082, n1083, n1084, n1085, n1086, n1087, n1088,
n1089, n1090, n1091, n1092, n1093, n1094, n1095, n1096, n1097, n1098,
n1099, n1100, n1101, n1102, n1103, n1104, n1105, n1106, n1107, n1108,
n1109, n1110, n1111, n1112, n1113, n1114, n1115, n1116, n1117, n1118,
n1119, n1120, n1121, n1122, n1123, n1124, n1125, n1126, n1127, n1128,
n1129, n1130, n1131, n1132, n1133, n1134, n1135, n1136, n1137, n1138,
n1139, n1140, n1141, n1142, n1143, n1144, n1145, n1146, n1147, n1148,
n1149, n1150, n1151, n1152, n1153, n1154, n1155, n1156, n1157, n1158,
n1159, n1160, n1161, n1162, n1163, n1164, n1165, n1166, n1167, n1168,
n1169, n1170, n1171, n1172, n1173, n1174, n1175, n1176, n1177, n1178,
n1179, n1180, n1181, n1182, n1183, n1184, n1185, n1186, n1187, n1188,
n1189, n1190, n1191, n1192, n1193, n1194, n1195, n1196, n1197, n1198,
n1199, n1200, n1201, n1202, n1203, n1204, n1205, n1206, n1207, n1208,
n1209, n1210, n1211, n1212, n1213, n1214, n1215, n1216, n1217, n1218,
n1219, n1220, n1221, n1222, n1223, n1224, n1225, n1226, n1227, n1228,
n1229, n1230, n1231, n1232, n1233, n1234, n1235, n1236, n1237, n1238,
n1239, n1240, n1241, n1242, n1243, n1244, n1245, n1246, n1247, n1248,
n1249, n1250, n1251, n1252, n1253, n1254, n1255, n1256, n1257, n1258,
n1259, n1260, n1261, n1262, n1263, n1264, n1265, n1266, n1267, n1268,
n1269, n1270, n1271, n1272, n1273, n1274, n1275, n1276, n1277, n1278,
n1279, n1280, n1281, n1282, n1283, n1284, n1285, n1286, n1287, n1288,
n1289, n1290, n1291, n1292, n1293, n1294, n1295, n1296, n1298, n1299,
n1300, n1301, n1302, n1303, n1304, n1305, n1306, n1307, n1308, n1309,
n1310, n1311, n1312, n1313, n1314, n1315, n1316, n1317, n1318, n1319,
n1320, n1321, n1322, n1323, n1324, n1325, n1326, n1327, n1328, n1329,
n1330, n1331, n1332, n1333, n1334, n1335, n1336, n1337, n1338, n1339,
n1340, n1341, n1342, n1343, n1344, n1345, n1347, n1348, n1349, n1350,
n1352, n1353, n1355, n1356, n1357, n1358, n1359, n1360, n1361, n1362,
n1363, n1364, n1365, n1366, n1367, n1368, n1369, n1370, n1371, n1372,
n1373, n1374, n1375, n1376, n1377, n1378, n1379, n1380, n1381, n1382,
n1383, n1384, n1385, n1386, n1387, n1388, n1389, n1390, n1391, n1392,
n1393, n1394, n1395, n1396, n1397, n1398, n1399, n1400, n1401, n1402,
n1403, n1404, n1405, n1406, n1407, n1408, n1409, n1410, n1411, n1412,
n1413, n1414, n1415, n1416, n1417, n1418, n1419, n1420, n1421, n1422,
n1423, n1424, n1425, n1426, n1427, n1428, n1429, n1430, n1431, n1432,
n1433, n1434, n1435, n1436, n1437, n1438, n1439, n1440, n1441, n1442,
n1443, n1444, n1445, n1446, n1447, n1448, n1449, n1450, n1451, n1452,
n1453, n1454, n1455, n1456, n1457, n1458, n1459, n1460, n1461, n1462,
n1463, n1464, n1465, n1466, n1467, n1468, n1469, n1470, n1471, n1472,
n1473, n1474, n1475, n1476, n1477, n1478, n1479, n1480, n1481, n1482,
n1483, n1484, n1485, n1486, n1487, n1488, n1489, n1490, n1491, n1492,
n1493, n1494, n1495, n1496, n1497, n1498, n1499, n1500, n1501, n1502,
n1503, n1504, n1505, n1506, n1507, n1508, n1509, n1510, n1511, n1512,
n1513, n1514, n1515, n1516, n1517, n1518, n1519, n1520, n1521, n1522,
n1523, n1524, n1525, n1526, n1527, n1528, n1529, n1530, n1531, n1532,
n1533, n1534, n1535, n1536, n1537, n1538, n1539, n1540, n1541, n1542,
n1543, n1544, n1545, n1546, n1547, n1548, n1549, n1550, n1551, n1552,
n1553, n1554, n1555, n1556, n1557, n1558, n1559, n1560, n1561, n1562,
n1563, n1564, n1565, n1566, n1567, n1568, n1569, n1570, n1571, n1572,
n1573, n1574, n1575, n1576, n1577, n1578, n1579, n1580, n1581, n1582,
n1583, n1584, n1585, n1586, n1587, n1588, n1589, n1590, n1591, n1592,
n1593, n1594, n1595, n1596, n1597, n1598, n1599, n1600, n1601, n1602,
n1603, n1604, n1605, n1606, n1607, n1608, n1609, n1610, n1611, n1612,
n1613, n1614, n1615, n1616, n1617, n1618, n1619, n1620, n1621, n1622,
n1623, n1624, n1625, n1626, n1627, n1628, n1629, n1630, n1631, n1632,
n1633, n1634, n1635, n1636, n1637, n1638, n1639, n1640, n1641, n1642,
n1643, n1644, n1645, n1646, n1647, n1648, n1649, n1650, n1651, n1652,
n1653, n1654, n1655, n1656, n1657, n1658, n1659, n1660, n1661, n1662,
n1663, n1664, n1665, n1666, n1667, n1668, n1669, n1670, n1671, n1672,
n1673, n1674, n1675, n1676, n1677, n1678, n1679, n1680, n1681, n1682,
n1683, n1684, n1685, n1686, n1687, n1688, n1689, n1690, n1691, n1692,
n1693, n1694, n1695, n1696, n1697, n1698, n1699, n1700, n1701, n1702,
n1703, n1704, n1705, n1706, n1707, n1708, n1709, n1710, n1711, n1712,
n1713, n1714, n1715, n1716, n1717, n1718, n1719, n1720, n1721, n1722;
wire [47:0] P_Sgf;
wire [1:0] FSM_selector_B;
wire [31:0] Op_MX;
wire [31:0] Op_MY;
wire [8:0] exp_oper_result;
wire [8:0] S_Oper_A_exp;
wire [23:0] Add_result;
wire [23:0] Sgf_normalized_result;
wire [3:0] FS_Module_state_reg;
wire [8:0] Exp_module_Data_S;
wire [11:8] Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left;
wire [16:1] Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B;
wire [13:8] Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right;
wire [9:0] Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left;
wire [11:8] Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left;
DFFRXLTS Operands_load_reg_YMRegister_Q_reg_31_ ( .D(n381), .CK(clk), .RN(
n1715), .Q(Op_MY[31]) );
DFFRXLTS Zero_Result_Detect_Zero_Info_Mult_Q_reg_0_ ( .D(n311), .CK(clk),
.RN(n1710), .Q(zero_flag), .QN(n430) );
DFFRXLTS Operands_load_reg_XMRegister_Q_reg_30_ ( .D(n374), .CK(clk), .RN(
n1709), .QN(n428) );
DFFRXLTS Operands_load_reg_XMRegister_Q_reg_29_ ( .D(n373), .CK(clk), .RN(
n1717), .QN(n409) );
DFFRXLTS Operands_load_reg_XMRegister_Q_reg_14_ ( .D(n358), .CK(clk), .RN(
n1709), .Q(Op_MX[14]), .QN(n417) );
DFFRXLTS Operands_load_reg_XMRegister_Q_reg_12_ ( .D(n356), .CK(clk), .RN(
n1713), .Q(Op_MX[12]), .QN(n418) );
DFFRXLTS Operands_load_reg_XMRegister_Q_reg_8_ ( .D(n352), .CK(clk), .RN(
n1715), .QN(n397) );
DFFRXLTS Operands_load_reg_XMRegister_Q_reg_6_ ( .D(n350), .CK(clk), .RN(
n1715), .QN(n394) );
DFFRXLTS Operands_load_reg_XMRegister_Q_reg_1_ ( .D(n345), .CK(clk), .RN(
n1718), .QN(n412) );
DFFRXLTS Operands_load_reg_XMRegister_Q_reg_31_ ( .D(n343), .CK(clk), .RN(
n1716), .Q(Op_MX[31]) );
DFFRXLTS Adder_M_Add_Subt_Result_Q_reg_22_ ( .D(n287), .CK(clk), .RN(n1709),
.QN(n439) );
DFFRXLTS Adder_M_Add_Subt_Result_Q_reg_21_ ( .D(n288), .CK(clk), .RN(n1708),
.QN(n448) );
DFFRXLTS Adder_M_Add_Subt_Result_Q_reg_20_ ( .D(n289), .CK(clk), .RN(n393),
.QN(n438) );
DFFRXLTS Adder_M_Add_Subt_Result_Q_reg_19_ ( .D(n290), .CK(clk), .RN(n393),
.QN(n447) );
DFFRXLTS Adder_M_Add_Subt_Result_Q_reg_18_ ( .D(n291), .CK(clk), .RN(n1715),
.QN(n437) );
DFFRXLTS Adder_M_Add_Subt_Result_Q_reg_17_ ( .D(n292), .CK(clk), .RN(n1714),
.QN(n446) );
DFFRXLTS Adder_M_Add_Subt_Result_Q_reg_16_ ( .D(n293), .CK(clk), .RN(n1712),
.QN(n436) );
DFFRXLTS Adder_M_Add_Subt_Result_Q_reg_15_ ( .D(n294), .CK(clk), .RN(n1713),
.QN(n445) );
DFFRXLTS Adder_M_Add_Subt_Result_Q_reg_14_ ( .D(n295), .CK(clk), .RN(n1712),
.QN(n435) );
DFFRXLTS Adder_M_Add_Subt_Result_Q_reg_13_ ( .D(n296), .CK(clk), .RN(n1712),
.QN(n444) );
DFFRXLTS Adder_M_Add_Subt_Result_Q_reg_12_ ( .D(n297), .CK(clk), .RN(n1709),
.QN(n434) );
DFFRXLTS Adder_M_Add_Subt_Result_Q_reg_11_ ( .D(n298), .CK(clk), .RN(n1718),
.QN(n443) );
DFFRXLTS Adder_M_Add_Subt_Result_Q_reg_10_ ( .D(n299), .CK(clk), .RN(n1714),
.QN(n433) );
DFFRXLTS Adder_M_Add_Subt_Result_Q_reg_9_ ( .D(n300), .CK(clk), .RN(n1714),
.QN(n442) );
DFFRXLTS Adder_M_Add_Subt_Result_Q_reg_8_ ( .D(n301), .CK(clk), .RN(n1713),
.QN(n432) );
DFFRXLTS Adder_M_Add_Subt_Result_Q_reg_7_ ( .D(n302), .CK(clk), .RN(n393),
.QN(n441) );
DFFRXLTS Adder_M_Add_Subt_Result_Q_reg_6_ ( .D(n303), .CK(clk), .RN(n1710),
.QN(n431) );
DFFRXLTS Adder_M_Add_Subt_Result_Q_reg_5_ ( .D(n304), .CK(clk), .RN(n393),
.QN(n451) );
DFFRXLTS Adder_M_Add_Subt_Result_Q_reg_4_ ( .D(n305), .CK(clk), .RN(n1711),
.QN(n449) );
DFFRXLTS Adder_M_Add_Subt_Result_Q_reg_3_ ( .D(n306), .CK(clk), .RN(n1716),
.QN(n450) );
DFFRXLTS Adder_M_Add_Subt_Result_Q_reg_1_ ( .D(n308), .CK(clk), .RN(n1710),
.QN(n440) );
DFFRXLTS Adder_M_Add_Subt_Result_Q_reg_0_ ( .D(n309), .CK(clk), .RN(n1709),
.Q(Add_result[0]) );
DFFRXLTS Adder_M_Add_Subt_Result_Q_reg_23_ ( .D(n286), .CK(clk), .RN(n1716),
.Q(Add_result[23]) );
DFFRXLTS Operands_load_reg_YMRegister_Q_reg_30_ ( .D(n342), .CK(clk), .RN(
n1716), .QN(n425) );
DFFRXLTS Operands_load_reg_YMRegister_Q_reg_29_ ( .D(n341), .CK(clk), .RN(
n393), .QN(n426) );
DFFRXLTS Operands_load_reg_YMRegister_Q_reg_28_ ( .D(n340), .CK(clk), .RN(
n1708), .QN(n408) );
DFFRXLTS Operands_load_reg_YMRegister_Q_reg_26_ ( .D(n338), .CK(clk), .RN(
n1717), .QN(n398) );
DFFRXLTS Operands_load_reg_YMRegister_Q_reg_25_ ( .D(n337), .CK(clk), .RN(
n1718), .QN(n407) );
DFFRXLTS Operands_load_reg_YMRegister_Q_reg_24_ ( .D(n336), .CK(clk), .RN(
n1717), .QN(n396) );
DFFRXLTS Operands_load_reg_YMRegister_Q_reg_15_ ( .D(n327), .CK(clk), .RN(
n1710), .QN(n416) );
DFFRXLTS Operands_load_reg_YMRegister_Q_reg_14_ ( .D(n326), .CK(clk), .RN(
n1718), .Q(Op_MY[14]), .QN(n401) );
DFFRXLTS Operands_load_reg_YMRegister_Q_reg_9_ ( .D(n321), .CK(clk), .RN(
n1709), .QN(n413) );
DFFRXLTS Operands_load_reg_YMRegister_Q_reg_8_ ( .D(n320), .CK(clk), .RN(
n1709), .QN(n399) );
DFFRXLTS Operands_load_reg_YMRegister_Q_reg_6_ ( .D(n318), .CK(clk), .RN(
n1715), .QN(n395) );
DFFRXLTS Operands_load_reg_YMRegister_Q_reg_1_ ( .D(n313), .CK(clk), .RN(
n1718), .QN(n400) );
DFFRXLTS Sgf_operation_EVEN1_finalreg_Q_reg_46_ ( .D(n284), .CK(clk), .RN(
n1719), .Q(P_Sgf[46]) );
DFFRXLTS Sgf_operation_EVEN1_finalreg_Q_reg_45_ ( .D(n283), .CK(clk), .RN(
n1720), .Q(P_Sgf[45]), .QN(n1691) );
DFFRXLTS Sgf_operation_EVEN1_finalreg_Q_reg_44_ ( .D(n282), .CK(clk), .RN(
n167), .Q(P_Sgf[44]), .QN(n1685) );
DFFRXLTS Sgf_operation_EVEN1_finalreg_Q_reg_43_ ( .D(n281), .CK(clk), .RN(
n1719), .Q(P_Sgf[43]), .QN(n1692) );
DFFRXLTS Sgf_operation_EVEN1_finalreg_Q_reg_42_ ( .D(n280), .CK(clk), .RN(
n1720), .Q(P_Sgf[42]), .QN(n1693) );
DFFRXLTS Sgf_operation_EVEN1_finalreg_Q_reg_41_ ( .D(n279), .CK(clk), .RN(
n167), .Q(P_Sgf[41]), .QN(n1694) );
DFFRXLTS Sgf_operation_EVEN1_finalreg_Q_reg_40_ ( .D(n278), .CK(clk), .RN(
n1719), .Q(P_Sgf[40]), .QN(n1695) );
DFFRXLTS Sgf_operation_EVEN1_finalreg_Q_reg_39_ ( .D(n277), .CK(clk), .RN(
n1720), .Q(P_Sgf[39]), .QN(n1696) );
DFFRXLTS Sgf_operation_EVEN1_finalreg_Q_reg_38_ ( .D(n276), .CK(clk), .RN(
n167), .Q(P_Sgf[38]), .QN(n1697) );
DFFRXLTS Sgf_operation_EVEN1_finalreg_Q_reg_37_ ( .D(n275), .CK(clk), .RN(
n1719), .Q(P_Sgf[37]), .QN(n1698) );
DFFRXLTS Sgf_operation_EVEN1_finalreg_Q_reg_36_ ( .D(n274), .CK(clk), .RN(
n1720), .Q(P_Sgf[36]), .QN(n1699) );
DFFRXLTS Sgf_operation_EVEN1_finalreg_Q_reg_35_ ( .D(n273), .CK(clk), .RN(
n167), .Q(P_Sgf[35]), .QN(n1700) );
DFFRXLTS Sgf_operation_EVEN1_finalreg_Q_reg_34_ ( .D(n272), .CK(clk), .RN(
n1719), .Q(P_Sgf[34]), .QN(n1701) );
DFFRXLTS Sgf_operation_EVEN1_finalreg_Q_reg_33_ ( .D(n271), .CK(clk), .RN(
n1720), .Q(P_Sgf[33]), .QN(n1702) );
DFFRXLTS Sgf_operation_EVEN1_finalreg_Q_reg_32_ ( .D(n270), .CK(clk), .RN(
n167), .Q(P_Sgf[32]), .QN(n1703) );
DFFRXLTS Sgf_operation_EVEN1_finalreg_Q_reg_31_ ( .D(n269), .CK(clk), .RN(
n1719), .Q(P_Sgf[31]), .QN(n1704) );
DFFRXLTS Sgf_operation_EVEN1_finalreg_Q_reg_30_ ( .D(n268), .CK(clk), .RN(
n1720), .Q(P_Sgf[30]), .QN(n1705) );
DFFRXLTS Sgf_operation_EVEN1_finalreg_Q_reg_29_ ( .D(n267), .CK(clk), .RN(
n167), .Q(P_Sgf[29]), .QN(n1706) );
DFFRXLTS Sgf_operation_EVEN1_finalreg_Q_reg_28_ ( .D(n266), .CK(clk), .RN(
n1719), .Q(P_Sgf[28]), .QN(n1686) );
DFFRXLTS Sgf_operation_EVEN1_finalreg_Q_reg_27_ ( .D(n265), .CK(clk), .RN(
n1720), .Q(P_Sgf[27]), .QN(n1687) );
DFFRXLTS Sgf_operation_EVEN1_finalreg_Q_reg_26_ ( .D(n264), .CK(clk), .RN(
n167), .Q(P_Sgf[26]), .QN(n1688) );
DFFRXLTS Sgf_operation_EVEN1_finalreg_Q_reg_25_ ( .D(n263), .CK(clk), .RN(
n1719), .Q(P_Sgf[25]), .QN(n1689) );
DFFRXLTS Sgf_operation_EVEN1_finalreg_Q_reg_24_ ( .D(n262), .CK(clk), .RN(
n1720), .Q(P_Sgf[24]), .QN(n1690) );
DFFRXLTS Sgf_operation_EVEN1_finalreg_Q_reg_23_ ( .D(n261), .CK(clk), .RN(
n167), .Q(P_Sgf[23]) );
DFFRXLTS Sgf_operation_EVEN1_finalreg_Q_reg_22_ ( .D(n260), .CK(clk), .RN(
n1719), .Q(P_Sgf[22]) );
DFFRXLTS Sgf_operation_EVEN1_finalreg_Q_reg_21_ ( .D(n259), .CK(clk), .RN(
n1720), .Q(P_Sgf[21]) );
DFFRXLTS Sgf_operation_EVEN1_finalreg_Q_reg_20_ ( .D(n258), .CK(clk), .RN(
n167), .Q(P_Sgf[20]) );
DFFRXLTS Sgf_operation_EVEN1_finalreg_Q_reg_19_ ( .D(n257), .CK(clk), .RN(
n1719), .Q(P_Sgf[19]) );
DFFRXLTS Sgf_operation_EVEN1_finalreg_Q_reg_18_ ( .D(n256), .CK(clk), .RN(
n1720), .Q(P_Sgf[18]) );
DFFRXLTS Sgf_operation_EVEN1_finalreg_Q_reg_17_ ( .D(n255), .CK(clk), .RN(
n167), .Q(P_Sgf[17]) );
DFFRXLTS Sgf_operation_EVEN1_finalreg_Q_reg_16_ ( .D(n254), .CK(clk), .RN(
n1719), .Q(P_Sgf[16]) );
DFFRXLTS Sgf_operation_EVEN1_finalreg_Q_reg_15_ ( .D(n253), .CK(clk), .RN(
n1720), .Q(P_Sgf[15]) );
DFFRXLTS Sgf_operation_EVEN1_finalreg_Q_reg_14_ ( .D(n252), .CK(clk), .RN(
n167), .Q(P_Sgf[14]) );
DFFRXLTS Sgf_operation_EVEN1_finalreg_Q_reg_13_ ( .D(n251), .CK(clk), .RN(
n1719), .Q(P_Sgf[13]) );
DFFRXLTS Sgf_operation_EVEN1_finalreg_Q_reg_12_ ( .D(n250), .CK(clk), .RN(
n1721), .Q(P_Sgf[12]) );
DFFRXLTS Sgf_operation_EVEN1_finalreg_Q_reg_11_ ( .D(n249), .CK(clk), .RN(
n1721), .Q(P_Sgf[11]) );
DFFRXLTS Sgf_operation_EVEN1_finalreg_Q_reg_10_ ( .D(n248), .CK(clk), .RN(
n1721), .Q(P_Sgf[10]) );
DFFRXLTS Sgf_operation_EVEN1_finalreg_Q_reg_8_ ( .D(n246), .CK(clk), .RN(
n1721), .Q(P_Sgf[8]) );
DFFRXLTS Sgf_operation_EVEN1_finalreg_Q_reg_7_ ( .D(n245), .CK(clk), .RN(
n1721), .Q(P_Sgf[7]) );
DFFRXLTS Sgf_operation_EVEN1_finalreg_Q_reg_6_ ( .D(n244), .CK(clk), .RN(
n1721), .Q(P_Sgf[6]) );
DFFRXLTS Sgf_operation_EVEN1_finalreg_Q_reg_5_ ( .D(n243), .CK(clk), .RN(
n1721), .Q(P_Sgf[5]) );
DFFRXLTS Sgf_operation_EVEN1_finalreg_Q_reg_4_ ( .D(n242), .CK(clk), .RN(
n1721), .Q(P_Sgf[4]) );
DFFRXLTS Sgf_operation_EVEN1_finalreg_Q_reg_3_ ( .D(n241), .CK(clk), .RN(
n1721), .Q(P_Sgf[3]) );
DFFRXLTS Sgf_operation_EVEN1_finalreg_Q_reg_2_ ( .D(n240), .CK(clk), .RN(
n1721), .Q(P_Sgf[2]) );
DFFRXLTS Sgf_operation_EVEN1_finalreg_Q_reg_1_ ( .D(n239), .CK(clk), .RN(
n167), .Q(P_Sgf[1]) );
DFFRXLTS Sgf_operation_EVEN1_finalreg_Q_reg_0_ ( .D(n238), .CK(clk), .RN(
n167), .Q(P_Sgf[0]) );
DFFRXLTS Exp_module_Oflow_A_m_Q_reg_0_ ( .D(n225), .CK(clk), .RN(n1714), .Q(
Exp_module_Overflow_flag_A) );
DFFRXLTS Barrel_Shifter_module_Output_Reg_Q_reg_2_ ( .D(n204), .CK(clk),
.RN(n1716), .QN(n406) );
DFFRXLTS Barrel_Shifter_module_Output_Reg_Q_reg_1_ ( .D(n203), .CK(clk),
.RN(n1718), .QN(n423) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_0_ ( .D(n200),
.CK(clk), .RN(n1710), .Q(final_result_ieee[0]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_1_ ( .D(n199),
.CK(clk), .RN(n1712), .Q(final_result_ieee[1]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_2_ ( .D(n198),
.CK(clk), .RN(n1711), .Q(final_result_ieee[2]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_3_ ( .D(n197),
.CK(clk), .RN(n1713), .Q(final_result_ieee[3]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_4_ ( .D(n196),
.CK(clk), .RN(n1715), .Q(final_result_ieee[4]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_5_ ( .D(n195),
.CK(clk), .RN(n1717), .Q(final_result_ieee[5]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_6_ ( .D(n194),
.CK(clk), .RN(n393), .Q(final_result_ieee[6]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_7_ ( .D(n193),
.CK(clk), .RN(n393), .Q(final_result_ieee[7]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_8_ ( .D(n192),
.CK(clk), .RN(n1708), .Q(final_result_ieee[8]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_9_ ( .D(n191),
.CK(clk), .RN(n393), .Q(final_result_ieee[9]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_10_ ( .D(n190),
.CK(clk), .RN(n1716), .Q(final_result_ieee[10]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_11_ ( .D(n189),
.CK(clk), .RN(n1708), .Q(final_result_ieee[11]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_12_ ( .D(n188),
.CK(clk), .RN(n1709), .Q(final_result_ieee[12]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_13_ ( .D(n187),
.CK(clk), .RN(n1722), .Q(final_result_ieee[13]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_14_ ( .D(n186),
.CK(clk), .RN(n1722), .Q(final_result_ieee[14]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_15_ ( .D(n185),
.CK(clk), .RN(n1722), .Q(final_result_ieee[15]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_16_ ( .D(n184),
.CK(clk), .RN(n1722), .Q(final_result_ieee[16]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_17_ ( .D(n183),
.CK(clk), .RN(n1722), .Q(final_result_ieee[17]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_18_ ( .D(n182),
.CK(clk), .RN(n1722), .Q(final_result_ieee[18]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_19_ ( .D(n181),
.CK(clk), .RN(n1722), .Q(final_result_ieee[19]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_20_ ( .D(n180),
.CK(clk), .RN(n1722), .Q(final_result_ieee[20]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_21_ ( .D(n179),
.CK(clk), .RN(n1712), .Q(final_result_ieee[21]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_22_ ( .D(n178),
.CK(clk), .RN(n1709), .Q(final_result_ieee[22]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_23_ ( .D(n177),
.CK(clk), .RN(n1717), .Q(final_result_ieee[23]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_24_ ( .D(n176),
.CK(clk), .RN(n1708), .Q(final_result_ieee[24]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_25_ ( .D(n175),
.CK(clk), .RN(n1717), .Q(final_result_ieee[25]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_26_ ( .D(n174),
.CK(clk), .RN(n1713), .Q(final_result_ieee[26]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_27_ ( .D(n173),
.CK(clk), .RN(n1711), .Q(final_result_ieee[27]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_28_ ( .D(n172),
.CK(clk), .RN(n1714), .Q(final_result_ieee[28]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_29_ ( .D(n171),
.CK(clk), .RN(n1711), .Q(final_result_ieee[29]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_30_ ( .D(n170),
.CK(clk), .RN(n1711), .Q(final_result_ieee[30]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_31_ ( .D(n168),
.CK(clk), .RN(n1709), .Q(final_result_ieee[31]), .QN(n1707) );
CMPR32X2TS DP_OP_36J10_126_4699_U9 ( .A(DP_OP_36J10_126_4699_n21), .B(
S_Oper_A_exp[1]), .C(DP_OP_36J10_126_4699_n9), .CO(
DP_OP_36J10_126_4699_n8), .S(Exp_module_Data_S[1]) );
CMPR32X2TS DP_OP_36J10_126_4699_U8 ( .A(DP_OP_36J10_126_4699_n20), .B(
S_Oper_A_exp[2]), .C(DP_OP_36J10_126_4699_n8), .CO(
DP_OP_36J10_126_4699_n7), .S(Exp_module_Data_S[2]) );
CMPR32X2TS DP_OP_36J10_126_4699_U7 ( .A(DP_OP_36J10_126_4699_n19), .B(
S_Oper_A_exp[3]), .C(DP_OP_36J10_126_4699_n7), .CO(
DP_OP_36J10_126_4699_n6), .S(Exp_module_Data_S[3]) );
CMPR32X2TS DP_OP_36J10_126_4699_U6 ( .A(DP_OP_36J10_126_4699_n18), .B(
S_Oper_A_exp[4]), .C(DP_OP_36J10_126_4699_n6), .CO(
DP_OP_36J10_126_4699_n5), .S(Exp_module_Data_S[4]) );
CMPR32X2TS DP_OP_36J10_126_4699_U5 ( .A(DP_OP_36J10_126_4699_n17), .B(
S_Oper_A_exp[5]), .C(DP_OP_36J10_126_4699_n5), .CO(
DP_OP_36J10_126_4699_n4), .S(Exp_module_Data_S[5]) );
CMPR32X2TS DP_OP_36J10_126_4699_U4 ( .A(DP_OP_36J10_126_4699_n16), .B(
S_Oper_A_exp[6]), .C(DP_OP_36J10_126_4699_n4), .CO(
DP_OP_36J10_126_4699_n3), .S(Exp_module_Data_S[6]) );
CMPR32X2TS DP_OP_36J10_126_4699_U3 ( .A(DP_OP_36J10_126_4699_n15), .B(
S_Oper_A_exp[7]), .C(DP_OP_36J10_126_4699_n3), .CO(
DP_OP_36J10_126_4699_n2), .S(Exp_module_Data_S[7]) );
CMPR32X2TS DP_OP_36J10_126_4699_U2 ( .A(DP_OP_36J10_126_4699_n33), .B(
S_Oper_A_exp[8]), .C(DP_OP_36J10_126_4699_n2), .CO(
DP_OP_36J10_126_4699_n1), .S(Exp_module_Data_S[8]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_23_ ( .D(n310), .CK(clk),
.RN(n1716), .Q(Sgf_normalized_result[23]), .QN(n1684) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_2_ ( .D(n307), .CK(clk), .RN(n1711),
.Q(Add_result[2]), .QN(n1683) );
DFFRX1TS Exp_module_Underflow_m_Q_reg_0_ ( .D(n201), .CK(clk), .RN(n1718),
.Q(underflow_flag), .QN(n1682) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_22_ ( .D(n224), .CK(clk),
.RN(n1712), .Q(Sgf_normalized_result[22]), .QN(n1680) );
DFFRX2TS FS_Module_state_reg_reg_0_ ( .D(n379), .CK(clk), .RN(n1719), .Q(
FS_Module_state_reg[0]), .QN(n1679) );
DFFRX1TS Sel_C_Q_reg_0_ ( .D(n375), .CK(clk), .RN(n393), .Q(FSM_selector_C),
.QN(n1678) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_20_ ( .D(n222), .CK(clk),
.RN(n1708), .Q(Sgf_normalized_result[20]), .QN(n1677) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_18_ ( .D(n220), .CK(clk),
.RN(n393), .Q(Sgf_normalized_result[18]), .QN(n1676) );
DFFRX2TS Sel_B_Q_reg_1_ ( .D(n235), .CK(clk), .RN(n1718), .Q(
FSM_selector_B[1]), .QN(n1675) );
DFFRX1TS Sel_B_Q_reg_0_ ( .D(n236), .CK(clk), .RN(n393), .Q(
FSM_selector_B[0]), .QN(n1674) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_16_ ( .D(n218), .CK(clk),
.RN(n1714), .Q(Sgf_normalized_result[16]), .QN(n1673) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_14_ ( .D(n216), .CK(clk),
.RN(n1713), .Q(Sgf_normalized_result[14]), .QN(n1672) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_12_ ( .D(n214), .CK(clk),
.RN(n393), .Q(Sgf_normalized_result[12]), .QN(n1671) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_10_ ( .D(n212), .CK(clk),
.RN(n1710), .Q(Sgf_normalized_result[10]), .QN(n1670) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_6_ ( .D(n208), .CK(clk),
.RN(n1714), .Q(Sgf_normalized_result[6]), .QN(n1668) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_4_ ( .D(n206), .CK(clk),
.RN(n1717), .Q(Sgf_normalized_result[4]), .QN(n1667) );
DFFRX2TS FS_Module_state_reg_reg_2_ ( .D(n377), .CK(clk), .RN(n1719), .Q(
FS_Module_state_reg[2]), .QN(n1666) );
CMPR42X1TS DP_OP_156J10_125_3370_U46 ( .A(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[8]), .B(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[1]), .C(
DP_OP_156J10_125_3370_n110), .D(DP_OP_156J10_125_3370_n133), .ICI(
DP_OP_156J10_125_3370_n81), .S(DP_OP_156J10_125_3370_n78), .ICO(
DP_OP_156J10_125_3370_n76), .CO(DP_OP_156J10_125_3370_n77) );
CMPR42X1TS DP_OP_156J10_125_3370_U45 ( .A(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[9]), .B(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[2]), .C(
DP_OP_156J10_125_3370_n109), .D(DP_OP_156J10_125_3370_n132), .ICI(
DP_OP_156J10_125_3370_n76), .S(DP_OP_156J10_125_3370_n75), .ICO(
DP_OP_156J10_125_3370_n73), .CO(DP_OP_156J10_125_3370_n74) );
CMPR42X1TS DP_OP_156J10_125_3370_U44 ( .A(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[10]), .B(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[3]), .C(
DP_OP_156J10_125_3370_n108), .D(DP_OP_156J10_125_3370_n131), .ICI(
DP_OP_156J10_125_3370_n73), .S(DP_OP_156J10_125_3370_n72), .ICO(
DP_OP_156J10_125_3370_n70), .CO(DP_OP_156J10_125_3370_n71) );
CMPR42X1TS DP_OP_156J10_125_3370_U43 ( .A(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[11]), .B(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[4]), .C(
DP_OP_156J10_125_3370_n107), .D(DP_OP_156J10_125_3370_n130), .ICI(
DP_OP_156J10_125_3370_n70), .S(DP_OP_156J10_125_3370_n69), .ICO(
DP_OP_156J10_125_3370_n67), .CO(DP_OP_156J10_125_3370_n68) );
CMPR42X1TS DP_OP_156J10_125_3370_U42 ( .A(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[12]), .B(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[5]), .C(
DP_OP_156J10_125_3370_n106), .D(DP_OP_156J10_125_3370_n129), .ICI(
DP_OP_156J10_125_3370_n67), .S(DP_OP_156J10_125_3370_n66), .ICO(
DP_OP_156J10_125_3370_n64), .CO(DP_OP_156J10_125_3370_n65) );
CMPR42X1TS DP_OP_156J10_125_3370_U41 ( .A(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[13]), .B(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[6]), .C(
DP_OP_156J10_125_3370_n105), .D(DP_OP_156J10_125_3370_n128), .ICI(
DP_OP_156J10_125_3370_n64), .S(DP_OP_156J10_125_3370_n63), .ICO(
DP_OP_156J10_125_3370_n61), .CO(DP_OP_156J10_125_3370_n62) );
CMPR42X1TS DP_OP_156J10_125_3370_U40 ( .A(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[0]), .B(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[7]), .C(
DP_OP_156J10_125_3370_n104), .D(DP_OP_156J10_125_3370_n127), .ICI(
DP_OP_156J10_125_3370_n61), .S(DP_OP_156J10_125_3370_n60), .ICO(
DP_OP_156J10_125_3370_n58), .CO(DP_OP_156J10_125_3370_n59) );
CMPR42X1TS DP_OP_156J10_125_3370_U39 ( .A(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[1]), .B(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[8]), .C(
DP_OP_156J10_125_3370_n103), .D(DP_OP_156J10_125_3370_n126), .ICI(
DP_OP_156J10_125_3370_n58), .S(DP_OP_156J10_125_3370_n57), .ICO(
DP_OP_156J10_125_3370_n55), .CO(DP_OP_156J10_125_3370_n56) );
CMPR42X1TS DP_OP_156J10_125_3370_U38 ( .A(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[2]), .B(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[9]), .C(
DP_OP_156J10_125_3370_n102), .D(DP_OP_156J10_125_3370_n125), .ICI(
DP_OP_156J10_125_3370_n55), .S(DP_OP_156J10_125_3370_n54), .ICO(
DP_OP_156J10_125_3370_n52), .CO(DP_OP_156J10_125_3370_n53) );
CMPR42X1TS DP_OP_156J10_125_3370_U37 ( .A(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[3]), .B(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[10]), .C(
DP_OP_156J10_125_3370_n101), .D(DP_OP_156J10_125_3370_n124), .ICI(
DP_OP_156J10_125_3370_n52), .S(DP_OP_156J10_125_3370_n51), .ICO(
DP_OP_156J10_125_3370_n49), .CO(DP_OP_156J10_125_3370_n50) );
CMPR42X1TS DP_OP_156J10_125_3370_U36 ( .A(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[4]), .B(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[11]), .C(
DP_OP_156J10_125_3370_n100), .D(DP_OP_156J10_125_3370_n123), .ICI(
DP_OP_156J10_125_3370_n49), .S(DP_OP_156J10_125_3370_n48), .ICO(
DP_OP_156J10_125_3370_n46), .CO(DP_OP_156J10_125_3370_n47) );
CMPR42X1TS DP_OP_156J10_125_3370_U35 ( .A(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[5]), .B(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[12]), .C(
DP_OP_156J10_125_3370_n99), .D(DP_OP_156J10_125_3370_n122), .ICI(
DP_OP_156J10_125_3370_n46), .S(DP_OP_156J10_125_3370_n45), .ICO(
DP_OP_156J10_125_3370_n43), .CO(DP_OP_156J10_125_3370_n44) );
CMPR42X1TS DP_OP_156J10_125_3370_U34 ( .A(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[6]), .B(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[13]), .C(
DP_OP_156J10_125_3370_n98), .D(DP_OP_156J10_125_3370_n121), .ICI(
DP_OP_156J10_125_3370_n43), .S(DP_OP_156J10_125_3370_n42), .ICO(
DP_OP_156J10_125_3370_n40), .CO(DP_OP_156J10_125_3370_n41) );
CMPR42X1TS DP_OP_156J10_125_3370_U33 ( .A(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[7]), .B(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[14]), .C(
DP_OP_156J10_125_3370_n97), .D(DP_OP_156J10_125_3370_n120), .ICI(
DP_OP_156J10_125_3370_n40), .S(DP_OP_156J10_125_3370_n39), .ICO(
DP_OP_156J10_125_3370_n37), .CO(DP_OP_156J10_125_3370_n38) );
CMPR42X1TS DP_OP_156J10_125_3370_U32 ( .A(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[8]), .B(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[15]), .C(
DP_OP_156J10_125_3370_n96), .D(DP_OP_156J10_125_3370_n119), .ICI(
DP_OP_156J10_125_3370_n37), .S(DP_OP_156J10_125_3370_n36), .ICO(
DP_OP_156J10_125_3370_n34), .CO(DP_OP_156J10_125_3370_n35) );
CMPR42X1TS DP_OP_156J10_125_3370_U31 ( .A(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[9]), .B(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[16]), .C(
DP_OP_156J10_125_3370_n95), .D(DP_OP_156J10_125_3370_n118), .ICI(
DP_OP_156J10_125_3370_n34), .S(DP_OP_156J10_125_3370_n33), .ICO(
DP_OP_156J10_125_3370_n31), .CO(DP_OP_156J10_125_3370_n32) );
CMPR42X1TS DP_OP_155J10_124_2038_U253 ( .A(DP_OP_155J10_124_2038_n370), .B(
DP_OP_155J10_124_2038_n360), .C(DP_OP_155J10_124_2038_n365), .D(
DP_OP_155J10_124_2038_n335), .ICI(DP_OP_155J10_124_2038_n332), .S(
DP_OP_155J10_124_2038_n330), .ICO(DP_OP_155J10_124_2038_n328), .CO(
DP_OP_155J10_124_2038_n329) );
CMPR42X1TS DP_OP_155J10_124_2038_U250 ( .A(DP_OP_155J10_124_2038_n364), .B(
DP_OP_155J10_124_2038_n331), .C(DP_OP_155J10_124_2038_n328), .D(
DP_OP_155J10_124_2038_n327), .ICI(DP_OP_155J10_124_2038_n325), .S(
DP_OP_155J10_124_2038_n323), .ICO(DP_OP_155J10_124_2038_n321), .CO(
DP_OP_155J10_124_2038_n322) );
CMPR42X1TS DP_OP_155J10_124_2038_U247 ( .A(DP_OP_155J10_124_2038_n326), .B(
DP_OP_155J10_124_2038_n324), .C(DP_OP_155J10_124_2038_n320), .D(
DP_OP_155J10_124_2038_n318), .ICI(DP_OP_155J10_124_2038_n321), .S(
DP_OP_155J10_124_2038_n316), .ICO(DP_OP_155J10_124_2038_n314), .CO(
DP_OP_155J10_124_2038_n315) );
CMPR42X1TS DP_OP_155J10_124_2038_U245 ( .A(DP_OP_155J10_124_2038_n352), .B(
DP_OP_155J10_124_2038_n319), .C(DP_OP_155J10_124_2038_n317), .D(
DP_OP_155J10_124_2038_n313), .ICI(DP_OP_155J10_124_2038_n314), .S(
DP_OP_155J10_124_2038_n311), .ICO(DP_OP_155J10_124_2038_n309), .CO(
DP_OP_155J10_124_2038_n310) );
CMPR42X1TS DP_OP_155J10_124_2038_U244 ( .A(DP_OP_155J10_124_2038_n351), .B(
DP_OP_155J10_124_2038_n341), .C(DP_OP_155J10_124_2038_n346), .D(
DP_OP_155J10_124_2038_n312), .ICI(DP_OP_155J10_124_2038_n309), .S(
DP_OP_155J10_124_2038_n308), .ICO(DP_OP_155J10_124_2038_n306), .CO(
DP_OP_155J10_124_2038_n307) );
CMPR42X1TS DP_OP_155J10_124_2038_U180 ( .A(DP_OP_155J10_124_2038_n279), .B(
DP_OP_155J10_124_2038_n269), .C(DP_OP_155J10_124_2038_n274), .D(
DP_OP_155J10_124_2038_n244), .ICI(DP_OP_155J10_124_2038_n241), .S(
DP_OP_155J10_124_2038_n239), .ICO(DP_OP_155J10_124_2038_n237), .CO(
DP_OP_155J10_124_2038_n238) );
CMPR42X1TS DP_OP_155J10_124_2038_U177 ( .A(DP_OP_155J10_124_2038_n273), .B(
DP_OP_155J10_124_2038_n240), .C(DP_OP_155J10_124_2038_n237), .D(
DP_OP_155J10_124_2038_n236), .ICI(DP_OP_155J10_124_2038_n234), .S(
DP_OP_155J10_124_2038_n232), .ICO(DP_OP_155J10_124_2038_n230), .CO(
DP_OP_155J10_124_2038_n231) );
CMPR42X1TS DP_OP_155J10_124_2038_U174 ( .A(DP_OP_155J10_124_2038_n235), .B(
DP_OP_155J10_124_2038_n233), .C(DP_OP_155J10_124_2038_n229), .D(
DP_OP_155J10_124_2038_n227), .ICI(DP_OP_155J10_124_2038_n230), .S(
DP_OP_155J10_124_2038_n225), .ICO(DP_OP_155J10_124_2038_n223), .CO(
DP_OP_155J10_124_2038_n224) );
CMPR42X1TS DP_OP_155J10_124_2038_U172 ( .A(DP_OP_155J10_124_2038_n261), .B(
DP_OP_155J10_124_2038_n228), .C(DP_OP_155J10_124_2038_n226), .D(
DP_OP_155J10_124_2038_n222), .ICI(DP_OP_155J10_124_2038_n223), .S(
DP_OP_155J10_124_2038_n220), .ICO(DP_OP_155J10_124_2038_n218), .CO(
DP_OP_155J10_124_2038_n219) );
CMPR42X1TS DP_OP_155J10_124_2038_U171 ( .A(DP_OP_155J10_124_2038_n260), .B(
DP_OP_155J10_124_2038_n250), .C(DP_OP_155J10_124_2038_n255), .D(
DP_OP_155J10_124_2038_n221), .ICI(DP_OP_155J10_124_2038_n218), .S(
DP_OP_155J10_124_2038_n217), .ICO(DP_OP_155J10_124_2038_n215), .CO(
DP_OP_155J10_124_2038_n216) );
CMPR42X1TS DP_OP_155J10_124_2038_U39 ( .A(DP_OP_155J10_124_2038_n202), .B(
DP_OP_155J10_124_2038_n87), .C(DP_OP_155J10_124_2038_n201), .D(
DP_OP_155J10_124_2038_n118), .ICI(DP_OP_155J10_124_2038_n125), .S(
DP_OP_155J10_124_2038_n75), .ICO(DP_OP_155J10_124_2038_n73), .CO(
DP_OP_155J10_124_2038_n74) );
CMPR42X1TS DP_OP_155J10_124_2038_U37 ( .A(DP_OP_155J10_124_2038_n86), .B(
DP_OP_155J10_124_2038_n124), .C(DP_OP_155J10_124_2038_n72), .D(
DP_OP_155J10_124_2038_n117), .ICI(DP_OP_155J10_124_2038_n91), .S(
DP_OP_155J10_124_2038_n70), .ICO(DP_OP_155J10_124_2038_n68), .CO(
DP_OP_155J10_124_2038_n69) );
CMPR42X1TS DP_OP_155J10_124_2038_U35 ( .A(DP_OP_155J10_124_2038_n116), .B(
DP_OP_155J10_124_2038_n109), .C(DP_OP_155J10_124_2038_n123), .D(
DP_OP_155J10_124_2038_n68), .ICI(DP_OP_155J10_124_2038_n67), .S(
DP_OP_155J10_124_2038_n65), .ICO(DP_OP_155J10_124_2038_n63), .CO(
DP_OP_155J10_124_2038_n64) );
CMPR42X1TS DP_OP_155J10_124_2038_U32 ( .A(DP_OP_155J10_124_2038_n122), .B(
DP_OP_155J10_124_2038_n62), .C(DP_OP_155J10_124_2038_n108), .D(
DP_OP_155J10_124_2038_n90), .ICI(DP_OP_155J10_124_2038_n60), .S(
DP_OP_155J10_124_2038_n58), .ICO(DP_OP_155J10_124_2038_n56), .CO(
DP_OP_155J10_124_2038_n57) );
CMPR42X1TS DP_OP_155J10_124_2038_U31 ( .A(DP_OP_155J10_124_2038_n114), .B(
DP_OP_155J10_124_2038_n61), .C(DP_OP_155J10_124_2038_n83), .D(
DP_OP_155J10_124_2038_n197), .ICI(DP_OP_155J10_124_2038_n100), .S(
DP_OP_155J10_124_2038_n55), .ICO(DP_OP_155J10_124_2038_n53), .CO(
DP_OP_155J10_124_2038_n54) );
CMPR42X1TS DP_OP_155J10_124_2038_U30 ( .A(DP_OP_155J10_124_2038_n121), .B(
DP_OP_155J10_124_2038_n107), .C(DP_OP_155J10_124_2038_n59), .D(
DP_OP_155J10_124_2038_n56), .ICI(DP_OP_155J10_124_2038_n55), .S(
DP_OP_155J10_124_2038_n52), .ICO(DP_OP_155J10_124_2038_n50), .CO(
DP_OP_155J10_124_2038_n51) );
CMPR42X1TS DP_OP_155J10_124_2038_U29 ( .A(DP_OP_155J10_124_2038_n120), .B(
DP_OP_155J10_124_2038_n113), .C(DP_OP_155J10_124_2038_n106), .D(
DP_OP_155J10_124_2038_n99), .ICI(DP_OP_155J10_124_2038_n82), .S(
DP_OP_155J10_124_2038_n49), .ICO(DP_OP_155J10_124_2038_n47), .CO(
DP_OP_155J10_124_2038_n48) );
CMPR42X1TS DP_OP_155J10_124_2038_U28 ( .A(DP_OP_155J10_124_2038_n53), .B(
DP_OP_155J10_124_2038_n196), .C(DP_OP_155J10_124_2038_n50), .D(
DP_OP_155J10_124_2038_n54), .ICI(DP_OP_155J10_124_2038_n49), .S(
DP_OP_155J10_124_2038_n46), .ICO(DP_OP_155J10_124_2038_n44), .CO(
DP_OP_155J10_124_2038_n45) );
CMPR42X1TS DP_OP_155J10_124_2038_U27 ( .A(DP_OP_155J10_124_2038_n119), .B(
DP_OP_155J10_124_2038_n112), .C(DP_OP_155J10_124_2038_n105), .D(
DP_OP_155J10_124_2038_n98), .ICI(DP_OP_155J10_124_2038_n47), .S(
DP_OP_155J10_124_2038_n43), .ICO(DP_OP_155J10_124_2038_n41), .CO(
DP_OP_155J10_124_2038_n42) );
CMPR42X1TS DP_OP_155J10_124_2038_U26 ( .A(
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[8]), .B(
DP_OP_155J10_124_2038_n81), .C(DP_OP_155J10_124_2038_n48), .D(
DP_OP_155J10_124_2038_n44), .ICI(DP_OP_155J10_124_2038_n43), .S(
DP_OP_155J10_124_2038_n40), .ICO(DP_OP_155J10_124_2038_n38), .CO(
DP_OP_155J10_124_2038_n39) );
CMPR42X1TS DP_OP_155J10_124_2038_U25 ( .A(DP_OP_155J10_124_2038_n111), .B(
DP_OP_155J10_124_2038_n104), .C(DP_OP_155J10_124_2038_n97), .D(
DP_OP_155J10_124_2038_n41), .ICI(DP_OP_155J10_124_2038_n195), .S(
DP_OP_155J10_124_2038_n37), .ICO(DP_OP_155J10_124_2038_n35), .CO(
DP_OP_155J10_124_2038_n36) );
CMPR42X1TS DP_OP_155J10_124_2038_U24 ( .A(DP_OP_155J10_124_2038_n42), .B(
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[9]), .C(
DP_OP_155J10_124_2038_n80), .D(DP_OP_155J10_124_2038_n38), .ICI(
DP_OP_155J10_124_2038_n37), .S(DP_OP_155J10_124_2038_n34), .ICO(
DP_OP_155J10_124_2038_n32), .CO(DP_OP_155J10_124_2038_n33) );
CMPR42X1TS DP_OP_155J10_124_2038_U23 ( .A(DP_OP_155J10_124_2038_n110), .B(
DP_OP_155J10_124_2038_n103), .C(DP_OP_155J10_124_2038_n96), .D(
DP_OP_155J10_124_2038_n35), .ICI(DP_OP_155J10_124_2038_n194), .S(
DP_OP_155J10_124_2038_n31), .ICO(DP_OP_155J10_124_2038_n29), .CO(
DP_OP_155J10_124_2038_n30) );
CMPR42X1TS DP_OP_155J10_124_2038_U22 ( .A(DP_OP_155J10_124_2038_n36), .B(
DP_OP_155J10_124_2038_n32), .C(DP_OP_155J10_124_2038_n193), .D(
DP_OP_155J10_124_2038_n79), .ICI(DP_OP_155J10_124_2038_n31), .S(
DP_OP_155J10_124_2038_n28), .ICO(DP_OP_155J10_124_2038_n26), .CO(
DP_OP_155J10_124_2038_n27) );
CMPR42X1TS DP_OP_155J10_124_2038_U20 ( .A(DP_OP_155J10_124_2038_n25), .B(
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[11]), .C(
DP_OP_155J10_124_2038_n30), .D(DP_OP_155J10_124_2038_n78), .ICI(
DP_OP_155J10_124_2038_n26), .S(DP_OP_155J10_124_2038_n23), .ICO(
DP_OP_155J10_124_2038_n21), .CO(DP_OP_155J10_124_2038_n22) );
CMPR42X1TS DP_OP_155J10_124_2038_U19 ( .A(DP_OP_155J10_124_2038_n94), .B(
DP_OP_155J10_124_2038_n101), .C(DP_OP_155J10_124_2038_n24), .D(
DP_OP_155J10_124_2038_n192), .ICI(DP_OP_155J10_124_2038_n21), .S(
DP_OP_155J10_124_2038_n20), .ICO(DP_OP_155J10_124_2038_n18), .CO(
DP_OP_155J10_124_2038_n19) );
CMPR42X1TS DP_OP_154J10_123_2038_U254 ( .A(DP_OP_154J10_123_2038_n369), .B(
DP_OP_154J10_123_2038_n359), .C(DP_OP_154J10_123_2038_n364), .D(
DP_OP_154J10_123_2038_n335), .ICI(DP_OP_154J10_123_2038_n332), .S(
DP_OP_154J10_123_2038_n330), .ICO(DP_OP_154J10_123_2038_n328), .CO(
DP_OP_154J10_123_2038_n329) );
CMPR42X1TS DP_OP_154J10_123_2038_U251 ( .A(DP_OP_154J10_123_2038_n358), .B(
DP_OP_154J10_123_2038_n331), .C(DP_OP_154J10_123_2038_n328), .D(
DP_OP_154J10_123_2038_n327), .ICI(DP_OP_154J10_123_2038_n325), .S(
DP_OP_154J10_123_2038_n323), .ICO(DP_OP_154J10_123_2038_n321), .CO(
DP_OP_154J10_123_2038_n322) );
CMPR42X1TS DP_OP_154J10_123_2038_U248 ( .A(DP_OP_154J10_123_2038_n326), .B(
DP_OP_154J10_123_2038_n320), .C(DP_OP_154J10_123_2038_n324), .D(
DP_OP_154J10_123_2038_n318), .ICI(DP_OP_154J10_123_2038_n321), .S(
DP_OP_154J10_123_2038_n316), .ICO(DP_OP_154J10_123_2038_n314), .CO(
DP_OP_154J10_123_2038_n315) );
CMPR42X1TS DP_OP_154J10_123_2038_U246 ( .A(DP_OP_154J10_123_2038_n351), .B(
DP_OP_154J10_123_2038_n319), .C(DP_OP_154J10_123_2038_n313), .D(
DP_OP_154J10_123_2038_n317), .ICI(DP_OP_154J10_123_2038_n314), .S(
DP_OP_154J10_123_2038_n311), .ICO(DP_OP_154J10_123_2038_n309), .CO(
DP_OP_154J10_123_2038_n310) );
CMPR42X1TS DP_OP_154J10_123_2038_U245 ( .A(Op_MX[21]), .B(Op_MY[21]), .C(
DP_OP_154J10_123_2038_n345), .D(DP_OP_154J10_123_2038_n312), .ICI(
DP_OP_154J10_123_2038_n309), .S(DP_OP_154J10_123_2038_n308), .ICO(
DP_OP_154J10_123_2038_n306), .CO(DP_OP_154J10_123_2038_n307) );
CMPR42X1TS DP_OP_154J10_123_2038_U180 ( .A(DP_OP_154J10_123_2038_n279), .B(
DP_OP_154J10_123_2038_n269), .C(DP_OP_154J10_123_2038_n274), .D(
DP_OP_154J10_123_2038_n244), .ICI(DP_OP_154J10_123_2038_n241), .S(
DP_OP_154J10_123_2038_n239), .ICO(DP_OP_154J10_123_2038_n237), .CO(
DP_OP_154J10_123_2038_n238) );
CMPR42X1TS DP_OP_154J10_123_2038_U177 ( .A(DP_OP_154J10_123_2038_n273), .B(
DP_OP_154J10_123_2038_n240), .C(DP_OP_154J10_123_2038_n237), .D(
DP_OP_154J10_123_2038_n236), .ICI(DP_OP_154J10_123_2038_n234), .S(
DP_OP_154J10_123_2038_n232), .ICO(DP_OP_154J10_123_2038_n230), .CO(
DP_OP_154J10_123_2038_n231) );
CMPR42X1TS DP_OP_154J10_123_2038_U174 ( .A(DP_OP_154J10_123_2038_n235), .B(
DP_OP_154J10_123_2038_n233), .C(DP_OP_154J10_123_2038_n229), .D(
DP_OP_154J10_123_2038_n227), .ICI(DP_OP_154J10_123_2038_n230), .S(
DP_OP_154J10_123_2038_n225), .ICO(DP_OP_154J10_123_2038_n223), .CO(
DP_OP_154J10_123_2038_n224) );
CMPR42X1TS DP_OP_154J10_123_2038_U172 ( .A(DP_OP_154J10_123_2038_n261), .B(
DP_OP_154J10_123_2038_n228), .C(DP_OP_154J10_123_2038_n226), .D(
DP_OP_154J10_123_2038_n222), .ICI(DP_OP_154J10_123_2038_n223), .S(
DP_OP_154J10_123_2038_n220), .ICO(DP_OP_154J10_123_2038_n218), .CO(
DP_OP_154J10_123_2038_n219) );
CMPR42X1TS DP_OP_154J10_123_2038_U171 ( .A(DP_OP_154J10_123_2038_n260), .B(
DP_OP_154J10_123_2038_n250), .C(DP_OP_154J10_123_2038_n255), .D(
DP_OP_154J10_123_2038_n221), .ICI(DP_OP_154J10_123_2038_n218), .S(
DP_OP_154J10_123_2038_n217), .ICO(DP_OP_154J10_123_2038_n215), .CO(
DP_OP_154J10_123_2038_n216) );
CMPR42X1TS DP_OP_154J10_123_2038_U39 ( .A(DP_OP_154J10_123_2038_n202), .B(
DP_OP_154J10_123_2038_n87), .C(DP_OP_154J10_123_2038_n201), .D(
DP_OP_154J10_123_2038_n118), .ICI(DP_OP_154J10_123_2038_n125), .S(
DP_OP_154J10_123_2038_n75), .ICO(DP_OP_154J10_123_2038_n73), .CO(
DP_OP_154J10_123_2038_n74) );
CMPR42X1TS DP_OP_154J10_123_2038_U37 ( .A(DP_OP_154J10_123_2038_n86), .B(
DP_OP_154J10_123_2038_n124), .C(DP_OP_154J10_123_2038_n72), .D(
DP_OP_154J10_123_2038_n117), .ICI(DP_OP_154J10_123_2038_n91), .S(
DP_OP_154J10_123_2038_n70), .ICO(DP_OP_154J10_123_2038_n68), .CO(
DP_OP_154J10_123_2038_n69) );
CMPR42X1TS DP_OP_154J10_123_2038_U35 ( .A(DP_OP_154J10_123_2038_n116), .B(
DP_OP_154J10_123_2038_n109), .C(DP_OP_154J10_123_2038_n123), .D(
DP_OP_154J10_123_2038_n68), .ICI(DP_OP_154J10_123_2038_n67), .S(
DP_OP_154J10_123_2038_n65), .ICO(DP_OP_154J10_123_2038_n63), .CO(
DP_OP_154J10_123_2038_n64) );
CMPR42X1TS DP_OP_154J10_123_2038_U32 ( .A(DP_OP_154J10_123_2038_n62), .B(
DP_OP_154J10_123_2038_n122), .C(DP_OP_154J10_123_2038_n60), .D(
DP_OP_154J10_123_2038_n64), .ICI(DP_OP_154J10_123_2038_n108), .S(
DP_OP_154J10_123_2038_n58), .ICO(DP_OP_154J10_123_2038_n56), .CO(
DP_OP_154J10_123_2038_n57) );
CMPR42X1TS DP_OP_154J10_123_2038_U31 ( .A(DP_OP_154J10_123_2038_n114), .B(
DP_OP_154J10_123_2038_n61), .C(DP_OP_154J10_123_2038_n83), .D(
DP_OP_154J10_123_2038_n197), .ICI(DP_OP_154J10_123_2038_n100), .S(
DP_OP_154J10_123_2038_n55), .ICO(DP_OP_154J10_123_2038_n53), .CO(
DP_OP_154J10_123_2038_n54) );
CMPR42X1TS DP_OP_154J10_123_2038_U30 ( .A(DP_OP_154J10_123_2038_n121), .B(
DP_OP_154J10_123_2038_n59), .C(DP_OP_154J10_123_2038_n107), .D(
DP_OP_154J10_123_2038_n56), .ICI(DP_OP_154J10_123_2038_n55), .S(
DP_OP_154J10_123_2038_n52), .ICO(DP_OP_154J10_123_2038_n50), .CO(
DP_OP_154J10_123_2038_n51) );
CMPR42X1TS DP_OP_154J10_123_2038_U29 ( .A(DP_OP_154J10_123_2038_n120), .B(
DP_OP_154J10_123_2038_n113), .C(DP_OP_154J10_123_2038_n53), .D(
DP_OP_154J10_123_2038_n196), .ICI(DP_OP_154J10_123_2038_n82), .S(
DP_OP_154J10_123_2038_n49), .ICO(DP_OP_154J10_123_2038_n47), .CO(
DP_OP_154J10_123_2038_n48) );
CMPR42X1TS DP_OP_154J10_123_2038_U28 ( .A(DP_OP_154J10_123_2038_n99), .B(
DP_OP_154J10_123_2038_n106), .C(DP_OP_154J10_123_2038_n54), .D(
DP_OP_154J10_123_2038_n50), .ICI(DP_OP_154J10_123_2038_n49), .S(
DP_OP_154J10_123_2038_n46), .ICO(DP_OP_154J10_123_2038_n44), .CO(
DP_OP_154J10_123_2038_n45) );
CMPR42X1TS DP_OP_154J10_123_2038_U27 ( .A(DP_OP_154J10_123_2038_n119), .B(
DP_OP_154J10_123_2038_n112), .C(DP_OP_154J10_123_2038_n98), .D(
DP_OP_154J10_123_2038_n105), .ICI(
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[8]), .S(
DP_OP_154J10_123_2038_n43), .ICO(DP_OP_154J10_123_2038_n41), .CO(
DP_OP_154J10_123_2038_n42) );
CMPR42X1TS DP_OP_154J10_123_2038_U26 ( .A(DP_OP_154J10_123_2038_n47), .B(
DP_OP_154J10_123_2038_n81), .C(DP_OP_154J10_123_2038_n44), .D(
DP_OP_154J10_123_2038_n48), .ICI(DP_OP_154J10_123_2038_n43), .S(
DP_OP_154J10_123_2038_n40), .ICO(DP_OP_154J10_123_2038_n38), .CO(
DP_OP_154J10_123_2038_n39) );
CMPR42X1TS DP_OP_154J10_123_2038_U25 ( .A(DP_OP_154J10_123_2038_n111), .B(
DP_OP_154J10_123_2038_n97), .C(DP_OP_154J10_123_2038_n104), .D(
DP_OP_154J10_123_2038_n195), .ICI(DP_OP_154J10_123_2038_n41), .S(
DP_OP_154J10_123_2038_n37), .ICO(DP_OP_154J10_123_2038_n35), .CO(
DP_OP_154J10_123_2038_n36) );
CMPR42X1TS DP_OP_154J10_123_2038_U24 ( .A(
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[9]), .B(
DP_OP_154J10_123_2038_n80), .C(DP_OP_154J10_123_2038_n42), .D(
DP_OP_154J10_123_2038_n38), .ICI(DP_OP_154J10_123_2038_n37), .S(
DP_OP_154J10_123_2038_n34), .ICO(DP_OP_154J10_123_2038_n32), .CO(
DP_OP_154J10_123_2038_n33) );
CMPR42X1TS DP_OP_154J10_123_2038_U23 ( .A(DP_OP_154J10_123_2038_n110), .B(
DP_OP_154J10_123_2038_n96), .C(DP_OP_154J10_123_2038_n103), .D(
DP_OP_154J10_123_2038_n35), .ICI(DP_OP_154J10_123_2038_n194), .S(
DP_OP_154J10_123_2038_n31), .ICO(DP_OP_154J10_123_2038_n29), .CO(
DP_OP_154J10_123_2038_n30) );
CMPR42X1TS DP_OP_154J10_123_2038_U22 ( .A(DP_OP_154J10_123_2038_n36), .B(
DP_OP_154J10_123_2038_n79), .C(DP_OP_154J10_123_2038_n32), .D(
DP_OP_154J10_123_2038_n31), .ICI(DP_OP_154J10_123_2038_n193), .S(
DP_OP_154J10_123_2038_n28), .ICO(DP_OP_154J10_123_2038_n26), .CO(
DP_OP_154J10_123_2038_n27) );
CMPR42X1TS DP_OP_154J10_123_2038_U20 ( .A(
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[11]), .B(
DP_OP_154J10_123_2038_n25), .C(DP_OP_154J10_123_2038_n78), .D(
DP_OP_154J10_123_2038_n30), .ICI(DP_OP_154J10_123_2038_n26), .S(
DP_OP_154J10_123_2038_n23), .ICO(DP_OP_154J10_123_2038_n21), .CO(
DP_OP_154J10_123_2038_n22) );
CMPR42X1TS DP_OP_154J10_123_2038_U19 ( .A(DP_OP_154J10_123_2038_n94), .B(
DP_OP_154J10_123_2038_n101), .C(DP_OP_154J10_123_2038_n24), .D(
DP_OP_154J10_123_2038_n192), .ICI(DP_OP_154J10_123_2038_n21), .S(
DP_OP_154J10_123_2038_n20), .ICO(DP_OP_154J10_123_2038_n18), .CO(
DP_OP_154J10_123_2038_n19) );
CMPR42X1TS DP_OP_153J10_122_5442_U283 ( .A(DP_OP_153J10_122_5442_n394), .B(
DP_OP_153J10_122_5442_n414), .C(DP_OP_153J10_122_5442_n407), .D(
DP_OP_153J10_122_5442_n400), .ICI(DP_OP_153J10_122_5442_n380), .S(
DP_OP_153J10_122_5442_n377), .ICO(DP_OP_153J10_122_5442_n375), .CO(
DP_OP_153J10_122_5442_n376) );
CMPR42X1TS DP_OP_153J10_122_5442_U282 ( .A(DP_OP_153J10_122_5442_n413), .B(
DP_OP_153J10_122_5442_n393), .C(DP_OP_153J10_122_5442_n399), .D(
DP_OP_153J10_122_5442_n406), .ICI(DP_OP_153J10_122_5442_n375), .S(
DP_OP_153J10_122_5442_n374), .ICO(DP_OP_153J10_122_5442_n372), .CO(
DP_OP_153J10_122_5442_n373) );
CMPR42X1TS DP_OP_153J10_122_5442_U280 ( .A(DP_OP_153J10_122_5442_n405), .B(
DP_OP_153J10_122_5442_n398), .C(DP_OP_153J10_122_5442_n412), .D(
DP_OP_153J10_122_5442_n371), .ICI(DP_OP_153J10_122_5442_n372), .S(
DP_OP_153J10_122_5442_n369), .ICO(DP_OP_153J10_122_5442_n367), .CO(
DP_OP_153J10_122_5442_n368) );
CMPR42X1TS DP_OP_153J10_122_5442_U278 ( .A(DP_OP_153J10_122_5442_n404), .B(
DP_OP_153J10_122_5442_n370), .C(DP_OP_153J10_122_5442_n397), .D(
DP_OP_153J10_122_5442_n366), .ICI(DP_OP_153J10_122_5442_n367), .S(
DP_OP_153J10_122_5442_n364), .ICO(DP_OP_153J10_122_5442_n362), .CO(
DP_OP_153J10_122_5442_n363) );
CMPR42X1TS DP_OP_153J10_122_5442_U277 ( .A(DP_OP_153J10_122_5442_n365), .B(
DP_OP_153J10_122_5442_n396), .C(DP_OP_153J10_122_5442_n392), .D(
DP_OP_153J10_122_5442_n403), .ICI(DP_OP_153J10_122_5442_n362), .S(
DP_OP_153J10_122_5442_n361), .ICO(DP_OP_153J10_122_5442_n359), .CO(
DP_OP_153J10_122_5442_n360) );
CMPR42X1TS DP_OP_153J10_122_5442_U192 ( .A(DP_OP_153J10_122_5442_n306), .B(
DP_OP_153J10_122_5442_n296), .C(DP_OP_153J10_122_5442_n274), .D(
DP_OP_153J10_122_5442_n273), .ICI(DP_OP_153J10_122_5442_n311), .S(
DP_OP_153J10_122_5442_n271), .ICO(DP_OP_153J10_122_5442_n269), .CO(
DP_OP_153J10_122_5442_n270) );
CMPR42X1TS DP_OP_153J10_122_5442_U189 ( .A(DP_OP_153J10_122_5442_n268), .B(
DP_OP_153J10_122_5442_n305), .C(DP_OP_153J10_122_5442_n290), .D(
DP_OP_153J10_122_5442_n266), .ICI(DP_OP_153J10_122_5442_n269), .S(
DP_OP_153J10_122_5442_n264), .ICO(DP_OP_153J10_122_5442_n262), .CO(
DP_OP_153J10_122_5442_n263) );
CMPR42X1TS DP_OP_153J10_122_5442_U186 ( .A(DP_OP_153J10_122_5442_n289), .B(
DP_OP_153J10_122_5442_n265), .C(DP_OP_153J10_122_5442_n261), .D(
DP_OP_153J10_122_5442_n262), .ICI(DP_OP_153J10_122_5442_n259), .S(
DP_OP_153J10_122_5442_n257), .ICO(DP_OP_153J10_122_5442_n255), .CO(
DP_OP_153J10_122_5442_n256) );
CMPR42X1TS DP_OP_153J10_122_5442_U184 ( .A(DP_OP_153J10_122_5442_n293), .B(
DP_OP_153J10_122_5442_n288), .C(DP_OP_153J10_122_5442_n254), .D(
DP_OP_153J10_122_5442_n258), .ICI(DP_OP_153J10_122_5442_n255), .S(
DP_OP_153J10_122_5442_n252), .ICO(DP_OP_153J10_122_5442_n250), .CO(
DP_OP_153J10_122_5442_n251) );
CMPR42X1TS DP_OP_153J10_122_5442_U183 ( .A(DP_OP_153J10_122_5442_n292), .B(
DP_OP_153J10_122_5442_n282), .C(DP_OP_153J10_122_5442_n287), .D(
DP_OP_153J10_122_5442_n253), .ICI(DP_OP_153J10_122_5442_n250), .S(
DP_OP_153J10_122_5442_n249), .ICO(DP_OP_153J10_122_5442_n247), .CO(
DP_OP_153J10_122_5442_n248) );
CMPR42X1TS DP_OP_153J10_122_5442_U63 ( .A(DP_OP_153J10_122_5442_n234), .B(
DP_OP_153J10_122_5442_n205), .C(DP_OP_153J10_122_5442_n191), .D(
DP_OP_153J10_122_5442_n128), .ICI(DP_OP_153J10_122_5442_n127), .S(
DP_OP_153J10_122_5442_n125), .ICO(DP_OP_153J10_122_5442_n123), .CO(
DP_OP_153J10_122_5442_n124) );
CMPR42X1TS DP_OP_153J10_122_5442_U60 ( .A(DP_OP_153J10_122_5442_n204), .B(
DP_OP_153J10_122_5442_n183), .C(DP_OP_153J10_122_5442_n122), .D(
DP_OP_153J10_122_5442_n120), .ICI(DP_OP_153J10_122_5442_n124), .S(
DP_OP_153J10_122_5442_n118), .ICO(DP_OP_153J10_122_5442_n116), .CO(
DP_OP_153J10_122_5442_n117) );
CMPR42X1TS DP_OP_153J10_122_5442_U58 ( .A(DP_OP_153J10_122_5442_n121), .B(
DP_OP_153J10_122_5442_n182), .C(DP_OP_153J10_122_5442_n196), .D(
DP_OP_153J10_122_5442_n115), .ICI(DP_OP_153J10_122_5442_n116), .S(
DP_OP_153J10_122_5442_n113), .ICO(DP_OP_153J10_122_5442_n111), .CO(
DP_OP_153J10_122_5442_n112) );
CMPR42X1TS DP_OP_153J10_122_5442_U57 ( .A(DP_OP_153J10_122_5442_n119), .B(
DP_OP_153J10_122_5442_n175), .C(DP_OP_153J10_122_5442_n203), .D(
DP_OP_153J10_122_5442_n113), .ICI(DP_OP_153J10_122_5442_n117), .S(
DP_OP_153J10_122_5442_n110), .ICO(DP_OP_153J10_122_5442_n108), .CO(
DP_OP_153J10_122_5442_n109) );
CMPR42X1TS DP_OP_153J10_122_5442_U54 ( .A(DP_OP_153J10_122_5442_n107), .B(
DP_OP_153J10_122_5442_n195), .C(DP_OP_153J10_122_5442_n174), .D(
DP_OP_153J10_122_5442_n105), .ICI(DP_OP_153J10_122_5442_n202), .S(
DP_OP_153J10_122_5442_n103), .ICO(DP_OP_153J10_122_5442_n101), .CO(
DP_OP_153J10_122_5442_n102) );
CMPR42X1TS DP_OP_153J10_122_5442_U53 ( .A(DP_OP_153J10_122_5442_n112), .B(
DP_OP_153J10_122_5442_n108), .C(DP_OP_153J10_122_5442_n167), .D(
DP_OP_153J10_122_5442_n103), .ICI(DP_OP_153J10_122_5442_n109), .S(
DP_OP_153J10_122_5442_n100), .ICO(DP_OP_153J10_122_5442_n98), .CO(
DP_OP_153J10_122_5442_n99) );
CMPR42X1TS DP_OP_153J10_122_5442_U51 ( .A(DP_OP_153J10_122_5442_n106), .B(
DP_OP_153J10_122_5442_n97), .C(DP_OP_153J10_122_5442_n173), .D(
DP_OP_153J10_122_5442_n187), .ICI(DP_OP_153J10_122_5442_n104), .S(
DP_OP_153J10_122_5442_n95), .ICO(DP_OP_153J10_122_5442_n93), .CO(
DP_OP_153J10_122_5442_n94) );
CMPR42X1TS DP_OP_153J10_122_5442_U50 ( .A(DP_OP_153J10_122_5442_n101), .B(
DP_OP_153J10_122_5442_n166), .C(DP_OP_153J10_122_5442_n194), .D(
DP_OP_153J10_122_5442_n98), .ICI(DP_OP_153J10_122_5442_n95), .S(
DP_OP_153J10_122_5442_n92), .ICO(DP_OP_153J10_122_5442_n90), .CO(
DP_OP_153J10_122_5442_n91) );
CMPR42X1TS DP_OP_153J10_122_5442_U49 ( .A(DP_OP_153J10_122_5442_n201), .B(
DP_OP_153J10_122_5442_n159), .C(DP_OP_153J10_122_5442_n102), .D(
DP_OP_153J10_122_5442_n229), .ICI(DP_OP_153J10_122_5442_n92), .S(
DP_OP_153J10_122_5442_n89), .ICO(DP_OP_153J10_122_5442_n87), .CO(
DP_OP_153J10_122_5442_n88) );
CMPR42X1TS DP_OP_153J10_122_5442_U46 ( .A(DP_OP_153J10_122_5442_n93), .B(
DP_OP_153J10_122_5442_n165), .C(DP_OP_153J10_122_5442_n186), .D(
DP_OP_153J10_122_5442_n151), .ICI(DP_OP_153J10_122_5442_n158), .S(
DP_OP_153J10_122_5442_n82), .ICO(DP_OP_153J10_122_5442_n80), .CO(
DP_OP_153J10_122_5442_n81) );
CMPR42X1TS DP_OP_153J10_122_5442_U45 ( .A(DP_OP_153J10_122_5442_n200), .B(
DP_OP_153J10_122_5442_n90), .C(DP_OP_153J10_122_5442_n94), .D(
DP_OP_153J10_122_5442_n193), .ICI(DP_OP_153J10_122_5442_n87), .S(
DP_OP_153J10_122_5442_n79), .ICO(DP_OP_153J10_122_5442_n77), .CO(
DP_OP_153J10_122_5442_n78) );
CMPR42X1TS DP_OP_153J10_122_5442_U44 ( .A(DP_OP_153J10_122_5442_n84), .B(
DP_OP_153J10_122_5442_n91), .C(DP_OP_153J10_122_5442_n82), .D(
DP_OP_153J10_122_5442_n79), .ICI(DP_OP_153J10_122_5442_n228), .S(
DP_OP_153J10_122_5442_n76), .ICO(DP_OP_153J10_122_5442_n74), .CO(
DP_OP_153J10_122_5442_n75) );
CMPR42X1TS DP_OP_153J10_122_5442_U41 ( .A(DP_OP_153J10_122_5442_n73), .B(
DP_OP_153J10_122_5442_n83), .C(DP_OP_153J10_122_5442_n192), .D(
DP_OP_153J10_122_5442_n150), .ICI(DP_OP_153J10_122_5442_n71), .S(
DP_OP_153J10_122_5442_n69), .ICO(DP_OP_153J10_122_5442_n67), .CO(
DP_OP_153J10_122_5442_n68) );
CMPR42X1TS DP_OP_153J10_122_5442_U40 ( .A(DP_OP_153J10_122_5442_n80), .B(
DP_OP_153J10_122_5442_n185), .C(DP_OP_153J10_122_5442_n157), .D(
DP_OP_153J10_122_5442_n77), .ICI(DP_OP_153J10_122_5442_n81), .S(
DP_OP_153J10_122_5442_n66), .ICO(DP_OP_153J10_122_5442_n64), .CO(
DP_OP_153J10_122_5442_n65) );
CMPR42X1TS DP_OP_153J10_122_5442_U39 ( .A(DP_OP_153J10_122_5442_n78), .B(
DP_OP_153J10_122_5442_n69), .C(DP_OP_153J10_122_5442_n74), .D(
DP_OP_153J10_122_5442_n66), .ICI(DP_OP_153J10_122_5442_n227), .S(
DP_OP_153J10_122_5442_n63), .ICO(DP_OP_153J10_122_5442_n61), .CO(
DP_OP_153J10_122_5442_n62) );
CMPR42X1TS DP_OP_153J10_122_5442_U37 ( .A(DP_OP_153J10_122_5442_n72), .B(
DP_OP_153J10_122_5442_n149), .C(DP_OP_153J10_122_5442_n184), .D(
DP_OP_153J10_122_5442_n156), .ICI(DP_OP_153J10_122_5442_n60), .S(
DP_OP_153J10_122_5442_n58), .ICO(DP_OP_153J10_122_5442_n56), .CO(
DP_OP_153J10_122_5442_n57) );
CMPR42X1TS DP_OP_153J10_122_5442_U36 ( .A(DP_OP_153J10_122_5442_n177), .B(
DP_OP_153J10_122_5442_n70), .C(DP_OP_153J10_122_5442_n67), .D(
DP_OP_153J10_122_5442_n64), .ICI(DP_OP_153J10_122_5442_n68), .S(
DP_OP_153J10_122_5442_n55), .ICO(DP_OP_153J10_122_5442_n53), .CO(
DP_OP_153J10_122_5442_n54) );
CMPR42X1TS DP_OP_153J10_122_5442_U35 ( .A(DP_OP_153J10_122_5442_n58), .B(
DP_OP_153J10_122_5442_n65), .C(DP_OP_153J10_122_5442_n55), .D(
DP_OP_153J10_122_5442_n61), .ICI(DP_OP_153J10_122_5442_n62), .S(
DP_OP_153J10_122_5442_n52), .ICO(DP_OP_153J10_122_5442_n50), .CO(
DP_OP_153J10_122_5442_n51) );
CMPR42X1TS DP_OP_153J10_122_5442_U34 ( .A(DP_OP_153J10_122_5442_n133), .B(
DP_OP_153J10_122_5442_n162), .C(DP_OP_153J10_122_5442_n148), .D(
DP_OP_153J10_122_5442_n176), .ICI(DP_OP_153J10_122_5442_n155), .S(
DP_OP_153J10_122_5442_n49), .ICO(DP_OP_153J10_122_5442_n47), .CO(
DP_OP_153J10_122_5442_n48) );
CMPR42X1TS DP_OP_153J10_122_5442_U33 ( .A(DP_OP_153J10_122_5442_n169), .B(
DP_OP_153J10_122_5442_n59), .C(DP_OP_153J10_122_5442_n56), .D(
DP_OP_153J10_122_5442_n53), .ICI(DP_OP_153J10_122_5442_n57), .S(
DP_OP_153J10_122_5442_n46), .ICO(DP_OP_153J10_122_5442_n44), .CO(
DP_OP_153J10_122_5442_n45) );
CMPR42X1TS DP_OP_153J10_122_5442_U32 ( .A(DP_OP_153J10_122_5442_n49), .B(
DP_OP_153J10_122_5442_n54), .C(DP_OP_153J10_122_5442_n46), .D(
DP_OP_153J10_122_5442_n50), .ICI(DP_OP_153J10_122_5442_n51), .S(
DP_OP_153J10_122_5442_n43), .ICO(DP_OP_153J10_122_5442_n41), .CO(
DP_OP_153J10_122_5442_n42) );
CMPR42X1TS DP_OP_153J10_122_5442_U30 ( .A(DP_OP_153J10_122_5442_n161), .B(
DP_OP_153J10_122_5442_n154), .C(DP_OP_153J10_122_5442_n47), .D(
DP_OP_153J10_122_5442_n40), .ICI(DP_OP_153J10_122_5442_n44), .S(
DP_OP_153J10_122_5442_n38), .ICO(DP_OP_153J10_122_5442_n36), .CO(
DP_OP_153J10_122_5442_n37) );
CMPR42X1TS DP_OP_153J10_122_5442_U29 ( .A(DP_OP_153J10_122_5442_n48), .B(
DP_OP_153J10_122_5442_n38), .C(DP_OP_153J10_122_5442_n45), .D(
DP_OP_153J10_122_5442_n41), .ICI(DP_OP_153J10_122_5442_n224), .S(
DP_OP_153J10_122_5442_n35), .ICO(DP_OP_153J10_122_5442_n33), .CO(
DP_OP_153J10_122_5442_n34) );
CMPR42X1TS DP_OP_153J10_122_5442_U25 ( .A(DP_OP_153J10_122_5442_n36), .B(
DP_OP_153J10_122_5442_n32), .C(DP_OP_153J10_122_5442_n30), .D(
DP_OP_153J10_122_5442_n37), .ICI(DP_OP_153J10_122_5442_n33), .S(
DP_OP_153J10_122_5442_n28), .ICO(DP_OP_153J10_122_5442_n26), .CO(
DP_OP_153J10_122_5442_n27) );
CMPR42X1TS DP_OP_153J10_122_5442_U22 ( .A(DP_OP_153J10_122_5442_n145), .B(
DP_OP_153J10_122_5442_n31), .C(DP_OP_153J10_122_5442_n29), .D(
DP_OP_153J10_122_5442_n25), .ICI(DP_OP_153J10_122_5442_n26), .S(
DP_OP_153J10_122_5442_n23), .ICO(DP_OP_153J10_122_5442_n21), .CO(
DP_OP_153J10_122_5442_n22) );
DFFRXLTS Barrel_Shifter_module_Output_Reg_Q_reg_8_ ( .D(n210), .CK(clk),
.RN(n393), .Q(Sgf_normalized_result[8]), .QN(n1669) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_11_ ( .D(n355), .CK(clk), .RN(
n1712), .Q(Op_MX[11]) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_21_ ( .D(n333), .CK(clk), .RN(
n1715), .Q(Op_MY[21]) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_0_ ( .D(n344), .CK(clk), .RN(
n1710), .Q(Op_MX[0]) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_22_ ( .D(n334), .CK(clk), .RN(
n1714), .Q(Op_MY[22]) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_2_ ( .D(n346), .CK(clk), .RN(
n393), .Q(Op_MX[2]) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_9_ ( .D(n353), .CK(clk), .RN(
n1716), .Q(Op_MX[9]) );
DFFRX2TS FS_Module_state_reg_reg_3_ ( .D(n380), .CK(clk), .RN(n1719), .Q(
FS_Module_state_reg[3]) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_17_ ( .D(n361), .CK(clk), .RN(
n1716), .Q(Op_MX[17]), .QN(n419) );
DFFRX2TS Barrel_Shifter_module_Output_Reg_Q_reg_0_ ( .D(n202), .CK(clk),
.RN(n1713), .Q(Sgf_normalized_result[0]) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_12_ ( .D(n324), .CK(clk), .RN(
n393), .Q(Op_MY[12]), .QN(n405) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_17_ ( .D(n329), .CK(clk), .RN(
n1715), .Q(Op_MY[17]), .QN(n402) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_3_ ( .D(n205), .CK(clk),
.RN(n1711), .Q(Sgf_normalized_result[3]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_5_ ( .D(n207), .CK(clk),
.RN(n1713), .Q(Sgf_normalized_result[5]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_7_ ( .D(n209), .CK(clk),
.RN(n1718), .Q(Sgf_normalized_result[7]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_9_ ( .D(n211), .CK(clk),
.RN(n1710), .Q(Sgf_normalized_result[9]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_11_ ( .D(n213), .CK(clk),
.RN(n393), .Q(Sgf_normalized_result[11]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_13_ ( .D(n215), .CK(clk),
.RN(n1713), .Q(Sgf_normalized_result[13]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_15_ ( .D(n217), .CK(clk),
.RN(n1710), .Q(Sgf_normalized_result[15]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_17_ ( .D(n219), .CK(clk),
.RN(n1713), .Q(Sgf_normalized_result[17]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_19_ ( .D(n221), .CK(clk),
.RN(n1714), .Q(Sgf_normalized_result[19]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_21_ ( .D(n223), .CK(clk),
.RN(n1710), .Q(Sgf_normalized_result[21]) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_11_ ( .D(n323), .CK(clk), .RN(
n1716), .Q(Op_MY[11]) );
DFFRX1TS Sgf_operation_EVEN1_finalreg_Q_reg_47_ ( .D(n237), .CK(clk), .RN(
n167), .Q(P_Sgf[47]) );
DFFRX1TS Exp_module_exp_result_m_Q_reg_7_ ( .D(n227), .CK(clk), .RN(n1715),
.Q(exp_oper_result[7]) );
DFFRX1TS Exp_module_exp_result_m_Q_reg_6_ ( .D(n228), .CK(clk), .RN(n393),
.Q(exp_oper_result[6]) );
DFFRX1TS Exp_module_exp_result_m_Q_reg_5_ ( .D(n229), .CK(clk), .RN(n1716),
.Q(exp_oper_result[5]) );
DFFRX1TS Exp_module_exp_result_m_Q_reg_4_ ( .D(n230), .CK(clk), .RN(n1714),
.Q(exp_oper_result[4]) );
DFFRX1TS Exp_module_exp_result_m_Q_reg_3_ ( .D(n231), .CK(clk), .RN(n1715),
.Q(exp_oper_result[3]) );
DFFRX1TS Exp_module_exp_result_m_Q_reg_2_ ( .D(n232), .CK(clk), .RN(n1712),
.Q(exp_oper_result[2]) );
DFFRX1TS Exp_module_exp_result_m_Q_reg_1_ ( .D(n233), .CK(clk), .RN(n1712),
.Q(exp_oper_result[1]) );
DFFRX1TS Exp_module_exp_result_m_Q_reg_0_ ( .D(n234), .CK(clk), .RN(n1708),
.Q(exp_oper_result[0]) );
DFFRX1TS Adder_M_Add_overflow_Result_Q_reg_0_ ( .D(n285), .CK(clk), .RN(
n1718), .Q(FSM_add_overflow_flag) );
DFFRX1TS Exp_module_exp_result_m_Q_reg_8_ ( .D(n226), .CK(clk), .RN(n1712),
.Q(exp_oper_result[8]) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_2_ ( .D(n314), .CK(clk), .RN(
n1718), .Q(Op_MY[2]) );
DFFRX1TS Operands_load_reg_XMRegister_Q_reg_23_ ( .D(n367), .CK(clk), .RN(
n1717), .Q(Op_MX[23]) );
DFFRX1TS Operands_load_reg_XMRegister_Q_reg_26_ ( .D(n370), .CK(clk), .RN(
n393), .Q(Op_MX[26]) );
DFFRX1TS Operands_load_reg_XMRegister_Q_reg_27_ ( .D(n371), .CK(clk), .RN(
n1716), .Q(Op_MX[27]) );
DFFRX1TS Operands_load_reg_XMRegister_Q_reg_25_ ( .D(n369), .CK(clk), .RN(
n1711), .Q(Op_MX[25]) );
DFFRX1TS Sgf_operation_EVEN1_finalreg_Q_reg_9_ ( .D(n247), .CK(clk), .RN(
n1721), .Q(P_Sgf[9]) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_18_ ( .D(n330), .CK(clk), .RN(
n1716), .Q(Op_MY[18]) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_21_ ( .D(n365), .CK(clk), .RN(
n1715), .Q(Op_MX[21]) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_20_ ( .D(n364), .CK(clk), .RN(
n1710), .Q(Op_MX[20]) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_19_ ( .D(n363), .CK(clk), .RN(
n1718), .Q(Op_MX[19]) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_22_ ( .D(n366), .CK(clk), .RN(
n1708), .Q(Op_MX[22]) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_0_ ( .D(n312), .CK(clk), .RN(
n1717), .Q(Op_MY[0]) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_20_ ( .D(n332), .CK(clk), .RN(
n1712), .Q(Op_MY[20]) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_18_ ( .D(n362), .CK(clk), .RN(
n1714), .Q(Op_MX[18]) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_10_ ( .D(n354), .CK(clk), .RN(
n1717), .Q(Op_MX[10]) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_19_ ( .D(n331), .CK(clk), .RN(
n1708), .Q(Op_MY[19]) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_7_ ( .D(n351), .CK(clk), .RN(
n1713), .Q(Op_MX[7]) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_3_ ( .D(n347), .CK(clk), .RN(
n1711), .Q(Op_MX[3]) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_5_ ( .D(n349), .CK(clk), .RN(
n393), .Q(Op_MX[5]) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_7_ ( .D(n319), .CK(clk), .RN(
n1711), .Q(Op_MY[7]) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_13_ ( .D(n357), .CK(clk), .RN(
n1718), .Q(Op_MX[13]), .QN(n420) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_13_ ( .D(n325), .CK(clk), .RN(
n1708), .Q(Op_MY[13]), .QN(n403) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_15_ ( .D(n359), .CK(clk), .RN(
n1716), .Q(Op_MX[15]), .QN(n422) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_16_ ( .D(n360), .CK(clk), .RN(
n393), .Q(Op_MX[16]), .QN(n421) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_16_ ( .D(n328), .CK(clk), .RN(
n1717), .Q(Op_MY[16]), .QN(n404) );
DFFRX1TS Operands_load_reg_YMRegister_Q_reg_23_ ( .D(n335), .CK(clk), .RN(
n1718), .Q(Op_MY[23]) );
DFFRX1TS Operands_load_reg_XMRegister_Q_reg_28_ ( .D(n372), .CK(clk), .RN(
n1708), .Q(Op_MX[28]) );
DFFRX1TS Operands_load_reg_XMRegister_Q_reg_24_ ( .D(n368), .CK(clk), .RN(
n1716), .Q(Op_MX[24]) );
DFFRX1TS Operands_load_reg_YMRegister_Q_reg_27_ ( .D(n339), .CK(clk), .RN(
n1711), .Q(Op_MY[27]) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_3_ ( .D(n315), .CK(clk), .RN(
n393), .Q(Op_MY[3]) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_4_ ( .D(n348), .CK(clk), .RN(
n1718), .Q(n392) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_4_ ( .D(n316), .CK(clk), .RN(
n1718), .Q(Op_MY[4]) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_5_ ( .D(n317), .CK(clk), .RN(
n393), .Q(Op_MY[5]) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_10_ ( .D(n322), .CK(clk), .RN(
n1709), .Q(n391) );
DFFRX4TS FS_Module_state_reg_reg_1_ ( .D(n378), .CK(clk), .RN(n167), .Q(
FS_Module_state_reg[1]) );
DFFRX2TS Sel_A_Q_reg_0_ ( .D(n376), .CK(clk), .RN(n1716), .Q(FSM_selector_A),
.QN(n1681) );
CMPR32X2TS DP_OP_36J10_126_4699_U10 ( .A(S_Oper_A_exp[0]), .B(
DP_OP_36J10_126_4699_n33), .C(DP_OP_36J10_126_4699_n22), .CO(
DP_OP_36J10_126_4699_n9), .S(Exp_module_Data_S[0]) );
OR2X6TS U406 ( .A(n1389), .B(FSM_selector_C), .Y(n1306) );
NAND2X4TS U407 ( .A(n1340), .B(n1339), .Y(n1352) );
CMPR32X2TS U408 ( .A(n632), .B(n572), .C(n631), .CO(n610), .S(n708) );
CMPR32X2TS U409 ( .A(n1197), .B(n1196), .C(n1195), .CO(n1192), .S(n1635) );
CMPR32X2TS U410 ( .A(Op_MX[10]), .B(Op_MX[22]), .C(n522), .CO(n515), .S(n637) );
CMPR32X2TS U411 ( .A(n391), .B(Op_MY[22]), .C(n525), .CO(n514), .S(n643) );
CMPR32X2TS U412 ( .A(n495), .B(Op_MY[21]), .C(n521), .CO(n525), .S(n657) );
CMPR32X2TS U413 ( .A(Op_MX[9]), .B(Op_MX[21]), .C(n517), .CO(n522), .S(n661)
);
CMPR32X2TS U414 ( .A(n496), .B(Op_MX[20]), .C(n518), .CO(n517), .S(n604) );
CMPR32X2TS U415 ( .A(n492), .B(Op_MY[20]), .C(n519), .CO(n521), .S(n606) );
CMPR32X2TS U416 ( .A(Op_MX[7]), .B(Op_MX[19]), .C(n520), .CO(n518), .S(n551)
);
CMPR32X2TS U417 ( .A(Op_MY[7]), .B(Op_MY[19]), .C(n516), .CO(n519), .S(n546)
);
CMPR32X2TS U418 ( .A(n499), .B(Op_MX[18]), .C(n579), .CO(n520), .S(n611) );
CMPR32X2TS U419 ( .A(n498), .B(Op_MY[18]), .C(n577), .CO(n516), .S(n750) );
CMPR32X2TS U420 ( .A(Op_MY[16]), .B(Op_MY[22]), .C(n848), .CO(n847), .S(n872) );
CMPR32X2TS U421 ( .A(n483), .B(Op_MY[21]), .C(n850), .CO(n848), .S(n874) );
CMPR32X2TS U422 ( .A(Op_MY[5]), .B(Op_MY[17]), .C(n578), .CO(n577), .S(n752)
);
CMPR32X4TS U423 ( .A(Op_MX[5]), .B(Op_MX[17]), .C(n571), .CO(n579), .S(n572)
);
CMPR32X2TS U424 ( .A(Op_MX[16]), .B(Op_MX[22]), .C(n844), .CO(n876), .S(n846) );
CMPR32X2TS U425 ( .A(n485), .B(Op_MY[20]), .C(n852), .CO(n850), .S(n883) );
CMPR32X2TS U426 ( .A(Op_MY[4]), .B(Op_MY[16]), .C(n580), .CO(n578), .S(n730)
);
CMPR32X2TS U427 ( .A(Op_MY[13]), .B(Op_MY[19]), .C(n854), .CO(n852), .S(
n1129) );
CMPR32X2TS U428 ( .A(n487), .B(Op_MX[20]), .C(n859), .CO(n842), .S(n861) );
CMPR32X4TS U429 ( .A(Op_MX[3]), .B(Op_MX[15]), .C(n573), .CO(n575), .S(n574)
);
CMPR32X4TS U430 ( .A(n493), .B(Op_MX[13]), .C(n528), .CO(n582), .S(n529) );
CMPR32X2TS U431 ( .A(n1097), .B(n1196), .C(n1096), .CO(n1114), .S(n1116) );
CMPR32X2TS U432 ( .A(n392), .B(Op_MX[10]), .C(n962), .CO(n993), .S(n963) );
NOR2XLTS U433 ( .A(n773), .B(n763), .Y(n809) );
NOR2XLTS U434 ( .A(n402), .B(n420), .Y(n834) );
NOR2XLTS U435 ( .A(n402), .B(n486), .Y(n831) );
NOR2XLTS U436 ( .A(n747), .B(n736), .Y(n794) );
AO22X1TS U437 ( .A0(n1661), .A1(P_Sgf[47]), .B0(n1660), .B1(n1659), .Y(n237)
);
AO22X1TS U438 ( .A0(n1629), .A1(P_Sgf[46]), .B0(n1660), .B1(n1511), .Y(n284)
);
AO22X1TS U439 ( .A0(n1661), .A1(P_Sgf[45]), .B0(n1612), .B1(n1514), .Y(n283)
);
AO22X1TS U440 ( .A0(n1629), .A1(P_Sgf[44]), .B0(n1643), .B1(n1517), .Y(n282)
);
AO22X1TS U441 ( .A0(n1661), .A1(P_Sgf[43]), .B0(n1643), .B1(n1520), .Y(n281)
);
AO22X1TS U442 ( .A0(n1629), .A1(P_Sgf[42]), .B0(n1612), .B1(n1523), .Y(n280)
);
AO22X1TS U443 ( .A0(n1661), .A1(P_Sgf[41]), .B0(n1612), .B1(n1526), .Y(n279)
);
AO22X1TS U444 ( .A0(n1629), .A1(P_Sgf[40]), .B0(n1612), .B1(n1529), .Y(n278)
);
AO22X1TS U445 ( .A0(n1661), .A1(P_Sgf[39]), .B0(n1612), .B1(n1532), .Y(n277)
);
AO22X1TS U446 ( .A0(n1629), .A1(P_Sgf[38]), .B0(n1612), .B1(n1535), .Y(n276)
);
AO22X1TS U447 ( .A0(n1661), .A1(P_Sgf[37]), .B0(n1612), .B1(n1539), .Y(n275)
);
ADDFX1TS U448 ( .A(n1586), .B(n1585), .CI(n1584), .CO(n1580), .S(n1587) );
OAI21X1TS U449 ( .A0(n1141), .A1(n1140), .B0(n1142), .Y(n1139) );
OAI21X1TS U450 ( .A0(n1101), .A1(n1100), .B0(n1102), .Y(n1099) );
OAI21X1TS U451 ( .A0(n748), .A1(n712), .B0(n700), .Y(n699) );
NOR2X1TS U452 ( .A(n754), .B(n770), .Y(n626) );
NOR2X1TS U453 ( .A(n754), .B(n790), .Y(DP_OP_153J10_122_5442_n155) );
NOR2X1TS U454 ( .A(n771), .B(n790), .Y(n629) );
NOR2X1TS U455 ( .A(n760), .B(n790), .Y(n635) );
NOR2X1TS U456 ( .A(n755), .B(n789), .Y(n627) );
NOR2X1TS U457 ( .A(n759), .B(n789), .Y(n633) );
NOR2X1TS U458 ( .A(n755), .B(n757), .Y(DP_OP_153J10_122_5442_n176) );
NOR2X1TS U459 ( .A(n790), .B(n789), .Y(n791) );
NOR2X1TS U460 ( .A(n773), .B(n765), .Y(n674) );
NOR2X1TS U461 ( .A(n773), .B(n743), .Y(n767) );
NOR2X1TS U462 ( .A(n772), .B(n769), .Y(n810) );
NOR2X1TS U463 ( .A(n773), .B(n812), .Y(n540) );
NOR2X1TS U464 ( .A(n765), .B(n769), .Y(n808) );
ADDFX1TS U465 ( .A(n614), .B(n752), .CI(n613), .CO(n619), .S(n615) );
NOR2X1TS U466 ( .A(n743), .B(n680), .Y(n675) );
NOR2X1TS U467 ( .A(n772), .B(n680), .Y(n807) );
CLKBUFX3TS U468 ( .A(n860), .Y(n937) );
NAND2X2TS U469 ( .A(n876), .B(Op_MX[17]), .Y(n1140) );
INVX3TS U470 ( .A(n574), .Y(n729) );
INVX3TS U471 ( .A(n914), .Y(n917) );
OR3X2TS U472 ( .A(underflow_flag), .B(overflow_flag), .C(n1662), .Y(n1664)
);
ADDFX1TS U473 ( .A(n392), .B(Op_MX[16]), .CI(n575), .CO(n571), .S(n621) );
INVX3TS U474 ( .A(n1035), .Y(n1039) );
NOR2X4TS U475 ( .A(n1385), .B(n1654), .Y(n1345) );
INVX6TS U476 ( .A(n1665), .Y(n1662) );
BUFX6TS U477 ( .A(n1722), .Y(n393) );
NAND2BX4TS U478 ( .AN(n1344), .B(n1343), .Y(n1660) );
ADDHX2TS U479 ( .A(Op_MX[18]), .B(n489), .CO(n858), .S(n1123) );
ADDHX2TS U480 ( .A(n489), .B(Op_MX[0]), .CO(n528), .S(n753) );
OA21X2TS U481 ( .A0(n1253), .A1(n1342), .B0(FS_Module_state_reg[1]), .Y(
n1254) );
ADDHX2TS U482 ( .A(n498), .B(Op_MY[0]), .CO(n971), .S(n1095) );
ADDHX2TS U483 ( .A(n499), .B(Op_MX[0]), .CO(n975), .S(n1086) );
INVX3TS U484 ( .A(n413), .Y(n495) );
INVX3TS U485 ( .A(n399), .Y(n492) );
INVX3TS U486 ( .A(n397), .Y(n496) );
ADDHX2TS U487 ( .A(Op_MY[12]), .B(Op_MY[0]), .CO(n547), .S(n600) );
INVX3TS U488 ( .A(n394), .Y(n499) );
ADDHX2TS U489 ( .A(Op_MY[18]), .B(Op_MY[12]), .CO(n854), .S(n1136) );
INVX3TS U490 ( .A(n412), .Y(n493) );
INVX2TS U491 ( .A(n400), .Y(n491) );
INVX3TS U492 ( .A(n395), .Y(n498) );
NOR2XLTS U493 ( .A(n756), .B(n783), .Y(n787) );
NOR2XLTS U494 ( .A(n784), .B(n783), .Y(n785) );
NOR2XLTS U495 ( .A(n756), .B(n757), .Y(n663) );
NOR2XLTS U496 ( .A(n771), .B(n758), .Y(DP_OP_153J10_122_5442_n151) );
NOR2XLTS U497 ( .A(n790), .B(n783), .Y(DP_OP_153J10_122_5442_n187) );
NOR2XLTS U498 ( .A(n760), .B(n784), .Y(n645) );
NOR2XLTS U499 ( .A(n759), .B(n757), .Y(n647) );
NOR2XLTS U500 ( .A(n797), .B(n783), .Y(n666) );
NOR2XLTS U501 ( .A(n759), .B(n761), .Y(DP_OP_153J10_122_5442_n202) );
NOR2XLTS U502 ( .A(n754), .B(n797), .Y(DP_OP_153J10_122_5442_n158) );
NOR2XLTS U503 ( .A(n784), .B(n789), .Y(n652) );
NOR2XLTS U504 ( .A(n790), .B(n757), .Y(n651) );
NOR2XLTS U505 ( .A(n770), .B(n796), .Y(DP_OP_153J10_122_5442_n193) );
NOR2XLTS U506 ( .A(n771), .B(n797), .Y(DP_OP_153J10_122_5442_n150) );
NOR2XLTS U507 ( .A(n754), .B(n784), .Y(DP_OP_153J10_122_5442_n156) );
NOR2XLTS U508 ( .A(n765), .B(n680), .Y(n806) );
NOR2XLTS U509 ( .A(n743), .B(n764), .Y(n684) );
NOR2XLTS U510 ( .A(n743), .B(n762), .Y(n677) );
NOR2XLTS U511 ( .A(n726), .B(n747), .Y(n593) );
CLKAND2X2TS U512 ( .A(Op_MY[7]), .B(Op_MX[9]), .Y(n1075) );
CLKAND2X2TS U513 ( .A(n498), .B(Op_MX[10]), .Y(n1074) );
CLKAND2X2TS U514 ( .A(Op_MY[7]), .B(Op_MX[10]), .Y(n1085) );
CLKAND2X2TS U515 ( .A(Op_MX[11]), .B(n498), .Y(n1084) );
CLKAND2X2TS U516 ( .A(n495), .B(n496), .Y(n1055) );
CLKAND2X2TS U517 ( .A(n492), .B(Op_MX[9]), .Y(n1057) );
CLKAND2X2TS U518 ( .A(Op_MY[11]), .B(n499), .Y(n1056) );
CLKAND2X2TS U519 ( .A(Op_MX[11]), .B(Op_MY[7]), .Y(n1080) );
CLKAND2X2TS U520 ( .A(n492), .B(Op_MX[10]), .Y(n1081) );
CLKAND2X2TS U521 ( .A(Op_MY[11]), .B(Op_MX[7]), .Y(n1059) );
CLKAND2X2TS U522 ( .A(n391), .B(n496), .Y(n1058) );
CLKAND2X2TS U523 ( .A(n495), .B(Op_MX[9]), .Y(n1060) );
NOR2XLTS U524 ( .A(n758), .B(n796), .Y(n667) );
NOR2XLTS U525 ( .A(n797), .B(n761), .Y(n669) );
NOR2XLTS U526 ( .A(n758), .B(n761), .Y(n1439) );
CLKAND2X2TS U527 ( .A(n495), .B(Op_MX[10]), .Y(n1064) );
CLKAND2X2TS U528 ( .A(Op_MX[11]), .B(n492), .Y(n1066) );
CLKAND2X2TS U529 ( .A(Op_MY[11]), .B(n496), .Y(n1065) );
NOR2XLTS U530 ( .A(n763), .B(n762), .Y(n524) );
NOR2XLTS U531 ( .A(n763), .B(n680), .Y(n682) );
NOR2XLTS U532 ( .A(n765), .B(n762), .Y(n681) );
NOR2XLTS U533 ( .A(n772), .B(n764), .Y(n686) );
NOR2XLTS U534 ( .A(n679), .B(n769), .Y(n688) );
NOR2XLTS U535 ( .A(n404), .B(n486), .Y(n833) );
NOR2XLTS U536 ( .A(n419), .B(n403), .Y(n911) );
NOR2XLTS U537 ( .A(n484), .B(n421), .Y(n912) );
NOR2XLTS U538 ( .A(n812), .B(n764), .Y(DP_OP_153J10_122_5442_n311) );
NOR2XLTS U539 ( .A(n419), .B(n484), .Y(n832) );
NOR2XLTS U540 ( .A(n913), .B(n421), .Y(n830) );
NOR2XLTS U541 ( .A(n921), .B(n1124), .Y(DP_OP_154J10_123_2038_n100) );
CLKAND2X2TS U542 ( .A(Op_MX[22]), .B(Op_MY[18]), .Y(n941) );
CLKAND2X2TS U543 ( .A(Op_MY[19]), .B(Op_MX[21]), .Y(n942) );
CLKAND2X2TS U544 ( .A(Op_MY[20]), .B(Op_MX[21]), .Y(n926) );
CLKAND2X2TS U545 ( .A(Op_MX[22]), .B(Op_MY[19]), .Y(n928) );
CLKAND2X2TS U546 ( .A(Op_MY[22]), .B(Op_MX[19]), .Y(n927) );
CLKAND2X2TS U547 ( .A(Op_MY[22]), .B(Op_MX[20]), .Y(n929) );
CLKAND2X2TS U548 ( .A(Op_MY[21]), .B(Op_MX[21]), .Y(n931) );
CLKAND2X2TS U549 ( .A(Op_MX[22]), .B(Op_MY[20]), .Y(n930) );
CLKAND2X2TS U550 ( .A(Op_MX[22]), .B(Op_MY[21]), .Y(n841) );
CLKAND2X2TS U551 ( .A(Op_MX[5]), .B(n491), .Y(n1082) );
CLKAND2X2TS U552 ( .A(Op_MY[2]), .B(n392), .Y(n1083) );
CLKAND2X2TS U553 ( .A(Op_MY[4]), .B(Op_MX[2]), .Y(n1061) );
CLKAND2X2TS U554 ( .A(Op_MY[3]), .B(Op_MX[3]), .Y(n1063) );
CLKAND2X2TS U555 ( .A(Op_MY[5]), .B(n493), .Y(n1062) );
CLKAND2X2TS U556 ( .A(Op_MX[5]), .B(Op_MY[2]), .Y(n1045) );
CLKAND2X2TS U557 ( .A(Op_MY[5]), .B(Op_MX[2]), .Y(n1044) );
CLKAND2X2TS U558 ( .A(Op_MY[3]), .B(n392), .Y(n1043) );
CLKAND2X2TS U559 ( .A(Op_MY[7]), .B(Op_MX[7]), .Y(n511) );
CLKAND2X2TS U560 ( .A(n492), .B(n499), .Y(n512) );
CLKAND2X2TS U561 ( .A(n498), .B(Op_MX[9]), .Y(n1072) );
CLKAND2X2TS U562 ( .A(Op_MY[7]), .B(n496), .Y(n1073) );
CLKAND2X2TS U563 ( .A(n492), .B(Op_MX[7]), .Y(n510) );
CLKAND2X2TS U564 ( .A(n495), .B(n499), .Y(n509) );
CLKAND2X2TS U565 ( .A(n495), .B(Op_MX[7]), .Y(DP_OP_155J10_124_2038_n365) );
CLKAND2X2TS U566 ( .A(n492), .B(n496), .Y(DP_OP_155J10_124_2038_n360) );
CLKAND2X2TS U567 ( .A(n391), .B(n499), .Y(DP_OP_155J10_124_2038_n370) );
CLKAND2X2TS U568 ( .A(n391), .B(Op_MX[7]), .Y(DP_OP_155J10_124_2038_n364) );
CLKAND2X2TS U569 ( .A(n391), .B(Op_MX[9]), .Y(DP_OP_155J10_124_2038_n352) );
CLKAND2X2TS U570 ( .A(Op_MY[11]), .B(Op_MX[9]), .Y(
DP_OP_155J10_124_2038_n351) );
CLKAND2X2TS U571 ( .A(n391), .B(Op_MX[10]), .Y(DP_OP_155J10_124_2038_n346)
);
CLKAND2X2TS U572 ( .A(Op_MX[11]), .B(n495), .Y(DP_OP_155J10_124_2038_n341)
);
CLKAND2X2TS U573 ( .A(Op_MY[11]), .B(Op_MX[10]), .Y(n1020) );
CLKAND2X2TS U574 ( .A(Op_MX[11]), .B(n391), .Y(n1021) );
NOR2XLTS U575 ( .A(n405), .B(n421), .Y(n903) );
NOR2XLTS U576 ( .A(n403), .B(n422), .Y(n904) );
NOR2XLTS U577 ( .A(n913), .B(n486), .Y(n836) );
NOR2XLTS U578 ( .A(n419), .B(n405), .Y(n839) );
NOR2XLTS U579 ( .A(n403), .B(n421), .Y(n840) );
NOR2XLTS U580 ( .A(n679), .B(n680), .Y(n532) );
AOI2BB2XLTS U581 ( .B0(n876), .B1(Op_MX[17]), .A0N(Op_MX[17]), .A1N(n876),
.Y(n845) );
NOR2XLTS U582 ( .A(n419), .B(n404), .Y(n899) );
CLKAND2X2TS U583 ( .A(Op_MY[19]), .B(Op_MX[19]), .Y(n503) );
CLKAND2X2TS U584 ( .A(Op_MY[20]), .B(Op_MX[18]), .Y(n504) );
CLKAND2X2TS U585 ( .A(Op_MY[19]), .B(Op_MX[20]), .Y(n933) );
CLKAND2X2TS U586 ( .A(Op_MY[18]), .B(Op_MX[21]), .Y(n932) );
CLKAND2X2TS U587 ( .A(Op_MY[20]), .B(Op_MX[19]), .Y(n502) );
CLKAND2X2TS U588 ( .A(Op_MY[21]), .B(Op_MX[18]), .Y(n501) );
CLKAND2X2TS U589 ( .A(Op_MY[21]), .B(Op_MX[19]), .Y(
DP_OP_154J10_123_2038_n364) );
CLKAND2X2TS U590 ( .A(Op_MY[20]), .B(Op_MX[20]), .Y(
DP_OP_154J10_123_2038_n359) );
CLKAND2X2TS U591 ( .A(Op_MY[22]), .B(Op_MX[18]), .Y(
DP_OP_154J10_123_2038_n369) );
CLKAND2X2TS U592 ( .A(Op_MY[21]), .B(Op_MX[20]), .Y(
DP_OP_154J10_123_2038_n358) );
CLKAND2X2TS U593 ( .A(Op_MY[22]), .B(Op_MX[21]), .Y(
DP_OP_154J10_123_2038_n351) );
CLKAND2X2TS U594 ( .A(Op_MY[22]), .B(Op_MX[22]), .Y(
DP_OP_154J10_123_2038_n345) );
CLKAND2X2TS U595 ( .A(Op_MY[0]), .B(n392), .Y(n1076) );
CLKAND2X2TS U596 ( .A(n491), .B(Op_MX[3]), .Y(n1077) );
CLKAND2X2TS U597 ( .A(Op_MX[5]), .B(Op_MY[0]), .Y(n1078) );
CLKAND2X2TS U598 ( .A(n491), .B(n392), .Y(n1079) );
CLKAND2X2TS U599 ( .A(Op_MY[3]), .B(Op_MX[2]), .Y(n1069) );
CLKAND2X2TS U600 ( .A(Op_MY[2]), .B(Op_MX[3]), .Y(n1071) );
CLKAND2X2TS U601 ( .A(Op_MY[5]), .B(Op_MX[0]), .Y(n1070) );
CLKAND2X2TS U602 ( .A(Op_MY[4]), .B(Op_MX[3]), .Y(DP_OP_155J10_124_2038_n261) );
CLKAND2X2TS U603 ( .A(Op_MX[5]), .B(Op_MY[3]), .Y(DP_OP_155J10_124_2038_n250) );
CLKAND2X2TS U604 ( .A(Op_MY[5]), .B(Op_MX[3]), .Y(DP_OP_155J10_124_2038_n260) );
CLKAND2X2TS U605 ( .A(Op_MY[4]), .B(n392), .Y(DP_OP_155J10_124_2038_n255) );
CLKAND2X2TS U606 ( .A(Op_MX[5]), .B(Op_MY[4]), .Y(n1029) );
CLKAND2X2TS U607 ( .A(Op_MY[5]), .B(n392), .Y(n1028) );
CLKAND2X2TS U608 ( .A(n498), .B(Op_MX[7]), .Y(n1005) );
CLKAND2X2TS U609 ( .A(Op_MY[7]), .B(n499), .Y(n1004) );
CLKAND2X2TS U610 ( .A(n498), .B(n496), .Y(n1010) );
CLKAND2X2TS U611 ( .A(Op_MY[11]), .B(Op_MX[11]), .Y(n1025) );
NOR2XLTS U612 ( .A(n403), .B(n420), .Y(n821) );
NOR2XLTS U613 ( .A(n401), .B(n418), .Y(n822) );
NOR2XLTS U614 ( .A(n405), .B(n422), .Y(n924) );
NOR2XLTS U615 ( .A(n403), .B(n417), .Y(n925) );
NOR2XLTS U616 ( .A(n484), .B(n420), .Y(n820) );
NOR2XLTS U617 ( .A(n913), .B(n488), .Y(n819) );
NOR2XLTS U618 ( .A(n1124), .B(n867), .Y(n1160) );
NOR2XLTS U619 ( .A(n419), .B(n402), .Y(n909) );
CLKAND2X2TS U620 ( .A(Op_MY[18]), .B(Op_MX[19]), .Y(n886) );
CLKAND2X2TS U621 ( .A(Op_MY[19]), .B(Op_MX[18]), .Y(n885) );
CLKAND2X2TS U622 ( .A(Op_MY[18]), .B(Op_MX[20]), .Y(n888) );
CLKAND2X2TS U623 ( .A(Op_MY[2]), .B(Op_MX[0]), .Y(n952) );
CLKAND2X2TS U624 ( .A(n491), .B(n493), .Y(n951) );
CLKAND2X2TS U625 ( .A(Op_MY[0]), .B(Op_MX[3]), .Y(n1067) );
CLKAND2X2TS U626 ( .A(n491), .B(Op_MX[2]), .Y(n1068) );
CLKAND2X2TS U627 ( .A(Op_MY[3]), .B(Op_MX[0]), .Y(n949) );
CLKAND2X2TS U628 ( .A(Op_MY[2]), .B(n493), .Y(n950) );
CLKAND2X2TS U629 ( .A(Op_MY[2]), .B(Op_MX[2]), .Y(DP_OP_155J10_124_2038_n269) );
CLKAND2X2TS U630 ( .A(Op_MY[4]), .B(Op_MX[0]), .Y(DP_OP_155J10_124_2038_n279) );
CLKAND2X2TS U631 ( .A(Op_MY[3]), .B(n493), .Y(DP_OP_155J10_124_2038_n274) );
CLKAND2X2TS U632 ( .A(Op_MY[4]), .B(n493), .Y(DP_OP_155J10_124_2038_n273) );
CLKAND2X2TS U633 ( .A(Op_MY[5]), .B(Op_MX[5]), .Y(n1033) );
NOR2XLTS U634 ( .A(n405), .B(n486), .Y(n892) );
NAND3XLTS U635 ( .A(FS_Module_state_reg[1]), .B(FSM_add_overflow_flag), .C(
n1342), .Y(n1343) );
CLKAND2X2TS U636 ( .A(n491), .B(Op_MX[0]), .Y(n1088) );
CLKAND2X2TS U637 ( .A(Op_MY[0]), .B(n493), .Y(n1089) );
CLKAND2X2TS U638 ( .A(Op_MY[0]), .B(Op_MX[2]), .Y(n1007) );
AO22XLTS U639 ( .A0(Data_MY[27]), .A1(n1341), .B0(n1359), .B1(Op_MY[27]),
.Y(n339) );
AO22XLTS U640 ( .A0(Data_MX[24]), .A1(n1361), .B0(n1359), .B1(Op_MX[24]),
.Y(n368) );
AO22XLTS U641 ( .A0(Data_MX[28]), .A1(n1361), .B0(n1359), .B1(Op_MX[28]),
.Y(n372) );
AO22XLTS U642 ( .A0(n1341), .A1(Data_MY[16]), .B0(n1358), .B1(Op_MY[16]),
.Y(n328) );
AO22XLTS U643 ( .A0(n1361), .A1(Data_MX[16]), .B0(n1362), .B1(Op_MX[16]),
.Y(n360) );
AO22XLTS U644 ( .A0(n1361), .A1(Data_MX[15]), .B0(n1362), .B1(Op_MX[15]),
.Y(n359) );
AO22XLTS U645 ( .A0(n1341), .A1(Data_MY[13]), .B0(n1360), .B1(Op_MY[13]),
.Y(n325) );
AO22XLTS U646 ( .A0(n1361), .A1(Data_MX[13]), .B0(n1362), .B1(Op_MX[13]),
.Y(n357) );
AO22XLTS U647 ( .A0(n1363), .A1(Data_MY[7]), .B0(n1360), .B1(Op_MY[7]), .Y(
n319) );
AO22XLTS U648 ( .A0(n1361), .A1(Data_MX[5]), .B0(n1358), .B1(Op_MX[5]), .Y(
n349) );
AO22XLTS U649 ( .A0(n1363), .A1(Data_MX[3]), .B0(n1358), .B1(Op_MX[3]), .Y(
n347) );
AO22XLTS U650 ( .A0(n1363), .A1(Data_MX[7]), .B0(n1358), .B1(Op_MX[7]), .Y(
n351) );
AO22XLTS U651 ( .A0(n1363), .A1(Data_MY[19]), .B0(n1359), .B1(Op_MY[19]),
.Y(n331) );
AO22XLTS U652 ( .A0(n1361), .A1(Data_MX[10]), .B0(n1358), .B1(Op_MX[10]),
.Y(n354) );
AO22XLTS U653 ( .A0(n1361), .A1(Data_MX[18]), .B0(n1362), .B1(Op_MX[18]),
.Y(n362) );
AO22XLTS U654 ( .A0(n1363), .A1(Data_MY[20]), .B0(n1359), .B1(Op_MY[20]),
.Y(n332) );
AO22XLTS U655 ( .A0(n1363), .A1(Data_MY[0]), .B0(n1362), .B1(Op_MY[0]), .Y(
n312) );
AO22XLTS U656 ( .A0(n1363), .A1(Data_MX[22]), .B0(n1362), .B1(Op_MX[22]),
.Y(n366) );
AO22XLTS U657 ( .A0(n1361), .A1(Data_MX[19]), .B0(n1362), .B1(Op_MX[19]),
.Y(n363) );
AO22XLTS U658 ( .A0(n1361), .A1(Data_MX[20]), .B0(n1362), .B1(Op_MX[20]),
.Y(n364) );
AO22XLTS U659 ( .A0(n1361), .A1(Data_MX[21]), .B0(n1362), .B1(Op_MX[21]),
.Y(n365) );
AO22XLTS U660 ( .A0(n1363), .A1(Data_MY[18]), .B0(n1359), .B1(Op_MY[18]),
.Y(n330) );
AO22XLTS U661 ( .A0(Data_MX[25]), .A1(n1341), .B0(n1359), .B1(Op_MX[25]),
.Y(n369) );
AO22XLTS U662 ( .A0(Data_MX[27]), .A1(n1341), .B0(n1359), .B1(Op_MX[27]),
.Y(n371) );
AO22XLTS U663 ( .A0(Data_MX[26]), .A1(n1341), .B0(n1359), .B1(Op_MX[26]),
.Y(n370) );
AO22XLTS U664 ( .A0(Data_MX[23]), .A1(n1341), .B0(n1359), .B1(Op_MX[23]),
.Y(n367) );
AO22XLTS U665 ( .A0(n1363), .A1(Data_MY[4]), .B0(n1360), .B1(Op_MY[4]), .Y(
n316) );
AO22XLTS U666 ( .A0(n1361), .A1(Data_MY[5]), .B0(n1360), .B1(Op_MY[5]), .Y(
n317) );
AO22XLTS U667 ( .A0(n1363), .A1(Data_MY[2]), .B0(n1362), .B1(Op_MY[2]), .Y(
n314) );
AO22XLTS U668 ( .A0(n1361), .A1(Data_MY[3]), .B0(n1360), .B1(Op_MY[3]), .Y(
n315) );
AO22XLTS U669 ( .A0(n1361), .A1(Data_MY[11]), .B0(n1360), .B1(Op_MY[11]),
.Y(n323) );
AO22XLTS U670 ( .A0(n1341), .A1(Data_MY[17]), .B0(n1360), .B1(Op_MY[17]),
.Y(n329) );
AO22XLTS U671 ( .A0(n1361), .A1(Data_MY[12]), .B0(n1360), .B1(Op_MY[12]),
.Y(n324) );
AO22XLTS U672 ( .A0(n1361), .A1(Data_MX[17]), .B0(n1362), .B1(Op_MX[17]),
.Y(n361) );
AO22XLTS U673 ( .A0(n1361), .A1(Data_MX[9]), .B0(n1358), .B1(Op_MX[9]), .Y(
n353) );
AO22XLTS U674 ( .A0(n1363), .A1(Data_MX[2]), .B0(n1358), .B1(Op_MX[2]), .Y(
n346) );
AO22XLTS U675 ( .A0(n1363), .A1(Data_MY[22]), .B0(n1358), .B1(Op_MY[22]),
.Y(n334) );
AO22XLTS U676 ( .A0(n1363), .A1(Data_MX[0]), .B0(n1359), .B1(Op_MX[0]), .Y(
n344) );
AO22XLTS U677 ( .A0(n1363), .A1(Data_MY[21]), .B0(n1360), .B1(Op_MY[21]),
.Y(n333) );
AO22XLTS U678 ( .A0(n1361), .A1(Data_MX[11]), .B0(n1358), .B1(Op_MX[11]),
.Y(n355) );
AO22XLTS U679 ( .A0(n1661), .A1(P_Sgf[1]), .B0(n1654), .B1(n1652), .Y(n239)
);
AO22XLTS U680 ( .A0(n1629), .A1(P_Sgf[24]), .B0(n1643), .B1(n1591), .Y(n262)
);
AO22XLTS U681 ( .A0(n1629), .A1(P_Sgf[25]), .B0(n1643), .B1(n1587), .Y(n263)
);
AO22XLTS U682 ( .A0(n1629), .A1(P_Sgf[26]), .B0(n1643), .B1(n1583), .Y(n264)
);
AO22XLTS U683 ( .A0(n1629), .A1(P_Sgf[27]), .B0(n1643), .B1(n1579), .Y(n265)
);
AO22XLTS U684 ( .A0(n1629), .A1(P_Sgf[28]), .B0(n1643), .B1(n1575), .Y(n266)
);
AO22XLTS U685 ( .A0(n1629), .A1(P_Sgf[29]), .B0(n1643), .B1(n1571), .Y(n267)
);
AO22XLTS U686 ( .A0(n1629), .A1(P_Sgf[30]), .B0(n1643), .B1(n1567), .Y(n268)
);
AO22XLTS U687 ( .A0(n1629), .A1(P_Sgf[31]), .B0(n1612), .B1(n1563), .Y(n269)
);
AO22XLTS U688 ( .A0(n1629), .A1(P_Sgf[32]), .B0(n1612), .B1(n1559), .Y(n270)
);
AO22XLTS U689 ( .A0(n1661), .A1(P_Sgf[33]), .B0(n1612), .B1(n1555), .Y(n271)
);
AO22XLTS U690 ( .A0(n1629), .A1(P_Sgf[34]), .B0(n1612), .B1(n1551), .Y(n272)
);
AO22XLTS U691 ( .A0(n1661), .A1(P_Sgf[35]), .B0(n1612), .B1(n1547), .Y(n273)
);
AO22XLTS U692 ( .A0(n1629), .A1(P_Sgf[36]), .B0(n1612), .B1(n1543), .Y(n274)
);
AO22XLTS U693 ( .A0(n1341), .A1(Data_MY[1]), .B0(n1362), .B1(n491), .Y(n313)
);
AO22XLTS U694 ( .A0(n1361), .A1(Data_MY[6]), .B0(n1360), .B1(n498), .Y(n318)
);
AO22XLTS U695 ( .A0(n1361), .A1(Data_MY[8]), .B0(n1360), .B1(n492), .Y(n320)
);
AO22XLTS U696 ( .A0(n1341), .A1(Data_MY[9]), .B0(n1360), .B1(n495), .Y(n321)
);
AO22XLTS U697 ( .A0(n1361), .A1(Data_MY[10]), .B0(n1360), .B1(n391), .Y(n322) );
AO22XLTS U698 ( .A0(n1361), .A1(Data_MY[14]), .B0(n1359), .B1(n485), .Y(n326) );
AO22XLTS U699 ( .A0(n1341), .A1(Data_MY[15]), .B0(n1360), .B1(n483), .Y(n327) );
OAI211XLTS U700 ( .A0(Sgf_normalized_result[3]), .A1(n1393), .B0(n1438),
.C0(n1395), .Y(n1394) );
AO22XLTS U701 ( .A0(n1438), .A1(n1396), .B0(n1433), .B1(n463), .Y(n305) );
OAI211XLTS U702 ( .A0(Sgf_normalized_result[5]), .A1(n1397), .B0(n1428),
.C0(n1399), .Y(n1398) );
AO22XLTS U703 ( .A0(n1438), .A1(n1400), .B0(n1433), .B1(n474), .Y(n303) );
AO22XLTS U704 ( .A0(n1438), .A1(n1404), .B0(n1433), .B1(n475), .Y(n301) );
AO22XLTS U705 ( .A0(n1438), .A1(n1407), .B0(n1433), .B1(n476), .Y(n299) );
AO22XLTS U706 ( .A0(n1438), .A1(n1411), .B0(n1433), .B1(n477), .Y(n297) );
AO22XLTS U707 ( .A0(n1438), .A1(n1415), .B0(n1433), .B1(n478), .Y(n295) );
AO22XLTS U708 ( .A0(n1438), .A1(n1419), .B0(n1433), .B1(n479), .Y(n293) );
AO22XLTS U709 ( .A0(n1438), .A1(n1423), .B0(n1433), .B1(n480), .Y(n291) );
AO22XLTS U710 ( .A0(n1438), .A1(n1427), .B0(n1433), .B1(n481), .Y(n289) );
AO22XLTS U711 ( .A0(n1341), .A1(Data_MX[1]), .B0(n1358), .B1(n493), .Y(n345)
);
AO22XLTS U712 ( .A0(n1341), .A1(Data_MX[4]), .B0(n1358), .B1(n392), .Y(n348)
);
AO22XLTS U713 ( .A0(n1341), .A1(Data_MX[6]), .B0(n1358), .B1(n499), .Y(n350)
);
AO22XLTS U714 ( .A0(n1361), .A1(Data_MX[8]), .B0(n1358), .B1(n496), .Y(n352)
);
AO22XLTS U715 ( .A0(n1361), .A1(Data_MX[12]), .B0(n1362), .B1(n489), .Y(n356) );
AO22XLTS U716 ( .A0(n1361), .A1(Data_MX[14]), .B0(n1362), .B1(n487), .Y(n358) );
AO22XLTS U717 ( .A0(Data_MX[29]), .A1(n1341), .B0(n1359), .B1(n457), .Y(n373) );
AO22XLTS U718 ( .A0(Data_MX[30]), .A1(n1341), .B0(n1359), .B1(n456), .Y(n374) );
OR2X1TS U719 ( .A(Op_MX[27]), .B(Op_MX[26]), .Y(n410) );
OR2X1TS U720 ( .A(Op_MY[2]), .B(Op_MY[3]), .Y(n411) );
OR2X1TS U721 ( .A(n1669), .B(n1403), .Y(n424) );
OR2X1TS U722 ( .A(Op_MX[23]), .B(Op_MX[25]), .Y(n427) );
OR2X1TS U723 ( .A(Op_MY[4]), .B(Op_MY[5]), .Y(n429) );
CLKINVX6TS U724 ( .A(rst), .Y(n167) );
ADDHX1TS U725 ( .A(n779), .B(n778), .CO(n648), .S(DP_OP_153J10_122_5442_n97)
);
ADDHX1TS U726 ( .A(Op_MY[19]), .B(Op_MX[19]), .CO(DP_OP_154J10_123_2038_n319), .S(DP_OP_154J10_123_2038_n320) );
ADDHX1TS U727 ( .A(n1052), .B(n1051), .CO(DP_OP_155J10_124_2038_n61), .S(
DP_OP_155J10_124_2038_n62) );
NOR2X1TS U728 ( .A(n743), .B(n769), .Y(DP_OP_153J10_122_5442_n292) );
NOR2X2TS U729 ( .A(n1680), .B(n1431), .Y(n1434) );
NOR2X2TS U730 ( .A(n1668), .B(n1399), .Y(n1401) );
INVX2TS U731 ( .A(n424), .Y(n452) );
NOR2X2TS U732 ( .A(n1670), .B(n1406), .Y(n1408) );
NOR2X2TS U733 ( .A(n1671), .B(n1410), .Y(n1412) );
NOR2X2TS U734 ( .A(n1672), .B(n1414), .Y(n1416) );
NOR2X2TS U735 ( .A(n1673), .B(n1418), .Y(n1420) );
NOR2X2TS U736 ( .A(n1676), .B(n1422), .Y(n1424) );
NOR2X2TS U737 ( .A(n1677), .B(n1426), .Y(n1429) );
NOR4X1TS U738 ( .A(n499), .B(Op_MX[7]), .C(n496), .D(Op_MX[9]), .Y(n1376) );
NOR4X1TS U739 ( .A(n498), .B(Op_MY[7]), .C(n492), .D(n495), .Y(n1368) );
NOR4X1TS U740 ( .A(Op_MX[2]), .B(Op_MX[3]), .C(n392), .D(Op_MX[5]), .Y(n1379) );
NOR4X1TS U741 ( .A(Op_MY[18]), .B(Op_MY[19]), .C(Op_MY[20]), .D(Op_MY[21]),
.Y(n1367) );
OAI22X2TS U742 ( .A0(beg_FSM), .A1(n1709), .B0(ack_FSM), .B1(n1322), .Y(
n1353) );
OAI2BB2X4TS U743 ( .B0(n402), .B1(n847), .A0N(n847), .A1N(n402), .Y(n919) );
BUFX4TS U744 ( .A(n1722), .Y(n1716) );
BUFX4TS U745 ( .A(n1722), .Y(n1718) );
BUFX4TS U746 ( .A(n1722), .Y(n1709) );
INVX6TS U747 ( .A(n1352), .Y(n1361) );
ADDHX1TS U748 ( .A(n1089), .B(n1088), .CO(n1008), .S(n1652) );
ADDHX1TS U749 ( .A(n1172), .B(n1171), .CO(n1173), .S(n1656) );
ADDHX1TS U750 ( .A(n611), .B(n610), .CO(n612), .S(n703) );
INVX2TS U751 ( .A(n426), .Y(n453) );
INVX2TS U752 ( .A(n408), .Y(n454) );
NOR4X1TS U753 ( .A(Op_MY[22]), .B(n453), .C(n454), .D(Op_MY[27]), .Y(n1364)
);
NOR3XLTS U754 ( .A(Op_MX[24]), .B(Op_MX[0]), .C(n493), .Y(n1378) );
INVX2TS U755 ( .A(n396), .Y(n455) );
INVX2TS U756 ( .A(n428), .Y(n456) );
INVX2TS U757 ( .A(n409), .Y(n457) );
NOR4X1TS U758 ( .A(Op_MX[22]), .B(n456), .C(n457), .D(Op_MX[28]), .Y(n1372)
);
INVX2TS U759 ( .A(n407), .Y(n458) );
NOR3XLTS U760 ( .A(Op_MY[23]), .B(Op_MY[0]), .C(n491), .Y(n1370) );
INVX2TS U761 ( .A(n398), .Y(n459) );
INVX2TS U762 ( .A(n425), .Y(n460) );
INVX2TS U763 ( .A(n450), .Y(n461) );
INVX2TS U764 ( .A(n451), .Y(n462) );
INVX2TS U765 ( .A(n449), .Y(n463) );
INVX2TS U766 ( .A(n441), .Y(n464) );
INVX2TS U767 ( .A(n442), .Y(n465) );
INVX2TS U768 ( .A(n443), .Y(n466) );
INVX2TS U769 ( .A(n444), .Y(n467) );
INVX2TS U770 ( .A(n445), .Y(n468) );
INVX2TS U771 ( .A(n446), .Y(n469) );
INVX2TS U772 ( .A(n447), .Y(n470) );
INVX2TS U773 ( .A(n448), .Y(n471) );
INVX2TS U774 ( .A(n440), .Y(n472) );
INVX2TS U775 ( .A(n439), .Y(n473) );
INVX2TS U776 ( .A(n431), .Y(n474) );
INVX2TS U777 ( .A(n432), .Y(n475) );
INVX2TS U778 ( .A(n433), .Y(n476) );
INVX2TS U779 ( .A(n434), .Y(n477) );
INVX2TS U780 ( .A(n435), .Y(n478) );
INVX2TS U781 ( .A(n436), .Y(n479) );
INVX2TS U782 ( .A(n437), .Y(n480) );
INVX2TS U783 ( .A(n438), .Y(n481) );
CLKBUFX3TS U784 ( .A(n1246), .Y(n1436) );
NOR2XLTS U785 ( .A(n773), .B(n679), .Y(n685) );
NOR2X4TS U786 ( .A(Op_MX[11]), .B(n515), .Y(n773) );
BUFX6TS U787 ( .A(n1255), .Y(n1302) );
CLKINVX3TS U788 ( .A(n1436), .Y(n1428) );
INVX3TS U789 ( .A(n1436), .Y(n1438) );
ADDHX1TS U790 ( .A(n1005), .B(n1004), .CO(n1011), .S(n1196) );
INVX3TS U791 ( .A(n1254), .Y(n1387) );
INVX3TS U792 ( .A(n1254), .Y(n1303) );
CLKINVX6TS U793 ( .A(n1664), .Y(n1663) );
BUFX6TS U794 ( .A(n1256), .Y(n1308) );
INVX2TS U795 ( .A(n406), .Y(n482) );
ADDHX1TS U796 ( .A(n1126), .B(n1125), .CO(n893), .S(n1585) );
NOR4X1TS U797 ( .A(n485), .B(n483), .C(Op_MY[16]), .D(Op_MY[17]), .Y(n1366)
);
NOR4X1TS U798 ( .A(n487), .B(Op_MX[15]), .C(Op_MX[16]), .D(Op_MX[17]), .Y(
n1374) );
INVX2TS U799 ( .A(n416), .Y(n483) );
CMPR32X4TS U800 ( .A(Op_MX[15]), .B(Op_MX[21]), .C(n842), .CO(n844), .S(n914) );
ADDFX2TS U801 ( .A(n491), .B(Op_MY[13]), .CI(n547), .CO(n585), .S(n607) );
NOR4X1TS U802 ( .A(n391), .B(Op_MY[11]), .C(Op_MY[12]), .D(Op_MY[13]), .Y(
n1369) );
NOR4X1TS U803 ( .A(Op_MX[10]), .B(Op_MX[11]), .C(n489), .D(Op_MX[13]), .Y(
n1377) );
INVX2TS U804 ( .A(Op_MY[14]), .Y(n484) );
INVX2TS U805 ( .A(n484), .Y(n485) );
INVX2TS U806 ( .A(Op_MX[14]), .Y(n486) );
INVX2TS U807 ( .A(n486), .Y(n487) );
INVX2TS U808 ( .A(Op_MX[12]), .Y(n488) );
INVX2TS U809 ( .A(n488), .Y(n489) );
INVX2TS U810 ( .A(n423), .Y(n490) );
ADDFX2TS U811 ( .A(n491), .B(Op_MY[7]), .CI(n971), .CO(n969), .S(n1092) );
CMPR32X4TS U812 ( .A(Op_MX[5]), .B(Op_MX[11]), .C(n993), .CO(n994), .S(n1037) );
CMPR32X4TS U813 ( .A(Op_MX[3]), .B(Op_MX[9]), .C(n960), .CO(n962), .S(n1035)
);
ADDFX2TS U814 ( .A(n493), .B(Op_MX[7]), .CI(n975), .CO(n976), .S(n1091) );
ADDFX2TS U815 ( .A(Op_MX[13]), .B(Op_MX[19]), .CI(n858), .CO(n859), .S(n1128) );
NOR4X1TS U816 ( .A(P_Sgf[6]), .B(P_Sgf[7]), .C(P_Sgf[8]), .D(P_Sgf[9]), .Y(
n1311) );
NOR2XLTS U817 ( .A(n410), .B(n427), .Y(n1373) );
NOR2XLTS U818 ( .A(n411), .B(n429), .Y(n1371) );
BUFX4TS U819 ( .A(n167), .Y(n1719) );
ADDHX1TS U820 ( .A(n750), .B(n619), .CO(n709), .S(n609) );
INVX6TS U821 ( .A(n1660), .Y(n1629) );
NOR2X4TS U822 ( .A(Op_MY[11]), .B(n514), .Y(n743) );
CLKAND2X4TS U823 ( .A(n1344), .B(n1249), .Y(DP_OP_36J10_126_4699_n33) );
INVX4TS U824 ( .A(n1352), .Y(n1341) );
BUFX6TS U825 ( .A(n1258), .Y(n1307) );
CLKINVX6TS U826 ( .A(n1244), .Y(n1722) );
NOR2X4TS U827 ( .A(Op_MY[17]), .B(n847), .Y(n1141) );
NOR3X2TS U828 ( .A(n1666), .B(FS_Module_state_reg[0]), .C(
FS_Module_state_reg[3]), .Y(n1344) );
NOR2XLTS U829 ( .A(n797), .B(n796), .Y(n801) );
NOR2XLTS U830 ( .A(n756), .B(n796), .Y(n665) );
NOR2XLTS U831 ( .A(n1087), .B(n1054), .Y(DP_OP_155J10_124_2038_n100) );
NOR2XLTS U832 ( .A(n765), .B(n764), .Y(n523) );
NOR2XLTS U833 ( .A(n913), .B(n422), .Y(n835) );
INVX2TS U834 ( .A(n1086), .Y(n984) );
NOR2XLTS U835 ( .A(n401), .B(n422), .Y(n838) );
NOR2XLTS U836 ( .A(n1124), .B(n937), .Y(DP_OP_154J10_123_2038_n118) );
NOR2XLTS U837 ( .A(n1087), .B(n1049), .Y(DP_OP_155J10_124_2038_n118) );
NOR2XLTS U838 ( .A(n1087), .B(n984), .Y(n1119) );
OAI211XLTS U839 ( .A0(Sgf_normalized_result[15]), .A1(n1416), .B0(n1428),
.C0(n1418), .Y(n1417) );
OAI211XLTS U840 ( .A0(n1248), .A1(n1674), .B0(n1436), .C0(n1386), .Y(n236)
);
OAI211XLTS U841 ( .A0(n1306), .A1(n1689), .B0(n1268), .C0(n1267), .Y(n203)
);
CMPR32X2TS U842 ( .A(Op_MY[22]), .B(Op_MX[22]), .C(
DP_OP_154J10_123_2038_n306), .CO(n881), .S(n506) );
CMPR32X2TS U843 ( .A(n502), .B(n501), .C(n500), .CO(n814), .S(n817) );
ADDHXLTS U844 ( .A(n504), .B(n503), .CO(n500), .S(n887) );
NOR2X1TS U845 ( .A(n881), .B(n880), .Y(DP_OP_154J10_123_2038_n192) );
INVX2TS U846 ( .A(DP_OP_154J10_123_2038_n192), .Y(
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[11]) );
CMPR32X2TS U847 ( .A(DP_OP_154J10_123_2038_n307), .B(n506), .C(n505), .CO(
n880), .S(Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[9]) );
CMPR32X2TS U848 ( .A(DP_OP_154J10_123_2038_n308), .B(
DP_OP_154J10_123_2038_n310), .C(n507), .CO(n505), .S(
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[8]) );
CMPR32X2TS U849 ( .A(n510), .B(n509), .C(n508), .CO(n944), .S(n947) );
ADDHXLTS U850 ( .A(n512), .B(n511), .CO(n508), .S(n1009) );
CMPR32X2TS U851 ( .A(DP_OP_155J10_124_2038_n308), .B(
DP_OP_155J10_124_2038_n310), .C(n513), .CO(n1022), .S(
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[8]) );
CLKXOR2X2TS U852 ( .A(Op_MY[11]), .B(n514), .Y(n812) );
CLKXOR2X2TS U853 ( .A(Op_MX[11]), .B(n515), .Y(n811) );
NOR2X1TS U854 ( .A(n743), .B(n811), .Y(n539) );
INVX2TS U855 ( .A(n546), .Y(n679) );
INVX2TS U856 ( .A(n661), .Y(n680) );
INVX2TS U857 ( .A(n604), .Y(n762) );
NOR2X1TS U858 ( .A(n679), .B(n762), .Y(n527) );
INVX2TS U859 ( .A(n606), .Y(n763) );
INVX2TS U860 ( .A(n551), .Y(n764) );
NOR2X1TS U861 ( .A(n763), .B(n764), .Y(n526) );
INVX2TS U862 ( .A(n657), .Y(n765) );
INVX2TS U863 ( .A(n637), .Y(n769) );
ADDHXLTS U864 ( .A(n524), .B(n523), .CO(n687), .S(n530) );
INVX2TS U865 ( .A(n643), .Y(n772) );
NOR2X1TS U866 ( .A(n811), .B(n679), .Y(n536) );
ADDHX1TS U867 ( .A(n527), .B(n526), .CO(n531), .S(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[1]) );
NOR2X1TS U868 ( .A(n679), .B(n764), .Y(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[0]) );
INVX4TS U869 ( .A(n529), .Y(DP_OP_153J10_122_5442_n412) );
CMPR32X2TS U870 ( .A(n532), .B(n531), .C(n530), .CO(n535), .S(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[2]) );
CMPR32X2TS U871 ( .A(n535), .B(n534), .C(n533), .CO(n537), .S(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[3]) );
CMPR32X2TS U872 ( .A(n537), .B(n536), .C(DP_OP_153J10_122_5442_n271), .CO(
n538), .S(Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[4]) );
CMPR32X2TS U873 ( .A(DP_OP_153J10_122_5442_n264), .B(
DP_OP_153J10_122_5442_n270), .C(n538), .CO(n672), .S(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[5]) );
CMPR32X2TS U874 ( .A(n540), .B(n539), .C(DP_OP_153J10_122_5442_n247), .CO(
n768), .S(n542) );
CMPR32X2TS U875 ( .A(DP_OP_153J10_122_5442_n248), .B(n542), .C(n541), .CO(
n766), .S(Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[9]) );
INVX2TS U876 ( .A(n1466), .Y(n555) );
INVX2TS U877 ( .A(Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[9]), .Y(
n557) );
INVX2TS U878 ( .A(Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[0]), .Y(
n1441) );
INVX2TS U879 ( .A(n600), .Y(n747) );
INVX2TS U880 ( .A(n753), .Y(n543) );
NOR2X1TS U881 ( .A(n747), .B(n543), .Y(n1510) );
INVX2TS U882 ( .A(n1510), .Y(n1440) );
INVX2TS U883 ( .A(n544), .Y(n758) );
INVX2TS U884 ( .A(n545), .Y(n761) );
ADDHXLTS U885 ( .A(n600), .B(n546), .CO(n608), .S(n544) );
INVX2TS U886 ( .A(n548), .Y(n797) );
AOI21X1TS U887 ( .A0(n600), .A1(n753), .B0(DP_OP_153J10_122_5442_n412), .Y(
n603) );
NAND2X1TS U888 ( .A(n529), .B(n543), .Y(n550) );
INVX2TS U889 ( .A(n607), .Y(n711) );
AOI22X1TS U890 ( .A0(n529), .A1(n711), .B0(n607), .B1(
DP_OP_153J10_122_5442_n412), .Y(n549) );
OAI22X1TS U891 ( .A0(n600), .A1(n550), .B0(n549), .B1(n543), .Y(n602) );
INVX2TS U892 ( .A(n1465), .Y(n668) );
ADDHXLTS U893 ( .A(n753), .B(n551), .CO(n605), .S(n545) );
INVX2TS U894 ( .A(n552), .Y(n796) );
INVX2TS U895 ( .A(Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[2]), .Y(
n567) );
INVX2TS U896 ( .A(Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[3]), .Y(
n565) );
INVX2TS U897 ( .A(Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[4]), .Y(
n563) );
INVX2TS U898 ( .A(Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[5]), .Y(
n561) );
CMPR32X2TS U899 ( .A(DP_OP_153J10_122_5442_n35), .B(
DP_OP_153J10_122_5442_n42), .C(n553), .CO(n737), .S(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[11]) );
CMPR32X2TS U900 ( .A(DP_OP_153J10_122_5442_n43), .B(n555), .C(n554), .CO(
n553), .S(Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[10]) );
CMPR32X2TS U901 ( .A(DP_OP_153J10_122_5442_n52), .B(n557), .C(n556), .CO(
n554), .S(Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[9]) );
CMPR32X2TS U902 ( .A(DP_OP_153J10_122_5442_n63), .B(
DP_OP_153J10_122_5442_n75), .C(n558), .CO(n556), .S(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[8]) );
CMPR32X2TS U903 ( .A(DP_OP_153J10_122_5442_n76), .B(
DP_OP_153J10_122_5442_n88), .C(n559), .CO(n558), .S(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[7]) );
CMPR32X2TS U904 ( .A(n560), .B(DP_OP_153J10_122_5442_n99), .C(
DP_OP_153J10_122_5442_n89), .CO(n559), .S(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[6]) );
CMPR32X2TS U905 ( .A(n562), .B(n561), .C(DP_OP_153J10_122_5442_n100), .CO(
n560), .S(Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[5]) );
CMPR32X2TS U906 ( .A(n564), .B(n563), .C(DP_OP_153J10_122_5442_n110), .CO(
n562), .S(Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[4]) );
CMPR32X2TS U907 ( .A(n566), .B(n565), .C(DP_OP_153J10_122_5442_n118), .CO(
n564), .S(Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[3]) );
CMPR32X2TS U908 ( .A(n568), .B(n567), .C(DP_OP_153J10_122_5442_n125), .CO(
n566), .S(Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[2]) );
CMPR32X2TS U909 ( .A(Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[1]),
.B(n570), .C(n569), .CO(n568), .S(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[1]) );
INVX4TS U910 ( .A(n572), .Y(n718) );
INVX2TS U911 ( .A(n621), .Y(n691) );
AOI22X1TS U912 ( .A0(n574), .A1(n691), .B0(n621), .B1(n729), .Y(n576) );
BUFX3TS U913 ( .A(n576), .Y(n726) );
OAI221X4TS U914 ( .A0(n621), .A1(n572), .B0(n691), .B1(n718), .C0(n726), .Y(
n724) );
INVX2TS U915 ( .A(n750), .Y(n748) );
AOI22X1TS U916 ( .A0(n572), .A1(n748), .B0(n750), .B1(n718), .Y(n713) );
OAI22X1TS U917 ( .A0(n718), .A1(n726), .B0(n724), .B1(n713), .Y(n695) );
INVX2TS U918 ( .A(n695), .Y(n693) );
INVX2TS U919 ( .A(n752), .Y(n727) );
AOI2BB2X4TS U920 ( .B0(n611), .B1(n718), .A0N(n718), .A1N(n611), .Y(n746) );
INVX2TS U921 ( .A(n730), .Y(n731) );
NAND2X2TS U922 ( .A(n572), .B(n611), .Y(n712) );
OAI22X1TS U923 ( .A0(n727), .A1(n746), .B0(n731), .B1(n712), .Y(n692) );
AOI22X1TS U924 ( .A0(n572), .A1(n711), .B0(n607), .B1(n718), .Y(n723) );
AOI22X1TS U925 ( .A0(n572), .A1(n747), .B0(n600), .B1(n718), .Y(n581) );
OAI22X1TS U926 ( .A0(n726), .A1(n723), .B0(n724), .B1(n581), .Y(n590) );
CMPR32X2TS U927 ( .A(Op_MX[2]), .B(n487), .C(n582), .CO(n573), .S(n660) );
INVX2TS U928 ( .A(n660), .Y(n775) );
AOI22X1TS U929 ( .A0(n529), .A1(n775), .B0(n660), .B1(
DP_OP_153J10_122_5442_n412), .Y(n583) );
BUFX3TS U930 ( .A(n583), .Y(n736) );
CMPR32X2TS U931 ( .A(Op_MY[3]), .B(n483), .C(n584), .CO(n580), .S(n715) );
INVX2TS U932 ( .A(n715), .Y(n716) );
AOI22X1TS U933 ( .A0(n574), .A1(n716), .B0(n715), .B1(n729), .Y(n733) );
OAI221X4TS U934 ( .A0(n660), .A1(n574), .B0(n775), .B1(n729), .C0(n736), .Y(
n734) );
CMPR32X2TS U935 ( .A(Op_MY[2]), .B(n485), .C(n585), .CO(n584), .S(n719) );
INVX2TS U936 ( .A(n719), .Y(n720) );
AOI22X1TS U937 ( .A0(n574), .A1(n720), .B0(n719), .B1(n729), .Y(n587) );
OAI22X1TS U938 ( .A0(n736), .A1(n733), .B0(n734), .B1(n587), .Y(n589) );
AOI22X1TS U939 ( .A0(n529), .A1(n731), .B0(n730), .B1(
DP_OP_153J10_122_5442_n412), .Y(n586) );
OAI32X1TS U940 ( .A0(n753), .A1(n715), .A2(DP_OP_153J10_122_5442_n412), .B0(
n586), .B1(n543), .Y(n594) );
AOI22X1TS U941 ( .A0(n574), .A1(n711), .B0(n607), .B1(n729), .Y(n597) );
OAI22X1TS U942 ( .A0(n736), .A1(n587), .B0(n734), .B1(n597), .Y(n592) );
CMPR32X2TS U943 ( .A(n590), .B(n589), .C(n588), .CO(n641), .S(n782) );
AOI22X1TS U944 ( .A0(n529), .A1(n727), .B0(n752), .B1(
DP_OP_153J10_122_5442_n412), .Y(n591) );
OAI32X1TS U945 ( .A0(n753), .A1(n730), .A2(DP_OP_153J10_122_5442_n412), .B0(
n591), .B1(n543), .Y(n777) );
OAI32X1TS U946 ( .A0(n718), .A1(n600), .A2(n726), .B0(n724), .B1(n718), .Y(
n776) );
CMPR32X2TS U947 ( .A(n594), .B(n593), .C(n592), .CO(n588), .S(n655) );
AOI22X1TS U948 ( .A0(n529), .A1(n716), .B0(n715), .B1(
DP_OP_153J10_122_5442_n412), .Y(n595) );
OAI32X1TS U949 ( .A0(n753), .A1(n719), .A2(DP_OP_153J10_122_5442_n412), .B0(
n595), .B1(n543), .Y(n599) );
AOI22X1TS U950 ( .A0(n574), .A1(n747), .B0(n600), .B1(n729), .Y(n596) );
OAI22X1TS U951 ( .A0(n736), .A1(n597), .B0(n734), .B1(n596), .Y(n598) );
ADDHXLTS U952 ( .A(n599), .B(n598), .CO(n654), .S(n800) );
OAI32X1TS U953 ( .A0(n729), .A1(n600), .A2(n736), .B0(n734), .B1(n729), .Y(
n799) );
AOI22X1TS U954 ( .A0(n529), .A1(n720), .B0(n719), .B1(
DP_OP_153J10_122_5442_n412), .Y(n601) );
OAI32X1TS U955 ( .A0(n753), .A1(n607), .A2(DP_OP_153J10_122_5442_n412), .B0(
n601), .B1(n543), .Y(n795) );
ADDHX1TS U956 ( .A(n603), .B(n602), .CO(n793), .S(n1465) );
INVX2TS U957 ( .A(n773), .Y(n632) );
CMPR32X2TS U958 ( .A(n605), .B(n529), .C(n604), .CO(n659), .S(n552) );
INVX2TS U959 ( .A(n811), .Y(n620) );
INVX2TS U960 ( .A(n703), .Y(n754) );
INVX2TS U961 ( .A(n743), .Y(n614) );
CMPR32X2TS U962 ( .A(n608), .B(n607), .C(n606), .CO(n656), .S(n548) );
INVX2TS U963 ( .A(n812), .Y(n616) );
INVX2TS U964 ( .A(n609), .Y(n770) );
INVX2TS U965 ( .A(n612), .Y(n771) );
INVX2TS U966 ( .A(n615), .Y(n759) );
NOR2X1TS U967 ( .A(n771), .B(n759), .Y(n625) );
CMPR32X2TS U968 ( .A(n617), .B(n730), .C(n616), .CO(n613), .S(n618) );
INVX2TS U969 ( .A(n618), .Y(n790) );
INVX2TS U970 ( .A(Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[11]),
.Y(n628) );
INVX2TS U971 ( .A(n709), .Y(n755) );
CMPR32X2TS U972 ( .A(n622), .B(n621), .C(n620), .CO(n631), .S(n623) );
INVX2TS U973 ( .A(n623), .Y(n789) );
CMPR32X2TS U974 ( .A(n626), .B(n625), .C(n624), .CO(
DP_OP_153J10_122_5442_n29), .S(DP_OP_153J10_122_5442_n30) );
CMPR32X2TS U975 ( .A(n629), .B(n628), .C(n627), .CO(n624), .S(
DP_OP_153J10_122_5442_n40) );
CMPR32X2TS U976 ( .A(DP_OP_153J10_122_5442_n364), .B(
DP_OP_153J10_122_5442_n368), .C(n630), .CO(n689), .S(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[9]) );
INVX2TS U977 ( .A(n708), .Y(n760) );
INVX2TS U978 ( .A(Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[9]), .Y(
n634) );
CMPR32X2TS U979 ( .A(n635), .B(n634), .C(n633), .CO(
DP_OP_153J10_122_5442_n59), .S(DP_OP_153J10_122_5442_n60) );
CMPR32X2TS U980 ( .A(n637), .B(n574), .C(n636), .CO(n622), .S(n638) );
INVX2TS U981 ( .A(n638), .Y(n757) );
CMPR32X2TS U982 ( .A(DP_OP_153J10_122_5442_n374), .B(
DP_OP_153J10_122_5442_n376), .C(n639), .CO(n690), .S(n1449) );
INVX2TS U983 ( .A(n1449), .Y(n649) );
CMPR32X2TS U984 ( .A(DP_OP_153J10_122_5442_n377), .B(n641), .C(n640), .CO(
n639), .S(n1458) );
INVX2TS U985 ( .A(n1458), .Y(n779) );
CMPR32X2TS U986 ( .A(n643), .B(n715), .C(n642), .CO(n617), .S(n644) );
INVX2TS U987 ( .A(n644), .Y(n784) );
NOR2X1TS U988 ( .A(n784), .B(n757), .Y(n778) );
CMPR32X2TS U989 ( .A(n647), .B(n646), .C(n645), .CO(
DP_OP_153J10_122_5442_n70), .S(DP_OP_153J10_122_5442_n71) );
ADDHXLTS U990 ( .A(n649), .B(n648), .CO(n646), .S(n650) );
CMPR32X2TS U991 ( .A(n652), .B(n651), .C(n650), .CO(
DP_OP_153J10_122_5442_n83), .S(DP_OP_153J10_122_5442_n84) );
CMPR32X2TS U992 ( .A(n655), .B(n654), .C(n653), .CO(n780), .S(n1461) );
INVX2TS U993 ( .A(n1461), .Y(n788) );
CMPR32X2TS U994 ( .A(n657), .B(n719), .C(n656), .CO(n642), .S(n658) );
INVX2TS U995 ( .A(n658), .Y(n756) );
CMPR32X2TS U996 ( .A(n661), .B(n660), .C(n659), .CO(n636), .S(n662) );
INVX2TS U997 ( .A(n662), .Y(n783) );
CMPR32X2TS U998 ( .A(n664), .B(n663), .C(DP_OP_153J10_122_5442_n111), .CO(
DP_OP_153J10_122_5442_n104), .S(DP_OP_153J10_122_5442_n105) );
CMPR32X2TS U999 ( .A(n666), .B(n665), .C(DP_OP_153J10_122_5442_n123), .CO(
DP_OP_153J10_122_5442_n119), .S(DP_OP_153J10_122_5442_n120) );
CMPR32X2TS U1000 ( .A(n669), .B(n668), .C(n667), .CO(
DP_OP_153J10_122_5442_n128), .S(n569) );
CMPR32X2TS U1001 ( .A(DP_OP_153J10_122_5442_n249), .B(
DP_OP_153J10_122_5442_n251), .C(n670), .CO(n541), .S(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[8]) );
CMPR32X2TS U1002 ( .A(DP_OP_153J10_122_5442_n252), .B(
DP_OP_153J10_122_5442_n256), .C(n671), .CO(n670), .S(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[7]) );
CMPR32X2TS U1003 ( .A(DP_OP_153J10_122_5442_n257), .B(
DP_OP_153J10_122_5442_n263), .C(n672), .CO(n671), .S(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[6]) );
CMPR32X2TS U1004 ( .A(n675), .B(n674), .C(n673), .CO(
DP_OP_153J10_122_5442_n253), .S(DP_OP_153J10_122_5442_n254) );
NOR2X1TS U1005 ( .A(n812), .B(n680), .Y(n676) );
CMPR32X2TS U1006 ( .A(n678), .B(n677), .C(n676), .CO(
DP_OP_153J10_122_5442_n258), .S(DP_OP_153J10_122_5442_n259) );
ADDHXLTS U1007 ( .A(n682), .B(n681), .CO(n805), .S(n534) );
CMPR32X2TS U1008 ( .A(n685), .B(n684), .C(n683), .CO(
DP_OP_153J10_122_5442_n265), .S(DP_OP_153J10_122_5442_n266) );
CMPR32X2TS U1009 ( .A(n688), .B(n687), .C(n686), .CO(
DP_OP_153J10_122_5442_n274), .S(n533) );
CMPR32X2TS U1010 ( .A(DP_OP_153J10_122_5442_n361), .B(
DP_OP_153J10_122_5442_n363), .C(n689), .CO(n697), .S(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[10]) );
CMPR32X2TS U1011 ( .A(DP_OP_153J10_122_5442_n369), .B(
DP_OP_153J10_122_5442_n373), .C(n690), .CO(n630), .S(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[8]) );
OAI22X1TS U1012 ( .A0(n748), .A1(n746), .B0(n727), .B1(n712), .Y(n696) );
OAI21X1TS U1013 ( .A0(n729), .A1(n691), .B0(n572), .Y(n694) );
CMPR32X2TS U1014 ( .A(n693), .B(n692), .C(DP_OP_153J10_122_5442_n359), .CO(
n707), .S(n698) );
CMPR32X2TS U1015 ( .A(n696), .B(n695), .C(n694), .CO(n702), .S(n706) );
CMPR32X2TS U1016 ( .A(DP_OP_153J10_122_5442_n360), .B(n698), .C(n697), .CO(
n705), .S(Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[11]) );
OAI31X1TS U1017 ( .A0(n748), .A1(n700), .A2(n712), .B0(n699), .Y(n701) );
XNOR2X2TS U1018 ( .A(n702), .B(n701), .Y(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[13]) );
NAND2X1TS U1019 ( .A(n709), .B(n703), .Y(n704) );
XNOR2X1TS U1020 ( .A(Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[13]),
.B(n704), .Y(DP_OP_153J10_122_5442_n25) );
CMPR32X2TS U1021 ( .A(n707), .B(n706), .C(n705), .CO(n700), .S(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[12]) );
NAND2X1TS U1022 ( .A(n709), .B(n708), .Y(n710) );
XNOR2X1TS U1023 ( .A(Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[12]),
.B(n710), .Y(DP_OP_153J10_122_5442_n32) );
OAI22X1TS U1024 ( .A0(n716), .A1(n746), .B0(n720), .B1(n712), .Y(
DP_OP_153J10_122_5442_n365) );
OAI22X1TS U1025 ( .A0(n720), .A1(n746), .B0(n711), .B1(n712), .Y(
DP_OP_153J10_122_5442_n370) );
OAI22X1TS U1026 ( .A0(n731), .A1(n746), .B0(n716), .B1(n712), .Y(
DP_OP_153J10_122_5442_n392) );
OAI22X1TS U1027 ( .A0(n747), .A1(n712), .B0(n711), .B1(n746), .Y(
DP_OP_153J10_122_5442_n393) );
AOI22X1TS U1028 ( .A0(n572), .A1(n727), .B0(n752), .B1(n718), .Y(n714) );
OAI22X1TS U1029 ( .A0(n726), .A1(n713), .B0(n724), .B1(n714), .Y(
DP_OP_153J10_122_5442_n396) );
AOI22X1TS U1030 ( .A0(n572), .A1(n731), .B0(n730), .B1(n718), .Y(n717) );
OAI22X1TS U1031 ( .A0(n726), .A1(n714), .B0(n724), .B1(n717), .Y(
DP_OP_153J10_122_5442_n397) );
AOI22X1TS U1032 ( .A0(n572), .A1(n716), .B0(n715), .B1(n718), .Y(n722) );
OAI22X1TS U1033 ( .A0(n726), .A1(n717), .B0(n724), .B1(n722), .Y(
DP_OP_153J10_122_5442_n398) );
AOI22X1TS U1034 ( .A0(n572), .A1(n720), .B0(n719), .B1(n718), .Y(n725) );
OAI22X1TS U1035 ( .A0(n726), .A1(n722), .B0(n724), .B1(n725), .Y(
DP_OP_153J10_122_5442_n399) );
OAI22X1TS U1036 ( .A0(n726), .A1(n725), .B0(n724), .B1(n723), .Y(
DP_OP_153J10_122_5442_n400) );
AOI22X1TS U1037 ( .A0(n574), .A1(n748), .B0(n750), .B1(n729), .Y(n728) );
OAI22X1TS U1038 ( .A0(n729), .A1(n736), .B0(n734), .B1(n728), .Y(
DP_OP_153J10_122_5442_n404) );
AOI22X1TS U1039 ( .A0(n574), .A1(n727), .B0(n752), .B1(n729), .Y(n732) );
OAI22X1TS U1040 ( .A0(n736), .A1(n728), .B0(n734), .B1(n732), .Y(
DP_OP_153J10_122_5442_n405) );
AOI22X1TS U1041 ( .A0(n574), .A1(n731), .B0(n730), .B1(n729), .Y(n735) );
OAI22X1TS U1042 ( .A0(n736), .A1(n732), .B0(n734), .B1(n735), .Y(
DP_OP_153J10_122_5442_n406) );
OAI22X1TS U1043 ( .A0(n736), .A1(n735), .B0(n734), .B1(n733), .Y(
DP_OP_153J10_122_5442_n407) );
AOI21X1TS U1044 ( .A0(n750), .A1(n543), .B0(DP_OP_153J10_122_5442_n412), .Y(
DP_OP_153J10_122_5442_n413) );
CMPR32X2TS U1045 ( .A(DP_OP_153J10_122_5442_n34), .B(
DP_OP_153J10_122_5442_n28), .C(n737), .CO(n740), .S(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[12]) );
OAI21X1TS U1046 ( .A0(n755), .A1(n754), .B0(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[13]), .Y(n739) );
NOR2X1TS U1047 ( .A(n755), .B(n771), .Y(n738) );
CMPR32X2TS U1048 ( .A(n739), .B(n738), .C(DP_OP_153J10_122_5442_n21), .CO(
n745), .S(n742) );
CMPR32X2TS U1049 ( .A(DP_OP_153J10_122_5442_n27), .B(
DP_OP_153J10_122_5442_n23), .C(n740), .CO(n741), .S(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[13]) );
XNOR2X1TS U1050 ( .A(n745), .B(n744), .Y(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[15]) );
CMPR32X2TS U1051 ( .A(n742), .B(DP_OP_153J10_122_5442_n22), .C(n741), .CO(
n744), .S(Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[14]) );
NOR2X1TS U1052 ( .A(n745), .B(n744), .Y(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[16]) );
INVX2TS U1053 ( .A(Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[10]),
.Y(DP_OP_153J10_122_5442_n133) );
NOR2X1TS U1054 ( .A(n754), .B(n758), .Y(DP_OP_153J10_122_5442_n159) );
NOR2X1TS U1055 ( .A(n754), .B(n756), .Y(DP_OP_153J10_122_5442_n157) );
NOR2X1TS U1056 ( .A(n755), .B(n761), .Y(DP_OP_153J10_122_5442_n200) );
NOR2X1TS U1057 ( .A(n760), .B(n797), .Y(DP_OP_153J10_122_5442_n166) );
OAI21X1TS U1058 ( .A0(n755), .A1(n760), .B0(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[12]), .Y(
DP_OP_153J10_122_5442_n31) );
NOR2X1TS U1059 ( .A(n790), .B(n796), .Y(DP_OP_153J10_122_5442_n195) );
NOR2X1TS U1060 ( .A(n770), .B(n761), .Y(DP_OP_153J10_122_5442_n201) );
NOR2X1TS U1061 ( .A(n759), .B(n796), .Y(DP_OP_153J10_122_5442_n194) );
NOR2X1TS U1062 ( .A(n760), .B(n758), .Y(DP_OP_153J10_122_5442_n167) );
NOR2X1TS U1063 ( .A(n797), .B(n789), .Y(DP_OP_153J10_122_5442_n174) );
NOR2X1TS U1064 ( .A(n756), .B(n789), .Y(DP_OP_153J10_122_5442_n173) );
NOR2X1TS U1065 ( .A(n770), .B(n783), .Y(DP_OP_153J10_122_5442_n185) );
NOR2X1TS U1066 ( .A(n760), .B(n756), .Y(DP_OP_153J10_122_5442_n165) );
NOR2X1TS U1067 ( .A(n747), .B(n746), .Y(DP_OP_153J10_122_5442_n394) );
NOR2X1TS U1068 ( .A(n790), .B(n761), .Y(DP_OP_153J10_122_5442_n203) );
NOR2X1TS U1069 ( .A(n758), .B(n789), .Y(DP_OP_153J10_122_5442_n175) );
NOR2X1TS U1070 ( .A(n755), .B(n796), .Y(DP_OP_153J10_122_5442_n192) );
NOR2X1TS U1071 ( .A(n759), .B(n783), .Y(DP_OP_153J10_122_5442_n186) );
NOR2X1TS U1072 ( .A(n770), .B(n757), .Y(DP_OP_153J10_122_5442_n177) );
NOR2X1TS U1073 ( .A(n755), .B(n783), .Y(DP_OP_153J10_122_5442_n184) );
INVX2TS U1074 ( .A(Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[1]), .Y(
DP_OP_153J10_122_5442_n234) );
NOR2X1TS U1075 ( .A(n754), .B(n759), .Y(DP_OP_153J10_122_5442_n154) );
INVX2TS U1076 ( .A(DP_OP_153J10_122_5442_n370), .Y(
DP_OP_153J10_122_5442_n371) );
NOR2X1TS U1077 ( .A(n771), .B(n756), .Y(DP_OP_153J10_122_5442_n149) );
AOI22X1TS U1078 ( .A0(n750), .A1(DP_OP_153J10_122_5442_n412), .B0(n529),
.B1(n748), .Y(n751) );
OAI32X1TS U1079 ( .A0(n753), .A1(n752), .A2(DP_OP_153J10_122_5442_n412),
.B0(n751), .B1(n543), .Y(DP_OP_153J10_122_5442_n414) );
NOR2X1TS U1080 ( .A(n770), .B(n789), .Y(DP_OP_153J10_122_5442_n169) );
NOR2X1TS U1081 ( .A(n797), .B(n757), .Y(DP_OP_153J10_122_5442_n182) );
NOR2X1TS U1082 ( .A(n784), .B(n796), .Y(DP_OP_153J10_122_5442_n196) );
NOR2X1TS U1083 ( .A(n756), .B(n761), .Y(DP_OP_153J10_122_5442_n205) );
NOR2X1TS U1084 ( .A(n758), .B(n783), .Y(DP_OP_153J10_122_5442_n191) );
INVX2TS U1085 ( .A(Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[6]), .Y(
DP_OP_153J10_122_5442_n229) );
NOR2X1TS U1086 ( .A(n760), .B(n770), .Y(DP_OP_153J10_122_5442_n161) );
INVX2TS U1087 ( .A(DP_OP_153J10_122_5442_n365), .Y(
DP_OP_153J10_122_5442_n366) );
NOR2X1TS U1088 ( .A(n758), .B(n757), .Y(DP_OP_153J10_122_5442_n183) );
NOR2X1TS U1089 ( .A(n760), .B(n759), .Y(DP_OP_153J10_122_5442_n162) );
NOR2X1TS U1090 ( .A(n784), .B(n761), .Y(DP_OP_153J10_122_5442_n204) );
NOR2X1TS U1091 ( .A(n771), .B(n784), .Y(DP_OP_153J10_122_5442_n148) );
INVX2TS U1092 ( .A(Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[7]), .Y(
DP_OP_153J10_122_5442_n228) );
INVX2TS U1093 ( .A(Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[8]), .Y(
DP_OP_153J10_122_5442_n227) );
NOR2X1TS U1094 ( .A(n812), .B(n762), .Y(DP_OP_153J10_122_5442_n305) );
NOR2X1TS U1095 ( .A(n811), .B(n763), .Y(DP_OP_153J10_122_5442_n290) );
NOR2X1TS U1096 ( .A(n772), .B(n762), .Y(DP_OP_153J10_122_5442_n306) );
NOR2X1TS U1097 ( .A(n763), .B(n769), .Y(DP_OP_153J10_122_5442_n296) );
NOR2X1TS U1098 ( .A(n811), .B(n765), .Y(DP_OP_153J10_122_5442_n289) );
CMPR32X2TS U1099 ( .A(n768), .B(n767), .C(n766), .CO(n1470), .S(n1466) );
INVX2TS U1100 ( .A(n1470), .Y(DP_OP_153J10_122_5442_n224) );
NOR2X1TS U1101 ( .A(n812), .B(n769), .Y(DP_OP_153J10_122_5442_n293) );
NOR2X1TS U1102 ( .A(n811), .B(n772), .Y(DP_OP_153J10_122_5442_n288) );
NOR2X1TS U1103 ( .A(n771), .B(n770), .Y(DP_OP_153J10_122_5442_n145) );
NOR2X1TS U1104 ( .A(n773), .B(n772), .Y(DP_OP_153J10_122_5442_n282) );
OAI21X1TS U1105 ( .A0(DP_OP_153J10_122_5442_n412), .A1(n775), .B0(n574), .Y(
DP_OP_153J10_122_5442_n403) );
ADDHXLTS U1106 ( .A(n777), .B(n776), .CO(DP_OP_153J10_122_5442_n380), .S(
n781) );
CMPR32X2TS U1107 ( .A(n782), .B(n781), .C(n780), .CO(n640), .S(n1460) );
INVX2TS U1108 ( .A(n1460), .Y(n786) );
ADDHXLTS U1109 ( .A(n786), .B(n785), .CO(DP_OP_153J10_122_5442_n106), .S(
DP_OP_153J10_122_5442_n107) );
ADDHXLTS U1110 ( .A(n788), .B(n787), .CO(n664), .S(
DP_OP_153J10_122_5442_n115) );
INVX2TS U1111 ( .A(Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[8]),
.Y(n792) );
ADDHXLTS U1112 ( .A(n792), .B(n791), .CO(DP_OP_153J10_122_5442_n72), .S(
DP_OP_153J10_122_5442_n73) );
CMPR32X2TS U1113 ( .A(n795), .B(n794), .C(n793), .CO(n798), .S(n1463) );
INVX2TS U1114 ( .A(n1463), .Y(n802) );
CMPR32X2TS U1115 ( .A(n800), .B(n799), .C(n798), .CO(n653), .S(n1462) );
INVX2TS U1116 ( .A(n1462), .Y(n804) );
ADDHXLTS U1117 ( .A(n802), .B(n801), .CO(n803), .S(
DP_OP_153J10_122_5442_n127) );
ADDHXLTS U1118 ( .A(n804), .B(n803), .CO(DP_OP_153J10_122_5442_n121), .S(
DP_OP_153J10_122_5442_n122) );
ADDHXLTS U1119 ( .A(n806), .B(n805), .CO(n683), .S(
DP_OP_153J10_122_5442_n273) );
ADDHXLTS U1120 ( .A(n808), .B(n807), .CO(n678), .S(
DP_OP_153J10_122_5442_n268) );
ADDHXLTS U1121 ( .A(n810), .B(n809), .CO(n673), .S(
DP_OP_153J10_122_5442_n261) );
NOR2X1TS U1122 ( .A(n812), .B(n811), .Y(DP_OP_153J10_122_5442_n287) );
CMPR32X2TS U1123 ( .A(DP_OP_154J10_123_2038_n330), .B(n814), .C(n813), .CO(
n938), .S(n1217) );
INVX2TS U1124 ( .A(n1217), .Y(n829) );
CMPR32X2TS U1125 ( .A(n817), .B(n816), .C(n815), .CO(n813), .S(n1211) );
INVX2TS U1126 ( .A(n1211), .Y(n916) );
INVX2TS U1127 ( .A(n483), .Y(n913) );
CMPR32X2TS U1128 ( .A(n820), .B(n819), .C(n818), .CO(n824), .S(n907) );
NOR2X1TS U1129 ( .A(n405), .B(n420), .Y(n1126) );
NOR2X1TS U1130 ( .A(n403), .B(n418), .Y(n1125) );
ADDHXLTS U1131 ( .A(n822), .B(n821), .CO(n818), .S(n891) );
INVX2TS U1132 ( .A(n1573), .Y(n827) );
CMPR32X2TS U1133 ( .A(DP_OP_154J10_123_2038_n239), .B(n824), .C(n823), .CO(
n890), .S(n1573) );
INVX2TS U1134 ( .A(n1569), .Y(n825) );
CMPR32X2TS U1135 ( .A(n826), .B(n825), .C(DP_OP_154J10_123_2038_n63), .CO(
DP_OP_154J10_123_2038_n59), .S(DP_OP_154J10_123_2038_n60) );
CMPR32X2TS U1136 ( .A(n829), .B(n828), .C(n827), .CO(n826), .S(
DP_OP_154J10_123_2038_n67) );
CMPR32X2TS U1137 ( .A(n832), .B(n831), .C(n830), .CO(
DP_OP_154J10_123_2038_n221), .S(DP_OP_154J10_123_2038_n222) );
CMPR32X2TS U1138 ( .A(n835), .B(n834), .C(n833), .CO(
DP_OP_154J10_123_2038_n226), .S(DP_OP_154J10_123_2038_n227) );
NOR2X1TS U1139 ( .A(n402), .B(n488), .Y(n837) );
CMPR32X2TS U1140 ( .A(n838), .B(n837), .C(n836), .CO(
DP_OP_154J10_123_2038_n233), .S(DP_OP_154J10_123_2038_n234) );
ADDHXLTS U1141 ( .A(n840), .B(n839), .CO(DP_OP_154J10_123_2038_n235), .S(
DP_OP_154J10_123_2038_n236) );
CMPR32X2TS U1142 ( .A(Op_MY[20]), .B(Op_MX[20]), .C(n841), .CO(
DP_OP_154J10_123_2038_n312), .S(DP_OP_154J10_123_2038_n313) );
ADDHXLTS U1143 ( .A(Op_MY[18]), .B(Op_MX[18]), .CO(
DP_OP_154J10_123_2038_n326), .S(DP_OP_154J10_123_2038_n327) );
INVX2TS U1144 ( .A(n846), .Y(n879) );
AOI22X1TS U1145 ( .A0(n914), .A1(n879), .B0(n846), .B1(n917), .Y(n843) );
BUFX3TS U1146 ( .A(n843), .Y(n1135) );
BUFX3TS U1147 ( .A(n845), .Y(n1137) );
INVX2TS U1148 ( .A(n1141), .Y(n868) );
INVX2TS U1149 ( .A(n1137), .Y(n878) );
AOI22X1TS U1150 ( .A0(n1137), .A1(n868), .B0(n1141), .B1(n878), .Y(n918) );
OAI221X4TS U1151 ( .A0(n846), .A1(n878), .B0(n879), .B1(n1137), .C0(n1135),
.Y(n1134) );
INVX2TS U1152 ( .A(n919), .Y(n870) );
AOI22X1TS U1153 ( .A0(n1137), .A1(n870), .B0(n919), .B1(n878), .Y(n849) );
OAI22X1TS U1154 ( .A0(n1135), .A1(n918), .B0(n1134), .B1(n849), .Y(
DP_OP_154J10_123_2038_n103) );
INVX2TS U1155 ( .A(n872), .Y(n920) );
AOI22X1TS U1156 ( .A0(n1137), .A1(n872), .B0(n920), .B1(n878), .Y(n851) );
OAI22X1TS U1157 ( .A0(n851), .A1(n1134), .B0(n1135), .B1(n849), .Y(
DP_OP_154J10_123_2038_n104) );
INVX2TS U1158 ( .A(n874), .Y(n877) );
AOI22X1TS U1159 ( .A0(n1137), .A1(n874), .B0(n877), .B1(n878), .Y(n853) );
OAI22X1TS U1160 ( .A0(n851), .A1(n1135), .B0(n853), .B1(n1134), .Y(
DP_OP_154J10_123_2038_n105) );
INVX2TS U1161 ( .A(n883), .Y(n882) );
AOI22X1TS U1162 ( .A0(n1137), .A1(n883), .B0(n882), .B1(n878), .Y(n855) );
OAI22X1TS U1163 ( .A0(n853), .A1(n1135), .B0(n855), .B1(n1134), .Y(
DP_OP_154J10_123_2038_n106) );
INVX2TS U1164 ( .A(n1129), .Y(n1127) );
AOI22X1TS U1165 ( .A0(n1137), .A1(n1129), .B0(n1127), .B1(n878), .Y(n857) );
OAI22X1TS U1166 ( .A0(n855), .A1(n1135), .B0(n857), .B1(n1134), .Y(
DP_OP_154J10_123_2038_n107) );
INVX2TS U1167 ( .A(n1136), .Y(n1124) );
AOI22X1TS U1168 ( .A0(n1137), .A1(n1136), .B0(n1124), .B1(n878), .Y(n856) );
OAI22X1TS U1169 ( .A0(n857), .A1(n1135), .B0(n1134), .B1(n856), .Y(
DP_OP_154J10_123_2038_n108) );
INVX4TS U1170 ( .A(n1128), .Y(DP_OP_154J10_123_2038_n119) );
AOI22X1TS U1171 ( .A0(n914), .A1(n1141), .B0(n868), .B1(n917), .Y(n862) );
INVX2TS U1172 ( .A(n861), .Y(n915) );
AOI22X1TS U1173 ( .A0(n1128), .A1(n915), .B0(n861), .B1(
DP_OP_154J10_123_2038_n119), .Y(n860) );
OAI221X4TS U1174 ( .A0(n861), .A1(n914), .B0(n915), .B1(n917), .C0(n937),
.Y(n935) );
OAI22X1TS U1175 ( .A0(n862), .A1(n935), .B0(n917), .B1(n937), .Y(
DP_OP_154J10_123_2038_n111) );
AOI22X1TS U1176 ( .A0(n914), .A1(n919), .B0(n870), .B1(n917), .Y(n863) );
OAI22X1TS U1177 ( .A0(n862), .A1(n937), .B0(n863), .B1(n935), .Y(
DP_OP_154J10_123_2038_n112) );
AOI22X1TS U1178 ( .A0(n914), .A1(n920), .B0(n872), .B1(n917), .Y(n864) );
OAI22X1TS U1179 ( .A0(n863), .A1(n937), .B0(n935), .B1(n864), .Y(
DP_OP_154J10_123_2038_n113) );
AOI22X1TS U1180 ( .A0(n914), .A1(n877), .B0(n874), .B1(n917), .Y(n936) );
OAI22X1TS U1181 ( .A0(n937), .A1(n864), .B0(n935), .B1(n936), .Y(
DP_OP_154J10_123_2038_n114) );
AOI22X1TS U1182 ( .A0(n914), .A1(n882), .B0(n883), .B1(n917), .Y(n934) );
AOI22X1TS U1183 ( .A0(n914), .A1(n1127), .B0(n1129), .B1(n917), .Y(n866) );
OAI22X1TS U1184 ( .A0(n937), .A1(n934), .B0(n935), .B1(n866), .Y(
DP_OP_154J10_123_2038_n116) );
AOI22X1TS U1185 ( .A0(n914), .A1(n1124), .B0(n1136), .B1(n917), .Y(n865) );
OAI22X1TS U1186 ( .A0(n937), .A1(n866), .B0(n935), .B1(n865), .Y(
DP_OP_154J10_123_2038_n117) );
INVX2TS U1187 ( .A(n1123), .Y(n867) );
AOI21X1TS U1188 ( .A0(n868), .A1(n867), .B0(DP_OP_154J10_123_2038_n119), .Y(
DP_OP_154J10_123_2038_n120) );
AOI22X1TS U1189 ( .A0(n1141), .A1(n1128), .B0(DP_OP_154J10_123_2038_n119),
.B1(n868), .Y(n869) );
OAI32X1TS U1190 ( .A0(n1123), .A1(n870), .A2(DP_OP_154J10_123_2038_n119),
.B0(n869), .B1(n867), .Y(DP_OP_154J10_123_2038_n121) );
AOI22X1TS U1191 ( .A0(n919), .A1(n1128), .B0(DP_OP_154J10_123_2038_n119),
.B1(n870), .Y(n871) );
OAI32X1TS U1192 ( .A0(n1123), .A1(n872), .A2(DP_OP_154J10_123_2038_n119),
.B0(n871), .B1(n867), .Y(DP_OP_154J10_123_2038_n122) );
AOI22X1TS U1193 ( .A0(n872), .A1(DP_OP_154J10_123_2038_n119), .B0(n1128),
.B1(n920), .Y(n873) );
OAI32X1TS U1194 ( .A0(n1123), .A1(n874), .A2(DP_OP_154J10_123_2038_n119),
.B0(n873), .B1(n867), .Y(DP_OP_154J10_123_2038_n123) );
AOI22X1TS U1195 ( .A0(n874), .A1(DP_OP_154J10_123_2038_n119), .B0(n1128),
.B1(n877), .Y(n875) );
OAI32X1TS U1196 ( .A0(n1123), .A1(n883), .A2(DP_OP_154J10_123_2038_n119),
.B0(n875), .B1(n867), .Y(DP_OP_154J10_123_2038_n124) );
INVX2TS U1197 ( .A(n1140), .Y(n921) );
AOI22X1TS U1198 ( .A0(n921), .A1(n919), .B0(n1141), .B1(n1140), .Y(
DP_OP_154J10_123_2038_n94) );
AOI22X1TS U1199 ( .A0(n921), .A1(n877), .B0(n920), .B1(n1140), .Y(
DP_OP_154J10_123_2038_n96) );
AOI22X1TS U1200 ( .A0(n921), .A1(n882), .B0(n877), .B1(n1140), .Y(
DP_OP_154J10_123_2038_n97) );
AOI22X1TS U1201 ( .A0(n921), .A1(n1127), .B0(n882), .B1(n1140), .Y(
DP_OP_154J10_123_2038_n98) );
AOI22X1TS U1202 ( .A0(n921), .A1(n1124), .B0(n1127), .B1(n1140), .Y(
DP_OP_154J10_123_2038_n99) );
OAI21X1TS U1203 ( .A0(n917), .A1(n879), .B0(n878), .Y(
DP_OP_154J10_123_2038_n101) );
XOR2X1TS U1204 ( .A(n881), .B(n880), .Y(DP_OP_154J10_123_2038_n193) );
NOR2X1TS U1205 ( .A(n1135), .B(n1124), .Y(DP_OP_154J10_123_2038_n109) );
AOI22X1TS U1206 ( .A0(n883), .A1(DP_OP_154J10_123_2038_n119), .B0(n1128),
.B1(n882), .Y(n884) );
OAI32X1TS U1207 ( .A0(n1123), .A1(n1129), .A2(DP_OP_154J10_123_2038_n119),
.B0(n884), .B1(n867), .Y(DP_OP_154J10_123_2038_n125) );
ADDHX1TS U1208 ( .A(n886), .B(n885), .CO(n889), .S(n1205) );
INVX2TS U1209 ( .A(n1205), .Y(DP_OP_154J10_123_2038_n202) );
CMPR32X2TS U1210 ( .A(n889), .B(n888), .C(n887), .CO(n815), .S(n1214) );
INVX2TS U1211 ( .A(n1214), .Y(DP_OP_154J10_123_2038_n201) );
CMPR32X2TS U1212 ( .A(DP_OP_154J10_123_2038_n232), .B(
DP_OP_154J10_123_2038_n238), .C(n890), .CO(n896), .S(n1569) );
INVX2TS U1213 ( .A(n1454), .Y(DP_OP_154J10_123_2038_n83) );
CMPR32X2TS U1214 ( .A(n893), .B(n892), .C(n891), .CO(n905), .S(n1581) );
INVX2TS U1215 ( .A(n1581), .Y(DP_OP_154J10_123_2038_n87) );
CMPR32X2TS U1216 ( .A(DP_OP_154J10_123_2038_n311), .B(
DP_OP_154J10_123_2038_n315), .C(n894), .CO(n507), .S(n1175) );
INVX2TS U1217 ( .A(n1175), .Y(DP_OP_154J10_123_2038_n196) );
CMPR32X2TS U1218 ( .A(DP_OP_154J10_123_2038_n316), .B(
DP_OP_154J10_123_2038_n322), .C(n895), .CO(n894), .S(n1223) );
INVX2TS U1219 ( .A(n1223), .Y(DP_OP_154J10_123_2038_n197) );
CMPR32X2TS U1220 ( .A(DP_OP_154J10_123_2038_n225), .B(
DP_OP_154J10_123_2038_n231), .C(n896), .CO(n902), .S(n1454) );
INVX2TS U1221 ( .A(n1241), .Y(DP_OP_154J10_123_2038_n81) );
NOR2X1TS U1222 ( .A(n402), .B(n421), .Y(n898) );
CMPR32X2TS U1223 ( .A(DP_OP_154J10_123_2038_n217), .B(
DP_OP_154J10_123_2038_n219), .C(n897), .CO(n900), .S(n1241) );
INVX2TS U1224 ( .A(n1232), .Y(DP_OP_154J10_123_2038_n80) );
CMPR32X2TS U1225 ( .A(n899), .B(n898), .C(DP_OP_154J10_123_2038_n215), .CO(
n910), .S(n901) );
CMPR32X2TS U1226 ( .A(DP_OP_154J10_123_2038_n216), .B(n901), .C(n900), .CO(
n908), .S(n1232) );
INVX2TS U1227 ( .A(n1235), .Y(DP_OP_154J10_123_2038_n79) );
CMPR32X2TS U1228 ( .A(DP_OP_154J10_123_2038_n220), .B(
DP_OP_154J10_123_2038_n224), .C(n902), .CO(n897), .S(n1446) );
INVX2TS U1229 ( .A(n1446), .Y(DP_OP_154J10_123_2038_n82) );
INVX2TS U1230 ( .A(Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[8]), .Y(
DP_OP_154J10_123_2038_n195) );
INVX2TS U1231 ( .A(Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[9]), .Y(
DP_OP_154J10_123_2038_n194) );
NOR2X1TS U1232 ( .A(n484), .B(n417), .Y(DP_OP_154J10_123_2038_n269) );
ADDHXLTS U1233 ( .A(n904), .B(n903), .CO(DP_OP_154J10_123_2038_n240), .S(
DP_OP_154J10_123_2038_n241) );
CMPR32X2TS U1234 ( .A(n907), .B(n906), .C(n905), .CO(n823), .S(n1577) );
INVX2TS U1235 ( .A(n1577), .Y(DP_OP_154J10_123_2038_n86) );
NOR2X1TS U1236 ( .A(n913), .B(n420), .Y(DP_OP_154J10_123_2038_n274) );
CMPR32X2TS U1237 ( .A(n910), .B(n909), .C(n908), .CO(n1202), .S(n1235) );
INVX2TS U1238 ( .A(n1202), .Y(DP_OP_154J10_123_2038_n78) );
NOR2X1TS U1239 ( .A(n404), .B(n420), .Y(DP_OP_154J10_123_2038_n273) );
ADDHXLTS U1240 ( .A(n912), .B(n911), .CO(DP_OP_154J10_123_2038_n228), .S(
DP_OP_154J10_123_2038_n229) );
NOR2X1TS U1241 ( .A(n419), .B(n913), .Y(DP_OP_154J10_123_2038_n250) );
OAI21X1TS U1242 ( .A0(DP_OP_154J10_123_2038_n119), .A1(n915), .B0(n914), .Y(
DP_OP_154J10_123_2038_n110) );
NOR2X1TS U1243 ( .A(n404), .B(n422), .Y(DP_OP_154J10_123_2038_n261) );
NOR2X1TS U1244 ( .A(n404), .B(n421), .Y(DP_OP_154J10_123_2038_n255) );
ADDHXLTS U1245 ( .A(DP_OP_154J10_123_2038_n73), .B(n916), .CO(n828), .S(
DP_OP_154J10_123_2038_n72) );
OAI32X1TS U1246 ( .A0(n917), .A1(n1136), .A2(n937), .B0(n935), .B1(n917),
.Y(DP_OP_154J10_123_2038_n91) );
OAI22X1TS U1247 ( .A0(n1137), .A1(n1135), .B0(n918), .B1(n1134), .Y(n923) );
AOI22X1TS U1248 ( .A0(n921), .A1(n920), .B0(n919), .B1(n1140), .Y(n922) );
CMPR32X2TS U1249 ( .A(n923), .B(n922), .C(DP_OP_154J10_123_2038_n29), .CO(
DP_OP_154J10_123_2038_n24), .S(DP_OP_154J10_123_2038_n25) );
ADDHXLTS U1250 ( .A(n925), .B(n924), .CO(DP_OP_154J10_123_2038_n244), .S(
n906) );
NOR2X1TS U1251 ( .A(n404), .B(n488), .Y(DP_OP_154J10_123_2038_n279) );
CMPR32X2TS U1252 ( .A(n928), .B(n927), .C(n926), .CO(
DP_OP_154J10_123_2038_n324), .S(DP_OP_154J10_123_2038_n325) );
CMPR32X2TS U1253 ( .A(n931), .B(n930), .C(n929), .CO(
DP_OP_154J10_123_2038_n317), .S(DP_OP_154J10_123_2038_n318) );
ADDHXLTS U1254 ( .A(n933), .B(n932), .CO(DP_OP_154J10_123_2038_n335), .S(
n816) );
OAI22X1TS U1255 ( .A0(n937), .A1(n936), .B0(n935), .B1(n934), .Y(n940) );
CMPR32X2TS U1256 ( .A(DP_OP_154J10_123_2038_n323), .B(
DP_OP_154J10_123_2038_n329), .C(n938), .CO(n895), .S(n1220) );
INVX2TS U1257 ( .A(n1220), .Y(n939) );
ADDHXLTS U1258 ( .A(n940), .B(n939), .CO(DP_OP_154J10_123_2038_n61), .S(
DP_OP_154J10_123_2038_n62) );
NOR2X1TS U1259 ( .A(n402), .B(n422), .Y(DP_OP_154J10_123_2038_n260) );
ADDHXLTS U1260 ( .A(n942), .B(n941), .CO(DP_OP_154J10_123_2038_n331), .S(
DP_OP_154J10_123_2038_n332) );
CMPR32X2TS U1261 ( .A(DP_OP_155J10_124_2038_n330), .B(n944), .C(n943), .CO(
n1050), .S(n1190) );
INVX2TS U1262 ( .A(n1190), .Y(n959) );
CMPR32X2TS U1263 ( .A(n947), .B(n946), .C(n945), .CO(n943), .S(n1181) );
INVX2TS U1264 ( .A(n1181), .Y(n1053) );
CMPR32X2TS U1265 ( .A(n950), .B(n949), .C(n948), .CO(n954), .S(n1016) );
ADDHXLTS U1266 ( .A(n952), .B(n951), .CO(n948), .S(n1006) );
INVX2TS U1267 ( .A(n1649), .Y(n957) );
CMPR32X2TS U1268 ( .A(DP_OP_155J10_124_2038_n239), .B(n954), .C(n953), .CO(
n1012), .S(n1649) );
INVX2TS U1269 ( .A(n1648), .Y(n955) );
CMPR32X2TS U1270 ( .A(n956), .B(n955), .C(DP_OP_155J10_124_2038_n63), .CO(
DP_OP_155J10_124_2038_n59), .S(DP_OP_155J10_124_2038_n60) );
CMPR32X2TS U1271 ( .A(n959), .B(n958), .C(n957), .CO(n956), .S(
DP_OP_155J10_124_2038_n67) );
INVX2TS U1272 ( .A(n963), .Y(n1038) );
AOI22X1TS U1273 ( .A0(n1035), .A1(n1038), .B0(n963), .B1(n1039), .Y(n961) );
BUFX3TS U1274 ( .A(n961), .Y(n1041) );
INVX2TS U1275 ( .A(n985), .Y(n1100) );
INVX4TS U1276 ( .A(n1037), .Y(n1042) );
AOI22X1TS U1277 ( .A0(n1037), .A1(n1100), .B0(n985), .B1(n1042), .Y(n998) );
OAI221X4TS U1278 ( .A0(n963), .A1(n1037), .B0(n1038), .B1(n1042), .C0(n1041),
.Y(n1040) );
CMPR32X2TS U1279 ( .A(Op_MY[5]), .B(Op_MY[11]), .C(n964), .CO(n985), .S(n987) );
INVX2TS U1280 ( .A(n987), .Y(n997) );
AOI22X1TS U1281 ( .A0(n1037), .A1(n997), .B0(n987), .B1(n1042), .Y(n966) );
OAI22X1TS U1282 ( .A0(n1041), .A1(n998), .B0(n1040), .B1(n966), .Y(
DP_OP_155J10_124_2038_n103) );
CMPR32X2TS U1283 ( .A(Op_MY[4]), .B(n391), .C(n965), .CO(n964), .S(n989) );
INVX2TS U1284 ( .A(n989), .Y(n996) );
AOI22X1TS U1285 ( .A0(n1037), .A1(n996), .B0(n989), .B1(n1042), .Y(n968) );
OAI22X1TS U1286 ( .A0(n1041), .A1(n966), .B0(n1040), .B1(n968), .Y(
DP_OP_155J10_124_2038_n104) );
CMPR32X2TS U1287 ( .A(Op_MY[3]), .B(n495), .C(n967), .CO(n965), .S(n991) );
INVX2TS U1288 ( .A(n991), .Y(n995) );
AOI22X1TS U1289 ( .A0(n1037), .A1(n995), .B0(n991), .B1(n1042), .Y(n970) );
OAI22X1TS U1290 ( .A0(n1041), .A1(n968), .B0(n1040), .B1(n970), .Y(
DP_OP_155J10_124_2038_n105) );
CMPR32X2TS U1291 ( .A(Op_MY[2]), .B(n492), .C(n969), .CO(n967), .S(n1002) );
INVX2TS U1292 ( .A(n1002), .Y(n1001) );
AOI22X1TS U1293 ( .A0(n1037), .A1(n1001), .B0(n1002), .B1(n1042), .Y(n972)
);
OAI22X1TS U1294 ( .A0(n1041), .A1(n970), .B0(n1040), .B1(n972), .Y(
DP_OP_155J10_124_2038_n106) );
INVX2TS U1295 ( .A(n1092), .Y(n1090) );
AOI22X1TS U1296 ( .A0(n1037), .A1(n1090), .B0(n1092), .B1(n1042), .Y(n974)
);
OAI22X1TS U1297 ( .A0(n1041), .A1(n972), .B0(n1040), .B1(n974), .Y(
DP_OP_155J10_124_2038_n107) );
INVX2TS U1298 ( .A(n1095), .Y(n1087) );
AOI22X1TS U1299 ( .A0(n1037), .A1(n1087), .B0(n1095), .B1(n1042), .Y(n973)
);
OAI22X1TS U1300 ( .A0(n1041), .A1(n974), .B0(n1040), .B1(n973), .Y(
DP_OP_155J10_124_2038_n108) );
INVX4TS U1301 ( .A(n1091), .Y(DP_OP_155J10_124_2038_n119) );
CMPR32X2TS U1302 ( .A(Op_MX[2]), .B(n496), .C(n976), .CO(n960), .S(n978) );
INVX2TS U1303 ( .A(n978), .Y(n1036) );
AOI22X1TS U1304 ( .A0(n1091), .A1(n1036), .B0(n978), .B1(
DP_OP_155J10_124_2038_n119), .Y(n977) );
BUFX3TS U1305 ( .A(n977), .Y(n1049) );
OAI221X4TS U1306 ( .A0(n978), .A1(n1035), .B0(n1036), .B1(n1039), .C0(n1049),
.Y(n1047) );
AOI22X1TS U1307 ( .A0(n1035), .A1(n1100), .B0(n985), .B1(n1039), .Y(n979) );
OAI22X1TS U1308 ( .A0(n1039), .A1(n1049), .B0(n1047), .B1(n979), .Y(
DP_OP_155J10_124_2038_n111) );
AOI22X1TS U1309 ( .A0(n1035), .A1(n997), .B0(n987), .B1(n1039), .Y(n980) );
OAI22X1TS U1310 ( .A0(n1049), .A1(n979), .B0(n1047), .B1(n980), .Y(
DP_OP_155J10_124_2038_n112) );
AOI22X1TS U1311 ( .A0(n1035), .A1(n996), .B0(n989), .B1(n1039), .Y(n981) );
OAI22X1TS U1312 ( .A0(n1049), .A1(n980), .B0(n1047), .B1(n981), .Y(
DP_OP_155J10_124_2038_n113) );
AOI22X1TS U1313 ( .A0(n1035), .A1(n995), .B0(n991), .B1(n1039), .Y(n1048) );
OAI22X1TS U1314 ( .A0(n1049), .A1(n981), .B0(n1047), .B1(n1048), .Y(
DP_OP_155J10_124_2038_n114) );
AOI22X1TS U1315 ( .A0(n1035), .A1(n1001), .B0(n1002), .B1(n1039), .Y(n1046)
);
AOI22X1TS U1316 ( .A0(n1035), .A1(n1090), .B0(n1092), .B1(n1039), .Y(n983)
);
OAI22X1TS U1317 ( .A0(n1049), .A1(n1046), .B0(n1047), .B1(n983), .Y(
DP_OP_155J10_124_2038_n116) );
AOI22X1TS U1318 ( .A0(n1035), .A1(n1087), .B0(n1095), .B1(n1039), .Y(n982)
);
OAI22X1TS U1319 ( .A0(n1049), .A1(n983), .B0(n1047), .B1(n982), .Y(
DP_OP_155J10_124_2038_n117) );
AOI21X1TS U1320 ( .A0(n985), .A1(n984), .B0(DP_OP_155J10_124_2038_n119), .Y(
DP_OP_155J10_124_2038_n120) );
AOI22X1TS U1321 ( .A0(n985), .A1(DP_OP_155J10_124_2038_n119), .B0(n1091),
.B1(n1100), .Y(n986) );
OAI32X1TS U1322 ( .A0(n1086), .A1(n987), .A2(DP_OP_155J10_124_2038_n119),
.B0(n986), .B1(n984), .Y(DP_OP_155J10_124_2038_n121) );
AOI22X1TS U1323 ( .A0(n987), .A1(DP_OP_155J10_124_2038_n119), .B0(n1091),
.B1(n997), .Y(n988) );
OAI32X1TS U1324 ( .A0(n1086), .A1(n989), .A2(DP_OP_155J10_124_2038_n119),
.B0(n988), .B1(n984), .Y(DP_OP_155J10_124_2038_n122) );
AOI22X1TS U1325 ( .A0(n989), .A1(DP_OP_155J10_124_2038_n119), .B0(n1091),
.B1(n996), .Y(n990) );
OAI32X1TS U1326 ( .A0(n1086), .A1(n991), .A2(DP_OP_155J10_124_2038_n119),
.B0(n990), .B1(n984), .Y(DP_OP_155J10_124_2038_n123) );
AOI22X1TS U1327 ( .A0(n991), .A1(DP_OP_155J10_124_2038_n119), .B0(n1091),
.B1(n995), .Y(n992) );
OAI32X1TS U1328 ( .A0(n1086), .A1(n1002), .A2(DP_OP_155J10_124_2038_n119),
.B0(n992), .B1(n984), .Y(DP_OP_155J10_124_2038_n124) );
AOI2BB2X4TS U1329 ( .B0(n994), .B1(n1042), .A0N(n1042), .A1N(n994), .Y(n1054) );
NAND2X2TS U1330 ( .A(n1037), .B(n994), .Y(n1101) );
OAI22X1TS U1331 ( .A0(n1100), .A1(n1054), .B0(n997), .B1(n1101), .Y(
DP_OP_155J10_124_2038_n94) );
OAI22X1TS U1332 ( .A0(n996), .A1(n1054), .B0(n995), .B1(n1101), .Y(
DP_OP_155J10_124_2038_n96) );
OAI22X1TS U1333 ( .A0(n995), .A1(n1054), .B0(n1001), .B1(n1101), .Y(
DP_OP_155J10_124_2038_n97) );
OAI22X1TS U1334 ( .A0(n1001), .A1(n1054), .B0(n1090), .B1(n1101), .Y(
DP_OP_155J10_124_2038_n98) );
OAI22X1TS U1335 ( .A0(n1090), .A1(n1054), .B0(n1087), .B1(n1101), .Y(
DP_OP_155J10_124_2038_n99) );
OAI22X1TS U1336 ( .A0(n997), .A1(n1054), .B0(n996), .B1(n1101), .Y(n1000) );
OAI22X1TS U1337 ( .A0(n1042), .A1(n1041), .B0(n1040), .B1(n998), .Y(n999) );
CMPR32X2TS U1338 ( .A(n1000), .B(n999), .C(DP_OP_155J10_124_2038_n29), .CO(
DP_OP_155J10_124_2038_n24), .S(DP_OP_155J10_124_2038_n25) );
NOR2X1TS U1339 ( .A(n1041), .B(n1087), .Y(DP_OP_155J10_124_2038_n109) );
AOI22X1TS U1340 ( .A0(n1002), .A1(DP_OP_155J10_124_2038_n119), .B0(n1091),
.B1(n1001), .Y(n1003) );
OAI32X1TS U1341 ( .A0(n1086), .A1(n1092), .A2(DP_OP_155J10_124_2038_n119),
.B0(n1003), .B1(n984), .Y(DP_OP_155J10_124_2038_n125) );
INVX2TS U1342 ( .A(n1196), .Y(DP_OP_155J10_124_2038_n202) );
CMPR32X2TS U1343 ( .A(n1008), .B(n1007), .C(n1006), .CO(n1014), .S(n1651) );
INVX2TS U1344 ( .A(n1651), .Y(DP_OP_155J10_124_2038_n87) );
CMPR32X2TS U1345 ( .A(n1011), .B(n1010), .C(n1009), .CO(n945), .S(n1193) );
INVX2TS U1346 ( .A(n1193), .Y(DP_OP_155J10_124_2038_n201) );
CMPR32X2TS U1347 ( .A(DP_OP_155J10_124_2038_n232), .B(
DP_OP_155J10_124_2038_n238), .C(n1012), .CO(n1017), .S(n1648) );
INVX2TS U1348 ( .A(n1456), .Y(DP_OP_155J10_124_2038_n83) );
CMPR32X2TS U1349 ( .A(DP_OP_155J10_124_2038_n316), .B(
DP_OP_155J10_124_2038_n322), .C(n1013), .CO(n1018), .S(n1187) );
INVX2TS U1350 ( .A(n1187), .Y(DP_OP_155J10_124_2038_n197) );
CMPR32X2TS U1351 ( .A(n1016), .B(n1015), .C(n1014), .CO(n953), .S(n1650) );
INVX2TS U1352 ( .A(n1650), .Y(DP_OP_155J10_124_2038_n86) );
CMPR32X2TS U1353 ( .A(DP_OP_155J10_124_2038_n225), .B(
DP_OP_155J10_124_2038_n231), .C(n1017), .CO(n1027), .S(n1456) );
INVX2TS U1354 ( .A(n1238), .Y(DP_OP_155J10_124_2038_n81) );
CMPR32X2TS U1355 ( .A(DP_OP_155J10_124_2038_n311), .B(
DP_OP_155J10_124_2038_n315), .C(n1018), .CO(n513), .S(n1169) );
INVX2TS U1356 ( .A(n1169), .Y(DP_OP_155J10_124_2038_n196) );
CMPR32X2TS U1357 ( .A(DP_OP_155J10_124_2038_n217), .B(
DP_OP_155J10_124_2038_n219), .C(n1019), .CO(n1030), .S(n1238) );
INVX2TS U1358 ( .A(n1226), .Y(DP_OP_155J10_124_2038_n80) );
CMPR32X2TS U1359 ( .A(n1021), .B(n1020), .C(DP_OP_155J10_124_2038_n306),
.CO(n1026), .S(n1023) );
CMPR32X2TS U1360 ( .A(DP_OP_155J10_124_2038_n307), .B(n1023), .C(n1022),
.CO(n1024), .S(Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[9]) );
CMPR32X2TS U1361 ( .A(n1026), .B(n1025), .C(n1024), .CO(
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[11]), .S(n1166) );
INVX2TS U1362 ( .A(n1166), .Y(DP_OP_155J10_124_2038_n193) );
CMPR32X2TS U1363 ( .A(DP_OP_155J10_124_2038_n220), .B(
DP_OP_155J10_124_2038_n224), .C(n1027), .CO(n1019), .S(n1443) );
INVX2TS U1364 ( .A(n1443), .Y(DP_OP_155J10_124_2038_n82) );
CMPR32X2TS U1365 ( .A(n1029), .B(n1028), .C(DP_OP_155J10_124_2038_n215),
.CO(n1034), .S(n1031) );
CMPR32X2TS U1366 ( .A(DP_OP_155J10_124_2038_n216), .B(n1031), .C(n1030),
.CO(n1032), .S(n1226) );
INVX2TS U1367 ( .A(n1229), .Y(DP_OP_155J10_124_2038_n79) );
INVX2TS U1368 ( .A(Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[8]), .Y(
DP_OP_155J10_124_2038_n195) );
INVX2TS U1369 ( .A(Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[9]), .Y(
DP_OP_155J10_124_2038_n194) );
CMPR32X2TS U1370 ( .A(n1034), .B(n1033), .C(n1032), .CO(n1178), .S(n1229) );
INVX2TS U1371 ( .A(n1178), .Y(DP_OP_155J10_124_2038_n78) );
INVX2TS U1372 ( .A(Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[11]),
.Y(DP_OP_155J10_124_2038_n192) );
OAI21X1TS U1373 ( .A0(DP_OP_155J10_124_2038_n119), .A1(n1036), .B0(n1035),
.Y(DP_OP_155J10_124_2038_n110) );
OAI21X1TS U1374 ( .A0(n1039), .A1(n1038), .B0(n1037), .Y(
DP_OP_155J10_124_2038_n101) );
OAI32X1TS U1375 ( .A0(n1039), .A1(n1095), .A2(n1049), .B0(n1047), .B1(n1039),
.Y(DP_OP_155J10_124_2038_n91) );
OAI32X1TS U1376 ( .A0(n1042), .A1(n1095), .A2(n1041), .B0(n1040), .B1(n1042),
.Y(DP_OP_155J10_124_2038_n90) );
CMPR32X2TS U1377 ( .A(n1045), .B(n1044), .C(n1043), .CO(
DP_OP_155J10_124_2038_n221), .S(DP_OP_155J10_124_2038_n222) );
OAI22X1TS U1378 ( .A0(n1049), .A1(n1048), .B0(n1047), .B1(n1046), .Y(n1052)
);
CMPR32X2TS U1379 ( .A(DP_OP_155J10_124_2038_n323), .B(
DP_OP_155J10_124_2038_n329), .C(n1050), .CO(n1013), .S(n1184) );
INVX2TS U1380 ( .A(n1184), .Y(n1051) );
ADDHXLTS U1381 ( .A(DP_OP_155J10_124_2038_n73), .B(n1053), .CO(n958), .S(
DP_OP_155J10_124_2038_n72) );
CMPR32X2TS U1382 ( .A(n1057), .B(n1056), .C(n1055), .CO(
DP_OP_155J10_124_2038_n324), .S(DP_OP_155J10_124_2038_n325) );
CMPR32X2TS U1383 ( .A(n1060), .B(n1059), .C(n1058), .CO(
DP_OP_155J10_124_2038_n317), .S(DP_OP_155J10_124_2038_n318) );
CMPR32X2TS U1384 ( .A(n1063), .B(n1062), .C(n1061), .CO(
DP_OP_155J10_124_2038_n226), .S(DP_OP_155J10_124_2038_n227) );
CMPR32X2TS U1385 ( .A(n1066), .B(n1065), .C(n1064), .CO(
DP_OP_155J10_124_2038_n312), .S(DP_OP_155J10_124_2038_n313) );
ADDHXLTS U1386 ( .A(n1068), .B(n1067), .CO(DP_OP_155J10_124_2038_n244), .S(
n1015) );
CMPR32X2TS U1387 ( .A(n1071), .B(n1070), .C(n1069), .CO(
DP_OP_155J10_124_2038_n233), .S(DP_OP_155J10_124_2038_n234) );
ADDHXLTS U1388 ( .A(n1073), .B(n1072), .CO(DP_OP_155J10_124_2038_n335), .S(
n946) );
ADDHXLTS U1389 ( .A(n1075), .B(n1074), .CO(DP_OP_155J10_124_2038_n331), .S(
DP_OP_155J10_124_2038_n332) );
ADDHXLTS U1390 ( .A(n1077), .B(n1076), .CO(DP_OP_155J10_124_2038_n240), .S(
DP_OP_155J10_124_2038_n241) );
ADDHXLTS U1391 ( .A(n1079), .B(n1078), .CO(DP_OP_155J10_124_2038_n235), .S(
DP_OP_155J10_124_2038_n236) );
ADDHXLTS U1392 ( .A(n1081), .B(n1080), .CO(DP_OP_155J10_124_2038_n319), .S(
DP_OP_155J10_124_2038_n320) );
ADDHXLTS U1393 ( .A(n1083), .B(n1082), .CO(DP_OP_155J10_124_2038_n228), .S(
DP_OP_155J10_124_2038_n229) );
ADDHXLTS U1394 ( .A(n1085), .B(n1084), .CO(DP_OP_155J10_124_2038_n326), .S(
DP_OP_155J10_124_2038_n327) );
AOI21X1TS U1395 ( .A0(n1095), .A1(n1086), .B0(DP_OP_155J10_124_2038_n119),
.Y(n1118) );
NAND2X1TS U1396 ( .A(n498), .B(n499), .Y(n1120) );
NAND2X1TS U1397 ( .A(Op_MY[0]), .B(Op_MX[0]), .Y(n1464) );
INVX2TS U1398 ( .A(n1652), .Y(n1097) );
NAND2X1TS U1399 ( .A(n1091), .B(n984), .Y(n1094) );
AOI22X1TS U1400 ( .A0(n1092), .A1(DP_OP_155J10_124_2038_n119), .B0(n1091),
.B1(n1090), .Y(n1093) );
OAI22X1TS U1401 ( .A0(n1095), .A1(n1094), .B0(n1093), .B1(n984), .Y(n1096)
);
XOR2X1TS U1402 ( .A(n1098), .B(DP_OP_155J10_124_2038_n19), .Y(n1102) );
OAI31X1TS U1403 ( .A0(n1102), .A1(n1101), .A2(n1100), .B0(n1099), .Y(n1103)
);
XOR2X1TS U1404 ( .A(DP_OP_155J10_124_2038_n18), .B(n1103), .Y(n1170) );
CMPR32X2TS U1405 ( .A(DP_OP_155J10_124_2038_n20), .B(
DP_OP_155J10_124_2038_n22), .C(n1104), .CO(n1098), .S(n1188) );
CMPR32X2TS U1406 ( .A(DP_OP_155J10_124_2038_n23), .B(
DP_OP_155J10_124_2038_n27), .C(n1105), .CO(n1104), .S(n1185) );
CMPR32X2TS U1407 ( .A(DP_OP_155J10_124_2038_n28), .B(
DP_OP_155J10_124_2038_n33), .C(n1106), .CO(n1105), .S(n1191) );
CMPR32X2TS U1408 ( .A(DP_OP_155J10_124_2038_n34), .B(
DP_OP_155J10_124_2038_n39), .C(n1107), .CO(n1106), .S(n1182) );
CMPR32X2TS U1409 ( .A(DP_OP_155J10_124_2038_n40), .B(
DP_OP_155J10_124_2038_n45), .C(n1108), .CO(n1107), .S(n1194) );
CMPR32X2TS U1410 ( .A(DP_OP_155J10_124_2038_n46), .B(
DP_OP_155J10_124_2038_n51), .C(n1109), .CO(n1108), .S(n1197) );
CMPR32X2TS U1411 ( .A(DP_OP_155J10_124_2038_n52), .B(
DP_OP_155J10_124_2038_n57), .C(n1110), .CO(n1109), .S(n1200) );
INVX2TS U1412 ( .A(n1120), .Y(n1199) );
CMPR32X2TS U1413 ( .A(n1111), .B(DP_OP_155J10_124_2038_n64), .C(
DP_OP_155J10_124_2038_n58), .CO(n1110), .S(n1179) );
CMPR32X2TS U1414 ( .A(DP_OP_155J10_124_2038_n65), .B(
DP_OP_155J10_124_2038_n69), .C(n1112), .CO(n1111), .S(n1230) );
CMPR32X2TS U1415 ( .A(n1113), .B(DP_OP_155J10_124_2038_n74), .C(
DP_OP_155J10_124_2038_n70), .CO(n1112), .S(n1227) );
CMPR32X2TS U1416 ( .A(n1115), .B(n1114), .C(DP_OP_155J10_124_2038_n75), .CO(
n1113), .S(n1239) );
CMPR32X2TS U1417 ( .A(n1118), .B(n1117), .C(n1116), .CO(n1115), .S(n1444) );
CMPR32X2TS U1418 ( .A(n1120), .B(n1464), .C(n1119), .CO(n1117), .S(n1455) );
INVX2TS U1419 ( .A(n1605), .Y(DP_OP_156J10_125_3370_n98) );
ADDHX1TS U1420 ( .A(Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[8]),
.B(n1121), .CO(n1122), .S(n1605) );
INVX2TS U1421 ( .A(n1601), .Y(DP_OP_156J10_125_3370_n97) );
ADDHX1TS U1422 ( .A(Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[9]),
.B(n1122), .CO(n1165), .S(n1601) );
INVX2TS U1423 ( .A(n1597), .Y(DP_OP_156J10_125_3370_n96) );
AOI21X1TS U1424 ( .A0(n1136), .A1(n1123), .B0(DP_OP_154J10_123_2038_n119),
.Y(n1159) );
NAND2X1TS U1425 ( .A(Op_MY[18]), .B(Op_MX[18]), .Y(n1162) );
NOR2X1TS U1426 ( .A(n405), .B(n488), .Y(n1589) );
INVX2TS U1427 ( .A(n1589), .Y(n1161) );
INVX2TS U1428 ( .A(n1585), .Y(n1133) );
NAND2X1TS U1429 ( .A(n1128), .B(n867), .Y(n1131) );
AOI22X1TS U1430 ( .A0(n1129), .A1(DP_OP_154J10_123_2038_n119), .B0(n1128),
.B1(n1127), .Y(n1130) );
OAI22X1TS U1431 ( .A0(n1136), .A1(n1131), .B0(n1130), .B1(n867), .Y(n1132)
);
CMPR32X2TS U1432 ( .A(n1133), .B(n1205), .C(n1132), .CO(n1155), .S(n1157) );
OAI32X1TS U1433 ( .A0(n1137), .A1(n1136), .A2(n1135), .B0(n1134), .B1(n1137),
.Y(n1151) );
XOR2X1TS U1434 ( .A(n1138), .B(DP_OP_154J10_123_2038_n19), .Y(n1142) );
OAI31X1TS U1435 ( .A0(n1142), .A1(n1141), .A2(n1140), .B0(n1139), .Y(n1143)
);
XOR2X1TS U1436 ( .A(DP_OP_154J10_123_2038_n18), .B(n1143), .Y(n1176) );
CMPR32X2TS U1437 ( .A(DP_OP_154J10_123_2038_n22), .B(
DP_OP_154J10_123_2038_n20), .C(n1144), .CO(n1138), .S(n1224) );
CMPR32X2TS U1438 ( .A(DP_OP_154J10_123_2038_n23), .B(
DP_OP_154J10_123_2038_n27), .C(n1145), .CO(n1144), .S(n1221) );
CMPR32X2TS U1439 ( .A(DP_OP_154J10_123_2038_n28), .B(
DP_OP_154J10_123_2038_n33), .C(n1146), .CO(n1145), .S(n1218) );
CMPR32X2TS U1440 ( .A(DP_OP_154J10_123_2038_n34), .B(
DP_OP_154J10_123_2038_n39), .C(n1147), .CO(n1146), .S(n1212) );
CMPR32X2TS U1441 ( .A(DP_OP_154J10_123_2038_n40), .B(
DP_OP_154J10_123_2038_n45), .C(n1148), .CO(n1147), .S(n1215) );
CMPR32X2TS U1442 ( .A(DP_OP_154J10_123_2038_n46), .B(
DP_OP_154J10_123_2038_n51), .C(n1149), .CO(n1148), .S(n1206) );
CMPR32X2TS U1443 ( .A(DP_OP_154J10_123_2038_n52), .B(
DP_OP_154J10_123_2038_n57), .C(n1150), .CO(n1149), .S(n1209) );
INVX2TS U1444 ( .A(n1162), .Y(n1208) );
CMPR32X2TS U1445 ( .A(n1152), .B(n1151), .C(DP_OP_154J10_123_2038_n58), .CO(
n1150), .S(n1203) );
CMPR32X2TS U1446 ( .A(DP_OP_154J10_123_2038_n65), .B(
DP_OP_154J10_123_2038_n69), .C(n1153), .CO(n1152), .S(n1236) );
CMPR32X2TS U1447 ( .A(n1154), .B(DP_OP_154J10_123_2038_n74), .C(
DP_OP_154J10_123_2038_n70), .CO(n1153), .S(n1233) );
CMPR32X2TS U1448 ( .A(n1156), .B(n1155), .C(DP_OP_154J10_123_2038_n75), .CO(
n1154), .S(n1242) );
CMPR32X2TS U1449 ( .A(n1159), .B(n1158), .C(n1157), .CO(n1156), .S(n1447) );
CMPR32X2TS U1450 ( .A(n1162), .B(n1161), .C(n1160), .CO(n1158), .S(n1453) );
INVX2TS U1451 ( .A(n1516), .Y(DP_OP_156J10_125_3370_n121) );
ADDHX1TS U1452 ( .A(Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[8]), .B(
n1163), .CO(n1164), .S(n1516) );
INVX2TS U1453 ( .A(n1513), .Y(DP_OP_156J10_125_3370_n120) );
INVX2TS U1454 ( .A(DP_OP_154J10_123_2038_n193), .Y(n1172) );
ADDHX1TS U1455 ( .A(Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[9]), .B(
n1164), .CO(n1171), .S(n1513) );
INVX2TS U1456 ( .A(n1656), .Y(DP_OP_156J10_125_3370_n119) );
ADDHX1TS U1457 ( .A(n1166), .B(n1165), .CO(n1167), .S(n1597) );
XOR2X1TS U1458 ( .A(n1167), .B(
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[11]), .Y(n1593) );
INVX2TS U1459 ( .A(n1593), .Y(DP_OP_156J10_125_3370_n95) );
CMPR32X2TS U1460 ( .A(n1170), .B(n1169), .C(n1168), .CO(n1121), .S(n1609) );
INVX2TS U1461 ( .A(n1609), .Y(DP_OP_156J10_125_3370_n99) );
XOR2X1TS U1462 ( .A(n1173), .B(
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[11]), .Y(n1657) );
INVX2TS U1463 ( .A(n1657), .Y(DP_OP_156J10_125_3370_n118) );
CMPR32X2TS U1464 ( .A(n1176), .B(n1175), .C(n1174), .CO(n1163), .S(n1519) );
INVX2TS U1465 ( .A(n1519), .Y(DP_OP_156J10_125_3370_n122) );
CMPR32X2TS U1466 ( .A(n1179), .B(n1178), .C(n1177), .CO(n1198), .S(n1641) );
INVX2TS U1467 ( .A(n1641), .Y(DP_OP_156J10_125_3370_n107) );
CMPR32X2TS U1468 ( .A(n1182), .B(n1181), .C(n1180), .CO(n1189), .S(n1626) );
INVX2TS U1469 ( .A(n1626), .Y(DP_OP_156J10_125_3370_n103) );
CMPR32X2TS U1470 ( .A(n1185), .B(n1184), .C(n1183), .CO(n1186), .S(n1618) );
INVX2TS U1471 ( .A(n1618), .Y(DP_OP_156J10_125_3370_n101) );
CMPR32X2TS U1472 ( .A(n1188), .B(n1187), .C(n1186), .CO(n1168), .S(n1614) );
INVX2TS U1473 ( .A(n1614), .Y(DP_OP_156J10_125_3370_n100) );
CMPR32X2TS U1474 ( .A(n1191), .B(n1190), .C(n1189), .CO(n1183), .S(n1622) );
INVX2TS U1475 ( .A(n1622), .Y(DP_OP_156J10_125_3370_n102) );
CMPR32X2TS U1476 ( .A(n1194), .B(n1193), .C(n1192), .CO(n1180), .S(n1631) );
INVX2TS U1477 ( .A(n1631), .Y(DP_OP_156J10_125_3370_n104) );
INVX2TS U1478 ( .A(n1635), .Y(DP_OP_156J10_125_3370_n105) );
CMPR32X2TS U1479 ( .A(n1200), .B(n1199), .C(n1198), .CO(n1195), .S(n1639) );
INVX2TS U1480 ( .A(n1639), .Y(DP_OP_156J10_125_3370_n106) );
CMPR32X2TS U1481 ( .A(n1203), .B(n1202), .C(n1201), .CO(n1207), .S(n1545) );
INVX2TS U1482 ( .A(n1545), .Y(DP_OP_156J10_125_3370_n130) );
CMPR32X2TS U1483 ( .A(n1206), .B(n1205), .C(n1204), .CO(n1213), .S(n1537) );
INVX2TS U1484 ( .A(n1537), .Y(DP_OP_156J10_125_3370_n128) );
CMPR32X2TS U1485 ( .A(n1209), .B(n1208), .C(n1207), .CO(n1204), .S(n1541) );
INVX2TS U1486 ( .A(n1541), .Y(DP_OP_156J10_125_3370_n129) );
CMPR32X2TS U1487 ( .A(n1212), .B(n1211), .C(n1210), .CO(n1216), .S(n1531) );
INVX2TS U1488 ( .A(n1531), .Y(DP_OP_156J10_125_3370_n126) );
CMPR32X2TS U1489 ( .A(n1215), .B(n1214), .C(n1213), .CO(n1210), .S(n1534) );
INVX2TS U1490 ( .A(n1534), .Y(DP_OP_156J10_125_3370_n127) );
CMPR32X2TS U1491 ( .A(n1218), .B(n1217), .C(n1216), .CO(n1219), .S(n1528) );
INVX2TS U1492 ( .A(n1528), .Y(DP_OP_156J10_125_3370_n125) );
CMPR32X2TS U1493 ( .A(n1221), .B(n1220), .C(n1219), .CO(n1222), .S(n1525) );
INVX2TS U1494 ( .A(n1525), .Y(DP_OP_156J10_125_3370_n124) );
CMPR32X2TS U1495 ( .A(n1224), .B(n1223), .C(n1222), .CO(n1174), .S(n1522) );
INVX2TS U1496 ( .A(n1522), .Y(DP_OP_156J10_125_3370_n123) );
CMPR32X2TS U1497 ( .A(n1227), .B(n1226), .C(n1225), .CO(n1228), .S(n1644) );
INVX2TS U1498 ( .A(n1644), .Y(DP_OP_156J10_125_3370_n109) );
CMPR32X2TS U1499 ( .A(n1230), .B(n1229), .C(n1228), .CO(n1177), .S(n1642) );
INVX2TS U1500 ( .A(n1642), .Y(DP_OP_156J10_125_3370_n108) );
CMPR32X2TS U1501 ( .A(n1233), .B(n1232), .C(n1231), .CO(n1234), .S(n1553) );
INVX2TS U1502 ( .A(n1553), .Y(DP_OP_156J10_125_3370_n132) );
CMPR32X2TS U1503 ( .A(n1236), .B(n1235), .C(n1234), .CO(n1201), .S(n1549) );
INVX2TS U1504 ( .A(n1549), .Y(DP_OP_156J10_125_3370_n131) );
CMPR32X2TS U1505 ( .A(n1239), .B(n1238), .C(n1237), .CO(n1225), .S(n1645) );
INVX2TS U1506 ( .A(n1645), .Y(DP_OP_156J10_125_3370_n110) );
CMPR32X2TS U1507 ( .A(n1242), .B(n1241), .C(n1240), .CO(n1231), .S(n1557) );
INVX2TS U1508 ( .A(n1557), .Y(DP_OP_156J10_125_3370_n133) );
INVX2TS U1509 ( .A(FS_Module_state_reg[1]), .Y(n1249) );
NOR2X1TS U1510 ( .A(FS_Module_state_reg[2]), .B(FS_Module_state_reg[3]), .Y(
n1339) );
NAND2X1TS U1511 ( .A(n1679), .B(n1339), .Y(n1243) );
NOR2X1TS U1512 ( .A(FS_Module_state_reg[1]), .B(n1243), .Y(n1244) );
OR2X1TS U1513 ( .A(exp_oper_result[8]), .B(Exp_module_Overflow_flag_A), .Y(
overflow_flag) );
BUFX3TS U1514 ( .A(n167), .Y(n1720) );
BUFX3TS U1515 ( .A(n167), .Y(n1721) );
BUFX3TS U1516 ( .A(n1722), .Y(n1712) );
BUFX3TS U1517 ( .A(n1722), .Y(n1711) );
BUFX3TS U1518 ( .A(n1722), .Y(n1710) );
BUFX3TS U1519 ( .A(n1722), .Y(n1713) );
BUFX3TS U1520 ( .A(n1722), .Y(n1708) );
BUFX3TS U1521 ( .A(n1722), .Y(n1717) );
BUFX3TS U1522 ( .A(n1722), .Y(n1715) );
BUFX3TS U1523 ( .A(n1722), .Y(n1714) );
NOR2X1TS U1524 ( .A(n1249), .B(FS_Module_state_reg[2]), .Y(n1338) );
NOR2XLTS U1525 ( .A(FS_Module_state_reg[3]), .B(n1679), .Y(n1245) );
NAND2X1TS U1526 ( .A(n1338), .B(n1245), .Y(n1386) );
INVX2TS U1527 ( .A(n1386), .Y(n1385) );
NOR2X2TS U1528 ( .A(FS_Module_state_reg[1]), .B(n1679), .Y(n1340) );
NAND3XLTS U1529 ( .A(FS_Module_state_reg[3]), .B(n1340), .C(n1666), .Y(n1246) );
NOR2X1TS U1530 ( .A(FS_Module_state_reg[3]), .B(n1666), .Y(n1253) );
NAND2X1TS U1531 ( .A(n1340), .B(n1253), .Y(n1355) );
NOR2BX1TS U1532 ( .AN(P_Sgf[47]), .B(n1355), .Y(n1248) );
INVX2TS U1533 ( .A(n1248), .Y(n1247) );
OAI31X1TS U1534 ( .A0(n1385), .A1(n1438), .A2(n1675), .B0(n1247), .Y(n235)
);
NAND2X1TS U1535 ( .A(FS_Module_state_reg[3]), .B(n1666), .Y(n1252) );
NOR3XLTS U1536 ( .A(n1252), .B(n1249), .C(n1679), .Y(n1250) );
CLKBUFX3TS U1537 ( .A(n1250), .Y(n1665) );
XOR2X1TS U1538 ( .A(Op_MX[31]), .B(Op_MY[31]), .Y(n1318) );
NOR2XLTS U1539 ( .A(n1318), .B(underflow_flag), .Y(n1251) );
OAI32X1TS U1540 ( .A0(n1662), .A1(n1251), .A2(overflow_flag), .B0(n1665),
.B1(n1707), .Y(n168) );
NOR2X2TS U1541 ( .A(FS_Module_state_reg[0]), .B(n1252), .Y(n1342) );
AOI32X2TS U1542 ( .A0(FSM_add_overflow_flag), .A1(FS_Module_state_reg[1]),
.A2(n1342), .B0(n1344), .B1(FS_Module_state_reg[1]), .Y(n1389) );
NOR2XLTS U1543 ( .A(n1389), .B(n1678), .Y(n1255) );
AOI22X1TS U1544 ( .A0(n482), .A1(n1387), .B0(n1302), .B1(n461), .Y(n1260) );
NAND2X1TS U1545 ( .A(n1254), .B(n1389), .Y(n1257) );
NOR2XLTS U1546 ( .A(FSM_selector_C), .B(n1257), .Y(n1256) );
NOR2XLTS U1547 ( .A(n1678), .B(n1257), .Y(n1258) );
AOI22X1TS U1548 ( .A0(n1308), .A1(P_Sgf[25]), .B0(n1307), .B1(Add_result[2]),
.Y(n1259) );
OAI211XLTS U1549 ( .A0(n1306), .A1(n1688), .B0(n1260), .C0(n1259), .Y(n204)
);
AOI22X1TS U1550 ( .A0(Sgf_normalized_result[0]), .A1(n1303), .B0(n1302),
.B1(n472), .Y(n1262) );
AOI22X1TS U1551 ( .A0(n1308), .A1(P_Sgf[23]), .B0(n1307), .B1(Add_result[0]),
.Y(n1261) );
OAI211XLTS U1552 ( .A0(n1306), .A1(n1690), .B0(n1262), .C0(n1261), .Y(n202)
);
AOI22X1TS U1553 ( .A0(Sgf_normalized_result[3]), .A1(n1387), .B0(n1302),
.B1(n463), .Y(n1264) );
AOI22X1TS U1554 ( .A0(n1308), .A1(P_Sgf[26]), .B0(n1307), .B1(n461), .Y(
n1263) );
OAI211XLTS U1555 ( .A0(n1306), .A1(n1687), .B0(n1264), .C0(n1263), .Y(n205)
);
AOI22X1TS U1556 ( .A0(Sgf_normalized_result[5]), .A1(n1387), .B0(n474), .B1(
n1302), .Y(n1266) );
AOI22X1TS U1557 ( .A0(n1308), .A1(P_Sgf[28]), .B0(n1307), .B1(n462), .Y(
n1265) );
OAI211XLTS U1558 ( .A0(n1306), .A1(n1706), .B0(n1266), .C0(n1265), .Y(n207)
);
AOI22X1TS U1559 ( .A0(n490), .A1(n1387), .B0(n1302), .B1(Add_result[2]), .Y(
n1268) );
AOI22X1TS U1560 ( .A0(n1308), .A1(P_Sgf[24]), .B0(n1307), .B1(n472), .Y(
n1267) );
AOI22X1TS U1561 ( .A0(Sgf_normalized_result[4]), .A1(n1387), .B0(n1302),
.B1(n462), .Y(n1270) );
AOI22X1TS U1562 ( .A0(n1308), .A1(P_Sgf[27]), .B0(n1307), .B1(n463), .Y(
n1269) );
OAI211XLTS U1563 ( .A0(n1306), .A1(n1686), .B0(n1270), .C0(n1269), .Y(n206)
);
AOI22X1TS U1564 ( .A0(Sgf_normalized_result[17]), .A1(n1387), .B0(n480),
.B1(n1302), .Y(n1272) );
AOI22X1TS U1565 ( .A0(n469), .A1(n1307), .B0(n1308), .B1(P_Sgf[40]), .Y(
n1271) );
OAI211XLTS U1566 ( .A0(n1306), .A1(n1694), .B0(n1272), .C0(n1271), .Y(n219)
);
AOI22X1TS U1567 ( .A0(Sgf_normalized_result[7]), .A1(n1387), .B0(n475), .B1(
n1302), .Y(n1274) );
AOI22X1TS U1568 ( .A0(n464), .A1(n1307), .B0(n1308), .B1(P_Sgf[30]), .Y(
n1273) );
OAI211XLTS U1569 ( .A0(n1306), .A1(n1704), .B0(n1274), .C0(n1273), .Y(n209)
);
AOI22X1TS U1570 ( .A0(Sgf_normalized_result[21]), .A1(n1303), .B0(n473),
.B1(n1302), .Y(n1276) );
AOI22X1TS U1571 ( .A0(n471), .A1(n1307), .B0(n1308), .B1(P_Sgf[44]), .Y(
n1275) );
OAI211XLTS U1572 ( .A0(n1691), .A1(n1306), .B0(n1276), .C0(n1275), .Y(n223)
);
AOI22X1TS U1573 ( .A0(Sgf_normalized_result[19]), .A1(n1303), .B0(n481),
.B1(n1302), .Y(n1278) );
AOI22X1TS U1574 ( .A0(n470), .A1(n1307), .B0(n1308), .B1(P_Sgf[42]), .Y(
n1277) );
OAI211XLTS U1575 ( .A0(n1306), .A1(n1692), .B0(n1278), .C0(n1277), .Y(n221)
);
AOI22X1TS U1576 ( .A0(Sgf_normalized_result[9]), .A1(n1387), .B0(n476), .B1(
n1302), .Y(n1280) );
AOI22X1TS U1577 ( .A0(n465), .A1(n1307), .B0(n1308), .B1(P_Sgf[32]), .Y(
n1279) );
OAI211XLTS U1578 ( .A0(n1306), .A1(n1702), .B0(n1280), .C0(n1279), .Y(n211)
);
AOI22X1TS U1579 ( .A0(Sgf_normalized_result[11]), .A1(n1303), .B0(n477),
.B1(n1302), .Y(n1282) );
AOI22X1TS U1580 ( .A0(n466), .A1(n1307), .B0(n1308), .B1(P_Sgf[34]), .Y(
n1281) );
OAI211XLTS U1581 ( .A0(n1306), .A1(n1700), .B0(n1282), .C0(n1281), .Y(n213)
);
AOI22X1TS U1582 ( .A0(Sgf_normalized_result[15]), .A1(n1303), .B0(n479),
.B1(n1302), .Y(n1284) );
AOI22X1TS U1583 ( .A0(n468), .A1(n1307), .B0(n1308), .B1(P_Sgf[38]), .Y(
n1283) );
OAI211XLTS U1584 ( .A0(n1306), .A1(n1696), .B0(n1284), .C0(n1283), .Y(n217)
);
AOI22X1TS U1585 ( .A0(Sgf_normalized_result[13]), .A1(n1303), .B0(n478),
.B1(n1302), .Y(n1286) );
AOI22X1TS U1586 ( .A0(n467), .A1(n1307), .B0(n1308), .B1(P_Sgf[36]), .Y(
n1285) );
OAI211XLTS U1587 ( .A0(n1306), .A1(n1698), .B0(n1286), .C0(n1285), .Y(n215)
);
AOI22X1TS U1588 ( .A0(Sgf_normalized_result[10]), .A1(n1387), .B0(n466),
.B1(n1302), .Y(n1288) );
AOI22X1TS U1589 ( .A0(n476), .A1(n1307), .B0(n1308), .B1(P_Sgf[33]), .Y(
n1287) );
OAI211XLTS U1590 ( .A0(n1306), .A1(n1701), .B0(n1288), .C0(n1287), .Y(n212)
);
AOI22X1TS U1591 ( .A0(Sgf_normalized_result[6]), .A1(n1387), .B0(n464), .B1(
n1302), .Y(n1290) );
AOI22X1TS U1592 ( .A0(n474), .A1(n1307), .B0(n1308), .B1(P_Sgf[29]), .Y(
n1289) );
OAI211XLTS U1593 ( .A0(n1306), .A1(n1705), .B0(n1290), .C0(n1289), .Y(n208)
);
AOI22X1TS U1594 ( .A0(Sgf_normalized_result[20]), .A1(n1303), .B0(n471),
.B1(n1302), .Y(n1292) );
AOI22X1TS U1595 ( .A0(n481), .A1(n1307), .B0(n1308), .B1(P_Sgf[43]), .Y(
n1291) );
OAI211XLTS U1596 ( .A0(n1685), .A1(n1306), .B0(n1292), .C0(n1291), .Y(n222)
);
AOI22X1TS U1597 ( .A0(Sgf_normalized_result[12]), .A1(n1303), .B0(n467),
.B1(n1302), .Y(n1294) );
AOI22X1TS U1598 ( .A0(n477), .A1(n1307), .B0(n1308), .B1(P_Sgf[35]), .Y(
n1293) );
OAI211XLTS U1599 ( .A0(n1306), .A1(n1699), .B0(n1294), .C0(n1293), .Y(n214)
);
AOI22X1TS U1600 ( .A0(Sgf_normalized_result[8]), .A1(n1387), .B0(n465), .B1(
n1302), .Y(n1296) );
AOI22X1TS U1601 ( .A0(n475), .A1(n1307), .B0(n1308), .B1(P_Sgf[31]), .Y(
n1295) );
OAI211XLTS U1602 ( .A0(n1306), .A1(n1703), .B0(n1296), .C0(n1295), .Y(n210)
);
AOI22X1TS U1603 ( .A0(Sgf_normalized_result[16]), .A1(n1303), .B0(n469),
.B1(n1302), .Y(n1299) );
AOI22X1TS U1604 ( .A0(n479), .A1(n1307), .B0(n1308), .B1(P_Sgf[39]), .Y(
n1298) );
OAI211XLTS U1605 ( .A0(n1306), .A1(n1695), .B0(n1299), .C0(n1298), .Y(n218)
);
AOI22X1TS U1606 ( .A0(Sgf_normalized_result[14]), .A1(n1303), .B0(n468),
.B1(n1302), .Y(n1301) );
AOI22X1TS U1607 ( .A0(n478), .A1(n1307), .B0(n1308), .B1(P_Sgf[37]), .Y(
n1300) );
OAI211XLTS U1608 ( .A0(n1306), .A1(n1697), .B0(n1301), .C0(n1300), .Y(n216)
);
AOI22X1TS U1609 ( .A0(Sgf_normalized_result[18]), .A1(n1303), .B0(n470),
.B1(n1302), .Y(n1305) );
AOI22X1TS U1610 ( .A0(n480), .A1(n1307), .B0(n1308), .B1(P_Sgf[41]), .Y(
n1304) );
OAI211XLTS U1611 ( .A0(n1306), .A1(n1693), .B0(n1305), .C0(n1304), .Y(n220)
);
AOI22X1TS U1612 ( .A0(FSM_selector_C), .A1(Add_result[23]), .B0(P_Sgf[46]),
.B1(n1678), .Y(n1388) );
AOI22X1TS U1613 ( .A0(Sgf_normalized_result[22]), .A1(n1387), .B0(n473),
.B1(n1307), .Y(n1310) );
NAND2X1TS U1614 ( .A(n1308), .B(P_Sgf[45]), .Y(n1309) );
OAI211XLTS U1615 ( .A0(n1389), .A1(n1388), .B0(n1310), .C0(n1309), .Y(n224)
);
INVX2TS U1616 ( .A(n1342), .Y(n1321) );
NOR4X1TS U1617 ( .A(P_Sgf[14]), .B(P_Sgf[15]), .C(P_Sgf[16]), .D(P_Sgf[17]),
.Y(n1317) );
NOR4X1TS U1618 ( .A(P_Sgf[18]), .B(P_Sgf[19]), .C(P_Sgf[20]), .D(P_Sgf[21]),
.Y(n1316) );
NOR4X1TS U1619 ( .A(P_Sgf[2]), .B(P_Sgf[3]), .C(P_Sgf[4]), .D(P_Sgf[5]), .Y(
n1314) );
NOR3XLTS U1620 ( .A(P_Sgf[22]), .B(P_Sgf[0]), .C(P_Sgf[1]), .Y(n1313) );
NOR4X1TS U1621 ( .A(P_Sgf[10]), .B(P_Sgf[11]), .C(P_Sgf[12]), .D(P_Sgf[13]),
.Y(n1312) );
AND4X1TS U1622 ( .A(n1314), .B(n1313), .C(n1312), .D(n1311), .Y(n1315) );
NAND3XLTS U1623 ( .A(n1317), .B(n1316), .C(n1315), .Y(n1320) );
MXI2X1TS U1624 ( .A(round_mode[0]), .B(round_mode[1]), .S0(n1318), .Y(n1319)
);
OAI211X1TS U1625 ( .A0(round_mode[0]), .A1(round_mode[1]), .B0(n1320), .C0(
n1319), .Y(n1335) );
OAI31X1TS U1626 ( .A0(FS_Module_state_reg[1]), .A1(n1321), .A2(n1335), .B0(
n1678), .Y(n375) );
NAND2X1TS U1627 ( .A(FS_Module_state_reg[2]), .B(FS_Module_state_reg[3]),
.Y(n1336) );
NOR3X1TS U1628 ( .A(FS_Module_state_reg[1]), .B(FS_Module_state_reg[0]), .C(
n1336), .Y(ready) );
AOI22X1TS U1629 ( .A0(DP_OP_36J10_126_4699_n33), .A1(n430), .B0(n1666), .B1(
n1679), .Y(n1323) );
INVX2TS U1630 ( .A(ready), .Y(n1322) );
OAI22X1TS U1631 ( .A0(n1323), .A1(n1353), .B0(P_Sgf[47]), .B1(n1355), .Y(
n379) );
INVX2TS U1632 ( .A(DP_OP_36J10_126_4699_n33), .Y(n1356) );
OAI21XLTS U1633 ( .A0(n1666), .A1(n1353), .B0(FS_Module_state_reg[3]), .Y(
n1324) );
OAI211XLTS U1634 ( .A0(n430), .A1(n1356), .B0(n1303), .C0(n1324), .Y(n380)
);
NOR3BX1TS U1635 ( .AN(n460), .B(FSM_selector_B[0]), .C(FSM_selector_B[1]),
.Y(n1325) );
XOR2X1TS U1636 ( .A(DP_OP_36J10_126_4699_n33), .B(n1325), .Y(
DP_OP_36J10_126_4699_n15) );
OR2X2TS U1637 ( .A(FSM_selector_B[1]), .B(n1674), .Y(n1332) );
OAI2BB1X1TS U1638 ( .A0N(n453), .A1N(n1675), .B0(n1332), .Y(n1326) );
XOR2X1TS U1639 ( .A(DP_OP_36J10_126_4699_n33), .B(n1326), .Y(
DP_OP_36J10_126_4699_n16) );
OAI2BB1X1TS U1640 ( .A0N(n454), .A1N(n1675), .B0(n1332), .Y(n1327) );
XOR2X1TS U1641 ( .A(DP_OP_36J10_126_4699_n33), .B(n1327), .Y(
DP_OP_36J10_126_4699_n17) );
OAI2BB1X1TS U1642 ( .A0N(Op_MY[27]), .A1N(n1675), .B0(n1332), .Y(n1328) );
XOR2X1TS U1643 ( .A(DP_OP_36J10_126_4699_n33), .B(n1328), .Y(
DP_OP_36J10_126_4699_n18) );
OAI2BB1X1TS U1644 ( .A0N(n459), .A1N(n1675), .B0(n1332), .Y(n1329) );
XOR2X1TS U1645 ( .A(DP_OP_36J10_126_4699_n33), .B(n1329), .Y(
DP_OP_36J10_126_4699_n19) );
OAI2BB1X1TS U1646 ( .A0N(n458), .A1N(n1675), .B0(n1332), .Y(n1330) );
XOR2X1TS U1647 ( .A(DP_OP_36J10_126_4699_n33), .B(n1330), .Y(
DP_OP_36J10_126_4699_n20) );
OAI2BB1X1TS U1648 ( .A0N(n455), .A1N(n1675), .B0(n1332), .Y(n1331) );
XOR2X1TS U1649 ( .A(DP_OP_36J10_126_4699_n33), .B(n1331), .Y(
DP_OP_36J10_126_4699_n21) );
NOR2XLTS U1650 ( .A(FSM_selector_B[1]), .B(Op_MY[23]), .Y(n1333) );
OAI21XLTS U1651 ( .A0(FSM_selector_B[0]), .A1(n1333), .B0(n1332), .Y(n1334)
);
XOR2X1TS U1652 ( .A(DP_OP_36J10_126_4699_n33), .B(n1334), .Y(
DP_OP_36J10_126_4699_n22) );
AOI22X1TS U1653 ( .A0(n1340), .A1(n1336), .B0(n1342), .B1(n1335), .Y(n1337)
);
OAI2BB1X1TS U1654 ( .A0N(n1338), .A1N(n1679), .B0(n1337), .Y(n378) );
AO22XLTS U1655 ( .A0(Data_MY[26]), .A1(n1363), .B0(n1352), .B1(n459), .Y(
n338) );
AO22XLTS U1656 ( .A0(Data_MY[25]), .A1(n1363), .B0(n1352), .B1(n458), .Y(
n337) );
AO22XLTS U1657 ( .A0(Data_MY[30]), .A1(n1363), .B0(n1352), .B1(n460), .Y(
n342) );
AO22XLTS U1658 ( .A0(Data_MY[24]), .A1(n1363), .B0(n1352), .B1(n455), .Y(
n336) );
AO22XLTS U1659 ( .A0(Data_MY[29]), .A1(n1363), .B0(n1352), .B1(n453), .Y(
n341) );
AO22XLTS U1660 ( .A0(Data_MY[28]), .A1(n1341), .B0(n1352), .B1(n454), .Y(
n340) );
BUFX3TS U1661 ( .A(n1352), .Y(n1359) );
MX2X1TS U1662 ( .A(Op_MY[23]), .B(Data_MY[23]), .S0(n1363), .Y(n335) );
NAND2X1TS U1663 ( .A(n1386), .B(n1681), .Y(n376) );
NOR2BX1TS U1664 ( .AN(exp_oper_result[8]), .B(n1681), .Y(S_Oper_A_exp[8]) );
BUFX3TS U1665 ( .A(n1660), .Y(n1654) );
MX2X1TS U1666 ( .A(Exp_module_Data_S[7]), .B(exp_oper_result[7]), .S0(n1345),
.Y(n227) );
MX2X1TS U1667 ( .A(n456), .B(exp_oper_result[7]), .S0(FSM_selector_A), .Y(
S_Oper_A_exp[7]) );
MX2X1TS U1668 ( .A(Exp_module_Data_S[6]), .B(exp_oper_result[6]), .S0(n1345),
.Y(n228) );
MX2X1TS U1669 ( .A(n457), .B(exp_oper_result[6]), .S0(FSM_selector_A), .Y(
S_Oper_A_exp[6]) );
MX2X1TS U1670 ( .A(Exp_module_Data_S[5]), .B(exp_oper_result[5]), .S0(n1345),
.Y(n229) );
MX2X1TS U1671 ( .A(Op_MX[28]), .B(exp_oper_result[5]), .S0(FSM_selector_A),
.Y(S_Oper_A_exp[5]) );
MX2X1TS U1672 ( .A(Exp_module_Data_S[4]), .B(exp_oper_result[4]), .S0(n1345),
.Y(n230) );
MX2X1TS U1673 ( .A(Op_MX[27]), .B(exp_oper_result[4]), .S0(FSM_selector_A),
.Y(S_Oper_A_exp[4]) );
MX2X1TS U1674 ( .A(Exp_module_Data_S[3]), .B(exp_oper_result[3]), .S0(n1345),
.Y(n231) );
MX2X1TS U1675 ( .A(Op_MX[26]), .B(exp_oper_result[3]), .S0(FSM_selector_A),
.Y(S_Oper_A_exp[3]) );
MX2X1TS U1676 ( .A(Exp_module_Data_S[2]), .B(exp_oper_result[2]), .S0(n1345),
.Y(n232) );
MX2X1TS U1677 ( .A(Op_MX[25]), .B(exp_oper_result[2]), .S0(FSM_selector_A),
.Y(S_Oper_A_exp[2]) );
MX2X1TS U1678 ( .A(Exp_module_Data_S[1]), .B(exp_oper_result[1]), .S0(n1345),
.Y(n233) );
MX2X1TS U1679 ( .A(Op_MX[24]), .B(exp_oper_result[1]), .S0(FSM_selector_A),
.Y(S_Oper_A_exp[1]) );
MX2X1TS U1680 ( .A(Exp_module_Data_S[0]), .B(exp_oper_result[0]), .S0(n1345),
.Y(n234) );
MX2X1TS U1681 ( .A(Op_MX[23]), .B(exp_oper_result[0]), .S0(FSM_selector_A),
.Y(S_Oper_A_exp[0]) );
MX2X1TS U1682 ( .A(Exp_module_Data_S[8]), .B(exp_oper_result[8]), .S0(n1345),
.Y(n226) );
XNOR2X1TS U1683 ( .A(DP_OP_36J10_126_4699_n1), .B(n1356), .Y(n1347) );
CLKINVX6TS U1684 ( .A(n1660), .Y(n1661) );
MX2X1TS U1685 ( .A(n1347), .B(Exp_module_Overflow_flag_A), .S0(n1661), .Y(
n225) );
NAND4XLTS U1686 ( .A(Exp_module_Data_S[3]), .B(Exp_module_Data_S[2]), .C(
Exp_module_Data_S[1]), .D(Exp_module_Data_S[0]), .Y(n1348) );
NAND4BXLTS U1687 ( .AN(n1348), .B(Exp_module_Data_S[6]), .C(
Exp_module_Data_S[5]), .D(Exp_module_Data_S[4]), .Y(n1349) );
NAND3BXLTS U1688 ( .AN(Exp_module_Data_S[7]), .B(n1385), .C(n1349), .Y(n1350) );
OAI22X1TS U1689 ( .A0(Exp_module_Data_S[8]), .A1(n1350), .B0(n1385), .B1(
n1682), .Y(n201) );
CLKINVX6TS U1690 ( .A(n1352), .Y(n1363) );
AO22XLTS U1691 ( .A0(n1363), .A1(Data_MY[31]), .B0(n1352), .B1(Op_MY[31]),
.Y(n381) );
AOI32X1TS U1692 ( .A0(FS_Module_state_reg[1]), .A1(n1666), .A2(
FS_Module_state_reg[0]), .B0(FS_Module_state_reg[2]), .B1(n1353), .Y(
n1357) );
NAND3XLTS U1693 ( .A(n1357), .B(n1356), .C(n1355), .Y(n377) );
BUFX3TS U1694 ( .A(n1352), .Y(n1362) );
BUFX3TS U1695 ( .A(n1352), .Y(n1358) );
AO22XLTS U1696 ( .A0(n1363), .A1(Data_MX[31]), .B0(n1358), .B1(Op_MX[31]),
.Y(n343) );
BUFX3TS U1697 ( .A(n1352), .Y(n1360) );
NOR4X1TS U1698 ( .A(n459), .B(n458), .C(n460), .D(n455), .Y(n1365) );
NAND4XLTS U1699 ( .A(n1367), .B(n1366), .C(n1365), .D(n1364), .Y(n1383) );
NAND4XLTS U1700 ( .A(n1371), .B(n1370), .C(n1369), .D(n1368), .Y(n1382) );
NOR4X1TS U1701 ( .A(Op_MX[18]), .B(Op_MX[19]), .C(Op_MX[20]), .D(Op_MX[21]),
.Y(n1375) );
NAND4XLTS U1702 ( .A(n1375), .B(n1374), .C(n1373), .D(n1372), .Y(n1381) );
NAND4XLTS U1703 ( .A(n1379), .B(n1378), .C(n1377), .D(n1376), .Y(n1380) );
OAI22X1TS U1704 ( .A0(n1383), .A1(n1382), .B0(n1381), .B1(n1380), .Y(n1384)
);
AO22XLTS U1705 ( .A0(n1386), .A1(zero_flag), .B0(n1385), .B1(n1384), .Y(n311) );
AOI32X1TS U1706 ( .A0(n1389), .A1(n1254), .A2(n1388), .B0(n1684), .B1(n1303),
.Y(n310) );
AOI2BB2XLTS U1707 ( .B0(n1438), .B1(Sgf_normalized_result[0]), .A0N(
Add_result[0]), .A1N(n1428), .Y(n309) );
NOR2XLTS U1708 ( .A(n490), .B(Sgf_normalized_result[0]), .Y(n1390) );
AOI21X1TS U1709 ( .A0(Sgf_normalized_result[0]), .A1(n490), .B0(n1390), .Y(
n1391) );
AOI2BB2XLTS U1710 ( .B0(n1438), .B1(n1391), .A0N(n472), .A1N(n1428), .Y(n308) );
OR3X1TS U1711 ( .A(n482), .B(n490), .C(Sgf_normalized_result[0]), .Y(n1393)
);
OAI21XLTS U1712 ( .A0(n490), .A1(Sgf_normalized_result[0]), .B0(n482), .Y(
n1392) );
AOI32X1TS U1713 ( .A0(n1393), .A1(n1438), .A2(n1392), .B0(n1683), .B1(n1436),
.Y(n307) );
BUFX4TS U1714 ( .A(n1436), .Y(n1433) );
NAND2X1TS U1715 ( .A(Sgf_normalized_result[3]), .B(n1393), .Y(n1395) );
OAI2BB1X1TS U1716 ( .A0N(n461), .A1N(n1433), .B0(n1394), .Y(n306) );
NAND2X1TS U1717 ( .A(n1667), .B(n1395), .Y(n1397) );
OAI21XLTS U1718 ( .A0(n1395), .A1(n1667), .B0(n1397), .Y(n1396) );
NAND2X1TS U1719 ( .A(Sgf_normalized_result[5]), .B(n1397), .Y(n1399) );
OAI2BB1X1TS U1720 ( .A0N(n462), .A1N(n1433), .B0(n1398), .Y(n304) );
AOI21X1TS U1721 ( .A0(n1668), .A1(n1399), .B0(n1401), .Y(n1400) );
NAND2X1TS U1722 ( .A(Sgf_normalized_result[7]), .B(n1401), .Y(n1403) );
OAI211XLTS U1723 ( .A0(Sgf_normalized_result[7]), .A1(n1401), .B0(n1428),
.C0(n1403), .Y(n1402) );
OAI2BB1X1TS U1724 ( .A0N(n464), .A1N(n1433), .B0(n1402), .Y(n302) );
AOI21X1TS U1725 ( .A0(n1669), .A1(n1403), .B0(n452), .Y(n1404) );
NAND2X1TS U1726 ( .A(Sgf_normalized_result[9]), .B(n452), .Y(n1406) );
OAI211XLTS U1727 ( .A0(Sgf_normalized_result[9]), .A1(n452), .B0(n1428),
.C0(n1406), .Y(n1405) );
OAI2BB1X1TS U1728 ( .A0N(n465), .A1N(n1433), .B0(n1405), .Y(n300) );
AOI21X1TS U1729 ( .A0(n1670), .A1(n1406), .B0(n1408), .Y(n1407) );
NAND2X1TS U1730 ( .A(Sgf_normalized_result[11]), .B(n1408), .Y(n1410) );
OAI211XLTS U1731 ( .A0(Sgf_normalized_result[11]), .A1(n1408), .B0(n1428),
.C0(n1410), .Y(n1409) );
OAI2BB1X1TS U1732 ( .A0N(n466), .A1N(n1433), .B0(n1409), .Y(n298) );
AOI21X1TS U1733 ( .A0(n1671), .A1(n1410), .B0(n1412), .Y(n1411) );
NAND2X1TS U1734 ( .A(Sgf_normalized_result[13]), .B(n1412), .Y(n1414) );
OAI211XLTS U1735 ( .A0(Sgf_normalized_result[13]), .A1(n1412), .B0(n1428),
.C0(n1414), .Y(n1413) );
OAI2BB1X1TS U1736 ( .A0N(n467), .A1N(n1433), .B0(n1413), .Y(n296) );
AOI21X1TS U1737 ( .A0(n1672), .A1(n1414), .B0(n1416), .Y(n1415) );
NAND2X1TS U1738 ( .A(Sgf_normalized_result[15]), .B(n1416), .Y(n1418) );
OAI2BB1X1TS U1739 ( .A0N(n468), .A1N(n1433), .B0(n1417), .Y(n294) );
AOI21X1TS U1740 ( .A0(n1673), .A1(n1418), .B0(n1420), .Y(n1419) );
NAND2X1TS U1741 ( .A(Sgf_normalized_result[17]), .B(n1420), .Y(n1422) );
OAI211XLTS U1742 ( .A0(Sgf_normalized_result[17]), .A1(n1420), .B0(n1428),
.C0(n1422), .Y(n1421) );
OAI2BB1X1TS U1743 ( .A0N(n469), .A1N(n1433), .B0(n1421), .Y(n292) );
AOI21X1TS U1744 ( .A0(n1676), .A1(n1422), .B0(n1424), .Y(n1423) );
NAND2X1TS U1745 ( .A(Sgf_normalized_result[19]), .B(n1424), .Y(n1426) );
OAI211XLTS U1746 ( .A0(Sgf_normalized_result[19]), .A1(n1424), .B0(n1428),
.C0(n1426), .Y(n1425) );
OAI2BB1X1TS U1747 ( .A0N(n470), .A1N(n1433), .B0(n1425), .Y(n290) );
AOI21X1TS U1748 ( .A0(n1677), .A1(n1426), .B0(n1429), .Y(n1427) );
NAND2X1TS U1749 ( .A(Sgf_normalized_result[21]), .B(n1429), .Y(n1431) );
OAI211XLTS U1750 ( .A0(Sgf_normalized_result[21]), .A1(n1429), .B0(n1428),
.C0(n1431), .Y(n1430) );
OAI2BB1X1TS U1751 ( .A0N(n471), .A1N(n1433), .B0(n1430), .Y(n288) );
AOI211XLTS U1752 ( .A0(n1680), .A1(n1431), .B0(n1434), .C0(n1436), .Y(n1432)
);
AO21XLTS U1753 ( .A0(n473), .A1(n1433), .B0(n1432), .Y(n287) );
AOI21X1TS U1754 ( .A0(n1434), .A1(Sgf_normalized_result[23]), .B0(n1436),
.Y(n1437) );
OAI21XLTS U1755 ( .A0(n1434), .A1(Sgf_normalized_result[23]), .B0(n1437),
.Y(n1435) );
OAI2BB1X1TS U1756 ( .A0N(Add_result[23]), .A1N(n1436), .B0(n1435), .Y(n286)
);
AOI2BB1XLTS U1757 ( .A0N(n1428), .A1N(FSM_add_overflow_flag), .B0(n1437),
.Y(n285) );
CMPR32X2TS U1758 ( .A(n1441), .B(n1440), .C(n1439), .CO(n570), .S(n1448) );
CMPR32X2TS U1759 ( .A(n1444), .B(n1443), .C(n1442), .CO(n1237), .S(n1646) );
INVX2TS U1760 ( .A(n1646), .Y(n1452) );
CMPR32X2TS U1761 ( .A(n1447), .B(n1446), .C(n1445), .CO(n1240), .S(n1561) );
INVX2TS U1762 ( .A(n1561), .Y(n1451) );
ADDHXLTS U1763 ( .A(n1449), .B(n1448), .CO(DP_OP_156J10_125_3370_n81), .S(
n1450) );
CMPR32X2TS U1764 ( .A(n1452), .B(n1451), .C(n1450), .CO(n1489), .S(n1492) );
ADDHX1TS U1765 ( .A(n1454), .B(n1453), .CO(n1445), .S(n1565) );
INVX2TS U1766 ( .A(n1565), .Y(n1459) );
ADDHX1TS U1767 ( .A(n1456), .B(n1455), .CO(n1442), .S(n1647) );
INVX2TS U1768 ( .A(n1647), .Y(n1457) );
CMPR32X2TS U1769 ( .A(n1459), .B(n1458), .C(n1457), .CO(n1491), .S(n1495) );
CMPR32X2TS U1770 ( .A(n825), .B(n1460), .C(n955), .CO(n1494), .S(n1498) );
CMPR32X2TS U1771 ( .A(n827), .B(n1461), .C(n957), .CO(n1497), .S(n1501) );
CMPR32X2TS U1772 ( .A(DP_OP_154J10_123_2038_n86), .B(n1462), .C(
DP_OP_155J10_124_2038_n86), .CO(n1500), .S(n1504) );
CMPR32X2TS U1773 ( .A(DP_OP_154J10_123_2038_n87), .B(n1463), .C(
DP_OP_155J10_124_2038_n87), .CO(n1503), .S(n1507) );
NAND2BXLTS U1774 ( .AN(n1465), .B(n1585), .Y(n1506) );
INVX2TS U1775 ( .A(n1464), .Y(n1653) );
XOR2X1TS U1776 ( .A(n1465), .B(n1585), .Y(n1508) );
ADDHXLTS U1777 ( .A(n1466), .B(DP_OP_156J10_125_3370_n31), .CO(n1467), .S(
n1472) );
XNOR2X1TS U1778 ( .A(n1468), .B(n1467), .Y(n1469) );
XOR2X1TS U1779 ( .A(n1470), .B(n1469), .Y(n1538) );
CMPR32X2TS U1780 ( .A(n1472), .B(DP_OP_156J10_125_3370_n32), .C(n1471), .CO(
n1468), .S(n1542) );
CMPR32X2TS U1781 ( .A(DP_OP_156J10_125_3370_n33), .B(
DP_OP_156J10_125_3370_n35), .C(n1473), .CO(n1471), .S(n1546) );
CMPR32X2TS U1782 ( .A(DP_OP_156J10_125_3370_n36), .B(
DP_OP_156J10_125_3370_n38), .C(n1474), .CO(n1473), .S(n1550) );
CMPR32X2TS U1783 ( .A(DP_OP_156J10_125_3370_n39), .B(
DP_OP_156J10_125_3370_n41), .C(n1475), .CO(n1474), .S(n1554) );
CMPR32X2TS U1784 ( .A(DP_OP_156J10_125_3370_n42), .B(
DP_OP_156J10_125_3370_n44), .C(n1476), .CO(n1475), .S(n1558) );
CMPR32X2TS U1785 ( .A(DP_OP_156J10_125_3370_n45), .B(
DP_OP_156J10_125_3370_n47), .C(n1477), .CO(n1476), .S(n1562) );
CMPR32X2TS U1786 ( .A(DP_OP_156J10_125_3370_n48), .B(
DP_OP_156J10_125_3370_n50), .C(n1478), .CO(n1477), .S(n1566) );
CMPR32X2TS U1787 ( .A(DP_OP_156J10_125_3370_n51), .B(
DP_OP_156J10_125_3370_n53), .C(n1479), .CO(n1478), .S(n1570) );
CMPR32X2TS U1788 ( .A(DP_OP_156J10_125_3370_n54), .B(
DP_OP_156J10_125_3370_n56), .C(n1480), .CO(n1479), .S(n1574) );
CMPR32X2TS U1789 ( .A(DP_OP_156J10_125_3370_n57), .B(
DP_OP_156J10_125_3370_n59), .C(n1481), .CO(n1480), .S(n1578) );
CMPR32X2TS U1790 ( .A(DP_OP_156J10_125_3370_n60), .B(
DP_OP_156J10_125_3370_n62), .C(n1482), .CO(n1481), .S(n1582) );
CMPR32X2TS U1791 ( .A(DP_OP_156J10_125_3370_n63), .B(
DP_OP_156J10_125_3370_n65), .C(n1483), .CO(n1482), .S(n1586) );
CMPR32X2TS U1792 ( .A(DP_OP_156J10_125_3370_n66), .B(
DP_OP_156J10_125_3370_n68), .C(n1484), .CO(n1483), .S(n1590) );
CMPR32X2TS U1793 ( .A(DP_OP_156J10_125_3370_n69), .B(
DP_OP_156J10_125_3370_n71), .C(n1485), .CO(n1484), .S(n1594) );
CMPR32X2TS U1794 ( .A(DP_OP_156J10_125_3370_n72), .B(
DP_OP_156J10_125_3370_n74), .C(n1486), .CO(n1485), .S(n1598) );
CMPR32X2TS U1795 ( .A(DP_OP_156J10_125_3370_n75), .B(
DP_OP_156J10_125_3370_n77), .C(n1487), .CO(n1486), .S(n1602) );
CMPR32X2TS U1796 ( .A(DP_OP_156J10_125_3370_n78), .B(n1489), .C(n1488), .CO(
n1487), .S(n1606) );
CMPR32X2TS U1797 ( .A(n1492), .B(n1491), .C(n1490), .CO(n1488), .S(n1610) );
CMPR32X2TS U1798 ( .A(n1495), .B(n1494), .C(n1493), .CO(n1490), .S(n1615) );
CMPR32X2TS U1799 ( .A(n1498), .B(n1497), .C(n1496), .CO(n1493), .S(n1619) );
CMPR32X2TS U1800 ( .A(n1501), .B(n1500), .C(n1499), .CO(n1496), .S(n1623) );
CMPR32X2TS U1801 ( .A(n1504), .B(n1503), .C(n1502), .CO(n1499), .S(n1627) );
CMPR32X2TS U1802 ( .A(n1507), .B(n1506), .C(n1505), .CO(n1502), .S(n1632) );
CMPR32X2TS U1803 ( .A(n1509), .B(n1097), .C(n1508), .CO(n1505), .S(n1636) );
CMPR32X2TS U1804 ( .A(n1161), .B(n1510), .C(n1464), .CO(n1509), .S(n1638) );
BUFX3TS U1805 ( .A(n1660), .Y(n1612) );
ADDHXLTS U1806 ( .A(n1513), .B(n1512), .CO(n1655), .S(n1514) );
BUFX3TS U1807 ( .A(n1660), .Y(n1643) );
ADDHXLTS U1808 ( .A(n1516), .B(n1515), .CO(n1512), .S(n1517) );
ADDHXLTS U1809 ( .A(n1519), .B(n1518), .CO(n1515), .S(n1520) );
ADDHXLTS U1810 ( .A(n1522), .B(n1521), .CO(n1518), .S(n1523) );
ADDHXLTS U1811 ( .A(n1525), .B(n1524), .CO(n1521), .S(n1526) );
ADDHXLTS U1812 ( .A(n1528), .B(n1527), .CO(n1524), .S(n1529) );
ADDHXLTS U1813 ( .A(n1531), .B(n1530), .CO(n1527), .S(n1532) );
ADDHXLTS U1814 ( .A(n1534), .B(n1533), .CO(n1530), .S(n1535) );
CMPR32X2TS U1815 ( .A(n1538), .B(n1537), .C(n1536), .CO(n1533), .S(n1539) );
CMPR32X2TS U1816 ( .A(n1542), .B(n1541), .C(n1540), .CO(n1536), .S(n1543) );
CMPR32X2TS U1817 ( .A(n1546), .B(n1545), .C(n1544), .CO(n1540), .S(n1547) );
CMPR32X2TS U1818 ( .A(n1550), .B(n1549), .C(n1548), .CO(n1544), .S(n1551) );
CMPR32X2TS U1819 ( .A(n1554), .B(n1553), .C(n1552), .CO(n1548), .S(n1555) );
CMPR32X2TS U1820 ( .A(n1558), .B(n1557), .C(n1556), .CO(n1552), .S(n1559) );
CMPR32X2TS U1821 ( .A(n1562), .B(n1561), .C(n1560), .CO(n1556), .S(n1563) );
CMPR32X2TS U1822 ( .A(n1566), .B(n1565), .C(n1564), .CO(n1560), .S(n1567) );
CMPR32X2TS U1823 ( .A(n1570), .B(n1569), .C(n1568), .CO(n1564), .S(n1571) );
CMPR32X2TS U1824 ( .A(n1574), .B(n1573), .C(n1572), .CO(n1568), .S(n1575) );
CMPR32X2TS U1825 ( .A(n1578), .B(n1577), .C(n1576), .CO(n1572), .S(n1579) );
CMPR32X2TS U1826 ( .A(n1582), .B(n1581), .C(n1580), .CO(n1576), .S(n1583) );
CMPR32X2TS U1827 ( .A(n1590), .B(n1589), .C(n1588), .CO(n1584), .S(n1591) );
CMPR32X2TS U1828 ( .A(n1594), .B(n1593), .C(n1592), .CO(n1588), .S(n1595) );
AO22XLTS U1829 ( .A0(n1629), .A1(P_Sgf[23]), .B0(n1643), .B1(n1595), .Y(n261) );
CMPR32X2TS U1830 ( .A(n1598), .B(n1597), .C(n1596), .CO(n1592), .S(n1599) );
AO22XLTS U1831 ( .A0(n1629), .A1(P_Sgf[22]), .B0(n1643), .B1(n1599), .Y(n260) );
CMPR32X2TS U1832 ( .A(n1602), .B(n1601), .C(n1600), .CO(n1596), .S(n1603) );
AO22XLTS U1833 ( .A0(n1629), .A1(P_Sgf[21]), .B0(n1643), .B1(n1603), .Y(n259) );
CMPR32X2TS U1834 ( .A(n1606), .B(n1605), .C(n1604), .CO(n1600), .S(n1607) );
AO22XLTS U1835 ( .A0(n1629), .A1(P_Sgf[20]), .B0(n1643), .B1(n1607), .Y(n258) );
CMPR32X2TS U1836 ( .A(n1610), .B(n1609), .C(n1608), .CO(n1604), .S(n1611) );
AO22XLTS U1837 ( .A0(n1629), .A1(P_Sgf[19]), .B0(n1612), .B1(n1611), .Y(n257) );
CMPR32X2TS U1838 ( .A(n1615), .B(n1614), .C(n1613), .CO(n1608), .S(n1616) );
AO22XLTS U1839 ( .A0(n1629), .A1(P_Sgf[18]), .B0(n1660), .B1(n1616), .Y(n256) );
CMPR32X2TS U1840 ( .A(n1619), .B(n1618), .C(n1617), .CO(n1613), .S(n1620) );
AO22XLTS U1841 ( .A0(n1629), .A1(P_Sgf[17]), .B0(n1660), .B1(n1620), .Y(n255) );
CMPR32X2TS U1842 ( .A(n1623), .B(n1622), .C(n1621), .CO(n1617), .S(n1624) );
AO22XLTS U1843 ( .A0(n1629), .A1(P_Sgf[16]), .B0(n1660), .B1(n1624), .Y(n254) );
CMPR32X2TS U1844 ( .A(n1627), .B(n1626), .C(n1625), .CO(n1621), .S(n1628) );
AO22XLTS U1845 ( .A0(n1629), .A1(P_Sgf[15]), .B0(n1660), .B1(n1628), .Y(n253) );
CMPR32X2TS U1846 ( .A(n1632), .B(n1631), .C(n1630), .CO(n1625), .S(n1633) );
AO22XLTS U1847 ( .A0(n1661), .A1(P_Sgf[14]), .B0(n1660), .B1(n1633), .Y(n252) );
CMPR32X2TS U1848 ( .A(n1636), .B(n1635), .C(n1634), .CO(n1630), .S(n1637) );
AO22XLTS U1849 ( .A0(n1661), .A1(P_Sgf[13]), .B0(n1654), .B1(n1637), .Y(n251) );
ADDHXLTS U1850 ( .A(n1639), .B(n1638), .CO(n1634), .S(n1640) );
AO22XLTS U1851 ( .A0(n1661), .A1(P_Sgf[12]), .B0(n1660), .B1(n1640), .Y(n250) );
AO22XLTS U1852 ( .A0(n1661), .A1(P_Sgf[11]), .B0(n1654), .B1(n1641), .Y(n249) );
AO22XLTS U1853 ( .A0(n1661), .A1(P_Sgf[10]), .B0(n1643), .B1(n1642), .Y(n248) );
AO22XLTS U1854 ( .A0(n1661), .A1(P_Sgf[9]), .B0(n1654), .B1(n1644), .Y(n247)
);
AO22XLTS U1855 ( .A0(n1661), .A1(P_Sgf[8]), .B0(n1654), .B1(n1645), .Y(n246)
);
AO22XLTS U1856 ( .A0(n1661), .A1(P_Sgf[7]), .B0(n1654), .B1(n1646), .Y(n245)
);
AO22XLTS U1857 ( .A0(n1661), .A1(P_Sgf[6]), .B0(n1654), .B1(n1647), .Y(n244)
);
AO22XLTS U1858 ( .A0(n1661), .A1(P_Sgf[5]), .B0(n1654), .B1(n1648), .Y(n243)
);
AO22XLTS U1859 ( .A0(n1661), .A1(P_Sgf[4]), .B0(n1654), .B1(n1649), .Y(n242)
);
AO22XLTS U1860 ( .A0(n1661), .A1(P_Sgf[3]), .B0(n1654), .B1(n1650), .Y(n241)
);
AO22XLTS U1861 ( .A0(n1661), .A1(P_Sgf[2]), .B0(n1654), .B1(n1651), .Y(n240)
);
AO22XLTS U1862 ( .A0(n1661), .A1(P_Sgf[0]), .B0(n1654), .B1(n1653), .Y(n238)
);
ADDHXLTS U1863 ( .A(n1656), .B(n1655), .CO(n1658), .S(n1511) );
XOR2X1TS U1864 ( .A(n1658), .B(n1657), .Y(n1659) );
AO22XLTS U1865 ( .A0(Sgf_normalized_result[0]), .A1(n1663), .B0(
final_result_ieee[0]), .B1(n1662), .Y(n200) );
AO22XLTS U1866 ( .A0(n490), .A1(n1663), .B0(final_result_ieee[1]), .B1(n1662), .Y(n199) );
AO22XLTS U1867 ( .A0(n482), .A1(n1663), .B0(final_result_ieee[2]), .B1(n1662), .Y(n198) );
AO22XLTS U1868 ( .A0(Sgf_normalized_result[3]), .A1(n1663), .B0(
final_result_ieee[3]), .B1(n1662), .Y(n197) );
AO22XLTS U1869 ( .A0(Sgf_normalized_result[4]), .A1(n1663), .B0(
final_result_ieee[4]), .B1(n1662), .Y(n196) );
AO22XLTS U1870 ( .A0(Sgf_normalized_result[5]), .A1(n1663), .B0(
final_result_ieee[5]), .B1(n1662), .Y(n195) );
AO22XLTS U1871 ( .A0(Sgf_normalized_result[6]), .A1(n1663), .B0(
final_result_ieee[6]), .B1(n1662), .Y(n194) );
AO22XLTS U1872 ( .A0(Sgf_normalized_result[7]), .A1(n1663), .B0(
final_result_ieee[7]), .B1(n1662), .Y(n193) );
AO22XLTS U1873 ( .A0(Sgf_normalized_result[8]), .A1(n1663), .B0(
final_result_ieee[8]), .B1(n1662), .Y(n192) );
AO22XLTS U1874 ( .A0(Sgf_normalized_result[9]), .A1(n1663), .B0(
final_result_ieee[9]), .B1(n1662), .Y(n191) );
AO22XLTS U1875 ( .A0(Sgf_normalized_result[10]), .A1(n1663), .B0(
final_result_ieee[10]), .B1(n1662), .Y(n190) );
AO22XLTS U1876 ( .A0(Sgf_normalized_result[11]), .A1(n1663), .B0(
final_result_ieee[11]), .B1(n1662), .Y(n189) );
AO22XLTS U1877 ( .A0(Sgf_normalized_result[12]), .A1(n1663), .B0(
final_result_ieee[12]), .B1(n1662), .Y(n188) );
AO22XLTS U1878 ( .A0(Sgf_normalized_result[13]), .A1(n1663), .B0(
final_result_ieee[13]), .B1(n1662), .Y(n187) );
AO22XLTS U1879 ( .A0(Sgf_normalized_result[14]), .A1(n1663), .B0(
final_result_ieee[14]), .B1(n1662), .Y(n186) );
AO22XLTS U1880 ( .A0(Sgf_normalized_result[15]), .A1(n1663), .B0(
final_result_ieee[15]), .B1(n1662), .Y(n185) );
AO22XLTS U1881 ( .A0(Sgf_normalized_result[16]), .A1(n1663), .B0(
final_result_ieee[16]), .B1(n1662), .Y(n184) );
AO22XLTS U1882 ( .A0(Sgf_normalized_result[17]), .A1(n1663), .B0(
final_result_ieee[17]), .B1(n1662), .Y(n183) );
AO22XLTS U1883 ( .A0(Sgf_normalized_result[18]), .A1(n1663), .B0(
final_result_ieee[18]), .B1(n1662), .Y(n182) );
AO22XLTS U1884 ( .A0(Sgf_normalized_result[19]), .A1(n1663), .B0(
final_result_ieee[19]), .B1(n1662), .Y(n181) );
AO22XLTS U1885 ( .A0(Sgf_normalized_result[20]), .A1(n1663), .B0(
final_result_ieee[20]), .B1(n1662), .Y(n180) );
AO22XLTS U1886 ( .A0(Sgf_normalized_result[21]), .A1(n1663), .B0(
final_result_ieee[21]), .B1(n1662), .Y(n179) );
AO22XLTS U1887 ( .A0(Sgf_normalized_result[22]), .A1(n1663), .B0(
final_result_ieee[22]), .B1(n1662), .Y(n178) );
OA22X1TS U1888 ( .A0(n1665), .A1(final_result_ieee[23]), .B0(
exp_oper_result[0]), .B1(n1664), .Y(n177) );
OA22X1TS U1889 ( .A0(n1665), .A1(final_result_ieee[24]), .B0(
exp_oper_result[1]), .B1(n1664), .Y(n176) );
OA22X1TS U1890 ( .A0(n1665), .A1(final_result_ieee[25]), .B0(
exp_oper_result[2]), .B1(n1664), .Y(n175) );
OA22X1TS U1891 ( .A0(n1665), .A1(final_result_ieee[26]), .B0(
exp_oper_result[3]), .B1(n1664), .Y(n174) );
OA22X1TS U1892 ( .A0(n1665), .A1(final_result_ieee[27]), .B0(
exp_oper_result[4]), .B1(n1664), .Y(n173) );
OA22X1TS U1893 ( .A0(n1665), .A1(final_result_ieee[28]), .B0(
exp_oper_result[5]), .B1(n1664), .Y(n172) );
OA22X1TS U1894 ( .A0(n1665), .A1(final_result_ieee[29]), .B0(
exp_oper_result[6]), .B1(n1664), .Y(n171) );
OA22X1TS U1895 ( .A0(n1665), .A1(final_result_ieee[30]), .B0(
exp_oper_result[7]), .B1(n1664), .Y(n170) );
initial $sdf_annotate("FPU_Multiplication_Function_ASIC_fpu_syn_constraints_clk40.tcl_RKOA_1STAGE_syn.sdf");
endmodule |
module limbus_cpu_cpu_debug_slave_sysclk (
// inputs:
clk,
ir_in,
sr,
vs_udr,
vs_uir,
// outputs:
jdo,
take_action_break_a,
take_action_break_b,
take_action_break_c,
take_action_ocimem_a,
take_action_ocimem_b,
take_action_tracectrl,
take_no_action_break_a,
take_no_action_break_b,
take_no_action_break_c,
take_no_action_ocimem_a
)
;
output [ 37: 0] jdo;
output take_action_break_a;
output take_action_break_b;
output take_action_break_c;
output take_action_ocimem_a;
output take_action_ocimem_b;
output take_action_tracectrl;
output take_no_action_break_a;
output take_no_action_break_b;
output take_no_action_break_c;
output take_no_action_ocimem_a;
input clk;
input [ 1: 0] ir_in;
input [ 37: 0] sr;
input vs_udr;
input vs_uir;
reg enable_action_strobe /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
reg [ 1: 0] ir /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
reg [ 37: 0] jdo /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
reg jxuir /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
reg sync2_udr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
reg sync2_uir /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
wire sync_udr;
wire sync_uir;
wire take_action_break_a;
wire take_action_break_b;
wire take_action_break_c;
wire take_action_ocimem_a;
wire take_action_ocimem_b;
wire take_action_tracectrl;
wire take_no_action_break_a;
wire take_no_action_break_b;
wire take_no_action_break_c;
wire take_no_action_ocimem_a;
wire unxunused_resetxx3;
wire unxunused_resetxx4;
reg update_jdo_strobe /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
assign unxunused_resetxx3 = 1'b1;
altera_std_synchronizer the_altera_std_synchronizer3
(
.clk (clk),
.din (vs_udr),
.dout (sync_udr),
.reset_n (unxunused_resetxx3)
);
defparam the_altera_std_synchronizer3.depth = 2;
assign unxunused_resetxx4 = 1'b1;
altera_std_synchronizer the_altera_std_synchronizer4
(
.clk (clk),
.din (vs_uir),
.dout (sync_uir),
.reset_n (unxunused_resetxx4)
);
defparam the_altera_std_synchronizer4.depth = 2;
always @(posedge clk)
begin
sync2_udr <= sync_udr;
update_jdo_strobe <= sync_udr & ~sync2_udr;
enable_action_strobe <= update_jdo_strobe;
sync2_uir <= sync_uir;
jxuir <= sync_uir & ~sync2_uir;
end
assign take_action_ocimem_a = enable_action_strobe && (ir == 2'b00) &&
~jdo[35] && jdo[34];
assign take_no_action_ocimem_a = enable_action_strobe && (ir == 2'b00) &&
~jdo[35] && ~jdo[34];
assign take_action_ocimem_b = enable_action_strobe && (ir == 2'b00) &&
jdo[35];
assign take_action_break_a = enable_action_strobe && (ir == 2'b10) &&
~jdo[36] &&
jdo[37];
assign take_no_action_break_a = enable_action_strobe && (ir == 2'b10) &&
~jdo[36] &&
~jdo[37];
assign take_action_break_b = enable_action_strobe && (ir == 2'b10) &&
jdo[36] && ~jdo[35] &&
jdo[37];
assign take_no_action_break_b = enable_action_strobe && (ir == 2'b10) &&
jdo[36] && ~jdo[35] &&
~jdo[37];
assign take_action_break_c = enable_action_strobe && (ir == 2'b10) &&
jdo[36] && jdo[35] &&
jdo[37];
assign take_no_action_break_c = enable_action_strobe && (ir == 2'b10) &&
jdo[36] && jdo[35] &&
~jdo[37];
assign take_action_tracectrl = enable_action_strobe && (ir == 2'b11) &&
jdo[15];
always @(posedge clk)
begin
if (jxuir)
ir <= ir_in;
if (update_jdo_strobe)
jdo <= sr;
end
endmodule |
module inport #(parameter X_LOCAL = 2, parameter Y_LOCAL = 2)
(
input wire clka,
input wire rsta,
input wire [1:0] diff_pair_din,
input wire [47:0] channel_din,
output wire request_dout,
output wire x_hit_dout,
output wire y_hit_dout,
output wire [47:0] packet_dout
);
//---- Signal declaration
// Port flow_handler
wire request_unreg;
// Segmentation Registers
reg [47:0] input_pipe_reg = 48'b0;
// Register for arbitration request
reg request_reg;
// Port flow_handler
input_flow_handler inport_flow_handler
(
.clka (clka),
.rsta (rsta),
.diff_pair_p(diff_pair_din[1]),
.diff_pair_n(diff_pair_din[0]),
.pipe_en (request_unreg)
); // flow_handler
// Registered outputs
assign packet_dout = input_pipe_reg[47:0];
assign request_dout = request_reg;
// Derived outputs
assign x_hit_dout = (input_pipe_reg[47:44] == X_LOCAL) ? 1'b1 : 1'b0;
assign y_hit_dout = (input_pipe_reg[43:40] == Y_LOCAL) ? 1'b1 : 1'b0;
//---- Memory Elements
// Segmentation Registers
always @(posedge clka)
if (request_unreg)
input_pipe_reg <= channel_din;
// Register for arbitration request
always @(posedge clka)
request_reg <= request_unreg;
endmodule |
module altera_mem_if_ddr3_phy_0001_qsys_sequencer_sequencer_ram (
// inputs:
address,
byteenable,
chipselect,
clk,
clken,
reset,
write,
writedata,
// outputs:
readdata
)
;
parameter INIT_FILE = "../altera_mem_if_ddr3_phy_0001_qsys_sequencer_sequencer_ram.hex";
output [ 31: 0] readdata;
input [ 8: 0] address;
input [ 3: 0] byteenable;
input chipselect;
input clk;
input clken;
input reset;
input write;
input [ 31: 0] writedata;
wire [ 31: 0] readdata;
wire wren;
assign wren = chipselect & write;
//s1, which is an e_avalon_slave
//s2, which is an e_avalon_slave
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
altsyncram the_altsyncram
(
.address_a (address),
.byteena_a (byteenable),
.clock0 (clk),
.clocken0 (clken),
.data_a (writedata),
.q_a (readdata),
.wren_a (wren)
);
defparam the_altsyncram.byte_size = 8,
the_altsyncram.init_file = "UNUSED",
the_altsyncram.lpm_type = "altsyncram",
the_altsyncram.maximum_depth = 512,
the_altsyncram.numwords_a = 512,
the_altsyncram.operation_mode = "SINGLE_PORT",
the_altsyncram.outdata_reg_a = "UNREGISTERED",
the_altsyncram.ram_block_type = "AUTO",
the_altsyncram.read_during_write_mode_mixed_ports = "DONT_CARE",
the_altsyncram.width_a = 32,
the_altsyncram.width_byteena_a = 4,
the_altsyncram.widthad_a = 9;
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// altsyncram the_altsyncram
// (
// .address_a (address),
// .byteena_a (byteenable),
// .clock0 (clk),
// .clocken0 (clken),
// .data_a (writedata),
// .q_a (readdata),
// .wren_a (wren)
// );
//
// defparam the_altsyncram.byte_size = 8,
// the_altsyncram.init_file = "UNUSED",
// the_altsyncram.lpm_type = "altsyncram",
// the_altsyncram.maximum_depth = 512,
// the_altsyncram.numwords_a = 512,
// the_altsyncram.operation_mode = "SINGLE_PORT",
// the_altsyncram.outdata_reg_a = "UNREGISTERED",
// the_altsyncram.ram_block_type = "AUTO",
// the_altsyncram.read_during_write_mode_mixed_ports = "DONT_CARE",
// the_altsyncram.width_a = 32,
// the_altsyncram.width_byteena_a = 4,
// the_altsyncram.widthad_a = 9;
//
//synthesis read_comments_as_HDL off
endmodule |
module boothMultiplier(
input [3:0] multiplicand,
input [3:0] multiplier,
output [7:0] product,
input clock,
input reset
);
reg [3:0] A, Q, M;
reg Q_1;
reg [3:0] count;
wire [3:0] sum, difference;
always @(posedge clock)
begin
if (reset) begin
A <= 4'b0;
M <= multiplicand;
Q <= multiplier;
Q_1 <= 1'b0;
count <= 3'b0;
end
else begin
case ({Q[0], Q_1})
2'b01 : {A, Q, Q_1} <= {sum[3], sum, Q};
2'b10 : {A, Q, Q_1} <= {difference[3], difference, Q};
default: {A, Q, Q_1} <= {A[3], A, Q};
endcase
count <= count + 1;
end
end
alu adder (A, M, 0,sum);
alu subtracter (A, ~M, 1,difference);
assign product = {A, Q};
endmodule |
module alu(a,b,cin,out);
input [3:0] a;
input [3:0] b;
input cin;
output [3:0] out;
assign out = a + b + cin;
endmodule |
module top();
// Inputs are registered
reg A1;
reg A2;
reg A3;
reg A4;
reg B1;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A1 = 1'bX;
A2 = 1'bX;
A3 = 1'bX;
A4 = 1'bX;
B1 = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A1 = 1'b0;
#40 A2 = 1'b0;
#60 A3 = 1'b0;
#80 A4 = 1'b0;
#100 B1 = 1'b0;
#120 VGND = 1'b0;
#140 VNB = 1'b0;
#160 VPB = 1'b0;
#180 VPWR = 1'b0;
#200 A1 = 1'b1;
#220 A2 = 1'b1;
#240 A3 = 1'b1;
#260 A4 = 1'b1;
#280 B1 = 1'b1;
#300 VGND = 1'b1;
#320 VNB = 1'b1;
#340 VPB = 1'b1;
#360 VPWR = 1'b1;
#380 A1 = 1'b0;
#400 A2 = 1'b0;
#420 A3 = 1'b0;
#440 A4 = 1'b0;
#460 B1 = 1'b0;
#480 VGND = 1'b0;
#500 VNB = 1'b0;
#520 VPB = 1'b0;
#540 VPWR = 1'b0;
#560 VPWR = 1'b1;
#580 VPB = 1'b1;
#600 VNB = 1'b1;
#620 VGND = 1'b1;
#640 B1 = 1'b1;
#660 A4 = 1'b1;
#680 A3 = 1'b1;
#700 A2 = 1'b1;
#720 A1 = 1'b1;
#740 VPWR = 1'bx;
#760 VPB = 1'bx;
#780 VNB = 1'bx;
#800 VGND = 1'bx;
#820 B1 = 1'bx;
#840 A4 = 1'bx;
#860 A3 = 1'bx;
#880 A2 = 1'bx;
#900 A1 = 1'bx;
end
sky130_fd_sc_lp__a41o dut (.A1(A1), .A2(A2), .A3(A3), .A4(A4), .B1(B1), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule |
module RAMB16_S1_S9 (
CLKA, CLKB, ENB, WEA, WEB, ENA, SSRA, SSRB, DIPB, ADDRA, ADDRB, DIA, DIB, DOA, DOB, DOPB
);
input wire CLKA;
input wire CLKB;
output reg [7 : 0] DOB;
output reg [0 : 0] DOA;
input wire [0 : 0] WEA;
input wire [0 : 0] WEB;
input wire [10 : 0] ADDRB;
input wire [13 : 0] ADDRA;
input wire [7 : 0] DIB;
input wire [0 : 0] DIA;
input wire ENB;
input wire ENA;
input wire SSRA;
input wire SSRB;
input wire DIPB;
output wire DOPB;
parameter WIDTHA = 1;
parameter SIZEA = 16384;
parameter ADDRWIDTHA = 14;
parameter WIDTHB = 8;
parameter SIZEB = 2048;
parameter ADDRWIDTHB = 11;
`define max(a,b) (a) > (b) ? (a) : (b)
`define min(a,b) (a) < (b) ? (a) : (b)
`include "../includes/log2func.v"
localparam maxSIZE = `max(SIZEA, SIZEB);
localparam maxWIDTH = `max(WIDTHA, WIDTHB);
localparam minWIDTH = `min(WIDTHA, WIDTHB);
localparam RATIO = maxWIDTH / minWIDTH;
localparam log2RATIO = `CLOG2(RATIO);
reg [minWIDTH-1:0] RAM [0:maxSIZE-1];
always @(posedge CLKA)
if (WEA)
RAM[ADDRA] <= DIA;
else
DOA <= RAM[ADDRA];
genvar i;
generate for (i = 0; i < RATIO; i = i+1)
begin: portA
localparam [log2RATIO-1:0] lsbaddr = i;
always @(posedge CLKB)
if (WEB)
RAM[{ADDRB, lsbaddr}] <= DIB[(i+1)*minWIDTH-1:i*minWIDTH];
else
DOB[(i+1)*minWIDTH-1:i*minWIDTH] <= RAM[{ADDRB, lsbaddr}];
end
endgenerate
endmodule |
module outputs
wire [63 : 0] mav_sie_write, mav_write, mv_read, mv_sie_read;
// register rg_mie
reg [11 : 0] rg_mie;
reg [11 : 0] rg_mie$D_IN;
wire rg_mie$EN;
// rule scheduling signals
wire CAN_FIRE_mav_sie_write,
CAN_FIRE_mav_write,
CAN_FIRE_reset,
WILL_FIRE_mav_sie_write,
WILL_FIRE_mav_write,
WILL_FIRE_reset;
// inputs to muxes for submodule ports
wire [11 : 0] MUX_rg_mie$write_1__VAL_3;
// remaining internal signals
wire [11 : 0] mie__h92, x__h467, x__h901;
wire seie__h132,
seie__h562,
ssie__h126,
ssie__h556,
stie__h129,
stie__h559,
ueie__h131,
ueie__h561,
usie__h125,
usie__h555,
utie__h128,
utie__h558;
// action method reset
assign CAN_FIRE_reset = 1'd1 ;
assign WILL_FIRE_reset = EN_reset ;
// value method mv_read
assign mv_read = { 52'd0, rg_mie } ;
// actionvalue method mav_write
assign mav_write = { 52'd0, mie__h92 } ;
assign CAN_FIRE_mav_write = 1'd1 ;
assign WILL_FIRE_mav_write = EN_mav_write ;
// value method mv_sie_read
assign mv_sie_read = { 52'd0, x__h467 } ;
// actionvalue method mav_sie_write
assign mav_sie_write = { 52'd0, x__h901 } ;
assign CAN_FIRE_mav_sie_write = 1'd1 ;
assign WILL_FIRE_mav_sie_write = EN_mav_sie_write ;
// inputs to muxes for submodule ports
assign MUX_rg_mie$write_1__VAL_3 =
{ rg_mie[11],
1'b0,
seie__h562,
ueie__h561,
rg_mie[7],
1'b0,
stie__h559,
utie__h558,
rg_mie[3],
1'b0,
ssie__h556,
usie__h555 } ;
// register rg_mie
always@(EN_mav_write or
mie__h92 or
EN_reset or EN_mav_sie_write or MUX_rg_mie$write_1__VAL_3)
case (1'b1)
EN_mav_write: rg_mie$D_IN = mie__h92;
EN_reset: rg_mie$D_IN = 12'd0;
EN_mav_sie_write: rg_mie$D_IN = MUX_rg_mie$write_1__VAL_3;
default: rg_mie$D_IN = 12'b101010101010 /* unspecified value */ ;
endcase
assign rg_mie$EN = EN_mav_write || EN_mav_sie_write || EN_reset ;
// remaining internal signals
assign mie__h92 =
{ mav_write_wordxl[11],
1'b0,
seie__h132,
ueie__h131,
mav_write_wordxl[7],
1'b0,
stie__h129,
utie__h128,
mav_write_wordxl[3],
1'b0,
ssie__h126,
usie__h125 } ;
assign seie__h132 = mav_write_misa[18] && mav_write_wordxl[9] ;
assign seie__h562 = mav_sie_write_misa[18] && mav_sie_write_wordxl[9] ;
assign ssie__h126 = mav_write_misa[18] && mav_write_wordxl[1] ;
assign ssie__h556 = mav_sie_write_misa[18] && mav_sie_write_wordxl[1] ;
assign stie__h129 = mav_write_misa[18] && mav_write_wordxl[5] ;
assign stie__h559 = mav_sie_write_misa[18] && mav_sie_write_wordxl[5] ;
assign ueie__h131 = mav_write_misa[13] && mav_write_wordxl[8] ;
assign ueie__h561 = mav_sie_write_misa[13] && mav_sie_write_wordxl[8] ;
assign usie__h125 = mav_write_misa[13] && mav_write_wordxl[0] ;
assign usie__h555 = mav_sie_write_misa[13] && mav_sie_write_wordxl[0] ;
assign utie__h128 = mav_write_misa[13] && mav_write_wordxl[4] ;
assign utie__h558 = mav_sie_write_misa[13] && mav_sie_write_wordxl[4] ;
assign x__h467 =
{ 2'd0, rg_mie[9:8], 2'd0, rg_mie[5:4], 2'd0, rg_mie[1:0] } ;
assign x__h901 =
{ 2'd0,
seie__h562,
ueie__h561,
2'd0,
stie__h559,
utie__h558,
2'd0,
ssie__h556,
usie__h555 } ;
// handling of inlined registers
always@(posedge CLK)
begin
if (RST_N == `BSV_RESET_VALUE)
begin
rg_mie <= `BSV_ASSIGNMENT_DELAY 12'd0;
end
else
begin
if (rg_mie$EN) rg_mie <= `BSV_ASSIGNMENT_DELAY rg_mie$D_IN;
end
end
// synopsys translate_off
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
initial
begin
rg_mie = 12'hAAA;
end
`endif // BSV_NO_INITIAL_BLOCKS
// synopsys translate_on
endmodule |
module zqynq_lab_1_design_axi_timer_0_1(capturetrig0, capturetrig1, generateout0,
generateout1, pwm0, interrupt, freeze, s_axi_aclk, s_axi_aresetn, s_axi_awaddr, s_axi_awvalid,
s_axi_awready, s_axi_wdata, s_axi_wstrb, s_axi_wvalid, s_axi_wready, s_axi_bresp,
s_axi_bvalid, s_axi_bready, s_axi_araddr, s_axi_arvalid, s_axi_arready, s_axi_rdata,
s_axi_rresp, s_axi_rvalid, s_axi_rready)
/* synthesis syn_black_box black_box_pad_pin="capturetrig0,capturetrig1,generateout0,generateout1,pwm0,interrupt,freeze,s_axi_aclk,s_axi_aresetn,s_axi_awaddr[4:0],s_axi_awvalid,s_axi_awready,s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wvalid,s_axi_wready,s_axi_bresp[1:0],s_axi_bvalid,s_axi_bready,s_axi_araddr[4:0],s_axi_arvalid,s_axi_arready,s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rvalid,s_axi_rready" */;
input capturetrig0;
input capturetrig1;
output generateout0;
output generateout1;
output pwm0;
output interrupt;
input freeze;
input s_axi_aclk;
input s_axi_aresetn;
input [4:0]s_axi_awaddr;
input s_axi_awvalid;
output s_axi_awready;
input [31:0]s_axi_wdata;
input [3:0]s_axi_wstrb;
input s_axi_wvalid;
output s_axi_wready;
output [1:0]s_axi_bresp;
output s_axi_bvalid;
input s_axi_bready;
input [4:0]s_axi_araddr;
input s_axi_arvalid;
output s_axi_arready;
output [31:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output s_axi_rvalid;
input s_axi_rready;
endmodule |
module works only with 16/32/64 gtx input data width");
$finish;
end
endgenerate
`ifdef SIMULATION
// info msgs
always @ (posedge clk)
begin
if (txcominit) begin
HOST_OOB_TITLE = "Issued cominit";
$display("[Host] OOB: %s @%t",HOST_OOB_TITLE,$time);
end
if (txcomwake) begin
HOST_OOB_TITLE = "Issued comwake";
$display("[Host] OOB: %s @%t",HOST_OOB_TITLE,$time);
end
if (state_wait_linkup) begin
HOST_OOB_TITLE = "Link is up";
$display("[Host] OOB: %s @%t",HOST_OOB_TITLE,$time);
end
if (set_wait_synp) begin
HOST_OOB_TITLE = "Started continious align sending";
$display("[Host] OOB: %s @%t",HOST_OOB_TITLE,$time);
end
end
`endif
always @ (posedge clk)
rxcom_timer <= rst | rxcominit_done & state_wait_cominit | rxcomwake_done & state_wait_comwake | rxcominitdet & state_wait_cominit | rxcomwakedet & state_wait_comwake ? 10'h0 : cominit_req_l & state_idle | rxcominitdet_l & state_wait_cominit | rxcomwakedet_l & state_wait_comwake ? rxcom_timer + CLK_TO_TIMER_CONTRIB[9:0] : 10'h0;
// set data outputs to gtx
assign txdata_out = txdata;
assign txcharisk_out = txcharisk;
// rxelectidle timer logic
assign eidle_timer_done = eidle_timer == 64;
always @ (posedge clk)
eidle_timer <= rst | rxelecidle | ~state_wait_eidle ? 8'b0 : eidle_timer + CLK_TO_TIMER_CONTRIB[7:0];
always @ (posedge clk) begin
if (rst || !detected_alignp) detected_alignp_cntr <= NUM_CON_ALIGNS;
else if (|detected_alignp_cntr) detected_alignp_cntr <= detected_alignp_cntr -1;
detected_alignp_r <= detected_alignp_cntr == 0;
end
always @ (posedge clk)
debug <= rst ? 12'h000 : {
state_idle,
state_wait_cominit,
state_wait_comwake,
state_recal_tx,
state_wait_eidle,
state_wait_rxrst,
state_wait_align,
state_wait_synp,
state_wait_linkup,
state_error,
oob_start,
oob_error} | debug;
endmodule |
module tb_sim;
`include "bch_params.vh"
parameter T = 3;
parameter OPTION = "SERIAL";
parameter DATA_BITS = 5;
parameter BITS = 1;
parameter REG_RATIO = 1;
parameter SEED = 0;
localparam BCH_PARAMS = bch_params(DATA_BITS, T);
reg [31:0] seed = SEED;
initial begin
$dumpfile("test.vcd");
$dumpvars(0);
end
localparam TCQ = 1;
reg clk = 0;
reg reset = 0;
reg [DATA_BITS-1:0] din = 0;
reg [$clog2(T+2)-1:0] nerr = 0;
reg [`BCH_CODE_BITS(BCH_PARAMS)-1:0] error = 0;
function [DATA_BITS-1:0] randk;
input [31:0] useless;
integer i;
begin
for (i = 0; i < (31 + DATA_BITS) / 32; i = i + 1)
if (i * 32 > DATA_BITS) begin
if (DATA_BITS % 32)
/* Placate isim */
randk[i*32+:(DATA_BITS%32) ? (DATA_BITS%32) : 1] = $random(seed);
end else
randk[i*32+:32] = $random(seed);
end
endfunction
function integer n_errors;
input [31:0] useless;
integer i;
begin
n_errors = (32'h7fff_ffff & $random(seed)) % (T + 1);
end
endfunction
function [`BCH_CODE_BITS(BCH_PARAMS)-1:0] rande;
input [31:0] nerr;
integer i;
begin
rande = 0;
while (nerr) begin
i = (32'h7fff_ffff & $random(seed)) % (`BCH_CODE_BITS(BCH_PARAMS));
if (!((1 << i) & rande)) begin
rande = rande | (1 << i);
nerr = nerr - 1;
end
end
end
endfunction
reg encode_start = 0;
wire wrong;
wire ready;
reg active = 0;
sim #(BCH_PARAMS, OPTION, BITS, REG_RATIO) u_sim(
.clk(clk),
.reset(1'b0),
.data_in(din),
.error(error),
.ready(ready),
.encode_start(active),
.wrong(wrong)
);
always
#5 clk = ~clk;
always @(posedge wrong)
#10 $finish;
reg [31:0] s;
always @(posedge clk) begin
if (ready) begin
s = seed;
#1;
din <= randk(0);
#1;
nerr <= n_errors(0);
#1;
error <= rande(nerr);
#1;
active <= 1;
$display("%b %d flips - %b (seed = %d)", din, nerr, error, s);
end
end
initial begin
$display("GF(2^%1d) (%1d, %1d/%1d, %1d) %s",
`BCH_M(BCH_PARAMS), `BCH_N(BCH_PARAMS), `BCH_K(BCH_PARAMS),
DATA_BITS, `BCH_T(BCH_PARAMS), OPTION);
@(posedge clk);
@(posedge clk);
reset <= #1 1;
@(posedge clk);
@(posedge clk);
reset <= #1 0;
end
endmodule |
module MAC_rx_FF (
Reset ,
Clk_MAC ,
Clk_SYS ,
//MAC_rx_ctrl interface
Fifo_data ,
Fifo_data_en ,
Fifo_full ,
Fifo_data_err ,
Fifo_data_end ,
//CPU
Rx_Hwmark,
Rx_Lwmark,
RX_APPEND_CRC,
//user interface
Rx_mac_ra ,
Rx_mac_rd ,
Rx_mac_data ,
Rx_mac_BE ,
Rx_mac_sop ,
Rx_mac_pa,
Rx_mac_eop
);
input Reset ;
input Clk_MAC ;
input Clk_SYS ;
//MAC_rx_ctrl interface
input [7:0] Fifo_data ;
input Fifo_data_en ;
output Fifo_full ;
input Fifo_data_err ;
input Fifo_data_end ;
//CPU
input RX_APPEND_CRC ;
input [4:0] Rx_Hwmark ;
input [4:0] Rx_Lwmark ;
//user interface
output Rx_mac_ra ;//
input Rx_mac_rd ;
output [31:0] Rx_mac_data ;
output [1:0] Rx_mac_BE ;
output Rx_mac_pa ;
output Rx_mac_sop ;
output Rx_mac_eop ;
//******************************************************************************
//internal signals
//******************************************************************************
parameter State_byte3 =4'd0;
parameter State_byte2 =4'd1;
parameter State_byte1 =4'd2;
parameter State_byte0 =4'd3;
parameter State_be0 =4'd4;
parameter State_be3 =4'd5;
parameter State_be2 =4'd6;
parameter State_be1 =4'd7;
parameter State_err_end =4'd8;
parameter State_idle =4'd9;
parameter SYS_read =3'd0;
parameter SYS_pause =3'd1;
parameter SYS_wait_end =3'd2;
parameter SYS_idle =3'd3;
parameter FF_emtpy_err =3'd4;
reg [`MAC_RX_FF_DEPTH-1:0] Add_wr;
reg [`MAC_RX_FF_DEPTH-1:0] Add_wr_ungray;
reg [`MAC_RX_FF_DEPTH-1:0] Add_wr_gray;
reg [`MAC_RX_FF_DEPTH-1:0] Add_wr_gray_dl1;
reg [`MAC_RX_FF_DEPTH-1:0] Add_wr_reg;
reg [`MAC_RX_FF_DEPTH-1:0] Add_rd;
reg [`MAC_RX_FF_DEPTH-1:0] Add_rd_pl1;
reg [`MAC_RX_FF_DEPTH-1:0] Add_rd_gray;
reg [`MAC_RX_FF_DEPTH-1:0] Add_rd_gray_dl1;
reg [`MAC_RX_FF_DEPTH-1:0] Add_rd_ungray;
reg [35:0] Din;
reg [35:0] Din_tmp;
reg [35:0] Din_tmp_reg;
wire[35:0] Dout;
reg Wr_en;
reg Wr_en_tmp;
reg Wr_en_ptr;
wire[`MAC_RX_FF_DEPTH-1:0] Add_wr_pluse;
wire[`MAC_RX_FF_DEPTH-1:0] Add_wr_pluse4;
wire[`MAC_RX_FF_DEPTH-1:0] Add_wr_pluse3;
wire[`MAC_RX_FF_DEPTH-1:0] Add_wr_pluse2;
reg Full;
reg Almost_full;
reg Empty /* synthesis syn_keep=1 */;
reg [3:0] Current_state /* synthesis syn_keep=1 */;
reg [3:0] Next_state;
reg [7:0] Fifo_data_byte0;
reg [7:0] Fifo_data_byte1;
reg [7:0] Fifo_data_byte2;
reg [7:0] Fifo_data_byte3;
reg Fifo_data_en_dl1;
reg [7:0] Fifo_data_dl1;
reg Rx_mac_sop_tmp ;
reg Rx_mac_sop ;
reg Rx_mac_ra ;
reg Rx_mac_pa ;
reg [2:0] Current_state_SYS /* synthesis syn_keep=1 */;
reg [2:0] Next_state_SYS ;
reg [5:0] Packet_number_inFF /* synthesis syn_keep=1 */;
reg Packet_number_sub ;
wire Packet_number_add_edge;
reg Packet_number_add_dl1;
reg Packet_number_add_dl2;
reg Packet_number_add ;
reg Packet_number_add_tmp ;
reg Packet_number_add_tmp_dl1;
reg Packet_number_add_tmp_dl2;
reg Rx_mac_sop_tmp_dl1;
reg [35:0] Dout_dl1;
reg [4:0] Fifo_data_count;
reg Rx_mac_pa_tmp ;
reg Add_wr_jump_tmp ;
reg Add_wr_jump_tmp_pl1 ;
reg Add_wr_jump ;
reg Add_wr_jump_rd_pl1 ;
reg [4:0] Rx_Hwmark_pl ;
reg [4:0] Rx_Lwmark_pl ;
reg Addr_freshed_ptr ;
integer i ;
//******************************************************************************
//domain Clk_MAC,write data to dprom.a-port for write
//******************************************************************************
always @ (posedge Clk_MAC or posedge Reset)
if (Reset)
Current_state <=State_idle;
else
Current_state <=Next_state;
always @(Current_state or Fifo_data_en or Fifo_data_err or Fifo_data_end)
case (Current_state)
State_idle:
if (Fifo_data_en)
Next_state =State_byte3;
else
Next_state =Current_state;
State_byte3:
if (Fifo_data_en)
Next_state =State_byte2;
else if (Fifo_data_err)
Next_state =State_err_end;
else if (Fifo_data_end)
Next_state =State_be1;
else
Next_state =Current_state;
State_byte2:
if (Fifo_data_en)
Next_state =State_byte1;
else if (Fifo_data_err)
Next_state =State_err_end;
else if (Fifo_data_end)
Next_state =State_be2;
else
Next_state =Current_state;
State_byte1:
if (Fifo_data_en)
Next_state =State_byte0;
else if (Fifo_data_err)
Next_state =State_err_end;
else if (Fifo_data_end)
Next_state =State_be3;
else
Next_state =Current_state;
State_byte0:
if (Fifo_data_en)
Next_state =State_byte3;
else if (Fifo_data_err)
Next_state =State_err_end;
else if (Fifo_data_end)
Next_state =State_be0;
else
Next_state =Current_state;
State_be1:
Next_state =State_idle;
State_be2:
Next_state =State_idle;
State_be3:
Next_state =State_idle;
State_be0:
Next_state =State_idle;
State_err_end:
Next_state =State_idle;
default:
Next_state =State_idle;
endcase
//
always @ (posedge Clk_MAC or posedge Reset)
if (Reset)
Add_wr_reg <=0;
else if (Current_state==State_idle)
Add_wr_reg <=Add_wr;
//
always @ (posedge Reset or posedge Clk_MAC)
if (Reset)
Add_wr_gray <=0;
else
begin
Add_wr_gray[`MAC_RX_FF_DEPTH-1] <=Add_wr[`MAC_RX_FF_DEPTH-1];
for (i=`MAC_RX_FF_DEPTH-2;i>=0;i=i-1)
Add_wr_gray[i] <=Add_wr[i+1]^Add_wr[i];
end
//
always @ (posedge Clk_MAC or posedge Reset)
if (Reset)
Add_rd_gray_dl1 <=0;
else
Add_rd_gray_dl1 <=Add_rd_gray;
always @ (posedge Clk_MAC or posedge Reset)
if (Reset)
Add_rd_ungray =0;
else
begin
Add_rd_ungray[`MAC_RX_FF_DEPTH-1] =Add_rd_gray_dl1[`MAC_RX_FF_DEPTH-1];
for (i=`MAC_RX_FF_DEPTH-2;i>=0;i=i-1)
Add_rd_ungray[i] =Add_rd_ungray[i+1]^Add_rd_gray_dl1[i];
end
assign Add_wr_pluse=Add_wr+1;
assign Add_wr_pluse4=Add_wr+4;
assign Add_wr_pluse3=Add_wr+3;
assign Add_wr_pluse2=Add_wr+2;
always @ (posedge Clk_MAC or posedge Reset)
if (Reset)
Full <=0;
else if (Add_wr_pluse==Add_rd_ungray)
Full <=1;
else
Full <=0;
always @ (posedge Clk_MAC or posedge Reset)
if (Reset)
Almost_full <=0;
else if (Add_wr_pluse4==Add_rd_ungray||
Add_wr_pluse3==Add_rd_ungray||
Add_wr_pluse2==Add_rd_ungray||
Add_wr_pluse==Add_rd_ungray
)
Almost_full <=1;
else
Almost_full <=0;
assign Fifo_full =Almost_full;
//
always @ (posedge Clk_MAC or posedge Reset)
if (Reset)
Add_wr <=0;
else if (Current_state==State_err_end)
Add_wr <=Add_wr_reg;
else if (Wr_en&&!Full)
Add_wr <=Add_wr +1;
always @ (posedge Clk_MAC or posedge Reset)
if (Reset)
Add_wr_jump_tmp <=0;
else if (Current_state==State_err_end)
Add_wr_jump_tmp <=1;
else
Add_wr_jump_tmp <=0;
always @ (posedge Clk_MAC or posedge Reset)
if (Reset)
Add_wr_jump_tmp_pl1 <=0;
else
Add_wr_jump_tmp_pl1 <=Add_wr_jump_tmp;
always @ (posedge Clk_MAC or posedge Reset)
if (Reset)
Add_wr_jump <=0;
else if (Current_state==State_err_end)
Add_wr_jump <=1;
else if (Add_wr_jump_tmp_pl1)
Add_wr_jump <=0;
//
always @ (posedge Clk_MAC or posedge Reset)
if (Reset)
Fifo_data_en_dl1 <=0;
else
Fifo_data_en_dl1 <=Fifo_data_en;
always @ (posedge Clk_MAC or posedge Reset)
if (Reset)
Fifo_data_dl1 <=0;
else
Fifo_data_dl1 <=Fifo_data;
always @ (posedge Clk_MAC or posedge Reset)
if (Reset)
Fifo_data_byte3 <=0;
else if (Current_state==State_byte3&&Fifo_data_en_dl1)
Fifo_data_byte3 <=Fifo_data_dl1;
always @ (posedge Clk_MAC or posedge Reset)
if (Reset)
Fifo_data_byte2 <=0;
else if (Current_state==State_byte2&&Fifo_data_en_dl1)
Fifo_data_byte2 <=Fifo_data_dl1;
always @ (posedge Clk_MAC or posedge Reset)
if (Reset)
Fifo_data_byte1 <=0;
else if (Current_state==State_byte1&&Fifo_data_en_dl1)
Fifo_data_byte1 <=Fifo_data_dl1;
always @ (* )
case (Current_state)
State_be0:
Din_tmp ={4'b1000,Fifo_data_byte3,Fifo_data_byte2,Fifo_data_byte1,Fifo_data_dl1};
State_be1:
Din_tmp ={4'b1001,Fifo_data_byte3,24'h0};
State_be2:
Din_tmp ={4'b1010,Fifo_data_byte3,Fifo_data_byte2,16'h0};
State_be3:
Din_tmp ={4'b1011,Fifo_data_byte3,Fifo_data_byte2,Fifo_data_byte1,8'h0};
default:
Din_tmp ={4'b0000,Fifo_data_byte3,Fifo_data_byte2,Fifo_data_byte1,Fifo_data_dl1};
endcase
always @ (*)
if (Current_state==State_be0||Current_state==State_be1||
Current_state==State_be2||Current_state==State_be3||
(Current_state==State_byte0&&Fifo_data_en))
Wr_en_tmp =1;
else
Wr_en_tmp =0;
always @ (posedge Clk_MAC or posedge Reset)
if (Reset)
Din_tmp_reg <=0;
else if(Wr_en_tmp)
Din_tmp_reg <=Din_tmp;
always @ (posedge Clk_MAC or posedge Reset)
if (Reset)
Wr_en_ptr <=0;
else if(Current_state==State_idle)
Wr_en_ptr <=0;
else if(Wr_en_tmp)
Wr_en_ptr <=1;
//if not append FCS,delay one cycle write data and Wr_en signal to drop FCS
always @ (posedge Clk_MAC or posedge Reset)
if (Reset)
begin
Wr_en <=0;
Din <=0;
end
else if(RX_APPEND_CRC)
begin
Wr_en <=Wr_en_tmp;
Din <=Din_tmp;
end
else
begin
Wr_en <=Wr_en_tmp&&Wr_en_ptr;
Din <={Din_tmp[35:32],Din_tmp_reg[31:0]};
end
//this signal for read side to handle the packet number in fifo
always @ (posedge Clk_MAC or posedge Reset)
if (Reset)
Packet_number_add_tmp <=0;
else if (Current_state==State_be0||Current_state==State_be1||
Current_state==State_be2||Current_state==State_be3)
Packet_number_add_tmp <=1;
else
Packet_number_add_tmp <=0;
always @ (posedge Clk_MAC or posedge Reset)
if (Reset)
begin
Packet_number_add_tmp_dl1 <=0;
Packet_number_add_tmp_dl2 <=0;
end
else
begin
Packet_number_add_tmp_dl1 <=Packet_number_add_tmp;
Packet_number_add_tmp_dl2 <=Packet_number_add_tmp_dl1;
end
//Packet_number_add delay to Din[35] is needed to make sure the data have been wroten to ram.
//expand to two cycles long almost=16 ns
//if the Clk_SYS period less than 16 ns ,this signal need to expand to 3 or more clock cycles
always @ (posedge Clk_MAC or posedge Reset)
if (Reset)
Packet_number_add <=0;
else if (Packet_number_add_tmp_dl1||Packet_number_add_tmp_dl2)
Packet_number_add <=1;
else
Packet_number_add <=0;
//******************************************************************************
//domain Clk_SYS,read data from dprom.b-port for read
//******************************************************************************
always @ (posedge Clk_SYS or posedge Reset)
if (Reset)
Current_state_SYS <=SYS_idle;
else
Current_state_SYS <=Next_state_SYS;
always @ (Current_state_SYS or Rx_mac_rd or Rx_mac_ra or Dout or Empty)
case (Current_state_SYS)
SYS_idle:
if (Rx_mac_rd&&Rx_mac_ra&&!Empty)
Next_state_SYS =SYS_read;
else if(Rx_mac_rd&&Rx_mac_ra&&Empty)
Next_state_SYS =FF_emtpy_err;
else
Next_state_SYS =Current_state_SYS;
SYS_read:
if (Dout[35])
Next_state_SYS =SYS_wait_end;
else if (!Rx_mac_rd)
Next_state_SYS =SYS_pause;
else if (Empty)
Next_state_SYS =FF_emtpy_err;
else
Next_state_SYS =Current_state_SYS;
SYS_pause:
if (Rx_mac_rd)
Next_state_SYS =SYS_read;
else
Next_state_SYS =Current_state_SYS;
FF_emtpy_err:
if (!Empty)
Next_state_SYS =SYS_read;
else
Next_state_SYS =Current_state_SYS;
SYS_wait_end:
if (!Rx_mac_rd)
Next_state_SYS =SYS_idle;
else
Next_state_SYS =Current_state_SYS;
default:
Next_state_SYS =SYS_idle;
endcase
//gen Rx_mac_ra
always @ (posedge Clk_SYS or posedge Reset)
if (Reset)
begin
Packet_number_add_dl1 <=0;
Packet_number_add_dl2 <=0;
end
else
begin
Packet_number_add_dl1 <=Packet_number_add;
Packet_number_add_dl2 <=Packet_number_add_dl1;
end
assign Packet_number_add_edge=Packet_number_add_dl1&!Packet_number_add_dl2;
always @ (Current_state_SYS or Next_state_SYS)
if (Current_state_SYS==SYS_read&&Next_state_SYS==SYS_wait_end)
Packet_number_sub =1;
else
Packet_number_sub =0;
always @ (posedge Clk_SYS or posedge Reset)
if (Reset)
Packet_number_inFF <=0;
else if (Packet_number_add_edge&&!Packet_number_sub)
Packet_number_inFF <=Packet_number_inFF + 1;
else if (!Packet_number_add_edge&&Packet_number_sub&&Packet_number_inFF!=0)
Packet_number_inFF <=Packet_number_inFF - 1;
always @ (posedge Clk_SYS or posedge Reset)
if (Reset)
Fifo_data_count <=0;
else
Fifo_data_count <=Add_wr_ungray[`MAC_RX_FF_DEPTH-1:`MAC_RX_FF_DEPTH-5]-Add_rd[`MAC_RX_FF_DEPTH-1:`MAC_RX_FF_DEPTH-5];
always @ (posedge Clk_SYS or posedge Reset)
if (Reset)
begin
Rx_Hwmark_pl <=0;
Rx_Lwmark_pl <=0;
end
else
begin
Rx_Hwmark_pl <=Rx_Hwmark;
Rx_Lwmark_pl <=Rx_Lwmark;
end
always @ (posedge Clk_SYS or posedge Reset)
if (Reset)
Rx_mac_ra <=0;
else if (Packet_number_inFF==0&&Fifo_data_count<=Rx_Lwmark_pl)
Rx_mac_ra <=0;
else if (Packet_number_inFF>=1||Fifo_data_count>=Rx_Hwmark_pl)
Rx_mac_ra <=1;
//control Add_rd signal;
always @ (posedge Clk_SYS or posedge Reset)
if (Reset)
Add_rd <=0;
else if (Current_state_SYS==SYS_read&&!(Dout[35]&&Addr_freshed_ptr))
Add_rd <=Add_rd + 1;
always @ (posedge Clk_SYS or posedge Reset)
if (Reset)
Add_rd_pl1 <=0;
else
Add_rd_pl1 <=Add_rd;
always @ (*)
if (Add_rd_pl1==Add_rd)
Addr_freshed_ptr =0;
else
Addr_freshed_ptr =1;
//
always @ (posedge Reset or posedge Clk_SYS)
if (Reset)
Add_rd_gray <=0;
else
begin
Add_rd_gray[`MAC_RX_FF_DEPTH-1] <=Add_rd[`MAC_RX_FF_DEPTH-1];
for (i=`MAC_RX_FF_DEPTH-2;i>=0;i=i-1)
Add_rd_gray[i] <=Add_rd[i+1]^Add_rd[i];
end
//
always @ (posedge Clk_SYS or posedge Reset)
if (Reset)
Add_wr_gray_dl1 <=0;
else
Add_wr_gray_dl1 <=Add_wr_gray;
always @ (posedge Clk_SYS or posedge Reset)
if (Reset)
Add_wr_jump_rd_pl1 <=0;
else
Add_wr_jump_rd_pl1 <=Add_wr_jump;
always @ (posedge Clk_SYS or posedge Reset)
if (Reset)
Add_wr_ungray =0;
else if (!Add_wr_jump_rd_pl1)
begin
Add_wr_ungray[`MAC_RX_FF_DEPTH-1] =Add_wr_gray_dl1[`MAC_RX_FF_DEPTH-1];
for (i=`MAC_RX_FF_DEPTH-2;i>=0;i=i-1)
Add_wr_ungray[i] =Add_wr_ungray[i+1]^Add_wr_gray_dl1[i];
end
//empty signal gen
always @ (posedge Clk_SYS or posedge Reset)
if (Reset)
Empty <=1;
else if (Add_rd==Add_wr_ungray)
Empty <=1;
else
Empty <=0;
always @ (posedge Clk_SYS or posedge Reset)
if (Reset)
Dout_dl1 <=0;
else
Dout_dl1 <=Dout;
assign Rx_mac_data =Dout_dl1[31:0];
assign Rx_mac_BE =Dout_dl1[33:32];
assign Rx_mac_eop =Dout_dl1[35];
//aligned to Addr_rd
always @ (posedge Clk_SYS or posedge Reset)
if (Reset)
Rx_mac_pa_tmp <=0;
else if (Current_state_SYS==SYS_read&&!(Dout[35]&&Addr_freshed_ptr))
Rx_mac_pa_tmp <=1;
else
Rx_mac_pa_tmp <=0;
always @ (posedge Clk_SYS or posedge Reset)
if (Reset)
Rx_mac_pa <=0;
else
Rx_mac_pa <=Rx_mac_pa_tmp;
always @ (posedge Clk_SYS or posedge Reset)
if (Reset)
Rx_mac_sop_tmp <=0;
else if (Current_state_SYS==SYS_idle&&Next_state_SYS==SYS_read)
Rx_mac_sop_tmp <=1;
else
Rx_mac_sop_tmp <=0;
always @ (posedge Clk_SYS or posedge Reset)
if (Reset)
begin
Rx_mac_sop_tmp_dl1 <=0;
Rx_mac_sop <=0;
end
else
begin
Rx_mac_sop_tmp_dl1 <=Rx_mac_sop_tmp;
Rx_mac_sop <=Rx_mac_sop_tmp_dl1;
end
//******************************************************************************
duram #(36,`MAC_RX_FF_DEPTH,"M4K") U_duram(
.data_a (Din ),
.wren_a (Wr_en ),
.address_a (Add_wr ),
.address_b (Add_rd ),
.clock_a (Clk_MAC ),
.clock_b (Clk_SYS ),
.q_b (Dout ));
endmodule |
module sky130_fd_sc_hs__clkdlyinv3sd3 (
//# {{data|Data Signals}}
input A,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule |
module system_acl_iface_mm_interconnect_1 (
input wire pll_outclk0_clk, // pll_outclk0.clk
input wire clock_cross_kernel_mem1_m0_reset_reset_bridge_in_reset_reset, // clock_cross_kernel_mem1_m0_reset_reset_bridge_in_reset.reset
input wire [29:0] clock_cross_kernel_mem1_m0_address, // clock_cross_kernel_mem1_m0.address
output wire clock_cross_kernel_mem1_m0_waitrequest, // .waitrequest
input wire [4:0] clock_cross_kernel_mem1_m0_burstcount, // .burstcount
input wire [31:0] clock_cross_kernel_mem1_m0_byteenable, // .byteenable
input wire clock_cross_kernel_mem1_m0_read, // .read
output wire [255:0] clock_cross_kernel_mem1_m0_readdata, // .readdata
output wire clock_cross_kernel_mem1_m0_readdatavalid, // .readdatavalid
input wire clock_cross_kernel_mem1_m0_write, // .write
input wire [255:0] clock_cross_kernel_mem1_m0_writedata, // .writedata
input wire clock_cross_kernel_mem1_m0_debugaccess, // .debugaccess
output wire [24:0] address_span_extender_kernel_windowed_slave_address, // address_span_extender_kernel_windowed_slave.address
output wire address_span_extender_kernel_windowed_slave_write, // .write
output wire address_span_extender_kernel_windowed_slave_read, // .read
input wire [255:0] address_span_extender_kernel_windowed_slave_readdata, // .readdata
output wire [255:0] address_span_extender_kernel_windowed_slave_writedata, // .writedata
output wire [4:0] address_span_extender_kernel_windowed_slave_burstcount, // .burstcount
output wire [31:0] address_span_extender_kernel_windowed_slave_byteenable, // .byteenable
input wire address_span_extender_kernel_windowed_slave_readdatavalid, // .readdatavalid
input wire address_span_extender_kernel_windowed_slave_waitrequest // .waitrequest
);
wire clock_cross_kernel_mem1_m0_translator_avalon_universal_master_0_waitrequest; // address_span_extender_kernel_windowed_slave_translator:uav_waitrequest -> clock_cross_kernel_mem1_m0_translator:uav_waitrequest
wire [9:0] clock_cross_kernel_mem1_m0_translator_avalon_universal_master_0_burstcount; // clock_cross_kernel_mem1_m0_translator:uav_burstcount -> address_span_extender_kernel_windowed_slave_translator:uav_burstcount
wire [255:0] clock_cross_kernel_mem1_m0_translator_avalon_universal_master_0_writedata; // clock_cross_kernel_mem1_m0_translator:uav_writedata -> address_span_extender_kernel_windowed_slave_translator:uav_writedata
wire [29:0] clock_cross_kernel_mem1_m0_translator_avalon_universal_master_0_address; // clock_cross_kernel_mem1_m0_translator:uav_address -> address_span_extender_kernel_windowed_slave_translator:uav_address
wire clock_cross_kernel_mem1_m0_translator_avalon_universal_master_0_lock; // clock_cross_kernel_mem1_m0_translator:uav_lock -> address_span_extender_kernel_windowed_slave_translator:uav_lock
wire clock_cross_kernel_mem1_m0_translator_avalon_universal_master_0_write; // clock_cross_kernel_mem1_m0_translator:uav_write -> address_span_extender_kernel_windowed_slave_translator:uav_write
wire clock_cross_kernel_mem1_m0_translator_avalon_universal_master_0_read; // clock_cross_kernel_mem1_m0_translator:uav_read -> address_span_extender_kernel_windowed_slave_translator:uav_read
wire [255:0] clock_cross_kernel_mem1_m0_translator_avalon_universal_master_0_readdata; // address_span_extender_kernel_windowed_slave_translator:uav_readdata -> clock_cross_kernel_mem1_m0_translator:uav_readdata
wire clock_cross_kernel_mem1_m0_translator_avalon_universal_master_0_debugaccess; // clock_cross_kernel_mem1_m0_translator:uav_debugaccess -> address_span_extender_kernel_windowed_slave_translator:uav_debugaccess
wire [31:0] clock_cross_kernel_mem1_m0_translator_avalon_universal_master_0_byteenable; // clock_cross_kernel_mem1_m0_translator:uav_byteenable -> address_span_extender_kernel_windowed_slave_translator:uav_byteenable
wire clock_cross_kernel_mem1_m0_translator_avalon_universal_master_0_readdatavalid; // address_span_extender_kernel_windowed_slave_translator:uav_readdatavalid -> clock_cross_kernel_mem1_m0_translator:uav_readdatavalid
altera_merlin_master_translator #(
.AV_ADDRESS_W (30),
.AV_DATA_W (256),
.AV_BURSTCOUNT_W (5),
.AV_BYTEENABLE_W (32),
.UAV_ADDRESS_W (30),
.UAV_BURSTCOUNT_W (10),
.USE_READ (1),
.USE_WRITE (1),
.USE_BEGINBURSTTRANSFER (0),
.USE_BEGINTRANSFER (0),
.USE_CHIPSELECT (0),
.USE_BURSTCOUNT (1),
.USE_READDATAVALID (1),
.USE_WAITREQUEST (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (32),
.AV_ADDRESS_SYMBOLS (1),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (1),
.UAV_CONSTANT_BURST_BEHAVIOR (1),
.AV_LINEWRAPBURSTS (0),
.AV_REGISTERINCOMINGSIGNALS (0)
) clock_cross_kernel_mem1_m0_translator (
.clk (pll_outclk0_clk), // clk.clk
.reset (clock_cross_kernel_mem1_m0_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (clock_cross_kernel_mem1_m0_translator_avalon_universal_master_0_address), // avalon_universal_master_0.address
.uav_burstcount (clock_cross_kernel_mem1_m0_translator_avalon_universal_master_0_burstcount), // .burstcount
.uav_read (clock_cross_kernel_mem1_m0_translator_avalon_universal_master_0_read), // .read
.uav_write (clock_cross_kernel_mem1_m0_translator_avalon_universal_master_0_write), // .write
.uav_waitrequest (clock_cross_kernel_mem1_m0_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.uav_readdatavalid (clock_cross_kernel_mem1_m0_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.uav_byteenable (clock_cross_kernel_mem1_m0_translator_avalon_universal_master_0_byteenable), // .byteenable
.uav_readdata (clock_cross_kernel_mem1_m0_translator_avalon_universal_master_0_readdata), // .readdata
.uav_writedata (clock_cross_kernel_mem1_m0_translator_avalon_universal_master_0_writedata), // .writedata
.uav_lock (clock_cross_kernel_mem1_m0_translator_avalon_universal_master_0_lock), // .lock
.uav_debugaccess (clock_cross_kernel_mem1_m0_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_address (clock_cross_kernel_mem1_m0_address), // avalon_anti_master_0.address
.av_waitrequest (clock_cross_kernel_mem1_m0_waitrequest), // .waitrequest
.av_burstcount (clock_cross_kernel_mem1_m0_burstcount), // .burstcount
.av_byteenable (clock_cross_kernel_mem1_m0_byteenable), // .byteenable
.av_read (clock_cross_kernel_mem1_m0_read), // .read
.av_readdata (clock_cross_kernel_mem1_m0_readdata), // .readdata
.av_readdatavalid (clock_cross_kernel_mem1_m0_readdatavalid), // .readdatavalid
.av_write (clock_cross_kernel_mem1_m0_write), // .write
.av_writedata (clock_cross_kernel_mem1_m0_writedata), // .writedata
.av_debugaccess (clock_cross_kernel_mem1_m0_debugaccess), // .debugaccess
.av_beginbursttransfer (1'b0), // (terminated)
.av_begintransfer (1'b0), // (terminated)
.av_chipselect (1'b0), // (terminated)
.av_lock (1'b0), // (terminated)
.uav_clken (), // (terminated)
.av_clken (1'b1), // (terminated)
.uav_response (2'b00), // (terminated)
.av_response (), // (terminated)
.uav_writeresponserequest (), // (terminated)
.uav_writeresponsevalid (1'b0), // (terminated)
.av_writeresponserequest (1'b0), // (terminated)
.av_writeresponsevalid () // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (25),
.AV_DATA_W (256),
.UAV_DATA_W (256),
.AV_BURSTCOUNT_W (5),
.AV_BYTEENABLE_W (32),
.UAV_BYTEENABLE_W (32),
.UAV_ADDRESS_W (30),
.UAV_BURSTCOUNT_W (10),
.AV_READLATENCY (0),
.USE_READDATAVALID (1),
.USE_WAITREQUEST (1),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (32),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) address_span_extender_kernel_windowed_slave_translator (
.clk (pll_outclk0_clk), // clk.clk
.reset (clock_cross_kernel_mem1_m0_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (clock_cross_kernel_mem1_m0_translator_avalon_universal_master_0_address), // avalon_universal_slave_0.address
.uav_burstcount (clock_cross_kernel_mem1_m0_translator_avalon_universal_master_0_burstcount), // .burstcount
.uav_read (clock_cross_kernel_mem1_m0_translator_avalon_universal_master_0_read), // .read
.uav_write (clock_cross_kernel_mem1_m0_translator_avalon_universal_master_0_write), // .write
.uav_waitrequest (clock_cross_kernel_mem1_m0_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.uav_readdatavalid (clock_cross_kernel_mem1_m0_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.uav_byteenable (clock_cross_kernel_mem1_m0_translator_avalon_universal_master_0_byteenable), // .byteenable
.uav_readdata (clock_cross_kernel_mem1_m0_translator_avalon_universal_master_0_readdata), // .readdata
.uav_writedata (clock_cross_kernel_mem1_m0_translator_avalon_universal_master_0_writedata), // .writedata
.uav_lock (clock_cross_kernel_mem1_m0_translator_avalon_universal_master_0_lock), // .lock
.uav_debugaccess (clock_cross_kernel_mem1_m0_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_address (address_span_extender_kernel_windowed_slave_address), // avalon_anti_slave_0.address
.av_write (address_span_extender_kernel_windowed_slave_write), // .write
.av_read (address_span_extender_kernel_windowed_slave_read), // .read
.av_readdata (address_span_extender_kernel_windowed_slave_readdata), // .readdata
.av_writedata (address_span_extender_kernel_windowed_slave_writedata), // .writedata
.av_burstcount (address_span_extender_kernel_windowed_slave_burstcount), // .burstcount
.av_byteenable (address_span_extender_kernel_windowed_slave_byteenable), // .byteenable
.av_readdatavalid (address_span_extender_kernel_windowed_slave_readdatavalid), // .readdatavalid
.av_waitrequest (address_span_extender_kernel_windowed_slave_waitrequest), // .waitrequest
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponserequest (1'b0), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponserequest (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
endmodule |
module Speck_Block_Cipher_Multirate_v1_0_tb;
reg tb_ACLK;
reg tb_ARESETn;
// Create an instance of the example tb
`BD_WRAPPER dut (.ACLK(tb_ACLK),
.ARESETN(tb_ARESETn));
// Local Variables
// AMBA S00_AXI AXI4 Lite Local Reg
reg [`S00_AXI_DATA_BUS_WIDTH-1:0] S00_AXI_rd_data_lite;
reg [`S00_AXI_DATA_BUS_WIDTH-1:0] S00_AXI_test_data_lite [3:0];
reg [`RESP_BUS_WIDTH-1:0] S00_AXI_lite_response;
reg [`S00_AXI_ADDRESS_BUS_WIDTH-1:0] S00_AXI_mtestAddress;
reg [3-1:0] S00_AXI_mtestProtection_lite;
integer S00_AXI_mtestvectorlite; // Master side testvector
integer S00_AXI_mtestdatasizelite;
integer result_slave_lite;
// Simple Reset Generator and test
initial begin
tb_ARESETn = 1'b0;
#500;
// Release the reset on the posedge of the clk.
@(posedge tb_ACLK);
tb_ARESETn = 1'b1;
@(posedge tb_ACLK);
end
// Simple Clock Generator
initial tb_ACLK = 1'b0;
always #10 tb_ACLK = !tb_ACLK;
//------------------------------------------------------------------------
// TEST LEVEL API: CHECK_RESPONSE_OKAY
//------------------------------------------------------------------------
// Description:
// CHECK_RESPONSE_OKAY(lite_response)
// This task checks if the return lite_response is equal to OKAY
//------------------------------------------------------------------------
task automatic CHECK_RESPONSE_OKAY;
input [`RESP_BUS_WIDTH-1:0] response;
begin
if (response !== `RESPONSE_OKAY) begin
$display("TESTBENCH ERROR! lite_response is not OKAY",
"\n expected = 0x%h",`RESPONSE_OKAY,
"\n actual = 0x%h",response);
$stop;
end
end
endtask
//------------------------------------------------------------------------
// TEST LEVEL API: COMPARE_LITE_DATA
//------------------------------------------------------------------------
// Description:
// COMPARE_LITE_DATA(expected,actual)
// This task checks if the actual data is equal to the expected data.
// X is used as don't care but it is not permitted for the full vector
// to be don't care.
//------------------------------------------------------------------------
`define S_AXI_DATA_BUS_WIDTH 32
task automatic COMPARE_LITE_DATA;
input [`S_AXI_DATA_BUS_WIDTH-1:0]expected;
input [`S_AXI_DATA_BUS_WIDTH-1:0]actual;
begin
if (expected === 'hx || actual === 'hx) begin
$display("TESTBENCH ERROR! COMPARE_LITE_DATA cannot be performed with an expected or actual vector that is all 'x'!");
result_slave_lite = 0;
$stop;
end
if (actual != expected) begin
$display("TESTBENCH ERROR! Data expected is not equal to actual.",
"\nexpected = 0x%h",expected,
"\nactual = 0x%h",actual);
result_slave_lite = 0;
$stop;
end
else
begin
$display("TESTBENCH Passed! Data expected is equal to actual.",
"\n expected = 0x%h",expected,
"\n actual = 0x%h",actual);
end
end
endtask
task automatic S00_AXI_TEST;
begin
$display("---------------------------------------------------------");
$display("EXAMPLE TEST : S00_AXI");
$display("Simple register write and read example");
$display("---------------------------------------------------------");
S00_AXI_mtestvectorlite = 0;
S00_AXI_mtestAddress = `S00_AXI_SLAVE_ADDRESS;
S00_AXI_mtestProtection_lite = 0;
S00_AXI_mtestdatasizelite = `S00_AXI_MAX_DATA_SIZE;
result_slave_lite = 1;
for (S00_AXI_mtestvectorlite = 0; S00_AXI_mtestvectorlite <= 3; S00_AXI_mtestvectorlite = S00_AXI_mtestvectorlite + 1)
begin
dut.`BD_INST_NAME.master_0.cdn_axi4_lite_master_bfm_inst.WRITE_BURST_CONCURRENT( S00_AXI_mtestAddress,
S00_AXI_mtestProtection_lite,
S00_AXI_test_data_lite[S00_AXI_mtestvectorlite],
S00_AXI_mtestdatasizelite,
S00_AXI_lite_response);
$display("EXAMPLE TEST %d write : DATA = 0x%h, lite_response = 0x%h",S00_AXI_mtestvectorlite,S00_AXI_test_data_lite[S00_AXI_mtestvectorlite],S00_AXI_lite_response);
CHECK_RESPONSE_OKAY(S00_AXI_lite_response);
dut.`BD_INST_NAME.master_0.cdn_axi4_lite_master_bfm_inst.READ_BURST(S00_AXI_mtestAddress,
S00_AXI_mtestProtection_lite,
S00_AXI_rd_data_lite,
S00_AXI_lite_response);
$display("EXAMPLE TEST %d read : DATA = 0x%h, lite_response = 0x%h",S00_AXI_mtestvectorlite,S00_AXI_rd_data_lite,S00_AXI_lite_response);
CHECK_RESPONSE_OKAY(S00_AXI_lite_response);
COMPARE_LITE_DATA(S00_AXI_test_data_lite[S00_AXI_mtestvectorlite],S00_AXI_rd_data_lite);
$display("EXAMPLE TEST %d : Sequential write and read burst transfers complete from the master side. %d",S00_AXI_mtestvectorlite,S00_AXI_mtestvectorlite);
S00_AXI_mtestAddress = S00_AXI_mtestAddress + 32'h00000004;
end
$display("---------------------------------------------------------");
$display("EXAMPLE TEST S00_AXI: PTGEN_TEST_FINISHED!");
if ( result_slave_lite ) begin
$display("PTGEN_TEST: PASSED!");
end else begin
$display("PTGEN_TEST: FAILED!");
end
$display("---------------------------------------------------------");
end
endtask
// Create the test vectors
initial begin
// When performing debug enable all levels of INFO messages.
wait(tb_ARESETn === 0) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
dut.`BD_INST_NAME.master_0.cdn_axi4_lite_master_bfm_inst.set_channel_level_info(1);
// Create test data vectors
S00_AXI_test_data_lite[0] = 32'h0101FFFF;
S00_AXI_test_data_lite[1] = 32'habcd0001;
S00_AXI_test_data_lite[2] = 32'hdead0011;
S00_AXI_test_data_lite[3] = 32'hbeef0011;
end
// Drive the BFM
initial begin
// Wait for end of reset
wait(tb_ARESETn === 0) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
S00_AXI_TEST();
end
endmodule |
module, integrated by testbench
pipe3 pipe3_1( dataIn, dataIn3,
wbyteen2, wbyteen3,
regwren2, regwren3,
rwraddrd2, rwraddrd3,
reginmuxop2, reginmuxop3,
aluOut, aluOut3,
instruction2, instruction3,
clk,
reset);
// ------------- Stage 4 WB ---------------------
mux128 reginmux(aluOut3,
dataIn,
wrdata,
reginmuxop3 );
// WR inputs of previously instantiated regfile used
// ------------- Hazard Detection -----------------
hazard_detect hazard_detect1(instruction1, instruction2, instruction3,
hz1_a_or_d, hz1_b, hz3_a_or_d, hz3_b);
endmodule |
module cmp_top ();
wire rst_l ;
wire pwrok ;
wire [2:0] j_pack2 ;
wire [2:0] j_pack3 ;
wire [2:0] j_pack6 ;
wire [5:0] j_req_out_l_0 ;
wire [5:0] j_req_out_l_1 ;
wire [5:0] j_req_out_l_2 ;
wire [5:0] j_req_out_l_3 ;
wire [5:0] j_req_out_l_4 ;
wire [5:0] j_req_out_l_5 ;
wire [5:0] j_req_out_l_6 ;
wire [5:0] j_req_in_l_0 ;
wire [5:0] j_req_in_l_1 ;
wire [5:0] j_req_in_l_2 ;
wire [5:0] j_req_in_l_3 ;
wire [5:0] j_req_in_l_4 ;
wire [5:0] j_req_in_l_5 ;
wire [5:0] j_req_in_l_6 ;
reg [2:0] j_pack0_d1 ;
reg [2:0] j_pack0_d2 ;
reg [2:0] j_pack0_d3 ;
reg [2:0] j_pack1_d1 ;
reg [2:0] j_pack1_d2 ;
reg [2:0] j_pack1_d3 ;
reg j_fatal_error_l ;
reg [2:0] j_pack0_d ;
reg [2:0] j_pack1_d ;
reg [2:0] j_pack2_d ;
reg [2:0] j_pack3_d ;
reg [2:0] j_pack4_d ;
reg [2:0] j_pack5_d ;
reg [2:0] j_pack6_d ;
reg j_par_d1 ;
reg j_par_d2 ;
reg jbus_j_por_l_reg ;
reg jbi_io_j_ad_en_d ;
reg jbi_io_j_adp_en_d ;
reg jbi_io_j_adtype_en_d ;
reg jbi_io_j_pack0_en_d ;
reg jbi_io_j_pack1_en_d ;
reg [1:0] sjm_4_status ;
reg [1:0] sjm_5_status ;
reg trigger_sjm_4 ;
reg trigger_sjm_5 ;
reg reset_handler_done ;
integer sjm_init_status ;
wire start_sjm ;
wire jbus_j_por_l ;
wire j_change_l ;
wire j_clk ;
wire pwron_rst_l ;
wire j_rst_l ;
wire j_err_5 ;
wire xir_l ;
wire valid0 ;
wire valid1 ;
wire p_trdy ;
wire p_int_arb ;
wire g_int_arb ;
wire pci_master_rst_l ;
wire [7:0] pci_int1_l ;
wire [7:0] pci_int2_l ;
wire [7:0] pci_int3_l ;
wire [7:0] pci_int4_l ;
wire [5:0] pci_int5_l ;
wire [3:0] pci_int6_l ;
wire [3:0] pci_int7_l ;
wire [3:0] pci_int8_l ;
wire [7:4] pci_int4;
wire [5:0] int_in_l ;
wire p_clk ;
wire g_clk ;
wire g_rd_clk, g_rd_clk_l ;
wire g_upa_refclk, g_upa_refclk_l ;
wire upa_clk ;
wire p_bpclk ;
wire ichip_clk ;
wire p_rst_l ;
wire g_rst_l ;
wire [7:0] stub_done ;
wire [7:0] stub_pass ;
wire cken_off_done ;
wire warm_rst_l ;
wire warm_rst_trig_l ;
wire [7:0] pll_byp_offset ;
reg do_bist_warm_rst_trig_l ;
reg pwron_seq_done ;
reg trig_tap_cmd;
reg tap_end_cmd;
reg in_pll_byp;
integer delay;
wire [2:0] DBG_CK_P;
wire [2:0] DBG_CK_N;
wire [39:0] DBG_DQ;
wire DBG_VREF;
wire BURNIN;
wire [1:0] CLKOBS; // From iop of iop.v
wire [2:0] DIODE_TOP; // From iop of iop.v
wire MDC; // From iop of iop.v
wire SSI_MOSI; // From iop of iop.v
wire SSI_SCK; // From iop of iop.v
wire TDO; // From iop of iop.v
wire DO_BIST; // To iop of iop.v
wire DRAM01_N_REF_RES; // To iop of iop.v
wire DRAM01_P_REF_RES; // To iop of iop.v
wire DRAM02_SCL; // To cmp_dram of cmp_dram.v
wire DRAM13_SCL; // To cmp_dram of cmp_dram.v
wire DRAM23_N_REF_RES; // To iop of iop.v
wire DRAM23_P_REF_RES; // To iop of iop.v
wire DRAM_FAIL_OVER; // To cmp_dram of cmp_dram.v
wire [5:0] DRAM_FAIL_PART; // To cmp_dram of cmp_dram.v
wire EXT_INT_L; // To iop of iop.v
wire HSTL_VREF; // To iop of iop.v
wire JBUS_N_REF_RES; // To iop of iop.v
wire JBUS_P_REF_RES; // To iop of iop.v
wire [1:0] J_CLK; // To iop of iop.v
wire PGRM_EN; // To iop of iop.v
wire PWRON_RST_L; // To iop of iop.v
wire SSI_MISO; // To iop of iop.v
wire TCK; // To iop of iop.v
wire TCK2; // To iop of iop.v
wire TDI; // To iop of iop.v
wire TEMP_TRIG; // To iop of iop.v
wire TEST_MODE; // To iop of iop.v
wire TMS; // To iop of iop.v
wire TRIGIN; // To iop of iop.v
wire TRST_L; // To iop of iop.v
wire VDD_PLL; // To iop of iop.v
wire VDD_TSR; // To iop of iop.v
wire [2:0] XXSA; // To cmp_dram of cmp_dram.v
wire XXWP; // To cmp_dram of cmp_dram.v
wire DRAM02_SDA; // To/From cmp_dram of cmp_dram.v
wire [14:0] DRAM0_ADDR; // From iop of iop.v
wire [2:0] DRAM0_BA; // From iop of iop.v
wire DRAM0_CAS_L; // From iop of iop.v
wire [15:0] DRAM0_CB; // To/From iop of iop.v, ...
wire DRAM0_CKE; // From iop of iop.v
wire [3:0] DRAM0_CK_N; // From iop of iop.v
wire [3:0] DRAM0_CK_P; // From iop of iop.v
wire [3:0] DRAM0_CS_L; // From iop of iop.v
wire [127:0] DRAM0_DQ; // To/From iop of iop.v, ...
wire [35:0] DRAM0_DQS; // To/From iop of iop.v, ...
wire DRAM0_RAS_L; // From iop of iop.v
wire DRAM0_WE_L; // From iop of iop.v
wire DRAM13_SDA; // To/From cmp_dram of cmp_dram.v
wire [14:0] DRAM1_ADDR; // From iop of iop.v
wire [2:0] DRAM1_BA; // From iop of iop.v
wire DRAM1_CAS_L; // From iop of iop.v
wire [15:0] DRAM1_CB; // To/From iop of iop.v, ...
wire DRAM1_CKE; // From iop of iop.v
wire [3:0] DRAM1_CK_N; // From iop of iop.v
wire [3:0] DRAM1_CK_P; // From iop of iop.v
wire [3:0] DRAM1_CS_L; // From iop of iop.v
wire [127:0] DRAM1_DQ; // To/From iop of iop.v, ...
wire [35:0] DRAM1_DQS; // To/From iop of iop.v, ...
wire DRAM1_RAS_L; // From iop of iop.v
wire DRAM1_WE_L; // From iop of iop.v
wire [14:0] DRAM2_ADDR; // From iop of iop.v
wire [2:0] DRAM2_BA; // From iop of iop.v
wire DRAM2_CAS_L; // From iop of iop.v
wire [15:0] DRAM2_CB; // To/From iop of iop.v, ...
wire DRAM2_CKE; // From iop of iop.v
wire [3:0] DRAM2_CK_N; // From iop of iop.v
wire [3:0] DRAM2_CK_P; // From iop of iop.v
wire [3:0] DRAM2_CS_L; // From iop of iop.v
wire [127:0] DRAM2_DQ; // To/From iop of iop.v, ...
wire [35:0] DRAM2_DQS; // To/From iop of iop.v, ...
wire DRAM2_RAS_L; // From iop of iop.v
wire DRAM2_WE_L; // From iop of iop.v
wire [14:0] DRAM3_ADDR; // From iop of iop.v
wire [2:0] DRAM3_BA; // From iop of iop.v
wire DRAM3_CAS_L; // From iop of iop.v
wire [15:0] DRAM3_CB; // To/From iop of iop.v, ...
wire DRAM3_CKE; // From iop of iop.v
wire [3:0] DRAM3_CK_N; // From iop of iop.v
wire [3:0] DRAM3_CK_P; // From iop of iop.v
wire [3:0] DRAM3_CS_L; // From iop of iop.v
wire [127:0] DRAM3_DQ; // To/From iop of iop.v, ...
wire [35:0] DRAM3_DQS; // To/From iop of iop.v, ...
wire DRAM3_RAS_L; // From iop of iop.v
wire DRAM3_WE_L; // From iop of iop.v
wire [127:0] J_AD; // To/From iop of iop.v
wire [3:0] J_ADP; // To/From iop of iop.v
wire [7:0] J_ADTYPE; // To/From iop of iop.v
wire [2:0] J_PACK0; // To/From iop of iop.v
wire [2:0] J_PACK1; // To/From iop of iop.v
wire [2:0] J_PACK4; // To/From iop of iop.v
wire [2:0] J_PACK5; // To/From iop of iop.v
wire J_PAR; // To/From iop of iop.v
wire J_REQ0_OUT_L; // To/From iop of iop.v
wire J_REQ1_OUT_L; // To/From iop of iop.v
wire J_REQ4_IN_L; // To/From iop of iop.v
wire J_REQ5_IN_L; // To/From iop of iop.v
wire J_RST_L; // To/From iop of iop.v
wire SPARE_DDR0_PIN; // To/From iop of iop.v
wire [2:0] SPARE_DDR1_PIN;
wire [2:0] SPARE_DDR2_PIN; // To/From iop of iop.v
wire [2:0] SPARE_DDR3_PIN; // To/From iop of iop.v
wire SPARE_MISC_PIN; // To/From iop of iop.v
wire DTL_L_VREF; // To/From iop of iop.v
wire DTL_R_VREF; // To/From iop of iop.v
wire CLK_STRETCH; // To/From iop of iop.v
wire PMI; // To/From iop of iop.v
wire PLL_CHAR_IN; // To/From iop of iop.v
wire VREG_SELBG_L; // To/From iop of iop.v
wire SPARE_JBUSR_PIN; // To/From iop of iop.v
wire [1:0] TSR_TESTIO; // To/From iop of iop.v
wire [2:0] DIODE_BOT; // To/From iop of iop.v
reg [2048:0] filename;
// dummy wire used only by coreccx_coverage
wire [11:0] coreccx_pcx_retry_req_cov;
//wire for tap testing.
wire cmp_tck;
wire tclk;
`ifdef DRAM_SAT
wire clk_ddr_slfrsh ;
wire cmp_gclk ;
wire cmp_grst_l ;
wire cmp_grst ;
wire cmp_arst_l ;
wire cmp_gdbginit_l ;
wire cmp_adbginit_l ;
wire jbus_j_clk ;
//wire jbus_gclk = jbus_j_clk ;
wire jbus_gclk;
wire jbus_grst_l ;
wire jbus_arst_l ;
wire jbus_gdbginit_l ;
wire jbus_adbginit_l ;
wire dram_gclk ;
wire free_dram_gclk ;
wire dram_grst_l ;
wire dram_arst_l ;
wire dram_gdbginit_l ;
wire dram_adbginit_l ;
assign j_clk = jbus_j_clk;
assign cmp_top.iop.dram_gdbginit_l = dram_gdbginit_l ;
assign cmp_top.iop.dram_adbginit_l = dram_adbginit_l ;
assign cmp_top.iop.jbus_gdbginit_l = jbus_gdbginit_l ;
assign cmp_top.iop.jbus_adbginit_l = jbus_adbginit_l ;
assign cmp_top.iop.cmp_gdbginit_out_l = cmp_gdbginit_l ;
assign cmp_top.iop.cmp_adbginit_l = cmp_adbginit_l ;
assign cmp_top.iop.ccx_rclk = cmp_gclk; // ccx_rclk is the clock for L2-DRAM buffers.
assign cmp_top.iop.cmp_gclk = cmp_gclk ;
assign cmp_top.iop.dram_gclk = dram_gclk ;
assign cmp_top.iop.jbus_gclk = jbus_gclk ;
//assign cmp_top.iop.bscan_clock_dr_in = tck ;
assign cmp_top.iop.jbus_grst_l = jbus_grst_l ;
assign cmp_top.iop.dram_grst_l = dram_grst_l ;
assign cmp_top.iop.cmp_grst_out_l = cmp_grst_l ;
assign cmp_top.iop.jbus_arst_l = jbus_arst_l ;
assign cmp_top.iop.dram_arst_l = dram_arst_l ;
assign cmp_top.iop.cmp_arst_l = cmp_arst_l ;
assign cmp_grst = ~cmp_grst_l ;
`else
`ifdef MSS_SAT
// wires used by MSS coverage only
wire l2_iq_cas12_cov_0 = 0;
wire l2_iq_cas12_cov_1 = 0;
wire l2_iq_cas12_cov_2 = 0;
wire l2_iq_cas12_cov_3 = 0;
wire [13:0] l2_atomic_store_cov_0 = 0;
wire [13:0] l2_atomic_store_cov_1 = 0;
wire [13:0] l2_atomic_store_cov_2 = 0;
wire [13:0] l2_atomic_store_cov_3 = 0;
wire [2:0] l2_pst1_dataerr_pst2_tagerr_cov_0 = 0;
wire [2:0] l2_pst1_dataerr_pst2_tagerr_cov_1 = 0;
wire [2:0] l2_pst1_dataerr_pst2_tagerr_cov_2 = 0;
wire [2:0] l2_pst1_dataerr_pst2_tagerr_cov_3 = 0;
reg ctu_tst_pre_grst_l;
wire clk_ddr_slfrsh ;
wire cmp_gclk ;
wire cmp_rclk = cmp_top.iop.ccx.rclk ;
wire cmp_grst_l ;
wire cmp_grst ;
wire cmp_arst_l ;
wire cmp_gdbginit_l ;
wire cmp_adbginit_l ;
wire jbus_j_clk ;
//wire jbus_gclk = jbus_j_clk ;
wire jbus_gclk;
wire jbus_grst_l ;
wire jbus_arst_l ;
wire jbus_gdbginit_l ;
wire jbus_adbginit_l ;
wire dram_gclk ;
wire free_dram_gclk ;
wire dram_grst_l ;
wire dram_arst_l ;
wire dram_gdbginit_l ;
wire dram_adbginit_l ;
assign j_clk = jbus_j_clk;
assign cmp_top.iop.dram_gdbginit_l = dram_gdbginit_l ;
assign cmp_top.iop.dram_adbginit_l = dram_adbginit_l ;
assign cmp_top.iop.jbus_gdbginit_l = jbus_gdbginit_l ;
assign cmp_top.iop.jbus_adbginit_l = jbus_adbginit_l ;
assign cmp_top.iop.cmp_gdbginit_out_l = cmp_gdbginit_l ;
assign cmp_top.iop.cmp_adbginit_l = cmp_adbginit_l ;
assign cmp_top.iop.cmp_gclk = cmp_gclk ;
assign cmp_top.iop.dram_gclk = dram_gclk ;
assign cmp_top.iop.jbus_gclk = jbus_gclk ;
assign cmp_top.iop.jbus_grst_l = jbus_grst_l ;
assign cmp_top.iop.dram_grst_l = dram_grst_l ;
assign cmp_top.iop.cmp_grst_out_l = cmp_grst_l ;
assign cmp_top.iop.jbus_arst_l = jbus_arst_l ;
assign cmp_top.iop.dram_arst_l = dram_arst_l ;
assign cmp_top.iop.cmp_arst_l = cmp_arst_l ;
assign cmp_grst = ~cmp_grst_l ;
`else
wire clk_ddr_slfrsh ;
wire cmp_grst_l = cmp_top.iop.cmp_grst_out_l ;
wire cmp_grst = ~cmp_top.iop.cmp_grst_out_l ;
wire jbus_gclk = cmp_top.iop.jbus_gclk ;
wire cmp_gclk = cmp_top.iop.cmp_gclk ;
wire cmp_rclk = cmp_top.iop.sparc0.rclk ;
wire dram_gclk = cmp_top.iop.dram_gclk ;
wire jbus_j_clk = j_clk ;
wire jbus_j_clk_l = ~jbus_j_clk;
`endif // ifdef MSS_SAT
`endif // ifdef DRAM_SAT
////////////////////////////////////////////////////////
// jtag interface
////////////////////////////////////////////////////////
`ifdef DRAM_SAT
assign cmp_top.iop.ctu_misc_mode_ctl = 1'b0 ;
assign cmp_top.iop.ctu_misc_shift_dr = 1'b0 ;
assign cmp_top.iop.ctu_misc_hiz_l = 1'b0 ;
assign cmp_top.iop.ctu_misc_update_dr = 1'b0 ;
assign cmp_top.iop.ctu_misc_clock_dr = 1'b0 ;
assign cmp_top.iop.io_test_mode = 1'b0 ;
assign cmp_top.iop.ctu_ddr1_hiz_l = 0 ;
assign cmp_top.iop.ctu_ddr1_mode_ctl = 0 ;
assign cmp_top.iop.ctu_ddr2_mode_ctl = 0 ;
assign cmp_top.iop.ctu_ddr2_hiz_l = 0 ;
assign cmp_top.iop.ctu_ddr3_mode_ctl = 0 ;
assign cmp_top.iop.ctu_ddr3_hiz_l = 0 ;
assign cmp_top.iop.ctu_dram02_cmp_cken = 1'b1 ;
assign cmp_top.iop.ctu_dram13_cmp_cken = 1'b1 ;
assign cmp_top.iop.ctu_ddr0_dram_cken = 1 ;
assign cmp_top.iop.ctu_ddr1_dram_cken = 1 ;
assign cmp_top.iop.ctu_ddr2_dram_cken = 1 ;
assign cmp_top.iop.ctu_ddr3_dram_cken = 1 ;
assign cmp_top.iop.ctu_dram02_dram_cken = 1 ;
assign cmp_top.iop.ctu_dram13_dram_cken = 1 ;
assign cmp_top.iop.ctu_dram02_jbus_cken = 1 ;
assign cmp_top.iop.ctu_dram13_jbus_cken = 1 ;
assign cmp_top.iop.global_shift_enable = 1'b0 ;
assign cmp_top.iop.ctu_dram_selfrsh = clk_ddr_slfrsh;
assign cmp_top.iop.ctu_ddr0_hiz_l = 0 ;
assign cmp_top.iop.ctu_ddr0_mode_ctl = 0 ;
assign cmp_top.iop.ctu_ddr_testmode_l = 1'b1;
assign cmp_top.iop.ctu_tst_scanmode = 0 ;
assign cmp_top.iop.ctu_tst_macrotest = 0 ;
assign cmp_top.iop.ctu_tst_pre_grst_l = 1 ;
assign cmp_top.iop.ctu_tst_scan_disable = 0 ;
`endif
`ifdef MSS_SAT
assign cmp_top.iop.ctu_misc_mode_ctl = 1'b0 ;
assign cmp_top.iop.ctu_misc_shift_dr = 1'b0 ;
assign cmp_top.iop.ctu_misc_hiz_l = 1'b0 ;
assign cmp_top.iop.ctu_misc_update_dr = 1'b0 ;
assign cmp_top.iop.ctu_misc_clock_dr = 1'b0 ;
assign cmp_top.iop.ctu_ddr0_hiz_l = 0 ;
assign cmp_top.iop.ctu_ddr1_hiz_l = 0 ;
assign cmp_top.iop.ctu_ddr2_hiz_l = 0 ;
assign cmp_top.iop.ctu_ddr3_hiz_l = 0 ;
assign cmp_top.iop.ctu_ddr0_mode_ctl = 0 ;
assign cmp_top.iop.ctu_ddr1_mode_ctl = 0 ;
assign cmp_top.iop.ctu_ddr2_mode_ctl = 0 ;
assign cmp_top.iop.ctu_ddr3_mode_ctl = 0 ;
assign cmp_top.iop.ctu_scdata0_cmp_cken = 1'b1 ;
assign cmp_top.iop.ctu_scdata1_cmp_cken = 1'b1 ;
assign cmp_top.iop.ctu_scdata2_cmp_cken = 1'b1 ;
assign cmp_top.iop.ctu_scdata3_cmp_cken = 1'b1 ;
assign cmp_top.iop.ctu_sctag0_cmp_cken = 1'b1 ;
assign cmp_top.iop.ctu_sctag1_cmp_cken = 1'b1 ;
assign cmp_top.iop.ctu_sctag2_cmp_cken = 1'b1 ;
assign cmp_top.iop.ctu_sctag3_cmp_cken = 1'b1 ;
assign cmp_top.iop.ctu_ccx_cmp_cken = 1'b1 ;
assign cmp_top.iop.ctu_ddr0_dram_cken = 1 ;
assign cmp_top.iop.ctu_ddr1_dram_cken = 1 ;
assign cmp_top.iop.ctu_ddr2_dram_cken = 1 ;
assign cmp_top.iop.ctu_ddr3_dram_cken = 1 ;
assign cmp_top.iop.ctu_dram02_cmp_cken = 1'b1 ;
assign cmp_top.iop.ctu_dram13_cmp_cken = 1'b1 ;
assign cmp_top.iop.ctu_dram02_dram_cken = 1 ;
assign cmp_top.iop.ctu_dram13_dram_cken = 1 ;
assign cmp_top.iop.ctu_dram02_jbus_cken = 1 ;
assign cmp_top.iop.ctu_dram13_jbus_cken = 1 ;
assign cmp_top.iop.io_test_mode = 1'b0 ;
assign cmp_top.iop.global_shift_enable = 1'b0 ;
assign cmp_top.iop.ctu_dram_selfrsh = clk_ddr_slfrsh;
assign cmp_top.iop.ctu_ddr_testmode_l = 1'b1;
assign cmp_top.iop.ctu_tst_scanmode = 0 ;
assign cmp_top.iop.ctu_tst_macrotest = 0 ;
assign cmp_top.iop.ctu_tst_scan_disable = 0 ;
assign cmp_top.iop.ctu_sctag0_mbisten = 0;
assign cmp_top.iop.ctu_sctag1_mbisten = 0;
assign cmp_top.iop.ctu_sctag2_mbisten = 0;
assign cmp_top.iop.ctu_sctag3_mbisten = 0;
assign cmp_top.iop.ctu_tst_pre_grst_l = ctu_tst_pre_grst_l;
initial begin
ctu_tst_pre_grst_l = 0;
repeat(120) @(posedge cmp_gclk);
ctu_tst_pre_grst_l = 1;
end
`endif
////////////////////////////////////////////////////////
// OpenSPARCT1 instantiation
////////////////////////////////////////////////////////
OpenSPARCT1 iop(/*AUTOINST*/
// Outputs
.DRAM0_RAS_L (DRAM0_RAS_L),
.DRAM0_CAS_L (DRAM0_CAS_L),
.DRAM0_WE_L (DRAM0_WE_L),
.DRAM0_CS_L (DRAM0_CS_L[3:0]),
.DRAM0_CKE (DRAM0_CKE),
.DRAM0_ADDR (DRAM0_ADDR[14:0]),
.DRAM0_BA (DRAM0_BA[2:0]),
.DRAM0_CK_P (DRAM0_CK_P[3:0]),
.DRAM0_CK_N (DRAM0_CK_N[3:0]),
.DRAM1_RAS_L (DRAM1_RAS_L),
.DRAM1_CAS_L (DRAM1_CAS_L),
.DRAM1_WE_L (DRAM1_WE_L),
.DRAM1_CS_L (DRAM1_CS_L[3:0]),
.DRAM1_CKE (DRAM1_CKE),
.DRAM1_ADDR (DRAM1_ADDR[14:0]),
.DRAM1_BA (DRAM1_BA[2:0]),
.DRAM1_CK_P (DRAM1_CK_P[3:0]),
.DRAM1_CK_N (DRAM1_CK_N[3:0]),
.CLKOBS (CLKOBS[1:0]),
.DRAM2_RAS_L (DRAM2_RAS_L),
.DRAM2_CAS_L (DRAM2_CAS_L),
.DRAM2_WE_L (DRAM2_WE_L),
.DRAM2_CS_L (DRAM2_CS_L[3:0]),
.DRAM2_CKE (DRAM2_CKE),
.DRAM2_ADDR (DRAM2_ADDR[14:0]),
.DRAM2_BA (DRAM2_BA[2:0]),
.DRAM2_CK_P (DRAM2_CK_P[3:0]),
.DRAM2_CK_N (DRAM2_CK_N[3:0]),
.DRAM3_RAS_L (DRAM3_RAS_L),
.DRAM3_CAS_L (DRAM3_CAS_L),
.DRAM3_WE_L (DRAM3_WE_L),
.DRAM3_CS_L (DRAM3_CS_L[3:0]),
.DRAM3_CKE (DRAM3_CKE),
.DRAM3_ADDR (DRAM3_ADDR[14:0]),
.DRAM3_BA (DRAM3_BA[2:0]),
.DRAM3_CK_P (DRAM3_CK_P[3:0]),
.DRAM3_CK_N (DRAM3_CK_N[3:0]),
.J_PACK0 (J_PACK0[2:0]),
.J_PACK1 (J_PACK1[2:0]),
.J_REQ0_OUT_L (J_REQ0_OUT_L),
.J_REQ1_OUT_L (J_REQ1_OUT_L),
.J_ERR (J_ERR),
.TSR_TESTIO (TSR_TESTIO[1:0]),
.DIODE_TOP (DIODE_TOP[2:0]),
.DIODE_BOT (DIODE_BOT[2:0]),
.TDO (TDO),
.SSI_MOSI (SSI_MOSI),
.SSI_SCK (SSI_SCK),
.PMO (PMO),
.VDD_SENSE (VDD_SENSE),
.VSS_SENSE (VSS_SENSE),
// Inouts
.DBG_DQ (DBG_DQ[39:0]),
.DBG_CK_P (DBG_CK_P[2:0]),
.DBG_CK_N (DBG_CK_N[2:0]),
.DBG_VREF (DBG_VREF),
.DRAM0_DQ (DRAM0_DQ[127:0]),
.DRAM0_CB (DRAM0_CB[15:0]),
.DRAM0_DQS (DRAM0_DQS[35:0]),
.SPARE_DDR0_PIN (SPARE_DDR0_PIN),
.DRAM1_DQ (DRAM1_DQ[127:0]),
.DRAM1_CB (DRAM1_CB[15:0]),
.DRAM1_DQS (DRAM1_DQS[35:0]),
.SPARE_DDR1_PIN (SPARE_DDR1_PIN[2:0]),
.DRAM2_DQ (DRAM2_DQ[127:0]),
.DRAM2_CB (DRAM2_CB[15:0]),
.DRAM2_DQS (DRAM2_DQS[35:0]),
.SPARE_DDR2_PIN (SPARE_DDR2_PIN[2:0]),
.DRAM3_DQ (DRAM3_DQ[127:0]),
.DRAM3_CB (DRAM3_CB[15:0]),
.DRAM3_DQS (DRAM3_DQS[35:0]),
.SPARE_DDR3_PIN (SPARE_DDR3_PIN[2:0]),
.J_AD (J_AD[127:0]),
.J_ADP (J_ADP[3:0]),
.J_ADTYPE (J_ADTYPE[7:0]),
.J_PAR (J_PAR),
.SPARE_JBUSR_PIN (SPARE_JBUSR_PIN),
.VDDA (VDDA),
.VPP (VPP),
.SPARE_MISC_PIN (SPARE_MISC_PIN),
// Inputs
.BURNIN (BURNIN),
.DRAM01_P_REF_RES (DRAM01_P_REF_RES),
.DRAM01_N_REF_RES (DRAM01_N_REF_RES),
.DRAM23_P_REF_RES (DRAM23_P_REF_RES),
.DRAM23_N_REF_RES (DRAM23_N_REF_RES),
.J_PACK4 (J_PACK4[2:0]),
.J_PACK5 (J_PACK5[2:0]),
.J_REQ4_IN_L (J_REQ4_IN_L),
.J_REQ5_IN_L (J_REQ5_IN_L),
.J_RST_L (J_RST_L),
.DTL_L_VREF (DTL_L_VREF),
.DTL_R_VREF (DTL_R_VREF),
.JBUS_P_REF_RES (JBUS_P_REF_RES),
.JBUS_N_REF_RES (JBUS_N_REF_RES),
.J_CLK (J_CLK[1:0]),
.TCK (TCK),
.TCK2 (TCK2),
.TRST_L (TRST_L),
.TDI (TDI),
.TMS (TMS),
.TEST_MODE (TEST_MODE),
.PWRON_RST_L (PWRON_RST_L),
.SSI_MISO (SSI_MISO),
.CLK_STRETCH (CLK_STRETCH),
.DO_BIST (DO_BIST),
.EXT_INT_L (EXT_INT_L),
.PMI (PMI),
.PGRM_EN (PGRM_EN),
.PLL_CHAR_IN (PLL_CHAR_IN),
.VREG_SELBG_L (VREG_SELBG_L),
.TEMP_TRIG (TEMP_TRIG),
.TRIGIN (TRIGIN),
.HSTL_VREF (HSTL_VREF));
// .VDD_PLL (VDD_PLL),
// .VDD_TSR (VDD_TSR));
`ifdef RTL_DRAM02
// instantiate dram modules
cmp_dram cmp_dram(/*AUTOINST*/
// Inouts
.DRAM0_CB (DRAM0_CB[15:0]),
.DRAM0_DQ (DRAM0_DQ[127:0]),
.DRAM0_DQS (DRAM0_DQS[35:0]),
.DRAM1_CB (DRAM1_CB[15:0]),
.DRAM1_DQ (DRAM1_DQ[127:0]),
.DRAM1_DQS (DRAM1_DQS[35:0]),
.DRAM2_CB (DRAM2_CB[15:0]),
.DRAM2_DQ (DRAM2_DQ[127:0]),
.DRAM2_DQS (DRAM2_DQS[35:0]),
.DRAM3_CB (DRAM3_CB[15:0]),
.DRAM3_DQ (DRAM3_DQ[127:0]),
.DRAM3_DQS (DRAM3_DQS[35:0]),
.DRAM02_SDA (DRAM02_SDA),
.DRAM13_SDA (DRAM13_SDA),
// Inputs
.DRAM02_SCL (DRAM02_SCL),
.DRAM13_SCL (DRAM13_SCL),
.DRAM0_ADDR (DRAM0_ADDR[14:0]),
.DRAM0_BA (DRAM0_BA[2:0]),
.DRAM0_CAS_L (DRAM0_CAS_L),
.DRAM0_CKE (DRAM0_CKE),
.DRAM0_CK_N (DRAM0_CK_N[3:0]),
.DRAM0_CK_P (DRAM0_CK_P[3:0]),
.DRAM0_CS_L (DRAM0_CS_L[3:0]),
.DRAM0_RAS_L (DRAM0_RAS_L),
.DRAM0_RST_L (cmp_top.iop.cmp_grst_out_l), // Templated
.DRAM0_WE_L (DRAM0_WE_L),
.DRAM1_ADDR (DRAM1_ADDR[14:0]),
.DRAM1_BA (DRAM1_BA[2:0]),
.DRAM1_CAS_L (DRAM1_CAS_L),
.DRAM1_CKE (DRAM1_CKE),
.DRAM1_CK_N (DRAM1_CK_N[3:0]),
.DRAM1_CK_P (DRAM1_CK_P[3:0]),
.DRAM1_CS_L (DRAM1_CS_L[3:0]),
.DRAM1_RAS_L (DRAM1_RAS_L),
.DRAM1_RST_L (cmp_top.iop.cmp_grst_out_l), // Templated
.DRAM1_WE_L (DRAM1_WE_L),
.DRAM2_ADDR (DRAM2_ADDR[14:0]),
.DRAM2_BA (DRAM2_BA[2:0]),
.DRAM2_CAS_L (DRAM2_CAS_L),
.DRAM2_CKE (DRAM2_CKE),
.DRAM2_CK_N (DRAM2_CK_N[3:0]),
.DRAM2_CK_P (DRAM2_CK_P[3:0]),
.DRAM2_CS_L (DRAM2_CS_L[3:0]),
.DRAM2_RAS_L (DRAM2_RAS_L),
.DRAM2_RST_L (cmp_top.iop.cmp_grst_out_l), // Templated
.DRAM2_WE_L (DRAM2_WE_L),
.DRAM3_ADDR (DRAM3_ADDR[14:0]),
.DRAM3_BA (DRAM3_BA[2:0]),
.DRAM3_CAS_L (DRAM3_CAS_L),
.DRAM3_CKE (DRAM3_CKE),
.DRAM3_CK_N (DRAM3_CK_N[3:0]),
.DRAM3_CK_P (DRAM3_CK_P[3:0]),
.DRAM3_CS_L (DRAM3_CS_L[3:0]),
.DRAM3_RAS_L (DRAM3_RAS_L),
.DRAM3_RST_L (cmp_top.iop.cmp_grst_out_l), // Templated
.DRAM3_WE_L (DRAM3_WE_L),
.DRAM_FAIL_OVER (DRAM_FAIL_OVER),
.DRAM_FAIL_PART (DRAM_FAIL_PART[5:0]),
.XXSA (XXSA[2:0]),
.XXWP (XXWP),
.cmp_grst (cmp_grst),
.dram_gclk (cmp_top.iop.dram_gclk));
`endif
/*monitor AUTO_TEMPLATE
(
.rst_l(cmp_grst_l),
.clk(cmp_gclk),
);
*/
monitor monitor(/*AUTOINST*/
// Inputs
.clk (cmp_rclk), // Templated
.cmp_gclk (cmp_gclk), // Templated
.rst_l (cmp_grst_l)); // Templated
`ifdef RTL_IOBDG
dbg_port_chk dbg_port_chk () ;
`endif
cmp_mem cmp_mem();
`ifdef GATE_SIM
`else
`ifdef MSS_SAT
`else
`ifdef DRAM_SAT
err_inject err_inject();
`else
err_inject err_inject();
one_hot_mux_mon one_hot_mux_mon();
`endif // ifdef DRAM_SAT
`endif // ifdef MSS_SAT
`endif // ifdef GATE_SIM
`ifdef DRAM_SAT
`else
`ifdef MSS_SAT
slam_init slam_init();
pcx_stall pcx_stall();
cpx_stall cpx_stall();
`else
`ifdef GATE_SIM
`else
// randomly asserts sctag_pcx_stall_pq to exercise protocol adherence of Core
pcx_stall pcx_stall();
// randomly asserts CPX stall signal to make CPX packets arrive at the Cores in bursts
cpx_stall cpx_stall();
`endif // ifdef GATE_SIM
////////////////////////////////////////////////////////
// system interfaces - boot rom, external interrupts
////////////////////////////////////////////////////////
initial begin
$init_jbus_model("mem.image");
end
bw_sys bw_sys(/*AUTOINST*/
// Outputs
.ssi_miso (SSI_MISO),
.ext_int_l (EXT_INT_L),
.warm_rst_l (warm_rst_trig_l),
.temp_trig (TEMP_TRIG),
.clk_stretch (CLK_STRETCH),
// Inputs
.j_rst_l (j_rst_l),
.jbus_gclk (jbus_j_clk),
.ssi_sck (SSI_SCK),
.ssi_mosi (SSI_MOSI));
////////////////////////////////////////////////////////
// slam initial values into model
////////////////////////////////////////////////////////
slam_init slam_init () ;
////////////////////////////////////////////////////////
// efuse stub
////////////////////////////////////////////////////////
assign PGRM_EN = 0 ;
// efuse_stub efuse_stub (
// .efc_iob_coreavail_dshift (`TOP_MOD.iop.efc_iob_coreavail_dshift),
// .efc_iob_fuse_clk1 (`TOP_MOD.iop.efc_iob_fuse_clk1),
// .efc_iob_fuse_data (`TOP_MOD.iop.efc_iob_fuse_data),
// .efc_iob_fusestat_dshift (`TOP_MOD.iop.efc_iob_fusestat_dshift),
// .efc_iob_sernum0_dshift (`TOP_MOD.iop.efc_iob_sernum0_dshift),
// .efc_iob_sernum1_dshift (`TOP_MOD.iop.efc_iob_sernum1_dshift),
// .efc_iob_sernum2_dshift (`TOP_MOD.iop.efc_iob_sernum2_dshift),
// .jbus_arst_l (cmp_top.iop.jbus_arst_l),
// .jbus_gclk (jbus_j_clk)
// );
`endif // ifdef MSS_SAT
`endif // ifdef DRAM_SAT
////////////////////////////////////////////////////////
// clock generator stub
////////////////////////////////////////////////////////
`ifdef MSS_SAT
`define DRAM_OR_MSS_SAT
`else
`ifdef DRAM_SAT
`define DRAM_OR_MSS_SAT
`endif
`endif
`ifdef DRAM_OR_MSS_SAT
assign TCK = 1'b0 ;
assign TCK2 = 1'b0 ;
assign TEST_MODE = 1'b0 ;
sys_clk sys_clk (
// InOuts
.pwron_rst_l (pwron_rst_l),
.j_rst_l (j_rst_l),
.free_jbus_gclk (jbus_j_clk),
//.jbus_gclk (j_clk),
.jbus_gclk (jbus_gclk),
.free_clk (free_clk),
.dram_gclk (dram_gclk),
.free_dram_gclk (free_dram_gclk),
.cmp_gclk (cmp_gclk),
.pci_gclk (pci_gclk),
.io_gb_clkref (io_gb_clkref),
.jbus_grst_l (jbus_grst_l),
.cmp_grst_l (cmp_grst_l),
.dram_grst_l (dram_grst_l),
.jbus_arst_l (jbus_arst_l),
.cmp_arst_l (cmp_arst_l),
.dram_arst_l (dram_arst_l),
// .ctu_jbi_fst_rst_l (`TOP_MOD.iop.ctu_jbi_fst_rst_l),
.ctu_jbi_ssiclk (`TOP_MOD.iop.ctu_jbi_ssiclk),
.jbus_gdbginit_l (jbus_gdbginit_l),
.cmp_gdbginit_l (cmp_gdbginit_l),
.dram_gdbginit_l (dram_gdbginit_l),
.jbus_adbginit_l (jbus_adbginit_l),
.cmp_adbginit_l (cmp_adbginit_l),
.dram_adbginit_l (dram_adbginit_l),
.clspine_jbus_tx_sync (`TOP_MOD.iop.ctu_jbus_tx_sync_out),
.clspine_jbus_rx_sync (`TOP_MOD.iop.ctu_jbus_rx_sync_out),
.clspine_dram_tx_sync (`TOP_MOD.iop.ctu_dram_tx_sync_out),
.clspine_dram_rx_sync (`TOP_MOD.iop.ctu_dram_rx_sync_out),
// Inputs
.rst_l (rst_l));
`else
assign stub_pass[3] = 1'b1 ;
assign stub_done[3] = cken_off_done ;
assign TCK2 = TCK ;
// this part determines when to trigger a warm reset so that do_bist sequence can be driven
initial begin
pwron_seq_done = 1'b0 ;
do_bist_warm_rst_trig_l = 1'b1;
// wait for pwron_rst_l deassertion
@(posedge pwron_rst_l);
// wait for first deassertion of j_rst_l, cold pwron
@(posedge j_rst_l);
pwron_seq_done = 1'b1;
if ($test$plusargs("do_bist")) begin
// wait for wake thread to determine when efc array readout is done
// @(posedge cmp_top.iop.ctu_iob_wake_thr);
// need to be more deterministic, and since efc readout is deterministic, can hard set a wait time
// 22 cyles from deassertion of J_RST_L to efc_read_start, 8K to wake_thr
repeat (8022 * pll_byp_offset) @(posedge j_clk);
// trigger a warm reset
do_bist_warm_rst_trig_l = 1'b0;
@(posedge j_clk);
do_bist_warm_rst_trig_l = 1'b1;
end
end
assign warm_rst_l = j_fatal_error_l & warm_rst_trig_l & do_bist_warm_rst_trig_l;
cmp_clk cmp_clk (
.warm_rst_l (warm_rst_l), // input
.in_pll_byp (in_pll_byp), // input
.test_mode (TEST_MODE),
.cken_off_done (cken_off_done), // output
.tck (cmp_tck), // output
.pwron_rst_l (pwron_rst_l), // output
.j_rst_l (j_rst_l), // output
.xir_l (xir_l), // output
.pwrok (pwrok), // output
.j_clk (j_clk), // output
.pll_char_in (PLL_CHAR_IN), // output
.do_bist (DO_BIST), // output
.g_rd_clk (g_rd_clk), // output
.g_upa_refclk (g_upa_refclk), // output
.p_clk (p_clk), // output
.ichip_clk (ichip_clk)) ; // output
`endif // ifdef DRAM_OR_MSS_SAT
`ifdef DRAM_SAT
`else
`ifdef MSS_SAT
`else
////////////////////////////////////////////////////////
// iobridge rtl/stub
////////////////////////////////////////////////////////
`ifdef RTL_IOBDG
`else
ciop_iob ciop_iob(
// Outputs
.iob_clk_l2_tr (`TOP_MOD.iop.iob_ctu_l2_tr),
.iob_clk_tr (`TOP_MOD.iop.iob_ctu_tr),
.iob_cpx_data_ca (`TOP_MOD.iop.iob_cpx_data_ca[`CPX_WIDTH-1:0]),
.iob_cpx_req_cq (`TOP_MOD.iop.iob_cpx_req_cq[`IOB_CPU_WIDTH-1:0]),
.iob_ctu_coreavail (`TOP_MOD.iop.iob_ctu_coreavail[`IOB_CPU_WIDTH-1:0]),
.iob_io_dbg_data (`TOP_MOD.iop.iob_io_dbg_data[39:0]),
.iob_io_dbg_en (`TOP_MOD.iop.iob_io_dbg_en),
.iob_jbi_dbg_hi_data(`TOP_MOD.iop.iob_jbi_dbg_hi_data[47:0]),
.iob_jbi_dbg_hi_vld(`TOP_MOD.iop.iob_jbi_dbg_hi_vld),
.iob_jbi_dbg_lo_data(`TOP_MOD.iop.iob_jbi_dbg_lo_data[47:0]),
.iob_jbi_dbg_lo_vld(`TOP_MOD.iop.iob_jbi_dbg_lo_vld),
.iob_jbi_mondo_ack (`TOP_MOD.iop.iob_jbi_mondo_ack),
.iob_jbi_mondo_nack(`TOP_MOD.iop.iob_jbi_mondo_nack),
.iob_pcx_stall_pq (`TOP_MOD.iop.iob_pcx_stall_pq),
.iob_clk_data (`TOP_MOD.iop.iob_clsp_data[`IOB_CLK_WIDTH-1:0]),
.iob_clk_stall (`TOP_MOD.iop.iob_clsp_stall),
.iob_clk_vld (`TOP_MOD.iop.iob_clsp_vld),
.iob_dram02_data (`TOP_MOD.iop.iob_dram02_data[`IOB_DRAM_WIDTH-1:0]),
.iob_dram02_stall (`TOP_MOD.iop.iob_dram02_stall),
.iob_dram02_vld (`TOP_MOD.iop.iob_dram02_vld),
.iob_dram13_data (`TOP_MOD.iop.iob_dram13_data[`IOB_DRAM_WIDTH-1:0]),
.iob_dram13_stall (`TOP_MOD.iop.iob_dram13_stall),
.iob_dram13_vld (`TOP_MOD.iop.iob_dram13_vld),
.iob_jbi_pio_data (`TOP_MOD.iop.iob_jbi_pio_data[`IOB_JBI_WIDTH-1:0]),
.iob_jbi_pio_stall (`TOP_MOD.iop.iob_jbi_pio_stall),
.iob_jbi_pio_vld (`TOP_MOD.iop.iob_jbi_pio_vld),
.iob_jbi_spi_data (`TOP_MOD.iop.iob_jbi_spi_data[`IOB_SPI_WIDTH-1:0]),
.iob_jbi_spi_stall (`TOP_MOD.iop.iob_jbi_spi_stall),
.iob_jbi_spi_vld (`TOP_MOD.iop.iob_jbi_spi_vld),
.iob_tap_data (`TOP_MOD.iop.iob_tap_data[`IOB_TAP_WIDTH-1:0]),
.iob_tap_stall (`TOP_MOD.iop.iob_tap_stall),
.iob_tap_vld (`TOP_MOD.iop.iob_tap_vld),
.iob_scanout (`TOP_MOD.iop.par_scan_tail[30]),
.iob_io_dbg_ck_p (`TOP_MOD.iop.iob_io_dbg_ck_p[2:0]),
.iob_io_dbg_ck_n (`TOP_MOD.iop.iob_io_dbg_ck_n[2:0]),
// Inputs
.clk_iob_cken (`TOP_MOD.iop.ctu_iob_jbus_cken),
.clspine_iob_resetstat (`TOP_MOD.iop.ctu_iob_resetstat[`IOB_RESET_STAT_WIDTH-1:0]),
.clspine_iob_resetstat_wr (`TOP_MOD.iop.ctu_iob_resetstat_wr),
.clspine_jbus_rx_sync (`TOP_MOD.iop.ctu_jbus_rx_sync_out),
.clspine_jbus_tx_sync (`TOP_MOD.iop.ctu_jbus_tx_sync_out),
.cpx_iob_grant_cx2 (`TOP_MOD.iop.cpx_iob_grant_cx2[`IOB_CPU_WIDTH-1:0]),
.ctu_iob_wake_thr (`TOP_MOD.iop.ctu_iob_wake_thr),
.jbi_iob_mondo_data(`TOP_MOD.iop.jbi_iob_mondo_data[`JBI_IOB_MONDO_BUS_WIDTH-1:0]),
.jbi_iob_mondo_vld (`TOP_MOD.iop.jbi_iob_mondo_vld),
.jbus_gclk (`TOP_MOD.iop.jbi.jbus_rclk),
.jbus_grst_l (`TOP_MOD.iop.jbi.jbus_grst_l),
.pcx_iob_data_px2 (`TOP_MOD.iop.pcx_iob_data_px2[`PCX_WIDTH-1:0]),
.pcx_iob_data_rdy_px2(`TOP_MOD.iop.pcx_iob_data_rdy_px2),
.dram02_iob_data (`TOP_MOD.iop.dram02_iob_data[`DRAM_IOB_WIDTH-1:0]),
.dram02_iob_stall (`TOP_MOD.iop.dram02_iob_stall),
.dram02_iob_vld (`TOP_MOD.iop.dram02_iob_vld),
.dram13_iob_data (`TOP_MOD.iop.dram13_iob_data[`DRAM_IOB_WIDTH-1:0]),
.dram13_iob_stall (`TOP_MOD.iop.dram13_iob_stall),
.dram13_iob_vld (`TOP_MOD.iop.dram13_iob_vld),
.jbi_iob_pio_data (`TOP_MOD.iop.jbi_iob_pio_data[`JBI_IOB_WIDTH-1:0]),
.jbi_iob_pio_stall (`TOP_MOD.iop.jbi_iob_pio_stall),
.jbi_iob_pio_vld (`TOP_MOD.iop.jbi_iob_pio_vld),
.jbi_iob_spi_data (`TOP_MOD.iop.jbi_iob_spi_data[`SPI_IOB_WIDTH-1:0]),
.jbi_iob_spi_stall (`TOP_MOD.iop.jbi_iob_spi_stall),
.jbi_iob_spi_vld (`TOP_MOD.iop.jbi_iob_spi_vld),
`ifdef GATE_SIM_SPARC
.spc0_inst_done (`TOP_MOD.monitor.pc_cmp.spc0_inst_done),
.pc_w0 (`PCPATH0.ifu_fdp.pc_w),
`else
`ifdef RTL_SPARC0
.spc0_inst_done (`TOP_MOD.monitor.pc_cmp.spc0_inst_done),
.pc_w0 (`PCPATH0.fdp.pc_w),
`else
.spc0_inst_done (1'b0),
.pc_w0 (49'h0),
`endif
`endif // ifdef GATE_SIM_SPARC
`ifdef RTL_SPARC1
.spc1_inst_done (`TOP_MOD.monitor.pc_cmp.spc1_inst_done),
.pc_w1 (`PCPATH1.fdp.pc_w),
`else
.spc1_inst_done (1'b0),
.pc_w1 (49'h0),
`endif
`ifdef RTL_SPARC2
.spc2_inst_done (`TOP_MOD.monitor.pc_cmp.spc2_inst_done),
.pc_w2 (`PCPATH2.fdp.pc_w),
`else
.spc2_inst_done (1'b0),
.pc_w2 (49'h0),
`endif
`ifdef RTL_SPARC3
.spc3_inst_done (`TOP_MOD.monitor.pc_cmp.spc3_inst_done),
.pc_w3 (`PCPATH3.fdp.pc_w),
`else
.spc3_inst_done (1'b0),
.pc_w3 (49'h0),
`endif
`ifdef RTL_SPARC4
.spc4_inst_done (`TOP_MOD.monitor.pc_cmp.spc4_inst_done),
.pc_w4 (`PCPATH4.fdp.pc_w),
`else
.spc4_inst_done (1'b0),
.pc_w4 (49'h0),
`endif
`ifdef RTL_SPARC5
.spc5_inst_done (`TOP_MOD.monitor.pc_cmp.spc5_inst_done),
.pc_w5 (`PCPATH5.fdp.pc_w),
`else
.spc5_inst_done (1'b0),
.pc_w5 (49'h0),
`endif
`ifdef RTL_SPARC6
.spc6_inst_done (`TOP_MOD.monitor.pc_cmp.spc6_inst_done),
.pc_w6 (`PCPATH6.fdp.pc_w),
`else
.spc6_inst_done (1'b0),
.pc_w6 (49'h0),
`endif
`ifdef RTL_SPARC7
.spc7_inst_done (`TOP_MOD.monitor.pc_cmp.spc7_inst_done),
.pc_w7 (`PCPATH7.fdp.pc_w),
`else
.spc7_inst_done (1'b0),
.pc_w7 (49'h0),
`endif
.cmp_gclk (`TOP_MOD.iop.ccx.rclk));
`endif // ifdef RTL_IOBDG
`endif // ifdef MSS_SAT
`endif // ifdef DRAM_SAT
////////////////////////////////////////////////////////
// dft stuff
////////////////////////////////////////////////////////
// assign DO_BIST = 1'b0;
// assign CLK_STRETCH = 1'b0;
assign VREG_SELBG_L = 1'b0 ;
// assign PLL_CHAR_IN = 1'b0 ;
assign VDD_PLL = 1'b1 ;
assign VDD_TSR = 1'b1 ;
// flags for verification environment
reg fail_flag, diag_done;
initial begin
fail_flag = 0;
diag_done =0;
end // initial begin
// parse command line for monitors
initial begin
$monInit();
$monErrorDisable() ;
while (cmp_top.iop.jbus_grst_l !== 1'b0) @(posedge j_clk) ;
@(posedge cmp_top.iop.jbus_grst_l) ;
$monErrorEnable() ;
end
`ifdef DRAM_SAT
`else
`ifdef MSS_SAT
assign J_RST_L = j_rst_l ;
`else
////////////////////////////////////////////////////////
// jbus proper
////////////////////////////////////////////////////////
assign (weak0,weak1) J_AD = 128'hffffffffffffffffffffffffffffffff ;
assign (weak0,weak1) J_ADP = 4'b1111 ;
assign (weak0,weak1) J_ADTYPE = 8'b11111111 ;
assign (weak0,weak1) J_PACK0 = 3'b111 ;
assign (weak0,weak1) J_PACK1 = 3'b111 ;
assign (weak0,weak1) j_pack2 = 3'b111 ;
assign (weak0,weak1) j_pack3 = 3'b111 ;
assign (weak0,weak1) J_PACK4 = 3'b111 ;
assign (weak0,weak1) J_PACK5 = 3'b111 ;
assign (weak0,weak1) j_pack6 = 3'b111 ;
// for pll bypass case, to ensure repeatability we mask out the clock until
// entering bypass mode
reg j_clk_mask;
initial begin
j_clk_mask = 1'b1;
if ($test$plusargs("tap_pll_byp")) begin
if ($test$plusargs("mask_j_clk")) begin
$display("cmp_top.v: %0d masking j_clk", $time);
j_clk_mask = 1'b0;
@(posedge cmp_top.iop.ctu.pll_bypass);
repeat (4) @(posedge j_clk);
j_clk_mask = 1'b1;
$display("cmp_top.v: %0d unmasking j_clk", $time);
end
end
end
assign J_CLK [0] = j_clk & j_clk_mask;
assign J_CLK [1] = ~j_clk & j_clk_mask;
assign (weak0,weak1) j_req_out_l_0 = 6'b111111 ;
assign (weak0,weak1) j_req_out_l_1 = 6'b111111 ;
assign (weak0,weak1) j_req_out_l_2 = 6'b111111 ;
assign (weak0,weak1) j_req_out_l_3 = 6'b111111 ;
assign (weak0,weak1) j_req_out_l_4 = 6'b111111 ;
assign (weak0,weak1) j_req_out_l_5 = 6'b111111 ;
assign (weak0,weak1) j_req_out_l_6 = 6'b111111 ;
assign (weak0,weak1) j_req_in_l_0 = 6'b111111 ;
assign (weak0,weak1) j_req_in_l_1 = 6'b111111 ;
assign (weak0,weak1) j_req_in_l_2 = 6'b111111 ;
assign (weak0,weak1) j_req_in_l_3 = 6'b111111 ;
assign (weak0,weak1) j_req_in_l_4 = 6'b111111 ;
assign (weak0,weak1) j_req_in_l_5 = 6'b111111 ;
assign (weak0,weak1) j_req_in_l_6 = 6'b111111 ;
assign (weak0,weak1) j_change_l = 1'b1 ;
// bw pins
assign j_req_out_l_0 = {3{J_REQ1_OUT_L,J_REQ0_OUT_L}} ;
assign J_REQ4_IN_L = j_req_in_l_0 [3] ;
assign J_REQ5_IN_L = j_req_in_l_0 [4] ;
// bw
assign j_req_in_l_0 [3] = j_req_out_l_4 [0] ;
assign j_req_in_l_0 [4] = j_req_out_l_5 [0] ;
// sjm 4
assign j_req_in_l_4 [0] = j_req_out_l_5 [0] ;
assign j_req_in_l_4 [2] = j_req_out_l_0 [0] ;
assign j_req_in_l_4 [3] = j_req_out_l_1 [0] ;
// sjm 5
assign j_req_in_l_5 [1] = j_req_out_l_0 [1] ;
assign j_req_in_l_5 [2] = j_req_out_l_1 [0] ;
assign j_req_in_l_5 [5] = j_req_out_l_4 [0] ;
////////////////////////////////////////////////////////
// sjm
////////////////////////////////////////////////////////
initial begin
jbus_j_por_l_reg = 1'b0 ;
repeat (15) @(posedge jbus_j_clk) ;
jbus_j_por_l_reg = 1'b1 ;
end
assign jbus_j_por_l = jbus_j_por_l_reg ;
initial begin
$disable_errwarnmon();
end
// disable_errwarnmon is used to disable the dispmon error messages during reset
always @(negedge J_RST_L) begin
$dispmon("reset", 0, "Detected reset assertion. Will disable errwarnmon") ;
$disable_errwarnmon() ;
end
// enable_errwarnmon is used to enable the dispmon error messages after reset
always @(posedge J_RST_L) begin
if (pwron_seq_done == 1'b1) begin
$dispmon("reset", 0, "Detected reset deassertion. Will enable errwarnmon") ;
$enable_errwarnmon() ;
end
end
`ifdef NO_SJM
`else
// { start ifndef NO_SJM, SJM code segment
initial begin
// Trigger sjm stubs
trigger_sjm_4 = 1'b0;
trigger_sjm_5 = 1'b0;
// Drive reset to pci master stubs
reset_handler_done = 1'b0;
sjm_init_status = $sjm_init ;
end
always @(posedge j_clk) begin
while (cmp_top.iop.jbus_grst_l !== 1'b0) @(posedge j_clk) ;
// added to start sjms after second reset for tester runs
if ($test$plusargs("tester_rst_seq")) begin
repeat (2) @(posedge cmp_top.iop.jbus_grst_l) ;
end else
@(posedge cmp_top.iop.jbus_grst_l) ;
repeat (8) @(posedge j_clk) ;
trigger_sjm_4 = 1'b1;
trigger_sjm_5 = 1'b1;
reset_handler_done = 1'b1;
end
// } end ifndef NO_SJM, SJM code segment
`endif
assign stub_pass[1] = 1'b1 ; // sjm will die before getting here if a failure occurs
assign stub_done[1] = (sjm_4_status === 2'b11) ? 1'b1 : 1'b0 ;
`ifdef NO_SJM
`else
// { start ifndef NO_SJM, SJM code segment
////////////////////////////////////////////////////////
// sjm 4
////////////////////////////////////////////////////////
always @(posedge j_clk) begin
cmp_top.j_sjm_4.sjm_status (sjm_4_status) ;
// $info (0, "sjm 4 status %d", sjm_4_status);
end
always @ (posedge trigger_sjm_4) begin
$info (0, "Starting sjm_4 master devices");
cmp_top.j_sjm_4.sjm_start_executing;
end
jp_sjm j_sjm_4 (
.j_id (3'b100),
.j_req_in_l (j_req_in_l_4),
.j_req_out_l (j_req_out_l_4), //output
.j_ad (J_AD), //inout
.j_adp (J_ADP), //inout
.j_adtype (J_ADTYPE), //inout
.j_pack0 (J_PACK0), //inout
.j_pack1 (J_PACK1), //inout
.j_pack2 (j_pack2), //inout
.j_pack3 (j_pack3), //inout
.j_pack4 (J_PACK4), //inout
.j_pack5 (J_PACK5), //inout
.j_pack6 (j_pack6), //inout
.j_change_l (j_change_l), //inout
.j_rst_l (j_rst_l), //inout
.j_por_l (jbus_j_por_l), //inout
.j_clk (jbus_j_clk),
.pwr_ok (pwrok)
);
// } end ifndef NO_SJM, SJM code segment
`endif
assign stub_pass[2] = 1'b1 ; // sjm will die before getting here if a failure occurs
assign stub_done[2] = (sjm_5_status === 2'b11) ? 1'b1 : 1'b0 ;
// { start SJM_5 code segment
// These signals are driven by I/O Bridge when it is present
// in the system.
assign j_err_5 = 1'b0;
assign J_PAR = j_par_d2 ;
assign J_RST_L = j_rst_l ;
assign PWRON_RST_L = pwron_rst_l ;
assign p_rst_l = 1'b1;
assign g_rst_l = 1'b1;
////////////////////////////////////////////////////////
// jbus fatal error detection
////////////////////////////////////////////////////////
// DOK ON for 4 consecutive cycles indicates a fatal error. I/O Bridge
// should recognize this and assert j_rst_l.
always @(posedge jbus_j_clk) begin
j_pack0_d1 <= J_PACK0 ;
j_pack0_d2 <= j_pack0_d1 ;
j_pack0_d3 <= j_pack0_d2 ;
j_pack1_d1 <= J_PACK1 ;
j_pack1_d2 <= j_pack1_d1 ;
j_pack1_d3 <= j_pack1_d2 ;
j_fatal_error_l <= ((J_PACK0 === 3'h7) &&
(j_pack0_d1 === 3'h7) &&
(j_pack0_d2 === 3'h7) &&
(j_pack0_d3 === 3'h7)) ||
((J_PACK1 === 3'h7) &&
(j_pack1_d1 === 3'h7) &&
(j_pack1_d2 === 3'h7) &&
(j_pack1_d3 === 3'h7)) ? 1'b0 : 1'b1 ;
end
`ifdef NO_SJM
`else
// { start ifndef NO_SJM, SJM code segment
////////////////////////////////////////////////////////
// sjm 5
////////////////////////////////////////////////////////
always @(posedge j_clk) begin
cmp_top.j_sjm_5.sjm_status (sjm_5_status) ;
// $info (0, "sjm 5 status %d", sjm_5_status);
end
always @ (posedge trigger_sjm_5) begin
$info (0, "Starting sjm_5 master devices");
cmp_top.j_sjm_5.sjm_start_executing;
end
jp_sjm j_sjm_5 (
.j_id (3'b101),
.j_req_in_l (j_req_in_l_5),
.j_req_out_l (j_req_out_l_5), //output
.j_ad (J_AD), //inout
.j_adp (J_ADP), //inout
.j_adtype (J_ADTYPE), //inout
.j_pack0 (J_PACK0), //inout
.j_pack1 (J_PACK1), //inout
.j_pack2 (j_pack2), //inout
.j_pack3 (j_pack3), //inout
.j_pack4 (J_PACK4), //inout
.j_pack5 (J_PACK5), //inout
.j_pack6 (j_pack6), //inout
.j_change_l (j_change_l), //inout
.j_rst_l (j_rst_l), //inout
.j_por_l (jbus_j_por_l), //inout
.j_clk (jbus_j_clk),
.pwr_ok (pwrok)
);
// } end ifndef NO_SJM, SJM code segment
`endif
// } end SJM_5 code segment
////////////////////////////////////////////////////////
// parity generation
////////////////////////////////////////////////////////
always @(posedge jbus_j_clk) begin
j_pack0_d <= J_PACK0 ;
j_pack1_d <= J_PACK1 ;
j_pack2_d <= j_pack2 ;
j_pack3_d <= j_pack3 ;
j_pack4_d <= J_PACK4 ;
j_pack5_d <= J_PACK5 ;
j_pack6_d <= j_pack6 ;
j_par_d1 <= ~ ((j_req_out_l_0 [0]) ^
(j_req_out_l_1 [0]) ^
(j_req_out_l_2 [0]) ^
(j_req_out_l_3 [0]) ^
(j_req_out_l_4 [0]) ^
(j_req_out_l_5 [0]) ^
(j_req_out_l_6 [0]) ^
(^ j_pack0_d) ^
(^ j_pack1_d) ^
(^ j_pack2_d) ^
(^ j_pack3_d) ^
(^ j_pack4_d) ^
(^ j_pack5_d) ^
(^ j_pack6_d)) ;
j_par_d2 <= j_par_d1 ;
end
`ifdef NO_JBUS_MON
`else
////////////////////////////////////////////////////////
// jbus monitor
////////////////////////////////////////////////////////
always @(posedge diag_done) begin
$jbus_mon_finish;
end
jbus_monitor jbus_monitor (
.jbus_j_req_out_l_0 (j_req_out_l_0),
.jbus_j_req_out_l_1 (j_req_out_l_1),
.jbus_j_req_out_l_2 (j_req_out_l_2),
.jbus_j_req_out_l_3 (j_req_out_l_3),
.jbus_j_req_out_l_4 (j_req_out_l_4),
.jbus_j_req_out_l_5 (j_req_out_l_5),
.jbus_j_req_out_l_6 (j_req_out_l_6),
.jbus_j_ad (J_AD),
.jbus_j_adtype (J_ADTYPE),
.jbus_j_adp (J_ADP),
.jbus_j_pack0 (J_PACK0),
.jbus_j_pack1 (J_PACK1),
.jbus_j_pack2 (j_pack2),
.jbus_j_pack3 (j_pack3),
.jbus_j_pack4 (J_PACK4),
.jbus_j_pack5 (J_PACK5),
.jbus_j_pack6 (j_pack6),
.jbus_j_par (J_PAR),
.jbus_j_rst (j_rst_l),
.jbus_j_por (jbus_j_por_l),
.jbus_j_clk (jbus_j_clk),
.local_ports (7'h33),
.jbus_j_err ({1'b0, j_err_5, 5'h0}),
.jbus_j_change_l (j_change_l)
);
`endif // NO_JBUS_MON
`endif // ifdef MSS_SAT
`endif // ifdef DRAM_SAT
`ifdef INCLUDE_SAS_TASKS
// turn on sas interface after a delay
reg need_sas_sparc_intf_update;
initial begin
need_sas_sparc_intf_update = 0;
#12500;
need_sas_sparc_intf_update = 1;
end // initial begin
sas_intf sas_intf(/*AUTOINST*/
// Inputs
.clk (cmp_rclk), // Templated
.rst_l (cmp_grst_l)); // Templated
// create sas tasks
sas_tasks sas_tasks(/*AUTOINST*/
// Inputs
.clk (cmp_rclk), // Templated
.rst_l (cmp_grst_l)); // Templated
// sparc pipe flow monitor
sparc_pipe_flow sparc_pipe_flow(/*AUTOINST*/
// Inputs
.clk (cmp_rclk)); // Templated
// initialize client to communicate with ref model through socket
integer vsocket, i, list_handle;
initial begin
//list_handle = $bw_list(list_handle, 0);chin's change
//if not use sas, list should not be called
if($test$plusargs("use_sas_tasks"))begin
list_handle = $bw_list(list_handle, 0);
$bw_socket_init();
end
end
`endif // ifdef INCLUDE_SAS_TASKS
`ifdef GATE_SIM
initial $sdf_annotate ("cmp_top.sdf") ;
`endif
// This code is needed for production vector generation
// please do not remove it
`ifdef RTL_PAD_JBUSR
always @(posedge cmp_top.iop.pad_jbusr.clk) begin
jbi_io_j_ad_en_d = cmp_top.iop.pad_jbusr.jbi_io_j_ad_en ;
jbi_io_j_adp_en_d = cmp_top.iop.pad_jbusr.jbi_io_j_adp_en ;
jbi_io_j_adtype_en_d = cmp_top.iop.pad_jbusr.jbi_io_j_adtype_en ;
jbi_io_j_pack0_en_d = cmp_top.iop.pad_jbusr.jbi_io_j_pack0_en ;
jbi_io_j_pack1_en_d = cmp_top.iop.pad_jbusr.jbi_io_j_pack1_en ;
end
`endif
`ifdef NO_VERA
// { start of NO_VERA
// Sniper is not present when vera is missing ... tie the sparc
// ports off here
`ifdef RTL_SPARC0
`else
assign cmp_top.iop.spc0_pcx_data_pa = 1'b0 ;
assign cmp_top.iop.spc0_pcx_req_pq = 5'b00000 ;
assign cmp_top.iop.spc0_pcx_atom_pq = 1'b0 ;
`endif
`ifdef RTL_SPARC1
`else
assign cmp_top.iop.spc1_pcx_data_pa = 1'b0 ;
assign cmp_top.iop.spc1_pcx_req_pq = 5'b00000 ;
assign cmp_top.iop.spc1_pcx_atom_pq = 1'b0 ;
`endif
`ifdef RTL_SPARC2
`else
assign cmp_top.iop.spc2_pcx_data_pa = 1'b0 ;
assign cmp_top.iop.spc2_pcx_req_pq = 5'b00000 ;
assign cmp_top.iop.spc2_pcx_atom_pq = 1'b0 ;
`endif
`ifdef RTL_SPARC3
`else
assign cmp_top.iop.spc3_pcx_data_pa = 1'b0 ;
assign cmp_top.iop.spc3_pcx_req_pq = 5'b00000 ;
assign cmp_top.iop.spc3_pcx_atom_pq = 1'b0 ;
`endif
`ifdef RTL_SPARC4
`else
assign cmp_top.iop.spc4_pcx_data_pa = 1'b0 ;
assign cmp_top.iop.spc4_pcx_req_pq = 5'b00000 ;
assign cmp_top.iop.spc4_pcx_atom_pq = 1'b0 ;
`endif
`ifdef RTL_SPARC5
`else
assign cmp_top.iop.spc5_pcx_data_pa = 1'b0 ;
assign cmp_top.iop.spc5_pcx_req_pq = 5'b00000 ;
assign cmp_top.iop.spc5_pcx_atom_pq = 1'b0 ;
`endif
`ifdef RTL_SPARC6
`else
assign cmp_top.iop.spc6_pcx_data_pa = 1'b0 ;
assign cmp_top.iop.spc6_pcx_req_pq = 5'b00000 ;
assign cmp_top.iop.spc6_pcx_atom_pq = 1'b0 ;
`endif
`ifdef RTL_SPARC7
`else
assign cmp_top.iop.spc7_pcx_data_pa = 1'b0 ;
assign cmp_top.iop.spc7_pcx_req_pq = 5'b00000 ;
assign cmp_top.iop.spc7_pcx_atom_pq = 1'b0 ;
`endif
// } endif of NO_VERA
`endif
`ifdef MSS_SAT
`else
//tcl interface
`ifdef TCL_TAP_TEST
assign TCK = tclk;
tap tap( // Outputs
.stub_done (stub_done[0]),
.stub_pass(stub_pass[0]),
.trst_n (TRST_L),
.tms (TMS),
.tdi (TDI),
.trigin(TRIGIN),
.tclk(tclk),
// Inputs
.tdo (TDO),
.tck(cmp_tck)
);
`else
assign TCK = cmp_tck;
task send_tap_cmd;
begin
tap_end_cmd = 1'b1; // this will enable the final tap command that goes back to rst state
@(posedge j_clk);
trig_tap_cmd = 1'b1;
@(posedge j_clk);
trig_tap_cmd = 1'b0;
end
endtask
// all tap related commands
initial begin
trig_tap_cmd = 1'b0;
tap_end_cmd = 1'b0;
in_pll_byp = 1'b0;
if ($test$plusargs("tester_tap_seq")) begin
// pll bypass
if ($test$plusargs("tap_pll_byp")) begin
@(negedge cmp_top.tap_stub.stub_done); // wait for tap_stub to get ready
repeat (2) @(posedge TCK); // addition wait required for tap_stub
$display("cmp_top.v: %0d sending pll_bypass command thru tap", $time);
send_tap_cmd;
in_pll_byp = 1'b1;
end
// wait for first j_rst_l deassertion, warm reset
@(posedge pwron_seq_done);
// clock divider programming
if ($test$plusargs("tap_wr_clk_div")) begin
$display("cmp_top.v: %0d programming clk divs thru tap", $time);
repeat (200) @(posedge j_clk);
send_tap_cmd;
delay = 7350 - 200;
end
else begin
// 22 cycles, then efc_read_start issued, efc array readout will take 8K cycles
// inside the efc, the word addr count == 6'h3f at 7322 cycles, starting from pwron_seq_done
// question is to count 7350 or sync on the word addr count in the efc?
// why 7350? no particular reason. multiply by 4 during pll bypass mode
delay = 7350 * pll_byp_offset;
end
$display("cmp_top.v: %0d waiting %d jbus cycles for efc array readout", $time, delay);
repeat (delay) @(posedge j_clk);
// send efc_byp_data and efc_byp command
if ($test$plusargs("tap_efc_byp")) begin
$display("cmp_top.v: %0d sending efc_bypass_data and efc_bypass_cmd thru tap", $time);
send_tap_cmd;
end
// toggle out of pll_bypass
if ($test$plusargs("tap_clr_pll_bypass")) begin
send_tap_cmd;
end
// wait for start of warm rst, where bisi will started on do_bist pin
$display("cmp_top.v: %0d syncing on start of warm reset", $time);
@(negedge j_rst_l);
$display("cmp_top.v: %0d warm reset started", $time);
@(posedge j_clk);
// wait for end of warm_rst, when do_bist happens, then wait to issue bist_abort
$display("cmp_top.v: %0d syncing on end of warm reset", $time);
@(posedge j_rst_l);
$display("cmp_top.v: %0d end of warm reset detected", $time);
// bist_abort
if ($test$plusargs("tap_bist_abort")) begin
// bist_abort after 10K cpu cycles, in bypass mode cpu clk is same as j_clk
// in normal mode at 4:16 ratio, that comes to 2500 j_clk cycles
delay = 2500 * pll_byp_offset;
$display("cmp_top.v: %0d waiting %d jbus cycles before issuing bist_abort", $time, delay);
repeat (delay) @(posedge j_clk);
$display("cmp_top.v: %0d sending bist_abort thru tap", $time);
send_tap_cmd;
end
// the final tap command, go to reset state
if (tap_end_cmd == 1'b1) begin
$display("cmp_top.v: %0d sending tap end command", $time);
send_tap_cmd;
end
end
end
assign pll_byp_offset = 1 + (3 * in_pll_byp);
tap_stub tap_stub (
// Outputs
.stub_done (stub_done[0]),
.stub_pass (stub_pass[0]),
.trst_n (TRST_L),
.tms (TMS),
.tdi (TDI),
.trigin(TRIGIN),
// Inputs
.tdo (TDO),
.tck (TCK),
.diag_done (diag_done),
.trig_tap_cmd(trig_tap_cmd)
) ;
`endif
`endif
`ifdef FSDB_OFF
`else
// control dumping of debussy waveform
integer limitInMegaBytes;
initial begin
if ($test$plusargs("debussy")) begin
// the following must be specified before any other fsdb command
// [Viranjit 04/13/04]
if ($value$plusargs ("fsdbDumplimit=%d", limitInMegaBytes)) begin
$fsdbDumplimit(limitInMegaBytes);
end
if ($value$plusargs ("fsdbfile=%s", filename)) begin
$fsdbDumpfile(filename);
end
if ($test$plusargs("gate_sim")) begin
$fsdbDumpvars(1, cmp_top.iop);
`ifdef RTL_SPARC0
$fsdbDumpvars(1, cmp_top.iop.sparc0);
`endif
`ifdef RTL_SPARC1
$fsdbDumpvars(1, cmp_top.iop.sparc1);
`endif
`ifdef RTL_SPARC2
$fsdbDumpvars(1, cmp_top.iop.sparc2);
`endif
`ifdef RTL_SPARC3
$fsdbDumpvars(1, cmp_top.iop.sparc3);
`endif
`ifdef RTL_SPARC4
$fsdbDumpvars(1, cmp_top.iop.sparc4);
`endif
`ifdef RTL_SPARC5
$fsdbDumpvars(1, cmp_top.iop.sparc5);
`endif
`ifdef RTL_SPARC6
$fsdbDumpvars(1, cmp_top.iop.sparc6);
`endif
`ifdef RTL_SPARC7
$fsdbDumpvars(1, cmp_top.iop.sparc7);
`endif
end
else if ($test$plusargs("pinonly")) begin
$fsdbDumpvars(1, cmp_top.cmp_gclk);
$fsdbDumpvars(1, cmp_top.dram_gclk);
$fsdbDumpvars(1, cmp_top.jbus_gclk);
$fsdbDumpvars(1, cmp_top.iop.ctu_dram_rx_sync_out);
$fsdbDumpvars(1, cmp_top.iop.ctu_dram_tx_sync_out);
$fsdbDumpvars(1, cmp_top.iop.ctu_jbus_rx_sync_out);
$fsdbDumpvars(1, cmp_top.iop.ctu_jbus_tx_sync_out);
`ifdef GATE_SIM
`else
$fsdbDumpvars(1, cmp_top.iop.ctu.ctu_clsp.u_ctu_clsp_ctrl.text);
`endif
$fsdbDumpvars(1, cmp_top.DBG_CK_P);
$fsdbDumpvars(1, cmp_top.DBG_CK_N);
$fsdbDumpvars(1, cmp_top.DBG_DQ);
$fsdbDumpvars(1, cmp_top.DRAM0_RAS_L);
$fsdbDumpvars(1, cmp_top.DRAM0_CAS_L);
$fsdbDumpvars(1, cmp_top.DRAM0_WE_L);
$fsdbDumpvars(1, cmp_top.DRAM0_CS_L);
$fsdbDumpvars(1, cmp_top.DRAM0_CKE);
$fsdbDumpvars(1, cmp_top.DRAM0_ADDR);
$fsdbDumpvars(1, cmp_top.DRAM0_BA);
$fsdbDumpvars(1, cmp_top.ddr0_dq);
$fsdbDumpvars(1, cmp_top.ddr0_cb);
$fsdbDumpvars(1, cmp_top.DRAM0_DQS);
$fsdbDumpvars(1, cmp_top.DRAM0_CK_P);
$fsdbDumpvars(1, cmp_top.DRAM0_CK_N);
$fsdbDumpvars(1, cmp_top.SPARE_DDR0_PIN);
`ifdef RTL_PAD_DDR0
$fsdbDumpvars(1, cmp_top.ddr0_pad_dq_oe);
$fsdbDumpvars(1, cmp_top.ddr0_pad_dqs_oe);
`endif
$fsdbDumpvars(1, cmp_top.DRAM1_RAS_L);
$fsdbDumpvars(1, cmp_top.DRAM1_CAS_L);
$fsdbDumpvars(1, cmp_top.DRAM1_WE_L);
$fsdbDumpvars(1, cmp_top.DRAM1_CS_L);
$fsdbDumpvars(1, cmp_top.DRAM1_CKE);
$fsdbDumpvars(1, cmp_top.DRAM1_ADDR);
$fsdbDumpvars(1, cmp_top.DRAM1_BA);
$fsdbDumpvars(1, cmp_top.ddr1_dq);
$fsdbDumpvars(1, cmp_top.ddr1_cb);
$fsdbDumpvars(1, cmp_top.DRAM1_DQS);
$fsdbDumpvars(1, cmp_top.DRAM1_CK_P);
$fsdbDumpvars(1, cmp_top.DRAM1_CK_N);
$fsdbDumpvars(1, cmp_top.SPARE_DDR1_PIN);
`ifdef RTL_PAD_DDR1
$fsdbDumpvars(1, cmp_top.ddr1_pad_dq_oe);
$fsdbDumpvars(1, cmp_top.ddr1_pad_dqs_oe);
`endif
$fsdbDumpvars(1, cmp_top.CLKOBS);
$fsdbDumpvars(1, cmp_top.DRAM2_RAS_L);
$fsdbDumpvars(1, cmp_top.DRAM2_CAS_L);
$fsdbDumpvars(1, cmp_top.DRAM2_WE_L);
$fsdbDumpvars(1, cmp_top.DRAM2_CS_L);
$fsdbDumpvars(1, cmp_top.DRAM2_CKE);
$fsdbDumpvars(1, cmp_top.DRAM2_ADDR);
$fsdbDumpvars(1, cmp_top.DRAM2_BA);
$fsdbDumpvars(1, cmp_top.ddr2_dq);
$fsdbDumpvars(1, cmp_top.ddr2_cb);
$fsdbDumpvars(1, cmp_top.DRAM2_DQS);
$fsdbDumpvars(1, cmp_top.DRAM2_CK_P);
$fsdbDumpvars(1, cmp_top.DRAM2_CK_N);
$fsdbDumpvars(1, cmp_top.SPARE_DDR2_PIN);
`ifdef RTL_PAD_DDR2
$fsdbDumpvars(1, cmp_top.ddr2_pad_dq_oe);
$fsdbDumpvars(1, cmp_top.ddr2_pad_dqs_oe);
`endif
$fsdbDumpvars(1, cmp_top.DRAM3_RAS_L);
$fsdbDumpvars(1, cmp_top.DRAM3_CAS_L);
$fsdbDumpvars(1, cmp_top.DRAM3_WE_L);
$fsdbDumpvars(1, cmp_top.DRAM3_CS_L);
$fsdbDumpvars(1, cmp_top.DRAM3_CKE);
$fsdbDumpvars(1, cmp_top.DRAM3_ADDR);
$fsdbDumpvars(1, cmp_top.DRAM3_BA);
$fsdbDumpvars(1, cmp_top.ddr3_dq);
$fsdbDumpvars(1, cmp_top.ddr3_cb);
$fsdbDumpvars(1, cmp_top.DRAM3_DQS);
$fsdbDumpvars(1, cmp_top.DRAM3_CK_P);
$fsdbDumpvars(1, cmp_top.DRAM3_CK_N);
$fsdbDumpvars(1, cmp_top.SPARE_DDR3_PIN);
`ifdef RTL_PAD_DDR3
$fsdbDumpvars(1, cmp_top.ddr3_pad_dq_oe);
$fsdbDumpvars(1, cmp_top.ddr3_pad_dqs_oe);
`endif
$fsdbDumpvars(1, cmp_top.J_CLK);
$fsdbDumpvars(1, cmp_top.J_REQ4_IN_L);
$fsdbDumpvars(1, cmp_top.J_REQ5_IN_L);
$fsdbDumpvars(1, cmp_top.J_REQ0_OUT_L);
$fsdbDumpvars(1, cmp_top.J_REQ1_OUT_L);
$fsdbDumpvars(1, cmp_top.J_AD);
$fsdbDumpvars(1, cmp_top.J_ADP);
$fsdbDumpvars(1, cmp_top.J_ADTYPE);
$fsdbDumpvars(1, cmp_top.J_PACK0);
$fsdbDumpvars(1, cmp_top.J_PACK1);
$fsdbDumpvars(1, cmp_top.jbi_io_j_ad_en_d);
$fsdbDumpvars(1, cmp_top.jbi_io_j_adp_en_d);
$fsdbDumpvars(1, cmp_top.jbi_io_j_adtype_en_d);
$fsdbDumpvars(1, cmp_top.jbi_io_j_pack0_en_d);
$fsdbDumpvars(1, cmp_top.jbi_io_j_pack1_en_d);
$fsdbDumpvars(1, cmp_top.J_PACK4);
$fsdbDumpvars(1, cmp_top.J_PACK5);
$fsdbDumpvars(1, cmp_top.J_PAR);
$fsdbDumpvars(1, cmp_top.J_ERR);
$fsdbDumpvars(1, cmp_top.J_RST_L);
$fsdbDumpvars(1, cmp_top.SPARE_JBUSR_PIN);
$fsdbDumpvars(1, cmp_top.SPARE_MISC_PIN);
$fsdbDumpvars(1, cmp_top.BURNIN);
$fsdbDumpvars(1, cmp_top.TEMP_TRIG);
$fsdbDumpvars(1, cmp_top.PWRON_RST_L);
$fsdbDumpvars(1, cmp_top.TDI);
$fsdbDumpvars(1, cmp_top.TDO);
$fsdbDumpvars(1, cmp_top.TCK);
$fsdbDumpvars(1, cmp_top.TCK2);
$fsdbDumpvars(1, cmp_top.TRST_L);
$fsdbDumpvars(1, cmp_top.TMS);
$fsdbDumpvars(1, cmp_top.PLL_CHAR_IN);
$fsdbDumpvars(1, cmp_top.DO_BIST);
$fsdbDumpvars(1, cmp_top.TRIGIN);
$fsdbDumpvars(1, cmp_top.SSI_MOSI);
$fsdbDumpvars(1, cmp_top.SSI_MISO);
$fsdbDumpvars(1, cmp_top.SSI_SCK);
$fsdbDumpvars(1, cmp_top.EXT_INT_L);
$fsdbDumpvars(1, cmp_top.TEST_MODE);
$fsdbDumpvars(1, cmp_top.PGRM_EN);
$fsdbDumpvars(1, cmp_top.PMI);
$fsdbDumpvars(1, cmp_top.PMO);
$fsdbDumpvars(1, cmp_top.CLK_STRETCH);
$fsdbDumpvars(1, cmp_top.VREG_SELBG_L);
$fsdbDumpvars(1, cmp_top.iop.ctu_iob_wake_thr);
`ifdef RTL_IOBDG
$fsdbDumpvars(1, cmp_top.dbg_port_chk.dbg_dq_a4i0) ;
$fsdbDumpvars(1, cmp_top.dbg_port_chk.dbg_dq_a2i0) ;
$fsdbDumpvars(1, cmp_top.dbg_port_chk.dbg_dq_a2i1) ;
$fsdbDumpvars(1, cmp_top.dbg_port_chk.dbg_dq_a2i2) ;
$fsdbDumpvars(1, cmp_top.dbg_port_chk.dbg_dq_a2i3) ;
$fsdbDumpvars(1, cmp_top.dbg_port_chk.dbg_dq_a2i6) ;
$fsdbDumpvars(1, cmp_top.dbg_port_chk.dbg_dq_a2i7) ;
$fsdbDumpvars(1, cmp_top.dbg_port_chk.dbg_dq_a3i7) ;
$fsdbDumpvars(1, cmp_top.dbg_port_chk.dbg_dq_a3i6) ;
$fsdbDumpvars(1, cmp_top.dbg_port_chk.dbg_dq_a3i3) ;
`endif
end
else if ($test$plusargs("gate_top"))
begin
$fsdbDumpvars(1,cmp_top.iop);
end
else begin
$fsdbDumpvars(0, cmp_top);
end
end
end
`endif
///////////////////////////////////////////////
// Generate fake OE for DQ and CB pads at DDR0.
///////////////////////////////////////////////
`ifdef RTL_PAD_DDR0
`ifdef GATE_SIM_DRAM
wire ddr0_pad_dqs_oe = cmp_top.iop.pad_ddr0.ddr0_ddr_ch_I0_I0_ddr_6sig0_dqs_pad0_dqs_edgelogic_oe_n ;
`else
wire ddr0_pad_dqs_oe = cmp_top.iop.pad_ddr0.ddr0_ddr_ch.I0.I0.ddr_6sig0.dqs_pad0.dqs_edgelogic.oe ;
wire ddr0_drive_dqs_q = cmp_top.iop.pad_ddr0.ddr0_ddr_ch.I0.I0.ddr_6sig0.dqs_pad0.dqs_edgelogic.drive_dqs_q;
wire ddr0_dqs_read = cmp_top.iop.pad_ddr0.ddr0_ddr_ch.I0.I0.ddr_6sig0.dq_pad0.dq_edgelogic.dqs_read;
`endif
dffrl_async #(1) flop_ddr0_oe(
.din(ddr0_drive_dqs_q),
.q(ddr0_pad_dq_oe),
.rst_l(pwron_rst_l),
.clk(~ddr0_dqs_read), .si(), .so(), .se(1'b0));
wire [127:0] ddr0_dq = ddr0_pad_dqs_oe & ddr0_pad_dq_oe ? cmp_top.DRAM0_DQ :
ddr0_pad_dqs_oe ? 128'hz :
cmp_top.DRAM0_DQ ;
wire [15:0] ddr0_cb = ddr0_pad_dqs_oe & ddr0_pad_dq_oe ? cmp_top.DRAM0_CB :
ddr0_pad_dqs_oe ? 16'hz :
cmp_top.DRAM0_CB;
`endif
///////////////////////////////////////////////
// FOR DDR1
///////////////////////////////////////////////
`ifdef RTL_PAD_DDR1
`ifdef GATE_SIM_DRAM
wire ddr1_pad_dqs_oe = cmp_top.iop.pad_ddr1.ddr1_ddr_ch_b_I0_I0_ddr_6sig0_dqs_pad0_dqs_edgelogic_oe_n ;
`else
wire ddr1_pad_dqs_oe = cmp_top.iop.pad_ddr1.ddr1_ddr_ch_b.I0.I0.ddr_6sig0.dqs_pad0.dqs_edgelogic.oe ;
wire ddr1_drive_dqs_q = cmp_top.iop.pad_ddr1.ddr1_ddr_ch_b.I0.I0.ddr_6sig0.dqs_pad0.dqs_edgelogic.drive_dqs_q;
wire ddr1_dqs_read = cmp_top.iop.pad_ddr1.ddr1_ddr_ch_b.I0.I0.ddr_6sig0.dq_pad0.dq_edgelogic.dqs_read;
`endif
dffrl_async #(1) flop_ddr1_oe(
.din(ddr1_drive_dqs_q),
.q(ddr1_pad_dq_oe),
.rst_l(pwron_rst_l),
.clk(~ddr1_dqs_read), .si(), .so(), .se(1'b0));
wire [127:0] ddr1_dq = ddr1_pad_dqs_oe & ddr1_pad_dq_oe ? cmp_top.DRAM1_DQ :
ddr1_pad_dqs_oe ? 128'hz :
cmp_top.DRAM1_DQ ;
wire [15:0] ddr1_cb = ddr1_pad_dqs_oe & ddr1_pad_dq_oe ? cmp_top.DRAM1_CB :
ddr1_pad_dqs_oe ? 16'hz :
cmp_top.DRAM1_CB;
`endif
///////////////////////////////////////////////
// FOR DDR2
///////////////////////////////////////////////
`ifdef RTL_PAD_DDR2
`ifdef GATE_SIM_DRAM
wire ddr2_pad_dqs_oe = cmp_top.iop.pad_ddr2.ddr2_ddr_ch_I0_I0_ddr_6sig0_dqs_pad0_dqs_edgelogic_oe_n ;
`else
wire ddr2_pad_dqs_oe = cmp_top.iop.pad_ddr2.ddr2_ddr_ch.I0.I0.ddr_6sig0.dqs_pad0.dqs_edgelogic.oe ;
wire ddr2_drive_dqs_q = cmp_top.iop.pad_ddr2.ddr2_ddr_ch.I0.I0.ddr_6sig0.dqs_pad0.dqs_edgelogic.drive_dqs_q;
wire ddr2_dqs_read = cmp_top.iop.pad_ddr2.ddr2_ddr_ch.I0.I0.ddr_6sig0.dq_pad0.dq_edgelogic.dqs_read;
`endif
dffrl_async #(1) flop_ddr2_oe(
.din(ddr2_drive_dqs_q),
.q(ddr2_pad_dq_oe),
.rst_l(pwron_rst_l),
.clk(~ddr2_dqs_read), .si(), .so(), .se(1'b0));
wire [127:0] ddr2_dq = ddr2_pad_dqs_oe & ddr2_pad_dq_oe ? cmp_top.DRAM2_DQ :
ddr2_pad_dqs_oe ? 128'hz :
cmp_top.DRAM2_DQ ;
wire [15:0] ddr2_cb = ddr2_pad_dqs_oe & ddr2_pad_dq_oe ? cmp_top.DRAM2_CB :
ddr2_pad_dqs_oe ? 16'hz :
cmp_top.DRAM2_CB;
`endif
///////////////////////////////////////////////
// FOR DDR3
///////////////////////////////////////////////
`ifdef RTL_PAD_DDR3
`ifdef GATE_SIM_DRAM
wire ddr3_pad_dqs_oe = cmp_top.iop.pad_ddr3.ddr3_ddr_ch_b_I0_I0_ddr_6sig2_dqs_pad0_dqs_edgelogic_oe_n ;
`else
wire ddr3_pad_dqs_oe = cmp_top.iop.pad_ddr3.ddr3_ddr_ch_b.I0.I0.ddr_6sig0.dqs_pad0.dqs_edgelogic.oe ;
wire ddr3_drive_dqs_q = cmp_top.iop.pad_ddr3.ddr3_ddr_ch_b.I0.I0.ddr_6sig0.dqs_pad0.dqs_edgelogic.drive_dqs_q;
wire ddr3_dqs_read = cmp_top.iop.pad_ddr3.ddr3_ddr_ch_b.I0.I0.ddr_6sig0.dq_pad0.dq_edgelogic.dqs_read;
`endif
dffrl_async #(1) flop_ddr3_oe(
.din(ddr3_drive_dqs_q),
.q(ddr3_pad_dq_oe),
.rst_l(pwron_rst_l),
.clk(~ddr3_dqs_read), .si(), .so(), .se(1'b0));
wire [127:0] ddr3_dq = ddr3_pad_dqs_oe & ddr3_pad_dq_oe ? cmp_top.DRAM3_DQ :
ddr3_pad_dqs_oe ? 128'hz :
cmp_top.DRAM3_DQ ;
wire [15:0] ddr3_cb = ddr3_pad_dqs_oe & ddr3_pad_dq_oe ? cmp_top.DRAM3_CB :
ddr3_pad_dqs_oe ? 16'hz :
cmp_top.DRAM3_CB;
`endif
endmodule |
module mt48lc8m16a2 (Dq, Addr, Ba, Clk, Cke, Cs_n, Ras_n, Cas_n, We_n, Dqm);
parameter addr_bits = 12;
parameter data_bits = 16;
parameter col_bits = 9;
parameter mem_sizes = 2097151;
inout [data_bits - 1 : 0] Dq;
input [addr_bits - 1 : 0] Addr;
input [1 : 0] Ba;
input Clk;
input Cke;
input Cs_n;
input Ras_n;
input Cas_n;
input We_n;
input [1 : 0] Dqm;
reg [data_bits - 1 : 0] Bank0 [0 : mem_sizes];
reg [data_bits - 1 : 0] Bank1 [0 : mem_sizes];
reg [data_bits - 1 : 0] Bank2 [0 : mem_sizes];
reg [data_bits - 1 : 0] Bank3 [0 : mem_sizes];
reg [1 : 0] Bank_addr [0 : 3]; // Bank Address Pipeline
reg [col_bits - 1 : 0] Col_addr [0 : 3]; // Column Address Pipeline
reg [3 : 0] Command [0 : 3]; // Command Operation Pipeline
reg [1 : 0] Dqm_reg0, Dqm_reg1; // DQM Operation Pipeline
reg [addr_bits - 1 : 0] B0_row_addr, B1_row_addr, B2_row_addr, B3_row_addr;
reg [addr_bits - 1 : 0] Mode_reg;
reg [data_bits - 1 : 0] Dq_reg, Dq_dqm;
reg [col_bits - 1 : 0] Col_temp, Burst_counter;
reg Act_b0, Act_b1, Act_b2, Act_b3; // Bank Activate
reg Pc_b0, Pc_b1, Pc_b2, Pc_b3; // Bank Precharge
reg [1 : 0] Bank_precharge [0 : 3]; // Precharge Command
reg A10_precharge [0 : 3]; // Addr[10] = 1 (All banks)
reg Auto_precharge [0 : 3]; // RW Auto Precharge (Bank)
reg Read_precharge [0 : 3]; // R Auto Precharge
reg Write_precharge [0 : 3]; // W Auto Precharge
reg RW_interrupt_read [0 : 3]; // RW Interrupt Read with Auto Precharge
reg RW_interrupt_write [0 : 3]; // RW Interrupt Write with Auto Precharge
reg [1 : 0] RW_interrupt_bank; // RW Interrupt Bank
integer RW_interrupt_counter [0 : 3]; // RW Interrupt Counter
integer Count_precharge [0 : 3]; // RW Auto Precharge Counter
reg Data_in_enable;
reg Data_out_enable;
reg [1 : 0] Bank, Prev_bank;
reg [addr_bits - 1 : 0] Row;
reg [col_bits - 1 : 0] Col, Col_brst;
// Internal system clock
reg CkeZ, Sys_clk;
// Commands Decode
wire Active_enable = ~Cs_n & ~Ras_n & Cas_n & We_n;
wire Aref_enable = ~Cs_n & ~Ras_n & ~Cas_n & We_n;
wire Burst_term = ~Cs_n & Ras_n & Cas_n & ~We_n;
wire Mode_reg_enable = ~Cs_n & ~Ras_n & ~Cas_n & ~We_n;
wire Prech_enable = ~Cs_n & ~Ras_n & Cas_n & ~We_n;
wire Read_enable = ~Cs_n & Ras_n & ~Cas_n & We_n;
wire Write_enable = ~Cs_n & Ras_n & ~Cas_n & ~We_n;
// Burst Length Decode
wire Burst_length_1 = ~Mode_reg[2] & ~Mode_reg[1] & ~Mode_reg[0];
wire Burst_length_2 = ~Mode_reg[2] & ~Mode_reg[1] & Mode_reg[0];
wire Burst_length_4 = ~Mode_reg[2] & Mode_reg[1] & ~Mode_reg[0];
wire Burst_length_8 = ~Mode_reg[2] & Mode_reg[1] & Mode_reg[0];
wire Burst_length_f = Mode_reg[2] & Mode_reg[1] & Mode_reg[0];
// CAS Latency Decode
wire Cas_latency_2 = ~Mode_reg[6] & Mode_reg[5] & ~Mode_reg[4];
wire Cas_latency_3 = ~Mode_reg[6] & Mode_reg[5] & Mode_reg[4];
// Write Burst Mode
wire Write_burst_mode = Mode_reg[9];
// wire Debug = 1'b1; // Debug messages : 1 = On
wire Debug = 1'b0; // Debug messages : 1 = On
wire Dq_chk = Sys_clk & Data_in_enable; // Check setup/hold time for DQ
assign Dq = Dq_reg; // DQ buffer
// Commands Operation
`define ACT 0
`define NOP 1
`define READ 2
`define WRITE 3
`define PRECH 4
`define A_REF 5
`define BST 6
`define LMR 7
// Timing Parameters for -7E PC133 CL2
parameter tAC = 5.4;
parameter tHZ = 5.4;
parameter tOH = 3.0;
parameter tMRD = 2.0; // 2 Clk Cycles
parameter tRAS = 37.0;
parameter tRC = 60.0;
parameter tRCD = 15.0;
parameter tRFC = 66.0;
parameter tRP = 15.0;
parameter tRRD = 14.0;
parameter tWRa = 7.0; // A2 Version - Auto precharge mode (1 Clk + 7 ns)
parameter tWRm = 14.0; // A2 Version - Manual precharge mode (14 ns)
// Timing Check variable
time MRD_chk;
time WR_chkm [0 : 3];
time RFC_chk, RRD_chk;
time RC_chk0, RC_chk1, RC_chk2, RC_chk3;
time RAS_chk0, RAS_chk1, RAS_chk2, RAS_chk3;
time RCD_chk0, RCD_chk1, RCD_chk2, RCD_chk3;
time RP_chk0, RP_chk1, RP_chk2, RP_chk3;
initial begin
Dq_reg = {data_bits{1'bz}};
Data_in_enable = 0; Data_out_enable = 0;
Act_b0 = 1; Act_b1 = 1; Act_b2 = 1; Act_b3 = 1;
Pc_b0 = 0; Pc_b1 = 0; Pc_b2 = 0; Pc_b3 = 0;
WR_chkm[0] = 0; WR_chkm[1] = 0; WR_chkm[2] = 0; WR_chkm[3] = 0;
RW_interrupt_read[0] = 0; RW_interrupt_read[1] = 0; RW_interrupt_read[2] = 0; RW_interrupt_read[3] = 0;
RW_interrupt_write[0] = 0; RW_interrupt_write[1] = 0; RW_interrupt_write[2] = 0; RW_interrupt_write[3] = 0;
MRD_chk = 0; RFC_chk = 0; RRD_chk = 0;
RAS_chk0 = 0; RAS_chk1 = 0; RAS_chk2 = 0; RAS_chk3 = 0;
RCD_chk0 = 0; RCD_chk1 = 0; RCD_chk2 = 0; RCD_chk3 = 0;
RC_chk0 = 0; RC_chk1 = 0; RC_chk2 = 0; RC_chk3 = 0;
RP_chk0 = 0; RP_chk1 = 0; RP_chk2 = 0; RP_chk3 = 0;
$timeformat (-9, 1, " ns", 12);
end
// System clock generator
always begin
@ (posedge Clk) begin
Sys_clk = CkeZ;
CkeZ = Cke;
end
@ (negedge Clk) begin
Sys_clk = 1'b0;
end
end
always @ (posedge Sys_clk) begin
// Internal Commamd Pipelined
Command[0] = Command[1];
Command[1] = Command[2];
Command[2] = Command[3];
Command[3] = `NOP;
Col_addr[0] = Col_addr[1];
Col_addr[1] = Col_addr[2];
Col_addr[2] = Col_addr[3];
Col_addr[3] = {col_bits{1'b0}};
Bank_addr[0] = Bank_addr[1];
Bank_addr[1] = Bank_addr[2];
Bank_addr[2] = Bank_addr[3];
Bank_addr[3] = 2'b0;
Bank_precharge[0] = Bank_precharge[1];
Bank_precharge[1] = Bank_precharge[2];
Bank_precharge[2] = Bank_precharge[3];
Bank_precharge[3] = 2'b0;
A10_precharge[0] = A10_precharge[1];
A10_precharge[1] = A10_precharge[2];
A10_precharge[2] = A10_precharge[3];
A10_precharge[3] = 1'b0;
// Dqm pipeline for Read
Dqm_reg0 = Dqm_reg1;
Dqm_reg1 = Dqm;
// Read or Write with Auto Precharge Counter
if (Auto_precharge[0] === 1'b1) begin
Count_precharge[0] = Count_precharge[0] + 1;
end
if (Auto_precharge[1] === 1'b1) begin
Count_precharge[1] = Count_precharge[1] + 1;
end
if (Auto_precharge[2] === 1'b1) begin
Count_precharge[2] = Count_precharge[2] + 1;
end
if (Auto_precharge[3] === 1'b1) begin
Count_precharge[3] = Count_precharge[3] + 1;
end
// Read or Write Interrupt Counter
if (RW_interrupt_write[0] === 1'b1) begin
RW_interrupt_counter[0] = RW_interrupt_counter[0] + 1;
end
if (RW_interrupt_write[1] === 1'b1) begin
RW_interrupt_counter[1] = RW_interrupt_counter[1] + 1;
end
if (RW_interrupt_write[2] === 1'b1) begin
RW_interrupt_counter[2] = RW_interrupt_counter[2] + 1;
end
if (RW_interrupt_write[3] === 1'b1) begin
RW_interrupt_counter[3] = RW_interrupt_counter[3] + 1;
end
// tMRD Counter
MRD_chk = MRD_chk + 1;
// Auto Refresh
if (Aref_enable === 1'b1) begin
if (Debug) begin
$display ("%m : at time %t AREF : Auto Refresh", $time);
end
// Auto Refresh to Auto Refresh
if ($time - RFC_chk < tRFC) begin
$display ("%m : at time %t ERROR: tRFC violation during Auto Refresh", $time);
end
// Precharge to Auto Refresh
if (($time - RP_chk0 < tRP) || ($time - RP_chk1 < tRP) ||
($time - RP_chk2 < tRP) || ($time - RP_chk3 < tRP)) begin
$display ("%m : at time %t ERROR: tRP violation during Auto Refresh", $time);
end
// Precharge to Refresh
if (Pc_b0 === 1'b0 || Pc_b1 === 1'b0 || Pc_b2 === 1'b0 || Pc_b3 === 1'b0) begin
$display ("%m : at time %t ERROR: All banks must be Precharge before Auto Refresh", $time);
end
// Load Mode Register to Auto Refresh
if (MRD_chk < tMRD) begin
$display ("%m : at time %t ERROR: tMRD violation during Auto Refresh", $time);
end
// Record Current tRFC time
RFC_chk = $time;
end
// Load Mode Register
if (Mode_reg_enable === 1'b1) begin
// Register Mode
Mode_reg = Addr;
// Decode CAS Latency, Burst Length, Burst Type, and Write Burst Mode
if (Debug) begin
$display ("%m : at time %t LMR : Load Mode Register", $time);
// CAS Latency
case (Addr[6 : 4])
3'b010 : $display ("%m : CAS Latency = 2");
3'b011 : $display ("%m : CAS Latency = 3");
default : $display ("%m : CAS Latency = Reserved");
endcase
// Burst Length
case (Addr[2 : 0])
3'b000 : $display ("%m : Burst Length = 1");
3'b001 : $display ("%m : Burst Length = 2");
3'b010 : $display ("%m : Burst Length = 4");
3'b011 : $display ("%m : Burst Length = 8");
3'b111 : $display ("%m : Burst Length = Full");
default : $display ("%m : Burst Length = Reserved");
endcase
// Burst Type
if (Addr[3] === 1'b0) begin
$display ("%m : Burst Type = Sequential");
end else if (Addr[3] === 1'b1) begin
$display ("%m : Burst Type = Interleaved");
end else begin
$display ("%m : Burst Type = Reserved");
end
// Write Burst Mode
if (Addr[9] === 1'b0) begin
$display ("%m : Write Burst Mode = Programmed Burst Length");
end else if (Addr[9] === 1'b1) begin
$display ("%m : Write Burst Mode = Single Location Access");
end else begin
$display ("%m : Write Burst Mode = Reserved");
end
end
// Precharge to Load Mode Register
if (Pc_b0 === 1'b0 && Pc_b1 === 1'b0 && Pc_b2 === 1'b0 && Pc_b3 === 1'b0) begin
$display ("%m : at time %t ERROR: all banks must be Precharge before Load Mode Register", $time);
end
// Precharge to Load Mode Register
if (($time - RP_chk0 < tRP) || ($time - RP_chk1 < tRP) ||
($time - RP_chk2 < tRP) || ($time - RP_chk3 < tRP)) begin
$display ("%m : at time %t ERROR: tRP violation during Load Mode Register", $time);
end
// Auto Refresh to Load Mode Register
if ($time - RFC_chk < tRFC) begin
$display ("%m : at time %t ERROR: tRFC violation during Load Mode Register", $time);
end
// Load Mode Register to Load Mode Register
if (MRD_chk < tMRD) begin
$display ("%m : at time %t ERROR: tMRD violation during Load Mode Register", $time);
end
// Reset MRD Counter
MRD_chk = 0;
end
// Active Block (Latch Bank Address and Row Address)
if (Active_enable === 1'b1) begin
// Activate an open bank can corrupt data
if ((Ba === 2'b00 && Act_b0 === 1'b1) || (Ba === 2'b01 && Act_b1 === 1'b1) ||
(Ba === 2'b10 && Act_b2 === 1'b1) || (Ba === 2'b11 && Act_b3 === 1'b1)) begin
$display ("%m : at time %t ERROR: Bank already activated -- data can be corrupted", $time);
$stop; // JEA debug
end
// Activate Bank 0
if (Ba === 2'b00 && Pc_b0 === 1'b1) begin
// Debug Message
if (Debug) begin
$display ("%m : at time %t ACT : Bank = 0 Row = %d", $time, Addr);
end
// ACTIVE to ACTIVE command period
if ($time - RC_chk0 < tRC) begin
$display ("%m : at time %t ERROR: tRC violation during Activate bank 0", $time);
end
// Precharge to Activate Bank 0
if ($time - RP_chk0 < tRP) begin
$display ("%m : at time %t ERROR: tRP violation during Activate bank 0", $time);
end
// Record variables
Act_b0 = 1'b1;
Pc_b0 = 1'b0;
B0_row_addr = Addr [addr_bits - 1 : 0];
RAS_chk0 = $time;
RC_chk0 = $time;
RCD_chk0 = $time;
end
if (Ba == 2'b01 && Pc_b1 == 1'b1) begin
// Debug Message
if (Debug) begin
$display ("%m : at time %t ACT : Bank = 1 Row = %d", $time, Addr);
end
// ACTIVE to ACTIVE command period
if ($time - RC_chk1 < tRC) begin
$display ("%m : at time %t ERROR: tRC violation during Activate bank 1", $time);
end
// Precharge to Activate Bank 1
if ($time - RP_chk1 < tRP) begin
$display ("%m : at time %t ERROR: tRP violation during Activate bank 1", $time);
end
// Record variables
Act_b1 = 1'b1;
Pc_b1 = 1'b0;
B1_row_addr = Addr [addr_bits - 1 : 0];
RAS_chk1 = $time;
RC_chk1 = $time;
RCD_chk1 = $time;
end
if (Ba == 2'b10 && Pc_b2 == 1'b1) begin
// Debug Message
if (Debug) begin
$display ("%m : at time %t ACT : Bank = 2 Row = %d", $time, Addr);
end
// ACTIVE to ACTIVE command period
if ($time - RC_chk2 < tRC) begin
$display ("%m : at time %t ERROR: tRC violation during Activate bank 2", $time);
end
// Precharge to Activate Bank 2
if ($time - RP_chk2 < tRP) begin
$display ("%m : at time %t ERROR: tRP violation during Activate bank 2", $time);
end
// Record variables
Act_b2 = 1'b1;
Pc_b2 = 1'b0;
B2_row_addr = Addr [addr_bits - 1 : 0];
RAS_chk2 = $time;
RC_chk2 = $time;
RCD_chk2 = $time;
end
if (Ba == 2'b11 && Pc_b3 == 1'b1) begin
// Debug Message
if (Debug) begin
$display ("%m : at time %t ACT : Bank = 3 Row = %d", $time, Addr);
end
// ACTIVE to ACTIVE command period
if ($time - RC_chk3 < tRC) begin
$display ("%m : at time %t ERROR: tRC violation during Activate bank 3", $time);
end
// Precharge to Activate Bank 3
if ($time - RP_chk3 < tRP) begin
$display ("%m : at time %t ERROR: tRP violation during Activate bank 3", $time);
end
// Record variables
Act_b3 = 1'b1;
Pc_b3 = 1'b0;
B3_row_addr = Addr [addr_bits - 1 : 0];
RAS_chk3 = $time;
RC_chk3 = $time;
RCD_chk3 = $time;
end
// Active Bank A to Active Bank B
if ((Prev_bank != Ba) && ($time - RRD_chk < tRRD)) begin
$display ("%m : at time %t ERROR: tRRD violation during Activate bank = %d", $time, Ba);
end
// Auto Refresh to Activate
if ($time - RFC_chk < tRFC) begin
$display ("%m : at time %t ERROR: tRFC violation during Activate bank = %d", $time, Ba);
end
// Load Mode Register to Active
if (MRD_chk < tMRD ) begin
$display ("%m : at time %t ERROR: tMRD violation during Activate bank = %d", $time, Ba);
end
// Record variables for checking violation
RRD_chk = $time;
Prev_bank = Ba;
end
// Precharge Block
if (Prech_enable == 1'b1) begin
// Load Mode Register to Precharge
if ($time - MRD_chk < tMRD) begin
$display ("%m : at time %t ERROR: tMRD violaiton during Precharge", $time);
end
// Precharge Bank 0
if ((Addr[10] === 1'b1 || (Addr[10] === 1'b0 && Ba === 2'b00)) && Act_b0 === 1'b1) begin
Act_b0 = 1'b0;
Pc_b0 = 1'b1;
RP_chk0 = $time;
// Activate to Precharge
if ($time - RAS_chk0 < tRAS) begin
$display ("%m : at time %t ERROR: tRAS violation during Precharge", $time);
end
// tWR violation check for write
if ($time - WR_chkm[0] < tWRm) begin
$display ("%m : at time %t ERROR: tWR violation during Precharge", $time);
end
end
// Precharge Bank 1
if ((Addr[10] === 1'b1 || (Addr[10] === 1'b0 && Ba === 2'b01)) && Act_b1 === 1'b1) begin
Act_b1 = 1'b0;
Pc_b1 = 1'b1;
RP_chk1 = $time;
// Activate to Precharge
if ($time - RAS_chk1 < tRAS) begin
$display ("%m : at time %t ERROR: tRAS violation during Precharge", $time);
end
// tWR violation check for write
if ($time - WR_chkm[1] < tWRm) begin
$display ("%m : at time %t ERROR: tWR violation during Precharge", $time);
end
end
// Precharge Bank 2
if ((Addr[10] === 1'b1 || (Addr[10] === 1'b0 && Ba === 2'b10)) && Act_b2 === 1'b1) begin
Act_b2 = 1'b0;
Pc_b2 = 1'b1;
RP_chk2 = $time;
// Activate to Precharge
if ($time - RAS_chk2 < tRAS) begin
$display ("%m : at time %t ERROR: tRAS violation during Precharge", $time);
end
// tWR violation check for write
if ($time - WR_chkm[2] < tWRm) begin
$display ("%m : at time %t ERROR: tWR violation during Precharge", $time);
end
end
// Precharge Bank 3
if ((Addr[10] === 1'b1 || (Addr[10] === 1'b0 && Ba === 2'b11)) && Act_b3 === 1'b1) begin
Act_b3 = 1'b0;
Pc_b3 = 1'b1;
RP_chk3 = $time;
// Activate to Precharge
if ($time - RAS_chk3 < tRAS) begin
$display ("%m : at time %t ERROR: tRAS violation during Precharge", $time);
end
// tWR violation check for write
if ($time - WR_chkm[3] < tWRm) begin
$display ("%m : at time %t ERROR: tWR violation during Precharge", $time);
end
end
// Terminate a Write Immediately (if same bank or all banks)
if (Data_in_enable === 1'b1 && (Bank === Ba || Addr[10] === 1'b1)) begin
Data_in_enable = 1'b0;
end
// Precharge Command Pipeline for Read
if (Cas_latency_3 === 1'b1) begin
Command[2] = `PRECH;
Bank_precharge[2] = Ba;
A10_precharge[2] = Addr[10];
end else if (Cas_latency_2 === 1'b1) begin
Command[1] = `PRECH;
Bank_precharge[1] = Ba;
A10_precharge[1] = Addr[10];
end
end
// Burst terminate
if (Burst_term === 1'b1) begin
// Terminate a Write Immediately
if (Data_in_enable == 1'b1) begin
Data_in_enable = 1'b0;
end
// Terminate a Read Depend on CAS Latency
if (Cas_latency_3 === 1'b1) begin
Command[2] = `BST;
end else if (Cas_latency_2 == 1'b1) begin
Command[1] = `BST;
end
// Display debug message
if (Debug) begin
$display ("%m : at time %t BST : Burst Terminate",$time);
end
end
// Read, Write, Column Latch
if (Read_enable === 1'b1) begin
// Check to see if bank is open (ACT)
if ((Ba == 2'b00 && Pc_b0 == 1'b1) || (Ba == 2'b01 && Pc_b1 == 1'b1) ||
(Ba == 2'b10 && Pc_b2 == 1'b1) || (Ba == 2'b11 && Pc_b3 == 1'b1)) begin
$display("%m : at time %t ERROR: Bank is not Activated for Read", $time);
end
// Activate to Read or Write
if ((Ba == 2'b00) && ($time - RCD_chk0 < tRCD) ||
(Ba == 2'b01) && ($time - RCD_chk1 < tRCD) ||
(Ba == 2'b10) && ($time - RCD_chk2 < tRCD) ||
(Ba == 2'b11) && ($time - RCD_chk3 < tRCD)) begin
$display("%m : at time %t ERROR: tRCD violation during Read", $time);
end
// CAS Latency pipeline
if (Cas_latency_3 == 1'b1) begin
Command[2] = `READ;
Col_addr[2] = Addr;
Bank_addr[2] = Ba;
end else if (Cas_latency_2 == 1'b1) begin
Command[1] = `READ;
Col_addr[1] = Addr;
Bank_addr[1] = Ba;
end
// Read interrupt Write (terminate Write immediately)
if (Data_in_enable == 1'b1) begin
Data_in_enable = 1'b0;
// Interrupting a Write with Autoprecharge
if (Auto_precharge[RW_interrupt_bank] == 1'b1 && Write_precharge[RW_interrupt_bank] == 1'b1) begin
RW_interrupt_write[RW_interrupt_bank] = 1'b1;
RW_interrupt_counter[RW_interrupt_bank] = 0;
// Display debug message
if (Debug) begin
$display ("%m : at time %t NOTE : Read interrupt Write with Autoprecharge", $time);
end
end
end
// Write with Auto Precharge
if (Addr[10] == 1'b1) begin
Auto_precharge[Ba] = 1'b1;
Count_precharge[Ba] = 0;
RW_interrupt_bank = Ba;
Read_precharge[Ba] = 1'b1;
end
end
// Write Command
if (Write_enable == 1'b1) begin
// Activate to Write
if ((Ba == 2'b00 && Pc_b0 == 1'b1) || (Ba == 2'b01 && Pc_b1 == 1'b1) ||
(Ba == 2'b10 && Pc_b2 == 1'b1) || (Ba == 2'b11 && Pc_b3 == 1'b1)) begin
$display("%m : at time %t ERROR: Bank is not Activated for Write", $time);
end
// Activate to Read or Write
if ((Ba == 2'b00) && ($time - RCD_chk0 < tRCD) ||
(Ba == 2'b01) && ($time - RCD_chk1 < tRCD) ||
(Ba == 2'b10) && ($time - RCD_chk2 < tRCD) ||
(Ba == 2'b11) && ($time - RCD_chk3 < tRCD)) begin
$display("%m : at time %t ERROR: tRCD violation during Read", $time);
end
// Latch Write command, Bank, and Column
Command[0] = `WRITE;
Col_addr[0] = Addr;
Bank_addr[0] = Ba;
// Write interrupt Write (terminate Write immediately)
if (Data_in_enable == 1'b1) begin
Data_in_enable = 1'b0;
// Interrupting a Write with Autoprecharge
if (Auto_precharge[RW_interrupt_bank] == 1'b1 && Write_precharge[RW_interrupt_bank] == 1'b1) begin
RW_interrupt_write[RW_interrupt_bank] = 1'b1;
// Display debug message
if (Debug) begin
$display ("%m : at time %t NOTE : Read Bank %d interrupt Write Bank %d with Autoprecharge", $time, Ba, RW_interrupt_bank);
end
end
end
// Write interrupt Read (terminate Read immediately)
if (Data_out_enable == 1'b1) begin
Data_out_enable = 1'b0;
// Interrupting a Read with Autoprecharge
if (Auto_precharge[RW_interrupt_bank] == 1'b1 && Read_precharge[RW_interrupt_bank] == 1'b1) begin
RW_interrupt_read[RW_interrupt_bank] = 1'b1;
// Display debug message
if (Debug) begin
$display ("%m : at time %t NOTE : Write Bank %d interrupt Read Bank %d with Autoprecharge", $time, Ba, RW_interrupt_bank);
end
end
end
// Write with Auto Precharge
if (Addr[10] == 1'b1) begin
Auto_precharge[Ba] = 1'b1;
Count_precharge[Ba] = 0;
RW_interrupt_bank = Ba;
Write_precharge[Ba] = 1'b1;
end
end
/*
Write with Auto Precharge Calculation
The device start internal precharge when:
1. Meet minimum tRAS requirement
and 2. tWR cycle(s) after last valid data
or 3. Interrupt by a Read or Write (with or without Auto Precharge)
Note: Model is starting the internal precharge 1 cycle after they meet all the
requirement but tRP will be compensate for the time after the 1 cycle.
*/
if ((Auto_precharge[0] == 1'b1) && (Write_precharge[0] == 1'b1)) begin
if ((($time - RAS_chk0 >= tRAS) && // Case 1
(((Burst_length_1 == 1'b1 || Write_burst_mode == 1'b1) && Count_precharge [0] >= 1) || // Case 2
(Burst_length_2 == 1'b1 && Count_precharge [0] >= 2) ||
(Burst_length_4 == 1'b1 && Count_precharge [0] >= 4) ||
(Burst_length_8 == 1'b1 && Count_precharge [0] >= 8))) ||
(RW_interrupt_write[0] == 1'b1 && RW_interrupt_counter[0] >= 1)) begin // Case 3
Auto_precharge[0] = 1'b0;
Write_precharge[0] = 1'b0;
RW_interrupt_write[0] = 1'b0;
Pc_b0 = 1'b1;
Act_b0 = 1'b0;
RP_chk0 = $time + tWRa;
if (Debug) begin
$display ("%m : at time %t NOTE : Start Internal Auto Precharge for Bank 0", $time);
end
end
end
if ((Auto_precharge[1] == 1'b1) && (Write_precharge[1] == 1'b1)) begin
if ((($time - RAS_chk1 >= tRAS) && // Case 1
(((Burst_length_1 == 1'b1 || Write_burst_mode == 1'b1) && Count_precharge [1] >= 1) || // Case 2
(Burst_length_2 == 1'b1 && Count_precharge [1] >= 2) ||
(Burst_length_4 == 1'b1 && Count_precharge [1] >= 4) ||
(Burst_length_8 == 1'b1 && Count_precharge [1] >= 8))) ||
(RW_interrupt_write[1] == 1'b1 && RW_interrupt_counter[1] >= 1)) begin // Case 3
Auto_precharge[1] = 1'b0;
Write_precharge[1] = 1'b0;
RW_interrupt_write[1] = 1'b0;
Pc_b1 = 1'b1;
Act_b1 = 1'b0;
RP_chk1 = $time + tWRa;
if (Debug) begin
$display ("%m : at time %t NOTE : Start Internal Auto Precharge for Bank 1", $time);
end
end
end
if ((Auto_precharge[2] == 1'b1) && (Write_precharge[2] == 1'b1)) begin
if ((($time - RAS_chk2 >= tRAS) && // Case 1
(((Burst_length_1 == 1'b1 || Write_burst_mode == 1'b1) && Count_precharge [2] >= 1) || // Case 2
(Burst_length_2 == 1'b1 && Count_precharge [2] >= 2) ||
(Burst_length_4 == 1'b1 && Count_precharge [2] >= 4) ||
(Burst_length_8 == 1'b1 && Count_precharge [2] >= 8))) ||
(RW_interrupt_write[2] == 1'b1 && RW_interrupt_counter[2] >= 1)) begin // Case 3
Auto_precharge[2] = 1'b0;
Write_precharge[2] = 1'b0;
RW_interrupt_write[2] = 1'b0;
Pc_b2 = 1'b1;
Act_b2 = 1'b0;
RP_chk2 = $time + tWRa;
if (Debug) begin
$display ("%m : at time %t NOTE : Start Internal Auto Precharge for Bank 2", $time);
end
end
end
if ((Auto_precharge[3] == 1'b1) && (Write_precharge[3] == 1'b1)) begin
if ((($time - RAS_chk3 >= tRAS) && // Case 1
(((Burst_length_1 == 1'b1 || Write_burst_mode == 1'b1) && Count_precharge [3] >= 1) || // Case 2
(Burst_length_2 == 1'b1 && Count_precharge [3] >= 2) ||
(Burst_length_4 == 1'b1 && Count_precharge [3] >= 4) ||
(Burst_length_8 == 1'b1 && Count_precharge [3] >= 8))) ||
(RW_interrupt_write[3] == 1'b1 && RW_interrupt_counter[3] >= 1)) begin // Case 3
Auto_precharge[3] = 1'b0;
Write_precharge[3] = 1'b0;
RW_interrupt_write[3] = 1'b0;
Pc_b3 = 1'b1;
Act_b3 = 1'b0;
RP_chk3 = $time + tWRa;
if (Debug) begin
$display ("%m : at time %t NOTE : Start Internal Auto Precharge for Bank 3", $time);
end
end
end
// Read with Auto Precharge Calculation
// The device start internal precharge:
// 1. Meet minimum tRAS requirement
// and 2. CAS Latency - 1 cycles before last burst
// or 3. Interrupt by a Read or Write (with or without AutoPrecharge)
if ((Auto_precharge[0] == 1'b1) && (Read_precharge[0] == 1'b1)) begin
if ((($time - RAS_chk0 >= tRAS) && // Case 1
((Burst_length_1 == 1'b1 && Count_precharge[0] >= 1) || // Case 2
(Burst_length_2 == 1'b1 && Count_precharge[0] >= 2) ||
(Burst_length_4 == 1'b1 && Count_precharge[0] >= 4) ||
(Burst_length_8 == 1'b1 && Count_precharge[0] >= 8))) ||
(RW_interrupt_read[0] == 1'b1)) begin // Case 3
Pc_b0 = 1'b1;
Act_b0 = 1'b0;
RP_chk0 = $time;
Auto_precharge[0] = 1'b0;
Read_precharge[0] = 1'b0;
RW_interrupt_read[0] = 1'b0;
if (Debug) begin
$display ("%m : at time %t NOTE : Start Internal Auto Precharge for Bank 0", $time);
end
end
end
if ((Auto_precharge[1] == 1'b1) && (Read_precharge[1] == 1'b1)) begin
if ((($time - RAS_chk1 >= tRAS) &&
((Burst_length_1 == 1'b1 && Count_precharge[1] >= 1) ||
(Burst_length_2 == 1'b1 && Count_precharge[1] >= 2) ||
(Burst_length_4 == 1'b1 && Count_precharge[1] >= 4) ||
(Burst_length_8 == 1'b1 && Count_precharge[1] >= 8))) ||
(RW_interrupt_read[1] == 1'b1)) begin
Pc_b1 = 1'b1;
Act_b1 = 1'b0;
RP_chk1 = $time;
Auto_precharge[1] = 1'b0;
Read_precharge[1] = 1'b0;
RW_interrupt_read[1] = 1'b0;
if (Debug) begin
$display ("%m : at time %t NOTE : Start Internal Auto Precharge for Bank 1", $time);
end
end
end
if ((Auto_precharge[2] == 1'b1) && (Read_precharge[2] == 1'b1)) begin
if ((($time - RAS_chk2 >= tRAS) &&
((Burst_length_1 == 1'b1 && Count_precharge[2] >= 1) ||
(Burst_length_2 == 1'b1 && Count_precharge[2] >= 2) ||
(Burst_length_4 == 1'b1 && Count_precharge[2] >= 4) ||
(Burst_length_8 == 1'b1 && Count_precharge[2] >= 8))) ||
(RW_interrupt_read[2] == 1'b1)) begin
Pc_b2 = 1'b1;
Act_b2 = 1'b0;
RP_chk2 = $time;
Auto_precharge[2] = 1'b0;
Read_precharge[2] = 1'b0;
RW_interrupt_read[2] = 1'b0;
if (Debug) begin
$display ("%m : at time %t NOTE : Start Internal Auto Precharge for Bank 2", $time);
end
end
end
if ((Auto_precharge[3] == 1'b1) && (Read_precharge[3] == 1'b1)) begin
if ((($time - RAS_chk3 >= tRAS) &&
((Burst_length_1 == 1'b1 && Count_precharge[3] >= 1) ||
(Burst_length_2 == 1'b1 && Count_precharge[3] >= 2) ||
(Burst_length_4 == 1'b1 && Count_precharge[3] >= 4) ||
(Burst_length_8 == 1'b1 && Count_precharge[3] >= 8))) ||
(RW_interrupt_read[3] == 1'b1)) begin
Pc_b3 = 1'b1;
Act_b3 = 1'b0;
RP_chk3 = $time;
Auto_precharge[3] = 1'b0;
Read_precharge[3] = 1'b0;
RW_interrupt_read[3] = 1'b0;
if (Debug) begin
$display("%m : at time %t NOTE : Start Internal Auto Precharge for Bank 3", $time);
end
end
end
// Internal Precharge or Bst
if (Command[0] == `PRECH) begin // Precharge terminate a read with same bank or all banks
if (Bank_precharge[0] == Bank || A10_precharge[0] == 1'b1) begin
if (Data_out_enable == 1'b1) begin
Data_out_enable = 1'b0;
end
end
end else if (Command[0] == `BST) begin // BST terminate a read to current bank
if (Data_out_enable == 1'b1) begin
Data_out_enable = 1'b0;
end
end
if (Data_out_enable == 1'b0) begin
Dq_reg <= #tOH {data_bits{1'bz}};
end
// Detect Read or Write command
if (Command[0] == `READ) begin
Bank = Bank_addr[0];
Col = Col_addr[0];
Col_brst = Col_addr[0];
case (Bank_addr[0])
2'b00 : Row = B0_row_addr;
2'b01 : Row = B1_row_addr;
2'b10 : Row = B2_row_addr;
2'b11 : Row = B3_row_addr;
endcase
Burst_counter = 0;
Data_in_enable = 1'b0;
Data_out_enable = 1'b1;
end else if (Command[0] == `WRITE) begin
Bank = Bank_addr[0];
Col = Col_addr[0];
Col_brst = Col_addr[0];
case (Bank_addr[0])
2'b00 : Row = B0_row_addr;
2'b01 : Row = B1_row_addr;
2'b10 : Row = B2_row_addr;
2'b11 : Row = B3_row_addr;
endcase
Burst_counter = 0;
Data_in_enable = 1'b1;
Data_out_enable = 1'b0;
end
// DQ buffer (Driver/Receiver)
if (Data_in_enable == 1'b1) begin // Writing Data to Memory
// Array buffer
case (Bank)
2'b00 : Dq_dqm = Bank0 [{Row, Col}];
2'b01 : Dq_dqm = Bank1 [{Row, Col}];
2'b10 : Dq_dqm = Bank2 [{Row, Col}];
2'b11 : Dq_dqm = Bank3 [{Row, Col}];
endcase
// Dqm operation
if (Dqm[0] == 1'b0) begin
Dq_dqm [ 7 : 0] = Dq [ 7 : 0];
end
if (Dqm[1] == 1'b0) begin
Dq_dqm [15 : 8] = Dq [15 : 8];
end
// Write to memory
case (Bank)
2'b00 : Bank0 [{Row, Col}] = Dq_dqm;
2'b01 : Bank1 [{Row, Col}] = Dq_dqm;
2'b10 : Bank2 [{Row, Col}] = Dq_dqm;
2'b11 : Bank3 [{Row, Col}] = Dq_dqm;
endcase
// Display debug message
if (Dqm !== 2'b11) begin
// Record tWR for manual precharge
WR_chkm [Bank] = $time;
if (Debug) begin
$display("%m : at time %t WRITE: Bank = %d Row = %d, Col = %d, Data = %d", $time, Bank, Row, Col, Dq_dqm);
end
end else begin
if (Debug) begin
$display("%m : at time %t WRITE: Bank = %d Row = %d, Col = %d, Data = Hi-Z due to DQM", $time, Bank, Row, Col);
end
end
// Advance burst counter subroutine
#tHZ Burst_decode;
end else if (Data_out_enable == 1'b1) begin // Reading Data from Memory
// Array buffer
case (Bank)
2'b00 : Dq_dqm = Bank0[{Row, Col}];
2'b01 : Dq_dqm = Bank1[{Row, Col}];
2'b10 : Dq_dqm = Bank2[{Row, Col}];
2'b11 : Dq_dqm = Bank3[{Row, Col}];
endcase
// Dqm operation
if (Dqm_reg0 [0] == 1'b1) begin
Dq_dqm [ 7 : 0] = 8'bz;
end
if (Dqm_reg0 [1] == 1'b1) begin
Dq_dqm [15 : 8] = 8'bz;
end
// Display debug message
if (Dqm_reg0 !== 2'b11) begin
Dq_reg = #tAC Dq_dqm;
if (Debug) begin
$display("%m : at time %t READ : Bank = %d Row = %d, Col = %d, Data = %d", $time, Bank, Row, Col, Dq_reg);
end
end else begin
Dq_reg = #tHZ {data_bits{1'bz}};
if (Debug) begin
$display("%m : at time %t READ : Bank = %d Row = %d, Col = %d, Data = Hi-Z due to DQM", $time, Bank, Row, Col);
end
end
// Advance burst counter subroutine
Burst_decode;
end
end
// Burst counter decode
task Burst_decode;
begin
// Advance Burst Counter
Burst_counter = Burst_counter + 1;
// Burst Type
if (Mode_reg[3] == 1'b0) begin // Sequential Burst
Col_temp = Col + 1;
end else if (Mode_reg[3] == 1'b1) begin // Interleaved Burst
Col_temp[2] = Burst_counter[2] ^ Col_brst[2];
Col_temp[1] = Burst_counter[1] ^ Col_brst[1];
Col_temp[0] = Burst_counter[0] ^ Col_brst[0];
end
// Burst Length
if (Burst_length_2) begin // Burst Length = 2
Col [0] = Col_temp [0];
end else if (Burst_length_4) begin // Burst Length = 4
Col [1 : 0] = Col_temp [1 : 0];
end else if (Burst_length_8) begin // Burst Length = 8
Col [2 : 0] = Col_temp [2 : 0];
end else begin // Burst Length = FULL
Col = Col_temp;
end
// Burst Read Single Write
if (Write_burst_mode == 1'b1) begin
Data_in_enable = 1'b0;
end
// Data Counter
if (Burst_length_1 == 1'b1) begin
if (Burst_counter >= 1) begin
Data_in_enable = 1'b0;
Data_out_enable = 1'b0;
end
end else if (Burst_length_2 == 1'b1) begin
if (Burst_counter >= 2) begin
Data_in_enable = 1'b0;
Data_out_enable = 1'b0;
end
end else if (Burst_length_4 == 1'b1) begin
if (Burst_counter >= 4) begin
Data_in_enable = 1'b0;
Data_out_enable = 1'b0;
end
end else if (Burst_length_8 == 1'b1) begin
if (Burst_counter >= 8) begin
Data_in_enable = 1'b0;
Data_out_enable = 1'b0;
end
end
end
endtask
// // Timing Parameters for -7E (133 MHz @ CL2)
// specify
// specparam
// tAH = 0.8, // Addr, Ba Hold Time
// tAS = 1.5, // Addr, Ba Setup Time
// tCH = 2.5, // Clock High-Level Width
// tCL = 2.5, // Clock Low-Level Width
// tCK = 7.0, // Clock Cycle Time
// tDH = 0.8, // Data-in Hold Time
// tDS = 1.5, // Data-in Setup Time
// tCKH = 0.8, // CKE Hold Time
// tCKS = 1.5, // CKE Setup Time
// tCMH = 0.8, // CS#, RAS#, CAS#, WE#, DQM# Hold Time
// tCMS = 1.5; // CS#, RAS#, CAS#, WE#, DQM# Setup Time
// $width (posedge Clk, tCH);
// $width (negedge Clk, tCL);
// $period (negedge Clk, tCK);
// $period (posedge Clk, tCK);
// $setuphold(posedge Clk, Cke, tCKS, tCKH);
// $setuphold(posedge Clk, Cs_n, tCMS, tCMH);
// $setuphold(posedge Clk, Cas_n, tCMS, tCMH);
// $setuphold(posedge Clk, Ras_n, tCMS, tCMH);
// $setuphold(posedge Clk, We_n, tCMS, tCMH);
// $setuphold(posedge Clk, Addr, tAS, tAH);
// $setuphold(posedge Clk, Ba, tAS, tAH);
// $setuphold(posedge Clk, Dqm, tCMS, tCMH);
// $setuphold(posedge Dq_chk, Dq, tDS, tDH);
// endspecify
endmodule |
module test();
typedef logic [7:0] pa08;
typedef pa08 [1:0] pa16;
typedef pa16 [1:0] pa32;
typedef pa32 [1:0] pa64;
// variables used in casting
pa08 var_08;
pa16 var_16;
pa32 var_32;
pa64 var_64;
real var_real;
// error counter
bit err = 0;
initial begin
var_08 = pa08'(4'h5); if (var_08 !== 8'h05) begin $display("FAILED -- var_08 = 'h%0h != 8'h05", var_08); err=1; end
var_16 = pa16'(var_08); if (var_16 !== 16'h05) begin $display("FAILED -- var_16 = 'h%0h != 16'h05", var_16); err=1; end
var_32 = pa32'(var_16); if (var_32 !== 32'h05) begin $display("FAILED -- var_32 = 'h%0h != 32'h05", var_32); err=1; end
var_64 = pa64'(var_32); if (var_64 !== 64'h05) begin $display("FAILED -- var_64 = 'h%0h != 64'h05", var_64); err=1; end
var_real = 13.4; var_08 = pa08'(var_real); if (var_08 !== 13) begin $display("FAILED -- var_08 = %d != 13", var_08); err=1; end
var_real = 14.5; var_16 = pa16'(var_real); if (var_16 !== 15) begin $display("FAILED -- var_16 = %d != 15", var_16); err=1; end
var_real = 15.6; var_32 = pa32'(var_real); if (var_32 !== 16) begin $display("FAILED -- var_32 = %d != 16", var_32); err=1; end
var_real = -15.6; var_64 = pa64'(var_real); if (var_64 !== -16) begin $display("FAILED -- var_64 = %d != -16", var_64); err=1; end
var_08 = pa08'(4'hf); if (var_08 !== 8'h0f) begin $display("FAILED -- var_08 = 'h%0h != 8'h0f", var_08); err=1; end
var_16 = pa08'(16'h0f0f); if (var_16 !== 16'h0f) begin $display("FAILED -- var_16 = 'h%0h != 16'h0f", var_16); err=1; end
if (!err) $display("PASSED");
end
endmodule |
module
fdct #(coef_width, di_width, 12)
fdct_zigzag(
.clk(clk),
.ena(ena),
.rst(rst),
.dstrb(dstrb),
.din(din),
.dout(fdct_dout),
.douten(fdct_doe)
);
// delay 'fdct_dout' => wait for synchronous quantization RAM/ROM
always @(posedge clk)
if(ena)
dfdct_dout <= #1 fdct_dout;
// Hookup QNR (Quantization and Rounding) unit
jpeg_qnr
qnr(
.clk(clk),
.ena(ena),
.rst(rst),
.dstrb(fdct_doe),
.din(dfdct_dout),
.qnt_val(qnt_val),
.qnt_cnt(qnt_cnt),
.dout(qnr_dout),
.douten(qnr_doe)
);
// delay douten 1 clk_cycle => account for delayed fdct_res & qnt_val
always @(posedge clk)
if(ena)
dqnr_doe <= #1 qnr_doe;
//
// TODO: Insert DC differential generator here.
//
wire [11:0] dc_diff_dout = {qnr_dout[10], qnr_dout};
wire dc_diff_doe = dqnr_doe;
// Hookup Run Length Encoder
jpeg_rle
rle(
.clk(clk),
.ena(ena),
.rst(rst),
.dstrb(dc_diff_doe),
.din(dc_diff_dout),
.size(size),
.rlen(rlen),
.amp(amp),
.douten(douten),
.bstart()
);
endmodule |
module
dct #(coef_width, di_width, do_width)
dct_mod(
.clk(clk),
.ena(ena),
.rst(rst),
.dstrb(dstrb),
.din(din),
.dout_00(res00),
.dout_01(res01),
.dout_02(res02),
.dout_03(res03),
.dout_04(res04),
.dout_05(res05),
.dout_06(res06),
.dout_07(res07),
.dout_10(res10),
.dout_11(res11),
.dout_12(res12),
.dout_13(res13),
.dout_14(res14),
.dout_15(res15),
.dout_16(res16),
.dout_17(res17),
.dout_20(res20),
.dout_21(res21),
.dout_22(res22),
.dout_23(res23),
.dout_24(res24),
.dout_25(res25),
.dout_26(res26),
.dout_27(res27),
.dout_30(res30),
.dout_31(res31),
.dout_32(res32),
.dout_33(res33),
.dout_34(res34),
.dout_35(res35),
.dout_36(res36),
.dout_37(res37),
.dout_40(res40),
.dout_41(res41),
.dout_42(res42),
.dout_43(res43),
.dout_44(res44),
.dout_45(res45),
.dout_46(res46),
.dout_47(res47),
.dout_50(res50),
.dout_51(res51),
.dout_52(res52),
.dout_53(res53),
.dout_54(res54),
.dout_55(res55),
.dout_56(res56),
.dout_57(res57),
.dout_60(res60),
.dout_61(res61),
.dout_62(res62),
.dout_63(res63),
.dout_64(res64),
.dout_65(res65),
.dout_66(res66),
.dout_67(res67),
.dout_70(res70),
.dout_71(res71),
.dout_72(res72),
.dout_73(res73),
.dout_74(res74),
.dout_75(res75),
.dout_76(res76),
.dout_77(res77),
.douten(doe)
);
// Hookup ZigZag unit
zigzag zigzag_mod(
.clk(clk),
.ena(ena),
.dstrb(doe),
.din_00(res00),
.din_01(res01),
.din_02(res02),
.din_03(res03),
.din_04(res04),
.din_05(res05),
.din_06(res06),
.din_07(res07),
.din_10(res10),
.din_11(res11),
.din_12(res12),
.din_13(res13),
.din_14(res14),
.din_15(res15),
.din_16(res16),
.din_17(res17),
.din_20(res20),
.din_21(res21),
.din_22(res22),
.din_23(res23),
.din_24(res24),
.din_25(res25),
.din_26(res26),
.din_27(res27),
.din_30(res30),
.din_31(res31),
.din_32(res32),
.din_33(res33),
.din_34(res34),
.din_35(res35),
.din_36(res36),
.din_37(res37),
.din_40(res40),
.din_41(res41),
.din_42(res42),
.din_43(res43),
.din_44(res44),
.din_45(res45),
.din_46(res46),
.din_47(res47),
.din_50(res50),
.din_51(res51),
.din_52(res52),
.din_53(res53),
.din_54(res54),
.din_55(res55),
.din_56(res56),
.din_57(res57),
.din_60(res60),
.din_61(res61),
.din_62(res62),
.din_63(res63),
.din_64(res64),
.din_65(res65),
.din_66(res66),
.din_67(res67),
.din_70(res70),
.din_71(res71),
.din_72(res72),
.din_73(res73),
.din_74(res74),
.din_75(res75),
.din_76(res76),
.din_77(res77),
.dout(dout),
.douten(douten)
);
endmodule |
module body
//
// generate sample counter
reg [5:0] sample_cnt;
wire dcnt = &sample_cnt;
always @(posedge clk or negedge rst)
if (~rst)
sample_cnt <= #1 6'h0;
else if (ena)
if(dstrb)
sample_cnt <= #1 6'h0;
else if(~dcnt)
sample_cnt <= #1 sample_cnt + 6'h1;
// internal signals
always @(posedge clk or negedge rst)
if (~rst)
begin
go <= #1 1'b0;
dgo <= #1 1'b0;
ddgo <= #1 1'b0;
ddin <= #1 0;
douten <= #1 1'b0;
ddcnt <= #1 1'b1;
dddcnt <= #1 1'b1;
end
else if (ena)
begin
go <= #1 dstrb;
dgo <= #1 go;
ddgo <= #1 dgo;
ddin <= #1 din;
ddcnt <= #1 dcnt;
dddcnt <= #1 ddcnt;
douten <= #1 ddcnt & ~dddcnt;
end
// Hookup DCT units
// V = 0
dctub #(coef_width, di_width, 3'h0)
dct_block_0 (
.clk(clk),
.ena(ena),
.ddgo(ddgo),
.x(sample_cnt[2:0]),
.y(sample_cnt[5:3]),
.ddin(ddin),
.dout0(dout_00), // (U,V) = (0,0)
.dout1(dout_01), // (U,V) = (0,1)
.dout2(dout_02), // (U,V) = (0,2)
.dout3(dout_03), // (U,V) = (0,3)
.dout4(dout_04), // (U,V) = (0,4)
.dout5(dout_05), // (U,V) = (0,5)
.dout6(dout_06), // (U,V) = (0,6)
.dout7(dout_07) // (U,V) = (0,7)
);
// V = 1
dctub #(coef_width, di_width, 3'h1)
dct_block_1 (
.clk(clk),
.ena(ena),
.ddgo(ddgo),
.x(sample_cnt[2:0]),
.y(sample_cnt[5:3]),
.ddin(ddin),
.dout0(dout_10), // (U,V) = (1,0)
.dout1(dout_11), // (U,V) = (1,1)
.dout2(dout_12), // (U,V) = (1,2)
.dout3(dout_13), // (U,V) = (1,3)
.dout4(dout_14), // (U,V) = (1,4)
.dout5(dout_15), // (U,V) = (1,5)
.dout6(dout_16), // (U,V) = (1,6)
.dout7(dout_17) // (U,V) = (1,7)
);
// V = 2
dctub #(coef_width, di_width, 3'h2)
dct_block_2 (
.clk(clk),
.ena(ena),
.ddgo(ddgo),
.x(sample_cnt[2:0]),
.y(sample_cnt[5:3]),
.ddin(ddin),
.dout0(dout_20), // (U,V) = (2,0)
.dout1(dout_21), // (U,V) = (2,1)
.dout2(dout_22), // (U,V) = (2,2)
.dout3(dout_23), // (U,V) = (2,3)
.dout4(dout_24), // (U,V) = (2,4)
.dout5(dout_25), // (U,V) = (2,5)
.dout6(dout_26), // (U,V) = (2,6)
.dout7(dout_27) // (U,V) = (2,7)
);
// V = 3
dctub #(coef_width, di_width, 3'h3)
dct_block_3 (
.clk(clk),
.ena(ena),
.ddgo(ddgo),
.x(sample_cnt[2:0]),
.y(sample_cnt[5:3]),
.ddin(ddin),
.dout0(dout_30), // (U,V) = (3,0)
.dout1(dout_31), // (U,V) = (3,1)
.dout2(dout_32), // (U,V) = (3,2)
.dout3(dout_33), // (U,V) = (3,3)
.dout4(dout_34), // (U,V) = (3,4)
.dout5(dout_35), // (U,V) = (3,5)
.dout6(dout_36), // (U,V) = (3,6)
.dout7(dout_37) // (U,V) = (3,7)
);
// V = 4
dctub #(coef_width, di_width, 3'h4)
dct_block_4 (
.clk(clk),
.ena(ena),
.ddgo(ddgo),
.x(sample_cnt[2:0]),
.y(sample_cnt[5:3]),
.ddin(ddin),
.dout0(dout_40), // (U,V) = (4,0)
.dout1(dout_41), // (U,V) = (4,1)
.dout2(dout_42), // (U,V) = (4,2)
.dout3(dout_43), // (U,V) = (4,3)
.dout4(dout_44), // (U,V) = (4,4)
.dout5(dout_45), // (U,V) = (4,5)
.dout6(dout_46), // (U,V) = (4,6)
.dout7(dout_47) // (U,V) = (4,7)
);
// V = 5
dctub #(coef_width, di_width, 3'h5)
dct_block_5 (
.clk(clk),
.ena(ena),
.ddgo(ddgo),
.x(sample_cnt[2:0]),
.y(sample_cnt[5:3]),
.ddin(ddin),
.dout0(dout_50), // (U,V) = (5,0)
.dout1(dout_51), // (U,V) = (5,1)
.dout2(dout_52), // (U,V) = (5,2)
.dout3(dout_53), // (U,V) = (5,3)
.dout4(dout_54), // (U,V) = (5,4)
.dout5(dout_55), // (U,V) = (5,5)
.dout6(dout_56), // (U,V) = (5,6)
.dout7(dout_57) // (U,V) = (5,7)
);
// V = 6
dctub #(coef_width, di_width, 3'h6)
dct_block_6 (
.clk(clk),
.ena(ena),
.ddgo(ddgo),
.x(sample_cnt[2:0]),
.y(sample_cnt[5:3]),
.ddin(ddin),
.dout0(dout_60), // (U,V) = (6,0)
.dout1(dout_61), // (U,V) = (6,1)
.dout2(dout_62), // (U,V) = (6,2)
.dout3(dout_63), // (U,V) = (6,3)
.dout4(dout_64), // (U,V) = (6,4)
.dout5(dout_65), // (U,V) = (6,5)
.dout6(dout_66), // (U,V) = (6,6)
.dout7(dout_67) // (U,V) = (6,7)
);
// V = 7
dctub #(coef_width, di_width, 3'h7)
dct_block_7 (
.clk(clk),
.ena(ena),
.ddgo(ddgo),
.x(sample_cnt[2:0]),
.y(sample_cnt[5:3]),
.ddin(ddin),
.dout0(dout_70), // (U,V) = (7,0)
.dout1(dout_71), // (U,V) = (7,1)
.dout2(dout_72), // (U,V) = (7,2)
.dout3(dout_73), // (U,V) = (7,3)
.dout4(dout_74), // (U,V) = (7,4)
.dout5(dout_75), // (U,V) = (7,5)
.dout6(dout_76), // (U,V) = (7,6)
.dout7(dout_77) // (U,V) = (7,7)
);
endmodule |
module body
//
// Hookup DCT units
dctu #(coef_width, di_width, v, 3'h0)
dct_unit_0 (
.clk(clk),
.ena(ena),
.ddgo(ddgo),
.x(x),
.y(y),
.ddin(ddin),
.dout(dout0)
);
dctu #(coef_width, di_width, v, 3'h1)
dct_unit_1 (
.clk(clk),
.ena(ena),
.ddgo(ddgo),
.x(x),
.y(y),
.ddin(ddin),
.dout(dout1)
);
dctu #(coef_width, di_width, v, 3'h2)
dct_unit_2 (
.clk(clk),
.ena(ena),
.ddgo(ddgo),
.x(x),
.y(y),
.ddin(ddin),
.dout(dout2)
);
dctu #(coef_width, di_width, v, 3'h3)
dct_unit_3 (
.clk(clk),
.ena(ena),
.ddgo(ddgo),
.x(x),
.y(y),
.ddin(ddin),
.dout(dout3)
);
dctu #(coef_width, di_width, v, 3'h4)
dct_unit_4 (
.clk(clk),
.ena(ena),
.ddgo(ddgo),
.x(x),
.y(y),
.ddin(ddin),
.dout(dout4)
);
dctu #(coef_width, di_width, v, 3'h5)
dct_unit_5 (
.clk(clk),
.ena(ena),
.ddgo(ddgo),
.x(x),
.y(y),
.ddin(ddin),
.dout(dout5)
);
dctu #(coef_width, di_width, v, 3'h6)
dct_unit_6 (
.clk(clk),
.ena(ena),
.ddgo(ddgo),
.x(x),
.y(y),
.ddin(ddin),
.dout(dout6)
);
dctu #(coef_width, di_width, v, 3'h7)
dct_unit_7 (
.clk(clk),
.ena(ena),
.ddgo(ddgo),
.x(x),
.y(y),
.ddin(ddin),
.dout(dout7)
);
endmodule |
module jpeg_qnr(clk, ena, rst, dstrb, din, qnt_val, qnt_cnt, dout, douten);
//
// parameters
//
parameter d_width = 12;
parameter z_width = 2 * d_width;
//
// inputs & outputs
//
input clk; // system clock
input ena; // clock enable
input rst; // asynchronous active low reset
input dstrb; // present dstrb 1clk cycle before din
input [d_width-1:0] din; // data input
input [ 7:0] qnt_val; // quantization value
output [ 5:0] qnt_cnt; // sample number (get quantization value qnt_cnt)
output [10:0] dout; // data output
output douten;
//
// variables
//
wire [z_width-1:0] iz; // intermediate divident value
wire [d_width-1:0] id; // intermediate dividor value
wire [d_width :0] iq; // intermediate result divider
reg [d_width :0] rq; // rounded q-value
reg [d_width+3:0] dep;// data enable pipeline
// generate sample counter
reg [5:0] qnt_cnt;
wire dcnt = &qnt_cnt;
always @(posedge clk or negedge rst)
if (~rst)
qnt_cnt <= #1 6'h0;
else if (dstrb)
qnt_cnt <= #1 6'h0;
else if (ena)
qnt_cnt <= #1 qnt_cnt + 6'h1;
// generate intermediate dividor/divident values
assign id = { {(d_width - 8){1'b0}}, qnt_val};
assign iz = { {(z_width - d_width){din[d_width-1]}}, din};
// hookup division unit
div_su #(z_width)
divider (
.clk(clk),
.ena(ena),
.z(iz),
.d(id),
.q(iq),
.s(),
.div0(),
.ovf()
);
// round result to the nearest integer
always @(posedge clk)
if (ena)
if (iq[0])
if (iq[d_width])
rq <= #1 iq - 1'h1;
else
rq <= #1 iq + 1'h1;
else
rq <= #1 iq;
// assign dout signal
assign dout = rq[d_width -1: d_width-11];
// generate data-out enable signal
// This is a pipeline, data is not dependant on sample-count
integer n;
always @(posedge clk or negedge rst)
if (!rst)
dep <= #1 0;
else if(ena)
begin
dep[0] <= #1 dstrb;
for (n=1; n <= d_width +3; n = n +1)
dep[n] <= #1 dep[n-1];
end
assign douten = dep[d_width +3];
endmodule |
module body
//
reg ddstrb;
always @(posedge clk)
ddstrb <= #1 dstrb;
// generate run-length encoded signals
jpeg_rle1 rle(
.clk(clk),
.rst(rst),
.ena(ena),
.go(ddstrb),
.din(din),
.rlen(rle_rlen),
.size(rle_size),
.amp(rle_amp),
.den(rle_den),
.dcterm(rle_dc)
);
// Find (15,0) (0,0) sequences and replace by (0,0)
// There can be max. 4 (15,0) sequences in a row
// step1
jpeg_rzs rz1(
.clk(clk),
.rst(rst),
.ena(ena),
.rleni(rle_rlen),
.sizei(rle_size),
.ampi(rle_amp),
.deni(rle_den),
.dci(rle_dc),
.rleno(rz1_rlen),
.sizeo(rz1_size),
.ampo(rz1_amp),
.deno(rz1_den),
.dco(rz1_dc)
);
// step2
jpeg_rzs rz2(
.clk(clk),
.rst(rst),
.ena(ena),
.rleni(rz1_rlen),
.sizei(rz1_size),
.ampi(rz1_amp),
.deni(rz1_den),
.dci(rz1_dc),
.rleno(rz2_rlen),
.sizeo(rz2_size),
.ampo(rz2_amp),
.deno(rz2_den),
.dco(rz2_dc)
);
// step3
jpeg_rzs rz3(
.clk(clk),
.rst(rst),
.ena(ena),
.rleni(rz2_rlen),
.sizei(rz2_size),
.ampi(rz2_amp),
.deni(rz2_den),
.dci(rz2_dc),
.rleno(rz3_rlen),
.sizeo(rz3_size),
.ampo(rz3_amp),
.deno(rz3_den),
.dco(rz3_dc)
);
// step4
jpeg_rzs rz4(
.clk(clk),
.rst(rst),
.ena(ena),
.rleni(rz3_rlen),
.sizei(rz3_size),
.ampi(rz3_amp),
.deni(rz3_den),
.dci(rz3_dc),
.rleno(rz4_rlen),
.sizeo(rz4_size),
.ampo(rz4_amp),
.deno(rz4_den),
.dco(rz4_dc)
);
// assign outputs
assign rlen = rz4_rlen;
assign size = rz4_size;
assign amp = rz4_amp;
assign douten = rz4_den;
assign bstart = rz4_dc;
endmodule |
module body
//
// hookup cosine-table
always @(posedge clk)
if(ena)
coef <= #1 dct_cos_table(x, y, u, v);
// hookup dct-mac unit
dct_mac #(8, coef_width)
macu (
.clk(clk),
.ena(ena),
.dclr(ddgo),
.din(ddin),
.coef( coef[31:31 -coef_width +1] ),
.result(result)
);
assign dout = result[coef_width +10: coef_width -1];
endmodule |
module body
//
always @(posedge clk)
if(ena & deni)
begin
size <= #1 sizei;
rlen <= #1 rleni;
amp <= #1 ampi;
end
always @(posedge clk)
if(ena)
begin
sizeo <= #1 size;
rleno <= #1 rlen;
ampo <= #1 amp;
dc <= #1 dci;
dco <= #1 dc;
end
assign zerobl = &rleni & ~|sizei & deni;
assign eob = ~|{rleni, sizei} & deni & ~dci;
always @(posedge clk or negedge rst)
if (!rst)
begin
state <= #1 1'b0;
den <= #1 1'b0;
deno <= #1 1'b0;
end
else
if(ena)
case (state) // synopsys full_case parallel_case
1'b0:
begin
if (zerobl)
begin
state <= #1 1'b1; // go to zero-detection state
den <= #1 1'b0; // do not yet set data output enable
deno <= #1 den; // output previous data
end
else
begin
state <= #1 1'b0; // stay in 'normal' state
den <= #1 deni; // set data output enable
deno <= #1 den; // output previous data
end
end
1'b1:
begin
deno <= #1 1'b0;
if (deni)
if (zerobl)
begin
state <= #1 1'b1; // stay in zero-detection state
den <= #1 1'b0; // hold current zer-block
deno <= #1 1'b1; // output previous zero-block
end
else if (eob)
begin
state <= #1 1'b0; // go to 'normal' state
den <= #1 1'b1; // set output enable for EOB
deno <= #1 1'b0; // (was already zero), maybe optimize ??
end
else
begin
state <= #1 1'b0; // go to normal state
den <= #1 1'b1; // set data output enable
deno <= #1 1'b1; // oops, zero-block should have been output
end
end
endcase
endmodule |
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