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module sky130_fd_sc_hvl__o22ai_1 (
Y ,
A1,
A2,
B1,
B2
);
output Y ;
input A1;
input A2;
input B1;
input B2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hvl__o22ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2)
);
endmodule |
module audio_buffer ( rclk, // read from avalon bus
wclk, // write to audio_effects
reset,
audio_ip,
read, //sample_req from audio_codec
audio_out,
audio_irq
);
input rclk,wclk,reset,read;
input [15:0] audio_ip;
output [15:0] audio_out;
output audio_irq;
reg [15:0] buffer1 [0:99];
reg [15:0] buffer2 [0:99];
reg [6:0] indexr = 7'd0;
reg [6:0] indexr_prev = 7'd0;
reg [6:0] indexw = 7'd0;
reg buf_cnt = 1'b0;
reg start_read;
reg irq;
reg irq_prev;
wire irq_edge;
reg [15:0] audio_out;
assign audio_irq = irq;
always @(posedge rclk)
irq_prev<= audio_irq;
assign irq_edge = audio_irq & (~irq_prev);
always @(posedge rclk) begin
if (reset ) begin
start_read <= 0;
indexr <= 7'd00;
end else if (irq_edge)
indexr_prev <= 0;
else if (indexr_prev < 100) begin
start_read <= 1'd1;
indexr_prev <= indexr;
indexr <= indexr + 1'b1;
end else begin
start_read <= 1'd0;
indexr <= 0;
end
end
always @(posedge rclk) begin
if (start_read) begin // write enable for buffer
if (buf_cnt==0)
buffer1[indexr] <= audio_ip;
else
buffer2[indexr] <= audio_ip;
end
end
always @(posedge wclk) begin
if (reset ) begin
indexw <= 7'd00;
irq <= 0;
end
else if (read) begin
if (indexw == 7'd99) begin
indexw <= 7'd00;
buf_cnt <= buf_cnt + 1'b1;
irq <= 1;
end
else begin
indexw <= indexw + 1'b1;
irq <= 0;
end
if (buf_cnt==0)
audio_out <= buffer2[indexw];
else
audio_out <= buffer1[indexw];
end
end
endmodule |
module bsg_cache_dma
import bsg_cache_pkg::*;
#(parameter `BSG_INV_PARAM(addr_width_p)
,parameter `BSG_INV_PARAM(data_width_p)
,parameter `BSG_INV_PARAM(block_size_in_words_p)
,parameter `BSG_INV_PARAM(sets_p)
,parameter `BSG_INV_PARAM(ways_p)
,parameter dma_data_width_p=data_width_p
,parameter lg_block_size_in_words_lp=`BSG_SAFE_CLOG2(block_size_in_words_p)
,parameter lg_sets_lp=`BSG_SAFE_CLOG2(sets_p)
,parameter lg_ways_lp=`BSG_SAFE_CLOG2(ways_p)
,parameter data_mask_width_lp=(data_width_p>>3)
,parameter dma_data_mask_width_lp=(dma_data_width_p>>3)
,parameter burst_len_lp=(block_size_in_words_p*data_width_p/dma_data_width_p)
,parameter lg_burst_len_lp=`BSG_SAFE_CLOG2(burst_len_lp)
,parameter burst_size_in_words_lp=(dma_data_width_p/data_width_p)
,parameter lg_burst_size_in_words_lp=`BSG_SAFE_CLOG2(burst_size_in_words_lp)
,parameter data_mem_els_lp=(sets_p*burst_len_lp)
,parameter lg_data_mem_els_lp=`BSG_SAFE_CLOG2(data_mem_els_lp)
,parameter bsg_cache_dma_pkt_width_lp=`bsg_cache_dma_pkt_width(addr_width_p)
,parameter debug_p=0
)
(
input clk_i
,input reset_i
,input bsg_cache_dma_cmd_e dma_cmd_i
,input [lg_ways_lp-1:0] dma_way_i
,input [addr_width_p-1:0] dma_addr_i
,output logic done_o
,output logic [data_width_p-1:0] snoop_word_o
,output logic [bsg_cache_dma_pkt_width_lp-1:0] dma_pkt_o
,output logic dma_pkt_v_o
,input dma_pkt_yumi_i
,input [dma_data_width_p-1:0] dma_data_i
,input dma_data_v_i
,output logic dma_data_ready_o
,output logic [dma_data_width_p-1:0] dma_data_o
,output logic dma_data_v_o
,input dma_data_yumi_i
,output logic data_mem_v_o
,output logic data_mem_w_o
,output logic [lg_data_mem_els_lp-1:0] data_mem_addr_o
,output logic [ways_p-1:0][dma_data_mask_width_lp-1:0] data_mem_w_mask_o
,output logic [ways_p-1:0][dma_data_width_p-1:0] data_mem_data_o
,input [ways_p-1:0][dma_data_width_p-1:0] data_mem_data_i
,output logic dma_evict_o // data eviction in progress
);
// localparam
//
localparam counter_width_lp=`BSG_SAFE_CLOG2(burst_len_lp+1);
localparam byte_offset_width_lp=`BSG_SAFE_CLOG2(data_width_p>>3);
localparam block_offset_width_lp=(block_size_in_words_p > 1) ? byte_offset_width_lp+lg_block_size_in_words_lp : byte_offset_width_lp;
// dma states
//
typedef enum logic [1:0] {
IDLE
,GET_FILL_DATA
,SEND_EVICT_DATA
} dma_state_e;
dma_state_e dma_state_n;
dma_state_e dma_state_r;
// dma counter
//
logic counter_clear;
logic counter_up;
logic [counter_width_lp-1:0] counter_r;
bsg_counter_clear_up #(
.max_val_p(burst_len_lp)
) dma_counter (
.clk_i(clk_i)
,.reset_i(reset_i)
,.clear_i(counter_clear)
,.up_i(counter_up)
,.count_o(counter_r)
);
wire counter_fill_max = counter_r == (burst_len_lp-1);
wire counter_evict_max = counter_r == burst_len_lp;
// dma packet
//
`declare_bsg_cache_dma_pkt_s(addr_width_p);
bsg_cache_dma_pkt_s dma_pkt;
// in fifo
//
logic in_fifo_v_lo;
logic [dma_data_width_p-1:0] in_fifo_data_lo;
logic in_fifo_yumi_li;
bsg_fifo_1r1w_small #(
.width_p(dma_data_width_p)
,.els_p((burst_len_lp<2) ? 2 : burst_len_lp)
) in_fifo (
.clk_i(clk_i)
,.reset_i(reset_i)
,.data_i(dma_data_i)
,.v_i(dma_data_v_i)
,.ready_o(dma_data_ready_o)
,.v_o(in_fifo_v_lo)
,.data_o(in_fifo_data_lo)
,.yumi_i(in_fifo_yumi_li)
);
// out fifo
//
logic out_fifo_v_li;
logic out_fifo_ready_lo;
logic [dma_data_width_p-1:0] out_fifo_data_li;
bsg_two_fifo #(
.width_p(dma_data_width_p)
) out_fifo (
.clk_i(clk_i)
,.reset_i(reset_i)
,.v_i(out_fifo_v_li)
,.data_i(out_fifo_data_li)
,.ready_o(out_fifo_ready_lo)
,.v_o(dma_data_v_o)
,.data_o(dma_data_o)
,.yumi_i(dma_data_yumi_i)
);
assign dma_pkt_o = dma_pkt;
logic [ways_p-1:0] dma_way_mask;
bsg_decode #(
.num_out_p(ways_p)
) dma_way_demux (
.i(dma_way_i)
,.o(dma_way_mask)
);
bsg_expand_bitmask #(
.in_width_p(ways_p)
,.expand_p(dma_data_mask_width_lp)
) expand0 (
.i(dma_way_mask)
,.o(data_mem_w_mask_o)
);
if (burst_len_lp == 1) begin
assign data_mem_addr_o = dma_addr_i[block_offset_width_lp+:lg_sets_lp];
end
//else if (burst_len_lp == block_size_in_words_p) begin
// assign data_mem_addr_o = {
// dma_addr_i[block_offset_width_lp+:lg_sets_lp],
// counter_r[0+:lg_burst_len_lp]
// };
//end
else begin
assign data_mem_addr_o = {
dma_addr_i[block_offset_width_lp+:lg_sets_lp],
counter_r[0+:lg_burst_len_lp]
};
end
assign data_mem_data_o = {ways_p{in_fifo_data_lo}};
bsg_mux #(
.width_p(dma_data_width_p)
,.els_p(ways_p)
) write_data_mux (
.data_i(data_mem_data_i)
,.sel_i(dma_way_i)
,.data_o(out_fifo_data_li)
);
always_comb begin
done_o = 1'b0;
dma_pkt_v_o = 1'b0;
dma_pkt.write_not_read = 1'b0;
dma_pkt.addr = {
dma_addr_i[addr_width_p-1:block_offset_width_lp],
{(block_offset_width_lp){1'b0}}
};
data_mem_v_o = 1'b0;
data_mem_w_o = 1'b0;
in_fifo_yumi_li = 1'b0;
dma_state_n = IDLE;
out_fifo_v_li = 1'b0;
counter_clear = 1'b0;
counter_up = 1'b0;
dma_evict_o = 1'b0;
case (dma_state_r)
// wait for dma_cmd from bsg_cache_miss.
// when transitioning from GET_FILL_DATA or SEND_EVICT_DATA state,
// make sure that counter is cleared to zero.
IDLE: begin
counter_clear = 1'b0;
counter_up = 1'b0;
data_mem_v_o = 1'b0;
dma_pkt_v_o = 1'b0;
dma_pkt.write_not_read = 1'b0;
done_o = 1'b0;
dma_state_n = IDLE;
case (dma_cmd_i)
e_dma_send_fill_addr: begin
dma_pkt_v_o = 1'b1;
dma_pkt.write_not_read = 1'b0;
done_o = dma_pkt_yumi_i;
dma_state_n = IDLE;
end
e_dma_send_evict_addr: begin
dma_pkt_v_o = 1'b1;
dma_pkt.write_not_read = 1'b1;
done_o = dma_pkt_yumi_i;
dma_state_n = IDLE;
end
e_dma_get_fill_data: begin
counter_clear = 1'b1;
dma_state_n = GET_FILL_DATA;
end
e_dma_send_evict_data: begin
// we are reading the first word, as we are transitioning out.
// so the counter is incremented to 1.
counter_clear = 1'b1;
counter_up = 1'b1;
data_mem_v_o = 1'b1;
dma_state_n = SEND_EVICT_DATA;
end
e_dma_nop: begin
// nothing happens.
end
default: begin
// this should never happen.
end
endcase
end
// receive the block data from dma_data_i
// and write into data_mem word by word.
GET_FILL_DATA: begin
dma_state_n = counter_fill_max & in_fifo_v_lo
? IDLE
: GET_FILL_DATA;
data_mem_v_o = in_fifo_v_lo;
data_mem_w_o = in_fifo_v_lo;
in_fifo_yumi_li = in_fifo_v_lo;
counter_up = in_fifo_v_lo & ~counter_fill_max;
counter_clear = in_fifo_v_lo & counter_fill_max;
done_o = counter_fill_max & in_fifo_v_lo;
end
// read the requested block from data_mem and send it out over
// dma_data_o word by word.
SEND_EVICT_DATA: begin
// counter_r in this context means the number of words read from
// data_mem so far.
dma_state_n = counter_evict_max & out_fifo_ready_lo
? IDLE
: SEND_EVICT_DATA;
counter_up = out_fifo_ready_lo & ~counter_evict_max;
counter_clear = out_fifo_ready_lo & counter_evict_max;
out_fifo_v_li = 1'b1;
data_mem_v_o = out_fifo_ready_lo & ~counter_evict_max;
done_o = counter_evict_max & out_fifo_ready_lo;
dma_evict_o = 1'b1;
end
default: begin
// this should never happen, but if it does, then go back to IDLE.
dma_state_n = IDLE;
end
endcase
end
// snoop_word register
// As the fill data is coming in, grab the word that matches the block
// offset, so that we don't have to read the data_mem again to return the
// load data.
logic [lg_burst_size_in_words_lp-1:0] snoop_word_offset;
logic snoop_word_we;
logic [data_width_p-1:0] snoop_word_n;
assign snoop_word_offset = dma_addr_i[byte_offset_width_lp+:lg_burst_size_in_words_lp];
if (burst_len_lp == 1) begin
assign snoop_word_we = (dma_state_r == GET_FILL_DATA) & in_fifo_v_lo;
end
else if (burst_len_lp == block_size_in_words_p) begin
assign snoop_word_we = (dma_state_r == GET_FILL_DATA) & in_fifo_v_lo
& (counter_r[0+:lg_burst_len_lp] == dma_addr_i[byte_offset_width_lp+:lg_burst_len_lp]);
end
else begin
assign snoop_word_we = (dma_state_r == GET_FILL_DATA) & in_fifo_v_lo
& (counter_r[0+:lg_burst_len_lp] == dma_addr_i[byte_offset_width_lp+lg_burst_size_in_words_lp+:lg_burst_len_lp]);
end
bsg_mux #(
.width_p(data_width_p)
,.els_p(burst_size_in_words_lp)
) snoop_mux0 (
.data_i(in_fifo_data_lo)
,.sel_i(snoop_word_offset)
,.data_o(snoop_word_n)
);
// synopsys sync_set_reset "reset_i"
always_ff @ (posedge clk_i) begin
if (reset_i) begin
dma_state_r <= IDLE;
end
else begin
dma_state_r <= dma_state_n;
if (snoop_word_we) begin
snoop_word_o <= snoop_word_n;
end
end
end
// synopsys translate_off
always_ff @ (posedge clk_i) begin
if (debug_p) begin
if (dma_pkt_v_o & dma_pkt_yumi_i) begin
$display("<VCACHE> DMA_PKT we:%0d addr:%8h // %8t",
dma_pkt.write_not_read, dma_pkt.addr, $time);
end
end
end
// synopsys translate_on
endmodule |
module cart (
input clk_in, // system clock signal
// Mapper config data.
input [39:0] cfg_in, // cartridge config (from iNES header)
input cfg_upd_in, // pulse signal on cfg_in update
// PRG-ROM interface.
input prg_nce_in, // prg-rom chip enable (active low)
input [14:0] prg_a_in, // prg-rom address
input prg_r_nw_in, // prg-rom read/write select
input [ 7:0] prg_d_in, // prg-rom data in
output [ 7:0] prg_d_out, // prg-rom data out
// CHR-ROM interface.
input [13:0] chr_a_in, // chr-rom address
input chr_r_nw_in, // chr-rom read/write select
input [ 7:0] chr_d_in, // chr-rom data in
output [ 7:0] chr_d_out, // chr-rom data out
output ciram_nce_out, // vram chip enable (active low)
output ciram_a10_out // vram a10 value (controls mirroring)
);
wire prgrom_bram_we;
wire [14:0] prgrom_bram_a;
wire [7:0] prgrom_bram_dout;
// Block ram instance for PRG-ROM memory range (0x8000 - 0xFFFF). Will eventually be
// replaced with SRAM.
single_port_ram_sync #(
.ADDR_WIDTH (15 ),
.DATA_WIDTH (8 ))
prgrom_bram (
.clk (clk_in ),
.we (prgrom_bram_we ),
.addr_a (prgrom_bram_a ),
.din_a (prg_d_in ),
.dout_a (prgrom_bram_dout )
);
assign prgrom_bram_we = (~prg_nce_in) ? ~prg_r_nw_in : 1'b0;
assign prg_d_out = (~prg_nce_in) ? prgrom_bram_dout : 8'h00;
assign prgrom_bram_a = (cfg_in[33]) ? prg_a_in[14:0] : { 1'b0, prg_a_in[13:0] };
wire chrrom_pat_bram_we;
wire [7:0] chrrom_pat_bram_dout;
// Block ram instance for "CHR Pattern Table" memory range (0x0000 - 0x1FFF).
single_port_ram_sync #(
.ADDR_WIDTH (13 ),
.DATA_WIDTH (8 ))
chrrom_pat_bram (
.clk (clk_in ),
.we (chrrom_pat_bram_we ),
.addr_a (chr_a_in[12:0] ),
.din_a (chr_d_in ),
.dout_a (chrrom_pat_bram_dout )
);
assign ciram_nce_out = ~chr_a_in[13];
assign ciram_a10_out = (cfg_in[16]) ? chr_a_in[10] : chr_a_in[11];
assign chrrom_pat_bram_we = (ciram_nce_out) ? ~chr_r_nw_in : 1'b0;
assign chr_d_out = (ciram_nce_out) ? chrrom_pat_bram_dout : 8'h00;
endmodule |
module sdrdrum_arty_tb;
reg clk = 1'b0;
reg eth_clk = 1'b0;
reg rstn = 1'b0;
sdrdrum_arty dut (
.clk_in(clk),
.rstn_in(rstn),
.adc_a_data(1'b0),
.adc_b_data(1'b0),
.adc_c_data(1'b0),
.adc_d_data(1'b0),
// Ethernet
.eth_phy_rxd(4'b0),
.eth_phy_rx_clk(1'b0),
.eth_phy_rx_dv(1'b0),
.eth_phy_rx_er(1'b0),
.eth_phy_tx_clk(eth_clk),
.eth_phy_crs(1'b0),
.eth_phy_col(1'b0),
// IO
.switches(4'b0),
.buttons(4'b0)
);
initial begin
#500 rstn = 1'b1;
end
always begin
#20 eth_clk = ~eth_clk;
end
always begin
#5 clk = ~clk;
end
endmodule |
module ad_iqcor (
// data interface
clk,
valid,
data_i,
data_q,
valid_out,
data_out,
// control interface
iqcor_enable,
iqcor_coeff_1,
iqcor_coeff_2);
// select i/q if disabled
parameter IQSEL = 0;
// data interface
input clk;
input valid;
input [15:0] data_i;
input [15:0] data_q;
output valid_out;
output [15:0] data_out;
// control interface
input iqcor_enable;
input [15:0] iqcor_coeff_1;
input [15:0] iqcor_coeff_2;
// internal registers
reg p1_valid = 'd0;
reg [15:0] p1_data_i = 'd0;
reg [15:0] p1_data_q = 'd0;
reg p2_valid = 'd0;
reg p2_sign_i = 'd0;
reg p2_sign_q = 'd0;
reg [14:0] p2_magn_i = 'd0;
reg [14:0] p2_magn_q = 'd0;
reg p3_valid = 'd0;
reg [15:0] p3_data_i = 'd0;
reg [15:0] p3_data_q = 'd0;
reg p4_valid = 'd0;
reg [15:0] p4_data = 'd0;
reg valid_out = 'd0;
reg [15:0] data_out = 'd0;
// internal signals
wire [15:0] p2_data_i_s;
wire [15:0] p2_data_q_s;
wire p3_valid_s;
wire [31:0] p3_magn_i_s;
wire p3_sign_i_s;
wire [31:0] p3_magn_q_s;
wire p3_sign_q_s;
wire [15:0] p3_data_2s_i_p_s;
wire [15:0] p3_data_2s_q_p_s;
wire [15:0] p3_data_2s_i_n_s;
wire [15:0] p3_data_2s_q_n_s;
// apply offsets first
always @(posedge clk) begin
p1_valid <= valid;
p1_data_i <= data_i;
p1_data_q <= data_q;
end
// convert to sign-magnitude
assign p2_data_i_s = ~p1_data_i + 1'b1;
assign p2_data_q_s = ~p1_data_q + 1'b1;
always @(posedge clk) begin
p2_valid <= p1_valid;
p2_sign_i <= p1_data_i[15] ^ iqcor_coeff_1[15];
p2_sign_q <= p1_data_q[15] ^ iqcor_coeff_2[15];
p2_magn_i <= (p1_data_i[15] == 1'b1) ? p2_data_i_s[14:0] : p1_data_i[14:0];
p2_magn_q <= (p1_data_q[15] == 1'b1) ? p2_data_q_s[14:0] : p1_data_q[14:0];
end
// scaling functions - i
mul_u16 #(.DELAY_DATA_WIDTH(2)) i_mul_u16_i (
.clk (clk),
.data_a ({1'b0, p2_magn_i}),
.data_b ({1'b0, iqcor_coeff_1[14:0]}),
.data_p (p3_magn_i_s),
.ddata_in ({p2_valid, p2_sign_i}),
.ddata_out ({p3_valid_s, p3_sign_i_s}));
// scaling functions - q
mul_u16 #(.DELAY_DATA_WIDTH(1)) i_mul_u16_q (
.clk (clk),
.data_a ({1'b0, p2_magn_q}),
.data_b ({1'b0, iqcor_coeff_2[14:0]}),
.data_p (p3_magn_q_s),
.ddata_in (p2_sign_q),
.ddata_out (p3_sign_q_s));
// convert to 2s-complements
assign p3_data_2s_i_p_s = {1'b0, p3_magn_i_s[28:14]};
assign p3_data_2s_q_p_s = {1'b0, p3_magn_q_s[28:14]};
assign p3_data_2s_i_n_s = ~p3_data_2s_i_p_s + 1'b1;
assign p3_data_2s_q_n_s = ~p3_data_2s_q_p_s + 1'b1;
always @(posedge clk) begin
p3_valid <= p3_valid_s;
p3_data_i <= (p3_sign_i_s == 1'b1) ? p3_data_2s_i_n_s : p3_data_2s_i_p_s;
p3_data_q <= (p3_sign_q_s == 1'b1) ? p3_data_2s_q_n_s : p3_data_2s_q_p_s;
end
// corrected output is sum of two
always @(posedge clk) begin
p4_valid <= p3_valid;
p4_data <= p3_data_i + p3_data_q;
end
// output registers
always @(posedge clk) begin
if (iqcor_enable == 1'b1) begin
valid_out <= p4_valid;
data_out <= p4_data;
end else if (IQSEL == 1) begin
valid_out <= valid;
data_out <= data_q;
end else begin
valid_out <= valid;
data_out <= data_i;
end
end
endmodule |
module testcache();
reg clk;
reg re, we, we2, we3;
reg [31:0] address, writedata;
wire [31:0] readdatacache,readmissdata;
wire hit, miss, dirty;
// test
memory_system DUT(clk, re, we, we2, we3, address, writedata, readdatacache, hit, miss, dirty);
// generate clock to sequence tests
always begin
clk <= 1;
#5;
clk <= 0;
# 5;
end
// check results
initial begin
/*
re <= 1'b0;
we <= 1'b0;
we2 <=1'b0;
we3 <= 1'b0;
address <= 32'h0;
writedata <= 32'b0;
#10;
// Write Hit: if in cache, write in cache
re <= 1'b0;
we <= 1'b1;
we2 <= 1'b0;
we3 <= 1'b0;
address <= 32'h50;
writedata <= 32'h7;
#10;
we <= 1'b0;
#10;
// Read Hit: Hit generated, no need to go to main memory, read out of cache valid
re <= 1'b1;
we <= 1'b0;
we2 <= 1'b0;
we3 <= 1'b0;
address <= 32'h50;
writedata <= 32'hxxxxxxxx;
#10;
re <= 1'b0;
#10;
// Write Hit: if in cache, write in cache
re <= 1'b0;
we <= 1'b1;
we2 <= 1'b0;
we3 <= 1'b0;
address <= 32'h54;
writedata <= 32'h7;
#10;
we <= 1'b0;
#200;
*/
// Write Miss: Miss generated, gets main memory, write this data to this cache value
re <= 1'b0;
we <= 1'b1;
we2 <= 1'b0;
we3 <= 1'b0;
address <= 32'h00004012;
writedata <= 32'h12345678;
#10;
we <= 1'b0;
#200;
we2 <= 1'b1;
#5;
we2 <= 1'b0;
#5;
// Read Hit: Hit generated, no need to go to main memory, read out of cache valid
re <= 1'b1;
we <= 1'b0;
we2 <= 1'b0;
we3 <= 1'b0;
address <= 32'h00004012;
writedata <= 32'hxxxxxxxx;
#10;
re <= 1'b0;
#10;
// Read Miss: !Hit generated, gets main memory, read out of cache is initialized mainmemory value after writing new cache value
re <= 1'b1;
we <= 1'b0;
we2 <= 1'b0;
we3 <= 1'b0;
address <= 32'h00008012;
writedata <= 32'hxxxxxxxx;
#10;
re <= 1'b0;
#200;
we3 <= 1'b1;
#5;
we3 <= 1'b0;
#20;
// Write Hit: if in cache, write in cache
re <= 1'b0;
we <= 1'b1;
we2 <= 1'b0;
we3 <= 1'b0;
address <= 32'h00008011;
writedata <= 32'h87654321;
#10;
we <= 1'b0;
#200;
// Write Hit: if in cache, write in cache
re <= 1'b0;
we <= 1'b1;
we2 <= 1'b0;
we3 <= 1'b0;
address <= 32'h00008010;
writedata <= 32'h01010101;
#10;
we <= 1'b0;
#200;
end
endmodule |
module spi_rx(
clk,
reset_n,
sdi,
sck,
ss_n,
adrs,
data,
rx_valid);
input wire clk, reset_n, sdi, sck, ss_n;
output wire rx_valid;
output wire [7:0] adrs, data;
reg [15:0] shift_reg, rx_buf1, rx_buf2;
reg [3:0] rx_cnt;
reg [2:0] valid_sync;
wire rx_done;
assign rx_done = &rx_cnt;
assign adrs = rx_buf2[15:8];
assign data = rx_buf2[7:0];
assign rx_valid = valid_sync[2];
always @(posedge clk, negedge reset_n)
begin
if(!reset_n)
begin
valid_sync <= 0;
rx_buf2 <= 0;
end
else
begin
valid_sync <= {valid_sync[1:0], rx_done};
if(valid_sync[1]) rx_buf2 <= rx_buf1;
else rx_buf2 <= rx_buf2;
end
end
always @(negedge sck, negedge reset_n)
begin
if(!reset_n)
begin
shift_reg <= 0;
rx_buf1 <= 0;
rx_cnt <= 0;
end
else if(!ss_n)
begin
shift_reg <= {shift_reg[13:0], sdi};
rx_cnt <= rx_cnt + 1;
if(rx_done) rx_buf1 <= {shift_reg, sdi};
end
end
endmodule |
module latch_EX_MEM
#(
parameter B=32, W=5
)
(
input wire clk,
input wire reset,
inout wire ena,
/* Data signals INPUTS */
//input wire [B-1:0] add_result_in,
input wire [B-1:0] alu_result_in,
input wire [B-1:0] r_data2_in,
input wire [W-1:0] mux_RegDst_in,
//input wire [B-1:0] pc_jump_in,
/* Data signals OUTPUTS */
//output wire [B-1:0]add_result_out,
output wire [B-1:0]alu_result_out,
output wire [B-1:0]r_data2_out,
output wire [W-1:0]mux_RegDst_out,
//output wire [B-1:0] pc_jump_out,
/* Control signals INPUTS*/
//input wire zero_in,
//Write back
input wire wb_RegWrite_in,
input wire wb_MemtoReg_in,
//Memory
//input wire m_Jump_in,
//input wire m_Branch_in,
//input wire m_BranchNot_in,
//input wire m_MemRead_in,
input wire m_MemWrite_in,
//Other
input [5:0] opcode_in,
/* Control signals OUTPUTS */
//output wire zero_out,
//Write back
output wire wb_RegWrite_out,
output wire wb_MemtoReg_out,
//Memory
//output wire m_Jump_out,
//output wire m_Branch_out,
//output wire m_BranchNot_out,
//output wire m_MemRead_out,
output wire m_MemWrite_out,
//Other
output wire [5:0] opcode_out
);
/* Data REGISTERS */
//reg [B-1:0] add_result_reg;
reg [B-1:0] alu_result_reg;
reg [B-1:0] r_data2_reg;
reg [W-1:0] mux_RegDst_reg;
//reg [B-1:0] pc_jump_reg;
/* Control REGISTERS */
//reg zero_reg;
//Write back
reg wb_RegWrite_reg;
reg wb_MemtoReg_reg;
//Memory
//reg m_Jump_reg;
//reg m_Branch_reg;
//reg m_BranchNot_reg;
//reg m_MemRead_reg;
reg m_MemWrite_reg;
//other
reg [5:0] opcode_reg;
always @(posedge clk)
begin
if (reset)
begin
//add_result_reg <= 0;
alu_result_reg <= 0;
r_data2_reg <= 0;
mux_RegDst_reg <= 0;
//pc_jump_reg <= 0;
//zero_reg <= 0;
wb_RegWrite_reg <= 0;
wb_MemtoReg_reg <= 0;
//m_Jump_reg <= 0;
//m_Branch_reg <= 0;
//m_BranchNot_reg <= 0;
//m_MemRead_reg <= 0;
m_MemWrite_reg <= 0;
opcode_reg <= 0;
end
else
if(ena==1'b1)
begin
/* Data signals write to ID_EX register */
//add_result_reg <= add_result_in;
alu_result_reg <= alu_result_in;
r_data2_reg <= r_data2_in;
mux_RegDst_reg <= mux_RegDst_in;
//pc_jump_reg <= pc_jump_in;
/* Control signals write to ID_EX register */
//zero_reg <= zero_in;
//Write back
wb_RegWrite_reg <= wb_RegWrite_in;
wb_MemtoReg_reg <= wb_MemtoReg_in;
//Memory
//m_Jump_reg <= m_Jump_in;
//m_Branch_reg <= m_Branch_in;
//m_BranchNot_reg <= m_BranchNot_in;
//m_MemRead_reg <= m_MemRead_in;
m_MemWrite_reg <= m_MemWrite_in;
//Other
opcode_reg <= opcode_in;
end
end
/* Data signals read from ID_EX register */
//assign add_result_out = add_result_reg;
assign alu_result_out = alu_result_reg;
assign r_data2_out = r_data2_reg;
assign mux_RegDst_out = mux_RegDst_reg;
//assign pc_jump_out = pc_jump_reg;
/* Control signals read from ID_EX register */
//assign zero_out = zero_reg;
//Write back
assign wb_RegWrite_out = wb_RegWrite_reg;
assign wb_MemtoReg_out = wb_MemtoReg_reg;
//Memory
//assign m_Jump_out = m_Jump_reg;
//assign m_Branch_out = m_Branch_reg;
//assign m_BranchNot_out = m_BranchNot_reg;
//assign m_MemRead_out = m_MemRead_reg;
assign m_MemWrite_out = m_MemWrite_reg;
assign opcode_out = opcode_reg;
endmodule |
module RAMConcur_TBV (
);
// Verilog Only Testbench for `RAMConcur`
reg [3:0] addr = 0;
wire [3:0] dout;
reg clk = 0;
reg [3:0] din = 0;
reg writeE = 0;
reg [3:0] RAMConcur0_0_1_2_memory [0:4-1];
initial begin: INITIALIZE_RAMCONCUR0_0_1_2_MEMORY
integer i;
for(i=0; i<4; i=i+1) begin
RAMConcur0_0_1_2_memory[i] = 0;
end
end
always @(posedge clk) begin: RAMCONCUR_TBV_RAMCONCUR0_0_1_2_WRITEACTION
if (writeE) begin
RAMConcur0_0_1_2_memory[addr] <= din;
end
end
assign dout = RAMConcur0_0_1_2_memory[addr];
initial begin: RAMCONCUR_TBV_CLK_SIGNAL
while (1'b1) begin
clk <= (!clk);
# 1;
end
end
initial begin: RAMCONCUR_TBV_STIMULES
integer i;
for (i=0; i<1; i=i+1) begin
@(negedge clk);
end
for (i=0; i<4; i=i+1) begin
@(posedge clk);
writeE <= 1'b1;
addr <= i;
case (i)
0: din <= 3;
1: din <= 2;
2: din <= 1;
default: din <= 0;
endcase
end
for (i=0; i<1; i=i+1) begin
@(posedge clk);
writeE <= 1'b0;
end
for (i=0; i<4; i=i+1) begin
@(posedge clk);
addr <= i;
end
for (i=0; i<4; i=i+1) begin
@(posedge clk);
writeE <= 1'b1;
addr <= i;
case ((-i))
0: din <= 3;
1: din <= 2;
2: din <= 1;
default: din <= 0;
endcase
end
for (i=0; i<1; i=i+1) begin
@(posedge clk);
writeE <= 1'b0;
end
for (i=0; i<4; i=i+1) begin
@(posedge clk);
addr <= i;
end
$finish;
end
always @(posedge clk) begin: RAMCONCUR_TBV_PRINT_DATA
$write("%h", addr);
$write(" ");
$write("%h", din);
$write(" ");
$write("%h", writeE);
$write(" ");
$write("%h", dout);
$write(" ");
$write("%h", clk);
$write("\n");
end
endmodule |
module eb17_ctrl #(
parameter ZERO = 7'b1_0_01_00_0,
parameter ONE = 7'b1_1_00_11_0,
parameter TWO = 7'b0_1_10_10_1
) (
input t_0_req,
output t_0_ack,
output i_0_req,
input i_0_ack,
output en0, en1, sel,
input clk, reset_n
);
// State machine
reg [6:0] state, state_nxt;
always @(posedge clk or negedge reset_n)
if (~reset_n) state <= ZERO;
else state <= state_nxt;
// state d0 d1 t.ack i.req en0 en1 sel
// ZERO - - 1 0 t.req 0 0 1_0_01_00_0
// ONE + - 1 1 t.req & i.ack t.req & ~i.ack 0 1_1_00_11_0
// TWO + + 0 1 i.ack t.req & i.ack 1 0_1_10_10_1
always @*
casez({state, t_0_req, i_0_ack})
{ZERO, 2'b1?} : state_nxt = ONE;
{ONE, 2'b01} : state_nxt = ZERO;
{ONE, 2'b10} : state_nxt = TWO;
{TWO, 2'b?1} : state_nxt = ONE;
default state_nxt = state;
endcase
assign t_0_ack = state[6];
assign i_0_req = state[5];
assign en0 = (state[4] | t_0_req) & (state[3] | i_0_ack);
assign en1 = (state[2] & t_0_req) & (state[1] ^ i_0_ack);
assign sel = state[0];
endmodule |
module e203_reset_ctrl #(
parameter MASTER = 1
)(
input clk, // clock
input rst_n, // async reset
input test_mode, // test mode
// The core's clk and rst
output rst_core,
// The ITCM/DTCM clk and rst
`ifdef E203_HAS_ITCM
output rst_itcm,
`endif
`ifdef E203_HAS_DTCM
output rst_dtcm,
`endif
// The Top always on clk and rst
output rst_aon
);
wire rst_sync_n;
`ifndef E203_HAS_LOCKSTEP//{
localparam RST_SYNC_LEVEL = `E203_ASYNC_FF_LEVELS;
`endif//}
reg [RST_SYNC_LEVEL-1:0] rst_sync_r;
generate
if(MASTER == 1) begin:master_gen
always @(posedge clk or negedge rst_n)
begin:rst_sync_PROC
if(rst_n == 1'b0)
begin
rst_sync_r[RST_SYNC_LEVEL-1:0] <= {RST_SYNC_LEVEL{1'b0}};
end
else
begin
rst_sync_r[RST_SYNC_LEVEL-1:0] <= {rst_sync_r[RST_SYNC_LEVEL-2:0],1'b1};
end
end
assign rst_sync_n = test_mode ? rst_n : rst_sync_r[`E203_ASYNC_FF_LEVELS-1];
end
else begin:slave_gen
// Just pass through for slave in lockstep mode
always @ *
begin:rst_sync_PROC
rst_sync_r = {RST_SYNC_LEVEL{1'b0}};
end
assign rst_sync_n = rst_n;
end
endgenerate
// The core's clk and rst
assign rst_core = rst_sync_n;
// The ITCM/DTCM clk and rst
`ifdef E203_HAS_ITCM
assign rst_itcm = rst_sync_n;
`endif
`ifdef E203_HAS_DTCM
assign rst_dtcm = rst_sync_n;
`endif
// The Top always on clk and rst
assign rst_aon = rst_sync_n;
endmodule |
module sky130_fd_sc_hd__dfbbn (
Q ,
Q_N ,
D ,
CLK_N ,
SET_B ,
RESET_B
);
// Module ports
output Q ;
output Q_N ;
input D ;
input CLK_N ;
input SET_B ;
input RESET_B;
// Local signals
wire RESET;
wire SET ;
wire CLK ;
wire buf_Q;
// Delay Name Output Other arguments
not not0 (RESET , RESET_B );
not not1 (SET , SET_B );
not not2 (CLK , CLK_N );
sky130_fd_sc_hd__udp_dff$NSR `UNIT_DELAY dff0 (buf_Q , SET, RESET, CLK, D);
buf buf0 (Q , buf_Q );
not not3 (Q_N , buf_Q );
endmodule |
module sky130_fd_sc_hs__a22oi (
Y ,
A1 ,
A2 ,
B1 ,
B2 ,
VPWR,
VGND
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
endmodule |
module sky130_fd_sc_ls__edfxbp (
Q ,
Q_N,
CLK,
D ,
DE
);
// Module ports
output Q ;
output Q_N;
input CLK;
input D ;
input DE ;
// Local signals
wire buf_Q ;
wire mux_out;
// Delay Name Output Other arguments
sky130_fd_sc_ls__udp_mux_2to1 mux_2to10 (mux_out, buf_Q, D, DE );
sky130_fd_sc_ls__udp_dff$P `UNIT_DELAY dff0 (buf_Q , mux_out, CLK );
buf buf0 (Q , buf_Q );
not not0 (Q_N , buf_Q );
endmodule |
module sky130_fd_sc_hd__and2b (
X ,
A_N,
B
);
// Module ports
output X ;
input A_N;
input B ;
// Local signals
wire not0_out ;
wire and0_out_X;
// Name Output Other arguments
not not0 (not0_out , A_N );
and and0 (and0_out_X, not0_out, B );
buf buf0 (X , and0_out_X );
endmodule |
module simple_spi_top(
clk_i, rst_i, cyc_i, stb_i, adr_i, we_i, dat_i, dat_o, ack_o,
inta_o,
sck_o, mosi_o, miso_i
);
//
// Inputs & outputs
//
// 8bit WISHBONE bus slave interface
input clk_i; // clock
input rst_i; // reset (asynchronous active low)
input cyc_i; // cycle
input stb_i; // strobe
input [1:0] adr_i; // address
input we_i; // write enable
input [7:0] dat_i; // data output
output [7:0] dat_o; // data input
output ack_o; // normal bus termination
output inta_o; // interrupt output
// SPI port
output sck_o; // serial clock output
output mosi_o; // MasterOut SlaveIN
input miso_i; // MasterIn SlaveOut
//
// Module body
//
reg [7:0] spcr; // Serial Peripheral Control Register ('HC11 naming)
wire [7:0] spsr; // Serial Peripheral Status register ('HC11 naming)
reg [7:0] sper; // Serial Peripheral Extension register
reg [7:0] treg; // Transfer register
// fifo signals
wire [7:0] rfdout;
reg wfre, rfwe;
wire rfre, rffull, rfempty;
wire [7:0] wfdin, wfdout;
wire wfwe, wffull, wfempty;
// misc signals
wire tirq; // transfer interrupt (selected number of transfers done)
wire wfov; // write fifo overrun (writing while fifo full)
reg state; // statemachine state
reg ena_mosi; // mosi_o clock-enable
reg [2:0] bcnt;
//
// Wishbone interface
wire wb_acc = cyc_i & stb_i; // WISHBONE access
wire wb_wr = wb_acc & we_i; // WISHBONE write access
// dat_i
always @(posedge clk_i or negedge rst_i)
if (~rst_i)
begin
spcr <= #1 8'h10; // set master bit
sper <= #1 8'h00;
end
else if (wb_wr)
begin
if (adr_i == 2'b00)
spcr <= #1 dat_i | 8'h10; // always set master bit
if (adr_i == 2'b11)
sper <= #1 dat_i;
end
// write fifo
assign wfwe = wb_acc & (adr_i == 2'b10) & ack_o & we_i;
assign wfov = wfwe & wffull;
// dat_o
reg [7:0] dat_o;
always @(posedge clk_i)
case(adr_i) // synopsys full_case parallel_case
2'b00: dat_o <= #1 spcr;
2'b01: dat_o <= #1 spsr;
2'b10: dat_o <= #1 rfdout;
2'b11: dat_o <= #1 sper;
endcase
// read fifo
assign rfre = wb_acc & (adr_i == 2'b10) & ack_o & ~we_i;
// ack_o
reg ack_o;
always @(posedge clk_i or negedge rst_i)
if (~rst_i)
ack_o <= #1 1'b0;
else
ack_o <= #1 wb_acc & !ack_o;
// decode Serial Peripheral Control Register
wire spie = spcr[7]; // Interrupt enable bit
wire spe = spcr[6]; // System Enable bit
wire dwom = spcr[5]; // Port D Wired-OR Mode Bit
wire mstr = spcr[4]; // Master Mode Select Bit
wire cpol = spcr[3]; // Clock Polarity Bit
wire cpha = spcr[2]; // Clock Phase Bit
wire [1:0] spr = spcr[1:0]; // Clock Rate Select Bits
// decode Serial Peripheral Extension Register
wire [1:0] icnt = sper[7:6]; // interrupt on transfer count
wire [1:0] spre = sper[1:0]; // extended clock rate select
wire [3:0] espr = {spre, spr};
// generate status register
wire wr_spsr = wb_wr & (adr_i == 2'b01);
reg spif;
always @(posedge clk_i)
if (~spe)
spif <= #1 1'b0;
else
spif <= #1 (tirq | spif) & ~(wr_spsr & dat_i[7]);
reg wcol;
always @(posedge clk_i)
if (~spe)
wcol <= #1 1'b0;
else
wcol <= #1 (wfov | wcol) & ~(wr_spsr & dat_i[6]);
assign spsr[7] = spif;
assign spsr[6] = wcol;
assign spsr[5:4] = 2'b00;
assign spsr[3] = wffull;
assign spsr[2] = wfempty;
assign spsr[1] = rffull;
assign spsr[0] = rfempty;
// generate IRQ output (inta_o)
reg inta_o;
always @(posedge clk_i)
inta_o <= #1 spif & spie;
//
// hookup read/write buffer fifo
fifo4 #(8)
rfifo(
.clk ( clk_i ),
.rst ( rst_i ),
.clr ( ~spe ),
.din ( treg ),
.we ( rfwe ),
.dout ( rfdout ),
.re ( rfre ),
.full ( rffull ),
.empty ( rfempty )
),
wfifo(
.clk ( clk_i ),
.rst ( rst_i ),
.clr ( ~spe ),
.din ( dat_i ),
.we ( wfwe ),
.dout ( wfdout ),
.re ( wfre ),
.full ( wffull ),
.empty ( wfempty )
);
//
// generate clk divider
reg [9:0] clkcnt;
always @(posedge clk_i)
if(~spe)
clkcnt <= #1 10'h0;
else if (|clkcnt & state)
clkcnt <= #1 clkcnt - 10'h1;
else
case (espr) // synopsys full_case parallel_case
4'h0: clkcnt <= #1 10'h0; // 2
4'h1: clkcnt <= #1 10'h1; // 4
4'h2: clkcnt <= #1 10'h7; // 16
4'h3: clkcnt <= #1 10'hf; // 32
4'h4: clkcnt <= #1 10'h3f; // 128
4'h5: clkcnt <= #1 10'h7f; // 256
4'h6: clkcnt <= #1 10'h1ff; // 1024
4'h7: clkcnt <= #1 10'h3ff; // 2048
endcase
// generate internal SCK
reg sck;
always @(posedge clk_i)
if (~spe)
sck <= #1 1'b0;
else
sck <= #1 sck ^ ~(|clkcnt);
// generate SCK_O
reg sck_o;
always @(posedge clk_i)
sck_o <= #1 sck ^ cpol;
// generate clock-enable signal
reg ena;
always @(posedge clk_i)
ena <= #1 ~(|clkcnt) & (~sck ^ cpha);
// generate ena_mosi (clock data in)
reg hold_ena;
always @(posedge clk_i or negedge rst_i)
if(~rst_i)
hold_ena <= #1 1'b0;
else
hold_ena <= state & (ena | hold_ena) & ~ena_mosi;
always @(posedge clk_i)
ena_mosi <= #1 ~(|clkcnt) & hold_ena;
// store miso
reg smiso;
always @(posedge clk_i)
if(ena)
smiso <= #1 miso_i;
// transfer statemachine
//reg [2:0] bcnt; // bit count
always @(posedge clk_i)
if (~spe)
begin
state <= #1 1'b0; // idle
bcnt <= #1 3'h0;
treg <= #1 8'h00;
wfre <= #1 1'b0;
rfwe <= #1 1'b0;
end
else
begin
wfre <= #1 1'b0;
rfwe <= #1 1'b0;
if(~state) // idle
begin
bcnt <= #1 3'h7; // set transfer counter
treg <= #1 wfdout; // load transfer register
if (~wfempty)
begin
state <= #1 1'b1; // goto transfer state
wfre <= #1 1'b1;
end
end
if(state & ena_mosi)
begin
treg <= #1 {treg[6:0], smiso}; //miso_i};
bcnt <= #1 bcnt -3'h1;
if (~|bcnt)
begin
state <= #1 1'b0; // goto idle state
rfwe <= #1 1'b1;
end
end
end
assign mosi_o = treg[7];
// count number of transfers (for interrupt generation)
reg [1:0] tcnt; // transfer count
always @(posedge clk_i)
if (~spe)
tcnt <= #1 icnt;
else if (rfwe) // rfwe gets asserted when all bits have been transfered
if (|tcnt)
tcnt <= #1 tcnt - 2'h1;
else
tcnt <= #1 icnt;
assign tirq = ~|tcnt & rfwe;
endmodule |
module sky130_fd_sc_ms__a2bb2oi_4 (
Y ,
A1_N,
A2_N,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__a2bb2oi base (
.Y(Y),
.A1_N(A1_N),
.A2_N(A2_N),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule |
module sky130_fd_sc_ms__a2bb2oi_4 (
Y ,
A1_N,
A2_N,
B1 ,
B2
);
output Y ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__a2bb2oi base (
.Y(Y),
.A1_N(A1_N),
.A2_N(A2_N),
.B1(B1),
.B2(B2)
);
endmodule |
module BarrelShifterTestBench;
parameter sim_time = 750*2; // Num of Cycles * 2
reg [31:0] Rs,Rm,IR;
reg SR29_IN;
wire SR29_OUT;
wire [31:0] Out;
//BarrelShifter(input [31] Rs,Rm,IR,input SR29_IN,output SR29_OUT,output [31:0] Out);
BarrelShifter bs(Rs,Rm,IR,SR29_IN,SR29_OUT,Out);
initial fork
Rs=0;Rm=0;IR=0;SR29_IN=0;
#1 Rs=1;#1 Rm=2;#1 IR[4]=1;#1 SR29_IN=0;
#2 Rs=1;#2 Rm=4; #2 SR29_IN=0;
#3 Rs=1;#3 Rm=8; #3 SR29_IN=0;
#4 Rs=8;#4 Rm=1; #4 SR29_IN=0;
#10 Rs=1;#10 Rm=2;#10 IR[6:5]=1;#10 SR29_IN=0;
#11 Rs=1;#11 Rm=4; #11 SR29_IN=0;
#12 Rs=1;#12 Rm=8; #12 SR29_IN=0;
#13 Rs=8;#13 Rm=1; #13 SR29_IN=0;
#20 Rs=1;#20 Rm=2;#20 IR[6:5]=2;#20 SR29_IN=0;
#21 Rs=1;#21 Rm=4; #21 SR29_IN=0;
#22 Rs=1;#22 Rm=8; #22 SR29_IN=0;
#23 Rs=8;#23 Rm=1; #23 SR29_IN=0;
#24 Rs=8;#24 Rm=32'hF0000001; #24 SR29_IN=0;
#30 Rs=1;#30 Rm=2;#30 IR[6:5]=3;#30 SR29_IN=0;
#31 Rs=1;#31 Rm=4; #31 SR29_IN=0;
#32 Rs=1;#32 Rm=8; #32 SR29_IN=0;
#33 Rs=8;#33 Rm=1; #33 SR29_IN=0;
#34 Rs=8;#34 Rm=32'hF0000001; #34 SR29_IN=0;
#40 IR[11:8]=0;#40 IR[7:0]=0;#40 IR[27:25]=1;#40 IR[4]=0;#40 SR29_IN=0;
#41 IR[11:8]=8;#41 IR[7:0] =1 ; #41 SR29_IN=0;
#50 Rs=0;#50 Rm=0;#50 IR[27:25]=3'b101;#50 SR29_IN=0;
join
initial #sim_time $finish;
initial begin
$dumpfile("BarrelShifterTestBench.vcd");
$dumpvars(0,BarrelShifterTestBench);
$display(" Test Results" );
$monitor("Rs=%8h,Rm=%8h,IR=%8h,Out=%8h,SR29_IN=%1b,SR29_OUT=%1b",Rs,Rm,IR,Out,SR29_IN,SR29_OUT);
end
endmodule |
module tx_run_length_limiter #(
parameter LANE_WIDTH =64,
parameter GRANULARITY =4,
parameter RUN_LIMIT =85
)
(
input wire clk,
input wire res_n,
input wire enable,
input wire [LANE_WIDTH-1:0] data_in,
output reg [LANE_WIDTH-1:0] data_out,
output reg rf_bit_flip
);
localparam NUM_CHUNKS = (LANE_WIDTH + GRANULARITY-1)/(GRANULARITY);
localparam REM_BITS = LANE_WIDTH - (GRANULARITY * (LANE_WIDTH/GRANULARITY));
localparam COUNT_BITS = 8;
wire [NUM_CHUNKS-1:0] no_flip;
wire [NUM_CHUNKS-1:0] still_counting_top;
wire [NUM_CHUNKS-1:0] still_counting_bottom;
wire [COUNT_BITS-1:0] count_top;
wire [COUNT_BITS-1:0] count_top_part [NUM_CHUNKS-1:0];
wire [COUNT_BITS-1:0] count_bottom;
wire [COUNT_BITS-1:0] count_bottom_part [NUM_CHUNKS-1:0];
wire bit_flip;
reg [COUNT_BITS-1:0] count_bottom_d1;
reg no_flip_bottom_d1;
reg data_in_bottom_d1;
genvar chunk;
genvar chunkT;
genvar chunkB;
generate
assign no_flip[0] = &( {data_in[GRANULARITY-1:0],data_in_bottom_d1}) ||
&(~{data_in[GRANULARITY-1:0],data_in_bottom_d1});
for(chunk=1; chunk<NUM_CHUNKS-1; chunk=chunk+1) begin : no_flip_gen
assign no_flip[chunk] = &( data_in[(chunk+1)*(GRANULARITY)-1:chunk*(GRANULARITY)-1]) ||
&(~data_in[(chunk+1)*(GRANULARITY)-1:chunk*(GRANULARITY)-1]);
end
assign no_flip[NUM_CHUNKS-1] = &( data_in[LANE_WIDTH-1:(NUM_CHUNKS-1)*(GRANULARITY)-1]) ||
&(~data_in[LANE_WIDTH-1:(NUM_CHUNKS-1)*(GRANULARITY)-1]);
// Start at the top and count until a flip is found
assign still_counting_top[0] = no_flip[0];
assign count_top_part[0] = (no_flip[0] ? GRANULARITY : 0);
for(chunkT=1; chunkT<NUM_CHUNKS; chunkT=chunkT+1) begin : count_top_gen
assign still_counting_top[chunkT] = still_counting_top[chunkT-1] && no_flip[chunkT];
assign count_top_part[chunkT] = (still_counting_top[chunkT] ? GRANULARITY : 0) + count_top_part[chunkT-1];
end
assign count_top = (still_counting_top[NUM_CHUNKS-1] ? LANE_WIDTH : // No flips found
count_top_part[NUM_CHUNKS-2]) + // Take the last value
(no_flip[0] ? (count_bottom_d1 == 0 ? 1 : count_bottom_d1) : 0); // Add the saved count
// Start at the bottom and count until a flip is found
assign still_counting_bottom[0] = no_flip[NUM_CHUNKS-1];
assign count_bottom_part[0] = 0;
for(chunkB=1; chunkB<NUM_CHUNKS; chunkB=chunkB+1) begin : count_bottom_gen
assign still_counting_bottom[chunkB] = still_counting_bottom[chunkB-1] && no_flip[NUM_CHUNKS-1-chunkB];
assign count_bottom_part[chunkB] = (still_counting_bottom[chunkB] ? GRANULARITY : 0) + count_bottom_part[chunkB-1];
end
assign count_bottom = still_counting_bottom[NUM_CHUNKS-1] ? LANE_WIDTH + (count_bottom_d1 == 0 ? 1 : count_bottom_d1) : // No flips found + saved count
count_bottom_part[NUM_CHUNKS-2] + // Take the last value
(no_flip[NUM_CHUNKS-1] ? (REM_BITS ? REM_BITS : GRANULARITY) + 1 : 0); // Add the remainder
endgenerate
assign bit_flip = count_top > (RUN_LIMIT - (GRANULARITY-1) - (REM_BITS ? REM_BITS-1 : GRANULARITY-1));
`ifdef ASYNC_RES
always @(posedge clk or negedge res_n) begin `else
always @(posedge clk) begin `endif
`ifdef RESET_ALL
if(!res_n) begin
data_out <= {DWIDTH {1'b0}};
end else
`endif
begin
if (enable && bit_flip) begin
data_out <= {data_in[LANE_WIDTH-1:1], ~data_in[0]};
end else begin
data_out <= data_in;
end
end
if (!res_n) begin
count_bottom_d1 <= { COUNT_BITS {1'b0}};
no_flip_bottom_d1 <= 1'b0;
data_in_bottom_d1 <= 1'b0;
rf_bit_flip <= 1'b0;
end else begin
count_bottom_d1 <= count_bottom;
no_flip_bottom_d1 <= no_flip[NUM_CHUNKS-1];
data_in_bottom_d1 <= data_in[LANE_WIDTH-1];
if (enable && bit_flip) begin
rf_bit_flip <= bit_flip;
end
end
end
endmodule |
module sky130_fd_sc_hvl__sdfrtp (
Q ,
CLK ,
D ,
SCD ,
SCE ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire buf_Q ;
wire RESET ;
wire mux_out ;
reg notifier ;
wire cond0 ;
wire cond1 ;
wire cond2 ;
wire cond3 ;
wire D_delayed ;
wire SCD_delayed ;
wire SCE_delayed ;
wire RESET_B_delayed;
wire CLK_delayed ;
wire buf0_out_Q ;
// Name Output Other arguments
not not0 (RESET , RESET_B_delayed );
sky130_fd_sc_hvl__udp_mux_2to1 mux_2to10 (mux_out , D_delayed, SCD_delayed, SCE_delayed );
sky130_fd_sc_hvl__udp_dff$PR_pp$PG$N dff0 (buf_Q , mux_out, CLK_delayed, RESET, notifier, VPWR, VGND);
assign cond0 = ( RESET_B_delayed === 1'b1 );
assign cond1 = ( ( SCE_delayed === 1'b0 ) & cond0 );
assign cond2 = ( ( SCE_delayed === 1'b1 ) & cond0 );
assign cond3 = ( ( D_delayed !== SCD_delayed ) & cond0 );
buf buf0 (buf0_out_Q, buf_Q );
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (Q , buf0_out_Q, VPWR, VGND );
endmodule |
module SCELL(input wire valid1,
input wire valid2,
output wire deq1,
output wire deq2,
input wire [`SORTW-1:0] din1,
input wire [`SORTW-1:0] din2,
input wire full,
output wire [`SORTW-1:0] dout,
output wire enq);
wire cmp1 = (din1 < din2);
function [`SORTW-1:0] mux;
input [`SORTW-1:0] a;
input [`SORTW-1:0] b;
input sel;
begin
case (sel)
1'b0: mux = a;
1'b1: mux = b;
endcase
end
endfunction
assign enq = (!full && valid1 && valid2);
assign deq1 = (enq && cmp1);
assign deq2 = (enq && !cmp1);
assign dout = mux(din2, din1, cmp1);
endmodule |
module MRE2 #(parameter FIFO_SIZE = 1, // dummy, just for portability
parameter FIFO_WIDTH = 32) // fifo width in bit
(input wire CLK,
input wire RST,
input wire enq,
input wire deq,
input wire [FIFO_WIDTH-1:0] din,
output wire [FIFO_WIDTH-1:0] dot,
output wire emp,
output wire full,
output reg [FIFO_SIZE:0] cnt);
reg head, tail;
reg [FIFO_WIDTH-1:0] mem [(1<<FIFO_SIZE)-1:0];
assign emp = (cnt==0);
assign full = (cnt==2);
assign dot = mem[head];
always @(posedge CLK) begin
if (RST) {cnt, head, tail} <= 0;
else begin
case ({enq, deq})
2'b01: begin head<=~head; cnt<=cnt-1; end
2'b10: begin mem[tail]<=din; tail<=~tail; cnt<=cnt+1; end
2'b11: begin mem[tail]<=din; head<=~head; tail<=~tail; end
endcase
end
end
endmodule |
module BFIFO #(parameter FIFO_SIZE = 2, // size in log scale, 2 for 4 entry, 3 for 8 entry
parameter FIFO_WIDTH = 32) // fifo width in bit
(input wire CLK,
input wire RST,
input wire enq,
input wire deq,
input wire [FIFO_WIDTH-1:0] din,
output reg [FIFO_WIDTH-1:0] dot,
output wire emp,
output wire full,
output reg [FIFO_SIZE:0] cnt);
reg [FIFO_SIZE-1:0] head, tail;
reg [FIFO_WIDTH-1:0] mem [(1<<FIFO_SIZE)-1:0];
assign emp = (cnt==0);
assign full = (cnt==(1<<FIFO_SIZE));
always @(posedge CLK) dot <= mem[head];
always @(posedge CLK) begin
if (RST) {cnt, head, tail} <= 0;
else begin
case ({enq, deq})
2'b01: begin head<=head+1; cnt<=cnt-1; end
2'b10: begin mem[tail]<=din; tail<=tail+1; cnt<=cnt+1; end
2'b11: begin mem[tail]<=din; head<=head+1; tail<=tail+1; end
endcase
end
end
endmodule |
module's enqueue signal
output reg im_req); // DRAM data request
wire req;
reg deq;
wire [`DRAMW-1:0] im_dot;
wire [`IB_SIZE:0] im_cnt;
wire im_full, im_emp;
wire im_enq = den; // (!im_full && den);
wire im_deq = (req && !im_emp);
always @(posedge CLK) im_req <= (im_cnt<`REQ_THRE);
always @(posedge CLK) deq <= im_deq;
BFIFO #(`IB_SIZE, `DRAMW) // note, using BRAM
imf(.CLK(CLK), .RST(RST), .enq(im_enq), .deq(im_deq), .din(din),
.dot(im_dot), .emp(im_emp), .full(im_full), .cnt(im_cnt));
INMOD inmod(.CLK(CLK), .RST(RST), .d_dout(im_dot), .d_douten(deq),
.IB_full(IB_full), .im_dot(dot), .IB_enq(IB_enq), .im_req(req));
endmodule |
module
assign im_req = (im_emp || im_deq); // note!!!
assign im_dot = mux(dot_t[31:0], dot[31:0], cntez);
always @(posedge CLK) begin
if (RST) begin
cnte <= 0;
end else begin
if (IB_enq) cnte <= cnte + 1;
end
end
always @(posedge CLK) begin
if (RST) begin
cntez <= 1;
end else begin
case ({IB_enq, (cnte==15)})
2'b10: cntez <= 0;
2'b11: cntez <= 1;
endcase
end
end
always @(posedge CLK) begin
if (RST) begin
cntef <= 0;
end else begin
case ({IB_enq, (cnte==14)})
2'b10: cntef <= 0;
2'b11: cntef <= 1;
endcase
end
end
always @(posedge CLK) begin
case ({IB_enq, cntez})
2'b10: dot_t <= {32'b0, dot_t[`DRAMW-1:32]};
2'b11: dot_t <= {32'b0, dot[`DRAMW-1:32]};
endcase
end
MRE2 #(1, `DRAMW) imf(.CLK(CLK), .RST(RST), .enq(im_enq), .deq(im_deq),
.din(d_dout), .dot(dot), .emp(im_emp), .full(im_full));
endmodule |
module's enqueue
function mux1;
input a;
input b;
input sel;
begin
case (sel)
1'b0: mux1 = a;
1'b1: mux1 = b;
endcase
end
endfunction
function [`SORTW-1:0] mux32;
input [`SORTW-1:0] a;
input [`SORTW-1:0] b;
input sel;
begin
case (sel)
1'b0: mux32 = a;
1'b1: mux32 = b;
endcase
end
endfunction
/*****************************************/
wire [`SORTW-1:0] F_dout;
wire F_deq, F_emp;
reg [31:0] ecnt; // the number of elements in one iteration
reg ecntz; // ecnt==0 ?
wire f_full;
MRE2 #(1,`SORTW) F(.CLK(CLK), .RST(RST), .enq(ib_enq), .deq(F_deq), // input buffer FIFO
.din(din), .dot(F_dout), .emp(F_emp), .full(f_full));
assign ib_full = mux1(f_full, 0, F_deq); // INBUF back_pressure
/*****************************************/
assign enq = !full && (!F_emp || ecntz); // enqueue for the next buffer
assign F_deq = enq && (ecnt!=0); //
assign dot = mux32(F_dout, `MAX_VALUE, ecntz);
always @(posedge CLK) begin
if (RST || idone) begin
ecnt <= (`ELEMS_PER_UNIT << (phase * `WAY_LOG)); /// note
ecntz <= 0;
end else begin
if (ecnt!=0 && enq) ecnt <= ecnt - 1;
if (ecnt==1 && enq) ecntz <= 1; // old version has a bug here!
end
end
endmodule |
module STREE(input wire CLK,
input wire RST_in,
input wire irst,
input wire frst,
input wire [`PHASE_W] phase_in,
input wire [`SORTW*`SORT_WAY-1:0] s_din, // sorting-tree input data
input wire [`SORT_WAY-1:0] enq, // enqueue
output wire [`SORT_WAY-1:0] full, // buffer is full ?
input wire deq, // dequeue
output wire [`SORTW-1:0] dot, // output data
output wire emp);
reg RST;
always @(posedge CLK) RST <= RST_in;
reg [`PHASE_W] phase;
always @(posedge CLK) phase <= phase_in;
wire [`SORTW-1:0] d00, d01, d02, d03;
assign {d00, d01, d02, d03} = s_din;
wire F01_enq, F01_deq, F01_emp, F01_full; wire [31:0] F01_din, F01_dot; wire [1:0] F01_cnt;
wire F02_enq, F02_deq, F02_emp, F02_full; wire [31:0] F02_din, F02_dot; wire [1:0] F02_cnt;
wire F03_enq, F03_deq, F03_emp, F03_full; wire [31:0] F03_din, F03_dot; wire [1:0] F03_cnt;
wire F04_enq, F04_deq, F04_emp, F04_full; wire [31:0] F04_din, F04_dot; wire [1:0] F04_cnt;
wire F05_enq, F05_deq, F05_emp, F05_full; wire [31:0] F05_din, F05_dot; wire [1:0] F05_cnt;
wire F06_enq, F06_deq, F06_emp, F06_full; wire [31:0] F06_din, F06_dot; wire [1:0] F06_cnt;
wire F07_enq, F07_deq, F07_emp, F07_full; wire [31:0] F07_din, F07_dot; wire [1:0] F07_cnt;
INBUF IN04(CLK, RST, full[0], F04_full, F04_enq, d00, F04_din, enq[0], phase, irst);
INBUF IN05(CLK, RST, full[1], F05_full, F05_enq, d01, F05_din, enq[1], phase, irst);
INBUF IN06(CLK, RST, full[2], F06_full, F06_enq, d02, F06_din, enq[2], phase, irst);
INBUF IN07(CLK, RST, full[3], F07_full, F07_enq, d03, F07_din, enq[3], phase, irst);
MRE2 #(1,32) F01(CLK, frst, F01_enq, F01_deq, F01_din, F01_dot, F01_emp, F01_full, F01_cnt);
MRE2 #(1,32) F02(CLK, frst, F02_enq, F02_deq, F02_din, F02_dot, F02_emp, F02_full, F02_cnt);
MRE2 #(1,32) F03(CLK, frst, F03_enq, F03_deq, F03_din, F03_dot, F03_emp, F03_full, F03_cnt);
MRE2 #(1,32) F04(CLK, frst, F04_enq, F04_deq, F04_din, F04_dot, F04_emp, F04_full, F04_cnt);
MRE2 #(1,32) F05(CLK, frst, F05_enq, F05_deq, F05_din, F05_dot, F05_emp, F05_full, F05_cnt);
MRE2 #(1,32) F06(CLK, frst, F06_enq, F06_deq, F06_din, F06_dot, F06_emp, F06_full, F06_cnt);
MRE2 #(1,32) F07(CLK, frst, F07_enq, F07_deq, F07_din, F07_dot, F07_emp, F07_full, F07_cnt);
SCELL S01(!F02_emp, !F03_emp, F02_deq, F03_deq, F02_dot, F03_dot, F01_full, F01_din, F01_enq);
SCELL S02(!F04_emp, !F05_emp, F04_deq, F05_deq, F04_dot, F05_dot, F02_full, F02_din, F02_enq);
SCELL S03(!F06_emp, !F07_emp, F06_deq, F07_deq, F06_dot, F07_dot, F03_full, F03_din, F03_enq);
assign F01_deq = deq;
assign dot = F01_dot;
assign emp = F01_emp;
endmodule |
module OTMOD(input wire CLK,
input wire RST,
input wire F01_deq,
input wire [`SORTW-1:0] F01_dot,
input wire OB_deq,
output wire [`DRAMW-1:0] OB_dot,
output wire OB_full,
output reg OB_req);
reg [3:0] ob_buf_t_cnt; // counter for temporary register
reg ob_enque;
reg [`DRAMW-1:0] ob_buf_t;
wire [`DRAMW-1:0] OB_din = ob_buf_t;
wire OB_enq = ob_enque;
wire [`OB_SIZE:0] OB_cnt;
always @(posedge CLK) OB_req <= (OB_cnt>=`DRAM_WBLOCKS);
always @(posedge CLK) begin
if (F01_deq) ob_buf_t <= {F01_dot, ob_buf_t[`DRAMW-1:32]};
end
always @(posedge CLK) begin
if (RST) begin
ob_buf_t_cnt <= 0;
end else begin
if (F01_deq) ob_buf_t_cnt <= ob_buf_t_cnt + 1;
end
end
always @(posedge CLK) ob_enque <= (F01_deq && ob_buf_t_cnt == 15);
BFIFO #(`OB_SIZE, `DRAMW) OB(.CLK(CLK), .RST(RST), .enq(OB_enq), .deq(OB_deq),
.din(OB_din), .dot(OB_dot), .full(OB_full), .cnt(OB_cnt));
endmodule |
module COMPARATOR #(parameter WIDTH = 32)
(input wire [WIDTH-1:0] DIN0,
input wire [WIDTH-1:0] DIN1,
output wire [WIDTH-1:0] DOUT0,
output wire [WIDTH-1:0] DOUT1);
wire comp_rslt = (DIN0 < DIN1);
function [WIDTH-1:0] mux;
input [WIDTH-1:0] a;
input [WIDTH-1:0] b;
input sel;
begin
case (sel)
1'b0: mux = a;
1'b1: mux = b;
endcase
end
endfunction
assign DOUT0 = mux(DIN1, DIN0, comp_rslt);
assign DOUT1 = mux(DIN0, DIN1, comp_rslt);
endmodule |
module SORTINGNETWORK(input wire CLK,
input wire RST_IN,
input wire [`SRTP_WAY:0] DATAEN_IN,
input wire [511:0] DIN_T,
output reg [511:0] DOUT,
output reg [`SRTP_WAY:0] DATAEN_OUT);
reg RST;
reg [511:0] DIN;
reg [`SRTP_WAY:0] DATAEN;
always @(posedge CLK) RST <= RST_IN;
always @(posedge CLK) DIN <= DIN_T;
always @(posedge CLK) DATAEN <= (RST) ? 0 : DATAEN_IN;
// Stage A
////////////////////////////////////////////////////////////////////////////////////////////////
wire [`WW] A15,A14,A13,A12,A11,A10,A09,A08,A07,A06,A05,A04,A03,A02,A01,A00; // output
wire [`WW] a15,a14,a13,a12,a11,a10,a09,a08,a07,a06,a05,a04,a03,a02,a01,a00; // input
assign {a15,a14,a13,a12,a11,a10,a09,a08,a07,a06,a05,a04,a03,a02,a01,a00} = DIN;
COMPARATOR comp00(a00, a01, A00, A01);
COMPARATOR comp01(a02, a03, A02, A03);
COMPARATOR comp02(a04, a05, A04, A05);
COMPARATOR comp03(a06, a07, A06, A07);
COMPARATOR comp04(a08, a09, A08, A09);
COMPARATOR comp05(a10, a11, A10, A11);
COMPARATOR comp06(a12, a13, A12, A13);
COMPARATOR comp07(a14, a15, A14, A15);
reg [511:0] pdA; // pipeline regester A for data
reg [`SRTP_WAY:0] pcA; // pipeline regester A for control
always @(posedge CLK) pdA <= {A15,A14,A13,A12,A11,A10,A09,A08,A07,A06,A05,A04,A03,A02,A01,A00};
always @(posedge CLK) pcA <= (RST) ? 0 : DATAEN;
// Stage B
////////////////////////////////////////////////////////////////////////////////////////////////
wire [`WW] B15,B14,B13,B12,B11,B10,B09,B08,B07,B06,B05,B04,B03,B02,B01,B00; // output
wire [`WW] b15,b14,b13,b12,b11,b10,b09,b08,b07,b06,b05,b04,b03,b02,b01,b00; // input
assign {b15,b14,b13,b12,b11,b10,b09,b08,b07,b06,b05,b04,b03,b02,b01,b00} = pdA;
COMPARATOR comp10(b00, b02, B00, B02);
COMPARATOR comp11(b04, b06, B04, B06);
COMPARATOR comp12(b08, b10, B08, B10);
COMPARATOR comp13(b12, b14, B12, B14);
COMPARATOR comp14(b01, b03, B01, B03);
COMPARATOR comp15(b05, b07, B05, B07);
COMPARATOR comp16(b09, b11, B09, B11);
COMPARATOR comp17(b13, b15, B13, B15);
reg [511:0] pdB; // pipeline regester A for data
reg [`SRTP_WAY:0] pcB; // pipeline regester A for control
always @(posedge CLK) pdB <= {B15,B14,B13,B12,B11,B10,B09,B08,B07,B06,B05,B04,B03,B02,B01,B00};
always @(posedge CLK) pcB <= (RST) ? 0 : pcA;
// Stage C
////////////////////////////////////////////////////////////////////////////////////////////////
wire [`WW] C15,C14,C13,C12,C11,C10,C09,C08,C07,C06,C05,C04,C03,C02,C01,C00; // output
wire [`WW] c15,c14,c13,c12,c11,c10,c09,c08,c07,c06,c05,c04,c03,c02,c01,c00; // input
assign {c15,c14,c13,c12,c11,c10,c09,c08,c07,c06,c05,c04,c03,c02,c01,c00} = pdB;
assign {C00,C03,C04,C07,C08,C11,C12,C15} = {c00,c03,c04,c07,c08,c11,c12,c15};
COMPARATOR comp20(c01, c02, C01, C02);
COMPARATOR comp21(c05, c06, C05, C06);
COMPARATOR comp22(c09, c10, C09, C10);
COMPARATOR comp23(c13, c14, C13, C14);
reg [511:0] pdC; // pipeline regester A for data
reg [`SRTP_WAY:0] pcC; // pipeline regester A for control
always @(posedge CLK) pdC <= {C15,C14,C13,C12,C11,C10,C09,C08,C07,C06,C05,C04,C03,C02,C01,C00};
always @(posedge CLK) pcC <= (RST) ? 0 : pcB;
// Stage D
////////////////////////////////////////////////////////////////////////////////////////////////
wire [`WW] D15,D14,D13,D12,D11,D10,D09,D08,D07,D06,D05,D04,D03,D02,D01,D00; // output
wire [`WW] d15,d14,d13,d12,d11,d10,d09,d08,d07,d06,d05,d04,d03,d02,d01,d00; // input
assign {d15,d14,d13,d12,d11,d10,d09,d08,d07,d06,d05,d04,d03,d02,d01,d00} = pdC;
COMPARATOR comp30(d00, d04, D00, D04);
COMPARATOR comp31(d08, d12, D08, D12);
COMPARATOR comp32(d01, d05, D01, D05);
COMPARATOR comp33(d09, d13, D09, D13);
COMPARATOR comp34(d02, d06, D02, D06);
COMPARATOR comp35(d10, d14, D10, D14);
COMPARATOR comp36(d03, d07, D03, D07);
COMPARATOR comp37(d11, d15, D11, D15);
reg [511:0] pdD; // pipeline regester A for data
reg [`SRTP_WAY:0] pcD; // pipeline regester A for control
always @(posedge CLK) pdD <= {D15,D14,D13,D12,D11,D10,D09,D08,D07,D06,D05,D04,D03,D02,D01,D00};
always @(posedge CLK) pcD <= (RST) ? 0 : pcC;
// Stage E
////////////////////////////////////////////////////////////////////////////////////////////////
wire [`WW] E15,E14,E13,E12,E11,E10,E09,E08,E07,E06,E05,E04,E03,E02,E01,E00; // output
wire [`WW] e15,e14,e13,e12,e11,e10,e09,e08,e07,e06,e05,e04,e03,e02,e01,e00; // input
assign {e15,e14,e13,e12,e11,e10,e09,e08,e07,e06,e05,e04,e03,e02,e01,e00} = pdD;
assign {E00,E01,E06,E07,E08,E09,E14,E15} = {e00,e01,e06,e07,e08,e09,e14,e15};
COMPARATOR comp40(e02, e04, E02, E04);
COMPARATOR comp41(e10, e12, E10, E12);
COMPARATOR comp42(e03, e05, E03, E05);
COMPARATOR comp43(e11, e13, E11, E13);
reg [511:0] pdE; // pipeline regester A for data
reg [`SRTP_WAY:0] pcE; // pipeline regester A for control
always @(posedge CLK) pdE <= {E15,E14,E13,E12,E11,E10,E09,E08,E07,E06,E05,E04,E03,E02,E01,E00};
always @(posedge CLK) pcE <= (RST) ? 0 : pcD;
// Stage F
////////////////////////////////////////////////////////////////////////////////////////////////
wire [`WW] F15,F14,F13,F12,F11,F10,F09,F08,F07,F06,F05,F04,F03,F02,F01,F00; // output
wire [`WW] f15,f14,f13,f12,f11,f10,f09,f08,f07,f06,f05,f04,f03,f02,f01,f00; // input
assign {f15,f14,f13,f12,f11,f10,f09,f08,f07,f06,f05,f04,f03,f02,f01,f00} = pdE;
assign {F00,F07,F08,F15} = {f00,f07,f08,f15};
COMPARATOR comp50(f01, f02, F01, F02);
COMPARATOR comp51(f03, f04, F03, F04);
COMPARATOR comp52(f05, f06, F05, F06);
COMPARATOR comp53(f09, f10, F09, F10);
COMPARATOR comp54(f11, f12, F11, F12);
COMPARATOR comp55(f13, f14, F13, F14);
reg [511:0] pdF; // pipeline regester A for data
reg [`SRTP_WAY:0] pcF; // pipeline regester A for control
always @(posedge CLK) pdF <= {F15,F14,F13,F12,F11,F10,F09,F08,F07,F06,F05,F04,F03,F02,F01,F00};
always @(posedge CLK) pcF <= (RST) ? 0 : pcE;
// Stage G
////////////////////////////////////////////////////////////////////////////////////////////////
wire [`WW] G15,G14,G13,G12,G11,G10,G09,G08,G07,G06,G05,G04,G03,G02,G01,G00; // output
wire [`WW] g15,g14,g13,g12,g11,g10,g09,g08,g07,g06,g05,g04,g03,g02,g01,g00; // input
assign {g15,g14,g13,g12,g11,g10,g09,g08,g07,g06,g05,g04,g03,g02,g01,g00} = pdF;
COMPARATOR comp60(g00, g08, G00, G08);
COMPARATOR comp61(g01, g09, G01, G09);
COMPARATOR comp62(g02, g10, G02, G10);
COMPARATOR comp63(g03, g11, G03, G11);
COMPARATOR comp64(g04, g12, G04, G12);
COMPARATOR comp65(g05, g13, G05, G13);
COMPARATOR comp66(g06, g14, G06, G14);
COMPARATOR comp67(g07, g15, G07, G15);
reg [511:0] pdG; // pipeline regester A for data
reg [`SRTP_WAY:0] pcG; // pipeline regester A for control
always @(posedge CLK) pdG <= {G15,G14,G13,G12,G11,G10,G09,G08,G07,G06,G05,G04,G03,G02,G01,G00};
always @(posedge CLK) pcG <= (RST) ? 0 : pcF;
// Stage H
////////////////////////////////////////////////////////////////////////////////////////////////
wire [`WW] H15,H14,H13,H12,H11,H10,H09,H08,H07,H06,H05,H04,H03,H02,H01,H00; // output
wire [`WW] h15,h14,h13,h12,h11,h10,h09,h08,h07,h06,h05,h04,h03,h02,h01,h00; // input
assign {h15,h14,h13,h12,h11,h10,h09,h08,h07,h06,h05,h04,h03,h02,h01,h00} = pdG;
assign {H00,H01,H02,H03,H12,H13,H14,H15} = {h00,h01,h02,h03,h12,h13,h14,h15};
COMPARATOR comp70(h04, h08, H04, H08);
COMPARATOR comp71(h05, h09, H05, H09);
COMPARATOR comp72(h06, h10, H06, H10);
COMPARATOR comp73(h07, h11, H07, H11);
reg [511:0] pdH; // pipeline regester A for data
reg [`SRTP_WAY:0] pcH; // pipeline regester A for control
always @(posedge CLK) pdH <= {H15,H14,H13,H12,H11,H10,H09,H08,H07,H06,H05,H04,H03,H02,H01,H00};
always @(posedge CLK) pcH <= (RST) ? 0 : pcG;
// Stage I
////////////////////////////////////////////////////////////////////////////////////////////////
wire [`WW] I15,I14,I13,I12,I11,I10,I09,I08,I07,I06,I05,I04,I03,I02,I01,I00; // output
wire [`WW] i15,i14,i13,i12,i11,i10,i09,i08,i07,i06,i05,i04,i03,i02,i01,i00; // input
assign {i15,i14,i13,i12,i11,i10,i09,i08,i07,i06,i05,i04,i03,i02,i01,i00} = pdH;
assign {I00,I01,I14,I15} = {i00,i01,i14,i15};
COMPARATOR comp80(i02, i04, I02, I04);
COMPARATOR comp81(i06, i08, I06, I08);
COMPARATOR comp82(i10, i12, I10, I12);
COMPARATOR comp83(i03, i05, I03, I05);
COMPARATOR comp84(i07, i09, I07, I09);
COMPARATOR comp85(i11, i13, I11, I13);
reg [511:0] pdI; // pipeline regester A for data
reg [`SRTP_WAY:0] pcI; // pipeline regester A for control
always @(posedge CLK) pdI <= {I15,I14,I13,I12,I11,I10,I09,I08,I07,I06,I05,I04,I03,I02,I01,I00};
always @(posedge CLK) pcI <= (RST) ? 0 : pcH;
// Stage J
////////////////////////////////////////////////////////////////////////////////////////////////
wire [`WW] J15,J14,J13,J12,J11,J10,J09,J08,J07,J06,J05,J04,J03,J02,J01,J00; // output
wire [`WW] j15,j14,j13,j12,j11,j10,j09,j08,j07,j06,j05,j04,j03,j02,j01,j00; // input
assign {j15,j14,j13,j12,j11,j10,j09,j08,j07,j06,j05,j04,j03,j02,j01,j00} = pdI;
assign {J00,J15} = {j00,j15};
COMPARATOR comp90(j01, j02, J01, J02);
COMPARATOR comp91(j03, j04, J03, J04);
COMPARATOR comp92(j05, j06, J05, J06);
COMPARATOR comp93(j07, j08, J07, J08);
COMPARATOR comp94(j09, j10, J09, J10);
COMPARATOR comp95(j11, j12, J11, J12);
COMPARATOR comp96(j13, j14, J13, J14);
always @(posedge CLK) DOUT <= {J15,J14,J13,J12,J11,J10,J09,J08,J07,J06,J05,J04,J03,J02,J01,J00};
always @(posedge CLK) DATAEN_OUT <= (RST) ? 0 : pcI;
endmodule |
module XORSHIFT #(parameter WIDTH = 32,
parameter SEED = 1)
(input wire CLK,
input wire RST,
input wire EN,
output wire [WIDTH-1:0] RAND_VAL);
reg [WIDTH-1:0] x;
reg [WIDTH-1:0] y;
reg [WIDTH-1:0] z;
reg [WIDTH-1:0] w;
wire [WIDTH-1:0] t = x^(x<<11);
// Mask MSB for not generating the maximum value
assign RAND_VAL = {1'b0, w[WIDTH-2:0]};
reg ocen;
always @(posedge CLK) ocen <= RST;
always @(posedge CLK) begin
if (RST) begin
x <= 123456789;
y <= 362436069;
z <= 521288629;
w <= 88675123 ^ SEED;
end else begin
if (EN || ocen) begin
x <= y;
y <= z;
z <= w;
w <= (w^(w>>19))^(t^(t>>8));
end
end
end
endmodule |
module CORE_W(input wire CLK, // clock
input wire RST_in, // reset
output reg initdone, // dram initialize is done
output reg sortdone, // sort is finished
input wire d_busy_in, // DRAM busy
input wire [1:0] d_mode_in, // DRAM mode
input wire din_bit, // DRAM data out
input wire din_en_in, // DRAM data out enable
output reg [3:0] data_out, // DRAM data in
input wire d_w_in, // DRAM write flag
output reg [1:0] d_req, // DRAM REQ access request (read/write)
output reg [31:0] d_initadr, // DRAM REQ initial address for the access
output reg [31:0] d_blocks, // DRAM REQ the number of blocks per one access
output wire ERROR); //
reg RST; always @(posedge CLK) RST <= RST_in;
wire initdone_w; always @(posedge CLK) initdone <= initdone_w;
wire sortdone_w; always @(posedge CLK) sortdone <= sortdone_w;
reg d_busy; always @(posedge CLK) d_busy <= d_busy_in;
reg [1:0] d_mode; always @(posedge CLK) d_mode <= d_mode_in;
reg [`DRAMW-1:0] din; always @(posedge CLK) din <= (RST) ? 0 : {din[`DRAMW-2:0], din_bit};
reg din_en; always @(posedge CLK) din_en <= din_en_in;
wire [1:0] d_req_w; always @(posedge CLK) d_req <= d_req_w;
wire dout_en;
wire [`DRAMW-1:0] dout;
reg [`DRAMW-1:0] dout_r;
always @(posedge CLK) dout_r <= dout;
reg d_w; always @(posedge CLK) d_w <= d_w_in;
always @(posedge CLK) data_out <= {^dout_r[127:0], ^dout_r[128+127:128],
^dout_r[256+127:256], ^dout_r[384+127:384]};
wire [31:0] d_initadr_w, d_blocks_w;
always @(posedge CLK) d_initadr <= d_initadr_w;
always @(posedge CLK) d_blocks <= d_blocks_w;
CORE core(CLK, RST, initdone_w, sortdone_w,
d_busy, dout, d_w, din, din_en, d_req_w, d_initadr_w, d_blocks_w, ERROR);
endmodule |
module
always @(posedge CLK) RST_INI <= RSTa;
reg [`SORTW-1:0] i_p,i_o,i_n,i_m,i_l,i_k,i_j,i_i,i_h,i_g,i_f,i_e,i_d,i_c,i_b,i_a;
generate
if (`INITTYPE == "xorshift") begin
wire [`SORTW-1:0] r15,r14,r13,r12,r11,r10,r09,r08,r07,r06,r05,r04,r03,r02,r01,r00;
XORSHIFT #(`SORTW, 32'h00000001) xorshift00(CLK, RST_INI, d_w, r00);
XORSHIFT #(`SORTW, 32'h00000002) xorshift01(CLK, RST_INI, d_w, r01);
XORSHIFT #(`SORTW, 32'h00000004) xorshift02(CLK, RST_INI, d_w, r02);
XORSHIFT #(`SORTW, 32'h00000008) xorshift03(CLK, RST_INI, d_w, r03);
XORSHIFT #(`SORTW, 32'h00000010) xorshift04(CLK, RST_INI, d_w, r04);
XORSHIFT #(`SORTW, 32'h00000020) xorshift05(CLK, RST_INI, d_w, r05);
XORSHIFT #(`SORTW, 32'h00000040) xorshift06(CLK, RST_INI, d_w, r06);
XORSHIFT #(`SORTW, 32'h00000080) xorshift07(CLK, RST_INI, d_w, r07);
XORSHIFT #(`SORTW, 32'h00000100) xorshift08(CLK, RST_INI, d_w, r08);
XORSHIFT #(`SORTW, 32'h00000200) xorshift09(CLK, RST_INI, d_w, r09);
XORSHIFT #(`SORTW, 32'h00000400) xorshift10(CLK, RST_INI, d_w, r10);
XORSHIFT #(`SORTW, 32'h00000800) xorshift11(CLK, RST_INI, d_w, r11);
XORSHIFT #(`SORTW, 32'h00001000) xorshift12(CLK, RST_INI, d_w, r12);
XORSHIFT #(`SORTW, 32'h00002000) xorshift13(CLK, RST_INI, d_w, r13);
XORSHIFT #(`SORTW, 32'h00004000) xorshift14(CLK, RST_INI, d_w, r14);
XORSHIFT #(`SORTW, 32'h00008000) xorshift15(CLK, RST_INI, d_w, r15);
always @(posedge CLK) begin
i_a <= r00;
i_b <= r01;
i_c <= r02;
i_d <= r03;
i_e <= r04;
i_f <= r05;
i_g <= r06;
i_h <= r07;
i_i <= r08;
i_j <= r09;
i_k <= r10;
i_l <= r11;
i_m <= r12;
i_n <= r13;
i_o <= r14;
i_p <= r15;
end
end else if (`INITTYPE == "reverse") begin
always @(posedge CLK) begin
if (RST_INI) begin
i_a <= `SORT_ELM+16;
i_b <= `SORT_ELM+16-1;
i_c <= `SORT_ELM+16-2;
i_d <= `SORT_ELM+16-3;
i_e <= `SORT_ELM+16-4;
i_f <= `SORT_ELM+16-5;
i_g <= `SORT_ELM+16-6;
i_h <= `SORT_ELM+16-7;
i_i <= `SORT_ELM+16-8;
i_j <= `SORT_ELM+16-9;
i_k <= `SORT_ELM+16-10;
i_l <= `SORT_ELM+16-11;
i_m <= `SORT_ELM+16-12;
i_n <= `SORT_ELM+16-13;
i_o <= `SORT_ELM+16-14;
i_p <= `SORT_ELM+16-15;
end else begin
if (d_w) begin
i_a <= i_a-16;
i_b <= i_b-16;
i_c <= i_c-16;
i_d <= i_d-16;
i_e <= i_e-16;
i_f <= i_f-16;
i_g <= i_g-16;
i_h <= i_h-16;
i_i <= i_i-16;
i_j <= i_j-16;
i_k <= i_k-16;
i_l <= i_l-16;
i_m <= i_m-16;
i_n <= i_n-16;
i_o <= i_o-16;
i_p <= i_p-16;
end
end
end
end else if (`INITTYPE == "sorted") begin
reg ocen;
always @(posedge CLK) begin
if (RST_INI) begin
ocen <= 0;
i_a <= 1;
i_b <= 2;
i_c <= 3;
i_d <= 4;
i_e <= 5;
i_f <= 6;
i_g <= 7;
i_h <= 8;
i_i <= 9;
i_j <= 10;
i_k <= 11;
i_l <= 12;
i_m <= 13;
i_n <= 14;
i_o <= 15;
i_p <= 16;
end else begin
if (d_w) begin
ocen <= 1;
i_a <= mux32(i_a, i_a+16, ocen);
i_b <= mux32(i_b, i_b+16, ocen);
i_c <= mux32(i_c, i_c+16, ocen);
i_d <= mux32(i_d, i_d+16, ocen);
i_e <= mux32(i_e, i_e+16, ocen);
i_f <= mux32(i_f, i_f+16, ocen);
i_g <= mux32(i_g, i_g+16, ocen);
i_h <= mux32(i_h, i_h+16, ocen);
i_i <= mux32(i_i, i_i+16, ocen);
i_j <= mux32(i_j, i_j+16, ocen);
i_k <= mux32(i_k, i_k+16, ocen);
i_l <= mux32(i_l, i_l+16, ocen);
i_m <= mux32(i_m, i_m+16, ocen);
i_n <= mux32(i_n, i_n+16, ocen);
i_o <= mux32(i_o, i_o+16, ocen);
i_p <= mux32(i_p, i_p+16, ocen);
end
end
end
end
endgenerate
always @(posedge CLK) idone_a <= initdone;
always @(posedge CLK) idone_b <= initdone;
always @(posedge CLK) idone_c <= initdone;
always @(posedge CLK) idone_d <= initdone;
assign d_din[255: 0] = mux256({i_h,i_g,i_f,i_e,i_d,i_c,i_b,i_a},
mux4in256(OB_dot0[255:0], OB_dot1[255:0], OB_dot2[255:0], OB_dot3[255:0], OB_dot_sel),
idone_a);
assign d_din[511:256] = mux256({i_p,i_o,i_n,i_m,i_l,i_k,i_j,i_i},
mux4in256(OB_dot0[511:256], OB_dot1[511:256], OB_dot2[511:256], OB_dot3[511:256], OB_dot_sel),
idone_b);
/**********************************************************************************************/
always @(posedge CLK) begin
dout_t <= d_dout;
doen_t <= d_douten;
// Stage 0
////////////////////////////////////
dout_tta <= stnet_dout;
dout_ttb <= stnet_dout;
doen_tta <= stnet_douten[0];
doen_ttb <= stnet_douten[0];
req_tt0_a <= stnet_douten[`SORT_WAY:1];
req_tt0_b <= stnet_douten[`SORT_WAY*2:`SORT_WAY+1];
req_tt0_c <= stnet_douten[`SORT_WAY*3:`SORT_WAY*2+1];
req_tt0_d <= stnet_douten[`SORT_WAY*4:`SORT_WAY*3+1];
// Stage 1
////////////////////////////////////
dout_t0_a <= dout_tta;
dout_t0_b <= dout_tta;
dout_t0_c <= dout_ttb;
dout_t0_d <= dout_ttb;
doen_t0_a <= doen_tta;
doen_t0_b <= doen_tta;
doen_t0_c <= doen_ttb;
doen_t0_d <= doen_ttb;
req_tt1_a <= req_tt0_a;
req_tt1_b <= req_tt0_b;
req_tt1_c <= req_tt0_c;
req_tt1_d <= req_tt0_d;
end
// for last_phase
// ###########################################################################
always @(posedge CLK) begin
if (RSTa) begin
last_phase <= 0;
end else begin
if (last_phase_a && last_phase_b) last_phase <= 1;
end
end
always @(posedge CLK) begin
if (RSTa) begin
last_phase_a <= 0;
end else begin
if (pexe_done_a && pexe_done_b) last_phase_a <= 1;
end
end
always @(posedge CLK) begin
if (RSTb) begin
last_phase_b <= 0;
end else begin
if (pexe_done_c && pexe_done_d) last_phase_b <= 1;
end
end
// for phase
// ###########################################################################
always @(posedge CLK) begin
if (RSTa) begin
phase <= `LAST_PHASE;
end else begin
if (elem==`SORT_ELM) phase <= phase+1;
end
end
always @(posedge CLK) begin
if (RSTa) begin
phase_a <= 0;
end else begin
if (elem_a==`SRTP_ELM) phase_a <= phase_a+1;
end
end
always @(posedge CLK) begin
if (RSTb) begin
phase_b <= 0;
end else begin
if (elem_b==`SRTP_ELM) phase_b <= phase_b+1;
end
end
always @(posedge CLK) begin
if (RSTc) begin
phase_c <= 0;
end else begin
if (elem_c==`SRTP_ELM) phase_c <= phase_c+1;
end
end
always @(posedge CLK) begin
if (RSTd) begin
phase_d <= 0;
end else begin
if (elem_d==`SRTP_ELM) phase_d <= phase_d+1;
end
end
// for pexe_done
// ###########################################################################
always @(posedge CLK) begin
if (RSTa) begin
pexe_done_a <= 0;
end else begin
if (phase_a==`LAST_PHASE) pexe_done_a <= 1;
end
end
always @(posedge CLK) begin
if (RSTb) begin
pexe_done_b <= 0;
end else begin
if (phase_b==`LAST_PHASE) pexe_done_b <= 1;
end
end
always @(posedge CLK) begin
if (RSTc) begin
pexe_done_c <= 0;
end else begin
if (phase_c==`LAST_PHASE) pexe_done_c <= 1;
end
end
always @(posedge CLK) begin
if (RSTd) begin
pexe_done_d <= 0;
end else begin
if (phase_d==`LAST_PHASE) pexe_done_d <= 1;
end
end
// for pexe_done_p
// ###########################################################################
always @(posedge CLK) begin
if (RSTa) begin
pexe_done_a_p <= 0;
end else begin
if (phase_a==`LAST_PHASE-1) pexe_done_a_p <= 1;
end
end
always @(posedge CLK) begin
if (RSTb) begin
pexe_done_b_p <= 0;
end else begin
if (phase_b==`LAST_PHASE-1) pexe_done_b_p <= 1;
end
end
always @(posedge CLK) begin
if (RSTc) begin
pexe_done_c_p <= 0;
end else begin
if (phase_c==`LAST_PHASE-1) pexe_done_c_p <= 1;
end
end
always @(posedge CLK) begin
if (RSTd) begin
pexe_done_d_p <= 0;
end else begin
if (phase_d==`LAST_PHASE-1) pexe_done_d_p <= 1;
end
end
// for elem
// ########################################################################### // not deleted
always @(posedge CLK) begin
if (RSTa) begin
elem <= 0;
elem_a <= 0;
end else begin
case (last_phase)
1'b0: begin
case ({OB_deq0, (elem_a==`SRTP_ELM)})
2'b01: elem_a <= 0;
2'b10: elem_a <= elem_a + 16;
endcase
end
1'b1: begin
case ({OB_deq0, (elem==`SORT_ELM)})
2'b01: elem <= 0;
2'b10: elem <= elem + 16;
endcase
end
endcase
end
end
always @(posedge CLK) begin
if (RSTb) begin
elem_b <= 0;
end else begin
case ({OB_deq1, (elem_b==`SRTP_ELM)})
2'b01: elem_b <= 0;
2'b10: elem_b <= elem_b + 16;
endcase
end
end
always @(posedge CLK) begin
if (RSTc) begin
elem_c <= 0;
end else begin
case ({OB_deq2, (elem_c==`SRTP_ELM)})
2'b01: elem_c <= 0;
2'b10: elem_c <= elem_c + 16;
endcase
end
end
always @(posedge CLK) begin
if (RSTd) begin
elem_d <= 0;
end else begin
case ({OB_deq3, (elem_d==`SRTP_ELM)})
2'b01: elem_d <= 0;
2'b10: elem_d <= elem_d + 16;
endcase
end
end
// for iter_done
// ###########################################################################
always @(posedge CLK) iter_done_a <= (ecnt_a==2);
always @(posedge CLK) iter_done_b <= (ecnt_b==2);
always @(posedge CLK) iter_done_c <= (ecnt_c==2);
always @(posedge CLK) iter_done_d <= (ecnt_d==2);
// for pchange
// ###########################################################################
always @(posedge CLK) pchange_a <= (elem_a==`SRTP_ELM);
always @(posedge CLK) pchange_b <= (elem_b==`SRTP_ELM);
always @(posedge CLK) pchange_c <= (elem_c==`SRTP_ELM);
always @(posedge CLK) pchange_d <= (elem_d==`SRTP_ELM);
// for irst
// ###########################################################################
always @(posedge CLK) irst_a <= mux1(((ecnt_a==2) || pchange_a), (ecnt==2), last_phase);
always @(posedge CLK) irst_b <= (ecnt_b==2) || pchange_b;
always @(posedge CLK) irst_c <= (ecnt_c==2) || pchange_c;
always @(posedge CLK) irst_d <= (ecnt_d==2) || pchange_d;
// for frst
// ###########################################################################
always @(posedge CLK) frst_a <= mux1((RSTa || (ecnt_a==2) || (elem_a==`SRTP_ELM)), (ecnt==2), last_phase);
always @(posedge CLK) frst_b <= RSTb || (ecnt_b==2) || (elem_b==`SRTP_ELM);
always @(posedge CLK) frst_c <= RSTc || (ecnt_c==2) || (elem_c==`SRTP_ELM);
always @(posedge CLK) frst_d <= RSTd || (ecnt_d==2) || (elem_d==`SRTP_ELM);
// for ecnt
// ###########################################################################
always @(posedge CLK) begin
if (RSTa) begin
ecnt <= ((`ELEMS_PER_UNIT<<`WAY_LOG) << (phase * `WAY_LOG));
end else begin
if (ecnt!=0 && F01_deq0 && last_phase) ecnt <= ecnt - 1;
end
end
always @(posedge CLK) begin
if (RSTa || iter_done_a || pchange_a) begin
ecnt_a <= ((`ELEMS_PER_UNIT<<`WAY_LOG) << (phase_a * `WAY_LOG));
end else begin
if (ecnt_a!=0 && F01_deq0 && !pexe_done_a) ecnt_a <= ecnt_a - 1;
end
end
always @(posedge CLK) begin
if (RSTb || iter_done_b || pchange_b) begin
ecnt_b <= ((`ELEMS_PER_UNIT<<`WAY_LOG) << (phase_b * `WAY_LOG));
end else begin
if (ecnt_b!=0 && F01_deq1 && !pexe_done_b) ecnt_b <= ecnt_b - 1;
end
end
always @(posedge CLK) begin
if (RSTc || iter_done_c || pchange_c) begin
ecnt_c <= ((`ELEMS_PER_UNIT<<`WAY_LOG) << (phase_c * `WAY_LOG));
end else begin
if (ecnt_c!=0 && F01_deq2 && !pexe_done_c) ecnt_c <= ecnt_c - 1;
end
end
always @(posedge CLK) begin
if (RSTd || iter_done_d || pchange_d) begin
ecnt_d <= ((`ELEMS_PER_UNIT<<`WAY_LOG) << (phase_d * `WAY_LOG));
end else begin
if (ecnt_d!=0 && F01_deq3 && !pexe_done_d) ecnt_d <= ecnt_d - 1;
end
end
// for sortdone
// ###########################################################################
always @(posedge CLK) begin
if (RSTa) begin
sortdone <= 0;
end else begin
if (phase==(`LAST_PHASE+1)) sortdone <= 1;
end
end
endmodule |
module music_ROM(
input clk,
input [7:0] address,
output reg [7:0] note
);
always @(posedge clk)
case(address)
0, 1: note <= 8'd27; // C C
2: note <= 8'd29; // D
3: note <= 8'd27; // C
4: note <= 8'd32; // F
5: note <= 8'd31; // E
6: note <= 8'd0;
7, 8: note <= 8'd27; // C C
9: note <= 8'd29; // D
10: note <= 8'd27; // C
11: note <= 8'd34; // G
12: note <= 8'd32; // F
13: note <= 8'd0;
14, 15: note <= 8'd27; //C C
16: note <= 8'd39; // C + 12
17: note <= 8'd24; // A
18: note <= 8'd32; // F
19: note <= 8'd31; // E
20: note <= 8'd29; // D
21: note <= 8'd0;
22, 23: note <= 8'd39; // B B
24: note <= 8'd24; // A
25: note <= 8'd32; // F
26: note <= 8'd34; // G
27: note <= 8'd32; // F
default: note <= 8'd0;
endcase
endmodule |
module divide_by12(numer, quotient, remain);
input [5:0] numer;
output [2:0] quotient;
output [3:0] remain;
reg [2:0] quotient;
reg [3:0] remain_bit3_bit2;
assign remain = {remain_bit3_bit2, numer[1:0]}; // the first 2 bits are copied through
always @(numer[5:2]) // and just do a divide by "3" on the remaining bits
case(numer[5:2])
0: begin quotient=0; remain_bit3_bit2=0; end
1: begin quotient=0; remain_bit3_bit2=1; end
2: begin quotient=0; remain_bit3_bit2=2; end
3: begin quotient=1; remain_bit3_bit2=0; end
4: begin quotient=1; remain_bit3_bit2=1; end
5: begin quotient=1; remain_bit3_bit2=2; end
6: begin quotient=2; remain_bit3_bit2=0; end
7: begin quotient=2; remain_bit3_bit2=1; end
8: begin quotient=2; remain_bit3_bit2=2; end
9: begin quotient=3; remain_bit3_bit2=0; end
10: begin quotient=3; remain_bit3_bit2=1; end
11: begin quotient=3; remain_bit3_bit2=2; end
12: begin quotient=4; remain_bit3_bit2=0; end
13: begin quotient=4; remain_bit3_bit2=1; end
14: begin quotient=4; remain_bit3_bit2=2; end
15: begin quotient=5; remain_bit3_bit2=0; end
endcase
endmodule |
module musicbox(
//////////// CLOCK //////////
input CLOCK_50,
//////////// SPEAKER //////////
output SPEAKER
);
reg clk;
always @(posedge CLOCK_50) clk <= ~clk;
reg [`COUNTER_SIZE-1:0] tone;
always @(posedge clk) tone <= tone+1;
wire [7:0] fullnote;
music_ROM ROM(.clk(clk), .address(tone[27:23]), .note(fullnote));
wire [2:0] octave;
wire [3:0] note;
divide_by12 divby12(.numer(fullnote[5:0]), .quotient(octave), .remain(note));
reg [8:0] clk_50divider;
always @(note)
case(note)
0: clk_50divider = 512-1; // A
1: clk_50divider = 483-1; // A#/Bb
2: clk_50divider = 456-1; // B
3: clk_50divider = 431-1; // C
4: clk_50divider = 406-1; // C#/Db
5: clk_50divider = 384-1; // D
6: clk_50divider = 362-1; // D#/Eb
7: clk_50divider = 342-1; // E
8: clk_50divider = 323-1; // F
9: clk_50divider = 304-1; // F#/Gb
10: clk_50divider = 287-1; // G
11: clk_50divider = 271-1; // G#/Ab
default: clk_50divider = 0; // should never happen
endcase
reg [8:0] counter_note;
always @(posedge clk) if (counter_note == 0) counter_note <= clk_50divider; else counter_note <= counter_note - 1;
reg [7:0] counter_octave;
always @(posedge clk)
if (counter_note == 0)
begin
if (counter_octave == 0)
counter_octave <= (octave == 0 ? 255:octave == 1 ? 127:octave == 2 ? 63:octave == 3 ? 31:octave == 4 ? 15:7);
else
counter_octave <= counter_octave - 1;
end
reg speaker;
assign SPEAKER = speaker;
always @(posedge clk) if (fullnote != 0 && counter_note == 0 && counter_octave == 0) speaker <= ~speaker;
endmodule |
module top_nto1_pll_diff_rx_and_tx (
input reset, // reset (active high)
input [5:0] datain_p, datain_n, // lvds data inputs
input clkin_p, clkin_n, // lvds clock input
output [5:0] dataout_p, dataout_n, // lvds data outputs
output clkout_p, clkout_n) ; // lvds clock output
// Parameters for serdes factor and number of IO pins
parameter integer S = 7 ; // Set the serdes factor to 8
parameter integer D = 6 ; // Set the number of inputs and outputs
parameter integer DS = (D*S)-1 ; // Used for bus widths = serdes factor * number of inputs - 1
wire rst ;
wire [DS:0] rxd ; // Data from serdeses
reg [DS:0] txd ; // Data to serdeses
reg [DS:0] rxr ; // Registered Data from serdeses
reg state ;
reg bslip ;
reg [3:0] count ;
wire [6:0] clk_iserdes_data ;
parameter [S-1:0] TX_CLK_GEN = 7'b1100001 ; // Transmit a constant to make a clock
assign rst = reset ; // active high reset pin
assign dummy_out = rxr ;
// Clock Input. Generate ioclocks via BUFIO2
serdes_1_to_n_clk_pll_s8_diff #(
.S (S),
.CLKIN_PERIOD (6.700),
.PLLD (1),
.PLLX (S),
.BS ("TRUE")) // Parameter to enable bitslip TRUE or FALSE (has to be true for video applications)
inst_clkin (
.clkin_p (clkin_p),
.clkin_n (clkin_n),
.rxioclk (rx_bufpll_clk_xn),
.pattern1 (7'b1100001), // default values for 7:1 video applications
.pattern2 (7'b1100011),
.rx_serdesstrobe (rx_serdesstrobe),
.rx_bufg_pll_x1 (rx_bufg_x1),
.bitslip (bitslip),
.reset (rst),
.datain (clk_iserdes_data),
.rx_pll_lckd (), // PLL locked - only used if a 2nd BUFPLL is required
.rx_pllout_xs (), // Multiplied PLL clock - only used if a 2nd BUFPLL is required
.rx_bufpll_lckd (rx_bufpll_lckd)) ;
// Data Inputs
assign not_bufpll_lckd = ~rx_bufpll_lckd ;
serdes_1_to_n_data_s8_diff #(
.S (S),
.D (D))
inst_datain (
.use_phase_detector (1'b1), // '1' enables the phase detector logic
.datain_p (datain_p),
.datain_n (datain_n),
.rxioclk (rx_bufpll_clk_xn),
.rxserdesstrobe (rx_serdesstrobe),
.gclk (rx_bufg_x1),
.bitslip (bitslip),
.reset (not_bufpll_lckd),
.data_out (rxd),
.debug_in (2'b00),
.debug ());
always @ (posedge rx_bufg_x1) // process received data
begin
txd <= rxd ;
end
// Transmitter Logic - Instantiate serialiser to generate forwarded clock
serdes_n_to_1_s8_diff #(
.S (S),
.D (1))
inst_clkout (
.dataout_p (clkout_p),
.dataout_n (clkout_n),
.txioclk (rx_bufpll_clk_xn),
.txserdesstrobe (rx_serdesstrobe),
.gclk (rx_bufg_x1),
.reset (rst),
.datain (TX_CLK_GEN)); // Transmit a constant to make the clock
// Instantiate Outputs and output serialisers for output data lines
serdes_n_to_1_s8_diff #(
.S (S),
.D (D))
inst_dataout (
.dataout_p (dataout_p),
.dataout_n (dataout_n),
.txioclk (rx_bufpll_clk_xn),
.txserdesstrobe (rx_serdesstrobe),
.gclk (rx_bufg_x1),
.reset (rst),
.datain (txd));
endmodule |
module bw_io_misc_chunk5(clk ,sel_bypass ,spare_misc_pad ,
spare_misc_paddata ,obsel ,io_tdo_en ,ckd ,vref ,vddo ,io_tdo ,
rst_val_up ,io_tdi ,mode_ctl ,rst_val_dn ,io_trst_l ,bsi ,io_tck ,
clock_dr ,tck ,shift_dr ,trst_l ,hiz_l ,tdi ,update_dr ,rst_io_l ,
por_l ,tdo ,se ,si ,reset_l ,so ,bso ,spare_misc_padoe ,
spare_misc_pad_to_core );
output [2:1] spare_misc_pad_to_core ;
input [2:1] spare_misc_paddata ;
input [5:4] obsel ;
input [2:1] spare_misc_padoe ;
inout [2:1] spare_misc_pad ;
output io_tdi ;
output io_trst_l ;
output io_tck ;
output so ;
output bso ;
input clk ;
input sel_bypass ;
input io_tdo_en ;
input ckd ;
input vref ;
input vddo ;
input io_tdo ;
input rst_val_up ;
input mode_ctl ;
input rst_val_dn ;
input bsi ;
input clock_dr ;
input shift_dr ;
input hiz_l ;
input update_dr ;
input rst_io_l ;
input por_l ;
input se ;
input si ;
input reset_l ;
inout tck ;
inout trst_l ;
inout tdi ;
inout tdo ;
supply0 vss ;
wire bscan_spare1_spare2 ;
wire net133 ;
wire bscan_spare2_spare1 ;
wire net084 ;
bw_io_cmos2_pad tdo_pad (
.oe (io_tdo_en ),
.vddo (vddo ),
.data (io_tdo ),
.to_core (net133 ),
.pad (tdo ),
.por_l (por_l ) );
bw_u1_ckbuf_40x Iclkbuf_5 (
.clk (net084 ),
.rclk (clk ) );
bw_io_hstl_pad spare_misc_pad_2_pad (
.obsel ({obsel } ),
.so (so ),
.clock_dr (clock_dr ),
.vref (vref ),
.update_dr (update_dr ),
.clk (net084 ),
.reset_l (reset_l ),
.hiz_l (hiz_l ),
.shift_dr (shift_dr ),
.rst_io_l (rst_io_l ),
.rst_val_up (rst_val_up ),
.bso (bscan_spare2_spare1 ),
.bsr_si (bsi ),
.rst_val_dn (rst_val_dn ),
.mode_ctl (mode_ctl ),
.si (bscan_spare1_spare2 ),
.oe (spare_misc_padoe[2] ),
.data (spare_misc_paddata[2] ),
.se (se ),
.to_core (spare_misc_pad_to_core[2] ),
.por_l (por_l ),
.pad (spare_misc_pad[2] ),
.vddo (vddo ),
.sel_bypass (sel_bypass ),
.ckd (ckd ) );
bw_io_hstl_pad spare_misc_pad_1_pad (
.obsel ({obsel } ),
.so (bscan_spare1_spare2 ),
.clock_dr (clock_dr ),
.vref (vref ),
.update_dr (update_dr ),
.clk (net084 ),
.reset_l (reset_l ),
.hiz_l (hiz_l ),
.shift_dr (shift_dr ),
.rst_io_l (rst_io_l ),
.rst_val_up (rst_val_up ),
.bso (bso ),
.bsr_si (bscan_spare2_spare1 ),
.rst_val_dn (rst_val_dn ),
.mode_ctl (mode_ctl ),
.si (si ),
.oe (spare_misc_padoe[1] ),
.data (spare_misc_paddata[1] ),
.se (se ),
.to_core (spare_misc_pad_to_core[1] ),
.por_l (por_l ),
.pad (spare_misc_pad[1] ),
.vddo (vddo ),
.sel_bypass (sel_bypass ),
.ckd (ckd ) );
bw_io_cmos2_pad_dn tck_pad (
.oe (vss ),
.vddo (vddo ),
.data (vss ),
.to_core (io_tck ),
.pad (tck ),
.por_l (por_l ) );
bw_io_cmos2_pad_up tdi_pad (
.oe (vss ),
.vddo (vddo ),
.data (vss ),
.to_core (io_tdi ),
.pad (tdi ),
.por_l (por_l ) );
bw_io_cmos2_pad_up trst_l_pad (
.oe (vss ),
.vddo (vddo ),
.data (vss ),
.to_core (io_trst_l ),
.pad (trst_l ),
.por_l (por_l ) );
endmodule |
module fifo(clock, reset, read, write, fifo_in, digitron_out, fifo_empty, fifo_full);
parameter DEPTH = 128; // 128 深
parameter DEPTH_BINARY = 7; // 深度的二进制位数
parameter WIDTH = 4; // 4bit宽
parameter MAX_CONT = 7'b1111111; // 计数器最大值127 [0~127]
// LED 灯的二进制表示
// 根据 《数字系统设计与Verilog DHL (6th Edition)》P153 所提供的7段数码管电路图
/*
—— a
| | f b
—— g
| | e c
—— d
*/
// Len_N = abcdefg
// 使用一个七段数码管基于16进制显示 4bit 数据
parameter
digitron_0 = 7'b1111110,
digitron_1 = 7'b0110000,
digitron_2 = 7'b1101101,
digitron_3 = 7'b0000110,
digitron_4 = 7'b0110011,
digitron_5 = 7'b1011011,
digitron_6 = 7'b1011111,
digitron_7 = 7'b1110000,
digitron_8 = 7'b1111111,
digitron_9 = 7'b1111011,
digitron_a = 7'b1100111,
digitron_b = 7'b0011111,
digitron_c = 7'b1001110,
digitron_d = 7'b0111101,
digitron_e = 7'b0110000,
digitron_f = 7'b1001111;
input clock,reset,read,write; // 时钟，重置，读开关，写开关
input [WIDTH-1:0]fifo_in; // FIFO 数据输入
output [6:0] digitron_out; // 数码管 FIFO 数据输出
output fifo_empty,fifo_full; // 空标志,满标志
reg div; // 驱动信号
reg [23:0] clock_count; // 时钟计数器
reg [6:0] digitron_out; // 数据输出寄存器
reg [WIDTH-1:0]fifo_out; // 数据输出寄存器
reg [WIDTH-1:0]ram[DEPTH-1:0]; // 128深度 8宽度的 RAM 寄存器
reg [DEPTH_BINARY-1:0]read_ptr,write_ptr,counter; // 读指针，写指针，计数器 长度为2^7
wire fifo_empty,fifo_full; // 空标志,满标志
initial
begin
counter = 0;
read_ptr = 0;
write_ptr = 0;
fifo_out = 0;
div = 0;
clock_count = 0;
digitron_out = digitron_0;
end
always@(posedge clock)
begin
if(clock_count == 24'b111111111111111111111111)
begin
div =~ div;
clock_count <= 0;
end
else
begin
clock_count <= clock_count+1;
end
end
assign fifo_empty = (counter == 0); //标志位赋值
assign fifo_full = (counter == DEPTH-1);
always@(posedge div) // 时钟同步驱动
if(reset) // Reset 重置FIFO
begin
read_ptr = 0;
write_ptr = 0;
counter = 0;
fifo_out = 0;
end
else
case({read,write}) // 相应读写开关
2'b00:; //没有读写指令
2'b01: //写指令，数据输入FIFO
begin
if (counter < DEPTH - 1) // 判断是否可写
begin
ram[write_ptr] = fifo_in;
counter = counter + 1;
write_ptr = (write_ptr == DEPTH-1)?0:write_ptr + 1;
end
end
2'b10: //读指令，数据读出FIFO
begin
if (counter > 0) // 判断是否可读
begin
fifo_out = ram[read_ptr];
case(fifo_out)
4'b0000 : digitron_out <= digitron_0;
4'b0001 : digitron_out <= digitron_1;
4'b0010 : digitron_out <= digitron_2;
4'b0011 : digitron_out <= digitron_3;
4'b0100 : digitron_out <= digitron_4;
4'b0101 : digitron_out <= digitron_5;
4'b0110 : digitron_out <= digitron_6;
4'b0111 : digitron_out <= digitron_7;
4'b1000 : digitron_out <= digitron_8;
4'b1001 : digitron_out <= digitron_9;
4'b1010 : digitron_out <= digitron_a;
4'b1011 : digitron_out <= digitron_b;
4'b1100 : digitron_out <= digitron_c;
4'b1101 : digitron_out <= digitron_d;
4'b1110 : digitron_out <= digitron_e;
4'b1111 : digitron_out <= digitron_f;
endcase
counter = counter - 1;
read_ptr = (read_ptr == DEPTH-1)?0:read_ptr + 1;
end
end
2'b11: //读写指令同时，数据可以直接输出
begin
if(counter == 0)
begin
fifo_out = fifo_in; // 直接输出
case(fifo_out) // todo : 去除case的冗余代码 2017.6.13
4'b0000 : digitron_out <= digitron_0;
4'b0001 : digitron_out <= digitron_1;
4'b0010 : digitron_out <= digitron_2;
4'b0011 : digitron_out <= digitron_3;
4'b0100 : digitron_out <= digitron_4;
4'b0101 : digitron_out <= digitron_5;
4'b0110 : digitron_out <= digitron_6;
4'b0111 : digitron_out <= digitron_7;
4'b1000 : digitron_out <= digitron_8;
4'b1001 : digitron_out <= digitron_9;
4'b1010 : digitron_out <= digitron_a;
4'b1011 : digitron_out <= digitron_b;
4'b1100 : digitron_out <= digitron_c;
4'b1101 : digitron_out <= digitron_d;
4'b1110 : digitron_out <= digitron_e;
4'b1111 : digitron_out <= digitron_f;
endcase
end
else
begin
ram[write_ptr]=fifo_in;
fifo_out=ram[read_ptr];
case(fifo_out) // todo : 去除case的冗余代码 2017.6.13
4'b0000 : digitron_out <= digitron_0;
4'b0001 : digitron_out <= digitron_1;
4'b0010 : digitron_out <= digitron_2;
4'b0011 : digitron_out <= digitron_3;
4'b0100 : digitron_out <= digitron_4;
4'b0101 : digitron_out <= digitron_5;
4'b0110 : digitron_out <= digitron_6;
4'b0111 : digitron_out <= digitron_7;
4'b1000 : digitron_out <= digitron_8;
4'b1001 : digitron_out <= digitron_9;
4'b1010 : digitron_out <= digitron_a;
4'b1011 : digitron_out <= digitron_b;
4'b1100 : digitron_out <= digitron_c;
4'b1101 : digitron_out <= digitron_d;
4'b1110 : digitron_out <= digitron_e;
4'b1111 : digitron_out <= digitron_f;
endcase
write_ptr=(write_ptr==DEPTH-1)?0:write_ptr+1;
read_ptr=(read_ptr==DEPTH-1)?0:write_ptr+1;
end
end
endcase
endmodule |
module debouncing(
// BJ_CLK, //采集时钟
// RESET, //系统复位信号 [低电平有效]
// BUTTON_IN, //按键输入信号
// BUTTON_OUT //消抖后的输出信号
// );
// input BJ_CLK;
// input RESET;
// input BUTTON_IN;
// output BUTTON_OUT;
// reg BUTTON_IN_Q, BUTTON_IN_2Q, BUTTON_IN_3Q;
// always @(posedge BJ_CLK or negedge RESET)
// begin
// if(~RESET)
// begin
// BUTTON_IN_Q <= 1'b1;
// BUTTON_IN_2Q <= 1'b1;
// BUTTON_IN_3Q <= 1'b1;
// end
// else
// begin
// BUTTON_IN_Q <= BUTTON_IN;
// BUTTON_IN_2Q <= BUTTON_IN_Q;
// BUTTON_IN_3Q <= BUTTON_IN_2Q;
// end
// end
// wire BUTTON_OUT = BUTTON_IN_2Q | BUTTON_IN_3Q;
// endmodule |
module sky130_fd_sc_hd__a221o (
//# {{data|Data Signals}}
input A1 ,
input A2 ,
input B1 ,
input B2 ,
input C1 ,
output X ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule |
module updateCRC16 (rstCRC, CRCResult, CRCEn, dataIn, ready, clk, rst);
input rstCRC;
input CRCEn;
input [7:0] dataIn;
input clk;
input rst;
output [15:0] CRCResult;
output ready;
wire rstCRC;
wire CRCEn;
wire [7:0] dataIn;
wire clk;
wire rst;
reg [15:0] CRCResult;
reg ready;
reg doUpdateCRC;
reg [7:0] data;
reg [3:0] i;
always @(posedge clk)
begin
if (rst == 1'b1 || rstCRC == 1'b1) begin
doUpdateCRC <= 1'b0;
i <= 4'h0;
CRCResult <= 16'hffff;
ready <= 1'b1;
end
else
begin
if (doUpdateCRC == 1'b0)
begin
if (CRCEn == 1'b1) begin
doUpdateCRC <= 1'b1;
data <= dataIn;
ready <= 1'b0;
end
end
else begin
i <= i + 1'b1;
if ( (CRCResult[0] ^ data[0]) == 1'b1) begin
CRCResult <= {1'b0, CRCResult[15:1]} ^ 16'ha001;
end
else begin
CRCResult <= {1'b0, CRCResult[15:1]};
end
data <= {1'b0, data[7:1]};
if (i == 4'h7)
begin
doUpdateCRC <= 1'b0;
i <= 4'h0;
ready <= 1'b1;
end
end
end
end
endmodule |
module handling read requests
rptr_empty
#(ASIZE)
rptr_empty (
.arempty (arempty),
.rempty (rempty),
.raddr (raddr),
.rptr (rptr),
.rq2_wptr (rq2_wptr),
.rinc (rinc),
.rclk (rclk),
.rrst_n (rrst_n)
);
endmodule |
module sky130_fd_sc_hs__nor4b_4 (
Y ,
A ,
B ,
C ,
D_N ,
VPWR,
VGND
);
output Y ;
input A ;
input B ;
input C ;
input D_N ;
input VPWR;
input VGND;
sky130_fd_sc_hs__nor4b base (
.Y(Y),
.A(A),
.B(B),
.C(C),
.D_N(D_N),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule |
module sky130_fd_sc_hs__nor4b_4 (
Y ,
A ,
B ,
C ,
D_N
);
output Y ;
input A ;
input B ;
input C ;
input D_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__nor4b base (
.Y(Y),
.A(A),
.B(B),
.C(C),
.D_N(D_N)
);
endmodule |
module pippo_id(
clk, rst,
id_inst, id_cia, id_snia, id_valid,
ex_inst, ex_cia, ex_snia, ex_valid,
gpr_addr_rda, gpr_addr_rdb, gpr_addr_rdc, gpr_rda_en, gpr_rdb_en, gpr_rdc_en,
ex_imm, ex_sel_a, ex_sel_b,
ex_branch_addrofs, reg_zero, ex_spr_addr,
set_atomic, clear_atomic,
ex_bpu_uops, ex_alu_uops, ex_cr_uops, ex_lsu_uops, ex_reg_uops,
ex_rfwb_uops, ex_gpr_addr_wra, ex_gpr_addr_wrb,
multicycle_cnt, id_freeze, ex_freeze, wb_freeze, flushpipe,
sig_syscall, sig_rfi, sig_rfci, sig_eieio, sig_isync, sig_sync, sig_illegal, sig_emulate,
id_sig_ibuserr, sig_ibuserr
);
input clk;
input rst;
// pipeling registers
input id_valid;
input [31:0] id_inst;
input [29:0] id_cia;
input [29:0] id_snia;
output ex_valid;
output [31:0] ex_inst;
output [29:0] ex_cia;
output [29:0] ex_snia;
// operand signals: gpr read port - assert at current stage
output [`GPR_ADDR_WIDTH-1:0] gpr_addr_rda;
output [`GPR_ADDR_WIDTH-1:0] gpr_addr_rdb;
output [`GPR_ADDR_WIDTH-1:0] gpr_addr_rdc;
output gpr_rda_en;
output gpr_rdb_en;
output gpr_rdc_en;
// operand signals: imm and operandmux control - need pipeling, assert at following stage
output [31:0] ex_imm;
output [`OPSEL_WIDTH-1:0] ex_sel_a;
output [`OPSEL_WIDTH-1:0] ex_sel_b;
// operand signals: address displacement or address - need pipeling, assert at following stage
output [29:0] ex_branch_addrofs;
output reg_zero;
output [`SPR_ADDR_WIDTH-1:0] ex_spr_addr;
// uops signals, need pipeling, assert at following stages
output [`BPUUOPS_WIDTH-1:0] ex_bpu_uops;
output [`ALUUOPS_WIDTH-1:0] ex_alu_uops;
output [`LSUUOPS_WIDTH-1:0] ex_lsu_uops;
output [`CRUOPS_WIDTH-1:0] ex_cr_uops;
output [`REGUOPS_WIDTH-1:0] ex_reg_uops;
// wb signals, need pipeling
// note: write-back enable signals are encoded in rfwb_uops
output [`RFWBUOPS_WIDTH-1:0] ex_rfwb_uops;
output [`GPR_ADDR_WIDTH-1:0] ex_gpr_addr_wra;
output [`GPR_ADDR_WIDTH-1:0] ex_gpr_addr_wrb;
// pipeling control signals
input id_freeze;
input ex_freeze;
input wb_freeze;
input flushpipe;
// atomic memory access for lsu
output set_atomic;
output clear_atomic;
// multicycle instruction counter, assert at following stages
output [`MULTICYCLE_WIDTH-1:0] multicycle_cnt;
// exception request signals
output sig_rfi;
output sig_rfci;
output sig_syscall;
output sig_illegal;
output sig_emulate;
// exception requests pipeling from IF stage
input id_sig_ibuserr;
output sig_ibuserr;
// synchronization signals
output sig_eieio;
output sig_isync;
output sig_sync;
//
// Whole decoder
//
reg [`BPUUOPS_WIDTH-1:0] id_bpu_uops;
reg [`ALUUOPS_WIDTH-1:0] id_alu_uops;
reg [`LSUUOPS_WIDTH-1:0] id_lsu_uops;
reg [`CRUOPS_WIDTH-1:0] id_cr_uops;
reg [`REGUOPS_WIDTH-1:0] id_reg_uops;
reg [`GPR_ADDR_WIDTH-1:0] gpr_addr_rda;
reg [`GPR_ADDR_WIDTH-1:0] gpr_addr_rdb;
reg [`GPR_ADDR_WIDTH-1:0] gpr_addr_rdc;
reg gpr_rda_en;
reg gpr_rdb_en;
reg gpr_rdc_en;
reg [`RFWBUOPS_WIDTH-1:0] id_rfwb_uops;
reg [`GPR_ADDR_WIDTH-1:0] id_gpr_addr_wra;
reg [`GPR_ADDR_WIDTH-1:0] id_gpr_addr_wrb;
reg [29:0] id_branch_addrofs;
reg id_reg_zero;
reg reg_zero;
reg [9:0] id_spr_addr;
reg [31:0] id_imm;
reg sel_imm;
reg id_set_atomic;
reg set_atomic;
reg id_clear_atomic;
reg clear_atomic;
reg [`MULTICYCLE_WIDTH-1:0] multicycle;
reg id_sig_illegal;
reg id_sig_emulate;
reg id_sig_syscall;
reg id_sig_eieio;
reg id_sig_isync;
reg id_sig_sync;
reg id_sig_rfi;
reg id_sig_rfci;
always @(id_inst or id_cia or id_snia or id_valid) begin
// EX/WB uops
id_bpu_uops = {2'b00, `BPUOP_NOP}; // {AA, LK, `BPUOP_NOP}
id_alu_uops = {2'b00, `ALUOP_NOP}; // {OE, Rc, `ALUOP_NOP}
id_lsu_uops = {1'b0, `LSUOP_NOP}; // {update, `LSUOP_NOP}
id_reg_uops = `REGOP_NOP;
id_cr_uops = `CROP_NOP;
// gprs access
gpr_addr_rda = id_inst[20:16];
gpr_addr_rdb = id_inst[15:11];
gpr_addr_rdc = id_inst[25:21];
gpr_rda_en = 1'b0;
gpr_rdb_en = 1'b0;
gpr_rdc_en = 1'b0;
// wb
id_rfwb_uops = `RFWBOP_NOP;
id_gpr_addr_wra = id_inst[25:21];
id_gpr_addr_wrb = id_inst[20:16]; // b bus for load/store with update inst.'s EA write-back
// imm
sel_imm = 1'b0;
id_imm = 32'd0;
// address operands
id_branch_addrofs = 30'd0;
id_spr_addr = 10'd0;
id_reg_zero = 1'b0;
// atomic memory access
id_set_atomic = 1'b0;
id_clear_atomic = 1'b0;
// multicycle instruction indicator: to extend pipeline stages - for memory access and complex insts
multicycle = `EXTEND_ZERO_CYCLES;
// exception request
id_sig_illegal = 1'b1;
id_sig_emulate = 1'b0;
id_sig_syscall = 1'b0;
id_sig_rfi = 1'b0;
id_sig_rfci = 1'b0;
// synchronization request
id_sig_eieio = 1'b0;
id_sig_isync = 1'b0;
id_sig_sync = 1'b0;
case (id_inst[31:26]) // synopsys parallel_case
//
// I-Form
//
// inst: b[l][a],
// execution: bpu
// flowchart:
// b: (cia+imm) -> PC
// ba: imm -> PC
// bl: (cia+imm) -> PC; (cia+4) -> LR
// bla: imm -> PC; (cia+4) -> LR
`Bx_OPCD: begin
id_bpu_uops = {id_inst[1:0], `BPUOP_BIMM}; // {AA,LK, `BPUOP_BIMM}
id_branch_addrofs = {{6{id_inst[25]}}, id_inst[25:2]};
id_sig_illegal = 1'b0;
end
//
// B-Form
//
// inst: bc[l][a]
// execution: bpu
// flowchart:
// (CTR, BO, BI) -> (c)
// bc: (cia+imm) ->(c) PC
// bca: imm -> (c)PC
// bcl: (cia+imm) -> (c)PC; (cia+4) -> LR
// bcla: imm -> (c)PC; (cia+4) -> LR
`BCx_OPCD: begin
id_bpu_uops = {id_inst[1:0], `BPUOP_BCIMM}; // {AA,LK, `BPUOP_BCIMM}
id_branch_addrofs = {{16{id_inst[15]}}, id_inst[15:2]};
id_sig_illegal = 1'b0;
end
//
// SC-Form
//
// inst: sc
// execution: except
// wb: (MSR) -> (SRR1);
// (PC)->(SRR0);
// EVPR[0:15]||0x0C00 -> PC;
// 0 -> (MSR[WE, EE, PR, DR, IR])
//
`SC_OPCD: begin
id_sig_syscall = 1;
id_sig_illegal = 1'b0;
`ifdef pippo_VERBOSE
// synopsys translate_off
$display("Generating sig_syscall");
// synopsys translate_on
`endif
end
//
// D-Form
// All D-Form inst. have unique OPCD
//
// addi
`ADDI_OPCD: begin
id_alu_uops = {2'b00, `ALUOP_ADD};
id_reg_zero = (id_inst[20:16] == 5'b00000);
gpr_addr_rda = id_inst[20:16];
gpr_rda_en = 1'b1;
id_imm = {{16{id_inst[15]}}, id_inst[15:0]};
sel_imm = 1'b1;
id_rfwb_uops = `RFWBOP_ALU;
id_gpr_addr_wra = id_inst[25:21];
id_sig_illegal = 1'b0;
end
// addic
`ADDIC_OPCD: begin
id_alu_uops = {2'b00, `ALUOP_ADDC};
gpr_addr_rda = id_inst[20:16];
gpr_rda_en = 1'b1;
id_imm = {{16{id_inst[15]}}, id_inst[15:0]};
sel_imm = 1'b1;
id_rfwb_uops = `RFWBOP_ALU;
id_gpr_addr_wra = id_inst[25:21];
id_sig_illegal = 1'b0;
end
// addic.
`ADDICx_OPCD: begin
id_alu_uops = {2'b01, `ALUOP_ADDC}; // record CR
gpr_addr_rda = id_inst[20:16];
gpr_rda_en = 1'b1;
id_imm = {{16{id_inst[15]}}, id_inst[15:0]};
sel_imm = 1'b1;
id_rfwb_uops = `RFWBOP_ALU;
id_gpr_addr_wra = id_inst[25:21];
id_sig_illegal = 1'b0;
end
// addis
`ADDIS_OPCD: begin
id_alu_uops = {2'b01, `ALUOP_ADDC}; // record CR
id_reg_zero = (id_inst[20:16] == 5'b00000);
gpr_addr_rda = id_inst[20:16];
gpr_rda_en = 1'b1;
id_imm = {id_inst[15:0], {16{1'b0}}};
sel_imm = 1'b1;
id_rfwb_uops = `RFWBOP_ALU;
id_gpr_addr_wra = id_inst[25:21];
id_sig_illegal = 1'b0;
end
`ANDIx_OPCD: begin
id_alu_uops = {2'b01, `ALUOP_AND}; // record CR
gpr_addr_rda = id_inst[25:21];
gpr_rda_en = 1'b1;
id_imm = {{16{1'b0}}, id_inst[15:0]};
sel_imm = 1'b1;
id_rfwb_uops = `RFWBOP_ALU;
id_gpr_addr_wra = id_inst[20:16];
id_sig_illegal = 1'b0;
end
`ANDISx_OPCD: begin
id_alu_uops = {2'b01, `ALUOP_AND}; // record CR
gpr_addr_rda = id_inst[25:21];
gpr_rda_en = 1'b1;
id_imm = {id_inst[15:0], {16{1'b0}}};
sel_imm = 1'b1;
id_rfwb_uops = `RFWBOP_ALU;
id_gpr_addr_wra = id_inst[20:16];
id_sig_illegal = 1'b0;
end
`ORI_OPCD: begin
id_alu_uops = {2'b00, `ALUOP_OR};
gpr_addr_rda = id_inst[25:21];
gpr_rda_en = 1'b1;
id_imm = {{16{1'b0}}, id_inst[15:0]};
sel_imm = 1'b1;
id_rfwb_uops = `RFWBOP_ALU;
id_gpr_addr_wra = id_inst[20:16];
id_sig_illegal = 1'b0;
end
`ORIS_OPCD: begin
id_alu_uops = {2'b00, `ALUOP_OR};
gpr_addr_rda = id_inst[25:21];
gpr_rda_en = 1'b1;
id_imm = {id_inst[15:0], {16{1'b0}}};
sel_imm = 1'b1;
id_rfwb_uops = `RFWBOP_ALU;
id_gpr_addr_wra = id_inst[20:16];
id_sig_illegal = 1'b0;
end
`XORI_OPCD: begin
id_alu_uops = {2'b00, `ALUOP_XOR};
gpr_addr_rda = id_inst[25:21];
gpr_rda_en = 1'b1;
id_imm = {{16{1'b0}}, id_inst[15:0]};
sel_imm = 1'b1;
id_rfwb_uops = `RFWBOP_ALU;
id_gpr_addr_wra = id_inst[20:16];
id_sig_illegal = 1'b0;
end
`XORIS_OPCD: begin
id_alu_uops = {2'b00, `ALUOP_XOR};
gpr_addr_rda = id_inst[25:21];
gpr_rda_en = 1'b1;
id_imm = {id_inst[15:0], {16{1'b0}}};
sel_imm = 1'b1;
id_rfwb_uops = `RFWBOP_ALU;
id_gpr_addr_wra = id_inst[20:16];
id_sig_illegal = 1'b0;
end
// inst: cmpi
// execution: alu
// flowchart:
// (RA) cmp EXTS(IM) -> CR[CRbf]
`CMPI_OPCD: begin
id_cr_uops = `CROP_CMP;
gpr_addr_rda = id_inst[20:16];
gpr_rda_en = 1'b1;
id_imm = {{16{id_inst[15]}}, id_inst[15:0]};
sel_imm = 1'b1;
id_sig_illegal = 1'b0;
end
// inst: cmpli
// execution: alu
// flowchart:
// (RA) cmpl EXTS(IM) -> CR[CRbf]
`CMPLI_OPCD: begin
id_cr_uops = `CROP_CMPL;
gpr_addr_rda = id_inst[20:16];
gpr_rda_en = 1'b1;
id_imm = {{16{id_inst[15]}}, id_inst[15:0]};
sel_imm = 1'b1;
id_sig_illegal = 1'b0;
end
// inst.: lbz
// execution: lsu
// flowchart:
// 1, (RA|0) + EXTS(D) -> EA;
// 2, {24{0}, mem(EA, 1 Byte)} -> (RT)
`LBZ_OPCD: begin
id_lsu_uops = {1'b0, `LSUOP_LBZ};
id_reg_zero = (id_inst[20:16] == 5'b00000);
gpr_addr_rda = id_inst[20:16];
gpr_rda_en = 1'b1;
id_imm = {{16{id_inst[15]}}, id_inst[15:0]};
sel_imm = 1'b1;
id_rfwb_uops = `RFWBOP_LSU;
id_gpr_addr_wra = id_inst[25:21];
id_sig_illegal = 1'b0;
end
// inst.: lha
// execution: lsu
// flowchart:
// 1, (RA|0) + EXTS(D) -> EA;
// 2, EXTS(mem(EA, 2 Byte)) -> (RT)
`LHA_OPCD: begin
id_lsu_uops = {1'b0, `LSUOP_LHA};
id_reg_zero = (id_inst[20:16] == 5'b00000);
gpr_addr_rda = id_inst[20:16];
gpr_rda_en = 1'b1;
id_imm = {{16{id_inst[15]}}, id_inst[15:0]};
sel_imm = 1'b1;
id_rfwb_uops = `RFWBOP_LSU;
id_gpr_addr_wra = id_inst[25:21];
id_sig_illegal = 1'b0;
end
// inst.: lhz
// execution: lsu
// flowchart:
// 1, (RA|0) + EXTS(D) -> EA;
// 2, {16{0}, mem(EA, 2 Byte)} -> (RT)
`LHZ_OPCD: begin
id_lsu_uops = {1'b0, `LSUOP_LHZ};
id_reg_zero = (id_inst[20:16] == 5'b00000);
gpr_addr_rda = id_inst[20:16];
gpr_rda_en = 1'b1;
id_imm = {{16{id_inst[15]}}, id_inst[15:0]};
sel_imm = 1'b1;
id_rfwb_uops = `RFWBOP_LSU;
id_gpr_addr_wra = id_inst[25:21];
id_sig_illegal = 1'b0;
end
// inst.: lwz
// execution: lsu
// flowchart:
// 1, (RA|0) + EXTS(D) -> EA;
// 2, mem(EA, 4 Byte) -> (RT)
`LWZ_OPCD: begin
id_lsu_uops = {1'b0, `LSUOP_LWZ};
id_reg_zero = (id_inst[20:16] == 5'b00000);
gpr_addr_rda = id_inst[20:16];
gpr_rda_en = 1'b1;
id_imm = {{16{id_inst[15]}}, id_inst[15:0]};
sel_imm = 1'b1;
id_rfwb_uops = `RFWBOP_LSU;
id_gpr_addr_wra = id_inst[25:21];
id_sig_illegal = 1'b0;
end
// inst.: stb
// execution: lsu
// flowchart:
// 1, (RA|0) + EXTS(D) -> EA;
// 2, RS[7:0] -> mem(EA, 1 Byte)
`STB_OPCD: begin
id_lsu_uops = {1'b0, `LSUOP_STB};
id_reg_zero = (id_inst[20:16] == 5'b00000);
gpr_addr_rda = id_inst[20:16];
gpr_rda_en = 1'b1;
id_imm = {{16{id_inst[15]}}, id_inst[15:0]};
sel_imm = 1'b1;
gpr_addr_rdc = id_inst[25:21];
gpr_rdc_en = 1'b1;
id_sig_illegal = 1'b0;
end
// inst.: sth
// execution: lsu
// flowchart:
// 1, (RA|0) + EXTS(D) -> EA;
// 2, RS[15:0] -> mem(EA, 2 Byte)
`STH_OPCD: begin
id_lsu_uops = {1'b0, `LSUOP_STH};
id_reg_zero = (id_inst[20:16] == 5'b00000);
gpr_addr_rda = id_inst[20:16];
gpr_rda_en = 1'b1;
id_imm = {{16{id_inst[15]}}, id_inst[15:0]};
sel_imm = 1'b1;
gpr_addr_rdc = id_inst[25:21];
gpr_rdc_en = 1'b1;
id_sig_illegal = 1'b0;
end
// inst.: stw
// execution: lsu
// flowchart:
// 1, (RA|0) + EXTS(D) -> EA;
// 2, RS[31:0] -> mem(EA, 4 Byte)
`STW_OPCD: begin
id_lsu_uops = {1'b0, `LSUOP_STW};
id_reg_zero = (id_inst[20:16] == 5'b00000);
gpr_addr_rda = id_inst[20:16];
gpr_rda_en = 1'b1;
id_imm = {{16{id_inst[15]}}, id_inst[15:0]};
sel_imm = 1'b1;
gpr_addr_rdc = id_inst[25:21];
gpr_rdc_en = 1'b1;
id_sig_illegal = 1'b0;
end
// lbzu
`LBZU_OPCD: begin
id_lsu_uops = {1'b1, `LSUOP_LBZ};
id_reg_zero = (id_inst[20:16] == 5'b00000); // [TBD] invalid form, how to deal at hardware side
gpr_addr_rda = id_inst[20:16];
gpr_rda_en = 1'b1;
id_imm = {{16{id_inst[15]}}, id_inst[15:0]};
sel_imm = 1'b1;
id_rfwb_uops = `RFWBOP_LSUTWO;
id_gpr_addr_wra = id_inst[25:21];
id_gpr_addr_wrb = id_inst[20:16];
id_sig_illegal = 1'b0;
end
// lhau
`LHAU_OPCD: begin
id_lsu_uops = {1'b1, `LSUOP_LHA};
id_reg_zero = (id_inst[20:16] == 5'b00000);
gpr_addr_rda = id_inst[20:16];
gpr_rda_en = 1'b1;
id_imm = {{16{id_inst[15]}}, id_inst[15:0]};
sel_imm = 1'b1;
id_rfwb_uops = `RFWBOP_LSUTWO;
id_gpr_addr_wra = id_inst[25:21];
id_gpr_addr_wrb = id_inst[20:16];
id_sig_illegal = 1'b0;
end
// lhzu
`LHZU_OPCD: begin
id_lsu_uops = {1'b1, `LSUOP_LHZ};
id_reg_zero = (id_inst[20:16] == 5'b00000);
gpr_addr_rda = id_inst[20:16];
gpr_rda_en = 1'b1;
id_imm = {{16{id_inst[15]}}, id_inst[15:0]};
sel_imm = 1'b1;
id_rfwb_uops = `RFWBOP_LSUTWO;
id_gpr_addr_wra = id_inst[25:21];
id_gpr_addr_wrb = id_inst[20:16];
id_sig_illegal = 1'b0;
end
// lwzu
`LWZU_OPCD: begin
id_lsu_uops = {1'b1, `LSUOP_LWZ};
id_reg_zero = (id_inst[20:16] == 5'b00000);
gpr_addr_rda = id_inst[20:16];
gpr_rda_en = 1'b1;
id_imm = {{16{id_inst[15]}}, id_inst[15:0]};
sel_imm = 1'b1;
id_rfwb_uops = `RFWBOP_LSUTWO;
id_gpr_addr_wra = id_inst[25:21];
id_gpr_addr_wrb = id_inst[20:16];
id_sig_illegal = 1'b0;
end
// stbu
`STBU_OPCD: begin
id_lsu_uops = {1'b1, `LSUOP_STB};
id_reg_zero = (id_inst[20:16] == 5'b00000);
gpr_addr_rda = id_inst[20:16];
gpr_rda_en = 1'b1;
id_imm = {{16{id_inst[15]}}, id_inst[15:0]};
sel_imm = 1'b1;
gpr_addr_rdc = id_inst[25:21];
gpr_rdc_en = 1'b1;
id_rfwb_uops = `RFWBOP_LSUEA;
id_gpr_addr_wrb = id_inst[20:16]; //[TBV] to use write port b
id_sig_illegal = 1'b0;
end
// sthu
`STHU_OPCD: begin
id_lsu_uops = {1'b1, `LSUOP_STH};
id_reg_zero = (id_inst[20:16] == 5'b00000);
gpr_addr_rda = id_inst[20:16];
gpr_rda_en = 1'b1;
id_imm = {{16{id_inst[15]}}, id_inst[15:0]};
sel_imm = 1'b1;
gpr_addr_rdc = id_inst[25:21];
gpr_rdc_en = 1'b1;
id_rfwb_uops = `RFWBOP_LSUEA;
id_gpr_addr_wrb = id_inst[20:16];
id_sig_illegal = 1'b0;
end
// stwu
`STWU_OPCD: begin
id_lsu_uops = {1'b1, `LSUOP_STW};
id_reg_zero = (id_inst[20:16] == 5'b00000);
gpr_addr_rda = id_inst[20:16];
gpr_rda_en = 1'b1;
id_imm = {{16{id_inst[15]}}, id_inst[15:0]};
sel_imm = 1'b1;
gpr_addr_rdc = id_inst[25:21];
gpr_rdc_en = 1'b1;
id_rfwb_uops = `RFWBOP_LSUEA;
id_gpr_addr_wrb = id_inst[20:16];
id_sig_illegal = 1'b0;
end
// mulli
`MULLI_OPCD: begin
id_alu_uops = {2'b00, `ALUOP_MULLI};
gpr_addr_rda = id_inst[20:16];
gpr_rda_en = 1'b1;
id_imm = {{16{id_inst[15]}}, id_inst[15:0]};
sel_imm = 1'b1;
gpr_addr_rdc = id_inst[25:21];
gpr_rdc_en = 1'b1;
id_rfwb_uops = `RFWBOP_ALU;
id_sig_illegal = 1'b0;
multicycle = `EXTEND_TWO_CYCLES;
end
// lmw
`LMW_OPCD: begin
id_sig_illegal = 1'b0;
id_sig_emulate = 1'b1;
end
// stmw
`STMW_OPCD: begin
id_sig_illegal = 1'b0;
id_sig_emulate = 1'b1;
end
// subfic
// exe: RB - EXTS(IM) -> RT;
`SUBFIC_OPCD: begin
id_alu_uops = {2'b00,`ALUOP_SUBFC};
gpr_addr_rda = id_inst[20:16];
gpr_rda_en = 1'b1;
id_imm = {{16{id_inst[15]}}, id_inst[15:0]};
sel_imm = 1'b1;
id_rfwb_uops = `RFWBOP_ALU;
id_gpr_addr_wra = id_inst[25:21];
id_sig_illegal = 1'b0;
end
// twi
// exe:
`TWI_OPCD: begin
id_cr_uops = `CROP_TRAP;
gpr_addr_rda = id_inst[20:16];
gpr_rda_en = 1'b1;
id_imm = {{16{id_inst[15]}}, id_inst[15:0]};
sel_imm = 1'b1;
id_sig_illegal = 1'b0;
end
//
// XL-Form
// all XL-Form instructions have same OPCD: 19
//
`BCCTRx_OPCD: begin
case (id_inst[10:1]) // synopsys parallel_case
// inst: bcctr[l], XL-Form
// execution: bpu
// flowchart:
// (CTR, BO, BI) -> (c)
// bcctr: (CTR[31:2], 2'b00) -> (c)PC; (c)(CTR)
// bcctrl: (CTR[31:2], 2'b00) -> (c)PC; (c)(CTR); (cia+4) -> LR
`BCCTRx_XO: begin
id_bpu_uops = {1'b0, id_inst[0], `BPUOP_BCCTR}; // {AA,LK, BPUOP}
id_sig_illegal = 1'b0;
end
// inst: bclr[l], XL-Form
// execution: bpu
// flowchart:
// (CTR, BO, BI) -> (c)
// bclr: (LR[31:2], 2'b00) -> (c)PC; (c)(CTR)
// bclrl: (LR[31:2], 2'b00) -> (c)PC; (c)(CTR); (cia+4) -> LR
`BCLRx_XO: begin
id_bpu_uops = {1'b0, id_inst[0], `BPUOP_BCLR}; // {AA,LK, BPUOP}
id_sig_illegal = 1'b0;
end
// inst: crand, XL-form
// execution: alu
// flowchart:
// CR[crb_a] func CR[crb_b] -> CR[crb_d]
`CRAND_XO: begin
id_cr_uops = `CROP_AND;
id_sig_illegal = 1'b0;
end
`CRANDC_XO : begin
id_cr_uops = `CROP_ANDC;
id_sig_illegal = 1'b0;
end
`CREQV_XO : begin
id_cr_uops = `CROP_EQV;
id_sig_illegal = 1'b0;
end
`CRORC_XO : begin
id_cr_uops = `CROP_ORC;
id_sig_illegal = 1'b0;
end
`CRNAND_XO : begin
id_cr_uops = `CROP_NAND;
id_sig_illegal = 1'b0;
end
`CRNOR_XO : begin
id_cr_uops = `CROP_NOR;
id_sig_illegal = 1'b0;
end
`CROR_XO : begin
id_cr_uops = `CROP_OR;
id_sig_illegal = 1'b0;
end
`CRXOR_XO : begin
id_cr_uops = `CROP_XOR;
id_sig_illegal = 1'b0;
end
`MCRF_XO : begin
id_reg_uops = `REGOP_MCRF;
id_sig_illegal = 1'b0;
end
`ISYNC_XO : begin
id_sig_isync = 1;
id_sig_illegal = 1'b0;
`ifdef pippo_VERBOSE
// synopsys translate_off
$display("Generating sig_isync");
// synopsys translate_on
`endif
end
`RFI_XO : begin
id_sig_rfi = 1;
id_sig_illegal = 1'b0;
`ifdef pippo_VERBOSE
// synopsys translate_off
$display("Generating sig_rfi");
// synopsys translate_on
`endif
end
`RFCI_XO : begin
id_sig_rfci = 1;
id_sig_illegal = 1'b0;
`ifdef pippo_VERBOSE
// synopsys translate_off
$display("Generating sig_rfci");
// synopsys translate_on
`endif
end
endcase // XO field of XL-Form
end
//
// OPCD: 31
// including£º
// 1, all XO-form instructions
// 2, all XFX-form instructions
// 3, part of X-form instructions, excluding fpu-related instructions(OPCD-63)
//
`ADDx_OPCD: begin
casex (id_inst[10:1]) // synopsys parallel_case
//
// XO-Form
//
// inst.: add[o][.]
// execution: alu
// flowchart:
// (RA)+(RB) -> (RT);
// (RT)->(Rc)CR[CR0]
// (RT)->(OE)XER[SO, OV]
{1'bx, `ADDx_XO}: begin
id_alu_uops = {id_inst[10], id_inst[0],`ALUOP_ADD}; // {OE,Rc,`ALUOP_ADD}
gpr_addr_rda = id_inst[20:16];
gpr_addr_rdb = id_inst[15:11];
gpr_rda_en = 1'b1;
gpr_rdb_en = 1'b1;
id_rfwb_uops = `RFWBOP_ALU;
id_gpr_addr_wra = id_inst[25:21];
id_sig_illegal = 1'b0;
end
// inst.: addc[o][.]
// execution: alu
// flowchart:
// (RA)+(RB) -> (RT);
// (RT)->XER[CA]
// (RT)->(Rc)CR[CR0]
// (RT)->(OE)XER[SO, OV]
{1'bx, `ADDCx_XO}: begin
id_alu_uops = {id_inst[10], id_inst[0],`ALUOP_ADDC};
gpr_addr_rda = id_inst[20:16];
gpr_addr_rdb = id_inst[15:11];
gpr_rda_en = 1'b1;
gpr_rdb_en = 1'b1;
id_rfwb_uops = `RFWBOP_ALU;
id_gpr_addr_wra = id_inst[25:21];
id_sig_illegal = 1'b0;
end
// inst: subf[o][.] - alu
// exe: RB - RA -> RT;
// (Rc)CR[CR0], (OE)XER[SO, OV]
{1'bx, `SUBFx_XO}: begin
id_alu_uops = {id_inst[10], id_inst[0],`ALUOP_SUBF};
gpr_addr_rda = id_inst[20:16];
gpr_addr_rdb = id_inst[15:11];
gpr_rda_en = 1'b1;
gpr_rdb_en = 1'b1;
id_rfwb_uops = `RFWBOP_ALU;
id_gpr_addr_wra = id_inst[25:21];
id_sig_illegal = 1'b0;
end
// Inst: neg[o][.] - alu
// exe: Rev(RA) + 1 -> RT;
// (Rc)CR[CR0], (OE)XER[SO, OV]
{1'bx, `NEGx_XO}: begin
id_alu_uops = {id_inst[10], id_inst[0],`ALUOP_NEG};
gpr_addr_rda = id_inst[20:16];
gpr_rda_en = 1'b1;
id_rfwb_uops = `RFWBOP_ALU;
id_gpr_addr_wra = id_inst[25:21];
id_sig_illegal = 1'b0;
end
// Inst: adde[o][.] - alu
// exe: RA + RB + XER[CA] -> RT, XER[CA];
// (Rc)CR[CR0], (OE)XER[SO, OV]
{1'bx, `ADDEx_XO}: begin
id_alu_uops = {id_inst[10], id_inst[0],`ALUOP_ADDE};
gpr_addr_rda = id_inst[20:16];
gpr_addr_rdb = id_inst[15:11];
gpr_rda_en = 1'b1;
gpr_rdb_en = 1'b1;
id_rfwb_uops = `RFWBOP_ALU;
id_gpr_addr_wra = id_inst[25:21];
id_sig_illegal = 1'b0;
end
// ADDMEx
// Inst: addme[o][.] - alu
// exe: RA + XER[CA] + (-1) -> RT, XER[CA];
// (Rc)CR[CR0], (OE)XER[SO, OV]
{1'bx, `ADDMEx_XO}: begin
id_alu_uops = {id_inst[10], id_inst[0],`ALUOP_ADDE};
gpr_addr_rda = id_inst[20:16];
gpr_rda_en = 1'b1;
id_imm = {32{1'b1}};
sel_imm = 1'b1;
id_rfwb_uops = `RFWBOP_ALU;
id_gpr_addr_wra = id_inst[25:21];
id_sig_illegal = 1'b0;
end
// Inst: addze[o][.] - alu
// exe: RA + XER[CA] -> RT, XER[CA];
// (Rc)CR[CR0], (OE)XER[SO, OV]
{1'bx, `ADDZEx_XO}: begin
id_alu_uops = {id_inst[10], id_inst[0],`ALUOP_ADDE};
gpr_addr_rda = id_inst[20:16];
gpr_rda_en = 1'b1;
id_imm = {32{1'b0}};
sel_imm = 1'b1;
id_rfwb_uops = `RFWBOP_ALU;
id_gpr_addr_wra = id_inst[25:21];
id_sig_illegal = 1'b0;
end
// Inst: subfc[o][.] - alu
// exe: RB - RA -> RT, XER[CA];
// (Rc)CR[CR0], (OE)XER[SO, OV]
{1'bx, `SUBFCx_XO}: begin
id_alu_uops = {id_inst[10], id_inst[0],`ALUOP_SUBFC};
gpr_addr_rda = id_inst[20:16];
gpr_addr_rdb = id_inst[15:11];
gpr_rda_en = 1'b1;
gpr_rdb_en = 1'b1;
id_rfwb_uops = `RFWBOP_ALU;
id_gpr_addr_wra = id_inst[25:21];
id_sig_illegal = 1'b0;
end
// Inst: subfe[o][.] - alu
// exe: Rev(RA) + RB + XER[CA] -> RT, XER[CA];
// (Rc)CR[CR0], (OE)XER[SO, OV]
{1'bx, `SUBFEx_XO}: begin
id_alu_uops = {id_inst[10], id_inst[0],`ALUOP_SUBFE};
gpr_addr_rda = id_inst[20:16];
gpr_addr_rdb = id_inst[15:11];
gpr_rda_en = 1'b1;
gpr_rdb_en = 1'b1;
id_rfwb_uops = `RFWBOP_ALU;
id_gpr_addr_wra = id_inst[25:21];
id_sig_illegal = 1'b0;
end
// Inst: subfme[o][.] - alu
// exe: Rev(RA) - 1 + XER[CA] -> RT, XER[CA];
// (Rc)CR[CR0], (OE)XER[SO, OV]
{1'bx, `SUBFMEx_XO}: begin
id_alu_uops = {id_inst[10], id_inst[0],`ALUOP_SUBFE};
gpr_addr_rda = id_inst[20:16];
gpr_rda_en = 1'b1;
id_imm = {32{1'b1}};
sel_imm = 1'b1;
id_rfwb_uops = `RFWBOP_ALU;
id_gpr_addr_wra = id_inst[25:21];
id_sig_illegal = 1'b0;
end
// Inst: subfze[o][.] - alu
// exe: Rev(RA) + XER[CA] -> RT, XER[CA];
// (Rc)CR[CR0], (OE)XER[SO, OV]
{1'bx, `SUBFZEx_XO}: begin
id_alu_uops = {id_inst[10], id_inst[0],`ALUOP_SUBFE};
gpr_addr_rda = id_inst[20:16];
gpr_rda_en = 1'b1;
id_imm = {32{1'b0}};
sel_imm = 1'b1;
id_rfwb_uops = `RFWBOP_ALU;
id_gpr_addr_wra = id_inst[25:21];
id_sig_illegal = 1'b0;
end
// MULHWx
{1'b0, `MULHWx_XO}: begin
id_alu_uops = {1'b0, id_inst[0], `ALUOP_MULHW};
gpr_addr_rda = id_inst[20:16];
gpr_rda_en = 1'b1;
gpr_addr_rdb = id_inst[15:11];
gpr_rdb_en = 1'b1;
gpr_addr_rdc = id_inst[25:21];
gpr_rdc_en = 1'b1;
id_rfwb_uops = `RFWBOP_ALU;
id_sig_illegal = 1'b0;
multicycle = `EXTEND_TWO_CYCLES;
end
// MULLWx - Not Implemented Currently
{1'bx, `MULLWx_XO}: begin
id_alu_uops = {id_inst[10], id_inst[0],`ALUOP_MULHWU};
gpr_addr_rda = id_inst[20:16];
gpr_rda_en = 1'b1;
gpr_addr_rdb = id_inst[15:11];
gpr_rdb_en = 1'b1;
gpr_addr_rdc = id_inst[25:21];
gpr_rdc_en = 1'b1;
id_rfwb_uops = `RFWBOP_ALU;
id_sig_illegal = 1'b0;
multicycle = `EXTEND_TWO_CYCLES;
end
// MULHWUx - Not Implemented Currently
{1'b0, `MULHWUx_XO}: begin
id_alu_uops = {1'b0, id_inst[0],`ALUOP_MULHW};
gpr_addr_rda = id_inst[20:16];
gpr_rda_en = 1'b1;
gpr_addr_rdb = id_inst[15:11];
gpr_rdb_en = 1'b1;
gpr_addr_rdc = id_inst[25:21];
gpr_rdc_en = 1'b1;
id_rfwb_uops = `RFWBOP_ALU;
id_sig_illegal = 1'b0;
multicycle = `EXTEND_TWO_CYCLES;
end
// DIVWx - Not Implemented Currently
{1'b0, `DIVWx_XO}: begin
id_sig_illegal = 1'b0;
id_sig_emulate = 1'b1;
end
// DIVWUx - Not Implemented Currently
{1'b0, `DIVWUx_XO}: begin
id_sig_illegal = 1'b0;
id_sig_emulate = 1'b1;
end
//
// XFX-Form
//
// mfspr
`MFSPR_XO: begin
id_reg_uops = `REGOP_MFSPR;
id_spr_addr = {id_inst[15:11], id_inst[20:16]};
id_rfwb_uops = `RFWBOP_SPRS;
id_gpr_addr_wra = id_inst[25:21];
id_sig_illegal = 1'b0;
end
// mtspr
`MTSPR_XO: begin
id_reg_uops = `REGOP_MTSPR;
id_spr_addr = {id_inst[15:11], id_inst[20:16]};
gpr_addr_rda = id_inst[25:21];
gpr_rda_en = 1'b1;
id_sig_illegal = 1'b0;
end
// mtcrf
`MTCRF_XO: begin
id_reg_uops = `REGOP_MTCRF;
gpr_addr_rda = id_inst[25:21];
gpr_rda_en = 1'b1;
id_sig_illegal = 1'b0;
end
// mftb: not-implemented
// mfspr
`MFTB_XO: begin
id_reg_uops = `REGOP_MFSPR;
id_spr_addr = {id_inst[15:11], id_inst[20:16]};
id_rfwb_uops = `RFWBOP_SPRS;
id_gpr_addr_wra = id_inst[25:21];
id_sig_illegal = 1'b0;
end
// mtdcr/mfdcr: not-implemented
`MFDCR_XO: begin
id_reg_uops = `REGOP_MFSPR;
id_spr_addr = {id_inst[15:11], id_inst[20:16]};
id_rfwb_uops = `RFWBOP_SPRS;
id_gpr_addr_wra = id_inst[25:21];
id_sig_illegal = 1'b0;
end
// mtdcr/mfdcr: not-implemented
`MTDCR_XO: begin
id_reg_uops = `REGOP_MTSPR;
id_spr_addr = {id_inst[15:11], id_inst[20:16]};
gpr_addr_rda = id_inst[25:21];
gpr_rda_en = 1'b1;
id_sig_illegal = 1'b0;
end
//
// X-Form
//
// inst: and[.]
// execution: alu
// flowchart:
// (RS) and (RB) -> (RA)
`ANDx_XO: begin
id_alu_uops = {1'b0, id_inst[0], `ALUOP_AND};
gpr_addr_rda = id_inst[25:21];
gpr_addr_rdb = id_inst[15:11];
gpr_rda_en = 1'b1;
gpr_rdb_en = 1'b1;
id_rfwb_uops = `RFWBOP_ALU;
id_gpr_addr_wra = id_inst[20:16];
id_sig_illegal = 1'b0;
end
// inst: andc[.]
// execution: alu
// flowchart:
// (RS) andc (RB) -> (RA)
`ANDCx_XO: begin
id_alu_uops = {1'b0, id_inst[0], `ALUOP_ANDC};
gpr_addr_rda = id_inst[25:21];
gpr_addr_rdb = id_inst[15:11];
gpr_rda_en = 1'b1;
gpr_rdb_en = 1'b1;
id_rfwb_uops = `RFWBOP_ALU;
id_gpr_addr_wra = id_inst[20:16];
id_sig_illegal = 1'b0;
end
// inst: nand[.]
// execution: alu
// flowchart:
// (RS) nand (RB) -> (RA)
`NANDx_XO: begin
id_alu_uops = {1'b0, id_inst[0], `ALUOP_NAND};
gpr_addr_rda = id_inst[25:21];
gpr_addr_rdb = id_inst[15:11];
gpr_rda_en = 1'b1;
gpr_rdb_en = 1'b1;
id_rfwb_uops = `RFWBOP_ALU;
id_gpr_addr_wra = id_inst[20:16];
id_sig_illegal = 1'b0;
end
// inst: or[.]
// execution: alu
// flowchart:
// (RS) or (RB) -> (RA)
`ORx_XO: begin
id_alu_uops = {1'b0, id_inst[0], `ALUOP_OR};
gpr_addr_rda = id_inst[25:21];
gpr_addr_rdb = id_inst[15:11];
gpr_rda_en = 1'b1;
gpr_rdb_en = 1'b1;
id_rfwb_uops = `RFWBOP_ALU;
id_gpr_addr_wra = id_inst[20:16];
id_sig_illegal = 1'b0;
end
// inst: orc[.]
// execution: alu
// flowchart:
// (RS) orc (RB) -> (RA)
`ORCx_XO: begin
id_alu_uops = {1'b0, id_inst[0], `ALUOP_ORC};
gpr_addr_rda = id_inst[25:21];
gpr_addr_rdb = id_inst[15:11];
gpr_rda_en = 1'b1;
gpr_rdb_en = 1'b1;
id_rfwb_uops = `RFWBOP_ALU;
id_gpr_addr_wra = id_inst[20:16];
id_sig_illegal = 1'b0;
end
// inst: xor[.]
// execution: alu
// flowchart:
// (RS) xor (RB) -> (RA)
`XORx_XO: begin
id_alu_uops = {1'b0, id_inst[0], `ALUOP_XOR};
gpr_addr_rda = id_inst[25:21];
gpr_addr_rdb = id_inst[15:11];
gpr_rda_en = 1'b1;
gpr_rdb_en = 1'b1;
id_rfwb_uops = `RFWBOP_ALU;
id_gpr_addr_wra = id_inst[20:16];
id_sig_illegal = 1'b0;
end
// inst: nor[.]
// execution: alu
// flowchart:
// (RS) nor (RB) -> (RA)
`NORx_XO: begin
id_alu_uops = {1'b0, id_inst[0], `ALUOP_NOR};
gpr_addr_rda = id_inst[25:21];
gpr_addr_rdb = id_inst[15:11];
gpr_rda_en = 1'b1;
gpr_rdb_en = 1'b1;
id_rfwb_uops = `RFWBOP_ALU;
id_gpr_addr_wra = id_inst[20:16];
id_sig_illegal = 1'b0;
end
// inst: eqv[.]
// execution: alu
// flowchart:
// (RS) eqv (RB) -> (RA)
`EQVx_XO: begin
id_alu_uops = {1'b0, id_inst[0], `ALUOP_EQV};
gpr_addr_rda = id_inst[25:21];
gpr_addr_rdb = id_inst[15:11];
gpr_rda_en = 1'b1;
gpr_rdb_en = 1'b1;
id_rfwb_uops = `RFWBOP_ALU;
id_gpr_addr_wra = id_inst[20:16];
id_sig_illegal = 1'b0;
end
// inst: cntlzw[.]
// execution: alu
// flowchart:
// cntlzw(RS) -> (RA)
`CNTLZWx_XO: begin
id_alu_uops = {1'b0, id_inst[0], `ALUOP_CNTLZW};
gpr_addr_rda = id_inst[25:21];
gpr_rda_en = 1'b1;
id_rfwb_uops = `RFWBOP_ALU;
id_gpr_addr_wra = id_inst[20:16];
id_sig_illegal = 1'b0;
end
// inst: extsb[.]
// execution: alu
// flowchart:
// extsb(RS) -> (RA)
`EXTSBx_XO: begin
id_alu_uops = {1'b0, id_inst[0], `ALUOP_EXTSB};
gpr_addr_rda = id_inst[25:21];
gpr_rda_en = 1'b1;
id_rfwb_uops = `RFWBOP_ALU;
id_gpr_addr_wra = id_inst[20:16];
id_sig_illegal = 1'b0;
end
// inst: extsh[.]
// execution: alu
// flowchart:
// extsb(RS) -> (RA)
`EXTSHx_XO: begin
id_alu_uops = {1'b0, id_inst[0], `ALUOP_EXTSH};
gpr_addr_rda = id_inst[25:21];
gpr_rda_en = 1'b1;
id_rfwb_uops = `RFWBOP_ALU;
id_gpr_addr_wra = id_inst[20:16];
id_sig_illegal = 1'b0;
end
// inst: slw[.]
// execution: alu
// flowchart:
// (RS) slw (RB) -> (RA)
`SLWx_XO: begin
id_alu_uops = {1'b0, id_inst[0], `ALUOP_SLW};
gpr_addr_rda = id_inst[25:21];
gpr_addr_rdb = id_inst[15:11];
gpr_rda_en = 1'b1;
gpr_rdb_en = 1'b1;
id_rfwb_uops = `RFWBOP_ALU;
id_gpr_addr_wra = id_inst[20:16];
id_sig_illegal = 1'b0;
end
// inst: srw[.]
// execution: alu
// flowchart:
// (RS) srw (RB) -> (RA)
`SRWx_XO: begin
id_alu_uops = {1'b0, id_inst[0], `ALUOP_SRW};
gpr_addr_rda = id_inst[25:21];
gpr_addr_rdb = id_inst[15:11];
gpr_rda_en = 1'b1;
gpr_rdb_en = 1'b1;
id_rfwb_uops = `RFWBOP_ALU;
id_gpr_addr_wra = id_inst[20:16];
id_sig_illegal = 1'b0;
end
// inst: sraw[.]
// execution: alu
// flowchart:
// (RS) sraw (RB) -> (RA)
`SRAWx_XO: begin
id_alu_uops = {1'b0, id_inst[0], `ALUOP_SRAW};
gpr_addr_rda = id_inst[25:21];
gpr_addr_rdb = id_inst[15:11];
gpr_rda_en = 1'b1;
gpr_rdb_en = 1'b1;
id_rfwb_uops = `RFWBOP_ALU;
id_gpr_addr_wra = id_inst[20:16];
id_sig_illegal = 1'b0;
end
// inst: srawi[.]
// execution: alu
// flowchart:
// (RS) sraw (SH) -> (RA)
`SRAWIx_XO: begin
id_alu_uops = {1'b0, id_inst[0], `ALUOP_SRAWI};
gpr_addr_rda = id_inst[25:21];
gpr_rda_en = 1'b1;
id_rfwb_uops = `RFWBOP_ALU;
id_gpr_addr_wra = id_inst[20:16];
id_sig_illegal = 1'b0;
end
// inst: cmp
// execution: alu
// flowchart:
// (RA) cmp (RB) -> CR[CRbf]
`CMP_XO: begin
id_cr_uops = `CROP_CMP;
gpr_addr_rda = id_inst[20:16];
gpr_addr_rdb = id_inst[15:11];
gpr_rda_en = 1'b1;
gpr_rdb_en = 1'b1;
id_sig_illegal = 1'b0;
end
// inst: cmpl
// execution: alu
// flowchart:
// (RA) cmpl (RB) -> CR[CRbf]
`CMPL_XO: begin
id_cr_uops = `CROP_CMPL;
gpr_addr_rda = id_inst[20:16];
gpr_addr_rdb = id_inst[15:11];
gpr_rda_en = 1'b1;
gpr_rdb_en = 1'b1;
id_sig_illegal = 1'b0;
end
// inst.: lbzx
// execution: lsu
// flowchart:
// 1, (RA|0) + (RB) -> EA;
// 2, {24{0}, mem(EA, 1 Byte)} -> (RT)
`LBZX_XO: begin
id_lsu_uops = {1'b0, `LSUOP_LBZ};
id_reg_zero = (id_inst[20:16] == 5'b00000);
gpr_addr_rda = id_inst[20:16];
gpr_rda_en = 1'b1;
gpr_addr_rdb = id_inst[15:11];
gpr_rdb_en = 1'b1;
id_rfwb_uops = `RFWBOP_LSU;
id_gpr_addr_wra = id_inst[25:21];
id_sig_illegal = 1'b0;
end
// inst.: lhax
// execution: lsu
// flowchart:
// 1, (RA|0) + (RB) -> EA;
// 2, {16{sign}, mem(EA, 2 Byte)} -> (RT)
`LHAX_XO: begin
id_lsu_uops = {1'b0, `LSUOP_LHA};
id_reg_zero = (id_inst[20:16] == 5'b00000);
gpr_addr_rda = id_inst[20:16];
gpr_rda_en = 1'b1;
gpr_addr_rdb = id_inst[15:11];
gpr_rdb_en = 1'b1;
id_rfwb_uops = `RFWBOP_LSU;
id_gpr_addr_wra = id_inst[25:21];
id_sig_illegal = 1'b0;
end
// inst.: lhzx
// execution: lsu
// flowchart:
// 1, (RA|0) + (RB) -> EA;
// 2, {16{0}, mem(EA, 2 Byte)} -> (RT)
`LHZX_XO: begin
id_lsu_uops = {1'b0, `LSUOP_LHZ};
id_reg_zero = (id_inst[20:16] == 5'b00000);
gpr_addr_rda = id_inst[20:16];
gpr_rda_en = 1'b1;
gpr_addr_rdb = id_inst[15:11];
gpr_rdb_en = 1'b1;
id_rfwb_uops = `RFWBOP_LSU;
id_gpr_addr_wra = id_inst[25:21];
id_sig_illegal = 1'b0;
end
// inst.: lhbrx
// execution: lsu
// flowchart:
// 1, (RA|0) + (RB) -> EA;
// 2, {16{0}, mem(EA+1, 1 Byte), mem(EA, 1 Byte)} -> (RT)
`LHBRX_XO: begin
id_lsu_uops = {1'b0, `LSUOP_LHZB};
id_reg_zero = (id_inst[20:16] == 5'b00000);
gpr_addr_rda = id_inst[20:16];
gpr_rda_en = 1'b1;
gpr_addr_rdb = id_inst[15:11];
gpr_rdb_en = 1'b1;
id_rfwb_uops = `RFWBOP_LSU;
id_gpr_addr_wra = id_inst[25:21];
id_sig_illegal = 1'b0;
end
// inst.: lwzx
// execution: lsu
// flowchart:
// 1, (RA|0) + (RB) -> EA;
// 2, mem(EA, 4 Byte) -> (RT)
`LWZX_XO: begin
id_lsu_uops = {1'b0, `LSUOP_LWZ};
id_reg_zero = (id_inst[20:16] == 5'b00000);
gpr_addr_rda = id_inst[20:16];
gpr_rda_en = 1'b1;
gpr_addr_rdb = id_inst[15:11];
gpr_rdb_en = 1'b1;
id_rfwb_uops = `RFWBOP_LSU;
id_gpr_addr_wra = id_inst[25:21];
id_sig_illegal = 1'b0;
end
// inst.: lwbrx
// execution: lsu
// flowchart:
// 1, (RA|0) + (RB) -> EA;
// 2, {mem(EA+3, 1 Byte), mem(EA+2, 1 Byte), mem(EA+1, 1 Byte), mem(EA, 1 Byte), }-> (RT)
`LWBRX_XO: begin
id_lsu_uops = {1'b0, `LSUOP_LWZB};
id_reg_zero = (id_inst[20:16] == 5'b00000);
gpr_addr_rda = id_inst[20:16];
gpr_rda_en = 1'b1;
gpr_addr_rdb = id_inst[15:11];
gpr_rdb_en = 1'b1;
id_rfwb_uops = `RFWBOP_LSU;
id_gpr_addr_wra = id_inst[25:21];
id_sig_illegal = 1'b0;
end
// inst.: lwarx
// execution: lsu
// flowchart:
// 1, (RA|0) + (RB) -> EA;
// 2, mem(EA, 4 Byte) -> (RT)
// 3, reg_atomic set to 1
`LWARX_XO: begin
id_lsu_uops = {1'b0, `LSUOP_LWZ};
id_reg_zero = (id_inst[20:16] == 5'b00000);
id_set_atomic = 1'b1;
gpr_addr_rda = id_inst[20:16];
gpr_rda_en = 1'b1;
gpr_addr_rdb = id_inst[15:11];
gpr_rdb_en = 1'b1;
id_rfwb_uops = `RFWBOP_LSU;
id_gpr_addr_wra = id_inst[25:21];
id_sig_illegal = 1'b0;
end
// inst.: stwcx.
// execution: lsu
// flowchart:
// 1, (RA|0) + EXTS(D) -> EA;
// 2, RS[31:0] -> mem(EA, 4)
`STWCXx_XO: begin
id_lsu_uops = {1'b0, `LSUOP_STW};
id_reg_zero = (id_inst[20:16] == 5'b00000);
id_clear_atomic = 1'b1;
gpr_addr_rda = id_inst[20:16];
gpr_rda_en = 1'b1;
gpr_addr_rdb = id_inst[15:11];
gpr_rdb_en = 1'b1;
gpr_addr_rdc = id_inst[25:21];
gpr_rdc_en = 1'b1;
id_sig_illegal = 1'b0;
end
// inst.: stbx
// execution: lsu
// flowchart:
// 1, (RA|0) + EXTS(D) -> EA;
// 2, RS[7:0] -> mem(EA, 1)
`STBX_XO: begin
id_lsu_uops = {1'b0, `LSUOP_STB};
id_reg_zero = (id_inst[20:16] == 5'b00000);
gpr_addr_rda = id_inst[20:16];
gpr_rda_en = 1'b1;
gpr_addr_rdb = id_inst[15:11];
gpr_rdb_en = 1'b1;
gpr_addr_rdc = id_inst[25:21];
gpr_rdc_en = 1'b1;
id_sig_illegal = 1'b0;
end
// inst.: sthx
// execution: lsu
// flowchart:
// 1, (RA|0) + EXTS(D) -> EA;
// 2, RS[15:0] -> mem(EA, 2)
`STHX_XO: begin
id_lsu_uops = {1'b0, `LSUOP_STH};
id_reg_zero = (id_inst[20:16] == 5'b00000);
gpr_addr_rda = id_inst[20:16];
gpr_rda_en = 1'b1;
gpr_addr_rdb = id_inst[15:11];
gpr_rdb_en = 1'b1;
gpr_addr_rdc = id_inst[25:21];
gpr_rdc_en = 1'b1;
id_sig_illegal = 1'b0;
end
// inst.: sthbrx
// execution: lsu
// flowchart:
// 1, (RA|0) + EXTS(D) -> EA;
// 2, {RS[7:0], RS[15:8]} -> mem(EA, 2)
`STHBRX_XO: begin
id_lsu_uops = {1'b0, `LSUOP_STHB};
id_reg_zero = (id_inst[20:16] == 5'b00000);
gpr_addr_rda = id_inst[20:16];
gpr_rda_en = 1'b1;
gpr_addr_rdb = id_inst[15:11];
gpr_rdb_en = 1'b1;
gpr_addr_rdc = id_inst[25:21];
gpr_rdc_en = 1'b1;
id_sig_illegal = 1'b0;
end
// inst.: stwx
// execution: lsu
// flowchart:
// 1, (RA|0) + EXTS(D) -> EA;
// 2, RS[31:0] -> mem(EA, 4)
`STWX_XO: begin
id_lsu_uops = {1'b0, `LSUOP_STW};
id_reg_zero = (id_inst[20:16] == 5'b00000);
gpr_addr_rda = id_inst[20:16];
gpr_rda_en = 1'b1;
gpr_addr_rdb = id_inst[15:11];
gpr_rdb_en = 1'b1;
gpr_addr_rdc = id_inst[25:21];
gpr_rdc_en = 1'b1;
id_sig_illegal = 1'b0;
end
// inst.: stwbrx
// execution: lsu
// flowchart:
// 1, (RA|0) + EXTS(D) -> EA;
// 2, {RS[7:0], RS[15:8], RS[23:16], RS[31:24]} -> mem(EA, 4)
`STWBRX_XO: begin
id_lsu_uops = {1'b0, `LSUOP_STWB};
id_reg_zero = (id_inst[20:16] == 5'b00000);
gpr_addr_rda = id_inst[20:16];
gpr_rda_en = 1'b1;
gpr_addr_rdb = id_inst[15:11];
gpr_rdb_en = 1'b1;
gpr_addr_rdc = id_inst[25:21];
gpr_rdc_en = 1'b1;
id_sig_illegal = 1'b0;
end
// lbzux
`LBZUX_XO: begin
id_lsu_uops = {1'b1, `LSUOP_LBZ};
id_reg_zero = (id_inst[20:16] == 5'b00000);
gpr_addr_rda = id_inst[20:16];
gpr_rda_en = 1'b1;
gpr_addr_rdb = id_inst[15:11];
gpr_rdb_en = 1'b1;
id_rfwb_uops = `RFWBOP_LSUTWO;
id_gpr_addr_wra = id_inst[25:21];
id_gpr_addr_wrb = id_inst[20:16];
id_sig_illegal = 1'b0;
end
// lhaux
`LHAUX_XO: begin
id_lsu_uops = {1'b1, `LSUOP_LHA};
id_reg_zero = (id_inst[20:16] == 5'b00000);
gpr_addr_rda = id_inst[20:16];
gpr_rda_en = 1'b1;
gpr_addr_rdb = id_inst[15:11];
gpr_rdb_en = 1'b1;
id_rfwb_uops = `RFWBOP_LSUTWO;
id_gpr_addr_wra = id_inst[25:21];
id_gpr_addr_wrb = id_inst[20:16];
id_sig_illegal = 1'b0;
end
// lhzux
`LHZUX_XO: begin
id_lsu_uops = {1'b1, `LSUOP_LHZ};
id_reg_zero = (id_inst[20:16] == 5'b00000);
gpr_addr_rda = id_inst[20:16];
gpr_rda_en = 1'b1;
gpr_addr_rdb = id_inst[15:11];
gpr_rdb_en = 1'b1;
id_rfwb_uops = `RFWBOP_LSUTWO;
id_gpr_addr_wra = id_inst[25:21];
id_gpr_addr_wrb = id_inst[20:16];
id_sig_illegal = 1'b0;
end
// lwzux
`LWZUX_XO: begin
id_lsu_uops = {1'b1, `LSUOP_LWZ};
id_reg_zero = (id_inst[20:16] == 5'b00000);
gpr_addr_rda = id_inst[20:16];
gpr_rda_en = 1'b1;
gpr_addr_rdb = id_inst[15:11];
gpr_rdb_en = 1'b1;
id_rfwb_uops = `RFWBOP_LSUTWO;
id_gpr_addr_wra = id_inst[25:21];
id_gpr_addr_wrb = id_inst[20:16];
id_sig_illegal = 1'b0;
end
// stbux
`STBUX_XO: begin
id_lsu_uops = {1'b1, `LSUOP_STB};
id_reg_zero = (id_inst[20:16] == 5'b00000);
gpr_addr_rda = id_inst[20:16];
gpr_rda_en = 1'b1;
gpr_addr_rdb = id_inst[15:11];
gpr_rdb_en = 1'b1;
gpr_addr_rdc = id_inst[25:21];
gpr_rdc_en = 1'b1;
id_rfwb_uops = `RFWBOP_LSUEA;
id_gpr_addr_wrb = id_inst[20:16];
id_sig_illegal = 1'b0;
end
// sthux
`STHUX_XO: begin
id_lsu_uops = {1'b1, `LSUOP_STH};
id_reg_zero = (id_inst[20:16] == 5'b00000);
gpr_addr_rda = id_inst[20:16];
gpr_rda_en = 1'b1;
gpr_addr_rdb = id_inst[15:11];
gpr_rdb_en = 1'b1;
gpr_addr_rdc = id_inst[25:21];
gpr_rdc_en = 1'b1;
id_rfwb_uops = `RFWBOP_LSUEA;
id_gpr_addr_wrb = id_inst[20:16];
id_sig_illegal = 1'b0;
end
// stwux
`STWUX_XO: begin
id_lsu_uops = {1'b1, `LSUOP_STW};
id_reg_zero = (id_inst[20:16] == 5'b00000);
gpr_addr_rda = id_inst[20:16];
gpr_rda_en = 1'b1;
gpr_addr_rdb = id_inst[15:11];
gpr_rdb_en = 1'b1;
gpr_addr_rdc = id_inst[25:21];
gpr_rdc_en = 1'b1;
id_rfwb_uops = `RFWBOP_LSUEA;
id_gpr_addr_wrb = id_inst[20:16];
id_sig_illegal = 1'b0;
end
// mfcr
`MFCR_XO: begin
id_reg_uops = `REGOP_MFCR;
id_rfwb_uops = `RFWBOP_SPRS;
id_gpr_addr_wra = id_inst[25:21];
id_sig_illegal = 1'b0;
end
// mfmsr
`MFMSR_XO: begin
id_reg_uops = `REGOP_MFMSR;
id_rfwb_uops = `RFWBOP_SPRS;
id_gpr_addr_wra = id_inst[25:21];
id_sig_illegal = 1'b0;
end
// mtspr
`MTMSR_XO: begin
id_reg_uops = `REGOP_MTMSR;
gpr_addr_rda = id_inst[25:21];
gpr_rda_en = 1'b1;
id_sig_illegal = 1'b0;
end
// mcrxr
`MCRXR_XO: begin
id_reg_uops = `REGOP_MCRXR;
id_sig_illegal = 1'b0;
end
// tw
`TW_XO: begin
id_cr_uops = `CROP_TRAP;
gpr_addr_rda = id_inst[20:16];
gpr_addr_rdb = id_inst[15:11];
gpr_rda_en = 1'b1;
gpr_rda_en = 1'b1;
id_sig_illegal = 1'b0;
end
// sync
`SYNC_XO: begin
id_sig_sync = 1;
id_sig_illegal = 1'b0;
`ifdef pippo_VERBOSE
// synopsys translate_off
$display("Generating sig_sync");
// synopsys translate_on
`endif
end
// eieio
`EIEIO_XO: begin
id_sig_eieio = 1;
id_sig_illegal = 1'b0;
`ifdef pippo_VERBOSE
// synopsys translate_off
$display("Generating sig_eieio");
// synopsys translate_on
`endif
end
//
// inst. below are decoding as X-Form, to affirm[TBD]
//
// wrtee
`WRTEE_XO: begin
id_reg_uops = `REGOP_WRTEE;
gpr_addr_rda = id_inst[25:21];
gpr_rda_en = 1'b1;
id_sig_illegal = 1'b0;
end
// wrteei
`WRTEEI_XO: begin
id_reg_uops = `REGOP_WRTEE;
id_imm = {{16{1'bx}}, id_inst[15], {15{1'bx}}};
sel_imm = 1'b1;
id_sig_illegal = 1'b0;
end
endcase // XO field
end
//
// M-Form
//
// inst: rlwimix[.]
// execution: alu
// flowchart:
`RLWIMIx_OPCD: begin
id_alu_uops = {1'b0, id_inst[0], `ALUOP_RLWIMI};
gpr_addr_rda = id_inst[25:21];
gpr_addr_rdb = id_inst[20:16];
gpr_rda_en = 1'b1;
gpr_rdb_en = 1'b1;
id_rfwb_uops = `RFWBOP_ALU;
id_gpr_addr_wra = id_inst[20:16];
id_sig_illegal = 1'b0;
end
// inst: rlwinmx[.]
// execution: alu
// flowchart:
`RLWINMx_OPCD: begin
id_alu_uops = {1'b0, id_inst[0], `ALUOP_RLWINM};
gpr_addr_rda = id_inst[25:21];
gpr_rda_en = 1'b1;
id_rfwb_uops = `RFWBOP_ALU;
id_gpr_addr_wra = id_inst[20:16];
id_sig_illegal = 1'b0;
end
// inst: rlwnmx[.]
// execution: alu
// flowchart:
`RLWNMx_OPCD: begin
id_alu_uops = {1'b0, id_inst[0], `ALUOP_RLWNM};
gpr_addr_rda = id_inst[25:21];
gpr_addr_rdb = id_inst[15:11];
gpr_rda_en = 1'b1;
gpr_rdb_en = 1'b1;
id_rfwb_uops = `RFWBOP_ALU;
id_gpr_addr_wra = id_inst[20:16];
id_sig_illegal = 1'b0;
end
// XFL-Form
// inst: mtfsf (Move to FPSCR Fields), Not-Implemented at pippo
// A-Form
// for FPU, currently non implemented
endcase // OPCODE field
end
//
// Forwarding logic
//
// write address pipeling
// [TBV] reset and flush logic
reg [`GPR_ADDR_WIDTH-1:0] ex_gpr_addr_wra;
reg [`GPR_ADDR_WIDTH-1:0] ex_gpr_addr_wrb;
always @(posedge clk or posedge rst) begin
if (rst) begin
ex_gpr_addr_wra <= #1 5'd0;
ex_gpr_addr_wrb <= #1 5'd0;
end
else if (!ex_freeze & id_freeze | flushpipe) begin
ex_gpr_addr_wra <= #1 5'd0;
ex_gpr_addr_wrb <= #1 5'd0;
end
else if (!ex_freeze) begin
ex_gpr_addr_wra <= #1 id_gpr_addr_wra;
ex_gpr_addr_wrb <= #1 id_gpr_addr_wrb;
end
end
// operandmux control signals: sel_a/sel_b
reg [`OPSEL_WIDTH-1:0] id_sel_a;
reg [`OPSEL_WIDTH-1:0] id_sel_b;
always @(gpr_addr_rda or ex_gpr_addr_wra or ex_gpr_addr_wrb or ex_rfwb_uops) begin
if ((gpr_addr_rda == ex_gpr_addr_wra) && ex_rfwb_uops[0])
id_sel_a = `OPSEL_WBFWD;
else if ((gpr_addr_rda == ex_gpr_addr_wrb) && ex_rfwb_uops[1])
id_sel_a = `OPSEL_WBFWD;
else
id_sel_a = `OPSEL_RF;
end
always @(sel_imm or gpr_addr_rdb or ex_gpr_addr_wra or ex_gpr_addr_wrb or ex_rfwb_uops) begin
if (sel_imm)
id_sel_b = `OPSEL_IMM;
else if ((gpr_addr_rdb == ex_gpr_addr_wra) && ex_rfwb_uops[0])
id_sel_b = `OPSEL_WBFWD;
else if ((gpr_addr_rdb == ex_gpr_addr_wrb) && ex_rfwb_uops[1])
id_sel_b = `OPSEL_WBFWD;
else
id_sel_b = `OPSEL_RF;
end
// [TBV] operandmuxÐźţ¨sel_a/sel_b£©µÄ¸´Î»Âß¼ºÍ¶³½áÂß¼
reg [`OPSEL_WIDTH-1:0] ex_sel_a;
reg [`OPSEL_WIDTH-1:0] ex_sel_b;
always @(posedge clk or posedge rst) begin
if (rst) begin
ex_sel_a <= #1 `OPSEL_RF;
ex_sel_b <= #1 `OPSEL_RF;
end
else if (!ex_freeze & id_freeze | flushpipe) begin
ex_sel_a <= #1 `OPSEL_RF;
ex_sel_b <= #1 `OPSEL_RF;
end
else if (!ex_freeze) begin
ex_sel_a <= #1 id_sel_a;
ex_sel_b <= #1 id_sel_b;
end
end
//
// Multicycle stall, send at EXE stage
//
reg [`MULTICYCLE_WIDTH-1:0] multicycle_cnt;
always @(posedge clk or posedge rst) begin
if (rst)
multicycle_cnt <= #1 2'b00;
else if (|multicycle_cnt)
multicycle_cnt <= #1 multicycle_cnt - 2'd1;
else if (|multicycle & !ex_freeze)
multicycle_cnt <= #1 multicycle;
end
//
// ID/EX pipelining logic
//
// pipeling of uops
reg [`BPUUOPS_WIDTH-1:0] ex_bpu_uops;
reg [`ALUUOPS_WIDTH-1:0] ex_alu_uops;
reg [`LSUUOPS_WIDTH-1:0] ex_lsu_uops;
reg [`RFWBUOPS_WIDTH-1:0] ex_reg_uops;
reg [`RFWBUOPS_WIDTH-1:0] ex_cr_uops;
always @(posedge clk or posedge rst) begin
if (rst) begin
ex_bpu_uops <= #1 {2'b00, `BPUOP_NOP}; // {AA, LK, `BPUOP_NOP}
ex_alu_uops <= #1 {2'b00, `ALUOP_NOP}; // {OE, Rc, `ALUOP_ADD}
ex_lsu_uops <= #1 `LSUOP_NOP;
ex_reg_uops <= #1 `REGOP_NOP;
ex_cr_uops <= #1 `CROP_NOP;
end
else if (!ex_freeze & id_freeze | flushpipe) begin
ex_bpu_uops <= #1 {2'b00, `BPUOP_NOP}; // {AA, LK, `BPUOP_NOP}
ex_alu_uops <= #1 {2'b00, `ALUOP_NOP}; // {OE, Rc, `ALUOP_ADD}
ex_lsu_uops <= #1 `LSUOP_NOP;
ex_reg_uops <= #1 `REGOP_NOP;
ex_cr_uops <= #1 `CROP_NOP;
end
else if (!ex_freeze) begin
ex_bpu_uops <= #1 id_bpu_uops;
ex_alu_uops <= #1 id_alu_uops;
ex_lsu_uops <= #1 id_lsu_uops;
ex_reg_uops <= #1 id_reg_uops;
ex_cr_uops <= #1 id_cr_uops;
end
end
// RFWB_UPOS pipelining
reg [`RFWBUOPS_WIDTH-1:0] ex_rfwb_uops;
always @(posedge clk or posedge rst) begin
if (rst) begin
ex_rfwb_uops <= #1 `RFWBOP_NOP;
end
else if (!ex_freeze & id_freeze | flushpipe) begin
ex_rfwb_uops <= #1 `RFWBOP_NOP;
end
else if (!ex_freeze) begin
ex_rfwb_uops <= #1 id_rfwb_uops;
end
end
// pipeling of operands
reg [29:0] ex_branch_addrofs;
//reg [31:0] ex_lsu_addrofs;
reg [9:0] ex_spr_addr;
reg [31:0] ex_imm;
always @(posedge clk or posedge rst) begin
if (rst) begin
ex_branch_addrofs <= #1 30'd0;
// ex_lsu_addrofs <= #1 32'd0;
reg_zero <= #1 1'b0;
ex_spr_addr <= #1 10'd0;
ex_imm <= #1 32'd0;
set_atomic <= 1'b0;
clear_atomic <= 1'b0;
end
else if (!ex_freeze & id_freeze | flushpipe) begin
ex_branch_addrofs <= #1 30'd0;
// ex_lsu_addrofs <= #1 32'd0;
reg_zero <= #1 1'b0;
ex_spr_addr <= #1 10'd0;
ex_imm <= #1 32'd0;
set_atomic <= 1'b0;
clear_atomic <= 1'b0;
end
else if (!ex_freeze) begin
ex_branch_addrofs <= #1 id_branch_addrofs;
// ex_lsu_addrofs <= #1 id_lsu_addrofs;
reg_zero <= #1 id_reg_zero;
ex_spr_addr <= #1 id_spr_addr;
ex_imm <= #1 id_imm;
set_atomic <= id_set_atomic;
clear_atomic <= id_clear_atomic;
end
end
// pipelining of exception requests
reg sig_syscall;
reg sig_eieio;
reg sig_isync;
reg sig_sync;
reg sig_illegal;
reg sig_emulate;
reg sig_rfi;
reg sig_rfci;
reg sig_ibuserr;
always @(posedge clk or posedge rst) begin
if (rst) begin
sig_illegal <= #1 1'b0;
sig_emulate <= #1 1'b0;
sig_syscall <= #1 1'b0;
sig_eieio <= #1 1'b0;
sig_isync <= #1 1'b0;
sig_sync <= #1 1'b0;
sig_ibuserr <= #1 1'b0;
sig_rfi <= #1 1'b0;
sig_rfci <= #1 1'b0;
end
else if (!ex_freeze & id_freeze | flushpipe) begin
sig_illegal <= #1 1'b0;
sig_emulate <= #1 1'b0;
sig_syscall <= #1 1'b0;
sig_eieio <= #1 1'b0;
sig_isync <= #1 1'b0;
sig_sync <= #1 1'b0;
sig_ibuserr <= #1 1'b0;
sig_rfi <= #1 1'b0;
sig_rfci <= #1 1'b0;
end
else if (!ex_freeze) begin
sig_illegal <= #1 id_sig_illegal;
sig_emulate <= #1 id_sig_emulate;
sig_syscall <= #1 id_sig_syscall;
sig_eieio <= #1 id_sig_eieio;
sig_isync <= #1 id_sig_isync;
sig_sync <= #1 id_sig_sync;
sig_ibuserr <= #1 id_sig_ibuserr;
sig_rfi <= #1 id_sig_rfi;
sig_rfci <= #1 id_sig_rfci;
end
end
// Pipelining inst./CIA/NIA
// [TBD] the coding style of pipeling logic: functional and performance verification
reg ex_valid, ex_valid_value;
reg [31:0] ex_inst, ex_inst_value;
reg [29:0] ex_cia, ex_cia_value;
reg [29:0] ex_snia, ex_snia_value;
always @(id_freeze or ex_freeze or flushpipe or
id_valid or id_inst or id_cia or id_snia or
ex_valid or ex_inst or ex_cia or ex_snia) begin
casex ({id_freeze, ex_freeze, flushpipe}) // synopsys parallel_case
3'b000: begin // Normal pipelining.
ex_valid_value = id_valid;
ex_inst_value = id_inst;
ex_cia_value = id_cia;
ex_snia_value = id_snia;
end
3'bxx1: begin // flushpipe is asserted, insert NOP bubble
ex_valid_value = 1'b0;
ex_inst_value = `pippo_PWR_NOP;
ex_cia_value = id_cia;
ex_snia_value = id_snia;
end
4'b100: begin // id_freeze is asserted, ex_freeze is disasserted, insert NOP bubble
ex_valid_value = 1'b0;
ex_inst_value = `pippo_PWR_NOP;
ex_cia_value = id_cia;
ex_snia_value = id_snia;
end
4'b110: begin // id_freeze/ex_freeze is asserted, insert KCS bubble
ex_valid_value = id_valid;
ex_inst_value = id_inst;
ex_cia_value = id_cia;
ex_snia_value = id_snia;
end
default: begin
ex_valid_value = 1'b0;
ex_inst_value = `pippo_PWR_NOP;
ex_cia_value = id_cia;
ex_snia_value = id_snia;
end
endcase
end
always @(posedge clk or posedge rst) begin
if(rst) begin
ex_valid <= #1 1'b0;
ex_inst <= #1 `pippo_PWR_NOP;
ex_cia <= #1 30'd0;
ex_snia <= #1 30'd0;
end
else begin
ex_valid <= #1 ex_valid_value;
ex_inst <= #1 ex_inst_value;
ex_cia <= #1 ex_cia_value;
ex_snia <= #1 ex_snia_value;
`ifdef pippo_VERBOSE
// synopsys translate_off
$display("%t: ex_valid <= %h", $time, ex_valid);
$display("%t: ex_inst <= %h", $time, ex_inst);
$display("%t: ex_cia <= %h", $time, ex_cia);
$display("%t: ex_snia <= %h", $time, ex_snia);
// synopsys translate_on
`endif
end
end
endmodule |
module sky130_fd_sc_ms__sdfxtp_4 (
Q ,
CLK ,
D ,
SCD ,
SCE ,
VPWR,
VGND,
VPB ,
VNB
);
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__sdfxtp base (
.Q(Q),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule |
module sky130_fd_sc_ms__sdfxtp_4 (
Q ,
CLK,
D ,
SCD,
SCE
);
output Q ;
input CLK;
input D ;
input SCD;
input SCE;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__sdfxtp base (
.Q(Q),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE)
);
endmodule |
module dcf77_encoder #(parameter CLOCK_FREQUENCY = 16000000
) (
input wire clk, //Clock
input wire reset, //Reset-Signal
input wire dcf77_non_inverted,
output reg dcf_sec,
output reg [58:0] dcf_outputbits
);
reg [59:0] dcf_bits;
//reg dcf_sec;
reg [30:0] cnt; //variabel
reg [2:0] dcf_edge;
parameter CNT_MAX = (11*CLOCK_FREQUENCY)/10; //1.1 sec //minute finished
parameter CNT_SAMPLE = (15*CLOCK_FREQUENCY)/100; //150 ms // < 150ms = 0; else 1
always@(posedge clk or posedge reset) begin
if(reset) begin
dcf_outputbits <= 60'b0;
dcf_bits <= 60'b0;
dcf_sec <= 1'b0;
cnt <= 0;
dcf_edge <= 3'b0;
end else begin
dcf_edge <= {dcf_edge[1:0], dcf77_non_inverted};
if(cnt < CNT_MAX) cnt <= cnt + 1;
if(dcf_edge[2:1] == 2'b01) begin
if(cnt == CNT_MAX) begin //minute finished, long 0 detected
dcf_sec <= 1'b1;
dcf_outputbits <= dcf_bits[59:1];
dcf_bits <= 0;
end else begin
dcf_sec <= 1'b0;
end
cnt <= 0;
end else dcf_sec <= 1'b0;
if(dcf_edge[2:1] == 2'b10) begin
if(cnt < CNT_SAMPLE) begin
dcf_bits <= {1'b0, dcf_bits[59:1]}; //check if cnt if < 150ms or above 150ms
end
else begin
dcf_bits <= {1'b1, dcf_bits[59:1]};
end
end
end
end
endmodule |
module
addition addition (busADD, busA, busB, zADD, oADD, cADD, nADD);
// Running the GUI part of simulation
additiontester tester (busADD, busA, busB, zADD, oADD, cADD, nADD);
// file for gtkwave
initial
begin
$dumpfile("additiontest.vcd");
$dumpvars(1, addition);
end
endmodule |
module additiontester (busADD, busA, busB, zADD, oADD, cADD, nADD);
input [31:0] busADD;
output reg [31:0] busA, busB;
input zADD, oADD, cADD, nADD;
parameter d = 20;
initial // Response
begin
$display("busADD \t busA \t busB \t\t zADD \t oADD \t cADD \t nADD \t ");
#d;
end
reg [31:0] i;
initial // Stimulus
begin
$monitor("%b \t %b \t %b \t %b \t %b \t %b \t %b", busADD, busA, busB, zADD, oADD, cADD, nADD, $time);
// positive + positive
busA = 32'h01010101; busB = 32'h01010101;
#d;
busA = 32'h7FFFFFFF; busB = 32'h7FFFFFFF; // should overflow
#d;
// positive + negative
busA = 32'h01010101; busB = 32'hFFFFFFFF; // 01010101 + -1
#d;
busA = 32'h00000001; busB = 32'hF0000000;
#d;
// negative + positive
busA = 32'hFFFFFFFF; busB = 32'h01010101;
#d;
busA = 32'hF0000000; busB = 32'h00000001;
#d;
// negative + negative
busA = 32'hFFFFFFFF; busB = 32'hFFFFFFFF; // -1 + -1
#d;
busA = 32'h90000000; busB = 32'h80000000; // should overflow
#d;
#(3*d);
$stop;
$finish;
end
endmodule |
module mult_17x16
(CLK,
A,
B,
P);
(* x_interface_info = "xilinx.com:signal:clock:1.0 clk_intf CLK" *) input CLK;
(* x_interface_info = "xilinx.com:signal:data:1.0 a_intf DATA" *) input [16:0]A;
(* x_interface_info = "xilinx.com:signal:data:1.0 b_intf DATA" *) input [15:0]B;
(* x_interface_info = "xilinx.com:signal:data:1.0 p_intf DATA" *) output [24:0]P;
wire [16:0]A;
wire [15:0]B;
wire CLK;
wire [24:0]P;
wire [47:0]NLW_U0_PCASC_UNCONNECTED;
wire [1:0]NLW_U0_ZERO_DETECT_UNCONNECTED;
(* C_A_TYPE = "1" *)
(* C_A_WIDTH = "17" *)
(* C_B_TYPE = "1" *)
(* C_B_VALUE = "10000001" *)
(* C_B_WIDTH = "16" *)
(* C_CCM_IMP = "0" *)
(* C_CE_OVERRIDES_SCLR = "0" *)
(* C_HAS_CE = "0" *)
(* C_HAS_SCLR = "0" *)
(* C_HAS_ZERO_DETECT = "0" *)
(* C_LATENCY = "4" *)
(* C_MODEL_TYPE = "0" *)
(* C_MULT_TYPE = "0" *)
(* C_OUT_HIGH = "32" *)
(* C_OUT_LOW = "8" *)
(* C_ROUND_OUTPUT = "0" *)
(* C_ROUND_PT = "0" *)
(* C_VERBOSITY = "0" *)
(* C_XDEVICEFAMILY = "kintexu" *)
(* c_optimize_goal = "1" *)
(* downgradeipidentifiedwarnings = "yes" *)
mult_17x16_mult_gen_v12_0_12 U0
(.A(A),
.B(B),
.CE(1'b1),
.CLK(CLK),
.P(P),
.PCASC(NLW_U0_PCASC_UNCONNECTED[47:0]),
.SCLR(1'b0),
.ZERO_DETECT(NLW_U0_ZERO_DETECT_UNCONNECTED[1:0]));
endmodule |
module mult_17x16_mult_gen_v12_0_12
(CLK,
A,
B,
CE,
SCLR,
ZERO_DETECT,
P,
PCASC);
input CLK;
input [16:0]A;
input [15:0]B;
input CE;
input SCLR;
output [1:0]ZERO_DETECT;
output [24:0]P;
output [47:0]PCASC;
wire \<const0> ;
wire [16:0]A;
wire [15:0]B;
wire CLK;
wire [24:0]P;
wire [47:0]NLW_i_mult_PCASC_UNCONNECTED;
wire [1:0]NLW_i_mult_ZERO_DETECT_UNCONNECTED;
assign PCASC[47] = \<const0> ;
assign PCASC[46] = \<const0> ;
assign PCASC[45] = \<const0> ;
assign PCASC[44] = \<const0> ;
assign PCASC[43] = \<const0> ;
assign PCASC[42] = \<const0> ;
assign PCASC[41] = \<const0> ;
assign PCASC[40] = \<const0> ;
assign PCASC[39] = \<const0> ;
assign PCASC[38] = \<const0> ;
assign PCASC[37] = \<const0> ;
assign PCASC[36] = \<const0> ;
assign PCASC[35] = \<const0> ;
assign PCASC[34] = \<const0> ;
assign PCASC[33] = \<const0> ;
assign PCASC[32] = \<const0> ;
assign PCASC[31] = \<const0> ;
assign PCASC[30] = \<const0> ;
assign PCASC[29] = \<const0> ;
assign PCASC[28] = \<const0> ;
assign PCASC[27] = \<const0> ;
assign PCASC[26] = \<const0> ;
assign PCASC[25] = \<const0> ;
assign PCASC[24] = \<const0> ;
assign PCASC[23] = \<const0> ;
assign PCASC[22] = \<const0> ;
assign PCASC[21] = \<const0> ;
assign PCASC[20] = \<const0> ;
assign PCASC[19] = \<const0> ;
assign PCASC[18] = \<const0> ;
assign PCASC[17] = \<const0> ;
assign PCASC[16] = \<const0> ;
assign PCASC[15] = \<const0> ;
assign PCASC[14] = \<const0> ;
assign PCASC[13] = \<const0> ;
assign PCASC[12] = \<const0> ;
assign PCASC[11] = \<const0> ;
assign PCASC[10] = \<const0> ;
assign PCASC[9] = \<const0> ;
assign PCASC[8] = \<const0> ;
assign PCASC[7] = \<const0> ;
assign PCASC[6] = \<const0> ;
assign PCASC[5] = \<const0> ;
assign PCASC[4] = \<const0> ;
assign PCASC[3] = \<const0> ;
assign PCASC[2] = \<const0> ;
assign PCASC[1] = \<const0> ;
assign PCASC[0] = \<const0> ;
assign ZERO_DETECT[1] = \<const0> ;
assign ZERO_DETECT[0] = \<const0> ;
GND GND
(.G(\<const0> ));
(* C_A_TYPE = "1" *)
(* C_A_WIDTH = "17" *)
(* C_B_TYPE = "1" *)
(* C_B_VALUE = "10000001" *)
(* C_B_WIDTH = "16" *)
(* C_CCM_IMP = "0" *)
(* C_CE_OVERRIDES_SCLR = "0" *)
(* C_HAS_CE = "0" *)
(* C_HAS_SCLR = "0" *)
(* C_HAS_ZERO_DETECT = "0" *)
(* C_LATENCY = "4" *)
(* C_MODEL_TYPE = "0" *)
(* C_MULT_TYPE = "0" *)
(* C_OUT_HIGH = "32" *)
(* C_OUT_LOW = "8" *)
(* C_ROUND_OUTPUT = "0" *)
(* C_ROUND_PT = "0" *)
(* C_VERBOSITY = "0" *)
(* C_XDEVICEFAMILY = "kintexu" *)
(* c_optimize_goal = "1" *)
(* downgradeipidentifiedwarnings = "yes" *)
mult_17x16_mult_gen_v12_0_12_viv i_mult
(.A(A),
.B(B),
.CE(1'b0),
.CLK(CLK),
.P(P),
.PCASC(NLW_i_mult_PCASC_UNCONNECTED[47:0]),
.SCLR(1'b0),
.ZERO_DETECT(NLW_i_mult_ZERO_DETECT_UNCONNECTED[1:0]));
endmodule |
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule |
module testbench;
//
// Model the free running clock on the Basys 3 bpard
//
reg clk;
initial begin
clk <= 1'b0;
forever
#5 clk <= ~clk;
end
//
// Model the reset as the center button on the Basys 3 board
//
reg reset;
initial begin
reset <= 1'b0;
#13 reset <= 1'b1;
#57 reset <= 1'b0;
end
//
// Models of LEDs and Swotches on the Basys 3 board
//
reg [7:0] switches_reg =0;
wire [7:0] switches;
wire [7:0] leds;
assign switches = switches_reg;
basic dut(/*AUTOARG*/
// Inouts
.SWITCHES(switches),
.LEDS(leds),
// Inputs
.CLK_IN(clk),
.RESET_IN(reset)
) ;
//
// Test Case Tools
//
reg test_passed = 0;
reg test_failed = 0;
integer i;
//
// If test fails, alert user and terminate simulation
//
always @(posedge test_failed) begin
$display("Test Failed @ %d" % $time);
#10 $finish;
end
//
// If test passes, alert user and terminate simulation
//
always @(posedge test_passed) begin
$display("TEST PASSED @ %d", $time);
#10 $finish;
end
//
// Time out issues, if our test does not complete in time, fail it
//
initial begin
#100_000;
$display("TEST CASE TIMED OUT ");
test_failed <= 1;
end
//
// Run our test case!
//
initial begin
//
// Wait for reset to finish before starting test case
//
@(posedge reset);
repeat (10) @(posedge clk);
for (i=0; i<8; i=i+1) begin
switches_reg[i] <= (1 << i); //Flip switch up
@(posedge leds[i]); //Wait for corresponding LED to light up
end
repeat (10) @(posedge clk);
switches_reg <= 8'hFF;
repeat (10) @(posedge clk);
for (i=0; i<8; i=i+1) begin
switches_reg[i] <= (0 << i); //Flip switch down
@(negedge leds[i]); //Wait for corresponding LED to turn off
end
test_passed <= 1;
end
endmodule |
module MultiState(
input clk,
input rst,
input [5:0] op,
output [2:0] state
);
reg [2:0] tmp;
assign state = tmp;
always@(posedge clk) begin
if (rst == 0) begin
tmp = 3'B000;
end else begin
case (tmp)
3'B000: tmp = 3'B001;
3'B001: begin
if (op[5:3] == 3'B111) begin // j, jal, jr, halt
tmp = 3'B000;
end else begin // others
tmp = 3'B010;
end
end
3'B010: begin
if (op[5:2] == 4'B1101) begin // beq, bltz
tmp = 3'B000;
end else if (op[5:2] == 4'B1100) begin // sw, lw
tmp = 3'B100;
end else begin // others
tmp = 3'B011;
end
end
3'B011: tmp = 3'B000;
3'B100: begin
if (op[0] == 1) begin // lw
tmp = 3'B011;
end else begin
tmp = 3'B000;
end
end
endcase
end
end
endmodule |
module sky130_fd_sc_hs__edfxbp (
//# {{data|Data Signals}}
input D ,
output Q ,
output Q_N,
//# {{control|Control Signals}}
input DE ,
//# {{clocks|Clocking}}
input CLK
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule |
module sandbox
(
output wire [127:0] OLED_S0,
output wire [127:0] OLED_S1,
output wire [127:0] OLED_S2,
output wire [127:0] OLED_S3,
input wire GCLK,
output wire [7:0] LD,
input wire [7:0] SW,
output wire [7:0] JA,
input wire [7:0] JB,
input wire BTNC,
input wire BTND,
input wire BTNL,
input wire BTNR,
input wire BTNU
);
wire MISO;
wire MOSI;
wire SS;
wire SCLK;
reg SS_REG = 1'b0;
reg SCLK_REG = 1'b0;
assign JA[2] = SS_REG;
assign JA[3] = SCLK_REG;
always @(posedge GCLK) begin
SS_REG <= SS;
SCLK_REG <= SCLK;
end
//assign JA[3] = SCLK;
SPI #(.m(15), .Tbit(100)) spi
(
// External interfaces
.str0(OLED_S0),
.str1(OLED_S1),
.str2(OLED_S2),
.str3(OLED_S3),
.GCLK(GCLK),
.RST(BTND),
.SW(SW),
// Transmission start switch
.st(BTNC),
// SPI Master bus
//.MASTER_MISO(MISO),
//.MASTER_MOSI(MOSI),
.MASTER_SS(SS),
.MASTER_SCLK(SCLK),
.MASTER_MISO(JB[0]),
.MASTER_MOSI(JA[1]),
//.MASTER_SS(JA[2]),
//.MASTER_SCLK(JA[3]),
// SPI Slave bus
//.SLAVE_MISO(MISO),
//.SLAVE_MOSI(MOSI),
.SLAVE_SS(SS),
.SLAVE_SCLK(SCLK),
.SLAVE_MOSI(JB[1]),
.SLAVE_MISO(JA[0])
//.SLAVE_SS(JB[2])
//.SLAVE_SCLK(JB[3])
);
endmodule |
module OUT_FIFO (
ALMOSTEMPTY,
ALMOSTFULL,
EMPTY,
FULL,
Q0,
Q1,
Q2,
Q3,
Q4,
Q5,
Q6,
Q7,
Q8,
Q9,
D0,
D1,
D2,
D3,
D4,
D5,
D6,
D7,
D8,
D9,
RDCLK,
RDEN,
RESET,
WRCLK,
WREN
);
`ifdef XIL_TIMING
parameter LOC = "UNPLACED";
`endif
parameter integer ALMOST_EMPTY_VALUE = 1;
parameter integer ALMOST_FULL_VALUE = 1;
parameter ARRAY_MODE = "ARRAY_MODE_8_X_4";
parameter OUTPUT_DISABLE = "FALSE";
parameter SYNCHRONOUS_MODE = "FALSE";
`ifdef XIL_TIMING
localparam in_delay = 0;
localparam out_delay = 0;
`else
localparam in_delay = 1;
localparam out_delay = 10;
`endif
localparam INCLK_DELAY = 0;
localparam OUTCLK_DELAY = 0;
localparam MODULE_NAME = "OUT_FIFO";
output ALMOSTEMPTY;
output ALMOSTFULL;
output EMPTY;
output FULL;
output [3:0] Q0;
output [3:0] Q1;
output [3:0] Q2;
output [3:0] Q3;
output [3:0] Q4;
output [3:0] Q7;
output [3:0] Q8;
output [3:0] Q9;
output [7:0] Q5;
output [7:0] Q6;
input RDCLK;
input RDEN;
input RESET;
input WRCLK;
input WREN;
input [7:0] D0;
input [7:0] D1;
input [7:0] D2;
input [7:0] D3;
input [7:0] D4;
input [7:0] D5;
input [7:0] D6;
input [7:0] D7;
input [7:0] D8;
input [7:0] D9;
reg [0:0] ARRAY_MODE_BINARY;
reg [0:0] OUTPUT_DISABLE_BINARY;
reg [0:0] SLOW_RD_CLK_BINARY;
reg [0:0] SLOW_WR_CLK_BINARY;
reg [0:0] SYNCHRONOUS_MODE_BINARY;
reg [3:0] SPARE_BINARY;
reg [7:0] ALMOST_EMPTY_VALUE_BINARY;
reg [7:0] ALMOST_FULL_VALUE_BINARY;
tri0 GSR = glbl.GSR;
`ifdef XIL_TIMING
reg notifier;
`endif
initial begin
case (ALMOST_EMPTY_VALUE)
1 : ALMOST_EMPTY_VALUE_BINARY <= 8'b01000001;
2 : ALMOST_EMPTY_VALUE_BINARY <= 8'b01100011;
default : begin
$display("Attribute Syntax Error : The Attribute ALMOST_EMPTY_VALUE on %s instance %m is set to %d. Legal values for this attribute are 1 to 2.", MODULE_NAME, ALMOST_EMPTY_VALUE);
#1 $finish;
end
endcase
case (ALMOST_FULL_VALUE)
1 : ALMOST_FULL_VALUE_BINARY <= 8'b01000001;
2 : ALMOST_FULL_VALUE_BINARY <= 8'b01100011;
default : begin
$display("Attribute Syntax Error : The Attribute ALMOST_FULL_VALUE on %s instance %m is set to %d. Legal values for this attribute are 1 to 2.", MODULE_NAME, ALMOST_FULL_VALUE);
#1 $finish;
end
endcase
case (ARRAY_MODE)
"ARRAY_MODE_8_X_4" : ARRAY_MODE_BINARY <= 1'b1;
"ARRAY_MODE_4_X_4" : ARRAY_MODE_BINARY <= 1'b0;
default : begin
$display("Attribute Syntax Error : The Attribute ARRAY_MODE on %s instance %m is set to %s. Legal values for this attribute are ARRAY_MODE_8_X_4 or ARRAY_MODE_4_X_4.", MODULE_NAME, ARRAY_MODE);
#1 $finish;
end
endcase
case (OUTPUT_DISABLE)
"FALSE" : OUTPUT_DISABLE_BINARY <= 1'b0;
"TRUE" : OUTPUT_DISABLE_BINARY <= 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute OUTPUT_DISABLE on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, OUTPUT_DISABLE);
#1 $finish;
end
endcase
SLOW_RD_CLK_BINARY <= 1'b0;
SLOW_WR_CLK_BINARY <= 1'b0;
SPARE_BINARY <= 4'b0;
case (SYNCHRONOUS_MODE)
"FALSE" : SYNCHRONOUS_MODE_BINARY <= 1'b0;
default : begin
$display("Attribute Syntax Error : The Attribute SYNCHRONOUS_MODE on %s instance %m is set to %s. The legal value for this attribute is FALSE.", MODULE_NAME, SYNCHRONOUS_MODE);
#1 $finish;
end
endcase
end
wire [3:0] delay_Q0;
wire [3:0] delay_Q1;
wire [3:0] delay_Q2;
wire [3:0] delay_Q3;
wire [3:0] delay_Q4;
wire [3:0] delay_Q7;
wire [3:0] delay_Q8;
wire [3:0] delay_Q9;
wire [7:0] delay_Q5;
wire [7:0] delay_Q6;
wire delay_ALMOSTEMPTY;
wire delay_ALMOSTFULL;
wire delay_EMPTY;
wire delay_FULL;
wire [3:0] delay_SCANOUT;
wire [7:0] delay_D0;
wire [7:0] delay_D1;
wire [7:0] delay_D2;
wire [7:0] delay_D3;
wire [7:0] delay_D4;
wire [7:0] delay_D5;
wire [7:0] delay_D6;
wire [7:0] delay_D7;
wire [7:0] delay_D8;
wire [7:0] delay_D9;
wire delay_RDCLK;
wire delay_RDEN;
wire delay_RESET;
wire delay_SCANENB = 1'b1;
wire delay_TESTMODEB = 1'b1;
wire delay_TESTREADDISB = 1'b1;
wire delay_TESTWRITEDISB = 1'b1;
wire [3:0] delay_SCANIN = 4'hf;
wire delay_WRCLK;
wire delay_WREN;
wire delay_GSR;
assign #(out_delay) ALMOSTEMPTY = delay_ALMOSTEMPTY;
assign #(out_delay) ALMOSTFULL = delay_ALMOSTFULL;
assign #(out_delay) EMPTY = delay_EMPTY;
assign #(out_delay) FULL = delay_FULL;
assign #(out_delay) Q0 = delay_Q0;
assign #(out_delay) Q1 = delay_Q1;
assign #(out_delay) Q2 = delay_Q2;
assign #(out_delay) Q3 = delay_Q3;
assign #(out_delay) Q4 = delay_Q4;
assign #(out_delay) Q5 = delay_Q5;
assign #(out_delay) Q6 = delay_Q6;
assign #(out_delay) Q7 = delay_Q7;
assign #(out_delay) Q8 = delay_Q8;
assign #(out_delay) Q9 = delay_Q9;
`ifndef XIL_TIMING
assign #(INCLK_DELAY) delay_RDCLK = RDCLK;
assign #(INCLK_DELAY) delay_WRCLK = WRCLK;
assign #(in_delay) delay_D0 = D0;
assign #(in_delay) delay_D1 = D1;
assign #(in_delay) delay_D2 = D2;
assign #(in_delay) delay_D3 = D3;
assign #(in_delay) delay_D4 = D4;
assign #(in_delay) delay_D5 = D5;
assign #(in_delay) delay_D6 = D6;
assign #(in_delay) delay_D7 = D7;
assign #(in_delay) delay_D8 = D8;
assign #(in_delay) delay_D9 = D9;
assign #(in_delay) delay_RDEN = RDEN;
`endif
assign #(in_delay) delay_RESET = RESET;
`ifndef XIL_TIMING
assign #(in_delay) delay_WREN = WREN;
`endif
assign delay_GSR = GSR;
SIP_OUT_FIFO OUT_FIFO_INST (
.ALMOST_EMPTY_VALUE (ALMOST_EMPTY_VALUE_BINARY),
.ALMOST_FULL_VALUE (ALMOST_FULL_VALUE_BINARY),
.ARRAY_MODE (ARRAY_MODE_BINARY),
.OUTPUT_DISABLE (OUTPUT_DISABLE_BINARY),
.SLOW_RD_CLK (SLOW_RD_CLK_BINARY),
.SLOW_WR_CLK (SLOW_WR_CLK_BINARY),
.SPARE (SPARE_BINARY),
.SYNCHRONOUS_MODE (SYNCHRONOUS_MODE_BINARY),
.ALMOSTEMPTY (delay_ALMOSTEMPTY),
.ALMOSTFULL (delay_ALMOSTFULL),
.EMPTY (delay_EMPTY),
.FULL (delay_FULL),
.Q0 (delay_Q0),
.Q1 (delay_Q1),
.Q2 (delay_Q2),
.Q3 (delay_Q3),
.Q4 (delay_Q4),
.Q5 (delay_Q5),
.Q6 (delay_Q6),
.Q7 (delay_Q7),
.Q8 (delay_Q8),
.Q9 (delay_Q9),
.SCANOUT (delay_SCANOUT),
.D0 (delay_D0),
.D1 (delay_D1),
.D2 (delay_D2),
.D3 (delay_D3),
.D4 (delay_D4),
.D5 (delay_D5),
.D6 (delay_D6),
.D7 (delay_D7),
.D8 (delay_D8),
.D9 (delay_D9),
.RDCLK (delay_RDCLK),
.RDEN (delay_RDEN),
.RESET (delay_RESET),
.SCANENB (delay_SCANENB),
.SCANIN (delay_SCANIN),
.TESTMODEB (delay_TESTMODEB),
.TESTREADDISB (delay_TESTREADDISB),
.TESTWRITEDISB (delay_TESTWRITEDISB),
.WRCLK (delay_WRCLK),
.WREN (delay_WREN),
.GSR (delay_GSR)
);
`ifdef XIL_TIMING
specify
$period (negedge RDCLK, 0:0:0, notifier);
$period (negedge WRCLK, 0:0:0, notifier);
$period (posedge RDCLK, 0:0:0, notifier);
$period (posedge WRCLK, 0:0:0, notifier);
$setuphold (posedge RDCLK, negedge RDEN, 0:0:0, 0:0:0, notifier,,, delay_RDCLK, delay_RDEN);
$setuphold (posedge RDCLK, posedge RDEN, 0:0:0, 0:0:0, notifier,,, delay_RDCLK, delay_RDEN);
$setuphold (posedge WRCLK, negedge D0, 0:0:0, 0:0:0, notifier,,, delay_WRCLK, delay_D0);
$setuphold (posedge WRCLK, negedge D1, 0:0:0, 0:0:0, notifier,,, delay_WRCLK, delay_D1);
$setuphold (posedge WRCLK, negedge D2, 0:0:0, 0:0:0, notifier,,, delay_WRCLK, delay_D2);
$setuphold (posedge WRCLK, negedge D3, 0:0:0, 0:0:0, notifier,,, delay_WRCLK, delay_D3);
$setuphold (posedge WRCLK, negedge D4, 0:0:0, 0:0:0, notifier,,, delay_WRCLK, delay_D4);
$setuphold (posedge WRCLK, negedge D5, 0:0:0, 0:0:0, notifier,,, delay_WRCLK, delay_D5);
$setuphold (posedge WRCLK, negedge D6, 0:0:0, 0:0:0, notifier,,, delay_WRCLK, delay_D6);
$setuphold (posedge WRCLK, negedge D7, 0:0:0, 0:0:0, notifier,,, delay_WRCLK, delay_D7);
$setuphold (posedge WRCLK, negedge D8, 0:0:0, 0:0:0, notifier,,, delay_WRCLK, delay_D8);
$setuphold (posedge WRCLK, negedge D9, 0:0:0, 0:0:0, notifier,,, delay_WRCLK, delay_D9);
$setuphold (posedge WRCLK, negedge WREN, 0:0:0, 0:0:0, notifier,,, delay_WRCLK, delay_WREN);
$setuphold (posedge WRCLK, posedge D0, 0:0:0, 0:0:0, notifier,,, delay_WRCLK, delay_D0);
$setuphold (posedge WRCLK, posedge D1, 0:0:0, 0:0:0, notifier,,, delay_WRCLK, delay_D1);
$setuphold (posedge WRCLK, posedge D2, 0:0:0, 0:0:0, notifier,,, delay_WRCLK, delay_D2);
$setuphold (posedge WRCLK, posedge D3, 0:0:0, 0:0:0, notifier,,, delay_WRCLK, delay_D3);
$setuphold (posedge WRCLK, posedge D4, 0:0:0, 0:0:0, notifier,,, delay_WRCLK, delay_D4);
$setuphold (posedge WRCLK, posedge D5, 0:0:0, 0:0:0, notifier,,, delay_WRCLK, delay_D5);
$setuphold (posedge WRCLK, posedge D6, 0:0:0, 0:0:0, notifier,,, delay_WRCLK, delay_D6);
$setuphold (posedge WRCLK, posedge D7, 0:0:0, 0:0:0, notifier,,, delay_WRCLK, delay_D7);
$setuphold (posedge WRCLK, posedge D8, 0:0:0, 0:0:0, notifier,,, delay_WRCLK, delay_D8);
$setuphold (posedge WRCLK, posedge D9, 0:0:0, 0:0:0, notifier,,, delay_WRCLK, delay_D9);
$setuphold (posedge WRCLK, posedge WREN, 0:0:0, 0:0:0, notifier,,, delay_WRCLK, delay_WREN);
$width (negedge RDCLK, 0:0:0, 0, notifier);
$width (negedge RESET, 0:0:0, 0, notifier);
$width (negedge WRCLK, 0:0:0, 0, notifier);
$width (posedge RDCLK, 0:0:0, 0, notifier);
$width (posedge RESET, 0:0:0, 0, notifier);
$width (posedge WRCLK, 0:0:0, 0, notifier);
( RDCLK *> ALMOSTEMPTY) = (10:10:10, 10:10:10);
( RDCLK *> EMPTY) = (10:10:10, 10:10:10);
( RDCLK *> Q0) = (10:10:10, 10:10:10);
( RDCLK *> Q1) = (10:10:10, 10:10:10);
( RDCLK *> Q2) = (10:10:10, 10:10:10);
( RDCLK *> Q3) = (10:10:10, 10:10:10);
( RDCLK *> Q4) = (10:10:10, 10:10:10);
( RDCLK *> Q5) = (10:10:10, 10:10:10);
( RDCLK *> Q6) = (10:10:10, 10:10:10);
( RDCLK *> Q7) = (10:10:10, 10:10:10);
( RDCLK *> Q8) = (10:10:10, 10:10:10);
( RDCLK *> Q9) = (10:10:10, 10:10:10);
if (OUTPUT_DISABLE_BINARY) ( RDEN *> Q0) = (10:10:10, 10:10:10);
if (OUTPUT_DISABLE_BINARY) ( RDEN *> Q1) = (10:10:10, 10:10:10);
if (OUTPUT_DISABLE_BINARY) ( RDEN *> Q2) = (10:10:10, 10:10:10);
if (OUTPUT_DISABLE_BINARY) ( RDEN *> Q3) = (10:10:10, 10:10:10);
if (OUTPUT_DISABLE_BINARY) ( RDEN *> Q4) = (10:10:10, 10:10:10);
if (OUTPUT_DISABLE_BINARY) ( RDEN *> Q5) = (10:10:10, 10:10:10);
if (OUTPUT_DISABLE_BINARY) ( RDEN *> Q6) = (10:10:10, 10:10:10);
if (OUTPUT_DISABLE_BINARY) ( RDEN *> Q7) = (10:10:10, 10:10:10);
if (OUTPUT_DISABLE_BINARY) ( RDEN *> Q8) = (10:10:10, 10:10:10);
if (OUTPUT_DISABLE_BINARY) ( RDEN *> Q9) = (10:10:10, 10:10:10);
( WRCLK *> ALMOSTFULL) = (10:10:10, 10:10:10);
( WRCLK *> FULL) = (10:10:10, 10:10:10);
specparam PATHPULSE$ = 0;
endspecify
`endif
endmodule |
module uart_loader
(
input clk,
input calib_done,
input disabled,
output reg started,
output reg done,
output [7:0] progress,
input rx,
output reg mem_cmd_en,
output [2:0] mem_cmd_instr,
output [5:0] mem_cmd_bl,
output reg [29:0] mem_cmd_byte_addr,
input mem_cmd_empty,
input mem_cmd_full,
output reg mem_wr_en,
output [3:0] mem_wr_mask,
output reg [31:0] mem_wr_data,
input mem_wr_full,
input mem_wr_empty,
input [6:0] mem_wr_count,
input mem_wr_underrun,
input mem_wr_error
);
// Our interface with RAM is write-only, so always give the
// write command (000)
assign mem_cmd_instr = 3'b000;
// We always want to write 256-byte blocks to RAM, so always
// use a burst length of 64 32-bit chunks
assign mem_cmd_bl = 6'b111111;
// We also always want to write 32-bit chunks, so don't mask
// any bytes
assign mem_wr_mask = 4'b0000;
// Initialize registers
initial begin
started = 0;
done = 0;
mem_cmd_en = 0;
mem_wr_en = 0;
end
// A reader for individual bytes of data off of the serial
// interface. Use a higher baud rate so we get better throughput.
// Data transfer takes ((2^19)/BAUD) = 4.55 seconds at 115200 baud
wire busy;
wire [7:0] uart_data;
uart uart_
(
.clk(clk),
.rst(1'b0),
.rx(rx),
.busy(busy),
.data(uart_data)
);
// State machine logic to load data
reg [2:0] state = 0;
reg [7:0] cur_line = 0;
reg [7:0] cur_byte = 0;
reg busy_prev = 0;
assign progress = cur_line;
always @ (posedge clk) begin
busy_prev <= busy;
mem_cmd_en <= 0;
mem_wr_en <= 0;
case (state)
// Wait for calibration to complete
0: begin
if (calib_done) begin
state <= 1;
end
end
// Receive 256 bytes, load them into the RAM fifo
1: begin
// If we just received a byte
if (!busy && busy_prev && !disabled) begin
started <= 1;
cur_byte <= cur_byte + 1;
mem_wr_data <= { mem_wr_data[23:0], uart_data };
// If we just filled up a word, send it
// to the write fifo
if (2'b11 == cur_byte[1:0]) begin
mem_wr_en <= 1;
end
// If we just filled up a row, send a write command
if (255 == cur_byte) begin
state <= 2;
end
end
end
// Send a write command for the line
2: begin
if (mem_cmd_en) begin
if (255 == cur_line) begin
state <= 3;
end else begin
cur_line <= cur_line + 1;
state <= 1;
end
end else begin
mem_cmd_byte_addr <= { `MAIN_MEM_PREFIX, cur_line, 8'b0 };
mem_cmd_en <= 1;
end
end
// Send the done signal and do nothing
3: begin
done <= 1;
end
endcase
end
endmodule |
module pr_region_default_mm_bridge_0 #(
parameter DATA_WIDTH = 32,
parameter SYMBOL_WIDTH = 8,
parameter HDL_ADDR_WIDTH = 10,
parameter BURSTCOUNT_WIDTH = 1,
parameter PIPELINE_COMMAND = 1,
parameter PIPELINE_RESPONSE = 1
) (
input wire clk, // clk.clk
input wire m0_waitrequest, // m0.waitrequest
input wire [DATA_WIDTH-1:0] m0_readdata, // .readdata
input wire m0_readdatavalid, // .readdatavalid
output wire [BURSTCOUNT_WIDTH-1:0] m0_burstcount, // .burstcount
output wire [DATA_WIDTH-1:0] m0_writedata, // .writedata
output wire [HDL_ADDR_WIDTH-1:0] m0_address, // .address
output wire m0_write, // .write
output wire m0_read, // .read
output wire [3:0] m0_byteenable, // .byteenable
output wire m0_debugaccess, // .debugaccess
input wire reset, // reset.reset
output wire s0_waitrequest, // s0.waitrequest
output wire [DATA_WIDTH-1:0] s0_readdata, // .readdata
output wire s0_readdatavalid, // .readdatavalid
input wire [BURSTCOUNT_WIDTH-1:0] s0_burstcount, // .burstcount
input wire [DATA_WIDTH-1:0] s0_writedata, // .writedata
input wire [HDL_ADDR_WIDTH-1:0] s0_address, // .address
input wire s0_write, // .write
input wire s0_read, // .read
input wire [3:0] s0_byteenable, // .byteenable
input wire s0_debugaccess // .debugaccess
);
altera_avalon_mm_bridge #(
.DATA_WIDTH (DATA_WIDTH),
.SYMBOL_WIDTH (SYMBOL_WIDTH),
.HDL_ADDR_WIDTH (HDL_ADDR_WIDTH),
.BURSTCOUNT_WIDTH (BURSTCOUNT_WIDTH),
.PIPELINE_COMMAND (PIPELINE_COMMAND),
.PIPELINE_RESPONSE (PIPELINE_RESPONSE)
) mm_bridge_0 (
.clk (clk), // input, width = 1, clk.clk
.reset (reset), // input, width = 1, reset.reset
.s0_waitrequest (s0_waitrequest), // output, width = 1, s0.waitrequest
.s0_readdata (s0_readdata), // output, width = DATA_WIDTH, .readdata
.s0_readdatavalid (s0_readdatavalid), // output, width = 1, .readdatavalid
.s0_burstcount (s0_burstcount), // input, width = BURSTCOUNT_WIDTH, .burstcount
.s0_writedata (s0_writedata), // input, width = DATA_WIDTH, .writedata
.s0_address (s0_address), // input, width = HDL_ADDR_WIDTH, .address
.s0_write (s0_write), // input, width = 1, .write
.s0_read (s0_read), // input, width = 1, .read
.s0_byteenable (s0_byteenable), // input, width = 4, .byteenable
.s0_debugaccess (s0_debugaccess), // input, width = 1, .debugaccess
.m0_waitrequest (m0_waitrequest), // input, width = 1, m0.waitrequest
.m0_readdata (m0_readdata), // input, width = DATA_WIDTH, .readdata
.m0_readdatavalid (m0_readdatavalid), // input, width = 1, .readdatavalid
.m0_burstcount (m0_burstcount), // output, width = BURSTCOUNT_WIDTH, .burstcount
.m0_writedata (m0_writedata), // output, width = DATA_WIDTH, .writedata
.m0_address (m0_address), // output, width = HDL_ADDR_WIDTH, .address
.m0_write (m0_write), // output, width = 1, .write
.m0_read (m0_read), // output, width = 1, .read
.m0_byteenable (m0_byteenable), // output, width = 4, .byteenable
.m0_debugaccess (m0_debugaccess), // output, width = 1, .debugaccess
.s0_response (), // (terminated),
.m0_response (2'b00) // (terminated),
);
endmodule |
module lab3_mm_interconnect_0 (
input wire [11:0] hps_0_h2f_lw_axi_master_awid, // hps_0_h2f_lw_axi_master.awid
input wire [20:0] hps_0_h2f_lw_axi_master_awaddr, // .awaddr
input wire [3:0] hps_0_h2f_lw_axi_master_awlen, // .awlen
input wire [2:0] hps_0_h2f_lw_axi_master_awsize, // .awsize
input wire [1:0] hps_0_h2f_lw_axi_master_awburst, // .awburst
input wire [1:0] hps_0_h2f_lw_axi_master_awlock, // .awlock
input wire [3:0] hps_0_h2f_lw_axi_master_awcache, // .awcache
input wire [2:0] hps_0_h2f_lw_axi_master_awprot, // .awprot
input wire hps_0_h2f_lw_axi_master_awvalid, // .awvalid
output wire hps_0_h2f_lw_axi_master_awready, // .awready
input wire [11:0] hps_0_h2f_lw_axi_master_wid, // .wid
input wire [31:0] hps_0_h2f_lw_axi_master_wdata, // .wdata
input wire [3:0] hps_0_h2f_lw_axi_master_wstrb, // .wstrb
input wire hps_0_h2f_lw_axi_master_wlast, // .wlast
input wire hps_0_h2f_lw_axi_master_wvalid, // .wvalid
output wire hps_0_h2f_lw_axi_master_wready, // .wready
output wire [11:0] hps_0_h2f_lw_axi_master_bid, // .bid
output wire [1:0] hps_0_h2f_lw_axi_master_bresp, // .bresp
output wire hps_0_h2f_lw_axi_master_bvalid, // .bvalid
input wire hps_0_h2f_lw_axi_master_bready, // .bready
input wire [11:0] hps_0_h2f_lw_axi_master_arid, // .arid
input wire [20:0] hps_0_h2f_lw_axi_master_araddr, // .araddr
input wire [3:0] hps_0_h2f_lw_axi_master_arlen, // .arlen
input wire [2:0] hps_0_h2f_lw_axi_master_arsize, // .arsize
input wire [1:0] hps_0_h2f_lw_axi_master_arburst, // .arburst
input wire [1:0] hps_0_h2f_lw_axi_master_arlock, // .arlock
input wire [3:0] hps_0_h2f_lw_axi_master_arcache, // .arcache
input wire [2:0] hps_0_h2f_lw_axi_master_arprot, // .arprot
input wire hps_0_h2f_lw_axi_master_arvalid, // .arvalid
output wire hps_0_h2f_lw_axi_master_arready, // .arready
output wire [11:0] hps_0_h2f_lw_axi_master_rid, // .rid
output wire [31:0] hps_0_h2f_lw_axi_master_rdata, // .rdata
output wire [1:0] hps_0_h2f_lw_axi_master_rresp, // .rresp
output wire hps_0_h2f_lw_axi_master_rlast, // .rlast
output wire hps_0_h2f_lw_axi_master_rvalid, // .rvalid
input wire hps_0_h2f_lw_axi_master_rready, // .rready
input wire clk_0_clk_clk, // clk_0_clk.clk
input wire hps_0_h2f_lw_axi_master_agent_clk_reset_reset_bridge_in_reset_reset, // hps_0_h2f_lw_axi_master_agent_clk_reset_reset_bridge_in_reset.reset
input wire master_0_clk_reset_reset_bridge_in_reset_reset, // master_0_clk_reset_reset_bridge_in_reset.reset
input wire vga_led_0_reset_sink_reset_bridge_in_reset_reset, // vga_led_0_reset_sink_reset_bridge_in_reset.reset
input wire [31:0] master_0_master_address, // master_0_master.address
output wire master_0_master_waitrequest, // .waitrequest
input wire [3:0] master_0_master_byteenable, // .byteenable
input wire master_0_master_read, // .read
output wire [31:0] master_0_master_readdata, // .readdata
output wire master_0_master_readdatavalid, // .readdatavalid
input wire master_0_master_write, // .write
input wire [31:0] master_0_master_writedata, // .writedata
output wire [0:0] audio_emulator_0_avalon_slave_0_address, // audio_emulator_0_avalon_slave_0.address
output wire audio_emulator_0_avalon_slave_0_write, // .write
output wire [15:0] audio_emulator_0_avalon_slave_0_writedata, // .writedata
output wire audio_emulator_0_avalon_slave_0_chipselect, // .chipselect
output wire [3:0] vga_led_0_avalon_slave_0_address, // vga_led_0_avalon_slave_0.address
output wire vga_led_0_avalon_slave_0_write, // .write
output wire [15:0] vga_led_0_avalon_slave_0_writedata, // .writedata
output wire vga_led_0_avalon_slave_0_chipselect // .chipselect
);
wire master_0_master_translator_avalon_universal_master_0_waitrequest; // master_0_master_translator_avalon_universal_master_0_agent:av_waitrequest -> master_0_master_translator:uav_waitrequest
wire [2:0] master_0_master_translator_avalon_universal_master_0_burstcount; // master_0_master_translator:uav_burstcount -> master_0_master_translator_avalon_universal_master_0_agent:av_burstcount
wire [31:0] master_0_master_translator_avalon_universal_master_0_writedata; // master_0_master_translator:uav_writedata -> master_0_master_translator_avalon_universal_master_0_agent:av_writedata
wire [31:0] master_0_master_translator_avalon_universal_master_0_address; // master_0_master_translator:uav_address -> master_0_master_translator_avalon_universal_master_0_agent:av_address
wire master_0_master_translator_avalon_universal_master_0_lock; // master_0_master_translator:uav_lock -> master_0_master_translator_avalon_universal_master_0_agent:av_lock
wire master_0_master_translator_avalon_universal_master_0_write; // master_0_master_translator:uav_write -> master_0_master_translator_avalon_universal_master_0_agent:av_write
wire master_0_master_translator_avalon_universal_master_0_read; // master_0_master_translator:uav_read -> master_0_master_translator_avalon_universal_master_0_agent:av_read
wire [31:0] master_0_master_translator_avalon_universal_master_0_readdata; // master_0_master_translator_avalon_universal_master_0_agent:av_readdata -> master_0_master_translator:uav_readdata
wire master_0_master_translator_avalon_universal_master_0_debugaccess; // master_0_master_translator:uav_debugaccess -> master_0_master_translator_avalon_universal_master_0_agent:av_debugaccess
wire [3:0] master_0_master_translator_avalon_universal_master_0_byteenable; // master_0_master_translator:uav_byteenable -> master_0_master_translator_avalon_universal_master_0_agent:av_byteenable
wire master_0_master_translator_avalon_universal_master_0_readdatavalid; // master_0_master_translator_avalon_universal_master_0_agent:av_readdatavalid -> master_0_master_translator:uav_readdatavalid
wire vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_waitrequest; // vga_led_0_avalon_slave_0_translator:uav_waitrequest -> vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_waitrequest
wire [1:0] vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_burstcount; // vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_burstcount -> vga_led_0_avalon_slave_0_translator:uav_burstcount
wire [15:0] vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_writedata; // vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_writedata -> vga_led_0_avalon_slave_0_translator:uav_writedata
wire [31:0] vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_address; // vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_address -> vga_led_0_avalon_slave_0_translator:uav_address
wire vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_write; // vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_write -> vga_led_0_avalon_slave_0_translator:uav_write
wire vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_lock; // vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_lock -> vga_led_0_avalon_slave_0_translator:uav_lock
wire vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_read; // vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_read -> vga_led_0_avalon_slave_0_translator:uav_read
wire [15:0] vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_readdata; // vga_led_0_avalon_slave_0_translator:uav_readdata -> vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_readdata
wire vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // vga_led_0_avalon_slave_0_translator:uav_readdatavalid -> vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_readdatavalid
wire vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_debugaccess; // vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_debugaccess -> vga_led_0_avalon_slave_0_translator:uav_debugaccess
wire [1:0] vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_byteenable; // vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_byteenable -> vga_led_0_avalon_slave_0_translator:uav_byteenable
wire vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
wire vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_valid; // vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_source_valid -> vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
wire vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
wire [105:0] vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_data; // vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_source_data -> vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
wire vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_ready; // vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_source_ready
wire vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
wire vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_sink_valid
wire vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
wire [105:0] vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_sink_data
wire vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_sink_ready -> vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
wire vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo:in_valid
wire [17:0] vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo:in_data
wire vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo:in_ready -> vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
wire vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_out_valid; // vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo:out_valid -> vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
wire [17:0] vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_out_data; // vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo:out_data -> vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
wire vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_out_ready; // vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo:out_ready
wire audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_waitrequest; // audio_emulator_0_avalon_slave_0_translator:uav_waitrequest -> audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_waitrequest
wire [1:0] audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_burstcount; // audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_burstcount -> audio_emulator_0_avalon_slave_0_translator:uav_burstcount
wire [15:0] audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_writedata; // audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_writedata -> audio_emulator_0_avalon_slave_0_translator:uav_writedata
wire [31:0] audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_address; // audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_address -> audio_emulator_0_avalon_slave_0_translator:uav_address
wire audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_write; // audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_write -> audio_emulator_0_avalon_slave_0_translator:uav_write
wire audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_lock; // audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_lock -> audio_emulator_0_avalon_slave_0_translator:uav_lock
wire audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_read; // audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_read -> audio_emulator_0_avalon_slave_0_translator:uav_read
wire [15:0] audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_readdata; // audio_emulator_0_avalon_slave_0_translator:uav_readdata -> audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_readdata
wire audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // audio_emulator_0_avalon_slave_0_translator:uav_readdatavalid -> audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_readdatavalid
wire audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_debugaccess; // audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_debugaccess -> audio_emulator_0_avalon_slave_0_translator:uav_debugaccess
wire [1:0] audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_byteenable; // audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_byteenable -> audio_emulator_0_avalon_slave_0_translator:uav_byteenable
wire audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
wire audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_valid; // audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_source_valid -> audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
wire audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
wire [105:0] audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_data; // audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_source_data -> audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
wire audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_ready; // audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_source_ready
wire audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
wire audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_sink_valid
wire audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
wire [105:0] audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_sink_data
wire audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_sink_ready -> audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
wire audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo:in_valid
wire [17:0] audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo:in_data
wire audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo:in_ready -> audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
wire audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_out_valid; // audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo:out_valid -> audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
wire [17:0] audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_out_data; // audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo:out_data -> audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
wire audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_out_ready; // audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo:out_ready
wire hps_0_h2f_lw_axi_master_agent_write_cp_endofpacket; // hps_0_h2f_lw_axi_master_agent:write_cp_endofpacket -> addr_router:sink_endofpacket
wire hps_0_h2f_lw_axi_master_agent_write_cp_valid; // hps_0_h2f_lw_axi_master_agent:write_cp_valid -> addr_router:sink_valid
wire hps_0_h2f_lw_axi_master_agent_write_cp_startofpacket; // hps_0_h2f_lw_axi_master_agent:write_cp_startofpacket -> addr_router:sink_startofpacket
wire [122:0] hps_0_h2f_lw_axi_master_agent_write_cp_data; // hps_0_h2f_lw_axi_master_agent:write_cp_data -> addr_router:sink_data
wire hps_0_h2f_lw_axi_master_agent_write_cp_ready; // addr_router:sink_ready -> hps_0_h2f_lw_axi_master_agent:write_cp_ready
wire hps_0_h2f_lw_axi_master_agent_read_cp_endofpacket; // hps_0_h2f_lw_axi_master_agent:read_cp_endofpacket -> addr_router_001:sink_endofpacket
wire hps_0_h2f_lw_axi_master_agent_read_cp_valid; // hps_0_h2f_lw_axi_master_agent:read_cp_valid -> addr_router_001:sink_valid
wire hps_0_h2f_lw_axi_master_agent_read_cp_startofpacket; // hps_0_h2f_lw_axi_master_agent:read_cp_startofpacket -> addr_router_001:sink_startofpacket
wire [122:0] hps_0_h2f_lw_axi_master_agent_read_cp_data; // hps_0_h2f_lw_axi_master_agent:read_cp_data -> addr_router_001:sink_data
wire hps_0_h2f_lw_axi_master_agent_read_cp_ready; // addr_router_001:sink_ready -> hps_0_h2f_lw_axi_master_agent:read_cp_ready
wire master_0_master_translator_avalon_universal_master_0_agent_cp_endofpacket; // master_0_master_translator_avalon_universal_master_0_agent:cp_endofpacket -> addr_router_002:sink_endofpacket
wire master_0_master_translator_avalon_universal_master_0_agent_cp_valid; // master_0_master_translator_avalon_universal_master_0_agent:cp_valid -> addr_router_002:sink_valid
wire master_0_master_translator_avalon_universal_master_0_agent_cp_startofpacket; // master_0_master_translator_avalon_universal_master_0_agent:cp_startofpacket -> addr_router_002:sink_startofpacket
wire [122:0] master_0_master_translator_avalon_universal_master_0_agent_cp_data; // master_0_master_translator_avalon_universal_master_0_agent:cp_data -> addr_router_002:sink_data
wire master_0_master_translator_avalon_universal_master_0_agent_cp_ready; // addr_router_002:sink_ready -> master_0_master_translator_avalon_universal_master_0_agent:cp_ready
wire vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_endofpacket; // vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router:sink_endofpacket
wire vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_valid; // vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rp_valid -> id_router:sink_valid
wire vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_startofpacket; // vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router:sink_startofpacket
wire [104:0] vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_data; // vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rp_data -> id_router:sink_data
wire vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_ready; // id_router:sink_ready -> vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rp_ready
wire audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_endofpacket; // audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_001:sink_endofpacket
wire audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_valid; // audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_001:sink_valid
wire audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_startofpacket; // audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_001:sink_startofpacket
wire [104:0] audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_data; // audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rp_data -> id_router_001:sink_data
wire audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_001:sink_ready -> audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rp_ready
wire addr_router_src_endofpacket; // addr_router:src_endofpacket -> limiter:cmd_sink_endofpacket
wire addr_router_src_valid; // addr_router:src_valid -> limiter:cmd_sink_valid
wire addr_router_src_startofpacket; // addr_router:src_startofpacket -> limiter:cmd_sink_startofpacket
wire [122:0] addr_router_src_data; // addr_router:src_data -> limiter:cmd_sink_data
wire [2:0] addr_router_src_channel; // addr_router:src_channel -> limiter:cmd_sink_channel
wire addr_router_src_ready; // limiter:cmd_sink_ready -> addr_router:src_ready
wire limiter_cmd_src_endofpacket; // limiter:cmd_src_endofpacket -> cmd_xbar_demux:sink_endofpacket
wire limiter_cmd_src_startofpacket; // limiter:cmd_src_startofpacket -> cmd_xbar_demux:sink_startofpacket
wire [122:0] limiter_cmd_src_data; // limiter:cmd_src_data -> cmd_xbar_demux:sink_data
wire [2:0] limiter_cmd_src_channel; // limiter:cmd_src_channel -> cmd_xbar_demux:sink_channel
wire limiter_cmd_src_ready; // cmd_xbar_demux:sink_ready -> limiter:cmd_src_ready
wire rsp_xbar_mux_src_endofpacket; // rsp_xbar_mux:src_endofpacket -> limiter:rsp_sink_endofpacket
wire rsp_xbar_mux_src_valid; // rsp_xbar_mux:src_valid -> limiter:rsp_sink_valid
wire rsp_xbar_mux_src_startofpacket; // rsp_xbar_mux:src_startofpacket -> limiter:rsp_sink_startofpacket
wire [122:0] rsp_xbar_mux_src_data; // rsp_xbar_mux:src_data -> limiter:rsp_sink_data
wire [2:0] rsp_xbar_mux_src_channel; // rsp_xbar_mux:src_channel -> limiter:rsp_sink_channel
wire rsp_xbar_mux_src_ready; // limiter:rsp_sink_ready -> rsp_xbar_mux:src_ready
wire limiter_rsp_src_endofpacket; // limiter:rsp_src_endofpacket -> hps_0_h2f_lw_axi_master_agent:write_rp_endofpacket
wire limiter_rsp_src_valid; // limiter:rsp_src_valid -> hps_0_h2f_lw_axi_master_agent:write_rp_valid
wire limiter_rsp_src_startofpacket; // limiter:rsp_src_startofpacket -> hps_0_h2f_lw_axi_master_agent:write_rp_startofpacket
wire [122:0] limiter_rsp_src_data; // limiter:rsp_src_data -> hps_0_h2f_lw_axi_master_agent:write_rp_data
wire [2:0] limiter_rsp_src_channel; // limiter:rsp_src_channel -> hps_0_h2f_lw_axi_master_agent:write_rp_channel
wire limiter_rsp_src_ready; // hps_0_h2f_lw_axi_master_agent:write_rp_ready -> limiter:rsp_src_ready
wire addr_router_001_src_endofpacket; // addr_router_001:src_endofpacket -> limiter_001:cmd_sink_endofpacket
wire addr_router_001_src_valid; // addr_router_001:src_valid -> limiter_001:cmd_sink_valid
wire addr_router_001_src_startofpacket; // addr_router_001:src_startofpacket -> limiter_001:cmd_sink_startofpacket
wire [122:0] addr_router_001_src_data; // addr_router_001:src_data -> limiter_001:cmd_sink_data
wire [2:0] addr_router_001_src_channel; // addr_router_001:src_channel -> limiter_001:cmd_sink_channel
wire addr_router_001_src_ready; // limiter_001:cmd_sink_ready -> addr_router_001:src_ready
wire limiter_001_cmd_src_endofpacket; // limiter_001:cmd_src_endofpacket -> cmd_xbar_demux_001:sink_endofpacket
wire limiter_001_cmd_src_startofpacket; // limiter_001:cmd_src_startofpacket -> cmd_xbar_demux_001:sink_startofpacket
wire [122:0] limiter_001_cmd_src_data; // limiter_001:cmd_src_data -> cmd_xbar_demux_001:sink_data
wire [2:0] limiter_001_cmd_src_channel; // limiter_001:cmd_src_channel -> cmd_xbar_demux_001:sink_channel
wire limiter_001_cmd_src_ready; // cmd_xbar_demux_001:sink_ready -> limiter_001:cmd_src_ready
wire rsp_xbar_mux_001_src_endofpacket; // rsp_xbar_mux_001:src_endofpacket -> limiter_001:rsp_sink_endofpacket
wire rsp_xbar_mux_001_src_valid; // rsp_xbar_mux_001:src_valid -> limiter_001:rsp_sink_valid
wire rsp_xbar_mux_001_src_startofpacket; // rsp_xbar_mux_001:src_startofpacket -> limiter_001:rsp_sink_startofpacket
wire [122:0] rsp_xbar_mux_001_src_data; // rsp_xbar_mux_001:src_data -> limiter_001:rsp_sink_data
wire [2:0] rsp_xbar_mux_001_src_channel; // rsp_xbar_mux_001:src_channel -> limiter_001:rsp_sink_channel
wire rsp_xbar_mux_001_src_ready; // limiter_001:rsp_sink_ready -> rsp_xbar_mux_001:src_ready
wire limiter_001_rsp_src_endofpacket; // limiter_001:rsp_src_endofpacket -> hps_0_h2f_lw_axi_master_agent:read_rp_endofpacket
wire limiter_001_rsp_src_valid; // limiter_001:rsp_src_valid -> hps_0_h2f_lw_axi_master_agent:read_rp_valid
wire limiter_001_rsp_src_startofpacket; // limiter_001:rsp_src_startofpacket -> hps_0_h2f_lw_axi_master_agent:read_rp_startofpacket
wire [122:0] limiter_001_rsp_src_data; // limiter_001:rsp_src_data -> hps_0_h2f_lw_axi_master_agent:read_rp_data
wire [2:0] limiter_001_rsp_src_channel; // limiter_001:rsp_src_channel -> hps_0_h2f_lw_axi_master_agent:read_rp_channel
wire limiter_001_rsp_src_ready; // hps_0_h2f_lw_axi_master_agent:read_rp_ready -> limiter_001:rsp_src_ready
wire addr_router_002_src_endofpacket; // addr_router_002:src_endofpacket -> limiter_002:cmd_sink_endofpacket
wire addr_router_002_src_valid; // addr_router_002:src_valid -> limiter_002:cmd_sink_valid
wire addr_router_002_src_startofpacket; // addr_router_002:src_startofpacket -> limiter_002:cmd_sink_startofpacket
wire [122:0] addr_router_002_src_data; // addr_router_002:src_data -> limiter_002:cmd_sink_data
wire [2:0] addr_router_002_src_channel; // addr_router_002:src_channel -> limiter_002:cmd_sink_channel
wire addr_router_002_src_ready; // limiter_002:cmd_sink_ready -> addr_router_002:src_ready
wire limiter_002_cmd_src_endofpacket; // limiter_002:cmd_src_endofpacket -> cmd_xbar_demux_002:sink_endofpacket
wire limiter_002_cmd_src_startofpacket; // limiter_002:cmd_src_startofpacket -> cmd_xbar_demux_002:sink_startofpacket
wire [122:0] limiter_002_cmd_src_data; // limiter_002:cmd_src_data -> cmd_xbar_demux_002:sink_data
wire [2:0] limiter_002_cmd_src_channel; // limiter_002:cmd_src_channel -> cmd_xbar_demux_002:sink_channel
wire limiter_002_cmd_src_ready; // cmd_xbar_demux_002:sink_ready -> limiter_002:cmd_src_ready
wire rsp_xbar_mux_002_src_endofpacket; // rsp_xbar_mux_002:src_endofpacket -> limiter_002:rsp_sink_endofpacket
wire rsp_xbar_mux_002_src_valid; // rsp_xbar_mux_002:src_valid -> limiter_002:rsp_sink_valid
wire rsp_xbar_mux_002_src_startofpacket; // rsp_xbar_mux_002:src_startofpacket -> limiter_002:rsp_sink_startofpacket
wire [122:0] rsp_xbar_mux_002_src_data; // rsp_xbar_mux_002:src_data -> limiter_002:rsp_sink_data
wire [2:0] rsp_xbar_mux_002_src_channel; // rsp_xbar_mux_002:src_channel -> limiter_002:rsp_sink_channel
wire rsp_xbar_mux_002_src_ready; // limiter_002:rsp_sink_ready -> rsp_xbar_mux_002:src_ready
wire limiter_002_rsp_src_endofpacket; // limiter_002:rsp_src_endofpacket -> master_0_master_translator_avalon_universal_master_0_agent:rp_endofpacket
wire limiter_002_rsp_src_valid; // limiter_002:rsp_src_valid -> master_0_master_translator_avalon_universal_master_0_agent:rp_valid
wire limiter_002_rsp_src_startofpacket; // limiter_002:rsp_src_startofpacket -> master_0_master_translator_avalon_universal_master_0_agent:rp_startofpacket
wire [122:0] limiter_002_rsp_src_data; // limiter_002:rsp_src_data -> master_0_master_translator_avalon_universal_master_0_agent:rp_data
wire [2:0] limiter_002_rsp_src_channel; // limiter_002:rsp_src_channel -> master_0_master_translator_avalon_universal_master_0_agent:rp_channel
wire limiter_002_rsp_src_ready; // master_0_master_translator_avalon_universal_master_0_agent:rp_ready -> limiter_002:rsp_src_ready
wire burst_adapter_source0_endofpacket; // burst_adapter:source0_endofpacket -> vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:cp_endofpacket
wire burst_adapter_source0_valid; // burst_adapter:source0_valid -> vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:cp_valid
wire burst_adapter_source0_startofpacket; // burst_adapter:source0_startofpacket -> vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:cp_startofpacket
wire [104:0] burst_adapter_source0_data; // burst_adapter:source0_data -> vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:cp_data
wire burst_adapter_source0_ready; // vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:cp_ready -> burst_adapter:source0_ready
wire [2:0] burst_adapter_source0_channel; // burst_adapter:source0_channel -> vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:cp_channel
wire burst_adapter_001_source0_endofpacket; // burst_adapter_001:source0_endofpacket -> audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:cp_endofpacket
wire burst_adapter_001_source0_valid; // burst_adapter_001:source0_valid -> audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:cp_valid
wire burst_adapter_001_source0_startofpacket; // burst_adapter_001:source0_startofpacket -> audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:cp_startofpacket
wire [104:0] burst_adapter_001_source0_data; // burst_adapter_001:source0_data -> audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:cp_data
wire burst_adapter_001_source0_ready; // audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:cp_ready -> burst_adapter_001:source0_ready
wire [2:0] burst_adapter_001_source0_channel; // burst_adapter_001:source0_channel -> audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:cp_channel
wire cmd_xbar_demux_src0_endofpacket; // cmd_xbar_demux:src0_endofpacket -> cmd_xbar_mux:sink0_endofpacket
wire cmd_xbar_demux_src0_valid; // cmd_xbar_demux:src0_valid -> cmd_xbar_mux:sink0_valid
wire cmd_xbar_demux_src0_startofpacket; // cmd_xbar_demux:src0_startofpacket -> cmd_xbar_mux:sink0_startofpacket
wire [122:0] cmd_xbar_demux_src0_data; // cmd_xbar_demux:src0_data -> cmd_xbar_mux:sink0_data
wire [2:0] cmd_xbar_demux_src0_channel; // cmd_xbar_demux:src0_channel -> cmd_xbar_mux:sink0_channel
wire cmd_xbar_demux_src0_ready; // cmd_xbar_mux:sink0_ready -> cmd_xbar_demux:src0_ready
wire cmd_xbar_demux_src1_endofpacket; // cmd_xbar_demux:src1_endofpacket -> cmd_xbar_mux_001:sink0_endofpacket
wire cmd_xbar_demux_src1_valid; // cmd_xbar_demux:src1_valid -> cmd_xbar_mux_001:sink0_valid
wire cmd_xbar_demux_src1_startofpacket; // cmd_xbar_demux:src1_startofpacket -> cmd_xbar_mux_001:sink0_startofpacket
wire [122:0] cmd_xbar_demux_src1_data; // cmd_xbar_demux:src1_data -> cmd_xbar_mux_001:sink0_data
wire [2:0] cmd_xbar_demux_src1_channel; // cmd_xbar_demux:src1_channel -> cmd_xbar_mux_001:sink0_channel
wire cmd_xbar_demux_src1_ready; // cmd_xbar_mux_001:sink0_ready -> cmd_xbar_demux:src1_ready
wire cmd_xbar_demux_001_src0_endofpacket; // cmd_xbar_demux_001:src0_endofpacket -> cmd_xbar_mux:sink1_endofpacket
wire cmd_xbar_demux_001_src0_valid; // cmd_xbar_demux_001:src0_valid -> cmd_xbar_mux:sink1_valid
wire cmd_xbar_demux_001_src0_startofpacket; // cmd_xbar_demux_001:src0_startofpacket -> cmd_xbar_mux:sink1_startofpacket
wire [122:0] cmd_xbar_demux_001_src0_data; // cmd_xbar_demux_001:src0_data -> cmd_xbar_mux:sink1_data
wire [2:0] cmd_xbar_demux_001_src0_channel; // cmd_xbar_demux_001:src0_channel -> cmd_xbar_mux:sink1_channel
wire cmd_xbar_demux_001_src0_ready; // cmd_xbar_mux:sink1_ready -> cmd_xbar_demux_001:src0_ready
wire cmd_xbar_demux_001_src1_endofpacket; // cmd_xbar_demux_001:src1_endofpacket -> cmd_xbar_mux_001:sink1_endofpacket
wire cmd_xbar_demux_001_src1_valid; // cmd_xbar_demux_001:src1_valid -> cmd_xbar_mux_001:sink1_valid
wire cmd_xbar_demux_001_src1_startofpacket; // cmd_xbar_demux_001:src1_startofpacket -> cmd_xbar_mux_001:sink1_startofpacket
wire [122:0] cmd_xbar_demux_001_src1_data; // cmd_xbar_demux_001:src1_data -> cmd_xbar_mux_001:sink1_data
wire [2:0] cmd_xbar_demux_001_src1_channel; // cmd_xbar_demux_001:src1_channel -> cmd_xbar_mux_001:sink1_channel
wire cmd_xbar_demux_001_src1_ready; // cmd_xbar_mux_001:sink1_ready -> cmd_xbar_demux_001:src1_ready
wire cmd_xbar_demux_002_src0_endofpacket; // cmd_xbar_demux_002:src0_endofpacket -> cmd_xbar_mux:sink2_endofpacket
wire cmd_xbar_demux_002_src0_valid; // cmd_xbar_demux_002:src0_valid -> cmd_xbar_mux:sink2_valid
wire cmd_xbar_demux_002_src0_startofpacket; // cmd_xbar_demux_002:src0_startofpacket -> cmd_xbar_mux:sink2_startofpacket
wire [122:0] cmd_xbar_demux_002_src0_data; // cmd_xbar_demux_002:src0_data -> cmd_xbar_mux:sink2_data
wire [2:0] cmd_xbar_demux_002_src0_channel; // cmd_xbar_demux_002:src0_channel -> cmd_xbar_mux:sink2_channel
wire cmd_xbar_demux_002_src0_ready; // cmd_xbar_mux:sink2_ready -> cmd_xbar_demux_002:src0_ready
wire cmd_xbar_demux_002_src1_endofpacket; // cmd_xbar_demux_002:src1_endofpacket -> cmd_xbar_mux_001:sink2_endofpacket
wire cmd_xbar_demux_002_src1_valid; // cmd_xbar_demux_002:src1_valid -> cmd_xbar_mux_001:sink2_valid
wire cmd_xbar_demux_002_src1_startofpacket; // cmd_xbar_demux_002:src1_startofpacket -> cmd_xbar_mux_001:sink2_startofpacket
wire [122:0] cmd_xbar_demux_002_src1_data; // cmd_xbar_demux_002:src1_data -> cmd_xbar_mux_001:sink2_data
wire [2:0] cmd_xbar_demux_002_src1_channel; // cmd_xbar_demux_002:src1_channel -> cmd_xbar_mux_001:sink2_channel
wire cmd_xbar_demux_002_src1_ready; // cmd_xbar_mux_001:sink2_ready -> cmd_xbar_demux_002:src1_ready
wire rsp_xbar_demux_src0_endofpacket; // rsp_xbar_demux:src0_endofpacket -> rsp_xbar_mux:sink0_endofpacket
wire rsp_xbar_demux_src0_valid; // rsp_xbar_demux:src0_valid -> rsp_xbar_mux:sink0_valid
wire rsp_xbar_demux_src0_startofpacket; // rsp_xbar_demux:src0_startofpacket -> rsp_xbar_mux:sink0_startofpacket
wire [122:0] rsp_xbar_demux_src0_data; // rsp_xbar_demux:src0_data -> rsp_xbar_mux:sink0_data
wire [2:0] rsp_xbar_demux_src0_channel; // rsp_xbar_demux:src0_channel -> rsp_xbar_mux:sink0_channel
wire rsp_xbar_demux_src0_ready; // rsp_xbar_mux:sink0_ready -> rsp_xbar_demux:src0_ready
wire rsp_xbar_demux_src1_endofpacket; // rsp_xbar_demux:src1_endofpacket -> rsp_xbar_mux_001:sink0_endofpacket
wire rsp_xbar_demux_src1_valid; // rsp_xbar_demux:src1_valid -> rsp_xbar_mux_001:sink0_valid
wire rsp_xbar_demux_src1_startofpacket; // rsp_xbar_demux:src1_startofpacket -> rsp_xbar_mux_001:sink0_startofpacket
wire [122:0] rsp_xbar_demux_src1_data; // rsp_xbar_demux:src1_data -> rsp_xbar_mux_001:sink0_data
wire [2:0] rsp_xbar_demux_src1_channel; // rsp_xbar_demux:src1_channel -> rsp_xbar_mux_001:sink0_channel
wire rsp_xbar_demux_src1_ready; // rsp_xbar_mux_001:sink0_ready -> rsp_xbar_demux:src1_ready
wire rsp_xbar_demux_src2_endofpacket; // rsp_xbar_demux:src2_endofpacket -> rsp_xbar_mux_002:sink0_endofpacket
wire rsp_xbar_demux_src2_valid; // rsp_xbar_demux:src2_valid -> rsp_xbar_mux_002:sink0_valid
wire rsp_xbar_demux_src2_startofpacket; // rsp_xbar_demux:src2_startofpacket -> rsp_xbar_mux_002:sink0_startofpacket
wire [122:0] rsp_xbar_demux_src2_data; // rsp_xbar_demux:src2_data -> rsp_xbar_mux_002:sink0_data
wire [2:0] rsp_xbar_demux_src2_channel; // rsp_xbar_demux:src2_channel -> rsp_xbar_mux_002:sink0_channel
wire rsp_xbar_demux_src2_ready; // rsp_xbar_mux_002:sink0_ready -> rsp_xbar_demux:src2_ready
wire rsp_xbar_demux_001_src0_endofpacket; // rsp_xbar_demux_001:src0_endofpacket -> rsp_xbar_mux:sink1_endofpacket
wire rsp_xbar_demux_001_src0_valid; // rsp_xbar_demux_001:src0_valid -> rsp_xbar_mux:sink1_valid
wire rsp_xbar_demux_001_src0_startofpacket; // rsp_xbar_demux_001:src0_startofpacket -> rsp_xbar_mux:sink1_startofpacket
wire [122:0] rsp_xbar_demux_001_src0_data; // rsp_xbar_demux_001:src0_data -> rsp_xbar_mux:sink1_data
wire [2:0] rsp_xbar_demux_001_src0_channel; // rsp_xbar_demux_001:src0_channel -> rsp_xbar_mux:sink1_channel
wire rsp_xbar_demux_001_src0_ready; // rsp_xbar_mux:sink1_ready -> rsp_xbar_demux_001:src0_ready
wire rsp_xbar_demux_001_src1_endofpacket; // rsp_xbar_demux_001:src1_endofpacket -> rsp_xbar_mux_001:sink1_endofpacket
wire rsp_xbar_demux_001_src1_valid; // rsp_xbar_demux_001:src1_valid -> rsp_xbar_mux_001:sink1_valid
wire rsp_xbar_demux_001_src1_startofpacket; // rsp_xbar_demux_001:src1_startofpacket -> rsp_xbar_mux_001:sink1_startofpacket
wire [122:0] rsp_xbar_demux_001_src1_data; // rsp_xbar_demux_001:src1_data -> rsp_xbar_mux_001:sink1_data
wire [2:0] rsp_xbar_demux_001_src1_channel; // rsp_xbar_demux_001:src1_channel -> rsp_xbar_mux_001:sink1_channel
wire rsp_xbar_demux_001_src1_ready; // rsp_xbar_mux_001:sink1_ready -> rsp_xbar_demux_001:src1_ready
wire rsp_xbar_demux_001_src2_endofpacket; // rsp_xbar_demux_001:src2_endofpacket -> rsp_xbar_mux_002:sink1_endofpacket
wire rsp_xbar_demux_001_src2_valid; // rsp_xbar_demux_001:src2_valid -> rsp_xbar_mux_002:sink1_valid
wire rsp_xbar_demux_001_src2_startofpacket; // rsp_xbar_demux_001:src2_startofpacket -> rsp_xbar_mux_002:sink1_startofpacket
wire [122:0] rsp_xbar_demux_001_src2_data; // rsp_xbar_demux_001:src2_data -> rsp_xbar_mux_002:sink1_data
wire [2:0] rsp_xbar_demux_001_src2_channel; // rsp_xbar_demux_001:src2_channel -> rsp_xbar_mux_002:sink1_channel
wire rsp_xbar_demux_001_src2_ready; // rsp_xbar_mux_002:sink1_ready -> rsp_xbar_demux_001:src2_ready
wire id_router_src_endofpacket; // id_router:src_endofpacket -> width_adapter:in_endofpacket
wire id_router_src_valid; // id_router:src_valid -> width_adapter:in_valid
wire id_router_src_startofpacket; // id_router:src_startofpacket -> width_adapter:in_startofpacket
wire [104:0] id_router_src_data; // id_router:src_data -> width_adapter:in_data
wire [2:0] id_router_src_channel; // id_router:src_channel -> width_adapter:in_channel
wire id_router_src_ready; // width_adapter:in_ready -> id_router:src_ready
wire width_adapter_src_endofpacket; // width_adapter:out_endofpacket -> rsp_xbar_demux:sink_endofpacket
wire width_adapter_src_valid; // width_adapter:out_valid -> rsp_xbar_demux:sink_valid
wire width_adapter_src_startofpacket; // width_adapter:out_startofpacket -> rsp_xbar_demux:sink_startofpacket
wire [122:0] width_adapter_src_data; // width_adapter:out_data -> rsp_xbar_demux:sink_data
wire width_adapter_src_ready; // rsp_xbar_demux:sink_ready -> width_adapter:out_ready
wire [2:0] width_adapter_src_channel; // width_adapter:out_channel -> rsp_xbar_demux:sink_channel
wire id_router_001_src_endofpacket; // id_router_001:src_endofpacket -> width_adapter_001:in_endofpacket
wire id_router_001_src_valid; // id_router_001:src_valid -> width_adapter_001:in_valid
wire id_router_001_src_startofpacket; // id_router_001:src_startofpacket -> width_adapter_001:in_startofpacket
wire [104:0] id_router_001_src_data; // id_router_001:src_data -> width_adapter_001:in_data
wire [2:0] id_router_001_src_channel; // id_router_001:src_channel -> width_adapter_001:in_channel
wire id_router_001_src_ready; // width_adapter_001:in_ready -> id_router_001:src_ready
wire width_adapter_001_src_endofpacket; // width_adapter_001:out_endofpacket -> rsp_xbar_demux_001:sink_endofpacket
wire width_adapter_001_src_valid; // width_adapter_001:out_valid -> rsp_xbar_demux_001:sink_valid
wire width_adapter_001_src_startofpacket; // width_adapter_001:out_startofpacket -> rsp_xbar_demux_001:sink_startofpacket
wire [122:0] width_adapter_001_src_data; // width_adapter_001:out_data -> rsp_xbar_demux_001:sink_data
wire width_adapter_001_src_ready; // rsp_xbar_demux_001:sink_ready -> width_adapter_001:out_ready
wire [2:0] width_adapter_001_src_channel; // width_adapter_001:out_channel -> rsp_xbar_demux_001:sink_channel
wire cmd_xbar_mux_src_endofpacket; // cmd_xbar_mux:src_endofpacket -> width_adapter_002:in_endofpacket
wire cmd_xbar_mux_src_valid; // cmd_xbar_mux:src_valid -> width_adapter_002:in_valid
wire cmd_xbar_mux_src_startofpacket; // cmd_xbar_mux:src_startofpacket -> width_adapter_002:in_startofpacket
wire [122:0] cmd_xbar_mux_src_data; // cmd_xbar_mux:src_data -> width_adapter_002:in_data
wire [2:0] cmd_xbar_mux_src_channel; // cmd_xbar_mux:src_channel -> width_adapter_002:in_channel
wire cmd_xbar_mux_src_ready; // width_adapter_002:in_ready -> cmd_xbar_mux:src_ready
wire width_adapter_002_src_endofpacket; // width_adapter_002:out_endofpacket -> burst_adapter:sink0_endofpacket
wire width_adapter_002_src_valid; // width_adapter_002:out_valid -> burst_adapter:sink0_valid
wire width_adapter_002_src_startofpacket; // width_adapter_002:out_startofpacket -> burst_adapter:sink0_startofpacket
wire [104:0] width_adapter_002_src_data; // width_adapter_002:out_data -> burst_adapter:sink0_data
wire width_adapter_002_src_ready; // burst_adapter:sink0_ready -> width_adapter_002:out_ready
wire [2:0] width_adapter_002_src_channel; // width_adapter_002:out_channel -> burst_adapter:sink0_channel
wire cmd_xbar_mux_001_src_endofpacket; // cmd_xbar_mux_001:src_endofpacket -> width_adapter_003:in_endofpacket
wire cmd_xbar_mux_001_src_valid; // cmd_xbar_mux_001:src_valid -> width_adapter_003:in_valid
wire cmd_xbar_mux_001_src_startofpacket; // cmd_xbar_mux_001:src_startofpacket -> width_adapter_003:in_startofpacket
wire [122:0] cmd_xbar_mux_001_src_data; // cmd_xbar_mux_001:src_data -> width_adapter_003:in_data
wire [2:0] cmd_xbar_mux_001_src_channel; // cmd_xbar_mux_001:src_channel -> width_adapter_003:in_channel
wire cmd_xbar_mux_001_src_ready; // width_adapter_003:in_ready -> cmd_xbar_mux_001:src_ready
wire width_adapter_003_src_endofpacket; // width_adapter_003:out_endofpacket -> burst_adapter_001:sink0_endofpacket
wire width_adapter_003_src_valid; // width_adapter_003:out_valid -> burst_adapter_001:sink0_valid
wire width_adapter_003_src_startofpacket; // width_adapter_003:out_startofpacket -> burst_adapter_001:sink0_startofpacket
wire [104:0] width_adapter_003_src_data; // width_adapter_003:out_data -> burst_adapter_001:sink0_data
wire width_adapter_003_src_ready; // burst_adapter_001:sink0_ready -> width_adapter_003:out_ready
wire [2:0] width_adapter_003_src_channel; // width_adapter_003:out_channel -> burst_adapter_001:sink0_channel
wire [2:0] limiter_cmd_valid_data; // limiter:cmd_src_valid -> cmd_xbar_demux:sink_valid
wire [2:0] limiter_001_cmd_valid_data; // limiter_001:cmd_src_valid -> cmd_xbar_demux_001:sink_valid
wire [2:0] limiter_002_cmd_valid_data; // limiter_002:cmd_src_valid -> cmd_xbar_demux_002:sink_valid
altera_merlin_master_translator #(
.AV_ADDRESS_W (32),
.AV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (32),
.UAV_BURSTCOUNT_W (3),
.USE_READ (1),
.USE_WRITE (1),
.USE_BEGINBURSTTRANSFER (0),
.USE_BEGINTRANSFER (0),
.USE_CHIPSELECT (0),
.USE_BURSTCOUNT (0),
.USE_READDATAVALID (1),
.USE_WAITREQUEST (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (1),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_LINEWRAPBURSTS (0),
.AV_REGISTERINCOMINGSIGNALS (0)
) master_0_master_translator (
.clk (clk_0_clk_clk), // clk.clk
.reset (vga_led_0_reset_sink_reset_bridge_in_reset_reset), // reset.reset
.uav_address (master_0_master_translator_avalon_universal_master_0_address), // avalon_universal_master_0.address
.uav_burstcount (master_0_master_translator_avalon_universal_master_0_burstcount), // .burstcount
.uav_read (master_0_master_translator_avalon_universal_master_0_read), // .read
.uav_write (master_0_master_translator_avalon_universal_master_0_write), // .write
.uav_waitrequest (master_0_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.uav_readdatavalid (master_0_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.uav_byteenable (master_0_master_translator_avalon_universal_master_0_byteenable), // .byteenable
.uav_readdata (master_0_master_translator_avalon_universal_master_0_readdata), // .readdata
.uav_writedata (master_0_master_translator_avalon_universal_master_0_writedata), // .writedata
.uav_lock (master_0_master_translator_avalon_universal_master_0_lock), // .lock
.uav_debugaccess (master_0_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_address (master_0_master_address), // avalon_anti_master_0.address
.av_waitrequest (master_0_master_waitrequest), // .waitrequest
.av_byteenable (master_0_master_byteenable), // .byteenable
.av_read (master_0_master_read), // .read
.av_readdata (master_0_master_readdata), // .readdata
.av_readdatavalid (master_0_master_readdatavalid), // .readdatavalid
.av_write (master_0_master_write), // .write
.av_writedata (master_0_master_writedata), // .writedata
.av_burstcount (1'b1), // (terminated)
.av_beginbursttransfer (1'b0), // (terminated)
.av_begintransfer (1'b0), // (terminated)
.av_chipselect (1'b0), // (terminated)
.av_lock (1'b0), // (terminated)
.av_debugaccess (1'b0), // (terminated)
.uav_clken (), // (terminated)
.av_clken (1'b1), // (terminated)
.uav_response (2'b00), // (terminated)
.av_response (), // (terminated)
.uav_writeresponserequest (), // (terminated)
.uav_writeresponsevalid (1'b0), // (terminated)
.av_writeresponserequest (1'b0), // (terminated)
.av_writeresponsevalid () // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (4),
.AV_DATA_W (16),
.UAV_DATA_W (16),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (2),
.UAV_BYTEENABLE_W (2),
.UAV_ADDRESS_W (32),
.UAV_BURSTCOUNT_W (2),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (2),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) vga_led_0_avalon_slave_0_translator (
.clk (clk_0_clk_clk), // clk.clk
.reset (vga_led_0_reset_sink_reset_bridge_in_reset_reset), // reset.reset
.uav_address (vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
.uav_read (vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_read), // .read
.uav_write (vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_write), // .write
.uav_waitrequest (vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
.uav_readdata (vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
.uav_writedata (vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
.uav_lock (vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
.uav_debugaccess (vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
.av_address (vga_led_0_avalon_slave_0_address), // avalon_anti_slave_0.address
.av_write (vga_led_0_avalon_slave_0_write), // .write
.av_writedata (vga_led_0_avalon_slave_0_writedata), // .writedata
.av_chipselect (vga_led_0_avalon_slave_0_chipselect), // .chipselect
.av_read (), // (terminated)
.av_readdata (16'b1101111010101101), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponserequest (1'b0), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponserequest (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (1),
.AV_DATA_W (16),
.UAV_DATA_W (16),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (2),
.UAV_BYTEENABLE_W (2),
.UAV_ADDRESS_W (32),
.UAV_BURSTCOUNT_W (2),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (2),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) audio_emulator_0_avalon_slave_0_translator (
.clk (clk_0_clk_clk), // clk.clk
.reset (vga_led_0_reset_sink_reset_bridge_in_reset_reset), // reset.reset
.uav_address (audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
.uav_read (audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_read), // .read
.uav_write (audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_write), // .write
.uav_waitrequest (audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
.uav_readdata (audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
.uav_writedata (audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
.uav_lock (audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
.uav_debugaccess (audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
.av_address (audio_emulator_0_avalon_slave_0_address), // avalon_anti_slave_0.address
.av_write (audio_emulator_0_avalon_slave_0_write), // .write
.av_writedata (audio_emulator_0_avalon_slave_0_writedata), // .writedata
.av_chipselect (audio_emulator_0_avalon_slave_0_chipselect), // .chipselect
.av_read (), // (terminated)
.av_readdata (16'b1101111010101101), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponserequest (1'b0), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponserequest (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_axi_master_ni #(
.ID_WIDTH (12),
.ADDR_WIDTH (21),
.RDATA_WIDTH (32),
.WDATA_WIDTH (32),
.ADDR_USER_WIDTH (1),
.DATA_USER_WIDTH (1),
.AXI_BURST_LENGTH_WIDTH (4),
.AXI_LOCK_WIDTH (2),
.AXI_VERSION ("AXI3"),
.WRITE_ISSUING_CAPABILITY (8),
.READ_ISSUING_CAPABILITY (8),
.PKT_BEGIN_BURST (95),
.PKT_CACHE_H (117),
.PKT_CACHE_L (114),
.PKT_ADDR_SIDEBAND_H (93),
.PKT_ADDR_SIDEBAND_L (93),
.PKT_PROTECTION_H (113),
.PKT_PROTECTION_L (111),
.PKT_BURST_SIZE_H (90),
.PKT_BURST_SIZE_L (88),
.PKT_BURST_TYPE_H (92),
.PKT_BURST_TYPE_L (91),
.PKT_RESPONSE_STATUS_L (118),
.PKT_RESPONSE_STATUS_H (119),
.PKT_BURSTWRAP_H (87),
.PKT_BURSTWRAP_L (81),
.PKT_BYTE_CNT_H (80),
.PKT_BYTE_CNT_L (74),
.PKT_ADDR_H (67),
.PKT_ADDR_L (36),
.PKT_TRANS_EXCLUSIVE (73),
.PKT_TRANS_LOCK (72),
.PKT_TRANS_COMPRESSED_READ (68),
.PKT_TRANS_POSTED (69),
.PKT_TRANS_WRITE (70),
.PKT_TRANS_READ (71),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (97),
.PKT_SRC_ID_L (97),
.PKT_DEST_ID_H (98),
.PKT_DEST_ID_L (98),
.PKT_THREAD_ID_H (110),
.PKT_THREAD_ID_L (99),
.PKT_QOS_L (96),
.PKT_QOS_H (96),
.PKT_ORI_BURST_SIZE_L (120),
.PKT_ORI_BURST_SIZE_H (122),
.PKT_DATA_SIDEBAND_H (94),
.PKT_DATA_SIDEBAND_L (94),
.ST_DATA_W (123),
.ST_CHANNEL_W (3),
.ID (0)
) hps_0_h2f_lw_axi_master_agent (
.aclk (clk_0_clk_clk), // clk.clk
.aresetn (~hps_0_h2f_lw_axi_master_agent_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset_n
.write_cp_valid (hps_0_h2f_lw_axi_master_agent_write_cp_valid), // write_cp.valid
.write_cp_data (hps_0_h2f_lw_axi_master_agent_write_cp_data), // .data
.write_cp_startofpacket (hps_0_h2f_lw_axi_master_agent_write_cp_startofpacket), // .startofpacket
.write_cp_endofpacket (hps_0_h2f_lw_axi_master_agent_write_cp_endofpacket), // .endofpacket
.write_cp_ready (hps_0_h2f_lw_axi_master_agent_write_cp_ready), // .ready
.write_rp_valid (limiter_rsp_src_valid), // write_rp.valid
.write_rp_data (limiter_rsp_src_data), // .data
.write_rp_channel (limiter_rsp_src_channel), // .channel
.write_rp_startofpacket (limiter_rsp_src_startofpacket), // .startofpacket
.write_rp_endofpacket (limiter_rsp_src_endofpacket), // .endofpacket
.write_rp_ready (limiter_rsp_src_ready), // .ready
.read_cp_valid (hps_0_h2f_lw_axi_master_agent_read_cp_valid), // read_cp.valid
.read_cp_data (hps_0_h2f_lw_axi_master_agent_read_cp_data), // .data
.read_cp_startofpacket (hps_0_h2f_lw_axi_master_agent_read_cp_startofpacket), // .startofpacket
.read_cp_endofpacket (hps_0_h2f_lw_axi_master_agent_read_cp_endofpacket), // .endofpacket
.read_cp_ready (hps_0_h2f_lw_axi_master_agent_read_cp_ready), // .ready
.read_rp_valid (limiter_001_rsp_src_valid), // read_rp.valid
.read_rp_data (limiter_001_rsp_src_data), // .data
.read_rp_channel (limiter_001_rsp_src_channel), // .channel
.read_rp_startofpacket (limiter_001_rsp_src_startofpacket), // .startofpacket
.read_rp_endofpacket (limiter_001_rsp_src_endofpacket), // .endofpacket
.read_rp_ready (limiter_001_rsp_src_ready), // .ready
.awid (hps_0_h2f_lw_axi_master_awid), // altera_axi_slave.awid
.awaddr (hps_0_h2f_lw_axi_master_awaddr), // .awaddr
.awlen (hps_0_h2f_lw_axi_master_awlen), // .awlen
.awsize (hps_0_h2f_lw_axi_master_awsize), // .awsize
.awburst (hps_0_h2f_lw_axi_master_awburst), // .awburst
.awlock (hps_0_h2f_lw_axi_master_awlock), // .awlock
.awcache (hps_0_h2f_lw_axi_master_awcache), // .awcache
.awprot (hps_0_h2f_lw_axi_master_awprot), // .awprot
.awvalid (hps_0_h2f_lw_axi_master_awvalid), // .awvalid
.awready (hps_0_h2f_lw_axi_master_awready), // .awready
.wid (hps_0_h2f_lw_axi_master_wid), // .wid
.wdata (hps_0_h2f_lw_axi_master_wdata), // .wdata
.wstrb (hps_0_h2f_lw_axi_master_wstrb), // .wstrb
.wlast (hps_0_h2f_lw_axi_master_wlast), // .wlast
.wvalid (hps_0_h2f_lw_axi_master_wvalid), // .wvalid
.wready (hps_0_h2f_lw_axi_master_wready), // .wready
.bid (hps_0_h2f_lw_axi_master_bid), // .bid
.bresp (hps_0_h2f_lw_axi_master_bresp), // .bresp
.bvalid (hps_0_h2f_lw_axi_master_bvalid), // .bvalid
.bready (hps_0_h2f_lw_axi_master_bready), // .bready
.arid (hps_0_h2f_lw_axi_master_arid), // .arid
.araddr (hps_0_h2f_lw_axi_master_araddr), // .araddr
.arlen (hps_0_h2f_lw_axi_master_arlen), // .arlen
.arsize (hps_0_h2f_lw_axi_master_arsize), // .arsize
.arburst (hps_0_h2f_lw_axi_master_arburst), // .arburst
.arlock (hps_0_h2f_lw_axi_master_arlock), // .arlock
.arcache (hps_0_h2f_lw_axi_master_arcache), // .arcache
.arprot (hps_0_h2f_lw_axi_master_arprot), // .arprot
.arvalid (hps_0_h2f_lw_axi_master_arvalid), // .arvalid
.arready (hps_0_h2f_lw_axi_master_arready), // .arready
.rid (hps_0_h2f_lw_axi_master_rid), // .rid
.rdata (hps_0_h2f_lw_axi_master_rdata), // .rdata
.rresp (hps_0_h2f_lw_axi_master_rresp), // .rresp
.rlast (hps_0_h2f_lw_axi_master_rlast), // .rlast
.rvalid (hps_0_h2f_lw_axi_master_rvalid), // .rvalid
.rready (hps_0_h2f_lw_axi_master_rready), // .rready
.awuser (1'b0), // (terminated)
.aruser (1'b0), // (terminated)
.awqos (4'b0000), // (terminated)
.arqos (4'b0000), // (terminated)
.awregion (4'b0000), // (terminated)
.arregion (4'b0000), // (terminated)
.wuser (8'b00000000), // (terminated)
.ruser (), // (terminated)
.buser () // (terminated)
);
altera_merlin_master_agent #(
.PKT_PROTECTION_H (113),
.PKT_PROTECTION_L (111),
.PKT_BEGIN_BURST (95),
.PKT_BURSTWRAP_H (87),
.PKT_BURSTWRAP_L (81),
.PKT_BURST_SIZE_H (90),
.PKT_BURST_SIZE_L (88),
.PKT_BURST_TYPE_H (92),
.PKT_BURST_TYPE_L (91),
.PKT_BYTE_CNT_H (80),
.PKT_BYTE_CNT_L (74),
.PKT_ADDR_H (67),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (68),
.PKT_TRANS_POSTED (69),
.PKT_TRANS_WRITE (70),
.PKT_TRANS_READ (71),
.PKT_TRANS_LOCK (72),
.PKT_TRANS_EXCLUSIVE (73),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (97),
.PKT_SRC_ID_L (97),
.PKT_DEST_ID_H (98),
.PKT_DEST_ID_L (98),
.PKT_THREAD_ID_H (110),
.PKT_THREAD_ID_L (99),
.PKT_CACHE_H (117),
.PKT_CACHE_L (114),
.PKT_DATA_SIDEBAND_H (94),
.PKT_DATA_SIDEBAND_L (94),
.PKT_QOS_H (96),
.PKT_QOS_L (96),
.PKT_ADDR_SIDEBAND_H (93),
.PKT_ADDR_SIDEBAND_L (93),
.PKT_RESPONSE_STATUS_H (119),
.PKT_RESPONSE_STATUS_L (118),
.PKT_ORI_BURST_SIZE_L (120),
.PKT_ORI_BURST_SIZE_H (122),
.ST_DATA_W (123),
.ST_CHANNEL_W (3),
.AV_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_RSP (0),
.ID (1),
.BURSTWRAP_VALUE (127),
.CACHE_VALUE (0),
.SECURE_ACCESS_BIT (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) master_0_master_translator_avalon_universal_master_0_agent (
.clk (clk_0_clk_clk), // clk.clk
.reset (vga_led_0_reset_sink_reset_bridge_in_reset_reset), // clk_reset.reset
.av_address (master_0_master_translator_avalon_universal_master_0_address), // av.address
.av_write (master_0_master_translator_avalon_universal_master_0_write), // .write
.av_read (master_0_master_translator_avalon_universal_master_0_read), // .read
.av_writedata (master_0_master_translator_avalon_universal_master_0_writedata), // .writedata
.av_readdata (master_0_master_translator_avalon_universal_master_0_readdata), // .readdata
.av_waitrequest (master_0_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.av_readdatavalid (master_0_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.av_byteenable (master_0_master_translator_avalon_universal_master_0_byteenable), // .byteenable
.av_burstcount (master_0_master_translator_avalon_universal_master_0_burstcount), // .burstcount
.av_debugaccess (master_0_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_lock (master_0_master_translator_avalon_universal_master_0_lock), // .lock
.cp_valid (master_0_master_translator_avalon_universal_master_0_agent_cp_valid), // cp.valid
.cp_data (master_0_master_translator_avalon_universal_master_0_agent_cp_data), // .data
.cp_startofpacket (master_0_master_translator_avalon_universal_master_0_agent_cp_startofpacket), // .startofpacket
.cp_endofpacket (master_0_master_translator_avalon_universal_master_0_agent_cp_endofpacket), // .endofpacket
.cp_ready (master_0_master_translator_avalon_universal_master_0_agent_cp_ready), // .ready
.rp_valid (limiter_002_rsp_src_valid), // rp.valid
.rp_data (limiter_002_rsp_src_data), // .data
.rp_channel (limiter_002_rsp_src_channel), // .channel
.rp_startofpacket (limiter_002_rsp_src_startofpacket), // .startofpacket
.rp_endofpacket (limiter_002_rsp_src_endofpacket), // .endofpacket
.rp_ready (limiter_002_rsp_src_ready), // .ready
.av_response (), // (terminated)
.av_writeresponserequest (1'b0), // (terminated)
.av_writeresponsevalid () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_DATA_H (15),
.PKT_DATA_L (0),
.PKT_BEGIN_BURST (77),
.PKT_SYMBOL_W (8),
.PKT_BYTEEN_H (17),
.PKT_BYTEEN_L (16),
.PKT_ADDR_H (49),
.PKT_ADDR_L (18),
.PKT_TRANS_COMPRESSED_READ (50),
.PKT_TRANS_POSTED (51),
.PKT_TRANS_WRITE (52),
.PKT_TRANS_READ (53),
.PKT_TRANS_LOCK (54),
.PKT_SRC_ID_H (79),
.PKT_SRC_ID_L (79),
.PKT_DEST_ID_H (80),
.PKT_DEST_ID_L (80),
.PKT_BURSTWRAP_H (69),
.PKT_BURSTWRAP_L (63),
.PKT_BYTE_CNT_H (62),
.PKT_BYTE_CNT_L (56),
.PKT_PROTECTION_H (95),
.PKT_PROTECTION_L (93),
.PKT_RESPONSE_STATUS_H (101),
.PKT_RESPONSE_STATUS_L (100),
.PKT_BURST_SIZE_H (72),
.PKT_BURST_SIZE_L (70),
.PKT_ORI_BURST_SIZE_L (102),
.PKT_ORI_BURST_SIZE_H (104),
.ST_CHANNEL_W (3),
.ST_DATA_W (105),
.AVS_BURSTCOUNT_W (2),
.SUPPRESS_0_BYTEEN_CMD (1),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent (
.clk (clk_0_clk_clk), // clk.clk
.reset (vga_led_0_reset_sink_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_address), // m0.address
.m0_burstcount (vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
.m0_byteenable (vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
.m0_debugaccess (vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
.m0_lock (vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
.m0_readdata (vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
.m0_readdatavalid (vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
.m0_read (vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_read), // .read
.m0_waitrequest (vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
.m0_writedata (vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
.m0_write (vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_write), // .write
.rp_endofpacket (vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_ready), // .ready
.rp_valid (vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
.rp_data (vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_data), // .data
.rp_startofpacket (vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
.cp_ready (burst_adapter_source0_ready), // cp.ready
.cp_valid (burst_adapter_source0_valid), // .valid
.cp_data (burst_adapter_source0_data), // .data
.cp_startofpacket (burst_adapter_source0_startofpacket), // .startofpacket
.cp_endofpacket (burst_adapter_source0_endofpacket), // .endofpacket
.cp_channel (burst_adapter_source0_channel), // .channel
.rf_sink_ready (vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // .data
.rf_source_ready (vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
.rf_source_startofpacket (vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_out_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_out_valid), // .valid
.rdata_fifo_sink_data (vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_out_data), // .data
.rdata_fifo_src_ready (vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponserequest (), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (106),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo (
.clk (clk_0_clk_clk), // clk.clk
.reset (vga_led_0_reset_sink_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_data), // in.data
.in_valid (vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
.in_ready (vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_ready), // .ready
.in_startofpacket (vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
.out_data (vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // out.data
.out_valid (vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
.out_ready (vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (18),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (0),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (0),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo (
.clk (clk_0_clk_clk), // clk.clk
.reset (vga_led_0_reset_sink_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // in.data
.in_valid (vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
.in_ready (vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // .ready
.out_data (vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_out_data), // out.data
.out_valid (vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_out_valid), // .valid
.out_ready (vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_out_ready), // .ready
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_startofpacket (1'b0), // (terminated)
.in_endofpacket (1'b0), // (terminated)
.out_startofpacket (), // (terminated)
.out_endofpacket (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_DATA_H (15),
.PKT_DATA_L (0),
.PKT_BEGIN_BURST (77),
.PKT_SYMBOL_W (8),
.PKT_BYTEEN_H (17),
.PKT_BYTEEN_L (16),
.PKT_ADDR_H (49),
.PKT_ADDR_L (18),
.PKT_TRANS_COMPRESSED_READ (50),
.PKT_TRANS_POSTED (51),
.PKT_TRANS_WRITE (52),
.PKT_TRANS_READ (53),
.PKT_TRANS_LOCK (54),
.PKT_SRC_ID_H (79),
.PKT_SRC_ID_L (79),
.PKT_DEST_ID_H (80),
.PKT_DEST_ID_L (80),
.PKT_BURSTWRAP_H (69),
.PKT_BURSTWRAP_L (63),
.PKT_BYTE_CNT_H (62),
.PKT_BYTE_CNT_L (56),
.PKT_PROTECTION_H (95),
.PKT_PROTECTION_L (93),
.PKT_RESPONSE_STATUS_H (101),
.PKT_RESPONSE_STATUS_L (100),
.PKT_BURST_SIZE_H (72),
.PKT_BURST_SIZE_L (70),
.PKT_ORI_BURST_SIZE_L (102),
.PKT_ORI_BURST_SIZE_H (104),
.ST_CHANNEL_W (3),
.ST_DATA_W (105),
.AVS_BURSTCOUNT_W (2),
.SUPPRESS_0_BYTEEN_CMD (1),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent (
.clk (clk_0_clk_clk), // clk.clk
.reset (vga_led_0_reset_sink_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_address), // m0.address
.m0_burstcount (audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
.m0_byteenable (audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
.m0_debugaccess (audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
.m0_lock (audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
.m0_readdata (audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
.m0_readdatavalid (audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
.m0_read (audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_read), // .read
.m0_waitrequest (audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
.m0_writedata (audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
.m0_write (audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_write), // .write
.rp_endofpacket (audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_ready), // .ready
.rp_valid (audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
.rp_data (audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_data), // .data
.rp_startofpacket (audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
.cp_ready (burst_adapter_001_source0_ready), // cp.ready
.cp_valid (burst_adapter_001_source0_valid), // .valid
.cp_data (burst_adapter_001_source0_data), // .data
.cp_startofpacket (burst_adapter_001_source0_startofpacket), // .startofpacket
.cp_endofpacket (burst_adapter_001_source0_endofpacket), // .endofpacket
.cp_channel (burst_adapter_001_source0_channel), // .channel
.rf_sink_ready (audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // .data
.rf_source_ready (audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
.rf_source_startofpacket (audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_out_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_out_valid), // .valid
.rdata_fifo_sink_data (audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_out_data), // .data
.rdata_fifo_src_ready (audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponserequest (), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (106),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo (
.clk (clk_0_clk_clk), // clk.clk
.reset (vga_led_0_reset_sink_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_data), // in.data
.in_valid (audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
.in_ready (audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_ready), // .ready
.in_startofpacket (audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
.out_data (audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // out.data
.out_valid (audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
.out_ready (audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (18),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (0),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (0),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo (
.clk (clk_0_clk_clk), // clk.clk
.reset (vga_led_0_reset_sink_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // in.data
.in_valid (audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
.in_ready (audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // .ready
.out_data (audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_out_data), // out.data
.out_valid (audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_out_valid), // .valid
.out_ready (audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_out_ready), // .ready
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_startofpacket (1'b0), // (terminated)
.in_endofpacket (1'b0), // (terminated)
.out_startofpacket (), // (terminated)
.out_endofpacket (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
lab3_mm_interconnect_0_addr_router addr_router (
.sink_ready (hps_0_h2f_lw_axi_master_agent_write_cp_ready), // sink.ready
.sink_valid (hps_0_h2f_lw_axi_master_agent_write_cp_valid), // .valid
.sink_data (hps_0_h2f_lw_axi_master_agent_write_cp_data), // .data
.sink_startofpacket (hps_0_h2f_lw_axi_master_agent_write_cp_startofpacket), // .startofpacket
.sink_endofpacket (hps_0_h2f_lw_axi_master_agent_write_cp_endofpacket), // .endofpacket
.clk (clk_0_clk_clk), // clk.clk
.reset (hps_0_h2f_lw_axi_master_agent_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (addr_router_src_ready), // src.ready
.src_valid (addr_router_src_valid), // .valid
.src_data (addr_router_src_data), // .data
.src_channel (addr_router_src_channel), // .channel
.src_startofpacket (addr_router_src_startofpacket), // .startofpacket
.src_endofpacket (addr_router_src_endofpacket) // .endofpacket
);
lab3_mm_interconnect_0_addr_router addr_router_001 (
.sink_ready (hps_0_h2f_lw_axi_master_agent_read_cp_ready), // sink.ready
.sink_valid (hps_0_h2f_lw_axi_master_agent_read_cp_valid), // .valid
.sink_data (hps_0_h2f_lw_axi_master_agent_read_cp_data), // .data
.sink_startofpacket (hps_0_h2f_lw_axi_master_agent_read_cp_startofpacket), // .startofpacket
.sink_endofpacket (hps_0_h2f_lw_axi_master_agent_read_cp_endofpacket), // .endofpacket
.clk (clk_0_clk_clk), // clk.clk
.reset (hps_0_h2f_lw_axi_master_agent_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (addr_router_001_src_ready), // src.ready
.src_valid (addr_router_001_src_valid), // .valid
.src_data (addr_router_001_src_data), // .data
.src_channel (addr_router_001_src_channel), // .channel
.src_startofpacket (addr_router_001_src_startofpacket), // .startofpacket
.src_endofpacket (addr_router_001_src_endofpacket) // .endofpacket
);
lab3_mm_interconnect_0_addr_router addr_router_002 (
.sink_ready (master_0_master_translator_avalon_universal_master_0_agent_cp_ready), // sink.ready
.sink_valid (master_0_master_translator_avalon_universal_master_0_agent_cp_valid), // .valid
.sink_data (master_0_master_translator_avalon_universal_master_0_agent_cp_data), // .data
.sink_startofpacket (master_0_master_translator_avalon_universal_master_0_agent_cp_startofpacket), // .startofpacket
.sink_endofpacket (master_0_master_translator_avalon_universal_master_0_agent_cp_endofpacket), // .endofpacket
.clk (clk_0_clk_clk), // clk.clk
.reset (vga_led_0_reset_sink_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (addr_router_002_src_ready), // src.ready
.src_valid (addr_router_002_src_valid), // .valid
.src_data (addr_router_002_src_data), // .data
.src_channel (addr_router_002_src_channel), // .channel
.src_startofpacket (addr_router_002_src_startofpacket), // .startofpacket
.src_endofpacket (addr_router_002_src_endofpacket) // .endofpacket
);
lab3_mm_interconnect_0_id_router id_router (
.sink_ready (vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready
.sink_valid (vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
.sink_data (vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_data), // .data
.sink_startofpacket (vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_endofpacket), // .endofpacket
.clk (clk_0_clk_clk), // clk.clk
.reset (vga_led_0_reset_sink_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (id_router_src_ready), // src.ready
.src_valid (id_router_src_valid), // .valid
.src_data (id_router_src_data), // .data
.src_channel (id_router_src_channel), // .channel
.src_startofpacket (id_router_src_startofpacket), // .startofpacket
.src_endofpacket (id_router_src_endofpacket) // .endofpacket
);
lab3_mm_interconnect_0_id_router id_router_001 (
.sink_ready (audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready
.sink_valid (audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
.sink_data (audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_data), // .data
.sink_startofpacket (audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_endofpacket), // .endofpacket
.clk (clk_0_clk_clk), // clk.clk
.reset (vga_led_0_reset_sink_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (id_router_001_src_ready), // src.ready
.src_valid (id_router_001_src_valid), // .valid
.src_data (id_router_001_src_data), // .data
.src_channel (id_router_001_src_channel), // .channel
.src_startofpacket (id_router_001_src_startofpacket), // .startofpacket
.src_endofpacket (id_router_001_src_endofpacket) // .endofpacket
);
altera_merlin_traffic_limiter #(
.PKT_DEST_ID_H (98),
.PKT_DEST_ID_L (98),
.PKT_SRC_ID_H (97),
.PKT_SRC_ID_L (97),
.PKT_TRANS_POSTED (69),
.PKT_TRANS_WRITE (70),
.MAX_OUTSTANDING_RESPONSES (3),
.PIPELINED (0),
.ST_DATA_W (123),
.ST_CHANNEL_W (3),
.VALID_WIDTH (3),
.ENFORCE_ORDER (1),
.PREVENT_HAZARDS (0),
.PKT_BYTE_CNT_H (80),
.PKT_BYTE_CNT_L (74),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.REORDER (0)
) limiter (
.clk (clk_0_clk_clk), // clk.clk
.reset (hps_0_h2f_lw_axi_master_agent_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.cmd_sink_ready (addr_router_src_ready), // cmd_sink.ready
.cmd_sink_valid (addr_router_src_valid), // .valid
.cmd_sink_data (addr_router_src_data), // .data
.cmd_sink_channel (addr_router_src_channel), // .channel
.cmd_sink_startofpacket (addr_router_src_startofpacket), // .startofpacket
.cmd_sink_endofpacket (addr_router_src_endofpacket), // .endofpacket
.cmd_src_ready (limiter_cmd_src_ready), // cmd_src.ready
.cmd_src_data (limiter_cmd_src_data), // .data
.cmd_src_channel (limiter_cmd_src_channel), // .channel
.cmd_src_startofpacket (limiter_cmd_src_startofpacket), // .startofpacket
.cmd_src_endofpacket (limiter_cmd_src_endofpacket), // .endofpacket
.rsp_sink_ready (rsp_xbar_mux_src_ready), // rsp_sink.ready
.rsp_sink_valid (rsp_xbar_mux_src_valid), // .valid
.rsp_sink_channel (rsp_xbar_mux_src_channel), // .channel
.rsp_sink_data (rsp_xbar_mux_src_data), // .data
.rsp_sink_startofpacket (rsp_xbar_mux_src_startofpacket), // .startofpacket
.rsp_sink_endofpacket (rsp_xbar_mux_src_endofpacket), // .endofpacket
.rsp_src_ready (limiter_rsp_src_ready), // rsp_src.ready
.rsp_src_valid (limiter_rsp_src_valid), // .valid
.rsp_src_data (limiter_rsp_src_data), // .data
.rsp_src_channel (limiter_rsp_src_channel), // .channel
.rsp_src_startofpacket (limiter_rsp_src_startofpacket), // .startofpacket
.rsp_src_endofpacket (limiter_rsp_src_endofpacket), // .endofpacket
.cmd_src_valid (limiter_cmd_valid_data) // cmd_valid.data
);
altera_merlin_traffic_limiter #(
.PKT_DEST_ID_H (98),
.PKT_DEST_ID_L (98),
.PKT_SRC_ID_H (97),
.PKT_SRC_ID_L (97),
.PKT_TRANS_POSTED (69),
.PKT_TRANS_WRITE (70),
.MAX_OUTSTANDING_RESPONSES (3),
.PIPELINED (0),
.ST_DATA_W (123),
.ST_CHANNEL_W (3),
.VALID_WIDTH (3),
.ENFORCE_ORDER (1),
.PREVENT_HAZARDS (0),
.PKT_BYTE_CNT_H (80),
.PKT_BYTE_CNT_L (74),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.REORDER (0)
) limiter_001 (
.clk (clk_0_clk_clk), // clk.clk
.reset (hps_0_h2f_lw_axi_master_agent_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.cmd_sink_ready (addr_router_001_src_ready), // cmd_sink.ready
.cmd_sink_valid (addr_router_001_src_valid), // .valid
.cmd_sink_data (addr_router_001_src_data), // .data
.cmd_sink_channel (addr_router_001_src_channel), // .channel
.cmd_sink_startofpacket (addr_router_001_src_startofpacket), // .startofpacket
.cmd_sink_endofpacket (addr_router_001_src_endofpacket), // .endofpacket
.cmd_src_ready (limiter_001_cmd_src_ready), // cmd_src.ready
.cmd_src_data (limiter_001_cmd_src_data), // .data
.cmd_src_channel (limiter_001_cmd_src_channel), // .channel
.cmd_src_startofpacket (limiter_001_cmd_src_startofpacket), // .startofpacket
.cmd_src_endofpacket (limiter_001_cmd_src_endofpacket), // .endofpacket
.rsp_sink_ready (rsp_xbar_mux_001_src_ready), // rsp_sink.ready
.rsp_sink_valid (rsp_xbar_mux_001_src_valid), // .valid
.rsp_sink_channel (rsp_xbar_mux_001_src_channel), // .channel
.rsp_sink_data (rsp_xbar_mux_001_src_data), // .data
.rsp_sink_startofpacket (rsp_xbar_mux_001_src_startofpacket), // .startofpacket
.rsp_sink_endofpacket (rsp_xbar_mux_001_src_endofpacket), // .endofpacket
.rsp_src_ready (limiter_001_rsp_src_ready), // rsp_src.ready
.rsp_src_valid (limiter_001_rsp_src_valid), // .valid
.rsp_src_data (limiter_001_rsp_src_data), // .data
.rsp_src_channel (limiter_001_rsp_src_channel), // .channel
.rsp_src_startofpacket (limiter_001_rsp_src_startofpacket), // .startofpacket
.rsp_src_endofpacket (limiter_001_rsp_src_endofpacket), // .endofpacket
.cmd_src_valid (limiter_001_cmd_valid_data) // cmd_valid.data
);
altera_merlin_traffic_limiter #(
.PKT_DEST_ID_H (98),
.PKT_DEST_ID_L (98),
.PKT_SRC_ID_H (97),
.PKT_SRC_ID_L (97),
.PKT_TRANS_POSTED (69),
.PKT_TRANS_WRITE (70),
.MAX_OUTSTANDING_RESPONSES (3),
.PIPELINED (0),
.ST_DATA_W (123),
.ST_CHANNEL_W (3),
.VALID_WIDTH (3),
.ENFORCE_ORDER (1),
.PREVENT_HAZARDS (0),
.PKT_BYTE_CNT_H (80),
.PKT_BYTE_CNT_L (74),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.REORDER (0)
) limiter_002 (
.clk (clk_0_clk_clk), // clk.clk
.reset (vga_led_0_reset_sink_reset_bridge_in_reset_reset), // clk_reset.reset
.cmd_sink_ready (addr_router_002_src_ready), // cmd_sink.ready
.cmd_sink_valid (addr_router_002_src_valid), // .valid
.cmd_sink_data (addr_router_002_src_data), // .data
.cmd_sink_channel (addr_router_002_src_channel), // .channel
.cmd_sink_startofpacket (addr_router_002_src_startofpacket), // .startofpacket
.cmd_sink_endofpacket (addr_router_002_src_endofpacket), // .endofpacket
.cmd_src_ready (limiter_002_cmd_src_ready), // cmd_src.ready
.cmd_src_data (limiter_002_cmd_src_data), // .data
.cmd_src_channel (limiter_002_cmd_src_channel), // .channel
.cmd_src_startofpacket (limiter_002_cmd_src_startofpacket), // .startofpacket
.cmd_src_endofpacket (limiter_002_cmd_src_endofpacket), // .endofpacket
.rsp_sink_ready (rsp_xbar_mux_002_src_ready), // rsp_sink.ready
.rsp_sink_valid (rsp_xbar_mux_002_src_valid), // .valid
.rsp_sink_channel (rsp_xbar_mux_002_src_channel), // .channel
.rsp_sink_data (rsp_xbar_mux_002_src_data), // .data
.rsp_sink_startofpacket (rsp_xbar_mux_002_src_startofpacket), // .startofpacket
.rsp_sink_endofpacket (rsp_xbar_mux_002_src_endofpacket), // .endofpacket
.rsp_src_ready (limiter_002_rsp_src_ready), // rsp_src.ready
.rsp_src_valid (limiter_002_rsp_src_valid), // .valid
.rsp_src_data (limiter_002_rsp_src_data), // .data
.rsp_src_channel (limiter_002_rsp_src_channel), // .channel
.rsp_src_startofpacket (limiter_002_rsp_src_startofpacket), // .startofpacket
.rsp_src_endofpacket (limiter_002_rsp_src_endofpacket), // .endofpacket
.cmd_src_valid (limiter_002_cmd_valid_data) // cmd_valid.data
);
altera_merlin_burst_adapter #(
.PKT_ADDR_H (49),
.PKT_ADDR_L (18),
.PKT_BEGIN_BURST (77),
.PKT_BYTE_CNT_H (62),
.PKT_BYTE_CNT_L (56),
.PKT_BYTEEN_H (17),
.PKT_BYTEEN_L (16),
.PKT_BURST_SIZE_H (72),
.PKT_BURST_SIZE_L (70),
.PKT_BURST_TYPE_H (74),
.PKT_BURST_TYPE_L (73),
.PKT_BURSTWRAP_H (69),
.PKT_BURSTWRAP_L (63),
.PKT_TRANS_COMPRESSED_READ (50),
.PKT_TRANS_WRITE (52),
.PKT_TRANS_READ (53),
.OUT_NARROW_SIZE (0),
.IN_NARROW_SIZE (1),
.OUT_FIXED (0),
.OUT_COMPLETE_WRAP (0),
.ST_DATA_W (105),
.ST_CHANNEL_W (3),
.OUT_BYTE_CNT_H (57),
.OUT_BURSTWRAP_H (69),
.COMPRESSED_READ_SUPPORT (1),
.BYTEENABLE_SYNTHESIS (1),
.PIPE_INPUTS (0),
.NO_WRAP_SUPPORT (0),
.BURSTWRAP_CONST_MASK (0),
.BURSTWRAP_CONST_VALUE (0)
) burst_adapter (
.clk (clk_0_clk_clk), // cr0.clk
.reset (vga_led_0_reset_sink_reset_bridge_in_reset_reset), // cr0_reset.reset
.sink0_valid (width_adapter_002_src_valid), // sink0.valid
.sink0_data (width_adapter_002_src_data), // .data
.sink0_channel (width_adapter_002_src_channel), // .channel
.sink0_startofpacket (width_adapter_002_src_startofpacket), // .startofpacket
.sink0_endofpacket (width_adapter_002_src_endofpacket), // .endofpacket
.sink0_ready (width_adapter_002_src_ready), // .ready
.source0_valid (burst_adapter_source0_valid), // source0.valid
.source0_data (burst_adapter_source0_data), // .data
.source0_channel (burst_adapter_source0_channel), // .channel
.source0_startofpacket (burst_adapter_source0_startofpacket), // .startofpacket
.source0_endofpacket (burst_adapter_source0_endofpacket), // .endofpacket
.source0_ready (burst_adapter_source0_ready) // .ready
);
altera_merlin_burst_adapter #(
.PKT_ADDR_H (49),
.PKT_ADDR_L (18),
.PKT_BEGIN_BURST (77),
.PKT_BYTE_CNT_H (62),
.PKT_BYTE_CNT_L (56),
.PKT_BYTEEN_H (17),
.PKT_BYTEEN_L (16),
.PKT_BURST_SIZE_H (72),
.PKT_BURST_SIZE_L (70),
.PKT_BURST_TYPE_H (74),
.PKT_BURST_TYPE_L (73),
.PKT_BURSTWRAP_H (69),
.PKT_BURSTWRAP_L (63),
.PKT_TRANS_COMPRESSED_READ (50),
.PKT_TRANS_WRITE (52),
.PKT_TRANS_READ (53),
.OUT_NARROW_SIZE (0),
.IN_NARROW_SIZE (1),
.OUT_FIXED (0),
.OUT_COMPLETE_WRAP (0),
.ST_DATA_W (105),
.ST_CHANNEL_W (3),
.OUT_BYTE_CNT_H (57),
.OUT_BURSTWRAP_H (69),
.COMPRESSED_READ_SUPPORT (1),
.BYTEENABLE_SYNTHESIS (1),
.PIPE_INPUTS (0),
.NO_WRAP_SUPPORT (0),
.BURSTWRAP_CONST_MASK (0),
.BURSTWRAP_CONST_VALUE (0)
) burst_adapter_001 (
.clk (clk_0_clk_clk), // cr0.clk
.reset (vga_led_0_reset_sink_reset_bridge_in_reset_reset), // cr0_reset.reset
.sink0_valid (width_adapter_003_src_valid), // sink0.valid
.sink0_data (width_adapter_003_src_data), // .data
.sink0_channel (width_adapter_003_src_channel), // .channel
.sink0_startofpacket (width_adapter_003_src_startofpacket), // .startofpacket
.sink0_endofpacket (width_adapter_003_src_endofpacket), // .endofpacket
.sink0_ready (width_adapter_003_src_ready), // .ready
.source0_valid (burst_adapter_001_source0_valid), // source0.valid
.source0_data (burst_adapter_001_source0_data), // .data
.source0_channel (burst_adapter_001_source0_channel), // .channel
.source0_startofpacket (burst_adapter_001_source0_startofpacket), // .startofpacket
.source0_endofpacket (burst_adapter_001_source0_endofpacket), // .endofpacket
.source0_ready (burst_adapter_001_source0_ready) // .ready
);
lab3_mm_interconnect_0_cmd_xbar_demux cmd_xbar_demux (
.clk (clk_0_clk_clk), // clk.clk
.reset (hps_0_h2f_lw_axi_master_agent_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (limiter_cmd_src_ready), // sink.ready
.sink_channel (limiter_cmd_src_channel), // .channel
.sink_data (limiter_cmd_src_data), // .data
.sink_startofpacket (limiter_cmd_src_startofpacket), // .startofpacket
.sink_endofpacket (limiter_cmd_src_endofpacket), // .endofpacket
.sink_valid (limiter_cmd_valid_data), // sink_valid.data
.src0_ready (cmd_xbar_demux_src0_ready), // src0.ready
.src0_valid (cmd_xbar_demux_src0_valid), // .valid
.src0_data (cmd_xbar_demux_src0_data), // .data
.src0_channel (cmd_xbar_demux_src0_channel), // .channel
.src0_startofpacket (cmd_xbar_demux_src0_startofpacket), // .startofpacket
.src0_endofpacket (cmd_xbar_demux_src0_endofpacket), // .endofpacket
.src1_ready (cmd_xbar_demux_src1_ready), // src1.ready
.src1_valid (cmd_xbar_demux_src1_valid), // .valid
.src1_data (cmd_xbar_demux_src1_data), // .data
.src1_channel (cmd_xbar_demux_src1_channel), // .channel
.src1_startofpacket (cmd_xbar_demux_src1_startofpacket), // .startofpacket
.src1_endofpacket (cmd_xbar_demux_src1_endofpacket) // .endofpacket
);
lab3_mm_interconnect_0_cmd_xbar_demux cmd_xbar_demux_001 (
.clk (clk_0_clk_clk), // clk.clk
.reset (hps_0_h2f_lw_axi_master_agent_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (limiter_001_cmd_src_ready), // sink.ready
.sink_channel (limiter_001_cmd_src_channel), // .channel
.sink_data (limiter_001_cmd_src_data), // .data
.sink_startofpacket (limiter_001_cmd_src_startofpacket), // .startofpacket
.sink_endofpacket (limiter_001_cmd_src_endofpacket), // .endofpacket
.sink_valid (limiter_001_cmd_valid_data), // sink_valid.data
.src0_ready (cmd_xbar_demux_001_src0_ready), // src0.ready
.src0_valid (cmd_xbar_demux_001_src0_valid), // .valid
.src0_data (cmd_xbar_demux_001_src0_data), // .data
.src0_channel (cmd_xbar_demux_001_src0_channel), // .channel
.src0_startofpacket (cmd_xbar_demux_001_src0_startofpacket), // .startofpacket
.src0_endofpacket (cmd_xbar_demux_001_src0_endofpacket), // .endofpacket
.src1_ready (cmd_xbar_demux_001_src1_ready), // src1.ready
.src1_valid (cmd_xbar_demux_001_src1_valid), // .valid
.src1_data (cmd_xbar_demux_001_src1_data), // .data
.src1_channel (cmd_xbar_demux_001_src1_channel), // .channel
.src1_startofpacket (cmd_xbar_demux_001_src1_startofpacket), // .startofpacket
.src1_endofpacket (cmd_xbar_demux_001_src1_endofpacket) // .endofpacket
);
lab3_mm_interconnect_0_cmd_xbar_demux cmd_xbar_demux_002 (
.clk (clk_0_clk_clk), // clk.clk
.reset (vga_led_0_reset_sink_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (limiter_002_cmd_src_ready), // sink.ready
.sink_channel (limiter_002_cmd_src_channel), // .channel
.sink_data (limiter_002_cmd_src_data), // .data
.sink_startofpacket (limiter_002_cmd_src_startofpacket), // .startofpacket
.sink_endofpacket (limiter_002_cmd_src_endofpacket), // .endofpacket
.sink_valid (limiter_002_cmd_valid_data), // sink_valid.data
.src0_ready (cmd_xbar_demux_002_src0_ready), // src0.ready
.src0_valid (cmd_xbar_demux_002_src0_valid), // .valid
.src0_data (cmd_xbar_demux_002_src0_data), // .data
.src0_channel (cmd_xbar_demux_002_src0_channel), // .channel
.src0_startofpacket (cmd_xbar_demux_002_src0_startofpacket), // .startofpacket
.src0_endofpacket (cmd_xbar_demux_002_src0_endofpacket), // .endofpacket
.src1_ready (cmd_xbar_demux_002_src1_ready), // src1.ready
.src1_valid (cmd_xbar_demux_002_src1_valid), // .valid
.src1_data (cmd_xbar_demux_002_src1_data), // .data
.src1_channel (cmd_xbar_demux_002_src1_channel), // .channel
.src1_startofpacket (cmd_xbar_demux_002_src1_startofpacket), // .startofpacket
.src1_endofpacket (cmd_xbar_demux_002_src1_endofpacket) // .endofpacket
);
lab3_mm_interconnect_0_cmd_xbar_mux cmd_xbar_mux (
.clk (clk_0_clk_clk), // clk.clk
.reset (vga_led_0_reset_sink_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_xbar_mux_src_ready), // src.ready
.src_valid (cmd_xbar_mux_src_valid), // .valid
.src_data (cmd_xbar_mux_src_data), // .data
.src_channel (cmd_xbar_mux_src_channel), // .channel
.src_startofpacket (cmd_xbar_mux_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_xbar_mux_src_endofpacket), // .endofpacket
.sink0_ready (cmd_xbar_demux_src0_ready), // sink0.ready
.sink0_valid (cmd_xbar_demux_src0_valid), // .valid
.sink0_channel (cmd_xbar_demux_src0_channel), // .channel
.sink0_data (cmd_xbar_demux_src0_data), // .data
.sink0_startofpacket (cmd_xbar_demux_src0_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_xbar_demux_src0_endofpacket), // .endofpacket
.sink1_ready (cmd_xbar_demux_001_src0_ready), // sink1.ready
.sink1_valid (cmd_xbar_demux_001_src0_valid), // .valid
.sink1_channel (cmd_xbar_demux_001_src0_channel), // .channel
.sink1_data (cmd_xbar_demux_001_src0_data), // .data
.sink1_startofpacket (cmd_xbar_demux_001_src0_startofpacket), // .startofpacket
.sink1_endofpacket (cmd_xbar_demux_001_src0_endofpacket), // .endofpacket
.sink2_ready (cmd_xbar_demux_002_src0_ready), // sink2.ready
.sink2_valid (cmd_xbar_demux_002_src0_valid), // .valid
.sink2_channel (cmd_xbar_demux_002_src0_channel), // .channel
.sink2_data (cmd_xbar_demux_002_src0_data), // .data
.sink2_startofpacket (cmd_xbar_demux_002_src0_startofpacket), // .startofpacket
.sink2_endofpacket (cmd_xbar_demux_002_src0_endofpacket) // .endofpacket
);
lab3_mm_interconnect_0_cmd_xbar_mux cmd_xbar_mux_001 (
.clk (clk_0_clk_clk), // clk.clk
.reset (vga_led_0_reset_sink_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_xbar_mux_001_src_ready), // src.ready
.src_valid (cmd_xbar_mux_001_src_valid), // .valid
.src_data (cmd_xbar_mux_001_src_data), // .data
.src_channel (cmd_xbar_mux_001_src_channel), // .channel
.src_startofpacket (cmd_xbar_mux_001_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_xbar_mux_001_src_endofpacket), // .endofpacket
.sink0_ready (cmd_xbar_demux_src1_ready), // sink0.ready
.sink0_valid (cmd_xbar_demux_src1_valid), // .valid
.sink0_channel (cmd_xbar_demux_src1_channel), // .channel
.sink0_data (cmd_xbar_demux_src1_data), // .data
.sink0_startofpacket (cmd_xbar_demux_src1_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_xbar_demux_src1_endofpacket), // .endofpacket
.sink1_ready (cmd_xbar_demux_001_src1_ready), // sink1.ready
.sink1_valid (cmd_xbar_demux_001_src1_valid), // .valid
.sink1_channel (cmd_xbar_demux_001_src1_channel), // .channel
.sink1_data (cmd_xbar_demux_001_src1_data), // .data
.sink1_startofpacket (cmd_xbar_demux_001_src1_startofpacket), // .startofpacket
.sink1_endofpacket (cmd_xbar_demux_001_src1_endofpacket), // .endofpacket
.sink2_ready (cmd_xbar_demux_002_src1_ready), // sink2.ready
.sink2_valid (cmd_xbar_demux_002_src1_valid), // .valid
.sink2_channel (cmd_xbar_demux_002_src1_channel), // .channel
.sink2_data (cmd_xbar_demux_002_src1_data), // .data
.sink2_startofpacket (cmd_xbar_demux_002_src1_startofpacket), // .startofpacket
.sink2_endofpacket (cmd_xbar_demux_002_src1_endofpacket) // .endofpacket
);
lab3_mm_interconnect_0_rsp_xbar_demux rsp_xbar_demux (
.clk (clk_0_clk_clk), // clk.clk
.reset (vga_led_0_reset_sink_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (width_adapter_src_ready), // sink.ready
.sink_channel (width_adapter_src_channel), // .channel
.sink_data (width_adapter_src_data), // .data
.sink_startofpacket (width_adapter_src_startofpacket), // .startofpacket
.sink_endofpacket (width_adapter_src_endofpacket), // .endofpacket
.sink_valid (width_adapter_src_valid), // .valid
.src0_ready (rsp_xbar_demux_src0_ready), // src0.ready
.src0_valid (rsp_xbar_demux_src0_valid), // .valid
.src0_data (rsp_xbar_demux_src0_data), // .data
.src0_channel (rsp_xbar_demux_src0_channel), // .channel
.src0_startofpacket (rsp_xbar_demux_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_xbar_demux_src0_endofpacket), // .endofpacket
.src1_ready (rsp_xbar_demux_src1_ready), // src1.ready
.src1_valid (rsp_xbar_demux_src1_valid), // .valid
.src1_data (rsp_xbar_demux_src1_data), // .data
.src1_channel (rsp_xbar_demux_src1_channel), // .channel
.src1_startofpacket (rsp_xbar_demux_src1_startofpacket), // .startofpacket
.src1_endofpacket (rsp_xbar_demux_src1_endofpacket), // .endofpacket
.src2_ready (rsp_xbar_demux_src2_ready), // src2.ready
.src2_valid (rsp_xbar_demux_src2_valid), // .valid
.src2_data (rsp_xbar_demux_src2_data), // .data
.src2_channel (rsp_xbar_demux_src2_channel), // .channel
.src2_startofpacket (rsp_xbar_demux_src2_startofpacket), // .startofpacket
.src2_endofpacket (rsp_xbar_demux_src2_endofpacket) // .endofpacket
);
lab3_mm_interconnect_0_rsp_xbar_demux rsp_xbar_demux_001 (
.clk (clk_0_clk_clk), // clk.clk
.reset (vga_led_0_reset_sink_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (width_adapter_001_src_ready), // sink.ready
.sink_channel (width_adapter_001_src_channel), // .channel
.sink_data (width_adapter_001_src_data), // .data
.sink_startofpacket (width_adapter_001_src_startofpacket), // .startofpacket
.sink_endofpacket (width_adapter_001_src_endofpacket), // .endofpacket
.sink_valid (width_adapter_001_src_valid), // .valid
.src0_ready (rsp_xbar_demux_001_src0_ready), // src0.ready
.src0_valid (rsp_xbar_demux_001_src0_valid), // .valid
.src0_data (rsp_xbar_demux_001_src0_data), // .data
.src0_channel (rsp_xbar_demux_001_src0_channel), // .channel
.src0_startofpacket (rsp_xbar_demux_001_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_xbar_demux_001_src0_endofpacket), // .endofpacket
.src1_ready (rsp_xbar_demux_001_src1_ready), // src1.ready
.src1_valid (rsp_xbar_demux_001_src1_valid), // .valid
.src1_data (rsp_xbar_demux_001_src1_data), // .data
.src1_channel (rsp_xbar_demux_001_src1_channel), // .channel
.src1_startofpacket (rsp_xbar_demux_001_src1_startofpacket), // .startofpacket
.src1_endofpacket (rsp_xbar_demux_001_src1_endofpacket), // .endofpacket
.src2_ready (rsp_xbar_demux_001_src2_ready), // src2.ready
.src2_valid (rsp_xbar_demux_001_src2_valid), // .valid
.src2_data (rsp_xbar_demux_001_src2_data), // .data
.src2_channel (rsp_xbar_demux_001_src2_channel), // .channel
.src2_startofpacket (rsp_xbar_demux_001_src2_startofpacket), // .startofpacket
.src2_endofpacket (rsp_xbar_demux_001_src2_endofpacket) // .endofpacket
);
lab3_mm_interconnect_0_rsp_xbar_mux rsp_xbar_mux (
.clk (clk_0_clk_clk), // clk.clk
.reset (hps_0_h2f_lw_axi_master_agent_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (rsp_xbar_mux_src_ready), // src.ready
.src_valid (rsp_xbar_mux_src_valid), // .valid
.src_data (rsp_xbar_mux_src_data), // .data
.src_channel (rsp_xbar_mux_src_channel), // .channel
.src_startofpacket (rsp_xbar_mux_src_startofpacket), // .startofpacket
.src_endofpacket (rsp_xbar_mux_src_endofpacket), // .endofpacket
.sink0_ready (rsp_xbar_demux_src0_ready), // sink0.ready
.sink0_valid (rsp_xbar_demux_src0_valid), // .valid
.sink0_channel (rsp_xbar_demux_src0_channel), // .channel
.sink0_data (rsp_xbar_demux_src0_data), // .data
.sink0_startofpacket (rsp_xbar_demux_src0_startofpacket), // .startofpacket
.sink0_endofpacket (rsp_xbar_demux_src0_endofpacket), // .endofpacket
.sink1_ready (rsp_xbar_demux_001_src0_ready), // sink1.ready
.sink1_valid (rsp_xbar_demux_001_src0_valid), // .valid
.sink1_channel (rsp_xbar_demux_001_src0_channel), // .channel
.sink1_data (rsp_xbar_demux_001_src0_data), // .data
.sink1_startofpacket (rsp_xbar_demux_001_src0_startofpacket), // .startofpacket
.sink1_endofpacket (rsp_xbar_demux_001_src0_endofpacket) // .endofpacket
);
lab3_mm_interconnect_0_rsp_xbar_mux rsp_xbar_mux_001 (
.clk (clk_0_clk_clk), // clk.clk
.reset (hps_0_h2f_lw_axi_master_agent_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (rsp_xbar_mux_001_src_ready), // src.ready
.src_valid (rsp_xbar_mux_001_src_valid), // .valid
.src_data (rsp_xbar_mux_001_src_data), // .data
.src_channel (rsp_xbar_mux_001_src_channel), // .channel
.src_startofpacket (rsp_xbar_mux_001_src_startofpacket), // .startofpacket
.src_endofpacket (rsp_xbar_mux_001_src_endofpacket), // .endofpacket
.sink0_ready (rsp_xbar_demux_src1_ready), // sink0.ready
.sink0_valid (rsp_xbar_demux_src1_valid), // .valid
.sink0_channel (rsp_xbar_demux_src1_channel), // .channel
.sink0_data (rsp_xbar_demux_src1_data), // .data
.sink0_startofpacket (rsp_xbar_demux_src1_startofpacket), // .startofpacket
.sink0_endofpacket (rsp_xbar_demux_src1_endofpacket), // .endofpacket
.sink1_ready (rsp_xbar_demux_001_src1_ready), // sink1.ready
.sink1_valid (rsp_xbar_demux_001_src1_valid), // .valid
.sink1_channel (rsp_xbar_demux_001_src1_channel), // .channel
.sink1_data (rsp_xbar_demux_001_src1_data), // .data
.sink1_startofpacket (rsp_xbar_demux_001_src1_startofpacket), // .startofpacket
.sink1_endofpacket (rsp_xbar_demux_001_src1_endofpacket) // .endofpacket
);
lab3_mm_interconnect_0_rsp_xbar_mux rsp_xbar_mux_002 (
.clk (clk_0_clk_clk), // clk.clk
.reset (vga_led_0_reset_sink_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (rsp_xbar_mux_002_src_ready), // src.ready
.src_valid (rsp_xbar_mux_002_src_valid), // .valid
.src_data (rsp_xbar_mux_002_src_data), // .data
.src_channel (rsp_xbar_mux_002_src_channel), // .channel
.src_startofpacket (rsp_xbar_mux_002_src_startofpacket), // .startofpacket
.src_endofpacket (rsp_xbar_mux_002_src_endofpacket), // .endofpacket
.sink0_ready (rsp_xbar_demux_src2_ready), // sink0.ready
.sink0_valid (rsp_xbar_demux_src2_valid), // .valid
.sink0_channel (rsp_xbar_demux_src2_channel), // .channel
.sink0_data (rsp_xbar_demux_src2_data), // .data
.sink0_startofpacket (rsp_xbar_demux_src2_startofpacket), // .startofpacket
.sink0_endofpacket (rsp_xbar_demux_src2_endofpacket), // .endofpacket
.sink1_ready (rsp_xbar_demux_001_src2_ready), // sink1.ready
.sink1_valid (rsp_xbar_demux_001_src2_valid), // .valid
.sink1_channel (rsp_xbar_demux_001_src2_channel), // .channel
.sink1_data (rsp_xbar_demux_001_src2_data), // .data
.sink1_startofpacket (rsp_xbar_demux_001_src2_startofpacket), // .startofpacket
.sink1_endofpacket (rsp_xbar_demux_001_src2_endofpacket) // .endofpacket
);
altera_merlin_width_adapter #(
.IN_PKT_ADDR_H (49),
.IN_PKT_ADDR_L (18),
.IN_PKT_DATA_H (15),
.IN_PKT_DATA_L (0),
.IN_PKT_BYTEEN_H (17),
.IN_PKT_BYTEEN_L (16),
.IN_PKT_BYTE_CNT_H (62),
.IN_PKT_BYTE_CNT_L (56),
.IN_PKT_TRANS_COMPRESSED_READ (50),
.IN_PKT_BURSTWRAP_H (69),
.IN_PKT_BURSTWRAP_L (63),
.IN_PKT_BURST_SIZE_H (72),
.IN_PKT_BURST_SIZE_L (70),
.IN_PKT_RESPONSE_STATUS_H (101),
.IN_PKT_RESPONSE_STATUS_L (100),
.IN_PKT_TRANS_EXCLUSIVE (55),
.IN_PKT_BURST_TYPE_H (74),
.IN_PKT_BURST_TYPE_L (73),
.IN_PKT_ORI_BURST_SIZE_L (102),
.IN_PKT_ORI_BURST_SIZE_H (104),
.IN_ST_DATA_W (105),
.OUT_PKT_ADDR_H (67),
.OUT_PKT_ADDR_L (36),
.OUT_PKT_DATA_H (31),
.OUT_PKT_DATA_L (0),
.OUT_PKT_BYTEEN_H (35),
.OUT_PKT_BYTEEN_L (32),
.OUT_PKT_BYTE_CNT_H (80),
.OUT_PKT_BYTE_CNT_L (74),
.OUT_PKT_TRANS_COMPRESSED_READ (68),
.OUT_PKT_BURST_SIZE_H (90),
.OUT_PKT_BURST_SIZE_L (88),
.OUT_PKT_RESPONSE_STATUS_H (119),
.OUT_PKT_RESPONSE_STATUS_L (118),
.OUT_PKT_TRANS_EXCLUSIVE (73),
.OUT_PKT_BURST_TYPE_H (92),
.OUT_PKT_BURST_TYPE_L (91),
.OUT_PKT_ORI_BURST_SIZE_L (120),
.OUT_PKT_ORI_BURST_SIZE_H (122),
.OUT_ST_DATA_W (123),
.ST_CHANNEL_W (3),
.OPTIMIZE_FOR_RSP (0),
.RESPONSE_PATH (1),
.CONSTANT_BURST_SIZE (0),
.PACKING (1)
) width_adapter (
.clk (clk_0_clk_clk), // clk.clk
.reset (vga_led_0_reset_sink_reset_bridge_in_reset_reset), // clk_reset.reset
.in_valid (id_router_src_valid), // sink.valid
.in_channel (id_router_src_channel), // .channel
.in_startofpacket (id_router_src_startofpacket), // .startofpacket
.in_endofpacket (id_router_src_endofpacket), // .endofpacket
.in_ready (id_router_src_ready), // .ready
.in_data (id_router_src_data), // .data
.out_endofpacket (width_adapter_src_endofpacket), // src.endofpacket
.out_data (width_adapter_src_data), // .data
.out_channel (width_adapter_src_channel), // .channel
.out_valid (width_adapter_src_valid), // .valid
.out_ready (width_adapter_src_ready), // .ready
.out_startofpacket (width_adapter_src_startofpacket), // .startofpacket
.in_command_size_data (3'b000) // (terminated)
);
altera_merlin_width_adapter #(
.IN_PKT_ADDR_H (49),
.IN_PKT_ADDR_L (18),
.IN_PKT_DATA_H (15),
.IN_PKT_DATA_L (0),
.IN_PKT_BYTEEN_H (17),
.IN_PKT_BYTEEN_L (16),
.IN_PKT_BYTE_CNT_H (62),
.IN_PKT_BYTE_CNT_L (56),
.IN_PKT_TRANS_COMPRESSED_READ (50),
.IN_PKT_BURSTWRAP_H (69),
.IN_PKT_BURSTWRAP_L (63),
.IN_PKT_BURST_SIZE_H (72),
.IN_PKT_BURST_SIZE_L (70),
.IN_PKT_RESPONSE_STATUS_H (101),
.IN_PKT_RESPONSE_STATUS_L (100),
.IN_PKT_TRANS_EXCLUSIVE (55),
.IN_PKT_BURST_TYPE_H (74),
.IN_PKT_BURST_TYPE_L (73),
.IN_PKT_ORI_BURST_SIZE_L (102),
.IN_PKT_ORI_BURST_SIZE_H (104),
.IN_ST_DATA_W (105),
.OUT_PKT_ADDR_H (67),
.OUT_PKT_ADDR_L (36),
.OUT_PKT_DATA_H (31),
.OUT_PKT_DATA_L (0),
.OUT_PKT_BYTEEN_H (35),
.OUT_PKT_BYTEEN_L (32),
.OUT_PKT_BYTE_CNT_H (80),
.OUT_PKT_BYTE_CNT_L (74),
.OUT_PKT_TRANS_COMPRESSED_READ (68),
.OUT_PKT_BURST_SIZE_H (90),
.OUT_PKT_BURST_SIZE_L (88),
.OUT_PKT_RESPONSE_STATUS_H (119),
.OUT_PKT_RESPONSE_STATUS_L (118),
.OUT_PKT_TRANS_EXCLUSIVE (73),
.OUT_PKT_BURST_TYPE_H (92),
.OUT_PKT_BURST_TYPE_L (91),
.OUT_PKT_ORI_BURST_SIZE_L (120),
.OUT_PKT_ORI_BURST_SIZE_H (122),
.OUT_ST_DATA_W (123),
.ST_CHANNEL_W (3),
.OPTIMIZE_FOR_RSP (0),
.RESPONSE_PATH (1),
.CONSTANT_BURST_SIZE (0),
.PACKING (1)
) width_adapter_001 (
.clk (clk_0_clk_clk), // clk.clk
.reset (vga_led_0_reset_sink_reset_bridge_in_reset_reset), // clk_reset.reset
.in_valid (id_router_001_src_valid), // sink.valid
.in_channel (id_router_001_src_channel), // .channel
.in_startofpacket (id_router_001_src_startofpacket), // .startofpacket
.in_endofpacket (id_router_001_src_endofpacket), // .endofpacket
.in_ready (id_router_001_src_ready), // .ready
.in_data (id_router_001_src_data), // .data
.out_endofpacket (width_adapter_001_src_endofpacket), // src.endofpacket
.out_data (width_adapter_001_src_data), // .data
.out_channel (width_adapter_001_src_channel), // .channel
.out_valid (width_adapter_001_src_valid), // .valid
.out_ready (width_adapter_001_src_ready), // .ready
.out_startofpacket (width_adapter_001_src_startofpacket), // .startofpacket
.in_command_size_data (3'b000) // (terminated)
);
altera_merlin_width_adapter #(
.IN_PKT_ADDR_H (67),
.IN_PKT_ADDR_L (36),
.IN_PKT_DATA_H (31),
.IN_PKT_DATA_L (0),
.IN_PKT_BYTEEN_H (35),
.IN_PKT_BYTEEN_L (32),
.IN_PKT_BYTE_CNT_H (80),
.IN_PKT_BYTE_CNT_L (74),
.IN_PKT_TRANS_COMPRESSED_READ (68),
.IN_PKT_BURSTWRAP_H (87),
.IN_PKT_BURSTWRAP_L (81),
.IN_PKT_BURST_SIZE_H (90),
.IN_PKT_BURST_SIZE_L (88),
.IN_PKT_RESPONSE_STATUS_H (119),
.IN_PKT_RESPONSE_STATUS_L (118),
.IN_PKT_TRANS_EXCLUSIVE (73),
.IN_PKT_BURST_TYPE_H (92),
.IN_PKT_BURST_TYPE_L (91),
.IN_PKT_ORI_BURST_SIZE_L (120),
.IN_PKT_ORI_BURST_SIZE_H (122),
.IN_ST_DATA_W (123),
.OUT_PKT_ADDR_H (49),
.OUT_PKT_ADDR_L (18),
.OUT_PKT_DATA_H (15),
.OUT_PKT_DATA_L (0),
.OUT_PKT_BYTEEN_H (17),
.OUT_PKT_BYTEEN_L (16),
.OUT_PKT_BYTE_CNT_H (62),
.OUT_PKT_BYTE_CNT_L (56),
.OUT_PKT_TRANS_COMPRESSED_READ (50),
.OUT_PKT_BURST_SIZE_H (72),
.OUT_PKT_BURST_SIZE_L (70),
.OUT_PKT_RESPONSE_STATUS_H (101),
.OUT_PKT_RESPONSE_STATUS_L (100),
.OUT_PKT_TRANS_EXCLUSIVE (55),
.OUT_PKT_BURST_TYPE_H (74),
.OUT_PKT_BURST_TYPE_L (73),
.OUT_PKT_ORI_BURST_SIZE_L (102),
.OUT_PKT_ORI_BURST_SIZE_H (104),
.OUT_ST_DATA_W (105),
.ST_CHANNEL_W (3),
.OPTIMIZE_FOR_RSP (0),
.RESPONSE_PATH (0),
.CONSTANT_BURST_SIZE (0),
.PACKING (0)
) width_adapter_002 (
.clk (clk_0_clk_clk), // clk.clk
.reset (vga_led_0_reset_sink_reset_bridge_in_reset_reset), // clk_reset.reset
.in_valid (cmd_xbar_mux_src_valid), // sink.valid
.in_channel (cmd_xbar_mux_src_channel), // .channel
.in_startofpacket (cmd_xbar_mux_src_startofpacket), // .startofpacket
.in_endofpacket (cmd_xbar_mux_src_endofpacket), // .endofpacket
.in_ready (cmd_xbar_mux_src_ready), // .ready
.in_data (cmd_xbar_mux_src_data), // .data
.out_endofpacket (width_adapter_002_src_endofpacket), // src.endofpacket
.out_data (width_adapter_002_src_data), // .data
.out_channel (width_adapter_002_src_channel), // .channel
.out_valid (width_adapter_002_src_valid), // .valid
.out_ready (width_adapter_002_src_ready), // .ready
.out_startofpacket (width_adapter_002_src_startofpacket), // .startofpacket
.in_command_size_data (3'b000) // (terminated)
);
altera_merlin_width_adapter #(
.IN_PKT_ADDR_H (67),
.IN_PKT_ADDR_L (36),
.IN_PKT_DATA_H (31),
.IN_PKT_DATA_L (0),
.IN_PKT_BYTEEN_H (35),
.IN_PKT_BYTEEN_L (32),
.IN_PKT_BYTE_CNT_H (80),
.IN_PKT_BYTE_CNT_L (74),
.IN_PKT_TRANS_COMPRESSED_READ (68),
.IN_PKT_BURSTWRAP_H (87),
.IN_PKT_BURSTWRAP_L (81),
.IN_PKT_BURST_SIZE_H (90),
.IN_PKT_BURST_SIZE_L (88),
.IN_PKT_RESPONSE_STATUS_H (119),
.IN_PKT_RESPONSE_STATUS_L (118),
.IN_PKT_TRANS_EXCLUSIVE (73),
.IN_PKT_BURST_TYPE_H (92),
.IN_PKT_BURST_TYPE_L (91),
.IN_PKT_ORI_BURST_SIZE_L (120),
.IN_PKT_ORI_BURST_SIZE_H (122),
.IN_ST_DATA_W (123),
.OUT_PKT_ADDR_H (49),
.OUT_PKT_ADDR_L (18),
.OUT_PKT_DATA_H (15),
.OUT_PKT_DATA_L (0),
.OUT_PKT_BYTEEN_H (17),
.OUT_PKT_BYTEEN_L (16),
.OUT_PKT_BYTE_CNT_H (62),
.OUT_PKT_BYTE_CNT_L (56),
.OUT_PKT_TRANS_COMPRESSED_READ (50),
.OUT_PKT_BURST_SIZE_H (72),
.OUT_PKT_BURST_SIZE_L (70),
.OUT_PKT_RESPONSE_STATUS_H (101),
.OUT_PKT_RESPONSE_STATUS_L (100),
.OUT_PKT_TRANS_EXCLUSIVE (55),
.OUT_PKT_BURST_TYPE_H (74),
.OUT_PKT_BURST_TYPE_L (73),
.OUT_PKT_ORI_BURST_SIZE_L (102),
.OUT_PKT_ORI_BURST_SIZE_H (104),
.OUT_ST_DATA_W (105),
.ST_CHANNEL_W (3),
.OPTIMIZE_FOR_RSP (0),
.RESPONSE_PATH (0),
.CONSTANT_BURST_SIZE (0),
.PACKING (0)
) width_adapter_003 (
.clk (clk_0_clk_clk), // clk.clk
.reset (vga_led_0_reset_sink_reset_bridge_in_reset_reset), // clk_reset.reset
.in_valid (cmd_xbar_mux_001_src_valid), // sink.valid
.in_channel (cmd_xbar_mux_001_src_channel), // .channel
.in_startofpacket (cmd_xbar_mux_001_src_startofpacket), // .startofpacket
.in_endofpacket (cmd_xbar_mux_001_src_endofpacket), // .endofpacket
.in_ready (cmd_xbar_mux_001_src_ready), // .ready
.in_data (cmd_xbar_mux_001_src_data), // .data
.out_endofpacket (width_adapter_003_src_endofpacket), // src.endofpacket
.out_data (width_adapter_003_src_data), // .data
.out_channel (width_adapter_003_src_channel), // .channel
.out_valid (width_adapter_003_src_valid), // .valid
.out_ready (width_adapter_003_src_ready), // .ready
.out_startofpacket (width_adapter_003_src_startofpacket), // .startofpacket
.in_command_size_data (3'b000) // (terminated)
);
endmodule |
module sctag_retdp(/*AUTOARG*/
// Outputs
retdp_data_c7_buf, retdp_ecc_c7_buf, so,
// Inputs
scdata_sctag_decc_c6, rclk, si, se
);
output [127:0] retdp_data_c7_buf;
output [ 27:0] retdp_ecc_c7_buf;
output so;
input [155:0] scdata_sctag_decc_c6;
input rclk;
input si, se;
// Output of the L2$ data array.
wire [127:0] retdp_data_c6;
wire [ 27:0] retdp_ecc_c6;
assign {retdp_data_c6[31:0], retdp_ecc_c6[6:0]} = scdata_sctag_decc_c6[38:0];
assign {retdp_data_c6[63:32], retdp_ecc_c6[13:7]} = scdata_sctag_decc_c6[77:39];
assign {retdp_data_c6[95:64], retdp_ecc_c6[20:14]} = scdata_sctag_decc_c6[116:78];
assign {retdp_data_c6[127:96], retdp_ecc_c6[27:21]} = scdata_sctag_decc_c6[155:117];
// arrange these flops in 16 rows and 10 columns
// row0 ->{ data[2:0],ecc[6:0]}
// row1 ->{ data[12:3]}
// row2 ->{ data[22:13]}
// row3 ->{ data[31:23]}
// and so 0n. Buffer the outputs of each
// bit with a 40x buffer/inverter.
dff_s #(128) ff_data_rtn_c7
(.q (retdp_data_c7_buf[127:0]),
.din (retdp_data_c6[127:0]),
.clk (rclk),
.se(se), .si (), .so ()
) ;
dff_s #(28) ff_ecc_rtn_c7
(.q (retdp_ecc_c7_buf[27:0]),
.din (retdp_ecc_c6[27:0]),
.clk (rclk),
.se(se), .si (), .so ()
) ;
endmodule |
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7
(CAN0_PHY_TX,
CAN0_PHY_RX,
CAN1_PHY_TX,
CAN1_PHY_RX,
ENET0_GMII_TX_EN,
ENET0_GMII_TX_ER,
ENET0_MDIO_MDC,
ENET0_MDIO_O,
ENET0_MDIO_T,
ENET0_PTP_DELAY_REQ_RX,
ENET0_PTP_DELAY_REQ_TX,
ENET0_PTP_PDELAY_REQ_RX,
ENET0_PTP_PDELAY_REQ_TX,
ENET0_PTP_PDELAY_RESP_RX,
ENET0_PTP_PDELAY_RESP_TX,
ENET0_PTP_SYNC_FRAME_RX,
ENET0_PTP_SYNC_FRAME_TX,
ENET0_SOF_RX,
ENET0_SOF_TX,
ENET0_GMII_TXD,
ENET0_GMII_COL,
ENET0_GMII_CRS,
ENET0_GMII_RX_CLK,
ENET0_GMII_RX_DV,
ENET0_GMII_RX_ER,
ENET0_GMII_TX_CLK,
ENET0_MDIO_I,
ENET0_EXT_INTIN,
ENET0_GMII_RXD,
ENET1_GMII_TX_EN,
ENET1_GMII_TX_ER,
ENET1_MDIO_MDC,
ENET1_MDIO_O,
ENET1_MDIO_T,
ENET1_PTP_DELAY_REQ_RX,
ENET1_PTP_DELAY_REQ_TX,
ENET1_PTP_PDELAY_REQ_RX,
ENET1_PTP_PDELAY_REQ_TX,
ENET1_PTP_PDELAY_RESP_RX,
ENET1_PTP_PDELAY_RESP_TX,
ENET1_PTP_SYNC_FRAME_RX,
ENET1_PTP_SYNC_FRAME_TX,
ENET1_SOF_RX,
ENET1_SOF_TX,
ENET1_GMII_TXD,
ENET1_GMII_COL,
ENET1_GMII_CRS,
ENET1_GMII_RX_CLK,
ENET1_GMII_RX_DV,
ENET1_GMII_RX_ER,
ENET1_GMII_TX_CLK,
ENET1_MDIO_I,
ENET1_EXT_INTIN,
ENET1_GMII_RXD,
GPIO_I,
GPIO_O,
GPIO_T,
I2C0_SDA_I,
I2C0_SDA_O,
I2C0_SDA_T,
I2C0_SCL_I,
I2C0_SCL_O,
I2C0_SCL_T,
I2C1_SDA_I,
I2C1_SDA_O,
I2C1_SDA_T,
I2C1_SCL_I,
I2C1_SCL_O,
I2C1_SCL_T,
PJTAG_TCK,
PJTAG_TMS,
PJTAG_TDI,
PJTAG_TDO,
SDIO0_CLK,
SDIO0_CLK_FB,
SDIO0_CMD_O,
SDIO0_CMD_I,
SDIO0_CMD_T,
SDIO0_DATA_I,
SDIO0_DATA_O,
SDIO0_DATA_T,
SDIO0_LED,
SDIO0_CDN,
SDIO0_WP,
SDIO0_BUSPOW,
SDIO0_BUSVOLT,
SDIO1_CLK,
SDIO1_CLK_FB,
SDIO1_CMD_O,
SDIO1_CMD_I,
SDIO1_CMD_T,
SDIO1_DATA_I,
SDIO1_DATA_O,
SDIO1_DATA_T,
SDIO1_LED,
SDIO1_CDN,
SDIO1_WP,
SDIO1_BUSPOW,
SDIO1_BUSVOLT,
SPI0_SCLK_I,
SPI0_SCLK_O,
SPI0_SCLK_T,
SPI0_MOSI_I,
SPI0_MOSI_O,
SPI0_MOSI_T,
SPI0_MISO_I,
SPI0_MISO_O,
SPI0_MISO_T,
SPI0_SS_I,
SPI0_SS_O,
SPI0_SS1_O,
SPI0_SS2_O,
SPI0_SS_T,
SPI1_SCLK_I,
SPI1_SCLK_O,
SPI1_SCLK_T,
SPI1_MOSI_I,
SPI1_MOSI_O,
SPI1_MOSI_T,
SPI1_MISO_I,
SPI1_MISO_O,
SPI1_MISO_T,
SPI1_SS_I,
SPI1_SS_O,
SPI1_SS1_O,
SPI1_SS2_O,
SPI1_SS_T,
UART0_DTRN,
UART0_RTSN,
UART0_TX,
UART0_CTSN,
UART0_DCDN,
UART0_DSRN,
UART0_RIN,
UART0_RX,
UART1_DTRN,
UART1_RTSN,
UART1_TX,
UART1_CTSN,
UART1_DCDN,
UART1_DSRN,
UART1_RIN,
UART1_RX,
TTC0_WAVE0_OUT,
TTC0_WAVE1_OUT,
TTC0_WAVE2_OUT,
TTC0_CLK0_IN,
TTC0_CLK1_IN,
TTC0_CLK2_IN,
TTC1_WAVE0_OUT,
TTC1_WAVE1_OUT,
TTC1_WAVE2_OUT,
TTC1_CLK0_IN,
TTC1_CLK1_IN,
TTC1_CLK2_IN,
WDT_CLK_IN,
WDT_RST_OUT,
TRACE_CLK,
TRACE_CTL,
TRACE_DATA,
TRACE_CLK_OUT,
USB0_PORT_INDCTL,
USB0_VBUS_PWRSELECT,
USB0_VBUS_PWRFAULT,
USB1_PORT_INDCTL,
USB1_VBUS_PWRSELECT,
USB1_VBUS_PWRFAULT,
SRAM_INTIN,
M_AXI_GP0_ARESETN,
M_AXI_GP0_ARVALID,
M_AXI_GP0_AWVALID,
M_AXI_GP0_BREADY,
M_AXI_GP0_RREADY,
M_AXI_GP0_WLAST,
M_AXI_GP0_WVALID,
M_AXI_GP0_ARID,
M_AXI_GP0_AWID,
M_AXI_GP0_WID,
M_AXI_GP0_ARBURST,
M_AXI_GP0_ARLOCK,
M_AXI_GP0_ARSIZE,
M_AXI_GP0_AWBURST,
M_AXI_GP0_AWLOCK,
M_AXI_GP0_AWSIZE,
M_AXI_GP0_ARPROT,
M_AXI_GP0_AWPROT,
M_AXI_GP0_ARADDR,
M_AXI_GP0_AWADDR,
M_AXI_GP0_WDATA,
M_AXI_GP0_ARCACHE,
M_AXI_GP0_ARLEN,
M_AXI_GP0_ARQOS,
M_AXI_GP0_AWCACHE,
M_AXI_GP0_AWLEN,
M_AXI_GP0_AWQOS,
M_AXI_GP0_WSTRB,
M_AXI_GP0_ACLK,
M_AXI_GP0_ARREADY,
M_AXI_GP0_AWREADY,
M_AXI_GP0_BVALID,
M_AXI_GP0_RLAST,
M_AXI_GP0_RVALID,
M_AXI_GP0_WREADY,
M_AXI_GP0_BID,
M_AXI_GP0_RID,
M_AXI_GP0_BRESP,
M_AXI_GP0_RRESP,
M_AXI_GP0_RDATA,
M_AXI_GP1_ARESETN,
M_AXI_GP1_ARVALID,
M_AXI_GP1_AWVALID,
M_AXI_GP1_BREADY,
M_AXI_GP1_RREADY,
M_AXI_GP1_WLAST,
M_AXI_GP1_WVALID,
M_AXI_GP1_ARID,
M_AXI_GP1_AWID,
M_AXI_GP1_WID,
M_AXI_GP1_ARBURST,
M_AXI_GP1_ARLOCK,
M_AXI_GP1_ARSIZE,
M_AXI_GP1_AWBURST,
M_AXI_GP1_AWLOCK,
M_AXI_GP1_AWSIZE,
M_AXI_GP1_ARPROT,
M_AXI_GP1_AWPROT,
M_AXI_GP1_ARADDR,
M_AXI_GP1_AWADDR,
M_AXI_GP1_WDATA,
M_AXI_GP1_ARCACHE,
M_AXI_GP1_ARLEN,
M_AXI_GP1_ARQOS,
M_AXI_GP1_AWCACHE,
M_AXI_GP1_AWLEN,
M_AXI_GP1_AWQOS,
M_AXI_GP1_WSTRB,
M_AXI_GP1_ACLK,
M_AXI_GP1_ARREADY,
M_AXI_GP1_AWREADY,
M_AXI_GP1_BVALID,
M_AXI_GP1_RLAST,
M_AXI_GP1_RVALID,
M_AXI_GP1_WREADY,
M_AXI_GP1_BID,
M_AXI_GP1_RID,
M_AXI_GP1_BRESP,
M_AXI_GP1_RRESP,
M_AXI_GP1_RDATA,
S_AXI_GP0_ARESETN,
S_AXI_GP0_ARREADY,
S_AXI_GP0_AWREADY,
S_AXI_GP0_BVALID,
S_AXI_GP0_RLAST,
S_AXI_GP0_RVALID,
S_AXI_GP0_WREADY,
S_AXI_GP0_BRESP,
S_AXI_GP0_RRESP,
S_AXI_GP0_RDATA,
S_AXI_GP0_BID,
S_AXI_GP0_RID,
S_AXI_GP0_ACLK,
S_AXI_GP0_ARVALID,
S_AXI_GP0_AWVALID,
S_AXI_GP0_BREADY,
S_AXI_GP0_RREADY,
S_AXI_GP0_WLAST,
S_AXI_GP0_WVALID,
S_AXI_GP0_ARBURST,
S_AXI_GP0_ARLOCK,
S_AXI_GP0_ARSIZE,
S_AXI_GP0_AWBURST,
S_AXI_GP0_AWLOCK,
S_AXI_GP0_AWSIZE,
S_AXI_GP0_ARPROT,
S_AXI_GP0_AWPROT,
S_AXI_GP0_ARADDR,
S_AXI_GP0_AWADDR,
S_AXI_GP0_WDATA,
S_AXI_GP0_ARCACHE,
S_AXI_GP0_ARLEN,
S_AXI_GP0_ARQOS,
S_AXI_GP0_AWCACHE,
S_AXI_GP0_AWLEN,
S_AXI_GP0_AWQOS,
S_AXI_GP0_WSTRB,
S_AXI_GP0_ARID,
S_AXI_GP0_AWID,
S_AXI_GP0_WID,
S_AXI_GP1_ARESETN,
S_AXI_GP1_ARREADY,
S_AXI_GP1_AWREADY,
S_AXI_GP1_BVALID,
S_AXI_GP1_RLAST,
S_AXI_GP1_RVALID,
S_AXI_GP1_WREADY,
S_AXI_GP1_BRESP,
S_AXI_GP1_RRESP,
S_AXI_GP1_RDATA,
S_AXI_GP1_BID,
S_AXI_GP1_RID,
S_AXI_GP1_ACLK,
S_AXI_GP1_ARVALID,
S_AXI_GP1_AWVALID,
S_AXI_GP1_BREADY,
S_AXI_GP1_RREADY,
S_AXI_GP1_WLAST,
S_AXI_GP1_WVALID,
S_AXI_GP1_ARBURST,
S_AXI_GP1_ARLOCK,
S_AXI_GP1_ARSIZE,
S_AXI_GP1_AWBURST,
S_AXI_GP1_AWLOCK,
S_AXI_GP1_AWSIZE,
S_AXI_GP1_ARPROT,
S_AXI_GP1_AWPROT,
S_AXI_GP1_ARADDR,
S_AXI_GP1_AWADDR,
S_AXI_GP1_WDATA,
S_AXI_GP1_ARCACHE,
S_AXI_GP1_ARLEN,
S_AXI_GP1_ARQOS,
S_AXI_GP1_AWCACHE,
S_AXI_GP1_AWLEN,
S_AXI_GP1_AWQOS,
S_AXI_GP1_WSTRB,
S_AXI_GP1_ARID,
S_AXI_GP1_AWID,
S_AXI_GP1_WID,
S_AXI_ACP_ARESETN,
S_AXI_ACP_ARREADY,
S_AXI_ACP_AWREADY,
S_AXI_ACP_BVALID,
S_AXI_ACP_RLAST,
S_AXI_ACP_RVALID,
S_AXI_ACP_WREADY,
S_AXI_ACP_BRESP,
S_AXI_ACP_RRESP,
S_AXI_ACP_BID,
S_AXI_ACP_RID,
S_AXI_ACP_RDATA,
S_AXI_ACP_ACLK,
S_AXI_ACP_ARVALID,
S_AXI_ACP_AWVALID,
S_AXI_ACP_BREADY,
S_AXI_ACP_RREADY,
S_AXI_ACP_WLAST,
S_AXI_ACP_WVALID,
S_AXI_ACP_ARID,
S_AXI_ACP_ARPROT,
S_AXI_ACP_AWID,
S_AXI_ACP_AWPROT,
S_AXI_ACP_WID,
S_AXI_ACP_ARADDR,
S_AXI_ACP_AWADDR,
S_AXI_ACP_ARCACHE,
S_AXI_ACP_ARLEN,
S_AXI_ACP_ARQOS,
S_AXI_ACP_AWCACHE,
S_AXI_ACP_AWLEN,
S_AXI_ACP_AWQOS,
S_AXI_ACP_ARBURST,
S_AXI_ACP_ARLOCK,
S_AXI_ACP_ARSIZE,
S_AXI_ACP_AWBURST,
S_AXI_ACP_AWLOCK,
S_AXI_ACP_AWSIZE,
S_AXI_ACP_ARUSER,
S_AXI_ACP_AWUSER,
S_AXI_ACP_WDATA,
S_AXI_ACP_WSTRB,
S_AXI_HP0_ARESETN,
S_AXI_HP0_ARREADY,
S_AXI_HP0_AWREADY,
S_AXI_HP0_BVALID,
S_AXI_HP0_RLAST,
S_AXI_HP0_RVALID,
S_AXI_HP0_WREADY,
S_AXI_HP0_BRESP,
S_AXI_HP0_RRESP,
S_AXI_HP0_BID,
S_AXI_HP0_RID,
S_AXI_HP0_RDATA,
S_AXI_HP0_RCOUNT,
S_AXI_HP0_WCOUNT,
S_AXI_HP0_RACOUNT,
S_AXI_HP0_WACOUNT,
S_AXI_HP0_ACLK,
S_AXI_HP0_ARVALID,
S_AXI_HP0_AWVALID,
S_AXI_HP0_BREADY,
S_AXI_HP0_RDISSUECAP1_EN,
S_AXI_HP0_RREADY,
S_AXI_HP0_WLAST,
S_AXI_HP0_WRISSUECAP1_EN,
S_AXI_HP0_WVALID,
S_AXI_HP0_ARBURST,
S_AXI_HP0_ARLOCK,
S_AXI_HP0_ARSIZE,
S_AXI_HP0_AWBURST,
S_AXI_HP0_AWLOCK,
S_AXI_HP0_AWSIZE,
S_AXI_HP0_ARPROT,
S_AXI_HP0_AWPROT,
S_AXI_HP0_ARADDR,
S_AXI_HP0_AWADDR,
S_AXI_HP0_ARCACHE,
S_AXI_HP0_ARLEN,
S_AXI_HP0_ARQOS,
S_AXI_HP0_AWCACHE,
S_AXI_HP0_AWLEN,
S_AXI_HP0_AWQOS,
S_AXI_HP0_ARID,
S_AXI_HP0_AWID,
S_AXI_HP0_WID,
S_AXI_HP0_WDATA,
S_AXI_HP0_WSTRB,
S_AXI_HP1_ARESETN,
S_AXI_HP1_ARREADY,
S_AXI_HP1_AWREADY,
S_AXI_HP1_BVALID,
S_AXI_HP1_RLAST,
S_AXI_HP1_RVALID,
S_AXI_HP1_WREADY,
S_AXI_HP1_BRESP,
S_AXI_HP1_RRESP,
S_AXI_HP1_BID,
S_AXI_HP1_RID,
S_AXI_HP1_RDATA,
S_AXI_HP1_RCOUNT,
S_AXI_HP1_WCOUNT,
S_AXI_HP1_RACOUNT,
S_AXI_HP1_WACOUNT,
S_AXI_HP1_ACLK,
S_AXI_HP1_ARVALID,
S_AXI_HP1_AWVALID,
S_AXI_HP1_BREADY,
S_AXI_HP1_RDISSUECAP1_EN,
S_AXI_HP1_RREADY,
S_AXI_HP1_WLAST,
S_AXI_HP1_WRISSUECAP1_EN,
S_AXI_HP1_WVALID,
S_AXI_HP1_ARBURST,
S_AXI_HP1_ARLOCK,
S_AXI_HP1_ARSIZE,
S_AXI_HP1_AWBURST,
S_AXI_HP1_AWLOCK,
S_AXI_HP1_AWSIZE,
S_AXI_HP1_ARPROT,
S_AXI_HP1_AWPROT,
S_AXI_HP1_ARADDR,
S_AXI_HP1_AWADDR,
S_AXI_HP1_ARCACHE,
S_AXI_HP1_ARLEN,
S_AXI_HP1_ARQOS,
S_AXI_HP1_AWCACHE,
S_AXI_HP1_AWLEN,
S_AXI_HP1_AWQOS,
S_AXI_HP1_ARID,
S_AXI_HP1_AWID,
S_AXI_HP1_WID,
S_AXI_HP1_WDATA,
S_AXI_HP1_WSTRB,
S_AXI_HP2_ARESETN,
S_AXI_HP2_ARREADY,
S_AXI_HP2_AWREADY,
S_AXI_HP2_BVALID,
S_AXI_HP2_RLAST,
S_AXI_HP2_RVALID,
S_AXI_HP2_WREADY,
S_AXI_HP2_BRESP,
S_AXI_HP2_RRESP,
S_AXI_HP2_BID,
S_AXI_HP2_RID,
S_AXI_HP2_RDATA,
S_AXI_HP2_RCOUNT,
S_AXI_HP2_WCOUNT,
S_AXI_HP2_RACOUNT,
S_AXI_HP2_WACOUNT,
S_AXI_HP2_ACLK,
S_AXI_HP2_ARVALID,
S_AXI_HP2_AWVALID,
S_AXI_HP2_BREADY,
S_AXI_HP2_RDISSUECAP1_EN,
S_AXI_HP2_RREADY,
S_AXI_HP2_WLAST,
S_AXI_HP2_WRISSUECAP1_EN,
S_AXI_HP2_WVALID,
S_AXI_HP2_ARBURST,
S_AXI_HP2_ARLOCK,
S_AXI_HP2_ARSIZE,
S_AXI_HP2_AWBURST,
S_AXI_HP2_AWLOCK,
S_AXI_HP2_AWSIZE,
S_AXI_HP2_ARPROT,
S_AXI_HP2_AWPROT,
S_AXI_HP2_ARADDR,
S_AXI_HP2_AWADDR,
S_AXI_HP2_ARCACHE,
S_AXI_HP2_ARLEN,
S_AXI_HP2_ARQOS,
S_AXI_HP2_AWCACHE,
S_AXI_HP2_AWLEN,
S_AXI_HP2_AWQOS,
S_AXI_HP2_ARID,
S_AXI_HP2_AWID,
S_AXI_HP2_WID,
S_AXI_HP2_WDATA,
S_AXI_HP2_WSTRB,
S_AXI_HP3_ARESETN,
S_AXI_HP3_ARREADY,
S_AXI_HP3_AWREADY,
S_AXI_HP3_BVALID,
S_AXI_HP3_RLAST,
S_AXI_HP3_RVALID,
S_AXI_HP3_WREADY,
S_AXI_HP3_BRESP,
S_AXI_HP3_RRESP,
S_AXI_HP3_BID,
S_AXI_HP3_RID,
S_AXI_HP3_RDATA,
S_AXI_HP3_RCOUNT,
S_AXI_HP3_WCOUNT,
S_AXI_HP3_RACOUNT,
S_AXI_HP3_WACOUNT,
S_AXI_HP3_ACLK,
S_AXI_HP3_ARVALID,
S_AXI_HP3_AWVALID,
S_AXI_HP3_BREADY,
S_AXI_HP3_RDISSUECAP1_EN,
S_AXI_HP3_RREADY,
S_AXI_HP3_WLAST,
S_AXI_HP3_WRISSUECAP1_EN,
S_AXI_HP3_WVALID,
S_AXI_HP3_ARBURST,
S_AXI_HP3_ARLOCK,
S_AXI_HP3_ARSIZE,
S_AXI_HP3_AWBURST,
S_AXI_HP3_AWLOCK,
S_AXI_HP3_AWSIZE,
S_AXI_HP3_ARPROT,
S_AXI_HP3_AWPROT,
S_AXI_HP3_ARADDR,
S_AXI_HP3_AWADDR,
S_AXI_HP3_ARCACHE,
S_AXI_HP3_ARLEN,
S_AXI_HP3_ARQOS,
S_AXI_HP3_AWCACHE,
S_AXI_HP3_AWLEN,
S_AXI_HP3_AWQOS,
S_AXI_HP3_ARID,
S_AXI_HP3_AWID,
S_AXI_HP3_WID,
S_AXI_HP3_WDATA,
S_AXI_HP3_WSTRB,
IRQ_P2F_DMAC_ABORT,
IRQ_P2F_DMAC0,
IRQ_P2F_DMAC1,
IRQ_P2F_DMAC2,
IRQ_P2F_DMAC3,
IRQ_P2F_DMAC4,
IRQ_P2F_DMAC5,
IRQ_P2F_DMAC6,
IRQ_P2F_DMAC7,
IRQ_P2F_SMC,
IRQ_P2F_QSPI,
IRQ_P2F_CTI,
IRQ_P2F_GPIO,
IRQ_P2F_USB0,
IRQ_P2F_ENET0,
IRQ_P2F_ENET_WAKE0,
IRQ_P2F_SDIO0,
IRQ_P2F_I2C0,
IRQ_P2F_SPI0,
IRQ_P2F_UART0,
IRQ_P2F_CAN0,
IRQ_P2F_USB1,
IRQ_P2F_ENET1,
IRQ_P2F_ENET_WAKE1,
IRQ_P2F_SDIO1,
IRQ_P2F_I2C1,
IRQ_P2F_SPI1,
IRQ_P2F_UART1,
IRQ_P2F_CAN1,
IRQ_F2P,
Core0_nFIQ,
Core0_nIRQ,
Core1_nFIQ,
Core1_nIRQ,
DMA0_DATYPE,
DMA0_DAVALID,
DMA0_DRREADY,
DMA0_RSTN,
DMA1_DATYPE,
DMA1_DAVALID,
DMA1_DRREADY,
DMA1_RSTN,
DMA2_DATYPE,
DMA2_DAVALID,
DMA2_DRREADY,
DMA2_RSTN,
DMA3_DATYPE,
DMA3_DAVALID,
DMA3_DRREADY,
DMA3_RSTN,
DMA0_ACLK,
DMA0_DAREADY,
DMA0_DRLAST,
DMA0_DRVALID,
DMA1_ACLK,
DMA1_DAREADY,
DMA1_DRLAST,
DMA1_DRVALID,
DMA2_ACLK,
DMA2_DAREADY,
DMA2_DRLAST,
DMA2_DRVALID,
DMA3_ACLK,
DMA3_DAREADY,
DMA3_DRLAST,
DMA3_DRVALID,
DMA0_DRTYPE,
DMA1_DRTYPE,
DMA2_DRTYPE,
DMA3_DRTYPE,
FCLK_CLK3,
FCLK_CLK2,
FCLK_CLK1,
FCLK_CLK0,
FCLK_CLKTRIG3_N,
FCLK_CLKTRIG2_N,
FCLK_CLKTRIG1_N,
FCLK_CLKTRIG0_N,
FCLK_RESET3_N,
FCLK_RESET2_N,
FCLK_RESET1_N,
FCLK_RESET0_N,
FTMD_TRACEIN_DATA,
FTMD_TRACEIN_VALID,
FTMD_TRACEIN_CLK,
FTMD_TRACEIN_ATID,
FTMT_F2P_TRIG_0,
FTMT_F2P_TRIGACK_0,
FTMT_F2P_TRIG_1,
FTMT_F2P_TRIGACK_1,
FTMT_F2P_TRIG_2,
FTMT_F2P_TRIGACK_2,
FTMT_F2P_TRIG_3,
FTMT_F2P_TRIGACK_3,
FTMT_F2P_DEBUG,
FTMT_P2F_TRIGACK_0,
FTMT_P2F_TRIG_0,
FTMT_P2F_TRIGACK_1,
FTMT_P2F_TRIG_1,
FTMT_P2F_TRIGACK_2,
FTMT_P2F_TRIG_2,
FTMT_P2F_TRIGACK_3,
FTMT_P2F_TRIG_3,
FTMT_P2F_DEBUG,
FPGA_IDLE_N,
EVENT_EVENTO,
EVENT_STANDBYWFE,
EVENT_STANDBYWFI,
EVENT_EVENTI,
DDR_ARB,
MIO,
DDR_CAS_n,
DDR_CKE,
DDR_Clk_n,
DDR_Clk,
DDR_CS_n,
DDR_DRSTB,
DDR_ODT,
DDR_RAS_n,
DDR_WEB,
DDR_BankAddr,
DDR_Addr,
DDR_VRN,
DDR_VRP,
DDR_DM,
DDR_DQ,
DDR_DQS_n,
DDR_DQS,
PS_SRSTB,
PS_CLK,
PS_PORB);
output CAN0_PHY_TX;
input CAN0_PHY_RX;
output CAN1_PHY_TX;
input CAN1_PHY_RX;
output ENET0_GMII_TX_EN;
output ENET0_GMII_TX_ER;
output ENET0_MDIO_MDC;
output ENET0_MDIO_O;
output ENET0_MDIO_T;
output ENET0_PTP_DELAY_REQ_RX;
output ENET0_PTP_DELAY_REQ_TX;
output ENET0_PTP_PDELAY_REQ_RX;
output ENET0_PTP_PDELAY_REQ_TX;
output ENET0_PTP_PDELAY_RESP_RX;
output ENET0_PTP_PDELAY_RESP_TX;
output ENET0_PTP_SYNC_FRAME_RX;
output ENET0_PTP_SYNC_FRAME_TX;
output ENET0_SOF_RX;
output ENET0_SOF_TX;
output [7:0]ENET0_GMII_TXD;
input ENET0_GMII_COL;
input ENET0_GMII_CRS;
input ENET0_GMII_RX_CLK;
input ENET0_GMII_RX_DV;
input ENET0_GMII_RX_ER;
input ENET0_GMII_TX_CLK;
input ENET0_MDIO_I;
input ENET0_EXT_INTIN;
input [7:0]ENET0_GMII_RXD;
output ENET1_GMII_TX_EN;
output ENET1_GMII_TX_ER;
output ENET1_MDIO_MDC;
output ENET1_MDIO_O;
output ENET1_MDIO_T;
output ENET1_PTP_DELAY_REQ_RX;
output ENET1_PTP_DELAY_REQ_TX;
output ENET1_PTP_PDELAY_REQ_RX;
output ENET1_PTP_PDELAY_REQ_TX;
output ENET1_PTP_PDELAY_RESP_RX;
output ENET1_PTP_PDELAY_RESP_TX;
output ENET1_PTP_SYNC_FRAME_RX;
output ENET1_PTP_SYNC_FRAME_TX;
output ENET1_SOF_RX;
output ENET1_SOF_TX;
output [7:0]ENET1_GMII_TXD;
input ENET1_GMII_COL;
input ENET1_GMII_CRS;
input ENET1_GMII_RX_CLK;
input ENET1_GMII_RX_DV;
input ENET1_GMII_RX_ER;
input ENET1_GMII_TX_CLK;
input ENET1_MDIO_I;
input ENET1_EXT_INTIN;
input [7:0]ENET1_GMII_RXD;
input [63:0]GPIO_I;
output [63:0]GPIO_O;
output [63:0]GPIO_T;
input I2C0_SDA_I;
output I2C0_SDA_O;
output I2C0_SDA_T;
input I2C0_SCL_I;
output I2C0_SCL_O;
output I2C0_SCL_T;
input I2C1_SDA_I;
output I2C1_SDA_O;
output I2C1_SDA_T;
input I2C1_SCL_I;
output I2C1_SCL_O;
output I2C1_SCL_T;
input PJTAG_TCK;
input PJTAG_TMS;
input PJTAG_TDI;
output PJTAG_TDO;
output SDIO0_CLK;
input SDIO0_CLK_FB;
output SDIO0_CMD_O;
input SDIO0_CMD_I;
output SDIO0_CMD_T;
input [3:0]SDIO0_DATA_I;
output [3:0]SDIO0_DATA_O;
output [3:0]SDIO0_DATA_T;
output SDIO0_LED;
input SDIO0_CDN;
input SDIO0_WP;
output SDIO0_BUSPOW;
output [2:0]SDIO0_BUSVOLT;
output SDIO1_CLK;
input SDIO1_CLK_FB;
output SDIO1_CMD_O;
input SDIO1_CMD_I;
output SDIO1_CMD_T;
input [3:0]SDIO1_DATA_I;
output [3:0]SDIO1_DATA_O;
output [3:0]SDIO1_DATA_T;
output SDIO1_LED;
input SDIO1_CDN;
input SDIO1_WP;
output SDIO1_BUSPOW;
output [2:0]SDIO1_BUSVOLT;
input SPI0_SCLK_I;
output SPI0_SCLK_O;
output SPI0_SCLK_T;
input SPI0_MOSI_I;
output SPI0_MOSI_O;
output SPI0_MOSI_T;
input SPI0_MISO_I;
output SPI0_MISO_O;
output SPI0_MISO_T;
input SPI0_SS_I;
output SPI0_SS_O;
output SPI0_SS1_O;
output SPI0_SS2_O;
output SPI0_SS_T;
input SPI1_SCLK_I;
output SPI1_SCLK_O;
output SPI1_SCLK_T;
input SPI1_MOSI_I;
output SPI1_MOSI_O;
output SPI1_MOSI_T;
input SPI1_MISO_I;
output SPI1_MISO_O;
output SPI1_MISO_T;
input SPI1_SS_I;
output SPI1_SS_O;
output SPI1_SS1_O;
output SPI1_SS2_O;
output SPI1_SS_T;
output UART0_DTRN;
output UART0_RTSN;
output UART0_TX;
input UART0_CTSN;
input UART0_DCDN;
input UART0_DSRN;
input UART0_RIN;
input UART0_RX;
output UART1_DTRN;
output UART1_RTSN;
output UART1_TX;
input UART1_CTSN;
input UART1_DCDN;
input UART1_DSRN;
input UART1_RIN;
input UART1_RX;
output TTC0_WAVE0_OUT;
output TTC0_WAVE1_OUT;
output TTC0_WAVE2_OUT;
input TTC0_CLK0_IN;
input TTC0_CLK1_IN;
input TTC0_CLK2_IN;
output TTC1_WAVE0_OUT;
output TTC1_WAVE1_OUT;
output TTC1_WAVE2_OUT;
input TTC1_CLK0_IN;
input TTC1_CLK1_IN;
input TTC1_CLK2_IN;
input WDT_CLK_IN;
output WDT_RST_OUT;
input TRACE_CLK;
output TRACE_CTL;
output [1:0]TRACE_DATA;
output TRACE_CLK_OUT;
output [1:0]USB0_PORT_INDCTL;
output USB0_VBUS_PWRSELECT;
input USB0_VBUS_PWRFAULT;
output [1:0]USB1_PORT_INDCTL;
output USB1_VBUS_PWRSELECT;
input USB1_VBUS_PWRFAULT;
input SRAM_INTIN;
output M_AXI_GP0_ARESETN;
output M_AXI_GP0_ARVALID;
output M_AXI_GP0_AWVALID;
output M_AXI_GP0_BREADY;
output M_AXI_GP0_RREADY;
output M_AXI_GP0_WLAST;
output M_AXI_GP0_WVALID;
output [11:0]M_AXI_GP0_ARID;
output [11:0]M_AXI_GP0_AWID;
output [11:0]M_AXI_GP0_WID;
output [1:0]M_AXI_GP0_ARBURST;
output [1:0]M_AXI_GP0_ARLOCK;
output [2:0]M_AXI_GP0_ARSIZE;
output [1:0]M_AXI_GP0_AWBURST;
output [1:0]M_AXI_GP0_AWLOCK;
output [2:0]M_AXI_GP0_AWSIZE;
output [2:0]M_AXI_GP0_ARPROT;
output [2:0]M_AXI_GP0_AWPROT;
output [31:0]M_AXI_GP0_ARADDR;
output [31:0]M_AXI_GP0_AWADDR;
output [31:0]M_AXI_GP0_WDATA;
output [3:0]M_AXI_GP0_ARCACHE;
output [3:0]M_AXI_GP0_ARLEN;
output [3:0]M_AXI_GP0_ARQOS;
output [3:0]M_AXI_GP0_AWCACHE;
output [3:0]M_AXI_GP0_AWLEN;
output [3:0]M_AXI_GP0_AWQOS;
output [3:0]M_AXI_GP0_WSTRB;
input M_AXI_GP0_ACLK;
input M_AXI_GP0_ARREADY;
input M_AXI_GP0_AWREADY;
input M_AXI_GP0_BVALID;
input M_AXI_GP0_RLAST;
input M_AXI_GP0_RVALID;
input M_AXI_GP0_WREADY;
input [11:0]M_AXI_GP0_BID;
input [11:0]M_AXI_GP0_RID;
input [1:0]M_AXI_GP0_BRESP;
input [1:0]M_AXI_GP0_RRESP;
input [31:0]M_AXI_GP0_RDATA;
output M_AXI_GP1_ARESETN;
output M_AXI_GP1_ARVALID;
output M_AXI_GP1_AWVALID;
output M_AXI_GP1_BREADY;
output M_AXI_GP1_RREADY;
output M_AXI_GP1_WLAST;
output M_AXI_GP1_WVALID;
output [11:0]M_AXI_GP1_ARID;
output [11:0]M_AXI_GP1_AWID;
output [11:0]M_AXI_GP1_WID;
output [1:0]M_AXI_GP1_ARBURST;
output [1:0]M_AXI_GP1_ARLOCK;
output [2:0]M_AXI_GP1_ARSIZE;
output [1:0]M_AXI_GP1_AWBURST;
output [1:0]M_AXI_GP1_AWLOCK;
output [2:0]M_AXI_GP1_AWSIZE;
output [2:0]M_AXI_GP1_ARPROT;
output [2:0]M_AXI_GP1_AWPROT;
output [31:0]M_AXI_GP1_ARADDR;
output [31:0]M_AXI_GP1_AWADDR;
output [31:0]M_AXI_GP1_WDATA;
output [3:0]M_AXI_GP1_ARCACHE;
output [3:0]M_AXI_GP1_ARLEN;
output [3:0]M_AXI_GP1_ARQOS;
output [3:0]M_AXI_GP1_AWCACHE;
output [3:0]M_AXI_GP1_AWLEN;
output [3:0]M_AXI_GP1_AWQOS;
output [3:0]M_AXI_GP1_WSTRB;
input M_AXI_GP1_ACLK;
input M_AXI_GP1_ARREADY;
input M_AXI_GP1_AWREADY;
input M_AXI_GP1_BVALID;
input M_AXI_GP1_RLAST;
input M_AXI_GP1_RVALID;
input M_AXI_GP1_WREADY;
input [11:0]M_AXI_GP1_BID;
input [11:0]M_AXI_GP1_RID;
input [1:0]M_AXI_GP1_BRESP;
input [1:0]M_AXI_GP1_RRESP;
input [31:0]M_AXI_GP1_RDATA;
output S_AXI_GP0_ARESETN;
output S_AXI_GP0_ARREADY;
output S_AXI_GP0_AWREADY;
output S_AXI_GP0_BVALID;
output S_AXI_GP0_RLAST;
output S_AXI_GP0_RVALID;
output S_AXI_GP0_WREADY;
output [1:0]S_AXI_GP0_BRESP;
output [1:0]S_AXI_GP0_RRESP;
output [31:0]S_AXI_GP0_RDATA;
output [5:0]S_AXI_GP0_BID;
output [5:0]S_AXI_GP0_RID;
input S_AXI_GP0_ACLK;
input S_AXI_GP0_ARVALID;
input S_AXI_GP0_AWVALID;
input S_AXI_GP0_BREADY;
input S_AXI_GP0_RREADY;
input S_AXI_GP0_WLAST;
input S_AXI_GP0_WVALID;
input [1:0]S_AXI_GP0_ARBURST;
input [1:0]S_AXI_GP0_ARLOCK;
input [2:0]S_AXI_GP0_ARSIZE;
input [1:0]S_AXI_GP0_AWBURST;
input [1:0]S_AXI_GP0_AWLOCK;
input [2:0]S_AXI_GP0_AWSIZE;
input [2:0]S_AXI_GP0_ARPROT;
input [2:0]S_AXI_GP0_AWPROT;
input [31:0]S_AXI_GP0_ARADDR;
input [31:0]S_AXI_GP0_AWADDR;
input [31:0]S_AXI_GP0_WDATA;
input [3:0]S_AXI_GP0_ARCACHE;
input [3:0]S_AXI_GP0_ARLEN;
input [3:0]S_AXI_GP0_ARQOS;
input [3:0]S_AXI_GP0_AWCACHE;
input [3:0]S_AXI_GP0_AWLEN;
input [3:0]S_AXI_GP0_AWQOS;
input [3:0]S_AXI_GP0_WSTRB;
input [5:0]S_AXI_GP0_ARID;
input [5:0]S_AXI_GP0_AWID;
input [5:0]S_AXI_GP0_WID;
output S_AXI_GP1_ARESETN;
output S_AXI_GP1_ARREADY;
output S_AXI_GP1_AWREADY;
output S_AXI_GP1_BVALID;
output S_AXI_GP1_RLAST;
output S_AXI_GP1_RVALID;
output S_AXI_GP1_WREADY;
output [1:0]S_AXI_GP1_BRESP;
output [1:0]S_AXI_GP1_RRESP;
output [31:0]S_AXI_GP1_RDATA;
output [5:0]S_AXI_GP1_BID;
output [5:0]S_AXI_GP1_RID;
input S_AXI_GP1_ACLK;
input S_AXI_GP1_ARVALID;
input S_AXI_GP1_AWVALID;
input S_AXI_GP1_BREADY;
input S_AXI_GP1_RREADY;
input S_AXI_GP1_WLAST;
input S_AXI_GP1_WVALID;
input [1:0]S_AXI_GP1_ARBURST;
input [1:0]S_AXI_GP1_ARLOCK;
input [2:0]S_AXI_GP1_ARSIZE;
input [1:0]S_AXI_GP1_AWBURST;
input [1:0]S_AXI_GP1_AWLOCK;
input [2:0]S_AXI_GP1_AWSIZE;
input [2:0]S_AXI_GP1_ARPROT;
input [2:0]S_AXI_GP1_AWPROT;
input [31:0]S_AXI_GP1_ARADDR;
input [31:0]S_AXI_GP1_AWADDR;
input [31:0]S_AXI_GP1_WDATA;
input [3:0]S_AXI_GP1_ARCACHE;
input [3:0]S_AXI_GP1_ARLEN;
input [3:0]S_AXI_GP1_ARQOS;
input [3:0]S_AXI_GP1_AWCACHE;
input [3:0]S_AXI_GP1_AWLEN;
input [3:0]S_AXI_GP1_AWQOS;
input [3:0]S_AXI_GP1_WSTRB;
input [5:0]S_AXI_GP1_ARID;
input [5:0]S_AXI_GP1_AWID;
input [5:0]S_AXI_GP1_WID;
output S_AXI_ACP_ARESETN;
output S_AXI_ACP_ARREADY;
output S_AXI_ACP_AWREADY;
output S_AXI_ACP_BVALID;
output S_AXI_ACP_RLAST;
output S_AXI_ACP_RVALID;
output S_AXI_ACP_WREADY;
output [1:0]S_AXI_ACP_BRESP;
output [1:0]S_AXI_ACP_RRESP;
output [2:0]S_AXI_ACP_BID;
output [2:0]S_AXI_ACP_RID;
output [63:0]S_AXI_ACP_RDATA;
input S_AXI_ACP_ACLK;
input S_AXI_ACP_ARVALID;
input S_AXI_ACP_AWVALID;
input S_AXI_ACP_BREADY;
input S_AXI_ACP_RREADY;
input S_AXI_ACP_WLAST;
input S_AXI_ACP_WVALID;
input [2:0]S_AXI_ACP_ARID;
input [2:0]S_AXI_ACP_ARPROT;
input [2:0]S_AXI_ACP_AWID;
input [2:0]S_AXI_ACP_AWPROT;
input [2:0]S_AXI_ACP_WID;
input [31:0]S_AXI_ACP_ARADDR;
input [31:0]S_AXI_ACP_AWADDR;
input [3:0]S_AXI_ACP_ARCACHE;
input [3:0]S_AXI_ACP_ARLEN;
input [3:0]S_AXI_ACP_ARQOS;
input [3:0]S_AXI_ACP_AWCACHE;
input [3:0]S_AXI_ACP_AWLEN;
input [3:0]S_AXI_ACP_AWQOS;
input [1:0]S_AXI_ACP_ARBURST;
input [1:0]S_AXI_ACP_ARLOCK;
input [2:0]S_AXI_ACP_ARSIZE;
input [1:0]S_AXI_ACP_AWBURST;
input [1:0]S_AXI_ACP_AWLOCK;
input [2:0]S_AXI_ACP_AWSIZE;
input [4:0]S_AXI_ACP_ARUSER;
input [4:0]S_AXI_ACP_AWUSER;
input [63:0]S_AXI_ACP_WDATA;
input [7:0]S_AXI_ACP_WSTRB;
output S_AXI_HP0_ARESETN;
output S_AXI_HP0_ARREADY;
output S_AXI_HP0_AWREADY;
output S_AXI_HP0_BVALID;
output S_AXI_HP0_RLAST;
output S_AXI_HP0_RVALID;
output S_AXI_HP0_WREADY;
output [1:0]S_AXI_HP0_BRESP;
output [1:0]S_AXI_HP0_RRESP;
output [5:0]S_AXI_HP0_BID;
output [5:0]S_AXI_HP0_RID;
output [63:0]S_AXI_HP0_RDATA;
output [7:0]S_AXI_HP0_RCOUNT;
output [7:0]S_AXI_HP0_WCOUNT;
output [2:0]S_AXI_HP0_RACOUNT;
output [5:0]S_AXI_HP0_WACOUNT;
input S_AXI_HP0_ACLK;
input S_AXI_HP0_ARVALID;
input S_AXI_HP0_AWVALID;
input S_AXI_HP0_BREADY;
input S_AXI_HP0_RDISSUECAP1_EN;
input S_AXI_HP0_RREADY;
input S_AXI_HP0_WLAST;
input S_AXI_HP0_WRISSUECAP1_EN;
input S_AXI_HP0_WVALID;
input [1:0]S_AXI_HP0_ARBURST;
input [1:0]S_AXI_HP0_ARLOCK;
input [2:0]S_AXI_HP0_ARSIZE;
input [1:0]S_AXI_HP0_AWBURST;
input [1:0]S_AXI_HP0_AWLOCK;
input [2:0]S_AXI_HP0_AWSIZE;
input [2:0]S_AXI_HP0_ARPROT;
input [2:0]S_AXI_HP0_AWPROT;
input [31:0]S_AXI_HP0_ARADDR;
input [31:0]S_AXI_HP0_AWADDR;
input [3:0]S_AXI_HP0_ARCACHE;
input [3:0]S_AXI_HP0_ARLEN;
input [3:0]S_AXI_HP0_ARQOS;
input [3:0]S_AXI_HP0_AWCACHE;
input [3:0]S_AXI_HP0_AWLEN;
input [3:0]S_AXI_HP0_AWQOS;
input [5:0]S_AXI_HP0_ARID;
input [5:0]S_AXI_HP0_AWID;
input [5:0]S_AXI_HP0_WID;
input [63:0]S_AXI_HP0_WDATA;
input [7:0]S_AXI_HP0_WSTRB;
output S_AXI_HP1_ARESETN;
output S_AXI_HP1_ARREADY;
output S_AXI_HP1_AWREADY;
output S_AXI_HP1_BVALID;
output S_AXI_HP1_RLAST;
output S_AXI_HP1_RVALID;
output S_AXI_HP1_WREADY;
output [1:0]S_AXI_HP1_BRESP;
output [1:0]S_AXI_HP1_RRESP;
output [5:0]S_AXI_HP1_BID;
output [5:0]S_AXI_HP1_RID;
output [63:0]S_AXI_HP1_RDATA;
output [7:0]S_AXI_HP1_RCOUNT;
output [7:0]S_AXI_HP1_WCOUNT;
output [2:0]S_AXI_HP1_RACOUNT;
output [5:0]S_AXI_HP1_WACOUNT;
input S_AXI_HP1_ACLK;
input S_AXI_HP1_ARVALID;
input S_AXI_HP1_AWVALID;
input S_AXI_HP1_BREADY;
input S_AXI_HP1_RDISSUECAP1_EN;
input S_AXI_HP1_RREADY;
input S_AXI_HP1_WLAST;
input S_AXI_HP1_WRISSUECAP1_EN;
input S_AXI_HP1_WVALID;
input [1:0]S_AXI_HP1_ARBURST;
input [1:0]S_AXI_HP1_ARLOCK;
input [2:0]S_AXI_HP1_ARSIZE;
input [1:0]S_AXI_HP1_AWBURST;
input [1:0]S_AXI_HP1_AWLOCK;
input [2:0]S_AXI_HP1_AWSIZE;
input [2:0]S_AXI_HP1_ARPROT;
input [2:0]S_AXI_HP1_AWPROT;
input [31:0]S_AXI_HP1_ARADDR;
input [31:0]S_AXI_HP1_AWADDR;
input [3:0]S_AXI_HP1_ARCACHE;
input [3:0]S_AXI_HP1_ARLEN;
input [3:0]S_AXI_HP1_ARQOS;
input [3:0]S_AXI_HP1_AWCACHE;
input [3:0]S_AXI_HP1_AWLEN;
input [3:0]S_AXI_HP1_AWQOS;
input [5:0]S_AXI_HP1_ARID;
input [5:0]S_AXI_HP1_AWID;
input [5:0]S_AXI_HP1_WID;
input [63:0]S_AXI_HP1_WDATA;
input [7:0]S_AXI_HP1_WSTRB;
output S_AXI_HP2_ARESETN;
output S_AXI_HP2_ARREADY;
output S_AXI_HP2_AWREADY;
output S_AXI_HP2_BVALID;
output S_AXI_HP2_RLAST;
output S_AXI_HP2_RVALID;
output S_AXI_HP2_WREADY;
output [1:0]S_AXI_HP2_BRESP;
output [1:0]S_AXI_HP2_RRESP;
output [5:0]S_AXI_HP2_BID;
output [5:0]S_AXI_HP2_RID;
output [63:0]S_AXI_HP2_RDATA;
output [7:0]S_AXI_HP2_RCOUNT;
output [7:0]S_AXI_HP2_WCOUNT;
output [2:0]S_AXI_HP2_RACOUNT;
output [5:0]S_AXI_HP2_WACOUNT;
input S_AXI_HP2_ACLK;
input S_AXI_HP2_ARVALID;
input S_AXI_HP2_AWVALID;
input S_AXI_HP2_BREADY;
input S_AXI_HP2_RDISSUECAP1_EN;
input S_AXI_HP2_RREADY;
input S_AXI_HP2_WLAST;
input S_AXI_HP2_WRISSUECAP1_EN;
input S_AXI_HP2_WVALID;
input [1:0]S_AXI_HP2_ARBURST;
input [1:0]S_AXI_HP2_ARLOCK;
input [2:0]S_AXI_HP2_ARSIZE;
input [1:0]S_AXI_HP2_AWBURST;
input [1:0]S_AXI_HP2_AWLOCK;
input [2:0]S_AXI_HP2_AWSIZE;
input [2:0]S_AXI_HP2_ARPROT;
input [2:0]S_AXI_HP2_AWPROT;
input [31:0]S_AXI_HP2_ARADDR;
input [31:0]S_AXI_HP2_AWADDR;
input [3:0]S_AXI_HP2_ARCACHE;
input [3:0]S_AXI_HP2_ARLEN;
input [3:0]S_AXI_HP2_ARQOS;
input [3:0]S_AXI_HP2_AWCACHE;
input [3:0]S_AXI_HP2_AWLEN;
input [3:0]S_AXI_HP2_AWQOS;
input [5:0]S_AXI_HP2_ARID;
input [5:0]S_AXI_HP2_AWID;
input [5:0]S_AXI_HP2_WID;
input [63:0]S_AXI_HP2_WDATA;
input [7:0]S_AXI_HP2_WSTRB;
output S_AXI_HP3_ARESETN;
output S_AXI_HP3_ARREADY;
output S_AXI_HP3_AWREADY;
output S_AXI_HP3_BVALID;
output S_AXI_HP3_RLAST;
output S_AXI_HP3_RVALID;
output S_AXI_HP3_WREADY;
output [1:0]S_AXI_HP3_BRESP;
output [1:0]S_AXI_HP3_RRESP;
output [5:0]S_AXI_HP3_BID;
output [5:0]S_AXI_HP3_RID;
output [63:0]S_AXI_HP3_RDATA;
output [7:0]S_AXI_HP3_RCOUNT;
output [7:0]S_AXI_HP3_WCOUNT;
output [2:0]S_AXI_HP3_RACOUNT;
output [5:0]S_AXI_HP3_WACOUNT;
input S_AXI_HP3_ACLK;
input S_AXI_HP3_ARVALID;
input S_AXI_HP3_AWVALID;
input S_AXI_HP3_BREADY;
input S_AXI_HP3_RDISSUECAP1_EN;
input S_AXI_HP3_RREADY;
input S_AXI_HP3_WLAST;
input S_AXI_HP3_WRISSUECAP1_EN;
input S_AXI_HP3_WVALID;
input [1:0]S_AXI_HP3_ARBURST;
input [1:0]S_AXI_HP3_ARLOCK;
input [2:0]S_AXI_HP3_ARSIZE;
input [1:0]S_AXI_HP3_AWBURST;
input [1:0]S_AXI_HP3_AWLOCK;
input [2:0]S_AXI_HP3_AWSIZE;
input [2:0]S_AXI_HP3_ARPROT;
input [2:0]S_AXI_HP3_AWPROT;
input [31:0]S_AXI_HP3_ARADDR;
input [31:0]S_AXI_HP3_AWADDR;
input [3:0]S_AXI_HP3_ARCACHE;
input [3:0]S_AXI_HP3_ARLEN;
input [3:0]S_AXI_HP3_ARQOS;
input [3:0]S_AXI_HP3_AWCACHE;
input [3:0]S_AXI_HP3_AWLEN;
input [3:0]S_AXI_HP3_AWQOS;
input [5:0]S_AXI_HP3_ARID;
input [5:0]S_AXI_HP3_AWID;
input [5:0]S_AXI_HP3_WID;
input [63:0]S_AXI_HP3_WDATA;
input [7:0]S_AXI_HP3_WSTRB;
output IRQ_P2F_DMAC_ABORT;
output IRQ_P2F_DMAC0;
output IRQ_P2F_DMAC1;
output IRQ_P2F_DMAC2;
output IRQ_P2F_DMAC3;
output IRQ_P2F_DMAC4;
output IRQ_P2F_DMAC5;
output IRQ_P2F_DMAC6;
output IRQ_P2F_DMAC7;
output IRQ_P2F_SMC;
output IRQ_P2F_QSPI;
output IRQ_P2F_CTI;
output IRQ_P2F_GPIO;
output IRQ_P2F_USB0;
output IRQ_P2F_ENET0;
output IRQ_P2F_ENET_WAKE0;
output IRQ_P2F_SDIO0;
output IRQ_P2F_I2C0;
output IRQ_P2F_SPI0;
output IRQ_P2F_UART0;
output IRQ_P2F_CAN0;
output IRQ_P2F_USB1;
output IRQ_P2F_ENET1;
output IRQ_P2F_ENET_WAKE1;
output IRQ_P2F_SDIO1;
output IRQ_P2F_I2C1;
output IRQ_P2F_SPI1;
output IRQ_P2F_UART1;
output IRQ_P2F_CAN1;
input [1:0]IRQ_F2P;
input Core0_nFIQ;
input Core0_nIRQ;
input Core1_nFIQ;
input Core1_nIRQ;
output [1:0]DMA0_DATYPE;
output DMA0_DAVALID;
output DMA0_DRREADY;
output DMA0_RSTN;
output [1:0]DMA1_DATYPE;
output DMA1_DAVALID;
output DMA1_DRREADY;
output DMA1_RSTN;
output [1:0]DMA2_DATYPE;
output DMA2_DAVALID;
output DMA2_DRREADY;
output DMA2_RSTN;
output [1:0]DMA3_DATYPE;
output DMA3_DAVALID;
output DMA3_DRREADY;
output DMA3_RSTN;
input DMA0_ACLK;
input DMA0_DAREADY;
input DMA0_DRLAST;
input DMA0_DRVALID;
input DMA1_ACLK;
input DMA1_DAREADY;
input DMA1_DRLAST;
input DMA1_DRVALID;
input DMA2_ACLK;
input DMA2_DAREADY;
input DMA2_DRLAST;
input DMA2_DRVALID;
input DMA3_ACLK;
input DMA3_DAREADY;
input DMA3_DRLAST;
input DMA3_DRVALID;
input [1:0]DMA0_DRTYPE;
input [1:0]DMA1_DRTYPE;
input [1:0]DMA2_DRTYPE;
input [1:0]DMA3_DRTYPE;
output FCLK_CLK3;
output FCLK_CLK2;
output FCLK_CLK1;
output FCLK_CLK0;
input FCLK_CLKTRIG3_N;
input FCLK_CLKTRIG2_N;
input FCLK_CLKTRIG1_N;
input FCLK_CLKTRIG0_N;
output FCLK_RESET3_N;
output FCLK_RESET2_N;
output FCLK_RESET1_N;
output FCLK_RESET0_N;
input [31:0]FTMD_TRACEIN_DATA;
input FTMD_TRACEIN_VALID;
input FTMD_TRACEIN_CLK;
input [3:0]FTMD_TRACEIN_ATID;
input FTMT_F2P_TRIG_0;
output FTMT_F2P_TRIGACK_0;
input FTMT_F2P_TRIG_1;
output FTMT_F2P_TRIGACK_1;
input FTMT_F2P_TRIG_2;
output FTMT_F2P_TRIGACK_2;
input FTMT_F2P_TRIG_3;
output FTMT_F2P_TRIGACK_3;
input [31:0]FTMT_F2P_DEBUG;
input FTMT_P2F_TRIGACK_0;
output FTMT_P2F_TRIG_0;
input FTMT_P2F_TRIGACK_1;
output FTMT_P2F_TRIG_1;
input FTMT_P2F_TRIGACK_2;
output FTMT_P2F_TRIG_2;
input FTMT_P2F_TRIGACK_3;
output FTMT_P2F_TRIG_3;
output [31:0]FTMT_P2F_DEBUG;
input FPGA_IDLE_N;
output EVENT_EVENTO;
output [1:0]EVENT_STANDBYWFE;
output [1:0]EVENT_STANDBYWFI;
input EVENT_EVENTI;
input [3:0]DDR_ARB;
inout [53:0]MIO;
inout DDR_CAS_n;
inout DDR_CKE;
inout DDR_Clk_n;
inout DDR_Clk;
inout DDR_CS_n;
inout DDR_DRSTB;
inout DDR_ODT;
inout DDR_RAS_n;
inout DDR_WEB;
inout [2:0]DDR_BankAddr;
inout [14:0]DDR_Addr;
inout DDR_VRN;
inout DDR_VRP;
inout [3:0]DDR_DM;
inout [31:0]DDR_DQ;
inout [3:0]DDR_DQS_n;
inout [3:0]DDR_DQS;
inout PS_SRSTB;
inout PS_CLK;
inout PS_PORB;
wire \<const0> ;
wire \<const1> ;
wire CAN0_PHY_RX;
wire CAN0_PHY_TX;
wire CAN1_PHY_RX;
wire CAN1_PHY_TX;
wire Core0_nFIQ;
wire Core0_nIRQ;
wire Core1_nFIQ;
wire Core1_nIRQ;
wire [3:0]DDR_ARB;
wire [14:0]DDR_Addr;
wire [2:0]DDR_BankAddr;
wire DDR_CAS_n;
wire DDR_CKE;
wire DDR_CS_n;
wire DDR_Clk;
wire DDR_Clk_n;
wire [3:0]DDR_DM;
wire [31:0]DDR_DQ;
wire [3:0]DDR_DQS;
wire [3:0]DDR_DQS_n;
wire DDR_DRSTB;
wire DDR_ODT;
wire DDR_RAS_n;
wire DDR_VRN;
wire DDR_VRP;
wire DDR_WEB;
wire DMA0_ACLK;
wire DMA0_DAREADY;
wire [1:0]DMA0_DATYPE;
wire DMA0_DAVALID;
wire DMA0_DRLAST;
wire DMA0_DRREADY;
wire [1:0]DMA0_DRTYPE;
wire DMA0_DRVALID;
wire DMA0_RSTN;
wire DMA1_ACLK;
wire DMA1_DAREADY;
wire [1:0]DMA1_DATYPE;
wire DMA1_DAVALID;
wire DMA1_DRLAST;
wire DMA1_DRREADY;
wire [1:0]DMA1_DRTYPE;
wire DMA1_DRVALID;
wire DMA1_RSTN;
wire DMA2_ACLK;
wire DMA2_DAREADY;
wire [1:0]DMA2_DATYPE;
wire DMA2_DAVALID;
wire DMA2_DRLAST;
wire DMA2_DRREADY;
wire [1:0]DMA2_DRTYPE;
wire DMA2_DRVALID;
wire DMA2_RSTN;
wire DMA3_ACLK;
wire DMA3_DAREADY;
wire [1:0]DMA3_DATYPE;
wire DMA3_DAVALID;
wire DMA3_DRLAST;
wire DMA3_DRREADY;
wire [1:0]DMA3_DRTYPE;
wire DMA3_DRVALID;
wire DMA3_RSTN;
wire ENET0_EXT_INTIN;
wire ENET0_GMII_RX_CLK;
wire ENET0_GMII_TX_CLK;
wire ENET0_MDIO_I;
wire ENET0_MDIO_MDC;
wire ENET0_MDIO_O;
wire ENET0_MDIO_T;
wire ENET0_MDIO_T_n;
wire ENET0_PTP_DELAY_REQ_RX;
wire ENET0_PTP_DELAY_REQ_TX;
wire ENET0_PTP_PDELAY_REQ_RX;
wire ENET0_PTP_PDELAY_REQ_TX;
wire ENET0_PTP_PDELAY_RESP_RX;
wire ENET0_PTP_PDELAY_RESP_TX;
wire ENET0_PTP_SYNC_FRAME_RX;
wire ENET0_PTP_SYNC_FRAME_TX;
wire ENET0_SOF_RX;
wire ENET0_SOF_TX;
wire ENET1_EXT_INTIN;
wire ENET1_GMII_RX_CLK;
wire ENET1_GMII_TX_CLK;
wire ENET1_MDIO_I;
wire ENET1_MDIO_MDC;
wire ENET1_MDIO_O;
wire ENET1_MDIO_T;
wire ENET1_MDIO_T_n;
wire ENET1_PTP_DELAY_REQ_RX;
wire ENET1_PTP_DELAY_REQ_TX;
wire ENET1_PTP_PDELAY_REQ_RX;
wire ENET1_PTP_PDELAY_REQ_TX;
wire ENET1_PTP_PDELAY_RESP_RX;
wire ENET1_PTP_PDELAY_RESP_TX;
wire ENET1_PTP_SYNC_FRAME_RX;
wire ENET1_PTP_SYNC_FRAME_TX;
wire ENET1_SOF_RX;
wire ENET1_SOF_TX;
wire EVENT_EVENTI;
wire EVENT_EVENTO;
wire [1:0]EVENT_STANDBYWFE;
wire [1:0]EVENT_STANDBYWFI;
wire FCLK_CLK0;
wire FCLK_CLK1;
wire FCLK_CLK2;
wire FCLK_CLK3;
wire [0:0]FCLK_CLK_unbuffered;
wire FCLK_RESET0_N;
wire FCLK_RESET1_N;
wire FCLK_RESET2_N;
wire FCLK_RESET3_N;
wire FPGA_IDLE_N;
wire FTMD_TRACEIN_CLK;
wire [31:0]FTMT_F2P_DEBUG;
wire FTMT_F2P_TRIGACK_0;
wire FTMT_F2P_TRIGACK_1;
wire FTMT_F2P_TRIGACK_2;
wire FTMT_F2P_TRIGACK_3;
wire FTMT_F2P_TRIG_0;
wire FTMT_F2P_TRIG_1;
wire FTMT_F2P_TRIG_2;
wire FTMT_F2P_TRIG_3;
wire [31:0]FTMT_P2F_DEBUG;
wire FTMT_P2F_TRIGACK_0;
wire FTMT_P2F_TRIGACK_1;
wire FTMT_P2F_TRIGACK_2;
wire FTMT_P2F_TRIGACK_3;
wire FTMT_P2F_TRIG_0;
wire FTMT_P2F_TRIG_1;
wire FTMT_P2F_TRIG_2;
wire FTMT_P2F_TRIG_3;
wire [63:0]GPIO_I;
wire [63:0]GPIO_O;
wire [63:0]GPIO_T;
wire I2C0_SCL_I;
wire I2C0_SCL_O;
wire I2C0_SCL_T;
wire I2C0_SCL_T_n;
wire I2C0_SDA_I;
wire I2C0_SDA_O;
wire I2C0_SDA_T;
wire I2C0_SDA_T_n;
wire I2C1_SCL_I;
wire I2C1_SCL_O;
wire I2C1_SCL_T;
wire I2C1_SCL_T_n;
wire I2C1_SDA_I;
wire I2C1_SDA_O;
wire I2C1_SDA_T;
wire I2C1_SDA_T_n;
wire [1:0]IRQ_F2P;
wire IRQ_P2F_CAN0;
wire IRQ_P2F_CAN1;
wire IRQ_P2F_CTI;
wire IRQ_P2F_DMAC0;
wire IRQ_P2F_DMAC1;
wire IRQ_P2F_DMAC2;
wire IRQ_P2F_DMAC3;
wire IRQ_P2F_DMAC4;
wire IRQ_P2F_DMAC5;
wire IRQ_P2F_DMAC6;
wire IRQ_P2F_DMAC7;
wire IRQ_P2F_DMAC_ABORT;
wire IRQ_P2F_ENET0;
wire IRQ_P2F_ENET1;
wire IRQ_P2F_ENET_WAKE0;
wire IRQ_P2F_ENET_WAKE1;
wire IRQ_P2F_GPIO;
wire IRQ_P2F_I2C0;
wire IRQ_P2F_I2C1;
wire IRQ_P2F_QSPI;
wire IRQ_P2F_SDIO0;
wire IRQ_P2F_SDIO1;
wire IRQ_P2F_SMC;
wire IRQ_P2F_SPI0;
wire IRQ_P2F_SPI1;
wire IRQ_P2F_UART0;
wire IRQ_P2F_UART1;
wire IRQ_P2F_USB0;
wire IRQ_P2F_USB1;
wire [53:0]MIO;
wire M_AXI_GP0_ACLK;
wire [31:0]M_AXI_GP0_ARADDR;
wire [1:0]M_AXI_GP0_ARBURST;
wire [3:0]\^M_AXI_GP0_ARCACHE ;
wire M_AXI_GP0_ARESETN;
wire [11:0]M_AXI_GP0_ARID;
wire [3:0]M_AXI_GP0_ARLEN;
wire [1:0]M_AXI_GP0_ARLOCK;
wire [2:0]M_AXI_GP0_ARPROT;
wire [3:0]M_AXI_GP0_ARQOS;
wire M_AXI_GP0_ARREADY;
wire [1:0]\^M_AXI_GP0_ARSIZE ;
wire M_AXI_GP0_ARVALID;
wire [31:0]M_AXI_GP0_AWADDR;
wire [1:0]M_AXI_GP0_AWBURST;
wire [3:0]\^M_AXI_GP0_AWCACHE ;
wire [11:0]M_AXI_GP0_AWID;
wire [3:0]M_AXI_GP0_AWLEN;
wire [1:0]M_AXI_GP0_AWLOCK;
wire [2:0]M_AXI_GP0_AWPROT;
wire [3:0]M_AXI_GP0_AWQOS;
wire M_AXI_GP0_AWREADY;
wire [1:0]\^M_AXI_GP0_AWSIZE ;
wire M_AXI_GP0_AWVALID;
wire [11:0]M_AXI_GP0_BID;
wire M_AXI_GP0_BREADY;
wire [1:0]M_AXI_GP0_BRESP;
wire M_AXI_GP0_BVALID;
wire [31:0]M_AXI_GP0_RDATA;
wire [11:0]M_AXI_GP0_RID;
wire M_AXI_GP0_RLAST;
wire M_AXI_GP0_RREADY;
wire [1:0]M_AXI_GP0_RRESP;
wire M_AXI_GP0_RVALID;
wire [31:0]M_AXI_GP0_WDATA;
wire [11:0]M_AXI_GP0_WID;
wire M_AXI_GP0_WLAST;
wire M_AXI_GP0_WREADY;
wire [3:0]M_AXI_GP0_WSTRB;
wire M_AXI_GP0_WVALID;
wire M_AXI_GP1_ACLK;
wire [31:0]M_AXI_GP1_ARADDR;
wire [1:0]M_AXI_GP1_ARBURST;
wire [3:0]\^M_AXI_GP1_ARCACHE ;
wire M_AXI_GP1_ARESETN;
wire [11:0]M_AXI_GP1_ARID;
wire [3:0]M_AXI_GP1_ARLEN;
wire [1:0]M_AXI_GP1_ARLOCK;
wire [2:0]M_AXI_GP1_ARPROT;
wire [3:0]M_AXI_GP1_ARQOS;
wire M_AXI_GP1_ARREADY;
wire [1:0]\^M_AXI_GP1_ARSIZE ;
wire M_AXI_GP1_ARVALID;
wire [31:0]M_AXI_GP1_AWADDR;
wire [1:0]M_AXI_GP1_AWBURST;
wire [3:0]\^M_AXI_GP1_AWCACHE ;
wire [11:0]M_AXI_GP1_AWID;
wire [3:0]M_AXI_GP1_AWLEN;
wire [1:0]M_AXI_GP1_AWLOCK;
wire [2:0]M_AXI_GP1_AWPROT;
wire [3:0]M_AXI_GP1_AWQOS;
wire M_AXI_GP1_AWREADY;
wire [1:0]\^M_AXI_GP1_AWSIZE ;
wire M_AXI_GP1_AWVALID;
wire [11:0]M_AXI_GP1_BID;
wire M_AXI_GP1_BREADY;
wire [1:0]M_AXI_GP1_BRESP;
wire M_AXI_GP1_BVALID;
wire [31:0]M_AXI_GP1_RDATA;
wire [11:0]M_AXI_GP1_RID;
wire M_AXI_GP1_RLAST;
wire M_AXI_GP1_RREADY;
wire [1:0]M_AXI_GP1_RRESP;
wire M_AXI_GP1_RVALID;
wire [31:0]M_AXI_GP1_WDATA;
wire [11:0]M_AXI_GP1_WID;
wire M_AXI_GP1_WLAST;
wire M_AXI_GP1_WREADY;
wire [3:0]M_AXI_GP1_WSTRB;
wire M_AXI_GP1_WVALID;
wire PJTAG_TCK;
wire PJTAG_TDI;
wire PJTAG_TMS;
wire PS_CLK;
wire PS_PORB;
wire PS_SRSTB;
wire SDIO0_BUSPOW;
wire [2:0]SDIO0_BUSVOLT;
wire SDIO0_CDN;
wire SDIO0_CLK;
wire SDIO0_CLK_FB;
wire SDIO0_CMD_I;
wire SDIO0_CMD_O;
wire SDIO0_CMD_T;
wire SDIO0_CMD_T_n;
wire [3:0]SDIO0_DATA_I;
wire [3:0]SDIO0_DATA_O;
wire [3:0]SDIO0_DATA_T;
wire [3:0]SDIO0_DATA_T_n;
wire SDIO0_LED;
wire SDIO0_WP;
wire SDIO1_BUSPOW;
wire [2:0]SDIO1_BUSVOLT;
wire SDIO1_CDN;
wire SDIO1_CLK;
wire SDIO1_CLK_FB;
wire SDIO1_CMD_I;
wire SDIO1_CMD_O;
wire SDIO1_CMD_T;
wire SDIO1_CMD_T_n;
wire [3:0]SDIO1_DATA_I;
wire [3:0]SDIO1_DATA_O;
wire [3:0]SDIO1_DATA_T;
wire [3:0]SDIO1_DATA_T_n;
wire SDIO1_LED;
wire SDIO1_WP;
wire SPI0_MISO_I;
wire SPI0_MISO_O;
wire SPI0_MISO_T;
wire SPI0_MISO_T_n;
wire SPI0_MOSI_I;
wire SPI0_MOSI_O;
wire SPI0_MOSI_T;
wire SPI0_MOSI_T_n;
wire SPI0_SCLK_I;
wire SPI0_SCLK_O;
wire SPI0_SCLK_T;
wire SPI0_SCLK_T_n;
wire SPI0_SS1_O;
wire SPI0_SS2_O;
wire SPI0_SS_I;
wire SPI0_SS_O;
wire SPI0_SS_T;
wire SPI0_SS_T_n;
wire SPI1_MISO_I;
wire SPI1_MISO_O;
wire SPI1_MISO_T;
wire SPI1_MISO_T_n;
wire SPI1_MOSI_I;
wire SPI1_MOSI_O;
wire SPI1_MOSI_T;
wire SPI1_MOSI_T_n;
wire SPI1_SCLK_I;
wire SPI1_SCLK_O;
wire SPI1_SCLK_T;
wire SPI1_SCLK_T_n;
wire SPI1_SS1_O;
wire SPI1_SS2_O;
wire SPI1_SS_I;
wire SPI1_SS_O;
wire SPI1_SS_T;
wire SPI1_SS_T_n;
wire SRAM_INTIN;
wire S_AXI_ACP_ACLK;
wire [31:0]S_AXI_ACP_ARADDR;
wire [1:0]S_AXI_ACP_ARBURST;
wire [3:0]S_AXI_ACP_ARCACHE;
wire S_AXI_ACP_ARESETN;
wire [2:0]S_AXI_ACP_ARID;
wire [3:0]S_AXI_ACP_ARLEN;
wire [1:0]S_AXI_ACP_ARLOCK;
wire [2:0]S_AXI_ACP_ARPROT;
wire [3:0]S_AXI_ACP_ARQOS;
wire S_AXI_ACP_ARREADY;
wire [2:0]S_AXI_ACP_ARSIZE;
wire [4:0]S_AXI_ACP_ARUSER;
wire S_AXI_ACP_ARVALID;
wire [31:0]S_AXI_ACP_AWADDR;
wire [1:0]S_AXI_ACP_AWBURST;
wire [3:0]S_AXI_ACP_AWCACHE;
wire [2:0]S_AXI_ACP_AWID;
wire [3:0]S_AXI_ACP_AWLEN;
wire [1:0]S_AXI_ACP_AWLOCK;
wire [2:0]S_AXI_ACP_AWPROT;
wire [3:0]S_AXI_ACP_AWQOS;
wire S_AXI_ACP_AWREADY;
wire [2:0]S_AXI_ACP_AWSIZE;
wire [4:0]S_AXI_ACP_AWUSER;
wire S_AXI_ACP_AWVALID;
wire [2:0]S_AXI_ACP_BID;
wire S_AXI_ACP_BREADY;
wire [1:0]S_AXI_ACP_BRESP;
wire S_AXI_ACP_BVALID;
wire [63:0]S_AXI_ACP_RDATA;
wire [2:0]S_AXI_ACP_RID;
wire S_AXI_ACP_RLAST;
wire S_AXI_ACP_RREADY;
wire [1:0]S_AXI_ACP_RRESP;
wire S_AXI_ACP_RVALID;
wire [63:0]S_AXI_ACP_WDATA;
wire [2:0]S_AXI_ACP_WID;
wire S_AXI_ACP_WLAST;
wire S_AXI_ACP_WREADY;
wire [7:0]S_AXI_ACP_WSTRB;
wire S_AXI_ACP_WVALID;
wire S_AXI_GP0_ACLK;
wire [31:0]S_AXI_GP0_ARADDR;
wire [1:0]S_AXI_GP0_ARBURST;
wire [3:0]S_AXI_GP0_ARCACHE;
wire S_AXI_GP0_ARESETN;
wire [5:0]S_AXI_GP0_ARID;
wire [3:0]S_AXI_GP0_ARLEN;
wire [1:0]S_AXI_GP0_ARLOCK;
wire [2:0]S_AXI_GP0_ARPROT;
wire [3:0]S_AXI_GP0_ARQOS;
wire S_AXI_GP0_ARREADY;
wire [2:0]S_AXI_GP0_ARSIZE;
wire S_AXI_GP0_ARVALID;
wire [31:0]S_AXI_GP0_AWADDR;
wire [1:0]S_AXI_GP0_AWBURST;
wire [3:0]S_AXI_GP0_AWCACHE;
wire [5:0]S_AXI_GP0_AWID;
wire [3:0]S_AXI_GP0_AWLEN;
wire [1:0]S_AXI_GP0_AWLOCK;
wire [2:0]S_AXI_GP0_AWPROT;
wire [3:0]S_AXI_GP0_AWQOS;
wire S_AXI_GP0_AWREADY;
wire [2:0]S_AXI_GP0_AWSIZE;
wire S_AXI_GP0_AWVALID;
wire [5:0]S_AXI_GP0_BID;
wire S_AXI_GP0_BREADY;
wire [1:0]S_AXI_GP0_BRESP;
wire S_AXI_GP0_BVALID;
wire [31:0]S_AXI_GP0_RDATA;
wire [5:0]S_AXI_GP0_RID;
wire S_AXI_GP0_RLAST;
wire S_AXI_GP0_RREADY;
wire [1:0]S_AXI_GP0_RRESP;
wire S_AXI_GP0_RVALID;
wire [31:0]S_AXI_GP0_WDATA;
wire [5:0]S_AXI_GP0_WID;
wire S_AXI_GP0_WLAST;
wire S_AXI_GP0_WREADY;
wire [3:0]S_AXI_GP0_WSTRB;
wire S_AXI_GP0_WVALID;
wire S_AXI_GP1_ACLK;
wire [31:0]S_AXI_GP1_ARADDR;
wire [1:0]S_AXI_GP1_ARBURST;
wire [3:0]S_AXI_GP1_ARCACHE;
wire S_AXI_GP1_ARESETN;
wire [5:0]S_AXI_GP1_ARID;
wire [3:0]S_AXI_GP1_ARLEN;
wire [1:0]S_AXI_GP1_ARLOCK;
wire [2:0]S_AXI_GP1_ARPROT;
wire [3:0]S_AXI_GP1_ARQOS;
wire S_AXI_GP1_ARREADY;
wire [2:0]S_AXI_GP1_ARSIZE;
wire S_AXI_GP1_ARVALID;
wire [31:0]S_AXI_GP1_AWADDR;
wire [1:0]S_AXI_GP1_AWBURST;
wire [3:0]S_AXI_GP1_AWCACHE;
wire [5:0]S_AXI_GP1_AWID;
wire [3:0]S_AXI_GP1_AWLEN;
wire [1:0]S_AXI_GP1_AWLOCK;
wire [2:0]S_AXI_GP1_AWPROT;
wire [3:0]S_AXI_GP1_AWQOS;
wire S_AXI_GP1_AWREADY;
wire [2:0]S_AXI_GP1_AWSIZE;
wire S_AXI_GP1_AWVALID;
wire [5:0]S_AXI_GP1_BID;
wire S_AXI_GP1_BREADY;
wire [1:0]S_AXI_GP1_BRESP;
wire S_AXI_GP1_BVALID;
wire [31:0]S_AXI_GP1_RDATA;
wire [5:0]S_AXI_GP1_RID;
wire S_AXI_GP1_RLAST;
wire S_AXI_GP1_RREADY;
wire [1:0]S_AXI_GP1_RRESP;
wire S_AXI_GP1_RVALID;
wire [31:0]S_AXI_GP1_WDATA;
wire [5:0]S_AXI_GP1_WID;
wire S_AXI_GP1_WLAST;
wire S_AXI_GP1_WREADY;
wire [3:0]S_AXI_GP1_WSTRB;
wire S_AXI_GP1_WVALID;
wire S_AXI_HP0_ACLK;
wire [31:0]S_AXI_HP0_ARADDR;
wire [1:0]S_AXI_HP0_ARBURST;
wire [3:0]S_AXI_HP0_ARCACHE;
wire S_AXI_HP0_ARESETN;
wire [5:0]S_AXI_HP0_ARID;
wire [3:0]S_AXI_HP0_ARLEN;
wire [1:0]S_AXI_HP0_ARLOCK;
wire [2:0]S_AXI_HP0_ARPROT;
wire [3:0]S_AXI_HP0_ARQOS;
wire S_AXI_HP0_ARREADY;
wire [2:0]S_AXI_HP0_ARSIZE;
wire S_AXI_HP0_ARVALID;
wire [31:0]S_AXI_HP0_AWADDR;
wire [1:0]S_AXI_HP0_AWBURST;
wire [3:0]S_AXI_HP0_AWCACHE;
wire [5:0]S_AXI_HP0_AWID;
wire [3:0]S_AXI_HP0_AWLEN;
wire [1:0]S_AXI_HP0_AWLOCK;
wire [2:0]S_AXI_HP0_AWPROT;
wire [3:0]S_AXI_HP0_AWQOS;
wire S_AXI_HP0_AWREADY;
wire [2:0]S_AXI_HP0_AWSIZE;
wire S_AXI_HP0_AWVALID;
wire [5:0]S_AXI_HP0_BID;
wire S_AXI_HP0_BREADY;
wire [1:0]S_AXI_HP0_BRESP;
wire S_AXI_HP0_BVALID;
wire [2:0]S_AXI_HP0_RACOUNT;
wire [7:0]S_AXI_HP0_RCOUNT;
wire [63:0]S_AXI_HP0_RDATA;
wire S_AXI_HP0_RDISSUECAP1_EN;
wire [5:0]S_AXI_HP0_RID;
wire S_AXI_HP0_RLAST;
wire S_AXI_HP0_RREADY;
wire [1:0]S_AXI_HP0_RRESP;
wire S_AXI_HP0_RVALID;
wire [5:0]S_AXI_HP0_WACOUNT;
wire [7:0]S_AXI_HP0_WCOUNT;
wire [63:0]S_AXI_HP0_WDATA;
wire [5:0]S_AXI_HP0_WID;
wire S_AXI_HP0_WLAST;
wire S_AXI_HP0_WREADY;
wire S_AXI_HP0_WRISSUECAP1_EN;
wire [7:0]S_AXI_HP0_WSTRB;
wire S_AXI_HP0_WVALID;
wire S_AXI_HP1_ACLK;
wire [31:0]S_AXI_HP1_ARADDR;
wire [1:0]S_AXI_HP1_ARBURST;
wire [3:0]S_AXI_HP1_ARCACHE;
wire S_AXI_HP1_ARESETN;
wire [5:0]S_AXI_HP1_ARID;
wire [3:0]S_AXI_HP1_ARLEN;
wire [1:0]S_AXI_HP1_ARLOCK;
wire [2:0]S_AXI_HP1_ARPROT;
wire [3:0]S_AXI_HP1_ARQOS;
wire S_AXI_HP1_ARREADY;
wire [2:0]S_AXI_HP1_ARSIZE;
wire S_AXI_HP1_ARVALID;
wire [31:0]S_AXI_HP1_AWADDR;
wire [1:0]S_AXI_HP1_AWBURST;
wire [3:0]S_AXI_HP1_AWCACHE;
wire [5:0]S_AXI_HP1_AWID;
wire [3:0]S_AXI_HP1_AWLEN;
wire [1:0]S_AXI_HP1_AWLOCK;
wire [2:0]S_AXI_HP1_AWPROT;
wire [3:0]S_AXI_HP1_AWQOS;
wire S_AXI_HP1_AWREADY;
wire [2:0]S_AXI_HP1_AWSIZE;
wire S_AXI_HP1_AWVALID;
wire [5:0]S_AXI_HP1_BID;
wire S_AXI_HP1_BREADY;
wire [1:0]S_AXI_HP1_BRESP;
wire S_AXI_HP1_BVALID;
wire [2:0]S_AXI_HP1_RACOUNT;
wire [7:0]S_AXI_HP1_RCOUNT;
wire [63:0]S_AXI_HP1_RDATA;
wire S_AXI_HP1_RDISSUECAP1_EN;
wire [5:0]S_AXI_HP1_RID;
wire S_AXI_HP1_RLAST;
wire S_AXI_HP1_RREADY;
wire [1:0]S_AXI_HP1_RRESP;
wire S_AXI_HP1_RVALID;
wire [5:0]S_AXI_HP1_WACOUNT;
wire [7:0]S_AXI_HP1_WCOUNT;
wire [63:0]S_AXI_HP1_WDATA;
wire [5:0]S_AXI_HP1_WID;
wire S_AXI_HP1_WLAST;
wire S_AXI_HP1_WREADY;
wire S_AXI_HP1_WRISSUECAP1_EN;
wire [7:0]S_AXI_HP1_WSTRB;
wire S_AXI_HP1_WVALID;
wire S_AXI_HP2_ACLK;
wire [31:0]S_AXI_HP2_ARADDR;
wire [1:0]S_AXI_HP2_ARBURST;
wire [3:0]S_AXI_HP2_ARCACHE;
wire S_AXI_HP2_ARESETN;
wire [5:0]S_AXI_HP2_ARID;
wire [3:0]S_AXI_HP2_ARLEN;
wire [1:0]S_AXI_HP2_ARLOCK;
wire [2:0]S_AXI_HP2_ARPROT;
wire [3:0]S_AXI_HP2_ARQOS;
wire S_AXI_HP2_ARREADY;
wire [2:0]S_AXI_HP2_ARSIZE;
wire S_AXI_HP2_ARVALID;
wire [31:0]S_AXI_HP2_AWADDR;
wire [1:0]S_AXI_HP2_AWBURST;
wire [3:0]S_AXI_HP2_AWCACHE;
wire [5:0]S_AXI_HP2_AWID;
wire [3:0]S_AXI_HP2_AWLEN;
wire [1:0]S_AXI_HP2_AWLOCK;
wire [2:0]S_AXI_HP2_AWPROT;
wire [3:0]S_AXI_HP2_AWQOS;
wire S_AXI_HP2_AWREADY;
wire [2:0]S_AXI_HP2_AWSIZE;
wire S_AXI_HP2_AWVALID;
wire [5:0]S_AXI_HP2_BID;
wire S_AXI_HP2_BREADY;
wire [1:0]S_AXI_HP2_BRESP;
wire S_AXI_HP2_BVALID;
wire [2:0]S_AXI_HP2_RACOUNT;
wire [7:0]S_AXI_HP2_RCOUNT;
wire [63:0]S_AXI_HP2_RDATA;
wire S_AXI_HP2_RDISSUECAP1_EN;
wire [5:0]S_AXI_HP2_RID;
wire S_AXI_HP2_RLAST;
wire S_AXI_HP2_RREADY;
wire [1:0]S_AXI_HP2_RRESP;
wire S_AXI_HP2_RVALID;
wire [5:0]S_AXI_HP2_WACOUNT;
wire [7:0]S_AXI_HP2_WCOUNT;
wire [63:0]S_AXI_HP2_WDATA;
wire [5:0]S_AXI_HP2_WID;
wire S_AXI_HP2_WLAST;
wire S_AXI_HP2_WREADY;
wire S_AXI_HP2_WRISSUECAP1_EN;
wire [7:0]S_AXI_HP2_WSTRB;
wire S_AXI_HP2_WVALID;
wire S_AXI_HP3_ACLK;
wire [31:0]S_AXI_HP3_ARADDR;
wire [1:0]S_AXI_HP3_ARBURST;
wire [3:0]S_AXI_HP3_ARCACHE;
wire S_AXI_HP3_ARESETN;
wire [5:0]S_AXI_HP3_ARID;
wire [3:0]S_AXI_HP3_ARLEN;
wire [1:0]S_AXI_HP3_ARLOCK;
wire [2:0]S_AXI_HP3_ARPROT;
wire [3:0]S_AXI_HP3_ARQOS;
wire S_AXI_HP3_ARREADY;
wire [2:0]S_AXI_HP3_ARSIZE;
wire S_AXI_HP3_ARVALID;
wire [31:0]S_AXI_HP3_AWADDR;
wire [1:0]S_AXI_HP3_AWBURST;
wire [3:0]S_AXI_HP3_AWCACHE;
wire [5:0]S_AXI_HP3_AWID;
wire [3:0]S_AXI_HP3_AWLEN;
wire [1:0]S_AXI_HP3_AWLOCK;
wire [2:0]S_AXI_HP3_AWPROT;
wire [3:0]S_AXI_HP3_AWQOS;
wire S_AXI_HP3_AWREADY;
wire [2:0]S_AXI_HP3_AWSIZE;
wire S_AXI_HP3_AWVALID;
wire [5:0]S_AXI_HP3_BID;
wire S_AXI_HP3_BREADY;
wire [1:0]S_AXI_HP3_BRESP;
wire S_AXI_HP3_BVALID;
wire [2:0]S_AXI_HP3_RACOUNT;
wire [7:0]S_AXI_HP3_RCOUNT;
wire [63:0]S_AXI_HP3_RDATA;
wire S_AXI_HP3_RDISSUECAP1_EN;
wire [5:0]S_AXI_HP3_RID;
wire S_AXI_HP3_RLAST;
wire S_AXI_HP3_RREADY;
wire [1:0]S_AXI_HP3_RRESP;
wire S_AXI_HP3_RVALID;
wire [5:0]S_AXI_HP3_WACOUNT;
wire [7:0]S_AXI_HP3_WCOUNT;
wire [63:0]S_AXI_HP3_WDATA;
wire [5:0]S_AXI_HP3_WID;
wire S_AXI_HP3_WLAST;
wire S_AXI_HP3_WREADY;
wire S_AXI_HP3_WRISSUECAP1_EN;
wire [7:0]S_AXI_HP3_WSTRB;
wire S_AXI_HP3_WVALID;
wire TRACE_CLK;
(* RTL_KEEP = "true" *) wire \TRACE_CTL_PIPE[0] ;
(* RTL_KEEP = "true" *) wire \TRACE_CTL_PIPE[1] ;
(* RTL_KEEP = "true" *) wire \TRACE_CTL_PIPE[2] ;
(* RTL_KEEP = "true" *) wire \TRACE_CTL_PIPE[3] ;
(* RTL_KEEP = "true" *) wire \TRACE_CTL_PIPE[4] ;
(* RTL_KEEP = "true" *) wire \TRACE_CTL_PIPE[5] ;
(* RTL_KEEP = "true" *) wire \TRACE_CTL_PIPE[6] ;
(* RTL_KEEP = "true" *) wire \TRACE_CTL_PIPE[7] ;
(* RTL_KEEP = "true" *) wire [1:0]\TRACE_DATA_PIPE[0] ;
(* RTL_KEEP = "true" *) wire [1:0]\TRACE_DATA_PIPE[1] ;
(* RTL_KEEP = "true" *) wire [1:0]\TRACE_DATA_PIPE[2] ;
(* RTL_KEEP = "true" *) wire [1:0]\TRACE_DATA_PIPE[3] ;
(* RTL_KEEP = "true" *) wire [1:0]\TRACE_DATA_PIPE[4] ;
(* RTL_KEEP = "true" *) wire [1:0]\TRACE_DATA_PIPE[5] ;
(* RTL_KEEP = "true" *) wire [1:0]\TRACE_DATA_PIPE[6] ;
(* RTL_KEEP = "true" *) wire [1:0]\TRACE_DATA_PIPE[7] ;
wire TTC0_CLK0_IN;
wire TTC0_CLK1_IN;
wire TTC0_CLK2_IN;
wire TTC0_WAVE0_OUT;
wire TTC0_WAVE1_OUT;
wire TTC0_WAVE2_OUT;
wire TTC1_CLK0_IN;
wire TTC1_CLK1_IN;
wire TTC1_CLK2_IN;
wire TTC1_WAVE0_OUT;
wire TTC1_WAVE1_OUT;
wire TTC1_WAVE2_OUT;
wire UART0_CTSN;
wire UART0_DCDN;
wire UART0_DSRN;
wire UART0_DTRN;
wire UART0_RIN;
wire UART0_RTSN;
wire UART0_RX;
wire UART0_TX;
wire UART1_CTSN;
wire UART1_DCDN;
wire UART1_DSRN;
wire UART1_DTRN;
wire UART1_RIN;
wire UART1_RTSN;
wire UART1_RX;
wire UART1_TX;
wire [1:0]USB0_PORT_INDCTL;
wire USB0_VBUS_PWRFAULT;
wire USB0_VBUS_PWRSELECT;
wire [1:0]USB1_PORT_INDCTL;
wire USB1_VBUS_PWRFAULT;
wire USB1_VBUS_PWRSELECT;
wire WDT_CLK_IN;
wire WDT_RST_OUT;
wire [14:0]buffered_DDR_Addr;
wire [2:0]buffered_DDR_BankAddr;
wire buffered_DDR_CAS_n;
wire buffered_DDR_CKE;
wire buffered_DDR_CS_n;
wire buffered_DDR_Clk;
wire buffered_DDR_Clk_n;
wire [3:0]buffered_DDR_DM;
wire [31:0]buffered_DDR_DQ;
wire [3:0]buffered_DDR_DQS;
wire [3:0]buffered_DDR_DQS_n;
wire buffered_DDR_DRSTB;
wire buffered_DDR_ODT;
wire buffered_DDR_RAS_n;
wire buffered_DDR_VRN;
wire buffered_DDR_VRP;
wire buffered_DDR_WEB;
wire [53:0]buffered_MIO;
wire buffered_PS_CLK;
wire buffered_PS_PORB;
wire buffered_PS_SRSTB;
wire [63:0]gpio_out_t_n;
wire NLW_PS7_i_EMIOENET0GMIITXEN_UNCONNECTED;
wire NLW_PS7_i_EMIOENET0GMIITXER_UNCONNECTED;
wire NLW_PS7_i_EMIOENET1GMIITXEN_UNCONNECTED;
wire NLW_PS7_i_EMIOENET1GMIITXER_UNCONNECTED;
wire NLW_PS7_i_EMIOPJTAGTDO_UNCONNECTED;
wire NLW_PS7_i_EMIOPJTAGTDTN_UNCONNECTED;
wire NLW_PS7_i_EMIOTRACECTL_UNCONNECTED;
wire [7:0]NLW_PS7_i_EMIOENET0GMIITXD_UNCONNECTED;
wire [7:0]NLW_PS7_i_EMIOENET1GMIITXD_UNCONNECTED;
wire [31:0]NLW_PS7_i_EMIOTRACEDATA_UNCONNECTED;
wire [1:1]NLW_PS7_i_MAXIGP0ARCACHE_UNCONNECTED;
wire [1:1]NLW_PS7_i_MAXIGP0AWCACHE_UNCONNECTED;
wire [1:1]NLW_PS7_i_MAXIGP1ARCACHE_UNCONNECTED;
wire [1:1]NLW_PS7_i_MAXIGP1AWCACHE_UNCONNECTED;
assign ENET0_GMII_TXD[7] = \<const0> ;
assign ENET0_GMII_TXD[6] = \<const0> ;
assign ENET0_GMII_TXD[5] = \<const0> ;
assign ENET0_GMII_TXD[4] = \<const0> ;
assign ENET0_GMII_TXD[3] = \<const0> ;
assign ENET0_GMII_TXD[2] = \<const0> ;
assign ENET0_GMII_TXD[1] = \<const0> ;
assign ENET0_GMII_TXD[0] = \<const0> ;
assign ENET0_GMII_TX_EN = \<const0> ;
assign ENET0_GMII_TX_ER = \<const0> ;
assign ENET1_GMII_TXD[7] = \<const0> ;
assign ENET1_GMII_TXD[6] = \<const0> ;
assign ENET1_GMII_TXD[5] = \<const0> ;
assign ENET1_GMII_TXD[4] = \<const0> ;
assign ENET1_GMII_TXD[3] = \<const0> ;
assign ENET1_GMII_TXD[2] = \<const0> ;
assign ENET1_GMII_TXD[1] = \<const0> ;
assign ENET1_GMII_TXD[0] = \<const0> ;
assign ENET1_GMII_TX_EN = \<const0> ;
assign ENET1_GMII_TX_ER = \<const0> ;
assign M_AXI_GP0_ARCACHE[3:2] = \^M_AXI_GP0_ARCACHE [3:2];
assign M_AXI_GP0_ARCACHE[1] = \<const1> ;
assign M_AXI_GP0_ARCACHE[0] = \^M_AXI_GP0_ARCACHE [0];
assign M_AXI_GP0_ARSIZE[2] = \<const0> ;
assign M_AXI_GP0_ARSIZE[1:0] = \^M_AXI_GP0_ARSIZE [1:0];
assign M_AXI_GP0_AWCACHE[3:2] = \^M_AXI_GP0_AWCACHE [3:2];
assign M_AXI_GP0_AWCACHE[1] = \<const1> ;
assign M_AXI_GP0_AWCACHE[0] = \^M_AXI_GP0_AWCACHE [0];
assign M_AXI_GP0_AWSIZE[2] = \<const0> ;
assign M_AXI_GP0_AWSIZE[1:0] = \^M_AXI_GP0_AWSIZE [1:0];
assign M_AXI_GP1_ARCACHE[3:2] = \^M_AXI_GP1_ARCACHE [3:2];
assign M_AXI_GP1_ARCACHE[1] = \<const1> ;
assign M_AXI_GP1_ARCACHE[0] = \^M_AXI_GP1_ARCACHE [0];
assign M_AXI_GP1_ARSIZE[2] = \<const0> ;
assign M_AXI_GP1_ARSIZE[1:0] = \^M_AXI_GP1_ARSIZE [1:0];
assign M_AXI_GP1_AWCACHE[3:2] = \^M_AXI_GP1_AWCACHE [3:2];
assign M_AXI_GP1_AWCACHE[1] = \<const1> ;
assign M_AXI_GP1_AWCACHE[0] = \^M_AXI_GP1_AWCACHE [0];
assign M_AXI_GP1_AWSIZE[2] = \<const0> ;
assign M_AXI_GP1_AWSIZE[1:0] = \^M_AXI_GP1_AWSIZE [1:0];
assign PJTAG_TDO = \<const0> ;
assign TRACE_CLK_OUT = \<const0> ;
assign TRACE_CTL = \TRACE_CTL_PIPE[0] ;
assign TRACE_DATA[1:0] = \TRACE_DATA_PIPE[0] ;
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_CAS_n_BIBUF
(.IO(buffered_DDR_CAS_n),
.PAD(DDR_CAS_n));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_CKE_BIBUF
(.IO(buffered_DDR_CKE),
.PAD(DDR_CKE));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_CS_n_BIBUF
(.IO(buffered_DDR_CS_n),
.PAD(DDR_CS_n));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_Clk_BIBUF
(.IO(buffered_DDR_Clk),
.PAD(DDR_Clk));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_Clk_n_BIBUF
(.IO(buffered_DDR_Clk_n),
.PAD(DDR_Clk_n));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_DRSTB_BIBUF
(.IO(buffered_DDR_DRSTB),
.PAD(DDR_DRSTB));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_ODT_BIBUF
(.IO(buffered_DDR_ODT),
.PAD(DDR_ODT));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_RAS_n_BIBUF
(.IO(buffered_DDR_RAS_n),
.PAD(DDR_RAS_n));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_VRN_BIBUF
(.IO(buffered_DDR_VRN),
.PAD(DDR_VRN));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_VRP_BIBUF
(.IO(buffered_DDR_VRP),
.PAD(DDR_VRP));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_WEB_BIBUF
(.IO(buffered_DDR_WEB),
.PAD(DDR_WEB));
LUT1 #(
.INIT(2'h1))
ENET0_MDIO_T_INST_0
(.I0(ENET0_MDIO_T_n),
.O(ENET0_MDIO_T));
LUT1 #(
.INIT(2'h1))
ENET1_MDIO_T_INST_0
(.I0(ENET1_MDIO_T_n),
.O(ENET1_MDIO_T));
GND GND
(.G(\<const0> ));
LUT1 #(
.INIT(2'h1))
\GPIO_T[0]_INST_0
(.I0(gpio_out_t_n[0]),
.O(GPIO_T[0]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[10]_INST_0
(.I0(gpio_out_t_n[10]),
.O(GPIO_T[10]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[11]_INST_0
(.I0(gpio_out_t_n[11]),
.O(GPIO_T[11]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[12]_INST_0
(.I0(gpio_out_t_n[12]),
.O(GPIO_T[12]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[13]_INST_0
(.I0(gpio_out_t_n[13]),
.O(GPIO_T[13]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[14]_INST_0
(.I0(gpio_out_t_n[14]),
.O(GPIO_T[14]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[15]_INST_0
(.I0(gpio_out_t_n[15]),
.O(GPIO_T[15]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[16]_INST_0
(.I0(gpio_out_t_n[16]),
.O(GPIO_T[16]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[17]_INST_0
(.I0(gpio_out_t_n[17]),
.O(GPIO_T[17]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[18]_INST_0
(.I0(gpio_out_t_n[18]),
.O(GPIO_T[18]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[19]_INST_0
(.I0(gpio_out_t_n[19]),
.O(GPIO_T[19]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[1]_INST_0
(.I0(gpio_out_t_n[1]),
.O(GPIO_T[1]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[20]_INST_0
(.I0(gpio_out_t_n[20]),
.O(GPIO_T[20]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[21]_INST_0
(.I0(gpio_out_t_n[21]),
.O(GPIO_T[21]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[22]_INST_0
(.I0(gpio_out_t_n[22]),
.O(GPIO_T[22]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[23]_INST_0
(.I0(gpio_out_t_n[23]),
.O(GPIO_T[23]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[24]_INST_0
(.I0(gpio_out_t_n[24]),
.O(GPIO_T[24]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[25]_INST_0
(.I0(gpio_out_t_n[25]),
.O(GPIO_T[25]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[26]_INST_0
(.I0(gpio_out_t_n[26]),
.O(GPIO_T[26]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[27]_INST_0
(.I0(gpio_out_t_n[27]),
.O(GPIO_T[27]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[28]_INST_0
(.I0(gpio_out_t_n[28]),
.O(GPIO_T[28]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[29]_INST_0
(.I0(gpio_out_t_n[29]),
.O(GPIO_T[29]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[2]_INST_0
(.I0(gpio_out_t_n[2]),
.O(GPIO_T[2]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[30]_INST_0
(.I0(gpio_out_t_n[30]),
.O(GPIO_T[30]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[31]_INST_0
(.I0(gpio_out_t_n[31]),
.O(GPIO_T[31]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[32]_INST_0
(.I0(gpio_out_t_n[32]),
.O(GPIO_T[32]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[33]_INST_0
(.I0(gpio_out_t_n[33]),
.O(GPIO_T[33]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[34]_INST_0
(.I0(gpio_out_t_n[34]),
.O(GPIO_T[34]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[35]_INST_0
(.I0(gpio_out_t_n[35]),
.O(GPIO_T[35]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[36]_INST_0
(.I0(gpio_out_t_n[36]),
.O(GPIO_T[36]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[37]_INST_0
(.I0(gpio_out_t_n[37]),
.O(GPIO_T[37]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[38]_INST_0
(.I0(gpio_out_t_n[38]),
.O(GPIO_T[38]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[39]_INST_0
(.I0(gpio_out_t_n[39]),
.O(GPIO_T[39]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[3]_INST_0
(.I0(gpio_out_t_n[3]),
.O(GPIO_T[3]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[40]_INST_0
(.I0(gpio_out_t_n[40]),
.O(GPIO_T[40]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[41]_INST_0
(.I0(gpio_out_t_n[41]),
.O(GPIO_T[41]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[42]_INST_0
(.I0(gpio_out_t_n[42]),
.O(GPIO_T[42]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[43]_INST_0
(.I0(gpio_out_t_n[43]),
.O(GPIO_T[43]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[44]_INST_0
(.I0(gpio_out_t_n[44]),
.O(GPIO_T[44]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[45]_INST_0
(.I0(gpio_out_t_n[45]),
.O(GPIO_T[45]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[46]_INST_0
(.I0(gpio_out_t_n[46]),
.O(GPIO_T[46]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[47]_INST_0
(.I0(gpio_out_t_n[47]),
.O(GPIO_T[47]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[48]_INST_0
(.I0(gpio_out_t_n[48]),
.O(GPIO_T[48]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[49]_INST_0
(.I0(gpio_out_t_n[49]),
.O(GPIO_T[49]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[4]_INST_0
(.I0(gpio_out_t_n[4]),
.O(GPIO_T[4]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[50]_INST_0
(.I0(gpio_out_t_n[50]),
.O(GPIO_T[50]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[51]_INST_0
(.I0(gpio_out_t_n[51]),
.O(GPIO_T[51]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[52]_INST_0
(.I0(gpio_out_t_n[52]),
.O(GPIO_T[52]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[53]_INST_0
(.I0(gpio_out_t_n[53]),
.O(GPIO_T[53]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[54]_INST_0
(.I0(gpio_out_t_n[54]),
.O(GPIO_T[54]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[55]_INST_0
(.I0(gpio_out_t_n[55]),
.O(GPIO_T[55]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[56]_INST_0
(.I0(gpio_out_t_n[56]),
.O(GPIO_T[56]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[57]_INST_0
(.I0(gpio_out_t_n[57]),
.O(GPIO_T[57]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[58]_INST_0
(.I0(gpio_out_t_n[58]),
.O(GPIO_T[58]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[59]_INST_0
(.I0(gpio_out_t_n[59]),
.O(GPIO_T[59]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[5]_INST_0
(.I0(gpio_out_t_n[5]),
.O(GPIO_T[5]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[60]_INST_0
(.I0(gpio_out_t_n[60]),
.O(GPIO_T[60]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[61]_INST_0
(.I0(gpio_out_t_n[61]),
.O(GPIO_T[61]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[62]_INST_0
(.I0(gpio_out_t_n[62]),
.O(GPIO_T[62]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[63]_INST_0
(.I0(gpio_out_t_n[63]),
.O(GPIO_T[63]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[6]_INST_0
(.I0(gpio_out_t_n[6]),
.O(GPIO_T[6]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[7]_INST_0
(.I0(gpio_out_t_n[7]),
.O(GPIO_T[7]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[8]_INST_0
(.I0(gpio_out_t_n[8]),
.O(GPIO_T[8]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[9]_INST_0
(.I0(gpio_out_t_n[9]),
.O(GPIO_T[9]));
LUT1 #(
.INIT(2'h1))
I2C0_SCL_T_INST_0
(.I0(I2C0_SCL_T_n),
.O(I2C0_SCL_T));
LUT1 #(
.INIT(2'h1))
I2C0_SDA_T_INST_0
(.I0(I2C0_SDA_T_n),
.O(I2C0_SDA_T));
LUT1 #(
.INIT(2'h1))
I2C1_SCL_T_INST_0
(.I0(I2C1_SCL_T_n),
.O(I2C1_SCL_T));
LUT1 #(
.INIT(2'h1))
I2C1_SDA_T_INST_0
(.I0(I2C1_SDA_T_n),
.O(I2C1_SDA_T));
(* BOX_TYPE = "PRIMITIVE" *)
PS7 PS7_i
(.DDRA(buffered_DDR_Addr),
.DDRARB(DDR_ARB),
.DDRBA(buffered_DDR_BankAddr),
.DDRCASB(buffered_DDR_CAS_n),
.DDRCKE(buffered_DDR_CKE),
.DDRCKN(buffered_DDR_Clk_n),
.DDRCKP(buffered_DDR_Clk),
.DDRCSB(buffered_DDR_CS_n),
.DDRDM(buffered_DDR_DM),
.DDRDQ(buffered_DDR_DQ),
.DDRDQSN(buffered_DDR_DQS_n),
.DDRDQSP(buffered_DDR_DQS),
.DDRDRSTB(buffered_DDR_DRSTB),
.DDRODT(buffered_DDR_ODT),
.DDRRASB(buffered_DDR_RAS_n),
.DDRVRN(buffered_DDR_VRN),
.DDRVRP(buffered_DDR_VRP),
.DDRWEB(buffered_DDR_WEB),
.DMA0ACLK(DMA0_ACLK),
.DMA0DAREADY(DMA0_DAREADY),
.DMA0DATYPE(DMA0_DATYPE),
.DMA0DAVALID(DMA0_DAVALID),
.DMA0DRLAST(DMA0_DRLAST),
.DMA0DRREADY(DMA0_DRREADY),
.DMA0DRTYPE(DMA0_DRTYPE),
.DMA0DRVALID(DMA0_DRVALID),
.DMA0RSTN(DMA0_RSTN),
.DMA1ACLK(DMA1_ACLK),
.DMA1DAREADY(DMA1_DAREADY),
.DMA1DATYPE(DMA1_DATYPE),
.DMA1DAVALID(DMA1_DAVALID),
.DMA1DRLAST(DMA1_DRLAST),
.DMA1DRREADY(DMA1_DRREADY),
.DMA1DRTYPE(DMA1_DRTYPE),
.DMA1DRVALID(DMA1_DRVALID),
.DMA1RSTN(DMA1_RSTN),
.DMA2ACLK(DMA2_ACLK),
.DMA2DAREADY(DMA2_DAREADY),
.DMA2DATYPE(DMA2_DATYPE),
.DMA2DAVALID(DMA2_DAVALID),
.DMA2DRLAST(DMA2_DRLAST),
.DMA2DRREADY(DMA2_DRREADY),
.DMA2DRTYPE(DMA2_DRTYPE),
.DMA2DRVALID(DMA2_DRVALID),
.DMA2RSTN(DMA2_RSTN),
.DMA3ACLK(DMA3_ACLK),
.DMA3DAREADY(DMA3_DAREADY),
.DMA3DATYPE(DMA3_DATYPE),
.DMA3DAVALID(DMA3_DAVALID),
.DMA3DRLAST(DMA3_DRLAST),
.DMA3DRREADY(DMA3_DRREADY),
.DMA3DRTYPE(DMA3_DRTYPE),
.DMA3DRVALID(DMA3_DRVALID),
.DMA3RSTN(DMA3_RSTN),
.EMIOCAN0PHYRX(CAN0_PHY_RX),
.EMIOCAN0PHYTX(CAN0_PHY_TX),
.EMIOCAN1PHYRX(CAN1_PHY_RX),
.EMIOCAN1PHYTX(CAN1_PHY_TX),
.EMIOENET0EXTINTIN(ENET0_EXT_INTIN),
.EMIOENET0GMIICOL(1'b0),
.EMIOENET0GMIICRS(1'b0),
.EMIOENET0GMIIRXCLK(ENET0_GMII_RX_CLK),
.EMIOENET0GMIIRXD({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.EMIOENET0GMIIRXDV(1'b0),
.EMIOENET0GMIIRXER(1'b0),
.EMIOENET0GMIITXCLK(ENET0_GMII_TX_CLK),
.EMIOENET0GMIITXD(NLW_PS7_i_EMIOENET0GMIITXD_UNCONNECTED[7:0]),
.EMIOENET0GMIITXEN(NLW_PS7_i_EMIOENET0GMIITXEN_UNCONNECTED),
.EMIOENET0GMIITXER(NLW_PS7_i_EMIOENET0GMIITXER_UNCONNECTED),
.EMIOENET0MDIOI(ENET0_MDIO_I),
.EMIOENET0MDIOMDC(ENET0_MDIO_MDC),
.EMIOENET0MDIOO(ENET0_MDIO_O),
.EMIOENET0MDIOTN(ENET0_MDIO_T_n),
.EMIOENET0PTPDELAYREQRX(ENET0_PTP_DELAY_REQ_RX),
.EMIOENET0PTPDELAYREQTX(ENET0_PTP_DELAY_REQ_TX),
.EMIOENET0PTPPDELAYREQRX(ENET0_PTP_PDELAY_REQ_RX),
.EMIOENET0PTPPDELAYREQTX(ENET0_PTP_PDELAY_REQ_TX),
.EMIOENET0PTPPDELAYRESPRX(ENET0_PTP_PDELAY_RESP_RX),
.EMIOENET0PTPPDELAYRESPTX(ENET0_PTP_PDELAY_RESP_TX),
.EMIOENET0PTPSYNCFRAMERX(ENET0_PTP_SYNC_FRAME_RX),
.EMIOENET0PTPSYNCFRAMETX(ENET0_PTP_SYNC_FRAME_TX),
.EMIOENET0SOFRX(ENET0_SOF_RX),
.EMIOENET0SOFTX(ENET0_SOF_TX),
.EMIOENET1EXTINTIN(ENET1_EXT_INTIN),
.EMIOENET1GMIICOL(1'b0),
.EMIOENET1GMIICRS(1'b0),
.EMIOENET1GMIIRXCLK(ENET1_GMII_RX_CLK),
.EMIOENET1GMIIRXD({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.EMIOENET1GMIIRXDV(1'b0),
.EMIOENET1GMIIRXER(1'b0),
.EMIOENET1GMIITXCLK(ENET1_GMII_TX_CLK),
.EMIOENET1GMIITXD(NLW_PS7_i_EMIOENET1GMIITXD_UNCONNECTED[7:0]),
.EMIOENET1GMIITXEN(NLW_PS7_i_EMIOENET1GMIITXEN_UNCONNECTED),
.EMIOENET1GMIITXER(NLW_PS7_i_EMIOENET1GMIITXER_UNCONNECTED),
.EMIOENET1MDIOI(ENET1_MDIO_I),
.EMIOENET1MDIOMDC(ENET1_MDIO_MDC),
.EMIOENET1MDIOO(ENET1_MDIO_O),
.EMIOENET1MDIOTN(ENET1_MDIO_T_n),
.EMIOENET1PTPDELAYREQRX(ENET1_PTP_DELAY_REQ_RX),
.EMIOENET1PTPDELAYREQTX(ENET1_PTP_DELAY_REQ_TX),
.EMIOENET1PTPPDELAYREQRX(ENET1_PTP_PDELAY_REQ_RX),
.EMIOENET1PTPPDELAYREQTX(ENET1_PTP_PDELAY_REQ_TX),
.EMIOENET1PTPPDELAYRESPRX(ENET1_PTP_PDELAY_RESP_RX),
.EMIOENET1PTPPDELAYRESPTX(ENET1_PTP_PDELAY_RESP_TX),
.EMIOENET1PTPSYNCFRAMERX(ENET1_PTP_SYNC_FRAME_RX),
.EMIOENET1PTPSYNCFRAMETX(ENET1_PTP_SYNC_FRAME_TX),
.EMIOENET1SOFRX(ENET1_SOF_RX),
.EMIOENET1SOFTX(ENET1_SOF_TX),
.EMIOGPIOI(GPIO_I),
.EMIOGPIOO(GPIO_O),
.EMIOGPIOTN(gpio_out_t_n),
.EMIOI2C0SCLI(I2C0_SCL_I),
.EMIOI2C0SCLO(I2C0_SCL_O),
.EMIOI2C0SCLTN(I2C0_SCL_T_n),
.EMIOI2C0SDAI(I2C0_SDA_I),
.EMIOI2C0SDAO(I2C0_SDA_O),
.EMIOI2C0SDATN(I2C0_SDA_T_n),
.EMIOI2C1SCLI(I2C1_SCL_I),
.EMIOI2C1SCLO(I2C1_SCL_O),
.EMIOI2C1SCLTN(I2C1_SCL_T_n),
.EMIOI2C1SDAI(I2C1_SDA_I),
.EMIOI2C1SDAO(I2C1_SDA_O),
.EMIOI2C1SDATN(I2C1_SDA_T_n),
.EMIOPJTAGTCK(PJTAG_TCK),
.EMIOPJTAGTDI(PJTAG_TDI),
.EMIOPJTAGTDO(NLW_PS7_i_EMIOPJTAGTDO_UNCONNECTED),
.EMIOPJTAGTDTN(NLW_PS7_i_EMIOPJTAGTDTN_UNCONNECTED),
.EMIOPJTAGTMS(PJTAG_TMS),
.EMIOSDIO0BUSPOW(SDIO0_BUSPOW),
.EMIOSDIO0BUSVOLT(SDIO0_BUSVOLT),
.EMIOSDIO0CDN(SDIO0_CDN),
.EMIOSDIO0CLK(SDIO0_CLK),
.EMIOSDIO0CLKFB(SDIO0_CLK_FB),
.EMIOSDIO0CMDI(SDIO0_CMD_I),
.EMIOSDIO0CMDO(SDIO0_CMD_O),
.EMIOSDIO0CMDTN(SDIO0_CMD_T_n),
.EMIOSDIO0DATAI(SDIO0_DATA_I),
.EMIOSDIO0DATAO(SDIO0_DATA_O),
.EMIOSDIO0DATATN(SDIO0_DATA_T_n),
.EMIOSDIO0LED(SDIO0_LED),
.EMIOSDIO0WP(SDIO0_WP),
.EMIOSDIO1BUSPOW(SDIO1_BUSPOW),
.EMIOSDIO1BUSVOLT(SDIO1_BUSVOLT),
.EMIOSDIO1CDN(SDIO1_CDN),
.EMIOSDIO1CLK(SDIO1_CLK),
.EMIOSDIO1CLKFB(SDIO1_CLK_FB),
.EMIOSDIO1CMDI(SDIO1_CMD_I),
.EMIOSDIO1CMDO(SDIO1_CMD_O),
.EMIOSDIO1CMDTN(SDIO1_CMD_T_n),
.EMIOSDIO1DATAI(SDIO1_DATA_I),
.EMIOSDIO1DATAO(SDIO1_DATA_O),
.EMIOSDIO1DATATN(SDIO1_DATA_T_n),
.EMIOSDIO1LED(SDIO1_LED),
.EMIOSDIO1WP(SDIO1_WP),
.EMIOSPI0MI(SPI0_MISO_I),
.EMIOSPI0MO(SPI0_MOSI_O),
.EMIOSPI0MOTN(SPI0_MOSI_T_n),
.EMIOSPI0SCLKI(SPI0_SCLK_I),
.EMIOSPI0SCLKO(SPI0_SCLK_O),
.EMIOSPI0SCLKTN(SPI0_SCLK_T_n),
.EMIOSPI0SI(SPI0_MOSI_I),
.EMIOSPI0SO(SPI0_MISO_O),
.EMIOSPI0SSIN(SPI0_SS_I),
.EMIOSPI0SSNTN(SPI0_SS_T_n),
.EMIOSPI0SSON({SPI0_SS2_O,SPI0_SS1_O,SPI0_SS_O}),
.EMIOSPI0STN(SPI0_MISO_T_n),
.EMIOSPI1MI(SPI1_MISO_I),
.EMIOSPI1MO(SPI1_MOSI_O),
.EMIOSPI1MOTN(SPI1_MOSI_T_n),
.EMIOSPI1SCLKI(SPI1_SCLK_I),
.EMIOSPI1SCLKO(SPI1_SCLK_O),
.EMIOSPI1SCLKTN(SPI1_SCLK_T_n),
.EMIOSPI1SI(SPI1_MOSI_I),
.EMIOSPI1SO(SPI1_MISO_O),
.EMIOSPI1SSIN(SPI1_SS_I),
.EMIOSPI1SSNTN(SPI1_SS_T_n),
.EMIOSPI1SSON({SPI1_SS2_O,SPI1_SS1_O,SPI1_SS_O}),
.EMIOSPI1STN(SPI1_MISO_T_n),
.EMIOSRAMINTIN(SRAM_INTIN),
.EMIOTRACECLK(TRACE_CLK),
.EMIOTRACECTL(NLW_PS7_i_EMIOTRACECTL_UNCONNECTED),
.EMIOTRACEDATA(NLW_PS7_i_EMIOTRACEDATA_UNCONNECTED[31:0]),
.EMIOTTC0CLKI({TTC0_CLK2_IN,TTC0_CLK1_IN,TTC0_CLK0_IN}),
.EMIOTTC0WAVEO({TTC0_WAVE2_OUT,TTC0_WAVE1_OUT,TTC0_WAVE0_OUT}),
.EMIOTTC1CLKI({TTC1_CLK2_IN,TTC1_CLK1_IN,TTC1_CLK0_IN}),
.EMIOTTC1WAVEO({TTC1_WAVE2_OUT,TTC1_WAVE1_OUT,TTC1_WAVE0_OUT}),
.EMIOUART0CTSN(UART0_CTSN),
.EMIOUART0DCDN(UART0_DCDN),
.EMIOUART0DSRN(UART0_DSRN),
.EMIOUART0DTRN(UART0_DTRN),
.EMIOUART0RIN(UART0_RIN),
.EMIOUART0RTSN(UART0_RTSN),
.EMIOUART0RX(UART0_RX),
.EMIOUART0TX(UART0_TX),
.EMIOUART1CTSN(UART1_CTSN),
.EMIOUART1DCDN(UART1_DCDN),
.EMIOUART1DSRN(UART1_DSRN),
.EMIOUART1DTRN(UART1_DTRN),
.EMIOUART1RIN(UART1_RIN),
.EMIOUART1RTSN(UART1_RTSN),
.EMIOUART1RX(UART1_RX),
.EMIOUART1TX(UART1_TX),
.EMIOUSB0PORTINDCTL(USB0_PORT_INDCTL),
.EMIOUSB0VBUSPWRFAULT(USB0_VBUS_PWRFAULT),
.EMIOUSB0VBUSPWRSELECT(USB0_VBUS_PWRSELECT),
.EMIOUSB1PORTINDCTL(USB1_PORT_INDCTL),
.EMIOUSB1VBUSPWRFAULT(USB1_VBUS_PWRFAULT),
.EMIOUSB1VBUSPWRSELECT(USB1_VBUS_PWRSELECT),
.EMIOWDTCLKI(WDT_CLK_IN),
.EMIOWDTRSTO(WDT_RST_OUT),
.EVENTEVENTI(EVENT_EVENTI),
.EVENTEVENTO(EVENT_EVENTO),
.EVENTSTANDBYWFE(EVENT_STANDBYWFE),
.EVENTSTANDBYWFI(EVENT_STANDBYWFI),
.FCLKCLK({FCLK_CLK3,FCLK_CLK2,FCLK_CLK1,FCLK_CLK_unbuffered}),
.FCLKCLKTRIGN({1'b0,1'b0,1'b0,1'b0}),
.FCLKRESETN({FCLK_RESET3_N,FCLK_RESET2_N,FCLK_RESET1_N,FCLK_RESET0_N}),
.FPGAIDLEN(FPGA_IDLE_N),
.FTMDTRACEINATID({1'b0,1'b0,1'b0,1'b0}),
.FTMDTRACEINCLOCK(FTMD_TRACEIN_CLK),
.FTMDTRACEINDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.FTMDTRACEINVALID(1'b0),
.FTMTF2PDEBUG(FTMT_F2P_DEBUG),
.FTMTF2PTRIG({FTMT_F2P_TRIG_3,FTMT_F2P_TRIG_2,FTMT_F2P_TRIG_1,FTMT_F2P_TRIG_0}),
.FTMTF2PTRIGACK({FTMT_F2P_TRIGACK_3,FTMT_F2P_TRIGACK_2,FTMT_F2P_TRIGACK_1,FTMT_F2P_TRIGACK_0}),
.FTMTP2FDEBUG(FTMT_P2F_DEBUG),
.FTMTP2FTRIG({FTMT_P2F_TRIG_3,FTMT_P2F_TRIG_2,FTMT_P2F_TRIG_1,FTMT_P2F_TRIG_0}),
.FTMTP2FTRIGACK({FTMT_P2F_TRIGACK_3,FTMT_P2F_TRIGACK_2,FTMT_P2F_TRIGACK_1,FTMT_P2F_TRIGACK_0}),
.IRQF2P({Core1_nFIQ,Core0_nFIQ,Core1_nIRQ,Core0_nIRQ,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,IRQ_F2P}),
.IRQP2F({IRQ_P2F_DMAC_ABORT,IRQ_P2F_DMAC7,IRQ_P2F_DMAC6,IRQ_P2F_DMAC5,IRQ_P2F_DMAC4,IRQ_P2F_DMAC3,IRQ_P2F_DMAC2,IRQ_P2F_DMAC1,IRQ_P2F_DMAC0,IRQ_P2F_SMC,IRQ_P2F_QSPI,IRQ_P2F_CTI,IRQ_P2F_GPIO,IRQ_P2F_USB0,IRQ_P2F_ENET0,IRQ_P2F_ENET_WAKE0,IRQ_P2F_SDIO0,IRQ_P2F_I2C0,IRQ_P2F_SPI0,IRQ_P2F_UART0,IRQ_P2F_CAN0,IRQ_P2F_USB1,IRQ_P2F_ENET1,IRQ_P2F_ENET_WAKE1,IRQ_P2F_SDIO1,IRQ_P2F_I2C1,IRQ_P2F_SPI1,IRQ_P2F_UART1,IRQ_P2F_CAN1}),
.MAXIGP0ACLK(M_AXI_GP0_ACLK),
.MAXIGP0ARADDR(M_AXI_GP0_ARADDR),
.MAXIGP0ARBURST(M_AXI_GP0_ARBURST),
.MAXIGP0ARCACHE(\^M_AXI_GP0_ARCACHE ),
.MAXIGP0ARESETN(M_AXI_GP0_ARESETN),
.MAXIGP0ARID(M_AXI_GP0_ARID),
.MAXIGP0ARLEN(M_AXI_GP0_ARLEN),
.MAXIGP0ARLOCK(M_AXI_GP0_ARLOCK),
.MAXIGP0ARPROT(M_AXI_GP0_ARPROT),
.MAXIGP0ARQOS(M_AXI_GP0_ARQOS),
.MAXIGP0ARREADY(M_AXI_GP0_ARREADY),
.MAXIGP0ARSIZE(\^M_AXI_GP0_ARSIZE ),
.MAXIGP0ARVALID(M_AXI_GP0_ARVALID),
.MAXIGP0AWADDR(M_AXI_GP0_AWADDR),
.MAXIGP0AWBURST(M_AXI_GP0_AWBURST),
.MAXIGP0AWCACHE(\^M_AXI_GP0_AWCACHE ),
.MAXIGP0AWID(M_AXI_GP0_AWID),
.MAXIGP0AWLEN(M_AXI_GP0_AWLEN),
.MAXIGP0AWLOCK(M_AXI_GP0_AWLOCK),
.MAXIGP0AWPROT(M_AXI_GP0_AWPROT),
.MAXIGP0AWQOS(M_AXI_GP0_AWQOS),
.MAXIGP0AWREADY(M_AXI_GP0_AWREADY),
.MAXIGP0AWSIZE(\^M_AXI_GP0_AWSIZE ),
.MAXIGP0AWVALID(M_AXI_GP0_AWVALID),
.MAXIGP0BID(M_AXI_GP0_BID),
.MAXIGP0BREADY(M_AXI_GP0_BREADY),
.MAXIGP0BRESP(M_AXI_GP0_BRESP),
.MAXIGP0BVALID(M_AXI_GP0_BVALID),
.MAXIGP0RDATA(M_AXI_GP0_RDATA),
.MAXIGP0RID(M_AXI_GP0_RID),
.MAXIGP0RLAST(M_AXI_GP0_RLAST),
.MAXIGP0RREADY(M_AXI_GP0_RREADY),
.MAXIGP0RRESP(M_AXI_GP0_RRESP),
.MAXIGP0RVALID(M_AXI_GP0_RVALID),
.MAXIGP0WDATA(M_AXI_GP0_WDATA),
.MAXIGP0WID(M_AXI_GP0_WID),
.MAXIGP0WLAST(M_AXI_GP0_WLAST),
.MAXIGP0WREADY(M_AXI_GP0_WREADY),
.MAXIGP0WSTRB(M_AXI_GP0_WSTRB),
.MAXIGP0WVALID(M_AXI_GP0_WVALID),
.MAXIGP1ACLK(M_AXI_GP1_ACLK),
.MAXIGP1ARADDR(M_AXI_GP1_ARADDR),
.MAXIGP1ARBURST(M_AXI_GP1_ARBURST),
.MAXIGP1ARCACHE(\^M_AXI_GP1_ARCACHE ),
.MAXIGP1ARESETN(M_AXI_GP1_ARESETN),
.MAXIGP1ARID(M_AXI_GP1_ARID),
.MAXIGP1ARLEN(M_AXI_GP1_ARLEN),
.MAXIGP1ARLOCK(M_AXI_GP1_ARLOCK),
.MAXIGP1ARPROT(M_AXI_GP1_ARPROT),
.MAXIGP1ARQOS(M_AXI_GP1_ARQOS),
.MAXIGP1ARREADY(M_AXI_GP1_ARREADY),
.MAXIGP1ARSIZE(\^M_AXI_GP1_ARSIZE ),
.MAXIGP1ARVALID(M_AXI_GP1_ARVALID),
.MAXIGP1AWADDR(M_AXI_GP1_AWADDR),
.MAXIGP1AWBURST(M_AXI_GP1_AWBURST),
.MAXIGP1AWCACHE(\^M_AXI_GP1_AWCACHE ),
.MAXIGP1AWID(M_AXI_GP1_AWID),
.MAXIGP1AWLEN(M_AXI_GP1_AWLEN),
.MAXIGP1AWLOCK(M_AXI_GP1_AWLOCK),
.MAXIGP1AWPROT(M_AXI_GP1_AWPROT),
.MAXIGP1AWQOS(M_AXI_GP1_AWQOS),
.MAXIGP1AWREADY(M_AXI_GP1_AWREADY),
.MAXIGP1AWSIZE(\^M_AXI_GP1_AWSIZE ),
.MAXIGP1AWVALID(M_AXI_GP1_AWVALID),
.MAXIGP1BID(M_AXI_GP1_BID),
.MAXIGP1BREADY(M_AXI_GP1_BREADY),
.MAXIGP1BRESP(M_AXI_GP1_BRESP),
.MAXIGP1BVALID(M_AXI_GP1_BVALID),
.MAXIGP1RDATA(M_AXI_GP1_RDATA),
.MAXIGP1RID(M_AXI_GP1_RID),
.MAXIGP1RLAST(M_AXI_GP1_RLAST),
.MAXIGP1RREADY(M_AXI_GP1_RREADY),
.MAXIGP1RRESP(M_AXI_GP1_RRESP),
.MAXIGP1RVALID(M_AXI_GP1_RVALID),
.MAXIGP1WDATA(M_AXI_GP1_WDATA),
.MAXIGP1WID(M_AXI_GP1_WID),
.MAXIGP1WLAST(M_AXI_GP1_WLAST),
.MAXIGP1WREADY(M_AXI_GP1_WREADY),
.MAXIGP1WSTRB(M_AXI_GP1_WSTRB),
.MAXIGP1WVALID(M_AXI_GP1_WVALID),
.MIO(buffered_MIO),
.PSCLK(buffered_PS_CLK),
.PSPORB(buffered_PS_PORB),
.PSSRSTB(buffered_PS_SRSTB),
.SAXIACPACLK(S_AXI_ACP_ACLK),
.SAXIACPARADDR(S_AXI_ACP_ARADDR),
.SAXIACPARBURST(S_AXI_ACP_ARBURST),
.SAXIACPARCACHE(S_AXI_ACP_ARCACHE),
.SAXIACPARESETN(S_AXI_ACP_ARESETN),
.SAXIACPARID(S_AXI_ACP_ARID),
.SAXIACPARLEN(S_AXI_ACP_ARLEN),
.SAXIACPARLOCK(S_AXI_ACP_ARLOCK),
.SAXIACPARPROT(S_AXI_ACP_ARPROT),
.SAXIACPARQOS(S_AXI_ACP_ARQOS),
.SAXIACPARREADY(S_AXI_ACP_ARREADY),
.SAXIACPARSIZE(S_AXI_ACP_ARSIZE[1:0]),
.SAXIACPARUSER(S_AXI_ACP_ARUSER),
.SAXIACPARVALID(S_AXI_ACP_ARVALID),
.SAXIACPAWADDR(S_AXI_ACP_AWADDR),
.SAXIACPAWBURST(S_AXI_ACP_AWBURST),
.SAXIACPAWCACHE(S_AXI_ACP_AWCACHE),
.SAXIACPAWID(S_AXI_ACP_AWID),
.SAXIACPAWLEN(S_AXI_ACP_AWLEN),
.SAXIACPAWLOCK(S_AXI_ACP_AWLOCK),
.SAXIACPAWPROT(S_AXI_ACP_AWPROT),
.SAXIACPAWQOS(S_AXI_ACP_AWQOS),
.SAXIACPAWREADY(S_AXI_ACP_AWREADY),
.SAXIACPAWSIZE(S_AXI_ACP_AWSIZE[1:0]),
.SAXIACPAWUSER(S_AXI_ACP_AWUSER),
.SAXIACPAWVALID(S_AXI_ACP_AWVALID),
.SAXIACPBID(S_AXI_ACP_BID),
.SAXIACPBREADY(S_AXI_ACP_BREADY),
.SAXIACPBRESP(S_AXI_ACP_BRESP),
.SAXIACPBVALID(S_AXI_ACP_BVALID),
.SAXIACPRDATA(S_AXI_ACP_RDATA),
.SAXIACPRID(S_AXI_ACP_RID),
.SAXIACPRLAST(S_AXI_ACP_RLAST),
.SAXIACPRREADY(S_AXI_ACP_RREADY),
.SAXIACPRRESP(S_AXI_ACP_RRESP),
.SAXIACPRVALID(S_AXI_ACP_RVALID),
.SAXIACPWDATA(S_AXI_ACP_WDATA),
.SAXIACPWID(S_AXI_ACP_WID),
.SAXIACPWLAST(S_AXI_ACP_WLAST),
.SAXIACPWREADY(S_AXI_ACP_WREADY),
.SAXIACPWSTRB(S_AXI_ACP_WSTRB),
.SAXIACPWVALID(S_AXI_ACP_WVALID),
.SAXIGP0ACLK(S_AXI_GP0_ACLK),
.SAXIGP0ARADDR(S_AXI_GP0_ARADDR),
.SAXIGP0ARBURST(S_AXI_GP0_ARBURST),
.SAXIGP0ARCACHE(S_AXI_GP0_ARCACHE),
.SAXIGP0ARESETN(S_AXI_GP0_ARESETN),
.SAXIGP0ARID(S_AXI_GP0_ARID),
.SAXIGP0ARLEN(S_AXI_GP0_ARLEN),
.SAXIGP0ARLOCK(S_AXI_GP0_ARLOCK),
.SAXIGP0ARPROT(S_AXI_GP0_ARPROT),
.SAXIGP0ARQOS(S_AXI_GP0_ARQOS),
.SAXIGP0ARREADY(S_AXI_GP0_ARREADY),
.SAXIGP0ARSIZE(S_AXI_GP0_ARSIZE[1:0]),
.SAXIGP0ARVALID(S_AXI_GP0_ARVALID),
.SAXIGP0AWADDR(S_AXI_GP0_AWADDR),
.SAXIGP0AWBURST(S_AXI_GP0_AWBURST),
.SAXIGP0AWCACHE(S_AXI_GP0_AWCACHE),
.SAXIGP0AWID(S_AXI_GP0_AWID),
.SAXIGP0AWLEN(S_AXI_GP0_AWLEN),
.SAXIGP0AWLOCK(S_AXI_GP0_AWLOCK),
.SAXIGP0AWPROT(S_AXI_GP0_AWPROT),
.SAXIGP0AWQOS(S_AXI_GP0_AWQOS),
.SAXIGP0AWREADY(S_AXI_GP0_AWREADY),
.SAXIGP0AWSIZE(S_AXI_GP0_AWSIZE[1:0]),
.SAXIGP0AWVALID(S_AXI_GP0_AWVALID),
.SAXIGP0BID(S_AXI_GP0_BID),
.SAXIGP0BREADY(S_AXI_GP0_BREADY),
.SAXIGP0BRESP(S_AXI_GP0_BRESP),
.SAXIGP0BVALID(S_AXI_GP0_BVALID),
.SAXIGP0RDATA(S_AXI_GP0_RDATA),
.SAXIGP0RID(S_AXI_GP0_RID),
.SAXIGP0RLAST(S_AXI_GP0_RLAST),
.SAXIGP0RREADY(S_AXI_GP0_RREADY),
.SAXIGP0RRESP(S_AXI_GP0_RRESP),
.SAXIGP0RVALID(S_AXI_GP0_RVALID),
.SAXIGP0WDATA(S_AXI_GP0_WDATA),
.SAXIGP0WID(S_AXI_GP0_WID),
.SAXIGP0WLAST(S_AXI_GP0_WLAST),
.SAXIGP0WREADY(S_AXI_GP0_WREADY),
.SAXIGP0WSTRB(S_AXI_GP0_WSTRB),
.SAXIGP0WVALID(S_AXI_GP0_WVALID),
.SAXIGP1ACLK(S_AXI_GP1_ACLK),
.SAXIGP1ARADDR(S_AXI_GP1_ARADDR),
.SAXIGP1ARBURST(S_AXI_GP1_ARBURST),
.SAXIGP1ARCACHE(S_AXI_GP1_ARCACHE),
.SAXIGP1ARESETN(S_AXI_GP1_ARESETN),
.SAXIGP1ARID(S_AXI_GP1_ARID),
.SAXIGP1ARLEN(S_AXI_GP1_ARLEN),
.SAXIGP1ARLOCK(S_AXI_GP1_ARLOCK),
.SAXIGP1ARPROT(S_AXI_GP1_ARPROT),
.SAXIGP1ARQOS(S_AXI_GP1_ARQOS),
.SAXIGP1ARREADY(S_AXI_GP1_ARREADY),
.SAXIGP1ARSIZE(S_AXI_GP1_ARSIZE[1:0]),
.SAXIGP1ARVALID(S_AXI_GP1_ARVALID),
.SAXIGP1AWADDR(S_AXI_GP1_AWADDR),
.SAXIGP1AWBURST(S_AXI_GP1_AWBURST),
.SAXIGP1AWCACHE(S_AXI_GP1_AWCACHE),
.SAXIGP1AWID(S_AXI_GP1_AWID),
.SAXIGP1AWLEN(S_AXI_GP1_AWLEN),
.SAXIGP1AWLOCK(S_AXI_GP1_AWLOCK),
.SAXIGP1AWPROT(S_AXI_GP1_AWPROT),
.SAXIGP1AWQOS(S_AXI_GP1_AWQOS),
.SAXIGP1AWREADY(S_AXI_GP1_AWREADY),
.SAXIGP1AWSIZE(S_AXI_GP1_AWSIZE[1:0]),
.SAXIGP1AWVALID(S_AXI_GP1_AWVALID),
.SAXIGP1BID(S_AXI_GP1_BID),
.SAXIGP1BREADY(S_AXI_GP1_BREADY),
.SAXIGP1BRESP(S_AXI_GP1_BRESP),
.SAXIGP1BVALID(S_AXI_GP1_BVALID),
.SAXIGP1RDATA(S_AXI_GP1_RDATA),
.SAXIGP1RID(S_AXI_GP1_RID),
.SAXIGP1RLAST(S_AXI_GP1_RLAST),
.SAXIGP1RREADY(S_AXI_GP1_RREADY),
.SAXIGP1RRESP(S_AXI_GP1_RRESP),
.SAXIGP1RVALID(S_AXI_GP1_RVALID),
.SAXIGP1WDATA(S_AXI_GP1_WDATA),
.SAXIGP1WID(S_AXI_GP1_WID),
.SAXIGP1WLAST(S_AXI_GP1_WLAST),
.SAXIGP1WREADY(S_AXI_GP1_WREADY),
.SAXIGP1WSTRB(S_AXI_GP1_WSTRB),
.SAXIGP1WVALID(S_AXI_GP1_WVALID),
.SAXIHP0ACLK(S_AXI_HP0_ACLK),
.SAXIHP0ARADDR(S_AXI_HP0_ARADDR),
.SAXIHP0ARBURST(S_AXI_HP0_ARBURST),
.SAXIHP0ARCACHE(S_AXI_HP0_ARCACHE),
.SAXIHP0ARESETN(S_AXI_HP0_ARESETN),
.SAXIHP0ARID(S_AXI_HP0_ARID),
.SAXIHP0ARLEN(S_AXI_HP0_ARLEN),
.SAXIHP0ARLOCK(S_AXI_HP0_ARLOCK),
.SAXIHP0ARPROT(S_AXI_HP0_ARPROT),
.SAXIHP0ARQOS(S_AXI_HP0_ARQOS),
.SAXIHP0ARREADY(S_AXI_HP0_ARREADY),
.SAXIHP0ARSIZE(S_AXI_HP0_ARSIZE[1:0]),
.SAXIHP0ARVALID(S_AXI_HP0_ARVALID),
.SAXIHP0AWADDR(S_AXI_HP0_AWADDR),
.SAXIHP0AWBURST(S_AXI_HP0_AWBURST),
.SAXIHP0AWCACHE(S_AXI_HP0_AWCACHE),
.SAXIHP0AWID(S_AXI_HP0_AWID),
.SAXIHP0AWLEN(S_AXI_HP0_AWLEN),
.SAXIHP0AWLOCK(S_AXI_HP0_AWLOCK),
.SAXIHP0AWPROT(S_AXI_HP0_AWPROT),
.SAXIHP0AWQOS(S_AXI_HP0_AWQOS),
.SAXIHP0AWREADY(S_AXI_HP0_AWREADY),
.SAXIHP0AWSIZE(S_AXI_HP0_AWSIZE[1:0]),
.SAXIHP0AWVALID(S_AXI_HP0_AWVALID),
.SAXIHP0BID(S_AXI_HP0_BID),
.SAXIHP0BREADY(S_AXI_HP0_BREADY),
.SAXIHP0BRESP(S_AXI_HP0_BRESP),
.SAXIHP0BVALID(S_AXI_HP0_BVALID),
.SAXIHP0RACOUNT(S_AXI_HP0_RACOUNT),
.SAXIHP0RCOUNT(S_AXI_HP0_RCOUNT),
.SAXIHP0RDATA(S_AXI_HP0_RDATA),
.SAXIHP0RDISSUECAP1EN(S_AXI_HP0_RDISSUECAP1_EN),
.SAXIHP0RID(S_AXI_HP0_RID),
.SAXIHP0RLAST(S_AXI_HP0_RLAST),
.SAXIHP0RREADY(S_AXI_HP0_RREADY),
.SAXIHP0RRESP(S_AXI_HP0_RRESP),
.SAXIHP0RVALID(S_AXI_HP0_RVALID),
.SAXIHP0WACOUNT(S_AXI_HP0_WACOUNT),
.SAXIHP0WCOUNT(S_AXI_HP0_WCOUNT),
.SAXIHP0WDATA(S_AXI_HP0_WDATA),
.SAXIHP0WID(S_AXI_HP0_WID),
.SAXIHP0WLAST(S_AXI_HP0_WLAST),
.SAXIHP0WREADY(S_AXI_HP0_WREADY),
.SAXIHP0WRISSUECAP1EN(S_AXI_HP0_WRISSUECAP1_EN),
.SAXIHP0WSTRB(S_AXI_HP0_WSTRB),
.SAXIHP0WVALID(S_AXI_HP0_WVALID),
.SAXIHP1ACLK(S_AXI_HP1_ACLK),
.SAXIHP1ARADDR(S_AXI_HP1_ARADDR),
.SAXIHP1ARBURST(S_AXI_HP1_ARBURST),
.SAXIHP1ARCACHE(S_AXI_HP1_ARCACHE),
.SAXIHP1ARESETN(S_AXI_HP1_ARESETN),
.SAXIHP1ARID(S_AXI_HP1_ARID),
.SAXIHP1ARLEN(S_AXI_HP1_ARLEN),
.SAXIHP1ARLOCK(S_AXI_HP1_ARLOCK),
.SAXIHP1ARPROT(S_AXI_HP1_ARPROT),
.SAXIHP1ARQOS(S_AXI_HP1_ARQOS),
.SAXIHP1ARREADY(S_AXI_HP1_ARREADY),
.SAXIHP1ARSIZE(S_AXI_HP1_ARSIZE[1:0]),
.SAXIHP1ARVALID(S_AXI_HP1_ARVALID),
.SAXIHP1AWADDR(S_AXI_HP1_AWADDR),
.SAXIHP1AWBURST(S_AXI_HP1_AWBURST),
.SAXIHP1AWCACHE(S_AXI_HP1_AWCACHE),
.SAXIHP1AWID(S_AXI_HP1_AWID),
.SAXIHP1AWLEN(S_AXI_HP1_AWLEN),
.SAXIHP1AWLOCK(S_AXI_HP1_AWLOCK),
.SAXIHP1AWPROT(S_AXI_HP1_AWPROT),
.SAXIHP1AWQOS(S_AXI_HP1_AWQOS),
.SAXIHP1AWREADY(S_AXI_HP1_AWREADY),
.SAXIHP1AWSIZE(S_AXI_HP1_AWSIZE[1:0]),
.SAXIHP1AWVALID(S_AXI_HP1_AWVALID),
.SAXIHP1BID(S_AXI_HP1_BID),
.SAXIHP1BREADY(S_AXI_HP1_BREADY),
.SAXIHP1BRESP(S_AXI_HP1_BRESP),
.SAXIHP1BVALID(S_AXI_HP1_BVALID),
.SAXIHP1RACOUNT(S_AXI_HP1_RACOUNT),
.SAXIHP1RCOUNT(S_AXI_HP1_RCOUNT),
.SAXIHP1RDATA(S_AXI_HP1_RDATA),
.SAXIHP1RDISSUECAP1EN(S_AXI_HP1_RDISSUECAP1_EN),
.SAXIHP1RID(S_AXI_HP1_RID),
.SAXIHP1RLAST(S_AXI_HP1_RLAST),
.SAXIHP1RREADY(S_AXI_HP1_RREADY),
.SAXIHP1RRESP(S_AXI_HP1_RRESP),
.SAXIHP1RVALID(S_AXI_HP1_RVALID),
.SAXIHP1WACOUNT(S_AXI_HP1_WACOUNT),
.SAXIHP1WCOUNT(S_AXI_HP1_WCOUNT),
.SAXIHP1WDATA(S_AXI_HP1_WDATA),
.SAXIHP1WID(S_AXI_HP1_WID),
.SAXIHP1WLAST(S_AXI_HP1_WLAST),
.SAXIHP1WREADY(S_AXI_HP1_WREADY),
.SAXIHP1WRISSUECAP1EN(S_AXI_HP1_WRISSUECAP1_EN),
.SAXIHP1WSTRB(S_AXI_HP1_WSTRB),
.SAXIHP1WVALID(S_AXI_HP1_WVALID),
.SAXIHP2ACLK(S_AXI_HP2_ACLK),
.SAXIHP2ARADDR(S_AXI_HP2_ARADDR),
.SAXIHP2ARBURST(S_AXI_HP2_ARBURST),
.SAXIHP2ARCACHE(S_AXI_HP2_ARCACHE),
.SAXIHP2ARESETN(S_AXI_HP2_ARESETN),
.SAXIHP2ARID(S_AXI_HP2_ARID),
.SAXIHP2ARLEN(S_AXI_HP2_ARLEN),
.SAXIHP2ARLOCK(S_AXI_HP2_ARLOCK),
.SAXIHP2ARPROT(S_AXI_HP2_ARPROT),
.SAXIHP2ARQOS(S_AXI_HP2_ARQOS),
.SAXIHP2ARREADY(S_AXI_HP2_ARREADY),
.SAXIHP2ARSIZE(S_AXI_HP2_ARSIZE[1:0]),
.SAXIHP2ARVALID(S_AXI_HP2_ARVALID),
.SAXIHP2AWADDR(S_AXI_HP2_AWADDR),
.SAXIHP2AWBURST(S_AXI_HP2_AWBURST),
.SAXIHP2AWCACHE(S_AXI_HP2_AWCACHE),
.SAXIHP2AWID(S_AXI_HP2_AWID),
.SAXIHP2AWLEN(S_AXI_HP2_AWLEN),
.SAXIHP2AWLOCK(S_AXI_HP2_AWLOCK),
.SAXIHP2AWPROT(S_AXI_HP2_AWPROT),
.SAXIHP2AWQOS(S_AXI_HP2_AWQOS),
.SAXIHP2AWREADY(S_AXI_HP2_AWREADY),
.SAXIHP2AWSIZE(S_AXI_HP2_AWSIZE[1:0]),
.SAXIHP2AWVALID(S_AXI_HP2_AWVALID),
.SAXIHP2BID(S_AXI_HP2_BID),
.SAXIHP2BREADY(S_AXI_HP2_BREADY),
.SAXIHP2BRESP(S_AXI_HP2_BRESP),
.SAXIHP2BVALID(S_AXI_HP2_BVALID),
.SAXIHP2RACOUNT(S_AXI_HP2_RACOUNT),
.SAXIHP2RCOUNT(S_AXI_HP2_RCOUNT),
.SAXIHP2RDATA(S_AXI_HP2_RDATA),
.SAXIHP2RDISSUECAP1EN(S_AXI_HP2_RDISSUECAP1_EN),
.SAXIHP2RID(S_AXI_HP2_RID),
.SAXIHP2RLAST(S_AXI_HP2_RLAST),
.SAXIHP2RREADY(S_AXI_HP2_RREADY),
.SAXIHP2RRESP(S_AXI_HP2_RRESP),
.SAXIHP2RVALID(S_AXI_HP2_RVALID),
.SAXIHP2WACOUNT(S_AXI_HP2_WACOUNT),
.SAXIHP2WCOUNT(S_AXI_HP2_WCOUNT),
.SAXIHP2WDATA(S_AXI_HP2_WDATA),
.SAXIHP2WID(S_AXI_HP2_WID),
.SAXIHP2WLAST(S_AXI_HP2_WLAST),
.SAXIHP2WREADY(S_AXI_HP2_WREADY),
.SAXIHP2WRISSUECAP1EN(S_AXI_HP2_WRISSUECAP1_EN),
.SAXIHP2WSTRB(S_AXI_HP2_WSTRB),
.SAXIHP2WVALID(S_AXI_HP2_WVALID),
.SAXIHP3ACLK(S_AXI_HP3_ACLK),
.SAXIHP3ARADDR(S_AXI_HP3_ARADDR),
.SAXIHP3ARBURST(S_AXI_HP3_ARBURST),
.SAXIHP3ARCACHE(S_AXI_HP3_ARCACHE),
.SAXIHP3ARESETN(S_AXI_HP3_ARESETN),
.SAXIHP3ARID(S_AXI_HP3_ARID),
.SAXIHP3ARLEN(S_AXI_HP3_ARLEN),
.SAXIHP3ARLOCK(S_AXI_HP3_ARLOCK),
.SAXIHP3ARPROT(S_AXI_HP3_ARPROT),
.SAXIHP3ARQOS(S_AXI_HP3_ARQOS),
.SAXIHP3ARREADY(S_AXI_HP3_ARREADY),
.SAXIHP3ARSIZE(S_AXI_HP3_ARSIZE[1:0]),
.SAXIHP3ARVALID(S_AXI_HP3_ARVALID),
.SAXIHP3AWADDR(S_AXI_HP3_AWADDR),
.SAXIHP3AWBURST(S_AXI_HP3_AWBURST),
.SAXIHP3AWCACHE(S_AXI_HP3_AWCACHE),
.SAXIHP3AWID(S_AXI_HP3_AWID),
.SAXIHP3AWLEN(S_AXI_HP3_AWLEN),
.SAXIHP3AWLOCK(S_AXI_HP3_AWLOCK),
.SAXIHP3AWPROT(S_AXI_HP3_AWPROT),
.SAXIHP3AWQOS(S_AXI_HP3_AWQOS),
.SAXIHP3AWREADY(S_AXI_HP3_AWREADY),
.SAXIHP3AWSIZE(S_AXI_HP3_AWSIZE[1:0]),
.SAXIHP3AWVALID(S_AXI_HP3_AWVALID),
.SAXIHP3BID(S_AXI_HP3_BID),
.SAXIHP3BREADY(S_AXI_HP3_BREADY),
.SAXIHP3BRESP(S_AXI_HP3_BRESP),
.SAXIHP3BVALID(S_AXI_HP3_BVALID),
.SAXIHP3RACOUNT(S_AXI_HP3_RACOUNT),
.SAXIHP3RCOUNT(S_AXI_HP3_RCOUNT),
.SAXIHP3RDATA(S_AXI_HP3_RDATA),
.SAXIHP3RDISSUECAP1EN(S_AXI_HP3_RDISSUECAP1_EN),
.SAXIHP3RID(S_AXI_HP3_RID),
.SAXIHP3RLAST(S_AXI_HP3_RLAST),
.SAXIHP3RREADY(S_AXI_HP3_RREADY),
.SAXIHP3RRESP(S_AXI_HP3_RRESP),
.SAXIHP3RVALID(S_AXI_HP3_RVALID),
.SAXIHP3WACOUNT(S_AXI_HP3_WACOUNT),
.SAXIHP3WCOUNT(S_AXI_HP3_WCOUNT),
.SAXIHP3WDATA(S_AXI_HP3_WDATA),
.SAXIHP3WID(S_AXI_HP3_WID),
.SAXIHP3WLAST(S_AXI_HP3_WLAST),
.SAXIHP3WREADY(S_AXI_HP3_WREADY),
.SAXIHP3WRISSUECAP1EN(S_AXI_HP3_WRISSUECAP1_EN),
.SAXIHP3WSTRB(S_AXI_HP3_WSTRB),
.SAXIHP3WVALID(S_AXI_HP3_WVALID));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF PS_CLK_BIBUF
(.IO(buffered_PS_CLK),
.PAD(PS_CLK));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF PS_PORB_BIBUF
(.IO(buffered_PS_PORB),
.PAD(PS_PORB));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF PS_SRSTB_BIBUF
(.IO(buffered_PS_SRSTB),
.PAD(PS_SRSTB));
LUT1 #(
.INIT(2'h1))
SDIO0_CMD_T_INST_0
(.I0(SDIO0_CMD_T_n),
.O(SDIO0_CMD_T));
LUT1 #(
.INIT(2'h1))
\SDIO0_DATA_T[0]_INST_0
(.I0(SDIO0_DATA_T_n[0]),
.O(SDIO0_DATA_T[0]));
LUT1 #(
.INIT(2'h1))
\SDIO0_DATA_T[1]_INST_0
(.I0(SDIO0_DATA_T_n[1]),
.O(SDIO0_DATA_T[1]));
LUT1 #(
.INIT(2'h1))
\SDIO0_DATA_T[2]_INST_0
(.I0(SDIO0_DATA_T_n[2]),
.O(SDIO0_DATA_T[2]));
LUT1 #(
.INIT(2'h1))
\SDIO0_DATA_T[3]_INST_0
(.I0(SDIO0_DATA_T_n[3]),
.O(SDIO0_DATA_T[3]));
LUT1 #(
.INIT(2'h1))
SDIO1_CMD_T_INST_0
(.I0(SDIO1_CMD_T_n),
.O(SDIO1_CMD_T));
LUT1 #(
.INIT(2'h1))
\SDIO1_DATA_T[0]_INST_0
(.I0(SDIO1_DATA_T_n[0]),
.O(SDIO1_DATA_T[0]));
LUT1 #(
.INIT(2'h1))
\SDIO1_DATA_T[1]_INST_0
(.I0(SDIO1_DATA_T_n[1]),
.O(SDIO1_DATA_T[1]));
LUT1 #(
.INIT(2'h1))
\SDIO1_DATA_T[2]_INST_0
(.I0(SDIO1_DATA_T_n[2]),
.O(SDIO1_DATA_T[2]));
LUT1 #(
.INIT(2'h1))
\SDIO1_DATA_T[3]_INST_0
(.I0(SDIO1_DATA_T_n[3]),
.O(SDIO1_DATA_T[3]));
LUT1 #(
.INIT(2'h1))
SPI0_MISO_T_INST_0
(.I0(SPI0_MISO_T_n),
.O(SPI0_MISO_T));
LUT1 #(
.INIT(2'h1))
SPI0_MOSI_T_INST_0
(.I0(SPI0_MOSI_T_n),
.O(SPI0_MOSI_T));
LUT1 #(
.INIT(2'h1))
SPI0_SCLK_T_INST_0
(.I0(SPI0_SCLK_T_n),
.O(SPI0_SCLK_T));
LUT1 #(
.INIT(2'h1))
SPI0_SS_T_INST_0
(.I0(SPI0_SS_T_n),
.O(SPI0_SS_T));
LUT1 #(
.INIT(2'h1))
SPI1_MISO_T_INST_0
(.I0(SPI1_MISO_T_n),
.O(SPI1_MISO_T));
LUT1 #(
.INIT(2'h1))
SPI1_MOSI_T_INST_0
(.I0(SPI1_MOSI_T_n),
.O(SPI1_MOSI_T));
LUT1 #(
.INIT(2'h1))
SPI1_SCLK_T_INST_0
(.I0(SPI1_SCLK_T_n),
.O(SPI1_SCLK_T));
LUT1 #(
.INIT(2'h1))
SPI1_SS_T_INST_0
(.I0(SPI1_SS_T_n),
.O(SPI1_SS_T));
VCC VCC
(.P(\<const1> ));
(* BOX_TYPE = "PRIMITIVE" *)
BUFG \buffer_fclk_clk_0.FCLK_CLK_0_BUFG
(.I(FCLK_CLK_unbuffered),
.O(FCLK_CLK0));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[0].MIO_BIBUF
(.IO(buffered_MIO[0]),
.PAD(MIO[0]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[10].MIO_BIBUF
(.IO(buffered_MIO[10]),
.PAD(MIO[10]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[11].MIO_BIBUF
(.IO(buffered_MIO[11]),
.PAD(MIO[11]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[12].MIO_BIBUF
(.IO(buffered_MIO[12]),
.PAD(MIO[12]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[13].MIO_BIBUF
(.IO(buffered_MIO[13]),
.PAD(MIO[13]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[14].MIO_BIBUF
(.IO(buffered_MIO[14]),
.PAD(MIO[14]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[15].MIO_BIBUF
(.IO(buffered_MIO[15]),
.PAD(MIO[15]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[16].MIO_BIBUF
(.IO(buffered_MIO[16]),
.PAD(MIO[16]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[17].MIO_BIBUF
(.IO(buffered_MIO[17]),
.PAD(MIO[17]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[18].MIO_BIBUF
(.IO(buffered_MIO[18]),
.PAD(MIO[18]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[19].MIO_BIBUF
(.IO(buffered_MIO[19]),
.PAD(MIO[19]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[1].MIO_BIBUF
(.IO(buffered_MIO[1]),
.PAD(MIO[1]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[20].MIO_BIBUF
(.IO(buffered_MIO[20]),
.PAD(MIO[20]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[21].MIO_BIBUF
(.IO(buffered_MIO[21]),
.PAD(MIO[21]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[22].MIO_BIBUF
(.IO(buffered_MIO[22]),
.PAD(MIO[22]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[23].MIO_BIBUF
(.IO(buffered_MIO[23]),
.PAD(MIO[23]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[24].MIO_BIBUF
(.IO(buffered_MIO[24]),
.PAD(MIO[24]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[25].MIO_BIBUF
(.IO(buffered_MIO[25]),
.PAD(MIO[25]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[26].MIO_BIBUF
(.IO(buffered_MIO[26]),
.PAD(MIO[26]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[27].MIO_BIBUF
(.IO(buffered_MIO[27]),
.PAD(MIO[27]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[28].MIO_BIBUF
(.IO(buffered_MIO[28]),
.PAD(MIO[28]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[29].MIO_BIBUF
(.IO(buffered_MIO[29]),
.PAD(MIO[29]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[2].MIO_BIBUF
(.IO(buffered_MIO[2]),
.PAD(MIO[2]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[30].MIO_BIBUF
(.IO(buffered_MIO[30]),
.PAD(MIO[30]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[31].MIO_BIBUF
(.IO(buffered_MIO[31]),
.PAD(MIO[31]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[32].MIO_BIBUF
(.IO(buffered_MIO[32]),
.PAD(MIO[32]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[33].MIO_BIBUF
(.IO(buffered_MIO[33]),
.PAD(MIO[33]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[34].MIO_BIBUF
(.IO(buffered_MIO[34]),
.PAD(MIO[34]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[35].MIO_BIBUF
(.IO(buffered_MIO[35]),
.PAD(MIO[35]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[36].MIO_BIBUF
(.IO(buffered_MIO[36]),
.PAD(MIO[36]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[37].MIO_BIBUF
(.IO(buffered_MIO[37]),
.PAD(MIO[37]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[38].MIO_BIBUF
(.IO(buffered_MIO[38]),
.PAD(MIO[38]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[39].MIO_BIBUF
(.IO(buffered_MIO[39]),
.PAD(MIO[39]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[3].MIO_BIBUF
(.IO(buffered_MIO[3]),
.PAD(MIO[3]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[40].MIO_BIBUF
(.IO(buffered_MIO[40]),
.PAD(MIO[40]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[41].MIO_BIBUF
(.IO(buffered_MIO[41]),
.PAD(MIO[41]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[42].MIO_BIBUF
(.IO(buffered_MIO[42]),
.PAD(MIO[42]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[43].MIO_BIBUF
(.IO(buffered_MIO[43]),
.PAD(MIO[43]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[44].MIO_BIBUF
(.IO(buffered_MIO[44]),
.PAD(MIO[44]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[45].MIO_BIBUF
(.IO(buffered_MIO[45]),
.PAD(MIO[45]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[46].MIO_BIBUF
(.IO(buffered_MIO[46]),
.PAD(MIO[46]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[47].MIO_BIBUF
(.IO(buffered_MIO[47]),
.PAD(MIO[47]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[48].MIO_BIBUF
(.IO(buffered_MIO[48]),
.PAD(MIO[48]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[49].MIO_BIBUF
(.IO(buffered_MIO[49]),
.PAD(MIO[49]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[4].MIO_BIBUF
(.IO(buffered_MIO[4]),
.PAD(MIO[4]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[50].MIO_BIBUF
(.IO(buffered_MIO[50]),
.PAD(MIO[50]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[51].MIO_BIBUF
(.IO(buffered_MIO[51]),
.PAD(MIO[51]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[52].MIO_BIBUF
(.IO(buffered_MIO[52]),
.PAD(MIO[52]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[53].MIO_BIBUF
(.IO(buffered_MIO[53]),
.PAD(MIO[53]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[5].MIO_BIBUF
(.IO(buffered_MIO[5]),
.PAD(MIO[5]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[6].MIO_BIBUF
(.IO(buffered_MIO[6]),
.PAD(MIO[6]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[7].MIO_BIBUF
(.IO(buffered_MIO[7]),
.PAD(MIO[7]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[8].MIO_BIBUF
(.IO(buffered_MIO[8]),
.PAD(MIO[8]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[9].MIO_BIBUF
(.IO(buffered_MIO[9]),
.PAD(MIO[9]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk14[0].DDR_BankAddr_BIBUF
(.IO(buffered_DDR_BankAddr[0]),
.PAD(DDR_BankAddr[0]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk14[1].DDR_BankAddr_BIBUF
(.IO(buffered_DDR_BankAddr[1]),
.PAD(DDR_BankAddr[1]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk14[2].DDR_BankAddr_BIBUF
(.IO(buffered_DDR_BankAddr[2]),
.PAD(DDR_BankAddr[2]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[0].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[0]),
.PAD(DDR_Addr[0]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[10].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[10]),
.PAD(DDR_Addr[10]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[11].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[11]),
.PAD(DDR_Addr[11]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[12].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[12]),
.PAD(DDR_Addr[12]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[13].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[13]),
.PAD(DDR_Addr[13]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[14].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[14]),
.PAD(DDR_Addr[14]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[1].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[1]),
.PAD(DDR_Addr[1]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[2].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[2]),
.PAD(DDR_Addr[2]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[3].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[3]),
.PAD(DDR_Addr[3]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[4].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[4]),
.PAD(DDR_Addr[4]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[5].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[5]),
.PAD(DDR_Addr[5]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[6].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[6]),
.PAD(DDR_Addr[6]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[7].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[7]),
.PAD(DDR_Addr[7]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[8].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[8]),
.PAD(DDR_Addr[8]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[9].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[9]),
.PAD(DDR_Addr[9]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk16[0].DDR_DM_BIBUF
(.IO(buffered_DDR_DM[0]),
.PAD(DDR_DM[0]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk16[1].DDR_DM_BIBUF
(.IO(buffered_DDR_DM[1]),
.PAD(DDR_DM[1]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk16[2].DDR_DM_BIBUF
(.IO(buffered_DDR_DM[2]),
.PAD(DDR_DM[2]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk16[3].DDR_DM_BIBUF
(.IO(buffered_DDR_DM[3]),
.PAD(DDR_DM[3]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[0].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[0]),
.PAD(DDR_DQ[0]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[10].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[10]),
.PAD(DDR_DQ[10]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[11].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[11]),
.PAD(DDR_DQ[11]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[12].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[12]),
.PAD(DDR_DQ[12]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[13].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[13]),
.PAD(DDR_DQ[13]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[14].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[14]),
.PAD(DDR_DQ[14]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[15].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[15]),
.PAD(DDR_DQ[15]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[16].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[16]),
.PAD(DDR_DQ[16]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[17].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[17]),
.PAD(DDR_DQ[17]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[18].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[18]),
.PAD(DDR_DQ[18]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[19].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[19]),
.PAD(DDR_DQ[19]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[1].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[1]),
.PAD(DDR_DQ[1]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[20].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[20]),
.PAD(DDR_DQ[20]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[21].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[21]),
.PAD(DDR_DQ[21]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[22].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[22]),
.PAD(DDR_DQ[22]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[23].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[23]),
.PAD(DDR_DQ[23]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[24].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[24]),
.PAD(DDR_DQ[24]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[25].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[25]),
.PAD(DDR_DQ[25]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[26].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[26]),
.PAD(DDR_DQ[26]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[27].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[27]),
.PAD(DDR_DQ[27]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[28].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[28]),
.PAD(DDR_DQ[28]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[29].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[29]),
.PAD(DDR_DQ[29]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[2].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[2]),
.PAD(DDR_DQ[2]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[30].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[30]),
.PAD(DDR_DQ[30]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[31].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[31]),
.PAD(DDR_DQ[31]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[3].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[3]),
.PAD(DDR_DQ[3]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[4].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[4]),
.PAD(DDR_DQ[4]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[5].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[5]),
.PAD(DDR_DQ[5]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[6].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[6]),
.PAD(DDR_DQ[6]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[7].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[7]),
.PAD(DDR_DQ[7]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[8].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[8]),
.PAD(DDR_DQ[8]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[9].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[9]),
.PAD(DDR_DQ[9]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk18[0].DDR_DQS_n_BIBUF
(.IO(buffered_DDR_DQS_n[0]),
.PAD(DDR_DQS_n[0]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk18[1].DDR_DQS_n_BIBUF
(.IO(buffered_DDR_DQS_n[1]),
.PAD(DDR_DQS_n[1]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk18[2].DDR_DQS_n_BIBUF
(.IO(buffered_DDR_DQS_n[2]),
.PAD(DDR_DQS_n[2]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk18[3].DDR_DQS_n_BIBUF
(.IO(buffered_DDR_DQS_n[3]),
.PAD(DDR_DQS_n[3]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk19[0].DDR_DQS_BIBUF
(.IO(buffered_DDR_DQS[0]),
.PAD(DDR_DQS[0]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk19[1].DDR_DQS_BIBUF
(.IO(buffered_DDR_DQS[1]),
.PAD(DDR_DQS[1]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk19[2].DDR_DQS_BIBUF
(.IO(buffered_DDR_DQS[2]),
.PAD(DDR_DQS[2]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk19[3].DDR_DQS_BIBUF
(.IO(buffered_DDR_DQS[3]),
.PAD(DDR_DQS[3]));
LUT1 #(
.INIT(2'h2))
i_0
(.I0(1'b0),
.O(\TRACE_CTL_PIPE[0] ));
LUT1 #(
.INIT(2'h2))
i_1
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[0] [1]));
LUT1 #(
.INIT(2'h2))
i_10
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[7] [1]));
LUT1 #(
.INIT(2'h2))
i_11
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[7] [0]));
LUT1 #(
.INIT(2'h2))
i_12
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[6] [1]));
LUT1 #(
.INIT(2'h2))
i_13
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[6] [0]));
LUT1 #(
.INIT(2'h2))
i_14
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[5] [1]));
LUT1 #(
.INIT(2'h2))
i_15
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[5] [0]));
LUT1 #(
.INIT(2'h2))
i_16
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[4] [1]));
LUT1 #(
.INIT(2'h2))
i_17
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[4] [0]));
LUT1 #(
.INIT(2'h2))
i_18
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[3] [1]));
LUT1 #(
.INIT(2'h2))
i_19
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[3] [0]));
LUT1 #(
.INIT(2'h2))
i_2
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[0] [0]));
LUT1 #(
.INIT(2'h2))
i_20
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[2] [1]));
LUT1 #(
.INIT(2'h2))
i_21
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[2] [0]));
LUT1 #(
.INIT(2'h2))
i_22
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[1] [1]));
LUT1 #(
.INIT(2'h2))
i_23
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[1] [0]));
LUT1 #(
.INIT(2'h2))
i_3
(.I0(1'b0),
.O(\TRACE_CTL_PIPE[7] ));
LUT1 #(
.INIT(2'h2))
i_4
(.I0(1'b0),
.O(\TRACE_CTL_PIPE[6] ));
LUT1 #(
.INIT(2'h2))
i_5
(.I0(1'b0),
.O(\TRACE_CTL_PIPE[5] ));
LUT1 #(
.INIT(2'h2))
i_6
(.I0(1'b0),
.O(\TRACE_CTL_PIPE[4] ));
LUT1 #(
.INIT(2'h2))
i_7
(.I0(1'b0),
.O(\TRACE_CTL_PIPE[3] ));
LUT1 #(
.INIT(2'h2))
i_8
(.I0(1'b0),
.O(\TRACE_CTL_PIPE[2] ));
LUT1 #(
.INIT(2'h2))
i_9
(.I0(1'b0),
.O(\TRACE_CTL_PIPE[1] ));
endmodule |
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix
(TTC0_WAVE0_OUT,
TTC0_WAVE1_OUT,
TTC0_WAVE2_OUT,
USB0_PORT_INDCTL,
USB0_VBUS_PWRSELECT,
USB0_VBUS_PWRFAULT,
M_AXI_GP0_ARVALID,
M_AXI_GP0_AWVALID,
M_AXI_GP0_BREADY,
M_AXI_GP0_RREADY,
M_AXI_GP0_WLAST,
M_AXI_GP0_WVALID,
M_AXI_GP0_ARID,
M_AXI_GP0_AWID,
M_AXI_GP0_WID,
M_AXI_GP0_ARBURST,
M_AXI_GP0_ARLOCK,
M_AXI_GP0_ARSIZE,
M_AXI_GP0_AWBURST,
M_AXI_GP0_AWLOCK,
M_AXI_GP0_AWSIZE,
M_AXI_GP0_ARPROT,
M_AXI_GP0_AWPROT,
M_AXI_GP0_ARADDR,
M_AXI_GP0_AWADDR,
M_AXI_GP0_WDATA,
M_AXI_GP0_ARCACHE,
M_AXI_GP0_ARLEN,
M_AXI_GP0_ARQOS,
M_AXI_GP0_AWCACHE,
M_AXI_GP0_AWLEN,
M_AXI_GP0_AWQOS,
M_AXI_GP0_WSTRB,
M_AXI_GP0_ACLK,
M_AXI_GP0_ARREADY,
M_AXI_GP0_AWREADY,
M_AXI_GP0_BVALID,
M_AXI_GP0_RLAST,
M_AXI_GP0_RVALID,
M_AXI_GP0_WREADY,
M_AXI_GP0_BID,
M_AXI_GP0_RID,
M_AXI_GP0_BRESP,
M_AXI_GP0_RRESP,
M_AXI_GP0_RDATA,
IRQ_F2P,
FCLK_CLK0,
FCLK_RESET0_N,
MIO,
DDR_CAS_n,
DDR_CKE,
DDR_Clk_n,
DDR_Clk,
DDR_CS_n,
DDR_DRSTB,
DDR_ODT,
DDR_RAS_n,
DDR_WEB,
DDR_BankAddr,
DDR_Addr,
DDR_VRN,
DDR_VRP,
DDR_DM,
DDR_DQ,
DDR_DQS_n,
DDR_DQS,
PS_SRSTB,
PS_CLK,
PS_PORB);
output TTC0_WAVE0_OUT;
output TTC0_WAVE1_OUT;
output TTC0_WAVE2_OUT;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:usbctrl:1.0 USBIND_0 PORT_INDCTL" *) output [1:0]USB0_PORT_INDCTL;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:usbctrl:1.0 USBIND_0 VBUS_PWRSELECT" *) output USB0_VBUS_PWRSELECT;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:usbctrl:1.0 USBIND_0 VBUS_PWRFAULT" *) input USB0_VBUS_PWRFAULT;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARVALID" *) output M_AXI_GP0_ARVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWVALID" *) output M_AXI_GP0_AWVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BREADY" *) output M_AXI_GP0_BREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RREADY" *) output M_AXI_GP0_RREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WLAST" *) output M_AXI_GP0_WLAST;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WVALID" *) output M_AXI_GP0_WVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARID" *) output [11:0]M_AXI_GP0_ARID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWID" *) output [11:0]M_AXI_GP0_AWID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WID" *) output [11:0]M_AXI_GP0_WID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARBURST" *) output [1:0]M_AXI_GP0_ARBURST;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARLOCK" *) output [1:0]M_AXI_GP0_ARLOCK;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARSIZE" *) output [2:0]M_AXI_GP0_ARSIZE;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWBURST" *) output [1:0]M_AXI_GP0_AWBURST;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWLOCK" *) output [1:0]M_AXI_GP0_AWLOCK;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWSIZE" *) output [2:0]M_AXI_GP0_AWSIZE;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARPROT" *) output [2:0]M_AXI_GP0_ARPROT;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWPROT" *) output [2:0]M_AXI_GP0_AWPROT;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARADDR" *) output [31:0]M_AXI_GP0_ARADDR;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWADDR" *) output [31:0]M_AXI_GP0_AWADDR;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WDATA" *) output [31:0]M_AXI_GP0_WDATA;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARCACHE" *) output [3:0]M_AXI_GP0_ARCACHE;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARLEN" *) output [3:0]M_AXI_GP0_ARLEN;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARQOS" *) output [3:0]M_AXI_GP0_ARQOS;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWCACHE" *) output [3:0]M_AXI_GP0_AWCACHE;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWLEN" *) output [3:0]M_AXI_GP0_AWLEN;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWQOS" *) output [3:0]M_AXI_GP0_AWQOS;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WSTRB" *) output [3:0]M_AXI_GP0_WSTRB;
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 M_AXI_GP0_ACLK CLK" *) input M_AXI_GP0_ACLK;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARREADY" *) input M_AXI_GP0_ARREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWREADY" *) input M_AXI_GP0_AWREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BVALID" *) input M_AXI_GP0_BVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RLAST" *) input M_AXI_GP0_RLAST;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RVALID" *) input M_AXI_GP0_RVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WREADY" *) input M_AXI_GP0_WREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BID" *) input [11:0]M_AXI_GP0_BID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RID" *) input [11:0]M_AXI_GP0_RID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BRESP" *) input [1:0]M_AXI_GP0_BRESP;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RRESP" *) input [1:0]M_AXI_GP0_RRESP;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RDATA" *) input [31:0]M_AXI_GP0_RDATA;
(* X_INTERFACE_INFO = "xilinx.com:signal:interrupt:1.0 IRQ_F2P INTERRUPT" *) input [1:0]IRQ_F2P;
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 FCLK_CLK0 CLK" *) output FCLK_CLK0;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 FCLK_RESET0_N RST" *) output FCLK_RESET0_N;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO MIO" *) inout [53:0]MIO;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CAS_N" *) inout DDR_CAS_n;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CKE" *) inout DDR_CKE;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CK_N" *) inout DDR_Clk_n;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CK_P" *) inout DDR_Clk;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CS_N" *) inout DDR_CS_n;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR RESET_N" *) inout DDR_DRSTB;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR ODT" *) inout DDR_ODT;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR RAS_N" *) inout DDR_RAS_n;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR WE_N" *) inout DDR_WEB;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR BA" *) inout [2:0]DDR_BankAddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR ADDR" *) inout [14:0]DDR_Addr;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO DDR_VRN" *) inout DDR_VRN;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO DDR_VRP" *) inout DDR_VRP;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DM" *) inout [3:0]DDR_DM;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DQ" *) inout [31:0]DDR_DQ;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DQS_N" *) inout [3:0]DDR_DQS_n;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DQS_P" *) inout [3:0]DDR_DQS;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_SRSTB" *) inout PS_SRSTB;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_CLK" *) inout PS_CLK;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_PORB" *) inout PS_PORB;
wire [14:0]DDR_Addr;
wire [2:0]DDR_BankAddr;
wire DDR_CAS_n;
wire DDR_CKE;
wire DDR_CS_n;
wire DDR_Clk;
wire DDR_Clk_n;
wire [3:0]DDR_DM;
wire [31:0]DDR_DQ;
wire [3:0]DDR_DQS;
wire [3:0]DDR_DQS_n;
wire DDR_DRSTB;
wire DDR_ODT;
wire DDR_RAS_n;
wire DDR_VRN;
wire DDR_VRP;
wire DDR_WEB;
wire FCLK_CLK0;
wire FCLK_RESET0_N;
wire [1:0]IRQ_F2P;
wire [53:0]MIO;
wire M_AXI_GP0_ACLK;
wire [31:0]M_AXI_GP0_ARADDR;
wire [1:0]M_AXI_GP0_ARBURST;
wire [3:0]M_AXI_GP0_ARCACHE;
wire [11:0]M_AXI_GP0_ARID;
wire [3:0]M_AXI_GP0_ARLEN;
wire [1:0]M_AXI_GP0_ARLOCK;
wire [2:0]M_AXI_GP0_ARPROT;
wire [3:0]M_AXI_GP0_ARQOS;
wire M_AXI_GP0_ARREADY;
wire [2:0]M_AXI_GP0_ARSIZE;
wire M_AXI_GP0_ARVALID;
wire [31:0]M_AXI_GP0_AWADDR;
wire [1:0]M_AXI_GP0_AWBURST;
wire [3:0]M_AXI_GP0_AWCACHE;
wire [11:0]M_AXI_GP0_AWID;
wire [3:0]M_AXI_GP0_AWLEN;
wire [1:0]M_AXI_GP0_AWLOCK;
wire [2:0]M_AXI_GP0_AWPROT;
wire [3:0]M_AXI_GP0_AWQOS;
wire M_AXI_GP0_AWREADY;
wire [2:0]M_AXI_GP0_AWSIZE;
wire M_AXI_GP0_AWVALID;
wire [11:0]M_AXI_GP0_BID;
wire M_AXI_GP0_BREADY;
wire [1:0]M_AXI_GP0_BRESP;
wire M_AXI_GP0_BVALID;
wire [31:0]M_AXI_GP0_RDATA;
wire [11:0]M_AXI_GP0_RID;
wire M_AXI_GP0_RLAST;
wire M_AXI_GP0_RREADY;
wire [1:0]M_AXI_GP0_RRESP;
wire M_AXI_GP0_RVALID;
wire [31:0]M_AXI_GP0_WDATA;
wire [11:0]M_AXI_GP0_WID;
wire M_AXI_GP0_WLAST;
wire M_AXI_GP0_WREADY;
wire [3:0]M_AXI_GP0_WSTRB;
wire M_AXI_GP0_WVALID;
wire PS_CLK;
wire PS_PORB;
wire PS_SRSTB;
wire TTC0_WAVE0_OUT;
wire TTC0_WAVE1_OUT;
wire TTC0_WAVE2_OUT;
wire [1:0]USB0_PORT_INDCTL;
wire USB0_VBUS_PWRFAULT;
wire USB0_VBUS_PWRSELECT;
wire NLW_inst_CAN0_PHY_TX_UNCONNECTED;
wire NLW_inst_CAN1_PHY_TX_UNCONNECTED;
wire NLW_inst_DMA0_DAVALID_UNCONNECTED;
wire NLW_inst_DMA0_DRREADY_UNCONNECTED;
wire NLW_inst_DMA0_RSTN_UNCONNECTED;
wire NLW_inst_DMA1_DAVALID_UNCONNECTED;
wire NLW_inst_DMA1_DRREADY_UNCONNECTED;
wire NLW_inst_DMA1_RSTN_UNCONNECTED;
wire NLW_inst_DMA2_DAVALID_UNCONNECTED;
wire NLW_inst_DMA2_DRREADY_UNCONNECTED;
wire NLW_inst_DMA2_RSTN_UNCONNECTED;
wire NLW_inst_DMA3_DAVALID_UNCONNECTED;
wire NLW_inst_DMA3_DRREADY_UNCONNECTED;
wire NLW_inst_DMA3_RSTN_UNCONNECTED;
wire NLW_inst_ENET0_GMII_TX_EN_UNCONNECTED;
wire NLW_inst_ENET0_GMII_TX_ER_UNCONNECTED;
wire NLW_inst_ENET0_MDIO_MDC_UNCONNECTED;
wire NLW_inst_ENET0_MDIO_O_UNCONNECTED;
wire NLW_inst_ENET0_MDIO_T_UNCONNECTED;
wire NLW_inst_ENET0_PTP_DELAY_REQ_RX_UNCONNECTED;
wire NLW_inst_ENET0_PTP_DELAY_REQ_TX_UNCONNECTED;
wire NLW_inst_ENET0_PTP_PDELAY_REQ_RX_UNCONNECTED;
wire NLW_inst_ENET0_PTP_PDELAY_REQ_TX_UNCONNECTED;
wire NLW_inst_ENET0_PTP_PDELAY_RESP_RX_UNCONNECTED;
wire NLW_inst_ENET0_PTP_PDELAY_RESP_TX_UNCONNECTED;
wire NLW_inst_ENET0_PTP_SYNC_FRAME_RX_UNCONNECTED;
wire NLW_inst_ENET0_PTP_SYNC_FRAME_TX_UNCONNECTED;
wire NLW_inst_ENET0_SOF_RX_UNCONNECTED;
wire NLW_inst_ENET0_SOF_TX_UNCONNECTED;
wire NLW_inst_ENET1_GMII_TX_EN_UNCONNECTED;
wire NLW_inst_ENET1_GMII_TX_ER_UNCONNECTED;
wire NLW_inst_ENET1_MDIO_MDC_UNCONNECTED;
wire NLW_inst_ENET1_MDIO_O_UNCONNECTED;
wire NLW_inst_ENET1_MDIO_T_UNCONNECTED;
wire NLW_inst_ENET1_PTP_DELAY_REQ_RX_UNCONNECTED;
wire NLW_inst_ENET1_PTP_DELAY_REQ_TX_UNCONNECTED;
wire NLW_inst_ENET1_PTP_PDELAY_REQ_RX_UNCONNECTED;
wire NLW_inst_ENET1_PTP_PDELAY_REQ_TX_UNCONNECTED;
wire NLW_inst_ENET1_PTP_PDELAY_RESP_RX_UNCONNECTED;
wire NLW_inst_ENET1_PTP_PDELAY_RESP_TX_UNCONNECTED;
wire NLW_inst_ENET1_PTP_SYNC_FRAME_RX_UNCONNECTED;
wire NLW_inst_ENET1_PTP_SYNC_FRAME_TX_UNCONNECTED;
wire NLW_inst_ENET1_SOF_RX_UNCONNECTED;
wire NLW_inst_ENET1_SOF_TX_UNCONNECTED;
wire NLW_inst_EVENT_EVENTO_UNCONNECTED;
wire NLW_inst_FCLK_CLK1_UNCONNECTED;
wire NLW_inst_FCLK_CLK2_UNCONNECTED;
wire NLW_inst_FCLK_CLK3_UNCONNECTED;
wire NLW_inst_FCLK_RESET1_N_UNCONNECTED;
wire NLW_inst_FCLK_RESET2_N_UNCONNECTED;
wire NLW_inst_FCLK_RESET3_N_UNCONNECTED;
wire NLW_inst_FTMT_F2P_TRIGACK_0_UNCONNECTED;
wire NLW_inst_FTMT_F2P_TRIGACK_1_UNCONNECTED;
wire NLW_inst_FTMT_F2P_TRIGACK_2_UNCONNECTED;
wire NLW_inst_FTMT_F2P_TRIGACK_3_UNCONNECTED;
wire NLW_inst_FTMT_P2F_TRIG_0_UNCONNECTED;
wire NLW_inst_FTMT_P2F_TRIG_1_UNCONNECTED;
wire NLW_inst_FTMT_P2F_TRIG_2_UNCONNECTED;
wire NLW_inst_FTMT_P2F_TRIG_3_UNCONNECTED;
wire NLW_inst_I2C0_SCL_O_UNCONNECTED;
wire NLW_inst_I2C0_SCL_T_UNCONNECTED;
wire NLW_inst_I2C0_SDA_O_UNCONNECTED;
wire NLW_inst_I2C0_SDA_T_UNCONNECTED;
wire NLW_inst_I2C1_SCL_O_UNCONNECTED;
wire NLW_inst_I2C1_SCL_T_UNCONNECTED;
wire NLW_inst_I2C1_SDA_O_UNCONNECTED;
wire NLW_inst_I2C1_SDA_T_UNCONNECTED;
wire NLW_inst_IRQ_P2F_CAN0_UNCONNECTED;
wire NLW_inst_IRQ_P2F_CAN1_UNCONNECTED;
wire NLW_inst_IRQ_P2F_CTI_UNCONNECTED;
wire NLW_inst_IRQ_P2F_DMAC0_UNCONNECTED;
wire NLW_inst_IRQ_P2F_DMAC1_UNCONNECTED;
wire NLW_inst_IRQ_P2F_DMAC2_UNCONNECTED;
wire NLW_inst_IRQ_P2F_DMAC3_UNCONNECTED;
wire NLW_inst_IRQ_P2F_DMAC4_UNCONNECTED;
wire NLW_inst_IRQ_P2F_DMAC5_UNCONNECTED;
wire NLW_inst_IRQ_P2F_DMAC6_UNCONNECTED;
wire NLW_inst_IRQ_P2F_DMAC7_UNCONNECTED;
wire NLW_inst_IRQ_P2F_DMAC_ABORT_UNCONNECTED;
wire NLW_inst_IRQ_P2F_ENET0_UNCONNECTED;
wire NLW_inst_IRQ_P2F_ENET1_UNCONNECTED;
wire NLW_inst_IRQ_P2F_ENET_WAKE0_UNCONNECTED;
wire NLW_inst_IRQ_P2F_ENET_WAKE1_UNCONNECTED;
wire NLW_inst_IRQ_P2F_GPIO_UNCONNECTED;
wire NLW_inst_IRQ_P2F_I2C0_UNCONNECTED;
wire NLW_inst_IRQ_P2F_I2C1_UNCONNECTED;
wire NLW_inst_IRQ_P2F_QSPI_UNCONNECTED;
wire NLW_inst_IRQ_P2F_SDIO0_UNCONNECTED;
wire NLW_inst_IRQ_P2F_SDIO1_UNCONNECTED;
wire NLW_inst_IRQ_P2F_SMC_UNCONNECTED;
wire NLW_inst_IRQ_P2F_SPI0_UNCONNECTED;
wire NLW_inst_IRQ_P2F_SPI1_UNCONNECTED;
wire NLW_inst_IRQ_P2F_UART0_UNCONNECTED;
wire NLW_inst_IRQ_P2F_UART1_UNCONNECTED;
wire NLW_inst_IRQ_P2F_USB0_UNCONNECTED;
wire NLW_inst_IRQ_P2F_USB1_UNCONNECTED;
wire NLW_inst_M_AXI_GP0_ARESETN_UNCONNECTED;
wire NLW_inst_M_AXI_GP1_ARESETN_UNCONNECTED;
wire NLW_inst_M_AXI_GP1_ARVALID_UNCONNECTED;
wire NLW_inst_M_AXI_GP1_AWVALID_UNCONNECTED;
wire NLW_inst_M_AXI_GP1_BREADY_UNCONNECTED;
wire NLW_inst_M_AXI_GP1_RREADY_UNCONNECTED;
wire NLW_inst_M_AXI_GP1_WLAST_UNCONNECTED;
wire NLW_inst_M_AXI_GP1_WVALID_UNCONNECTED;
wire NLW_inst_PJTAG_TDO_UNCONNECTED;
wire NLW_inst_SDIO0_BUSPOW_UNCONNECTED;
wire NLW_inst_SDIO0_CLK_UNCONNECTED;
wire NLW_inst_SDIO0_CMD_O_UNCONNECTED;
wire NLW_inst_SDIO0_CMD_T_UNCONNECTED;
wire NLW_inst_SDIO0_LED_UNCONNECTED;
wire NLW_inst_SDIO1_BUSPOW_UNCONNECTED;
wire NLW_inst_SDIO1_CLK_UNCONNECTED;
wire NLW_inst_SDIO1_CMD_O_UNCONNECTED;
wire NLW_inst_SDIO1_CMD_T_UNCONNECTED;
wire NLW_inst_SDIO1_LED_UNCONNECTED;
wire NLW_inst_SPI0_MISO_O_UNCONNECTED;
wire NLW_inst_SPI0_MISO_T_UNCONNECTED;
wire NLW_inst_SPI0_MOSI_O_UNCONNECTED;
wire NLW_inst_SPI0_MOSI_T_UNCONNECTED;
wire NLW_inst_SPI0_SCLK_O_UNCONNECTED;
wire NLW_inst_SPI0_SCLK_T_UNCONNECTED;
wire NLW_inst_SPI0_SS1_O_UNCONNECTED;
wire NLW_inst_SPI0_SS2_O_UNCONNECTED;
wire NLW_inst_SPI0_SS_O_UNCONNECTED;
wire NLW_inst_SPI0_SS_T_UNCONNECTED;
wire NLW_inst_SPI1_MISO_O_UNCONNECTED;
wire NLW_inst_SPI1_MISO_T_UNCONNECTED;
wire NLW_inst_SPI1_MOSI_O_UNCONNECTED;
wire NLW_inst_SPI1_MOSI_T_UNCONNECTED;
wire NLW_inst_SPI1_SCLK_O_UNCONNECTED;
wire NLW_inst_SPI1_SCLK_T_UNCONNECTED;
wire NLW_inst_SPI1_SS1_O_UNCONNECTED;
wire NLW_inst_SPI1_SS2_O_UNCONNECTED;
wire NLW_inst_SPI1_SS_O_UNCONNECTED;
wire NLW_inst_SPI1_SS_T_UNCONNECTED;
wire NLW_inst_S_AXI_ACP_ARESETN_UNCONNECTED;
wire NLW_inst_S_AXI_ACP_ARREADY_UNCONNECTED;
wire NLW_inst_S_AXI_ACP_AWREADY_UNCONNECTED;
wire NLW_inst_S_AXI_ACP_BVALID_UNCONNECTED;
wire NLW_inst_S_AXI_ACP_RLAST_UNCONNECTED;
wire NLW_inst_S_AXI_ACP_RVALID_UNCONNECTED;
wire NLW_inst_S_AXI_ACP_WREADY_UNCONNECTED;
wire NLW_inst_S_AXI_GP0_ARESETN_UNCONNECTED;
wire NLW_inst_S_AXI_GP0_ARREADY_UNCONNECTED;
wire NLW_inst_S_AXI_GP0_AWREADY_UNCONNECTED;
wire NLW_inst_S_AXI_GP0_BVALID_UNCONNECTED;
wire NLW_inst_S_AXI_GP0_RLAST_UNCONNECTED;
wire NLW_inst_S_AXI_GP0_RVALID_UNCONNECTED;
wire NLW_inst_S_AXI_GP0_WREADY_UNCONNECTED;
wire NLW_inst_S_AXI_GP1_ARESETN_UNCONNECTED;
wire NLW_inst_S_AXI_GP1_ARREADY_UNCONNECTED;
wire NLW_inst_S_AXI_GP1_AWREADY_UNCONNECTED;
wire NLW_inst_S_AXI_GP1_BVALID_UNCONNECTED;
wire NLW_inst_S_AXI_GP1_RLAST_UNCONNECTED;
wire NLW_inst_S_AXI_GP1_RVALID_UNCONNECTED;
wire NLW_inst_S_AXI_GP1_WREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP0_ARESETN_UNCONNECTED;
wire NLW_inst_S_AXI_HP0_ARREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP0_AWREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP0_BVALID_UNCONNECTED;
wire NLW_inst_S_AXI_HP0_RLAST_UNCONNECTED;
wire NLW_inst_S_AXI_HP0_RVALID_UNCONNECTED;
wire NLW_inst_S_AXI_HP0_WREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP1_ARESETN_UNCONNECTED;
wire NLW_inst_S_AXI_HP1_ARREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP1_AWREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP1_BVALID_UNCONNECTED;
wire NLW_inst_S_AXI_HP1_RLAST_UNCONNECTED;
wire NLW_inst_S_AXI_HP1_RVALID_UNCONNECTED;
wire NLW_inst_S_AXI_HP1_WREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP2_ARESETN_UNCONNECTED;
wire NLW_inst_S_AXI_HP2_ARREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP2_AWREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP2_BVALID_UNCONNECTED;
wire NLW_inst_S_AXI_HP2_RLAST_UNCONNECTED;
wire NLW_inst_S_AXI_HP2_RVALID_UNCONNECTED;
wire NLW_inst_S_AXI_HP2_WREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP3_ARESETN_UNCONNECTED;
wire NLW_inst_S_AXI_HP3_ARREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP3_AWREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP3_BVALID_UNCONNECTED;
wire NLW_inst_S_AXI_HP3_RLAST_UNCONNECTED;
wire NLW_inst_S_AXI_HP3_RVALID_UNCONNECTED;
wire NLW_inst_S_AXI_HP3_WREADY_UNCONNECTED;
wire NLW_inst_TRACE_CLK_OUT_UNCONNECTED;
wire NLW_inst_TRACE_CTL_UNCONNECTED;
wire NLW_inst_TTC1_WAVE0_OUT_UNCONNECTED;
wire NLW_inst_TTC1_WAVE1_OUT_UNCONNECTED;
wire NLW_inst_TTC1_WAVE2_OUT_UNCONNECTED;
wire NLW_inst_UART0_DTRN_UNCONNECTED;
wire NLW_inst_UART0_RTSN_UNCONNECTED;
wire NLW_inst_UART0_TX_UNCONNECTED;
wire NLW_inst_UART1_DTRN_UNCONNECTED;
wire NLW_inst_UART1_RTSN_UNCONNECTED;
wire NLW_inst_UART1_TX_UNCONNECTED;
wire NLW_inst_USB1_VBUS_PWRSELECT_UNCONNECTED;
wire NLW_inst_WDT_RST_OUT_UNCONNECTED;
wire [1:0]NLW_inst_DMA0_DATYPE_UNCONNECTED;
wire [1:0]NLW_inst_DMA1_DATYPE_UNCONNECTED;
wire [1:0]NLW_inst_DMA2_DATYPE_UNCONNECTED;
wire [1:0]NLW_inst_DMA3_DATYPE_UNCONNECTED;
wire [7:0]NLW_inst_ENET0_GMII_TXD_UNCONNECTED;
wire [7:0]NLW_inst_ENET1_GMII_TXD_UNCONNECTED;
wire [1:0]NLW_inst_EVENT_STANDBYWFE_UNCONNECTED;
wire [1:0]NLW_inst_EVENT_STANDBYWFI_UNCONNECTED;
wire [31:0]NLW_inst_FTMT_P2F_DEBUG_UNCONNECTED;
wire [63:0]NLW_inst_GPIO_O_UNCONNECTED;
wire [63:0]NLW_inst_GPIO_T_UNCONNECTED;
wire [31:0]NLW_inst_M_AXI_GP1_ARADDR_UNCONNECTED;
wire [1:0]NLW_inst_M_AXI_GP1_ARBURST_UNCONNECTED;
wire [3:0]NLW_inst_M_AXI_GP1_ARCACHE_UNCONNECTED;
wire [11:0]NLW_inst_M_AXI_GP1_ARID_UNCONNECTED;
wire [3:0]NLW_inst_M_AXI_GP1_ARLEN_UNCONNECTED;
wire [1:0]NLW_inst_M_AXI_GP1_ARLOCK_UNCONNECTED;
wire [2:0]NLW_inst_M_AXI_GP1_ARPROT_UNCONNECTED;
wire [3:0]NLW_inst_M_AXI_GP1_ARQOS_UNCONNECTED;
wire [2:0]NLW_inst_M_AXI_GP1_ARSIZE_UNCONNECTED;
wire [31:0]NLW_inst_M_AXI_GP1_AWADDR_UNCONNECTED;
wire [1:0]NLW_inst_M_AXI_GP1_AWBURST_UNCONNECTED;
wire [3:0]NLW_inst_M_AXI_GP1_AWCACHE_UNCONNECTED;
wire [11:0]NLW_inst_M_AXI_GP1_AWID_UNCONNECTED;
wire [3:0]NLW_inst_M_AXI_GP1_AWLEN_UNCONNECTED;
wire [1:0]NLW_inst_M_AXI_GP1_AWLOCK_UNCONNECTED;
wire [2:0]NLW_inst_M_AXI_GP1_AWPROT_UNCONNECTED;
wire [3:0]NLW_inst_M_AXI_GP1_AWQOS_UNCONNECTED;
wire [2:0]NLW_inst_M_AXI_GP1_AWSIZE_UNCONNECTED;
wire [31:0]NLW_inst_M_AXI_GP1_WDATA_UNCONNECTED;
wire [11:0]NLW_inst_M_AXI_GP1_WID_UNCONNECTED;
wire [3:0]NLW_inst_M_AXI_GP1_WSTRB_UNCONNECTED;
wire [2:0]NLW_inst_SDIO0_BUSVOLT_UNCONNECTED;
wire [3:0]NLW_inst_SDIO0_DATA_O_UNCONNECTED;
wire [3:0]NLW_inst_SDIO0_DATA_T_UNCONNECTED;
wire [2:0]NLW_inst_SDIO1_BUSVOLT_UNCONNECTED;
wire [3:0]NLW_inst_SDIO1_DATA_O_UNCONNECTED;
wire [3:0]NLW_inst_SDIO1_DATA_T_UNCONNECTED;
wire [2:0]NLW_inst_S_AXI_ACP_BID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_ACP_BRESP_UNCONNECTED;
wire [63:0]NLW_inst_S_AXI_ACP_RDATA_UNCONNECTED;
wire [2:0]NLW_inst_S_AXI_ACP_RID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_ACP_RRESP_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_GP0_BID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_GP0_BRESP_UNCONNECTED;
wire [31:0]NLW_inst_S_AXI_GP0_RDATA_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_GP0_RID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_GP0_RRESP_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_GP1_BID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_GP1_BRESP_UNCONNECTED;
wire [31:0]NLW_inst_S_AXI_GP1_RDATA_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_GP1_RID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_GP1_RRESP_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP0_BID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_HP0_BRESP_UNCONNECTED;
wire [2:0]NLW_inst_S_AXI_HP0_RACOUNT_UNCONNECTED;
wire [7:0]NLW_inst_S_AXI_HP0_RCOUNT_UNCONNECTED;
wire [63:0]NLW_inst_S_AXI_HP0_RDATA_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP0_RID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_HP0_RRESP_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP0_WACOUNT_UNCONNECTED;
wire [7:0]NLW_inst_S_AXI_HP0_WCOUNT_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP1_BID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_HP1_BRESP_UNCONNECTED;
wire [2:0]NLW_inst_S_AXI_HP1_RACOUNT_UNCONNECTED;
wire [7:0]NLW_inst_S_AXI_HP1_RCOUNT_UNCONNECTED;
wire [63:0]NLW_inst_S_AXI_HP1_RDATA_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP1_RID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_HP1_RRESP_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP1_WACOUNT_UNCONNECTED;
wire [7:0]NLW_inst_S_AXI_HP1_WCOUNT_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP2_BID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_HP2_BRESP_UNCONNECTED;
wire [2:0]NLW_inst_S_AXI_HP2_RACOUNT_UNCONNECTED;
wire [7:0]NLW_inst_S_AXI_HP2_RCOUNT_UNCONNECTED;
wire [63:0]NLW_inst_S_AXI_HP2_RDATA_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP2_RID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_HP2_RRESP_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP2_WACOUNT_UNCONNECTED;
wire [7:0]NLW_inst_S_AXI_HP2_WCOUNT_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP3_BID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_HP3_BRESP_UNCONNECTED;
wire [2:0]NLW_inst_S_AXI_HP3_RACOUNT_UNCONNECTED;
wire [7:0]NLW_inst_S_AXI_HP3_RCOUNT_UNCONNECTED;
wire [63:0]NLW_inst_S_AXI_HP3_RDATA_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP3_RID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_HP3_RRESP_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP3_WACOUNT_UNCONNECTED;
wire [7:0]NLW_inst_S_AXI_HP3_WCOUNT_UNCONNECTED;
wire [1:0]NLW_inst_TRACE_DATA_UNCONNECTED;
wire [1:0]NLW_inst_USB1_PORT_INDCTL_UNCONNECTED;
(* C_DM_WIDTH = "4" *)
(* C_DQS_WIDTH = "4" *)
(* C_DQ_WIDTH = "32" *)
(* C_EMIO_GPIO_WIDTH = "64" *)
(* C_EN_EMIO_ENET0 = "0" *)
(* C_EN_EMIO_ENET1 = "0" *)
(* C_EN_EMIO_PJTAG = "0" *)
(* C_EN_EMIO_TRACE = "0" *)
(* C_FCLK_CLK0_BUF = "TRUE" *)
(* C_FCLK_CLK1_BUF = "FALSE" *)
(* C_FCLK_CLK2_BUF = "FALSE" *)
(* C_FCLK_CLK3_BUF = "FALSE" *)
(* C_GP0_EN_MODIFIABLE_TXN = "1" *)
(* C_GP1_EN_MODIFIABLE_TXN = "1" *)
(* C_INCLUDE_ACP_TRANS_CHECK = "0" *)
(* C_INCLUDE_TRACE_BUFFER = "0" *)
(* C_IRQ_F2P_MODE = "DIRECT" *)
(* C_MIO_PRIMITIVE = "54" *)
(* C_M_AXI_GP0_ENABLE_STATIC_REMAP = "0" *)
(* C_M_AXI_GP0_ID_WIDTH = "12" *)
(* C_M_AXI_GP0_THREAD_ID_WIDTH = "12" *)
(* C_M_AXI_GP1_ENABLE_STATIC_REMAP = "0" *)
(* C_M_AXI_GP1_ID_WIDTH = "12" *)
(* C_M_AXI_GP1_THREAD_ID_WIDTH = "12" *)
(* C_NUM_F2P_INTR_INPUTS = "2" *)
(* C_PACKAGE_NAME = "clg484" *)
(* C_PS7_SI_REV = "PRODUCTION" *)
(* C_S_AXI_ACP_ARUSER_VAL = "31" *)
(* C_S_AXI_ACP_AWUSER_VAL = "31" *)
(* C_S_AXI_ACP_ID_WIDTH = "3" *)
(* C_S_AXI_GP0_ID_WIDTH = "6" *)
(* C_S_AXI_GP1_ID_WIDTH = "6" *)
(* C_S_AXI_HP0_DATA_WIDTH = "64" *)
(* C_S_AXI_HP0_ID_WIDTH = "6" *)
(* C_S_AXI_HP1_DATA_WIDTH = "64" *)
(* C_S_AXI_HP1_ID_WIDTH = "6" *)
(* C_S_AXI_HP2_DATA_WIDTH = "64" *)
(* C_S_AXI_HP2_ID_WIDTH = "6" *)
(* C_S_AXI_HP3_DATA_WIDTH = "64" *)
(* C_S_AXI_HP3_ID_WIDTH = "6" *)
(* C_TRACE_BUFFER_CLOCK_DELAY = "12" *)
(* C_TRACE_BUFFER_FIFO_SIZE = "128" *)
(* C_TRACE_INTERNAL_WIDTH = "2" *)
(* C_TRACE_PIPELINE_WIDTH = "8" *)
(* C_USE_AXI_NONSECURE = "0" *)
(* C_USE_DEFAULT_ACP_USER_VAL = "0" *)
(* C_USE_M_AXI_GP0 = "1" *)
(* C_USE_M_AXI_GP1 = "0" *)
(* C_USE_S_AXI_ACP = "0" *)
(* C_USE_S_AXI_GP0 = "0" *)
(* C_USE_S_AXI_GP1 = "0" *)
(* C_USE_S_AXI_HP0 = "0" *)
(* C_USE_S_AXI_HP1 = "0" *)
(* C_USE_S_AXI_HP2 = "0" *)
(* C_USE_S_AXI_HP3 = "0" *)
(* HW_HANDOFF = "zqynq_lab_1_design_processing_system7_0_1.hwdef" *)
(* POWER = "<PROCESSOR name={system} numA9Cores={2} clockFreq={666.666667} load={0.5} /><MEMORY name={code} memType={DDR3} dataWidth={32} clockFreq={533.333313} readRate={0.5} writeRate={0.5} /><IO interface={GPIO_Bank_1} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={1} usageRate={0.5} /><IO interface={GPIO_Bank_0} ioStandard={LVCMOS33} bidis={10} ioBank={Vcco_p0} clockFreq={1} usageRate={0.5} /><IO interface={Timer} ioStandard={} bidis={0} ioBank={} clockFreq={111.111115} usageRate={0.5} /><IO interface={UART} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={50.000000} usageRate={0.5} /><IO interface={SD} ioStandard={LVCMOS18} bidis={8} ioBank={Vcco_p1} clockFreq={50.000000} usageRate={0.5} /><IO interface={USB} ioStandard={LVCMOS18} bidis={12} ioBank={Vcco_p1} clockFreq={60} usageRate={0.5} /><IO interface={GigE} ioStandard={LVCMOS18} bidis={14} ioBank={Vcco_p1} clockFreq={125.000000} usageRate={0.5} /><IO interface={QSPI} ioStandard={LVCMOS33} bidis={6} ioBank={Vcco_p0} clockFreq={200.000000} usageRate={0.5} /><PLL domain={Processor} vco={1333.333} /><PLL domain={Memory} vco={1066.667} /><PLL domain={IO} vco={1000.000} /><AXI interface={M_AXI_GP0} dataWidth={32} clockFreq={100} usageRate={0.5} />/>" *)
(* USE_TRACE_DATA_EDGE_DETECTOR = "0" *)
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 inst
(.CAN0_PHY_RX(1'b0),
.CAN0_PHY_TX(NLW_inst_CAN0_PHY_TX_UNCONNECTED),
.CAN1_PHY_RX(1'b0),
.CAN1_PHY_TX(NLW_inst_CAN1_PHY_TX_UNCONNECTED),
.Core0_nFIQ(1'b0),
.Core0_nIRQ(1'b0),
.Core1_nFIQ(1'b0),
.Core1_nIRQ(1'b0),
.DDR_ARB({1'b0,1'b0,1'b0,1'b0}),
.DDR_Addr(DDR_Addr),
.DDR_BankAddr(DDR_BankAddr),
.DDR_CAS_n(DDR_CAS_n),
.DDR_CKE(DDR_CKE),
.DDR_CS_n(DDR_CS_n),
.DDR_Clk(DDR_Clk),
.DDR_Clk_n(DDR_Clk_n),
.DDR_DM(DDR_DM),
.DDR_DQ(DDR_DQ),
.DDR_DQS(DDR_DQS),
.DDR_DQS_n(DDR_DQS_n),
.DDR_DRSTB(DDR_DRSTB),
.DDR_ODT(DDR_ODT),
.DDR_RAS_n(DDR_RAS_n),
.DDR_VRN(DDR_VRN),
.DDR_VRP(DDR_VRP),
.DDR_WEB(DDR_WEB),
.DMA0_ACLK(1'b0),
.DMA0_DAREADY(1'b0),
.DMA0_DATYPE(NLW_inst_DMA0_DATYPE_UNCONNECTED[1:0]),
.DMA0_DAVALID(NLW_inst_DMA0_DAVALID_UNCONNECTED),
.DMA0_DRLAST(1'b0),
.DMA0_DRREADY(NLW_inst_DMA0_DRREADY_UNCONNECTED),
.DMA0_DRTYPE({1'b0,1'b0}),
.DMA0_DRVALID(1'b0),
.DMA0_RSTN(NLW_inst_DMA0_RSTN_UNCONNECTED),
.DMA1_ACLK(1'b0),
.DMA1_DAREADY(1'b0),
.DMA1_DATYPE(NLW_inst_DMA1_DATYPE_UNCONNECTED[1:0]),
.DMA1_DAVALID(NLW_inst_DMA1_DAVALID_UNCONNECTED),
.DMA1_DRLAST(1'b0),
.DMA1_DRREADY(NLW_inst_DMA1_DRREADY_UNCONNECTED),
.DMA1_DRTYPE({1'b0,1'b0}),
.DMA1_DRVALID(1'b0),
.DMA1_RSTN(NLW_inst_DMA1_RSTN_UNCONNECTED),
.DMA2_ACLK(1'b0),
.DMA2_DAREADY(1'b0),
.DMA2_DATYPE(NLW_inst_DMA2_DATYPE_UNCONNECTED[1:0]),
.DMA2_DAVALID(NLW_inst_DMA2_DAVALID_UNCONNECTED),
.DMA2_DRLAST(1'b0),
.DMA2_DRREADY(NLW_inst_DMA2_DRREADY_UNCONNECTED),
.DMA2_DRTYPE({1'b0,1'b0}),
.DMA2_DRVALID(1'b0),
.DMA2_RSTN(NLW_inst_DMA2_RSTN_UNCONNECTED),
.DMA3_ACLK(1'b0),
.DMA3_DAREADY(1'b0),
.DMA3_DATYPE(NLW_inst_DMA3_DATYPE_UNCONNECTED[1:0]),
.DMA3_DAVALID(NLW_inst_DMA3_DAVALID_UNCONNECTED),
.DMA3_DRLAST(1'b0),
.DMA3_DRREADY(NLW_inst_DMA3_DRREADY_UNCONNECTED),
.DMA3_DRTYPE({1'b0,1'b0}),
.DMA3_DRVALID(1'b0),
.DMA3_RSTN(NLW_inst_DMA3_RSTN_UNCONNECTED),
.ENET0_EXT_INTIN(1'b0),
.ENET0_GMII_COL(1'b0),
.ENET0_GMII_CRS(1'b0),
.ENET0_GMII_RXD({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.ENET0_GMII_RX_CLK(1'b0),
.ENET0_GMII_RX_DV(1'b0),
.ENET0_GMII_RX_ER(1'b0),
.ENET0_GMII_TXD(NLW_inst_ENET0_GMII_TXD_UNCONNECTED[7:0]),
.ENET0_GMII_TX_CLK(1'b0),
.ENET0_GMII_TX_EN(NLW_inst_ENET0_GMII_TX_EN_UNCONNECTED),
.ENET0_GMII_TX_ER(NLW_inst_ENET0_GMII_TX_ER_UNCONNECTED),
.ENET0_MDIO_I(1'b0),
.ENET0_MDIO_MDC(NLW_inst_ENET0_MDIO_MDC_UNCONNECTED),
.ENET0_MDIO_O(NLW_inst_ENET0_MDIO_O_UNCONNECTED),
.ENET0_MDIO_T(NLW_inst_ENET0_MDIO_T_UNCONNECTED),
.ENET0_PTP_DELAY_REQ_RX(NLW_inst_ENET0_PTP_DELAY_REQ_RX_UNCONNECTED),
.ENET0_PTP_DELAY_REQ_TX(NLW_inst_ENET0_PTP_DELAY_REQ_TX_UNCONNECTED),
.ENET0_PTP_PDELAY_REQ_RX(NLW_inst_ENET0_PTP_PDELAY_REQ_RX_UNCONNECTED),
.ENET0_PTP_PDELAY_REQ_TX(NLW_inst_ENET0_PTP_PDELAY_REQ_TX_UNCONNECTED),
.ENET0_PTP_PDELAY_RESP_RX(NLW_inst_ENET0_PTP_PDELAY_RESP_RX_UNCONNECTED),
.ENET0_PTP_PDELAY_RESP_TX(NLW_inst_ENET0_PTP_PDELAY_RESP_TX_UNCONNECTED),
.ENET0_PTP_SYNC_FRAME_RX(NLW_inst_ENET0_PTP_SYNC_FRAME_RX_UNCONNECTED),
.ENET0_PTP_SYNC_FRAME_TX(NLW_inst_ENET0_PTP_SYNC_FRAME_TX_UNCONNECTED),
.ENET0_SOF_RX(NLW_inst_ENET0_SOF_RX_UNCONNECTED),
.ENET0_SOF_TX(NLW_inst_ENET0_SOF_TX_UNCONNECTED),
.ENET1_EXT_INTIN(1'b0),
.ENET1_GMII_COL(1'b0),
.ENET1_GMII_CRS(1'b0),
.ENET1_GMII_RXD({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.ENET1_GMII_RX_CLK(1'b0),
.ENET1_GMII_RX_DV(1'b0),
.ENET1_GMII_RX_ER(1'b0),
.ENET1_GMII_TXD(NLW_inst_ENET1_GMII_TXD_UNCONNECTED[7:0]),
.ENET1_GMII_TX_CLK(1'b0),
.ENET1_GMII_TX_EN(NLW_inst_ENET1_GMII_TX_EN_UNCONNECTED),
.ENET1_GMII_TX_ER(NLW_inst_ENET1_GMII_TX_ER_UNCONNECTED),
.ENET1_MDIO_I(1'b0),
.ENET1_MDIO_MDC(NLW_inst_ENET1_MDIO_MDC_UNCONNECTED),
.ENET1_MDIO_O(NLW_inst_ENET1_MDIO_O_UNCONNECTED),
.ENET1_MDIO_T(NLW_inst_ENET1_MDIO_T_UNCONNECTED),
.ENET1_PTP_DELAY_REQ_RX(NLW_inst_ENET1_PTP_DELAY_REQ_RX_UNCONNECTED),
.ENET1_PTP_DELAY_REQ_TX(NLW_inst_ENET1_PTP_DELAY_REQ_TX_UNCONNECTED),
.ENET1_PTP_PDELAY_REQ_RX(NLW_inst_ENET1_PTP_PDELAY_REQ_RX_UNCONNECTED),
.ENET1_PTP_PDELAY_REQ_TX(NLW_inst_ENET1_PTP_PDELAY_REQ_TX_UNCONNECTED),
.ENET1_PTP_PDELAY_RESP_RX(NLW_inst_ENET1_PTP_PDELAY_RESP_RX_UNCONNECTED),
.ENET1_PTP_PDELAY_RESP_TX(NLW_inst_ENET1_PTP_PDELAY_RESP_TX_UNCONNECTED),
.ENET1_PTP_SYNC_FRAME_RX(NLW_inst_ENET1_PTP_SYNC_FRAME_RX_UNCONNECTED),
.ENET1_PTP_SYNC_FRAME_TX(NLW_inst_ENET1_PTP_SYNC_FRAME_TX_UNCONNECTED),
.ENET1_SOF_RX(NLW_inst_ENET1_SOF_RX_UNCONNECTED),
.ENET1_SOF_TX(NLW_inst_ENET1_SOF_TX_UNCONNECTED),
.EVENT_EVENTI(1'b0),
.EVENT_EVENTO(NLW_inst_EVENT_EVENTO_UNCONNECTED),
.EVENT_STANDBYWFE(NLW_inst_EVENT_STANDBYWFE_UNCONNECTED[1:0]),
.EVENT_STANDBYWFI(NLW_inst_EVENT_STANDBYWFI_UNCONNECTED[1:0]),
.FCLK_CLK0(FCLK_CLK0),
.FCLK_CLK1(NLW_inst_FCLK_CLK1_UNCONNECTED),
.FCLK_CLK2(NLW_inst_FCLK_CLK2_UNCONNECTED),
.FCLK_CLK3(NLW_inst_FCLK_CLK3_UNCONNECTED),
.FCLK_CLKTRIG0_N(1'b0),
.FCLK_CLKTRIG1_N(1'b0),
.FCLK_CLKTRIG2_N(1'b0),
.FCLK_CLKTRIG3_N(1'b0),
.FCLK_RESET0_N(FCLK_RESET0_N),
.FCLK_RESET1_N(NLW_inst_FCLK_RESET1_N_UNCONNECTED),
.FCLK_RESET2_N(NLW_inst_FCLK_RESET2_N_UNCONNECTED),
.FCLK_RESET3_N(NLW_inst_FCLK_RESET3_N_UNCONNECTED),
.FPGA_IDLE_N(1'b0),
.FTMD_TRACEIN_ATID({1'b0,1'b0,1'b0,1'b0}),
.FTMD_TRACEIN_CLK(1'b0),
.FTMD_TRACEIN_DATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.FTMD_TRACEIN_VALID(1'b0),
.FTMT_F2P_DEBUG({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.FTMT_F2P_TRIGACK_0(NLW_inst_FTMT_F2P_TRIGACK_0_UNCONNECTED),
.FTMT_F2P_TRIGACK_1(NLW_inst_FTMT_F2P_TRIGACK_1_UNCONNECTED),
.FTMT_F2P_TRIGACK_2(NLW_inst_FTMT_F2P_TRIGACK_2_UNCONNECTED),
.FTMT_F2P_TRIGACK_3(NLW_inst_FTMT_F2P_TRIGACK_3_UNCONNECTED),
.FTMT_F2P_TRIG_0(1'b0),
.FTMT_F2P_TRIG_1(1'b0),
.FTMT_F2P_TRIG_2(1'b0),
.FTMT_F2P_TRIG_3(1'b0),
.FTMT_P2F_DEBUG(NLW_inst_FTMT_P2F_DEBUG_UNCONNECTED[31:0]),
.FTMT_P2F_TRIGACK_0(1'b0),
.FTMT_P2F_TRIGACK_1(1'b0),
.FTMT_P2F_TRIGACK_2(1'b0),
.FTMT_P2F_TRIGACK_3(1'b0),
.FTMT_P2F_TRIG_0(NLW_inst_FTMT_P2F_TRIG_0_UNCONNECTED),
.FTMT_P2F_TRIG_1(NLW_inst_FTMT_P2F_TRIG_1_UNCONNECTED),
.FTMT_P2F_TRIG_2(NLW_inst_FTMT_P2F_TRIG_2_UNCONNECTED),
.FTMT_P2F_TRIG_3(NLW_inst_FTMT_P2F_TRIG_3_UNCONNECTED),
.GPIO_I({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.GPIO_O(NLW_inst_GPIO_O_UNCONNECTED[63:0]),
.GPIO_T(NLW_inst_GPIO_T_UNCONNECTED[63:0]),
.I2C0_SCL_I(1'b0),
.I2C0_SCL_O(NLW_inst_I2C0_SCL_O_UNCONNECTED),
.I2C0_SCL_T(NLW_inst_I2C0_SCL_T_UNCONNECTED),
.I2C0_SDA_I(1'b0),
.I2C0_SDA_O(NLW_inst_I2C0_SDA_O_UNCONNECTED),
.I2C0_SDA_T(NLW_inst_I2C0_SDA_T_UNCONNECTED),
.I2C1_SCL_I(1'b0),
.I2C1_SCL_O(NLW_inst_I2C1_SCL_O_UNCONNECTED),
.I2C1_SCL_T(NLW_inst_I2C1_SCL_T_UNCONNECTED),
.I2C1_SDA_I(1'b0),
.I2C1_SDA_O(NLW_inst_I2C1_SDA_O_UNCONNECTED),
.I2C1_SDA_T(NLW_inst_I2C1_SDA_T_UNCONNECTED),
.IRQ_F2P(IRQ_F2P),
.IRQ_P2F_CAN0(NLW_inst_IRQ_P2F_CAN0_UNCONNECTED),
.IRQ_P2F_CAN1(NLW_inst_IRQ_P2F_CAN1_UNCONNECTED),
.IRQ_P2F_CTI(NLW_inst_IRQ_P2F_CTI_UNCONNECTED),
.IRQ_P2F_DMAC0(NLW_inst_IRQ_P2F_DMAC0_UNCONNECTED),
.IRQ_P2F_DMAC1(NLW_inst_IRQ_P2F_DMAC1_UNCONNECTED),
.IRQ_P2F_DMAC2(NLW_inst_IRQ_P2F_DMAC2_UNCONNECTED),
.IRQ_P2F_DMAC3(NLW_inst_IRQ_P2F_DMAC3_UNCONNECTED),
.IRQ_P2F_DMAC4(NLW_inst_IRQ_P2F_DMAC4_UNCONNECTED),
.IRQ_P2F_DMAC5(NLW_inst_IRQ_P2F_DMAC5_UNCONNECTED),
.IRQ_P2F_DMAC6(NLW_inst_IRQ_P2F_DMAC6_UNCONNECTED),
.IRQ_P2F_DMAC7(NLW_inst_IRQ_P2F_DMAC7_UNCONNECTED),
.IRQ_P2F_DMAC_ABORT(NLW_inst_IRQ_P2F_DMAC_ABORT_UNCONNECTED),
.IRQ_P2F_ENET0(NLW_inst_IRQ_P2F_ENET0_UNCONNECTED),
.IRQ_P2F_ENET1(NLW_inst_IRQ_P2F_ENET1_UNCONNECTED),
.IRQ_P2F_ENET_WAKE0(NLW_inst_IRQ_P2F_ENET_WAKE0_UNCONNECTED),
.IRQ_P2F_ENET_WAKE1(NLW_inst_IRQ_P2F_ENET_WAKE1_UNCONNECTED),
.IRQ_P2F_GPIO(NLW_inst_IRQ_P2F_GPIO_UNCONNECTED),
.IRQ_P2F_I2C0(NLW_inst_IRQ_P2F_I2C0_UNCONNECTED),
.IRQ_P2F_I2C1(NLW_inst_IRQ_P2F_I2C1_UNCONNECTED),
.IRQ_P2F_QSPI(NLW_inst_IRQ_P2F_QSPI_UNCONNECTED),
.IRQ_P2F_SDIO0(NLW_inst_IRQ_P2F_SDIO0_UNCONNECTED),
.IRQ_P2F_SDIO1(NLW_inst_IRQ_P2F_SDIO1_UNCONNECTED),
.IRQ_P2F_SMC(NLW_inst_IRQ_P2F_SMC_UNCONNECTED),
.IRQ_P2F_SPI0(NLW_inst_IRQ_P2F_SPI0_UNCONNECTED),
.IRQ_P2F_SPI1(NLW_inst_IRQ_P2F_SPI1_UNCONNECTED),
.IRQ_P2F_UART0(NLW_inst_IRQ_P2F_UART0_UNCONNECTED),
.IRQ_P2F_UART1(NLW_inst_IRQ_P2F_UART1_UNCONNECTED),
.IRQ_P2F_USB0(NLW_inst_IRQ_P2F_USB0_UNCONNECTED),
.IRQ_P2F_USB1(NLW_inst_IRQ_P2F_USB1_UNCONNECTED),
.MIO(MIO),
.M_AXI_GP0_ACLK(M_AXI_GP0_ACLK),
.M_AXI_GP0_ARADDR(M_AXI_GP0_ARADDR),
.M_AXI_GP0_ARBURST(M_AXI_GP0_ARBURST),
.M_AXI_GP0_ARCACHE(M_AXI_GP0_ARCACHE),
.M_AXI_GP0_ARESETN(NLW_inst_M_AXI_GP0_ARESETN_UNCONNECTED),
.M_AXI_GP0_ARID(M_AXI_GP0_ARID),
.M_AXI_GP0_ARLEN(M_AXI_GP0_ARLEN),
.M_AXI_GP0_ARLOCK(M_AXI_GP0_ARLOCK),
.M_AXI_GP0_ARPROT(M_AXI_GP0_ARPROT),
.M_AXI_GP0_ARQOS(M_AXI_GP0_ARQOS),
.M_AXI_GP0_ARREADY(M_AXI_GP0_ARREADY),
.M_AXI_GP0_ARSIZE(M_AXI_GP0_ARSIZE),
.M_AXI_GP0_ARVALID(M_AXI_GP0_ARVALID),
.M_AXI_GP0_AWADDR(M_AXI_GP0_AWADDR),
.M_AXI_GP0_AWBURST(M_AXI_GP0_AWBURST),
.M_AXI_GP0_AWCACHE(M_AXI_GP0_AWCACHE),
.M_AXI_GP0_AWID(M_AXI_GP0_AWID),
.M_AXI_GP0_AWLEN(M_AXI_GP0_AWLEN),
.M_AXI_GP0_AWLOCK(M_AXI_GP0_AWLOCK),
.M_AXI_GP0_AWPROT(M_AXI_GP0_AWPROT),
.M_AXI_GP0_AWQOS(M_AXI_GP0_AWQOS),
.M_AXI_GP0_AWREADY(M_AXI_GP0_AWREADY),
.M_AXI_GP0_AWSIZE(M_AXI_GP0_AWSIZE),
.M_AXI_GP0_AWVALID(M_AXI_GP0_AWVALID),
.M_AXI_GP0_BID(M_AXI_GP0_BID),
.M_AXI_GP0_BREADY(M_AXI_GP0_BREADY),
.M_AXI_GP0_BRESP(M_AXI_GP0_BRESP),
.M_AXI_GP0_BVALID(M_AXI_GP0_BVALID),
.M_AXI_GP0_RDATA(M_AXI_GP0_RDATA),
.M_AXI_GP0_RID(M_AXI_GP0_RID),
.M_AXI_GP0_RLAST(M_AXI_GP0_RLAST),
.M_AXI_GP0_RREADY(M_AXI_GP0_RREADY),
.M_AXI_GP0_RRESP(M_AXI_GP0_RRESP),
.M_AXI_GP0_RVALID(M_AXI_GP0_RVALID),
.M_AXI_GP0_WDATA(M_AXI_GP0_WDATA),
.M_AXI_GP0_WID(M_AXI_GP0_WID),
.M_AXI_GP0_WLAST(M_AXI_GP0_WLAST),
.M_AXI_GP0_WREADY(M_AXI_GP0_WREADY),
.M_AXI_GP0_WSTRB(M_AXI_GP0_WSTRB),
.M_AXI_GP0_WVALID(M_AXI_GP0_WVALID),
.M_AXI_GP1_ACLK(1'b0),
.M_AXI_GP1_ARADDR(NLW_inst_M_AXI_GP1_ARADDR_UNCONNECTED[31:0]),
.M_AXI_GP1_ARBURST(NLW_inst_M_AXI_GP1_ARBURST_UNCONNECTED[1:0]),
.M_AXI_GP1_ARCACHE(NLW_inst_M_AXI_GP1_ARCACHE_UNCONNECTED[3:0]),
.M_AXI_GP1_ARESETN(NLW_inst_M_AXI_GP1_ARESETN_UNCONNECTED),
.M_AXI_GP1_ARID(NLW_inst_M_AXI_GP1_ARID_UNCONNECTED[11:0]),
.M_AXI_GP1_ARLEN(NLW_inst_M_AXI_GP1_ARLEN_UNCONNECTED[3:0]),
.M_AXI_GP1_ARLOCK(NLW_inst_M_AXI_GP1_ARLOCK_UNCONNECTED[1:0]),
.M_AXI_GP1_ARPROT(NLW_inst_M_AXI_GP1_ARPROT_UNCONNECTED[2:0]),
.M_AXI_GP1_ARQOS(NLW_inst_M_AXI_GP1_ARQOS_UNCONNECTED[3:0]),
.M_AXI_GP1_ARREADY(1'b0),
.M_AXI_GP1_ARSIZE(NLW_inst_M_AXI_GP1_ARSIZE_UNCONNECTED[2:0]),
.M_AXI_GP1_ARVALID(NLW_inst_M_AXI_GP1_ARVALID_UNCONNECTED),
.M_AXI_GP1_AWADDR(NLW_inst_M_AXI_GP1_AWADDR_UNCONNECTED[31:0]),
.M_AXI_GP1_AWBURST(NLW_inst_M_AXI_GP1_AWBURST_UNCONNECTED[1:0]),
.M_AXI_GP1_AWCACHE(NLW_inst_M_AXI_GP1_AWCACHE_UNCONNECTED[3:0]),
.M_AXI_GP1_AWID(NLW_inst_M_AXI_GP1_AWID_UNCONNECTED[11:0]),
.M_AXI_GP1_AWLEN(NLW_inst_M_AXI_GP1_AWLEN_UNCONNECTED[3:0]),
.M_AXI_GP1_AWLOCK(NLW_inst_M_AXI_GP1_AWLOCK_UNCONNECTED[1:0]),
.M_AXI_GP1_AWPROT(NLW_inst_M_AXI_GP1_AWPROT_UNCONNECTED[2:0]),
.M_AXI_GP1_AWQOS(NLW_inst_M_AXI_GP1_AWQOS_UNCONNECTED[3:0]),
.M_AXI_GP1_AWREADY(1'b0),
.M_AXI_GP1_AWSIZE(NLW_inst_M_AXI_GP1_AWSIZE_UNCONNECTED[2:0]),
.M_AXI_GP1_AWVALID(NLW_inst_M_AXI_GP1_AWVALID_UNCONNECTED),
.M_AXI_GP1_BID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.M_AXI_GP1_BREADY(NLW_inst_M_AXI_GP1_BREADY_UNCONNECTED),
.M_AXI_GP1_BRESP({1'b0,1'b0}),
.M_AXI_GP1_BVALID(1'b0),
.M_AXI_GP1_RDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.M_AXI_GP1_RID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.M_AXI_GP1_RLAST(1'b0),
.M_AXI_GP1_RREADY(NLW_inst_M_AXI_GP1_RREADY_UNCONNECTED),
.M_AXI_GP1_RRESP({1'b0,1'b0}),
.M_AXI_GP1_RVALID(1'b0),
.M_AXI_GP1_WDATA(NLW_inst_M_AXI_GP1_WDATA_UNCONNECTED[31:0]),
.M_AXI_GP1_WID(NLW_inst_M_AXI_GP1_WID_UNCONNECTED[11:0]),
.M_AXI_GP1_WLAST(NLW_inst_M_AXI_GP1_WLAST_UNCONNECTED),
.M_AXI_GP1_WREADY(1'b0),
.M_AXI_GP1_WSTRB(NLW_inst_M_AXI_GP1_WSTRB_UNCONNECTED[3:0]),
.M_AXI_GP1_WVALID(NLW_inst_M_AXI_GP1_WVALID_UNCONNECTED),
.PJTAG_TCK(1'b0),
.PJTAG_TDI(1'b0),
.PJTAG_TDO(NLW_inst_PJTAG_TDO_UNCONNECTED),
.PJTAG_TMS(1'b0),
.PS_CLK(PS_CLK),
.PS_PORB(PS_PORB),
.PS_SRSTB(PS_SRSTB),
.SDIO0_BUSPOW(NLW_inst_SDIO0_BUSPOW_UNCONNECTED),
.SDIO0_BUSVOLT(NLW_inst_SDIO0_BUSVOLT_UNCONNECTED[2:0]),
.SDIO0_CDN(1'b0),
.SDIO0_CLK(NLW_inst_SDIO0_CLK_UNCONNECTED),
.SDIO0_CLK_FB(1'b0),
.SDIO0_CMD_I(1'b0),
.SDIO0_CMD_O(NLW_inst_SDIO0_CMD_O_UNCONNECTED),
.SDIO0_CMD_T(NLW_inst_SDIO0_CMD_T_UNCONNECTED),
.SDIO0_DATA_I({1'b0,1'b0,1'b0,1'b0}),
.SDIO0_DATA_O(NLW_inst_SDIO0_DATA_O_UNCONNECTED[3:0]),
.SDIO0_DATA_T(NLW_inst_SDIO0_DATA_T_UNCONNECTED[3:0]),
.SDIO0_LED(NLW_inst_SDIO0_LED_UNCONNECTED),
.SDIO0_WP(1'b0),
.SDIO1_BUSPOW(NLW_inst_SDIO1_BUSPOW_UNCONNECTED),
.SDIO1_BUSVOLT(NLW_inst_SDIO1_BUSVOLT_UNCONNECTED[2:0]),
.SDIO1_CDN(1'b0),
.SDIO1_CLK(NLW_inst_SDIO1_CLK_UNCONNECTED),
.SDIO1_CLK_FB(1'b0),
.SDIO1_CMD_I(1'b0),
.SDIO1_CMD_O(NLW_inst_SDIO1_CMD_O_UNCONNECTED),
.SDIO1_CMD_T(NLW_inst_SDIO1_CMD_T_UNCONNECTED),
.SDIO1_DATA_I({1'b0,1'b0,1'b0,1'b0}),
.SDIO1_DATA_O(NLW_inst_SDIO1_DATA_O_UNCONNECTED[3:0]),
.SDIO1_DATA_T(NLW_inst_SDIO1_DATA_T_UNCONNECTED[3:0]),
.SDIO1_LED(NLW_inst_SDIO1_LED_UNCONNECTED),
.SDIO1_WP(1'b0),
.SPI0_MISO_I(1'b0),
.SPI0_MISO_O(NLW_inst_SPI0_MISO_O_UNCONNECTED),
.SPI0_MISO_T(NLW_inst_SPI0_MISO_T_UNCONNECTED),
.SPI0_MOSI_I(1'b0),
.SPI0_MOSI_O(NLW_inst_SPI0_MOSI_O_UNCONNECTED),
.SPI0_MOSI_T(NLW_inst_SPI0_MOSI_T_UNCONNECTED),
.SPI0_SCLK_I(1'b0),
.SPI0_SCLK_O(NLW_inst_SPI0_SCLK_O_UNCONNECTED),
.SPI0_SCLK_T(NLW_inst_SPI0_SCLK_T_UNCONNECTED),
.SPI0_SS1_O(NLW_inst_SPI0_SS1_O_UNCONNECTED),
.SPI0_SS2_O(NLW_inst_SPI0_SS2_O_UNCONNECTED),
.SPI0_SS_I(1'b0),
.SPI0_SS_O(NLW_inst_SPI0_SS_O_UNCONNECTED),
.SPI0_SS_T(NLW_inst_SPI0_SS_T_UNCONNECTED),
.SPI1_MISO_I(1'b0),
.SPI1_MISO_O(NLW_inst_SPI1_MISO_O_UNCONNECTED),
.SPI1_MISO_T(NLW_inst_SPI1_MISO_T_UNCONNECTED),
.SPI1_MOSI_I(1'b0),
.SPI1_MOSI_O(NLW_inst_SPI1_MOSI_O_UNCONNECTED),
.SPI1_MOSI_T(NLW_inst_SPI1_MOSI_T_UNCONNECTED),
.SPI1_SCLK_I(1'b0),
.SPI1_SCLK_O(NLW_inst_SPI1_SCLK_O_UNCONNECTED),
.SPI1_SCLK_T(NLW_inst_SPI1_SCLK_T_UNCONNECTED),
.SPI1_SS1_O(NLW_inst_SPI1_SS1_O_UNCONNECTED),
.SPI1_SS2_O(NLW_inst_SPI1_SS2_O_UNCONNECTED),
.SPI1_SS_I(1'b0),
.SPI1_SS_O(NLW_inst_SPI1_SS_O_UNCONNECTED),
.SPI1_SS_T(NLW_inst_SPI1_SS_T_UNCONNECTED),
.SRAM_INTIN(1'b0),
.S_AXI_ACP_ACLK(1'b0),
.S_AXI_ACP_ARADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_ARBURST({1'b0,1'b0}),
.S_AXI_ACP_ARCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_ARESETN(NLW_inst_S_AXI_ACP_ARESETN_UNCONNECTED),
.S_AXI_ACP_ARID({1'b0,1'b0,1'b0}),
.S_AXI_ACP_ARLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_ARLOCK({1'b0,1'b0}),
.S_AXI_ACP_ARPROT({1'b0,1'b0,1'b0}),
.S_AXI_ACP_ARQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_ARREADY(NLW_inst_S_AXI_ACP_ARREADY_UNCONNECTED),
.S_AXI_ACP_ARSIZE({1'b0,1'b0,1'b0}),
.S_AXI_ACP_ARUSER({1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_ARVALID(1'b0),
.S_AXI_ACP_AWADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_AWBURST({1'b0,1'b0}),
.S_AXI_ACP_AWCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_AWID({1'b0,1'b0,1'b0}),
.S_AXI_ACP_AWLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_AWLOCK({1'b0,1'b0}),
.S_AXI_ACP_AWPROT({1'b0,1'b0,1'b0}),
.S_AXI_ACP_AWQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_AWREADY(NLW_inst_S_AXI_ACP_AWREADY_UNCONNECTED),
.S_AXI_ACP_AWSIZE({1'b0,1'b0,1'b0}),
.S_AXI_ACP_AWUSER({1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_AWVALID(1'b0),
.S_AXI_ACP_BID(NLW_inst_S_AXI_ACP_BID_UNCONNECTED[2:0]),
.S_AXI_ACP_BREADY(1'b0),
.S_AXI_ACP_BRESP(NLW_inst_S_AXI_ACP_BRESP_UNCONNECTED[1:0]),
.S_AXI_ACP_BVALID(NLW_inst_S_AXI_ACP_BVALID_UNCONNECTED),
.S_AXI_ACP_RDATA(NLW_inst_S_AXI_ACP_RDATA_UNCONNECTED[63:0]),
.S_AXI_ACP_RID(NLW_inst_S_AXI_ACP_RID_UNCONNECTED[2:0]),
.S_AXI_ACP_RLAST(NLW_inst_S_AXI_ACP_RLAST_UNCONNECTED),
.S_AXI_ACP_RREADY(1'b0),
.S_AXI_ACP_RRESP(NLW_inst_S_AXI_ACP_RRESP_UNCONNECTED[1:0]),
.S_AXI_ACP_RVALID(NLW_inst_S_AXI_ACP_RVALID_UNCONNECTED),
.S_AXI_ACP_WDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_WID({1'b0,1'b0,1'b0}),
.S_AXI_ACP_WLAST(1'b0),
.S_AXI_ACP_WREADY(NLW_inst_S_AXI_ACP_WREADY_UNCONNECTED),
.S_AXI_ACP_WSTRB({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_WVALID(1'b0),
.S_AXI_GP0_ACLK(1'b0),
.S_AXI_GP0_ARADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_ARBURST({1'b0,1'b0}),
.S_AXI_GP0_ARCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_ARESETN(NLW_inst_S_AXI_GP0_ARESETN_UNCONNECTED),
.S_AXI_GP0_ARID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_ARLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_ARLOCK({1'b0,1'b0}),
.S_AXI_GP0_ARPROT({1'b0,1'b0,1'b0}),
.S_AXI_GP0_ARQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_ARREADY(NLW_inst_S_AXI_GP0_ARREADY_UNCONNECTED),
.S_AXI_GP0_ARSIZE({1'b0,1'b0,1'b0}),
.S_AXI_GP0_ARVALID(1'b0),
.S_AXI_GP0_AWADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_AWBURST({1'b0,1'b0}),
.S_AXI_GP0_AWCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_AWID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_AWLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_AWLOCK({1'b0,1'b0}),
.S_AXI_GP0_AWPROT({1'b0,1'b0,1'b0}),
.S_AXI_GP0_AWQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_AWREADY(NLW_inst_S_AXI_GP0_AWREADY_UNCONNECTED),
.S_AXI_GP0_AWSIZE({1'b0,1'b0,1'b0}),
.S_AXI_GP0_AWVALID(1'b0),
.S_AXI_GP0_BID(NLW_inst_S_AXI_GP0_BID_UNCONNECTED[5:0]),
.S_AXI_GP0_BREADY(1'b0),
.S_AXI_GP0_BRESP(NLW_inst_S_AXI_GP0_BRESP_UNCONNECTED[1:0]),
.S_AXI_GP0_BVALID(NLW_inst_S_AXI_GP0_BVALID_UNCONNECTED),
.S_AXI_GP0_RDATA(NLW_inst_S_AXI_GP0_RDATA_UNCONNECTED[31:0]),
.S_AXI_GP0_RID(NLW_inst_S_AXI_GP0_RID_UNCONNECTED[5:0]),
.S_AXI_GP0_RLAST(NLW_inst_S_AXI_GP0_RLAST_UNCONNECTED),
.S_AXI_GP0_RREADY(1'b0),
.S_AXI_GP0_RRESP(NLW_inst_S_AXI_GP0_RRESP_UNCONNECTED[1:0]),
.S_AXI_GP0_RVALID(NLW_inst_S_AXI_GP0_RVALID_UNCONNECTED),
.S_AXI_GP0_WDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_WID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_WLAST(1'b0),
.S_AXI_GP0_WREADY(NLW_inst_S_AXI_GP0_WREADY_UNCONNECTED),
.S_AXI_GP0_WSTRB({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_WVALID(1'b0),
.S_AXI_GP1_ACLK(1'b0),
.S_AXI_GP1_ARADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_ARBURST({1'b0,1'b0}),
.S_AXI_GP1_ARCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_ARESETN(NLW_inst_S_AXI_GP1_ARESETN_UNCONNECTED),
.S_AXI_GP1_ARID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_ARLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_ARLOCK({1'b0,1'b0}),
.S_AXI_GP1_ARPROT({1'b0,1'b0,1'b0}),
.S_AXI_GP1_ARQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_ARREADY(NLW_inst_S_AXI_GP1_ARREADY_UNCONNECTED),
.S_AXI_GP1_ARSIZE({1'b0,1'b0,1'b0}),
.S_AXI_GP1_ARVALID(1'b0),
.S_AXI_GP1_AWADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_AWBURST({1'b0,1'b0}),
.S_AXI_GP1_AWCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_AWID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_AWLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_AWLOCK({1'b0,1'b0}),
.S_AXI_GP1_AWPROT({1'b0,1'b0,1'b0}),
.S_AXI_GP1_AWQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_AWREADY(NLW_inst_S_AXI_GP1_AWREADY_UNCONNECTED),
.S_AXI_GP1_AWSIZE({1'b0,1'b0,1'b0}),
.S_AXI_GP1_AWVALID(1'b0),
.S_AXI_GP1_BID(NLW_inst_S_AXI_GP1_BID_UNCONNECTED[5:0]),
.S_AXI_GP1_BREADY(1'b0),
.S_AXI_GP1_BRESP(NLW_inst_S_AXI_GP1_BRESP_UNCONNECTED[1:0]),
.S_AXI_GP1_BVALID(NLW_inst_S_AXI_GP1_BVALID_UNCONNECTED),
.S_AXI_GP1_RDATA(NLW_inst_S_AXI_GP1_RDATA_UNCONNECTED[31:0]),
.S_AXI_GP1_RID(NLW_inst_S_AXI_GP1_RID_UNCONNECTED[5:0]),
.S_AXI_GP1_RLAST(NLW_inst_S_AXI_GP1_RLAST_UNCONNECTED),
.S_AXI_GP1_RREADY(1'b0),
.S_AXI_GP1_RRESP(NLW_inst_S_AXI_GP1_RRESP_UNCONNECTED[1:0]),
.S_AXI_GP1_RVALID(NLW_inst_S_AXI_GP1_RVALID_UNCONNECTED),
.S_AXI_GP1_WDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_WID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_WLAST(1'b0),
.S_AXI_GP1_WREADY(NLW_inst_S_AXI_GP1_WREADY_UNCONNECTED),
.S_AXI_GP1_WSTRB({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_WVALID(1'b0),
.S_AXI_HP0_ACLK(1'b0),
.S_AXI_HP0_ARADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_ARBURST({1'b0,1'b0}),
.S_AXI_HP0_ARCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_ARESETN(NLW_inst_S_AXI_HP0_ARESETN_UNCONNECTED),
.S_AXI_HP0_ARID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_ARLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_ARLOCK({1'b0,1'b0}),
.S_AXI_HP0_ARPROT({1'b0,1'b0,1'b0}),
.S_AXI_HP0_ARQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_ARREADY(NLW_inst_S_AXI_HP0_ARREADY_UNCONNECTED),
.S_AXI_HP0_ARSIZE({1'b0,1'b0,1'b0}),
.S_AXI_HP0_ARVALID(1'b0),
.S_AXI_HP0_AWADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_AWBURST({1'b0,1'b0}),
.S_AXI_HP0_AWCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_AWID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_AWLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_AWLOCK({1'b0,1'b0}),
.S_AXI_HP0_AWPROT({1'b0,1'b0,1'b0}),
.S_AXI_HP0_AWQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_AWREADY(NLW_inst_S_AXI_HP0_AWREADY_UNCONNECTED),
.S_AXI_HP0_AWSIZE({1'b0,1'b0,1'b0}),
.S_AXI_HP0_AWVALID(1'b0),
.S_AXI_HP0_BID(NLW_inst_S_AXI_HP0_BID_UNCONNECTED[5:0]),
.S_AXI_HP0_BREADY(1'b0),
.S_AXI_HP0_BRESP(NLW_inst_S_AXI_HP0_BRESP_UNCONNECTED[1:0]),
.S_AXI_HP0_BVALID(NLW_inst_S_AXI_HP0_BVALID_UNCONNECTED),
.S_AXI_HP0_RACOUNT(NLW_inst_S_AXI_HP0_RACOUNT_UNCONNECTED[2:0]),
.S_AXI_HP0_RCOUNT(NLW_inst_S_AXI_HP0_RCOUNT_UNCONNECTED[7:0]),
.S_AXI_HP0_RDATA(NLW_inst_S_AXI_HP0_RDATA_UNCONNECTED[63:0]),
.S_AXI_HP0_RDISSUECAP1_EN(1'b0),
.S_AXI_HP0_RID(NLW_inst_S_AXI_HP0_RID_UNCONNECTED[5:0]),
.S_AXI_HP0_RLAST(NLW_inst_S_AXI_HP0_RLAST_UNCONNECTED),
.S_AXI_HP0_RREADY(1'b0),
.S_AXI_HP0_RRESP(NLW_inst_S_AXI_HP0_RRESP_UNCONNECTED[1:0]),
.S_AXI_HP0_RVALID(NLW_inst_S_AXI_HP0_RVALID_UNCONNECTED),
.S_AXI_HP0_WACOUNT(NLW_inst_S_AXI_HP0_WACOUNT_UNCONNECTED[5:0]),
.S_AXI_HP0_WCOUNT(NLW_inst_S_AXI_HP0_WCOUNT_UNCONNECTED[7:0]),
.S_AXI_HP0_WDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_WID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_WLAST(1'b0),
.S_AXI_HP0_WREADY(NLW_inst_S_AXI_HP0_WREADY_UNCONNECTED),
.S_AXI_HP0_WRISSUECAP1_EN(1'b0),
.S_AXI_HP0_WSTRB({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_WVALID(1'b0),
.S_AXI_HP1_ACLK(1'b0),
.S_AXI_HP1_ARADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_ARBURST({1'b0,1'b0}),
.S_AXI_HP1_ARCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_ARESETN(NLW_inst_S_AXI_HP1_ARESETN_UNCONNECTED),
.S_AXI_HP1_ARID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_ARLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_ARLOCK({1'b0,1'b0}),
.S_AXI_HP1_ARPROT({1'b0,1'b0,1'b0}),
.S_AXI_HP1_ARQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_ARREADY(NLW_inst_S_AXI_HP1_ARREADY_UNCONNECTED),
.S_AXI_HP1_ARSIZE({1'b0,1'b0,1'b0}),
.S_AXI_HP1_ARVALID(1'b0),
.S_AXI_HP1_AWADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_AWBURST({1'b0,1'b0}),
.S_AXI_HP1_AWCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_AWID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_AWLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_AWLOCK({1'b0,1'b0}),
.S_AXI_HP1_AWPROT({1'b0,1'b0,1'b0}),
.S_AXI_HP1_AWQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_AWREADY(NLW_inst_S_AXI_HP1_AWREADY_UNCONNECTED),
.S_AXI_HP1_AWSIZE({1'b0,1'b0,1'b0}),
.S_AXI_HP1_AWVALID(1'b0),
.S_AXI_HP1_BID(NLW_inst_S_AXI_HP1_BID_UNCONNECTED[5:0]),
.S_AXI_HP1_BREADY(1'b0),
.S_AXI_HP1_BRESP(NLW_inst_S_AXI_HP1_BRESP_UNCONNECTED[1:0]),
.S_AXI_HP1_BVALID(NLW_inst_S_AXI_HP1_BVALID_UNCONNECTED),
.S_AXI_HP1_RACOUNT(NLW_inst_S_AXI_HP1_RACOUNT_UNCONNECTED[2:0]),
.S_AXI_HP1_RCOUNT(NLW_inst_S_AXI_HP1_RCOUNT_UNCONNECTED[7:0]),
.S_AXI_HP1_RDATA(NLW_inst_S_AXI_HP1_RDATA_UNCONNECTED[63:0]),
.S_AXI_HP1_RDISSUECAP1_EN(1'b0),
.S_AXI_HP1_RID(NLW_inst_S_AXI_HP1_RID_UNCONNECTED[5:0]),
.S_AXI_HP1_RLAST(NLW_inst_S_AXI_HP1_RLAST_UNCONNECTED),
.S_AXI_HP1_RREADY(1'b0),
.S_AXI_HP1_RRESP(NLW_inst_S_AXI_HP1_RRESP_UNCONNECTED[1:0]),
.S_AXI_HP1_RVALID(NLW_inst_S_AXI_HP1_RVALID_UNCONNECTED),
.S_AXI_HP1_WACOUNT(NLW_inst_S_AXI_HP1_WACOUNT_UNCONNECTED[5:0]),
.S_AXI_HP1_WCOUNT(NLW_inst_S_AXI_HP1_WCOUNT_UNCONNECTED[7:0]),
.S_AXI_HP1_WDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_WID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_WLAST(1'b0),
.S_AXI_HP1_WREADY(NLW_inst_S_AXI_HP1_WREADY_UNCONNECTED),
.S_AXI_HP1_WRISSUECAP1_EN(1'b0),
.S_AXI_HP1_WSTRB({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_WVALID(1'b0),
.S_AXI_HP2_ACLK(1'b0),
.S_AXI_HP2_ARADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_ARBURST({1'b0,1'b0}),
.S_AXI_HP2_ARCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_ARESETN(NLW_inst_S_AXI_HP2_ARESETN_UNCONNECTED),
.S_AXI_HP2_ARID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_ARLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_ARLOCK({1'b0,1'b0}),
.S_AXI_HP2_ARPROT({1'b0,1'b0,1'b0}),
.S_AXI_HP2_ARQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_ARREADY(NLW_inst_S_AXI_HP2_ARREADY_UNCONNECTED),
.S_AXI_HP2_ARSIZE({1'b0,1'b0,1'b0}),
.S_AXI_HP2_ARVALID(1'b0),
.S_AXI_HP2_AWADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_AWBURST({1'b0,1'b0}),
.S_AXI_HP2_AWCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_AWID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_AWLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_AWLOCK({1'b0,1'b0}),
.S_AXI_HP2_AWPROT({1'b0,1'b0,1'b0}),
.S_AXI_HP2_AWQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_AWREADY(NLW_inst_S_AXI_HP2_AWREADY_UNCONNECTED),
.S_AXI_HP2_AWSIZE({1'b0,1'b0,1'b0}),
.S_AXI_HP2_AWVALID(1'b0),
.S_AXI_HP2_BID(NLW_inst_S_AXI_HP2_BID_UNCONNECTED[5:0]),
.S_AXI_HP2_BREADY(1'b0),
.S_AXI_HP2_BRESP(NLW_inst_S_AXI_HP2_BRESP_UNCONNECTED[1:0]),
.S_AXI_HP2_BVALID(NLW_inst_S_AXI_HP2_BVALID_UNCONNECTED),
.S_AXI_HP2_RACOUNT(NLW_inst_S_AXI_HP2_RACOUNT_UNCONNECTED[2:0]),
.S_AXI_HP2_RCOUNT(NLW_inst_S_AXI_HP2_RCOUNT_UNCONNECTED[7:0]),
.S_AXI_HP2_RDATA(NLW_inst_S_AXI_HP2_RDATA_UNCONNECTED[63:0]),
.S_AXI_HP2_RDISSUECAP1_EN(1'b0),
.S_AXI_HP2_RID(NLW_inst_S_AXI_HP2_RID_UNCONNECTED[5:0]),
.S_AXI_HP2_RLAST(NLW_inst_S_AXI_HP2_RLAST_UNCONNECTED),
.S_AXI_HP2_RREADY(1'b0),
.S_AXI_HP2_RRESP(NLW_inst_S_AXI_HP2_RRESP_UNCONNECTED[1:0]),
.S_AXI_HP2_RVALID(NLW_inst_S_AXI_HP2_RVALID_UNCONNECTED),
.S_AXI_HP2_WACOUNT(NLW_inst_S_AXI_HP2_WACOUNT_UNCONNECTED[5:0]),
.S_AXI_HP2_WCOUNT(NLW_inst_S_AXI_HP2_WCOUNT_UNCONNECTED[7:0]),
.S_AXI_HP2_WDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_WID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_WLAST(1'b0),
.S_AXI_HP2_WREADY(NLW_inst_S_AXI_HP2_WREADY_UNCONNECTED),
.S_AXI_HP2_WRISSUECAP1_EN(1'b0),
.S_AXI_HP2_WSTRB({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_WVALID(1'b0),
.S_AXI_HP3_ACLK(1'b0),
.S_AXI_HP3_ARADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_ARBURST({1'b0,1'b0}),
.S_AXI_HP3_ARCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_ARESETN(NLW_inst_S_AXI_HP3_ARESETN_UNCONNECTED),
.S_AXI_HP3_ARID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_ARLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_ARLOCK({1'b0,1'b0}),
.S_AXI_HP3_ARPROT({1'b0,1'b0,1'b0}),
.S_AXI_HP3_ARQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_ARREADY(NLW_inst_S_AXI_HP3_ARREADY_UNCONNECTED),
.S_AXI_HP3_ARSIZE({1'b0,1'b0,1'b0}),
.S_AXI_HP3_ARVALID(1'b0),
.S_AXI_HP3_AWADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_AWBURST({1'b0,1'b0}),
.S_AXI_HP3_AWCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_AWID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_AWLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_AWLOCK({1'b0,1'b0}),
.S_AXI_HP3_AWPROT({1'b0,1'b0,1'b0}),
.S_AXI_HP3_AWQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_AWREADY(NLW_inst_S_AXI_HP3_AWREADY_UNCONNECTED),
.S_AXI_HP3_AWSIZE({1'b0,1'b0,1'b0}),
.S_AXI_HP3_AWVALID(1'b0),
.S_AXI_HP3_BID(NLW_inst_S_AXI_HP3_BID_UNCONNECTED[5:0]),
.S_AXI_HP3_BREADY(1'b0),
.S_AXI_HP3_BRESP(NLW_inst_S_AXI_HP3_BRESP_UNCONNECTED[1:0]),
.S_AXI_HP3_BVALID(NLW_inst_S_AXI_HP3_BVALID_UNCONNECTED),
.S_AXI_HP3_RACOUNT(NLW_inst_S_AXI_HP3_RACOUNT_UNCONNECTED[2:0]),
.S_AXI_HP3_RCOUNT(NLW_inst_S_AXI_HP3_RCOUNT_UNCONNECTED[7:0]),
.S_AXI_HP3_RDATA(NLW_inst_S_AXI_HP3_RDATA_UNCONNECTED[63:0]),
.S_AXI_HP3_RDISSUECAP1_EN(1'b0),
.S_AXI_HP3_RID(NLW_inst_S_AXI_HP3_RID_UNCONNECTED[5:0]),
.S_AXI_HP3_RLAST(NLW_inst_S_AXI_HP3_RLAST_UNCONNECTED),
.S_AXI_HP3_RREADY(1'b0),
.S_AXI_HP3_RRESP(NLW_inst_S_AXI_HP3_RRESP_UNCONNECTED[1:0]),
.S_AXI_HP3_RVALID(NLW_inst_S_AXI_HP3_RVALID_UNCONNECTED),
.S_AXI_HP3_WACOUNT(NLW_inst_S_AXI_HP3_WACOUNT_UNCONNECTED[5:0]),
.S_AXI_HP3_WCOUNT(NLW_inst_S_AXI_HP3_WCOUNT_UNCONNECTED[7:0]),
.S_AXI_HP3_WDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_WID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_WLAST(1'b0),
.S_AXI_HP3_WREADY(NLW_inst_S_AXI_HP3_WREADY_UNCONNECTED),
.S_AXI_HP3_WRISSUECAP1_EN(1'b0),
.S_AXI_HP3_WSTRB({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_WVALID(1'b0),
.TRACE_CLK(1'b0),
.TRACE_CLK_OUT(NLW_inst_TRACE_CLK_OUT_UNCONNECTED),
.TRACE_CTL(NLW_inst_TRACE_CTL_UNCONNECTED),
.TRACE_DATA(NLW_inst_TRACE_DATA_UNCONNECTED[1:0]),
.TTC0_CLK0_IN(1'b0),
.TTC0_CLK1_IN(1'b0),
.TTC0_CLK2_IN(1'b0),
.TTC0_WAVE0_OUT(TTC0_WAVE0_OUT),
.TTC0_WAVE1_OUT(TTC0_WAVE1_OUT),
.TTC0_WAVE2_OUT(TTC0_WAVE2_OUT),
.TTC1_CLK0_IN(1'b0),
.TTC1_CLK1_IN(1'b0),
.TTC1_CLK2_IN(1'b0),
.TTC1_WAVE0_OUT(NLW_inst_TTC1_WAVE0_OUT_UNCONNECTED),
.TTC1_WAVE1_OUT(NLW_inst_TTC1_WAVE1_OUT_UNCONNECTED),
.TTC1_WAVE2_OUT(NLW_inst_TTC1_WAVE2_OUT_UNCONNECTED),
.UART0_CTSN(1'b0),
.UART0_DCDN(1'b0),
.UART0_DSRN(1'b0),
.UART0_DTRN(NLW_inst_UART0_DTRN_UNCONNECTED),
.UART0_RIN(1'b0),
.UART0_RTSN(NLW_inst_UART0_RTSN_UNCONNECTED),
.UART0_RX(1'b1),
.UART0_TX(NLW_inst_UART0_TX_UNCONNECTED),
.UART1_CTSN(1'b0),
.UART1_DCDN(1'b0),
.UART1_DSRN(1'b0),
.UART1_DTRN(NLW_inst_UART1_DTRN_UNCONNECTED),
.UART1_RIN(1'b0),
.UART1_RTSN(NLW_inst_UART1_RTSN_UNCONNECTED),
.UART1_RX(1'b1),
.UART1_TX(NLW_inst_UART1_TX_UNCONNECTED),
.USB0_PORT_INDCTL(USB0_PORT_INDCTL),
.USB0_VBUS_PWRFAULT(USB0_VBUS_PWRFAULT),
.USB0_VBUS_PWRSELECT(USB0_VBUS_PWRSELECT),
.USB1_PORT_INDCTL(NLW_inst_USB1_PORT_INDCTL_UNCONNECTED[1:0]),
.USB1_VBUS_PWRFAULT(1'b0),
.USB1_VBUS_PWRSELECT(NLW_inst_USB1_VBUS_PWRSELECT_UNCONNECTED),
.WDT_CLK_IN(1'b0),
.WDT_RST_OUT(NLW_inst_WDT_RST_OUT_UNCONNECTED));
endmodule |
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (strong1, weak0) GSR = GSR_int;
assign (strong1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule |
module Tx8b10b_tb ();
reg clk; // System clock
reg rst; // Reset; synchronous and active high
reg en; // Enable bit
reg [7:0] dataIn; // Data to transmit
reg writeStrobe; // Write data to transmit FIFO
wire dataPresent; // FIFO has data still in it
wire halfFull; // FIFO halfway full
wire full; // FIFO is completely full. Don't write to it.
wire tx; // Transmit bit
integer i;
integer dcOffset;
always #1 clk = ~clk;
initial begin
dcOffset = 1'b0;
clk = 1'b0;
rst = 1'b1;
en = 1'b1;
dataIn = 'd0;
writeStrobe = 1'b0;
@(posedge clk)
@(posedge clk)
rst = 1'b0;
for (i=0; i<50000; i=i+1) begin
wait(~full);
@(posedge clk) dataIn <= $random(); writeStrobe = 1'b1;
@(posedge clk) writeStrobe = 1'b0;
@(posedge clk);
end
$stop(2);
end
always @(posedge clk) begin
dcOffset <= dcOffset + $signed({tx, 1'b1});
end
Tx8b10b #(
.FILL_WORD_RD0(10'b0011111010), // Send when no data present & RD=-1
.FILL_WORD_RD1(10'b1100000101), // Send when no data present & RD=1
.FILL_WORD_FLIP(1'b1), // Flip status of Running Disparity when using fill word
.LOG2_DEPTH(4) // log2(depth of FIFO buffer). Must be an integer.
)
uut (
.clk(clk), // System clock
.rst(rst), // Reset, synchronous and active high
.en(en), // Enable strobe for transmitting
.dataIn(dataIn), // [7:0] Data to transmit
.writeStrobe(writeStrobe), // Write data to transmit FIFO
.dataPresent(dataPresent), // FIFO has data still in it
.halfFull(halfFull), // FIFO halfway full
.full(full), // FIFO is completely full. Don't write to it.
.tx(tx) // Transmit bit
);
endmodule |
module SGMII_TX(
clk,
reset,
ff_tx_clk,
ff_tx_data,//
ff_tx_sop,
ff_tx_mod,
ff_tx_eop,
ff_tx_err,
ff_tx_wren,
ff_tx_crc_fwd,//CRC ADD
tx_ff_uflow,
ff_tx_rdy,//core ready
ff_tx_septy,
ff_tx_a_full,
ff_tx_a_empty,
pkt_send_add,
data_in_wrreq,
data_in,
data_in_almostfull,
data_in_valid_wrreq,
data_in_valid );
input clk;
input reset;
input ff_tx_clk;
output [31:0] ff_tx_data;
output [1:0] ff_tx_mod;
output ff_tx_sop;
output ff_tx_eop;
output ff_tx_err;
output ff_tx_wren;
output ff_tx_crc_fwd;
input tx_ff_uflow;
input ff_tx_rdy;
input ff_tx_septy;
input ff_tx_a_full;
input ff_tx_a_empty;
output pkt_send_add;
input data_in_wrreq;
input [133:0] data_in;
output data_in_almostfull;
input data_in_valid_wrreq;
input data_in_valid;
reg [31:0] ff_tx_data;
reg [1:0] ff_tx_mod;
reg ff_tx_sop;
reg ff_tx_eop;
reg ff_tx_err;
reg ff_tx_wren;
reg ff_tx_crc_fwd;
reg pkt_send_add;
reg [133:0] data_in_q_r;
reg [2:0] current_state;
parameter idle_s = 3'b000,
transmit_byte0_s = 3'b001,
transmit_byte1_s = 3'b010,
transmit_byte2_s = 3'b011,
transmit_byte3_s = 3'b100,
discard_s = 3'b101;
always@(posedge ff_tx_clk or negedge reset)
if(!reset) begin
ff_tx_data <= 32'b0;
ff_tx_mod <= 2'b0;
ff_tx_sop <= 1'b0;
ff_tx_eop <= 1'b0;
ff_tx_err <= 1'b0;
ff_tx_wren <= 1'b0;
ff_tx_crc_fwd <= 1'b1;
data_in_rdreq <= 1'b0;
data_in_valid_rdreq <= 1'b0;
pkt_send_add <= 1'b0;
data_in_q_r <= 134'b0;
current_state <= idle_s;
end
else begin
case(current_state)
idle_s: begin
ff_tx_crc_fwd <= 1'b1;
ff_tx_wren <= 1'b0;
ff_tx_sop <= 1'b0;
ff_tx_eop <= 1'b0;
ff_tx_mod <= 2'b0;
if(ff_tx_rdy == 1'b1) begin
if(!data_in_valid_empty) begin//0:has pkt 1:no pkt
data_in_rdreq <= 1'b1;
data_in_valid_rdreq <= 1'b1;
if(data_in_valid_q == 1'b1) begin//pkt valid
pkt_send_add <= 1'b1;
data_in_q_r <= data_in_q;
ff_tx_sop <= 1'b1;
ff_tx_data <= data_in_q[127:96];
ff_tx_wren <= 1'b1;
current_state <= transmit_byte1_s;
end
else begin//pkt error
pkt_send_add <= 1'b0;
current_state <= discard_s;
end
end
else begin
current_state <= idle_s;
end
end
else begin
current_state <= idle_s;
end
end
transmit_byte0_s: begin
data_in_rdreq <= 1'b0;
if(ff_tx_rdy == 1'b0) begin//MAC core don't ready need wait
current_state <= transmit_byte0_s;
ff_tx_wren <= 1'b0;
end
else begin
ff_tx_data <= data_in_q_r[127:96];
ff_tx_wren <= 1'b1;
if(data_in_q_r[133:132] == 2'b10) begin//pkt tail
if(data_in_q_r[131:130] == 2'b11)begin
ff_tx_eop <= 1'b1;
ff_tx_mod <= data_in_q_r[129:128];
ff_tx_crc_fwd <= 1'b0;
current_state <= idle_s;
end
else
current_state <= transmit_byte1_s;
end
else begin
current_state <= transmit_byte1_s;
end
end
end
transmit_byte1_s: begin
ff_tx_sop <= 1'b0;
data_in_rdreq <= 1'b0;
data_in_valid_rdreq <= 1'b0;
pkt_send_add <= 1'b0;
if(ff_tx_rdy == 1'b0) begin
current_state <= transmit_byte1_s;
ff_tx_wren <= 1'b0;
end
else begin
ff_tx_data <= data_in_q_r[95:64];
ff_tx_wren <= 1'b1;
if(data_in_q_r[133:132] == 2'b10) begin
if(data_in_q_r[131:130] == 2'b10)begin
ff_tx_eop <= 1'b1;
ff_tx_crc_fwd <= 1'b0;
ff_tx_mod <= data_in_q_r[129:128];
current_state <= idle_s;
end
else
current_state <= transmit_byte2_s;
end
else begin
current_state <= transmit_byte2_s;
end
end
end
transmit_byte2_s: begin
if(ff_tx_rdy == 1'b0) begin
current_state <= transmit_byte2_s;
ff_tx_wren <= 1'b0;
end
else begin
ff_tx_data <= data_in_q_r[63:32];
ff_tx_wren <= 1'b1;
if(data_in_q_r[133:132] == 2'b10) begin
if(data_in_q_r[131:130] == 2'b01)begin
ff_tx_eop <= 1'b1;
ff_tx_crc_fwd <= 1'b0;
ff_tx_mod <= data_in_q_r[129:128];
current_state <= idle_s;
end
else
current_state <= transmit_byte3_s;
end
else begin
current_state <= transmit_byte3_s;
end
end
end
transmit_byte3_s: begin
if(ff_tx_rdy == 1'b0) begin
current_state <= transmit_byte3_s;
ff_tx_wren <= 1'b0;
end
else begin
ff_tx_data <= data_in_q_r[31:0];
ff_tx_wren <= 1'b1;
if(data_in_q_r[133:132] == 2'b10) begin
ff_tx_eop <= 1'b1;
ff_tx_crc_fwd <= 1'b0;
ff_tx_mod <= data_in_q_r[129:128];
current_state <= idle_s;
end
else begin
data_in_rdreq <= 1'b1;
data_in_q_r <= data_in_q;
current_state <= transmit_byte0_s;
end
end
end
discard_s: begin
data_in_valid_rdreq <= 1'b0;
if(data_in_q[133:132]==2'b10) begin
data_in_rdreq <= 1'b0;
current_state <= idle_s;
end
else begin
data_in_rdreq <= 1'b1;
current_state <= discard_s;
end
end
endcase
end
reg data_in_rdreq;
wire [7:0] data_in_usedw;
assign data_in_almostfull = data_in_usedw[7];
wire [133:0] data_in_q;
asyn_256_134 asyn_256_134(
.aclr(!reset),
.wrclk(clk),
.wrreq(data_in_wrreq),
.data(data_in),
.rdclk(ff_tx_clk),
.rdreq(data_in_rdreq),
.q(data_in_q),
.wrusedw(data_in_usedw)
);
reg data_in_valid_rdreq;
wire data_in_valid_q;
wire data_in_valid_empty;
asyn_64_1 asyn_64_1(
.aclr(!reset),
.wrclk(clk),
.wrreq(data_in_valid_wrreq),
.data(data_in_valid),
.rdclk(ff_tx_clk),
.rdreq(data_in_valid_rdreq),
.q(data_in_valid_q),
.rdempty(data_in_valid_empty)
);
endmodule |
module sky130_fd_sc_hd__einvp (
Z ,
A ,
TE
);
output Z ;
input A ;
input TE;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule |
module t (
input i_clk_wr,
input i_clk_rd
);
wire wr$wen;
wire [7:0] wr$addr;
wire [7:0] wr$wdata;
wire [7:0] wr$rdata;
wire rd$wen;
wire [7:0] rd$addr;
wire [7:0] rd$wdata;
wire [7:0] rd$rdata;
wire clk_wr;
wire clk_rd;
`ifdef MULTI_CLK
assign clk_wr = i_clk_wr;
assign clk_rd = i_clk_rd;
`else
assign clk_wr = i_clk_wr;
assign clk_rd = i_clk_wr;
`endif
FooWr u_wr (
.i_clk ( clk_wr ),
.o_wen ( wr$wen ),
.o_addr ( wr$addr ),
.o_wdata ( wr$wdata ),
.i_rdata ( wr$rdata )
);
FooRd u_rd (
.i_clk ( clk_rd ),
.o_wen ( rd$wen ),
.o_addr ( rd$addr ),
.o_wdata ( rd$wdata ),
.i_rdata ( rd$rdata )
);
FooMem u_mem (
.iv_clk ( {clk_wr, clk_rd } ),
.iv_wen ( {wr$wen, rd$wen } ),
.iv_addr ( {wr$addr, rd$addr } ),
.iv_wdata ( {wr$wdata,rd$wdata} ),
.ov_rdata ( {wr$rdata,rd$rdata} )
);
endmodule |
module FooWr(
input i_clk,
output o_wen,
output [7:0] o_addr,
output [7:0] o_wdata,
input [7:0] i_rdata
);
reg [7:0] cnt = 0;
// Count [0,200]
always @( posedge i_clk )
if ( cnt < 8'd50 )
cnt <= cnt + 8'd1;
// Write addr in (10,30) if even
assign o_wen = ( cnt > 8'd10 ) && ( cnt < 8'd30 ) && ( cnt[0] == 1'b0 );
assign o_addr = cnt;
assign o_wdata = cnt;
endmodule |
module FooRd(
input i_clk,
output o_wen,
output [7:0] o_addr,
output [7:0] o_wdata,
input [7:0] i_rdata
);
reg [7:0] cnt = 0;
reg [7:0] addr_r;
reg en_r;
// Count [0,200]
always @( posedge i_clk )
if ( cnt < 8'd200 )
cnt <= cnt + 8'd1;
// Read data
assign o_wen = 0;
assign o_addr = cnt - 8'd100;
// Track issued read
always @( posedge i_clk )
begin
addr_r <= o_addr;
en_r <= ( cnt > 8'd110 ) && ( cnt < 8'd130 ) && ( cnt[0] == 1'b0 );
end
// Display to console 100 cycles after writer
always @( negedge i_clk )
if ( en_r ) begin
`ifdef TEST_VERBOSE
$display( "MEM[%x] == %x", addr_r, i_rdata );
`endif
if (addr_r != i_rdata) $stop;
end
endmodule |
module FooMem(
input [2 -1:0] iv_clk,
input [2 -1:0] iv_wen,
input [2*8-1:0] iv_addr,
input [2*8-1:0] iv_wdata,
output [2*8-1:0] ov_rdata
);
FooMemImpl u_impl (
.a_clk ( iv_clk [0*1+:1] ),
.a_wen ( iv_wen [0*1+:1] ),
.a_addr ( iv_addr [0*8+:8] ),
.a_wdata ( iv_wdata[0*8+:8] ),
.a_rdata ( ov_rdata[0*8+:8] ),
.b_clk ( iv_clk [1*1+:1] ),
.b_wen ( iv_wen [1*1+:1] ),
.b_addr ( iv_addr [1*8+:8] ),
.b_wdata ( iv_wdata[1*8+:8] ),
.b_rdata ( ov_rdata[1*8+:8] )
);
endmodule |
module FooMemImpl(
input a_clk,
input a_wen,
input [7:0] a_addr,
input [7:0] a_wdata,
output [7:0] a_rdata,
input b_clk,
input b_wen,
input [7:0] b_addr,
input [7:0] b_wdata,
output [7:0] b_rdata
);
/* verilator lint_off MULTIDRIVEN */
reg [7:0] mem[0:255];
/* verilator lint_on MULTIDRIVEN */
always @( posedge a_clk )
if ( a_wen )
mem[a_addr] <= a_wdata;
always @( posedge b_clk )
if ( b_wen )
mem[b_addr] <= b_wdata;
always @( posedge a_clk )
a_rdata <= mem[a_addr];
always @( posedge b_clk )
b_rdata <= mem[b_addr];
endmodule |
module MAC #(
parameter N = 5,
parameter PIPE = 3,
parameter WIDTH = 16,
parameter M_WIDTH = 2*WIDTH+N-1
)(
input clk,
input sof,
input [WIDTH-1:0] A,
input [WIDTH-1:0] B,
output reg [M_WIDTH-1:0] C,
output reg valid
);
reg state;
reg [7:0] n,p;
wire [2*WIDTH-1:0] O;
parameter
IDLE = 1'b0,
MAC = 1'b1;
initial begin
n <= N;
p <= PIPE;
C <= 0;
valid <= 1'b0;
state <= IDLE;
end
always@(posedge clk) begin
case(state)
IDLE: begin
p <= PIPE;
n <= N;
C <= 0;
valid <= 1'b0;
if(sof) begin
if(p > 1)
p <= p-1;
else begin// if ((p == 1) || (p ==0))
p <= 0;
state <= MAC;
end
end
end
MAC: begin
C <= C + O;
n <= n-1;
valid <= 1'b0;
if(n == 1) begin
valid <= 1'b1;
if(!sof)
state <= IDLE;
else begin
n <= N;
//C <= 0;
end
end
if(n == N)
C <= O;
end
endcase
end
MULT mult_16W (
.clk (clk), // input clk
.a (A), // input [15 : 0] a
.b (B), // input [15 : 0] b
.p (O) // output [31 : 0] p
);
endmodule |
module pwm_demo(
input CLK_100MHz,
input [2:0] ADDRESS,
input [7:0] DATA,
input SW1,
output [7:0] PWM,
output reg [7:0] LED
);
wire [2:0] address;
wire [7:0] data;
wire latch;
assign address = ADDRESS;
assign data = DATA;
assign latch = ~SW1;
reg [7:0] period [0:256-1];
pwm_generator pwm0(.clk(CLK_100MHz), .period(period[0]), .pin(PWM[0]));
pwm_generator pwm1(.clk(CLK_100MHz), .period(period[1]), .pin(PWM[1]));
pwm_generator pwm2(.clk(CLK_100MHz), .period(period[2]), .pin(PWM[2]));
pwm_generator pwm3(.clk(CLK_100MHz), .period(period[3]), .pin(PWM[3]));
pwm_generator pwm4(.clk(CLK_100MHz), .period(period[4]), .pin(PWM[4]));
pwm_generator pwm5(.clk(CLK_100MHz), .period(period[5]), .pin(PWM[5]));
pwm_generator pwm6(.clk(CLK_100MHz), .period(period[6]), .pin(PWM[6]));
pwm_generator pwm7(.clk(CLK_100MHz), .period(period[7]), .pin(PWM[7]));
always @(posedge CLK_100MHz) begin
if (latch) begin
LED <= address;
period[address] <= data;
end
end
endmodule |
module pwm_generator(
input clk,
input [7:0] period,
output pin
);
reg [7:0] counter;
reg pin_out;
assign pin = pin_out;
always @(posedge clk) begin
if (counter < period)
counter <= counter + 1;
else begin
counter <= 0;
case (pin)
1'b0: pin_out <= 1;
1'b1: pin_out <= 0;
default: pin_out <= 0;
endcase
end
end
endmodule |
module sky130_fd_sc_hdll__inputiso1p (
X ,
A ,
SLEEP,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input SLEEP;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire or0_out_X;
// Name Output Other arguments
or or0 (or0_out_X, A, SLEEP );
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp0 (X , or0_out_X, VPWR, VGND);
endmodule |
module tx_multiplexer_32
#(
parameter C_PCI_DATA_WIDTH = 9'd32,
parameter C_NUM_CHNL = 4'd12,
parameter C_TAG_WIDTH = 5, // Number of outstanding requests
parameter C_VENDOR = "XILINX"
)
(
input CLK,
input RST_IN,
input [C_NUM_CHNL-1:0] WR_REQ, // Write request
input [(C_NUM_CHNL*`SIG_ADDR_W)-1:0] WR_ADDR, // Write address
input [(C_NUM_CHNL*`SIG_LEN_W)-1:0] WR_LEN, // Write data length
input [(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0] WR_DATA, // Write data
output [C_NUM_CHNL-1:0] WR_DATA_REN, // Write data read enable
output [C_NUM_CHNL-1:0] WR_ACK, // Write request has been accepted
input [C_NUM_CHNL-1:0] RD_REQ, // Read request
input [(C_NUM_CHNL*2)-1:0] RD_SG_CHNL, // Read request channel for scatter gather lists
input [(C_NUM_CHNL*`SIG_ADDR_W)-1:0] RD_ADDR, // Read request address
input [(C_NUM_CHNL*`SIG_LEN_W)-1:0] RD_LEN, // Read request length
output [C_NUM_CHNL-1:0] RD_ACK, // Read request has been accepted
output [5:0] INT_TAG, // Internal tag to exchange with external
output INT_TAG_VALID, // High to signal tag exchange
input [C_TAG_WIDTH-1:0] EXT_TAG, // External tag to provide in exchange for internal tag
input EXT_TAG_VALID, // High to signal external tag is valid
output TX_ENG_RD_REQ_SENT, // Read completion request issued
input RXBUF_SPACE_AVAIL,
// Interface: TXR Engine
output TXR_DATA_VALID,
output [C_PCI_DATA_WIDTH-1:0] TXR_DATA,
output TXR_DATA_START_FLAG,
output [clog2s(C_PCI_DATA_WIDTH/32)-1:0] TXR_DATA_START_OFFSET,
output TXR_DATA_END_FLAG,
output [clog2s(C_PCI_DATA_WIDTH/32)-1:0] TXR_DATA_END_OFFSET,
input TXR_DATA_READY,
output TXR_META_VALID,
output [`SIG_FBE_W-1:0] TXR_META_FDWBE,
output [`SIG_LBE_W-1:0] TXR_META_LDWBE,
output [`SIG_ADDR_W-1:0] TXR_META_ADDR,
output [`SIG_LEN_W-1:0] TXR_META_LENGTH,
output [`SIG_TAG_W-1:0] TXR_META_TAG,
output [`SIG_TC_W-1:0] TXR_META_TC,
output [`SIG_ATTR_W-1:0] TXR_META_ATTR,
output [`SIG_TYPE_W-1:0] TXR_META_TYPE,
output TXR_META_EP,
input TXR_META_READY
);
`include "functions.vh"
// Local parameters
localparam C_DATA_DELAY = 6'd1; // Delays read/write params to accommodate tx_port_buffer delay and tx_engine_formatter delay.
(* syn_encoding = "user" *)
(* fsm_encoding = "user" *)
reg [5:0] rMainState=`S_TXENGUPR32_MAIN_IDLE, _rMainState=`S_TXENGUPR32_MAIN_IDLE;
reg [3:0] rCountChnl=0, _rCountChnl=0;
reg [C_TAG_WIDTH-1:0] rCountTag=0, _rCountTag=0;
reg [9:0] rCount=0, _rCount=0;
reg rCountDone=0, _rCountDone=0;
reg rCountStart=0, _rCountStart=0;
reg rCount32=0, _rCount32=0;
reg [C_NUM_CHNL-1:0] rWrDataRen=0, _rWrDataRen=0;
reg rTxEngRdReqAck, _rTxEngRdReqAck;
wire wRdReq;
wire [3:0] wRdReqChnl;
wire wWrReq;
wire [3:0] wWrReqChnl;
wire wRdAck;
wire [3:0] wCountChnl;
wire [11:0] wCountChnlShiftDW = (wCountChnl*C_PCI_DATA_WIDTH); // Mult can exceed 9 bits, so make this a wire
wire [63:0] wRdAddr;
wire [9:0] wRdLen;
wire [1:0] wRdSgChnl;
wire [63:0] wWrAddr;
wire [9:0] wWrLen;
wire [C_PCI_DATA_WIDTH-1:0] wWrData;
reg [3:0] rRdChnl=0, _rRdChnl=0;
reg [61:0] rRdAddr=62'd0, _rRdAddr=62'd0;
reg [9:0] rRdLen=0, _rRdLen=0;
reg [1:0] rRdSgChnl=0, _rRdSgChnl=0;
reg [3:0] rWrChnl=0, _rWrChnl=0;
reg [61:0] rWrAddr=62'd0, _rWrAddr=62'd0;
reg [9:0] rWrLen=0, _rWrLen=0;
reg [C_PCI_DATA_WIDTH-1:0] rWrData={C_PCI_DATA_WIDTH{1'd0}}, _rWrData={C_PCI_DATA_WIDTH{1'd0}};
(* syn_encoding = "user" *)
(* fsm_encoding = "user" *)
reg [3:0] rCapState=`S_TXENGUPR32_CAP_RD_WR, _rCapState=`S_TXENGUPR32_CAP_RD_WR;
reg [C_NUM_CHNL-1:0] rRdAck=0, _rRdAck=0;
reg [C_NUM_CHNL-1:0] rWrAck=0, _rWrAck=0;
reg rIsWr=0, _rIsWr=0;
reg [5:0] rCapChnl=0, _rCapChnl=0;
reg [61:0] rCapAddr=62'd0, _rCapAddr=62'd0;
reg rCapAddr64=0, _rCapAddr64=0;
reg [9:0] rCapLen=0, _rCapLen=0;
reg rCapIsWr=0, _rCapIsWr=0;
reg rExtTagReq=0, _rExtTagReq=0;
reg [C_TAG_WIDTH-1:0] rExtTag=0, _rExtTag=0;
reg [C_DATA_DELAY-1:0] rWnR=0, _rWnR=0;
reg [(C_DATA_DELAY*4)-1:0] rChnl=0, _rChnl=0;
reg [(C_DATA_DELAY*8)-1:0] rTag=0, _rTag=0;
reg [(C_DATA_DELAY*62)-1:0] rAddr=0, _rAddr=0;
reg [C_DATA_DELAY-1:0] rAddr64=0, _rAddr64=0;
reg [(C_DATA_DELAY*10)-1:0] rLen=0, _rLen=0;
reg [C_DATA_DELAY-1:0] rLenEQ1=0, _rLenEQ1=0;
reg [C_DATA_DELAY-1:0] rValid=0, _rValid=0;
reg [C_DATA_DELAY-1:0] rDone=0, _rDone=0;
reg [C_DATA_DELAY-1:0] rStart=0, _rStart=0;
assign wRdAddr = RD_ADDR[wRdReqChnl * `SIG_ADDR_W +: `SIG_ADDR_W];
assign wRdLen = RD_LEN[wRdReqChnl * `SIG_LEN_W +: `SIG_LEN_W];
assign wRdSgChnl = RD_SG_CHNL[wRdReqChnl * 2 +: 2];
assign wWrAddr = WR_ADDR[wWrReqChnl * `SIG_ADDR_W +: `SIG_ADDR_W];
assign wWrLen = WR_LEN[wWrReqChnl * `SIG_LEN_W +: `SIG_LEN_W];
assign wWrData = WR_DATA[wCountChnl * C_PCI_DATA_WIDTH +: C_PCI_DATA_WIDTH];
assign WR_DATA_REN = rWrDataRen;
assign WR_ACK = rWrAck;
assign RD_ACK = rRdAck;
assign INT_TAG = {rRdSgChnl, rRdChnl};
assign INT_TAG_VALID = rExtTagReq;
assign TX_ENG_RD_REQ_SENT = rTxEngRdReqAck;
assign wRdAck = (wRdReq & EXT_TAG_VALID & RXBUF_SPACE_AVAIL);
// Search for the next request so that we can move onto it immediately after
// the current channel has released its request.
tx_engine_selector #(.C_NUM_CHNL(C_NUM_CHNL)) selRd (.RST(RST_IN), .CLK(CLK), .REQ_ALL(RD_REQ), .REQ(wRdReq), .CHNL(wRdReqChnl));
tx_engine_selector #(.C_NUM_CHNL(C_NUM_CHNL)) selWr (.RST(RST_IN), .CLK(CLK), .REQ_ALL(WR_REQ), .REQ(wWrReq), .CHNL(wWrReqChnl));
// Buffer shift-selected channel request signals and FIFO data.
always @ (posedge CLK) begin
rRdChnl <= #1 _rRdChnl;
rRdAddr <= #1 _rRdAddr;
rRdLen <= #1 _rRdLen;
rRdSgChnl <= #1 _rRdSgChnl;
rWrChnl <= #1 _rWrChnl;
rWrAddr <= #1 _rWrAddr;
rWrLen <= #1 _rWrLen;
rWrData <= #1 _rWrData;
end
always @ (*) begin
_rRdChnl = wRdReqChnl;
_rRdAddr = wRdAddr[63:2];
_rRdLen = wRdLen;
_rRdSgChnl = wRdSgChnl;
_rWrChnl = wWrReqChnl;
_rWrAddr = wWrAddr[63:2];
_rWrLen = wWrLen;
_rWrData = wWrData;
end
// Accept requests when the selector indicates. Capture the buffered
// request parameters for hand-off to the formatting pipeline. Then
// acknowledge the receipt to the channel so it can deassert the
// request, and let the selector choose another channel.
always @ (posedge CLK) begin
rCapState <= #1 (RST_IN ? `S_TXENGUPR32_CAP_RD_WR : _rCapState);
rRdAck <= #1 (RST_IN ? {C_NUM_CHNL{1'd0}} : _rRdAck);
rWrAck <= #1 (RST_IN ? {C_NUM_CHNL{1'd0}} : _rWrAck);
rIsWr <= #1 _rIsWr;
rCapChnl <= #1 _rCapChnl;
rCapAddr <= #1 _rCapAddr;
rCapAddr64 <= #1 _rCapAddr64;
rCapLen <= #1 _rCapLen;
rCapIsWr <= #1 _rCapIsWr;
rExtTagReq <= #1 _rExtTagReq;
rExtTag <= #1 _rExtTag;
rTxEngRdReqAck <= #1 _rTxEngRdReqAck;
end
always @ (*) begin
_rCapState = rCapState;
_rRdAck = rRdAck;
_rWrAck = rWrAck;
_rIsWr = rIsWr;
_rCapChnl = rCapChnl;
_rCapAddr = rCapAddr;
_rCapAddr64 = (rCapAddr[61:30] != 0);
_rCapLen = rCapLen;
_rCapIsWr = rCapIsWr;
_rExtTagReq = rExtTagReq;
_rExtTag = rExtTag;
_rTxEngRdReqAck = rTxEngRdReqAck;
case (rCapState)
`S_TXENGUPR32_CAP_RD_WR : begin
_rIsWr = !wRdReq;
_rRdAck = ((wRdAck)<<wRdReqChnl);
_rTxEngRdReqAck = wRdAck;
_rExtTagReq = wRdAck;
_rCapState = (wRdAck ? `S_TXENGUPR32_CAP_CAP : `S_TXENGUPR32_CAP_WR_RD);
end
`S_TXENGUPR32_CAP_WR_RD : begin
_rIsWr = wWrReq;
_rWrAck = (wWrReq<<wWrReqChnl);
_rCapState = (wWrReq ? `S_TXENGUPR32_CAP_CAP : `S_TXENGUPR32_CAP_RD_WR);
end
`S_TXENGUPR32_CAP_CAP : begin
_rTxEngRdReqAck = 0;
_rRdAck = 0;
_rWrAck = 0;
_rCapIsWr = rIsWr;
_rExtTagReq = 0;
_rExtTag = EXT_TAG;
if (rIsWr) begin
_rCapChnl = {2'd0, rWrChnl};
_rCapAddr = rWrAddr;
_rCapLen = rWrLen;
end
else begin
_rCapChnl = {rRdSgChnl, rRdChnl};
_rCapAddr = rRdAddr;
_rCapLen = rRdLen;
end
_rCapState = `S_TXENGUPR32_CAP_REL;
end
`S_TXENGUPR32_CAP_REL : begin
// Push into the formatting pipeline when ready
if (TXR_META_READY & rMainState[0]) // S_TXENGUPR32_MAIN_IDLE
_rCapState = (`S_TXENGUPR32_CAP_WR_RD>>(rCapIsWr)); // Changes to S_TXENGUPR32_CAP_RD_WR
end
default : begin
_rCapState = `S_TXENGUPR32_CAP_RD_WR;
end
endcase
end
// Start the read/write when space is available in the output FIFO and when
// request parameters have been captured (i.e. a pending request).
always @ (posedge CLK) begin
rMainState <= #1 (RST_IN ? `S_TXENGUPR32_MAIN_IDLE : _rMainState);
rCount <= #1 _rCount;
rCountDone <= #1 _rCountDone;
rCountStart <= #1 _rCountStart;
rCountChnl <= #1 _rCountChnl;
rCountTag <= #1 _rCountTag;
rCount32 <= #1 _rCount32;
rWrDataRen <= #1 _rWrDataRen;
end
always @ (*) begin
_rMainState = rMainState;
_rCount = rCount;
_rCountDone = rCountDone;
_rCountChnl = rCountChnl;
_rCountTag = rCountTag;
_rCount32 = rCount32;
_rWrDataRen = rWrDataRen;
_rCountStart = 0;
case (rMainState)
`S_TXENGUPR32_MAIN_IDLE : begin
_rCount = rCapLen;
_rCountDone = (rCapLen == 10'd1);
_rCountChnl = rCapChnl[3:0];
_rCountTag = rExtTag;
_rCount32 = (rCapAddr[61:30] == 0);
_rWrDataRen = ((TXR_META_READY & rCapState[3] & rCapIsWr)<<(rCapChnl[3:0])); // S_TXENGUPR32_CAP_REL
_rCountStart = (TXR_META_READY & rCapState[3]);
if (TXR_META_READY & rCapState[3]) // S_TXENGUPR32_CAP_REL
_rMainState = (`S_TXENGUPR32_MAIN_RD<<(rCapIsWr)); // Change to S_TXENGUPR32_MAIN_WR;
end
`S_TXENGUPR32_MAIN_RD : begin
_rMainState = (`S_TXENGUPR32_MAIN_WAIT_1<<(rCount32)); // Change to S_TXENGUPR32_MAIN_WAIT_2
end
`S_TXENGUPR32_MAIN_WR : begin
_rCount = rCount - 1'd1;
_rCountDone = (rCount == 2'd2);
if (rCountDone) begin
_rWrDataRen = 0;
_rMainState = (`S_TXENGUPR32_MAIN_WAIT_0<<(rCount32)); // Change to S_TXENGUPR32_MAIN_WAIT_1
end
end
`S_TXENGUPR32_MAIN_WAIT_0 : begin
_rMainState = `S_TXENGUPR32_MAIN_WAIT_1;
end
`S_TXENGUPR32_MAIN_WAIT_1 : begin
_rMainState = `S_TXENGUPR32_MAIN_WAIT_2;
end
`S_TXENGUPR32_MAIN_WAIT_2 : begin
_rMainState = `S_TXENGUPR32_MAIN_IDLE;
end
default : begin
_rMainState = `S_TXENGUPR32_MAIN_IDLE;
end
endcase
end
// Shift in the captured parameters and valid signal every cycle.
// This pipeline will keep the formatter busy.
assign wCountChnl = rCountChnl[3:0];
always @ (posedge CLK) begin
rWnR <= #1 _rWnR;
rChnl <= #1 _rChnl;
rTag <= #1 _rTag;
rAddr <= #1 _rAddr;
rAddr64 <= #1 _rAddr64;
rLen <= #1 _rLen;
rLenEQ1 <= #1 _rLenEQ1;
rValid <= #1 _rValid;
end
always @ (*) begin
_rWnR = ((rWnR<<1) | rCapIsWr);
_rChnl = ((rChnl<<4) | rCountChnl);
_rTag = ((rTag<<8) | (8'd0 | rCountTag));
_rAddr = ((rAddr<<62) | rCapAddr);
_rAddr64 = ((rAddr64<<1) | rCapAddr64);
_rLen = ((rLen<<10) | rCapLen);
_rLenEQ1 = ((rLenEQ1<<1) | (rCapLen == 10'd1));
_rValid = ((rValid<<1) | (rMainState[2] | rMainState[1])); // S_TXENGUPR64_MAIN_RD | S_TXENGUPR64_MAIN_WR
_rDone = rDone<<1 | rCountDone;
_rStart = rStart<<1 | rCountStart;
end
assign TXR_DATA = rWrData;
assign TXR_DATA_VALID = rValid[(C_DATA_DELAY-1)*1 +:1];
assign TXR_DATA_START_FLAG = rStart[(C_DATA_DELAY-1)*1 +:1];
assign TXR_DATA_START_OFFSET = 0;
assign TXR_DATA_END_FLAG = rDone[(C_DATA_DELAY-1)*1 +:1];
assign TXR_DATA_END_OFFSET = rLen[(C_DATA_DELAY-1)*10 +:`SIG_OFFSET_W] - 1;
assign TXR_META_VALID = rCountStart;
assign TXR_META_TYPE = rCapIsWr ? `TRLS_REQ_WR : `TRLS_REQ_RD;
assign TXR_META_ADDR = {rCapAddr,2'b00};
assign TXR_META_LENGTH = rCapLen;
assign TXR_META_LDWBE = rCapLen == 10'd1 ? 0 : 4'b1111;
assign TXR_META_FDWBE = 4'b1111;
assign TXR_META_TAG = rCountTag;
assign TXR_META_EP = 1'b0;
assign TXR_META_ATTR = 3'b110;
assign TXR_META_TC = 0;
endmodule |
module sky130_fd_sc_ms__nand4b (
Y ,
A_N ,
B ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A_N ;
input B ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule |
module sky130_fd_sc_hs__dlrtp (
RESET_B,
D ,
GATE ,
Q
);
input RESET_B;
input D ;
input GATE ;
output Q ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule |
module sky130_fd_sc_hvl__dfrbp (
Q ,
Q_N ,
CLK ,
D ,
RESET_B
);
output Q ;
output Q_N ;
input CLK ;
input D ;
input RESET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule |
module sky130_fd_sc_hdll__clkinvlp (
Y,
A
);
// Module ports
output Y;
input A;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire not0_out_Y;
// Name Output Other arguments
not not0 (not0_out_Y, A );
buf buf0 (Y , not0_out_Y );
endmodule |
module one0_handler (oh1,control,literal);
input [13:0] oh1;
output reg [15:0] literal;
output reg [25:0] control;
always begin
case (oh1[13:9])
5'b110xx: begin assign control = {8'b01100000,oh1[10:8],14'b000101};
assign literal={oh1[7],oh1[7],oh1[7],oh1[7],oh1[7],oh1[7],oh1[7],oh1[7],oh1[7:0]}; end //brz
5'b111xx: begin assign control = {8'b01100000,oh1[10:8],14'b000101};
assign literal={oh1[7],oh1[7],oh1[7],oh1[7],oh1[7],oh1[7],oh1[7],oh1[7],oh1[7:0]}; end //brn
5'b100xx: begin assign control = {5'b00000,oh1[10:8],17'b00000000101000010};
assign literal={4'b0000,oh1[7:0]}; end
5'b101xx: begin assign control = {8'b01100000,oh1[10:8],14'b00010110100000};
assign literal={4'b0000,oh1[7:0]}; end
5'b01100: begin assign control = {8'b01100000,oh1[10:8],14'b00010010000001};
assign literal={3'b000,oh1[8:0]}; end
5'b01101: begin assign control = {11'b01100000000,oh1[10:8],11'b11010000001};
assign literal={3'b000,oh1[8:0]}; end
5'b00010: begin assign control = {5'b00000,oh1[10:8],14'b00000000000110};
assign literal={3'b000,oh1[8:0]}; end
endcase
end
endmodule |
module store_queue(
input clk, rst,
input issue, mem_wen,
input mem_ren, //this is a load, don't release a store at this cycle, since d-mem is single port
input [31:0] rs_data, //used to calculating load/store address
input [31:0] rt_data, //data for store
//from the load-store station
input [15:0] immed,
input [3:0] rob_in,
input [5:0] p_rd_in,
input stall_hazard,
//from ROB, for retire stage, set the ready bit in
input retire_ST,
input [3:0] retire_rob,
input recover,
input [3:0] rec_rob,
output sq_full,
//////////////these five signals go to the arbiter,
output reg isLS,
output [31:0] load_result,
output reg [5:0] ls_p_rd,
output reg [3:0] ls_rob,
output reg ls_RegDest
//this signal is the write enable signal for store queue, it indicates the complete of the store instruction
);
///////////////***************************store queue logic********************************//////////////////////
reg [3:0] head, tail;
reg [1:0] head_addr;
reg [2:0] counter;
wire read, write;
wire head_retired;
//issue head store to data memory when the head is ready, and no load executed
assign read = !stall_hazard && !recover && head_retired && !mem_ren;
//get instruction from the reservation station if it is a store and it is issued
assign write = issue && mem_wen && !stall_hazard && !recover && !sq_full;
//counter recording full or empty status
always @(posedge clk or negedge rst) begin
if (!rst)
counter <= 3'b000;
else if (write && read)
counter <= counter;
else if (write)
counter <= counter + 1;
else if (read)
counter <= counter - 1;
end
assign sq_full = (counter == 3'b100);
//increase head when read, increase tail when write
always @(posedge clk or negedge rst) begin
if (!rst) begin
head <= 4'b0001;
head_addr <= 2'b00;
tail <= 4'b0001;
end
else begin
if (write) begin
tail <= {tail[2:0], tail[3]};
end
if (read) begin
head <= {head[2:0], head[3]};
head_addr <= head_addr + 1;
end
end
end
reg [31:0] value_queue [0:3];
reg [15:0] addr_queue [0:3];
reg [3:0] rob_queue [0:3];
reg [2:0] control_queue [0:3]; //[0]:valid, [1]:mem_wen [2]: ready
//reg [1:0] priority_queue [0:3]; //recoding priority, deciding which store is the youngest
////////////////////////memory address generator
wire [31:0] address_in;
assign address_in = rs_data + {{16{immed[15]}}, immed};
/////////////////combinational logic, comparators////////////////////////////
wire [3:0] rt_rob_match_array, rec_rob_match_array, addr_match_array;
genvar i;
generate for(i = 0; i < 4; i = i + 1) begin : combinational
//for retire stage, set the ready bit
assign rt_rob_match_array[i] = (rob_queue[i] == retire_rob) && retire_ST && control_queue[i][0] && control_queue[i][1];
//for recovery, flush the entry if rob number matches, and recover is high
assign rec_rob_match_array[i] = (rob_queue[i] == rec_rob) && recover && control_queue[i][0] && control_queue[i][1];
//for incoming load instruction, address match when valid, mem_ren is 1,
assign addr_match_array[i] = (addr_queue[i] == address_in[15:0]) && control_queue[i][0] && control_queue[i][1] && mem_ren;
end
endgenerate
////////////////////////sequential logic/////////////////////////////////////////
genvar j;
generate for (j = 0; j < 4; j = j + 1) begin : sequential
always @(posedge clk or negedge rst) begin
if (!rst) begin
value_queue[j] <= 0;
addr_queue[j] <= 0;
rob_queue[j] <= 0;
control_queue[j] <= 0;
end
else if (write && tail[j]) begin //this is the tail, match cannot happen on tail,
value_queue[j] <= rt_data;
addr_queue[j] <= address_in[15:0]; //the memory will only use 16 bit memory address
rob_queue[j] <= rob_in;
control_queue[j] <= {1'b0, mem_wen, 1'b1};
end else begin
if (rt_rob_match_array[j]) begin //set ready bit
control_queue[j][2] <= 1'b1;
end
if (rec_rob_match_array[j]) begin //flush this entry
control_queue[j][1] <= 1'b0; //only need to flush mem_wen, thus it cannot write to D-Mem, and cannot
end //match with incoming load, retired rob
if (read && head[j]) begin
control_queue[j][0] <= 1'b0; //set to invalid
end
end
end
end
endgenerate
assign head_retired = control_queue[head_addr][2] && control_queue[head_addr][0];
///////////////***************************end of store queue logic********************************//////////////////////
//////////////////////////////////////////data memory and load forwarding logic/////////////////////////
//////////////signals from store queue (load instruction will also use this address) to the memory
wire [31:0] store_data;
wire [15:0] mem_addr; //can be store addr or load addr
wire mem_wen_out;
wire mem_ren_out;
wire [31:0] load_data_from_mem;
wire [31:0] fwd_data_int;
wire isFwd;
assign store_data = value_queue[head_addr];
assign mem_addr = mem_ren_out ? address_in : addr_queue[head_addr];
assign mem_wen_out = (& control_queue[head_addr]) && !mem_ren;
assign mem_ren_out = mem_ren && issue;
////////////this may lead to errors if one stores to same address twice within 4 stores
assign fwd_data_int = addr_match_array[0] ? value_queue[0] :
addr_match_array[1] ? value_queue[1] :
addr_match_array[2] ? value_queue[2] :
addr_match_array[3] ? value_queue[3] : 32'h00000000;
assign isFwd = |addr_match_array; //if any of the entry matches, forwarding the data to load
/////////////////////////////data memory, data available at next clock edge////////////////////
data_mem i_data_mem(.clk(clk), .en(mem_ren_out), .we(mem_wen_out), .wdata(store_data), .addr(mem_addr[13:0]), .rdata(load_data_from_mem));
reg isFwd_reg;
reg [31:0] fwd_data_reg;
//////delay forwarding data by 1 cycle, because the load data from another path(memory) has 1 cycle delay
always @(posedge clk or negedge rst) begin
if (!rst) begin
fwd_data_reg <= 0;
isFwd_reg <= 0;
isLS <= 0;
ls_p_rd <= 0;
ls_rob <= 0;
ls_RegDest <= 0;
end
else begin
fwd_data_reg <= fwd_data_int;
isFwd_reg <= isFwd;
isLS <= mem_ren_out | write;
ls_p_rd <= p_rd_in;
ls_rob <= rob_in;
ls_RegDest <= mem_ren && issue;
end
end
assign load_result = isFwd_reg ? fwd_data_reg : load_data_from_mem;
endmodule |
module eth_mac_1g #
(
parameter DATA_WIDTH = 8,
parameter ENABLE_PADDING = 1,
parameter MIN_FRAME_LENGTH = 64,
parameter TX_PTP_TS_ENABLE = 0,
parameter TX_PTP_TS_WIDTH = 96,
parameter TX_PTP_TAG_ENABLE = TX_PTP_TS_ENABLE,
parameter TX_PTP_TAG_WIDTH = 16,
parameter RX_PTP_TS_ENABLE = 0,
parameter RX_PTP_TS_WIDTH = 96,
parameter TX_USER_WIDTH = (TX_PTP_TAG_ENABLE ? TX_PTP_TAG_WIDTH : 0) + 1,
parameter RX_USER_WIDTH = (RX_PTP_TS_ENABLE ? RX_PTP_TS_WIDTH : 0) + 1
)
(
input wire rx_clk,
input wire rx_rst,
input wire tx_clk,
input wire tx_rst,
/*
* AXI input
*/
input wire [DATA_WIDTH-1:0] tx_axis_tdata,
input wire tx_axis_tvalid,
output wire tx_axis_tready,
input wire tx_axis_tlast,
input wire [TX_USER_WIDTH-1:0] tx_axis_tuser,
/*
* AXI output
*/
output wire [DATA_WIDTH-1:0] rx_axis_tdata,
output wire rx_axis_tvalid,
output wire rx_axis_tlast,
output wire [RX_USER_WIDTH-1:0] rx_axis_tuser,
/*
* GMII interface
*/
input wire [DATA_WIDTH-1:0] gmii_rxd,
input wire gmii_rx_dv,
input wire gmii_rx_er,
output wire [DATA_WIDTH-1:0] gmii_txd,
output wire gmii_tx_en,
output wire gmii_tx_er,
/*
* PTP
*/
input wire [TX_PTP_TS_WIDTH-1:0] tx_ptp_ts,
input wire [RX_PTP_TS_WIDTH-1:0] rx_ptp_ts,
output wire [TX_PTP_TS_WIDTH-1:0] tx_axis_ptp_ts,
output wire [TX_PTP_TAG_WIDTH-1:0] tx_axis_ptp_ts_tag,
output wire tx_axis_ptp_ts_valid,
/*
* Control
*/
input wire rx_clk_enable,
input wire tx_clk_enable,
input wire rx_mii_select,
input wire tx_mii_select,
/*
* Status
*/
output wire tx_start_packet,
output wire tx_error_underflow,
output wire rx_start_packet,
output wire rx_error_bad_frame,
output wire rx_error_bad_fcs,
/*
* Configuration
*/
input wire [7:0] ifg_delay
);
axis_gmii_rx #(
.DATA_WIDTH(DATA_WIDTH),
.PTP_TS_ENABLE(RX_PTP_TS_ENABLE),
.PTP_TS_WIDTH(RX_PTP_TS_WIDTH),
.USER_WIDTH(RX_USER_WIDTH)
)
axis_gmii_rx_inst (
.clk(rx_clk),
.rst(rx_rst),
.gmii_rxd(gmii_rxd),
.gmii_rx_dv(gmii_rx_dv),
.gmii_rx_er(gmii_rx_er),
.m_axis_tdata(rx_axis_tdata),
.m_axis_tvalid(rx_axis_tvalid),
.m_axis_tlast(rx_axis_tlast),
.m_axis_tuser(rx_axis_tuser),
.ptp_ts(rx_ptp_ts),
.clk_enable(rx_clk_enable),
.mii_select(rx_mii_select),
.start_packet(rx_start_packet),
.error_bad_frame(rx_error_bad_frame),
.error_bad_fcs(rx_error_bad_fcs)
);
axis_gmii_tx #(
.DATA_WIDTH(DATA_WIDTH),
.ENABLE_PADDING(ENABLE_PADDING),
.MIN_FRAME_LENGTH(MIN_FRAME_LENGTH),
.PTP_TS_ENABLE(TX_PTP_TS_ENABLE),
.PTP_TS_WIDTH(TX_PTP_TS_WIDTH),
.PTP_TAG_ENABLE(TX_PTP_TAG_ENABLE),
.PTP_TAG_WIDTH(TX_PTP_TAG_WIDTH),
.USER_WIDTH(TX_USER_WIDTH)
)
axis_gmii_tx_inst (
.clk(tx_clk),
.rst(tx_rst),
.s_axis_tdata(tx_axis_tdata),
.s_axis_tvalid(tx_axis_tvalid),
.s_axis_tready(tx_axis_tready),
.s_axis_tlast(tx_axis_tlast),
.s_axis_tuser(tx_axis_tuser),
.gmii_txd(gmii_txd),
.gmii_tx_en(gmii_tx_en),
.gmii_tx_er(gmii_tx_er),
.ptp_ts(tx_ptp_ts),
.m_axis_ptp_ts(tx_axis_ptp_ts),
.m_axis_ptp_ts_tag(tx_axis_ptp_ts_tag),
.m_axis_ptp_ts_valid(tx_axis_ptp_ts_valid),
.clk_enable(tx_clk_enable),
.mii_select(tx_mii_select),
.ifg_delay(ifg_delay),
.start_packet(tx_start_packet),
.error_underflow(tx_error_underflow)
);
endmodule |
module.
// In general, the default values need not be changed.
// State "m1_rx_clk_l" has been chosen on purpose. Since the input
// synchronizing flip-flops initially contain zero, it takes one clk
// for them to update to reflect the actual (idle = high) status of
// the I/O lines from the keyboard. Therefore, choosing 0 for m1_rx_clk_l
// allows the state machine to transition to m1_rx_clk_h when the true
// values of the input signals become present at the outputs of the
// synchronizing flip-flops. This initial transition is harmless, and it
// eliminates the need for a "reset" pulse before the interface can operate.
parameter m1_rx_clk_h = 1;
parameter m1_rx_clk_l = 0;
parameter m1_rx_falling_edge_marker = 13;
parameter m1_rx_rising_edge_marker = 14;
parameter m1_tx_force_clk_l = 3;
parameter m1_tx_first_wait_clk_h = 10;
parameter m1_tx_first_wait_clk_l = 11;
parameter m1_tx_reset_timer = 12;
parameter m1_tx_wait_clk_h = 2;
parameter m1_tx_clk_h = 4;
parameter m1_tx_clk_l = 5;
parameter m1_tx_wait_keyboard_ack = 6;
parameter m1_tx_done_recovery = 7;
parameter m1_tx_error_no_keyboard_ack = 8;
parameter m1_tx_rising_edge_marker = 9;
// Nets and registers
wire rx_output_event;
wire rx_output_strobe;
wire rx_shifting_done;
wire tx_shifting_done;
wire timer_60usec_done;
wire timer_5usec_done;
wire released;
wire [6:0] xt_code;
reg [3:0] bit_count;
reg [3:0] m1_state;
reg [3:0] m1_next_state;
reg ps2_clk_hi_z; // Without keyboard, high Z equals 1 due to pullups.
reg ps2_data_hi_z; // Without keyboard, high Z equals 1 due to pullups.
reg ps2_clk_s; // Synchronous version of this input
reg ps2_data_s; // Synchronous version of this input
reg enable_timer_60usec;
reg enable_timer_5usec;
reg [TIMER_60USEC_BITS_PP-1:0] timer_60usec_count;
reg [TIMER_5USEC_BITS_PP-1:0] timer_5usec_count;
reg [`TOTAL_BITS-1:0] q;
reg hold_released; // Holds prior value, cleared at rx_output_strobe
// Module instantiation
translate_8042 tr0 (
.at_code (q[7:1]),
.xt_code (xt_code)
);
// Continuous assignments
// This signal is high for one clock at the end of the timer count.
assign rx_shifting_done = (bit_count == `TOTAL_BITS);
assign tx_shifting_done = (bit_count == `TOTAL_BITS-1);
assign rx_output_event = (rx_shifting_done
&& ~released
);
assign rx_output_strobe = (rx_shifting_done
&& ~released
&& ( (TRAP_SHIFT_KEYS_PP == 0)
|| ( (q[8:1] != `RIGHT_SHIFT)
&&(q[8:1] != `LEFT_SHIFT)
)
)
);
assign ps2_clk_ = ps2_clk_hi_z ? 1'bZ : 1'b0;
assign ps2_data_ = ps2_data_hi_z ? 1'bZ : 1'b0;
assign timer_60usec_done =
(timer_60usec_count == (TIMER_60USEC_VALUE_PP - 1));
assign timer_5usec_done = (timer_5usec_count == TIMER_5USEC_VALUE_PP - 1);
// Create the signals which indicate special scan codes received.
// These are the "unlatched versions."
//assign extended = (q[8:1] == `EXTEND_CODE) && rx_shifting_done;
assign released = (q[8:1] == `RELEASE_CODE) && rx_shifting_done;
// Behaviour
// intr
always @(posedge wb_clk_i)
wb_tgc_o <= wb_rst_i ? 1'b0
: ((rx_output_strobe & !wb_tgc_i) ? 1'b1
: (wb_tgc_o ? !wb_tgc_i : 1'b0));
// This is the shift register
always @(posedge wb_clk_i)
if (wb_rst_i) q <= 0;
// else if (((m1_state == m1_rx_clk_h) && ~ps2_clk_s)
else if ( (m1_state == m1_rx_falling_edge_marker)
||(m1_state == m1_tx_rising_edge_marker) )
q <= {ps2_data_s,q[`TOTAL_BITS-1:1]};
// This is the 60usec timer counter
always @(posedge wb_clk_i)
if (~enable_timer_60usec) timer_60usec_count <= 0;
else if (~timer_60usec_done) timer_60usec_count <= timer_60usec_count + 1;
// This is the 5usec timer counter
always @(posedge wb_clk_i)
if (~enable_timer_5usec) timer_5usec_count <= 0;
else if (~timer_5usec_done) timer_5usec_count <= timer_5usec_count + 1;
// Input "synchronizing" logic -- synchronizes the inputs to the state
// machine clock, thus avoiding errors related to
// spurious state machine transitions.
//
// Since the initial state of registers is zero, and the idle state
// of the ps2_clk and ps2_data lines is "1" (due to pullups), the
// "sense" of the ps2_clk_s signal is inverted from the true signal.
// This allows the state machine to "come up" in the correct
always @(posedge wb_clk_i)
begin
ps2_clk_s <= ps2_clk_;
ps2_data_s <= ps2_data_;
end
// State transition logic
always @(m1_state
or q
or tx_shifting_done
or ps2_clk_s
or ps2_data_s
or timer_60usec_done
or timer_5usec_done
)
begin : m1_state_logic
// Output signals default to this value,
// unless changed in a state condition.
ps2_clk_hi_z <= 1;
ps2_data_hi_z <= 1;
enable_timer_60usec <= 0;
enable_timer_5usec <= 0;
case (m1_state)
m1_rx_clk_h :
begin
enable_timer_60usec <= 1;
if (~ps2_clk_s)
m1_next_state <= m1_rx_falling_edge_marker;
else m1_next_state <= m1_rx_clk_h;
end
m1_rx_falling_edge_marker :
begin
enable_timer_60usec <= 0;
m1_next_state <= m1_rx_clk_l;
end
m1_rx_rising_edge_marker :
begin
enable_timer_60usec <= 0;
m1_next_state <= m1_rx_clk_h;
end
m1_rx_clk_l :
begin
enable_timer_60usec <= 1;
if (ps2_clk_s)
m1_next_state <= m1_rx_rising_edge_marker;
else m1_next_state <= m1_rx_clk_l;
end
m1_tx_reset_timer :
begin
enable_timer_60usec <= 0;
m1_next_state <= m1_tx_force_clk_l;
end
m1_tx_force_clk_l :
begin
enable_timer_60usec <= 1;
ps2_clk_hi_z <= 0; // Force the ps2_clk line low.
if (timer_60usec_done)
m1_next_state <= m1_tx_first_wait_clk_h;
else m1_next_state <= m1_tx_force_clk_l;
end
m1_tx_first_wait_clk_h :
begin
enable_timer_5usec <= 1;
ps2_data_hi_z <= 0; // Start bit.
if (~ps2_clk_s && timer_5usec_done)
m1_next_state <= m1_tx_clk_l;
else
m1_next_state <= m1_tx_first_wait_clk_h;
end
// This state must be included because the device might possibly
// delay for up to 10 milliseconds before beginning its clock pulses.
// During that waiting time, we cannot drive the data (q[0]) because it
// is possibly 1, which would cause the keyboard to abort its receive
// and the expected clocks would then never be generated.
m1_tx_first_wait_clk_l :
begin
ps2_data_hi_z <= 0;
if (~ps2_clk_s) m1_next_state <= m1_tx_clk_l;
else m1_next_state <= m1_tx_first_wait_clk_l;
end
m1_tx_wait_clk_h :
begin
enable_timer_5usec <= 1;
ps2_data_hi_z <= q[0];
if (ps2_clk_s && timer_5usec_done)
m1_next_state <= m1_tx_rising_edge_marker;
else
m1_next_state <= m1_tx_wait_clk_h;
end
m1_tx_rising_edge_marker :
begin
ps2_data_hi_z <= q[0];
m1_next_state <= m1_tx_clk_h;
end
m1_tx_clk_h :
begin
ps2_data_hi_z <= q[0];
if (tx_shifting_done) m1_next_state <= m1_tx_wait_keyboard_ack;
else if (~ps2_clk_s) m1_next_state <= m1_tx_clk_l;
else m1_next_state <= m1_tx_clk_h;
end
m1_tx_clk_l :
begin
ps2_data_hi_z <= q[0];
if (ps2_clk_s) m1_next_state <= m1_tx_wait_clk_h;
else m1_next_state <= m1_tx_clk_l;
end
m1_tx_wait_keyboard_ack :
begin
if (~ps2_clk_s && ps2_data_s)
m1_next_state <= m1_tx_error_no_keyboard_ack;
else if (~ps2_clk_s && ~ps2_data_s)
m1_next_state <= m1_tx_done_recovery;
else m1_next_state <= m1_tx_wait_keyboard_ack;
end
m1_tx_done_recovery :
begin
if (ps2_clk_s && ps2_data_s) m1_next_state <= m1_rx_clk_h;
else m1_next_state <= m1_tx_done_recovery;
end
m1_tx_error_no_keyboard_ack :
begin
if (ps2_clk_s && ps2_data_s) m1_next_state <= m1_rx_clk_h;
else m1_next_state <= m1_tx_error_no_keyboard_ack;
end
default : m1_next_state <= m1_rx_clk_h;
endcase
end
// State register
always @(posedge wb_clk_i)
begin : m1_state_register
if (wb_rst_i) m1_state <= m1_rx_clk_h;
else m1_state <= m1_next_state;
end
// wb_dat_o - scancode
always @(posedge wb_clk_i)
if (wb_rst_i) wb_dat_o <= 8'b0;
else wb_dat_o <=
(rx_output_strobe && q[8:1]) ? (q[8] ? q[8:1]
: {hold_released,xt_code})
: wb_dat_o;
// This is the bit counter
always @(posedge wb_clk_i)
begin
if (wb_rst_i
|| rx_shifting_done
|| (m1_state == m1_tx_wait_keyboard_ack) // After tx is done.
) bit_count <= 0; // normal reset
else if (timer_60usec_done
&& (m1_state == m1_rx_clk_h)
&& (ps2_clk_s)
) bit_count <= 0; // rx watchdog timer reset
else if ( (m1_state == m1_rx_falling_edge_marker) // increment for rx
||(m1_state == m1_tx_rising_edge_marker) // increment for tx
)
bit_count <= bit_count + 1;
end
// Store the special scan code status bits
// Not the final output, but an intermediate storage place,
// until the entire set of output data can be assembled.
always @(posedge wb_clk_i)
if (wb_rst_i || rx_output_event) hold_released <= 0;
else if (rx_shifting_done && released) hold_released <= 1;
endmodule |
module translate_8042 (
input [6:0] at_code,
output reg [6:0] xt_code
);
// Behaviour
always @(at_code)
case (at_code)
7'h00: xt_code <= 7'h7f;
7'h01: xt_code <= 7'h43;
7'h02: xt_code <= 7'h41;
7'h03: xt_code <= 7'h3f;
7'h04: xt_code <= 7'h3d;
7'h05: xt_code <= 7'h3b;
7'h06: xt_code <= 7'h3c;
7'h07: xt_code <= 7'h58;
7'h08: xt_code <= 7'h64;
7'h09: xt_code <= 7'h44;
7'h0a: xt_code <= 7'h42;
7'h0b: xt_code <= 7'h40;
7'h0c: xt_code <= 7'h3e;
7'h0d: xt_code <= 7'h0f;
7'h0e: xt_code <= 7'h29;
7'h0f: xt_code <= 7'h59;
7'h10: xt_code <= 7'h65;
7'h11: xt_code <= 7'h38;
7'h12: xt_code <= 7'h2a;
7'h13: xt_code <= 7'h70;
7'h14: xt_code <= 7'h1d;
7'h15: xt_code <= 7'h10;
7'h16: xt_code <= 7'h02;
7'h17: xt_code <= 7'h5a;
7'h18: xt_code <= 7'h66;
7'h19: xt_code <= 7'h71;
7'h1a: xt_code <= 7'h2c;
7'h1b: xt_code <= 7'h1f;
7'h1c: xt_code <= 7'h1e;
7'h1d: xt_code <= 7'h11;
7'h1e: xt_code <= 7'h03;
7'h1f: xt_code <= 7'h5b;
7'h20: xt_code <= 7'h67;
7'h21: xt_code <= 7'h2e;
7'h22: xt_code <= 7'h2d;
7'h23: xt_code <= 7'h20;
7'h24: xt_code <= 7'h12;
7'h25: xt_code <= 7'h05;
7'h26: xt_code <= 7'h04;
7'h27: xt_code <= 7'h5c;
7'h28: xt_code <= 7'h68;
7'h29: xt_code <= 7'h39;
7'h2a: xt_code <= 7'h2f;
7'h2b: xt_code <= 7'h21;
7'h2c: xt_code <= 7'h14;
7'h2d: xt_code <= 7'h13;
7'h2e: xt_code <= 7'h06;
7'h2f: xt_code <= 7'h5d;
7'h30: xt_code <= 7'h69;
7'h31: xt_code <= 7'h31;
7'h32: xt_code <= 7'h30;
7'h33: xt_code <= 7'h23;
7'h34: xt_code <= 7'h22;
7'h35: xt_code <= 7'h15;
7'h36: xt_code <= 7'h07;
7'h37: xt_code <= 7'h5e;
7'h38: xt_code <= 7'h6a;
7'h39: xt_code <= 7'h72;
7'h3a: xt_code <= 7'h32;
7'h3b: xt_code <= 7'h24;
7'h3c: xt_code <= 7'h16;
7'h3d: xt_code <= 7'h08;
7'h3e: xt_code <= 7'h09;
7'h3f: xt_code <= 7'h5f;
7'h40: xt_code <= 7'h6b;
7'h41: xt_code <= 7'h33;
7'h42: xt_code <= 7'h25;
7'h43: xt_code <= 7'h17;
7'h44: xt_code <= 7'h18;
7'h45: xt_code <= 7'h0b;
7'h46: xt_code <= 7'h0a;
7'h47: xt_code <= 7'h60;
7'h48: xt_code <= 7'h6c;
7'h49: xt_code <= 7'h34;
7'h4a: xt_code <= 7'h35;
7'h4b: xt_code <= 7'h26;
7'h4c: xt_code <= 7'h27;
7'h4d: xt_code <= 7'h19;
7'h4e: xt_code <= 7'h0c;
7'h4f: xt_code <= 7'h61;
7'h50: xt_code <= 7'h6d;
7'h51: xt_code <= 7'h73;
7'h52: xt_code <= 7'h28;
7'h53: xt_code <= 7'h74;
7'h54: xt_code <= 7'h1a;
7'h55: xt_code <= 7'h0d;
7'h56: xt_code <= 7'h62;
7'h57: xt_code <= 7'h6e;
7'h58: xt_code <= 7'h3a;
7'h59: xt_code <= 7'h36;
7'h5a: xt_code <= 7'h1c;
7'h5b: xt_code <= 7'h1b;
7'h5c: xt_code <= 7'h75;
7'h5d: xt_code <= 7'h2b;
7'h5e: xt_code <= 7'h63;
7'h5f: xt_code <= 7'h76;
7'h60: xt_code <= 7'h55;
7'h61: xt_code <= 7'h56;
7'h62: xt_code <= 7'h77;
7'h63: xt_code <= 7'h78;
7'h64: xt_code <= 7'h79;
7'h65: xt_code <= 7'h7a;
7'h66: xt_code <= 7'h0e;
7'h67: xt_code <= 7'h7b;
7'h68: xt_code <= 7'h7c;
7'h69: xt_code <= 7'h4f;
7'h6a: xt_code <= 7'h7d;
7'h6b: xt_code <= 7'h4b;
7'h6c: xt_code <= 7'h47;
7'h6d: xt_code <= 7'h7e;
7'h6e: xt_code <= 7'h7f;
7'h6f: xt_code <= 7'h6f;
7'h70: xt_code <= 7'h52;
7'h71: xt_code <= 7'h53;
7'h72: xt_code <= 7'h50;
7'h73: xt_code <= 7'h4c;
7'h74: xt_code <= 7'h4d;
7'h75: xt_code <= 7'h48;
7'h76: xt_code <= 7'h01;
7'h77: xt_code <= 7'h45;
7'h78: xt_code <= 7'h57;
7'h79: xt_code <= 7'h4e;
7'h7a: xt_code <= 7'h51;
7'h7b: xt_code <= 7'h4a;
7'h7c: xt_code <= 7'h37;
7'h7d: xt_code <= 7'h49;
7'h7e: xt_code <= 7'h46;
7'h7f: xt_code <= 7'h54;
endcase
endmodule |
module Key_Command_Controller
(
// Key Input Signals
input KEY_CLEAR,
input KEY_ADD,
input KEY_SUB,
// Command Signals
input CMD_DONE,
output reg CMD_CLEAR,
output reg CMD_COMPUTE,
output reg CMD_OPERATION,
// System Signals
input CLK,
input RESET
);
//
// BCD Binary Encoder State Machine
//
reg [3:0] State;
localparam [3:0]
S0 = 4'b0001,
S1 = 4'b0010,
S2 = 4'b0100,
S3 = 4'b1000;
reg [1:0] key_reg;
always @(posedge CLK, posedge RESET)
begin
if (RESET)
begin
key_reg <= 2'h0;
CMD_CLEAR <= 1'b0;
CMD_COMPUTE <= 1'b0;
CMD_OPERATION <= 1'b0;
State <= S0;
end
else
begin
case (State)
S0 :
begin
// Capture Keys
key_reg <= { KEY_SUB, KEY_ADD };
// Wait for a Key Input
if (KEY_CLEAR)
State <= S2;
else if (KEY_ADD | KEY_SUB)
State <= S1;
end
S1 :
begin
// Set the operation
case (key_reg)
2'b01 : CMD_OPERATION <= 1'b0; // Add
2'b10 : CMD_OPERATION <= 1'b1; // Sub
default : CMD_OPERATION <= 1'b0; // Invalid
endcase
// Only start computation for a valid key input
if (^key_reg)
CMD_COMPUTE <= 1'b1;
// If valid wait for command to finish, otherwise abort.
if (^key_reg)
State <= S3;
else
State <= S0;
end
S2 :
begin
// Set the Clear Command
CMD_CLEAR <= 1'b1;
State <= S3;
end
S3 :
begin
// Clear the Command signals
CMD_CLEAR <= 1'b0;
CMD_COMPUTE <= 1'b0;
// Wait for Command to finish
if (CMD_DONE)
State <= S0;
end
endcase
end
end
endmodule |
module sky130_fd_sc_ls__decaphetap (
VPWR,
VGND,
VPB
);
// Module ports
input VPWR;
input VGND;
input VPB ;
// No contents.
endmodule |
module sky130_fd_sc_hdll__nor4bb (
Y ,
A ,
B ,
C_N ,
D_N ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input C_N ;
input D_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule |
module BAR1_WRAPPER#(
parameter INTERFACE_TYPE = 4'b0010,
parameter FPGA_FAMILY = 8'h14
)
(
clk, // I
rst_n, // I
en,
cfg_cap_max_lnk_width, // I [5:0]
cfg_neg_max_lnk_width, // I [5:0]
cfg_cap_max_lnk_speed, // I [3:0]
cfg_neg_max_lnk_speed, // I [3:0]
cfg_cap_max_payload_size, // I [2:0]
cfg_prg_max_payload_size, // I [2:0]
cfg_max_rd_req_size, // I [2:0]
a_i, // I [6:0]
wr_en_i, // I
wr_be_i, // I [7:0]
wr_busy_o, // O
rd_d_o, // O [31:0]
rd_be_i, // I [3:0]
wr_d_i, // I [31:0]
init_rst_o, // O
mrd_start_o, // O
mrd_done_i, // O
mrd_addr_o, // O [31:0]
mrd_len_o, // O [31:0]
mrd_tlp_tc_o, // O [2:0]
mrd_64b_en_o, // O
mrd_phant_func_dis1_o, // O
mrd_up_addr_o, // O [7:0]
mrd_size_o, // O [31:0]
mrd_relaxed_order_o, // O
mrd_nosnoop_o, // O
mrd_wrr_cnt_o, // O [7:0]
mrd_done_clr, // O
mwr_start_o, // O
mwr_done_i, // I
mwr_addr_o, // O [31:0]
mwr_len_o, // O [31:0]
mwr_tlp_tc_o, // O [2:0]
mwr_64b_en_o, // O
mwr_phant_func_dis1_o, // O
mwr_up_addr_o, // O [7:0]
mwr_size_o, // O [31:0]
mwr_relaxed_order_o, // O
mwr_nosnoop_o, // O
mwr_wrr_cnt_o, // O [7:0]
mwr_done_clr,
cpl_ur_found_i, // I [7:0]
cpl_ur_tag_i, // I [7:0]
cpld_found_i, // I [31:0]
cpld_data_size_i, // I [31:0]
cpld_malformed_i, // I
cpl_streaming_o, // O
rd_metering_o, // O
cfg_interrupt_di, // O
cfg_interrupt_do, // I
cfg_interrupt_mmenable, // I
cfg_interrupt_msienable, // I
cfg_interrupt_legacyclr, // O
`ifdef PCIE2_0
pl_directed_link_change,
pl_ltssm_state,
pl_directed_link_width,
pl_directed_link_speed,
pl_directed_link_auton,
pl_upstream_preemph_src,
pl_sel_link_width,
pl_sel_link_rate,
pl_link_gen2_capable,
pl_link_partner_gen2_supported,
pl_initial_link_width,
pl_link_upcfg_capable,
pl_lane_reversal_mode,
pl_width_change_err_i,
pl_speed_change_err_i,
clr_pl_width_change_err,
clr_pl_speed_change_err,
clear_directed_speed_change_i,
`endif
trn_rnp_ok_n_o,
trn_tstr_n_o
);
parameter BAR1_WR_RST = 5'b00001;
parameter BAR1_WR_WAIT = 5'b00010;
parameter BAR1_WR_READ = 5'b00100;
parameter BAR1_WR_WRITE= 5'b01000;
parameter BAR1_WR_DONE = 5'b10000;
input clk;
input rst_n;
input en;
input [5:0] cfg_cap_max_lnk_width;
input [5:0] cfg_neg_max_lnk_width;
input [3:0] cfg_cap_max_lnk_speed;
input [3:0] cfg_neg_max_lnk_speed;
input [2:0] cfg_cap_max_payload_size;
input [2:0] cfg_prg_max_payload_size;
input [2:0] cfg_max_rd_req_size;
// read port
//
input [6:0] a_i;
input [3:0] rd_be_i;
output [31:0] rd_d_o;
// write port
//
input wr_en_i;
input [7:0] wr_be_i;
input [31:0] wr_d_i;
output wr_busy_o;
// CSR bits
output init_rst_o;
output mrd_start_o;
input mrd_done_i;
output [31:0] mrd_addr_o;
output [15:0] mrd_len_o;
output [2:0] mrd_tlp_tc_o;
output mrd_64b_en_o;
output mrd_phant_func_dis1_o;
output [7:0] mrd_up_addr_o;
output [31:0] mrd_size_o;
output mrd_relaxed_order_o;
output mrd_nosnoop_o;
output [7:0] mrd_wrr_cnt_o;
output mrd_done_clr;
output mwr_start_o;
input mwr_done_i;
output [31:0] mwr_addr_o;
output [15:0] mwr_len_o;
output [2:0] mwr_tlp_tc_o;
output mwr_64b_en_o;
output mwr_phant_func_dis1_o;
output [7:0] mwr_up_addr_o;
output [31:0] mwr_size_o;
output mwr_relaxed_order_o;
output mwr_nosnoop_o;
output [7:0] mwr_wrr_cnt_o;
output mwr_done_clr;
input [7:0] cpl_ur_found_i;
input [7:0] cpl_ur_tag_i;
input [31:0] cpld_found_i;
input [31:0] cpld_data_size_i;
input cpld_malformed_i;
output cpl_streaming_o;
output rd_metering_o;
output trn_rnp_ok_n_o;
output trn_tstr_n_o;
output [7:0] cfg_interrupt_di;
input [7:0] cfg_interrupt_do;
input [2:0] cfg_interrupt_mmenable;
input cfg_interrupt_msienable;
output cfg_interrupt_legacyclr;
`ifdef PCIE2_0
output [1:0] pl_directed_link_change;
input [5:0] pl_ltssm_state;
output [1:0] pl_directed_link_width;
output pl_directed_link_speed;
output pl_directed_link_auton;
output pl_upstream_preemph_src;
input [1:0] pl_sel_link_width;
input pl_sel_link_rate;
input pl_link_gen2_capable;
input pl_link_partner_gen2_supported;
input [2:0] pl_initial_link_width;
input pl_link_upcfg_capable;
input [1:0] pl_lane_reversal_mode;
input pl_width_change_err_i;
input pl_speed_change_err_i;
output clr_pl_width_change_err;
output lr_pl_speed_change_err;
input clear_directed_speed_change_i;
`endif
wire [31:0] bar1_rd_data;
reg [6:0] addr_q;
reg [3:0] wr_be_q;
reg [31:0] wr_d_q;
reg wr_busy_o;
reg bar1_wr_en;
reg [31:0] pre_wr_data;
reg [31:0] bar1_wr_data;
reg [4:0] bar1_wr_state;
// BAR1 write control state machine
//
always @ ( posedge clk ) begin
if( !rst_n ) begin
bar1_wr_en <= 1'b0;
wr_busy_o <= 1'b0;
addr_q <= 7'b0;
wr_be_q <= 4'b0;
wr_d_q <= 32'b0;
pre_wr_data <= 32'b0;
bar1_wr_data <= 32'b0;
bar1_wr_state <= BAR1_WR_RST;
end
else begin
case ( bar1_wr_state )
BAR1_WR_RST: begin
bar1_wr_en <= 1'b0;
wr_busy_o <= 1'b0;
addr_q <= a_i;
if( wr_en_i ) begin
wr_be_q <= wr_be_i[3:0];
wr_d_q <= wr_d_i;
wr_busy_o <= 1'b1;
bar1_wr_state <= BAR1_WR_WAIT;
end
end
BAR1_WR_WAIT: begin
bar1_wr_state <= BAR1_WR_READ;
end
BAR1_WR_READ: begin
pre_wr_data <= bar1_rd_data;
bar1_wr_state <= BAR1_WR_WRITE;
end
BAR1_WR_WRITE: begin
bar1_wr_en <= 1'b1;
bar1_wr_data <= { { wr_be_q[3] ? wr_d_q[31:24] : pre_wr_data[31:24] } ,
{ wr_be_q[2] ? wr_d_q[23:16] : pre_wr_data[23:16] } ,
{ wr_be_q[1] ? wr_d_q[15:8] : pre_wr_data[15:8] } ,
{ wr_be_q[0] ? wr_d_q[7:0] : pre_wr_data[7:0] }
};
bar1_wr_state <= BAR1_WR_DONE;
end
BAR1_WR_DONE: begin
wr_busy_o <= 1'b0;
bar1_wr_state <= BAR1_WR_RST;
end
default: bar1_wr_state <= BAR1_WR_RST;
endcase
end
end
/*
* BAR1 Read Controller
*/
/* Handle Read byte enables */
assign rd_d_o = {{rd_be_i[0] ? bar1_rd_data[07:00] : 8'h0},
{rd_be_i[1] ? bar1_rd_data[15:08] : 8'h0},
{rd_be_i[2] ? bar1_rd_data[23:16] : 8'h0},
{rd_be_i[3] ? bar1_rd_data[31:24] : 8'h0}};
BAR1# (
.INTERFACE_TYPE(INTERFACE_TYPE),
.FPGA_FAMILY(FPGA_FAMILY)
) bar1(
.clk(clk), // I
.rst_n(rst_n), // I
.en(en),
.cfg_cap_max_lnk_width(cfg_cap_max_lnk_width), // I [5:0]
.cfg_neg_max_lnk_width(cfg_neg_max_lnk_width), // I [5:0]
.cfg_cap_max_lnk_speed(cfg_cap_max_lnk_speed),
.cfg_neg_max_lnk_speed(cfg_neg_max_lnk_speed),
.cfg_cap_max_payload_size(cfg_cap_max_payload_size), // I [2:0]
.cfg_prg_max_payload_size(cfg_prg_max_payload_size), // I [2:0]
.cfg_max_rd_req_size(cfg_max_rd_req_size), // I [2:0]
.a_i(addr_q), // I [8:0]
.wr_en_i(bar1_wr_en), // I
.rd_d_o(bar1_rd_data), // O [31:0]
.wr_d_i(bar1_wr_data), // I [31:0]
.init_rst_o(init_rst_o), // O
.mrd_start_o(mrd_start_o), // O
.mrd_done_i(mrd_done_i), // I
.mrd_addr_o(mrd_addr_o), // O [31:0]
.mrd_len_o(mrd_len_o), // O [31:0]
.mrd_tlp_tc_o(mrd_tlp_tc_o), // O [2:0]
.mrd_64b_en_o(mrd_64b_en_o), // O
.mrd_phant_func_dis1_o(mrd_phant_func_dis1_o), // O
.mrd_up_addr_o(mrd_up_addr_o), // O [7:0]
.mrd_size_o(mrd_size_o), // O [31:0]
.mrd_relaxed_order_o(mrd_relaxed_order_o), // O
.mrd_nosnoop_o(mrd_nosnoop_o), // O
.mrd_wrr_cnt_o(mrd_wrr_cnt_o), // O [7:0]
.mrd_done_clr(mrd_done_clr), // O
.mwr_start_o(mwr_start_o), // O
.mwr_done_i(mwr_done_i), // I
.mwr_addr_o(mwr_addr_o), // O [31:0]
.mwr_len_o(mwr_len_o), // O [31:0]
.mwr_tlp_tc_o(mwr_tlp_tc_o), // O [2:0]
.mwr_64b_en_o(mwr_64b_en_o), // O
.mwr_phant_func_dis1_o(mwr_phant_func_dis1_o), // O
.mwr_up_addr_o(mwr_up_addr_o), // O [7:0]
.mwr_size_o(mwr_size_o), // O [31:0]
.mwr_relaxed_order_o(mwr_relaxed_order_o), // O
.mwr_nosnoop_o(mwr_nosnoop_o), // O
.mwr_wrr_cnt_o(mwr_wrr_cnt_o), // O [7:0]
.mwr_done_clr(mwr_done_clr),
.cpl_ur_found_i(cpl_ur_found_i), // I [7:0]
.cpl_ur_tag_i(cpl_ur_tag_i), // I [7:0]
.cpld_found_i(cpld_found_i), // I [31:0]
.cpld_data_size_i(cpld_data_size_i), // I [31:0]
.cpld_malformed_i(cpld_malformed_i), // I
.cpl_streaming_o(cpl_streaming_o), // O
.rd_metering_o(rd_metering_o), // O
.cfg_interrupt_di(cfg_interrupt_di), // O
.cfg_interrupt_do(cfg_interrupt_do), // I
.cfg_interrupt_mmenable(cfg_interrupt_mmenable), // I
.cfg_interrupt_msienable(cfg_interrupt_msienable), // I
.cfg_interrupt_legacyclr(cfg_interrupt_legacyclr), // O
`ifdef PCIE2_0
.pl_directed_link_change(pl_directed_link_change),
.pl_ltssm_state(pl_ltssm_state),
.pl_directed_link_width(pl_directed_link_width),
.pl_directed_link_speed(pl_directed_link_speed),
.pl_directed_link_auton(pl_directed_link_auton),
.pl_upstream_preemph_src(pl_upstream_preemph_src),
.pl_sel_link_width(pl_sel_link_width),
.pl_sel_link_rate(pl_sel_link_rate),
.pl_link_gen2_capable(pl_link_gen2_capable),
.pl_link_partner_gen2_supported(pl_link_partner_gen2_supported),
.pl_initial_link_width(pl_initial_link_width),
.pl_link_upcfg_capable(pl_link_upcfg_capable),
.pl_lane_reversal_mode(pl_lane_reversal_mode),
.pl_width_change_err_i(pl_width_change_err_i),
.pl_speed_change_err_i(pl_speed_change_err_i),
.clr_pl_width_change_err(clr_pl_width_change_err),
.clr_pl_speed_change_err(clr_pl_speed_change_err),
.clear_directed_speed_change_i(clear_directed_speed_change_i),
`endif
.trn_rnp_ok_n_o(trn_rnp_ok_n_o),
.trn_tstr_n_o(trn_tstr_n_o)
);
endmodule |
module Block_Mat_exit1573_p (
ap_clk,
ap_rst,
ap_start,
start_full_n,
ap_done,
ap_continue,
ap_idle,
ap_ready,
start_out,
start_write,
height,
width,
min,
max,
min_out_din,
min_out_full_n,
min_out_write,
img0_rows_V_out_din,
img0_rows_V_out_full_n,
img0_rows_V_out_write,
img0_cols_V_out_din,
img0_cols_V_out_full_n,
img0_cols_V_out_write,
img2_rows_V_out_din,
img2_rows_V_out_full_n,
img2_rows_V_out_write,
img2_cols_V_out_din,
img2_cols_V_out_full_n,
img2_cols_V_out_write,
img3_rows_V_out_din,
img3_rows_V_out_full_n,
img3_rows_V_out_write,
img3_cols_V_out_din,
img3_cols_V_out_full_n,
img3_cols_V_out_write,
p_cols_assign_cast_out_out_din,
p_cols_assign_cast_out_out_full_n,
p_cols_assign_cast_out_out_write,
p_rows_assign_cast_out_out_din,
p_rows_assign_cast_out_out_full_n,
p_rows_assign_cast_out_out_write,
tmp_3_cast_out_out_din,
tmp_3_cast_out_out_full_n,
tmp_3_cast_out_out_write,
max_out_din,
max_out_full_n,
max_out_write
);
parameter ap_ST_fsm_state1 = 1'd1;
input ap_clk;
input ap_rst;
input ap_start;
input start_full_n;
output ap_done;
input ap_continue;
output ap_idle;
output ap_ready;
output start_out;
output start_write;
input [15:0] height;
input [15:0] width;
input [7:0] min;
input [7:0] max;
output [7:0] min_out_din;
input min_out_full_n;
output min_out_write;
output [15:0] img0_rows_V_out_din;
input img0_rows_V_out_full_n;
output img0_rows_V_out_write;
output [15:0] img0_cols_V_out_din;
input img0_cols_V_out_full_n;
output img0_cols_V_out_write;
output [15:0] img2_rows_V_out_din;
input img2_rows_V_out_full_n;
output img2_rows_V_out_write;
output [15:0] img2_cols_V_out_din;
input img2_cols_V_out_full_n;
output img2_cols_V_out_write;
output [15:0] img3_rows_V_out_din;
input img3_rows_V_out_full_n;
output img3_rows_V_out_write;
output [15:0] img3_cols_V_out_din;
input img3_cols_V_out_full_n;
output img3_cols_V_out_write;
output [11:0] p_cols_assign_cast_out_out_din;
input p_cols_assign_cast_out_out_full_n;
output p_cols_assign_cast_out_out_write;
output [11:0] p_rows_assign_cast_out_out_din;
input p_rows_assign_cast_out_out_full_n;
output p_rows_assign_cast_out_out_write;
output [7:0] tmp_3_cast_out_out_din;
input tmp_3_cast_out_out_full_n;
output tmp_3_cast_out_out_write;
output [7:0] max_out_din;
input max_out_full_n;
output max_out_write;
reg ap_done;
reg ap_idle;
reg start_write;
reg min_out_write;
reg img0_rows_V_out_write;
reg img0_cols_V_out_write;
reg img2_rows_V_out_write;
reg img2_cols_V_out_write;
reg img3_rows_V_out_write;
reg img3_cols_V_out_write;
reg p_cols_assign_cast_out_out_write;
reg p_rows_assign_cast_out_out_write;
reg tmp_3_cast_out_out_write;
reg max_out_write;
reg real_start;
reg start_once_reg;
reg ap_done_reg;
(* fsm_encoding = "none" *) reg [0:0] ap_CS_fsm;
wire ap_CS_fsm_state1;
reg internal_ap_ready;
reg min_out_blk_n;
reg img0_rows_V_out_blk_n;
reg img0_cols_V_out_blk_n;
reg img2_rows_V_out_blk_n;
reg img2_cols_V_out_blk_n;
reg img3_rows_V_out_blk_n;
reg img3_cols_V_out_blk_n;
reg p_cols_assign_cast_out_out_blk_n;
reg p_rows_assign_cast_out_out_blk_n;
reg tmp_3_cast_out_out_blk_n;
reg max_out_blk_n;
reg ap_block_state1;
reg [0:0] ap_NS_fsm;
// power-on initialization
initial begin
#0 start_once_reg = 1'b0;
#0 ap_done_reg = 1'b0;
#0 ap_CS_fsm = 1'd1;
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_CS_fsm <= ap_ST_fsm_state1;
end else begin
ap_CS_fsm <= ap_NS_fsm;
end
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_done_reg <= 1'b0;
end else begin
if ((ap_continue == 1'b1)) begin
ap_done_reg <= 1'b0;
end else if ((~((max_out_full_n == 1'b0) | (tmp_3_cast_out_out_full_n == 1'b0) | (p_rows_assign_cast_out_out_full_n == 1'b0) | (p_cols_assign_cast_out_out_full_n == 1'b0) | (real_start == 1'b0) | (img3_cols_V_out_full_n == 1'b0) | (img3_rows_V_out_full_n == 1'b0) | (img2_cols_V_out_full_n == 1'b0) | (img2_rows_V_out_full_n == 1'b0) | (img0_cols_V_out_full_n == 1'b0) | (img0_rows_V_out_full_n == 1'b0) | (min_out_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
ap_done_reg <= 1'b1;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
start_once_reg <= 1'b0;
end else begin
if (((internal_ap_ready == 1'b0) & (real_start == 1'b1))) begin
start_once_reg <= 1'b1;
end else if ((internal_ap_ready == 1'b1)) begin
start_once_reg <= 1'b0;
end
end
end
always @ (*) begin
if ((~((max_out_full_n == 1'b0) | (tmp_3_cast_out_out_full_n == 1'b0) | (p_rows_assign_cast_out_out_full_n == 1'b0) | (p_cols_assign_cast_out_out_full_n == 1'b0) | (real_start == 1'b0) | (img3_cols_V_out_full_n == 1'b0) | (img3_rows_V_out_full_n == 1'b0) | (img2_cols_V_out_full_n == 1'b0) | (img2_rows_V_out_full_n == 1'b0) | (img0_cols_V_out_full_n == 1'b0) | (img0_rows_V_out_full_n == 1'b0) | (min_out_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
ap_done = 1'b1;
end else begin
ap_done = ap_done_reg;
end
end
always @ (*) begin
if (((real_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin
ap_idle = 1'b1;
end else begin
ap_idle = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_CS_fsm_state1)) begin
img0_cols_V_out_blk_n = img0_cols_V_out_full_n;
end else begin
img0_cols_V_out_blk_n = 1'b1;
end
end
always @ (*) begin
if ((~((max_out_full_n == 1'b0) | (tmp_3_cast_out_out_full_n == 1'b0) | (p_rows_assign_cast_out_out_full_n == 1'b0) | (p_cols_assign_cast_out_out_full_n == 1'b0) | (real_start == 1'b0) | (img3_cols_V_out_full_n == 1'b0) | (img3_rows_V_out_full_n == 1'b0) | (img2_cols_V_out_full_n == 1'b0) | (img2_rows_V_out_full_n == 1'b0) | (img0_cols_V_out_full_n == 1'b0) | (img0_rows_V_out_full_n == 1'b0) | (min_out_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
img0_cols_V_out_write = 1'b1;
end else begin
img0_cols_V_out_write = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_CS_fsm_state1)) begin
img0_rows_V_out_blk_n = img0_rows_V_out_full_n;
end else begin
img0_rows_V_out_blk_n = 1'b1;
end
end
always @ (*) begin
if ((~((max_out_full_n == 1'b0) | (tmp_3_cast_out_out_full_n == 1'b0) | (p_rows_assign_cast_out_out_full_n == 1'b0) | (p_cols_assign_cast_out_out_full_n == 1'b0) | (real_start == 1'b0) | (img3_cols_V_out_full_n == 1'b0) | (img3_rows_V_out_full_n == 1'b0) | (img2_cols_V_out_full_n == 1'b0) | (img2_rows_V_out_full_n == 1'b0) | (img0_cols_V_out_full_n == 1'b0) | (img0_rows_V_out_full_n == 1'b0) | (min_out_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
img0_rows_V_out_write = 1'b1;
end else begin
img0_rows_V_out_write = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_CS_fsm_state1)) begin
img2_cols_V_out_blk_n = img2_cols_V_out_full_n;
end else begin
img2_cols_V_out_blk_n = 1'b1;
end
end
always @ (*) begin
if ((~((max_out_full_n == 1'b0) | (tmp_3_cast_out_out_full_n == 1'b0) | (p_rows_assign_cast_out_out_full_n == 1'b0) | (p_cols_assign_cast_out_out_full_n == 1'b0) | (real_start == 1'b0) | (img3_cols_V_out_full_n == 1'b0) | (img3_rows_V_out_full_n == 1'b0) | (img2_cols_V_out_full_n == 1'b0) | (img2_rows_V_out_full_n == 1'b0) | (img0_cols_V_out_full_n == 1'b0) | (img0_rows_V_out_full_n == 1'b0) | (min_out_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
img2_cols_V_out_write = 1'b1;
end else begin
img2_cols_V_out_write = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_CS_fsm_state1)) begin
img2_rows_V_out_blk_n = img2_rows_V_out_full_n;
end else begin
img2_rows_V_out_blk_n = 1'b1;
end
end
always @ (*) begin
if ((~((max_out_full_n == 1'b0) | (tmp_3_cast_out_out_full_n == 1'b0) | (p_rows_assign_cast_out_out_full_n == 1'b0) | (p_cols_assign_cast_out_out_full_n == 1'b0) | (real_start == 1'b0) | (img3_cols_V_out_full_n == 1'b0) | (img3_rows_V_out_full_n == 1'b0) | (img2_cols_V_out_full_n == 1'b0) | (img2_rows_V_out_full_n == 1'b0) | (img0_cols_V_out_full_n == 1'b0) | (img0_rows_V_out_full_n == 1'b0) | (min_out_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
img2_rows_V_out_write = 1'b1;
end else begin
img2_rows_V_out_write = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_CS_fsm_state1)) begin
img3_cols_V_out_blk_n = img3_cols_V_out_full_n;
end else begin
img3_cols_V_out_blk_n = 1'b1;
end
end
always @ (*) begin
if ((~((max_out_full_n == 1'b0) | (tmp_3_cast_out_out_full_n == 1'b0) | (p_rows_assign_cast_out_out_full_n == 1'b0) | (p_cols_assign_cast_out_out_full_n == 1'b0) | (real_start == 1'b0) | (img3_cols_V_out_full_n == 1'b0) | (img3_rows_V_out_full_n == 1'b0) | (img2_cols_V_out_full_n == 1'b0) | (img2_rows_V_out_full_n == 1'b0) | (img0_cols_V_out_full_n == 1'b0) | (img0_rows_V_out_full_n == 1'b0) | (min_out_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
img3_cols_V_out_write = 1'b1;
end else begin
img3_cols_V_out_write = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_CS_fsm_state1)) begin
img3_rows_V_out_blk_n = img3_rows_V_out_full_n;
end else begin
img3_rows_V_out_blk_n = 1'b1;
end
end
always @ (*) begin
if ((~((max_out_full_n == 1'b0) | (tmp_3_cast_out_out_full_n == 1'b0) | (p_rows_assign_cast_out_out_full_n == 1'b0) | (p_cols_assign_cast_out_out_full_n == 1'b0) | (real_start == 1'b0) | (img3_cols_V_out_full_n == 1'b0) | (img3_rows_V_out_full_n == 1'b0) | (img2_cols_V_out_full_n == 1'b0) | (img2_rows_V_out_full_n == 1'b0) | (img0_cols_V_out_full_n == 1'b0) | (img0_rows_V_out_full_n == 1'b0) | (min_out_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
img3_rows_V_out_write = 1'b1;
end else begin
img3_rows_V_out_write = 1'b0;
end
end
always @ (*) begin
if ((~((max_out_full_n == 1'b0) | (tmp_3_cast_out_out_full_n == 1'b0) | (p_rows_assign_cast_out_out_full_n == 1'b0) | (p_cols_assign_cast_out_out_full_n == 1'b0) | (real_start == 1'b0) | (img3_cols_V_out_full_n == 1'b0) | (img3_rows_V_out_full_n == 1'b0) | (img2_cols_V_out_full_n == 1'b0) | (img2_rows_V_out_full_n == 1'b0) | (img0_cols_V_out_full_n == 1'b0) | (img0_rows_V_out_full_n == 1'b0) | (min_out_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
internal_ap_ready = 1'b1;
end else begin
internal_ap_ready = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_CS_fsm_state1)) begin
max_out_blk_n = max_out_full_n;
end else begin
max_out_blk_n = 1'b1;
end
end
always @ (*) begin
if ((~((max_out_full_n == 1'b0) | (tmp_3_cast_out_out_full_n == 1'b0) | (p_rows_assign_cast_out_out_full_n == 1'b0) | (p_cols_assign_cast_out_out_full_n == 1'b0) | (real_start == 1'b0) | (img3_cols_V_out_full_n == 1'b0) | (img3_rows_V_out_full_n == 1'b0) | (img2_cols_V_out_full_n == 1'b0) | (img2_rows_V_out_full_n == 1'b0) | (img0_cols_V_out_full_n == 1'b0) | (img0_rows_V_out_full_n == 1'b0) | (min_out_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
max_out_write = 1'b1;
end else begin
max_out_write = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_CS_fsm_state1)) begin
min_out_blk_n = min_out_full_n;
end else begin
min_out_blk_n = 1'b1;
end
end
always @ (*) begin
if ((~((max_out_full_n == 1'b0) | (tmp_3_cast_out_out_full_n == 1'b0) | (p_rows_assign_cast_out_out_full_n == 1'b0) | (p_cols_assign_cast_out_out_full_n == 1'b0) | (real_start == 1'b0) | (img3_cols_V_out_full_n == 1'b0) | (img3_rows_V_out_full_n == 1'b0) | (img2_cols_V_out_full_n == 1'b0) | (img2_rows_V_out_full_n == 1'b0) | (img0_cols_V_out_full_n == 1'b0) | (img0_rows_V_out_full_n == 1'b0) | (min_out_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
min_out_write = 1'b1;
end else begin
min_out_write = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_CS_fsm_state1)) begin
p_cols_assign_cast_out_out_blk_n = p_cols_assign_cast_out_out_full_n;
end else begin
p_cols_assign_cast_out_out_blk_n = 1'b1;
end
end
always @ (*) begin
if ((~((max_out_full_n == 1'b0) | (tmp_3_cast_out_out_full_n == 1'b0) | (p_rows_assign_cast_out_out_full_n == 1'b0) | (p_cols_assign_cast_out_out_full_n == 1'b0) | (real_start == 1'b0) | (img3_cols_V_out_full_n == 1'b0) | (img3_rows_V_out_full_n == 1'b0) | (img2_cols_V_out_full_n == 1'b0) | (img2_rows_V_out_full_n == 1'b0) | (img0_cols_V_out_full_n == 1'b0) | (img0_rows_V_out_full_n == 1'b0) | (min_out_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
p_cols_assign_cast_out_out_write = 1'b1;
end else begin
p_cols_assign_cast_out_out_write = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_CS_fsm_state1)) begin
p_rows_assign_cast_out_out_blk_n = p_rows_assign_cast_out_out_full_n;
end else begin
p_rows_assign_cast_out_out_blk_n = 1'b1;
end
end
always @ (*) begin
if ((~((max_out_full_n == 1'b0) | (tmp_3_cast_out_out_full_n == 1'b0) | (p_rows_assign_cast_out_out_full_n == 1'b0) | (p_cols_assign_cast_out_out_full_n == 1'b0) | (real_start == 1'b0) | (img3_cols_V_out_full_n == 1'b0) | (img3_rows_V_out_full_n == 1'b0) | (img2_cols_V_out_full_n == 1'b0) | (img2_rows_V_out_full_n == 1'b0) | (img0_cols_V_out_full_n == 1'b0) | (img0_rows_V_out_full_n == 1'b0) | (min_out_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
p_rows_assign_cast_out_out_write = 1'b1;
end else begin
p_rows_assign_cast_out_out_write = 1'b0;
end
end
always @ (*) begin
if (((start_full_n == 1'b0) & (start_once_reg == 1'b0))) begin
real_start = 1'b0;
end else begin
real_start = ap_start;
end
end
always @ (*) begin
if (((start_once_reg == 1'b0) & (real_start == 1'b1))) begin
start_write = 1'b1;
end else begin
start_write = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_CS_fsm_state1)) begin
tmp_3_cast_out_out_blk_n = tmp_3_cast_out_out_full_n;
end else begin
tmp_3_cast_out_out_blk_n = 1'b1;
end
end
always @ (*) begin
if ((~((max_out_full_n == 1'b0) | (tmp_3_cast_out_out_full_n == 1'b0) | (p_rows_assign_cast_out_out_full_n == 1'b0) | (p_cols_assign_cast_out_out_full_n == 1'b0) | (real_start == 1'b0) | (img3_cols_V_out_full_n == 1'b0) | (img3_rows_V_out_full_n == 1'b0) | (img2_cols_V_out_full_n == 1'b0) | (img2_rows_V_out_full_n == 1'b0) | (img0_cols_V_out_full_n == 1'b0) | (img0_rows_V_out_full_n == 1'b0) | (min_out_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
tmp_3_cast_out_out_write = 1'b1;
end else begin
tmp_3_cast_out_out_write = 1'b0;
end
end
always @ (*) begin
case (ap_CS_fsm)
ap_ST_fsm_state1 : begin
ap_NS_fsm = ap_ST_fsm_state1;
end
default : begin
ap_NS_fsm = 'bx;
end
endcase
end
assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0];
always @ (*) begin
ap_block_state1 = ((max_out_full_n == 1'b0) | (tmp_3_cast_out_out_full_n == 1'b0) | (p_rows_assign_cast_out_out_full_n == 1'b0) | (p_cols_assign_cast_out_out_full_n == 1'b0) | (real_start == 1'b0) | (img3_cols_V_out_full_n == 1'b0) | (img3_rows_V_out_full_n == 1'b0) | (img2_cols_V_out_full_n == 1'b0) | (img2_rows_V_out_full_n == 1'b0) | (img0_cols_V_out_full_n == 1'b0) | (img0_rows_V_out_full_n == 1'b0) | (min_out_full_n == 1'b0) | (ap_done_reg == 1'b1));
end
assign ap_ready = internal_ap_ready;
assign img0_cols_V_out_din = width;
assign img0_rows_V_out_din = height;
assign img2_cols_V_out_din = width;
assign img2_rows_V_out_din = height;
assign img3_cols_V_out_din = width;
assign img3_rows_V_out_din = height;
assign max_out_din = max;
assign min_out_din = min;
assign p_cols_assign_cast_out_out_din = width[11:0];
assign p_rows_assign_cast_out_out_din = height[11:0];
assign start_out = real_start;
assign tmp_3_cast_out_out_din = min;
endmodule |
module sky130_fd_sc_lp__a21oi (
//# {{data|Data Signals}}
input A1 ,
input A2 ,
input B1 ,
output Y ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule |
module
input e_tx_ack;
// Control bits inputs (none)
//############
//# Arbitrate & forward
//############
reg ready;
reg [102:0] fifo_data;
// priority-based ready signals
wire rr_ready = ~emrr_empty & ~emm_tx_wr_wait;
wire rq_ready = ~emrq_empty & ~emm_tx_rd_wait & ~rr_ready;
wire wr_ready = ~emwr_empty & ~emm_tx_wr_wait & ~rr_ready & ~rq_ready;
// FIFO read enables, when we're idle or done with the current datum
wire emrr_rd_en = rr_ready & (~ready | emtx_ack);
wire emrq_rd_en = rq_ready & (~ready | emtx_ack);
wire emwr_rd_en = wr_ready & (~ready | emtx_ack);
always @ (posedge clk) begin
if( reset ) begin
ready <= 1'b0;
fifo_data <= 'd0;
end else begin
if( emrr_rd_en ) begin
ready <= 1'b1;
fifo_data <= emrr_rd_data;
end else if( emrq_rd_en ) begin
ready <= 1'b1;
fifo_data <= emrq_rd_data;
end else if( emwr_rd_en ) begin
ready <= 1'b1;
fifo_data <= emwr_rd_data;
end else if( emtx_ack ) begin
ready <= 1'b0;
end
end // else: !if( reset )
end // always @ (posedge clock)
//#############################
//# Break-out the emesh signals
//#############################
assign e_tx_access = ready;
assign e_tx_write = fifo_data[102];
assign e_tx_datamode = fifo_data[101:100];
assign e_tx_ctrlmode = fifo_data[99:96];
assign e_tx_dstaddr = fifo_data[95:64];
assign e_tx_srcaddr = fifo_data[63:32];
assign e_tx_data = fifo_data[31:0];
endmodule |
module gcd_mem3 (
clk,
req_msg,
req_rdy,
req_val,
reset,
resp_msg,
resp_rdy,
resp_val,
mem_out0,
mem_out1,
mem_out2);
input clk;
input [31:0] req_msg;
output req_rdy;
input req_val;
input reset;
output [15:0] resp_msg;
input resp_rdy;
output resp_val;
output [6:0] mem_out0;
output [6:0] mem_out1;
output [6:0] mem_out2;
wire [6:0] data;
// mem0/rd_out -> r1* -> r2* -> r3* -> mem1/wd_in
DFF_X1 r10 (.D(mem_out0[0]),
.CK(clk),
.Q(l1[0]));
DFF_X1 r11 (.D(mem_out0[1]),
.CK(clk),
.Q(l1[1]));
DFF_X1 r12 (.D(mem_out0[2]),
.CK(clk),
.Q(l1[2]));
DFF_X1 r13 (.D(mem_out0[3]),
.CK(clk),
.Q(l1[3]));
DFF_X1 r14 (.D(mem_out0[4]),
.CK(clk),
.Q(l1[4]));
DFF_X1 r15 (.D(mem_out0[5]),
.CK(clk),
.Q(l1[5]));
DFF_X1 r16 (.D(mem_out0[6]),
.CK(clk),
.Q(l1[6]));
DFF_X1 r20 (.D(l1[0]),
.CK(clk),
.Q(l2[0]));
DFF_X1 r21 (.D(l1[1]),
.CK(clk),
.Q(l2[1]));
DFF_X1 r22 (.D(l1[2]),
.CK(clk),
.Q(l2[2]));
DFF_X1 r23 (.D(l1[3]),
.CK(clk),
.Q(l2[3]));
DFF_X1 r24 (.D(l1[4]),
.CK(clk),
.Q(l2[4]));
DFF_X1 r25 (.D(l1[5]),
.CK(clk),
.Q(l2[5]));
DFF_X1 r26 (.D(l1[6]),
.CK(clk),
.Q(l2[6]));
DFF_X1 r30 (.D(l2[0]),
.CK(clk),
.Q(l3[0]));
DFF_X1 r31 (.D(l2[1]),
.CK(clk),
.Q(l3[1]));
DFF_X1 r32 (.D(l2[2]),
.CK(clk),
.Q(l3[2]));
DFF_X1 r33 (.D(l2[3]),
.CK(clk),
.Q(l3[3]));
DFF_X1 r34 (.D(l2[4]),
.CK(clk),
.Q(l3[4]));
DFF_X1 r35 (.D(l2[5]),
.CK(clk),
.Q(l3[5]));
DFF_X1 r36 (.D(l2[6]),
.CK(clk),
.Q(l3[6]));
fakeram45_64x7 mem0 (.clk(clk),
.rd_out(mem_out0),
.we_in(_006_),
.ce_in(_007_),
.addr_in({ _008_,
_009_,
_010_,
_011_,
_012_,
_013_ }),
.wd_in({ _014_,
_015_,
_016_,
_017_,
_018_,
_019_,
_020_ }),
.w_mask_in({ _021_,
_076_,
_077_,
_078_,
_079_,
_080_,
_081_ }));
fakeram45_64x7 mem1 (.clk(clk),
.rd_out(mem_out1),
.we_in(_090_),
.ce_in(_091_),
.addr_in({ _092_,
_093_,
_094_,
_095_,
_096_,
_097_ }),
.wd_in(l3[6:0]),
.w_mask_in({ _105_,
_106_,
_107_,
_054_,
_055_,
_056_,
_003_ }));
fakeram45_64x7 mem2 (.clk(clk),
.rd_out(mem_out2),
.we_in(_012_),
.ce_in(_013_),
.addr_in({ _014_,
_015_,
_016_,
_017_,
_018_,
_019_ }),
.wd_in({ _020_,
_021_,
_076_,
_077_,
_078_,
_079_,
_080_ }),
.w_mask_in({ _081_,
_082_,
_083_,
_084_,
_085_,
_086_,
_087_ }));
endmodule |
module pcie_recv_fifo
(clk,
srst,
din,
wr_en,
rd_en,
dout,
full,
empty);
(* x_interface_info = "xilinx.com:signal:clock:1.0 core_clk CLK" *) input clk;
input srst;
(* x_interface_info = "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_DATA" *) input [127:0]din;
(* x_interface_info = "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_EN" *) input wr_en;
(* x_interface_info = "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_EN" *) input rd_en;
(* x_interface_info = "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_DATA" *) output [127:0]dout;
(* x_interface_info = "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE FULL" *) output full;
(* x_interface_info = "xilinx.com:interface:fifo_read:1.0 FIFO_READ EMPTY" *) output empty;
wire clk;
wire [127:0]din;
wire [127:0]dout;
wire empty;
wire full;
wire rd_en;
wire srst;
wire wr_en;
wire NLW_U0_almost_empty_UNCONNECTED;
wire NLW_U0_almost_full_UNCONNECTED;
wire NLW_U0_axi_ar_dbiterr_UNCONNECTED;
wire NLW_U0_axi_ar_overflow_UNCONNECTED;
wire NLW_U0_axi_ar_prog_empty_UNCONNECTED;
wire NLW_U0_axi_ar_prog_full_UNCONNECTED;
wire NLW_U0_axi_ar_sbiterr_UNCONNECTED;
wire NLW_U0_axi_ar_underflow_UNCONNECTED;
wire NLW_U0_axi_aw_dbiterr_UNCONNECTED;
wire NLW_U0_axi_aw_overflow_UNCONNECTED;
wire NLW_U0_axi_aw_prog_empty_UNCONNECTED;
wire NLW_U0_axi_aw_prog_full_UNCONNECTED;
wire NLW_U0_axi_aw_sbiterr_UNCONNECTED;
wire NLW_U0_axi_aw_underflow_UNCONNECTED;
wire NLW_U0_axi_b_dbiterr_UNCONNECTED;
wire NLW_U0_axi_b_overflow_UNCONNECTED;
wire NLW_U0_axi_b_prog_empty_UNCONNECTED;
wire NLW_U0_axi_b_prog_full_UNCONNECTED;
wire NLW_U0_axi_b_sbiterr_UNCONNECTED;
wire NLW_U0_axi_b_underflow_UNCONNECTED;
wire NLW_U0_axi_r_dbiterr_UNCONNECTED;
wire NLW_U0_axi_r_overflow_UNCONNECTED;
wire NLW_U0_axi_r_prog_empty_UNCONNECTED;
wire NLW_U0_axi_r_prog_full_UNCONNECTED;
wire NLW_U0_axi_r_sbiterr_UNCONNECTED;
wire NLW_U0_axi_r_underflow_UNCONNECTED;
wire NLW_U0_axi_w_dbiterr_UNCONNECTED;
wire NLW_U0_axi_w_overflow_UNCONNECTED;
wire NLW_U0_axi_w_prog_empty_UNCONNECTED;
wire NLW_U0_axi_w_prog_full_UNCONNECTED;
wire NLW_U0_axi_w_sbiterr_UNCONNECTED;
wire NLW_U0_axi_w_underflow_UNCONNECTED;
wire NLW_U0_axis_dbiterr_UNCONNECTED;
wire NLW_U0_axis_overflow_UNCONNECTED;
wire NLW_U0_axis_prog_empty_UNCONNECTED;
wire NLW_U0_axis_prog_full_UNCONNECTED;
wire NLW_U0_axis_sbiterr_UNCONNECTED;
wire NLW_U0_axis_underflow_UNCONNECTED;
wire NLW_U0_dbiterr_UNCONNECTED;
wire NLW_U0_m_axi_arvalid_UNCONNECTED;
wire NLW_U0_m_axi_awvalid_UNCONNECTED;
wire NLW_U0_m_axi_bready_UNCONNECTED;
wire NLW_U0_m_axi_rready_UNCONNECTED;
wire NLW_U0_m_axi_wlast_UNCONNECTED;
wire NLW_U0_m_axi_wvalid_UNCONNECTED;
wire NLW_U0_m_axis_tlast_UNCONNECTED;
wire NLW_U0_m_axis_tvalid_UNCONNECTED;
wire NLW_U0_overflow_UNCONNECTED;
wire NLW_U0_prog_empty_UNCONNECTED;
wire NLW_U0_prog_full_UNCONNECTED;
wire NLW_U0_rd_rst_busy_UNCONNECTED;
wire NLW_U0_s_axi_arready_UNCONNECTED;
wire NLW_U0_s_axi_awready_UNCONNECTED;
wire NLW_U0_s_axi_bvalid_UNCONNECTED;
wire NLW_U0_s_axi_rlast_UNCONNECTED;
wire NLW_U0_s_axi_rvalid_UNCONNECTED;
wire NLW_U0_s_axi_wready_UNCONNECTED;
wire NLW_U0_s_axis_tready_UNCONNECTED;
wire NLW_U0_sbiterr_UNCONNECTED;
wire NLW_U0_underflow_UNCONNECTED;
wire NLW_U0_valid_UNCONNECTED;
wire NLW_U0_wr_ack_UNCONNECTED;
wire NLW_U0_wr_rst_busy_UNCONNECTED;
wire [4:0]NLW_U0_axi_ar_data_count_UNCONNECTED;
wire [4:0]NLW_U0_axi_ar_rd_data_count_UNCONNECTED;
wire [4:0]NLW_U0_axi_ar_wr_data_count_UNCONNECTED;
wire [4:0]NLW_U0_axi_aw_data_count_UNCONNECTED;
wire [4:0]NLW_U0_axi_aw_rd_data_count_UNCONNECTED;
wire [4:0]NLW_U0_axi_aw_wr_data_count_UNCONNECTED;
wire [4:0]NLW_U0_axi_b_data_count_UNCONNECTED;
wire [4:0]NLW_U0_axi_b_rd_data_count_UNCONNECTED;
wire [4:0]NLW_U0_axi_b_wr_data_count_UNCONNECTED;
wire [10:0]NLW_U0_axi_r_data_count_UNCONNECTED;
wire [10:0]NLW_U0_axi_r_rd_data_count_UNCONNECTED;
wire [10:0]NLW_U0_axi_r_wr_data_count_UNCONNECTED;
wire [10:0]NLW_U0_axi_w_data_count_UNCONNECTED;
wire [10:0]NLW_U0_axi_w_rd_data_count_UNCONNECTED;
wire [10:0]NLW_U0_axi_w_wr_data_count_UNCONNECTED;
wire [10:0]NLW_U0_axis_data_count_UNCONNECTED;
wire [10:0]NLW_U0_axis_rd_data_count_UNCONNECTED;
wire [10:0]NLW_U0_axis_wr_data_count_UNCONNECTED;
wire [9:0]NLW_U0_data_count_UNCONNECTED;
wire [31:0]NLW_U0_m_axi_araddr_UNCONNECTED;
wire [1:0]NLW_U0_m_axi_arburst_UNCONNECTED;
wire [3:0]NLW_U0_m_axi_arcache_UNCONNECTED;
wire [0:0]NLW_U0_m_axi_arid_UNCONNECTED;
wire [7:0]NLW_U0_m_axi_arlen_UNCONNECTED;
wire [0:0]NLW_U0_m_axi_arlock_UNCONNECTED;
wire [2:0]NLW_U0_m_axi_arprot_UNCONNECTED;
wire [3:0]NLW_U0_m_axi_arqos_UNCONNECTED;
wire [3:0]NLW_U0_m_axi_arregion_UNCONNECTED;
wire [2:0]NLW_U0_m_axi_arsize_UNCONNECTED;
wire [0:0]NLW_U0_m_axi_aruser_UNCONNECTED;
wire [31:0]NLW_U0_m_axi_awaddr_UNCONNECTED;
wire [1:0]NLW_U0_m_axi_awburst_UNCONNECTED;
wire [3:0]NLW_U0_m_axi_awcache_UNCONNECTED;
wire [0:0]NLW_U0_m_axi_awid_UNCONNECTED;
wire [7:0]NLW_U0_m_axi_awlen_UNCONNECTED;
wire [0:0]NLW_U0_m_axi_awlock_UNCONNECTED;
wire [2:0]NLW_U0_m_axi_awprot_UNCONNECTED;
wire [3:0]NLW_U0_m_axi_awqos_UNCONNECTED;
wire [3:0]NLW_U0_m_axi_awregion_UNCONNECTED;
wire [2:0]NLW_U0_m_axi_awsize_UNCONNECTED;
wire [0:0]NLW_U0_m_axi_awuser_UNCONNECTED;
wire [63:0]NLW_U0_m_axi_wdata_UNCONNECTED;
wire [0:0]NLW_U0_m_axi_wid_UNCONNECTED;
wire [7:0]NLW_U0_m_axi_wstrb_UNCONNECTED;
wire [0:0]NLW_U0_m_axi_wuser_UNCONNECTED;
wire [7:0]NLW_U0_m_axis_tdata_UNCONNECTED;
wire [0:0]NLW_U0_m_axis_tdest_UNCONNECTED;
wire [0:0]NLW_U0_m_axis_tid_UNCONNECTED;
wire [0:0]NLW_U0_m_axis_tkeep_UNCONNECTED;
wire [0:0]NLW_U0_m_axis_tstrb_UNCONNECTED;
wire [3:0]NLW_U0_m_axis_tuser_UNCONNECTED;
wire [9:0]NLW_U0_rd_data_count_UNCONNECTED;
wire [0:0]NLW_U0_s_axi_bid_UNCONNECTED;
wire [1:0]NLW_U0_s_axi_bresp_UNCONNECTED;
wire [0:0]NLW_U0_s_axi_buser_UNCONNECTED;
wire [63:0]NLW_U0_s_axi_rdata_UNCONNECTED;
wire [0:0]NLW_U0_s_axi_rid_UNCONNECTED;
wire [1:0]NLW_U0_s_axi_rresp_UNCONNECTED;
wire [0:0]NLW_U0_s_axi_ruser_UNCONNECTED;
wire [9:0]NLW_U0_wr_data_count_UNCONNECTED;
(* C_ADD_NGC_CONSTRAINT = "0" *)
(* C_APPLICATION_TYPE_AXIS = "0" *)
(* C_APPLICATION_TYPE_RACH = "0" *)
(* C_APPLICATION_TYPE_RDCH = "0" *)
(* C_APPLICATION_TYPE_WACH = "0" *)
(* C_APPLICATION_TYPE_WDCH = "0" *)
(* C_APPLICATION_TYPE_WRCH = "0" *)
(* C_AXIS_TDATA_WIDTH = "8" *)
(* C_AXIS_TDEST_WIDTH = "1" *)
(* C_AXIS_TID_WIDTH = "1" *)
(* C_AXIS_TKEEP_WIDTH = "1" *)
(* C_AXIS_TSTRB_WIDTH = "1" *)
(* C_AXIS_TUSER_WIDTH = "4" *)
(* C_AXIS_TYPE = "0" *)
(* C_AXI_ADDR_WIDTH = "32" *)
(* C_AXI_ARUSER_WIDTH = "1" *)
(* C_AXI_AWUSER_WIDTH = "1" *)
(* C_AXI_BUSER_WIDTH = "1" *)
(* C_AXI_DATA_WIDTH = "64" *)
(* C_AXI_ID_WIDTH = "1" *)
(* C_AXI_LEN_WIDTH = "8" *)
(* C_AXI_LOCK_WIDTH = "1" *)
(* C_AXI_RUSER_WIDTH = "1" *)
(* C_AXI_TYPE = "1" *)
(* C_AXI_WUSER_WIDTH = "1" *)
(* C_COMMON_CLOCK = "1" *)
(* C_COUNT_TYPE = "0" *)
(* C_DATA_COUNT_WIDTH = "10" *)
(* C_DEFAULT_VALUE = "BlankString" *)
(* C_DIN_WIDTH = "128" *)
(* C_DIN_WIDTH_AXIS = "1" *)
(* C_DIN_WIDTH_RACH = "32" *)
(* C_DIN_WIDTH_RDCH = "64" *)
(* C_DIN_WIDTH_WACH = "32" *)
(* C_DIN_WIDTH_WDCH = "64" *)
(* C_DIN_WIDTH_WRCH = "2" *)
(* C_DOUT_RST_VAL = "0" *)
(* C_DOUT_WIDTH = "128" *)
(* C_ENABLE_RLOCS = "0" *)
(* C_ENABLE_RST_SYNC = "1" *)
(* C_EN_SAFETY_CKT = "0" *)
(* C_ERROR_INJECTION_TYPE = "0" *)
(* C_ERROR_INJECTION_TYPE_AXIS = "0" *)
(* C_ERROR_INJECTION_TYPE_RACH = "0" *)
(* C_ERROR_INJECTION_TYPE_RDCH = "0" *)
(* C_ERROR_INJECTION_TYPE_WACH = "0" *)
(* C_ERROR_INJECTION_TYPE_WDCH = "0" *)
(* C_ERROR_INJECTION_TYPE_WRCH = "0" *)
(* C_FAMILY = "virtex7" *)
(* C_FULL_FLAGS_RST_VAL = "0" *)
(* C_HAS_ALMOST_EMPTY = "0" *)
(* C_HAS_ALMOST_FULL = "0" *)
(* C_HAS_AXIS_TDATA = "1" *)
(* C_HAS_AXIS_TDEST = "0" *)
(* C_HAS_AXIS_TID = "0" *)
(* C_HAS_AXIS_TKEEP = "0" *)
(* C_HAS_AXIS_TLAST = "0" *)
(* C_HAS_AXIS_TREADY = "1" *)
(* C_HAS_AXIS_TSTRB = "0" *)
(* C_HAS_AXIS_TUSER = "1" *)
(* C_HAS_AXI_ARUSER = "0" *)
(* C_HAS_AXI_AWUSER = "0" *)
(* C_HAS_AXI_BUSER = "0" *)
(* C_HAS_AXI_ID = "0" *)
(* C_HAS_AXI_RD_CHANNEL = "1" *)
(* C_HAS_AXI_RUSER = "0" *)
(* C_HAS_AXI_WR_CHANNEL = "1" *)
(* C_HAS_AXI_WUSER = "0" *)
(* C_HAS_BACKUP = "0" *)
(* C_HAS_DATA_COUNT = "0" *)
(* C_HAS_DATA_COUNTS_AXIS = "0" *)
(* C_HAS_DATA_COUNTS_RACH = "0" *)
(* C_HAS_DATA_COUNTS_RDCH = "0" *)
(* C_HAS_DATA_COUNTS_WACH = "0" *)
(* C_HAS_DATA_COUNTS_WDCH = "0" *)
(* C_HAS_DATA_COUNTS_WRCH = "0" *)
(* C_HAS_INT_CLK = "0" *)
(* C_HAS_MASTER_CE = "0" *)
(* C_HAS_MEMINIT_FILE = "0" *)
(* C_HAS_OVERFLOW = "0" *)
(* C_HAS_PROG_FLAGS_AXIS = "0" *)
(* C_HAS_PROG_FLAGS_RACH = "0" *)
(* C_HAS_PROG_FLAGS_RDCH = "0" *)
(* C_HAS_PROG_FLAGS_WACH = "0" *)
(* C_HAS_PROG_FLAGS_WDCH = "0" *)
(* C_HAS_PROG_FLAGS_WRCH = "0" *)
(* C_HAS_RD_DATA_COUNT = "0" *)
(* C_HAS_RD_RST = "0" *)
(* C_HAS_RST = "0" *)
(* C_HAS_SLAVE_CE = "0" *)
(* C_HAS_SRST = "1" *)
(* C_HAS_UNDERFLOW = "0" *)
(* C_HAS_VALID = "0" *)
(* C_HAS_WR_ACK = "0" *)
(* C_HAS_WR_DATA_COUNT = "0" *)
(* C_HAS_WR_RST = "0" *)
(* C_IMPLEMENTATION_TYPE = "0" *)
(* C_IMPLEMENTATION_TYPE_AXIS = "1" *)
(* C_IMPLEMENTATION_TYPE_RACH = "1" *)
(* C_IMPLEMENTATION_TYPE_RDCH = "1" *)
(* C_IMPLEMENTATION_TYPE_WACH = "1" *)
(* C_IMPLEMENTATION_TYPE_WDCH = "1" *)
(* C_IMPLEMENTATION_TYPE_WRCH = "1" *)
(* C_INIT_WR_PNTR_VAL = "0" *)
(* C_INTERFACE_TYPE = "0" *)
(* C_MEMORY_TYPE = "1" *)
(* C_MIF_FILE_NAME = "BlankString" *)
(* C_MSGON_VAL = "1" *)
(* C_OPTIMIZATION_MODE = "0" *)
(* C_OVERFLOW_LOW = "0" *)
(* C_POWER_SAVING_MODE = "0" *)
(* C_PRELOAD_LATENCY = "0" *)
(* C_PRELOAD_REGS = "1" *)
(* C_PRIM_FIFO_TYPE = "512x72" *)
(* C_PRIM_FIFO_TYPE_AXIS = "1kx18" *)
(* C_PRIM_FIFO_TYPE_RACH = "512x36" *)
(* C_PRIM_FIFO_TYPE_RDCH = "1kx36" *)
(* C_PRIM_FIFO_TYPE_WACH = "512x36" *)
(* C_PRIM_FIFO_TYPE_WDCH = "1kx36" *)
(* C_PRIM_FIFO_TYPE_WRCH = "512x36" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL = "4" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS = "1022" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH = "1022" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH = "1022" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH = "1022" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH = "1022" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH = "1022" *)
(* C_PROG_EMPTY_THRESH_NEGATE_VAL = "5" *)
(* C_PROG_EMPTY_TYPE = "0" *)
(* C_PROG_EMPTY_TYPE_AXIS = "0" *)
(* C_PROG_EMPTY_TYPE_RACH = "0" *)
(* C_PROG_EMPTY_TYPE_RDCH = "0" *)
(* C_PROG_EMPTY_TYPE_WACH = "0" *)
(* C_PROG_EMPTY_TYPE_WDCH = "0" *)
(* C_PROG_EMPTY_TYPE_WRCH = "0" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL = "511" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL_AXIS = "1023" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL_RACH = "1023" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL_RDCH = "1023" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL_WACH = "1023" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL_WDCH = "1023" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL_WRCH = "1023" *)
(* C_PROG_FULL_THRESH_NEGATE_VAL = "510" *)
(* C_PROG_FULL_TYPE = "0" *)
(* C_PROG_FULL_TYPE_AXIS = "0" *)
(* C_PROG_FULL_TYPE_RACH = "0" *)
(* C_PROG_FULL_TYPE_RDCH = "0" *)
(* C_PROG_FULL_TYPE_WACH = "0" *)
(* C_PROG_FULL_TYPE_WDCH = "0" *)
(* C_PROG_FULL_TYPE_WRCH = "0" *)
(* C_RACH_TYPE = "0" *)
(* C_RDCH_TYPE = "0" *)
(* C_RD_DATA_COUNT_WIDTH = "10" *)
(* C_RD_DEPTH = "512" *)
(* C_RD_FREQ = "1" *)
(* C_RD_PNTR_WIDTH = "9" *)
(* C_REG_SLICE_MODE_AXIS = "0" *)
(* C_REG_SLICE_MODE_RACH = "0" *)
(* C_REG_SLICE_MODE_RDCH = "0" *)
(* C_REG_SLICE_MODE_WACH = "0" *)
(* C_REG_SLICE_MODE_WDCH = "0" *)
(* C_REG_SLICE_MODE_WRCH = "0" *)
(* C_SYNCHRONIZER_STAGE = "2" *)
(* C_UNDERFLOW_LOW = "0" *)
(* C_USE_COMMON_OVERFLOW = "0" *)
(* C_USE_COMMON_UNDERFLOW = "0" *)
(* C_USE_DEFAULT_SETTINGS = "0" *)
(* C_USE_DOUT_RST = "1" *)
(* C_USE_ECC = "0" *)
(* C_USE_ECC_AXIS = "0" *)
(* C_USE_ECC_RACH = "0" *)
(* C_USE_ECC_RDCH = "0" *)
(* C_USE_ECC_WACH = "0" *)
(* C_USE_ECC_WDCH = "0" *)
(* C_USE_ECC_WRCH = "0" *)
(* C_USE_EMBEDDED_REG = "0" *)
(* C_USE_FIFO16_FLAGS = "0" *)
(* C_USE_FWFT_DATA_COUNT = "1" *)
(* C_USE_PIPELINE_REG = "0" *)
(* C_VALID_LOW = "0" *)
(* C_WACH_TYPE = "0" *)
(* C_WDCH_TYPE = "0" *)
(* C_WRCH_TYPE = "0" *)
(* C_WR_ACK_LOW = "0" *)
(* C_WR_DATA_COUNT_WIDTH = "10" *)
(* C_WR_DEPTH = "512" *)
(* C_WR_DEPTH_AXIS = "1024" *)
(* C_WR_DEPTH_RACH = "16" *)
(* C_WR_DEPTH_RDCH = "1024" *)
(* C_WR_DEPTH_WACH = "16" *)
(* C_WR_DEPTH_WDCH = "1024" *)
(* C_WR_DEPTH_WRCH = "16" *)
(* C_WR_FREQ = "1" *)
(* C_WR_PNTR_WIDTH = "9" *)
(* C_WR_PNTR_WIDTH_AXIS = "10" *)
(* C_WR_PNTR_WIDTH_RACH = "4" *)
(* C_WR_PNTR_WIDTH_RDCH = "10" *)
(* C_WR_PNTR_WIDTH_WACH = "4" *)
(* C_WR_PNTR_WIDTH_WDCH = "10" *)
(* C_WR_PNTR_WIDTH_WRCH = "4" *)
(* C_WR_RESPONSE_LATENCY = "1" *)
pcie_recv_fifo_fifo_generator_v13_0_1 U0
(.almost_empty(NLW_U0_almost_empty_UNCONNECTED),
.almost_full(NLW_U0_almost_full_UNCONNECTED),
.axi_ar_data_count(NLW_U0_axi_ar_data_count_UNCONNECTED[4:0]),
.axi_ar_dbiterr(NLW_U0_axi_ar_dbiterr_UNCONNECTED),
.axi_ar_injectdbiterr(1'b0),
.axi_ar_injectsbiterr(1'b0),
.axi_ar_overflow(NLW_U0_axi_ar_overflow_UNCONNECTED),
.axi_ar_prog_empty(NLW_U0_axi_ar_prog_empty_UNCONNECTED),
.axi_ar_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0}),
.axi_ar_prog_full(NLW_U0_axi_ar_prog_full_UNCONNECTED),
.axi_ar_prog_full_thresh({1'b0,1'b0,1'b0,1'b0}),
.axi_ar_rd_data_count(NLW_U0_axi_ar_rd_data_count_UNCONNECTED[4:0]),
.axi_ar_sbiterr(NLW_U0_axi_ar_sbiterr_UNCONNECTED),
.axi_ar_underflow(NLW_U0_axi_ar_underflow_UNCONNECTED),
.axi_ar_wr_data_count(NLW_U0_axi_ar_wr_data_count_UNCONNECTED[4:0]),
.axi_aw_data_count(NLW_U0_axi_aw_data_count_UNCONNECTED[4:0]),
.axi_aw_dbiterr(NLW_U0_axi_aw_dbiterr_UNCONNECTED),
.axi_aw_injectdbiterr(1'b0),
.axi_aw_injectsbiterr(1'b0),
.axi_aw_overflow(NLW_U0_axi_aw_overflow_UNCONNECTED),
.axi_aw_prog_empty(NLW_U0_axi_aw_prog_empty_UNCONNECTED),
.axi_aw_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0}),
.axi_aw_prog_full(NLW_U0_axi_aw_prog_full_UNCONNECTED),
.axi_aw_prog_full_thresh({1'b0,1'b0,1'b0,1'b0}),
.axi_aw_rd_data_count(NLW_U0_axi_aw_rd_data_count_UNCONNECTED[4:0]),
.axi_aw_sbiterr(NLW_U0_axi_aw_sbiterr_UNCONNECTED),
.axi_aw_underflow(NLW_U0_axi_aw_underflow_UNCONNECTED),
.axi_aw_wr_data_count(NLW_U0_axi_aw_wr_data_count_UNCONNECTED[4:0]),
.axi_b_data_count(NLW_U0_axi_b_data_count_UNCONNECTED[4:0]),
.axi_b_dbiterr(NLW_U0_axi_b_dbiterr_UNCONNECTED),
.axi_b_injectdbiterr(1'b0),
.axi_b_injectsbiterr(1'b0),
.axi_b_overflow(NLW_U0_axi_b_overflow_UNCONNECTED),
.axi_b_prog_empty(NLW_U0_axi_b_prog_empty_UNCONNECTED),
.axi_b_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0}),
.axi_b_prog_full(NLW_U0_axi_b_prog_full_UNCONNECTED),
.axi_b_prog_full_thresh({1'b0,1'b0,1'b0,1'b0}),
.axi_b_rd_data_count(NLW_U0_axi_b_rd_data_count_UNCONNECTED[4:0]),
.axi_b_sbiterr(NLW_U0_axi_b_sbiterr_UNCONNECTED),
.axi_b_underflow(NLW_U0_axi_b_underflow_UNCONNECTED),
.axi_b_wr_data_count(NLW_U0_axi_b_wr_data_count_UNCONNECTED[4:0]),
.axi_r_data_count(NLW_U0_axi_r_data_count_UNCONNECTED[10:0]),
.axi_r_dbiterr(NLW_U0_axi_r_dbiterr_UNCONNECTED),
.axi_r_injectdbiterr(1'b0),
.axi_r_injectsbiterr(1'b0),
.axi_r_overflow(NLW_U0_axi_r_overflow_UNCONNECTED),
.axi_r_prog_empty(NLW_U0_axi_r_prog_empty_UNCONNECTED),
.axi_r_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.axi_r_prog_full(NLW_U0_axi_r_prog_full_UNCONNECTED),
.axi_r_prog_full_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.axi_r_rd_data_count(NLW_U0_axi_r_rd_data_count_UNCONNECTED[10:0]),
.axi_r_sbiterr(NLW_U0_axi_r_sbiterr_UNCONNECTED),
.axi_r_underflow(NLW_U0_axi_r_underflow_UNCONNECTED),
.axi_r_wr_data_count(NLW_U0_axi_r_wr_data_count_UNCONNECTED[10:0]),
.axi_w_data_count(NLW_U0_axi_w_data_count_UNCONNECTED[10:0]),
.axi_w_dbiterr(NLW_U0_axi_w_dbiterr_UNCONNECTED),
.axi_w_injectdbiterr(1'b0),
.axi_w_injectsbiterr(1'b0),
.axi_w_overflow(NLW_U0_axi_w_overflow_UNCONNECTED),
.axi_w_prog_empty(NLW_U0_axi_w_prog_empty_UNCONNECTED),
.axi_w_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.axi_w_prog_full(NLW_U0_axi_w_prog_full_UNCONNECTED),
.axi_w_prog_full_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.axi_w_rd_data_count(NLW_U0_axi_w_rd_data_count_UNCONNECTED[10:0]),
.axi_w_sbiterr(NLW_U0_axi_w_sbiterr_UNCONNECTED),
.axi_w_underflow(NLW_U0_axi_w_underflow_UNCONNECTED),
.axi_w_wr_data_count(NLW_U0_axi_w_wr_data_count_UNCONNECTED[10:0]),
.axis_data_count(NLW_U0_axis_data_count_UNCONNECTED[10:0]),
.axis_dbiterr(NLW_U0_axis_dbiterr_UNCONNECTED),
.axis_injectdbiterr(1'b0),
.axis_injectsbiterr(1'b0),
.axis_overflow(NLW_U0_axis_overflow_UNCONNECTED),
.axis_prog_empty(NLW_U0_axis_prog_empty_UNCONNECTED),
.axis_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.axis_prog_full(NLW_U0_axis_prog_full_UNCONNECTED),
.axis_prog_full_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.axis_rd_data_count(NLW_U0_axis_rd_data_count_UNCONNECTED[10:0]),
.axis_sbiterr(NLW_U0_axis_sbiterr_UNCONNECTED),
.axis_underflow(NLW_U0_axis_underflow_UNCONNECTED),
.axis_wr_data_count(NLW_U0_axis_wr_data_count_UNCONNECTED[10:0]),
.backup(1'b0),
.backup_marker(1'b0),
.clk(clk),
.data_count(NLW_U0_data_count_UNCONNECTED[9:0]),
.dbiterr(NLW_U0_dbiterr_UNCONNECTED),
.din(din),
.dout(dout),
.empty(empty),
.full(full),
.injectdbiterr(1'b0),
.injectsbiterr(1'b0),
.int_clk(1'b0),
.m_aclk(1'b0),
.m_aclk_en(1'b0),
.m_axi_araddr(NLW_U0_m_axi_araddr_UNCONNECTED[31:0]),
.m_axi_arburst(NLW_U0_m_axi_arburst_UNCONNECTED[1:0]),
.m_axi_arcache(NLW_U0_m_axi_arcache_UNCONNECTED[3:0]),
.m_axi_arid(NLW_U0_m_axi_arid_UNCONNECTED[0]),
.m_axi_arlen(NLW_U0_m_axi_arlen_UNCONNECTED[7:0]),
.m_axi_arlock(NLW_U0_m_axi_arlock_UNCONNECTED[0]),
.m_axi_arprot(NLW_U0_m_axi_arprot_UNCONNECTED[2:0]),
.m_axi_arqos(NLW_U0_m_axi_arqos_UNCONNECTED[3:0]),
.m_axi_arready(1'b0),
.m_axi_arregion(NLW_U0_m_axi_arregion_UNCONNECTED[3:0]),
.m_axi_arsize(NLW_U0_m_axi_arsize_UNCONNECTED[2:0]),
.m_axi_aruser(NLW_U0_m_axi_aruser_UNCONNECTED[0]),
.m_axi_arvalid(NLW_U0_m_axi_arvalid_UNCONNECTED),
.m_axi_awaddr(NLW_U0_m_axi_awaddr_UNCONNECTED[31:0]),
.m_axi_awburst(NLW_U0_m_axi_awburst_UNCONNECTED[1:0]),
.m_axi_awcache(NLW_U0_m_axi_awcache_UNCONNECTED[3:0]),
.m_axi_awid(NLW_U0_m_axi_awid_UNCONNECTED[0]),
.m_axi_awlen(NLW_U0_m_axi_awlen_UNCONNECTED[7:0]),
.m_axi_awlock(NLW_U0_m_axi_awlock_UNCONNECTED[0]),
.m_axi_awprot(NLW_U0_m_axi_awprot_UNCONNECTED[2:0]),
.m_axi_awqos(NLW_U0_m_axi_awqos_UNCONNECTED[3:0]),
.m_axi_awready(1'b0),
.m_axi_awregion(NLW_U0_m_axi_awregion_UNCONNECTED[3:0]),
.m_axi_awsize(NLW_U0_m_axi_awsize_UNCONNECTED[2:0]),
.m_axi_awuser(NLW_U0_m_axi_awuser_UNCONNECTED[0]),
.m_axi_awvalid(NLW_U0_m_axi_awvalid_UNCONNECTED),
.m_axi_bid(1'b0),
.m_axi_bready(NLW_U0_m_axi_bready_UNCONNECTED),
.m_axi_bresp({1'b0,1'b0}),
.m_axi_buser(1'b0),
.m_axi_bvalid(1'b0),
.m_axi_rdata({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.m_axi_rid(1'b0),
.m_axi_rlast(1'b0),
.m_axi_rready(NLW_U0_m_axi_rready_UNCONNECTED),
.m_axi_rresp({1'b0,1'b0}),
.m_axi_ruser(1'b0),
.m_axi_rvalid(1'b0),
.m_axi_wdata(NLW_U0_m_axi_wdata_UNCONNECTED[63:0]),
.m_axi_wid(NLW_U0_m_axi_wid_UNCONNECTED[0]),
.m_axi_wlast(NLW_U0_m_axi_wlast_UNCONNECTED),
.m_axi_wready(1'b0),
.m_axi_wstrb(NLW_U0_m_axi_wstrb_UNCONNECTED[7:0]),
.m_axi_wuser(NLW_U0_m_axi_wuser_UNCONNECTED[0]),
.m_axi_wvalid(NLW_U0_m_axi_wvalid_UNCONNECTED),
.m_axis_tdata(NLW_U0_m_axis_tdata_UNCONNECTED[7:0]),
.m_axis_tdest(NLW_U0_m_axis_tdest_UNCONNECTED[0]),
.m_axis_tid(NLW_U0_m_axis_tid_UNCONNECTED[0]),
.m_axis_tkeep(NLW_U0_m_axis_tkeep_UNCONNECTED[0]),
.m_axis_tlast(NLW_U0_m_axis_tlast_UNCONNECTED),
.m_axis_tready(1'b0),
.m_axis_tstrb(NLW_U0_m_axis_tstrb_UNCONNECTED[0]),
.m_axis_tuser(NLW_U0_m_axis_tuser_UNCONNECTED[3:0]),
.m_axis_tvalid(NLW_U0_m_axis_tvalid_UNCONNECTED),
.overflow(NLW_U0_overflow_UNCONNECTED),
.prog_empty(NLW_U0_prog_empty_UNCONNECTED),
.prog_empty_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.prog_empty_thresh_assert({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.prog_empty_thresh_negate({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.prog_full(NLW_U0_prog_full_UNCONNECTED),
.prog_full_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.prog_full_thresh_assert({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.prog_full_thresh_negate({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.rd_clk(1'b0),
.rd_data_count(NLW_U0_rd_data_count_UNCONNECTED[9:0]),
.rd_en(rd_en),
.rd_rst(1'b0),
.rd_rst_busy(NLW_U0_rd_rst_busy_UNCONNECTED),
.rst(1'b0),
.s_aclk(1'b0),
.s_aclk_en(1'b0),
.s_aresetn(1'b0),
.s_axi_araddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_arburst({1'b0,1'b0}),
.s_axi_arcache({1'b0,1'b0,1'b0,1'b0}),
.s_axi_arid(1'b0),
.s_axi_arlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_arlock(1'b0),
.s_axi_arprot({1'b0,1'b0,1'b0}),
.s_axi_arqos({1'b0,1'b0,1'b0,1'b0}),
.s_axi_arready(NLW_U0_s_axi_arready_UNCONNECTED),
.s_axi_arregion({1'b0,1'b0,1'b0,1'b0}),
.s_axi_arsize({1'b0,1'b0,1'b0}),
.s_axi_aruser(1'b0),
.s_axi_arvalid(1'b0),
.s_axi_awaddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_awburst({1'b0,1'b0}),
.s_axi_awcache({1'b0,1'b0,1'b0,1'b0}),
.s_axi_awid(1'b0),
.s_axi_awlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_awlock(1'b0),
.s_axi_awprot({1'b0,1'b0,1'b0}),
.s_axi_awqos({1'b0,1'b0,1'b0,1'b0}),
.s_axi_awready(NLW_U0_s_axi_awready_UNCONNECTED),
.s_axi_awregion({1'b0,1'b0,1'b0,1'b0}),
.s_axi_awsize({1'b0,1'b0,1'b0}),
.s_axi_awuser(1'b0),
.s_axi_awvalid(1'b0),
.s_axi_bid(NLW_U0_s_axi_bid_UNCONNECTED[0]),
.s_axi_bready(1'b0),
.s_axi_bresp(NLW_U0_s_axi_bresp_UNCONNECTED[1:0]),
.s_axi_buser(NLW_U0_s_axi_buser_UNCONNECTED[0]),
.s_axi_bvalid(NLW_U0_s_axi_bvalid_UNCONNECTED),
.s_axi_rdata(NLW_U0_s_axi_rdata_UNCONNECTED[63:0]),
.s_axi_rid(NLW_U0_s_axi_rid_UNCONNECTED[0]),
.s_axi_rlast(NLW_U0_s_axi_rlast_UNCONNECTED),
.s_axi_rready(1'b0),
.s_axi_rresp(NLW_U0_s_axi_rresp_UNCONNECTED[1:0]),
.s_axi_ruser(NLW_U0_s_axi_ruser_UNCONNECTED[0]),
.s_axi_rvalid(NLW_U0_s_axi_rvalid_UNCONNECTED),
.s_axi_wdata({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_wid(1'b0),
.s_axi_wlast(1'b0),
.s_axi_wready(NLW_U0_s_axi_wready_UNCONNECTED),
.s_axi_wstrb({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_wuser(1'b0),
.s_axi_wvalid(1'b0),
.s_axis_tdata({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axis_tdest(1'b0),
.s_axis_tid(1'b0),
.s_axis_tkeep(1'b0),
.s_axis_tlast(1'b0),
.s_axis_tready(NLW_U0_s_axis_tready_UNCONNECTED),
.s_axis_tstrb(1'b0),
.s_axis_tuser({1'b0,1'b0,1'b0,1'b0}),
.s_axis_tvalid(1'b0),
.sbiterr(NLW_U0_sbiterr_UNCONNECTED),
.sleep(1'b0),
.srst(srst),
.underflow(NLW_U0_underflow_UNCONNECTED),
.valid(NLW_U0_valid_UNCONNECTED),
.wr_ack(NLW_U0_wr_ack_UNCONNECTED),
.wr_clk(1'b0),
.wr_data_count(NLW_U0_wr_data_count_UNCONNECTED[9:0]),
.wr_en(wr_en),
.wr_rst(1'b0),
.wr_rst_busy(NLW_U0_wr_rst_busy_UNCONNECTED));
endmodule |
module pcie_recv_fifo_blk_mem_gen_generic_cstr
(D,
clk,
tmp_ram_rd_en,
ram_full_fb_i_reg,
srst,
\gc0.count_d1_reg[8] ,
\gcc0.gc0.count_d1_reg[8] ,
din);
output [127:0]D;
input clk;
input tmp_ram_rd_en;
input [0:0]ram_full_fb_i_reg;
input srst;
input [8:0]\gc0.count_d1_reg[8] ;
input [8:0]\gcc0.gc0.count_d1_reg[8] ;
input [127:0]din;
wire [127:0]D;
wire clk;
wire [127:0]din;
wire [8:0]\gc0.count_d1_reg[8] ;
wire [8:0]\gcc0.gc0.count_d1_reg[8] ;
wire [0:0]ram_full_fb_i_reg;
wire srst;
wire tmp_ram_rd_en;
pcie_recv_fifo_blk_mem_gen_prim_width \ramloop[0].ram.r
(.D(D[71:0]),
.clk(clk),
.din(din[71:0]),
.\gc0.count_d1_reg[8] (\gc0.count_d1_reg[8] ),
.\gcc0.gc0.count_d1_reg[8] (\gcc0.gc0.count_d1_reg[8] ),
.ram_full_fb_i_reg(ram_full_fb_i_reg),
.srst(srst),
.tmp_ram_rd_en(tmp_ram_rd_en));
pcie_recv_fifo_blk_mem_gen_prim_width__parameterized0 \ramloop[1].ram.r
(.D(D[127:72]),
.clk(clk),
.din(din[127:72]),
.\gc0.count_d1_reg[8] (\gc0.count_d1_reg[8] ),
.\gcc0.gc0.count_d1_reg[8] (\gcc0.gc0.count_d1_reg[8] ),
.ram_full_fb_i_reg(ram_full_fb_i_reg),
.srst(srst),
.tmp_ram_rd_en(tmp_ram_rd_en));
endmodule |
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