module_content
stringlengths 18
1.05M
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module body
//
assign icoef = { {(mwidth-cwidth){coef[cwidth-1]}}, coef};
assign idin = { {(mwidth-dwidth){din[dwidth-1]}}, din};
// generate multiplier structure
always @(posedge clk)
if(ena)
mult_res <= #1 icoef * idin;
assign ext_mult_res = { {3{mult_res[mwidth-1]}}, mult_res};
// generate adder structure
always @(posedge clk)
if(ena)
if(dclr)
result <= #1 ext_mult_res;
else
result <= #1 ext_mult_res + result;
endmodule |
module div_uu(clk, ena, z, d, q, s, div0, ovf);
//
// parameters
//
parameter z_width = 16;
parameter d_width = z_width /2;
//
// inputs & outputs
//
input clk; // system clock
input ena; // clock enable
input [z_width -1:0] z; // divident
input [d_width -1:0] d; // divisor
output [d_width -1:0] q; // quotient
reg [d_width-1:0] q;
output [d_width -1:0] s; // remainder
reg [d_width-1:0] s;
output div0;
reg div0;
output ovf;
reg ovf;
//
// functions
//
function [z_width:0] gen_s;
input [z_width:0] si;
input [z_width:0] di;
begin
if(si[z_width])
gen_s = {si[z_width-1:0], 1'b0} + di;
else
gen_s = {si[z_width-1:0], 1'b0} - di;
end
endfunction
function [d_width-1:0] gen_q;
input [d_width-1:0] qi;
input [z_width:0] si;
begin
gen_q = {qi[d_width-2:0], ~si[z_width]};
end
endfunction
function [d_width-1:0] assign_s;
input [z_width:0] si;
input [z_width:0] di;
reg [z_width:0] tmp;
begin
if(si[z_width])
tmp = si + di;
else
tmp = si;
assign_s = tmp[z_width-1:z_width-4];
end
endfunction
//
// variables
//
reg [d_width-1:0] q_pipe [d_width-1:0];
reg [z_width:0] s_pipe [d_width:0];
reg [z_width:0] d_pipe [d_width:0];
reg [d_width:0] div0_pipe, ovf_pipe;
//
// perform parameter checks
//
// synopsys translate_off
initial
begin
if(d_width !== z_width / 2)
$display("div.v parameter error (d_width != z_width/2).");
end
// synopsys translate_on
integer n0, n1, n2, n3;
// generate divisor (d) pipe
always @(d)
d_pipe[0] <= {1'b0, d, {(z_width-d_width){1'b0}} };
always @(posedge clk)
if(ena)
for(n0=1; n0 <= d_width; n0=n0+1)
d_pipe[n0] <= #1 d_pipe[n0-1];
// generate internal remainder pipe
always @(z)
s_pipe[0] <= z;
always @(posedge clk)
if(ena)
for(n1=1; n1 <= d_width; n1=n1+1)
s_pipe[n1] <= #1 gen_s(s_pipe[n1-1], d_pipe[n1-1]);
// generate quotient pipe
always @(posedge clk)
q_pipe[0] <= #1 0;
always @(posedge clk)
if(ena)
for(n2=1; n2 < d_width; n2=n2+1)
q_pipe[n2] <= #1 gen_q(q_pipe[n2-1], s_pipe[n2]);
// flags (divide_by_zero, overflow)
always @(z or d)
begin
ovf_pipe[0] <= !(z[z_width-1:d_width] < d);
div0_pipe[0] <= ~|d;
end
always @(posedge clk)
if(ena)
for(n3=1; n3 <= d_width; n3=n3+1)
begin
ovf_pipe[n3] <= #1 ovf_pipe[n3-1];
div0_pipe[n3] <= #1 div0_pipe[n3-1];
end
// assign outputs
always @(posedge clk)
if(ena)
ovf <= #1 ovf_pipe[d_width];
always @(posedge clk)
if(ena)
div0 <= #1 div0_pipe[d_width];
always @(posedge clk)
if(ena)
q <= #1 gen_q(q_pipe[d_width-1], s_pipe[d_width]);
always @(posedge clk)
if(ena)
s <= #1 assign_s(s_pipe[d_width], d_pipe[d_width]);
endmodule |
module body
//
// delay d
always @(posedge clk)
if (ena)
id <= #1 d;
// check z, take abs value
always @(posedge clk)
if (ena)
if (z[z_width-1])
iz <= #1 ~z +1'h1;
else
iz <= #1 z;
// generate spipe (sign bit pipe)
integer n;
always @(posedge clk)
if(ena)
begin
spipe[0] <= #1 z[z_width-1];
for(n=1; n <= d_width+1; n=n+1)
spipe[n] <= #1 spipe[n-1];
end
// hookup non-restoring divider
div_uu #(z_width, d_width)
divider (
.clk(clk),
.ena(ena),
.z(iz),
.d(id),
.q(iq),
.s(is),
.div0(idiv0),
.ovf(iovf)
);
// correct divider results if 'd' was negative
always @(posedge clk)
if(ena)
if(spipe[d_width+1])
begin
q <= #1 (~iq) + 1'h1;
s <= #1 (~is) + 1'h1;
end
else
begin
q <= #1 {1'b0, iq};
s <= #1 {1'b0, is};
end
// delay flags same as results
always @(posedge clk)
if(ena)
begin
div0 <= #1 idiv0;
ovf <= #1 iovf;
end
endmodule |
module body
//
//
// function declarations
//
// Function abs; absolute value
function [10:0] abs;
input [11:0] a;
begin
if (a[11])
abs = (~a[10:0]) +11'h1;
else
abs = a[10:0];
end
endfunction
// Function cat, calculates category for Din
function [3:0] cat;
input [11:0] a;
reg [10:0] tmp;
begin
// get absolute value
tmp = abs(a);
// determine category
casex(tmp) // synopsys full_case parallel_case
11'b1??_????_???? : cat = 4'hb; // 1024..2047
11'b01?_????_???? : cat = 4'ha; // 512..1023
11'b001_????_???? : cat = 4'h9; // 256.. 511
11'b000_1???_???? : cat = 4'h8; // 128.. 255
11'b000_01??_???? : cat = 4'h7; // 64.. 127
11'b000_001?_???? : cat = 4'h6; // 32.. 63
11'b000_0001_???? : cat = 4'h5; // 16.. 31
11'b000_0000_1??? : cat = 4'h4; // 8.. 15
11'b000_0000_01?? : cat = 4'h3; // 4.. 7
11'b000_0000_001? : cat = 4'h2; // 2.. 3
11'b000_0000_0001 : cat = 4'h1; // 1
11'b000_0000_0000 : cat = 4'h0; // 0 (DC only)
endcase
end
endfunction
// Function modamp, calculate additional bits per category
function [10:0] rem;
input [11:0] a;
reg [10:0] tmp, tmp_rem;
begin
tmp_rem = a[11] ? (a[10:0] - 10'h1) : a[10:0];
if(0)
begin
// get absolute value
tmp = abs(a);
casex(tmp) // synopsys full_case parallel_case
11'b1??_????_???? : rem = tmp_rem & 11'b111_1111_1111;
11'b01?_????_???? : rem = tmp_rem & 11'b011_1111_1111;
11'b001_????_???? : rem = tmp_rem & 11'b001_1111_1111;
11'b000_1???_???? : rem = tmp_rem & 11'b000_1111_1111;
11'b000_01??_???? : rem = tmp_rem & 11'b000_0111_1111;
11'b000_001?_???? : rem = tmp_rem & 11'b000_0011_1111;
11'b000_0001_???? : rem = tmp_rem & 11'b000_0001_1111;
11'b000_0000_1??? : rem = tmp_rem & 11'b000_0000_1111;
11'b000_0000_01?? : rem = tmp_rem & 11'b000_0000_0111;
11'b000_0000_001? : rem = tmp_rem & 11'b000_0000_0011;
11'b000_0000_0001 : rem = tmp_rem & 11'b000_0000_0001;
11'b000_0000_0000 : rem = tmp_rem & 11'b000_0000_0000;
endcase
end
else
rem = tmp_rem;
end
endfunction
// detect zero
assign is_zero = ~|din;
// assign dout
always @(posedge clk)
if (ena)
amp <= #1 rem(din);
// generate sample counter
always @(posedge clk)
if (ena)
if (go)
sample_cnt <= #1 1; // count AC-terms, 'go=1' is sample-zero
else
sample_cnt <= #1 sample_cnt +1;
// generate zero counter
always @(posedge clk)
if (ena)
if (is_zero)
zero_cnt <= #1 zero_cnt +1;
else
zero_cnt <= #1 0;
// statemachine, create intermediate results
always @(posedge clk or negedge rst)
if(!rst)
begin
state <= #1 dc;
rlen <= #1 0;
size <= #1 0;
den <= #1 1'b0;
dcterm <= #1 1'b0;
end
else if (ena)
case (state) // synopsys full_case parallel_case
dc:
begin
rlen <= #1 0;
size <= #1 cat(din);
if(go)
begin
state <= #1 ac;
den <= #1 1'b1;
dcterm <= #1 1'b1;
end
else
begin
state <= #1 dc;
den <= #1 1'b0;
dcterm <= #1 1'b0;
end
end
ac:
if(&sample_cnt) // finished current block
begin
state <= #1 dc;
if (is_zero) // last sample zero? send EOB
begin
rlen <= #1 0;
size <= #1 0;
den <= #1 1'b1;
dcterm <= #1 1'b0;
end
else
begin
rlen <= #1 zero_cnt;
size <= #1 cat(din);
den <= #1 1'b1;
dcterm <= #1 1'b0;
end
end
else
begin
state <= #1 ac;
rlen <= #1 zero_cnt;
dcterm <= #1 1'b0;
if (is_zero)
begin
size <= #1 0;
den <= #1 &zero_cnt;
end
else
begin
size <= #1 cat(din);
den <= #1 1'b1;
end
end
endcase
endmodule |
module body
//
always @(posedge clk)
if(ena)
ld_zigzag <= #1 dstrb;
assign douten = ld_zigzag;
//
// Generate zig-zag structure
//
// This implicates that the quantization step be performed after
// the zig-zagging.
//
// 0: 1: 2: 3: 4: 5: 6: 7: 0: 1: 2: 3: 4: 5: 6: 7:
// 0: 63 62 58 57 49 48 36 35 3f 3e 3a 39 31 30 24 23
// 1: 61 59 56 50 47 37 34 21 3d 3b 38 32 2f 25 22 15
// 2: 60 55 51 46 38 33 22 20 3c 37 33 2e 26 21 16 14
// 3: 54 52 45 39 32 23 19 10 36 34 2d 27 20 17 13 0a
// 4: 53 44 40 31 24 18 11 09 35 2c 28 1f 18 12 0b 09
// 5: 43 41 30 25 17 12 08 03 2b 29 1e 19 11 0c 08 03
// 6: 42 29 26 16 13 07 04 02 2a 1d 1a 10 0d 07 04 02
// 7: 28 27 15 14 06 05 01 00 1c 1b 0f 0e 06 05 01 00
//
// zig-zag the DCT results
integer n;
always @(posedge clk)
if(ena)
if(ld_zigzag) // reload results-register file
begin
sresult[63] <= #1 din_00;
sresult[62] <= #1 din_01;
sresult[61] <= #1 din_10;
sresult[60] <= #1 din_20;
sresult[59] <= #1 din_11;
sresult[58] <= #1 din_02;
sresult[57] <= #1 din_03;
sresult[56] <= #1 din_12;
sresult[55] <= #1 din_21;
sresult[54] <= #1 din_30;
sresult[53] <= #1 din_40;
sresult[52] <= #1 din_31;
sresult[51] <= #1 din_22;
sresult[50] <= #1 din_13;
sresult[49] <= #1 din_04;
sresult[48] <= #1 din_05;
sresult[47] <= #1 din_14;
sresult[46] <= #1 din_23;
sresult[45] <= #1 din_32;
sresult[44] <= #1 din_41;
sresult[43] <= #1 din_50;
sresult[42] <= #1 din_60;
sresult[41] <= #1 din_51;
sresult[40] <= #1 din_42;
sresult[39] <= #1 din_33;
sresult[38] <= #1 din_24;
sresult[37] <= #1 din_15;
sresult[36] <= #1 din_06;
sresult[35] <= #1 din_07;
sresult[34] <= #1 din_16;
sresult[33] <= #1 din_25;
sresult[32] <= #1 din_34;
sresult[31] <= #1 din_43;
sresult[30] <= #1 din_52;
sresult[29] <= #1 din_61;
sresult[28] <= #1 din_70;
sresult[27] <= #1 din_71;
sresult[26] <= #1 din_62;
sresult[25] <= #1 din_53;
sresult[24] <= #1 din_44;
sresult[23] <= #1 din_35;
sresult[22] <= #1 din_26;
sresult[21] <= #1 din_17;
sresult[20] <= #1 din_27;
sresult[19] <= #1 din_36;
sresult[18] <= #1 din_45;
sresult[17] <= #1 din_54;
sresult[16] <= #1 din_63;
sresult[15] <= #1 din_72;
sresult[14] <= #1 din_73;
sresult[13] <= #1 din_64;
sresult[12] <= #1 din_55;
sresult[11] <= #1 din_46;
sresult[10] <= #1 din_37;
sresult[09] <= #1 din_47;
sresult[08] <= #1 din_56;
sresult[07] <= #1 din_65;
sresult[06] <= #1 din_74;
sresult[05] <= #1 din_75;
sresult[04] <= #1 din_66;
sresult[03] <= #1 din_57;
sresult[02] <= #1 din_67;
sresult[01] <= #1 din_76;
sresult[00] <= #1 din_77;
end
else // shift results out
for (n=1; n<=63; n=n+1) // do not change sresult[0]
sresult[n] <= #1 sresult[n -1];
assign dout = sresult[63];
endmodule |
module memory_mux (
input select,
input enable_0,
input command_0,
input [31:0] address_0,
input [31:0] write_data_0,
input [3:0] write_mask_0,
output [31:0] read_data_0,
output valid_0,
input enable_1,
input command_1,
input [31:0] address_1,
input [31:0] write_data_1,
input [3:0] write_mask_1,
output [31:0] read_data_1,
output valid_1,
output enable,
output command,
output [31:0] address,
output [31:0] write_data,
output [3:0] write_mask,
input [31:0] read_data,
input valid
);
assign enable = select ? enable_1 : enable_0;
assign command = select ? command_1 : command_0;
assign address = select ? address_1 : address_0;
assign write_data = select ? write_data_1 : write_data_0;
assign write_mask = select ? write_mask_1 : write_mask_0;
assign read_data_1 = read_data;
assign read_data_0 = read_data;
assign valid_1 = select ? valid : 1'b0;
assign valid_0 = !select ? valid : 1'b0;
endmodule |
module sky130_fd_sc_hs__a311o (
//# {{data|Data Signals}}
input A1 ,
input A2 ,
input A3 ,
input B1 ,
input C1 ,
output X ,
//# {{power|Power}}
input VPWR,
input VGND
);
endmodule |
module Approx_adder_W16 ( add_sub, in1, in2, res );
input [15:0] in1;
input [15:0] in2;
output [16:0] res;
input add_sub;
wire n58, n59, n60, n61, n62, n63, n64, n65, n66, n67, n68, n69, n70, n71,
n72, n73, n74, n75, n76, n77, n78, n79, n80, n81, n82, n83, n84, n85,
n86, n87, n88, n89, n90, n91, n92, n93, n94, n95, n96, n97, n98, n99,
n100, n101, n102, n103, n104, n105, n106, n107, n108, n109, n110,
n111, n112, n113, n114, n115, n116, n117, n118, n119, n120, n121,
n122, n123, n124, n125, n126, n127, n128, n129, n130, n131, n132,
n133, n134, n135, n136, n137, n138, n139, n140, n141, n142, n143,
n144, n145, n146, n147, n148, n149, n150, n151, n152, n153, n154,
n155, n156, n157, n158, n159, n160, n161, n162, n163, n164, n165,
n166, n167, n168, n169, n170, n171, n172, n173, n174, n175, n176,
n177, n178, n179, n180, n181, n182, n183, n184;
OA21XLTS U74 ( .A0(n181), .A1(n183), .B0(n161), .Y(n131) );
NAND2X1TS U75 ( .A(n64), .B(n63), .Y(n182) );
NAND2X1TS U76 ( .A(n117), .B(in1[3]), .Y(n161) );
XNOR2X2TS U77 ( .A(n69), .B(in2[15]), .Y(n112) );
NAND2X1TS U78 ( .A(n100), .B(in1[10]), .Y(n136) );
NAND2X1TS U79 ( .A(n70), .B(add_sub), .Y(n71) );
NAND2X1TS U80 ( .A(in1[2]), .B(n59), .Y(n181) );
CMPR32X2TS U81 ( .A(n157), .B(in1[7]), .C(n156), .CO(n170), .S(res[7]) );
XOR2X2TS U82 ( .A(n73), .B(in2[13]), .Y(n107) );
NOR2X1TS U83 ( .A(n72), .B(n101), .Y(n73) );
NAND2XLTS U84 ( .A(n98), .B(add_sub), .Y(n99) );
NOR2XLTS U85 ( .A(n102), .B(n101), .Y(n103) );
XOR2X2TS U86 ( .A(n91), .B(in2[9]), .Y(n95) );
NOR2X1TS U87 ( .A(n90), .B(n101), .Y(n91) );
INVX2TS U88 ( .A(add_sub), .Y(n101) );
NOR2XLTS U89 ( .A(n101), .B(n60), .Y(n61) );
XOR2X1TS U90 ( .A(n103), .B(in2[11]), .Y(n104) );
NAND2X1TS U91 ( .A(n106), .B(in1[12]), .Y(n145) );
NOR2X6TS U92 ( .A(n92), .B(in2[8]), .Y(n90) );
NAND2X2TS U93 ( .A(n79), .B(add_sub), .Y(n80) );
NAND2X2TS U94 ( .A(n177), .B(n176), .Y(n178) );
XNOR2X2TS U95 ( .A(n75), .B(in2[12]), .Y(n106) );
NAND2X2TS U96 ( .A(n74), .B(add_sub), .Y(n75) );
NOR2X6TS U97 ( .A(n79), .B(in2[6]), .Y(n77) );
AO21X2TS U98 ( .A0(n114), .A1(n174), .B0(n113), .Y(res[16]) );
XOR2X1TS U99 ( .A(n155), .B(n154), .Y(res[13]) );
AOI21X2TS U100 ( .A0(n151), .A1(n150), .B0(n149), .Y(n155) );
NAND2X2TS U101 ( .A(n107), .B(in1[13]), .Y(n152) );
XOR2X1TS U102 ( .A(n129), .B(n128), .Y(res[9]) );
XNOR2X2TS U103 ( .A(n99), .B(in2[10]), .Y(n100) );
XOR2X1TS U104 ( .A(n166), .B(n165), .Y(res[6]) );
XNOR2X2TS U105 ( .A(n93), .B(in2[8]), .Y(n94) );
XOR2X1TS U106 ( .A(n121), .B(n158), .Y(res[5]) );
NOR2X1TS U107 ( .A(n164), .B(n163), .Y(n165) );
AND2X2TS U108 ( .A(n88), .B(in1[6]), .Y(n163) );
OA21XLTS U109 ( .A0(n64), .A1(n63), .B0(n182), .Y(res[2]) );
INVX1TS U110 ( .A(n158), .Y(n162) );
XOR2XLTS U111 ( .A(n180), .B(n122), .Y(res[1]) );
XOR2X1TS U112 ( .A(n130), .B(in1[1]), .Y(n122) );
OAI21X1TS U113 ( .A0(n180), .A1(in1[1]), .B0(n130), .Y(n62) );
AOI2BB1XLTS U114 ( .A0N(in2[0]), .A1N(in1[0]), .B0(n180), .Y(res[0]) );
OAI21X1TS U115 ( .A0(in2[1]), .A1(in2[0]), .B0(add_sub), .Y(n58) );
OAI21X1TS U116 ( .A0(n131), .A1(n160), .B0(n119), .Y(n121) );
NAND2X4TS U117 ( .A(n118), .B(in1[4]), .Y(n119) );
XNOR2X2TS U118 ( .A(n116), .B(in2[3]), .Y(n117) );
NAND2BX4TS U119 ( .AN(in2[7]), .B(n77), .Y(n92) );
XNOR2X2TS U120 ( .A(n82), .B(in2[4]), .Y(n118) );
NAND2X1TS U121 ( .A(n81), .B(add_sub), .Y(n82) );
XNOR2X2TS U122 ( .A(n84), .B(in2[5]), .Y(n120) );
NAND2X2TS U123 ( .A(n92), .B(add_sub), .Y(n93) );
NOR2BX2TS U124 ( .AN(in1[0]), .B(n60), .Y(n180) );
OAI21X2TS U125 ( .A0(n118), .A1(in1[4]), .B0(n119), .Y(n160) );
INVX2TS U126 ( .A(n167), .Y(n124) );
NAND2BX2TS U127 ( .AN(in2[13]), .B(n72), .Y(n70) );
INVX2TS U128 ( .A(n163), .Y(n89) );
NAND2X1TS U129 ( .A(n168), .B(n167), .Y(n169) );
XOR2XLTS U130 ( .A(n139), .B(n138), .Y(res[10]) );
NAND2X1TS U131 ( .A(n150), .B(n145), .Y(n146) );
NOR2X4TS U132 ( .A(n95), .B(in1[9]), .Y(n125) );
AOI21X2TS U133 ( .A0(n89), .A1(n159), .B0(n164), .Y(n156) );
NOR2X4TS U134 ( .A(n112), .B(in1[15]), .Y(n175) );
OAI21X4TS U135 ( .A0(n110), .A1(n144), .B0(n109), .Y(n174) );
AOI21X4TS U136 ( .A0(n143), .A1(n141), .B0(n105), .Y(n144) );
AOI21X2TS U137 ( .A0(n153), .A1(n149), .B0(n108), .Y(n109) );
NAND2BX4TS U138 ( .AN(in2[9]), .B(n90), .Y(n98) );
XNOR2X4TS U139 ( .A(n71), .B(in2[14]), .Y(n111) );
OAI21X4TS U140 ( .A0(n119), .A1(n85), .B0(n120), .Y(n86) );
XNOR2X4TS U141 ( .A(n80), .B(in2[6]), .Y(n88) );
XNOR2X1TS U142 ( .A(n58), .B(in2[2]), .Y(n59) );
OAI21X1TS U143 ( .A0(in1[2]), .A1(n59), .B0(n181), .Y(n133) );
INVX2TS U144 ( .A(n133), .Y(n64) );
INVX4TS U145 ( .A(in2[0]), .Y(n60) );
CLKXOR2X2TS U146 ( .A(n61), .B(in2[1]), .Y(n130) );
OAI2BB1X1TS U147 ( .A0N(n180), .A1N(in1[1]), .B0(n62), .Y(n63) );
INVX2TS U148 ( .A(in2[1]), .Y(n67) );
INVX2TS U149 ( .A(in2[2]), .Y(n66) );
INVX2TS U150 ( .A(in2[3]), .Y(n65) );
NAND4X4TS U151 ( .A(n60), .B(n67), .C(n66), .D(n65), .Y(n81) );
NOR2X4TS U152 ( .A(n81), .B(in2[4]), .Y(n83) );
INVX2TS U153 ( .A(in2[5]), .Y(n68) );
NAND2X4TS U154 ( .A(n83), .B(n68), .Y(n79) );
NOR2X4TS U155 ( .A(n98), .B(in2[10]), .Y(n102) );
NAND2BX4TS U156 ( .AN(in2[11]), .B(n102), .Y(n74) );
NOR2X4TS U157 ( .A(n74), .B(in2[12]), .Y(n72) );
OAI21X1TS U158 ( .A0(n70), .A1(in2[14]), .B0(add_sub), .Y(n69) );
NOR2X2TS U159 ( .A(n111), .B(in1[14]), .Y(n147) );
NOR2X1TS U160 ( .A(n175), .B(n147), .Y(n114) );
OR2X2TS U161 ( .A(n107), .B(in1[13]), .Y(n153) );
NOR2X1TS U162 ( .A(n106), .B(in1[12]), .Y(n76) );
INVX2TS U163 ( .A(n76), .Y(n150) );
NAND2X2TS U164 ( .A(n153), .B(n150), .Y(n110) );
NOR2X1TS U165 ( .A(n77), .B(n101), .Y(n78) );
XOR2X1TS U166 ( .A(n78), .B(in2[7]), .Y(n157) );
INVX2TS U167 ( .A(n119), .Y(n87) );
INVX2TS U168 ( .A(in1[5]), .Y(n85) );
NOR2X1TS U169 ( .A(n83), .B(n101), .Y(n84) );
OAI21X4TS U170 ( .A0(n87), .A1(in1[5]), .B0(n86), .Y(n159) );
NOR2X2TS U171 ( .A(n88), .B(in1[6]), .Y(n164) );
NOR2X2TS U172 ( .A(n94), .B(in1[8]), .Y(n123) );
NOR2X1TS U173 ( .A(n125), .B(n123), .Y(n97) );
NAND2X2TS U174 ( .A(n94), .B(in1[8]), .Y(n167) );
NAND2X2TS U175 ( .A(n95), .B(in1[9]), .Y(n126) );
OAI21X1TS U176 ( .A0(n125), .A1(n167), .B0(n126), .Y(n96) );
AOI21X4TS U177 ( .A0(n170), .A1(n97), .B0(n96), .Y(n139) );
NOR2X2TS U178 ( .A(n100), .B(in1[10]), .Y(n135) );
OAI21X4TS U179 ( .A0(n139), .A1(n135), .B0(n136), .Y(n143) );
OR2X2TS U180 ( .A(n104), .B(in1[11]), .Y(n141) );
NAND2X2TS U181 ( .A(n104), .B(in1[11]), .Y(n140) );
INVX2TS U182 ( .A(n140), .Y(n105) );
INVX2TS U183 ( .A(n145), .Y(n149) );
INVX2TS U184 ( .A(n152), .Y(n108) );
NAND2X2TS U185 ( .A(n111), .B(in1[14]), .Y(n171) );
NAND2X2TS U186 ( .A(n112), .B(in1[15]), .Y(n176) );
OAI21X1TS U187 ( .A0(n175), .A1(n171), .B0(n176), .Y(n113) );
OR3X1TS U188 ( .A(in2[2]), .B(in2[1]), .C(in2[0]), .Y(n115) );
NAND2X1TS U189 ( .A(add_sub), .B(n115), .Y(n116) );
OAI21X2TS U190 ( .A0(n117), .A1(in1[3]), .B0(n161), .Y(n183) );
XNOR2X1TS U191 ( .A(n120), .B(in1[5]), .Y(n158) );
INVX2TS U192 ( .A(n123), .Y(n168) );
AOI21X1TS U193 ( .A0(n170), .A1(n168), .B0(n124), .Y(n129) );
INVX2TS U194 ( .A(n125), .Y(n127) );
NAND2X1TS U195 ( .A(n127), .B(n126), .Y(n128) );
NAND2X1TS U196 ( .A(n130), .B(in1[1]), .Y(n132) );
OAI31X1TS U197 ( .A0(n133), .A1(n183), .A2(n132), .B0(n131), .Y(n134) );
XNOR2X1TS U198 ( .A(n134), .B(n160), .Y(res[4]) );
INVX2TS U199 ( .A(n135), .Y(n137) );
NAND2X1TS U200 ( .A(n137), .B(n136), .Y(n138) );
NAND2X1TS U201 ( .A(n141), .B(n140), .Y(n142) );
XNOR2X1TS U202 ( .A(n143), .B(n142), .Y(res[11]) );
INVX2TS U203 ( .A(n144), .Y(n151) );
XNOR2X1TS U204 ( .A(n151), .B(n146), .Y(res[12]) );
INVX2TS U205 ( .A(n147), .Y(n173) );
NAND2X1TS U206 ( .A(n173), .B(n171), .Y(n148) );
XNOR2X1TS U207 ( .A(n174), .B(n148), .Y(res[14]) );
NAND2X1TS U208 ( .A(n153), .B(n152), .Y(n154) );
OAI31X1TS U209 ( .A0(n162), .A1(n161), .A2(n160), .B0(n159), .Y(n166) );
XNOR2X1TS U210 ( .A(n170), .B(n169), .Y(res[8]) );
INVX2TS U211 ( .A(n171), .Y(n172) );
AOI21X4TS U212 ( .A0(n174), .A1(n173), .B0(n172), .Y(n179) );
INVX2TS U213 ( .A(n175), .Y(n177) );
XOR2X1TS U214 ( .A(n179), .B(n178), .Y(res[15]) );
NAND2X1TS U215 ( .A(n182), .B(n181), .Y(n184) );
XNOR2X1TS U216 ( .A(n184), .B(n183), .Y(res[3]) );
initial $sdf_annotate("Approx_adder_GDAN8M8P3_syn.sdf");
endmodule |
module SSeg_map(input[63:0]Disp_num,
output[63:0]Seg_map
);
assign Seg_map = {Disp_num[0], Disp_num[4], Disp_num[16], Disp_num[25], Disp_num[17], Disp_num[5], Disp_num[12], Disp_num[24],
Disp_num[1], Disp_num[6], Disp_num[18], Disp_num[27], Disp_num[19], Disp_num[7], Disp_num[13], Disp_num[26],
Disp_num[2], Disp_num[8], Disp_num[20], Disp_num[29], Disp_num[21], Disp_num[9], Disp_num[14], Disp_num[28],
Disp_num[3], Disp_num[10], Disp_num[22], Disp_num[31], Disp_num[23], Disp_num[11], Disp_num[15], Disp_num[30],
Disp_num[0], Disp_num[4], Disp_num[16], Disp_num[25], Disp_num[17], Disp_num[5], Disp_num[12], Disp_num[24],
Disp_num[1], Disp_num[6], Disp_num[18], Disp_num[27], Disp_num[19], Disp_num[7], Disp_num[13], Disp_num[26],
Disp_num[2], Disp_num[8], Disp_num[20], Disp_num[29], Disp_num[21], Disp_num[9], Disp_num[14], Disp_num[28],
Disp_num[3], Disp_num[10], Disp_num[22], Disp_num[31], Disp_num[23], Disp_num[11], Disp_num[15], Disp_num[30]};
endmodule |
module i2s_test;
// Inputs
reg clock;
reg reset;
reg [15:0] left_data;
reg [15:0] right_data;
// Outputs
wire mclk;
wire lrck;
wire sclk;
wire sdin;
// Instantiate the Unit Under Test (UUT)
i2s_out uut (
.clock(clock),
.reset(reset),
.left_data(left_data),
.right_data(right_data),
.mclk(mclk),
.lrck(lrck),
.sclk(sclk),
.sdin(sdin)
);
initial begin
// Initialize Inputs
clock = 0;
reset = 0;
left_data = 0;
right_data = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
end
endmodule |
module OC_Buff(in, out);
input in;
output out;
assign out = in ? 1'bz : 1'b0;
endmodule |
module pluto_spi_rspi(clk, SCK, MOSI, MISO, SSEL, LED, nConfig, nRESET, nPE, quadA, quadB, quadZ, up, down, dout, din);
parameter QW=14;
input clk;
input SCK, SSEL, MOSI, nRESET;
output MISO, nConfig, nPE;
output LED;
//output [3:0] down = 4'bZZZZ;
//output [3:0] up = 4'bZZZZ;
input [7:0] din;
input [3:0] quadA;
input [3:0] quadB;
input [3:0] quadZ;
wire do_tristate;
assign nConfig = nRESET;
//assign nConfig = 1'b1;
assign nPE = 1'b1;
reg[9:0] real_dout;
output [9:0] dout = do_tristate ? 10'bZZZZZZZZZZ : real_dout;
wire[3:0] real_up;
output [3:0] up = do_tristate ? 4'bZZZZ : real_up;
wire[3:0] real_down;
output [3:0] down = do_tristate ? 4'bZZZZ : real_down;
reg Zpolarity;
//**********************************************************************
// PWM stuff
// PWM clock is about 20kHz for clk @ 40MHz, 11-bit cnt
wire pwm_at_top;
reg [10:0] pwmcnt;
wire [10:0] top = 11'd2047;
assign pwm_at_top = (pwmcnt == top);
reg [15:0] pwm0, pwm1, pwm2, pwm3;
always @(posedge clk) begin
if(pwm_at_top) pwmcnt <= 0;
else pwmcnt <= pwmcnt + 11'd1;
end
wire [10:0] pwmrev = {
pwmcnt[4], pwmcnt[5], pwmcnt[6], pwmcnt[7], pwmcnt[8], pwmcnt[9],
pwmcnt[10], pwmcnt[3:0]};
wire [10:0] pwmcmp0 = pwm0[14] ? pwmrev : pwmcnt; // pwm0[14] = pdm/pwm bit
// wire [10:0] pwmcmp1 = pwm1[14] ? pwmrev : pwmcnt;
// wire [10:0] pwmcmp2 = pwm2[14] ? pwmrev : pwmcnt;
// wire [10:0] pwmcmp3 = pwm3[14] ? pwmrev : pwmcnt;
wire pwmact0 = pwm0[10:0] > pwmcmp0;
wire pwmact1 = pwm1[10:0] > pwmcmp0;
wire pwmact2 = pwm2[10:0] > pwmcmp0;
wire pwmact3 = pwm3[10:0] > pwmcmp0;
assign real_up[0] = pwm0[12] ^ (pwm0[15] ? 1'd0 : pwmact0);
assign real_up[1] = pwm1[12] ^ (pwm1[15] ? 1'd0 : pwmact1);
assign real_up[2] = pwm2[12] ^ (pwm2[15] ? 1'd0 : pwmact2);
assign real_up[3] = pwm3[12] ^ (pwm3[15] ? 1'd0 : pwmact3);
assign real_down[0] = pwm0[13] ^ (~pwm0[15] ? 1'd0 : pwmact0);
assign real_down[1] = pwm1[13] ^ (~pwm1[15] ? 1'd0 : pwmact1);
assign real_down[2] = pwm2[13] ^ (~pwm2[15] ? 1'd0 : pwmact2);
assign real_down[3] = pwm3[13] ^ (~pwm3[15] ? 1'd0 : pwmact3);
//**********************************************************************
// Quadrature stuff
// Quadrature is digitized at 40MHz into 14-bit counters
// Read up to 2^13 pulses / polling period = 8MHz for 1kHz servo period
reg qtest;
wire [2*QW:0] quad0, quad1, quad2, quad3;
wire qr0, qr1, qr2, qr3;
//quad q0(clk, qtest ? real_dout[0] : quadA[0], qtest ? real_dout[1] : quadB[0], qtest ? real_dout[2] : quadZ[0]^Zpolarity, qr0, quad0);
quad q0(clk, quadA[0], quadB[0], quadZ[0]^Zpolarity, qr0, quad0);
quad q1(clk, quadA[1], quadB[1], quadZ[1]^Zpolarity, qr1, quad1);
quad q2(clk, quadA[2], quadB[2], quadZ[2]^Zpolarity, qr2, quad2);
quad q3(clk, quadA[3], quadB[3], quadZ[3]^Zpolarity, qr3, quad3);
//**********************************************************************
// SPI zeugs
// synchronizing the handshakes
//
reg [2:0] SCKr;
always @(posedge clk) SCKr <= {SCKr[1:0], SCK};
wire SCK_risingedge = (SCKr[2:1]==2'b01); // now we can detect SCK rising edges
wire SCK_fallingedge = (SCKr[2:1]==2'b10); // and falling edges
wire SCK_high = SCKr[1]; // SCK is high
// same thing for SSEL
reg [2:0] SSELr;
always @(posedge clk) SSELr <= {SSELr[1:0], SSEL};
wire SSEL_active = ~SSELr[1]; // SSEL is active low
wire SSEL_startmessage = (SSELr[2:1]==2'b10); // message starts at falling edge
wire SSEL_endmessage = (SSELr[2:1]==2'b01); // message stops at rising edge
wire MOSI_data = MOSI;
// we handle SPI in 8-bits format, so we need a 3 bits counter to count the bits as they come in
reg [2:0] bitcnt;
reg byte_received; // high when 8 bit has been received
reg [4:0] spibytecnt;
reg [7:0] data_recvd;
reg [7:0] data_sent;
reg [7:0] data_outbuf;
always @(posedge clk) begin
if(SSEL_startmessage) begin
//data_sent <= data_outbuf;
bitcnt <= 3'b000;
spibytecnt <= 5'b00000;
end
if(SSEL_active) begin
if(SCK_risingedge) begin
data_recvd <= {data_recvd[6:0], MOSI_data};
bitcnt <= bitcnt + 3'b001;
if(bitcnt==3'b000)
data_sent <= data_outbuf;
end
else if(SCK_fallingedge) begin
data_sent <= {data_sent[6:0], 1'b0};
if(bitcnt==3'b000) begin
spibytecnt <= spibytecnt + 5'b00001;
end
end
byte_received <= SCK_risingedge && (bitcnt==3'b111);
end
end
assign MISO = data_sent[7]; // send MSB first
// we assume that there is only one slave on the SPI bus
// so we don't bother with a tri-state buffer for MISO
// otherwise we would need to tri-state MISO when SSEL is inactive
reg [7:0] data_inbuf;
always @(posedge clk) begin
if(SSEL_active) begin
//------------------------------------------------- word 0
if(spibytecnt == 5'b00000) begin // 0
data_outbuf <= quad0[7:0];
if(byte_received)
data_inbuf <= data_recvd; //pwm0[7:0]
end
else if(spibytecnt == 5'b00001) begin // 1
data_outbuf <= quad0[15:8];
if(byte_received)
pwm0 <= {data_recvd,data_inbuf}; //pwm0
end
else if(spibytecnt == 5'b00010) begin // 2
data_outbuf <= quad0[23:16];
if(byte_received)
data_inbuf <= data_recvd; //pwm1[7:0]
end
else if(spibytecnt == 5'b00011) begin // 3
data_outbuf <= {4'b0, quad0[27:24]};
if(byte_received)
pwm1 <= {data_recvd,data_inbuf}; //pwm1
end
//------------------------------------------------- word 1
else if(spibytecnt == 5'b00100) begin // 4
data_outbuf <= quad1[7:0];
if(byte_received)
data_inbuf <= data_recvd; //pwm2[7:0]
end
else if(spibytecnt == 5'b00101) begin // 5
data_outbuf <= quad1[15:8];
if(byte_received)
pwm2 <= {data_recvd,data_inbuf}; //pwm2
end
else if(spibytecnt == 5'b00110) begin // 6
data_outbuf <= quad1[23:16];
if(byte_received)
data_inbuf <= data_recvd; //pwm3[7:0]
end
else if(spibytecnt == 5'b00111) begin // 7
data_outbuf <= {4'b0, quad1[27:24]};
if(byte_received)
pwm3 <= {data_recvd,data_inbuf}; //pwm3
end
//------------------------------------------------- word 2
else if(spibytecnt == 5'b01000) begin // 8
data_outbuf <= quad2[7:0];
if(byte_received)
data_inbuf <= data_recvd; //real_dout[7:0]
end
else if(spibytecnt == 5'b01001) begin // 9
data_outbuf <= quad2[15:8];
if(byte_received) begin
real_dout <= {data_recvd[1:0],data_inbuf}; //real_dout[9:8]
Zpolarity <= data_recvd[7]; //Zpolarity
qtest <= data_recvd[5]; //qtest
end
end
else if(spibytecnt == 5'b01010) data_outbuf <= quad2[23:16]; // 10
else if(spibytecnt == 5'b01011) data_outbuf <= {4'b0, quad2[27:24]}; // 11
//------------------------------------------------- word 3
else if(spibytecnt == 5'b01100) data_outbuf <= quad3[7:0];
else if(spibytecnt == 5'b01101) data_outbuf <= quad3[15:8];
else if(spibytecnt == 5'b01110) data_outbuf <= quad3[23:16];
else if(spibytecnt == 5'b01111) data_outbuf <= {4'b0, quad3[27:24]};
//------------------------------------------------- word 4
else if(spibytecnt == 5'b10000) data_outbuf <= din;
else if(spibytecnt == 5'b10001) data_outbuf <= {quadB, quadZ};
else if(spibytecnt == 5'b10010) data_outbuf <= {4'b0, quadA};
else if(spibytecnt == 5'b10011) data_outbuf <= 8'b0;
else data_outbuf <= spibytecnt;
end
end
assign LED = (real_up[0] ^ real_down[0]);
endmodule |
module opl3_cpu_wrapper
(DDR_addr,
DDR_ba,
DDR_cas_n,
DDR_ck_n,
DDR_ck_p,
DDR_cke,
DDR_cs_n,
DDR_dm,
DDR_dq,
DDR_dqs_n,
DDR_dqs_p,
DDR_odt,
DDR_ras_n,
DDR_reset_n,
DDR_we_n,
FIXED_IO_ddr_vrn,
FIXED_IO_ddr_vrp,
FIXED_IO_mio,
FIXED_IO_ps_clk,
FIXED_IO_ps_porb,
FIXED_IO_ps_srstb,
ac_mclk,
ac_mute_n,
clk125,
i2s_sclk,
i2s_sd,
i2s_ws,
iic_0_scl_io,
iic_0_sda_io,
led);
inout [14:0]DDR_addr;
inout [2:0]DDR_ba;
inout DDR_cas_n;
inout DDR_ck_n;
inout DDR_ck_p;
inout DDR_cke;
inout DDR_cs_n;
inout [3:0]DDR_dm;
inout [31:0]DDR_dq;
inout [3:0]DDR_dqs_n;
inout [3:0]DDR_dqs_p;
inout DDR_odt;
inout DDR_ras_n;
inout DDR_reset_n;
inout DDR_we_n;
inout FIXED_IO_ddr_vrn;
inout FIXED_IO_ddr_vrp;
inout [53:0]FIXED_IO_mio;
inout FIXED_IO_ps_clk;
inout FIXED_IO_ps_porb;
inout FIXED_IO_ps_srstb;
output ac_mclk;
output ac_mute_n;
input clk125;
output i2s_sclk;
output i2s_sd;
output i2s_ws;
inout iic_0_scl_io;
inout iic_0_sda_io;
output [3:0]led;
wire [14:0]DDR_addr;
wire [2:0]DDR_ba;
wire DDR_cas_n;
wire DDR_ck_n;
wire DDR_ck_p;
wire DDR_cke;
wire DDR_cs_n;
wire [3:0]DDR_dm;
wire [31:0]DDR_dq;
wire [3:0]DDR_dqs_n;
wire [3:0]DDR_dqs_p;
wire DDR_odt;
wire DDR_ras_n;
wire DDR_reset_n;
wire DDR_we_n;
wire FIXED_IO_ddr_vrn;
wire FIXED_IO_ddr_vrp;
wire [53:0]FIXED_IO_mio;
wire FIXED_IO_ps_clk;
wire FIXED_IO_ps_porb;
wire FIXED_IO_ps_srstb;
wire ac_mclk;
wire ac_mute_n;
wire clk125;
wire i2s_sclk;
wire i2s_sd;
wire i2s_ws;
wire iic_0_scl_i;
wire iic_0_scl_io;
wire iic_0_scl_o;
wire iic_0_scl_t;
wire iic_0_sda_i;
wire iic_0_sda_io;
wire iic_0_sda_o;
wire iic_0_sda_t;
wire [3:0]led;
IOBUF iic_0_scl_iobuf
(.I(iic_0_scl_o),
.IO(iic_0_scl_io),
.O(iic_0_scl_i),
.T(iic_0_scl_t));
IOBUF iic_0_sda_iobuf
(.I(iic_0_sda_o),
.IO(iic_0_sda_io),
.O(iic_0_sda_i),
.T(iic_0_sda_t));
opl3_cpu opl3_cpu_i
(.DDR_addr(DDR_addr),
.DDR_ba(DDR_ba),
.DDR_cas_n(DDR_cas_n),
.DDR_ck_n(DDR_ck_n),
.DDR_ck_p(DDR_ck_p),
.DDR_cke(DDR_cke),
.DDR_cs_n(DDR_cs_n),
.DDR_dm(DDR_dm),
.DDR_dq(DDR_dq),
.DDR_dqs_n(DDR_dqs_n),
.DDR_dqs_p(DDR_dqs_p),
.DDR_odt(DDR_odt),
.DDR_ras_n(DDR_ras_n),
.DDR_reset_n(DDR_reset_n),
.DDR_we_n(DDR_we_n),
.FIXED_IO_ddr_vrn(FIXED_IO_ddr_vrn),
.FIXED_IO_ddr_vrp(FIXED_IO_ddr_vrp),
.FIXED_IO_mio(FIXED_IO_mio),
.FIXED_IO_ps_clk(FIXED_IO_ps_clk),
.FIXED_IO_ps_porb(FIXED_IO_ps_porb),
.FIXED_IO_ps_srstb(FIXED_IO_ps_srstb),
.IIC_0_scl_i(iic_0_scl_i),
.IIC_0_scl_o(iic_0_scl_o),
.IIC_0_scl_t(iic_0_scl_t),
.IIC_0_sda_i(iic_0_sda_i),
.IIC_0_sda_o(iic_0_sda_o),
.IIC_0_sda_t(iic_0_sda_t),
.ac_mclk(ac_mclk),
.ac_mute_n(ac_mute_n),
.clk125(clk125),
.i2s_sclk(i2s_sclk),
.i2s_sd(i2s_sd),
.i2s_ws(i2s_ws),
.led(led));
endmodule |
module sky130_fd_sc_hdll__udp_dlatch$P (
Q ,
D ,
GATE
);
output Q ;
input D ;
input GATE;
endmodule |
module jt51_phrom
(
input [4:0] addr,
input clk,
output reg [45:0] ph
);
reg [45:0] sinetable[31:0];
initial
begin
sinetable[5'd0 ] = 46'b0001100000100100010001000010101010101001010010;
sinetable[5'd1 ] = 46'b0001100000110100000100000010010001001101000001;
sinetable[5'd2 ] = 46'b0001100000110100000100110010001011001101100000;
sinetable[5'd3 ] = 46'b0001110000010000000000110010110001001101110010;
sinetable[5'd4 ] = 46'b0001110000010000001100000010111010001101101001;
sinetable[5'd5 ] = 46'b0001110000010100001001100010000000101101111010;
sinetable[5'd6 ] = 46'b0001110000010100001101100010010011001101011010;
sinetable[5'd7 ] = 46'b0001110000011100000101010010111000101111111100;
sinetable[5'd8 ] = 46'b0001110000111000000001110010101110001101110111;
sinetable[5'd9 ] = 46'b0001110000111000010100111000011101011010100110;
sinetable[5'd10] = 46'b0001110000111100011000011000111100001001111010;
sinetable[5'd11] = 46'b0001110000111100011100111001101011001001110111;
sinetable[5'd12] = 46'b0100100001010000010001011001001000111010110111;
sinetable[5'd13] = 46'b0100100001010100010001001001110001111100101010;
sinetable[5'd14] = 46'b0100100001010100010101101101111110100101000110;
sinetable[5'd15] = 46'b0100100011100000001000011001010110101101111001;
sinetable[5'd16] = 46'b0100100011100100001000101011100101001011101111;
sinetable[5'd17] = 46'b0100100011101100000111011010000001011010110001;
sinetable[5'd18] = 46'b0100110011001000000111101010000010111010111111;
sinetable[5'd19] = 46'b0100110011001100001011011110101110110110000001;
sinetable[5'd20] = 46'b0100110011101000011010111011001010001101110001;
sinetable[5'd21] = 46'b0100110011101101011010110101111001010100001111;
sinetable[5'd22] = 46'b0111000010000001010111000101010101010110010111;
sinetable[5'd23] = 46'b0111000010000101010111110111110101010010111011;
sinetable[5'd24] = 46'b0111000010110101101000101100001000010000011001;
sinetable[5'd25] = 46'b0111010010011001100100011110100100010010010010;
sinetable[5'd26] = 46'b0111010010111010100101100101000000110100100011;
sinetable[5'd27] = 46'b1010000010011010101101011101100001110010011010;
sinetable[5'd28] = 46'b1010000010111111111100100111010100010000111001;
sinetable[5'd29] = 46'b1010010111110100110010001100111001010110100000;
sinetable[5'd30] = 46'b1011010111010011111011011110000100110010100001;
sinetable[5'd31] = 46'b1110011011110001111011100111100001110110100111;
end
always @ (posedge clk)
ph <= sinetable[addr];
endmodule |
module sky130_fd_sc_hd__tapvgnd2 ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule |
module
input [DATA_WIDTH-1:0] in_data;
input [CTRL_WIDTH-1:0] in_ctrl;
output in_rdy;
input in_wr;
// --- Register interface
input reg_req_in;
input reg_ack_in;
input reg_rd_wr_L_in;
input [`UDP_REG_ADDR_WIDTH-1:0] reg_addr_in;
input [`CPCI_NF2_DATA_WIDTH-1:0] reg_data_in;
input [UDP_REG_SRC_WIDTH-1:0] reg_src_in;
output reg_req_out;
output reg_ack_out;
output reg_rd_wr_L_out;
output [`UDP_REG_ADDR_WIDTH-1:0] reg_addr_out;
output [`CPCI_NF2_DATA_WIDTH-1:0] reg_data_out;
output [UDP_REG_SRC_WIDTH-1:0] reg_src_out;
// --- SRAM sm interface
output [SRAM_ADDR_WIDTH-1:0] wr_0_addr;
output wr_0_req;
input wr_0_ack;
output [DATA_WIDTH+CTRL_WIDTH-1:0] wr_0_data;
input rd_0_ack;
input [DATA_WIDTH+CTRL_WIDTH-1:0] rd_0_data;
input rd_0_vld;
output [SRAM_ADDR_WIDTH-1:0] rd_0_addr;
output rd_0_req;
// --- Misc
input clk;
input reset;
function integer log2;
input integer number;
begin
log2=0;
while(2**log2<number) begin
log2=log2+1;
end
end
endfunction // log2
//------------- Internal Parameters ---------------
parameter NUM_OQ_WIDTH = log2(NUM_OUTPUT_QUEUES);
parameter PKT_LEN_WIDTH = 11;
parameter PKT_WORDS_WIDTH = PKT_LEN_WIDTH-log2(CTRL_WIDTH);
parameter MAX_PKT = 2048; // allow for 2K bytes
parameter PKT_BYTE_CNT_WIDTH = log2(MAX_PKT);
parameter PKT_WORD_CNT_WIDTH = log2(MAX_PKT/CTRL_WIDTH);
//--------------- Regs/Wires ----------------------
wire [SRAM_ADDR_WIDTH-1:0] src_oq_rd_addr;
wire [SRAM_ADDR_WIDTH-1:0] src_oq_high_addr;
wire [SRAM_ADDR_WIDTH-1:0] src_oq_low_addr;
wire [NUM_OUTPUT_QUEUES-1:0]src_oq_empty;
wire [SRAM_ADDR_WIDTH-1:0] src_oq_rd_addr_new;
wire pkt_removed;
wire [PKT_LEN_WIDTH-1:0] removed_pkt_data_length;
wire [CTRL_WIDTH-1:0] removed_pkt_overhead_length;
wire [PKT_WORDS_WIDTH-1:0] removed_pkt_total_word_length;
wire [NUM_OQ_WIDTH-1:0] src_oq;
wire [NUM_OQ_WIDTH-1:0] removed_oq;
wire rd_src_addr;
wire [NUM_OUTPUT_QUEUES-1:0] enable_send_pkt;
wire dst_oq_avail;
wire [NUM_OQ_WIDTH-1:0] parsed_dst_oq;
wire [PKT_BYTE_CNT_WIDTH-1:0] parsed_pkt_byte_len;
wire [PKT_WORD_CNT_WIDTH-1:0] parsed_pkt_word_len;
wire rd_dst_oq;
wire [SRAM_ADDR_WIDTH-1:0] dst_oq_wr_addr_new;
wire pkt_stored;
wire pkt_dropped;
wire [PKT_LEN_WIDTH-1:0] stored_pkt_data_length;
wire [CTRL_WIDTH-1:0] stored_pkt_overhead_length;
wire [PKT_WORDS_WIDTH-1:0] stored_pkt_total_word_length;
wire [NUM_OQ_WIDTH-1:0] dst_oq;
wire rd_dst_addr;
wire [SRAM_ADDR_WIDTH-1:0] dst_oq_high_addr;
wire [SRAM_ADDR_WIDTH-1:0] dst_oq_low_addr;
wire [SRAM_ADDR_WIDTH-1:0] dst_oq_wr_addr;
wire [NUM_OUTPUT_QUEUES-1:0]dst_oq_full;
wire input_fifo_rd_en;
wire input_fifo_empty;
wire [DATA_WIDTH-1:0] input_fifo_data_out;
wire [CTRL_WIDTH-1:0] input_fifo_ctrl_out;
wire input_fifo_nearly_full;
//---------------- Modules ------------------------
oq_header_parser
#(.DATA_WIDTH(DATA_WIDTH),
.CTRL_WIDTH(CTRL_WIDTH),
.OP_LUT_STAGE_NUM(OP_LUT_STAGE_NUM),
.NUM_OUTPUT_QUEUES(NUM_OUTPUT_QUEUES))
oq_header_parser
(
.parsed_dst_oq (parsed_dst_oq),
.parsed_pkt_byte_len (parsed_pkt_byte_len),
.parsed_pkt_word_len (parsed_pkt_word_len),
.header_parser_rdy (header_parser_rdy),
.dst_oq_avail (dst_oq_avail),
.rd_dst_oq (rd_dst_oq),
.in_wr (in_wr),
.in_ctrl (in_ctrl),
.in_data (in_data),
.clk (clk),
.reset (reset));
fallthrough_small_fifo
#(.WIDTH(DATA_WIDTH+CTRL_WIDTH),
.MAX_DEPTH_BITS(3))
input_fifo
(.dout({input_fifo_ctrl_out, input_fifo_data_out}),
.full(),
.prog_full (),
.nearly_full(input_fifo_nearly_full),
.empty(input_fifo_empty),
.din({in_ctrl, in_data}),
.wr_en(in_wr),
.rd_en(input_fifo_rd_en),
.reset(reset),
.clk(clk));
store_pkt
#(.DATA_WIDTH(DATA_WIDTH),
.CTRL_WIDTH(CTRL_WIDTH),
.NUM_OUTPUT_QUEUES(NUM_OUTPUT_QUEUES),
.SRAM_ADDR_WIDTH(SRAM_ADDR_WIDTH),
.OQ_STAGE_NUM (STAGE_NUM),
.PKT_LEN_WIDTH(PKT_LEN_WIDTH))
store_pkt
( // --- Interface to header_parser
.dst_oq_avail (dst_oq_avail),
.parsed_dst_oq (parsed_dst_oq),
.parsed_pkt_byte_len (parsed_pkt_byte_len),
.parsed_pkt_word_len (parsed_pkt_word_len),
.rd_dst_oq (rd_dst_oq),
// --- Interface to registers
.dst_oq_wr_addr_new (dst_oq_wr_addr_new),
.pkt_stored (pkt_stored),
.pkt_dropped (pkt_dropped),
.stored_pkt_data_length (stored_pkt_data_length),
.stored_pkt_overhead_length (stored_pkt_overhead_length),
.stored_pkt_total_word_length (stored_pkt_total_word_length),
.dst_oq (dst_oq),
.rd_dst_addr (rd_dst_addr),
.dst_oq_high_addr (dst_oq_high_addr),
.dst_oq_low_addr (dst_oq_low_addr),
.dst_oq_wr_addr (dst_oq_wr_addr),
.dst_oq_full (dst_oq_full),
// --- Interface to SRAM
.wr_0_addr (wr_0_addr),
.wr_0_req (wr_0_req),
.wr_0_ack (wr_0_ack),
.wr_0_data (wr_0_data),
// --- Interface to input fifo
.input_fifo_rd_en (input_fifo_rd_en),
.input_fifo_empty (input_fifo_empty),
.input_fifo_data_out (input_fifo_data_out),
.input_fifo_ctrl_out (input_fifo_ctrl_out),
// --- misc
.clk (clk),
.reset (reset));
remove_pkt
#(.DATA_WIDTH(DATA_WIDTH),
.CTRL_WIDTH(CTRL_WIDTH),
.NUM_OUTPUT_QUEUES(NUM_OUTPUT_QUEUES),
.SRAM_ADDR_WIDTH(SRAM_ADDR_WIDTH),
.OQ_STAGE_NUM (STAGE_NUM),
.OP_LUT_STAGE_NUM(OP_LUT_STAGE_NUM),
.PKT_LEN_WIDTH(PKT_LEN_WIDTH))
remove_pkt
(// --- Interface to SRAM
.rd_0_ack (rd_0_ack),
.rd_0_data (rd_0_data),
.rd_0_vld (rd_0_vld),
.rd_0_addr (rd_0_addr),
.rd_0_req (rd_0_req),
// --- Interface to regs
.src_oq_rd_addr (src_oq_rd_addr),
.src_oq_high_addr (src_oq_high_addr),
.src_oq_low_addr (src_oq_low_addr),
.src_oq_empty (src_oq_empty),
.src_oq_rd_addr_new (src_oq_rd_addr_new),
.pkt_removed (pkt_removed),
.removed_pkt_data_length (removed_pkt_data_length),
.removed_pkt_overhead_length (removed_pkt_overhead_length),
.removed_pkt_total_word_length (removed_pkt_total_word_length),
.src_oq (src_oq),
.removed_oq (removed_oq),
.rd_src_addr (rd_src_addr),
.enable_send_pkt (enable_send_pkt),
// --- Interface to datapath
.out_data_0 (out_data_0),
.out_ctrl_0 (out_ctrl_0),
.out_wr_0 (out_wr_0),
.out_rdy_0 (out_rdy_0),
.out_data_1 (out_data_1),
.out_ctrl_1 (out_ctrl_1),
.out_wr_1 (out_wr_1),
.out_rdy_1 (out_rdy_1),
.out_data_2 (out_data_2),
.out_ctrl_2 (out_ctrl_2),
.out_wr_2 (out_wr_2),
.out_rdy_2 (out_rdy_2),
.out_data_3 (out_data_3),
.out_ctrl_3 (out_ctrl_3),
.out_wr_3 (out_wr_3),
.out_rdy_3 (out_rdy_3),
.out_data_4 (out_data_4),
.out_ctrl_4 (out_ctrl_4),
.out_wr_4 (out_wr_4),
.out_rdy_4 (out_rdy_4),
.out_data_5 (out_data_5),
.out_ctrl_5 (out_ctrl_5),
.out_wr_5 (out_wr_5),
.out_rdy_5 (out_rdy_5),
.out_data_6 (out_data_6),
.out_ctrl_6 (out_ctrl_6),
.out_wr_6 (out_wr_6),
.out_rdy_6 (out_rdy_6),
.out_data_7 (out_data_7),
.out_ctrl_7 (out_ctrl_7),
.out_wr_7 (out_wr_7),
.out_rdy_7 (out_rdy_7),
// --- Misc
.clk (clk),
.reset (reset));
oq_regs
#(
.SRAM_ADDR_WIDTH(SRAM_ADDR_WIDTH),
.CTRL_WIDTH(CTRL_WIDTH),
.UDP_REG_SRC_WIDTH (UDP_REG_SRC_WIDTH),
.NUM_OUTPUT_QUEUES(NUM_OUTPUT_QUEUES),
.PKT_LEN_WIDTH(PKT_LEN_WIDTH))
oq_regs
(// --- interface to udp_reg_grp
.reg_req_in (reg_req_in),
.reg_ack_in (reg_ack_in),
.reg_rd_wr_L_in (reg_rd_wr_L_in),
.reg_addr_in (reg_addr_in),
.reg_data_in (reg_data_in),
.reg_src_in (reg_src_in),
.reg_req_out (reg_req_out),
.reg_ack_out (reg_ack_out),
.reg_rd_wr_L_out (reg_rd_wr_L_out),
.reg_addr_out (reg_addr_out),
.reg_data_out (reg_data_out),
.reg_src_out (reg_src_out),
// --- interface to remove_pkt
.src_oq_rd_addr (src_oq_rd_addr),
.src_oq_high_addr (src_oq_high_addr),
.src_oq_low_addr (src_oq_low_addr),
.src_oq_empty (src_oq_empty),
.src_oq_rd_addr_new (src_oq_rd_addr_new),
.pkt_removed (pkt_removed),
.removed_pkt_data_length (removed_pkt_data_length),
.removed_pkt_overhead_length (removed_pkt_overhead_length),
.removed_pkt_total_word_length (removed_pkt_total_word_length),
.src_oq (src_oq),
.removed_oq (removed_oq),
.rd_src_addr (rd_src_addr),
.enable_send_pkt (enable_send_pkt),
// --- interface to store_pkt
.dst_oq_wr_addr_new (dst_oq_wr_addr_new),
.pkt_stored (pkt_stored),
.stored_pkt_data_length (stored_pkt_data_length),
.stored_pkt_overhead_length (stored_pkt_overhead_length),
.stored_pkt_total_word_length (stored_pkt_total_word_length),
.pkt_dropped (pkt_dropped),
.dst_oq (dst_oq),
.rd_dst_addr (rd_dst_addr),
.dst_oq_high_addr (dst_oq_high_addr),
.dst_oq_low_addr (dst_oq_low_addr),
.dst_oq_wr_addr (dst_oq_wr_addr),
.dst_oq_full (dst_oq_full),
// --- Misc
.clk (clk),
.reset (reset));
//------------------ Logic ------------------------
assign in_rdy = header_parser_rdy && !input_fifo_nearly_full;
endmodule |
module sky130_fd_sc_hs__inv_8 (
Y ,
A ,
VPWR,
VGND
);
output Y ;
input A ;
input VPWR;
input VGND;
sky130_fd_sc_hs__inv base (
.Y(Y),
.A(A),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule |
module sky130_fd_sc_hs__inv_8 (
Y,
A
);
output Y;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__inv base (
.Y(Y),
.A(A)
);
endmodule |
module sump2 #
(
parameter depth_len = 1024,
parameter depth_bits = 10,
parameter event_bytes = 4,
parameter data_dwords = 16,
parameter nonrle_en = 1,
parameter rle_en = 1,
parameter data_en = 1,
parameter pattern_en = 1,
parameter trigger_nth_en = 1,
parameter trigger_dly_en = 1,
parameter trigger_wd_en = 1,
parameter deep_sump_en = 0,
parameter freq_mhz = 16'd80,
parameter freq_fracts = 16'h0000,
parameter sump_id = 16'hABBA,
parameter sump_rev = 8'h02
)
(
input wire reset,
input wire clk_cap,
input wire clk_lb,
input wire lb_cs_ctrl,
input wire lb_cs_data,
input wire lb_wr,
input wire lb_rd,
input wire [31:0] lb_wr_d,
output reg [31:0] lb_rd_d,
output reg lb_rd_rdy,
output reg active,
output wire [31:0] user_ctrl,
output wire [31:0] user_pat0,
output wire [31:0] user_pat1,
input wire trigger_in,
output reg trigger_out,
output reg ds_trigger,
output reg [31:0] ds_events,
output wire [31:0] ds_user_ctrl,
output reg [5:0] ds_cmd_lb,
output reg [5:0] ds_cmd_cap,
output reg ds_rd_req,
output reg ds_wr_req,
output reg [31:0] ds_wr_d,
input wire [31:0] ds_rd_d,
input wire ds_rd_rdy,
input wire ds_rle_pre_done,
input wire ds_rle_post_done,
input wire [31:0] events_din,
input wire [127:0] dwords_3_0,
input wire [127:0] dwords_7_4,
input wire [127:0] dwords_11_8,
input wire [127:0] dwords_15_12
);
wire reset_loc;
wire [15:0] zeros;
wire [15:0] ones;
wire [7:0] cap_status;
wire [5:0] ctrl_cmd;
reg [5:0] ctrl_cmd_loc;
reg ctrl_cmd_xfer;
wire [4:0] ctrl_rd_page;
wire [15:0] ctrl_rd_ptr;
reg [5:0] ctrl_reg;
reg [31:0] events_loc;
reg trigger_loc;
reg trigger_or;
reg trigger_or_p1;
reg trigger_and;
reg trigger_and_p1;
reg trigger_pat;
reg trigger_pat_p1;
reg xfer_clr;
reg rd_inc;
reg armed_jk;
reg triggered_jk;
reg acquired_jk;
reg complete_jk;
reg [31:0] ctrl_04_reg;
reg [31:0] ctrl_05_reg;
reg [31:0] ctrl_06_reg;
reg [31:0] ctrl_07_reg;
reg [31:0] ctrl_08_reg;
reg [31:0] ctrl_09_reg;
reg [31:0] ctrl_0a_reg;
reg [31:0] ctrl_0b_reg;
reg [31:0] ctrl_10_reg;
reg [31:0] ctrl_11_reg;
reg [31:0] ctrl_12_reg;
reg [31:0] ctrl_13_reg;
reg [31:0] ctrl_14_reg;
reg [31:0] ctrl_1d_reg;
wire [31:0] watchdog_reg;
reg [31:0] watchdog_cnt;
reg wd_armed_jk;
reg trigger_wd;
wire [31:0] trigger_bits;
wire [3:0] trigger_type;
wire [31:0] trigger_pos;
wire [15:0] trigger_nth;
wire [15:0] trigger_delay;
reg [15:0] trigger_dly_cnt;
wire [31:0] rle_event_en;
reg [15:0] trigger_cnt;
reg [31:0] ram_rd_d;
reg [depth_bits-1:0] post_trig_cnt;
reg [depth_bits-1:0] trigger_ptr;
reg trigger_in_meta;
reg trigger_in_p1;
reg trigger_in_p2;
wire [31:0] pat0;
wire [31:0] pat1;
// Variable Size Capture BRAM
reg [31:0] event_ram_array[depth_len-1:0];
reg [127:0] dwords_3_0_ram_array[depth_len-1:0];
reg [127:0] dwords_7_4_ram_array[depth_len-1:0];
reg [127:0] dwords_11_8_ram_array[depth_len-1:0];
reg [127:0] dwords_15_12_ram_array[depth_len-1:0];
reg [127:0] dwords_3_0_p1;
reg [127:0] dwords_7_4_p1;
reg [127:0] dwords_11_8_p1;
reg [127:0] dwords_15_12_p1;
reg [127:0] dwords_3_0_p2;
reg [127:0] dwords_7_4_p2;
reg [127:0] dwords_11_8_p2;
reg [127:0] dwords_15_12_p2;
reg [127:0] dwords_3_0_do;
reg [127:0] dwords_7_4_do;
reg [127:0] dwords_11_8_do;
reg [127:0] dwords_15_12_do;
reg [depth_bits-1:0] c_addr;
reg [depth_bits-1:0] c_addr_p1;
reg c_we;
reg c_we_p1;
wire [31:0] c_di;
reg [31:0] c_di_p1;
reg [depth_bits-1:0] d_addr;
reg [31:0] d_do;
reg [63:0] rle_ram_array[depth_len-1:0];
reg [depth_bits-1:0] a_addr;
reg [depth_bits-1:0] a_addr_p1;
reg a_we;
reg a_we_p1;
reg [63:0] a_di;
reg [63:0] a_di_p1;
reg [depth_bits-1:0] b_addr;
reg [63:0] b_do;
wire [31:0] data_en_bits;
reg data_en_loc;
reg data_en_loc_p1;
reg [31:0] events_pre;
reg [31:0] events_p1;
reg [31:0] events_p2;
reg [31:0] rle_time;
reg [31:0] rle_time_p1;
reg rle_wd_sample;
reg rle_pre_jk;
reg rle_done_jk;
reg rle_done_loc;
reg rle_pre_done_loc;
wire [7:0] data_4x_dwords;
assign zeros = 16'd0;
assign ones = 16'hFFFF;
assign reset_loc = reset;
//assign cap_status = { rle_en, 1'b0, rle_done_loc, ~rle_pre_jk,
assign cap_status = { rle_en, 1'b0, rle_done_loc, rle_pre_done_loc,
complete_jk, acquired_jk, triggered_jk, armed_jk };
//-----------------------------------------------------------------------------
// Flop the input events and support reduction for much smaller designs.
//-----------------------------------------------------------------------------
always @ ( posedge clk_cap ) begin : proc_done
rle_done_loc <= rle_done_jk && ( deep_sump_en==0 || ds_rle_post_done==1);
rle_pre_done_loc <= ~rle_pre_jk && ( deep_sump_en==0 || ds_rle_pre_done==1);
end // proc_din
//-----------------------------------------------------------------------------
// Flop the input events and support reduction for much smaller designs.
//-----------------------------------------------------------------------------
always @ ( posedge clk_cap ) begin : proc_din
if ( event_bytes == 1 ) begin
events_loc <= { 24'd0, events_din[7:0] };
end else if ( event_bytes == 2 ) begin
events_loc <= { 16'd0, events_din[15:0] };
end else if ( event_bytes == 3 ) begin
events_loc <= { 8'd0, events_din[23:0] };
end else begin
events_loc <= { events_din[31:0] };
end
if ( rle_en == 1 ) begin
events_pre <= events_loc[31:0] & rle_event_en[31:0];
events_p1 <= events_pre[31:0];
events_p2 <= events_p1[31:0];
end
end // proc_din
//-----------------------------------------------------------------------------
// Capture Logic. When armed, capture in a continuous loop until trigger is
// detected and then capture N/2 samples more.
// Note: Software Must go from Idle to Arm to clear the JKs.
//-----------------------------------------------------------------------------
always @ ( * ) begin : proc_data_en
if ( data_en_bits == 32'h00000000 || data_en == 0 ||
( data_en_bits[31:0] & events_din[31:0] ) != 32'h00000000 ) begin
data_en_loc <= 1;// Capture sample in time
end else begin
data_en_loc <= 0;// Prevent sample capture
end
end // proc_data_en
//-----------------------------------------------------------------------------
// Capture Logic. When armed, capture in a continuous loop until trigger is
// detected and then capture N/2 samples more.
// Note: Software Must go from Idle to Arm to clear the JKs.
//-----------------------------------------------------------------------------
integer i;
always @ ( posedge clk_cap ) begin : proc_trig
trigger_in_meta <= trigger_in;
trigger_in_p1 <= trigger_in_meta;
trigger_in_p2 <= trigger_in_p1;
trigger_or <= 0;
trigger_and <= 0;
trigger_pat <= 0;
trigger_or_p1 <= trigger_or;
trigger_and_p1 <= trigger_and;
trigger_pat_p1 <= trigger_pat;
data_en_loc_p1 <= data_en_loc;
for ( i = 0; i <= 31; i=i+1 ) begin
if ( trigger_bits[i] == 1 && events_loc[i] == 1 ) begin
trigger_or <= 1;// This is a 32bit OR
end
end
if ( ( events_loc[31:0] & trigger_bits[31:0] ) == trigger_bits[31:0] ) begin
trigger_and <= 1;
end
if (
(( events_loc[31:0] & pat0[31:0] ) ^
( pat1[31:0] & pat0[31:0] ) ) == 32'h00000000 ) begin
if ( pattern_en == 1 ) begin
trigger_pat <= 1;// Exact 32bit Pattern Match
end
end
end // proc_trig
//-----------------------------------------------------------------------------
// Capture Logic. When armed, capture in a continuous loop until trigger is
// detected and then capture N/2 samples more.
// Note: Software Must go from Idle to Arm to clear the JKs.
//-----------------------------------------------------------------------------
always @ ( posedge clk_cap ) begin : proc_cap
c_we <= 0;
trigger_out <= 0;
trigger_loc <= 0;
trigger_wd <= 0;
active <= 0;
ds_trigger <= 0;
ds_events <= events_p1[31:0];
// CMD_ARM
if ( ctrl_cmd_loc == 6'h01 ) begin
active <= 1;
// Watchdog gets armed on 1st kick. Every kick after clears count.
// If count expires, assert trigger_wd.
if ( trigger_wd_en == 1 && ( trigger_or != trigger_or_p1 ) ) begin
wd_armed_jk <= 1;
end
if ( wd_armed_jk == 0 || ( trigger_or != trigger_or_p1 ) ) begin
watchdog_cnt <= 32'd0;
trigger_wd <= 0;
end else begin
watchdog_cnt <= watchdog_cnt[31:0] + 1;
if ( watchdog_cnt == watchdog_reg[31:0] ) begin
trigger_wd <= 1;
wd_armed_jk <= 0;
end
end
if ( triggered_jk == 0 && acquired_jk == 0 ) begin
// PreTrigger Acquire
armed_jk <= 1;
if ( data_en_loc == 1 || data_en_loc_p1 == 1 ) begin
c_we <= 1;
c_addr <= c_addr + 1;
end
if ( trigger_dly_cnt != 16'hFFFF ) begin
trigger_dly_cnt <= trigger_dly_cnt + 1;
end
if ( ( trigger_type==4'h0 && trigger_and==1 && trigger_and_p1==0 ) ||
( trigger_type==4'h1 && trigger_and==0 && trigger_and_p1==1 ) ||
( trigger_type==4'h2 && trigger_or ==1 && trigger_or_p1 ==0 ) ||
( trigger_type==4'h3 && trigger_or ==0 && trigger_or_p1 ==1 ) ||
( trigger_type==4'h4 && trigger_pat==1 && trigger_pat_p1==0 ) ||
( trigger_type==4'h5 && trigger_pat==0 && trigger_pat_p1==1 ) ||
( trigger_type==4'h6 && trigger_in_p1 ==1 && trigger_in_p2 ==0 ) ||
( trigger_type==4'h7 && trigger_in_p1 ==0 && trigger_in_p2 ==1 ) ||
( trigger_type==4'h8 && trigger_wd == 1 )
) begin
if ( trigger_dly_cnt == 16'hFFFF || trigger_dly_en==0 ) begin
trigger_dly_cnt <= 16'd0;
trigger_loc <= 1;// Only used if trigger delay is removed
c_we <= 1;// Store Trigger even if data_en_loc == 0
c_addr <= c_addr + 1;
end
end
// Don't allow trigger until pre-trig buffer is full
// If there is a deep_sump block, wait for it as well.
// if ( complete_jk == 1 ) begin
if ( complete_jk == 1 && ( deep_sump_en==0 || ds_rle_pre_done==1) ) begin
if ( ( trigger_dly_cnt == trigger_delay[15:0] ) ||
( trigger_dly_en==0 && trigger_loc == 1 ) ) begin
trigger_dly_cnt <= 16'hFFFF;
if ( trigger_cnt == trigger_nth[15:0] || trigger_nth_en==0 ) begin
armed_jk <= 0;
trigger_ptr <= c_addr[depth_bits-1:0];
trigger_out <= 1;
triggered_jk <= 1;
ds_trigger <= 1;
end
trigger_cnt <= trigger_cnt + 1;
end
end
end else if ( triggered_jk == 1 && acquired_jk == 0 ) begin
// PostTrigger Acquire
trigger_out <= 1;
if ( data_en_loc == 1 || data_en_loc_p1 == 1 ) begin
c_we <= 1;
c_addr <= c_addr + 1;
post_trig_cnt <= post_trig_cnt + 1;
end
if ( post_trig_cnt == trigger_pos[depth_bits-1:0] ) begin
acquired_jk <= 1;
c_we <= 0;
end
end
// If RAM has rolled, then pre-trigger buffer is full. Assert status bit.
// If RAM hasn't rolled, then pre-trigger samples start at 0x0.
if ( c_addr[depth_bits-1] == 0 && c_addr_p1[depth_bits-1] == 1 ) begin
complete_jk <= 1;
end
// CMD_RESET
end else if ( ctrl_cmd_loc == 6'h02 ) begin
c_addr <= zeros[depth_bits-1:0];
post_trig_cnt <= zeros[depth_bits-1:0];
post_trig_cnt[1:0] <= 2'b11;// Subtracts 3 from trigger_pos for alignment
trigger_cnt <= 16'd1;
trigger_dly_cnt <= 16'hFFFF;
armed_jk <= 0;
triggered_jk <= 0;
acquired_jk <= 0;
complete_jk <= 0;
wd_armed_jk <= 0;
end
// Cleanly xfer clock domains
xfer_clr <= 0;
if ( ctrl_cmd_xfer == 1 ) begin
ctrl_cmd_loc <= ctrl_cmd[5:0];
xfer_clr <= 1;
end
ds_cmd_cap <= ctrl_cmd_loc[5:0];
end // proc_cap
assign c_di = events_loc[31:0];
//-----------------------------------------------------------------------------
// RLE Capture Logic. This captures and stores event changes along with
// time stamps to a x64 BRAM. 1st half of RAM is any pre-trigger activity.
// 2nd half of RAM is post-trigger activity. Pre-trig is circular and must
// be unrolled by software in correct order. Enabling RLE block is optional.
//-----------------------------------------------------------------------------
always @ ( posedge clk_cap ) begin : proc_rle
a_we <= 0;
rle_time_p1 <= rle_time[31:0];
// Prevent RLE from hanging in cases where no activity happens after the
// trigger event by storing a non-changing sample periodically every
// 2^24 clock cycles ( about 100ms at 100 MHz )
rle_wd_sample <= rle_time[15] & ~ rle_time_p1[15];
// CMD_ARM
if ( ctrl_cmd_loc == 6'h01 ) begin
rle_time <= rle_time[31:0] + 1;
if ( triggered_jk == 0 ) begin
a_addr[depth_bits-1] <= 0;// Pre-Trigger Half
// If the prebuffer is invalid, store everything, change or no change
// as to immediately fill up RAM with valid samples
// Once prebuffer is valid, only store event deltas ( RLE )
if ( rle_pre_jk == 1 || rle_wd_sample == 1 ||
( events_p1 != events_p2[31:0] ) ) begin
a_we <= 1;
a_addr[depth_bits-2:0] <= a_addr[depth_bits-2:0] + 1;
if ( a_addr[depth_bits-2:0] == ones[depth_bits-2:0] ) begin
rle_pre_jk <= 0;// PreBuffer is completely valid - and rolling
end
end
end else if ( triggered_jk == 1 && rle_done_jk == 0 ) begin
if ( ( events_p1 != events_p2[31:0] ) || ( rle_wd_sample == 1) ) begin
a_we <= 1;
a_addr[depth_bits-2:0] <= a_addr[depth_bits-2:0] + 1;
// If previous write was to last address in RAM, then call it quits
if ( a_addr[depth_bits-2:0] == ones[depth_bits-2:0] ) begin
rle_done_jk <= 1;// Post-Trig RAM is full
a_we <= 0;
a_addr[depth_bits-2:0] <= a_addr[depth_bits-2:0];
end
// If previous cycle was pre-trig, set address to start of post trig
if ( a_addr[depth_bits-1] == 0 ) begin
a_addr[depth_bits-1] <= 1;// Post-Trigger Half
a_addr[depth_bits-2:0] <= zeros[depth_bits-2:0];
end
end
end
// CMD_RESET
end else if ( ctrl_cmd_loc == 6'h02 ) begin
rle_time <= 32'd0;// 43 seconds at 100 MHz
a_addr <= zeros[depth_bits-1:0];
rle_pre_jk <= 1;
rle_done_jk <= 0;
end
a_di[31:0] <= events_p1[31:0];
a_di[63:32] <= rle_time[31:0];
end // proc_rle
//-----------------------------------------------------------------------------
// Create write/read bus interface to the sump2_deep block
// 0x18 : Read Deep-RAM Width+Length
// 0x19 : Read Deep-RAM Trigger Location + Status
// 0x1a : Read Deep-RAM Data ( address auto incrementing )
// 0x1b : Load Deep-RAM Read Pointer
// 0x1c : Load Deep-RAM Read Page
// 0x1d : Load Deep-Sump User Control
// 0x1e : Load Deep-Sump User Mask
// 0x1f : Load Deep-Sump User Config
// Note: ds_user_ctrl is decoded locally here as it may be used to switch
// between multiple deep_sump.v instances, for example one may use fast
// on chip BRAM and another might use slower external DRAM. A user may
// decide to mux between the two with a ds_user_ctrl bit.
//-----------------------------------------------------------------------------
always @ ( posedge clk_lb ) begin : proc_lb_ds
ds_wr_req <= 0;
ds_rd_req <= 0;
if ( lb_wr == 1 && lb_cs_data == 1 ) begin
if ( ctrl_cmd[5:0] == 6'h1b ||
ctrl_cmd[5:0] == 6'h1c ||
ctrl_cmd[5:0] == 6'h1e ||
ctrl_cmd[5:0] == 6'h1f ) begin
ds_wr_req <= 1;
ds_wr_d <= lb_wr_d[31:0];
end
end
if ( lb_rd == 1 && lb_cs_data == 1 ) begin
if ( ctrl_cmd[5:0] == 6'h18 ||
ctrl_cmd[5:0] == 6'h19 ||
ctrl_cmd[5:0] == 6'h1a ) begin
ds_rd_req <= 1;
end
end
end
//-----------------------------------------------------------------------------
// LocalBus Write Ctrl register
//-----------------------------------------------------------------------------
always @ ( posedge clk_lb ) begin : proc_lb_wr
ds_cmd_lb <= ctrl_reg[5:0];
if ( lb_wr == 1 && lb_cs_ctrl == 1 ) begin
ctrl_reg[5:0] <= lb_wr_d[5:0];
ctrl_cmd_xfer <= 1;
end
if ( lb_wr == 1 && lb_cs_data == 1 ) begin
case( ctrl_cmd[5:0] )
6'h04 : ctrl_04_reg <= lb_wr_d[31:0];
6'h05 : ctrl_05_reg <= lb_wr_d[31:0];
6'h06 : ctrl_06_reg <= lb_wr_d[31:0];
6'h07 : ctrl_07_reg <= lb_wr_d[31:0];
6'h08 : ctrl_08_reg <= lb_wr_d[31:0];
6'h09 : ctrl_09_reg <= lb_wr_d[31:0];
6'h0A : ctrl_0a_reg <= lb_wr_d[31:0];
6'h0B : ctrl_0b_reg <= lb_wr_d[31:0];
6'h10 : ctrl_10_reg <= lb_wr_d[31:0];
6'h11 : ctrl_11_reg <= lb_wr_d[31:0];
6'h12 : ctrl_12_reg <= lb_wr_d[31:0];
6'h13 : ctrl_13_reg <= lb_wr_d[31:0];
6'h14 : ctrl_14_reg <= lb_wr_d[31:0];
6'h1d : ctrl_1d_reg <= lb_wr_d[31:0];
endcase
end
if ( xfer_clr == 1 ) begin
ctrl_cmd_xfer <= 0;
end
if ( ctrl_cmd == 6'h01 ) begin
d_addr <= c_addr[depth_bits-1:0];// When Acq stops, d_addr will be last
end
if ( lb_wr == 1 && lb_cs_data == 1 && ctrl_cmd == 6'h09 ) begin
d_addr <= lb_wr_d[depth_bits-1:0];// Load user specified address
end
if ( rd_inc == 1 ) begin
d_addr <= d_addr[depth_bits-1:0] + 1;// Auto Increment on each read
end
if ( reset_loc == 1 ) begin
ctrl_reg[5:0] <= 6'd0;
ctrl_cmd_xfer <= 1;// Flag to xfer ctrl_reg into other clock domain
end
end
assign ctrl_cmd[5:0] = ctrl_reg[5:0];
assign trigger_type = ctrl_04_reg[3:0];
assign trigger_bits = ctrl_05_reg[31:0];
assign trigger_nth = ctrl_06_reg[15:0];
assign trigger_delay = ctrl_06_reg[31:16];
assign trigger_pos = ctrl_07_reg[31:0];
assign rle_event_en = ctrl_08_reg[31:0];
assign user_ctrl[31:0] = ctrl_10_reg[31:0];
assign user_pat0[31:0] = ctrl_11_reg[31:0];
assign user_pat1[31:0] = ctrl_12_reg[31:0];
assign pat0[31:0] = ctrl_11_reg[31:0];
assign pat1[31:0] = ctrl_12_reg[31:0];
assign data_en_bits[31:0] = ctrl_13_reg[31:0];
assign watchdog_reg[31:0] = ctrl_14_reg[31:0];
assign ds_user_ctrl[31:0] = ctrl_1d_reg[31:0];
assign ctrl_rd_ptr[15:0] = ctrl_09_reg[15:0];
assign ctrl_rd_page[4:0] = ctrl_0a_reg[4:0];
assign data_4x_dwords = data_dwords;
//-----------------------------------------------------------------------------
// LocalBus readback of ctrl_reg and data_reg
//-----------------------------------------------------------------------------
always @ ( posedge clk_lb ) begin : proc_lb_rd
lb_rd_d <= 32'd0;
lb_rd_rdy <= 0;
rd_inc <= 0;
if ( lb_rd == 1 && lb_cs_ctrl == 1 ) begin
lb_rd_d[5:0] <= ctrl_reg[5:0];
lb_rd_rdy <= 1;
end
if ( ds_rd_rdy == 1 && deep_sump_en == 1 ) begin
lb_rd_d <= ds_rd_d[31:0];
lb_rd_rdy <= 1;
end
if ( lb_rd == 1 && lb_cs_data == 1 ) begin
if ( ctrl_cmd == 6'h00 ||
ctrl_cmd == 6'h01
) begin
lb_rd_d[7:0] <= cap_status[7:0];
lb_rd_rdy <= 1;
end
if ( ctrl_cmd == 6'h0b ) begin
lb_rd_d[31:16] <= sump_id;// Identification
lb_rd_d[15:8] <= sump_rev;// Revision
lb_rd_d[7] <= deep_sump_en;
lb_rd_d[6] <= data_en;
lb_rd_d[5] <= trigger_wd_en;
lb_rd_d[4] <= ~ nonrle_en;// Invert to disable backwards SW comptbl
lb_rd_d[3] <= rle_en;
lb_rd_d[2] <= pattern_en;
lb_rd_d[1] <= trigger_nth_en;
lb_rd_d[0] <= trigger_dly_en;
lb_rd_rdy <= 1;
end
if ( ctrl_cmd == 6'h0c ) begin
lb_rd_d[31:28] <= rle_en ;// 1 if RLE RAM exists
lb_rd_d[27:24] <= event_bytes;// How Many Event Bytes 1-4
lb_rd_d[23:16] <= data_4x_dwords[5:2];// How Many 32bit BRAMs data 4x
lb_rd_d[15:0] <= depth_len; // How deep RAMs are
lb_rd_rdy <= 1;
end
if ( ctrl_cmd == 6'h0d ) begin
lb_rd_d[15:0] <= freq_fracts;// Fractional MHz bits 1/2,1/4,etc.
lb_rd_d[31:16] <= freq_mhz ;// Integer MHz
lb_rd_rdy <= 1;
end
if ( ctrl_cmd == 6'h0e ) begin
lb_rd_d[depth_bits-1:0] <= trigger_ptr[depth_bits-1:0];// Where Trig Is
lb_rd_rdy <= 1;
end
if ( ctrl_cmd == 6'h0f ) begin
lb_rd_d <= ram_rd_d[31:0];
rd_inc <= 1;// Auto Increment RAM Address
lb_rd_rdy <= 1;
end
end
// Mux between the BRAMs
case( ctrl_rd_page[4:0] )
5'H02 : ram_rd_d <= b_do[31:0]; // RLE Data
5'H03 : ram_rd_d <= b_do[63:32]; // RLE Time
5'H10 : ram_rd_d <= dwords_3_0_do[31:0];
5'H11 : ram_rd_d <= dwords_3_0_do[63:32];
5'H12 : ram_rd_d <= dwords_3_0_do[95:64];
5'H13 : ram_rd_d <= dwords_3_0_do[127:96];
5'H14 : ram_rd_d <= dwords_7_4_do[31:0];
5'H15 : ram_rd_d <= dwords_7_4_do[63:32];
5'H16 : ram_rd_d <= dwords_7_4_do[95:64];
5'H17 : ram_rd_d <= dwords_7_4_do[127:96];
5'H18 : ram_rd_d <= dwords_11_8_do[31:0];
5'H19 : ram_rd_d <= dwords_11_8_do[63:32];
5'H1a : ram_rd_d <= dwords_11_8_do[95:64];
5'H1b : ram_rd_d <= dwords_11_8_do[127:96];
5'H1c : ram_rd_d <= dwords_15_12_do[31:0];
5'H1d : ram_rd_d <= dwords_15_12_do[63:32];
5'H1e : ram_rd_d <= dwords_15_12_do[95:64];
5'H1f : ram_rd_d <= dwords_15_12_do[127:96];
default : ram_rd_d <= d_do[31:0]; // Events
endcase
end // proc_lb_rd
//-----------------------------------------------------------------------------
// Data Dual Port RAM - Infer RAM here to make easy to change depth on the fly
//-----------------------------------------------------------------------------
always @( posedge clk_cap )
begin
c_we_p1 <= c_we;
c_addr_p1 <= c_addr;
c_di_p1 <= c_di;
if ( c_we_p1 ) begin
if ( nonrle_en == 1 ) begin
event_ram_array[c_addr_p1] <= c_di_p1;
end
end // if ( c_we )
dwords_3_0_p1 <= dwords_3_0[127:0];
dwords_7_4_p1 <= dwords_7_4[127:0];
dwords_11_8_p1 <= dwords_11_8[127:0];
dwords_15_12_p1 <= dwords_15_12[127:0];
dwords_3_0_p2 <= dwords_3_0_p1[127:0];
dwords_7_4_p2 <= dwords_7_4_p1[127:0];
dwords_11_8_p2 <= dwords_11_8_p1[127:0];
dwords_15_12_p2 <= dwords_15_12_p1[127:0];
if ( c_we_p1 ) begin
if ( data_dwords >= 4 ) begin
dwords_3_0_ram_array[ c_addr_p1 ] <= dwords_3_0_p2[127:0];
end
if ( data_dwords >= 8 ) begin
dwords_7_4_ram_array[ c_addr_p1 ] <= dwords_7_4_p2[127:0];
end
if ( data_dwords >= 12 ) begin
dwords_11_8_ram_array[ c_addr_p1 ] <= dwords_11_8_p2[127:0];
end
if ( data_dwords >= 16 ) begin
dwords_15_12_ram_array[ c_addr_p1 ] <= dwords_15_12_p2[127:0];
end
end // if ( c_we )
end // always
//-----------------------------------------------------------------------------
// 2nd Port of RAM is clocked from local bus
//-----------------------------------------------------------------------------
always @( posedge clk_lb )
begin
if ( nonrle_en == 1 ) begin
d_do <= event_ram_array[d_addr] ;
end
if ( data_dwords >= 4 ) begin
dwords_3_0_do <= dwords_3_0_ram_array[ d_addr ];
end
if ( data_dwords >= 8 ) begin
dwords_7_4_do <= dwords_7_4_ram_array[ d_addr ];
end
if ( data_dwords >= 12 ) begin
dwords_11_8_do <= dwords_11_8_ram_array[ d_addr ];
end
if ( data_dwords >= 16 ) begin
dwords_15_12_do <= dwords_15_12_ram_array[ d_addr ];
end
end // always
//-----------------------------------------------------------------------------
// RLE Dual Port RAM - Infer RAM here to make easy to change depth on the fly
//-----------------------------------------------------------------------------
always @( posedge clk_cap )
begin
if ( rle_en == 1 ) begin
a_we_p1 <= a_we;
a_addr_p1 <= a_addr;
a_we_p1 <= a_we;
a_addr_p1 <= a_addr;
a_di_p1 <= a_di;
if ( a_we_p1 ) begin
rle_ram_array[a_addr_p1] <= a_di_p1;
end // if ( a_we )
end
end // always
//-----------------------------------------------------------------------------
// 2nd Port of RAM is clocked from local bus
//-----------------------------------------------------------------------------
always @( posedge clk_lb )
begin
if ( rle_en == 1 ) begin
b_do <= rle_ram_array[d_addr];
end
end // always
endmodule |
module MAC_top(
//system signals
input Reset ,
input Clk_125M ,
input Clk_user ,
input Clk_reg ,
output [2:0] Speed ,
//user interface
output Rx_mac_ra ,
input Rx_mac_rd ,
output [31:0] Rx_mac_data ,
output [1:0] Rx_mac_BE ,
output Rx_mac_pa ,
output Rx_mac_sop ,
output Rx_mac_eop ,
//user interface
output Tx_mac_wa ,
input Tx_mac_wr ,
input [31:0] Tx_mac_data ,
input [1:0] Tx_mac_BE ,//big endian
input Tx_mac_sop ,
input Tx_mac_eop ,
//pkg_lgth fifo
input Pkg_lgth_fifo_rd ,
output Pkg_lgth_fifo_ra ,
output [15:0] Pkg_lgth_fifo_data ,
//Phy interface
//Phy interface
output Gtx_clk ,//used only in GMII mode
input Rx_clk ,
input Tx_clk ,//used only in MII mode
output Tx_er ,
output Tx_en ,
output [7:0] Txd ,
input Rx_er ,
input Rx_dv ,
input [7:0] Rxd ,
input Crs ,
input Col ,
//host interface
input CSB ,
input WRB ,
input [15:0] CD_in ,
output [15:0] CD_out ,
input [7:0] CA ,
//mdx
output Mdo, // MII Management Data Output
output MdoEn, // MII Management Data Output Enable
input Mdi,
output Mdc // MII Management Data Clock
);
//******************************************************************************
//internal signals
//******************************************************************************
//RMON interface
wire [15:0] Rx_pkt_length_rmon ;
wire Rx_apply_rmon ;
wire [2:0] Rx_pkt_err_type_rmon ;
wire [2:0] Rx_pkt_type_rmon ;
wire [2:0] Tx_pkt_type_rmon ;
wire [15:0] Tx_pkt_length_rmon ;
wire Tx_apply_rmon ;
wire [2:0] Tx_pkt_err_type_rmon ;
//PHY interface
wire MCrs_dv ;
wire [7:0] MRxD ;
wire MRxErr ;
//flow_control signals
wire [15:0] pause_quanta ;
wire pause_quanta_val ;
//PHY interface
wire [7:0] MTxD ;
wire MTxEn ;
wire MCRS ;
//interface clk signals
wire MAC_tx_clk ;
wire MAC_rx_clk ;
wire MAC_tx_clk_div ;
wire MAC_rx_clk_div ;
//reg signals
wire [4:0] Tx_Hwmark ;
wire [4:0] Tx_Lwmark ;
wire pause_frame_send_en ;
wire [15:0] pause_quanta_set ;
wire MAC_tx_add_en ;
wire FullDuplex ;
wire [3:0] MaxRetry ;
wire [5:0] IFGset ;
wire [7:0] MAC_tx_add_prom_data ;
wire [2:0] MAC_tx_add_prom_add ;
wire MAC_tx_add_prom_wr ;
wire tx_pause_en ;
wire xoff_cpu ;
wire xon_cpu ;
//Rx host interface
wire MAC_rx_add_chk_en ;
wire [7:0] MAC_rx_add_prom_data ;
wire [2:0] MAC_rx_add_prom_add ;
wire MAC_rx_add_prom_wr ;
wire broadcast_filter_en ;
wire [15:0] broadcast_MAX ;
wire RX_APPEND_CRC ;
wire [4:0] Rx_Hwmark ;
wire [4:0] Rx_Lwmark ;
wire CRC_chk_en ;
wire [5:0] RX_IFG_SET ;
wire [15:0] RX_MAX_LENGTH ;
wire [6:0] RX_MIN_LENGTH ;
//RMON host interface
wire [5:0] CPU_rd_addr ;
wire CPU_rd_apply ;
wire CPU_rd_grant ;
wire [31:0] CPU_rd_dout ;
//Phy int host interface
wire Line_loop_en ;
//MII to CPU
wire [7:0] Divider ;
wire [15:0] CtrlData ;
wire [4:0] Rgad ;
wire [4:0] Fiad ;
wire NoPre ;
wire WCtrlData ;
wire RStat ;
wire ScanStat ;
wire Busy ;
wire LinkFail ;
wire Nvalid ;
wire [15:0] Prsd ;
wire WCtrlDataStart ;
wire RStatStart ;
wire UpdateMIIRX_DATAReg ;
wire [15:0] broadcast_bucket_depth ;
wire [15:0] broadcast_bucket_interval ;
wire Pkg_lgth_fifo_empty;
reg rx_pkg_lgth_fifo_wr_tmp;
reg rx_pkg_lgth_fifo_wr_tmp_pl1;
reg rx_pkg_lgth_fifo_wr;
//******************************************************************************
//internal signals
//******************************************************************************
MAC_rx U_MAC_rx(
.Reset (Reset ),
.Clk_user (Clk_user ),
.Clk (MAC_rx_clk_div ),
//RMII interface (//PHY interface ),
.MCrs_dv (MCrs_dv ),
.MRxD (MRxD ),
.MRxErr (MRxErr ),
//flow_control signals (//flow_control signals ),
.pause_quanta (pause_quanta ),
.pause_quanta_val (pause_quanta_val ),
//user interface (//user interface ),
.Rx_mac_ra (Rx_mac_ra ),
.Rx_mac_rd (Rx_mac_rd ),
.Rx_mac_data (Rx_mac_data ),
.Rx_mac_BE (Rx_mac_BE ),
.Rx_mac_pa (Rx_mac_pa ),
.Rx_mac_sop (Rx_mac_sop ),
.Rx_mac_eop (Rx_mac_eop ),
//CPU (//CPU ),
.MAC_rx_add_chk_en (MAC_rx_add_chk_en ),
.MAC_add_prom_data (MAC_rx_add_prom_data ),
.MAC_add_prom_add (MAC_rx_add_prom_add ),
.MAC_add_prom_wr (MAC_rx_add_prom_wr ),
.broadcast_filter_en (broadcast_filter_en ),
.broadcast_bucket_depth (broadcast_bucket_depth ),
.broadcast_bucket_interval (broadcast_bucket_interval ),
.RX_APPEND_CRC (RX_APPEND_CRC ),
.Rx_Hwmark (Rx_Hwmark ),
.Rx_Lwmark (Rx_Lwmark ),
.CRC_chk_en (CRC_chk_en ),
.RX_IFG_SET (RX_IFG_SET ),
.RX_MAX_LENGTH (RX_MAX_LENGTH ),
.RX_MIN_LENGTH (RX_MIN_LENGTH ),
//RMON interface (//RMON interface ),
.Rx_pkt_length_rmon (Rx_pkt_length_rmon ),
.Rx_apply_rmon (Rx_apply_rmon ),
.Rx_pkt_err_type_rmon (Rx_pkt_err_type_rmon ),
.Rx_pkt_type_rmon (Rx_pkt_type_rmon )
);
MAC_tx U_MAC_tx(
.Reset (Reset ),
.Clk (MAC_tx_clk_div ),
.Clk_user (Clk_user ),
//PHY interface (//PHY interface ),
.TxD (MTxD ),
.TxEn (MTxEn ),
.CRS (MCRS ),
//RMON (//RMON ),
.Tx_pkt_type_rmon (Tx_pkt_type_rmon ),
.Tx_pkt_length_rmon (Tx_pkt_length_rmon ),
.Tx_apply_rmon (Tx_apply_rmon ),
.Tx_pkt_err_type_rmon (Tx_pkt_err_type_rmon ),
//user interface (//user interface ),
.Tx_mac_wa (Tx_mac_wa ),
.Tx_mac_wr (Tx_mac_wr ),
.Tx_mac_data (Tx_mac_data ),
.Tx_mac_BE (Tx_mac_BE ),
.Tx_mac_sop (Tx_mac_sop ),
.Tx_mac_eop (Tx_mac_eop ),
//host interface (//host interface ),
.Tx_Hwmark (Tx_Hwmark ),
.Tx_Lwmark (Tx_Lwmark ),
.pause_frame_send_en (pause_frame_send_en ),
.pause_quanta_set (pause_quanta_set ),
.MAC_tx_add_en (MAC_tx_add_en ),
.FullDuplex (FullDuplex ),
.MaxRetry (MaxRetry ),
.IFGset (IFGset ),
.MAC_add_prom_data (MAC_tx_add_prom_data ),
.MAC_add_prom_add (MAC_tx_add_prom_add ),
.MAC_add_prom_wr (MAC_tx_add_prom_wr ),
.tx_pause_en (tx_pause_en ),
.xoff_cpu (xoff_cpu ),
.xon_cpu (xon_cpu ),
//MAC_rx_flow (//MAC_rx_flow ),
.pause_quanta (pause_quanta ),
.pause_quanta_val (pause_quanta_val )
);
assign Pkg_lgth_fifo_ra=!Pkg_lgth_fifo_empty;
always @ (posedge Reset or posedge MAC_rx_clk_div)
if (Reset)
rx_pkg_lgth_fifo_wr_tmp <=0;
else if(Rx_apply_rmon&&Rx_pkt_err_type_rmon==3'b100)
rx_pkg_lgth_fifo_wr_tmp <=1;
else
rx_pkg_lgth_fifo_wr_tmp <=0;
always @ (posedge Reset or posedge MAC_rx_clk_div)
if (Reset)
rx_pkg_lgth_fifo_wr_tmp_pl1 <=0;
else
rx_pkg_lgth_fifo_wr_tmp_pl1 <=rx_pkg_lgth_fifo_wr_tmp;
always @ (posedge Reset or posedge MAC_rx_clk_div)
if (Reset)
rx_pkg_lgth_fifo_wr <=0;
else if(rx_pkg_lgth_fifo_wr_tmp&!rx_pkg_lgth_fifo_wr_tmp_pl1)
rx_pkg_lgth_fifo_wr <=1;
else
rx_pkg_lgth_fifo_wr <=0;
afifo U_rx_pkg_lgth_fifo (
.din (RX_APPEND_CRC?Rx_pkt_length_rmon:Rx_pkt_length_rmon-4),
.wr_en (rx_pkg_lgth_fifo_wr ),
.wr_clk (MAC_rx_clk_div ),
.rd_en (Pkg_lgth_fifo_rd ),
.rd_clk (Clk_user ),
.ainit (Reset ),
.dout (Pkg_lgth_fifo_data ),
.full ( ),
.almost_full ( ),
.empty (Pkg_lgth_fifo_empty ),
.wr_count ( ),
.rd_count ( ),
.rd_ack ( ),
.wr_ack ( ));
RMON U_RMON(
.Clk (Clk_reg ),
.Reset (Reset ),
//Tx_RMON (//Tx_RMON ),
.Tx_pkt_type_rmon (Tx_pkt_type_rmon ),
.Tx_pkt_length_rmon (Tx_pkt_length_rmon ),
.Tx_apply_rmon (Tx_apply_rmon ),
.Tx_pkt_err_type_rmon (Tx_pkt_err_type_rmon ),
//Tx_RMON (//Tx_RMON ),
.Rx_pkt_type_rmon (Rx_pkt_type_rmon ),
.Rx_pkt_length_rmon (Rx_pkt_length_rmon ),
.Rx_apply_rmon (Rx_apply_rmon ),
.Rx_pkt_err_type_rmon (Rx_pkt_err_type_rmon ),
//CPU (//CPU ),
.CPU_rd_addr (CPU_rd_addr ),
.CPU_rd_apply (CPU_rd_apply ),
.CPU_rd_grant (CPU_rd_grant ),
.CPU_rd_dout (CPU_rd_dout )
);
Phy_int U_Phy_int(
.Reset (Reset ),
.MAC_rx_clk (MAC_rx_clk ),
.MAC_tx_clk (MAC_tx_clk ),
//Rx interface (//Rx interface ),
.MCrs_dv (MCrs_dv ),
.MRxD (MRxD ),
.MRxErr (MRxErr ),
//Tx interface (//Tx interface ),
.MTxD (MTxD ),
.MTxEn (MTxEn ),
.MCRS (MCRS ),
//Phy interface (//Phy interface ),
.Tx_er (Tx_er ),
.Tx_en (Tx_en ),
.Txd (Txd ),
.Rx_er (Rx_er ),
.Rx_dv (Rx_dv ),
.Rxd (Rxd ),
.Crs (Crs ),
.Col (Col ),
//host interface (//host interface ),
.Line_loop_en (Line_loop_en ),
.Speed (Speed )
);
Clk_ctrl U_Clk_ctrl(
.Reset (Reset ),
.Clk_125M (Clk_125M ),
//host interface (//host interface ),
.Speed (Speed ),
//Phy interface (//Phy interface ),
.Gtx_clk (Gtx_clk ),
.Rx_clk (Rx_clk ),
.Tx_clk (Tx_clk ),
//interface clk (//interface clk ),
.MAC_tx_clk (MAC_tx_clk ),
.MAC_rx_clk (MAC_rx_clk ),
.MAC_tx_clk_div (MAC_tx_clk_div ),
.MAC_rx_clk_div (MAC_rx_clk_div )
);
eth_miim U_eth_miim(
.Clk (Clk_reg ),
.Reset (Reset ),
.Divider (Divider ),
.NoPre (NoPre ),
.CtrlData (CtrlData ),
.Rgad (Rgad ),
.Fiad (Fiad ),
.WCtrlData (WCtrlData ),
.RStat (RStat ),
.ScanStat (ScanStat ),
.Mdo (Mdo ),
.MdoEn (MdoEn ),
.Mdi (Mdi ),
.Mdc (Mdc ),
.Busy (Busy ),
.Prsd (Prsd ),
.LinkFail (LinkFail ),
.Nvalid (Nvalid ),
.WCtrlDataStart (WCtrlDataStart ),
.RStatStart (RStatStart ),
.UpdateMIIRX_DATAReg (UpdateMIIRX_DATAReg ));
Reg_int U_Reg_int(
.Reset (Reset ),
.Clk_reg (Clk_reg ),
.CSB (CSB ),
.WRB (WRB ),
.CD_in (CD_in ),
.CD_out (CD_out ),
.CA (CA ),
//Tx host interface (//Tx host interface ),
.Tx_Hwmark (Tx_Hwmark ),
.Tx_Lwmark (Tx_Lwmark ),
.pause_frame_send_en (pause_frame_send_en ),
.pause_quanta_set (pause_quanta_set ),
.MAC_tx_add_en (MAC_tx_add_en ),
.FullDuplex (FullDuplex ),
.MaxRetry (MaxRetry ),
.IFGset (IFGset ),
.MAC_tx_add_prom_data (MAC_tx_add_prom_data ),
.MAC_tx_add_prom_add (MAC_tx_add_prom_add ),
.MAC_tx_add_prom_wr (MAC_tx_add_prom_wr ),
.tx_pause_en (tx_pause_en ),
.xoff_cpu (xoff_cpu ),
.xon_cpu (xon_cpu ),
//Rx host interface (//Rx host interface ),
.MAC_rx_add_chk_en (MAC_rx_add_chk_en ),
.MAC_rx_add_prom_data (MAC_rx_add_prom_data ),
.MAC_rx_add_prom_add (MAC_rx_add_prom_add ),
.MAC_rx_add_prom_wr (MAC_rx_add_prom_wr ),
.broadcast_filter_en (broadcast_filter_en ),
.broadcast_bucket_depth (broadcast_bucket_depth ),
.broadcast_bucket_interval (broadcast_bucket_interval ),
.RX_APPEND_CRC (RX_APPEND_CRC ),
.Rx_Hwmark (Rx_Hwmark ),
.Rx_Lwmark (Rx_Lwmark ),
.CRC_chk_en (CRC_chk_en ),
.RX_IFG_SET (RX_IFG_SET ),
.RX_MAX_LENGTH (RX_MAX_LENGTH ),
.RX_MIN_LENGTH (RX_MIN_LENGTH ),
//RMON host interface (//RMON host interface ),
.CPU_rd_addr (CPU_rd_addr ),
.CPU_rd_apply (CPU_rd_apply ),
.CPU_rd_grant (CPU_rd_grant ),
.CPU_rd_dout (CPU_rd_dout ),
//Phy int host interface (//Phy int host interface ),
.Line_loop_en (Line_loop_en ),
.Speed (Speed ),
//MII to CPU (//MII to CPU ),
.Divider (Divider ),
.CtrlData (CtrlData ),
.Rgad (Rgad ),
.Fiad (Fiad ),
.NoPre (NoPre ),
.WCtrlData (WCtrlData ),
.RStat (RStat ),
.ScanStat (ScanStat ),
.Busy (Busy ),
.LinkFail (LinkFail ),
.Nvalid (Nvalid ),
.Prsd (Prsd ),
.WCtrlDataStart (WCtrlDataStart ),
.RStatStart (RStatStart ),
.UpdateMIIRX_DATAReg (UpdateMIIRX_DATAReg )
);
endmodule |
module fifo_formalbench;
wire reset = 1'b0;
wire clock;
wire enque, deque;
wire [3:0] enque_data, deque_data, data0, data1, data2, data3;
wire is_full, is_empty;
fifo f0
( .reset
, .clock
, .enque
, .deque
, .enque_data
, .deque_data
, .enqued
, .dequed
, .is_full
, .is_empty
);
// psl default clock = (posedge clock);
// psl assmue always stable(data0);
// psl assmue always stable(data1);
// psl assmue always stable(data2);
// psl assmue always stable(data3);
// psl what_goes_in_may_come_out : assert always
// {! is_full && enque && enque_data == data0; enqued} |=>
// {(! is_empty)[*]; deque; (! dequed)[*]; dequed && deque_data == data0};
// psl what_goes_in_can_be_forced_out : assert always ((always deque) -> (
// {! is_full && enque && enque_data == data0; enqued} |=>
// {[*]; dequed && deque_data == data0} !));
// psl single_in_single_out : assert always
// {is_empty && enque && enque_data == data0; enqued; (! deque)[*]; deque; dequed} |->
// (deque_data == data0);
// psl empty_to_full_to_empty : cover
// { is_empty && enque && enque_data == data0
// ; (! enqued)[*]
// ; enqued && enque && enque_data == data1
// ; (! enqued)[*]
// ; enqued && enque && enque_data == data2
// ; (! enqued)[*]
// ; enqued && enque && enque_data == data3
// ; (! enqued)[*]
// ; enqued && is_full
// ; deque
// ; (! dequed)[*]
// ; dequed && deque_data == data0 && deque
// ; (! dequed)[*]
// ; dequed && deque_data == data1 && deque
// ; (! dequed)[*]
// ; dequed && deque_data == data2 && deque
// ; (! dequed)[*]
// ; dequed && deque_data == data3 && is_empty
// };
// psl immediate_enque : assert always {! is_full && enque} |=> enqued;
// psl immediate_deque : assert always {! is_empty && deque} |=> dequed;
// psl concurrent_enque_deque : assert always {! is_empty && enque && deque} |=> (enqued && dequed);
endmodule |
module sky130_fd_sc_lp__o32a (
//# {{data|Data Signals}}
input A1,
input A2,
input A3,
input B1,
input B2,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule |
module test_ace;
// Inputs
reg clk50mhz;
reg reset;
reg ear;
// Outputs
wire spk;
wire mic;
wire video;
wire sync;
// Instantiate the Unit Under Test (UUT)
jace_en_fpga uut (
.clk50mhz(clk50mhz),
.reset(reset),
.ear(ear),
.spk(spk),
.mic(mic),
.video(video),
.sync(sync)
);
initial begin
// Initialize Inputs
clk50mhz = 0;
reset = 1;
ear = 0;
// Wait 100 ns for global reset to finish
#1000;
reset = 0;
// Add stimulus here
end
always
#77 clk50mhz = !clk50mhz;
endmodule |
module infrastructure #
(
parameter C_INCLK_PERIOD = 2500,
parameter C_RST_ACT_LOW = 1,
parameter C_INPUT_CLK_TYPE = "DIFFERENTIAL",
parameter C_CLKOUT0_DIVIDE = 1,
parameter C_CLKOUT1_DIVIDE = 1,
parameter C_CLKOUT2_DIVIDE = 16,
parameter C_CLKOUT3_DIVIDE = 8,
parameter C_CLKFBOUT_MULT = 2,
parameter C_DIVCLK_DIVIDE = 1
)
(
input sys_clk_p,
input sys_clk_n,
input sys_clk,
input sys_rst_i,
output clk0,
output rst0,
output async_rst,
output sysclk_2x,
output sysclk_2x_180,
output mcb_drp_clk,
output pll_ce_0,
output pll_ce_90,
output pll_lock
);
// # of clock cycles to delay deassertion of reset. Needs to be a fairly
// high number not so much for metastability protection, but to give time
// for reset (i.e. stable clock cycles) to propagate through all state
// machines and to all control signals (i.e. not all control signals have
// resets, instead they rely on base state logic being reset, and the effect
// of that reset propagating through the logic). Need this because we may not
// be getting stable clock cycles while reset asserted (i.e. since reset
// depends on PLL/DCM lock status)
localparam RST_SYNC_NUM = 25;
localparam CLK_PERIOD_NS = C_INCLK_PERIOD / 1000.0;
localparam CLK_PERIOD_INT = C_INCLK_PERIOD/1000;
wire clk_2x_0;
wire clk_2x_180;
wire clk0_bufg;
wire clk0_bufg_in;
wire mcb_drp_clk_bufg_in;
wire clkfbout_clkfbin;
wire locked;
reg [RST_SYNC_NUM-1:0] rst0_sync_r /* synthesis syn_maxfan = 10 */;
wire rst_tmp;
reg powerup_pll_locked;
reg syn_clk0_powerup_pll_locked;
wire sys_rst;
wire bufpll_mcb_locked;
(* KEEP = "TRUE" *) wire sys_clk_ibufg;
assign sys_rst = C_RST_ACT_LOW ? ~sys_rst_i: sys_rst_i;
assign clk0 = clk0_bufg;
assign pll_lock = bufpll_mcb_locked;
generate
if (C_INPUT_CLK_TYPE == "DIFFERENTIAL") begin: diff_input_clk
//***********************************************************************
// Differential input clock input buffers
//***********************************************************************
IBUFGDS #
(
.DIFF_TERM ("TRUE")
)
u_ibufg_sys_clk
(
.I (sys_clk_p),
.IB (sys_clk_n),
.O (sys_clk_ibufg)
);
end else if (C_INPUT_CLK_TYPE == "SINGLE_ENDED") begin: se_input_clk
//***********************************************************************
// SINGLE_ENDED input clock input buffers
//***********************************************************************
IBUFG u_ibufg_sys_clk
(
.I (sys_clk),
.O (sys_clk_ibufg)
);
end
endgenerate
//***************************************************************************
// Global clock generation and distribution
//***************************************************************************
PLL_ADV #
(
.BANDWIDTH ("OPTIMIZED"),
.CLKIN1_PERIOD (CLK_PERIOD_NS),
.CLKIN2_PERIOD (CLK_PERIOD_NS),
.CLKOUT0_DIVIDE (C_CLKOUT0_DIVIDE),
.CLKOUT1_DIVIDE (C_CLKOUT1_DIVIDE),
.CLKOUT2_DIVIDE (C_CLKOUT2_DIVIDE),
.CLKOUT3_DIVIDE (C_CLKOUT3_DIVIDE),
.CLKOUT4_DIVIDE (1),
.CLKOUT5_DIVIDE (1),
.CLKOUT0_PHASE (0.000),
.CLKOUT1_PHASE (180.000),
.CLKOUT2_PHASE (0.000),
.CLKOUT3_PHASE (0.000),
.CLKOUT4_PHASE (0.000),
.CLKOUT5_PHASE (0.000),
.CLKOUT0_DUTY_CYCLE (0.500),
.CLKOUT1_DUTY_CYCLE (0.500),
.CLKOUT2_DUTY_CYCLE (0.500),
.CLKOUT3_DUTY_CYCLE (0.500),
.CLKOUT4_DUTY_CYCLE (0.500),
.CLKOUT5_DUTY_CYCLE (0.500),
.SIM_DEVICE ("SPARTAN6"),
.COMPENSATION ("INTERNAL"),
.DIVCLK_DIVIDE (C_DIVCLK_DIVIDE),
.CLKFBOUT_MULT (C_CLKFBOUT_MULT),
.CLKFBOUT_PHASE (0.0),
.REF_JITTER (0.005000)
)
u_pll_adv
(
.CLKFBIN (clkfbout_clkfbin),
.CLKINSEL (1'b1),
.CLKIN1 (sys_clk_ibufg),
.CLKIN2 (1'b0),
.DADDR (5'b0),
.DCLK (1'b0),
.DEN (1'b0),
.DI (16'b0),
.DWE (1'b0),
.REL (1'b0),
.RST (sys_rst),
.CLKFBDCM (),
.CLKFBOUT (clkfbout_clkfbin),
.CLKOUTDCM0 (),
.CLKOUTDCM1 (),
.CLKOUTDCM2 (),
.CLKOUTDCM3 (),
.CLKOUTDCM4 (),
.CLKOUTDCM5 (),
.CLKOUT0 (clk_2x_0),
.CLKOUT1 (clk_2x_180),
.CLKOUT2 (clk0_bufg_in),
.CLKOUT3 (mcb_drp_clk_bufg_in),
.CLKOUT4 (),
.CLKOUT5 (),
.DO (),
.DRDY (),
.LOCKED (locked)
);
BUFG U_BUFG_CLK0
(
.O (clk0_bufg),
.I (clk0_bufg_in)
);
BUFGCE U_BUFG_CLK1
(
.O (mcb_drp_clk),
.I (mcb_drp_clk_bufg_in),
.CE (locked)
);
always @(posedge mcb_drp_clk , posedge sys_rst)
if(sys_rst)
powerup_pll_locked <= 1'b0;
else if (bufpll_mcb_locked)
powerup_pll_locked <= 1'b1;
always @(posedge clk0_bufg , posedge sys_rst)
if(sys_rst)
syn_clk0_powerup_pll_locked <= 1'b0;
else if (bufpll_mcb_locked)
syn_clk0_powerup_pll_locked <= 1'b1;
//***************************************************************************
// Reset synchronization
// NOTES:
// 1. shut down the whole operation if the PLL hasn't yet locked (and
// by inference, this means that external SYS_RST_IN has been asserted -
// PLL deasserts LOCKED as soon as SYS_RST_IN asserted)
// 2. asynchronously assert reset. This was we can assert reset even if
// there is no clock (needed for things like 3-stating output buffers).
// reset deassertion is synchronous.
// 3. asynchronous reset only look at pll_lock from PLL during power up. After
// power up and pll_lock is asserted, the powerup_pll_locked will be asserted
// forever until sys_rst is asserted again. PLL will lose lock when FPGA
// enters suspend mode. We don't want reset to MCB get
// asserted in the application that needs suspend feature.
//***************************************************************************
assign async_rst = sys_rst | ~powerup_pll_locked;
// synthesis attribute max_fanout of rst0_sync_r is 10
assign rst_tmp = sys_rst | ~syn_clk0_powerup_pll_locked;
always @(posedge clk0_bufg or posedge rst_tmp)
if (rst_tmp)
rst0_sync_r <= {RST_SYNC_NUM{1'b1}};
else
// logical left shift by one (pads with 0)
rst0_sync_r <= rst0_sync_r << 1;
assign rst0 = rst0_sync_r[RST_SYNC_NUM-1];
BUFPLL_MCB BUFPLL_MCB1
( .IOCLK0 (sysclk_2x),
.IOCLK1 (sysclk_2x_180),
.LOCKED (locked),
.GCLK (mcb_drp_clk),
.SERDESSTROBE0 (pll_ce_0),
.SERDESSTROBE1 (pll_ce_90),
.PLLIN0 (clk_2x_0),
.PLLIN1 (clk_2x_180),
.LOCK (bufpll_mcb_locked)
);
endmodule |
module pcx_dp_macc_l(/*AUTOARG*/
// Outputs
data_out_px_l, scan_out, shiftenable_buf,
// Inputs
arb_pcxdp_qsel1_pa, arb_pcxdp_qsel0_pa, arb_pcxdp_grant_pa,
arb_pcxdp_shift_px, arb_pcxdp_q0_hold_pa, src_pcx_data_pa,
data_crit_px_l, data_ncrit_px_l, rclk, scan_in, shiftenable
);
output [129:0] data_out_px_l; // pcx to destination pkt
output scan_out;
output shiftenable_buf;
input arb_pcxdp_qsel1_pa; // queue write sel
input arb_pcxdp_qsel0_pa; // queue write sel
input arb_pcxdp_grant_pa;//grant signal
input arb_pcxdp_shift_px;//grant signal
input arb_pcxdp_q0_hold_pa;//grant signal
input [129:0] src_pcx_data_pa; // spache to pcx data
input [129:0] data_crit_px_l;
input [129:0] data_ncrit_px_l;
input rclk;
//input tmb_l;
input scan_in;
input shiftenable;
wire grant_px;
wire [129:0] q0_datain_pa;
wire [129:0] q1_dataout, q0_dataout;
wire [129:0] data_px_l;
wire clkq0, clkq1;
reg clkenq0, clkenq1;
//HEADER SECTION
// Generate gated clocks for hold function
assign shiftenable_buf = shiftenable;
//replace tmb_l w/ ~se
wire se_l ;
assign se_l = ~shiftenable ;
clken_buf ck0 (
.clk (clkq0),
.rclk (rclk),
.enb_l(~arb_pcxdp_q0_hold_pa),
.tmb_l(se_l));
clken_buf ck1 (
.clk (clkq1),
.rclk (rclk),
.enb_l(~arb_pcxdp_qsel1_pa),
.tmb_l(se_l));
// Latch and drive grant signal
// Generate write selects
dff_s #(1) dff_pcx_grin_r(
.din (arb_pcxdp_grant_pa),
.q (grant_px),
.clk (rclk),
.se (1'b0),
.si (1'b0),
.so ());
//DATAPATH SECTION
dff_s #(130) dff_pcx_datain_q1(
.din (src_pcx_data_pa[129:0]),
.q (q1_dataout[129:0]),
.clk (clkq1),
.se (1'b0),
.si (),
.so ());
/*
mux2ds #(`PCX_WIDTH) mx2ds_pcx_datain_q0(
.dout (q0_datain_pa[`PCX_WIDTH-1:0]),
.in0 (q1_dataout[`PCX_WIDTH-1:0]),
.in1 (src_pcx_data_pa[`PCX_WIDTH-1:0]),
.sel0 (arb_pcxdp_shift_px),
.sel1 (arb_pcxdp_qsel0_pa));
*/
assign q0_datain_pa[129:0] =
(arb_pcxdp_qsel0_pa ? src_pcx_data_pa[129:0] : 130'd0) |
(arb_pcxdp_shift_px ? q1_dataout[129:0] : 130'd0) ;
dff_s #(130) dff_pcx_datain_q0(
.din (q0_datain_pa[129:0]),
.q (q0_dataout[129:0]),
.clk (clkq0),
.se (1'b0),
.si (),
.so ());
assign data_px_l[129:0] = ~(grant_px ? q0_dataout[129:0]:130'd0);
assign data_out_px_l[129:0] = data_px_l[129:0] & data_crit_px_l[129:0] & data_ncrit_px_l[129:0];
// Global Variables:
// verilog-library-directories:("." "../../../../../common/rtl" "../rtl")
// End:
// Code start here
//
endmodule |
module sctag_iqctl
(/*AUTOARG*/
// Outputs
so, iq_array_wr_en, iq_array_wr_wl, iq_array_rd_en,
iq_array_rd_wl, sctag_pcx_stall_pq, iq_arbctl_vld_px2,
pcx_sctag_atm_px2_p, iqctl_sel_pcx, iqctl_sel_c1, iqctl_hold_rd,
sel_c1reg_over_iqarray,
// Inputs
rclk, arst_l, grst_l, se, si, pcx_sctag_data_rdy_px1,
pcx_sctag_atm_px1, sehold, arbctl_iqsel_px2
) ;
input rclk;
input arst_l;
input grst_l;
input se;
input si;
input pcx_sctag_data_rdy_px1;
input pcx_sctag_atm_px1;
input sehold; // NEW_PIN post 4.2
input arbctl_iqsel_px2;
output so;
output iq_array_wr_en;
output [3:0] iq_array_wr_wl;
output iq_array_rd_en;
output [3:0] iq_array_rd_wl;
output sctag_pcx_stall_pq;
output iq_arbctl_vld_px2;
output pcx_sctag_atm_px2_p;
output iqctl_sel_pcx;
output iqctl_sel_c1;
output iqctl_hold_rd;
output sel_c1reg_over_iqarray;
////////////////////////////////////////////////////////////////////////////////
// Local Wires declaration
////////////////////////////////////////////////////////////////////////////////
wire pcx_sctag_data_rdy_px2 ;
wire pcx_sctag_data_rdy_px2_d1 ;
wire arbctl_iqsel_px2_d1 ;
wire set_c1_reg_inst_vld ;
wire c1_reg_inst_vld ;
wire inc_wr_ptr_px2 ;
wire inc_wr_ptr_c1 ;
wire sel_wrptr_same, sel_wrptr_plus1 ;
wire [3:0] wrptr, wrptr_plus1 ;
wire [3:0] wrptr_d1, wrptr_plus1_d1 ;
wire inc_rd_ptr_px2 ;
wire [3:0] rdptr, rdptr_plus1 ;
wire [3:0] rdptr_d1 ;
wire sel_qcount_plus1 ;
wire sel_qcount_minus1 ;
wire sel_qcount_same ;
wire [4:0] que_cnt, que_cnt_plus1, que_cnt_minus1 ;
wire [4:0] next_que_cnt ;
wire que_cnt_0, que_cnt_0_p, que_cnt_0_n ;
wire que_cnt_1, que_cnt_1_p, que_cnt_1_n ;
wire que_cnt_1_plus, que_cnt_1_plus_p, que_cnt_1_plus_n ;
wire que_cnt_2, que_cnt_2_p, que_cnt_2_n ;
wire que_cnt_2_plus_p ;
wire que_cnt_3_p ;
wire que_cnt_11_p ;
wire que_cnt_12, que_cnt_12_p, que_cnt_12_n ;
wire que_cnt_12_plus, que_cnt_12_plus_p, que_cnt_12_plus_n ;
wire que_cnt_13_p ;
wire que_cnt_13_plus_p ;
wire set_iqctl_sel_iq ;
wire set_iqctl_sel_pcx ;
wire iqctl_sel_iq;
wire iqctl_sel_iq_d1;
wire iqctl_sel_iq_fe;
wire dbb_rst_l;
///////////////////////////////////////////////////////////////////
// Reset flop
///////////////////////////////////////////////////////////////////
dffrl_async #(1) reset_flop (.q(dbb_rst_l),
.clk(rclk),
.rst_l(arst_l),
.din(grst_l),
.se(se), .si(), .so());
////////////////////////////////////////////////////////////////////////////////
dff_s #(1) ff_pcx_sctag_data_rdy_px2
(.q (pcx_sctag_data_rdy_px2),
.din (pcx_sctag_data_rdy_px1),
.clk (rclk),
.se(se), .si (), .so ()
) ;
dff_s #(1) ff_pcx_sctag_data_rdy_px2_d1
(.q (pcx_sctag_data_rdy_px2_d1),
.din (pcx_sctag_data_rdy_px2),
.clk (rclk),
.se(se), .si (), .so ()
) ;
dff_s #(1) ff_pcx_sctag_atm_px2_p
(.q (pcx_sctag_atm_px2_p),
.din (pcx_sctag_atm_px1),
.clk (rclk),
.se(se), .si (), .so ()
) ;
dff_s #(1) ff_arbctl_iqsel_px2_d1
(.q (arbctl_iqsel_px2_d1),
.din (arbctl_iqsel_px2),
.clk (rclk),
.se(se), .si (), .so ()
) ;
////////////////////////////////////////////////////////////////////////////////
// "c1_reg_inst_vld" signal will be used to indicate that there is a valid
// instructon in the C1 Flop. C1 flop instruction is only valid if the queue is
// empty and the instruction issued by the pcx is not selected in the same cycle
// by the arbiter. C1 flop is used to store the instruction for only one cycle
// in the case queue is empty and instruction issued by pcx is not selected by
// arbiter in the same cycle.
////////////////////////////////////////////////////////////////////////////////
assign set_c1_reg_inst_vld = ((que_cnt_0 | (que_cnt_1 & sel_qcount_minus1)) &
~c1_reg_inst_vld & pcx_sctag_data_rdy_px2 & ~arbctl_iqsel_px2) |
(((c1_reg_inst_vld) |
(que_cnt_1 & ~sel_qcount_minus1 & ~sel_qcount_plus1) |
(que_cnt_2 & sel_qcount_minus1)) &
pcx_sctag_data_rdy_px2 & arbctl_iqsel_px2) ;
dff_s #(1) ff_pcx_inst_vld_c1
(.q (c1_reg_inst_vld),
.din (set_c1_reg_inst_vld),
.clk (rclk),
.se(se), .si (), .so ()
) ;
////////////////////////////////////////////////////////////////////////////////
// Pipeline for Write Enable and Write Pointer generation for PH2 write
//
//===================================================
// PX2 | C1 |
//===================================================
// write into | write into |
// IQ array | IQ array |
// | |
// gen wrt en | gen wrt en |
// | |
// gen inc wrt | Mux select new gen inc wrt |
// ptr signal | wrt pointer ptr signal |
// | |
// gen wrt ptr | gen wrt ptr |
// plus 1 | plus 1 |
//===================================================
////////////////////////////////////////////////////////////////////////////////
assign inc_wr_ptr_px2 = pcx_sctag_data_rdy_px2 & (~arbctl_iqsel_px2 |
((~que_cnt_0 & ~(que_cnt_1 & sel_qcount_minus1)) |
c1_reg_inst_vld)) ;
dff_s #(1) ff_inc_wr_ptr_c1
(.q (inc_wr_ptr_c1),
.din (inc_wr_ptr_px2),
.clk (rclk),
.se(se), .si (), .so ()
) ;
assign sel_wrptr_plus1 = dbb_rst_l & inc_wr_ptr_c1 ;
assign sel_wrptr_same = dbb_rst_l & ~inc_wr_ptr_c1 ;
assign wrptr_plus1 = wrptr + 4'b1 ;
mux3ds #(4) mux_wrptr
(.dout (wrptr[3:0]),
.in0 (4'b0), .sel0 (~dbb_rst_l),
.in1 (wrptr_plus1_d1[3:0]), .sel1 (sel_wrptr_plus1),
.in2 (wrptr_d1[3:0]), .sel2 (sel_wrptr_same)
) ;
dff_s #(4) ff_array_wr_ptr_plus1
(.q (wrptr_plus1_d1[3:0]),
.din (wrptr_plus1[3:0]),
.clk (rclk),
.se(se), .si (), .so ()
) ;
dff_s #(4) ff_array_wr_ptr
(.q (wrptr_d1[3:0]),
.din (wrptr[3:0]),
.clk (rclk),
.se(se), .si (), .so ()
) ;
assign iq_array_wr_en = pcx_sctag_data_rdy_px2 ;
assign iq_array_wr_wl = wrptr ;
////////////////////////////////////////////////////////////////////////////////
//==================================================
// PX2 | C1 |
//==================================================
// gen rd en | gen rd en |
// | |
// mux slect new | gen rd ptr mux slect new |
// rd ptr | plus 1 rd ptr |
//==================================================
//
// Generation of Mux select for selecting between Read Pointer and it's
// Incremented value depends on the 'arbctl_iqsel_px2' signal. New value of
// write pointer is selected and transmitted to the IQ array for reading the
// array. Since 'arbctl_iqsel_px2' signal arrives late in the cycle this may
// create timing problem.
//
////////////////////////////////////////////////////////////////////////////////
assign iq_array_rd_en = iq_arbctl_vld_px2 ;
assign iq_array_rd_wl = rdptr ;
assign inc_rd_ptr_px2 = c1_reg_inst_vld |
(que_cnt_1 & sel_qcount_plus1 & arbctl_iqsel_px2) |
(que_cnt_1_plus & ~(que_cnt_2 & sel_qcount_minus1) &
arbctl_iqsel_px2) ;
assign rdptr_plus1 = rdptr_d1 + 4'b1 ;
mux2ds #(4) mux_rdptr
(.dout (rdptr[3:0]),
.in0 (rdptr_d1[3:0]), .sel0 (~inc_rd_ptr_px2),
.in1 (rdptr_plus1[3:0]), .sel1 (inc_rd_ptr_px2)
) ;
dffrl_s #(4) ff_array_rd_ptr
(.q (rdptr_d1[3:0]),
.din (rdptr[3:0]),
.clk (rclk), .rst_l(dbb_rst_l),
.se(se), .si (), .so ()
) ;
////////////////////////////////////////////////////////////////////////////////
//==============================================================================
// PX2 | C1 | C2
//==============================================================================
// latch pcx rdy | gen qcount inc, dec or | new Qcount vlue
// & iqsel signals | same sig. |
// | |
// | gen next compare values | new compare values
// | based on current qcount |
// | & inc, dec or same signal |
// | |
// | latch pcx rdy | gen qcount inc, dec or
// | & iqsel signals | same sig.
// | |
// | | gen next compare values
// | | based on current qcount
// | | & inc, dec or same signal
// | |
// | | latch pcx rdy
// | | & iqsel signals
////////////////////////////////////////////////////////////////////////////////
assign sel_qcount_plus1 = pcx_sctag_data_rdy_px2_d1 & ~arbctl_iqsel_px2_d1 ;
assign sel_qcount_minus1 = ~pcx_sctag_data_rdy_px2_d1 & arbctl_iqsel_px2_d1 ;
assign sel_qcount_same = ~(sel_qcount_plus1 | sel_qcount_minus1) ;
assign que_cnt_plus1 = que_cnt + 5'b1 ;
assign que_cnt_minus1 = que_cnt - 5'b1 ;
mux3ds #(5) mux_que_cnt
(.dout (next_que_cnt[4:0]),
.in0 (que_cnt_plus1[4:0]), .sel0 (sel_qcount_plus1),
.in1 (que_cnt_minus1[4:0]), .sel1 (sel_qcount_minus1),
.in2 (que_cnt[4:0]), .sel2 (sel_qcount_same)
) ;
dffrl_s #(5) ff_que_cnt
(.q (que_cnt[4:0]),
.din (next_que_cnt[4:0]),
.clk (rclk), .rst_l (dbb_rst_l),
.se(se), .si (), .so ()
) ;
assign que_cnt_0_p = ~(|que_cnt[4:0]) ;
assign que_cnt_1_p = (~que_cnt_1_plus & que_cnt[0]) ;
assign que_cnt_1_plus_p = |(que_cnt[4:1]) ;
assign que_cnt_2_p = ~(|que_cnt[4:2] | que_cnt[0]) & que_cnt[1] ;
assign que_cnt_2_plus_p = (|que_cnt[4:2]) | (&que_cnt[1:0]) ;
assign que_cnt_3_p = ~(|que_cnt[4:2]) & (&que_cnt[1:0]) ;
assign que_cnt_11_p = (que_cnt == 5'd11) ;
assign que_cnt_12_p = (que_cnt == 5'd12) ;
assign que_cnt_12_plus_p = (que_cnt > 5'd12) ;
assign que_cnt_13_p = (que_cnt == 5'd13) ;
assign que_cnt_13_plus_p = (que_cnt > 5'd13) ;
assign que_cnt_0_n = (que_cnt_0_p & sel_qcount_same) |
(que_cnt_1_p & sel_qcount_minus1) ;
assign que_cnt_1_n = (que_cnt_1_p & sel_qcount_same) |
(que_cnt_0_p & sel_qcount_plus1) |
(que_cnt_2_p & sel_qcount_minus1) ;
assign que_cnt_1_plus_n = (que_cnt_1_plus_p & (sel_qcount_same | sel_qcount_plus1)) |
(que_cnt_1_p & sel_qcount_plus1) |
(que_cnt_2_plus_p & sel_qcount_minus1) ;
assign que_cnt_2_n = (que_cnt_2_p & sel_qcount_same) |
(que_cnt_1_p & sel_qcount_plus1) |
(que_cnt_3_p & sel_qcount_minus1) ;
assign que_cnt_12_n = (que_cnt_12_p & sel_qcount_same) |
(que_cnt_11_p & sel_qcount_plus1) |
(que_cnt_13_p & sel_qcount_minus1) ;
assign que_cnt_12_plus_n = (que_cnt_12_plus_p & (sel_qcount_same | sel_qcount_plus1)) |
(que_cnt_12_p & sel_qcount_plus1) |
(que_cnt_13_plus_p & sel_qcount_minus1) ;
dff_s #(1) ff_que_cnt_0
(.q (que_cnt_0),
.din (que_cnt_0_n),
.clk (rclk),
.se(se), .si (), .so ()
) ;
dff_s #(1) ff_que_cnt_1
(.q (que_cnt_1),
.din (que_cnt_1_n),
.clk (rclk),
.se(se), .si (), .so ()
) ;
dff_s #(1) ff_que_cnt_1_plus
(.q (que_cnt_1_plus),
.din (que_cnt_1_plus_n),
.clk (rclk),
.se(se), .si (), .so ()
) ;
dff_s #(1) ff_que_cnt_2
(.q (que_cnt_2),
.din (que_cnt_2_n),
.clk (rclk),
.se(se), .si (), .so ()
) ;
dff_s #(1) ff_que_cnt_12
(.q (que_cnt_12),
.din (que_cnt_12_n),
.clk (rclk),
.se(se), .si (), .so ()
) ;
dff_s #(1) ff_que_cnt_12_plus
(.q (que_cnt_12_plus),
.din (que_cnt_12_plus_n),
.clk (rclk),
.se(se), .si (), .so ()
) ;
////////////////////////////////////////////////////////////////////////////////
// ----\/ FIX for macrotest \/---------
// sehold is high during macrotest. This will ensure that the array
// data is always chosen over the c1reg data during macrotest.
////////////////////////////////////////////////////////////////////////////////
assign sel_c1reg_over_iqarray = (wrptr_d1 == rdptr_d1) & ~sehold ;
////////////////////////////////////////////////////////////////////////////////
// MUX sel generation for IQ dp.
////////////////////////////////////////////////////////////////////////////////
//assign iqctl_sel_iq = ~c1_reg_inst_vld &
// (que_cnt_1_plus | (que_cnt_1 & ~arbctl_iqsel_px2_d1)) ;
assign set_iqctl_sel_iq = ~set_c1_reg_inst_vld &
(que_cnt_1_plus_n | (que_cnt_1_n & ~arbctl_iqsel_px2)) ;
dff_s #(1) ff_iqctl_sel_iq
(.q (iqctl_sel_iq),
.din (set_iqctl_sel_iq),
.clk (rclk),
.se (se), .si (), .so ()
) ;
//assign iqctl_sel_c1 = c1_reg_inst_vld ;
dff_s #(1) ff_iqctl_sel_c1
(.q (iqctl_sel_c1),
.din (set_c1_reg_inst_vld),
.clk (rclk),
.se (se), .si (), .so ()
) ;
//assign iqctl_sel_pcx = ~iqctl_sel_iq & ~iqctl_sel_c1 ;
assign set_iqctl_sel_pcx = ~set_iqctl_sel_iq & ~set_c1_reg_inst_vld ;
dff_s #(1) ff_iqctl_sel_pcx
(.q (iqctl_sel_pcx),
.din (set_iqctl_sel_pcx),
.clk (rclk),
.se (se), .si (), .so ()
) ;
dff_s #(1) ff_iqctl_sel_iq_d1
(.q (iqctl_sel_iq_d1),
.din (iqctl_sel_iq),
.clk (rclk),
.se (se), .si (), .so ()
) ;
assign iqctl_sel_iq_fe = iqctl_sel_iq_d1 & ~iqctl_sel_iq ;
assign iqctl_hold_rd = iqctl_sel_iq & ~arbctl_iqsel_px2 & ~iqctl_sel_iq_fe ;
////////////////////////////////////////////////////////////////////////////////
// IQ COUNT
//
// MUX here
// PQ PA PX1 PX2 C1 C2(counter update for pckt in PX2)
// PQ PA PX1 PX2 C1 C2
// PQ PA PX1 PX2 C1 C2
// PQ PA PX1 PX2 C1
// PQ PA PX1 PX2 C1 C2
// PQ PA PX1 PX2 C1
//
// When the stall is signalled, there can potentially be 5 packets in C1,
// PX2, Px1, PA and PQ that need to be queued in the IQ. The packet in PQ may
// be an atomic hence, the high water mark is 11.
////////////////////////////////////////////////////////////////////////////////
assign sctag_pcx_stall_pq = que_cnt_12_plus |
(que_cnt_12 & (pcx_sctag_data_rdy_px2_d1 &
~arbctl_iqsel_px2_d1)) ;
assign iq_arbctl_vld_px2 = pcx_sctag_data_rdy_px2 | c1_reg_inst_vld |
(que_cnt_1_plus | (que_cnt_1 & ~sel_qcount_minus1)) ;
endmodule |
module RegBankS2Sim;
reg clock;
reg reset;
reg [11:0] inst;
reg inst_en;
wire [7:0] out;
initial begin
#0 $dumpfile(`VCDFILE);
#0 $dumpvars;
#1000 $finish;
end
initial begin
#0 clock = 1;
forever #2 clock = ~clock;
end
initial begin
#0 reset = 0;
#1 reset = 1;
#4 reset = 0;
end
initial begin
#0.1 inst_en = 0;
// Test each instruction.
#8 inst = {`RegBankS2_LD0,8'hAE};
inst_en = 1;
#4 inst = {`RegBankS2_RDO,8'bxxxxxxx0};
inst_en = 1;
#4 inst = {`RegBankS2_LD1,8'hAB};
inst_en = 1;
#4 inst = {`RegBankS2_RDO,8'bxxxxxxx1};
inst_en = 1;
#4 inst = {`RegBankS2_NOP,8'bxxxxxxxx};
inst_en = 1;
// Test disabled instruction.
#4 inst = {`RegBankS2_LD1,8'h87};
inst_en = 0;
#4 inst = {`RegBankS2_LD0,8'hAE};
inst_en = 1;
// Test bad instruction.
#4 inst = {8'hF,8'hAB};
inst_en = 1;
#4 inst = {`RegBankS2_LD1,8'h27};
inst_en = 1;
#4 reset = 1;
#8 reset = 0;
#4 inst = {`RegBankS2_LD0,8'h1A};
inst_en = 1;
#4 inst = {`RegBankS2_NOP,8'bxxxxxxxx};
inst_en = 1;
end
RegBankS2
rbs2 (.clock(clock),
.reset(reset),
.inst(inst),
.inst_en(inst_en),
.out(out));
endmodule |
module sky130_fd_sc_hvl__lsbufhv2lv_simple (
//# {{data|Data Signals}}
input A,
output X
);
// Voltage supply signals
supply1 VPWR ;
supply0 VGND ;
supply1 LVPWR;
supply1 VPB ;
supply0 VNB ;
endmodule |
module sky130_fd_sc_ls__nand3 (
Y,
A,
B,
C
);
output Y;
input A;
input B;
input C;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule |
module top();
// Inputs are registered
reg D;
reg DATA_EN;
reg VPWR;
reg VGND;
// Outputs are wires
wire Q;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
DATA_EN = 1'bX;
VGND = 1'bX;
VPWR = 1'bX;
#20 D = 1'b0;
#40 DATA_EN = 1'b0;
#60 VGND = 1'b0;
#80 VPWR = 1'b0;
#100 D = 1'b1;
#120 DATA_EN = 1'b1;
#140 VGND = 1'b1;
#160 VPWR = 1'b1;
#180 D = 1'b0;
#200 DATA_EN = 1'b0;
#220 VGND = 1'b0;
#240 VPWR = 1'b0;
#260 VPWR = 1'b1;
#280 VGND = 1'b1;
#300 DATA_EN = 1'b1;
#320 D = 1'b1;
#340 VPWR = 1'bx;
#360 VGND = 1'bx;
#380 DATA_EN = 1'bx;
#400 D = 1'bx;
end
// Create a clock
reg CLK;
initial
begin
CLK = 1'b0;
end
always
begin
#5 CLK = ~CLK;
end
sky130_fd_sc_hs__udp_dff$PE_pp$PG dut (.D(D), .DATA_EN(DATA_EN), .VPWR(VPWR), .VGND(VGND), .Q(Q), .CLK(CLK));
endmodule |
module sky130_fd_sc_ms__dlygate4sd2 (
//# {{data|Data Signals}}
input A,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule |
module th24 ( y, a, b, c, d );
output y;
input a, b, c, d;
specify
specparam CDS_LIBNAME = "static";
specparam CDS_CELLNAME = "th24";
specparam CDS_VIEWNAME = "schematic";
endspecify
nfet_b N13 ( .d(net61), .g(y), .s(cds_globals.gnd_),
.b(cds_globals.gnd_));
nfet_b N12 ( .d(net41), .g(d), .s(net61), .b(cds_globals.gnd_));
nfet_b N11 ( .d(net50), .g(y), .s(cds_globals.gnd_),
.b(cds_globals.gnd_));
nfet_b N9 ( .d(net50), .g(d), .s(cds_globals.gnd_),
.b(cds_globals.gnd_));
nfet_b N8 ( .d(net41), .g(c), .s(net50), .b(cds_globals.gnd_));
nfet_b N7 ( .d(net44), .g(y), .s(cds_globals.gnd_),
.b(cds_globals.gnd_));
nfet_b N6 ( .d(net41), .g(b), .s(net44), .b(cds_globals.gnd_));
nfet_b N5 ( .d(net44), .g(d), .s(cds_globals.gnd_),
.b(cds_globals.gnd_));
nfet_b N3 ( .d(net44), .g(c), .s(cds_globals.gnd_),
.b(cds_globals.gnd_));
nfet_b N2 ( .d(net41), .g(a), .s(net44), .b(cds_globals.gnd_));
nfet_b N1 ( .d(net41), .g(a), .s(net66), .b(cds_globals.gnd_));
nfet_b N0 ( .d(net66), .g(b), .s(cds_globals.gnd_),
.b(cds_globals.gnd_));
pfet_b P11 ( .b(cds_globals.vdd_), .g(b), .s(cds_globals.vdd_),
.d(net49));
pfet_b P10 ( .b(cds_globals.vdd_), .g(a), .s(cds_globals.vdd_),
.d(net49));
pfet_b P9 ( .b(cds_globals.vdd_), .g(c), .s(net49), .d(net62));
pfet_b P8 ( .b(cds_globals.vdd_), .g(d), .s(net62), .d(net63));
pfet_b P7 ( .b(cds_globals.vdd_), .g(y), .s(net63), .d(net41));
pfet_b P6 ( .b(cds_globals.vdd_), .g(d), .s(net36), .d(net64));
pfet_b P5 ( .b(cds_globals.vdd_), .g(y), .s(net64), .d(net41));
pfet_b P4 ( .b(cds_globals.vdd_), .g(y), .s(net35), .d(net41));
pfet_b P3 ( .b(cds_globals.vdd_), .g(a), .s(cds_globals.vdd_),
.d(net65));
pfet_b P2 ( .b(cds_globals.vdd_), .g(b), .s(net65), .d(net36));
pfet_b P1 ( .b(cds_globals.vdd_), .g(c), .s(net36), .d(net35));
pfet_b P0 ( .b(cds_globals.vdd_), .g(d), .s(net35), .d(net41));
inv I11 ( y, net41);
endmodule |
module sky130_fd_sc_ls__maj3_1 (
X ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__maj3 base (
.X(X),
.A(A),
.B(B),
.C(C),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule |
module sky130_fd_sc_ls__maj3_1 (
X,
A,
B,
C
);
output X;
input A;
input B;
input C;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__maj3 base (
.X(X),
.A(A),
.B(B),
.C(C)
);
endmodule |
module ddr3_s4_uniphy_example (
input wire pll_ref_clk, // pll_ref_clk.clk
input wire global_reset_n, // global_reset.reset_n
input wire soft_reset_n, // soft_reset.reset_n
output wire [12:0] mem_a, // memory.mem_a
output wire [2:0] mem_ba, // .mem_ba
output wire mem_ck, // .mem_ck
output wire mem_ck_n, // .mem_ck_n
output wire mem_cke, // .mem_cke
output wire mem_cs_n, // .mem_cs_n
output wire [1:0] mem_dm, // .mem_dm
output wire mem_ras_n, // .mem_ras_n
output wire mem_cas_n, // .mem_cas_n
output wire mem_we_n, // .mem_we_n
output wire mem_reset_n, // .mem_reset_n
inout wire [15:0] mem_dq, // .mem_dq
inout wire [1:0] mem_dqs, // .mem_dqs
inout wire [1:0] mem_dqs_n, // .mem_dqs_n
output wire mem_odt, // .mem_odt
output wire local_init_done, // emif_status.local_init_done
output wire local_cal_success, // .local_cal_success
output wire local_cal_fail, // .local_cal_fail
input wire oct_rdn, // oct.rdn
input wire oct_rup, // .rup
output wire drv_status_pass, // drv_status.pass
output wire drv_status_fail, // .fail
output wire drv_status_test_complete, // .test_complete
output wire local_powerdn_ack, // local_powerdown.local_powerdn_ack
input wire local_powerdn_req // .local_powerdn_req
);
wire if0_afi_clk_clk; // if0:afi_clk -> [d0:clk, d0_avl_translator:clk, if0_avl_translator:clk, rst_controller:clk]
wire if0_afi_reset_reset; // if0:afi_reset_n -> [d0:reset_n, rst_controller:reset_in0]
wire [2:0] d0_avl_burstcount; // d0:avl_size -> d0_avl_translator:av_burstcount
wire d0_avl_waitrequest; // d0_avl_translator:av_waitrequest -> d0:avl_ready
wire [63:0] d0_avl_writedata; // d0:avl_wdata -> d0_avl_translator:av_writedata
wire [26:0] d0_avl_address; // d0:avl_addr -> d0_avl_translator:av_address
wire d0_avl_write; // d0:avl_write_req -> d0_avl_translator:av_write
wire d0_avl_beginbursttransfer; // d0:avl_burstbegin -> d0_avl_translator:av_beginbursttransfer
wire d0_avl_read; // d0:avl_read_req -> d0_avl_translator:av_read
wire [63:0] d0_avl_readdata; // d0_avl_translator:av_readdata -> d0:avl_rdata
wire [7:0] d0_avl_byteenable; // d0:avl_be -> d0_avl_translator:av_byteenable
wire d0_avl_readdatavalid; // d0_avl_translator:av_readdatavalid -> d0:avl_rdata_valid
wire d0_avl_translator_avalon_universal_master_0_waitrequest; // if0_avl_translator:uav_waitrequest -> d0_avl_translator:uav_waitrequest
wire [5:0] d0_avl_translator_avalon_universal_master_0_burstcount; // d0_avl_translator:uav_burstcount -> if0_avl_translator:uav_burstcount
wire [63:0] d0_avl_translator_avalon_universal_master_0_writedata; // d0_avl_translator:uav_writedata -> if0_avl_translator:uav_writedata
wire [26:0] d0_avl_translator_avalon_universal_master_0_address; // d0_avl_translator:uav_address -> if0_avl_translator:uav_address
wire d0_avl_translator_avalon_universal_master_0_lock; // d0_avl_translator:uav_lock -> if0_avl_translator:uav_lock
wire d0_avl_translator_avalon_universal_master_0_write; // d0_avl_translator:uav_write -> if0_avl_translator:uav_write
wire d0_avl_translator_avalon_universal_master_0_read; // d0_avl_translator:uav_read -> if0_avl_translator:uav_read
wire [63:0] d0_avl_translator_avalon_universal_master_0_readdata; // if0_avl_translator:uav_readdata -> d0_avl_translator:uav_readdata
wire d0_avl_translator_avalon_universal_master_0_debugaccess; // d0_avl_translator:uav_debugaccess -> if0_avl_translator:uav_debugaccess
wire [7:0] d0_avl_translator_avalon_universal_master_0_byteenable; // d0_avl_translator:uav_byteenable -> if0_avl_translator:uav_byteenable
wire d0_avl_translator_avalon_universal_master_0_readdatavalid; // if0_avl_translator:uav_readdatavalid -> d0_avl_translator:uav_readdatavalid
wire if0_avl_translator_avalon_anti_slave_0_waitrequest; // if0:avl_ready -> if0_avl_translator:av_waitrequest
wire [2:0] if0_avl_translator_avalon_anti_slave_0_burstcount; // if0_avl_translator:av_burstcount -> if0:avl_size
wire [63:0] if0_avl_translator_avalon_anti_slave_0_writedata; // if0_avl_translator:av_writedata -> if0:avl_wdata
wire [23:0] if0_avl_translator_avalon_anti_slave_0_address; // if0_avl_translator:av_address -> if0:avl_addr
wire if0_avl_translator_avalon_anti_slave_0_write; // if0_avl_translator:av_write -> if0:avl_write_req
wire if0_avl_translator_avalon_anti_slave_0_beginbursttransfer; // if0_avl_translator:av_beginbursttransfer -> if0:avl_burstbegin
wire if0_avl_translator_avalon_anti_slave_0_read; // if0_avl_translator:av_read -> if0:avl_read_req
wire [63:0] if0_avl_translator_avalon_anti_slave_0_readdata; // if0:avl_rdata -> if0_avl_translator:av_readdata
wire if0_avl_translator_avalon_anti_slave_0_readdatavalid; // if0:avl_rdata_valid -> if0_avl_translator:av_readdatavalid
wire [7:0] if0_avl_translator_avalon_anti_slave_0_byteenable; // if0_avl_translator:av_byteenable -> if0:avl_be
wire rst_controller_reset_out_reset; // rst_controller:reset_out -> [d0_avl_translator:reset, if0_avl_translator:reset]
ddr3_s4_uniphy_example_if0 if0 (
.pll_ref_clk (pll_ref_clk), // pll_ref_clk.clk
.global_reset_n (global_reset_n), // global_reset.reset_n
.soft_reset_n (soft_reset_n), // soft_reset.reset_n
.afi_clk (if0_afi_clk_clk), // afi_clk.clk
.afi_half_clk (), // afi_half_clk.clk
.afi_reset_n (if0_afi_reset_reset), // afi_reset.reset_n
.mem_a (mem_a), // memory.mem_a
.mem_ba (mem_ba), // .mem_ba
.mem_ck (mem_ck), // .mem_ck
.mem_ck_n (mem_ck_n), // .mem_ck_n
.mem_cke (mem_cke), // .mem_cke
.mem_cs_n (mem_cs_n), // .mem_cs_n
.mem_dm (mem_dm), // .mem_dm
.mem_ras_n (mem_ras_n), // .mem_ras_n
.mem_cas_n (mem_cas_n), // .mem_cas_n
.mem_we_n (mem_we_n), // .mem_we_n
.mem_reset_n (mem_reset_n), // .mem_reset_n
.mem_dq (mem_dq), // .mem_dq
.mem_dqs (mem_dqs), // .mem_dqs
.mem_dqs_n (mem_dqs_n), // .mem_dqs_n
.mem_odt (mem_odt), // .mem_odt
.avl_ready (if0_avl_translator_avalon_anti_slave_0_waitrequest), // avl.waitrequest_n
.avl_burstbegin (if0_avl_translator_avalon_anti_slave_0_beginbursttransfer), // .beginbursttransfer
.avl_addr (if0_avl_translator_avalon_anti_slave_0_address), // .address
.avl_rdata_valid (if0_avl_translator_avalon_anti_slave_0_readdatavalid), // .readdatavalid
.avl_rdata (if0_avl_translator_avalon_anti_slave_0_readdata), // .readdata
.avl_wdata (if0_avl_translator_avalon_anti_slave_0_writedata), // .writedata
.avl_be (if0_avl_translator_avalon_anti_slave_0_byteenable), // .byteenable
.avl_read_req (if0_avl_translator_avalon_anti_slave_0_read), // .read
.avl_write_req (if0_avl_translator_avalon_anti_slave_0_write), // .write
.avl_size (if0_avl_translator_avalon_anti_slave_0_burstcount), // .burstcount
.local_init_done (local_init_done), // status.local_init_done
.local_cal_success (local_cal_success), // .local_cal_success
.local_cal_fail (local_cal_fail), // .local_cal_fail
.oct_rdn (oct_rdn), // oct.rdn
.oct_rup (oct_rup), // .rup
.local_powerdn_ack (local_powerdn_ack), // local_powerdown.local_powerdn_ack
.local_powerdn_req (local_powerdn_req) // .local_powerdn_req
);
ddr3_s4_uniphy_example_d0 #(
.DEVICE_FAMILY ("Stratix IV"),
.TG_AVL_DATA_WIDTH (64),
.TG_AVL_ADDR_WIDTH (27),
.TG_AVL_WORD_ADDR_WIDTH (24),
.TG_AVL_SIZE_WIDTH (3),
.TG_AVL_BE_WIDTH (8),
.TG_GEN_BYTE_ADDR (1),
.TG_NUM_DRIVER_LOOP (1),
.TG_RANDOM_BYTE_ENABLE (1),
.TG_ENABLE_READ_COMPARE (1),
.TG_POWER_OF_TWO_BURSTS_ONLY (0),
.TG_BURST_ON_BURST_BOUNDARY (0),
.TG_TIMEOUT_COUNTER_WIDTH (30),
.TG_MAX_READ_LATENCY (20),
.TG_SINGLE_RW_SEQ_ADDR_COUNT (32),
.TG_SINGLE_RW_RAND_ADDR_COUNT (32),
.TG_SINGLE_RW_RAND_SEQ_ADDR_COUNT (32),
.TG_BLOCK_RW_SEQ_ADDR_COUNT (8),
.TG_BLOCK_RW_RAND_ADDR_COUNT (8),
.TG_BLOCK_RW_RAND_SEQ_ADDR_COUNT (8),
.TG_BLOCK_RW_BLOCK_SIZE (8),
.TG_TEMPLATE_STAGE_COUNT (4),
.TG_SEQ_ADDR_GEN_MIN_BURSTCOUNT (1),
.TG_SEQ_ADDR_GEN_MAX_BURSTCOUNT (4),
.TG_RAND_ADDR_GEN_MIN_BURSTCOUNT (1),
.TG_RAND_ADDR_GEN_MAX_BURSTCOUNT (4),
.TG_RAND_SEQ_ADDR_GEN_MIN_BURSTCOUNT (1),
.TG_RAND_SEQ_ADDR_GEN_MAX_BURSTCOUNT (4),
.TG_RAND_SEQ_ADDR_GEN_RAND_ADDR_PERCENT (50)
) d0 (
.clk (if0_afi_clk_clk), // avl_clock.clk
.reset_n (if0_afi_reset_reset), // avl_reset.reset_n
.pass (drv_status_pass), // status.pass
.fail (drv_status_fail), // .fail
.test_complete (drv_status_test_complete), // .test_complete
.avl_ready (~d0_avl_waitrequest), // avl.waitrequest_n
.avl_addr (d0_avl_address), // .address
.avl_size (d0_avl_burstcount), // .burstcount
.avl_wdata (d0_avl_writedata), // .writedata
.avl_rdata (d0_avl_readdata), // .readdata
.avl_write_req (d0_avl_write), // .write
.avl_read_req (d0_avl_read), // .read
.avl_rdata_valid (d0_avl_readdatavalid), // .readdatavalid
.avl_be (d0_avl_byteenable), // .byteenable
.avl_burstbegin (d0_avl_beginbursttransfer) // .beginbursttransfer
);
altera_merlin_master_translator #(
.AV_ADDRESS_W (27),
.AV_DATA_W (64),
.AV_BURSTCOUNT_W (3),
.AV_BYTEENABLE_W (8),
.UAV_ADDRESS_W (27),
.UAV_BURSTCOUNT_W (6),
.USE_READ (1),
.USE_WRITE (1),
.USE_BEGINBURSTTRANSFER (1),
.USE_BEGINTRANSFER (0),
.USE_CHIPSELECT (0),
.USE_BURSTCOUNT (1),
.USE_READDATAVALID (1),
.USE_WAITREQUEST (1),
.AV_SYMBOLS_PER_WORD (8),
.AV_ADDRESS_SYMBOLS (1),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (1),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_LINEWRAPBURSTS (0),
.AV_REGISTERINCOMINGSIGNALS (0)
) d0_avl_translator (
.clk (if0_afi_clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // reset.reset
.uav_address (d0_avl_translator_avalon_universal_master_0_address), // avalon_universal_master_0.address
.uav_burstcount (d0_avl_translator_avalon_universal_master_0_burstcount), // .burstcount
.uav_read (d0_avl_translator_avalon_universal_master_0_read), // .read
.uav_write (d0_avl_translator_avalon_universal_master_0_write), // .write
.uav_waitrequest (d0_avl_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.uav_readdatavalid (d0_avl_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.uav_byteenable (d0_avl_translator_avalon_universal_master_0_byteenable), // .byteenable
.uav_readdata (d0_avl_translator_avalon_universal_master_0_readdata), // .readdata
.uav_writedata (d0_avl_translator_avalon_universal_master_0_writedata), // .writedata
.uav_lock (d0_avl_translator_avalon_universal_master_0_lock), // .lock
.uav_debugaccess (d0_avl_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_address (d0_avl_address), // avalon_anti_master_0.address
.av_waitrequest (d0_avl_waitrequest), // .waitrequest
.av_burstcount (d0_avl_burstcount), // .burstcount
.av_byteenable (d0_avl_byteenable), // .byteenable
.av_beginbursttransfer (d0_avl_beginbursttransfer), // .beginbursttransfer
.av_read (d0_avl_read), // .read
.av_readdata (d0_avl_readdata), // .readdata
.av_readdatavalid (d0_avl_readdatavalid), // .readdatavalid
.av_write (d0_avl_write), // .write
.av_writedata (d0_avl_writedata), // .writedata
.av_begintransfer (1'b0), // (terminated)
.av_chipselect (1'b0), // (terminated)
.av_lock (1'b0), // (terminated)
.av_debugaccess (1'b0), // (terminated)
.uav_clken (), // (terminated)
.av_clken (1'b1) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (24),
.AV_DATA_W (64),
.UAV_DATA_W (64),
.AV_BURSTCOUNT_W (3),
.AV_BYTEENABLE_W (8),
.UAV_BYTEENABLE_W (8),
.UAV_ADDRESS_W (27),
.UAV_BURSTCOUNT_W (6),
.AV_READLATENCY (0),
.USE_READDATAVALID (1),
.USE_WAITREQUEST (1),
.USE_UAV_CLKEN (0),
.AV_SYMBOLS_PER_WORD (8),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) if0_avl_translator (
.clk (if0_afi_clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // reset.reset
.uav_address (d0_avl_translator_avalon_universal_master_0_address), // avalon_universal_slave_0.address
.uav_burstcount (d0_avl_translator_avalon_universal_master_0_burstcount), // .burstcount
.uav_read (d0_avl_translator_avalon_universal_master_0_read), // .read
.uav_write (d0_avl_translator_avalon_universal_master_0_write), // .write
.uav_waitrequest (d0_avl_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.uav_readdatavalid (d0_avl_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.uav_byteenable (d0_avl_translator_avalon_universal_master_0_byteenable), // .byteenable
.uav_readdata (d0_avl_translator_avalon_universal_master_0_readdata), // .readdata
.uav_writedata (d0_avl_translator_avalon_universal_master_0_writedata), // .writedata
.uav_lock (d0_avl_translator_avalon_universal_master_0_lock), // .lock
.uav_debugaccess (d0_avl_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_address (if0_avl_translator_avalon_anti_slave_0_address), // avalon_anti_slave_0.address
.av_write (if0_avl_translator_avalon_anti_slave_0_write), // .write
.av_read (if0_avl_translator_avalon_anti_slave_0_read), // .read
.av_readdata (if0_avl_translator_avalon_anti_slave_0_readdata), // .readdata
.av_writedata (if0_avl_translator_avalon_anti_slave_0_writedata), // .writedata
.av_beginbursttransfer (if0_avl_translator_avalon_anti_slave_0_beginbursttransfer), // .beginbursttransfer
.av_burstcount (if0_avl_translator_avalon_anti_slave_0_burstcount), // .burstcount
.av_byteenable (if0_avl_translator_avalon_anti_slave_0_byteenable), // .byteenable
.av_readdatavalid (if0_avl_translator_avalon_anti_slave_0_readdatavalid), // .readdatavalid
.av_waitrequest (~if0_avl_translator_avalon_anti_slave_0_waitrequest), // .waitrequest
.av_begintransfer (), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable () // (terminated)
);
altera_reset_controller #(
.NUM_RESET_INPUTS (1),
.OUTPUT_RESET_SYNC_EDGES ("deassert"),
.SYNC_DEPTH (2)
) rst_controller (
.reset_in0 (~if0_afi_reset_reset), // reset_in0.reset
.clk (if0_afi_clk_clk), // clk.clk
.reset_out (rst_controller_reset_out_reset), // reset_out.reset
.reset_in1 (1'b0), // (terminated)
.reset_in2 (1'b0), // (terminated)
.reset_in3 (1'b0), // (terminated)
.reset_in4 (1'b0), // (terminated)
.reset_in5 (1'b0), // (terminated)
.reset_in6 (1'b0), // (terminated)
.reset_in7 (1'b0), // (terminated)
.reset_in8 (1'b0), // (terminated)
.reset_in9 (1'b0), // (terminated)
.reset_in10 (1'b0), // (terminated)
.reset_in11 (1'b0), // (terminated)
.reset_in12 (1'b0), // (terminated)
.reset_in13 (1'b0), // (terminated)
.reset_in14 (1'b0), // (terminated)
.reset_in15 (1'b0) // (terminated)
);
endmodule |
module alu_mult(reg_A,reg_B,ctrl_ww,alu_op,result);
// Output signals...
// Result from copmputing an arithmetic or logical operation
output [0:127] result;
// Input signals
input [0:127] reg_A;
input [0:127] reg_B;
// Control signal bits - ww
input [0:1] ctrl_ww;
input [0:4] alu_op;
// Defining constants: parameter [name_of_constant] = value;
parameter max_128_bits = 128'hffffffffffffffffffffffffffffffff;
// Declare "reg" signals:
reg [0:127] result;
reg [0:127] p_pdt;
// Temporary reg variables for WW=8, for 8-bit multiplication
reg [0:15] p_pdt8a;
reg [0:15] p_pdt8a2;
reg [0:15] p_pdt8b;
reg [0:15] p_pdt8b2;
reg [0:15] p_pdt8c;
reg [0:15] p_pdt8c2;
reg [0:15] p_pdt8d;
reg [0:15] p_pdt8d2;
reg [0:15] p_pdt8e;
reg [0:15] p_pdt8e2;
reg [0:15] p_pdt8f;
reg [0:15] p_pdt8f2;
reg [0:15] p_pdt8g;
reg [0:15] p_pdt8g2;
reg [0:15] p_pdt8h;
reg [0:15] p_pdt8h2;
// Temporary reg variables for WW=16, for 16-bit multiplication
reg [0:31] p_pdt16a;
reg [0:31] p_pdt16a2;
reg [0:31] p_pdt16a3;
reg [0:31] p_pdt16b;
reg [0:31] p_pdt16b2;
reg [0:31] p_pdt16c;
reg [0:31] p_pdt16c2;
reg [0:31] p_pdt16d;
reg [0:31] p_pdt16d2;
integer sgn;
integer i;
integer j;
always @(reg_A or reg_B or ctrl_ww or alu_op)
begin
p_pdt=128'd0;
p_pdt8a=16'd0;
p_pdt8a2=16'd0;
p_pdt8b=16'd0;
p_pdt8b2=16'd0;
p_pdt8c=16'd0;
p_pdt8c2=16'd0;
p_pdt8d=16'd0;
p_pdt8d2=16'd0;
p_pdt8e=16'd0;
p_pdt8e2=16'd0;
p_pdt8f=16'd0;
p_pdt8f2=16'd0;
p_pdt8g=16'd0;
p_pdt8g2=16'd0;
p_pdt8h=16'd0;
p_pdt8h2=16'd0;
p_pdt16a=32'd0;
p_pdt16a2=32'd0;
p_pdt16b=32'd0;
p_pdt16b2=32'd0;
p_pdt16c=32'd0;
p_pdt16c2=32'd0;
p_pdt16d=32'd0;
p_pdt16d2=32'd0;
/**
* Based on the assigned arithmetic or logic instruction,
* carry out the appropriate function on the operands
*/
case(alu_op)
/**
* In computer science, a logical shift is a shift operator
* that shifts all the bits of its operand. Unlike an
* arithmetic shift, a logical shift does not preserve
* a number's sign bit or distinguish a number's exponent
* from its mantissa; every bit in the operand is simply
* moved a given number of bit positions, and the vacant
* bit-positions are filled in, generally with zeros
* (compare with a circular shift).
*
* SRL,SLL,Srli,sra,srai...
*/
// !!TROY PART 2 START!!
// ======================================================
// Signed Multiplication - even subfields
`aluwmules:
begin
case(ctrl_ww)
(`w8+2'b1): // aluwmules AND `w8
begin
// Process the 1st byte
// Process operand B
p_pdt8a2[8:15]=reg_B[0:7];
p_pdt8a2[0:7]=8'd0;
// Process operand A
if(reg_A[0]==1'd1)
begin
p_pdt8a[8:15]=1+~reg_A[0:7];
if(reg_B[0]==1'd1)
begin
p_pdt8a2[8:15]=1+~reg_B[0:7];
end
else
begin
p_pdt8a2[8:15]=reg_B[0:7];
end
end
else
begin
p_pdt8a[8:15]=reg_A[0:7];
end
p_pdt8a[0:7]=8'd0;
// Determine the 1st recoded bit and compute the result
if(p_pdt8a2[15]==1'd1)
begin
p_pdt[0:15]=p_pdt[0:15] - p_pdt8a[0:15];
end
else
begin
p_pdt[0:15]=p_pdt[0:15]+0;
end
// Multiply the numbers using the shift-and-add method
for(sgn=14; sgn>=8; sgn=sgn-1)
begin
/**
* Shift the multiplier to determine the partial
* product for this current shift
*/
if((p_pdt8a2[sgn]==1'b1) && (p_pdt8a2[sgn+1]==1'b0))
begin
// Compute the partial products and sum them up
p_pdt[0:15]=p_pdt[0:15]-(p_pdt8a<<(7-(sgn%8)));
end
else if((p_pdt8a2[sgn]==1'b0) && (p_pdt8a2[sgn+1]==1'b1))
begin
// Compute the partial products and sum them up
p_pdt[0:15]=p_pdt[0:15]+(p_pdt8a<<(7-(sgn%8)));
end
else
begin
p_pdt[0:15]=p_pdt[0:15]+0;
end
end
if(p_pdt8a[8]==1'd1)
begin
result[0:15]<=1+~p_pdt[0:15];
end
else
begin
result[0:15]<=p_pdt[0:15];
end
// Process the 2nd byte
// Process operand B
p_pdt8b2[8:15]=reg_B[16:23];
p_pdt8b2[0:7]=8'd0;
// Process operand A
if(reg_A[16]==1'd1)
begin
p_pdt8b[8:15]=1+~reg_A[16:23];
if(reg_B[16]==1'd1)
begin
p_pdt8b2[8:15]=1+~reg_B[16:23];
end
else
begin
p_pdt8b2[8:15]=reg_B[16:23];
end
end
else
begin
p_pdt8b[8:15]=reg_A[16:23];
end
p_pdt8b[0:7]=8'd0;
$display("p_pdt8b[0:15]",p_pdt8b[0:15]);
$display("p_pdt8b2[0:15]",p_pdt8b2[0:15]);
// Determine the 1st recoded bit and compute the result
if(p_pdt8b2[15]==1'd1)
begin
p_pdt[16:31]=p_pdt[16:31] - p_pdt8b[0:15];
end
else
begin
p_pdt[16:31]=p_pdt[16:31]+0;
end
$display("p_pdt[16:31]",p_pdt[16:31]);
// Multiply the numbers using the shift-and-add method
for(sgn=14; sgn>=8; sgn=sgn-1)
begin
/**
* Shift the multiplier to determine the partial
* product for this current shift
*/
if((p_pdt8b2[sgn]==1'b1) && (p_pdt8b2[sgn+1]==1'b0))
begin
// Compute the partial products and sum them up
p_pdt[16:31]=p_pdt[16:31]-(p_pdt8b<<(7-(sgn%8)));
$display("MINUSp_pdt[16:31]",p_pdt[16:31]);
end
else if((p_pdt8b2[sgn]==1'b0) && (p_pdt8b2[sgn+1]==1'b1))
begin
// Compute the partial products and sum them up
p_pdt[16:31]=p_pdt[16:31]+(p_pdt8b<<(7-(sgn%8)));
$display("ADDp_pdt[16:31]",p_pdt[16:31]);
end
else
begin
p_pdt[16:31]=p_pdt[16:31]+0;
$display("ZEROp_pdt[16:31]",p_pdt[16:31]);
end
end
if(p_pdt8b[8]==1'd1)
begin
result[16:31]<=1+~p_pdt[16:31];
$display("INVp_pdt[16:31]",p_pdt[16:31]);
end
else
begin
result[16:31]<=p_pdt[16:31];
$display("RESp_pdt[16:31]",p_pdt[16:31]);
end
// Process the 3rd byte
// Process operand B
p_pdt8c2[8:15]=reg_B[32:39];
p_pdt8c2[0:7]=8'd0;
// Process operand A
if(reg_A[32]==1'd1)
begin
p_pdt8c[8:15]=1+~reg_A[32:39];
if(reg_B[32]==1'd1)
begin
p_pdt8c2[8:15]=1+~reg_B[32:39];
end
else
begin
p_pdt8c2[8:15]=reg_B[32:39];
end
end
else
begin
p_pdt8c[8:15]=reg_A[32:39];
end
p_pdt8c[0:7]=8'd0;
// Determine the 1st recoded bit and compute the result
if(p_pdt8c2[15]==1'd1)
begin
p_pdt[32:47]=p_pdt[32:47] - p_pdt8c[0:15];
end
else
begin
p_pdt[32:47]=p_pdt[32:47]+0;
end
// Multiply the numbers using the shift-and-add method
for(sgn=14; sgn>=8; sgn=sgn-1)
begin
/**
* Shift the multiplier to determine the partial
* product for this current shift
*/
if((p_pdt8c2[sgn]==1'b1) && (p_pdt8c2[sgn+1]==1'b0))
begin
// Compute the partial products and sum them up
p_pdt[32:47]=p_pdt[32:47]-(p_pdt8c<<(7-(sgn%8)));
end
else if((p_pdt8c2[sgn]==1'b0) && (p_pdt8c2[sgn+1]==1'b1))
begin
// Compute the partial products and sum them up
p_pdt[32:47]=p_pdt[32:47]+(p_pdt8c<<(7-(sgn%8)));
end
else
begin
p_pdt[32:47]=p_pdt[32:47]+0;
end
end
if(p_pdt8c[8]==1'd1)
begin
result[32:47]<=1+~p_pdt[32:47];
end
else
begin
result[32:47]<=p_pdt[32:47];
end
// Process the 4th byte
// Process operand B
p_pdt8d2[8:15]=reg_B[48:55];
p_pdt8d2[0:7]=8'd0;
// Process operand A
if(reg_A[48]==1'd1)
begin
p_pdt8d[8:15]=1+~reg_A[48:55];
if(reg_B[48]==1'd1)
begin
p_pdt8d2[8:15]=1+~reg_B[48:55];
end
else
begin
p_pdt8d2[8:15]=reg_B[48:55];
end
end
else
begin
p_pdt8d[8:15]=reg_A[48:55];
end
p_pdt8d[0:7]=8'd0;
// Determine the 1st recoded bit and compute the result
if(p_pdt8d2[15]==1'd1)
begin
p_pdt[48:63]=p_pdt[48:63] - p_pdt8d[0:15];
end
else
begin
p_pdt[48:63]=p_pdt[48:63]+0;
end
// Multiply the numbers using the shift-and-add method
for(sgn=14; sgn>=8; sgn=sgn-1)
begin
/**
* Shift the multiplier to determine the partial
* product for this current shift
*/
if((p_pdt8d2[sgn]==1'b1) && (p_pdt8d2[sgn+1]==1'b0))
begin
// Compute the partial products and sum them up
p_pdt[48:63]=p_pdt[48:63]-(p_pdt8d<<(7-(sgn%8)));
end
else if((p_pdt8d2[sgn]==1'b0) && (p_pdt8d2[sgn+1]==1'b1))
begin
// Compute the partial products and sum them up
p_pdt[48:63]=p_pdt[48:63]+(p_pdt8d<<(7-(sgn%8)));
end
else
begin
p_pdt[48:63]=p_pdt[48:63]+0;
end
end
if(p_pdt8d[8]==1'd1)
begin
result[48:63]<=1+~p_pdt[48:63];
end
else
begin
result[48:63]<=p_pdt[48:63];
end
// Process the 5th byte
// Process operand B
p_pdt8e2[8:15]=reg_B[64:71];
p_pdt8e2[0:7]=8'd0;
// Process operand A
if(reg_A[64]==1'd1)
begin
p_pdt8e[8:15]=1+~reg_A[64:71];
if(reg_B[64]==1'd1)
begin
p_pdt8e2[8:15]=1+~reg_B[64:71];
end
else
begin
p_pdt8e2[8:15]=reg_B[64:71];
end
end
else
begin
p_pdt8e[8:15]=reg_A[64:71];
end
p_pdt8e[0:7]=8'd0;
// Determine the 1st recoded bit and compute the result
if(p_pdt8e2[15]==1'd1)
begin
p_pdt[64:79]=p_pdt[64:79] - p_pdt8e[0:15];
end
else
begin
p_pdt[64:79]=p_pdt[64:79]+0;
end
// Multiply the numbers using the shift-and-add method
for(sgn=14; sgn>=8; sgn=sgn-1)
begin
/**
* Shift the multiplier to determine the partial
* product for this current shift
*/
if((p_pdt8e2[sgn]==1'b1) && (p_pdt8e2[sgn+1]==1'b0))
begin
// Compute the partial products and sum them up
p_pdt[64:79]=p_pdt[64:79]-(p_pdt8e<<(7-(sgn%8)));
end
else if((p_pdt8e2[sgn]==1'b0) && (p_pdt8e2[sgn+1]==1'b1))
begin
// Compute the partial products and sum them up
p_pdt[64:79]=p_pdt[64:79]+(p_pdt8e<<(7-(sgn%8)));
end
else
begin
p_pdt[64:79]=p_pdt[64:79]+0;
end
end
if(p_pdt8e[8]==1'd1)
begin
result[64:79]<=1+~p_pdt[64:79];
end
else
begin
result[64:79]<=p_pdt[64:79];
end
// Process the 6th byte
// Process operand B
p_pdt8f2[8:15]=reg_B[80:87];
p_pdt8f2[0:7]=8'd0;
// Process operand A
if(reg_A[80]==1'd1)
begin
p_pdt8f[8:15]=1+~reg_A[80:87];
if(reg_B[80]==1'd1)
begin
p_pdt8f2[8:15]=1+~reg_B[80:87];
end
else
begin
p_pdt8f2[8:15]=reg_B[80:87];
end
end
else
begin
p_pdt8f[8:15]=reg_A[80:87];
end
p_pdt8f[0:7]=8'd0;
// Determine the 1st recoded bit and compute the result
if(p_pdt8f2[15]==1'd1)
begin
p_pdt[80:95]=p_pdt[80:95] - p_pdt8f[0:15];
end
else
begin
p_pdt[80:95]=p_pdt[80:95]+0;
end
// Multiply the numbers using the shift-and-add method
for(sgn=14; sgn>=8; sgn=sgn-1)
begin
/**
* Shift the multiplier to determine the partial
* product for this current shift
*/
if((p_pdt8f2[sgn]==1'b1) && (p_pdt8f2[sgn+1]==1'b0))
begin
// Compute the partial products and sum them up
p_pdt[80:95]=p_pdt[80:95]-(p_pdt8f<<(7-(sgn%8)));
end
else if((p_pdt8f2[sgn]==1'b0) && (p_pdt8f2[sgn+1]==1'b1))
begin
// Compute the partial products and sum them up
p_pdt[80:95]=p_pdt[80:95]+(p_pdt8f<<(7-(sgn%8)));
end
else
begin
p_pdt[80:95]=p_pdt[80:95]+0;
end
end
if(p_pdt8f[8]==1'd1)
begin
result[80:95]<=1+~p_pdt[80:95];
end
else
begin
result[80:95]<=p_pdt[80:95];
end
// Process the 7th byte
// Process operand B
p_pdt8g2[8:15]=reg_B[96:103];
p_pdt8g2[0:7]=8'd0;
// Process operand A
if(reg_A[96]==1'd1)
begin
p_pdt8g[8:15]=1+~reg_A[96:103];
if(reg_B[96]==1'd1)
begin
p_pdt8g2[8:15]=1+~reg_B[96:103];
end
else
begin
p_pdt8g2[8:15]=reg_B[96:103];
end
end
else
begin
p_pdt8g[8:15]=reg_A[96:103];
end
p_pdt8g[0:7]=8'd0;
// Determine the 1st recoded bit and compute the result
if(p_pdt8g2[15]==1'd1)
begin
p_pdt[96:111]=p_pdt[96:111] - p_pdt8g[0:15];
end
else
begin
p_pdt[96:111]=p_pdt[96:111]+0;
end
// Multiply the numbers using the shift-and-add method
for(sgn=14; sgn>=8; sgn=sgn-1)
begin
/**
* Shift the multiplier to determine the partial
* product for this current shift
*/
if((p_pdt8g2[sgn]==1'b1) && (p_pdt8g2[sgn+1]==1'b0))
begin
// Compute the partial products and sum them up
p_pdt[96:111]=p_pdt[96:111]-(p_pdt8g<<(7-(sgn%8)));
end
else if((p_pdt8g2[sgn]==1'b0) && (p_pdt8g2[sgn+1]==1'b1))
begin
// Compute the partial products and sum them up
p_pdt[96:111]=p_pdt[96:111]+(p_pdt8g<<(7-(sgn%8)));
end
else
begin
p_pdt[96:111]=p_pdt[96:111]+0;
end
end
if(p_pdt8g[8]==1'd1)
begin
result[96:111]<=1+~p_pdt[96:111];
end
else
begin
result[96:111]<=p_pdt[96:111];
end
// Process the 8th byte
// Process operand B
p_pdt8h2[8:15]=reg_B[112:119];
p_pdt8h2[0:7]=8'd0;
// Process operand A
if(reg_A[112]==1'd1)
begin
p_pdt8h[8:15]=1+~reg_A[112:119];
if(reg_B[112]==1'd1)
begin
p_pdt8h2[8:15]=1+~reg_B[112:119];
end
else
begin
p_pdt8h2[8:15]=reg_B[112:119];
end
end
else
begin
p_pdt8h[8:15]=reg_A[112:119];
end
p_pdt8h[0:7]=8'd0;
// Determine the 1st recoded bit and compute the result
if(p_pdt8h2[15]==1'd1)
begin
p_pdt[112:127]=p_pdt[112:127] - p_pdt8h[0:15];
end
else
begin
p_pdt[112:127]=p_pdt[112:127]+0;
end
// Multiply the numbers using the shift-and-add method
for(sgn=14; sgn>=8; sgn=sgn-1)
begin
/**
* Shift the multiplier to determine the partial
* product for this current shift
*/
if((p_pdt8h2[sgn]==1'b1) && (p_pdt8h2[sgn+1]==1'b0))
begin
// Compute the partial products and sum them up
p_pdt[112:127]=p_pdt[112:127]-(p_pdt8h<<(7-(sgn%8)));
end
else if((p_pdt8h2[sgn]==1'b0) && (p_pdt8h2[sgn+1]==1'b1))
begin
// Compute the partial products and sum them up
p_pdt[112:127]=p_pdt[112:127]+(p_pdt8h<<(7-(sgn%8)));
end
else
begin
p_pdt[112:127]=p_pdt[112:127]+0;
end
end
if(p_pdt8h[8]==1'd1)
begin
result[112:127]<=1+~p_pdt[112:127];
end
else
begin
result[112:127]<=p_pdt[112:127];
end
// =======================================================
// =======================================================
// =======================================================
end
(`w16+2'b1): // aluwmules AND `w16
begin
// Process the first pair of bytes
// Process operand B
p_pdt16a2[16:31]=reg_B[0:15];
p_pdt16a2[0:15]=16'd0;
// Process operand A
if(reg_A[0]==1'd1)
begin
p_pdt16a[16:31]=1+~reg_A[0:15];
if(reg_B[0]==1'd1)
begin
p_pdt16a2[16:31]=1+~reg_B[0:15];
end
else
begin
p_pdt16a2[16:31]=reg_B[0:15];
end
end
else
begin
p_pdt16a[16:31]=reg_A[0:15];
end
p_pdt16a[0:15]=16'd0;
// Determine the 1st recoded bit and compute the result
if(p_pdt16a2[31]==1'd1)
begin
p_pdt[0:31]=p_pdt[0:31] - p_pdt16a[0:31];
end
else
begin
p_pdt[0:31]=p_pdt[0:31]+0;
end
// Multiply the numbers using the shift-and-add method
for(sgn=30; sgn>=16; sgn=sgn-1)
begin
/**
* Shift the multiplier to determine the partial
* product for this current shift
*/
if((p_pdt16a2[sgn]==1'b1) && (p_pdt16a2[sgn+1]==1'b0))
begin
// Compute the partial products and sum them up
p_pdt[0:31]=p_pdt[0:31]-(p_pdt16a<<(15-(sgn%16)));
end
else if((p_pdt16a2[sgn]==1'b0) && (p_pdt16a2[sgn+1]==1'b1))
begin
// Compute the partial products and sum them up
p_pdt[0:31]=p_pdt[0:31]+(p_pdt16a<<(15-(sgn%16)));
end
else
begin
p_pdt[0:31]=p_pdt[0:31]+0;
end
end
if(p_pdt16a[16]==1'd1)
begin
result[0:31]<=1+~p_pdt[0:31];
end
else
begin
result[0:31]<=p_pdt[0:31];
end
// Process the second pair of bytes
// Process operand B
p_pdt16b2[16:31]=reg_B[32:47];
p_pdt16b2[0:15]=16'd0;
// Process operand A
if(reg_A[32]==1'd1)
begin
p_pdt16b[16:31]=1+~reg_A[32:47];
if(reg_B[32]==1'd1)
begin
p_pdt16b2[16:31]=1+~reg_B[32:47];
end
else
begin
p_pdt16b2[16:31]=reg_B[32:47];
end
end
else
begin
p_pdt16b[16:31]=reg_A[0:15];
end
p_pdt16b[0:15]=16'd0;
// Determine the 1st recoded bit and compute the result
if(p_pdt16b2[31]==1'd1)
begin
p_pdt[32:63]=p_pdt[32:63] - p_pdt16b[0:31];
end
else
begin
p_pdt[32:63]=p_pdt[32:63]+0;
end
// Multiply the numbers using the shift-and-add method
for(sgn=30; sgn>=16; sgn=sgn-1)
begin
/**
* Shift the multiplier to determine the partial
* product for this current shift
*/
if((p_pdt16b2[sgn]==1'b1) && (p_pdt16b2[sgn+1]==1'b0))
begin
// Compute the partial products and sum them up
p_pdt[32:63]=p_pdt[32:63]-(p_pdt16b<<(15-(sgn%16)));
end
else if((p_pdt16b2[sgn]==1'b0) && (p_pdt16b2[sgn+1]==1'b1))
begin
// Compute the partial products and sum them up
p_pdt[32:63]=p_pdt[32:63]+(p_pdt16b<<(15-(sgn%16)));
end
else
begin
p_pdt[32:63]=p_pdt[32:63]+0;
end
end
if(p_pdt16b[16]==1'd1)
begin
result[32:63]<=1+~p_pdt[32:63];
end
else
begin
result[32:63]<=p_pdt[32:63];
end
// Process the third pair of bytes
// Process operand B
p_pdt16c2[16:31]=reg_B[64:79];
p_pdt16c2[0:15]=16'd0;
// Process operand A
if(reg_A[64]==1'd1)
begin
p_pdt16c[16:31]=1+~reg_A[64:79];
if(reg_B[64]==1'd1)
begin
p_pdt16c2[16:31]=1+~reg_B[64:79];
end
else
begin
p_pdt16c2[16:31]=reg_B[64:79];
end
end
else
begin
p_pdt16c[16:31]=reg_A[64:79];
end
p_pdt16c[0:15]=16'd0;
// Determine the 1st recoded bit and compute the result
if(p_pdt16c2[31]==1'd1)
begin
p_pdt[64:95]=p_pdt[64:95] - p_pdt16c[0:31];
end
else
begin
p_pdt[64:95]=p_pdt[64:95]+0;
end
// Multiply the numbers using the shift-and-add method
for(sgn=30; sgn>=16; sgn=sgn-1)
begin
/**
* Shift the multiplier to determine the partial
* product for this current shift
*/
if((p_pdt16c2[sgn]==1'b1) && (p_pdt16c2[sgn+1]==1'b0))
begin
// Compute the partial products and sum them up
p_pdt[64:95]=p_pdt[64:95]-(p_pdt16c<<(15-(sgn%16)));
end
else if((p_pdt16c2[sgn]==1'b0) && (p_pdt16c2[sgn+1]==1'b1))
begin
// Compute the partial products and sum them up
p_pdt[64:95]=p_pdt[64:95]+(p_pdt16c<<(15-(sgn%16)));
end
else
begin
p_pdt[64:95]=p_pdt[64:95]+0;
end
end
if(p_pdt16c[16]==1'd1)
begin
result[64:95]<=1+~p_pdt[64:95];
end
else
begin
result[64:95]<=p_pdt[64:95];
end
// Process the fourth pair of bytes
// Process operand B
p_pdt16d2[16:31]=reg_B[96:111];
p_pdt16d2[0:15]=16'd0;
// Process operand A
if(reg_A[96]==1'd1)
begin
p_pdt16d[16:31]=1+~reg_A[96:111];
if(reg_B[96]==1'd1)
begin
p_pdt16d2[16:31]=1+~reg_B[96:111];
end
else
begin
p_pdt16d2[16:31]=reg_B[96:111];
end
end
else
begin
p_pdt16d[16:31]=reg_A[96:111];
end
p_pdt16d[0:15]=16'd0;
// Determine the 1st recoded bit and compute the result
if(p_pdt16d2[31]==1'd1)
begin
p_pdt[96:127]=p_pdt[96:127] - p_pdt16d[0:31];
end
else
begin
p_pdt[96:127]=p_pdt[96:127]+0;
end
// Multiply the numbers using the shift-and-add method
for(sgn=30; sgn>=16; sgn=sgn-1)
begin
/**
* Shift the multiplier to determine the partial
* product for this current shift
*/
if((p_pdt16d2[sgn]==1'b1) && (p_pdt16d2[sgn+1]==1'b0))
begin
// Compute the partial products and sum them up
p_pdt[96:127]=p_pdt[96:127]-(p_pdt16d<<(15-(sgn%16)));
end
else if((p_pdt16d2[sgn]==1'b0) && (p_pdt16d2[sgn+1]==1'b1))
begin
// Compute the partial products and sum them up
p_pdt[96:127]=p_pdt[96:127]+(p_pdt16d<<(15-(sgn%16)));
end
else
begin
p_pdt[96:127]=p_pdt[96:127]+0;
end
end
if(p_pdt16d[16]==1'd1)
begin
result[96:127]<=1+~p_pdt[96:127];
end
else
begin
result[96:127]<=p_pdt[96:127];
end
end
default: // aluwmules AND Default
begin
result<=128'd0;
end
endcase
end
// ======================================================
// Signed Multiplication - odd subfields
`aluwmulos:
begin
case(ctrl_ww)
(`w8+2'b1): // aluwmulos AND `w8
begin
// Process the 1st byte
// Process operand B
p_pdt8a2[8:15]=reg_B[8:15];
p_pdt8a2[0:7]=8'd0;
// Process operand A
if(reg_A[8]==1'd1)
begin
p_pdt8a[8:15]=1+~reg_A[8:15];
if(reg_B[8]==1'd1)
begin
p_pdt8a2[8:15]=1+~reg_B[8:15];
end
else
begin
p_pdt8a2[8:15]=reg_B[8:15];
end
end
else
begin
p_pdt8a[8:15]=reg_A[8:15];
end
p_pdt8a[0:7]=8'd0;
// Determine the 1st recoded bit and compute the result
if(p_pdt8a2[15]==1'd1)
begin
p_pdt[0:15]=p_pdt[0:15] - p_pdt8a[0:15];
end
else
begin
p_pdt[0:15]=p_pdt[0:15]+0;
end
// Multiply the numbers using the shift-and-add method
for(sgn=14; sgn>=8; sgn=sgn-1)
begin
/**
* Shift the multiplier to determine the partial
* product for this current shift
*/
if((p_pdt8a2[sgn]==1'b1) && (p_pdt8a2[sgn+1]==1'b0))
begin
// Compute the partial products and sum them up
p_pdt[0:15]=p_pdt[0:15]-(p_pdt8a<<(7-(sgn%8)));
end
else if((p_pdt8a2[sgn]==1'b0) && (p_pdt8a2[sgn+1]==1'b1))
begin
// Compute the partial products and sum them up
p_pdt[0:15]=p_pdt[0:15]+(p_pdt8a<<(7-(sgn%8)));
end
else
begin
p_pdt[0:15]=p_pdt[0:15]+0;
end
end
if(p_pdt8a[8]==1'd1)
begin
result[0:15]<=1+~p_pdt[0:15];
end
else
begin
result[0:15]<=p_pdt[0:15];
end
// Process the 2nd byte
// Process operand B
p_pdt8b2[8:15]=reg_B[24:31];
p_pdt8b2[0:7]=8'd0;
// Process operand A
if(reg_A[24]==1'd1)
begin
p_pdt8b[8:15]=1+~reg_A[24:31];
if(reg_B[24]==1'd1)
begin
p_pdt8b2[8:15]=1+~reg_B[24:31];
end
else
begin
p_pdt8b2[8:15]=reg_B[24:31];
end
end
else
begin
p_pdt8b[8:15]=reg_A[24:31];
end
p_pdt8b[0:7]=8'd0;
// Determine the 1st recoded bit and compute the result
if(p_pdt8b2[15]==1'd1)
begin
p_pdt[16:31]=p_pdt[16:31] - p_pdt8b[0:15];
end
else
begin
p_pdt[16:31]=p_pdt[16:31]+0;
end
// Multiply the numbers using the shift-and-add method
for(sgn=14; sgn>=8; sgn=sgn-1)
begin
/**
* Shift the multiplier to determine the partial
* product for this current shift
*/
if((p_pdt8b2[sgn]==1'b1) && (p_pdt8b2[sgn+1]==1'b0))
begin
// Compute the partial products and sum them up
p_pdt[16:31]=p_pdt[16:31]-(p_pdt8b<<(7-(sgn%8)));
end
else if((p_pdt8b2[sgn]==1'b0) && (p_pdt8b2[sgn+1]==1'b1))
begin
// Compute the partial products and sum them up
p_pdt[16:31]=p_pdt[16:31]+(p_pdt8b<<(7-(sgn%8)));
end
else
begin
p_pdt[16:31]=p_pdt[16:31]+0;
end
end
if(p_pdt8b[8]==1'd1)
begin
result[16:31]<=1+~p_pdt[16:31];
end
else
begin
result[16:31]<=p_pdt[16:31];
end
// Process the 3rd byte
// Process operand B
p_pdt8c2[8:15]=reg_B[40:47];
p_pdt8c2[0:7]=8'd0;
// Process operand A
if(reg_A[40]==1'd1)
begin
p_pdt8c[8:15]=1+~reg_A[40:47];
if(reg_B[40]==1'd1)
begin
p_pdt8c2[8:15]=1+~reg_B[40:47];
end
else
begin
p_pdt8c2[8:15]=reg_B[40:47];
end
end
else
begin
p_pdt8c[8:15]=reg_A[40:47];
end
p_pdt8c[0:7]=8'd0;
// Determine the 1st recoded bit and compute the result
if(p_pdt8c2[15]==1'd1)
begin
p_pdt[32:47]=p_pdt[32:47] - p_pdt8c[0:15];
end
else
begin
p_pdt[32:47]=p_pdt[32:47]+0;
end
// Multiply the numbers using the shift-and-add method
for(sgn=14; sgn>=8; sgn=sgn-1)
begin
/**
* Shift the multiplier to determine the partial
* product for this current shift
*/
if((p_pdt8c2[sgn]==1'b1) && (p_pdt8c2[sgn+1]==1'b0))
begin
// Compute the partial products and sum them up
p_pdt[32:47]=p_pdt[32:47]-(p_pdt8c<<(7-(sgn%8)));
end
else if((p_pdt8c2[sgn]==1'b0) && (p_pdt8c2[sgn+1]==1'b1))
begin
// Compute the partial products and sum them up
p_pdt[32:47]=p_pdt[32:47]+(p_pdt8c<<(7-(sgn%8)));
end
else
begin
p_pdt[32:47]=p_pdt[32:47]+0;
end
end
if(p_pdt8c[8]==1'd1)
begin
result[32:47]<=1+~p_pdt[32:47];
end
else
begin
result[32:47]<=p_pdt[32:47];
end
// Process the 4th byte
// Process operand B
p_pdt8d2[8:15]=reg_B[56:63];
p_pdt8d2[0:7]=8'd0;
// Process operand A
if(reg_A[56]==1'd1)
begin
p_pdt8d[8:15]=1+~reg_A[56:63];
if(reg_B[56]==1'd1)
begin
p_pdt8d2[8:15]=1+~reg_B[56:63];
end
else
begin
p_pdt8d2[8:15]=reg_B[56:63];
end
end
else
begin
p_pdt8d[8:15]=reg_A[56:63];
end
p_pdt8d[0:7]=8'd0;
// Determine the 1st recoded bit and compute the result
if(p_pdt8d2[15]==1'd1)
begin
p_pdt[48:63]=p_pdt[48:63] - p_pdt8d[0:15];
end
else
begin
p_pdt[48:63]=p_pdt[48:63]+0;
end
// Multiply the numbers using the shift-and-add method
for(sgn=14; sgn>=8; sgn=sgn-1)
begin
/**
* Shift the multiplier to determine the partial
* product for this current shift
*/
if((p_pdt8d2[sgn]==1'b1) && (p_pdt8d2[sgn+1]==1'b0))
begin
// Compute the partial products and sum them up
p_pdt[48:63]=p_pdt[48:63]-(p_pdt8d<<(7-(sgn%8)));
end
else if((p_pdt8d2[sgn]==1'b0) && (p_pdt8d2[sgn+1]==1'b1))
begin
// Compute the partial products and sum them up
p_pdt[48:63]=p_pdt[48:63]+(p_pdt8d<<(7-(sgn%8)));
end
else
begin
p_pdt[48:63]=p_pdt[48:63]+0;
end
end
if(p_pdt8d[8]==1'd1)
begin
result[48:63]<=1+~p_pdt[48:63];
end
else
begin
result[48:63]<=p_pdt[48:63];
end
// Process the 5th byte
// Process operand B
p_pdt8e2[8:15]=reg_B[72:79];
p_pdt8e2[0:7]=8'd0;
// Process operand A
if(reg_A[72]==1'd1)
begin
p_pdt8e[8:15]=1+~reg_A[72:79];
if(reg_B[72]==1'd1)
begin
p_pdt8e2[8:15]=1+~reg_B[72:79];
end
else
begin
p_pdt8e2[8:15]=reg_B[72:79];
end
end
else
begin
p_pdt8e[8:15]=reg_A[72:79];
end
p_pdt8e[0:7]=8'd0;
// Determine the 1st recoded bit and compute the result
if(p_pdt8e2[15]==1'd1)
begin
p_pdt[64:79]=p_pdt[64:79] - p_pdt8e[0:15];
end
else
begin
p_pdt[64:79]=p_pdt[64:79]+0;
end
// Multiply the numbers using the shift-and-add method
for(sgn=14; sgn>=8; sgn=sgn-1)
begin
/**
* Shift the multiplier to determine the partial
* product for this current shift
*/
if((p_pdt8e2[sgn]==1'b1) && (p_pdt8e2[sgn+1]==1'b0))
begin
// Compute the partial products and sum them up
p_pdt[64:79]=p_pdt[64:79]-(p_pdt8e<<(7-(sgn%8)));
end
else if((p_pdt8e2[sgn]==1'b0) && (p_pdt8e2[sgn+1]==1'b1))
begin
// Compute the partial products and sum them up
p_pdt[64:79]=p_pdt[64:79]+(p_pdt8e<<(7-(sgn%8)));
end
else
begin
p_pdt[64:79]=p_pdt[64:79]+0;
end
end
if(p_pdt8e[8]==1'd1)
begin
result[64:79]<=1+~p_pdt[64:79];
end
else
begin
result[64:79]<=p_pdt[64:79];
end
// Process the 6th byte
// Process operand B
p_pdt8f2[8:15]=reg_B[88:95];
p_pdt8f2[0:7]=8'd0;
// Process operand A
if(reg_A[88]==1'd1)
begin
p_pdt8f[8:15]=1+~reg_A[88:95];
if(reg_B[88]==1'd1)
begin
p_pdt8f2[8:15]=1+~reg_B[88:95];
end
else
begin
p_pdt8f2[8:15]=reg_B[88:95];
end
end
else
begin
p_pdt8f[8:15]=reg_A[88:95];
end
p_pdt8f[0:7]=8'd0;
// Determine the 1st recoded bit and compute the result
if(p_pdt8f2[15]==1'd1)
begin
p_pdt[80:95]=p_pdt[80:95] - p_pdt8f[0:15];
end
else
begin
p_pdt[80:95]=p_pdt[80:95]+0;
end
// Multiply the numbers using the shift-and-add method
for(sgn=14; sgn>=8; sgn=sgn-1)
begin
/**
* Shift the multiplier to determine the partial
* product for this current shift
*/
if((p_pdt8f2[sgn]==1'b1) && (p_pdt8f2[sgn+1]==1'b0))
begin
// Compute the partial products and sum them up
p_pdt[80:95]=p_pdt[80:95]-(p_pdt8f<<(7-(sgn%8)));
end
else if((p_pdt8f2[sgn]==1'b0) && (p_pdt8f2[sgn+1]==1'b1))
begin
// Compute the partial products and sum them up
p_pdt[80:95]=p_pdt[80:95]+(p_pdt8f<<(7-(sgn%8)));
end
else
begin
p_pdt[80:95]=p_pdt[80:95]+0;
end
end
if(p_pdt8f[8]==1'd1)
begin
result[80:95]<=1+~p_pdt[80:95];
end
else
begin
result[80:95]<=p_pdt[80:95];
end
// Process the 7th byte
// Process operand B
p_pdt8g2[8:15]=reg_B[104:111];
p_pdt8g2[0:7]=8'd0;
// Process operand A
if(reg_A[104]==1'd1)
begin
p_pdt8g[8:15]=1+~reg_A[104:111];
if(reg_B[104]==1'd1)
begin
p_pdt8g2[8:15]=1+~reg_B[104:111];
end
else
begin
p_pdt8g2[8:15]=reg_B[104:111];
end
end
else
begin
p_pdt8g[8:15]=reg_A[104:111];
end
p_pdt8g[0:7]=8'd0;
// Determine the 1st recoded bit and compute the result
if(p_pdt8g2[15]==1'd1)
begin
p_pdt[96:111]=p_pdt[96:111] - p_pdt8g[0:15];
end
else
begin
p_pdt[96:111]=p_pdt[96:111]+0;
end
// Multiply the numbers using the shift-and-add method
for(sgn=14; sgn>=8; sgn=sgn-1)
begin
/**
* Shift the multiplier to determine the partial
* product for this current shift
*/
if((p_pdt8g2[sgn]==1'b1) && (p_pdt8g2[sgn+1]==1'b0))
begin
// Compute the partial products and sum them up
p_pdt[96:111]=p_pdt[96:111]-(p_pdt8g<<(7-(sgn%8)));
end
else if((p_pdt8g2[sgn]==1'b0) && (p_pdt8g2[sgn+1]==1'b1))
begin
// Compute the partial products and sum them up
p_pdt[96:111]=p_pdt[96:111]+(p_pdt8g<<(7-(sgn%8)));
end
else
begin
p_pdt[96:111]=p_pdt[96:111]+0;
end
end
if(p_pdt8g[8]==1'd1)
begin
result[96:111]<=1+~p_pdt[96:111];
end
else
begin
result[96:111]<=p_pdt[96:111];
end
// Process the 8th byte
// Process operand B
p_pdt8h2[8:15]=reg_B[120:127];
p_pdt8h2[0:7]=8'd0;
// Process operand A
if(reg_A[120]==1'd1)
begin
p_pdt8h[8:15]=1+~reg_A[120:127];
if(reg_B[120]==1'd1)
begin
p_pdt8h2[8:15]=1+~reg_B[120:127];
end
else
begin
p_pdt8h2[8:15]=reg_B[120:127];
end
end
else
begin
p_pdt8h[8:15]=reg_A[120:127];
end
p_pdt8h[0:7]=8'd0;
// Determine the 1st recoded bit and compute the result
if(p_pdt8h2[15]==1'd1)
begin
p_pdt[112:127]=p_pdt[112:127] - p_pdt8h[0:15];
end
else
begin
p_pdt[112:127]=p_pdt[112:127]+0;
end
// Multiply the numbers using the shift-and-add method
for(sgn=14; sgn>=8; sgn=sgn-1)
begin
/**
* Shift the multiplier to determine the partial
* product for this current shift
*/
if((p_pdt8h2[sgn]==1'b1) && (p_pdt8h2[sgn+1]==1'b0))
begin
// Compute the partial products and sum them up
p_pdt[112:127]=p_pdt[112:127]-(p_pdt8h<<(7-(sgn%8)));
end
else if((p_pdt8h2[sgn]==1'b0) && (p_pdt8h2[sgn+1]==1'b1))
begin
// Compute the partial products and sum them up
p_pdt[112:127]=p_pdt[112:127]+(p_pdt8h<<(7-(sgn%8)));
end
else
begin
p_pdt[112:127]=p_pdt[112:127]+0;
end
end
if(p_pdt8h[8]==1'd1)
begin
result[112:127]<=1+~p_pdt[112:127];
end
else
begin
result[112:127]<=p_pdt[112:127];
end
// ---------------------------------------
end
(`w16+2'b1): // aluwmulos AND `w16
begin
// Process the first pair of bytes
// Process operand B
p_pdt16a2[16:31]=reg_B[16:31];
p_pdt16a2[0:15]=16'd0;
// Process operand A
if(reg_A[16]==1'd1)
begin
p_pdt16a[16:31]=1+~reg_A[16:31];
if(reg_B[16]==1'd1)
begin
p_pdt16a2[16:31]=1+~reg_B[16:31];
end
else
begin
p_pdt16a2[16:31]=reg_B[16:31];
end
end
else
begin
p_pdt16a[16:31]=reg_A[16:31];
end
p_pdt16a[0:15]=16'd0;
// Determine the 1st recoded bit and compute the result
if(p_pdt16a2[31]==1'd1)
begin
p_pdt[0:31]=p_pdt[0:31] - p_pdt16a[0:31];
end
else
begin
p_pdt[0:31]=p_pdt[0:31]+0;
end
// Multiply the numbers using the shift-and-add method
for(sgn=30; sgn>=16; sgn=sgn-1)
begin
/**
* Shift the multiplier to determine the partial
* product for this current shift
*/
if((p_pdt16a2[sgn]==1'b1) && (p_pdt16a2[sgn+1]==1'b0))
begin
// Compute the partial products and sum them up
p_pdt[0:31]=p_pdt[0:31]-(p_pdt16a<<(15-(sgn%16)));
end
else if((p_pdt16a2[sgn]==1'b0) && (p_pdt16a2[sgn+1]==1'b1))
begin
// Compute the partial products and sum them up
p_pdt[0:31]=p_pdt[0:31]+(p_pdt16a<<(15-(sgn%16)));
end
else
begin
p_pdt[0:31]=p_pdt[0:31]+0;
end
end
if(p_pdt16a[16]==1'd1)
begin
result[0:31]<=1+~p_pdt[0:31];
end
else
begin
result[0:31]<=p_pdt[0:31];
end
// Process the second pair of bytes
// Process operand B
p_pdt16b2[16:31]=reg_B[48:63];
p_pdt16b2[0:15]=16'd0;
// Process operand A
if(reg_A[48]==1'd1)
begin
p_pdt16b[16:31]=1+~reg_A[48:63];
if(reg_B[48]==1'd1)
begin
p_pdt16b2[16:31]=1+~reg_B[48:63];
end
else
begin
p_pdt16b2[16:31]=reg_B[48:63];
end
end
else
begin
p_pdt16b[16:31]=reg_A[48:63];
end
p_pdt16b[0:15]=16'd0;
// Determine the 1st recoded bit and compute the result
if(p_pdt16b2[31]==1'd1)
begin
p_pdt[32:63]=p_pdt[32:63] - p_pdt16b[0:31];
end
else
begin
p_pdt[32:63]=p_pdt[32:63]+0;
end
// Multiply the numbers using the shift-and-add method
for(sgn=30; sgn>=16; sgn=sgn-1)
begin
/**
* Shift the multiplier to determine the partial
* product for this current shift
*/
if((p_pdt16b2[sgn]==1'b1) && (p_pdt16b2[sgn+1]==1'b0))
begin
// Compute the partial products and sum them up
p_pdt[32:63]=p_pdt[32:63]-(p_pdt16b<<(15-(sgn%16)));
end
else if((p_pdt16b2[sgn]==1'b0) && (p_pdt16b2[sgn+1]==1'b1))
begin
// Compute the partial products and sum them up
p_pdt[32:63]=p_pdt[32:63]+(p_pdt16b<<(15-(sgn%16)));
end
else
begin
p_pdt[32:63]=p_pdt[32:63]+0;
end
end
if(p_pdt16b[16]==1'd1)
begin
result[32:63]<=1+~p_pdt[32:63];
end
else
begin
result[32:63]<=p_pdt[32:63];
end
// Process the third pair of bytes
// Process operand B
p_pdt16c2[16:31]=reg_B[80:95];
p_pdt16c2[0:15]=16'd0;
// Process operand A
if(reg_A[80]==1'd1)
begin
p_pdt16c[16:31]=1+~reg_A[80:95];
if(reg_B[80]==1'd1)
begin
p_pdt16c2[16:31]=1+~reg_B[80:95];
end
else
begin
p_pdt16c2[16:31]=reg_B[80:95];
end
end
else
begin
p_pdt16c[16:31]=reg_A[80:95];
end
p_pdt16c[0:15]=16'd0;
// Determine the 1st recoded bit and compute the result
if(p_pdt16c2[31]==1'd1)
begin
p_pdt[64:95]=p_pdt[64:95] - p_pdt16c[0:31];
end
else
begin
p_pdt[64:95]=p_pdt[64:95]+0;
end
// Multiply the numbers using the shift-and-add method
for(sgn=30; sgn>=16; sgn=sgn-1)
begin
/**
* Shift the multiplier to determine the partial
* product for this current shift
*/
if((p_pdt16c2[sgn]==1'b1) && (p_pdt16c2[sgn+1]==1'b0))
begin
// Compute the partial products and sum them up
p_pdt[64:95]=p_pdt[64:95]-(p_pdt16c<<(15-(sgn%16)));
end
else if((p_pdt16c2[sgn]==1'b0) && (p_pdt16c2[sgn+1]==1'b1))
begin
// Compute the partial products and sum them up
p_pdt[64:95]=p_pdt[64:95]+(p_pdt16c<<(15-(sgn%16)));
end
else
begin
p_pdt[64:95]=p_pdt[64:95]+0;
end
end
if(p_pdt16c[16]==1'd1)
begin
result[64:95]<=1+~p_pdt[64:95];
end
else
begin
result[64:95]<=p_pdt[64:95];
end
// Process the fourth pair of bytes
// Process operand B
p_pdt16d2[16:31]=reg_B[112:127];
p_pdt16d2[0:15]=16'd0;
// Process operand A
if(reg_A[112]==1'd1)
begin
p_pdt16d[16:31]=1+~reg_A[112:127];
if(reg_B[112]==1'd1)
begin
p_pdt16d2[16:31]=1+~reg_B[112:127];
end
else
begin
p_pdt16d2[16:31]=reg_B[112:127];
end
end
else
begin
p_pdt16d[16:31]=reg_A[112:127];
end
p_pdt16d[0:15]=16'd0;
// Determine the 1st recoded bit and compute the result
if(p_pdt16d2[31]==1'd1)
begin
p_pdt[96:127]=p_pdt[96:127] - p_pdt16d[0:31];
end
else
begin
p_pdt[96:127]=p_pdt[96:127]+0;
end
// Multiply the numbers using the shift-and-add method
for(sgn=30; sgn>=16; sgn=sgn-1)
begin
/**
* Shift the multiplier to determine the partial
* product for this current shift
*/
if((p_pdt16d2[sgn]==1'b1) && (p_pdt16d2[sgn+1]==1'b0))
begin
// Compute the partial products and sum them up
p_pdt[96:127]=p_pdt[96:127]-(p_pdt16d<<(15-(sgn%16)));
end
else if((p_pdt16d2[sgn]==1'b0) && (p_pdt16d2[sgn+1]==1'b1))
begin
// Compute the partial products and sum them up
p_pdt[96:127]=p_pdt[96:127]+(p_pdt16d<<(15-(sgn%16)));
end
else
begin
p_pdt[96:127]=p_pdt[96:127]+0;
end
end
if(p_pdt16d[16]==1'd1)
begin
result[96:127]<=1+~p_pdt[96:127];
end
else
begin
result[96:127]<=p_pdt[96:127];
end
end
default: // aluwmules AND Default
begin
result<=128'd0;
end
endcase
end
// ===========================================
// Unsigned Multiplication - even subfields
`aluwmuleu:
begin
case(ctrl_ww)
(`w8+2'b1):
begin
// 1st even byte
// extend operand B
p_pdt8a2={{8{1'b0}},reg_B[0+(16*0):7+(16*0)]};
// extend operand A
p_pdt8a={{8{1'b0}},reg_A[0+(16*0):7+(16*0)]};
// i loops through each bit to compute sum of partial products
for (i=15; i>7; i=i-1)
p_pdt[0+(16*0):15+(16*0)]=p_pdt[0+(16*0):15+(16*0)]
+ (p_pdt8a[i]?(p_pdt8a2<<(8'd15-i)):16'b0);
// 2nd even byte
// extend operand B
p_pdt8b2={{8{1'b0}},reg_B[0+(16*1):7+(16*1)]};
// extend operand A
p_pdt8b={{8{1'b0}},reg_A[0+(16*1):7+(16*1)]};
// i loops through each bit to compute sum of partial products
for (i=15; i>7; i=i-1)
p_pdt[0+(16*1):15+(16*1)]=p_pdt[0+(16*1):15+(16*1)]
+ (p_pdt8b[i]?(p_pdt8b2<<(8'd15-i)):16'b0);
// 3rd even byte
// extend operand B
p_pdt8c2={{8{1'b0}},reg_B[0+(16*2):7+(16*2)]};
// extend operand A
p_pdt8c={{8{1'b0}},reg_A[0+(16*2):7+(16*2)]};
// i loops through each bit to compute sum of partial products
for (i=15; i>7; i=i-1)
p_pdt[0+(16*2):15+(16*2)]=p_pdt[0+(16*2):15+(16*2)]
+ (p_pdt8c[i]?(p_pdt8c2<<(8'd15-i)):16'b0);
// 4th even byte
// extend operand B
p_pdt8d2={{8{1'b0}},reg_B[0+(16*3):7+(16*3)]};
// extend operand A
p_pdt8d={{8{1'b0}},reg_A[0+(16*3):7+(16*3)]};
// i loops through each bit to compute sum of partial products
for (i=15; i>7; i=i-1)
p_pdt[0+(16*3):15+(16*3)]=p_pdt[0+(16*3):15+(16*3)]
+ (p_pdt8d[i]?(p_pdt8d2<<(8'd15-i)):16'b0);
// 5th even byte
// extend operand B
p_pdt8e2={{8{1'b0}},reg_B[0+(16*4):7+(16*4)]};
// extend operand A
p_pdt8e={{8{1'b0}},reg_A[0+(16*4):7+(16*4)]};
// i loops through each bit to compute sum of partial products
for (i=15; i>7; i=i-1)
p_pdt[0+(16*4):15+(16*4)]=p_pdt[0+(16*4):15+(16*4)]
+ (p_pdt8e[i]?(p_pdt8e2<<(8'd15-i)):16'b0);
// 6th even byte
// extend operand B
p_pdt8f2={{8{1'b0}},reg_B[0+(16*5):7+(16*5)]};
// extend operand A
p_pdt8f={{8{1'b0}},reg_A[0+(16*5):7+(16*5)]};
// i loops through each bit to compute sum of partial products
for (i=15; i>7; i=i-1)
p_pdt[0+(16*5):15+(16*5)]=p_pdt[0+(16*5):15+(16*5)]
+ (p_pdt8f[i]?(p_pdt8f2<<(8'd15-i)):16'b0);
// 7th even byte
// extend operand B
p_pdt8g2={{8{1'b0}},reg_B[0+(16*6):7+(16*6)]};
// extend operand A
p_pdt8g={{8{1'b0}},reg_A[0+(16*6):7+(16*6)]};
// i loops through each bit to compute sum of partial products
for (i=15; i>7; i=i-1)
p_pdt[0+(16*6):15+(16*6)]=p_pdt[0+(16*6):15+(16*6)]
+ (p_pdt8g[i]?(p_pdt8g2<<(8'd15-i)):16'b0);
// 8th even byte
// extend operand B
p_pdt8h2={{8{1'b0}},reg_B[0+(16*7):7+(16*7)]};
// extend operand A
p_pdt8h={{8{1'b0}},reg_A[0+(16*7):7+(16*7)]};
// i loops through each bit to compute sum of partial products
for (i=15; i>7; i=i-1)
p_pdt[0+(16*7):15+(16*7)]=p_pdt[0+(16*7):15+(16*7)]
+ (p_pdt8h[i]?(p_pdt8h2<<(8'd15-i)):16'b0);
result<=p_pdt;
end // case (`w8+2'b1)
(`w16+2'b1):
begin
// 1st word
// extend operand B
p_pdt16a2={{16{1'b0}},reg_B[0+(32*0):15+(32*0)]};
// extend operand A
p_pdt16a={{16{1'b0}},reg_A[0+(32*0):15+(32*0)]};
// i loops through each bit to compute sum due to partial products
for (i=31; i>15; i=i-1)
p_pdt[0+(32*0):31+(32*0)]=p_pdt[0+(32*0):31+(32*0)]
+ (p_pdt16a[i]?(p_pdt16a2<<(8'd31-i)):32'b0);
// 2nd word
// extend operand B
p_pdt16b2={{16{1'b0}},reg_B[0+(32*1):15+(32*1)]};
// extend operand A
p_pdt16b={{16{1'b0}},reg_A[0+(32*1):15+(32*1)]};
// i loops through each bit to compute sum due to partial products
for (i=31; i>15; i=i-1)
p_pdt[0+(32*1):31+(32*1)]=p_pdt[0+(32*1):31+(32*1)]
+ (p_pdt16b[i]?(p_pdt16b2<<(8'd31-i)):32'b0);
// 3rd word
// extend operand B
p_pdt16c2={{16{1'b0}},reg_B[0+(32*2):15+(32*2)]};
// extend operand A
p_pdt16c={{16{1'b0}},reg_A[0+(32*2):15+(32*2)]};
// i loops through each bit to compute sum due to partial products
for (i=31; i>15; i=i-1)
p_pdt[0+(32*2):31+(32*2)]=p_pdt[0+(32*2):31+(32*2)]
+ (p_pdt16c[i]?(p_pdt16c2<<(8'd31-i)):32'b0);
// 4th word
// extend operand B
p_pdt16d2={{16{1'b0}},reg_B[0+(32*3):15+(32*3)]};
// extend operand A
p_pdt16d={{16{1'b0}},reg_A[0+(32*3):15+(32*3)]};
// i loops through each bit to compute sum due to partial products
for (i=31; i>15; i=i-1)
p_pdt[0+(32*3):31+(32*3)]=p_pdt[0+(32*3):31+(32*3)]
+ (p_pdt16d[i]?(p_pdt16d2<<(8'd31-i)):32'b0);
result<=p_pdt;
end // case (`w16+2'b1)
default:
begin
result<=128'd0;
end
endcase // case(ctrl_ww)
end
// ===================================
// Unsigned Multiplication - odd subfields
`aluwmulou:
begin
case(ctrl_ww)
(`w8+2'd1): // aluwmulou AND `w8
begin
p_pdt8a[8:15]=reg_A[8:15];
p_pdt8a[0:7]=8'd0;
p_pdt8a2[0:15]={{8{1'b0}},reg_B[8:15]};
for(sgn=15; sgn>=8; sgn=sgn-1)
begin
p_pdt[0:15]=p_pdt[0:15]+((p_pdt8a[sgn]==1'd1)?(p_pdt8a2<<(8'd15-sgn)):16'b0);
end
p_pdt8b[8:15]=reg_A[24:31];
p_pdt8b[0:7]=8'd0;
p_pdt8b2[0:15]={{8{1'b0}},reg_B[24:31]};
for(sgn=15; sgn>=8; sgn=sgn-1)
begin
p_pdt[16:31]=p_pdt[16:31]+((p_pdt8b[sgn]==1'd1)?(p_pdt8b2<<(8'd15-sgn)):16'b0);
end
p_pdt8c[8:15]=reg_A[40:47];
p_pdt8c[0:7]=8'd0;
p_pdt8c2[0:15]={{8{1'b0}},reg_B[40:47]};
for(sgn=15; sgn>=8; sgn=sgn-1)
begin
p_pdt[32:47]=p_pdt[32:47]+((p_pdt8c[sgn]==1'd1)?(p_pdt8c2<<(8'd15-sgn)):16'b0);
end
p_pdt8d[8:15]=reg_A[56:63];
p_pdt8d[0:7]=8'd0;
p_pdt8d2[0:15]={{8{1'b0}},reg_B[56:63]};
for(sgn=15; sgn>=8; sgn=sgn-1)
begin
p_pdt[48:63]=p_pdt[48:63]+((p_pdt8d[sgn]==1'd1)?(p_pdt8d2<<(8'd15-sgn)):16'b0);
end
p_pdt8e[8:15]=reg_A[72:79];
p_pdt8e[0:7]=8'd0;
p_pdt8e2[0:15]={{8{1'b0}},reg_B[72:79]};
for(sgn=15; sgn>=8; sgn=sgn-1)
begin
p_pdt[64:79]=p_pdt[64:79]+((p_pdt8e[sgn]==1'd1)?(p_pdt8e2<<(8'd15-sgn)):16'b0);
end
p_pdt8f[8:15]=reg_A[88:95];
p_pdt8f[0:7]=8'd0;
p_pdt8f2[0:15]={{8{1'b0}},reg_B[88:95]};
for(sgn=15; sgn>=8; sgn=sgn-1)
begin
p_pdt[80:95]=p_pdt[80:95]+((p_pdt8f[sgn]==1'd1)?(p_pdt8f2<<(8'd15-sgn)):16'b0);
end
p_pdt8g[8:15]=reg_A[104:111];
p_pdt8g[0:7]=8'd0;
p_pdt8g2[0:15]={{8{1'b0}},reg_B[104:111]};
for(sgn=15; sgn>=8; sgn=sgn-1)
begin
p_pdt[96:111]=p_pdt[96:111]+((p_pdt8g[sgn]==1'd1)?(p_pdt8g2<<(8'd15-sgn)):16'b0);
end
p_pdt8h[8:15]=reg_A[120:127];
p_pdt8h[0:7]=8'd0;
p_pdt8h2[0:15]={{8{1'b0}},reg_B[120:127]};
for(sgn=15; sgn>=8; sgn=sgn-1)
begin
p_pdt[112:127]=p_pdt[112:127]+((p_pdt8h[sgn]==1'd1)?(p_pdt8h2<<(8'd15-sgn)):16'b0);
end
result<=p_pdt;
end
(`w16+2'b01): // aluwmulou AND `w16
begin
p_pdt16a[0:31]={{16{1'b0}},reg_B[16:31]};
p_pdt16a2[0:31]={{16{1'b0}},reg_A[16:31]};
p_pdt16b[0:31]={{16{1'b0}},reg_B[48:63]};
p_pdt16b2[0:31]={{16{1'b0}},reg_A[48:63]};
p_pdt16c[0:31]={{16{1'b0}},reg_B[80:95]};
p_pdt16c2[0:31]={{16{1'b0}},reg_A[80:95]};
p_pdt16d[0:31]={{16{1'b0}},reg_B[112:127]};
p_pdt16d2[0:31]={{16{1'b0}},reg_A[112:127]};
for(sgn=31; sgn>=16; sgn=sgn-1)
begin
p_pdt[0:31]=p_pdt[0:31]+((p_pdt16a[sgn]==1'd1)?(p_pdt16a2<<(16'd31-sgn)):32'd0);
p_pdt[32:63]=p_pdt[32:63]+((p_pdt16b[sgn]==1'd1)?(p_pdt16b2<<(16'd31-sgn)):32'd0);
p_pdt[64:95]=p_pdt[64:95]+((p_pdt16c[sgn]==1'd1)?(p_pdt16c2<<(16'd31-sgn)):32'd0);
p_pdt[96:127]=p_pdt[96:127]+((p_pdt16d[sgn]==1'd1)?(p_pdt16d2<<(16'd31-sgn)):32'd0);
end
result<=p_pdt;
end
default: // aluwmulou AND Default
begin
result<=128'd0;
end
endcase
end
// !!TROY PART 2 END!!
// ==================================================================
default:
begin
// Default arithmetic/logic operation
result<=128'd0;
end
endcase
end
endmodule |
module RAT_prog_rom_0_0
(ADDRESS,
INSTRUCTION,
CLK);
input [9:0]ADDRESS;
output [17:0]INSTRUCTION;
(* x_interface_info = "xilinx.com:signal:clock:1.0 CLK CLK" *) input CLK;
wire [9:0]ADDRESS;
wire CLK;
wire [17:0]INSTRUCTION;
RAT_prog_rom_0_0_prog_rom U0
(.ADDRESS(ADDRESS),
.CLK(CLK),
.INSTRUCTION(INSTRUCTION));
endmodule |
module RAT_prog_rom_0_0_prog_rom
(INSTRUCTION,
CLK,
ADDRESS);
output [17:0]INSTRUCTION;
input CLK;
input [9:0]ADDRESS;
wire [9:0]ADDRESS;
wire CLK;
wire [17:0]INSTRUCTION;
wire [15:0]NLW_ram_1024_x_18_DIBDI_UNCONNECTED;
wire [1:0]NLW_ram_1024_x_18_DIPBDIP_UNCONNECTED;
wire [15:0]NLW_ram_1024_x_18_DOBDO_UNCONNECTED;
wire [1:0]NLW_ram_1024_x_18_DOPBDOP_UNCONNECTED;
(* CLOCK_DOMAINS = "INDEPENDENT" *)
(* XILINX_LEGACY_PRIM = "RAMB16_S18" *)
(* XILINX_TRANSFORM_PINMAP = "ADDR[0]:ADDRARDADDR[4] ADDR[1]:ADDRARDADDR[5] ADDR[2]:ADDRARDADDR[6] ADDR[3]:ADDRARDADDR[7] ADDR[4]:ADDRARDADDR[8] ADDR[5]:ADDRARDADDR[9] ADDR[6]:ADDRARDADDR[10] ADDR[7]:ADDRARDADDR[11] ADDR[8]:ADDRARDADDR[12] ADDR[9]:ADDRARDADDR[13] CLK:CLKARDCLK DI[0]:DIADI[0] DI[10]:DIADI[10] DI[11]:DIADI[11] DI[12]:DIADI[12] DI[13]:DIADI[13] DI[14]:DIADI[14] DI[15]:DIADI[15] DI[1]:DIADI[1] DI[2]:DIADI[2] DI[3]:DIADI[3] DI[4]:DIADI[4] DI[5]:DIADI[5] DI[6]:DIADI[6] DI[7]:DIADI[7] DI[8]:DIADI[8] DI[9]:DIADI[9] DIP[0]:DIPADIP[0] DIP[1]:DIPADIP[1] DO[0]:DOADO[0] DO[10]:DOADO[10] DO[11]:DOADO[11] DO[12]:DOADO[12] DO[13]:DOADO[13] DO[14]:DOADO[14] DO[15]:DOADO[15] DO[1]:DOADO[1] DO[2]:DOADO[2] DO[3]:DOADO[3] DO[4]:DOADO[4] DO[5]:DOADO[5] DO[6]:DOADO[6] DO[7]:DOADO[7] DO[8]:DOADO[8] DO[9]:DOADO[9] DOP[0]:DOPADOP[0] DOP[1]:DOPADOP[1] EN:ENARDEN SSR:RSTRAMARSTRAM WE:WEA[1],WEA[0]" *)
(* box_type = "PRIMITIVE" *)
RAMB18E1 #(
.DOA_REG(0),
.DOB_REG(0),
.INITP_00(256'h000000000000000000000000000000000000000000000000000000CF00000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000080804A400A5A6BFF2A20),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(18'h00000),
.INIT_B(18'h00000),
.READ_WIDTH_A(18),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SRVAL_A(18'h00000),
.SRVAL_B(18'h00000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_WIDTH_A(18))
ram_1024_x_18
(.ADDRARDADDR({ADDRESS,1'b1,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
.CLKARDCLK(CLK),
.CLKBWRCLK(1'b0),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIBDI(NLW_ram_1024_x_18_DIBDI_UNCONNECTED[15:0]),
.DIPADIP({1'b0,1'b0}),
.DIPBDIP(NLW_ram_1024_x_18_DIPBDIP_UNCONNECTED[1:0]),
.DOADO(INSTRUCTION[15:0]),
.DOBDO(NLW_ram_1024_x_18_DOBDO_UNCONNECTED[15:0]),
.DOPADOP(INSTRUCTION[17:16]),
.DOPBDOP(NLW_ram_1024_x_18_DOPBDOP_UNCONNECTED[1:0]),
.ENARDEN(1'b1),
.ENBWREN(1'b0),
.REGCEAREGCE(1'b0),
.REGCEB(1'b0),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.WEA({1'b0,1'b0}),
.WEBWE({1'b0,1'b0,1'b0,1'b0}));
endmodule |
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule |
module sky130_fd_sc_hs__fahcin (
COUT,
SUM ,
A ,
B ,
CIN ,
VPWR,
VGND
);
// Module ports
output COUT;
output SUM ;
input A ;
input B ;
input CIN ;
input VPWR;
input VGND;
// Local signals
wire ci ;
wire xor0_out_SUM ;
wire u_vpwr_vgnd0_out_SUM ;
wire a_b ;
wire a_ci ;
wire b_ci ;
wire or0_out_COUT ;
wire u_vpwr_vgnd1_out_COUT;
// Name Output Other arguments
not not0 (ci , CIN );
xor xor0 (xor0_out_SUM , A, B, ci );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_SUM , xor0_out_SUM, VPWR, VGND);
buf buf0 (SUM , u_vpwr_vgnd0_out_SUM );
and and0 (a_b , A, B );
and and1 (a_ci , A, ci );
and and2 (b_ci , B, ci );
or or0 (or0_out_COUT , a_b, a_ci, b_ci );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd1 (u_vpwr_vgnd1_out_COUT, or0_out_COUT, VPWR, VGND);
buf buf1 (COUT , u_vpwr_vgnd1_out_COUT );
endmodule |
module sparc_ffu_ctl_visctl (/*AUTOARG*/
// Outputs
ctl_vis_sel_add, ctl_vis_sel_log, ctl_vis_sel_align,
ctl_vis_add32, ctl_vis_subtract, ctl_vis_cin, ctl_vis_align0,
ctl_vis_align2, ctl_vis_align4, ctl_vis_align6, ctl_vis_align_odd,
ctl_vis_log_sel_pass, ctl_vis_log_sel_nand, ctl_vis_log_sel_nor,
ctl_vis_log_sel_xor, ctl_vis_log_invert_rs1,
ctl_vis_log_invert_rs2, ctl_vis_log_constant,
ctl_vis_log_pass_const, ctl_vis_log_pass_rs1,
ctl_vis_log_pass_rs2, vis_result, illegal_vis_e, vis_nofrf_e,
visop_m, visop_w_vld, vis_wen_next, fpu_rnd,
ffu_exu_rsr_data_hi_m, ffu_exu_rsr_data_mid_m,
ffu_exu_rsr_data_lo_m, ctl_dp_wsr_data_w2, ctl_dp_gsr_wsr_w2,
ctl_dp_thr_e,
// Inputs
clk, se, reset, opf, tid_w2, tid_e, tid, visop_e, kill_w,
ifu_tlu_sraddr_d, exu_ffu_wsr_inst_e, exu_ffu_gsr_align_m,
exu_ffu_gsr_rnd_m, exu_ffu_gsr_mask_m, exu_ffu_gsr_scale_m,
ifu_ffu_rnd_e, dp_ctl_fsr_rnd, flush_w2, thr_match_mw2,
thr_match_ww2, ifu_tlu_inst_vld_w, ue_trap_w3, frs1_e, frs2_e,
frd_e, rollback_c3, rollback_rs2_w2, visop, rollback_rs1_w3,
dp_ctl_gsr_mask_e, dp_ctl_gsr_scale_e
) ;
input clk;
input se;
input reset;
input [8:0] opf;
input [1:0] tid_w2;
input [1:0] tid_e;
input [1:0] tid;
input visop_e;
input kill_w;
input [6:0] ifu_tlu_sraddr_d;
input exu_ffu_wsr_inst_e;
input [2:0] exu_ffu_gsr_align_m;
input [2:0] exu_ffu_gsr_rnd_m;
input [31:0] exu_ffu_gsr_mask_m;
input [4:0] exu_ffu_gsr_scale_m;
input [2:0] ifu_ffu_rnd_e;
input [1:0] dp_ctl_fsr_rnd;
input flush_w2;
input thr_match_mw2;
input thr_match_ww2;
input ifu_tlu_inst_vld_w;
input ue_trap_w3;
input [4:0] frs1_e;
input [4:0] frs2_e;
input [4:0] frd_e;
input rollback_c3;
input rollback_rs2_w2;
input visop;
input rollback_rs1_w3;
input [31:0] dp_ctl_gsr_mask_e;
input [4:0] dp_ctl_gsr_scale_e;
output ctl_vis_sel_add;
output ctl_vis_sel_log;
output ctl_vis_sel_align;
output ctl_vis_add32;
output ctl_vis_subtract;
output ctl_vis_cin;
output ctl_vis_align0;
output ctl_vis_align2;
output ctl_vis_align4;
output ctl_vis_align6;
output ctl_vis_align_odd;
output ctl_vis_log_sel_pass;
output ctl_vis_log_sel_nand;
output ctl_vis_log_sel_nor;
output ctl_vis_log_sel_xor;
output ctl_vis_log_invert_rs1;
output ctl_vis_log_invert_rs2;
output ctl_vis_log_constant;
output ctl_vis_log_pass_const;
output ctl_vis_log_pass_rs1;
output ctl_vis_log_pass_rs2;
output vis_result;
output illegal_vis_e;
output vis_nofrf_e;
output visop_m;
output visop_w_vld;
output vis_wen_next;
output [1:0] fpu_rnd;
output [31:0] ffu_exu_rsr_data_hi_m;
output [2:0] ffu_exu_rsr_data_mid_m;
output [7:0] ffu_exu_rsr_data_lo_m;
output [36:0] ctl_dp_wsr_data_w2;
output [3:0] ctl_dp_gsr_wsr_w2;
output [3:0] ctl_dp_thr_e;
wire illegal_rs1_e;
wire illegal_rs2_e;
wire illegal_siam_e;
wire rs2_check_nonzero_e;
wire rs1_check_nonzero_e;
wire visop_e;
wire issue_visop_e;
wire visop_m;
wire visop_w;
wire visop_w_vld;
wire visop_w2_vld;
wire visop_w2;
wire visop_w3;
wire visop_w3_vld;
wire add;
wire align;
wire logic;
wire siam;
wire alignaddr;
wire opf_log_zero;
wire opf_log_one;
wire opf_log_src1;
wire opf_log_src2;
wire opf_log_not1;
wire opf_log_not2;
wire opf_log_or;
wire opf_log_nor;
wire opf_log_and;
wire opf_log_nand;
wire opf_log_xor;
wire opf_log_xnor;
wire opf_log_ornot1;
wire opf_log_ornot2;
wire opf_log_andnot1;
wire opf_log_andnot2;
wire invert_rs1_next;
wire invert_rs2_next;
wire log_pass_rs1_next;
wire log_pass_rs2_next;
wire log_pass_rs1;
wire log_pass_rs2;
wire [2:0] t0_gsr_rnd;
wire [2:0] t1_gsr_rnd;
wire [2:0] t2_gsr_rnd;
wire [2:0] t3_gsr_rnd;
wire [2:0] t0_gsr_align;
wire [2:0] t1_gsr_align;
wire [2:0] t2_gsr_align;
wire [2:0] t3_gsr_align;
wire [2:0] t0_gsr_rnd_next;
wire [2:0] t1_gsr_rnd_next;
wire [2:0] t2_gsr_rnd_next;
wire [2:0] t3_gsr_rnd_next;
wire [2:0] t0_gsr_align_next;
wire [2:0] t1_gsr_align_next;
wire [2:0] t2_gsr_align_next;
wire [2:0] t3_gsr_align_next;
wire [2:0] gsr_rnd_e;
wire [2:0] gsr_align_e;
wire t0_rnd_wen_l;
wire t0_gsr_wsr_w2;
wire t0_siam_w2;
wire t0_align_wen_l;
wire t0_alignaddr_w2;
wire t1_rnd_wen_l;
wire t1_gsr_wsr_w2;
wire t1_siam_w2;
wire t1_align_wen_l;
wire t1_alignaddr_w2;
wire t2_rnd_wen_l;
wire t2_gsr_wsr_w2;
wire t2_siam_w2;
wire t2_align_wen_l;
wire t2_alignaddr_w2;
wire t3_rnd_wen_l;
wire t3_gsr_wsr_w2;
wire t3_siam_w2;
wire t3_align_wen_l;
wire t3_alignaddr_w2;
wire [2:0] siam_rnd;
wire [3:0] thr_w2;
wire [3:0] ctl_dp_thr_e;
wire [3:0] thr_fp;
wire gsr_addr_d;
wire gsr_addr_e;
wire wgsr_e;
wire wgsr_m;
wire wgsr_w;
wire wgsr_vld_m;
wire wgsr_vld_w;
wire wgsr_vld_w2;
wire wgsr_w2;
wire [2:0] gsr_rnd;
wire [1:0] fpu_rnd_next;
wire [2:0] gsr_align;
wire [2:0] gsr_align_d1;
wire [2:0] align_addr_data_w2;
wire [2:0] wgsr_align_offset_w;
wire [2:0] wgsr_rnd_w;
wire [2:0] wgsr_align_offset_w2;
wire [2:0] wgsr_rnd_w2;
wire [36:0] wsr_data_m;
wire [36:0] wsr_data_w;
//////////////////////////////////////
// VIS PIPELINE
//------------------------------------
// Note: rs2_ce, rs2_ue, rs1_ue will kill vis instruction
// in addition to any traps, etc.
// These are incorporated into the "kill" signals
// E: ren rs2
// M: ren rs1
// W: rs2 data ready, check rs2 ecc
// W2: rs1 data ready, check rs1 ecc
// W3: execute vis operation (result written to rs2/rd flop)
// W4: gen ecc and write to frf
dff_s visop_e2m(.din(issue_visop_e), .clk(clk), .q(visop_m), .si(), .so(), .se(se));
dff_s visop_m2w(.din(visop_m), .clk(clk), .q(visop_w), .si(), .so(), .se(se));
dff_s visop_w2w2(.din(visop_w_vld), .clk(clk), .q(visop_w2), .si(), .so(), .se(se));
dff_s visop_w22w3(.din(visop_w2_vld), .clk(clk), .q(visop_w3), .si(), .so(), .se(se));
assign issue_visop_e = visop_e | visop & rollback_c3;
// only check kills in w since they are accumulated into kill_w
assign visop_w_vld = visop_w & ~kill_w;
assign visop_w2_vld = visop_w2 & ~flush_w2 & ~rollback_rs2_w2;
assign visop_w3_vld = visop_w3 & ~ue_trap_w3 & ~rollback_rs1_w3;
assign vis_result = visop_w3_vld;
assign vis_wen_next = vis_result & ~siam & ~alignaddr;
////////////////////////////////////
// Decode opf
////////////////////////////////////
assign add = ~opf[8] & ~opf[7] & opf[6] & ~opf[5] & opf[4] & ~opf[3];
assign align = ~opf[8] & ~opf[7] & opf[6] & ~opf[5] & ~opf[4] & opf[3] & ~opf[2] & ~opf[1] & ~opf[0];
assign logic = ~opf[8] & ~opf[7] & opf[6] & opf[5];
assign siam = ~opf[8] & opf[7] & ~opf[6] & ~opf[5] & ~opf[4] & ~opf[3] & ~opf[2] & ~opf[1] & opf[0];
assign alignaddr = ~opf[8] & ~opf[7] & ~opf[6] & ~opf[5] & opf[4] & opf[3] & ~opf[2] & ~opf[0]; //alignaddress
assign illegal_vis_e = (visop_e & ~(add | align | logic | siam | alignaddr) |
illegal_rs1_e | illegal_rs2_e | illegal_siam_e);
assign rs1_check_nonzero_e = visop_e & (siam | (logic & (opf_log_zero | opf_log_one | opf_log_src2 | opf_log_not2)));
assign rs2_check_nonzero_e = visop_e & logic & (opf_log_zero | opf_log_one | opf_log_src1 | opf_log_not1);
assign illegal_rs1_e = (frs1_e[4:0] != 5'b00000) & rs1_check_nonzero_e;
assign illegal_rs2_e = (frs2_e[4:0] != 5'b00000) & rs2_check_nonzero_e;
assign illegal_siam_e = ((frd_e[4:0] != 5'b00000) | frs2_e[4] | frs2_e[3]) & siam & visop_e;
assign vis_nofrf_e = visop_e & (siam | alignaddr | opf_log_zero | opf_log_one);
// controls for add
// Make subtract come out of its own flop for loading purposes (very critical timing)
dff_s sub_dff(.din(opf[2]), .clk(clk), .q(ctl_vis_subtract), .se(se), .si(), .so());
assign ctl_vis_cin = opf[2];
assign ctl_vis_add32 = opf[1];
// controls for logic
assign opf_log_zero = ~opf[4] & ~opf[3] & ~opf[2] & ~opf[1];
assign opf_log_nor = ~opf[4] & ~opf[3] & ~opf[2] & opf[1];
assign opf_log_andnot2 = ~opf[4] & ~opf[3] & opf[2] & ~opf[1];
assign opf_log_not2 = ~opf[4] & ~opf[3] & opf[2] & opf[1];
assign opf_log_andnot1 = ~opf[4] & opf[3] & ~opf[2] & ~opf[1];
assign opf_log_not1 = ~opf[4] & opf[3] & ~opf[2] & opf[1];
assign opf_log_xor = ~opf[4] & opf[3] & opf[2] & ~opf[1];
assign opf_log_nand = ~opf[4] & opf[3] & opf[2] & opf[1];
assign opf_log_and = opf[4] & ~opf[3] & ~opf[2] & ~opf[1];
assign opf_log_xnor = opf[4] & ~opf[3] & ~opf[2] & opf[1];
assign opf_log_src1 = opf[4] & ~opf[3] & opf[2] & ~opf[1];
assign opf_log_ornot2 = opf[4] & ~opf[3] & opf[2] & opf[1];
assign opf_log_src2 = opf[4] & opf[3] & ~opf[2] & ~opf[1];
assign opf_log_ornot1 = opf[4] & opf[3] & ~opf[2] & opf[1];
assign opf_log_or = opf[4] & opf[3] & opf[2] & ~opf[1];
assign opf_log_one = opf[4] & opf[3] & opf[2] & opf[1];
// selects for logic mux
assign ctl_vis_log_sel_nand = opf_log_or | opf_log_nand | opf_log_ornot1 | opf_log_ornot2;
assign ctl_vis_log_sel_xor = opf_log_xor | opf_log_xnor;
assign ctl_vis_log_sel_nor = opf_log_and | opf_log_nor | opf_log_andnot1 | opf_log_andnot2;
assign ctl_vis_log_sel_pass = (opf_log_zero | opf_log_one | opf_log_src1 | opf_log_src2 |
opf_log_not1 | opf_log_not2);
assign invert_rs1_next = (opf_log_not1 | opf_log_or | opf_log_and |
opf_log_ornot2 | opf_log_andnot2);
assign invert_rs2_next = (opf_log_not2 | opf_log_or | opf_log_and |
opf_log_ornot1 | opf_log_andnot1 | opf_log_xnor);
dff_s invert_rs1_dff(.din(invert_rs1_next), .clk(clk), .q(ctl_vis_log_invert_rs1),
.se(se), .si(), .so());
dff_s invert_rs2_dff(.din(invert_rs2_next), .clk(clk), .q(ctl_vis_log_invert_rs2),
.se(se), .si(), .so());
// precalculate to help timing
assign log_pass_rs1_next = opf_log_src1 | opf_log_not1;
assign log_pass_rs2_next = opf_log_src2 | opf_log_not2;
dff_s #(2) log_pass_dff(.din({log_pass_rs1_next,log_pass_rs2_next}), .clk(clk),
.q({log_pass_rs1,log_pass_rs2}), .se(se), .si(), .so());
assign ctl_vis_log_pass_rs1 = log_pass_rs1;
assign ctl_vis_log_pass_rs2 = log_pass_rs2 & ~log_pass_rs1;
assign ctl_vis_log_constant = opf_log_one;
assign ctl_vis_log_pass_const = ~(ctl_vis_log_pass_rs1 | ctl_vis_log_pass_rs2);
// controls for falign
assign ctl_vis_align0 = ~gsr_align_d1[2] & ~gsr_align_d1[1];
assign ctl_vis_align2 = ~gsr_align_d1[2] & gsr_align_d1[1];
assign ctl_vis_align4 = gsr_align_d1[2] & ~gsr_align_d1[1];
assign ctl_vis_align6 = gsr_align_d1[2] & gsr_align_d1[1];
assign ctl_vis_align_odd = gsr_align_d1[0];
// controls for output mux
assign ctl_vis_sel_add = add;
assign ctl_vis_sel_align = align;
assign ctl_vis_sel_log = ~(add | align);
///////////////////////////////////////////////////////////
// GSR.alignaddr_offset, GSR.IM, GSR.IRND
///////////////////////////////////////////////////////////
mux4ds #(6) curr_gsr_mux(.dout({gsr_rnd[2:0], gsr_align[2:0]}),
.in0({t0_gsr_rnd[2:0], t0_gsr_align[2:0]}),
.in1({t1_gsr_rnd[2:0], t1_gsr_align[2:0]}),
.in2({t2_gsr_rnd[2:0], t2_gsr_align[2:0]}),
.in3({t3_gsr_rnd[2:0], t3_gsr_align[2:0]}),
.sel0(thr_fp[0]),
.sel1(thr_fp[1]),
.sel2(thr_fp[2]),
.sel3(thr_fp[3]));
mux4ds #(6) gsr_e_mux(.dout({gsr_rnd_e[2:0], gsr_align_e[2:0]}),
.in0({t0_gsr_rnd[2:0], t0_gsr_align[2:0]}),
.in1({t1_gsr_rnd[2:0], t1_gsr_align[2:0]}),
.in2({t2_gsr_rnd[2:0], t2_gsr_align[2:0]}),
.in3({t3_gsr_rnd[2:0], t3_gsr_align[2:0]}),
.sel0(ctl_dp_thr_e[0]),
.sel1(ctl_dp_thr_e[1]),
.sel2(ctl_dp_thr_e[2]),
.sel3(ctl_dp_thr_e[3]));
dff_s #(43) gsr_e2m(.din({dp_ctl_gsr_mask_e[31:0],gsr_rnd_e[2:0],
dp_ctl_gsr_scale_e[4:0],gsr_align_e[2:0]}), .clk(clk),
.q({ffu_exu_rsr_data_hi_m[31:0],ffu_exu_rsr_data_mid_m[2:0], ffu_exu_rsr_data_lo_m[7:0]}),
.se(se), .si(), .so());
dff_s #(3) gsr_align_dff(.din(gsr_align[2:0]), .clk(clk), .q(gsr_align_d1[2:0]), .se(se), .si(), .so());
// put in to help timing for sending to lsu
dff_s #(2) fpu_rnd_dff(.din(fpu_rnd_next[1:0]), .clk(clk), .q(fpu_rnd[1:0]), .si(), .so(), .se(se));
assign fpu_rnd_next[1:0] = (gsr_rnd[2])? gsr_rnd[1:0]: dp_ctl_fsr_rnd[1:0];
// if alignaddress_little then write the 2's complement
assign align_addr_data_w2[2:0] = (opf[1])? (~wgsr_align_offset_w2[2:0] + 3'b001):
wgsr_align_offset_w2[2:0];
assign gsr_addr_d = (ifu_tlu_sraddr_d[6:0] == 7'b0010011);
assign wgsr_e = exu_ffu_wsr_inst_e & gsr_addr_e;
dff_s gsr_addr_d2e(.din(gsr_addr_d), .clk(clk), .q(gsr_addr_e), .se(se), .si(), .so());
// need independent kill checks because this isn't killed by new fpop
assign wgsr_vld_m = wgsr_m & ~(thr_match_mw2 & flush_w2);
assign wgsr_vld_w = wgsr_w & ifu_tlu_inst_vld_w & ~(thr_match_ww2 & flush_w2);
assign wgsr_vld_w2 = wgsr_w2 & ~flush_w2;
dff_s wgsr_e2m(.din(wgsr_e), .clk(clk), .q(wgsr_m), .si(), .so(), .se(se));
dff_s wgsr_m2w(.din(wgsr_vld_m), .clk(clk), .q(wgsr_w), .si(), .so(), .se(se));
dff_s wgsr_w2w2(.din(wgsr_vld_w), .clk(clk), .q(wgsr_w2), .si(), .so(), .se(se));
assign thr_w2[3] = (tid_w2[1:0] == 2'b11);
assign thr_w2[2] = (tid_w2[1:0] == 2'b10);
assign thr_w2[1] = (tid_w2[1:0] == 2'b01);
assign thr_w2[0] = (tid_w2[1:0] == 2'b00);
assign ctl_dp_thr_e[3] = (tid_e[1:0] == 2'b11);
assign ctl_dp_thr_e[2] = (tid_e[1:0] == 2'b10);
assign ctl_dp_thr_e[1] = (tid_e[1:0] == 2'b01);
assign ctl_dp_thr_e[0] = (tid_e[1:0] == 2'b00);
assign thr_fp[3] = (tid[1:0] == 2'b11);
assign thr_fp[2] = (tid[1:0] == 2'b10);
assign thr_fp[1] = (tid[1:0] == 2'b01);
assign thr_fp[0] = (tid[1:0] == 2'b00);
assign t0_siam_w2 = thr_fp[0] & siam & visop_w2_vld;
assign t0_gsr_wsr_w2 = thr_w2[0] & wgsr_vld_w2;
assign t0_alignaddr_w2 = thr_fp[0] & alignaddr & visop_w2_vld;
assign t0_rnd_wen_l = ~(t0_gsr_wsr_w2 | t0_siam_w2);
assign t0_align_wen_l = ~(t0_gsr_wsr_w2 | t0_alignaddr_w2);
assign t1_siam_w2 = thr_fp[1] & siam & visop_w2_vld;
assign t1_gsr_wsr_w2 = thr_w2[1] & wgsr_vld_w2;
assign t1_alignaddr_w2 = thr_fp[1] & alignaddr & visop_w2_vld;
assign t1_rnd_wen_l = ~(t1_gsr_wsr_w2 | t1_siam_w2);
assign t1_align_wen_l = ~(t1_gsr_wsr_w2 | t1_alignaddr_w2);
assign t2_siam_w2 = thr_fp[2] & siam & visop_w2_vld;
assign t2_gsr_wsr_w2 = thr_w2[2] & wgsr_vld_w2;
assign t2_alignaddr_w2 = thr_fp[2] & alignaddr & visop_w2_vld;
assign t2_rnd_wen_l = ~(t2_gsr_wsr_w2 | t2_siam_w2);
assign t2_align_wen_l = ~(t2_gsr_wsr_w2 | t2_alignaddr_w2);
assign t3_siam_w2 = thr_fp[3] & siam & visop_w2_vld;
assign t3_gsr_wsr_w2 = thr_w2[3] & wgsr_vld_w2;
assign t3_alignaddr_w2 = thr_fp[3] & alignaddr & visop_w2_vld;
assign t3_rnd_wen_l = ~(t3_gsr_wsr_w2 | t3_siam_w2);
assign t3_align_wen_l = ~(t3_gsr_wsr_w2 | t3_alignaddr_w2);
assign ctl_dp_gsr_wsr_w2[3:0] = {t3_gsr_wsr_w2,t2_gsr_wsr_w2,t1_gsr_wsr_w2,t0_gsr_wsr_w2};
// Storage flops and muxes
mux3ds #(3) t0_rnd_mux(.dout(t0_gsr_rnd_next[2:0]),
.in0(t0_gsr_rnd[2:0]),
.in1(wgsr_rnd_w2[2:0]),
.in2(siam_rnd[2:0]),
.sel0(t0_rnd_wen_l),
.sel1(t0_gsr_wsr_w2),
.sel2(t0_siam_w2));
mux3ds #(3) t0_align_mux(.dout(t0_gsr_align_next[2:0]),
.in0(t0_gsr_align[2:0]),
.in1(wgsr_align_offset_w2[2:0]),
.in2(align_addr_data_w2[2:0]),
.sel0(t0_align_wen_l),
.sel1(t0_gsr_wsr_w2),
.sel2(t0_alignaddr_w2));
mux3ds #(3) t1_rnd_mux(.dout(t1_gsr_rnd_next[2:0]),
.in0(t1_gsr_rnd[2:0]),
.in1(wgsr_rnd_w2[2:0]),
.in2(siam_rnd[2:0]),
.sel0(t1_rnd_wen_l),
.sel1(t1_gsr_wsr_w2),
.sel2(t1_siam_w2));
mux3ds #(3) t1_align_mux(.dout(t1_gsr_align_next[2:0]),
.in0(t1_gsr_align[2:0]),
.in1(wgsr_align_offset_w2[2:0]),
.in2(align_addr_data_w2[2:0]),
.sel0(t1_align_wen_l),
.sel1(t1_gsr_wsr_w2),
.sel2(t1_alignaddr_w2));
mux3ds #(3) t2_rnd_mux(.dout(t2_gsr_rnd_next[2:0]),
.in0(t2_gsr_rnd[2:0]),
.in1(wgsr_rnd_w2[2:0]),
.in2(siam_rnd[2:0]),
.sel0(t2_rnd_wen_l),
.sel1(t2_gsr_wsr_w2),
.sel2(t2_siam_w2));
mux3ds #(3) t2_align_mux(.dout(t2_gsr_align_next[2:0]),
.in0(t2_gsr_align[2:0]),
.in1(wgsr_align_offset_w2[2:0]),
.in2(align_addr_data_w2[2:0]),
.sel0(t2_align_wen_l),
.sel1(t2_gsr_wsr_w2),
.sel2(t2_alignaddr_w2));
mux3ds #(3) t3_rnd_mux(.dout(t3_gsr_rnd_next[2:0]),
.in0(t3_gsr_rnd[2:0]),
.in1(wgsr_rnd_w2[2:0]),
.in2(siam_rnd[2:0]),
.sel0(t3_rnd_wen_l),
.sel1(t3_gsr_wsr_w2),
.sel2(t3_siam_w2));
mux3ds #(3) t3_align_mux(.dout(t3_gsr_align_next[2:0]),
.in0(t3_gsr_align[2:0]),
.in1(wgsr_align_offset_w2[2:0]),
.in2(align_addr_data_w2[2:0]),
.sel0(t3_align_wen_l),
.sel1(t3_gsr_wsr_w2),
.sel2(t3_alignaddr_w2));
dffr_s #(6) t0_gsr_dff(.din({t0_gsr_rnd_next[2:0], t0_gsr_align_next[2:0]}), .clk(clk),
.q({t0_gsr_rnd[2:0], t0_gsr_align[2:0]}), .se(se),
.si(), .so(), .rst(reset));
dffr_s #(6) t1_gsr_dff(.din({t1_gsr_rnd_next[2:0], t1_gsr_align_next[2:0]}), .clk(clk),
.q({t1_gsr_rnd[2:0], t1_gsr_align[2:0]}), .se(se),
.si(), .so(), .rst(reset));
dffr_s #(6) t2_gsr_dff(.din({t2_gsr_rnd_next[2:0], t2_gsr_align_next[2:0]}), .clk(clk),
.q({t2_gsr_rnd[2:0], t2_gsr_align[2:0]}), .se(se),
.si(), .so(), .rst(reset));
dffr_s #(6) t3_gsr_dff(.din({t3_gsr_rnd_next[2:0], t3_gsr_align_next[2:0]}), .clk(clk),
.q({t3_gsr_rnd[2:0], t3_gsr_align[2:0]}), .se(se),
.si(), .so(), .rst(reset));
dffre_s #(3) siam_rnd_dff(.din(ifu_ffu_rnd_e[2:0]), .clk(clk),
.q(siam_rnd), .se(se), .si(), .so(),
.rst(reset), .en(visop_e));
dff_s #(3) align_offset_dff1(.din(exu_ffu_gsr_align_m[2:0]), .clk(clk),
.q(wgsr_align_offset_w[2:0]), .se(se), .si(), .so());
dff_s #(3) align_offset_dff2(.din(wgsr_align_offset_w[2:0]), .clk(clk),
.q(wgsr_align_offset_w2[2:0]), .se(se), .si(), .so());
dff_s #(3) rnd_dff1(.din(exu_ffu_gsr_rnd_m[2:0]), .clk(clk),
.q(wgsr_rnd_w[2:0]), .se(se), .si(), .so());
dff_s #(3) rnd_dff2(.din(wgsr_rnd_w[2:0]), .clk(clk),
.q(wgsr_rnd_w2[2:0]), .se(se), .si(), .so());
assign wsr_data_m[36:0] = {exu_ffu_gsr_mask_m[31:0], exu_ffu_gsr_scale_m[4:0]};
dff_s #(37) wsr_data_m2w(.din(wsr_data_m[36:0]), .clk(clk), .q(wsr_data_w[36:0]),
.se(se), .si(), .so());
dff_s #(37) wsr_data_w2w2(.din(wsr_data_w[36:0]), .clk(clk), .q(ctl_dp_wsr_data_w2[36:0]),
.se(se), .si(), .so());
endmodule |
module altpcie_pll_100_250 (
areset,
inclk0,
c0);
input areset;
input inclk0;
output c0;
wire [5:0] sub_wire0;
wire [0:0] sub_wire2 = 1'h0;
wire [0:0] sub_wire4 = 1'h1;
wire [0:0] sub_wire1 = sub_wire0[0:0];
wire c0 = sub_wire1;
wire [5:0] sub_wire3 = {sub_wire2, sub_wire2, sub_wire2, sub_wire2, sub_wire2, sub_wire4};
wire sub_wire5 = inclk0;
wire [1:0] sub_wire6 = {sub_wire2, sub_wire5};
wire [3:0] sub_wire7 = {sub_wire2, sub_wire2, sub_wire2, sub_wire2};
altpll altpll_component (
.clkena (sub_wire3),
.inclk (sub_wire6),
.extclkena (sub_wire7),
.areset (areset),
.clk (sub_wire0)
// synopsys translate_off
,
.scanclk (),
.pllena (),
.sclkout1 (),
.sclkout0 (),
.fbin (),
.scandone (),
.clkloss (),
.extclk (),
.clkswitch (),
.pfdena (),
.scanaclr (),
.clkbad (),
.scandata (),
.enable1 (),
.scandataout (),
.enable0 (),
.scanwrite (),
.locked (),
.activeclock (),
.scanread ()
// synopsys translate_on
);
defparam
altpll_component.bandwidth = 500000,
altpll_component.bandwidth_type = "CUSTOM",
altpll_component.clk0_divide_by = 2,
altpll_component.clk0_duty_cycle = 50,
altpll_component.clk0_multiply_by = 5,
altpll_component.clk0_phase_shift = "0",
altpll_component.compensate_clock = "CLK0",
altpll_component.inclk0_input_frequency = 10000,
altpll_component.intended_device_family = "Stratix GX",
altpll_component.lpm_type = "altpll",
altpll_component.operation_mode = "NORMAL",
altpll_component.pll_type = "ENHANCED",
altpll_component.spread_frequency = 0;
endmodule |
module PLL_100M (
inclk0,
c0,
locked);
input inclk0;
output c0;
output locked;
wire [0:0] sub_wire2 = 1'h0;
wire [4:0] sub_wire3;
wire sub_wire5;
wire sub_wire0 = inclk0;
wire [1:0] sub_wire1 = {sub_wire2, sub_wire0};
wire [0:0] sub_wire4 = sub_wire3[0:0];
wire c0 = sub_wire4;
wire locked = sub_wire5;
altpll altpll_component (
.inclk (sub_wire1),
.clk (sub_wire3),
.locked (sub_wire5),
.activeclock (),
.areset (1'b0),
.clkbad (),
.clkena ({6{1'b1}}),
.clkloss (),
.clkswitch (1'b0),
.configupdate (1'b0),
.enable0 (),
.enable1 (),
.extclk (),
.extclkena ({4{1'b1}}),
.fbin (1'b1),
.fbmimicbidir (),
.fbout (),
.fref (),
.icdrclk (),
.pfdena (1'b1),
.phasecounterselect ({4{1'b1}}),
.phasedone (),
.phasestep (1'b1),
.phaseupdown (1'b1),
.pllena (1'b1),
.scanaclr (1'b0),
.scanclk (1'b0),
.scanclkena (1'b1),
.scandata (1'b0),
.scandataout (),
.scandone (),
.scanread (1'b0),
.scanwrite (1'b0),
.sclkout0 (),
.sclkout1 (),
.vcooverrange (),
.vcounderrange ());
defparam
altpll_component.bandwidth_type = "AUTO",
altpll_component.clk0_divide_by = 1,
altpll_component.clk0_duty_cycle = 50,
altpll_component.clk0_multiply_by = 10,
altpll_component.clk0_phase_shift = "0",
altpll_component.compensate_clock = "CLK0",
altpll_component.inclk0_input_frequency = 100000,
altpll_component.intended_device_family = "Cyclone IV E",
altpll_component.lpm_hint = "CBX_MODULE_PREFIX=PLL_100M",
altpll_component.lpm_type = "altpll",
altpll_component.operation_mode = "NORMAL",
altpll_component.pll_type = "AUTO",
altpll_component.port_activeclock = "PORT_UNUSED",
altpll_component.port_areset = "PORT_UNUSED",
altpll_component.port_clkbad0 = "PORT_UNUSED",
altpll_component.port_clkbad1 = "PORT_UNUSED",
altpll_component.port_clkloss = "PORT_UNUSED",
altpll_component.port_clkswitch = "PORT_UNUSED",
altpll_component.port_configupdate = "PORT_UNUSED",
altpll_component.port_fbin = "PORT_UNUSED",
altpll_component.port_inclk0 = "PORT_USED",
altpll_component.port_inclk1 = "PORT_UNUSED",
altpll_component.port_locked = "PORT_USED",
altpll_component.port_pfdena = "PORT_UNUSED",
altpll_component.port_phasecounterselect = "PORT_UNUSED",
altpll_component.port_phasedone = "PORT_UNUSED",
altpll_component.port_phasestep = "PORT_UNUSED",
altpll_component.port_phaseupdown = "PORT_UNUSED",
altpll_component.port_pllena = "PORT_UNUSED",
altpll_component.port_scanaclr = "PORT_UNUSED",
altpll_component.port_scanclk = "PORT_UNUSED",
altpll_component.port_scanclkena = "PORT_UNUSED",
altpll_component.port_scandata = "PORT_UNUSED",
altpll_component.port_scandataout = "PORT_UNUSED",
altpll_component.port_scandone = "PORT_UNUSED",
altpll_component.port_scanread = "PORT_UNUSED",
altpll_component.port_scanwrite = "PORT_UNUSED",
altpll_component.port_clk0 = "PORT_USED",
altpll_component.port_clk1 = "PORT_UNUSED",
altpll_component.port_clk2 = "PORT_UNUSED",
altpll_component.port_clk3 = "PORT_UNUSED",
altpll_component.port_clk4 = "PORT_UNUSED",
altpll_component.port_clk5 = "PORT_UNUSED",
altpll_component.port_clkena0 = "PORT_UNUSED",
altpll_component.port_clkena1 = "PORT_UNUSED",
altpll_component.port_clkena2 = "PORT_UNUSED",
altpll_component.port_clkena3 = "PORT_UNUSED",
altpll_component.port_clkena4 = "PORT_UNUSED",
altpll_component.port_clkena5 = "PORT_UNUSED",
altpll_component.port_extclk0 = "PORT_UNUSED",
altpll_component.port_extclk1 = "PORT_UNUSED",
altpll_component.port_extclk2 = "PORT_UNUSED",
altpll_component.port_extclk3 = "PORT_UNUSED",
altpll_component.self_reset_on_loss_lock = "ON",
altpll_component.width_clock = 5;
endmodule |
module adder_tb;
parameter N_BITS_A = 3;
parameter BIN_PT_A = 1;
parameter SIGNED_A = 1;
parameter N_BITS_B = 4;
parameter BIN_PT_B = 3;
parameter SIGNED_B = 0;
parameter N_BITS_OUT = 6;
parameter BIN_PT_OUT = 3;
reg [N_BITS_A-1:0] a;
reg [N_BITS_B-1:0] b;
wire [N_BITS_OUT-1:0] sum;
initial begin
a = 3'b0_0_0; // 0
b = 4'b0_001; // + 1/8
// 1/8
#10
a = 3'b1_1_1; // -1/2
b = 4'b0_001; // + 1/8
// -3/8
#5
a = 3'b1_1_0; // -1
b = 4'b0_100; // + 1/2
// -1/2
#5
a = 3'b0_0_1; // 1/2
b = 4'b1_000; // + 1
// 3/2
#10 ;
$finish;
end //initial
adder #(.N_BITS_A(N_BITS_A),
.BIN_PT_A(BIN_PT_A),
.SIGNED_A(SIGNED_A),
.N_BITS_B(N_BITS_B),
.BIN_PT_B(BIN_PT_B),
.SIGNED_B(SIGNED_B),
.N_BITS_OUT(N_BITS_OUT),
.BIN_PT_OUT(BIN_PT_OUT)) a0 (a, b, sum);
initial begin
$monitor("%t, a = \t(%d,%d)b'%b\t a_padded = \t(%d,%d)b'%b\n%t, b = \t(%d,%d)b'%b\t b_padded = \t(%d,%d)b'%b\n%t, sum = \t\t\t\t\t(%d,%d)b'%b", $time, N_BITS_A, BIN_PT_A, a, N_BITS_OUT, BIN_PT_OUT, a0.add0.a_padded, $time, N_BITS_B, BIN_PT_B, b, N_BITS_OUT, BIN_PT_OUT, a0.add0.b_padded, $time, N_BITS_OUT, BIN_PT_OUT, sum);
end
endmodule |
module mac_core (
input wire clk, // control_port_clock_connection.clk
input wire reset, // reset_connection.reset
input wire [7:0] reg_addr, // control_port.address
output wire [31:0] reg_data_out, // .readdata
input wire reg_rd, // .read
input wire [31:0] reg_data_in, // .writedata
input wire reg_wr, // .write
output wire reg_busy, // .waitrequest
input wire tx_clk, // pcs_mac_tx_clock_connection.clk
input wire rx_clk, // pcs_mac_rx_clock_connection.clk
input wire set_10, // mac_status_connection.set_10
input wire set_1000, // .set_1000
output wire eth_mode, // .eth_mode
output wire ena_10, // .ena_10
input wire [7:0] gm_rx_d, // mac_gmii_connection.gmii_rx_d
input wire gm_rx_dv, // .gmii_rx_dv
input wire gm_rx_err, // .gmii_rx_err
output wire [7:0] gm_tx_d, // .gmii_tx_d
output wire gm_tx_en, // .gmii_tx_en
output wire gm_tx_err, // .gmii_tx_err
input wire [3:0] m_rx_d, // mac_mii_connection.mii_rx_d
input wire m_rx_en, // .mii_rx_dv
input wire m_rx_err, // .mii_rx_err
output wire [3:0] m_tx_d, // .mii_tx_d
output wire m_tx_en, // .mii_tx_en
output wire m_tx_err, // .mii_tx_err
input wire m_rx_crs, // .mii_crs
input wire m_rx_col, // .mii_col
input wire ff_rx_clk, // receive_clock_connection.clk
input wire ff_tx_clk, // transmit_clock_connection.clk
output wire [31:0] ff_rx_data, // receive.data
output wire ff_rx_eop, // .endofpacket
output wire [5:0] rx_err, // .error
output wire [1:0] ff_rx_mod, // .empty
input wire ff_rx_rdy, // .ready
output wire ff_rx_sop, // .startofpacket
output wire ff_rx_dval, // .valid
input wire [31:0] ff_tx_data, // transmit.data
input wire ff_tx_eop, // .endofpacket
input wire ff_tx_err, // .error
input wire [1:0] ff_tx_mod, // .empty
output wire ff_tx_rdy, // .ready
input wire ff_tx_sop, // .startofpacket
input wire ff_tx_wren, // .valid
output wire magic_wakeup, // mac_misc_connection.magic_wakeup
input wire magic_sleep_n, // .magic_sleep_n
input wire ff_tx_crc_fwd, // .ff_tx_crc_fwd
output wire ff_tx_septy, // .ff_tx_septy
output wire tx_ff_uflow, // .tx_ff_uflow
output wire ff_tx_a_full, // .ff_tx_a_full
output wire ff_tx_a_empty, // .ff_tx_a_empty
output wire [17:0] rx_err_stat, // .rx_err_stat
output wire [3:0] rx_frm_type, // .rx_frm_type
output wire ff_rx_dsav, // .ff_rx_dsav
output wire ff_rx_a_full, // .ff_rx_a_full
output wire ff_rx_a_empty // .ff_rx_a_empty
);
mac_core_0002 mac_core_inst (
.clk (clk), // control_port_clock_connection.clk
.reset (reset), // reset_connection.reset
.reg_addr (reg_addr), // control_port.address
.reg_data_out (reg_data_out), // .readdata
.reg_rd (reg_rd), // .read
.reg_data_in (reg_data_in), // .writedata
.reg_wr (reg_wr), // .write
.reg_busy (reg_busy), // .waitrequest
.tx_clk (tx_clk), // pcs_mac_tx_clock_connection.clk
.rx_clk (rx_clk), // pcs_mac_rx_clock_connection.clk
.set_10 (set_10), // mac_status_connection.set_10
.set_1000 (set_1000), // .set_1000
.eth_mode (eth_mode), // .eth_mode
.ena_10 (ena_10), // .ena_10
.gm_rx_d (gm_rx_d), // mac_gmii_connection.gmii_rx_d
.gm_rx_dv (gm_rx_dv), // .gmii_rx_dv
.gm_rx_err (gm_rx_err), // .gmii_rx_err
.gm_tx_d (gm_tx_d), // .gmii_tx_d
.gm_tx_en (gm_tx_en), // .gmii_tx_en
.gm_tx_err (gm_tx_err), // .gmii_tx_err
.m_rx_d (m_rx_d), // mac_mii_connection.mii_rx_d
.m_rx_en (m_rx_en), // .mii_rx_dv
.m_rx_err (m_rx_err), // .mii_rx_err
.m_tx_d (m_tx_d), // .mii_tx_d
.m_tx_en (m_tx_en), // .mii_tx_en
.m_tx_err (m_tx_err), // .mii_tx_err
.m_rx_crs (m_rx_crs), // .mii_crs
.m_rx_col (m_rx_col), // .mii_col
.ff_rx_clk (ff_rx_clk), // receive_clock_connection.clk
.ff_tx_clk (ff_tx_clk), // transmit_clock_connection.clk
.ff_rx_data (ff_rx_data), // receive.data
.ff_rx_eop (ff_rx_eop), // .endofpacket
.rx_err (rx_err), // .error
.ff_rx_mod (ff_rx_mod), // .empty
.ff_rx_rdy (ff_rx_rdy), // .ready
.ff_rx_sop (ff_rx_sop), // .startofpacket
.ff_rx_dval (ff_rx_dval), // .valid
.ff_tx_data (ff_tx_data), // transmit.data
.ff_tx_eop (ff_tx_eop), // .endofpacket
.ff_tx_err (ff_tx_err), // .error
.ff_tx_mod (ff_tx_mod), // .empty
.ff_tx_rdy (ff_tx_rdy), // .ready
.ff_tx_sop (ff_tx_sop), // .startofpacket
.ff_tx_wren (ff_tx_wren), // .valid
.magic_wakeup (magic_wakeup), // mac_misc_connection.magic_wakeup
.magic_sleep_n (magic_sleep_n), // .magic_sleep_n
.ff_tx_crc_fwd (ff_tx_crc_fwd), // .ff_tx_crc_fwd
.ff_tx_septy (ff_tx_septy), // .ff_tx_septy
.tx_ff_uflow (tx_ff_uflow), // .tx_ff_uflow
.ff_tx_a_full (ff_tx_a_full), // .ff_tx_a_full
.ff_tx_a_empty (ff_tx_a_empty), // .ff_tx_a_empty
.rx_err_stat (rx_err_stat), // .rx_err_stat
.rx_frm_type (rx_frm_type), // .rx_frm_type
.ff_rx_dsav (ff_rx_dsav), // .ff_rx_dsav
.ff_rx_a_full (ff_rx_a_full), // .ff_rx_a_full
.ff_rx_a_empty (ff_rx_a_empty) // .ff_rx_a_empty
);
endmodule |
module sky130_fd_sc_lp__and4b (
//# {{data|Data Signals}}
input A_N ,
input B ,
input C ,
input D ,
output X ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule |
module pulse_gen(
input clk, // 12 MHz base clock
input RS232_Rx, // Receive pin for the FTDI chip
input resetn, // Reset the cycle
output RS232_Tx, // Transmit pin for the FTDI chip
output Pulse, // Output pin for the switch
output Sync, // Output pin for the SYNC pulse
// output FM, // Output pin for the FM pulse
output P2
// output P3,
// output P4,
// output J1_4,
// output J1_5,
// output J1_6,
// output J1_7,
// output J1_8,
// output J1_9,
// output J1_10,
// output J4_3,
// output J4_4,
// output J4_5,
// output J4_6,
// output J4_7,
// output J4_8,
// output J4_9
);
wire [31:0] period;
wire [15:0] p1width;
wire [15:0] delay;
wire [15:0] p2width;
wire [15:0] nut_del;
wire [7:0] nut_wid;
wire block;
wire [7:0] pulse_block;
wire [15:0] pulse_block_off;
wire [7:0] cpmg;
wire rx_done;
// wire [6:0] pre_att;
// wire [6:0] post_att;
// NOSIM_START
wire clk_pll;
wire clk_pll_gl;
wire lock;
// Setting the PLL to output a 201 MHz clock, based on code from
// https://gist.github.com/thoughtpolice/8ec923e1b3fc4bb12c11aa23b4dc53b5#file-ice40-v
// Note: These values are slightly different from those outputted by icepll
pll ecppll(
.clock_in(clk),
.clock_out(clk_pll),
.locked(lock)
);
// Setting up communications with LabView over USB
pulse_control control(
.clk(clk),
.RS232_Rx(RS232_Rx),
.RS232_Tx(RS232_Tx),
.per(period),
.p1wid(p1width),
.del(delay),
.p2wid(p2width),
.nut_d(nut_del),
.nut_w(nut_wid),
// .pr_att(pre_att),
// .po_att(post_att),
.cp(cpmg),
.p_bl(pulse_block),
.p_bl_off(pulse_block_off),
.bl(block),
.rxd(rx_done)
);
// NOSIM_END
// Generating the necessary pulses
pulses pulses(
.clk(clk),
.clk_pll(clk_pll),
.reset(resetn),
.per(period),
.p1wid(p1width),
.del(delay),
.p2wid(p2width),
.nut_d(nut_del),
.nut_w(nut_wid),
// .pr_att(pre_att),
// .po_att(post_att),
.cp(cpmg),
.p_bl(pulse_block),
.p_bl_off(pulse_block_off),
.bl(block),
.rxd(rx_done),
.sync_on(Sync),
.pulse_on(Pulse),
// .Att1({J1_4, J1_5, J1_6, J1_7, J1_8, J1_9, J1_10}),
// .Att3({J4_9, J4_8, J4_7, J4_6, J4_5, J4_4, J4_3}),
.inhib(P2)
// .test({FM, P3, P4})
);
// NOSIM2_START
endmodule |
module shift_mux_array
#(parameter SWR=26, parameter LEVEL=5)
(
input wire [SWR-1:0] Data_i,
input wire select_i,
input wire bit_shift_i,
output wire [SWR-1:0] Data_o
);
genvar j;
localparam integer lvl = 2**(LEVEL);
localparam integer x = (SWR - 1);
generate for (j=0; j<=SWR-1 ; j=j+1) begin : MUX_ODDNORM
localparam integer sh=(2**LEVEL)+j; //value for second mux input. It changes in exponentation by 2 for each level
case ((lvl+j)>(x))
1'b1: begin :BSHITMUX
//assign mux_out = (sel) ? din_1 : din_0;
assign Data_o[j] = (select_i) ? bit_shift_i : Data_i[j];
end
1'b0: begin : FSHITMUX
assign Data_o[j] = (select_i) ? Data_i[lvl+j] : Data_i[j];
end
endcase
end
endgenerate
endmodule |
module cmp_pcxandcpx (/*AUTOARG*/
// Inputs
clk, rst_l, spc_pcx_req_pq, spc_pcx_data_pa, cpx_spc_data_cx, cpu
);
input clk;
input rst_l;
//siganls
input [4:0] spc_pcx_req_pq;
input [`PCX_WIDTH-1:0] spc_pcx_data_pa;
input [`CPX_WIDTH-1:0] cpx_spc_data_cx;
input [31:0] cpu;
reg [127:0] pcx;
reg spc_pcx_req_pq_vld;
always @(posedge clk)begin
// victorm 08/11/03
spc_pcx_req_pq_vld <= #1 |spc_pcx_req_pq[4:0];
if(spc_pcx_data_pa[`PCX_VLD] &&
(`PC_CMP.finish_mask != `PC_CMP.good) &&
(`MONITOR.bad == 0)) begin
case(spc_pcx_data_pa[`PCX_RQ_HI:`PCX_RQ_LO])
`LOAD_RQ : pcx = "LOAD_RQ";
`IMISS_RQ : pcx = "IMISS_RQ";
`STORE_RQ : pcx = "STORE_RQ";
`CAS1_RQ : pcx = "CAS1_RQ";
`CAS2_RQ : pcx = "CAS2_RQ";
`SWAP_RQ : pcx = "SWAP_RQ";
`STRLOAD_RQ: pcx = "STRLOAD_RQ";
`STRST_RQ : pcx = "STRST_RQ";
`STQ_RQ : pcx = "STQ_RQ";
`INT_RQ : pcx = "INT_RQ";
`FWD_RQ : pcx = "FWD_RQ";
`FWD_RPY : pcx = "FWD_RPY";
`RSVD_RQ : pcx = "RSVD_RQ";
5'b01010 : pcx = "FPOP1";
5'b01011 : pcx = "FPOP2";
endcase
if(spc_pcx_req_pq_vld)
$display("%0d:Info cpu(%x) pcx %0s packet received -> %b", $time, cpu[2:0], pcx, spc_pcx_data_pa);
end
if(cpx_spc_data_cx[`CPX_VLD] &&
//(`PC_CMP.finish_mask != `PC_CMP.good) &&
(`MONITOR.bad == 0))begin
case(cpx_spc_data_cx[`CPX_RQ_HI:`CPX_RQ_LO])
`LOAD_RET : pcx = "LOAD_RET";
`IFILL_RET: pcx = "IFILL_RET";
`INV_RET : pcx = "INV_RET";
`ST_ACK : pcx = "ST_ACK";
`AT_ACK : pcx = "AT_ACK";
`INT_RET : begin
pcx = "INT_RET";
if(cpx_spc_data_cx[17:16] == 3)begin
if(`PC_CMP.active_thread[cpx_spc_data_cx[12:8]])begin
`PC_CMP.back_thread[cpx_spc_data_cx[12:8]]=1;
end
end
if(cpx_spc_data_cx[17:16] != 1)begin
$display("%0d:Info cpu(%x) thread(%x) received interrupt vector -> %x Also, active_thread->%x", $time,
cpx_spc_data_cx[12:10], cpx_spc_data_cx[9:8], cpx_spc_data_cx[5:0], `PC_CMP.active_thread);
end
else if(cpx_spc_data_cx[17:16] == 1)begin
if(`PC_CMP.active_thread[cpx_spc_data_cx[12:8]])`PC_CMP.back_thread[cpx_spc_data_cx[12:8]]=1;
`PC_CMP.active_thread[cpx_spc_data_cx[12:8]] = 1'b1;
$display("%0d:Info cpu(%x) thread(%x) received interrupt vector -> %x Also, active_thread->%x", $time,
cpx_spc_data_cx[12:10], cpx_spc_data_cx[9:8], cpx_spc_data_cx[5:0], `PC_CMP.active_thread);
end
end
`TEST_RET : pcx = "TEST_RET";
`FP_RET : pcx = "FP_RET";
`EVICT_REQ: pcx = "EVICT_REQ";
`ERR_RET : pcx = "ERR_RET";
`STRLOAD_RET : pcx = "STRLOAD_RET";
`STRST_ACK: pcx = "STRST_ACK";
`FWD_RQ_RET:pcx = "FWD_RQ_RET";
`FWD_RPY_RET:pcx= "FWD_RPY_RET";
`RSVD_RET : pcx = "RSVD_RET";
endcase
$display("%0d:Info cpu(%x) cpx %0s packet received -> %b", $time, cpu[2:0], pcx, cpx_spc_data_cx);
end
end
endmodule |
module sky130_fd_sc_hdll__nor3 (
//# {{data|Data Signals}}
input A,
input B,
input C,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule |
module genrom #( // Parameters
parameter AW = 4, // Address width in bits
parameter DW = 8, // Data witdh in bits
parameter EXTRA = 4
)
( // Ports
input clk, // Global clock signal
input wire [ AW :0] addr, // Address
input wire [ EXTRA-1:0] extra, // Length of data to be fetch
input wire [ AW :0] lower_bound,
input wire [ AW :0] upper_bound,
output reg [2**EXTRA*DW-1:0] data=0, // Output data
output reg error=0 // none / out of limits
);
// Parameter: name of the file with the ROM content
parameter ROMFILE = "prog.list";
// Calc the number of total positions of memory
localparam NPOS = 1 << (AW+1);
// Memory
reg [DW-1: 0] rom [0: NPOS-1];
// Read the memory
always @(posedge clk) begin
error <= addr < lower_bound || addr > upper_bound;
case (extra)
0: data <= rom[addr ];
1: data <= {rom[addr ], rom[addr+ 1]};
2: data <= {rom[addr ], rom[addr+ 1], rom[addr+ 2]};
3: data <= {rom[addr ], rom[addr+ 1], rom[addr+ 2], rom[addr+ 3]};
4: data <= {rom[addr ], rom[addr+ 1], rom[addr+ 2], rom[addr+ 3],
rom[addr+ 4]};
5: data <= {rom[addr ], rom[addr+ 1], rom[addr+ 2], rom[addr+ 3],
rom[addr+ 4], rom[addr+ 5]};
6: data <= {rom[addr ], rom[addr+ 1], rom[addr+ 2], rom[addr+ 3],
rom[addr+ 4], rom[addr+ 5], rom[addr+ 6]};
7: data <= {rom[addr ], rom[addr+ 1], rom[addr+ 2], rom[addr+ 3],
rom[addr+ 4], rom[addr+ 5], rom[addr+ 6], rom[addr+ 7]};
8: data <= {rom[addr ], rom[addr+ 1], rom[addr+ 2], rom[addr+ 3],
rom[addr+ 4], rom[addr+ 5], rom[addr+ 6], rom[addr+ 7],
rom[addr+ 8]};
9: data <= {rom[addr ], rom[addr+ 1], rom[addr+ 2], rom[addr+ 3],
rom[addr+ 4], rom[addr+ 5], rom[addr+ 6], rom[addr+ 7],
rom[addr+ 8], rom[addr+ 9]};
10: data <= {rom[addr ], rom[addr+ 1], rom[addr+ 2], rom[addr+ 3],
rom[addr+ 4], rom[addr+ 5], rom[addr+ 6], rom[addr+ 7],
rom[addr+ 8], rom[addr+ 9], rom[addr+10]};
11: data <= {rom[addr ], rom[addr+ 1], rom[addr+ 2], rom[addr+ 3],
rom[addr+ 4], rom[addr+ 5], rom[addr+ 6], rom[addr+ 7],
rom[addr+ 8], rom[addr+ 9], rom[addr+10], rom[addr+11]};
12: data <= {rom[addr ], rom[addr+ 1], rom[addr+ 2], rom[addr+ 3],
rom[addr+ 4], rom[addr+ 5], rom[addr+ 6], rom[addr+ 7],
rom[addr+ 8], rom[addr+ 9], rom[addr+10], rom[addr+11],
rom[addr+12]};
13: data <= {rom[addr ], rom[addr+ 1], rom[addr+ 2], rom[addr+ 3],
rom[addr+ 4], rom[addr+ 5], rom[addr+ 6], rom[addr+ 7],
rom[addr+ 8], rom[addr+ 9], rom[addr+10], rom[addr+11],
rom[addr+12], rom[addr+13]};
14: data <= {rom[addr ], rom[addr+ 1], rom[addr+ 2], rom[addr+ 3],
rom[addr+ 4], rom[addr+ 5], rom[addr+ 6], rom[addr+ 7],
rom[addr+ 8], rom[addr+ 9], rom[addr+10], rom[addr+11],
rom[addr+12], rom[addr+13], rom[addr+14]};
15: data <= {rom[addr ], rom[addr+ 1], rom[addr+ 2], rom[addr+ 3],
rom[addr+ 4], rom[addr+ 5], rom[addr+ 6], rom[addr+ 7],
rom[addr+ 8], rom[addr+ 9], rom[addr+10], rom[addr+11],
rom[addr+12], rom[addr+13], rom[addr+14], rom[addr+15]};
endcase
end
// Load in memory the `ROMFILE` file. Values must be given in hexadecimal
initial begin
$readmemh(ROMFILE, rom);
end
endmodule |
module of core 'X' signals are system inputs
// and 'Y' signals are system outputs
dft_top dft_top_instance (.clk(clk), .reset(reset), .next(next), .next_out(next_out),
.X0(X0), .Y0(Y0),
.X1(X1), .Y1(Y1),
.X2(X2), .Y2(Y2),
.X3(X3), .Y3(Y3));
// You can use this counter to verify that the gap and latency are as expected.
always @(posedge clk) begin
if (clrCnt) counter <= 0;
else counter <= counter+1;
end
initial begin
@(posedge clk);
@(posedge clk);
// On the next cycle, begin loading input vector.
next <= 1;
clrCnt <= 1;
@(posedge clk);
clrCnt <= 0;
next <= 0;
// The 2048 complex data points enter the system over 1024 cycles
for (j=0; j < 1023; j = j+1) begin
// Input: 2 complex words per cycle
for (k=0; k < 4; k = k+1) begin
in[k] <= j*4 + k;
end
@(posedge clk);
end
j = 1023;
for (k=0; k < 4; k = k+1) begin
in[k] <= j*4 + k;
end
@(posedge clk);
// Wait until the next data vector can be entered
while (counter < 11285)
@(posedge clk);
// On the next cycle, we will start the next data vector
next <= 1;
clrCnt <= 1;
@(posedge clk);
clrCnt <= 0;
next <= 0;
// Start entering next input vector
for (j=0; j < 1023; j = j+1) begin
// Input 4 words per cycle
for (k=0; k < 4; k = k+1) begin
in[k] <= 4096 + j*4 + k;
end
@(posedge clk);
end
j = 1023;
for (k=0; k < 4; k = k+1) begin
in[k] <= 4096 + j*4 + k;
end
end
initial begin
// set initial values
in[0] <= 0;
in[1] <= 0;
in[2] <= 0;
in[3] <= 0;
next <= 0;
reset <= 0;
@(posedge clk);
reset <= 1;
@(posedge clk);
reset <= 0;
@(posedge clk);
@(posedge clk);
// Wait until next_out goes high, then wait one clock cycle and begin receiving data
@(posedge next_out);
@(posedge clk); #1;
$display("--- begin output 1---");
for (m=0; m < 1023; m=m+1) begin
$display("%x", Y0);
$display("%x", Y1);
$display("%x", Y2);
$display("%x", Y3);
@(posedge clk); #1;
end
$display("%x", Y0);
$display("%x", Y1);
$display("%x", Y2);
$display("%x", Y3);
// Wait until next_out goes high, then wait one clock cycle and begin receiving data
@(posedge next_out);
@(posedge clk); #1;
$display("--- begin output 2---");
for (m=0; m < 1023; m=m+1) begin
$display("%x", Y0);
$display("%x", Y1);
$display("%x", Y2);
$display("%x", Y3);
@(posedge clk); #1;
end
$display("%x", Y0);
$display("%x", Y1);
$display("%x", Y2);
$display("%x", Y3);
$finish;
end
endmodule |
module dft_top(clk, reset, next, next_out,
X0, Y0,
X1, Y1,
X2, Y2,
X3, Y3);
output next_out;
input clk, reset, next;
input [11:0] X0,
X1,
X2,
X3;
output [11:0] Y0,
Y1,
Y2,
Y3;
wire [11:0] t0_0;
wire [11:0] t0_1;
wire [11:0] t0_2;
wire [11:0] t0_3;
wire next_0;
wire [11:0] t1_0;
wire [11:0] t1_1;
wire [11:0] t1_2;
wire [11:0] t1_3;
wire next_1;
wire [11:0] t2_0;
wire [11:0] t2_1;
wire [11:0] t2_2;
wire [11:0] t2_3;
wire next_2;
assign t0_0 = X0;
assign Y0 = t2_0;
assign t0_1 = X1;
assign Y1 = t2_1;
assign t0_2 = X2;
assign Y2 = t2_2;
assign t0_3 = X3;
assign Y3 = t2_3;
assign next_0 = next;
assign next_out = next_2;
// latency=980, gap=1024
rc41776 stage0(.clk(clk), .reset(reset), .next(next_0), .next_out(next_1),
.X0(t0_0), .Y0(t1_0),
.X1(t0_1), .Y1(t1_1),
.X2(t0_2), .Y2(t1_2),
.X3(t0_3), .Y3(t1_3));
// latency=11287, gap=11287
ICompose_46101 IComposeInst46328(.next(next_1), .clk(clk), .reset(reset), .next_out(next_2),
.X0(t1_0), .Y0(t2_0),
.X1(t1_1), .Y1(t2_1),
.X2(t1_2), .Y2(t2_2),
.X3(t1_3), .Y3(t2_3));
endmodule |
module rc41776(clk, reset, next, next_out,
X0, Y0,
X1, Y1,
X2, Y2,
X3, Y3);
output next_out;
input clk, reset, next;
input [11:0] X0,
X1,
X2,
X3;
output [11:0] Y0,
Y1,
Y2,
Y3;
wire [23:0] t0;
wire [23:0] s0;
assign t0 = {X0, X1};
wire [23:0] t1;
wire [23:0] s1;
assign t1 = {X2, X3};
assign Y0 = s0[23:12];
assign Y1 = s0[11:0];
assign Y2 = s1[23:12];
assign Y3 = s1[11:0];
perm41774 instPerm46329(.x0(t0), .y0(s0),
.x1(t1), .y1(s1),
.clk(clk), .next(next), .next_out(next_out), .reset(reset)
);
endmodule |
module perm41774(clk, next, reset, next_out,
x0, y0,
x1, y1);
parameter numBanks = 2;
parameter logBanks = 1;
parameter depth = 1024;
parameter logDepth = 10;
parameter width = 24;
input [width-1:0] x0;
output [width-1:0] y0;
wire [width-1:0] ybuff0;
input [width-1:0] x1;
output [width-1:0] y1;
wire [width-1:0] ybuff1;
input clk, next, reset;
output next_out;
wire next0;
reg inFlip0, outFlip0;
reg inActive, outActive;
wire [logBanks-1:0] inBank0, outBank0;
wire [logDepth-1:0] inAddr0, outAddr0;
wire [logBanks-1:0] outBank_a0;
wire [logDepth-1:0] outAddr_a0;
wire [logDepth+logBanks-1:0] addr0, addr0b, addr0c;
wire [logBanks-1:0] inBank1, outBank1;
wire [logDepth-1:0] inAddr1, outAddr1;
wire [logBanks-1:0] outBank_a1;
wire [logDepth-1:0] outAddr_a1;
wire [logDepth+logBanks-1:0] addr1, addr1b, addr1c;
reg [logDepth-1:0] inCount, outCount, outCount_d, outCount_dd, outCount_for_rd_addr, outCount_for_rd_data;
assign addr0 = {inCount, 1'd0};
assign addr0b = {outCount, 1'd0};
assign addr0c = {outCount_for_rd_addr, 1'd0};
assign addr1 = {inCount, 1'd1};
assign addr1b = {outCount, 1'd1};
assign addr1c = {outCount_for_rd_addr, 1'd1};
wire [width+logDepth-1:0] w_0_0, w_0_1, w_1_0, w_1_1;
reg [width-1:0] z_0_0;
reg [width-1:0] z_0_1;
wire [width-1:0] z_1_0, z_1_1;
wire [logDepth-1:0] u_0_0, u_0_1, u_1_0, u_1_1;
always @(posedge clk) begin
end
assign inBank0[0] = addr0[10] ^ addr0[0];
assign inAddr0[0] = addr0[9];
assign inAddr0[1] = addr0[8];
assign inAddr0[2] = addr0[7];
assign inAddr0[3] = addr0[6];
assign inAddr0[4] = addr0[5];
assign inAddr0[5] = addr0[4];
assign inAddr0[6] = addr0[3];
assign inAddr0[7] = addr0[2];
assign inAddr0[8] = addr0[1];
assign inAddr0[9] = addr0[0];
assign outBank0[0] = addr0b[10] ^ addr0b[0];
assign outAddr0[0] = addr0b[1];
assign outAddr0[1] = addr0b[2];
assign outAddr0[2] = addr0b[3];
assign outAddr0[3] = addr0b[4];
assign outAddr0[4] = addr0b[5];
assign outAddr0[5] = addr0b[6];
assign outAddr0[6] = addr0b[7];
assign outAddr0[7] = addr0b[8];
assign outAddr0[8] = addr0b[9];
assign outAddr0[9] = addr0b[10];
assign outBank_a0[0] = addr0c[10] ^ addr0c[0];
assign outAddr_a0[0] = addr0c[1];
assign outAddr_a0[1] = addr0c[2];
assign outAddr_a0[2] = addr0c[3];
assign outAddr_a0[3] = addr0c[4];
assign outAddr_a0[4] = addr0c[5];
assign outAddr_a0[5] = addr0c[6];
assign outAddr_a0[6] = addr0c[7];
assign outAddr_a0[7] = addr0c[8];
assign outAddr_a0[8] = addr0c[9];
assign outAddr_a0[9] = addr0c[10];
assign inBank1[0] = addr1[10] ^ addr1[0];
assign inAddr1[0] = addr1[9];
assign inAddr1[1] = addr1[8];
assign inAddr1[2] = addr1[7];
assign inAddr1[3] = addr1[6];
assign inAddr1[4] = addr1[5];
assign inAddr1[5] = addr1[4];
assign inAddr1[6] = addr1[3];
assign inAddr1[7] = addr1[2];
assign inAddr1[8] = addr1[1];
assign inAddr1[9] = addr1[0];
assign outBank1[0] = addr1b[10] ^ addr1b[0];
assign outAddr1[0] = addr1b[1];
assign outAddr1[1] = addr1b[2];
assign outAddr1[2] = addr1b[3];
assign outAddr1[3] = addr1b[4];
assign outAddr1[4] = addr1b[5];
assign outAddr1[5] = addr1b[6];
assign outAddr1[6] = addr1b[7];
assign outAddr1[7] = addr1b[8];
assign outAddr1[8] = addr1b[9];
assign outAddr1[9] = addr1b[10];
assign outBank_a1[0] = addr1c[10] ^ addr1c[0];
assign outAddr_a1[0] = addr1c[1];
assign outAddr_a1[1] = addr1c[2];
assign outAddr_a1[2] = addr1c[3];
assign outAddr_a1[3] = addr1c[4];
assign outAddr_a1[4] = addr1c[5];
assign outAddr_a1[5] = addr1c[6];
assign outAddr_a1[6] = addr1c[7];
assign outAddr_a1[7] = addr1c[8];
assign outAddr_a1[8] = addr1c[9];
assign outAddr_a1[9] = addr1c[10];
nextReg #(978, 10) nextReg_46334(.X(next), .Y(next0), .reset(reset), .clk(clk));
shiftRegFIFO #(2, 1) shiftFIFO_46337(.X(next0), .Y(next_out), .clk(clk));
memArray2048_41774 #(numBanks, logBanks, depth, logDepth, width)
memSys(.inFlip(inFlip0), .outFlip(outFlip0), .next(next), .reset(reset),
.x0(w_1_0[width+logDepth-1:logDepth]), .y0(ybuff0),
.inAddr0(w_1_0[logDepth-1:0]),
.outAddr0(u_1_0),
.x1(w_1_1[width+logDepth-1:logDepth]), .y1(ybuff1),
.inAddr1(w_1_1[logDepth-1:0]),
.outAddr1(u_1_1),
.clk(clk));
always @(posedge clk) begin
if (reset == 1) begin
z_0_0 <= 0;
z_0_1 <= 0;
inFlip0 <= 0; outFlip0 <= 1; outCount <= 0; inCount <= 0;
outCount_for_rd_addr <= 0;
outCount_for_rd_data <= 0;
end
else begin
outCount_d <= outCount;
outCount_dd <= outCount_d;
if (inCount == 977)
outCount_for_rd_addr <= 0;
else
outCount_for_rd_addr <= outCount_for_rd_addr+1;
if (inCount == 979)
outCount_for_rd_data <= 0;
else
outCount_for_rd_data <= outCount_for_rd_data+1;
z_0_0 <= ybuff0;
z_0_1 <= ybuff1;
if (inCount == 977) begin
outFlip0 <= ~outFlip0;
outCount <= 0;
end
else
outCount <= outCount+1;
if (inCount == 1023) begin
inFlip0 <= ~inFlip0;
end
if (next == 1) begin
if (inCount >= 977)
inFlip0 <= ~inFlip0;
inCount <= 0;
end
else
inCount <= inCount + 1;
end
end
assign w_0_0 = {x0, inAddr0};
assign w_0_1 = {x1, inAddr1};
assign y0 = z_1_0;
assign y1 = z_1_1;
assign u_0_0 = outAddr_a0;
assign u_0_1 = outAddr_a1;
wire wr_ctrl_st_0;
assign wr_ctrl_st_0 = inCount[9];
switch #(logDepth+width) in_sw_0_0(.x0(w_0_0), .x1(w_0_1), .y0(w_1_0), .y1(w_1_1), .ctrl(wr_ctrl_st_0));
wire rdd_ctrl_st_0;
assign rdd_ctrl_st_0 = outCount_for_rd_data[9];
switch #(width) out_sw_0_0(.x0(z_0_0), .x1(z_0_1), .y0(z_1_0), .y1(z_1_1), .ctrl(rdd_ctrl_st_0));
wire rda_ctrl_st_0;
assign rda_ctrl_st_0 = outCount_for_rd_addr[9];
switch #(logDepth) rdaddr_sw_0_0(.x0(u_0_0), .x1(u_0_1), .y0(u_1_0), .y1(u_1_1), .ctrl(rda_ctrl_st_0));
endmodule |
module memArray2048_41774(next, reset,
x0, y0,
inAddr0,
outAddr0,
x1, y1,
inAddr1,
outAddr1,
clk, inFlip, outFlip);
parameter numBanks = 2;
parameter logBanks = 1;
parameter depth = 1024;
parameter logDepth = 10;
parameter width = 24;
input clk, next, reset;
input inFlip, outFlip;
wire next0;
input [width-1:0] x0;
output [width-1:0] y0;
input [logDepth-1:0] inAddr0, outAddr0;
input [width-1:0] x1;
output [width-1:0] y1;
input [logDepth-1:0] inAddr1, outAddr1;
nextReg #(1024, 10) nextReg_46342(.X(next), .Y(next0), .reset(reset), .clk(clk));
memMod #(depth*2, width, logDepth+1)
memMod0(.in(x0), .out(y0), .inAddr({inFlip, inAddr0}),
.outAddr({outFlip, outAddr0}), .writeSel(1'b1), .clk(clk));
memMod #(depth*2, width, logDepth+1)
memMod1(.in(x1), .out(y1), .inAddr({inFlip, inAddr1}),
.outAddr({outFlip, outAddr1}), .writeSel(1'b1), .clk(clk));
endmodule |
module nextReg(X, Y, reset, clk);
parameter depth=2, logDepth=1;
output Y;
input X;
input clk, reset;
reg [logDepth:0] count;
reg active;
assign Y = (count == depth) ? 1 : 0;
always @ (posedge clk) begin
if (reset == 1) begin
count <= 0;
active <= 0;
end
else if (X == 1) begin
active <= 1;
count <= 1;
end
else if (count == depth) begin
count <= 0;
active <= 0;
end
else if (active)
count <= count+1;
end
endmodule |
module memMod(in, out, inAddr, outAddr, writeSel, clk);
parameter depth=1024, width=16, logDepth=10;
input [width-1:0] in;
input [logDepth-1:0] inAddr, outAddr;
input writeSel, clk;
output [width-1:0] out;
reg [width-1:0] out;
// synthesis attribute ram_style of mem is block
reg [width-1:0] mem[depth-1:0];
always @(posedge clk) begin
out <= mem[outAddr];
if (writeSel)
mem[inAddr] <= in;
end
endmodule |
module memMod_dist(in, out, inAddr, outAddr, writeSel, clk);
parameter depth=1024, width=16, logDepth=10;
input [width-1:0] in;
input [logDepth-1:0] inAddr, outAddr;
input writeSel, clk;
output [width-1:0] out;
reg [width-1:0] out;
// synthesis attribute ram_style of mem is distributed
reg [width-1:0] mem[depth-1:0];
always @(posedge clk) begin
out <= mem[outAddr];
if (writeSel)
mem[inAddr] <= in;
end
endmodule |
module switch(ctrl, x0, x1, y0, y1);
parameter width = 16;
input [width-1:0] x0, x1;
output [width-1:0] y0, y1;
input ctrl;
assign y0 = (ctrl == 0) ? x0 : x1;
assign y1 = (ctrl == 0) ? x1 : x0;
endmodule |
module shiftRegFIFO(X, Y, clk);
parameter depth=1, width=1;
output [width-1:0] Y;
input [width-1:0] X;
input clk;
reg [width-1:0] mem [depth-1:0];
integer index;
assign Y = mem[depth-1];
always @ (posedge clk) begin
for(index=1;index<depth;index=index+1) begin
mem[index] <= mem[index-1];
end
mem[0]<=X;
end
endmodule |
module ICompose_46101(clk, reset, next, next_out,
X0, Y0,
X1, Y1,
X2, Y2,
X3, Y3);
output next_out;
reg next_out;
input clk, reset, next;
reg [10:0] cycle_count;
reg [10:0] count;
input [11:0] X0,
X1,
X2,
X3;
output [11:0] Y0,
Y1,
Y2,
Y3;
reg [11:0] Y0,
Y1,
Y2,
Y3;
reg int_next;
reg state;
wire [11:0] t0;
reg [11:0] s0;
wire [11:0] t1;
reg [11:0] s1;
wire [11:0] t2;
reg [11:0] s2;
wire [11:0] t3;
reg [11:0] s3;
reg [1:0] iri_state;
wire int_next_out;
reg [4:0] i1;
statementList46099 instList46347 (.clk(clk), .reset(reset), .next(int_next), .next_out(int_next_out),
.i1_in(i1),
.X0(s0), .Y0(t0),
.X1(s1), .Y1(t1),
.X2(s2), .Y2(t2),
.X3(s3), .Y3(t3));
always @(posedge clk) begin
if (reset == 1) begin
int_next <= 0;
i1 <= 10;
cycle_count <= 0;
next_out <= 0;
iri_state <= 0;
Y0 <= 0;
Y1 <= 0;
Y2 <= 0;
Y3 <= 0;
end
else begin
Y0 <= t0;
Y1 <= t1;
Y2 <= t2;
Y3 <= t3;
next_out <= 0;
case (iri_state)
0: begin
i1 <= 10;
cycle_count <= 0;
if (next == 1) begin
int_next <= 1;
iri_state <= 1;
end
else begin
int_next <= 0;
iri_state <= 0;
end
end
1: begin
int_next <= 0;
cycle_count <= cycle_count + 1;
i1 <= i1;
if (cycle_count < 1024)
iri_state <= 1;
else
iri_state <= 2;
end
2: begin
cycle_count <= 0;
i1 <= i1 - 1;
if (i1 > 0) begin
iri_state <= 1;
int_next <= 1;
end
else begin
iri_state <= 0;
next_out <= 1;
int_next <= 0;
end
end
endcase
end
end
always @(posedge clk) begin
if (reset == 1) begin
state <= 0;
count <= 0;
s0 <= 0;
s1 <= 0;
s2 <= 0;
s3 <= 0;
end
else begin
case (state)
0: begin
count <= 0;
if (next == 1) begin
state <= 1;
count <= 0;
s0 <= X0;
s1 <= X1;
s2 <= X2;
s3 <= X3;
end
else begin
state <= 0;
count <= 0;
s0 <= t0;
s1 <= t1;
s2 <= t2;
s3 <= t3;
end
end
1: begin
count <= count + 1;
if (count < 1024) begin
s0 <= X0;
s1 <= X1;
s2 <= X2;
s3 <= X3;
state <= 1;
end
else begin
s0 <= t0;
s1 <= t1;
s2 <= t2;
s3 <= t3;
state <= 0;
end
end
endcase
end
end
endmodule |
module statementList46099(clk, reset, next, next_out,
i1_in,
X0, Y0,
X1, Y1,
X2, Y2,
X3, Y3);
output next_out;
input clk, reset, next;
input [4:0] i1_in;
input [11:0] X0,
X1,
X2,
X3;
output [11:0] Y0,
Y1,
Y2,
Y3;
wire [11:0] t0_0;
wire [11:0] t0_1;
wire [11:0] t0_2;
wire [11:0] t0_3;
wire next_0;
wire [11:0] t1_0;
wire [11:0] t1_1;
wire [11:0] t1_2;
wire [11:0] t1_3;
wire next_1;
wire [11:0] t2_0;
wire [11:0] t2_1;
wire [11:0] t2_2;
wire [11:0] t2_3;
wire next_2;
wire [11:0] t3_0;
wire [11:0] t3_1;
wire [11:0] t3_2;
wire [11:0] t3_3;
wire next_3;
wire [4:0] i1;
wire [4:0] i1_0;
assign t0_0 = X0;
assign Y0 = t3_0;
assign t0_1 = X1;
assign Y1 = t3_1;
assign t0_2 = X2;
assign Y2 = t3_2;
assign t0_3 = X3;
assign Y3 = t3_3;
assign next_0 = next;
assign next_out = next_3;
assign i1_0 = i1_in;
// latency=11, gap=1024
DirSum_46014 DirSumInst46350(.next(next_0), .clk(clk), .reset(reset), .next_out(next_1),
.i1(i1_0),
.X0(t0_0), .Y0(t1_0),
.X1(t0_1), .Y1(t1_1),
.X2(t0_2), .Y2(t1_2),
.X3(t0_3), .Y3(t1_3));
// latency=2, gap=1024
codeBlock46016 codeBlockIsnt46351(.clk(clk), .reset(reset), .next_in(next_1), .next_out(next_2),
.X0_in(t1_0), .Y0(t2_0),
.X1_in(t1_1), .Y1(t2_1),
.X2_in(t1_2), .Y2(t2_2),
.X3_in(t1_3), .Y3(t2_3));
// latency=1012, gap=1024
rc46097 instrc46352(.clk(clk), .reset(reset), .next(next_2), .next_out(next_3),
.X0(t2_0), .Y0(t3_0),
.X1(t2_1), .Y1(t3_1),
.X2(t2_2), .Y2(t3_2),
.X3(t2_3), .Y3(t3_3));
endmodule |
module DirSum_46014(clk, reset, next, next_out,
i1,
X0, Y0,
X1, Y1,
X2, Y2,
X3, Y3);
output next_out;
input clk, reset, next;
input [4:0] i1;
reg [9:0] i2;
input [11:0] X0,
X1,
X2,
X3;
output [11:0] Y0,
Y1,
Y2,
Y3;
always @(posedge clk) begin
if (reset == 1) begin
i2 <= 0;
end
else begin
if (next == 1)
i2 <= 0;
else if (i2 == 1023)
i2 <= 0;
else
i2 <= i2 + 1;
end
end
codeBlock41778 codeBlockIsnt46353(.clk(clk), .reset(reset), .next_in(next), .next_out(next_out),
.i2_in(i2),
.i1_in(i1),
.X0_in(X0), .Y0(Y0),
.X1_in(X1), .Y1(Y1),
.X2_in(X2), .Y2(Y2),
.X3_in(X3), .Y3(Y3));
endmodule |
module D1_43962(addr, out, clk);
input clk;
output [11:0] out;
reg [11:0] out, out2, out3;
input [10:0] addr;
always @(posedge clk) begin
out2 <= out3;
out <= out2;
case(addr)
0: out3 <= 12'h400;
1: out3 <= 12'h400;
2: out3 <= 12'h400;
3: out3 <= 12'h400;
4: out3 <= 12'h400;
5: out3 <= 12'h400;
6: out3 <= 12'h400;
7: out3 <= 12'h400;
8: out3 <= 12'h400;
9: out3 <= 12'h400;
10: out3 <= 12'h400;
11: out3 <= 12'h3ff;
12: out3 <= 12'h3ff;
13: out3 <= 12'h3ff;
14: out3 <= 12'h3ff;
15: out3 <= 12'h3ff;
16: out3 <= 12'h3ff;
17: out3 <= 12'h3ff;
18: out3 <= 12'h3fe;
19: out3 <= 12'h3fe;
20: out3 <= 12'h3fe;
21: out3 <= 12'h3fe;
22: out3 <= 12'h3fe;
23: out3 <= 12'h3fd;
24: out3 <= 12'h3fd;
25: out3 <= 12'h3fd;
26: out3 <= 12'h3fd;
27: out3 <= 12'h3fc;
28: out3 <= 12'h3fc;
29: out3 <= 12'h3fc;
30: out3 <= 12'h3fc;
31: out3 <= 12'h3fb;
32: out3 <= 12'h3fb;
33: out3 <= 12'h3fb;
34: out3 <= 12'h3fa;
35: out3 <= 12'h3fa;
36: out3 <= 12'h3fa;
37: out3 <= 12'h3f9;
38: out3 <= 12'h3f9;
39: out3 <= 12'h3f9;
40: out3 <= 12'h3f8;
41: out3 <= 12'h3f8;
42: out3 <= 12'h3f8;
43: out3 <= 12'h3f7;
44: out3 <= 12'h3f7;
45: out3 <= 12'h3f6;
46: out3 <= 12'h3f6;
47: out3 <= 12'h3f5;
48: out3 <= 12'h3f5;
49: out3 <= 12'h3f4;
50: out3 <= 12'h3f4;
51: out3 <= 12'h3f3;
52: out3 <= 12'h3f3;
53: out3 <= 12'h3f2;
54: out3 <= 12'h3f2;
55: out3 <= 12'h3f1;
56: out3 <= 12'h3f1;
57: out3 <= 12'h3f0;
58: out3 <= 12'h3f0;
59: out3 <= 12'h3ef;
60: out3 <= 12'h3ef;
61: out3 <= 12'h3ee;
62: out3 <= 12'h3ee;
63: out3 <= 12'h3ed;
64: out3 <= 12'h3ec;
65: out3 <= 12'h3ec;
66: out3 <= 12'h3eb;
67: out3 <= 12'h3ea;
68: out3 <= 12'h3ea;
69: out3 <= 12'h3e9;
70: out3 <= 12'h3e8;
71: out3 <= 12'h3e8;
72: out3 <= 12'h3e7;
73: out3 <= 12'h3e6;
74: out3 <= 12'h3e6;
75: out3 <= 12'h3e5;
76: out3 <= 12'h3e4;
77: out3 <= 12'h3e4;
78: out3 <= 12'h3e3;
79: out3 <= 12'h3e2;
80: out3 <= 12'h3e1;
81: out3 <= 12'h3e1;
82: out3 <= 12'h3e0;
83: out3 <= 12'h3df;
84: out3 <= 12'h3de;
85: out3 <= 12'h3dd;
86: out3 <= 12'h3dd;
87: out3 <= 12'h3dc;
88: out3 <= 12'h3db;
89: out3 <= 12'h3da;
90: out3 <= 12'h3d9;
91: out3 <= 12'h3d8;
92: out3 <= 12'h3d7;
93: out3 <= 12'h3d7;
94: out3 <= 12'h3d6;
95: out3 <= 12'h3d5;
96: out3 <= 12'h3d4;
97: out3 <= 12'h3d3;
98: out3 <= 12'h3d2;
99: out3 <= 12'h3d1;
100: out3 <= 12'h3d0;
101: out3 <= 12'h3cf;
102: out3 <= 12'h3ce;
103: out3 <= 12'h3cd;
104: out3 <= 12'h3cc;
105: out3 <= 12'h3cb;
106: out3 <= 12'h3ca;
107: out3 <= 12'h3c9;
108: out3 <= 12'h3c8;
109: out3 <= 12'h3c7;
110: out3 <= 12'h3c6;
111: out3 <= 12'h3c5;
112: out3 <= 12'h3c4;
113: out3 <= 12'h3c3;
114: out3 <= 12'h3c2;
115: out3 <= 12'h3c1;
116: out3 <= 12'h3c0;
117: out3 <= 12'h3bf;
118: out3 <= 12'h3be;
119: out3 <= 12'h3bd;
120: out3 <= 12'h3bb;
121: out3 <= 12'h3ba;
122: out3 <= 12'h3b9;
123: out3 <= 12'h3b8;
124: out3 <= 12'h3b7;
125: out3 <= 12'h3b6;
126: out3 <= 12'h3b4;
127: out3 <= 12'h3b3;
128: out3 <= 12'h3b2;
129: out3 <= 12'h3b1;
130: out3 <= 12'h3b0;
131: out3 <= 12'h3ae;
132: out3 <= 12'h3ad;
133: out3 <= 12'h3ac;
134: out3 <= 12'h3ab;
135: out3 <= 12'h3a9;
136: out3 <= 12'h3a8;
137: out3 <= 12'h3a7;
138: out3 <= 12'h3a6;
139: out3 <= 12'h3a4;
140: out3 <= 12'h3a3;
141: out3 <= 12'h3a2;
142: out3 <= 12'h3a0;
143: out3 <= 12'h39f;
144: out3 <= 12'h39e;
145: out3 <= 12'h39c;
146: out3 <= 12'h39b;
147: out3 <= 12'h39a;
148: out3 <= 12'h398;
149: out3 <= 12'h397;
150: out3 <= 12'h395;
151: out3 <= 12'h394;
152: out3 <= 12'h393;
153: out3 <= 12'h391;
154: out3 <= 12'h390;
155: out3 <= 12'h38e;
156: out3 <= 12'h38d;
157: out3 <= 12'h38b;
158: out3 <= 12'h38a;
159: out3 <= 12'h389;
160: out3 <= 12'h387;
161: out3 <= 12'h386;
162: out3 <= 12'h384;
163: out3 <= 12'h383;
164: out3 <= 12'h381;
165: out3 <= 12'h380;
166: out3 <= 12'h37e;
167: out3 <= 12'h37d;
168: out3 <= 12'h37b;
169: out3 <= 12'h379;
170: out3 <= 12'h378;
171: out3 <= 12'h376;
172: out3 <= 12'h375;
173: out3 <= 12'h373;
174: out3 <= 12'h372;
175: out3 <= 12'h370;
176: out3 <= 12'h36e;
177: out3 <= 12'h36d;
178: out3 <= 12'h36b;
179: out3 <= 12'h369;
180: out3 <= 12'h368;
181: out3 <= 12'h366;
182: out3 <= 12'h364;
183: out3 <= 12'h363;
184: out3 <= 12'h361;
185: out3 <= 12'h35f;
186: out3 <= 12'h35e;
187: out3 <= 12'h35c;
188: out3 <= 12'h35a;
189: out3 <= 12'h359;
190: out3 <= 12'h357;
191: out3 <= 12'h355;
192: out3 <= 12'h353;
193: out3 <= 12'h352;
194: out3 <= 12'h350;
195: out3 <= 12'h34e;
196: out3 <= 12'h34c;
197: out3 <= 12'h34b;
198: out3 <= 12'h349;
199: out3 <= 12'h347;
200: out3 <= 12'h345;
201: out3 <= 12'h343;
202: out3 <= 12'h342;
203: out3 <= 12'h340;
204: out3 <= 12'h33e;
205: out3 <= 12'h33c;
206: out3 <= 12'h33a;
207: out3 <= 12'h338;
208: out3 <= 12'h336;
209: out3 <= 12'h335;
210: out3 <= 12'h333;
211: out3 <= 12'h331;
212: out3 <= 12'h32f;
213: out3 <= 12'h32d;
214: out3 <= 12'h32b;
215: out3 <= 12'h329;
216: out3 <= 12'h327;
217: out3 <= 12'h325;
218: out3 <= 12'h323;
219: out3 <= 12'h321;
220: out3 <= 12'h31f;
221: out3 <= 12'h31e;
222: out3 <= 12'h31c;
223: out3 <= 12'h31a;
224: out3 <= 12'h318;
225: out3 <= 12'h316;
226: out3 <= 12'h314;
227: out3 <= 12'h312;
228: out3 <= 12'h310;
229: out3 <= 12'h30e;
230: out3 <= 12'h30b;
231: out3 <= 12'h309;
232: out3 <= 12'h307;
233: out3 <= 12'h305;
234: out3 <= 12'h303;
235: out3 <= 12'h301;
236: out3 <= 12'h2ff;
237: out3 <= 12'h2fd;
238: out3 <= 12'h2fb;
239: out3 <= 12'h2f9;
240: out3 <= 12'h2f7;
241: out3 <= 12'h2f5;
242: out3 <= 12'h2f3;
243: out3 <= 12'h2f0;
244: out3 <= 12'h2ee;
245: out3 <= 12'h2ec;
246: out3 <= 12'h2ea;
247: out3 <= 12'h2e8;
248: out3 <= 12'h2e6;
249: out3 <= 12'h2e3;
250: out3 <= 12'h2e1;
251: out3 <= 12'h2df;
252: out3 <= 12'h2dd;
253: out3 <= 12'h2db;
254: out3 <= 12'h2d9;
255: out3 <= 12'h2d6;
256: out3 <= 12'h2d4;
257: out3 <= 12'h2d2;
258: out3 <= 12'h2d0;
259: out3 <= 12'h2cd;
260: out3 <= 12'h2cb;
261: out3 <= 12'h2c9;
262: out3 <= 12'h2c7;
263: out3 <= 12'h2c4;
264: out3 <= 12'h2c2;
265: out3 <= 12'h2c0;
266: out3 <= 12'h2be;
267: out3 <= 12'h2bb;
268: out3 <= 12'h2b9;
269: out3 <= 12'h2b7;
270: out3 <= 12'h2b4;
271: out3 <= 12'h2b2;
272: out3 <= 12'h2b0;
273: out3 <= 12'h2ad;
274: out3 <= 12'h2ab;
275: out3 <= 12'h2a9;
276: out3 <= 12'h2a6;
277: out3 <= 12'h2a4;
278: out3 <= 12'h2a2;
279: out3 <= 12'h29f;
280: out3 <= 12'h29d;
281: out3 <= 12'h29a;
282: out3 <= 12'h298;
283: out3 <= 12'h296;
284: out3 <= 12'h293;
285: out3 <= 12'h291;
286: out3 <= 12'h28e;
287: out3 <= 12'h28c;
288: out3 <= 12'h28a;
289: out3 <= 12'h287;
290: out3 <= 12'h285;
291: out3 <= 12'h282;
292: out3 <= 12'h280;
293: out3 <= 12'h27d;
294: out3 <= 12'h27b;
295: out3 <= 12'h278;
296: out3 <= 12'h276;
297: out3 <= 12'h274;
298: out3 <= 12'h271;
299: out3 <= 12'h26f;
300: out3 <= 12'h26c;
301: out3 <= 12'h26a;
302: out3 <= 12'h267;
303: out3 <= 12'h265;
304: out3 <= 12'h262;
305: out3 <= 12'h25f;
306: out3 <= 12'h25d;
307: out3 <= 12'h25a;
308: out3 <= 12'h258;
309: out3 <= 12'h255;
310: out3 <= 12'h253;
311: out3 <= 12'h250;
312: out3 <= 12'h24e;
313: out3 <= 12'h24b;
314: out3 <= 12'h248;
315: out3 <= 12'h246;
316: out3 <= 12'h243;
317: out3 <= 12'h241;
318: out3 <= 12'h23e;
319: out3 <= 12'h23c;
320: out3 <= 12'h239;
321: out3 <= 12'h236;
322: out3 <= 12'h234;
323: out3 <= 12'h231;
324: out3 <= 12'h22e;
325: out3 <= 12'h22c;
326: out3 <= 12'h229;
327: out3 <= 12'h226;
328: out3 <= 12'h224;
329: out3 <= 12'h221;
330: out3 <= 12'h21f;
331: out3 <= 12'h21c;
332: out3 <= 12'h219;
333: out3 <= 12'h217;
334: out3 <= 12'h214;
335: out3 <= 12'h211;
336: out3 <= 12'h20e;
337: out3 <= 12'h20c;
338: out3 <= 12'h209;
339: out3 <= 12'h206;
340: out3 <= 12'h204;
341: out3 <= 12'h201;
342: out3 <= 12'h1fe;
343: out3 <= 12'h1fb;
344: out3 <= 12'h1f9;
345: out3 <= 12'h1f6;
346: out3 <= 12'h1f3;
347: out3 <= 12'h1f1;
348: out3 <= 12'h1ee;
349: out3 <= 12'h1eb;
350: out3 <= 12'h1e8;
351: out3 <= 12'h1e5;
352: out3 <= 12'h1e3;
353: out3 <= 12'h1e0;
354: out3 <= 12'h1dd;
355: out3 <= 12'h1da;
356: out3 <= 12'h1d8;
357: out3 <= 12'h1d5;
358: out3 <= 12'h1d2;
359: out3 <= 12'h1cf;
360: out3 <= 12'h1cc;
361: out3 <= 12'h1ca;
362: out3 <= 12'h1c7;
363: out3 <= 12'h1c4;
364: out3 <= 12'h1c1;
365: out3 <= 12'h1be;
366: out3 <= 12'h1bb;
367: out3 <= 12'h1b9;
368: out3 <= 12'h1b6;
369: out3 <= 12'h1b3;
370: out3 <= 12'h1b0;
371: out3 <= 12'h1ad;
372: out3 <= 12'h1aa;
373: out3 <= 12'h1a8;
374: out3 <= 12'h1a5;
375: out3 <= 12'h1a2;
376: out3 <= 12'h19f;
377: out3 <= 12'h19c;
378: out3 <= 12'h199;
379: out3 <= 12'h196;
380: out3 <= 12'h193;
381: out3 <= 12'h191;
382: out3 <= 12'h18e;
383: out3 <= 12'h18b;
384: out3 <= 12'h188;
385: out3 <= 12'h185;
386: out3 <= 12'h182;
387: out3 <= 12'h17f;
388: out3 <= 12'h17c;
389: out3 <= 12'h179;
390: out3 <= 12'h176;
391: out3 <= 12'h173;
392: out3 <= 12'h171;
393: out3 <= 12'h16e;
394: out3 <= 12'h16b;
395: out3 <= 12'h168;
396: out3 <= 12'h165;
397: out3 <= 12'h162;
398: out3 <= 12'h15f;
399: out3 <= 12'h15c;
400: out3 <= 12'h159;
401: out3 <= 12'h156;
402: out3 <= 12'h153;
403: out3 <= 12'h150;
404: out3 <= 12'h14d;
405: out3 <= 12'h14a;
406: out3 <= 12'h147;
407: out3 <= 12'h144;
408: out3 <= 12'h141;
409: out3 <= 12'h13e;
410: out3 <= 12'h13b;
411: out3 <= 12'h138;
412: out3 <= 12'h135;
413: out3 <= 12'h132;
414: out3 <= 12'h12f;
415: out3 <= 12'h12c;
416: out3 <= 12'h129;
417: out3 <= 12'h126;
418: out3 <= 12'h123;
419: out3 <= 12'h120;
420: out3 <= 12'h11d;
421: out3 <= 12'h11a;
422: out3 <= 12'h117;
423: out3 <= 12'h114;
424: out3 <= 12'h111;
425: out3 <= 12'h10e;
426: out3 <= 12'h10b;
427: out3 <= 12'h108;
428: out3 <= 12'h105;
429: out3 <= 12'h102;
430: out3 <= 12'hff;
431: out3 <= 12'hfc;
432: out3 <= 12'hf9;
433: out3 <= 12'hf6;
434: out3 <= 12'hf3;
435: out3 <= 12'hf0;
436: out3 <= 12'hed;
437: out3 <= 12'hea;
438: out3 <= 12'he6;
439: out3 <= 12'he3;
440: out3 <= 12'he0;
441: out3 <= 12'hdd;
442: out3 <= 12'hda;
443: out3 <= 12'hd7;
444: out3 <= 12'hd4;
445: out3 <= 12'hd1;
446: out3 <= 12'hce;
447: out3 <= 12'hcb;
448: out3 <= 12'hc8;
449: out3 <= 12'hc5;
450: out3 <= 12'hc2;
451: out3 <= 12'hbf;
452: out3 <= 12'hbb;
453: out3 <= 12'hb8;
454: out3 <= 12'hb5;
455: out3 <= 12'hb2;
456: out3 <= 12'haf;
457: out3 <= 12'hac;
458: out3 <= 12'ha9;
459: out3 <= 12'ha6;
460: out3 <= 12'ha3;
461: out3 <= 12'ha0;
462: out3 <= 12'h9c;
463: out3 <= 12'h99;
464: out3 <= 12'h96;
465: out3 <= 12'h93;
466: out3 <= 12'h90;
467: out3 <= 12'h8d;
468: out3 <= 12'h8a;
469: out3 <= 12'h87;
470: out3 <= 12'h84;
471: out3 <= 12'h80;
472: out3 <= 12'h7d;
473: out3 <= 12'h7a;
474: out3 <= 12'h77;
475: out3 <= 12'h74;
476: out3 <= 12'h71;
477: out3 <= 12'h6e;
478: out3 <= 12'h6b;
479: out3 <= 12'h67;
480: out3 <= 12'h64;
481: out3 <= 12'h61;
482: out3 <= 12'h5e;
483: out3 <= 12'h5b;
484: out3 <= 12'h58;
485: out3 <= 12'h55;
486: out3 <= 12'h52;
487: out3 <= 12'h4e;
488: out3 <= 12'h4b;
489: out3 <= 12'h48;
490: out3 <= 12'h45;
491: out3 <= 12'h42;
492: out3 <= 12'h3f;
493: out3 <= 12'h3c;
494: out3 <= 12'h39;
495: out3 <= 12'h35;
496: out3 <= 12'h32;
497: out3 <= 12'h2f;
498: out3 <= 12'h2c;
499: out3 <= 12'h29;
500: out3 <= 12'h26;
501: out3 <= 12'h23;
502: out3 <= 12'h1f;
503: out3 <= 12'h1c;
504: out3 <= 12'h19;
505: out3 <= 12'h16;
506: out3 <= 12'h13;
507: out3 <= 12'h10;
508: out3 <= 12'hd;
509: out3 <= 12'h9;
510: out3 <= 12'h6;
511: out3 <= 12'h3;
512: out3 <= 12'h0;
513: out3 <= 12'hffd;
514: out3 <= 12'hffa;
515: out3 <= 12'hff7;
516: out3 <= 12'hff3;
517: out3 <= 12'hff0;
518: out3 <= 12'hfed;
519: out3 <= 12'hfea;
520: out3 <= 12'hfe7;
521: out3 <= 12'hfe4;
522: out3 <= 12'hfe1;
523: out3 <= 12'hfdd;
524: out3 <= 12'hfda;
525: out3 <= 12'hfd7;
526: out3 <= 12'hfd4;
527: out3 <= 12'hfd1;
528: out3 <= 12'hfce;
529: out3 <= 12'hfcb;
530: out3 <= 12'hfc7;
531: out3 <= 12'hfc4;
532: out3 <= 12'hfc1;
533: out3 <= 12'hfbe;
534: out3 <= 12'hfbb;
535: out3 <= 12'hfb8;
536: out3 <= 12'hfb5;
537: out3 <= 12'hfb2;
538: out3 <= 12'hfae;
539: out3 <= 12'hfab;
540: out3 <= 12'hfa8;
541: out3 <= 12'hfa5;
542: out3 <= 12'hfa2;
543: out3 <= 12'hf9f;
544: out3 <= 12'hf9c;
545: out3 <= 12'hf99;
546: out3 <= 12'hf95;
547: out3 <= 12'hf92;
548: out3 <= 12'hf8f;
549: out3 <= 12'hf8c;
550: out3 <= 12'hf89;
551: out3 <= 12'hf86;
552: out3 <= 12'hf83;
553: out3 <= 12'hf80;
554: out3 <= 12'hf7c;
555: out3 <= 12'hf79;
556: out3 <= 12'hf76;
557: out3 <= 12'hf73;
558: out3 <= 12'hf70;
559: out3 <= 12'hf6d;
560: out3 <= 12'hf6a;
561: out3 <= 12'hf67;
562: out3 <= 12'hf64;
563: out3 <= 12'hf60;
564: out3 <= 12'hf5d;
565: out3 <= 12'hf5a;
566: out3 <= 12'hf57;
567: out3 <= 12'hf54;
568: out3 <= 12'hf51;
569: out3 <= 12'hf4e;
570: out3 <= 12'hf4b;
571: out3 <= 12'hf48;
572: out3 <= 12'hf45;
573: out3 <= 12'hf41;
574: out3 <= 12'hf3e;
575: out3 <= 12'hf3b;
576: out3 <= 12'hf38;
577: out3 <= 12'hf35;
578: out3 <= 12'hf32;
579: out3 <= 12'hf2f;
580: out3 <= 12'hf2c;
581: out3 <= 12'hf29;
582: out3 <= 12'hf26;
583: out3 <= 12'hf23;
584: out3 <= 12'hf20;
585: out3 <= 12'hf1d;
586: out3 <= 12'hf1a;
587: out3 <= 12'hf16;
588: out3 <= 12'hf13;
589: out3 <= 12'hf10;
590: out3 <= 12'hf0d;
591: out3 <= 12'hf0a;
592: out3 <= 12'hf07;
593: out3 <= 12'hf04;
594: out3 <= 12'hf01;
595: out3 <= 12'hefe;
596: out3 <= 12'hefb;
597: out3 <= 12'hef8;
598: out3 <= 12'hef5;
599: out3 <= 12'hef2;
600: out3 <= 12'heef;
601: out3 <= 12'heec;
602: out3 <= 12'hee9;
603: out3 <= 12'hee6;
604: out3 <= 12'hee3;
605: out3 <= 12'hee0;
606: out3 <= 12'hedd;
607: out3 <= 12'heda;
608: out3 <= 12'hed7;
609: out3 <= 12'hed4;
610: out3 <= 12'hed1;
611: out3 <= 12'hece;
612: out3 <= 12'hecb;
613: out3 <= 12'hec8;
614: out3 <= 12'hec5;
615: out3 <= 12'hec2;
616: out3 <= 12'hebf;
617: out3 <= 12'hebc;
618: out3 <= 12'heb9;
619: out3 <= 12'heb6;
620: out3 <= 12'heb3;
621: out3 <= 12'heb0;
622: out3 <= 12'head;
623: out3 <= 12'heaa;
624: out3 <= 12'hea7;
625: out3 <= 12'hea4;
626: out3 <= 12'hea1;
627: out3 <= 12'he9e;
628: out3 <= 12'he9b;
629: out3 <= 12'he98;
630: out3 <= 12'he95;
631: out3 <= 12'he92;
632: out3 <= 12'he8f;
633: out3 <= 12'he8d;
634: out3 <= 12'he8a;
635: out3 <= 12'he87;
636: out3 <= 12'he84;
637: out3 <= 12'he81;
638: out3 <= 12'he7e;
639: out3 <= 12'he7b;
640: out3 <= 12'he78;
641: out3 <= 12'he75;
642: out3 <= 12'he72;
643: out3 <= 12'he6f;
644: out3 <= 12'he6d;
645: out3 <= 12'he6a;
646: out3 <= 12'he67;
647: out3 <= 12'he64;
648: out3 <= 12'he61;
649: out3 <= 12'he5e;
650: out3 <= 12'he5b;
651: out3 <= 12'he58;
652: out3 <= 12'he56;
653: out3 <= 12'he53;
654: out3 <= 12'he50;
655: out3 <= 12'he4d;
656: out3 <= 12'he4a;
657: out3 <= 12'he47;
658: out3 <= 12'he45;
659: out3 <= 12'he42;
660: out3 <= 12'he3f;
661: out3 <= 12'he3c;
662: out3 <= 12'he39;
663: out3 <= 12'he36;
664: out3 <= 12'he34;
665: out3 <= 12'he31;
666: out3 <= 12'he2e;
667: out3 <= 12'he2b;
668: out3 <= 12'he28;
669: out3 <= 12'he26;
670: out3 <= 12'he23;
671: out3 <= 12'he20;
672: out3 <= 12'he1d;
673: out3 <= 12'he1b;
674: out3 <= 12'he18;
675: out3 <= 12'he15;
676: out3 <= 12'he12;
677: out3 <= 12'he0f;
678: out3 <= 12'he0d;
679: out3 <= 12'he0a;
680: out3 <= 12'he07;
681: out3 <= 12'he05;
682: out3 <= 12'he02;
683: out3 <= 12'hdff;
684: out3 <= 12'hdfc;
685: out3 <= 12'hdfa;
686: out3 <= 12'hdf7;
687: out3 <= 12'hdf4;
688: out3 <= 12'hdf2;
689: out3 <= 12'hdef;
690: out3 <= 12'hdec;
691: out3 <= 12'hde9;
692: out3 <= 12'hde7;
693: out3 <= 12'hde4;
694: out3 <= 12'hde1;
695: out3 <= 12'hddf;
696: out3 <= 12'hddc;
697: out3 <= 12'hdda;
698: out3 <= 12'hdd7;
699: out3 <= 12'hdd4;
700: out3 <= 12'hdd2;
701: out3 <= 12'hdcf;
702: out3 <= 12'hdcc;
703: out3 <= 12'hdca;
704: out3 <= 12'hdc7;
705: out3 <= 12'hdc4;
706: out3 <= 12'hdc2;
707: out3 <= 12'hdbf;
708: out3 <= 12'hdbd;
709: out3 <= 12'hdba;
710: out3 <= 12'hdb8;
711: out3 <= 12'hdb5;
712: out3 <= 12'hdb2;
713: out3 <= 12'hdb0;
714: out3 <= 12'hdad;
715: out3 <= 12'hdab;
716: out3 <= 12'hda8;
717: out3 <= 12'hda6;
718: out3 <= 12'hda3;
719: out3 <= 12'hda1;
720: out3 <= 12'hd9e;
721: out3 <= 12'hd9b;
722: out3 <= 12'hd99;
723: out3 <= 12'hd96;
724: out3 <= 12'hd94;
725: out3 <= 12'hd91;
726: out3 <= 12'hd8f;
727: out3 <= 12'hd8c;
728: out3 <= 12'hd8a;
729: out3 <= 12'hd88;
730: out3 <= 12'hd85;
731: out3 <= 12'hd83;
732: out3 <= 12'hd80;
733: out3 <= 12'hd7e;
734: out3 <= 12'hd7b;
735: out3 <= 12'hd79;
736: out3 <= 12'hd76;
737: out3 <= 12'hd74;
738: out3 <= 12'hd72;
739: out3 <= 12'hd6f;
740: out3 <= 12'hd6d;
741: out3 <= 12'hd6a;
742: out3 <= 12'hd68;
743: out3 <= 12'hd66;
744: out3 <= 12'hd63;
745: out3 <= 12'hd61;
746: out3 <= 12'hd5e;
747: out3 <= 12'hd5c;
748: out3 <= 12'hd5a;
749: out3 <= 12'hd57;
750: out3 <= 12'hd55;
751: out3 <= 12'hd53;
752: out3 <= 12'hd50;
753: out3 <= 12'hd4e;
754: out3 <= 12'hd4c;
755: out3 <= 12'hd49;
756: out3 <= 12'hd47;
757: out3 <= 12'hd45;
758: out3 <= 12'hd42;
759: out3 <= 12'hd40;
760: out3 <= 12'hd3e;
761: out3 <= 12'hd3c;
762: out3 <= 12'hd39;
763: out3 <= 12'hd37;
764: out3 <= 12'hd35;
765: out3 <= 12'hd33;
766: out3 <= 12'hd30;
767: out3 <= 12'hd2e;
768: out3 <= 12'hd2c;
769: out3 <= 12'hd2a;
770: out3 <= 12'hd27;
771: out3 <= 12'hd25;
772: out3 <= 12'hd23;
773: out3 <= 12'hd21;
774: out3 <= 12'hd1f;
775: out3 <= 12'hd1d;
776: out3 <= 12'hd1a;
777: out3 <= 12'hd18;
778: out3 <= 12'hd16;
779: out3 <= 12'hd14;
780: out3 <= 12'hd12;
781: out3 <= 12'hd10;
782: out3 <= 12'hd0d;
783: out3 <= 12'hd0b;
784: out3 <= 12'hd09;
785: out3 <= 12'hd07;
786: out3 <= 12'hd05;
787: out3 <= 12'hd03;
788: out3 <= 12'hd01;
789: out3 <= 12'hcff;
790: out3 <= 12'hcfd;
791: out3 <= 12'hcfb;
792: out3 <= 12'hcf9;
793: out3 <= 12'hcf7;
794: out3 <= 12'hcf5;
795: out3 <= 12'hcf2;
796: out3 <= 12'hcf0;
797: out3 <= 12'hcee;
798: out3 <= 12'hcec;
799: out3 <= 12'hcea;
800: out3 <= 12'hce8;
801: out3 <= 12'hce6;
802: out3 <= 12'hce4;
803: out3 <= 12'hce2;
804: out3 <= 12'hce1;
805: out3 <= 12'hcdf;
806: out3 <= 12'hcdd;
807: out3 <= 12'hcdb;
808: out3 <= 12'hcd9;
809: out3 <= 12'hcd7;
810: out3 <= 12'hcd5;
811: out3 <= 12'hcd3;
812: out3 <= 12'hcd1;
813: out3 <= 12'hccf;
814: out3 <= 12'hccd;
815: out3 <= 12'hccb;
816: out3 <= 12'hcca;
817: out3 <= 12'hcc8;
818: out3 <= 12'hcc6;
819: out3 <= 12'hcc4;
820: out3 <= 12'hcc2;
821: out3 <= 12'hcc0;
822: out3 <= 12'hcbe;
823: out3 <= 12'hcbd;
824: out3 <= 12'hcbb;
825: out3 <= 12'hcb9;
826: out3 <= 12'hcb7;
827: out3 <= 12'hcb5;
828: out3 <= 12'hcb4;
829: out3 <= 12'hcb2;
830: out3 <= 12'hcb0;
831: out3 <= 12'hcae;
832: out3 <= 12'hcad;
833: out3 <= 12'hcab;
834: out3 <= 12'hca9;
835: out3 <= 12'hca7;
836: out3 <= 12'hca6;
837: out3 <= 12'hca4;
838: out3 <= 12'hca2;
839: out3 <= 12'hca1;
840: out3 <= 12'hc9f;
841: out3 <= 12'hc9d;
842: out3 <= 12'hc9c;
843: out3 <= 12'hc9a;
844: out3 <= 12'hc98;
845: out3 <= 12'hc97;
846: out3 <= 12'hc95;
847: out3 <= 12'hc93;
848: out3 <= 12'hc92;
849: out3 <= 12'hc90;
850: out3 <= 12'hc8e;
851: out3 <= 12'hc8d;
852: out3 <= 12'hc8b;
853: out3 <= 12'hc8a;
854: out3 <= 12'hc88;
855: out3 <= 12'hc87;
856: out3 <= 12'hc85;
857: out3 <= 12'hc83;
858: out3 <= 12'hc82;
859: out3 <= 12'hc80;
860: out3 <= 12'hc7f;
861: out3 <= 12'hc7d;
862: out3 <= 12'hc7c;
863: out3 <= 12'hc7a;
864: out3 <= 12'hc79;
865: out3 <= 12'hc77;
866: out3 <= 12'hc76;
867: out3 <= 12'hc75;
868: out3 <= 12'hc73;
869: out3 <= 12'hc72;
870: out3 <= 12'hc70;
871: out3 <= 12'hc6f;
872: out3 <= 12'hc6d;
873: out3 <= 12'hc6c;
874: out3 <= 12'hc6b;
875: out3 <= 12'hc69;
876: out3 <= 12'hc68;
877: out3 <= 12'hc66;
878: out3 <= 12'hc65;
879: out3 <= 12'hc64;
880: out3 <= 12'hc62;
881: out3 <= 12'hc61;
882: out3 <= 12'hc60;
883: out3 <= 12'hc5e;
884: out3 <= 12'hc5d;
885: out3 <= 12'hc5c;
886: out3 <= 12'hc5a;
887: out3 <= 12'hc59;
888: out3 <= 12'hc58;
889: out3 <= 12'hc57;
890: out3 <= 12'hc55;
891: out3 <= 12'hc54;
892: out3 <= 12'hc53;
893: out3 <= 12'hc52;
894: out3 <= 12'hc50;
895: out3 <= 12'hc4f;
896: out3 <= 12'hc4e;
897: out3 <= 12'hc4d;
898: out3 <= 12'hc4c;
899: out3 <= 12'hc4a;
900: out3 <= 12'hc49;
901: out3 <= 12'hc48;
902: out3 <= 12'hc47;
903: out3 <= 12'hc46;
904: out3 <= 12'hc45;
905: out3 <= 12'hc43;
906: out3 <= 12'hc42;
907: out3 <= 12'hc41;
908: out3 <= 12'hc40;
909: out3 <= 12'hc3f;
910: out3 <= 12'hc3e;
911: out3 <= 12'hc3d;
912: out3 <= 12'hc3c;
913: out3 <= 12'hc3b;
914: out3 <= 12'hc3a;
915: out3 <= 12'hc39;
916: out3 <= 12'hc38;
917: out3 <= 12'hc37;
918: out3 <= 12'hc36;
919: out3 <= 12'hc35;
920: out3 <= 12'hc34;
921: out3 <= 12'hc33;
922: out3 <= 12'hc32;
923: out3 <= 12'hc31;
924: out3 <= 12'hc30;
925: out3 <= 12'hc2f;
926: out3 <= 12'hc2e;
927: out3 <= 12'hc2d;
928: out3 <= 12'hc2c;
929: out3 <= 12'hc2b;
930: out3 <= 12'hc2a;
931: out3 <= 12'hc29;
932: out3 <= 12'hc29;
933: out3 <= 12'hc28;
934: out3 <= 12'hc27;
935: out3 <= 12'hc26;
936: out3 <= 12'hc25;
937: out3 <= 12'hc24;
938: out3 <= 12'hc23;
939: out3 <= 12'hc23;
940: out3 <= 12'hc22;
941: out3 <= 12'hc21;
942: out3 <= 12'hc20;
943: out3 <= 12'hc1f;
944: out3 <= 12'hc1f;
945: out3 <= 12'hc1e;
946: out3 <= 12'hc1d;
947: out3 <= 12'hc1c;
948: out3 <= 12'hc1c;
949: out3 <= 12'hc1b;
950: out3 <= 12'hc1a;
951: out3 <= 12'hc1a;
952: out3 <= 12'hc19;
953: out3 <= 12'hc18;
954: out3 <= 12'hc18;
955: out3 <= 12'hc17;
956: out3 <= 12'hc16;
957: out3 <= 12'hc16;
958: out3 <= 12'hc15;
959: out3 <= 12'hc14;
960: out3 <= 12'hc14;
961: out3 <= 12'hc13;
962: out3 <= 12'hc12;
963: out3 <= 12'hc12;
964: out3 <= 12'hc11;
965: out3 <= 12'hc11;
966: out3 <= 12'hc10;
967: out3 <= 12'hc10;
968: out3 <= 12'hc0f;
969: out3 <= 12'hc0f;
970: out3 <= 12'hc0e;
971: out3 <= 12'hc0e;
972: out3 <= 12'hc0d;
973: out3 <= 12'hc0d;
974: out3 <= 12'hc0c;
975: out3 <= 12'hc0c;
976: out3 <= 12'hc0b;
977: out3 <= 12'hc0b;
978: out3 <= 12'hc0a;
979: out3 <= 12'hc0a;
980: out3 <= 12'hc09;
981: out3 <= 12'hc09;
982: out3 <= 12'hc08;
983: out3 <= 12'hc08;
984: out3 <= 12'hc08;
985: out3 <= 12'hc07;
986: out3 <= 12'hc07;
987: out3 <= 12'hc07;
988: out3 <= 12'hc06;
989: out3 <= 12'hc06;
990: out3 <= 12'hc06;
991: out3 <= 12'hc05;
992: out3 <= 12'hc05;
993: out3 <= 12'hc05;
994: out3 <= 12'hc04;
995: out3 <= 12'hc04;
996: out3 <= 12'hc04;
997: out3 <= 12'hc04;
998: out3 <= 12'hc03;
999: out3 <= 12'hc03;
1000: out3 <= 12'hc03;
1001: out3 <= 12'hc03;
1002: out3 <= 12'hc02;
1003: out3 <= 12'hc02;
1004: out3 <= 12'hc02;
1005: out3 <= 12'hc02;
1006: out3 <= 12'hc02;
1007: out3 <= 12'hc01;
1008: out3 <= 12'hc01;
1009: out3 <= 12'hc01;
1010: out3 <= 12'hc01;
1011: out3 <= 12'hc01;
1012: out3 <= 12'hc01;
1013: out3 <= 12'hc01;
1014: out3 <= 12'hc00;
1015: out3 <= 12'hc00;
1016: out3 <= 12'hc00;
1017: out3 <= 12'hc00;
1018: out3 <= 12'hc00;
1019: out3 <= 12'hc00;
1020: out3 <= 12'hc00;
1021: out3 <= 12'hc00;
1022: out3 <= 12'hc00;
1023: out3 <= 12'hc00;
1024: out3 <= 12'h400;
1025: out3 <= 12'h400;
1026: out3 <= 12'h400;
1027: out3 <= 12'h400;
1028: out3 <= 12'h400;
1029: out3 <= 12'h400;
1030: out3 <= 12'h3ff;
1031: out3 <= 12'h3ff;
1032: out3 <= 12'h3ff;
1033: out3 <= 12'h3fe;
1034: out3 <= 12'h3fe;
1035: out3 <= 12'h3fe;
1036: out3 <= 12'h3fd;
1037: out3 <= 12'h3fd;
1038: out3 <= 12'h3fc;
1039: out3 <= 12'h3fc;
1040: out3 <= 12'h3fb;
1041: out3 <= 12'h3fa;
1042: out3 <= 12'h3fa;
1043: out3 <= 12'h3f9;
1044: out3 <= 12'h3f8;
1045: out3 <= 12'h3f8;
1046: out3 <= 12'h3f7;
1047: out3 <= 12'h3f6;
1048: out3 <= 12'h3f5;
1049: out3 <= 12'h3f4;
1050: out3 <= 12'h3f3;
1051: out3 <= 12'h3f2;
1052: out3 <= 12'h3f1;
1053: out3 <= 12'h3f0;
1054: out3 <= 12'h3ef;
1055: out3 <= 12'h3ee;
1056: out3 <= 12'h3ec;
1057: out3 <= 12'h3eb;
1058: out3 <= 12'h3ea;
1059: out3 <= 12'h3e8;
1060: out3 <= 12'h3e7;
1061: out3 <= 12'h3e6;
1062: out3 <= 12'h3e4;
1063: out3 <= 12'h3e3;
1064: out3 <= 12'h3e1;
1065: out3 <= 12'h3e0;
1066: out3 <= 12'h3de;
1067: out3 <= 12'h3dd;
1068: out3 <= 12'h3db;
1069: out3 <= 12'h3d9;
1070: out3 <= 12'h3d7;
1071: out3 <= 12'h3d6;
1072: out3 <= 12'h3d4;
1073: out3 <= 12'h3d2;
1074: out3 <= 12'h3d0;
1075: out3 <= 12'h3ce;
1076: out3 <= 12'h3cc;
1077: out3 <= 12'h3ca;
1078: out3 <= 12'h3c8;
1079: out3 <= 12'h3c6;
1080: out3 <= 12'h3c4;
1081: out3 <= 12'h3c2;
1082: out3 <= 12'h3c0;
1083: out3 <= 12'h3be;
1084: out3 <= 12'h3bb;
1085: out3 <= 12'h3b9;
1086: out3 <= 12'h3b7;
1087: out3 <= 12'h3b4;
1088: out3 <= 12'h3b2;
1089: out3 <= 12'h3b0;
1090: out3 <= 12'h3ad;
1091: out3 <= 12'h3ab;
1092: out3 <= 12'h3a8;
1093: out3 <= 12'h3a6;
1094: out3 <= 12'h3a3;
1095: out3 <= 12'h3a0;
1096: out3 <= 12'h39e;
1097: out3 <= 12'h39b;
1098: out3 <= 12'h398;
1099: out3 <= 12'h395;
1100: out3 <= 12'h393;
1101: out3 <= 12'h390;
1102: out3 <= 12'h38d;
1103: out3 <= 12'h38a;
1104: out3 <= 12'h387;
1105: out3 <= 12'h384;
1106: out3 <= 12'h381;
1107: out3 <= 12'h37e;
1108: out3 <= 12'h37b;
1109: out3 <= 12'h378;
1110: out3 <= 12'h375;
1111: out3 <= 12'h372;
1112: out3 <= 12'h36e;
1113: out3 <= 12'h36b;
1114: out3 <= 12'h368;
1115: out3 <= 12'h364;
1116: out3 <= 12'h361;
1117: out3 <= 12'h35e;
1118: out3 <= 12'h35a;
1119: out3 <= 12'h357;
1120: out3 <= 12'h353;
1121: out3 <= 12'h350;
1122: out3 <= 12'h34c;
1123: out3 <= 12'h349;
1124: out3 <= 12'h345;
1125: out3 <= 12'h342;
1126: out3 <= 12'h33e;
1127: out3 <= 12'h33a;
1128: out3 <= 12'h336;
1129: out3 <= 12'h333;
1130: out3 <= 12'h32f;
1131: out3 <= 12'h32b;
1132: out3 <= 12'h327;
1133: out3 <= 12'h323;
1134: out3 <= 12'h31f;
1135: out3 <= 12'h31c;
1136: out3 <= 12'h318;
1137: out3 <= 12'h314;
1138: out3 <= 12'h310;
1139: out3 <= 12'h30b;
1140: out3 <= 12'h307;
1141: out3 <= 12'h303;
1142: out3 <= 12'h2ff;
1143: out3 <= 12'h2fb;
1144: out3 <= 12'h2f7;
1145: out3 <= 12'h2f3;
1146: out3 <= 12'h2ee;
1147: out3 <= 12'h2ea;
1148: out3 <= 12'h2e6;
1149: out3 <= 12'h2e1;
1150: out3 <= 12'h2dd;
1151: out3 <= 12'h2d9;
1152: out3 <= 12'h2d4;
1153: out3 <= 12'h2d0;
1154: out3 <= 12'h2cb;
1155: out3 <= 12'h2c7;
1156: out3 <= 12'h2c2;
1157: out3 <= 12'h2be;
1158: out3 <= 12'h2b9;
1159: out3 <= 12'h2b4;
1160: out3 <= 12'h2b0;
1161: out3 <= 12'h2ab;
1162: out3 <= 12'h2a6;
1163: out3 <= 12'h2a2;
1164: out3 <= 12'h29d;
1165: out3 <= 12'h298;
1166: out3 <= 12'h293;
1167: out3 <= 12'h28e;
1168: out3 <= 12'h28a;
1169: out3 <= 12'h285;
1170: out3 <= 12'h280;
1171: out3 <= 12'h27b;
1172: out3 <= 12'h276;
1173: out3 <= 12'h271;
1174: out3 <= 12'h26c;
1175: out3 <= 12'h267;
1176: out3 <= 12'h262;
1177: out3 <= 12'h25d;
1178: out3 <= 12'h258;
1179: out3 <= 12'h253;
1180: out3 <= 12'h24e;
1181: out3 <= 12'h248;
1182: out3 <= 12'h243;
1183: out3 <= 12'h23e;
1184: out3 <= 12'h239;
1185: out3 <= 12'h234;
1186: out3 <= 12'h22e;
1187: out3 <= 12'h229;
1188: out3 <= 12'h224;
1189: out3 <= 12'h21f;
1190: out3 <= 12'h219;
1191: out3 <= 12'h214;
1192: out3 <= 12'h20e;
1193: out3 <= 12'h209;
1194: out3 <= 12'h204;
1195: out3 <= 12'h1fe;
1196: out3 <= 12'h1f9;
1197: out3 <= 12'h1f3;
1198: out3 <= 12'h1ee;
1199: out3 <= 12'h1e8;
1200: out3 <= 12'h1e3;
1201: out3 <= 12'h1dd;
1202: out3 <= 12'h1d8;
1203: out3 <= 12'h1d2;
1204: out3 <= 12'h1cc;
1205: out3 <= 12'h1c7;
1206: out3 <= 12'h1c1;
1207: out3 <= 12'h1bb;
1208: out3 <= 12'h1b6;
1209: out3 <= 12'h1b0;
1210: out3 <= 12'h1aa;
1211: out3 <= 12'h1a5;
1212: out3 <= 12'h19f;
1213: out3 <= 12'h199;
1214: out3 <= 12'h193;
1215: out3 <= 12'h18e;
1216: out3 <= 12'h188;
1217: out3 <= 12'h182;
1218: out3 <= 12'h17c;
1219: out3 <= 12'h176;
1220: out3 <= 12'h171;
1221: out3 <= 12'h16b;
1222: out3 <= 12'h165;
1223: out3 <= 12'h15f;
1224: out3 <= 12'h159;
1225: out3 <= 12'h153;
1226: out3 <= 12'h14d;
1227: out3 <= 12'h147;
1228: out3 <= 12'h141;
1229: out3 <= 12'h13b;
1230: out3 <= 12'h135;
1231: out3 <= 12'h12f;
1232: out3 <= 12'h129;
1233: out3 <= 12'h123;
1234: out3 <= 12'h11d;
1235: out3 <= 12'h117;
1236: out3 <= 12'h111;
1237: out3 <= 12'h10b;
1238: out3 <= 12'h105;
1239: out3 <= 12'hff;
1240: out3 <= 12'hf9;
1241: out3 <= 12'hf3;
1242: out3 <= 12'hed;
1243: out3 <= 12'he6;
1244: out3 <= 12'he0;
1245: out3 <= 12'hda;
1246: out3 <= 12'hd4;
1247: out3 <= 12'hce;
1248: out3 <= 12'hc8;
1249: out3 <= 12'hc2;
1250: out3 <= 12'hbb;
1251: out3 <= 12'hb5;
1252: out3 <= 12'haf;
1253: out3 <= 12'ha9;
1254: out3 <= 12'ha3;
1255: out3 <= 12'h9c;
1256: out3 <= 12'h96;
1257: out3 <= 12'h90;
1258: out3 <= 12'h8a;
1259: out3 <= 12'h84;
1260: out3 <= 12'h7d;
1261: out3 <= 12'h77;
1262: out3 <= 12'h71;
1263: out3 <= 12'h6b;
1264: out3 <= 12'h64;
1265: out3 <= 12'h5e;
1266: out3 <= 12'h58;
1267: out3 <= 12'h52;
1268: out3 <= 12'h4b;
1269: out3 <= 12'h45;
1270: out3 <= 12'h3f;
1271: out3 <= 12'h39;
1272: out3 <= 12'h32;
1273: out3 <= 12'h2c;
1274: out3 <= 12'h26;
1275: out3 <= 12'h1f;
1276: out3 <= 12'h19;
1277: out3 <= 12'h13;
1278: out3 <= 12'hd;
1279: out3 <= 12'h6;
1280: out3 <= 12'h0;
1281: out3 <= 12'hffa;
1282: out3 <= 12'hff3;
1283: out3 <= 12'hfed;
1284: out3 <= 12'hfe7;
1285: out3 <= 12'hfe1;
1286: out3 <= 12'hfda;
1287: out3 <= 12'hfd4;
1288: out3 <= 12'hfce;
1289: out3 <= 12'hfc7;
1290: out3 <= 12'hfc1;
1291: out3 <= 12'hfbb;
1292: out3 <= 12'hfb5;
1293: out3 <= 12'hfae;
1294: out3 <= 12'hfa8;
1295: out3 <= 12'hfa2;
1296: out3 <= 12'hf9c;
1297: out3 <= 12'hf95;
1298: out3 <= 12'hf8f;
1299: out3 <= 12'hf89;
1300: out3 <= 12'hf83;
1301: out3 <= 12'hf7c;
1302: out3 <= 12'hf76;
1303: out3 <= 12'hf70;
1304: out3 <= 12'hf6a;
1305: out3 <= 12'hf64;
1306: out3 <= 12'hf5d;
1307: out3 <= 12'hf57;
1308: out3 <= 12'hf51;
1309: out3 <= 12'hf4b;
1310: out3 <= 12'hf45;
1311: out3 <= 12'hf3e;
1312: out3 <= 12'hf38;
1313: out3 <= 12'hf32;
1314: out3 <= 12'hf2c;
1315: out3 <= 12'hf26;
1316: out3 <= 12'hf20;
1317: out3 <= 12'hf1a;
1318: out3 <= 12'hf13;
1319: out3 <= 12'hf0d;
1320: out3 <= 12'hf07;
1321: out3 <= 12'hf01;
1322: out3 <= 12'hefb;
1323: out3 <= 12'hef5;
1324: out3 <= 12'heef;
1325: out3 <= 12'hee9;
1326: out3 <= 12'hee3;
1327: out3 <= 12'hedd;
1328: out3 <= 12'hed7;
1329: out3 <= 12'hed1;
1330: out3 <= 12'hecb;
1331: out3 <= 12'hec5;
1332: out3 <= 12'hebf;
1333: out3 <= 12'heb9;
1334: out3 <= 12'heb3;
1335: out3 <= 12'head;
1336: out3 <= 12'hea7;
1337: out3 <= 12'hea1;
1338: out3 <= 12'he9b;
1339: out3 <= 12'he95;
1340: out3 <= 12'he8f;
1341: out3 <= 12'he8a;
1342: out3 <= 12'he84;
1343: out3 <= 12'he7e;
1344: out3 <= 12'he78;
1345: out3 <= 12'he72;
1346: out3 <= 12'he6d;
1347: out3 <= 12'he67;
1348: out3 <= 12'he61;
1349: out3 <= 12'he5b;
1350: out3 <= 12'he56;
1351: out3 <= 12'he50;
1352: out3 <= 12'he4a;
1353: out3 <= 12'he45;
1354: out3 <= 12'he3f;
1355: out3 <= 12'he39;
1356: out3 <= 12'he34;
1357: out3 <= 12'he2e;
1358: out3 <= 12'he28;
1359: out3 <= 12'he23;
1360: out3 <= 12'he1d;
1361: out3 <= 12'he18;
1362: out3 <= 12'he12;
1363: out3 <= 12'he0d;
1364: out3 <= 12'he07;
1365: out3 <= 12'he02;
1366: out3 <= 12'hdfc;
1367: out3 <= 12'hdf7;
1368: out3 <= 12'hdf2;
1369: out3 <= 12'hdec;
1370: out3 <= 12'hde7;
1371: out3 <= 12'hde1;
1372: out3 <= 12'hddc;
1373: out3 <= 12'hdd7;
1374: out3 <= 12'hdd2;
1375: out3 <= 12'hdcc;
1376: out3 <= 12'hdc7;
1377: out3 <= 12'hdc2;
1378: out3 <= 12'hdbd;
1379: out3 <= 12'hdb8;
1380: out3 <= 12'hdb2;
1381: out3 <= 12'hdad;
1382: out3 <= 12'hda8;
1383: out3 <= 12'hda3;
1384: out3 <= 12'hd9e;
1385: out3 <= 12'hd99;
1386: out3 <= 12'hd94;
1387: out3 <= 12'hd8f;
1388: out3 <= 12'hd8a;
1389: out3 <= 12'hd85;
1390: out3 <= 12'hd80;
1391: out3 <= 12'hd7b;
1392: out3 <= 12'hd76;
1393: out3 <= 12'hd72;
1394: out3 <= 12'hd6d;
1395: out3 <= 12'hd68;
1396: out3 <= 12'hd63;
1397: out3 <= 12'hd5e;
1398: out3 <= 12'hd5a;
1399: out3 <= 12'hd55;
1400: out3 <= 12'hd50;
1401: out3 <= 12'hd4c;
1402: out3 <= 12'hd47;
1403: out3 <= 12'hd42;
1404: out3 <= 12'hd3e;
1405: out3 <= 12'hd39;
1406: out3 <= 12'hd35;
1407: out3 <= 12'hd30;
1408: out3 <= 12'hd2c;
1409: out3 <= 12'hd27;
1410: out3 <= 12'hd23;
1411: out3 <= 12'hd1f;
1412: out3 <= 12'hd1a;
1413: out3 <= 12'hd16;
1414: out3 <= 12'hd12;
1415: out3 <= 12'hd0d;
1416: out3 <= 12'hd09;
1417: out3 <= 12'hd05;
1418: out3 <= 12'hd01;
1419: out3 <= 12'hcfd;
1420: out3 <= 12'hcf9;
1421: out3 <= 12'hcf5;
1422: out3 <= 12'hcf0;
1423: out3 <= 12'hcec;
1424: out3 <= 12'hce8;
1425: out3 <= 12'hce4;
1426: out3 <= 12'hce1;
1427: out3 <= 12'hcdd;
1428: out3 <= 12'hcd9;
1429: out3 <= 12'hcd5;
1430: out3 <= 12'hcd1;
1431: out3 <= 12'hccd;
1432: out3 <= 12'hcca;
1433: out3 <= 12'hcc6;
1434: out3 <= 12'hcc2;
1435: out3 <= 12'hcbe;
1436: out3 <= 12'hcbb;
1437: out3 <= 12'hcb7;
1438: out3 <= 12'hcb4;
1439: out3 <= 12'hcb0;
1440: out3 <= 12'hcad;
1441: out3 <= 12'hca9;
1442: out3 <= 12'hca6;
1443: out3 <= 12'hca2;
1444: out3 <= 12'hc9f;
1445: out3 <= 12'hc9c;
1446: out3 <= 12'hc98;
1447: out3 <= 12'hc95;
1448: out3 <= 12'hc92;
1449: out3 <= 12'hc8e;
1450: out3 <= 12'hc8b;
1451: out3 <= 12'hc88;
1452: out3 <= 12'hc85;
1453: out3 <= 12'hc82;
1454: out3 <= 12'hc7f;
1455: out3 <= 12'hc7c;
1456: out3 <= 12'hc79;
1457: out3 <= 12'hc76;
1458: out3 <= 12'hc73;
1459: out3 <= 12'hc70;
1460: out3 <= 12'hc6d;
1461: out3 <= 12'hc6b;
1462: out3 <= 12'hc68;
1463: out3 <= 12'hc65;
1464: out3 <= 12'hc62;
1465: out3 <= 12'hc60;
1466: out3 <= 12'hc5d;
1467: out3 <= 12'hc5a;
1468: out3 <= 12'hc58;
1469: out3 <= 12'hc55;
1470: out3 <= 12'hc53;
1471: out3 <= 12'hc50;
1472: out3 <= 12'hc4e;
1473: out3 <= 12'hc4c;
1474: out3 <= 12'hc49;
1475: out3 <= 12'hc47;
1476: out3 <= 12'hc45;
1477: out3 <= 12'hc42;
1478: out3 <= 12'hc40;
1479: out3 <= 12'hc3e;
1480: out3 <= 12'hc3c;
1481: out3 <= 12'hc3a;
1482: out3 <= 12'hc38;
1483: out3 <= 12'hc36;
1484: out3 <= 12'hc34;
1485: out3 <= 12'hc32;
1486: out3 <= 12'hc30;
1487: out3 <= 12'hc2e;
1488: out3 <= 12'hc2c;
1489: out3 <= 12'hc2a;
1490: out3 <= 12'hc29;
1491: out3 <= 12'hc27;
1492: out3 <= 12'hc25;
1493: out3 <= 12'hc23;
1494: out3 <= 12'hc22;
1495: out3 <= 12'hc20;
1496: out3 <= 12'hc1f;
1497: out3 <= 12'hc1d;
1498: out3 <= 12'hc1c;
1499: out3 <= 12'hc1a;
1500: out3 <= 12'hc19;
1501: out3 <= 12'hc18;
1502: out3 <= 12'hc16;
1503: out3 <= 12'hc15;
1504: out3 <= 12'hc14;
1505: out3 <= 12'hc12;
1506: out3 <= 12'hc11;
1507: out3 <= 12'hc10;
1508: out3 <= 12'hc0f;
1509: out3 <= 12'hc0e;
1510: out3 <= 12'hc0d;
1511: out3 <= 12'hc0c;
1512: out3 <= 12'hc0b;
1513: out3 <= 12'hc0a;
1514: out3 <= 12'hc09;
1515: out3 <= 12'hc08;
1516: out3 <= 12'hc08;
1517: out3 <= 12'hc07;
1518: out3 <= 12'hc06;
1519: out3 <= 12'hc06;
1520: out3 <= 12'hc05;
1521: out3 <= 12'hc04;
1522: out3 <= 12'hc04;
1523: out3 <= 12'hc03;
1524: out3 <= 12'hc03;
1525: out3 <= 12'hc02;
1526: out3 <= 12'hc02;
1527: out3 <= 12'hc02;
1528: out3 <= 12'hc01;
1529: out3 <= 12'hc01;
1530: out3 <= 12'hc01;
1531: out3 <= 12'hc00;
1532: out3 <= 12'hc00;
1533: out3 <= 12'hc00;
1534: out3 <= 12'hc00;
1535: out3 <= 12'hc00;
1536: out3 <= 12'hc00;
1537: out3 <= 12'hc00;
1538: out3 <= 12'hc00;
1539: out3 <= 12'hc00;
1540: out3 <= 12'hc00;
1541: out3 <= 12'hc00;
1542: out3 <= 12'hc01;
1543: out3 <= 12'hc01;
1544: out3 <= 12'hc01;
1545: out3 <= 12'hc02;
1546: out3 <= 12'hc02;
1547: out3 <= 12'hc02;
1548: out3 <= 12'hc03;
1549: out3 <= 12'hc03;
1550: out3 <= 12'hc04;
1551: out3 <= 12'hc04;
1552: out3 <= 12'hc05;
1553: out3 <= 12'hc06;
1554: out3 <= 12'hc06;
1555: out3 <= 12'hc07;
1556: out3 <= 12'hc08;
1557: out3 <= 12'hc08;
1558: out3 <= 12'hc09;
1559: out3 <= 12'hc0a;
1560: out3 <= 12'hc0b;
1561: out3 <= 12'hc0c;
1562: out3 <= 12'hc0d;
1563: out3 <= 12'hc0e;
1564: out3 <= 12'hc0f;
1565: out3 <= 12'hc10;
1566: out3 <= 12'hc11;
1567: out3 <= 12'hc12;
1568: out3 <= 12'hc14;
1569: out3 <= 12'hc15;
1570: out3 <= 12'hc16;
1571: out3 <= 12'hc18;
1572: out3 <= 12'hc19;
1573: out3 <= 12'hc1a;
1574: out3 <= 12'hc1c;
1575: out3 <= 12'hc1d;
1576: out3 <= 12'hc1f;
1577: out3 <= 12'hc20;
1578: out3 <= 12'hc22;
1579: out3 <= 12'hc23;
1580: out3 <= 12'hc25;
1581: out3 <= 12'hc27;
1582: out3 <= 12'hc29;
1583: out3 <= 12'hc2a;
1584: out3 <= 12'hc2c;
1585: out3 <= 12'hc2e;
1586: out3 <= 12'hc30;
1587: out3 <= 12'hc32;
1588: out3 <= 12'hc34;
1589: out3 <= 12'hc36;
1590: out3 <= 12'hc38;
1591: out3 <= 12'hc3a;
1592: out3 <= 12'hc3c;
1593: out3 <= 12'hc3e;
1594: out3 <= 12'hc40;
1595: out3 <= 12'hc42;
1596: out3 <= 12'hc45;
1597: out3 <= 12'hc47;
1598: out3 <= 12'hc49;
1599: out3 <= 12'hc4c;
1600: out3 <= 12'hc4e;
1601: out3 <= 12'hc50;
1602: out3 <= 12'hc53;
1603: out3 <= 12'hc55;
1604: out3 <= 12'hc58;
1605: out3 <= 12'hc5a;
1606: out3 <= 12'hc5d;
1607: out3 <= 12'hc60;
1608: out3 <= 12'hc62;
1609: out3 <= 12'hc65;
1610: out3 <= 12'hc68;
1611: out3 <= 12'hc6b;
1612: out3 <= 12'hc6d;
1613: out3 <= 12'hc70;
1614: out3 <= 12'hc73;
1615: out3 <= 12'hc76;
1616: out3 <= 12'hc79;
1617: out3 <= 12'hc7c;
1618: out3 <= 12'hc7f;
1619: out3 <= 12'hc82;
1620: out3 <= 12'hc85;
1621: out3 <= 12'hc88;
1622: out3 <= 12'hc8b;
1623: out3 <= 12'hc8e;
1624: out3 <= 12'hc92;
1625: out3 <= 12'hc95;
1626: out3 <= 12'hc98;
1627: out3 <= 12'hc9c;
1628: out3 <= 12'hc9f;
1629: out3 <= 12'hca2;
1630: out3 <= 12'hca6;
1631: out3 <= 12'hca9;
1632: out3 <= 12'hcad;
1633: out3 <= 12'hcb0;
1634: out3 <= 12'hcb4;
1635: out3 <= 12'hcb7;
1636: out3 <= 12'hcbb;
1637: out3 <= 12'hcbe;
1638: out3 <= 12'hcc2;
1639: out3 <= 12'hcc6;
1640: out3 <= 12'hcca;
1641: out3 <= 12'hccd;
1642: out3 <= 12'hcd1;
1643: out3 <= 12'hcd5;
1644: out3 <= 12'hcd9;
1645: out3 <= 12'hcdd;
1646: out3 <= 12'hce1;
1647: out3 <= 12'hce4;
1648: out3 <= 12'hce8;
1649: out3 <= 12'hcec;
1650: out3 <= 12'hcf0;
1651: out3 <= 12'hcf5;
1652: out3 <= 12'hcf9;
1653: out3 <= 12'hcfd;
1654: out3 <= 12'hd01;
1655: out3 <= 12'hd05;
1656: out3 <= 12'hd09;
1657: out3 <= 12'hd0d;
1658: out3 <= 12'hd12;
1659: out3 <= 12'hd16;
1660: out3 <= 12'hd1a;
1661: out3 <= 12'hd1f;
1662: out3 <= 12'hd23;
1663: out3 <= 12'hd27;
1664: out3 <= 12'hd2c;
1665: out3 <= 12'hd30;
1666: out3 <= 12'hd35;
1667: out3 <= 12'hd39;
1668: out3 <= 12'hd3e;
1669: out3 <= 12'hd42;
1670: out3 <= 12'hd47;
1671: out3 <= 12'hd4c;
1672: out3 <= 12'hd50;
1673: out3 <= 12'hd55;
1674: out3 <= 12'hd5a;
1675: out3 <= 12'hd5e;
1676: out3 <= 12'hd63;
1677: out3 <= 12'hd68;
1678: out3 <= 12'hd6d;
1679: out3 <= 12'hd72;
1680: out3 <= 12'hd76;
1681: out3 <= 12'hd7b;
1682: out3 <= 12'hd80;
1683: out3 <= 12'hd85;
1684: out3 <= 12'hd8a;
1685: out3 <= 12'hd8f;
1686: out3 <= 12'hd94;
1687: out3 <= 12'hd99;
1688: out3 <= 12'hd9e;
1689: out3 <= 12'hda3;
1690: out3 <= 12'hda8;
1691: out3 <= 12'hdad;
1692: out3 <= 12'hdb2;
1693: out3 <= 12'hdb8;
1694: out3 <= 12'hdbd;
1695: out3 <= 12'hdc2;
1696: out3 <= 12'hdc7;
1697: out3 <= 12'hdcc;
1698: out3 <= 12'hdd2;
1699: out3 <= 12'hdd7;
1700: out3 <= 12'hddc;
1701: out3 <= 12'hde1;
1702: out3 <= 12'hde7;
1703: out3 <= 12'hdec;
1704: out3 <= 12'hdf2;
1705: out3 <= 12'hdf7;
1706: out3 <= 12'hdfc;
1707: out3 <= 12'he02;
1708: out3 <= 12'he07;
1709: out3 <= 12'he0d;
1710: out3 <= 12'he12;
1711: out3 <= 12'he18;
1712: out3 <= 12'he1d;
1713: out3 <= 12'he23;
1714: out3 <= 12'he28;
1715: out3 <= 12'he2e;
1716: out3 <= 12'he34;
1717: out3 <= 12'he39;
1718: out3 <= 12'he3f;
1719: out3 <= 12'he45;
1720: out3 <= 12'he4a;
1721: out3 <= 12'he50;
1722: out3 <= 12'he56;
1723: out3 <= 12'he5b;
1724: out3 <= 12'he61;
1725: out3 <= 12'he67;
1726: out3 <= 12'he6d;
1727: out3 <= 12'he72;
1728: out3 <= 12'he78;
1729: out3 <= 12'he7e;
1730: out3 <= 12'he84;
1731: out3 <= 12'he8a;
1732: out3 <= 12'he8f;
1733: out3 <= 12'he95;
1734: out3 <= 12'he9b;
1735: out3 <= 12'hea1;
1736: out3 <= 12'hea7;
1737: out3 <= 12'head;
1738: out3 <= 12'heb3;
1739: out3 <= 12'heb9;
1740: out3 <= 12'hebf;
1741: out3 <= 12'hec5;
1742: out3 <= 12'hecb;
1743: out3 <= 12'hed1;
1744: out3 <= 12'hed7;
1745: out3 <= 12'hedd;
1746: out3 <= 12'hee3;
1747: out3 <= 12'hee9;
1748: out3 <= 12'heef;
1749: out3 <= 12'hef5;
1750: out3 <= 12'hefb;
1751: out3 <= 12'hf01;
1752: out3 <= 12'hf07;
1753: out3 <= 12'hf0d;
1754: out3 <= 12'hf13;
1755: out3 <= 12'hf1a;
1756: out3 <= 12'hf20;
1757: out3 <= 12'hf26;
1758: out3 <= 12'hf2c;
1759: out3 <= 12'hf32;
1760: out3 <= 12'hf38;
1761: out3 <= 12'hf3e;
1762: out3 <= 12'hf45;
1763: out3 <= 12'hf4b;
1764: out3 <= 12'hf51;
1765: out3 <= 12'hf57;
1766: out3 <= 12'hf5d;
1767: out3 <= 12'hf64;
1768: out3 <= 12'hf6a;
1769: out3 <= 12'hf70;
1770: out3 <= 12'hf76;
1771: out3 <= 12'hf7c;
1772: out3 <= 12'hf83;
1773: out3 <= 12'hf89;
1774: out3 <= 12'hf8f;
1775: out3 <= 12'hf95;
1776: out3 <= 12'hf9c;
1777: out3 <= 12'hfa2;
1778: out3 <= 12'hfa8;
1779: out3 <= 12'hfae;
1780: out3 <= 12'hfb5;
1781: out3 <= 12'hfbb;
1782: out3 <= 12'hfc1;
1783: out3 <= 12'hfc7;
1784: out3 <= 12'hfce;
1785: out3 <= 12'hfd4;
1786: out3 <= 12'hfda;
1787: out3 <= 12'hfe1;
1788: out3 <= 12'hfe7;
1789: out3 <= 12'hfed;
1790: out3 <= 12'hff3;
1791: out3 <= 12'hffa;
1792: out3 <= 12'h0;
1793: out3 <= 12'h6;
1794: out3 <= 12'hd;
1795: out3 <= 12'h13;
1796: out3 <= 12'h19;
1797: out3 <= 12'h1f;
1798: out3 <= 12'h26;
1799: out3 <= 12'h2c;
1800: out3 <= 12'h32;
1801: out3 <= 12'h39;
1802: out3 <= 12'h3f;
1803: out3 <= 12'h45;
1804: out3 <= 12'h4b;
1805: out3 <= 12'h52;
1806: out3 <= 12'h58;
1807: out3 <= 12'h5e;
1808: out3 <= 12'h64;
1809: out3 <= 12'h6b;
1810: out3 <= 12'h71;
1811: out3 <= 12'h77;
1812: out3 <= 12'h7d;
1813: out3 <= 12'h84;
1814: out3 <= 12'h8a;
1815: out3 <= 12'h90;
1816: out3 <= 12'h96;
1817: out3 <= 12'h9c;
1818: out3 <= 12'ha3;
1819: out3 <= 12'ha9;
1820: out3 <= 12'haf;
1821: out3 <= 12'hb5;
1822: out3 <= 12'hbb;
1823: out3 <= 12'hc2;
1824: out3 <= 12'hc8;
1825: out3 <= 12'hce;
1826: out3 <= 12'hd4;
1827: out3 <= 12'hda;
1828: out3 <= 12'he0;
1829: out3 <= 12'he6;
1830: out3 <= 12'hed;
1831: out3 <= 12'hf3;
1832: out3 <= 12'hf9;
1833: out3 <= 12'hff;
1834: out3 <= 12'h105;
1835: out3 <= 12'h10b;
1836: out3 <= 12'h111;
1837: out3 <= 12'h117;
1838: out3 <= 12'h11d;
1839: out3 <= 12'h123;
1840: out3 <= 12'h129;
1841: out3 <= 12'h12f;
1842: out3 <= 12'h135;
1843: out3 <= 12'h13b;
1844: out3 <= 12'h141;
1845: out3 <= 12'h147;
1846: out3 <= 12'h14d;
1847: out3 <= 12'h153;
1848: out3 <= 12'h159;
1849: out3 <= 12'h15f;
1850: out3 <= 12'h165;
1851: out3 <= 12'h16b;
1852: out3 <= 12'h171;
1853: out3 <= 12'h176;
1854: out3 <= 12'h17c;
1855: out3 <= 12'h182;
1856: out3 <= 12'h188;
1857: out3 <= 12'h18e;
1858: out3 <= 12'h193;
1859: out3 <= 12'h199;
1860: out3 <= 12'h19f;
1861: out3 <= 12'h1a5;
1862: out3 <= 12'h1aa;
1863: out3 <= 12'h1b0;
1864: out3 <= 12'h1b6;
1865: out3 <= 12'h1bb;
1866: out3 <= 12'h1c1;
1867: out3 <= 12'h1c7;
1868: out3 <= 12'h1cc;
1869: out3 <= 12'h1d2;
1870: out3 <= 12'h1d8;
1871: out3 <= 12'h1dd;
1872: out3 <= 12'h1e3;
1873: out3 <= 12'h1e8;
1874: out3 <= 12'h1ee;
1875: out3 <= 12'h1f3;
1876: out3 <= 12'h1f9;
1877: out3 <= 12'h1fe;
1878: out3 <= 12'h204;
1879: out3 <= 12'h209;
1880: out3 <= 12'h20e;
1881: out3 <= 12'h214;
1882: out3 <= 12'h219;
1883: out3 <= 12'h21f;
1884: out3 <= 12'h224;
1885: out3 <= 12'h229;
1886: out3 <= 12'h22e;
1887: out3 <= 12'h234;
1888: out3 <= 12'h239;
1889: out3 <= 12'h23e;
1890: out3 <= 12'h243;
1891: out3 <= 12'h248;
1892: out3 <= 12'h24e;
1893: out3 <= 12'h253;
1894: out3 <= 12'h258;
1895: out3 <= 12'h25d;
1896: out3 <= 12'h262;
1897: out3 <= 12'h267;
1898: out3 <= 12'h26c;
1899: out3 <= 12'h271;
1900: out3 <= 12'h276;
1901: out3 <= 12'h27b;
1902: out3 <= 12'h280;
1903: out3 <= 12'h285;
1904: out3 <= 12'h28a;
1905: out3 <= 12'h28e;
1906: out3 <= 12'h293;
1907: out3 <= 12'h298;
1908: out3 <= 12'h29d;
1909: out3 <= 12'h2a2;
1910: out3 <= 12'h2a6;
1911: out3 <= 12'h2ab;
1912: out3 <= 12'h2b0;
1913: out3 <= 12'h2b4;
1914: out3 <= 12'h2b9;
1915: out3 <= 12'h2be;
1916: out3 <= 12'h2c2;
1917: out3 <= 12'h2c7;
1918: out3 <= 12'h2cb;
1919: out3 <= 12'h2d0;
1920: out3 <= 12'h2d4;
1921: out3 <= 12'h2d9;
1922: out3 <= 12'h2dd;
1923: out3 <= 12'h2e1;
1924: out3 <= 12'h2e6;
1925: out3 <= 12'h2ea;
1926: out3 <= 12'h2ee;
1927: out3 <= 12'h2f3;
1928: out3 <= 12'h2f7;
1929: out3 <= 12'h2fb;
1930: out3 <= 12'h2ff;
1931: out3 <= 12'h303;
1932: out3 <= 12'h307;
1933: out3 <= 12'h30b;
1934: out3 <= 12'h310;
1935: out3 <= 12'h314;
1936: out3 <= 12'h318;
1937: out3 <= 12'h31c;
1938: out3 <= 12'h31f;
1939: out3 <= 12'h323;
1940: out3 <= 12'h327;
1941: out3 <= 12'h32b;
1942: out3 <= 12'h32f;
1943: out3 <= 12'h333;
1944: out3 <= 12'h336;
1945: out3 <= 12'h33a;
1946: out3 <= 12'h33e;
1947: out3 <= 12'h342;
1948: out3 <= 12'h345;
1949: out3 <= 12'h349;
1950: out3 <= 12'h34c;
1951: out3 <= 12'h350;
1952: out3 <= 12'h353;
1953: out3 <= 12'h357;
1954: out3 <= 12'h35a;
1955: out3 <= 12'h35e;
1956: out3 <= 12'h361;
1957: out3 <= 12'h364;
1958: out3 <= 12'h368;
1959: out3 <= 12'h36b;
1960: out3 <= 12'h36e;
1961: out3 <= 12'h372;
1962: out3 <= 12'h375;
1963: out3 <= 12'h378;
1964: out3 <= 12'h37b;
1965: out3 <= 12'h37e;
1966: out3 <= 12'h381;
1967: out3 <= 12'h384;
1968: out3 <= 12'h387;
1969: out3 <= 12'h38a;
1970: out3 <= 12'h38d;
1971: out3 <= 12'h390;
1972: out3 <= 12'h393;
1973: out3 <= 12'h395;
1974: out3 <= 12'h398;
1975: out3 <= 12'h39b;
1976: out3 <= 12'h39e;
1977: out3 <= 12'h3a0;
1978: out3 <= 12'h3a3;
1979: out3 <= 12'h3a6;
1980: out3 <= 12'h3a8;
1981: out3 <= 12'h3ab;
1982: out3 <= 12'h3ad;
1983: out3 <= 12'h3b0;
1984: out3 <= 12'h3b2;
1985: out3 <= 12'h3b4;
1986: out3 <= 12'h3b7;
1987: out3 <= 12'h3b9;
1988: out3 <= 12'h3bb;
1989: out3 <= 12'h3be;
1990: out3 <= 12'h3c0;
1991: out3 <= 12'h3c2;
1992: out3 <= 12'h3c4;
1993: out3 <= 12'h3c6;
1994: out3 <= 12'h3c8;
1995: out3 <= 12'h3ca;
1996: out3 <= 12'h3cc;
1997: out3 <= 12'h3ce;
1998: out3 <= 12'h3d0;
1999: out3 <= 12'h3d2;
2000: out3 <= 12'h3d4;
2001: out3 <= 12'h3d6;
2002: out3 <= 12'h3d7;
2003: out3 <= 12'h3d9;
2004: out3 <= 12'h3db;
2005: out3 <= 12'h3dd;
2006: out3 <= 12'h3de;
2007: out3 <= 12'h3e0;
2008: out3 <= 12'h3e1;
2009: out3 <= 12'h3e3;
2010: out3 <= 12'h3e4;
2011: out3 <= 12'h3e6;
2012: out3 <= 12'h3e7;
2013: out3 <= 12'h3e8;
2014: out3 <= 12'h3ea;
2015: out3 <= 12'h3eb;
2016: out3 <= 12'h3ec;
2017: out3 <= 12'h3ee;
2018: out3 <= 12'h3ef;
2019: out3 <= 12'h3f0;
2020: out3 <= 12'h3f1;
2021: out3 <= 12'h3f2;
2022: out3 <= 12'h3f3;
2023: out3 <= 12'h3f4;
2024: out3 <= 12'h3f5;
2025: out3 <= 12'h3f6;
2026: out3 <= 12'h3f7;
2027: out3 <= 12'h3f8;
2028: out3 <= 12'h3f8;
2029: out3 <= 12'h3f9;
2030: out3 <= 12'h3fa;
2031: out3 <= 12'h3fa;
2032: out3 <= 12'h3fb;
2033: out3 <= 12'h3fc;
2034: out3 <= 12'h3fc;
2035: out3 <= 12'h3fd;
2036: out3 <= 12'h3fd;
2037: out3 <= 12'h3fe;
2038: out3 <= 12'h3fe;
2039: out3 <= 12'h3fe;
2040: out3 <= 12'h3ff;
2041: out3 <= 12'h3ff;
2042: out3 <= 12'h3ff;
2043: out3 <= 12'h400;
2044: out3 <= 12'h400;
2045: out3 <= 12'h400;
2046: out3 <= 12'h400;
2047: out3 <= 12'h400;
default: out3 <= 0;
endcase
end
// synthesis attribute rom_style of out3 is "block"
endmodule |
module D2_46012(addr, out, clk);
input clk;
output [11:0] out;
reg [11:0] out, out2, out3;
input [10:0] addr;
always @(posedge clk) begin
out2 <= out3;
out <= out2;
case(addr)
0: out3 <= 12'h0;
1: out3 <= 12'hffd;
2: out3 <= 12'hffa;
3: out3 <= 12'hff7;
4: out3 <= 12'hff3;
5: out3 <= 12'hff0;
6: out3 <= 12'hfed;
7: out3 <= 12'hfea;
8: out3 <= 12'hfe7;
9: out3 <= 12'hfe4;
10: out3 <= 12'hfe1;
11: out3 <= 12'hfdd;
12: out3 <= 12'hfda;
13: out3 <= 12'hfd7;
14: out3 <= 12'hfd4;
15: out3 <= 12'hfd1;
16: out3 <= 12'hfce;
17: out3 <= 12'hfcb;
18: out3 <= 12'hfc7;
19: out3 <= 12'hfc4;
20: out3 <= 12'hfc1;
21: out3 <= 12'hfbe;
22: out3 <= 12'hfbb;
23: out3 <= 12'hfb8;
24: out3 <= 12'hfb5;
25: out3 <= 12'hfb2;
26: out3 <= 12'hfae;
27: out3 <= 12'hfab;
28: out3 <= 12'hfa8;
29: out3 <= 12'hfa5;
30: out3 <= 12'hfa2;
31: out3 <= 12'hf9f;
32: out3 <= 12'hf9c;
33: out3 <= 12'hf99;
34: out3 <= 12'hf95;
35: out3 <= 12'hf92;
36: out3 <= 12'hf8f;
37: out3 <= 12'hf8c;
38: out3 <= 12'hf89;
39: out3 <= 12'hf86;
40: out3 <= 12'hf83;
41: out3 <= 12'hf80;
42: out3 <= 12'hf7c;
43: out3 <= 12'hf79;
44: out3 <= 12'hf76;
45: out3 <= 12'hf73;
46: out3 <= 12'hf70;
47: out3 <= 12'hf6d;
48: out3 <= 12'hf6a;
49: out3 <= 12'hf67;
50: out3 <= 12'hf64;
51: out3 <= 12'hf60;
52: out3 <= 12'hf5d;
53: out3 <= 12'hf5a;
54: out3 <= 12'hf57;
55: out3 <= 12'hf54;
56: out3 <= 12'hf51;
57: out3 <= 12'hf4e;
58: out3 <= 12'hf4b;
59: out3 <= 12'hf48;
60: out3 <= 12'hf45;
61: out3 <= 12'hf41;
62: out3 <= 12'hf3e;
63: out3 <= 12'hf3b;
64: out3 <= 12'hf38;
65: out3 <= 12'hf35;
66: out3 <= 12'hf32;
67: out3 <= 12'hf2f;
68: out3 <= 12'hf2c;
69: out3 <= 12'hf29;
70: out3 <= 12'hf26;
71: out3 <= 12'hf23;
72: out3 <= 12'hf20;
73: out3 <= 12'hf1d;
74: out3 <= 12'hf1a;
75: out3 <= 12'hf16;
76: out3 <= 12'hf13;
77: out3 <= 12'hf10;
78: out3 <= 12'hf0d;
79: out3 <= 12'hf0a;
80: out3 <= 12'hf07;
81: out3 <= 12'hf04;
82: out3 <= 12'hf01;
83: out3 <= 12'hefe;
84: out3 <= 12'hefb;
85: out3 <= 12'hef8;
86: out3 <= 12'hef5;
87: out3 <= 12'hef2;
88: out3 <= 12'heef;
89: out3 <= 12'heec;
90: out3 <= 12'hee9;
91: out3 <= 12'hee6;
92: out3 <= 12'hee3;
93: out3 <= 12'hee0;
94: out3 <= 12'hedd;
95: out3 <= 12'heda;
96: out3 <= 12'hed7;
97: out3 <= 12'hed4;
98: out3 <= 12'hed1;
99: out3 <= 12'hece;
100: out3 <= 12'hecb;
101: out3 <= 12'hec8;
102: out3 <= 12'hec5;
103: out3 <= 12'hec2;
104: out3 <= 12'hebf;
105: out3 <= 12'hebc;
106: out3 <= 12'heb9;
107: out3 <= 12'heb6;
108: out3 <= 12'heb3;
109: out3 <= 12'heb0;
110: out3 <= 12'head;
111: out3 <= 12'heaa;
112: out3 <= 12'hea7;
113: out3 <= 12'hea4;
114: out3 <= 12'hea1;
115: out3 <= 12'he9e;
116: out3 <= 12'he9b;
117: out3 <= 12'he98;
118: out3 <= 12'he95;
119: out3 <= 12'he92;
120: out3 <= 12'he8f;
121: out3 <= 12'he8d;
122: out3 <= 12'he8a;
123: out3 <= 12'he87;
124: out3 <= 12'he84;
125: out3 <= 12'he81;
126: out3 <= 12'he7e;
127: out3 <= 12'he7b;
128: out3 <= 12'he78;
129: out3 <= 12'he75;
130: out3 <= 12'he72;
131: out3 <= 12'he6f;
132: out3 <= 12'he6d;
133: out3 <= 12'he6a;
134: out3 <= 12'he67;
135: out3 <= 12'he64;
136: out3 <= 12'he61;
137: out3 <= 12'he5e;
138: out3 <= 12'he5b;
139: out3 <= 12'he58;
140: out3 <= 12'he56;
141: out3 <= 12'he53;
142: out3 <= 12'he50;
143: out3 <= 12'he4d;
144: out3 <= 12'he4a;
145: out3 <= 12'he47;
146: out3 <= 12'he45;
147: out3 <= 12'he42;
148: out3 <= 12'he3f;
149: out3 <= 12'he3c;
150: out3 <= 12'he39;
151: out3 <= 12'he36;
152: out3 <= 12'he34;
153: out3 <= 12'he31;
154: out3 <= 12'he2e;
155: out3 <= 12'he2b;
156: out3 <= 12'he28;
157: out3 <= 12'he26;
158: out3 <= 12'he23;
159: out3 <= 12'he20;
160: out3 <= 12'he1d;
161: out3 <= 12'he1b;
162: out3 <= 12'he18;
163: out3 <= 12'he15;
164: out3 <= 12'he12;
165: out3 <= 12'he0f;
166: out3 <= 12'he0d;
167: out3 <= 12'he0a;
168: out3 <= 12'he07;
169: out3 <= 12'he05;
170: out3 <= 12'he02;
171: out3 <= 12'hdff;
172: out3 <= 12'hdfc;
173: out3 <= 12'hdfa;
174: out3 <= 12'hdf7;
175: out3 <= 12'hdf4;
176: out3 <= 12'hdf2;
177: out3 <= 12'hdef;
178: out3 <= 12'hdec;
179: out3 <= 12'hde9;
180: out3 <= 12'hde7;
181: out3 <= 12'hde4;
182: out3 <= 12'hde1;
183: out3 <= 12'hddf;
184: out3 <= 12'hddc;
185: out3 <= 12'hdda;
186: out3 <= 12'hdd7;
187: out3 <= 12'hdd4;
188: out3 <= 12'hdd2;
189: out3 <= 12'hdcf;
190: out3 <= 12'hdcc;
191: out3 <= 12'hdca;
192: out3 <= 12'hdc7;
193: out3 <= 12'hdc4;
194: out3 <= 12'hdc2;
195: out3 <= 12'hdbf;
196: out3 <= 12'hdbd;
197: out3 <= 12'hdba;
198: out3 <= 12'hdb8;
199: out3 <= 12'hdb5;
200: out3 <= 12'hdb2;
201: out3 <= 12'hdb0;
202: out3 <= 12'hdad;
203: out3 <= 12'hdab;
204: out3 <= 12'hda8;
205: out3 <= 12'hda6;
206: out3 <= 12'hda3;
207: out3 <= 12'hda1;
208: out3 <= 12'hd9e;
209: out3 <= 12'hd9b;
210: out3 <= 12'hd99;
211: out3 <= 12'hd96;
212: out3 <= 12'hd94;
213: out3 <= 12'hd91;
214: out3 <= 12'hd8f;
215: out3 <= 12'hd8c;
216: out3 <= 12'hd8a;
217: out3 <= 12'hd88;
218: out3 <= 12'hd85;
219: out3 <= 12'hd83;
220: out3 <= 12'hd80;
221: out3 <= 12'hd7e;
222: out3 <= 12'hd7b;
223: out3 <= 12'hd79;
224: out3 <= 12'hd76;
225: out3 <= 12'hd74;
226: out3 <= 12'hd72;
227: out3 <= 12'hd6f;
228: out3 <= 12'hd6d;
229: out3 <= 12'hd6a;
230: out3 <= 12'hd68;
231: out3 <= 12'hd66;
232: out3 <= 12'hd63;
233: out3 <= 12'hd61;
234: out3 <= 12'hd5e;
235: out3 <= 12'hd5c;
236: out3 <= 12'hd5a;
237: out3 <= 12'hd57;
238: out3 <= 12'hd55;
239: out3 <= 12'hd53;
240: out3 <= 12'hd50;
241: out3 <= 12'hd4e;
242: out3 <= 12'hd4c;
243: out3 <= 12'hd49;
244: out3 <= 12'hd47;
245: out3 <= 12'hd45;
246: out3 <= 12'hd42;
247: out3 <= 12'hd40;
248: out3 <= 12'hd3e;
249: out3 <= 12'hd3c;
250: out3 <= 12'hd39;
251: out3 <= 12'hd37;
252: out3 <= 12'hd35;
253: out3 <= 12'hd33;
254: out3 <= 12'hd30;
255: out3 <= 12'hd2e;
256: out3 <= 12'hd2c;
257: out3 <= 12'hd2a;
258: out3 <= 12'hd27;
259: out3 <= 12'hd25;
260: out3 <= 12'hd23;
261: out3 <= 12'hd21;
262: out3 <= 12'hd1f;
263: out3 <= 12'hd1d;
264: out3 <= 12'hd1a;
265: out3 <= 12'hd18;
266: out3 <= 12'hd16;
267: out3 <= 12'hd14;
268: out3 <= 12'hd12;
269: out3 <= 12'hd10;
270: out3 <= 12'hd0d;
271: out3 <= 12'hd0b;
272: out3 <= 12'hd09;
273: out3 <= 12'hd07;
274: out3 <= 12'hd05;
275: out3 <= 12'hd03;
276: out3 <= 12'hd01;
277: out3 <= 12'hcff;
278: out3 <= 12'hcfd;
279: out3 <= 12'hcfb;
280: out3 <= 12'hcf9;
281: out3 <= 12'hcf7;
282: out3 <= 12'hcf5;
283: out3 <= 12'hcf2;
284: out3 <= 12'hcf0;
285: out3 <= 12'hcee;
286: out3 <= 12'hcec;
287: out3 <= 12'hcea;
288: out3 <= 12'hce8;
289: out3 <= 12'hce6;
290: out3 <= 12'hce4;
291: out3 <= 12'hce2;
292: out3 <= 12'hce1;
293: out3 <= 12'hcdf;
294: out3 <= 12'hcdd;
295: out3 <= 12'hcdb;
296: out3 <= 12'hcd9;
297: out3 <= 12'hcd7;
298: out3 <= 12'hcd5;
299: out3 <= 12'hcd3;
300: out3 <= 12'hcd1;
301: out3 <= 12'hccf;
302: out3 <= 12'hccd;
303: out3 <= 12'hccb;
304: out3 <= 12'hcca;
305: out3 <= 12'hcc8;
306: out3 <= 12'hcc6;
307: out3 <= 12'hcc4;
308: out3 <= 12'hcc2;
309: out3 <= 12'hcc0;
310: out3 <= 12'hcbe;
311: out3 <= 12'hcbd;
312: out3 <= 12'hcbb;
313: out3 <= 12'hcb9;
314: out3 <= 12'hcb7;
315: out3 <= 12'hcb5;
316: out3 <= 12'hcb4;
317: out3 <= 12'hcb2;
318: out3 <= 12'hcb0;
319: out3 <= 12'hcae;
320: out3 <= 12'hcad;
321: out3 <= 12'hcab;
322: out3 <= 12'hca9;
323: out3 <= 12'hca7;
324: out3 <= 12'hca6;
325: out3 <= 12'hca4;
326: out3 <= 12'hca2;
327: out3 <= 12'hca1;
328: out3 <= 12'hc9f;
329: out3 <= 12'hc9d;
330: out3 <= 12'hc9c;
331: out3 <= 12'hc9a;
332: out3 <= 12'hc98;
333: out3 <= 12'hc97;
334: out3 <= 12'hc95;
335: out3 <= 12'hc93;
336: out3 <= 12'hc92;
337: out3 <= 12'hc90;
338: out3 <= 12'hc8e;
339: out3 <= 12'hc8d;
340: out3 <= 12'hc8b;
341: out3 <= 12'hc8a;
342: out3 <= 12'hc88;
343: out3 <= 12'hc87;
344: out3 <= 12'hc85;
345: out3 <= 12'hc83;
346: out3 <= 12'hc82;
347: out3 <= 12'hc80;
348: out3 <= 12'hc7f;
349: out3 <= 12'hc7d;
350: out3 <= 12'hc7c;
351: out3 <= 12'hc7a;
352: out3 <= 12'hc79;
353: out3 <= 12'hc77;
354: out3 <= 12'hc76;
355: out3 <= 12'hc75;
356: out3 <= 12'hc73;
357: out3 <= 12'hc72;
358: out3 <= 12'hc70;
359: out3 <= 12'hc6f;
360: out3 <= 12'hc6d;
361: out3 <= 12'hc6c;
362: out3 <= 12'hc6b;
363: out3 <= 12'hc69;
364: out3 <= 12'hc68;
365: out3 <= 12'hc66;
366: out3 <= 12'hc65;
367: out3 <= 12'hc64;
368: out3 <= 12'hc62;
369: out3 <= 12'hc61;
370: out3 <= 12'hc60;
371: out3 <= 12'hc5e;
372: out3 <= 12'hc5d;
373: out3 <= 12'hc5c;
374: out3 <= 12'hc5a;
375: out3 <= 12'hc59;
376: out3 <= 12'hc58;
377: out3 <= 12'hc57;
378: out3 <= 12'hc55;
379: out3 <= 12'hc54;
380: out3 <= 12'hc53;
381: out3 <= 12'hc52;
382: out3 <= 12'hc50;
383: out3 <= 12'hc4f;
384: out3 <= 12'hc4e;
385: out3 <= 12'hc4d;
386: out3 <= 12'hc4c;
387: out3 <= 12'hc4a;
388: out3 <= 12'hc49;
389: out3 <= 12'hc48;
390: out3 <= 12'hc47;
391: out3 <= 12'hc46;
392: out3 <= 12'hc45;
393: out3 <= 12'hc43;
394: out3 <= 12'hc42;
395: out3 <= 12'hc41;
396: out3 <= 12'hc40;
397: out3 <= 12'hc3f;
398: out3 <= 12'hc3e;
399: out3 <= 12'hc3d;
400: out3 <= 12'hc3c;
401: out3 <= 12'hc3b;
402: out3 <= 12'hc3a;
403: out3 <= 12'hc39;
404: out3 <= 12'hc38;
405: out3 <= 12'hc37;
406: out3 <= 12'hc36;
407: out3 <= 12'hc35;
408: out3 <= 12'hc34;
409: out3 <= 12'hc33;
410: out3 <= 12'hc32;
411: out3 <= 12'hc31;
412: out3 <= 12'hc30;
413: out3 <= 12'hc2f;
414: out3 <= 12'hc2e;
415: out3 <= 12'hc2d;
416: out3 <= 12'hc2c;
417: out3 <= 12'hc2b;
418: out3 <= 12'hc2a;
419: out3 <= 12'hc29;
420: out3 <= 12'hc29;
421: out3 <= 12'hc28;
422: out3 <= 12'hc27;
423: out3 <= 12'hc26;
424: out3 <= 12'hc25;
425: out3 <= 12'hc24;
426: out3 <= 12'hc23;
427: out3 <= 12'hc23;
428: out3 <= 12'hc22;
429: out3 <= 12'hc21;
430: out3 <= 12'hc20;
431: out3 <= 12'hc1f;
432: out3 <= 12'hc1f;
433: out3 <= 12'hc1e;
434: out3 <= 12'hc1d;
435: out3 <= 12'hc1c;
436: out3 <= 12'hc1c;
437: out3 <= 12'hc1b;
438: out3 <= 12'hc1a;
439: out3 <= 12'hc1a;
440: out3 <= 12'hc19;
441: out3 <= 12'hc18;
442: out3 <= 12'hc18;
443: out3 <= 12'hc17;
444: out3 <= 12'hc16;
445: out3 <= 12'hc16;
446: out3 <= 12'hc15;
447: out3 <= 12'hc14;
448: out3 <= 12'hc14;
449: out3 <= 12'hc13;
450: out3 <= 12'hc12;
451: out3 <= 12'hc12;
452: out3 <= 12'hc11;
453: out3 <= 12'hc11;
454: out3 <= 12'hc10;
455: out3 <= 12'hc10;
456: out3 <= 12'hc0f;
457: out3 <= 12'hc0f;
458: out3 <= 12'hc0e;
459: out3 <= 12'hc0e;
460: out3 <= 12'hc0d;
461: out3 <= 12'hc0d;
462: out3 <= 12'hc0c;
463: out3 <= 12'hc0c;
464: out3 <= 12'hc0b;
465: out3 <= 12'hc0b;
466: out3 <= 12'hc0a;
467: out3 <= 12'hc0a;
468: out3 <= 12'hc09;
469: out3 <= 12'hc09;
470: out3 <= 12'hc08;
471: out3 <= 12'hc08;
472: out3 <= 12'hc08;
473: out3 <= 12'hc07;
474: out3 <= 12'hc07;
475: out3 <= 12'hc07;
476: out3 <= 12'hc06;
477: out3 <= 12'hc06;
478: out3 <= 12'hc06;
479: out3 <= 12'hc05;
480: out3 <= 12'hc05;
481: out3 <= 12'hc05;
482: out3 <= 12'hc04;
483: out3 <= 12'hc04;
484: out3 <= 12'hc04;
485: out3 <= 12'hc04;
486: out3 <= 12'hc03;
487: out3 <= 12'hc03;
488: out3 <= 12'hc03;
489: out3 <= 12'hc03;
490: out3 <= 12'hc02;
491: out3 <= 12'hc02;
492: out3 <= 12'hc02;
493: out3 <= 12'hc02;
494: out3 <= 12'hc02;
495: out3 <= 12'hc01;
496: out3 <= 12'hc01;
497: out3 <= 12'hc01;
498: out3 <= 12'hc01;
499: out3 <= 12'hc01;
500: out3 <= 12'hc01;
501: out3 <= 12'hc01;
502: out3 <= 12'hc00;
503: out3 <= 12'hc00;
504: out3 <= 12'hc00;
505: out3 <= 12'hc00;
506: out3 <= 12'hc00;
507: out3 <= 12'hc00;
508: out3 <= 12'hc00;
509: out3 <= 12'hc00;
510: out3 <= 12'hc00;
511: out3 <= 12'hc00;
512: out3 <= 12'hc00;
513: out3 <= 12'hc00;
514: out3 <= 12'hc00;
515: out3 <= 12'hc00;
516: out3 <= 12'hc00;
517: out3 <= 12'hc00;
518: out3 <= 12'hc00;
519: out3 <= 12'hc00;
520: out3 <= 12'hc00;
521: out3 <= 12'hc00;
522: out3 <= 12'hc00;
523: out3 <= 12'hc01;
524: out3 <= 12'hc01;
525: out3 <= 12'hc01;
526: out3 <= 12'hc01;
527: out3 <= 12'hc01;
528: out3 <= 12'hc01;
529: out3 <= 12'hc01;
530: out3 <= 12'hc02;
531: out3 <= 12'hc02;
532: out3 <= 12'hc02;
533: out3 <= 12'hc02;
534: out3 <= 12'hc02;
535: out3 <= 12'hc03;
536: out3 <= 12'hc03;
537: out3 <= 12'hc03;
538: out3 <= 12'hc03;
539: out3 <= 12'hc04;
540: out3 <= 12'hc04;
541: out3 <= 12'hc04;
542: out3 <= 12'hc04;
543: out3 <= 12'hc05;
544: out3 <= 12'hc05;
545: out3 <= 12'hc05;
546: out3 <= 12'hc06;
547: out3 <= 12'hc06;
548: out3 <= 12'hc06;
549: out3 <= 12'hc07;
550: out3 <= 12'hc07;
551: out3 <= 12'hc07;
552: out3 <= 12'hc08;
553: out3 <= 12'hc08;
554: out3 <= 12'hc08;
555: out3 <= 12'hc09;
556: out3 <= 12'hc09;
557: out3 <= 12'hc0a;
558: out3 <= 12'hc0a;
559: out3 <= 12'hc0b;
560: out3 <= 12'hc0b;
561: out3 <= 12'hc0c;
562: out3 <= 12'hc0c;
563: out3 <= 12'hc0d;
564: out3 <= 12'hc0d;
565: out3 <= 12'hc0e;
566: out3 <= 12'hc0e;
567: out3 <= 12'hc0f;
568: out3 <= 12'hc0f;
569: out3 <= 12'hc10;
570: out3 <= 12'hc10;
571: out3 <= 12'hc11;
572: out3 <= 12'hc11;
573: out3 <= 12'hc12;
574: out3 <= 12'hc12;
575: out3 <= 12'hc13;
576: out3 <= 12'hc14;
577: out3 <= 12'hc14;
578: out3 <= 12'hc15;
579: out3 <= 12'hc16;
580: out3 <= 12'hc16;
581: out3 <= 12'hc17;
582: out3 <= 12'hc18;
583: out3 <= 12'hc18;
584: out3 <= 12'hc19;
585: out3 <= 12'hc1a;
586: out3 <= 12'hc1a;
587: out3 <= 12'hc1b;
588: out3 <= 12'hc1c;
589: out3 <= 12'hc1c;
590: out3 <= 12'hc1d;
591: out3 <= 12'hc1e;
592: out3 <= 12'hc1f;
593: out3 <= 12'hc1f;
594: out3 <= 12'hc20;
595: out3 <= 12'hc21;
596: out3 <= 12'hc22;
597: out3 <= 12'hc23;
598: out3 <= 12'hc23;
599: out3 <= 12'hc24;
600: out3 <= 12'hc25;
601: out3 <= 12'hc26;
602: out3 <= 12'hc27;
603: out3 <= 12'hc28;
604: out3 <= 12'hc29;
605: out3 <= 12'hc29;
606: out3 <= 12'hc2a;
607: out3 <= 12'hc2b;
608: out3 <= 12'hc2c;
609: out3 <= 12'hc2d;
610: out3 <= 12'hc2e;
611: out3 <= 12'hc2f;
612: out3 <= 12'hc30;
613: out3 <= 12'hc31;
614: out3 <= 12'hc32;
615: out3 <= 12'hc33;
616: out3 <= 12'hc34;
617: out3 <= 12'hc35;
618: out3 <= 12'hc36;
619: out3 <= 12'hc37;
620: out3 <= 12'hc38;
621: out3 <= 12'hc39;
622: out3 <= 12'hc3a;
623: out3 <= 12'hc3b;
624: out3 <= 12'hc3c;
625: out3 <= 12'hc3d;
626: out3 <= 12'hc3e;
627: out3 <= 12'hc3f;
628: out3 <= 12'hc40;
629: out3 <= 12'hc41;
630: out3 <= 12'hc42;
631: out3 <= 12'hc43;
632: out3 <= 12'hc45;
633: out3 <= 12'hc46;
634: out3 <= 12'hc47;
635: out3 <= 12'hc48;
636: out3 <= 12'hc49;
637: out3 <= 12'hc4a;
638: out3 <= 12'hc4c;
639: out3 <= 12'hc4d;
640: out3 <= 12'hc4e;
641: out3 <= 12'hc4f;
642: out3 <= 12'hc50;
643: out3 <= 12'hc52;
644: out3 <= 12'hc53;
645: out3 <= 12'hc54;
646: out3 <= 12'hc55;
647: out3 <= 12'hc57;
648: out3 <= 12'hc58;
649: out3 <= 12'hc59;
650: out3 <= 12'hc5a;
651: out3 <= 12'hc5c;
652: out3 <= 12'hc5d;
653: out3 <= 12'hc5e;
654: out3 <= 12'hc60;
655: out3 <= 12'hc61;
656: out3 <= 12'hc62;
657: out3 <= 12'hc64;
658: out3 <= 12'hc65;
659: out3 <= 12'hc66;
660: out3 <= 12'hc68;
661: out3 <= 12'hc69;
662: out3 <= 12'hc6b;
663: out3 <= 12'hc6c;
664: out3 <= 12'hc6d;
665: out3 <= 12'hc6f;
666: out3 <= 12'hc70;
667: out3 <= 12'hc72;
668: out3 <= 12'hc73;
669: out3 <= 12'hc75;
670: out3 <= 12'hc76;
671: out3 <= 12'hc77;
672: out3 <= 12'hc79;
673: out3 <= 12'hc7a;
674: out3 <= 12'hc7c;
675: out3 <= 12'hc7d;
676: out3 <= 12'hc7f;
677: out3 <= 12'hc80;
678: out3 <= 12'hc82;
679: out3 <= 12'hc83;
680: out3 <= 12'hc85;
681: out3 <= 12'hc87;
682: out3 <= 12'hc88;
683: out3 <= 12'hc8a;
684: out3 <= 12'hc8b;
685: out3 <= 12'hc8d;
686: out3 <= 12'hc8e;
687: out3 <= 12'hc90;
688: out3 <= 12'hc92;
689: out3 <= 12'hc93;
690: out3 <= 12'hc95;
691: out3 <= 12'hc97;
692: out3 <= 12'hc98;
693: out3 <= 12'hc9a;
694: out3 <= 12'hc9c;
695: out3 <= 12'hc9d;
696: out3 <= 12'hc9f;
697: out3 <= 12'hca1;
698: out3 <= 12'hca2;
699: out3 <= 12'hca4;
700: out3 <= 12'hca6;
701: out3 <= 12'hca7;
702: out3 <= 12'hca9;
703: out3 <= 12'hcab;
704: out3 <= 12'hcad;
705: out3 <= 12'hcae;
706: out3 <= 12'hcb0;
707: out3 <= 12'hcb2;
708: out3 <= 12'hcb4;
709: out3 <= 12'hcb5;
710: out3 <= 12'hcb7;
711: out3 <= 12'hcb9;
712: out3 <= 12'hcbb;
713: out3 <= 12'hcbd;
714: out3 <= 12'hcbe;
715: out3 <= 12'hcc0;
716: out3 <= 12'hcc2;
717: out3 <= 12'hcc4;
718: out3 <= 12'hcc6;
719: out3 <= 12'hcc8;
720: out3 <= 12'hcca;
721: out3 <= 12'hccb;
722: out3 <= 12'hccd;
723: out3 <= 12'hccf;
724: out3 <= 12'hcd1;
725: out3 <= 12'hcd3;
726: out3 <= 12'hcd5;
727: out3 <= 12'hcd7;
728: out3 <= 12'hcd9;
729: out3 <= 12'hcdb;
730: out3 <= 12'hcdd;
731: out3 <= 12'hcdf;
732: out3 <= 12'hce1;
733: out3 <= 12'hce2;
734: out3 <= 12'hce4;
735: out3 <= 12'hce6;
736: out3 <= 12'hce8;
737: out3 <= 12'hcea;
738: out3 <= 12'hcec;
739: out3 <= 12'hcee;
740: out3 <= 12'hcf0;
741: out3 <= 12'hcf2;
742: out3 <= 12'hcf5;
743: out3 <= 12'hcf7;
744: out3 <= 12'hcf9;
745: out3 <= 12'hcfb;
746: out3 <= 12'hcfd;
747: out3 <= 12'hcff;
748: out3 <= 12'hd01;
749: out3 <= 12'hd03;
750: out3 <= 12'hd05;
751: out3 <= 12'hd07;
752: out3 <= 12'hd09;
753: out3 <= 12'hd0b;
754: out3 <= 12'hd0d;
755: out3 <= 12'hd10;
756: out3 <= 12'hd12;
757: out3 <= 12'hd14;
758: out3 <= 12'hd16;
759: out3 <= 12'hd18;
760: out3 <= 12'hd1a;
761: out3 <= 12'hd1d;
762: out3 <= 12'hd1f;
763: out3 <= 12'hd21;
764: out3 <= 12'hd23;
765: out3 <= 12'hd25;
766: out3 <= 12'hd27;
767: out3 <= 12'hd2a;
768: out3 <= 12'hd2c;
769: out3 <= 12'hd2e;
770: out3 <= 12'hd30;
771: out3 <= 12'hd33;
772: out3 <= 12'hd35;
773: out3 <= 12'hd37;
774: out3 <= 12'hd39;
775: out3 <= 12'hd3c;
776: out3 <= 12'hd3e;
777: out3 <= 12'hd40;
778: out3 <= 12'hd42;
779: out3 <= 12'hd45;
780: out3 <= 12'hd47;
781: out3 <= 12'hd49;
782: out3 <= 12'hd4c;
783: out3 <= 12'hd4e;
784: out3 <= 12'hd50;
785: out3 <= 12'hd53;
786: out3 <= 12'hd55;
787: out3 <= 12'hd57;
788: out3 <= 12'hd5a;
789: out3 <= 12'hd5c;
790: out3 <= 12'hd5e;
791: out3 <= 12'hd61;
792: out3 <= 12'hd63;
793: out3 <= 12'hd66;
794: out3 <= 12'hd68;
795: out3 <= 12'hd6a;
796: out3 <= 12'hd6d;
797: out3 <= 12'hd6f;
798: out3 <= 12'hd72;
799: out3 <= 12'hd74;
800: out3 <= 12'hd76;
801: out3 <= 12'hd79;
802: out3 <= 12'hd7b;
803: out3 <= 12'hd7e;
804: out3 <= 12'hd80;
805: out3 <= 12'hd83;
806: out3 <= 12'hd85;
807: out3 <= 12'hd88;
808: out3 <= 12'hd8a;
809: out3 <= 12'hd8c;
810: out3 <= 12'hd8f;
811: out3 <= 12'hd91;
812: out3 <= 12'hd94;
813: out3 <= 12'hd96;
814: out3 <= 12'hd99;
815: out3 <= 12'hd9b;
816: out3 <= 12'hd9e;
817: out3 <= 12'hda1;
818: out3 <= 12'hda3;
819: out3 <= 12'hda6;
820: out3 <= 12'hda8;
821: out3 <= 12'hdab;
822: out3 <= 12'hdad;
823: out3 <= 12'hdb0;
824: out3 <= 12'hdb2;
825: out3 <= 12'hdb5;
826: out3 <= 12'hdb8;
827: out3 <= 12'hdba;
828: out3 <= 12'hdbd;
829: out3 <= 12'hdbf;
830: out3 <= 12'hdc2;
831: out3 <= 12'hdc4;
832: out3 <= 12'hdc7;
833: out3 <= 12'hdca;
834: out3 <= 12'hdcc;
835: out3 <= 12'hdcf;
836: out3 <= 12'hdd2;
837: out3 <= 12'hdd4;
838: out3 <= 12'hdd7;
839: out3 <= 12'hdda;
840: out3 <= 12'hddc;
841: out3 <= 12'hddf;
842: out3 <= 12'hde1;
843: out3 <= 12'hde4;
844: out3 <= 12'hde7;
845: out3 <= 12'hde9;
846: out3 <= 12'hdec;
847: out3 <= 12'hdef;
848: out3 <= 12'hdf2;
849: out3 <= 12'hdf4;
850: out3 <= 12'hdf7;
851: out3 <= 12'hdfa;
852: out3 <= 12'hdfc;
853: out3 <= 12'hdff;
854: out3 <= 12'he02;
855: out3 <= 12'he05;
856: out3 <= 12'he07;
857: out3 <= 12'he0a;
858: out3 <= 12'he0d;
859: out3 <= 12'he0f;
860: out3 <= 12'he12;
861: out3 <= 12'he15;
862: out3 <= 12'he18;
863: out3 <= 12'he1b;
864: out3 <= 12'he1d;
865: out3 <= 12'he20;
866: out3 <= 12'he23;
867: out3 <= 12'he26;
868: out3 <= 12'he28;
869: out3 <= 12'he2b;
870: out3 <= 12'he2e;
871: out3 <= 12'he31;
872: out3 <= 12'he34;
873: out3 <= 12'he36;
874: out3 <= 12'he39;
875: out3 <= 12'he3c;
876: out3 <= 12'he3f;
877: out3 <= 12'he42;
878: out3 <= 12'he45;
879: out3 <= 12'he47;
880: out3 <= 12'he4a;
881: out3 <= 12'he4d;
882: out3 <= 12'he50;
883: out3 <= 12'he53;
884: out3 <= 12'he56;
885: out3 <= 12'he58;
886: out3 <= 12'he5b;
887: out3 <= 12'he5e;
888: out3 <= 12'he61;
889: out3 <= 12'he64;
890: out3 <= 12'he67;
891: out3 <= 12'he6a;
892: out3 <= 12'he6d;
893: out3 <= 12'he6f;
894: out3 <= 12'he72;
895: out3 <= 12'he75;
896: out3 <= 12'he78;
897: out3 <= 12'he7b;
898: out3 <= 12'he7e;
899: out3 <= 12'he81;
900: out3 <= 12'he84;
901: out3 <= 12'he87;
902: out3 <= 12'he8a;
903: out3 <= 12'he8d;
904: out3 <= 12'he8f;
905: out3 <= 12'he92;
906: out3 <= 12'he95;
907: out3 <= 12'he98;
908: out3 <= 12'he9b;
909: out3 <= 12'he9e;
910: out3 <= 12'hea1;
911: out3 <= 12'hea4;
912: out3 <= 12'hea7;
913: out3 <= 12'heaa;
914: out3 <= 12'head;
915: out3 <= 12'heb0;
916: out3 <= 12'heb3;
917: out3 <= 12'heb6;
918: out3 <= 12'heb9;
919: out3 <= 12'hebc;
920: out3 <= 12'hebf;
921: out3 <= 12'hec2;
922: out3 <= 12'hec5;
923: out3 <= 12'hec8;
924: out3 <= 12'hecb;
925: out3 <= 12'hece;
926: out3 <= 12'hed1;
927: out3 <= 12'hed4;
928: out3 <= 12'hed7;
929: out3 <= 12'heda;
930: out3 <= 12'hedd;
931: out3 <= 12'hee0;
932: out3 <= 12'hee3;
933: out3 <= 12'hee6;
934: out3 <= 12'hee9;
935: out3 <= 12'heec;
936: out3 <= 12'heef;
937: out3 <= 12'hef2;
938: out3 <= 12'hef5;
939: out3 <= 12'hef8;
940: out3 <= 12'hefb;
941: out3 <= 12'hefe;
942: out3 <= 12'hf01;
943: out3 <= 12'hf04;
944: out3 <= 12'hf07;
945: out3 <= 12'hf0a;
946: out3 <= 12'hf0d;
947: out3 <= 12'hf10;
948: out3 <= 12'hf13;
949: out3 <= 12'hf16;
950: out3 <= 12'hf1a;
951: out3 <= 12'hf1d;
952: out3 <= 12'hf20;
953: out3 <= 12'hf23;
954: out3 <= 12'hf26;
955: out3 <= 12'hf29;
956: out3 <= 12'hf2c;
957: out3 <= 12'hf2f;
958: out3 <= 12'hf32;
959: out3 <= 12'hf35;
960: out3 <= 12'hf38;
961: out3 <= 12'hf3b;
962: out3 <= 12'hf3e;
963: out3 <= 12'hf41;
964: out3 <= 12'hf45;
965: out3 <= 12'hf48;
966: out3 <= 12'hf4b;
967: out3 <= 12'hf4e;
968: out3 <= 12'hf51;
969: out3 <= 12'hf54;
970: out3 <= 12'hf57;
971: out3 <= 12'hf5a;
972: out3 <= 12'hf5d;
973: out3 <= 12'hf60;
974: out3 <= 12'hf64;
975: out3 <= 12'hf67;
976: out3 <= 12'hf6a;
977: out3 <= 12'hf6d;
978: out3 <= 12'hf70;
979: out3 <= 12'hf73;
980: out3 <= 12'hf76;
981: out3 <= 12'hf79;
982: out3 <= 12'hf7c;
983: out3 <= 12'hf80;
984: out3 <= 12'hf83;
985: out3 <= 12'hf86;
986: out3 <= 12'hf89;
987: out3 <= 12'hf8c;
988: out3 <= 12'hf8f;
989: out3 <= 12'hf92;
990: out3 <= 12'hf95;
991: out3 <= 12'hf99;
992: out3 <= 12'hf9c;
993: out3 <= 12'hf9f;
994: out3 <= 12'hfa2;
995: out3 <= 12'hfa5;
996: out3 <= 12'hfa8;
997: out3 <= 12'hfab;
998: out3 <= 12'hfae;
999: out3 <= 12'hfb2;
1000: out3 <= 12'hfb5;
1001: out3 <= 12'hfb8;
1002: out3 <= 12'hfbb;
1003: out3 <= 12'hfbe;
1004: out3 <= 12'hfc1;
1005: out3 <= 12'hfc4;
1006: out3 <= 12'hfc7;
1007: out3 <= 12'hfcb;
1008: out3 <= 12'hfce;
1009: out3 <= 12'hfd1;
1010: out3 <= 12'hfd4;
1011: out3 <= 12'hfd7;
1012: out3 <= 12'hfda;
1013: out3 <= 12'hfdd;
1014: out3 <= 12'hfe1;
1015: out3 <= 12'hfe4;
1016: out3 <= 12'hfe7;
1017: out3 <= 12'hfea;
1018: out3 <= 12'hfed;
1019: out3 <= 12'hff0;
1020: out3 <= 12'hff3;
1021: out3 <= 12'hff7;
1022: out3 <= 12'hffa;
1023: out3 <= 12'hffd;
1024: out3 <= 12'h0;
1025: out3 <= 12'hffa;
1026: out3 <= 12'hff3;
1027: out3 <= 12'hfed;
1028: out3 <= 12'hfe7;
1029: out3 <= 12'hfe1;
1030: out3 <= 12'hfda;
1031: out3 <= 12'hfd4;
1032: out3 <= 12'hfce;
1033: out3 <= 12'hfc7;
1034: out3 <= 12'hfc1;
1035: out3 <= 12'hfbb;
1036: out3 <= 12'hfb5;
1037: out3 <= 12'hfae;
1038: out3 <= 12'hfa8;
1039: out3 <= 12'hfa2;
1040: out3 <= 12'hf9c;
1041: out3 <= 12'hf95;
1042: out3 <= 12'hf8f;
1043: out3 <= 12'hf89;
1044: out3 <= 12'hf83;
1045: out3 <= 12'hf7c;
1046: out3 <= 12'hf76;
1047: out3 <= 12'hf70;
1048: out3 <= 12'hf6a;
1049: out3 <= 12'hf64;
1050: out3 <= 12'hf5d;
1051: out3 <= 12'hf57;
1052: out3 <= 12'hf51;
1053: out3 <= 12'hf4b;
1054: out3 <= 12'hf45;
1055: out3 <= 12'hf3e;
1056: out3 <= 12'hf38;
1057: out3 <= 12'hf32;
1058: out3 <= 12'hf2c;
1059: out3 <= 12'hf26;
1060: out3 <= 12'hf20;
1061: out3 <= 12'hf1a;
1062: out3 <= 12'hf13;
1063: out3 <= 12'hf0d;
1064: out3 <= 12'hf07;
1065: out3 <= 12'hf01;
1066: out3 <= 12'hefb;
1067: out3 <= 12'hef5;
1068: out3 <= 12'heef;
1069: out3 <= 12'hee9;
1070: out3 <= 12'hee3;
1071: out3 <= 12'hedd;
1072: out3 <= 12'hed7;
1073: out3 <= 12'hed1;
1074: out3 <= 12'hecb;
1075: out3 <= 12'hec5;
1076: out3 <= 12'hebf;
1077: out3 <= 12'heb9;
1078: out3 <= 12'heb3;
1079: out3 <= 12'head;
1080: out3 <= 12'hea7;
1081: out3 <= 12'hea1;
1082: out3 <= 12'he9b;
1083: out3 <= 12'he95;
1084: out3 <= 12'he8f;
1085: out3 <= 12'he8a;
1086: out3 <= 12'he84;
1087: out3 <= 12'he7e;
1088: out3 <= 12'he78;
1089: out3 <= 12'he72;
1090: out3 <= 12'he6d;
1091: out3 <= 12'he67;
1092: out3 <= 12'he61;
1093: out3 <= 12'he5b;
1094: out3 <= 12'he56;
1095: out3 <= 12'he50;
1096: out3 <= 12'he4a;
1097: out3 <= 12'he45;
1098: out3 <= 12'he3f;
1099: out3 <= 12'he39;
1100: out3 <= 12'he34;
1101: out3 <= 12'he2e;
1102: out3 <= 12'he28;
1103: out3 <= 12'he23;
1104: out3 <= 12'he1d;
1105: out3 <= 12'he18;
1106: out3 <= 12'he12;
1107: out3 <= 12'he0d;
1108: out3 <= 12'he07;
1109: out3 <= 12'he02;
1110: out3 <= 12'hdfc;
1111: out3 <= 12'hdf7;
1112: out3 <= 12'hdf2;
1113: out3 <= 12'hdec;
1114: out3 <= 12'hde7;
1115: out3 <= 12'hde1;
1116: out3 <= 12'hddc;
1117: out3 <= 12'hdd7;
1118: out3 <= 12'hdd2;
1119: out3 <= 12'hdcc;
1120: out3 <= 12'hdc7;
1121: out3 <= 12'hdc2;
1122: out3 <= 12'hdbd;
1123: out3 <= 12'hdb8;
1124: out3 <= 12'hdb2;
1125: out3 <= 12'hdad;
1126: out3 <= 12'hda8;
1127: out3 <= 12'hda3;
1128: out3 <= 12'hd9e;
1129: out3 <= 12'hd99;
1130: out3 <= 12'hd94;
1131: out3 <= 12'hd8f;
1132: out3 <= 12'hd8a;
1133: out3 <= 12'hd85;
1134: out3 <= 12'hd80;
1135: out3 <= 12'hd7b;
1136: out3 <= 12'hd76;
1137: out3 <= 12'hd72;
1138: out3 <= 12'hd6d;
1139: out3 <= 12'hd68;
1140: out3 <= 12'hd63;
1141: out3 <= 12'hd5e;
1142: out3 <= 12'hd5a;
1143: out3 <= 12'hd55;
1144: out3 <= 12'hd50;
1145: out3 <= 12'hd4c;
1146: out3 <= 12'hd47;
1147: out3 <= 12'hd42;
1148: out3 <= 12'hd3e;
1149: out3 <= 12'hd39;
1150: out3 <= 12'hd35;
1151: out3 <= 12'hd30;
1152: out3 <= 12'hd2c;
1153: out3 <= 12'hd27;
1154: out3 <= 12'hd23;
1155: out3 <= 12'hd1f;
1156: out3 <= 12'hd1a;
1157: out3 <= 12'hd16;
1158: out3 <= 12'hd12;
1159: out3 <= 12'hd0d;
1160: out3 <= 12'hd09;
1161: out3 <= 12'hd05;
1162: out3 <= 12'hd01;
1163: out3 <= 12'hcfd;
1164: out3 <= 12'hcf9;
1165: out3 <= 12'hcf5;
1166: out3 <= 12'hcf0;
1167: out3 <= 12'hcec;
1168: out3 <= 12'hce8;
1169: out3 <= 12'hce4;
1170: out3 <= 12'hce1;
1171: out3 <= 12'hcdd;
1172: out3 <= 12'hcd9;
1173: out3 <= 12'hcd5;
1174: out3 <= 12'hcd1;
1175: out3 <= 12'hccd;
1176: out3 <= 12'hcca;
1177: out3 <= 12'hcc6;
1178: out3 <= 12'hcc2;
1179: out3 <= 12'hcbe;
1180: out3 <= 12'hcbb;
1181: out3 <= 12'hcb7;
1182: out3 <= 12'hcb4;
1183: out3 <= 12'hcb0;
1184: out3 <= 12'hcad;
1185: out3 <= 12'hca9;
1186: out3 <= 12'hca6;
1187: out3 <= 12'hca2;
1188: out3 <= 12'hc9f;
1189: out3 <= 12'hc9c;
1190: out3 <= 12'hc98;
1191: out3 <= 12'hc95;
1192: out3 <= 12'hc92;
1193: out3 <= 12'hc8e;
1194: out3 <= 12'hc8b;
1195: out3 <= 12'hc88;
1196: out3 <= 12'hc85;
1197: out3 <= 12'hc82;
1198: out3 <= 12'hc7f;
1199: out3 <= 12'hc7c;
1200: out3 <= 12'hc79;
1201: out3 <= 12'hc76;
1202: out3 <= 12'hc73;
1203: out3 <= 12'hc70;
1204: out3 <= 12'hc6d;
1205: out3 <= 12'hc6b;
1206: out3 <= 12'hc68;
1207: out3 <= 12'hc65;
1208: out3 <= 12'hc62;
1209: out3 <= 12'hc60;
1210: out3 <= 12'hc5d;
1211: out3 <= 12'hc5a;
1212: out3 <= 12'hc58;
1213: out3 <= 12'hc55;
1214: out3 <= 12'hc53;
1215: out3 <= 12'hc50;
1216: out3 <= 12'hc4e;
1217: out3 <= 12'hc4c;
1218: out3 <= 12'hc49;
1219: out3 <= 12'hc47;
1220: out3 <= 12'hc45;
1221: out3 <= 12'hc42;
1222: out3 <= 12'hc40;
1223: out3 <= 12'hc3e;
1224: out3 <= 12'hc3c;
1225: out3 <= 12'hc3a;
1226: out3 <= 12'hc38;
1227: out3 <= 12'hc36;
1228: out3 <= 12'hc34;
1229: out3 <= 12'hc32;
1230: out3 <= 12'hc30;
1231: out3 <= 12'hc2e;
1232: out3 <= 12'hc2c;
1233: out3 <= 12'hc2a;
1234: out3 <= 12'hc29;
1235: out3 <= 12'hc27;
1236: out3 <= 12'hc25;
1237: out3 <= 12'hc23;
1238: out3 <= 12'hc22;
1239: out3 <= 12'hc20;
1240: out3 <= 12'hc1f;
1241: out3 <= 12'hc1d;
1242: out3 <= 12'hc1c;
1243: out3 <= 12'hc1a;
1244: out3 <= 12'hc19;
1245: out3 <= 12'hc18;
1246: out3 <= 12'hc16;
1247: out3 <= 12'hc15;
1248: out3 <= 12'hc14;
1249: out3 <= 12'hc12;
1250: out3 <= 12'hc11;
1251: out3 <= 12'hc10;
1252: out3 <= 12'hc0f;
1253: out3 <= 12'hc0e;
1254: out3 <= 12'hc0d;
1255: out3 <= 12'hc0c;
1256: out3 <= 12'hc0b;
1257: out3 <= 12'hc0a;
1258: out3 <= 12'hc09;
1259: out3 <= 12'hc08;
1260: out3 <= 12'hc08;
1261: out3 <= 12'hc07;
1262: out3 <= 12'hc06;
1263: out3 <= 12'hc06;
1264: out3 <= 12'hc05;
1265: out3 <= 12'hc04;
1266: out3 <= 12'hc04;
1267: out3 <= 12'hc03;
1268: out3 <= 12'hc03;
1269: out3 <= 12'hc02;
1270: out3 <= 12'hc02;
1271: out3 <= 12'hc02;
1272: out3 <= 12'hc01;
1273: out3 <= 12'hc01;
1274: out3 <= 12'hc01;
1275: out3 <= 12'hc00;
1276: out3 <= 12'hc00;
1277: out3 <= 12'hc00;
1278: out3 <= 12'hc00;
1279: out3 <= 12'hc00;
1280: out3 <= 12'hc00;
1281: out3 <= 12'hc00;
1282: out3 <= 12'hc00;
1283: out3 <= 12'hc00;
1284: out3 <= 12'hc00;
1285: out3 <= 12'hc00;
1286: out3 <= 12'hc01;
1287: out3 <= 12'hc01;
1288: out3 <= 12'hc01;
1289: out3 <= 12'hc02;
1290: out3 <= 12'hc02;
1291: out3 <= 12'hc02;
1292: out3 <= 12'hc03;
1293: out3 <= 12'hc03;
1294: out3 <= 12'hc04;
1295: out3 <= 12'hc04;
1296: out3 <= 12'hc05;
1297: out3 <= 12'hc06;
1298: out3 <= 12'hc06;
1299: out3 <= 12'hc07;
1300: out3 <= 12'hc08;
1301: out3 <= 12'hc08;
1302: out3 <= 12'hc09;
1303: out3 <= 12'hc0a;
1304: out3 <= 12'hc0b;
1305: out3 <= 12'hc0c;
1306: out3 <= 12'hc0d;
1307: out3 <= 12'hc0e;
1308: out3 <= 12'hc0f;
1309: out3 <= 12'hc10;
1310: out3 <= 12'hc11;
1311: out3 <= 12'hc12;
1312: out3 <= 12'hc14;
1313: out3 <= 12'hc15;
1314: out3 <= 12'hc16;
1315: out3 <= 12'hc18;
1316: out3 <= 12'hc19;
1317: out3 <= 12'hc1a;
1318: out3 <= 12'hc1c;
1319: out3 <= 12'hc1d;
1320: out3 <= 12'hc1f;
1321: out3 <= 12'hc20;
1322: out3 <= 12'hc22;
1323: out3 <= 12'hc23;
1324: out3 <= 12'hc25;
1325: out3 <= 12'hc27;
1326: out3 <= 12'hc29;
1327: out3 <= 12'hc2a;
1328: out3 <= 12'hc2c;
1329: out3 <= 12'hc2e;
1330: out3 <= 12'hc30;
1331: out3 <= 12'hc32;
1332: out3 <= 12'hc34;
1333: out3 <= 12'hc36;
1334: out3 <= 12'hc38;
1335: out3 <= 12'hc3a;
1336: out3 <= 12'hc3c;
1337: out3 <= 12'hc3e;
1338: out3 <= 12'hc40;
1339: out3 <= 12'hc42;
1340: out3 <= 12'hc45;
1341: out3 <= 12'hc47;
1342: out3 <= 12'hc49;
1343: out3 <= 12'hc4c;
1344: out3 <= 12'hc4e;
1345: out3 <= 12'hc50;
1346: out3 <= 12'hc53;
1347: out3 <= 12'hc55;
1348: out3 <= 12'hc58;
1349: out3 <= 12'hc5a;
1350: out3 <= 12'hc5d;
1351: out3 <= 12'hc60;
1352: out3 <= 12'hc62;
1353: out3 <= 12'hc65;
1354: out3 <= 12'hc68;
1355: out3 <= 12'hc6b;
1356: out3 <= 12'hc6d;
1357: out3 <= 12'hc70;
1358: out3 <= 12'hc73;
1359: out3 <= 12'hc76;
1360: out3 <= 12'hc79;
1361: out3 <= 12'hc7c;
1362: out3 <= 12'hc7f;
1363: out3 <= 12'hc82;
1364: out3 <= 12'hc85;
1365: out3 <= 12'hc88;
1366: out3 <= 12'hc8b;
1367: out3 <= 12'hc8e;
1368: out3 <= 12'hc92;
1369: out3 <= 12'hc95;
1370: out3 <= 12'hc98;
1371: out3 <= 12'hc9c;
1372: out3 <= 12'hc9f;
1373: out3 <= 12'hca2;
1374: out3 <= 12'hca6;
1375: out3 <= 12'hca9;
1376: out3 <= 12'hcad;
1377: out3 <= 12'hcb0;
1378: out3 <= 12'hcb4;
1379: out3 <= 12'hcb7;
1380: out3 <= 12'hcbb;
1381: out3 <= 12'hcbe;
1382: out3 <= 12'hcc2;
1383: out3 <= 12'hcc6;
1384: out3 <= 12'hcca;
1385: out3 <= 12'hccd;
1386: out3 <= 12'hcd1;
1387: out3 <= 12'hcd5;
1388: out3 <= 12'hcd9;
1389: out3 <= 12'hcdd;
1390: out3 <= 12'hce1;
1391: out3 <= 12'hce4;
1392: out3 <= 12'hce8;
1393: out3 <= 12'hcec;
1394: out3 <= 12'hcf0;
1395: out3 <= 12'hcf5;
1396: out3 <= 12'hcf9;
1397: out3 <= 12'hcfd;
1398: out3 <= 12'hd01;
1399: out3 <= 12'hd05;
1400: out3 <= 12'hd09;
1401: out3 <= 12'hd0d;
1402: out3 <= 12'hd12;
1403: out3 <= 12'hd16;
1404: out3 <= 12'hd1a;
1405: out3 <= 12'hd1f;
1406: out3 <= 12'hd23;
1407: out3 <= 12'hd27;
1408: out3 <= 12'hd2c;
1409: out3 <= 12'hd30;
1410: out3 <= 12'hd35;
1411: out3 <= 12'hd39;
1412: out3 <= 12'hd3e;
1413: out3 <= 12'hd42;
1414: out3 <= 12'hd47;
1415: out3 <= 12'hd4c;
1416: out3 <= 12'hd50;
1417: out3 <= 12'hd55;
1418: out3 <= 12'hd5a;
1419: out3 <= 12'hd5e;
1420: out3 <= 12'hd63;
1421: out3 <= 12'hd68;
1422: out3 <= 12'hd6d;
1423: out3 <= 12'hd72;
1424: out3 <= 12'hd76;
1425: out3 <= 12'hd7b;
1426: out3 <= 12'hd80;
1427: out3 <= 12'hd85;
1428: out3 <= 12'hd8a;
1429: out3 <= 12'hd8f;
1430: out3 <= 12'hd94;
1431: out3 <= 12'hd99;
1432: out3 <= 12'hd9e;
1433: out3 <= 12'hda3;
1434: out3 <= 12'hda8;
1435: out3 <= 12'hdad;
1436: out3 <= 12'hdb2;
1437: out3 <= 12'hdb8;
1438: out3 <= 12'hdbd;
1439: out3 <= 12'hdc2;
1440: out3 <= 12'hdc7;
1441: out3 <= 12'hdcc;
1442: out3 <= 12'hdd2;
1443: out3 <= 12'hdd7;
1444: out3 <= 12'hddc;
1445: out3 <= 12'hde1;
1446: out3 <= 12'hde7;
1447: out3 <= 12'hdec;
1448: out3 <= 12'hdf2;
1449: out3 <= 12'hdf7;
1450: out3 <= 12'hdfc;
1451: out3 <= 12'he02;
1452: out3 <= 12'he07;
1453: out3 <= 12'he0d;
1454: out3 <= 12'he12;
1455: out3 <= 12'he18;
1456: out3 <= 12'he1d;
1457: out3 <= 12'he23;
1458: out3 <= 12'he28;
1459: out3 <= 12'he2e;
1460: out3 <= 12'he34;
1461: out3 <= 12'he39;
1462: out3 <= 12'he3f;
1463: out3 <= 12'he45;
1464: out3 <= 12'he4a;
1465: out3 <= 12'he50;
1466: out3 <= 12'he56;
1467: out3 <= 12'he5b;
1468: out3 <= 12'he61;
1469: out3 <= 12'he67;
1470: out3 <= 12'he6d;
1471: out3 <= 12'he72;
1472: out3 <= 12'he78;
1473: out3 <= 12'he7e;
1474: out3 <= 12'he84;
1475: out3 <= 12'he8a;
1476: out3 <= 12'he8f;
1477: out3 <= 12'he95;
1478: out3 <= 12'he9b;
1479: out3 <= 12'hea1;
1480: out3 <= 12'hea7;
1481: out3 <= 12'head;
1482: out3 <= 12'heb3;
1483: out3 <= 12'heb9;
1484: out3 <= 12'hebf;
1485: out3 <= 12'hec5;
1486: out3 <= 12'hecb;
1487: out3 <= 12'hed1;
1488: out3 <= 12'hed7;
1489: out3 <= 12'hedd;
1490: out3 <= 12'hee3;
1491: out3 <= 12'hee9;
1492: out3 <= 12'heef;
1493: out3 <= 12'hef5;
1494: out3 <= 12'hefb;
1495: out3 <= 12'hf01;
1496: out3 <= 12'hf07;
1497: out3 <= 12'hf0d;
1498: out3 <= 12'hf13;
1499: out3 <= 12'hf1a;
1500: out3 <= 12'hf20;
1501: out3 <= 12'hf26;
1502: out3 <= 12'hf2c;
1503: out3 <= 12'hf32;
1504: out3 <= 12'hf38;
1505: out3 <= 12'hf3e;
1506: out3 <= 12'hf45;
1507: out3 <= 12'hf4b;
1508: out3 <= 12'hf51;
1509: out3 <= 12'hf57;
1510: out3 <= 12'hf5d;
1511: out3 <= 12'hf64;
1512: out3 <= 12'hf6a;
1513: out3 <= 12'hf70;
1514: out3 <= 12'hf76;
1515: out3 <= 12'hf7c;
1516: out3 <= 12'hf83;
1517: out3 <= 12'hf89;
1518: out3 <= 12'hf8f;
1519: out3 <= 12'hf95;
1520: out3 <= 12'hf9c;
1521: out3 <= 12'hfa2;
1522: out3 <= 12'hfa8;
1523: out3 <= 12'hfae;
1524: out3 <= 12'hfb5;
1525: out3 <= 12'hfbb;
1526: out3 <= 12'hfc1;
1527: out3 <= 12'hfc7;
1528: out3 <= 12'hfce;
1529: out3 <= 12'hfd4;
1530: out3 <= 12'hfda;
1531: out3 <= 12'hfe1;
1532: out3 <= 12'hfe7;
1533: out3 <= 12'hfed;
1534: out3 <= 12'hff3;
1535: out3 <= 12'hffa;
1536: out3 <= 12'h0;
1537: out3 <= 12'h6;
1538: out3 <= 12'hd;
1539: out3 <= 12'h13;
1540: out3 <= 12'h19;
1541: out3 <= 12'h1f;
1542: out3 <= 12'h26;
1543: out3 <= 12'h2c;
1544: out3 <= 12'h32;
1545: out3 <= 12'h39;
1546: out3 <= 12'h3f;
1547: out3 <= 12'h45;
1548: out3 <= 12'h4b;
1549: out3 <= 12'h52;
1550: out3 <= 12'h58;
1551: out3 <= 12'h5e;
1552: out3 <= 12'h64;
1553: out3 <= 12'h6b;
1554: out3 <= 12'h71;
1555: out3 <= 12'h77;
1556: out3 <= 12'h7d;
1557: out3 <= 12'h84;
1558: out3 <= 12'h8a;
1559: out3 <= 12'h90;
1560: out3 <= 12'h96;
1561: out3 <= 12'h9c;
1562: out3 <= 12'ha3;
1563: out3 <= 12'ha9;
1564: out3 <= 12'haf;
1565: out3 <= 12'hb5;
1566: out3 <= 12'hbb;
1567: out3 <= 12'hc2;
1568: out3 <= 12'hc8;
1569: out3 <= 12'hce;
1570: out3 <= 12'hd4;
1571: out3 <= 12'hda;
1572: out3 <= 12'he0;
1573: out3 <= 12'he6;
1574: out3 <= 12'hed;
1575: out3 <= 12'hf3;
1576: out3 <= 12'hf9;
1577: out3 <= 12'hff;
1578: out3 <= 12'h105;
1579: out3 <= 12'h10b;
1580: out3 <= 12'h111;
1581: out3 <= 12'h117;
1582: out3 <= 12'h11d;
1583: out3 <= 12'h123;
1584: out3 <= 12'h129;
1585: out3 <= 12'h12f;
1586: out3 <= 12'h135;
1587: out3 <= 12'h13b;
1588: out3 <= 12'h141;
1589: out3 <= 12'h147;
1590: out3 <= 12'h14d;
1591: out3 <= 12'h153;
1592: out3 <= 12'h159;
1593: out3 <= 12'h15f;
1594: out3 <= 12'h165;
1595: out3 <= 12'h16b;
1596: out3 <= 12'h171;
1597: out3 <= 12'h176;
1598: out3 <= 12'h17c;
1599: out3 <= 12'h182;
1600: out3 <= 12'h188;
1601: out3 <= 12'h18e;
1602: out3 <= 12'h193;
1603: out3 <= 12'h199;
1604: out3 <= 12'h19f;
1605: out3 <= 12'h1a5;
1606: out3 <= 12'h1aa;
1607: out3 <= 12'h1b0;
1608: out3 <= 12'h1b6;
1609: out3 <= 12'h1bb;
1610: out3 <= 12'h1c1;
1611: out3 <= 12'h1c7;
1612: out3 <= 12'h1cc;
1613: out3 <= 12'h1d2;
1614: out3 <= 12'h1d8;
1615: out3 <= 12'h1dd;
1616: out3 <= 12'h1e3;
1617: out3 <= 12'h1e8;
1618: out3 <= 12'h1ee;
1619: out3 <= 12'h1f3;
1620: out3 <= 12'h1f9;
1621: out3 <= 12'h1fe;
1622: out3 <= 12'h204;
1623: out3 <= 12'h209;
1624: out3 <= 12'h20e;
1625: out3 <= 12'h214;
1626: out3 <= 12'h219;
1627: out3 <= 12'h21f;
1628: out3 <= 12'h224;
1629: out3 <= 12'h229;
1630: out3 <= 12'h22e;
1631: out3 <= 12'h234;
1632: out3 <= 12'h239;
1633: out3 <= 12'h23e;
1634: out3 <= 12'h243;
1635: out3 <= 12'h248;
1636: out3 <= 12'h24e;
1637: out3 <= 12'h253;
1638: out3 <= 12'h258;
1639: out3 <= 12'h25d;
1640: out3 <= 12'h262;
1641: out3 <= 12'h267;
1642: out3 <= 12'h26c;
1643: out3 <= 12'h271;
1644: out3 <= 12'h276;
1645: out3 <= 12'h27b;
1646: out3 <= 12'h280;
1647: out3 <= 12'h285;
1648: out3 <= 12'h28a;
1649: out3 <= 12'h28e;
1650: out3 <= 12'h293;
1651: out3 <= 12'h298;
1652: out3 <= 12'h29d;
1653: out3 <= 12'h2a2;
1654: out3 <= 12'h2a6;
1655: out3 <= 12'h2ab;
1656: out3 <= 12'h2b0;
1657: out3 <= 12'h2b4;
1658: out3 <= 12'h2b9;
1659: out3 <= 12'h2be;
1660: out3 <= 12'h2c2;
1661: out3 <= 12'h2c7;
1662: out3 <= 12'h2cb;
1663: out3 <= 12'h2d0;
1664: out3 <= 12'h2d4;
1665: out3 <= 12'h2d9;
1666: out3 <= 12'h2dd;
1667: out3 <= 12'h2e1;
1668: out3 <= 12'h2e6;
1669: out3 <= 12'h2ea;
1670: out3 <= 12'h2ee;
1671: out3 <= 12'h2f3;
1672: out3 <= 12'h2f7;
1673: out3 <= 12'h2fb;
1674: out3 <= 12'h2ff;
1675: out3 <= 12'h303;
1676: out3 <= 12'h307;
1677: out3 <= 12'h30b;
1678: out3 <= 12'h310;
1679: out3 <= 12'h314;
1680: out3 <= 12'h318;
1681: out3 <= 12'h31c;
1682: out3 <= 12'h31f;
1683: out3 <= 12'h323;
1684: out3 <= 12'h327;
1685: out3 <= 12'h32b;
1686: out3 <= 12'h32f;
1687: out3 <= 12'h333;
1688: out3 <= 12'h336;
1689: out3 <= 12'h33a;
1690: out3 <= 12'h33e;
1691: out3 <= 12'h342;
1692: out3 <= 12'h345;
1693: out3 <= 12'h349;
1694: out3 <= 12'h34c;
1695: out3 <= 12'h350;
1696: out3 <= 12'h353;
1697: out3 <= 12'h357;
1698: out3 <= 12'h35a;
1699: out3 <= 12'h35e;
1700: out3 <= 12'h361;
1701: out3 <= 12'h364;
1702: out3 <= 12'h368;
1703: out3 <= 12'h36b;
1704: out3 <= 12'h36e;
1705: out3 <= 12'h372;
1706: out3 <= 12'h375;
1707: out3 <= 12'h378;
1708: out3 <= 12'h37b;
1709: out3 <= 12'h37e;
1710: out3 <= 12'h381;
1711: out3 <= 12'h384;
1712: out3 <= 12'h387;
1713: out3 <= 12'h38a;
1714: out3 <= 12'h38d;
1715: out3 <= 12'h390;
1716: out3 <= 12'h393;
1717: out3 <= 12'h395;
1718: out3 <= 12'h398;
1719: out3 <= 12'h39b;
1720: out3 <= 12'h39e;
1721: out3 <= 12'h3a0;
1722: out3 <= 12'h3a3;
1723: out3 <= 12'h3a6;
1724: out3 <= 12'h3a8;
1725: out3 <= 12'h3ab;
1726: out3 <= 12'h3ad;
1727: out3 <= 12'h3b0;
1728: out3 <= 12'h3b2;
1729: out3 <= 12'h3b4;
1730: out3 <= 12'h3b7;
1731: out3 <= 12'h3b9;
1732: out3 <= 12'h3bb;
1733: out3 <= 12'h3be;
1734: out3 <= 12'h3c0;
1735: out3 <= 12'h3c2;
1736: out3 <= 12'h3c4;
1737: out3 <= 12'h3c6;
1738: out3 <= 12'h3c8;
1739: out3 <= 12'h3ca;
1740: out3 <= 12'h3cc;
1741: out3 <= 12'h3ce;
1742: out3 <= 12'h3d0;
1743: out3 <= 12'h3d2;
1744: out3 <= 12'h3d4;
1745: out3 <= 12'h3d6;
1746: out3 <= 12'h3d7;
1747: out3 <= 12'h3d9;
1748: out3 <= 12'h3db;
1749: out3 <= 12'h3dd;
1750: out3 <= 12'h3de;
1751: out3 <= 12'h3e0;
1752: out3 <= 12'h3e1;
1753: out3 <= 12'h3e3;
1754: out3 <= 12'h3e4;
1755: out3 <= 12'h3e6;
1756: out3 <= 12'h3e7;
1757: out3 <= 12'h3e8;
1758: out3 <= 12'h3ea;
1759: out3 <= 12'h3eb;
1760: out3 <= 12'h3ec;
1761: out3 <= 12'h3ee;
1762: out3 <= 12'h3ef;
1763: out3 <= 12'h3f0;
1764: out3 <= 12'h3f1;
1765: out3 <= 12'h3f2;
1766: out3 <= 12'h3f3;
1767: out3 <= 12'h3f4;
1768: out3 <= 12'h3f5;
1769: out3 <= 12'h3f6;
1770: out3 <= 12'h3f7;
1771: out3 <= 12'h3f8;
1772: out3 <= 12'h3f8;
1773: out3 <= 12'h3f9;
1774: out3 <= 12'h3fa;
1775: out3 <= 12'h3fa;
1776: out3 <= 12'h3fb;
1777: out3 <= 12'h3fc;
1778: out3 <= 12'h3fc;
1779: out3 <= 12'h3fd;
1780: out3 <= 12'h3fd;
1781: out3 <= 12'h3fe;
1782: out3 <= 12'h3fe;
1783: out3 <= 12'h3fe;
1784: out3 <= 12'h3ff;
1785: out3 <= 12'h3ff;
1786: out3 <= 12'h3ff;
1787: out3 <= 12'h400;
1788: out3 <= 12'h400;
1789: out3 <= 12'h400;
1790: out3 <= 12'h400;
1791: out3 <= 12'h400;
1792: out3 <= 12'h400;
1793: out3 <= 12'h400;
1794: out3 <= 12'h400;
1795: out3 <= 12'h400;
1796: out3 <= 12'h400;
1797: out3 <= 12'h400;
1798: out3 <= 12'h3ff;
1799: out3 <= 12'h3ff;
1800: out3 <= 12'h3ff;
1801: out3 <= 12'h3fe;
1802: out3 <= 12'h3fe;
1803: out3 <= 12'h3fe;
1804: out3 <= 12'h3fd;
1805: out3 <= 12'h3fd;
1806: out3 <= 12'h3fc;
1807: out3 <= 12'h3fc;
1808: out3 <= 12'h3fb;
1809: out3 <= 12'h3fa;
1810: out3 <= 12'h3fa;
1811: out3 <= 12'h3f9;
1812: out3 <= 12'h3f8;
1813: out3 <= 12'h3f8;
1814: out3 <= 12'h3f7;
1815: out3 <= 12'h3f6;
1816: out3 <= 12'h3f5;
1817: out3 <= 12'h3f4;
1818: out3 <= 12'h3f3;
1819: out3 <= 12'h3f2;
1820: out3 <= 12'h3f1;
1821: out3 <= 12'h3f0;
1822: out3 <= 12'h3ef;
1823: out3 <= 12'h3ee;
1824: out3 <= 12'h3ec;
1825: out3 <= 12'h3eb;
1826: out3 <= 12'h3ea;
1827: out3 <= 12'h3e8;
1828: out3 <= 12'h3e7;
1829: out3 <= 12'h3e6;
1830: out3 <= 12'h3e4;
1831: out3 <= 12'h3e3;
1832: out3 <= 12'h3e1;
1833: out3 <= 12'h3e0;
1834: out3 <= 12'h3de;
1835: out3 <= 12'h3dd;
1836: out3 <= 12'h3db;
1837: out3 <= 12'h3d9;
1838: out3 <= 12'h3d7;
1839: out3 <= 12'h3d6;
1840: out3 <= 12'h3d4;
1841: out3 <= 12'h3d2;
1842: out3 <= 12'h3d0;
1843: out3 <= 12'h3ce;
1844: out3 <= 12'h3cc;
1845: out3 <= 12'h3ca;
1846: out3 <= 12'h3c8;
1847: out3 <= 12'h3c6;
1848: out3 <= 12'h3c4;
1849: out3 <= 12'h3c2;
1850: out3 <= 12'h3c0;
1851: out3 <= 12'h3be;
1852: out3 <= 12'h3bb;
1853: out3 <= 12'h3b9;
1854: out3 <= 12'h3b7;
1855: out3 <= 12'h3b4;
1856: out3 <= 12'h3b2;
1857: out3 <= 12'h3b0;
1858: out3 <= 12'h3ad;
1859: out3 <= 12'h3ab;
1860: out3 <= 12'h3a8;
1861: out3 <= 12'h3a6;
1862: out3 <= 12'h3a3;
1863: out3 <= 12'h3a0;
1864: out3 <= 12'h39e;
1865: out3 <= 12'h39b;
1866: out3 <= 12'h398;
1867: out3 <= 12'h395;
1868: out3 <= 12'h393;
1869: out3 <= 12'h390;
1870: out3 <= 12'h38d;
1871: out3 <= 12'h38a;
1872: out3 <= 12'h387;
1873: out3 <= 12'h384;
1874: out3 <= 12'h381;
1875: out3 <= 12'h37e;
1876: out3 <= 12'h37b;
1877: out3 <= 12'h378;
1878: out3 <= 12'h375;
1879: out3 <= 12'h372;
1880: out3 <= 12'h36e;
1881: out3 <= 12'h36b;
1882: out3 <= 12'h368;
1883: out3 <= 12'h364;
1884: out3 <= 12'h361;
1885: out3 <= 12'h35e;
1886: out3 <= 12'h35a;
1887: out3 <= 12'h357;
1888: out3 <= 12'h353;
1889: out3 <= 12'h350;
1890: out3 <= 12'h34c;
1891: out3 <= 12'h349;
1892: out3 <= 12'h345;
1893: out3 <= 12'h342;
1894: out3 <= 12'h33e;
1895: out3 <= 12'h33a;
1896: out3 <= 12'h336;
1897: out3 <= 12'h333;
1898: out3 <= 12'h32f;
1899: out3 <= 12'h32b;
1900: out3 <= 12'h327;
1901: out3 <= 12'h323;
1902: out3 <= 12'h31f;
1903: out3 <= 12'h31c;
1904: out3 <= 12'h318;
1905: out3 <= 12'h314;
1906: out3 <= 12'h310;
1907: out3 <= 12'h30b;
1908: out3 <= 12'h307;
1909: out3 <= 12'h303;
1910: out3 <= 12'h2ff;
1911: out3 <= 12'h2fb;
1912: out3 <= 12'h2f7;
1913: out3 <= 12'h2f3;
1914: out3 <= 12'h2ee;
1915: out3 <= 12'h2ea;
1916: out3 <= 12'h2e6;
1917: out3 <= 12'h2e1;
1918: out3 <= 12'h2dd;
1919: out3 <= 12'h2d9;
1920: out3 <= 12'h2d4;
1921: out3 <= 12'h2d0;
1922: out3 <= 12'h2cb;
1923: out3 <= 12'h2c7;
1924: out3 <= 12'h2c2;
1925: out3 <= 12'h2be;
1926: out3 <= 12'h2b9;
1927: out3 <= 12'h2b4;
1928: out3 <= 12'h2b0;
1929: out3 <= 12'h2ab;
1930: out3 <= 12'h2a6;
1931: out3 <= 12'h2a2;
1932: out3 <= 12'h29d;
1933: out3 <= 12'h298;
1934: out3 <= 12'h293;
1935: out3 <= 12'h28e;
1936: out3 <= 12'h28a;
1937: out3 <= 12'h285;
1938: out3 <= 12'h280;
1939: out3 <= 12'h27b;
1940: out3 <= 12'h276;
1941: out3 <= 12'h271;
1942: out3 <= 12'h26c;
1943: out3 <= 12'h267;
1944: out3 <= 12'h262;
1945: out3 <= 12'h25d;
1946: out3 <= 12'h258;
1947: out3 <= 12'h253;
1948: out3 <= 12'h24e;
1949: out3 <= 12'h248;
1950: out3 <= 12'h243;
1951: out3 <= 12'h23e;
1952: out3 <= 12'h239;
1953: out3 <= 12'h234;
1954: out3 <= 12'h22e;
1955: out3 <= 12'h229;
1956: out3 <= 12'h224;
1957: out3 <= 12'h21f;
1958: out3 <= 12'h219;
1959: out3 <= 12'h214;
1960: out3 <= 12'h20e;
1961: out3 <= 12'h209;
1962: out3 <= 12'h204;
1963: out3 <= 12'h1fe;
1964: out3 <= 12'h1f9;
1965: out3 <= 12'h1f3;
1966: out3 <= 12'h1ee;
1967: out3 <= 12'h1e8;
1968: out3 <= 12'h1e3;
1969: out3 <= 12'h1dd;
1970: out3 <= 12'h1d8;
1971: out3 <= 12'h1d2;
1972: out3 <= 12'h1cc;
1973: out3 <= 12'h1c7;
1974: out3 <= 12'h1c1;
1975: out3 <= 12'h1bb;
1976: out3 <= 12'h1b6;
1977: out3 <= 12'h1b0;
1978: out3 <= 12'h1aa;
1979: out3 <= 12'h1a5;
1980: out3 <= 12'h19f;
1981: out3 <= 12'h199;
1982: out3 <= 12'h193;
1983: out3 <= 12'h18e;
1984: out3 <= 12'h188;
1985: out3 <= 12'h182;
1986: out3 <= 12'h17c;
1987: out3 <= 12'h176;
1988: out3 <= 12'h171;
1989: out3 <= 12'h16b;
1990: out3 <= 12'h165;
1991: out3 <= 12'h15f;
1992: out3 <= 12'h159;
1993: out3 <= 12'h153;
1994: out3 <= 12'h14d;
1995: out3 <= 12'h147;
1996: out3 <= 12'h141;
1997: out3 <= 12'h13b;
1998: out3 <= 12'h135;
1999: out3 <= 12'h12f;
2000: out3 <= 12'h129;
2001: out3 <= 12'h123;
2002: out3 <= 12'h11d;
2003: out3 <= 12'h117;
2004: out3 <= 12'h111;
2005: out3 <= 12'h10b;
2006: out3 <= 12'h105;
2007: out3 <= 12'hff;
2008: out3 <= 12'hf9;
2009: out3 <= 12'hf3;
2010: out3 <= 12'hed;
2011: out3 <= 12'he6;
2012: out3 <= 12'he0;
2013: out3 <= 12'hda;
2014: out3 <= 12'hd4;
2015: out3 <= 12'hce;
2016: out3 <= 12'hc8;
2017: out3 <= 12'hc2;
2018: out3 <= 12'hbb;
2019: out3 <= 12'hb5;
2020: out3 <= 12'haf;
2021: out3 <= 12'ha9;
2022: out3 <= 12'ha3;
2023: out3 <= 12'h9c;
2024: out3 <= 12'h96;
2025: out3 <= 12'h90;
2026: out3 <= 12'h8a;
2027: out3 <= 12'h84;
2028: out3 <= 12'h7d;
2029: out3 <= 12'h77;
2030: out3 <= 12'h71;
2031: out3 <= 12'h6b;
2032: out3 <= 12'h64;
2033: out3 <= 12'h5e;
2034: out3 <= 12'h58;
2035: out3 <= 12'h52;
2036: out3 <= 12'h4b;
2037: out3 <= 12'h45;
2038: out3 <= 12'h3f;
2039: out3 <= 12'h39;
2040: out3 <= 12'h32;
2041: out3 <= 12'h2c;
2042: out3 <= 12'h26;
2043: out3 <= 12'h1f;
2044: out3 <= 12'h19;
2045: out3 <= 12'h13;
2046: out3 <= 12'hd;
2047: out3 <= 12'h6;
default: out3 <= 0;
endcase
end
// synthesis attribute rom_style of out3 is "block"
endmodule |
module codeBlock41778(clk, reset, next_in, next_out,
i2_in,
i1_in,
X0_in, Y0,
X1_in, Y1,
X2_in, Y2,
X3_in, Y3);
output next_out;
input clk, reset, next_in;
reg next;
input [9:0] i2_in;
reg [9:0] i2;
input [4:0] i1_in;
reg [4:0] i1;
input [11:0] X0_in,
X1_in,
X2_in,
X3_in;
reg [11:0] X0,
X1,
X2,
X3;
output [11:0] Y0,
Y1,
Y2,
Y3;
shiftRegFIFO #(10, 1) shiftFIFO_46356(.X(next), .Y(next_out), .clk(clk));
wire [10:0] a57;
wire [9:0] a59;
wire [10:0] a60;
wire signed [11:0] a70;
wire signed [11:0] a71;
wire [11:0] a58;
reg [10:0] tm15;
reg signed [11:0] tm16;
reg signed [11:0] tm23;
reg signed [11:0] tm44;
reg signed [11:0] tm54;
reg [11:0] a61;
wire [10:0] a62;
reg signed [11:0] tm17;
reg signed [11:0] tm24;
reg signed [11:0] tm45;
reg signed [11:0] tm55;
wire [11:0] a63;
reg signed [11:0] tm18;
reg signed [11:0] tm25;
reg signed [11:0] tm46;
reg signed [11:0] tm56;
reg signed [11:0] tm19;
reg signed [11:0] tm26;
reg signed [11:0] tm47;
reg signed [11:0] tm57;
reg signed [11:0] tm20;
reg signed [11:0] tm27;
reg signed [11:0] tm48;
reg signed [11:0] tm58;
wire signed [11:0] tm5;
wire signed [11:0] a64;
wire signed [11:0] tm6;
wire signed [11:0] a66;
reg signed [11:0] tm21;
reg signed [11:0] tm28;
reg signed [11:0] tm49;
reg signed [11:0] tm59;
reg signed [11:0] tm7;
reg signed [11:0] tm8;
reg signed [11:0] tm22;
reg signed [11:0] tm29;
reg signed [11:0] tm50;
reg signed [11:0] tm60;
reg signed [11:0] tm51;
reg signed [11:0] tm61;
wire signed [11:0] a65;
wire signed [11:0] a67;
wire signed [11:0] a68;
wire signed [11:0] a69;
reg signed [11:0] tm52;
reg signed [11:0] tm62;
wire signed [11:0] Y0;
wire signed [11:0] Y1;
wire signed [11:0] Y2;
wire signed [11:0] Y3;
reg signed [11:0] tm53;
reg signed [11:0] tm63;
wire [0:0] tm1;
assign tm1 = 1'h1;
wire [9:0] tm2;
assign tm2 = 10'h3ff;
wire [10:0] tm4;
assign tm4 = 11'h400;
assign a57 = i2 << 1;
assign a59 = tm2 << i1;
assign a60 = {a59, tm1[0:0]};
assign a70 = X2;
assign a71 = X3;
assign a62 = {a61[0:0], a61[10:1]};
assign a64 = tm5;
assign a66 = tm6;
assign Y0 = tm53;
assign Y1 = tm63;
D1_43962 instD1inst0_43962(.addr(a63[10:0]), .out(tm5), .clk(clk));
D2_46012 instD2inst0_46012(.addr(a63[10:0]), .out(tm6), .clk(clk));
addfxp #(12, 1) add41797(.a({1'b0, a57}), .b({11'b0, tm1}), .clk(clk), .q(a58)); // 0
subfxp #(12, 1) sub41829(.a({1'b0, a62}), .b({1'b0, tm4}), .clk(clk), .q(a63)); // 2
multfix #(12, 2) m41851(.a(tm7), .b(tm22), .clk(clk), .q_sc(a65), .q_unsc(), .rst(reset));
multfix #(12, 2) m41873(.a(tm8), .b(tm29), .clk(clk), .q_sc(a67), .q_unsc(), .rst(reset));
multfix #(12, 2) m41891(.a(tm8), .b(tm22), .clk(clk), .q_sc(a68), .q_unsc(), .rst(reset));
multfix #(12, 2) m41902(.a(tm7), .b(tm29), .clk(clk), .q_sc(a69), .q_unsc(), .rst(reset));
subfxp #(12, 1) sub41880(.a(a65), .b(a67), .clk(clk), .q(Y2)); // 9
addfxp #(12, 1) add41909(.a(a68), .b(a69), .clk(clk), .q(Y3)); // 9
always @(posedge clk) begin
if (reset == 1) begin
tm7 <= 0;
tm22 <= 0;
tm8 <= 0;
tm29 <= 0;
tm8 <= 0;
tm22 <= 0;
tm7 <= 0;
tm29 <= 0;
end
else begin
i2 <= i2_in;
i1 <= i1_in;
X0 <= X0_in;
X1 <= X1_in;
X2 <= X2_in;
X3 <= X3_in;
next <= next_in;
tm15 <= a60;
tm16 <= a70;
tm23 <= a71;
tm44 <= X0;
tm54 <= X1;
a61 <= (a58 & tm15);
tm17 <= tm16;
tm24 <= tm23;
tm45 <= tm44;
tm55 <= tm54;
tm18 <= tm17;
tm25 <= tm24;
tm46 <= tm45;
tm56 <= tm55;
tm19 <= tm18;
tm26 <= tm25;
tm47 <= tm46;
tm57 <= tm56;
tm20 <= tm19;
tm27 <= tm26;
tm48 <= tm47;
tm58 <= tm57;
tm21 <= tm20;
tm28 <= tm27;
tm49 <= tm48;
tm59 <= tm58;
tm7 <= a64;
tm8 <= a66;
tm22 <= tm21;
tm29 <= tm28;
tm50 <= tm49;
tm60 <= tm59;
tm51 <= tm50;
tm61 <= tm60;
tm52 <= tm51;
tm62 <= tm61;
tm53 <= tm52;
tm63 <= tm62;
end
end
endmodule |
module codeBlock46016(clk, reset, next_in, next_out,
X0_in, Y0,
X1_in, Y1,
X2_in, Y2,
X3_in, Y3);
output next_out;
input clk, reset, next_in;
reg next;
input [11:0] X0_in,
X1_in,
X2_in,
X3_in;
reg [11:0] X0,
X1,
X2,
X3;
output [11:0] Y0,
Y1,
Y2,
Y3;
shiftRegFIFO #(1, 1) shiftFIFO_46359(.X(next), .Y(next_out), .clk(clk));
wire signed [11:0] a9;
wire signed [11:0] a10;
wire signed [11:0] a11;
wire signed [11:0] a12;
wire signed [12:0] tm11;
wire signed [12:0] tm12;
wire signed [12:0] tm13;
wire signed [12:0] tm14;
wire signed [11:0] Y0;
wire signed [11:0] Y1;
wire signed [11:0] Y2;
wire signed [11:0] Y3;
wire signed [11:0] t21;
wire signed [11:0] t22;
wire signed [11:0] t23;
wire signed [11:0] t24;
assign a9 = X0;
assign a10 = X2;
assign a11 = X1;
assign a12 = X3;
assign Y0 = t21;
assign Y1 = t22;
assign Y2 = t23;
assign Y3 = t24;
assign t21 = tm11[12:1];
assign t22 = tm12[12:1];
assign t23 = tm13[12:1];
assign t24 = tm14[12:1];
addfxp #(13, 1) add46028(.a({{1{a9[11]}}, a9}), .b({{1{a10[11]}}, a10}), .clk(clk), .q(tm11)); // 0
addfxp #(13, 1) add46043(.a({{1{a11[11]}}, a11}), .b({{1{a12[11]}}, a12}), .clk(clk), .q(tm12)); // 0
subfxp #(13, 1) sub46058(.a({{1{a9[11]}}, a9}), .b({{1{a10[11]}}, a10}), .clk(clk), .q(tm13)); // 0
subfxp #(13, 1) sub46073(.a({{1{a11[11]}}, a11}), .b({{1{a12[11]}}, a12}), .clk(clk), .q(tm14)); // 0
always @(posedge clk) begin
if (reset == 1) begin
end
else begin
X0 <= X0_in;
X1 <= X1_in;
X2 <= X2_in;
X3 <= X3_in;
next <= next_in;
end
end
endmodule |
module rc46097(clk, reset, next, next_out,
X0, Y0,
X1, Y1,
X2, Y2,
X3, Y3);
output next_out;
input clk, reset, next;
input [11:0] X0,
X1,
X2,
X3;
output [11:0] Y0,
Y1,
Y2,
Y3;
wire [23:0] t0;
wire [23:0] s0;
assign t0 = {X0, X1};
wire [23:0] t1;
wire [23:0] s1;
assign t1 = {X2, X3};
assign Y0 = s0[23:12];
assign Y1 = s0[11:0];
assign Y2 = s1[23:12];
assign Y3 = s1[11:0];
perm46095 instPerm46360(.x0(t0), .y0(s0),
.x1(t1), .y1(s1),
.clk(clk), .next(next), .next_out(next_out), .reset(reset)
);
endmodule |
module perm46095(clk, next, reset, next_out,
x0, y0,
x1, y1);
parameter numBanks = 2;
parameter logBanks = 1;
parameter depth = 1024;
parameter logDepth = 10;
parameter width = 24;
input [width-1:0] x0;
output [width-1:0] y0;
wire [width-1:0] ybuff0;
input [width-1:0] x1;
output [width-1:0] y1;
wire [width-1:0] ybuff1;
input clk, next, reset;
output next_out;
wire next0;
reg inFlip0, outFlip0;
reg inActive, outActive;
wire [logBanks-1:0] inBank0, outBank0;
wire [logDepth-1:0] inAddr0, outAddr0;
wire [logBanks-1:0] outBank_a0;
wire [logDepth-1:0] outAddr_a0;
wire [logDepth+logBanks-1:0] addr0, addr0b, addr0c;
wire [logBanks-1:0] inBank1, outBank1;
wire [logDepth-1:0] inAddr1, outAddr1;
wire [logBanks-1:0] outBank_a1;
wire [logDepth-1:0] outAddr_a1;
wire [logDepth+logBanks-1:0] addr1, addr1b, addr1c;
reg [logDepth-1:0] inCount, outCount, outCount_d, outCount_dd, outCount_for_rd_addr, outCount_for_rd_data;
assign addr0 = {inCount, 1'd0};
assign addr0b = {outCount, 1'd0};
assign addr0c = {outCount_for_rd_addr, 1'd0};
assign addr1 = {inCount, 1'd1};
assign addr1b = {outCount, 1'd1};
assign addr1c = {outCount_for_rd_addr, 1'd1};
wire [width+logDepth-1:0] w_0_0, w_0_1, w_1_0, w_1_1;
reg [width-1:0] z_0_0;
reg [width-1:0] z_0_1;
wire [width-1:0] z_1_0, z_1_1;
wire [logDepth-1:0] u_0_0, u_0_1, u_1_0, u_1_1;
always @(posedge clk) begin
end
assign inBank0[0] = addr0[1] ^ addr0[0];
assign inAddr0[0] = addr0[2];
assign inAddr0[1] = addr0[3];
assign inAddr0[2] = addr0[4];
assign inAddr0[3] = addr0[5];
assign inAddr0[4] = addr0[6];
assign inAddr0[5] = addr0[7];
assign inAddr0[6] = addr0[8];
assign inAddr0[7] = addr0[9];
assign inAddr0[8] = addr0[10];
assign inAddr0[9] = addr0[0];
assign outBank0[0] = addr0b[10] ^ addr0b[0];
assign outAddr0[0] = addr0b[1];
assign outAddr0[1] = addr0b[2];
assign outAddr0[2] = addr0b[3];
assign outAddr0[3] = addr0b[4];
assign outAddr0[4] = addr0b[5];
assign outAddr0[5] = addr0b[6];
assign outAddr0[6] = addr0b[7];
assign outAddr0[7] = addr0b[8];
assign outAddr0[8] = addr0b[9];
assign outAddr0[9] = addr0b[10];
assign outBank_a0[0] = addr0c[10] ^ addr0c[0];
assign outAddr_a0[0] = addr0c[1];
assign outAddr_a0[1] = addr0c[2];
assign outAddr_a0[2] = addr0c[3];
assign outAddr_a0[3] = addr0c[4];
assign outAddr_a0[4] = addr0c[5];
assign outAddr_a0[5] = addr0c[6];
assign outAddr_a0[6] = addr0c[7];
assign outAddr_a0[7] = addr0c[8];
assign outAddr_a0[8] = addr0c[9];
assign outAddr_a0[9] = addr0c[10];
assign inBank1[0] = addr1[1] ^ addr1[0];
assign inAddr1[0] = addr1[2];
assign inAddr1[1] = addr1[3];
assign inAddr1[2] = addr1[4];
assign inAddr1[3] = addr1[5];
assign inAddr1[4] = addr1[6];
assign inAddr1[5] = addr1[7];
assign inAddr1[6] = addr1[8];
assign inAddr1[7] = addr1[9];
assign inAddr1[8] = addr1[10];
assign inAddr1[9] = addr1[0];
assign outBank1[0] = addr1b[10] ^ addr1b[0];
assign outAddr1[0] = addr1b[1];
assign outAddr1[1] = addr1b[2];
assign outAddr1[2] = addr1b[3];
assign outAddr1[3] = addr1b[4];
assign outAddr1[4] = addr1b[5];
assign outAddr1[5] = addr1b[6];
assign outAddr1[6] = addr1b[7];
assign outAddr1[7] = addr1b[8];
assign outAddr1[8] = addr1b[9];
assign outAddr1[9] = addr1b[10];
assign outBank_a1[0] = addr1c[10] ^ addr1c[0];
assign outAddr_a1[0] = addr1c[1];
assign outAddr_a1[1] = addr1c[2];
assign outAddr_a1[2] = addr1c[3];
assign outAddr_a1[3] = addr1c[4];
assign outAddr_a1[4] = addr1c[5];
assign outAddr_a1[5] = addr1c[6];
assign outAddr_a1[6] = addr1c[7];
assign outAddr_a1[7] = addr1c[8];
assign outAddr_a1[8] = addr1c[9];
assign outAddr_a1[9] = addr1c[10];
nextReg #(1010, 10) nextReg_46365(.X(next), .Y(next0), .reset(reset), .clk(clk));
shiftRegFIFO #(2, 1) shiftFIFO_46368(.X(next0), .Y(next_out), .clk(clk));
memArray2048_46095 #(numBanks, logBanks, depth, logDepth, width)
memSys(.inFlip(inFlip0), .outFlip(outFlip0), .next(next), .reset(reset),
.x0(w_1_0[width+logDepth-1:logDepth]), .y0(ybuff0),
.inAddr0(w_1_0[logDepth-1:0]),
.outAddr0(u_1_0),
.x1(w_1_1[width+logDepth-1:logDepth]), .y1(ybuff1),
.inAddr1(w_1_1[logDepth-1:0]),
.outAddr1(u_1_1),
.clk(clk));
always @(posedge clk) begin
if (reset == 1) begin
z_0_0 <= 0;
z_0_1 <= 0;
inFlip0 <= 0; outFlip0 <= 1; outCount <= 0; inCount <= 0;
outCount_for_rd_addr <= 0;
outCount_for_rd_data <= 0;
end
else begin
outCount_d <= outCount;
outCount_dd <= outCount_d;
if (inCount == 1009)
outCount_for_rd_addr <= 0;
else
outCount_for_rd_addr <= outCount_for_rd_addr+1;
if (inCount == 1011)
outCount_for_rd_data <= 0;
else
outCount_for_rd_data <= outCount_for_rd_data+1;
z_0_0 <= ybuff0;
z_0_1 <= ybuff1;
if (inCount == 1009) begin
outFlip0 <= ~outFlip0;
outCount <= 0;
end
else
outCount <= outCount+1;
if (inCount == 1023) begin
inFlip0 <= ~inFlip0;
end
if (next == 1) begin
if (inCount >= 1009)
inFlip0 <= ~inFlip0;
inCount <= 0;
end
else
inCount <= inCount + 1;
end
end
assign w_0_0 = {x0, inAddr0};
assign w_0_1 = {x1, inAddr1};
assign y0 = z_1_0;
assign y1 = z_1_1;
assign u_0_0 = outAddr_a0;
assign u_0_1 = outAddr_a1;
wire wr_ctrl_st_0;
assign wr_ctrl_st_0 = inCount[0];
switch #(logDepth+width) in_sw_0_0(.x0(w_0_0), .x1(w_0_1), .y0(w_1_0), .y1(w_1_1), .ctrl(wr_ctrl_st_0));
wire rdd_ctrl_st_0;
assign rdd_ctrl_st_0 = outCount_for_rd_data[9];
switch #(width) out_sw_0_0(.x0(z_0_0), .x1(z_0_1), .y0(z_1_0), .y1(z_1_1), .ctrl(rdd_ctrl_st_0));
wire rda_ctrl_st_0;
assign rda_ctrl_st_0 = outCount_for_rd_addr[9];
switch #(logDepth) rdaddr_sw_0_0(.x0(u_0_0), .x1(u_0_1), .y0(u_1_0), .y1(u_1_1), .ctrl(rda_ctrl_st_0));
endmodule |
module memArray2048_46095(next, reset,
x0, y0,
inAddr0,
outAddr0,
x1, y1,
inAddr1,
outAddr1,
clk, inFlip, outFlip);
parameter numBanks = 2;
parameter logBanks = 1;
parameter depth = 1024;
parameter logDepth = 10;
parameter width = 24;
input clk, next, reset;
input inFlip, outFlip;
wire next0;
input [width-1:0] x0;
output [width-1:0] y0;
input [logDepth-1:0] inAddr0, outAddr0;
input [width-1:0] x1;
output [width-1:0] y1;
input [logDepth-1:0] inAddr1, outAddr1;
nextReg #(1024, 10) nextReg_46373(.X(next), .Y(next0), .reset(reset), .clk(clk));
memMod #(depth*2, width, logDepth+1)
memMod0(.in(x0), .out(y0), .inAddr({inFlip, inAddr0}),
.outAddr({outFlip, outAddr0}), .writeSel(1'b1), .clk(clk));
memMod #(depth*2, width, logDepth+1)
memMod1(.in(x1), .out(y1), .inAddr({inFlip, inAddr1}),
.outAddr({outFlip, outAddr1}), .writeSel(1'b1), .clk(clk));
endmodule |
module multfix(clk, rst, a, b, q_sc, q_unsc);
parameter WIDTH=35, CYCLES=6;
input signed [WIDTH-1:0] a,b;
output [WIDTH-1:0] q_sc;
output [WIDTH-1:0] q_unsc;
input clk, rst;
reg signed [2*WIDTH-1:0] q[CYCLES-1:0];
wire signed [2*WIDTH-1:0] res;
integer i;
assign res = q[CYCLES-1];
assign q_unsc = res[WIDTH-1:0];
assign q_sc = {res[2*WIDTH-1], res[2*WIDTH-4:WIDTH-2]};
always @(posedge clk) begin
q[0] <= a * b;
for (i = 1; i < CYCLES; i=i+1) begin
q[i] <= q[i-1];
end
end
endmodule |
module addfxp(a, b, q, clk);
parameter width = 16, cycles=1;
input signed [width-1:0] a, b;
input clk;
output signed [width-1:0] q;
reg signed [width-1:0] res[cycles-1:0];
assign q = res[cycles-1];
integer i;
always @(posedge clk) begin
res[0] <= a+b;
for (i=1; i < cycles; i = i+1)
res[i] <= res[i-1];
end
endmodule |
module subfxp(a, b, q, clk);
parameter width = 16, cycles=1;
input signed [width-1:0] a, b;
input clk;
output signed [width-1:0] q;
reg signed [width-1:0] res[cycles-1:0];
assign q = res[cycles-1];
integer i;
always @(posedge clk) begin
res[0] <= a-b;
for (i=1; i < cycles; i = i+1)
res[i] <= res[i-1];
end
endmodule |
module T_uxa_ps2_shfreg;
// Inputs
reg ps2_d_i;
reg ps2_c_i;
reg reset_i;
reg sys_clk_i;
// Outputs
wire [7:0] d_o;
wire frame_o;
// Instantiate the Unit Under Test (UUT)
M_uxa_ps2_shfreg uut (
.ps2_d_i(ps2_d_i),
.ps2_c_i(ps2_c_i),
.d_o(d_o),
.frame_o(frame_o),
.reset_i(reset_i),
.sys_clk_i(sys_clk_i)
);
always begin
#40 sys_clk_i <= 1;
#40 sys_clk_i <= 0;
end
initial begin
// Initialize Inputs
ps2_d_i = 1;
ps2_c_i = 1;
reset_i = 1;
sys_clk_i = 0;
#80 reset_i = 0;
#50000 ps2_d_i = 0; ps2_c_i = 0;
#50000 ps2_c_i = 1;
#50000 ps2_d_i = 0; ps2_c_i = 0;
#50000 ps2_c_i = 1;
#50000 ps2_d_i = 0; ps2_c_i = 0;
#50000 ps2_c_i = 1;
#50000 ps2_d_i = 1; ps2_c_i = 0;
#50000 ps2_c_i = 1;
#50000 ps2_d_i = 0; ps2_c_i = 0;
#50000 ps2_c_i = 1;
#50000 ps2_d_i = 0; ps2_c_i = 0;
#50000 ps2_c_i = 1;
#50000 ps2_d_i = 1; ps2_c_i = 0;
#50000 ps2_c_i = 1;
#50000 ps2_d_i = 1; ps2_c_i = 0;
#50000 ps2_c_i = 1;
#50000 ps2_d_i = 0; ps2_c_i = 0;
#50000 ps2_c_i = 1;
#50000 ps2_d_i = 1; ps2_c_i = 0;
#50000 ps2_c_i = 1;
#50000 ps2_d_i = 1; ps2_c_i = 0;
#50000 ps2_c_i = 1;
#320 ;
if(d_o != 8'b01100100) begin
$display("Deserializer failed to grab byte correctly.");
$stop;
end
if(frame_o != 1) begin
$display("Deserializer failed to sync to the PS/2 frame.");
$stop;
end
reset_i = 1;
#80 reset_i = 0;
if(d_o != 8'b11111111) begin
$display("Deserializer didn't reset when instructed.");
$stop;
end
if(frame_o != 0) begin
$display("Frame indicator didn't reset when instructed.");
$stop;
end
end
endmodule |
module analinput(clk, pay, pby, miso, mosi, cs, sck);
parameter PADDLESIZE = 0;
parameter SCREENHEIGHT = 0;
input clk;
output reg[9:0] pay;
output reg[9:0] pby;
input miso;
output reg mosi;
output reg cs;
output sck;
parameter state0 = 0, state1 = 1, state2 = 2, state3 = 3;
reg [1:0] state;
reg [4:0] sckcount;
reg [11:0] datain;
reg ab;
assign sck = clk;
always @(posedge sck) begin
case(state)
state0:
begin
ab <= 1;
state <= state1;
end
state1:
begin
ab <= !ab;
cs <= 0;
mosi <= !ab;
sckcount <= 15;
state <= state2;
end
state2:
begin
if (sckcount != 0)
sckcount <= sckcount - 1'b1;
else
state <= state3;
end
state3:
begin
cs <= 1;
mosi <= 0;
if (ab == 0) begin
pay <= paddlelimiter(datain[11:3]);
end else begin
pby <= paddlelimiter(datain[11:3]);
end
state <= state1;
end
default:
state <= state0;
endcase
end
always @(negedge sck) begin
if (state == state2)
datain <= (datain << 1) | miso;
else if (state == state1)
datain <= 0;
end
//
// Limit paddle position to stay within screen coordinates
//
function [9:0] paddlelimiter;
input [9:0] py;
begin
if (py < PADDLESIZE/2)
paddlelimiter = PADDLESIZE/2;
else
if (py > SCREENHEIGHT-96/2)
paddlelimiter = SCREENHEIGHT-PADDLESIZE/2;
else
paddlelimiter = py;
end
endfunction
endmodule |
module sky130_fd_sc_hd__o21a (
//# {{data|Data Signals}}
input A1,
input A2,
input B1,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule |
module sky130_fd_sc_hdll__a31o (
//# {{data|Data Signals}}
input A1,
input A2,
input A3,
input B1,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule |
module ExOp64_3B(
/* verilator lint_off UNUSED */
clock, reset,
opCmd, opStepPc,
regIdRs, regValRs,
regIdRt, regValRt,
regIdRn, regValRn,
immValRi, idInGenPc,
regOutId, regOutVal,
regOutOK, ctlInSr
);
input clock;
input reset;
input[7:0] opCmd; //command opcode
input[3:0] opStepPc;
input[63:0] idInGenPc; //ID's Next PC (Next Fetch)
input[6:0] regIdRs;
input[6:0] regIdRt;
input[6:0] regIdRn;
input[63:0] regValRs; //Rs input value
input[63:0] regValRt; //Rt input value
input[63:0] regValRn; //Rn input value
input[63:0] immValRi; //immediate/disp value
output[63:0] regOutVal; //Rn output value
output[6:0] regOutId; //Rn, value to write
output[1:0] regOutOK; //execute status
/* Special Registers */
input[63:0] ctlInSr; //SR in
// input[63:0] ctlInPr; //PR in
// input[63:0] ctlInPc; //PC in
// input[63:0] ctlInMach; //MACH:MACL in
// input[63:0] ctlInMacl; //MACH:MACL in
// output[63:0] ctlOutMach; //MACH:MACL out
// output[63:0] ctlOutMacl; //MACH:MACL out
/* Temporary */
reg[63:0] tRegOutVal; //Rn, output value
reg[6:0] tRegOutId; //Rn, output register
reg[1:0] tRegOutOK; //execute status
/* verilator lint_off UNOPTFLAT */
reg[63:0] tAguRtRi; //AGU Rt+Ri
reg[63:0] tAguRtRiSc; //AGU (Rt+Ri)*Sc
reg[63:0] tAguAddr; //AGU Address
/* verilator lint_on UNOPTFLAT */
assign regOutVal = tRegOutVal;
assign regOutId = tRegOutId;
assign regOutOK = tRegOutOK;
reg tInAluC;
reg tOutAluC;
reg tTriggerExc;
/*
reg[63:0] tShadValRs;
reg[ 7:0] tShadValRt;
wire[63:0] tShadValRn;
reg[ 2:0] tShadOp;
ExShad64 sh64(
clock, reset,
tShadValRs, tShadValRt,
tShadValRn, tShadOp);
*/
reg[64:0] tAluDn1;
reg[64:0] tAluDn2;
reg tAluQ0;
reg tAluM0;
reg tAluT0;
reg tAluQ1;
reg tAluM1;
reg tAluT1;
reg tAluQ2;
reg tAluM2;
reg tAluT2;
/* EX */
always @*
begin
tRegOutVal=0;
tRegOutId=UREG_ZZR;
tRegOutOK=UMEM_OK_OK;
tInAluC=1'bX;
tOutAluC=1'bX;
// tMacValRs=64'hX;
// tMacValRt=64'hX;
// tMacValRu=64'hX;
// tMacOp=0;
// tShadValRs=32'hXXXXXXXX;
// tShadValRt=8'hXX;
// tShadOp=0;
tTriggerExc=0;
// tCtlNxtPc=ctlInPc+{28'h0, opStepPc};
// tCtlPrPc=tCtlNxtPc + 2;
// tCtlBraPc=tCtlPrPc + (immValRi<<1);
/*
tAguRtRi=regValRt+immValRi;
if(regIdRt==UREG_R0)
begin
tAguAddr=opCmd[2]?
(regValRs+tAguRtRi):
(regValRn+tAguRtRi);
end
else
begin
case(opCmd[2:0])
3'h0: tAguAddr=regValRn+tAguRtRi;
3'h1: tAguAddr=regValRn+(tAguRtRi<<1);
3'h2: tAguAddr=regValRn+(tAguRtRi<<2);
3'h3: tAguAddr=regValRn+(tAguRtRi<<3);
3'h4: tAguAddr=regValRs+tAguRtRi;
3'h5: tAguAddr=regValRs+(tAguRtRi<<1);
3'h6: tAguAddr=regValRs+(tAguRtRi<<2);
3'h7: tAguAddr=regValRs+(tAguRtRi<<3);
endcase
end
*/
/*
tAguRtRi=regValRt+immValRi;
case(opCmd[1:0])
2'h0: tAguRtRiSc=tAguRtRi;
2'h1: tAguRtRiSc={tAguRtRi[62:0], 1'b0};
2'h2: tAguRtRiSc={tAguRtRi[61:0], 2'b0};
2'h3: tAguRtRiSc={tAguRtRi[60:0], 3'b0};
endcase
tAguAddr=(opCmd[2]?regValRs:regValRn)+
((regIdRt==UREG_R0)?tAguRtRi:tAguRtRiSc);
*/
casez(opCmd)
UCMD_NONE: begin
end
UCMD_MOV_RR: begin
tRegOutVal=regValRs;
tRegOutId=regIdRn;
end
UCMD_MOV_RI: begin
tRegOutVal=immValRi;
tRegOutId=regIdRn;
end
/*
UCMD_LEAB_MR: begin
tRegOutVal=tAguAddr;
tRegOutId=regIdRn;
end
UCMD_LEAW_MR: begin
tRegOutVal=tAguAddr;
tRegOutId=regIdRn;
end
UCMD_LEAL_MR: begin
tRegOutVal=tAguAddr;
tRegOutId=regIdRn;
end
UCMD_LEAQ_MR: begin
tRegOutVal=tAguAddr;
tRegOutId=regIdRn;
end
*/
UCMD_ALU_ADD: begin
tRegOutVal=regValRs+regValRt;
tRegOutId=regIdRn;
end
UCMD_ALU_SUB: begin
tRegOutVal=regValRs-regValRt;
tRegOutId=regIdRn;
end
UCMD_ALU_MUL: begin
// tRegOutVal=regValRs*regValRt;
tRegOutId=regIdRn;
// tMacValRs = {32'h0, regValRs};
// tMacValRt = {32'h0, regValRt};
// tMacOp = 2'h3;
end
UCMD_ALU_AND: begin
tRegOutVal=regValRs®ValRt;
tRegOutId=regIdRn;
end
UCMD_ALU_OR: begin
tRegOutVal=regValRs|regValRt;
tRegOutId=regIdRn;
end
UCMD_ALU_XOR: begin
tRegOutVal=regValRs^regValRt;
tRegOutId=regIdRn;
end
UCMD_ALU_ADDC: begin
tInAluC=ctlInSr[0];
{tOutAluC, tRegOutVal}=
{ 1'b0, regValRs+regValRt}+
{64'h0, tInAluC};
// tCtlOutSr[0]=tOutAluC;
tRegOutId=regIdRn;
end
UCMD_ALU_SUBC: begin
tInAluC=ctlInSr[0];
{tOutAluC, tRegOutVal}=
{ 1'b0, regValRs-regValRt}-
{64'h0, tInAluC};
// tCtlOutSr[0]=tOutAluC;
tRegOutId=regIdRn;
end
UCMD_ALU_ADDV: begin
{tOutAluC, tRegOutVal}=
{ regValRs[63], regValRs}+
{ regValRt[63], regValRt};
// tCtlOutSr[0]=tOutAluC^tRegOutVal[31];
tRegOutId=regIdRn;
end
UCMD_ALU_SUBV: begin
{tOutAluC, tRegOutVal}=
{ regValRs[63], regValRs}-
{ regValRt[63], regValRt};
// tCtlOutSr[0]=tOutAluC^tRegOutVal[31];
tRegOutId=regIdRn;
end
/*
UCMD_ALU_SHAD: begin
tShadValRs=regValRs;
tShadOp=2;
tShadValRt=regValRt[7:0];
tRegOutId=regIdRn;
end
UCMD_ALU_SHLD: begin
tShadValRs=regValRs;
tShadOp=1;
tShadValRt=regValRt[7:0];
tRegOutId=regIdRn;
end
UCMD_ALU_SHADR: begin
tShadValRs=regValRs;
tShadOp=4;
tShadValRt=regValRt[7:0];
tRegOutId=regIdRn;
end
UCMD_ALU_SHLDR: begin
tShadValRs=regValRs;
tShadOp=3;
tShadValRt=regValRt[7:0];
tRegOutId=regIdRn;
end
*/
UCMD_ALU_LDSH16: begin
tRegOutVal={regValRs[47:0], 16'h0} +
regValRt;
tRegOutId=regIdRn;
end
UCMD_ALU_NOT: begin
tRegOutVal=~regValRs;
tRegOutId=regIdRn;
end
UCMD_ALU_SWAPB: begin
tRegOutVal={
regValRs[55:48],
regValRs[63:56],
regValRs[39:32],
regValRs[47:40],
regValRs[23:16],
regValRs[31:24],
regValRs[ 7: 0],
regValRs[15: 8]
};
tRegOutId=regIdRn;
end
UCMD_ALU_SWAPW: begin
tRegOutVal={
regValRs[47:32],
regValRs[63:48],
regValRs[15: 0],
regValRs[31:16]};
tRegOutId=regIdRn;
end
UCMD_ALU_EXTUB: begin
tRegOutVal={56'h0, regValRs[7:0]};
tRegOutId=regIdRn;
end
UCMD_ALU_EXTUW: begin
tRegOutVal={48'h0, regValRs[15:0]};
tRegOutId=regIdRn;
end
UCMD_ALU_EXTSB: begin
tRegOutVal={regValRs[7]?56'hFF_FFFF_FFFF_FFFF:56'h0, regValRs[7:0]};
tRegOutId=regIdRn;
end
UCMD_ALU_EXTSW: begin
tRegOutVal={regValRs[15]?48'hFFFF_FFFF_FFFF:48'h0, regValRs[15:0]};
tRegOutId=regIdRn;
end
UCMD_ALU_NEG: begin
tRegOutVal=-regValRs;
tRegOutId=regIdRn;
end
UCMD_ALU_NEGC: begin
{tOutAluC, tRegOutVal}=
{1'b1, ~regValRs}+
(ctlInSr[0] ? 65'h0 : 65'h1);
tRegOutId=regIdRn;
end
default: begin end
endcase
end
endmodule |
module TimeHoldOver_Qsys_nios2_gen2_0_cpu_debug_slave_sysclk (
// inputs:
clk,
ir_in,
sr,
vs_udr,
vs_uir,
// outputs:
jdo,
take_action_break_a,
take_action_break_b,
take_action_break_c,
take_action_ocimem_a,
take_action_ocimem_b,
take_action_tracectrl,
take_no_action_break_a,
take_no_action_break_b,
take_no_action_break_c,
take_no_action_ocimem_a
)
;
output [ 37: 0] jdo;
output take_action_break_a;
output take_action_break_b;
output take_action_break_c;
output take_action_ocimem_a;
output take_action_ocimem_b;
output take_action_tracectrl;
output take_no_action_break_a;
output take_no_action_break_b;
output take_no_action_break_c;
output take_no_action_ocimem_a;
input clk;
input [ 1: 0] ir_in;
input [ 37: 0] sr;
input vs_udr;
input vs_uir;
reg enable_action_strobe /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
reg [ 1: 0] ir /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
reg [ 37: 0] jdo /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
reg jxuir /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
reg sync2_udr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
reg sync2_uir /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
wire sync_udr;
wire sync_uir;
wire take_action_break_a;
wire take_action_break_b;
wire take_action_break_c;
wire take_action_ocimem_a;
wire take_action_ocimem_b;
wire take_action_tracectrl;
wire take_no_action_break_a;
wire take_no_action_break_b;
wire take_no_action_break_c;
wire take_no_action_ocimem_a;
wire unxunused_resetxx3;
wire unxunused_resetxx4;
reg update_jdo_strobe /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
assign unxunused_resetxx3 = 1'b1;
altera_std_synchronizer the_altera_std_synchronizer3
(
.clk (clk),
.din (vs_udr),
.dout (sync_udr),
.reset_n (unxunused_resetxx3)
);
defparam the_altera_std_synchronizer3.depth = 2;
assign unxunused_resetxx4 = 1'b1;
altera_std_synchronizer the_altera_std_synchronizer4
(
.clk (clk),
.din (vs_uir),
.dout (sync_uir),
.reset_n (unxunused_resetxx4)
);
defparam the_altera_std_synchronizer4.depth = 2;
always @(posedge clk)
begin
sync2_udr <= sync_udr;
update_jdo_strobe <= sync_udr & ~sync2_udr;
enable_action_strobe <= update_jdo_strobe;
sync2_uir <= sync_uir;
jxuir <= sync_uir & ~sync2_uir;
end
assign take_action_ocimem_a = enable_action_strobe && (ir == 2'b00) &&
~jdo[35] && jdo[34];
assign take_no_action_ocimem_a = enable_action_strobe && (ir == 2'b00) &&
~jdo[35] && ~jdo[34];
assign take_action_ocimem_b = enable_action_strobe && (ir == 2'b00) &&
jdo[35];
assign take_action_break_a = enable_action_strobe && (ir == 2'b10) &&
~jdo[36] &&
jdo[37];
assign take_no_action_break_a = enable_action_strobe && (ir == 2'b10) &&
~jdo[36] &&
~jdo[37];
assign take_action_break_b = enable_action_strobe && (ir == 2'b10) &&
jdo[36] && ~jdo[35] &&
jdo[37];
assign take_no_action_break_b = enable_action_strobe && (ir == 2'b10) &&
jdo[36] && ~jdo[35] &&
~jdo[37];
assign take_action_break_c = enable_action_strobe && (ir == 2'b10) &&
jdo[36] && jdo[35] &&
jdo[37];
assign take_no_action_break_c = enable_action_strobe && (ir == 2'b10) &&
jdo[36] && jdo[35] &&
~jdo[37];
assign take_action_tracectrl = enable_action_strobe && (ir == 2'b11) &&
jdo[15];
always @(posedge clk)
begin
if (jxuir)
ir <= ir_in;
if (update_jdo_strobe)
jdo <= sr;
end
endmodule |
module sky130_fd_sc_hs__sdfxbp (
CLK ,
D ,
Q ,
Q_N ,
SCD ,
SCE ,
VPWR,
VGND
);
input CLK ;
input D ;
output Q ;
output Q_N ;
input SCD ;
input SCE ;
input VPWR;
input VGND;
endmodule |
module main (
// Clk Input
input clk_in,
// Data Pins
output reset,
output sclk, // Half the speed of data_clk, a 20,000th the speed of clk
output sdata,
output scmd,
// Power Pins
output vbat,
output vdd,
// LED String Data Pins
output status_led,
output light_clk,
output light_data
);
// GPIO OUT MAP
// 0 - VDD
// 1 - VBAT
// 2 - RESET
// 3 - SCLK
// 4 - SDATA
// 5 - SCMD
//wire [31 : 0] gpio;
zynq_1_wrapper cpu();
assign vdd = 0;
assign vbat = 0;
assign reset = 0;
assign sclk = 0;
assign sdata = 0;
assign scmd = 0;
//assign status_led = gpio[6];
assign light_clk = 0;
assign light_data = 0;
assign status_led = 1;
wire clk;
IBUFG clk_buf(.I(clk_in), .O(clk)); // Clock Buffer Conversion
endmodule |
module ALU_CONTROL(input [5:0] funct, input [1:0] alu_op, output reg [2:0] select);
always @ *
begin
case (alu_op)
2'b00:
begin
select <= 3'b010; // LW / SW
end
2'b01:
begin
select <= 3'b110; // BRE
end
2'b10:
begin
case (funct)
6'b100000:
begin
select <= 3'b010; // R add
end
6'b100010:
begin
select <= 3'b110; // R sub
end
6'b100100:
begin
select <= 3'b000; // R and
end
6'b100101:
begin
select <= 3'b001; // R or
end
6'b101010:
begin
select <= 3'b111; // R slt
end
endcase
end
2'b11:
begin
select <= 3'b011; // Invalid input
end
endcase
end
endmodule |
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_GPIO_Core
(ip2bus_data,
GPIO_xferAck_i,
gpio_xferAck_Reg,
GPIO_intr,
Q,
gpio_io_o,
gpio_io_t,
Read_Reg_Rst,
\Not_Dual.gpio_OE_reg[7]_0 ,
s_axi_aclk,
\Not_Dual.gpio_OE_reg[6]_0 ,
\Not_Dual.gpio_OE_reg[5]_0 ,
\Not_Dual.gpio_OE_reg[4]_0 ,
\Not_Dual.gpio_OE_reg[3]_0 ,
\Not_Dual.gpio_OE_reg[2]_0 ,
\Not_Dual.gpio_OE_reg[1]_0 ,
GPIO_DBus_i,
bus2ip_reset,
bus2ip_cs,
gpio_io_i,
E,
D,
bus2ip_rnw_i_reg);
output [7:0]ip2bus_data;
output GPIO_xferAck_i;
output gpio_xferAck_Reg;
output GPIO_intr;
output [7:0]Q;
output [7:0]gpio_io_o;
output [7:0]gpio_io_t;
input Read_Reg_Rst;
input \Not_Dual.gpio_OE_reg[7]_0 ;
input s_axi_aclk;
input \Not_Dual.gpio_OE_reg[6]_0 ;
input \Not_Dual.gpio_OE_reg[5]_0 ;
input \Not_Dual.gpio_OE_reg[4]_0 ;
input \Not_Dual.gpio_OE_reg[3]_0 ;
input \Not_Dual.gpio_OE_reg[2]_0 ;
input \Not_Dual.gpio_OE_reg[1]_0 ;
input [0:0]GPIO_DBus_i;
input bus2ip_reset;
input [0:0]bus2ip_cs;
input [7:0]gpio_io_i;
input [0:0]E;
input [7:0]D;
input [0:0]bus2ip_rnw_i_reg;
wire [7:0]D;
wire [0:0]E;
wire [0:0]GPIO_DBus_i;
wire GPIO_intr;
wire GPIO_xferAck_i;
wire \Not_Dual.GEN_INTERRUPT.GPIO_intr_i_2_n_0 ;
wire \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg_n_0_[0] ;
wire \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg_n_0_[1] ;
wire \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg_n_0_[7] ;
wire \Not_Dual.gpio_OE_reg[1]_0 ;
wire \Not_Dual.gpio_OE_reg[2]_0 ;
wire \Not_Dual.gpio_OE_reg[3]_0 ;
wire \Not_Dual.gpio_OE_reg[4]_0 ;
wire \Not_Dual.gpio_OE_reg[5]_0 ;
wire \Not_Dual.gpio_OE_reg[6]_0 ;
wire \Not_Dual.gpio_OE_reg[7]_0 ;
wire [7:0]Q;
wire Read_Reg_Rst;
wire [0:0]bus2ip_cs;
wire bus2ip_reset;
wire [0:0]bus2ip_rnw_i_reg;
wire [0:7]gpio_data_in_xor;
wire [7:0]gpio_io_i;
wire [0:7]gpio_io_i_d2;
wire [7:0]gpio_io_o;
wire [7:0]gpio_io_t;
wire gpio_xferAck_Reg;
wire iGPIO_xferAck;
wire [7:0]ip2bus_data;
wire or_ints;
wire p_1_in;
wire p_2_in;
wire p_3_in;
wire p_4_in;
wire p_5_in;
wire s_axi_aclk;
LUT5 #(
.INIT(32'hFFFFFFFE))
\Not_Dual.GEN_INTERRUPT.GPIO_intr_i_1
(.I0(p_2_in),
.I1(p_3_in),
.I2(p_1_in),
.I3(\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg_n_0_[1] ),
.I4(\Not_Dual.GEN_INTERRUPT.GPIO_intr_i_2_n_0 ),
.O(or_ints));
LUT4 #(
.INIT(16'hFFFE))
\Not_Dual.GEN_INTERRUPT.GPIO_intr_i_2
(.I0(p_5_in),
.I1(p_4_in),
.I2(\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg_n_0_[0] ),
.I3(\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg_n_0_[7] ),
.O(\Not_Dual.GEN_INTERRUPT.GPIO_intr_i_2_n_0 ));
FDRE \Not_Dual.GEN_INTERRUPT.GPIO_intr_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(or_ints),
.Q(GPIO_intr),
.R(bus2ip_reset));
FDRE \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg[0]
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_data_in_xor[0]),
.Q(\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg_n_0_[0] ),
.R(bus2ip_reset));
FDRE \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg[1]
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_data_in_xor[1]),
.Q(\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg_n_0_[1] ),
.R(bus2ip_reset));
FDRE \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg[2]
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_data_in_xor[2]),
.Q(p_1_in),
.R(bus2ip_reset));
FDRE \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg[3]
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_data_in_xor[3]),
.Q(p_2_in),
.R(bus2ip_reset));
FDRE \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg[4]
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_data_in_xor[4]),
.Q(p_3_in),
.R(bus2ip_reset));
FDRE \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg[5]
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_data_in_xor[5]),
.Q(p_4_in),
.R(bus2ip_reset));
FDRE \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg[6]
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_data_in_xor[6]),
.Q(p_5_in),
.R(bus2ip_reset));
FDRE \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg[7]
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_data_in_xor[7]),
.Q(\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg_n_0_[7] ),
.R(bus2ip_reset));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync \Not_Dual.INPUT_DOUBLE_REGS3
(.D({gpio_data_in_xor[0],gpio_data_in_xor[1],gpio_data_in_xor[2],gpio_data_in_xor[3],gpio_data_in_xor[4],gpio_data_in_xor[5],gpio_data_in_xor[6],gpio_data_in_xor[7]}),
.Q(Q),
.gpio_io_i(gpio_io_i),
.s_axi_aclk(s_axi_aclk),
.scndry_vect_out({gpio_io_i_d2[0],gpio_io_i_d2[1],gpio_io_i_d2[2],gpio_io_i_d2[3],gpio_io_i_d2[4],gpio_io_i_d2[5],gpio_io_i_d2[6],gpio_io_i_d2[7]}));
FDRE \Not_Dual.READ_REG_GEN[0].GPIO_DBus_i_reg[24]
(.C(s_axi_aclk),
.CE(1'b1),
.D(GPIO_DBus_i),
.Q(ip2bus_data[7]),
.R(Read_Reg_Rst));
FDRE \Not_Dual.READ_REG_GEN[1].GPIO_DBus_i_reg[25]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\Not_Dual.gpio_OE_reg[1]_0 ),
.Q(ip2bus_data[6]),
.R(Read_Reg_Rst));
FDRE \Not_Dual.READ_REG_GEN[2].GPIO_DBus_i_reg[26]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\Not_Dual.gpio_OE_reg[2]_0 ),
.Q(ip2bus_data[5]),
.R(Read_Reg_Rst));
FDRE \Not_Dual.READ_REG_GEN[3].GPIO_DBus_i_reg[27]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\Not_Dual.gpio_OE_reg[3]_0 ),
.Q(ip2bus_data[4]),
.R(Read_Reg_Rst));
FDRE \Not_Dual.READ_REG_GEN[4].GPIO_DBus_i_reg[28]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\Not_Dual.gpio_OE_reg[4]_0 ),
.Q(ip2bus_data[3]),
.R(Read_Reg_Rst));
FDRE \Not_Dual.READ_REG_GEN[5].GPIO_DBus_i_reg[29]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\Not_Dual.gpio_OE_reg[5]_0 ),
.Q(ip2bus_data[2]),
.R(Read_Reg_Rst));
FDRE \Not_Dual.READ_REG_GEN[6].GPIO_DBus_i_reg[30]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\Not_Dual.gpio_OE_reg[6]_0 ),
.Q(ip2bus_data[1]),
.R(Read_Reg_Rst));
FDRE \Not_Dual.READ_REG_GEN[7].GPIO_DBus_i_reg[31]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\Not_Dual.gpio_OE_reg[7]_0 ),
.Q(ip2bus_data[0]),
.R(Read_Reg_Rst));
FDRE \Not_Dual.gpio_Data_In_reg[0]
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_io_i_d2[0]),
.Q(Q[7]),
.R(1'b0));
FDRE \Not_Dual.gpio_Data_In_reg[1]
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_io_i_d2[1]),
.Q(Q[6]),
.R(1'b0));
FDRE \Not_Dual.gpio_Data_In_reg[2]
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_io_i_d2[2]),
.Q(Q[5]),
.R(1'b0));
FDRE \Not_Dual.gpio_Data_In_reg[3]
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_io_i_d2[3]),
.Q(Q[4]),
.R(1'b0));
FDRE \Not_Dual.gpio_Data_In_reg[4]
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_io_i_d2[4]),
.Q(Q[3]),
.R(1'b0));
FDRE \Not_Dual.gpio_Data_In_reg[5]
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_io_i_d2[5]),
.Q(Q[2]),
.R(1'b0));
FDRE \Not_Dual.gpio_Data_In_reg[6]
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_io_i_d2[6]),
.Q(Q[1]),
.R(1'b0));
FDRE \Not_Dual.gpio_Data_In_reg[7]
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_io_i_d2[7]),
.Q(Q[0]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Not_Dual.gpio_Data_Out_reg[0]
(.C(s_axi_aclk),
.CE(E),
.D(D[7]),
.Q(gpio_io_o[7]),
.R(bus2ip_reset));
FDRE #(
.INIT(1'b0))
\Not_Dual.gpio_Data_Out_reg[1]
(.C(s_axi_aclk),
.CE(E),
.D(D[6]),
.Q(gpio_io_o[6]),
.R(bus2ip_reset));
FDRE #(
.INIT(1'b0))
\Not_Dual.gpio_Data_Out_reg[2]
(.C(s_axi_aclk),
.CE(E),
.D(D[5]),
.Q(gpio_io_o[5]),
.R(bus2ip_reset));
FDRE #(
.INIT(1'b0))
\Not_Dual.gpio_Data_Out_reg[3]
(.C(s_axi_aclk),
.CE(E),
.D(D[4]),
.Q(gpio_io_o[4]),
.R(bus2ip_reset));
FDRE #(
.INIT(1'b0))
\Not_Dual.gpio_Data_Out_reg[4]
(.C(s_axi_aclk),
.CE(E),
.D(D[3]),
.Q(gpio_io_o[3]),
.R(bus2ip_reset));
FDRE #(
.INIT(1'b0))
\Not_Dual.gpio_Data_Out_reg[5]
(.C(s_axi_aclk),
.CE(E),
.D(D[2]),
.Q(gpio_io_o[2]),
.R(bus2ip_reset));
FDRE #(
.INIT(1'b0))
\Not_Dual.gpio_Data_Out_reg[6]
(.C(s_axi_aclk),
.CE(E),
.D(D[1]),
.Q(gpio_io_o[1]),
.R(bus2ip_reset));
FDRE #(
.INIT(1'b0))
\Not_Dual.gpio_Data_Out_reg[7]
(.C(s_axi_aclk),
.CE(E),
.D(D[0]),
.Q(gpio_io_o[0]),
.R(bus2ip_reset));
FDSE #(
.INIT(1'b1))
\Not_Dual.gpio_OE_reg[0]
(.C(s_axi_aclk),
.CE(bus2ip_rnw_i_reg),
.D(D[7]),
.Q(gpio_io_t[7]),
.S(bus2ip_reset));
FDSE #(
.INIT(1'b1))
\Not_Dual.gpio_OE_reg[1]
(.C(s_axi_aclk),
.CE(bus2ip_rnw_i_reg),
.D(D[6]),
.Q(gpio_io_t[6]),
.S(bus2ip_reset));
FDSE #(
.INIT(1'b1))
\Not_Dual.gpio_OE_reg[2]
(.C(s_axi_aclk),
.CE(bus2ip_rnw_i_reg),
.D(D[5]),
.Q(gpio_io_t[5]),
.S(bus2ip_reset));
FDSE #(
.INIT(1'b1))
\Not_Dual.gpio_OE_reg[3]
(.C(s_axi_aclk),
.CE(bus2ip_rnw_i_reg),
.D(D[4]),
.Q(gpio_io_t[4]),
.S(bus2ip_reset));
FDSE #(
.INIT(1'b1))
\Not_Dual.gpio_OE_reg[4]
(.C(s_axi_aclk),
.CE(bus2ip_rnw_i_reg),
.D(D[3]),
.Q(gpio_io_t[3]),
.S(bus2ip_reset));
FDSE #(
.INIT(1'b1))
\Not_Dual.gpio_OE_reg[5]
(.C(s_axi_aclk),
.CE(bus2ip_rnw_i_reg),
.D(D[2]),
.Q(gpio_io_t[2]),
.S(bus2ip_reset));
FDSE #(
.INIT(1'b1))
\Not_Dual.gpio_OE_reg[6]
(.C(s_axi_aclk),
.CE(bus2ip_rnw_i_reg),
.D(D[1]),
.Q(gpio_io_t[1]),
.S(bus2ip_reset));
FDSE #(
.INIT(1'b1))
\Not_Dual.gpio_OE_reg[7]
(.C(s_axi_aclk),
.CE(bus2ip_rnw_i_reg),
.D(D[0]),
.Q(gpio_io_t[0]),
.S(bus2ip_reset));
FDRE gpio_xferAck_Reg_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(GPIO_xferAck_i),
.Q(gpio_xferAck_Reg),
.R(bus2ip_reset));
LUT3 #(
.INIT(8'h10))
iGPIO_xferAck_i_1
(.I0(gpio_xferAck_Reg),
.I1(GPIO_xferAck_i),
.I2(bus2ip_cs),
.O(iGPIO_xferAck));
FDRE iGPIO_xferAck_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(iGPIO_xferAck),
.Q(GPIO_xferAck_i),
.R(bus2ip_reset));
endmodule |
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_address_decoder
(\ip2bus_data_i_D1_reg[0] ,
\Not_Dual.gpio_Data_Out_reg[7] ,
\ip_irpt_enable_reg_reg[0] ,
s_axi_arready,
s_axi_wready,
D,
\Not_Dual.READ_REG_GEN[7].GPIO_DBus_i_reg[31] ,
\Not_Dual.READ_REG_GEN[6].GPIO_DBus_i_reg[30] ,
\Not_Dual.READ_REG_GEN[5].GPIO_DBus_i_reg[29] ,
\Not_Dual.READ_REG_GEN[4].GPIO_DBus_i_reg[28] ,
\Not_Dual.READ_REG_GEN[3].GPIO_DBus_i_reg[27] ,
\Not_Dual.READ_REG_GEN[2].GPIO_DBus_i_reg[26] ,
\Not_Dual.READ_REG_GEN[1].GPIO_DBus_i_reg[25] ,
GPIO_DBus_i,
E,
\Not_Dual.gpio_Data_Out_reg[0] ,
\ip2bus_data_i_D1_reg[0]_0 ,
intr2bus_rdack0,
irpt_rdack,
irpt_wrack,
interrupt_wrce_strb,
Read_Reg_Rst,
\INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_reg ,
intr_rd_ce_or_reduce,
\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_reg ,
intr_wr_ce_or_reduce,
\ip_irpt_enable_reg_reg[0]_0 ,
ipif_glbl_irpt_enable_reg_reg,
start2,
s_axi_aclk,
s_axi_aresetn,
Q,
is_read,
ip2bus_rdack_i_D1,
is_write_reg,
ip2bus_wrack_i_D1,
s_axi_wdata,
\bus2ip_addr_i_reg[8] ,
gpio_io_t,
\Not_Dual.gpio_Data_In_reg[0] ,
bus2ip_rnw_i_reg,
bus2ip_reset,
p_0_in,
irpt_rdack_d1,
irpt_wrack_d1,
ip2bus_data,
p_3_in,
p_1_in,
GPIO_xferAck_i,
gpio_xferAck_Reg,
ip2Bus_RdAck_intr_reg_hole_d1,
ip2Bus_WrAck_intr_reg_hole_d1);
output \ip2bus_data_i_D1_reg[0] ;
output \Not_Dual.gpio_Data_Out_reg[7] ;
output \ip_irpt_enable_reg_reg[0] ;
output s_axi_arready;
output s_axi_wready;
output [7:0]D;
output \Not_Dual.READ_REG_GEN[7].GPIO_DBus_i_reg[31] ;
output \Not_Dual.READ_REG_GEN[6].GPIO_DBus_i_reg[30] ;
output \Not_Dual.READ_REG_GEN[5].GPIO_DBus_i_reg[29] ;
output \Not_Dual.READ_REG_GEN[4].GPIO_DBus_i_reg[28] ;
output \Not_Dual.READ_REG_GEN[3].GPIO_DBus_i_reg[27] ;
output \Not_Dual.READ_REG_GEN[2].GPIO_DBus_i_reg[26] ;
output \Not_Dual.READ_REG_GEN[1].GPIO_DBus_i_reg[25] ;
output [0:0]GPIO_DBus_i;
output [0:0]E;
output [0:0]\Not_Dual.gpio_Data_Out_reg[0] ;
output [1:0]\ip2bus_data_i_D1_reg[0]_0 ;
output intr2bus_rdack0;
output irpt_rdack;
output irpt_wrack;
output interrupt_wrce_strb;
output Read_Reg_Rst;
output \INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_reg ;
output intr_rd_ce_or_reduce;
output \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_reg ;
output intr_wr_ce_or_reduce;
output \ip_irpt_enable_reg_reg[0]_0 ;
output ipif_glbl_irpt_enable_reg_reg;
input start2;
input s_axi_aclk;
input s_axi_aresetn;
input [3:0]Q;
input is_read;
input ip2bus_rdack_i_D1;
input is_write_reg;
input ip2bus_wrack_i_D1;
input [15:0]s_axi_wdata;
input [6:0]\bus2ip_addr_i_reg[8] ;
input [7:0]gpio_io_t;
input [7:0]\Not_Dual.gpio_Data_In_reg[0] ;
input bus2ip_rnw_i_reg;
input bus2ip_reset;
input [0:0]p_0_in;
input irpt_rdack_d1;
input irpt_wrack_d1;
input [0:0]ip2bus_data;
input [0:0]p_3_in;
input [0:0]p_1_in;
input GPIO_xferAck_i;
input gpio_xferAck_Reg;
input ip2Bus_RdAck_intr_reg_hole_d1;
input ip2Bus_WrAck_intr_reg_hole_d1;
wire Bus_RNW_reg_i_1_n_0;
wire [7:0]D;
wire [0:0]E;
wire \GEN_BKEND_CE_REGISTERS[16].ce_out_i[16]_i_1_n_0 ;
wire \GEN_BKEND_CE_REGISTERS[17].ce_out_i[17]_i_1_n_0 ;
wire \GEN_BKEND_CE_REGISTERS[18].ce_out_i[18]_i_1_n_0 ;
wire \GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0 ;
wire \GEN_BKEND_CE_REGISTERS[19].ce_out_i_reg_n_0_[19] ;
wire \GEN_BKEND_CE_REGISTERS[4].ce_out_i[4]_i_1_n_0 ;
wire [0:0]GPIO_DBus_i;
wire GPIO_xferAck_i;
wire \INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_reg ;
wire \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_2_n_0 ;
wire \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_3_n_0 ;
wire \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_4_n_0 ;
wire \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_reg ;
wire \Not_Dual.READ_REG_GEN[1].GPIO_DBus_i_reg[25] ;
wire \Not_Dual.READ_REG_GEN[2].GPIO_DBus_i_reg[26] ;
wire \Not_Dual.READ_REG_GEN[3].GPIO_DBus_i_reg[27] ;
wire \Not_Dual.READ_REG_GEN[4].GPIO_DBus_i_reg[28] ;
wire \Not_Dual.READ_REG_GEN[5].GPIO_DBus_i_reg[29] ;
wire \Not_Dual.READ_REG_GEN[6].GPIO_DBus_i_reg[30] ;
wire \Not_Dual.READ_REG_GEN[7].GPIO_DBus_i_reg[31] ;
wire [7:0]\Not_Dual.gpio_Data_In_reg[0] ;
wire [0:0]\Not_Dual.gpio_Data_Out_reg[0] ;
wire \Not_Dual.gpio_Data_Out_reg[7] ;
wire [3:0]Q;
wire Read_Reg_Rst;
wire [6:0]\bus2ip_addr_i_reg[8] ;
wire bus2ip_reset;
wire bus2ip_rnw_i_reg;
wire [7:0]gpio_io_t;
wire gpio_xferAck_Reg;
wire interrupt_wrce_strb;
wire intr2bus_rdack0;
wire intr_rd_ce_or_reduce;
wire intr_wr_ce_or_reduce;
wire ip2Bus_RdAck_intr_reg_hole_d1;
wire ip2Bus_WrAck_intr_reg_hole_d1;
wire [0:0]ip2bus_data;
wire \ip2bus_data_i_D1_reg[0] ;
wire [1:0]\ip2bus_data_i_D1_reg[0]_0 ;
wire ip2bus_rdack_i_D1;
wire ip2bus_wrack_i_D1;
wire \ip_irpt_enable_reg_reg[0] ;
wire \ip_irpt_enable_reg_reg[0]_0 ;
wire ipif_glbl_irpt_enable_reg_reg;
wire irpt_rdack;
wire irpt_rdack_d1;
wire irpt_wrack;
wire irpt_wrack_d1;
wire is_read;
wire is_write_reg;
wire [0:0]p_0_in;
wire p_10_in;
wire p_10_out;
wire p_11_in;
wire p_11_out;
wire p_12_in;
wire p_12_out;
wire p_13_in;
wire p_13_out;
wire p_14_in;
wire p_14_out;
wire p_15_in;
wire p_15_out;
wire p_16_in;
wire [0:0]p_1_in;
wire p_2_in;
wire [0:0]p_3_in;
wire p_3_in_0;
wire p_4_in;
wire p_4_out;
wire p_5_in;
wire p_5_out;
wire p_6_in;
wire p_6_out;
wire p_7_in;
wire p_7_out;
wire p_8_out;
wire p_9_in;
wire p_9_out;
wire pselect_hit_i_1;
wire s_axi_aclk;
wire s_axi_aresetn;
wire s_axi_arready;
wire [15:0]s_axi_wdata;
wire s_axi_wready;
wire start2;
LUT3 #(
.INIT(8'hB8))
Bus_RNW_reg_i_1
(.I0(bus2ip_rnw_i_reg),
.I1(start2),
.I2(\ip_irpt_enable_reg_reg[0] ),
.O(Bus_RNW_reg_i_1_n_0));
FDRE Bus_RNW_reg_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(Bus_RNW_reg_i_1_n_0),
.Q(\ip_irpt_enable_reg_reg[0] ),
.R(1'b0));
LUT6 #(
.INIT(64'h0040000000000000))
\GEN_BKEND_CE_REGISTERS[10].ce_out_i[10]_i_1
(.I0(\bus2ip_addr_i_reg[8] [3]),
.I1(\bus2ip_addr_i_reg[8] [1]),
.I2(\bus2ip_addr_i_reg[8] [2]),
.I3(\bus2ip_addr_i_reg[8] [0]),
.I4(\bus2ip_addr_i_reg[8] [6]),
.I5(start2),
.O(p_9_out));
FDRE \GEN_BKEND_CE_REGISTERS[10].ce_out_i_reg[10]
(.C(s_axi_aclk),
.CE(start2),
.D(p_9_out),
.Q(p_10_in),
.R(\GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0 ));
LUT6 #(
.INIT(64'h4000000000000000))
\GEN_BKEND_CE_REGISTERS[11].ce_out_i[11]_i_1
(.I0(\bus2ip_addr_i_reg[8] [3]),
.I1(\bus2ip_addr_i_reg[8] [1]),
.I2(\bus2ip_addr_i_reg[8] [2]),
.I3(\bus2ip_addr_i_reg[8] [0]),
.I4(\bus2ip_addr_i_reg[8] [6]),
.I5(start2),
.O(p_8_out));
FDRE \GEN_BKEND_CE_REGISTERS[11].ce_out_i_reg[11]
(.C(s_axi_aclk),
.CE(start2),
.D(p_8_out),
.Q(p_9_in),
.R(\GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0 ));
LUT6 #(
.INIT(64'h0004000000000000))
\GEN_BKEND_CE_REGISTERS[12].ce_out_i[12]_i_1
(.I0(\bus2ip_addr_i_reg[8] [1]),
.I1(\bus2ip_addr_i_reg[8] [3]),
.I2(\bus2ip_addr_i_reg[8] [2]),
.I3(\bus2ip_addr_i_reg[8] [0]),
.I4(\bus2ip_addr_i_reg[8] [6]),
.I5(start2),
.O(p_7_out));
FDRE \GEN_BKEND_CE_REGISTERS[12].ce_out_i_reg[12]
(.C(s_axi_aclk),
.CE(start2),
.D(p_7_out),
.Q(\ip2bus_data_i_D1_reg[0] ),
.R(\GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0 ));
LUT6 #(
.INIT(64'h0400000000000000))
\GEN_BKEND_CE_REGISTERS[13].ce_out_i[13]_i_1
(.I0(\bus2ip_addr_i_reg[8] [1]),
.I1(\bus2ip_addr_i_reg[8] [3]),
.I2(\bus2ip_addr_i_reg[8] [2]),
.I3(\bus2ip_addr_i_reg[8] [0]),
.I4(\bus2ip_addr_i_reg[8] [6]),
.I5(start2),
.O(p_6_out));
FDRE \GEN_BKEND_CE_REGISTERS[13].ce_out_i_reg[13]
(.C(s_axi_aclk),
.CE(start2),
.D(p_6_out),
.Q(p_7_in),
.R(\GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0 ));
LUT6 #(
.INIT(64'h0008000000000000))
\GEN_BKEND_CE_REGISTERS[14].ce_out_i[14]_i_1
(.I0(\bus2ip_addr_i_reg[8] [1]),
.I1(\bus2ip_addr_i_reg[8] [3]),
.I2(\bus2ip_addr_i_reg[8] [2]),
.I3(\bus2ip_addr_i_reg[8] [0]),
.I4(\bus2ip_addr_i_reg[8] [6]),
.I5(start2),
.O(p_5_out));
FDRE \GEN_BKEND_CE_REGISTERS[14].ce_out_i_reg[14]
(.C(s_axi_aclk),
.CE(start2),
.D(p_5_out),
.Q(p_6_in),
.R(\GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0 ));
LUT6 #(
.INIT(64'h0800000000000000))
\GEN_BKEND_CE_REGISTERS[15].ce_out_i[15]_i_1
(.I0(\bus2ip_addr_i_reg[8] [1]),
.I1(\bus2ip_addr_i_reg[8] [3]),
.I2(\bus2ip_addr_i_reg[8] [2]),
.I3(\bus2ip_addr_i_reg[8] [0]),
.I4(\bus2ip_addr_i_reg[8] [6]),
.I5(start2),
.O(p_4_out));
FDRE \GEN_BKEND_CE_REGISTERS[15].ce_out_i_reg[15]
(.C(s_axi_aclk),
.CE(start2),
.D(p_4_out),
.Q(p_5_in),
.R(\GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0 ));
LUT6 #(
.INIT(64'h0008000000000000))
\GEN_BKEND_CE_REGISTERS[16].ce_out_i[16]_i_1
(.I0(\bus2ip_addr_i_reg[8] [3]),
.I1(\bus2ip_addr_i_reg[8] [2]),
.I2(\bus2ip_addr_i_reg[8] [1]),
.I3(\bus2ip_addr_i_reg[8] [0]),
.I4(\bus2ip_addr_i_reg[8] [6]),
.I5(start2),
.O(\GEN_BKEND_CE_REGISTERS[16].ce_out_i[16]_i_1_n_0 ));
FDRE \GEN_BKEND_CE_REGISTERS[16].ce_out_i_reg[16]
(.C(s_axi_aclk),
.CE(start2),
.D(\GEN_BKEND_CE_REGISTERS[16].ce_out_i[16]_i_1_n_0 ),
.Q(p_4_in),
.R(\GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0 ));
LUT6 #(
.INIT(64'h0800000000000000))
\GEN_BKEND_CE_REGISTERS[17].ce_out_i[17]_i_1
(.I0(\bus2ip_addr_i_reg[8] [3]),
.I1(\bus2ip_addr_i_reg[8] [2]),
.I2(\bus2ip_addr_i_reg[8] [1]),
.I3(\bus2ip_addr_i_reg[8] [0]),
.I4(\bus2ip_addr_i_reg[8] [6]),
.I5(start2),
.O(\GEN_BKEND_CE_REGISTERS[17].ce_out_i[17]_i_1_n_0 ));
FDRE \GEN_BKEND_CE_REGISTERS[17].ce_out_i_reg[17]
(.C(s_axi_aclk),
.CE(start2),
.D(\GEN_BKEND_CE_REGISTERS[17].ce_out_i[17]_i_1_n_0 ),
.Q(p_3_in_0),
.R(\GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0 ));
LUT6 #(
.INIT(64'h0080000000000000))
\GEN_BKEND_CE_REGISTERS[18].ce_out_i[18]_i_1
(.I0(\bus2ip_addr_i_reg[8] [3]),
.I1(\bus2ip_addr_i_reg[8] [1]),
.I2(\bus2ip_addr_i_reg[8] [2]),
.I3(\bus2ip_addr_i_reg[8] [0]),
.I4(\bus2ip_addr_i_reg[8] [6]),
.I5(start2),
.O(\GEN_BKEND_CE_REGISTERS[18].ce_out_i[18]_i_1_n_0 ));
FDRE \GEN_BKEND_CE_REGISTERS[18].ce_out_i_reg[18]
(.C(s_axi_aclk),
.CE(start2),
.D(\GEN_BKEND_CE_REGISTERS[18].ce_out_i[18]_i_1_n_0 ),
.Q(p_2_in),
.R(\GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0 ));
LUT3 #(
.INIT(8'hFD))
\GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1
(.I0(s_axi_aresetn),
.I1(s_axi_arready),
.I2(s_axi_wready),
.O(\GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0 ));
LUT6 #(
.INIT(64'h8000000000000000))
\GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_2
(.I0(\bus2ip_addr_i_reg[8] [3]),
.I1(\bus2ip_addr_i_reg[8] [1]),
.I2(\bus2ip_addr_i_reg[8] [2]),
.I3(\bus2ip_addr_i_reg[8] [0]),
.I4(\bus2ip_addr_i_reg[8] [6]),
.I5(start2),
.O(p_15_out));
FDRE \GEN_BKEND_CE_REGISTERS[19].ce_out_i_reg[19]
(.C(s_axi_aclk),
.CE(start2),
.D(p_15_out),
.Q(\GEN_BKEND_CE_REGISTERS[19].ce_out_i_reg_n_0_[19] ),
.R(\GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0 ));
LUT6 #(
.INIT(64'h0001000000000000))
\GEN_BKEND_CE_REGISTERS[4].ce_out_i[4]_i_1
(.I0(\bus2ip_addr_i_reg[8] [1]),
.I1(\bus2ip_addr_i_reg[8] [2]),
.I2(\bus2ip_addr_i_reg[8] [3]),
.I3(\bus2ip_addr_i_reg[8] [0]),
.I4(\bus2ip_addr_i_reg[8] [6]),
.I5(start2),
.O(\GEN_BKEND_CE_REGISTERS[4].ce_out_i[4]_i_1_n_0 ));
FDRE \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]
(.C(s_axi_aclk),
.CE(start2),
.D(\GEN_BKEND_CE_REGISTERS[4].ce_out_i[4]_i_1_n_0 ),
.Q(p_16_in),
.R(\GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0 ));
LUT6 #(
.INIT(64'h0100000000000000))
\GEN_BKEND_CE_REGISTERS[5].ce_out_i[5]_i_1
(.I0(\bus2ip_addr_i_reg[8] [1]),
.I1(\bus2ip_addr_i_reg[8] [2]),
.I2(\bus2ip_addr_i_reg[8] [3]),
.I3(\bus2ip_addr_i_reg[8] [0]),
.I4(\bus2ip_addr_i_reg[8] [6]),
.I5(start2),
.O(p_14_out));
FDRE \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]
(.C(s_axi_aclk),
.CE(start2),
.D(p_14_out),
.Q(p_15_in),
.R(\GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0 ));
LUT6 #(
.INIT(64'h0002000000000000))
\GEN_BKEND_CE_REGISTERS[6].ce_out_i[6]_i_1
(.I0(\bus2ip_addr_i_reg[8] [1]),
.I1(\bus2ip_addr_i_reg[8] [2]),
.I2(\bus2ip_addr_i_reg[8] [3]),
.I3(\bus2ip_addr_i_reg[8] [0]),
.I4(\bus2ip_addr_i_reg[8] [6]),
.I5(start2),
.O(p_13_out));
FDRE \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]
(.C(s_axi_aclk),
.CE(start2),
.D(p_13_out),
.Q(p_14_in),
.R(\GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0 ));
LUT6 #(
.INIT(64'h0200000000000000))
\GEN_BKEND_CE_REGISTERS[7].ce_out_i[7]_i_1
(.I0(\bus2ip_addr_i_reg[8] [1]),
.I1(\bus2ip_addr_i_reg[8] [2]),
.I2(\bus2ip_addr_i_reg[8] [3]),
.I3(\bus2ip_addr_i_reg[8] [0]),
.I4(\bus2ip_addr_i_reg[8] [6]),
.I5(start2),
.O(p_12_out));
FDRE \GEN_BKEND_CE_REGISTERS[7].ce_out_i_reg[7]
(.C(s_axi_aclk),
.CE(start2),
.D(p_12_out),
.Q(p_13_in),
.R(\GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0 ));
LUT6 #(
.INIT(64'h0004000000000000))
\GEN_BKEND_CE_REGISTERS[8].ce_out_i[8]_i_1
(.I0(\bus2ip_addr_i_reg[8] [3]),
.I1(\bus2ip_addr_i_reg[8] [2]),
.I2(\bus2ip_addr_i_reg[8] [1]),
.I3(\bus2ip_addr_i_reg[8] [0]),
.I4(\bus2ip_addr_i_reg[8] [6]),
.I5(start2),
.O(p_11_out));
FDRE \GEN_BKEND_CE_REGISTERS[8].ce_out_i_reg[8]
(.C(s_axi_aclk),
.CE(start2),
.D(p_11_out),
.Q(p_12_in),
.R(\GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0 ));
LUT6 #(
.INIT(64'h0400000000000000))
\GEN_BKEND_CE_REGISTERS[9].ce_out_i[9]_i_1
(.I0(\bus2ip_addr_i_reg[8] [3]),
.I1(\bus2ip_addr_i_reg[8] [2]),
.I2(\bus2ip_addr_i_reg[8] [1]),
.I3(\bus2ip_addr_i_reg[8] [0]),
.I4(\bus2ip_addr_i_reg[8] [6]),
.I5(start2),
.O(p_10_out));
FDRE \GEN_BKEND_CE_REGISTERS[9].ce_out_i_reg[9]
(.C(s_axi_aclk),
.CE(start2),
.D(p_10_out),
.Q(p_11_in),
.R(\GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT4 #(
.INIT(16'hFE00))
\INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_d1_i_1
(.I0(\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_2_n_0 ),
.I1(\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_3_n_0 ),
.I2(\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_4_n_0 ),
.I3(\ip_irpt_enable_reg_reg[0] ),
.O(intr_rd_ce_or_reduce));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT5 #(
.INIT(32'h00FE0000))
\INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_i_1
(.I0(\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_2_n_0 ),
.I1(\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_3_n_0 ),
.I2(\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_4_n_0 ),
.I3(ip2Bus_RdAck_intr_reg_hole_d1),
.I4(\ip_irpt_enable_reg_reg[0] ),
.O(\INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_reg ));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT4 #(
.INIT(16'h00FE))
\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_1
(.I0(\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_2_n_0 ),
.I1(\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_3_n_0 ),
.I2(\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_4_n_0 ),
.I3(\ip_irpt_enable_reg_reg[0] ),
.O(intr_wr_ce_or_reduce));
LUT5 #(
.INIT(32'hFFFFFFFE))
\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_2
(.I0(p_16_in),
.I1(p_2_in),
.I2(\GEN_BKEND_CE_REGISTERS[19].ce_out_i_reg_n_0_[19] ),
.I3(p_14_in),
.I4(p_15_in),
.O(\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_2_n_0 ));
LUT4 #(
.INIT(16'hFFFE))
\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_3
(.I0(p_12_in),
.I1(p_13_in),
.I2(p_10_in),
.I3(p_11_in),
.O(\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_3_n_0 ));
LUT4 #(
.INIT(16'hFFFE))
\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_4
(.I0(p_5_in),
.I1(p_7_in),
.I2(p_3_in_0),
.I3(p_4_in),
.O(\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_4_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT5 #(
.INIT(32'h000000FE))
\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_i_1
(.I0(\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_2_n_0 ),
.I1(\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_3_n_0 ),
.I2(\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_4_n_0 ),
.I3(\ip_irpt_enable_reg_reg[0] ),
.I4(ip2Bus_WrAck_intr_reg_hole_d1),
.O(\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_reg ));
LUT6 #(
.INIT(64'h0000000000000002))
\MEM_DECODE_GEN[0].cs_out_i[0]_i_1
(.I0(start2),
.I1(\bus2ip_addr_i_reg[8] [6]),
.I2(\bus2ip_addr_i_reg[8] [4]),
.I3(\bus2ip_addr_i_reg[8] [5]),
.I4(\bus2ip_addr_i_reg[8] [3]),
.I5(\bus2ip_addr_i_reg[8] [2]),
.O(pselect_hit_i_1));
FDRE \MEM_DECODE_GEN[0].cs_out_i_reg[0]
(.C(s_axi_aclk),
.CE(start2),
.D(pselect_hit_i_1),
.Q(\Not_Dual.gpio_Data_Out_reg[7] ),
.R(\GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0 ));
LUT6 #(
.INIT(64'h000A0000000C0000))
\Not_Dual.READ_REG_GEN[0].GPIO_DBus_i[24]_i_1
(.I0(gpio_io_t[7]),
.I1(\Not_Dual.gpio_Data_In_reg[0] [7]),
.I2(\bus2ip_addr_i_reg[8] [6]),
.I3(\bus2ip_addr_i_reg[8] [1]),
.I4(\Not_Dual.gpio_Data_Out_reg[7] ),
.I5(\bus2ip_addr_i_reg[8] [0]),
.O(GPIO_DBus_i));
LUT6 #(
.INIT(64'h000A0000000C0000))
\Not_Dual.READ_REG_GEN[1].GPIO_DBus_i[25]_i_1
(.I0(gpio_io_t[6]),
.I1(\Not_Dual.gpio_Data_In_reg[0] [6]),
.I2(\bus2ip_addr_i_reg[8] [6]),
.I3(\bus2ip_addr_i_reg[8] [1]),
.I4(\Not_Dual.gpio_Data_Out_reg[7] ),
.I5(\bus2ip_addr_i_reg[8] [0]),
.O(\Not_Dual.READ_REG_GEN[1].GPIO_DBus_i_reg[25] ));
LUT6 #(
.INIT(64'h000A0000000C0000))
\Not_Dual.READ_REG_GEN[2].GPIO_DBus_i[26]_i_1
(.I0(gpio_io_t[5]),
.I1(\Not_Dual.gpio_Data_In_reg[0] [5]),
.I2(\bus2ip_addr_i_reg[8] [6]),
.I3(\bus2ip_addr_i_reg[8] [1]),
.I4(\Not_Dual.gpio_Data_Out_reg[7] ),
.I5(\bus2ip_addr_i_reg[8] [0]),
.O(\Not_Dual.READ_REG_GEN[2].GPIO_DBus_i_reg[26] ));
LUT6 #(
.INIT(64'h000A0000000C0000))
\Not_Dual.READ_REG_GEN[3].GPIO_DBus_i[27]_i_1
(.I0(gpio_io_t[4]),
.I1(\Not_Dual.gpio_Data_In_reg[0] [4]),
.I2(\bus2ip_addr_i_reg[8] [6]),
.I3(\bus2ip_addr_i_reg[8] [1]),
.I4(\Not_Dual.gpio_Data_Out_reg[7] ),
.I5(\bus2ip_addr_i_reg[8] [0]),
.O(\Not_Dual.READ_REG_GEN[3].GPIO_DBus_i_reg[27] ));
LUT6 #(
.INIT(64'h000A0000000C0000))
\Not_Dual.READ_REG_GEN[4].GPIO_DBus_i[28]_i_1
(.I0(gpio_io_t[3]),
.I1(\Not_Dual.gpio_Data_In_reg[0] [3]),
.I2(\bus2ip_addr_i_reg[8] [6]),
.I3(\bus2ip_addr_i_reg[8] [1]),
.I4(\Not_Dual.gpio_Data_Out_reg[7] ),
.I5(\bus2ip_addr_i_reg[8] [0]),
.O(\Not_Dual.READ_REG_GEN[4].GPIO_DBus_i_reg[28] ));
LUT6 #(
.INIT(64'h000A0000000C0000))
\Not_Dual.READ_REG_GEN[5].GPIO_DBus_i[29]_i_1
(.I0(gpio_io_t[2]),
.I1(\Not_Dual.gpio_Data_In_reg[0] [2]),
.I2(\bus2ip_addr_i_reg[8] [6]),
.I3(\bus2ip_addr_i_reg[8] [1]),
.I4(\Not_Dual.gpio_Data_Out_reg[7] ),
.I5(\bus2ip_addr_i_reg[8] [0]),
.O(\Not_Dual.READ_REG_GEN[5].GPIO_DBus_i_reg[29] ));
LUT6 #(
.INIT(64'h000A0000000C0000))
\Not_Dual.READ_REG_GEN[6].GPIO_DBus_i[30]_i_1
(.I0(gpio_io_t[1]),
.I1(\Not_Dual.gpio_Data_In_reg[0] [1]),
.I2(\bus2ip_addr_i_reg[8] [6]),
.I3(\bus2ip_addr_i_reg[8] [1]),
.I4(\Not_Dual.gpio_Data_Out_reg[7] ),
.I5(\bus2ip_addr_i_reg[8] [0]),
.O(\Not_Dual.READ_REG_GEN[6].GPIO_DBus_i_reg[30] ));
LUT4 #(
.INIT(16'hFFDF))
\Not_Dual.READ_REG_GEN[7].GPIO_DBus_i[31]_i_1
(.I0(\Not_Dual.gpio_Data_Out_reg[7] ),
.I1(GPIO_xferAck_i),
.I2(bus2ip_rnw_i_reg),
.I3(gpio_xferAck_Reg),
.O(Read_Reg_Rst));
LUT6 #(
.INIT(64'h000A0000000C0000))
\Not_Dual.READ_REG_GEN[7].GPIO_DBus_i[31]_i_2
(.I0(gpio_io_t[0]),
.I1(\Not_Dual.gpio_Data_In_reg[0] [0]),
.I2(\bus2ip_addr_i_reg[8] [6]),
.I3(\bus2ip_addr_i_reg[8] [1]),
.I4(\Not_Dual.gpio_Data_Out_reg[7] ),
.I5(\bus2ip_addr_i_reg[8] [0]),
.O(\Not_Dual.READ_REG_GEN[7].GPIO_DBus_i_reg[31] ));
LUT6 #(
.INIT(64'hFFFFFFFF00000100))
\Not_Dual.gpio_Data_Out[0]_i_1
(.I0(bus2ip_rnw_i_reg),
.I1(\bus2ip_addr_i_reg[8] [6]),
.I2(\bus2ip_addr_i_reg[8] [1]),
.I3(\Not_Dual.gpio_Data_Out_reg[7] ),
.I4(\bus2ip_addr_i_reg[8] [0]),
.I5(bus2ip_reset),
.O(\Not_Dual.gpio_Data_Out_reg[0] ));
LUT4 #(
.INIT(16'hBA8A))
\Not_Dual.gpio_Data_Out[0]_i_2
(.I0(s_axi_wdata[15]),
.I1(\bus2ip_addr_i_reg[8] [1]),
.I2(\Not_Dual.gpio_Data_Out_reg[7] ),
.I3(s_axi_wdata[7]),
.O(D[7]));
LUT4 #(
.INIT(16'hBA8A))
\Not_Dual.gpio_Data_Out[1]_i_1
(.I0(s_axi_wdata[14]),
.I1(\bus2ip_addr_i_reg[8] [1]),
.I2(\Not_Dual.gpio_Data_Out_reg[7] ),
.I3(s_axi_wdata[6]),
.O(D[6]));
LUT4 #(
.INIT(16'hBA8A))
\Not_Dual.gpio_Data_Out[2]_i_1
(.I0(s_axi_wdata[13]),
.I1(\bus2ip_addr_i_reg[8] [1]),
.I2(\Not_Dual.gpio_Data_Out_reg[7] ),
.I3(s_axi_wdata[5]),
.O(D[5]));
LUT4 #(
.INIT(16'hBA8A))
\Not_Dual.gpio_Data_Out[3]_i_1
(.I0(s_axi_wdata[12]),
.I1(\bus2ip_addr_i_reg[8] [1]),
.I2(\Not_Dual.gpio_Data_Out_reg[7] ),
.I3(s_axi_wdata[4]),
.O(D[4]));
LUT4 #(
.INIT(16'hBA8A))
\Not_Dual.gpio_Data_Out[4]_i_1
(.I0(s_axi_wdata[11]),
.I1(\bus2ip_addr_i_reg[8] [1]),
.I2(\Not_Dual.gpio_Data_Out_reg[7] ),
.I3(s_axi_wdata[3]),
.O(D[3]));
LUT4 #(
.INIT(16'hBA8A))
\Not_Dual.gpio_Data_Out[5]_i_1
(.I0(s_axi_wdata[10]),
.I1(\bus2ip_addr_i_reg[8] [1]),
.I2(\Not_Dual.gpio_Data_Out_reg[7] ),
.I3(s_axi_wdata[2]),
.O(D[2]));
LUT4 #(
.INIT(16'hBA8A))
\Not_Dual.gpio_Data_Out[6]_i_1
(.I0(s_axi_wdata[9]),
.I1(\bus2ip_addr_i_reg[8] [1]),
.I2(\Not_Dual.gpio_Data_Out_reg[7] ),
.I3(s_axi_wdata[1]),
.O(D[1]));
LUT4 #(
.INIT(16'hBA8A))
\Not_Dual.gpio_Data_Out[7]_i_1
(.I0(s_axi_wdata[8]),
.I1(\bus2ip_addr_i_reg[8] [1]),
.I2(\Not_Dual.gpio_Data_Out_reg[7] ),
.I3(s_axi_wdata[0]),
.O(D[0]));
LUT6 #(
.INIT(64'hFFFFFFFF01000000))
\Not_Dual.gpio_OE[0]_i_1
(.I0(bus2ip_rnw_i_reg),
.I1(\bus2ip_addr_i_reg[8] [6]),
.I2(\bus2ip_addr_i_reg[8] [1]),
.I3(\Not_Dual.gpio_Data_Out_reg[7] ),
.I4(\bus2ip_addr_i_reg[8] [0]),
.I5(bus2ip_reset),
.O(E));
LUT5 #(
.INIT(32'h44444440))
intr2bus_rdack_i_1
(.I0(irpt_rdack_d1),
.I1(\ip_irpt_enable_reg_reg[0] ),
.I2(p_9_in),
.I3(\ip2bus_data_i_D1_reg[0] ),
.I4(p_6_in),
.O(intr2bus_rdack0));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT5 #(
.INIT(32'h000000FE))
intr2bus_wrack_i_1
(.I0(p_9_in),
.I1(\ip2bus_data_i_D1_reg[0] ),
.I2(p_6_in),
.I3(\ip_irpt_enable_reg_reg[0] ),
.I4(irpt_wrack_d1),
.O(interrupt_wrce_strb));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT5 #(
.INIT(32'h00000080))
\ip2bus_data_i_D1[0]_i_1
(.I0(p_0_in),
.I1(p_9_in),
.I2(\ip_irpt_enable_reg_reg[0] ),
.I3(p_6_in),
.I4(\ip2bus_data_i_D1_reg[0] ),
.O(\ip2bus_data_i_D1_reg[0]_0 [1]));
LUT6 #(
.INIT(64'hEEEEAAAAFAAAAAAA))
\ip2bus_data_i_D1[31]_i_1
(.I0(ip2bus_data),
.I1(p_3_in),
.I2(p_1_in),
.I3(p_6_in),
.I4(\ip_irpt_enable_reg_reg[0] ),
.I5(\ip2bus_data_i_D1_reg[0] ),
.O(\ip2bus_data_i_D1_reg[0]_0 [0]));
LUT4 #(
.INIT(16'hFB08))
\ip_irpt_enable_reg[0]_i_1
(.I0(s_axi_wdata[0]),
.I1(p_6_in),
.I2(\ip_irpt_enable_reg_reg[0] ),
.I3(p_1_in),
.O(\ip_irpt_enable_reg_reg[0]_0 ));
LUT4 #(
.INIT(16'hFB08))
ipif_glbl_irpt_enable_reg_i_1
(.I0(s_axi_wdata[15]),
.I1(p_9_in),
.I2(\ip_irpt_enable_reg_reg[0] ),
.I3(p_0_in),
.O(ipif_glbl_irpt_enable_reg_reg));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT4 #(
.INIT(16'hFE00))
irpt_rdack_d1_i_1
(.I0(p_9_in),
.I1(\ip2bus_data_i_D1_reg[0] ),
.I2(p_6_in),
.I3(\ip_irpt_enable_reg_reg[0] ),
.O(irpt_rdack));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT4 #(
.INIT(16'h00FE))
irpt_wrack_d1_i_1
(.I0(p_9_in),
.I1(\ip2bus_data_i_D1_reg[0] ),
.I2(p_6_in),
.I3(\ip_irpt_enable_reg_reg[0] ),
.O(irpt_wrack));
LUT6 #(
.INIT(64'hFFFFFFFF00020000))
s_axi_arready_INST_0
(.I0(Q[3]),
.I1(Q[2]),
.I2(Q[1]),
.I3(Q[0]),
.I4(is_read),
.I5(ip2bus_rdack_i_D1),
.O(s_axi_arready));
LUT6 #(
.INIT(64'hFFFFFFFF00020000))
s_axi_wready_INST_0
(.I0(Q[3]),
.I1(Q[2]),
.I2(Q[1]),
.I3(Q[0]),
.I4(is_write_reg),
.I5(ip2bus_wrack_i_D1),
.O(s_axi_wready));
endmodule |
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio
(s_axi_aclk,
s_axi_aresetn,
s_axi_awaddr,
s_axi_awvalid,
s_axi_awready,
s_axi_wdata,
s_axi_wstrb,
s_axi_wvalid,
s_axi_wready,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_araddr,
s_axi_arvalid,
s_axi_arready,
s_axi_rdata,
s_axi_rresp,
s_axi_rvalid,
s_axi_rready,
ip2intc_irpt,
gpio_io_i,
gpio_io_o,
gpio_io_t,
gpio2_io_i,
gpio2_io_o,
gpio2_io_t);
(* max_fanout = "10000" *) (* sigis = "Clk" *) input s_axi_aclk;
(* max_fanout = "10000" *) (* sigis = "Rst" *) input s_axi_aresetn;
input [8:0]s_axi_awaddr;
input s_axi_awvalid;
output s_axi_awready;
input [31:0]s_axi_wdata;
input [3:0]s_axi_wstrb;
input s_axi_wvalid;
output s_axi_wready;
output [1:0]s_axi_bresp;
output s_axi_bvalid;
input s_axi_bready;
input [8:0]s_axi_araddr;
input s_axi_arvalid;
output s_axi_arready;
output [31:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output s_axi_rvalid;
input s_axi_rready;
(* sigis = "INTR_LEVEL_HIGH" *) output ip2intc_irpt;
input [7:0]gpio_io_i;
output [7:0]gpio_io_o;
output [7:0]gpio_io_t;
input [31:0]gpio2_io_i;
output [31:0]gpio2_io_o;
output [31:0]gpio2_io_t;
wire \<const0> ;
wire \<const1> ;
wire AXI_LITE_IPIF_I_n_16;
wire AXI_LITE_IPIF_I_n_17;
wire AXI_LITE_IPIF_I_n_18;
wire AXI_LITE_IPIF_I_n_19;
wire AXI_LITE_IPIF_I_n_20;
wire AXI_LITE_IPIF_I_n_21;
wire AXI_LITE_IPIF_I_n_22;
wire AXI_LITE_IPIF_I_n_24;
wire AXI_LITE_IPIF_I_n_25;
wire AXI_LITE_IPIF_I_n_33;
wire AXI_LITE_IPIF_I_n_35;
wire AXI_LITE_IPIF_I_n_37;
wire AXI_LITE_IPIF_I_n_38;
wire [0:7]DBus_Reg;
wire [24:24]GPIO_DBus_i;
wire GPIO_intr;
wire GPIO_xferAck_i;
wire IP2INTC_Irpt_i;
wire \I_SLAVE_ATTACHMENT/I_DECODER/Bus_RNW_reg ;
wire \I_SLAVE_ATTACHMENT/I_DECODER/p_8_in ;
wire Read_Reg_Rst;
wire [1:1]bus2ip_cs;
wire bus2ip_reset;
wire bus2ip_reset_i_1_n_0;
wire bus2ip_rnw;
wire [0:7]gpio_Data_In;
wire [7:0]gpio_io_i;
wire [7:0]gpio_io_o;
wire [7:0]gpio_io_t;
wire gpio_xferAck_Reg;
wire interrupt_wrce_strb;
wire intr2bus_rdack0;
wire intr_rd_ce_or_reduce;
wire intr_wr_ce_or_reduce;
wire ip2Bus_RdAck_intr_reg_hole;
wire ip2Bus_RdAck_intr_reg_hole_d1;
wire ip2Bus_WrAck_intr_reg_hole;
wire ip2Bus_WrAck_intr_reg_hole_d1;
wire [24:31]ip2bus_data;
wire [31:31]ip2bus_data_i;
wire [0:31]ip2bus_data_i_D1;
wire ip2bus_rdack_i;
wire ip2bus_rdack_i_D1;
wire ip2bus_wrack_i;
wire ip2bus_wrack_i_D1;
wire ip2intc_irpt;
wire irpt_rdack;
wire irpt_rdack_d1;
wire irpt_wrack;
wire irpt_wrack_d1;
wire [31:31]p_0_in;
wire [0:0]p_0_out;
wire [0:0]p_1_in;
wire [0:0]p_3_in;
(* MAX_FANOUT = "10000" *) (* RTL_MAX_FANOUT = "found" *) (* sigis = "Clk" *) wire s_axi_aclk;
wire [8:0]s_axi_araddr;
(* MAX_FANOUT = "10000" *) (* RTL_MAX_FANOUT = "found" *) (* sigis = "Rst" *) wire s_axi_aresetn;
wire s_axi_arready;
wire s_axi_arvalid;
wire [8:0]s_axi_awaddr;
wire s_axi_awvalid;
wire s_axi_bready;
wire s_axi_bvalid;
wire [31:0]\^s_axi_rdata ;
wire s_axi_rready;
wire s_axi_rvalid;
wire [31:0]s_axi_wdata;
wire s_axi_wready;
wire s_axi_wvalid;
assign gpio2_io_o[31] = \<const0> ;
assign gpio2_io_o[30] = \<const0> ;
assign gpio2_io_o[29] = \<const0> ;
assign gpio2_io_o[28] = \<const0> ;
assign gpio2_io_o[27] = \<const0> ;
assign gpio2_io_o[26] = \<const0> ;
assign gpio2_io_o[25] = \<const0> ;
assign gpio2_io_o[24] = \<const0> ;
assign gpio2_io_o[23] = \<const0> ;
assign gpio2_io_o[22] = \<const0> ;
assign gpio2_io_o[21] = \<const0> ;
assign gpio2_io_o[20] = \<const0> ;
assign gpio2_io_o[19] = \<const0> ;
assign gpio2_io_o[18] = \<const0> ;
assign gpio2_io_o[17] = \<const0> ;
assign gpio2_io_o[16] = \<const0> ;
assign gpio2_io_o[15] = \<const0> ;
assign gpio2_io_o[14] = \<const0> ;
assign gpio2_io_o[13] = \<const0> ;
assign gpio2_io_o[12] = \<const0> ;
assign gpio2_io_o[11] = \<const0> ;
assign gpio2_io_o[10] = \<const0> ;
assign gpio2_io_o[9] = \<const0> ;
assign gpio2_io_o[8] = \<const0> ;
assign gpio2_io_o[7] = \<const0> ;
assign gpio2_io_o[6] = \<const0> ;
assign gpio2_io_o[5] = \<const0> ;
assign gpio2_io_o[4] = \<const0> ;
assign gpio2_io_o[3] = \<const0> ;
assign gpio2_io_o[2] = \<const0> ;
assign gpio2_io_o[1] = \<const0> ;
assign gpio2_io_o[0] = \<const0> ;
assign gpio2_io_t[31] = \<const1> ;
assign gpio2_io_t[30] = \<const1> ;
assign gpio2_io_t[29] = \<const1> ;
assign gpio2_io_t[28] = \<const1> ;
assign gpio2_io_t[27] = \<const1> ;
assign gpio2_io_t[26] = \<const1> ;
assign gpio2_io_t[25] = \<const1> ;
assign gpio2_io_t[24] = \<const1> ;
assign gpio2_io_t[23] = \<const1> ;
assign gpio2_io_t[22] = \<const1> ;
assign gpio2_io_t[21] = \<const1> ;
assign gpio2_io_t[20] = \<const1> ;
assign gpio2_io_t[19] = \<const1> ;
assign gpio2_io_t[18] = \<const1> ;
assign gpio2_io_t[17] = \<const1> ;
assign gpio2_io_t[16] = \<const1> ;
assign gpio2_io_t[15] = \<const1> ;
assign gpio2_io_t[14] = \<const1> ;
assign gpio2_io_t[13] = \<const1> ;
assign gpio2_io_t[12] = \<const1> ;
assign gpio2_io_t[11] = \<const1> ;
assign gpio2_io_t[10] = \<const1> ;
assign gpio2_io_t[9] = \<const1> ;
assign gpio2_io_t[8] = \<const1> ;
assign gpio2_io_t[7] = \<const1> ;
assign gpio2_io_t[6] = \<const1> ;
assign gpio2_io_t[5] = \<const1> ;
assign gpio2_io_t[4] = \<const1> ;
assign gpio2_io_t[3] = \<const1> ;
assign gpio2_io_t[2] = \<const1> ;
assign gpio2_io_t[1] = \<const1> ;
assign gpio2_io_t[0] = \<const1> ;
assign s_axi_awready = s_axi_wready;
assign s_axi_bresp[1] = \<const0> ;
assign s_axi_bresp[0] = \<const0> ;
assign s_axi_rdata[31] = \^s_axi_rdata [31];
assign s_axi_rdata[30] = \<const0> ;
assign s_axi_rdata[29] = \<const0> ;
assign s_axi_rdata[28] = \<const0> ;
assign s_axi_rdata[27] = \<const0> ;
assign s_axi_rdata[26] = \<const0> ;
assign s_axi_rdata[25] = \<const0> ;
assign s_axi_rdata[24] = \<const0> ;
assign s_axi_rdata[23] = \<const0> ;
assign s_axi_rdata[22] = \<const0> ;
assign s_axi_rdata[21] = \<const0> ;
assign s_axi_rdata[20] = \<const0> ;
assign s_axi_rdata[19] = \<const0> ;
assign s_axi_rdata[18] = \<const0> ;
assign s_axi_rdata[17] = \<const0> ;
assign s_axi_rdata[16] = \<const0> ;
assign s_axi_rdata[15] = \<const0> ;
assign s_axi_rdata[14] = \<const0> ;
assign s_axi_rdata[13] = \<const0> ;
assign s_axi_rdata[12] = \<const0> ;
assign s_axi_rdata[11] = \<const0> ;
assign s_axi_rdata[10] = \<const0> ;
assign s_axi_rdata[9] = \<const0> ;
assign s_axi_rdata[8] = \<const0> ;
assign s_axi_rdata[7:0] = \^s_axi_rdata [7:0];
assign s_axi_rresp[1] = \<const0> ;
assign s_axi_rresp[0] = \<const0> ;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_lite_ipif AXI_LITE_IPIF_I
(.Bus_RNW_reg(\I_SLAVE_ATTACHMENT/I_DECODER/Bus_RNW_reg ),
.D({DBus_Reg[0],DBus_Reg[1],DBus_Reg[2],DBus_Reg[3],DBus_Reg[4],DBus_Reg[5],DBus_Reg[6],DBus_Reg[7]}),
.E(AXI_LITE_IPIF_I_n_24),
.GPIO_DBus_i(GPIO_DBus_i),
.GPIO_xferAck_i(GPIO_xferAck_i),
.\INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_reg (AXI_LITE_IPIF_I_n_33),
.\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_reg (AXI_LITE_IPIF_I_n_35),
.\Not_Dual.READ_REG_GEN[1].GPIO_DBus_i_reg[25] (AXI_LITE_IPIF_I_n_22),
.\Not_Dual.READ_REG_GEN[2].GPIO_DBus_i_reg[26] (AXI_LITE_IPIF_I_n_21),
.\Not_Dual.READ_REG_GEN[3].GPIO_DBus_i_reg[27] (AXI_LITE_IPIF_I_n_20),
.\Not_Dual.READ_REG_GEN[4].GPIO_DBus_i_reg[28] (AXI_LITE_IPIF_I_n_19),
.\Not_Dual.READ_REG_GEN[5].GPIO_DBus_i_reg[29] (AXI_LITE_IPIF_I_n_18),
.\Not_Dual.READ_REG_GEN[6].GPIO_DBus_i_reg[30] (AXI_LITE_IPIF_I_n_17),
.\Not_Dual.READ_REG_GEN[7].GPIO_DBus_i_reg[31] (AXI_LITE_IPIF_I_n_16),
.\Not_Dual.gpio_Data_Out_reg[0] (AXI_LITE_IPIF_I_n_25),
.Q({gpio_Data_In[0],gpio_Data_In[1],gpio_Data_In[2],gpio_Data_In[3],gpio_Data_In[4],gpio_Data_In[5],gpio_Data_In[6],gpio_Data_In[7]}),
.Read_Reg_Rst(Read_Reg_Rst),
.bus2ip_cs(bus2ip_cs),
.bus2ip_reset(bus2ip_reset),
.bus2ip_rnw(bus2ip_rnw),
.gpio_io_t(gpio_io_t),
.gpio_xferAck_Reg(gpio_xferAck_Reg),
.interrupt_wrce_strb(interrupt_wrce_strb),
.intr2bus_rdack0(intr2bus_rdack0),
.intr_rd_ce_or_reduce(intr_rd_ce_or_reduce),
.intr_wr_ce_or_reduce(intr_wr_ce_or_reduce),
.ip2Bus_RdAck_intr_reg_hole_d1(ip2Bus_RdAck_intr_reg_hole_d1),
.ip2Bus_WrAck_intr_reg_hole_d1(ip2Bus_WrAck_intr_reg_hole_d1),
.ip2bus_data(ip2bus_data[31]),
.\ip2bus_data_i_D1_reg[0] ({p_0_out,ip2bus_data_i}),
.\ip2bus_data_i_D1_reg[0]_0 ({ip2bus_data_i_D1[0],ip2bus_data_i_D1[24],ip2bus_data_i_D1[25],ip2bus_data_i_D1[26],ip2bus_data_i_D1[27],ip2bus_data_i_D1[28],ip2bus_data_i_D1[29],ip2bus_data_i_D1[30],ip2bus_data_i_D1[31]}),
.ip2bus_rdack_i_D1(ip2bus_rdack_i_D1),
.ip2bus_wrack_i_D1(ip2bus_wrack_i_D1),
.\ip_irpt_enable_reg_reg[0] (AXI_LITE_IPIF_I_n_37),
.ipif_glbl_irpt_enable_reg_reg(AXI_LITE_IPIF_I_n_38),
.irpt_rdack(irpt_rdack),
.irpt_rdack_d1(irpt_rdack_d1),
.irpt_wrack(irpt_wrack),
.irpt_wrack_d1(irpt_wrack_d1),
.p_0_in(p_0_in),
.p_1_in(p_1_in),
.p_3_in(p_3_in),
.p_8_in(\I_SLAVE_ATTACHMENT/I_DECODER/p_8_in ),
.s_axi_aclk(s_axi_aclk),
.s_axi_araddr(s_axi_araddr[8:2]),
.s_axi_aresetn(s_axi_aresetn),
.s_axi_arready(s_axi_arready),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_awaddr(s_axi_awaddr[8:2]),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_bready(s_axi_bready),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_rdata({\^s_axi_rdata [31],\^s_axi_rdata [7:0]}),
.s_axi_rready(s_axi_rready),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_wdata({s_axi_wdata[31:24],s_axi_wdata[7:0]}),
.s_axi_wready(s_axi_wready),
.s_axi_wvalid(s_axi_wvalid));
GND GND
(.G(\<const0> ));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_interrupt_control \INTR_CTRLR_GEN.INTERRUPT_CONTROL_I
(.Bus_RNW_reg(\I_SLAVE_ATTACHMENT/I_DECODER/Bus_RNW_reg ),
.\GEN_BKEND_CE_REGISTERS[11].ce_out_i_reg[11] (AXI_LITE_IPIF_I_n_38),
.\GEN_BKEND_CE_REGISTERS[14].ce_out_i_reg[14] (AXI_LITE_IPIF_I_n_37),
.GPIO_intr(GPIO_intr),
.GPIO_xferAck_i(GPIO_xferAck_i),
.IP2INTC_Irpt_i(IP2INTC_Irpt_i),
.bus2ip_reset(bus2ip_reset),
.bus2ip_rnw(bus2ip_rnw),
.interrupt_wrce_strb(interrupt_wrce_strb),
.intr2bus_rdack0(intr2bus_rdack0),
.ip2Bus_RdAck_intr_reg_hole(ip2Bus_RdAck_intr_reg_hole),
.ip2Bus_WrAck_intr_reg_hole(ip2Bus_WrAck_intr_reg_hole),
.ip2bus_rdack_i(ip2bus_rdack_i),
.ip2bus_wrack_i(ip2bus_wrack_i),
.irpt_rdack(irpt_rdack),
.irpt_rdack_d1(irpt_rdack_d1),
.irpt_wrack(irpt_wrack),
.irpt_wrack_d1(irpt_wrack_d1),
.p_0_in(p_0_in),
.p_1_in(p_1_in),
.p_3_in(p_3_in),
.p_8_in(\I_SLAVE_ATTACHMENT/I_DECODER/p_8_in ),
.s_axi_aclk(s_axi_aclk),
.s_axi_wdata(s_axi_wdata[0]));
FDRE \INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_d1_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(intr_rd_ce_or_reduce),
.Q(ip2Bus_RdAck_intr_reg_hole_d1),
.R(bus2ip_reset));
FDRE \INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(AXI_LITE_IPIF_I_n_33),
.Q(ip2Bus_RdAck_intr_reg_hole),
.R(bus2ip_reset));
FDRE \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(intr_wr_ce_or_reduce),
.Q(ip2Bus_WrAck_intr_reg_hole_d1),
.R(bus2ip_reset));
FDRE \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(AXI_LITE_IPIF_I_n_35),
.Q(ip2Bus_WrAck_intr_reg_hole),
.R(bus2ip_reset));
(* sigis = "INTR_LEVEL_HIGH" *)
FDRE \INTR_CTRLR_GEN.ip2intc_irpt_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(IP2INTC_Irpt_i),
.Q(ip2intc_irpt),
.R(bus2ip_reset));
VCC VCC
(.P(\<const1> ));
LUT1 #(
.INIT(2'h1))
bus2ip_reset_i_1
(.I0(s_axi_aresetn),
.O(bus2ip_reset_i_1_n_0));
FDRE bus2ip_reset_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(bus2ip_reset_i_1_n_0),
.Q(bus2ip_reset),
.R(1'b0));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_GPIO_Core gpio_core_1
(.D({DBus_Reg[0],DBus_Reg[1],DBus_Reg[2],DBus_Reg[3],DBus_Reg[4],DBus_Reg[5],DBus_Reg[6],DBus_Reg[7]}),
.E(AXI_LITE_IPIF_I_n_25),
.GPIO_DBus_i(GPIO_DBus_i),
.GPIO_intr(GPIO_intr),
.GPIO_xferAck_i(GPIO_xferAck_i),
.\Not_Dual.gpio_OE_reg[1]_0 (AXI_LITE_IPIF_I_n_22),
.\Not_Dual.gpio_OE_reg[2]_0 (AXI_LITE_IPIF_I_n_21),
.\Not_Dual.gpio_OE_reg[3]_0 (AXI_LITE_IPIF_I_n_20),
.\Not_Dual.gpio_OE_reg[4]_0 (AXI_LITE_IPIF_I_n_19),
.\Not_Dual.gpio_OE_reg[5]_0 (AXI_LITE_IPIF_I_n_18),
.\Not_Dual.gpio_OE_reg[6]_0 (AXI_LITE_IPIF_I_n_17),
.\Not_Dual.gpio_OE_reg[7]_0 (AXI_LITE_IPIF_I_n_16),
.Q({gpio_Data_In[0],gpio_Data_In[1],gpio_Data_In[2],gpio_Data_In[3],gpio_Data_In[4],gpio_Data_In[5],gpio_Data_In[6],gpio_Data_In[7]}),
.Read_Reg_Rst(Read_Reg_Rst),
.bus2ip_cs(bus2ip_cs),
.bus2ip_reset(bus2ip_reset),
.bus2ip_rnw_i_reg(AXI_LITE_IPIF_I_n_24),
.gpio_io_i(gpio_io_i),
.gpio_io_o(gpio_io_o),
.gpio_io_t(gpio_io_t),
.gpio_xferAck_Reg(gpio_xferAck_Reg),
.ip2bus_data({ip2bus_data[24],ip2bus_data[25],ip2bus_data[26],ip2bus_data[27],ip2bus_data[28],ip2bus_data[29],ip2bus_data[30],ip2bus_data[31]}),
.s_axi_aclk(s_axi_aclk));
FDRE \ip2bus_data_i_D1_reg[0]
(.C(s_axi_aclk),
.CE(1'b1),
.D(p_0_out),
.Q(ip2bus_data_i_D1[0]),
.R(bus2ip_reset));
FDRE \ip2bus_data_i_D1_reg[24]
(.C(s_axi_aclk),
.CE(1'b1),
.D(ip2bus_data[24]),
.Q(ip2bus_data_i_D1[24]),
.R(bus2ip_reset));
FDRE \ip2bus_data_i_D1_reg[25]
(.C(s_axi_aclk),
.CE(1'b1),
.D(ip2bus_data[25]),
.Q(ip2bus_data_i_D1[25]),
.R(bus2ip_reset));
FDRE \ip2bus_data_i_D1_reg[26]
(.C(s_axi_aclk),
.CE(1'b1),
.D(ip2bus_data[26]),
.Q(ip2bus_data_i_D1[26]),
.R(bus2ip_reset));
FDRE \ip2bus_data_i_D1_reg[27]
(.C(s_axi_aclk),
.CE(1'b1),
.D(ip2bus_data[27]),
.Q(ip2bus_data_i_D1[27]),
.R(bus2ip_reset));
FDRE \ip2bus_data_i_D1_reg[28]
(.C(s_axi_aclk),
.CE(1'b1),
.D(ip2bus_data[28]),
.Q(ip2bus_data_i_D1[28]),
.R(bus2ip_reset));
FDRE \ip2bus_data_i_D1_reg[29]
(.C(s_axi_aclk),
.CE(1'b1),
.D(ip2bus_data[29]),
.Q(ip2bus_data_i_D1[29]),
.R(bus2ip_reset));
FDRE \ip2bus_data_i_D1_reg[30]
(.C(s_axi_aclk),
.CE(1'b1),
.D(ip2bus_data[30]),
.Q(ip2bus_data_i_D1[30]),
.R(bus2ip_reset));
FDRE \ip2bus_data_i_D1_reg[31]
(.C(s_axi_aclk),
.CE(1'b1),
.D(ip2bus_data_i),
.Q(ip2bus_data_i_D1[31]),
.R(bus2ip_reset));
FDRE ip2bus_rdack_i_D1_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(ip2bus_rdack_i),
.Q(ip2bus_rdack_i_D1),
.R(bus2ip_reset));
FDRE ip2bus_wrack_i_D1_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(ip2bus_wrack_i),
.Q(ip2bus_wrack_i_D1),
.R(bus2ip_reset));
endmodule |
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_lite_ipif
(p_8_in,
bus2ip_rnw,
bus2ip_cs,
Bus_RNW_reg,
s_axi_rvalid,
s_axi_bvalid,
s_axi_arready,
s_axi_wready,
D,
\Not_Dual.READ_REG_GEN[7].GPIO_DBus_i_reg[31] ,
\Not_Dual.READ_REG_GEN[6].GPIO_DBus_i_reg[30] ,
\Not_Dual.READ_REG_GEN[5].GPIO_DBus_i_reg[29] ,
\Not_Dual.READ_REG_GEN[4].GPIO_DBus_i_reg[28] ,
\Not_Dual.READ_REG_GEN[3].GPIO_DBus_i_reg[27] ,
\Not_Dual.READ_REG_GEN[2].GPIO_DBus_i_reg[26] ,
\Not_Dual.READ_REG_GEN[1].GPIO_DBus_i_reg[25] ,
GPIO_DBus_i,
E,
\Not_Dual.gpio_Data_Out_reg[0] ,
\ip2bus_data_i_D1_reg[0] ,
intr2bus_rdack0,
irpt_rdack,
irpt_wrack,
interrupt_wrce_strb,
Read_Reg_Rst,
\INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_reg ,
intr_rd_ce_or_reduce,
\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_reg ,
intr_wr_ce_or_reduce,
\ip_irpt_enable_reg_reg[0] ,
ipif_glbl_irpt_enable_reg_reg,
s_axi_rdata,
bus2ip_reset,
s_axi_aclk,
s_axi_arvalid,
s_axi_aresetn,
ip2bus_rdack_i_D1,
ip2bus_wrack_i_D1,
s_axi_bready,
s_axi_rready,
s_axi_awaddr,
s_axi_araddr,
s_axi_awvalid,
s_axi_wvalid,
s_axi_wdata,
gpio_io_t,
Q,
p_0_in,
irpt_rdack_d1,
irpt_wrack_d1,
ip2bus_data,
p_3_in,
p_1_in,
GPIO_xferAck_i,
gpio_xferAck_Reg,
ip2Bus_RdAck_intr_reg_hole_d1,
ip2Bus_WrAck_intr_reg_hole_d1,
\ip2bus_data_i_D1_reg[0]_0 );
output p_8_in;
output bus2ip_rnw;
output [0:0]bus2ip_cs;
output Bus_RNW_reg;
output s_axi_rvalid;
output s_axi_bvalid;
output s_axi_arready;
output s_axi_wready;
output [7:0]D;
output \Not_Dual.READ_REG_GEN[7].GPIO_DBus_i_reg[31] ;
output \Not_Dual.READ_REG_GEN[6].GPIO_DBus_i_reg[30] ;
output \Not_Dual.READ_REG_GEN[5].GPIO_DBus_i_reg[29] ;
output \Not_Dual.READ_REG_GEN[4].GPIO_DBus_i_reg[28] ;
output \Not_Dual.READ_REG_GEN[3].GPIO_DBus_i_reg[27] ;
output \Not_Dual.READ_REG_GEN[2].GPIO_DBus_i_reg[26] ;
output \Not_Dual.READ_REG_GEN[1].GPIO_DBus_i_reg[25] ;
output [0:0]GPIO_DBus_i;
output [0:0]E;
output [0:0]\Not_Dual.gpio_Data_Out_reg[0] ;
output [1:0]\ip2bus_data_i_D1_reg[0] ;
output intr2bus_rdack0;
output irpt_rdack;
output irpt_wrack;
output interrupt_wrce_strb;
output Read_Reg_Rst;
output \INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_reg ;
output intr_rd_ce_or_reduce;
output \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_reg ;
output intr_wr_ce_or_reduce;
output \ip_irpt_enable_reg_reg[0] ;
output ipif_glbl_irpt_enable_reg_reg;
output [8:0]s_axi_rdata;
input bus2ip_reset;
input s_axi_aclk;
input s_axi_arvalid;
input s_axi_aresetn;
input ip2bus_rdack_i_D1;
input ip2bus_wrack_i_D1;
input s_axi_bready;
input s_axi_rready;
input [6:0]s_axi_awaddr;
input [6:0]s_axi_araddr;
input s_axi_awvalid;
input s_axi_wvalid;
input [15:0]s_axi_wdata;
input [7:0]gpio_io_t;
input [7:0]Q;
input [0:0]p_0_in;
input irpt_rdack_d1;
input irpt_wrack_d1;
input [0:0]ip2bus_data;
input [0:0]p_3_in;
input [0:0]p_1_in;
input GPIO_xferAck_i;
input gpio_xferAck_Reg;
input ip2Bus_RdAck_intr_reg_hole_d1;
input ip2Bus_WrAck_intr_reg_hole_d1;
input [8:0]\ip2bus_data_i_D1_reg[0]_0 ;
wire Bus_RNW_reg;
wire [7:0]D;
wire [0:0]E;
wire [0:0]GPIO_DBus_i;
wire GPIO_xferAck_i;
wire \INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_reg ;
wire \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_reg ;
wire \Not_Dual.READ_REG_GEN[1].GPIO_DBus_i_reg[25] ;
wire \Not_Dual.READ_REG_GEN[2].GPIO_DBus_i_reg[26] ;
wire \Not_Dual.READ_REG_GEN[3].GPIO_DBus_i_reg[27] ;
wire \Not_Dual.READ_REG_GEN[4].GPIO_DBus_i_reg[28] ;
wire \Not_Dual.READ_REG_GEN[5].GPIO_DBus_i_reg[29] ;
wire \Not_Dual.READ_REG_GEN[6].GPIO_DBus_i_reg[30] ;
wire \Not_Dual.READ_REG_GEN[7].GPIO_DBus_i_reg[31] ;
wire [0:0]\Not_Dual.gpio_Data_Out_reg[0] ;
wire [7:0]Q;
wire Read_Reg_Rst;
wire [0:0]bus2ip_cs;
wire bus2ip_reset;
wire bus2ip_rnw;
wire [7:0]gpio_io_t;
wire gpio_xferAck_Reg;
wire interrupt_wrce_strb;
wire intr2bus_rdack0;
wire intr_rd_ce_or_reduce;
wire intr_wr_ce_or_reduce;
wire ip2Bus_RdAck_intr_reg_hole_d1;
wire ip2Bus_WrAck_intr_reg_hole_d1;
wire [0:0]ip2bus_data;
wire [1:0]\ip2bus_data_i_D1_reg[0] ;
wire [8:0]\ip2bus_data_i_D1_reg[0]_0 ;
wire ip2bus_rdack_i_D1;
wire ip2bus_wrack_i_D1;
wire \ip_irpt_enable_reg_reg[0] ;
wire ipif_glbl_irpt_enable_reg_reg;
wire irpt_rdack;
wire irpt_rdack_d1;
wire irpt_wrack;
wire irpt_wrack_d1;
wire [0:0]p_0_in;
wire [0:0]p_1_in;
wire [0:0]p_3_in;
wire p_8_in;
wire s_axi_aclk;
wire [6:0]s_axi_araddr;
wire s_axi_aresetn;
wire s_axi_arready;
wire s_axi_arvalid;
wire [6:0]s_axi_awaddr;
wire s_axi_awvalid;
wire s_axi_bready;
wire s_axi_bvalid;
wire [8:0]s_axi_rdata;
wire s_axi_rready;
wire s_axi_rvalid;
wire [15:0]s_axi_wdata;
wire s_axi_wready;
wire s_axi_wvalid;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_slave_attachment I_SLAVE_ATTACHMENT
(.D(D),
.E(E),
.GPIO_DBus_i(GPIO_DBus_i),
.GPIO_xferAck_i(GPIO_xferAck_i),
.\INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_reg (\INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_reg ),
.\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_reg (\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_reg ),
.\Not_Dual.READ_REG_GEN[1].GPIO_DBus_i_reg[25] (\Not_Dual.READ_REG_GEN[1].GPIO_DBus_i_reg[25] ),
.\Not_Dual.READ_REG_GEN[2].GPIO_DBus_i_reg[26] (\Not_Dual.READ_REG_GEN[2].GPIO_DBus_i_reg[26] ),
.\Not_Dual.READ_REG_GEN[3].GPIO_DBus_i_reg[27] (\Not_Dual.READ_REG_GEN[3].GPIO_DBus_i_reg[27] ),
.\Not_Dual.READ_REG_GEN[4].GPIO_DBus_i_reg[28] (\Not_Dual.READ_REG_GEN[4].GPIO_DBus_i_reg[28] ),
.\Not_Dual.READ_REG_GEN[5].GPIO_DBus_i_reg[29] (\Not_Dual.READ_REG_GEN[5].GPIO_DBus_i_reg[29] ),
.\Not_Dual.READ_REG_GEN[6].GPIO_DBus_i_reg[30] (\Not_Dual.READ_REG_GEN[6].GPIO_DBus_i_reg[30] ),
.\Not_Dual.READ_REG_GEN[7].GPIO_DBus_i_reg[31] (\Not_Dual.READ_REG_GEN[7].GPIO_DBus_i_reg[31] ),
.\Not_Dual.gpio_Data_Out_reg[0] (\Not_Dual.gpio_Data_Out_reg[0] ),
.\Not_Dual.gpio_Data_Out_reg[7] (bus2ip_cs),
.\Not_Dual.gpio_OE_reg[0] (bus2ip_rnw),
.Q(Q),
.Read_Reg_Rst(Read_Reg_Rst),
.bus2ip_reset(bus2ip_reset),
.gpio_io_t(gpio_io_t),
.gpio_xferAck_Reg(gpio_xferAck_Reg),
.interrupt_wrce_strb(interrupt_wrce_strb),
.intr2bus_rdack0(intr2bus_rdack0),
.intr_rd_ce_or_reduce(intr_rd_ce_or_reduce),
.intr_wr_ce_or_reduce(intr_wr_ce_or_reduce),
.ip2Bus_RdAck_intr_reg_hole_d1(ip2Bus_RdAck_intr_reg_hole_d1),
.ip2Bus_WrAck_intr_reg_hole_d1(ip2Bus_WrAck_intr_reg_hole_d1),
.ip2bus_data(ip2bus_data),
.\ip2bus_data_i_D1_reg[0] (p_8_in),
.\ip2bus_data_i_D1_reg[0]_0 (\ip2bus_data_i_D1_reg[0] ),
.\ip2bus_data_i_D1_reg[0]_1 (\ip2bus_data_i_D1_reg[0]_0 ),
.ip2bus_rdack_i_D1(ip2bus_rdack_i_D1),
.ip2bus_wrack_i_D1(ip2bus_wrack_i_D1),
.\ip_irpt_enable_reg_reg[0] (Bus_RNW_reg),
.\ip_irpt_enable_reg_reg[0]_0 (\ip_irpt_enable_reg_reg[0] ),
.ipif_glbl_irpt_enable_reg_reg(ipif_glbl_irpt_enable_reg_reg),
.irpt_rdack(irpt_rdack),
.irpt_rdack_d1(irpt_rdack_d1),
.irpt_wrack(irpt_wrack),
.irpt_wrack_d1(irpt_wrack_d1),
.p_0_in(p_0_in),
.p_1_in(p_1_in),
.p_3_in(p_3_in),
.s_axi_aclk(s_axi_aclk),
.s_axi_araddr(s_axi_araddr),
.s_axi_aresetn(s_axi_aresetn),
.s_axi_arready(s_axi_arready),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_bready(s_axi_bready),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_rdata(s_axi_rdata),
.s_axi_rready(s_axi_rready),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_wdata(s_axi_wdata),
.s_axi_wready(s_axi_wready),
.s_axi_wvalid(s_axi_wvalid));
endmodule |
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync
(D,
scndry_vect_out,
Q,
gpio_io_i,
s_axi_aclk);
output [7:0]D;
output [7:0]scndry_vect_out;
input [7:0]Q;
input [7:0]gpio_io_i;
input s_axi_aclk;
wire [7:0]D;
wire [7:0]Q;
wire [7:0]gpio_io_i;
wire s_axi_aclk;
wire s_level_out_bus_d1_cdc_to_0;
wire s_level_out_bus_d1_cdc_to_1;
wire s_level_out_bus_d1_cdc_to_2;
wire s_level_out_bus_d1_cdc_to_3;
wire s_level_out_bus_d1_cdc_to_4;
wire s_level_out_bus_d1_cdc_to_5;
wire s_level_out_bus_d1_cdc_to_6;
wire s_level_out_bus_d1_cdc_to_7;
wire s_level_out_bus_d2_0;
wire s_level_out_bus_d2_1;
wire s_level_out_bus_d2_2;
wire s_level_out_bus_d2_3;
wire s_level_out_bus_d2_4;
wire s_level_out_bus_d2_5;
wire s_level_out_bus_d2_6;
wire s_level_out_bus_d2_7;
wire s_level_out_bus_d3_0;
wire s_level_out_bus_d3_1;
wire s_level_out_bus_d3_2;
wire s_level_out_bus_d3_3;
wire s_level_out_bus_d3_4;
wire s_level_out_bus_d3_5;
wire s_level_out_bus_d3_6;
wire s_level_out_bus_d3_7;
wire [7:0]scndry_vect_out;
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d1_cdc_to_0),
.Q(s_level_out_bus_d2_0),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d1_cdc_to_1),
.Q(s_level_out_bus_d2_1),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d1_cdc_to_2),
.Q(s_level_out_bus_d2_2),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d1_cdc_to_3),
.Q(s_level_out_bus_d2_3),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d1_cdc_to_4),
.Q(s_level_out_bus_d2_4),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[5].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d1_cdc_to_5),
.Q(s_level_out_bus_d2_5),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[6].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d1_cdc_to_6),
.Q(s_level_out_bus_d2_6),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[7].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d1_cdc_to_7),
.Q(s_level_out_bus_d2_7),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d2_0),
.Q(s_level_out_bus_d3_0),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d2_1),
.Q(s_level_out_bus_d3_1),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d2_2),
.Q(s_level_out_bus_d3_2),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d2_3),
.Q(s_level_out_bus_d3_3),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d2_4),
.Q(s_level_out_bus_d3_4),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[5].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d2_5),
.Q(s_level_out_bus_d3_5),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[6].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d2_6),
.Q(s_level_out_bus_d3_6),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[7].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d2_7),
.Q(s_level_out_bus_d3_7),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d3_0),
.Q(scndry_vect_out[0]),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d3_1),
.Q(scndry_vect_out[1]),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d3_2),
.Q(scndry_vect_out[2]),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d3_3),
.Q(scndry_vect_out[3]),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d3_4),
.Q(scndry_vect_out[4]),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[5].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d3_5),
.Q(scndry_vect_out[5]),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[6].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d3_6),
.Q(scndry_vect_out[6]),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[7].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d3_7),
.Q(scndry_vect_out[7]),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[0].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_io_i[0]),
.Q(s_level_out_bus_d1_cdc_to_0),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[1].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_io_i[1]),
.Q(s_level_out_bus_d1_cdc_to_1),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[2].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_io_i[2]),
.Q(s_level_out_bus_d1_cdc_to_2),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[3].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_io_i[3]),
.Q(s_level_out_bus_d1_cdc_to_3),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[4].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_io_i[4]),
.Q(s_level_out_bus_d1_cdc_to_4),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[5].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_io_i[5]),
.Q(s_level_out_bus_d1_cdc_to_5),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[6].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_io_i[6]),
.Q(s_level_out_bus_d1_cdc_to_6),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[7].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_io_i[7]),
.Q(s_level_out_bus_d1_cdc_to_7),
.R(1'b0));
LUT2 #(
.INIT(4'h6))
\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg[0]_i_1
(.I0(Q[7]),
.I1(scndry_vect_out[7]),
.O(D[7]));
LUT2 #(
.INIT(4'h6))
\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg[1]_i_1
(.I0(Q[6]),
.I1(scndry_vect_out[6]),
.O(D[6]));
LUT2 #(
.INIT(4'h6))
\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg[2]_i_1
(.I0(Q[5]),
.I1(scndry_vect_out[5]),
.O(D[5]));
LUT2 #(
.INIT(4'h6))
\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg[3]_i_1
(.I0(Q[4]),
.I1(scndry_vect_out[4]),
.O(D[4]));
LUT2 #(
.INIT(4'h6))
\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg[4]_i_1
(.I0(Q[3]),
.I1(scndry_vect_out[3]),
.O(D[3]));
LUT2 #(
.INIT(4'h6))
\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg[5]_i_1
(.I0(Q[2]),
.I1(scndry_vect_out[2]),
.O(D[2]));
LUT2 #(
.INIT(4'h6))
\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg[6]_i_1
(.I0(Q[1]),
.I1(scndry_vect_out[1]),
.O(D[1]));
LUT2 #(
.INIT(4'h6))
\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg[7]_i_1
(.I0(Q[0]),
.I1(scndry_vect_out[0]),
.O(D[0]));
endmodule |
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix
(s_axi_aclk,
s_axi_aresetn,
s_axi_awaddr,
s_axi_awvalid,
s_axi_awready,
s_axi_wdata,
s_axi_wstrb,
s_axi_wvalid,
s_axi_wready,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_araddr,
s_axi_arvalid,
s_axi_arready,
s_axi_rdata,
s_axi_rresp,
s_axi_rvalid,
s_axi_rready,
ip2intc_irpt,
gpio_io_i,
gpio_io_o,
gpio_io_t);
(* x_interface_info = "xilinx.com:signal:clock:1.0 S_AXI_ACLK CLK" *) input s_axi_aclk;
(* x_interface_info = "xilinx.com:signal:reset:1.0 S_AXI_ARESETN RST" *) input s_axi_aresetn;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *) input [8:0]s_axi_awaddr;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI AWVALID" *) input s_axi_awvalid;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI AWREADY" *) output s_axi_awready;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI WDATA" *) input [31:0]s_axi_wdata;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI WSTRB" *) input [3:0]s_axi_wstrb;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI WVALID" *) input s_axi_wvalid;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *) output s_axi_wready;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *) output [1:0]s_axi_bresp;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *) output s_axi_bvalid;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *) input s_axi_bready;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI ARADDR" *) input [8:0]s_axi_araddr;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI ARVALID" *) input s_axi_arvalid;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI ARREADY" *) output s_axi_arready;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI RDATA" *) output [31:0]s_axi_rdata;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI RRESP" *) output [1:0]s_axi_rresp;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI RVALID" *) output s_axi_rvalid;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *) input s_axi_rready;
(* x_interface_info = "xilinx.com:signal:interrupt:1.0 IP2INTC_IRQ INTERRUPT" *) output ip2intc_irpt;
(* x_interface_info = "xilinx.com:interface:gpio:1.0 GPIO TRI_I" *) input [7:0]gpio_io_i;
(* x_interface_info = "xilinx.com:interface:gpio:1.0 GPIO TRI_O" *) output [7:0]gpio_io_o;
(* x_interface_info = "xilinx.com:interface:gpio:1.0 GPIO TRI_T" *) output [7:0]gpio_io_t;
wire [7:0]gpio_io_i;
wire [7:0]gpio_io_o;
wire [7:0]gpio_io_t;
wire ip2intc_irpt;
wire s_axi_aclk;
wire [8:0]s_axi_araddr;
wire s_axi_aresetn;
wire s_axi_arready;
wire s_axi_arvalid;
wire [8:0]s_axi_awaddr;
wire s_axi_awready;
wire s_axi_awvalid;
wire s_axi_bready;
wire [1:0]s_axi_bresp;
wire s_axi_bvalid;
wire [31:0]s_axi_rdata;
wire s_axi_rready;
wire [1:0]s_axi_rresp;
wire s_axi_rvalid;
wire [31:0]s_axi_wdata;
wire s_axi_wready;
wire [3:0]s_axi_wstrb;
wire s_axi_wvalid;
wire [31:0]NLW_U0_gpio2_io_o_UNCONNECTED;
wire [31:0]NLW_U0_gpio2_io_t_UNCONNECTED;
(* C_ALL_INPUTS = "0" *)
(* C_ALL_INPUTS_2 = "0" *)
(* C_ALL_OUTPUTS = "0" *)
(* C_ALL_OUTPUTS_2 = "0" *)
(* C_DOUT_DEFAULT = "0" *)
(* C_DOUT_DEFAULT_2 = "0" *)
(* C_FAMILY = "zynq" *)
(* C_GPIO2_WIDTH = "32" *)
(* C_GPIO_WIDTH = "8" *)
(* C_INTERRUPT_PRESENT = "1" *)
(* C_IS_DUAL = "0" *)
(* C_S_AXI_ADDR_WIDTH = "9" *)
(* C_S_AXI_DATA_WIDTH = "32" *)
(* C_TRI_DEFAULT = "-1" *)
(* C_TRI_DEFAULT_2 = "-1" *)
(* downgradeipidentifiedwarnings = "yes" *)
(* ip_group = "LOGICORE" *)
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio U0
(.gpio2_io_i({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.gpio2_io_o(NLW_U0_gpio2_io_o_UNCONNECTED[31:0]),
.gpio2_io_t(NLW_U0_gpio2_io_t_UNCONNECTED[31:0]),
.gpio_io_i(gpio_io_i),
.gpio_io_o(gpio_io_o),
.gpio_io_t(gpio_io_t),
.ip2intc_irpt(ip2intc_irpt),
.s_axi_aclk(s_axi_aclk),
.s_axi_araddr(s_axi_araddr),
.s_axi_aresetn(s_axi_aresetn),
.s_axi_arready(s_axi_arready),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awready(s_axi_awready),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_bready(s_axi_bready),
.s_axi_bresp(s_axi_bresp),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_rdata(s_axi_rdata),
.s_axi_rready(s_axi_rready),
.s_axi_rresp(s_axi_rresp),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_wdata(s_axi_wdata),
.s_axi_wready(s_axi_wready),
.s_axi_wstrb(s_axi_wstrb),
.s_axi_wvalid(s_axi_wvalid));
endmodule |
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_interrupt_control
(irpt_wrack_d1,
p_3_in,
irpt_rdack_d1,
p_1_in,
p_0_in,
IP2INTC_Irpt_i,
ip2bus_wrack_i,
ip2bus_rdack_i,
bus2ip_reset,
irpt_wrack,
s_axi_aclk,
GPIO_intr,
interrupt_wrce_strb,
irpt_rdack,
intr2bus_rdack0,
\GEN_BKEND_CE_REGISTERS[14].ce_out_i_reg[14] ,
\GEN_BKEND_CE_REGISTERS[11].ce_out_i_reg[11] ,
p_8_in,
s_axi_wdata,
Bus_RNW_reg,
ip2Bus_WrAck_intr_reg_hole,
bus2ip_rnw,
GPIO_xferAck_i,
ip2Bus_RdAck_intr_reg_hole);
output irpt_wrack_d1;
output [0:0]p_3_in;
output irpt_rdack_d1;
output [0:0]p_1_in;
output [0:0]p_0_in;
output IP2INTC_Irpt_i;
output ip2bus_wrack_i;
output ip2bus_rdack_i;
input bus2ip_reset;
input irpt_wrack;
input s_axi_aclk;
input GPIO_intr;
input interrupt_wrce_strb;
input irpt_rdack;
input intr2bus_rdack0;
input \GEN_BKEND_CE_REGISTERS[14].ce_out_i_reg[14] ;
input \GEN_BKEND_CE_REGISTERS[11].ce_out_i_reg[11] ;
input p_8_in;
input [0:0]s_axi_wdata;
input Bus_RNW_reg;
input ip2Bus_WrAck_intr_reg_hole;
input bus2ip_rnw;
input GPIO_xferAck_i;
input ip2Bus_RdAck_intr_reg_hole;
wire Bus_RNW_reg;
wire \GEN_BKEND_CE_REGISTERS[11].ce_out_i_reg[11] ;
wire \GEN_BKEND_CE_REGISTERS[14].ce_out_i_reg[14] ;
wire \GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg[0]_i_1_n_0 ;
wire \GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg[0]_i_2_n_0 ;
wire GPIO_intr;
wire GPIO_xferAck_i;
wire IP2INTC_Irpt_i;
wire bus2ip_reset;
wire bus2ip_rnw;
wire interrupt_wrce_strb;
wire intr2bus_rdack;
wire intr2bus_rdack0;
wire intr2bus_wrack;
wire ip2Bus_RdAck_intr_reg_hole;
wire ip2Bus_WrAck_intr_reg_hole;
wire ip2bus_rdack_i;
wire ip2bus_wrack_i;
wire irpt_dly1;
wire irpt_dly2;
wire irpt_rdack;
wire irpt_rdack_d1;
wire irpt_wrack;
wire irpt_wrack_d1;
wire [0:0]p_0_in;
wire [0:0]p_1_in;
wire [0:0]p_3_in;
wire p_8_in;
wire s_axi_aclk;
wire [0:0]s_axi_wdata;
FDSE \DO_IRPT_INPUT[0].GEN_POS_EDGE_DETECT.irpt_dly1_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(GPIO_intr),
.Q(irpt_dly1),
.S(bus2ip_reset));
FDSE \DO_IRPT_INPUT[0].GEN_POS_EDGE_DETECT.irpt_dly2_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(irpt_dly1),
.Q(irpt_dly2),
.S(bus2ip_reset));
LUT6 #(
.INIT(64'hF4F4F4F44FF4F4F4))
\GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg[0]_i_1
(.I0(irpt_dly2),
.I1(irpt_dly1),
.I2(p_3_in),
.I3(p_8_in),
.I4(s_axi_wdata),
.I5(\GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg[0]_i_2_n_0 ),
.O(\GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg[0]_i_1_n_0 ));
LUT2 #(
.INIT(4'hE))
\GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg[0]_i_2
(.I0(irpt_wrack_d1),
.I1(Bus_RNW_reg),
.O(\GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg[0]_i_2_n_0 ));
FDRE \GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg[0]_i_1_n_0 ),
.Q(p_3_in),
.R(bus2ip_reset));
LUT3 #(
.INIT(8'h80))
\INTR_CTRLR_GEN.ip2intc_irpt_i_1
(.I0(p_3_in),
.I1(p_1_in),
.I2(p_0_in),
.O(IP2INTC_Irpt_i));
FDRE intr2bus_rdack_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(intr2bus_rdack0),
.Q(intr2bus_rdack),
.R(bus2ip_reset));
FDRE intr2bus_wrack_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(interrupt_wrce_strb),
.Q(intr2bus_wrack),
.R(bus2ip_reset));
LUT4 #(
.INIT(16'hFEEE))
ip2bus_rdack_i_D1_i_1
(.I0(ip2Bus_RdAck_intr_reg_hole),
.I1(intr2bus_rdack),
.I2(bus2ip_rnw),
.I3(GPIO_xferAck_i),
.O(ip2bus_rdack_i));
LUT4 #(
.INIT(16'hEFEE))
ip2bus_wrack_i_D1_i_1
(.I0(ip2Bus_WrAck_intr_reg_hole),
.I1(intr2bus_wrack),
.I2(bus2ip_rnw),
.I3(GPIO_xferAck_i),
.O(ip2bus_wrack_i));
FDRE \ip_irpt_enable_reg_reg[0]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\GEN_BKEND_CE_REGISTERS[14].ce_out_i_reg[14] ),
.Q(p_1_in),
.R(bus2ip_reset));
FDRE ipif_glbl_irpt_enable_reg_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(\GEN_BKEND_CE_REGISTERS[11].ce_out_i_reg[11] ),
.Q(p_0_in),
.R(bus2ip_reset));
FDRE irpt_rdack_d1_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(irpt_rdack),
.Q(irpt_rdack_d1),
.R(bus2ip_reset));
FDRE irpt_wrack_d1_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(irpt_wrack),
.Q(irpt_wrack_d1),
.R(bus2ip_reset));
endmodule |
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_slave_attachment
(\ip2bus_data_i_D1_reg[0] ,
\Not_Dual.gpio_OE_reg[0] ,
\Not_Dual.gpio_Data_Out_reg[7] ,
\ip_irpt_enable_reg_reg[0] ,
s_axi_rvalid,
s_axi_bvalid,
s_axi_arready,
s_axi_wready,
D,
\Not_Dual.READ_REG_GEN[7].GPIO_DBus_i_reg[31] ,
\Not_Dual.READ_REG_GEN[6].GPIO_DBus_i_reg[30] ,
\Not_Dual.READ_REG_GEN[5].GPIO_DBus_i_reg[29] ,
\Not_Dual.READ_REG_GEN[4].GPIO_DBus_i_reg[28] ,
\Not_Dual.READ_REG_GEN[3].GPIO_DBus_i_reg[27] ,
\Not_Dual.READ_REG_GEN[2].GPIO_DBus_i_reg[26] ,
\Not_Dual.READ_REG_GEN[1].GPIO_DBus_i_reg[25] ,
GPIO_DBus_i,
E,
\Not_Dual.gpio_Data_Out_reg[0] ,
\ip2bus_data_i_D1_reg[0]_0 ,
intr2bus_rdack0,
irpt_rdack,
irpt_wrack,
interrupt_wrce_strb,
Read_Reg_Rst,
\INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_reg ,
intr_rd_ce_or_reduce,
\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_reg ,
intr_wr_ce_or_reduce,
\ip_irpt_enable_reg_reg[0]_0 ,
ipif_glbl_irpt_enable_reg_reg,
s_axi_rdata,
bus2ip_reset,
s_axi_aclk,
s_axi_arvalid,
s_axi_aresetn,
ip2bus_rdack_i_D1,
ip2bus_wrack_i_D1,
s_axi_bready,
s_axi_rready,
s_axi_awaddr,
s_axi_araddr,
s_axi_awvalid,
s_axi_wvalid,
s_axi_wdata,
gpio_io_t,
Q,
p_0_in,
irpt_rdack_d1,
irpt_wrack_d1,
ip2bus_data,
p_3_in,
p_1_in,
GPIO_xferAck_i,
gpio_xferAck_Reg,
ip2Bus_RdAck_intr_reg_hole_d1,
ip2Bus_WrAck_intr_reg_hole_d1,
\ip2bus_data_i_D1_reg[0]_1 );
output \ip2bus_data_i_D1_reg[0] ;
output \Not_Dual.gpio_OE_reg[0] ;
output \Not_Dual.gpio_Data_Out_reg[7] ;
output \ip_irpt_enable_reg_reg[0] ;
output s_axi_rvalid;
output s_axi_bvalid;
output s_axi_arready;
output s_axi_wready;
output [7:0]D;
output \Not_Dual.READ_REG_GEN[7].GPIO_DBus_i_reg[31] ;
output \Not_Dual.READ_REG_GEN[6].GPIO_DBus_i_reg[30] ;
output \Not_Dual.READ_REG_GEN[5].GPIO_DBus_i_reg[29] ;
output \Not_Dual.READ_REG_GEN[4].GPIO_DBus_i_reg[28] ;
output \Not_Dual.READ_REG_GEN[3].GPIO_DBus_i_reg[27] ;
output \Not_Dual.READ_REG_GEN[2].GPIO_DBus_i_reg[26] ;
output \Not_Dual.READ_REG_GEN[1].GPIO_DBus_i_reg[25] ;
output [0:0]GPIO_DBus_i;
output [0:0]E;
output [0:0]\Not_Dual.gpio_Data_Out_reg[0] ;
output [1:0]\ip2bus_data_i_D1_reg[0]_0 ;
output intr2bus_rdack0;
output irpt_rdack;
output irpt_wrack;
output interrupt_wrce_strb;
output Read_Reg_Rst;
output \INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_reg ;
output intr_rd_ce_or_reduce;
output \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_reg ;
output intr_wr_ce_or_reduce;
output \ip_irpt_enable_reg_reg[0]_0 ;
output ipif_glbl_irpt_enable_reg_reg;
output [8:0]s_axi_rdata;
input bus2ip_reset;
input s_axi_aclk;
input s_axi_arvalid;
input s_axi_aresetn;
input ip2bus_rdack_i_D1;
input ip2bus_wrack_i_D1;
input s_axi_bready;
input s_axi_rready;
input [6:0]s_axi_awaddr;
input [6:0]s_axi_araddr;
input s_axi_awvalid;
input s_axi_wvalid;
input [15:0]s_axi_wdata;
input [7:0]gpio_io_t;
input [7:0]Q;
input [0:0]p_0_in;
input irpt_rdack_d1;
input irpt_wrack_d1;
input [0:0]ip2bus_data;
input [0:0]p_3_in;
input [0:0]p_1_in;
input GPIO_xferAck_i;
input gpio_xferAck_Reg;
input ip2Bus_RdAck_intr_reg_hole_d1;
input ip2Bus_WrAck_intr_reg_hole_d1;
input [8:0]\ip2bus_data_i_D1_reg[0]_1 ;
wire [7:0]D;
wire [0:0]E;
wire [0:0]GPIO_DBus_i;
wire GPIO_xferAck_i;
wire [3:0]\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 ;
wire \INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_reg ;
wire \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_reg ;
wire \Not_Dual.READ_REG_GEN[1].GPIO_DBus_i_reg[25] ;
wire \Not_Dual.READ_REG_GEN[2].GPIO_DBus_i_reg[26] ;
wire \Not_Dual.READ_REG_GEN[3].GPIO_DBus_i_reg[27] ;
wire \Not_Dual.READ_REG_GEN[4].GPIO_DBus_i_reg[28] ;
wire \Not_Dual.READ_REG_GEN[5].GPIO_DBus_i_reg[29] ;
wire \Not_Dual.READ_REG_GEN[6].GPIO_DBus_i_reg[30] ;
wire \Not_Dual.READ_REG_GEN[7].GPIO_DBus_i_reg[31] ;
wire [0:0]\Not_Dual.gpio_Data_Out_reg[0] ;
wire \Not_Dual.gpio_Data_Out_reg[7] ;
wire \Not_Dual.gpio_OE_reg[0] ;
wire [7:0]Q;
wire Read_Reg_Rst;
wire [0:6]bus2ip_addr;
wire bus2ip_reset;
wire bus2ip_rnw_i06_out;
wire clear;
wire [7:0]gpio_io_t;
wire gpio_xferAck_Reg;
wire interrupt_wrce_strb;
wire intr2bus_rdack0;
wire intr_rd_ce_or_reduce;
wire intr_wr_ce_or_reduce;
wire ip2Bus_RdAck_intr_reg_hole_d1;
wire ip2Bus_WrAck_intr_reg_hole_d1;
wire [0:0]ip2bus_data;
wire \ip2bus_data_i_D1_reg[0] ;
wire [1:0]\ip2bus_data_i_D1_reg[0]_0 ;
wire [8:0]\ip2bus_data_i_D1_reg[0]_1 ;
wire ip2bus_rdack_i_D1;
wire ip2bus_wrack_i_D1;
wire \ip_irpt_enable_reg_reg[0] ;
wire \ip_irpt_enable_reg_reg[0]_0 ;
wire ipif_glbl_irpt_enable_reg_reg;
wire irpt_rdack;
wire irpt_rdack_d1;
wire irpt_wrack;
wire irpt_wrack_d1;
wire is_read;
wire is_read_i_1_n_0;
wire is_write;
wire is_write_i_1_n_0;
wire is_write_reg_n_0;
wire [0:0]p_0_in;
wire [1:0]p_0_out__0;
wire [0:0]p_1_in;
wire [8:2]p_1_in__0;
wire [0:0]p_3_in;
wire [3:0]plusOp;
wire s_axi_aclk;
wire [6:0]s_axi_araddr;
wire s_axi_aresetn;
wire s_axi_arready;
wire s_axi_arvalid;
wire [6:0]s_axi_awaddr;
wire s_axi_awvalid;
wire s_axi_bready;
wire s_axi_bvalid;
wire s_axi_bvalid_i_i_1_n_0;
wire [8:0]s_axi_rdata;
wire s_axi_rdata_i;
wire s_axi_rready;
wire s_axi_rvalid;
wire s_axi_rvalid_i_i_1_n_0;
wire [15:0]s_axi_wdata;
wire s_axi_wready;
wire s_axi_wvalid;
wire start2;
wire start2_i_1_n_0;
wire [1:0]state;
wire \state[1]_i_2_n_0 ;
wire \state[1]_i_3_n_0 ;
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT1 #(
.INIT(2'h1))
\INCLUDE_DPHASE_TIMER.dpto_cnt[0]_i_1
(.I0(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [0]),
.O(plusOp[0]));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT2 #(
.INIT(4'h6))
\INCLUDE_DPHASE_TIMER.dpto_cnt[1]_i_1
(.I0(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [0]),
.I1(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [1]),
.O(plusOp[1]));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT3 #(
.INIT(8'h78))
\INCLUDE_DPHASE_TIMER.dpto_cnt[2]_i_1
(.I0(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [1]),
.I1(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [0]),
.I2(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [2]),
.O(plusOp[2]));
LUT2 #(
.INIT(4'h9))
\INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_1
(.I0(state[1]),
.I1(state[0]),
.O(clear));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT4 #(
.INIT(16'h7F80))
\INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_2
(.I0(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [2]),
.I1(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [0]),
.I2(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [1]),
.I3(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [3]),
.O(plusOp[3]));
FDRE \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[0]
(.C(s_axi_aclk),
.CE(1'b1),
.D(plusOp[0]),
.Q(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [0]),
.R(clear));
FDRE \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[1]
(.C(s_axi_aclk),
.CE(1'b1),
.D(plusOp[1]),
.Q(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [1]),
.R(clear));
FDRE \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[2]
(.C(s_axi_aclk),
.CE(1'b1),
.D(plusOp[2]),
.Q(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [2]),
.R(clear));
FDRE \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]
(.C(s_axi_aclk),
.CE(1'b1),
.D(plusOp[3]),
.Q(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [3]),
.R(clear));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_address_decoder I_DECODER
(.D(D),
.E(E),
.GPIO_DBus_i(GPIO_DBus_i),
.GPIO_xferAck_i(GPIO_xferAck_i),
.\INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_reg (\INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_reg ),
.\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_reg (\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_reg ),
.\Not_Dual.READ_REG_GEN[1].GPIO_DBus_i_reg[25] (\Not_Dual.READ_REG_GEN[1].GPIO_DBus_i_reg[25] ),
.\Not_Dual.READ_REG_GEN[2].GPIO_DBus_i_reg[26] (\Not_Dual.READ_REG_GEN[2].GPIO_DBus_i_reg[26] ),
.\Not_Dual.READ_REG_GEN[3].GPIO_DBus_i_reg[27] (\Not_Dual.READ_REG_GEN[3].GPIO_DBus_i_reg[27] ),
.\Not_Dual.READ_REG_GEN[4].GPIO_DBus_i_reg[28] (\Not_Dual.READ_REG_GEN[4].GPIO_DBus_i_reg[28] ),
.\Not_Dual.READ_REG_GEN[5].GPIO_DBus_i_reg[29] (\Not_Dual.READ_REG_GEN[5].GPIO_DBus_i_reg[29] ),
.\Not_Dual.READ_REG_GEN[6].GPIO_DBus_i_reg[30] (\Not_Dual.READ_REG_GEN[6].GPIO_DBus_i_reg[30] ),
.\Not_Dual.READ_REG_GEN[7].GPIO_DBus_i_reg[31] (\Not_Dual.READ_REG_GEN[7].GPIO_DBus_i_reg[31] ),
.\Not_Dual.gpio_Data_In_reg[0] (Q),
.\Not_Dual.gpio_Data_Out_reg[0] (\Not_Dual.gpio_Data_Out_reg[0] ),
.\Not_Dual.gpio_Data_Out_reg[7] (\Not_Dual.gpio_Data_Out_reg[7] ),
.Q(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 ),
.Read_Reg_Rst(Read_Reg_Rst),
.\bus2ip_addr_i_reg[8] ({bus2ip_addr[0],bus2ip_addr[1],bus2ip_addr[2],bus2ip_addr[3],bus2ip_addr[4],bus2ip_addr[5],bus2ip_addr[6]}),
.bus2ip_reset(bus2ip_reset),
.bus2ip_rnw_i_reg(\Not_Dual.gpio_OE_reg[0] ),
.gpio_io_t(gpio_io_t),
.gpio_xferAck_Reg(gpio_xferAck_Reg),
.interrupt_wrce_strb(interrupt_wrce_strb),
.intr2bus_rdack0(intr2bus_rdack0),
.intr_rd_ce_or_reduce(intr_rd_ce_or_reduce),
.intr_wr_ce_or_reduce(intr_wr_ce_or_reduce),
.ip2Bus_RdAck_intr_reg_hole_d1(ip2Bus_RdAck_intr_reg_hole_d1),
.ip2Bus_WrAck_intr_reg_hole_d1(ip2Bus_WrAck_intr_reg_hole_d1),
.ip2bus_data(ip2bus_data),
.\ip2bus_data_i_D1_reg[0] (\ip2bus_data_i_D1_reg[0] ),
.\ip2bus_data_i_D1_reg[0]_0 (\ip2bus_data_i_D1_reg[0]_0 ),
.ip2bus_rdack_i_D1(ip2bus_rdack_i_D1),
.ip2bus_wrack_i_D1(ip2bus_wrack_i_D1),
.\ip_irpt_enable_reg_reg[0] (\ip_irpt_enable_reg_reg[0] ),
.\ip_irpt_enable_reg_reg[0]_0 (\ip_irpt_enable_reg_reg[0]_0 ),
.ipif_glbl_irpt_enable_reg_reg(ipif_glbl_irpt_enable_reg_reg),
.irpt_rdack(irpt_rdack),
.irpt_rdack_d1(irpt_rdack_d1),
.irpt_wrack(irpt_wrack),
.irpt_wrack_d1(irpt_wrack_d1),
.is_read(is_read),
.is_write_reg(is_write_reg_n_0),
.p_0_in(p_0_in),
.p_1_in(p_1_in),
.p_3_in(p_3_in),
.s_axi_aclk(s_axi_aclk),
.s_axi_aresetn(s_axi_aresetn),
.s_axi_arready(s_axi_arready),
.s_axi_wdata(s_axi_wdata),
.s_axi_wready(s_axi_wready),
.start2(start2));
LUT5 #(
.INIT(32'hABAAA8AA))
\bus2ip_addr_i[2]_i_1
(.I0(s_axi_awaddr[0]),
.I1(state[1]),
.I2(state[0]),
.I3(s_axi_arvalid),
.I4(s_axi_araddr[0]),
.O(p_1_in__0[2]));
LUT5 #(
.INIT(32'hABAAA8AA))
\bus2ip_addr_i[3]_i_1
(.I0(s_axi_awaddr[1]),
.I1(state[1]),
.I2(state[0]),
.I3(s_axi_arvalid),
.I4(s_axi_araddr[1]),
.O(p_1_in__0[3]));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT5 #(
.INIT(32'hABAAA8AA))
\bus2ip_addr_i[4]_i_1
(.I0(s_axi_awaddr[2]),
.I1(state[1]),
.I2(state[0]),
.I3(s_axi_arvalid),
.I4(s_axi_araddr[2]),
.O(p_1_in__0[4]));
LUT5 #(
.INIT(32'hABAAA8AA))
\bus2ip_addr_i[5]_i_1
(.I0(s_axi_awaddr[3]),
.I1(state[1]),
.I2(state[0]),
.I3(s_axi_arvalid),
.I4(s_axi_araddr[3]),
.O(p_1_in__0[5]));
LUT5 #(
.INIT(32'hABAAA8AA))
\bus2ip_addr_i[6]_i_1
(.I0(s_axi_awaddr[4]),
.I1(state[1]),
.I2(state[0]),
.I3(s_axi_arvalid),
.I4(s_axi_araddr[4]),
.O(p_1_in__0[6]));
LUT5 #(
.INIT(32'hABAAA8AA))
\bus2ip_addr_i[7]_i_1
(.I0(s_axi_awaddr[5]),
.I1(state[1]),
.I2(state[0]),
.I3(s_axi_arvalid),
.I4(s_axi_araddr[5]),
.O(p_1_in__0[7]));
LUT5 #(
.INIT(32'hABAAA8AA))
\bus2ip_addr_i[8]_i_1
(.I0(s_axi_awaddr[6]),
.I1(state[1]),
.I2(state[0]),
.I3(s_axi_arvalid),
.I4(s_axi_araddr[6]),
.O(p_1_in__0[8]));
FDRE \bus2ip_addr_i_reg[2]
(.C(s_axi_aclk),
.CE(start2_i_1_n_0),
.D(p_1_in__0[2]),
.Q(bus2ip_addr[6]),
.R(bus2ip_reset));
FDRE \bus2ip_addr_i_reg[3]
(.C(s_axi_aclk),
.CE(start2_i_1_n_0),
.D(p_1_in__0[3]),
.Q(bus2ip_addr[5]),
.R(bus2ip_reset));
FDRE \bus2ip_addr_i_reg[4]
(.C(s_axi_aclk),
.CE(start2_i_1_n_0),
.D(p_1_in__0[4]),
.Q(bus2ip_addr[4]),
.R(bus2ip_reset));
FDRE \bus2ip_addr_i_reg[5]
(.C(s_axi_aclk),
.CE(start2_i_1_n_0),
.D(p_1_in__0[5]),
.Q(bus2ip_addr[3]),
.R(bus2ip_reset));
FDRE \bus2ip_addr_i_reg[6]
(.C(s_axi_aclk),
.CE(start2_i_1_n_0),
.D(p_1_in__0[6]),
.Q(bus2ip_addr[2]),
.R(bus2ip_reset));
FDRE \bus2ip_addr_i_reg[7]
(.C(s_axi_aclk),
.CE(start2_i_1_n_0),
.D(p_1_in__0[7]),
.Q(bus2ip_addr[1]),
.R(bus2ip_reset));
FDRE \bus2ip_addr_i_reg[8]
(.C(s_axi_aclk),
.CE(start2_i_1_n_0),
.D(p_1_in__0[8]),
.Q(bus2ip_addr[0]),
.R(bus2ip_reset));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT3 #(
.INIT(8'h02))
bus2ip_rnw_i_i_1
(.I0(s_axi_arvalid),
.I1(state[0]),
.I2(state[1]),
.O(bus2ip_rnw_i06_out));
FDRE bus2ip_rnw_i_reg
(.C(s_axi_aclk),
.CE(start2_i_1_n_0),
.D(bus2ip_rnw_i06_out),
.Q(\Not_Dual.gpio_OE_reg[0] ),
.R(bus2ip_reset));
LUT5 #(
.INIT(32'h3FFA000A))
is_read_i_1
(.I0(s_axi_arvalid),
.I1(\state[1]_i_2_n_0 ),
.I2(state[1]),
.I3(state[0]),
.I4(is_read),
.O(is_read_i_1_n_0));
FDRE is_read_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(is_read_i_1_n_0),
.Q(is_read),
.R(bus2ip_reset));
LUT6 #(
.INIT(64'h1000FFFF10000000))
is_write_i_1
(.I0(state[1]),
.I1(s_axi_arvalid),
.I2(s_axi_wvalid),
.I3(s_axi_awvalid),
.I4(is_write),
.I5(is_write_reg_n_0),
.O(is_write_i_1_n_0));
LUT6 #(
.INIT(64'hF88800000000FFFF))
is_write_i_2
(.I0(s_axi_bready),
.I1(s_axi_bvalid),
.I2(s_axi_rready),
.I3(s_axi_rvalid),
.I4(state[1]),
.I5(state[0]),
.O(is_write));
FDRE is_write_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(is_write_i_1_n_0),
.Q(is_write_reg_n_0),
.R(bus2ip_reset));
LUT5 #(
.INIT(32'h08FF0808))
s_axi_bvalid_i_i_1
(.I0(s_axi_wready),
.I1(state[1]),
.I2(state[0]),
.I3(s_axi_bready),
.I4(s_axi_bvalid),
.O(s_axi_bvalid_i_i_1_n_0));
FDRE #(
.INIT(1'b0))
s_axi_bvalid_i_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_axi_bvalid_i_i_1_n_0),
.Q(s_axi_bvalid),
.R(bus2ip_reset));
LUT2 #(
.INIT(4'h2))
\s_axi_rdata_i[31]_i_1
(.I0(state[0]),
.I1(state[1]),
.O(s_axi_rdata_i));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[0]
(.C(s_axi_aclk),
.CE(s_axi_rdata_i),
.D(\ip2bus_data_i_D1_reg[0]_1 [0]),
.Q(s_axi_rdata[0]),
.R(bus2ip_reset));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[1]
(.C(s_axi_aclk),
.CE(s_axi_rdata_i),
.D(\ip2bus_data_i_D1_reg[0]_1 [1]),
.Q(s_axi_rdata[1]),
.R(bus2ip_reset));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[2]
(.C(s_axi_aclk),
.CE(s_axi_rdata_i),
.D(\ip2bus_data_i_D1_reg[0]_1 [2]),
.Q(s_axi_rdata[2]),
.R(bus2ip_reset));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[31]
(.C(s_axi_aclk),
.CE(s_axi_rdata_i),
.D(\ip2bus_data_i_D1_reg[0]_1 [8]),
.Q(s_axi_rdata[8]),
.R(bus2ip_reset));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[3]
(.C(s_axi_aclk),
.CE(s_axi_rdata_i),
.D(\ip2bus_data_i_D1_reg[0]_1 [3]),
.Q(s_axi_rdata[3]),
.R(bus2ip_reset));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[4]
(.C(s_axi_aclk),
.CE(s_axi_rdata_i),
.D(\ip2bus_data_i_D1_reg[0]_1 [4]),
.Q(s_axi_rdata[4]),
.R(bus2ip_reset));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[5]
(.C(s_axi_aclk),
.CE(s_axi_rdata_i),
.D(\ip2bus_data_i_D1_reg[0]_1 [5]),
.Q(s_axi_rdata[5]),
.R(bus2ip_reset));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[6]
(.C(s_axi_aclk),
.CE(s_axi_rdata_i),
.D(\ip2bus_data_i_D1_reg[0]_1 [6]),
.Q(s_axi_rdata[6]),
.R(bus2ip_reset));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[7]
(.C(s_axi_aclk),
.CE(s_axi_rdata_i),
.D(\ip2bus_data_i_D1_reg[0]_1 [7]),
.Q(s_axi_rdata[7]),
.R(bus2ip_reset));
LUT5 #(
.INIT(32'h08FF0808))
s_axi_rvalid_i_i_1
(.I0(s_axi_arready),
.I1(state[0]),
.I2(state[1]),
.I3(s_axi_rready),
.I4(s_axi_rvalid),
.O(s_axi_rvalid_i_i_1_n_0));
FDRE #(
.INIT(1'b0))
s_axi_rvalid_i_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_axi_rvalid_i_i_1_n_0),
.Q(s_axi_rvalid),
.R(bus2ip_reset));
LUT5 #(
.INIT(32'h000000F8))
start2_i_1
(.I0(s_axi_awvalid),
.I1(s_axi_wvalid),
.I2(s_axi_arvalid),
.I3(state[0]),
.I4(state[1]),
.O(start2_i_1_n_0));
FDRE start2_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(start2_i_1_n_0),
.Q(start2),
.R(bus2ip_reset));
LUT5 #(
.INIT(32'h0FFFAACC))
\state[0]_i_1
(.I0(s_axi_wready),
.I1(s_axi_arvalid),
.I2(\state[1]_i_2_n_0 ),
.I3(state[1]),
.I4(state[0]),
.O(p_0_out__0[0]));
LUT6 #(
.INIT(64'h2E2E2E2ECCCCFFCC))
\state[1]_i_1
(.I0(s_axi_arready),
.I1(state[1]),
.I2(\state[1]_i_2_n_0 ),
.I3(\state[1]_i_3_n_0 ),
.I4(s_axi_arvalid),
.I5(state[0]),
.O(p_0_out__0[1]));
LUT4 #(
.INIT(16'hF888))
\state[1]_i_2
(.I0(s_axi_bready),
.I1(s_axi_bvalid),
.I2(s_axi_rready),
.I3(s_axi_rvalid),
.O(\state[1]_i_2_n_0 ));
LUT2 #(
.INIT(4'h8))
\state[1]_i_3
(.I0(s_axi_awvalid),
.I1(s_axi_wvalid),
.O(\state[1]_i_3_n_0 ));
FDRE \state_reg[0]
(.C(s_axi_aclk),
.CE(1'b1),
.D(p_0_out__0[0]),
.Q(state[0]),
.R(bus2ip_reset));
FDRE \state_reg[1]
(.C(s_axi_aclk),
.CE(1'b1),
.D(p_0_out__0[1]),
.Q(state[1]),
.R(bus2ip_reset));
endmodule |
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule |
module sky130_fd_sc_lp__inputiso0p (
//# {{data|Data Signals}}
input A ,
output X ,
//# {{power|Power}}
input SLEEP
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule |
module sdDualMagnitude #(
parameter WIDTH = 16,
parameter GAIN = 6
)
(
input clk, ///< System Clock
input rst, ///< Reset, active high & synchronous
input en, ///< Enable (use to clock at slower rate)
input inSin, ///< Sigma-delta input, sine channel
input inCos, ///< Sigma-delta input, cosine channel
output wire [WIDTH-1:0] out ///< Magnitude of signal
);
localparam WIDTH_WORD = 16;
reg [WIDTH+GAIN-1:0] acc;
reg [2:0] sinC;
reg [2:0] cosC;
reg [3:0] sums;
reg inCosD1;
reg inSinD1;
always @(posedge clk) begin
if (rst) begin
acc <= 'd0;
inCosD1 <= 1'b0;
inSinD1 <= 1'b0;
sinC <= 3'b000;
cosC <= 3'b000;
sums <= 4'd0;
end
else if (en) begin
inSinD1 <= inSin;
inCosD1 <= inCos;
sums <= {4{sinC[2]&cosC[2]}} | {1'b0, sinC[2]^cosC[2], sinC[1]&cosC[1], sinC[1]^cosC[1]};
sinC <= (inSin ^ inSinD1) ? 3'b001 : {|sinC[2:1], sinC[0], 1'b0};
cosC <= (inCos ^ inCosD1) ? 3'b001 : {|cosC[2:1], cosC[0], 1'b0};
acc <= acc - (acc >>> GAIN) + {sums[2], {10{sums[3]}}, sums[1], sums[0], {3{sums[3]}}};
end
end
assign out = (acc >>> GAIN);
endmodule |
module top();
// Inputs are registered
reg A;
reg B;
reg C;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
B = 1'bX;
C = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 B = 1'b0;
#60 C = 1'b0;
#80 VGND = 1'b0;
#100 VNB = 1'b0;
#120 VPB = 1'b0;
#140 VPWR = 1'b0;
#160 A = 1'b1;
#180 B = 1'b1;
#200 C = 1'b1;
#220 VGND = 1'b1;
#240 VNB = 1'b1;
#260 VPB = 1'b1;
#280 VPWR = 1'b1;
#300 A = 1'b0;
#320 B = 1'b0;
#340 C = 1'b0;
#360 VGND = 1'b0;
#380 VNB = 1'b0;
#400 VPB = 1'b0;
#420 VPWR = 1'b0;
#440 VPWR = 1'b1;
#460 VPB = 1'b1;
#480 VNB = 1'b1;
#500 VGND = 1'b1;
#520 C = 1'b1;
#540 B = 1'b1;
#560 A = 1'b1;
#580 VPWR = 1'bx;
#600 VPB = 1'bx;
#620 VNB = 1'bx;
#640 VGND = 1'bx;
#660 C = 1'bx;
#680 B = 1'bx;
#700 A = 1'bx;
end
sky130_fd_sc_hd__xor3 dut (.A(A), .B(B), .C(C), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule |
module axi_hp_abort(
input hclk,
input hrst, // just disables processing inputs
input abort,
output busy, // should disable control of afi_wvalid, afi_awid
output reg done,
input afi_awvalid, // afi_awready is supposed to be always on when afi_awvalid (caller uses fifo counetrs) ?
input afi_awready, //
input [ 5:0] afi_awid,
input [3:0] afi_awlen,
input afi_wvalid_in,
input afi_wready,
output afi_wvalid,
output reg [ 5:0] afi_wid,
input afi_arvalid,
input afi_arready,
input [ 3:0] afi_arlen,
input afi_rready_in,
input afi_rvalid,
output afi_rready,
output afi_wlast,
// TODO: Try to resolve problems when afi_racount, afi_wacount afi_wcount do not match expected
input [ 2:0] afi_racount,
input [ 7:0] afi_rcount,
input [ 5:0] afi_wacount,
input [ 7:0] afi_wcount,
output reg dirty, // single bit to be sampled in different clock domain to see if flushing is needed
output reg axi_mismatch, // calculated as 'dirty' but axi hp counters are 0
output [21:0] debug
);
reg busy_r;
wire done_w = busy_r && !dirty ;
reg [3:0] aw_lengths_ram[0:31];
reg [4:0] aw_lengths_waddr = 0;
reg [4:0] aw_lengths_raddr = 0;
reg [5:0] aw_count = 0;
reg [7:0] w_count = 0;
reg [7:0] r_count = 0;
reg adav = 0;
wire arwr = !hrst && afi_arvalid && afi_arready;
wire drd = !hrst && afi_rvalid && afi_rready_in;
wire awr = !hrst && afi_awvalid && afi_awready;
reg ard_r = 0; // additional length read if not much data
wire ard = adav && ((|w_count[7:4]) || ard_r);
wire wwr = !hrst && afi_wready && afi_wvalid_in;
reg afi_rready_r;
reg afi_wlast_r; // wait one cycle after last in each burst (just to ease timing)
reg busy_aborting; // actually aborting
wire reset_counters = busy_r && !busy_aborting;
assign busy = busy_r;
assign afi_rready = busy_aborting && (|r_count) && ((|afi_rcount[7:1]) || (!afi_rready_r && afi_rcount[0]));
assign afi_wlast = busy_aborting && adav && (w_count[3:0] == aw_lengths_ram[aw_lengths_raddr]);
assign afi_wvalid = busy_aborting && adav && !afi_wlast_r;
assign debug = {aw_count[5:0], w_count[7:0], r_count[7:0]};
// Watch for transactios performed by others (and this one too)
always @ (posedge hclk) begin
// read channel
if (reset_counters) r_count <= 0;
else if (drd)
if (arwr) r_count <= r_count + {4'b0, afi_arlen};
else r_count <= r_count - 1;
else
if (arwr) r_count <= w_count + {4'b0, afi_arlen} + 1;
// write channel
if (awr) afi_wid <= afi_awid; // one command is supposed to use just one awid/wid
if (awr) aw_lengths_ram [aw_lengths_waddr] <= afi_awlen;
if (reset_counters) aw_lengths_waddr <= 0;
else if (awr) aw_lengths_waddr <= aw_lengths_waddr + 1;
if (reset_counters) aw_lengths_raddr <= 0;
else if (ard) aw_lengths_raddr <= aw_lengths_raddr + 1;
if (reset_counters) aw_count <= 0;
else if ( awr && !ard) aw_count <= aw_count + 1;
else if (!awr && ard) aw_count <= aw_count - 1;
adav <= !reset_counters && (|aw_count[5:1]) || ((awr || aw_count[0]) && !ard) || (awr && aw_count[0]);
ard_r <= !ard && adav && (w_count[3:0] > aw_lengths_ram[aw_lengths_raddr]);
if (reset_counters) w_count <= 0;
else if (wwr)
if (ard) w_count <= w_count - {4'b0, aw_lengths_ram[aw_lengths_raddr]};
else w_count <= w_count + 1;
else
if (ard) w_count <= w_count - {4'b0, aw_lengths_ram[aw_lengths_raddr]} - 1;
dirty <= (|r_count) || (|aw_count); // assuming w_count can never be non-zero? - no
end
// flushing part
always @ (posedge hclk) begin
if (abort) busy_r <= 1;
else if (done_w) busy_r <= 0;
if (abort && ((|afi_racount) || (|afi_rcount) || (|afi_wacount) || (|afi_wcount))) busy_aborting <= 1;
else if (done_w) busy_aborting <= 0;
done <= done_w;
afi_rready_r <= afi_rready;
afi_wlast_r <= afi_wlast;
axi_mismatch <= busy && !busy_aborting && dirty; //
end
endmodule |
module - will be implemented by the testbench
.clk(clk),
.rst(rst),
// Inputs
.gm_or_lds(lsu2mem_gm_or_lds),
.rd_en(lsu2mem_rd_en),
.wr_en(lsu2mem_wr_en),
.addresses(lsu2mem_addr),
.wr_data(lsu2mem_wr_data),
.input_tag(lsu2mem_tag_req),
.wr_mask(lsu2mem_wr_mask),
// Outputs
.rd_data(mem2lsu_rd_data),
.output_tag(mem2lsu_tag_resp),
.ack(mem2lsu_ack),
.tracemon_addr(mem2tracemon_addr),
.tracemon_store_data(mem2tracemon_store_data),
.tracemon_store_en(mem2tracemon_store_en)
);
//SAIF flow
`ifdef SAIF
initial begin
$set_gate_level_monitoring("rtl_on", "mda");
$set_toggle_region(gpu_tb.DUT[0]);
#0;
$toggle_start;
end
`endif
//waveforms
initial begin
if ($test$plusargs("dump_waveforms")) begin
$vcdpluson(0,gpu_tb);
if ($test$plusargs("dump_glitches")) begin
$vcdplusdeltacycleon;
$vcdplusglitchon;
end
end
end
genvar tg;
generate
for (tg=0; tg < NUMOFCU; tg=tg+1) begin : TT
tracemon #(.CUID(tg)) tracemon0 (
// Dummy unit to aid testbench
.issue2tracemon_barrier_retire_en(issue2tracemon_barrier_retire_en),
.issue2tracemon_barrier_retire_wf_bitmap(issue2tracemon_barrier_retire_wf_bitmap),
.issue2tracemon_barrier_retire_pc(issue2tracemon_barrier_retire_pc),
.issue2tracemon_waitcnt_retire_en(issue2tracemon_waitcnt_retire_en),
.issue2tracemon_waitcnt_retire_wfid(issue2tracemon_waitcnt_retire_wfid),
.issue2tracemon_waitcnt_retire_pc(issue2tracemon_waitcnt_retire_pc),
.simd0_2tracemon_retire_pc(simd0_2tracemon_retire_pc),
.simd1_2tracemon_retire_pc(simd1_2tracemon_retire_pc),
.simd2_2tracemon_retire_pc(simd2_2tracemon_retire_pc),
.simd3_2tracemon_retire_pc(simd3_2tracemon_retire_pc),
.simf0_2tracemon_retire_pc(simf0_2tracemon_retire_pc),
.simf1_2tracemon_retire_pc(simf1_2tracemon_retire_pc),
.simf2_2tracemon_retire_pc(simf2_2tracemon_retire_pc),
.simf3_2tracemon_retire_pc(simf3_2tracemon_retire_pc),
.lsu2tracemon_retire_pc(lsu2tracemon_retire_pc),
.salu2tracemon_retire_pc(salu2tracemon_retire_pc),
.salu2tracemon_exec_word_sel(salu2tracemon_exec_word_sel),
.salu2tracemon_vcc_word_sel(salu2tracemon_vcc_word_sel),
.wave2decode_instr_valid(wave2decode_instr_valid),
.wave2decode_sgpr_base(wave2decode_sgpr_base),
.wave2decode_vgpr_base(wave2decode_vgpr_base),
.wave2decode_lds_base(wave2decode_lds_base),
.wave2decode_wfid(wave2decode_wfid),
.salu2sgpr_instr_done(salu2sgpr_instr_done),
.salu2sgpr_instr_done_wfid(salu2sgpr_instr_done_wfid),
.salu2exec_wr_exec_en(salu2exec_wr_exec_en),
.salu2exec_wr_exec_value(salu2exec_wr_exec_value),
.salu2exec_wr_vcc_en(salu2exec_wr_vcc_en),
.salu2exec_wr_vcc_value(salu2exec_wr_vcc_value),
.salu2exec_wr_scc_en(salu2exec_wr_scc_en),
.salu2exec_wr_scc_value(salu2exec_wr_scc_value),
.salu2sgpr_dest_wr_en(salu2sgpr_dest_wr_en),
.salu2sgpr_dest_addr(salu2sgpr_dest_addr),
.salu2sgpr_dest_data(salu2sgpr_dest_data),
.salu2fetchwaveissue_branch_wfid(salu2fetchwaveissue_branch_wfid),
.salu2fetchwaveissue_branch_en(salu2fetchwaveissue_branch_en),
.salu2fetchwaveissue_branch_taken(salu2fetchwaveissue_branch_taken),
.salu2fetch_branch_pc_value(salu2fetch_branch_pc_value),
.simd0_2vgpr_instr_done(simd0_2vgpr_instr_done),
.simd0_2vgpr_instr_done_wfid(simd0_2vgpr_instr_done_wfid),
.simd1_2vgpr_instr_done(simd1_2vgpr_instr_done),
.simd1_2vgpr_instr_done_wfid(simd1_2vgpr_instr_done_wfid),
.simd2_2vgpr_instr_done(simd2_2vgpr_instr_done),
.simd2_2vgpr_instr_done_wfid(simd2_2vgpr_instr_done_wfid),
.simd3_2vgpr_instr_done(simd3_2vgpr_instr_done),
.simd3_2vgpr_instr_done_wfid(simd3_2vgpr_instr_done_wfid),
.simd0_2exec_wr_vcc_en(simd0_2exec_wr_vcc_en),
.simd0_2exec_wr_vcc_value(simd0_2exec_wr_vcc_value),
.simd0_2vgpr_wr_en(simd0_2vgpr_wr_en),
.simd0_2vgpr_dest_addr(simd0_2vgpr_dest_addr),
.simd0_2vgpr_dest_data(simd0_2vgpr_dest_data),
.simd0_2vgpr_wr_mask(simd0_2vgpr_wr_mask),
.simd1_2exec_wr_vcc_en(simd1_2exec_wr_vcc_en),
.simd1_2exec_wr_vcc_value(simd1_2exec_wr_vcc_value),
.simd1_2vgpr_wr_en(simd1_2vgpr_wr_en),
.simd1_2vgpr_dest_addr(simd1_2vgpr_dest_addr),
.simd1_2vgpr_dest_data(simd1_2vgpr_dest_data),
.simd1_2vgpr_wr_mask(simd1_2vgpr_wr_mask),
.simd2_2exec_wr_vcc_en(simd2_2exec_wr_vcc_en),
.simd2_2exec_wr_vcc_value(simd2_2exec_wr_vcc_value),
.simd2_2vgpr_wr_en(simd2_2vgpr_wr_en),
.simd2_2vgpr_dest_addr(simd2_2vgpr_dest_addr),
.simd2_2vgpr_dest_data(simd2_2vgpr_dest_data),
.simd2_2vgpr_wr_mask(simd2_2vgpr_wr_mask),
.simd3_2exec_wr_vcc_en(simd3_2exec_wr_vcc_en),
.simd3_2exec_wr_vcc_value(simd3_2exec_wr_vcc_value),
.simd3_2vgpr_wr_en(simd3_2vgpr_wr_en),
.simd3_2vgpr_dest_addr(simd3_2vgpr_dest_addr),
.simd3_2vgpr_dest_data(simd3_2vgpr_dest_data),
.simd3_2vgpr_wr_mask(simd3_2vgpr_wr_mask),
.simf0_2vgpr_instr_done(simf0_2vgpr_instr_done),
.simf0_2vgpr_instr_done_wfid(simf0_2vgpr_instr_done_wfid),
.simf1_2vgpr_instr_done(simf1_2vgpr_instr_done),
.simf1_2vgpr_instr_done_wfid(simf1_2vgpr_instr_done_wfid),
.simf2_2vgpr_instr_done(simf2_2vgpr_instr_done),
.simf2_2vgpr_instr_done_wfid(simf2_2vgpr_instr_done_wfid),
.simf3_2vgpr_instr_done(simf3_2vgpr_instr_done),
.simf3_2vgpr_instr_done_wfid(simf3_2vgpr_instr_done_wfid),
.simf0_2exec_wr_vcc_en(simf0_2exec_wr_vcc_en),
.simf0_2exec_wr_vcc_value(simf0_2exec_wr_vcc_value),
.simf0_2vgpr_wr_en(simf0_2vgpr_wr_en),
.simf0_2vgpr_dest_addr(simf0_2vgpr_dest_addr),
.simf0_2vgpr_dest_data(simf0_2vgpr_dest_data),
.simf0_2vgpr_wr_mask(simf0_2vgpr_wr_mask),
.simf1_2exec_wr_vcc_en(simf1_2exec_wr_vcc_en),
.simf1_2exec_wr_vcc_value(simf1_2exec_wr_vcc_value),
.simf1_2vgpr_wr_en(simf1_2vgpr_wr_en),
.simf1_2vgpr_dest_addr(simf1_2vgpr_dest_addr),
.simf1_2vgpr_dest_data(simf1_2vgpr_dest_data),
.simf1_2vgpr_wr_mask(simf1_2vgpr_wr_mask),
.simf2_2exec_wr_vcc_en(simf2_2exec_wr_vcc_en),
.simf2_2exec_wr_vcc_value(simf2_2exec_wr_vcc_value),
.simf2_2vgpr_wr_en(simf2_2vgpr_wr_en),
.simf2_2vgpr_dest_addr(simf2_2vgpr_dest_addr),
.simf2_2vgpr_dest_data(simf2_2vgpr_dest_data),
.simf2_2vgpr_wr_mask(simf2_2vgpr_wr_mask),
.simf3_2exec_wr_vcc_en(simf3_2exec_wr_vcc_en),
.simf3_2exec_wr_vcc_value(simf3_2exec_wr_vcc_value),
.simf3_2vgpr_wr_en(simf3_2vgpr_wr_en),
.simf3_2vgpr_dest_addr(simf3_2vgpr_dest_addr),
.simf3_2vgpr_dest_data(simf3_2vgpr_dest_data),
.simf3_2vgpr_wr_mask(simf3_2vgpr_wr_mask),
.simd0_2sgpr_wr_addr(simd0_2sgpr_wr_addr),
.simd0_2sgpr_wr_en(simd0_2sgpr_wr_en),
.simd0_2sgpr_wr_data(simd0_2sgpr_wr_data),
.simd1_2sgpr_wr_addr(simd1_2sgpr_wr_addr),
.simd1_2sgpr_wr_en(simd1_2sgpr_wr_en),
.simd1_2sgpr_wr_data(simd1_2sgpr_wr_data),
.simd2_2sgpr_wr_addr(simd2_2sgpr_wr_addr),
.simd2_2sgpr_wr_en(simd2_2sgpr_wr_en),
.simd2_2sgpr_wr_data(simd2_2sgpr_wr_data),
.simd3_2sgpr_wr_addr(simd3_2sgpr_wr_addr),
.simd3_2sgpr_wr_en(simd3_2sgpr_wr_en),
.simd3_2sgpr_wr_data(simd3_2sgpr_wr_data),
.simf0_2sgpr_wr_addr(simf0_2sgpr_wr_addr),
.simf0_2sgpr_wr_en(simf0_2sgpr_wr_en),
.simf0_2sgpr_wr_data(simf0_2sgpr_wr_data),
.simf1_2sgpr_wr_addr(simf1_2sgpr_wr_addr),
.simf1_2sgpr_wr_en(simf1_2sgpr_wr_en),
.simf1_2sgpr_wr_data(simf1_2sgpr_wr_data),
.simf2_2sgpr_wr_addr(simf2_2sgpr_wr_addr),
.simf2_2sgpr_wr_en(simf2_2sgpr_wr_en),
.simf2_2sgpr_wr_data(simf2_2sgpr_wr_data),
.simf3_2sgpr_wr_addr(simf3_2sgpr_wr_addr),
.simf3_2sgpr_wr_en(simf3_2sgpr_wr_en),
.simf3_2sgpr_wr_data(simf3_2sgpr_wr_data),
.lsu2sgpr_instr_done(lsu2sgpr_instr_done),
.lsu2sgpr_instr_done_wfid(lsu2sgpr_instr_done_wfid),
.lsu2sgpr_dest_wr_en(lsu2sgpr_dest_wr_en),
.lsu2sgpr_dest_addr(lsu2sgpr_dest_addr),
.lsu2sgpr_dest_data(lsu2sgpr_dest_data),
.lsu2vgpr_instr_done(lsu2vgpr_instr_done),
.lsu2vgpr_dest_data(lsu2vgpr_dest_data),
.lsu2vgpr_dest_addr(lsu2vgpr_dest_addr),
.lsu2vgpr_dest_wr_mask(lsu2vgpr_dest_wr_mask),
.lsu2vgpr_instr_done_wfid(lsu2vgpr_instr_done_wfid),
.lsu2vgpr_dest_wr_en(lsu2vgpr_dest_wr_en),
.issue2fetchwave_wf_done_en(issue2fetchwave_wf_done_en),
.issue2fetchwave_wf_done_wf_id(issue2fetchwave_wf_done_wf_id),
.mem2tracemon_addr(mem2tracemon_addr),
.mem2tracemon_store_data(mem2tracemon_store_data),
.mem2tracemon_store_en(mem2tracemon_store_en),
.decode2tracemon_collinstr(decode2tracemon_collinstr),
.decode2tracemon_colldone(decode2tracemon_colldone),
.decode2issue_instr_pc(decode2issue_instr_pc),
.decode2issue_valid(decode2issue_valid),
.decode2issue_wfid(decode2issue_wfid),
.rfa2execvgprsgpr_select_fu(rfa2execvgprsgpr_select_fu),
.lsu2tracemon_gm_or_lds(lsu2tracemon_gm_or_lds),
.fetch2tracemon_dispatch(fetch2tracemon_dispatch),
.fetch2tracemon_wf_tag(fetch2tracemon_wf_tag),
.fetch2tracemon_new_wfid(fetch2tracemon_new_wfid),
.salu2exec_wr_m0_en(salu2exec_wr_m0_en),
.salu2exec_wr_m0_value(salu2exec_wr_m0_value),
.decode2issue_barrier(decode2issue_barrier),
.clk(clk),
.rst(rst),
.kernel_id(iter-1)
);
end
endgenerate
genvar pg;
generate
for (pg=0; pg < NUMOFCU; pg=pg+1) begin : PT
profiler #(.CUID(pg)) profiler0 (
// unit to aid in profiling
.salu2sgpr_instr_done(salu2sgpr_instr_done),
.salu2fetchwaveissue_branch_en(salu2fetchwaveissue_branch_en),
.simd0_2vgpr_instr_done(DUT[pg].simd0_2rfa_queue_entry_valid),
.simd1_2vgpr_instr_done(DUT[pg].simd1_2rfa_queue_entry_valid),
.simd2_2vgpr_instr_done(DUT[pg].simd2_2rfa_queue_entry_valid),
.simd3_2vgpr_instr_done(DUT[pg].simd3_2rfa_queue_entry_valid),
.simf0_2vgpr_instr_done(DUT[pg].simf0_2rfa_queue_entry_valid),
.simf1_2vgpr_instr_done(DUT[pg].simf1_2rfa_queue_entry_valid),
.simf2_2vgpr_instr_done(DUT[pg].simf2_2rfa_queue_entry_valid),
.simf3_2vgpr_instr_done(DUT[pg].simf3_2rfa_queue_entry_valid),
.rfa2execvgprsgpr_select_fu(rfa2execvgprsgpr_select_fu),
.lsu2vgpr_instr_done(lsu2vgpr_instr_done),
.lsu2sgpr_instr_done(lsu2sgpr_instr_done),
.salu_alu_select(DUT[pg].issue2salu_alu_select),
.simd0_alu_select(DUT[pg].issue2simd0_alu_select),
.simd1_alu_select(DUT[pg].issue2simd1_alu_select),
.simd2_alu_select(DUT[pg].issue2simd2_alu_select),
.simd3_alu_select(DUT[pg].issue2simd3_alu_select),
.simf0_alu_select(DUT[pg].issue2simf0_alu_select),
.simf1_alu_select(DUT[pg].issue2simf1_alu_select),
.simf2_alu_select(DUT[pg].issue2simf2_alu_select),
.simf3_alu_select(DUT[pg].issue2simf3_alu_select),
.lsu_select(DUT[pg].issue2lsu_lsu_select),
.clk(clk)
);
end
endgenerate
initial begin
$display("Starting");
cycle_count = 0;
//instr_count = 0;
end
initial begin
clk = 0;
while (1) begin
`ifdef GATES
$value$plusargs("CLOCKPERIOD=%d",clockperiod);
half_clockperiod = clockperiod / 2;
deassert_reset = (clockperiod * 12) + half_clockperiod + (half_clockperiod / 2);
#half_clockperiod;
if(clk == 1'b0)
begin
$display("GATES MONITOR %m : Posedge of CLK at time %t", $time);
end
`else
#2; //Period is 4 clock ticks or 4ns for rtl
`endif
clk = ~clk;
end
end
initial begin
rst = 1;
`ifdef GATES
#1;
#(deassert_reset-1);
`else
#51; //Period is 4 clock ticks; So reset is deasserted after 12.75 clock periods
`endif
rst = 0;
end
initial begin
iter = 0;
wf_rem = 0;
// maximum simulation time
$value$plusargs("KILLTIME=%d",killtime);
$display("gpu_tb.v: Setting simulation time limit of #%d", killtime);
#killtime;
$display("gpu_tb.v: Simulation terminated. Maximum simulation time of #%d reached!", killtime);
terminate();
end
always @(posedge clk) begin
if (wf_rem <= 0) begin
kern = Initialize(NUMOFCU, iter);
if (kern <= 0) terminate();
#0;
wf_rem = getTotalWavefronts();
$readmemh("instr.mem", instr_buffer0.instr_memory);
$readmemh("data.mem", memory0.data_memory);
iter = iter + 1;
end
end
always @ (posedge clk) begin
if (rst) begin
// check <= 1'b0;
dispatch2cu_wf_dispatch <= 'b0;
end
end
always @ (posedge clk) begin
cycle_count = cycle_count + 1;
if (!rst) begin
if (ScheduleWavefront()==1'b1) begin
#1
thrds = getWfNumThrds();
setVregs = getSetVregs();
setSregs = getSetSregs();
cuid = getCuId();
// set vregs
for (x = 0; x < setVregs; x++) begin
vregKey = getVregKey(x, 0);
for (y = 0; y < thrds; y++) begin
vregVal = getVregValue(x, y);
// set the vregister
for(a = 0; a < 32; a++) begin
setVregValue(cuid, y, vregKey, a, vregVal[a]);
//DUT[cuid].vgpr0.reg_file.bank[y].word[vregKey].bits[a].dff_0.state = vregVal[a];
end
end
end
// set sregs
for (z = 0; z < setSregs; z++) begin
sregKey = getSregKey(z);
sregVal = getSregValue(z);
// set the sregister
for(a = 0; a < 32; a++) begin
setSregValue(cuid, sregKey, a, sregVal[a]);
//DUT[cuid].sgpr0.sgpr_reg_file.word[sregKey].bits[a].dff_0.state = sregVal[a];
end
end
dispatch2cu_vgpr_base_dispatch <= getVregBase();
dispatch2cu_sgpr_base_dispatch <= getSregBase();
dispatch2cu_lds_base_dispatch <= getLdsBase();
vregsize <= getVregSize();
sregsize <= getSregSize();
ldssize <= getLdsSize();
dispatch2cu_start_pc_dispatch <= getPC();
dispatch2cu_wf_size_dispatch <= getWfNumThrds() - 1;
dispatch2cu_wf_tag_dispatch <= getWfTag();
dispatch2cu_wg_wf_count <= getWfCnt();
for (m = 0; m < NUMOFCU; m++) begin
// $display("CUID: %d",getCuId());
if(m==getCuId()) dispatch2cu_wf_dispatch[m] <= 1'b1;
else dispatch2cu_wf_dispatch[m] <= 1'b0;
// $display("m: %d dispatch2cu_wf_dispatch: %d",m,dispatch2cu_wf_dispatch[m]);
end
end
else begin
for ( m = 0; m < NUMOFCU; m++) begin
dispatch2cu_vgpr_base_dispatch <= 10'bx;
dispatch2cu_sgpr_base_dispatch <= 9'bx;
dispatch2cu_lds_base_dispatch <= 16'bx;
vregsize <= 10'bx;
sregsize <= 9'bx;
ldssize <= 16'bx;
dispatch2cu_start_pc_dispatch <= 32'bx;
dispatch2cu_wf_size_dispatch <= 6'bx;
dispatch2cu_wf_tag_dispatch <= 11'bx;
dispatch2cu_wf_dispatch[m] <= 1'b0;
end
end
if(|{dispatch2cu_wf_dispatch, cu2dispatch_wf_done})
$display ("--------------------------------------");
for(n=0; n<NUMOFCU; n++) begin
if(|{dispatch2cu_wf_dispatch[n], cu2dispatch_wf_done[n]})
$display ("Time: %g CU: %d Dispatch: %b cu2dispatch_wf_done: %b", $time, n, dispatch2cu_wf_dispatch[n], cu2dispatch_wf_done[n]);
end
if(|dispatch2cu_wf_dispatch) begin
$display ("VGPR_Size value: %d", vregsize);
$display ("SREG_Size value: %d", sregsize);
$display ("LDS_Size value: %d", ldssize);
$display ("PC value: %d", dispatch2cu_start_pc_dispatch);
$display ("WFID: %d", dispatch2cu_wf_tag_dispatch);
end
end
end
always @ (posedge clk) begin
for(n=0; n<NUMOFCU; n++) begin
if (cu2dispatch_wf_done[n]) begin
DescheduleWavefront(n, cu2dispatch_wf_tag_done[((n * 15) + 14)-:15]); // cuid
$display("Descheduled WFID: %d from CU: %d", cu2dispatch_wf_tag_done[((n * 15) + 14)-:15], n);
$display ("--------------------------------------");
wf_rem = wf_rem - 1;
$display("Wavefronts remaining : %d", wf_rem);
end
end
end
fault_injection fault_injector(.clk(clk));
task terminate;
begin
`ifdef SAIF
$toggle_stop;
$toggle_report("backward.saif",1.0e-9,"gpu_tb.DUT[0]");
`endif
$finish;
end
endtask
endmodule |
module sky130_fd_sc_hd__dlxbp (
Q ,
Q_N ,
D ,
GATE,
VPWR,
VGND,
VPB ,
VNB
);
output Q ;
output Q_N ;
input D ;
input GATE;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule |
module sky130_fd_sc_hvl__dfsbp (
Q ,
Q_N ,
CLK ,
D ,
SET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
output Q_N ;
input CLK ;
input D ;
input SET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire buf_Q ;
wire SET ;
wire buf0_out_Q ;
wire not1_out_qn;
// Delay Name Output Other arguments
not not0 (SET , SET_B );
sky130_fd_sc_hvl__udp_dff$PS_pp$PG$N `UNIT_DELAY dff0 (buf_Q , D, CLK, SET, , VPWR, VGND);
buf buf0 (buf0_out_Q , buf_Q );
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (Q , buf0_out_Q, VPWR, VGND );
not not1 (not1_out_qn, buf_Q );
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp1 (Q_N , not1_out_qn, VPWR, VGND );
endmodule |
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