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module adc_clk_gen (/*AUTOARG*/
// Outputs
adc_clk,
// Inputs
wb_clk, rst_pad_i, clk_speed_select
) ;
input wb_clk;
input rst_pad_i;
input [2:0] clk_speed_select;
output reg adc_clk;
reg [15:0] adc_clk_count;
wire [7:0] adc_clk_count_terminal = (1 << clk_speed_select)-1;
always @(posedge wb_clk)
if (rst_pad_i) begin
adc_clk <= 0;
adc_clk_count <= 0;
end else begin
adc_clk_count <= adc_clk_count+1;
if (adc_clk_count >= adc_clk_count_terminal) begin
adc_clk <= ~adc_clk;
adc_clk_count <= 0;
end
end
endmodule |
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(clk, probe0, probe1, probe2, probe3, probe4, probe5,
probe6, probe7, probe8, probe9, probe10, probe11, probe12, probe13, probe14, probe15, probe16, probe17,
probe18, probe19, probe20, probe21, probe22, probe23, probe24, probe25)
/* synthesis syn_black_box black_box_pad_pin="clk,probe0[63:0],probe1[63:0],probe2[0:0],probe3[0:0],probe4[0:0],probe5[0:0],probe6[0:0],probe7[63:0],probe8[0:0],probe9[0:0],probe10[0:0],probe11[0:0],probe12[63:0],probe13[0:0],probe14[0:0],probe15[0:0],probe16[0:0],probe17[0:0],probe18[7:0],probe19[8:0],probe20[0:0],probe21[2:0],probe22[2:0],probe23[0:0],probe24[7:0],probe25[0:0]" */;
input clk;
input [63:0]probe0;
input [63:0]probe1;
input [0:0]probe2;
input [0:0]probe3;
input [0:0]probe4;
input [0:0]probe5;
input [0:0]probe6;
input [63:0]probe7;
input [0:0]probe8;
input [0:0]probe9;
input [0:0]probe10;
input [0:0]probe11;
input [63:0]probe12;
input [0:0]probe13;
input [0:0]probe14;
input [0:0]probe15;
input [0:0]probe16;
input [0:0]probe17;
input [7:0]probe18;
input [8:0]probe19;
input [0:0]probe20;
input [2:0]probe21;
input [2:0]probe22;
input [0:0]probe23;
input [7:0]probe24;
input [0:0]probe25;
endmodule |
module regstatus (
input clk,
input rst,
input wr_regs_en,
input [4:0] wr_regs_tag,
input [3:0] wr_regs_rb_tag,
input [4:0] rd_reg_tag1,
input [4:0] rd_reg_tag2,
input commit_en,
input [4:0] commit_reg_tag,
input flush_regs,
output [3:0] rd_rb_tag1,
output rd_bsy1,
output [3:0] rd_rb_tag2,
output rd_bsy2
);
typedef struct packed {
bit [3:0] rb_tag;
bit bsy;
}regstatusStruct;
regstatusStruct regs_array [31:0];
always @(posedge clk, negedge rst) begin
if (!rst) begin
for ( int i = 0; i < $size(regs_array); i++) begin
regs_array[i] <= {$size(regstatusStruct){1'b0}};
end
end
else begin
if (flush_regs) begin
for ( int i = 0; i < $size(regs_array); i++) begin
regs_array[i] <= {$size(regstatusStruct){1'b0}};
end
end
else begin
if (wr_regs_en) begin
regs_array[wr_regs_tag].rb_tag <= wr_regs_rb_tag;
regs_array[wr_regs_tag].bsy <= 1'b1;
end
if (commit_en) begin
//wr_regs_en has higher priority
if (!(wr_regs_en && wr_regs_tag == commit_reg_tag)) begin
regs_array[commit_reg_tag].bsy <= 1'b0;
end
end
end
end
end // always @ (posedge clk, negedge rst)
assign rd_rb_tag1 = regs_array[rd_reg_tag1].rb_tag;
assign rd_bsy1 = regs_array[rd_reg_tag1].bsy;
assign rd_rb_tag2 = regs_array[rd_reg_tag2].rb_tag;
assign rd_bsy2 = regs_array[rd_reg_tag2].bsy;
endmodule |
module car(
clka,
addra,
douta
);
input clka;
input [12 : 0] addra;
output [11 : 0] douta;
// synthesis translate_off
BLK_MEM_GEN_V7_3 #(
.C_ADDRA_WIDTH(13),
.C_ADDRB_WIDTH(13),
.C_ALGORITHM(1),
.C_AXI_ID_WIDTH(4),
.C_AXI_SLAVE_TYPE(0),
.C_AXI_TYPE(1),
.C_BYTE_SIZE(9),
.C_COMMON_CLK(0),
.C_DEFAULT_DATA("0"),
.C_DISABLE_WARN_BHV_COLL(0),
.C_DISABLE_WARN_BHV_RANGE(0),
.C_ENABLE_32BIT_ADDRESS(0),
.C_FAMILY("artix7"),
.C_HAS_AXI_ID(0),
.C_HAS_ENA(0),
.C_HAS_ENB(0),
.C_HAS_INJECTERR(0),
.C_HAS_MEM_OUTPUT_REGS_A(0),
.C_HAS_MEM_OUTPUT_REGS_B(0),
.C_HAS_MUX_OUTPUT_REGS_A(0),
.C_HAS_MUX_OUTPUT_REGS_B(0),
.C_HAS_REGCEA(0),
.C_HAS_REGCEB(0),
.C_HAS_RSTA(0),
.C_HAS_RSTB(0),
.C_HAS_SOFTECC_INPUT_REGS_A(0),
.C_HAS_SOFTECC_OUTPUT_REGS_B(0),
.C_INIT_FILE("BlankString"),
.C_INIT_FILE_NAME("car.mif"),
.C_INITA_VAL("0"),
.C_INITB_VAL("0"),
.C_INTERFACE_TYPE(0),
.C_LOAD_INIT_FILE(1),
.C_MEM_TYPE(3),
.C_MUX_PIPELINE_STAGES(0),
.C_PRIM_TYPE(1),
.C_READ_DEPTH_A(6000),
.C_READ_DEPTH_B(6000),
.C_READ_WIDTH_A(12),
.C_READ_WIDTH_B(12),
.C_RST_PRIORITY_A("CE"),
.C_RST_PRIORITY_B("CE"),
.C_RST_TYPE("SYNC"),
.C_RSTRAM_A(0),
.C_RSTRAM_B(0),
.C_SIM_COLLISION_CHECK("ALL"),
.C_USE_BRAM_BLOCK(0),
.C_USE_BYTE_WEA(0),
.C_USE_BYTE_WEB(0),
.C_USE_DEFAULT_DATA(0),
.C_USE_ECC(0),
.C_USE_SOFTECC(0),
.C_WEA_WIDTH(1),
.C_WEB_WIDTH(1),
.C_WRITE_DEPTH_A(6000),
.C_WRITE_DEPTH_B(6000),
.C_WRITE_MODE_A("WRITE_FIRST"),
.C_WRITE_MODE_B("WRITE_FIRST"),
.C_WRITE_WIDTH_A(12),
.C_WRITE_WIDTH_B(12),
.C_XDEVICEFAMILY("artix7")
)
inst (
.CLKA(clka),
.ADDRA(addra),
.DOUTA(douta),
.RSTA(),
.ENA(),
.REGCEA(),
.WEA(),
.DINA(),
.CLKB(),
.RSTB(),
.ENB(),
.REGCEB(),
.WEB(),
.ADDRB(),
.DINB(),
.DOUTB(),
.INJECTSBITERR(),
.INJECTDBITERR(),
.SBITERR(),
.DBITERR(),
.RDADDRECC(),
.S_ACLK(),
.S_ARESETN(),
.S_AXI_AWID(),
.S_AXI_AWADDR(),
.S_AXI_AWLEN(),
.S_AXI_AWSIZE(),
.S_AXI_AWBURST(),
.S_AXI_AWVALID(),
.S_AXI_AWREADY(),
.S_AXI_WDATA(),
.S_AXI_WSTRB(),
.S_AXI_WLAST(),
.S_AXI_WVALID(),
.S_AXI_WREADY(),
.S_AXI_BID(),
.S_AXI_BRESP(),
.S_AXI_BVALID(),
.S_AXI_BREADY(),
.S_AXI_ARID(),
.S_AXI_ARADDR(),
.S_AXI_ARLEN(),
.S_AXI_ARSIZE(),
.S_AXI_ARBURST(),
.S_AXI_ARVALID(),
.S_AXI_ARREADY(),
.S_AXI_RID(),
.S_AXI_RDATA(),
.S_AXI_RRESP(),
.S_AXI_RLAST(),
.S_AXI_RVALID(),
.S_AXI_RREADY(),
.S_AXI_INJECTSBITERR(),
.S_AXI_INJECTDBITERR(),
.S_AXI_SBITERR(),
.S_AXI_DBITERR(),
.S_AXI_RDADDRECC()
);
// synthesis translate_on
endmodule |
module SPI_AD(
input SPI_CLK,
input New_Word,
input [12:0] Addr,
input [7:0] Data,
output reg [7:0] q,
input RW, //1 Write; 0 :read
output reg SPI_CS,
inout reg SPI_Data,
output reg Over
);
reg [15:0] CMD;
reg [7:0] Wr_Data;
reg [7:0] SPI_Counter;
always @(negedge SPI_CLK or posedge New_Word ) begin
if(New_Word) begin
CMD <={RW,1'b0,1'b0,Addr[12:0]};
Wr_Data <= Data;
SPI_Counter <= 8'd0;
Over <= 1'b0;
SPI_CS <= 1'b1;
SPI_Data <= 1'b0;
end
else begin
if(SPI_Counter <8'd16) begin // first CMD
SPI_Counter <= SPI_Counter + 1'b1;
SPI_Data <= CMD[15];
CMD <= CMD <<1;
SPI_CS <= 1'b0;
q <= 8'd00;
end
else if(SPI_Counter <8'd24) begin //Data
SPI_Counter <= SPI_Counter + 1'b1;
if(RW) begin
q <= {q[6:0],SPI_Data};
SPI_Data <= 1'bz;
end
else begin
SPI_Data <= Wr_Data[7];
Wr_Data <= Wr_Data <<1;
end
SPI_CS <= 1'b0;
end
else if(SPI_Counter <8'd25) begin //Data
SPI_Counter <= SPI_Counter + 1'b1;
if(RW) begin
q <= {q[6:0],SPI_Data};
SPI_Data <= 1'bz;
end
SPI_CS <= 1'b1;
end
else if(SPI_Counter <8'd32) begin // interval
SPI_Counter <= SPI_Counter + 1'b1;
SPI_CS <= 1'b1;
SPI_Data <= 1'bz;
Over <= 1'b1;
end
else begin
SPI_Data <= 1'bz;
SPI_CS <= 1'b1;
Over <= 1'b1;
end
end
end
endmodule |
module pdp1_alu(al_op, al_a, al_b, al_r, al_ovfl, al_w);
parameter pdp_model = "PDP-1D";
input [0:4] al_op;
input [0:17] al_a;
input [0:17] al_b;
output reg [0:17] al_r;
output reg al_ovfl;
output reg al_w;
wire [0:17] w_add_opa;
wire [0:17] w_add_opb;
assign w_add_opa = (al_op == `PDP1_OP_ISP |
al_op == `PDP1_OP_IDX) ? 18'h1 : al_a;
assign w_add_opb = (al_op == `PDP1_OP_SUB) ? ~al_b : al_b;
wire [0:17] w_add_immed1;
wire [0:17] w_add_result;
wire [0:17] w_add_normalized;
wire w_add_ovfl;
assign {w_add_ovfl, w_add_immed1} = w_add_opa + w_add_opb;
assign w_add_result = (w_add_ovfl) ? (w_add_immed1) + 1 : w_add_immed1;
assign w_add_normalized = (&w_add_result) ? 18'h0 : w_add_result;
always @(al_op or al_a or al_b or w_add_result or
w_add_normalized or w_add_ovfl) begin
al_w = 1'b1;
case(al_op)
`PDP1_OP_ADD,
`PDP1_OP_SUB:
begin
al_r <= w_add_normalized;
al_ovfl <= (~w_add_opa[0] ^ w_add_opb[0]) &
(w_add_opa[0] ^ w_add_result[0]);
end
`PDP1_OP_ISP,
`PDP1_OP_IDX:
begin
al_r <= w_add_normalized;
al_ovfl <= 0;
end
`PDP1_OP_AND:
al_r <= al_a & al_b;
`PDP1_OP_XOR:
al_r <= al_a ^ al_b;
`PDP1_OP_IOR:
al_r <= al_a | al_b;
default:
{al_ovfl, al_r, al_w} <= 0;
endcase // case (al_op)
end
endmodule |
module bw_ctu_pad_cluster (
// Inouts:
jclk , // Differential System Clock Inputs
tsr_testio , // Tempsensor test signals
vddo , // 1.5V vdd
vdda // 1.8V analog vdd
);
inout [1:0] jclk;
inout [1:0] tsr_testio;
inout vddo;
inout vdda;
//synopsys translate_off
//synopsys translate_on
endmodule |
module PE(clk, reset, ctrl, d0, d1, d2, out);
input clk;
input reset;
input [10:0] ctrl;
input [197:0] d0;
input [`WIDTH:0] d1, d2;
output [`WIDTH:0] out;
reg [197:0] R0;
reg [`WIDTH:0] R1, R2, R3;
wire [1:0] e0, e1, e2; /* part of R0 */
wire [`WIDTH:0] ppg0, ppg1, ppg2, /* output of PPG */
mx0, mx1, mx2, mx3, mx4, mx5, mx6, /* output of MUX */
ad0, ad1, ad2, /* output of GF(3^m) adder */
cu0, cu1, cu2, /* output of cubic */
mo0, mo1, mo2, /* output of mod_p */
t0, t1, t2;
wire c0,c1,c2,c3,c4,c5,c6,c7,c8,c9,c10;
assign {c0,c1,c2,c3,c4,c5,c6,c7,c8,c9,c10} = ctrl;
assign mx0 = c0 ? d1 : ad2;
assign mx1 = c2 ? d2 : ad2;
always @ (posedge clk)
if(reset) R1 <= 0;
else if (c1) R1 <= mx0;
always @ (posedge clk)
if(reset) R2 <= 0;
else if (c3) R2 <= mx1;
always @ (posedge clk)
if(reset) R0 <= 0;
else if (c4) R0 <= d0;
else if (c5) R0 <= R0 << 6;
assign {e2,e1,e0} = R0[197:192];
PPG
ppg_0 (e0, R1, ppg0),
ppg_1 (e1, R2, ppg1),
ppg_2 (e2, R1, ppg2);
v0 v0_ (ppg0, cu0);
v1 v1_ (ppg1, cu1);
v2 v2_ (ppg2, cu2);
assign mx2 = c6 ? ppg0 : cu0;
assign mx3 = c6 ? ppg1 : cu1;
assign mx4 = c6 ? mo1 : cu2;
assign mx5 = c7 ? mo2 : R3;
mod_p
mod_p_0 (mx3, mo0),
mod_p_1 (ppg2, t0),
mod_p_2 (t0, mo1),
mod_p_3 (R3, t1),
mod_p_4 (t1, t2),
mod_p_5 (t2, mo2);
assign mx6 = c9 ? mo0 : mx3;
f3m_add
f3m_add_0 (mx2, mx6, ad0),
f3m_add_1 (mx4, c8 ? mx5 : 0, ad1),
f3m_add_2 (ad0, ad1, ad2);
always @ (posedge clk)
if (reset) R3 <= 0;
else if (c10) R3 <= ad2;
else R3 <= 0; /* change */
assign out = R3;
endmodule |
module mod_p(B, C);
input [`WIDTH:0] B;
output [`WIDTH:0] C;
wire [`WIDTH+2:0] A;
assign A = {B[`WIDTH:0], 2'd0}; // A == B*x
wire [1:0] w0;
f3_mult m0 (A[195:194], 2'd2, w0);
f3_add s0 (A[1:0], {w0[0], w0[1]}, C[1:0]); //f3_sub s0 (A[1:0], w0, C[1:0]);
assign C[23:2] = A[23:2];
wire [1:0] w12;
f3_mult m12 (A[195:194], 2'd1, w12);
f3_add s12 (A[25:24], {w12[0], w12[1]}, C[25:24]); // f3_sub s12 (A[25:24], w12, C[25:24]);
assign C[193:26] = A[193:26];
endmodule |
module PPG(d, A, C);
input [1:0] d;
input [`WIDTH:0] A;
output [`WIDTH:0] C;
genvar i;
generate
for (i=0; i < `M; i=i+1)
begin: ppg0
f3_mult f3_mult_0 (d, A[2*i+1:2*i], C[2*i+1:2*i]);
end
endgenerate
endmodule |
module f3m_add(A, B, C);
input [`WIDTH : 0] A, B;
output [`WIDTH : 0] C;
genvar i;
generate
for(i=0; i<`M; i=i+1) begin: aa
f3_add aa(A[(2*i+1) : 2*i], B[(2*i+1) : 2*i], C[(2*i+1) : 2*i]);
end
endgenerate
endmodule |
module f3_add(A, B, C);
input [1:0] A, B;
output [1:0] C;
wire a0, a1, b0, b1, c0, c1;
assign {a1, a0} = A;
assign {b1, b0} = B;
assign C = {c1, c0};
assign c0 = ( a0 & ~a1 & ~b0 & ~b1) |
(~a0 & ~a1 & b0 & ~b1) |
(~a0 & a1 & ~b0 & b1) ;
assign c1 = (~a0 & a1 & ~b0 & ~b1) |
( a0 & ~a1 & b0 & ~b1) |
(~a0 & ~a1 & ~b0 & b1) ;
endmodule |
module f3_mult(A, B, C);
input [1:0] A;
input [1:0] B;
output [1:0] C;
wire a0, a1, b0, b1;
assign {a1, a0} = A;
assign {b1, b0} = B;
assign C[0] = (~a1 & a0 & ~b1 & b0) | (a1 & ~a0 & b1 & ~b0);
assign C[1] = (~a1 & a0 & b1 & ~b0) | (a1 & ~a0 & ~b1 & b0);
endmodule |
module sky130_fd_sc_hdll__a31oi (
Y ,
A1,
A2,
A3,
B1
);
output Y ;
input A1;
input A2;
input A3;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule |
module sky130_fd_sc_hs__dfsbp_2 (
CLK ,
D ,
Q ,
Q_N ,
SET_B,
VPWR ,
VGND
);
input CLK ;
input D ;
output Q ;
output Q_N ;
input SET_B;
input VPWR ;
input VGND ;
sky130_fd_sc_hs__dfsbp base (
.CLK(CLK),
.D(D),
.Q(Q),
.Q_N(Q_N),
.SET_B(SET_B),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule |
module sky130_fd_sc_hs__dfsbp_2 (
CLK ,
D ,
Q ,
Q_N ,
SET_B
);
input CLK ;
input D ;
output Q ;
output Q_N ;
input SET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__dfsbp base (
.CLK(CLK),
.D(D),
.Q(Q),
.Q_N(Q_N),
.SET_B(SET_B)
);
endmodule |
module top (
input CLK,
input RX,
output TX,
output reg LED1,
output reg LED2,
output reg LED3,
output reg LED4,
output reg LED5
);
parameter integer BAUD_RATE = 9600;
parameter integer CLOCK_FREQ_HZ = 12000000;
localparam integer HALF_PERIOD = CLOCK_FREQ_HZ / (2 * BAUD_RATE);
reg [7:0] buffer;
reg buffer_valid;
reg [$clog2(3*HALF_PERIOD):0] cycle_cnt;
reg [3:0] bit_cnt = 0;
reg recv = 0;
initial begin
LED1 = 0;
LED2 = 0;
LED3 = 0;
LED4 = 0;
LED5 = 0;
end
always @(posedge CLK) begin
buffer_valid <= 0;
if (!recv) begin
if (!RX) begin
cycle_cnt <= HALF_PERIOD;
bit_cnt <= 0;
recv <= 1;
end
end else begin
if (cycle_cnt == 2*HALF_PERIOD) begin
cycle_cnt <= 0;
bit_cnt <= bit_cnt + 1;
if (bit_cnt == 9) begin
buffer_valid <= 1;
recv <= 0;
end else begin
buffer <= {RX, buffer[7:1]};
end
end else begin
cycle_cnt <= cycle_cnt + 1;
end
end
end
always @(posedge CLK) begin
if (buffer_valid) begin
if (buffer == "1") LED1 <= !LED1;
if (buffer == "2") LED2 <= !LED2;
if (buffer == "3") LED3 <= !LED3;
if (buffer == "4") LED4 <= !LED4;
if (buffer == "5") LED5 <= !LED5;
end
end
assign TX = RX;
endmodule |
module aes_8_bit (rst, clk, key_in, d_in, d_out, d_vld);
input rst, clk;
input [7:0] key_in;
input [7:0] d_in;
output [7:0] d_out;
output reg d_vld;
//key scheduler controller
wire [3:0] round_cnt_w;
reg input_sel, sbox_sel, last_out_sel, bit_out_sel;
reg [7:0] rcon_en;
reg [3:0] cnt;
reg [7:0] round_cnt;
reg [2:0] state;
wire [7:0] rk_delayed_out, rk_last_out;
reg [1:0] c3;
wire pld;
reg [7:0] mc_en_reg;
reg pld_reg;
wire [7:0] mc_en;
reg [7:0] d_out;
wire [7:0] d_out_w;
always @ (posedge clk)
begin
d_out <= d_out_w;
end
assign pld = pld_reg;
assign mc_en = mc_en_reg;
assign round_cnt_w = round_cnt[7:4];
key_expansion key (key_in, rk_delayed_out, round_cnt_w, rk_last_out, clk, input_sel, sbox_sel, last_out_sel, bit_out_sel, rcon_en);
aes_data_path data_path (d_in, d_out_w, pld, c3, clk, mc_en, rk_delayed_out, rk_last_out);
parameter load = 3'h0; //load 16 byte
parameter b1st = 3'h1; //first byte need rcon
parameter b2nd = 3'h2; //2byte go through sbox
parameter b3rd = 3'h3; //last byte go through sbox from redundant register
parameter norm = 3'h4; //normal round calculate two columns
parameter shif = 3'h5; //shift 4 byte
//state machine for key schedule
always @ (posedge clk)
begin
if (rst == 1'b1)
begin
state <= load;
cnt <= 4'h0;
end
else
begin
case (state)
load:
begin
cnt <= cnt + 4'h1;
if (cnt == 4'hf)
begin
state <= b1st;
cnt <= 4'h0;
end
end
b1st:
begin
state <= b2nd;
cnt <= 4'h0;
end
b2nd:
begin
cnt <= cnt + 4'h1;
if (cnt == 4'h1)
begin
state <= b3rd;
cnt <= 4'h0;
end
end
b3rd:
begin
state <= norm;
cnt <= 4'h0;
end
norm:
begin
cnt <= cnt + 4'h1;
if(cnt == 4'h7)
begin
state <= shif;
cnt <= 4'h0;
end
end
shif:
begin
cnt <= cnt + 4'h1;
if(cnt == 4'h3)
begin
state <= b1st;
cnt <= 4'h0;
end
end
endcase
end
end
//mux select and rcon enable for key schedule
always @ (*)
begin
case(state)
load:
begin
input_sel <= 1'b0;
sbox_sel <= 1'b1;
last_out_sel <= 1'b0;
bit_out_sel <= 1'b0;
rcon_en <= 8'h00;
end
b1st:
begin
input_sel <= 1'b1;
sbox_sel <= 1'b1;
last_out_sel <= 1'b0;
bit_out_sel <= 1'b1;
rcon_en <= 8'hFF;
end
b2nd:
begin
input_sel <= 1'b1;
sbox_sel <= 1'b1;
last_out_sel <= 1'b0;
bit_out_sel <= 1'b1;
rcon_en <= 8'h00;
end
b3rd:
begin
input_sel <= 1'b1;
sbox_sel <= 1'b0;
last_out_sel <= 1'b0;
bit_out_sel <= 1'b1;
rcon_en <= 8'h00;
end
norm:
begin
input_sel <= 1'b1;
sbox_sel <= 1'b0;
last_out_sel <= 1'b1;
bit_out_sel <= 1'b1;
rcon_en <= 8'h00;
end
shif:
begin
input_sel <= 1'b1;
sbox_sel <= 1'b0;
last_out_sel <= 1'b1;
bit_out_sel <= 1'b0;
rcon_en <= 8'h00;
end
default:
begin
input_sel <= 1'b0;
sbox_sel <= 1'b1;
last_out_sel <= 1'b0;
bit_out_sel <= 1'b0;
rcon_en <= 8'h00;
end
endcase
end
//round counter
always @ (posedge clk)
begin
if (rst == 1'b1 || cnt == 4'hf || round_cnt_w == 4'ha)
begin
round_cnt <= 6'h00;
end
else
begin
round_cnt <= round_cnt + 6'h01;
end
end
//state machine shift row
always @ (posedge clk)
begin
if (state == load)
begin
c3 <= 2'h3;
end
else
begin
case (round_cnt[3:0])
4'h0: c3 <= 2'h2;
4'h1: c3 <= 2'h1;
4'h2: c3 <= 2'h0;
4'h3: c3 <= 2'h3;
4'h4: c3 <= 2'h2;
4'h5: c3 <= 2'h1;
4'h6: c3 <= 2'h1;
4'h7: c3 <= 2'h3;
4'h8: c3 <= 2'h2;
4'h9: c3 <= 2'h3;
4'hA: c3 <= 2'h2;
4'hB: c3 <= 2'h3;
4'hC: c3 <= 2'h3;
4'hD: c3 <= 2'h3;
4'hE: c3 <= 2'h3;
4'hF: c3 <= 2'h3;
endcase
end
end
//mixcoloumn enable
always @ (posedge clk)
begin
if (round_cnt[1:0] == 2'b11)
begin
mc_en_reg <= 8'h00;
end
else
begin
mc_en_reg <= 8'hFF;
end
end
//parelle load
always @ (posedge clk)
begin
if (state == load)
begin
pld_reg <= 1'b0;
end
else
begin
if (round_cnt[1:0] == 2'b11)
begin
pld_reg <= 1'b1;
end
else
begin
pld_reg <= 1'b0;
end
end
end
always @(posedge clk)
begin
if (rst == 1'b1)
begin
d_vld <= 1'b0;
end
else
begin
if (round_cnt == 8'h90)
begin
d_vld <= 1'b1;
end
end
end
endmodule |
module sky130_fd_sc_lp__srdlxtp (
Q ,
D ,
GATE ,
SLEEP_B
);
// Module ports
output Q ;
input D ;
input GATE ;
input SLEEP_B;
// Module supplies
supply1 KAPWR;
supply1 VPWR ;
supply0 VGND ;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire buf_Q ;
wire GATE_delayed;
wire D_delayed ;
reg notifier ;
wire awake ;
// Name Output Other arguments
sky130_fd_sc_lp__udp_dlatch$P_pp$PKG$sN dlatch0 (buf_Q , D_delayed, GATE_delayed, SLEEP_B, notifier, KAPWR, VGND, VPWR);
assign awake = ( SLEEP_B === 1'b1 );
bufif1 bufif10 (Q , buf_Q, VPWR );
endmodule |
module sky130_fd_sc_hvl__nor2 (
Y,
A,
B
);
// Module ports
output Y;
input A;
input B;
// Local signals
wire nor0_out_Y;
// Name Output Other arguments
nor nor0 (nor0_out_Y, A, B );
buf buf0 (Y , nor0_out_Y );
endmodule |
module sky130_fd_sc_hd__dlymetal6s6s (
//# {{data|Data Signals}}
input A ,
output X ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule |
module system_top (
// fmc fpga interface
eth_rx_clk,
eth_rx_cntrl,
eth_rx_data,
eth_tx_clk_out,
eth_tx_cntrl,
eth_tx_data,
eth_mdc,
eth_mdio_i,
eth_mdio_o,
eth_mdio_t,
eth_phy_resetn,
// phy interface
phy_resetn,
phy_rx_clk,
phy_rx_cntrl,
phy_rx_data,
phy_tx_clk_out,
phy_tx_cntrl,
phy_tx_data,
phy_mdc,
phy_mdio);
// fmc fpga interface
output eth_rx_clk;
output eth_rx_cntrl;
output [ 3:0] eth_rx_data;
input eth_tx_clk_out;
input eth_tx_cntrl;
input [ 3:0] eth_tx_data;
input eth_mdc;
output eth_mdio_i;
input eth_mdio_o;
input eth_mdio_t;
input eth_phy_resetn;
// phy interface
output phy_resetn;
input phy_rx_clk;
input phy_rx_cntrl;
input [ 3:0] phy_rx_data;
output phy_tx_clk_out;
output phy_tx_cntrl;
output [ 3:0] phy_tx_data;
output phy_mdc;
inout phy_mdio;
// simple pass through
assign eth_rx_clk = phy_rx_clk;
assign eth_rx_cntrl = phy_rx_cntrl;
assign eth_rx_data = phy_rx_data;
assign phy_tx_clk_out = eth_tx_clk_out;
assign phy_tx_cntrl = eth_tx_cntrl;
assign phy_tx_data = eth_tx_data;
assign phy_mdc = eth_mdc;
assign phy_mdio = (eth_mdio_t == 1'b0) ? eth_mdio_o : 1'bz;
assign eth_mdio_i = phy_mdio;
assign phy_resetn = eth_phy_resetn;
endmodule |
module sctag_pcx_rptr_2 (/*AUTOARG*/
// Outputs
sig_buf,
// Inputs
sig
);
// this repeater has 164 bits
output [163:0] sig_buf;
input [163:0] sig;
assign sig_buf = sig;
//output pcx_sctag_data_rdy_px1_buf;
//output [`PCX_WIDTH-1:0] pcx_sctag_data_px2_buf; // pcx to sctag packet
//output pcx_sctag_atm_px1_buf; // indicates that the current packet is atm with the next
//output sctag_pcx_stall_pq_buf;
//input pcx_sctag_data_rdy_px1;
//input [`PCX_WIDTH-1:0] pcx_sctag_data_px2; // pcx to sctag packet
//input pcx_sctag_atm_px1; // indicates that the current packet is atm with the next
//input sctag_pcx_stall_pq;
//assign pcx_sctag_data_rdy_px1_buf = pcx_sctag_data_rdy_px1;
//assign pcx_sctag_data_px2_buf = pcx_sctag_data_px2;
//assign pcx_sctag_atm_px1_buf = pcx_sctag_atm_px1;
//assign sctag_pcx_stall_pq_buf = sctag_pcx_stall_pq;
endmodule |
module at the start
* of the simulation
*/
always begin
/**
* Clock frequency is arbitrarily chosen;
* Period = 5ns <==> 200 MHz clock
*/
#5 clock = 0;
#5 clock = 1;
end
// ============================================================
/**
* Instantiate an instance of regfile() so that
* inputs can be passed to the Device Under Test (DUT)
* Given instance name is "rg"
*/
program_counter pc (
// instance_name(signal name),
// Signal name can be the same as the instance name
// next_pc,cur_pc,rst,clk
n_pc,c_pc,reset,clock);
// ============================================================
/**
* Initial block start executing sequentially @ t=0
* If and when a delay is encountered, the execution of this block
* pauses or waits until the delay time has passed, before resuming
* execution
*
* Each intial or always block executes concurrently; that is,
* multiple "always" or "initial" blocks will execute simultaneously
*
* E.g.
* always
* begin
* #10 clk_50 = ~clk_50; // Invert clock signal every 10 ns
* // Clock signal has a period of 20 ns or 50 MHz
* end
*/
initial
begin
$sdf_annotate("../sdf/program_counter.sdf",pc,"TYPICAL", "1.0:1.0:1.0", "FROM_MTM");
// "$time" indicates the current time in the simulation
$display($time, " << Starting the simulation >>");
c_pc=$random;
reset=1'b1;
#9
c_pc=200;
reset=1'b0;
// Write to 8 data locations
for(count=200; count<216; count=count+1)
begin
#20
//c_pc=count;
c_pc=n_pc;
reset=1'b0;
end
// end simulation
#30
$display($time, " << Finishing the simulation >>");
$finish;
end
endmodule |
module pdp1_sbs(i_clk, i_rst,
sb_ireq, sb_dne,
pb_att, pb_op, pb_sqb,
tr_lp, tr_ptr, tr_tyo, tr_tyi, tr_tp, tr_drm);
input i_clk;
input i_rst;
output reg sb_ireq;
input sb_dne;
input pb_att;
input [0:10] pb_op;
output [0:5] pb_sqb;
input tr_lp;
input tr_ptr;
input tr_tyo;
input tr_tyi;
input tr_tp;
input tr_drm;
reg r_en;
wire w_tr_any;
assign pb_sqb = {tr_lp, tr_ptr, tr_tyo, tr_tyi, tr_tp, tr_drm, r_en};
assign w_tr_any = (|pb_sqb[0:4]);
always @(posedge i_clk) begin
if(i_rst) begin
sb_ireq <= 1'b0;
r_en <= 1'b0;
end
else begin
if(pb_att) begin
case(pb_op)
`PDP1_SBS_ESM:
r_en <= 1'b1;
`PDP1_SBS_LSM:
r_en <= 1'b0;
`PDP1_SBS_CBS:
sb_ireq <= 1'b0;
endcase // case (pb_op)
end
else begin
if(w_tr_any & ~sb_dne)
sb_ireq <= 1'b1;
else if(sb_dne & sb_ireq)
sb_ireq <= 1'b0;
end
end
end
endmodule |
module sky130_fd_sc_lp__dlrbn (
//# {{data|Data Signals}}
input D ,
output Q ,
output Q_N ,
//# {{control|Control Signals}}
input RESET_B,
//# {{clocks|Clocking}}
input GATE_N ,
//# {{power|Power}}
input VPB ,
input VPWR ,
input VGND ,
input VNB
);
endmodule |
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(CLK, A, B, P)
/* synthesis syn_black_box black_box_pad_pin="CLK,A[7:0],B[7:0],P[15:0]" */;
input CLK;
input [7:0]A;
input [7:0]B;
output [15:0]P;
endmodule |
module clk_166M_83M_exdes
#(
parameter TCQ = 100
)
(// Clock in ports
input CLK_IN1,
// Reset that only drives logic in example design
input COUNTER_RESET,
// High bits of counters driven by clocks
output [3:1] COUNT,
// Status and control signals
input RESET,
output LOCKED
);
// Parameters for the counters
//-------------------------------
// Counter width
localparam C_W = 16;
// Number of counters
localparam NUM_C = 3;
genvar count_gen;
// When the clock goes out of lock, reset the counters
wire reset_int = !LOCKED || RESET || COUNTER_RESET;
reg [NUM_C:1] rst_sync;
reg [NUM_C:1] rst_sync_int;
reg [NUM_C:1] rst_sync_int1;
reg [NUM_C:1] rst_sync_int2;
// Declare the clocks and counters
wire [NUM_C:1] clk_int;
wire [NUM_C:1] clk;
reg [C_W-1:0] counter [NUM_C:1];
// Instantiation of the clocking network
//--------------------------------------
clk_166M_83M clknetwork
(// Clock in ports
.CLK_IN1 (CLK_IN1),
// Clock out ports
.CLK_OUT1 (clk_int[1]),
.CLK_OUT2 (clk_int[2]),
.CLK_OUT3 (clk_int[3]),
// Status and control signals
.RESET (RESET),
.LOCKED (LOCKED));
// Connect the output clocks to the design
//-----------------------------------------
assign clk[1] = clk_int[1];
assign clk[2] = clk_int[2];
assign clk[3] = clk_int[3];
// Reset synchronizer
//-----------------------------------
generate for (count_gen = 1; count_gen <= NUM_C; count_gen = count_gen + 1) begin: counters_1
always @(posedge reset_int or posedge clk[count_gen]) begin
if (reset_int) begin
rst_sync[count_gen] <= 1'b1;
rst_sync_int[count_gen]<= 1'b1;
rst_sync_int1[count_gen]<= 1'b1;
rst_sync_int2[count_gen]<= 1'b1;
end
else begin
rst_sync[count_gen] <= 1'b0;
rst_sync_int[count_gen] <= rst_sync[count_gen];
rst_sync_int1[count_gen] <= rst_sync_int[count_gen];
rst_sync_int2[count_gen] <= rst_sync_int1[count_gen];
end
end
end
endgenerate
// Output clock sampling
//-----------------------------------
generate for (count_gen = 1; count_gen <= NUM_C; count_gen = count_gen + 1) begin: counters
always @(posedge clk[count_gen] or posedge rst_sync_int2[count_gen]) begin
if (rst_sync_int2[count_gen]) begin
counter[count_gen] <= #TCQ { C_W { 1'b 0 } };
end else begin
counter[count_gen] <= #TCQ counter[count_gen] + 1'b 1;
end
end
// alias the high bit of each counter to the corresponding
// bit in the output bus
assign COUNT[count_gen] = counter[count_gen][C_W-1];
end
endgenerate
endmodule |
module sky130_fd_sc_hs__sdlclkp (
GCLK,
GATE,
CLK ,
SCE ,
VPWR,
VGND
);
// Module ports
output GCLK;
input GATE;
input CLK ;
input SCE ;
input VPWR;
input VGND;
// Local signals
wire m0 ;
wire m0n ;
wire clkn ;
wire CLK_delayed ;
wire SCE_delayed ;
wire GATE_delayed ;
wire SCE_gate_delayed;
reg notifier ;
wire awake ;
wire SCE_awake ;
wire GATE_awake ;
// Name Output Other arguments
not not0 (m0n , m0 );
not not1 (clkn , CLK_delayed );
nor nor0 (SCE_gate_delayed, GATE_delayed, SCE_delayed );
sky130_fd_sc_hs__u_dl_p_no_pg u_dl_p_no_pg0 (m0 , SCE_gate_delayed, clkn, notifier, VPWR, VGND);
and and0 (GCLK , m0n, CLK_delayed );
assign awake = ( VPWR === 1'b1 );
assign SCE_awake = ( awake & ( GATE_delayed === 1'b0 ) );
assign GATE_awake = ( awake & ( SCE_delayed === 1'b0 ) );
endmodule |
module Problem2(
input A,
input B,
input C,
input D,
output reg X
);
always @ (A or B or C or D)
begin
if ((~A & B & ~C & ~D) == 1)
X = 1;
else if ((~A & ~B & C & D) == 1)
X = 1;
else if ((A & D & ~B & ~C) == 1)
X = 1;
else if ((A & B & C & ~D) == 1)
X = 1;
else if ((~A & ~B & C & ~D) == 1)
X = 1;
//else if ((A & D & ~ B & C) == 1)
//X = 1;
else if ((D & ~B & C) == 1)
X = 1;
else if ((~A & B & C & D) == 1)
X = 1;
else if ((A & ~B & C & ~D) == 1)
X = 1;
else if ((~A & ~B & C & ~D) == 1)
X = 1;
else if ((A & B & C & D) == 1)
X = 1;
else
X = 0;
end
endmodule |
module sky130_fd_sc_lp__and2 (
X ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire and0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
and and0 (and0_out_X , A, B );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule |
module bios (
address,
clock,
q);
input [11:0] address;
input clock;
output [7:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [7:0] sub_wire0;
wire [7:0] q = sub_wire0[7:0];
altsyncram altsyncram_component (
.address_a (address),
.clock0 (clock),
.q_a (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.address_b (1'b1),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_a ({8{1'b1}}),
.data_b (1'b1),
.eccstatus (),
.q_b (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_a (1'b0),
.wren_b (1'b0));
defparam
altsyncram_component.address_aclr_a = "NONE",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.init_file = "bios.mif",
altsyncram_component.intended_device_family = "Cyclone III",
altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 4096,
altsyncram_component.operation_mode = "ROM",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_reg_a = "UNREGISTERED",
altsyncram_component.widthad_a = 12,
altsyncram_component.width_a = 8,
altsyncram_component.width_byteena_a = 1;
endmodule |
module at the start
* of the simulation
*/
always begin
// Clock frequency is arbitrarily chosen
#10 clk = 0;
#10 clk = 1;
end
// Create the register (flip-flop) for the initial/1st stage
always@(posedge clk)
begin
if(reset)
begin
r_b<=0;
r_e<=0;
end
else
begin
r_e<=e;
r_b<=b;
end
end
// Create the register (flip-flop) for the 2nd stage
always@(posedge clk)
begin
if(reset)
begin
r_c<=0;
rr_e<=0;
rr_b<=0;
end
else
begin
r_c<=c;
rr_e<=r_e;
rr_b<=r_b;
end
end
// Create the register (flip-flop) for the 3rd stage
always@(posedge clk)
begin
if(reset)
begin
rb<=0;
end
else
begin
r_qx<=cx;
rb<=rr_b;
e2<=rr_e;
end
end
/**
* Initial block start executing sequentially @ t=0
* If and when a delay is encountered, the execution of this block
* pauses or waits until the delay time has passed, before resuming
* execution
*
* Each intial or always block executes concurrently; that is,
* multiple "always" or "initial" blocks will execute simultaneously
*
* E.g.
* always
* begin
* #10 clk_50 = ~clk_50; // Invert clock signal every 10 ns
* // Clock signal has a period of 20 ns or 50 MHz
* end
*/
initial
begin
$sdf_annotate("../sdf/encoder.sdf",enc,"TYPICAL", "1.0:1.0:1.0", "FROM_MTM");
$sdf_annotate("../sdf/decoder.sdf",dec,"TYPICAL", "1.0:1.0:1.0", "FROM_MTM");
// "$time" indicates the current time in the simulation
$display(" << Starting the simulation >>");
reset=1;
#20;
reset=0;
b = $random;
e = 12'b000000000000;
$display(q, "<< Displaying q >>");
$display(rb, "<< Displaying rb >>");
#20;
b = $random;
e = 12'b000000000000;
$display(q, "<< Displaying q >>");
$display(rb, "<< Displaying rb >>");
#20;
b = $random;
e = 12'b000001000000;
$display(q, "<< Displaying q >>");
$display(rb, "<< Displaying rb >>");
#20;
b = $random;
e = 12'b000000000000;
$display(q, "<< Displaying q >>");
$display(rb, "<< Displaying rb >>");
#20;
b = $random;
e = 12'b000000000000;
$display(q, "<< Displaying q >>");
$display(rb, "<< Displaying rb >>");
#20;
b = $random;
e = 12'b000010000000;
$display(q, "<< Displaying q >>");
$display(rb, "<< Displaying rb >>");
#20;
b = $random;
e = 12'b000000000000;
$display(q, "<< Displaying q >>");
$display(rb, "<< Displaying rb >>");
#20;
b = $random;
e = 12'b000000000000;
$display(q, "<< Displaying q >>");
$display(rb, "<< Displaying rb >>");
#20;
b = $random;
e = 12'b001000000000;
$display(q, "<< Displaying q >>");
$display(rb, "<< Displaying rb >>");
#20;
b = $random;
e = 12'b000000000000;
$display(q, "<< Displaying q >>");
$display(rb, "<< Displaying rb >>");
#300;
$display(" << Finishing the simulation >>");
$finish;
end
endmodule |
module stream_tg #(
parameter DATA_WIDTH = 64,
parameter KEEP_WIDTH = 8,
parameter START_ADDR = 0,
parameter START_DATA = 0,
parameter BTT = 23'd8,
parameter DRR = 1'b0,
parameter DSA = 6'd0
)
(
input aclk,
input aresetn,
output [71:0] write_cmd,
output write_cmd_valid,
input write_cmd_ready,
output [DATA_WIDTH-1: 0] write_data,
output write_data_valid,
input write_data_ready,
output [KEEP_WIDTH-1: 0] write_data_keep,
output write_data_last,
output [71:0] read_cmd,
output read_cmd_valid,
input read_cmd_ready,
input [DATA_WIDTH-1: 0] read_data,
input read_data_valid,
input [KEEP_WIDTH-1: 0] read_data_keep,
input read_data_last,
output read_data_ready,
input [7:0] read_sts_data,
input read_sts_valid,
output read_sts_ready,
input [31:0] write_sts_data,
input write_sts_valid,
output write_sts_ready,
output compare_error
);
//local parameters for test state machine
localparam ITERATIONS = 1; //test iterations. Each iteration involves state transition from WRITE TO COMPARE
localparam IDLE = 3'd0;
localparam START = 3'd1;
localparam WRITE_CMD = 3'd2;
localparam WRITE_DATA = 3'd3;
localparam READ_CMD = 3'd4;
localparam READ_DATA = 3'd5;
localparam COMPARE = 3'd6;
localparam FINISH = 3'd7;
//localparam BTT = 23'd16;
localparam TYPE = 1'd1;
localparam EOF = 1'd1;
//localparam DRR = 1'd1;
localparam TAG = 4'd0;
localparam RSVD = 4'd0;
reg [31:0] iter_count_r;
reg [2:0] test_state_r;
reg [71:0] write_cmd_r;
reg write_cmd_valid_r;
reg [DATA_WIDTH-1: 0] write_data_r, write_data_r1;
reg write_data_valid_r;
reg [KEEP_WIDTH-1: 0] write_data_keep_r, write_data_keep_r1;
reg write_data_last_r;
reg [71:0] read_cmd_r;
reg read_cmd_valid_r;
reg [DATA_WIDTH-1: 0] read_data_r, read_data_r1;
reg read_data_valid_r;
reg [KEEP_WIDTH-1: 0] read_data_keep_r, read_data_keep_r1;
reg read_data_last_r, read_data_last_r1;
reg compare_error_r;
assign compare_error = compare_error_r;
assign write_cmd = write_cmd_r;
assign write_cmd_valid = write_cmd_valid_r;
assign write_data = write_data_r;
assign write_data_valid = write_data_valid_r;
assign write_data_keep = write_data_keep_r;
assign write_data_last = write_data_last_r;
assign read_cmd = read_cmd_r;
assign read_cmd_valid = read_cmd_valid_r;
assign read_data_ready = 1'b1;
assign read_sts_ready = 1'b1;
assign write_sts_ready = 1'b1;
//main state machine
always @(posedge aclk)
if (~aresetn) begin
write_cmd_r[22:0] <= BTT;
write_cmd_r[23] <= TYPE;
write_cmd_r[29:24] <= DSA;
write_cmd_r[30] <= EOF;
write_cmd_r[31] <= DRR;
write_cmd_r[63:32] <= START_ADDR;
write_cmd_r[67:64] <= TAG;
write_cmd_r[71:68] <= RSVD;
read_cmd_r[22:0] <= BTT;
read_cmd_r[23] <= TYPE;
read_cmd_r[29:24] <= DSA;
read_cmd_r[30] <= EOF;
read_cmd_r[31] <= DRR;
read_cmd_r[63:32] <= START_ADDR;
read_cmd_r[67:64] <= TAG;
read_cmd_r[71:68] <= RSVD;
write_data_r <= START_DATA;
write_cmd_valid_r <= 1'b0;
write_data_valid_r <= 1'b0;
read_cmd_valid_r <= 1'b0;
write_data_keep_r <= 0;
write_data_last_r <= 1'b0;
//iter_count_r <= 0;
test_state_r <= IDLE;
compare_error_r <= 1'b0;
read_data_r <= 0;
read_data_keep_r <= 0;
read_data_last_r <= 0;
end
else
case (test_state_r)
IDLE: begin test_state_r <= START; end
START: begin
test_state_r <= WRITE_CMD;
write_cmd_valid_r <= 1'b1;
end
WRITE_CMD: begin
if (write_cmd_ready) begin
write_cmd_valid_r <= 1'b0;
test_state_r <= WRITE_DATA;
write_data_keep_r <= {{KEEP_WIDTH}{1'b1}};
write_data_last_r <= 1'b1;
write_data_valid_r <= 1'b1;
write_cmd_r[63:32] <= write_cmd_r[63:32] + 1;
end
end
WRITE_DATA: begin
if (write_data_ready) begin
write_data_valid_r <= 1'b0;
write_data_last_r <= 1'b0;
end
if (write_sts_valid & write_sts_data[7]) begin
test_state_r <= READ_CMD;
read_cmd_valid_r <= 1'b1;
end
end
READ_CMD: begin
if (read_cmd_ready) begin
read_cmd_valid_r <= 1'b0;
end
if (read_sts_valid & read_sts_data[7]) begin
test_state_r <= READ_DATA;
read_cmd_r[63:32] <= read_cmd_r[63:32] + 1;
end
end
READ_DATA: begin
if (read_data_valid) begin
read_data_r <= read_data;
read_data_keep_r <= read_data_keep;
read_data_last_r <= read_data_last;
end
if (read_data_last_r) begin
test_state_r <= COMPARE;
end
end
COMPARE: begin
if ((read_data_r1 != write_data_r1) | (read_data_keep_r1 != write_data_keep_r1)) begin
compare_error_r <= 1'b1;
end
test_state_r <= FINISH;
end
FINISH: begin
//test_state_r <= FINISH;
test_state_r <= START;
end
endcase
always @(posedge aclk) begin
read_data_r1 <= read_data_r;
read_data_keep_r1 <= read_data_keep_r;
write_data_r1 <= write_data_r;
write_data_keep_r1 <= write_data_keep_r;
end
endmodule |
module display(CLK, BPM, PLAY, SEGA, SEGD);
input CLK; // 100MHz clock input
input [7:0] BPM; // 8-bit BPM value
//input [5:0] TONE; // 6-bit tone code
//input [3:0] DURATION; // 4-bit duration code
input PLAY; // Play/Pause Input
output reg [3:0] SEGA; // Display-select (common anode) output
output [7:0] SEGD; // Display-pattern output
wire [11:0] BCD;
reg [3:0] CURRENT_DIG;// Which BCD digit is currently displaying
//assign BCD = 12'h123;
byte_to_BCD btb_blk (BPM, BCD);
bcdtoseg seg_disp_blk (1'b1, 1'b1, CURRENT_DIG[3], CURRENT_DIG[2], CURRENT_DIG[1], CURRENT_DIG[0], 1'b1, /*unconnected*/
, SEGD[7], SEGD[6], SEGD[5], SEGD[4], SEGD[3], SEGD[2], SEGD[1]);
// Turn decimal point off
assign SEGD[0] = 1;
reg [16:0] waveCount;
parameter
KHZ_WAVE = 17'd100000, // The full period of a 1kHz wave with 100MHz clock
DISP_D0 = ~4'b0001,
DISP_D1 = ~4'b0010,
DISP_D2 = ~4'b0100,
DISP_D3 = ~4'b1000,
DISP_OFF = ~4'b0000;
initial begin
waveCount = 0;
// OFF
SEGA = ~4'h0;
CURRENT_DIG[3:0] = 4'h0;
end
always @(posedge CLK) begin
//increment waveCount to use as 1KHz wave
waveCount = waveCount + 1;
//increment the counter to count up to duration
//active contains state of whether you've finished the note or not
//selecting the digit to display
// TODO: Display state on the first digit, e.g. P for paused
if (waveCount < KHZ_WAVE/4) begin
if (~PLAY) begin
SEGA = DISP_D0;
CURRENT_DIG = 4'hF;
end else begin
SEGA = DISP_OFF;
CURRENT_DIG = 4'd0;
end
end else if (waveCount < KHZ_WAVE/2) begin
SEGA = DISP_D1;
CURRENT_DIG = BCD[11:8];
end else if (waveCount < KHZ_WAVE*3/4) begin
SEGA = DISP_D2;
CURRENT_DIG = BCD[7:4];
end else if (waveCount < KHZ_WAVE)begin
SEGA = DISP_D3;
CURRENT_DIG = BCD[3:0];
end else
waveCount = 0;
end
endmodule |
module HalfAdder(input a,b, output sum, carry);
Xor g1(a, b, sum);
And g2(a, b, carry);
endmodule |
module FullAdder(input a,b,c, output sum, carry);
wire s1, c1, c2;
Xor g1(a, b, s1);
Xor g2(s1, c, sum);
And g3(a, b, c1);
And g4(s1, c, c2);
Xor g5(c2, c1, carry);
endmodule |
module Add16(input[15:0] a,b, output[15:0] out);
wire [15:0] c;
FullAdder g01(a[0], b[0], 1'b0, out[0], c[0]);
FullAdder g02(a[1], b[1], c[0], out[1], c[1]);
FullAdder g03(a[2], b[2], c[1], out[2], c[2]);
FullAdder g04(a[3], b[3], c[2], out[3], c[3]);
FullAdder g05(a[4], b[4], c[3], out[4], c[4]);
FullAdder g06(a[5], b[5], c[4], out[5], c[5]);
FullAdder g07(a[6], b[6], c[5], out[6], c[6]);
FullAdder g08(a[7], b[7], c[6], out[7], c[7]);
FullAdder g09(a[8], b[8], c[7], out[8], c[8]);
FullAdder g10(a[9], b[9], c[8], out[9], c[9]);
FullAdder g11(a[10], b[10], c[9], out[10], c[10]);
FullAdder g12(a[11], b[11], c[10], out[11], c[11]);
FullAdder g13(a[12], b[12], c[11], out[12], c[12]);
FullAdder g14(a[13], b[13], c[12], out[13], c[13]);
FullAdder g15(a[14], b[14], c[13], out[14], c[14]);
FullAdder g16(a[15], b[15], c[14], out[15], c[15]);
endmodule |
module Inc16(input[15:0] in, output[15:0] out);
Add16 g1(in, 16'h1, out);
endmodule |
module ALU(input[15:0] x, y, input zx,nx,zy,ny,f,no, output[15:0] out, output zr, ng);
wire[15:0] x1, notx1, x2, y1, noty1, y2, andxy, addxy, o1, noto1, o2;
wire orLow, orHigh, notzr;
Mux16 g1(x, 16'b0, zx, x1); // if (zx == 1) set x = 0
Not16 g2(x1, notx1);
Mux16 g3(x1, notx1, nx, x2); // if (nx == 1) set x = !x
Mux16 g4(y, 16'b0, zy, y1); // if (zy == 1) set y = 0
Not16 g5(y1, noty1);
Mux16 g6(y1, noty1, ny, y2); // if (ny == 1) set y = !y
Add16 g7(x2, y2, addxy); // addxy = x + y
And16 g8(x2, y2, andxy); // andxy = x & y
Mux16 g9(andxy, addxy, f, o1); // if (f == 1) set out = x + y else set out = x & y
Not16 g10(o1, noto1);
Mux16 g11(o1, noto1, no, o2); // if (no == 1) set out = !out
// o2 就是 out, 但必須中間節點才能再次當作輸入，所以先用 o2。
And16 g12(o2, o2, out);
Or8Way g13(out[7:0], orLow); // orLow = Or(out[0..7]);
Or8Way g14(out[15:8], orHigh);// orHigh = Or(out[8..15]);
Or g15(orLow, orHigh, notzr); // nzr = Or(out[0..15]);
Not g16(notzr, zr); // zr = !nzr
And g17(o2[15], o2[15], ng); // ng = out[15]
And16 g18(o2, o2, out);
endmodule |
module daala_zynq_axis_dwidth_converter_0_0 (
aclk,
aresetn,
s_axis_tvalid,
s_axis_tready,
s_axis_tdata,
s_axis_tlast,
m_axis_tvalid,
m_axis_tready,
m_axis_tdata,
m_axis_tkeep,
m_axis_tlast
);
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLKIF CLK" *)
input aclk;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RSTIF RST" *)
input aresetn;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TVALID" *)
input s_axis_tvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TREADY" *)
output s_axis_tready;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TDATA" *)
input [63 : 0] s_axis_tdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TLAST" *)
input s_axis_tlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS TVALID" *)
output m_axis_tvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS TREADY" *)
input m_axis_tready;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS TDATA" *)
output [255 : 0] m_axis_tdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS TKEEP" *)
output [31 : 0] m_axis_tkeep;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS TLAST" *)
output m_axis_tlast;
axis_dwidth_converter_v1_1_axis_dwidth_converter #(
.C_FAMILY("zynq"),
.C_S_AXIS_TDATA_WIDTH(64),
.C_M_AXIS_TDATA_WIDTH(256),
.C_AXIS_TID_WIDTH(1),
.C_AXIS_TDEST_WIDTH(1),
.C_S_AXIS_TUSER_WIDTH(1),
.C_M_AXIS_TUSER_WIDTH(1),
.C_AXIS_SIGNAL_SET('B00010011)
) inst (
.aclk(aclk),
.aresetn(aresetn),
.aclken(1'H1),
.s_axis_tvalid(s_axis_tvalid),
.s_axis_tready(s_axis_tready),
.s_axis_tdata(s_axis_tdata),
.s_axis_tstrb(8'HFF),
.s_axis_tkeep(8'HFF),
.s_axis_tlast(s_axis_tlast),
.s_axis_tid(1'H0),
.s_axis_tdest(1'H0),
.s_axis_tuser(1'H0),
.m_axis_tvalid(m_axis_tvalid),
.m_axis_tready(m_axis_tready),
.m_axis_tdata(m_axis_tdata),
.m_axis_tstrb(),
.m_axis_tkeep(m_axis_tkeep),
.m_axis_tlast(m_axis_tlast),
.m_axis_tid(),
.m_axis_tdest(),
.m_axis_tuser()
);
endmodule |
module /*pci_pci_*/tpram
(
// Generic synchronous two-port RAM interface
clk_a,
rst_a,
ce_a,
we_a,
oe_a,
addr_a,
di_a,
do_a,
clk_b,
rst_b,
ce_b,
we_b,
oe_b,
addr_b,
di_b,
do_b
`ifdef PCI_BIST
,
// debug chain signals
mbist_si_i, // bist scan serial in
mbist_so_o, // bist scan serial out
mbist_ctrl_i // bist chain shift control
`endif
);
//
// Default address and data buses width
//
parameter aw = 8;
parameter dw = 40;
//
// Generic synchronous two-port RAM interface
//
input clk_a; // Clock
input rst_a; // Reset
input ce_a; // Chip enable input
input we_a; // Write enable input
input oe_a; // Output enable input
input [aw-1:0] addr_a; // address bus inputs
input [dw-1:0] di_a; // input data bus
output [dw-1:0] do_a; // output data bus
input clk_b; // Clock
input rst_b; // Reset
input ce_b; // Chip enable input
input we_b; // Write enable input
input oe_b; // Output enable input
input [aw-1:0] addr_b; // address bus inputs
input [dw-1:0] di_b; // input data bus
output [dw-1:0] do_b; // output data bus
`ifdef PCI_BIST
// debug chain signals
input mbist_si_i; // bist scan serial in
output mbist_so_o; // bist scan serial out
input [`PCI_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i; // bist chain shift control
`endif
//
// Internal wires and registers
//
`ifdef PCI_VS_STP
`define PCI_PCI_RAM_SELECTED
`ifdef PCI_BIST
vs_hdtp_64x40_bist i_vs_hdtp_64x40_bist
`else
vs_hdtp_64x40 i_vs_hdtp_64x40
`endif
(
.RCK (clk_b),
.WCK (clk_a),
.RADR (addr_b),
.WADR (addr_a),
.DI (di_a),
.DOUT (do_b),
.REN (1'b0),
.WEN (!we_a)
`ifdef PCI_BIST
,
// debug chain signals
.mbist_si_i (mbist_si_i),
.mbist_so_o (mbist_so_o),
.mbist_ctrl_i (mbist_ctrl_i)
`endif
);
assign do_a = 0 ;
`endif
`ifdef PCI_ARTISAN_SDP
`define PCI_PCI_RAM_SELECTED
//
// Instantiation of ASIC memory:
//
// Artisan Synchronous Double-Port RAM (ra2sh)
//
`ifdef PCI_BIST
art_hsdp_64x40_bist /*#(dw, 1<<aw, aw) */ artisan_sdp
(
.QA(do_a),
.CLKA(clk_a),
.CENA(~ce_a),
.WENA(~we_a),
.AA(addr_a),
.DA(di_a),
.OENA(~oe_a),
.QB(do_b),
.CLKB(clk_b),
.CENB(~ce_b),
.WENB(~we_b),
.AB(addr_b),
.DB(di_b),
.OENB(~oe_b),
.mbist_si_i (mbist_si_i),
.mbist_so_o (mbist_so_o),
.mbist_ctrl_i (mbist_ctrl_i)
);
`else
art_hsdp_64x40 /*#(dw, 1<<aw, aw) */ artisan_sdp
(
.QA(do_a),
.CLKA(clk_a),
.CENA(~ce_a),
.WENA(~we_a),
.AA(addr_a),
.DA(di_a),
.OENA(~oe_a),
.QB(do_b),
.CLKB(clk_b),
.CENB(~ce_b),
.WENB(~we_b),
.AB(addr_b),
.DB(di_b),
.OENB(~oe_b)
);
`endif
`endif
`ifdef AVANT_ATP
`define PCI_PCI_RAM_SELECTED
//
// Instantiation of ASIC memory:
//
// Avant! Asynchronous Two-Port RAM
//
avant_atp avant_atp(
.web(~we),
.reb(),
.oeb(~oe),
.rcsb(),
.wcsb(),
.ra(addr),
.wa(addr),
.di(di),
.do(do)
);
`endif
`ifdef VIRAGE_STP
`define PCI_PCI_RAM_SELECTED
//
// Instantiation of ASIC memory:
//
// Virage Synchronous 2-port R/W RAM
//
virage_stp virage_stp(
.QA(do_a),
.QB(do_b),
.ADRA(addr_a),
.DA(di_a),
.WEA(we_a),
.OEA(oe_a),
.MEA(ce_a),
.CLKA(clk_a),
.ADRB(adr_b),
.DB(di_b),
.WEB(we_b),
.OEB(oe_b),
.MEB(ce_b),
.CLKB(clk_b)
);
`endif
`ifdef PCI_XILINX_RAMB4
`define PCI_PCI_RAM_SELECTED
//
// Instantiation of FPGA memory:
//
// Virtex/Spartan2
//
//
// Block 0
//
RAMB4_S16_S16 ramb4_s16_s16_0(
.CLKA(clk_a),
.RSTA(rst_a),
.ADDRA(addr_a),
.DIA(di_a[15:0]),
.ENA(ce_a),
.WEA(we_a),
.DOA(do_a[15:0]),
.CLKB(clk_b),
.RSTB(rst_b),
.ADDRB(addr_b),
.DIB(di_b[15:0]),
.ENB(ce_b),
.WEB(we_b),
.DOB(do_b[15:0])
);
//
// Block 1
//
RAMB4_S16_S16 ramb4_s16_s16_1(
.CLKA(clk_a),
.RSTA(rst_a),
.ADDRA(addr_a),
.DIA(di_a[31:16]),
.ENA(ce_a),
.WEA(we_a),
.DOA(do_a[31:16]),
.CLKB(clk_b),
.RSTB(rst_b),
.ADDRB(addr_b),
.DIB(di_b[31:16]),
.ENB(ce_b),
.WEB(we_b),
.DOB(do_b[31:16])
);
//
// Block 2
//
// block ram2 wires - non generic width of block rams
wire [15:0] blk2_di_a = {8'h00, di_a[39:32]} ;
wire [15:0] blk2_di_b = {8'h00, di_b[39:32]} ;
wire [15:0] blk2_do_a ;
wire [15:0] blk2_do_b ;
assign do_a[39:32] = blk2_do_a[7:0] ;
assign do_b[39:32] = blk2_do_b[7:0] ;
RAMB4_S16_S16 ramb4_s16_s16_2(
.CLKA(clk_a),
.RSTA(rst_a),
.ADDRA(addr_a),
.DIA(blk2_di_a),
.ENA(ce_a),
.WEA(we_a),
.DOA(blk2_do_a),
.CLKB(clk_b),
.RSTB(rst_b),
.ADDRB(addr_b),
.DIB(blk2_di_b),
.ENB(ce_b),
.WEB(we_b),
.DOB(blk2_do_b)
);
`endif
`ifdef PCI_XILINX_DIST_RAM
`define PCI_PCI_RAM_SELECTED
reg [(aw-1):0] out_address ;
always@(posedge clk_b or posedge rst_b)
begin
if ( rst_b )
out_address <= #1 0 ;
else if (ce_b)
out_address <= #1 addr_b ;
end
pci_ram_16x40d #(aw) pci_distributed_ram
(
.data_out (do_b),
.we (we_a),
.data_in (di_a),
.read_address (out_address),
.write_address (addr_a),
.wclk (clk_a)
);
assign do_a = 0 ;
`endif
`ifdef PCI_PCI_RAM_SELECTED
`else
//
// Generic two-port synchronous RAM model
//
//
// Generic RAM's registers and wires
//
reg [dw-1:0] mem [(1<<aw)-1:0]; // RAM content
reg [dw-1:0] do_reg_b, do_reg_a; // RAM data output register
//
// Data output drivers
//
assign do_a = do_reg_a ;
assign do_b = do_reg_b ;
//
// RAM read and write
//
always @(posedge clk_a) begin
if (ce_a)
begin
if (we_a)
mem[addr_a] <= #1 di_a;
do_reg_a <= #1 mem[addr_a];
end
end
always @(posedge clk_b) begin
if (ce_b)
begin
if (we_b)
mem[addr_b] <= #1 di_b;
do_reg_b <= #1 mem[addr_b];
end
end
// synopsys translate_off
integer f;
initial begin
for (f = 0; f < 1<<aw; f = f + 1) begin
mem[f] = 0;
end
end
// synopsys translate_on
`endif
endmodule |
module daala_zynq_daala_4x4_transpose_0_0 (
axis_clk,
axis_aresetn,
s00_axis_tdata,
s00_axis_tlast,
s00_axis_tvalid,
s00_axis_tready,
m00_axis_tdata,
m00_axis_tlast,
m00_axis_tvalid,
m00_axis_tready
);
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 axis_clk CLK" *)
input axis_clk;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 axis_aresetn RST" *)
input axis_aresetn;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S00_AXIS TDATA" *)
input [255 : 0] s00_axis_tdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S00_AXIS TLAST" *)
input s00_axis_tlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S00_AXIS TVALID" *)
input s00_axis_tvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S00_AXIS TREADY" *)
output s00_axis_tready;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M00_AXIS TDATA" *)
output [255 : 0] m00_axis_tdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M00_AXIS TLAST" *)
output m00_axis_tlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M00_AXIS TVALID" *)
output m00_axis_tvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M00_AXIS TREADY" *)
input m00_axis_tready;
daala_4x4_transpose_v1_0 #(
.C_S00_AXIS_TDATA_WIDTH(256),
.C_M00_AXIS_TDATA_WIDTH(256)
) inst (
.axis_clk(axis_clk),
.axis_aresetn(axis_aresetn),
.s00_axis_tdata(s00_axis_tdata),
.s00_axis_tlast(s00_axis_tlast),
.s00_axis_tvalid(s00_axis_tvalid),
.s00_axis_tready(s00_axis_tready),
.m00_axis_tdata(m00_axis_tdata),
.m00_axis_tlast(m00_axis_tlast),
.m00_axis_tvalid(m00_axis_tvalid),
.m00_axis_tready(m00_axis_tready)
);
endmodule |
module dmac_dest_fifo_inf #(
parameter ID_WIDTH = 3,
parameter DATA_WIDTH = 64,
parameter BEATS_PER_BURST_WIDTH = 4)(
input clk,
input resetn,
input enable,
output enabled,
input req_valid,
output req_ready,
output [ID_WIDTH-1:0] response_id,
output reg [ID_WIDTH-1:0] data_id = 'h0,
input data_eot,
input response_eot,
input en,
output reg [DATA_WIDTH-1:0] dout,
output reg valid,
output reg underflow,
output xfer_req,
output fifo_ready,
input fifo_valid,
input [DATA_WIDTH-1:0] fifo_data,
input fifo_last,
output response_valid,
input response_ready,
output response_resp_eot,
output [1:0] response_resp
);
`include "inc_id.vh"
reg active = 1'b0;
/* Last beat of the burst */
wire fifo_last_beat;
/* Last beat of the segment */
wire fifo_eot_beat;
assign enabled = enable;
assign fifo_ready = en & (fifo_valid | ~enable);
/* fifo_last == 1'b1 implies fifo_valid == 1'b1 */
assign fifo_last_beat = fifo_ready & fifo_last;
assign fifo_eot_beat = fifo_last_beat & data_eot;
assign req_ready = fifo_eot_beat | ~active;
assign xfer_req = active;
always @(posedge clk) begin
if (en) begin
dout <= fifo_valid ? fifo_data : {DATA_WIDTH{1'b0}};
valid <= fifo_valid & enable;
underflow <= ~(fifo_valid & enable);
end else begin
valid <= 1'b0;
underflow <= 1'b0;
end
end
always @(posedge clk) begin
if (resetn == 1'b0) begin
data_id <= 'h00;
end else if (fifo_last_beat == 1'b1) begin
data_id <= inc_id(data_id);
end
end
always @(posedge clk) begin
if (resetn == 1'b0) begin
active <= 1'b0;
end else if (req_valid == 1'b1) begin
active <= 1'b1;
end else if (fifo_eot_beat == 1'b1) begin
active <= 1'b0;
end
end
dmac_response_generator # (
.ID_WIDTH(ID_WIDTH)
) i_response_generator (
.clk(clk),
.resetn(resetn),
.enable(enable),
.enabled(),
.request_id(data_id),
.response_id(response_id),
.eot(response_eot),
.resp_valid(response_valid),
.resp_ready(response_ready),
.resp_eot(response_resp_eot),
.resp_resp(response_resp)
);
endmodule |
module VGA_top(
input clk,
input rst,
input [7:0]snake,
input [7:0]apple_x,
input [7:0]apple_y,
output [9:0]x_pos,
output [9:0]y_pos,
output hsync,
output vsync,
output [11:0] color_out
);
wire clk_n;
clk_unit myclk(
.clk(clk),
.rst(rst),
.clk_n(clk_n)
);
VGA_Control VGA
(
.clk(clk_n),
.rst(rst),
.hsync(hsync),
.vsync(vsync),
.snake(snake),
.color_out(color_out),
.x_pos(x_pos),
.y_pos(y_pos),
.apple_x(apple_x),
.apple_y(apple_y)
);
endmodule |
module axis_eth_fcs_check
(
input wire clk,
input wire rst,
/*
* AXI input
*/
input wire [7:0] s_axis_tdata,
input wire s_axis_tvalid,
output wire s_axis_tready,
input wire s_axis_tlast,
input wire s_axis_tuser,
/*
* AXI output
*/
output wire [7:0] m_axis_tdata,
output wire m_axis_tvalid,
input wire m_axis_tready,
output wire m_axis_tlast,
output wire m_axis_tuser,
/*
* Status
*/
output wire busy,
output wire error_bad_fcs
);
localparam [1:0]
STATE_IDLE = 2'd0,
STATE_PAYLOAD = 2'd1;
reg [1:0] state_reg = STATE_IDLE, state_next;
// datapath control signals
reg reset_crc;
reg update_crc;
reg shift_in;
reg shift_reset;
reg [7:0] s_axis_tdata_d0 = 8'd0;
reg [7:0] s_axis_tdata_d1 = 8'd0;
reg [7:0] s_axis_tdata_d2 = 8'd0;
reg [7:0] s_axis_tdata_d3 = 8'd0;
reg s_axis_tvalid_d0 = 1'b0;
reg s_axis_tvalid_d1 = 1'b0;
reg s_axis_tvalid_d2 = 1'b0;
reg s_axis_tvalid_d3 = 1'b0;
reg busy_reg = 1'b0;
reg error_bad_fcs_reg = 1'b0, error_bad_fcs_next;
reg s_axis_tready_reg = 1'b0, s_axis_tready_next;
reg [31:0] crc_state = 32'hFFFFFFFF;
wire [31:0] crc_next;
// internal datapath
reg [7:0] m_axis_tdata_int;
reg m_axis_tvalid_int;
reg m_axis_tready_int_reg = 1'b0;
reg m_axis_tlast_int;
reg m_axis_tuser_int;
wire m_axis_tready_int_early;
assign s_axis_tready = s_axis_tready_reg;
assign busy = busy_reg;
assign error_bad_fcs = error_bad_fcs_reg;
lfsr #(
.LFSR_WIDTH(32),
.LFSR_POLY(32'h4c11db7),
.LFSR_CONFIG("GALOIS"),
.LFSR_FEED_FORWARD(0),
.REVERSE(1),
.DATA_WIDTH(8),
.STYLE("AUTO")
)
eth_crc_8 (
.data_in(s_axis_tdata_d3),
.state_in(crc_state),
.data_out(),
.state_out(crc_next)
);
always @* begin
state_next = STATE_IDLE;
reset_crc = 1'b0;
update_crc = 1'b0;
shift_in = 1'b0;
shift_reset = 1'b0;
s_axis_tready_next = 1'b0;
m_axis_tdata_int = 8'd0;
m_axis_tvalid_int = 1'b0;
m_axis_tlast_int = 1'b0;
m_axis_tuser_int = 1'b0;
error_bad_fcs_next = 1'b0;
case (state_reg)
STATE_IDLE: begin
// idle state - wait for data
s_axis_tready_next = m_axis_tready_int_early;
reset_crc = 1'b1;
m_axis_tdata_int = s_axis_tdata_d3;
m_axis_tvalid_int = s_axis_tvalid_d3 && s_axis_tvalid;
m_axis_tlast_int = 1'b0;
m_axis_tuser_int = 1'b0;
if (s_axis_tready && s_axis_tvalid) begin
shift_in = 1'b1;
if (s_axis_tvalid_d3) begin
reset_crc = 1'b0;
update_crc = 1'b1;
if (s_axis_tlast) begin
shift_reset = 1'b1;
reset_crc = 1'b1;
m_axis_tlast_int = 1'b1;
m_axis_tuser_int = s_axis_tuser;
if ({s_axis_tdata, s_axis_tdata_d0, s_axis_tdata_d1, s_axis_tdata_d2} != ~crc_next) begin
m_axis_tuser_int = 1'b1;
error_bad_fcs_next = 1'b1;
end
s_axis_tready_next = m_axis_tready_int_early;
state_next = STATE_IDLE;
end else begin
state_next = STATE_PAYLOAD;
end
end else begin
state_next = STATE_IDLE;
end
end else begin
state_next = STATE_IDLE;
end
end
STATE_PAYLOAD: begin
// transfer payload
s_axis_tready_next = m_axis_tready_int_early;
m_axis_tdata_int = s_axis_tdata_d3;
m_axis_tvalid_int = s_axis_tvalid_d3 && s_axis_tvalid;
m_axis_tlast_int = 1'b0;
m_axis_tuser_int = 1'b0;
if (s_axis_tready && s_axis_tvalid) begin
shift_in = 1'b1;
update_crc = 1'b1;
if (s_axis_tlast) begin
shift_reset = 1'b1;
reset_crc = 1'b1;
m_axis_tlast_int = 1'b1;
m_axis_tuser_int = s_axis_tuser;
if ({s_axis_tdata, s_axis_tdata_d0, s_axis_tdata_d1, s_axis_tdata_d2} != ~crc_next) begin
m_axis_tuser_int = 1'b1;
error_bad_fcs_next = 1'b1;
end
s_axis_tready_next = m_axis_tready_int_early;
state_next = STATE_IDLE;
end else begin
state_next = STATE_PAYLOAD;
end
end else begin
state_next = STATE_PAYLOAD;
end
end
endcase
end
always @(posedge clk) begin
if (rst) begin
state_reg <= STATE_IDLE;
s_axis_tready_reg <= 1'b0;
busy_reg <= 1'b0;
error_bad_fcs_reg <= 1'b0;
s_axis_tvalid_d0 <= 1'b0;
s_axis_tvalid_d1 <= 1'b0;
s_axis_tvalid_d2 <= 1'b0;
s_axis_tvalid_d3 <= 1'b0;
crc_state <= 32'hFFFFFFFF;
end else begin
state_reg <= state_next;
s_axis_tready_reg <= s_axis_tready_next;
busy_reg <= state_next != STATE_IDLE;
error_bad_fcs_reg <= error_bad_fcs_next;
// datapath
if (reset_crc) begin
crc_state <= 32'hFFFFFFFF;
end else if (update_crc) begin
crc_state <= crc_next;
end
if (shift_reset) begin
s_axis_tvalid_d0 <= 1'b0;
s_axis_tvalid_d1 <= 1'b0;
s_axis_tvalid_d2 <= 1'b0;
s_axis_tvalid_d3 <= 1'b0;
end else if (shift_in) begin
s_axis_tvalid_d0 <= s_axis_tvalid;
s_axis_tvalid_d1 <= s_axis_tvalid_d0;
s_axis_tvalid_d2 <= s_axis_tvalid_d1;
s_axis_tvalid_d3 <= s_axis_tvalid_d2;
end
end
if (shift_in) begin
s_axis_tdata_d0 <= s_axis_tdata;
s_axis_tdata_d1 <= s_axis_tdata_d0;
s_axis_tdata_d2 <= s_axis_tdata_d1;
s_axis_tdata_d3 <= s_axis_tdata_d2;
end
end
// output datapath logic
reg [7:0] m_axis_tdata_reg = 8'd0;
reg m_axis_tvalid_reg = 1'b0, m_axis_tvalid_next;
reg m_axis_tlast_reg = 1'b0;
reg m_axis_tuser_reg = 1'b0;
reg [7:0] temp_m_axis_tdata_reg = 8'd0;
reg temp_m_axis_tvalid_reg = 1'b0, temp_m_axis_tvalid_next;
reg temp_m_axis_tlast_reg = 1'b0;
reg temp_m_axis_tuser_reg = 1'b0;
// datapath control
reg store_axis_int_to_output;
reg store_axis_int_to_temp;
reg store_axis_temp_to_output;
assign m_axis_tdata = m_axis_tdata_reg;
assign m_axis_tvalid = m_axis_tvalid_reg;
assign m_axis_tlast = m_axis_tlast_reg;
assign m_axis_tuser = m_axis_tuser_reg;
// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
assign m_axis_tready_int_early = m_axis_tready || (!temp_m_axis_tvalid_reg && (!m_axis_tvalid_reg || !m_axis_tvalid_int));
always @* begin
// transfer sink ready state to source
m_axis_tvalid_next = m_axis_tvalid_reg;
temp_m_axis_tvalid_next = temp_m_axis_tvalid_reg;
store_axis_int_to_output = 1'b0;
store_axis_int_to_temp = 1'b0;
store_axis_temp_to_output = 1'b0;
if (m_axis_tready_int_reg) begin
// input is ready
if (m_axis_tready || !m_axis_tvalid_reg) begin
// output is ready or currently not valid, transfer data to output
m_axis_tvalid_next = m_axis_tvalid_int;
store_axis_int_to_output = 1'b1;
end else begin
// output is not ready, store input in temp
temp_m_axis_tvalid_next = m_axis_tvalid_int;
store_axis_int_to_temp = 1'b1;
end
end else if (m_axis_tready) begin
// input is not ready, but output is ready
m_axis_tvalid_next = temp_m_axis_tvalid_reg;
temp_m_axis_tvalid_next = 1'b0;
store_axis_temp_to_output = 1'b1;
end
end
always @(posedge clk) begin
if (rst) begin
m_axis_tvalid_reg <= 1'b0;
m_axis_tready_int_reg <= 1'b0;
temp_m_axis_tvalid_reg <= 1'b0;
end else begin
m_axis_tvalid_reg <= m_axis_tvalid_next;
m_axis_tready_int_reg <= m_axis_tready_int_early;
temp_m_axis_tvalid_reg <= temp_m_axis_tvalid_next;
end
// datapath
if (store_axis_int_to_output) begin
m_axis_tdata_reg <= m_axis_tdata_int;
m_axis_tlast_reg <= m_axis_tlast_int;
m_axis_tuser_reg <= m_axis_tuser_int;
end else if (store_axis_temp_to_output) begin
m_axis_tdata_reg <= temp_m_axis_tdata_reg;
m_axis_tlast_reg <= temp_m_axis_tlast_reg;
m_axis_tuser_reg <= temp_m_axis_tuser_reg;
end
if (store_axis_int_to_temp) begin
temp_m_axis_tdata_reg <= m_axis_tdata_int;
temp_m_axis_tlast_reg <= m_axis_tlast_int;
temp_m_axis_tuser_reg <= m_axis_tuser_int;
end
end
endmodule |
module ram #(
parameter WIDTH = 16,
parameter ADDR_WIDTH = 8
) (
input [WIDTH - 1:0] din,
input wire [ADDR_WIDTH - 1:0] addr,
input wire write_en,
input clk,
output reg [WIDTH - 1:0] dout);
localparam HI = WIDTH - 1;
localparam NWORDS = (WIDTH + 15) / 16;
localparam WIDTH_PAD = NWORDS * 16 - WIDTH;
localparam WIDTH_ALIGN = NWORDS * 16;
// Address
// addr[ADDR_WIDTH - 1:0]
// is split to 'offset' (in 16-bit words):
// offset = addr[7:0]
// and 'selector':
// sel = addr[ADDR_WIDTH - 1:8]
// The 8-bit 'offset' part can be mapped to block RAM
// and 'sel' is then implemented on top of it as mux.
localparam SEL_WIDTH = ADDR_WIDTH <= 8 ? 0 : ADDR_WIDTH - 8;
localparam NSEL = 1 << SEL_WIDTH;
wire [WIDTH_ALIGN - 1:0] din_pad;
wire [NSEL*WIDTH_ALIGN - 1:0] douts;
wire [7:0] offset;
wire [SEL_WIDTH - 1:0] sel;
assign din_pad = din;
assign offset = addr[7:0];
assign sel = NSEL == 1 ? 1'b0 : addr[ADDR_WIDTH - 1:8];
genvar i, j;
generate
for(i = 0; i < NSEL; i = i + 1) begin
for(j = 0; j < WIDTH_ALIGN; j = j + 16) begin
ram256x16 bank (
.din(din_pad[j + 15:j]),
.addr(offset),
.write_en(write_en & (sel == i)), // TODO: use decoder?
.clk(clk),
.dout(douts[i*WIDTH_ALIGN + j + 15:i*WIDTH_ALIGN + j]));
end
end
endgenerate
integer k, l;
always @* begin
dout = {WIDTH{1'bx}};
for(k = 0; k < NSEL; k = k + 1) begin
if (sel == k) // TODO: use decoder?
for (l = 0; l < WIDTH; l = l + 1)
dout[l] = douts[k*WIDTH_ALIGN + l];
end
end
endmodule |
module Spartan3AN_PicoBlaze_LCD(
//////////// CLOCK //////////
CLK_50M,
//////////// LCD //////////
LCD_DB,
LCD_E,
LCD_RS,
LCD_RW
);
//=======================================================
// PARAMETER declarations
//=======================================================
parameter LCD_PORT_ID = 8'h00;
//=======================================================
// PORT declarations
//=======================================================
input wire CLK_50M;
output wire [7:0] LCD_DB;
output wire LCD_E;
output wire LCD_RS;
output wire LCD_RW;
//=======================================================
// REG/WIRE declarations
//=======================================================
wire [7:0] Lcd_Port;
//=======================================================
// Structural coding
//=======================================================
//******************************************************************//
// Instantiate PicoBlaze and the Program ROM. //
//******************************************************************//
wire [9:0] address;
wire [17:0] instruction;
wire [7:0] port_id;
wire [7:0] out_port;
wire [7:0] in_port;
wire write_strobe;
wire read_strobe;
wire interrupt;
wire reset;
kcpsm3 kcpsm3_inst (
.address(address),
.instruction(instruction),
.port_id(port_id),
.write_strobe(write_strobe),
.out_port(out_port),
.read_strobe(read_strobe),
.in_port(in_port),
.interrupt(interrupt),
.interrupt_ack(),
.reset(reset),
.clk(CLK_50M));
picocode picocode_inst (
.address(address),
.instruction(instruction),
.clk(CLK_50M));
PicoBlaze_OutReg #(.LOCAL_PORT_ID(LCD_PORT_ID)) Lcd_Port_inst(
.clk(CLK_50M),
.reset(reset),
.port_id(port_id),
.write_strobe(write_strobe),
.out_port(out_port),
.new_out_port(Lcd_Port));
//=======================================================
// Connections & assigns
//=======================================================
//******************************************************************//
// Input PicoBlaze Interface. //
//******************************************************************//
assign in_port = 8'h00;
assign interrupt = 1'b0;
assign reset = 1'b0;
//******************************************************************//
// Output PicoBlaze Interface. //
//******************************************************************//
assign LCD_E=Lcd_Port[0];
assign LCD_RW=Lcd_Port[1];
assign LCD_RS=Lcd_Port[2];
assign LCD_DB={Lcd_Port[7:4],4'bzzzz};
endmodule |
module top();
// Inputs are registered
reg A;
reg B;
reg C_N;
reg VPWR;
reg VGND;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
B = 1'bX;
C_N = 1'bX;
VGND = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 B = 1'b0;
#60 C_N = 1'b0;
#80 VGND = 1'b0;
#100 VPWR = 1'b0;
#120 A = 1'b1;
#140 B = 1'b1;
#160 C_N = 1'b1;
#180 VGND = 1'b1;
#200 VPWR = 1'b1;
#220 A = 1'b0;
#240 B = 1'b0;
#260 C_N = 1'b0;
#280 VGND = 1'b0;
#300 VPWR = 1'b0;
#320 VPWR = 1'b1;
#340 VGND = 1'b1;
#360 C_N = 1'b1;
#380 B = 1'b1;
#400 A = 1'b1;
#420 VPWR = 1'bx;
#440 VGND = 1'bx;
#460 C_N = 1'bx;
#480 B = 1'bx;
#500 A = 1'bx;
end
sky130_fd_sc_hs__or3b dut (.A(A), .B(B), .C_N(C_N), .VPWR(VPWR), .VGND(VGND), .X(X));
endmodule |
module DMA_READ_QUEUE(
clk,
srst,
din,
wr_en,
rd_en,
dout,
full,
empty
);
input clk;
input srst;
input [63 : 0] din;
input wr_en;
input rd_en;
output [63 : 0] dout;
output full;
output empty;
// synthesis translate_off
FIFO_GENERATOR_V8_4 #(
.C_ADD_NGC_CONSTRAINT(0),
.C_APPLICATION_TYPE_AXIS(0),
.C_APPLICATION_TYPE_RACH(0),
.C_APPLICATION_TYPE_RDCH(0),
.C_APPLICATION_TYPE_WACH(0),
.C_APPLICATION_TYPE_WDCH(0),
.C_APPLICATION_TYPE_WRCH(0),
.C_AXI_ADDR_WIDTH(32),
.C_AXI_ARUSER_WIDTH(1),
.C_AXI_AWUSER_WIDTH(1),
.C_AXI_BUSER_WIDTH(1),
.C_AXI_DATA_WIDTH(64),
.C_AXI_ID_WIDTH(4),
.C_AXI_RUSER_WIDTH(1),
.C_AXI_TYPE(0),
.C_AXI_WUSER_WIDTH(1),
.C_AXIS_TDATA_WIDTH(64),
.C_AXIS_TDEST_WIDTH(4),
.C_AXIS_TID_WIDTH(8),
.C_AXIS_TKEEP_WIDTH(4),
.C_AXIS_TSTRB_WIDTH(4),
.C_AXIS_TUSER_WIDTH(4),
.C_AXIS_TYPE(0),
.C_COMMON_CLOCK(1),
.C_COUNT_TYPE(0),
.C_DATA_COUNT_WIDTH(5),
.C_DEFAULT_VALUE("BlankString"),
.C_DIN_WIDTH(64),
.C_DIN_WIDTH_AXIS(1),
.C_DIN_WIDTH_RACH(32),
.C_DIN_WIDTH_RDCH(64),
.C_DIN_WIDTH_WACH(32),
.C_DIN_WIDTH_WDCH(64),
.C_DIN_WIDTH_WRCH(2),
.C_DOUT_RST_VAL("0"),
.C_DOUT_WIDTH(64),
.C_ENABLE_RLOCS(0),
.C_ENABLE_RST_SYNC(1),
.C_ERROR_INJECTION_TYPE(0),
.C_ERROR_INJECTION_TYPE_AXIS(0),
.C_ERROR_INJECTION_TYPE_RACH(0),
.C_ERROR_INJECTION_TYPE_RDCH(0),
.C_ERROR_INJECTION_TYPE_WACH(0),
.C_ERROR_INJECTION_TYPE_WDCH(0),
.C_ERROR_INJECTION_TYPE_WRCH(0),
.C_FAMILY("virtex6"),
.C_FULL_FLAGS_RST_VAL(0),
.C_HAS_ALMOST_EMPTY(0),
.C_HAS_ALMOST_FULL(0),
.C_HAS_AXI_ARUSER(0),
.C_HAS_AXI_AWUSER(0),
.C_HAS_AXI_BUSER(0),
.C_HAS_AXI_RD_CHANNEL(0),
.C_HAS_AXI_RUSER(0),
.C_HAS_AXI_WR_CHANNEL(0),
.C_HAS_AXI_WUSER(0),
.C_HAS_AXIS_TDATA(0),
.C_HAS_AXIS_TDEST(0),
.C_HAS_AXIS_TID(0),
.C_HAS_AXIS_TKEEP(0),
.C_HAS_AXIS_TLAST(0),
.C_HAS_AXIS_TREADY(1),
.C_HAS_AXIS_TSTRB(0),
.C_HAS_AXIS_TUSER(0),
.C_HAS_BACKUP(0),
.C_HAS_DATA_COUNT(0),
.C_HAS_DATA_COUNTS_AXIS(0),
.C_HAS_DATA_COUNTS_RACH(0),
.C_HAS_DATA_COUNTS_RDCH(0),
.C_HAS_DATA_COUNTS_WACH(0),
.C_HAS_DATA_COUNTS_WDCH(0),
.C_HAS_DATA_COUNTS_WRCH(0),
.C_HAS_INT_CLK(0),
.C_HAS_MASTER_CE(0),
.C_HAS_MEMINIT_FILE(0),
.C_HAS_OVERFLOW(0),
.C_HAS_PROG_FLAGS_AXIS(0),
.C_HAS_PROG_FLAGS_RACH(0),
.C_HAS_PROG_FLAGS_RDCH(0),
.C_HAS_PROG_FLAGS_WACH(0),
.C_HAS_PROG_FLAGS_WDCH(0),
.C_HAS_PROG_FLAGS_WRCH(0),
.C_HAS_RD_DATA_COUNT(0),
.C_HAS_RD_RST(0),
.C_HAS_RST(0),
.C_HAS_SLAVE_CE(0),
.C_HAS_SRST(1),
.C_HAS_UNDERFLOW(0),
.C_HAS_VALID(0),
.C_HAS_WR_ACK(0),
.C_HAS_WR_DATA_COUNT(0),
.C_HAS_WR_RST(0),
.C_IMPLEMENTATION_TYPE(0),
.C_IMPLEMENTATION_TYPE_AXIS(1),
.C_IMPLEMENTATION_TYPE_RACH(1),
.C_IMPLEMENTATION_TYPE_RDCH(1),
.C_IMPLEMENTATION_TYPE_WACH(1),
.C_IMPLEMENTATION_TYPE_WDCH(1),
.C_IMPLEMENTATION_TYPE_WRCH(1),
.C_INIT_WR_PNTR_VAL(0),
.C_INTERFACE_TYPE(0),
.C_MEMORY_TYPE(2),
.C_MIF_FILE_NAME("BlankString"),
.C_MSGON_VAL(1),
.C_OPTIMIZATION_MODE(0),
.C_OVERFLOW_LOW(0),
.C_PRELOAD_LATENCY(0),
.C_PRELOAD_REGS(1),
.C_PRIM_FIFO_TYPE("512x72"),
.C_PROG_EMPTY_THRESH_ASSERT_VAL(4),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH(1022),
.C_PROG_EMPTY_THRESH_NEGATE_VAL(5),
.C_PROG_EMPTY_TYPE(0),
.C_PROG_EMPTY_TYPE_AXIS(5),
.C_PROG_EMPTY_TYPE_RACH(5),
.C_PROG_EMPTY_TYPE_RDCH(5),
.C_PROG_EMPTY_TYPE_WACH(5),
.C_PROG_EMPTY_TYPE_WDCH(5),
.C_PROG_EMPTY_TYPE_WRCH(5),
.C_PROG_FULL_THRESH_ASSERT_VAL(15),
.C_PROG_FULL_THRESH_ASSERT_VAL_AXIS(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_RACH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_RDCH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_WACH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_WDCH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_WRCH(1023),
.C_PROG_FULL_THRESH_NEGATE_VAL(14),
.C_PROG_FULL_TYPE(0),
.C_PROG_FULL_TYPE_AXIS(5),
.C_PROG_FULL_TYPE_RACH(5),
.C_PROG_FULL_TYPE_RDCH(5),
.C_PROG_FULL_TYPE_WACH(5),
.C_PROG_FULL_TYPE_WDCH(5),
.C_PROG_FULL_TYPE_WRCH(5),
.C_RACH_TYPE(0),
.C_RD_DATA_COUNT_WIDTH(5),
.C_RD_DEPTH(16),
.C_RD_FREQ(1),
.C_RD_PNTR_WIDTH(4),
.C_RDCH_TYPE(0),
.C_REG_SLICE_MODE_AXIS(0),
.C_REG_SLICE_MODE_RACH(0),
.C_REG_SLICE_MODE_RDCH(0),
.C_REG_SLICE_MODE_WACH(0),
.C_REG_SLICE_MODE_WDCH(0),
.C_REG_SLICE_MODE_WRCH(0),
.C_SYNCHRONIZER_STAGE(2),
.C_UNDERFLOW_LOW(0),
.C_USE_COMMON_OVERFLOW(0),
.C_USE_COMMON_UNDERFLOW(0),
.C_USE_DEFAULT_SETTINGS(0),
.C_USE_DOUT_RST(1),
.C_USE_ECC(0),
.C_USE_ECC_AXIS(0),
.C_USE_ECC_RACH(0),
.C_USE_ECC_RDCH(0),
.C_USE_ECC_WACH(0),
.C_USE_ECC_WDCH(0),
.C_USE_ECC_WRCH(0),
.C_USE_EMBEDDED_REG(0),
.C_USE_FIFO16_FLAGS(0),
.C_USE_FWFT_DATA_COUNT(1),
.C_VALID_LOW(0),
.C_WACH_TYPE(0),
.C_WDCH_TYPE(0),
.C_WR_ACK_LOW(0),
.C_WR_DATA_COUNT_WIDTH(5),
.C_WR_DEPTH(16),
.C_WR_DEPTH_AXIS(1024),
.C_WR_DEPTH_RACH(16),
.C_WR_DEPTH_RDCH(1024),
.C_WR_DEPTH_WACH(16),
.C_WR_DEPTH_WDCH(1024),
.C_WR_DEPTH_WRCH(16),
.C_WR_FREQ(1),
.C_WR_PNTR_WIDTH(4),
.C_WR_PNTR_WIDTH_AXIS(10),
.C_WR_PNTR_WIDTH_RACH(4),
.C_WR_PNTR_WIDTH_RDCH(10),
.C_WR_PNTR_WIDTH_WACH(4),
.C_WR_PNTR_WIDTH_WDCH(10),
.C_WR_PNTR_WIDTH_WRCH(4),
.C_WR_RESPONSE_LATENCY(1),
.C_WRCH_TYPE(0)
)
inst (
.CLK(clk),
.SRST(srst),
.DIN(din),
.WR_EN(wr_en),
.RD_EN(rd_en),
.DOUT(dout),
.FULL(full),
.EMPTY(empty),
.BACKUP(),
.BACKUP_MARKER(),
.RST(),
.WR_CLK(),
.WR_RST(),
.RD_CLK(),
.RD_RST(),
.PROG_EMPTY_THRESH(),
.PROG_EMPTY_THRESH_ASSERT(),
.PROG_EMPTY_THRESH_NEGATE(),
.PROG_FULL_THRESH(),
.PROG_FULL_THRESH_ASSERT(),
.PROG_FULL_THRESH_NEGATE(),
.INT_CLK(),
.INJECTDBITERR(),
.INJECTSBITERR(),
.ALMOST_FULL(),
.WR_ACK(),
.OVERFLOW(),
.ALMOST_EMPTY(),
.VALID(),
.UNDERFLOW(),
.DATA_COUNT(),
.RD_DATA_COUNT(),
.WR_DATA_COUNT(),
.PROG_FULL(),
.PROG_EMPTY(),
.SBITERR(),
.DBITERR(),
.M_ACLK(),
.S_ACLK(),
.S_ARESETN(),
.M_ACLK_EN(),
.S_ACLK_EN(),
.S_AXI_AWID(),
.S_AXI_AWADDR(),
.S_AXI_AWLEN(),
.S_AXI_AWSIZE(),
.S_AXI_AWBURST(),
.S_AXI_AWLOCK(),
.S_AXI_AWCACHE(),
.S_AXI_AWPROT(),
.S_AXI_AWQOS(),
.S_AXI_AWREGION(),
.S_AXI_AWUSER(),
.S_AXI_AWVALID(),
.S_AXI_AWREADY(),
.S_AXI_WID(),
.S_AXI_WDATA(),
.S_AXI_WSTRB(),
.S_AXI_WLAST(),
.S_AXI_WUSER(),
.S_AXI_WVALID(),
.S_AXI_WREADY(),
.S_AXI_BID(),
.S_AXI_BRESP(),
.S_AXI_BUSER(),
.S_AXI_BVALID(),
.S_AXI_BREADY(),
.M_AXI_AWID(),
.M_AXI_AWADDR(),
.M_AXI_AWLEN(),
.M_AXI_AWSIZE(),
.M_AXI_AWBURST(),
.M_AXI_AWLOCK(),
.M_AXI_AWCACHE(),
.M_AXI_AWPROT(),
.M_AXI_AWQOS(),
.M_AXI_AWREGION(),
.M_AXI_AWUSER(),
.M_AXI_AWVALID(),
.M_AXI_AWREADY(),
.M_AXI_WID(),
.M_AXI_WDATA(),
.M_AXI_WSTRB(),
.M_AXI_WLAST(),
.M_AXI_WUSER(),
.M_AXI_WVALID(),
.M_AXI_WREADY(),
.M_AXI_BID(),
.M_AXI_BRESP(),
.M_AXI_BUSER(),
.M_AXI_BVALID(),
.M_AXI_BREADY(),
.S_AXI_ARID(),
.S_AXI_ARADDR(),
.S_AXI_ARLEN(),
.S_AXI_ARSIZE(),
.S_AXI_ARBURST(),
.S_AXI_ARLOCK(),
.S_AXI_ARCACHE(),
.S_AXI_ARPROT(),
.S_AXI_ARQOS(),
.S_AXI_ARREGION(),
.S_AXI_ARUSER(),
.S_AXI_ARVALID(),
.S_AXI_ARREADY(),
.S_AXI_RID(),
.S_AXI_RDATA(),
.S_AXI_RRESP(),
.S_AXI_RLAST(),
.S_AXI_RUSER(),
.S_AXI_RVALID(),
.S_AXI_RREADY(),
.M_AXI_ARID(),
.M_AXI_ARADDR(),
.M_AXI_ARLEN(),
.M_AXI_ARSIZE(),
.M_AXI_ARBURST(),
.M_AXI_ARLOCK(),
.M_AXI_ARCACHE(),
.M_AXI_ARPROT(),
.M_AXI_ARQOS(),
.M_AXI_ARREGION(),
.M_AXI_ARUSER(),
.M_AXI_ARVALID(),
.M_AXI_ARREADY(),
.M_AXI_RID(),
.M_AXI_RDATA(),
.M_AXI_RRESP(),
.M_AXI_RLAST(),
.M_AXI_RUSER(),
.M_AXI_RVALID(),
.M_AXI_RREADY(),
.S_AXIS_TVALID(),
.S_AXIS_TREADY(),
.S_AXIS_TDATA(),
.S_AXIS_TSTRB(),
.S_AXIS_TKEEP(),
.S_AXIS_TLAST(),
.S_AXIS_TID(),
.S_AXIS_TDEST(),
.S_AXIS_TUSER(),
.M_AXIS_TVALID(),
.M_AXIS_TREADY(),
.M_AXIS_TDATA(),
.M_AXIS_TSTRB(),
.M_AXIS_TKEEP(),
.M_AXIS_TLAST(),
.M_AXIS_TID(),
.M_AXIS_TDEST(),
.M_AXIS_TUSER(),
.AXI_AW_INJECTSBITERR(),
.AXI_AW_INJECTDBITERR(),
.AXI_AW_PROG_FULL_THRESH(),
.AXI_AW_PROG_EMPTY_THRESH(),
.AXI_AW_DATA_COUNT(),
.AXI_AW_WR_DATA_COUNT(),
.AXI_AW_RD_DATA_COUNT(),
.AXI_AW_SBITERR(),
.AXI_AW_DBITERR(),
.AXI_AW_OVERFLOW(),
.AXI_AW_UNDERFLOW(),
.AXI_W_INJECTSBITERR(),
.AXI_W_INJECTDBITERR(),
.AXI_W_PROG_FULL_THRESH(),
.AXI_W_PROG_EMPTY_THRESH(),
.AXI_W_DATA_COUNT(),
.AXI_W_WR_DATA_COUNT(),
.AXI_W_RD_DATA_COUNT(),
.AXI_W_SBITERR(),
.AXI_W_DBITERR(),
.AXI_W_OVERFLOW(),
.AXI_W_UNDERFLOW(),
.AXI_B_INJECTSBITERR(),
.AXI_B_INJECTDBITERR(),
.AXI_B_PROG_FULL_THRESH(),
.AXI_B_PROG_EMPTY_THRESH(),
.AXI_B_DATA_COUNT(),
.AXI_B_WR_DATA_COUNT(),
.AXI_B_RD_DATA_COUNT(),
.AXI_B_SBITERR(),
.AXI_B_DBITERR(),
.AXI_B_OVERFLOW(),
.AXI_B_UNDERFLOW(),
.AXI_AR_INJECTSBITERR(),
.AXI_AR_INJECTDBITERR(),
.AXI_AR_PROG_FULL_THRESH(),
.AXI_AR_PROG_EMPTY_THRESH(),
.AXI_AR_DATA_COUNT(),
.AXI_AR_WR_DATA_COUNT(),
.AXI_AR_RD_DATA_COUNT(),
.AXI_AR_SBITERR(),
.AXI_AR_DBITERR(),
.AXI_AR_OVERFLOW(),
.AXI_AR_UNDERFLOW(),
.AXI_R_INJECTSBITERR(),
.AXI_R_INJECTDBITERR(),
.AXI_R_PROG_FULL_THRESH(),
.AXI_R_PROG_EMPTY_THRESH(),
.AXI_R_DATA_COUNT(),
.AXI_R_WR_DATA_COUNT(),
.AXI_R_RD_DATA_COUNT(),
.AXI_R_SBITERR(),
.AXI_R_DBITERR(),
.AXI_R_OVERFLOW(),
.AXI_R_UNDERFLOW(),
.AXIS_INJECTSBITERR(),
.AXIS_INJECTDBITERR(),
.AXIS_PROG_FULL_THRESH(),
.AXIS_PROG_EMPTY_THRESH(),
.AXIS_DATA_COUNT(),
.AXIS_WR_DATA_COUNT(),
.AXIS_RD_DATA_COUNT(),
.AXIS_SBITERR(),
.AXIS_DBITERR(),
.AXIS_OVERFLOW(),
.AXIS_UNDERFLOW()
);
// synthesis translate_on
endmodule |
module BRAMTDC_256_SWITCHING (d, q, tdc_event, tdc_readnext, tdc_switch, CLK, tdc_request, data_size);
parameter width = 1;
output wire [(width*36)-1:0] q;
input wire [(width*36)-1:0] d;
input wire CLK;
input wire tdc_event;
input wire tdc_readnext;
input wire tdc_switch;
input wire tdc_request;
output reg [7:0] data_size;
wire [31:0] data_size_counter;
slimfast_multioption_counter #(.clip_count(0)) DATASIZE_COUNTER (
.countClock(CLK),
.count(tdc_event == 1'b1 && data_size_counter[7:0] != 8'b1111_1111),
.reset(tdc_request),
.countout(data_size_counter));
always@(posedge CLK)
begin
//the stored data_size is without the trigger, so a size of "2" are 3 events
if (tdc_switch == 1'b1) data_size <= data_size_counter[7:0];
end
genvar k;
generate
for (k=0; k < width; k=k+1) begin : TDCS
(* EQUIVALENT_REGISTER_REMOVAL="NO" *) reg area = 1'b0;
wire [31:0] a_write_counter;
wire [7:0] a_read_counter;
wire [7:0] a_write = a_write_counter[7:0];
wire [7:0] a_read = a_read_counter[7:0];
//he will complain about "Property EQUIVALENT REGISTER REMOVAL not applicable on a instance", but it works
(* EQUIVALENT_REGISTER_REMOVAL="NO" *) slimfast_multioption_counter #(.clip_count(0)) WRITE_ADDR_COUNTER (
.countClock(CLK),
.count(tdc_event),
.reset(1'b0),
.countout(a_write_counter));
//he will complain about "Property EQUIVALENT REGISTER REMOVAL not applicable on a instance", but it works
(* EQUIVALENT_REGISTER_REMOVAL="NO" *) loadable_downcounter8 READ_ADDR_COUNTER (
.countClock(CLK),
.count(tdc_readnext),
.loadvalue(a_write),
.load(tdc_switch),
.countout(a_read_counter));
always@(posedge CLK)
begin
if (tdc_switch == 1'b1) area <= ~area;
end
RAMB16_S36_S36 #(
.INIT_A(36'h000000000), // Value of output RAM registers on Port A at startup
.INIT_B(36'h000000000), // Value of output RAM registers on Port B at startup
.SRVAL_A(36'h000000000), // Port A output value upon SSR assertion
.SRVAL_B(36'h000000000), // Port B output value upon SSR assertion
.WRITE_MODE_A("WRITE_FIRST"), // WRITE_FIRST, READ_FIRST or NO_CHANGE
.WRITE_MODE_B("WRITE_FIRST"), // WRITE_FIRST, READ_FIRST or NO_CHANGE
.SIM_COLLISION_CHECK("ALL"), // "NONE", "WARNING_ONLY", "GENERATE_X_ONLY", "ALL"
// The following INIT_xx declarations specify the initial contents of the RAM
// Address 0 to 127
.INIT_00(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
.INIT_01(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
.INIT_02(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
.INIT_03(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
.INIT_04(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
.INIT_05(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
.INIT_06(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
.INIT_07(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
.INIT_08(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
.INIT_09(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
.INIT_0A(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
.INIT_0B(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
.INIT_0C(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
.INIT_0D(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
.INIT_0E(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
.INIT_0F(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
// Address 128 to 255
.INIT_10(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
.INIT_11(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
.INIT_12(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
.INIT_13(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
.INIT_14(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
.INIT_15(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
.INIT_16(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
.INIT_17(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
.INIT_18(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
.INIT_19(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
.INIT_1A(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
.INIT_1B(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
.INIT_1C(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
.INIT_1D(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
.INIT_1E(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
.INIT_1F(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
// Address 256 to 383
.INIT_20(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
.INIT_21(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
.INIT_22(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
.INIT_23(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
.INIT_24(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
.INIT_25(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
.INIT_26(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
.INIT_27(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
.INIT_28(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
.INIT_29(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
.INIT_2A(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
.INIT_2B(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
.INIT_2C(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
.INIT_2D(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
.INIT_2E(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
.INIT_2F(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
// Address 384 to 511
.INIT_30(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
.INIT_31(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
.INIT_32(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
.INIT_33(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
.INIT_34(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
.INIT_35(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
.INIT_36(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
.INIT_37(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
.INIT_38(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
.INIT_39(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
.INIT_3A(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
.INIT_3B(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
.INIT_3C(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
.INIT_3D(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
.INIT_3E(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
.INIT_3F(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
// The next set of INITP_xx are for the parity bits
// Address 0 to 127
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
// Address 128 to 255
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
// Address 256 to 383
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
// Address 384 to 511
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000)
) RAMB_TDC (
.DIA(d[k*36+31:k*36]), // Port A 32-bit Data Input
.DIPA(d[k*36+35:k*36+32]), // Port A 4-bit parity Input
.DOA(), // Port A 32-bit Data Output
.DOPA(), // Port A 4-bit Parity Output
.ADDRA({area,a_write}), // Port B 9-bit Address Input
.CLKA(CLK), // Port A Clock
.WEA(1'b1), // Port A Write Enable Input
.ENA(1'b1), // Port A RAM Enable Input
.SSRA(1'b0), // Port A Synchronous Set/Reset Input
.DIB(32'b0), // Port B 32-bit Data Input
.DIPB(4'b0), // Port-B 4-bit parity Input
.DOB(q[k*36+31:k*36]), // Port B 32-bit Data Output
.DOPB(q[k*36+35:k*36+32]), // Port B 4-bit Parity Output
.ADDRB({~area,a_read}), // Port A 9-bit Address Input
.CLKB(CLK), // Port B Clock
.ENB(1'b1), // Port B RAM Enable Input
.SSRB(1'b0), // Port B Synchronous Set/Reset Input
.WEB(1'b0) // Port B Write Enable Input
);
end
endgenerate
endmodule |
module sky130_fd_sc_ms__nand4b (
Y ,
A_N ,
B ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A_N ;
input B ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire not0_out ;
wire nand0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
not not0 (not0_out , A_N );
nand nand0 (nand0_out_Y , D, C, B, not0_out );
sky130_fd_sc_ms__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nand0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule |
module top(
//////// CLOCK //////////
input CLOCK_50,
//input CLOCK2_50,
//input CLOCK3_50,
//input ENETCLK_25,
//////// Sma //////////
//input SMA_CLKIN,
//output SMA_CLKOUT,
//////// LED //////////
output [8:0] LEDG,
output [17:0] LEDR,
//////// KEY //////////
input [3:0] KEY,
//////// SW //////////
input [17:0] SW,
//////// SEG7 //////////
output [6:0] HEX0,
output [6:0] HEX1,
output [6:0] HEX2,
output [6:0] HEX3,
output [6:0] HEX4,
output [6:0] HEX5,
output [6:0] HEX6,
output [6:0] HEX7,
//////// LCD //////////
//output LCD_BLON,
//inout [7:0] LCD_DATA,
//output LCD_EN,
//output LCD_ON,
//output LCD_RS,
//output LCD_RW,
//////////// RS232 //////////
//output UART_CTS,
//input UART_RTS,
input UART_RXD,
output UART_TXD,
//////////// PS2 //////////
//inout PS2_CLK,
//inout PS2_DAT,
//inout PS2_CLK2,
//inout PS2_DAT2,
//////////// SDCARD //////////
//output SD_CLK,
//inout SD_CMD,
//inout [3:0] SD_DAT,
//input SD_WP_N,
//////////// VGA //////////
//output [7:0] VGA_B,
//output VGA_BLANK_N,
//output VGA_CLK,
//output [7:0] VGA_G,
//output VGA_HS,
//output [7:0] VGA_R,
//output VGA_SYNC_N,
//output VGA_VS,
//////////// Audio //////////
//input AUD_ADCDAT,
//inout AUD_ADCLRCK,
//inout AUD_BCLK,
//output AUD_DACDAT,
//inout AUD_DACLRCK,
//output AUD_XCK,
//////////// I2C for EEPROM //////////
//output EEP_I2C_SCLK,
//inout EEP_I2C_SDAT,
//////////// I2C for Audio and Tv-Decode //////////
//output I2C_SCLK,
//inout I2C_SDAT,
//////////// Ethernet 0 //////////
//output ENET0_GTX_CLK,
//input ENET0_INT_N,
//output ENET0_MDC,
//inout ENET0_MDIO,
//output ENET0_RST_N,
//input ENET0_RX_CLK,
//input ENET0_RX_COL,
//input ENET0_RX_CRS,
//input [3:0] ENET0_RX_DATA,
//input ENET0_RX_DV,
//input ENET0_RX_ER,
//input ENET0_TX_CLK,
//output [3:0] ENET0_TX_DATA,
//output ENET0_TX_EN,
//output ENET0_TX_ER,
//input ENET0_LINK100,
//////////// Ethernet 1 //////////
//output ENET1_GTX_CLK,
//input ENET1_INT_N,
//output ENET1_MDC,
//inout ENET1_MDIO,
//output ENET1_RST_N,
//input ENET1_RX_CLK,
//input ENET1_RX_COL,
//input ENET1_RX_CRS,
//input [3:0] ENET1_RX_DATA,
//input ENET1_RX_DV,
//input ENET1_RX_ER,
//input ENET1_TX_CLK,
//output [3:0] ENET1_TX_DATA,
//output ENET1_TX_EN,
//output ENET1_TX_ER,
//input ENET1_LINK100,
//////////// TV Decoder 1 //////////
//input TD_CLK27,
//input [7:0] TD_DATA,
//input TD_HS,
//output TD_RESET_N,
//input TD_VS,
//////////// USB OTG controller //////////
//inout [15:0] OTG_DATA,
//output [1:0] OTG_ADDR,
//output OTG_CS_N,
//output OTG_WR_N,
//output OTG_RD_N,
//input [1:0] OTG_INT,
//output OTG_RST_N,
//input [1:0] OTG_DREQ,
//output [1:0] OTG_DACK_N,
//inout OTG_FSPEED,
//inout OTG_LSPEED,
//////////// IR Receiver //////////
//input IRDA_RXD,
//////////// SDRAM //////////
//output [12:0] DRAM_ADDR,
//output [1:0] DRAM_BA,
//output DRAM_CAS_N,
//output DRAM_CKE,
//output DRAM_CLK,
//output DRAM_CS_N,
//inout [31:0] DRAM_DQ,
//output [3:0] DRAM_DQM,
//output DRAM_RAS_N,
//output DRAM_WE_N,
//////////// SRAM //////////
//output [19:0] SRAM_ADDR,
//output SRAM_CE_N,
//inout [15:0] SRAM_DQ,
//output SRAM_LB_N,
//output SRAM_OE_N,
//output SRAM_UB_N,
//output SRAM_WE_N,
//////////// Flash //////////
//output [22:0] FL_ADDR,
//output FL_CE_N,
//inout [7:0] FL_DQ,
//output FL_OE_N,
//output FL_RST_N,
//input FL_RY,
//output FL_WE_N,
//output FL_WP_N,
//////////// GPIO //////////
inout [35:0] GPIO,
//////////// HSMC (LVDS) //////////
//input HSMC_CLKIN_N1,
//input HSMC_CLKIN_N2,
//input HSMC_CLKIN_P1,
//input HSMC_CLKIN_P2,
//input HSMC_CLKIN0,
//output HSMC_CLKOUT_N1,
//output HSMC_CLKOUT_N2,
//output HSMC_CLKOUT_P1,
//output HSMC_CLKOUT_P2,
//output HSMC_CLKOUT0,
//inout [3:0] HSMC_D,
//input [16:0] HSMC_RX_D_N,
//input [16:0] HSMC_RX_D_P,
//output [16:0] HSMC_TX_D_N,
//output [16:0] HSMC_TX_D_P,
//////// EXTEND IO //////////
//inout [6:0] EX_IO,
/* put a dummy input here to satisfy the apparent requirement that there be something immediately before ); */
input _DUMMY
);
/* global regs */
reg rst;
reg halt;
initial begin
rst <= 0;
halt <= 0;
end
always @(posedge fastclk)
begin
rst = !KEY[0];
end
wire fastclk = CLOCK_50;
/* latch halt on the negedge of the main clock to keep it from glitching the clock
if you hit the key in the middle of an up phase */
always @(negedge fastclk)
begin
if (!KEY[1]) begin
halt <= 1;
end else begin
halt <= 0;
end
end
/* clock generation */
wire slowclk = !halt ? fastclk : 1'b0;
/* instantiate the cpu */
wire cpu_re;
wire cpu_we;
wire [29:0] memaddr;
wire [31:0] rmemdata;
wire [31:0] wmemdata;
wire [31:0] cpudebugout;
cpu cpu0(
.clk(slowclk),
.rst(rst),
.mem_re(cpu_re),
.mem_we(cpu_we),
.memaddr(memaddr),
.rmemdata(rmemdata),
.wmemdata(wmemdata),
.debugout(cpudebugout)
);
/* main memory */
wire mem_re = cpu_re && (memaddr[29] == 0);
wire mem_we = cpu_we && (memaddr[29] == 0);
syncmem mem0(
.clk(slowclk),
.re(mem_re),
.we(mem_we),
.addr(memaddr),
.rdata(rmemdata),
.wdata(wmemdata)
);
/* uart */
wire uart_re = cpu_re && (memaddr[29:14] == 16'b1000000000000000);
wire uart_we = cpu_we && (memaddr[29:14] == 16'b1000000000000000);
uart uart0(
.clk(slowclk),
.rst(rst),
.hwtx(UART_TXD),
.hwrx(UART_RXD),
.addr(memaddr[0]),
.re(uart_re),
.we(uart_we),
.wdata(wmemdata),
.rdata(rmemdata),
.rxchar(),
.rxvalid()
);
/* debug register */
wire debuglatch_we = cpu_we && (memaddr[29:14] == 16'b1000000000000001);
reg[31:0] debuglatch;
always @(posedge slowclk) begin
if (debuglatch_we) begin
debuglatch <= wmemdata;
end
end
//`define WITH_SRAM
`ifdef WITH_SRAM
assign SRAM_UB_N = 0;
assign SRAM_LB_N = 0;
wire read_sync;
wire write_sync;
integer addr;
reg [1:0] retest;
always @(negedge slowclk) begin
retest <= retest + 1;
end
always @(posedge read_sync or posedge write_sync) begin
addr <= addr + 1;
end
sramcontroller sram(
.clk(slowclk),
.addr(addr),
.indata(0),
.re(retest[1]),
.we(retest[0]),
.read_sync(read_sync),
.write_sync(write_sync),
.memclk(memclk),
.sram_addr(SRAM_ADDR),
.sram_data(SRAM_DQ),
.sram_ce(SRAM_CE_N),
.sram_re(SRAM_OE_N),
.sram_we(SRAM_WE_N)
);
`endif
reg[31:0] debugreg;
always @*
begin
if (SW[1]) begin
debugreg = cpudebugout;
end else if (SW[1]) begin
debugreg = rmemdata[31:0];
end else if (SW[0]) begin
debugreg = debuglatch[31:0];
end else begin
debugreg = memaddr[29:0];
end
end
/* debug info */
seven_segment seg0(debugreg[3:0], HEX0);
seven_segment seg1(debugreg[7:4], HEX1);
seven_segment seg2(debugreg[11:8], HEX2);
seven_segment seg3(debugreg[15:12], HEX3);
seven_segment seg4(debugreg[19:16], HEX4);
seven_segment seg5(debugreg[23:20], HEX5);
seven_segment seg6(debugreg[27:24], HEX6);
seven_segment seg7(debugreg[31:28], HEX7);
assign LEDG[0] = rst;
assign LEDG[1] = slowclk;
assign LEDG[2] = mem_re;
assign LEDG[3] = mem_we;
assign LEDG[8:4] = 0;
assign LEDR = 0;
assign GPIO = 0;
//assign GPIO_1[0] = slowclk;
//assign GPIO_1[1] = mem_re;
//assign GPIO_1[2] = mem_we;
//assign GPIO_1[7:3] = memaddr[4:0];
//assign GPIO_1[15:8] = wmemdata[7:0];
//assign GPIO_1[8] = memclk;
//assign GPIO_1[9] = read_sync;
//assign GPIO_1[10] = write_sync;
//assign GPIO_1[11] = SRAM_CE_N;
//assign GPIO_1[12] = SRAM_OE_N;
//assign GPIO_1[15:13] = SRAM_ADDR[2:0];
//assign GPIO_1[0] = UART_TXD;
//assign GPIO_1[1] = UART_RXD;
endmodule |
module syncmem(
input clk,
input re,
input we,
input [29:0] addr,
output reg [31:0] rdata,
input [31:0] wdata
);
reg [31:0] mem [0:4096];
initial begin
$readmemh("../test/test2.asm.hex", mem);
end
always @(posedge clk) begin
if (re)
rdata <= mem[addr];
else
rdata <= 32'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz;
if (we)
mem[addr] <= wdata;
end
endmodule |
module outputs)
wire dut_access; // From dv_elink of dv_elink.v
wire dut_failed; // From dv_elink of dv_elink.v
wire [PW-1:0] dut_packet; // From dv_elink of dv_elink.v
wire dut_passed; // From dv_elink of dv_elink.v
wire dut_rd_wait; // From dv_elink of dv_elink.v
wire dut_wr_wait; // From dv_elink of dv_elink.v
// End of automatics
emesh2packet e2p (
// Outputs
.packet_out (ext_packet[PW-1:0]),
// Inputs
.access_in (ext_access),
.write_in (ext_write),
.datamode_in (ext_datamode[1:0]),
.ctrlmode_in (ext_ctrlmode[3:0]),
.dstaddr_in (ext_dstaddr[AW-1:0]),
.data_in (ext_data[DW-1:0]),
.srcaddr_in (ext_srcaddr[AW-1:0]));
//dut
dv_elink dv_elink(/*AUTOINST*/
// Outputs
.dut_passed (dut_passed),
.dut_failed (dut_failed),
.dut_rd_wait (dut_rd_wait),
.dut_wr_wait (dut_wr_wait),
.dut_access (dut_access),
.dut_packet (dut_packet[PW-1:0]),
// Inputs
.clk (clk),
.reset (reset),
.ext_access (ext_access),
.ext_packet (ext_packet[PW-1:0]),
.ext_rd_wait (ext_rd_wait),
.ext_wr_wait (ext_wr_wait));
endmodule |
module Rotator(
input[31:0] RotatorIn,
input[4:0] RotatorBitNum,
input[1:0] RotatorOp,
output[31:0] RotatorOut
);
/*
reg[31:0] RotatorIn;
reg[4:0] RotatorBitNum;
reg[1:0] RotatorOp;
initial begin
RotatorIn = 32'h00001998;
RotatorBitNum = 5'b11001;
RotatorOp = 0;
#100
RotatorOp = 2;
#100
RotatorOp = 3;
end*/
assign RotatorOut =
{32{RotatorOp==2'b00}} & (RotatorIn[31:0] << {1'b0,RotatorBitNum[4:0]}) |
{32{RotatorOp==2'b10}} & ({32'h0,RotatorIn[31:0]} >> {1'b0,RotatorBitNum[4:0]}) |
{32{RotatorOp==2'b11}} & ({{32{RotatorIn[31]}}, RotatorIn[31:0]} >> {1'b0,RotatorBitNum[4:0]}) ;
endmodule |
module design_1_auto_pc_1 (
aclk,
aresetn,
s_axi_awid,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awlock,
s_axi_awcache,
s_axi_awprot,
s_axi_awqos,
s_axi_awvalid,
s_axi_awready,
s_axi_wid,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wvalid,
s_axi_wready,
s_axi_bid,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_arid,
s_axi_araddr,
s_axi_arlen,
s_axi_arsize,
s_axi_arburst,
s_axi_arlock,
s_axi_arcache,
s_axi_arprot,
s_axi_arqos,
s_axi_arvalid,
s_axi_arready,
s_axi_rid,
s_axi_rdata,
s_axi_rresp,
s_axi_rlast,
s_axi_rvalid,
s_axi_rready,
m_axi_awaddr,
m_axi_awprot,
m_axi_awvalid,
m_axi_awready,
m_axi_wdata,
m_axi_wstrb,
m_axi_wvalid,
m_axi_wready,
m_axi_bresp,
m_axi_bvalid,
m_axi_bready,
m_axi_araddr,
m_axi_arprot,
m_axi_arvalid,
m_axi_arready,
m_axi_rdata,
m_axi_rresp,
m_axi_rvalid,
m_axi_rready
);
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLK CLK" *)
input wire aclk;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RST RST" *)
input wire aresetn;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWID" *)
input wire [11 : 0] s_axi_awid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *)
input wire [31 : 0] s_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLEN" *)
input wire [3 : 0] s_axi_awlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE" *)
input wire [2 : 0] s_axi_awsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWBURST" *)
input wire [1 : 0] s_axi_awburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK" *)
input wire [1 : 0] s_axi_awlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE" *)
input wire [3 : 0] s_axi_awcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWPROT" *)
input wire [2 : 0] s_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWQOS" *)
input wire [3 : 0] s_axi_awqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWVALID" *)
input wire s_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREADY" *)
output wire s_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WID" *)
input wire [11 : 0] s_axi_wid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WDATA" *)
input wire [31 : 0] s_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WSTRB" *)
input wire [3 : 0] s_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WLAST" *)
input wire s_axi_wlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WVALID" *)
input wire s_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *)
output wire s_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BID" *)
output wire [11 : 0] s_axi_bid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *)
output wire [1 : 0] s_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *)
output wire s_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *)
input wire s_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARID" *)
input wire [11 : 0] s_axi_arid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARADDR" *)
input wire [31 : 0] s_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLEN" *)
input wire [3 : 0] s_axi_arlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARSIZE" *)
input wire [2 : 0] s_axi_arsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARBURST" *)
input wire [1 : 0] s_axi_arburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLOCK" *)
input wire [1 : 0] s_axi_arlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARCACHE" *)
input wire [3 : 0] s_axi_arcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARPROT" *)
input wire [2 : 0] s_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARQOS" *)
input wire [3 : 0] s_axi_arqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARVALID" *)
input wire s_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREADY" *)
output wire s_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RID" *)
output wire [11 : 0] s_axi_rid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RDATA" *)
output wire [31 : 0] s_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RRESP" *)
output wire [1 : 0] s_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RLAST" *)
output wire s_axi_rlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RVALID" *)
output wire s_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *)
input wire s_axi_rready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWADDR" *)
output wire [31 : 0] m_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWPROT" *)
output wire [2 : 0] m_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWVALID" *)
output wire m_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREADY" *)
input wire m_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WDATA" *)
output wire [31 : 0] m_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WSTRB" *)
output wire [3 : 0] m_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WVALID" *)
output wire m_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WREADY" *)
input wire m_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BRESP" *)
input wire [1 : 0] m_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BVALID" *)
input wire m_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BREADY" *)
output wire m_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARADDR" *)
output wire [31 : 0] m_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARPROT" *)
output wire [2 : 0] m_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARVALID" *)
output wire m_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREADY" *)
input wire m_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RDATA" *)
input wire [31 : 0] m_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RRESP" *)
input wire [1 : 0] m_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RVALID" *)
input wire m_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RREADY" *)
output wire m_axi_rready;
axi_protocol_converter_v2_1_8_axi_protocol_converter #(
.C_FAMILY("zynq"),
.C_M_AXI_PROTOCOL(2),
.C_S_AXI_PROTOCOL(1),
.C_IGNORE_ID(0),
.C_AXI_ID_WIDTH(12),
.C_AXI_ADDR_WIDTH(32),
.C_AXI_DATA_WIDTH(32),
.C_AXI_SUPPORTS_WRITE(1),
.C_AXI_SUPPORTS_READ(1),
.C_AXI_SUPPORTS_USER_SIGNALS(0),
.C_AXI_AWUSER_WIDTH(1),
.C_AXI_ARUSER_WIDTH(1),
.C_AXI_WUSER_WIDTH(1),
.C_AXI_RUSER_WIDTH(1),
.C_AXI_BUSER_WIDTH(1),
.C_TRANSLATION_MODE(2)
) inst (
.aclk(aclk),
.aresetn(aresetn),
.s_axi_awid(s_axi_awid),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awlen(s_axi_awlen),
.s_axi_awsize(s_axi_awsize),
.s_axi_awburst(s_axi_awburst),
.s_axi_awlock(s_axi_awlock),
.s_axi_awcache(s_axi_awcache),
.s_axi_awprot(s_axi_awprot),
.s_axi_awregion(4'H0),
.s_axi_awqos(s_axi_awqos),
.s_axi_awuser(1'H0),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_awready(s_axi_awready),
.s_axi_wid(s_axi_wid),
.s_axi_wdata(s_axi_wdata),
.s_axi_wstrb(s_axi_wstrb),
.s_axi_wlast(s_axi_wlast),
.s_axi_wuser(1'H0),
.s_axi_wvalid(s_axi_wvalid),
.s_axi_wready(s_axi_wready),
.s_axi_bid(s_axi_bid),
.s_axi_bresp(s_axi_bresp),
.s_axi_buser(),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_bready(s_axi_bready),
.s_axi_arid(s_axi_arid),
.s_axi_araddr(s_axi_araddr),
.s_axi_arlen(s_axi_arlen),
.s_axi_arsize(s_axi_arsize),
.s_axi_arburst(s_axi_arburst),
.s_axi_arlock(s_axi_arlock),
.s_axi_arcache(s_axi_arcache),
.s_axi_arprot(s_axi_arprot),
.s_axi_arregion(4'H0),
.s_axi_arqos(s_axi_arqos),
.s_axi_aruser(1'H0),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_arready(s_axi_arready),
.s_axi_rid(s_axi_rid),
.s_axi_rdata(s_axi_rdata),
.s_axi_rresp(s_axi_rresp),
.s_axi_rlast(s_axi_rlast),
.s_axi_ruser(),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_rready(s_axi_rready),
.m_axi_awid(),
.m_axi_awaddr(m_axi_awaddr),
.m_axi_awlen(),
.m_axi_awsize(),
.m_axi_awburst(),
.m_axi_awlock(),
.m_axi_awcache(),
.m_axi_awprot(m_axi_awprot),
.m_axi_awregion(),
.m_axi_awqos(),
.m_axi_awuser(),
.m_axi_awvalid(m_axi_awvalid),
.m_axi_awready(m_axi_awready),
.m_axi_wid(),
.m_axi_wdata(m_axi_wdata),
.m_axi_wstrb(m_axi_wstrb),
.m_axi_wlast(),
.m_axi_wuser(),
.m_axi_wvalid(m_axi_wvalid),
.m_axi_wready(m_axi_wready),
.m_axi_bid(12'H000),
.m_axi_bresp(m_axi_bresp),
.m_axi_buser(1'H0),
.m_axi_bvalid(m_axi_bvalid),
.m_axi_bready(m_axi_bready),
.m_axi_arid(),
.m_axi_araddr(m_axi_araddr),
.m_axi_arlen(),
.m_axi_arsize(),
.m_axi_arburst(),
.m_axi_arlock(),
.m_axi_arcache(),
.m_axi_arprot(m_axi_arprot),
.m_axi_arregion(),
.m_axi_arqos(),
.m_axi_aruser(),
.m_axi_arvalid(m_axi_arvalid),
.m_axi_arready(m_axi_arready),
.m_axi_rid(12'H000),
.m_axi_rdata(m_axi_rdata),
.m_axi_rresp(m_axi_rresp),
.m_axi_rlast(1'H1),
.m_axi_ruser(1'H0),
.m_axi_rvalid(m_axi_rvalid),
.m_axi_rready(m_axi_rready)
);
endmodule |
module sky130_fd_sc_hd__lpflow_isobufsrckapwr_16 (
X ,
SLEEP,
A ,
KAPWR,
VPWR ,
VGND ,
VPB ,
VNB
);
output X ;
input SLEEP;
input A ;
input KAPWR;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_hd__lpflow_isobufsrckapwr base (
.X(X),
.SLEEP(SLEEP),
.A(A),
.KAPWR(KAPWR),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule |
module sky130_fd_sc_hd__lpflow_isobufsrckapwr_16 (
X ,
SLEEP,
A
);
output X ;
input SLEEP;
input A ;
// Voltage supply signals
supply1 KAPWR;
supply1 VPWR ;
supply0 VGND ;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__lpflow_isobufsrckapwr base (
.X(X),
.SLEEP(SLEEP),
.A(A)
);
endmodule |
module sky130_fd_sc_lp__a21oi (
Y ,
A1 ,
A2 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire and0_out ;
wire nor0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
and and0 (and0_out , A1, A2 );
nor nor0 (nor0_out_Y , B1, and0_out );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nor0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule |
module BDCLed_TBV (
);
// myHDL -> Verilog Testbench for `BDCLed`
reg clk = 0;
wire [1:0] sw;
reg [3:0] led = 0;
wire [7:0] BDCLed0_0_duty_led;
reg [7:0] BDCLed0_0_counter = 0;
assign sw = 2'd0;
assign BDCLed0_0_duty_led = 8'd8;
always @(led, sw, clk) begin: BDCLED_TBV_PRINT_DATA
$write("%h", sw);
$write(" ");
$write("%h", clk);
$write(" ");
$write("%h", led);
$write("\n");
end
always @(posedge clk) begin: BDCLED_TBV_BDCLED0_0_LOGIC
BDCLed0_0_counter <= (BDCLed0_0_counter + 1);
if ((BDCLed0_0_counter < BDCLed0_0_duty_led)) begin
led <= 15;
end
else begin
led <= 0;
end
end
initial begin: BDCLED_TBV_CLK_SIGNAL
while (1'b1) begin
clk <= (!clk);
# 1;
end
end
initial begin: BDCLED_TBV_STIMULES
integer i;
i = 0;
while (1'b1) begin
if ((i == 1000)) begin
$finish;
end
i = i + 1;
@(posedge clk);
end
end
endmodule |
module twelve_ios (sclk, // @negedge
pre_wen, // 1 cycle ahead of write data
di, // [15:0] data in
io_do, // [5:0] data to I/O pins
io_t, // [5:0] tristate I/O pins
da, // [5:0] data from port A (USB?)
da_en, // [5:0] data enable from port A (USB?)
db, // [5:0] data from port B
db_en, // [5:0] data enable from port B
dc, // [5:0] data from port C
dc_en); // [5:0] data enable from port C
input sclk;
input pre_wen;
input [15:0] di;
output [11:0] io_do;
output [11:0] io_t;
input [11:0] da;
input [11:0] da_en;
input [11:0] db;
input [11:0] db_en;
input [11:0] dc;
input [11:0] dc_en;
// wire [23:0] cr; // control register - reset at powerup
wire [11:0] ds; // "software" data (programmed by lower 24 bits)
wire [11:0] ds_en; // "software" data enable (programmed by lower 24 bits)
wire [ 3:0] ch_en; // channel enable
reg pre_wen_d;
reg cr_wen;
reg [31:0] did; // registered (dealyed by 1 clock) version of di[25:0]
wire [11:0] ds_en_m;
wire [11:0] da_en_m;
wire [11:0] db_en_m;
wire [11:0] dc_en_m;
assign dc_en_m[11:0]= dc_en[11:0] & {12{ch_en[3]}};
assign db_en_m[11:0]= db_en[11:0] & {12{ch_en[2]}} & ~dc_en_m[11:0];
assign da_en_m[11:0]= da_en[11:0] & {12{ch_en[1]}} & ~dc_en_m[11:0] & ~db_en_m[11:0];
assign ds_en_m[11:0]= ds_en[11:0] & {12{ch_en[0]}} & ~dc_en_m[11:0] & ~db_en_m[11:0] & ~da_en_m[11:0];
assign io_do[11:0]=(dc_en_m[11:0] & dc[11:0]) |
(db_en_m[11:0] & db[11:0]) |
(da_en_m[11:0] & da[11:0]) |
(ds_en_m[11:0] & ds[11:0]);
assign io_t[11:0]=~(dc_en_m[11:0] | db_en_m[11:0] | da_en_m[11:0] | ds_en_m[11:0]);
// 0 0 0 - no change -
// 0 1 1 1 0
// 1 0 2 1 1
// 1 1 3 0 0
FDE_1 i_ds_0 (.C(sclk), .CE(cr_wen & (did[ 0] | did[ 1])), .D( ~did[ 0] ), .Q(ds[ 0]));
FDE_1 i_ds_1 (.C(sclk), .CE(cr_wen & (did[ 2] | did[ 3])), .D( ~did[ 2] ), .Q(ds[ 1]));
FDE_1 i_ds_2 (.C(sclk), .CE(cr_wen & (did[ 4] | did[ 5])), .D( ~did[ 4] ), .Q(ds[ 2]));
FDE_1 i_ds_3 (.C(sclk), .CE(cr_wen & (did[ 6] | did[ 7])), .D( ~did[ 6] ), .Q(ds[ 3]));
FDE_1 i_ds_4 (.C(sclk), .CE(cr_wen & (did[ 8] | did[ 9])), .D( ~did[ 8] ), .Q(ds[ 4]));
FDE_1 i_ds_5 (.C(sclk), .CE(cr_wen & (did[10] | did[11])), .D( ~did[10] ), .Q(ds[ 5]));
FDE_1 i_ds_6 (.C(sclk), .CE(cr_wen & (did[12] | did[13])), .D( ~did[12] ), .Q(ds[ 6]));
FDE_1 i_ds_7 (.C(sclk), .CE(cr_wen & (did[14] | did[15])), .D( ~did[14] ), .Q(ds[ 7]));
FDE_1 i_ds_8 (.C(sclk), .CE(cr_wen & (did[16] | did[17])), .D( ~did[16] ), .Q(ds[ 8]));
FDE_1 i_ds_9 (.C(sclk), .CE(cr_wen & (did[18] | did[19])), .D( ~did[18] ), .Q(ds[ 9]));
FDE_1 i_ds_10 (.C(sclk), .CE(cr_wen & (did[20] | did[21])), .D( ~did[20] ), .Q(ds[10]));
FDE_1 i_ds_11 (.C(sclk), .CE(cr_wen & (did[22] | did[23])), .D( ~did[22] ), .Q(ds[11]));
FDE_1 i_ds_en_0 (.C(sclk), .CE(cr_wen & (did[ 0] | did[ 1])), .D(~(did[ 1] & did[ 0])), .Q(ds_en[ 0]));
FDE_1 i_ds_en_1 (.C(sclk), .CE(cr_wen & (did[ 2] | did[ 3])), .D(~(did[ 3] & did[ 2])), .Q(ds_en[ 1]));
FDE_1 i_ds_en_2 (.C(sclk), .CE(cr_wen & (did[ 4] | did[ 5])), .D(~(did[ 5] & did[ 4])), .Q(ds_en[ 2]));
FDE_1 i_ds_en_3 (.C(sclk), .CE(cr_wen & (did[ 6] | did[ 7])), .D(~(did[ 7] & did[ 6])), .Q(ds_en[ 3]));
FDE_1 i_ds_en_4 (.C(sclk), .CE(cr_wen & (did[ 8] | did[ 9])), .D(~(did[ 9] & did[ 8])), .Q(ds_en[ 4]));
FDE_1 i_ds_en_5 (.C(sclk), .CE(cr_wen & (did[10] | did[11])), .D(~(did[11] & did[10])), .Q(ds_en[ 5]));
FDE_1 i_ds_en_6 (.C(sclk), .CE(cr_wen & (did[12] | did[13])), .D(~(did[13] & did[12])), .Q(ds_en[ 6]));
FDE_1 i_ds_en_7 (.C(sclk), .CE(cr_wen & (did[14] | did[15])), .D(~(did[15] & did[14])), .Q(ds_en[ 7]));
FDE_1 i_ds_en_8 (.C(sclk), .CE(cr_wen & (did[16] | did[17])), .D(~(did[17] & did[16])), .Q(ds_en[ 8]));
FDE_1 i_ds_en_9 (.C(sclk), .CE(cr_wen & (did[18] | did[19])), .D(~(did[19] & did[18])), .Q(ds_en[ 9]));
FDE_1 i_ds_en_10 (.C(sclk), .CE(cr_wen & (did[20] | did[21])), .D(~(did[21] & did[20])), .Q(ds_en[10]));
FDE_1 i_ds_en_11 (.C(sclk), .CE(cr_wen & (did[22] | did[23])), .D(~(did[23] & did[22])), .Q(ds_en[11]));
FDE_1 #(.INIT(1'b1)) i_ch_en_0 (.C(sclk), .CE(cr_wen & did[25]), .D(did[24]), .Q(ch_en[ 0]));
FDE_1 #(.INIT(1'b0)) i_ch_en_1 (.C(sclk), .CE(cr_wen & did[27]), .D(did[26]), .Q(ch_en[ 1]));
FDE_1 #(.INIT(1'b0)) i_ch_en_2 (.C(sclk), .CE(cr_wen & did[29]), .D(did[28]), .Q(ch_en[ 2]));
FDE_1 #(.INIT(1'b0)) i_ch_en_3 (.C(sclk), .CE(cr_wen & did[31]), .D(did[30]), .Q(ch_en[ 3]));
always @ (negedge sclk) begin
pre_wen_d <= pre_wen;
cr_wen <=pre_wen_d;
if (pre_wen) did[15: 0] <= di[15:0];
if (pre_wen_d) did[31:16] <= di[15:0];
end
endmodule |
module SCB_P4_v3_20_0 (
interrupt,
clock,
rx_tr_out,
tx_tr_out,
s_mosi,
s_sclk,
s_ss,
m_miso,
m_mosi,
m_sclk,
m_ss0,
m_ss1,
m_ss2,
m_ss3,
s_miso,
rx_in,
cts_in,
tx_out,
rts_out);
output interrupt;
input clock;
output rx_tr_out;
output tx_tr_out;
input s_mosi;
input s_sclk;
input s_ss;
input m_miso;
output m_mosi;
output m_sclk;
output m_ss0;
output m_ss1;
output m_ss2;
output m_ss3;
output s_miso;
input rx_in;
input cts_in;
output tx_out;
output rts_out;
wire uncfg_rx_irq;
wire sclk_m_wire;
wire Net_1264;
wire Net_1258;
wire rx_irq;
wire [3:0] select_m_wire;
wire Net_1099;
wire Net_1090;
wire Net_467;
wire Net_1316;
wire Net_252;
wire Net_1089;
wire Net_1320;
wire Net_1257;
wire sclk_s_wire;
wire Net_1268;
wire Net_1297;
wire Net_547;
wire Net_1001;
wire mosi_s_wire;
wire rts_wire;
wire mosi_m_wire;
wire Net_891;
wire Net_1263;
wire miso_s_wire;
wire cts_wire;
wire Net_899;
wire tx_wire;
wire Net_1028;
wire rx_wire;
wire Net_916;
wire Net_1000;
wire scl_wire;
wire miso_m_wire;
wire Net_1172;
wire Net_1170;
wire select_s_wire;
wire sda_wire;
wire Net_847;
cy_clock_v1_0
#(.id("43ec2fa1-bf22-4b71-9477-b6ca7b97f0b0/2dc2d7a8-ce2b-43c7-af4a-821c8cd73ccf"),
.source_clock_id(""),
.divisor(0),
.period("7440476190.47619"),
.is_direct(0),
.is_digital(0))
SCBCLK
(.clock_out(Net_847));
// select_s_VM (cy_virtualmux_v1_0)
assign select_s_wire = s_ss;
// rx_VM (cy_virtualmux_v1_0)
assign rx_wire = Net_1172;
wire [0:0] tmpOE__rx_wake_net;
wire [0:0] tmpIO_0__rx_wake_net;
electrical [0:0] tmpSIOVREF__rx_wake_net;
cy_psoc3_pins_v1_10
#(.id("43ec2fa1-bf22-4b71-9477-b6ca7b97f0b0/e9408829-61ce-4f43-b0c1-855b87d0fbdc"),
.drive_mode(3'b001),
.ibuf_enabled(1'b1),
.init_dr_st(1'b0),
.input_clk_en(0),
.input_sync(1'b0),
.input_sync_mode(1'b0),
.intr_mode(2'b10),
.invert_in_clock(0),
.invert_in_clock_en(0),
.invert_in_reset(0),
.invert_out_clock(0),
.invert_out_clock_en(0),
.invert_out_reset(0),
.io_voltage(""),
.layout_mode("CONTIGUOUS"),
.oe_conn(1'b0),
.oe_reset(0),
.oe_sync(1'b0),
.output_clk_en(0),
.output_clock_mode(1'b0),
.output_conn(1'b0),
.output_mode(1'b0),
.output_reset(0),
.output_sync(1'b0),
.pa_in_clock(-1),
.pa_in_clock_en(-1),
.pa_in_reset(-1),
.pa_out_clock(-1),
.pa_out_clock_en(-1),
.pa_out_reset(-1),
.pin_aliases(""),
.pin_mode("I"),
.por_state(4),
.sio_group_cnt(0),
.sio_hyst(1'b1),
.sio_ibuf(""),
.sio_info(2'b00),
.sio_obuf(""),
.sio_refsel(""),
.sio_vtrip(""),
.sio_hifreq(""),
.sio_vohsel(""),
.slew_rate(1'b0),
.spanning(0),
.use_annotation(1'b0),
.vtrip(2'b00),
.width(1),
.ovt_hyst_trim(1'b0),
.ovt_needed(1'b0),
.ovt_slew_control(2'b00),
.input_buffer_sel(2'b00))
rx_wake
(.oe(tmpOE__rx_wake_net),
.y({1'b0}),
.fb({Net_1172}),
.io({tmpIO_0__rx_wake_net[0:0]}),
.siovref(tmpSIOVREF__rx_wake_net),
.interrupt({rx_irq}),
.in_clock({1'b0}),
.in_clock_en({1'b1}),
.in_reset({1'b0}),
.out_clock({1'b0}),
.out_clock_en({1'b1}),
.out_reset({1'b0}));
assign tmpOE__rx_wake_net = (`CYDEV_CHIP_MEMBER_USED == `CYDEV_CHIP_MEMBER_3A && `CYDEV_CHIP_REVISION_USED < `CYDEV_CHIP_REVISION_3A_ES3) ? ~{1'b1} : {1'b1};
// rx_wake_VM (cy_virtualmux_v1_0)
assign Net_1257 = rx_irq;
cy_isr_v1_0
#(.int_type(2'b10))
RX_WAKEUP_IRQ
(.int_signal(Net_1257));
// clock_VM (cy_virtualmux_v1_0)
assign Net_1170 = Net_847;
// sclk_s_VM (cy_virtualmux_v1_0)
assign sclk_s_wire = s_sclk;
// mosi_s_VM (cy_virtualmux_v1_0)
assign mosi_s_wire = s_mosi;
// miso_m_VM (cy_virtualmux_v1_0)
assign miso_m_wire = m_miso;
wire [0:0] tmpOE__tx_net;
wire [0:0] tmpFB_0__tx_net;
wire [0:0] tmpIO_0__tx_net;
wire [0:0] tmpINTERRUPT_0__tx_net;
electrical [0:0] tmpSIOVREF__tx_net;
cy_psoc3_pins_v1_10
#(.id("43ec2fa1-bf22-4b71-9477-b6ca7b97f0b0/23b8206d-1c77-4e61-be4a-b4037d5de5fc"),
.drive_mode(3'b110),
.ibuf_enabled(1'b0),
.init_dr_st(1'b1),
.input_clk_en(0),
.input_sync(1'b0),
.input_sync_mode(1'b0),
.intr_mode(2'b00),
.invert_in_clock(0),
.invert_in_clock_en(0),
.invert_in_reset(0),
.invert_out_clock(0),
.invert_out_clock_en(0),
.invert_out_reset(0),
.io_voltage(""),
.layout_mode("CONTIGUOUS"),
.oe_conn(1'b0),
.oe_reset(0),
.oe_sync(1'b0),
.output_clk_en(0),
.output_clock_mode(1'b0),
.output_conn(1'b1),
.output_mode(1'b0),
.output_reset(0),
.output_sync(1'b0),
.pa_in_clock(-1),
.pa_in_clock_en(-1),
.pa_in_reset(-1),
.pa_out_clock(-1),
.pa_out_clock_en(-1),
.pa_out_reset(-1),
.pin_aliases(""),
.pin_mode("B"),
.por_state(4),
.sio_group_cnt(0),
.sio_hyst(1'b1),
.sio_ibuf(""),
.sio_info(2'b00),
.sio_obuf(""),
.sio_refsel(""),
.sio_vtrip(""),
.sio_hifreq(""),
.sio_vohsel(""),
.slew_rate(1'b0),
.spanning(0),
.use_annotation(1'b0),
.vtrip(2'b00),
.width(1),
.ovt_hyst_trim(1'b0),
.ovt_needed(1'b0),
.ovt_slew_control(2'b00),
.input_buffer_sel(2'b00))
tx
(.oe(tmpOE__tx_net),
.y({tx_wire}),
.fb({tmpFB_0__tx_net[0:0]}),
.io({tmpIO_0__tx_net[0:0]}),
.siovref(tmpSIOVREF__tx_net),
.interrupt({tmpINTERRUPT_0__tx_net[0:0]}),
.in_clock({1'b0}),
.in_clock_en({1'b1}),
.in_reset({1'b0}),
.out_clock({1'b0}),
.out_clock_en({1'b1}),
.out_reset({1'b0}));
assign tmpOE__tx_net = (`CYDEV_CHIP_MEMBER_USED == `CYDEV_CHIP_MEMBER_3A && `CYDEV_CHIP_REVISION_USED < `CYDEV_CHIP_REVISION_3A_ES3) ? ~{1'b1} : {1'b1};
ZeroTerminal ZeroTerminal_7 (
.z(Net_1099));
assign Net_1258 = Net_847 | Net_1099;
// cts_VM (cy_virtualmux_v1_0)
assign cts_wire = cts_in;
cy_m0s8_scb_v2_0 SCB (
.rx(rx_wire),
.miso_m(miso_m_wire),
.select_m(select_m_wire[3:0]),
.sclk_m(sclk_m_wire),
.mosi_s(mosi_s_wire),
.select_s(select_s_wire),
.sclk_s(sclk_s_wire),
.mosi_m(mosi_m_wire),
.scl(scl_wire),
.sda(sda_wire),
.tx(tx_wire),
.miso_s(miso_s_wire),
.interrupt(interrupt),
.cts(cts_wire),
.rts(rts_wire),
.tx_req(tx_tr_out),
.rx_req(rx_tr_out),
.clock(Net_1170));
defparam SCB.scb_mode = 2;
// Device_VM4 (cy_virtualmux_v1_0)
assign uncfg_rx_irq = Net_1000;
assign m_mosi = mosi_m_wire;
assign m_sclk = sclk_m_wire;
assign m_ss0 = select_m_wire[0];
assign m_ss1 = select_m_wire[1];
assign m_ss2 = select_m_wire[2];
assign m_ss3 = select_m_wire[3];
assign s_miso = miso_s_wire;
assign tx_out = tx_wire;
assign rts_out = rts_wire;
endmodule |
module top ;
wire Net_3491;
wire Net_3490;
wire Net_3489;
wire Net_3488;
wire Net_3487;
wire Net_3486;
wire Net_3485;
wire Net_3484;
wire Net_3483;
wire Net_3482;
wire Net_3481;
wire Net_3480;
wire Net_3479;
wire Net_3478;
wire Net_3477;
wire Net_3476;
wire Net_3475;
wire Net_3474;
wire Net_3473;
wire Net_3450;
wire [0:0] tmpOE__LED_G_net;
wire [0:0] tmpFB_0__LED_G_net;
wire [0:0] tmpIO_0__LED_G_net;
wire [0:0] tmpINTERRUPT_0__LED_G_net;
electrical [0:0] tmpSIOVREF__LED_G_net;
cy_psoc3_pins_v1_10
#(.id("e851a3b9-efb8-48be-bbb8-b303b216c393"),
.drive_mode(3'b110),
.ibuf_enabled(1'b1),
.init_dr_st(1'b1),
.input_clk_en(0),
.input_sync(1'b1),
.input_sync_mode(1'b0),
.intr_mode(2'b00),
.invert_in_clock(0),
.invert_in_clock_en(0),
.invert_in_reset(0),
.invert_out_clock(0),
.invert_out_clock_en(0),
.invert_out_reset(0),
.io_voltage(""),
.layout_mode("CONTIGUOUS"),
.oe_conn(1'b0),
.oe_reset(0),
.oe_sync(1'b0),
.output_clk_en(0),
.output_clock_mode(1'b0),
.output_conn(1'b0),
.output_mode(1'b0),
.output_reset(0),
.output_sync(1'b0),
.pa_in_clock(-1),
.pa_in_clock_en(-1),
.pa_in_reset(-1),
.pa_out_clock(-1),
.pa_out_clock_en(-1),
.pa_out_reset(-1),
.pin_aliases(""),
.pin_mode("O"),
.por_state(4),
.sio_group_cnt(0),
.sio_hyst(1'b1),
.sio_ibuf(""),
.sio_info(2'b00),
.sio_obuf(""),
.sio_refsel(""),
.sio_vtrip(""),
.sio_hifreq(""),
.sio_vohsel(""),
.slew_rate(1'b0),
.spanning(0),
.use_annotation(1'b0),
.vtrip(2'b10),
.width(1),
.ovt_hyst_trim(1'b0),
.ovt_needed(1'b0),
.ovt_slew_control(2'b00),
.input_buffer_sel(2'b00))
LED_G
(.oe(tmpOE__LED_G_net),
.y({1'b0}),
.fb({tmpFB_0__LED_G_net[0:0]}),
.io({tmpIO_0__LED_G_net[0:0]}),
.siovref(tmpSIOVREF__LED_G_net),
.interrupt({tmpINTERRUPT_0__LED_G_net[0:0]}),
.in_clock({1'b0}),
.in_clock_en({1'b1}),
.in_reset({1'b0}),
.out_clock({1'b0}),
.out_clock_en({1'b1}),
.out_reset({1'b0}));
assign tmpOE__LED_G_net = (`CYDEV_CHIP_MEMBER_USED == `CYDEV_CHIP_MEMBER_3A && `CYDEV_CHIP_REVISION_USED < `CYDEV_CHIP_REVISION_3A_ES3) ? ~{1'b1} : {1'b1};
wire [0:0] tmpOE__LED_R_net;
wire [0:0] tmpFB_0__LED_R_net;
wire [0:0] tmpIO_0__LED_R_net;
wire [0:0] tmpINTERRUPT_0__LED_R_net;
electrical [0:0] tmpSIOVREF__LED_R_net;
cy_psoc3_pins_v1_10
#(.id("46bcb939-fabe-42b9-90af-3e1c6577dc70"),
.drive_mode(3'b110),
.ibuf_enabled(1'b1),
.init_dr_st(1'b1),
.input_clk_en(0),
.input_sync(1'b1),
.input_sync_mode(1'b0),
.intr_mode(2'b00),
.invert_in_clock(0),
.invert_in_clock_en(0),
.invert_in_reset(0),
.invert_out_clock(0),
.invert_out_clock_en(0),
.invert_out_reset(0),
.io_voltage(""),
.layout_mode("CONTIGUOUS"),
.oe_conn(1'b0),
.oe_reset(0),
.oe_sync(1'b0),
.output_clk_en(0),
.output_clock_mode(1'b0),
.output_conn(1'b0),
.output_mode(1'b0),
.output_reset(0),
.output_sync(1'b0),
.pa_in_clock(-1),
.pa_in_clock_en(-1),
.pa_in_reset(-1),
.pa_out_clock(-1),
.pa_out_clock_en(-1),
.pa_out_reset(-1),
.pin_aliases(""),
.pin_mode("O"),
.por_state(4),
.sio_group_cnt(0),
.sio_hyst(1'b1),
.sio_ibuf(""),
.sio_info(2'b00),
.sio_obuf(""),
.sio_refsel(""),
.sio_vtrip(""),
.sio_hifreq(""),
.sio_vohsel(""),
.slew_rate(1'b0),
.spanning(0),
.use_annotation(1'b0),
.vtrip(2'b10),
.width(1),
.ovt_hyst_trim(1'b0),
.ovt_needed(1'b0),
.ovt_slew_control(2'b00),
.input_buffer_sel(2'b00))
LED_R
(.oe(tmpOE__LED_R_net),
.y({1'b0}),
.fb({tmpFB_0__LED_R_net[0:0]}),
.io({tmpIO_0__LED_R_net[0:0]}),
.siovref(tmpSIOVREF__LED_R_net),
.interrupt({tmpINTERRUPT_0__LED_R_net[0:0]}),
.in_clock({1'b0}),
.in_clock_en({1'b1}),
.in_reset({1'b0}),
.out_clock({1'b0}),
.out_clock_en({1'b1}),
.out_reset({1'b0}));
assign tmpOE__LED_R_net = (`CYDEV_CHIP_MEMBER_USED == `CYDEV_CHIP_MEMBER_3A && `CYDEV_CHIP_REVISION_USED < `CYDEV_CHIP_REVISION_3A_ES3) ? ~{1'b1} : {1'b1};
cy_isr_v1_0
#(.int_type(2'b10))
WDT_isr
(.int_signal(Net_3450));
cy_gsref_v1_0
#(.guid("1563FAA8-0748-4a1c-9785-CED309984BE3"))
WDT
(.sig_out(Net_3450));
SCB_P4_v3_20_0 UART (
.cts_in(1'b0),
.tx_out(Net_3474),
.rts_out(Net_3475),
.interrupt(Net_3476),
.clock(1'b0),
.rx_tr_out(Net_3478),
.tx_tr_out(Net_3479),
.s_mosi(1'b0),
.s_sclk(1'b0),
.s_ss(1'b0),
.m_miso(1'b0),
.m_mosi(Net_3484),
.m_sclk(Net_3485),
.m_ss0(Net_3486),
.m_ss1(Net_3487),
.m_ss2(Net_3488),
.m_ss3(Net_3489),
.s_miso(Net_3490),
.rx_in(1'b0));
wire [0:0] tmpOE__LED_B_net;
wire [0:0] tmpFB_0__LED_B_net;
wire [0:0] tmpIO_0__LED_B_net;
wire [0:0] tmpINTERRUPT_0__LED_B_net;
electrical [0:0] tmpSIOVREF__LED_B_net;
cy_psoc3_pins_v1_10
#(.id("3b8d3c3c-27ec-4327-b3ef-9251ee2d52b4"),
.drive_mode(3'b110),
.ibuf_enabled(1'b1),
.init_dr_st(1'b1),
.input_clk_en(0),
.input_sync(1'b1),
.input_sync_mode(1'b0),
.intr_mode(2'b00),
.invert_in_clock(0),
.invert_in_clock_en(0),
.invert_in_reset(0),
.invert_out_clock(0),
.invert_out_clock_en(0),
.invert_out_reset(0),
.io_voltage(""),
.layout_mode("CONTIGUOUS"),
.oe_conn(1'b0),
.oe_reset(0),
.oe_sync(1'b0),
.output_clk_en(0),
.output_clock_mode(1'b0),
.output_conn(1'b0),
.output_mode(1'b0),
.output_reset(0),
.output_sync(1'b0),
.pa_in_clock(-1),
.pa_in_clock_en(-1),
.pa_in_reset(-1),
.pa_out_clock(-1),
.pa_out_clock_en(-1),
.pa_out_reset(-1),
.pin_aliases(""),
.pin_mode("O"),
.por_state(4),
.sio_group_cnt(0),
.sio_hyst(1'b1),
.sio_ibuf(""),
.sio_info(2'b00),
.sio_obuf(""),
.sio_refsel(""),
.sio_vtrip(""),
.sio_hifreq(""),
.sio_vohsel(""),
.slew_rate(1'b0),
.spanning(0),
.use_annotation(1'b0),
.vtrip(2'b10),
.width(1),
.ovt_hyst_trim(1'b0),
.ovt_needed(1'b0),
.ovt_slew_control(2'b00),
.input_buffer_sel(2'b00))
LED_B
(.oe(tmpOE__LED_B_net),
.y({1'b0}),
.fb({tmpFB_0__LED_B_net[0:0]}),
.io({tmpIO_0__LED_B_net[0:0]}),
.siovref(tmpSIOVREF__LED_B_net),
.interrupt({tmpINTERRUPT_0__LED_B_net[0:0]}),
.in_clock({1'b0}),
.in_clock_en({1'b1}),
.in_reset({1'b0}),
.out_clock({1'b0}),
.out_clock_en({1'b1}),
.out_reset({1'b0}));
assign tmpOE__LED_B_net = (`CYDEV_CHIP_MEMBER_USED == `CYDEV_CHIP_MEMBER_3A && `CYDEV_CHIP_REVISION_USED < `CYDEV_CHIP_REVISION_3A_ES3) ? ~{1'b1} : {1'b1};
cy_isr_v1_0
#(.int_type(2'b10))
UART_isr
(.int_signal(Net_3476));
endmodule |
module sky130_fd_sc_lp__decapkapwr ();
// Module supplies
supply1 KAPWR;
supply1 VPWR ;
supply0 VGND ;
supply1 VPB ;
supply0 VNB ;
// No contents.
endmodule |
module Altera_UP_I2C (
// Inputs
clk,
reset,
clear_ack,
clk_400KHz,
start_and_stop_en,
change_output_bit_en,
send_start_bit,
send_stop_bit,
data_in,
transfer_data,
read_byte,
num_bits_to_transfer,
// Bidirectionals
i2c_sdata,
// Outputs
i2c_sclk,
i2c_scen,
enable_clk,
ack,
data_from_i2c,
transfer_complete
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
parameter I2C_BUS_MODE = 1'b0;
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input clk;
input reset;
input clear_ack;
input clk_400KHz;
input start_and_stop_en;
input change_output_bit_en;
input send_start_bit;
input send_stop_bit;
input [7:0] data_in;
input transfer_data;
input read_byte;
input [2:0] num_bits_to_transfer;
// Bidirectionals
inout i2c_sdata; // I2C Data
// Outputs
output i2c_sclk; // I2C Clock
output reg i2c_scen;
output enable_clk;
output reg ack;
output reg [7:0] data_from_i2c;
output transfer_complete;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
// states
localparam I2C_STATE_0_IDLE = 3'h0,
I2C_STATE_1_PRE_START = 3'h1,
I2C_STATE_2_START_BIT = 3'h2,
I2C_STATE_3_TRANSFER_BYTE = 3'h3,
I2C_STATE_4_TRANSFER_ACK = 3'h4,
I2C_STATE_5_STOP_BIT = 3'h5,
I2C_STATE_6_COMPLETE = 3'h6;
/*****************************************************************************
* Internal wires and registers Declarations *
*****************************************************************************/
// Internal Wires
// Internal Registers
reg [2:0] current_bit;
reg [7:0] current_byte;
// State Machine Registers
reg [2:0] ns_i2c_transceiver;
reg [2:0] s_i2c_transceiver;
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
always @(posedge clk)
begin
if (reset == 1'b1)
s_i2c_transceiver <= I2C_STATE_0_IDLE;
else
s_i2c_transceiver <= ns_i2c_transceiver;
end
always @(*)
begin
// Defaults
ns_i2c_transceiver = I2C_STATE_0_IDLE;
case (s_i2c_transceiver)
I2C_STATE_0_IDLE:
begin
if ((send_start_bit == 1'b1) && (clk_400KHz == 1'b0))
ns_i2c_transceiver = I2C_STATE_1_PRE_START;
else if (send_start_bit == 1'b1)
ns_i2c_transceiver = I2C_STATE_2_START_BIT;
else if (send_stop_bit == 1'b1)
ns_i2c_transceiver = I2C_STATE_5_STOP_BIT;
else if (transfer_data == 1'b1)
ns_i2c_transceiver = I2C_STATE_3_TRANSFER_BYTE;
else
ns_i2c_transceiver = I2C_STATE_0_IDLE;
end
I2C_STATE_1_PRE_START:
begin
if (start_and_stop_en == 1'b1)
ns_i2c_transceiver = I2C_STATE_2_START_BIT;
else
ns_i2c_transceiver = I2C_STATE_1_PRE_START;
end
I2C_STATE_2_START_BIT:
begin
if (change_output_bit_en == 1'b1)
begin
if ((transfer_data == 1'b1) && (I2C_BUS_MODE == 1'b0))
ns_i2c_transceiver = I2C_STATE_3_TRANSFER_BYTE;
else
ns_i2c_transceiver = I2C_STATE_6_COMPLETE;
end
else
ns_i2c_transceiver = I2C_STATE_2_START_BIT;
end
I2C_STATE_3_TRANSFER_BYTE:
begin
if ((current_bit == 3'h0) && (change_output_bit_en == 1'b1))
begin
if ((I2C_BUS_MODE == 1'b0) || (num_bits_to_transfer == 3'h6))
ns_i2c_transceiver = I2C_STATE_4_TRANSFER_ACK;
else
ns_i2c_transceiver = I2C_STATE_6_COMPLETE;
end
else
ns_i2c_transceiver = I2C_STATE_3_TRANSFER_BYTE;
end
I2C_STATE_4_TRANSFER_ACK:
begin
if (change_output_bit_en == 1'b1)
ns_i2c_transceiver = I2C_STATE_6_COMPLETE;
else
ns_i2c_transceiver = I2C_STATE_4_TRANSFER_ACK;
end
I2C_STATE_5_STOP_BIT:
begin
if (start_and_stop_en == 1'b1)
ns_i2c_transceiver = I2C_STATE_6_COMPLETE;
else
ns_i2c_transceiver = I2C_STATE_5_STOP_BIT;
end
I2C_STATE_6_COMPLETE:
begin
if (transfer_data == 1'b0)
ns_i2c_transceiver = I2C_STATE_0_IDLE;
else
ns_i2c_transceiver = I2C_STATE_6_COMPLETE;
end
default:
begin
ns_i2c_transceiver = I2C_STATE_0_IDLE;
end
endcase
end
/*****************************************************************************
* Sequential logic *
*****************************************************************************/
// Output Registers
always @(posedge clk)
begin
if (reset == 1'b1)
i2c_scen <= 1'b1;
else if (change_output_bit_en & (s_i2c_transceiver == I2C_STATE_2_START_BIT))
i2c_scen <= 1'b0;
else if (s_i2c_transceiver == I2C_STATE_5_STOP_BIT)
i2c_scen <= 1'b1;
end
always @(posedge clk)
begin
if (reset == 1'b1)
ack <= 1'b0;
else if (clear_ack == 1'b1)
ack <= 1'b0;
else if (start_and_stop_en & (s_i2c_transceiver == I2C_STATE_4_TRANSFER_ACK))
ack <= i2c_sdata ^ I2C_BUS_MODE;
end
always @(posedge clk)
begin
if (reset == 1'b1)
data_from_i2c <= 8'h00;
else if (start_and_stop_en & (s_i2c_transceiver == I2C_STATE_3_TRANSFER_BYTE))
data_from_i2c <= {data_from_i2c[6:0], i2c_sdata};
end
// Internal Registers
always @(posedge clk)
begin
if (reset == 1'b1)
current_bit <= 3'h0;
else if ((s_i2c_transceiver == I2C_STATE_3_TRANSFER_BYTE) &&
(change_output_bit_en == 1'b1))
current_bit <= current_bit - 3'h1;
else if (s_i2c_transceiver != I2C_STATE_3_TRANSFER_BYTE)
current_bit <= num_bits_to_transfer;
end
always @(posedge clk)
begin
if (reset == 1'b1)
current_byte <= 8'h00;
else if ((s_i2c_transceiver == I2C_STATE_0_IDLE) ||
(s_i2c_transceiver == I2C_STATE_2_START_BIT))
current_byte <= data_in;
end
/*****************************************************************************
* Combinational logic *
*****************************************************************************/
assign i2c_sclk = (I2C_BUS_MODE == 1'b0) ?
clk_400KHz :
((s_i2c_transceiver == I2C_STATE_3_TRANSFER_BYTE) |
(s_i2c_transceiver == I2C_STATE_4_TRANSFER_ACK)) ?
clk_400KHz :
1'b0;
assign i2c_sdata =
(s_i2c_transceiver == I2C_STATE_2_START_BIT) ? 1'b0 :
(s_i2c_transceiver == I2C_STATE_5_STOP_BIT) ? 1'b0 :
((s_i2c_transceiver == I2C_STATE_4_TRANSFER_ACK) & read_byte) ? 1'b0 :
((s_i2c_transceiver == I2C_STATE_3_TRANSFER_BYTE) & ~read_byte) ?
current_byte[current_bit]
: 1'bz;
assign enable_clk = ~(s_i2c_transceiver == I2C_STATE_0_IDLE) &&
~(s_i2c_transceiver == I2C_STATE_6_COMPLETE);
assign transfer_complete =
(s_i2c_transceiver == I2C_STATE_6_COMPLETE) ? 1'b1 : 1'b0;
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
endmodule |
module xor3(input a ,input b,input c,output x);
assign x=a^b^c;
endmodule |
module alu2(input wire [31:0] srca,input wire [31:0]srcb,
input wire [1:0] alucontrol,
output reg[31:0] aluresult,output reg[3:0]aluflags);
reg [31:0]sum;
reg cout;
wire [31:0]srcbc=~srcb;
wire xa;
xor3 aa(alucontrol[0],srca[31],srca[31],xa);
always@(*)
begin
if(alucontrol[0]) {cout,sum}=srca+srcbc+1;
else {cout,sum}=srca+srcb;
case (alucontrol)
2'b00: aluresult=sum;
2'b01: aluresult=sum;
2'b10: aluresult=srca & srcb;
2'b11: aluresult=srca | srcb;
endcase
aluflags[3:2]={aluresult[31],aluresult==0}; //n,z flags
aluflags[1]= cout & ~alucontrol[1]; //carry out flag c
aluflags[0]= xa & (~alucontrol[1] & (aluresult[31] ^ srca[31]) ); //overflow flag v
end
endmodule |
module alu2(input wire [31:0] srca,input wire [31:0]srcb,
input wire [1:0] alucontrol,
output reg[31:0] aluresult,output wire[3:0]aluflags);
reg [31:0]sum;
reg cout;
wire [31:0]srcbc=~srcb;
always@(*) begin
if(alucontrol[0]) {cout,sum}=srca+srcbc+1;
else {cout,sum}=srca+srcb;
case (alucontrol)
2'b00: aluresult=sum;
2'b01: aluresult=sum;
2'b10: aluresult=srca & srcb;
2'b11: aluresult=srca | srcb;
endcase
end
assign aluflags[3:2]={aluresult[31],aluresult==0}; //n,z flags
assign aluflags[1]= cout & ~alucontrol[1]; //carry out flag c
assign aluflags[0]= (~(alucontrol[0]^srca[31]^srca[31])) & (~alucontrol[1]) & (aluresult[31] ^ srca[31]) ; //overflow flag v
endmodule |
module async_ram_1port
#(parameter Width = 64, Size=128)
( input [`log2(Size)-1:0] p0_pos
,input p0_enable
,input [Width-1:0] p0_in_data
,output reg [Width-1:0] p0_out_data
);
reg [Width-1:0] data [Size-1:0]; // synthesis syn_ramstyle = "block_ram"
reg [Width-1:0] d0;
always_comb begin
if (p0_enable) begin
d0 = 'b0;
end else begin
d0 = data[p0_pos];
end
end
always @(p0_pos or p0_in_data or p0_enable) begin
if (p0_enable) begin
data[p0_pos] = p0_in_data;
end
end
always_comb begin
p0_out_data = d0;
end
endmodule |
module sky130_fd_sc_ls__o21bai (
Y ,
A1 ,
A2 ,
B1_N,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1_N;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule |
module note2dds(CLK, NOTE, ADDER);
input wire CLK;
input wire [6:0] NOTE;
output [31:0] ADDER;
reg [31:0] ADDER_tbl [15:0];
reg [3:0] addr;
reg [3:0] divider;
// note div 12 ( * 0,08333333333333333333333333333333)
//; Add input / 16 to accumulator
//; Add input / 64 to accumulator
initial begin
addr <= 4'd0;
divider <= 4'd0;
ADDER_tbl[ 4'd0] <= 32'd0359575;
ADDER_tbl[ 4'd1] <= 32'd0380957;
ADDER_tbl[ 4'd2] <= 32'd0403610;
ADDER_tbl[ 4'd3] <= 32'd0427610;
ADDER_tbl[ 4'd4] <= 32'd0453037;
ADDER_tbl[ 4'd5] <= 32'd0479976;
ADDER_tbl[ 4'd6] <= 32'd0508516;
ADDER_tbl[ 4'd7] <= 32'd0538754;
ADDER_tbl[ 4'd8] <= 32'd0570790;
ADDER_tbl[ 4'd9] <= 32'd0604731;
ADDER_tbl[4'd10] <= 32'd0640691;
ADDER_tbl[4'd11] <= 32'd0678788;
ADDER_tbl[4'd12] <= 32'd0;
ADDER_tbl[4'd13] <= 32'd0;
ADDER_tbl[4'd14] <= 32'd0;
ADDER_tbl[4'd15] <= 32'd0;
end
assign ADDER = ADDER_tbl[addr] >> divider;
wire [3:0] diap = (NOTE < 12) ? 4'd00 :
(NOTE < 24) ? 4'd01 :
(NOTE < 36) ? 4'd02 :
(NOTE < 48) ? 4'd03 :
(NOTE < 60) ? 4'd04 :
(NOTE < 72) ? 4'd05 :
(NOTE < 84) ? 4'd06 :
(NOTE < 96) ? 4'd07 :
(NOTE < 108) ? 4'd08 :
(NOTE < 120) ? 4'd09 : 4'd010 ;
wire [6:0] c_addr = NOTE - (diap * 4'd012);
always @ (posedge CLK) begin
addr <= c_addr[3:0];
divider <= 4'd010 - diap;
end
endmodule |
module bw_r_rf16x32 (/*AUTOARG*/
// Outputs
dout, so,
// Inputs
rclk, se, si, reset_l, sehold, rst_tri_en, rd_adr1, rd_adr2,
rd_adr1_sel, rd_en, wr_adr, wr_en, bit_wen, din
);
input rclk;
input se;
input si;
input reset_l;
input sehold; // scan enable hold
input rst_tri_en;
// 11:5(I);10:4(D)
input [6:0] rd_adr1 ; // rd address-1
input [6:0] rd_adr2 ; // rd address-2
input rd_adr1_sel ; // sel rd addr 1
input rd_en ; // rd enable
// 11:7(I);10:6(D)
input [6:2] wr_adr ; // wr address
input wr_en ; // wr enable
input [15:0] bit_wen ; // write enable with bit select
input din ; // write data
output [3:0] dout ; // valid bits for tag compare
output so;
wire clk;
assign clk = rclk;
//----------------------------------------------------------------------
// Declarations
//----------------------------------------------------------------------
// local signals
wire [6:0] rd_index ;
// 512 bit array
`ifdef FPGA_SYN_IDCT
reg [31:0] idcv_ary_0000;
reg [31:0] idcv_ary_0001;
reg [31:0] idcv_ary_0010;
reg [31:0] idcv_ary_0011;
reg [31:0] idcv_ary_0100;
reg [31:0] idcv_ary_0101;
reg [31:0] idcv_ary_0110;
reg [31:0] idcv_ary_0111;
reg [31:0] idcv_ary_1000;
reg [31:0] idcv_ary_1001;
reg [31:0] idcv_ary_1010;
reg [31:0] idcv_ary_1011;
reg [31:0] idcv_ary_1100;
reg [31:0] idcv_ary_1101;
reg [31:0] idcv_ary_1110;
reg [31:0] idcv_ary_1111;
`else
reg [511:0] idcv_ary;
`endif
reg [3:0] vbit,
vbit_sa;
reg [6:2] wr_index_d1;
reg [6:0] rd_index_d1;
reg rdreq_d1,
wrreq_d1;
reg [15:0] bit_wen_d1;
reg din_d1;
reg [4:0] index;
wire rst_all;
//----------------------------------------------------------------------
// Code Begins Here
//----------------------------------------------------------------------
assign rst_all = rst_tri_en | ~reset_l;
// mux merged with flop on index
assign rd_index = rd_adr1_sel ? rd_adr1:rd_adr2 ;
// input flops
always @ (posedge clk)
begin
if (~sehold)
begin
rdreq_d1 <= rd_en ;
wrreq_d1 <= wr_en ;
rd_index_d1 <= rd_index;
wr_index_d1 <= wr_adr;
bit_wen_d1 <= bit_wen;
din_d1 <= din;
end
end
//----------------------------------------------------------------------
// Read Operation
//----------------------------------------------------------------------
`ifdef FPGA_SYN_IDCT
always @(/*AUTOSENSE*/
idcv_ary_0000 or idcv_ary_0001 or idcv_ary_0010 or idcv_ary_0011 or
idcv_ary_0100 or idcv_ary_1001 or idcv_ary_1010 or idcv_ary_0111 or
idcv_ary_1000 or idcv_ary_0101 or idcv_ary_0110 or idcv_ary_1011 or
idcv_ary_1100 or idcv_ary_1101 or idcv_ary_1110 or idcv_ary_1111 or rd_index_d1 or rdreq_d1)
`else
always @(/*AUTOSENSE*/idcv_ary or rd_index_d1 or rdreq_d1)
`endif
begin
if (rdreq_d1) // should work even if there is read
// write conflict. Data can be latest
// or previous but should not be x
begin
`ifdef FPGA_SYN_IDCT
case(rd_index_d1[1:0])
2'b00: begin
vbit[0] = idcv_ary_0000[{rd_index_d1[6:2]}];
vbit[1] = idcv_ary_0001[{rd_index_d1[6:2]}];
vbit[2] = idcv_ary_0010[{rd_index_d1[6:2]}];
vbit[3] = idcv_ary_0011[{rd_index_d1[6:2]}];
end
2'b01: begin
vbit[0] = idcv_ary_0100[{rd_index_d1[6:2]}];
vbit[1] = idcv_ary_0101[{rd_index_d1[6:2]}];
vbit[2] = idcv_ary_0110[{rd_index_d1[6:2]}];
vbit[3] = idcv_ary_0111[{rd_index_d1[6:2]}];
end
2'b10: begin
vbit[0] = idcv_ary_1000[{rd_index_d1[6:2]}];
vbit[1] = idcv_ary_1001[{rd_index_d1[6:2]}];
vbit[2] = idcv_ary_1010[{rd_index_d1[6:2]}];
vbit[3] = idcv_ary_1011[{rd_index_d1[6:2]}];
end
2'b11: begin
vbit[0] = idcv_ary_1100[{rd_index_d1[6:2]}];
vbit[1] = idcv_ary_1101[{rd_index_d1[6:2]}];
vbit[2] = idcv_ary_1110[{rd_index_d1[6:2]}];
vbit[3] = idcv_ary_1111[{rd_index_d1[6:2]}];
end
endcase
`else
vbit[0] = idcv_ary[{rd_index_d1, 2'b00}]; // way 0
vbit[1] = idcv_ary[{rd_index_d1, 2'b01}]; // way 1
vbit[2] = idcv_ary[{rd_index_d1, 2'b10}]; // way 2
vbit[3] = idcv_ary[{rd_index_d1, 2'b11}]; // way 3
`endif
end // if (rdreq_d1)
else // i/dcache disabled or rd disabled
begin
vbit[3:0] = 4'bx;
end // else: !if(rdreq_d1)
end // always @ (...
// r-w conflict case, returns old_data & new_data
// 12/06 modified to be
// 0 0 0
// 0 1 X
// 1 0 0
// 1 1 1
`ifdef FPGA_SYN_IDCT
initial
begin
for(index = 5'h0; index < 5'h1f; index = index+1)
begin
idcv_ary_0000[index] = 1'b0;
idcv_ary_0001[index] = 1'b0;
idcv_ary_0010[index] = 1'b0;
idcv_ary_0011[index] = 1'b0;
idcv_ary_0100[index] = 1'b0;
idcv_ary_0101[index] = 1'b0;
idcv_ary_0110[index] = 1'b0;
idcv_ary_0111[index] = 1'b0;
idcv_ary_1000[index] = 1'b0;
idcv_ary_1001[index] = 1'b0;
idcv_ary_1010[index] = 1'b0;
idcv_ary_1011[index] = 1'b0;
idcv_ary_1100[index] = 1'b0;
idcv_ary_1101[index] = 1'b0;
idcv_ary_1110[index] = 1'b0;
idcv_ary_1111[index] = 1'b0;
end
end
`endif
reg [3:0] wr_data;
always @ (/*AUTOSENSE*/bit_wen_d1 or rd_index_d1 or rst_all
or wr_index_d1 or wrreq_d1)
begin
if (rd_index_d1[6:2] == wr_index_d1[6:2])
case (rd_index_d1[1:0])
2'b00: wr_data = bit_wen_d1[3:0] & {4{wrreq_d1 & ~rst_all}};
2'b01: wr_data = bit_wen_d1[7:4] & {4{wrreq_d1 & ~rst_all}};
2'b10: wr_data = bit_wen_d1[11:8] & {4{wrreq_d1 & ~rst_all}};
default: wr_data = bit_wen_d1[15:12] & {4{wrreq_d1 & ~rst_all}};
endcase // case(rd_index_d1[1:0])
else
wr_data = 4'b0;
end
`ifdef FPGA_SYN_IDCT
assign dout[3:0] = (~reset_l | ~rdreq_d1) ? 4'b0000 :
(~wr_data & vbit | wr_data & {4{din_d1}} & vbit);
`else
// SA latch -- to make 0in happy
always @ (/*AUTOSENSE*/clk or din_d1 or vbit or wr_data)
begin
if (clk)
begin
vbit_sa <= (~wr_data & vbit |
wr_data & {4{din_d1}} & (vbit | 4'bxxxx));
end
end
// bug:2776 - remove holding the last read value
// reset_l rdreq_d1 dout
// 0 - 0
// 1 0 0
// 1 1 vbit_sa
assign dout[3:0] = (~reset_l | ~rdreq_d1) ? 4'b0000 : vbit_sa[3:0] ;
`endif
//----------------------------------------------------------------------
// Write Operation
//----------------------------------------------------------------------
// Invalidate/Write occurs on 16B boundary.
// For this purpose, 4x4 write-enables are required.
// Index thus corresponds to 11:7,6:5,w[1:0], where w=way (ICache)
// Index thus corresponds to 10:6,5:4,w[1:0], where w=way (DCache)
// Thru data-in, vld bit can be set or cleared.
always @ (negedge clk)
begin
if (wrreq_d1 & ~rst_all) // should work even if rd-wr conflict
begin
// line 0 (5:4=00)
`ifdef FPGA_SYN_IDCT
if (bit_wen_d1[0]) idcv_ary_0000[{wr_index_d1[6:2]}] = din_d1;
if (bit_wen_d1[1]) idcv_ary_0001[{wr_index_d1[6:2]}] = din_d1;
if (bit_wen_d1[2]) idcv_ary_0010[{wr_index_d1[6:2]}] = din_d1;
if (bit_wen_d1[3]) idcv_ary_0011[{wr_index_d1[6:2]}] = din_d1;
`else
if (bit_wen_d1[0])
idcv_ary[{wr_index_d1[6:2],2'b00,2'b00}] = din_d1;
if (bit_wen_d1[1])
idcv_ary[{wr_index_d1[6:2],2'b00,2'b01}] = din_d1;
if (bit_wen_d1[2])
idcv_ary[{wr_index_d1[6:2],2'b00,2'b10}] = din_d1;
if (bit_wen_d1[3])
idcv_ary[{wr_index_d1[6:2],2'b00,2'b11}] = din_d1;
`endif
// line 1 (5:4=01)
`ifdef FPGA_SYN_IDCT
if (bit_wen_d1[4]) idcv_ary_0100[{wr_index_d1[6:2]}] = din_d1;
if (bit_wen_d1[5]) idcv_ary_0101[{wr_index_d1[6:2]}] = din_d1;
if (bit_wen_d1[6]) idcv_ary_0110[{wr_index_d1[6:2]}] = din_d1;
if (bit_wen_d1[7]) idcv_ary_0111[{wr_index_d1[6:2]}] = din_d1;
`else
if (bit_wen_d1[4])
idcv_ary[{wr_index_d1[6:2],2'b01,2'b00}] = din_d1;
if (bit_wen_d1[5])
idcv_ary[{wr_index_d1[6:2],2'b01,2'b01}] = din_d1;
if (bit_wen_d1[6])
idcv_ary[{wr_index_d1[6:2],2'b01,2'b10}] = din_d1;
if (bit_wen_d1[7])
idcv_ary[{wr_index_d1[6:2],2'b01,2'b11}] = din_d1;
`endif
// line 2 (5:4=10)
`ifdef FPGA_SYN_IDCT
if (bit_wen_d1[8]) idcv_ary_1000[{wr_index_d1[6:2]}] = din_d1;
if (bit_wen_d1[9]) idcv_ary_1001[{wr_index_d1[6:2]}] = din_d1;
if (bit_wen_d1[10]) idcv_ary_1010[{wr_index_d1[6:2]}] = din_d1;
if (bit_wen_d1[11]) idcv_ary_1011[{wr_index_d1[6:2]}] = din_d1;
`else
if (bit_wen_d1[8])
idcv_ary[{wr_index_d1[6:2],2'b10,2'b00}] = din_d1;
if (bit_wen_d1[9])
idcv_ary[{wr_index_d1[6:2],2'b10,2'b01}] = din_d1;
if (bit_wen_d1[10])
idcv_ary[{wr_index_d1[6:2],2'b10,2'b10}] = din_d1;
if (bit_wen_d1[11])
idcv_ary[{wr_index_d1[6:2],2'b10,2'b11}] = din_d1;
`endif
// line 3 (5:4=11)
`ifdef FPGA_SYN_IDCT
if (bit_wen_d1[12]) idcv_ary_1100[{wr_index_d1[6:2]}] = din_d1;
if (bit_wen_d1[13]) idcv_ary_1101[{wr_index_d1[6:2]}] = din_d1;
if (bit_wen_d1[14]) idcv_ary_1110[{wr_index_d1[6:2]}] = din_d1;
if (bit_wen_d1[15]) idcv_ary_1111[{wr_index_d1[6:2]}] = din_d1;
`else
if (bit_wen_d1[12])
idcv_ary[{wr_index_d1[6:2],2'b11,2'b00}] = din_d1;
if (bit_wen_d1[13])
idcv_ary[{wr_index_d1[6:2],2'b11,2'b01}] = din_d1;
if (bit_wen_d1[14])
idcv_ary[{wr_index_d1[6:2],2'b11,2'b10}] = din_d1;
if (bit_wen_d1[15])
idcv_ary[{wr_index_d1[6:2],2'b11,2'b11}] = din_d1;
`endif
end
end // always @ (...
// synopsys translate_off
//----------------------------------------------------------------
// Monitors, shadow logic and other stuff not directly related to
// memory functionality
//----------------------------------------------------------------
`ifdef INNO_MUXEX
`else
// Address monitor
always @ (/*AUTOSENSE*/rd_index_d1 or rdreq_d1 or wr_index_d1
or wrreq_d1)
begin
if (rdreq_d1 && (rd_index_d1 == 7'bX))
begin
// 0in <fire -message "FATAL ERROR: bw_r_rf16x32 read address X"
`ifdef DEFINE_0IN
`else
//$error("RFRDADDR", "Error: bw_r_rf16x32 read address is %b\n", rd_index_d1);
`endif
end
else if (wrreq_d1 && (wr_index_d1 == 5'bX))
begin
// 0in <fire -message "FATAL ERROR: bw_r_rf16x32 write address X"
`ifdef DEFINE_0IN
`else
//$error("RFWRADDR", "Error: bw_r_rf16x32 write address is %b\n", wr_index_d1);
`endif
end
end // always @ (...
`endif // !`ifdef INNO_MUXEX
//reg [127:0] w0;
//reg [127:0] w1;
//reg [127:0] w2;
//reg [127:0] w3;
//integer i;
//
// always @(idcv_ary) begin
// for (i=0;i<128; i=i+1) begin
// w0[i] = idcv_ary[4*i];
// w1[i] = idcv_ary[4*i+1];
// w2[i] = idcv_ary[4*i+2];
// w3[i] = idcv_ary[4*i+3];
// end
// end
//
// reg [511:0] icv_ary;
//
// always @ (idcv_ary)
// icv_ary = idcv_ary;
// synopsys translate_on
endmodule |
module merlin_cs_regs
#(
parameter C_WORD_RESET_VECTOR = 30'h0
)
(
//
input wire clk_i,
input wire fclk_i,
input wire reset_i,
// access request / error reporting interface
input wire access_rd_i,
input wire access_wr_i,
input wire [11:0] access_addr_i,
output wire access_badcsr_o,
output wire access_badwrite_o,
output wire access_badpriv_o,
output reg [`RV_XLEN-1:0] access_rd_data_o,
// write-back interface
input wire wr_i, // already gated by the exceptions in the exception interface
input wire [1:0] wr_mode_i,
input wire [11:0] wr_addr_i,
input wire [`RV_XLEN-1:0] wr_data_i,
// exception, interrupt, and hart vectoring interface
input wire ex_valid_i,
input wire irqm_extern_i,
input wire irqm_softw_i,
input wire irqm_timer_i,
input wire irqs_extern_i,
input wire excp_ferr_i,
input wire excp_uerr_i,
input wire excp_maif_i,
input wire excp_mala_i,
input wire excp_masa_i,
input wire excp_ilgl_i,
input wire excp_ecall_i,
input wire [`RV_XLEN-1:0] excp_pc_i,
input wire [`RV_XLEN-1:0] excp_ins_i,
//
output wire interrupt_o,
//
output wire trap_call_o, // jump to trap
output wire [`RV_XLEN-1:0] trap_call_addr_o, // address to jump to
output wire [`RV_XLEN-1:0] trap_call_cause_o, // cause of trap
output reg [`RV_XLEN-1:0] trap_call_value_o, // trap call value ( [m|s|u]tval )
input wire trap_rtn_i, // return from trap
input wire [1:0] trap_rtn_mode_i, // mode of return ( [m|s|u]ret )
output reg [`RV_XLEN-1:0] trap_rtn_addr_o, // address to jump (return) to
// static i/o
output wire [1:0] mode_o // current processor mode
);
//--------------------------------------------------------------
// interface assignments
// access restriction logic
// csr read
reg access_badcsr;
// mstatus / sstatus / ustatus
wire [`RV_XLEN-1:0] mstatus;
wire [`RV_XLEN-1:0] sstatus;
wire [`RV_XLEN-1:0] ustatus;
//
reg [1:0] mode_d;
reg [1:0] mstatus_mpp_d;
reg mstatus_spp_d;
reg mstatus_mpie_d;
reg mstatus_spie_d;
reg mstatus_upie_d;
reg mstatus_mie_d;
reg mstatus_sie_d;
reg mstatus_uie_d;
//
reg [1:0] mode_q;
reg [1:0] mstatus_mpp_q;
reg mstatus_spp_q;
reg mstatus_mpie_q;
reg mstatus_spie_q;
reg mstatus_upie_q;
reg mstatus_mie_q;
reg mstatus_sie_q;
reg mstatus_uie_q;
// medeleg
wire [`RV_XLEN-1:0] medeleg;
//
reg medeleg_ecfs_d;
reg medeleg_ecfu_d;
reg medeleg_saf_d;
reg medeleg_sam_d;
reg medeleg_laf_d;
reg medeleg_lam_d;
reg medeleg_ii_d;
reg medeleg_iaf_d;
reg medeleg_iam_d;
//
reg medeleg_ecfs_q;
reg medeleg_ecfu_q;
reg medeleg_saf_q;
reg medeleg_sam_q;
reg medeleg_laf_q;
reg medeleg_lam_q;
reg medeleg_ii_q;
reg medeleg_iaf_q;
reg medeleg_iam_q;
// sedeleg
wire [`RV_XLEN-1:0] sedeleg;
//
reg sedeleg_ecfu_d;
reg sedeleg_saf_d;
reg sedeleg_sam_d;
reg sedeleg_laf_d;
reg sedeleg_lam_d;
reg sedeleg_ii_d;
reg sedeleg_iaf_d;
reg sedeleg_iam_d;
//
reg sedeleg_ecfu_q;
reg sedeleg_saf_q;
reg sedeleg_sam_q;
reg sedeleg_laf_q;
reg sedeleg_lam_q;
reg sedeleg_ii_q;
reg sedeleg_iaf_q;
reg sedeleg_iam_q;
// mideleg
wire [`RV_XLEN-1:0] mideleg;
//
reg mideleg_usi_d;
reg mideleg_ssi_d;
reg mideleg_uti_d;
reg mideleg_sti_d;
reg mideleg_uei_d;
reg mideleg_sei_d;
//
reg mideleg_usi_q;
reg mideleg_ssi_q;
reg mideleg_uti_q;
reg mideleg_sti_q;
reg mideleg_uei_q;
reg mideleg_sei_q;
// sideleg
wire [`RV_XLEN-1:0] sideleg;
//
reg sideleg_usi_d;
reg sideleg_uti_d;
reg sideleg_uei_d;
//
reg sideleg_usi_q;
reg sideleg_uti_q;
reg sideleg_uei_q;
// mtvec
wire [`RV_XLEN-1:0] mtvec;
//
reg [`RV_XLEN-3:0] mtvec_d;
reg [1:0] mtvec_mode_d;
//
reg [`RV_XLEN-3:0] mtvec_q;
reg [1:0] mtvec_mode_q;
// stvec
wire [`RV_XLEN-1:0] stvec;
//
reg [`RV_XLEN-3:0] stvec_d;
reg [1:0] stvec_mode_d;
//
reg [`RV_XLEN-3:0] stvec_q;
reg [1:0] stvec_mode_q;
// utvec
wire [`RV_XLEN-1:0] utvec;
//
reg [`RV_XLEN-3:0] utvec_d;
reg [1:0] utvec_mode_d;
//
reg [`RV_XLEN-3:0] utvec_q;
reg [1:0] utvec_mode_q;
// mie / sie / uie
wire [`RV_XLEN-1:0] mie;
wire [`RV_XLEN-1:0] sie;
wire [`RV_XLEN-1:0] uie;
//
reg mie_meie_d;
reg mie_seie_d;
reg mie_ueie_d;
reg mie_mtie_d;
reg mie_stie_d;
reg mie_utie_d;
reg mie_msie_d;
reg mie_ssie_d;
reg mie_usie_d;
//
reg mie_meie_q;
reg mie_seie_q;
reg mie_ueie_q;
reg mie_mtie_q;
reg mie_stie_q;
reg mie_utie_q;
reg mie_msie_q;
reg mie_ssie_q;
reg mie_usie_q;
// mip / sip / uip
wire [`RV_XLEN-1:0] mip;
wire [`RV_XLEN-1:0] sip;
wire [`RV_XLEN-1:0] uip;
//
wire mip_meip;
wire mip_mtip;
wire mip_msip;
wire mip_seip;
wire mip_stip;
wire mip_ssip;
wire mip_ueip;
wire mip_utip;
wire mip_usip;
//
reg mip_seip_d;
reg mip_ueip_d;
reg mip_stip_d;
reg mip_utip_d;
reg mip_ssip_d;
reg mip_usip_d;
//
reg mip_seip_q;
reg mip_ueip_q;
reg mip_stip_q;
reg mip_utip_q;
reg mip_ssip_q;
reg mip_usip_q;
// mscratch
wire [`RV_XLEN-1:0] mscratch;
//
reg [`RV_XLEN-1:0] mscratch_d;
//
reg [`RV_XLEN-1:0] mscratch_q;
// sscratch
wire [`RV_XLEN-1:0] sscratch;
//
reg [`RV_XLEN-1:0] sscratch_d;
//
reg [`RV_XLEN-1:0] sscratch_q;
// uscratch
wire [`RV_XLEN-1:0] uscratch;
//
reg [`RV_XLEN-1:0] uscratch_d;
//
reg [`RV_XLEN-1:0] uscratch_q;
// mepc
wire [`RV_XLEN-1:0] mepc;
//
`ifdef RV_CONFIG_STDEXT_C
reg [`RV_XLEN-2:0] mepc_d;
`else
reg [`RV_XLEN-3:0] mepc_d;
`endif
//
`ifdef RV_CONFIG_STDEXT_C
reg [`RV_XLEN-2:0] mepc_q;
`else
reg [`RV_XLEN-3:0] mepc_q;
`endif
// sepc
wire [`RV_XLEN-1:0] sepc;
//
`ifdef RV_CONFIG_STDEXT_C
reg [`RV_XLEN-2:0] sepc_d;
`else
reg [`RV_XLEN-3:0] sepc_d;
`endif
//
`ifdef RV_CONFIG_STDEXT_C
reg [`RV_XLEN-2:0] sepc_q;
`else
reg [`RV_XLEN-3:0] sepc_q;
`endif
// uepc
wire [`RV_XLEN-1:0] uepc;
//
`ifdef RV_CONFIG_STDEXT_C
reg [`RV_XLEN-2:0] uepc_d;
`else
reg [`RV_XLEN-3:0] uepc_d;
`endif
//
`ifdef RV_CONFIG_STDEXT_C
reg [`RV_XLEN-2:0] uepc_q;
`else
reg [`RV_XLEN-3:0] uepc_q;
`endif
// mcause
wire [`RV_XLEN-1:0] mcause;
//
reg mcause_int_d;
reg [3:0] mcause_code_d;
//
reg mcause_int_q;
reg [3:0] mcause_code_q;
// scause
wire [`RV_XLEN-1:0] scause;
//
reg scause_int_d;
reg [3:0] scause_code_d;
//
reg scause_int_q;
reg [3:0] scause_code_q;
// ucause
wire [`RV_XLEN-1:0] ucause;
//
reg ucause_int_d;
reg [3:0] ucause_code_d;
//
reg ucause_int_q;
reg [3:0] ucause_code_q;
// mtval
wire [`RV_XLEN-1:0] mtval;
//
reg [`RV_XLEN-1:0] mtval_d;
//
reg [`RV_XLEN-1:0] mtval_q;
// stval
wire [`RV_XLEN-1:0] stval;
//
reg [`RV_XLEN-1:0] stval_d;
//
reg [`RV_XLEN-1:0] stval_q;
// utval
wire [`RV_XLEN-1:0] utval;
//
reg [`RV_XLEN-1:0] utval_d;
//
reg [`RV_XLEN-1:0] utval_q;
// interrupt and exception logic
reg m_int_e_q;
reg m_int_t_q;
reg m_int_s_q;
reg s_int_e_q;
reg s_int_t_q;
reg s_int_s_q;
reg u_int_e_q;
reg u_int_t_q;
reg u_int_s_q;
//
reg interrupt;
reg [3:0] interrupt_cause;
reg [1:0] interrupt_mode;
//
reg exception;
reg [3:0] exception_cause;
reg [1:0] exception_mode;
// trap call logic
wire [3:0] trap_call_cause_code;
wire [1:0] trap_call_mode;
reg trap_call_vectored;
reg [`RV_XLEN-3:0] trap_call_base;
// trap return address mux
//--------------------------------------------------------------
//--------------------------------------------------------------
// read/modify/write functions
//--------------------------------------------------------------
function read_modify_write1;
input field_q;
input field_modifier;
begin
read_modify_write1 = field_modifier;
case (wr_mode_i)
2'b10 : read_modify_write1 = field_q | field_modifier;
2'b11 : read_modify_write1 = field_q & ~field_modifier;
default : begin
end
endcase
end
endfunction
//
function [1:0] read_modify_write2;
input [1:0] field_q;
input [1:0] field_modifier;
begin
read_modify_write2 = field_modifier;
case (wr_mode_i)
2'b10 : read_modify_write2 = field_q | field_modifier;
2'b11 : read_modify_write2 = field_q & ~field_modifier;
default : begin
end
endcase
end
endfunction
//
function [3:0] read_modify_write4;
input [3:0] field_q;
input [3:0] field_modifier;
begin
read_modify_write4 = field_modifier;
case (wr_mode_i)
2'b10 : read_modify_write4 = field_q | field_modifier;
2'b11 : read_modify_write4 = field_q & ~field_modifier;
default : begin
end
endcase
end
endfunction
//
`ifdef RV_CONFIG_STDEXT_C
function [`RV_XLEN-2:0] read_modify_writem1;
input [`RV_XLEN-2:0] field_q;
input [`RV_XLEN-2:0] field_modifier;
begin
read_modify_writem1 = field_modifier;
case (wr_mode_i)
2'b10 : read_modify_writem1 = field_q | field_modifier;
2'b11 : read_modify_writem1 = field_q & ~field_modifier;
default : begin
end
endcase
end
endfunction
`endif
//
function [`RV_XLEN-3:0] read_modify_writem2;
input [`RV_XLEN-3:0] field_q;
input [`RV_XLEN-3:0] field_modifier;
begin
read_modify_writem2 = field_modifier;
case (wr_mode_i)
2'b10 : read_modify_writem2 = field_q | field_modifier;
2'b11 : read_modify_writem2 = field_q & ~field_modifier;
default : begin
end
endcase
end
endfunction
//
function [`RV_XLEN-1:0] read_modify_write;
input [`RV_XLEN-1:0] field_q;
input [`RV_XLEN-1:0] field_modifier;
begin
read_modify_write = field_modifier;
case (wr_mode_i)
2'b10 : read_modify_write = field_q | field_modifier;
2'b11 : read_modify_write = field_q & ~field_modifier;
default : begin
end
endcase
end
endfunction
//--------------------------------------------------------------
// interface assignments
//--------------------------------------------------------------
assign interrupt_o = interrupt;
assign mode_o = mode_q;
//--------------------------------------------------------------
// access restriction logic
//--------------------------------------------------------------
assign access_badcsr_o = access_badcsr & (access_rd_i | access_wr_i);
assign access_badwrite_o = (access_addr_i[11:10] == 2'b11 ? access_wr_i
: 1'b0)
;
assign access_badpriv_o = (access_addr_i[9:8] > mode_d ? access_rd_i | access_wr_i
: 1'b0)
;
//--------------------------------------------------------------
// csr read
//--------------------------------------------------------------
always @ (*) begin
access_badcsr = 1'b0;
access_rd_data_o = { `RV_XLEN {1'bx} };
case (access_addr_i)
// user trap setup
12'h000 : access_rd_data_o = ustatus;
12'h004 : access_rd_data_o = uie;
12'h005 : access_rd_data_o = utvec;
// user trap handling
12'h040 : access_rd_data_o = uscratch;
12'h041 : access_rd_data_o = uepc;
12'h042 : access_rd_data_o = ucause;
12'h043 : access_rd_data_o = utval;
12'h044 : access_rd_data_o = uip;
// supervisor trap setup
12'h100 : access_rd_data_o = sstatus;
12'h102 : access_rd_data_o = sedeleg;
12'h103 : access_rd_data_o = sideleg;
12'h104 : access_rd_data_o = sie;
12'h105 : access_rd_data_o = stvec;
// 12'h106 : access_rd_data_o = ;
// supervisor trap handling
12'h140 : access_rd_data_o = sscratch;
12'h141 : access_rd_data_o = sepc;
12'h142 : access_rd_data_o = scause;
12'h143 : access_rd_data_o = stval;
12'h144 : access_rd_data_o = sip;
// machine information registers
// 12'hf00 : access_rd_data_o = ;
// 12'hf00 : access_rd_data_o = ;
// 12'hf00 : access_rd_data_o = ;
// 12'hf00 : access_rd_data_o = ;
// machine trap setup
12'h300 : access_rd_data_o = mstatus;
// 12'h301 : access_rd_data_o = ;
12'h302 : access_rd_data_o = medeleg;
12'h303 : access_rd_data_o = mideleg;
12'h304 : access_rd_data_o = mie;
12'h305 : access_rd_data_o = mtvec;
// 12'h306 : access_rd_data_o = ;
// machine trap handling
12'h340 : access_rd_data_o = mscratch;
12'h341 : access_rd_data_o = mepc;
12'h342 : access_rd_data_o = mcause;
12'h343 : access_rd_data_o = mtval;
12'h344 : access_rd_data_o = mip;
default : access_badcsr = 1'b1;
endcase
end
//--------------------------------------------------------------
// mstatus / sstatus / ustatus
//--------------------------------------------------------------
assign mstatus = {
`ifdef RV_CONFIG_STDEXT_64
1'b0, // SD - XS/FS signal dirty state
27'b0, // *WPRI*
2'b10, // SXL - supervisor XLEN (hardwired to 64-bit)
2'b10, // UXL - user XLEN (hardwired to 64-bit)
1'b0, // *WPRI*
`else // 32-bit is the only supported alternative at the moment
1'b0, // SD - XS/FS signal dirty state
`endif
8'b0, // *WPRI*
1'b0, // TSR - trap sret
1'b0, // TW - timeout wait
1'b0, // TVM - trap virtual memory
1'b0, // MXR - make executable readable
1'b0, // SUM - permit supervisor user mem access
1'b0, // MPRV - modify memory privilege
2'b0, // XS - user mode extension status
2'b0, // FS - fpu status
mstatus_mpp_d, // MPP - machine previous privilege
2'b0, // *WPRI*
mstatus_spp_d, // SPP - supervisor previous privilege
mstatus_mpie_d, // MPIE - machine previous interrupt enable
1'b0, // *WPRI*
mstatus_spie_d, // SPIE - supervisor previous interrupt enable
mstatus_upie_d, // UPIE - user previous interrupt enable
mstatus_mie_d, // MIE - machine interrupt enable
1'b0, // *WPRI*
mstatus_sie_d, // SIE - supervisor interrupt enable
mstatus_uie_d // UIE - user interrupt enable
};
assign sstatus = {
`ifdef RV_CONFIG_STDEXT_64
1'b0, // SD - XS/FS signal dirty state
27'b0, // *WPRI*
2'b00, // SXL - supervisor XLEN
2'b10, // UXL - user XLEN (hardwired to 64-bit)
1'b0, // *WPRI*
`else // 32-bit is the only supported alternative at the moment
1'b0, // SD - XS/FS signal dirty state
`endif
8'b0, // *WPRI*
1'b0, // TSR - trap sret
1'b0, // TW - timeout wait
1'b0, // TVM - trap virtual memory
1'b0, // MXR - make executable readable
1'b0, // SUM - permit supervisor user mem access
1'b0, // MPRV - modify memory privilege
2'b0, // XS - user mode extension status
2'b0, // FS - fpu status
2'b0, // MPP - machine previous privilege
2'b0, // *WPRI*
mstatus_spp_d, // SPP - supervisor previous privilege
1'b0, // MPIE - machine previous interrupt enable
1'b0, // *WPRI*
mstatus_spie_d, // SPIE - supervisor previous interrupt enable
mstatus_upie_d, // UPIE - user previous interrupt enable
1'b0, // MIE - machine interrupt enable
1'b0, // *WPRI*
mstatus_sie_d, // SIE - supervisor interrupt enable
mstatus_uie_d // UIE - user interrupt enable
};
assign ustatus = {
`ifdef RV_CONFIG_STDEXT_64
1'b0, // SD - XS/FS signal dirty state
27'b0, // *WPRI*
2'b00, // SXL - supervisor XLEN
2'b00, // UXL - user XLEN
1'b0, // *WPRI*
`else // 32-bit is the only supported alternative at the moment
1'b0, // SD - XS/FS signal dirty state
`endif
8'b0, // *WPRI*
1'b0, // TSR - trap sret
1'b0, // TW - timeout wait
1'b0, // TVM - trap virtual memory
1'b0, // MXR - make executable readable
1'b0, // SUM - permit supervisor user mem access
1'b0, // MPRV - modify memory privilege
2'b0, // XS - user mode extension status
2'b0, // FS - fpu status
2'b0, // MPP - machine previous privilege
2'b0, // *WPRI*
1'b0, // SPP - supervisor previous privilege
1'b0, // MPIE - machine previous interrupt enable
1'b0, // *WPRI*
1'b0, // SPIE - supervisor previous interrupt enable
mstatus_upie_d, // UPIE - user previous interrupt enable
1'b0, // MIE - machine interrupt enable
1'b0, // *WPRI*
1'b0, // SIE - supervisor interrupt enable
mstatus_uie_d // UIE - user interrupt enable
};
//
always @ (*) begin
mode_d = mode_q;
mstatus_mpp_d = mstatus_mpp_q;
mstatus_spp_d = mstatus_spp_q;
mstatus_mpie_d = mstatus_mpie_q;
mstatus_spie_d = mstatus_spie_q;
mstatus_upie_d = mstatus_upie_q;
mstatus_mie_d = mstatus_mie_q;
mstatus_sie_d = mstatus_sie_q;
mstatus_uie_d = mstatus_uie_q;
if (trap_call_o) begin
mode_d = trap_call_mode;
case (trap_call_mode)
`RV_CSR_MODE_MACHINE : begin
mstatus_mpp_d = mode_q;
mstatus_mpie_d = mstatus_mie_q;
mstatus_mie_d = 1'b0;
end
`RV_CSR_MODE_SUPERVISOR : begin
mstatus_spp_d = |mode_q; // 0 iff was user mode, 1 otherwise
mstatus_spie_d = mstatus_sie_q;
mstatus_sie_d = 1'b0;
end
`RV_CSR_MODE_USER : begin
mstatus_upie_d = mstatus_uie_q;
mstatus_uie_d = 1'b0;
end
default : begin
end
endcase
end else if (trap_rtn_i) begin
mstatus_mpp_d = `RV_CSR_MODE_USER;
mstatus_spp_d = 1'b0;
case (trap_rtn_mode_i)
`RV_CSR_MODE_MACHINE : begin
mode_d = mstatus_mpp_q;
mstatus_mie_d = mstatus_mpie_q;
mstatus_mpie_d = 1'b1;
end
`RV_CSR_MODE_SUPERVISOR : begin
if (mstatus_spp_q == 1'b0) begin
mode_d = `RV_CSR_MODE_USER;
end
mstatus_sie_d = mstatus_spie_q;
mstatus_spie_d = 1'b1;
end
`RV_CSR_MODE_USER : begin
mstatus_uie_d = mstatus_upie_q;
mstatus_upie_d = 1'b1;
end
default : begin
end
endcase
end else if (wr_i) begin
case (wr_addr_i)
12'h300 : begin // mstatus
mstatus_mpp_d = read_modify_write2(mstatus_mpp_q, wr_data_i[12:11]);
mstatus_spp_d = read_modify_write1(mstatus_spp_q, wr_data_i[8]);
mstatus_mpie_d = read_modify_write1(mstatus_mpie_q, wr_data_i[7]);
mstatus_spie_d = read_modify_write1(mstatus_spie_q, wr_data_i[5]);
mstatus_upie_d = read_modify_write1(mstatus_upie_q, wr_data_i[4]);
mstatus_mie_d = read_modify_write1(mstatus_mie_q, wr_data_i[3]);
mstatus_sie_d = read_modify_write1(mstatus_sie_q, wr_data_i[1]);
mstatus_uie_d = read_modify_write1(mstatus_uie_q, wr_data_i[0]);
end
12'h100 : begin // sstatus
mstatus_spp_d = read_modify_write1(mstatus_spp_q, wr_data_i[8]);
mstatus_spie_d = read_modify_write1(mstatus_spie_q, wr_data_i[5]);
mstatus_upie_d = read_modify_write1(mstatus_upie_q, wr_data_i[4]);
mstatus_sie_d = read_modify_write1(mstatus_sie_q, wr_data_i[1]);
mstatus_uie_d = read_modify_write1(mstatus_uie_q, wr_data_i[0]);
end
12'h000 : begin // ustatus
mstatus_upie_d = read_modify_write1(mstatus_upie_q, wr_data_i[4]);
mstatus_uie_d = read_modify_write1(mstatus_uie_q, wr_data_i[0]);
end
default : begin
end
endcase
end
end
//
always @ `RV_SYNC_LOGIC_CLOCK_RESET(clk_i, reset_i) begin
if (reset_i) begin
mode_q <= `RV_CSR_MODE_MACHINE;
mstatus_mpp_q <= 2'b0;
mstatus_spp_q <= 1'b0;
mstatus_mpie_q <= 1'b0;
mstatus_spie_q <= 1'b0;
mstatus_upie_q <= 1'b0;
mstatus_mie_q <= 1'b0;
mstatus_sie_q <= 1'b0;
mstatus_uie_q <= 1'b0;
end else begin
mode_q <= mode_d;
mstatus_mpp_q <= mstatus_mpp_d;
mstatus_spp_q <= mstatus_spp_d;
mstatus_mpie_q <= mstatus_mpie_d;
mstatus_spie_q <= mstatus_spie_d;
mstatus_upie_q <= mstatus_upie_d;
mstatus_mie_q <= mstatus_mie_d;
mstatus_sie_q <= mstatus_sie_d;
mstatus_uie_q <= mstatus_uie_d;
end
end
//--------------------------------------------------------------
// medeleg
//--------------------------------------------------------------
assign medeleg = {
`ifdef RV_CONFIG_STDEXT_64
32'b0, // *WARL*
`else // 32-bit is the only supported alternative at the moment
`endif
16'b0, // *WARL*
1'b0, // store/amo page fault
1'b0, // *WARL*
1'b0, // load page fault
1'b0, // instruction page fault
1'b0, // environment call from m-mode (cannot be delegated!)
1'b0, // *WARL*
medeleg_ecfs_d, // environment call from s-mode
medeleg_ecfu_d, // environment call from u-mode
medeleg_saf_d, // store/amo access fault
medeleg_sam_d, // store/amo address misaligned
medeleg_laf_d, // load access fault
medeleg_lam_d, // load address misaligned
1'b0, // breakpoint
medeleg_ii_d, // illegal instruction
medeleg_iaf_d, // instruction access fault
medeleg_iam_d // instruction address misaligned
};
//
always @ (*) begin
medeleg_ecfs_d = medeleg_ecfs_q;
medeleg_ecfu_d = medeleg_ecfu_q;
medeleg_saf_d = medeleg_saf_q;
medeleg_sam_d = medeleg_sam_q;
medeleg_laf_d = medeleg_laf_q;
medeleg_lam_d = medeleg_lam_q;
medeleg_ii_d = medeleg_ii_q;
medeleg_iaf_d = medeleg_iaf_q;
medeleg_iam_d = medeleg_iam_q;
if (wr_i) begin
if (wr_addr_i == 12'h302) begin
medeleg_ecfs_d = read_modify_write1(medeleg_ecfs_q, wr_data_i[9]);
medeleg_ecfu_d = read_modify_write1(medeleg_ecfu_q, wr_data_i[8]);
medeleg_saf_d = read_modify_write1(medeleg_saf_q, wr_data_i[7]);
medeleg_sam_d = read_modify_write1(medeleg_sam_q, wr_data_i[6]);
medeleg_laf_d = read_modify_write1(medeleg_laf_q, wr_data_i[5]);
medeleg_lam_d = read_modify_write1(medeleg_lam_q, wr_data_i[4]);
medeleg_ii_d = read_modify_write1(medeleg_ii_q, wr_data_i[2]);
medeleg_iaf_d = read_modify_write1(medeleg_iaf_q, wr_data_i[1]);
medeleg_iam_d = read_modify_write1(medeleg_iam_q, wr_data_i[0]);
end
end
end
//
always @ `RV_SYNC_LOGIC_CLOCK_RESET(clk_i, reset_i) begin
if (reset_i) begin
medeleg_ecfs_q <= 1'b0;
medeleg_ecfu_q <= 1'b0;
medeleg_saf_q <= 1'b0;
medeleg_sam_q <= 1'b0;
medeleg_laf_q <= 1'b0;
medeleg_lam_q <= 1'b0;
medeleg_ii_q <= 1'b0;
medeleg_iaf_q <= 1'b0;
medeleg_iam_q <= 1'b0;
end else begin
medeleg_ecfs_q <= medeleg_ecfs_d;
medeleg_ecfu_q <= medeleg_ecfu_d;
medeleg_saf_q <= medeleg_saf_d;
medeleg_sam_q <= medeleg_sam_d;
medeleg_laf_q <= medeleg_laf_d;
medeleg_lam_q <= medeleg_lam_d;
medeleg_ii_q <= medeleg_ii_d;
medeleg_iaf_q <= medeleg_iaf_d;
medeleg_iam_q <= medeleg_iam_d;
end
end
//--------------------------------------------------------------
// sedeleg
//--------------------------------------------------------------
assign sedeleg = {
`ifdef RV_CONFIG_STDEXT_64
32'b0, // *WARL*
`else // 32-bit is the only supported alternative at the moment
`endif
16'b0, // *WARL*
1'b0, // store/amo page fault
1'b0, // *WARL*
1'b0, // load page fault
1'b0, // instruction page fault
1'b0, // environment call from m-mode (cannot be delegated!)
1'b0, // *WARL*
1'b0, // environment call from s-mode (cannot be delegated!)
sedeleg_ecfu_d, // environment call from u-mode
sedeleg_saf_d, // store/amo access fault
sedeleg_sam_d, // store/amo address misaligned
sedeleg_laf_d, // load access fault
sedeleg_lam_d, // load address misaligned
1'b0, // breakpoint
sedeleg_ii_d, // illegal instruction
sedeleg_iaf_d, // instruction access fault
sedeleg_iam_d // instruction address misaligned
};
//
always @ (*) begin
sedeleg_ecfu_d = sedeleg_ecfu_q;
sedeleg_saf_d = sedeleg_saf_q;
sedeleg_sam_d = sedeleg_sam_q;
sedeleg_laf_d = sedeleg_laf_q;
sedeleg_lam_d = sedeleg_lam_q;
sedeleg_ii_d = sedeleg_ii_q;
sedeleg_iaf_d = sedeleg_iaf_q;
sedeleg_iam_d = sedeleg_iam_q;
if (wr_i) begin
if (wr_addr_i == 12'h102) begin
sedeleg_ecfu_d = read_modify_write1(sedeleg_ecfu_q, wr_data_i[8]);
sedeleg_saf_d = read_modify_write1(sedeleg_saf_q, wr_data_i[7]);
sedeleg_sam_d = read_modify_write1(sedeleg_sam_q, wr_data_i[6]);
sedeleg_laf_d = read_modify_write1(sedeleg_laf_q, wr_data_i[5]);
sedeleg_lam_d = read_modify_write1(sedeleg_lam_q, wr_data_i[4]);
sedeleg_ii_d = read_modify_write1(sedeleg_ii_q, wr_data_i[2]);
sedeleg_iaf_d = read_modify_write1(sedeleg_iaf_q, wr_data_i[1]);
sedeleg_iam_d = read_modify_write1(sedeleg_iam_q, wr_data_i[0]);
end
end
end
//
always @ `RV_SYNC_LOGIC_CLOCK_RESET(clk_i, reset_i) begin
if (reset_i) begin
sedeleg_ecfu_q <= 1'b0;
sedeleg_saf_q <= 1'b0;
sedeleg_sam_q <= 1'b0;
sedeleg_laf_q <= 1'b0;
sedeleg_lam_q <= 1'b0;
sedeleg_ii_q <= 1'b0;
sedeleg_iaf_q <= 1'b0;
sedeleg_iam_q <= 1'b0;
end else begin
sedeleg_ecfu_q <= sedeleg_ecfu_d;
sedeleg_saf_q <= sedeleg_saf_d;
sedeleg_sam_q <= sedeleg_sam_d;
sedeleg_laf_q <= sedeleg_laf_d;
sedeleg_lam_q <= sedeleg_lam_d;
sedeleg_ii_q <= sedeleg_ii_d;
sedeleg_iaf_q <= sedeleg_iaf_d;
sedeleg_iam_q <= sedeleg_iam_d;
end
end
//--------------------------------------------------------------
// mideleg
//--------------------------------------------------------------
assign mideleg = {
`ifdef RV_CONFIG_STDEXT_64
32'b0, // *WARL*
`else // 32-bit is the only supported alternative at the moment
`endif
20'b0, // *WARL*
1'b0, // machine external interrupt
1'b0, // *WARL*
mideleg_sei_d, // supervisor external interrupt
mideleg_uei_d, // user external interrupt
1'b0, // machine timer interrupt
1'b0, // *WARL*
mideleg_sti_d, // supervisor timer interrupt
mideleg_uti_d, // user timer interrupt
1'b0, // machine software interrupt
1'b0, // *WARL*
mideleg_ssi_d, // supervisor software interrupt
mideleg_usi_d // user software interrupt
};
//
always @ (*) begin
mideleg_usi_d = mideleg_usi_q;
mideleg_ssi_d = mideleg_ssi_q;
mideleg_uti_d = mideleg_uti_q;
mideleg_sti_d = mideleg_sti_q;
mideleg_uei_d = mideleg_uei_q;
mideleg_sei_d = mideleg_sei_q;
if (wr_i) begin
if (wr_addr_i == 12'h303) begin
mideleg_usi_d = read_modify_write1(mideleg_usi_q, wr_data_i[0]);
mideleg_ssi_d = read_modify_write1(mideleg_ssi_q, wr_data_i[1]);
mideleg_uti_d = read_modify_write1(mideleg_uti_q, wr_data_i[4]);
mideleg_sti_d = read_modify_write1(mideleg_sti_q, wr_data_i[5]);
mideleg_uei_d = read_modify_write1(mideleg_uei_q, wr_data_i[8]);
mideleg_sei_d = read_modify_write1(mideleg_sei_q, wr_data_i[9]);
end
end
end
//
always @ `RV_SYNC_LOGIC_CLOCK_RESET(clk_i, reset_i) begin
if (reset_i) begin
mideleg_usi_q <= 1'b0;
mideleg_ssi_q <= 1'b0;
mideleg_uti_q <= 1'b0;
mideleg_sti_q <= 1'b0;
mideleg_uei_q <= 1'b0;
mideleg_sei_q <= 1'b0;
end else begin
mideleg_usi_q <= mideleg_usi_d;
mideleg_ssi_q <= mideleg_ssi_d;
mideleg_uti_q <= mideleg_uti_d;
mideleg_sti_q <= mideleg_sti_d;
mideleg_uei_q <= mideleg_uei_d;
mideleg_sei_q <= mideleg_sei_d;
end
end
//--------------------------------------------------------------
// sideleg
//--------------------------------------------------------------
assign sideleg = {
`ifdef RV_CONFIG_STDEXT_64
32'b0, // *WARL*
`else // 32-bit is the only supported alternative at the moment
`endif
20'b0, // *WARL*
1'b0, // machine external interrupt
1'b0, // *WARL*
1'b0, // supervisor external interrupt
sideleg_uei_d, // user external interrupt
1'b0, // machine timer interrupt
1'b0, // *WARL*
1'b0, // supervisor timer interrupt
sideleg_uti_d, // user timer interrupt
1'b0, // machine software interrupt
1'b0, // *WARL*
1'b0, // supervisor software interrupt
sideleg_usi_d // user software interrupt
};
//
always @ (*) begin
sideleg_usi_d = sideleg_usi_q;
sideleg_uti_d = sideleg_uti_q;
sideleg_uei_d = sideleg_uei_q;
if (wr_i) begin
if (wr_addr_i == 12'h103) begin
sideleg_usi_d = read_modify_write1(sideleg_usi_q, wr_data_i[0]);
sideleg_uti_d = read_modify_write1(sideleg_uti_q, wr_data_i[4]);
sideleg_uei_d = read_modify_write1(sideleg_uei_q, wr_data_i[8]);
end
end
end
//
always @ `RV_SYNC_LOGIC_CLOCK_RESET(clk_i, reset_i) begin
if (reset_i) begin
sideleg_usi_q <= 1'b0;
sideleg_uti_q <= 1'b0;
sideleg_uei_q <= 1'b0;
end else begin
sideleg_usi_q <= sideleg_usi_d;
sideleg_uti_q <= sideleg_uti_d;
sideleg_uei_q <= sideleg_uei_d;
end
end
//--------------------------------------------------------------
// mtvec
//--------------------------------------------------------------
/*
* NOTE: In vectored mode icause replaces the bottom 4 bits of base field.
* See "trap call logic"
*/
assign mtvec = {
mtvec_d, // 32-bit aligned trap vector base address
mtvec_mode_d // trap vector mode (0 => direct, 1 => vectored, others => reserved)
};
//
always @ (*) begin
mtvec_d = mtvec_q;
mtvec_mode_d = mtvec_mode_q;
if (wr_i) begin
if (wr_addr_i == 12'h305) begin
mtvec_d = read_modify_writem2(mtvec_q, wr_data_i[`RV_XLEN-1:2]);
mtvec_mode_d = read_modify_write2(mtvec_mode_q, wr_data_i[1:0]);
end
end
end
//
always @ `RV_SYNC_LOGIC_CLOCK_RESET(clk_i, reset_i) begin
if (reset_i) begin
mtvec_q <= C_WORD_RESET_VECTOR;
mtvec_mode_q <= `RV_CSR_TVEC_MODE_DIRECT;
end else begin
mtvec_q <= mtvec_d;
mtvec_mode_q <= mtvec_mode_d;
end
end
//--------------------------------------------------------------
// stvec
//--------------------------------------------------------------
/*
* NOTE: In vectored mode icause replaces the bottom 4 bits of base field.
* See "trap call logic"
*/
assign stvec = {
stvec_d, // 32-bit aligned trap vector base address
stvec_mode_d // trap vector mode (0 => direct, 1 => vectored, others => reserved)
};
//
always @ (*) begin
stvec_d = stvec_q;
stvec_mode_d = stvec_mode_q;
if (wr_i) begin
if (wr_addr_i == 12'h105) begin
stvec_d = read_modify_writem2(stvec_q, wr_data_i[`RV_XLEN-1:2]);
stvec_mode_d = read_modify_write2(stvec_mode_q, wr_data_i[1:0]);
end
end
end
//
always @ `RV_SYNC_LOGIC_CLOCK(clk_i) begin
stvec_q <= stvec_d;
stvec_mode_q <= stvec_mode_d;
end
//--------------------------------------------------------------
// utvec
//--------------------------------------------------------------
/*
* NOTE: In vectored mode icause replaces the bottom 4 bits of base field.
* See "trap call logic"
*/
assign utvec = {
utvec_d, // 32-bit aligned trap vector base address
utvec_mode_d // trap vector mode (0 => direct, 1 => vectored, others => reserved)
};
//
always @ (*) begin
utvec_d = utvec_q;
utvec_mode_d = utvec_mode_q;
if (wr_i) begin
if (wr_addr_i == 12'h005) begin
utvec_d = read_modify_writem2(utvec_q, wr_data_i[`RV_XLEN-1:2]);
utvec_mode_d = read_modify_write2(utvec_mode_q, wr_data_i[1:0]);
end
end
end
//
always @ `RV_SYNC_LOGIC_CLOCK(clk_i) begin
utvec_q <= utvec_d;
utvec_mode_q <= utvec_mode_d;
end
//--------------------------------------------------------------
// mie / sie / uie
//--------------------------------------------------------------
assign mie = {
`ifdef RV_CONFIG_STDEXT_64
32'b0, // *WPRI*
`else // 32-bit is the only supported alternative at the moment
`endif
20'b0, // *WPRI*
mie_meie_d, // machine external interrupt enable
1'b0, // *WPRI*
mie_seie_d, // supervisor external interrupt enable
mie_ueie_d, // user external interrupt enable
mie_mtie_d, // machine timer interrupt enable
1'b0, // *WPRI*
mie_stie_d, // supervisor timer interrupt enable
mie_utie_d, // user timer interrupt enable
mie_msie_d, // machine software interrupt enable
1'b0, // *WPRI*
mie_ssie_d, // supervisor software interrupt enable
mie_usie_d // user software interrupt enable
};
//
assign sie = {
`ifdef RV_CONFIG_STDEXT_64
32'b0, // *WPRI*
`else // 32-bit is the only supported alternative at the moment
`endif
20'b0, // *WPRI*
1'b0, // machine external interrupt enable
1'b0, // *WPRI*
mie_seie_d, // supervisor external interrupt enable
mie_ueie_d, // user external interrupt enable
1'b0, // machine timer interrupt enable
1'b0, // *WPRI*
mie_stie_d, // supervisor timer interrupt enable
mie_utie_d, // user timer interrupt enable
1'b0, // machine software interrupt enable
1'b0, // *WPRI*
mie_ssie_d, // supervisor software interrupt enable
mie_usie_d // user software interrupt enable
};
//
assign uie = {
`ifdef RV_CONFIG_STDEXT_64
32'b0, // *WPRI*
`else // 32-bit is the only supported alternative at the moment
`endif
20'b0, // *WPRI*
1'b0, // machine external interrupt enable
1'b0, // *WPRI*
1'b0, // supervisor external interrupt enable
mie_ueie_d, // user external interrupt enable
1'b0, // machine timer interrupt enable
1'b0, // *WPRI*
1'b0, // supervisor timer interrupt enable
mie_utie_d, // user timer interrupt enable
1'b0, // machine software interrupt enable
1'b0, // *WPRI*
1'b0, // supervisor software interrupt enable
mie_usie_d // user software interrupt enable
};
//
always @ (*) begin
mie_meie_d = mie_meie_q;
mie_seie_d = mie_seie_q;
mie_ueie_d = mie_ueie_q;
mie_mtie_d = mie_mtie_q;
mie_stie_d = mie_stie_q;
mie_utie_d = mie_utie_q;
mie_msie_d = mie_msie_q;
mie_ssie_d = mie_ssie_q;
mie_usie_d = mie_usie_q;
if (wr_i) begin
case (wr_addr_i)
12'h304 : begin // mie
mie_meie_d = read_modify_write1(mie_meie_q, wr_data_i[11]);
mie_seie_d = read_modify_write1(mie_seie_q, wr_data_i[9]);
mie_ueie_d = read_modify_write1(mie_ueie_q, wr_data_i[8]);
mie_mtie_d = read_modify_write1(mie_mtie_q, wr_data_i[7]);
mie_stie_d = read_modify_write1(mie_stie_q, wr_data_i[5]);
mie_utie_d = read_modify_write1(mie_utie_q, wr_data_i[4]);
mie_msie_d = read_modify_write1(mie_msie_q, wr_data_i[3]);
mie_ssie_d = read_modify_write1(mie_ssie_q, wr_data_i[1]);
mie_usie_d = read_modify_write1(mie_usie_q, wr_data_i[0]);
end
12'h104 : begin // sie
mie_seie_d = read_modify_write1(mie_seie_q, wr_data_i[9]);
mie_ueie_d = read_modify_write1(mie_ueie_q, wr_data_i[8]);
mie_stie_d = read_modify_write1(mie_stie_q, wr_data_i[5]);
mie_utie_d = read_modify_write1(mie_utie_q, wr_data_i[4]);
mie_ssie_d = read_modify_write1(mie_ssie_q, wr_data_i[1]);
mie_usie_d = read_modify_write1(mie_usie_q, wr_data_i[0]);
end
12'h004 : begin // uie
mie_ueie_d = read_modify_write1(mie_ueie_q, wr_data_i[8]);
mie_utie_d = read_modify_write1(mie_utie_q, wr_data_i[4]);
mie_usie_d = read_modify_write1(mie_usie_q, wr_data_i[0]);
end
default : begin
end
endcase
end
end
//
always @ `RV_SYNC_LOGIC_CLOCK_RESET(clk_i, reset_i) begin
if (reset_i) begin
mie_meie_q <= 1'b0;
mie_seie_q <= 1'b0;
mie_ueie_q <= 1'b0;
mie_mtie_q <= 1'b0;
mie_stie_q <= 1'b0;
mie_utie_q <= 1'b0;
mie_msie_q <= 1'b0;
mie_ssie_q <= 1'b0;
mie_usie_q <= 1'b0;
end else begin
mie_meie_q <= mie_meie_d;
mie_seie_q <= mie_seie_d;
mie_ueie_q <= mie_ueie_d;
mie_mtie_q <= mie_mtie_d;
mie_stie_q <= mie_stie_d;
mie_utie_q <= mie_utie_d;
mie_msie_q <= mie_msie_d;
mie_ssie_q <= mie_ssie_d;
mie_usie_q <= mie_usie_d;
end
end
//--------------------------------------------------------------
// mip / sip / uip
//--------------------------------------------------------------
assign mip = {
`ifdef RV_CONFIG_STDEXT_64
32'b0, // *WPRI*
`else // 32-bit is the only supported alternative at the moment
`endif
20'b0, // *WPRI*
mip_meip, // machine external interrupt pending
1'b0, // *WPRI*
mip_seip, // supervisor external interrupt pending
mip_ueip, // user external interrupt pending
mip_mtip, // machine timer interrupt pending
1'b0, // *WPRI*
mip_stip, // supervisor timer interrupt pending
mip_utip, // user timer interrupt pending
mip_msip, // machine software interrupt pending
1'b0, // *WPRI*
mip_ssip, // supervisor software interrupt pending
mip_usip // user software interrupt pending
};
//
assign sip = {
`ifdef RV_CONFIG_STDEXT_64
32'b0, // *WPRI*
`else // 32-bit is the only supported alternative at the moment
`endif
20'b0, // *WPRI*
1'b0, // machine external interrupt pending
1'b0, // *WPRI*
mip_seip, // supervisor external interrupt pending
mip_ueip, // user external interrupt pending
1'b0, // machine timer interrupt pending
1'b0, // *WPRI*
mip_stip, // supervisor timer interrupt pending
mip_utip, // user timer interrupt pending
1'b0, // machine software interrupt pending
1'b0, // *WPRI*
mip_ssip, // supervisor software interrupt pending
mip_usip // user software interrupt pending
};
//
assign uip = {
`ifdef RV_CONFIG_STDEXT_64
32'b0, // *WPRI*
`else // 32-bit is the only supported alternative at the moment
`endif
20'b0, // *WPRI*
1'b0, // machine external interrupt pending
1'b0, // *WPRI*
1'b0, // supervisor external interrupt pending
mip_ueip, // user external interrupt pending
1'b0, // machine timer interrupt pending
1'b0, // *WPRI*
1'b0, // supervisor timer interrupt pending
mip_utip, // user timer interrupt pending
1'b0, // machine software interrupt pending
1'b0, // *WPRI*
1'b0, // supervisor software interrupt pending
mip_usip // user software interrupt pending
};
//
assign mip_meip = ( irqm_extern_i);
assign mip_mtip = ( irqm_timer_i );
assign mip_msip = ( irqm_softw_i );
assign mip_seip = (mip_seip_d | irqs_extern_i);
assign mip_stip = (mip_stip_d );
assign mip_ssip = (mip_ssip_d );
assign mip_ueip = (mip_ueip_d );
assign mip_utip = (mip_utip_d );
assign mip_usip = (mip_usip_d );
//
always @ (*) begin
mip_seip_d = mip_seip_q;
mip_ueip_d = mip_ueip_q;
mip_stip_d = mip_stip_q;
mip_utip_d = mip_utip_q;
mip_ssip_d = mip_ssip_q;
mip_usip_d = mip_usip_q;
if (wr_i) begin
case (wr_addr_i)
12'h344 : begin // mip
mip_seip_d = read_modify_write1(mip_seip_q, wr_data_i[9]);
mip_ueip_d = read_modify_write1(mip_ueip_q, wr_data_i[8]);
mip_stip_d = read_modify_write1(mip_stip_q, wr_data_i[5]);
mip_utip_d = read_modify_write1(mip_utip_q, wr_data_i[4]);
mip_ssip_d = read_modify_write1(mip_ssip_q, wr_data_i[1]);
mip_usip_d = read_modify_write1(mip_usip_q, wr_data_i[0]);
end
12'h144 : begin // sip
mip_ueip_d = read_modify_write1(mip_ueip_q, wr_data_i[8]);
mip_utip_d = read_modify_write1(mip_utip_q, wr_data_i[4]);
mip_ssip_d = read_modify_write1(mip_ssip_q, wr_data_i[1]);
mip_usip_d = read_modify_write1(mip_usip_q, wr_data_i[0]);
end
12'h044 : begin // uip
mip_usip_d = read_modify_write1(mip_usip_q, wr_data_i[0]);
end
default : begin
end
endcase
end
end
//
always @ `RV_SYNC_LOGIC_CLOCK_RESET(clk_i, reset_i) begin
if (reset_i) begin
mip_seip_q <= 1'b0;
mip_ueip_q <= 1'b0;
mip_stip_q <= 1'b0;
mip_utip_q <= 1'b0;
mip_ssip_q <= 1'b0;
mip_usip_q <= 1'b0;
end else begin
mip_seip_q <= mip_seip_d;
mip_ueip_q <= mip_ueip_d;
mip_stip_q <= mip_stip_d;
mip_utip_q <= mip_utip_d;
mip_ssip_q <= mip_ssip_d;
mip_usip_q <= mip_usip_d;
end
end
//--------------------------------------------------------------
// mscratch
//--------------------------------------------------------------
assign mscratch = mscratch_d; // scratch register
//
always @ (*) begin
mscratch_d = mscratch_q;
if (wr_i) begin
if (wr_addr_i == 12'h340) begin
mscratch_d = read_modify_write(mscratch_q, wr_data_i);
end
end
end
//
always @ `RV_SYNC_LOGIC_CLOCK(clk_i) begin
mscratch_q <= mscratch_d;
end
//--------------------------------------------------------------
// sscratch
//--------------------------------------------------------------
assign sscratch = sscratch_d; // scratch register
//
always @ (*) begin
sscratch_d = sscratch_q;
if (wr_i) begin
if (wr_addr_i == 12'h140) begin
sscratch_d = read_modify_write(sscratch_q, wr_data_i);
end
end
end
//
always @ `RV_SYNC_LOGIC_CLOCK(clk_i) begin
sscratch_q <= sscratch_d;
end
//--------------------------------------------------------------
// uscratch
//--------------------------------------------------------------
assign uscratch = uscratch_d; // scratch register
//
always @ (*) begin
uscratch_d = uscratch_q;
if (wr_i) begin
if (wr_addr_i == 12'h040) begin
uscratch_d = read_modify_write(uscratch_q, wr_data_i);
end
end
end
//
always @ `RV_SYNC_LOGIC_CLOCK(clk_i) begin
uscratch_q <= uscratch_d;
end
//--------------------------------------------------------------
// mepc
//--------------------------------------------------------------
assign mepc = {
mepc_d, // exception program counter
`ifdef RV_CONFIG_STDEXT_C
`else
1'b0,
`endif
1'b0
};
//
always @ (*) begin
mepc_d = mepc_q;
if (trap_call_o && trap_call_mode == `RV_CSR_MODE_MACHINE) begin
`ifdef RV_CONFIG_STDEXT_C
mepc_d = excp_pc_i[`RV_XLEN-1:1];
`else
mepc_d = excp_pc_i[`RV_XLEN-1:2];
`endif
end else if (wr_i) begin
if (wr_addr_i == 12'h341) begin
`ifdef RV_CONFIG_STDEXT_C
mepc_d = read_modify_writem1(mepc_q, wr_data_i[`RV_XLEN-1:1]);
`else
mepc_d = read_modify_writem2(mepc_q, wr_data_i[`RV_XLEN-1:2]);
`endif
end
end
end
//
always @ `RV_SYNC_LOGIC_CLOCK(clk_i) begin
mepc_q <= mepc_d;
end
//--------------------------------------------------------------
// sepc
//--------------------------------------------------------------
assign sepc = {
sepc_d, // exception program counter
`ifdef RV_CONFIG_STDEXT_C
`else
1'b0,
`endif
1'b0
};
//
always @ (*) begin
sepc_d = sepc_q;
if (trap_call_o && trap_call_mode == `RV_CSR_MODE_SUPERVISOR) begin
`ifdef RV_CONFIG_STDEXT_C
sepc_d = excp_pc_i[`RV_XLEN-1:1];
`else
sepc_d = excp_pc_i[`RV_XLEN-1:2];
`endif
end else if (wr_i) begin
if (wr_addr_i == 12'h141) begin
`ifdef RV_CONFIG_STDEXT_C
sepc_d = read_modify_writem1(sepc_q, wr_data_i[`RV_XLEN-1:1]);
`else
sepc_d = read_modify_writem2(sepc_q, wr_data_i[`RV_XLEN-1:2]);
`endif
end
end
end
//
always @ `RV_SYNC_LOGIC_CLOCK(clk_i) begin
sepc_q <= sepc_d;
end
//--------------------------------------------------------------
// uepc
//--------------------------------------------------------------
assign uepc = {
uepc_d, // exception program counter
`ifdef RV_CONFIG_STDEXT_C
`else
1'b0,
`endif
1'b0
};
//
always @ (*) begin
uepc_d = uepc_q;
if (trap_call_o && trap_call_mode == `RV_CSR_MODE_USER) begin
`ifdef RV_CONFIG_STDEXT_C
uepc_d = excp_pc_i[`RV_XLEN-1:1];
`else
uepc_d = excp_pc_i[`RV_XLEN-1:2];
`endif
end else if (wr_i) begin
if (wr_addr_i == 12'h041) begin
`ifdef RV_CONFIG_STDEXT_C
uepc_d = read_modify_writem1(uepc_q, wr_data_i[`RV_XLEN-1:1]);
`else
uepc_d = read_modify_writem2(uepc_q, wr_data_i[`RV_XLEN-1:2]);
`endif
end
end
end
//
always @ `RV_SYNC_LOGIC_CLOCK(clk_i) begin
uepc_q <= uepc_d;
end
//--------------------------------------------------------------
// mcause
//--------------------------------------------------------------
assign mcause = {
mcause_int_d, // interrupt
{ `RV_XLEN-5 {1'b0} }, // *WLRL*
mcause_code_d // cause code
};
//
always @ (*) begin
mcause_int_d = mcause_int_q;
mcause_code_d = mcause_code_q;
if (trap_call_o && trap_call_mode == `RV_CSR_MODE_MACHINE) begin
mcause_int_d = interrupt;
mcause_code_d = trap_call_cause_code;
end else if (wr_i) begin
if (wr_addr_i == 12'h342) begin
mcause_int_d = read_modify_write1(mcause_int_q, wr_data_i[`RV_XLEN-1]);
mcause_code_d = read_modify_write4(mcause_code_q, wr_data_i[3:0]);
end
end
end
//
always @ `RV_SYNC_LOGIC_CLOCK(clk_i) begin
mcause_int_q <= mcause_int_d;
mcause_code_q <= mcause_code_d;
end
//--------------------------------------------------------------
// scause
//--------------------------------------------------------------
assign scause = {
scause_int_d, // interrupt
{ `RV_XLEN-5 {1'b0} }, // *WLRL*
scause_code_d // cause code
};
//
always @ (*) begin
scause_int_d = scause_int_q;
scause_code_d = scause_code_q;
if (trap_call_o && trap_call_mode == `RV_CSR_MODE_SUPERVISOR) begin
scause_int_d = interrupt;
scause_code_d = trap_call_cause_code;
end else if (wr_i) begin
if (wr_addr_i == 12'h142) begin
scause_int_d = read_modify_write1(scause_int_q, wr_data_i[`RV_XLEN-1]);
scause_code_d = read_modify_write4(scause_code_q, wr_data_i[3:0]);
end
end
end
//
always @ `RV_SYNC_LOGIC_CLOCK(clk_i) begin
scause_int_q <= scause_int_d;
scause_code_q <= scause_code_d;
end
//--------------------------------------------------------------
// ucause
//--------------------------------------------------------------
assign ucause = {
ucause_int_d, // interrupt
{ `RV_XLEN-5 {1'b0} }, // *WLRL*
ucause_code_d // cause code
};
//
always @ (*) begin
ucause_int_d = ucause_int_q;
ucause_code_d = ucause_code_q;
if (trap_call_o && trap_call_mode == `RV_CSR_MODE_USER) begin
ucause_int_d = interrupt;
ucause_code_d = trap_call_cause_code;
end else if (wr_i) begin
if (wr_addr_i == 12'h042) begin
ucause_int_d = read_modify_write1(ucause_int_q, wr_data_i[`RV_XLEN-1]);
ucause_code_d = read_modify_write4(ucause_code_q, wr_data_i[3:0]);
end
end
end
//
always @ `RV_SYNC_LOGIC_CLOCK(clk_i) begin
ucause_int_q <= ucause_int_d;
ucause_code_q <= ucause_code_d;
end
//--------------------------------------------------------------
// mtval
//--------------------------------------------------------------
assign mtval = mtval_d; // trap value
//
always @ (*) begin
mtval_d = mtval_q;
if (trap_call_o && trap_call_mode == `RV_CSR_MODE_MACHINE) begin
mtval_d = trap_call_value_o;
end else if (wr_i) begin
if (wr_addr_i == 12'h343) begin
mtval_d = read_modify_write(mtval_q, wr_data_i);
end
end
end
//
always @ `RV_SYNC_LOGIC_CLOCK(clk_i) begin
mtval_q <= mtval_d;
end
//--------------------------------------------------------------
// stval
//--------------------------------------------------------------
assign stval = stval_d; // trap value
//
always @ (*) begin
stval_d = stval_q;
if (trap_call_o && trap_call_mode == `RV_CSR_MODE_SUPERVISOR) begin
stval_d = trap_call_value_o;
end else if (wr_i) begin
if (wr_addr_i == 12'h343) begin
stval_d = read_modify_write(stval_q, wr_data_i);
end
end
end
//
always @ `RV_SYNC_LOGIC_CLOCK(clk_i) begin
stval_q <= stval_d;
end
//--------------------------------------------------------------
// utval
//--------------------------------------------------------------
assign utval = utval_d; // trap value
//
always @ (*) begin
utval_d = utval_q;
if (trap_call_o && trap_call_mode == `RV_CSR_MODE_USER) begin
utval_d = trap_call_value_o;
end else if (wr_i) begin
if (wr_addr_i == 12'h343) begin
utval_d = read_modify_write(utval_q, wr_data_i);
end
end
end
//
always @ `RV_SYNC_LOGIC_CLOCK(clk_i) begin
utval_q <= utval_d;
end
//--------------------------------------------------------------
// interrupt and exception logic
//--------------------------------------------------------------
/*
* Traps should be taken with the following priority:
* 1) external interrupts
* 2) software interrupts
* 3) timer interrupts
* 4) synchronous traps
*/
always @ `RV_SYNC_LOGIC_CLOCK_RESET(fclk_i, reset_i) begin
if (reset_i) begin
m_int_e_q <= 1'b0;
m_int_t_q <= 1'b0;
m_int_s_q <= 1'b0;
s_int_e_q <= 1'b0;
s_int_t_q <= 1'b0;
s_int_s_q <= 1'b0;
u_int_e_q <= 1'b0;
u_int_t_q <= 1'b0;
u_int_s_q <= 1'b0;
end else begin
m_int_e_q <= mip_meip & mie_meie_q;
m_int_t_q <= mip_mtip & mie_mtie_q;
m_int_s_q <= mip_msip & mie_msie_q;
s_int_e_q <= mip_seip & mie_seie_q;
s_int_t_q <= mip_stip & mie_stie_q;
s_int_s_q <= mip_ssip & mie_ssie_q;
u_int_e_q <= mip_ueip & mie_ueie_q;
u_int_t_q <= mip_utip & mie_utie_q;
u_int_s_q <= mip_usip & mie_usie_q;
end
end
// interrupt logic
always @ (*) begin
interrupt = 1'b0;
interrupt_cause = 4'bx;
interrupt_mode = `RV_CSR_MODE_MACHINE;
case (mode_q)
`RV_CSR_MODE_MACHINE : begin
interrupt = (mstatus_mie_q & (m_int_e_q | m_int_t_q | m_int_s_q));
// interrupt cause encoder
if (m_int_e_q) begin // machine external interrupt
interrupt_cause = `RV_CSR_INTR_CAUSE_ME;
interrupt_mode = `RV_CSR_MODE_MACHINE;
end else if (m_int_s_q) begin // machine software interrupt
interrupt_cause = `RV_CSR_INTR_CAUSE_MS;
interrupt_mode = `RV_CSR_MODE_MACHINE;
end else begin // machine timer interrupt
interrupt_cause = `RV_CSR_INTR_CAUSE_MT;
interrupt_mode = `RV_CSR_MODE_MACHINE;
end
end
`RV_CSR_MODE_SUPERVISOR : begin
interrupt = ( (m_int_e_q | m_int_t_q | m_int_s_q)) |
(mstatus_sie_q & (s_int_e_q | s_int_t_q | s_int_s_q)) ;
// interrupt cause and mode encoder
if (m_int_e_q) begin // machine external interrupt
interrupt_cause = `RV_CSR_INTR_CAUSE_ME;
interrupt_mode = `RV_CSR_MODE_MACHINE;
end else if (m_int_s_q) begin // machine software interrupt
interrupt_cause = `RV_CSR_INTR_CAUSE_MS;
interrupt_mode = `RV_CSR_MODE_MACHINE;
end else if (m_int_t_q) begin // machine timer interrupt
interrupt_cause = `RV_CSR_INTR_CAUSE_MT;
interrupt_mode = `RV_CSR_MODE_MACHINE;
end else if (s_int_e_q) begin // supervisor external interrupt
interrupt_cause = `RV_CSR_INTR_CAUSE_SE;
interrupt_mode = (mideleg_sei_q ? `RV_CSR_MODE_SUPERVISOR
: `RV_CSR_MODE_MACHINE)
;
end else if (s_int_s_q) begin // supervisor software interrupt
interrupt_cause = `RV_CSR_INTR_CAUSE_SS;
interrupt_mode = (mideleg_ssi_q ? `RV_CSR_MODE_SUPERVISOR
: `RV_CSR_MODE_MACHINE)
;
end else begin // supervisor timer interrupt
interrupt_cause = `RV_CSR_INTR_CAUSE_ST;
interrupt_mode = (mideleg_sti_q ? `RV_CSR_MODE_SUPERVISOR
: `RV_CSR_MODE_MACHINE)
;
end
end
`RV_CSR_MODE_USER : begin
interrupt = ( (m_int_e_q | m_int_t_q | m_int_s_q)) |
( (s_int_e_q | s_int_t_q | s_int_s_q)) |
(mstatus_uie_q & (u_int_e_q | u_int_t_q | u_int_s_q)) ;
// interrupt cause and mode encoder
if (m_int_e_q) begin // machine external interrupt
interrupt_cause = `RV_CSR_INTR_CAUSE_ME;
interrupt_mode = `RV_CSR_MODE_MACHINE;
end else if (m_int_s_q) begin // machine software interrupt
interrupt_cause = `RV_CSR_INTR_CAUSE_MS;
interrupt_mode = `RV_CSR_MODE_MACHINE;
end else if (m_int_t_q) begin // machine timer interrupt
interrupt_cause = `RV_CSR_INTR_CAUSE_MT;
interrupt_mode = `RV_CSR_MODE_MACHINE;
end else if (s_int_e_q) begin // supervisor external interrupt
interrupt_cause = `RV_CSR_INTR_CAUSE_SE;
interrupt_mode = (mideleg_sei_q ? `RV_CSR_MODE_SUPERVISOR
: `RV_CSR_MODE_MACHINE)
;
end else if (s_int_s_q) begin // supervisor software interrupt
interrupt_cause = `RV_CSR_INTR_CAUSE_SS;
interrupt_mode = (mideleg_ssi_q ? `RV_CSR_MODE_SUPERVISOR
: `RV_CSR_MODE_MACHINE)
;
end else if (s_int_t_q) begin // supervisor timer interrupt
interrupt_cause = `RV_CSR_INTR_CAUSE_ST;
interrupt_mode = (mideleg_sti_q ? `RV_CSR_MODE_SUPERVISOR
: `RV_CSR_MODE_MACHINE)
;
end else if (u_int_e_q) begin // user external interrupt
interrupt_cause = `RV_CSR_INTR_CAUSE_UE;
interrupt_mode = (mideleg_uei_q ? (sideleg_uei_q ? `RV_CSR_MODE_USER
: `RV_CSR_MODE_SUPERVISOR)
: `RV_CSR_MODE_MACHINE)
;
end else if (u_int_s_q) begin // user software interrupt
interrupt_cause = `RV_CSR_INTR_CAUSE_US;
interrupt_mode = (mideleg_usi_q ? (sideleg_usi_q ? `RV_CSR_MODE_USER
: `RV_CSR_MODE_SUPERVISOR)
: `RV_CSR_MODE_MACHINE)
;
end else begin // user timer interrupt
interrupt_cause = `RV_CSR_INTR_CAUSE_UT;
interrupt_mode = (mideleg_uti_q ? (sideleg_uti_q ? `RV_CSR_MODE_USER
: `RV_CSR_MODE_SUPERVISOR)
: `RV_CSR_MODE_MACHINE)
;
end
end
default : begin
end
endcase
end
// exception logic
always @ (*) begin
exception = 1'b0;
exception_cause = 4'bx;
exception_mode = `RV_CSR_MODE_MACHINE;
case (mode_q)
`RV_CSR_MODE_MACHINE : begin
// exception cause and mode encoder
if (excp_ferr_i) begin
exception = 1'b1;
exception_cause = `RV_CSR_EXCP_CAUSE_INS_ACCESS_FAULT;
exception_mode = `RV_CSR_MODE_MACHINE;
end else if (excp_uerr_i) begin
exception = 1'b1;
exception_cause = `RV_CSR_EXCP_CAUSE_ILLEGAL_INS;
exception_mode = `RV_CSR_MODE_MACHINE;
end else if (excp_ilgl_i) begin
exception = 1'b1;
exception_cause = `RV_CSR_EXCP_CAUSE_ILLEGAL_INS;
exception_mode = `RV_CSR_MODE_MACHINE;
end else if (excp_maif_i) begin
exception = 1'b1;
exception_cause = `RV_CSR_EXCP_CAUSE_INS_ADDR_MISALIGNED;
exception_mode = `RV_CSR_MODE_MACHINE;
end else if (excp_mala_i) begin
exception = 1'b1;
exception_cause = `RV_CSR_EXCP_CAUSE_LOAD_ADDR_MISALIGNED;
exception_mode = `RV_CSR_MODE_MACHINE;
end else if (excp_masa_i) begin
exception = 1'b1;
exception_cause = `RV_CSR_EXCP_CAUSE_STORE_ADDR_MISALIGNED;
exception_mode = `RV_CSR_MODE_MACHINE;
end else if (excp_ecall_i) begin
exception = 1'b1;
exception_cause = `RV_CSR_EXCP_CAUSE_ECALL_FROM_MMODE;
exception_mode = `RV_CSR_MODE_MACHINE;
end
end
`RV_CSR_MODE_SUPERVISOR : begin
// exception cause and mode encoder
if (excp_ferr_i) begin
exception = 1'b1;
exception_cause = `RV_CSR_EXCP_CAUSE_INS_ACCESS_FAULT;
exception_mode = (medeleg_iaf_q ? `RV_CSR_MODE_SUPERVISOR
: `RV_CSR_MODE_MACHINE)
;
end else if (excp_uerr_i) begin
exception = 1'b1;
exception_cause = `RV_CSR_EXCP_CAUSE_ILLEGAL_INS;
exception_mode = (medeleg_ii_q ? `RV_CSR_MODE_SUPERVISOR
: `RV_CSR_MODE_MACHINE)
;
end else if (excp_ilgl_i) begin
exception = 1'b1;
exception_cause = `RV_CSR_EXCP_CAUSE_ILLEGAL_INS;
exception_mode = (medeleg_ii_q ? `RV_CSR_MODE_SUPERVISOR
: `RV_CSR_MODE_MACHINE)
;
end else if (excp_maif_i) begin
exception = 1'b1;
exception_cause = `RV_CSR_EXCP_CAUSE_INS_ADDR_MISALIGNED;
exception_mode = (medeleg_iam_q ? `RV_CSR_MODE_SUPERVISOR
: `RV_CSR_MODE_MACHINE)
;
end else if (excp_mala_i) begin
exception = 1'b1;
exception_cause = `RV_CSR_EXCP_CAUSE_LOAD_ADDR_MISALIGNED;
exception_mode = (medeleg_lam_q ? `RV_CSR_MODE_SUPERVISOR
: `RV_CSR_MODE_MACHINE)
;
end else if (excp_masa_i) begin
exception = 1'b1;
exception_cause = `RV_CSR_EXCP_CAUSE_STORE_ADDR_MISALIGNED;
exception_mode = (medeleg_sam_q ? `RV_CSR_MODE_SUPERVISOR
: `RV_CSR_MODE_MACHINE)
;
end else if (excp_ecall_i) begin
exception = 1'b1;
exception_cause = `RV_CSR_EXCP_CAUSE_ECALL_FROM_SMODE;
exception_mode = (medeleg_ecfs_q ? `RV_CSR_MODE_SUPERVISOR
: `RV_CSR_MODE_MACHINE)
;
end
end
`RV_CSR_MODE_USER : begin
// exception cause and mode encoder
if (excp_ferr_i) begin
exception = 1'b1;
exception_cause = `RV_CSR_EXCP_CAUSE_INS_ACCESS_FAULT;
exception_mode = (medeleg_iaf_q ? (sedeleg_iaf_q ? `RV_CSR_MODE_USER
: `RV_CSR_MODE_SUPERVISOR)
: `RV_CSR_MODE_MACHINE)
;
end else if (excp_uerr_i) begin
exception = 1'b1;
exception_cause = `RV_CSR_EXCP_CAUSE_ILLEGAL_INS;
exception_mode = (medeleg_ii_q ? (sedeleg_ii_q ? `RV_CSR_MODE_USER
: `RV_CSR_MODE_SUPERVISOR)
: `RV_CSR_MODE_MACHINE)
;
end else if (excp_ilgl_i) begin
exception = 1'b1;
exception_cause = `RV_CSR_EXCP_CAUSE_ILLEGAL_INS;
exception_mode = (medeleg_ii_q ? (sedeleg_ii_q ? `RV_CSR_MODE_USER
: `RV_CSR_MODE_SUPERVISOR)
: `RV_CSR_MODE_MACHINE)
;
end else if (excp_maif_i) begin
exception = 1'b1;
exception_cause = `RV_CSR_EXCP_CAUSE_INS_ADDR_MISALIGNED;
exception_mode = (medeleg_iam_q ? (sedeleg_iam_q ? `RV_CSR_MODE_USER
: `RV_CSR_MODE_SUPERVISOR)
: `RV_CSR_MODE_MACHINE)
;
end else if (excp_mala_i) begin
exception = 1'b1;
exception_cause = `RV_CSR_EXCP_CAUSE_LOAD_ADDR_MISALIGNED;
exception_mode = (medeleg_lam_q ? (sedeleg_lam_q ? `RV_CSR_MODE_USER
: `RV_CSR_MODE_SUPERVISOR)
: `RV_CSR_MODE_MACHINE)
;
end else if (excp_masa_i) begin
exception = 1'b1;
exception_cause = `RV_CSR_EXCP_CAUSE_STORE_ADDR_MISALIGNED;
exception_mode = (medeleg_sam_q ? (sedeleg_sam_q ? `RV_CSR_MODE_USER
: `RV_CSR_MODE_SUPERVISOR)
: `RV_CSR_MODE_MACHINE)
;
end else if (excp_ecall_i) begin
exception = 1'b1;
exception_cause = `RV_CSR_EXCP_CAUSE_ECALL_FROM_UMODE;
exception_mode = (medeleg_ecfu_q ? (sedeleg_ecfu_q ? `RV_CSR_MODE_USER
: `RV_CSR_MODE_SUPERVISOR)
: `RV_CSR_MODE_MACHINE)
;
end
end
default : begin
end
endcase
end
//--------------------------------------------------------------
// trap call logic
//--------------------------------------------------------------
/*
* Traps should be taken with the following priority:
* 1) external interrupts
* 2) software interrupts
* 3) timer interrupts
* 4) synchronous traps
*/
assign trap_call_o = ex_valid_i & (interrupt | exception);
assign trap_call_cause_o = { interrupt, { `RV_XLEN-5 {1'b0} }, trap_call_cause_code };
assign trap_call_addr_o = (trap_call_vectored ? { trap_call_base[`RV_XLEN-3:4], interrupt_cause, 2'b0 }
: { trap_call_base, 2'b0 })
;
assign trap_call_cause_code = (interrupt ? interrupt_cause
: exception_cause)
;
assign trap_call_mode = (interrupt ? interrupt_mode
: exception_mode)
;
// trap value encoder
always @ (*) begin
if (interrupt) begin // TODO hardware breakpoint | page fault
trap_call_value_o = { `RV_XLEN {1'b0} };
end else if (excp_maif_i | excp_mala_i | excp_masa_i) begin
trap_call_value_o = excp_pc_i;
end else if (excp_uerr_i | excp_ilgl_i) begin
trap_call_value_o = excp_ins_i;
end else begin
trap_call_value_o = { `RV_XLEN {1'b0} };
end
end
// trap call base address and offset mode decoder
always @ (*) begin
trap_call_vectored = 1'b0;
trap_call_base = { `RV_XLEN-2 {1'bx} };
case (trap_call_mode)
`RV_CSR_MODE_MACHINE : begin
trap_call_base = mtvec_q;
if (mtvec_mode_q == `RV_CSR_TVEC_MODE_VECTORED) begin
trap_call_vectored = interrupt;
end
end
`RV_CSR_MODE_SUPERVISOR : begin
trap_call_base = stvec_q;
if (stvec_mode_q == `RV_CSR_TVEC_MODE_VECTORED) begin
trap_call_vectored = interrupt;
end
end
`RV_CSR_MODE_USER : begin
trap_call_base = utvec_q;
if (utvec_mode_q == `RV_CSR_TVEC_MODE_VECTORED) begin
trap_call_vectored = interrupt;
end
end
default : begin
end
endcase
end
//--------------------------------------------------------------
// trap return address mux
//--------------------------------------------------------------
always @ (*) begin
trap_rtn_addr_o = { `RV_XLEN {1'bx} };
case (trap_rtn_mode_i)
`ifdef RV_CONFIG_STDEXT_C
`RV_CSR_MODE_MACHINE : trap_rtn_addr_o = { mepc_q, 1'b0 };
`RV_CSR_MODE_SUPERVISOR : trap_rtn_addr_o = { sepc_q, 1'b0 };
`RV_CSR_MODE_USER : trap_rtn_addr_o = { uepc_q, 1'b0 };
`else
`RV_CSR_MODE_MACHINE : trap_rtn_addr_o = { mepc_q, 2'b0 };
`RV_CSR_MODE_SUPERVISOR : trap_rtn_addr_o = { sepc_q, 2'b0 };
`RV_CSR_MODE_USER : trap_rtn_addr_o = { uepc_q, 2'b0 };
`endif
default : begin
end
endcase
end
endmodule |
module register_file
(
input wire clk,
// -- inputs ------------------------------------------------- >>>>>
input wire write_strobe_din,
input wire [ADDR_WIDTH-1:0] write_address_din,
input wire [`CHANNEL_WIDTH-1:0] write_data_din,
input wire [ADDR_WIDTH-1:0] read_address_din,
// -- outputs ------------------------------------------------ >>>>>
output wire [`CHANNEL_WIDTH-1:0] read_data_dout
);
// --- Definiciones Locales -------------------------------------- >>>>>
localparam ADDR_WIDTH = clog2(`BUFFER_DEPTH);
// -- Modelado de matriz de almacenamiento ----------------------- >>>>>
reg [`CHANNEL_WIDTH-1:0] REG_FILE [0:`BUFFER_DEPTH-1];
// -- Puerto de escritura sincrono ------------------------------- >>>>>
always @(posedge clk)
if (write_strobe_din)
REG_FILE[write_address_din] <= write_data_din;
// -- Puerto de lectura asincrono -------------------------------- >>>>>
assign read_data_dout = REG_FILE[read_address_din];
// -- Codigo no sintetizable ------------------------------------- >>>>>
// -- Funciones ---------------------------------------------- >>>>>
// -- Rutina de Inicializacion de Registro --------------- >>>>>
integer rf_index;
initial
for (rf_index = 0; rf_index < `BUFFER_DEPTH; rf_index = rf_index + 1)
REG_FILE[rf_index] = {`CHANNEL_WIDTH{1'b0}};
// -- Funcion de calculo: log2(x) ------------------------ >>>>>
function integer clog2;
input integer depth;
for (clog2=0; depth>0; clog2=clog2+1)
depth = depth >> 1;
endfunction
endmodule |
module
wire srx_pad_i;
wire srx_pad;
reg [7:0] wb_dat_o;
wire [`UART_ADDR_WIDTH-1:0] wb_addr_i;
wire [7:0] wb_dat_i;
reg [3:0] ier;
reg [3:0] iir;
reg [1:0] fcr; /// bits 7 and 6 of fcr. Other bits are ignored
reg [4:0] mcr;
reg [7:0] lcr;
reg [7:0] msr;
reg [15:0] dl; // 32-bit divisor latch
reg [7:0] scratch; // UART scratch register
reg start_dlc; // activate dlc on writing to UART_DL1
reg lsr_mask_d; // delay for lsr_mask condition
reg msi_reset; // reset MSR 4 lower bits indicator
//reg threi_clear; // THRE interrupt clear flag
reg [15:0] dlc; // 32-bit divisor latch counter
reg int_o;
reg [3:0] trigger_level; // trigger level of the receiver FIFO
reg rx_reset;
reg tx_reset;
wire dlab; // divisor latch access bit
wire cts_pad_i, dsr_pad_i, ri_pad_i, dcd_pad_i; // modem status bits
wire loopback; // loopback bit (MCR bit 4)
wire cts, dsr, ri, dcd; // effective signals
wire cts_c, dsr_c, ri_c, dcd_c; // Complement effective signals (considering loopback)
wire rts_pad_o, dtr_pad_o; // modem control outputs
// LSR bits wires and regs
wire [7:0] lsr;
wire lsr0, lsr1, lsr2, lsr3, lsr4, lsr5, lsr6, lsr7;
reg lsr0r, lsr1r, lsr2r, lsr3r, lsr4r, lsr5r, lsr6r, lsr7r;
wire lsr_mask; // lsr_mask
//
// ASSINGS
//
assign lsr[7:0] = { lsr7r, lsr6r, lsr5r, lsr4r, lsr3r, lsr2r, lsr1r, lsr0r };
assign {cts_pad_i, dsr_pad_i, ri_pad_i, dcd_pad_i} = modem_inputs;
assign {cts, dsr, ri, dcd} = ~{cts_pad_i,dsr_pad_i,ri_pad_i,dcd_pad_i};
assign {cts_c, dsr_c, ri_c, dcd_c} = loopback ? {mcr[`UART_MC_RTS],mcr[`UART_MC_DTR],mcr[`UART_MC_OUT1],mcr[`UART_MC_OUT2]}
: {cts_pad_i,dsr_pad_i,ri_pad_i,dcd_pad_i};
assign dlab = lcr[`UART_LC_DL];
assign loopback = mcr[4];
// assign modem outputs
assign rts_pad_o = mcr[`UART_MC_RTS];
assign dtr_pad_o = mcr[`UART_MC_DTR];
// Interrupt signals
wire rls_int; // receiver line status interrupt
wire rda_int; // receiver data available interrupt
wire ti_int; // timeout indicator interrupt
wire thre_int; // transmitter holding register empty interrupt
wire ms_int; // modem status interrupt
// FIFO signals
reg tf_push;
reg rf_pop;
wire [`UART_FIFO_REC_WIDTH-1:0] rf_data_out;
wire rf_error_bit; // an error (parity or framing) is inside the fifo
wire [`UART_FIFO_COUNTER_W-1:0] rf_count;
wire [`UART_FIFO_COUNTER_W-1:0] tf_count;
wire [2:0] tstate;
wire [3:0] rstate;
wire [9:0] counter_t;
wire thre_set_en; // THRE status is delayed one character time when a character is written to fifo.
reg [7:0] block_cnt; // While counter counts, THRE status is blocked (delayed one character cycle)
reg [7:0] block_value; // One character length minus stop bit
// Transmitter Instance
wire serial_out;
uart_transmitter transmitter(clk, wb_rst_i, lcr, tf_push, wb_dat_i, enable, serial_out, tstate, tf_count, tx_reset, lsr_mask);
// Synchronizing and sampling serial RX input
uart_sync_flops i_uart_sync_flops
(
.rst_i (wb_rst_i),
.clk_i (clk),
.stage1_rst_i (1'b0),
.stage1_clk_en_i (1'b1),
.async_dat_i (srx_pad_i),
.sync_dat_o (srx_pad)
);
defparam i_uart_sync_flops.width = 1;
defparam i_uart_sync_flops.init_value = 1'b1;
// handle loopback
wire serial_in = loopback ? serial_out : srx_pad;
assign stx_pad_o = loopback ? 1'b1 : serial_out;
// Receiver Instance
uart_receiver receiver(clk, wb_rst_i, lcr, rf_pop, serial_in, enable,
counter_t, rf_count, rf_data_out, rf_error_bit, rf_overrun, rx_reset, lsr_mask, rstate, rf_push_pulse);
// Asynchronous reading here because the outputs are sampled in uart_wb.v file
always @(dl or dlab or ier or iir or scratch
or lcr or lsr or msr or rf_data_out or wb_addr_i or wb_re_i) // asynchrounous reading
begin
case (wb_addr_i)
`UART_REG_RB : wb_dat_o = dlab ? dl[`UART_DL1] : rf_data_out[10:3];
`UART_REG_IE : wb_dat_o = dlab ? dl[`UART_DL2] : ier;
`UART_REG_II : wb_dat_o = {4'b1100,iir};
`UART_REG_LC : wb_dat_o = lcr;
`UART_REG_LS : wb_dat_o = lsr;
`UART_REG_MS : wb_dat_o = msr;
`UART_REG_SR : wb_dat_o = scratch;
default: wb_dat_o = 8'b0; // ??
endcase // case(wb_addr_i)
end // always @ (dl or dlab or ier or iir or scratch...
// rf_pop signal handling
always @(posedge clk or posedge wb_rst_i)
begin
if (wb_rst_i)
rf_pop <= 0;
else
if (rf_pop) // restore the signal to 0 after one clock cycle
rf_pop <= 0;
else
if (wb_re_i && wb_addr_i == `UART_REG_RB && !dlab)
rf_pop <= 1; // advance read pointer
end
wire lsr_mask_condition;
wire iir_read;
wire msr_read;
wire fifo_read;
wire fifo_write;
assign lsr_mask_condition = (wb_re_i && wb_addr_i == `UART_REG_LS && !dlab);
assign iir_read = (wb_re_i && wb_addr_i == `UART_REG_II && !dlab);
assign msr_read = (wb_re_i && wb_addr_i == `UART_REG_MS && !dlab);
assign fifo_read = (wb_re_i && wb_addr_i == `UART_REG_RB && !dlab);
assign fifo_write = (wb_we_i && wb_addr_i == `UART_REG_TR && !dlab);
// lsr_mask_d delayed signal handling
always @(posedge clk or posedge wb_rst_i)
begin
if (wb_rst_i)
lsr_mask_d <= 0;
else // reset bits in the Line Status Register
lsr_mask_d <= lsr_mask_condition;
end
// lsr_mask is rise detected
assign lsr_mask = lsr_mask_condition && ~lsr_mask_d;
// msi_reset signal handling
always @(posedge clk or posedge wb_rst_i)
begin
if (wb_rst_i)
msi_reset <= 1;
else
if (msi_reset)
msi_reset <= 0;
else
if (msr_read)
msi_reset <= 1; // reset bits in Modem Status Register
end
//
// WRITES AND RESETS //
//
// Line Control Register
always @(posedge clk or posedge wb_rst_i)
if (wb_rst_i)
lcr <= 8'b00000011; // 8n1 setting
else
if (wb_we_i && wb_addr_i==`UART_REG_LC)
lcr <= wb_dat_i;
// Interrupt Enable Register or UART_DL2
always @(posedge clk or posedge wb_rst_i)
if (wb_rst_i)
begin
ier <= 4'b0000; // no interrupts after reset
dl[`UART_DL2] <= 8'b0;
end
else
if (wb_we_i && wb_addr_i==`UART_REG_IE)
if (dlab)
begin
dl[`UART_DL2] <= wb_dat_i;
end
else
ier <= wb_dat_i[3:0]; // ier uses only 4 lsb
// FIFO Control Register and rx_reset, tx_reset signals
always @(posedge clk or posedge wb_rst_i)
if (wb_rst_i) begin
fcr <= 2'b11;
rx_reset <= 0;
tx_reset <= 0;
end else
if (wb_we_i && wb_addr_i==`UART_REG_FC) begin
fcr <= wb_dat_i[7:6];
rx_reset <= wb_dat_i[1];
tx_reset <= wb_dat_i[2];
end else begin
rx_reset <= 0;
tx_reset <= 0;
end
// Modem Control Register
always @(posedge clk or posedge wb_rst_i)
if (wb_rst_i)
mcr <= 5'b0;
else
if (wb_we_i && wb_addr_i==`UART_REG_MC)
mcr <= wb_dat_i[4:0];
// Scratch register
// Line Control Register
always @(posedge clk or posedge wb_rst_i)
if (wb_rst_i)
scratch <= 0; // 8n1 setting
else
if (wb_we_i && wb_addr_i==`UART_REG_SR)
scratch <= wb_dat_i;
// TX_FIFO or UART_DL1
always @(posedge clk or posedge wb_rst_i)
if (wb_rst_i)
begin
dl[`UART_DL1] <= 8'b0;
tf_push <= 1'b0;
start_dlc <= 1'b0;
end
else
if (wb_we_i && wb_addr_i==`UART_REG_TR)
if (dlab)
begin
dl[`UART_DL1] <= wb_dat_i;
start_dlc <= 1'b1; // enable DL counter
tf_push <= 1'b0;
end
else
begin
tf_push <= 1'b1;
start_dlc <= 1'b0;
end // else: !if(dlab)
else
begin
start_dlc <= 1'b0;
tf_push <= 1'b0;
end // else: !if(dlab)
// Receiver FIFO trigger level selection logic (asynchronous mux)
always @(fcr)
case (fcr[`UART_FC_TL])
2'b00 : trigger_level = 1;
2'b01 : trigger_level = 4;
2'b10 : trigger_level = 8;
2'b11 : trigger_level = 14;
endcase // case(fcr[`UART_FC_TL])
//
// STATUS REGISTERS //
//
// Modem Status Register
reg [3:0] delayed_modem_signals;
always @(posedge clk or posedge wb_rst_i)
begin
if (wb_rst_i)
begin
msr <= 0;
delayed_modem_signals[3:0] <= 0;
end
else begin
msr[`UART_MS_DDCD:`UART_MS_DCTS] <= msi_reset ? 4'b0 :
msr[`UART_MS_DDCD:`UART_MS_DCTS] | ({dcd, ri, dsr, cts} ^ delayed_modem_signals[3:0]);
msr[`UART_MS_CDCD:`UART_MS_CCTS] <= {dcd_c, ri_c, dsr_c, cts_c};
delayed_modem_signals[3:0] <= {dcd, ri, dsr, cts};
end
end
// Line Status Register
// activation conditions
assign lsr0 = (rf_count==0 && rf_push_pulse); // data in receiver fifo available set condition
assign lsr1 = rf_overrun; // Receiver overrun error
assign lsr2 = rf_data_out[1]; // parity error bit
assign lsr3 = rf_data_out[0]; // framing error bit
assign lsr4 = rf_data_out[2]; // break error in the character
assign lsr5 = (tf_count==5'b0 && thre_set_en); // transmitter fifo is empty
assign lsr6 = (tf_count==5'b0 && thre_set_en && (tstate == /*`S_IDLE */ 0)); // transmitter empty
assign lsr7 = rf_error_bit | rf_overrun;
// lsr bit0 (receiver data available)
reg lsr0_d;
always @(posedge clk or posedge wb_rst_i)
if (wb_rst_i) lsr0_d <= 0;
else lsr0_d <= lsr0;
always @(posedge clk or posedge wb_rst_i)
if (wb_rst_i) lsr0r <= 0;
else lsr0r <= (rf_count==1 && rf_pop && !rf_push_pulse || rx_reset) ? 0 : // deassert condition
lsr0r || (lsr0 && ~lsr0_d); // set on rise of lsr0 and keep asserted until deasserted
// lsr bit 1 (receiver overrun)
reg lsr1_d; // delayed
always @(posedge clk or posedge wb_rst_i)
if (wb_rst_i) lsr1_d <= 0;
else lsr1_d <= lsr1;
always @(posedge clk or posedge wb_rst_i)
if (wb_rst_i) lsr1r <= 0;
else lsr1r <= lsr_mask ? 0 : lsr1r || (lsr1 && ~lsr1_d); // set on rise
// lsr bit 2 (parity error)
reg lsr2_d; // delayed
always @(posedge clk or posedge wb_rst_i)
if (wb_rst_i) lsr2_d <= 0;
else lsr2_d <= lsr2;
always @(posedge clk or posedge wb_rst_i)
if (wb_rst_i) lsr2r <= 0;
else lsr2r <= lsr_mask ? 0 : lsr2r || (lsr2 && ~lsr2_d); // set on rise
// lsr bit 3 (framing error)
reg lsr3_d; // delayed
always @(posedge clk or posedge wb_rst_i)
if (wb_rst_i) lsr3_d <= 0;
else lsr3_d <= lsr3;
always @(posedge clk or posedge wb_rst_i)
if (wb_rst_i) lsr3r <= 0;
else lsr3r <= lsr_mask ? 0 : lsr3r || (lsr3 && ~lsr3_d); // set on rise
// lsr bit 4 (break indicator)
reg lsr4_d; // delayed
always @(posedge clk or posedge wb_rst_i)
if (wb_rst_i) lsr4_d <= 0;
else lsr4_d <= lsr4;
always @(posedge clk or posedge wb_rst_i)
if (wb_rst_i) lsr4r <= 0;
else lsr4r <= lsr_mask ? 0 : lsr4r || (lsr4 && ~lsr4_d);
// lsr bit 5 (transmitter fifo is empty)
reg lsr5_d;
always @(posedge clk or posedge wb_rst_i)
if (wb_rst_i) lsr5_d <= 1;
else lsr5_d <= lsr5;
always @(posedge clk or posedge wb_rst_i)
if (wb_rst_i) lsr5r <= 1;
else lsr5r <= (fifo_write) ? 0 : lsr5r || (lsr5 && ~lsr5_d);
// lsr bit 6 (transmitter empty indicator)
reg lsr6_d;
always @(posedge clk or posedge wb_rst_i)
if (wb_rst_i) lsr6_d <= 1;
else lsr6_d <= lsr6;
always @(posedge clk or posedge wb_rst_i)
if (wb_rst_i) lsr6r <= 1;
else lsr6r <= (fifo_write) ? 0 : lsr6r || (lsr6 && ~lsr6_d);
// lsr bit 7 (error in fifo)
reg lsr7_d;
always @(posedge clk or posedge wb_rst_i)
if (wb_rst_i) lsr7_d <= 0;
else lsr7_d <= lsr7;
always @(posedge clk or posedge wb_rst_i)
if (wb_rst_i) lsr7r <= 0;
else lsr7r <= lsr_mask ? 0 : lsr7r || (lsr7 && ~lsr7_d);
// Frequency divider
always @(posedge clk or posedge wb_rst_i)
begin
if (wb_rst_i)
dlc <= 0;
else
if (start_dlc | ~ (|dlc))
dlc <= dl - 1; // preset counter
else
dlc <= dlc - 1; // decrement counter
end
// Enable signal generation logic
always @(posedge clk or posedge wb_rst_i)
begin
if (wb_rst_i)
enable <= 1'b0;
else
if (|dl & ~(|dlc)) // dl>0 & dlc==0
enable <= 1'b1;
else
enable <= 1'b0;
end
// Delaying THRE status for one character cycle after a character is written to an empty fifo.
always @(lcr)
case (lcr[3:0])
4'b0000 : block_value = 95; // 6 bits
4'b0100 : block_value = 103; // 6.5 bits
4'b0001, 4'b1000 : block_value = 111; // 7 bits
4'b1100 : block_value = 119; // 7.5 bits
4'b0010, 4'b0101, 4'b1001 : block_value = 127; // 8 bits
4'b0011, 4'b0110, 4'b1010, 4'b1101 : block_value = 143; // 9 bits
4'b0111, 4'b1011, 4'b1110 : block_value = 159; // 10 bits
4'b1111 : block_value = 175; // 11 bits
endcase // case(lcr[3:0])
// Counting time of one character minus stop bit
always @(posedge clk or posedge wb_rst_i)
begin
if (wb_rst_i)
block_cnt <= 8'd0;
else
if(lsr5r & fifo_write) // THRE bit set & write to fifo occured
block_cnt <= block_value;
else
if (enable & block_cnt != 8'b0) // only work on enable times
block_cnt <= block_cnt - 1; // decrement break counter
end // always of break condition detection
// Generating THRE status enable signal
assign thre_set_en = ~(|block_cnt);
//
// INTERRUPT LOGIC
//
assign rls_int = ier[`UART_IE_RLS] && (lsr[`UART_LS_OE] || lsr[`UART_LS_PE] || lsr[`UART_LS_FE] || lsr[`UART_LS_BI]);
assign rda_int = ier[`UART_IE_RDA] && (rf_count >= {1'b0,trigger_level});
assign thre_int = ier[`UART_IE_THRE] && lsr[`UART_LS_TFE];
assign ms_int = ier[`UART_IE_MS] && (| msr[3:0]);
assign ti_int = ier[`UART_IE_RDA] && (counter_t == 10'b0) && (|rf_count);
reg rls_int_d;
reg thre_int_d;
reg ms_int_d;
reg ti_int_d;
reg rda_int_d;
// delay lines
always @(posedge clk or posedge wb_rst_i)
if (wb_rst_i) rls_int_d <= 0;
else rls_int_d <= rls_int;
always @(posedge clk or posedge wb_rst_i)
if (wb_rst_i) rda_int_d <= 0;
else rda_int_d <= rda_int;
always @(posedge clk or posedge wb_rst_i)
if (wb_rst_i) thre_int_d <= 0;
else thre_int_d <= thre_int;
always @(posedge clk or posedge wb_rst_i)
if (wb_rst_i) ms_int_d <= 0;
else ms_int_d <= ms_int;
always @(posedge clk or posedge wb_rst_i)
if (wb_rst_i) ti_int_d <= 0;
else ti_int_d <= ti_int;
// rise detection signals
wire rls_int_rise;
wire thre_int_rise;
wire ms_int_rise;
wire ti_int_rise;
wire rda_int_rise;
assign rda_int_rise = rda_int & ~rda_int_d;
assign rls_int_rise = rls_int & ~rls_int_d;
assign thre_int_rise = thre_int & ~thre_int_d;
assign ms_int_rise = ms_int & ~ms_int_d;
assign ti_int_rise = ti_int & ~ti_int_d;
// interrupt pending flags
reg rls_int_pnd;
reg rda_int_pnd;
reg thre_int_pnd;
reg ms_int_pnd;
reg ti_int_pnd;
// interrupt pending flags assignments
always @(posedge clk or posedge wb_rst_i)
if (wb_rst_i) rls_int_pnd <= 0;
else
rls_int_pnd <= lsr_mask ? 0 : // reset condition
rls_int_rise ? 1 : // latch condition
rls_int_pnd && ier[`UART_IE_RLS]; // default operation: remove if masked
always @(posedge clk or posedge wb_rst_i)
if (wb_rst_i) rda_int_pnd <= 0;
else
rda_int_pnd <= ((rf_count == {1'b0,trigger_level}) && fifo_read) ? 0 : // reset condition
rda_int_rise ? 1 : // latch condition
rda_int_pnd && ier[`UART_IE_RDA]; // default operation: remove if masked
always @(posedge clk or posedge wb_rst_i)
if (wb_rst_i) thre_int_pnd <= 0;
else
thre_int_pnd <= fifo_write || (iir_read & ~iir[`UART_II_IP] & iir[`UART_II_II] == `UART_II_THRE)? 0 :
thre_int_rise ? 1 :
thre_int_pnd && ier[`UART_IE_THRE];
always @(posedge clk or posedge wb_rst_i)
if (wb_rst_i) ms_int_pnd <= 0;
else
ms_int_pnd <= msr_read ? 0 :
ms_int_rise ? 1 :
ms_int_pnd && ier[`UART_IE_MS];
always @(posedge clk or posedge wb_rst_i)
if (wb_rst_i) ti_int_pnd <= 0;
else
ti_int_pnd <= fifo_read ? 0 :
ti_int_rise ? 1 :
ti_int_pnd && ier[`UART_IE_RDA];
// end of pending flags
// INT_O logic
always @(posedge clk or posedge wb_rst_i)
begin
if (wb_rst_i)
int_o <= 1'b0;
else
int_o <=
rls_int_pnd ? ~lsr_mask :
rda_int_pnd ? 1 :
ti_int_pnd ? ~fifo_read :
thre_int_pnd ? !(fifo_write & iir_read) :
ms_int_pnd ? ~msr_read :
0; // if no interrupt are pending
end
// Interrupt Identification register
always @(posedge clk or posedge wb_rst_i)
begin
if (wb_rst_i)
iir <= 1;
else
if (rls_int_pnd) // interrupt is pending
begin
iir[`UART_II_II] <= `UART_II_RLS; // set identification register to correct value
iir[`UART_II_IP] <= 1'b0; // and clear the IIR bit 0 (interrupt pending)
end else // the sequence of conditions determines priority of interrupt identification
if (rda_int)
begin
iir[`UART_II_II] <= `UART_II_RDA;
iir[`UART_II_IP] <= 1'b0;
end
else if (ti_int_pnd)
begin
iir[`UART_II_II] <= `UART_II_TI;
iir[`UART_II_IP] <= 1'b0;
end
else if (thre_int_pnd)
begin
iir[`UART_II_II] <= `UART_II_THRE;
iir[`UART_II_IP] <= 1'b0;
end
else if (ms_int_pnd)
begin
iir[`UART_II_II] <= `UART_II_MS;
iir[`UART_II_IP] <= 1'b0;
end else // no interrupt is pending
begin
iir[`UART_II_II] <= 0;
iir[`UART_II_IP] <= 1'b1;
end
end
endmodule |
module fifo_128x128a (
aclr,
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
rdempty,
rdusedw,
wrempty,
wrusedw);
input aclr;
input [127:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [127:0] q;
output rdempty;
output [6:0] rdusedw;
output wrempty;
output [6:0] wrusedw;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire sub_wire0;
wire [127:0] sub_wire1;
wire sub_wire2;
wire [6:0] sub_wire3;
wire [6:0] sub_wire4;
wire wrempty = sub_wire0;
wire [127:0] q = sub_wire1[127:0];
wire rdempty = sub_wire2;
wire [6:0] wrusedw = sub_wire3[6:0];
wire [6:0] rdusedw = sub_wire4[6:0];
dcfifo dcfifo_component (
.rdclk (rdclk),
.wrclk (wrclk),
.wrreq (wrreq),
.aclr (aclr),
.data (data),
.rdreq (rdreq),
.wrempty (sub_wire0),
.q (sub_wire1),
.rdempty (sub_wire2),
.wrusedw (sub_wire3),
.rdusedw (sub_wire4),
.rdfull (),
.wrfull ());
defparam
dcfifo_component.intended_device_family = "Arria II GX",
dcfifo_component.lpm_numwords = 128,
dcfifo_component.lpm_showahead = "ON",
dcfifo_component.lpm_type = "dcfifo",
dcfifo_component.lpm_width = 128,
dcfifo_component.lpm_widthu = 7,
dcfifo_component.overflow_checking = "ON",
dcfifo_component.rdsync_delaypipe = 4,
dcfifo_component.underflow_checking = "ON",
dcfifo_component.use_eab = "ON",
dcfifo_component.write_aclr_synch = "ON",
dcfifo_component.wrsync_delaypipe = 4;
endmodule |
module sky130_fd_sc_hd__udp_pwrgood_pp$G (
//# {{data|Data Signals}}
input UDP_IN ,
output UDP_OUT,
//# {{power|Power}}
input VGND
);
endmodule |
module m00_couplers_imp_1TEAG88
(M_ACLK,
M_ARESETN,
M_AXI_araddr,
M_AXI_arburst,
M_AXI_arcache,
M_AXI_arid,
M_AXI_arlen,
M_AXI_arlock,
M_AXI_arprot,
M_AXI_arqos,
M_AXI_arready,
M_AXI_arsize,
M_AXI_arvalid,
M_AXI_awaddr,
M_AXI_awburst,
M_AXI_awcache,
M_AXI_awid,
M_AXI_awlen,
M_AXI_awlock,
M_AXI_awprot,
M_AXI_awqos,
M_AXI_awready,
M_AXI_awsize,
M_AXI_awvalid,
M_AXI_bid,
M_AXI_bready,
M_AXI_bresp,
M_AXI_bvalid,
M_AXI_rdata,
M_AXI_rid,
M_AXI_rlast,
M_AXI_rready,
M_AXI_rresp,
M_AXI_rvalid,
M_AXI_wdata,
M_AXI_wid,
M_AXI_wlast,
M_AXI_wready,
M_AXI_wstrb,
M_AXI_wvalid,
S_ACLK,
S_ARESETN,
S_AXI_araddr,
S_AXI_arburst,
S_AXI_arcache,
S_AXI_arid,
S_AXI_arlen,
S_AXI_arlock,
S_AXI_arprot,
S_AXI_arqos,
S_AXI_arready,
S_AXI_arregion,
S_AXI_arsize,
S_AXI_arvalid,
S_AXI_awaddr,
S_AXI_awburst,
S_AXI_awcache,
S_AXI_awid,
S_AXI_awlen,
S_AXI_awlock,
S_AXI_awprot,
S_AXI_awqos,
S_AXI_awready,
S_AXI_awregion,
S_AXI_awsize,
S_AXI_awvalid,
S_AXI_bid,
S_AXI_bready,
S_AXI_bresp,
S_AXI_bvalid,
S_AXI_rdata,
S_AXI_rid,
S_AXI_rlast,
S_AXI_rready,
S_AXI_rresp,
S_AXI_rvalid,
S_AXI_wdata,
S_AXI_wlast,
S_AXI_wready,
S_AXI_wstrb,
S_AXI_wvalid);
input M_ACLK;
input [0:0]M_ARESETN;
output [31:0]M_AXI_araddr;
output [1:0]M_AXI_arburst;
output [3:0]M_AXI_arcache;
output [0:0]M_AXI_arid;
output [3:0]M_AXI_arlen;
output [1:0]M_AXI_arlock;
output [2:0]M_AXI_arprot;
output [3:0]M_AXI_arqos;
input M_AXI_arready;
output [2:0]M_AXI_arsize;
output M_AXI_arvalid;
output [31:0]M_AXI_awaddr;
output [1:0]M_AXI_awburst;
output [3:0]M_AXI_awcache;
output [0:0]M_AXI_awid;
output [3:0]M_AXI_awlen;
output [1:0]M_AXI_awlock;
output [2:0]M_AXI_awprot;
output [3:0]M_AXI_awqos;
input M_AXI_awready;
output [2:0]M_AXI_awsize;
output M_AXI_awvalid;
input [0:0]M_AXI_bid;
output M_AXI_bready;
input [1:0]M_AXI_bresp;
input M_AXI_bvalid;
input [63:0]M_AXI_rdata;
input [0:0]M_AXI_rid;
input M_AXI_rlast;
output M_AXI_rready;
input [1:0]M_AXI_rresp;
input M_AXI_rvalid;
output [63:0]M_AXI_wdata;
output [0:0]M_AXI_wid;
output M_AXI_wlast;
input M_AXI_wready;
output [7:0]M_AXI_wstrb;
output M_AXI_wvalid;
input S_ACLK;
input [0:0]S_ARESETN;
input [31:0]S_AXI_araddr;
input [1:0]S_AXI_arburst;
input [3:0]S_AXI_arcache;
input [0:0]S_AXI_arid;
input [7:0]S_AXI_arlen;
input [0:0]S_AXI_arlock;
input [2:0]S_AXI_arprot;
input [3:0]S_AXI_arqos;
output S_AXI_arready;
input [3:0]S_AXI_arregion;
input [2:0]S_AXI_arsize;
input S_AXI_arvalid;
input [31:0]S_AXI_awaddr;
input [1:0]S_AXI_awburst;
input [3:0]S_AXI_awcache;
input [0:0]S_AXI_awid;
input [7:0]S_AXI_awlen;
input [0:0]S_AXI_awlock;
input [2:0]S_AXI_awprot;
input [3:0]S_AXI_awqos;
output S_AXI_awready;
input [3:0]S_AXI_awregion;
input [2:0]S_AXI_awsize;
input S_AXI_awvalid;
output [0:0]S_AXI_bid;
input S_AXI_bready;
output [1:0]S_AXI_bresp;
output S_AXI_bvalid;
output [63:0]S_AXI_rdata;
output [0:0]S_AXI_rid;
output S_AXI_rlast;
input S_AXI_rready;
output [1:0]S_AXI_rresp;
output S_AXI_rvalid;
input [63:0]S_AXI_wdata;
input S_AXI_wlast;
output S_AXI_wready;
input [7:0]S_AXI_wstrb;
input S_AXI_wvalid;
wire S_ACLK_1;
wire [0:0]S_ARESETN_1;
wire [31:0]auto_pc_to_m00_couplers_ARADDR;
wire [1:0]auto_pc_to_m00_couplers_ARBURST;
wire [3:0]auto_pc_to_m00_couplers_ARCACHE;
wire [0:0]auto_pc_to_m00_couplers_ARID;
wire [3:0]auto_pc_to_m00_couplers_ARLEN;
wire [1:0]auto_pc_to_m00_couplers_ARLOCK;
wire [2:0]auto_pc_to_m00_couplers_ARPROT;
wire [3:0]auto_pc_to_m00_couplers_ARQOS;
wire auto_pc_to_m00_couplers_ARREADY;
wire [2:0]auto_pc_to_m00_couplers_ARSIZE;
wire auto_pc_to_m00_couplers_ARVALID;
wire [31:0]auto_pc_to_m00_couplers_AWADDR;
wire [1:0]auto_pc_to_m00_couplers_AWBURST;
wire [3:0]auto_pc_to_m00_couplers_AWCACHE;
wire [0:0]auto_pc_to_m00_couplers_AWID;
wire [3:0]auto_pc_to_m00_couplers_AWLEN;
wire [1:0]auto_pc_to_m00_couplers_AWLOCK;
wire [2:0]auto_pc_to_m00_couplers_AWPROT;
wire [3:0]auto_pc_to_m00_couplers_AWQOS;
wire auto_pc_to_m00_couplers_AWREADY;
wire [2:0]auto_pc_to_m00_couplers_AWSIZE;
wire auto_pc_to_m00_couplers_AWVALID;
wire [0:0]auto_pc_to_m00_couplers_BID;
wire auto_pc_to_m00_couplers_BREADY;
wire [1:0]auto_pc_to_m00_couplers_BRESP;
wire auto_pc_to_m00_couplers_BVALID;
wire [63:0]auto_pc_to_m00_couplers_RDATA;
wire [0:0]auto_pc_to_m00_couplers_RID;
wire auto_pc_to_m00_couplers_RLAST;
wire auto_pc_to_m00_couplers_RREADY;
wire [1:0]auto_pc_to_m00_couplers_RRESP;
wire auto_pc_to_m00_couplers_RVALID;
wire [63:0]auto_pc_to_m00_couplers_WDATA;
wire [0:0]auto_pc_to_m00_couplers_WID;
wire auto_pc_to_m00_couplers_WLAST;
wire auto_pc_to_m00_couplers_WREADY;
wire [7:0]auto_pc_to_m00_couplers_WSTRB;
wire auto_pc_to_m00_couplers_WVALID;
wire [31:0]m00_couplers_to_auto_pc_ARADDR;
wire [1:0]m00_couplers_to_auto_pc_ARBURST;
wire [3:0]m00_couplers_to_auto_pc_ARCACHE;
wire [0:0]m00_couplers_to_auto_pc_ARID;
wire [7:0]m00_couplers_to_auto_pc_ARLEN;
wire [0:0]m00_couplers_to_auto_pc_ARLOCK;
wire [2:0]m00_couplers_to_auto_pc_ARPROT;
wire [3:0]m00_couplers_to_auto_pc_ARQOS;
wire m00_couplers_to_auto_pc_ARREADY;
wire [3:0]m00_couplers_to_auto_pc_ARREGION;
wire [2:0]m00_couplers_to_auto_pc_ARSIZE;
wire m00_couplers_to_auto_pc_ARVALID;
wire [31:0]m00_couplers_to_auto_pc_AWADDR;
wire [1:0]m00_couplers_to_auto_pc_AWBURST;
wire [3:0]m00_couplers_to_auto_pc_AWCACHE;
wire [0:0]m00_couplers_to_auto_pc_AWID;
wire [7:0]m00_couplers_to_auto_pc_AWLEN;
wire [0:0]m00_couplers_to_auto_pc_AWLOCK;
wire [2:0]m00_couplers_to_auto_pc_AWPROT;
wire [3:0]m00_couplers_to_auto_pc_AWQOS;
wire m00_couplers_to_auto_pc_AWREADY;
wire [3:0]m00_couplers_to_auto_pc_AWREGION;
wire [2:0]m00_couplers_to_auto_pc_AWSIZE;
wire m00_couplers_to_auto_pc_AWVALID;
wire [0:0]m00_couplers_to_auto_pc_BID;
wire m00_couplers_to_auto_pc_BREADY;
wire [1:0]m00_couplers_to_auto_pc_BRESP;
wire m00_couplers_to_auto_pc_BVALID;
wire [63:0]m00_couplers_to_auto_pc_RDATA;
wire [0:0]m00_couplers_to_auto_pc_RID;
wire m00_couplers_to_auto_pc_RLAST;
wire m00_couplers_to_auto_pc_RREADY;
wire [1:0]m00_couplers_to_auto_pc_RRESP;
wire m00_couplers_to_auto_pc_RVALID;
wire [63:0]m00_couplers_to_auto_pc_WDATA;
wire m00_couplers_to_auto_pc_WLAST;
wire m00_couplers_to_auto_pc_WREADY;
wire [7:0]m00_couplers_to_auto_pc_WSTRB;
wire m00_couplers_to_auto_pc_WVALID;
assign M_AXI_araddr[31:0] = auto_pc_to_m00_couplers_ARADDR;
assign M_AXI_arburst[1:0] = auto_pc_to_m00_couplers_ARBURST;
assign M_AXI_arcache[3:0] = auto_pc_to_m00_couplers_ARCACHE;
assign M_AXI_arid[0] = auto_pc_to_m00_couplers_ARID;
assign M_AXI_arlen[3:0] = auto_pc_to_m00_couplers_ARLEN;
assign M_AXI_arlock[1:0] = auto_pc_to_m00_couplers_ARLOCK;
assign M_AXI_arprot[2:0] = auto_pc_to_m00_couplers_ARPROT;
assign M_AXI_arqos[3:0] = auto_pc_to_m00_couplers_ARQOS;
assign M_AXI_arsize[2:0] = auto_pc_to_m00_couplers_ARSIZE;
assign M_AXI_arvalid = auto_pc_to_m00_couplers_ARVALID;
assign M_AXI_awaddr[31:0] = auto_pc_to_m00_couplers_AWADDR;
assign M_AXI_awburst[1:0] = auto_pc_to_m00_couplers_AWBURST;
assign M_AXI_awcache[3:0] = auto_pc_to_m00_couplers_AWCACHE;
assign M_AXI_awid[0] = auto_pc_to_m00_couplers_AWID;
assign M_AXI_awlen[3:0] = auto_pc_to_m00_couplers_AWLEN;
assign M_AXI_awlock[1:0] = auto_pc_to_m00_couplers_AWLOCK;
assign M_AXI_awprot[2:0] = auto_pc_to_m00_couplers_AWPROT;
assign M_AXI_awqos[3:0] = auto_pc_to_m00_couplers_AWQOS;
assign M_AXI_awsize[2:0] = auto_pc_to_m00_couplers_AWSIZE;
assign M_AXI_awvalid = auto_pc_to_m00_couplers_AWVALID;
assign M_AXI_bready = auto_pc_to_m00_couplers_BREADY;
assign M_AXI_rready = auto_pc_to_m00_couplers_RREADY;
assign M_AXI_wdata[63:0] = auto_pc_to_m00_couplers_WDATA;
assign M_AXI_wid[0] = auto_pc_to_m00_couplers_WID;
assign M_AXI_wlast = auto_pc_to_m00_couplers_WLAST;
assign M_AXI_wstrb[7:0] = auto_pc_to_m00_couplers_WSTRB;
assign M_AXI_wvalid = auto_pc_to_m00_couplers_WVALID;
assign S_ACLK_1 = S_ACLK;
assign S_ARESETN_1 = S_ARESETN[0];
assign S_AXI_arready = m00_couplers_to_auto_pc_ARREADY;
assign S_AXI_awready = m00_couplers_to_auto_pc_AWREADY;
assign S_AXI_bid[0] = m00_couplers_to_auto_pc_BID;
assign S_AXI_bresp[1:0] = m00_couplers_to_auto_pc_BRESP;
assign S_AXI_bvalid = m00_couplers_to_auto_pc_BVALID;
assign S_AXI_rdata[63:0] = m00_couplers_to_auto_pc_RDATA;
assign S_AXI_rid[0] = m00_couplers_to_auto_pc_RID;
assign S_AXI_rlast = m00_couplers_to_auto_pc_RLAST;
assign S_AXI_rresp[1:0] = m00_couplers_to_auto_pc_RRESP;
assign S_AXI_rvalid = m00_couplers_to_auto_pc_RVALID;
assign S_AXI_wready = m00_couplers_to_auto_pc_WREADY;
assign auto_pc_to_m00_couplers_ARREADY = M_AXI_arready;
assign auto_pc_to_m00_couplers_AWREADY = M_AXI_awready;
assign auto_pc_to_m00_couplers_BID = M_AXI_bid[0];
assign auto_pc_to_m00_couplers_BRESP = M_AXI_bresp[1:0];
assign auto_pc_to_m00_couplers_BVALID = M_AXI_bvalid;
assign auto_pc_to_m00_couplers_RDATA = M_AXI_rdata[63:0];
assign auto_pc_to_m00_couplers_RID = M_AXI_rid[0];
assign auto_pc_to_m00_couplers_RLAST = M_AXI_rlast;
assign auto_pc_to_m00_couplers_RRESP = M_AXI_rresp[1:0];
assign auto_pc_to_m00_couplers_RVALID = M_AXI_rvalid;
assign auto_pc_to_m00_couplers_WREADY = M_AXI_wready;
assign m00_couplers_to_auto_pc_ARADDR = S_AXI_araddr[31:0];
assign m00_couplers_to_auto_pc_ARBURST = S_AXI_arburst[1:0];
assign m00_couplers_to_auto_pc_ARCACHE = S_AXI_arcache[3:0];
assign m00_couplers_to_auto_pc_ARID = S_AXI_arid[0];
assign m00_couplers_to_auto_pc_ARLEN = S_AXI_arlen[7:0];
assign m00_couplers_to_auto_pc_ARLOCK = S_AXI_arlock[0];
assign m00_couplers_to_auto_pc_ARPROT = S_AXI_arprot[2:0];
assign m00_couplers_to_auto_pc_ARQOS = S_AXI_arqos[3:0];
assign m00_couplers_to_auto_pc_ARREGION = S_AXI_arregion[3:0];
assign m00_couplers_to_auto_pc_ARSIZE = S_AXI_arsize[2:0];
assign m00_couplers_to_auto_pc_ARVALID = S_AXI_arvalid;
assign m00_couplers_to_auto_pc_AWADDR = S_AXI_awaddr[31:0];
assign m00_couplers_to_auto_pc_AWBURST = S_AXI_awburst[1:0];
assign m00_couplers_to_auto_pc_AWCACHE = S_AXI_awcache[3:0];
assign m00_couplers_to_auto_pc_AWID = S_AXI_awid[0];
assign m00_couplers_to_auto_pc_AWLEN = S_AXI_awlen[7:0];
assign m00_couplers_to_auto_pc_AWLOCK = S_AXI_awlock[0];
assign m00_couplers_to_auto_pc_AWPROT = S_AXI_awprot[2:0];
assign m00_couplers_to_auto_pc_AWQOS = S_AXI_awqos[3:0];
assign m00_couplers_to_auto_pc_AWREGION = S_AXI_awregion[3:0];
assign m00_couplers_to_auto_pc_AWSIZE = S_AXI_awsize[2:0];
assign m00_couplers_to_auto_pc_AWVALID = S_AXI_awvalid;
assign m00_couplers_to_auto_pc_BREADY = S_AXI_bready;
assign m00_couplers_to_auto_pc_RREADY = S_AXI_rready;
assign m00_couplers_to_auto_pc_WDATA = S_AXI_wdata[63:0];
assign m00_couplers_to_auto_pc_WLAST = S_AXI_wlast;
assign m00_couplers_to_auto_pc_WSTRB = S_AXI_wstrb[7:0];
assign m00_couplers_to_auto_pc_WVALID = S_AXI_wvalid;
system_auto_pc_1 auto_pc
(.aclk(S_ACLK_1),
.aresetn(S_ARESETN_1),
.m_axi_araddr(auto_pc_to_m00_couplers_ARADDR),
.m_axi_arburst(auto_pc_to_m00_couplers_ARBURST),
.m_axi_arcache(auto_pc_to_m00_couplers_ARCACHE),
.m_axi_arid(auto_pc_to_m00_couplers_ARID),
.m_axi_arlen(auto_pc_to_m00_couplers_ARLEN),
.m_axi_arlock(auto_pc_to_m00_couplers_ARLOCK),
.m_axi_arprot(auto_pc_to_m00_couplers_ARPROT),
.m_axi_arqos(auto_pc_to_m00_couplers_ARQOS),
.m_axi_arready(auto_pc_to_m00_couplers_ARREADY),
.m_axi_arsize(auto_pc_to_m00_couplers_ARSIZE),
.m_axi_arvalid(auto_pc_to_m00_couplers_ARVALID),
.m_axi_awaddr(auto_pc_to_m00_couplers_AWADDR),
.m_axi_awburst(auto_pc_to_m00_couplers_AWBURST),
.m_axi_awcache(auto_pc_to_m00_couplers_AWCACHE),
.m_axi_awid(auto_pc_to_m00_couplers_AWID),
.m_axi_awlen(auto_pc_to_m00_couplers_AWLEN),
.m_axi_awlock(auto_pc_to_m00_couplers_AWLOCK),
.m_axi_awprot(auto_pc_to_m00_couplers_AWPROT),
.m_axi_awqos(auto_pc_to_m00_couplers_AWQOS),
.m_axi_awready(auto_pc_to_m00_couplers_AWREADY),
.m_axi_awsize(auto_pc_to_m00_couplers_AWSIZE),
.m_axi_awvalid(auto_pc_to_m00_couplers_AWVALID),
.m_axi_bid(auto_pc_to_m00_couplers_BID),
.m_axi_bready(auto_pc_to_m00_couplers_BREADY),
.m_axi_bresp(auto_pc_to_m00_couplers_BRESP),
.m_axi_bvalid(auto_pc_to_m00_couplers_BVALID),
.m_axi_rdata(auto_pc_to_m00_couplers_RDATA),
.m_axi_rid(auto_pc_to_m00_couplers_RID),
.m_axi_rlast(auto_pc_to_m00_couplers_RLAST),
.m_axi_rready(auto_pc_to_m00_couplers_RREADY),
.m_axi_rresp(auto_pc_to_m00_couplers_RRESP),
.m_axi_rvalid(auto_pc_to_m00_couplers_RVALID),
.m_axi_wdata(auto_pc_to_m00_couplers_WDATA),
.m_axi_wid(auto_pc_to_m00_couplers_WID),
.m_axi_wlast(auto_pc_to_m00_couplers_WLAST),
.m_axi_wready(auto_pc_to_m00_couplers_WREADY),
.m_axi_wstrb(auto_pc_to_m00_couplers_WSTRB),
.m_axi_wvalid(auto_pc_to_m00_couplers_WVALID),
.s_axi_araddr(m00_couplers_to_auto_pc_ARADDR),
.s_axi_arburst(m00_couplers_to_auto_pc_ARBURST),
.s_axi_arcache(m00_couplers_to_auto_pc_ARCACHE),
.s_axi_arid(m00_couplers_to_auto_pc_ARID),
.s_axi_arlen(m00_couplers_to_auto_pc_ARLEN),
.s_axi_arlock(m00_couplers_to_auto_pc_ARLOCK),
.s_axi_arprot(m00_couplers_to_auto_pc_ARPROT),
.s_axi_arqos(m00_couplers_to_auto_pc_ARQOS),
.s_axi_arready(m00_couplers_to_auto_pc_ARREADY),
.s_axi_arregion(m00_couplers_to_auto_pc_ARREGION),
.s_axi_arsize(m00_couplers_to_auto_pc_ARSIZE),
.s_axi_arvalid(m00_couplers_to_auto_pc_ARVALID),
.s_axi_awaddr(m00_couplers_to_auto_pc_AWADDR),
.s_axi_awburst(m00_couplers_to_auto_pc_AWBURST),
.s_axi_awcache(m00_couplers_to_auto_pc_AWCACHE),
.s_axi_awid(m00_couplers_to_auto_pc_AWID),
.s_axi_awlen(m00_couplers_to_auto_pc_AWLEN),
.s_axi_awlock(m00_couplers_to_auto_pc_AWLOCK),
.s_axi_awprot(m00_couplers_to_auto_pc_AWPROT),
.s_axi_awqos(m00_couplers_to_auto_pc_AWQOS),
.s_axi_awready(m00_couplers_to_auto_pc_AWREADY),
.s_axi_awregion(m00_couplers_to_auto_pc_AWREGION),
.s_axi_awsize(m00_couplers_to_auto_pc_AWSIZE),
.s_axi_awvalid(m00_couplers_to_auto_pc_AWVALID),
.s_axi_bid(m00_couplers_to_auto_pc_BID),
.s_axi_bready(m00_couplers_to_auto_pc_BREADY),
.s_axi_bresp(m00_couplers_to_auto_pc_BRESP),
.s_axi_bvalid(m00_couplers_to_auto_pc_BVALID),
.s_axi_rdata(m00_couplers_to_auto_pc_RDATA),
.s_axi_rid(m00_couplers_to_auto_pc_RID),
.s_axi_rlast(m00_couplers_to_auto_pc_RLAST),
.s_axi_rready(m00_couplers_to_auto_pc_RREADY),
.s_axi_rresp(m00_couplers_to_auto_pc_RRESP),
.s_axi_rvalid(m00_couplers_to_auto_pc_RVALID),
.s_axi_wdata(m00_couplers_to_auto_pc_WDATA),
.s_axi_wlast(m00_couplers_to_auto_pc_WLAST),
.s_axi_wready(m00_couplers_to_auto_pc_WREADY),
.s_axi_wstrb(m00_couplers_to_auto_pc_WSTRB),
.s_axi_wvalid(m00_couplers_to_auto_pc_WVALID));
endmodule |
module m00_couplers_imp_WKXF3L
(M_ACLK,
M_ARESETN,
M_AXI_araddr,
M_AXI_arready,
M_AXI_arvalid,
M_AXI_awaddr,
M_AXI_awready,
M_AXI_awvalid,
M_AXI_bready,
M_AXI_bresp,
M_AXI_bvalid,
M_AXI_rdata,
M_AXI_rready,
M_AXI_rresp,
M_AXI_rvalid,
M_AXI_wdata,
M_AXI_wready,
M_AXI_wstrb,
M_AXI_wvalid,
S_ACLK,
S_ARESETN,
S_AXI_araddr,
S_AXI_arready,
S_AXI_arvalid,
S_AXI_awaddr,
S_AXI_awready,
S_AXI_awvalid,
S_AXI_bready,
S_AXI_bresp,
S_AXI_bvalid,
S_AXI_rdata,
S_AXI_rready,
S_AXI_rresp,
S_AXI_rvalid,
S_AXI_wdata,
S_AXI_wready,
S_AXI_wstrb,
S_AXI_wvalid);
input M_ACLK;
input [0:0]M_ARESETN;
output [4:0]M_AXI_araddr;
input M_AXI_arready;
output M_AXI_arvalid;
output [4:0]M_AXI_awaddr;
input M_AXI_awready;
output M_AXI_awvalid;
output M_AXI_bready;
input [1:0]M_AXI_bresp;
input M_AXI_bvalid;
input [31:0]M_AXI_rdata;
output M_AXI_rready;
input [1:0]M_AXI_rresp;
input M_AXI_rvalid;
output [31:0]M_AXI_wdata;
input M_AXI_wready;
output [3:0]M_AXI_wstrb;
output M_AXI_wvalid;
input S_ACLK;
input [0:0]S_ARESETN;
input [4:0]S_AXI_araddr;
output S_AXI_arready;
input S_AXI_arvalid;
input [4:0]S_AXI_awaddr;
output S_AXI_awready;
input S_AXI_awvalid;
input S_AXI_bready;
output [1:0]S_AXI_bresp;
output S_AXI_bvalid;
output [31:0]S_AXI_rdata;
input S_AXI_rready;
output [1:0]S_AXI_rresp;
output S_AXI_rvalid;
input [31:0]S_AXI_wdata;
output S_AXI_wready;
input [3:0]S_AXI_wstrb;
input S_AXI_wvalid;
wire [4:0]m00_couplers_to_m00_couplers_ARADDR;
wire m00_couplers_to_m00_couplers_ARREADY;
wire m00_couplers_to_m00_couplers_ARVALID;
wire [4:0]m00_couplers_to_m00_couplers_AWADDR;
wire m00_couplers_to_m00_couplers_AWREADY;
wire m00_couplers_to_m00_couplers_AWVALID;
wire m00_couplers_to_m00_couplers_BREADY;
wire [1:0]m00_couplers_to_m00_couplers_BRESP;
wire m00_couplers_to_m00_couplers_BVALID;
wire [31:0]m00_couplers_to_m00_couplers_RDATA;
wire m00_couplers_to_m00_couplers_RREADY;
wire [1:0]m00_couplers_to_m00_couplers_RRESP;
wire m00_couplers_to_m00_couplers_RVALID;
wire [31:0]m00_couplers_to_m00_couplers_WDATA;
wire m00_couplers_to_m00_couplers_WREADY;
wire [3:0]m00_couplers_to_m00_couplers_WSTRB;
wire m00_couplers_to_m00_couplers_WVALID;
assign M_AXI_araddr[4:0] = m00_couplers_to_m00_couplers_ARADDR;
assign M_AXI_arvalid = m00_couplers_to_m00_couplers_ARVALID;
assign M_AXI_awaddr[4:0] = m00_couplers_to_m00_couplers_AWADDR;
assign M_AXI_awvalid = m00_couplers_to_m00_couplers_AWVALID;
assign M_AXI_bready = m00_couplers_to_m00_couplers_BREADY;
assign M_AXI_rready = m00_couplers_to_m00_couplers_RREADY;
assign M_AXI_wdata[31:0] = m00_couplers_to_m00_couplers_WDATA;
assign M_AXI_wstrb[3:0] = m00_couplers_to_m00_couplers_WSTRB;
assign M_AXI_wvalid = m00_couplers_to_m00_couplers_WVALID;
assign S_AXI_arready = m00_couplers_to_m00_couplers_ARREADY;
assign S_AXI_awready = m00_couplers_to_m00_couplers_AWREADY;
assign S_AXI_bresp[1:0] = m00_couplers_to_m00_couplers_BRESP;
assign S_AXI_bvalid = m00_couplers_to_m00_couplers_BVALID;
assign S_AXI_rdata[31:0] = m00_couplers_to_m00_couplers_RDATA;
assign S_AXI_rresp[1:0] = m00_couplers_to_m00_couplers_RRESP;
assign S_AXI_rvalid = m00_couplers_to_m00_couplers_RVALID;
assign S_AXI_wready = m00_couplers_to_m00_couplers_WREADY;
assign m00_couplers_to_m00_couplers_ARADDR = S_AXI_araddr[4:0];
assign m00_couplers_to_m00_couplers_ARREADY = M_AXI_arready;
assign m00_couplers_to_m00_couplers_ARVALID = S_AXI_arvalid;
assign m00_couplers_to_m00_couplers_AWADDR = S_AXI_awaddr[4:0];
assign m00_couplers_to_m00_couplers_AWREADY = M_AXI_awready;
assign m00_couplers_to_m00_couplers_AWVALID = S_AXI_awvalid;
assign m00_couplers_to_m00_couplers_BREADY = S_AXI_bready;
assign m00_couplers_to_m00_couplers_BRESP = M_AXI_bresp[1:0];
assign m00_couplers_to_m00_couplers_BVALID = M_AXI_bvalid;
assign m00_couplers_to_m00_couplers_RDATA = M_AXI_rdata[31:0];
assign m00_couplers_to_m00_couplers_RREADY = S_AXI_rready;
assign m00_couplers_to_m00_couplers_RRESP = M_AXI_rresp[1:0];
assign m00_couplers_to_m00_couplers_RVALID = M_AXI_rvalid;
assign m00_couplers_to_m00_couplers_WDATA = S_AXI_wdata[31:0];
assign m00_couplers_to_m00_couplers_WREADY = M_AXI_wready;
assign m00_couplers_to_m00_couplers_WSTRB = S_AXI_wstrb[3:0];
assign m00_couplers_to_m00_couplers_WVALID = S_AXI_wvalid;
endmodule |
module m01_couplers_imp_1ORP4PS
(M_ACLK,
M_ARESETN,
M_AXI_araddr,
M_AXI_arready,
M_AXI_arvalid,
M_AXI_awaddr,
M_AXI_awready,
M_AXI_awvalid,
M_AXI_bready,
M_AXI_bresp,
M_AXI_bvalid,
M_AXI_rdata,
M_AXI_rready,
M_AXI_rresp,
M_AXI_rvalid,
M_AXI_wdata,
M_AXI_wready,
M_AXI_wvalid,
S_ACLK,
S_ARESETN,
S_AXI_araddr,
S_AXI_arready,
S_AXI_arvalid,
S_AXI_awaddr,
S_AXI_awready,
S_AXI_awvalid,
S_AXI_bready,
S_AXI_bresp,
S_AXI_bvalid,
S_AXI_rdata,
S_AXI_rready,
S_AXI_rresp,
S_AXI_rvalid,
S_AXI_wdata,
S_AXI_wready,
S_AXI_wvalid);
input M_ACLK;
input [0:0]M_ARESETN;
output [9:0]M_AXI_araddr;
input M_AXI_arready;
output M_AXI_arvalid;
output [9:0]M_AXI_awaddr;
input M_AXI_awready;
output M_AXI_awvalid;
output M_AXI_bready;
input [1:0]M_AXI_bresp;
input M_AXI_bvalid;
input [31:0]M_AXI_rdata;
output M_AXI_rready;
input [1:0]M_AXI_rresp;
input M_AXI_rvalid;
output [31:0]M_AXI_wdata;
input M_AXI_wready;
output M_AXI_wvalid;
input S_ACLK;
input [0:0]S_ARESETN;
input [9:0]S_AXI_araddr;
output S_AXI_arready;
input S_AXI_arvalid;
input [9:0]S_AXI_awaddr;
output S_AXI_awready;
input S_AXI_awvalid;
input S_AXI_bready;
output [1:0]S_AXI_bresp;
output S_AXI_bvalid;
output [31:0]S_AXI_rdata;
input S_AXI_rready;
output [1:0]S_AXI_rresp;
output S_AXI_rvalid;
input [31:0]S_AXI_wdata;
output S_AXI_wready;
input S_AXI_wvalid;
wire [9:0]m01_couplers_to_m01_couplers_ARADDR;
wire m01_couplers_to_m01_couplers_ARREADY;
wire m01_couplers_to_m01_couplers_ARVALID;
wire [9:0]m01_couplers_to_m01_couplers_AWADDR;
wire m01_couplers_to_m01_couplers_AWREADY;
wire m01_couplers_to_m01_couplers_AWVALID;
wire m01_couplers_to_m01_couplers_BREADY;
wire [1:0]m01_couplers_to_m01_couplers_BRESP;
wire m01_couplers_to_m01_couplers_BVALID;
wire [31:0]m01_couplers_to_m01_couplers_RDATA;
wire m01_couplers_to_m01_couplers_RREADY;
wire [1:0]m01_couplers_to_m01_couplers_RRESP;
wire m01_couplers_to_m01_couplers_RVALID;
wire [31:0]m01_couplers_to_m01_couplers_WDATA;
wire m01_couplers_to_m01_couplers_WREADY;
wire m01_couplers_to_m01_couplers_WVALID;
assign M_AXI_araddr[9:0] = m01_couplers_to_m01_couplers_ARADDR;
assign M_AXI_arvalid = m01_couplers_to_m01_couplers_ARVALID;
assign M_AXI_awaddr[9:0] = m01_couplers_to_m01_couplers_AWADDR;
assign M_AXI_awvalid = m01_couplers_to_m01_couplers_AWVALID;
assign M_AXI_bready = m01_couplers_to_m01_couplers_BREADY;
assign M_AXI_rready = m01_couplers_to_m01_couplers_RREADY;
assign M_AXI_wdata[31:0] = m01_couplers_to_m01_couplers_WDATA;
assign M_AXI_wvalid = m01_couplers_to_m01_couplers_WVALID;
assign S_AXI_arready = m01_couplers_to_m01_couplers_ARREADY;
assign S_AXI_awready = m01_couplers_to_m01_couplers_AWREADY;
assign S_AXI_bresp[1:0] = m01_couplers_to_m01_couplers_BRESP;
assign S_AXI_bvalid = m01_couplers_to_m01_couplers_BVALID;
assign S_AXI_rdata[31:0] = m01_couplers_to_m01_couplers_RDATA;
assign S_AXI_rresp[1:0] = m01_couplers_to_m01_couplers_RRESP;
assign S_AXI_rvalid = m01_couplers_to_m01_couplers_RVALID;
assign S_AXI_wready = m01_couplers_to_m01_couplers_WREADY;
assign m01_couplers_to_m01_couplers_ARADDR = S_AXI_araddr[9:0];
assign m01_couplers_to_m01_couplers_ARREADY = M_AXI_arready;
assign m01_couplers_to_m01_couplers_ARVALID = S_AXI_arvalid;
assign m01_couplers_to_m01_couplers_AWADDR = S_AXI_awaddr[9:0];
assign m01_couplers_to_m01_couplers_AWREADY = M_AXI_awready;
assign m01_couplers_to_m01_couplers_AWVALID = S_AXI_awvalid;
assign m01_couplers_to_m01_couplers_BREADY = S_AXI_bready;
assign m01_couplers_to_m01_couplers_BRESP = M_AXI_bresp[1:0];
assign m01_couplers_to_m01_couplers_BVALID = M_AXI_bvalid;
assign m01_couplers_to_m01_couplers_RDATA = M_AXI_rdata[31:0];
assign m01_couplers_to_m01_couplers_RREADY = S_AXI_rready;
assign m01_couplers_to_m01_couplers_RRESP = M_AXI_rresp[1:0];
assign m01_couplers_to_m01_couplers_RVALID = M_AXI_rvalid;
assign m01_couplers_to_m01_couplers_WDATA = S_AXI_wdata[31:0];
assign m01_couplers_to_m01_couplers_WREADY = M_AXI_wready;
assign m01_couplers_to_m01_couplers_WVALID = S_AXI_wvalid;
endmodule |
module m02_couplers_imp_1VD9O7M
(M_ACLK,
M_ARESETN,
M_AXI_araddr,
M_AXI_arready,
M_AXI_arvalid,
M_AXI_awaddr,
M_AXI_awready,
M_AXI_awvalid,
M_AXI_bready,
M_AXI_bresp,
M_AXI_bvalid,
M_AXI_rdata,
M_AXI_rready,
M_AXI_rresp,
M_AXI_rvalid,
M_AXI_wdata,
M_AXI_wready,
M_AXI_wstrb,
M_AXI_wvalid,
S_ACLK,
S_ARESETN,
S_AXI_araddr,
S_AXI_arready,
S_AXI_arvalid,
S_AXI_awaddr,
S_AXI_awready,
S_AXI_awvalid,
S_AXI_bready,
S_AXI_bresp,
S_AXI_bvalid,
S_AXI_rdata,
S_AXI_rready,
S_AXI_rresp,
S_AXI_rvalid,
S_AXI_wdata,
S_AXI_wready,
S_AXI_wstrb,
S_AXI_wvalid);
input M_ACLK;
input [0:0]M_ARESETN;
output [4:0]M_AXI_araddr;
input M_AXI_arready;
output M_AXI_arvalid;
output [4:0]M_AXI_awaddr;
input M_AXI_awready;
output M_AXI_awvalid;
output M_AXI_bready;
input [1:0]M_AXI_bresp;
input M_AXI_bvalid;
input [31:0]M_AXI_rdata;
output M_AXI_rready;
input [1:0]M_AXI_rresp;
input M_AXI_rvalid;
output [31:0]M_AXI_wdata;
input M_AXI_wready;
output [3:0]M_AXI_wstrb;
output M_AXI_wvalid;
input S_ACLK;
input [0:0]S_ARESETN;
input [4:0]S_AXI_araddr;
output S_AXI_arready;
input S_AXI_arvalid;
input [4:0]S_AXI_awaddr;
output S_AXI_awready;
input S_AXI_awvalid;
input S_AXI_bready;
output [1:0]S_AXI_bresp;
output S_AXI_bvalid;
output [31:0]S_AXI_rdata;
input S_AXI_rready;
output [1:0]S_AXI_rresp;
output S_AXI_rvalid;
input [31:0]S_AXI_wdata;
output S_AXI_wready;
input [3:0]S_AXI_wstrb;
input S_AXI_wvalid;
wire [4:0]m02_couplers_to_m02_couplers_ARADDR;
wire m02_couplers_to_m02_couplers_ARREADY;
wire m02_couplers_to_m02_couplers_ARVALID;
wire [4:0]m02_couplers_to_m02_couplers_AWADDR;
wire m02_couplers_to_m02_couplers_AWREADY;
wire m02_couplers_to_m02_couplers_AWVALID;
wire m02_couplers_to_m02_couplers_BREADY;
wire [1:0]m02_couplers_to_m02_couplers_BRESP;
wire m02_couplers_to_m02_couplers_BVALID;
wire [31:0]m02_couplers_to_m02_couplers_RDATA;
wire m02_couplers_to_m02_couplers_RREADY;
wire [1:0]m02_couplers_to_m02_couplers_RRESP;
wire m02_couplers_to_m02_couplers_RVALID;
wire [31:0]m02_couplers_to_m02_couplers_WDATA;
wire m02_couplers_to_m02_couplers_WREADY;
wire [3:0]m02_couplers_to_m02_couplers_WSTRB;
wire m02_couplers_to_m02_couplers_WVALID;
assign M_AXI_araddr[4:0] = m02_couplers_to_m02_couplers_ARADDR;
assign M_AXI_arvalid = m02_couplers_to_m02_couplers_ARVALID;
assign M_AXI_awaddr[4:0] = m02_couplers_to_m02_couplers_AWADDR;
assign M_AXI_awvalid = m02_couplers_to_m02_couplers_AWVALID;
assign M_AXI_bready = m02_couplers_to_m02_couplers_BREADY;
assign M_AXI_rready = m02_couplers_to_m02_couplers_RREADY;
assign M_AXI_wdata[31:0] = m02_couplers_to_m02_couplers_WDATA;
assign M_AXI_wstrb[3:0] = m02_couplers_to_m02_couplers_WSTRB;
assign M_AXI_wvalid = m02_couplers_to_m02_couplers_WVALID;
assign S_AXI_arready = m02_couplers_to_m02_couplers_ARREADY;
assign S_AXI_awready = m02_couplers_to_m02_couplers_AWREADY;
assign S_AXI_bresp[1:0] = m02_couplers_to_m02_couplers_BRESP;
assign S_AXI_bvalid = m02_couplers_to_m02_couplers_BVALID;
assign S_AXI_rdata[31:0] = m02_couplers_to_m02_couplers_RDATA;
assign S_AXI_rresp[1:0] = m02_couplers_to_m02_couplers_RRESP;
assign S_AXI_rvalid = m02_couplers_to_m02_couplers_RVALID;
assign S_AXI_wready = m02_couplers_to_m02_couplers_WREADY;
assign m02_couplers_to_m02_couplers_ARADDR = S_AXI_araddr[4:0];
assign m02_couplers_to_m02_couplers_ARREADY = M_AXI_arready;
assign m02_couplers_to_m02_couplers_ARVALID = S_AXI_arvalid;
assign m02_couplers_to_m02_couplers_AWADDR = S_AXI_awaddr[4:0];
assign m02_couplers_to_m02_couplers_AWREADY = M_AXI_awready;
assign m02_couplers_to_m02_couplers_AWVALID = S_AXI_awvalid;
assign m02_couplers_to_m02_couplers_BREADY = S_AXI_bready;
assign m02_couplers_to_m02_couplers_BRESP = M_AXI_bresp[1:0];
assign m02_couplers_to_m02_couplers_BVALID = M_AXI_bvalid;
assign m02_couplers_to_m02_couplers_RDATA = M_AXI_rdata[31:0];
assign m02_couplers_to_m02_couplers_RREADY = S_AXI_rready;
assign m02_couplers_to_m02_couplers_RRESP = M_AXI_rresp[1:0];
assign m02_couplers_to_m02_couplers_RVALID = M_AXI_rvalid;
assign m02_couplers_to_m02_couplers_WDATA = S_AXI_wdata[31:0];
assign m02_couplers_to_m02_couplers_WREADY = M_AXI_wready;
assign m02_couplers_to_m02_couplers_WSTRB = S_AXI_wstrb[3:0];
assign m02_couplers_to_m02_couplers_WVALID = S_AXI_wvalid;
endmodule |
module s00_couplers_imp_1P403ZT
(M_ACLK,
M_ARESETN,
M_AXI_araddr,
M_AXI_arburst,
M_AXI_arcache,
M_AXI_arlen,
M_AXI_arlock,
M_AXI_arprot,
M_AXI_arqos,
M_AXI_arready,
M_AXI_arsize,
M_AXI_arvalid,
M_AXI_rdata,
M_AXI_rlast,
M_AXI_rready,
M_AXI_rresp,
M_AXI_rvalid,
S_ACLK,
S_ARESETN,
S_AXI_araddr,
S_AXI_arburst,
S_AXI_arcache,
S_AXI_arlen,
S_AXI_arprot,
S_AXI_arready,
S_AXI_arsize,
S_AXI_arvalid,
S_AXI_rdata,
S_AXI_rlast,
S_AXI_rready,
S_AXI_rresp,
S_AXI_rvalid);
input M_ACLK;
input [0:0]M_ARESETN;
output [31:0]M_AXI_araddr;
output [1:0]M_AXI_arburst;
output [3:0]M_AXI_arcache;
output [7:0]M_AXI_arlen;
output [0:0]M_AXI_arlock;
output [2:0]M_AXI_arprot;
output [3:0]M_AXI_arqos;
input M_AXI_arready;
output [2:0]M_AXI_arsize;
output M_AXI_arvalid;
input [63:0]M_AXI_rdata;
input M_AXI_rlast;
output M_AXI_rready;
input [1:0]M_AXI_rresp;
input M_AXI_rvalid;
input S_ACLK;
input [0:0]S_ARESETN;
input [31:0]S_AXI_araddr;
input [1:0]S_AXI_arburst;
input [3:0]S_AXI_arcache;
input [7:0]S_AXI_arlen;
input [2:0]S_AXI_arprot;
output S_AXI_arready;
input [2:0]S_AXI_arsize;
input S_AXI_arvalid;
output [31:0]S_AXI_rdata;
output S_AXI_rlast;
input S_AXI_rready;
output [1:0]S_AXI_rresp;
output S_AXI_rvalid;
wire GND_1;
wire S_ACLK_1;
wire [0:0]S_ARESETN_1;
wire [31:0]auto_us_to_s00_couplers_ARADDR;
wire [1:0]auto_us_to_s00_couplers_ARBURST;
wire [3:0]auto_us_to_s00_couplers_ARCACHE;
wire [7:0]auto_us_to_s00_couplers_ARLEN;
wire [0:0]auto_us_to_s00_couplers_ARLOCK;
wire [2:0]auto_us_to_s00_couplers_ARPROT;
wire [3:0]auto_us_to_s00_couplers_ARQOS;
wire auto_us_to_s00_couplers_ARREADY;
wire [2:0]auto_us_to_s00_couplers_ARSIZE;
wire auto_us_to_s00_couplers_ARVALID;
wire [63:0]auto_us_to_s00_couplers_RDATA;
wire auto_us_to_s00_couplers_RLAST;
wire auto_us_to_s00_couplers_RREADY;
wire [1:0]auto_us_to_s00_couplers_RRESP;
wire auto_us_to_s00_couplers_RVALID;
wire [31:0]s00_couplers_to_auto_us_ARADDR;
wire [1:0]s00_couplers_to_auto_us_ARBURST;
wire [3:0]s00_couplers_to_auto_us_ARCACHE;
wire [7:0]s00_couplers_to_auto_us_ARLEN;
wire [2:0]s00_couplers_to_auto_us_ARPROT;
wire s00_couplers_to_auto_us_ARREADY;
wire [2:0]s00_couplers_to_auto_us_ARSIZE;
wire s00_couplers_to_auto_us_ARVALID;
wire [31:0]s00_couplers_to_auto_us_RDATA;
wire s00_couplers_to_auto_us_RLAST;
wire s00_couplers_to_auto_us_RREADY;
wire [1:0]s00_couplers_to_auto_us_RRESP;
wire s00_couplers_to_auto_us_RVALID;
assign M_AXI_araddr[31:0] = auto_us_to_s00_couplers_ARADDR;
assign M_AXI_arburst[1:0] = auto_us_to_s00_couplers_ARBURST;
assign M_AXI_arcache[3:0] = auto_us_to_s00_couplers_ARCACHE;
assign M_AXI_arlen[7:0] = auto_us_to_s00_couplers_ARLEN;
assign M_AXI_arlock[0] = auto_us_to_s00_couplers_ARLOCK;
assign M_AXI_arprot[2:0] = auto_us_to_s00_couplers_ARPROT;
assign M_AXI_arqos[3:0] = auto_us_to_s00_couplers_ARQOS;
assign M_AXI_arsize[2:0] = auto_us_to_s00_couplers_ARSIZE;
assign M_AXI_arvalid = auto_us_to_s00_couplers_ARVALID;
assign M_AXI_rready = auto_us_to_s00_couplers_RREADY;
assign S_ACLK_1 = S_ACLK;
assign S_ARESETN_1 = S_ARESETN[0];
assign S_AXI_arready = s00_couplers_to_auto_us_ARREADY;
assign S_AXI_rdata[31:0] = s00_couplers_to_auto_us_RDATA;
assign S_AXI_rlast = s00_couplers_to_auto_us_RLAST;
assign S_AXI_rresp[1:0] = s00_couplers_to_auto_us_RRESP;
assign S_AXI_rvalid = s00_couplers_to_auto_us_RVALID;
assign auto_us_to_s00_couplers_ARREADY = M_AXI_arready;
assign auto_us_to_s00_couplers_RDATA = M_AXI_rdata[63:0];
assign auto_us_to_s00_couplers_RLAST = M_AXI_rlast;
assign auto_us_to_s00_couplers_RRESP = M_AXI_rresp[1:0];
assign auto_us_to_s00_couplers_RVALID = M_AXI_rvalid;
assign s00_couplers_to_auto_us_ARADDR = S_AXI_araddr[31:0];
assign s00_couplers_to_auto_us_ARBURST = S_AXI_arburst[1:0];
assign s00_couplers_to_auto_us_ARCACHE = S_AXI_arcache[3:0];
assign s00_couplers_to_auto_us_ARLEN = S_AXI_arlen[7:0];
assign s00_couplers_to_auto_us_ARPROT = S_AXI_arprot[2:0];
assign s00_couplers_to_auto_us_ARSIZE = S_AXI_arsize[2:0];
assign s00_couplers_to_auto_us_ARVALID = S_AXI_arvalid;
assign s00_couplers_to_auto_us_RREADY = S_AXI_rready;
GND GND
(.G(GND_1));
system_auto_us_0 auto_us
(.m_axi_araddr(auto_us_to_s00_couplers_ARADDR),
.m_axi_arburst(auto_us_to_s00_couplers_ARBURST),
.m_axi_arcache(auto_us_to_s00_couplers_ARCACHE),
.m_axi_arlen(auto_us_to_s00_couplers_ARLEN),
.m_axi_arlock(auto_us_to_s00_couplers_ARLOCK),
.m_axi_arprot(auto_us_to_s00_couplers_ARPROT),
.m_axi_arqos(auto_us_to_s00_couplers_ARQOS),
.m_axi_arready(auto_us_to_s00_couplers_ARREADY),
.m_axi_arsize(auto_us_to_s00_couplers_ARSIZE),
.m_axi_arvalid(auto_us_to_s00_couplers_ARVALID),
.m_axi_rdata(auto_us_to_s00_couplers_RDATA),
.m_axi_rlast(auto_us_to_s00_couplers_RLAST),
.m_axi_rready(auto_us_to_s00_couplers_RREADY),
.m_axi_rresp(auto_us_to_s00_couplers_RRESP),
.m_axi_rvalid(auto_us_to_s00_couplers_RVALID),
.s_axi_aclk(S_ACLK_1),
.s_axi_araddr(s00_couplers_to_auto_us_ARADDR),
.s_axi_arburst(s00_couplers_to_auto_us_ARBURST),
.s_axi_arcache(s00_couplers_to_auto_us_ARCACHE),
.s_axi_aresetn(S_ARESETN_1),
.s_axi_arlen(s00_couplers_to_auto_us_ARLEN),
.s_axi_arlock(GND_1),
.s_axi_arprot(s00_couplers_to_auto_us_ARPROT),
.s_axi_arqos({GND_1,GND_1,GND_1,GND_1}),
.s_axi_arready(s00_couplers_to_auto_us_ARREADY),
.s_axi_arregion({GND_1,GND_1,GND_1,GND_1}),
.s_axi_arsize(s00_couplers_to_auto_us_ARSIZE),
.s_axi_arvalid(s00_couplers_to_auto_us_ARVALID),
.s_axi_rdata(s00_couplers_to_auto_us_RDATA),
.s_axi_rlast(s00_couplers_to_auto_us_RLAST),
.s_axi_rready(s00_couplers_to_auto_us_RREADY),
.s_axi_rresp(s00_couplers_to_auto_us_RRESP),
.s_axi_rvalid(s00_couplers_to_auto_us_RVALID));
endmodule |
module s00_couplers_imp_IK3G2O
(M_ACLK,
M_ARESETN,
M_AXI_araddr,
M_AXI_arprot,
M_AXI_arready,
M_AXI_arvalid,
M_AXI_awaddr,
M_AXI_awprot,
M_AXI_awready,
M_AXI_awvalid,
M_AXI_bready,
M_AXI_bresp,
M_AXI_bvalid,
M_AXI_rdata,
M_AXI_rready,
M_AXI_rresp,
M_AXI_rvalid,
M_AXI_wdata,
M_AXI_wready,
M_AXI_wstrb,
M_AXI_wvalid,
S_ACLK,
S_ARESETN,
S_AXI_araddr,
S_AXI_arburst,
S_AXI_arcache,
S_AXI_arid,
S_AXI_arlen,
S_AXI_arlock,
S_AXI_arprot,
S_AXI_arqos,
S_AXI_arready,
S_AXI_arsize,
S_AXI_arvalid,
S_AXI_awaddr,
S_AXI_awburst,
S_AXI_awcache,
S_AXI_awid,
S_AXI_awlen,
S_AXI_awlock,
S_AXI_awprot,
S_AXI_awqos,
S_AXI_awready,
S_AXI_awsize,
S_AXI_awvalid,
S_AXI_bid,
S_AXI_bready,
S_AXI_bresp,
S_AXI_bvalid,
S_AXI_rdata,
S_AXI_rid,
S_AXI_rlast,
S_AXI_rready,
S_AXI_rresp,
S_AXI_rvalid,
S_AXI_wdata,
S_AXI_wid,
S_AXI_wlast,
S_AXI_wready,
S_AXI_wstrb,
S_AXI_wvalid);
input M_ACLK;
input [0:0]M_ARESETN;
output [31:0]M_AXI_araddr;
output [2:0]M_AXI_arprot;
input M_AXI_arready;
output M_AXI_arvalid;
output [31:0]M_AXI_awaddr;
output [2:0]M_AXI_awprot;
input M_AXI_awready;
output M_AXI_awvalid;
output M_AXI_bready;
input [1:0]M_AXI_bresp;
input M_AXI_bvalid;
input [31:0]M_AXI_rdata;
output M_AXI_rready;
input [1:0]M_AXI_rresp;
input M_AXI_rvalid;
output [31:0]M_AXI_wdata;
input M_AXI_wready;
output [3:0]M_AXI_wstrb;
output M_AXI_wvalid;
input S_ACLK;
input [0:0]S_ARESETN;
input [31:0]S_AXI_araddr;
input [1:0]S_AXI_arburst;
input [3:0]S_AXI_arcache;
input [11:0]S_AXI_arid;
input [3:0]S_AXI_arlen;
input [1:0]S_AXI_arlock;
input [2:0]S_AXI_arprot;
input [3:0]S_AXI_arqos;
output S_AXI_arready;
input [2:0]S_AXI_arsize;
input S_AXI_arvalid;
input [31:0]S_AXI_awaddr;
input [1:0]S_AXI_awburst;
input [3:0]S_AXI_awcache;
input [11:0]S_AXI_awid;
input [3:0]S_AXI_awlen;
input [1:0]S_AXI_awlock;
input [2:0]S_AXI_awprot;
input [3:0]S_AXI_awqos;
output S_AXI_awready;
input [2:0]S_AXI_awsize;
input S_AXI_awvalid;
output [11:0]S_AXI_bid;
input S_AXI_bready;
output [1:0]S_AXI_bresp;
output S_AXI_bvalid;
output [31:0]S_AXI_rdata;
output [11:0]S_AXI_rid;
output S_AXI_rlast;
input S_AXI_rready;
output [1:0]S_AXI_rresp;
output S_AXI_rvalid;
input [31:0]S_AXI_wdata;
input [11:0]S_AXI_wid;
input S_AXI_wlast;
output S_AXI_wready;
input [3:0]S_AXI_wstrb;
input S_AXI_wvalid;
wire S_ACLK_1;
wire [0:0]S_ARESETN_1;
wire [31:0]auto_pc_to_s00_couplers_ARADDR;
wire [2:0]auto_pc_to_s00_couplers_ARPROT;
wire auto_pc_to_s00_couplers_ARREADY;
wire auto_pc_to_s00_couplers_ARVALID;
wire [31:0]auto_pc_to_s00_couplers_AWADDR;
wire [2:0]auto_pc_to_s00_couplers_AWPROT;
wire auto_pc_to_s00_couplers_AWREADY;
wire auto_pc_to_s00_couplers_AWVALID;
wire auto_pc_to_s00_couplers_BREADY;
wire [1:0]auto_pc_to_s00_couplers_BRESP;
wire auto_pc_to_s00_couplers_BVALID;
wire [31:0]auto_pc_to_s00_couplers_RDATA;
wire auto_pc_to_s00_couplers_RREADY;
wire [1:0]auto_pc_to_s00_couplers_RRESP;
wire auto_pc_to_s00_couplers_RVALID;
wire [31:0]auto_pc_to_s00_couplers_WDATA;
wire auto_pc_to_s00_couplers_WREADY;
wire [3:0]auto_pc_to_s00_couplers_WSTRB;
wire auto_pc_to_s00_couplers_WVALID;
wire [31:0]s00_couplers_to_auto_pc_ARADDR;
wire [1:0]s00_couplers_to_auto_pc_ARBURST;
wire [3:0]s00_couplers_to_auto_pc_ARCACHE;
wire [11:0]s00_couplers_to_auto_pc_ARID;
wire [3:0]s00_couplers_to_auto_pc_ARLEN;
wire [1:0]s00_couplers_to_auto_pc_ARLOCK;
wire [2:0]s00_couplers_to_auto_pc_ARPROT;
wire [3:0]s00_couplers_to_auto_pc_ARQOS;
wire s00_couplers_to_auto_pc_ARREADY;
wire [2:0]s00_couplers_to_auto_pc_ARSIZE;
wire s00_couplers_to_auto_pc_ARVALID;
wire [31:0]s00_couplers_to_auto_pc_AWADDR;
wire [1:0]s00_couplers_to_auto_pc_AWBURST;
wire [3:0]s00_couplers_to_auto_pc_AWCACHE;
wire [11:0]s00_couplers_to_auto_pc_AWID;
wire [3:0]s00_couplers_to_auto_pc_AWLEN;
wire [1:0]s00_couplers_to_auto_pc_AWLOCK;
wire [2:0]s00_couplers_to_auto_pc_AWPROT;
wire [3:0]s00_couplers_to_auto_pc_AWQOS;
wire s00_couplers_to_auto_pc_AWREADY;
wire [2:0]s00_couplers_to_auto_pc_AWSIZE;
wire s00_couplers_to_auto_pc_AWVALID;
wire [11:0]s00_couplers_to_auto_pc_BID;
wire s00_couplers_to_auto_pc_BREADY;
wire [1:0]s00_couplers_to_auto_pc_BRESP;
wire s00_couplers_to_auto_pc_BVALID;
wire [31:0]s00_couplers_to_auto_pc_RDATA;
wire [11:0]s00_couplers_to_auto_pc_RID;
wire s00_couplers_to_auto_pc_RLAST;
wire s00_couplers_to_auto_pc_RREADY;
wire [1:0]s00_couplers_to_auto_pc_RRESP;
wire s00_couplers_to_auto_pc_RVALID;
wire [31:0]s00_couplers_to_auto_pc_WDATA;
wire [11:0]s00_couplers_to_auto_pc_WID;
wire s00_couplers_to_auto_pc_WLAST;
wire s00_couplers_to_auto_pc_WREADY;
wire [3:0]s00_couplers_to_auto_pc_WSTRB;
wire s00_couplers_to_auto_pc_WVALID;
assign M_AXI_araddr[31:0] = auto_pc_to_s00_couplers_ARADDR;
assign M_AXI_arprot[2:0] = auto_pc_to_s00_couplers_ARPROT;
assign M_AXI_arvalid = auto_pc_to_s00_couplers_ARVALID;
assign M_AXI_awaddr[31:0] = auto_pc_to_s00_couplers_AWADDR;
assign M_AXI_awprot[2:0] = auto_pc_to_s00_couplers_AWPROT;
assign M_AXI_awvalid = auto_pc_to_s00_couplers_AWVALID;
assign M_AXI_bready = auto_pc_to_s00_couplers_BREADY;
assign M_AXI_rready = auto_pc_to_s00_couplers_RREADY;
assign M_AXI_wdata[31:0] = auto_pc_to_s00_couplers_WDATA;
assign M_AXI_wstrb[3:0] = auto_pc_to_s00_couplers_WSTRB;
assign M_AXI_wvalid = auto_pc_to_s00_couplers_WVALID;
assign S_ACLK_1 = S_ACLK;
assign S_ARESETN_1 = S_ARESETN[0];
assign S_AXI_arready = s00_couplers_to_auto_pc_ARREADY;
assign S_AXI_awready = s00_couplers_to_auto_pc_AWREADY;
assign S_AXI_bid[11:0] = s00_couplers_to_auto_pc_BID;
assign S_AXI_bresp[1:0] = s00_couplers_to_auto_pc_BRESP;
assign S_AXI_bvalid = s00_couplers_to_auto_pc_BVALID;
assign S_AXI_rdata[31:0] = s00_couplers_to_auto_pc_RDATA;
assign S_AXI_rid[11:0] = s00_couplers_to_auto_pc_RID;
assign S_AXI_rlast = s00_couplers_to_auto_pc_RLAST;
assign S_AXI_rresp[1:0] = s00_couplers_to_auto_pc_RRESP;
assign S_AXI_rvalid = s00_couplers_to_auto_pc_RVALID;
assign S_AXI_wready = s00_couplers_to_auto_pc_WREADY;
assign auto_pc_to_s00_couplers_ARREADY = M_AXI_arready;
assign auto_pc_to_s00_couplers_AWREADY = M_AXI_awready;
assign auto_pc_to_s00_couplers_BRESP = M_AXI_bresp[1:0];
assign auto_pc_to_s00_couplers_BVALID = M_AXI_bvalid;
assign auto_pc_to_s00_couplers_RDATA = M_AXI_rdata[31:0];
assign auto_pc_to_s00_couplers_RRESP = M_AXI_rresp[1:0];
assign auto_pc_to_s00_couplers_RVALID = M_AXI_rvalid;
assign auto_pc_to_s00_couplers_WREADY = M_AXI_wready;
assign s00_couplers_to_auto_pc_ARADDR = S_AXI_araddr[31:0];
assign s00_couplers_to_auto_pc_ARBURST = S_AXI_arburst[1:0];
assign s00_couplers_to_auto_pc_ARCACHE = S_AXI_arcache[3:0];
assign s00_couplers_to_auto_pc_ARID = S_AXI_arid[11:0];
assign s00_couplers_to_auto_pc_ARLEN = S_AXI_arlen[3:0];
assign s00_couplers_to_auto_pc_ARLOCK = S_AXI_arlock[1:0];
assign s00_couplers_to_auto_pc_ARPROT = S_AXI_arprot[2:0];
assign s00_couplers_to_auto_pc_ARQOS = S_AXI_arqos[3:0];
assign s00_couplers_to_auto_pc_ARSIZE = S_AXI_arsize[2:0];
assign s00_couplers_to_auto_pc_ARVALID = S_AXI_arvalid;
assign s00_couplers_to_auto_pc_AWADDR = S_AXI_awaddr[31:0];
assign s00_couplers_to_auto_pc_AWBURST = S_AXI_awburst[1:0];
assign s00_couplers_to_auto_pc_AWCACHE = S_AXI_awcache[3:0];
assign s00_couplers_to_auto_pc_AWID = S_AXI_awid[11:0];
assign s00_couplers_to_auto_pc_AWLEN = S_AXI_awlen[3:0];
assign s00_couplers_to_auto_pc_AWLOCK = S_AXI_awlock[1:0];
assign s00_couplers_to_auto_pc_AWPROT = S_AXI_awprot[2:0];
assign s00_couplers_to_auto_pc_AWQOS = S_AXI_awqos[3:0];
assign s00_couplers_to_auto_pc_AWSIZE = S_AXI_awsize[2:0];
assign s00_couplers_to_auto_pc_AWVALID = S_AXI_awvalid;
assign s00_couplers_to_auto_pc_BREADY = S_AXI_bready;
assign s00_couplers_to_auto_pc_RREADY = S_AXI_rready;
assign s00_couplers_to_auto_pc_WDATA = S_AXI_wdata[31:0];
assign s00_couplers_to_auto_pc_WID = S_AXI_wid[11:0];
assign s00_couplers_to_auto_pc_WLAST = S_AXI_wlast;
assign s00_couplers_to_auto_pc_WSTRB = S_AXI_wstrb[3:0];
assign s00_couplers_to_auto_pc_WVALID = S_AXI_wvalid;
system_auto_pc_0 auto_pc
(.aclk(S_ACLK_1),
.aresetn(S_ARESETN_1),
.m_axi_araddr(auto_pc_to_s00_couplers_ARADDR),
.m_axi_arprot(auto_pc_to_s00_couplers_ARPROT),
.m_axi_arready(auto_pc_to_s00_couplers_ARREADY),
.m_axi_arvalid(auto_pc_to_s00_couplers_ARVALID),
.m_axi_awaddr(auto_pc_to_s00_couplers_AWADDR),
.m_axi_awprot(auto_pc_to_s00_couplers_AWPROT),
.m_axi_awready(auto_pc_to_s00_couplers_AWREADY),
.m_axi_awvalid(auto_pc_to_s00_couplers_AWVALID),
.m_axi_bready(auto_pc_to_s00_couplers_BREADY),
.m_axi_bresp(auto_pc_to_s00_couplers_BRESP),
.m_axi_bvalid(auto_pc_to_s00_couplers_BVALID),
.m_axi_rdata(auto_pc_to_s00_couplers_RDATA),
.m_axi_rready(auto_pc_to_s00_couplers_RREADY),
.m_axi_rresp(auto_pc_to_s00_couplers_RRESP),
.m_axi_rvalid(auto_pc_to_s00_couplers_RVALID),
.m_axi_wdata(auto_pc_to_s00_couplers_WDATA),
.m_axi_wready(auto_pc_to_s00_couplers_WREADY),
.m_axi_wstrb(auto_pc_to_s00_couplers_WSTRB),
.m_axi_wvalid(auto_pc_to_s00_couplers_WVALID),
.s_axi_araddr(s00_couplers_to_auto_pc_ARADDR),
.s_axi_arburst(s00_couplers_to_auto_pc_ARBURST),
.s_axi_arcache(s00_couplers_to_auto_pc_ARCACHE),
.s_axi_arid(s00_couplers_to_auto_pc_ARID),
.s_axi_arlen(s00_couplers_to_auto_pc_ARLEN),
.s_axi_arlock(s00_couplers_to_auto_pc_ARLOCK),
.s_axi_arprot(s00_couplers_to_auto_pc_ARPROT),
.s_axi_arqos(s00_couplers_to_auto_pc_ARQOS),
.s_axi_arready(s00_couplers_to_auto_pc_ARREADY),
.s_axi_arsize(s00_couplers_to_auto_pc_ARSIZE),
.s_axi_arvalid(s00_couplers_to_auto_pc_ARVALID),
.s_axi_awaddr(s00_couplers_to_auto_pc_AWADDR),
.s_axi_awburst(s00_couplers_to_auto_pc_AWBURST),
.s_axi_awcache(s00_couplers_to_auto_pc_AWCACHE),
.s_axi_awid(s00_couplers_to_auto_pc_AWID),
.s_axi_awlen(s00_couplers_to_auto_pc_AWLEN),
.s_axi_awlock(s00_couplers_to_auto_pc_AWLOCK),
.s_axi_awprot(s00_couplers_to_auto_pc_AWPROT),
.s_axi_awqos(s00_couplers_to_auto_pc_AWQOS),
.s_axi_awready(s00_couplers_to_auto_pc_AWREADY),
.s_axi_awsize(s00_couplers_to_auto_pc_AWSIZE),
.s_axi_awvalid(s00_couplers_to_auto_pc_AWVALID),
.s_axi_bid(s00_couplers_to_auto_pc_BID),
.s_axi_bready(s00_couplers_to_auto_pc_BREADY),
.s_axi_bresp(s00_couplers_to_auto_pc_BRESP),
.s_axi_bvalid(s00_couplers_to_auto_pc_BVALID),
.s_axi_rdata(s00_couplers_to_auto_pc_RDATA),
.s_axi_rid(s00_couplers_to_auto_pc_RID),
.s_axi_rlast(s00_couplers_to_auto_pc_RLAST),
.s_axi_rready(s00_couplers_to_auto_pc_RREADY),
.s_axi_rresp(s00_couplers_to_auto_pc_RRESP),
.s_axi_rvalid(s00_couplers_to_auto_pc_RVALID),
.s_axi_wdata(s00_couplers_to_auto_pc_WDATA),
.s_axi_wid(s00_couplers_to_auto_pc_WID),
.s_axi_wlast(s00_couplers_to_auto_pc_WLAST),
.s_axi_wready(s00_couplers_to_auto_pc_WREADY),
.s_axi_wstrb(s00_couplers_to_auto_pc_WSTRB),
.s_axi_wvalid(s00_couplers_to_auto_pc_WVALID));
endmodule |
module s01_couplers_imp_VQ497S
(M_ACLK,
M_ARESETN,
M_AXI_awaddr,
M_AXI_awburst,
M_AXI_awcache,
M_AXI_awlen,
M_AXI_awlock,
M_AXI_awprot,
M_AXI_awqos,
M_AXI_awready,
M_AXI_awsize,
M_AXI_awvalid,
M_AXI_bready,
M_AXI_bresp,
M_AXI_bvalid,
M_AXI_wdata,
M_AXI_wlast,
M_AXI_wready,
M_AXI_wstrb,
M_AXI_wvalid,
S_ACLK,
S_ARESETN,
S_AXI_awaddr,
S_AXI_awburst,
S_AXI_awcache,
S_AXI_awlen,
S_AXI_awprot,
S_AXI_awready,
S_AXI_awsize,
S_AXI_awvalid,
S_AXI_bready,
S_AXI_bresp,
S_AXI_bvalid,
S_AXI_wdata,
S_AXI_wlast,
S_AXI_wready,
S_AXI_wstrb,
S_AXI_wvalid);
input M_ACLK;
input [0:0]M_ARESETN;
output [31:0]M_AXI_awaddr;
output [1:0]M_AXI_awburst;
output [3:0]M_AXI_awcache;
output [7:0]M_AXI_awlen;
output [0:0]M_AXI_awlock;
output [2:0]M_AXI_awprot;
output [3:0]M_AXI_awqos;
input M_AXI_awready;
output [2:0]M_AXI_awsize;
output M_AXI_awvalid;
output M_AXI_bready;
input [1:0]M_AXI_bresp;
input M_AXI_bvalid;
output [63:0]M_AXI_wdata;
output M_AXI_wlast;
input M_AXI_wready;
output [7:0]M_AXI_wstrb;
output M_AXI_wvalid;
input S_ACLK;
input [0:0]S_ARESETN;
input [31:0]S_AXI_awaddr;
input [1:0]S_AXI_awburst;
input [3:0]S_AXI_awcache;
input [7:0]S_AXI_awlen;
input [2:0]S_AXI_awprot;
output S_AXI_awready;
input [2:0]S_AXI_awsize;
input S_AXI_awvalid;
input S_AXI_bready;
output [1:0]S_AXI_bresp;
output S_AXI_bvalid;
input [31:0]S_AXI_wdata;
input S_AXI_wlast;
output S_AXI_wready;
input [3:0]S_AXI_wstrb;
input S_AXI_wvalid;
wire GND_1;
wire S_ACLK_1;
wire [0:0]S_ARESETN_1;
wire [31:0]auto_us_to_s01_couplers_AWADDR;
wire [1:0]auto_us_to_s01_couplers_AWBURST;
wire [3:0]auto_us_to_s01_couplers_AWCACHE;
wire [7:0]auto_us_to_s01_couplers_AWLEN;
wire [0:0]auto_us_to_s01_couplers_AWLOCK;
wire [2:0]auto_us_to_s01_couplers_AWPROT;
wire [3:0]auto_us_to_s01_couplers_AWQOS;
wire auto_us_to_s01_couplers_AWREADY;
wire [2:0]auto_us_to_s01_couplers_AWSIZE;
wire auto_us_to_s01_couplers_AWVALID;
wire auto_us_to_s01_couplers_BREADY;
wire [1:0]auto_us_to_s01_couplers_BRESP;
wire auto_us_to_s01_couplers_BVALID;
wire [63:0]auto_us_to_s01_couplers_WDATA;
wire auto_us_to_s01_couplers_WLAST;
wire auto_us_to_s01_couplers_WREADY;
wire [7:0]auto_us_to_s01_couplers_WSTRB;
wire auto_us_to_s01_couplers_WVALID;
wire [31:0]s01_couplers_to_auto_us_AWADDR;
wire [1:0]s01_couplers_to_auto_us_AWBURST;
wire [3:0]s01_couplers_to_auto_us_AWCACHE;
wire [7:0]s01_couplers_to_auto_us_AWLEN;
wire [2:0]s01_couplers_to_auto_us_AWPROT;
wire s01_couplers_to_auto_us_AWREADY;
wire [2:0]s01_couplers_to_auto_us_AWSIZE;
wire s01_couplers_to_auto_us_AWVALID;
wire s01_couplers_to_auto_us_BREADY;
wire [1:0]s01_couplers_to_auto_us_BRESP;
wire s01_couplers_to_auto_us_BVALID;
wire [31:0]s01_couplers_to_auto_us_WDATA;
wire s01_couplers_to_auto_us_WLAST;
wire s01_couplers_to_auto_us_WREADY;
wire [3:0]s01_couplers_to_auto_us_WSTRB;
wire s01_couplers_to_auto_us_WVALID;
assign M_AXI_awaddr[31:0] = auto_us_to_s01_couplers_AWADDR;
assign M_AXI_awburst[1:0] = auto_us_to_s01_couplers_AWBURST;
assign M_AXI_awcache[3:0] = auto_us_to_s01_couplers_AWCACHE;
assign M_AXI_awlen[7:0] = auto_us_to_s01_couplers_AWLEN;
assign M_AXI_awlock[0] = auto_us_to_s01_couplers_AWLOCK;
assign M_AXI_awprot[2:0] = auto_us_to_s01_couplers_AWPROT;
assign M_AXI_awqos[3:0] = auto_us_to_s01_couplers_AWQOS;
assign M_AXI_awsize[2:0] = auto_us_to_s01_couplers_AWSIZE;
assign M_AXI_awvalid = auto_us_to_s01_couplers_AWVALID;
assign M_AXI_bready = auto_us_to_s01_couplers_BREADY;
assign M_AXI_wdata[63:0] = auto_us_to_s01_couplers_WDATA;
assign M_AXI_wlast = auto_us_to_s01_couplers_WLAST;
assign M_AXI_wstrb[7:0] = auto_us_to_s01_couplers_WSTRB;
assign M_AXI_wvalid = auto_us_to_s01_couplers_WVALID;
assign S_ACLK_1 = S_ACLK;
assign S_ARESETN_1 = S_ARESETN[0];
assign S_AXI_awready = s01_couplers_to_auto_us_AWREADY;
assign S_AXI_bresp[1:0] = s01_couplers_to_auto_us_BRESP;
assign S_AXI_bvalid = s01_couplers_to_auto_us_BVALID;
assign S_AXI_wready = s01_couplers_to_auto_us_WREADY;
assign auto_us_to_s01_couplers_AWREADY = M_AXI_awready;
assign auto_us_to_s01_couplers_BRESP = M_AXI_bresp[1:0];
assign auto_us_to_s01_couplers_BVALID = M_AXI_bvalid;
assign auto_us_to_s01_couplers_WREADY = M_AXI_wready;
assign s01_couplers_to_auto_us_AWADDR = S_AXI_awaddr[31:0];
assign s01_couplers_to_auto_us_AWBURST = S_AXI_awburst[1:0];
assign s01_couplers_to_auto_us_AWCACHE = S_AXI_awcache[3:0];
assign s01_couplers_to_auto_us_AWLEN = S_AXI_awlen[7:0];
assign s01_couplers_to_auto_us_AWPROT = S_AXI_awprot[2:0];
assign s01_couplers_to_auto_us_AWSIZE = S_AXI_awsize[2:0];
assign s01_couplers_to_auto_us_AWVALID = S_AXI_awvalid;
assign s01_couplers_to_auto_us_BREADY = S_AXI_bready;
assign s01_couplers_to_auto_us_WDATA = S_AXI_wdata[31:0];
assign s01_couplers_to_auto_us_WLAST = S_AXI_wlast;
assign s01_couplers_to_auto_us_WSTRB = S_AXI_wstrb[3:0];
assign s01_couplers_to_auto_us_WVALID = S_AXI_wvalid;
GND GND
(.G(GND_1));
system_auto_us_1 auto_us
(.m_axi_awaddr(auto_us_to_s01_couplers_AWADDR),
.m_axi_awburst(auto_us_to_s01_couplers_AWBURST),
.m_axi_awcache(auto_us_to_s01_couplers_AWCACHE),
.m_axi_awlen(auto_us_to_s01_couplers_AWLEN),
.m_axi_awlock(auto_us_to_s01_couplers_AWLOCK),
.m_axi_awprot(auto_us_to_s01_couplers_AWPROT),
.m_axi_awqos(auto_us_to_s01_couplers_AWQOS),
.m_axi_awready(auto_us_to_s01_couplers_AWREADY),
.m_axi_awsize(auto_us_to_s01_couplers_AWSIZE),
.m_axi_awvalid(auto_us_to_s01_couplers_AWVALID),
.m_axi_bready(auto_us_to_s01_couplers_BREADY),
.m_axi_bresp(auto_us_to_s01_couplers_BRESP),
.m_axi_bvalid(auto_us_to_s01_couplers_BVALID),
.m_axi_wdata(auto_us_to_s01_couplers_WDATA),
.m_axi_wlast(auto_us_to_s01_couplers_WLAST),
.m_axi_wready(auto_us_to_s01_couplers_WREADY),
.m_axi_wstrb(auto_us_to_s01_couplers_WSTRB),
.m_axi_wvalid(auto_us_to_s01_couplers_WVALID),
.s_axi_aclk(S_ACLK_1),
.s_axi_aresetn(S_ARESETN_1),
.s_axi_awaddr(s01_couplers_to_auto_us_AWADDR),
.s_axi_awburst(s01_couplers_to_auto_us_AWBURST),
.s_axi_awcache(s01_couplers_to_auto_us_AWCACHE),
.s_axi_awlen(s01_couplers_to_auto_us_AWLEN),
.s_axi_awlock(GND_1),
.s_axi_awprot(s01_couplers_to_auto_us_AWPROT),
.s_axi_awqos({GND_1,GND_1,GND_1,GND_1}),
.s_axi_awready(s01_couplers_to_auto_us_AWREADY),
.s_axi_awregion({GND_1,GND_1,GND_1,GND_1}),
.s_axi_awsize(s01_couplers_to_auto_us_AWSIZE),
.s_axi_awvalid(s01_couplers_to_auto_us_AWVALID),
.s_axi_bready(s01_couplers_to_auto_us_BREADY),
.s_axi_bresp(s01_couplers_to_auto_us_BRESP),
.s_axi_bvalid(s01_couplers_to_auto_us_BVALID),
.s_axi_wdata(s01_couplers_to_auto_us_WDATA),
.s_axi_wlast(s01_couplers_to_auto_us_WLAST),
.s_axi_wready(s01_couplers_to_auto_us_WREADY),
.s_axi_wstrb(s01_couplers_to_auto_us_WSTRB),
.s_axi_wvalid(s01_couplers_to_auto_us_WVALID));
endmodule |
module system
(DDR_addr,
DDR_ba,
DDR_cas_n,
DDR_ck_n,
DDR_ck_p,
DDR_cke,
DDR_cs_n,
DDR_dm,
DDR_dq,
DDR_dqs_n,
DDR_dqs_p,
DDR_odt,
DDR_ras_n,
DDR_reset_n,
DDR_we_n,
FIXED_IO_ddr_vrn,
FIXED_IO_ddr_vrp,
FIXED_IO_mio,
FIXED_IO_ps_clk,
FIXED_IO_ps_porb,
FIXED_IO_ps_srstb);
inout [14:0]DDR_addr;
inout [2:0]DDR_ba;
inout DDR_cas_n;
inout DDR_ck_n;
inout DDR_ck_p;
inout DDR_cke;
inout DDR_cs_n;
inout [3:0]DDR_dm;
inout [31:0]DDR_dq;
inout [3:0]DDR_dqs_n;
inout [3:0]DDR_dqs_p;
inout DDR_odt;
inout DDR_ras_n;
inout DDR_reset_n;
inout DDR_we_n;
inout FIXED_IO_ddr_vrn;
inout FIXED_IO_ddr_vrp;
inout [53:0]FIXED_IO_mio;
inout FIXED_IO_ps_clk;
inout FIXED_IO_ps_porb;
inout FIXED_IO_ps_srstb;
wire GND_1;
wire [31:0]HLS_accel_0_OUTPUT_STREAM_TDATA;
wire [3:0]HLS_accel_0_OUTPUT_STREAM_TKEEP;
wire [0:0]HLS_accel_0_OUTPUT_STREAM_TLAST;
wire HLS_accel_0_OUTPUT_STREAM_TREADY;
wire HLS_accel_0_OUTPUT_STREAM_TVALID;
wire HLS_accel_0_interrupt;
wire VCC_1;
wire [31:0]axi_dma_0_M_AXIS_MM2S_TDATA;
wire [3:0]axi_dma_0_M_AXIS_MM2S_TKEEP;
wire axi_dma_0_M_AXIS_MM2S_TLAST;
wire axi_dma_0_M_AXIS_MM2S_TREADY;
wire axi_dma_0_M_AXIS_MM2S_TVALID;
wire [31:0]axi_dma_0_M_AXI_MM2S_ARADDR;
wire [1:0]axi_dma_0_M_AXI_MM2S_ARBURST;
wire [3:0]axi_dma_0_M_AXI_MM2S_ARCACHE;
wire [7:0]axi_dma_0_M_AXI_MM2S_ARLEN;
wire [2:0]axi_dma_0_M_AXI_MM2S_ARPROT;
wire axi_dma_0_M_AXI_MM2S_ARREADY;
wire [2:0]axi_dma_0_M_AXI_MM2S_ARSIZE;
wire axi_dma_0_M_AXI_MM2S_ARVALID;
wire [31:0]axi_dma_0_M_AXI_MM2S_RDATA;
wire axi_dma_0_M_AXI_MM2S_RLAST;
wire axi_dma_0_M_AXI_MM2S_RREADY;
wire [1:0]axi_dma_0_M_AXI_MM2S_RRESP;
wire axi_dma_0_M_AXI_MM2S_RVALID;
wire [31:0]axi_dma_0_M_AXI_S2MM_AWADDR;
wire [1:0]axi_dma_0_M_AXI_S2MM_AWBURST;
wire [3:0]axi_dma_0_M_AXI_S2MM_AWCACHE;
wire [7:0]axi_dma_0_M_AXI_S2MM_AWLEN;
wire [2:0]axi_dma_0_M_AXI_S2MM_AWPROT;
wire axi_dma_0_M_AXI_S2MM_AWREADY;
wire [2:0]axi_dma_0_M_AXI_S2MM_AWSIZE;
wire axi_dma_0_M_AXI_S2MM_AWVALID;
wire axi_dma_0_M_AXI_S2MM_BREADY;
wire [1:0]axi_dma_0_M_AXI_S2MM_BRESP;
wire axi_dma_0_M_AXI_S2MM_BVALID;
wire [31:0]axi_dma_0_M_AXI_S2MM_WDATA;
wire axi_dma_0_M_AXI_S2MM_WLAST;
wire axi_dma_0_M_AXI_S2MM_WREADY;
wire [3:0]axi_dma_0_M_AXI_S2MM_WSTRB;
wire axi_dma_0_M_AXI_S2MM_WVALID;
wire [31:0]axi_mem_intercon_M00_AXI_ARADDR;
wire [1:0]axi_mem_intercon_M00_AXI_ARBURST;
wire [3:0]axi_mem_intercon_M00_AXI_ARCACHE;
wire [0:0]axi_mem_intercon_M00_AXI_ARID;
wire [3:0]axi_mem_intercon_M00_AXI_ARLEN;
wire [1:0]axi_mem_intercon_M00_AXI_ARLOCK;
wire [2:0]axi_mem_intercon_M00_AXI_ARPROT;
wire [3:0]axi_mem_intercon_M00_AXI_ARQOS;
wire axi_mem_intercon_M00_AXI_ARREADY;
wire [2:0]axi_mem_intercon_M00_AXI_ARSIZE;
wire axi_mem_intercon_M00_AXI_ARVALID;
wire [31:0]axi_mem_intercon_M00_AXI_AWADDR;
wire [1:0]axi_mem_intercon_M00_AXI_AWBURST;
wire [3:0]axi_mem_intercon_M00_AXI_AWCACHE;
wire [0:0]axi_mem_intercon_M00_AXI_AWID;
wire [3:0]axi_mem_intercon_M00_AXI_AWLEN;
wire [1:0]axi_mem_intercon_M00_AXI_AWLOCK;
wire [2:0]axi_mem_intercon_M00_AXI_AWPROT;
wire [3:0]axi_mem_intercon_M00_AXI_AWQOS;
wire axi_mem_intercon_M00_AXI_AWREADY;
wire [2:0]axi_mem_intercon_M00_AXI_AWSIZE;
wire axi_mem_intercon_M00_AXI_AWVALID;
wire [2:0]axi_mem_intercon_M00_AXI_BID;
wire axi_mem_intercon_M00_AXI_BREADY;
wire [1:0]axi_mem_intercon_M00_AXI_BRESP;
wire axi_mem_intercon_M00_AXI_BVALID;
wire [63:0]axi_mem_intercon_M00_AXI_RDATA;
wire [2:0]axi_mem_intercon_M00_AXI_RID;
wire axi_mem_intercon_M00_AXI_RLAST;
wire axi_mem_intercon_M00_AXI_RREADY;
wire [1:0]axi_mem_intercon_M00_AXI_RRESP;
wire axi_mem_intercon_M00_AXI_RVALID;
wire [63:0]axi_mem_intercon_M00_AXI_WDATA;
wire [0:0]axi_mem_intercon_M00_AXI_WID;
wire axi_mem_intercon_M00_AXI_WLAST;
wire axi_mem_intercon_M00_AXI_WREADY;
wire [7:0]axi_mem_intercon_M00_AXI_WSTRB;
wire axi_mem_intercon_M00_AXI_WVALID;
wire axi_timer_0_interrupt;
wire [14:0]processing_system7_0_DDR_ADDR;
wire [2:0]processing_system7_0_DDR_BA;
wire processing_system7_0_DDR_CAS_N;
wire processing_system7_0_DDR_CKE;
wire processing_system7_0_DDR_CK_N;
wire processing_system7_0_DDR_CK_P;
wire processing_system7_0_DDR_CS_N;
wire [3:0]processing_system7_0_DDR_DM;
wire [31:0]processing_system7_0_DDR_DQ;
wire [3:0]processing_system7_0_DDR_DQS_N;
wire [3:0]processing_system7_0_DDR_DQS_P;
wire processing_system7_0_DDR_ODT;
wire processing_system7_0_DDR_RAS_N;
wire processing_system7_0_DDR_RESET_N;
wire processing_system7_0_DDR_WE_N;
wire processing_system7_0_FCLK_CLK0;
wire processing_system7_0_FCLK_RESET0_N;
wire processing_system7_0_FIXED_IO_DDR_VRN;
wire processing_system7_0_FIXED_IO_DDR_VRP;
wire [53:0]processing_system7_0_FIXED_IO_MIO;
wire processing_system7_0_FIXED_IO_PS_CLK;
wire processing_system7_0_FIXED_IO_PS_PORB;
wire processing_system7_0_FIXED_IO_PS_SRSTB;
wire [31:0]processing_system7_0_M_AXI_GP0_ARADDR;
wire [1:0]processing_system7_0_M_AXI_GP0_ARBURST;
wire [3:0]processing_system7_0_M_AXI_GP0_ARCACHE;
wire [11:0]processing_system7_0_M_AXI_GP0_ARID;
wire [3:0]processing_system7_0_M_AXI_GP0_ARLEN;
wire [1:0]processing_system7_0_M_AXI_GP0_ARLOCK;
wire [2:0]processing_system7_0_M_AXI_GP0_ARPROT;
wire [3:0]processing_system7_0_M_AXI_GP0_ARQOS;
wire processing_system7_0_M_AXI_GP0_ARREADY;
wire [2:0]processing_system7_0_M_AXI_GP0_ARSIZE;
wire processing_system7_0_M_AXI_GP0_ARVALID;
wire [31:0]processing_system7_0_M_AXI_GP0_AWADDR;
wire [1:0]processing_system7_0_M_AXI_GP0_AWBURST;
wire [3:0]processing_system7_0_M_AXI_GP0_AWCACHE;
wire [11:0]processing_system7_0_M_AXI_GP0_AWID;
wire [3:0]processing_system7_0_M_AXI_GP0_AWLEN;
wire [1:0]processing_system7_0_M_AXI_GP0_AWLOCK;
wire [2:0]processing_system7_0_M_AXI_GP0_AWPROT;
wire [3:0]processing_system7_0_M_AXI_GP0_AWQOS;
wire processing_system7_0_M_AXI_GP0_AWREADY;
wire [2:0]processing_system7_0_M_AXI_GP0_AWSIZE;
wire processing_system7_0_M_AXI_GP0_AWVALID;
wire [11:0]processing_system7_0_M_AXI_GP0_BID;
wire processing_system7_0_M_AXI_GP0_BREADY;
wire [1:0]processing_system7_0_M_AXI_GP0_BRESP;
wire processing_system7_0_M_AXI_GP0_BVALID;
wire [31:0]processing_system7_0_M_AXI_GP0_RDATA;
wire [11:0]processing_system7_0_M_AXI_GP0_RID;
wire processing_system7_0_M_AXI_GP0_RLAST;
wire processing_system7_0_M_AXI_GP0_RREADY;
wire [1:0]processing_system7_0_M_AXI_GP0_RRESP;
wire processing_system7_0_M_AXI_GP0_RVALID;
wire [31:0]processing_system7_0_M_AXI_GP0_WDATA;
wire [11:0]processing_system7_0_M_AXI_GP0_WID;
wire processing_system7_0_M_AXI_GP0_WLAST;
wire processing_system7_0_M_AXI_GP0_WREADY;
wire [3:0]processing_system7_0_M_AXI_GP0_WSTRB;
wire processing_system7_0_M_AXI_GP0_WVALID;
wire [4:0]processing_system7_0_axi_periph_M00_AXI_ARADDR;
wire processing_system7_0_axi_periph_M00_AXI_ARREADY;
wire processing_system7_0_axi_periph_M00_AXI_ARVALID;
wire [4:0]processing_system7_0_axi_periph_M00_AXI_AWADDR;
wire processing_system7_0_axi_periph_M00_AXI_AWREADY;
wire processing_system7_0_axi_periph_M00_AXI_AWVALID;
wire processing_system7_0_axi_periph_M00_AXI_BREADY;
wire [1:0]processing_system7_0_axi_periph_M00_AXI_BRESP;
wire processing_system7_0_axi_periph_M00_AXI_BVALID;
wire [31:0]processing_system7_0_axi_periph_M00_AXI_RDATA;
wire processing_system7_0_axi_periph_M00_AXI_RREADY;
wire [1:0]processing_system7_0_axi_periph_M00_AXI_RRESP;
wire processing_system7_0_axi_periph_M00_AXI_RVALID;
wire [31:0]processing_system7_0_axi_periph_M00_AXI_WDATA;
wire processing_system7_0_axi_periph_M00_AXI_WREADY;
wire [3:0]processing_system7_0_axi_periph_M00_AXI_WSTRB;
wire processing_system7_0_axi_periph_M00_AXI_WVALID;
wire [9:0]processing_system7_0_axi_periph_M01_AXI_ARADDR;
wire processing_system7_0_axi_periph_M01_AXI_ARREADY;
wire processing_system7_0_axi_periph_M01_AXI_ARVALID;
wire [9:0]processing_system7_0_axi_periph_M01_AXI_AWADDR;
wire processing_system7_0_axi_periph_M01_AXI_AWREADY;
wire processing_system7_0_axi_periph_M01_AXI_AWVALID;
wire processing_system7_0_axi_periph_M01_AXI_BREADY;
wire [1:0]processing_system7_0_axi_periph_M01_AXI_BRESP;
wire processing_system7_0_axi_periph_M01_AXI_BVALID;
wire [31:0]processing_system7_0_axi_periph_M01_AXI_RDATA;
wire processing_system7_0_axi_periph_M01_AXI_RREADY;
wire [1:0]processing_system7_0_axi_periph_M01_AXI_RRESP;
wire processing_system7_0_axi_periph_M01_AXI_RVALID;
wire [31:0]processing_system7_0_axi_periph_M01_AXI_WDATA;
wire processing_system7_0_axi_periph_M01_AXI_WREADY;
wire processing_system7_0_axi_periph_M01_AXI_WVALID;
wire [4:0]processing_system7_0_axi_periph_M02_AXI_ARADDR;
wire processing_system7_0_axi_periph_M02_AXI_ARREADY;
wire processing_system7_0_axi_periph_M02_AXI_ARVALID;
wire [4:0]processing_system7_0_axi_periph_M02_AXI_AWADDR;
wire processing_system7_0_axi_periph_M02_AXI_AWREADY;
wire processing_system7_0_axi_periph_M02_AXI_AWVALID;
wire processing_system7_0_axi_periph_M02_AXI_BREADY;
wire [1:0]processing_system7_0_axi_periph_M02_AXI_BRESP;
wire processing_system7_0_axi_periph_M02_AXI_BVALID;
wire [31:0]processing_system7_0_axi_periph_M02_AXI_RDATA;
wire processing_system7_0_axi_periph_M02_AXI_RREADY;
wire [1:0]processing_system7_0_axi_periph_M02_AXI_RRESP;
wire processing_system7_0_axi_periph_M02_AXI_RVALID;
wire [31:0]processing_system7_0_axi_periph_M02_AXI_WDATA;
wire processing_system7_0_axi_periph_M02_AXI_WREADY;
wire [3:0]processing_system7_0_axi_periph_M02_AXI_WSTRB;
wire processing_system7_0_axi_periph_M02_AXI_WVALID;
wire [0:0]rst_processing_system7_0_100M_interconnect_aresetn;
wire [0:0]rst_processing_system7_0_100M_peripheral_aresetn;
wire [1:0]xlconcat_0_dout;
GND GND
(.G(GND_1));
system_HLS_accel_0_0 HLS_accel_0
(.INPUT_STREAM_TDATA(axi_dma_0_M_AXIS_MM2S_TDATA),
.INPUT_STREAM_TDEST({GND_1,GND_1,GND_1,GND_1,GND_1}),
.INPUT_STREAM_TID({GND_1,GND_1,GND_1,GND_1,GND_1}),
.INPUT_STREAM_TKEEP(axi_dma_0_M_AXIS_MM2S_TKEEP),
.INPUT_STREAM_TLAST(axi_dma_0_M_AXIS_MM2S_TLAST),
.INPUT_STREAM_TREADY(axi_dma_0_M_AXIS_MM2S_TREADY),
.INPUT_STREAM_TSTRB({VCC_1,VCC_1,VCC_1}),
.INPUT_STREAM_TUSER({GND_1,GND_1,GND_1,GND_1}),
.INPUT_STREAM_TVALID(axi_dma_0_M_AXIS_MM2S_TVALID),
.OUTPUT_STREAM_TDATA(HLS_accel_0_OUTPUT_STREAM_TDATA),
.OUTPUT_STREAM_TKEEP(HLS_accel_0_OUTPUT_STREAM_TKEEP),
.OUTPUT_STREAM_TLAST(HLS_accel_0_OUTPUT_STREAM_TLAST),
.OUTPUT_STREAM_TREADY(HLS_accel_0_OUTPUT_STREAM_TREADY),
.OUTPUT_STREAM_TVALID(HLS_accel_0_OUTPUT_STREAM_TVALID),
.ap_clk(processing_system7_0_FCLK_CLK0),
.ap_rst_n(rst_processing_system7_0_100M_peripheral_aresetn),
.interrupt(HLS_accel_0_interrupt),
.s_axi_CONTROL_BUS_ARADDR(processing_system7_0_axi_periph_M00_AXI_ARADDR),
.s_axi_CONTROL_BUS_ARREADY(processing_system7_0_axi_periph_M00_AXI_ARREADY),
.s_axi_CONTROL_BUS_ARVALID(processing_system7_0_axi_periph_M00_AXI_ARVALID),
.s_axi_CONTROL_BUS_AWADDR(processing_system7_0_axi_periph_M00_AXI_AWADDR),
.s_axi_CONTROL_BUS_AWREADY(processing_system7_0_axi_periph_M00_AXI_AWREADY),
.s_axi_CONTROL_BUS_AWVALID(processing_system7_0_axi_periph_M00_AXI_AWVALID),
.s_axi_CONTROL_BUS_BREADY(processing_system7_0_axi_periph_M00_AXI_BREADY),
.s_axi_CONTROL_BUS_BRESP(processing_system7_0_axi_periph_M00_AXI_BRESP),
.s_axi_CONTROL_BUS_BVALID(processing_system7_0_axi_periph_M00_AXI_BVALID),
.s_axi_CONTROL_BUS_RDATA(processing_system7_0_axi_periph_M00_AXI_RDATA),
.s_axi_CONTROL_BUS_RREADY(processing_system7_0_axi_periph_M00_AXI_RREADY),
.s_axi_CONTROL_BUS_RRESP(processing_system7_0_axi_periph_M00_AXI_RRESP),
.s_axi_CONTROL_BUS_RVALID(processing_system7_0_axi_periph_M00_AXI_RVALID),
.s_axi_CONTROL_BUS_WDATA(processing_system7_0_axi_periph_M00_AXI_WDATA),
.s_axi_CONTROL_BUS_WREADY(processing_system7_0_axi_periph_M00_AXI_WREADY),
.s_axi_CONTROL_BUS_WSTRB(processing_system7_0_axi_periph_M00_AXI_WSTRB),
.s_axi_CONTROL_BUS_WVALID(processing_system7_0_axi_periph_M00_AXI_WVALID));
VCC VCC
(.P(VCC_1));
system_axi_dma_0_0 axi_dma_0
(.axi_resetn(rst_processing_system7_0_100M_peripheral_aresetn),
.m_axi_mm2s_aclk(processing_system7_0_FCLK_CLK0),
.m_axi_mm2s_araddr(axi_dma_0_M_AXI_MM2S_ARADDR),
.m_axi_mm2s_arburst(axi_dma_0_M_AXI_MM2S_ARBURST),
.m_axi_mm2s_arcache(axi_dma_0_M_AXI_MM2S_ARCACHE),
.m_axi_mm2s_arlen(axi_dma_0_M_AXI_MM2S_ARLEN),
.m_axi_mm2s_arprot(axi_dma_0_M_AXI_MM2S_ARPROT),
.m_axi_mm2s_arready(axi_dma_0_M_AXI_MM2S_ARREADY),
.m_axi_mm2s_arsize(axi_dma_0_M_AXI_MM2S_ARSIZE),
.m_axi_mm2s_arvalid(axi_dma_0_M_AXI_MM2S_ARVALID),
.m_axi_mm2s_rdata(axi_dma_0_M_AXI_MM2S_RDATA),
.m_axi_mm2s_rlast(axi_dma_0_M_AXI_MM2S_RLAST),
.m_axi_mm2s_rready(axi_dma_0_M_AXI_MM2S_RREADY),
.m_axi_mm2s_rresp(axi_dma_0_M_AXI_MM2S_RRESP),
.m_axi_mm2s_rvalid(axi_dma_0_M_AXI_MM2S_RVALID),
.m_axi_s2mm_aclk(processing_system7_0_FCLK_CLK0),
.m_axi_s2mm_awaddr(axi_dma_0_M_AXI_S2MM_AWADDR),
.m_axi_s2mm_awburst(axi_dma_0_M_AXI_S2MM_AWBURST),
.m_axi_s2mm_awcache(axi_dma_0_M_AXI_S2MM_AWCACHE),
.m_axi_s2mm_awlen(axi_dma_0_M_AXI_S2MM_AWLEN),
.m_axi_s2mm_awprot(axi_dma_0_M_AXI_S2MM_AWPROT),
.m_axi_s2mm_awready(axi_dma_0_M_AXI_S2MM_AWREADY),
.m_axi_s2mm_awsize(axi_dma_0_M_AXI_S2MM_AWSIZE),
.m_axi_s2mm_awvalid(axi_dma_0_M_AXI_S2MM_AWVALID),
.m_axi_s2mm_bready(axi_dma_0_M_AXI_S2MM_BREADY),
.m_axi_s2mm_bresp(axi_dma_0_M_AXI_S2MM_BRESP),
.m_axi_s2mm_bvalid(axi_dma_0_M_AXI_S2MM_BVALID),
.m_axi_s2mm_wdata(axi_dma_0_M_AXI_S2MM_WDATA),
.m_axi_s2mm_wlast(axi_dma_0_M_AXI_S2MM_WLAST),
.m_axi_s2mm_wready(axi_dma_0_M_AXI_S2MM_WREADY),
.m_axi_s2mm_wstrb(axi_dma_0_M_AXI_S2MM_WSTRB),
.m_axi_s2mm_wvalid(axi_dma_0_M_AXI_S2MM_WVALID),
.m_axis_mm2s_tdata(axi_dma_0_M_AXIS_MM2S_TDATA),
.m_axis_mm2s_tkeep(axi_dma_0_M_AXIS_MM2S_TKEEP),
.m_axis_mm2s_tlast(axi_dma_0_M_AXIS_MM2S_TLAST),
.m_axis_mm2s_tready(axi_dma_0_M_AXIS_MM2S_TREADY),
.m_axis_mm2s_tvalid(axi_dma_0_M_AXIS_MM2S_TVALID),
.s_axi_lite_aclk(processing_system7_0_FCLK_CLK0),
.s_axi_lite_araddr(processing_system7_0_axi_periph_M01_AXI_ARADDR),
.s_axi_lite_arready(processing_system7_0_axi_periph_M01_AXI_ARREADY),
.s_axi_lite_arvalid(processing_system7_0_axi_periph_M01_AXI_ARVALID),
.s_axi_lite_awaddr(processing_system7_0_axi_periph_M01_AXI_AWADDR),
.s_axi_lite_awready(processing_system7_0_axi_periph_M01_AXI_AWREADY),
.s_axi_lite_awvalid(processing_system7_0_axi_periph_M01_AXI_AWVALID),
.s_axi_lite_bready(processing_system7_0_axi_periph_M01_AXI_BREADY),
.s_axi_lite_bresp(processing_system7_0_axi_periph_M01_AXI_BRESP),
.s_axi_lite_bvalid(processing_system7_0_axi_periph_M01_AXI_BVALID),
.s_axi_lite_rdata(processing_system7_0_axi_periph_M01_AXI_RDATA),
.s_axi_lite_rready(processing_system7_0_axi_periph_M01_AXI_RREADY),
.s_axi_lite_rresp(processing_system7_0_axi_periph_M01_AXI_RRESP),
.s_axi_lite_rvalid(processing_system7_0_axi_periph_M01_AXI_RVALID),
.s_axi_lite_wdata(processing_system7_0_axi_periph_M01_AXI_WDATA),
.s_axi_lite_wready(processing_system7_0_axi_periph_M01_AXI_WREADY),
.s_axi_lite_wvalid(processing_system7_0_axi_periph_M01_AXI_WVALID),
.s_axis_s2mm_tdata(HLS_accel_0_OUTPUT_STREAM_TDATA),
.s_axis_s2mm_tkeep(HLS_accel_0_OUTPUT_STREAM_TKEEP),
.s_axis_s2mm_tlast(HLS_accel_0_OUTPUT_STREAM_TLAST),
.s_axis_s2mm_tready(HLS_accel_0_OUTPUT_STREAM_TREADY),
.s_axis_s2mm_tvalid(HLS_accel_0_OUTPUT_STREAM_TVALID));
system_axi_mem_intercon_0 axi_mem_intercon
(.ACLK(processing_system7_0_FCLK_CLK0),
.ARESETN(rst_processing_system7_0_100M_interconnect_aresetn),
.M00_ACLK(processing_system7_0_FCLK_CLK0),
.M00_ARESETN(rst_processing_system7_0_100M_peripheral_aresetn),
.M00_AXI_araddr(axi_mem_intercon_M00_AXI_ARADDR),
.M00_AXI_arburst(axi_mem_intercon_M00_AXI_ARBURST),
.M00_AXI_arcache(axi_mem_intercon_M00_AXI_ARCACHE),
.M00_AXI_arid(axi_mem_intercon_M00_AXI_ARID),
.M00_AXI_arlen(axi_mem_intercon_M00_AXI_ARLEN),
.M00_AXI_arlock(axi_mem_intercon_M00_AXI_ARLOCK),
.M00_AXI_arprot(axi_mem_intercon_M00_AXI_ARPROT),
.M00_AXI_arqos(axi_mem_intercon_M00_AXI_ARQOS),
.M00_AXI_arready(axi_mem_intercon_M00_AXI_ARREADY),
.M00_AXI_arsize(axi_mem_intercon_M00_AXI_ARSIZE),
.M00_AXI_arvalid(axi_mem_intercon_M00_AXI_ARVALID),
.M00_AXI_awaddr(axi_mem_intercon_M00_AXI_AWADDR),
.M00_AXI_awburst(axi_mem_intercon_M00_AXI_AWBURST),
.M00_AXI_awcache(axi_mem_intercon_M00_AXI_AWCACHE),
.M00_AXI_awid(axi_mem_intercon_M00_AXI_AWID),
.M00_AXI_awlen(axi_mem_intercon_M00_AXI_AWLEN),
.M00_AXI_awlock(axi_mem_intercon_M00_AXI_AWLOCK),
.M00_AXI_awprot(axi_mem_intercon_M00_AXI_AWPROT),
.M00_AXI_awqos(axi_mem_intercon_M00_AXI_AWQOS),
.M00_AXI_awready(axi_mem_intercon_M00_AXI_AWREADY),
.M00_AXI_awsize(axi_mem_intercon_M00_AXI_AWSIZE),
.M00_AXI_awvalid(axi_mem_intercon_M00_AXI_AWVALID),
.M00_AXI_bid(axi_mem_intercon_M00_AXI_BID[0]),
.M00_AXI_bready(axi_mem_intercon_M00_AXI_BREADY),
.M00_AXI_bresp(axi_mem_intercon_M00_AXI_BRESP),
.M00_AXI_bvalid(axi_mem_intercon_M00_AXI_BVALID),
.M00_AXI_rdata(axi_mem_intercon_M00_AXI_RDATA),
.M00_AXI_rid(axi_mem_intercon_M00_AXI_RID[0]),
.M00_AXI_rlast(axi_mem_intercon_M00_AXI_RLAST),
.M00_AXI_rready(axi_mem_intercon_M00_AXI_RREADY),
.M00_AXI_rresp(axi_mem_intercon_M00_AXI_RRESP),
.M00_AXI_rvalid(axi_mem_intercon_M00_AXI_RVALID),
.M00_AXI_wdata(axi_mem_intercon_M00_AXI_WDATA),
.M00_AXI_wid(axi_mem_intercon_M00_AXI_WID),
.M00_AXI_wlast(axi_mem_intercon_M00_AXI_WLAST),
.M00_AXI_wready(axi_mem_intercon_M00_AXI_WREADY),
.M00_AXI_wstrb(axi_mem_intercon_M00_AXI_WSTRB),
.M00_AXI_wvalid(axi_mem_intercon_M00_AXI_WVALID),
.S00_ACLK(processing_system7_0_FCLK_CLK0),
.S00_ARESETN(rst_processing_system7_0_100M_peripheral_aresetn),
.S00_AXI_araddr(axi_dma_0_M_AXI_MM2S_ARADDR),
.S00_AXI_arburst(axi_dma_0_M_AXI_MM2S_ARBURST),
.S00_AXI_arcache(axi_dma_0_M_AXI_MM2S_ARCACHE),
.S00_AXI_arlen(axi_dma_0_M_AXI_MM2S_ARLEN),
.S00_AXI_arprot(axi_dma_0_M_AXI_MM2S_ARPROT),
.S00_AXI_arready(axi_dma_0_M_AXI_MM2S_ARREADY),
.S00_AXI_arsize(axi_dma_0_M_AXI_MM2S_ARSIZE),
.S00_AXI_arvalid(axi_dma_0_M_AXI_MM2S_ARVALID),
.S00_AXI_rdata(axi_dma_0_M_AXI_MM2S_RDATA),
.S00_AXI_rlast(axi_dma_0_M_AXI_MM2S_RLAST),
.S00_AXI_rready(axi_dma_0_M_AXI_MM2S_RREADY),
.S00_AXI_rresp(axi_dma_0_M_AXI_MM2S_RRESP),
.S00_AXI_rvalid(axi_dma_0_M_AXI_MM2S_RVALID),
.S01_ACLK(processing_system7_0_FCLK_CLK0),
.S01_ARESETN(rst_processing_system7_0_100M_peripheral_aresetn),
.S01_AXI_awaddr(axi_dma_0_M_AXI_S2MM_AWADDR),
.S01_AXI_awburst(axi_dma_0_M_AXI_S2MM_AWBURST),
.S01_AXI_awcache(axi_dma_0_M_AXI_S2MM_AWCACHE),
.S01_AXI_awlen(axi_dma_0_M_AXI_S2MM_AWLEN),
.S01_AXI_awprot(axi_dma_0_M_AXI_S2MM_AWPROT),
.S01_AXI_awready(axi_dma_0_M_AXI_S2MM_AWREADY),
.S01_AXI_awsize(axi_dma_0_M_AXI_S2MM_AWSIZE),
.S01_AXI_awvalid(axi_dma_0_M_AXI_S2MM_AWVALID),
.S01_AXI_bready(axi_dma_0_M_AXI_S2MM_BREADY),
.S01_AXI_bresp(axi_dma_0_M_AXI_S2MM_BRESP),
.S01_AXI_bvalid(axi_dma_0_M_AXI_S2MM_BVALID),
.S01_AXI_wdata(axi_dma_0_M_AXI_S2MM_WDATA),
.S01_AXI_wlast(axi_dma_0_M_AXI_S2MM_WLAST),
.S01_AXI_wready(axi_dma_0_M_AXI_S2MM_WREADY),
.S01_AXI_wstrb(axi_dma_0_M_AXI_S2MM_WSTRB),
.S01_AXI_wvalid(axi_dma_0_M_AXI_S2MM_WVALID));
system_axi_timer_0_0 axi_timer_0
(.capturetrig0(GND_1),
.capturetrig1(GND_1),
.freeze(GND_1),
.interrupt(axi_timer_0_interrupt),
.s_axi_aclk(processing_system7_0_FCLK_CLK0),
.s_axi_araddr(processing_system7_0_axi_periph_M02_AXI_ARADDR),
.s_axi_aresetn(rst_processing_system7_0_100M_peripheral_aresetn),
.s_axi_arready(processing_system7_0_axi_periph_M02_AXI_ARREADY),
.s_axi_arvalid(processing_system7_0_axi_periph_M02_AXI_ARVALID),
.s_axi_awaddr(processing_system7_0_axi_periph_M02_AXI_AWADDR),
.s_axi_awready(processing_system7_0_axi_periph_M02_AXI_AWREADY),
.s_axi_awvalid(processing_system7_0_axi_periph_M02_AXI_AWVALID),
.s_axi_bready(processing_system7_0_axi_periph_M02_AXI_BREADY),
.s_axi_bresp(processing_system7_0_axi_periph_M02_AXI_BRESP),
.s_axi_bvalid(processing_system7_0_axi_periph_M02_AXI_BVALID),
.s_axi_rdata(processing_system7_0_axi_periph_M02_AXI_RDATA),
.s_axi_rready(processing_system7_0_axi_periph_M02_AXI_RREADY),
.s_axi_rresp(processing_system7_0_axi_periph_M02_AXI_RRESP),
.s_axi_rvalid(processing_system7_0_axi_periph_M02_AXI_RVALID),
.s_axi_wdata(processing_system7_0_axi_periph_M02_AXI_WDATA),
.s_axi_wready(processing_system7_0_axi_periph_M02_AXI_WREADY),
.s_axi_wstrb(processing_system7_0_axi_periph_M02_AXI_WSTRB),
.s_axi_wvalid(processing_system7_0_axi_periph_M02_AXI_WVALID));
system_processing_system7_0_0 processing_system7_0
(.DDR_Addr(DDR_addr[14:0]),
.DDR_BankAddr(DDR_ba[2:0]),
.DDR_CAS_n(DDR_cas_n),
.DDR_CKE(DDR_cke),
.DDR_CS_n(DDR_cs_n),
.DDR_Clk(DDR_ck_p),
.DDR_Clk_n(DDR_ck_n),
.DDR_DM(DDR_dm[3:0]),
.DDR_DQ(DDR_dq[31:0]),
.DDR_DQS(DDR_dqs_p[3:0]),
.DDR_DQS_n(DDR_dqs_n[3:0]),
.DDR_DRSTB(DDR_reset_n),
.DDR_ODT(DDR_odt),
.DDR_RAS_n(DDR_ras_n),
.DDR_VRN(FIXED_IO_ddr_vrn),
.DDR_VRP(FIXED_IO_ddr_vrp),
.DDR_WEB(DDR_we_n),
.FCLK_CLK0(processing_system7_0_FCLK_CLK0),
.FCLK_RESET0_N(processing_system7_0_FCLK_RESET0_N),
.IRQ_F2P(xlconcat_0_dout),
.MIO(FIXED_IO_mio[53:0]),
.M_AXI_GP0_ACLK(processing_system7_0_FCLK_CLK0),
.M_AXI_GP0_ARADDR(processing_system7_0_M_AXI_GP0_ARADDR),
.M_AXI_GP0_ARBURST(processing_system7_0_M_AXI_GP0_ARBURST),
.M_AXI_GP0_ARCACHE(processing_system7_0_M_AXI_GP0_ARCACHE),
.M_AXI_GP0_ARID(processing_system7_0_M_AXI_GP0_ARID),
.M_AXI_GP0_ARLEN(processing_system7_0_M_AXI_GP0_ARLEN),
.M_AXI_GP0_ARLOCK(processing_system7_0_M_AXI_GP0_ARLOCK),
.M_AXI_GP0_ARPROT(processing_system7_0_M_AXI_GP0_ARPROT),
.M_AXI_GP0_ARQOS(processing_system7_0_M_AXI_GP0_ARQOS),
.M_AXI_GP0_ARREADY(processing_system7_0_M_AXI_GP0_ARREADY),
.M_AXI_GP0_ARSIZE(processing_system7_0_M_AXI_GP0_ARSIZE),
.M_AXI_GP0_ARVALID(processing_system7_0_M_AXI_GP0_ARVALID),
.M_AXI_GP0_AWADDR(processing_system7_0_M_AXI_GP0_AWADDR),
.M_AXI_GP0_AWBURST(processing_system7_0_M_AXI_GP0_AWBURST),
.M_AXI_GP0_AWCACHE(processing_system7_0_M_AXI_GP0_AWCACHE),
.M_AXI_GP0_AWID(processing_system7_0_M_AXI_GP0_AWID),
.M_AXI_GP0_AWLEN(processing_system7_0_M_AXI_GP0_AWLEN),
.M_AXI_GP0_AWLOCK(processing_system7_0_M_AXI_GP0_AWLOCK),
.M_AXI_GP0_AWPROT(processing_system7_0_M_AXI_GP0_AWPROT),
.M_AXI_GP0_AWQOS(processing_system7_0_M_AXI_GP0_AWQOS),
.M_AXI_GP0_AWREADY(processing_system7_0_M_AXI_GP0_AWREADY),
.M_AXI_GP0_AWSIZE(processing_system7_0_M_AXI_GP0_AWSIZE),
.M_AXI_GP0_AWVALID(processing_system7_0_M_AXI_GP0_AWVALID),
.M_AXI_GP0_BID(processing_system7_0_M_AXI_GP0_BID),
.M_AXI_GP0_BREADY(processing_system7_0_M_AXI_GP0_BREADY),
.M_AXI_GP0_BRESP(processing_system7_0_M_AXI_GP0_BRESP),
.M_AXI_GP0_BVALID(processing_system7_0_M_AXI_GP0_BVALID),
.M_AXI_GP0_RDATA(processing_system7_0_M_AXI_GP0_RDATA),
.M_AXI_GP0_RID(processing_system7_0_M_AXI_GP0_RID),
.M_AXI_GP0_RLAST(processing_system7_0_M_AXI_GP0_RLAST),
.M_AXI_GP0_RREADY(processing_system7_0_M_AXI_GP0_RREADY),
.M_AXI_GP0_RRESP(processing_system7_0_M_AXI_GP0_RRESP),
.M_AXI_GP0_RVALID(processing_system7_0_M_AXI_GP0_RVALID),
.M_AXI_GP0_WDATA(processing_system7_0_M_AXI_GP0_WDATA),
.M_AXI_GP0_WID(processing_system7_0_M_AXI_GP0_WID),
.M_AXI_GP0_WLAST(processing_system7_0_M_AXI_GP0_WLAST),
.M_AXI_GP0_WREADY(processing_system7_0_M_AXI_GP0_WREADY),
.M_AXI_GP0_WSTRB(processing_system7_0_M_AXI_GP0_WSTRB),
.M_AXI_GP0_WVALID(processing_system7_0_M_AXI_GP0_WVALID),
.PS_CLK(FIXED_IO_ps_clk),
.PS_PORB(FIXED_IO_ps_porb),
.PS_SRSTB(FIXED_IO_ps_srstb),
.S_AXI_ACP_ACLK(processing_system7_0_FCLK_CLK0),
.S_AXI_ACP_ARADDR(axi_mem_intercon_M00_AXI_ARADDR),
.S_AXI_ACP_ARBURST(axi_mem_intercon_M00_AXI_ARBURST),
.S_AXI_ACP_ARCACHE(axi_mem_intercon_M00_AXI_ARCACHE),
.S_AXI_ACP_ARID(axi_mem_intercon_M00_AXI_ARID),
.S_AXI_ACP_ARLEN(axi_mem_intercon_M00_AXI_ARLEN),
.S_AXI_ACP_ARLOCK(axi_mem_intercon_M00_AXI_ARLOCK),
.S_AXI_ACP_ARPROT(axi_mem_intercon_M00_AXI_ARPROT),
.S_AXI_ACP_ARQOS(axi_mem_intercon_M00_AXI_ARQOS),
.S_AXI_ACP_ARREADY(axi_mem_intercon_M00_AXI_ARREADY),
.S_AXI_ACP_ARSIZE(axi_mem_intercon_M00_AXI_ARSIZE),
.S_AXI_ACP_ARUSER({GND_1,GND_1,GND_1,GND_1,GND_1}),
.S_AXI_ACP_ARVALID(axi_mem_intercon_M00_AXI_ARVALID),
.S_AXI_ACP_AWADDR(axi_mem_intercon_M00_AXI_AWADDR),
.S_AXI_ACP_AWBURST(axi_mem_intercon_M00_AXI_AWBURST),
.S_AXI_ACP_AWCACHE(axi_mem_intercon_M00_AXI_AWCACHE),
.S_AXI_ACP_AWID(axi_mem_intercon_M00_AXI_AWID),
.S_AXI_ACP_AWLEN(axi_mem_intercon_M00_AXI_AWLEN),
.S_AXI_ACP_AWLOCK(axi_mem_intercon_M00_AXI_AWLOCK),
.S_AXI_ACP_AWPROT(axi_mem_intercon_M00_AXI_AWPROT),
.S_AXI_ACP_AWQOS(axi_mem_intercon_M00_AXI_AWQOS),
.S_AXI_ACP_AWREADY(axi_mem_intercon_M00_AXI_AWREADY),
.S_AXI_ACP_AWSIZE(axi_mem_intercon_M00_AXI_AWSIZE),
.S_AXI_ACP_AWUSER({GND_1,GND_1,GND_1,GND_1,GND_1}),
.S_AXI_ACP_AWVALID(axi_mem_intercon_M00_AXI_AWVALID),
.S_AXI_ACP_BID(axi_mem_intercon_M00_AXI_BID),
.S_AXI_ACP_BREADY(axi_mem_intercon_M00_AXI_BREADY),
.S_AXI_ACP_BRESP(axi_mem_intercon_M00_AXI_BRESP),
.S_AXI_ACP_BVALID(axi_mem_intercon_M00_AXI_BVALID),
.S_AXI_ACP_RDATA(axi_mem_intercon_M00_AXI_RDATA),
.S_AXI_ACP_RID(axi_mem_intercon_M00_AXI_RID),
.S_AXI_ACP_RLAST(axi_mem_intercon_M00_AXI_RLAST),
.S_AXI_ACP_RREADY(axi_mem_intercon_M00_AXI_RREADY),
.S_AXI_ACP_RRESP(axi_mem_intercon_M00_AXI_RRESP),
.S_AXI_ACP_RVALID(axi_mem_intercon_M00_AXI_RVALID),
.S_AXI_ACP_WDATA(axi_mem_intercon_M00_AXI_WDATA),
.S_AXI_ACP_WID(axi_mem_intercon_M00_AXI_WID),
.S_AXI_ACP_WLAST(axi_mem_intercon_M00_AXI_WLAST),
.S_AXI_ACP_WREADY(axi_mem_intercon_M00_AXI_WREADY),
.S_AXI_ACP_WSTRB(axi_mem_intercon_M00_AXI_WSTRB),
.S_AXI_ACP_WVALID(axi_mem_intercon_M00_AXI_WVALID),
.USB0_VBUS_PWRFAULT(GND_1));
system_processing_system7_0_axi_periph_0 processing_system7_0_axi_periph
(.ACLK(processing_system7_0_FCLK_CLK0),
.ARESETN(rst_processing_system7_0_100M_interconnect_aresetn),
.M00_ACLK(processing_system7_0_FCLK_CLK0),
.M00_ARESETN(rst_processing_system7_0_100M_peripheral_aresetn),
.M00_AXI_araddr(processing_system7_0_axi_periph_M00_AXI_ARADDR),
.M00_AXI_arready(processing_system7_0_axi_periph_M00_AXI_ARREADY),
.M00_AXI_arvalid(processing_system7_0_axi_periph_M00_AXI_ARVALID),
.M00_AXI_awaddr(processing_system7_0_axi_periph_M00_AXI_AWADDR),
.M00_AXI_awready(processing_system7_0_axi_periph_M00_AXI_AWREADY),
.M00_AXI_awvalid(processing_system7_0_axi_periph_M00_AXI_AWVALID),
.M00_AXI_bready(processing_system7_0_axi_periph_M00_AXI_BREADY),
.M00_AXI_bresp(processing_system7_0_axi_periph_M00_AXI_BRESP),
.M00_AXI_bvalid(processing_system7_0_axi_periph_M00_AXI_BVALID),
.M00_AXI_rdata(processing_system7_0_axi_periph_M00_AXI_RDATA),
.M00_AXI_rready(processing_system7_0_axi_periph_M00_AXI_RREADY),
.M00_AXI_rresp(processing_system7_0_axi_periph_M00_AXI_RRESP),
.M00_AXI_rvalid(processing_system7_0_axi_periph_M00_AXI_RVALID),
.M00_AXI_wdata(processing_system7_0_axi_periph_M00_AXI_WDATA),
.M00_AXI_wready(processing_system7_0_axi_periph_M00_AXI_WREADY),
.M00_AXI_wstrb(processing_system7_0_axi_periph_M00_AXI_WSTRB),
.M00_AXI_wvalid(processing_system7_0_axi_periph_M00_AXI_WVALID),
.M01_ACLK(processing_system7_0_FCLK_CLK0),
.M01_ARESETN(rst_processing_system7_0_100M_peripheral_aresetn),
.M01_AXI_araddr(processing_system7_0_axi_periph_M01_AXI_ARADDR),
.M01_AXI_arready(processing_system7_0_axi_periph_M01_AXI_ARREADY),
.M01_AXI_arvalid(processing_system7_0_axi_periph_M01_AXI_ARVALID),
.M01_AXI_awaddr(processing_system7_0_axi_periph_M01_AXI_AWADDR),
.M01_AXI_awready(processing_system7_0_axi_periph_M01_AXI_AWREADY),
.M01_AXI_awvalid(processing_system7_0_axi_periph_M01_AXI_AWVALID),
.M01_AXI_bready(processing_system7_0_axi_periph_M01_AXI_BREADY),
.M01_AXI_bresp(processing_system7_0_axi_periph_M01_AXI_BRESP),
.M01_AXI_bvalid(processing_system7_0_axi_periph_M01_AXI_BVALID),
.M01_AXI_rdata(processing_system7_0_axi_periph_M01_AXI_RDATA),
.M01_AXI_rready(processing_system7_0_axi_periph_M01_AXI_RREADY),
.M01_AXI_rresp(processing_system7_0_axi_periph_M01_AXI_RRESP),
.M01_AXI_rvalid(processing_system7_0_axi_periph_M01_AXI_RVALID),
.M01_AXI_wdata(processing_system7_0_axi_periph_M01_AXI_WDATA),
.M01_AXI_wready(processing_system7_0_axi_periph_M01_AXI_WREADY),
.M01_AXI_wvalid(processing_system7_0_axi_periph_M01_AXI_WVALID),
.M02_ACLK(processing_system7_0_FCLK_CLK0),
.M02_ARESETN(rst_processing_system7_0_100M_peripheral_aresetn),
.M02_AXI_araddr(processing_system7_0_axi_periph_M02_AXI_ARADDR),
.M02_AXI_arready(processing_system7_0_axi_periph_M02_AXI_ARREADY),
.M02_AXI_arvalid(processing_system7_0_axi_periph_M02_AXI_ARVALID),
.M02_AXI_awaddr(processing_system7_0_axi_periph_M02_AXI_AWADDR),
.M02_AXI_awready(processing_system7_0_axi_periph_M02_AXI_AWREADY),
.M02_AXI_awvalid(processing_system7_0_axi_periph_M02_AXI_AWVALID),
.M02_AXI_bready(processing_system7_0_axi_periph_M02_AXI_BREADY),
.M02_AXI_bresp(processing_system7_0_axi_periph_M02_AXI_BRESP),
.M02_AXI_bvalid(processing_system7_0_axi_periph_M02_AXI_BVALID),
.M02_AXI_rdata(processing_system7_0_axi_periph_M02_AXI_RDATA),
.M02_AXI_rready(processing_system7_0_axi_periph_M02_AXI_RREADY),
.M02_AXI_rresp(processing_system7_0_axi_periph_M02_AXI_RRESP),
.M02_AXI_rvalid(processing_system7_0_axi_periph_M02_AXI_RVALID),
.M02_AXI_wdata(processing_system7_0_axi_periph_M02_AXI_WDATA),
.M02_AXI_wready(processing_system7_0_axi_periph_M02_AXI_WREADY),
.M02_AXI_wstrb(processing_system7_0_axi_periph_M02_AXI_WSTRB),
.M02_AXI_wvalid(processing_system7_0_axi_periph_M02_AXI_WVALID),
.S00_ACLK(processing_system7_0_FCLK_CLK0),
.S00_ARESETN(rst_processing_system7_0_100M_peripheral_aresetn),
.S00_AXI_araddr(processing_system7_0_M_AXI_GP0_ARADDR),
.S00_AXI_arburst(processing_system7_0_M_AXI_GP0_ARBURST),
.S00_AXI_arcache(processing_system7_0_M_AXI_GP0_ARCACHE),
.S00_AXI_arid(processing_system7_0_M_AXI_GP0_ARID),
.S00_AXI_arlen(processing_system7_0_M_AXI_GP0_ARLEN),
.S00_AXI_arlock(processing_system7_0_M_AXI_GP0_ARLOCK),
.S00_AXI_arprot(processing_system7_0_M_AXI_GP0_ARPROT),
.S00_AXI_arqos(processing_system7_0_M_AXI_GP0_ARQOS),
.S00_AXI_arready(processing_system7_0_M_AXI_GP0_ARREADY),
.S00_AXI_arsize(processing_system7_0_M_AXI_GP0_ARSIZE),
.S00_AXI_arvalid(processing_system7_0_M_AXI_GP0_ARVALID),
.S00_AXI_awaddr(processing_system7_0_M_AXI_GP0_AWADDR),
.S00_AXI_awburst(processing_system7_0_M_AXI_GP0_AWBURST),
.S00_AXI_awcache(processing_system7_0_M_AXI_GP0_AWCACHE),
.S00_AXI_awid(processing_system7_0_M_AXI_GP0_AWID),
.S00_AXI_awlen(processing_system7_0_M_AXI_GP0_AWLEN),
.S00_AXI_awlock(processing_system7_0_M_AXI_GP0_AWLOCK),
.S00_AXI_awprot(processing_system7_0_M_AXI_GP0_AWPROT),
.S00_AXI_awqos(processing_system7_0_M_AXI_GP0_AWQOS),
.S00_AXI_awready(processing_system7_0_M_AXI_GP0_AWREADY),
.S00_AXI_awsize(processing_system7_0_M_AXI_GP0_AWSIZE),
.S00_AXI_awvalid(processing_system7_0_M_AXI_GP0_AWVALID),
.S00_AXI_bid(processing_system7_0_M_AXI_GP0_BID),
.S00_AXI_bready(processing_system7_0_M_AXI_GP0_BREADY),
.S00_AXI_bresp(processing_system7_0_M_AXI_GP0_BRESP),
.S00_AXI_bvalid(processing_system7_0_M_AXI_GP0_BVALID),
.S00_AXI_rdata(processing_system7_0_M_AXI_GP0_RDATA),
.S00_AXI_rid(processing_system7_0_M_AXI_GP0_RID),
.S00_AXI_rlast(processing_system7_0_M_AXI_GP0_RLAST),
.S00_AXI_rready(processing_system7_0_M_AXI_GP0_RREADY),
.S00_AXI_rresp(processing_system7_0_M_AXI_GP0_RRESP),
.S00_AXI_rvalid(processing_system7_0_M_AXI_GP0_RVALID),
.S00_AXI_wdata(processing_system7_0_M_AXI_GP0_WDATA),
.S00_AXI_wid(processing_system7_0_M_AXI_GP0_WID),
.S00_AXI_wlast(processing_system7_0_M_AXI_GP0_WLAST),
.S00_AXI_wready(processing_system7_0_M_AXI_GP0_WREADY),
.S00_AXI_wstrb(processing_system7_0_M_AXI_GP0_WSTRB),
.S00_AXI_wvalid(processing_system7_0_M_AXI_GP0_WVALID));
system_rst_processing_system7_0_100M_0 rst_processing_system7_0_100M
(.aux_reset_in(VCC_1),
.dcm_locked(VCC_1),
.ext_reset_in(processing_system7_0_FCLK_RESET0_N),
.interconnect_aresetn(rst_processing_system7_0_100M_interconnect_aresetn),
.mb_debug_sys_rst(GND_1),
.peripheral_aresetn(rst_processing_system7_0_100M_peripheral_aresetn),
.slowest_sync_clk(processing_system7_0_FCLK_CLK0));
system_xlconcat_0_0 xlconcat_0
(.In0(HLS_accel_0_interrupt),
.In1(axi_timer_0_interrupt),
.dout(xlconcat_0_dout));
endmodule |
module system_axi_mem_intercon_0
(ACLK,
ARESETN,
M00_ACLK,
M00_ARESETN,
M00_AXI_araddr,
M00_AXI_arburst,
M00_AXI_arcache,
M00_AXI_arid,
M00_AXI_arlen,
M00_AXI_arlock,
M00_AXI_arprot,
M00_AXI_arqos,
M00_AXI_arready,
M00_AXI_arsize,
M00_AXI_arvalid,
M00_AXI_awaddr,
M00_AXI_awburst,
M00_AXI_awcache,
M00_AXI_awid,
M00_AXI_awlen,
M00_AXI_awlock,
M00_AXI_awprot,
M00_AXI_awqos,
M00_AXI_awready,
M00_AXI_awsize,
M00_AXI_awvalid,
M00_AXI_bid,
M00_AXI_bready,
M00_AXI_bresp,
M00_AXI_bvalid,
M00_AXI_rdata,
M00_AXI_rid,
M00_AXI_rlast,
M00_AXI_rready,
M00_AXI_rresp,
M00_AXI_rvalid,
M00_AXI_wdata,
M00_AXI_wid,
M00_AXI_wlast,
M00_AXI_wready,
M00_AXI_wstrb,
M00_AXI_wvalid,
S00_ACLK,
S00_ARESETN,
S00_AXI_araddr,
S00_AXI_arburst,
S00_AXI_arcache,
S00_AXI_arlen,
S00_AXI_arprot,
S00_AXI_arready,
S00_AXI_arsize,
S00_AXI_arvalid,
S00_AXI_rdata,
S00_AXI_rlast,
S00_AXI_rready,
S00_AXI_rresp,
S00_AXI_rvalid,
S01_ACLK,
S01_ARESETN,
S01_AXI_awaddr,
S01_AXI_awburst,
S01_AXI_awcache,
S01_AXI_awlen,
S01_AXI_awprot,
S01_AXI_awready,
S01_AXI_awsize,
S01_AXI_awvalid,
S01_AXI_bready,
S01_AXI_bresp,
S01_AXI_bvalid,
S01_AXI_wdata,
S01_AXI_wlast,
S01_AXI_wready,
S01_AXI_wstrb,
S01_AXI_wvalid);
input ACLK;
input [0:0]ARESETN;
input M00_ACLK;
input [0:0]M00_ARESETN;
output [31:0]M00_AXI_araddr;
output [1:0]M00_AXI_arburst;
output [3:0]M00_AXI_arcache;
output [0:0]M00_AXI_arid;
output [3:0]M00_AXI_arlen;
output [1:0]M00_AXI_arlock;
output [2:0]M00_AXI_arprot;
output [3:0]M00_AXI_arqos;
input M00_AXI_arready;
output [2:0]M00_AXI_arsize;
output M00_AXI_arvalid;
output [31:0]M00_AXI_awaddr;
output [1:0]M00_AXI_awburst;
output [3:0]M00_AXI_awcache;
output [0:0]M00_AXI_awid;
output [3:0]M00_AXI_awlen;
output [1:0]M00_AXI_awlock;
output [2:0]M00_AXI_awprot;
output [3:0]M00_AXI_awqos;
input M00_AXI_awready;
output [2:0]M00_AXI_awsize;
output M00_AXI_awvalid;
input [0:0]M00_AXI_bid;
output M00_AXI_bready;
input [1:0]M00_AXI_bresp;
input M00_AXI_bvalid;
input [63:0]M00_AXI_rdata;
input [0:0]M00_AXI_rid;
input M00_AXI_rlast;
output M00_AXI_rready;
input [1:0]M00_AXI_rresp;
input M00_AXI_rvalid;
output [63:0]M00_AXI_wdata;
output [0:0]M00_AXI_wid;
output M00_AXI_wlast;
input M00_AXI_wready;
output [7:0]M00_AXI_wstrb;
output M00_AXI_wvalid;
input S00_ACLK;
input [0:0]S00_ARESETN;
input [31:0]S00_AXI_araddr;
input [1:0]S00_AXI_arburst;
input [3:0]S00_AXI_arcache;
input [7:0]S00_AXI_arlen;
input [2:0]S00_AXI_arprot;
output S00_AXI_arready;
input [2:0]S00_AXI_arsize;
input S00_AXI_arvalid;
output [31:0]S00_AXI_rdata;
output S00_AXI_rlast;
input S00_AXI_rready;
output [1:0]S00_AXI_rresp;
output S00_AXI_rvalid;
input S01_ACLK;
input [0:0]S01_ARESETN;
input [31:0]S01_AXI_awaddr;
input [1:0]S01_AXI_awburst;
input [3:0]S01_AXI_awcache;
input [7:0]S01_AXI_awlen;
input [2:0]S01_AXI_awprot;
output S01_AXI_awready;
input [2:0]S01_AXI_awsize;
input S01_AXI_awvalid;
input S01_AXI_bready;
output [1:0]S01_AXI_bresp;
output S01_AXI_bvalid;
input [31:0]S01_AXI_wdata;
input S01_AXI_wlast;
output S01_AXI_wready;
input [3:0]S01_AXI_wstrb;
input S01_AXI_wvalid;
wire GND_1;
wire M00_ACLK_1;
wire [0:0]M00_ARESETN_1;
wire S00_ACLK_1;
wire [0:0]S00_ARESETN_1;
wire S01_ACLK_1;
wire [0:0]S01_ARESETN_1;
wire VCC_1;
wire axi_mem_intercon_ACLK_net;
wire [0:0]axi_mem_intercon_ARESETN_net;
wire [31:0]axi_mem_intercon_to_s00_couplers_ARADDR;
wire [1:0]axi_mem_intercon_to_s00_couplers_ARBURST;
wire [3:0]axi_mem_intercon_to_s00_couplers_ARCACHE;
wire [7:0]axi_mem_intercon_to_s00_couplers_ARLEN;
wire [2:0]axi_mem_intercon_to_s00_couplers_ARPROT;
wire axi_mem_intercon_to_s00_couplers_ARREADY;
wire [2:0]axi_mem_intercon_to_s00_couplers_ARSIZE;
wire axi_mem_intercon_to_s00_couplers_ARVALID;
wire [31:0]axi_mem_intercon_to_s00_couplers_RDATA;
wire axi_mem_intercon_to_s00_couplers_RLAST;
wire axi_mem_intercon_to_s00_couplers_RREADY;
wire [1:0]axi_mem_intercon_to_s00_couplers_RRESP;
wire axi_mem_intercon_to_s00_couplers_RVALID;
wire [31:0]axi_mem_intercon_to_s01_couplers_AWADDR;
wire [1:0]axi_mem_intercon_to_s01_couplers_AWBURST;
wire [3:0]axi_mem_intercon_to_s01_couplers_AWCACHE;
wire [7:0]axi_mem_intercon_to_s01_couplers_AWLEN;
wire [2:0]axi_mem_intercon_to_s01_couplers_AWPROT;
wire axi_mem_intercon_to_s01_couplers_AWREADY;
wire [2:0]axi_mem_intercon_to_s01_couplers_AWSIZE;
wire axi_mem_intercon_to_s01_couplers_AWVALID;
wire axi_mem_intercon_to_s01_couplers_BREADY;
wire [1:0]axi_mem_intercon_to_s01_couplers_BRESP;
wire axi_mem_intercon_to_s01_couplers_BVALID;
wire [31:0]axi_mem_intercon_to_s01_couplers_WDATA;
wire axi_mem_intercon_to_s01_couplers_WLAST;
wire axi_mem_intercon_to_s01_couplers_WREADY;
wire [3:0]axi_mem_intercon_to_s01_couplers_WSTRB;
wire axi_mem_intercon_to_s01_couplers_WVALID;
wire [31:0]m00_couplers_to_axi_mem_intercon_ARADDR;
wire [1:0]m00_couplers_to_axi_mem_intercon_ARBURST;
wire [3:0]m00_couplers_to_axi_mem_intercon_ARCACHE;
wire [0:0]m00_couplers_to_axi_mem_intercon_ARID;
wire [3:0]m00_couplers_to_axi_mem_intercon_ARLEN;
wire [1:0]m00_couplers_to_axi_mem_intercon_ARLOCK;
wire [2:0]m00_couplers_to_axi_mem_intercon_ARPROT;
wire [3:0]m00_couplers_to_axi_mem_intercon_ARQOS;
wire m00_couplers_to_axi_mem_intercon_ARREADY;
wire [2:0]m00_couplers_to_axi_mem_intercon_ARSIZE;
wire m00_couplers_to_axi_mem_intercon_ARVALID;
wire [31:0]m00_couplers_to_axi_mem_intercon_AWADDR;
wire [1:0]m00_couplers_to_axi_mem_intercon_AWBURST;
wire [3:0]m00_couplers_to_axi_mem_intercon_AWCACHE;
wire [0:0]m00_couplers_to_axi_mem_intercon_AWID;
wire [3:0]m00_couplers_to_axi_mem_intercon_AWLEN;
wire [1:0]m00_couplers_to_axi_mem_intercon_AWLOCK;
wire [2:0]m00_couplers_to_axi_mem_intercon_AWPROT;
wire [3:0]m00_couplers_to_axi_mem_intercon_AWQOS;
wire m00_couplers_to_axi_mem_intercon_AWREADY;
wire [2:0]m00_couplers_to_axi_mem_intercon_AWSIZE;
wire m00_couplers_to_axi_mem_intercon_AWVALID;
wire [0:0]m00_couplers_to_axi_mem_intercon_BID;
wire m00_couplers_to_axi_mem_intercon_BREADY;
wire [1:0]m00_couplers_to_axi_mem_intercon_BRESP;
wire m00_couplers_to_axi_mem_intercon_BVALID;
wire [63:0]m00_couplers_to_axi_mem_intercon_RDATA;
wire [0:0]m00_couplers_to_axi_mem_intercon_RID;
wire m00_couplers_to_axi_mem_intercon_RLAST;
wire m00_couplers_to_axi_mem_intercon_RREADY;
wire [1:0]m00_couplers_to_axi_mem_intercon_RRESP;
wire m00_couplers_to_axi_mem_intercon_RVALID;
wire [63:0]m00_couplers_to_axi_mem_intercon_WDATA;
wire [0:0]m00_couplers_to_axi_mem_intercon_WID;
wire m00_couplers_to_axi_mem_intercon_WLAST;
wire m00_couplers_to_axi_mem_intercon_WREADY;
wire [7:0]m00_couplers_to_axi_mem_intercon_WSTRB;
wire m00_couplers_to_axi_mem_intercon_WVALID;
wire [31:0]s00_couplers_to_xbar_ARADDR;
wire [1:0]s00_couplers_to_xbar_ARBURST;
wire [3:0]s00_couplers_to_xbar_ARCACHE;
wire [7:0]s00_couplers_to_xbar_ARLEN;
wire [0:0]s00_couplers_to_xbar_ARLOCK;
wire [2:0]s00_couplers_to_xbar_ARPROT;
wire [3:0]s00_couplers_to_xbar_ARQOS;
wire [0:0]s00_couplers_to_xbar_ARREADY;
wire [2:0]s00_couplers_to_xbar_ARSIZE;
wire s00_couplers_to_xbar_ARVALID;
wire [63:0]s00_couplers_to_xbar_RDATA;
wire [0:0]s00_couplers_to_xbar_RLAST;
wire s00_couplers_to_xbar_RREADY;
wire [1:0]s00_couplers_to_xbar_RRESP;
wire [0:0]s00_couplers_to_xbar_RVALID;
wire [31:0]s01_couplers_to_xbar_AWADDR;
wire [1:0]s01_couplers_to_xbar_AWBURST;
wire [3:0]s01_couplers_to_xbar_AWCACHE;
wire [7:0]s01_couplers_to_xbar_AWLEN;
wire [0:0]s01_couplers_to_xbar_AWLOCK;
wire [2:0]s01_couplers_to_xbar_AWPROT;
wire [3:0]s01_couplers_to_xbar_AWQOS;
wire [1:1]s01_couplers_to_xbar_AWREADY;
wire [2:0]s01_couplers_to_xbar_AWSIZE;
wire s01_couplers_to_xbar_AWVALID;
wire s01_couplers_to_xbar_BREADY;
wire [3:2]s01_couplers_to_xbar_BRESP;
wire [1:1]s01_couplers_to_xbar_BVALID;
wire [63:0]s01_couplers_to_xbar_WDATA;
wire s01_couplers_to_xbar_WLAST;
wire [1:1]s01_couplers_to_xbar_WREADY;
wire [7:0]s01_couplers_to_xbar_WSTRB;
wire s01_couplers_to_xbar_WVALID;
wire [31:0]xbar_to_m00_couplers_ARADDR;
wire [1:0]xbar_to_m00_couplers_ARBURST;
wire [3:0]xbar_to_m00_couplers_ARCACHE;
wire [0:0]xbar_to_m00_couplers_ARID;
wire [7:0]xbar_to_m00_couplers_ARLEN;
wire [0:0]xbar_to_m00_couplers_ARLOCK;
wire [2:0]xbar_to_m00_couplers_ARPROT;
wire [3:0]xbar_to_m00_couplers_ARQOS;
wire xbar_to_m00_couplers_ARREADY;
wire [3:0]xbar_to_m00_couplers_ARREGION;
wire [2:0]xbar_to_m00_couplers_ARSIZE;
wire [0:0]xbar_to_m00_couplers_ARVALID;
wire [31:0]xbar_to_m00_couplers_AWADDR;
wire [1:0]xbar_to_m00_couplers_AWBURST;
wire [3:0]xbar_to_m00_couplers_AWCACHE;
wire [0:0]xbar_to_m00_couplers_AWID;
wire [7:0]xbar_to_m00_couplers_AWLEN;
wire [0:0]xbar_to_m00_couplers_AWLOCK;
wire [2:0]xbar_to_m00_couplers_AWPROT;
wire [3:0]xbar_to_m00_couplers_AWQOS;
wire xbar_to_m00_couplers_AWREADY;
wire [3:0]xbar_to_m00_couplers_AWREGION;
wire [2:0]xbar_to_m00_couplers_AWSIZE;
wire [0:0]xbar_to_m00_couplers_AWVALID;
wire [0:0]xbar_to_m00_couplers_BID;
wire [0:0]xbar_to_m00_couplers_BREADY;
wire [1:0]xbar_to_m00_couplers_BRESP;
wire xbar_to_m00_couplers_BVALID;
wire [63:0]xbar_to_m00_couplers_RDATA;
wire [0:0]xbar_to_m00_couplers_RID;
wire xbar_to_m00_couplers_RLAST;
wire [0:0]xbar_to_m00_couplers_RREADY;
wire [1:0]xbar_to_m00_couplers_RRESP;
wire xbar_to_m00_couplers_RVALID;
wire [63:0]xbar_to_m00_couplers_WDATA;
wire [0:0]xbar_to_m00_couplers_WLAST;
wire xbar_to_m00_couplers_WREADY;
wire [7:0]xbar_to_m00_couplers_WSTRB;
wire [0:0]xbar_to_m00_couplers_WVALID;
wire [1:0]NLW_xbar_s_axi_awready_UNCONNECTED;
wire [3:0]NLW_xbar_s_axi_bresp_UNCONNECTED;
wire [1:0]NLW_xbar_s_axi_bvalid_UNCONNECTED;
wire [1:0]NLW_xbar_s_axi_wready_UNCONNECTED;
assign M00_ACLK_1 = M00_ACLK;
assign M00_ARESETN_1 = M00_ARESETN[0];
assign M00_AXI_araddr[31:0] = m00_couplers_to_axi_mem_intercon_ARADDR;
assign M00_AXI_arburst[1:0] = m00_couplers_to_axi_mem_intercon_ARBURST;
assign M00_AXI_arcache[3:0] = m00_couplers_to_axi_mem_intercon_ARCACHE;
assign M00_AXI_arid[0] = m00_couplers_to_axi_mem_intercon_ARID;
assign M00_AXI_arlen[3:0] = m00_couplers_to_axi_mem_intercon_ARLEN;
assign M00_AXI_arlock[1:0] = m00_couplers_to_axi_mem_intercon_ARLOCK;
assign M00_AXI_arprot[2:0] = m00_couplers_to_axi_mem_intercon_ARPROT;
assign M00_AXI_arqos[3:0] = m00_couplers_to_axi_mem_intercon_ARQOS;
assign M00_AXI_arsize[2:0] = m00_couplers_to_axi_mem_intercon_ARSIZE;
assign M00_AXI_arvalid = m00_couplers_to_axi_mem_intercon_ARVALID;
assign M00_AXI_awaddr[31:0] = m00_couplers_to_axi_mem_intercon_AWADDR;
assign M00_AXI_awburst[1:0] = m00_couplers_to_axi_mem_intercon_AWBURST;
assign M00_AXI_awcache[3:0] = m00_couplers_to_axi_mem_intercon_AWCACHE;
assign M00_AXI_awid[0] = m00_couplers_to_axi_mem_intercon_AWID;
assign M00_AXI_awlen[3:0] = m00_couplers_to_axi_mem_intercon_AWLEN;
assign M00_AXI_awlock[1:0] = m00_couplers_to_axi_mem_intercon_AWLOCK;
assign M00_AXI_awprot[2:0] = m00_couplers_to_axi_mem_intercon_AWPROT;
assign M00_AXI_awqos[3:0] = m00_couplers_to_axi_mem_intercon_AWQOS;
assign M00_AXI_awsize[2:0] = m00_couplers_to_axi_mem_intercon_AWSIZE;
assign M00_AXI_awvalid = m00_couplers_to_axi_mem_intercon_AWVALID;
assign M00_AXI_bready = m00_couplers_to_axi_mem_intercon_BREADY;
assign M00_AXI_rready = m00_couplers_to_axi_mem_intercon_RREADY;
assign M00_AXI_wdata[63:0] = m00_couplers_to_axi_mem_intercon_WDATA;
assign M00_AXI_wid[0] = m00_couplers_to_axi_mem_intercon_WID;
assign M00_AXI_wlast = m00_couplers_to_axi_mem_intercon_WLAST;
assign M00_AXI_wstrb[7:0] = m00_couplers_to_axi_mem_intercon_WSTRB;
assign M00_AXI_wvalid = m00_couplers_to_axi_mem_intercon_WVALID;
assign S00_ACLK_1 = S00_ACLK;
assign S00_ARESETN_1 = S00_ARESETN[0];
assign S00_AXI_arready = axi_mem_intercon_to_s00_couplers_ARREADY;
assign S00_AXI_rdata[31:0] = axi_mem_intercon_to_s00_couplers_RDATA;
assign S00_AXI_rlast = axi_mem_intercon_to_s00_couplers_RLAST;
assign S00_AXI_rresp[1:0] = axi_mem_intercon_to_s00_couplers_RRESP;
assign S00_AXI_rvalid = axi_mem_intercon_to_s00_couplers_RVALID;
assign S01_ACLK_1 = S01_ACLK;
assign S01_ARESETN_1 = S01_ARESETN[0];
assign S01_AXI_awready = axi_mem_intercon_to_s01_couplers_AWREADY;
assign S01_AXI_bresp[1:0] = axi_mem_intercon_to_s01_couplers_BRESP;
assign S01_AXI_bvalid = axi_mem_intercon_to_s01_couplers_BVALID;
assign S01_AXI_wready = axi_mem_intercon_to_s01_couplers_WREADY;
assign axi_mem_intercon_ACLK_net = ACLK;
assign axi_mem_intercon_ARESETN_net = ARESETN[0];
assign axi_mem_intercon_to_s00_couplers_ARADDR = S00_AXI_araddr[31:0];
assign axi_mem_intercon_to_s00_couplers_ARBURST = S00_AXI_arburst[1:0];
assign axi_mem_intercon_to_s00_couplers_ARCACHE = S00_AXI_arcache[3:0];
assign axi_mem_intercon_to_s00_couplers_ARLEN = S00_AXI_arlen[7:0];
assign axi_mem_intercon_to_s00_couplers_ARPROT = S00_AXI_arprot[2:0];
assign axi_mem_intercon_to_s00_couplers_ARSIZE = S00_AXI_arsize[2:0];
assign axi_mem_intercon_to_s00_couplers_ARVALID = S00_AXI_arvalid;
assign axi_mem_intercon_to_s00_couplers_RREADY = S00_AXI_rready;
assign axi_mem_intercon_to_s01_couplers_AWADDR = S01_AXI_awaddr[31:0];
assign axi_mem_intercon_to_s01_couplers_AWBURST = S01_AXI_awburst[1:0];
assign axi_mem_intercon_to_s01_couplers_AWCACHE = S01_AXI_awcache[3:0];
assign axi_mem_intercon_to_s01_couplers_AWLEN = S01_AXI_awlen[7:0];
assign axi_mem_intercon_to_s01_couplers_AWPROT = S01_AXI_awprot[2:0];
assign axi_mem_intercon_to_s01_couplers_AWSIZE = S01_AXI_awsize[2:0];
assign axi_mem_intercon_to_s01_couplers_AWVALID = S01_AXI_awvalid;
assign axi_mem_intercon_to_s01_couplers_BREADY = S01_AXI_bready;
assign axi_mem_intercon_to_s01_couplers_WDATA = S01_AXI_wdata[31:0];
assign axi_mem_intercon_to_s01_couplers_WLAST = S01_AXI_wlast;
assign axi_mem_intercon_to_s01_couplers_WSTRB = S01_AXI_wstrb[3:0];
assign axi_mem_intercon_to_s01_couplers_WVALID = S01_AXI_wvalid;
assign m00_couplers_to_axi_mem_intercon_ARREADY = M00_AXI_arready;
assign m00_couplers_to_axi_mem_intercon_AWREADY = M00_AXI_awready;
assign m00_couplers_to_axi_mem_intercon_BID = M00_AXI_bid[0];
assign m00_couplers_to_axi_mem_intercon_BRESP = M00_AXI_bresp[1:0];
assign m00_couplers_to_axi_mem_intercon_BVALID = M00_AXI_bvalid;
assign m00_couplers_to_axi_mem_intercon_RDATA = M00_AXI_rdata[63:0];
assign m00_couplers_to_axi_mem_intercon_RID = M00_AXI_rid[0];
assign m00_couplers_to_axi_mem_intercon_RLAST = M00_AXI_rlast;
assign m00_couplers_to_axi_mem_intercon_RRESP = M00_AXI_rresp[1:0];
assign m00_couplers_to_axi_mem_intercon_RVALID = M00_AXI_rvalid;
assign m00_couplers_to_axi_mem_intercon_WREADY = M00_AXI_wready;
GND GND
(.G(GND_1));
VCC VCC
(.P(VCC_1));
m00_couplers_imp_1TEAG88 m00_couplers
(.M_ACLK(M00_ACLK_1),
.M_ARESETN(M00_ARESETN_1),
.M_AXI_araddr(m00_couplers_to_axi_mem_intercon_ARADDR),
.M_AXI_arburst(m00_couplers_to_axi_mem_intercon_ARBURST),
.M_AXI_arcache(m00_couplers_to_axi_mem_intercon_ARCACHE),
.M_AXI_arid(m00_couplers_to_axi_mem_intercon_ARID),
.M_AXI_arlen(m00_couplers_to_axi_mem_intercon_ARLEN),
.M_AXI_arlock(m00_couplers_to_axi_mem_intercon_ARLOCK),
.M_AXI_arprot(m00_couplers_to_axi_mem_intercon_ARPROT),
.M_AXI_arqos(m00_couplers_to_axi_mem_intercon_ARQOS),
.M_AXI_arready(m00_couplers_to_axi_mem_intercon_ARREADY),
.M_AXI_arsize(m00_couplers_to_axi_mem_intercon_ARSIZE),
.M_AXI_arvalid(m00_couplers_to_axi_mem_intercon_ARVALID),
.M_AXI_awaddr(m00_couplers_to_axi_mem_intercon_AWADDR),
.M_AXI_awburst(m00_couplers_to_axi_mem_intercon_AWBURST),
.M_AXI_awcache(m00_couplers_to_axi_mem_intercon_AWCACHE),
.M_AXI_awid(m00_couplers_to_axi_mem_intercon_AWID),
.M_AXI_awlen(m00_couplers_to_axi_mem_intercon_AWLEN),
.M_AXI_awlock(m00_couplers_to_axi_mem_intercon_AWLOCK),
.M_AXI_awprot(m00_couplers_to_axi_mem_intercon_AWPROT),
.M_AXI_awqos(m00_couplers_to_axi_mem_intercon_AWQOS),
.M_AXI_awready(m00_couplers_to_axi_mem_intercon_AWREADY),
.M_AXI_awsize(m00_couplers_to_axi_mem_intercon_AWSIZE),
.M_AXI_awvalid(m00_couplers_to_axi_mem_intercon_AWVALID),
.M_AXI_bid(m00_couplers_to_axi_mem_intercon_BID),
.M_AXI_bready(m00_couplers_to_axi_mem_intercon_BREADY),
.M_AXI_bresp(m00_couplers_to_axi_mem_intercon_BRESP),
.M_AXI_bvalid(m00_couplers_to_axi_mem_intercon_BVALID),
.M_AXI_rdata(m00_couplers_to_axi_mem_intercon_RDATA),
.M_AXI_rid(m00_couplers_to_axi_mem_intercon_RID),
.M_AXI_rlast(m00_couplers_to_axi_mem_intercon_RLAST),
.M_AXI_rready(m00_couplers_to_axi_mem_intercon_RREADY),
.M_AXI_rresp(m00_couplers_to_axi_mem_intercon_RRESP),
.M_AXI_rvalid(m00_couplers_to_axi_mem_intercon_RVALID),
.M_AXI_wdata(m00_couplers_to_axi_mem_intercon_WDATA),
.M_AXI_wid(m00_couplers_to_axi_mem_intercon_WID),
.M_AXI_wlast(m00_couplers_to_axi_mem_intercon_WLAST),
.M_AXI_wready(m00_couplers_to_axi_mem_intercon_WREADY),
.M_AXI_wstrb(m00_couplers_to_axi_mem_intercon_WSTRB),
.M_AXI_wvalid(m00_couplers_to_axi_mem_intercon_WVALID),
.S_ACLK(axi_mem_intercon_ACLK_net),
.S_ARESETN(axi_mem_intercon_ARESETN_net),
.S_AXI_araddr(xbar_to_m00_couplers_ARADDR),
.S_AXI_arburst(xbar_to_m00_couplers_ARBURST),
.S_AXI_arcache(xbar_to_m00_couplers_ARCACHE),
.S_AXI_arid(xbar_to_m00_couplers_ARID),
.S_AXI_arlen(xbar_to_m00_couplers_ARLEN),
.S_AXI_arlock(xbar_to_m00_couplers_ARLOCK),
.S_AXI_arprot(xbar_to_m00_couplers_ARPROT),
.S_AXI_arqos(xbar_to_m00_couplers_ARQOS),
.S_AXI_arready(xbar_to_m00_couplers_ARREADY),
.S_AXI_arregion(xbar_to_m00_couplers_ARREGION),
.S_AXI_arsize(xbar_to_m00_couplers_ARSIZE),
.S_AXI_arvalid(xbar_to_m00_couplers_ARVALID),
.S_AXI_awaddr(xbar_to_m00_couplers_AWADDR),
.S_AXI_awburst(xbar_to_m00_couplers_AWBURST),
.S_AXI_awcache(xbar_to_m00_couplers_AWCACHE),
.S_AXI_awid(xbar_to_m00_couplers_AWID),
.S_AXI_awlen(xbar_to_m00_couplers_AWLEN),
.S_AXI_awlock(xbar_to_m00_couplers_AWLOCK),
.S_AXI_awprot(xbar_to_m00_couplers_AWPROT),
.S_AXI_awqos(xbar_to_m00_couplers_AWQOS),
.S_AXI_awready(xbar_to_m00_couplers_AWREADY),
.S_AXI_awregion(xbar_to_m00_couplers_AWREGION),
.S_AXI_awsize(xbar_to_m00_couplers_AWSIZE),
.S_AXI_awvalid(xbar_to_m00_couplers_AWVALID),
.S_AXI_bid(xbar_to_m00_couplers_BID),
.S_AXI_bready(xbar_to_m00_couplers_BREADY),
.S_AXI_bresp(xbar_to_m00_couplers_BRESP),
.S_AXI_bvalid(xbar_to_m00_couplers_BVALID),
.S_AXI_rdata(xbar_to_m00_couplers_RDATA),
.S_AXI_rid(xbar_to_m00_couplers_RID),
.S_AXI_rlast(xbar_to_m00_couplers_RLAST),
.S_AXI_rready(xbar_to_m00_couplers_RREADY),
.S_AXI_rresp(xbar_to_m00_couplers_RRESP),
.S_AXI_rvalid(xbar_to_m00_couplers_RVALID),
.S_AXI_wdata(xbar_to_m00_couplers_WDATA),
.S_AXI_wlast(xbar_to_m00_couplers_WLAST),
.S_AXI_wready(xbar_to_m00_couplers_WREADY),
.S_AXI_wstrb(xbar_to_m00_couplers_WSTRB),
.S_AXI_wvalid(xbar_to_m00_couplers_WVALID));
s00_couplers_imp_1P403ZT s00_couplers
(.M_ACLK(axi_mem_intercon_ACLK_net),
.M_ARESETN(axi_mem_intercon_ARESETN_net),
.M_AXI_araddr(s00_couplers_to_xbar_ARADDR),
.M_AXI_arburst(s00_couplers_to_xbar_ARBURST),
.M_AXI_arcache(s00_couplers_to_xbar_ARCACHE),
.M_AXI_arlen(s00_couplers_to_xbar_ARLEN),
.M_AXI_arlock(s00_couplers_to_xbar_ARLOCK),
.M_AXI_arprot(s00_couplers_to_xbar_ARPROT),
.M_AXI_arqos(s00_couplers_to_xbar_ARQOS),
.M_AXI_arready(s00_couplers_to_xbar_ARREADY),
.M_AXI_arsize(s00_couplers_to_xbar_ARSIZE),
.M_AXI_arvalid(s00_couplers_to_xbar_ARVALID),
.M_AXI_rdata(s00_couplers_to_xbar_RDATA),
.M_AXI_rlast(s00_couplers_to_xbar_RLAST),
.M_AXI_rready(s00_couplers_to_xbar_RREADY),
.M_AXI_rresp(s00_couplers_to_xbar_RRESP),
.M_AXI_rvalid(s00_couplers_to_xbar_RVALID),
.S_ACLK(S00_ACLK_1),
.S_ARESETN(S00_ARESETN_1),
.S_AXI_araddr(axi_mem_intercon_to_s00_couplers_ARADDR),
.S_AXI_arburst(axi_mem_intercon_to_s00_couplers_ARBURST),
.S_AXI_arcache(axi_mem_intercon_to_s00_couplers_ARCACHE),
.S_AXI_arlen(axi_mem_intercon_to_s00_couplers_ARLEN),
.S_AXI_arprot(axi_mem_intercon_to_s00_couplers_ARPROT),
.S_AXI_arready(axi_mem_intercon_to_s00_couplers_ARREADY),
.S_AXI_arsize(axi_mem_intercon_to_s00_couplers_ARSIZE),
.S_AXI_arvalid(axi_mem_intercon_to_s00_couplers_ARVALID),
.S_AXI_rdata(axi_mem_intercon_to_s00_couplers_RDATA),
.S_AXI_rlast(axi_mem_intercon_to_s00_couplers_RLAST),
.S_AXI_rready(axi_mem_intercon_to_s00_couplers_RREADY),
.S_AXI_rresp(axi_mem_intercon_to_s00_couplers_RRESP),
.S_AXI_rvalid(axi_mem_intercon_to_s00_couplers_RVALID));
s01_couplers_imp_VQ497S s01_couplers
(.M_ACLK(axi_mem_intercon_ACLK_net),
.M_ARESETN(axi_mem_intercon_ARESETN_net),
.M_AXI_awaddr(s01_couplers_to_xbar_AWADDR),
.M_AXI_awburst(s01_couplers_to_xbar_AWBURST),
.M_AXI_awcache(s01_couplers_to_xbar_AWCACHE),
.M_AXI_awlen(s01_couplers_to_xbar_AWLEN),
.M_AXI_awlock(s01_couplers_to_xbar_AWLOCK),
.M_AXI_awprot(s01_couplers_to_xbar_AWPROT),
.M_AXI_awqos(s01_couplers_to_xbar_AWQOS),
.M_AXI_awready(s01_couplers_to_xbar_AWREADY),
.M_AXI_awsize(s01_couplers_to_xbar_AWSIZE),
.M_AXI_awvalid(s01_couplers_to_xbar_AWVALID),
.M_AXI_bready(s01_couplers_to_xbar_BREADY),
.M_AXI_bresp(s01_couplers_to_xbar_BRESP),
.M_AXI_bvalid(s01_couplers_to_xbar_BVALID),
.M_AXI_wdata(s01_couplers_to_xbar_WDATA),
.M_AXI_wlast(s01_couplers_to_xbar_WLAST),
.M_AXI_wready(s01_couplers_to_xbar_WREADY),
.M_AXI_wstrb(s01_couplers_to_xbar_WSTRB),
.M_AXI_wvalid(s01_couplers_to_xbar_WVALID),
.S_ACLK(S01_ACLK_1),
.S_ARESETN(S01_ARESETN_1),
.S_AXI_awaddr(axi_mem_intercon_to_s01_couplers_AWADDR),
.S_AXI_awburst(axi_mem_intercon_to_s01_couplers_AWBURST),
.S_AXI_awcache(axi_mem_intercon_to_s01_couplers_AWCACHE),
.S_AXI_awlen(axi_mem_intercon_to_s01_couplers_AWLEN),
.S_AXI_awprot(axi_mem_intercon_to_s01_couplers_AWPROT),
.S_AXI_awready(axi_mem_intercon_to_s01_couplers_AWREADY),
.S_AXI_awsize(axi_mem_intercon_to_s01_couplers_AWSIZE),
.S_AXI_awvalid(axi_mem_intercon_to_s01_couplers_AWVALID),
.S_AXI_bready(axi_mem_intercon_to_s01_couplers_BREADY),
.S_AXI_bresp(axi_mem_intercon_to_s01_couplers_BRESP),
.S_AXI_bvalid(axi_mem_intercon_to_s01_couplers_BVALID),
.S_AXI_wdata(axi_mem_intercon_to_s01_couplers_WDATA),
.S_AXI_wlast(axi_mem_intercon_to_s01_couplers_WLAST),
.S_AXI_wready(axi_mem_intercon_to_s01_couplers_WREADY),
.S_AXI_wstrb(axi_mem_intercon_to_s01_couplers_WSTRB),
.S_AXI_wvalid(axi_mem_intercon_to_s01_couplers_WVALID));
system_xbar_1 xbar
(.aclk(axi_mem_intercon_ACLK_net),
.aresetn(axi_mem_intercon_ARESETN_net),
.m_axi_araddr(xbar_to_m00_couplers_ARADDR),
.m_axi_arburst(xbar_to_m00_couplers_ARBURST),
.m_axi_arcache(xbar_to_m00_couplers_ARCACHE),
.m_axi_arid(xbar_to_m00_couplers_ARID),
.m_axi_arlen(xbar_to_m00_couplers_ARLEN),
.m_axi_arlock(xbar_to_m00_couplers_ARLOCK),
.m_axi_arprot(xbar_to_m00_couplers_ARPROT),
.m_axi_arqos(xbar_to_m00_couplers_ARQOS),
.m_axi_arready(xbar_to_m00_couplers_ARREADY),
.m_axi_arregion(xbar_to_m00_couplers_ARREGION),
.m_axi_arsize(xbar_to_m00_couplers_ARSIZE),
.m_axi_arvalid(xbar_to_m00_couplers_ARVALID),
.m_axi_awaddr(xbar_to_m00_couplers_AWADDR),
.m_axi_awburst(xbar_to_m00_couplers_AWBURST),
.m_axi_awcache(xbar_to_m00_couplers_AWCACHE),
.m_axi_awid(xbar_to_m00_couplers_AWID),
.m_axi_awlen(xbar_to_m00_couplers_AWLEN),
.m_axi_awlock(xbar_to_m00_couplers_AWLOCK),
.m_axi_awprot(xbar_to_m00_couplers_AWPROT),
.m_axi_awqos(xbar_to_m00_couplers_AWQOS),
.m_axi_awready(xbar_to_m00_couplers_AWREADY),
.m_axi_awregion(xbar_to_m00_couplers_AWREGION),
.m_axi_awsize(xbar_to_m00_couplers_AWSIZE),
.m_axi_awvalid(xbar_to_m00_couplers_AWVALID),
.m_axi_bid(xbar_to_m00_couplers_BID),
.m_axi_bready(xbar_to_m00_couplers_BREADY),
.m_axi_bresp(xbar_to_m00_couplers_BRESP),
.m_axi_bvalid(xbar_to_m00_couplers_BVALID),
.m_axi_rdata(xbar_to_m00_couplers_RDATA),
.m_axi_rid(xbar_to_m00_couplers_RID),
.m_axi_rlast(xbar_to_m00_couplers_RLAST),
.m_axi_rready(xbar_to_m00_couplers_RREADY),
.m_axi_rresp(xbar_to_m00_couplers_RRESP),
.m_axi_rvalid(xbar_to_m00_couplers_RVALID),
.m_axi_wdata(xbar_to_m00_couplers_WDATA),
.m_axi_wlast(xbar_to_m00_couplers_WLAST),
.m_axi_wready(xbar_to_m00_couplers_WREADY),
.m_axi_wstrb(xbar_to_m00_couplers_WSTRB),
.m_axi_wvalid(xbar_to_m00_couplers_WVALID),
.s_axi_araddr({GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,s00_couplers_to_xbar_ARADDR}),
.s_axi_arburst({GND_1,GND_1,s00_couplers_to_xbar_ARBURST}),
.s_axi_arcache({GND_1,GND_1,GND_1,GND_1,s00_couplers_to_xbar_ARCACHE}),
.s_axi_arid({GND_1,GND_1}),
.s_axi_arlen({GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,VCC_1,GND_1,s00_couplers_to_xbar_ARLEN}),
.s_axi_arlock({GND_1,s00_couplers_to_xbar_ARLOCK}),
.s_axi_arprot({GND_1,GND_1,GND_1,s00_couplers_to_xbar_ARPROT}),
.s_axi_arqos({GND_1,GND_1,GND_1,GND_1,s00_couplers_to_xbar_ARQOS}),
.s_axi_arready(s00_couplers_to_xbar_ARREADY),
.s_axi_arsize({GND_1,GND_1,GND_1,s00_couplers_to_xbar_ARSIZE}),
.s_axi_arvalid({GND_1,s00_couplers_to_xbar_ARVALID}),
.s_axi_awaddr({s01_couplers_to_xbar_AWADDR,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1}),
.s_axi_awburst({s01_couplers_to_xbar_AWBURST,GND_1,GND_1}),
.s_axi_awcache({s01_couplers_to_xbar_AWCACHE,GND_1,GND_1,GND_1,GND_1}),
.s_axi_awid({GND_1,GND_1}),
.s_axi_awlen({s01_couplers_to_xbar_AWLEN,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1}),
.s_axi_awlock({s01_couplers_to_xbar_AWLOCK,GND_1}),
.s_axi_awprot({s01_couplers_to_xbar_AWPROT,GND_1,GND_1,GND_1}),
.s_axi_awqos({s01_couplers_to_xbar_AWQOS,GND_1,GND_1,GND_1,GND_1}),
.s_axi_awready({s01_couplers_to_xbar_AWREADY,NLW_xbar_s_axi_awready_UNCONNECTED[0]}),
.s_axi_awsize({s01_couplers_to_xbar_AWSIZE,GND_1,GND_1,GND_1}),
.s_axi_awvalid({s01_couplers_to_xbar_AWVALID,GND_1}),
.s_axi_bready({s01_couplers_to_xbar_BREADY,GND_1}),
.s_axi_bresp({s01_couplers_to_xbar_BRESP,NLW_xbar_s_axi_bresp_UNCONNECTED[1:0]}),
.s_axi_bvalid({s01_couplers_to_xbar_BVALID,NLW_xbar_s_axi_bvalid_UNCONNECTED[0]}),
.s_axi_rdata(s00_couplers_to_xbar_RDATA),
.s_axi_rlast(s00_couplers_to_xbar_RLAST),
.s_axi_rready({GND_1,s00_couplers_to_xbar_RREADY}),
.s_axi_rresp(s00_couplers_to_xbar_RRESP),
.s_axi_rvalid(s00_couplers_to_xbar_RVALID),
.s_axi_wdata({s01_couplers_to_xbar_WDATA,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1}),
.s_axi_wlast({s01_couplers_to_xbar_WLAST,VCC_1}),
.s_axi_wready({s01_couplers_to_xbar_WREADY,NLW_xbar_s_axi_wready_UNCONNECTED[0]}),
.s_axi_wstrb({s01_couplers_to_xbar_WSTRB,VCC_1,VCC_1,VCC_1,VCC_1,VCC_1,VCC_1,VCC_1,VCC_1}),
.s_axi_wvalid({s01_couplers_to_xbar_WVALID,GND_1}));
endmodule |
module system_processing_system7_0_axi_periph_0
(ACLK,
ARESETN,
M00_ACLK,
M00_ARESETN,
M00_AXI_araddr,
M00_AXI_arready,
M00_AXI_arvalid,
M00_AXI_awaddr,
M00_AXI_awready,
M00_AXI_awvalid,
M00_AXI_bready,
M00_AXI_bresp,
M00_AXI_bvalid,
M00_AXI_rdata,
M00_AXI_rready,
M00_AXI_rresp,
M00_AXI_rvalid,
M00_AXI_wdata,
M00_AXI_wready,
M00_AXI_wstrb,
M00_AXI_wvalid,
M01_ACLK,
M01_ARESETN,
M01_AXI_araddr,
M01_AXI_arready,
M01_AXI_arvalid,
M01_AXI_awaddr,
M01_AXI_awready,
M01_AXI_awvalid,
M01_AXI_bready,
M01_AXI_bresp,
M01_AXI_bvalid,
M01_AXI_rdata,
M01_AXI_rready,
M01_AXI_rresp,
M01_AXI_rvalid,
M01_AXI_wdata,
M01_AXI_wready,
M01_AXI_wvalid,
M02_ACLK,
M02_ARESETN,
M02_AXI_araddr,
M02_AXI_arready,
M02_AXI_arvalid,
M02_AXI_awaddr,
M02_AXI_awready,
M02_AXI_awvalid,
M02_AXI_bready,
M02_AXI_bresp,
M02_AXI_bvalid,
M02_AXI_rdata,
M02_AXI_rready,
M02_AXI_rresp,
M02_AXI_rvalid,
M02_AXI_wdata,
M02_AXI_wready,
M02_AXI_wstrb,
M02_AXI_wvalid,
S00_ACLK,
S00_ARESETN,
S00_AXI_araddr,
S00_AXI_arburst,
S00_AXI_arcache,
S00_AXI_arid,
S00_AXI_arlen,
S00_AXI_arlock,
S00_AXI_arprot,
S00_AXI_arqos,
S00_AXI_arready,
S00_AXI_arsize,
S00_AXI_arvalid,
S00_AXI_awaddr,
S00_AXI_awburst,
S00_AXI_awcache,
S00_AXI_awid,
S00_AXI_awlen,
S00_AXI_awlock,
S00_AXI_awprot,
S00_AXI_awqos,
S00_AXI_awready,
S00_AXI_awsize,
S00_AXI_awvalid,
S00_AXI_bid,
S00_AXI_bready,
S00_AXI_bresp,
S00_AXI_bvalid,
S00_AXI_rdata,
S00_AXI_rid,
S00_AXI_rlast,
S00_AXI_rready,
S00_AXI_rresp,
S00_AXI_rvalid,
S00_AXI_wdata,
S00_AXI_wid,
S00_AXI_wlast,
S00_AXI_wready,
S00_AXI_wstrb,
S00_AXI_wvalid);
input ACLK;
input [0:0]ARESETN;
input M00_ACLK;
input [0:0]M00_ARESETN;
output [4:0]M00_AXI_araddr;
input M00_AXI_arready;
output M00_AXI_arvalid;
output [4:0]M00_AXI_awaddr;
input M00_AXI_awready;
output M00_AXI_awvalid;
output M00_AXI_bready;
input [1:0]M00_AXI_bresp;
input M00_AXI_bvalid;
input [31:0]M00_AXI_rdata;
output M00_AXI_rready;
input [1:0]M00_AXI_rresp;
input M00_AXI_rvalid;
output [31:0]M00_AXI_wdata;
input M00_AXI_wready;
output [3:0]M00_AXI_wstrb;
output M00_AXI_wvalid;
input M01_ACLK;
input [0:0]M01_ARESETN;
output [9:0]M01_AXI_araddr;
input M01_AXI_arready;
output M01_AXI_arvalid;
output [9:0]M01_AXI_awaddr;
input M01_AXI_awready;
output M01_AXI_awvalid;
output M01_AXI_bready;
input [1:0]M01_AXI_bresp;
input M01_AXI_bvalid;
input [31:0]M01_AXI_rdata;
output M01_AXI_rready;
input [1:0]M01_AXI_rresp;
input M01_AXI_rvalid;
output [31:0]M01_AXI_wdata;
input M01_AXI_wready;
output M01_AXI_wvalid;
input M02_ACLK;
input [0:0]M02_ARESETN;
output [4:0]M02_AXI_araddr;
input M02_AXI_arready;
output M02_AXI_arvalid;
output [4:0]M02_AXI_awaddr;
input M02_AXI_awready;
output M02_AXI_awvalid;
output M02_AXI_bready;
input [1:0]M02_AXI_bresp;
input M02_AXI_bvalid;
input [31:0]M02_AXI_rdata;
output M02_AXI_rready;
input [1:0]M02_AXI_rresp;
input M02_AXI_rvalid;
output [31:0]M02_AXI_wdata;
input M02_AXI_wready;
output [3:0]M02_AXI_wstrb;
output M02_AXI_wvalid;
input S00_ACLK;
input [0:0]S00_ARESETN;
input [31:0]S00_AXI_araddr;
input [1:0]S00_AXI_arburst;
input [3:0]S00_AXI_arcache;
input [11:0]S00_AXI_arid;
input [3:0]S00_AXI_arlen;
input [1:0]S00_AXI_arlock;
input [2:0]S00_AXI_arprot;
input [3:0]S00_AXI_arqos;
output S00_AXI_arready;
input [2:0]S00_AXI_arsize;
input S00_AXI_arvalid;
input [31:0]S00_AXI_awaddr;
input [1:0]S00_AXI_awburst;
input [3:0]S00_AXI_awcache;
input [11:0]S00_AXI_awid;
input [3:0]S00_AXI_awlen;
input [1:0]S00_AXI_awlock;
input [2:0]S00_AXI_awprot;
input [3:0]S00_AXI_awqos;
output S00_AXI_awready;
input [2:0]S00_AXI_awsize;
input S00_AXI_awvalid;
output [11:0]S00_AXI_bid;
input S00_AXI_bready;
output [1:0]S00_AXI_bresp;
output S00_AXI_bvalid;
output [31:0]S00_AXI_rdata;
output [11:0]S00_AXI_rid;
output S00_AXI_rlast;
input S00_AXI_rready;
output [1:0]S00_AXI_rresp;
output S00_AXI_rvalid;
input [31:0]S00_AXI_wdata;
input [11:0]S00_AXI_wid;
input S00_AXI_wlast;
output S00_AXI_wready;
input [3:0]S00_AXI_wstrb;
input S00_AXI_wvalid;
wire M00_ACLK_1;
wire [0:0]M00_ARESETN_1;
wire M01_ACLK_1;
wire [0:0]M01_ARESETN_1;
wire M02_ACLK_1;
wire [0:0]M02_ARESETN_1;
wire S00_ACLK_1;
wire [0:0]S00_ARESETN_1;
wire [4:0]m00_couplers_to_processing_system7_0_axi_periph_ARADDR;
wire m00_couplers_to_processing_system7_0_axi_periph_ARREADY;
wire m00_couplers_to_processing_system7_0_axi_periph_ARVALID;
wire [4:0]m00_couplers_to_processing_system7_0_axi_periph_AWADDR;
wire m00_couplers_to_processing_system7_0_axi_periph_AWREADY;
wire m00_couplers_to_processing_system7_0_axi_periph_AWVALID;
wire m00_couplers_to_processing_system7_0_axi_periph_BREADY;
wire [1:0]m00_couplers_to_processing_system7_0_axi_periph_BRESP;
wire m00_couplers_to_processing_system7_0_axi_periph_BVALID;
wire [31:0]m00_couplers_to_processing_system7_0_axi_periph_RDATA;
wire m00_couplers_to_processing_system7_0_axi_periph_RREADY;
wire [1:0]m00_couplers_to_processing_system7_0_axi_periph_RRESP;
wire m00_couplers_to_processing_system7_0_axi_periph_RVALID;
wire [31:0]m00_couplers_to_processing_system7_0_axi_periph_WDATA;
wire m00_couplers_to_processing_system7_0_axi_periph_WREADY;
wire [3:0]m00_couplers_to_processing_system7_0_axi_periph_WSTRB;
wire m00_couplers_to_processing_system7_0_axi_periph_WVALID;
wire [9:0]m01_couplers_to_processing_system7_0_axi_periph_ARADDR;
wire m01_couplers_to_processing_system7_0_axi_periph_ARREADY;
wire m01_couplers_to_processing_system7_0_axi_periph_ARVALID;
wire [9:0]m01_couplers_to_processing_system7_0_axi_periph_AWADDR;
wire m01_couplers_to_processing_system7_0_axi_periph_AWREADY;
wire m01_couplers_to_processing_system7_0_axi_periph_AWVALID;
wire m01_couplers_to_processing_system7_0_axi_periph_BREADY;
wire [1:0]m01_couplers_to_processing_system7_0_axi_periph_BRESP;
wire m01_couplers_to_processing_system7_0_axi_periph_BVALID;
wire [31:0]m01_couplers_to_processing_system7_0_axi_periph_RDATA;
wire m01_couplers_to_processing_system7_0_axi_periph_RREADY;
wire [1:0]m01_couplers_to_processing_system7_0_axi_periph_RRESP;
wire m01_couplers_to_processing_system7_0_axi_periph_RVALID;
wire [31:0]m01_couplers_to_processing_system7_0_axi_periph_WDATA;
wire m01_couplers_to_processing_system7_0_axi_periph_WREADY;
wire m01_couplers_to_processing_system7_0_axi_periph_WVALID;
wire [4:0]m02_couplers_to_processing_system7_0_axi_periph_ARADDR;
wire m02_couplers_to_processing_system7_0_axi_periph_ARREADY;
wire m02_couplers_to_processing_system7_0_axi_periph_ARVALID;
wire [4:0]m02_couplers_to_processing_system7_0_axi_periph_AWADDR;
wire m02_couplers_to_processing_system7_0_axi_periph_AWREADY;
wire m02_couplers_to_processing_system7_0_axi_periph_AWVALID;
wire m02_couplers_to_processing_system7_0_axi_periph_BREADY;
wire [1:0]m02_couplers_to_processing_system7_0_axi_periph_BRESP;
wire m02_couplers_to_processing_system7_0_axi_periph_BVALID;
wire [31:0]m02_couplers_to_processing_system7_0_axi_periph_RDATA;
wire m02_couplers_to_processing_system7_0_axi_periph_RREADY;
wire [1:0]m02_couplers_to_processing_system7_0_axi_periph_RRESP;
wire m02_couplers_to_processing_system7_0_axi_periph_RVALID;
wire [31:0]m02_couplers_to_processing_system7_0_axi_periph_WDATA;
wire m02_couplers_to_processing_system7_0_axi_periph_WREADY;
wire [3:0]m02_couplers_to_processing_system7_0_axi_periph_WSTRB;
wire m02_couplers_to_processing_system7_0_axi_periph_WVALID;
wire processing_system7_0_axi_periph_ACLK_net;
wire [0:0]processing_system7_0_axi_periph_ARESETN_net;
wire [31:0]processing_system7_0_axi_periph_to_s00_couplers_ARADDR;
wire [1:0]processing_system7_0_axi_periph_to_s00_couplers_ARBURST;
wire [3:0]processing_system7_0_axi_periph_to_s00_couplers_ARCACHE;
wire [11:0]processing_system7_0_axi_periph_to_s00_couplers_ARID;
wire [3:0]processing_system7_0_axi_periph_to_s00_couplers_ARLEN;
wire [1:0]processing_system7_0_axi_periph_to_s00_couplers_ARLOCK;
wire [2:0]processing_system7_0_axi_periph_to_s00_couplers_ARPROT;
wire [3:0]processing_system7_0_axi_periph_to_s00_couplers_ARQOS;
wire processing_system7_0_axi_periph_to_s00_couplers_ARREADY;
wire [2:0]processing_system7_0_axi_periph_to_s00_couplers_ARSIZE;
wire processing_system7_0_axi_periph_to_s00_couplers_ARVALID;
wire [31:0]processing_system7_0_axi_periph_to_s00_couplers_AWADDR;
wire [1:0]processing_system7_0_axi_periph_to_s00_couplers_AWBURST;
wire [3:0]processing_system7_0_axi_periph_to_s00_couplers_AWCACHE;
wire [11:0]processing_system7_0_axi_periph_to_s00_couplers_AWID;
wire [3:0]processing_system7_0_axi_periph_to_s00_couplers_AWLEN;
wire [1:0]processing_system7_0_axi_periph_to_s00_couplers_AWLOCK;
wire [2:0]processing_system7_0_axi_periph_to_s00_couplers_AWPROT;
wire [3:0]processing_system7_0_axi_periph_to_s00_couplers_AWQOS;
wire processing_system7_0_axi_periph_to_s00_couplers_AWREADY;
wire [2:0]processing_system7_0_axi_periph_to_s00_couplers_AWSIZE;
wire processing_system7_0_axi_periph_to_s00_couplers_AWVALID;
wire [11:0]processing_system7_0_axi_periph_to_s00_couplers_BID;
wire processing_system7_0_axi_periph_to_s00_couplers_BREADY;
wire [1:0]processing_system7_0_axi_periph_to_s00_couplers_BRESP;
wire processing_system7_0_axi_periph_to_s00_couplers_BVALID;
wire [31:0]processing_system7_0_axi_periph_to_s00_couplers_RDATA;
wire [11:0]processing_system7_0_axi_periph_to_s00_couplers_RID;
wire processing_system7_0_axi_periph_to_s00_couplers_RLAST;
wire processing_system7_0_axi_periph_to_s00_couplers_RREADY;
wire [1:0]processing_system7_0_axi_periph_to_s00_couplers_RRESP;
wire processing_system7_0_axi_periph_to_s00_couplers_RVALID;
wire [31:0]processing_system7_0_axi_periph_to_s00_couplers_WDATA;
wire [11:0]processing_system7_0_axi_periph_to_s00_couplers_WID;
wire processing_system7_0_axi_periph_to_s00_couplers_WLAST;
wire processing_system7_0_axi_periph_to_s00_couplers_WREADY;
wire [3:0]processing_system7_0_axi_periph_to_s00_couplers_WSTRB;
wire processing_system7_0_axi_periph_to_s00_couplers_WVALID;
wire [31:0]s00_couplers_to_xbar_ARADDR;
wire [2:0]s00_couplers_to_xbar_ARPROT;
wire [0:0]s00_couplers_to_xbar_ARREADY;
wire s00_couplers_to_xbar_ARVALID;
wire [31:0]s00_couplers_to_xbar_AWADDR;
wire [2:0]s00_couplers_to_xbar_AWPROT;
wire [0:0]s00_couplers_to_xbar_AWREADY;
wire s00_couplers_to_xbar_AWVALID;
wire s00_couplers_to_xbar_BREADY;
wire [1:0]s00_couplers_to_xbar_BRESP;
wire [0:0]s00_couplers_to_xbar_BVALID;
wire [31:0]s00_couplers_to_xbar_RDATA;
wire s00_couplers_to_xbar_RREADY;
wire [1:0]s00_couplers_to_xbar_RRESP;
wire [0:0]s00_couplers_to_xbar_RVALID;
wire [31:0]s00_couplers_to_xbar_WDATA;
wire [0:0]s00_couplers_to_xbar_WREADY;
wire [3:0]s00_couplers_to_xbar_WSTRB;
wire s00_couplers_to_xbar_WVALID;
wire [31:0]xbar_to_m00_couplers_ARADDR;
wire xbar_to_m00_couplers_ARREADY;
wire [0:0]xbar_to_m00_couplers_ARVALID;
wire [31:0]xbar_to_m00_couplers_AWADDR;
wire xbar_to_m00_couplers_AWREADY;
wire [0:0]xbar_to_m00_couplers_AWVALID;
wire [0:0]xbar_to_m00_couplers_BREADY;
wire [1:0]xbar_to_m00_couplers_BRESP;
wire xbar_to_m00_couplers_BVALID;
wire [31:0]xbar_to_m00_couplers_RDATA;
wire [0:0]xbar_to_m00_couplers_RREADY;
wire [1:0]xbar_to_m00_couplers_RRESP;
wire xbar_to_m00_couplers_RVALID;
wire [31:0]xbar_to_m00_couplers_WDATA;
wire xbar_to_m00_couplers_WREADY;
wire [3:0]xbar_to_m00_couplers_WSTRB;
wire [0:0]xbar_to_m00_couplers_WVALID;
wire [63:32]xbar_to_m01_couplers_ARADDR;
wire xbar_to_m01_couplers_ARREADY;
wire [1:1]xbar_to_m01_couplers_ARVALID;
wire [63:32]xbar_to_m01_couplers_AWADDR;
wire xbar_to_m01_couplers_AWREADY;
wire [1:1]xbar_to_m01_couplers_AWVALID;
wire [1:1]xbar_to_m01_couplers_BREADY;
wire [1:0]xbar_to_m01_couplers_BRESP;
wire xbar_to_m01_couplers_BVALID;
wire [31:0]xbar_to_m01_couplers_RDATA;
wire [1:1]xbar_to_m01_couplers_RREADY;
wire [1:0]xbar_to_m01_couplers_RRESP;
wire xbar_to_m01_couplers_RVALID;
wire [63:32]xbar_to_m01_couplers_WDATA;
wire xbar_to_m01_couplers_WREADY;
wire [1:1]xbar_to_m01_couplers_WVALID;
wire [95:64]xbar_to_m02_couplers_ARADDR;
wire xbar_to_m02_couplers_ARREADY;
wire [2:2]xbar_to_m02_couplers_ARVALID;
wire [95:64]xbar_to_m02_couplers_AWADDR;
wire xbar_to_m02_couplers_AWREADY;
wire [2:2]xbar_to_m02_couplers_AWVALID;
wire [2:2]xbar_to_m02_couplers_BREADY;
wire [1:0]xbar_to_m02_couplers_BRESP;
wire xbar_to_m02_couplers_BVALID;
wire [31:0]xbar_to_m02_couplers_RDATA;
wire [2:2]xbar_to_m02_couplers_RREADY;
wire [1:0]xbar_to_m02_couplers_RRESP;
wire xbar_to_m02_couplers_RVALID;
wire [95:64]xbar_to_m02_couplers_WDATA;
wire xbar_to_m02_couplers_WREADY;
wire [11:8]xbar_to_m02_couplers_WSTRB;
wire [2:2]xbar_to_m02_couplers_WVALID;
wire [11:0]NLW_xbar_m_axi_wstrb_UNCONNECTED;
assign M00_ACLK_1 = M00_ACLK;
assign M00_ARESETN_1 = M00_ARESETN[0];
assign M00_AXI_araddr[4:0] = m00_couplers_to_processing_system7_0_axi_periph_ARADDR;
assign M00_AXI_arvalid = m00_couplers_to_processing_system7_0_axi_periph_ARVALID;
assign M00_AXI_awaddr[4:0] = m00_couplers_to_processing_system7_0_axi_periph_AWADDR;
assign M00_AXI_awvalid = m00_couplers_to_processing_system7_0_axi_periph_AWVALID;
assign M00_AXI_bready = m00_couplers_to_processing_system7_0_axi_periph_BREADY;
assign M00_AXI_rready = m00_couplers_to_processing_system7_0_axi_periph_RREADY;
assign M00_AXI_wdata[31:0] = m00_couplers_to_processing_system7_0_axi_periph_WDATA;
assign M00_AXI_wstrb[3:0] = m00_couplers_to_processing_system7_0_axi_periph_WSTRB;
assign M00_AXI_wvalid = m00_couplers_to_processing_system7_0_axi_periph_WVALID;
assign M01_ACLK_1 = M01_ACLK;
assign M01_ARESETN_1 = M01_ARESETN[0];
assign M01_AXI_araddr[9:0] = m01_couplers_to_processing_system7_0_axi_periph_ARADDR;
assign M01_AXI_arvalid = m01_couplers_to_processing_system7_0_axi_periph_ARVALID;
assign M01_AXI_awaddr[9:0] = m01_couplers_to_processing_system7_0_axi_periph_AWADDR;
assign M01_AXI_awvalid = m01_couplers_to_processing_system7_0_axi_periph_AWVALID;
assign M01_AXI_bready = m01_couplers_to_processing_system7_0_axi_periph_BREADY;
assign M01_AXI_rready = m01_couplers_to_processing_system7_0_axi_periph_RREADY;
assign M01_AXI_wdata[31:0] = m01_couplers_to_processing_system7_0_axi_periph_WDATA;
assign M01_AXI_wvalid = m01_couplers_to_processing_system7_0_axi_periph_WVALID;
assign M02_ACLK_1 = M02_ACLK;
assign M02_ARESETN_1 = M02_ARESETN[0];
assign M02_AXI_araddr[4:0] = m02_couplers_to_processing_system7_0_axi_periph_ARADDR;
assign M02_AXI_arvalid = m02_couplers_to_processing_system7_0_axi_periph_ARVALID;
assign M02_AXI_awaddr[4:0] = m02_couplers_to_processing_system7_0_axi_periph_AWADDR;
assign M02_AXI_awvalid = m02_couplers_to_processing_system7_0_axi_periph_AWVALID;
assign M02_AXI_bready = m02_couplers_to_processing_system7_0_axi_periph_BREADY;
assign M02_AXI_rready = m02_couplers_to_processing_system7_0_axi_periph_RREADY;
assign M02_AXI_wdata[31:0] = m02_couplers_to_processing_system7_0_axi_periph_WDATA;
assign M02_AXI_wstrb[3:0] = m02_couplers_to_processing_system7_0_axi_periph_WSTRB;
assign M02_AXI_wvalid = m02_couplers_to_processing_system7_0_axi_periph_WVALID;
assign S00_ACLK_1 = S00_ACLK;
assign S00_ARESETN_1 = S00_ARESETN[0];
assign S00_AXI_arready = processing_system7_0_axi_periph_to_s00_couplers_ARREADY;
assign S00_AXI_awready = processing_system7_0_axi_periph_to_s00_couplers_AWREADY;
assign S00_AXI_bid[11:0] = processing_system7_0_axi_periph_to_s00_couplers_BID;
assign S00_AXI_bresp[1:0] = processing_system7_0_axi_periph_to_s00_couplers_BRESP;
assign S00_AXI_bvalid = processing_system7_0_axi_periph_to_s00_couplers_BVALID;
assign S00_AXI_rdata[31:0] = processing_system7_0_axi_periph_to_s00_couplers_RDATA;
assign S00_AXI_rid[11:0] = processing_system7_0_axi_periph_to_s00_couplers_RID;
assign S00_AXI_rlast = processing_system7_0_axi_periph_to_s00_couplers_RLAST;
assign S00_AXI_rresp[1:0] = processing_system7_0_axi_periph_to_s00_couplers_RRESP;
assign S00_AXI_rvalid = processing_system7_0_axi_periph_to_s00_couplers_RVALID;
assign S00_AXI_wready = processing_system7_0_axi_periph_to_s00_couplers_WREADY;
assign m00_couplers_to_processing_system7_0_axi_periph_ARREADY = M00_AXI_arready;
assign m00_couplers_to_processing_system7_0_axi_periph_AWREADY = M00_AXI_awready;
assign m00_couplers_to_processing_system7_0_axi_periph_BRESP = M00_AXI_bresp[1:0];
assign m00_couplers_to_processing_system7_0_axi_periph_BVALID = M00_AXI_bvalid;
assign m00_couplers_to_processing_system7_0_axi_periph_RDATA = M00_AXI_rdata[31:0];
assign m00_couplers_to_processing_system7_0_axi_periph_RRESP = M00_AXI_rresp[1:0];
assign m00_couplers_to_processing_system7_0_axi_periph_RVALID = M00_AXI_rvalid;
assign m00_couplers_to_processing_system7_0_axi_periph_WREADY = M00_AXI_wready;
assign m01_couplers_to_processing_system7_0_axi_periph_ARREADY = M01_AXI_arready;
assign m01_couplers_to_processing_system7_0_axi_periph_AWREADY = M01_AXI_awready;
assign m01_couplers_to_processing_system7_0_axi_periph_BRESP = M01_AXI_bresp[1:0];
assign m01_couplers_to_processing_system7_0_axi_periph_BVALID = M01_AXI_bvalid;
assign m01_couplers_to_processing_system7_0_axi_periph_RDATA = M01_AXI_rdata[31:0];
assign m01_couplers_to_processing_system7_0_axi_periph_RRESP = M01_AXI_rresp[1:0];
assign m01_couplers_to_processing_system7_0_axi_periph_RVALID = M01_AXI_rvalid;
assign m01_couplers_to_processing_system7_0_axi_periph_WREADY = M01_AXI_wready;
assign m02_couplers_to_processing_system7_0_axi_periph_ARREADY = M02_AXI_arready;
assign m02_couplers_to_processing_system7_0_axi_periph_AWREADY = M02_AXI_awready;
assign m02_couplers_to_processing_system7_0_axi_periph_BRESP = M02_AXI_bresp[1:0];
assign m02_couplers_to_processing_system7_0_axi_periph_BVALID = M02_AXI_bvalid;
assign m02_couplers_to_processing_system7_0_axi_periph_RDATA = M02_AXI_rdata[31:0];
assign m02_couplers_to_processing_system7_0_axi_periph_RRESP = M02_AXI_rresp[1:0];
assign m02_couplers_to_processing_system7_0_axi_periph_RVALID = M02_AXI_rvalid;
assign m02_couplers_to_processing_system7_0_axi_periph_WREADY = M02_AXI_wready;
assign processing_system7_0_axi_periph_ACLK_net = ACLK;
assign processing_system7_0_axi_periph_ARESETN_net = ARESETN[0];
assign processing_system7_0_axi_periph_to_s00_couplers_ARADDR = S00_AXI_araddr[31:0];
assign processing_system7_0_axi_periph_to_s00_couplers_ARBURST = S00_AXI_arburst[1:0];
assign processing_system7_0_axi_periph_to_s00_couplers_ARCACHE = S00_AXI_arcache[3:0];
assign processing_system7_0_axi_periph_to_s00_couplers_ARID = S00_AXI_arid[11:0];
assign processing_system7_0_axi_periph_to_s00_couplers_ARLEN = S00_AXI_arlen[3:0];
assign processing_system7_0_axi_periph_to_s00_couplers_ARLOCK = S00_AXI_arlock[1:0];
assign processing_system7_0_axi_periph_to_s00_couplers_ARPROT = S00_AXI_arprot[2:0];
assign processing_system7_0_axi_periph_to_s00_couplers_ARQOS = S00_AXI_arqos[3:0];
assign processing_system7_0_axi_periph_to_s00_couplers_ARSIZE = S00_AXI_arsize[2:0];
assign processing_system7_0_axi_periph_to_s00_couplers_ARVALID = S00_AXI_arvalid;
assign processing_system7_0_axi_periph_to_s00_couplers_AWADDR = S00_AXI_awaddr[31:0];
assign processing_system7_0_axi_periph_to_s00_couplers_AWBURST = S00_AXI_awburst[1:0];
assign processing_system7_0_axi_periph_to_s00_couplers_AWCACHE = S00_AXI_awcache[3:0];
assign processing_system7_0_axi_periph_to_s00_couplers_AWID = S00_AXI_awid[11:0];
assign processing_system7_0_axi_periph_to_s00_couplers_AWLEN = S00_AXI_awlen[3:0];
assign processing_system7_0_axi_periph_to_s00_couplers_AWLOCK = S00_AXI_awlock[1:0];
assign processing_system7_0_axi_periph_to_s00_couplers_AWPROT = S00_AXI_awprot[2:0];
assign processing_system7_0_axi_periph_to_s00_couplers_AWQOS = S00_AXI_awqos[3:0];
assign processing_system7_0_axi_periph_to_s00_couplers_AWSIZE = S00_AXI_awsize[2:0];
assign processing_system7_0_axi_periph_to_s00_couplers_AWVALID = S00_AXI_awvalid;
assign processing_system7_0_axi_periph_to_s00_couplers_BREADY = S00_AXI_bready;
assign processing_system7_0_axi_periph_to_s00_couplers_RREADY = S00_AXI_rready;
assign processing_system7_0_axi_periph_to_s00_couplers_WDATA = S00_AXI_wdata[31:0];
assign processing_system7_0_axi_periph_to_s00_couplers_WID = S00_AXI_wid[11:0];
assign processing_system7_0_axi_periph_to_s00_couplers_WLAST = S00_AXI_wlast;
assign processing_system7_0_axi_periph_to_s00_couplers_WSTRB = S00_AXI_wstrb[3:0];
assign processing_system7_0_axi_periph_to_s00_couplers_WVALID = S00_AXI_wvalid;
m00_couplers_imp_WKXF3L m00_couplers
(.M_ACLK(M00_ACLK_1),
.M_ARESETN(M00_ARESETN_1),
.M_AXI_araddr(m00_couplers_to_processing_system7_0_axi_periph_ARADDR),
.M_AXI_arready(m00_couplers_to_processing_system7_0_axi_periph_ARREADY),
.M_AXI_arvalid(m00_couplers_to_processing_system7_0_axi_periph_ARVALID),
.M_AXI_awaddr(m00_couplers_to_processing_system7_0_axi_periph_AWADDR),
.M_AXI_awready(m00_couplers_to_processing_system7_0_axi_periph_AWREADY),
.M_AXI_awvalid(m00_couplers_to_processing_system7_0_axi_periph_AWVALID),
.M_AXI_bready(m00_couplers_to_processing_system7_0_axi_periph_BREADY),
.M_AXI_bresp(m00_couplers_to_processing_system7_0_axi_periph_BRESP),
.M_AXI_bvalid(m00_couplers_to_processing_system7_0_axi_periph_BVALID),
.M_AXI_rdata(m00_couplers_to_processing_system7_0_axi_periph_RDATA),
.M_AXI_rready(m00_couplers_to_processing_system7_0_axi_periph_RREADY),
.M_AXI_rresp(m00_couplers_to_processing_system7_0_axi_periph_RRESP),
.M_AXI_rvalid(m00_couplers_to_processing_system7_0_axi_periph_RVALID),
.M_AXI_wdata(m00_couplers_to_processing_system7_0_axi_periph_WDATA),
.M_AXI_wready(m00_couplers_to_processing_system7_0_axi_periph_WREADY),
.M_AXI_wstrb(m00_couplers_to_processing_system7_0_axi_periph_WSTRB),
.M_AXI_wvalid(m00_couplers_to_processing_system7_0_axi_periph_WVALID),
.S_ACLK(processing_system7_0_axi_periph_ACLK_net),
.S_ARESETN(processing_system7_0_axi_periph_ARESETN_net),
.S_AXI_araddr(xbar_to_m00_couplers_ARADDR[4:0]),
.S_AXI_arready(xbar_to_m00_couplers_ARREADY),
.S_AXI_arvalid(xbar_to_m00_couplers_ARVALID),
.S_AXI_awaddr(xbar_to_m00_couplers_AWADDR[4:0]),
.S_AXI_awready(xbar_to_m00_couplers_AWREADY),
.S_AXI_awvalid(xbar_to_m00_couplers_AWVALID),
.S_AXI_bready(xbar_to_m00_couplers_BREADY),
.S_AXI_bresp(xbar_to_m00_couplers_BRESP),
.S_AXI_bvalid(xbar_to_m00_couplers_BVALID),
.S_AXI_rdata(xbar_to_m00_couplers_RDATA),
.S_AXI_rready(xbar_to_m00_couplers_RREADY),
.S_AXI_rresp(xbar_to_m00_couplers_RRESP),
.S_AXI_rvalid(xbar_to_m00_couplers_RVALID),
.S_AXI_wdata(xbar_to_m00_couplers_WDATA),
.S_AXI_wready(xbar_to_m00_couplers_WREADY),
.S_AXI_wstrb(xbar_to_m00_couplers_WSTRB),
.S_AXI_wvalid(xbar_to_m00_couplers_WVALID));
m01_couplers_imp_1ORP4PS m01_couplers
(.M_ACLK(M01_ACLK_1),
.M_ARESETN(M01_ARESETN_1),
.M_AXI_araddr(m01_couplers_to_processing_system7_0_axi_periph_ARADDR),
.M_AXI_arready(m01_couplers_to_processing_system7_0_axi_periph_ARREADY),
.M_AXI_arvalid(m01_couplers_to_processing_system7_0_axi_periph_ARVALID),
.M_AXI_awaddr(m01_couplers_to_processing_system7_0_axi_periph_AWADDR),
.M_AXI_awready(m01_couplers_to_processing_system7_0_axi_periph_AWREADY),
.M_AXI_awvalid(m01_couplers_to_processing_system7_0_axi_periph_AWVALID),
.M_AXI_bready(m01_couplers_to_processing_system7_0_axi_periph_BREADY),
.M_AXI_bresp(m01_couplers_to_processing_system7_0_axi_periph_BRESP),
.M_AXI_bvalid(m01_couplers_to_processing_system7_0_axi_periph_BVALID),
.M_AXI_rdata(m01_couplers_to_processing_system7_0_axi_periph_RDATA),
.M_AXI_rready(m01_couplers_to_processing_system7_0_axi_periph_RREADY),
.M_AXI_rresp(m01_couplers_to_processing_system7_0_axi_periph_RRESP),
.M_AXI_rvalid(m01_couplers_to_processing_system7_0_axi_periph_RVALID),
.M_AXI_wdata(m01_couplers_to_processing_system7_0_axi_periph_WDATA),
.M_AXI_wready(m01_couplers_to_processing_system7_0_axi_periph_WREADY),
.M_AXI_wvalid(m01_couplers_to_processing_system7_0_axi_periph_WVALID),
.S_ACLK(processing_system7_0_axi_periph_ACLK_net),
.S_ARESETN(processing_system7_0_axi_periph_ARESETN_net),
.S_AXI_araddr(xbar_to_m01_couplers_ARADDR[41:32]),
.S_AXI_arready(xbar_to_m01_couplers_ARREADY),
.S_AXI_arvalid(xbar_to_m01_couplers_ARVALID),
.S_AXI_awaddr(xbar_to_m01_couplers_AWADDR[41:32]),
.S_AXI_awready(xbar_to_m01_couplers_AWREADY),
.S_AXI_awvalid(xbar_to_m01_couplers_AWVALID),
.S_AXI_bready(xbar_to_m01_couplers_BREADY),
.S_AXI_bresp(xbar_to_m01_couplers_BRESP),
.S_AXI_bvalid(xbar_to_m01_couplers_BVALID),
.S_AXI_rdata(xbar_to_m01_couplers_RDATA),
.S_AXI_rready(xbar_to_m01_couplers_RREADY),
.S_AXI_rresp(xbar_to_m01_couplers_RRESP),
.S_AXI_rvalid(xbar_to_m01_couplers_RVALID),
.S_AXI_wdata(xbar_to_m01_couplers_WDATA),
.S_AXI_wready(xbar_to_m01_couplers_WREADY),
.S_AXI_wvalid(xbar_to_m01_couplers_WVALID));
m02_couplers_imp_1VD9O7M m02_couplers
(.M_ACLK(M02_ACLK_1),
.M_ARESETN(M02_ARESETN_1),
.M_AXI_araddr(m02_couplers_to_processing_system7_0_axi_periph_ARADDR),
.M_AXI_arready(m02_couplers_to_processing_system7_0_axi_periph_ARREADY),
.M_AXI_arvalid(m02_couplers_to_processing_system7_0_axi_periph_ARVALID),
.M_AXI_awaddr(m02_couplers_to_processing_system7_0_axi_periph_AWADDR),
.M_AXI_awready(m02_couplers_to_processing_system7_0_axi_periph_AWREADY),
.M_AXI_awvalid(m02_couplers_to_processing_system7_0_axi_periph_AWVALID),
.M_AXI_bready(m02_couplers_to_processing_system7_0_axi_periph_BREADY),
.M_AXI_bresp(m02_couplers_to_processing_system7_0_axi_periph_BRESP),
.M_AXI_bvalid(m02_couplers_to_processing_system7_0_axi_periph_BVALID),
.M_AXI_rdata(m02_couplers_to_processing_system7_0_axi_periph_RDATA),
.M_AXI_rready(m02_couplers_to_processing_system7_0_axi_periph_RREADY),
.M_AXI_rresp(m02_couplers_to_processing_system7_0_axi_periph_RRESP),
.M_AXI_rvalid(m02_couplers_to_processing_system7_0_axi_periph_RVALID),
.M_AXI_wdata(m02_couplers_to_processing_system7_0_axi_periph_WDATA),
.M_AXI_wready(m02_couplers_to_processing_system7_0_axi_periph_WREADY),
.M_AXI_wstrb(m02_couplers_to_processing_system7_0_axi_periph_WSTRB),
.M_AXI_wvalid(m02_couplers_to_processing_system7_0_axi_periph_WVALID),
.S_ACLK(processing_system7_0_axi_periph_ACLK_net),
.S_ARESETN(processing_system7_0_axi_periph_ARESETN_net),
.S_AXI_araddr(xbar_to_m02_couplers_ARADDR[68:64]),
.S_AXI_arready(xbar_to_m02_couplers_ARREADY),
.S_AXI_arvalid(xbar_to_m02_couplers_ARVALID),
.S_AXI_awaddr(xbar_to_m02_couplers_AWADDR[68:64]),
.S_AXI_awready(xbar_to_m02_couplers_AWREADY),
.S_AXI_awvalid(xbar_to_m02_couplers_AWVALID),
.S_AXI_bready(xbar_to_m02_couplers_BREADY),
.S_AXI_bresp(xbar_to_m02_couplers_BRESP),
.S_AXI_bvalid(xbar_to_m02_couplers_BVALID),
.S_AXI_rdata(xbar_to_m02_couplers_RDATA),
.S_AXI_rready(xbar_to_m02_couplers_RREADY),
.S_AXI_rresp(xbar_to_m02_couplers_RRESP),
.S_AXI_rvalid(xbar_to_m02_couplers_RVALID),
.S_AXI_wdata(xbar_to_m02_couplers_WDATA),
.S_AXI_wready(xbar_to_m02_couplers_WREADY),
.S_AXI_wstrb(xbar_to_m02_couplers_WSTRB),
.S_AXI_wvalid(xbar_to_m02_couplers_WVALID));
s00_couplers_imp_IK3G2O s00_couplers
(.M_ACLK(processing_system7_0_axi_periph_ACLK_net),
.M_ARESETN(processing_system7_0_axi_periph_ARESETN_net),
.M_AXI_araddr(s00_couplers_to_xbar_ARADDR),
.M_AXI_arprot(s00_couplers_to_xbar_ARPROT),
.M_AXI_arready(s00_couplers_to_xbar_ARREADY),
.M_AXI_arvalid(s00_couplers_to_xbar_ARVALID),
.M_AXI_awaddr(s00_couplers_to_xbar_AWADDR),
.M_AXI_awprot(s00_couplers_to_xbar_AWPROT),
.M_AXI_awready(s00_couplers_to_xbar_AWREADY),
.M_AXI_awvalid(s00_couplers_to_xbar_AWVALID),
.M_AXI_bready(s00_couplers_to_xbar_BREADY),
.M_AXI_bresp(s00_couplers_to_xbar_BRESP),
.M_AXI_bvalid(s00_couplers_to_xbar_BVALID),
.M_AXI_rdata(s00_couplers_to_xbar_RDATA),
.M_AXI_rready(s00_couplers_to_xbar_RREADY),
.M_AXI_rresp(s00_couplers_to_xbar_RRESP),
.M_AXI_rvalid(s00_couplers_to_xbar_RVALID),
.M_AXI_wdata(s00_couplers_to_xbar_WDATA),
.M_AXI_wready(s00_couplers_to_xbar_WREADY),
.M_AXI_wstrb(s00_couplers_to_xbar_WSTRB),
.M_AXI_wvalid(s00_couplers_to_xbar_WVALID),
.S_ACLK(S00_ACLK_1),
.S_ARESETN(S00_ARESETN_1),
.S_AXI_araddr(processing_system7_0_axi_periph_to_s00_couplers_ARADDR),
.S_AXI_arburst(processing_system7_0_axi_periph_to_s00_couplers_ARBURST),
.S_AXI_arcache(processing_system7_0_axi_periph_to_s00_couplers_ARCACHE),
.S_AXI_arid(processing_system7_0_axi_periph_to_s00_couplers_ARID),
.S_AXI_arlen(processing_system7_0_axi_periph_to_s00_couplers_ARLEN),
.S_AXI_arlock(processing_system7_0_axi_periph_to_s00_couplers_ARLOCK),
.S_AXI_arprot(processing_system7_0_axi_periph_to_s00_couplers_ARPROT),
.S_AXI_arqos(processing_system7_0_axi_periph_to_s00_couplers_ARQOS),
.S_AXI_arready(processing_system7_0_axi_periph_to_s00_couplers_ARREADY),
.S_AXI_arsize(processing_system7_0_axi_periph_to_s00_couplers_ARSIZE),
.S_AXI_arvalid(processing_system7_0_axi_periph_to_s00_couplers_ARVALID),
.S_AXI_awaddr(processing_system7_0_axi_periph_to_s00_couplers_AWADDR),
.S_AXI_awburst(processing_system7_0_axi_periph_to_s00_couplers_AWBURST),
.S_AXI_awcache(processing_system7_0_axi_periph_to_s00_couplers_AWCACHE),
.S_AXI_awid(processing_system7_0_axi_periph_to_s00_couplers_AWID),
.S_AXI_awlen(processing_system7_0_axi_periph_to_s00_couplers_AWLEN),
.S_AXI_awlock(processing_system7_0_axi_periph_to_s00_couplers_AWLOCK),
.S_AXI_awprot(processing_system7_0_axi_periph_to_s00_couplers_AWPROT),
.S_AXI_awqos(processing_system7_0_axi_periph_to_s00_couplers_AWQOS),
.S_AXI_awready(processing_system7_0_axi_periph_to_s00_couplers_AWREADY),
.S_AXI_awsize(processing_system7_0_axi_periph_to_s00_couplers_AWSIZE),
.S_AXI_awvalid(processing_system7_0_axi_periph_to_s00_couplers_AWVALID),
.S_AXI_bid(processing_system7_0_axi_periph_to_s00_couplers_BID),
.S_AXI_bready(processing_system7_0_axi_periph_to_s00_couplers_BREADY),
.S_AXI_bresp(processing_system7_0_axi_periph_to_s00_couplers_BRESP),
.S_AXI_bvalid(processing_system7_0_axi_periph_to_s00_couplers_BVALID),
.S_AXI_rdata(processing_system7_0_axi_periph_to_s00_couplers_RDATA),
.S_AXI_rid(processing_system7_0_axi_periph_to_s00_couplers_RID),
.S_AXI_rlast(processing_system7_0_axi_periph_to_s00_couplers_RLAST),
.S_AXI_rready(processing_system7_0_axi_periph_to_s00_couplers_RREADY),
.S_AXI_rresp(processing_system7_0_axi_periph_to_s00_couplers_RRESP),
.S_AXI_rvalid(processing_system7_0_axi_periph_to_s00_couplers_RVALID),
.S_AXI_wdata(processing_system7_0_axi_periph_to_s00_couplers_WDATA),
.S_AXI_wid(processing_system7_0_axi_periph_to_s00_couplers_WID),
.S_AXI_wlast(processing_system7_0_axi_periph_to_s00_couplers_WLAST),
.S_AXI_wready(processing_system7_0_axi_periph_to_s00_couplers_WREADY),
.S_AXI_wstrb(processing_system7_0_axi_periph_to_s00_couplers_WSTRB),
.S_AXI_wvalid(processing_system7_0_axi_periph_to_s00_couplers_WVALID));
system_xbar_0 xbar
(.aclk(processing_system7_0_axi_periph_ACLK_net),
.aresetn(processing_system7_0_axi_periph_ARESETN_net),
.m_axi_araddr({xbar_to_m02_couplers_ARADDR,xbar_to_m01_couplers_ARADDR,xbar_to_m00_couplers_ARADDR}),
.m_axi_arready({xbar_to_m02_couplers_ARREADY,xbar_to_m01_couplers_ARREADY,xbar_to_m00_couplers_ARREADY}),
.m_axi_arvalid({xbar_to_m02_couplers_ARVALID,xbar_to_m01_couplers_ARVALID,xbar_to_m00_couplers_ARVALID}),
.m_axi_awaddr({xbar_to_m02_couplers_AWADDR,xbar_to_m01_couplers_AWADDR,xbar_to_m00_couplers_AWADDR}),
.m_axi_awready({xbar_to_m02_couplers_AWREADY,xbar_to_m01_couplers_AWREADY,xbar_to_m00_couplers_AWREADY}),
.m_axi_awvalid({xbar_to_m02_couplers_AWVALID,xbar_to_m01_couplers_AWVALID,xbar_to_m00_couplers_AWVALID}),
.m_axi_bready({xbar_to_m02_couplers_BREADY,xbar_to_m01_couplers_BREADY,xbar_to_m00_couplers_BREADY}),
.m_axi_bresp({xbar_to_m02_couplers_BRESP,xbar_to_m01_couplers_BRESP,xbar_to_m00_couplers_BRESP}),
.m_axi_bvalid({xbar_to_m02_couplers_BVALID,xbar_to_m01_couplers_BVALID,xbar_to_m00_couplers_BVALID}),
.m_axi_rdata({xbar_to_m02_couplers_RDATA,xbar_to_m01_couplers_RDATA,xbar_to_m00_couplers_RDATA}),
.m_axi_rready({xbar_to_m02_couplers_RREADY,xbar_to_m01_couplers_RREADY,xbar_to_m00_couplers_RREADY}),
.m_axi_rresp({xbar_to_m02_couplers_RRESP,xbar_to_m01_couplers_RRESP,xbar_to_m00_couplers_RRESP}),
.m_axi_rvalid({xbar_to_m02_couplers_RVALID,xbar_to_m01_couplers_RVALID,xbar_to_m00_couplers_RVALID}),
.m_axi_wdata({xbar_to_m02_couplers_WDATA,xbar_to_m01_couplers_WDATA,xbar_to_m00_couplers_WDATA}),
.m_axi_wready({xbar_to_m02_couplers_WREADY,xbar_to_m01_couplers_WREADY,xbar_to_m00_couplers_WREADY}),
.m_axi_wstrb({xbar_to_m02_couplers_WSTRB,NLW_xbar_m_axi_wstrb_UNCONNECTED[7:4],xbar_to_m00_couplers_WSTRB}),
.m_axi_wvalid({xbar_to_m02_couplers_WVALID,xbar_to_m01_couplers_WVALID,xbar_to_m00_couplers_WVALID}),
.s_axi_araddr(s00_couplers_to_xbar_ARADDR),
.s_axi_arprot(s00_couplers_to_xbar_ARPROT),
.s_axi_arready(s00_couplers_to_xbar_ARREADY),
.s_axi_arvalid(s00_couplers_to_xbar_ARVALID),
.s_axi_awaddr(s00_couplers_to_xbar_AWADDR),
.s_axi_awprot(s00_couplers_to_xbar_AWPROT),
.s_axi_awready(s00_couplers_to_xbar_AWREADY),
.s_axi_awvalid(s00_couplers_to_xbar_AWVALID),
.s_axi_bready(s00_couplers_to_xbar_BREADY),
.s_axi_bresp(s00_couplers_to_xbar_BRESP),
.s_axi_bvalid(s00_couplers_to_xbar_BVALID),
.s_axi_rdata(s00_couplers_to_xbar_RDATA),
.s_axi_rready(s00_couplers_to_xbar_RREADY),
.s_axi_rresp(s00_couplers_to_xbar_RRESP),
.s_axi_rvalid(s00_couplers_to_xbar_RVALID),
.s_axi_wdata(s00_couplers_to_xbar_WDATA),
.s_axi_wready(s00_couplers_to_xbar_WREADY),
.s_axi_wstrb(s00_couplers_to_xbar_WSTRB),
.s_axi_wvalid(s00_couplers_to_xbar_WVALID));
endmodule |
module sky130_fd_sc_hd__fill ();
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// No contents.
endmodule |
module or1200_freeze(
// Clock and reset
clk, rst,
// Internal i/f
multicycle, flushpipe, extend_flush, lsu_stall, if_stall,
lsu_unstall, du_stall, mac_stall,
abort_ex,
genpc_freeze, if_freeze, id_freeze, ex_freeze, wb_freeze,
icpu_ack_i, icpu_err_i
);
//
// I/O
//
input clk;
input rst;
input [`OR1200_MULTICYCLE_WIDTH-1:0] multicycle;
input flushpipe;
input extend_flush;
input lsu_stall;
input if_stall;
input lsu_unstall;
input abort_ex;
input du_stall;
input mac_stall;
output genpc_freeze;
output if_freeze;
output id_freeze;
output ex_freeze;
output wb_freeze;
input icpu_ack_i;
input icpu_err_i;
//
// Internal wires and regs
//
wire multicycle_freeze;
reg [`OR1200_MULTICYCLE_WIDTH-1:0] multicycle_cnt;
reg flushpipe_r;
//
// Pipeline freeze
//
// Rules how to create freeze signals:
// 1. Not overwriting pipeline stages:
// Freze signals at the beginning of pipeline (such as if_freeze) can be asserted more
// often than freeze signals at the of pipeline (such as wb_freeze). In other words, wb_freeze must never
// be asserted when ex_freeze is not. ex_freeze must never be asserted when id_freeze is not etc.
//
// 2. Inserting NOPs in the middle of pipeline only if supported:
// At this time, only ex_freeze (and wb_freeze) can be deassrted when id_freeze (and if_freeze) are asserted.
// This way NOP is asserted from stage ID into EX stage.
//
//assign genpc_freeze = du_stall | flushpipe_r | lsu_stall;
assign genpc_freeze = du_stall | flushpipe_r;
assign if_freeze = id_freeze | extend_flush;
//assign id_freeze = (lsu_stall | (~lsu_unstall & if_stall) | multicycle_freeze | force_dslot_fetch) & ~flushpipe | du_stall;
assign id_freeze = (lsu_stall | (~lsu_unstall & if_stall) | multicycle_freeze ) | du_stall | mac_stall;
assign ex_freeze = wb_freeze;
//assign wb_freeze = (lsu_stall | (~lsu_unstall & if_stall) | multicycle_freeze) & ~flushpipe | du_stall | mac_stall;
assign wb_freeze = (lsu_stall | (~lsu_unstall & if_stall) | multicycle_freeze) | du_stall | mac_stall | abort_ex;
//
// registered flushpipe
//
always @(posedge clk or posedge rst)
if (rst)
flushpipe_r <= #1 1'b0;
else if (icpu_ack_i | icpu_err_i)
// else if (!if_stall)
flushpipe_r <= #1 flushpipe;
else if (!flushpipe)
flushpipe_r <= #1 1'b0;
//
// Multicycle freeze
//
assign multicycle_freeze = |multicycle_cnt;
//
// Multicycle counter
//
always @(posedge clk or posedge rst)
if (rst)
multicycle_cnt <= #1 2'b00;
else if (|multicycle_cnt)
multicycle_cnt <= #1 multicycle_cnt - 2'd1;
else if (|multicycle & !ex_freeze)
multicycle_cnt <= #1 multicycle;
//
// Abstruct the signal we are interested in
//
//always @(posedge clk or posedge rst)
//$show_signal_value(or1200_freeze, if_freeze, id_freeze, ex_freeze, wb_freeze );
endmodule |
module sky130_fd_sc_ms__sdfxbp (
//# {{data|Data Signals}}
input D ,
output Q ,
output Q_N ,
//# {{scanchain|Scan Chain}}
input SCD ,
input SCE ,
//# {{clocks|Clocking}}
input CLK ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule |
module master_clock (
input wire refclk, // refclk.clk
input wire rst, // reset.reset
output wire outclk_0, // outclk0.clk
output wire outclk_1 // outclk1.clk
);
master_clock_0002 master_clock_inst (
.refclk (refclk), // refclk.clk
.rst (rst), // reset.reset
.outclk_0 (outclk_0), // outclk0.clk
.outclk_1 (outclk_1), // outclk1.clk
.locked () // (terminated)
);
endmodule |
module q_mul8
(
input CLK,
input RESET_X,
input INPUT_EN,
input [7:0] A_IN,
input [7:0] B_IN,
input [7:0] A_IN_INV,
input [7:0] B_IN_INV,
input A_SEL_INV,
input B_SEL_INV,
output OUTPUT_EN,
output [7:0] C_OUT,
input [31:0] MLC_GAGB,
// MULL ADD1
input [31:0] ML1_GAIN,
input [31:0] ML1_QPARAM,
input [31:0] ML2_GAIN,
input [31:0] ML2_QPARAM,
output [15:0] MIN,
output [15:0] MAX
);
// # vector
// AdBd_qt, AdBd_min, AdBd_max = q_mul_core(a_qt, Adash_min, Adash_max, b_qt, Bdash_min, Bdash_max, debug=debug)
// C_qt_0, C_qt_0_min, C_qt_0_max = q_add(qt_A_bmin, A_bmin_min, A_bmin_max, qt_B_amin, B_amin_min, B_amin_max, debug=debug)
// C_qt, c_min, c_max = q_add(AdBd_qt, AdBd_min, AdBd_max, C_qt_0, C_qt_0_min, C_qt_0_max, debug=debug)
wire [7:0] AdBd_qt;
wire mul_core_en;
wire [7:0] C_qt_0;
wire [7:0] qt_A_bmin;
wire [7:0] qt_B_amin;
wire add_1st_en;
assign qt_A_bmin = A_SEL_INV ? A_IN_INV : A_IN;
assign qt_B_amin = B_SEL_INV ? B_IN_INV : B_IN;
reg [7:0] AdBd_qt_1t;
q_mul_core8 mul_core
(
.CLK(CLK),
.RESET_X(RESET_X),
.INPUT_EN(INPUT_EN),
.A_IN(A_IN),
.B_IN(B_IN),
.OUTPUT_EN(mul_core_en),
.C_OUT(AdBd_qt),
.MLC_GAGB(MLC_GAGB)
);
q_add8 add_1st
(
.CLK(CLK),
.RESET_X(RESET_X),
.INPUT_EN(INPUT_EN),
.A_IN(qt_A_bmin),
.B_IN(qt_B_amin),
.OUTPUT_EN(add_1st_en),
.C_OUT(C_qt_0),
.GAIN(ML1_GAIN),
.Q_PARAM(ML1_QPARAM),
.MIN(),
.MAX()
);
q_add8 add_2nd
(
.CLK(CLK),
.RESET_X(RESET_X),
.INPUT_EN(add_1st_en),
.A_IN(AdBd_qt_1t),
.B_IN(C_qt_0),
.OUTPUT_EN(OUTPUT_EN),
.C_OUT(C_OUT),
.GAIN(ML2_GAIN),
.Q_PARAM(ML2_QPARAM),
.MIN(MIN),
.MAX(MAX)
);
always @ (posedge CLK or negedge RESET_X)begin
if (RESET_X == 0)begin
AdBd_qt_1t <= 8'h00;
end else begin
AdBd_qt_1t <= AdBd_qt;
end
end
endmodule |
module fpga_core #
(
parameter TARGET = "GENERIC"
)
(
/*
* Clock: 125MHz
* Synchronous reset
*/
input wire clk,
input wire clk90,
input wire rst,
/*
* GPIO
*/
input wire btnu,
input wire btnl,
input wire btnd,
input wire btnr,
input wire btnc,
input wire [7:0] sw,
output wire [7:0] led,
/*
* Ethernet: 1000BASE-T RGMII
*/
input wire phy_rx_clk,
input wire [3:0] phy_rxd,
input wire phy_rx_ctl,
output wire phy_tx_clk,
output wire [3:0] phy_txd,
output wire phy_tx_ctl,
output wire phy_reset_n,
input wire phy_int_n,
input wire phy_pme_n,
/*
* UART: 115200 bps, 8N1
*/
input wire uart_rxd,
output wire uart_txd
);
// AXI between MAC and Ethernet modules
wire [7:0] rx_axis_tdata;
wire rx_axis_tvalid;
wire rx_axis_tready;
wire rx_axis_tlast;
wire rx_axis_tuser;
wire [7:0] tx_axis_tdata;
wire tx_axis_tvalid;
wire tx_axis_tready;
wire tx_axis_tlast;
wire tx_axis_tuser;
// Ethernet frame between Ethernet modules and UDP stack
wire rx_eth_hdr_ready;
wire rx_eth_hdr_valid;
wire [47:0] rx_eth_dest_mac;
wire [47:0] rx_eth_src_mac;
wire [15:0] rx_eth_type;
wire [7:0] rx_eth_payload_axis_tdata;
wire rx_eth_payload_axis_tvalid;
wire rx_eth_payload_axis_tready;
wire rx_eth_payload_axis_tlast;
wire rx_eth_payload_axis_tuser;
wire tx_eth_hdr_ready;
wire tx_eth_hdr_valid;
wire [47:0] tx_eth_dest_mac;
wire [47:0] tx_eth_src_mac;
wire [15:0] tx_eth_type;
wire [7:0] tx_eth_payload_axis_tdata;
wire tx_eth_payload_axis_tvalid;
wire tx_eth_payload_axis_tready;
wire tx_eth_payload_axis_tlast;
wire tx_eth_payload_axis_tuser;
// IP frame connections
wire rx_ip_hdr_valid;
wire rx_ip_hdr_ready;
wire [47:0] rx_ip_eth_dest_mac;
wire [47:0] rx_ip_eth_src_mac;
wire [15:0] rx_ip_eth_type;
wire [3:0] rx_ip_version;
wire [3:0] rx_ip_ihl;
wire [5:0] rx_ip_dscp;
wire [1:0] rx_ip_ecn;
wire [15:0] rx_ip_length;
wire [15:0] rx_ip_identification;
wire [2:0] rx_ip_flags;
wire [12:0] rx_ip_fragment_offset;
wire [7:0] rx_ip_ttl;
wire [7:0] rx_ip_protocol;
wire [15:0] rx_ip_header_checksum;
wire [31:0] rx_ip_source_ip;
wire [31:0] rx_ip_dest_ip;
wire [7:0] rx_ip_payload_axis_tdata;
wire rx_ip_payload_axis_tvalid;
wire rx_ip_payload_axis_tready;
wire rx_ip_payload_axis_tlast;
wire rx_ip_payload_axis_tuser;
wire tx_ip_hdr_valid;
wire tx_ip_hdr_ready;
wire [5:0] tx_ip_dscp;
wire [1:0] tx_ip_ecn;
wire [15:0] tx_ip_length;
wire [7:0] tx_ip_ttl;
wire [7:0] tx_ip_protocol;
wire [31:0] tx_ip_source_ip;
wire [31:0] tx_ip_dest_ip;
wire [7:0] tx_ip_payload_axis_tdata;
wire tx_ip_payload_axis_tvalid;
wire tx_ip_payload_axis_tready;
wire tx_ip_payload_axis_tlast;
wire tx_ip_payload_axis_tuser;
// UDP frame connections
wire rx_udp_hdr_valid;
wire rx_udp_hdr_ready;
wire [47:0] rx_udp_eth_dest_mac;
wire [47:0] rx_udp_eth_src_mac;
wire [15:0] rx_udp_eth_type;
wire [3:0] rx_udp_ip_version;
wire [3:0] rx_udp_ip_ihl;
wire [5:0] rx_udp_ip_dscp;
wire [1:0] rx_udp_ip_ecn;
wire [15:0] rx_udp_ip_length;
wire [15:0] rx_udp_ip_identification;
wire [2:0] rx_udp_ip_flags;
wire [12:0] rx_udp_ip_fragment_offset;
wire [7:0] rx_udp_ip_ttl;
wire [7:0] rx_udp_ip_protocol;
wire [15:0] rx_udp_ip_header_checksum;
wire [31:0] rx_udp_ip_source_ip;
wire [31:0] rx_udp_ip_dest_ip;
wire [15:0] rx_udp_source_port;
wire [15:0] rx_udp_dest_port;
wire [15:0] rx_udp_length;
wire [15:0] rx_udp_checksum;
wire [7:0] rx_udp_payload_axis_tdata;
wire rx_udp_payload_axis_tvalid;
wire rx_udp_payload_axis_tready;
wire rx_udp_payload_axis_tlast;
wire rx_udp_payload_axis_tuser;
wire tx_udp_hdr_valid;
wire tx_udp_hdr_ready;
wire [5:0] tx_udp_ip_dscp;
wire [1:0] tx_udp_ip_ecn;
wire [7:0] tx_udp_ip_ttl;
wire [31:0] tx_udp_ip_source_ip;
wire [31:0] tx_udp_ip_dest_ip;
wire [15:0] tx_udp_source_port;
wire [15:0] tx_udp_dest_port;
wire [15:0] tx_udp_length;
wire [15:0] tx_udp_checksum;
wire [7:0] tx_udp_payload_axis_tdata;
wire tx_udp_payload_axis_tvalid;
wire tx_udp_payload_axis_tready;
wire tx_udp_payload_axis_tlast;
wire tx_udp_payload_axis_tuser;
wire [7:0] rx_fifo_udp_payload_axis_tdata;
wire rx_fifo_udp_payload_axis_tvalid;
wire rx_fifo_udp_payload_axis_tready;
wire rx_fifo_udp_payload_axis_tlast;
wire rx_fifo_udp_payload_axis_tuser;
wire [7:0] tx_fifo_udp_payload_axis_tdata;
wire tx_fifo_udp_payload_axis_tvalid;
wire tx_fifo_udp_payload_axis_tready;
wire tx_fifo_udp_payload_axis_tlast;
wire tx_fifo_udp_payload_axis_tuser;
// Configuration
wire [47:0] local_mac = 48'h02_00_00_00_00_00;
wire [31:0] local_ip = {8'd192, 8'd168, 8'd1, 8'd128};
wire [31:0] gateway_ip = {8'd192, 8'd168, 8'd1, 8'd1};
wire [31:0] subnet_mask = {8'd255, 8'd255, 8'd255, 8'd0};
// IP ports not used
assign rx_ip_hdr_ready = 1;
assign rx_ip_payload_axis_tready = 1;
assign tx_ip_hdr_valid = 0;
assign tx_ip_dscp = 0;
assign tx_ip_ecn = 0;
assign tx_ip_length = 0;
assign tx_ip_ttl = 0;
assign tx_ip_protocol = 0;
assign tx_ip_source_ip = 0;
assign tx_ip_dest_ip = 0;
assign tx_ip_payload_axis_tdata = 0;
assign tx_ip_payload_axis_tvalid = 0;
assign tx_ip_payload_axis_tlast = 0;
assign tx_ip_payload_axis_tuser = 0;
// Loop back UDP
wire match_cond = rx_udp_dest_port == 1234;
wire no_match = !match_cond;
reg match_cond_reg = 0;
reg no_match_reg = 0;
always @(posedge clk) begin
if (rst) begin
match_cond_reg <= 0;
no_match_reg <= 0;
end else begin
if (rx_udp_payload_axis_tvalid) begin
if ((!match_cond_reg && !no_match_reg) ||
(rx_udp_payload_axis_tvalid && rx_udp_payload_axis_tready && rx_udp_payload_axis_tlast)) begin
match_cond_reg <= match_cond;
no_match_reg <= no_match;
end
end else begin
match_cond_reg <= 0;
no_match_reg <= 0;
end
end
end
assign tx_udp_hdr_valid = rx_udp_hdr_valid && match_cond;
assign rx_udp_hdr_ready = (tx_eth_hdr_ready && match_cond) || no_match;
assign tx_udp_ip_dscp = 0;
assign tx_udp_ip_ecn = 0;
assign tx_udp_ip_ttl = 64;
assign tx_udp_ip_source_ip = local_ip;
assign tx_udp_ip_dest_ip = rx_udp_ip_source_ip;
assign tx_udp_source_port = rx_udp_dest_port;
assign tx_udp_dest_port = rx_udp_source_port;
assign tx_udp_length = rx_udp_length;
assign tx_udp_checksum = 0;
assign tx_udp_payload_axis_tdata = tx_fifo_udp_payload_axis_tdata;
assign tx_udp_payload_axis_tvalid = tx_fifo_udp_payload_axis_tvalid;
assign tx_fifo_udp_payload_axis_tready = tx_udp_payload_axis_tready;
assign tx_udp_payload_axis_tlast = tx_fifo_udp_payload_axis_tlast;
assign tx_udp_payload_axis_tuser = tx_fifo_udp_payload_axis_tuser;
assign rx_fifo_udp_payload_axis_tdata = rx_udp_payload_axis_tdata;
assign rx_fifo_udp_payload_axis_tvalid = rx_udp_payload_axis_tvalid && match_cond_reg;
assign rx_udp_payload_axis_tready = (rx_fifo_udp_payload_axis_tready && match_cond_reg) || no_match_reg;
assign rx_fifo_udp_payload_axis_tlast = rx_udp_payload_axis_tlast;
assign rx_fifo_udp_payload_axis_tuser = rx_udp_payload_axis_tuser;
// Place first payload byte onto LEDs
reg valid_last = 0;
reg [7:0] led_reg = 0;
always @(posedge clk) begin
if (rst) begin
led_reg <= 0;
end else begin
if (tx_udp_payload_axis_tvalid) begin
if (!valid_last) begin
led_reg <= tx_udp_payload_axis_tdata;
valid_last <= 1'b1;
end
if (tx_udp_payload_axis_tlast) begin
valid_last <= 1'b0;
end
end
end
end
//assign led = sw;
assign led = led_reg;
assign phy_reset_n = !rst;
assign uart_txd = 0;
eth_mac_1g_rgmii_fifo #(
.TARGET(TARGET),
.IODDR_STYLE("IODDR"),
.CLOCK_INPUT_STYLE("BUFR"),
.USE_CLK90("TRUE"),
.ENABLE_PADDING(1),
.MIN_FRAME_LENGTH(64),
.TX_FIFO_DEPTH(4096),
.TX_FRAME_FIFO(1),
.RX_FIFO_DEPTH(4096),
.RX_FRAME_FIFO(1)
)
eth_mac_inst (
.gtx_clk(clk),
.gtx_clk90(clk90),
.gtx_rst(rst),
.logic_clk(clk),
.logic_rst(rst),
.tx_axis_tdata(tx_axis_tdata),
.tx_axis_tvalid(tx_axis_tvalid),
.tx_axis_tready(tx_axis_tready),
.tx_axis_tlast(tx_axis_tlast),
.tx_axis_tuser(tx_axis_tuser),
.rx_axis_tdata(rx_axis_tdata),
.rx_axis_tvalid(rx_axis_tvalid),
.rx_axis_tready(rx_axis_tready),
.rx_axis_tlast(rx_axis_tlast),
.rx_axis_tuser(rx_axis_tuser),
.rgmii_rx_clk(phy_rx_clk),
.rgmii_rxd(phy_rxd),
.rgmii_rx_ctl(phy_rx_ctl),
.rgmii_tx_clk(phy_tx_clk),
.rgmii_txd(phy_txd),
.rgmii_tx_ctl(phy_tx_ctl),
.tx_fifo_overflow(),
.tx_fifo_bad_frame(),
.tx_fifo_good_frame(),
.rx_error_bad_frame(),
.rx_error_bad_fcs(),
.rx_fifo_overflow(),
.rx_fifo_bad_frame(),
.rx_fifo_good_frame(),
.speed(),
.ifg_delay(12)
);
eth_axis_rx
eth_axis_rx_inst (
.clk(clk),
.rst(rst),
// AXI input
.s_axis_tdata(rx_axis_tdata),
.s_axis_tvalid(rx_axis_tvalid),
.s_axis_tready(rx_axis_tready),
.s_axis_tlast(rx_axis_tlast),
.s_axis_tuser(rx_axis_tuser),
// Ethernet frame output
.m_eth_hdr_valid(rx_eth_hdr_valid),
.m_eth_hdr_ready(rx_eth_hdr_ready),
.m_eth_dest_mac(rx_eth_dest_mac),
.m_eth_src_mac(rx_eth_src_mac),
.m_eth_type(rx_eth_type),
.m_eth_payload_axis_tdata(rx_eth_payload_axis_tdata),
.m_eth_payload_axis_tvalid(rx_eth_payload_axis_tvalid),
.m_eth_payload_axis_tready(rx_eth_payload_axis_tready),
.m_eth_payload_axis_tlast(rx_eth_payload_axis_tlast),
.m_eth_payload_axis_tuser(rx_eth_payload_axis_tuser),
// Status signals
.busy(),
.error_header_early_termination()
);
eth_axis_tx
eth_axis_tx_inst (
.clk(clk),
.rst(rst),
// Ethernet frame input
.s_eth_hdr_valid(tx_eth_hdr_valid),
.s_eth_hdr_ready(tx_eth_hdr_ready),
.s_eth_dest_mac(tx_eth_dest_mac),
.s_eth_src_mac(tx_eth_src_mac),
.s_eth_type(tx_eth_type),
.s_eth_payload_axis_tdata(tx_eth_payload_axis_tdata),
.s_eth_payload_axis_tvalid(tx_eth_payload_axis_tvalid),
.s_eth_payload_axis_tready(tx_eth_payload_axis_tready),
.s_eth_payload_axis_tlast(tx_eth_payload_axis_tlast),
.s_eth_payload_axis_tuser(tx_eth_payload_axis_tuser),
// AXI output
.m_axis_tdata(tx_axis_tdata),
.m_axis_tvalid(tx_axis_tvalid),
.m_axis_tready(tx_axis_tready),
.m_axis_tlast(tx_axis_tlast),
.m_axis_tuser(tx_axis_tuser),
// Status signals
.busy()
);
udp_complete
udp_complete_inst (
.clk(clk),
.rst(rst),
// Ethernet frame input
.s_eth_hdr_valid(rx_eth_hdr_valid),
.s_eth_hdr_ready(rx_eth_hdr_ready),
.s_eth_dest_mac(rx_eth_dest_mac),
.s_eth_src_mac(rx_eth_src_mac),
.s_eth_type(rx_eth_type),
.s_eth_payload_axis_tdata(rx_eth_payload_axis_tdata),
.s_eth_payload_axis_tvalid(rx_eth_payload_axis_tvalid),
.s_eth_payload_axis_tready(rx_eth_payload_axis_tready),
.s_eth_payload_axis_tlast(rx_eth_payload_axis_tlast),
.s_eth_payload_axis_tuser(rx_eth_payload_axis_tuser),
// Ethernet frame output
.m_eth_hdr_valid(tx_eth_hdr_valid),
.m_eth_hdr_ready(tx_eth_hdr_ready),
.m_eth_dest_mac(tx_eth_dest_mac),
.m_eth_src_mac(tx_eth_src_mac),
.m_eth_type(tx_eth_type),
.m_eth_payload_axis_tdata(tx_eth_payload_axis_tdata),
.m_eth_payload_axis_tvalid(tx_eth_payload_axis_tvalid),
.m_eth_payload_axis_tready(tx_eth_payload_axis_tready),
.m_eth_payload_axis_tlast(tx_eth_payload_axis_tlast),
.m_eth_payload_axis_tuser(tx_eth_payload_axis_tuser),
// IP frame input
.s_ip_hdr_valid(tx_ip_hdr_valid),
.s_ip_hdr_ready(tx_ip_hdr_ready),
.s_ip_dscp(tx_ip_dscp),
.s_ip_ecn(tx_ip_ecn),
.s_ip_length(tx_ip_length),
.s_ip_ttl(tx_ip_ttl),
.s_ip_protocol(tx_ip_protocol),
.s_ip_source_ip(tx_ip_source_ip),
.s_ip_dest_ip(tx_ip_dest_ip),
.s_ip_payload_axis_tdata(tx_ip_payload_axis_tdata),
.s_ip_payload_axis_tvalid(tx_ip_payload_axis_tvalid),
.s_ip_payload_axis_tready(tx_ip_payload_axis_tready),
.s_ip_payload_axis_tlast(tx_ip_payload_axis_tlast),
.s_ip_payload_axis_tuser(tx_ip_payload_axis_tuser),
// IP frame output
.m_ip_hdr_valid(rx_ip_hdr_valid),
.m_ip_hdr_ready(rx_ip_hdr_ready),
.m_ip_eth_dest_mac(rx_ip_eth_dest_mac),
.m_ip_eth_src_mac(rx_ip_eth_src_mac),
.m_ip_eth_type(rx_ip_eth_type),
.m_ip_version(rx_ip_version),
.m_ip_ihl(rx_ip_ihl),
.m_ip_dscp(rx_ip_dscp),
.m_ip_ecn(rx_ip_ecn),
.m_ip_length(rx_ip_length),
.m_ip_identification(rx_ip_identification),
.m_ip_flags(rx_ip_flags),
.m_ip_fragment_offset(rx_ip_fragment_offset),
.m_ip_ttl(rx_ip_ttl),
.m_ip_protocol(rx_ip_protocol),
.m_ip_header_checksum(rx_ip_header_checksum),
.m_ip_source_ip(rx_ip_source_ip),
.m_ip_dest_ip(rx_ip_dest_ip),
.m_ip_payload_axis_tdata(rx_ip_payload_axis_tdata),
.m_ip_payload_axis_tvalid(rx_ip_payload_axis_tvalid),
.m_ip_payload_axis_tready(rx_ip_payload_axis_tready),
.m_ip_payload_axis_tlast(rx_ip_payload_axis_tlast),
.m_ip_payload_axis_tuser(rx_ip_payload_axis_tuser),
// UDP frame input
.s_udp_hdr_valid(tx_udp_hdr_valid),
.s_udp_hdr_ready(tx_udp_hdr_ready),
.s_udp_ip_dscp(tx_udp_ip_dscp),
.s_udp_ip_ecn(tx_udp_ip_ecn),
.s_udp_ip_ttl(tx_udp_ip_ttl),
.s_udp_ip_source_ip(tx_udp_ip_source_ip),
.s_udp_ip_dest_ip(tx_udp_ip_dest_ip),
.s_udp_source_port(tx_udp_source_port),
.s_udp_dest_port(tx_udp_dest_port),
.s_udp_length(tx_udp_length),
.s_udp_checksum(tx_udp_checksum),
.s_udp_payload_axis_tdata(tx_udp_payload_axis_tdata),
.s_udp_payload_axis_tvalid(tx_udp_payload_axis_tvalid),
.s_udp_payload_axis_tready(tx_udp_payload_axis_tready),
.s_udp_payload_axis_tlast(tx_udp_payload_axis_tlast),
.s_udp_payload_axis_tuser(tx_udp_payload_axis_tuser),
// UDP frame output
.m_udp_hdr_valid(rx_udp_hdr_valid),
.m_udp_hdr_ready(rx_udp_hdr_ready),
.m_udp_eth_dest_mac(rx_udp_eth_dest_mac),
.m_udp_eth_src_mac(rx_udp_eth_src_mac),
.m_udp_eth_type(rx_udp_eth_type),
.m_udp_ip_version(rx_udp_ip_version),
.m_udp_ip_ihl(rx_udp_ip_ihl),
.m_udp_ip_dscp(rx_udp_ip_dscp),
.m_udp_ip_ecn(rx_udp_ip_ecn),
.m_udp_ip_length(rx_udp_ip_length),
.m_udp_ip_identification(rx_udp_ip_identification),
.m_udp_ip_flags(rx_udp_ip_flags),
.m_udp_ip_fragment_offset(rx_udp_ip_fragment_offset),
.m_udp_ip_ttl(rx_udp_ip_ttl),
.m_udp_ip_protocol(rx_udp_ip_protocol),
.m_udp_ip_header_checksum(rx_udp_ip_header_checksum),
.m_udp_ip_source_ip(rx_udp_ip_source_ip),
.m_udp_ip_dest_ip(rx_udp_ip_dest_ip),
.m_udp_source_port(rx_udp_source_port),
.m_udp_dest_port(rx_udp_dest_port),
.m_udp_length(rx_udp_length),
.m_udp_checksum(rx_udp_checksum),
.m_udp_payload_axis_tdata(rx_udp_payload_axis_tdata),
.m_udp_payload_axis_tvalid(rx_udp_payload_axis_tvalid),
.m_udp_payload_axis_tready(rx_udp_payload_axis_tready),
.m_udp_payload_axis_tlast(rx_udp_payload_axis_tlast),
.m_udp_payload_axis_tuser(rx_udp_payload_axis_tuser),
// Status signals
.ip_rx_busy(),
.ip_tx_busy(),
.udp_rx_busy(),
.udp_tx_busy(),
.ip_rx_error_header_early_termination(),
.ip_rx_error_payload_early_termination(),
.ip_rx_error_invalid_header(),
.ip_rx_error_invalid_checksum(),
.ip_tx_error_payload_early_termination(),
.ip_tx_error_arp_failed(),
.udp_rx_error_header_early_termination(),
.udp_rx_error_payload_early_termination(),
.udp_tx_error_payload_early_termination(),
// Configuration
.local_mac(local_mac),
.local_ip(local_ip),
.gateway_ip(gateway_ip),
.subnet_mask(subnet_mask),
.clear_arp_cache(0)
);
axis_fifo #(
.DEPTH(8192),
.DATA_WIDTH(8),
.KEEP_ENABLE(0),
.ID_ENABLE(0),
.DEST_ENABLE(0),
.USER_ENABLE(1),
.USER_WIDTH(1),
.FRAME_FIFO(0)
)
udp_payload_fifo (
.clk(clk),
.rst(rst),
// AXI input
.s_axis_tdata(rx_fifo_udp_payload_axis_tdata),
.s_axis_tkeep(0),
.s_axis_tvalid(rx_fifo_udp_payload_axis_tvalid),
.s_axis_tready(rx_fifo_udp_payload_axis_tready),
.s_axis_tlast(rx_fifo_udp_payload_axis_tlast),
.s_axis_tid(0),
.s_axis_tdest(0),
.s_axis_tuser(rx_fifo_udp_payload_axis_tuser),
// AXI output
.m_axis_tdata(tx_fifo_udp_payload_axis_tdata),
.m_axis_tkeep(),
.m_axis_tvalid(tx_fifo_udp_payload_axis_tvalid),
.m_axis_tready(tx_fifo_udp_payload_axis_tready),
.m_axis_tlast(tx_fifo_udp_payload_axis_tlast),
.m_axis_tid(),
.m_axis_tdest(),
.m_axis_tuser(tx_fifo_udp_payload_axis_tuser),
// Status
.status_overflow(),
.status_bad_frame(),
.status_good_frame()
);
endmodule |
module MemoryController(
input clk,
input read_a, // Set to 1 to read from RAM
input read_b, // Set to 1 to read from RAM
input write, // Set to 1 to write to RAM
input [21:0] addr, // Address to read / write
input [7:0] din, // Data to write
output reg [7:0] dout_a, // Last read data a
output reg [7:0] dout_b, // Last read data b
output reg busy, // 1 while an operation is in progress
output MemWR, // Write Enable. WRITE when Low.
output [18:0] MemAdr,
inout [7:0] MemDB,
input [13:0] debugaddr,
output [15:0] debugdata
);
reg MemOE;
reg RamWR;
reg sramWR = 1'b1;
reg [7:0] data_to_write;
reg [18:0] MemAdrReg;
wire [7:0] vram_dout;
wire [7:0] ram_dout;
wire [7:0] prgrom_dout;
wire [7:0] chrrom_dout;
wire [7:0] prgram_dout;
wire prgrom_ena = addr[21:18] == 4'b0000;
wire chrrom_ena = addr[21:18] == 4'b1000;
wire vram_ena = addr[21:18] == 4'b1100;
wire ram_ena = addr[21:18] == 4'b1110;
wire prgram_ena = addr[21:18] == 4'b1111;
wire [7:0] memory_dout = prgrom_ena ? prgrom_dout :
chrrom_ena ? chrrom_dout :
vram_ena ? vram_dout :
ram_ena ? ram_dout : prgram_dout;
ram2k vram(clk, vram_ena, RamWR, addr[10:0], data_to_write, vram_dout); // VRAM in BRAM
ram2k ram(clk, ram_ena, RamWR, addr[10:0], data_to_write, ram_dout); // RAM in BRAM
ram8k prg_ram(clk, prgram_ena, RamWR, addr[12:0], data_to_write, prgram_dout); // Cart RAM in BRAM
assign chrrom_dout = MemDB;
assign prgrom_dout = MemDB;
assign MemDB = (!sramWR) ? data_to_write : 8'bz;
assign MemAdr = MemAdrReg;
assign MemWR = sramWR;
reg [1:0] cycles;
reg r_read_a;
always @(posedge clk) begin
// Initiate read or write
if (!busy) begin
if (read_a || read_b || write) begin
if (prgrom_ena) begin
MemAdrReg <= {1'b0, addr[17:0]}; // PRGROM in SRAM
end else if (chrrom_ena) begin
MemAdrReg <= {1'b1, addr[17:0]}; // CHRROM in SRAM
end
RamWR <= write;
sramWR <= !((write == 1) && (prgrom_ena || chrrom_ena));
MemOE <= !(write == 0);
busy <= 1;
data_to_write <= din;
cycles <= 0;
r_read_a <= read_a;
end else begin
MemOE <= 1;
RamWR <= 0;
sramWR <= 1;
busy <= 0;
cycles <= 0;
end
end else begin
if (cycles == 2) begin
// Now we have waited 3x45 = 135ns, latch incoming data on read.
if (!MemOE) begin
if (r_read_a) dout_a <= memory_dout;
else dout_b <= memory_dout;
end
MemOE <= 1; // Deassert Output Enable.
RamWR <= 0; // Deassert Write
sramWR <= 1;
busy <= 0;
cycles <= 0;
end else begin
cycles <= cycles + 1;
end
end
end
endmodule |
module pipeline ( input wire clk,
input wire rst,
output i_read_en,
output [31:0] i_addr,
input [31:0] i_instr_in,
input wb_done_i,
output wire d_read_en,
output wire d_write_en,
output wire [31:0] d_addr,
output wire [31:0] d_write_data,
input wire [31:0] d_data_in );
/* Interconnect wires*/
wire [1:0] pc_source;
wire pc_write;
wire [31:0] jump_addr;
wire [31:0] branch_addr;
wire [31:0] next_i_addr;
wire [31:0] i_fetched; // fetched instrcution from if
wire if_id_write_en; // write enable for IF/ID pipe reg
wire [31:0] wreg_data; // data to write into regfile
wire [4:0] ex_dst_reg;
wire [5:0] ex_opcode;
wire [31:0] ex_reg_data_1; // for jr
wire [4:0] id_rs;
wire [4:0] id_rt;
wire [5:0] id_opcode;
wire ID_EX_wb_reg_write;
wire ID_EX_wb_mem_to_reg;
wire ID_EX_mem_read;
wire ID_EX_mem_write;
wire ID_EX_ex_imm_command;
wire ID_EX_ex_alu_src_b;
wire ID_EX_ex_alu_rslt_src;
wire [1:0] ID_EX_ex_dst_reg_sel;
wire [1:0] ID_EX_ex_alu_op;
wire [31:0] ID_EX_A;
wire [31:0] ID_EX_B;
wire [31:0] ID_EX_sign_extend_offset;
wire [4:0] ID_EX_rt; // target register
wire [4:0] ID_EX_rd; // destination register
wire [4:0] ID_EX_rs; // source register
wire [5:0] ID_EX_opcode;
wire [31:0] EX_MEM_alu_result;
wire [31:0] EX_MEM_B_value;
wire [4:0] EX_MEM_dst_reg;
wire [5:0] EX_MEM_opcode;
wire EX_MEM_mem_read;
wire EX_MEM_mem_write;
wire EX_MEM_wb_reg_write;
wire EX_MEM_wb_mem_to_reg;
wire [4:0] MEM_WB_dst_reg;
wire MEM_WB_reg_write;
wire MEM_WB_mem_to_reg;
wire [31:0] MEM_WB_mem_out;
wire [31:0] MEM_WB_alu_out;
wire id_rt_is_source;
wire hazard_detected;
// forwarding control signals for muxes
wire [1:0] if_rs_forward_control;
wire [1:0] id_rt_forward_control;
wire [1:0] ex_rs_forward_control;
wire [1:0] ex_rt_forward_control;
if_stage ifetch_inst(
.clk ( clk ),
.rst ( rst ),
.pstop_i(pstop),
.if_id_write_en ( if_id_write_en ),
.pc_write ( pc_write ),
.pc_source ( pc_source ),
.i_read_en ( i_read_en ),
.i_addr ( i_addr ),
.i_instr_in ( i_instr_in),
.jump_addr ( jump_addr ),
.branch_addr ( branch_addr ),
.reg_data_1 ( ex_reg_data_1 ),
.IF_ID_instruction ( i_fetched ),
.IF_ID_next_i_addr ( next_i_addr ));
hazard_unit hazard_inst(
.clk ( clk ), // isn't needed for now
.rst ( rst ), // isn't needed for now
.ex_dst_reg ( ex_dst_reg ),
.pstop_o(pstop),
.mem_dst_reg ( EX_MEM_dst_reg ),
.id_rs ( id_rs ),
.id_rt ( id_rt ),
.mem_opcode ( EX_MEM_opcode ),
.ex_opcode ( ex_opcode ),
.id_opcode ( id_opcode ),
.id_rt_is_source ( id_rt_is_source ),
.ex_reg_write ( ID_EX_wb_reg_write ),
.mem_reg_write ( EX_MEM_wb_reg_write ),
.pc_write ( pc_write ),
.if_id_write_en ( if_id_write_en ),
.wb_done_i(wb_done_i),
.hazard_detected_o ( hazard_detected ));
forwarding_unit forwarding_inst(
.ex_mem_reg_write (EX_MEM_wb_reg_write),
.mem_wb_reg_write (MEM_WB_reg_write),
.ex_mem_dst_reg (EX_MEM_dst_reg),
.mem_wb_dst_reg (MEM_WB_dst_reg),
.id_ex_rs (ID_EX_rs),
.id_ex_rt (ID_EX_rt),
.if_id_rs (id_rs),
.if_id_rt (id_rt),
.if_rs_forward_control ( if_rs_forward_control ),
.id_rt_forward_control ( id_rt_forward_control ),
.ex_rs_forward_control ( ex_rs_forward_control ),
.ex_rt_forward_control ( ex_rt_forward_control ));
id_stage idecode_inst(
.clk ( clk ),
.rst ( rst ),
.reg_write ( MEM_WB_reg_write ),
.wreg_addr ( MEM_WB_dst_reg ), // write register number
.wreg_data ( wreg_data ), // data to write into regfile
.instruction ( i_fetched ),
.next_i_addr ( next_i_addr ), // instruction fetched, next instruction address
.pstop_i(pstop),
.rs_fwd_sel ( if_rs_forward_control ), // forwarding control signals
.rt_fwd_sel ( id_rt_forward_control ), // forwarding control signals
.mem_fwd_val ( EX_MEM_alu_result ), // forwarded data values from MEM
.wb_fwd_val ( wreg_data ), // forwarded data values from WB
.hazard ( hazard_detected ),
.id_rs( id_rs ),
.id_rt( id_rt ),
.id_opcode( id_opcode ),
.ID_EX_A ( ID_EX_A ),
.ID_EX_B ( ID_EX_B ),
.ID_EX_rt ( ID_EX_rt ),
.ID_EX_rs ( ID_EX_rs ),
.ID_EX_rd ( ID_EX_rd ),
.ID_EX_opcode ( ID_EX_opcode ),
.ID_EX_sign_extend_offset ( ID_EX_sign_extend_offset ),
.ID_EX_wb_reg_write ( ID_EX_wb_reg_write ),
.ID_EX_wb_mem_to_reg ( ID_EX_wb_mem_to_reg ),
.ID_EX_mem_read ( ID_EX_mem_read ),
.ID_EX_mem_write ( ID_EX_mem_write ),
.ID_EX_ex_imm_command ( ID_EX_ex_imm_command ),
.ID_EX_ex_alu_src_b ( ID_EX_ex_alu_src_b ),
.ID_EX_ex_alu_rslt_src ( ID_EX_ex_alu_rslt_src ),
.ID_EX_ex_dst_reg_sel ( ID_EX_ex_dst_reg_sel ),
.ID_EX_ex_alu_op ( ID_EX_ex_alu_op ),
.branch_addr ( branch_addr ),
.jump_addr ( jump_addr ),
.id_rt_is_source ( id_rt_is_source ),
.if_pc_source ( pc_source ));
ex_stage execute_inst(
.clk ( clk ),
.rst ( rst ),
.wb_reg_write ( ID_EX_wb_reg_write ),
.wb_mem_to_reg ( ID_EX_wb_mem_to_reg ),
.mem_read ( ID_EX_mem_read ),
.pstop_i(pstop),
.mem_write ( ID_EX_mem_write ),
.ex_imm_command ( ID_EX_ex_imm_command ),
.ex_alu_src_b ( ID_EX_ex_alu_src_b ),
.ex_alu_rslt_src ( ID_EX_ex_alu_rslt_src ),
.ex_dst_reg_sel ( ID_EX_ex_dst_reg_sel ),
.ex_alu_op ( ID_EX_ex_alu_op ),
.A ( ID_EX_A ),
.B ( ID_EX_B ),
.sign_extend_offset ( ID_EX_sign_extend_offset ),
.next_i_addr ( next_i_addr ), // execute: PC + 8
.rt ( ID_EX_rt ), // target register
.rd ( ID_EX_rd ), // destination register
.opcode ( ID_EX_opcode ),
.rs_fwd_sel ( ex_rs_forward_control ), // forwarding muxes control
.rt_fwd_sel ( ex_rt_forward_control ), // forwarding muxes control
.mem_fwd_val ( EX_MEM_alu_result ), // forwarding from MEM
.wb_fwd_val ( wreg_data ), // forwarding from WB
.ex_dst_reg ( ex_dst_reg ),
.alu_a_in ( ex_reg_data_1 ),
.ex_opcode ( ex_opcode ),
.EX_MEM_alu_result ( EX_MEM_alu_result ),
.EX_MEM_B_value ( EX_MEM_B_value ),
.EX_MEM_dst_reg ( EX_MEM_dst_reg ),
.EX_MEM_opcode ( EX_MEM_opcode ),
.EX_MEM_mem_read ( EX_MEM_mem_read ),
.EX_MEM_mem_write ( EX_MEM_mem_write ),
.EX_MEM_wb_reg_write ( EX_MEM_wb_reg_write ),
.EX_MEM_wb_mem_to_reg ( EX_MEM_wb_mem_to_reg ));
mem_stage memstage_inst(
.clk ( clk ),
.rst ( rst ),
.mem_read ( EX_MEM_mem_read ),
.mem_write ( EX_MEM_mem_write ),
.alu_result ( EX_MEM_alu_result ),
.B ( EX_MEM_B_value ),
.pstop_i(pstop),
.dst_reg ( EX_MEM_dst_reg ),
.wb_reg_write ( EX_MEM_wb_reg_write ),
.wb_mem_to_reg ( EX_MEM_wb_mem_to_reg ),
.MEM_WB_dst_reg ( MEM_WB_dst_reg ),
.MEM_WB_reg_write ( MEM_WB_reg_write ),
.MEM_WB_mem_to_reg ( MEM_WB_mem_to_reg ),
.MEM_WB_mem_out ( MEM_WB_mem_out ),
.MEM_WB_alu_out ( MEM_WB_alu_out ),
.d_read_en ( d_read_en ),
.d_write_en ( d_write_en ),
.d_addr ( d_addr ),
.d_write_data ( d_write_data ),
.d_data_in ( d_data_in ));
wb_stage wb_inst(
.mem_to_reg ( MEM_WB_mem_to_reg ),
.mem_out ( MEM_WB_mem_out ),
.alu_out ( MEM_WB_alu_out ),
.write_data ( wreg_data ));
endmodule |
module disp_ctrl (
clk,
reset_,
segments_,
digit_enable_,
addr,
cs,
req,
rnw,
wr_data,
rd_data,
rdy);
input clk;
input reset_;
output [6:0] segments_; // 7-segment display segments (active low)
output [3:0] digit_enable_; // Which digit(s) are being controlled
// This circuit provides software control over the 7-segment displays. Each
// display has two control registers, a mode register and a value register.
// They work as follows:
//
// control:
// [0] When 1, value register is a 7-bit value representing the state
// of each display segment. When 0, value register is interpreted
// as a 4-bit binary coded value (i.e., 4'b1000 displays an '8' on
// on the display).
//
// value:
// [6:0] Binary coded value (or raw segment values) to display depedning
// on control register value.
// Local address bus
input [7:0] addr;
input cs;
input req;
inout rnw;
input [7:0] wr_data;
output [7:0] rd_data;
output rdy;
reg [3:0] digit_display_mode;
reg [6:0] digit_0_value;
reg [6:0] digit_1_value;
reg [6:0] digit_2_value;
reg [6:0] digit_3_value;
reg rdy;
reg [7:0] rd_data;
wire [6:0] segments_;
wire [3:0] digit_enable_;
wire [6:0] digit_0_segments;
wire [6:0] digit_1_segments;
wire [6:0] digit_2_segments;
wire [6:0] digit_3_segments;
wire [6:0] digit_0;
wire [6:0] digit_1;
wire [6:0] digit_2;
wire [6:0] digit_3;
wire wr_enable;
wire rd_enable;
// Software addressable registers
parameter REG_DIGIT_0_MODE = 8'd0;
parameter REG_DIGIT_0_VALUE = 8'd1;
parameter REG_DIGIT_1_MODE = 8'd2;
parameter REG_DIGIT_1_VALUE = 8'd3;
parameter REG_DIGIT_2_MODE = 8'd4;
parameter REG_DIGIT_2_VALUE = 8'd5;
parameter REG_DIGIT_3_MODE = 8'd6;
parameter REG_DIGIT_3_VALUE = 8'd7;
assign wr_enable = cs && !rnw && req;
assign rd_enable = cs && rnw && req;
// Digit 0 display value
always@ (posedge clk or negedge reset_)
if (!reset_)
digit_0_value <= 7'h0;
else if (wr_enable && addr == REG_DIGIT_0_VALUE)
digit_0_value <= wr_data[6:0];
// Digit 1 display value
always@ (posedge clk or negedge reset_)
if (!reset_)
digit_1_value <= 7'h0;
else if (wr_enable && addr == REG_DIGIT_1_VALUE)
digit_1_value <= wr_data[6:0];
// Digit 2 display value
always@ (posedge clk or negedge reset_)
if (!reset_)
digit_2_value <= 7'h0;
else if (wr_enable && addr == REG_DIGIT_2_VALUE)
digit_2_value <= wr_data[6:0];
// Digit 3 display value
always@ (posedge clk or negedge reset_)
if (!reset_)
digit_3_value <= 7'h0;
else if (wr_enable && addr == REG_DIGIT_3_VALUE)
digit_3_value <= wr_data[6:0];
// Write digital display mode.
always@ (posedge clk or negedge reset_)
if (!reset_)
digit_display_mode <= 4'h0;
else if (wr_enable && addr == REG_DIGIT_0_MODE)
digit_display_mode[0] <= wr_data[0];
else if (wr_enable && addr == REG_DIGIT_1_MODE)
digit_display_mode[1] <= wr_data[1];
else if (wr_enable && addr == REG_DIGIT_2_MODE)
digit_display_mode[2] <= wr_data[2];
else if (wr_enable && addr == REG_DIGIT_3_MODE)
digit_display_mode[3] <= wr_data[3];
// Register readback
always@ (posedge clk or negedge reset_)
if (!reset_)
rd_data <= 8'h00;
else if (rd_enable)
rd_data <= (addr == REG_DIGIT_0_VALUE) ? {1'h0, digit_0_value} :
(addr == REG_DIGIT_1_VALUE) ? {1'h0, digit_1_value} :
(addr == REG_DIGIT_2_VALUE) ? {1'h0, digit_2_value} :
(addr == REG_DIGIT_3_VALUE) ? {1'h0, digit_3_value} :
(addr == REG_DIGIT_0_MODE) ? {7'h0, digit_display_mode[0]} :
(addr == REG_DIGIT_1_MODE) ? {7'h0, digit_display_mode[1]} :
(addr == REG_DIGIT_2_MODE) ? {7'h0, digit_display_mode[2]} :
(addr == REG_DIGIT_3_MODE) ? {7'h0, digit_display_mode[3]} :
8'h00;
// Readback ready generation
always@ (posedge clk or negedge reset_)
if (!reset_)
rdy <= 1'b0;
else
rdy <= req;
// Binary coded decimal to 7-segment display coders
bcdcoder digit0_coder (
.segment(digit_0_segments),
.bcd(digit_0_value[3:0])
);
bcdcoder digit1_coder (
.segment(digit_1_segments),
.bcd(digit_1_value[3:0])
);
bcdcoder digit2_coder (
.segment(digit_2_segments),
.bcd(digit_2_value[3:0])
);
bcdcoder digit3_coder (
.segment(digit_3_segments),
.bcd(digit_3_value[3:0])
);
// When display mode is 1, we interpret digit value as raw segment enables;
// otherwise, assume digit value is BCD (display a number between 0..9)
assign digit_0 = digit_display_mode[0] ? digit_0_value[6:0] : digit_0_segments;
assign digit_1 = digit_display_mode[1] ? digit_1_value[6:0] : digit_1_segments;
assign digit_2 = digit_display_mode[2] ? digit_2_value[6:0] : digit_2_segments;
assign digit_3 = digit_display_mode[3] ? digit_3_value[6:0] : digit_3_segments;
// Display driver instantiation
displaydriver displaydriver (
.clk(clk),
.reset_(reset_),
.digit_0(digit_0),
.digit_1(digit_1),
.digit_2(digit_2),
.digit_3(digit_3),
.segment_(segments_),
.digit_enable_(digit_enable_)
);
endmodule |
module hls_contrast_stredEe_DSP48_2(
input [8 - 1:0] in0,
input [23 - 1:0] in1,
input [29 - 1:0] in2,
output [30 - 1:0] dout);
wire signed [25 - 1:0] a;
wire signed [18 - 1:0] b;
wire signed [48 - 1:0] c;
wire signed [43 - 1:0] m;
wire signed [48 - 1:0] p;
assign a = $unsigned(in1);
assign b = $unsigned(in0);
assign c = $unsigned(in2);
assign m = a * b;
assign p = m + c;
assign dout = p;
endmodule |
module hls_contrast_stredEe(
din0,
din1,
din2,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter din2_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
input[din2_WIDTH - 1:0] din2;
output[dout_WIDTH - 1:0] dout;
hls_contrast_stredEe_DSP48_2 hls_contrast_stredEe_DSP48_2_U(
.in0( din0 ),
.in1( din1 ),
.in2( din2 ),
.dout( dout ));
endmodule |
module sky130_fd_sc_hvl__o22ai_1 (
Y ,
A1 ,
A2 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hvl__o22ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule |
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