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module sky130_fd_sc_ls__clkdlyinv3sd3_1 (
Y ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__clkdlyinv3sd3 base (
.Y(Y),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule |
module sky130_fd_sc_ls__clkdlyinv3sd3_1 (
Y,
A
);
output Y;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__clkdlyinv3sd3 base (
.Y(Y),
.A(A)
);
endmodule |
module sky130_fd_sc_hdll__einvp (
Z ,
A ,
TE
);
// Module ports
output Z ;
input A ;
input TE;
// Name Output Other arguments
notif1 notif10 (Z , A, TE );
endmodule |
module sky130_fd_sc_hdll__sdfrbp (
Q ,
Q_N ,
CLK ,
D ,
SCD ,
SCE ,
RESET_B
);
// Module ports
output Q ;
output Q_N ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input RESET_B;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire buf_Q ;
wire RESET ;
wire mux_out ;
reg notifier ;
wire D_delayed ;
wire SCD_delayed ;
wire SCE_delayed ;
wire RESET_B_delayed;
wire CLK_delayed ;
wire awake ;
wire cond0 ;
wire cond1 ;
wire cond2 ;
wire cond3 ;
wire cond4 ;
// Name Output Other arguments
not not0 (RESET , RESET_B_delayed );
sky130_fd_sc_hdll__udp_mux_2to1 mux_2to10 (mux_out, D_delayed, SCD_delayed, SCE_delayed );
sky130_fd_sc_hdll__udp_dff$PR_pp$PG$N dff0 (buf_Q , mux_out, CLK_delayed, RESET, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond0 = ( ( RESET_B_delayed === 1'b1 ) && awake );
assign cond1 = ( ( SCE_delayed === 1'b0 ) && cond0 );
assign cond2 = ( ( SCE_delayed === 1'b1 ) && cond0 );
assign cond3 = ( ( D_delayed !== SCD_delayed ) && cond0 );
assign cond4 = ( ( RESET_B === 1'b1 ) && awake );
buf buf0 (Q , buf_Q );
not not1 (Q_N , buf_Q );
endmodule |
module Mflipflop (out, in, clock, enable_l);
output out;
input in;
input clock;
input enable_l; // must be low to allow master to open
wire logic_0 = 1'b0 ;
wire logic_1 = 1'b1 ;
ASFFHA dff (.H(enable_l),.D(in),.Q(out),.CK(clock),.SM(logic_0),.SI(logic_0));
endmodule |
module MflipflopR (out, in, clock, enable_l,reset);
output out;
input in;
input clock;
input enable_l; // must be low to allow master to open
input reset;
wire logic_0 = 1'b0 ;
wire logic_1 = 1'b1 ;
wire resetn = ~reset ;
ASFFRHA dff (.H(enable_l),.D(in),.Q(out),.CK(clock),.SM(logic_0),.SI(logic_0),.R(resetn));
endmodule |
module Mflipflop_srh (out, in, scanen,sin, enable_l, reset_l, clock);
output out;
input in;
input scanen, sin ;
input clock;
input enable_l; // must be low to allow master to open
input reset_l;
ASFFRHA dff (
.Q(out),
.D(in),
.SM(scanen),
.SI(sin),
.H(enable_l),
.R(reset_l),
.CK(clock)
);
endmodule |
module Mflipflop_ar(out, in, async_reset_l, clock) ;
output out ;
input in ;
input async_reset_l ;
input clock ;
JSRFFA dff(.D(in), .CK(clock), .CL(async_reset_l), .PR(1'b1), .Q(out)) ;
endmodule |
module Mflipflop_sh (out, in, scanen,sin, enable_l, clock);
output out;
input in;
input scanen, sin ;
input clock;
input enable_l; // must be low to allow master to open
ASFFHA dff (
.Q(out),
.D(in),
.SM(scanen),
.SI(sin),
.H(enable_l),
.CK(clock)
);
endmodule |
module Mflipflop_rh (out, in, enable_l, reset_l, clock);
output out;
input in;
input clock;
input enable_l; // must be low to allow master to open
input reset_l;
ADFFRHA dff (
.Q(out),
.D(in),
.H(enable_l),
.R(reset_l),
.CK(clock)
);
endmodule |
module Mflipflop_sr (out, in, scanen, sin, reset_l, clock);
output out;
input in;
input clock;
input reset_l;
input scanen,sin ;
ASFFRA dff (
.Q(out),
.D(in),
.R(reset_l),
.SM(scanen),
.SI(sin),
.CK(clock)
);
endmodule |
module Mflipflop_s (out, in, scanen, sin, clock);
output out ;
input in ;
input clock ;
input sin ;
input scanen ;
ASFFA dff (
.Q(out),
.D(in),
.SM(scanen),
.SI(sin),
.CK(clock)
);
endmodule |
module Mflipflop_r (out, in, reset_l, clock);
output out ;
input in ;
input clock ;
input reset_l ; // must be low to allow master to open
ADFFRA dff (
.Q(out),
.D(in),
.R(reset_l),
.CK(clock)
);
endmodule |
module Mflipflop_h (out, in, enable_l, clock);
output out ;
input in ;
input clock ;
input enable_l ; // must be low to allow master to open
ASFFA dff (
.Q(out),
.D(in),
.SM(enable_l), // use the scan mux to implement hold function
.SI(out),
.CK(clock)
);
endmodule |
module Mflipflop_noop (out, in, clock);
output out ;
input in ;
input clock ;
JDFFA dff (
.Q(out),
.D(in),
.CK(clock)
);
endmodule |
module sky130_fd_sc_ms__or4bb (
X ,
A ,
B ,
C_N,
D_N
);
// Module ports
output X ;
input A ;
input B ;
input C_N;
input D_N;
// Local signals
wire nand0_out;
wire or0_out_X;
// Name Output Other arguments
nand nand0 (nand0_out, D_N, C_N );
or or0 (or0_out_X, B, A, nand0_out);
buf buf0 (X , or0_out_X );
endmodule |
module PATTERN(
input [2:0] out,
input out_valid,
input ready,
output reg [2:0] in,
output reg [2:0] mode,
output reg in_valid,
output reg clk,
output reg rst_n
);
reg [2:0] pixel[0:8];
reg [2:0] mode_t;
parameter CYCLE = `CYCLE_PERIOD;
parameter PATTERN_NUM = 5000;
integer latency, total_latency;
integer round;
integer temp, temp_M[0:8];
integer pattern_num, i, j;
initial begin
total_latency = 0;
end
initial begin
clk = 0;
#10;
forever #CYCLE clk = ~clk;
end
initial begin
in <= 'dx;
mode <= 'dx;
in_valid <= 'bx;
rst_n <= 1'b1;
#2;
rst_n <= 1'b0;
#4;
rst_n <= 1'b1;
check_rst;
in_valid <= 'b0;
@(negedge clk);
for(pattern_num=0;pattern_num<PATTERN_NUM;pattern_num=pattern_num+1) begin
wait_rdy;
round = {$random()}%10 + 1;
for(i=0;i<9;i=i+1) begin
pixel[i] = $random();
in_valid <= 1'b1;
in <= pixel[i];
check_rst;
@(negedge clk);
end
in <= 'dx;
in_valid = 1'b0;
for(i=0;i<round;i=i+1) begin
wait_rdy;
mode_t = {$random()}%7+1;
case(mode_t)
1: proc_mode1;
2: proc_mode2;
3: proc_mode3;
4: proc_mode4;
5: proc_mode5;
6: proc_mode6;
7: proc_mode7;
endcase
mode <= mode_t;
in_valid <= 1'b1;
check_rst;
@(negedge clk);
mode <= 'dx;
in_valid <= 1'b0;
end
wait_rdy;
mode <= 0;
in_valid <= 1'b1;
@(negedge clk);
mode <= 'dx;
in_valid <= 1'b0;
wait_out;
for(i=0;i<9;i=i+1) begin
if(out !== pixel[i]) begin
$display("");
$display("=================================================");
$display(" Failed!! PATTERN %4d is wrong! ", pattern_num+1);
$display(" ans is %d your ans is %d ", pixel[i],out);
$display("=================================================");
$display("");
repeat(9)@(negedge clk);
$finish;
end
@(negedge clk);
end
$display("");
$display(" Pass pattern %3d ", pattern_num+1);
@(negedge clk);
end
@(negedge clk);
$display ("--------------------------------------------------------------------");
$display (" Congratulations ! ");
$display (" You have passed all patterns ! ");
$display (" Your total latency is %6d ! ", total_latency);
$display ("--------------------------------------------------------------------");
@(negedge clk);
$finish;
end
task check_rst;
begin
if(out !== 'd0 || out_valid !== 1'b0) begin
$display("");
$display("=================================================");
$display(" Output should be reset !!!! ");
$display("=================================================");
$display("");
@(negedge clk);
$finish;
end
end
endtask
task wait_rdy;
begin
latency = 0;
while(!(ready === 1'b1)) begin
if(latency > 12) begin
$display("");
$display("=================================================");
$display(" Latency too more !!!! ");
$display("=================================================");
$display("");
@(negedge clk);
$finish;
end
latency = latency + 1;
total_latency = total_latency + 1;
@(negedge clk);
end
end
endtask
task wait_out;
begin
latency = 0;
while(!(out_valid === 1'b1)) begin
if(latency > 12) begin
$display("");
$display("=================================================");
$display(" Latency too more !!!! ");
$display("=================================================");
$display("");
@(negedge clk);
$finish;
end
latency = latency + 1;
total_latency = total_latency + 1;
@(negedge clk);
end
end
endtask
task proc_mode1;
begin
for(j=0;j<9;j=j+3) begin
temp = pixel[j];
pixel[j] = pixel[j+2];
pixel[j+2] = temp;
end
end
endtask
task proc_mode2;
begin
for(j=0;j<3;j=j+1) begin
temp = pixel[j];
pixel[j] = pixel[j+6];
pixel[j+6] = temp;
end
end
endtask
task proc_mode3;
begin
temp_M[0] = pixel[2];
temp_M[1] = pixel[5];
temp_M[2] = pixel[8];
temp_M[3] = pixel[1];
temp_M[4] = pixel[4];
temp_M[5] = pixel[7];
temp_M[6] = pixel[0];
temp_M[7] = pixel[3];
temp_M[8] = pixel[6];
for(j=0;j<9;j=j+1) begin
pixel[j] = temp_M[j];
end
end
endtask
task proc_mode4;
begin
temp_M[0] = pixel[6];
temp_M[1] = pixel[3];
temp_M[2] = pixel[0];
temp_M[3] = pixel[7];
temp_M[4] = pixel[4];
temp_M[5] = pixel[1];
temp_M[6] = pixel[8];
temp_M[7] = pixel[5];
temp_M[8] = pixel[2];
for(j=0;j<9;j=j+1) begin
pixel[j] = temp_M[j];
end
end
endtask
task proc_mode5;
begin
for(j=0;j<9;j=j+3) begin
if(pixel[j] < 'd7)
pixel[j] = pixel[j] + 1;
end
end
endtask
task proc_mode6;
begin
for(j=1;j<9;j=j+3) begin
if(pixel[j] < 'd7)
pixel[j] = pixel[j] + 1;
end
end
endtask
task proc_mode7;
begin
for(j=2;j<9;j=j+3) begin
if(pixel[j] < 'd7)
pixel[j] = pixel[j] + 1;
end
end
endtask
endmodule |
module top();
// Inputs are registered
reg D;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Q;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 D = 1'b0;
#40 VGND = 1'b0;
#60 VNB = 1'b0;
#80 VPB = 1'b0;
#100 VPWR = 1'b0;
#120 D = 1'b1;
#140 VGND = 1'b1;
#160 VNB = 1'b1;
#180 VPB = 1'b1;
#200 VPWR = 1'b1;
#220 D = 1'b0;
#240 VGND = 1'b0;
#260 VNB = 1'b0;
#280 VPB = 1'b0;
#300 VPWR = 1'b0;
#320 VPWR = 1'b1;
#340 VPB = 1'b1;
#360 VNB = 1'b1;
#380 VGND = 1'b1;
#400 D = 1'b1;
#420 VPWR = 1'bx;
#440 VPB = 1'bx;
#460 VNB = 1'bx;
#480 VGND = 1'bx;
#500 D = 1'bx;
end
// Create a clock
reg GATE_N;
initial
begin
GATE_N = 1'b0;
end
always
begin
#5 GATE_N = ~GATE_N;
end
sky130_fd_sc_hd__dlxtn dut (.D(D), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Q(Q), .GATE_N(GATE_N));
endmodule |
module PmodJSTK2
(AXI_LITE_GPIO_araddr,
AXI_LITE_GPIO_arready,
AXI_LITE_GPIO_arvalid,
AXI_LITE_GPIO_awaddr,
AXI_LITE_GPIO_awready,
AXI_LITE_GPIO_awvalid,
AXI_LITE_GPIO_bready,
AXI_LITE_GPIO_bresp,
AXI_LITE_GPIO_bvalid,
AXI_LITE_GPIO_rdata,
AXI_LITE_GPIO_rready,
AXI_LITE_GPIO_rresp,
AXI_LITE_GPIO_rvalid,
AXI_LITE_GPIO_wdata,
AXI_LITE_GPIO_wready,
AXI_LITE_GPIO_wstrb,
AXI_LITE_GPIO_wvalid,
AXI_LITE_SPI_araddr,
AXI_LITE_SPI_arready,
AXI_LITE_SPI_arvalid,
AXI_LITE_SPI_awaddr,
AXI_LITE_SPI_awready,
AXI_LITE_SPI_awvalid,
AXI_LITE_SPI_bready,
AXI_LITE_SPI_bresp,
AXI_LITE_SPI_bvalid,
AXI_LITE_SPI_rdata,
AXI_LITE_SPI_rready,
AXI_LITE_SPI_rresp,
AXI_LITE_SPI_rvalid,
AXI_LITE_SPI_wdata,
AXI_LITE_SPI_wready,
AXI_LITE_SPI_wstrb,
AXI_LITE_SPI_wvalid,
Pmod_out_pin10_i,
Pmod_out_pin10_o,
Pmod_out_pin10_t,
Pmod_out_pin1_i,
Pmod_out_pin1_o,
Pmod_out_pin1_t,
Pmod_out_pin2_i,
Pmod_out_pin2_o,
Pmod_out_pin2_t,
Pmod_out_pin3_i,
Pmod_out_pin3_o,
Pmod_out_pin3_t,
Pmod_out_pin4_i,
Pmod_out_pin4_o,
Pmod_out_pin4_t,
Pmod_out_pin7_i,
Pmod_out_pin7_o,
Pmod_out_pin7_t,
Pmod_out_pin8_i,
Pmod_out_pin8_o,
Pmod_out_pin8_t,
Pmod_out_pin9_i,
Pmod_out_pin9_o,
Pmod_out_pin9_t,
ext_spi_clk,
s_axi_aclk,
s_axi_aresetn);
input [8:0]AXI_LITE_GPIO_araddr;
output AXI_LITE_GPIO_arready;
input AXI_LITE_GPIO_arvalid;
input [8:0]AXI_LITE_GPIO_awaddr;
output AXI_LITE_GPIO_awready;
input AXI_LITE_GPIO_awvalid;
input AXI_LITE_GPIO_bready;
output [1:0]AXI_LITE_GPIO_bresp;
output AXI_LITE_GPIO_bvalid;
output [31:0]AXI_LITE_GPIO_rdata;
input AXI_LITE_GPIO_rready;
output [1:0]AXI_LITE_GPIO_rresp;
output AXI_LITE_GPIO_rvalid;
input [31:0]AXI_LITE_GPIO_wdata;
output AXI_LITE_GPIO_wready;
input [3:0]AXI_LITE_GPIO_wstrb;
input AXI_LITE_GPIO_wvalid;
input [6:0]AXI_LITE_SPI_araddr;
output AXI_LITE_SPI_arready;
input AXI_LITE_SPI_arvalid;
input [6:0]AXI_LITE_SPI_awaddr;
output AXI_LITE_SPI_awready;
input AXI_LITE_SPI_awvalid;
input AXI_LITE_SPI_bready;
output [1:0]AXI_LITE_SPI_bresp;
output AXI_LITE_SPI_bvalid;
output [31:0]AXI_LITE_SPI_rdata;
input AXI_LITE_SPI_rready;
output [1:0]AXI_LITE_SPI_rresp;
output AXI_LITE_SPI_rvalid;
input [31:0]AXI_LITE_SPI_wdata;
output AXI_LITE_SPI_wready;
input [3:0]AXI_LITE_SPI_wstrb;
input AXI_LITE_SPI_wvalid;
input Pmod_out_pin10_i;
output Pmod_out_pin10_o;
output Pmod_out_pin10_t;
input Pmod_out_pin1_i;
output Pmod_out_pin1_o;
output Pmod_out_pin1_t;
input Pmod_out_pin2_i;
output Pmod_out_pin2_o;
output Pmod_out_pin2_t;
input Pmod_out_pin3_i;
output Pmod_out_pin3_o;
output Pmod_out_pin3_t;
input Pmod_out_pin4_i;
output Pmod_out_pin4_o;
output Pmod_out_pin4_t;
input Pmod_out_pin7_i;
output Pmod_out_pin7_o;
output Pmod_out_pin7_t;
input Pmod_out_pin8_i;
output Pmod_out_pin8_o;
output Pmod_out_pin8_t;
input Pmod_out_pin9_i;
output Pmod_out_pin9_o;
output Pmod_out_pin9_t;
input ext_spi_clk;
input s_axi_aclk;
input s_axi_aresetn;
wire [6:0]AXI_LITE_1_ARADDR;
wire AXI_LITE_1_ARREADY;
wire AXI_LITE_1_ARVALID;
wire [6:0]AXI_LITE_1_AWADDR;
wire AXI_LITE_1_AWREADY;
wire AXI_LITE_1_AWVALID;
wire AXI_LITE_1_BREADY;
wire [1:0]AXI_LITE_1_BRESP;
wire AXI_LITE_1_BVALID;
wire [31:0]AXI_LITE_1_RDATA;
wire AXI_LITE_1_RREADY;
wire [1:0]AXI_LITE_1_RRESP;
wire AXI_LITE_1_RVALID;
wire [31:0]AXI_LITE_1_WDATA;
wire AXI_LITE_1_WREADY;
wire [3:0]AXI_LITE_1_WSTRB;
wire AXI_LITE_1_WVALID;
wire [8:0]S_AXI_1_ARADDR;
wire S_AXI_1_ARREADY;
wire S_AXI_1_ARVALID;
wire [8:0]S_AXI_1_AWADDR;
wire S_AXI_1_AWREADY;
wire S_AXI_1_AWVALID;
wire S_AXI_1_BREADY;
wire [1:0]S_AXI_1_BRESP;
wire S_AXI_1_BVALID;
wire [31:0]S_AXI_1_RDATA;
wire S_AXI_1_RREADY;
wire [1:0]S_AXI_1_RRESP;
wire S_AXI_1_RVALID;
wire [31:0]S_AXI_1_WDATA;
wire S_AXI_1_WREADY;
wire [3:0]S_AXI_1_WSTRB;
wire S_AXI_1_WVALID;
wire [0:0]axi_gpio_0_gpio_io_o;
wire [0:0]axi_gpio_0_gpio_io_t;
wire axi_quad_spi_0_io0_o;
wire axi_quad_spi_0_io0_t;
wire axi_quad_spi_0_io1_o;
wire axi_quad_spi_0_io1_t;
wire axi_quad_spi_0_sck_o;
wire axi_quad_spi_0_sck_t;
wire ext_spi_clk_1;
wire pmod_bridge_0_Pmod_out_PIN10_I;
wire pmod_bridge_0_Pmod_out_PIN10_O;
wire pmod_bridge_0_Pmod_out_PIN10_T;
wire pmod_bridge_0_Pmod_out_PIN1_I;
wire pmod_bridge_0_Pmod_out_PIN1_O;
wire pmod_bridge_0_Pmod_out_PIN1_T;
wire pmod_bridge_0_Pmod_out_PIN2_I;
wire pmod_bridge_0_Pmod_out_PIN2_O;
wire pmod_bridge_0_Pmod_out_PIN2_T;
wire pmod_bridge_0_Pmod_out_PIN3_I;
wire pmod_bridge_0_Pmod_out_PIN3_O;
wire pmod_bridge_0_Pmod_out_PIN3_T;
wire pmod_bridge_0_Pmod_out_PIN4_I;
wire pmod_bridge_0_Pmod_out_PIN4_O;
wire pmod_bridge_0_Pmod_out_PIN4_T;
wire pmod_bridge_0_Pmod_out_PIN7_I;
wire pmod_bridge_0_Pmod_out_PIN7_O;
wire pmod_bridge_0_Pmod_out_PIN7_T;
wire pmod_bridge_0_Pmod_out_PIN8_I;
wire pmod_bridge_0_Pmod_out_PIN8_O;
wire pmod_bridge_0_Pmod_out_PIN8_T;
wire pmod_bridge_0_Pmod_out_PIN9_I;
wire pmod_bridge_0_Pmod_out_PIN9_O;
wire pmod_bridge_0_Pmod_out_PIN9_T;
wire pmod_bridge_0_in0_I;
wire pmod_bridge_0_in1_I;
wire pmod_bridge_0_in2_I;
wire pmod_bridge_0_in3_I;
wire s_axi_aclk_1;
wire s_axi_aresetn_1;
assign AXI_LITE_1_ARADDR = AXI_LITE_SPI_araddr[6:0];
assign AXI_LITE_1_ARVALID = AXI_LITE_SPI_arvalid;
assign AXI_LITE_1_AWADDR = AXI_LITE_SPI_awaddr[6:0];
assign AXI_LITE_1_AWVALID = AXI_LITE_SPI_awvalid;
assign AXI_LITE_1_BREADY = AXI_LITE_SPI_bready;
assign AXI_LITE_1_RREADY = AXI_LITE_SPI_rready;
assign AXI_LITE_1_WDATA = AXI_LITE_SPI_wdata[31:0];
assign AXI_LITE_1_WSTRB = AXI_LITE_SPI_wstrb[3:0];
assign AXI_LITE_1_WVALID = AXI_LITE_SPI_wvalid;
assign AXI_LITE_GPIO_arready = S_AXI_1_ARREADY;
assign AXI_LITE_GPIO_awready = S_AXI_1_AWREADY;
assign AXI_LITE_GPIO_bresp[1:0] = S_AXI_1_BRESP;
assign AXI_LITE_GPIO_bvalid = S_AXI_1_BVALID;
assign AXI_LITE_GPIO_rdata[31:0] = S_AXI_1_RDATA;
assign AXI_LITE_GPIO_rresp[1:0] = S_AXI_1_RRESP;
assign AXI_LITE_GPIO_rvalid = S_AXI_1_RVALID;
assign AXI_LITE_GPIO_wready = S_AXI_1_WREADY;
assign AXI_LITE_SPI_arready = AXI_LITE_1_ARREADY;
assign AXI_LITE_SPI_awready = AXI_LITE_1_AWREADY;
assign AXI_LITE_SPI_bresp[1:0] = AXI_LITE_1_BRESP;
assign AXI_LITE_SPI_bvalid = AXI_LITE_1_BVALID;
assign AXI_LITE_SPI_rdata[31:0] = AXI_LITE_1_RDATA;
assign AXI_LITE_SPI_rresp[1:0] = AXI_LITE_1_RRESP;
assign AXI_LITE_SPI_rvalid = AXI_LITE_1_RVALID;
assign AXI_LITE_SPI_wready = AXI_LITE_1_WREADY;
assign Pmod_out_pin10_o = pmod_bridge_0_Pmod_out_PIN10_O;
assign Pmod_out_pin10_t = pmod_bridge_0_Pmod_out_PIN10_T;
assign Pmod_out_pin1_o = pmod_bridge_0_Pmod_out_PIN1_O;
assign Pmod_out_pin1_t = pmod_bridge_0_Pmod_out_PIN1_T;
assign Pmod_out_pin2_o = pmod_bridge_0_Pmod_out_PIN2_O;
assign Pmod_out_pin2_t = pmod_bridge_0_Pmod_out_PIN2_T;
assign Pmod_out_pin3_o = pmod_bridge_0_Pmod_out_PIN3_O;
assign Pmod_out_pin3_t = pmod_bridge_0_Pmod_out_PIN3_T;
assign Pmod_out_pin4_o = pmod_bridge_0_Pmod_out_PIN4_O;
assign Pmod_out_pin4_t = pmod_bridge_0_Pmod_out_PIN4_T;
assign Pmod_out_pin7_o = pmod_bridge_0_Pmod_out_PIN7_O;
assign Pmod_out_pin7_t = pmod_bridge_0_Pmod_out_PIN7_T;
assign Pmod_out_pin8_o = pmod_bridge_0_Pmod_out_PIN8_O;
assign Pmod_out_pin8_t = pmod_bridge_0_Pmod_out_PIN8_T;
assign Pmod_out_pin9_o = pmod_bridge_0_Pmod_out_PIN9_O;
assign Pmod_out_pin9_t = pmod_bridge_0_Pmod_out_PIN9_T;
assign S_AXI_1_ARADDR = AXI_LITE_GPIO_araddr[8:0];
assign S_AXI_1_ARVALID = AXI_LITE_GPIO_arvalid;
assign S_AXI_1_AWADDR = AXI_LITE_GPIO_awaddr[8:0];
assign S_AXI_1_AWVALID = AXI_LITE_GPIO_awvalid;
assign S_AXI_1_BREADY = AXI_LITE_GPIO_bready;
assign S_AXI_1_RREADY = AXI_LITE_GPIO_rready;
assign S_AXI_1_WDATA = AXI_LITE_GPIO_wdata[31:0];
assign S_AXI_1_WSTRB = AXI_LITE_GPIO_wstrb[3:0];
assign S_AXI_1_WVALID = AXI_LITE_GPIO_wvalid;
assign ext_spi_clk_1 = ext_spi_clk;
assign pmod_bridge_0_Pmod_out_PIN10_I = Pmod_out_pin10_i;
assign pmod_bridge_0_Pmod_out_PIN1_I = Pmod_out_pin1_i;
assign pmod_bridge_0_Pmod_out_PIN2_I = Pmod_out_pin2_i;
assign pmod_bridge_0_Pmod_out_PIN3_I = Pmod_out_pin3_i;
assign pmod_bridge_0_Pmod_out_PIN4_I = Pmod_out_pin4_i;
assign pmod_bridge_0_Pmod_out_PIN7_I = Pmod_out_pin7_i;
assign pmod_bridge_0_Pmod_out_PIN8_I = Pmod_out_pin8_i;
assign pmod_bridge_0_Pmod_out_PIN9_I = Pmod_out_pin9_i;
assign s_axi_aclk_1 = s_axi_aclk;
assign s_axi_aresetn_1 = s_axi_aresetn;
PmodJSTK2_axi_gpio_0_0 axi_gpio_0
(.gpio_io_i(pmod_bridge_0_in0_I),
.gpio_io_o(axi_gpio_0_gpio_io_o),
.gpio_io_t(axi_gpio_0_gpio_io_t),
.s_axi_aclk(s_axi_aclk_1),
.s_axi_araddr(S_AXI_1_ARADDR),
.s_axi_aresetn(s_axi_aresetn_1),
.s_axi_arready(S_AXI_1_ARREADY),
.s_axi_arvalid(S_AXI_1_ARVALID),
.s_axi_awaddr(S_AXI_1_AWADDR),
.s_axi_awready(S_AXI_1_AWREADY),
.s_axi_awvalid(S_AXI_1_AWVALID),
.s_axi_bready(S_AXI_1_BREADY),
.s_axi_bresp(S_AXI_1_BRESP),
.s_axi_bvalid(S_AXI_1_BVALID),
.s_axi_rdata(S_AXI_1_RDATA),
.s_axi_rready(S_AXI_1_RREADY),
.s_axi_rresp(S_AXI_1_RRESP),
.s_axi_rvalid(S_AXI_1_RVALID),
.s_axi_wdata(S_AXI_1_WDATA),
.s_axi_wready(S_AXI_1_WREADY),
.s_axi_wstrb(S_AXI_1_WSTRB),
.s_axi_wvalid(S_AXI_1_WVALID));
PmodJSTK2_axi_quad_spi_0_0 axi_quad_spi_0
(.ext_spi_clk(ext_spi_clk_1),
.io0_i(pmod_bridge_0_in1_I),
.io0_o(axi_quad_spi_0_io0_o),
.io0_t(axi_quad_spi_0_io0_t),
.io1_i(pmod_bridge_0_in2_I),
.io1_o(axi_quad_spi_0_io1_o),
.io1_t(axi_quad_spi_0_io1_t),
.s_axi_aclk(s_axi_aclk_1),
.s_axi_araddr(AXI_LITE_1_ARADDR),
.s_axi_aresetn(s_axi_aresetn_1),
.s_axi_arready(AXI_LITE_1_ARREADY),
.s_axi_arvalid(AXI_LITE_1_ARVALID),
.s_axi_awaddr(AXI_LITE_1_AWADDR),
.s_axi_awready(AXI_LITE_1_AWREADY),
.s_axi_awvalid(AXI_LITE_1_AWVALID),
.s_axi_bready(AXI_LITE_1_BREADY),
.s_axi_bresp(AXI_LITE_1_BRESP),
.s_axi_bvalid(AXI_LITE_1_BVALID),
.s_axi_rdata(AXI_LITE_1_RDATA),
.s_axi_rready(AXI_LITE_1_RREADY),
.s_axi_rresp(AXI_LITE_1_RRESP),
.s_axi_rvalid(AXI_LITE_1_RVALID),
.s_axi_wdata(AXI_LITE_1_WDATA),
.s_axi_wready(AXI_LITE_1_WREADY),
.s_axi_wstrb(AXI_LITE_1_WSTRB),
.s_axi_wvalid(AXI_LITE_1_WVALID),
.sck_i(pmod_bridge_0_in3_I),
.sck_o(axi_quad_spi_0_sck_o),
.sck_t(axi_quad_spi_0_sck_t),
.ss_i(1'b0));
PmodJSTK2_pmod_bridge_0_0 pmod_bridge_0
(.in0_I(pmod_bridge_0_in0_I),
.in0_O(axi_gpio_0_gpio_io_o),
.in0_T(axi_gpio_0_gpio_io_t),
.in1_I(pmod_bridge_0_in1_I),
.in1_O(axi_quad_spi_0_io0_o),
.in1_T(axi_quad_spi_0_io0_t),
.in2_I(pmod_bridge_0_in2_I),
.in2_O(axi_quad_spi_0_io1_o),
.in2_T(axi_quad_spi_0_io1_t),
.in3_I(pmod_bridge_0_in3_I),
.in3_O(axi_quad_spi_0_sck_o),
.in3_T(axi_quad_spi_0_sck_t),
.out0_I(pmod_bridge_0_Pmod_out_PIN1_I),
.out0_O(pmod_bridge_0_Pmod_out_PIN1_O),
.out0_T(pmod_bridge_0_Pmod_out_PIN1_T),
.out1_I(pmod_bridge_0_Pmod_out_PIN2_I),
.out1_O(pmod_bridge_0_Pmod_out_PIN2_O),
.out1_T(pmod_bridge_0_Pmod_out_PIN2_T),
.out2_I(pmod_bridge_0_Pmod_out_PIN3_I),
.out2_O(pmod_bridge_0_Pmod_out_PIN3_O),
.out2_T(pmod_bridge_0_Pmod_out_PIN3_T),
.out3_I(pmod_bridge_0_Pmod_out_PIN4_I),
.out3_O(pmod_bridge_0_Pmod_out_PIN4_O),
.out3_T(pmod_bridge_0_Pmod_out_PIN4_T),
.out4_I(pmod_bridge_0_Pmod_out_PIN7_I),
.out4_O(pmod_bridge_0_Pmod_out_PIN7_O),
.out4_T(pmod_bridge_0_Pmod_out_PIN7_T),
.out5_I(pmod_bridge_0_Pmod_out_PIN8_I),
.out5_O(pmod_bridge_0_Pmod_out_PIN8_O),
.out5_T(pmod_bridge_0_Pmod_out_PIN8_T),
.out6_I(pmod_bridge_0_Pmod_out_PIN9_I),
.out6_O(pmod_bridge_0_Pmod_out_PIN9_O),
.out6_T(pmod_bridge_0_Pmod_out_PIN9_T),
.out7_I(pmod_bridge_0_Pmod_out_PIN10_I),
.out7_O(pmod_bridge_0_Pmod_out_PIN10_O),
.out7_T(pmod_bridge_0_Pmod_out_PIN10_T));
endmodule |
module tb_coretest_test_core();
//----------------------------------------------------------------
// Internal constant and parameter definitions.
//----------------------------------------------------------------
parameter DEBUG = 0;
parameter VERBOSE = 0;
parameter CLK_HALF_PERIOD = 1;
parameter CLK_PERIOD = CLK_HALF_PERIOD * 2;
//----------------------------------------------------------------
// Register and Wire declarations.
//----------------------------------------------------------------
reg [31 : 0] cycle_ctr;
reg [31 : 0] error_ctr;
reg [31 : 0] tc_ctr;
reg tb_clk;
reg tb_reset_n;
reg tb_rxd;
wire tb_txd;
wire tb_rxd_syn;
wire [7 : 0] tb_rxd_data;
wire tb_rxd_ack;
wire tb_txd_syn;
wire [7 : 0] tb_txd_data;
wire tb_txd_ack;
wire [7 : 0] tb_debug;
reg txd_state;
//----------------------------------------------------------------
// Device Under Test.
//----------------------------------------------------------------
coretest_test_core dut(
.clk(tb_clk),
.reset_n(tb_reset_n),
.rxd(tb_rxd),
.txd(tb_txd),
.debug(tb_debug)
);
//----------------------------------------------------------------
// Concurrent assignments.
//----------------------------------------------------------------
//----------------------------------------------------------------
// clk_gen
//
// Clock generator process.
//----------------------------------------------------------------
always
begin : clk_gen
#CLK_HALF_PERIOD tb_clk = !tb_clk;
end // clk_gen
//----------------------------------------------------------------
// sys_monitor
//----------------------------------------------------------------
always
begin : sys_monitor
#(CLK_PERIOD);
if (VERBOSE)
begin
$display("cycle: 0x%016x", cycle_ctr);
end
cycle_ctr = cycle_ctr + 1;
end
//----------------------------------------------------------------
// tx_monitor
//
// Observes what happens on the dut tx port and reports it.
//----------------------------------------------------------------
always @*
begin : tx_monitor
if ((!tb_txd) && txd_state)
begin
$display("txd going low.");
txd_state = 0;
end
if (tb_txd && (!txd_state))
begin
$display("txd going high");
txd_state = 1;
end
end
//----------------------------------------------------------------
// dump_dut_state()
//
// Dump the state of the dut when needed.
//----------------------------------------------------------------
task dump_dut_state();
begin
$display("State of DUT");
$display("------------");
$display("");
end
endtask // dump_dut_state
//----------------------------------------------------------------
// reset_dut()
//----------------------------------------------------------------
task reset_dut();
begin
$display("*** Toggle reset.");
tb_reset_n = 0;
#(2 * CLK_PERIOD);
tb_reset_n = 1;
end
endtask // reset_dut
//----------------------------------------------------------------
// init_sim()
//
// Initialize all counters and testbed functionality as well
// as setting the DUT inputs to defined values.
//----------------------------------------------------------------
task init_sim();
begin
cycle_ctr = 0;
error_ctr = 0;
tc_ctr = 0;
tb_clk = 0;
tb_reset_n = 1;
tb_rxd = 1;
txd_state = 1;
end
endtask // init_sim
//----------------------------------------------------------------
// transmit_byte
//
// Transmit a byte of data to the DUT receive port.
//----------------------------------------------------------------
task transmit_byte(input [7 : 0] data);
integer i;
begin
$display("*** Transmitting byte 0x%02x to the dut.", data);
#10;
// Start bit
$display("*** Transmitting start bit.");
tb_rxd = 0;
#(CLK_PERIOD * dut.uart.DEFAULT_CLK_RATE);
// Send the bits LSB first.
for (i = 0 ; i < 8 ; i = i + 1)
begin
$display("*** Transmitting data[%1d] = 0x%01x.", i, data[i]);
tb_rxd = data[i];
#(CLK_PERIOD * dut.uart.DEFAULT_CLK_RATE);
end
// Send two stop bits. I.e. two bit times high (mark) value.
$display("*** Transmitting two stop bits.");
tb_rxd = 1;
#(2 * CLK_PERIOD * dut.uart.DEFAULT_CLK_RATE * dut.uart.DEFAULT_STOP_BITS);
$display("*** End of transmission.");
end
endtask // transmit_byte
//----------------------------------------------------------------
// check_transmit
//
// Transmits a byte and checks that it was captured internally
// by the dut.
//----------------------------------------------------------------
task check_transmit(input [7 : 0] data);
begin
tc_ctr = tc_ctr + 1;
transmit_byte(data);
// if (dut.core.rxd_byte_reg == data)
// begin
// $display("*** Correct data: 0x%01x captured by the dut.",
// dut.core.rxd_byte_reg);
// end
// else
// begin
// $display("*** Incorrect data: 0x%01x captured by the dut Should be: 0x%01x.",
// dut.core.rxd_byte_reg, data);
// error_ctr = error_ctr + 1;
// end
end
endtask // check_transmit
//----------------------------------------------------------------
// test_transmit
//
// Transmit a number of test bytes to the dut.
//----------------------------------------------------------------
task test_transmit();
begin
// Send reset command.
$display("*** Sending reset command.");
check_transmit(8'h55);
check_transmit(8'h01);
check_transmit(8'haa);
// Send read command.
$display("*** Sending Read command to CORE ID0 in test core.");
check_transmit(8'h55);
check_transmit(8'h10);
check_transmit(8'h01);
check_transmit(8'h00);
check_transmit(8'haa);
// Send read command.
$display("*** Sending Read command to CORE ID2 in test core.");
check_transmit(8'h55);
check_transmit(8'h10);
check_transmit(8'h01);
check_transmit(8'h01);
check_transmit(8'haa);
// Send read command.
$display("*** Sending Read command to rw-register in test_core. 11223344.");
check_transmit(8'h55);
check_transmit(8'h10);
check_transmit(8'h01);
check_transmit(8'h10);
check_transmit(8'haa);
// Send write command.
$display("*** Sending Write command to rw-register in test_core. deadbeef.");
check_transmit(8'h55);
check_transmit(8'h11);
check_transmit(8'h01);
check_transmit(8'h10);
check_transmit(8'hde);
check_transmit(8'had);
check_transmit(8'hbe);
check_transmit(8'hef);
check_transmit(8'haa);
// Send read command.
$display("*** Sending Read command to rw-register in test_core. deadbeef.");
check_transmit(8'h55);
check_transmit(8'h10);
check_transmit(8'h01);
check_transmit(8'h10);
check_transmit(8'haa);
// Send write command.
$display("*** Sending Write command to debug-register in test_core. 77.");
check_transmit(8'h55);
check_transmit(8'h11);
check_transmit(8'h01);
check_transmit(8'h20);
check_transmit(8'h00);
check_transmit(8'h00);
check_transmit(8'h00);
check_transmit(8'h77);
check_transmit(8'haa);
end
endtask // test_transmit
//----------------------------------------------------------------
// display_test_result()
//
// Display the accumulated test results.
//----------------------------------------------------------------
task display_test_result();
begin
if (error_ctr == 0)
begin
$display("*** All %02d test cases completed successfully", tc_ctr);
end
else
begin
$display("*** %02d test cases did not complete successfully.", error_ctr);
end
end
endtask // display_test_result
//----------------------------------------------------------------
// coretest_test_core
// The main test functionality.
//----------------------------------------------------------------
initial
begin : uart_test
$display(" -- Testbench for coretest_test_core started --");
init_sim();
dump_dut_state();
reset_dut();
dump_dut_state();
test_transmit();
$display("*** transmit done.");
#(1000000 * CLK_PERIOD);
$display("*** Wait completed.");
display_test_result();
$display("*** Simulation done.");
$finish;
end // uart_test
endmodule |
module obc_upper(
clka,
wea,
addra,
dina,
douta,
clkb,
web,
addrb,
dinb,
doutb
);
input clka;
input [0 : 0] wea;
input [7 : 0] addra;
input [1 : 0] dina;
output [1 : 0] douta;
input clkb;
input [0 : 0] web;
input [5 : 0] addrb;
input [7 : 0] dinb;
output [7 : 0] doutb;
// synthesis translate_off
BLK_MEM_GEN_V7_3 #(
.C_ADDRA_WIDTH(8),
.C_ADDRB_WIDTH(6),
.C_ALGORITHM(1),
.C_AXI_ID_WIDTH(4),
.C_AXI_SLAVE_TYPE(0),
.C_AXI_TYPE(1),
.C_BYTE_SIZE(9),
.C_COMMON_CLK(1),
.C_DEFAULT_DATA("0"),
.C_DISABLE_WARN_BHV_COLL(0),
.C_DISABLE_WARN_BHV_RANGE(0),
.C_ENABLE_32BIT_ADDRESS(0),
.C_FAMILY("spartan3"),
.C_HAS_AXI_ID(0),
.C_HAS_ENA(0),
.C_HAS_ENB(0),
.C_HAS_INJECTERR(0),
.C_HAS_MEM_OUTPUT_REGS_A(0),
.C_HAS_MEM_OUTPUT_REGS_B(0),
.C_HAS_MUX_OUTPUT_REGS_A(0),
.C_HAS_MUX_OUTPUT_REGS_B(0),
.C_HAS_REGCEA(0),
.C_HAS_REGCEB(0),
.C_HAS_RSTA(0),
.C_HAS_RSTB(0),
.C_HAS_SOFTECC_INPUT_REGS_A(0),
.C_HAS_SOFTECC_OUTPUT_REGS_B(0),
.C_INIT_FILE("BlankString"),
.C_INIT_FILE_NAME("no_coe_file_loaded"),
.C_INITA_VAL("0"),
.C_INITB_VAL("0"),
.C_INTERFACE_TYPE(0),
.C_LOAD_INIT_FILE(0),
.C_MEM_TYPE(2),
.C_MUX_PIPELINE_STAGES(0),
.C_PRIM_TYPE(1),
.C_READ_DEPTH_A(256),
.C_READ_DEPTH_B(64),
.C_READ_WIDTH_A(2),
.C_READ_WIDTH_B(8),
.C_RST_PRIORITY_A("CE"),
.C_RST_PRIORITY_B("CE"),
.C_RST_TYPE("SYNC"),
.C_RSTRAM_A(0),
.C_RSTRAM_B(0),
.C_SIM_COLLISION_CHECK("ALL"),
.C_USE_BRAM_BLOCK(0),
.C_USE_BYTE_WEA(0),
.C_USE_BYTE_WEB(0),
.C_USE_DEFAULT_DATA(0),
.C_USE_ECC(0),
.C_USE_SOFTECC(0),
.C_WEA_WIDTH(1),
.C_WEB_WIDTH(1),
.C_WRITE_DEPTH_A(256),
.C_WRITE_DEPTH_B(64),
.C_WRITE_MODE_A("WRITE_FIRST"),
.C_WRITE_MODE_B("WRITE_FIRST"),
.C_WRITE_WIDTH_A(2),
.C_WRITE_WIDTH_B(8),
.C_XDEVICEFAMILY("spartan3")
)
inst (
.CLKA(clka),
.WEA(wea),
.ADDRA(addra),
.DINA(dina),
.DOUTA(douta),
.CLKB(clkb),
.WEB(web),
.ADDRB(addrb),
.DINB(dinb),
.DOUTB(doutb),
.RSTA(),
.ENA(),
.REGCEA(),
.RSTB(),
.ENB(),
.REGCEB(),
.INJECTSBITERR(),
.INJECTDBITERR(),
.SBITERR(),
.DBITERR(),
.RDADDRECC(),
.S_ACLK(),
.S_ARESETN(),
.S_AXI_AWID(),
.S_AXI_AWADDR(),
.S_AXI_AWLEN(),
.S_AXI_AWSIZE(),
.S_AXI_AWBURST(),
.S_AXI_AWVALID(),
.S_AXI_AWREADY(),
.S_AXI_WDATA(),
.S_AXI_WSTRB(),
.S_AXI_WLAST(),
.S_AXI_WVALID(),
.S_AXI_WREADY(),
.S_AXI_BID(),
.S_AXI_BRESP(),
.S_AXI_BVALID(),
.S_AXI_BREADY(),
.S_AXI_ARID(),
.S_AXI_ARADDR(),
.S_AXI_ARLEN(),
.S_AXI_ARSIZE(),
.S_AXI_ARBURST(),
.S_AXI_ARVALID(),
.S_AXI_ARREADY(),
.S_AXI_RID(),
.S_AXI_RDATA(),
.S_AXI_RRESP(),
.S_AXI_RLAST(),
.S_AXI_RVALID(),
.S_AXI_RREADY(),
.S_AXI_INJECTSBITERR(),
.S_AXI_INJECTDBITERR(),
.S_AXI_SBITERR(),
.S_AXI_DBITERR(),
.S_AXI_RDADDRECC()
);
// synthesis translate_on
endmodule |
module timeunit;
initial $timeformat(-9,1," ns",9);
endmodule |
module TOP;
reg a;
wire clk;
wire z;
clk_gen #(.HALF_PERIOD(50)) cg(clk);
initial
begin
// @haco@ flop_it.haco-c
$prsim("flop_it.haco-c");
$prsim_cmd("echo $start of simulation");
$prsim_cmd("watchall");
$to_prsim("TOP.a", "a");
$to_prsim("TOP.clk", "clk");
$from_prsim("z", "TOP.z");
end
// these could be automatically generated
// by finding all globally unique instances of processes
// along with their hierarchical names
// e.g. from hacobjdump of .haco-c file
HAC_POS_FLOP #(.prsim_name("F.f[0]")) f0();
HAC_POS_FLOP #(.prsim_name("F.f[1]")) f1();
HAC_POS_FLOP #(.prsim_name("F.f[2]")) f2();
HAC_POS_FLOP #(.prsim_name("F.f[3]")) f3();
initial
begin
#20 a <= 1'b0;
#400 a <= 1'b1;
#400 a <= 1'b0;
#100 a <= 1'b1;
#100 a <= 1'b0;
#100 a <= 1'b1;
#300 a <= 1'b0;
#50 $finish;
end
endmodule |
module RAM8192x32_2RW (
address_a,
address_b,
byteena_a,
byteena_b,
clock,
data_a,
data_b,
wren_a,
wren_b,
q_a,
q_b);
input [12:0] address_a;
input [12:0] address_b;
input [3:0] byteena_a;
input [3:0] byteena_b;
input clock;
input [31:0] data_a;
input [31:0] data_b;
input wren_a;
input wren_b;
output [31:0] q_a;
output [31:0] q_b;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 [3:0] byteena_a;
tri1 [3:0] byteena_b;
tri1 clock;
tri0 wren_a;
tri0 wren_b;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
endmodule |
module system_c_addsub_0_0
(A,
B,
S);
(* x_interface_info = "xilinx.com:signal:data:1.0 a_intf DATA" *) input [9:0]A;
(* x_interface_info = "xilinx.com:signal:data:1.0 b_intf DATA" *) input [9:0]B;
(* x_interface_info = "xilinx.com:signal:data:1.0 s_intf DATA" *) output [9:0]S;
wire [9:0]A;
wire [9:0]B;
wire [9:0]S;
wire NLW_U0_C_OUT_UNCONNECTED;
(* C_BORROW_LOW = "1" *)
(* C_CE_OVERRIDES_BYPASS = "1" *)
(* C_CE_OVERRIDES_SCLR = "0" *)
(* C_IMPLEMENTATION = "0" *)
(* C_SCLR_OVERRIDES_SSET = "1" *)
(* C_VERBOSITY = "0" *)
(* C_XDEVICEFAMILY = "zynq" *)
(* c_a_type = "0" *)
(* c_a_width = "10" *)
(* c_add_mode = "0" *)
(* c_ainit_val = "0" *)
(* c_b_constant = "0" *)
(* c_b_type = "0" *)
(* c_b_value = "0000000000" *)
(* c_b_width = "10" *)
(* c_bypass_low = "0" *)
(* c_has_bypass = "0" *)
(* c_has_c_in = "0" *)
(* c_has_c_out = "0" *)
(* c_has_ce = "0" *)
(* c_has_sclr = "0" *)
(* c_has_sinit = "0" *)
(* c_has_sset = "0" *)
(* c_latency = "0" *)
(* c_out_width = "10" *)
(* c_sinit_val = "0" *)
(* downgradeipidentifiedwarnings = "yes" *)
system_c_addsub_0_0_c_addsub_v12_0_10 U0
(.A(A),
.ADD(1'b1),
.B(B),
.BYPASS(1'b0),
.CE(1'b1),
.CLK(1'b0),
.C_IN(1'b0),
.C_OUT(NLW_U0_C_OUT_UNCONNECTED),
.S(S),
.SCLR(1'b0),
.SINIT(1'b0),
.SSET(1'b0));
endmodule |
module system_c_addsub_0_0_c_addsub_v12_0_10
(A,
B,
CLK,
ADD,
C_IN,
CE,
BYPASS,
SCLR,
SSET,
SINIT,
C_OUT,
S);
input [9:0]A;
input [9:0]B;
input CLK;
input ADD;
input C_IN;
input CE;
input BYPASS;
input SCLR;
input SSET;
input SINIT;
output C_OUT;
output [9:0]S;
wire \<const0> ;
wire [9:0]A;
wire [9:0]B;
wire [9:0]S;
wire NLW_xst_addsub_C_OUT_UNCONNECTED;
assign C_OUT = \<const0> ;
GND GND
(.G(\<const0> ));
(* C_BORROW_LOW = "1" *)
(* C_CE_OVERRIDES_BYPASS = "1" *)
(* C_CE_OVERRIDES_SCLR = "0" *)
(* C_IMPLEMENTATION = "0" *)
(* C_SCLR_OVERRIDES_SSET = "1" *)
(* C_VERBOSITY = "0" *)
(* C_XDEVICEFAMILY = "zynq" *)
(* c_a_type = "0" *)
(* c_a_width = "10" *)
(* c_add_mode = "0" *)
(* c_ainit_val = "0" *)
(* c_b_constant = "0" *)
(* c_b_type = "0" *)
(* c_b_value = "0000000000" *)
(* c_b_width = "10" *)
(* c_bypass_low = "0" *)
(* c_has_bypass = "0" *)
(* c_has_c_in = "0" *)
(* c_has_c_out = "0" *)
(* c_has_ce = "0" *)
(* c_has_sclr = "0" *)
(* c_has_sinit = "0" *)
(* c_has_sset = "0" *)
(* c_latency = "0" *)
(* c_out_width = "10" *)
(* c_sinit_val = "0" *)
(* downgradeipidentifiedwarnings = "yes" *)
system_c_addsub_0_0_c_addsub_v12_0_10_viv xst_addsub
(.A(A),
.ADD(1'b0),
.B(B),
.BYPASS(1'b0),
.CE(1'b0),
.CLK(1'b0),
.C_IN(1'b0),
.C_OUT(NLW_xst_addsub_C_OUT_UNCONNECTED),
.S(S),
.SCLR(1'b0),
.SINIT(1'b0),
.SSET(1'b0));
endmodule |
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule |
module controller (sys_clk,
sram_clk,
nreset,
wb_cyc,
wb_stb_sram,
wb_stb_local,
wb_we,
wb_sel,
wb_ack,
wb_adr,
wb_dat_o,
wb_dat_i,
mSR_Select,
mSR_WE,
mSR_OE,
mSR_ADDR,
mRS2SR_DATA,
mSDR_DATAC2M,
mSDR_DATAM2C,
mSDR_Done,
mSDR_ADDR,
mSDR_RD,
mSDR_WR,
status,
cpu_done,
resetcpu,
gpio0_in,
gpio1_in,
gpio0_out,
gpio1_out,
gpio0_oe,
gpio1_oe,
sw,
key,
ps2_clk,
ps2_dat,
ps2_int,
I2C_SCLK,
I2C_SDAT_OUT,
I2C_SDAT_IN,
SRAM_DQ,
SRAM_DQ_OUT,
SRAM_DQ_OE,
SRAM_ADDR,
SRAM_UB_N,
SRAM_LB_N,
SRAM_OE_N,
SRAM_WE_N,
SRAM_CE_N,
DRAM_DQ,
DRAM_ADDR,
DRAM_LDQM,
DRAM_UDQM,
DRAM_WE_N,
DRAM_CAS_N,
DRAM_RAS_N,
DRAM_CS_N,
DRAM_BA_0,
DRAM_BA_1,
DRAM_CLK,
DRAM_CKE
);
// Clocks and reset
input sys_clk;
input sram_clk;
input nreset;
// Wishbone bus
input wb_cyc;
input wb_stb_sram;
input wb_stb_local;
input wb_we;
input [3:0] wb_sel;
input [31:0] wb_adr;
input [31:0] wb_dat_o; // An input, but matches name of LM32 interface
output [31:0] wb_dat_i; // An output, but matches name of LM32 interface
output wb_ack;
// USB-JTAG SRAM bus
input mSR_Select;
input mSR_WE;
input mSR_OE;
input [17:0] mSR_ADDR;
input [15:0] mRS2SR_DATA;
// USB-JTAG SDRAM bus
input [15:0] mSDR_DATAC2M;
output [15:0] mSDR_DATAM2C;
output mSDR_Done;
input [21:0] mSDR_ADDR;
input mSDR_RD;
input mSDR_WR;
// Execution control and status
output [31:0] status;
output cpu_done;
output resetcpu;
// SRAM interface
input [15:0] SRAM_DQ;
output [15:0] SRAM_DQ_OUT;
output SRAM_DQ_OE;
output [17:0] SRAM_ADDR;
output SRAM_UB_N;
output SRAM_LB_N;
output SRAM_OE_N;
output SRAM_WE_N;
output SRAM_CE_N;
// SDRAM Interface
inout [15:0] DRAM_DQ;
output [11:0] DRAM_ADDR;
output DRAM_LDQM;
output DRAM_UDQM;
output DRAM_WE_N;
output DRAM_CAS_N;
output DRAM_RAS_N;
output DRAM_CS_N;
output DRAM_BA_0;
output DRAM_BA_1;
output DRAM_CLK;
output DRAM_CKE;
input [35:0] gpio0_in;
input [35:0] gpio1_in;
output [35:0] gpio0_out;
output [35:0] gpio1_out;
output [35:0] gpio0_oe;
output [35:0] gpio1_oe;
input [9:0] sw;
input [3:0] key;
input ps2_clk;
input ps2_dat;
output ps2_int;
output I2C_SDAT_OUT;
input I2C_SDAT_IN;
output I2C_SCLK;
//-------------------------------------------------------------
// Internal state
//-------------------------------------------------------------
reg [31:0] status;
reg resetcpu;
reg cpu_done;
reg sram_ack;
reg [15:0] sram_latched_data;
reg swen_reg;
reg [39:0] gpio0_out_reg;
reg [39:0] gpio1_out_reg;
reg [39:0] gpio0_oe_reg;
reg [39:0] gpio1_oe_reg;
reg ps2_clk_last;
reg [9:0] ps2_shift;
reg [3:0] ps2_bit_count;
reg [31:0] ps2_rx_data;
reg [23:0] i2c_data;
reg i2c_go;
reg i2c_ack;
//-------------------------------------------------------------
//Combinatorial logic
//-------------------------------------------------------------
wire dram_cs_n_1_dummy;
wire [31:0] internal_dat;
wire i2c_end;
wire i2c_active;
wire i2c_ack_out;
wire [31:0] gpio_addr = `GPIO_BASE_ADDR;
wire [31:0] ps2_addr = `PS2_BASE_ADDR;
wire [31:0] i2c_addr = `I2C_BASE_ADDR;
// CPU SRAM access logic.
wire swrite = wb_cyc & wb_stb_sram & wb_we;
wire sube = sram_ack ? wb_sel[0] : wb_sel[2];
wire slbe = sram_ack ? wb_sel[1] : wb_sel[3];
wire [17:0] saddr = {wb_adr[18:2], sram_ack};
wire [15:0] sdata_out = sram_ack ? {wb_dat_o[7:0], wb_dat_o[15:8]} :
{wb_dat_o[23:16], wb_dat_o[31:24]}; // Big endian
wire [31:0] sdata_in = {sram_latched_data[7:0], sram_latched_data[15:8],
SRAM_DQ[7:0], SRAM_DQ[15:8]}; // Big endian
// Acknowledge immediately for local accesses, or on SRAM acknowledge.
assign wb_ack = wb_stb_local ? wb_cyc : sram_ack;
// Mux to the local bus for local accesses, else the SRAM returned data
assign wb_dat_i = wb_stb_local ? internal_dat : sdata_in;
// Connect the SRAM signals to either JTAG or CPU signals,
// depending on mSR_Select
assign SRAM_ADDR = mSR_Select ? mSR_ADDR : saddr;
assign SRAM_UB_N = mSR_Select ? 1'b0 : ~sube;
assign SRAM_LB_N = mSR_Select ? 1'b0 : ~slbe;
assign SRAM_OE_N = mSR_Select ? mSR_OE : swrite;
assign SRAM_WE_N = swen_reg;
assign SRAM_CE_N = 1'b0;
// Arbitrate access write data to the SRAM data bus. mSR_Select is
// set for JTAG access, and clear for CPU. When no active writes,
// bus is tri-stated (SRAM_DQ_OE clear).
assign SRAM_DQ_OUT = mSR_Select ? mRS2SR_DATA : sdata_out ;
assign SRAM_DQ_OE = (mSR_Select & ~mSR_WE) | (~mSR_Select & swrite);
//-------------------------------------------------------------
// SRAM state update logic
//-------------------------------------------------------------
// On an active bus cycle, acknowledge on second cycle, allowing
// two reads from SRAM to construct 32 bit word from each 16 bit
// SRAM read value. sram_ack is used as lower address bit. The
// first cycle's read data is stored in sram_latched_data.
always @(posedge sys_clk or negedge nreset)
begin
if (nreset == 1'b0)
begin
sram_ack <= 1'b0;
sram_latched_data <= 16'h0000;
end
else
begin
sram_ack <= 1'b0;
if ((wb_cyc & wb_stb_sram & ~sram_ack) == 1'b1)
begin
sram_ack <= 1'b1;
sram_latched_data <= SRAM_DQ;
end
end
end
//-------------------------------------------------------------
// SRAM write enable generation
//-------------------------------------------------------------
// A write is active when either JTAG write or CPU write, selected
// on mSR_Select bit 0
wire wr_req = mSR_Select ? ~mSR_WE : swrite;
// Generate a write enable signal for only half of a write access
// giving plenty of timing margin on writes, without the need for
// complex constraints. sram_clk has a maximum frequency of 80MHz
// in order to meet the minimum timings for SRAM on the ALTERA
// Cyclone II DE1 development board.
// ___ ___ ___
// sys_clk _/ \___/ \___/
// _ _ _ _ _ _
// sram_clk \_/ \_/ \_/ \_/ \_/
// _______
// OEn X/ \XXXXXXXXXXXX
// ___ _____________
// WEn \___/
always @(posedge sram_clk or negedge nreset)
begin
if (nreset == 1'b0)
begin
swen_reg <= 1'b1;
end
else
begin
if ((swen_reg & wr_req) == 1'b1)
begin
swen_reg <= 1'b0;
end
else
begin
swen_reg <= 1'b1;
end
end
end
//-------------------------------------------------------------
// Status state update logic
//-------------------------------------------------------------
// Put test status address into a wire for ease of bit slicing
wire [31:0] test_addr = `TEST_STATUS_ADDR;
wire [31:0] test_halt_addr = `TEST_HALT_ADDR;
// Generate CPU reset, and latch test status. When a JTAG write to test
// status address, the CPU us asserted or deasserted according to whether
// JTAG is master of the SRAM bus or not. The status is captured if the
// CPU does a write access to the test address.
always @(posedge sys_clk or negedge nreset)
begin
if (nreset == 1'b0)
begin
resetcpu <= 1'b1;
status <= 32'h00000000;
// By default, flag the CPU as done, since not all the code
// running on the system will update this, and test code waiting
// on CPU completion might hang. Software using this feature
// should clear this flag early on program execution, and set
// it just prior to completion.
cpu_done <= 1'b1;
end
else
begin
// If CPU potentially writing to a test address...
if ((wb_cyc & wb_we & wb_ack) == 1'b1)
begin
// If writing to the test_addr SRAM test result location,
// latch the data into status
if (wb_stb_sram == 1'b1 && wb_adr == test_addr)
begin
status <= wb_dat_o;
end
// If writing to the test 'CPU done' local address,
// update the 'CPU done' state
if (wb_stb_local == 1'b1 && wb_adr == test_halt_addr)
begin
cpu_done <= wb_dat_o[0];
end
end
// If controller writes to test location, when SRAM selected
// or CPU, release CPU reset, or reassert if SRAM selected for JTAG
if (mSR_WE == 1'b0 && mSR_ADDR == test_addr[18:1])
begin
resetcpu <= mSR_Select;
end
end
end
//-------------------------------------------------------------
// GPIO state update logic
//-------------------------------------------------------------
// Expand the 36 bits of the GPIO ports to the 40 bit connector positions, for register reads
wire [39:0] gpio40_0_in = {gpio0_in[35:26], 1'b0, 1'b1, gpio0_in[25:10], 1'b0, 1'b1, gpio0_in[9:0]};
wire [39:0] gpio40_1_in = {gpio0_in[35:26], 1'b0, 1'b1, gpio0_in[25:10], 1'b0, 1'b1, gpio0_in[9:0]};
wire [39:0] gpio40_0_oe_in = {gpio0_oe[35:26], 1'b0, 1'b1, gpio0_oe[25:10], 1'b0, 1'b1, gpio0_oe[9:0]};
wire [39:0] gpio40_1_oe_in = {gpio1_oe[35:26], 1'b0, 1'b1, gpio1_oe[25:10], 1'b0, 1'b1, gpio1_oe[9:0]};
// Collapse the 40 bit registers with connector positions, to 36 bit outputs
assign gpio0_out = {gpio0_out_reg[39:30], gpio0_out_reg[27:12], gpio0_out_reg[9:0]};
assign gpio1_out = {gpio1_out_reg[39:30], gpio1_out_reg[27:12], gpio1_out_reg[9:0]};
assign gpio0_oe = {gpio0_oe_reg [39:30], gpio0_oe_reg [27:12], gpio0_oe_reg [9:0]};
assign gpio1_oe = {gpio1_oe_reg [39:30], gpio1_oe_reg [27:12], gpio1_oe_reg [9:0]};
// Mux the internal registers to internal read data
wire [31:0] gpio_dat = (wb_adr[5:2] == (`GPIO_0_LO_REG >> 2)) ? gpio0_in[31:0] :
(wb_adr[5:2] == (`GPIO_0_HI_REG >> 2)) ? {24'h000000, gpio40_0_in[39:32]} :
(wb_adr[5:2] == (`GPIO_1_LO_REG >> 2)) ? gpio0_in[31:0] :
(wb_adr[5:2] == (`GPIO_1_HI_REG >> 2)) ? {24'h000000, gpio40_1_in[39:32]} :
(wb_adr[5:2] == (`GPIO_0_OE_LO_REG >> 2)) ? gpio0_oe_reg[31:0] :
(wb_adr[5:2] == (`GPIO_0_OE_HI_REG >> 2)) ? {24'h000000, gpio0_oe_reg[39:32]} :
(wb_adr[5:2] == (`GPIO_1_OE_LO_REG >> 2)) ? gpio1_oe_reg[31:0] :
(wb_adr[5:2] == (`GPIO_1_OE_HI_REG >> 2)) ? {24'h000000, gpio1_oe_reg[39:32]} :
(wb_adr[5:2] == (`GPIO_0_X_LO_REG >> 2)) ? gpio40_0_in[31:0] :
(wb_adr[5:2] == (`GPIO_0_X_HI_REG >> 2)) ? {24'h000000, gpio40_0_in[39:32]} :
(wb_adr[5:2] == (`GPIO_1_X_LO_REG >> 2)) ? gpio40_0_in[31:0] :
(wb_adr[5:2] == (`GPIO_1_X_HI_REG >> 2)) ? {24'h000000, gpio40_1_in[39:32]} :
(wb_adr[5:2] == (`GPIO_0_X_OE_LO_REG >> 2)) ? gpio40_0_oe_in[31:0] :
(wb_adr[5:2] == (`GPIO_0_X_OE_HI_REG >> 2)) ? {24'h000000, gpio40_0_oe_in[39:32]} :
(wb_adr[5:2] == (`GPIO_1_X_OE_LO_REG >> 2)) ? gpio40_1_oe_in[31:0] :
(wb_adr[5:2] == (`GPIO_1_X_OE_HI_REG >> 2)) ? {24'h000000, gpio40_1_oe_in[39:32]} :
32'h00000000;
wire [31:0] sw_dat = (wb_adr[5:2] == (`SWITCH_DPDT_REG >>2)) ? {22'h000000, sw} :
(wb_adr[5:2] == (`SWITCH_KEY_REG >> 2)) ? {28'h0000000, key} :
32'h00000000;
assign internal_dat = (wb_adr[30:28] == gpio_addr[30:28]) ? gpio_dat :
(wb_adr[30:28] == ps2_addr[30:28]) ? ps2_rx_data :
(wb_adr[30:28] == i2c_addr[30:28]) ? {i2c_active, i2c_ack, 6'h00, i2c_data} :
sw_dat;
// GPIO register writes
always @(posedge sys_clk or negedge nreset)
begin
if (nreset == 1'b0)
begin
gpio0_out_reg <= 40'd0;
gpio1_out_reg <= 40'd0;
gpio0_oe_reg <= 40'd0;
gpio1_oe_reg <= 40'd0;
end
else
begin
// If CPU writing to an internal address....
if ((wb_cyc & wb_stb_local & wb_we) == 1'b1)
begin
// If writing to the GPIO registers...
if (wb_adr[31:28] == gpio_addr[31:28])
begin
case (wb_adr[5:2])
// Write as a contiguous 36 bits, mapped to the 40 bits of connector
(`GPIO_0_LO_REG >> 2): gpio0_out_reg[35:0] <= {wb_dat_o[31:26], 1'b0, 1'b1, wb_dat_o[25:10], 1'b0, 1'b1, wb_dat_o[9:0]};
(`GPIO_0_HI_REG >> 2): gpio0_out_reg[39:36] <= wb_dat_o[3:0];
(`GPIO_1_LO_REG >> 2): gpio1_out_reg[35:0] <= {wb_dat_o[31:26], 1'b0, 1'b1, wb_dat_o[25:10], 1'b0, 1'b1, wb_dat_o[9:0]};
(`GPIO_1_HI_REG >> 2): gpio1_out_reg[39:36] <= wb_dat_o[3:0];
(`GPIO_0_OE_LO_REG >> 2): gpio0_oe_reg [35:0] <= {wb_dat_o[31:26], 1'b0, 1'b1, wb_dat_o[25:10], 1'b0, 1'b1, wb_dat_o[9:0]};
(`GPIO_0_OE_HI_REG >> 2): gpio0_oe_reg [39:36] <= wb_dat_o[3:0];
(`GPIO_1_OE_LO_REG >> 2): gpio1_oe_reg [35:0] <= {wb_dat_o[31:26], 1'b0, 1'b1, wb_dat_o[25:10], 1'b0, 1'b1, wb_dat_o[9:0]};
(`GPIO_1_OE_HI_REG >> 2): gpio1_oe_reg [39:36] <= wb_dat_o[3:0];
// Write directly as 40 bits of connector. Bits 10, 11, 28 and 29 have no affect (VCC and GND positions)
(`GPIO_0_X_LO_REG >> 2): gpio0_out_reg[31:0] <= wb_dat_o;
(`GPIO_0_X_HI_REG >> 2): gpio0_out_reg[39:32] <= wb_dat_o[7:0];
(`GPIO_1_X_LO_REG >> 2): gpio1_out_reg[31:0] <= wb_dat_o;
(`GPIO_1_X_HI_REG >> 2): gpio1_out_reg[39:32] <= wb_dat_o[7:0];
(`GPIO_0_X_OE_LO_REG >> 2): gpio0_oe_reg [31:0] <= wb_dat_o;
(`GPIO_0_X_OE_HI_REG >> 2): gpio0_oe_reg [39:32] <= wb_dat_o[7:0];
(`GPIO_1_X_OE_LO_REG >> 2): gpio1_oe_reg [31:0] <= wb_dat_o;
(`GPIO_1_X_OE_HI_REG >> 2): gpio1_oe_reg [39:32] <= wb_dat_o[7:0];
endcase
end
end
end
end
//-------------------------------------------------------------
// PS2 logic
//-------------------------------------------------------------
// Assert PS2 interrupt line whenever there is a valid byte
// in the PS2 rx data register.
assign ps2_int = ps2_rx_data[`PS2_RX_VALID_RNG];
always @(posedge sys_clk or negedge nreset)
begin
if (nreset == 1'b0)
begin
ps2_clk_last <= 1'b1;
ps2_bit_count <= 4'h0;
ps2_rx_data[`PS2_RX_VALID_RNG] <= 1'b0;
end
else
begin
ps2_clk_last <= ps2_clk;
// On falling edge of clock...
if (ps2_clk_last == 1'b1 && ps2_clk == 1'b0)
begin
// Shift in data bit
ps2_shift <= {ps2_dat, ps2_shift[9:1]};
// If this is the start bit, set the bit counter
if (ps2_bit_count == 4'h0)
begin
ps2_bit_count <= 4'd11;
end
// If this is the stop bit....
if (ps2_bit_count == 4'h1)
begin
// Latch the shifted in data
ps2_rx_data[28:0] <= {21'h000000, ps2_shift[8:1]};
// Set the valid bit
ps2_rx_data[`PS2_RX_VALID_RNG] <= 1'b1;
// Set the parity error if not odd parity (sticky)
ps2_rx_data[`PS2_RX_PAR_ERR_RNG] <= ps2_rx_data[`PS2_RX_PAR_ERR_RNG] | (~^ps2_shift[9:1]);
// Set overflow bit if valid bit not clear (sticky)
ps2_rx_data[`PS2_RX_OVRFLOW_RNG] <= ps2_rx_data[`PS2_RX_OVRFLOW_RNG] | ps2_rx_data[`PS2_RX_VALID_RNG];
end
end
// If CPU accessing a PS2 address....
if ((wb_cyc & wb_stb_local) == 1'b1 && wb_adr[31:28] == ps2_addr[31:28])
begin
// Writing to the PS2 register (regardless of address offset)
if (wb_we)
begin
ps2_rx_data <= wb_dat_o;
end
// When reading from the PS2 RX register, clear the valid bit
// (register can be peek'd without clearing valid at `PS2_RX_PEEK_OFFSET)
else
begin
if (wb_adr[5:2] == (`PS2_RX_REG >> 2))
begin
ps2_rx_data[`PS2_RX_VALID_RNG] <= 1'b0;
end
end
end
end
end
//-------------------------------------------------------------
// I2C
//-------------------------------------------------------------
always @(posedge sys_clk or negedge nreset)
begin
if (nreset == 1'b0)
begin
i2c_go <= 1'b0;
i2c_ack <= 1'b0;
end
else
begin
// If CPU writing to an I2C address....
if ((wb_cyc & wb_stb_local & wb_we) == 1'b1 && wb_adr[31:28] == i2c_addr[31:28])
begin
i2c_data <= wb_dat_o[23:0];
i2c_go <= 1'b1;
i2c_ack <= 1'b0;
end
if (i2c_end == 1'b1)
begin
i2c_go <= 1'b0;
i2c_ack <= i2c_ack_out;
end
end
end
I2C_Controller u1 (
.clk (sys_clk),
.nreset (nreset),
.I2C_SCLK (I2C_SCLK),
.I2C_SDAT_OUT(I2C_SDAT_OUT),
.I2C_SDAT_IN (I2C_SDAT_IN),
.I2C_DATA (i2c_data),
.GO (i2c_go),
.END (i2c_end),
.W_R (1'b1),
.ACK (i2c_ack_out),
.ACTIVE (i2c_active)
);
Sdram_Controller u2 (
// HOST
.CLK (sys_clk),
.REF_CLK (sys_clk),
.RESET_N (nreset),
.ADDR ({1'b0, mSDR_ADDR}),
.WR (mSDR_WR),
.RD (mSDR_RD),
.LENGTH (8'h01),
.ACT (),
.DONE (mSDR_Done),
.DATAIN (mSDR_DATAC2M),
.DATAOUT (mSDR_DATAM2C),
.IN_REQ (),
.OUT_VALID (),
.DM (2'b00),
// SDRAM
.SA (DRAM_ADDR),
.BA ({DRAM_BA_1, DRAM_BA_0}),
.CS_N ({dram_cs_n_1_dummy, DRAM_CS_N}),
.CKE (DRAM_CKE),
.RAS_N (DRAM_RAS_N),
.CAS_N (DRAM_CAS_N),
.WE_N (DRAM_WE_N),
.DQ (DRAM_DQ),
.DQM ({DRAM_UDQM, DRAM_LDQM})
);
endmodule |
module kvs_vs_RegexTop
(
input clk,
input rst,
input [511:0] input_data,
input input_valid,
input input_last,
output input_ready,
input [511:0] config_data,
input config_valid,
output config_ready,
output found_loc,
output found_valid,
input found_ready
);
parameter REGEX_COUNT_BITS = 4;
parameter MAX_REGEX_ENGINES = 16;
wire [511:0] regex_input_data [MAX_REGEX_ENGINES-1:0];
reg [511:0] regex_input_prebuf [MAX_REGEX_ENGINES-1:0];
wire [MAX_REGEX_ENGINES-1:0] regex_input_hasdata;
wire [MAX_REGEX_ENGINES-1:0] regex_input_almfull;
wire [MAX_REGEX_ENGINES-1:0] regex_input_notfull;
wire [MAX_REGEX_ENGINES-1:0] regex_input_ready;
reg [MAX_REGEX_ENGINES-1:0] regex_input_enable;
reg [MAX_REGEX_ENGINES-1:0] regex_input_type;
wire [MAX_REGEX_ENGINES*16-1:0] regex_output_index ;
wire [MAX_REGEX_ENGINES-1:0] regex_output_match;
wire [MAX_REGEX_ENGINES-1:0] regex_output_valid;
wire [MAX_REGEX_ENGINES-1:0] outfifo_valid;
wire [MAX_REGEX_ENGINES-1:0] outfifo_ready;
wire [MAX_REGEX_ENGINES-1:0] outfifo_data;
reg [REGEX_COUNT_BITS-1:0] outfifo_pos;
reg [REGEX_COUNT_BITS-1:0] current_regex_engine;
reg [REGEX_COUNT_BITS-1:0] config_regex_engine;
reg [REGEX_COUNT_BITS-1:0] output_regex_engine;
reg config_wait;
reg regex_inputbuffer_ok;
reg regex_inputbuffer_pre;
assign input_ready = (regex_inputbuffer_ok);
assign config_ready = ~regex_input_enable[config_regex_engine] && (regex_inputbuffer_ok);
reg rstBuf;
integer x;
always @(posedge clk) begin
rstBuf <= rst;
if (rst) begin
current_regex_engine <= 0;
config_regex_engine <= 0;
regex_input_enable <= 0;
output_regex_engine <= 0;
config_wait <= 0;
regex_inputbuffer_ok <= 0;
regex_inputbuffer_pre <= 0;
end
else begin
regex_input_enable <= 0;
regex_inputbuffer_pre <= (regex_input_notfull == {MAX_REGEX_ENGINES{1'b1}} ? 1 : 0) && (regex_input_almfull == 0 ? 1 : 0);
regex_inputbuffer_ok <= regex_inputbuffer_pre;
if (config_ready==1 && config_valid==1) begin
regex_input_prebuf[config_regex_engine] <= config_data;
regex_input_enable[config_regex_engine] <= 1;
regex_input_type[config_regex_engine] <= 1;
if (config_regex_engine==MAX_REGEX_ENGINES-1) begin
config_regex_engine <= 0;
end else begin
config_regex_engine <= config_regex_engine +1;
end
if (config_data[511]==1) begin
for (x=0; x<MAX_REGEX_ENGINES; x=x+1) begin
regex_input_prebuf[x] <= config_data;
end
regex_input_enable <= {MAX_REGEX_ENGINES{1'b1}};
regex_input_type <= {MAX_REGEX_ENGINES{1'b1}};
end
end
if (input_ready==1 && input_valid==1) begin
regex_input_prebuf[current_regex_engine] <= input_data;
regex_input_enable[current_regex_engine] <= 1;
regex_input_type[current_regex_engine] <= 0;
if (input_last==1) begin
if (current_regex_engine==MAX_REGEX_ENGINES-1) begin
current_regex_engine <= 0;
end else begin
current_regex_engine <= current_regex_engine +1;
end
end
end
if (found_valid==1 && found_ready==1) begin
if (output_regex_engine==MAX_REGEX_ENGINES-1) begin
output_regex_engine <= 0;
end else begin
output_regex_engine <= output_regex_engine+1;
end
end
end
end
assign found_valid = outfifo_valid[output_regex_engine];
assign found_loc = outfifo_data[output_regex_engine];
genvar X;
generate
for (X=0; X < MAX_REGEX_ENGINES; X=X+1)
begin: generateloop
/*nukv_fifogen #(
.DATA_SIZE(512),
.ADDR_BITS(4)
) */
fifo_generator_512_shallow_sync
fifo_values (
.s_aclk(clk),
.s_aresetn(~rstBuf),
.s_axis_tdata(regex_input_prebuf[X]),
.s_axis_tvalid(regex_input_enable[X]),
.s_axis_tready(regex_input_notfull[X]),
.axis_prog_full(regex_input_almfull[X]),
.m_axis_tdata(regex_input_data[X][511:0]),
.m_axis_tvalid(regex_input_hasdata[X]),
.m_axis_tready(regex_input_ready[X])
);
rem_top_ff rem_top_instance (
.clk(clk),
.rst(rstBuf),
.softRst((regex_input_enable[X] & regex_input_type[X])),
.input_valid(regex_input_hasdata[X]),
.input_data(regex_input_data[X][511:0]),
.input_ready(regex_input_ready[X]),
.output_valid(regex_output_valid[X]),
.output_match(regex_output_match[X]),
.output_index(regex_output_index[(X+1)*16-1:X*16])
);
/*kvs_LatchedRelay #(
.WIDTH(1)
) fifo_results (
.clk(clk),
.rst(rst),
.in_data(regex_output_match[X]),
.in_valid(regex_output_valid[X]),
.in_ready(),
.out_data(outfifo_data[X]),
.out_valid(outfifo_valid[X]),
.out_ready(outfifo_ready[X])
);*/
fifo_generator_1byte_sync
fifo_decision_from_regex (
.s_aclk(clk),
.s_aresetn(~rst),
.s_axis_tdata(regex_output_match[X]),
.s_axis_tvalid(regex_output_valid[X]),
.s_axis_tready(),
.m_axis_tdata(outfifo_data[X]),
.m_axis_tvalid(outfifo_valid[X]),
.m_axis_tready(outfifo_ready[X])
);
assign outfifo_ready[X] = output_regex_engine==X ? found_ready : 0;
end
endgenerate
endmodule |
module sky130_fd_sc_hs__nand4b (
//# {{data|Data Signals}}
input A_N ,
input B ,
input C ,
input D ,
output Y ,
//# {{power|Power}}
input VPWR,
input VGND
);
endmodule |
module prcfg_dac(
clk,
// control ports
control,
status,
// FIFO interface
src_dac_enable,
src_dac_data,
src_dac_valid,
dst_dac_enable,
dst_dac_data,
dst_dac_valid
);
localparam RP_ID = 8'hA0;
parameter CHANNEL_ID = 0;
input clk;
input [31:0] control;
output [31:0] status;
output src_dac_enable;
input [15:0] src_dac_data;
output src_dac_valid;
input dst_dac_enable;
output [15:0] dst_dac_data;
input dst_dac_valid;
reg src_dac_enable;
reg src_dac_valid;
reg [15:0] dst_dac_data;
assign status = {24'h0, RP_ID};
always @(posedge clk) begin
src_dac_enable <= dst_dac_enable;
dst_dac_data <= src_dac_data;
src_dac_valid <= dst_dac_valid;
end
endmodule |
module cpci_heartbeat
(
output reg heartbeat,
input reset,
input clk
);
// generate a much slower clock - 10 Hz
parameter MAX_COUNT = 6250000;
reg [23:0] ten_hertz_count;
always @(posedge clk)
if (reset) ten_hertz_count <= 'h0;
else
if (ten_hertz_count == MAX_COUNT) ten_hertz_count <= 'h0;
else ten_hertz_count <= ten_hertz_count + 24'h1;
reg ten_hertz;
always @(posedge clk)
if (reset) ten_hertz <= 'h0;
else ten_hertz <= (ten_hertz_count == MAX_COUNT) ? 1 : 0;
// this is the slow counting counter
reg [4:0] slow_count;
always @(posedge clk)
if (reset) slow_count <= 'h0;
else if (ten_hertz) begin
if (slow_count == 20) slow_count <= 'h0;
else slow_count <= slow_count + 'h1;
end
// Now generate hearbeat.
reg heartbeat_nxt;
always @* begin
heartbeat_nxt = 1;
if (slow_count == 'd0 ) heartbeat_nxt = 0;
if (slow_count == 'd2 ) heartbeat_nxt = 0;
if (slow_count == 'd10) heartbeat_nxt = 0;
if (slow_count == 'd12) heartbeat_nxt = 0;
end
always @(posedge clk) heartbeat <= heartbeat_nxt;
endmodule |
module display4digit(
input [15:0] A,
input clk,
output [7:0] segments,
output reg [3:0] digitselect
);
reg [18:0] counter = 0;
wire [1:0] toptwo;
reg [3:0] value4bit;
always @(posedge clk)
begin
counter <= counter + 1'b1;
end
assign toptwo[1:0] = counter[18:17]; // (100*10^6 cycles/sec)/(2^17 cycles/refresh) = (763 refreshes/sec)
always @(*)
begin
case(toptwo[1:0])
2'b00:
begin
digitselect <= ~4'b0001;
value4bit <= A[3:0];
end
2'b01:
begin
digitselect <= ~4'b0010;
value4bit <= A[7:4];
end
2'b10:
begin
digitselect <= ~4'b0100;
value4bit <= A[11:8];
end
default:
begin
digitselect <= ~4'b1000;
value4bit <= A[15:12];
end
endcase
end
HexTo7Seg myhexencoder(value4bit, segments);
endmodule |
module HexTo7Seg(
input [3:0] A,
output reg [7:0] SevenSegValue
);
always @(*)
begin
case(A)
4'h0: SevenSegValue <= ~8'b11111100;
4'h1: SevenSegValue <= ~8'b01100000;
4'h2: SevenSegValue <= ~8'b11011010;
4'h3: SevenSegValue <= ~8'b11110010;
4'h4: SevenSegValue <= ~8'b01100110;
4'h5: SevenSegValue <= ~8'b10110110;
4'h6: SevenSegValue <= ~8'b10111110;
4'h7: SevenSegValue <= ~8'b11100000;
4'h8: SevenSegValue <= ~8'b11111110;
4'h9: SevenSegValue <= ~8'b11110110;
4'hA: SevenSegValue <= ~8'b11101110;
4'hB: SevenSegValue <= ~8'b00111110;
4'hC: SevenSegValue <= ~8'b10011100;
4'hD: SevenSegValue <= ~8'b01111010;
4'hE: SevenSegValue <= ~8'b10011110;
default: SevenSegValue <= ~8'b10001110;
endcase
end
endmodule |
module sky130_fd_sc_ls__einvn (
Z ,
A ,
TE_B
);
// Module ports
output Z ;
input A ;
input TE_B;
// Name Output Other arguments
notif0 notif00 (Z , A, TE_B );
endmodule |
module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outreadylatency_check ( .error(1'b1) );
end
endgenerate
nios_dut_mm_interconnect_0_avalon_st_adapter_004_error_adapter_0 error_adapter_0 (
.clk (in_clk_0_clk), // clk.clk
.reset_n (~in_rst_0_reset), // reset.reset_n
.in_data (in_0_data), // in.data
.in_valid (in_0_valid), // .valid
.in_ready (in_0_ready), // .ready
.out_data (out_0_data), // out.data
.out_valid (out_0_valid), // .valid
.out_ready (out_0_ready), // .ready
.out_error (out_0_error) // .error
);
endmodule |
module sky130_fd_sc_ms__sdlclkp (
//# {{scanchain|Scan Chain}}
input SCE ,
//# {{clocks|Clocking}}
input CLK ,
input GATE,
output GCLK,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule |
module ip_design_zed_audio_ctrl_0_0
(BCLK,
LRCLK,
SDATA_I,
SDATA_O,
S_AXI_ACLK,
S_AXI_ARESETN,
S_AXI_AWADDR,
S_AXI_AWVALID,
S_AXI_WDATA,
S_AXI_WSTRB,
S_AXI_WVALID,
S_AXI_BREADY,
S_AXI_ARADDR,
S_AXI_ARVALID,
S_AXI_RREADY,
S_AXI_ARREADY,
S_AXI_RDATA,
S_AXI_RRESP,
S_AXI_RVALID,
S_AXI_WREADY,
S_AXI_BRESP,
S_AXI_BVALID,
S_AXI_AWREADY);
output BCLK;
output LRCLK;
input SDATA_I;
output SDATA_O;
(* max_fanout = "10000" *) (* sigis = "Clk" *) (* x_interface_info = "xilinx.com:signal:clock:1.0 S_AXI_signal_clock CLK" *)
(* x_interface_parameter = "XIL_INTERFACENAME S_AXI_signal_clock, ASSOCIATED_BUSIF S_AXI, ASSOCIATED_RESET S_AXI_ARESETN, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN ip_design_processing_system7_0_0_FCLK_CLK0" *) input S_AXI_ACLK;
(* max_fanout = "10000" *) (* sigis = "Rst" *) (* x_interface_info = "xilinx.com:signal:reset:1.0 S_AXI_signal_reset RST" *)
(* x_interface_parameter = "XIL_INTERFACENAME S_AXI_signal_reset, POLARITY ACTIVE_LOW" *) input S_AXI_ARESETN;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *) (* x_interface_parameter = "XIL_INTERFACENAME S_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 0, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.000, CLK_DOMAIN ip_design_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0" *) input [31:0]S_AXI_AWADDR;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI AWVALID" *) input S_AXI_AWVALID;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI WDATA" *) input [31:0]S_AXI_WDATA;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI WSTRB" *) input [3:0]S_AXI_WSTRB;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI WVALID" *) input S_AXI_WVALID;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *) input S_AXI_BREADY;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI ARADDR" *) input [31:0]S_AXI_ARADDR;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI ARVALID" *) input S_AXI_ARVALID;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *) input S_AXI_RREADY;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI ARREADY" *) output S_AXI_ARREADY;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI RDATA" *) output [31:0]S_AXI_RDATA;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI RRESP" *) output [1:0]S_AXI_RRESP;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI RVALID" *) output S_AXI_RVALID;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *) output S_AXI_WREADY;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *) output [1:0]S_AXI_BRESP;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *) output S_AXI_BVALID;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI AWREADY" *) output S_AXI_AWREADY;
wire \<const0> ;
wire BCLK;
wire LRCLK;
wire SDATA_I;
wire SDATA_O;
(* MAX_FANOUT = "10000" *) (* RTL_MAX_FANOUT = "found" *) (* sigis = "Clk" *) wire S_AXI_ACLK;
wire [31:0]S_AXI_ARADDR;
(* MAX_FANOUT = "10000" *) (* RTL_MAX_FANOUT = "found" *) (* sigis = "Rst" *) wire S_AXI_ARESETN;
wire S_AXI_ARREADY;
wire S_AXI_ARVALID;
wire [31:0]S_AXI_AWADDR;
wire S_AXI_AWREADY;
wire S_AXI_AWVALID;
wire S_AXI_BREADY;
wire S_AXI_BVALID;
wire [31:0]S_AXI_RDATA;
wire S_AXI_RREADY;
wire S_AXI_RVALID;
wire [31:0]S_AXI_WDATA;
wire S_AXI_WVALID;
assign S_AXI_BRESP[1] = \<const0> ;
assign S_AXI_BRESP[0] = \<const0> ;
assign S_AXI_RRESP[1] = \<const0> ;
assign S_AXI_RRESP[0] = \<const0> ;
assign S_AXI_WREADY = S_AXI_AWREADY;
GND GND
(.G(\<const0> ));
ip_design_zed_audio_ctrl_0_0_i2s_ctrl U0
(.SDATA_I(SDATA_I),
.SDATA_O(SDATA_O),
.S_AXI_ACLK(S_AXI_ACLK),
.S_AXI_ARADDR(S_AXI_ARADDR[4:2]),
.S_AXI_ARESETN(S_AXI_ARESETN),
.S_AXI_ARREADY(S_AXI_ARREADY),
.S_AXI_ARVALID(S_AXI_ARVALID),
.S_AXI_AWADDR(S_AXI_AWADDR[4:2]),
.S_AXI_AWREADY(S_AXI_AWREADY),
.S_AXI_AWVALID(S_AXI_AWVALID),
.S_AXI_BREADY(S_AXI_BREADY),
.S_AXI_BVALID(S_AXI_BVALID),
.S_AXI_RDATA(S_AXI_RDATA),
.S_AXI_RREADY(S_AXI_RREADY),
.S_AXI_RVALID(S_AXI_RVALID),
.S_AXI_WDATA(S_AXI_WDATA),
.S_AXI_WVALID(S_AXI_WVALID),
.out({LRCLK,BCLK}));
endmodule |
module ip_design_zed_audio_ctrl_0_0_address_decoder
(\DataTx_R_reg[0] ,
\DataTx_R_reg[0]_0 ,
\DataTx_R_reg[0]_1 ,
\DataTx_R_reg[0]_2 ,
\DataTx_R_reg[0]_3 ,
\DataTx_R_reg[0]_4 ,
data_rdy_bit_reg,
D,
S_AXI_AWREADY,
S_AXI_ARREADY,
E,
\DataTx_L_reg[0] ,
data_rdy_bit_reg_0,
\s_axi_rdata_i_reg[31] ,
s_axi_rvalid_i_reg,
s_axi_bvalid_i_reg,
S_AXI_ACLK,
Q,
S_AXI_ARVALID,
s_axi_bvalid_i_reg_0,
\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] ,
S_AXI_WVALID_0,
\state_reg[1] ,
S_AXI_ARESETN,
S_AXI_ARADDR,
S_AXI_AWADDR,
S_AXI_AWVALID,
S_AXI_WVALID,
data_rdy_bit,
\DataTx_R_reg[31] ,
\DataTx_L_reg[31] ,
\DataRx_R_reg[23] ,
\DataRx_L_reg[23] ,
\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0 ,
S_AXI_RREADY,
s_axi_rvalid_i_reg_0,
S_AXI_BREADY,
s_axi_bvalid_i_reg_1);
output \DataTx_R_reg[0] ;
output \DataTx_R_reg[0]_0 ;
output \DataTx_R_reg[0]_1 ;
output \DataTx_R_reg[0]_2 ;
output \DataTx_R_reg[0]_3 ;
output \DataTx_R_reg[0]_4 ;
output data_rdy_bit_reg;
output [1:0]D;
output S_AXI_AWREADY;
output S_AXI_ARREADY;
output [0:0]E;
output [0:0]\DataTx_L_reg[0] ;
output data_rdy_bit_reg_0;
output [31:0]\s_axi_rdata_i_reg[31] ;
output s_axi_rvalid_i_reg;
output s_axi_bvalid_i_reg;
input S_AXI_ACLK;
input [1:0]Q;
input S_AXI_ARVALID;
input s_axi_bvalid_i_reg_0;
input [0:0]\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] ;
input S_AXI_WVALID_0;
input \state_reg[1] ;
input S_AXI_ARESETN;
input [2:0]S_AXI_ARADDR;
input [2:0]S_AXI_AWADDR;
input S_AXI_AWVALID;
input S_AXI_WVALID;
input data_rdy_bit;
input [31:0]\DataTx_R_reg[31] ;
input [31:0]\DataTx_L_reg[31] ;
input [23:0]\DataRx_R_reg[23] ;
input [23:0]\DataRx_L_reg[23] ;
input \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0 ;
input S_AXI_RREADY;
input s_axi_rvalid_i_reg_0;
input S_AXI_BREADY;
input s_axi_bvalid_i_reg_1;
wire Bus_RNW_reg_i_1_n_0;
wire [1:0]D;
wire [23:0]\DataRx_L_reg[23] ;
wire [23:0]\DataRx_R_reg[23] ;
wire [0:0]\DataTx_L_reg[0] ;
wire [31:0]\DataTx_L_reg[31] ;
wire \DataTx_R_reg[0] ;
wire \DataTx_R_reg[0]_0 ;
wire \DataTx_R_reg[0]_1 ;
wire \DataTx_R_reg[0]_2 ;
wire \DataTx_R_reg[0]_3 ;
wire \DataTx_R_reg[0]_4 ;
wire [31:0]\DataTx_R_reg[31] ;
wire [0:0]E;
wire \GEN_BKEND_CE_REGISTERS[3].ce_out_i[3]_i_2_n_0 ;
wire \GEN_BKEND_CE_REGISTERS[3].ce_out_i[3]_i_3_n_0 ;
wire \GEN_BKEND_CE_REGISTERS[4].ce_out_i[4]_i_4_n_0 ;
wire \GEN_BKEND_CE_REGISTERS[4].ce_out_i[4]_i_5_n_0 ;
wire \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0 ;
wire [0:0]\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] ;
wire [1:0]Q;
wire S_AXI_ACLK;
wire [2:0]S_AXI_ARADDR;
wire S_AXI_ARESETN;
wire S_AXI_ARREADY;
wire S_AXI_ARREADY_INST_0_i_1_n_0;
wire S_AXI_ARVALID;
wire [2:0]S_AXI_AWADDR;
wire S_AXI_AWREADY;
wire S_AXI_AWVALID;
wire S_AXI_BREADY;
wire S_AXI_RREADY;
wire S_AXI_WVALID;
wire S_AXI_WVALID_0;
wire ce_expnd_i_0;
wire ce_expnd_i_1;
wire ce_expnd_i_2;
wire ce_expnd_i_3;
wire ce_expnd_i_4;
wire cs_ce_clr;
wire data_rdy_bit;
wire data_rdy_bit_reg;
wire data_rdy_bit_reg_0;
wire s_axi_bvalid_i0;
wire s_axi_bvalid_i_reg;
wire s_axi_bvalid_i_reg_0;
wire s_axi_bvalid_i_reg_1;
wire \s_axi_rdata_i[0]_i_2_n_0 ;
wire \s_axi_rdata_i[0]_i_3_n_0 ;
wire \s_axi_rdata_i[0]_i_4_n_0 ;
wire \s_axi_rdata_i[10]_i_2_n_0 ;
wire \s_axi_rdata_i[11]_i_2_n_0 ;
wire \s_axi_rdata_i[12]_i_2_n_0 ;
wire \s_axi_rdata_i[13]_i_2_n_0 ;
wire \s_axi_rdata_i[14]_i_2_n_0 ;
wire \s_axi_rdata_i[15]_i_2_n_0 ;
wire \s_axi_rdata_i[16]_i_2_n_0 ;
wire \s_axi_rdata_i[17]_i_2_n_0 ;
wire \s_axi_rdata_i[18]_i_2_n_0 ;
wire \s_axi_rdata_i[19]_i_2_n_0 ;
wire \s_axi_rdata_i[1]_i_2_n_0 ;
wire \s_axi_rdata_i[20]_i_2_n_0 ;
wire \s_axi_rdata_i[21]_i_2_n_0 ;
wire \s_axi_rdata_i[22]_i_2_n_0 ;
wire \s_axi_rdata_i[23]_i_2_n_0 ;
wire \s_axi_rdata_i[23]_i_3_n_0 ;
wire \s_axi_rdata_i[23]_i_4_n_0 ;
wire \s_axi_rdata_i[2]_i_2_n_0 ;
wire \s_axi_rdata_i[3]_i_2_n_0 ;
wire \s_axi_rdata_i[4]_i_2_n_0 ;
wire \s_axi_rdata_i[5]_i_2_n_0 ;
wire \s_axi_rdata_i[6]_i_2_n_0 ;
wire \s_axi_rdata_i[7]_i_2_n_0 ;
wire \s_axi_rdata_i[8]_i_2_n_0 ;
wire \s_axi_rdata_i[9]_i_2_n_0 ;
wire [31:0]\s_axi_rdata_i_reg[31] ;
wire s_axi_rvalid_i0;
wire s_axi_rvalid_i_reg;
wire s_axi_rvalid_i_reg_0;
wire start;
wire \state_reg[1] ;
LUT6 #(
.INIT(64'hFEFFFFFF02020202))
Bus_RNW_reg_i_1
(.I0(S_AXI_ARVALID),
.I1(Q[0]),
.I2(Q[1]),
.I3(S_AXI_AWVALID),
.I4(S_AXI_WVALID),
.I5(\DataTx_R_reg[0]_4 ),
.O(Bus_RNW_reg_i_1_n_0));
FDRE Bus_RNW_reg_reg
(.C(S_AXI_ACLK),
.CE(1'b1),
.D(Bus_RNW_reg_i_1_n_0),
.Q(\DataTx_R_reg[0]_4 ),
.R(1'b0));
LUT6 #(
.INIT(64'h0000000000000004))
\DataTx_L[31]_i_1
(.I0(\DataTx_R_reg[0]_0 ),
.I1(\DataTx_R_reg[0]_1 ),
.I2(\DataTx_R_reg[0]_4 ),
.I3(\DataTx_R_reg[0]_2 ),
.I4(\DataTx_R_reg[0]_3 ),
.I5(\DataTx_R_reg[0] ),
.O(\DataTx_L_reg[0] ));
LUT6 #(
.INIT(64'h0000000000000004))
\DataTx_R[31]_i_1
(.I0(\DataTx_R_reg[0]_1 ),
.I1(\DataTx_R_reg[0]_0 ),
.I2(\DataTx_R_reg[0]_4 ),
.I3(\DataTx_R_reg[0]_2 ),
.I4(\DataTx_R_reg[0]_3 ),
.I5(\DataTx_R_reg[0] ),
.O(E));
LUT6 #(
.INIT(64'h020202020202FF02))
\GEN_BKEND_CE_REGISTERS[0].ce_out_i[0]_i_1
(.I0(\GEN_BKEND_CE_REGISTERS[3].ce_out_i[3]_i_2_n_0 ),
.I1(S_AXI_ARADDR[0]),
.I2(S_AXI_ARADDR[1]),
.I3(\GEN_BKEND_CE_REGISTERS[3].ce_out_i[3]_i_3_n_0 ),
.I4(S_AXI_AWADDR[0]),
.I5(S_AXI_AWADDR[1]),
.O(ce_expnd_i_4));
FDRE \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]
(.C(S_AXI_ACLK),
.CE(start),
.D(ce_expnd_i_4),
.Q(\DataTx_R_reg[0]_3 ),
.R(cs_ce_clr));
LUT6 #(
.INIT(64'h08080808FF080808))
\GEN_BKEND_CE_REGISTERS[1].ce_out_i[1]_i_1
(.I0(\GEN_BKEND_CE_REGISTERS[3].ce_out_i[3]_i_2_n_0 ),
.I1(S_AXI_ARADDR[0]),
.I2(S_AXI_ARADDR[1]),
.I3(\GEN_BKEND_CE_REGISTERS[3].ce_out_i[3]_i_3_n_0 ),
.I4(S_AXI_AWADDR[0]),
.I5(S_AXI_AWADDR[1]),
.O(ce_expnd_i_3));
FDRE \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]
(.C(S_AXI_ACLK),
.CE(start),
.D(ce_expnd_i_3),
.Q(\DataTx_R_reg[0]_2 ),
.R(cs_ce_clr));
LUT6 #(
.INIT(64'h08080808FF080808))
\GEN_BKEND_CE_REGISTERS[2].ce_out_i[2]_i_1
(.I0(\GEN_BKEND_CE_REGISTERS[3].ce_out_i[3]_i_2_n_0 ),
.I1(S_AXI_ARADDR[1]),
.I2(S_AXI_ARADDR[0]),
.I3(\GEN_BKEND_CE_REGISTERS[3].ce_out_i[3]_i_3_n_0 ),
.I4(S_AXI_AWADDR[1]),
.I5(S_AXI_AWADDR[0]),
.O(ce_expnd_i_2));
FDRE \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]
(.C(S_AXI_ACLK),
.CE(start),
.D(ce_expnd_i_2),
.Q(\DataTx_R_reg[0]_1 ),
.R(cs_ce_clr));
LUT6 #(
.INIT(64'hFF80808080808080))
\GEN_BKEND_CE_REGISTERS[3].ce_out_i[3]_i_1
(.I0(\GEN_BKEND_CE_REGISTERS[3].ce_out_i[3]_i_2_n_0 ),
.I1(S_AXI_ARADDR[0]),
.I2(S_AXI_ARADDR[1]),
.I3(\GEN_BKEND_CE_REGISTERS[3].ce_out_i[3]_i_3_n_0 ),
.I4(S_AXI_AWADDR[0]),
.I5(S_AXI_AWADDR[1]),
.O(ce_expnd_i_1));
LUT4 #(
.INIT(16'h0002))
\GEN_BKEND_CE_REGISTERS[3].ce_out_i[3]_i_2
(.I0(S_AXI_ARVALID),
.I1(Q[0]),
.I2(Q[1]),
.I3(S_AXI_ARADDR[2]),
.O(\GEN_BKEND_CE_REGISTERS[3].ce_out_i[3]_i_2_n_0 ));
LUT6 #(
.INIT(64'h0000000000000040))
\GEN_BKEND_CE_REGISTERS[3].ce_out_i[3]_i_3
(.I0(S_AXI_ARVALID),
.I1(S_AXI_WVALID),
.I2(S_AXI_AWVALID),
.I3(Q[1]),
.I4(Q[0]),
.I5(S_AXI_AWADDR[2]),
.O(\GEN_BKEND_CE_REGISTERS[3].ce_out_i[3]_i_3_n_0 ));
FDRE \GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg[3]
(.C(S_AXI_ACLK),
.CE(start),
.D(ce_expnd_i_1),
.Q(\DataTx_R_reg[0]_0 ),
.R(cs_ce_clr));
LUT3 #(
.INIT(8'hFD))
\GEN_BKEND_CE_REGISTERS[4].ce_out_i[4]_i_1
(.I0(S_AXI_ARESETN),
.I1(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] ),
.I2(S_AXI_ARREADY_INST_0_i_1_n_0),
.O(cs_ce_clr));
LUT5 #(
.INIT(32'h03020202))
\GEN_BKEND_CE_REGISTERS[4].ce_out_i[4]_i_2
(.I0(S_AXI_ARVALID),
.I1(Q[0]),
.I2(Q[1]),
.I3(S_AXI_AWVALID),
.I4(S_AXI_WVALID),
.O(start));
LUT5 #(
.INIT(32'hAAAAAEAA))
\GEN_BKEND_CE_REGISTERS[4].ce_out_i[4]_i_3
(.I0(\GEN_BKEND_CE_REGISTERS[4].ce_out_i[4]_i_4_n_0 ),
.I1(\GEN_BKEND_CE_REGISTERS[4].ce_out_i[4]_i_5_n_0 ),
.I2(S_AXI_AWADDR[1]),
.I3(S_AXI_AWADDR[2]),
.I4(S_AXI_AWADDR[0]),
.O(ce_expnd_i_0));
LUT6 #(
.INIT(64'h0000000000000400))
\GEN_BKEND_CE_REGISTERS[4].ce_out_i[4]_i_4
(.I0(S_AXI_ARADDR[0]),
.I1(S_AXI_ARADDR[2]),
.I2(S_AXI_ARADDR[1]),
.I3(S_AXI_ARVALID),
.I4(Q[0]),
.I5(Q[1]),
.O(\GEN_BKEND_CE_REGISTERS[4].ce_out_i[4]_i_4_n_0 ));
LUT5 #(
.INIT(32'h00001000))
\GEN_BKEND_CE_REGISTERS[4].ce_out_i[4]_i_5
(.I0(Q[0]),
.I1(Q[1]),
.I2(S_AXI_AWVALID),
.I3(S_AXI_WVALID),
.I4(S_AXI_ARVALID),
.O(\GEN_BKEND_CE_REGISTERS[4].ce_out_i[4]_i_5_n_0 ));
FDRE \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]
(.C(S_AXI_ACLK),
.CE(start),
.D(ce_expnd_i_0),
.Q(\DataTx_R_reg[0] ),
.R(cs_ce_clr));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT3 #(
.INIT(8'hF8))
S_AXI_ARREADY_INST_0
(.I0(\DataTx_R_reg[0]_4 ),
.I1(S_AXI_ARREADY_INST_0_i_1_n_0),
.I2(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] ),
.O(S_AXI_ARREADY));
LUT5 #(
.INIT(32'hFFFFFFFE))
S_AXI_ARREADY_INST_0_i_1
(.I0(\DataTx_R_reg[0] ),
.I1(\DataTx_R_reg[0]_3 ),
.I2(\DataTx_R_reg[0]_2 ),
.I3(\DataTx_R_reg[0]_0 ),
.I4(\DataTx_R_reg[0]_1 ),
.O(S_AXI_ARREADY_INST_0_i_1_n_0));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT3 #(
.INIT(8'hF4))
S_AXI_AWREADY_INST_0
(.I0(\DataTx_R_reg[0]_4 ),
.I1(S_AXI_ARREADY_INST_0_i_1_n_0),
.I2(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] ),
.O(S_AXI_AWREADY));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT4 #(
.INIT(16'hFFFE))
data_rdy_bit_i_2
(.I0(\DataTx_R_reg[0] ),
.I1(\DataTx_R_reg[0]_3 ),
.I2(\DataTx_R_reg[0]_2 ),
.I3(\DataTx_R_reg[0]_4 ),
.O(data_rdy_bit_reg_0));
LUT6 #(
.INIT(64'hFFFFFFFFFFFEFFFF))
data_rdy_bit_i_3
(.I0(\DataTx_R_reg[0]_3 ),
.I1(\DataTx_R_reg[0]_2 ),
.I2(\DataTx_R_reg[0]_1 ),
.I3(\DataTx_R_reg[0]_0 ),
.I4(\DataTx_R_reg[0] ),
.I5(\DataTx_R_reg[0]_4 ),
.O(data_rdy_bit_reg));
LUT3 #(
.INIT(8'hBA))
s_axi_bvalid_i_i_1
(.I0(s_axi_bvalid_i0),
.I1(S_AXI_BREADY),
.I2(s_axi_bvalid_i_reg_1),
.O(s_axi_bvalid_i_reg));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT5 #(
.INIT(32'h0000AE00))
s_axi_bvalid_i_i_2
(.I0(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] ),
.I1(S_AXI_ARREADY_INST_0_i_1_n_0),
.I2(\DataTx_R_reg[0]_4 ),
.I3(Q[1]),
.I4(Q[0]),
.O(s_axi_bvalid_i0));
LUT6 #(
.INIT(64'hFFAAEAAAEAAAEAAA))
\s_axi_rdata_i[0]_i_1
(.I0(\s_axi_rdata_i[0]_i_2_n_0 ),
.I1(data_rdy_bit),
.I2(\DataTx_R_reg[0] ),
.I3(\s_axi_rdata_i[0]_i_3_n_0 ),
.I4(\DataTx_R_reg[0]_0 ),
.I5(\DataTx_R_reg[31] [0]),
.O(\s_axi_rdata_i_reg[31] [0]));
LUT6 #(
.INIT(64'hFFFFF888F888F888))
\s_axi_rdata_i[0]_i_2
(.I0(\s_axi_rdata_i[0]_i_4_n_0 ),
.I1(\DataTx_L_reg[31] [0]),
.I2(\s_axi_rdata_i[23]_i_3_n_0 ),
.I3(\DataRx_R_reg[23] [0]),
.I4(\DataRx_L_reg[23] [0]),
.I5(\s_axi_rdata_i[23]_i_2_n_0 ),
.O(\s_axi_rdata_i[0]_i_2_n_0 ));
LUT2 #(
.INIT(4'h8))
\s_axi_rdata_i[0]_i_3
(.I0(\DataTx_R_reg[0]_4 ),
.I1(\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0 ),
.O(\s_axi_rdata_i[0]_i_3_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT3 #(
.INIT(8'h80))
\s_axi_rdata_i[0]_i_4
(.I0(\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0 ),
.I1(\DataTx_R_reg[0]_4 ),
.I2(\DataTx_R_reg[0]_1 ),
.O(\s_axi_rdata_i[0]_i_4_n_0 ));
LUT5 #(
.INIT(32'hFFFFF888))
\s_axi_rdata_i[10]_i_1
(.I0(\DataRx_L_reg[23] [10]),
.I1(\s_axi_rdata_i[23]_i_2_n_0 ),
.I2(\s_axi_rdata_i[23]_i_3_n_0 ),
.I3(\DataRx_R_reg[23] [10]),
.I4(\s_axi_rdata_i[10]_i_2_n_0 ),
.O(\s_axi_rdata_i_reg[31] [10]));
LUT6 #(
.INIT(64'hF800000088000000))
\s_axi_rdata_i[10]_i_2
(.I0(\DataTx_L_reg[31] [10]),
.I1(\DataTx_R_reg[0]_1 ),
.I2(\DataTx_R_reg[31] [10]),
.I3(\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0 ),
.I4(\DataTx_R_reg[0]_4 ),
.I5(\DataTx_R_reg[0]_0 ),
.O(\s_axi_rdata_i[10]_i_2_n_0 ));
LUT5 #(
.INIT(32'hFFFFF888))
\s_axi_rdata_i[11]_i_1
(.I0(\DataRx_L_reg[23] [11]),
.I1(\s_axi_rdata_i[23]_i_2_n_0 ),
.I2(\s_axi_rdata_i[23]_i_3_n_0 ),
.I3(\DataRx_R_reg[23] [11]),
.I4(\s_axi_rdata_i[11]_i_2_n_0 ),
.O(\s_axi_rdata_i_reg[31] [11]));
LUT6 #(
.INIT(64'hF800000088000000))
\s_axi_rdata_i[11]_i_2
(.I0(\DataTx_L_reg[31] [11]),
.I1(\DataTx_R_reg[0]_1 ),
.I2(\DataTx_R_reg[31] [11]),
.I3(\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0 ),
.I4(\DataTx_R_reg[0]_4 ),
.I5(\DataTx_R_reg[0]_0 ),
.O(\s_axi_rdata_i[11]_i_2_n_0 ));
LUT5 #(
.INIT(32'hFFFFF888))
\s_axi_rdata_i[12]_i_1
(.I0(\DataRx_L_reg[23] [12]),
.I1(\s_axi_rdata_i[23]_i_2_n_0 ),
.I2(\s_axi_rdata_i[23]_i_3_n_0 ),
.I3(\DataRx_R_reg[23] [12]),
.I4(\s_axi_rdata_i[12]_i_2_n_0 ),
.O(\s_axi_rdata_i_reg[31] [12]));
LUT6 #(
.INIT(64'hF800000088000000))
\s_axi_rdata_i[12]_i_2
(.I0(\DataTx_L_reg[31] [12]),
.I1(\DataTx_R_reg[0]_1 ),
.I2(\DataTx_R_reg[31] [12]),
.I3(\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0 ),
.I4(\DataTx_R_reg[0]_4 ),
.I5(\DataTx_R_reg[0]_0 ),
.O(\s_axi_rdata_i[12]_i_2_n_0 ));
LUT5 #(
.INIT(32'hFFFFF888))
\s_axi_rdata_i[13]_i_1
(.I0(\DataRx_L_reg[23] [13]),
.I1(\s_axi_rdata_i[23]_i_2_n_0 ),
.I2(\s_axi_rdata_i[23]_i_3_n_0 ),
.I3(\DataRx_R_reg[23] [13]),
.I4(\s_axi_rdata_i[13]_i_2_n_0 ),
.O(\s_axi_rdata_i_reg[31] [13]));
LUT6 #(
.INIT(64'hF800000088000000))
\s_axi_rdata_i[13]_i_2
(.I0(\DataTx_L_reg[31] [13]),
.I1(\DataTx_R_reg[0]_1 ),
.I2(\DataTx_R_reg[31] [13]),
.I3(\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0 ),
.I4(\DataTx_R_reg[0]_4 ),
.I5(\DataTx_R_reg[0]_0 ),
.O(\s_axi_rdata_i[13]_i_2_n_0 ));
LUT5 #(
.INIT(32'hFFFFF888))
\s_axi_rdata_i[14]_i_1
(.I0(\DataRx_L_reg[23] [14]),
.I1(\s_axi_rdata_i[23]_i_2_n_0 ),
.I2(\s_axi_rdata_i[23]_i_3_n_0 ),
.I3(\DataRx_R_reg[23] [14]),
.I4(\s_axi_rdata_i[14]_i_2_n_0 ),
.O(\s_axi_rdata_i_reg[31] [14]));
LUT6 #(
.INIT(64'hF800000088000000))
\s_axi_rdata_i[14]_i_2
(.I0(\DataTx_L_reg[31] [14]),
.I1(\DataTx_R_reg[0]_1 ),
.I2(\DataTx_R_reg[31] [14]),
.I3(\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0 ),
.I4(\DataTx_R_reg[0]_4 ),
.I5(\DataTx_R_reg[0]_0 ),
.O(\s_axi_rdata_i[14]_i_2_n_0 ));
LUT5 #(
.INIT(32'hFFFFF888))
\s_axi_rdata_i[15]_i_1
(.I0(\DataRx_L_reg[23] [15]),
.I1(\s_axi_rdata_i[23]_i_2_n_0 ),
.I2(\s_axi_rdata_i[23]_i_3_n_0 ),
.I3(\DataRx_R_reg[23] [15]),
.I4(\s_axi_rdata_i[15]_i_2_n_0 ),
.O(\s_axi_rdata_i_reg[31] [15]));
LUT6 #(
.INIT(64'hF800000088000000))
\s_axi_rdata_i[15]_i_2
(.I0(\DataTx_L_reg[31] [15]),
.I1(\DataTx_R_reg[0]_1 ),
.I2(\DataTx_R_reg[31] [15]),
.I3(\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0 ),
.I4(\DataTx_R_reg[0]_4 ),
.I5(\DataTx_R_reg[0]_0 ),
.O(\s_axi_rdata_i[15]_i_2_n_0 ));
LUT5 #(
.INIT(32'hFFFFF888))
\s_axi_rdata_i[16]_i_1
(.I0(\DataRx_L_reg[23] [16]),
.I1(\s_axi_rdata_i[23]_i_2_n_0 ),
.I2(\s_axi_rdata_i[23]_i_3_n_0 ),
.I3(\DataRx_R_reg[23] [16]),
.I4(\s_axi_rdata_i[16]_i_2_n_0 ),
.O(\s_axi_rdata_i_reg[31] [16]));
LUT6 #(
.INIT(64'hF800000088000000))
\s_axi_rdata_i[16]_i_2
(.I0(\DataTx_L_reg[31] [16]),
.I1(\DataTx_R_reg[0]_1 ),
.I2(\DataTx_R_reg[31] [16]),
.I3(\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0 ),
.I4(\DataTx_R_reg[0]_4 ),
.I5(\DataTx_R_reg[0]_0 ),
.O(\s_axi_rdata_i[16]_i_2_n_0 ));
LUT5 #(
.INIT(32'hFFFFF888))
\s_axi_rdata_i[17]_i_1
(.I0(\DataRx_L_reg[23] [17]),
.I1(\s_axi_rdata_i[23]_i_2_n_0 ),
.I2(\s_axi_rdata_i[23]_i_3_n_0 ),
.I3(\DataRx_R_reg[23] [17]),
.I4(\s_axi_rdata_i[17]_i_2_n_0 ),
.O(\s_axi_rdata_i_reg[31] [17]));
LUT6 #(
.INIT(64'hF800000088000000))
\s_axi_rdata_i[17]_i_2
(.I0(\DataTx_L_reg[31] [17]),
.I1(\DataTx_R_reg[0]_1 ),
.I2(\DataTx_R_reg[31] [17]),
.I3(\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0 ),
.I4(\DataTx_R_reg[0]_4 ),
.I5(\DataTx_R_reg[0]_0 ),
.O(\s_axi_rdata_i[17]_i_2_n_0 ));
LUT5 #(
.INIT(32'hFFFFF888))
\s_axi_rdata_i[18]_i_1
(.I0(\DataRx_L_reg[23] [18]),
.I1(\s_axi_rdata_i[23]_i_2_n_0 ),
.I2(\s_axi_rdata_i[23]_i_3_n_0 ),
.I3(\DataRx_R_reg[23] [18]),
.I4(\s_axi_rdata_i[18]_i_2_n_0 ),
.O(\s_axi_rdata_i_reg[31] [18]));
LUT6 #(
.INIT(64'hF800000088000000))
\s_axi_rdata_i[18]_i_2
(.I0(\DataTx_L_reg[31] [18]),
.I1(\DataTx_R_reg[0]_1 ),
.I2(\DataTx_R_reg[31] [18]),
.I3(\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0 ),
.I4(\DataTx_R_reg[0]_4 ),
.I5(\DataTx_R_reg[0]_0 ),
.O(\s_axi_rdata_i[18]_i_2_n_0 ));
LUT5 #(
.INIT(32'hFFFFF888))
\s_axi_rdata_i[19]_i_1
(.I0(\DataRx_L_reg[23] [19]),
.I1(\s_axi_rdata_i[23]_i_2_n_0 ),
.I2(\s_axi_rdata_i[23]_i_3_n_0 ),
.I3(\DataRx_R_reg[23] [19]),
.I4(\s_axi_rdata_i[19]_i_2_n_0 ),
.O(\s_axi_rdata_i_reg[31] [19]));
LUT6 #(
.INIT(64'hF800000088000000))
\s_axi_rdata_i[19]_i_2
(.I0(\DataTx_L_reg[31] [19]),
.I1(\DataTx_R_reg[0]_1 ),
.I2(\DataTx_R_reg[31] [19]),
.I3(\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0 ),
.I4(\DataTx_R_reg[0]_4 ),
.I5(\DataTx_R_reg[0]_0 ),
.O(\s_axi_rdata_i[19]_i_2_n_0 ));
LUT5 #(
.INIT(32'hFFFFF888))
\s_axi_rdata_i[1]_i_1
(.I0(\DataRx_L_reg[23] [1]),
.I1(\s_axi_rdata_i[23]_i_2_n_0 ),
.I2(\s_axi_rdata_i[23]_i_3_n_0 ),
.I3(\DataRx_R_reg[23] [1]),
.I4(\s_axi_rdata_i[1]_i_2_n_0 ),
.O(\s_axi_rdata_i_reg[31] [1]));
LUT6 #(
.INIT(64'hF800000088000000))
\s_axi_rdata_i[1]_i_2
(.I0(\DataTx_L_reg[31] [1]),
.I1(\DataTx_R_reg[0]_1 ),
.I2(\DataTx_R_reg[31] [1]),
.I3(\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0 ),
.I4(\DataTx_R_reg[0]_4 ),
.I5(\DataTx_R_reg[0]_0 ),
.O(\s_axi_rdata_i[1]_i_2_n_0 ));
LUT5 #(
.INIT(32'hFFFFF888))
\s_axi_rdata_i[20]_i_1
(.I0(\DataRx_L_reg[23] [20]),
.I1(\s_axi_rdata_i[23]_i_2_n_0 ),
.I2(\s_axi_rdata_i[23]_i_3_n_0 ),
.I3(\DataRx_R_reg[23] [20]),
.I4(\s_axi_rdata_i[20]_i_2_n_0 ),
.O(\s_axi_rdata_i_reg[31] [20]));
LUT6 #(
.INIT(64'hF800000088000000))
\s_axi_rdata_i[20]_i_2
(.I0(\DataTx_L_reg[31] [20]),
.I1(\DataTx_R_reg[0]_1 ),
.I2(\DataTx_R_reg[31] [20]),
.I3(\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0 ),
.I4(\DataTx_R_reg[0]_4 ),
.I5(\DataTx_R_reg[0]_0 ),
.O(\s_axi_rdata_i[20]_i_2_n_0 ));
LUT5 #(
.INIT(32'hFFFFF888))
\s_axi_rdata_i[21]_i_1
(.I0(\DataRx_L_reg[23] [21]),
.I1(\s_axi_rdata_i[23]_i_2_n_0 ),
.I2(\s_axi_rdata_i[23]_i_3_n_0 ),
.I3(\DataRx_R_reg[23] [21]),
.I4(\s_axi_rdata_i[21]_i_2_n_0 ),
.O(\s_axi_rdata_i_reg[31] [21]));
LUT6 #(
.INIT(64'hF800000088000000))
\s_axi_rdata_i[21]_i_2
(.I0(\DataTx_L_reg[31] [21]),
.I1(\DataTx_R_reg[0]_1 ),
.I2(\DataTx_R_reg[31] [21]),
.I3(\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0 ),
.I4(\DataTx_R_reg[0]_4 ),
.I5(\DataTx_R_reg[0]_0 ),
.O(\s_axi_rdata_i[21]_i_2_n_0 ));
LUT5 #(
.INIT(32'hFFFFF888))
\s_axi_rdata_i[22]_i_1
(.I0(\DataRx_L_reg[23] [22]),
.I1(\s_axi_rdata_i[23]_i_2_n_0 ),
.I2(\s_axi_rdata_i[23]_i_3_n_0 ),
.I3(\DataRx_R_reg[23] [22]),
.I4(\s_axi_rdata_i[22]_i_2_n_0 ),
.O(\s_axi_rdata_i_reg[31] [22]));
LUT6 #(
.INIT(64'hF800000088000000))
\s_axi_rdata_i[22]_i_2
(.I0(\DataTx_L_reg[31] [22]),
.I1(\DataTx_R_reg[0]_1 ),
.I2(\DataTx_R_reg[31] [22]),
.I3(\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0 ),
.I4(\DataTx_R_reg[0]_4 ),
.I5(\DataTx_R_reg[0]_0 ),
.O(\s_axi_rdata_i[22]_i_2_n_0 ));
LUT5 #(
.INIT(32'hFFFFF888))
\s_axi_rdata_i[23]_i_1
(.I0(\DataRx_L_reg[23] [23]),
.I1(\s_axi_rdata_i[23]_i_2_n_0 ),
.I2(\s_axi_rdata_i[23]_i_3_n_0 ),
.I3(\DataRx_R_reg[23] [23]),
.I4(\s_axi_rdata_i[23]_i_4_n_0 ),
.O(\s_axi_rdata_i_reg[31] [23]));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT3 #(
.INIT(8'h80))
\s_axi_rdata_i[23]_i_2
(.I0(\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0 ),
.I1(\DataTx_R_reg[0]_4 ),
.I2(\DataTx_R_reg[0]_3 ),
.O(\s_axi_rdata_i[23]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT3 #(
.INIT(8'h80))
\s_axi_rdata_i[23]_i_3
(.I0(\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0 ),
.I1(\DataTx_R_reg[0]_4 ),
.I2(\DataTx_R_reg[0]_2 ),
.O(\s_axi_rdata_i[23]_i_3_n_0 ));
LUT6 #(
.INIT(64'hF800000088000000))
\s_axi_rdata_i[23]_i_4
(.I0(\DataTx_L_reg[31] [23]),
.I1(\DataTx_R_reg[0]_1 ),
.I2(\DataTx_R_reg[31] [23]),
.I3(\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0 ),
.I4(\DataTx_R_reg[0]_4 ),
.I5(\DataTx_R_reg[0]_0 ),
.O(\s_axi_rdata_i[23]_i_4_n_0 ));
LUT6 #(
.INIT(64'hF800000088000000))
\s_axi_rdata_i[24]_i_1
(.I0(\DataTx_L_reg[31] [24]),
.I1(\DataTx_R_reg[0]_1 ),
.I2(\DataTx_R_reg[31] [24]),
.I3(\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0 ),
.I4(\DataTx_R_reg[0]_4 ),
.I5(\DataTx_R_reg[0]_0 ),
.O(\s_axi_rdata_i_reg[31] [24]));
LUT6 #(
.INIT(64'hF800000088000000))
\s_axi_rdata_i[25]_i_1
(.I0(\DataTx_L_reg[31] [25]),
.I1(\DataTx_R_reg[0]_1 ),
.I2(\DataTx_R_reg[31] [25]),
.I3(\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0 ),
.I4(\DataTx_R_reg[0]_4 ),
.I5(\DataTx_R_reg[0]_0 ),
.O(\s_axi_rdata_i_reg[31] [25]));
LUT6 #(
.INIT(64'hF800000088000000))
\s_axi_rdata_i[26]_i_1
(.I0(\DataTx_L_reg[31] [26]),
.I1(\DataTx_R_reg[0]_1 ),
.I2(\DataTx_R_reg[31] [26]),
.I3(\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0 ),
.I4(\DataTx_R_reg[0]_4 ),
.I5(\DataTx_R_reg[0]_0 ),
.O(\s_axi_rdata_i_reg[31] [26]));
LUT6 #(
.INIT(64'hF800000088000000))
\s_axi_rdata_i[27]_i_1
(.I0(\DataTx_L_reg[31] [27]),
.I1(\DataTx_R_reg[0]_1 ),
.I2(\DataTx_R_reg[31] [27]),
.I3(\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0 ),
.I4(\DataTx_R_reg[0]_4 ),
.I5(\DataTx_R_reg[0]_0 ),
.O(\s_axi_rdata_i_reg[31] [27]));
LUT6 #(
.INIT(64'hF800000088000000))
\s_axi_rdata_i[28]_i_1
(.I0(\DataTx_L_reg[31] [28]),
.I1(\DataTx_R_reg[0]_1 ),
.I2(\DataTx_R_reg[31] [28]),
.I3(\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0 ),
.I4(\DataTx_R_reg[0]_4 ),
.I5(\DataTx_R_reg[0]_0 ),
.O(\s_axi_rdata_i_reg[31] [28]));
LUT6 #(
.INIT(64'hF800000088000000))
\s_axi_rdata_i[29]_i_1
(.I0(\DataTx_L_reg[31] [29]),
.I1(\DataTx_R_reg[0]_1 ),
.I2(\DataTx_R_reg[31] [29]),
.I3(\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0 ),
.I4(\DataTx_R_reg[0]_4 ),
.I5(\DataTx_R_reg[0]_0 ),
.O(\s_axi_rdata_i_reg[31] [29]));
LUT5 #(
.INIT(32'hFFFFF888))
\s_axi_rdata_i[2]_i_1
(.I0(\DataRx_L_reg[23] [2]),
.I1(\s_axi_rdata_i[23]_i_2_n_0 ),
.I2(\s_axi_rdata_i[23]_i_3_n_0 ),
.I3(\DataRx_R_reg[23] [2]),
.I4(\s_axi_rdata_i[2]_i_2_n_0 ),
.O(\s_axi_rdata_i_reg[31] [2]));
LUT6 #(
.INIT(64'hF800000088000000))
\s_axi_rdata_i[2]_i_2
(.I0(\DataTx_L_reg[31] [2]),
.I1(\DataTx_R_reg[0]_1 ),
.I2(\DataTx_R_reg[31] [2]),
.I3(\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0 ),
.I4(\DataTx_R_reg[0]_4 ),
.I5(\DataTx_R_reg[0]_0 ),
.O(\s_axi_rdata_i[2]_i_2_n_0 ));
LUT6 #(
.INIT(64'hF800000088000000))
\s_axi_rdata_i[30]_i_1
(.I0(\DataTx_L_reg[31] [30]),
.I1(\DataTx_R_reg[0]_1 ),
.I2(\DataTx_R_reg[31] [30]),
.I3(\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0 ),
.I4(\DataTx_R_reg[0]_4 ),
.I5(\DataTx_R_reg[0]_0 ),
.O(\s_axi_rdata_i_reg[31] [30]));
LUT6 #(
.INIT(64'hF800000088000000))
\s_axi_rdata_i[31]_i_2
(.I0(\DataTx_L_reg[31] [31]),
.I1(\DataTx_R_reg[0]_1 ),
.I2(\DataTx_R_reg[31] [31]),
.I3(\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0 ),
.I4(\DataTx_R_reg[0]_4 ),
.I5(\DataTx_R_reg[0]_0 ),
.O(\s_axi_rdata_i_reg[31] [31]));
LUT5 #(
.INIT(32'hFFFFF888))
\s_axi_rdata_i[3]_i_1
(.I0(\DataRx_L_reg[23] [3]),
.I1(\s_axi_rdata_i[23]_i_2_n_0 ),
.I2(\s_axi_rdata_i[23]_i_3_n_0 ),
.I3(\DataRx_R_reg[23] [3]),
.I4(\s_axi_rdata_i[3]_i_2_n_0 ),
.O(\s_axi_rdata_i_reg[31] [3]));
LUT6 #(
.INIT(64'hF800000088000000))
\s_axi_rdata_i[3]_i_2
(.I0(\DataTx_L_reg[31] [3]),
.I1(\DataTx_R_reg[0]_1 ),
.I2(\DataTx_R_reg[31] [3]),
.I3(\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0 ),
.I4(\DataTx_R_reg[0]_4 ),
.I5(\DataTx_R_reg[0]_0 ),
.O(\s_axi_rdata_i[3]_i_2_n_0 ));
LUT5 #(
.INIT(32'hFFFFF888))
\s_axi_rdata_i[4]_i_1
(.I0(\DataRx_L_reg[23] [4]),
.I1(\s_axi_rdata_i[23]_i_2_n_0 ),
.I2(\s_axi_rdata_i[23]_i_3_n_0 ),
.I3(\DataRx_R_reg[23] [4]),
.I4(\s_axi_rdata_i[4]_i_2_n_0 ),
.O(\s_axi_rdata_i_reg[31] [4]));
LUT6 #(
.INIT(64'hF800000088000000))
\s_axi_rdata_i[4]_i_2
(.I0(\DataTx_L_reg[31] [4]),
.I1(\DataTx_R_reg[0]_1 ),
.I2(\DataTx_R_reg[31] [4]),
.I3(\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0 ),
.I4(\DataTx_R_reg[0]_4 ),
.I5(\DataTx_R_reg[0]_0 ),
.O(\s_axi_rdata_i[4]_i_2_n_0 ));
LUT5 #(
.INIT(32'hFFFFF888))
\s_axi_rdata_i[5]_i_1
(.I0(\DataRx_L_reg[23] [5]),
.I1(\s_axi_rdata_i[23]_i_2_n_0 ),
.I2(\s_axi_rdata_i[23]_i_3_n_0 ),
.I3(\DataRx_R_reg[23] [5]),
.I4(\s_axi_rdata_i[5]_i_2_n_0 ),
.O(\s_axi_rdata_i_reg[31] [5]));
LUT6 #(
.INIT(64'hF800000088000000))
\s_axi_rdata_i[5]_i_2
(.I0(\DataTx_L_reg[31] [5]),
.I1(\DataTx_R_reg[0]_1 ),
.I2(\DataTx_R_reg[31] [5]),
.I3(\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0 ),
.I4(\DataTx_R_reg[0]_4 ),
.I5(\DataTx_R_reg[0]_0 ),
.O(\s_axi_rdata_i[5]_i_2_n_0 ));
LUT5 #(
.INIT(32'hFFFFF888))
\s_axi_rdata_i[6]_i_1
(.I0(\DataRx_L_reg[23] [6]),
.I1(\s_axi_rdata_i[23]_i_2_n_0 ),
.I2(\s_axi_rdata_i[23]_i_3_n_0 ),
.I3(\DataRx_R_reg[23] [6]),
.I4(\s_axi_rdata_i[6]_i_2_n_0 ),
.O(\s_axi_rdata_i_reg[31] [6]));
LUT6 #(
.INIT(64'hF800000088000000))
\s_axi_rdata_i[6]_i_2
(.I0(\DataTx_L_reg[31] [6]),
.I1(\DataTx_R_reg[0]_1 ),
.I2(\DataTx_R_reg[31] [6]),
.I3(\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0 ),
.I4(\DataTx_R_reg[0]_4 ),
.I5(\DataTx_R_reg[0]_0 ),
.O(\s_axi_rdata_i[6]_i_2_n_0 ));
LUT5 #(
.INIT(32'hFFFFF888))
\s_axi_rdata_i[7]_i_1
(.I0(\DataRx_L_reg[23] [7]),
.I1(\s_axi_rdata_i[23]_i_2_n_0 ),
.I2(\s_axi_rdata_i[23]_i_3_n_0 ),
.I3(\DataRx_R_reg[23] [7]),
.I4(\s_axi_rdata_i[7]_i_2_n_0 ),
.O(\s_axi_rdata_i_reg[31] [7]));
LUT6 #(
.INIT(64'hF800000088000000))
\s_axi_rdata_i[7]_i_2
(.I0(\DataTx_L_reg[31] [7]),
.I1(\DataTx_R_reg[0]_1 ),
.I2(\DataTx_R_reg[31] [7]),
.I3(\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0 ),
.I4(\DataTx_R_reg[0]_4 ),
.I5(\DataTx_R_reg[0]_0 ),
.O(\s_axi_rdata_i[7]_i_2_n_0 ));
LUT5 #(
.INIT(32'hFFFFF888))
\s_axi_rdata_i[8]_i_1
(.I0(\DataRx_L_reg[23] [8]),
.I1(\s_axi_rdata_i[23]_i_2_n_0 ),
.I2(\s_axi_rdata_i[23]_i_3_n_0 ),
.I3(\DataRx_R_reg[23] [8]),
.I4(\s_axi_rdata_i[8]_i_2_n_0 ),
.O(\s_axi_rdata_i_reg[31] [8]));
LUT6 #(
.INIT(64'hF800000088000000))
\s_axi_rdata_i[8]_i_2
(.I0(\DataTx_L_reg[31] [8]),
.I1(\DataTx_R_reg[0]_1 ),
.I2(\DataTx_R_reg[31] [8]),
.I3(\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0 ),
.I4(\DataTx_R_reg[0]_4 ),
.I5(\DataTx_R_reg[0]_0 ),
.O(\s_axi_rdata_i[8]_i_2_n_0 ));
LUT5 #(
.INIT(32'hFFFFF888))
\s_axi_rdata_i[9]_i_1
(.I0(\DataRx_L_reg[23] [9]),
.I1(\s_axi_rdata_i[23]_i_2_n_0 ),
.I2(\s_axi_rdata_i[23]_i_3_n_0 ),
.I3(\DataRx_R_reg[23] [9]),
.I4(\s_axi_rdata_i[9]_i_2_n_0 ),
.O(\s_axi_rdata_i_reg[31] [9]));
LUT6 #(
.INIT(64'hF800000088000000))
\s_axi_rdata_i[9]_i_2
(.I0(\DataTx_L_reg[31] [9]),
.I1(\DataTx_R_reg[0]_1 ),
.I2(\DataTx_R_reg[31] [9]),
.I3(\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0 ),
.I4(\DataTx_R_reg[0]_4 ),
.I5(\DataTx_R_reg[0]_0 ),
.O(\s_axi_rdata_i[9]_i_2_n_0 ));
LUT3 #(
.INIT(8'hBA))
s_axi_rvalid_i_i_1
(.I0(s_axi_rvalid_i0),
.I1(S_AXI_RREADY),
.I2(s_axi_rvalid_i_reg_0),
.O(s_axi_rvalid_i_reg));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT5 #(
.INIT(32'h0000EA00))
s_axi_rvalid_i_i_2
(.I0(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] ),
.I1(S_AXI_ARREADY_INST_0_i_1_n_0),
.I2(\DataTx_R_reg[0]_4 ),
.I3(Q[0]),
.I4(Q[1]),
.O(s_axi_rvalid_i0));
LUT4 #(
.INIT(16'hFFF4))
\state[0]_i_1
(.I0(Q[1]),
.I1(S_AXI_ARVALID),
.I2(s_axi_bvalid_i0),
.I3(s_axi_bvalid_i_reg_0),
.O(D[0]));
LUT6 #(
.INIT(64'hFFFFFFFFFFFF4454))
\state[1]_i_1
(.I0(Q[0]),
.I1(Q[1]),
.I2(S_AXI_WVALID_0),
.I3(S_AXI_ARVALID),
.I4(\state_reg[1] ),
.I5(s_axi_rvalid_i0),
.O(D[1]));
endmodule |
module ip_design_zed_audio_ctrl_0_0_axi_lite_ipif
(\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg ,
\GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg ,
\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg ,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg ,
\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg ,
Bus_RNW_reg,
S_AXI_RVALID,
S_AXI_BVALID,
data_rdy_bit_reg,
S_AXI_AWREADY,
S_AXI_ARREADY,
E,
\DataTx_L_reg[0] ,
data_rdy_bit_reg_0,
S_AXI_RDATA,
S_AXI_ACLK,
SR,
S_AXI_ARVALID,
S_AXI_ARESETN,
S_AXI_BREADY,
S_AXI_RREADY,
S_AXI_ARADDR,
S_AXI_AWADDR,
S_AXI_AWVALID,
S_AXI_WVALID,
data_rdy_bit,
Q,
\DataTx_L_reg[31] ,
\DataRx_R_reg[23] ,
\DataRx_L_reg[23] ,
\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4] );
output \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg ;
output \GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg ;
output \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg ;
output \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg ;
output \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg ;
output Bus_RNW_reg;
output S_AXI_RVALID;
output S_AXI_BVALID;
output data_rdy_bit_reg;
output S_AXI_AWREADY;
output S_AXI_ARREADY;
output [0:0]E;
output [0:0]\DataTx_L_reg[0] ;
output data_rdy_bit_reg_0;
output [31:0]S_AXI_RDATA;
input S_AXI_ACLK;
input [0:0]SR;
input S_AXI_ARVALID;
input S_AXI_ARESETN;
input S_AXI_BREADY;
input S_AXI_RREADY;
input [2:0]S_AXI_ARADDR;
input [2:0]S_AXI_AWADDR;
input S_AXI_AWVALID;
input S_AXI_WVALID;
input data_rdy_bit;
input [31:0]Q;
input [31:0]\DataTx_L_reg[31] ;
input [23:0]\DataRx_R_reg[23] ;
input [23:0]\DataRx_L_reg[23] ;
input \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4] ;
wire Bus_RNW_reg;
wire [23:0]\DataRx_L_reg[23] ;
wire [23:0]\DataRx_R_reg[23] ;
wire [0:0]\DataTx_L_reg[0] ;
wire [31:0]\DataTx_L_reg[31] ;
wire [0:0]E;
wire \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg ;
wire \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg ;
wire \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg ;
wire \GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg ;
wire \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg ;
wire \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4] ;
wire [31:0]Q;
wire [0:0]SR;
wire S_AXI_ACLK;
wire [2:0]S_AXI_ARADDR;
wire S_AXI_ARESETN;
wire S_AXI_ARREADY;
wire S_AXI_ARVALID;
wire [2:0]S_AXI_AWADDR;
wire S_AXI_AWREADY;
wire S_AXI_AWVALID;
wire S_AXI_BREADY;
wire S_AXI_BVALID;
wire [31:0]S_AXI_RDATA;
wire S_AXI_RREADY;
wire S_AXI_RVALID;
wire S_AXI_WVALID;
wire data_rdy_bit;
wire data_rdy_bit_reg;
wire data_rdy_bit_reg_0;
ip_design_zed_audio_ctrl_0_0_slave_attachment I_SLAVE_ATTACHMENT
(.\DataRx_L_reg[23] (\DataRx_L_reg[23] ),
.\DataRx_R_reg[23] (\DataRx_R_reg[23] ),
.\DataTx_L_reg[0] (\DataTx_L_reg[0] ),
.\DataTx_L_reg[31] (\DataTx_L_reg[31] ),
.\DataTx_R_reg[0] (\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg ),
.\DataTx_R_reg[0]_0 (\GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg ),
.\DataTx_R_reg[0]_1 (\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg ),
.\DataTx_R_reg[0]_2 (\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg ),
.\DataTx_R_reg[0]_3 (\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg ),
.\DataTx_R_reg[0]_4 (Bus_RNW_reg),
.E(E),
.\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4] (\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4] ),
.Q(Q),
.SR(SR),
.S_AXI_ACLK(S_AXI_ACLK),
.S_AXI_ARADDR(S_AXI_ARADDR),
.S_AXI_ARESETN(S_AXI_ARESETN),
.S_AXI_ARREADY(S_AXI_ARREADY),
.S_AXI_ARVALID(S_AXI_ARVALID),
.S_AXI_AWADDR(S_AXI_AWADDR),
.S_AXI_AWREADY(S_AXI_AWREADY),
.S_AXI_AWVALID(S_AXI_AWVALID),
.S_AXI_BREADY(S_AXI_BREADY),
.S_AXI_BVALID(S_AXI_BVALID),
.S_AXI_RDATA(S_AXI_RDATA),
.S_AXI_RREADY(S_AXI_RREADY),
.S_AXI_RVALID(S_AXI_RVALID),
.S_AXI_WVALID(S_AXI_WVALID),
.data_rdy_bit(data_rdy_bit),
.data_rdy_bit_reg(data_rdy_bit_reg),
.data_rdy_bit_reg_0(data_rdy_bit_reg_0));
endmodule |
module ip_design_zed_audio_ctrl_0_0_i2s_ctrl
(out,
S_AXI_RDATA,
S_AXI_AWREADY,
S_AXI_ARREADY,
S_AXI_BVALID,
S_AXI_RVALID,
SDATA_O,
S_AXI_ACLK,
SDATA_I,
S_AXI_WDATA,
S_AXI_ARVALID,
S_AXI_ARESETN,
S_AXI_BREADY,
S_AXI_RREADY,
S_AXI_ARADDR,
S_AXI_AWADDR,
S_AXI_AWVALID,
S_AXI_WVALID);
output [1:0]out;
output [31:0]S_AXI_RDATA;
output S_AXI_AWREADY;
output S_AXI_ARREADY;
output S_AXI_BVALID;
output S_AXI_RVALID;
output SDATA_O;
input S_AXI_ACLK;
input SDATA_I;
input [31:0]S_AXI_WDATA;
input S_AXI_ARVALID;
input S_AXI_ARESETN;
input S_AXI_BREADY;
input S_AXI_RREADY;
input [2:0]S_AXI_ARADDR;
input [2:0]S_AXI_AWADDR;
input S_AXI_AWVALID;
input S_AXI_WVALID;
wire AXI_LITE_IPIF_I_n_11;
wire AXI_LITE_IPIF_I_n_12;
wire AXI_LITE_IPIF_I_n_13;
wire AXI_LITE_IPIF_I_n_8;
wire [23:0]DataRx_L;
wire [23:0]DataRx_R;
wire [31:0]DataTx_L;
wire [31:0]DataTx_R;
wire \I_SLAVE_ATTACHMENT/I_DECODER/Bus_RNW_reg ;
wire \I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg ;
wire \I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg ;
wire \I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg ;
wire \I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg ;
wire \I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg ;
wire SDATA_I;
wire SDATA_O;
wire S_AXI_ACLK;
wire [2:0]S_AXI_ARADDR;
wire S_AXI_ARESETN;
wire S_AXI_ARREADY;
wire S_AXI_ARVALID;
wire [2:0]S_AXI_AWADDR;
wire S_AXI_AWREADY;
wire S_AXI_AWVALID;
wire S_AXI_BREADY;
wire S_AXI_BVALID;
wire [31:0]S_AXI_RDATA;
wire S_AXI_RREADY;
wire S_AXI_RVALID;
wire [31:0]S_AXI_WDATA;
wire S_AXI_WVALID;
wire USER_LOGIC_I_n_0;
wire USER_LOGIC_I_n_69;
wire data_rdy_bit;
wire [1:0]out;
ip_design_zed_audio_ctrl_0_0_axi_lite_ipif AXI_LITE_IPIF_I
(.Bus_RNW_reg(\I_SLAVE_ATTACHMENT/I_DECODER/Bus_RNW_reg ),
.\DataRx_L_reg[23] (DataRx_L),
.\DataRx_R_reg[23] (DataRx_R),
.\DataTx_L_reg[0] (AXI_LITE_IPIF_I_n_12),
.\DataTx_L_reg[31] (DataTx_L),
.E(AXI_LITE_IPIF_I_n_11),
.\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg (\I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg ),
.\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg (\I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg ),
.\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg (\I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg ),
.\GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg (\I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg ),
.\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg (\I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg ),
.\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4] (USER_LOGIC_I_n_0),
.Q(DataTx_R),
.SR(USER_LOGIC_I_n_69),
.S_AXI_ACLK(S_AXI_ACLK),
.S_AXI_ARADDR(S_AXI_ARADDR),
.S_AXI_ARESETN(S_AXI_ARESETN),
.S_AXI_ARREADY(S_AXI_ARREADY),
.S_AXI_ARVALID(S_AXI_ARVALID),
.S_AXI_AWADDR(S_AXI_AWADDR),
.S_AXI_AWREADY(S_AXI_AWREADY),
.S_AXI_AWVALID(S_AXI_AWVALID),
.S_AXI_BREADY(S_AXI_BREADY),
.S_AXI_BVALID(S_AXI_BVALID),
.S_AXI_RDATA(S_AXI_RDATA),
.S_AXI_RREADY(S_AXI_RREADY),
.S_AXI_RVALID(S_AXI_RVALID),
.S_AXI_WVALID(S_AXI_WVALID),
.data_rdy_bit(data_rdy_bit),
.data_rdy_bit_reg(AXI_LITE_IPIF_I_n_8),
.data_rdy_bit_reg_0(AXI_LITE_IPIF_I_n_13));
ip_design_zed_audio_ctrl_0_0_user_logic USER_LOGIC_I
(.Bus_RNW_reg(\I_SLAVE_ATTACHMENT/I_DECODER/Bus_RNW_reg ),
.E(AXI_LITE_IPIF_I_n_12),
.\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg (\I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg ),
.\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0] (AXI_LITE_IPIF_I_n_8),
.\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg (\I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg ),
.\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg (\I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg ),
.\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2] (AXI_LITE_IPIF_I_n_11),
.\GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg (\I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg ),
.\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg (\I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg ),
.\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4] (AXI_LITE_IPIF_I_n_13),
.Q(out),
.SDATA_I(SDATA_I),
.SDATA_O(SDATA_O),
.SR(USER_LOGIC_I_n_69),
.S_AXI_ACLK(S_AXI_ACLK),
.S_AXI_ARESETN(S_AXI_ARESETN),
.S_AXI_WDATA(S_AXI_WDATA),
.data_rdy_bit(data_rdy_bit),
.\s_axi_rdata_i_reg[23] (DataRx_L),
.\s_axi_rdata_i_reg[23]_0 (DataRx_R),
.\s_axi_rdata_i_reg[24] (USER_LOGIC_I_n_0),
.\s_axi_rdata_i_reg[31] (DataTx_L),
.\s_axi_rdata_i_reg[31]_0 (DataTx_R));
endmodule |
module ip_design_zed_audio_ctrl_0_0_iis_deser
(lrclk_d1,
sclk_d1,
E,
\rdata_reg_reg[23]_0 ,
\bit_cntr_reg[4]_0 ,
sdata_reg_reg,
\FSM_onehot_iis_state_reg[0] ,
data_rdy_bit_reg,
\FSM_onehot_iis_state_reg[0]_0 ,
\DataRx_L_reg[23] ,
\DataRx_R_reg[23] ,
Q,
S_AXI_ACLK,
\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg ,
\GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg ,
out,
data_rdy_bit,
\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4] ,
\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0] ,
S_AXI_ARESETN,
SDATA_I);
output lrclk_d1;
output sclk_d1;
output [0:0]E;
output [0:0]\rdata_reg_reg[23]_0 ;
output [0:0]\bit_cntr_reg[4]_0 ;
output sdata_reg_reg;
output \FSM_onehot_iis_state_reg[0] ;
output data_rdy_bit_reg;
output \FSM_onehot_iis_state_reg[0]_0 ;
output [23:0]\DataRx_L_reg[23] ;
output [23:0]\DataRx_R_reg[23] ;
input [1:0]Q;
input S_AXI_ACLK;
input \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg ;
input \GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg ;
input [2:0]out;
input data_rdy_bit;
input \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4] ;
input \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0] ;
input S_AXI_ARESETN;
input SDATA_I;
wire [23:0]\DataRx_L_reg[23] ;
wire [23:0]\DataRx_R_reg[23] ;
wire [0:0]E;
wire \FSM_onehot_iis_state_reg[0] ;
wire \FSM_onehot_iis_state_reg[0]_0 ;
wire \FSM_sequential_iis_state[0]_i_1_n_0 ;
wire \FSM_sequential_iis_state[1]_i_1_n_0 ;
wire \FSM_sequential_iis_state[2]_i_1_n_0 ;
wire \FSM_sequential_iis_state[2]_i_2_n_0 ;
wire \FSM_sequential_iis_state[2]_i_3_n_0 ;
wire \FSM_sequential_iis_state[2]_i_4_n_0 ;
wire \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0] ;
wire \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg ;
wire \GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg ;
wire \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4] ;
wire [1:0]Q;
wire SDATA_I;
wire S_AXI_ACLK;
wire S_AXI_ARESETN;
wire \bit_cntr[4]_i_1_n_0 ;
wire [0:0]\bit_cntr_reg[4]_0 ;
wire [4:0]bit_cntr_reg__0;
wire bit_rdy;
wire data_rdy_bit;
wire data_rdy_bit_i_4_n_0;
wire data_rdy_bit_reg;
wire eqOp;
(* RTL_KEEP = "yes" *) wire [2:0]iis_state;
wire ldata_reg;
wire ldata_reg0;
wire lrclk_d1;
wire [2:0]out;
wire [4:0]plusOp__1;
wire rdata_reg0;
wire [0:0]\rdata_reg_reg[23]_0 ;
wire sclk_d1;
wire sdata_reg_reg;
LUT4 #(
.INIT(16'h0080))
\DataRx_L[23]_i_1
(.I0(eqOp),
.I1(iis_state[2]),
.I2(iis_state[1]),
.I3(iis_state[0]),
.O(E));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT5 #(
.INIT(32'h00000020))
\DataRx_L[23]_i_2
(.I0(bit_cntr_reg__0[3]),
.I1(bit_cntr_reg__0[0]),
.I2(bit_cntr_reg__0[4]),
.I3(bit_cntr_reg__0[1]),
.I4(bit_cntr_reg__0[2]),
.O(eqOp));
LUT3 #(
.INIT(8'h40))
\FSM_onehot_iis_state[4]_i_3
(.I0(lrclk_d1),
.I1(Q[1]),
.I2(out[1]),
.O(\FSM_onehot_iis_state_reg[0]_0 ));
(* SOFT_HLUTNM = "soft_lutpair8" *)
LUT3 #(
.INIT(8'hDF))
\FSM_onehot_iis_state[4]_i_5
(.I0(lrclk_d1),
.I1(Q[1]),
.I2(out[0]),
.O(\FSM_onehot_iis_state_reg[0] ));
LUT6 #(
.INIT(64'h75777F7745444044))
\FSM_sequential_iis_state[0]_i_1
(.I0(iis_state[0]),
.I1(\FSM_sequential_iis_state[2]_i_2_n_0 ),
.I2(iis_state[1]),
.I3(iis_state[2]),
.I4(\FSM_sequential_iis_state[2]_i_3_n_0 ),
.I5(iis_state[0]),
.O(\FSM_sequential_iis_state[0]_i_1_n_0 ));
LUT6 #(
.INIT(64'h3A7B3F7B0A480048))
\FSM_sequential_iis_state[1]_i_1
(.I0(iis_state[0]),
.I1(\FSM_sequential_iis_state[2]_i_2_n_0 ),
.I2(iis_state[1]),
.I3(iis_state[2]),
.I4(\FSM_sequential_iis_state[2]_i_3_n_0 ),
.I5(iis_state[1]),
.O(\FSM_sequential_iis_state[1]_i_1_n_0 ));
LUT6 #(
.INIT(64'h3FB33FB30F800080))
\FSM_sequential_iis_state[2]_i_1
(.I0(iis_state[0]),
.I1(\FSM_sequential_iis_state[2]_i_2_n_0 ),
.I2(iis_state[1]),
.I3(iis_state[2]),
.I4(\FSM_sequential_iis_state[2]_i_3_n_0 ),
.I5(iis_state[2]),
.O(\FSM_sequential_iis_state[2]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFFA33FF000A330F))
\FSM_sequential_iis_state[2]_i_2
(.I0(bit_rdy),
.I1(\FSM_sequential_iis_state[2]_i_4_n_0 ),
.I2(iis_state[2]),
.I3(iis_state[0]),
.I4(iis_state[1]),
.I5(eqOp),
.O(\FSM_sequential_iis_state[2]_i_2_n_0 ));
LUT6 #(
.INIT(64'h22A222A2EEAE22A2))
\FSM_sequential_iis_state[2]_i_3
(.I0(bit_rdy),
.I1(iis_state[2]),
.I2(iis_state[0]),
.I3(iis_state[1]),
.I4(Q[1]),
.I5(lrclk_d1),
.O(\FSM_sequential_iis_state[2]_i_3_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair8" *)
LUT2 #(
.INIT(4'hB))
\FSM_sequential_iis_state[2]_i_4
(.I0(Q[1]),
.I1(lrclk_d1),
.O(\FSM_sequential_iis_state[2]_i_4_n_0 ));
(* FSM_ENCODED_STATES = "reset:000,wait_left:001,skip_left:010,read_left:011,wait_right:100,skip_right:101,read_right:110" *)
(* KEEP = "yes" *)
FDRE #(
.INIT(1'b0))
\FSM_sequential_iis_state_reg[0]
(.C(S_AXI_ACLK),
.CE(1'b1),
.D(\FSM_sequential_iis_state[0]_i_1_n_0 ),
.Q(iis_state[0]),
.R(1'b0));
(* FSM_ENCODED_STATES = "reset:000,wait_left:001,skip_left:010,read_left:011,wait_right:100,skip_right:101,read_right:110" *)
(* KEEP = "yes" *)
FDRE #(
.INIT(1'b0))
\FSM_sequential_iis_state_reg[1]
(.C(S_AXI_ACLK),
.CE(1'b1),
.D(\FSM_sequential_iis_state[1]_i_1_n_0 ),
.Q(iis_state[1]),
.R(1'b0));
(* FSM_ENCODED_STATES = "reset:000,wait_left:001,skip_left:010,read_left:011,wait_right:100,skip_right:101,read_right:110" *)
(* KEEP = "yes" *)
FDRE #(
.INIT(1'b0))
\FSM_sequential_iis_state_reg[2]
(.C(S_AXI_ACLK),
.CE(1'b1),
.D(\FSM_sequential_iis_state[2]_i_1_n_0 ),
.Q(iis_state[2]),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair9" *)
LUT1 #(
.INIT(2'h1))
\bit_cntr[0]_i_1
(.I0(bit_cntr_reg__0[0]),
.O(plusOp__1[0]));
(* SOFT_HLUTNM = "soft_lutpair9" *)
LUT2 #(
.INIT(4'h6))
\bit_cntr[1]_i_1
(.I0(bit_cntr_reg__0[0]),
.I1(bit_cntr_reg__0[1]),
.O(plusOp__1[1]));
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT3 #(
.INIT(8'h78))
\bit_cntr[2]_i_1
(.I0(bit_cntr_reg__0[1]),
.I1(bit_cntr_reg__0[0]),
.I2(bit_cntr_reg__0[2]),
.O(plusOp__1[2]));
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT4 #(
.INIT(16'h6CCC))
\bit_cntr[3]_i_1
(.I0(bit_cntr_reg__0[1]),
.I1(bit_cntr_reg__0[3]),
.I2(bit_cntr_reg__0[0]),
.I3(bit_cntr_reg__0[2]),
.O(plusOp__1[3]));
LUT3 #(
.INIT(8'hD7))
\bit_cntr[4]_i_1
(.I0(iis_state[1]),
.I1(iis_state[0]),
.I2(iis_state[2]),
.O(\bit_cntr[4]_i_1_n_0 ));
LUT2 #(
.INIT(4'h2))
\bit_cntr[4]_i_2
(.I0(Q[0]),
.I1(sclk_d1),
.O(bit_rdy));
(* SOFT_HLUTNM = "soft_lutpair10" *)
LUT2 #(
.INIT(4'h2))
\bit_cntr[4]_i_2__0
(.I0(sclk_d1),
.I1(Q[0]),
.O(\bit_cntr_reg[4]_0 ));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT5 #(
.INIT(32'h78F0F0F0))
\bit_cntr[4]_i_3
(.I0(bit_cntr_reg__0[3]),
.I1(bit_cntr_reg__0[2]),
.I2(bit_cntr_reg__0[4]),
.I3(bit_cntr_reg__0[1]),
.I4(bit_cntr_reg__0[0]),
.O(plusOp__1[4]));
FDRE #(
.INIT(1'b0))
\bit_cntr_reg[0]
(.C(S_AXI_ACLK),
.CE(bit_rdy),
.D(plusOp__1[0]),
.Q(bit_cntr_reg__0[0]),
.R(\bit_cntr[4]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\bit_cntr_reg[1]
(.C(S_AXI_ACLK),
.CE(bit_rdy),
.D(plusOp__1[1]),
.Q(bit_cntr_reg__0[1]),
.R(\bit_cntr[4]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\bit_cntr_reg[2]
(.C(S_AXI_ACLK),
.CE(bit_rdy),
.D(plusOp__1[2]),
.Q(bit_cntr_reg__0[2]),
.R(\bit_cntr[4]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\bit_cntr_reg[3]
(.C(S_AXI_ACLK),
.CE(bit_rdy),
.D(plusOp__1[3]),
.Q(bit_cntr_reg__0[3]),
.R(\bit_cntr[4]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\bit_cntr_reg[4]
(.C(S_AXI_ACLK),
.CE(bit_rdy),
.D(plusOp__1[4]),
.Q(bit_cntr_reg__0[4]),
.R(\bit_cntr[4]_i_1_n_0 ));
LUT6 #(
.INIT(64'hCC00EA0000000000))
data_rdy_bit_i_1
(.I0(data_rdy_bit),
.I1(E),
.I2(\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4] ),
.I3(\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0] ),
.I4(data_rdy_bit_i_4_n_0),
.I5(S_AXI_ARESETN),
.O(data_rdy_bit_reg));
LUT6 #(
.INIT(64'h0000000090000000))
data_rdy_bit_i_4
(.I0(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg ),
.I1(\GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg ),
.I2(eqOp),
.I3(iis_state[2]),
.I4(iis_state[1]),
.I5(iis_state[0]),
.O(data_rdy_bit_i_4_n_0));
LUT3 #(
.INIT(8'h01))
\ldata_reg[23]_i_1
(.I0(iis_state[1]),
.I1(iis_state[0]),
.I2(iis_state[2]),
.O(ldata_reg));
LUT5 #(
.INIT(32'h00004000))
\ldata_reg[23]_i_2
(.I0(iis_state[2]),
.I1(iis_state[0]),
.I2(iis_state[1]),
.I3(Q[0]),
.I4(sclk_d1),
.O(ldata_reg0));
FDRE #(
.INIT(1'b0))
\ldata_reg_reg[0]
(.C(S_AXI_ACLK),
.CE(ldata_reg0),
.D(SDATA_I),
.Q(\DataRx_L_reg[23] [0]),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\ldata_reg_reg[10]
(.C(S_AXI_ACLK),
.CE(ldata_reg0),
.D(\DataRx_L_reg[23] [9]),
.Q(\DataRx_L_reg[23] [10]),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\ldata_reg_reg[11]
(.C(S_AXI_ACLK),
.CE(ldata_reg0),
.D(\DataRx_L_reg[23] [10]),
.Q(\DataRx_L_reg[23] [11]),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\ldata_reg_reg[12]
(.C(S_AXI_ACLK),
.CE(ldata_reg0),
.D(\DataRx_L_reg[23] [11]),
.Q(\DataRx_L_reg[23] [12]),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\ldata_reg_reg[13]
(.C(S_AXI_ACLK),
.CE(ldata_reg0),
.D(\DataRx_L_reg[23] [12]),
.Q(\DataRx_L_reg[23] [13]),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\ldata_reg_reg[14]
(.C(S_AXI_ACLK),
.CE(ldata_reg0),
.D(\DataRx_L_reg[23] [13]),
.Q(\DataRx_L_reg[23] [14]),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\ldata_reg_reg[15]
(.C(S_AXI_ACLK),
.CE(ldata_reg0),
.D(\DataRx_L_reg[23] [14]),
.Q(\DataRx_L_reg[23] [15]),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\ldata_reg_reg[16]
(.C(S_AXI_ACLK),
.CE(ldata_reg0),
.D(\DataRx_L_reg[23] [15]),
.Q(\DataRx_L_reg[23] [16]),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\ldata_reg_reg[17]
(.C(S_AXI_ACLK),
.CE(ldata_reg0),
.D(\DataRx_L_reg[23] [16]),
.Q(\DataRx_L_reg[23] [17]),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\ldata_reg_reg[18]
(.C(S_AXI_ACLK),
.CE(ldata_reg0),
.D(\DataRx_L_reg[23] [17]),
.Q(\DataRx_L_reg[23] [18]),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\ldata_reg_reg[19]
(.C(S_AXI_ACLK),
.CE(ldata_reg0),
.D(\DataRx_L_reg[23] [18]),
.Q(\DataRx_L_reg[23] [19]),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\ldata_reg_reg[1]
(.C(S_AXI_ACLK),
.CE(ldata_reg0),
.D(\DataRx_L_reg[23] [0]),
.Q(\DataRx_L_reg[23] [1]),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\ldata_reg_reg[20]
(.C(S_AXI_ACLK),
.CE(ldata_reg0),
.D(\DataRx_L_reg[23] [19]),
.Q(\DataRx_L_reg[23] [20]),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\ldata_reg_reg[21]
(.C(S_AXI_ACLK),
.CE(ldata_reg0),
.D(\DataRx_L_reg[23] [20]),
.Q(\DataRx_L_reg[23] [21]),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\ldata_reg_reg[22]
(.C(S_AXI_ACLK),
.CE(ldata_reg0),
.D(\DataRx_L_reg[23] [21]),
.Q(\DataRx_L_reg[23] [22]),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\ldata_reg_reg[23]
(.C(S_AXI_ACLK),
.CE(ldata_reg0),
.D(\DataRx_L_reg[23] [22]),
.Q(\DataRx_L_reg[23] [23]),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\ldata_reg_reg[2]
(.C(S_AXI_ACLK),
.CE(ldata_reg0),
.D(\DataRx_L_reg[23] [1]),
.Q(\DataRx_L_reg[23] [2]),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\ldata_reg_reg[3]
(.C(S_AXI_ACLK),
.CE(ldata_reg0),
.D(\DataRx_L_reg[23] [2]),
.Q(\DataRx_L_reg[23] [3]),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\ldata_reg_reg[4]
(.C(S_AXI_ACLK),
.CE(ldata_reg0),
.D(\DataRx_L_reg[23] [3]),
.Q(\DataRx_L_reg[23] [4]),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\ldata_reg_reg[5]
(.C(S_AXI_ACLK),
.CE(ldata_reg0),
.D(\DataRx_L_reg[23] [4]),
.Q(\DataRx_L_reg[23] [5]),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\ldata_reg_reg[6]
(.C(S_AXI_ACLK),
.CE(ldata_reg0),
.D(\DataRx_L_reg[23] [5]),
.Q(\DataRx_L_reg[23] [6]),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\ldata_reg_reg[7]
(.C(S_AXI_ACLK),
.CE(ldata_reg0),
.D(\DataRx_L_reg[23] [6]),
.Q(\DataRx_L_reg[23] [7]),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\ldata_reg_reg[8]
(.C(S_AXI_ACLK),
.CE(ldata_reg0),
.D(\DataRx_L_reg[23] [7]),
.Q(\DataRx_L_reg[23] [8]),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\ldata_reg_reg[9]
(.C(S_AXI_ACLK),
.CE(ldata_reg0),
.D(\DataRx_L_reg[23] [8]),
.Q(\DataRx_L_reg[23] [9]),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
lrclk_d1_reg
(.C(S_AXI_ACLK),
.CE(1'b1),
.D(Q[1]),
.Q(lrclk_d1),
.R(1'b0));
LUT5 #(
.INIT(32'h00004000))
\rdata_reg[23]_i_1
(.I0(iis_state[0]),
.I1(iis_state[1]),
.I2(iis_state[2]),
.I3(Q[0]),
.I4(sclk_d1),
.O(rdata_reg0));
LUT6 #(
.INIT(64'h4040FF4040404040))
\rdata_reg[23]_i_1__0
(.I0(Q[0]),
.I1(sclk_d1),
.I2(out[2]),
.I3(out[0]),
.I4(Q[1]),
.I5(lrclk_d1),
.O(\rdata_reg_reg[23]_0 ));
FDRE #(
.INIT(1'b0))
\rdata_reg_reg[0]
(.C(S_AXI_ACLK),
.CE(rdata_reg0),
.D(SDATA_I),
.Q(\DataRx_R_reg[23] [0]),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\rdata_reg_reg[10]
(.C(S_AXI_ACLK),
.CE(rdata_reg0),
.D(\DataRx_R_reg[23] [9]),
.Q(\DataRx_R_reg[23] [10]),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\rdata_reg_reg[11]
(.C(S_AXI_ACLK),
.CE(rdata_reg0),
.D(\DataRx_R_reg[23] [10]),
.Q(\DataRx_R_reg[23] [11]),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\rdata_reg_reg[12]
(.C(S_AXI_ACLK),
.CE(rdata_reg0),
.D(\DataRx_R_reg[23] [11]),
.Q(\DataRx_R_reg[23] [12]),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\rdata_reg_reg[13]
(.C(S_AXI_ACLK),
.CE(rdata_reg0),
.D(\DataRx_R_reg[23] [12]),
.Q(\DataRx_R_reg[23] [13]),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\rdata_reg_reg[14]
(.C(S_AXI_ACLK),
.CE(rdata_reg0),
.D(\DataRx_R_reg[23] [13]),
.Q(\DataRx_R_reg[23] [14]),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\rdata_reg_reg[15]
(.C(S_AXI_ACLK),
.CE(rdata_reg0),
.D(\DataRx_R_reg[23] [14]),
.Q(\DataRx_R_reg[23] [15]),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\rdata_reg_reg[16]
(.C(S_AXI_ACLK),
.CE(rdata_reg0),
.D(\DataRx_R_reg[23] [15]),
.Q(\DataRx_R_reg[23] [16]),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\rdata_reg_reg[17]
(.C(S_AXI_ACLK),
.CE(rdata_reg0),
.D(\DataRx_R_reg[23] [16]),
.Q(\DataRx_R_reg[23] [17]),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\rdata_reg_reg[18]
(.C(S_AXI_ACLK),
.CE(rdata_reg0),
.D(\DataRx_R_reg[23] [17]),
.Q(\DataRx_R_reg[23] [18]),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\rdata_reg_reg[19]
(.C(S_AXI_ACLK),
.CE(rdata_reg0),
.D(\DataRx_R_reg[23] [18]),
.Q(\DataRx_R_reg[23] [19]),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\rdata_reg_reg[1]
(.C(S_AXI_ACLK),
.CE(rdata_reg0),
.D(\DataRx_R_reg[23] [0]),
.Q(\DataRx_R_reg[23] [1]),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\rdata_reg_reg[20]
(.C(S_AXI_ACLK),
.CE(rdata_reg0),
.D(\DataRx_R_reg[23] [19]),
.Q(\DataRx_R_reg[23] [20]),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\rdata_reg_reg[21]
(.C(S_AXI_ACLK),
.CE(rdata_reg0),
.D(\DataRx_R_reg[23] [20]),
.Q(\DataRx_R_reg[23] [21]),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\rdata_reg_reg[22]
(.C(S_AXI_ACLK),
.CE(rdata_reg0),
.D(\DataRx_R_reg[23] [21]),
.Q(\DataRx_R_reg[23] [22]),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\rdata_reg_reg[23]
(.C(S_AXI_ACLK),
.CE(rdata_reg0),
.D(\DataRx_R_reg[23] [22]),
.Q(\DataRx_R_reg[23] [23]),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\rdata_reg_reg[2]
(.C(S_AXI_ACLK),
.CE(rdata_reg0),
.D(\DataRx_R_reg[23] [1]),
.Q(\DataRx_R_reg[23] [2]),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\rdata_reg_reg[3]
(.C(S_AXI_ACLK),
.CE(rdata_reg0),
.D(\DataRx_R_reg[23] [2]),
.Q(\DataRx_R_reg[23] [3]),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\rdata_reg_reg[4]
(.C(S_AXI_ACLK),
.CE(rdata_reg0),
.D(\DataRx_R_reg[23] [3]),
.Q(\DataRx_R_reg[23] [4]),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\rdata_reg_reg[5]
(.C(S_AXI_ACLK),
.CE(rdata_reg0),
.D(\DataRx_R_reg[23] [4]),
.Q(\DataRx_R_reg[23] [5]),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\rdata_reg_reg[6]
(.C(S_AXI_ACLK),
.CE(rdata_reg0),
.D(\DataRx_R_reg[23] [5]),
.Q(\DataRx_R_reg[23] [6]),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\rdata_reg_reg[7]
(.C(S_AXI_ACLK),
.CE(rdata_reg0),
.D(\DataRx_R_reg[23] [6]),
.Q(\DataRx_R_reg[23] [7]),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\rdata_reg_reg[8]
(.C(S_AXI_ACLK),
.CE(rdata_reg0),
.D(\DataRx_R_reg[23] [7]),
.Q(\DataRx_R_reg[23] [8]),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\rdata_reg_reg[9]
(.C(S_AXI_ACLK),
.CE(rdata_reg0),
.D(\DataRx_R_reg[23] [8]),
.Q(\DataRx_R_reg[23] [9]),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
sclk_d1_reg
(.C(S_AXI_ACLK),
.CE(1'b1),
.D(Q[0]),
.Q(sclk_d1),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair10" *)
LUT2 #(
.INIT(4'hB))
sdata_reg_i_2
(.I0(Q[0]),
.I1(sclk_d1),
.O(sdata_reg_reg));
endmodule |
module ip_design_zed_audio_ctrl_0_0_iis_ser
(SDATA_O,
out,
S_AXI_ACLK,
Q,
sclk_d1,
lrclk_d1,
\DataTx_L_reg[23] ,
\DataTx_R_reg[23] ,
\clk_cntr_reg[4] ,
lrclk_d1_reg,
lrclk_d1_reg_0,
E,
sclk_d1_reg);
output SDATA_O;
output [2:0]out;
input S_AXI_ACLK;
input [1:0]Q;
input sclk_d1;
input lrclk_d1;
input [23:0]\DataTx_L_reg[23] ;
input [23:0]\DataTx_R_reg[23] ;
input \clk_cntr_reg[4] ;
input lrclk_d1_reg;
input lrclk_d1_reg_0;
input [0:0]E;
input [0:0]sclk_d1_reg;
wire [23:0]\DataTx_L_reg[23] ;
wire [23:0]\DataTx_R_reg[23] ;
wire [0:0]E;
wire \FSM_onehot_iis_state[1]_i_1_n_0 ;
wire \FSM_onehot_iis_state[2]_i_1_n_0 ;
wire \FSM_onehot_iis_state[3]_i_1_n_0 ;
wire \FSM_onehot_iis_state[4]_i_1_n_0 ;
wire \FSM_onehot_iis_state[4]_i_2_n_0 ;
wire [1:0]Q;
wire SDATA_O;
wire S_AXI_ACLK;
wire \bit_cntr[4]_i_1__0_n_0 ;
wire [4:0]bit_cntr_reg__0;
wire \clk_cntr_reg[4] ;
wire eqOp;
(* RTL_KEEP = "yes" *) wire ldata_reg;
wire \ldata_reg[0]_i_1_n_0 ;
wire \ldata_reg[10]_i_1_n_0 ;
wire \ldata_reg[11]_i_1_n_0 ;
wire \ldata_reg[12]_i_1_n_0 ;
wire \ldata_reg[13]_i_1_n_0 ;
wire \ldata_reg[14]_i_1_n_0 ;
wire \ldata_reg[15]_i_1_n_0 ;
wire \ldata_reg[16]_i_1_n_0 ;
wire \ldata_reg[17]_i_1_n_0 ;
wire \ldata_reg[18]_i_1_n_0 ;
wire \ldata_reg[19]_i_1_n_0 ;
wire \ldata_reg[1]_i_1_n_0 ;
wire \ldata_reg[20]_i_1_n_0 ;
wire \ldata_reg[21]_i_1_n_0 ;
wire \ldata_reg[22]_i_1_n_0 ;
wire \ldata_reg[23]_i_1__0_n_0 ;
wire \ldata_reg[23]_i_2__0_n_0 ;
wire \ldata_reg[2]_i_1_n_0 ;
wire \ldata_reg[3]_i_1_n_0 ;
wire \ldata_reg[4]_i_1_n_0 ;
wire \ldata_reg[5]_i_1_n_0 ;
wire \ldata_reg[6]_i_1_n_0 ;
wire \ldata_reg[7]_i_1_n_0 ;
wire \ldata_reg[8]_i_1_n_0 ;
wire \ldata_reg[9]_i_1_n_0 ;
wire \ldata_reg_reg_n_0_[0] ;
wire \ldata_reg_reg_n_0_[10] ;
wire \ldata_reg_reg_n_0_[11] ;
wire \ldata_reg_reg_n_0_[12] ;
wire \ldata_reg_reg_n_0_[13] ;
wire \ldata_reg_reg_n_0_[14] ;
wire \ldata_reg_reg_n_0_[15] ;
wire \ldata_reg_reg_n_0_[16] ;
wire \ldata_reg_reg_n_0_[17] ;
wire \ldata_reg_reg_n_0_[18] ;
wire \ldata_reg_reg_n_0_[19] ;
wire \ldata_reg_reg_n_0_[1] ;
wire \ldata_reg_reg_n_0_[20] ;
wire \ldata_reg_reg_n_0_[21] ;
wire \ldata_reg_reg_n_0_[22] ;
wire \ldata_reg_reg_n_0_[2] ;
wire \ldata_reg_reg_n_0_[3] ;
wire \ldata_reg_reg_n_0_[4] ;
wire \ldata_reg_reg_n_0_[5] ;
wire \ldata_reg_reg_n_0_[6] ;
wire \ldata_reg_reg_n_0_[7] ;
wire \ldata_reg_reg_n_0_[8] ;
wire \ldata_reg_reg_n_0_[9] ;
wire lrclk_d1;
wire lrclk_d1_reg;
wire lrclk_d1_reg_0;
(* RTL_KEEP = "yes" *) wire [2:0]out;
(* RTL_KEEP = "yes" *) wire p_0_in2_in;
wire [23:0]p_1_in;
wire p_2_in;
wire [4:0]plusOp__2;
wire \rdata_reg_reg_n_0_[0] ;
wire \rdata_reg_reg_n_0_[10] ;
wire \rdata_reg_reg_n_0_[11] ;
wire \rdata_reg_reg_n_0_[12] ;
wire \rdata_reg_reg_n_0_[13] ;
wire \rdata_reg_reg_n_0_[14] ;
wire \rdata_reg_reg_n_0_[15] ;
wire \rdata_reg_reg_n_0_[16] ;
wire \rdata_reg_reg_n_0_[17] ;
wire \rdata_reg_reg_n_0_[18] ;
wire \rdata_reg_reg_n_0_[19] ;
wire \rdata_reg_reg_n_0_[1] ;
wire \rdata_reg_reg_n_0_[20] ;
wire \rdata_reg_reg_n_0_[21] ;
wire \rdata_reg_reg_n_0_[22] ;
wire \rdata_reg_reg_n_0_[23] ;
wire \rdata_reg_reg_n_0_[2] ;
wire \rdata_reg_reg_n_0_[3] ;
wire \rdata_reg_reg_n_0_[4] ;
wire \rdata_reg_reg_n_0_[5] ;
wire \rdata_reg_reg_n_0_[6] ;
wire \rdata_reg_reg_n_0_[7] ;
wire \rdata_reg_reg_n_0_[8] ;
wire \rdata_reg_reg_n_0_[9] ;
wire sclk_d1;
wire [0:0]sclk_d1_reg;
wire sdata_reg_i_1_n_0;
LUT5 #(
.INIT(32'hAAAAAABA))
\FSM_onehot_iis_state[1]_i_1
(.I0(ldata_reg),
.I1(p_0_in2_in),
.I2(out[2]),
.I3(out[1]),
.I4(out[0]),
.O(\FSM_onehot_iis_state[1]_i_1_n_0 ));
LUT4 #(
.INIT(16'h0ACA))
\FSM_onehot_iis_state[2]_i_1
(.I0(p_0_in2_in),
.I1(out[0]),
.I2(\FSM_onehot_iis_state[4]_i_1_n_0 ),
.I3(ldata_reg),
.O(\FSM_onehot_iis_state[2]_i_1_n_0 ));
LUT3 #(
.INIT(8'h02))
\FSM_onehot_iis_state[3]_i_1
(.I0(p_0_in2_in),
.I1(ldata_reg),
.I2(out[0]),
.O(\FSM_onehot_iis_state[3]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFEEFFFFFEEEFFFF))
\FSM_onehot_iis_state[4]_i_1
(.I0(ldata_reg),
.I1(lrclk_d1_reg),
.I2(out[2]),
.I3(eqOp),
.I4(lrclk_d1_reg_0),
.I5(p_0_in2_in),
.O(\FSM_onehot_iis_state[4]_i_1_n_0 ));
LUT4 #(
.INIT(16'h0010))
\FSM_onehot_iis_state[4]_i_2
(.I0(ldata_reg),
.I1(p_0_in2_in),
.I2(out[1]),
.I3(out[0]),
.O(\FSM_onehot_iis_state[4]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair11" *)
LUT5 #(
.INIT(32'h02000000))
\FSM_onehot_iis_state[4]_i_4
(.I0(bit_cntr_reg__0[0]),
.I1(bit_cntr_reg__0[1]),
.I2(bit_cntr_reg__0[2]),
.I3(bit_cntr_reg__0[4]),
.I4(bit_cntr_reg__0[3]),
.O(eqOp));
(* FSM_ENCODED_STATES = "reset:00001,wait_left:00010,write_left:00100,wait_right:01000,write_right:10000" *)
(* KEEP = "yes" *)
FDRE #(
.INIT(1'b1))
\FSM_onehot_iis_state_reg[0]
(.C(S_AXI_ACLK),
.CE(\FSM_onehot_iis_state[4]_i_1_n_0 ),
.D(1'b0),
.Q(ldata_reg),
.R(1'b0));
(* FSM_ENCODED_STATES = "reset:00001,wait_left:00010,write_left:00100,wait_right:01000,write_right:10000" *)
(* KEEP = "yes" *)
FDRE #(
.INIT(1'b0))
\FSM_onehot_iis_state_reg[1]
(.C(S_AXI_ACLK),
.CE(\FSM_onehot_iis_state[4]_i_1_n_0 ),
.D(\FSM_onehot_iis_state[1]_i_1_n_0 ),
.Q(out[0]),
.R(1'b0));
(* FSM_ENCODED_STATES = "reset:00001,wait_left:00010,write_left:00100,wait_right:01000,write_right:10000" *)
(* KEEP = "yes" *)
FDRE #(
.INIT(1'b0))
\FSM_onehot_iis_state_reg[2]
(.C(S_AXI_ACLK),
.CE(1'b1),
.D(\FSM_onehot_iis_state[2]_i_1_n_0 ),
.Q(p_0_in2_in),
.R(1'b0));
(* FSM_ENCODED_STATES = "reset:00001,wait_left:00010,write_left:00100,wait_right:01000,write_right:10000" *)
(* KEEP = "yes" *)
FDRE #(
.INIT(1'b0))
\FSM_onehot_iis_state_reg[3]
(.C(S_AXI_ACLK),
.CE(\FSM_onehot_iis_state[4]_i_1_n_0 ),
.D(\FSM_onehot_iis_state[3]_i_1_n_0 ),
.Q(out[1]),
.R(1'b0));
(* FSM_ENCODED_STATES = "reset:00001,wait_left:00010,write_left:00100,wait_right:01000,write_right:10000" *)
(* KEEP = "yes" *)
FDRE #(
.INIT(1'b0))
\FSM_onehot_iis_state_reg[4]
(.C(S_AXI_ACLK),
.CE(\FSM_onehot_iis_state[4]_i_1_n_0 ),
.D(\FSM_onehot_iis_state[4]_i_2_n_0 ),
.Q(out[2]),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair13" *)
LUT1 #(
.INIT(2'h1))
\bit_cntr[0]_i_1__0
(.I0(bit_cntr_reg__0[0]),
.O(plusOp__2[0]));
(* SOFT_HLUTNM = "soft_lutpair13" *)
LUT2 #(
.INIT(4'h6))
\bit_cntr[1]_i_1__0
(.I0(bit_cntr_reg__0[0]),
.I1(bit_cntr_reg__0[1]),
.O(plusOp__2[1]));
(* SOFT_HLUTNM = "soft_lutpair12" *)
LUT3 #(
.INIT(8'h78))
\bit_cntr[2]_i_1__0
(.I0(bit_cntr_reg__0[1]),
.I1(bit_cntr_reg__0[0]),
.I2(bit_cntr_reg__0[2]),
.O(plusOp__2[2]));
(* SOFT_HLUTNM = "soft_lutpair12" *)
LUT4 #(
.INIT(16'h7F80))
\bit_cntr[3]_i_1__0
(.I0(bit_cntr_reg__0[2]),
.I1(bit_cntr_reg__0[0]),
.I2(bit_cntr_reg__0[1]),
.I3(bit_cntr_reg__0[3]),
.O(plusOp__2[3]));
LUT2 #(
.INIT(4'h1))
\bit_cntr[4]_i_1__0
(.I0(out[2]),
.I1(p_0_in2_in),
.O(\bit_cntr[4]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair11" *)
LUT5 #(
.INIT(32'h7FFF8000))
\bit_cntr[4]_i_3__0
(.I0(bit_cntr_reg__0[3]),
.I1(bit_cntr_reg__0[1]),
.I2(bit_cntr_reg__0[0]),
.I3(bit_cntr_reg__0[2]),
.I4(bit_cntr_reg__0[4]),
.O(plusOp__2[4]));
FDRE #(
.INIT(1'b0))
\bit_cntr_reg[0]
(.C(S_AXI_ACLK),
.CE(sclk_d1_reg),
.D(plusOp__2[0]),
.Q(bit_cntr_reg__0[0]),
.R(\bit_cntr[4]_i_1__0_n_0 ));
FDRE #(
.INIT(1'b0))
\bit_cntr_reg[1]
(.C(S_AXI_ACLK),
.CE(sclk_d1_reg),
.D(plusOp__2[1]),
.Q(bit_cntr_reg__0[1]),
.R(\bit_cntr[4]_i_1__0_n_0 ));
FDRE #(
.INIT(1'b0))
\bit_cntr_reg[2]
(.C(S_AXI_ACLK),
.CE(sclk_d1_reg),
.D(plusOp__2[2]),
.Q(bit_cntr_reg__0[2]),
.R(\bit_cntr[4]_i_1__0_n_0 ));
FDRE #(
.INIT(1'b0))
\bit_cntr_reg[3]
(.C(S_AXI_ACLK),
.CE(sclk_d1_reg),
.D(plusOp__2[3]),
.Q(bit_cntr_reg__0[3]),
.R(\bit_cntr[4]_i_1__0_n_0 ));
FDRE #(
.INIT(1'b0))
\bit_cntr_reg[4]
(.C(S_AXI_ACLK),
.CE(sclk_d1_reg),
.D(plusOp__2[4]),
.Q(bit_cntr_reg__0[4]),
.R(\bit_cntr[4]_i_1__0_n_0 ));
LUT4 #(
.INIT(16'h0800))
\ldata_reg[0]_i_1
(.I0(\DataTx_L_reg[23] [0]),
.I1(out[0]),
.I2(Q[1]),
.I3(lrclk_d1),
.O(\ldata_reg[0]_i_1_n_0 ));
LUT5 #(
.INIT(32'hAEAAA2AA))
\ldata_reg[10]_i_1
(.I0(\ldata_reg_reg_n_0_[9] ),
.I1(lrclk_d1),
.I2(Q[1]),
.I3(out[0]),
.I4(\DataTx_L_reg[23] [10]),
.O(\ldata_reg[10]_i_1_n_0 ));
LUT5 #(
.INIT(32'hAEAAA2AA))
\ldata_reg[11]_i_1
(.I0(\ldata_reg_reg_n_0_[10] ),
.I1(lrclk_d1),
.I2(Q[1]),
.I3(out[0]),
.I4(\DataTx_L_reg[23] [11]),
.O(\ldata_reg[11]_i_1_n_0 ));
LUT5 #(
.INIT(32'hAEAAA2AA))
\ldata_reg[12]_i_1
(.I0(\ldata_reg_reg_n_0_[11] ),
.I1(lrclk_d1),
.I2(Q[1]),
.I3(out[0]),
.I4(\DataTx_L_reg[23] [12]),
.O(\ldata_reg[12]_i_1_n_0 ));
LUT5 #(
.INIT(32'hAEAAA2AA))
\ldata_reg[13]_i_1
(.I0(\ldata_reg_reg_n_0_[12] ),
.I1(lrclk_d1),
.I2(Q[1]),
.I3(out[0]),
.I4(\DataTx_L_reg[23] [13]),
.O(\ldata_reg[13]_i_1_n_0 ));
LUT5 #(
.INIT(32'hAEAAA2AA))
\ldata_reg[14]_i_1
(.I0(\ldata_reg_reg_n_0_[13] ),
.I1(lrclk_d1),
.I2(Q[1]),
.I3(out[0]),
.I4(\DataTx_L_reg[23] [14]),
.O(\ldata_reg[14]_i_1_n_0 ));
LUT5 #(
.INIT(32'hAEAAA2AA))
\ldata_reg[15]_i_1
(.I0(\ldata_reg_reg_n_0_[14] ),
.I1(lrclk_d1),
.I2(Q[1]),
.I3(out[0]),
.I4(\DataTx_L_reg[23] [15]),
.O(\ldata_reg[15]_i_1_n_0 ));
LUT5 #(
.INIT(32'hAEAAA2AA))
\ldata_reg[16]_i_1
(.I0(\ldata_reg_reg_n_0_[15] ),
.I1(lrclk_d1),
.I2(Q[1]),
.I3(out[0]),
.I4(\DataTx_L_reg[23] [16]),
.O(\ldata_reg[16]_i_1_n_0 ));
LUT5 #(
.INIT(32'hAEAAA2AA))
\ldata_reg[17]_i_1
(.I0(\ldata_reg_reg_n_0_[16] ),
.I1(lrclk_d1),
.I2(Q[1]),
.I3(out[0]),
.I4(\DataTx_L_reg[23] [17]),
.O(\ldata_reg[17]_i_1_n_0 ));
LUT5 #(
.INIT(32'hAEAAA2AA))
\ldata_reg[18]_i_1
(.I0(\ldata_reg_reg_n_0_[17] ),
.I1(lrclk_d1),
.I2(Q[1]),
.I3(out[0]),
.I4(\DataTx_L_reg[23] [18]),
.O(\ldata_reg[18]_i_1_n_0 ));
LUT5 #(
.INIT(32'hAEAAA2AA))
\ldata_reg[19]_i_1
(.I0(\ldata_reg_reg_n_0_[18] ),
.I1(lrclk_d1),
.I2(Q[1]),
.I3(out[0]),
.I4(\DataTx_L_reg[23] [19]),
.O(\ldata_reg[19]_i_1_n_0 ));
LUT5 #(
.INIT(32'hAEAAA2AA))
\ldata_reg[1]_i_1
(.I0(\ldata_reg_reg_n_0_[0] ),
.I1(lrclk_d1),
.I2(Q[1]),
.I3(out[0]),
.I4(\DataTx_L_reg[23] [1]),
.O(\ldata_reg[1]_i_1_n_0 ));
LUT5 #(
.INIT(32'hAEAAA2AA))
\ldata_reg[20]_i_1
(.I0(\ldata_reg_reg_n_0_[19] ),
.I1(lrclk_d1),
.I2(Q[1]),
.I3(out[0]),
.I4(\DataTx_L_reg[23] [20]),
.O(\ldata_reg[20]_i_1_n_0 ));
LUT5 #(
.INIT(32'hAEAAA2AA))
\ldata_reg[21]_i_1
(.I0(\ldata_reg_reg_n_0_[20] ),
.I1(lrclk_d1),
.I2(Q[1]),
.I3(out[0]),
.I4(\DataTx_L_reg[23] [21]),
.O(\ldata_reg[21]_i_1_n_0 ));
LUT5 #(
.INIT(32'hAEAAA2AA))
\ldata_reg[22]_i_1
(.I0(\ldata_reg_reg_n_0_[21] ),
.I1(lrclk_d1),
.I2(Q[1]),
.I3(out[0]),
.I4(\DataTx_L_reg[23] [22]),
.O(\ldata_reg[22]_i_1_n_0 ));
LUT6 #(
.INIT(64'h2020FF2020202020))
\ldata_reg[23]_i_1__0
(.I0(p_0_in2_in),
.I1(Q[0]),
.I2(sclk_d1),
.I3(out[0]),
.I4(Q[1]),
.I5(lrclk_d1),
.O(\ldata_reg[23]_i_1__0_n_0 ));
LUT5 #(
.INIT(32'hAEAAA2AA))
\ldata_reg[23]_i_2__0
(.I0(\ldata_reg_reg_n_0_[22] ),
.I1(lrclk_d1),
.I2(Q[1]),
.I3(out[0]),
.I4(\DataTx_L_reg[23] [23]),
.O(\ldata_reg[23]_i_2__0_n_0 ));
LUT5 #(
.INIT(32'hAEAAA2AA))
\ldata_reg[2]_i_1
(.I0(\ldata_reg_reg_n_0_[1] ),
.I1(lrclk_d1),
.I2(Q[1]),
.I3(out[0]),
.I4(\DataTx_L_reg[23] [2]),
.O(\ldata_reg[2]_i_1_n_0 ));
LUT5 #(
.INIT(32'hAEAAA2AA))
\ldata_reg[3]_i_1
(.I0(\ldata_reg_reg_n_0_[2] ),
.I1(lrclk_d1),
.I2(Q[1]),
.I3(out[0]),
.I4(\DataTx_L_reg[23] [3]),
.O(\ldata_reg[3]_i_1_n_0 ));
LUT5 #(
.INIT(32'hAEAAA2AA))
\ldata_reg[4]_i_1
(.I0(\ldata_reg_reg_n_0_[3] ),
.I1(lrclk_d1),
.I2(Q[1]),
.I3(out[0]),
.I4(\DataTx_L_reg[23] [4]),
.O(\ldata_reg[4]_i_1_n_0 ));
LUT5 #(
.INIT(32'hAEAAA2AA))
\ldata_reg[5]_i_1
(.I0(\ldata_reg_reg_n_0_[4] ),
.I1(lrclk_d1),
.I2(Q[1]),
.I3(out[0]),
.I4(\DataTx_L_reg[23] [5]),
.O(\ldata_reg[5]_i_1_n_0 ));
LUT5 #(
.INIT(32'hAEAAA2AA))
\ldata_reg[6]_i_1
(.I0(\ldata_reg_reg_n_0_[5] ),
.I1(lrclk_d1),
.I2(Q[1]),
.I3(out[0]),
.I4(\DataTx_L_reg[23] [6]),
.O(\ldata_reg[6]_i_1_n_0 ));
LUT5 #(
.INIT(32'hAEAAA2AA))
\ldata_reg[7]_i_1
(.I0(\ldata_reg_reg_n_0_[6] ),
.I1(lrclk_d1),
.I2(Q[1]),
.I3(out[0]),
.I4(\DataTx_L_reg[23] [7]),
.O(\ldata_reg[7]_i_1_n_0 ));
LUT5 #(
.INIT(32'hAEAAA2AA))
\ldata_reg[8]_i_1
(.I0(\ldata_reg_reg_n_0_[7] ),
.I1(lrclk_d1),
.I2(Q[1]),
.I3(out[0]),
.I4(\DataTx_L_reg[23] [8]),
.O(\ldata_reg[8]_i_1_n_0 ));
LUT5 #(
.INIT(32'hAEAAA2AA))
\ldata_reg[9]_i_1
(.I0(\ldata_reg_reg_n_0_[8] ),
.I1(lrclk_d1),
.I2(Q[1]),
.I3(out[0]),
.I4(\DataTx_L_reg[23] [9]),
.O(\ldata_reg[9]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\ldata_reg_reg[0]
(.C(S_AXI_ACLK),
.CE(\ldata_reg[23]_i_1__0_n_0 ),
.D(\ldata_reg[0]_i_1_n_0 ),
.Q(\ldata_reg_reg_n_0_[0] ),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\ldata_reg_reg[10]
(.C(S_AXI_ACLK),
.CE(\ldata_reg[23]_i_1__0_n_0 ),
.D(\ldata_reg[10]_i_1_n_0 ),
.Q(\ldata_reg_reg_n_0_[10] ),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\ldata_reg_reg[11]
(.C(S_AXI_ACLK),
.CE(\ldata_reg[23]_i_1__0_n_0 ),
.D(\ldata_reg[11]_i_1_n_0 ),
.Q(\ldata_reg_reg_n_0_[11] ),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\ldata_reg_reg[12]
(.C(S_AXI_ACLK),
.CE(\ldata_reg[23]_i_1__0_n_0 ),
.D(\ldata_reg[12]_i_1_n_0 ),
.Q(\ldata_reg_reg_n_0_[12] ),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\ldata_reg_reg[13]
(.C(S_AXI_ACLK),
.CE(\ldata_reg[23]_i_1__0_n_0 ),
.D(\ldata_reg[13]_i_1_n_0 ),
.Q(\ldata_reg_reg_n_0_[13] ),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\ldata_reg_reg[14]
(.C(S_AXI_ACLK),
.CE(\ldata_reg[23]_i_1__0_n_0 ),
.D(\ldata_reg[14]_i_1_n_0 ),
.Q(\ldata_reg_reg_n_0_[14] ),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\ldata_reg_reg[15]
(.C(S_AXI_ACLK),
.CE(\ldata_reg[23]_i_1__0_n_0 ),
.D(\ldata_reg[15]_i_1_n_0 ),
.Q(\ldata_reg_reg_n_0_[15] ),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\ldata_reg_reg[16]
(.C(S_AXI_ACLK),
.CE(\ldata_reg[23]_i_1__0_n_0 ),
.D(\ldata_reg[16]_i_1_n_0 ),
.Q(\ldata_reg_reg_n_0_[16] ),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\ldata_reg_reg[17]
(.C(S_AXI_ACLK),
.CE(\ldata_reg[23]_i_1__0_n_0 ),
.D(\ldata_reg[17]_i_1_n_0 ),
.Q(\ldata_reg_reg_n_0_[17] ),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\ldata_reg_reg[18]
(.C(S_AXI_ACLK),
.CE(\ldata_reg[23]_i_1__0_n_0 ),
.D(\ldata_reg[18]_i_1_n_0 ),
.Q(\ldata_reg_reg_n_0_[18] ),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\ldata_reg_reg[19]
(.C(S_AXI_ACLK),
.CE(\ldata_reg[23]_i_1__0_n_0 ),
.D(\ldata_reg[19]_i_1_n_0 ),
.Q(\ldata_reg_reg_n_0_[19] ),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\ldata_reg_reg[1]
(.C(S_AXI_ACLK),
.CE(\ldata_reg[23]_i_1__0_n_0 ),
.D(\ldata_reg[1]_i_1_n_0 ),
.Q(\ldata_reg_reg_n_0_[1] ),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\ldata_reg_reg[20]
(.C(S_AXI_ACLK),
.CE(\ldata_reg[23]_i_1__0_n_0 ),
.D(\ldata_reg[20]_i_1_n_0 ),
.Q(\ldata_reg_reg_n_0_[20] ),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\ldata_reg_reg[21]
(.C(S_AXI_ACLK),
.CE(\ldata_reg[23]_i_1__0_n_0 ),
.D(\ldata_reg[21]_i_1_n_0 ),
.Q(\ldata_reg_reg_n_0_[21] ),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\ldata_reg_reg[22]
(.C(S_AXI_ACLK),
.CE(\ldata_reg[23]_i_1__0_n_0 ),
.D(\ldata_reg[22]_i_1_n_0 ),
.Q(\ldata_reg_reg_n_0_[22] ),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\ldata_reg_reg[23]
(.C(S_AXI_ACLK),
.CE(\ldata_reg[23]_i_1__0_n_0 ),
.D(\ldata_reg[23]_i_2__0_n_0 ),
.Q(p_2_in),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\ldata_reg_reg[2]
(.C(S_AXI_ACLK),
.CE(\ldata_reg[23]_i_1__0_n_0 ),
.D(\ldata_reg[2]_i_1_n_0 ),
.Q(\ldata_reg_reg_n_0_[2] ),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\ldata_reg_reg[3]
(.C(S_AXI_ACLK),
.CE(\ldata_reg[23]_i_1__0_n_0 ),
.D(\ldata_reg[3]_i_1_n_0 ),
.Q(\ldata_reg_reg_n_0_[3] ),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\ldata_reg_reg[4]
(.C(S_AXI_ACLK),
.CE(\ldata_reg[23]_i_1__0_n_0 ),
.D(\ldata_reg[4]_i_1_n_0 ),
.Q(\ldata_reg_reg_n_0_[4] ),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\ldata_reg_reg[5]
(.C(S_AXI_ACLK),
.CE(\ldata_reg[23]_i_1__0_n_0 ),
.D(\ldata_reg[5]_i_1_n_0 ),
.Q(\ldata_reg_reg_n_0_[5] ),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\ldata_reg_reg[6]
(.C(S_AXI_ACLK),
.CE(\ldata_reg[23]_i_1__0_n_0 ),
.D(\ldata_reg[6]_i_1_n_0 ),
.Q(\ldata_reg_reg_n_0_[6] ),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\ldata_reg_reg[7]
(.C(S_AXI_ACLK),
.CE(\ldata_reg[23]_i_1__0_n_0 ),
.D(\ldata_reg[7]_i_1_n_0 ),
.Q(\ldata_reg_reg_n_0_[7] ),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\ldata_reg_reg[8]
(.C(S_AXI_ACLK),
.CE(\ldata_reg[23]_i_1__0_n_0 ),
.D(\ldata_reg[8]_i_1_n_0 ),
.Q(\ldata_reg_reg_n_0_[8] ),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\ldata_reg_reg[9]
(.C(S_AXI_ACLK),
.CE(\ldata_reg[23]_i_1__0_n_0 ),
.D(\ldata_reg[9]_i_1_n_0 ),
.Q(\ldata_reg_reg_n_0_[9] ),
.R(ldata_reg));
LUT4 #(
.INIT(16'h0800))
\rdata_reg[0]_i_1
(.I0(\DataTx_R_reg[23] [0]),
.I1(out[0]),
.I2(Q[1]),
.I3(lrclk_d1),
.O(p_1_in[0]));
LUT5 #(
.INIT(32'hAEAAA2AA))
\rdata_reg[10]_i_1
(.I0(\rdata_reg_reg_n_0_[9] ),
.I1(lrclk_d1),
.I2(Q[1]),
.I3(out[0]),
.I4(\DataTx_R_reg[23] [10]),
.O(p_1_in[10]));
LUT5 #(
.INIT(32'hAEAAA2AA))
\rdata_reg[11]_i_1
(.I0(\rdata_reg_reg_n_0_[10] ),
.I1(lrclk_d1),
.I2(Q[1]),
.I3(out[0]),
.I4(\DataTx_R_reg[23] [11]),
.O(p_1_in[11]));
LUT5 #(
.INIT(32'hAEAAA2AA))
\rdata_reg[12]_i_1
(.I0(\rdata_reg_reg_n_0_[11] ),
.I1(lrclk_d1),
.I2(Q[1]),
.I3(out[0]),
.I4(\DataTx_R_reg[23] [12]),
.O(p_1_in[12]));
LUT5 #(
.INIT(32'hAEAAA2AA))
\rdata_reg[13]_i_1
(.I0(\rdata_reg_reg_n_0_[12] ),
.I1(lrclk_d1),
.I2(Q[1]),
.I3(out[0]),
.I4(\DataTx_R_reg[23] [13]),
.O(p_1_in[13]));
LUT5 #(
.INIT(32'hAEAAA2AA))
\rdata_reg[14]_i_1
(.I0(\rdata_reg_reg_n_0_[13] ),
.I1(lrclk_d1),
.I2(Q[1]),
.I3(out[0]),
.I4(\DataTx_R_reg[23] [14]),
.O(p_1_in[14]));
LUT5 #(
.INIT(32'hAEAAA2AA))
\rdata_reg[15]_i_1
(.I0(\rdata_reg_reg_n_0_[14] ),
.I1(lrclk_d1),
.I2(Q[1]),
.I3(out[0]),
.I4(\DataTx_R_reg[23] [15]),
.O(p_1_in[15]));
LUT5 #(
.INIT(32'hAEAAA2AA))
\rdata_reg[16]_i_1
(.I0(\rdata_reg_reg_n_0_[15] ),
.I1(lrclk_d1),
.I2(Q[1]),
.I3(out[0]),
.I4(\DataTx_R_reg[23] [16]),
.O(p_1_in[16]));
LUT5 #(
.INIT(32'hAEAAA2AA))
\rdata_reg[17]_i_1
(.I0(\rdata_reg_reg_n_0_[16] ),
.I1(lrclk_d1),
.I2(Q[1]),
.I3(out[0]),
.I4(\DataTx_R_reg[23] [17]),
.O(p_1_in[17]));
LUT5 #(
.INIT(32'hAEAAA2AA))
\rdata_reg[18]_i_1
(.I0(\rdata_reg_reg_n_0_[17] ),
.I1(lrclk_d1),
.I2(Q[1]),
.I3(out[0]),
.I4(\DataTx_R_reg[23] [18]),
.O(p_1_in[18]));
LUT5 #(
.INIT(32'hAEAAA2AA))
\rdata_reg[19]_i_1
(.I0(\rdata_reg_reg_n_0_[18] ),
.I1(lrclk_d1),
.I2(Q[1]),
.I3(out[0]),
.I4(\DataTx_R_reg[23] [19]),
.O(p_1_in[19]));
LUT5 #(
.INIT(32'hAEAAA2AA))
\rdata_reg[1]_i_1
(.I0(\rdata_reg_reg_n_0_[0] ),
.I1(lrclk_d1),
.I2(Q[1]),
.I3(out[0]),
.I4(\DataTx_R_reg[23] [1]),
.O(p_1_in[1]));
LUT5 #(
.INIT(32'hAEAAA2AA))
\rdata_reg[20]_i_1
(.I0(\rdata_reg_reg_n_0_[19] ),
.I1(lrclk_d1),
.I2(Q[1]),
.I3(out[0]),
.I4(\DataTx_R_reg[23] [20]),
.O(p_1_in[20]));
LUT5 #(
.INIT(32'hAEAAA2AA))
\rdata_reg[21]_i_1
(.I0(\rdata_reg_reg_n_0_[20] ),
.I1(lrclk_d1),
.I2(Q[1]),
.I3(out[0]),
.I4(\DataTx_R_reg[23] [21]),
.O(p_1_in[21]));
LUT5 #(
.INIT(32'hAEAAA2AA))
\rdata_reg[22]_i_1
(.I0(\rdata_reg_reg_n_0_[21] ),
.I1(lrclk_d1),
.I2(Q[1]),
.I3(out[0]),
.I4(\DataTx_R_reg[23] [22]),
.O(p_1_in[22]));
LUT5 #(
.INIT(32'hAEAAA2AA))
\rdata_reg[23]_i_2
(.I0(\rdata_reg_reg_n_0_[22] ),
.I1(lrclk_d1),
.I2(Q[1]),
.I3(out[0]),
.I4(\DataTx_R_reg[23] [23]),
.O(p_1_in[23]));
LUT5 #(
.INIT(32'hAEAAA2AA))
\rdata_reg[2]_i_1
(.I0(\rdata_reg_reg_n_0_[1] ),
.I1(lrclk_d1),
.I2(Q[1]),
.I3(out[0]),
.I4(\DataTx_R_reg[23] [2]),
.O(p_1_in[2]));
LUT5 #(
.INIT(32'hAEAAA2AA))
\rdata_reg[3]_i_1
(.I0(\rdata_reg_reg_n_0_[2] ),
.I1(lrclk_d1),
.I2(Q[1]),
.I3(out[0]),
.I4(\DataTx_R_reg[23] [3]),
.O(p_1_in[3]));
LUT5 #(
.INIT(32'hAEAAA2AA))
\rdata_reg[4]_i_1
(.I0(\rdata_reg_reg_n_0_[3] ),
.I1(lrclk_d1),
.I2(Q[1]),
.I3(out[0]),
.I4(\DataTx_R_reg[23] [4]),
.O(p_1_in[4]));
LUT5 #(
.INIT(32'hAEAAA2AA))
\rdata_reg[5]_i_1
(.I0(\rdata_reg_reg_n_0_[4] ),
.I1(lrclk_d1),
.I2(Q[1]),
.I3(out[0]),
.I4(\DataTx_R_reg[23] [5]),
.O(p_1_in[5]));
LUT5 #(
.INIT(32'hAEAAA2AA))
\rdata_reg[6]_i_1
(.I0(\rdata_reg_reg_n_0_[5] ),
.I1(lrclk_d1),
.I2(Q[1]),
.I3(out[0]),
.I4(\DataTx_R_reg[23] [6]),
.O(p_1_in[6]));
LUT5 #(
.INIT(32'hAEAAA2AA))
\rdata_reg[7]_i_1
(.I0(\rdata_reg_reg_n_0_[6] ),
.I1(lrclk_d1),
.I2(Q[1]),
.I3(out[0]),
.I4(\DataTx_R_reg[23] [7]),
.O(p_1_in[7]));
LUT5 #(
.INIT(32'hAEAAA2AA))
\rdata_reg[8]_i_1
(.I0(\rdata_reg_reg_n_0_[7] ),
.I1(lrclk_d1),
.I2(Q[1]),
.I3(out[0]),
.I4(\DataTx_R_reg[23] [8]),
.O(p_1_in[8]));
LUT5 #(
.INIT(32'hAEAAA2AA))
\rdata_reg[9]_i_1
(.I0(\rdata_reg_reg_n_0_[8] ),
.I1(lrclk_d1),
.I2(Q[1]),
.I3(out[0]),
.I4(\DataTx_R_reg[23] [9]),
.O(p_1_in[9]));
FDRE #(
.INIT(1'b0))
\rdata_reg_reg[0]
(.C(S_AXI_ACLK),
.CE(E),
.D(p_1_in[0]),
.Q(\rdata_reg_reg_n_0_[0] ),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\rdata_reg_reg[10]
(.C(S_AXI_ACLK),
.CE(E),
.D(p_1_in[10]),
.Q(\rdata_reg_reg_n_0_[10] ),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\rdata_reg_reg[11]
(.C(S_AXI_ACLK),
.CE(E),
.D(p_1_in[11]),
.Q(\rdata_reg_reg_n_0_[11] ),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\rdata_reg_reg[12]
(.C(S_AXI_ACLK),
.CE(E),
.D(p_1_in[12]),
.Q(\rdata_reg_reg_n_0_[12] ),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\rdata_reg_reg[13]
(.C(S_AXI_ACLK),
.CE(E),
.D(p_1_in[13]),
.Q(\rdata_reg_reg_n_0_[13] ),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\rdata_reg_reg[14]
(.C(S_AXI_ACLK),
.CE(E),
.D(p_1_in[14]),
.Q(\rdata_reg_reg_n_0_[14] ),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\rdata_reg_reg[15]
(.C(S_AXI_ACLK),
.CE(E),
.D(p_1_in[15]),
.Q(\rdata_reg_reg_n_0_[15] ),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\rdata_reg_reg[16]
(.C(S_AXI_ACLK),
.CE(E),
.D(p_1_in[16]),
.Q(\rdata_reg_reg_n_0_[16] ),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\rdata_reg_reg[17]
(.C(S_AXI_ACLK),
.CE(E),
.D(p_1_in[17]),
.Q(\rdata_reg_reg_n_0_[17] ),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\rdata_reg_reg[18]
(.C(S_AXI_ACLK),
.CE(E),
.D(p_1_in[18]),
.Q(\rdata_reg_reg_n_0_[18] ),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\rdata_reg_reg[19]
(.C(S_AXI_ACLK),
.CE(E),
.D(p_1_in[19]),
.Q(\rdata_reg_reg_n_0_[19] ),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\rdata_reg_reg[1]
(.C(S_AXI_ACLK),
.CE(E),
.D(p_1_in[1]),
.Q(\rdata_reg_reg_n_0_[1] ),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\rdata_reg_reg[20]
(.C(S_AXI_ACLK),
.CE(E),
.D(p_1_in[20]),
.Q(\rdata_reg_reg_n_0_[20] ),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\rdata_reg_reg[21]
(.C(S_AXI_ACLK),
.CE(E),
.D(p_1_in[21]),
.Q(\rdata_reg_reg_n_0_[21] ),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\rdata_reg_reg[22]
(.C(S_AXI_ACLK),
.CE(E),
.D(p_1_in[22]),
.Q(\rdata_reg_reg_n_0_[22] ),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\rdata_reg_reg[23]
(.C(S_AXI_ACLK),
.CE(E),
.D(p_1_in[23]),
.Q(\rdata_reg_reg_n_0_[23] ),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\rdata_reg_reg[2]
(.C(S_AXI_ACLK),
.CE(E),
.D(p_1_in[2]),
.Q(\rdata_reg_reg_n_0_[2] ),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\rdata_reg_reg[3]
(.C(S_AXI_ACLK),
.CE(E),
.D(p_1_in[3]),
.Q(\rdata_reg_reg_n_0_[3] ),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\rdata_reg_reg[4]
(.C(S_AXI_ACLK),
.CE(E),
.D(p_1_in[4]),
.Q(\rdata_reg_reg_n_0_[4] ),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\rdata_reg_reg[5]
(.C(S_AXI_ACLK),
.CE(E),
.D(p_1_in[5]),
.Q(\rdata_reg_reg_n_0_[5] ),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\rdata_reg_reg[6]
(.C(S_AXI_ACLK),
.CE(E),
.D(p_1_in[6]),
.Q(\rdata_reg_reg_n_0_[6] ),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\rdata_reg_reg[7]
(.C(S_AXI_ACLK),
.CE(E),
.D(p_1_in[7]),
.Q(\rdata_reg_reg_n_0_[7] ),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\rdata_reg_reg[8]
(.C(S_AXI_ACLK),
.CE(E),
.D(p_1_in[8]),
.Q(\rdata_reg_reg_n_0_[8] ),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\rdata_reg_reg[9]
(.C(S_AXI_ACLK),
.CE(E),
.D(p_1_in[9]),
.Q(\rdata_reg_reg_n_0_[9] ),
.R(ldata_reg));
LUT6 #(
.INIT(64'hFFFFCCAF0000CCA0))
sdata_reg_i_1
(.I0(\rdata_reg_reg_n_0_[23] ),
.I1(p_2_in),
.I2(out[2]),
.I3(p_0_in2_in),
.I4(\clk_cntr_reg[4] ),
.I5(SDATA_O),
.O(sdata_reg_i_1_n_0));
FDRE #(
.INIT(1'b0))
sdata_reg_reg
(.C(S_AXI_ACLK),
.CE(1'b1),
.D(sdata_reg_i_1_n_0),
.Q(SDATA_O),
.R(ldata_reg));
endmodule |
module ip_design_zed_audio_ctrl_0_0_slave_attachment
(\DataTx_R_reg[0] ,
\DataTx_R_reg[0]_0 ,
\DataTx_R_reg[0]_1 ,
\DataTx_R_reg[0]_2 ,
\DataTx_R_reg[0]_3 ,
\DataTx_R_reg[0]_4 ,
S_AXI_RVALID,
S_AXI_BVALID,
data_rdy_bit_reg,
S_AXI_AWREADY,
S_AXI_ARREADY,
E,
\DataTx_L_reg[0] ,
data_rdy_bit_reg_0,
S_AXI_RDATA,
S_AXI_ACLK,
SR,
S_AXI_ARVALID,
S_AXI_ARESETN,
S_AXI_BREADY,
S_AXI_RREADY,
S_AXI_ARADDR,
S_AXI_AWADDR,
S_AXI_AWVALID,
S_AXI_WVALID,
data_rdy_bit,
Q,
\DataTx_L_reg[31] ,
\DataRx_R_reg[23] ,
\DataRx_L_reg[23] ,
\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4] );
output \DataTx_R_reg[0] ;
output \DataTx_R_reg[0]_0 ;
output \DataTx_R_reg[0]_1 ;
output \DataTx_R_reg[0]_2 ;
output \DataTx_R_reg[0]_3 ;
output \DataTx_R_reg[0]_4 ;
output S_AXI_RVALID;
output S_AXI_BVALID;
output data_rdy_bit_reg;
output S_AXI_AWREADY;
output S_AXI_ARREADY;
output [0:0]E;
output [0:0]\DataTx_L_reg[0] ;
output data_rdy_bit_reg_0;
output [31:0]S_AXI_RDATA;
input S_AXI_ACLK;
input [0:0]SR;
input S_AXI_ARVALID;
input S_AXI_ARESETN;
input S_AXI_BREADY;
input S_AXI_RREADY;
input [2:0]S_AXI_ARADDR;
input [2:0]S_AXI_AWADDR;
input S_AXI_AWVALID;
input S_AXI_WVALID;
input data_rdy_bit;
input [31:0]Q;
input [31:0]\DataTx_L_reg[31] ;
input [23:0]\DataRx_R_reg[23] ;
input [23:0]\DataRx_L_reg[23] ;
input \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4] ;
wire [23:0]\DataRx_L_reg[23] ;
wire [23:0]\DataRx_R_reg[23] ;
wire [0:0]\DataTx_L_reg[0] ;
wire [31:0]\DataTx_L_reg[31] ;
wire \DataTx_R_reg[0] ;
wire \DataTx_R_reg[0]_0 ;
wire \DataTx_R_reg[0]_1 ;
wire \DataTx_R_reg[0]_2 ;
wire \DataTx_R_reg[0]_3 ;
wire \DataTx_R_reg[0]_4 ;
wire [0:0]E;
wire \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4] ;
wire \INCLUDE_DPHASE_TIMER.dpto_cnt_reg_n_0_[0] ;
wire \INCLUDE_DPHASE_TIMER.dpto_cnt_reg_n_0_[1] ;
wire \INCLUDE_DPHASE_TIMER.dpto_cnt_reg_n_0_[2] ;
wire [31:0]IP2Bus_Data;
wire I_DECODER_n_46;
wire I_DECODER_n_47;
wire I_DECODER_n_7;
wire I_DECODER_n_8;
wire [31:0]Q;
wire [0:0]SR;
wire S_AXI_ACLK;
wire [2:0]S_AXI_ARADDR;
wire S_AXI_ARESETN;
wire S_AXI_ARREADY;
wire S_AXI_ARVALID;
wire [2:0]S_AXI_AWADDR;
wire S_AXI_AWREADY;
wire S_AXI_AWVALID;
wire S_AXI_BREADY;
wire S_AXI_BVALID;
wire [31:0]S_AXI_RDATA;
wire S_AXI_RREADY;
wire S_AXI_RVALID;
wire S_AXI_WVALID;
wire data_rdy_bit;
wire data_rdy_bit_reg;
wire data_rdy_bit_reg_0;
wire p_2_out;
wire [3:0]plusOp;
wire rst;
wire s_axi_rdata_i;
wire [1:0]state;
wire \state[0]_i_2_n_0 ;
wire \state[1]_i_2_n_0 ;
wire \state[1]_i_3_n_0 ;
wire timeout;
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT1 #(
.INIT(2'h1))
\INCLUDE_DPHASE_TIMER.dpto_cnt[0]_i_1
(.I0(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg_n_0_[0] ),
.O(plusOp[0]));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT2 #(
.INIT(4'h6))
\INCLUDE_DPHASE_TIMER.dpto_cnt[1]_i_1
(.I0(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg_n_0_[0] ),
.I1(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg_n_0_[1] ),
.O(plusOp[1]));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT3 #(
.INIT(8'h78))
\INCLUDE_DPHASE_TIMER.dpto_cnt[2]_i_1
(.I0(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg_n_0_[1] ),
.I1(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg_n_0_[0] ),
.I2(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg_n_0_[2] ),
.O(plusOp[2]));
LUT2 #(
.INIT(4'h9))
\INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_1
(.I0(state[1]),
.I1(state[0]),
.O(p_2_out));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT4 #(
.INIT(16'h7F80))
\INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_2
(.I0(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg_n_0_[2] ),
.I1(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg_n_0_[0] ),
.I2(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg_n_0_[1] ),
.I3(timeout),
.O(plusOp[3]));
FDRE \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[0]
(.C(S_AXI_ACLK),
.CE(1'b1),
.D(plusOp[0]),
.Q(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg_n_0_[0] ),
.R(p_2_out));
FDRE \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[1]
(.C(S_AXI_ACLK),
.CE(1'b1),
.D(plusOp[1]),
.Q(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg_n_0_[1] ),
.R(p_2_out));
FDRE \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[2]
(.C(S_AXI_ACLK),
.CE(1'b1),
.D(plusOp[2]),
.Q(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg_n_0_[2] ),
.R(p_2_out));
FDRE \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]
(.C(S_AXI_ACLK),
.CE(1'b1),
.D(plusOp[3]),
.Q(timeout),
.R(p_2_out));
ip_design_zed_audio_ctrl_0_0_address_decoder I_DECODER
(.D({I_DECODER_n_7,I_DECODER_n_8}),
.\DataRx_L_reg[23] (\DataRx_L_reg[23] ),
.\DataRx_R_reg[23] (\DataRx_R_reg[23] ),
.\DataTx_L_reg[0] (\DataTx_L_reg[0] ),
.\DataTx_L_reg[31] (\DataTx_L_reg[31] ),
.\DataTx_R_reg[0] (\DataTx_R_reg[0] ),
.\DataTx_R_reg[0]_0 (\DataTx_R_reg[0]_0 ),
.\DataTx_R_reg[0]_1 (\DataTx_R_reg[0]_1 ),
.\DataTx_R_reg[0]_2 (\DataTx_R_reg[0]_2 ),
.\DataTx_R_reg[0]_3 (\DataTx_R_reg[0]_3 ),
.\DataTx_R_reg[0]_4 (\DataTx_R_reg[0]_4 ),
.\DataTx_R_reg[31] (Q),
.E(E),
.\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0 (\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4] ),
.\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] (timeout),
.Q(state),
.S_AXI_ACLK(S_AXI_ACLK),
.S_AXI_ARADDR(S_AXI_ARADDR),
.S_AXI_ARESETN(S_AXI_ARESETN),
.S_AXI_ARREADY(S_AXI_ARREADY),
.S_AXI_ARVALID(S_AXI_ARVALID),
.S_AXI_AWADDR(S_AXI_AWADDR),
.S_AXI_AWREADY(S_AXI_AWREADY),
.S_AXI_AWVALID(S_AXI_AWVALID),
.S_AXI_BREADY(S_AXI_BREADY),
.S_AXI_RREADY(S_AXI_RREADY),
.S_AXI_WVALID(S_AXI_WVALID),
.S_AXI_WVALID_0(\state[1]_i_2_n_0 ),
.data_rdy_bit(data_rdy_bit),
.data_rdy_bit_reg(data_rdy_bit_reg),
.data_rdy_bit_reg_0(data_rdy_bit_reg_0),
.s_axi_bvalid_i_reg(I_DECODER_n_47),
.s_axi_bvalid_i_reg_0(\state[0]_i_2_n_0 ),
.s_axi_bvalid_i_reg_1(S_AXI_BVALID),
.\s_axi_rdata_i_reg[31] (IP2Bus_Data),
.s_axi_rvalid_i_reg(I_DECODER_n_46),
.s_axi_rvalid_i_reg_0(S_AXI_RVALID),
.\state_reg[1] (\state[1]_i_3_n_0 ));
FDRE rst_reg
(.C(S_AXI_ACLK),
.CE(1'b1),
.D(SR),
.Q(rst),
.R(1'b0));
FDRE #(
.INIT(1'b0))
s_axi_bvalid_i_reg
(.C(S_AXI_ACLK),
.CE(1'b1),
.D(I_DECODER_n_47),
.Q(S_AXI_BVALID),
.R(rst));
LUT2 #(
.INIT(4'h2))
\s_axi_rdata_i[31]_i_1
(.I0(state[0]),
.I1(state[1]),
.O(s_axi_rdata_i));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[0]
(.C(S_AXI_ACLK),
.CE(s_axi_rdata_i),
.D(IP2Bus_Data[0]),
.Q(S_AXI_RDATA[0]),
.R(rst));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[10]
(.C(S_AXI_ACLK),
.CE(s_axi_rdata_i),
.D(IP2Bus_Data[10]),
.Q(S_AXI_RDATA[10]),
.R(rst));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[11]
(.C(S_AXI_ACLK),
.CE(s_axi_rdata_i),
.D(IP2Bus_Data[11]),
.Q(S_AXI_RDATA[11]),
.R(rst));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[12]
(.C(S_AXI_ACLK),
.CE(s_axi_rdata_i),
.D(IP2Bus_Data[12]),
.Q(S_AXI_RDATA[12]),
.R(rst));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[13]
(.C(S_AXI_ACLK),
.CE(s_axi_rdata_i),
.D(IP2Bus_Data[13]),
.Q(S_AXI_RDATA[13]),
.R(rst));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[14]
(.C(S_AXI_ACLK),
.CE(s_axi_rdata_i),
.D(IP2Bus_Data[14]),
.Q(S_AXI_RDATA[14]),
.R(rst));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[15]
(.C(S_AXI_ACLK),
.CE(s_axi_rdata_i),
.D(IP2Bus_Data[15]),
.Q(S_AXI_RDATA[15]),
.R(rst));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[16]
(.C(S_AXI_ACLK),
.CE(s_axi_rdata_i),
.D(IP2Bus_Data[16]),
.Q(S_AXI_RDATA[16]),
.R(rst));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[17]
(.C(S_AXI_ACLK),
.CE(s_axi_rdata_i),
.D(IP2Bus_Data[17]),
.Q(S_AXI_RDATA[17]),
.R(rst));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[18]
(.C(S_AXI_ACLK),
.CE(s_axi_rdata_i),
.D(IP2Bus_Data[18]),
.Q(S_AXI_RDATA[18]),
.R(rst));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[19]
(.C(S_AXI_ACLK),
.CE(s_axi_rdata_i),
.D(IP2Bus_Data[19]),
.Q(S_AXI_RDATA[19]),
.R(rst));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[1]
(.C(S_AXI_ACLK),
.CE(s_axi_rdata_i),
.D(IP2Bus_Data[1]),
.Q(S_AXI_RDATA[1]),
.R(rst));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[20]
(.C(S_AXI_ACLK),
.CE(s_axi_rdata_i),
.D(IP2Bus_Data[20]),
.Q(S_AXI_RDATA[20]),
.R(rst));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[21]
(.C(S_AXI_ACLK),
.CE(s_axi_rdata_i),
.D(IP2Bus_Data[21]),
.Q(S_AXI_RDATA[21]),
.R(rst));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[22]
(.C(S_AXI_ACLK),
.CE(s_axi_rdata_i),
.D(IP2Bus_Data[22]),
.Q(S_AXI_RDATA[22]),
.R(rst));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[23]
(.C(S_AXI_ACLK),
.CE(s_axi_rdata_i),
.D(IP2Bus_Data[23]),
.Q(S_AXI_RDATA[23]),
.R(rst));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[24]
(.C(S_AXI_ACLK),
.CE(s_axi_rdata_i),
.D(IP2Bus_Data[24]),
.Q(S_AXI_RDATA[24]),
.R(rst));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[25]
(.C(S_AXI_ACLK),
.CE(s_axi_rdata_i),
.D(IP2Bus_Data[25]),
.Q(S_AXI_RDATA[25]),
.R(rst));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[26]
(.C(S_AXI_ACLK),
.CE(s_axi_rdata_i),
.D(IP2Bus_Data[26]),
.Q(S_AXI_RDATA[26]),
.R(rst));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[27]
(.C(S_AXI_ACLK),
.CE(s_axi_rdata_i),
.D(IP2Bus_Data[27]),
.Q(S_AXI_RDATA[27]),
.R(rst));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[28]
(.C(S_AXI_ACLK),
.CE(s_axi_rdata_i),
.D(IP2Bus_Data[28]),
.Q(S_AXI_RDATA[28]),
.R(rst));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[29]
(.C(S_AXI_ACLK),
.CE(s_axi_rdata_i),
.D(IP2Bus_Data[29]),
.Q(S_AXI_RDATA[29]),
.R(rst));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[2]
(.C(S_AXI_ACLK),
.CE(s_axi_rdata_i),
.D(IP2Bus_Data[2]),
.Q(S_AXI_RDATA[2]),
.R(rst));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[30]
(.C(S_AXI_ACLK),
.CE(s_axi_rdata_i),
.D(IP2Bus_Data[30]),
.Q(S_AXI_RDATA[30]),
.R(rst));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[31]
(.C(S_AXI_ACLK),
.CE(s_axi_rdata_i),
.D(IP2Bus_Data[31]),
.Q(S_AXI_RDATA[31]),
.R(rst));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[3]
(.C(S_AXI_ACLK),
.CE(s_axi_rdata_i),
.D(IP2Bus_Data[3]),
.Q(S_AXI_RDATA[3]),
.R(rst));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[4]
(.C(S_AXI_ACLK),
.CE(s_axi_rdata_i),
.D(IP2Bus_Data[4]),
.Q(S_AXI_RDATA[4]),
.R(rst));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[5]
(.C(S_AXI_ACLK),
.CE(s_axi_rdata_i),
.D(IP2Bus_Data[5]),
.Q(S_AXI_RDATA[5]),
.R(rst));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[6]
(.C(S_AXI_ACLK),
.CE(s_axi_rdata_i),
.D(IP2Bus_Data[6]),
.Q(S_AXI_RDATA[6]),
.R(rst));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[7]
(.C(S_AXI_ACLK),
.CE(s_axi_rdata_i),
.D(IP2Bus_Data[7]),
.Q(S_AXI_RDATA[7]),
.R(rst));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[8]
(.C(S_AXI_ACLK),
.CE(s_axi_rdata_i),
.D(IP2Bus_Data[8]),
.Q(S_AXI_RDATA[8]),
.R(rst));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[9]
(.C(S_AXI_ACLK),
.CE(s_axi_rdata_i),
.D(IP2Bus_Data[9]),
.Q(S_AXI_RDATA[9]),
.R(rst));
FDRE #(
.INIT(1'b0))
s_axi_rvalid_i_reg
(.C(S_AXI_ACLK),
.CE(1'b1),
.D(I_DECODER_n_46),
.Q(S_AXI_RVALID),
.R(rst));
LUT6 #(
.INIT(64'h07770000FFFF0000))
\state[0]_i_2
(.I0(S_AXI_BVALID),
.I1(S_AXI_BREADY),
.I2(S_AXI_RREADY),
.I3(S_AXI_RVALID),
.I4(state[0]),
.I5(state[1]),
.O(\state[0]_i_2_n_0 ));
LUT2 #(
.INIT(4'h8))
\state[1]_i_2
(.I0(S_AXI_AWVALID),
.I1(S_AXI_WVALID),
.O(\state[1]_i_2_n_0 ));
LUT5 #(
.INIT(32'h002A2A2A))
\state[1]_i_3
(.I0(state[1]),
.I1(S_AXI_RVALID),
.I2(S_AXI_RREADY),
.I3(S_AXI_BREADY),
.I4(S_AXI_BVALID),
.O(\state[1]_i_3_n_0 ));
FDRE \state_reg[0]
(.C(S_AXI_ACLK),
.CE(1'b1),
.D(I_DECODER_n_8),
.Q(state[0]),
.R(rst));
FDRE \state_reg[1]
(.C(S_AXI_ACLK),
.CE(1'b1),
.D(I_DECODER_n_7),
.Q(state[1]),
.R(rst));
endmodule |
module ip_design_zed_audio_ctrl_0_0_user_logic
(\s_axi_rdata_i_reg[24] ,
Q,
data_rdy_bit,
SDATA_O,
\s_axi_rdata_i_reg[31] ,
\s_axi_rdata_i_reg[31]_0 ,
SR,
\s_axi_rdata_i_reg[23] ,
\s_axi_rdata_i_reg[23]_0 ,
\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg ,
Bus_RNW_reg,
\GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg ,
\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg ,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg ,
\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg ,
S_AXI_ACLK,
S_AXI_ARESETN,
\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4] ,
\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0] ,
SDATA_I,
E,
S_AXI_WDATA,
\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2] );
output \s_axi_rdata_i_reg[24] ;
output [1:0]Q;
output data_rdy_bit;
output SDATA_O;
output [31:0]\s_axi_rdata_i_reg[31] ;
output [31:0]\s_axi_rdata_i_reg[31]_0 ;
output [0:0]SR;
output [23:0]\s_axi_rdata_i_reg[23] ;
output [23:0]\s_axi_rdata_i_reg[23]_0 ;
input \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg ;
input Bus_RNW_reg;
input \GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg ;
input \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg ;
input \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg ;
input \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg ;
input S_AXI_ACLK;
input S_AXI_ARESETN;
input \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4] ;
input \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0] ;
input SDATA_I;
input [0:0]E;
input [31:0]S_AXI_WDATA;
input [0:0]\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2] ;
wire Bus_RNW_reg;
wire [0:0]E;
wire \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg ;
wire \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0] ;
wire \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg ;
wire \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg ;
wire [0:0]\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2] ;
wire \GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg ;
wire \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg ;
wire \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4] ;
wire Inst_iis_deser_n_3;
wire Inst_iis_deser_n_33;
wire Inst_iis_deser_n_34;
wire Inst_iis_deser_n_35;
wire Inst_iis_deser_n_36;
wire Inst_iis_deser_n_37;
wire Inst_iis_deser_n_38;
wire Inst_iis_deser_n_39;
wire Inst_iis_deser_n_40;
wire Inst_iis_deser_n_41;
wire Inst_iis_deser_n_42;
wire Inst_iis_deser_n_43;
wire Inst_iis_deser_n_44;
wire Inst_iis_deser_n_45;
wire Inst_iis_deser_n_46;
wire Inst_iis_deser_n_47;
wire Inst_iis_deser_n_48;
wire Inst_iis_deser_n_49;
wire Inst_iis_deser_n_5;
wire Inst_iis_deser_n_50;
wire Inst_iis_deser_n_51;
wire Inst_iis_deser_n_52;
wire Inst_iis_deser_n_53;
wire Inst_iis_deser_n_54;
wire Inst_iis_deser_n_55;
wire Inst_iis_deser_n_56;
wire Inst_iis_deser_n_6;
wire Inst_iis_deser_n_7;
wire Inst_iis_deser_n_8;
wire Inst_iis_ser_n_1;
wire Inst_iis_ser_n_2;
wire [1:0]Q;
wire SDATA_I;
wire SDATA_O;
wire [0:0]SR;
wire S_AXI_ACLK;
wire S_AXI_ARESETN;
wire [31:0]S_AXI_WDATA;
wire \clk_cntr[10]_i_2_n_0 ;
wire \clk_cntr_reg_n_0_[0] ;
wire \clk_cntr_reg_n_0_[1] ;
wire \clk_cntr_reg_n_0_[2] ;
wire \clk_cntr_reg_n_0_[3] ;
wire \clk_cntr_reg_n_0_[5] ;
wire \clk_cntr_reg_n_0_[6] ;
wire \clk_cntr_reg_n_0_[7] ;
wire \clk_cntr_reg_n_0_[8] ;
wire \clk_cntr_reg_n_0_[9] ;
wire data_rdy;
wire data_rdy_bit;
wire [23:0]ldata_reg;
wire lrclk_d1;
wire p_0_in4_in;
wire [10:0]plusOp__0;
wire [23:0]\s_axi_rdata_i_reg[23] ;
wire [23:0]\s_axi_rdata_i_reg[23]_0 ;
wire \s_axi_rdata_i_reg[24] ;
wire [31:0]\s_axi_rdata_i_reg[31] ;
wire [31:0]\s_axi_rdata_i_reg[31]_0 ;
wire sclk_d1;
wire write_bit;
FDRE #(
.INIT(1'b0))
\DataRx_L_reg[0]
(.C(S_AXI_ACLK),
.CE(data_rdy),
.D(ldata_reg[0]),
.Q(\s_axi_rdata_i_reg[23] [0]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\DataRx_L_reg[10]
(.C(S_AXI_ACLK),
.CE(data_rdy),
.D(ldata_reg[10]),
.Q(\s_axi_rdata_i_reg[23] [10]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\DataRx_L_reg[11]
(.C(S_AXI_ACLK),
.CE(data_rdy),
.D(ldata_reg[11]),
.Q(\s_axi_rdata_i_reg[23] [11]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\DataRx_L_reg[12]
(.C(S_AXI_ACLK),
.CE(data_rdy),
.D(ldata_reg[12]),
.Q(\s_axi_rdata_i_reg[23] [12]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\DataRx_L_reg[13]
(.C(S_AXI_ACLK),
.CE(data_rdy),
.D(ldata_reg[13]),
.Q(\s_axi_rdata_i_reg[23] [13]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\DataRx_L_reg[14]
(.C(S_AXI_ACLK),
.CE(data_rdy),
.D(ldata_reg[14]),
.Q(\s_axi_rdata_i_reg[23] [14]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\DataRx_L_reg[15]
(.C(S_AXI_ACLK),
.CE(data_rdy),
.D(ldata_reg[15]),
.Q(\s_axi_rdata_i_reg[23] [15]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\DataRx_L_reg[16]
(.C(S_AXI_ACLK),
.CE(data_rdy),
.D(ldata_reg[16]),
.Q(\s_axi_rdata_i_reg[23] [16]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\DataRx_L_reg[17]
(.C(S_AXI_ACLK),
.CE(data_rdy),
.D(ldata_reg[17]),
.Q(\s_axi_rdata_i_reg[23] [17]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\DataRx_L_reg[18]
(.C(S_AXI_ACLK),
.CE(data_rdy),
.D(ldata_reg[18]),
.Q(\s_axi_rdata_i_reg[23] [18]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\DataRx_L_reg[19]
(.C(S_AXI_ACLK),
.CE(data_rdy),
.D(ldata_reg[19]),
.Q(\s_axi_rdata_i_reg[23] [19]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\DataRx_L_reg[1]
(.C(S_AXI_ACLK),
.CE(data_rdy),
.D(ldata_reg[1]),
.Q(\s_axi_rdata_i_reg[23] [1]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\DataRx_L_reg[20]
(.C(S_AXI_ACLK),
.CE(data_rdy),
.D(ldata_reg[20]),
.Q(\s_axi_rdata_i_reg[23] [20]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\DataRx_L_reg[21]
(.C(S_AXI_ACLK),
.CE(data_rdy),
.D(ldata_reg[21]),
.Q(\s_axi_rdata_i_reg[23] [21]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\DataRx_L_reg[22]
(.C(S_AXI_ACLK),
.CE(data_rdy),
.D(ldata_reg[22]),
.Q(\s_axi_rdata_i_reg[23] [22]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\DataRx_L_reg[23]
(.C(S_AXI_ACLK),
.CE(data_rdy),
.D(ldata_reg[23]),
.Q(\s_axi_rdata_i_reg[23] [23]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\DataRx_L_reg[2]
(.C(S_AXI_ACLK),
.CE(data_rdy),
.D(ldata_reg[2]),
.Q(\s_axi_rdata_i_reg[23] [2]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\DataRx_L_reg[3]
(.C(S_AXI_ACLK),
.CE(data_rdy),
.D(ldata_reg[3]),
.Q(\s_axi_rdata_i_reg[23] [3]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\DataRx_L_reg[4]
(.C(S_AXI_ACLK),
.CE(data_rdy),
.D(ldata_reg[4]),
.Q(\s_axi_rdata_i_reg[23] [4]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\DataRx_L_reg[5]
(.C(S_AXI_ACLK),
.CE(data_rdy),
.D(ldata_reg[5]),
.Q(\s_axi_rdata_i_reg[23] [5]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\DataRx_L_reg[6]
(.C(S_AXI_ACLK),
.CE(data_rdy),
.D(ldata_reg[6]),
.Q(\s_axi_rdata_i_reg[23] [6]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\DataRx_L_reg[7]
(.C(S_AXI_ACLK),
.CE(data_rdy),
.D(ldata_reg[7]),
.Q(\s_axi_rdata_i_reg[23] [7]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\DataRx_L_reg[8]
(.C(S_AXI_ACLK),
.CE(data_rdy),
.D(ldata_reg[8]),
.Q(\s_axi_rdata_i_reg[23] [8]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\DataRx_L_reg[9]
(.C(S_AXI_ACLK),
.CE(data_rdy),
.D(ldata_reg[9]),
.Q(\s_axi_rdata_i_reg[23] [9]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\DataRx_R_reg[0]
(.C(S_AXI_ACLK),
.CE(data_rdy),
.D(Inst_iis_deser_n_56),
.Q(\s_axi_rdata_i_reg[23]_0 [0]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\DataRx_R_reg[10]
(.C(S_AXI_ACLK),
.CE(data_rdy),
.D(Inst_iis_deser_n_46),
.Q(\s_axi_rdata_i_reg[23]_0 [10]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\DataRx_R_reg[11]
(.C(S_AXI_ACLK),
.CE(data_rdy),
.D(Inst_iis_deser_n_45),
.Q(\s_axi_rdata_i_reg[23]_0 [11]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\DataRx_R_reg[12]
(.C(S_AXI_ACLK),
.CE(data_rdy),
.D(Inst_iis_deser_n_44),
.Q(\s_axi_rdata_i_reg[23]_0 [12]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\DataRx_R_reg[13]
(.C(S_AXI_ACLK),
.CE(data_rdy),
.D(Inst_iis_deser_n_43),
.Q(\s_axi_rdata_i_reg[23]_0 [13]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\DataRx_R_reg[14]
(.C(S_AXI_ACLK),
.CE(data_rdy),
.D(Inst_iis_deser_n_42),
.Q(\s_axi_rdata_i_reg[23]_0 [14]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\DataRx_R_reg[15]
(.C(S_AXI_ACLK),
.CE(data_rdy),
.D(Inst_iis_deser_n_41),
.Q(\s_axi_rdata_i_reg[23]_0 [15]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\DataRx_R_reg[16]
(.C(S_AXI_ACLK),
.CE(data_rdy),
.D(Inst_iis_deser_n_40),
.Q(\s_axi_rdata_i_reg[23]_0 [16]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\DataRx_R_reg[17]
(.C(S_AXI_ACLK),
.CE(data_rdy),
.D(Inst_iis_deser_n_39),
.Q(\s_axi_rdata_i_reg[23]_0 [17]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\DataRx_R_reg[18]
(.C(S_AXI_ACLK),
.CE(data_rdy),
.D(Inst_iis_deser_n_38),
.Q(\s_axi_rdata_i_reg[23]_0 [18]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\DataRx_R_reg[19]
(.C(S_AXI_ACLK),
.CE(data_rdy),
.D(Inst_iis_deser_n_37),
.Q(\s_axi_rdata_i_reg[23]_0 [19]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\DataRx_R_reg[1]
(.C(S_AXI_ACLK),
.CE(data_rdy),
.D(Inst_iis_deser_n_55),
.Q(\s_axi_rdata_i_reg[23]_0 [1]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\DataRx_R_reg[20]
(.C(S_AXI_ACLK),
.CE(data_rdy),
.D(Inst_iis_deser_n_36),
.Q(\s_axi_rdata_i_reg[23]_0 [20]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\DataRx_R_reg[21]
(.C(S_AXI_ACLK),
.CE(data_rdy),
.D(Inst_iis_deser_n_35),
.Q(\s_axi_rdata_i_reg[23]_0 [21]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\DataRx_R_reg[22]
(.C(S_AXI_ACLK),
.CE(data_rdy),
.D(Inst_iis_deser_n_34),
.Q(\s_axi_rdata_i_reg[23]_0 [22]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\DataRx_R_reg[23]
(.C(S_AXI_ACLK),
.CE(data_rdy),
.D(Inst_iis_deser_n_33),
.Q(\s_axi_rdata_i_reg[23]_0 [23]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\DataRx_R_reg[2]
(.C(S_AXI_ACLK),
.CE(data_rdy),
.D(Inst_iis_deser_n_54),
.Q(\s_axi_rdata_i_reg[23]_0 [2]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\DataRx_R_reg[3]
(.C(S_AXI_ACLK),
.CE(data_rdy),
.D(Inst_iis_deser_n_53),
.Q(\s_axi_rdata_i_reg[23]_0 [3]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\DataRx_R_reg[4]
(.C(S_AXI_ACLK),
.CE(data_rdy),
.D(Inst_iis_deser_n_52),
.Q(\s_axi_rdata_i_reg[23]_0 [4]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\DataRx_R_reg[5]
(.C(S_AXI_ACLK),
.CE(data_rdy),
.D(Inst_iis_deser_n_51),
.Q(\s_axi_rdata_i_reg[23]_0 [5]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\DataRx_R_reg[6]
(.C(S_AXI_ACLK),
.CE(data_rdy),
.D(Inst_iis_deser_n_50),
.Q(\s_axi_rdata_i_reg[23]_0 [6]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\DataRx_R_reg[7]
(.C(S_AXI_ACLK),
.CE(data_rdy),
.D(Inst_iis_deser_n_49),
.Q(\s_axi_rdata_i_reg[23]_0 [7]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\DataRx_R_reg[8]
(.C(S_AXI_ACLK),
.CE(data_rdy),
.D(Inst_iis_deser_n_48),
.Q(\s_axi_rdata_i_reg[23]_0 [8]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\DataRx_R_reg[9]
(.C(S_AXI_ACLK),
.CE(data_rdy),
.D(Inst_iis_deser_n_47),
.Q(\s_axi_rdata_i_reg[23]_0 [9]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\DataTx_L_reg[0]
(.C(S_AXI_ACLK),
.CE(E),
.D(S_AXI_WDATA[0]),
.Q(\s_axi_rdata_i_reg[31] [0]),
.R(SR));
FDRE #(
.INIT(1'b0))
\DataTx_L_reg[10]
(.C(S_AXI_ACLK),
.CE(E),
.D(S_AXI_WDATA[10]),
.Q(\s_axi_rdata_i_reg[31] [10]),
.R(SR));
FDRE #(
.INIT(1'b0))
\DataTx_L_reg[11]
(.C(S_AXI_ACLK),
.CE(E),
.D(S_AXI_WDATA[11]),
.Q(\s_axi_rdata_i_reg[31] [11]),
.R(SR));
FDRE #(
.INIT(1'b0))
\DataTx_L_reg[12]
(.C(S_AXI_ACLK),
.CE(E),
.D(S_AXI_WDATA[12]),
.Q(\s_axi_rdata_i_reg[31] [12]),
.R(SR));
FDRE #(
.INIT(1'b0))
\DataTx_L_reg[13]
(.C(S_AXI_ACLK),
.CE(E),
.D(S_AXI_WDATA[13]),
.Q(\s_axi_rdata_i_reg[31] [13]),
.R(SR));
FDRE #(
.INIT(1'b0))
\DataTx_L_reg[14]
(.C(S_AXI_ACLK),
.CE(E),
.D(S_AXI_WDATA[14]),
.Q(\s_axi_rdata_i_reg[31] [14]),
.R(SR));
FDRE #(
.INIT(1'b0))
\DataTx_L_reg[15]
(.C(S_AXI_ACLK),
.CE(E),
.D(S_AXI_WDATA[15]),
.Q(\s_axi_rdata_i_reg[31] [15]),
.R(SR));
FDRE #(
.INIT(1'b0))
\DataTx_L_reg[16]
(.C(S_AXI_ACLK),
.CE(E),
.D(S_AXI_WDATA[16]),
.Q(\s_axi_rdata_i_reg[31] [16]),
.R(SR));
FDRE #(
.INIT(1'b0))
\DataTx_L_reg[17]
(.C(S_AXI_ACLK),
.CE(E),
.D(S_AXI_WDATA[17]),
.Q(\s_axi_rdata_i_reg[31] [17]),
.R(SR));
FDRE #(
.INIT(1'b0))
\DataTx_L_reg[18]
(.C(S_AXI_ACLK),
.CE(E),
.D(S_AXI_WDATA[18]),
.Q(\s_axi_rdata_i_reg[31] [18]),
.R(SR));
FDRE #(
.INIT(1'b0))
\DataTx_L_reg[19]
(.C(S_AXI_ACLK),
.CE(E),
.D(S_AXI_WDATA[19]),
.Q(\s_axi_rdata_i_reg[31] [19]),
.R(SR));
FDRE #(
.INIT(1'b0))
\DataTx_L_reg[1]
(.C(S_AXI_ACLK),
.CE(E),
.D(S_AXI_WDATA[1]),
.Q(\s_axi_rdata_i_reg[31] [1]),
.R(SR));
FDRE #(
.INIT(1'b0))
\DataTx_L_reg[20]
(.C(S_AXI_ACLK),
.CE(E),
.D(S_AXI_WDATA[20]),
.Q(\s_axi_rdata_i_reg[31] [20]),
.R(SR));
FDRE #(
.INIT(1'b0))
\DataTx_L_reg[21]
(.C(S_AXI_ACLK),
.CE(E),
.D(S_AXI_WDATA[21]),
.Q(\s_axi_rdata_i_reg[31] [21]),
.R(SR));
FDRE #(
.INIT(1'b0))
\DataTx_L_reg[22]
(.C(S_AXI_ACLK),
.CE(E),
.D(S_AXI_WDATA[22]),
.Q(\s_axi_rdata_i_reg[31] [22]),
.R(SR));
FDRE #(
.INIT(1'b0))
\DataTx_L_reg[23]
(.C(S_AXI_ACLK),
.CE(E),
.D(S_AXI_WDATA[23]),
.Q(\s_axi_rdata_i_reg[31] [23]),
.R(SR));
FDRE #(
.INIT(1'b0))
\DataTx_L_reg[24]
(.C(S_AXI_ACLK),
.CE(E),
.D(S_AXI_WDATA[24]),
.Q(\s_axi_rdata_i_reg[31] [24]),
.R(SR));
FDRE #(
.INIT(1'b0))
\DataTx_L_reg[25]
(.C(S_AXI_ACLK),
.CE(E),
.D(S_AXI_WDATA[25]),
.Q(\s_axi_rdata_i_reg[31] [25]),
.R(SR));
FDRE #(
.INIT(1'b0))
\DataTx_L_reg[26]
(.C(S_AXI_ACLK),
.CE(E),
.D(S_AXI_WDATA[26]),
.Q(\s_axi_rdata_i_reg[31] [26]),
.R(SR));
FDRE #(
.INIT(1'b0))
\DataTx_L_reg[27]
(.C(S_AXI_ACLK),
.CE(E),
.D(S_AXI_WDATA[27]),
.Q(\s_axi_rdata_i_reg[31] [27]),
.R(SR));
FDRE #(
.INIT(1'b0))
\DataTx_L_reg[28]
(.C(S_AXI_ACLK),
.CE(E),
.D(S_AXI_WDATA[28]),
.Q(\s_axi_rdata_i_reg[31] [28]),
.R(SR));
FDRE #(
.INIT(1'b0))
\DataTx_L_reg[29]
(.C(S_AXI_ACLK),
.CE(E),
.D(S_AXI_WDATA[29]),
.Q(\s_axi_rdata_i_reg[31] [29]),
.R(SR));
FDRE #(
.INIT(1'b0))
\DataTx_L_reg[2]
(.C(S_AXI_ACLK),
.CE(E),
.D(S_AXI_WDATA[2]),
.Q(\s_axi_rdata_i_reg[31] [2]),
.R(SR));
FDRE #(
.INIT(1'b0))
\DataTx_L_reg[30]
(.C(S_AXI_ACLK),
.CE(E),
.D(S_AXI_WDATA[30]),
.Q(\s_axi_rdata_i_reg[31] [30]),
.R(SR));
FDRE #(
.INIT(1'b0))
\DataTx_L_reg[31]
(.C(S_AXI_ACLK),
.CE(E),
.D(S_AXI_WDATA[31]),
.Q(\s_axi_rdata_i_reg[31] [31]),
.R(SR));
FDRE #(
.INIT(1'b0))
\DataTx_L_reg[3]
(.C(S_AXI_ACLK),
.CE(E),
.D(S_AXI_WDATA[3]),
.Q(\s_axi_rdata_i_reg[31] [3]),
.R(SR));
FDRE #(
.INIT(1'b0))
\DataTx_L_reg[4]
(.C(S_AXI_ACLK),
.CE(E),
.D(S_AXI_WDATA[4]),
.Q(\s_axi_rdata_i_reg[31] [4]),
.R(SR));
FDRE #(
.INIT(1'b0))
\DataTx_L_reg[5]
(.C(S_AXI_ACLK),
.CE(E),
.D(S_AXI_WDATA[5]),
.Q(\s_axi_rdata_i_reg[31] [5]),
.R(SR));
FDRE #(
.INIT(1'b0))
\DataTx_L_reg[6]
(.C(S_AXI_ACLK),
.CE(E),
.D(S_AXI_WDATA[6]),
.Q(\s_axi_rdata_i_reg[31] [6]),
.R(SR));
FDRE #(
.INIT(1'b0))
\DataTx_L_reg[7]
(.C(S_AXI_ACLK),
.CE(E),
.D(S_AXI_WDATA[7]),
.Q(\s_axi_rdata_i_reg[31] [7]),
.R(SR));
FDRE #(
.INIT(1'b0))
\DataTx_L_reg[8]
(.C(S_AXI_ACLK),
.CE(E),
.D(S_AXI_WDATA[8]),
.Q(\s_axi_rdata_i_reg[31] [8]),
.R(SR));
FDRE #(
.INIT(1'b0))
\DataTx_L_reg[9]
(.C(S_AXI_ACLK),
.CE(E),
.D(S_AXI_WDATA[9]),
.Q(\s_axi_rdata_i_reg[31] [9]),
.R(SR));
FDRE #(
.INIT(1'b0))
\DataTx_R_reg[0]
(.C(S_AXI_ACLK),
.CE(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2] ),
.D(S_AXI_WDATA[0]),
.Q(\s_axi_rdata_i_reg[31]_0 [0]),
.R(SR));
FDRE #(
.INIT(1'b0))
\DataTx_R_reg[10]
(.C(S_AXI_ACLK),
.CE(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2] ),
.D(S_AXI_WDATA[10]),
.Q(\s_axi_rdata_i_reg[31]_0 [10]),
.R(SR));
FDRE #(
.INIT(1'b0))
\DataTx_R_reg[11]
(.C(S_AXI_ACLK),
.CE(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2] ),
.D(S_AXI_WDATA[11]),
.Q(\s_axi_rdata_i_reg[31]_0 [11]),
.R(SR));
FDRE #(
.INIT(1'b0))
\DataTx_R_reg[12]
(.C(S_AXI_ACLK),
.CE(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2] ),
.D(S_AXI_WDATA[12]),
.Q(\s_axi_rdata_i_reg[31]_0 [12]),
.R(SR));
FDRE #(
.INIT(1'b0))
\DataTx_R_reg[13]
(.C(S_AXI_ACLK),
.CE(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2] ),
.D(S_AXI_WDATA[13]),
.Q(\s_axi_rdata_i_reg[31]_0 [13]),
.R(SR));
FDRE #(
.INIT(1'b0))
\DataTx_R_reg[14]
(.C(S_AXI_ACLK),
.CE(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2] ),
.D(S_AXI_WDATA[14]),
.Q(\s_axi_rdata_i_reg[31]_0 [14]),
.R(SR));
FDRE #(
.INIT(1'b0))
\DataTx_R_reg[15]
(.C(S_AXI_ACLK),
.CE(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2] ),
.D(S_AXI_WDATA[15]),
.Q(\s_axi_rdata_i_reg[31]_0 [15]),
.R(SR));
FDRE #(
.INIT(1'b0))
\DataTx_R_reg[16]
(.C(S_AXI_ACLK),
.CE(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2] ),
.D(S_AXI_WDATA[16]),
.Q(\s_axi_rdata_i_reg[31]_0 [16]),
.R(SR));
FDRE #(
.INIT(1'b0))
\DataTx_R_reg[17]
(.C(S_AXI_ACLK),
.CE(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2] ),
.D(S_AXI_WDATA[17]),
.Q(\s_axi_rdata_i_reg[31]_0 [17]),
.R(SR));
FDRE #(
.INIT(1'b0))
\DataTx_R_reg[18]
(.C(S_AXI_ACLK),
.CE(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2] ),
.D(S_AXI_WDATA[18]),
.Q(\s_axi_rdata_i_reg[31]_0 [18]),
.R(SR));
FDRE #(
.INIT(1'b0))
\DataTx_R_reg[19]
(.C(S_AXI_ACLK),
.CE(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2] ),
.D(S_AXI_WDATA[19]),
.Q(\s_axi_rdata_i_reg[31]_0 [19]),
.R(SR));
FDRE #(
.INIT(1'b0))
\DataTx_R_reg[1]
(.C(S_AXI_ACLK),
.CE(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2] ),
.D(S_AXI_WDATA[1]),
.Q(\s_axi_rdata_i_reg[31]_0 [1]),
.R(SR));
FDRE #(
.INIT(1'b0))
\DataTx_R_reg[20]
(.C(S_AXI_ACLK),
.CE(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2] ),
.D(S_AXI_WDATA[20]),
.Q(\s_axi_rdata_i_reg[31]_0 [20]),
.R(SR));
FDRE #(
.INIT(1'b0))
\DataTx_R_reg[21]
(.C(S_AXI_ACLK),
.CE(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2] ),
.D(S_AXI_WDATA[21]),
.Q(\s_axi_rdata_i_reg[31]_0 [21]),
.R(SR));
FDRE #(
.INIT(1'b0))
\DataTx_R_reg[22]
(.C(S_AXI_ACLK),
.CE(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2] ),
.D(S_AXI_WDATA[22]),
.Q(\s_axi_rdata_i_reg[31]_0 [22]),
.R(SR));
FDRE #(
.INIT(1'b0))
\DataTx_R_reg[23]
(.C(S_AXI_ACLK),
.CE(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2] ),
.D(S_AXI_WDATA[23]),
.Q(\s_axi_rdata_i_reg[31]_0 [23]),
.R(SR));
FDRE #(
.INIT(1'b0))
\DataTx_R_reg[24]
(.C(S_AXI_ACLK),
.CE(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2] ),
.D(S_AXI_WDATA[24]),
.Q(\s_axi_rdata_i_reg[31]_0 [24]),
.R(SR));
FDRE #(
.INIT(1'b0))
\DataTx_R_reg[25]
(.C(S_AXI_ACLK),
.CE(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2] ),
.D(S_AXI_WDATA[25]),
.Q(\s_axi_rdata_i_reg[31]_0 [25]),
.R(SR));
FDRE #(
.INIT(1'b0))
\DataTx_R_reg[26]
(.C(S_AXI_ACLK),
.CE(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2] ),
.D(S_AXI_WDATA[26]),
.Q(\s_axi_rdata_i_reg[31]_0 [26]),
.R(SR));
FDRE #(
.INIT(1'b0))
\DataTx_R_reg[27]
(.C(S_AXI_ACLK),
.CE(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2] ),
.D(S_AXI_WDATA[27]),
.Q(\s_axi_rdata_i_reg[31]_0 [27]),
.R(SR));
FDRE #(
.INIT(1'b0))
\DataTx_R_reg[28]
(.C(S_AXI_ACLK),
.CE(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2] ),
.D(S_AXI_WDATA[28]),
.Q(\s_axi_rdata_i_reg[31]_0 [28]),
.R(SR));
FDRE #(
.INIT(1'b0))
\DataTx_R_reg[29]
(.C(S_AXI_ACLK),
.CE(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2] ),
.D(S_AXI_WDATA[29]),
.Q(\s_axi_rdata_i_reg[31]_0 [29]),
.R(SR));
FDRE #(
.INIT(1'b0))
\DataTx_R_reg[2]
(.C(S_AXI_ACLK),
.CE(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2] ),
.D(S_AXI_WDATA[2]),
.Q(\s_axi_rdata_i_reg[31]_0 [2]),
.R(SR));
FDRE #(
.INIT(1'b0))
\DataTx_R_reg[30]
(.C(S_AXI_ACLK),
.CE(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2] ),
.D(S_AXI_WDATA[30]),
.Q(\s_axi_rdata_i_reg[31]_0 [30]),
.R(SR));
FDRE #(
.INIT(1'b0))
\DataTx_R_reg[31]
(.C(S_AXI_ACLK),
.CE(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2] ),
.D(S_AXI_WDATA[31]),
.Q(\s_axi_rdata_i_reg[31]_0 [31]),
.R(SR));
FDRE #(
.INIT(1'b0))
\DataTx_R_reg[3]
(.C(S_AXI_ACLK),
.CE(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2] ),
.D(S_AXI_WDATA[3]),
.Q(\s_axi_rdata_i_reg[31]_0 [3]),
.R(SR));
FDRE #(
.INIT(1'b0))
\DataTx_R_reg[4]
(.C(S_AXI_ACLK),
.CE(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2] ),
.D(S_AXI_WDATA[4]),
.Q(\s_axi_rdata_i_reg[31]_0 [4]),
.R(SR));
FDRE #(
.INIT(1'b0))
\DataTx_R_reg[5]
(.C(S_AXI_ACLK),
.CE(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2] ),
.D(S_AXI_WDATA[5]),
.Q(\s_axi_rdata_i_reg[31]_0 [5]),
.R(SR));
FDRE #(
.INIT(1'b0))
\DataTx_R_reg[6]
(.C(S_AXI_ACLK),
.CE(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2] ),
.D(S_AXI_WDATA[6]),
.Q(\s_axi_rdata_i_reg[31]_0 [6]),
.R(SR));
FDRE #(
.INIT(1'b0))
\DataTx_R_reg[7]
(.C(S_AXI_ACLK),
.CE(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2] ),
.D(S_AXI_WDATA[7]),
.Q(\s_axi_rdata_i_reg[31]_0 [7]),
.R(SR));
FDRE #(
.INIT(1'b0))
\DataTx_R_reg[8]
(.C(S_AXI_ACLK),
.CE(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2] ),
.D(S_AXI_WDATA[8]),
.Q(\s_axi_rdata_i_reg[31]_0 [8]),
.R(SR));
FDRE #(
.INIT(1'b0))
\DataTx_R_reg[9]
(.C(S_AXI_ACLK),
.CE(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2] ),
.D(S_AXI_WDATA[9]),
.Q(\s_axi_rdata_i_reg[31]_0 [9]),
.R(SR));
ip_design_zed_audio_ctrl_0_0_iis_deser Inst_iis_deser
(.\DataRx_L_reg[23] (ldata_reg),
.\DataRx_R_reg[23] ({Inst_iis_deser_n_33,Inst_iis_deser_n_34,Inst_iis_deser_n_35,Inst_iis_deser_n_36,Inst_iis_deser_n_37,Inst_iis_deser_n_38,Inst_iis_deser_n_39,Inst_iis_deser_n_40,Inst_iis_deser_n_41,Inst_iis_deser_n_42,Inst_iis_deser_n_43,Inst_iis_deser_n_44,Inst_iis_deser_n_45,Inst_iis_deser_n_46,Inst_iis_deser_n_47,Inst_iis_deser_n_48,Inst_iis_deser_n_49,Inst_iis_deser_n_50,Inst_iis_deser_n_51,Inst_iis_deser_n_52,Inst_iis_deser_n_53,Inst_iis_deser_n_54,Inst_iis_deser_n_55,Inst_iis_deser_n_56}),
.E(data_rdy),
.\FSM_onehot_iis_state_reg[0] (Inst_iis_deser_n_6),
.\FSM_onehot_iis_state_reg[0]_0 (Inst_iis_deser_n_8),
.\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0] (\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0] ),
.\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg (\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg ),
.\GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg (\GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg ),
.\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4] (\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4] ),
.Q(Q),
.SDATA_I(SDATA_I),
.S_AXI_ACLK(S_AXI_ACLK),
.S_AXI_ARESETN(S_AXI_ARESETN),
.\bit_cntr_reg[4]_0 (write_bit),
.data_rdy_bit(data_rdy_bit),
.data_rdy_bit_reg(Inst_iis_deser_n_7),
.lrclk_d1(lrclk_d1),
.out({Inst_iis_ser_n_1,Inst_iis_ser_n_2,p_0_in4_in}),
.\rdata_reg_reg[23]_0 (Inst_iis_deser_n_3),
.sclk_d1(sclk_d1),
.sdata_reg_reg(Inst_iis_deser_n_5));
ip_design_zed_audio_ctrl_0_0_iis_ser Inst_iis_ser
(.\DataTx_L_reg[23] (\s_axi_rdata_i_reg[31] [23:0]),
.\DataTx_R_reg[23] (\s_axi_rdata_i_reg[31]_0 [23:0]),
.E(Inst_iis_deser_n_3),
.Q(Q),
.SDATA_O(SDATA_O),
.S_AXI_ACLK(S_AXI_ACLK),
.\clk_cntr_reg[4] (Inst_iis_deser_n_5),
.lrclk_d1(lrclk_d1),
.lrclk_d1_reg(Inst_iis_deser_n_8),
.lrclk_d1_reg_0(Inst_iis_deser_n_6),
.out({Inst_iis_ser_n_1,Inst_iis_ser_n_2,p_0_in4_in}),
.sclk_d1(sclk_d1),
.sclk_d1_reg(write_bit));
LUT1 #(
.INIT(2'h1))
\clk_cntr[0]_i_1
(.I0(\clk_cntr_reg_n_0_[0] ),
.O(plusOp__0[0]));
LUT6 #(
.INIT(64'hF7FFFFFF08000000))
\clk_cntr[10]_i_1
(.I0(\clk_cntr_reg_n_0_[9] ),
.I1(\clk_cntr_reg_n_0_[7] ),
.I2(\clk_cntr[10]_i_2_n_0 ),
.I3(\clk_cntr_reg_n_0_[6] ),
.I4(\clk_cntr_reg_n_0_[8] ),
.I5(Q[1]),
.O(plusOp__0[10]));
LUT6 #(
.INIT(64'h7FFFFFFFFFFFFFFF))
\clk_cntr[10]_i_2
(.I0(Q[0]),
.I1(\clk_cntr_reg_n_0_[2] ),
.I2(\clk_cntr_reg_n_0_[0] ),
.I3(\clk_cntr_reg_n_0_[1] ),
.I4(\clk_cntr_reg_n_0_[3] ),
.I5(\clk_cntr_reg_n_0_[5] ),
.O(\clk_cntr[10]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair16" *)
LUT2 #(
.INIT(4'h6))
\clk_cntr[1]_i_1
(.I0(\clk_cntr_reg_n_0_[0] ),
.I1(\clk_cntr_reg_n_0_[1] ),
.O(plusOp__0[1]));
(* SOFT_HLUTNM = "soft_lutpair16" *)
LUT3 #(
.INIT(8'h78))
\clk_cntr[2]_i_1
(.I0(\clk_cntr_reg_n_0_[1] ),
.I1(\clk_cntr_reg_n_0_[0] ),
.I2(\clk_cntr_reg_n_0_[2] ),
.O(plusOp__0[2]));
(* SOFT_HLUTNM = "soft_lutpair14" *)
LUT4 #(
.INIT(16'h7F80))
\clk_cntr[3]_i_1
(.I0(\clk_cntr_reg_n_0_[2] ),
.I1(\clk_cntr_reg_n_0_[0] ),
.I2(\clk_cntr_reg_n_0_[1] ),
.I3(\clk_cntr_reg_n_0_[3] ),
.O(plusOp__0[3]));
(* SOFT_HLUTNM = "soft_lutpair14" *)
LUT5 #(
.INIT(32'h7FFF8000))
\clk_cntr[4]_i_1
(.I0(\clk_cntr_reg_n_0_[3] ),
.I1(\clk_cntr_reg_n_0_[1] ),
.I2(\clk_cntr_reg_n_0_[0] ),
.I3(\clk_cntr_reg_n_0_[2] ),
.I4(Q[0]),
.O(plusOp__0[4]));
LUT6 #(
.INIT(64'h7FFFFFFF80000000))
\clk_cntr[5]_i_1
(.I0(Q[0]),
.I1(\clk_cntr_reg_n_0_[2] ),
.I2(\clk_cntr_reg_n_0_[0] ),
.I3(\clk_cntr_reg_n_0_[1] ),
.I4(\clk_cntr_reg_n_0_[3] ),
.I5(\clk_cntr_reg_n_0_[5] ),
.O(plusOp__0[5]));
(* SOFT_HLUTNM = "soft_lutpair17" *)
LUT2 #(
.INIT(4'h9))
\clk_cntr[6]_i_1
(.I0(\clk_cntr[10]_i_2_n_0 ),
.I1(\clk_cntr_reg_n_0_[6] ),
.O(plusOp__0[6]));
(* SOFT_HLUTNM = "soft_lutpair17" *)
LUT3 #(
.INIT(8'hD2))
\clk_cntr[7]_i_1
(.I0(\clk_cntr_reg_n_0_[6] ),
.I1(\clk_cntr[10]_i_2_n_0 ),
.I2(\clk_cntr_reg_n_0_[7] ),
.O(plusOp__0[7]));
(* SOFT_HLUTNM = "soft_lutpair15" *)
LUT4 #(
.INIT(16'hDF20))
\clk_cntr[8]_i_1
(.I0(\clk_cntr_reg_n_0_[7] ),
.I1(\clk_cntr[10]_i_2_n_0 ),
.I2(\clk_cntr_reg_n_0_[6] ),
.I3(\clk_cntr_reg_n_0_[8] ),
.O(plusOp__0[8]));
(* SOFT_HLUTNM = "soft_lutpair15" *)
LUT5 #(
.INIT(32'hF7FF0800))
\clk_cntr[9]_i_1
(.I0(\clk_cntr_reg_n_0_[8] ),
.I1(\clk_cntr_reg_n_0_[6] ),
.I2(\clk_cntr[10]_i_2_n_0 ),
.I3(\clk_cntr_reg_n_0_[7] ),
.I4(\clk_cntr_reg_n_0_[9] ),
.O(plusOp__0[9]));
FDRE #(
.INIT(1'b0))
\clk_cntr_reg[0]
(.C(S_AXI_ACLK),
.CE(1'b1),
.D(plusOp__0[0]),
.Q(\clk_cntr_reg_n_0_[0] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\clk_cntr_reg[10]
(.C(S_AXI_ACLK),
.CE(1'b1),
.D(plusOp__0[10]),
.Q(Q[1]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\clk_cntr_reg[1]
(.C(S_AXI_ACLK),
.CE(1'b1),
.D(plusOp__0[1]),
.Q(\clk_cntr_reg_n_0_[1] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\clk_cntr_reg[2]
(.C(S_AXI_ACLK),
.CE(1'b1),
.D(plusOp__0[2]),
.Q(\clk_cntr_reg_n_0_[2] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\clk_cntr_reg[3]
(.C(S_AXI_ACLK),
.CE(1'b1),
.D(plusOp__0[3]),
.Q(\clk_cntr_reg_n_0_[3] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\clk_cntr_reg[4]
(.C(S_AXI_ACLK),
.CE(1'b1),
.D(plusOp__0[4]),
.Q(Q[0]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\clk_cntr_reg[5]
(.C(S_AXI_ACLK),
.CE(1'b1),
.D(plusOp__0[5]),
.Q(\clk_cntr_reg_n_0_[5] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\clk_cntr_reg[6]
(.C(S_AXI_ACLK),
.CE(1'b1),
.D(plusOp__0[6]),
.Q(\clk_cntr_reg_n_0_[6] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\clk_cntr_reg[7]
(.C(S_AXI_ACLK),
.CE(1'b1),
.D(plusOp__0[7]),
.Q(\clk_cntr_reg_n_0_[7] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\clk_cntr_reg[8]
(.C(S_AXI_ACLK),
.CE(1'b1),
.D(plusOp__0[8]),
.Q(\clk_cntr_reg_n_0_[8] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\clk_cntr_reg[9]
(.C(S_AXI_ACLK),
.CE(1'b1),
.D(plusOp__0[9]),
.Q(\clk_cntr_reg_n_0_[9] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
data_rdy_bit_reg
(.C(S_AXI_ACLK),
.CE(1'b1),
.D(Inst_iis_deser_n_7),
.Q(data_rdy_bit),
.R(1'b0));
LUT1 #(
.INIT(2'h1))
rst_i_1
(.I0(S_AXI_ARESETN),
.O(SR));
LUT6 #(
.INIT(64'h0000000400040448))
slv_ip2bus_data
(.I0(\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg ),
.I1(Bus_RNW_reg),
.I2(\GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg ),
.I3(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg ),
.I4(\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg ),
.I5(\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg ),
.O(\s_axi_rdata_i_reg[24] ));
endmodule |
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (strong1, weak0) GSR = GSR_int;
assign (strong1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule |
module RAT_xlconcat_0_0(In0, In1, dout)
/* synthesis syn_black_box black_box_pad_pin="In0[7:0],In1[1:0],dout[9:0]" */;
input [7:0]In0;
input [1:0]In1;
output [9:0]dout;
endmodule |
module grid_AD7490(
input rsi_MRST_reset,
input csi_MCLK_clk,
input [31:0] avs_ctrl_writedata,
output [31:0] avs_ctrl_readdata,
input [3:0] avs_ctrl_address,
input [3:0] avs_ctrl_byteenable,
input avs_ctrl_write,
input avs_ctrl_read,
output avs_ctrl_waitrequest,
input csi_ADCCLK_clk,
output [3:0] aso_adc_channel,
output [15:0] aso_adc_data,
output aso_adc_valid,
input aso_adc_ready,
output coe_DIN,
input coe_DOUT,
output coe_SCLK,
output coe_CSN
);
assign avs_ctrl_readdata = read_data;
assign avs_ctrl_waitrequest = 1'b0;
assign aso_adc_channel = adc_aso_ch;
assign aso_adc_data = {adc_aso_data, 4'b0};
assign aso_adc_valid = adc_aso_valid;
assign coe_DIN = spi_din;
assign spi_dout = coe_DOUT;
assign coe_SCLK = spi_clk;
assign coe_CSN = spi_cs;
reg [31:0] read_data = 0;
reg spi_din = 0, spi_cs = 1, spi_clk = 1;
wire spi_dout;
reg [7:0] state = 0;
reg [7:0] delay = 0;
reg adc_range = 0;
reg adc_coding = 1;
reg adc_reset = 1;
reg [7:0] cnv_delay = 255;
reg [11:0] adc_ch[0:15] = 0;
reg [3:0] adc_addr = 0;
reg [3:0] adc_aso_ch = 0;
reg [11:0] adc_aso_data = 0;
reg adc_aso_valid = 0;
/*
* GRID_MOD_SIZE 0x0
* GRID_MOD_ID 0x4
* ADC_CTRL 0x8
* CNV_DELAY 0xC
* ADC_CH0 0x20
* ADC_CH1 0x22
* ADC_CH2 0x24
* ADC_CH3 0x26
* ADC_CH4 0x28
* ADC_CH5 0x2A
* ADC_CH6 0x2C
* ADC_CH7 0x2E
* ADC_CH8 0x30
* ADC_CH9 0x32
* ADC_CH10 0x34
* ADC_CH11 0x36
* ADC_CH12 0x38
* ADC_CH13 0x3A
* ADC_CH14 0x3C
* ADC_CH15 0x3E
*/
always@(posedge csi_MCLK_clk or posedge rsi_MRST_reset)
begin
if(rsi_MRST_reset) begin
read_data <= 0;
end
else begin
case(avs_ctrl_address)
0: read_data <= 64;
1: read_data <= 32'hEA680003;
2: read_data <= {4'b0, adc_addr, 7'b0, adc_range, 7'b0, adc_coding, 7'b0, adc_reset};
3: read_data <= {24'b0, cnv_delay};
8: read_data <= {adc_ch[1], 4'b0, adc_ch[0], 4'b0};
9: read_data <= {adc_ch[3], 4'b0, adc_ch[2], 4'b0};
10: read_data <= {adc_ch[5], 4'b0, adc_ch[4], 4'b0};
11: read_data <= {adc_ch[7], 4'b0, adc_ch[6], 4'b0};
12: read_data <= {adc_ch[9], 4'b0, adc_ch[8], 4'b0};
13: read_data <= {adc_ch[11], 4'b0, adc_ch[10], 4'b0};
14: read_data <= {adc_ch[13], 4'b0, adc_ch[12], 4'b0};
15: read_data <= {adc_ch[15], 4'b0, adc_ch[14], 4'b0};
default: read_data <= 0;
endcase
end
end
always@(posedge csi_MCLK_clk or posedge rsi_MRST_reset)
begin
if(rsi_MRST_reset) begin
adc_range <= 0;
adc_coding <= 1;
adc_reset <= 1;
cnv_delay <= 255;
end
else begin
if(avs_ctrl_write) begin
case(avs_ctrl_address)
2: begin
if(avs_ctrl_byteenable[2]) adc_range <= avs_ctrl_writedata[16];
if(avs_ctrl_byteenable[1]) adc_coding <= avs_ctrl_writedata[8];
if(avs_ctrl_byteenable[0]) adc_reset <= avs_ctrl_writedata[0];
end
3: begin
if(avs_ctrl_byteenable[0]) cnv_delay <= avs_ctrl_writedata[7:0];
end
default: begin end
endcase
end
end
end
wire rWRITE = 1;
wire rSEQ = 0;
wire rPM1 = 1;
wire rPM0 = 1;
wire rSHADOW = 0;
wire rWEAKTRI = 0;
always@(posedge csi_ADCCLK_clk or posedge adc_reset)
begin
if(adc_reset) begin
adc_ch[0] <= 0;
adc_ch[1] <= 0;
adc_ch[2] <= 0;
adc_ch[3] <= 0;
adc_ch[4] <= 0;
adc_ch[5] <= 0;
adc_ch[6] <= 0;
adc_ch[7] <= 0;
adc_ch[8] <= 0;
adc_ch[9] <= 0;
adc_ch[10] <= 0;
adc_ch[11] <= 0;
adc_ch[12] <= 0;
adc_ch[13] <= 0;
adc_ch[14] <= 0;
adc_ch[15] <= 0;
adc_addr <= 0;
adc_aso_ch <= 0;
adc_aso_data <= 0;
adc_aso_valid <= 0;
spi_din <= 0;
spi_cs <= 1;
spi_clk <= 1;
state <= 0;
delay <= 0;
end
else begin
case(state)
0: begin state <= state + 1; spi_clk <= 1; spi_din <= rWRITE; spi_cs <= 1; delay <= 0; end
1: begin if(delay > cnv_delay) begin delay <= 0; state <= state + 1; end else delay <= delay + 1; end
2: begin state <= state + 1; spi_clk <= 1; spi_din <= rWRITE; spi_cs <= 0; end
3: begin state <= state + 1; spi_clk <= 0; adc_aso_ch[3] <= spi_dout; end
4: begin state <= state + 1; spi_clk <= 1; spi_din <= rSEQ; end
5: begin state <= state + 1; spi_clk <= 0; adc_aso_ch[2] <= spi_dout; end
6: begin state <= state + 1; spi_clk <= 1; spi_din <= adc_addr[3]; end
7: begin state <= state + 1; spi_clk <= 0; adc_aso_ch[1] <= spi_dout; end
8: begin state <= state + 1; spi_clk <= 1; spi_din <= adc_addr[2]; end
9: begin state <= state + 1; spi_clk <= 0; adc_aso_ch[0] <= spi_dout; end
10: begin state <= state + 1; spi_clk <= 1; spi_din <= adc_addr[1]; end
11: begin state <= state + 1; spi_clk <= 0; adc_aso_data[11] <= spi_dout; end
12: begin state <= state + 1; spi_clk <= 1; spi_din <= adc_addr[0]; end
13: begin state <= state + 1; spi_clk <= 0; adc_aso_data[10] <= spi_dout; end
14: begin state <= state + 1; spi_clk <= 1; spi_din <= rPM1; end
15: begin state <= state + 1; spi_clk <= 0; adc_aso_data[9] <= spi_dout; end
16: begin state <= state + 1; spi_clk <= 1; spi_din <= rPM0; end
17: begin state <= state + 1; spi_clk <= 0; adc_aso_data[8] <= spi_dout; end
18: begin state <= state + 1; spi_clk <= 1; spi_din <= rSHADOW; end
19: begin state <= state + 1; spi_clk <= 0; adc_aso_data[7] <= spi_dout; end
20: begin state <= state + 1; spi_clk <= 1; spi_din <= rWEAKTRI; end
21: begin state <= state + 1; spi_clk <= 0; adc_aso_data[6] <= spi_dout; end
22: begin state <= state + 1; spi_clk <= 1; spi_din <= adc_range; end
23: begin state <= state + 1; spi_clk <= 0; adc_aso_data[5] <= spi_dout; end
24: begin state <= state + 1; spi_clk <= 1; spi_din <= adc_coding; end
25: begin state <= state + 1; spi_clk <= 0; adc_aso_data[4] <= spi_dout; end
26: begin state <= state + 1; spi_clk <= 1; spi_din <= 0; end
27: begin state <= state + 1; spi_clk <= 0; adc_aso_data[3] <= spi_dout; end
28: begin state <= state + 1; spi_clk <= 1; end
29: begin state <= state + 1; spi_clk <= 0; adc_aso_data[2] <= spi_dout; end
30: begin state <= state + 1; spi_clk <= 1; end
31: begin state <= state + 1; spi_clk <= 0; adc_aso_data[1] <= spi_dout; end
32: begin state <= state + 1; spi_clk <= 1; end
33: begin state <= state + 1; spi_clk <= 0; adc_aso_data[0] <= spi_dout; end
34: begin state <= state + 1; spi_clk <= 1; adc_ch[adc_aso_ch] <= adc_aso_data; adc_aso_valid <= 1; end
35: begin state <= 0; spi_cs <= 1; adc_aso_valid <= 0; adc_addr <= adc_addr + 1; end
default: begin
adc_ch[0] <= 0;
adc_ch[1] <= 0;
adc_ch[2] <= 0;
adc_ch[3] <= 0;
adc_ch[4] <= 0;
adc_ch[5] <= 0;
adc_ch[6] <= 0;
adc_ch[7] <= 0;
adc_ch[8] <= 0;
adc_ch[9] <= 0;
adc_ch[10] <= 0;
adc_ch[11] <= 0;
adc_ch[12] <= 0;
adc_ch[13] <= 0;
adc_ch[14] <= 0;
adc_ch[15] <= 0;
adc_addr <= 0;
adc_aso_ch <= 0;
adc_aso_data <= 0;
adc_aso_valid <= 0;
spi_din <= 0;
spi_cs <= 1;
spi_clk <= 1;
state <= 0;
delay <= 0;
end
endcase
end
end
endmodule |
module sky130_fd_sc_hs__a2bb2o (
X ,
A1_N,
A2_N,
B1 ,
B2
);
output X ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule |
module Approx_adder_W32 ( add_sub, in1, in2, res );
input [31:0] in1;
input [31:0] in2;
output [32:0] res;
input add_sub;
wire n9, n10, n11, n12, n13, n14, n15, n16, n17, n18, n19, n20, n21, n22,
n23, n24, n25, n26, n27, n28, n29, n30, n31, n32, n33, n34, n35, n36,
n37, n38, n39, n40, n41, n42, n43, n44, n45, n46, n47, n48, n49, n50,
n51, n52, n53, n54, n55, n56, n57, n58, n59, n60, n61, n62, n63, n64,
n65, n66, n67, n68, n69, n70, n71, n72, n73, n74, n75, n76, n77, n78,
n79, n80, n81, n82, n83, n84, n85, n86, n87, n88, n89, n90, n91, n92,
n93, n94, n95, n96, n97, n98, n99, n100, n101, n102, n103, n104, n105,
n106, n107, n108, n109, n110, n111, n112, n113, n114, n115, n116,
n117, n118, n119, n120, n121, n122, n123, n124, n125, n126, n127,
n128, n129, n130, n131, n132, n133, n134, n135, n136, n137, n138,
n139, n140, n141, n142, n143, n144, n145, n146, n147, n148, n149,
n150, n151, n152, n153, n154, n155, n156, n157, n158, n159, n160,
n161, n162, n163, n164, n165, n166, n167, n168, n169, n170, n171,
n172, n173, n174, n175, n176, n177, n178, n179, n180, n181, n182,
n183, n184, n185, n186, n187, n188, n189, n190, n191, n192, n193,
n194, n195, n196, n197, n198, n199, n200, n201, n202, n203, n204,
n205, n206, n207, n208, n209, n210, n211, n212, n213, n214, n215,
n216, n217, n218, n219, n220, n221, n222, n223, n224, n225, n226,
n227, n228, n229, n230, n231, n232, n233, n234, n235, n236, n237,
n238, n239, n240, n241, n242, n243, n244, n246, n247, n248, n249,
n250, n251, n252, n253, n254, n255, n256, n257, n258, n259, n260,
n261, n262, n263, n264, n265, n266, n267, n268, n269, n270, n271,
n272, n273, n274, n275, n276, n277, n278, n279, n280, n281, n282,
n283, n284, n285, n286, n287, n288, n289, n290, n291, n292, n293,
n294, n295, n296, n297, n298, n299, n300, n301, n302, n303, n304,
n305, n306, n307, n308, n309, n310, n311, n312, n313, n314, n315,
n316, n317, n318, n319, n320, n321, n322, n323, n324, n325, n326,
n327, n328, n329, n330, n331, n332, n333, n334, n335, n336, n337,
n338, n339, n340, n341, n342, n343, n344, n345, n346, n347, n348,
n349, n350, n351, n352, n353, n354, n355, n356, n357, n358, n359,
n360, n361, n362, n363, n364, n365, n366, n367, n369, n370;
OAI2BB1X2TS U43 ( .A0N(n264), .A1N(n274), .B0(n19), .Y(res[32]) );
XOR2X2TS U44 ( .A(n204), .B(n203), .Y(res[26]) );
XOR2X2TS U45 ( .A(n239), .B(n238), .Y(res[27]) );
XOR2X2TS U46 ( .A(n244), .B(n243), .Y(res[25]) );
XOR2X2TS U47 ( .A(n248), .B(n247), .Y(res[28]) );
NAND2X1TS U48 ( .A(n237), .B(n89), .Y(n238) );
NAND2X1TS U49 ( .A(n242), .B(n241), .Y(n243) );
NAND2X1TS U50 ( .A(n246), .B(n257), .Y(n247) );
NAND2X1TS U51 ( .A(n228), .B(n256), .Y(n229) );
NAND2X1TS U52 ( .A(n272), .B(n271), .Y(n273) );
NAND2XLTS U53 ( .A(n83), .B(n294), .Y(n295) );
NAND2XLTS U54 ( .A(n86), .B(n291), .Y(n292) );
NAND2XLTS U55 ( .A(n311), .B(n310), .Y(n313) );
NAND2XLTS U56 ( .A(n87), .B(n275), .Y(n276) );
NAND2X1TS U57 ( .A(n285), .B(n284), .Y(n286) );
NAND2X1TS U58 ( .A(n306), .B(n305), .Y(n307) );
NAND2XLTS U59 ( .A(n326), .B(n325), .Y(n327) );
NAND2XLTS U60 ( .A(n301), .B(n300), .Y(n302) );
NAND2X4TS U61 ( .A(n274), .B(n22), .Y(n77) );
OA21XLTS U62 ( .A0(n267), .A1(n271), .B0(n268), .Y(n19) );
OAI21X1TS U63 ( .A0(n308), .A1(n304), .B0(n305), .Y(n303) );
INVX6TS U64 ( .A(n45), .Y(n287) );
NOR2X1TS U65 ( .A(n231), .B(n233), .Y(n236) );
INVX2TS U66 ( .A(n289), .Y(n296) );
CLKBUFX2TS U67 ( .A(n297), .Y(n298) );
OR2X2TS U68 ( .A(n270), .B(n266), .Y(n79) );
NOR2X2TS U69 ( .A(n262), .B(in1[30]), .Y(n265) );
NAND2X2TS U70 ( .A(n263), .B(in1[31]), .Y(n268) );
NAND2X1TS U71 ( .A(n227), .B(in1[29]), .Y(n256) );
CLKMX2X2TS U72 ( .A(in2[30]), .B(n253), .S0(n252), .Y(n262) );
NAND2X2TS U73 ( .A(n219), .B(in1[28]), .Y(n257) );
NAND2X2TS U74 ( .A(n180), .B(in1[22]), .Y(n284) );
NAND2X1TS U75 ( .A(n181), .B(in1[23]), .Y(n280) );
OR2X2TS U76 ( .A(n168), .B(in1[20]), .Y(n83) );
NOR2X2TS U77 ( .A(n299), .B(n304), .Y(n160) );
NAND2X2TS U78 ( .A(n193), .B(in1[24]), .Y(n275) );
CLKMX2X4TS U79 ( .A(in2[29]), .B(n226), .S0(n225), .Y(n227) );
INVX2TS U80 ( .A(n291), .Y(n170) );
OR2X4TS U81 ( .A(n214), .B(in1[27]), .Y(n89) );
NAND2X2TS U82 ( .A(n157), .B(in1[18]), .Y(n305) );
NAND2X2TS U83 ( .A(n158), .B(in1[19]), .Y(n300) );
NOR2X2TS U84 ( .A(n251), .B(in2[30]), .Y(n249) );
CLKMX2X3TS U85 ( .A(in2[23]), .B(n175), .S0(n225), .Y(n181) );
OR2X2TS U86 ( .A(n142), .B(in1[16]), .Y(n82) );
NAND2X2TS U87 ( .A(n169), .B(in1[21]), .Y(n291) );
NOR2X1TS U88 ( .A(n224), .B(n223), .Y(n211) );
MX2X2TS U89 ( .A(in2[25]), .B(n189), .S0(add_sub), .Y(n194) );
MXI2X2TS U90 ( .A(n167), .B(n166), .S0(n225), .Y(n168) );
XOR2X1TS U91 ( .A(n174), .B(n173), .Y(n175) );
OR2X1TS U92 ( .A(n210), .B(in2[27]), .Y(n223) );
INVX4TS U93 ( .A(add_sub), .Y(n353) );
NOR3X2TS U94 ( .A(n176), .B(in2[22]), .C(n184), .Y(n174) );
INVX2TS U95 ( .A(n187), .Y(n153) );
NAND2X1TS U96 ( .A(n206), .B(n205), .Y(n210) );
INVX4TS U97 ( .A(n63), .Y(n61) );
INVX2TS U98 ( .A(in2[20]), .Y(n167) );
NOR2X2TS U99 ( .A(n176), .B(in2[20]), .Y(n163) );
CLKINVX2TS U100 ( .A(n128), .Y(n67) );
INVX2TS U101 ( .A(in2[26]), .Y(n205) );
NAND2X2TS U102 ( .A(n131), .B(in1[14]), .Y(n321) );
NAND2X4TS U103 ( .A(n127), .B(in1[12]), .Y(n330) );
NAND2X2TS U104 ( .A(n18), .B(in1[13]), .Y(n325) );
OR2X2TS U105 ( .A(in2[21]), .B(in2[20]), .Y(n184) );
NOR2X4TS U106 ( .A(in2[17]), .B(in2[16]), .Y(n162) );
XNOR2X2TS U107 ( .A(n112), .B(in2[11]), .Y(n113) );
NOR2X1TS U108 ( .A(in2[19]), .B(in2[18]), .Y(n161) );
OR2X6TS U109 ( .A(n104), .B(in1[8]), .Y(n84) );
CLKINVX6TS U110 ( .A(n346), .Y(n105) );
BUFX4TS U111 ( .A(add_sub), .Y(n252) );
NOR2X2TS U112 ( .A(in2[13]), .B(in2[12]), .Y(n133) );
XNOR2X2TS U113 ( .A(n111), .B(in2[10]), .Y(n93) );
OR2X4TS U114 ( .A(n115), .B(n116), .Y(n111) );
NAND2X6TS U115 ( .A(n52), .B(n350), .Y(n101) );
INVX4TS U116 ( .A(n54), .Y(n97) );
BUFX8TS U117 ( .A(add_sub), .Y(n225) );
INVX8TS U118 ( .A(add_sub), .Y(n94) );
INVX12TS U119 ( .A(in2[3]), .Y(n90) );
CLKINVX6TS U120 ( .A(in2[8]), .Y(n103) );
AND2X2TS U121 ( .A(n118), .B(n117), .Y(n119) );
NAND2X2TS U122 ( .A(in2[6]), .B(add_sub), .Y(n96) );
NOR2X1TS U123 ( .A(n176), .B(n184), .Y(n177) );
AOI21X2TS U124 ( .A0(n89), .A1(n216), .B0(n215), .Y(n217) );
NOR2X4TS U125 ( .A(n219), .B(in1[28]), .Y(n254) );
NOR2XLTS U126 ( .A(n11), .B(in2[2]), .Y(n364) );
OR2X2TS U127 ( .A(n193), .B(in1[24]), .Y(n87) );
OAI21X2TS U128 ( .A0(n220), .A1(n254), .B0(n257), .Y(n221) );
OA21XLTS U129 ( .A0(n336), .A1(n333), .B0(n334), .Y(n20) );
INVX2TS U130 ( .A(n298), .Y(n308) );
NAND2X1TS U131 ( .A(n209), .B(n232), .Y(n203) );
AND2X4TS U132 ( .A(n261), .B(n255), .Y(n9) );
AND2X2TS U133 ( .A(n94), .B(n95), .Y(n10) );
NAND2X2TS U134 ( .A(n92), .B(n352), .Y(n11) );
INVX2TS U135 ( .A(n275), .Y(n240) );
NOR2X4TS U136 ( .A(n227), .B(in1[29]), .Y(n258) );
NOR2X4TS U137 ( .A(n16), .B(n27), .Y(n29) );
INVX2TS U138 ( .A(n260), .Y(n220) );
NOR2X6TS U139 ( .A(n218), .B(n231), .Y(n255) );
INVX3TS U140 ( .A(n267), .Y(n269) );
INVX4TS U141 ( .A(n182), .Y(n46) );
INVX2TS U142 ( .A(n232), .Y(n216) );
NOR2X4TS U143 ( .A(n202), .B(in1[26]), .Y(n233) );
INVX2TS U144 ( .A(n254), .Y(n246) );
NOR2X4TS U145 ( .A(n258), .B(n254), .Y(n261) );
XNOR2X2TS U146 ( .A(n200), .B(in2[26]), .Y(n201) );
XOR2X2TS U147 ( .A(n177), .B(in2[22]), .Y(n178) );
MXI2X4TS U148 ( .A(n192), .B(n191), .S0(n225), .Y(n193) );
NAND2BX2TS U149 ( .AN(n153), .B(n162), .Y(n154) );
NAND2X4TS U150 ( .A(n269), .B(n268), .Y(n270) );
NAND2X4TS U151 ( .A(n209), .B(n89), .Y(n218) );
INVX2TS U152 ( .A(n183), .Y(n42) );
NOR2X4TS U153 ( .A(n196), .B(n195), .Y(n234) );
INVX4TS U154 ( .A(n233), .Y(n209) );
INVX2TS U155 ( .A(n36), .Y(n69) );
OAI21X2TS U156 ( .A0(n258), .A1(n257), .B0(n256), .Y(n259) );
INVX2TS U157 ( .A(n299), .Y(n301) );
INVX4TS U158 ( .A(n190), .Y(n242) );
INVX2TS U159 ( .A(n237), .Y(n215) );
MXI2X4TS U160 ( .A(n205), .B(n201), .S0(n252), .Y(n202) );
NAND2X4TS U161 ( .A(n147), .B(in1[17]), .Y(n310) );
INVX4TS U162 ( .A(n294), .Y(n290) );
MXI2X4TS U163 ( .A(n179), .B(n178), .S0(n252), .Y(n180) );
MX2X4TS U164 ( .A(in2[28]), .B(n212), .S0(n225), .Y(n219) );
NAND2X2TS U165 ( .A(n199), .B(n206), .Y(n200) );
NAND2X2TS U166 ( .A(n142), .B(in1[16]), .Y(n314) );
NOR2X4TS U167 ( .A(n149), .B(n153), .Y(n151) );
OR2X4TS U168 ( .A(n110), .B(in1[10]), .Y(n85) );
INVX6TS U169 ( .A(in2[10]), .Y(n117) );
INVX2TS U170 ( .A(in2[17]), .Y(n144) );
XNOR2X1TS U171 ( .A(n303), .B(n302), .Y(res[19]) );
NAND2X6TS U172 ( .A(n43), .B(n41), .Y(n47) );
XOR2X1TS U173 ( .A(n308), .B(n307), .Y(res[18]) );
NAND2X4TS U174 ( .A(n182), .B(n9), .Y(n71) );
OR2X4TS U175 ( .A(n213), .B(n254), .Y(n222) );
NOR2X4TS U176 ( .A(n16), .B(n79), .Y(n72) );
AND2X2TS U177 ( .A(n63), .B(n25), .Y(n24) );
AND2X2TS U178 ( .A(n270), .B(n272), .Y(n22) );
NOR2X1TS U179 ( .A(n267), .B(n265), .Y(n264) );
XOR2X1TS U180 ( .A(n20), .B(n332), .Y(res[12]) );
INVX2TS U181 ( .A(n231), .Y(n198) );
AND2X2TS U182 ( .A(n281), .B(n280), .Y(n23) );
XOR2X1TS U183 ( .A(n337), .B(n336), .Y(res[11]) );
NOR2X6TS U184 ( .A(n263), .B(in1[31]), .Y(n267) );
CLKAND2X2TS U185 ( .A(n271), .B(n265), .Y(n76) );
XNOR2X2TS U186 ( .A(n249), .B(in2[31]), .Y(n250) );
NOR2X4TS U187 ( .A(n194), .B(in1[25]), .Y(n190) );
NAND2X4TS U188 ( .A(n340), .B(n85), .Y(n37) );
MX2X2TS U189 ( .A(in2[27]), .B(n208), .S0(add_sub), .Y(n214) );
XOR2X1TS U190 ( .A(n345), .B(n13), .Y(res[9]) );
XNOR2X1TS U191 ( .A(n81), .B(in2[29]), .Y(n226) );
NAND2X4TS U192 ( .A(n320), .B(n321), .Y(n63) );
INVX4TS U193 ( .A(n333), .Y(n335) );
NAND2X4TS U194 ( .A(n114), .B(in1[11]), .Y(n334) );
NAND2X4TS U195 ( .A(n104), .B(in1[8]), .Y(n346) );
OAI21XLTS U196 ( .A0(n358), .A1(n353), .B0(n357), .Y(res[6]) );
OAI21XLTS U197 ( .A0(n366), .A1(n353), .B0(n365), .Y(res[3]) );
NAND3X6TS U198 ( .A(n35), .B(n32), .C(n30), .Y(n350) );
OAI21XLTS U199 ( .A0(n361), .A1(n353), .B0(n360), .Y(res[5]) );
OAI21XLTS U200 ( .A0(n363), .A1(n353), .B0(n362), .Y(res[2]) );
OAI21XLTS U201 ( .A0(n370), .A1(n353), .B0(n369), .Y(res[4]) );
OAI21XLTS U202 ( .A0(n355), .A1(n353), .B0(n354), .Y(res[1]) );
OR2X2TS U203 ( .A(in2[18]), .B(n148), .Y(n149) );
CLKINVX6TS U204 ( .A(n11), .Y(n12) );
OR2X1TS U205 ( .A(in2[0]), .B(in1[0]), .Y(res[0]) );
OAI21X4TS U206 ( .A0(n279), .A1(n284), .B0(n280), .Y(n182) );
NOR2X4TS U207 ( .A(n181), .B(in1[23]), .Y(n279) );
NAND3X4TS U208 ( .A(n78), .B(n77), .C(n74), .Y(res[31]) );
MX2X6TS U209 ( .A(in2[13]), .B(n124), .S0(n225), .Y(n18) );
NOR2X4TS U210 ( .A(n61), .B(n60), .Y(n62) );
NAND4X4TS U211 ( .A(n352), .B(n92), .C(n91), .D(n90), .Y(n48) );
XNOR2X2TS U212 ( .A(n154), .B(in2[18]), .Y(n155) );
INVX12TS U213 ( .A(in2[7]), .Y(n49) );
XNOR2X4TS U214 ( .A(n115), .B(in2[8]), .Y(n102) );
AOI21X1TS U215 ( .A0(n347), .A1(n84), .B0(n105), .Y(n13) );
XOR2X2TS U216 ( .A(n134), .B(in2[12]), .Y(n125) );
NOR2X4TS U217 ( .A(n147), .B(in1[17]), .Y(n309) );
MX2X4TS U218 ( .A(in2[17]), .B(n146), .S0(n225), .Y(n147) );
AND4X8TS U219 ( .A(n90), .B(n95), .C(n91), .D(n92), .Y(n14) );
INVX12TS U220 ( .A(in2[6]), .Y(n95) );
INVX12TS U221 ( .A(n277), .Y(n40) );
NAND2X8TS U222 ( .A(n187), .B(n186), .Y(n224) );
NOR4X2TS U223 ( .A(n185), .B(n184), .C(in2[23]), .D(in2[22]), .Y(n186) );
AND2X4TS U224 ( .A(n183), .B(n9), .Y(n80) );
XOR2X1TS U225 ( .A(n176), .B(n167), .Y(n166) );
NOR2X4TS U226 ( .A(n10), .B(n59), .Y(n58) );
NAND2BX4TS U227 ( .AN(in2[29]), .B(n81), .Y(n251) );
NOR3X4TS U228 ( .A(n224), .B(in2[28]), .C(n223), .Y(n81) );
NOR2X2TS U229 ( .A(n99), .B(in2[7]), .Y(n31) );
NAND2X4TS U230 ( .A(n90), .B(n91), .Y(n99) );
XOR2X1TS U231 ( .A(n293), .B(n292), .Y(res[21]) );
AOI21X4TS U232 ( .A0(n296), .A1(n83), .B0(n290), .Y(n293) );
NAND2X4TS U233 ( .A(n168), .B(in1[20]), .Y(n294) );
NAND2BX4TS U234 ( .AN(n185), .B(n187), .Y(n176) );
NOR2X4TS U235 ( .A(in2[25]), .B(in2[24]), .Y(n206) );
OAI21X4TS U236 ( .A0(n234), .A1(n218), .B0(n217), .Y(n260) );
XOR2X2TS U237 ( .A(n163), .B(in2[21]), .Y(n165) );
MXI2X4TS U238 ( .A(n165), .B(n164), .S0(n353), .Y(n169) );
NAND2X4TS U239 ( .A(n86), .B(n83), .Y(n172) );
MX2X4TS U240 ( .A(in2[19]), .B(n152), .S0(add_sub), .Y(n158) );
NAND2X8TS U241 ( .A(n134), .B(n133), .Y(n139) );
NAND2X8TS U242 ( .A(n103), .B(n108), .Y(n116) );
NOR2X4TS U243 ( .A(n224), .B(n210), .Y(n207) );
XNOR2X4TS U244 ( .A(n188), .B(in2[25]), .Y(n189) );
NOR2X4TS U245 ( .A(n224), .B(in2[24]), .Y(n188) );
MXI2X4TS U246 ( .A(n103), .B(n102), .S0(n225), .Y(n104) );
NOR2X6TS U247 ( .A(n70), .B(n334), .Y(n68) );
NAND2X4TS U248 ( .A(n134), .B(n126), .Y(n123) );
INVX2TS U249 ( .A(in2[16]), .Y(n141) );
INVX2TS U250 ( .A(in2[18]), .Y(n156) );
INVX2TS U251 ( .A(in1[7]), .Y(n53) );
NAND2X2TS U252 ( .A(n109), .B(in1[9]), .Y(n342) );
NAND2X4TS U253 ( .A(n110), .B(in1[10]), .Y(n338) );
NOR2X2TS U254 ( .A(n131), .B(in1[14]), .Y(n320) );
NOR2X4TS U255 ( .A(n180), .B(in1[22]), .Y(n283) );
INVX4TS U256 ( .A(n71), .Y(n27) );
INVX2TS U257 ( .A(n116), .Y(n120) );
INVX2TS U258 ( .A(in2[11]), .Y(n118) );
INVX2TS U259 ( .A(n96), .Y(n57) );
OAI21X2TS U260 ( .A0(n96), .A1(n17), .B0(in1[6]), .Y(n59) );
INVX6TS U261 ( .A(in2[9]), .Y(n108) );
INVX2TS U262 ( .A(in2[12]), .Y(n126) );
INVX12TS U263 ( .A(in2[5]), .Y(n51) );
INVX8TS U264 ( .A(in2[4]), .Y(n50) );
CLKAND2X2TS U265 ( .A(n49), .B(add_sub), .Y(n15) );
NAND2X1TS U266 ( .A(n34), .B(in2[7]), .Y(n33) );
INVX2TS U267 ( .A(n99), .Y(n34) );
CLKINVX6TS U268 ( .A(n68), .Y(n28) );
INVX2TS U269 ( .A(n88), .Y(n60) );
XOR2X1TS U270 ( .A(n151), .B(n150), .Y(n152) );
INVX2TS U271 ( .A(in2[19]), .Y(n150) );
INVX2TS U272 ( .A(in2[21]), .Y(n164) );
INVX2TS U273 ( .A(n224), .Y(n199) );
INVX2TS U274 ( .A(n241), .Y(n195) );
NOR2X2TS U275 ( .A(n275), .B(n190), .Y(n196) );
INVX2TS U276 ( .A(n171), .Y(n44) );
INVX2TS U277 ( .A(n255), .Y(n213) );
NOR2X4TS U278 ( .A(n279), .B(n283), .Y(n183) );
INVX2TS U279 ( .A(n314), .Y(n143) );
NOR2X4TS U280 ( .A(n158), .B(in1[19]), .Y(n299) );
OR2X4TS U281 ( .A(n169), .B(in1[21]), .Y(n86) );
CLKBUFX2TS U282 ( .A(n288), .Y(n289) );
NAND2X2TS U283 ( .A(n194), .B(in1[25]), .Y(n241) );
NAND2X4TS U284 ( .A(n202), .B(in1[26]), .Y(n232) );
INVX2TS U285 ( .A(n234), .Y(n197) );
NAND2X2TS U286 ( .A(n214), .B(in1[27]), .Y(n237) );
NAND2X2TS U287 ( .A(n242), .B(n87), .Y(n231) );
OAI21X1TS U288 ( .A0(n234), .A1(n233), .B0(n232), .Y(n235) );
NAND2X1TS U289 ( .A(n270), .B(n271), .Y(n75) );
NOR2XLTS U290 ( .A(n48), .B(in2[4]), .Y(n359) );
NAND2X1TS U291 ( .A(n349), .B(n52), .Y(n351) );
NAND2X1TS U292 ( .A(n84), .B(n346), .Y(n348) );
NAND2X1TS U293 ( .A(n343), .B(n342), .Y(n345) );
INVX2TS U294 ( .A(n341), .Y(n343) );
NAND2X1TS U295 ( .A(n85), .B(n338), .Y(n339) );
NAND2X1TS U296 ( .A(n335), .B(n334), .Y(n337) );
NAND2X1TS U297 ( .A(n331), .B(n330), .Y(n332) );
INVX2TS U298 ( .A(n329), .Y(n331) );
OAI21XLTS U299 ( .A0(n20), .A1(n329), .B0(n330), .Y(n328) );
INVX2TS U300 ( .A(n324), .Y(n326) );
NAND2X1TS U301 ( .A(n322), .B(n321), .Y(n323) );
INVX2TS U302 ( .A(n320), .Y(n322) );
NAND2X1TS U303 ( .A(n88), .B(n317), .Y(n318) );
CLKBUFX2TS U304 ( .A(n64), .Y(n25) );
NAND2X1TS U305 ( .A(n82), .B(n314), .Y(n315) );
XOR2XLTS U306 ( .A(n313), .B(n312), .Y(res[17]) );
INVX2TS U307 ( .A(n309), .Y(n311) );
XNOR2X1TS U308 ( .A(n296), .B(n295), .Y(res[20]) );
XOR2X1TS U309 ( .A(n287), .B(n286), .Y(res[22]) );
INVX2TS U310 ( .A(n283), .Y(n285) );
XOR2X2TS U311 ( .A(n282), .B(n23), .Y(res[23]) );
INVX2TS U312 ( .A(n279), .Y(n281) );
INVX2TS U313 ( .A(n258), .Y(n228) );
OAI21X1TS U314 ( .A0(n270), .A1(n76), .B0(n75), .Y(n74) );
NAND3X2TS U315 ( .A(n73), .B(n72), .C(n71), .Y(n78) );
NAND2X4TS U316 ( .A(n100), .B(n367), .Y(n55) );
NAND3X6TS U317 ( .A(n335), .B(n38), .C(n129), .Y(n36) );
CLKINVX12TS U318 ( .A(n26), .Y(n134) );
XNOR2X2TS U319 ( .A(n139), .B(in2[14]), .Y(n130) );
BUFX8TS U320 ( .A(n278), .Y(n45) );
NOR2X4TS U321 ( .A(in2[8]), .B(n115), .Y(n106) );
INVX8TS U322 ( .A(n115), .Y(n122) );
XNOR2X1TS U323 ( .A(n277), .B(n276), .Y(res[24]) );
NOR2X4TS U324 ( .A(n109), .B(in1[9]), .Y(n341) );
INVX16TS U325 ( .A(in2[0]), .Y(n352) );
NAND2X4TS U326 ( .A(n262), .B(in1[30]), .Y(n271) );
NOR2X4TS U327 ( .A(n157), .B(in1[18]), .Y(n304) );
AO21X4TS U328 ( .A0(n260), .A1(n261), .B0(n259), .Y(n16) );
AND2X8TS U329 ( .A(n50), .B(n51), .Y(n17) );
INVX2TS U330 ( .A(n271), .Y(n266) );
AND4X8TS U331 ( .A(n50), .B(n352), .C(n51), .D(n49), .Y(n21) );
INVX2TS U332 ( .A(n265), .Y(n272) );
INVX2TS U333 ( .A(n38), .Y(n336) );
CLKINVX6TS U334 ( .A(n48), .Y(n367) );
NOR2X4TS U335 ( .A(n114), .B(in1[11]), .Y(n333) );
XOR2X2TS U336 ( .A(n187), .B(in2[16]), .Y(n140) );
NAND2X8TS U337 ( .A(n14), .B(n21), .Y(n115) );
INVX8TS U338 ( .A(n129), .Y(n70) );
NAND2X8TS U339 ( .A(n122), .B(n121), .Y(n26) );
NAND3X8TS U340 ( .A(n55), .B(n58), .C(n56), .Y(n54) );
NOR2X8TS U341 ( .A(n39), .B(n221), .Y(n230) );
AND2X8TS U342 ( .A(n36), .B(n28), .Y(n65) );
AOI21X4TS U343 ( .A0(n347), .A1(n84), .B0(n105), .Y(n344) );
NAND2X8TS U344 ( .A(n101), .B(n349), .Y(n347) );
NAND2X8TS U345 ( .A(n73), .B(n29), .Y(n274) );
NAND2X8TS U346 ( .A(n45), .B(n80), .Y(n73) );
OAI2BB1X4TS U347 ( .A0N(n31), .A1N(n12), .B0(n98), .Y(n30) );
NAND3BX4TS U348 ( .AN(n33), .B(n12), .C(n100), .Y(n32) );
NAND2BX4TS U349 ( .AN(n100), .B(n15), .Y(n35) );
NAND2X8TS U350 ( .A(n64), .B(n62), .Y(n138) );
NAND2X8TS U351 ( .A(n65), .B(n66), .Y(n64) );
NAND2X8TS U352 ( .A(n37), .B(n338), .Y(n38) );
OAI21X4TS U353 ( .A0(n344), .A1(n341), .B0(n342), .Y(n340) );
NOR2X8TS U354 ( .A(n40), .B(n222), .Y(n39) );
AOI21X4TS U355 ( .A0(n171), .A1(n172), .B0(n42), .Y(n41) );
NAND2BX4TS U356 ( .AN(n44), .B(n288), .Y(n43) );
OAI21X2TS U357 ( .A0(n288), .A1(n172), .B0(n171), .Y(n278) );
NAND2X8TS U358 ( .A(n47), .B(n46), .Y(n277) );
XOR2X4TS U359 ( .A(n123), .B(in2[13]), .Y(n124) );
MXI2X8TS U360 ( .A(n126), .B(n125), .S0(n225), .Y(n127) );
MXI2X4TS U361 ( .A(n132), .B(n130), .S0(n252), .Y(n131) );
NAND2X8TS U362 ( .A(n54), .B(n53), .Y(n52) );
NAND2BX4TS U363 ( .AN(n367), .B(n57), .Y(n56) );
NOR3XLTS U364 ( .A(n68), .B(n69), .C(n128), .Y(n319) );
AND2X8TS U365 ( .A(n67), .B(n321), .Y(n66) );
INVX16TS U366 ( .A(in2[1]), .Y(n92) );
INVX16TS U367 ( .A(in2[2]), .Y(n91) );
XNOR2X1TS U368 ( .A(n315), .B(n316), .Y(res[16]) );
XNOR2X1TS U369 ( .A(n348), .B(n347), .Y(res[8]) );
XNOR2X1TS U370 ( .A(n340), .B(n339), .Y(res[10]) );
XNOR2X2TS U371 ( .A(n274), .B(n273), .Y(res[30]) );
OR2X8TS U372 ( .A(n137), .B(in1[15]), .Y(n88) );
MX2X4TS U373 ( .A(in2[11]), .B(n113), .S0(n252), .Y(n114) );
MXI2X4TS U374 ( .A(n117), .B(n93), .S0(n252), .Y(n110) );
AND2X4TS U375 ( .A(n17), .B(n95), .Y(n100) );
NAND2X8TS U376 ( .A(n97), .B(in1[7]), .Y(n349) );
XOR2X1TS U377 ( .A(add_sub), .B(in2[7]), .Y(n98) );
XNOR2X4TS U378 ( .A(n106), .B(n108), .Y(n107) );
MXI2X4TS U379 ( .A(n108), .B(n107), .S0(n225), .Y(n109) );
NOR2X4TS U380 ( .A(n111), .B(in2[10]), .Y(n112) );
AND2X8TS U381 ( .A(n120), .B(n119), .Y(n121) );
NOR2X8TS U382 ( .A(n18), .B(in1[13]), .Y(n324) );
NOR2X8TS U383 ( .A(n127), .B(in1[12]), .Y(n329) );
NOR2X8TS U384 ( .A(n324), .B(n329), .Y(n129) );
OAI21X4TS U385 ( .A0(n324), .A1(n330), .B0(n325), .Y(n128) );
INVX2TS U386 ( .A(in2[14]), .Y(n132) );
NAND3X1TS U387 ( .A(n134), .B(n133), .C(n132), .Y(n135) );
XOR2X1TS U388 ( .A(n135), .B(in2[15]), .Y(n136) );
MX2X4TS U389 ( .A(in2[15]), .B(n136), .S0(n252), .Y(n137) );
NAND2X6TS U390 ( .A(n137), .B(in1[15]), .Y(n317) );
NAND2X8TS U391 ( .A(n138), .B(n317), .Y(n316) );
NOR3X8TS U392 ( .A(n139), .B(in2[15]), .C(in2[14]), .Y(n187) );
MXI2X2TS U393 ( .A(n141), .B(n140), .S0(n252), .Y(n142) );
AOI21X4TS U394 ( .A0(n316), .A1(n82), .B0(n143), .Y(n312) );
NOR2X2TS U395 ( .A(n153), .B(in2[16]), .Y(n145) );
XOR2X1TS U396 ( .A(n145), .B(n144), .Y(n146) );
OAI21X4TS U397 ( .A0(n312), .A1(n309), .B0(n310), .Y(n297) );
INVX2TS U398 ( .A(n162), .Y(n148) );
MXI2X4TS U399 ( .A(n156), .B(n155), .S0(n252), .Y(n157) );
OAI21X4TS U400 ( .A0(n299), .A1(n305), .B0(n300), .Y(n159) );
AOI21X4TS U401 ( .A0(n297), .A1(n160), .B0(n159), .Y(n288) );
NAND2X2TS U402 ( .A(n162), .B(n161), .Y(n185) );
AOI21X4TS U403 ( .A0(n86), .A1(n290), .B0(n170), .Y(n171) );
INVX2TS U404 ( .A(in2[23]), .Y(n173) );
INVX2TS U405 ( .A(in2[22]), .Y(n179) );
INVX2TS U406 ( .A(in2[24]), .Y(n192) );
XNOR2X4TS U407 ( .A(n224), .B(in2[24]), .Y(n191) );
AOI21X4TS U408 ( .A0(n277), .A1(n198), .B0(n197), .Y(n204) );
XNOR2X1TS U409 ( .A(n207), .B(in2[27]), .Y(n208) );
XNOR2X1TS U410 ( .A(n211), .B(in2[28]), .Y(n212) );
XOR2X4TS U411 ( .A(n230), .B(n229), .Y(res[29]) );
AOI21X4TS U412 ( .A0(n277), .A1(n236), .B0(n235), .Y(n239) );
AOI21X4TS U413 ( .A0(n277), .A1(n87), .B0(n240), .Y(n244) );
AOI21X4TS U414 ( .A0(n277), .A1(n255), .B0(n260), .Y(n248) );
MX2X4TS U415 ( .A(in2[31]), .B(n250), .S0(n252), .Y(n263) );
XOR2X1TS U416 ( .A(n251), .B(in2[30]), .Y(n253) );
OAI21X4TS U417 ( .A0(n287), .A1(n283), .B0(n284), .Y(n282) );
INVX2TS U418 ( .A(n304), .Y(n306) );
XNOR2X1TS U419 ( .A(n24), .B(n318), .Y(res[15]) );
XOR2XLTS U420 ( .A(n319), .B(n323), .Y(res[14]) );
XNOR2X1TS U421 ( .A(n328), .B(n327), .Y(res[13]) );
XNOR2X1TS U422 ( .A(n351), .B(n350), .Y(res[7]) );
XOR2X1TS U423 ( .A(n352), .B(in2[1]), .Y(n355) );
AOI21X1TS U424 ( .A0(n94), .A1(in2[1]), .B0(in1[1]), .Y(n354) );
NAND2X1TS U425 ( .A(n367), .B(n17), .Y(n356) );
XNOR2X1TS U426 ( .A(n356), .B(in2[6]), .Y(n358) );
AOI21X1TS U427 ( .A0(n94), .A1(in2[6]), .B0(in1[6]), .Y(n357) );
XOR2X1TS U428 ( .A(n359), .B(in2[5]), .Y(n361) );
AOI21X1TS U429 ( .A0(n94), .A1(in2[5]), .B0(in1[5]), .Y(n360) );
XNOR2X1TS U430 ( .A(n11), .B(in2[2]), .Y(n363) );
AOI21X1TS U431 ( .A0(n353), .A1(in2[2]), .B0(in1[2]), .Y(n362) );
XNOR2X1TS U432 ( .A(n364), .B(n90), .Y(n366) );
AOI21X1TS U433 ( .A0(n94), .A1(in2[3]), .B0(in1[3]), .Y(n365) );
XOR2X1TS U434 ( .A(n367), .B(in2[4]), .Y(n370) );
AOI21X1TS U435 ( .A0(n94), .A1(in2[4]), .B0(in1[4]), .Y(n369) );
initial $sdf_annotate("Approx_adder_LOALPL7_syn.sdf");
endmodule |
module system_clk_wiz_0_0
(clk_out1,
clk_in1);
output clk_out1;
input clk_in1;
(* IBUF_LOW_PWR *) wire clk_in1;
wire clk_out1;
system_clk_wiz_0_0_system_clk_wiz_0_0_clk_wiz inst
(.clk_in1(clk_in1),
.clk_out1(clk_out1));
endmodule |
module system_clk_wiz_0_0_system_clk_wiz_0_0_clk_wiz
(clk_out1,
clk_in1);
output clk_out1;
input clk_in1;
wire clk_in1;
wire clk_in1_system_clk_wiz_0_0;
wire clk_out1;
wire clk_out1_system_clk_wiz_0_0;
wire clkfbout_buf_system_clk_wiz_0_0;
wire clkfbout_system_clk_wiz_0_0;
wire NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT1_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED;
wire NLW_mmcm_adv_inst_DRDY_UNCONNECTED;
wire NLW_mmcm_adv_inst_LOCKED_UNCONNECTED;
wire NLW_mmcm_adv_inst_PSDONE_UNCONNECTED;
wire [15:0]NLW_mmcm_adv_inst_DO_UNCONNECTED;
(* BOX_TYPE = "PRIMITIVE" *)
BUFG clkf_buf
(.I(clkfbout_system_clk_wiz_0_0),
.O(clkfbout_buf_system_clk_wiz_0_0));
(* BOX_TYPE = "PRIMITIVE" *)
(* CAPACITANCE = "DONT_CARE" *)
(* IBUF_DELAY_VALUE = "0" *)
(* IFD_DELAY_VALUE = "AUTO" *)
IBUF #(
.IOSTANDARD("DEFAULT"))
clkin1_ibufg
(.I(clk_in1),
.O(clk_in1_system_clk_wiz_0_0));
(* BOX_TYPE = "PRIMITIVE" *)
BUFG clkout1_buf
(.I(clk_out1_system_clk_wiz_0_0),
.O(clk_out1));
(* BOX_TYPE = "PRIMITIVE" *)
MMCME2_ADV #(
.BANDWIDTH("OPTIMIZED"),
.CLKFBOUT_MULT_F(44.625000),
.CLKFBOUT_PHASE(0.000000),
.CLKFBOUT_USE_FINE_PS("FALSE"),
.CLKIN1_PERIOD(10.000000),
.CLKIN2_PERIOD(0.000000),
.CLKOUT0_DIVIDE_F(75.000000),
.CLKOUT0_DUTY_CYCLE(0.500000),
.CLKOUT0_PHASE(0.000000),
.CLKOUT0_USE_FINE_PS("FALSE"),
.CLKOUT1_DIVIDE(1),
.CLKOUT1_DUTY_CYCLE(0.500000),
.CLKOUT1_PHASE(0.000000),
.CLKOUT1_USE_FINE_PS("FALSE"),
.CLKOUT2_DIVIDE(1),
.CLKOUT2_DUTY_CYCLE(0.500000),
.CLKOUT2_PHASE(0.000000),
.CLKOUT2_USE_FINE_PS("FALSE"),
.CLKOUT3_DIVIDE(1),
.CLKOUT3_DUTY_CYCLE(0.500000),
.CLKOUT3_PHASE(0.000000),
.CLKOUT3_USE_FINE_PS("FALSE"),
.CLKOUT4_CASCADE("FALSE"),
.CLKOUT4_DIVIDE(1),
.CLKOUT4_DUTY_CYCLE(0.500000),
.CLKOUT4_PHASE(0.000000),
.CLKOUT4_USE_FINE_PS("FALSE"),
.CLKOUT5_DIVIDE(1),
.CLKOUT5_DUTY_CYCLE(0.500000),
.CLKOUT5_PHASE(0.000000),
.CLKOUT5_USE_FINE_PS("FALSE"),
.CLKOUT6_DIVIDE(1),
.CLKOUT6_DUTY_CYCLE(0.500000),
.CLKOUT6_PHASE(0.000000),
.CLKOUT6_USE_FINE_PS("FALSE"),
.COMPENSATION("ZHOLD"),
.DIVCLK_DIVIDE(5),
.IS_CLKINSEL_INVERTED(1'b0),
.IS_PSEN_INVERTED(1'b0),
.IS_PSINCDEC_INVERTED(1'b0),
.IS_PWRDWN_INVERTED(1'b0),
.IS_RST_INVERTED(1'b0),
.REF_JITTER1(0.010000),
.REF_JITTER2(0.010000),
.SS_EN("FALSE"),
.SS_MODE("CENTER_HIGH"),
.SS_MOD_PERIOD(10000),
.STARTUP_WAIT("FALSE"))
mmcm_adv_inst
(.CLKFBIN(clkfbout_buf_system_clk_wiz_0_0),
.CLKFBOUT(clkfbout_system_clk_wiz_0_0),
.CLKFBOUTB(NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED),
.CLKFBSTOPPED(NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED),
.CLKIN1(clk_in1_system_clk_wiz_0_0),
.CLKIN2(1'b0),
.CLKINSEL(1'b1),
.CLKINSTOPPED(NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED),
.CLKOUT0(clk_out1_system_clk_wiz_0_0),
.CLKOUT0B(NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED),
.CLKOUT1(NLW_mmcm_adv_inst_CLKOUT1_UNCONNECTED),
.CLKOUT1B(NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED),
.CLKOUT2(NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED),
.CLKOUT2B(NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED),
.CLKOUT3(NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED),
.CLKOUT3B(NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED),
.CLKOUT4(NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED),
.CLKOUT5(NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED),
.CLKOUT6(NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED),
.DADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DCLK(1'b0),
.DEN(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DO(NLW_mmcm_adv_inst_DO_UNCONNECTED[15:0]),
.DRDY(NLW_mmcm_adv_inst_DRDY_UNCONNECTED),
.DWE(1'b0),
.LOCKED(NLW_mmcm_adv_inst_LOCKED_UNCONNECTED),
.PSCLK(1'b0),
.PSDONE(NLW_mmcm_adv_inst_PSDONE_UNCONNECTED),
.PSEN(1'b0),
.PSINCDEC(1'b0),
.PWRDWN(1'b0),
.RST(1'b0));
endmodule |
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule |
module sky130_fd_sc_hdll__and4bb (
X ,
A_N,
B_N,
C ,
D
);
output X ;
input A_N;
input B_N;
input C ;
input D ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule |
module instead of seperate busses to keep design tidy and easier to follow
parameter MEM_WIDTH = ADDR_WIDTH+DATA_WIDTH;
reg [MEM_WIDTH-1:0] mem [0:8];
reg start;//need to be used to make sure initial statements are correct
reg done;//needs to know when data becomes irrelevant and can stop hardware
always@(posedge clk)
begin:Main_Module
case(rst)
1'b0:
if(ena==1'b1 && start==1'b0)begin
start <= 1'b1;
done <= 1'b0;
memIn_addr <= {ADDR_WIDTH{1'b0}};
memOut_addr <= {ADDR_WIDTH{1'b0}};
data_out <= {DATA_WIDTH{1'b0}};
mem_wr_ena <= 1'b0;
end else
if(ena==1'b1) begin:Encryption
begin:Stage_FetchData
if(data_in!=={DATA_WIDTH{1'bx}})begin//bad practice but good assumption
mem[0] <= {memIn_addr-1,data_in};//decrement address since process happens one clock cycle in the future
memIn_addr <= memIn_addr+1;//increment m ram address
end else begin
done <= 1'b1;
mem[0] <= {MEM_WIDTH{1'b0}};
end
end
begin:Stage0_Stage3_Stage7_AddRoundKey//XOR with pin append address to the end
mem[1] <= |mem[0]==1'b0 ? mem[0] : {mem[0][ADDR_WIDTH+DATA_WIDTH-1:DATA_WIDTH],
mem[0][DATA_WIDTH-1:0] ^ key};
mem[4] <= |mem[3]==1'b0 ? mem[3] : {mem[3][ADDR_WIDTH+DATA_WIDTH-1:DATA_WIDTH],
mem[3][DATA_WIDTH-1:0] ^ key};
mem[8] <= |mem[7]==1'b0 ? mem[7] : {mem[7][ADDR_WIDTH+DATA_WIDTH-1:DATA_WIDTH],
mem[7][DATA_WIDTH-1:0] ^ key};
end
begin:Stage2_Stage6_SubBytes//Replace each byte according to loopup table
//Due to complexity and time constraint instead use 2's compliment
mem[3] <= |mem[2]==1'b0 ? mem[2] : {mem[2][ADDR_WIDTH+DATA_WIDTH-1:DATA_WIDTH],
~mem[2][DATA_WIDTH-1:0]+1'b1};
mem[7] <= |mem[6]==1'b0 ? mem[6] : {mem[6][ADDR_WIDTH+DATA_WIDTH-1:DATA_WIDTH],
~mem[6][DATA_WIDTH-1:0]+1'b1};
end
begin:Stage1_Stage5_ShiftRows
mem[2] <= |mem[1]==1'b0 ? mem[1] : {mem[1][ADDR_WIDTH+DATA_WIDTH-1:DATA_WIDTH],
mem[1][shift:0],mem[1][DATA_WIDTH-1:shift+1]};//>>mem[1][ADDR_WIDTH+DATA_WIDTH-1:DATA_WIDTH]};
mem[6] <= |mem[5]==1'b0 ? mem[5] : {mem[5][ADDR_WIDTH+DATA_WIDTH-1:DATA_WIDTH],
mem[5][shift:0],mem[5][DATA_WIDTH-1:shift+1]};//<<mem[5][ADDR_WIDTH+DATA_WIDTH-1:DATA_WIDTH]};
end
begin:Stage4_MixColumns//multMatrix by a set amount...this section is not implimented correctly
//due to time constraints data data by address
mem[5] <= |mem[4]==1'b0 ? mem[4] : {mem[4][ADDR_WIDTH+DATA_WIDTH-1:DATA_WIDTH],
mem[4][DATA_WIDTH-1:0]-mem[4][ADDR_WIDTH+DATA_WIDTH-1:DATA_WIDTH]};
end
begin:Stage8_Push_Data//if Performing Bitwise & on all bits doesn't return 0 or 1 then no more data needs to be processed
//placing & infront of a signal performs the AND operator on all bits
if(mem[8]!=={MEM_WIDTH{1'b0}})begin
mem_wr_ena <= 1'b1;
memOut_addr <= mem[8][ADDR_WIDTH+DATA_WIDTH-1:DATA_WIDTH];
data_out <= mem[8][DATA_WIDTH-1:0];
end
else if (done==1'b1) begin
finished <= 1'b1;
start <=1'b0;
done <= 1'b0;
mem_wr_ena <= 1'b0;
memIn_addr <= {ADDR_WIDTH{1'b0}};
memOut_addr <= {ADDR_WIDTH{1'b0}};
data_out <= {DATA_WIDTH{1'b0}};
$display("Decryption Completed");
end
end
end
1'b1:
begin:Reset
start <=1'b0;
done <= 1'b0;
finished <= 1'b0;
mem_wr_ena <= 1'b0;
memIn_addr <= {ADDR_WIDTH{1'b0}};
memOut_addr <= {ADDR_WIDTH{1'b0}};
data_out <= {DATA_WIDTH{1'b0}};
mem[0] <= {MEM_WIDTH{1'b0}};
mem[1] <= {MEM_WIDTH{1'b0}};
mem[2] <= {MEM_WIDTH{1'b0}};
mem[3] <= {MEM_WIDTH{1'b0}};
mem[4] <= {MEM_WIDTH{1'b0}};
mem[5] <= {MEM_WIDTH{1'b0}};
mem[6] <= {MEM_WIDTH{1'b0}};
mem[7] <= {MEM_WIDTH{1'b0}};
mem[8] <= {MEM_WIDTH{1'b0}};
end
endcase
end
endmodule |
module timeunit;
initial $timeformat(-9,1," ns",9);
endmodule |
module TOP;
wire in;
reg out0, out1, out2, out3, out;
clk_gen #(.HALF_PERIOD(1)) clk(in);
// prsim stuff
initial
begin
// @haco@ interleave-a.haco-c
$prsim("interleave-a.haco-c");
$prsim_cmd("echo $start of simulation");
$prsim_cmd("watchall");
$prsim_cmd("timing after");
$to_prsim("TOP.in", "in0");
$to_prsim("TOP.out0", "in1");
$to_prsim("TOP.out1", "in2");
$to_prsim("TOP.out2", "in3");
$to_prsim("TOP.out3", "in4");
$from_prsim("out0","TOP.out0");
$from_prsim("out1","TOP.out1");
$from_prsim("out2","TOP.out2");
$from_prsim("out3","TOP.out3");
$from_prsim("out4","TOP.out");
end
initial #6 $finish;
initial
$monitor("@%6.3f: out=%d,%d,%d,%d,%d", $realtime,
out0, out1, out2, out3, out);
endmodule |
module CORDIC_Arch3 #(parameter W = 32, parameter EW = 8, parameter SW = 23, parameter SWR=26, parameter EWR = 5)//*/
/*#(parameter W = 64, parameter EW = 11, parameter SW = 52, parameter SWR = 55, parameter EWR = 6) //-- Double Precision */
(
//Input Signals
input wire clk, // Reloj del sistema.
input wire rst, // Señal de reset del sistema.
input wire beg_fsm_cordic, // Señal de inicio de la maquina de estados del módulo CORDIC.
input wire ack_cordic, // Señal de acknowledge proveniente de otro módulo que indica que ha recibido el resultado del modulo CORDIC.
input wire operation, // Señal que indica si se realiza la operacion seno(1'b1) o coseno(1'b0).
input wire [W-1:0] data_in, // Dato de entrada, contiene el angulo que se desea calcular en radianes.
input wire [1:0] shift_region_flag, // Señal que indica si el ángulo a calcular esta fuera del rango de calculo del algoritmo CORDIC.
//input wire [1:0] r_mode,
//Output Signals
output wire ready_cordic, // Señal de salida que indica que se ha completado el calculo del seno/coseno.
output wire overflow_flag, // Bandera de overflow de la operacion.
output wire underflow_flag,
output wire zero_flag,
output wire busy,
output wire [W-1:0] data_output // Bus de datos con el valor final del angulo calculado.
);
//localparam d_var = 0; // Valor por defecto que se le carga al contador de variables.
//localparam d_iter = 0; // Valor por defecto que se le carga al contador de iteraciones.
localparam mode = 1'b0;
localparam iter_bits = 4; //Modificar valor para obtener diferente cantidad de iteraciones; ejem= 3=8iter, 4=16iter. etc
wire [W-1:0] x0,y0;
//%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
generate
case(W)
32:
begin : INITVALBLK1
assign x0 = 32'h3f1b74ee; // x0 = 0.607252935008881, valor inicial de la variable X.
assign y0 = 32'h00000000; // y0 = 0, valor inicial de la variable Y.
end
64:
begin : INITVALBLK2
assign x0 = 64'h3fe36e9db5086bc9; // x0 = 0.607252935008881, valor inicial de la variable X.
assign y0 = 64'h0000000000000000; // y0 = 0, valor inicial de la variable Y.
end
default:
begin : INITVALBLK3
assign x0 = 32'h3f1b74ee; // x0 = 0.607252935008881, valor inicial de la variable X.
assign y0 = 32'h00000000; // y0 = 0, valor inicial de la variable Y.
end
endcase
endgenerate
//%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
//--------------------------------------------------------------------------------------------------------------------------------------------------------------------------
//Signal declaration
//wire reset_reg_cordic;
//ENABLE
wire enab_d_ff_RB1; // Enable de la primera linea de registros.
wire enab_d_ff2_RB2; // Enable de la segunda linea de registros.
wire enab_RB3; // Enable del registro que guarda el valor del signo, dependiendo del modo del algoritmo.
wire enab_d_ff4_Xn, enab_d_ff4_Yn, enab_d_ff4_Zn; // Enable de los registros que guardan los datos provenientes del modulo de suma/resta.
wire enab_d_ff5_data_out; // Enable del registo que guarda el valor de salida final, listo para enviarse al procesador.
wire enab_cont_iter, enab_cont_var; // Enable de los contadores de variable e iteracion
//wire load_cont_iter, load_cont_var; // Señal de carga de un valor en los contadores de variable e iteraciones.
wire enab_dff_5;
//SELECTION
wire sel_mux_3; // Señales de seleccion provenientes de la maquina de estados.
wire [1:0] sel_mux_2; // Señal de seleccion que se activa dependiendo de la variable que se este calculando.
wire sel_mux_1_reg, sel_mux_3_reg; // Señales de seleccion provenientes de la maquina de estados.
wire [1:0] sel_mux_2_reg; // Señal de seleccion que se activa dependiendo de la variable que se este calculando.
//DATA WIRES
wire d_ff1_operation_out; // Salida del registro que guarda el dato de entrada de la operacion a realizar, coseno(1'b0) o seno(1'b1)
wire [1:0] d_ff1_shift_region_flag_out; // Salida del registro que guarda el dato de entrada que indica si el ángulo a calcular esta fuera del rango de calculo del algoritmo CORDIC.
wire [W-1:0] d_ff1_Z; // Salidas de los registros que guardan los valores iniciales de las variables X, Y y Z.
wire [W-1:0] d_ff_Xn, d_ff_Yn, d_ff_Zn; // Salidas de los registros que guardan los valores de las variables X, Y y Z despues de cada iteracion.
wire [W-1:0] first_mux_X, first_mux_Y, first_mux_Z; // Salidas de los mux que escogen entre un valor inicial y el valor obtenido en una iteracion.
wire [W-1:0] d_ff2_X, d_ff2_Y, d_ff2_Z; // Salidas de los registros que guardan los valores provenientes de la primera linea de mux.
wire sign; // Salida del mux que escoge entre el signo de Y o Z, dependiendo del modo, ya sea rotacion o vectorizacion.
wire [W-1:0] data_out_LUT; // Salida del modulo generate que genera la LUT necesaria dependiendo del ancho de palabra.
wire [iter_bits-1:0] cont_iter_out; // Salida del contador que cuenta las iteraciones realizadas.
wire [EW-1:0] sh_exp_x, sh_exp_y; // Salidas de los sumadores de punto fijo que realizan los desplazamientos.
wire [W-1:0] d_ff3_sh_x_out, d_ff3_sh_y_out; // Salida del registro que guarda el valor de X y Y luego de realizar los desplazamientos.
wire [W-1:0] d_ff3_LUT_out; // Salida del registro que guarda el valor de la LUT.
wire d_ff3_sign_out; // Salida del registro que guarda el valor del signo.
wire [1:0] cont_var_out; // Salida del contador que cuenta las variables calculadas.
wire [W-1:0] mux_sal; // Salida del mux final para colocar en la salida el valor deseado.
wire [W-1:0] data_output2; // Salida del registro antes del cambio de signo.
wire [W-1:0] fmtted_Result; // Salida del modulo de inversion de signo, dependiendo de si se el angulo de entrada estaba fuera del rango de calculo del algoritmo CORDIC.
wire min_tick_iter,max_tick_iter; // Señales que indican cuando se ha alcanzado el valor mas bajo y masalto de cuenta, correspondientemente en el contador de iteraciones.
wire min_tick_var,max_tick_var; // Señales que indican cuando se ha alcanzado el valor mas bajo y masalto de cuenta, correspondientemente en el contador de variables.
//wire enab_reg_sel_mux1,enab_reg_sel_mux2,enab_reg_sel_mux3;
wire ready_add_subt; // Señal que indica que se ha realizado la operacion de suma/resta en punto flotante.
wire [W-1:0] result_add_subt; // Dato de entrada, contiene el resultado del módulo de suma/resta.
wire beg_add_subt; // Señal de salida que indica que se debe de iniciar el modulo de suma/resta.
wire ack_add_subt; // Señal que le indica al modulo de suma/resta que se recibio el resultado de este modulo correctamente.
wire op_add_subt; // Señal hacia el módulo de suma/resta que indica si se va a realizar una suma(1'b0) o una resta(1'b1).
wire [W-1:0] add_subt_dataA; // Bus de datos hacia el modulo de suma/resta con el valor al que se le desea aplicar dicha operacion.
wire [W-1:0] add_subt_dataB; // Bus de datos hacia el modulo de suma/resta con el valor al que se le desea aplicar dicha operacion.
//Instanciación
//------------------------------------------------------------------------------------------------------------------------
//FSM
CORDIC_FSM_v3 inst_CORDIC_FSM_v3
(
.clk (clk),
.reset (rst),
.beg_FSM_CORDIC (beg_fsm_cordic),
.ACK_FSM_CORDIC (ack_cordic),
.exception (1'b0),
.max_tick_iter (max_tick_iter),
.max_tick_var (max_tick_var),
.enab_dff_z (enab_d_ff4_Zn),
// .reset_reg_cordic (reset_reg_cordic),
.ready_CORDIC (ready_cordic),
.beg_add_subt (beg_add_subt),
.enab_cont_iter (enab_cont_iter),
.enab_cont_var (enab_cont_var),
.enab_RB1 (enab_d_ff_RB1),
.enab_RB2 (enab_d_ff2_RB2),
.enab_RB3 (enab_RB3),
.enab_d_ff5_data_out (enab_d_ff5_data_out)
);
Up_counter #(.COUNTER_WIDTH(iter_bits)
) ITER_CONT (
.clk (clk),
.rst (rst),
.enable (enab_cont_iter),
.c_output_W (cont_iter_out)
);
assign max_tick_iter = (cont_iter_out == ((2**iter_bits)-1)) ? 1'b1 : 1'b0;
assign min_tick_iter = (cont_iter_out == 0) ? 1'b1 : 1'b0;
//Son dos, ya que son 3 variables a ser operadas por el FPADD
Up_counter #(.COUNTER_WIDTH(2)
) VAR_CONT (
.clk (clk),
.rst (rst),
.enable (ready_add_subt|enab_cont_var),
.c_output_W (cont_var_out)
);
assign max_tick_var = (cont_var_out == 2**2-1) ? 1'b1 : 1'b0;
//--------------------------------------------------------------------------------------------------------------------------------------------------------
//Primera Etapa: Registros que guardan los valores iniciales.
d_ff_en # (.W(1)) reg_operation
(
.clk(clk),//system clock
.rst(rst), //system reset
.enable(enab_d_ff_RB1), //load signal
.D(operation), //input signal
.Q(d_ff1_operation_out) //output signal
);
d_ff_en # (.W(2)) reg_region_flag
(
.clk(clk),//system clock
.rst(rst), //system reset
.enable(enab_d_ff_RB1), //load signal
.D(shift_region_flag), //input signal
.Q(d_ff1_shift_region_flag_out) //output signal
);
d_ff_en # (.W(W)) reg_Z0
(
.clk(clk),//system clock
.rst(rst), //system reset
.enable(enab_d_ff_RB1), //load signal
.D(data_in), //input signal
.Q(d_ff1_Z) //output signal
);
//--------------------------------------------------------------------------------------------------------------------------------------------------------
//Segunda Etapa : Registros que guardan el canal elegido para el mux, asi como los mux.
Mux_2x1 #(.W(W)) mux1_x0
(
.select(~min_tick_iter),
.ch_0(x0),
.ch_1(d_ff_Xn),
.data_out(first_mux_X)
);
Mux_2x1 #(.W(W)) mux1_y0
(
.select(~min_tick_iter),
.ch_0(y0),
.ch_1(d_ff_Yn),
.data_out(first_mux_Y)
);
Mux_2x1 #(.W(W)) mux1_z0
(
.select(~min_tick_iter),
.ch_0(d_ff1_Z),
.ch_1(d_ff_Zn),
.data_out(first_mux_Z)
);
//----------------------------------------------------------------------------------------------------------------------
//Tercera Etapa: Registros que guardan los datos provenientes de los mux.
d_ff_en # (.W(W)) reg_val_muxX_2stage
(
.clk(clk),//system clock
.rst(rst), //system reset
.enable(enab_d_ff2_RB2), //load signal
.D(first_mux_X), //input signal
.Q(d_ff2_X) //output signal
);
d_ff_en # (.W(W)) reg_val_muxY_2stage
(
.clk(clk),//system clock
.rst(rst), //system reset
.enable(enab_d_ff2_RB2), //load signal
.D(first_mux_Y), //input signal
.Q(d_ff2_Y) //output signal
);
d_ff_en # (.W(W)) reg_val_muxZ_2stage
(
.clk(clk),//system clock
.rst(rst), //system reset
.enable(enab_d_ff2_RB2), //load signal
.D(first_mux_Z), //input signal
.Q(d_ff2_Z) //output signal
);
//----------------------------------------------------------------------------------------------------------------------
//Cuarta Etapa : Restadores para el corrimiento del exponente de X y Y, Lookup-Table y mux de signo dependiendo del modo.
Simple_Subt #(.W(EW),.N(iter_bits)) shift_x
(
.A(d_ff2_X[W-2:SW]),
.B(cont_iter_out),
.Y(sh_exp_x)
);
Simple_Subt #(.W(EW),.N(iter_bits)) shift_y
(
.A(d_ff2_Y[W-2:SW]),
.B(cont_iter_out),
.Y(sh_exp_y)
);
//%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
generate
case(W)
32:
begin : LUTBLK1
LUT_CASE_32bits #(.W(W),.N(iter_bits)) LUT32
(
.address(cont_iter_out),
.data_out(data_out_LUT)
);
end
64:
begin : LUTBLK2
LUT_CASE_64bits #(.W(W),.N(iter_bits)) LUT64
(
.address(cont_iter_out),
.data_out(data_out_LUT)
);
end
default:
begin : LUTBLK3
LUT_CASE_32bits #(.W(W),.N(iter_bits)) LUT32
(
.address(cont_iter_out),
.data_out(data_out_LUT)
);
end
endcase
endgenerate
//%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
Mux_2x1 #(.W(1)) mux_sign
(
.select(mode),
.ch_0(d_ff2_Z[W-1]),
.ch_1(d_ff2_Y[W-1]),
.data_out(sign)
);
//-------------------------------------------------------------------------------------------------------------------------
//Quinta Etapa : Registros que guardan los datos provenientes de la etapa anterior.
d_ff_en # (.W(W)) reg_shift_x
(
.clk(clk),//system clock
.rst(rst), //system reset
.enable(enab_RB3), //load signal
.D({d_ff2_X[W-1],sh_exp_x,d_ff2_X[SW-1:0]}), //input signal
.Q(d_ff3_sh_x_out) //output signal
);
d_ff_en # (.W(W)) reg_shift_y
(
.clk(clk),//system clock
.rst(rst), //system reset
.enable(enab_RB3), //load signal
.D({d_ff2_Y[W-1],sh_exp_y,d_ff2_Y[SW-1:0]}), //input signal
.Q(d_ff3_sh_y_out) //output signal
);
d_ff_en # (.W(W)) reg_LUT
(
.clk(clk),//system clock
.rst(rst), //system reset
.enable(enab_RB3), //load signal
.D(data_out_LUT), //input signal
.Q(d_ff3_LUT_out) //output signal
);
d_ff_en # (.W(1)) reg_sign
(
.clk(clk),//system clock
.rst(rst), //system reset
.enable(enab_RB3), //load signal
.D(sign), //input signal
.Q(d_ff3_sign_out) //output signal
);
//-------------------------------------------------------------------------------------------------------------------------------------------------------
//Sexta Etapa : Mux de 3 canales que se activan dependiendo de la variable a calcular.
Mux_3x1_bv2 #(.W(W)) mux_3x1_var1
(
.select(cont_var_out),
.ch_0(d_ff2_X),
.ch_1(d_ff2_Y),
.ch_2(d_ff2_Z),
.data_out(add_subt_dataA)
);
Mux_3x1_bv2 #(.W(W)) mux_3x1_var2
(
.select (cont_var_out),
.ch_0 (d_ff3_sh_y_out),
.ch_1 (d_ff3_sh_x_out),
.ch_2 (d_ff3_LUT_out),
.data_out(add_subt_dataB)
);
PriorityEncoder_CORDIC inst_PriorityEncoder_CORDIC (
.enable(ready_add_subt),
.Data_i(cont_var_out),
.Data_o({enab_d_ff4_Zn,enab_d_ff4_Yn,enab_d_ff4_Xn})
);
Op_Select op_select_mod
(
.variable (~cont_var_out[0]),
.sign (d_ff3_sign_out),
.operation(op_add_subt)
);
//--------------------------------------------------------------------------------------------------------------------------------
//Septima Etapa : Instanciamiento del módulo de suma y resta.
FPU_PIPELINED_FPADDSUB #(
.W(W),
.EW(EW),
.SW(SW),
.SWR(SWR),
.EWR(EWR)
) inst_FPU_PIPELINED_FPADDSUB (
.clk (clk),
.rst (rst|enab_cont_iter),
// .beg_OP (enab_cont_var),
.beg_OP (beg_add_subt),
.Data_X (add_subt_dataA),
.Data_Y (add_subt_dataB),
.add_subt (op_add_subt),
.busy (busy),
.overflow_flag (overflow_flag),
.underflow_flag (underflow_flag),
.zero_flag (zero_flag),
.ready (ready_add_subt),
.final_result_ieee (result_add_subt)
);
//-------------------------------------------------------------------------------------------------------------------------------
//Octava Etapa: Registros que guardan los valores de calculo del modulo de suma y resta.
d_ff_en #(.W(W)) d_ff4_Xn
(
.clk (clk),
.rst (rst),
.enable(enab_d_ff4_Xn),
.D (result_add_subt),
.Q (d_ff_Xn)
);
d_ff_en #(.W(W)) d_ff4_Yn
(
.clk (clk),
.rst (rst),
.enable(enab_d_ff4_Yn),
.D (result_add_subt),
.Q (d_ff_Yn)
);
d_ff_en #(.W(W)) d_ff4_Zn
(
.clk (clk),
.rst (rst),
.enable(enab_d_ff4_Zn),
.D (result_add_subt),
.Q (d_ff_Zn)
);
//--------------------------------------------------------------------------------------------------------------------------------
//Novena Etapa: Mux de selección del valor de salida, así como el modulo de correccion de signo y los registros intermedios que
//guardan los datos de salida.
//Aca se decodifica el signo del resultado final
//y ademas se decodifica cual resultado vamos a escoger.
Mux_2x1 #(
.W(W)
) mux_2x1_sal (
.select (sel_mux_3),
.ch_0 (d_ff_Xn),
.ch_1 (d_ff_Yn),
.data_out (mux_sal)
);
DECO_CORDIC_EXT #(
.W(W)
) inst_DECO_CORDIC_EXT (
.data_i (mux_sal),
.operation (d_ff1_operation_out),
.shift_region_flag (d_ff1_shift_region_flag_out),
.sel_mux_3 (sel_mux_3),
.data_out_CORDECO (fmtted_Result)
);
d_ff_en #(.W(W)) d_ff5_data_out
(
.clk (clk),
.rst (rst),
.enable(enab_d_ff5_data_out),
.D (fmtted_Result),
.Q (data_output)
);
endmodule |
module fifo#(
parameter DATA_WIDTH = 8, // 8-bits data (default)
parameter ADDR_WIDTH = 8 // 8-bits address (default)
)(
input clk,
input rst,
input enqueue, // Insert data
input dequeue, // Remove data
input [(DATA_WIDTH-1):0] data_i, // Input data
output [(DATA_WIDTH-1):0] data_o, // Output data
output reg [(ADDR_WIDTH):0] count, // How many elements are in the FIFO (0->256)
output empty, // Empty flag
output full // Full flag
);
//--------------------------------------------------------------------------
// wires
//--------------------------------------------------------------------------
wire w_enqueue;
wire w_dequeue;
wire [(DATA_WIDTH-1):0] w_data_o;
//--------------------------------------------------------------------------
// registers
//--------------------------------------------------------------------------
reg [(ADDR_WIDTH-1):0] enqueue_ptr; // Addresses for reading from and writing to internal memory
reg [(ADDR_WIDTH-1):0] dequeue_ptr; // Addresses for reading from and writing to internal memory
//--------------------------------------------------------------------------
// Assignments
//--------------------------------------------------------------------------
assign empty = (count == 0);
assign full = (count == (1 << ADDR_WIDTH));
assign w_enqueue = (full) ? 1'b0 : enqueue; // Ignore if full
assign w_dequeue = (empty) ? 1'b0 : dequeue; // Ignore if empty
assign data_o = (empty) ? ((enqueue & dequeue) ? data_i : { DATA_WIDTH {1'b0} }) : w_data_o; // Read description
always @(posedge clk) begin
if (rst) begin
enqueue_ptr <= 0;
dequeue_ptr <= 0;
count <= 0;
end
else begin
enqueue_ptr <= (w_enqueue) ? enqueue_ptr + 1'b1 : enqueue_ptr;
dequeue_ptr <= (w_dequeue) ? dequeue_ptr + 1'b1 : dequeue_ptr;
count <= (w_enqueue ~^ w_dequeue) ? count : ((w_enqueue) ? count + 1'b1 : count - 1'b1); // Read description
end
end
ram #(DATA_WIDTH, ADDR_WIDTH) RAM(
.clk (clk),
.we (w_enqueue),
.read_address (dequeue_ptr),
.write_address (enqueue_ptr),
.data_i (data_i),
.data_o (w_data_o)
);
endmodule |
module sky130_fd_sc_hd__macro_sparecell (
//# {{data|Data Signals}}
output LO ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule |
module synth_ram #( parameter integer WORDS = 64) (
input clk,
input ena,
input [3:0] wen,
input [21:0] addr,
input [31:0] wdata,
output[31:0] rdata
);
reg [31:0] rdata;
reg [31:0] mem [0:WORDS-1];
always @(posedge clk) begin
if (ena == 1'b1) begin
rdata <= mem[addr];
if (wen[0]) mem[addr][ 7: 0] <= wdata[ 7: 0];
if (wen[1]) mem[addr][15: 8] <= wdata[15: 8];
if (wen[2]) mem[addr][23:16] <= wdata[23:16];
if (wen[3]) mem[addr][31:24] <= wdata[31:24];
end
end
endmodule |
module sky130_fd_sc_ms__nand4b_4 (
Y ,
A_N ,
B ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A_N ;
input B ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__nand4b base (
.Y(Y),
.A_N(A_N),
.B(B),
.C(C),
.D(D),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule |
module sky130_fd_sc_ms__nand4b_4 (
Y ,
A_N,
B ,
C ,
D
);
output Y ;
input A_N;
input B ;
input C ;
input D ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__nand4b base (
.Y(Y),
.A_N(A_N),
.B(B),
.C(C),
.D(D)
);
endmodule |
module sky130_fd_sc_lp__a41o (
X ,
A1 ,
A2 ,
A3 ,
A4 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A1 ;
input A2 ;
input A3 ;
input A4 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire and0_out ;
wire or0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
and and0 (and0_out , A1, A2, A3, A4 );
or or0 (or0_out_X , and0_out, B1 );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule |
module sky130_fd_sc_hd__lpflow_inputiso0n (
X ,
A ,
SLEEP_B,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input SLEEP_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire and0_out_X;
// Name Output Other arguments
and and0 (and0_out_X, A, SLEEP_B );
sky130_fd_sc_hd__udp_pwrgood$l_pp$PG pwrgood0 (X , and0_out_X, VPWR, VGND);
endmodule |
module pcie_data_sender #(parameter C_PCI_DATA_WIDTH = 128, INPUT_DATA_WIDTH = 8, NUM_PES = 8) (
input clk,
input rst,
//Collector Interface
output coll_ready,
input coll_data_valid,
input[INPUT_DATA_WIDTH - 1:0] coll_data,
//RIFFA TX Interface
output CHNL_TX,
input CHNL_TX_ACK,
output CHNL_TX_LAST,
output[`SIG_CHNL_LENGTH_W - 1:0] CHNL_TX_LEN,
output[30:0] CHNL_TX_OFF,
output[C_PCI_DATA_WIDTH - 1:0] CHNL_TX_DATA,
output reg CHNL_TX_DATA_VALID,
input CHNL_TX_DATA_REN,
input[`SIG_CHNL_LENGTH_W - 1:0] dna_len,
output idle,
input en
);
localparam DATA_PER_TX = C_PCI_DATA_WIDTH/INPUT_DATA_WIDTH; //number of data chunks that can fit with in C_PCI_DATA_WIDTH
parameter IT_BITS = $clog2(DATA_PER_TX);
reg state = STATE_IDLE;
localparam STATE_IDLE = 1'b0;
localparam STATE_SENDING = 1'b1;
reg[`SIG_CHNL_LENGTH_W - 1:0] dna_len_r, send_len;
reg tx_issued;
//state transition logic
always@(posedge clk) begin
if(rst) begin
state <= STATE_IDLE;
dna_len_r <= 0;
send_len <= 0;
end
else begin
case(state)
STATE_IDLE: begin
if(en) begin
dna_len_r <= (dna_len - NUM_PES)*NUM_PES >> 7 /*to 128-bit chunks*/ ; // excluding reference dna reads
send_len <= (dna_len - NUM_PES)*NUM_PES >> 5/*to 32-bit words*/; // excluding reference dna reads
state <= STATE_SENDING;
end
end //STATE_IDLE
STATE_SENDING: begin
if(tx_issued) begin
dna_len_r <= dna_len_r - 1;
if(dna_len_r == 1) begin
state <= STATE_IDLE;
end
end
end //STATE_SENDING
endcase
end
end
assign idle = (state == STATE_IDLE);
//Register Input Data
reg[INPUT_DATA_WIDTH - 1:0] data_r;
reg data_valid_r;
wire fetch_input = coll_ready;
always@(posedge clk) begin
if(rst) begin
data_r <= 0;
data_valid_r <= 0;
end
else begin
if(fetch_input) begin
data_r <= coll_data;
data_valid_r <= coll_data_valid;
end
end
end
//Put data chuck in tx buffer
reg[IT_BITS - 1:0] iter = 0;
reg[C_PCI_DATA_WIDTH - 1:0] tx_buffer;
reg tx_buffer_valid = 0;
always@(posedge clk) begin
if(rst) begin
tx_buffer <= 0;
tx_buffer_valid <= 0;
end
else begin
if(data_valid_r && coll_ready) begin
tx_buffer[iter*INPUT_DATA_WIDTH +:INPUT_DATA_WIDTH] <= data_r;
iter <= iter + 1'b1;
tx_buffer_valid <= &iter;
end
else if(tx_issued) begin
tx_buffer_valid <= 1'b0;
end
end
end
//TODO: consider adding one more register stage for better timing
//Send tx buffer to RIFFA
assign CHNL_TX_LEN = send_len; //C_PCI_DATA_WIDTH/32;
assign CHNL_TX_LAST = 1'b1; //(dna_len_r == 1);
assign CHNL_TX_OFF = 0;
assign CHNL_TX_DATA = tx_buffer;
assign CHNL_TX = (state == STATE_SENDING);
always@* begin
tx_issued = 1'b0;
CHNL_TX_DATA_VALID = 1'b0;
if(state == STATE_SENDING) begin
if(tx_buffer_valid) begin
CHNL_TX_DATA_VALID = 1'b1;
if(CHNL_TX_DATA_REN) begin
tx_issued = 1'b1;
end
end //tx_buffer_valid
end
end
assign coll_ready = ~tx_buffer_valid || (tx_buffer_valid && tx_issued);
endmodule |
module sky130_fd_sc_ms__nand2b (
Y ,
A_N,
B
);
output Y ;
input A_N;
input B ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule |
module ZynqDesign_xbar_1 (
aclk,
aresetn,
s_axi_awaddr,
s_axi_awprot,
s_axi_awvalid,
s_axi_awready,
s_axi_wdata,
s_axi_wstrb,
s_axi_wvalid,
s_axi_wready,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_araddr,
s_axi_arprot,
s_axi_arvalid,
s_axi_arready,
s_axi_rdata,
s_axi_rresp,
s_axi_rvalid,
s_axi_rready,
m_axi_awaddr,
m_axi_awprot,
m_axi_awvalid,
m_axi_awready,
m_axi_wdata,
m_axi_wstrb,
m_axi_wvalid,
m_axi_wready,
m_axi_bresp,
m_axi_bvalid,
m_axi_bready,
m_axi_araddr,
m_axi_arprot,
m_axi_arvalid,
m_axi_arready,
m_axi_rdata,
m_axi_rresp,
m_axi_rvalid,
m_axi_rready
);
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLKIF CLK" *)
input wire aclk;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RSTIF RST" *)
input wire aresetn;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWADDR" *)
input wire [31 : 0] s_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWPROT" *)
input wire [2 : 0] s_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWVALID" *)
input wire [0 : 0] s_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWREADY" *)
output wire [0 : 0] s_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WDATA" *)
input wire [31 : 0] s_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WSTRB" *)
input wire [3 : 0] s_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WVALID" *)
input wire [0 : 0] s_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WREADY" *)
output wire [0 : 0] s_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BRESP" *)
output wire [1 : 0] s_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BVALID" *)
output wire [0 : 0] s_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BREADY" *)
input wire [0 : 0] s_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARADDR" *)
input wire [31 : 0] s_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARPROT" *)
input wire [2 : 0] s_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARVALID" *)
input wire [0 : 0] s_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARREADY" *)
output wire [0 : 0] s_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RDATA" *)
output wire [31 : 0] s_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RRESP" *)
output wire [1 : 0] s_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RVALID" *)
output wire [0 : 0] s_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RREADY" *)
input wire [0 : 0] s_axi_rready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWADDR [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI AWADDR [31:0] [63:32], xilinx.com:interface:aximm:1.0 M02_AXI AWADDR [31:0] [95:64]" *)
output wire [95 : 0] m_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWPROT [2:0] [2:0], xilinx.com:interface:aximm:1.0 M01_AXI AWPROT [2:0] [5:3], xilinx.com:interface:aximm:1.0 M02_AXI AWPROT [2:0] [8:6]" *)
output wire [8 : 0] m_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI AWVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI AWVALID [0:0] [2:2]" *)
output wire [2 : 0] m_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI AWREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI AWREADY [0:0] [2:2]" *)
input wire [2 : 0] m_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WDATA [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI WDATA [31:0] [63:32], xilinx.com:interface:aximm:1.0 M02_AXI WDATA [31:0] [95:64]" *)
output wire [95 : 0] m_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WSTRB [3:0] [3:0], xilinx.com:interface:aximm:1.0 M01_AXI WSTRB [3:0] [7:4], xilinx.com:interface:aximm:1.0 M02_AXI WSTRB [3:0] [11:8]" *)
output wire [11 : 0] m_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI WVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI WVALID [0:0] [2:2]" *)
output wire [2 : 0] m_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI WREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI WREADY [0:0] [2:2]" *)
input wire [2 : 0] m_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI BRESP [1:0] [1:0], xilinx.com:interface:aximm:1.0 M01_AXI BRESP [1:0] [3:2], xilinx.com:interface:aximm:1.0 M02_AXI BRESP [1:0] [5:4]" *)
input wire [5 : 0] m_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI BVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI BVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI BVALID [0:0] [2:2]" *)
input wire [2 : 0] m_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI BREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI BREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI BREADY [0:0] [2:2]" *)
output wire [2 : 0] m_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARADDR [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI ARADDR [31:0] [63:32], xilinx.com:interface:aximm:1.0 M02_AXI ARADDR [31:0] [95:64]" *)
output wire [95 : 0] m_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARPROT [2:0] [2:0], xilinx.com:interface:aximm:1.0 M01_AXI ARPROT [2:0] [5:3], xilinx.com:interface:aximm:1.0 M02_AXI ARPROT [2:0] [8:6]" *)
output wire [8 : 0] m_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI ARVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI ARVALID [0:0] [2:2]" *)
output wire [2 : 0] m_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI ARREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI ARREADY [0:0] [2:2]" *)
input wire [2 : 0] m_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RDATA [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI RDATA [31:0] [63:32], xilinx.com:interface:aximm:1.0 M02_AXI RDATA [31:0] [95:64]" *)
input wire [95 : 0] m_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RRESP [1:0] [1:0], xilinx.com:interface:aximm:1.0 M01_AXI RRESP [1:0] [3:2], xilinx.com:interface:aximm:1.0 M02_AXI RRESP [1:0] [5:4]" *)
input wire [5 : 0] m_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI RVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI RVALID [0:0] [2:2]" *)
input wire [2 : 0] m_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI RREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI RREADY [0:0] [2:2]" *)
output wire [2 : 0] m_axi_rready;
axi_crossbar_v2_1_axi_crossbar #(
.C_FAMILY("zynq"),
.C_NUM_SLAVE_SLOTS(1),
.C_NUM_MASTER_SLOTS(3),
.C_AXI_ID_WIDTH(1),
.C_AXI_ADDR_WIDTH(32),
.C_AXI_DATA_WIDTH(32),
.C_AXI_PROTOCOL(2),
.C_NUM_ADDR_RANGES(1),
.C_M_AXI_BASE_ADDR(192'H00000000412100000000000043c000000000000041200000),
.C_M_AXI_ADDR_WIDTH(96'H000000100000001000000010),
.C_S_AXI_BASE_ID(32'H00000000),
.C_S_AXI_THREAD_ID_WIDTH(32'H00000000),
.C_AXI_SUPPORTS_USER_SIGNALS(0),
.C_AXI_AWUSER_WIDTH(1),
.C_AXI_ARUSER_WIDTH(1),
.C_AXI_WUSER_WIDTH(1),
.C_AXI_RUSER_WIDTH(1),
.C_AXI_BUSER_WIDTH(1),
.C_M_AXI_WRITE_CONNECTIVITY(96'H000000010000000100000001),
.C_M_AXI_READ_CONNECTIVITY(96'H000000010000000100000001),
.C_R_REGISTER(1),
.C_S_AXI_SINGLE_THREAD(32'H00000001),
.C_S_AXI_WRITE_ACCEPTANCE(32'H00000001),
.C_S_AXI_READ_ACCEPTANCE(32'H00000001),
.C_M_AXI_WRITE_ISSUING(96'H000000010000000100000001),
.C_M_AXI_READ_ISSUING(96'H000000010000000100000001),
.C_S_AXI_ARB_PRIORITY(32'H00000000),
.C_M_AXI_SECURE(96'H000000000000000000000000),
.C_CONNECTIVITY_MODE(0)
) inst (
.aclk(aclk),
.aresetn(aresetn),
.s_axi_awid(1'H0),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awlen(8'H00),
.s_axi_awsize(3'H0),
.s_axi_awburst(2'H0),
.s_axi_awlock(1'H0),
.s_axi_awcache(4'H0),
.s_axi_awprot(s_axi_awprot),
.s_axi_awqos(4'H0),
.s_axi_awuser(1'H0),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_awready(s_axi_awready),
.s_axi_wid(1'H0),
.s_axi_wdata(s_axi_wdata),
.s_axi_wstrb(s_axi_wstrb),
.s_axi_wlast(1'H1),
.s_axi_wuser(1'H0),
.s_axi_wvalid(s_axi_wvalid),
.s_axi_wready(s_axi_wready),
.s_axi_bid(),
.s_axi_bresp(s_axi_bresp),
.s_axi_buser(),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_bready(s_axi_bready),
.s_axi_arid(1'H0),
.s_axi_araddr(s_axi_araddr),
.s_axi_arlen(8'H00),
.s_axi_arsize(3'H0),
.s_axi_arburst(2'H0),
.s_axi_arlock(1'H0),
.s_axi_arcache(4'H0),
.s_axi_arprot(s_axi_arprot),
.s_axi_arqos(4'H0),
.s_axi_aruser(1'H0),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_arready(s_axi_arready),
.s_axi_rid(),
.s_axi_rdata(s_axi_rdata),
.s_axi_rresp(s_axi_rresp),
.s_axi_rlast(),
.s_axi_ruser(),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_rready(s_axi_rready),
.m_axi_awid(),
.m_axi_awaddr(m_axi_awaddr),
.m_axi_awlen(),
.m_axi_awsize(),
.m_axi_awburst(),
.m_axi_awlock(),
.m_axi_awcache(),
.m_axi_awprot(m_axi_awprot),
.m_axi_awregion(),
.m_axi_awqos(),
.m_axi_awuser(),
.m_axi_awvalid(m_axi_awvalid),
.m_axi_awready(m_axi_awready),
.m_axi_wid(),
.m_axi_wdata(m_axi_wdata),
.m_axi_wstrb(m_axi_wstrb),
.m_axi_wlast(),
.m_axi_wuser(),
.m_axi_wvalid(m_axi_wvalid),
.m_axi_wready(m_axi_wready),
.m_axi_bid(3'H0),
.m_axi_bresp(m_axi_bresp),
.m_axi_buser(3'H0),
.m_axi_bvalid(m_axi_bvalid),
.m_axi_bready(m_axi_bready),
.m_axi_arid(),
.m_axi_araddr(m_axi_araddr),
.m_axi_arlen(),
.m_axi_arsize(),
.m_axi_arburst(),
.m_axi_arlock(),
.m_axi_arcache(),
.m_axi_arprot(m_axi_arprot),
.m_axi_arregion(),
.m_axi_arqos(),
.m_axi_aruser(),
.m_axi_arvalid(m_axi_arvalid),
.m_axi_arready(m_axi_arready),
.m_axi_rid(3'H0),
.m_axi_rdata(m_axi_rdata),
.m_axi_rresp(m_axi_rresp),
.m_axi_rlast(3'H7),
.m_axi_ruser(3'H0),
.m_axi_rvalid(m_axi_rvalid),
.m_axi_rready(m_axi_rready)
);
endmodule |
module sky130_fd_sc_lp__udp_dlatch$PR_pp$PKG$sN (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{control|Control Signals}}
input RESET ,
//# {{clocks|Clocking}}
input GATE ,
//# {{power|Power}}
input SLEEP_B ,
input KAPWR ,
input NOTIFIER,
input VPWR ,
input VGND
);
endmodule |
module system_auto_us_2(s_axi_aclk, s_axi_aresetn, s_axi_awaddr,
s_axi_awlen, s_axi_awsize, s_axi_awburst, s_axi_awlock, s_axi_awcache, s_axi_awprot,
s_axi_awregion, s_axi_awqos, s_axi_awvalid, s_axi_awready, s_axi_wdata, s_axi_wstrb,
s_axi_wlast, s_axi_wvalid, s_axi_wready, s_axi_bresp, s_axi_bvalid, s_axi_bready,
m_axi_awaddr, m_axi_awlen, m_axi_awsize, m_axi_awburst, m_axi_awlock, m_axi_awcache,
m_axi_awprot, m_axi_awregion, m_axi_awqos, m_axi_awvalid, m_axi_awready, m_axi_wdata,
m_axi_wstrb, m_axi_wlast, m_axi_wvalid, m_axi_wready, m_axi_bresp, m_axi_bvalid,
m_axi_bready)
/* synthesis syn_black_box black_box_pad_pin="s_axi_aclk,s_axi_aresetn,s_axi_awaddr[31:0],s_axi_awlen[7:0],s_axi_awsize[2:0],s_axi_awburst[1:0],s_axi_awlock[0:0],s_axi_awcache[3:0],s_axi_awprot[2:0],s_axi_awregion[3:0],s_axi_awqos[3:0],s_axi_awvalid,s_axi_awready,s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wlast,s_axi_wvalid,s_axi_wready,s_axi_bresp[1:0],s_axi_bvalid,s_axi_bready,m_axi_awaddr[31:0],m_axi_awlen[7:0],m_axi_awsize[2:0],m_axi_awburst[1:0],m_axi_awlock[0:0],m_axi_awcache[3:0],m_axi_awprot[2:0],m_axi_awregion[3:0],m_axi_awqos[3:0],m_axi_awvalid,m_axi_awready,m_axi_wdata[63:0],m_axi_wstrb[7:0],m_axi_wlast,m_axi_wvalid,m_axi_wready,m_axi_bresp[1:0],m_axi_bvalid,m_axi_bready" */;
input s_axi_aclk;
input s_axi_aresetn;
input [31:0]s_axi_awaddr;
input [7:0]s_axi_awlen;
input [2:0]s_axi_awsize;
input [1:0]s_axi_awburst;
input [0:0]s_axi_awlock;
input [3:0]s_axi_awcache;
input [2:0]s_axi_awprot;
input [3:0]s_axi_awregion;
input [3:0]s_axi_awqos;
input s_axi_awvalid;
output s_axi_awready;
input [31:0]s_axi_wdata;
input [3:0]s_axi_wstrb;
input s_axi_wlast;
input s_axi_wvalid;
output s_axi_wready;
output [1:0]s_axi_bresp;
output s_axi_bvalid;
input s_axi_bready;
output [31:0]m_axi_awaddr;
output [7:0]m_axi_awlen;
output [2:0]m_axi_awsize;
output [1:0]m_axi_awburst;
output [0:0]m_axi_awlock;
output [3:0]m_axi_awcache;
output [2:0]m_axi_awprot;
output [3:0]m_axi_awregion;
output [3:0]m_axi_awqos;
output m_axi_awvalid;
input m_axi_awready;
output [63:0]m_axi_wdata;
output [7:0]m_axi_wstrb;
output m_axi_wlast;
output m_axi_wvalid;
input m_axi_wready;
input [1:0]m_axi_bresp;
input m_axi_bvalid;
output m_axi_bready;
endmodule |
module sky130_fd_sc_hd__tap_1 (
VPWR,
VGND,
VPB ,
VNB
);
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__tap base (
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule |
module sky130_fd_sc_hd__tap_1 ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__tap base ();
endmodule |
module busInterface (
input wire [31:0] mem_addr,
input wire [31:0] mem_rdata_gpio,
input wire [31:0] mem_rdata_uart,
input wire [31:0] mem_rdata_uartRx,
input wire [31:0] mem_rdata_timer,
input wire [31:0] mem_rdata_prng,
input wire [31:0] mem_rdata_memory,
input wire mem_ready_gpio,
input wire mem_ready_uart,
input wire mem_ready_uartRx,
input wire mem_ready_timer,
input wire mem_ready_prng,
input wire mem_ready_memory,
output wire mem_ready,
output wire [31:0] mem_rdata,
output wire [7:0] enables
);
always @(*) begin
enables = 0;
case (mem_addr[31:4])
28'hffff000: enables[0] = 1'd1;
28'hffff001: enables[1] = 1'd1;
28'hffff002: enables[2] = 1'd1;
28'hffff003: enables[3] = 1'd1;
28'hffff004: enables[4] = 1'd1;
28'hffff005: enables[5] = 1'd1;
28'hffff006: enables[6] = 1'd1;
default: enables[7] = 1;
endcase
case (mem_addr[31:4])
28'hffff000: mem_ready = mem_ready_memory;
28'hffff001: mem_ready = mem_ready_memory;
28'hffff002: mem_ready = mem_ready_uartRx;
28'hffff003: mem_ready = mem_ready_timer;
28'hffff004: mem_ready = mem_ready_uart;
28'hffff005: mem_ready = mem_ready_prng;
28'hffff006: mem_ready = mem_ready_gpio;
default: mem_ready = mem_ready_memory;
endcase
case (mem_addr[31:4])
28'hffff000: mem_rdata = mem_rdata_memory;
28'hffff001: mem_rdata = mem_rdata_memory;
28'hffff002: mem_rdata = mem_rdata_uartRx;
28'hffff003: mem_rdata = mem_rdata_timer;
28'hffff004: mem_rdata = mem_rdata_uart;
28'hffff005: mem_rdata = mem_rdata_prng;
28'hffff006: mem_rdata = mem_rdata_gpio;
default: mem_rdata = mem_rdata_memory;
endcase
end
endmodule |
module
else
// display score, rule, or game over
if (text_on[3] ||
((state_reg==newgame) && text_on[1]) || // rule
((state_reg==over) && text_on[0]))
rgb_next = text_rgb;
else if (graph_on) // display graph
rgb_next = graph_rgb;
else if (text_on[2]) // display logo
rgb_next = text_rgb;
// logo should not cover the ball I assume
// but, who cares
else
rgb_next = 3'b110; // yellow background
// output
assign rgb = rgb_reg;
endmodule |
module tb_uart_rx;
// Inputs
reg clk;
reg reset;
reg wren;
reg rden;
reg [7:0] din;
reg rxin;
reg [2:0] addr;
// Outputs
wire [8:0] dout;
parameter CLK_PERIOD=20; //clock period in ns. 20 ns = 50 MHZ
//parameter UUT_PERIOD=8'h1A; //57600 baudrate
parameter UUT_PERIOD=8'h0C; //115200 baudrate
parameter CLK16X_PERIOD=(CLK_PERIOD*(UUT_PERIOD+1)*2);
parameter CHARACTER_PERIOD = (CLK16X_PERIOD * 16 * 10);
// Instantiate the Unit Under Test (UUT)
uart_rx uut (
.clk(clk),
.reset(reset),
.wren(wren),
.rden(rden),
.din(din),
.dout(dout),
.rxin(rxin),
.addr(addr)
);
`define FSIZE 1024
integer infifo[(`FSIZE-1):0];
integer head,tail;
integer errors;
initial begin
clk = 0;
#100 //reset delay
forever #10 clk = ~clk;
end
//timeout process
initial begin
#(CHARACTER_PERIOD*35); //wait 35 characters
if (head != tail) begin
$display("%t: TIMEOUT, not all characters processed.",$time);
$display("The timeout is probably due to the DATARDY bit never going high.");
end
end
reg [9:0] shiftdata;
integer i;
task putserialdata;
input [8:0] outdata;
begin
infifo[head] = outdata;
head = head + 1;
if (head == `FSIZE) head = 0;
shiftdata ={1'b1,outdata[7:0],1'b0};
i = 0;
while (i != 10) begin
rxin = shiftdata[0];
#(CLK16X_PERIOD*16) //wait one bit time
i = i + 1;
shiftdata = {1'b1,shiftdata[9:1]};
end
end
endtask
task putserialdata_badstop;
input [8:0] outdata;
begin
infifo[head] = outdata;
head = head + 1;
if (head == `FSIZE) head = 0;
shiftdata ={1'b1,outdata[7:0],1'b0};
i = 0;
while (i != 10) begin
if (i == 9) rxin = 0;
else rxin = shiftdata[0];
#(CLK16X_PERIOD*16) //wait one bit time
i = i + 1;
shiftdata = {1'b1,shiftdata[9:1]};
end
end
endtask
task putserialdata_badstart;
input [8:0] outdata;
begin
infifo[head] = outdata;
head = head + 1;
if (head == `FSIZE) head = 0;
shiftdata ={1'b1,outdata[7:0],1'b0};
i = 0;
while (i != 10) begin
if (i == 0) begin
rxin = 0;
#(CLK16X_PERIOD*2);
rxin = 1; //bad start
#(CLK16X_PERIOD*14);
end else begin
rxin = shiftdata[0];
#(CLK16X_PERIOD*16); //wait one bit time
end
i = i + 1;
shiftdata = {1'b1,shiftdata[9:1]};
end
end
endtask
reg [8:0] expecteddata;
task readdata;
begin
//read status register, wait for TXDONE bit to be set
@(negedge clk);
rden = 1;
addr = 7; //status register
@(negedge clk);
while (dout[1] == 0) begin
@(negedge clk); //wait for DataRdy bit
end
addr = 5; //FIFO register
@(posedge clk); //must latch FIFO out data on posedge
if (expecteddata[8] == 1) begin
//expected framing error, just check ferr bit
if (dout[8] != 1) begin
errors = errors + 1;
$display("%t: FAIL,did not receive expected framing error",$time);
end else begin
$display("%t: PASS,received expected framing error",$time);
end
end else begin
//no expected framing error
if (expecteddata != dout) begin
errors = errors + 1;
$display("%t: FAIL,expected serial out of %h, found: %h",$time,expecteddata,dout);
end else begin
$display("%t: PASS,got expected serial out of %h",$time,expecteddata);
end
end
addr = 7;
rden = 0;
@(negedge clk);
end
endtask
task checkdata;
begin
while (head != tail) begin
expecteddata = infifo[tail];
tail = tail + 1;
if (tail == `FSIZE) tail = 0;
readdata();
end
end
endtask
task writerxen; //this writes a 'expectedbit' to the EN bit of the control register
input expectedbit;
begin
@(negedge clk);
din = {7'b0000000,expectedbit};
wren = 1;
addr = 7;
@(negedge clk);
wren = 0;
rden = 1;
@(negedge clk);
@(negedge clk);
if (dout[0] != expectedbit) begin
errors = errors + 1;
$display("%t: FAIL, writing UART RXEN bit = %h failed.",$time,expectedbit);
end else begin
$display("%t: PASS, writing UART RXEN bit = %h.",$time, expectedbit);
end
rden = 0;
@(negedge clk);
end
endtask
task rdoverrun; //read the overrun flag
input expectedbit;
begin
@(negedge clk);
addr = 7;
rden = 1;
@(negedge clk);
if (dout[2] != expectedbit) begin
errors = errors + 1;
$display("%t: FAIL, reading UART OVERRUN bit, expected: %h, actual: %h.",$time,expectedbit,dout[2]);
end else begin
$display("%t: PASS, reading UART OVERRUN bit: %h.",$time, expectedbit);
end
rden = 0;
end
endtask
task rddatardy; //read the data rdy flag
input expectedbit;
begin
@(negedge clk);
addr = 7;
rden = 1;
@(negedge clk);
if (dout[1] != expectedbit) begin
errors = errors + 1;
$display("%t: FAIL, reading UART DATARDY bit, expected: %h, actual: %h.",$time,expectedbit,dout[1]);
end else begin
$display("%t: PASS, reading UART DATARDY bit.",$time);
end
rden = 0;
end
endtask
integer j;
initial begin
// Initialize Inputs
#1
clk = 0;
reset = 1;
wren = 0;
rden = 0;
din = 0;
rxin = 1;
addr = 0;
errors = 0;
head = 0;
tail = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
reset = 0;
// Add stimulus here
@(negedge clk);
@(negedge clk);
@(negedge clk);
@(negedge clk);
@(negedge clk);
//first need to write the period register
din = UUT_PERIOD;
wren = 1;
addr = 4;
@(negedge clk);
wren = 0;
rden = 1;
@(negedge clk);
@(negedge clk);
if (dout != UUT_PERIOD) begin
errors = errors + 1;
$display("%t: FAIL, PERIOD register write/read failed: %h, expected: %h",$time,UUT_PERIOD,dout);
end else begin
$display("%t: PASS, Period register read/write",$time);
end
rden = 0;
@(negedge clk);
writerxen(1); //write a '1' to UART to get it started
putserialdata(9'h039);
checkdata();
putserialdata(9'h012);
putserialdata(9'h0D3);
putserialdata(9'h0B7);
#(CHARACTER_PERIOD*3)
#(CLK16X_PERIOD*16)
checkdata();
$display("Testing bad stop bit");
putserialdata_badstop(9'h155); //test bad stop bit
checkdata();
$display("Testing bad start bit");
putserialdata_badstop(9'h1AA); //test bad stop bit
checkdata();
putserialdata(9'h084);
checkdata();
//now test overrun
j = 0;
while (j != 18) begin
putserialdata(j+ 9'h030);
j = j + 1;
end
//check the overrun bit
@(negedge clk);
@(negedge clk);
@(negedge clk);
rdoverrun(0);
//send one more character, will set the overrun bit.
putserialdata(j+ 9'h030);
@(negedge clk);
@(negedge clk);
@(negedge clk);
rdoverrun(1);
//now reset the uart
writerxen(0); //write a '0' to UART RXEN to reset it.
//overrun should now be 0.
@(negedge clk);
@(negedge clk);
rdoverrun(0);
//data avaialble bit should be 0 as well
rddatardy(0);
//re-enable the modem
writerxen(1); //write a '1' to UART RXEN to enable it.
//we need flush our internal FIFO
head = 0; tail = 0;
//write one more datum to verify FIFO is restarted
putserialdata(9'h0A7);
checkdata();
$display("%t: All vectors done.",$time);
if (errors != 0)
$display("%t: FAIL, had %d errors during simulation.",$time,errors);
else
$display("%t: PASS, no errors during simulation.",$time);
end
endmodule |
module sky130_fd_sc_hdll__and3_1 (
X ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__and3 base (
.X(X),
.A(A),
.B(B),
.C(C),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule |
module sky130_fd_sc_hdll__and3_1 (
X,
A,
B,
C
);
output X;
input A;
input B;
input C;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__and3 base (
.X(X),
.A(A),
.B(B),
.C(C)
);
endmodule |
module hbi_wcregs
(
input hb_clk, // pci clock
input mclock, // MC clock
input hb_soft_reset_n, // reset
input [31:0] pci_data, // pci data, raw or converted from yuv
input [3:0] wc_be, // byte enables
input [3:0] wc_be_d, // byte enables
input clr_wc0, // clear cache0
input clr_wc1, // clear cache1
input ld_wc0, // load cache0
input ld_wc1, // load cache1
input wcregs_addr, // bit one of the RAM addr
input wcregs_we, // Write enable for the RAM
input [2:0] sub_buf_sel, // 1 of 4 "half buffers" for writing
input hst_push,
input hst_pop,
input [1:0] hst_mw_addr,
input select,
output [127:0] hb_pdo, // "write" pixel data to mc
output reg [15:0] hst_md, // byte mask data to mc
output reg mc_done,
output reg [1:0] push_count
);
reg [3:0] mask0; // byte enables buffers
reg [3:0] mask1;
reg [3:0] mask2;
reg [3:0] mask3;
reg [3:0] mask4; // byte enables buffers
reg [3:0] mask5;
reg [3:0] mask6;
reg [3:0] mask7;
reg [3:0] mask8; // byte enables buffers
reg [3:0] mask9;
reg [3:0] maska;
reg [3:0] maskb;
reg [3:0] maskc; // byte enables buffers
reg [3:0] maskd;
reg [3:0] maske;
reg [3:0] maskf;
reg [3:0] wc_be_i; // byte enables
reg [3:0] wc_be_di, wc_be_dii; // byte enables
reg clr_wc0_i; // clear cache0
reg clr_wc1_i; // clear cache1
reg ld_wc0_i; // load cache0
reg ld_wc1_i; // load cache1
reg [2:0] sub_buf_sel_i; // 1 of 4 "half buffers" for writing
reg [3:0] waddr;
reg we;
reg [1:0] pop_count;
wire [127:0] data_in;
// Technically agp data should be delayed one cycle. However, since I am not
// using it, it is sort of a place holder for DMA, I am leaving it as is
always @(posedge hb_clk) begin
waddr <= {wcregs_addr, sub_buf_sel} | select;
we <= wcregs_we;
wc_be_i <= select ? wc_be_di : wc_be;
wc_be_di <= wc_be_d;
clr_wc0_i <= clr_wc0;
clr_wc1_i <= clr_wc1;
ld_wc0_i <= ld_wc0;
ld_wc1_i <= ld_wc1;
sub_buf_sel_i <= sub_buf_sel | select;
end
dpram_32_128x16 U_MW_RAM
(
.data (pci_data),
.wren (we),
.wraddress (waddr),
.rdaddress (hst_mw_addr),
.byteena_a (~wc_be_i),
.wrclock (hb_clk),
.rdclock (mclock),
.q (hb_pdo)
);
// Mask (byte enable) buffer
// loads have precedence over clears. when a clear is received, every
// mask for that buffer is cleared, except for the selected mask being loaded
always @(posedge hb_clk) begin
case (sub_buf_sel_i) //synopsys full_case parallel_case
3'd0: begin
// Mask for Buffer 0
if (ld_wc0_i) mask0 <= mask0 & wc_be_i;
else if (clr_wc0_i) mask0 <= 4'hF;
if (clr_wc0_i) begin
mask1 <= 4'hF;
mask2 <= 4'hF;
mask3 <= 4'hF;
mask4 <= 4'hF;
mask5 <= 4'hF;
mask6 <= 4'hF;
mask7 <= 4'hF;
end
// Mask for buffer 1
if (ld_wc1_i) mask8 <= mask8 & wc_be_i;
else if (clr_wc1_i) mask8 <= 4'hF;
if (clr_wc1_i) begin
mask9 <= 4'hF;
maska <= 4'hF;
maskb <= 4'hF;
maskc <= 4'hF;
maskd <= 4'hF;
maske <= 4'hF;
maskf <= 4'hF;
end
end
3'd1: begin
// Mask for Buffer 0
if (ld_wc0_i) mask1 <= mask1 & wc_be_i;
else if (clr_wc0_i) mask1 <= 4'hF;
if (clr_wc0_i) begin
mask0 <= 4'hF;
mask2 <= 4'hF;
mask3 <= 4'hF;
mask4 <= 4'hF;
mask5 <= 4'hF;
mask6 <= 4'hF;
mask7 <= 4'hF;
end
// Mask for buffer 1
if (ld_wc1_i) mask9 <= mask9 & wc_be_i;
else if (clr_wc1_i) mask9 <= 4'hF;
if (clr_wc1_i) begin
mask8 <= 4'hF;
maska <= 4'hF;
maskb <= 4'hF;
maskc <= 4'hF;
maskd <= 4'hF;
maske <= 4'hF;
maskf <= 4'hF;
end
end
3'd2: begin
// Mask for Buffer 0
if (ld_wc0_i) mask2 <= mask2 & wc_be_i;
else if (clr_wc0_i) mask2 <= 4'hF;
if (clr_wc0_i) begin
mask0 <= 4'hF;
mask1 <= 4'hF;
mask3 <= 4'hF;
mask4 <= 4'hF;
mask5 <= 4'hF;
mask6 <= 4'hF;
mask7 <= 4'hF;
end
// Mask for buffer 1
if (ld_wc1_i) maska <= maska & wc_be_i;
else if (clr_wc1_i) maska <= 4'hF;
if (clr_wc1_i) begin
mask8 <= 4'hF;
mask9 <= 4'hF;
maskb <= 4'hF;
maskc <= 4'hF;
maskd <= 4'hF;
maske <= 4'hF;
maskf <= 4'hF;
end
end
3'd3: begin
// Mask for Buffer 0
if (ld_wc0_i) mask3 <= mask3 & wc_be_i;
else if (clr_wc0_i) mask3 <= 4'hF;
if (clr_wc0_i) begin
mask0 <= 4'hF;
mask1 <= 4'hF;
mask2 <= 4'hF;
mask4 <= 4'hF;
mask5 <= 4'hF;
mask6 <= 4'hF;
mask7 <= 4'hF;
end
// Mask for buffer 1
if (ld_wc1_i) maskb <= maskb & wc_be_i;
else if (clr_wc1_i) maskb <= 4'hF;
if (clr_wc1_i) begin
mask8 <= 4'hF;
mask9 <= 4'hF;
maska <= 4'hF;
maskc <= 4'hF;
maskd <= 4'hF;
maske <= 4'hF;
maskf <= 4'hF;
end
end
3'd4: begin
// Mask for Buffer 0
if (ld_wc0_i) mask4 <= mask4 & wc_be_i;
else if (clr_wc0_i) mask4 <= 4'hF;
if (clr_wc0_i) begin
mask0 <= 4'hF;
mask1 <= 4'hF;
mask2 <= 4'hF;
mask3 <= 4'hF;
mask5 <= 4'hF;
mask6 <= 4'hF;
mask7 <= 4'hF;
end
// Mask for buffer 1
if (ld_wc1_i) maskc <= maskc & wc_be_i;
else if (clr_wc1_i) maskc <= 4'hF;
if (clr_wc1_i) begin
mask8 <= 4'hF;
mask9 <= 4'hF;
maska <= 4'hF;
maskb <= 4'hF;
maskd <= 4'hF;
maske <= 4'hF;
maskf <= 4'hF;
end
end
3'd5: begin
// Mask for Buffer 0
if (ld_wc0_i) mask5 <= mask5 & wc_be_i;
else if (clr_wc0_i) mask5 <= 4'hF;
if (clr_wc0_i) begin
mask0 <= 4'hF;
mask1 <= 4'hF;
mask2 <= 4'hF;
mask3 <= 4'hF;
mask4 <= 4'hF;
mask6 <= 4'hF;
mask7 <= 4'hF;
end
// Mask for buffer 1
if (ld_wc1_i) maskd <= maskd & wc_be_i;
else if (clr_wc1_i) maskd <= 4'hF;
if (clr_wc1_i) begin
mask8 <= 4'hF;
mask9 <= 4'hF;
maska <= 4'hF;
maskb <= 4'hF;
maskc <= 4'hF;
maske <= 4'hF;
maskf <= 4'hF;
end
end
3'd6: begin
// Mask for Buffer 0
if (ld_wc0_i) mask6 <= mask6 & wc_be_i;
else if (clr_wc0_i) mask6 <= 4'hF;
if (clr_wc0_i) begin
mask0 <= 4'hF;
mask1 <= 4'hF;
mask2 <= 4'hF;
mask3 <= 4'hF;
mask4 <= 4'hF;
mask5 <= 4'hF;
mask7 <= 4'hF;
end
// Mask for buffer 1
if (ld_wc1_i) maske <= maske & wc_be_i;
else if (clr_wc1_i) maske <= 4'hF;
if (clr_wc1_i) begin
mask8 <= 4'hF;
mask9 <= 4'hF;
maska <= 4'hF;
maskb <= 4'hF;
maskc <= 4'hF;
maskd <= 4'hF;
maskf <= 4'hF;
end
end
3'd7: begin
// Mask for Buffer 0
if (ld_wc0_i) mask7 <= mask7 & wc_be_i;
else if (clr_wc0_i) mask7 <= 4'hF;
if (clr_wc0_i) begin
mask0 <= 4'hF;
mask1 <= 4'hF;
mask2 <= 4'hF;
mask3 <= 4'hF;
mask4 <= 4'hF;
mask5 <= 4'hF;
mask6 <= 4'hF;
end
// Mask for buffer 1
if (ld_wc1_i) maskf <= maskf & wc_be_i;
else if (clr_wc1_i) maskf <= 4'hF;
if (clr_wc1_i) begin
mask8 <= 4'hF;
mask9 <= 4'hF;
maska <= 4'hF;
maskb <= 4'hF;
maskc <= 4'hF;
maskd <= 4'hF;
maske <= 4'hF;
end
end
endcase // case(sub_buf_sel_i)
end // always @ (posedge hb_clk)
// pop, push counters, and done flag
always @(posedge mclock or negedge hb_soft_reset_n) begin
if (!hb_soft_reset_n) begin
push_count <= 2'b00;
pop_count <= 2'b00;
mc_done <= 1'b0;
end else begin
// push counter. It is used to tell when MC is done
if (hst_push) push_count <= push_count + 2'b01;
if (hst_pop) pop_count <= pop_count + 2'b01;
// Done flop. This toggles when MC is done. Writes are always 8 cycles,
// reads are always 16 cycles.
if ((hst_pop && pop_count[0]) || (hst_push && (push_count == 2'b11)))
mc_done <= ~mc_done;
end // else: !if(!hb_soft_reset_n)
end // always @ (posedge mclock or negedge hb_soft_reset_n)
// output mux
always @* begin
case (pop_count)
2'h3: hst_md = {maskf, maske, maskd, maskc};
2'h2: hst_md = {maskb, maska, mask9, mask8};
2'h1: hst_md = {mask7, mask6, mask5, mask4};
2'h0: hst_md = {mask3, mask2, mask1, mask0};
endcase // case(pop_count)
end // always @ (pop_count or...
endmodule |
module Testbench_Barrel_Shifter ();
parameter PERIOD = 10;
parameter EWR=5;
parameter SWR=26;
//inputs
reg clk;
reg rst;
reg load_i;
reg [EWR-1:0] Shift_Value_i;
reg [SWR-1:0] Shift_Data_i;
reg Left_Right_i;
reg Bit_Shift_i;
///////////////////OUTPUT//////////////////////////7
wire [SWR-1:0] N_mant_o;
Mux_Array_DW #(
.SWR(SWR),
.EWR(EWR)
) inst_Mux_Array (
.clk(clk),
.rst(rst),
.load_i(load_i),
.Data_i (Shift_Data_i),
.FSM_left_right_i (Left_Right_i),
.Shift_Value_i (Shift_Value_i),
.bit_shift_i (Bit_Shift_i),
.Data_o (N_mant_o)
);
integer Contador_shiftvalue = 0;
always begin
#(8*PERIOD/2) Contador_shiftvalue = Contador_shiftvalue + 1;
Shift_Value_i = Contador_shiftvalue;
Left_Right_i = ~Left_Right_i;
#(8*PERIOD/2);
end
always @ (N_mant_o )
begin
$monitor($time,"REA Salida = %b Entrada = %b Numero de Corrimiento: %d",N_mant_o,Shift_Data_i, Shift_Value_i);
$display($time,"TEO Salida = %b Entrada = %b Numero de Corrimiento: %d",(Shift_Data_i>>Shift_Value_i),Shift_Data_i,Shift_Value_i);
end
initial begin
// Initialize Input
rst = 1;
clk = 0;
load_i = 0;
Shift_Value_i = 0;
Shift_Data_i = $random;
Left_Right_i = 0;
Bit_Shift_i = 0;
#40 rst = 0;
load_i = 1;
end
initial begin
#(PERIOD * 1024);
$finish;
end
initial begin
clk = 1'b0;
#(PERIOD/2);
forever
#(PERIOD/2) clk = ~clk;
end
endmodule |
module tlu_misctl (/*AUTOARG*/
// outputs
tlu_exu_cwp_m, tlu_exu_ccr_m, tlu_lsu_asi_m, tlu_cwp_no_change_m,
tlu_sscan_misctl_data, tlu_ifu_trappc_w2, tlu_ifu_trapnpc_w2,
tlu_pc_new_w, tlu_npc_new_w, so,
// PIC experiment
tlu_exu_pic_onebelow_m, tlu_exu_pic_twobelow_m,
// inputs
ctu_sscan_tid, ifu_tlu_pc_m, exu_tlu_cwp0, exu_tlu_cwp1, exu_tlu_cwp2,
exu_tlu_cwp3, tlu_final_ttype_w2, tsa_wr_tid, tlu_true_pc_sel_w,
tsa1_wr_vld, tsa_ttype_en, tsa_rd_vld_e, tsa0_rdata_cwp, tsa0_rdata_pstate,
tsa0_rdata_asi, tsa0_rdata_ccr, tsa0_rdata_gl, tsa0_rdata_pc, tsa1_rdata_ttype,
tsa1_rdata_npc, tsa1_rdata_htstate, tlu_thrd_rsel_e, tlu_final_offset_w1,
tlu_partial_trap_pc_w1, tlu_restore_pc_w1, tlu_restore_npc_w1,
ifu_npc_w, tlu_restore_pc_sel_w1, tlu_pic_cnt_en_m, tlu_pic_onebelow_e,
tlu_pic_twobelow_e, tlu_rst, si, se, rclk);
// pich_threebelow_flg, pich_twobelow_flg, pich_onebelow_flg,
//=================================================
// output
//=================================================
output [`TSA_CCR_WIDTH-1:0] tlu_exu_ccr_m; // restored ccr
output [`TSA_CWP_WIDTH-1:0] tlu_exu_cwp_m; // restored cwp
output [`TLU_ASI_STATE_WIDTH-1:0] tlu_lsu_asi_m; // restored asi
output tlu_cwp_no_change_m; // cwp change indicator
//
// sscan output
output [`MISCTL_SSCAN_WIDTH-1:0] tlu_sscan_misctl_data;
//
// trap pc and npc
output [48:0] tlu_ifu_trappc_w2, tlu_ifu_trapnpc_w2;
output [48:0] tlu_pc_new_w, tlu_npc_new_w;
// global nets
output so;
// PIC experiment
output tlu_exu_pic_onebelow_m; // local traps send to exu
output tlu_exu_pic_twobelow_m; // local traps send to exu
//=================================================
// input
//=================================================
// sscan related inputs
input [`TLU_THRD_NUM-1:0] ctu_sscan_tid;
input [`TSA_TTYPE_WIDTH-1:0] tlu_final_ttype_w2;
input [1:0] tsa_wr_tid;
input tsa1_wr_vld, tsa_rd_vld_e;
input tsa_ttype_en;
//
// current cwp value from exu
input [2:0] exu_tlu_cwp0; // cwp - thread0
input [2:0] exu_tlu_cwp1; // cwp - thread1
input [2:0] exu_tlu_cwp2; // cwp - thread2
input [2:0] exu_tlu_cwp3; // cwp - thread3
//
// componets from trap stack arrays (tsas)
input [`TSA_CWP_WIDTH-1:0] tsa0_rdata_cwp;
input [`TSA_PSTATE_WIDTH-1:0] tsa0_rdata_pstate;
input [`TSA_CCR_WIDTH-1:0] tsa0_rdata_ccr;
input [`TLU_ASI_STATE_WIDTH-1:0] tsa0_rdata_asi;
input [`TSA_GLOBAL_WIDTH-1:0] tsa0_rdata_gl;
input [46:0] tsa0_rdata_pc;
input [`TSA_TTYPE_WIDTH-1:0] tsa1_rdata_ttype;
input [46:0] tsa1_rdata_npc;
input [`TSA_HTSTATE_WIDTH-1:0] tsa1_rdata_htstate;
//
// trap pc calculations signals
input [48:0] ifu_tlu_pc_m; // pc
// input [48:0] ifu_tlu_npc_m; // npc
input [`TSA_TTYPE_WIDTH-1:0] tlu_final_offset_w1;
input [33:0] tlu_partial_trap_pc_w1;
input [48:0] tlu_restore_pc_w1;
input [48:0] tlu_restore_npc_w1;
// input [48:0] ifu_pc_w;
input [48:0] ifu_npc_w;
input tlu_restore_pc_sel_w1;
//
// modified due to timing fix
input [2:0] tlu_true_pc_sel_w;
// input tlu_retry_inst_m;
// input tlu_done_inst_m;
// input tlu_dnrtry_inst_m_l;
//
input [`TLU_THRD_NUM-1:0] tlu_thrd_rsel_e;
// global nets
input si, se;
//
//clk
input rclk;
//
// PIC trap experiment
// input [`TLU_THRD_NUM-1:0] tlu_thread_inst_vld_w2; // valid inst for a thread
// input [`TLU_THRD_NUM-1:0] pich_threebelow_flg;
// input [`TLU_THRD_NUM-1:0] pich_twobelow_flg;
// input [`TLU_THRD_NUM-1:0] pich_onebelow_flg;
input tlu_pic_onebelow_e;
input tlu_pic_twobelow_e;
input tlu_pic_cnt_en_m;
input tlu_rst;
//=================================================
// local wires
//=================================================
// local clock
wire clk;
//
// staged thread id
wire [`TLU_THRD_NUM-1:0] thrd_sel_m;
wire [`TLU_THRD_NUM-1:0] tsa_wsel_thrd_w2;
//
// staged tsa_controls
wire tsa_rd_vld_m; // tsa_rd_vld_e,
//
// components from tsas
// tsa0
wire [`TLU_ASI_STATE_WIDTH-1:0] tsa0_asi_m;
wire [`TSA_CWP_WIDTH-1:0] tsa0_cwp_m;
wire [`TSA_CCR_WIDTH-1:0] tsa0_ccr_m;
wire [`TSA_PSTATE_WIDTH-1:0] tsa0_pstate_m;
wire [`TSA_GLOBAL_WIDTH-1:0] tsa0_gl_m;
wire [46:0] tsa0_pc_m;
// tsa1
wire [`TSA_TTYPE_WIDTH-1:0] tsa1_ttype_m;
wire [`TSA_HTSTATE_WIDTH-1:0] tsa1_htstate_m;
wire [46:0] tsa1_npc_m;
//
// modified for timing
// wire [48:0] pc_new_m, npc_new_m;
wire [48:0] pc_new_w, npc_new_w, ifu_pc_w;
wire [46:0] tsa0_pc_w, tsa1_npc_w;
//
// sscan related signals
wire [`TLU_THRD_NUM-1:0] sscan_tid_sel;
wire [`TLU_THRD_NUM-1:0] sscan_ttype_en;
wire [`TLU_THRD_NUM-1:0] sscan_tt_rd_sel;
wire [`TLU_THRD_NUM-1:0] sscan_tt_wr_sel;
wire [`TSA_TTYPE_WIDTH-1:0] sscan_tt0_data;
wire [`TSA_TTYPE_WIDTH-1:0] sscan_tt1_data;
wire [`TSA_TTYPE_WIDTH-1:0] sscan_tt2_data;
wire [`TSA_TTYPE_WIDTH-1:0] sscan_tt3_data;
wire [`TSA_TTYPE_WIDTH-1:0] sscan_tt0_din;
wire [`TSA_TTYPE_WIDTH-1:0] sscan_tt1_din;
wire [`TSA_TTYPE_WIDTH-1:0] sscan_tt2_din;
wire [`TSA_TTYPE_WIDTH-1:0] sscan_tt3_din;
wire [`MISCTL_SSCAN_WIDTH-1:0] misctl_sscan_test_data;
//
// cwp logic
wire cwp_no_change_m;
wire [`TSA_CWP_WIDTH-1:0] cwp_xor_m, trap_old_cwp_m;
wire [48:0] normal_trap_pc_w1, normal_trap_npc_w1;
wire [48:0] trap_pc_w1, trap_npc_w1;
wire [48:0] trap_pc_w2, trap_npc_w2;
//
// PIC experiment
wire tlu_pic_onebelow_m, tlu_pic_twobelow_m;
// wire [`TLU_THRD_NUM-1:0] pic_onebelow_e, pic_twobelow_e;
wire local_rst;
//
//=========================================================================================
// local clock
//=========================================================================================
assign clk = rclk;
//=========================================================================================
// TSA data capture
//=========================================================================================
dff_s #(`TSA_CCR_WIDTH) dff_tsa0_ccr_m (
.din (tsa0_rdata_ccr[`TSA_CCR_WIDTH-1:0]),
.q (tsa0_ccr_m[`TSA_CCR_WIDTH-1:0]),
.clk (clk),
.se (se),
.si (),
.so ()
);
dff_s #(`TSA_CWP_WIDTH) dff_tsa0_cwp_m (
.din (tsa0_rdata_cwp[`TSA_CWP_WIDTH-1:0]),
.q (tsa0_cwp_m[`TSA_CWP_WIDTH-1:0]),
.clk (clk),
.se (se),
.si (),
.so ()
);
dff_s #(`TLU_ASI_STATE_WIDTH) dff_lsu_asi_m (
.din (tsa0_rdata_asi[`TLU_ASI_STATE_WIDTH-1:0]),
.q (tsa0_asi_m[`TLU_ASI_STATE_WIDTH-1:0]),
.clk (clk),
.se (se),
.si (),
.so ()
);
dff_s #(`TSA_PSTATE_WIDTH) dff_tsa0_pstate_m (
.din (tsa0_rdata_pstate[`TSA_CCR_WIDTH-1:0]),
.q (tsa0_pstate_m[`TSA_PSTATE_WIDTH-1:0]),
.clk (clk),
.se (se),
.si (),
.so ()
);
dff_s #(`TSA_GLOBAL_WIDTH) dff_tsa0_gl_m (
.din (tsa0_rdata_gl[`TSA_GLOBAL_WIDTH-1:0]),
.q (tsa0_gl_m[`TSA_GLOBAL_WIDTH-1:0]),
.clk (clk),
.se (se),
.si (),
.so ()
);
dff_s #(47) dff_tsa0_pc_m (
.din (tsa0_rdata_pc[46:0]),
.q (tsa0_pc_m[46:0]),
.clk (clk),
.se (se),
.si (),
.so ()
);
dff_s #(`TSA_TTYPE_WIDTH) dff_tsa1_ttype_m (
.din (tsa1_rdata_ttype[`TSA_TTYPE_WIDTH-1:0]),
.q (tsa1_ttype_m[`TSA_TTYPE_WIDTH-1:0]),
.clk (clk),
.se (se),
.si (),
.so ()
);
dff_s #(`TSA_HTSTATE_WIDTH) dff_tsa1_htstate_m (
.din (tsa1_rdata_htstate[`TSA_HTSTATE_WIDTH-1:0]),
.q (tsa1_htstate_m[`TSA_HTSTATE_WIDTH-1:0]),
.clk (clk),
.se (se),
.si (),
.so ()
);
dff_s #(47) dff_tsa1_npc_m (
.din (tsa1_rdata_npc[46:0]),
.q (tsa1_npc_m[46:0]),
.clk (clk),
.se (se),
.si (),
.so ()
);
//
//=========================================================================================
// CWP/CCR restoration
//=========================================================================================
assign tlu_exu_ccr_m[`TSA_CCR_WIDTH-1:0] =
tsa0_ccr_m[`TSA_CCR_WIDTH-1:0];
assign tlu_exu_cwp_m[`TSA_CWP_WIDTH-1:0] =
tsa0_cwp_m[`TSA_CWP_WIDTH-1:0];
assign tlu_lsu_asi_m[`TLU_ASI_STATE_WIDTH-1:0] =
tsa0_asi_m[`TLU_ASI_STATE_WIDTH-1:0];
// modified/added for timing violations
// moved the logic from exu to tlu due to timing violations
dff_s #(`TLU_THRD_NUM) dff_thrd_sel_m (
.din (tlu_thrd_rsel_e[`TLU_THRD_NUM-1:0]),
.q (thrd_sel_m[`TLU_THRD_NUM-1:0]),
.clk (clk),
.se (se),
.si (),
.so ()
);
mux4ds #(`TSA_CWP_WIDTH) mux_trap_old_cwp_m(
.in0(exu_tlu_cwp0[`TSA_CWP_WIDTH-1:0]),
.in1(exu_tlu_cwp1[`TSA_CWP_WIDTH-1:0]),
.in2(exu_tlu_cwp2[`TSA_CWP_WIDTH-1:0]),
.in3(exu_tlu_cwp3[`TSA_CWP_WIDTH-1:0]),
.sel0(thrd_sel_m[0]),
.sel1(thrd_sel_m[1]),
.sel2(thrd_sel_m[2]),
.sel3(thrd_sel_m[3]),
.dout(trap_old_cwp_m[`TSA_CWP_WIDTH-1:0])
);
assign cwp_xor_m[`TSA_CWP_WIDTH-1:0] =
trap_old_cwp_m[`TSA_CWP_WIDTH-1:0] ^ tlu_exu_cwp_m[`TSA_CWP_WIDTH-1:0];
assign cwp_no_change_m = ~|(cwp_xor_m[`TSA_CWP_WIDTH-1:0]);
assign tlu_cwp_no_change_m = cwp_no_change_m;
//=========================================================================================
// Generate TTYPE SSCAN data
//=========================================================================================
//
// staging the tsa_rd_vld signal
// moved to tlu_tcl for timing
/*
dff_s dff_tsa_rd_vld_e (
.din (tsa_rd_vld),
.q (tsa_rd_vld_e),
.clk (clk),
.se (se),
.si (),
.so ()
);
*/
dff_s dff_tsa_rd_vld_m (
.din (tsa_rd_vld_e),
.q (tsa_rd_vld_m),
.clk (clk),
.se (se),
.si (),
.so ()
);
assign tsa_wsel_thrd_w2[0] = ~tsa_wr_tid[1] & ~tsa_wr_tid[0];
assign tsa_wsel_thrd_w2[1] = ~tsa_wr_tid[1] & tsa_wr_tid[0];
assign tsa_wsel_thrd_w2[2]= tsa_wr_tid[1] & ~tsa_wr_tid[0];
assign tsa_wsel_thrd_w2[3] = tsa_wr_tid[1] & tsa_wr_tid[0];
// generating write indicators of ttype to the tsa
assign sscan_tt_wr_sel[0] =
tsa_ttype_en & tsa1_wr_vld & tsa_wsel_thrd_w2[0];
assign sscan_tt_wr_sel[1] =
tsa_ttype_en & tsa1_wr_vld & tsa_wsel_thrd_w2[1];
assign sscan_tt_wr_sel[2] =
tsa_ttype_en & tsa1_wr_vld & tsa_wsel_thrd_w2[2];
assign sscan_tt_wr_sel[3] =
tsa_ttype_en & tsa1_wr_vld & tsa_wsel_thrd_w2[3];
//
// generating read indicators of ttype from the tsa
assign sscan_tt_rd_sel[0] =
tsa_rd_vld_m & thrd_sel_m[0];
assign sscan_tt_rd_sel[1] =
tsa_rd_vld_m & thrd_sel_m[1];
assign sscan_tt_rd_sel[2] =
tsa_rd_vld_m & thrd_sel_m[2];
assign sscan_tt_rd_sel[3] =
tsa_rd_vld_m & thrd_sel_m[3];
assign sscan_ttype_en[0] =
sscan_tt_rd_sel[0] | sscan_tt_wr_sel[0];
assign sscan_ttype_en[1] =
sscan_tt_rd_sel[1] | sscan_tt_wr_sel[1];
assign sscan_ttype_en[2] =
sscan_tt_rd_sel[2] | sscan_tt_wr_sel[2];
assign sscan_ttype_en[3] =
sscan_tt_rd_sel[3] | sscan_tt_wr_sel[3];
//
assign sscan_tt0_din[`TSA_TTYPE_WIDTH-1:0] =
(sscan_tt_wr_sel[0]) ?
tlu_final_ttype_w2[`TSA_TTYPE_WIDTH-1:0] :
tsa1_ttype_m[`TSA_TTYPE_WIDTH-1:0];
assign sscan_tt1_din[`TSA_TTYPE_WIDTH-1:0] =
(sscan_tt_wr_sel[1]) ?
tlu_final_ttype_w2[`TSA_TTYPE_WIDTH-1:0] :
tsa1_ttype_m[`TSA_TTYPE_WIDTH-1:0];
assign sscan_tt2_din[`TSA_TTYPE_WIDTH-1:0] =
(sscan_tt_wr_sel[2]) ?
tlu_final_ttype_w2[`TSA_TTYPE_WIDTH-1:0] :
tsa1_ttype_m[`TSA_TTYPE_WIDTH-1:0];
assign sscan_tt3_din[`TSA_TTYPE_WIDTH-1:0] =
(sscan_tt_wr_sel[3]) ?
tlu_final_ttype_w2[`TSA_TTYPE_WIDTH-1:0] :
tsa1_ttype_m[`TSA_TTYPE_WIDTH-1:0];
//
dffe_s #(`TSA_TTYPE_WIDTH) dffe_sscan_tt0_data (
.din (sscan_tt0_din[`TSA_TTYPE_WIDTH-1:0]),
.q (sscan_tt0_data[`TSA_TTYPE_WIDTH-1:0]),
.en (sscan_ttype_en[0]),
.clk (clk),
.se (se),
.si (),
.so ()
);
dffe_s #(`TSA_TTYPE_WIDTH) dffe_sscan_tt1_data (
.din (sscan_tt1_din[`TSA_TTYPE_WIDTH-1:0]),
.q (sscan_tt1_data[`TSA_TTYPE_WIDTH-1:0]),
.en (sscan_ttype_en[1]),
.clk (clk),
.se (se),
.si (),
.so ()
);
dffe_s #(`TSA_TTYPE_WIDTH) dffe_sscan_tt2_data (
.din (sscan_tt2_din[`TSA_TTYPE_WIDTH-1:0]),
.q (sscan_tt2_data[`TSA_TTYPE_WIDTH-1:0]),
.en (sscan_ttype_en[2]),
.clk (clk),
.se (se),
.si (),
.so ()
);
dffe_s #(`TSA_TTYPE_WIDTH) dffe_sscan_tt3_data (
.din (sscan_tt3_din[`TSA_TTYPE_WIDTH-1:0]),
.q (sscan_tt3_data[`TSA_TTYPE_WIDTH-1:0]),
.en (sscan_ttype_en[3]),
.clk (clk),
.se (se),
.si (),
.so ()
);
assign sscan_tid_sel[`TLU_THRD_NUM-1:0] =
ctu_sscan_tid[`TLU_THRD_NUM-1:0];
mux4ds #(`MISCTL_SSCAN_WIDTH) mx_sscan_test_data (
.in0 (sscan_tt0_data[`TSA_TTYPE_WIDTH-1:0]),
.in1 (sscan_tt1_data[`TSA_TTYPE_WIDTH-1:0]),
.in2 (sscan_tt2_data[`TSA_TTYPE_WIDTH-1:0]),
.in3 (sscan_tt3_data[`TSA_TTYPE_WIDTH-1:0]),
.sel0 (sscan_tid_sel[0]),
.sel1 (sscan_tid_sel[1]),
.sel2 (sscan_tid_sel[2]),
.sel3 (sscan_tid_sel[3]),
.dout (misctl_sscan_test_data[`MISCTL_SSCAN_WIDTH-1:0])
);
assign tlu_sscan_misctl_data[`MISCTL_SSCAN_WIDTH-1:0] =
misctl_sscan_test_data[`MISCTL_SSCAN_WIDTH-1:0];
//
// code moved from tlu_tcl - trap pc delivery logic
//
assign normal_trap_pc_w1[48:0] =
{1'b0, tlu_partial_trap_pc_w1[33:0],
tlu_final_offset_w1[`TSA_TTYPE_WIDTH-1:0], 5'b00000};
assign normal_trap_npc_w1[48:0] =
{1'b0, tlu_partial_trap_pc_w1[33:0],
tlu_final_offset_w1[`TSA_TTYPE_WIDTH-1:0], 5'b00100};
//
// code moved from tlu_tdp
mux2ds #(49) mx_trap_pc_w1 (
.in0 (normal_trap_pc_w1[48:0]),
.in1 (tlu_restore_pc_w1[48:0]),
.sel0 (~tlu_restore_pc_sel_w1),
.sel1 (tlu_restore_pc_sel_w1),
.dout (trap_pc_w1[48:0])
);
//
dff_s #(49) dff_trap_pc_w2 (
.din (trap_pc_w1[48:0]),
.q (trap_pc_w2[48:0]),
.clk (clk),
.se (se),
.si (),
.so ()
);
assign tlu_ifu_trappc_w2[48:0] = trap_pc_w2[48:0];
mux2ds #(49) mx_trap_npc_w1 (
.in0 (normal_trap_npc_w1[48:0]),
.in1 (tlu_restore_npc_w1[48:0]),
.sel0 (~tlu_restore_pc_sel_w1),
.sel1 (tlu_restore_pc_sel_w1),
.dout (trap_npc_w1[48:0])
);
//
dff_s #(49) dff_trap_npc_w2 (
.din (trap_npc_w1[48:0]),
.q (trap_npc_w2[48:0]),
.clk (clk),
.se (se),
.si (),
.so ()
);
assign tlu_ifu_trapnpc_w2[48:0] = trap_npc_w2[48:0];
//--------------------------------------------------------------------------------
// Recovery PC and NPC selection
//--------------------------------------------------------------------------------
// On done, npc will become pc.
// modified for timing
//
dff_s #(47) dff_tsa0_pc_w (
.din (tsa0_pc_m[46:0]),
.q (tsa0_pc_w[46:0]),
.clk (clk),
.se (se),
.si (),
.so ()
);
dff_s #(49) dff_ifu_pc_w (
.din (ifu_tlu_pc_m[48:0]),
.q (ifu_pc_w[48:0]),
.clk (clk),
.se (se),
.si (),
.so ()
);
mux3ds #(49) mux_pc_new_w (
.in0 ({tsa0_pc_w[46:0], 2'b00}),
.in1 ({tsa1_npc_w[46:0], 2'b00}),
.in2 (ifu_pc_w[48:0]),
.sel0 (tlu_true_pc_sel_w[0]),
.sel1 (tlu_true_pc_sel_w[1]),
.sel2 (tlu_true_pc_sel_w[2]),
.dout (pc_new_w[48:0])
);
assign tlu_pc_new_w[48:0] = pc_new_w[48:0];
//
// On done, npc will become pc.
// On done, npc will stay npc. The valid to the IFU will
// not be signaled along with npc for a done.
// modified for timing
dff_s #(47) dff_tsa1_npc_w (
.din (tsa1_npc_m[46:0]),
.q (tsa1_npc_w[46:0]),
.clk (clk),
.se (se),
.si (),
.so ()
);
mux2ds #(49) mux_npc_new_w (
.in0 ({tsa1_npc_w[46:0],2'b00}),
.in1 (ifu_npc_w[48:0]),
.sel0 (~tlu_true_pc_sel_w[2]),
.sel1 (tlu_true_pc_sel_w[2]),
.dout (npc_new_w[48:0])
);
assign tlu_npc_new_w[48:0] = npc_new_w[48:0];
//--------------------------------------------------------------------------------
// PIC trap experiment
//--------------------------------------------------------------------------------
// added for bug 4785
assign local_rst = tlu_rst;
dffr_s dffr_tlu_exu_pic_onebelow_m (
.din (tlu_pic_onebelow_e),
.q (tlu_pic_onebelow_m),
.rst (local_rst),
.clk (clk),
.se (se),
.si (),
.so ()
);
dffr_s dffr_tlu_exu_pic_twobelow_m (
.din (tlu_pic_twobelow_e),
.q (tlu_pic_twobelow_m),
.rst (local_rst),
.clk (clk),
.se (se),
.si (),
.so ()
);
assign tlu_exu_pic_onebelow_m =
tlu_pic_onebelow_m & tlu_pic_cnt_en_m;
assign tlu_exu_pic_twobelow_m =
tlu_pic_twobelow_m & tlu_pic_cnt_en_m;
/*
assign pic_onebelow_e[0] =
tlu_thread_inst_vld_w2[0]? pich_twobelow_flg[0]: pich_onebelow_flg[0];
assign pic_onebelow_e[1] =
tlu_thread_inst_vld_w2[1]? pich_twobelow_flg[1]: pich_onebelow_flg[1];
assign pic_onebelow_e[2] =
tlu_thread_inst_vld_w2[2]? pich_twobelow_flg[2]: pich_onebelow_flg[2];
assign pic_onebelow_e[3] =
tlu_thread_inst_vld_w2[3]? pich_twobelow_flg[3]: pich_onebelow_flg[3];
assign tlu_pic_onebelow_e =
(tlu_thrd_rsel_e[0]) ? pic_onebelow_e[0]:
(tlu_thrd_rsel_e[1]) ? pic_onebelow_e[1]:
(tlu_thrd_rsel_e[2]) ? pic_onebelow_e[2]:
pic_onebelow_e[3];
assign pic_twobelow_e[0] =
tlu_thread_inst_vld_w2[0]? pich_threebelow_flg[0]: pich_twobelow_flg[0];
assign pic_twobelow_e[1] =
tlu_thread_inst_vld_w2[1]? pich_threebelow_flg[1]: pich_twobelow_flg[1];
assign pic_twobelow_e[2] =
tlu_thread_inst_vld_w2[2]? pich_threebelow_flg[2]: pich_twobelow_flg[2];
assign pic_twobelow_e[3] =
tlu_thread_inst_vld_w2[3]? pich_threebelow_flg[3]: pich_twobelow_flg[3];
assign tlu_pic_twobelow_e =
(tlu_thrd_rsel_e[0]) ? pic_twobelow_e[0]:
(tlu_thrd_rsel_e[1]) ? pic_twobelow_e[1]:
(tlu_thrd_rsel_e[2]) ? pic_twobelow_e[2]:
pic_twobelow_e[3];
*/
endmodule |
module sky130_fd_sc_hdll__or2b (
X ,
A ,
B_N ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input B_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire not0_out ;
wire or0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
not not0 (not0_out , B_N );
or or0 (or0_out_X , not0_out, A );
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule |
module var24_multi (A, B, C, D, E, F, G, H, I, J, K, L, M, N, O, P, Q, R, S, T, U, V, W, X, valid);
input A, B, C, D, E, F, G, H, I, J, K, L, M, N, O, P, Q, R, S, T, U, V, W, X;
output valid;
wire [8:0] min_value = 9'd120;
wire [8:0] max_weight = 9'd60;
wire [8:0] max_volume = 9'd60;
wire [8:0] total_value =
A * 9'd4
+ B * 9'd8
+ C * 9'd0
+ D * 9'd20
+ E * 9'd10
+ F * 9'd12
+ G * 9'd18
+ H * 9'd14
+ I * 9'd6
+ J * 9'd15
+ K * 9'd30
+ L * 9'd8
+ M * 9'd16
+ N * 9'd18
+ O * 9'd18
+ P * 9'd14
+ Q * 9'd7
+ R * 9'd7
+ S * 9'd29
+ T * 9'd23
+ U * 9'd24
+ V * 9'd3
+ W * 9'd18
+ X * 9'd5;
wire [8:0] total_weight =
A * 9'd28
+ B * 9'd8
+ C * 9'd27
+ D * 9'd18
+ E * 9'd27
+ F * 9'd28
+ G * 9'd6
+ H * 9'd1
+ I * 9'd20
+ J * 9'd0
+ K * 9'd5
+ L * 9'd13
+ M * 9'd8
+ N * 9'd14
+ O * 9'd22
+ P * 9'd12
+ Q * 9'd23
+ R * 9'd26
+ S * 9'd1
+ T * 9'd22
+ U * 9'd26
+ V * 9'd15
+ W * 9'd0
+ X * 9'd21;
wire [8:0] total_volume =
A * 9'd27
+ B * 9'd27
+ C * 9'd4
+ D * 9'd4
+ E * 9'd0
+ F * 9'd24
+ G * 9'd4
+ H * 9'd20
+ I * 9'd12
+ J * 9'd15
+ K * 9'd5
+ L * 9'd2
+ M * 9'd9
+ N * 9'd28
+ O * 9'd19
+ P * 9'd18
+ Q * 9'd30
+ R * 9'd12
+ S * 9'd28
+ T * 9'd13
+ U * 9'd18
+ V * 9'd16
+ W * 9'd26
+ X * 9'd3;
assign valid = ((total_value >= min_value) && (total_weight <= max_weight) && (total_volume <= max_volume));
endmodule |
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(I2C0_SDA_I, I2C0_SDA_O, I2C0_SDA_T, I2C0_SCL_I,
I2C0_SCL_O, I2C0_SCL_T, SDIO0_WP, UART0_TX, UART0_RX, TTC0_WAVE0_OUT, TTC0_WAVE1_OUT,
TTC0_WAVE2_OUT, USB0_PORT_INDCTL, USB0_VBUS_PWRSELECT, USB0_VBUS_PWRFAULT,
M_AXI_GP0_ARVALID, M_AXI_GP0_AWVALID, M_AXI_GP0_BREADY, M_AXI_GP0_RREADY,
M_AXI_GP0_WLAST, M_AXI_GP0_WVALID, M_AXI_GP0_ARID, M_AXI_GP0_AWID, M_AXI_GP0_WID,
M_AXI_GP0_ARBURST, M_AXI_GP0_ARLOCK, M_AXI_GP0_ARSIZE, M_AXI_GP0_AWBURST,
M_AXI_GP0_AWLOCK, M_AXI_GP0_AWSIZE, M_AXI_GP0_ARPROT, M_AXI_GP0_AWPROT, M_AXI_GP0_ARADDR,
M_AXI_GP0_AWADDR, M_AXI_GP0_WDATA, M_AXI_GP0_ARCACHE, M_AXI_GP0_ARLEN, M_AXI_GP0_ARQOS,
M_AXI_GP0_AWCACHE, M_AXI_GP0_AWLEN, M_AXI_GP0_AWQOS, M_AXI_GP0_WSTRB, M_AXI_GP0_ACLK,
M_AXI_GP0_ARREADY, M_AXI_GP0_AWREADY, M_AXI_GP0_BVALID, M_AXI_GP0_RLAST,
M_AXI_GP0_RVALID, M_AXI_GP0_WREADY, M_AXI_GP0_BID, M_AXI_GP0_RID, M_AXI_GP0_BRESP,
M_AXI_GP0_RRESP, M_AXI_GP0_RDATA, IRQ_F2P, FCLK_CLK0, FCLK_RESET0_N, MIO, DDR_CAS_n, DDR_CKE,
DDR_Clk_n, DDR_Clk, DDR_CS_n, DDR_DRSTB, DDR_ODT, DDR_RAS_n, DDR_WEB, DDR_BankAddr, DDR_Addr,
DDR_VRN, DDR_VRP, DDR_DM, DDR_DQ, DDR_DQS_n, DDR_DQS, PS_SRSTB, PS_CLK, PS_PORB)
/* synthesis syn_black_box black_box_pad_pin="I2C0_SDA_I,I2C0_SDA_O,I2C0_SDA_T,I2C0_SCL_I,I2C0_SCL_O,I2C0_SCL_T,SDIO0_WP,UART0_TX,UART0_RX,TTC0_WAVE0_OUT,TTC0_WAVE1_OUT,TTC0_WAVE2_OUT,USB0_PORT_INDCTL[1:0],USB0_VBUS_PWRSELECT,USB0_VBUS_PWRFAULT,M_AXI_GP0_ARVALID,M_AXI_GP0_AWVALID,M_AXI_GP0_BREADY,M_AXI_GP0_RREADY,M_AXI_GP0_WLAST,M_AXI_GP0_WVALID,M_AXI_GP0_ARID[11:0],M_AXI_GP0_AWID[11:0],M_AXI_GP0_WID[11:0],M_AXI_GP0_ARBURST[1:0],M_AXI_GP0_ARLOCK[1:0],M_AXI_GP0_ARSIZE[2:0],M_AXI_GP0_AWBURST[1:0],M_AXI_GP0_AWLOCK[1:0],M_AXI_GP0_AWSIZE[2:0],M_AXI_GP0_ARPROT[2:0],M_AXI_GP0_AWPROT[2:0],M_AXI_GP0_ARADDR[31:0],M_AXI_GP0_AWADDR[31:0],M_AXI_GP0_WDATA[31:0],M_AXI_GP0_ARCACHE[3:0],M_AXI_GP0_ARLEN[3:0],M_AXI_GP0_ARQOS[3:0],M_AXI_GP0_AWCACHE[3:0],M_AXI_GP0_AWLEN[3:0],M_AXI_GP0_AWQOS[3:0],M_AXI_GP0_WSTRB[3:0],M_AXI_GP0_ACLK,M_AXI_GP0_ARREADY,M_AXI_GP0_AWREADY,M_AXI_GP0_BVALID,M_AXI_GP0_RLAST,M_AXI_GP0_RVALID,M_AXI_GP0_WREADY,M_AXI_GP0_BID[11:0],M_AXI_GP0_RID[11:0],M_AXI_GP0_BRESP[1:0],M_AXI_GP0_RRESP[1:0],M_AXI_GP0_RDATA[31:0],IRQ_F2P[0:0],FCLK_CLK0,FCLK_RESET0_N,MIO[53:0],DDR_CAS_n,DDR_CKE,DDR_Clk_n,DDR_Clk,DDR_CS_n,DDR_DRSTB,DDR_ODT,DDR_RAS_n,DDR_WEB,DDR_BankAddr[2:0],DDR_Addr[14:0],DDR_VRN,DDR_VRP,DDR_DM[3:0],DDR_DQ[31:0],DDR_DQS_n[3:0],DDR_DQS[3:0],PS_SRSTB,PS_CLK,PS_PORB" */;
input I2C0_SDA_I;
output I2C0_SDA_O;
output I2C0_SDA_T;
input I2C0_SCL_I;
output I2C0_SCL_O;
output I2C0_SCL_T;
input SDIO0_WP;
output UART0_TX;
input UART0_RX;
output TTC0_WAVE0_OUT;
output TTC0_WAVE1_OUT;
output TTC0_WAVE2_OUT;
output [1:0]USB0_PORT_INDCTL;
output USB0_VBUS_PWRSELECT;
input USB0_VBUS_PWRFAULT;
output M_AXI_GP0_ARVALID;
output M_AXI_GP0_AWVALID;
output M_AXI_GP0_BREADY;
output M_AXI_GP0_RREADY;
output M_AXI_GP0_WLAST;
output M_AXI_GP0_WVALID;
output [11:0]M_AXI_GP0_ARID;
output [11:0]M_AXI_GP0_AWID;
output [11:0]M_AXI_GP0_WID;
output [1:0]M_AXI_GP0_ARBURST;
output [1:0]M_AXI_GP0_ARLOCK;
output [2:0]M_AXI_GP0_ARSIZE;
output [1:0]M_AXI_GP0_AWBURST;
output [1:0]M_AXI_GP0_AWLOCK;
output [2:0]M_AXI_GP0_AWSIZE;
output [2:0]M_AXI_GP0_ARPROT;
output [2:0]M_AXI_GP0_AWPROT;
output [31:0]M_AXI_GP0_ARADDR;
output [31:0]M_AXI_GP0_AWADDR;
output [31:0]M_AXI_GP0_WDATA;
output [3:0]M_AXI_GP0_ARCACHE;
output [3:0]M_AXI_GP0_ARLEN;
output [3:0]M_AXI_GP0_ARQOS;
output [3:0]M_AXI_GP0_AWCACHE;
output [3:0]M_AXI_GP0_AWLEN;
output [3:0]M_AXI_GP0_AWQOS;
output [3:0]M_AXI_GP0_WSTRB;
input M_AXI_GP0_ACLK;
input M_AXI_GP0_ARREADY;
input M_AXI_GP0_AWREADY;
input M_AXI_GP0_BVALID;
input M_AXI_GP0_RLAST;
input M_AXI_GP0_RVALID;
input M_AXI_GP0_WREADY;
input [11:0]M_AXI_GP0_BID;
input [11:0]M_AXI_GP0_RID;
input [1:0]M_AXI_GP0_BRESP;
input [1:0]M_AXI_GP0_RRESP;
input [31:0]M_AXI_GP0_RDATA;
input [0:0]IRQ_F2P;
output FCLK_CLK0;
output FCLK_RESET0_N;
inout [53:0]MIO;
inout DDR_CAS_n;
inout DDR_CKE;
inout DDR_Clk_n;
inout DDR_Clk;
inout DDR_CS_n;
inout DDR_DRSTB;
inout DDR_ODT;
inout DDR_RAS_n;
inout DDR_WEB;
inout [2:0]DDR_BankAddr;
inout [14:0]DDR_Addr;
inout DDR_VRN;
inout DDR_VRP;
inout [3:0]DDR_DM;
inout [31:0]DDR_DQ;
inout [3:0]DDR_DQS_n;
inout [3:0]DDR_DQS;
inout PS_SRSTB;
inout PS_CLK;
inout PS_PORB;
endmodule |
module TestInitRam
#(
parameter ADDR_WIDTH = 4,
parameter DATA_WIDTH = 8,
parameter MEM_DEPTH = 64
)(
//------------Input Ports------------
input clk,
input rst,
//------------Output Ports-----------
output reg[DATA_WIDTH-1:0] key,
output reg finished,
output reg [ADDR_WIDTH-1:0] addrA,
output reg [ADDR_WIDTH-1:0] addrB,
output reg wr_enaA,
output reg wr_enaB,
output reg[DATA_WIDTH-1:0] data_outA,
output reg[DATA_WIDTH-1:0] data_outB
);
//------------Reg/ Wires-------------
reg [DATA_WIDTH-1:0] tempMem [0:MEM_DEPTH-1];
reg [ADDR_WIDTH-1:0] addr;
always@(posedge clk)//we don't care about synthesizable change whenever clk changes
begin:TransferData
if(tempMem[addr][DATA_WIDTH-1]==1'b1 || tempMem[addr][DATA_WIDTH-1]==1'b0)begin
wr_enaA <= 1'b1;
wr_enaB <= 1'b1;
addrA <= addr;
addrB <= addr+1;
data_outA <= tempMem[addr];
data_outB <= tempMem[addr+1];
addr <= addr+2;//increment address by two we have two ports lets use them both
end else begin
finished <= 1'b1;
wr_enaA <= 1'b0;
wr_enaB <= 1'b0;
addrA <= 0;
addrB <= 0;
wr_enaA<=0;
wr_enaB<=0;
data_outA<=0;
data_outB<=0;
end
end
always@(posedge clk)
begin:Reset
if(rst)
begin
addr <= 0;
addrA <= 0;
addrB <= 0;
wr_enaA<=0;
wr_enaB<=0;
finished<=0;
data_outA<=0;
data_outB<=0;
end
end
integer r1,c1;
initial
begin
r1 = $fopen("Input","rb");
c1 = $fread(tempMem,r1);
$fclose(r1);
end
initial
begin
key = "PASS";
end
endmodule |
module servo_ui(input_rs232,input_rs232_stb,output_control_ack,output_rs232_ack,clk,rst,output_control,output_rs232,output_control_stb,output_rs232_stb,input_rs232_ack);
integer file_count;
real fp_value;
input [15:0] input_rs232;
input input_rs232_stb;
input output_control_ack;
input output_rs232_ack;
input clk;
input rst;
output [15:0] output_control;
output [15:0] output_rs232;
output output_control_stb;
output output_rs232_stb;
output input_rs232_ack;
reg [15:0] timer;
reg timer_enable;
reg stage_0_enable;
reg stage_1_enable;
reg stage_2_enable;
reg [8:0] program_counter;
reg [8:0] program_counter_0;
reg [48:0] instruction_0;
reg [4:0] opcode_0;
reg [5:0] dest_0;
reg [5:0] src_0;
reg [5:0] srcb_0;
reg [31:0] literal_0;
reg [8:0] program_counter_1;
reg [4:0] opcode_1;
reg [5:0] dest_1;
reg [31:0] register_1;
reg [31:0] registerb_1;
reg [31:0] literal_1;
reg [5:0] dest_2;
reg [31:0] result_2;
reg write_enable_2;
reg [15:0] address_2;
reg [15:0] data_out_2;
reg [15:0] data_in_2;
reg memory_enable_2;
reg [15:0] address_4;
reg [31:0] data_out_4;
reg [31:0] data_in_4;
reg memory_enable_4;
reg [15:0] s_output_control_stb;
reg [15:0] s_output_rs232_stb;
reg [15:0] s_output_control;
reg [15:0] s_output_rs232;
reg [15:0] s_input_rs232_ack;
reg [15:0] memory_2 [180:0];
reg [48:0] instructions [285:0];
reg [31:0] registers [37:0];
//////////////////////////////////////////////////////////////////////////////
// MEMORY INITIALIZATION
//
// In order to reduce program size, array contents have been stored into
// memory at initialization. In an FPGA, this will result in the memory being
// initialized when the FPGA configures.
// Memory will not be re-initialized at reset.
// Dissable this behaviour using the no_initialize_memory switch
initial
begin
memory_2[2] = 83;
memory_2[3] = 101;
memory_2[4] = 114;
memory_2[5] = 118;
memory_2[6] = 111;
memory_2[7] = 32;
memory_2[8] = 67;
memory_2[9] = 111;
memory_2[10] = 110;
memory_2[11] = 116;
memory_2[12] = 114;
memory_2[13] = 111;
memory_2[14] = 108;
memory_2[15] = 108;
memory_2[16] = 101;
memory_2[17] = 114;
memory_2[18] = 10;
memory_2[19] = 0;
memory_2[20] = 74;
memory_2[21] = 111;
memory_2[22] = 110;
memory_2[23] = 97;
memory_2[24] = 116;
memory_2[25] = 104;
memory_2[26] = 97;
memory_2[27] = 110;
memory_2[28] = 32;
memory_2[29] = 80;
memory_2[30] = 32;
memory_2[31] = 68;
memory_2[32] = 97;
memory_2[33] = 119;
memory_2[34] = 115;
memory_2[35] = 111;
memory_2[36] = 110;
memory_2[37] = 10;
memory_2[38] = 0;
memory_2[39] = 50;
memory_2[40] = 48;
memory_2[41] = 49;
memory_2[42] = 51;
memory_2[43] = 45;
memory_2[44] = 49;
memory_2[45] = 50;
memory_2[46] = 45;
memory_2[47] = 50;
memory_2[48] = 52;
memory_2[49] = 10;
memory_2[50] = 0;
memory_2[51] = 69;
memory_2[52] = 110;
memory_2[53] = 116;
memory_2[54] = 101;
memory_2[55] = 114;
memory_2[56] = 32;
memory_2[57] = 83;
memory_2[58] = 101;
memory_2[59] = 114;
memory_2[60] = 118;
memory_2[61] = 111;
memory_2[62] = 32;
memory_2[63] = 48;
memory_2[64] = 32;
memory_2[65] = 116;
memory_2[66] = 111;
memory_2[67] = 32;
memory_2[68] = 55;
memory_2[69] = 58;
memory_2[70] = 10;
memory_2[71] = 0;
memory_2[72] = 126;
memory_2[73] = 36;
memory_2[74] = 10;
memory_2[75] = 0;
memory_2[76] = 115;
memory_2[77] = 101;
memory_2[78] = 114;
memory_2[79] = 118;
memory_2[80] = 111;
memory_2[81] = 32;
memory_2[82] = 115;
memory_2[83] = 104;
memory_2[84] = 111;
memory_2[85] = 117;
memory_2[86] = 108;
memory_2[87] = 100;
memory_2[88] = 32;
memory_2[89] = 98;
memory_2[90] = 101;
memory_2[91] = 32;
memory_2[92] = 98;
memory_2[93] = 101;
memory_2[94] = 116;
memory_2[95] = 119;
memory_2[96] = 101;
memory_2[97] = 101;
memory_2[98] = 110;
memory_2[99] = 32;
memory_2[100] = 48;
memory_2[101] = 32;
memory_2[102] = 97;
memory_2[103] = 110;
memory_2[104] = 100;
memory_2[105] = 32;
memory_2[106] = 55;
memory_2[107] = 0;
memory_2[108] = 69;
memory_2[109] = 110;
memory_2[110] = 116;
memory_2[111] = 101;
memory_2[112] = 114;
memory_2[113] = 32;
memory_2[114] = 80;
memory_2[115] = 111;
memory_2[116] = 115;
memory_2[117] = 105;
memory_2[118] = 116;
memory_2[119] = 105;
memory_2[120] = 111;
memory_2[121] = 110;
memory_2[122] = 32;
memory_2[123] = 45;
memory_2[124] = 53;
memory_2[125] = 48;
memory_2[126] = 48;
memory_2[127] = 32;
memory_2[128] = 116;
memory_2[129] = 111;
memory_2[130] = 32;
memory_2[131] = 53;
memory_2[132] = 48;
memory_2[133] = 48;
memory_2[134] = 58;
memory_2[135] = 10;
memory_2[136] = 0;
memory_2[137] = 126;
memory_2[138] = 36;
memory_2[139] = 10;
memory_2[140] = 0;
memory_2[141] = 112;
memory_2[142] = 111;
memory_2[143] = 115;
memory_2[144] = 105;
memory_2[145] = 116;
memory_2[146] = 105;
memory_2[147] = 111;
memory_2[148] = 110;
memory_2[149] = 32;
memory_2[150] = 115;
memory_2[151] = 104;
memory_2[152] = 111;
memory_2[153] = 117;
memory_2[154] = 108;
memory_2[155] = 100;
memory_2[156] = 32;
memory_2[157] = 98;
memory_2[158] = 101;
memory_2[159] = 32;
memory_2[160] = 98;
memory_2[161] = 101;
memory_2[162] = 116;
memory_2[163] = 119;
memory_2[164] = 101;
memory_2[165] = 101;
memory_2[166] = 110;
memory_2[167] = 32;
memory_2[168] = 45;
memory_2[169] = 53;
memory_2[170] = 48;
memory_2[171] = 48;
memory_2[172] = 32;
memory_2[173] = 97;
memory_2[174] = 110;
memory_2[175] = 100;
memory_2[176] = 32;
memory_2[177] = 53;
memory_2[178] = 48;
memory_2[179] = 48;
memory_2[180] = 0;
end
//////////////////////////////////////////////////////////////////////////////
// INSTRUCTION INITIALIZATION
//
// Initialise the contents of the instruction memory
//
// Intruction Set
// ==============
// 0 {'float': False, 'literal': True, 'right': False, 'unsigned': False, 'op': 'jmp_and_link'}
// 1 {'float': False, 'literal': False, 'right': False, 'unsigned': False, 'op': 'stop'}
// 2 {'right': False, 'float': False, 'unsigned': False, 'literal': False, 'input': 'rs232', 'op': 'read'}
// 3 {'float': False, 'literal': False, 'right': False, 'unsigned': False, 'op': 'nop'}
// 4 {'float': False, 'literal': False, 'right': False, 'unsigned': False, 'op': 'move'}
// 5 {'float': False, 'literal': False, 'right': False, 'unsigned': False, 'op': 'jmp_to_reg'}
// 6 {'right': False, 'float': False, 'unsigned': False, 'literal': False, 'output': 'rs232', 'op': 'write'}
// 7 {'float': False, 'literal': True, 'right': False, 'unsigned': False, 'op': 'literal'}
// 8 {'float': False, 'literal': False, 'right': False, 'unsigned': True, 'op': '+'}
// 9 {'right': False, 'element_size': 2, 'float': False, 'unsigned': False, 'literal': False, 'op': 'memory_read_request'}
// 10 {'right': False, 'element_size': 2, 'float': False, 'unsigned': False, 'literal': False, 'op': 'memory_read_wait'}
// 11 {'right': False, 'element_size': 2, 'float': False, 'unsigned': False, 'literal': False, 'op': 'memory_read'}
// 12 {'float': False, 'literal': True, 'right': False, 'unsigned': False, 'op': 'jmp_if_false'}
// 13 {'float': False, 'literal': True, 'right': True, 'unsigned': True, 'op': '+'}
// 14 {'float': False, 'literal': True, 'right': False, 'unsigned': False, 'op': 'goto'}
// 15 {'float': False, 'literal': True, 'right': True, 'unsigned': False, 'op': '>='}
// 16 {'float': False, 'literal': True, 'right': True, 'unsigned': False, 'op': '<='}
// 17 {'float': False, 'literal': True, 'right': True, 'unsigned': True, 'op': '=='}
// 18 {'float': False, 'literal': True, 'right': True, 'unsigned': True, 'op': '-'}
// 19 {'float': False, 'literal': True, 'right': True, 'unsigned': False, 'op': '*'}
// 20 {'float': False, 'literal': True, 'right': True, 'unsigned': True, 'op': '>='}
// 21 {'float': False, 'literal': True, 'right': True, 'unsigned': True, 'op': '<='}
// 22 {'right': False, 'float': False, 'unsigned': False, 'literal': False, 'output': 'control', 'op': 'write'}
// Intructions
// ===========
initial
begin
instructions[0] = {5'd0, 6'd27, 6'd0, 32'd161};//{'dest': 27, 'label': 161, 'op': 'jmp_and_link'}
instructions[1] = {5'd1, 6'd0, 6'd0, 32'd0};//{'op': 'stop'}
instructions[2] = {5'd2, 6'd1, 6'd0, 32'd0};//{'dest': 1, 'input': 'rs232', 'op': 'read'}
instructions[3] = {5'd3, 6'd0, 6'd0, 32'd0};//{'op': 'nop'}
instructions[4] = {5'd3, 6'd0, 6'd0, 32'd0};//{'op': 'nop'}
instructions[5] = {5'd4, 6'd14, 6'd1, 32'd0};//{'dest': 14, 'src': 1, 'op': 'move'}
instructions[6] = {5'd5, 6'd0, 6'd13, 32'd0};//{'src': 13, 'op': 'jmp_to_reg'}
instructions[7] = {5'd4, 6'd1, 6'd16, 32'd0};//{'dest': 1, 'src': 16, 'op': 'move'}
instructions[8] = {5'd3, 6'd0, 6'd0, 32'd0};//{'op': 'nop'}
instructions[9] = {5'd3, 6'd0, 6'd0, 32'd0};//{'op': 'nop'}
instructions[10] = {5'd6, 6'd0, 6'd1, 32'd0};//{'src': 1, 'output': 'rs232', 'op': 'write'}
instructions[11] = {5'd5, 6'd0, 6'd15, 32'd0};//{'src': 15, 'op': 'jmp_to_reg'}
instructions[12] = {5'd7, 6'd19, 6'd0, 32'd0};//{'dest': 19, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[13] = {5'd3, 6'd0, 6'd0, 32'd0};//{'op': 'nop'}
instructions[14] = {5'd3, 6'd0, 6'd0, 32'd0};//{'op': 'nop'}
instructions[15] = {5'd4, 6'd2, 6'd19, 32'd0};//{'dest': 2, 'src': 19, 'op': 'move'}
instructions[16] = {5'd3, 6'd0, 6'd0, 32'd0};//{'op': 'nop'}
instructions[17] = {5'd3, 6'd0, 6'd0, 32'd0};//{'op': 'nop'}
instructions[18] = {5'd8, 6'd3, 6'd2, 32'd18};//{'dest': 3, 'src': 2, 'srcb': 18, 'signed': False, 'op': '+'}
instructions[19] = {5'd3, 6'd0, 6'd0, 32'd0};//{'op': 'nop'}
instructions[20] = {5'd3, 6'd0, 6'd0, 32'd0};//{'op': 'nop'}
instructions[21] = {5'd9, 6'd0, 6'd3, 32'd0};//{'element_size': 2, 'src': 3, 'sequence': 32208080, 'op': 'memory_read_request'}
instructions[22] = {5'd3, 6'd0, 6'd0, 32'd0};//{'op': 'nop'}
instructions[23] = {5'd10, 6'd0, 6'd3, 32'd0};//{'element_size': 2, 'src': 3, 'sequence': 32208080, 'op': 'memory_read_wait'}
instructions[24] = {5'd11, 6'd1, 6'd3, 32'd0};//{'dest': 1, 'src': 3, 'sequence': 32208080, 'element_size': 2, 'op': 'memory_read'}
instructions[25] = {5'd3, 6'd0, 6'd0, 32'd0};//{'op': 'nop'}
instructions[26] = {5'd3, 6'd0, 6'd0, 32'd0};//{'op': 'nop'}
instructions[27] = {5'd12, 6'd0, 6'd1, 32'd45};//{'src': 1, 'label': 45, 'op': 'jmp_if_false'}
instructions[28] = {5'd4, 6'd3, 6'd19, 32'd0};//{'dest': 3, 'src': 19, 'op': 'move'}
instructions[29] = {5'd3, 6'd0, 6'd0, 32'd0};//{'op': 'nop'}
instructions[30] = {5'd3, 6'd0, 6'd0, 32'd0};//{'op': 'nop'}
instructions[31] = {5'd8, 6'd4, 6'd3, 32'd18};//{'dest': 4, 'src': 3, 'srcb': 18, 'signed': False, 'op': '+'}
instructions[32] = {5'd3, 6'd0, 6'd0, 32'd0};//{'op': 'nop'}
instructions[33] = {5'd3, 6'd0, 6'd0, 32'd0};//{'op': 'nop'}
instructions[34] = {5'd9, 6'd0, 6'd4, 32'd0};//{'element_size': 2, 'src': 4, 'sequence': 32212752, 'op': 'memory_read_request'}
instructions[35] = {5'd3, 6'd0, 6'd0, 32'd0};//{'op': 'nop'}
instructions[36] = {5'd10, 6'd0, 6'd4, 32'd0};//{'element_size': 2, 'src': 4, 'sequence': 32212752, 'op': 'memory_read_wait'}
instructions[37] = {5'd11, 6'd2, 6'd4, 32'd0};//{'dest': 2, 'src': 4, 'sequence': 32212752, 'element_size': 2, 'op': 'memory_read'}
instructions[38] = {5'd3, 6'd0, 6'd0, 32'd0};//{'op': 'nop'}
instructions[39] = {5'd3, 6'd0, 6'd0, 32'd0};//{'op': 'nop'}
instructions[40] = {5'd4, 6'd16, 6'd2, 32'd0};//{'dest': 16, 'src': 2, 'op': 'move'}
instructions[41] = {5'd0, 6'd15, 6'd0, 32'd7};//{'dest': 15, 'label': 7, 'op': 'jmp_and_link'}
instructions[42] = {5'd4, 6'd1, 6'd19, 32'd0};//{'dest': 1, 'src': 19, 'op': 'move'}
instructions[43] = {5'd13, 6'd19, 6'd19, 32'd1};//{'src': 19, 'right': 1, 'dest': 19, 'signed': False, 'op': '+', 'size': 2}
instructions[44] = {5'd14, 6'd0, 6'd0, 32'd46};//{'label': 46, 'op': 'goto'}
instructions[45] = {5'd14, 6'd0, 6'd0, 32'd47};//{'label': 47, 'op': 'goto'}
instructions[46] = {5'd14, 6'd0, 6'd0, 32'd13};//{'label': 13, 'op': 'goto'}
instructions[47] = {5'd5, 6'd0, 6'd17, 32'd0};//{'src': 17, 'op': 'jmp_to_reg'}
instructions[48] = {5'd4, 6'd2, 6'd22, 32'd0};//{'dest': 2, 'src': 22, 'op': 'move'}
instructions[49] = {5'd3, 6'd0, 6'd0, 32'd0};//{'op': 'nop'}
instructions[50] = {5'd3, 6'd0, 6'd0, 32'd0};//{'op': 'nop'}
instructions[51] = {5'd15, 6'd1, 6'd2, 32'd48};//{'src': 2, 'right': 48, 'dest': 1, 'signed': True, 'op': '>=', 'type': 'int', 'size': 2}
instructions[52] = {5'd3, 6'd0, 6'd0, 32'd0};//{'op': 'nop'}
instructions[53] = {5'd3, 6'd0, 6'd0, 32'd0};//{'op': 'nop'}
instructions[54] = {5'd12, 6'd0, 6'd1, 32'd59};//{'src': 1, 'label': 59, 'op': 'jmp_if_false'}
instructions[55] = {5'd4, 6'd2, 6'd22, 32'd0};//{'dest': 2, 'src': 22, 'op': 'move'}
instructions[56] = {5'd3, 6'd0, 6'd0, 32'd0};//{'op': 'nop'}
instructions[57] = {5'd3, 6'd0, 6'd0, 32'd0};//{'op': 'nop'}
instructions[58] = {5'd16, 6'd1, 6'd2, 32'd57};//{'src': 2, 'right': 57, 'dest': 1, 'signed': True, 'op': '<=', 'type': 'int', 'size': 2}
instructions[59] = {5'd3, 6'd0, 6'd0, 32'd0};//{'op': 'nop'}
instructions[60] = {5'd3, 6'd0, 6'd0, 32'd0};//{'op': 'nop'}
instructions[61] = {5'd12, 6'd0, 6'd1, 32'd68};//{'src': 1, 'label': 68, 'op': 'jmp_if_false'}
instructions[62] = {5'd7, 6'd1, 6'd0, 32'd1};//{'dest': 1, 'literal': 1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[63] = {5'd3, 6'd0, 6'd0, 32'd0};//{'op': 'nop'}
instructions[64] = {5'd3, 6'd0, 6'd0, 32'd0};//{'op': 'nop'}
instructions[65] = {5'd4, 6'd21, 6'd1, 32'd0};//{'dest': 21, 'src': 1, 'op': 'move'}
instructions[66] = {5'd5, 6'd0, 6'd20, 32'd0};//{'src': 20, 'op': 'jmp_to_reg'}
instructions[67] = {5'd14, 6'd0, 6'd0, 32'd68};//{'label': 68, 'op': 'goto'}
instructions[68] = {5'd7, 6'd1, 6'd0, 32'd0};//{'dest': 1, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[69] = {5'd3, 6'd0, 6'd0, 32'd0};//{'op': 'nop'}
instructions[70] = {5'd3, 6'd0, 6'd0, 32'd0};//{'op': 'nop'}
instructions[71] = {5'd4, 6'd21, 6'd1, 32'd0};//{'dest': 21, 'src': 1, 'op': 'move'}
instructions[72] = {5'd5, 6'd0, 6'd20, 32'd0};//{'src': 20, 'op': 'jmp_to_reg'}
instructions[73] = {5'd7, 6'd25, 6'd0, 32'd0};//{'dest': 25, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[74] = {5'd7, 6'd26, 6'd0, 32'd0};//{'dest': 26, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[75] = {5'd0, 6'd13, 6'd0, 32'd2};//{'dest': 13, 'label': 2, 'op': 'jmp_and_link'}
instructions[76] = {5'd4, 6'd1, 6'd14, 32'd0};//{'dest': 1, 'src': 14, 'op': 'move'}
instructions[77] = {5'd3, 6'd0, 6'd0, 32'd0};//{'op': 'nop'}
instructions[78] = {5'd3, 6'd0, 6'd0, 32'd0};//{'op': 'nop'}
instructions[79] = {5'd4, 6'd25, 6'd1, 32'd0};//{'dest': 25, 'src': 1, 'op': 'move'}
instructions[80] = {5'd3, 6'd0, 6'd0, 32'd0};//{'op': 'nop'}
instructions[81] = {5'd3, 6'd0, 6'd0, 32'd0};//{'op': 'nop'}
instructions[82] = {5'd4, 6'd2, 6'd25, 32'd0};//{'dest': 2, 'src': 25, 'op': 'move'}
instructions[83] = {5'd3, 6'd0, 6'd0, 32'd0};//{'op': 'nop'}
instructions[84] = {5'd3, 6'd0, 6'd0, 32'd0};//{'op': 'nop'}
instructions[85] = {5'd17, 6'd1, 6'd2, 32'd45};//{'src': 2, 'right': 45, 'dest': 1, 'signed': False, 'op': '==', 'type': 'int', 'size': 2}
instructions[86] = {5'd3, 6'd0, 6'd0, 32'd0};//{'op': 'nop'}
instructions[87] = {5'd3, 6'd0, 6'd0, 32'd0};//{'op': 'nop'}
instructions[88] = {5'd12, 6'd0, 6'd1, 32'd95};//{'src': 1, 'label': 95, 'op': 'jmp_if_false'}
instructions[89] = {5'd7, 6'd1, 6'd0, -32'd1};//{'dest': 1, 'literal': -1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[90] = {5'd7, 6'd1, 6'd0, 32'd0};//{'dest': 1, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[91] = {5'd3, 6'd0, 6'd0, 32'd0};//{'op': 'nop'}
instructions[92] = {5'd3, 6'd0, 6'd0, 32'd0};//{'op': 'nop'}
instructions[93] = {5'd4, 6'd26, 6'd1, 32'd0};//{'dest': 26, 'src': 1, 'op': 'move'}
instructions[94] = {5'd14, 6'd0, 6'd0, 32'd116};//{'label': 116, 'op': 'goto'}
instructions[95] = {5'd4, 6'd2, 6'd25, 32'd0};//{'dest': 2, 'src': 25, 'op': 'move'}
instructions[96] = {5'd3, 6'd0, 6'd0, 32'd0};//{'op': 'nop'}
instructions[97] = {5'd3, 6'd0, 6'd0, 32'd0};//{'op': 'nop'}
instructions[98] = {5'd17, 6'd1, 6'd2, 32'd43};//{'src': 2, 'right': 43, 'dest': 1, 'signed': False, 'op': '==', 'type': 'int', 'size': 2}
instructions[99] = {5'd3, 6'd0, 6'd0, 32'd0};//{'op': 'nop'}
instructions[100] = {5'd3, 6'd0, 6'd0, 32'd0};//{'op': 'nop'}
instructions[101] = {5'd12, 6'd0, 6'd1, 32'd108};//{'src': 1, 'label': 108, 'op': 'jmp_if_false'}
instructions[102] = {5'd7, 6'd1, 6'd0, 32'd1};//{'dest': 1, 'literal': 1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[103] = {5'd7, 6'd1, 6'd0, 32'd0};//{'dest': 1, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[104] = {5'd3, 6'd0, 6'd0, 32'd0};//{'op': 'nop'}
instructions[105] = {5'd3, 6'd0, 6'd0, 32'd0};//{'op': 'nop'}
instructions[106] = {5'd4, 6'd26, 6'd1, 32'd0};//{'dest': 26, 'src': 1, 'op': 'move'}
instructions[107] = {5'd14, 6'd0, 6'd0, 32'd116};//{'label': 116, 'op': 'goto'}
instructions[108] = {5'd7, 6'd1, 6'd0, 32'd1};//{'dest': 1, 'literal': 1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[109] = {5'd4, 6'd2, 6'd25, 32'd0};//{'dest': 2, 'src': 25, 'op': 'move'}
instructions[110] = {5'd3, 6'd0, 6'd0, 32'd0};//{'op': 'nop'}
instructions[111] = {5'd3, 6'd0, 6'd0, 32'd0};//{'op': 'nop'}
instructions[112] = {5'd18, 6'd1, 6'd2, 32'd48};//{'src': 2, 'right': 48, 'dest': 1, 'signed': False, 'op': '-', 'type': 'int', 'size': 2}
instructions[113] = {5'd3, 6'd0, 6'd0, 32'd0};//{'op': 'nop'}
instructions[114] = {5'd3, 6'd0, 6'd0, 32'd0};//{'op': 'nop'}
instructions[115] = {5'd4, 6'd26, 6'd1, 32'd0};//{'dest': 26, 'src': 1, 'op': 'move'}
instructions[116] = {5'd0, 6'd13, 6'd0, 32'd2};//{'dest': 13, 'label': 2, 'op': 'jmp_and_link'}
instructions[117] = {5'd4, 6'd1, 6'd14, 32'd0};//{'dest': 1, 'src': 14, 'op': 'move'}
instructions[118] = {5'd3, 6'd0, 6'd0, 32'd0};//{'op': 'nop'}
instructions[119] = {5'd3, 6'd0, 6'd0, 32'd0};//{'op': 'nop'}
instructions[120] = {5'd4, 6'd25, 6'd1, 32'd0};//{'dest': 25, 'src': 1, 'op': 'move'}
instructions[121] = {5'd4, 6'd2, 6'd26, 32'd0};//{'dest': 2, 'src': 26, 'op': 'move'}
instructions[122] = {5'd3, 6'd0, 6'd0, 32'd0};//{'op': 'nop'}
instructions[123] = {5'd3, 6'd0, 6'd0, 32'd0};//{'op': 'nop'}
instructions[124] = {5'd19, 6'd1, 6'd2, 32'd10};//{'src': 2, 'right': 10, 'dest': 1, 'signed': True, 'op': '*', 'type': 'int', 'size': 2}
instructions[125] = {5'd3, 6'd0, 6'd0, 32'd0};//{'op': 'nop'}
instructions[126] = {5'd3, 6'd0, 6'd0, 32'd0};//{'op': 'nop'}
instructions[127] = {5'd4, 6'd26, 6'd1, 32'd0};//{'dest': 26, 'src': 1, 'op': 'move'}
instructions[128] = {5'd3, 6'd0, 6'd0, 32'd0};//{'op': 'nop'}
instructions[129] = {5'd3, 6'd0, 6'd0, 32'd0};//{'op': 'nop'}
instructions[130] = {5'd4, 6'd2, 6'd26, 32'd0};//{'dest': 2, 'src': 26, 'op': 'move'}
instructions[131] = {5'd4, 6'd4, 6'd25, 32'd0};//{'dest': 4, 'src': 25, 'op': 'move'}
instructions[132] = {5'd3, 6'd0, 6'd0, 32'd0};//{'op': 'nop'}
instructions[133] = {5'd3, 6'd0, 6'd0, 32'd0};//{'op': 'nop'}
instructions[134] = {5'd18, 6'd3, 6'd4, 32'd48};//{'src': 4, 'right': 48, 'dest': 3, 'signed': False, 'op': '-', 'type': 'int', 'size': 2}
instructions[135] = {5'd3, 6'd0, 6'd0, 32'd0};//{'op': 'nop'}
instructions[136] = {5'd3, 6'd0, 6'd0, 32'd0};//{'op': 'nop'}
instructions[137] = {5'd8, 6'd1, 6'd2, 32'd3};//{'srcb': 3, 'src': 2, 'dest': 1, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[138] = {5'd3, 6'd0, 6'd0, 32'd0};//{'op': 'nop'}
instructions[139] = {5'd3, 6'd0, 6'd0, 32'd0};//{'op': 'nop'}
instructions[140] = {5'd4, 6'd26, 6'd1, 32'd0};//{'dest': 26, 'src': 1, 'op': 'move'}
instructions[141] = {5'd4, 6'd3, 6'd25, 32'd0};//{'dest': 3, 'src': 25, 'op': 'move'}
instructions[142] = {5'd3, 6'd0, 6'd0, 32'd0};//{'op': 'nop'}
instructions[143] = {5'd3, 6'd0, 6'd0, 32'd0};//{'op': 'nop'}
instructions[144] = {5'd4, 6'd22, 6'd3, 32'd0};//{'dest': 22, 'src': 3, 'op': 'move'}
instructions[145] = {5'd0, 6'd20, 6'd0, 32'd48};//{'dest': 20, 'label': 48, 'op': 'jmp_and_link'}
instructions[146] = {5'd4, 6'd2, 6'd21, 32'd0};//{'dest': 2, 'src': 21, 'op': 'move'}
instructions[147] = {5'd3, 6'd0, 6'd0, 32'd0};//{'op': 'nop'}
instructions[148] = {5'd3, 6'd0, 6'd0, 32'd0};//{'op': 'nop'}
instructions[149] = {5'd17, 6'd1, 6'd2, 32'd0};//{'src': 2, 'right': 0, 'dest': 1, 'signed': False, 'op': '==', 'type': 'int', 'size': 2}
instructions[150] = {5'd3, 6'd0, 6'd0, 32'd0};//{'op': 'nop'}
instructions[151] = {5'd3, 6'd0, 6'd0, 32'd0};//{'op': 'nop'}
instructions[152] = {5'd12, 6'd0, 6'd1, 32'd155};//{'src': 1, 'label': 155, 'op': 'jmp_if_false'}
instructions[153] = {5'd14, 6'd0, 6'd0, 32'd156};//{'label': 156, 'op': 'goto'}
instructions[154] = {5'd14, 6'd0, 6'd0, 32'd155};//{'label': 155, 'op': 'goto'}
instructions[155] = {5'd14, 6'd0, 6'd0, 32'd116};//{'label': 116, 'op': 'goto'}
instructions[156] = {5'd4, 6'd1, 6'd26, 32'd0};//{'dest': 1, 'src': 26, 'op': 'move'}
instructions[157] = {5'd3, 6'd0, 6'd0, 32'd0};//{'op': 'nop'}
instructions[158] = {5'd3, 6'd0, 6'd0, 32'd0};//{'op': 'nop'}
instructions[159] = {5'd4, 6'd24, 6'd1, 32'd0};//{'dest': 24, 'src': 1, 'op': 'move'}
instructions[160] = {5'd5, 6'd0, 6'd23, 32'd0};//{'src': 23, 'op': 'jmp_to_reg'}
instructions[161] = {5'd7, 6'd28, 6'd0, 32'd0};//{'dest': 28, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[162] = {5'd7, 6'd29, 6'd0, 32'd0};//{'dest': 29, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[163] = {5'd7, 6'd30, 6'd0, 32'd2};//{'dest': 30, 'literal': 2, 'op': 'literal'}
instructions[164] = {5'd3, 6'd0, 6'd0, 32'd0};//{'op': 'nop'}
instructions[165] = {5'd3, 6'd0, 6'd0, 32'd0};//{'op': 'nop'}
instructions[166] = {5'd4, 6'd5, 6'd30, 32'd0};//{'dest': 5, 'src': 30, 'op': 'move'}
instructions[167] = {5'd3, 6'd0, 6'd0, 32'd0};//{'op': 'nop'}
instructions[168] = {5'd3, 6'd0, 6'd0, 32'd0};//{'op': 'nop'}
instructions[169] = {5'd4, 6'd18, 6'd5, 32'd0};//{'dest': 18, 'src': 5, 'op': 'move'}
instructions[170] = {5'd0, 6'd17, 6'd0, 32'd12};//{'dest': 17, 'label': 12, 'op': 'jmp_and_link'}
instructions[171] = {5'd7, 6'd31, 6'd0, 32'd20};//{'dest': 31, 'literal': 20, 'op': 'literal'}
instructions[172] = {5'd3, 6'd0, 6'd0, 32'd0};//{'op': 'nop'}
instructions[173] = {5'd3, 6'd0, 6'd0, 32'd0};//{'op': 'nop'}
instructions[174] = {5'd4, 6'd6, 6'd31, 32'd0};//{'dest': 6, 'src': 31, 'op': 'move'}
instructions[175] = {5'd3, 6'd0, 6'd0, 32'd0};//{'op': 'nop'}
instructions[176] = {5'd3, 6'd0, 6'd0, 32'd0};//{'op': 'nop'}
instructions[177] = {5'd4, 6'd18, 6'd6, 32'd0};//{'dest': 18, 'src': 6, 'op': 'move'}
instructions[178] = {5'd0, 6'd17, 6'd0, 32'd12};//{'dest': 17, 'label': 12, 'op': 'jmp_and_link'}
instructions[179] = {5'd7, 6'd32, 6'd0, 32'd39};//{'dest': 32, 'literal': 39, 'op': 'literal'}
instructions[180] = {5'd3, 6'd0, 6'd0, 32'd0};//{'op': 'nop'}
instructions[181] = {5'd3, 6'd0, 6'd0, 32'd0};//{'op': 'nop'}
instructions[182] = {5'd4, 6'd7, 6'd32, 32'd0};//{'dest': 7, 'src': 32, 'op': 'move'}
instructions[183] = {5'd3, 6'd0, 6'd0, 32'd0};//{'op': 'nop'}
instructions[184] = {5'd3, 6'd0, 6'd0, 32'd0};//{'op': 'nop'}
instructions[185] = {5'd4, 6'd18, 6'd7, 32'd0};//{'dest': 18, 'src': 7, 'op': 'move'}
instructions[186] = {5'd0, 6'd17, 6'd0, 32'd12};//{'dest': 17, 'label': 12, 'op': 'jmp_and_link'}
instructions[187] = {5'd7, 6'd33, 6'd0, 32'd51};//{'dest': 33, 'literal': 51, 'op': 'literal'}
instructions[188] = {5'd3, 6'd0, 6'd0, 32'd0};//{'op': 'nop'}
instructions[189] = {5'd3, 6'd0, 6'd0, 32'd0};//{'op': 'nop'}
instructions[190] = {5'd4, 6'd8, 6'd33, 32'd0};//{'dest': 8, 'src': 33, 'op': 'move'}
instructions[191] = {5'd3, 6'd0, 6'd0, 32'd0};//{'op': 'nop'}
instructions[192] = {5'd3, 6'd0, 6'd0, 32'd0};//{'op': 'nop'}
instructions[193] = {5'd4, 6'd18, 6'd8, 32'd0};//{'dest': 18, 'src': 8, 'op': 'move'}
instructions[194] = {5'd0, 6'd17, 6'd0, 32'd12};//{'dest': 17, 'label': 12, 'op': 'jmp_and_link'}
instructions[195] = {5'd7, 6'd34, 6'd0, 32'd72};//{'dest': 34, 'literal': 72, 'op': 'literal'}
instructions[196] = {5'd3, 6'd0, 6'd0, 32'd0};//{'op': 'nop'}
instructions[197] = {5'd3, 6'd0, 6'd0, 32'd0};//{'op': 'nop'}
instructions[198] = {5'd4, 6'd9, 6'd34, 32'd0};//{'dest': 9, 'src': 34, 'op': 'move'}
instructions[199] = {5'd3, 6'd0, 6'd0, 32'd0};//{'op': 'nop'}
instructions[200] = {5'd3, 6'd0, 6'd0, 32'd0};//{'op': 'nop'}
instructions[201] = {5'd4, 6'd18, 6'd9, 32'd0};//{'dest': 18, 'src': 9, 'op': 'move'}
instructions[202] = {5'd0, 6'd17, 6'd0, 32'd12};//{'dest': 17, 'label': 12, 'op': 'jmp_and_link'}
instructions[203] = {5'd0, 6'd23, 6'd0, 32'd73};//{'dest': 23, 'label': 73, 'op': 'jmp_and_link'}
instructions[204] = {5'd4, 6'd1, 6'd24, 32'd0};//{'dest': 1, 'src': 24, 'op': 'move'}
instructions[205] = {5'd3, 6'd0, 6'd0, 32'd0};//{'op': 'nop'}
instructions[206] = {5'd3, 6'd0, 6'd0, 32'd0};//{'op': 'nop'}
instructions[207] = {5'd4, 6'd28, 6'd1, 32'd0};//{'dest': 28, 'src': 1, 'op': 'move'}
instructions[208] = {5'd3, 6'd0, 6'd0, 32'd0};//{'op': 'nop'}
instructions[209] = {5'd3, 6'd0, 6'd0, 32'd0};//{'op': 'nop'}
instructions[210] = {5'd4, 6'd2, 6'd28, 32'd0};//{'dest': 2, 'src': 28, 'op': 'move'}
instructions[211] = {5'd3, 6'd0, 6'd0, 32'd0};//{'op': 'nop'}
instructions[212] = {5'd3, 6'd0, 6'd0, 32'd0};//{'op': 'nop'}
instructions[213] = {5'd20, 6'd1, 6'd2, 32'd0};//{'src': 2, 'right': 0, 'dest': 1, 'signed': False, 'op': '>=', 'type': 'int', 'size': 2}
instructions[214] = {5'd3, 6'd0, 6'd0, 32'd0};//{'op': 'nop'}
instructions[215] = {5'd3, 6'd0, 6'd0, 32'd0};//{'op': 'nop'}
instructions[216] = {5'd12, 6'd0, 6'd1, 32'd221};//{'src': 1, 'label': 221, 'op': 'jmp_if_false'}
instructions[217] = {5'd4, 6'd2, 6'd28, 32'd0};//{'dest': 2, 'src': 28, 'op': 'move'}
instructions[218] = {5'd3, 6'd0, 6'd0, 32'd0};//{'op': 'nop'}
instructions[219] = {5'd3, 6'd0, 6'd0, 32'd0};//{'op': 'nop'}
instructions[220] = {5'd21, 6'd1, 6'd2, 32'd7};//{'src': 2, 'right': 7, 'dest': 1, 'signed': False, 'op': '<=', 'type': 'int', 'size': 2}
instructions[221] = {5'd3, 6'd0, 6'd0, 32'd0};//{'op': 'nop'}
instructions[222] = {5'd3, 6'd0, 6'd0, 32'd0};//{'op': 'nop'}
instructions[223] = {5'd12, 6'd0, 6'd1, 32'd226};//{'src': 1, 'label': 226, 'op': 'jmp_if_false'}
instructions[224] = {5'd14, 6'd0, 6'd0, 32'd235};//{'label': 235, 'op': 'goto'}
instructions[225] = {5'd14, 6'd0, 6'd0, 32'd234};//{'label': 234, 'op': 'goto'}
instructions[226] = {5'd7, 6'd35, 6'd0, 32'd76};//{'dest': 35, 'literal': 76, 'op': 'literal'}
instructions[227] = {5'd3, 6'd0, 6'd0, 32'd0};//{'op': 'nop'}
instructions[228] = {5'd3, 6'd0, 6'd0, 32'd0};//{'op': 'nop'}
instructions[229] = {5'd4, 6'd10, 6'd35, 32'd0};//{'dest': 10, 'src': 35, 'op': 'move'}
instructions[230] = {5'd3, 6'd0, 6'd0, 32'd0};//{'op': 'nop'}
instructions[231] = {5'd3, 6'd0, 6'd0, 32'd0};//{'op': 'nop'}
instructions[232] = {5'd4, 6'd18, 6'd10, 32'd0};//{'dest': 18, 'src': 10, 'op': 'move'}
instructions[233] = {5'd0, 6'd17, 6'd0, 32'd12};//{'dest': 17, 'label': 12, 'op': 'jmp_and_link'}
instructions[234] = {5'd14, 6'd0, 6'd0, 32'd187};//{'label': 187, 'op': 'goto'}
instructions[235] = {5'd7, 6'd36, 6'd0, 32'd108};//{'dest': 36, 'literal': 108, 'op': 'literal'}
instructions[236] = {5'd3, 6'd0, 6'd0, 32'd0};//{'op': 'nop'}
instructions[237] = {5'd3, 6'd0, 6'd0, 32'd0};//{'op': 'nop'}
instructions[238] = {5'd4, 6'd11, 6'd36, 32'd0};//{'dest': 11, 'src': 36, 'op': 'move'}
instructions[239] = {5'd3, 6'd0, 6'd0, 32'd0};//{'op': 'nop'}
instructions[240] = {5'd3, 6'd0, 6'd0, 32'd0};//{'op': 'nop'}
instructions[241] = {5'd4, 6'd18, 6'd11, 32'd0};//{'dest': 18, 'src': 11, 'op': 'move'}
instructions[242] = {5'd0, 6'd17, 6'd0, 32'd12};//{'dest': 17, 'label': 12, 'op': 'jmp_and_link'}
instructions[243] = {5'd7, 6'd37, 6'd0, 32'd137};//{'dest': 37, 'literal': 137, 'op': 'literal'}
instructions[244] = {5'd3, 6'd0, 6'd0, 32'd0};//{'op': 'nop'}
instructions[245] = {5'd3, 6'd0, 6'd0, 32'd0};//{'op': 'nop'}
instructions[246] = {5'd4, 6'd9, 6'd37, 32'd0};//{'dest': 9, 'src': 37, 'op': 'move'}
instructions[247] = {5'd3, 6'd0, 6'd0, 32'd0};//{'op': 'nop'}
instructions[248] = {5'd3, 6'd0, 6'd0, 32'd0};//{'op': 'nop'}
instructions[249] = {5'd4, 6'd18, 6'd9, 32'd0};//{'dest': 18, 'src': 9, 'op': 'move'}
instructions[250] = {5'd0, 6'd17, 6'd0, 32'd12};//{'dest': 17, 'label': 12, 'op': 'jmp_and_link'}
instructions[251] = {5'd4, 6'd2, 6'd29, 32'd0};//{'dest': 2, 'src': 29, 'op': 'move'}
instructions[252] = {5'd3, 6'd0, 6'd0, 32'd0};//{'op': 'nop'}
instructions[253] = {5'd3, 6'd0, 6'd0, 32'd0};//{'op': 'nop'}
instructions[254] = {5'd20, 6'd1, 6'd2, 32'd0};//{'src': 2, 'right': 0, 'dest': 1, 'signed': False, 'op': '>=', 'type': 'int', 'size': 2}
instructions[255] = {5'd3, 6'd0, 6'd0, 32'd0};//{'op': 'nop'}
instructions[256] = {5'd3, 6'd0, 6'd0, 32'd0};//{'op': 'nop'}
instructions[257] = {5'd12, 6'd0, 6'd1, 32'd262};//{'src': 1, 'label': 262, 'op': 'jmp_if_false'}
instructions[258] = {5'd4, 6'd2, 6'd29, 32'd0};//{'dest': 2, 'src': 29, 'op': 'move'}
instructions[259] = {5'd3, 6'd0, 6'd0, 32'd0};//{'op': 'nop'}
instructions[260] = {5'd3, 6'd0, 6'd0, 32'd0};//{'op': 'nop'}
instructions[261] = {5'd21, 6'd1, 6'd2, 32'd7};//{'src': 2, 'right': 7, 'dest': 1, 'signed': False, 'op': '<=', 'type': 'int', 'size': 2}
instructions[262] = {5'd3, 6'd0, 6'd0, 32'd0};//{'op': 'nop'}
instructions[263] = {5'd3, 6'd0, 6'd0, 32'd0};//{'op': 'nop'}
instructions[264] = {5'd12, 6'd0, 6'd1, 32'd267};//{'src': 1, 'label': 267, 'op': 'jmp_if_false'}
instructions[265] = {5'd14, 6'd0, 6'd0, 32'd276};//{'label': 276, 'op': 'goto'}
instructions[266] = {5'd14, 6'd0, 6'd0, 32'd275};//{'label': 275, 'op': 'goto'}
instructions[267] = {5'd7, 6'd0, 6'd0, 32'd141};//{'dest': 0, 'literal': 141, 'op': 'literal'}
instructions[268] = {5'd3, 6'd0, 6'd0, 32'd0};//{'op': 'nop'}
instructions[269] = {5'd3, 6'd0, 6'd0, 32'd0};//{'op': 'nop'}
instructions[270] = {5'd4, 6'd12, 6'd0, 32'd0};//{'dest': 12, 'src': 0, 'op': 'move'}
instructions[271] = {5'd3, 6'd0, 6'd0, 32'd0};//{'op': 'nop'}
instructions[272] = {5'd3, 6'd0, 6'd0, 32'd0};//{'op': 'nop'}
instructions[273] = {5'd4, 6'd18, 6'd12, 32'd0};//{'dest': 18, 'src': 12, 'op': 'move'}
instructions[274] = {5'd0, 6'd17, 6'd0, 32'd12};//{'dest': 17, 'label': 12, 'op': 'jmp_and_link'}
instructions[275] = {5'd14, 6'd0, 6'd0, 32'd235};//{'label': 235, 'op': 'goto'}
instructions[276] = {5'd4, 6'd1, 6'd28, 32'd0};//{'dest': 1, 'src': 28, 'op': 'move'}
instructions[277] = {5'd3, 6'd0, 6'd0, 32'd0};//{'op': 'nop'}
instructions[278] = {5'd3, 6'd0, 6'd0, 32'd0};//{'op': 'nop'}
instructions[279] = {5'd22, 6'd0, 6'd1, 32'd0};//{'src': 1, 'output': 'control', 'op': 'write'}
instructions[280] = {5'd4, 6'd1, 6'd29, 32'd0};//{'dest': 1, 'src': 29, 'op': 'move'}
instructions[281] = {5'd3, 6'd0, 6'd0, 32'd0};//{'op': 'nop'}
instructions[282] = {5'd3, 6'd0, 6'd0, 32'd0};//{'op': 'nop'}
instructions[283] = {5'd22, 6'd0, 6'd1, 32'd0};//{'src': 1, 'output': 'control', 'op': 'write'}
instructions[284] = {5'd14, 6'd0, 6'd0, 32'd187};//{'label': 187, 'op': 'goto'}
instructions[285] = {5'd5, 6'd0, 6'd27, 32'd0};//{'src': 27, 'op': 'jmp_to_reg'}
end
//////////////////////////////////////////////////////////////////////////////
// CPU IMPLEMENTAION OF C PROCESS
//
// This section of the file contains a CPU implementing the C process.
always @(posedge clk)
begin
//implement memory for 2 byte x n arrays
if (memory_enable_2 == 1'b1) begin
memory_2[address_2] <= data_in_2;
end
data_out_2 <= memory_2[address_2];
memory_enable_2 <= 1'b0;
write_enable_2 <= 0;
//stage 0 instruction fetch
if (stage_0_enable) begin
stage_1_enable <= 1;
instruction_0 <= instructions[program_counter];
opcode_0 = instruction_0[48:44];
dest_0 = instruction_0[43:38];
src_0 = instruction_0[37:32];
srcb_0 = instruction_0[5:0];
literal_0 = instruction_0[31:0];
if(write_enable_2) begin
registers[dest_2] <= result_2;
end
program_counter_0 <= program_counter;
program_counter <= program_counter + 1;
end
//stage 1 opcode fetch
if (stage_1_enable) begin
stage_2_enable <= 1;
register_1 <= registers[src_0];
registerb_1 <= registers[srcb_0];
dest_1 <= dest_0;
literal_1 <= literal_0;
opcode_1 <= opcode_0;
program_counter_1 <= program_counter_0;
end
//stage 2 opcode fetch
if (stage_2_enable) begin
dest_2 <= dest_1;
case(opcode_1)
16'd0:
begin
program_counter <= literal_1;
result_2 <= program_counter_1 + 1;
write_enable_2 <= 1;
stage_0_enable <= 1;
stage_1_enable <= 0;
stage_2_enable <= 0;
end
16'd1:
begin
stage_0_enable <= 0;
stage_1_enable <= 0;
stage_2_enable <= 0;
end
16'd2:
begin
stage_0_enable <= 0;
stage_1_enable <= 0;
stage_2_enable <= 0;
s_input_rs232_ack <= 1'b1;
end
16'd4:
begin
result_2 <= register_1;
write_enable_2 <= 1;
end
16'd5:
begin
program_counter <= register_1;
stage_0_enable <= 1;
stage_1_enable <= 0;
stage_2_enable <= 0;
end
16'd6:
begin
stage_0_enable <= 0;
stage_1_enable <= 0;
stage_2_enable <= 0;
s_output_rs232_stb <= 1'b1;
s_output_rs232 <= register_1;
end
16'd7:
begin
result_2 <= literal_1;
write_enable_2 <= 1;
end
16'd8:
begin
result_2 <= $unsigned(register_1) + $unsigned(registerb_1);
write_enable_2 <= 1;
end
16'd9:
begin
address_2 <= register_1;
end
16'd11:
begin
result_2 <= data_out_2;
write_enable_2 <= 1;
end
16'd12:
begin
if (register_1 == 0) begin
program_counter <= literal_1;
stage_0_enable <= 1;
stage_1_enable <= 0;
stage_2_enable <= 0;
end
end
16'd13:
begin
result_2 <= $unsigned(register_1) + $unsigned(literal_1);
write_enable_2 <= 1;
end
16'd14:
begin
program_counter <= literal_1;
stage_0_enable <= 1;
stage_1_enable <= 0;
stage_2_enable <= 0;
end
16'd15:
begin
result_2 <= $signed(register_1) >= $signed(literal_1);
write_enable_2 <= 1;
end
16'd16:
begin
result_2 <= $signed(register_1) <= $signed(literal_1);
write_enable_2 <= 1;
end
16'd17:
begin
result_2 <= $unsigned(register_1) == $unsigned(literal_1);
write_enable_2 <= 1;
end
16'd18:
begin
result_2 <= $unsigned(register_1) - $unsigned(literal_1);
write_enable_2 <= 1;
end
16'd19:
begin
result_2 <= $signed(register_1) * $signed(literal_1);
write_enable_2 <= 1;
end
16'd20:
begin
result_2 <= $unsigned(register_1) >= $unsigned(literal_1);
write_enable_2 <= 1;
end
16'd21:
begin
result_2 <= $unsigned(register_1) <= $unsigned(literal_1);
write_enable_2 <= 1;
end
16'd22:
begin
stage_0_enable <= 0;
stage_1_enable <= 0;
stage_2_enable <= 0;
s_output_control_stb <= 1'b1;
s_output_control <= register_1;
end
endcase
end
if (s_input_rs232_ack == 1'b1 && input_rs232_stb == 1'b1) begin
result_2 <= input_rs232;
write_enable_2 <= 1;
s_input_rs232_ack <= 1'b0;
stage_0_enable <= 1;
stage_1_enable <= 1;
stage_2_enable <= 1;
end
if (s_output_rs232_stb == 1'b1 && output_rs232_ack == 1'b1) begin
s_output_rs232_stb <= 1'b0;
stage_0_enable <= 1;
stage_1_enable <= 1;
stage_2_enable <= 1;
end
if (s_output_control_stb == 1'b1 && output_control_ack == 1'b1) begin
s_output_control_stb <= 1'b0;
stage_0_enable <= 1;
stage_1_enable <= 1;
stage_2_enable <= 1;
end
if (timer == 0) begin
if (timer_enable) begin
stage_0_enable <= 1;
stage_1_enable <= 1;
stage_2_enable <= 1;
timer_enable <= 0;
end
end else begin
timer <= timer - 1;
end
if (rst == 1'b1) begin
stage_0_enable <= 1;
stage_1_enable <= 0;
stage_2_enable <= 0;
timer <= 0;
timer_enable <= 0;
program_counter <= 0;
s_input_rs232_ack <= 0;
s_output_control_stb <= 0;
s_output_rs232_stb <= 0;
end
end
assign input_rs232_ack = s_input_rs232_ack;
assign output_control_stb = s_output_control_stb;
assign output_control = s_output_control;
assign output_rs232_stb = s_output_rs232_stb;
assign output_rs232 = s_output_rs232;
endmodule |
module sky130_fd_sc_hs__udp_dff$NR_pp$PKG$s (
Q ,
D ,
CLK_N ,
RESET ,
SLEEP_B,
KAPWR ,
VGND ,
VPWR
);
output Q ;
input D ;
input CLK_N ;
input RESET ;
input SLEEP_B;
input KAPWR ;
input VGND ;
input VPWR ;
endmodule |
module sky130_fd_sc_lp__nor4bb_4 (
Y ,
A ,
B ,
C_N ,
D_N ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input C_N ;
input D_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__nor4bb base (
.Y(Y),
.A(A),
.B(B),
.C_N(C_N),
.D_N(D_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule |
module sky130_fd_sc_lp__nor4bb_4 (
Y ,
A ,
B ,
C_N,
D_N
);
output Y ;
input A ;
input B ;
input C_N;
input D_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__nor4bb base (
.Y(Y),
.A(A),
.B(B),
.C_N(C_N),
.D_N(D_N)
);
endmodule |
module MMIO_slave(
input fclk,
input rst_n,
//AXI Inputs
output S_AXI_ACLK,
input [31:0] S_AXI_ARADDR,
input [11:0] S_AXI_ARID,
output S_AXI_ARREADY,
input S_AXI_ARVALID,
input [31:0] S_AXI_AWADDR,
input [11:0] S_AXI_AWID,
output S_AXI_AWREADY,
input S_AXI_AWVALID,
output [11:0] S_AXI_BID,
input S_AXI_BREADY,
output [1:0] S_AXI_BRESP,
output S_AXI_BVALID,
output [31:0] S_AXI_RDATA,
output [11:0] S_AXI_RID,
output S_AXI_RLAST,
input S_AXI_RREADY,
output [1:0] S_AXI_RRESP,
output S_AXI_RVALID,
input [31:0] S_AXI_WDATA,
output S_AXI_WREADY,
input [3:0] S_AXI_WSTRB,
input S_AXI_WVALID,
// MMIO regs
output [31:0] MMIO_CMD,
output [31:0] MMIO_CAM0_CMD,
output [31:0] MMIO_CAM1_CMD,
output [31:0] MMIO_FRAME_BYTES0,
output [31:0] MMIO_TRIBUF_ADDR0,
output [31:0] MMIO_FRAME_BYTES1,
output [31:0] MMIO_TRIBUF_ADDR1,
output [31:0] MMIO_FRAME_BYTES2,
output [31:0] MMIO_TRIBUF_ADDR2,
input [31:0] debug0,
input [31:0] debug1,
input [31:0] debug2,
input [31:0] debug3,
output reg rw_cam0_cmd_valid,
input [17:0] rw_cam0_resp,
input rw_cam0_resp_valid,
output reg rw_cam1_cmd_valid,
input [17:0] rw_cam1_resp,
input rw_cam1_resp_valid,
output MMIO_IRQ
);
assign S_AXI_ACLK = fclk;
//Convert Input signals to AXI lite, to avoid ID matching
wire [31:0] LITE_ARADDR;
wire LITE_ARREADY;
wire LITE_ARVALID;
wire [31:0] LITE_AWADDR;
wire LITE_AWREADY;
wire LITE_AWVALID;
wire LITE_BREADY;
reg [1:0] LITE_BRESP;
wire LITE_BVALID;
reg [31:0] LITE_RDATA;
wire LITE_RREADY;
reg [1:0] LITE_RRESP;
wire LITE_RVALID;
wire [31:0] LITE_WDATA;
wire LITE_WREADY;
wire [3:0] LITE_WSTRB;
wire LITE_WVALID;
wire MMIO_READY;
assign MMIO_READY = 1;
ict106_axilite_conv axilite(
.ACLK(S_AXI_ACLK),
.ARESETN(rst_n),
.S_AXI_ARADDR(S_AXI_ARADDR),
.S_AXI_ARID(S_AXI_ARID),
.S_AXI_ARREADY(S_AXI_ARREADY),
.S_AXI_ARVALID(S_AXI_ARVALID),
.S_AXI_AWADDR(S_AXI_AWADDR),
.S_AXI_AWID(S_AXI_AWID),
.S_AXI_AWREADY(S_AXI_AWREADY),
.S_AXI_AWVALID(S_AXI_AWVALID),
.S_AXI_BID(S_AXI_BID),
.S_AXI_BREADY(S_AXI_BREADY),
.S_AXI_BRESP(S_AXI_BRESP),
.S_AXI_BVALID(S_AXI_BVALID),
.S_AXI_RDATA(S_AXI_RDATA),
.S_AXI_RID(S_AXI_RID),
.S_AXI_RLAST(S_AXI_RLAST),
.S_AXI_RREADY(S_AXI_RREADY),
.S_AXI_RRESP(S_AXI_RRESP),
.S_AXI_RVALID(S_AXI_RVALID),
.S_AXI_WDATA(S_AXI_WDATA),
.S_AXI_WREADY(S_AXI_WREADY),
.S_AXI_WSTRB(S_AXI_WSTRB),
.S_AXI_WVALID(S_AXI_WVALID),
.M_AXI_ARADDR(LITE_ARADDR),
.M_AXI_ARREADY(LITE_ARREADY),
.M_AXI_ARVALID(LITE_ARVALID),
.M_AXI_AWADDR(LITE_AWADDR),
.M_AXI_AWREADY(LITE_AWREADY),
.M_AXI_AWVALID(LITE_AWVALID),
.M_AXI_BREADY(LITE_BREADY),
.M_AXI_BRESP(LITE_BRESP),
.M_AXI_BVALID(LITE_BVALID),
.M_AXI_RDATA(LITE_RDATA),
.M_AXI_RREADY(LITE_RREADY),
.M_AXI_RRESP(LITE_RRESP),
.M_AXI_RVALID(LITE_RVALID),
.M_AXI_WDATA(LITE_WDATA),
.M_AXI_WREADY(LITE_WREADY),
.M_AXI_WSTRB(LITE_WSTRB),
.M_AXI_WVALID(LITE_WVALID)
);
`include "math.v"
`include "macros.vh"
// Needs to be at least
parameter MMIO_SIZE = `MMIO_SIZE;
parameter [31:0] MMIO_STARTADDR = 32'h7000_0000;
parameter W = 32;
//This will only work on Verilog 2005
localparam MMIO_BITS = clog2(MMIO_SIZE);
reg [W-1:0] data[MMIO_SIZE-1:0];
parameter IDLE = 0, RWAIT = 1;
parameter OK = 2'b00, SLVERR = 2'b10;
//READS
reg r_state;
wire [MMIO_BITS-1:0] r_select;
assign r_select = LITE_ARADDR[MMIO_BITS+1:2];
assign ar_good = {LITE_ARADDR[31:(2+MMIO_BITS)], {MMIO_BITS{1'b0}}, LITE_ARADDR[1:0]} == MMIO_STARTADDR;
assign LITE_ARREADY = (r_state == IDLE);
assign LITE_RVALID = (r_state == RWAIT);
// TODO cam0_cmd_write might be valid for multiple cycles??
wire cam0_cmd_write;
assign cam0_cmd_write = (w_state==RWAIT) && LITE_WREADY && (w_select_r==`MMIO_CAM_CMD(0));
`REG(fclk, rw_cam0_cmd_valid, 0, cam0_cmd_write)
reg [31:0] cam0_resp;
reg [31:0] cam0_resp_cnt;
always @(posedge fclk or negedge rst_n) begin
if (!rst_n) begin
cam0_resp <= 32'h0;
cam0_resp_cnt[12:0] <= 0;
end
else if (rw_cam0_resp_valid) begin
cam0_resp <= {14'h0,rw_cam0_resp[17:0]};
cam0_resp_cnt <= cam0_resp_cnt + 1'b1;
end
end
// TODO cam1_cmd_write might be valid for multiple cycles??
wire cam1_cmd_write;
assign cam1_cmd_write = (w_state==RWAIT) && LITE_WREADY && (w_select_r==`MMIO_CAM_CMD(1));
`REG(fclk, rw_cam1_cmd_valid, 0, cam1_cmd_write)
reg [31:0] cam1_resp;
reg [31:0] cam1_resp_cnt;
always @(posedge fclk or negedge rst_n) begin
if (!rst_n) begin
cam1_resp <= 32'h0;
cam1_resp_cnt[12:0] <= 0;
end
else if (rw_cam1_resp_valid) begin
cam1_resp <= {14'h0,rw_cam1_resp[17:0]};
cam1_resp_cnt <= cam1_resp_cnt + 1'b1;
end
end
// Only need to specify read only registers
reg [31:0] read_data;
always @(*) begin
case(r_select)
`MMIO_DEBUG(0) : read_data = debug0;
`MMIO_DEBUG(1) : read_data = debug1;
`MMIO_DEBUG(2) : read_data = debug2;
`MMIO_DEBUG(3) : read_data = debug3;
`MMIO_CAM_RESP(0) : read_data = cam0_resp;
`MMIO_CAM_RESP_CNT(0) : read_data = cam0_resp_cnt;
`MMIO_CAM_RESP(1) : read_data = cam1_resp;
`MMIO_CAM_RESP_CNT(1) : read_data = cam1_resp_cnt;
default : read_data = data[r_select];
endcase
end
// MMIO Mappings
assign MMIO_CMD = data[`MMIO_CMD ];
assign MMIO_CAM0_CMD = data[`MMIO_CAM_CMD(0) ];
assign MMIO_CAM1_CMD = data[`MMIO_CAM_CMD(1) ];
assign MMIO_FRAME_BYTES0 = data[`MMIO_FRAME_BYTES(0) ];
assign MMIO_TRIBUF_ADDR0 = data[`MMIO_TRIBUF_ADDR(0) ];
assign MMIO_FRAME_BYTES1 = data[`MMIO_FRAME_BYTES(1) ];
assign MMIO_TRIBUF_ADDR1 = data[`MMIO_TRIBUF_ADDR(1) ];
assign MMIO_FRAME_BYTES2 = data[`MMIO_FRAME_BYTES(2) ];
assign MMIO_TRIBUF_ADDR2 = data[`MMIO_TRIBUF_ADDR(2) ];
always @(posedge fclk) begin
if(rst_n == 0) begin
r_state <= IDLE;
end else case(r_state)
IDLE: begin
if(LITE_ARVALID) begin
LITE_RRESP <= ar_good ? OK : SLVERR;
LITE_RDATA <= read_data;
r_state <= RWAIT;
end
end
RWAIT: begin
if(LITE_RREADY)
r_state <= IDLE;
end
endcase
end
//WRITES
reg w_state;
reg [MMIO_BITS-1:0] w_select_r;
reg w_wrotedata;
reg w_wroteresp;
wire [MMIO_BITS-1:0] w_select;
assign w_select = LITE_AWADDR[MMIO_BITS+1:2];
assign aw_good = {LITE_ARADDR[31:(2+MMIO_BITS)], {MMIO_BITS{1'b0}}, LITE_AWADDR[1:0]} == MMIO_STARTADDR;
assign LITE_AWREADY = (w_state == IDLE);
assign LITE_WREADY = (w_state == RWAIT) && !w_wrotedata;
assign LITE_BVALID = (w_state == RWAIT) && !w_wroteresp;
always @(posedge fclk) begin
if(rst_n == 0) begin
w_state <= IDLE;
w_wrotedata <= 0;
w_wroteresp <= 0;
end else case(w_state)
IDLE: begin
if(LITE_AWVALID) begin
LITE_BRESP <= aw_good ? OK : SLVERR;
w_select_r <= w_select;
w_state <= RWAIT;
w_wrotedata <= 0;
w_wroteresp <= 0;
end
end
RWAIT: begin
data[0] <= 0;
if (LITE_WREADY) begin
data[w_select_r] <= LITE_WDATA;
end
if((w_wrotedata || LITE_WVALID) && (w_wroteresp || LITE_BREADY)) begin
w_wrotedata <= 0;
w_wroteresp <= 0;
w_state <= IDLE;
end
else if (LITE_WVALID) begin
w_wrotedata <= 1;
end
else if (LITE_BREADY) begin
w_wroteresp <= 1;
end
end
endcase
end
reg v_state;
always @(posedge fclk) begin
if (rst_n == 0)
v_state <= IDLE;
else case(v_state)
IDLE:
if (LITE_WVALID && LITE_WREADY && w_select_r == 2'b00)
v_state <= RWAIT;
RWAIT:
if (MMIO_READY)
v_state <= IDLE;
endcase
end
// interrupts
assign MMIO_IRQ = 0;
endmodule |
module uart_sync_flops
(
// internal signals
rst_i,
clk_i,
stage1_rst_i,
stage1_clk_en_i,
async_dat_i,
sync_dat_o
);
parameter Tp = 1;
parameter width = 1;
parameter init_value = 1'b0;
input rst_i; // reset input
input clk_i; // clock input
input stage1_rst_i; // synchronous reset for stage 1 FF
input stage1_clk_en_i; // synchronous clock enable for stage 1 FF
input [width-1:0] async_dat_i; // asynchronous data input
output [width-1:0] sync_dat_o; // synchronous data output
//
// Interal signal declarations
//
reg [width-1:0] sync_dat_o;
reg [width-1:0] flop_0;
// first stage
always @ (posedge clk_i or posedge rst_i)
begin
if (rst_i)
flop_0 <= #Tp {width{init_value}};
else
flop_0 <= #Tp async_dat_i;
end
// second stage
always @ (posedge clk_i or posedge rst_i)
begin
if (rst_i)
sync_dat_o <= #Tp {width{init_value}};
else if (stage1_rst_i)
sync_dat_o <= #Tp {width{init_value}};
else if (stage1_clk_en_i)
sync_dat_o <= #Tp flop_0;
end
endmodule |
module tb_coretest();
//----------------------------------------------------------------
// Internal constant and parameter definitions.
//----------------------------------------------------------------
parameter DEBUG = 0;
parameter VERBOSE = 0;
parameter CMD_MONITOR = 1;
parameter REC_MONITOR = 0;
parameter CLK_HALF_PERIOD = 1;
parameter CLK_PERIOD = CLK_HALF_PERIOD * 2;
// Command and response constants.
parameter SOC = 8'h55;
parameter EOC = 8'haa;
parameter RESET_CMD = 8'h01;
parameter READ_CMD = 8'h10;
parameter WRITE_CMD = 8'h11;
parameter SOR = 8'haa;
parameter EOR = 8'h55;
parameter UNKNOWN = 8'hfe;
parameter ERROR = 8'hfd;
parameter READ_OK = 8'h7f;
parameter WRITE_OK = 8'h7e;
parameter RESET_OK = 8'h7d;
parameter MAX_MEM = 16'h00ff;
//----------------------------------------------------------------
// Register and Wire declarations.
//----------------------------------------------------------------
reg [31 : 0] cycle_ctr;
reg [31 : 0] error_ctr;
reg [31 : 0] tc_ctr;
reg tb_clk;
reg tb_reset_n;
reg tb_rx_syn;
reg [7 : 0] tb_rx_data;
wire tb_rx_ack;
wire tb_tx_syn;
wire [7 : 0] tb_tx_data;
reg tb_tx_ack;
wire tb_core_reset_;
wire tb_core_cs;
wire tb_core_we;
wire [15 : 0] tb_core_address;
wire [31 : 0] tb_core_write_data;
reg [31 : 0] tb_core_read_data;
reg tb_core_error;
reg [7 : 0] received_tx_data;
reg [31 : 0] test_mem [0 : (MAX_MEM - 1'b1)];
//----------------------------------------------------------------
// Device Under Test.
//----------------------------------------------------------------
coretest dut(
.clk(tb_clk),
.reset_n(tb_reset_n),
// Interface to communication core
.rx_syn(tb_rx_syn),
.rx_data(tb_rx_data),
.rx_ack(tb_rx_ack),
.tx_syn(tb_tx_syn),
.tx_data(tb_tx_data),
.tx_ack(tb_tx_ack),
// Interface to the core being tested.
.core_reset_n(tb_core_reset_n),
.core_cs(tb_core_cs),
.core_we(tb_core_we),
.core_address(tb_core_address),
.core_write_data(tb_core_write_data),
.core_read_data(tb_core_read_data),
.core_error(tb_core_error)
);
//----------------------------------------------------------------
// clk_gen
//
// Clock generator process.
//----------------------------------------------------------------
always
begin : clk_gen
#CLK_HALF_PERIOD tb_clk = !tb_clk;
end // clk_gen
//----------------------------------------------------------------
// sys_monitor
//
// System monitor. Can display status about the dut and TB
// every cycle.
//----------------------------------------------------------------
always
begin : sys_monitor
#(CLK_PERIOD);
if (DEBUG)
begin
dump_dut_state();
$display("");
end
if (VERBOSE)
begin
$display("cycle: 0x%016x", cycle_ctr);
end
cycle_ctr = cycle_ctr + 1;
end
//----------------------------------------------------------------
// command_monitor
//
// Observes any read/write or reset commands generated
// by the DUT.
//----------------------------------------------------------------
always
begin : command_monitor
#(CLK_PERIOD);
if (CMD_MONITOR)
begin
if (!tb_core_reset_n)
begin
$display("Core is being reset by coretest.");
end
if (tb_core_cs)
begin
if (tb_core_we)
begin
$display("Core is being written to: address 0x%08x = 0x%08x",
tb_core_address, tb_core_write_data);
end
else
begin
$display("Core is being read from: address 0x%08x = 0x%08x",
tb_core_address, tb_core_read_data);
end
end
end
end
//----------------------------------------------------------------
// receive_logic
//
// The logic needed to the correct handshake expected by the DUT
// when it is sending bytes.
//----------------------------------------------------------------
always @ (posedge tb_clk)
begin : receive_logic
if (tb_tx_syn)
begin
if (REC_MONITOR)
begin
$display("Receiving byte 0x%02x from the DUT.", tb_tx_data);
end
#(2 * CLK_PERIOD);
tb_tx_ack = 1;
#(2 * CLK_PERIOD);
tb_tx_ack = 0;
end
end // receive_logic
//----------------------------------------------------------------
// test_mem_logic
//
// The logic needed to implement the test memory. We basically
// implement a simple memory to allow read and write operations
// via commands to the DUT to really be executed.
//----------------------------------------------------------------
always @ (posedge tb_clk)
begin : test_mem_logic
if (tb_core_cs)
begin
if (tb_core_we)
begin
if (tb_core_address < MAX_MEM)
begin
$display("Writing to test_mem[0x%08x] = 0x%08x",
tb_core_address, tb_core_write_data);
test_mem[tb_core_address] = tb_core_write_data;
end
else
begin
$display("Writing to incorrect address 0x%08x",
tb_core_address);
tb_core_error = 1;
end
end
else
begin
if (tb_core_address < MAX_MEM)
begin
$display("Reading from test_mem[0x%08x] = 0x%08x",
tb_core_address, tb_core_read_data);
tb_core_read_data = test_mem[tb_core_address];
end
else
begin
$display("Reading from incorrect address 0x%08x",
tb_core_address);
tb_core_error = 1;
end
end
end
else
begin
tb_core_read_data = 32'h00000000;
tb_core_error = 0;
end
end
//----------------------------------------------------------------
// dump_dut_state()
//
// Dump the state of the dut when needed.
//----------------------------------------------------------------
task dump_dut_state();
begin
$display("State of DUT");
$display("------------");
$display("Inputs and outputs:");
$display("rx_syn = 0x%01x, rx_data = 0x%02x, rx_ack = 0x%01x",
dut.rx_syn, dut.rx_data, dut.rx_ack);
$display("tx_syn = 0x%01x, tx_data = 0x%02x, tx_ack = 0x%01x",
dut.tx_syn, dut.tx_data, dut.tx_ack);
$display("cs = 0x%01x, we = 0x%01x, address = 0x%04x, write_data = 0x%08x, read_data = 0x%08x, error = 0x%01x",
dut.core_cs, dut.core_we, dut.core_address, dut.core_write_data, dut.core_read_data, dut.core_error);
$display("");
$display("RX chain signals:");
$display("rx_buffer_wr_ptr = 0x%02x, rx_buffer_rd_ptr = 0x%02x, rx_buffer_ctr = 0x%02x, rx_buffer_empty = 0x%01x, rx_buffer_full = 0x%01x",
dut.rx_buffer_wr_ptr_reg, dut.rx_buffer_rd_ptr_reg, dut.rx_buffer_ctr_reg, dut.rx_buffer_empty, dut.rx_buffer_full);
$display("");
$display("Control signals and FSM state:");
$display("test_engine_reg = 0x%02x, cmd_reg = 0x%02x",
dut.test_engine_reg, dut.cmd_reg);
$display("");
end
endtask // dump_dut_state
//----------------------------------------------------------------
// reset_dut()
//----------------------------------------------------------------
task reset_dut();
begin
$display("*** Toggle reset.");
tb_reset_n = 0;
#(2 * CLK_PERIOD);
tb_reset_n = 1;
end
endtask // reset_dut
//----------------------------------------------------------------
// init_sim()
//
// Initialize all counters and testbed functionality as well
// as setting the DUT inputs to defined values.
//----------------------------------------------------------------
task init_sim();
reg [8 : 0] i;
begin
cycle_ctr = 0;
error_ctr = 0;
tc_ctr = 0;
tb_clk = 0;
tb_reset_n = 1;
tb_rx_syn = 0;
tb_rx_data = 8'h00;
tb_tx_ack = 0;
for (i = 0 ; i < 256 ; i = i + 1)
begin
test_mem[i[7 : 0]] = {4{i[7 : 0]}};
end
end
endtask // init_sim
//----------------------------------------------------------------
// send_byte
//
// Send a byte of data to the DUT.
//----------------------------------------------------------------
task send_byte(input [7 : 0] data);
integer i;
begin
if (VERBOSE)
begin
$display("*** Sending byte 0x%02x to the dut.", data);
$display("*** Setting RX data and RX SYN.");
end
tb_rx_data = data;
tb_rx_syn = 1;
while (!tb_rx_ack)
begin
#CLK_PERIOD;
if (VERBOSE)
begin
$display("*** Waiting for RX ACK.");
end
end
if (VERBOSE)
begin
$display("*** RX ACK seen. Dropping SYN.");
end
tb_rx_syn = 0;
#(2 * CLK_PERIOD);
end
endtask // send_byte
//----------------------------------------------------------------
// send_reset_command
//
// Generates a reset command to the dut.
//----------------------------------------------------------------
task send_reset_command();
begin
$display("*** Sending reset command.");
send_byte(SOC);
send_byte(RESET_CMD);
send_byte(EOC);
$display("*** Sending reset command done.");
end
endtask // send_write_command
//----------------------------------------------------------------
// send_read_command
//
// Generates a read command to the dut.
//----------------------------------------------------------------
task send_read_command(input [15 : 0] addr);
begin
$display("*** Sending read command: address 0x%04x.", addr);
send_byte(SOC);
send_byte(READ_CMD);
send_byte(addr[15 : 8]);
send_byte(addr[7 : 0]);
send_byte(EOC);
$display("*** Sending read command done.");
end
endtask // send_write_command
//----------------------------------------------------------------
// send_write_command
//
// Generates a write command to the dut.
//----------------------------------------------------------------
task send_write_command(input [15 : 0] addr, input [31 : 0] data);
begin
$display("*** Sending write command: address 0x%04x = 0x%08x.", addr, data);
send_byte(SOC);
send_byte(WRITE_CMD);
send_byte(addr[15 : 8]);
send_byte(addr[7 : 0]);
send_byte(data[31 : 24]);
send_byte(data[23 : 16]);
send_byte(data[15 : 8]);
send_byte(data[7 : 0]);
send_byte(EOC);
$display("*** Sending write command done.");
end
endtask // send_write_command
//----------------------------------------------------------------
// display_test_result()
//
// Display the accumulated test results.
//----------------------------------------------------------------
task display_test_result();
begin
if (error_ctr == 0)
begin
$display("*** All %02d test cases completed successfully", tc_ctr);
end
else
begin
$display("*** %02d test cases did not complete successfully.", error_ctr);
end
end
endtask // display_test_result
//----------------------------------------------------------------
// coretest_test
// The main test functionality.
//----------------------------------------------------------------
initial
begin : coretest_test
$display(" -- Testbench for coretest started --");
init_sim();
dump_dut_state();
reset_dut();
dump_dut_state();
#(64 * CLK_PERIOD);
send_reset_command();
send_read_command(16'h0023);
send_read_command(16'h0055);
send_write_command(16'h00aa, 32'h1337beef);
send_read_command(16'h00aa);
send_write_command(16'h0010, 32'h55aa55aa);
send_read_command(16'h0010);
#(200 * CLK_PERIOD);
display_test_result();
$display("*** Simulation done.");
$finish;
end // coretest_test
endmodule |
module esaxi (/*autoarg*/
// Outputs
txwr_access, txwr_packet, txrd_access, txrd_packet, rxrr_wait,
s_axi_arready, s_axi_awready, s_axi_bid, s_axi_bresp, s_axi_bvalid,
s_axi_rid, s_axi_rdata, s_axi_rlast, s_axi_rresp, s_axi_rvalid,
s_axi_wready,
// Inputs
txwr_wait, txrd_wait, rxrr_access, rxrr_packet, s_axi_aclk,
s_axi_aresetn, s_axi_arid, s_axi_araddr, s_axi_arburst,
s_axi_arcache, s_axi_arlock, s_axi_arlen, s_axi_arprot,
s_axi_arqos, s_axi_arsize, s_axi_arvalid, s_axi_awid, s_axi_awaddr,
s_axi_awburst, s_axi_awcache, s_axi_awlock, s_axi_awlen,
s_axi_awprot, s_axi_awqos, s_axi_awsize, s_axi_awvalid,
s_axi_bready, s_axi_rready, s_axi_wid, s_axi_wdata, s_axi_wlast,
s_axi_wstrb, s_axi_wvalid
);
parameter [11:0] ID = 12'h810;
parameter IDW = 12;
parameter PW = 104;
parameter [15:0] RETURN_ADDR = {ID,`EGROUP_RR};
parameter AW = 32;
parameter DW = 32;
/*****************************/
/*Write request for TX fifo */
/*****************************/
output txwr_access;
output [PW-1:0] txwr_packet;
input txwr_wait;
/*****************************/
/*Read request for TX fifo */
/*****************************/
output txrd_access;
output [PW-1:0] txrd_packet;
input txrd_wait;
/*****************************/
/*Read response from RX fifo */
/*****************************/
input rxrr_access;
input [PW-1:0] rxrr_packet;
output rxrr_wait;
/*****************************/
/*AXI slave interface */
/*****************************/
//Clock and reset
input s_axi_aclk;
input s_axi_aresetn;
//Read address channel
input [IDW-1:0] s_axi_arid; //write address ID
input [31:0] s_axi_araddr;
input [1:0] s_axi_arburst;
input [3:0] s_axi_arcache;
input [1:0] s_axi_arlock;
input [7:0] s_axi_arlen;
input [2:0] s_axi_arprot;
input [3:0] s_axi_arqos;
output s_axi_arready;
input [2:0] s_axi_arsize;
input s_axi_arvalid;
//Write address channel
input [IDW-1:0] s_axi_awid; //write address ID
input [31:0] s_axi_awaddr;
input [1:0] s_axi_awburst;
input [3:0] s_axi_awcache;
input [1:0] s_axi_awlock;
input [7:0] s_axi_awlen;
input [2:0] s_axi_awprot;
input [3:0] s_axi_awqos;
input [2:0] s_axi_awsize;
input s_axi_awvalid;
output s_axi_awready;
//Buffered write response channel
output [IDW-1:0] s_axi_bid; //write address ID
output [1:0] s_axi_bresp;
output s_axi_bvalid;
input s_axi_bready;
//Read channel
output [IDW-1:0] s_axi_rid; //write address ID
output [31:0] s_axi_rdata;
output s_axi_rlast;
output [1:0] s_axi_rresp;
output s_axi_rvalid;
input s_axi_rready;
//Write channel
input [IDW-1:0] s_axi_wid; //write address ID
input [31:0] s_axi_wdata;
input s_axi_wlast;
input [3:0] s_axi_wstrb;
input s_axi_wvalid;
output s_axi_wready;
//###################################################
//#WIRE/REG DECLARATIONS
//###################################################
reg s_axi_awready;
reg s_axi_wready;
reg s_axi_bvalid;
reg [1:0] s_axi_bresp;
reg s_axi_arready;
reg [31:0] axi_awaddr; // 32b for epiphany addr
reg [1:0] axi_awburst;
reg [2:0] axi_awsize;
reg [IDW-1:0] axi_bid; //what to do with this?
reg [31:0] axi_araddr;
reg [7:0] axi_arlen;
reg [1:0] axi_arburst;
reg [2:0] axi_arsize;
reg [31:0] s_axi_rdata;
reg [1:0] s_axi_rresp;
reg s_axi_rlast;
reg s_axi_rvalid;
reg [IDW-1:0] s_axi_rid;
reg read_active;
reg [31:0] read_addr;
reg write_active;
reg b_wait; // waiting to issue write response (unlikely?)
reg txwr_access;
reg [1:0] txwr_datamode;
reg [31:0] txwr_dstaddr;
reg [31:0] txwr_data;
reg [31:0] txwr_data_reg;
reg [31:0] txwr_dstaddr_reg;
reg [1:0] txwr_datamode_reg;
reg txrd_access;
reg [1:0] txrd_datamode;
reg [31:0] txrd_dstaddr;
reg [31:0] txrd_srcaddr; //read reaspne address
reg pre_wr_en; // delay for data alignment
reg ractive_reg; // need leading edge of active for 1st req
reg rnext;
wire last_wr_beat;
wire last_rd_beat;
wire [31:0] rxrr_mux_data;
wire [DW-1:0] rxrr_data;
//###################################################
//#PACKET TO MESH
//###################################################
//TXWR
emesh2packet e2p_txwr (
// Outputs
.packet_out (txwr_packet[PW-1:0]),
// Inputs
.access_in (txwr_access),
.write_in (1'b1),
.datamode_in (txwr_datamode[1:0]),
.ctrlmode_in (4'b0),
.dstaddr_in (txwr_dstaddr[AW-1:0]),
.data_in (txwr_data[DW-1:0]),
.srcaddr_in (32'b0)//only 32b slave write supported
);
//TXRD
emesh2packet e2p_txrd (
// Outputs
.packet_out (txrd_packet[PW-1:0]),
// Inputs
.access_in (txrd_access),
.write_in (txrd_write),
.datamode_in (txrd_datamode[1:0]),
.ctrlmode_in (4'b0),
.dstaddr_in (txrd_dstaddr[AW-1:0]),
.data_in (32'b0),
.srcaddr_in (txrd_srcaddr[AW-1:0])
);
//RXRR
packet2emesh p2e_rxrr (
// Outputs
.access_out (),
.write_out (),
.datamode_out (),
.ctrlmode_out (),
.dstaddr_out (),
.data_out (rxrr_data[DW-1:0]),
.srcaddr_out (),
// Inputs
.packet_in (rxrr_packet[PW-1:0])
);
//###################################################
//#WRITE ADDRESS CHANNEL
//###################################################
assign last_wr_beat = s_axi_wready & s_axi_wvalid & s_axi_wlast;
// axi_awready is asserted when there is no write transfer in progress
always @(posedge s_axi_aclk )
begin
if(~s_axi_aresetn)
begin
s_axi_awready <= 1'b1; //TODO: why not set default as 1?
write_active <= 1'b0;
end
else
begin
// we're always ready for an address cycle if we're not doing something else
// note: might make this faster by going ready on last beat instead of after,
// but if we want the very best each channel should be fifo'd.
if( ~s_axi_awready & ~write_active & ~b_wait )
s_axi_awready <= 1'b1;
else if( s_axi_awvalid )
s_axi_awready <= 1'b0;
// the write cycle is "active" as soon as we capture an address, it
// ends on the last beat.
if( s_axi_awready & s_axi_awvalid )
write_active <= 1'b1;
else if( last_wr_beat )
write_active <= 1'b0;
end // else: !if(~s_axi_aresetn)
end // always @ (posedge s_axi_aclk )
// capture address & other aw info, update address during cycle
always @( posedge s_axi_aclk )
if (~s_axi_aresetn)
begin
axi_bid[IDW-1:0] <= 'd0; // capture for write response
axi_awaddr[31:0] <= 32'd0;
axi_awsize[2:0] <= 3'd0;
axi_awburst[1:0] <= 2'd0;
end
else
begin
if( s_axi_awready & s_axi_awvalid )
begin
axi_bid[IDW-1:0] <= s_axi_awid[IDW-1:0];
axi_awaddr[31:0] <= s_axi_awaddr[31:0];
axi_awsize[2:0] <= s_axi_awsize[2:0]; // 0=byte, 1=16b, 2=32b
axi_awburst[1:0] <= s_axi_awburst[1:0]; // type, 0=fixed, 1=incr, 2=wrap
end
else if( s_axi_wvalid & s_axi_wready )
if( axi_awburst == 2'b01 )
begin //incremental burst
// the write address for all the beats in the transaction are increments by the data width.
// note: this should be based on awsize instead to support narrow bursts, i think.
axi_awaddr[31:2] <= axi_awaddr[31:2] + 30'd1;
//awaddr alignedto data width
axi_awaddr[1:0] <= 2'b0;
end // both fixed & wrapping types are treated as fixed, no update.
end // else: !if(~s_axi_aresetn)
//###################################################
//#WRITE RESPONSE CHANNEL
//###################################################
assign s_axi_bid = axi_bid;
always @ (posedge s_axi_aclk)
if(~s_axi_aresetn)
s_axi_wready <= 1'b0;
else
begin
if( last_wr_beat )
s_axi_wready <= 1'b0;
else if( write_active )
s_axi_wready <= ~txwr_wait;
end
always @( posedge s_axi_aclk )
if (~s_axi_aresetn)
begin
s_axi_bvalid <= 1'b0;
s_axi_bresp[1:0] <= 2'b0;
b_wait <= 1'b0;
end
else
begin
if( last_wr_beat )
begin
s_axi_bvalid <= 1'b1;
s_axi_bresp[1:0] <= 2'b0; // 'okay' response
b_wait <= ~s_axi_bready; // note: assumes bready will not drop without valid?
end
else if (s_axi_bready & s_axi_bvalid)
begin
s_axi_bvalid <= 1'b0;
b_wait <= 1'b0;
end
end // else: !if( s_axi_aresetn == 1'b0 )
//###################################################
//#READ REQUEST CHANNEL
//###################################################
assign last_rd_beat = s_axi_rvalid & s_axi_rlast & s_axi_rready;
always @( posedge s_axi_aclk )
if (~s_axi_aresetn)
begin
s_axi_arready <= 1'b0;
read_active <= 1'b0;
end
else
begin
//arready
if( ~s_axi_arready & ~read_active )
s_axi_arready <= 1'b1;
else if( s_axi_arvalid )
s_axi_arready <= 1'b0;
//read_active
if( s_axi_arready & s_axi_arvalid )
read_active <= 1'b1;
else if( last_rd_beat )
read_active <= 1'b0;
end // else: !if( s_axi_aresetn == 1'b0 )
//Read address channel state machine
always @( posedge s_axi_aclk )
if (~s_axi_aresetn)
begin
axi_araddr[31:0] <= 0;
axi_arlen <= 8'd0;
axi_arburst <= 2'd0;
axi_arsize[2:0] <= 3'b0;
s_axi_rlast <= 1'b0;
s_axi_rid[IDW-1:0] <= 'd0;
end
else
begin
if( s_axi_arready & s_axi_arvalid )
begin
axi_araddr[31:0] <= s_axi_araddr[31:0]; //NOTE: upper 2 bits get chopped by Zynq
axi_arlen[7:0] <= s_axi_arlen[7:0];
axi_arburst <= s_axi_arburst;
axi_arsize <= s_axi_arsize;
s_axi_rlast <= ~(|s_axi_arlen[7:0]);
s_axi_rid[IDW-1:0] <= s_axi_arid[IDW-1:0];
end
else if( s_axi_rvalid & s_axi_rready)
begin
axi_arlen[7:0] <= axi_arlen[7:0] - 1;
if(axi_arlen[7:0] == 8'd1)
s_axi_rlast <= 1'b1;
if( s_axi_arburst == 2'b01)
begin //incremental burst
// the read address for all the beats in the transaction are increments by awsize
// note: this should be based on awsize instead to support narrow bursts, i think?
axi_araddr[31:2] <= axi_araddr[31:2] + 1;//TODO: doesn;t seem right...
//araddr aligned to 4 byte boundary
axi_araddr[1:0] <= 2'b0;
//for awsize = 4 bytes (010)
end
end // if ( s_axi_rvalid & s_axi_rready)
end // else: !if( s_axi_aresetn == 1'b0 )
//###################################################
//#WRITE REQUEST
//###################################################
assign txwr_write = 1'b1;
always @( posedge s_axi_aclk )
if (~s_axi_aresetn)
begin
txwr_data_reg[31:0] <= 32'd0;
txwr_dstaddr_reg[31:0] <= 32'd0;
txwr_datamode_reg[1:0] <= 2'd0;
txwr_access <= 1'b0;
pre_wr_en <= 1'b0;
end
else
begin
pre_wr_en <= s_axi_wready & s_axi_wvalid;
txwr_access <= pre_wr_en;
txwr_datamode_reg[1:0] <= axi_awsize[1:0];
txwr_dstaddr_reg[31:2] <= axi_awaddr[31:2]; //set lsbs of address based on write strobes
if(s_axi_wstrb[0] | (axi_awsize[1:0]==2'b10))
begin
txwr_data_reg[31:0] <= s_axi_wdata[31:0];
txwr_dstaddr_reg[1:0] <= 2'd0;
end
else if(s_axi_wstrb[1])
begin
txwr_data_reg[31:0] <= {8'd0, s_axi_wdata[31:8]};
txwr_dstaddr_reg[1:0] <= 2'd1;
end
else if(s_axi_wstrb[2])
begin
txwr_data_reg[31:0] <= {16'd0, s_axi_wdata[31:16]};
txwr_dstaddr_reg[1:0] <= 2'd2;
end
else
begin
txwr_data_reg[31:0] <= {24'd0, s_axi_wdata[31:24]};
txwr_dstaddr_reg[1:0] <= 2'd3;
end
end // else: !if(~s_axi_aresetn)
//Pipeline stage!
always @( posedge s_axi_aclk )
begin
txwr_data[31:0] <= txwr_data_reg[31:0];
txwr_dstaddr[31:0] <= txwr_dstaddr_reg[31:0];
txwr_datamode[1:0] <= txwr_datamode_reg[1:0];
end
//###################################################
//#READ REQUEST (DATA CHANNEL)
//###################################################
// -- reads are performed by sending a read
// -- request out the tx port and waiting for
// -- data to come back through the rx read response port.
// --
// -- because elink reads are not generally
// -- returned in order, we will only allow
// -- one at a time.
//TODO: Fix this nonsense, need to improve performance
//Allow up to N outstanding transactions, use ID to match them up
//Need to look at txrd_wait signal
assign txrd_write = 1'b0;
always @( posedge s_axi_aclk )
if (~s_axi_aresetn)
begin
txrd_access <= 1'b0;
txrd_datamode[1:0] <= 2'd0;
txrd_dstaddr[31:0] <= 32'd0;
txrd_srcaddr[31:0] <= 32'd0;
ractive_reg <= 1'b0;
rnext <= 1'b0;
end
else
begin
ractive_reg <= read_active;
rnext <= s_axi_rvalid & s_axi_rready & ~s_axi_rlast;
txrd_access <= ( ~ractive_reg & read_active ) | rnext;
txrd_datamode[1:0] <= axi_arsize[1:0];
txrd_dstaddr[31:0] <= axi_araddr[31:0];
txrd_srcaddr[31:0] <= {RETURN_ADDR, 16'd0};
//TODO: use arid+srcaddr for out of order ?
end
//###################################################
//#READ RESPONSE (DATA CHANNEL)
//###################################################
//Read response AXI state machine
//Only one outstanding read
assign rxrr_wait = 1'b0;
always @( posedge s_axi_aclk )
if (~s_axi_aresetn)
begin
s_axi_rvalid <= 1'b0;
s_axi_rdata[31:0] <= 32'd0;
s_axi_rresp <= 2'd0;
end
else
begin
if( rxrr_access )
begin
s_axi_rvalid <= 1'b1;
s_axi_rresp <= 2'd0;
case( axi_arsize[1:0] )
2'b00: s_axi_rdata[31:0] <= {4{rxrr_data[7:0]}}; //8-bit
2'b01: s_axi_rdata[31:0] <= {2{rxrr_data[15:0]}}; //16-bit
default: s_axi_rdata[31:0] <= rxrr_data[31:0]; //32-bit
endcase // case ( axi_arsize[1:0] )
end
else if( s_axi_rready )
s_axi_rvalid <= 1'b0;
end // else: !if( s_axi_aresetn == 1'b0 )
endmodule |
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
reg [2:0] in;
wire a,y,y_fixed;
wire b = in[0];
wire en = in[1];
pullup(a);
ChildA childa ( .A(a), .B(b), .en(en), .Y(y),.Yfix(y_fixed) );
initial in=0;
// Test loop
always @ (posedge clk) begin
in <= in + 1;
$display ( "a %d b %d en %d y %d yfix: %d)" , a, b, en, y, y_fixed);
if (en) begin
// driving b
// a should be b
// y and yfix should also be b
if (a!=b || y != b || y_fixed != b) begin
$display ( "Expected a %d y %b yfix %b" , a, y, y_fixed);
$stop;
end
end else begin
// not driving b
// a should be 1 (pullup)
// y and yfix shold be 1
if (a!=1 || y != 1 || y_fixed != 1) begin
$display( "Expected a,y,yfix == 1");
$stop;
end
end
if (in==3) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule |
module ChildA(inout A, input B, input en, output Y, output Yfix);
// workaround
wire a_in = A;
ChildB childB(.A(A), .Y(Y));
assign A = en ? B : 1'bz;
ChildB childBfix(.A(a_in),.Y(Yfix));
endmodule |
module ChildB(input A, output Y);
assign Y = A;
endmodule |
module SHIFTREGRAM (
clken,
clock,
shiftin,
shiftout,
taps);
input clken;
input clock;
input [12:0] shiftin;
output [12:0] shiftout;
output [168:0] taps;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clken;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
endmodule |
module memory (
// Wishbone slave interface
input wb_clk_i,
input wb_rst_i,
input [15:0] wb_dat_i,
output [15:0] wb_dat_o,
input [19:1] wb_adr_i,
input wb_we_i,
input [ 1:0] wb_sel_i,
input wb_stb_i,
input wb_cyc_i,
output wb_ack_o
);
// Registers and nets
reg [15:0] ram[0:2**19-1];
wire we;
wire [7:0] bhw, blw;
// Assignments
assign wb_dat_o = ram[wb_adr_i];
assign wb_ack_o = wb_stb_i;
assign we = wb_we_i & wb_stb_i & wb_cyc_i;
assign bhw = wb_sel_i[1] ? wb_dat_i[15:8]
: ram[wb_adr_i][15:8];
assign blw = wb_sel_i[0] ? wb_dat_i[7:0]
: ram[wb_adr_i][7:0];
// Behaviour
always @(posedge wb_clk_i)
if (we) ram[wb_adr_i] <= { bhw, blw };
endmodule |
module mc_hst
(
input mclock,
input reset_n,
input hst_clock,
input hst_gnt, // Grant back from arbiter
input [22:0] hst_org, // Address for HBI request
input hst_read, // Read/write select for HBI request
input hst_req, // Request from HBI (sync to hst_clock)
input rc_push_en,
input rc_pop_en, /* Should also add a select bus so I know
who the push or pop is for. */
output reg [22:0] hst_arb_addr, // MC internal address to arbiter
output reg hst_pop, // Data increment for write data from HBI
output reg hst_push, // Write enable for read data back to HBI
output reg hst_rdy, /* Ready flag must be asserted before HBI
sends request */
output reg [1:0] hst_mw_addr, // The address to read from MW
output reg [1:0] hst_arb_page, // MC internal page count to arbiter
output reg hst_arb_read, // MC internal r/w select to arbiter
output hst_arb_req // MC internal request to arbiter
);
reg [22:0] capt_addr[1:0];
reg [1:0] capt_read;
reg input_select, output_select, capt_select;
reg [1:0] req_sync_1, req_sync_2, req_sync_3;
reg [1:0] hst_push_cnt;
reg [1:0] busy;
reg [1:0] clear_busy;
reg [1:0] clear_busy0;
reg [1:0] clear_busy1;
reg [1:0] avail_mc;
reg final_select;
reg [1:0] hst_arb_req_int;
assign hst_arb_req = |hst_arb_req_int;
// Implement asynchronous interface and capture registers.
// This process should be the only things that runs on hst_clock.
// It captures the request on hst_clock and generates synchronization logic
// to get back to hst_clock domain. It also generates the ready flag
always @ (posedge hst_clock or negedge reset_n) begin
if(!reset_n) begin
input_select <= 1'b0;
hst_rdy <= 1'b1;
capt_addr[0] <= 23'b0;
capt_addr[1] <= 23'b0;
capt_read <= 2'b0;
busy <= 2'b0;
clear_busy0 <= 2'b0;
clear_busy1 <= 2'b0;
end else begin // if (!reset_n)
clear_busy0 <= clear_busy;
clear_busy1 <= clear_busy0;
hst_rdy <= ~&busy;
// If we detect an edge on either clear, then clear the busy flag
if (clear_busy1[0] ^ clear_busy0[0]) busy[0] <= 1'b0;
if (clear_busy1[1] ^ clear_busy0[1]) busy[1] <= 1'b0;
// Capture registers grab necessary data whenever a new request is made
if (hst_req && ~&busy) begin
input_select <= ~input_select;
busy[input_select] <= 1'b1;
capt_addr[input_select] <= hst_org;
capt_read[input_select] <= hst_read;
hst_rdy <= 1'b0;
end
end // else: !if(!reset_n)
end // always @ (posedge hst_clock)
// This is the main mclock domain process.
// It implements synchronizers to move the request from hst_clock over to
// mclock domain. It also has all the mclock capture registers that forward
// the request on to the arbiter.
always @ (posedge mclock or negedge reset_n) begin
if(!reset_n) begin
hst_arb_req_int<= 1'b0;
req_sync_1 <= 2'b0;
req_sync_2 <= 2'b0;
req_sync_3 <= 2'b0;
avail_mc <= 2'b0;
capt_select <= 1'b0;
output_select <= 1'b0;
clear_busy <= 2'b0;
final_select <= 1'b0;
end else begin
// Triple register the request toggle for clock synchronization
req_sync_1 <= busy;
req_sync_2 <= req_sync_1;
req_sync_3 <= req_sync_2;
if (~req_sync_3[0] && req_sync_2[0]) avail_mc[0] <= 1'b1;
if (~req_sync_3[1] && req_sync_2[1]) avail_mc[1] <= 1'b1;
// A rising or falling transition on the synchronized request toggle
// indicates a new request is in the capture registers. In that case it
// is moved to the arbiter request registers and the request signal to
// the arbiter is asserted.
if (avail_mc[output_select]) begin
// make a new request to the arbiter
output_select <= ~output_select;
hst_arb_req_int[output_select] <= 1'b1;
avail_mc[output_select] <= 1'b0;
end // if (req_sync_2 ^ req_sync_3)
hst_arb_read <= capt_read[capt_select];
hst_arb_page <= capt_read[capt_select] ? 2'h3 : 2'h1;
hst_arb_addr <= capt_addr[capt_select];
// When we get a grant from the arbiter, deassert arbiter request and
// generate the grant toggle that is used to reassert ready.
// I should never get a request and grant in the same cycle
if(hst_gnt) begin
capt_select <= ~capt_select;
hst_arb_req_int[capt_select] <= 1'b0;
end // if (hst_gnt)
if (&hst_push_cnt | hst_mw_addr[0]) begin
clear_busy[final_select] <= ~clear_busy[final_select];
final_select <= ~final_select;
end
end // else: !if(!reset_n)
end // always @ (posedge mclock or negedge reset_n)
// finally, we need a process to forward push's and pop's correctly, and to
// mask writes that are part of the burst, but we don't have any data for.
always @ (posedge mclock or negedge reset_n) begin
if(!reset_n) begin
hst_push <= 1'b0;
hst_pop <= 1'b0;
hst_mw_addr <= 2'b0;
hst_push_cnt <= 2'b0;
end else begin
if (rc_push_en) begin
hst_push <= 1'b1;
hst_push_cnt <= hst_push_cnt + 2'b1;
end else hst_push <= 1'b0;
if (rc_pop_en) begin
hst_pop <= 1'b1;
hst_mw_addr <= hst_mw_addr + 2'b1;
end else hst_pop <= 1'b0;
end // else: !if(!reset_n)
end // always @ (posedge mclock)
endmodule |
module bsg_dff #(width_p=-1, harden_p=1, strength_p=1)
(input clock_i
,input [width_p-1:0] data_i
,output [width_p-1:0] data_o
);
`bsg_dff_macro(80,1) else
`bsg_dff_macro(79,1) else
`bsg_dff_macro(78,1) else
`bsg_dff_macro(77,1) else
`bsg_dff_macro(76,1) else
`bsg_dff_macro(75,1) else
`bsg_dff_macro(74,1) else
`bsg_dff_macro(73,1) else
`bsg_dff_macro(72,1) else
`bsg_dff_macro(71,1) else
`bsg_dff_macro(70,1) else
`bsg_dff_macro(69,1) else
`bsg_dff_macro(68,1) else
`bsg_dff_macro(67,1) else
`bsg_dff_macro(66,1) else
`bsg_dff_macro(65,1) else
`bsg_dff_macro(64,1) else
`bsg_dff_macro(63,1) else
`bsg_dff_macro(62,1) else
`bsg_dff_macro(61,1) else
`bsg_dff_macro(60,1) else
`bsg_dff_macro(59,1) else
`bsg_dff_macro(58,1) else
`bsg_dff_macro(57,1) else
`bsg_dff_macro(56,1) else
`bsg_dff_macro(55,1) else
`bsg_dff_macro(54,1) else
`bsg_dff_macro(53,1) else
`bsg_dff_macro(52,1) else
`bsg_dff_macro(51,1) else
`bsg_dff_macro(50,1) else
`bsg_dff_macro(49,1) else
`bsg_dff_macro(48,1) else
`bsg_dff_macro(47,1) else
`bsg_dff_macro(46,1) else
`bsg_dff_macro(45,1) else
`bsg_dff_macro(44,1) else
`bsg_dff_macro(43,1) else
`bsg_dff_macro(42,1) else
`bsg_dff_macro(41,1) else
`bsg_dff_macro(40,1) else
`bsg_dff_macro(39,1) else
`bsg_dff_macro(38,1) else
`bsg_dff_macro(37,1) else
`bsg_dff_macro(36,1) else
`bsg_dff_macro(35,1) else
`bsg_dff_macro(34,1) else
`bsg_dff_macro(33,1) else
`bsg_dff_macro(32,1) else
`bsg_dff_macro(31,1) else
`bsg_dff_macro(30,1) else
`bsg_dff_macro(29,1) else
`bsg_dff_macro(28,1) else
`bsg_dff_macro(27,1) else
`bsg_dff_macro(26,1) else
`bsg_dff_macro(25,1) else
`bsg_dff_macro(24,1) else
`bsg_dff_macro(23,1) else
`bsg_dff_macro(22,1) else
`bsg_dff_macro(21,1) else
`bsg_dff_macro(20,1) else
`bsg_dff_macro(19,1) else
`bsg_dff_macro(18,1) else
`bsg_dff_macro(17,1) else
`bsg_dff_macro(16,1) else
`bsg_dff_macro(15,1) else
`bsg_dff_macro(14,1) else
`bsg_dff_macro(13,1) else
`bsg_dff_macro(12,1) else
`bsg_dff_macro(11,1) else
`bsg_dff_macro(10,1) else
`bsg_dff_macro(9,1) else
`bsg_dff_macro(8,1) else
`bsg_dff_macro(7,1) else
`bsg_dff_macro(6,1) else
`bsg_dff_macro(5,1) else
`bsg_dff_macro(4,1) else
`bsg_dff_macro(3,1) else
`bsg_dff_macro(2,1) else
`bsg_dff_macro(1,1) else
`bsg_dff_macro(40,2) else
`bsg_dff_macro(39,2) else
`bsg_dff_macro(38,2) else
`bsg_dff_macro(37,2) else
`bsg_dff_macro(36,2) else
`bsg_dff_macro(35,2) else
`bsg_dff_macro(34,2) else
`bsg_dff_macro(33,2) else
`bsg_dff_macro(32,2) else
`bsg_dff_macro(31,2) else
`bsg_dff_macro(30,2) else
`bsg_dff_macro(29,2) else
`bsg_dff_macro(28,2) else
`bsg_dff_macro(27,2) else
`bsg_dff_macro(26,2) else
`bsg_dff_macro(25,2) else
`bsg_dff_macro(24,2) else
`bsg_dff_macro(23,2) else
`bsg_dff_macro(22,2) else
`bsg_dff_macro(21,2) else
`bsg_dff_macro(20,2) else
`bsg_dff_macro(19,2) else
`bsg_dff_macro(18,2) else
`bsg_dff_macro(17,2) else
`bsg_dff_macro(16,2) else
`bsg_dff_macro(15,2) else
`bsg_dff_macro(14,2) else
`bsg_dff_macro(13,2) else
`bsg_dff_macro(12,2) else
`bsg_dff_macro(11,2) else
`bsg_dff_macro(10,2) else
`bsg_dff_macro(9,2) else
`bsg_dff_macro(8,2) else
`bsg_dff_macro(7,2) else
`bsg_dff_macro(6,2) else
`bsg_dff_macro(5,2) else
`bsg_dff_macro(4,2) else
`bsg_dff_macro(3,2) else
`bsg_dff_macro(2,2) else
`bsg_dff_macro(1,2) else
`bsg_dff_macro(40,4) else
`bsg_dff_macro(39,4) else
`bsg_dff_macro(38,4) else
`bsg_dff_macro(37,4) else
`bsg_dff_macro(36,4) else
`bsg_dff_macro(35,4) else
`bsg_dff_macro(34,4) else
`bsg_dff_macro(33,4) else
`bsg_dff_macro(32,4) else
`bsg_dff_macro(31,4) else
`bsg_dff_macro(30,4) else
`bsg_dff_macro(29,4) else
`bsg_dff_macro(28,4) else
`bsg_dff_macro(27,4) else
`bsg_dff_macro(26,4) else
`bsg_dff_macro(25,4) else
`bsg_dff_macro(24,4) else
`bsg_dff_macro(23,4) else
`bsg_dff_macro(22,4) else
`bsg_dff_macro(21,4) else
`bsg_dff_macro(20,4) else
`bsg_dff_macro(19,4) else
`bsg_dff_macro(18,4) else
`bsg_dff_macro(17,4) else
`bsg_dff_macro(16,4) else
`bsg_dff_macro(15,4) else
`bsg_dff_macro(14,4) else
`bsg_dff_macro(13,4) else
`bsg_dff_macro(12,4) else
`bsg_dff_macro(11,4) else
`bsg_dff_macro(10,4) else
`bsg_dff_macro(9,4) else
`bsg_dff_macro(8,4) else
`bsg_dff_macro(7,4) else
`bsg_dff_macro(6,4) else
`bsg_dff_macro(5,4) else
`bsg_dff_macro(4,4) else
`bsg_dff_macro(3,4) else
`bsg_dff_macro(2,4) else
`bsg_dff_macro(1,4) else
`bsg_dff_macro(32,2)
else
`bsg_dff_macro(32,8)
else
begin: notmacro
reg [width_p-1:0] data_r;
assign data_o = data_r;
always @(posedge clock_i)
data_r <= data_i;
end
endmodule |
module zybo_zynq_design_auto_pc_0(aclk, aresetn, s_axi_awid, s_axi_awaddr,
s_axi_awlen, s_axi_awsize, s_axi_awburst, s_axi_awlock, s_axi_awcache, s_axi_awprot,
s_axi_awqos, s_axi_awvalid, s_axi_awready, s_axi_wid, s_axi_wdata, s_axi_wstrb, s_axi_wlast,
s_axi_wvalid, s_axi_wready, s_axi_bid, s_axi_bresp, s_axi_bvalid, s_axi_bready, s_axi_arid,
s_axi_araddr, s_axi_arlen, s_axi_arsize, s_axi_arburst, s_axi_arlock, s_axi_arcache,
s_axi_arprot, s_axi_arqos, s_axi_arvalid, s_axi_arready, s_axi_rid, s_axi_rdata, s_axi_rresp,
s_axi_rlast, s_axi_rvalid, s_axi_rready, m_axi_awaddr, m_axi_awprot, m_axi_awvalid,
m_axi_awready, m_axi_wdata, m_axi_wstrb, m_axi_wvalid, m_axi_wready, m_axi_bresp,
m_axi_bvalid, m_axi_bready, m_axi_araddr, m_axi_arprot, m_axi_arvalid, m_axi_arready,
m_axi_rdata, m_axi_rresp, m_axi_rvalid, m_axi_rready)
/* synthesis syn_black_box black_box_pad_pin="aclk,aresetn,s_axi_awid[11:0],s_axi_awaddr[31:0],s_axi_awlen[3:0],s_axi_awsize[2:0],s_axi_awburst[1:0],s_axi_awlock[1:0],s_axi_awcache[3:0],s_axi_awprot[2:0],s_axi_awqos[3:0],s_axi_awvalid,s_axi_awready,s_axi_wid[11:0],s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wlast,s_axi_wvalid,s_axi_wready,s_axi_bid[11:0],s_axi_bresp[1:0],s_axi_bvalid,s_axi_bready,s_axi_arid[11:0],s_axi_araddr[31:0],s_axi_arlen[3:0],s_axi_arsize[2:0],s_axi_arburst[1:0],s_axi_arlock[1:0],s_axi_arcache[3:0],s_axi_arprot[2:0],s_axi_arqos[3:0],s_axi_arvalid,s_axi_arready,s_axi_rid[11:0],s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rlast,s_axi_rvalid,s_axi_rready,m_axi_awaddr[31:0],m_axi_awprot[2:0],m_axi_awvalid,m_axi_awready,m_axi_wdata[31:0],m_axi_wstrb[3:0],m_axi_wvalid,m_axi_wready,m_axi_bresp[1:0],m_axi_bvalid,m_axi_bready,m_axi_araddr[31:0],m_axi_arprot[2:0],m_axi_arvalid,m_axi_arready,m_axi_rdata[31:0],m_axi_rresp[1:0],m_axi_rvalid,m_axi_rready" */;
input aclk;
input aresetn;
input [11:0]s_axi_awid;
input [31:0]s_axi_awaddr;
input [3:0]s_axi_awlen;
input [2:0]s_axi_awsize;
input [1:0]s_axi_awburst;
input [1:0]s_axi_awlock;
input [3:0]s_axi_awcache;
input [2:0]s_axi_awprot;
input [3:0]s_axi_awqos;
input s_axi_awvalid;
output s_axi_awready;
input [11:0]s_axi_wid;
input [31:0]s_axi_wdata;
input [3:0]s_axi_wstrb;
input s_axi_wlast;
input s_axi_wvalid;
output s_axi_wready;
output [11:0]s_axi_bid;
output [1:0]s_axi_bresp;
output s_axi_bvalid;
input s_axi_bready;
input [11:0]s_axi_arid;
input [31:0]s_axi_araddr;
input [3:0]s_axi_arlen;
input [2:0]s_axi_arsize;
input [1:0]s_axi_arburst;
input [1:0]s_axi_arlock;
input [3:0]s_axi_arcache;
input [2:0]s_axi_arprot;
input [3:0]s_axi_arqos;
input s_axi_arvalid;
output s_axi_arready;
output [11:0]s_axi_rid;
output [31:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output s_axi_rlast;
output s_axi_rvalid;
input s_axi_rready;
output [31:0]m_axi_awaddr;
output [2:0]m_axi_awprot;
output m_axi_awvalid;
input m_axi_awready;
output [31:0]m_axi_wdata;
output [3:0]m_axi_wstrb;
output m_axi_wvalid;
input m_axi_wready;
input [1:0]m_axi_bresp;
input m_axi_bvalid;
output m_axi_bready;
output [31:0]m_axi_araddr;
output [2:0]m_axi_arprot;
output m_axi_arvalid;
input m_axi_arready;
input [31:0]m_axi_rdata;
input [1:0]m_axi_rresp;
input m_axi_rvalid;
output m_axi_rready;
endmodule |
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