module_content
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module sky130_fd_sc_hs__a222o (
X ,
A1 ,
A2 ,
B1 ,
B2 ,
C1 ,
C2 ,
VPWR,
VGND
);
// Module ports
output X ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input C1 ;
input C2 ;
input VPWR;
input VGND;
// Local signals
wire B2 and0_out ;
wire B2 and1_out ;
wire B2 and2_out ;
wire or0_out_X ;
wire u_vpwr_vgnd0_out_X;
// Name Output Other arguments
and and0 (and0_out , B1, B2 );
and and1 (and1_out , A1, A2 );
and and2 (and2_out , C1, C2 );
or or0 (or0_out_X , and1_out, and0_out, and2_out);
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_X, or0_out_X, VPWR, VGND );
buf buf0 (X , u_vpwr_vgnd0_out_X );
endmodule |
module sky130_fd_sc_lp__or4bb (
X ,
A ,
B ,
C_N,
D_N
);
output X ;
input A ;
input B ;
input C_N;
input D_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule |
module CORDIC_Arch3v1_W32_EW8_SW23_SWR26_EWR5 ( clk, rst, beg_fsm_cordic,
ack_cordic, operation, data_in, shift_region_flag, ready_cordic,
data_output, beg_add_subt, add_subt_dataA, add_subt_dataB,
result_add_subt, op_add_subt, ready_add_subt, enab_cont_iter );
input [31:0] data_in;
input [1:0] shift_region_flag;
output [31:0] data_output;
output [31:0] add_subt_dataA;
output [31:0] add_subt_dataB;
input [31:0] result_add_subt;
input clk, rst, beg_fsm_cordic, ack_cordic, operation, ready_add_subt;
output ready_cordic, beg_add_subt, op_add_subt, enab_cont_iter;
wire d_ff1_operation_out, d_ff_Yn_31_, d_ff3_sign_out, n281, n640, n641,
n642, n643, n644, n645, n646, n647, n648, n649, n650, n651, n652,
n653, n654, n655, n656, n657, n658, n659, n660, n661, n662, n663,
n664, n665, n666, n667, n668, n669, n670, n671, n672, n673, n674,
n675, n676, n677, n678, n679, n680, n681, n682, n683, n684, n685,
n686, n687, n688, n689, n690, n691, n692, n693, n694, n695, n696,
n697, n698, n699, n700, n701, n702, n703, n704, n705, n706, n707,
n708, n709, n710, n711, n712, n713, n714, n715, n716, n717, n718,
n719, n720, n721, n722, n723, n724, n725, n726, n727, n728, n729,
n730, n731, n732, n733, n734, n735, n736, n737, n738, n739, n740,
n741, n742, n743, n744, n745, n746, n747, n748, n749, n750, n751,
n752, n753, n754, n755, n756, n757, n758, n759, n760, n761, n762,
n763, n764, n765, n766, n767, n768, n769, n770, n771, n772, n773,
n774, n775, n776, n777, n778, n779, n780, n781, n782, n783, n784,
n785, n786, n787, n788, n789, n790, n791, n792, n793, n794, n795,
n796, n797, n798, n799, n800, n801, n802, n803, n804, n805, n806,
n807, n808, n809, n810, n811, n812, n813, n814, n815, n816, n817,
n818, n819, n820, n821, n822, n823, n824, n825, n826, n827, n828,
n829, n830, n831, n832, n833, n834, n835, n836, n837, n838, n839,
n840, n841, n842, n843, n844, n845, n846, n847, n848, n849, n850,
n851, n852, n853, n854, n855, n856, n857, n858, n859, n860, n861,
n862, n863, n864, n865, n866, n867, n868, n869, n870, n871, n872,
n873, n874, n875, n876, n877, n878, n879, n880, n881, n882, n883,
n884, n885, n886, n887, n888, n889, n890, n891, n892, n893, n894,
n895, n896, n897, n898, n899, n900, n901, n902, n903, n904, n905,
n906, n907, n908, n909, n910, n911, n912, n913, n914, n915, n916,
n917, n918, n919, n920, n921, n922, n923, n924, n925, n926, n927,
n928, n929, n930, n931, n932, n933, n934, n935, n936, n937, n938,
n939, n940, n941, n942, n943, n944, n945, n946, n947, n948, n949,
n950, n951, n952, n953, n954, n955, n956, n957, n958, n959, n960,
n961, n962, n963, n964, n965, n966, n967, n968, n969, n970, n971,
n972, n973, n974, n975, n976, n977, n978, n979, n980, n981, n982,
n983, n984, n985, n986, n987, n988, n989, n990, intadd_365_B_1_,
intadd_365_CI, intadd_365_SUM_2_, intadd_365_SUM_1_,
intadd_365_SUM_0_, intadd_365_n3, intadd_365_n2, intadd_365_n1, n1056,
n1057, n1058, n1059, n1060, n1061, n1062, n1063, n1064, n1065, n1066,
n1067, n1068, n1069, n1070, n1071, n1072, n1073, n1074, n1075, n1076,
n1077, n1078, n1079, n1080, n1081, n1082, n1083, n1084, n1085, n1086,
n1087, n1088, n1089, n1090, n1091, n1092, n1093, n1094, n1095, n1096,
n1097, n1098, n1099, n1100, n1101, n1102, n1103, n1104, n1105, n1106,
n1107, n1108, n1109, n1110, n1111, n1112, n1113, n1114, n1115, n1116,
n1117, n1118, n1119, n1120, n1121, n1122, n1123, n1124, n1125, n1126,
n1127, n1128, n1129, n1130, n1131, n1132, n1133, n1134, n1135, n1136,
n1137, n1138, n1139, n1140, n1141, n1142, n1143, n1144, n1145, n1146,
n1147, n1148, n1149, n1150, n1151, n1152, n1153, n1154, n1155, n1156,
n1157, n1158, n1159, n1160, n1161, n1162, n1163, n1164, n1165, n1166,
n1167, n1168, n1169, n1170, n1171, n1172, n1173, n1174, n1175, n1176,
n1177, n1178, n1179, n1180, n1181, n1182, n1183, n1184, n1185, n1186,
n1187, n1188, n1189, n1190, n1191, n1192, n1193, n1194, n1195, n1196,
n1197, n1198, n1199, n1200, n1201, n1202, n1203, n1204, n1205, n1206,
n1207, n1208, n1209, n1210, n1211, n1212, n1213, n1214, n1215, n1216,
n1217, n1218, n1219, n1220, n1221, n1222, n1223, n1224, n1225, n1226,
n1227, n1228, n1229, n1230, n1231, n1232, n1233, n1234, n1235, n1236,
n1237, n1238, n1239, n1240, n1241, n1242, n1243, n1244, n1245, n1246,
n1247, n1248, n1249, n1250, n1251, n1252, n1253, n1254, n1255, n1256,
n1257, n1258, n1259, n1260, n1261, n1262, n1263, n1264, n1265, n1266,
n1267, n1268, n1269, n1270, n1271, n1272, n1273, n1274, n1275, n1276,
n1277, n1278, n1279, n1280, n1281, n1282, n1283, n1284, n1285, n1286,
n1287, n1288, n1289, n1290, n1291, n1292, n1293, n1294, n1295, n1296,
n1297, n1298, n1299, n1300, n1301, n1302, n1303, n1304, n1305, n1306,
n1307, n1308, n1309, n1310, n1311, n1312, n1313, n1314, n1315, n1316,
n1317, n1318, n1319, n1320, n1321, n1322, n1323, n1324, n1325, n1326,
n1327, n1328, n1329, n1330, n1331, n1332, n1333, n1334, n1335, n1336,
n1337, n1338, n1339, n1340, n1341, n1342, n1343, n1344, n1345, n1346,
n1347, n1348, n1349, n1350, n1351, n1352, n1353, n1354, n1355, n1356,
n1357, n1358, n1359, n1360, n1361, n1362, n1363, n1364, n1365, n1366,
n1367, n1368, n1369, n1370, n1371, n1372, n1373, n1374, n1375, n1376,
n1377, n1378, n1379, n1380, n1381, n1382, n1383, n1384, n1385, n1386,
n1387, n1388, n1389, n1390, n1391, n1392, n1393, n1394, n1395, n1396,
n1397, n1398, n1399, n1400, n1401, n1402, n1403, n1404, n1405, n1406,
n1407, n1408, n1409, n1410, n1411, n1412, n1413, n1414, n1415, n1416,
n1417, n1418, n1419, n1420, n1421, n1422, n1423, n1424, n1425, n1426,
n1427, n1428, n1429, n1430, n1431, n1432, n1433, n1434, n1435, n1436,
n1437, n1438, n1439, n1440, n1441, n1442, n1443, n1444, n1445, n1446,
n1447, n1448, n1449, n1450, n1451, n1452, n1453, n1454, n1455, n1456,
n1457, n1458, n1459, n1460, n1461, n1462, n1463, n1464, n1466, n1467,
n1468, n1469, n1470, n1471, n1472, n1473, n1474, n1475, n1476, n1477,
n1478, n1479, n1480, n1481, n1482, n1483, n1484, n1485, n1486, n1487,
n1488, n1489, n1490, n1491, n1492, n1493, n1494, n1495, n1496, n1497,
n1498, n1499, n1500, n1501, n1502, n1503, n1504, n1505, n1506, n1507,
n1508, n1509, n1510, n1511, n1512, n1513, n1514, n1515, n1516, n1517,
n1518, n1519, n1520, n1521, n1522, n1523, n1524, n1525, n1526, n1527,
n1528, n1529, n1530, n1531, n1532, n1533;
wire [3:1] cont_iter_out;
wire [1:0] cont_var_out;
wire [1:0] d_ff1_shift_region_flag_out;
wire [31:0] d_ff1_Z;
wire [31:0] d_ff_Xn;
wire [31:0] d_ff_Zn;
wire [29:0] d_ff2_X;
wire [31:1] d_ff2_Y;
wire [31:0] d_ff2_Z;
wire [31:0] d_ff3_sh_x_out;
wire [31:0] d_ff3_sh_y_out;
wire [27:0] d_ff3_LUT_out;
wire [7:0] inst_CORDIC_FSM_v3_state_next;
wire [7:0] inst_CORDIC_FSM_v3_state_reg;
DFFRXLTS reg_operation_Q_reg_0_ ( .D(n984), .CK(clk), .RN(n1529), .Q(
d_ff1_operation_out), .QN(n1495) );
DFFRXLTS reg_region_flag_Q_reg_0_ ( .D(n983), .CK(clk), .RN(n1529), .Q(
d_ff1_shift_region_flag_out[0]), .QN(n1504) );
DFFRXLTS reg_Z0_Q_reg_0_ ( .D(n981), .CK(clk), .RN(n1529), .Q(d_ff1_Z[0]) );
DFFRXLTS reg_Z0_Q_reg_1_ ( .D(n980), .CK(clk), .RN(n1528), .Q(d_ff1_Z[1]) );
DFFRXLTS reg_Z0_Q_reg_2_ ( .D(n979), .CK(clk), .RN(n1527), .Q(d_ff1_Z[2]) );
DFFRXLTS reg_Z0_Q_reg_3_ ( .D(n978), .CK(clk), .RN(n1528), .Q(d_ff1_Z[3]) );
DFFRXLTS reg_Z0_Q_reg_4_ ( .D(n977), .CK(clk), .RN(n1532), .Q(d_ff1_Z[4]) );
DFFRXLTS reg_Z0_Q_reg_5_ ( .D(n976), .CK(clk), .RN(n1531), .Q(d_ff1_Z[5]) );
DFFRXLTS reg_Z0_Q_reg_6_ ( .D(n975), .CK(clk), .RN(n1527), .Q(d_ff1_Z[6]) );
DFFRXLTS reg_Z0_Q_reg_7_ ( .D(n974), .CK(clk), .RN(n1532), .Q(d_ff1_Z[7]) );
DFFRXLTS reg_Z0_Q_reg_8_ ( .D(n973), .CK(clk), .RN(n1531), .Q(d_ff1_Z[8]) );
DFFRXLTS reg_Z0_Q_reg_9_ ( .D(n972), .CK(clk), .RN(n1528), .Q(d_ff1_Z[9]) );
DFFRXLTS reg_Z0_Q_reg_10_ ( .D(n971), .CK(clk), .RN(n1528), .Q(d_ff1_Z[10])
);
DFFRXLTS reg_Z0_Q_reg_11_ ( .D(n970), .CK(clk), .RN(n1528), .Q(d_ff1_Z[11])
);
DFFRXLTS reg_Z0_Q_reg_12_ ( .D(n969), .CK(clk), .RN(n1529), .Q(d_ff1_Z[12])
);
DFFRXLTS reg_Z0_Q_reg_13_ ( .D(n968), .CK(clk), .RN(n1527), .Q(d_ff1_Z[13])
);
DFFRXLTS reg_Z0_Q_reg_14_ ( .D(n967), .CK(clk), .RN(n1532), .Q(d_ff1_Z[14])
);
DFFRXLTS reg_Z0_Q_reg_15_ ( .D(n966), .CK(clk), .RN(n1531), .Q(d_ff1_Z[15])
);
DFFRXLTS reg_Z0_Q_reg_16_ ( .D(n965), .CK(clk), .RN(n1526), .Q(d_ff1_Z[16])
);
DFFRXLTS reg_Z0_Q_reg_17_ ( .D(n964), .CK(clk), .RN(n1530), .Q(d_ff1_Z[17])
);
DFFRXLTS reg_Z0_Q_reg_18_ ( .D(n963), .CK(clk), .RN(n1525), .Q(d_ff1_Z[18])
);
DFFRXLTS reg_Z0_Q_reg_19_ ( .D(n962), .CK(clk), .RN(n1515), .Q(d_ff1_Z[19])
);
DFFRXLTS reg_Z0_Q_reg_20_ ( .D(n961), .CK(clk), .RN(n1518), .Q(d_ff1_Z[20])
);
DFFRXLTS reg_Z0_Q_reg_21_ ( .D(n960), .CK(clk), .RN(n1187), .Q(d_ff1_Z[21])
);
DFFRXLTS reg_Z0_Q_reg_22_ ( .D(n959), .CK(clk), .RN(n1188), .Q(d_ff1_Z[22])
);
DFFRXLTS reg_Z0_Q_reg_23_ ( .D(n958), .CK(clk), .RN(n1525), .Q(d_ff1_Z[23])
);
DFFRXLTS reg_Z0_Q_reg_24_ ( .D(n957), .CK(clk), .RN(n1510), .Q(d_ff1_Z[24])
);
DFFRXLTS reg_Z0_Q_reg_25_ ( .D(n956), .CK(clk), .RN(n1519), .Q(d_ff1_Z[25])
);
DFFRXLTS reg_Z0_Q_reg_26_ ( .D(n955), .CK(clk), .RN(n1190), .Q(d_ff1_Z[26])
);
DFFRXLTS reg_Z0_Q_reg_27_ ( .D(n954), .CK(clk), .RN(n1188), .Q(d_ff1_Z[27])
);
DFFRXLTS reg_Z0_Q_reg_28_ ( .D(n953), .CK(clk), .RN(n1525), .Q(d_ff1_Z[28])
);
DFFRXLTS reg_Z0_Q_reg_29_ ( .D(n952), .CK(clk), .RN(n1523), .Q(d_ff1_Z[29])
);
DFFRXLTS reg_Z0_Q_reg_30_ ( .D(n951), .CK(clk), .RN(n1531), .Q(d_ff1_Z[30])
);
DFFRXLTS reg_Z0_Q_reg_31_ ( .D(n950), .CK(clk), .RN(n1526), .Q(d_ff1_Z[31])
);
DFFRXLTS d_ff4_Zn_Q_reg_0_ ( .D(n949), .CK(clk), .RN(n1528), .Q(d_ff_Zn[0])
);
DFFRXLTS d_ff4_Zn_Q_reg_1_ ( .D(n948), .CK(clk), .RN(n1530), .Q(d_ff_Zn[1])
);
DFFRXLTS d_ff4_Zn_Q_reg_2_ ( .D(n947), .CK(clk), .RN(n1526), .Q(d_ff_Zn[2])
);
DFFRXLTS d_ff4_Zn_Q_reg_3_ ( .D(n946), .CK(clk), .RN(n1527), .Q(d_ff_Zn[3])
);
DFFRXLTS d_ff4_Zn_Q_reg_4_ ( .D(n945), .CK(clk), .RN(n1532), .Q(d_ff_Zn[4])
);
DFFRXLTS d_ff4_Zn_Q_reg_5_ ( .D(n944), .CK(clk), .RN(n1531), .Q(d_ff_Zn[5])
);
DFFRXLTS d_ff4_Zn_Q_reg_6_ ( .D(n943), .CK(clk), .RN(n1528), .Q(d_ff_Zn[6])
);
DFFRXLTS d_ff4_Zn_Q_reg_7_ ( .D(n942), .CK(clk), .RN(n1526), .Q(d_ff_Zn[7])
);
DFFRXLTS d_ff4_Zn_Q_reg_8_ ( .D(n941), .CK(clk), .RN(n1529), .Q(d_ff_Zn[8])
);
DFFRXLTS d_ff4_Zn_Q_reg_9_ ( .D(n940), .CK(clk), .RN(n1530), .Q(d_ff_Zn[9])
);
DFFRXLTS d_ff4_Zn_Q_reg_10_ ( .D(n939), .CK(clk), .RN(n1530), .Q(d_ff_Zn[10]) );
DFFRXLTS d_ff4_Zn_Q_reg_11_ ( .D(n938), .CK(clk), .RN(n1528), .Q(d_ff_Zn[11]) );
DFFRXLTS d_ff4_Zn_Q_reg_12_ ( .D(n937), .CK(clk), .RN(n1529), .Q(d_ff_Zn[12]) );
DFFRXLTS d_ff4_Zn_Q_reg_13_ ( .D(n936), .CK(clk), .RN(n1527), .Q(d_ff_Zn[13]) );
DFFRXLTS d_ff4_Zn_Q_reg_14_ ( .D(n935), .CK(clk), .RN(n1532), .Q(d_ff_Zn[14]) );
DFFRXLTS d_ff4_Zn_Q_reg_15_ ( .D(n934), .CK(clk), .RN(n1531), .Q(d_ff_Zn[15]) );
DFFRXLTS d_ff4_Zn_Q_reg_16_ ( .D(n933), .CK(clk), .RN(n1529), .Q(d_ff_Zn[16]) );
DFFRXLTS d_ff4_Zn_Q_reg_17_ ( .D(n932), .CK(clk), .RN(n1528), .Q(d_ff_Zn[17]) );
DFFRXLTS d_ff4_Zn_Q_reg_18_ ( .D(n931), .CK(clk), .RN(n1526), .Q(d_ff_Zn[18]) );
DFFRXLTS d_ff4_Zn_Q_reg_19_ ( .D(n930), .CK(clk), .RN(n1528), .Q(d_ff_Zn[19]) );
DFFRXLTS d_ff4_Zn_Q_reg_20_ ( .D(n929), .CK(clk), .RN(n1527), .Q(d_ff_Zn[20]) );
DFFRXLTS d_ff4_Zn_Q_reg_21_ ( .D(n928), .CK(clk), .RN(n1532), .Q(d_ff_Zn[21]) );
DFFRXLTS d_ff4_Zn_Q_reg_22_ ( .D(n927), .CK(clk), .RN(n1530), .Q(d_ff_Zn[22]) );
DFFRXLTS d_ff4_Zn_Q_reg_23_ ( .D(n926), .CK(clk), .RN(n1527), .Q(d_ff_Zn[23]) );
DFFRXLTS d_ff4_Zn_Q_reg_24_ ( .D(n925), .CK(clk), .RN(n1532), .Q(d_ff_Zn[24]) );
DFFRXLTS d_ff4_Zn_Q_reg_25_ ( .D(n924), .CK(clk), .RN(n1531), .Q(d_ff_Zn[25]) );
DFFRXLTS d_ff4_Zn_Q_reg_26_ ( .D(n923), .CK(clk), .RN(n1526), .Q(d_ff_Zn[26]) );
DFFRXLTS d_ff4_Zn_Q_reg_27_ ( .D(n922), .CK(clk), .RN(n1529), .Q(d_ff_Zn[27]) );
DFFRXLTS d_ff4_Zn_Q_reg_28_ ( .D(n921), .CK(clk), .RN(n1529), .Q(d_ff_Zn[28]) );
DFFRXLTS d_ff4_Zn_Q_reg_29_ ( .D(n920), .CK(clk), .RN(n1526), .Q(d_ff_Zn[29]) );
DFFRXLTS d_ff4_Zn_Q_reg_30_ ( .D(n919), .CK(clk), .RN(n1527), .Q(d_ff_Zn[30]) );
DFFRXLTS d_ff4_Zn_Q_reg_31_ ( .D(n918), .CK(clk), .RN(n1532), .Q(d_ff_Zn[31]) );
DFFRXLTS d_ff4_Yn_Q_reg_0_ ( .D(n917), .CK(clk), .RN(n1531), .QN(n1104) );
DFFRXLTS d_ff4_Yn_Q_reg_1_ ( .D(n916), .CK(clk), .RN(n1530), .QN(n1089) );
DFFRXLTS d_ff4_Yn_Q_reg_2_ ( .D(n915), .CK(clk), .RN(n1532), .QN(n1090) );
DFFRXLTS d_ff4_Yn_Q_reg_3_ ( .D(n914), .CK(clk), .RN(n1531), .QN(n1091) );
DFFRXLTS d_ff4_Yn_Q_reg_4_ ( .D(n913), .CK(clk), .RN(n1529), .QN(n1092) );
DFFRXLTS d_ff4_Yn_Q_reg_5_ ( .D(n912), .CK(clk), .RN(n1526), .QN(n1093) );
DFFRXLTS d_ff4_Yn_Q_reg_6_ ( .D(n911), .CK(clk), .RN(n1526), .QN(n1094) );
DFFRXLTS d_ff4_Yn_Q_reg_7_ ( .D(n910), .CK(clk), .RN(n1530), .QN(n1095) );
DFFRXLTS d_ff4_Yn_Q_reg_8_ ( .D(n909), .CK(clk), .RN(n1530), .QN(n1096) );
DFFRXLTS d_ff4_Yn_Q_reg_9_ ( .D(n908), .CK(clk), .RN(n1532), .QN(n1097) );
DFFRXLTS d_ff4_Yn_Q_reg_10_ ( .D(n907), .CK(clk), .RN(n1531), .QN(n1098) );
DFFRXLTS d_ff4_Yn_Q_reg_11_ ( .D(n906), .CK(clk), .RN(n1528), .QN(n1083) );
DFFRXLTS d_ff4_Yn_Q_reg_12_ ( .D(n905), .CK(clk), .RN(n1530), .QN(n1062) );
DFFRXLTS d_ff4_Yn_Q_reg_13_ ( .D(n904), .CK(clk), .RN(n1530), .QN(n1063) );
DFFRXLTS d_ff4_Yn_Q_reg_14_ ( .D(n903), .CK(clk), .RN(n1188), .QN(n1064) );
DFFRXLTS d_ff4_Yn_Q_reg_15_ ( .D(n902), .CK(clk), .RN(n1525), .QN(n1065) );
DFFRXLTS d_ff4_Yn_Q_reg_16_ ( .D(n901), .CK(clk), .RN(n1189), .QN(n1066) );
DFFRXLTS d_ff4_Yn_Q_reg_17_ ( .D(n900), .CK(clk), .RN(n1516), .QN(n1067) );
DFFRXLTS d_ff4_Yn_Q_reg_18_ ( .D(n899), .CK(clk), .RN(n1531), .QN(n1068) );
DFFRXLTS d_ff4_Yn_Q_reg_19_ ( .D(n898), .CK(clk), .RN(n1533), .QN(n1084) );
DFFRXLTS d_ff4_Yn_Q_reg_20_ ( .D(n897), .CK(clk), .RN(n1510), .QN(n1085) );
DFFRXLTS d_ff4_Yn_Q_reg_21_ ( .D(n896), .CK(clk), .RN(n1525), .QN(n1086) );
DFFRXLTS d_ff4_Yn_Q_reg_22_ ( .D(n895), .CK(clk), .RN(n1529), .QN(n1087) );
DFFRXLTS d_ff4_Yn_Q_reg_23_ ( .D(n894), .CK(clk), .RN(n1523), .QN(n1107) );
DFFRXLTS d_ff4_Yn_Q_reg_24_ ( .D(n893), .CK(clk), .RN(n1511), .QN(n1088) );
DFFRXLTS d_ff4_Yn_Q_reg_25_ ( .D(n892), .CK(clk), .RN(n1512), .QN(n1099) );
DFFRXLTS d_ff4_Yn_Q_reg_26_ ( .D(n891), .CK(clk), .RN(n1530), .QN(n1100) );
DFFRXLTS d_ff4_Yn_Q_reg_27_ ( .D(n890), .CK(clk), .RN(n1529), .QN(n1101) );
DFFRXLTS d_ff4_Yn_Q_reg_28_ ( .D(n889), .CK(clk), .RN(n1526), .QN(n1108) );
DFFRXLTS d_ff4_Yn_Q_reg_29_ ( .D(n888), .CK(clk), .RN(n1526), .QN(n1102) );
DFFRXLTS d_ff4_Yn_Q_reg_30_ ( .D(n887), .CK(clk), .RN(n1527), .QN(n1103) );
DFFRXLTS d_ff4_Xn_Q_reg_12_ ( .D(n873), .CK(clk), .RN(n1530), .QN(n1109) );
DFFRXLTS d_ff4_Xn_Q_reg_13_ ( .D(n872), .CK(clk), .RN(n1522), .QN(n1110) );
DFFRXLTS d_ff4_Xn_Q_reg_14_ ( .D(n871), .CK(clk), .RN(n1527), .QN(n1111) );
DFFRXLTS d_ff4_Xn_Q_reg_15_ ( .D(n870), .CK(clk), .RN(n1521), .QN(n1105) );
DFFRXLTS d_ff4_Xn_Q_reg_16_ ( .D(n869), .CK(clk), .RN(n1514), .QN(n1112) );
DFFRXLTS d_ff4_Xn_Q_reg_17_ ( .D(n868), .CK(clk), .RN(n1515), .QN(n1113) );
DFFRXLTS d_ff4_Xn_Q_reg_18_ ( .D(n867), .CK(clk), .RN(n1517), .QN(n1106) );
DFFRXLTS reg_LUT_Q_reg_0_ ( .D(n821), .CK(clk), .RN(n1516), .Q(
d_ff3_LUT_out[0]) );
DFFRXLTS reg_LUT_Q_reg_1_ ( .D(n820), .CK(clk), .RN(n1522), .Q(
d_ff3_LUT_out[1]) );
DFFRXLTS reg_LUT_Q_reg_2_ ( .D(n819), .CK(clk), .RN(n1515), .Q(
d_ff3_LUT_out[2]) );
DFFRXLTS reg_LUT_Q_reg_3_ ( .D(n818), .CK(clk), .RN(n1517), .Q(
d_ff3_LUT_out[3]) );
DFFRXLTS reg_LUT_Q_reg_4_ ( .D(n817), .CK(clk), .RN(n1524), .Q(
d_ff3_LUT_out[4]) );
DFFRXLTS reg_LUT_Q_reg_6_ ( .D(n815), .CK(clk), .RN(n1521), .Q(
d_ff3_LUT_out[6]) );
DFFRXLTS reg_LUT_Q_reg_8_ ( .D(n813), .CK(clk), .RN(n1187), .Q(
d_ff3_LUT_out[8]) );
DFFRXLTS reg_LUT_Q_reg_9_ ( .D(n812), .CK(clk), .RN(n1514), .QN(n1178) );
DFFRXLTS reg_LUT_Q_reg_10_ ( .D(n811), .CK(clk), .RN(n1187), .Q(
d_ff3_LUT_out[10]) );
DFFRXLTS reg_LUT_Q_reg_12_ ( .D(n810), .CK(clk), .RN(n1515), .QN(n1180) );
DFFRXLTS reg_LUT_Q_reg_13_ ( .D(n809), .CK(clk), .RN(n1517), .Q(
d_ff3_LUT_out[13]) );
DFFRXLTS reg_LUT_Q_reg_21_ ( .D(n806), .CK(clk), .RN(n1516), .QN(n1181) );
DFFRXLTS reg_LUT_Q_reg_23_ ( .D(n805), .CK(clk), .RN(n1522), .Q(
d_ff3_LUT_out[23]) );
DFFRXLTS reg_LUT_Q_reg_24_ ( .D(n804), .CK(clk), .RN(n1523), .Q(
d_ff3_LUT_out[24]) );
DFFRXLTS reg_LUT_Q_reg_25_ ( .D(n803), .CK(clk), .RN(n1520), .Q(
d_ff3_LUT_out[25]) );
DFFRXLTS reg_LUT_Q_reg_26_ ( .D(n802), .CK(clk), .RN(n1519), .Q(
d_ff3_LUT_out[26]) );
DFFRXLTS reg_shift_y_Q_reg_23_ ( .D(n713), .CK(clk), .RN(n1518), .Q(
d_ff3_sh_y_out[23]) );
DFFRXLTS reg_shift_y_Q_reg_24_ ( .D(n712), .CK(clk), .RN(n1190), .Q(
d_ff3_sh_y_out[24]) );
DFFRXLTS reg_shift_y_Q_reg_25_ ( .D(n711), .CK(clk), .RN(n1518), .Q(
d_ff3_sh_y_out[25]) );
DFFRXLTS reg_shift_y_Q_reg_26_ ( .D(n710), .CK(clk), .RN(n1519), .Q(
d_ff3_sh_y_out[26]) );
DFFRXLTS reg_shift_y_Q_reg_27_ ( .D(n709), .CK(clk), .RN(n1520), .Q(
d_ff3_sh_y_out[27]) );
DFFRXLTS reg_shift_y_Q_reg_28_ ( .D(n708), .CK(clk), .RN(n1516), .Q(
d_ff3_sh_y_out[28]) );
DFFRXLTS reg_shift_y_Q_reg_29_ ( .D(n707), .CK(clk), .RN(n1522), .Q(
d_ff3_sh_y_out[29]) );
DFFRXLTS reg_shift_y_Q_reg_30_ ( .D(n706), .CK(clk), .RN(n1523), .Q(
d_ff3_sh_y_out[30]) );
DFFRXLTS reg_shift_x_Q_reg_23_ ( .D(n649), .CK(clk), .RN(n1520), .Q(
d_ff3_sh_x_out[23]) );
DFFRXLTS reg_shift_x_Q_reg_24_ ( .D(n648), .CK(clk), .RN(n1519), .Q(
d_ff3_sh_x_out[24]) );
DFFRXLTS reg_shift_x_Q_reg_25_ ( .D(n647), .CK(clk), .RN(n1188), .Q(
d_ff3_sh_x_out[25]) );
DFFRXLTS reg_shift_x_Q_reg_26_ ( .D(n646), .CK(clk), .RN(n1518), .Q(
d_ff3_sh_x_out[26]) );
DFFRXLTS reg_shift_x_Q_reg_27_ ( .D(n645), .CK(clk), .RN(n1518), .Q(
d_ff3_sh_x_out[27]) );
DFFRXLTS reg_shift_x_Q_reg_28_ ( .D(n644), .CK(clk), .RN(n1188), .Q(
d_ff3_sh_x_out[28]) );
DFFRXLTS reg_shift_x_Q_reg_29_ ( .D(n643), .CK(clk), .RN(n1516), .QN(n1179)
);
DFFRXLTS reg_shift_x_Q_reg_30_ ( .D(n642), .CK(clk), .RN(n1522), .Q(
d_ff3_sh_x_out[30]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_1_ ( .D(n799), .CK(clk), .RN(n1516), .Q(
d_ff2_Z[1]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_2_ ( .D(n798), .CK(clk), .RN(n1522), .Q(
d_ff2_Z[2]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_3_ ( .D(n797), .CK(clk), .RN(n1523), .Q(
d_ff2_Z[3]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_4_ ( .D(n796), .CK(clk), .RN(n1520), .Q(
d_ff2_Z[4]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_5_ ( .D(n795), .CK(clk), .RN(n1519), .Q(
d_ff2_Z[5]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_6_ ( .D(n794), .CK(clk), .RN(n1518), .Q(
d_ff2_Z[6]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_7_ ( .D(n793), .CK(clk), .RN(n1188), .Q(
d_ff2_Z[7]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_8_ ( .D(n792), .CK(clk), .RN(n1516), .Q(
d_ff2_Z[8]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_9_ ( .D(n791), .CK(clk), .RN(n1522), .Q(
d_ff2_Z[9]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_10_ ( .D(n790), .CK(clk), .RN(n1523), .Q(
d_ff2_Z[10]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_11_ ( .D(n789), .CK(clk), .RN(n1520), .Q(
d_ff2_Z[11]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_12_ ( .D(n788), .CK(clk), .RN(n1519), .Q(
d_ff2_Z[12]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_19_ ( .D(n781), .CK(clk), .RN(n1522), .Q(
d_ff2_Z[19]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_20_ ( .D(n780), .CK(clk), .RN(n1523), .Q(
d_ff2_Z[20]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_21_ ( .D(n779), .CK(clk), .RN(n1520), .Q(
d_ff2_Z[21]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_22_ ( .D(n778), .CK(clk), .RN(n1519), .Q(
d_ff2_Z[22]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_23_ ( .D(n777), .CK(clk), .RN(n1518), .Q(
d_ff2_Z[23]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_25_ ( .D(n775), .CK(clk), .RN(n1514), .Q(
d_ff2_Z[25]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_26_ ( .D(n774), .CK(clk), .RN(n1515), .Q(
d_ff2_Z[26]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_27_ ( .D(n773), .CK(clk), .RN(n1517), .Q(
d_ff2_Z[27]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_28_ ( .D(n772), .CK(clk), .RN(n1524), .Q(
d_ff2_Z[28]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_29_ ( .D(n771), .CK(clk), .RN(n1521), .Q(
d_ff2_Z[29]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_30_ ( .D(n770), .CK(clk), .RN(n1514), .Q(
d_ff2_Z[30]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_0_ ( .D(n767), .CK(clk), .RN(n1515), .QN(
n1058) );
DFFRXLTS reg_shift_y_Q_reg_0_ ( .D(n766), .CK(clk), .RN(n1521), .Q(
d_ff3_sh_y_out[0]) );
DFFRXLTS reg_shift_y_Q_reg_1_ ( .D(n764), .CK(clk), .RN(n1524), .Q(
d_ff3_sh_y_out[1]) );
DFFRXLTS reg_shift_y_Q_reg_2_ ( .D(n762), .CK(clk), .RN(n1519), .Q(
d_ff3_sh_y_out[2]) );
DFFRXLTS reg_shift_y_Q_reg_3_ ( .D(n760), .CK(clk), .RN(n1520), .Q(
d_ff3_sh_y_out[3]) );
DFFRXLTS reg_shift_y_Q_reg_4_ ( .D(n758), .CK(clk), .RN(n1523), .Q(
d_ff3_sh_y_out[4]) );
DFFRXLTS reg_shift_y_Q_reg_5_ ( .D(n756), .CK(clk), .RN(n1516), .Q(
d_ff3_sh_y_out[5]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_6_ ( .D(n755), .CK(clk), .RN(n1522), .QN(
n1059) );
DFFRXLTS reg_shift_y_Q_reg_6_ ( .D(n754), .CK(clk), .RN(n1188), .Q(
d_ff3_sh_y_out[6]) );
DFFRXLTS reg_shift_y_Q_reg_7_ ( .D(n752), .CK(clk), .RN(n1518), .Q(
d_ff3_sh_y_out[7]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_8_ ( .D(n751), .CK(clk), .RN(n1524), .QN(
n1060) );
DFFRXLTS reg_shift_y_Q_reg_8_ ( .D(n750), .CK(clk), .RN(n1517), .Q(
d_ff3_sh_y_out[8]) );
DFFRXLTS reg_shift_y_Q_reg_9_ ( .D(n748), .CK(clk), .RN(n1515), .Q(
d_ff3_sh_y_out[9]) );
DFFRXLTS reg_shift_y_Q_reg_10_ ( .D(n746), .CK(clk), .RN(n1514), .Q(
d_ff3_sh_y_out[10]) );
DFFRXLTS reg_shift_y_Q_reg_11_ ( .D(n744), .CK(clk), .RN(n1521), .Q(
d_ff3_sh_y_out[11]) );
DFFRXLTS reg_shift_y_Q_reg_12_ ( .D(n742), .CK(clk), .RN(n1524), .Q(
d_ff3_sh_y_out[12]) );
DFFRXLTS reg_shift_y_Q_reg_13_ ( .D(n740), .CK(clk), .RN(n1517), .Q(
d_ff3_sh_y_out[13]) );
DFFRXLTS reg_shift_y_Q_reg_14_ ( .D(n738), .CK(clk), .RN(n1517), .Q(
d_ff3_sh_y_out[14]) );
DFFRXLTS reg_shift_y_Q_reg_15_ ( .D(n736), .CK(clk), .RN(n1515), .Q(
d_ff3_sh_y_out[15]) );
DFFRXLTS reg_shift_y_Q_reg_16_ ( .D(n734), .CK(clk), .RN(n1187), .Q(
d_ff3_sh_y_out[16]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_17_ ( .D(n733), .CK(clk), .RN(n1524),
.QN(n1073) );
DFFRXLTS reg_shift_y_Q_reg_17_ ( .D(n732), .CK(clk), .RN(n1514), .Q(
d_ff3_sh_y_out[17]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_18_ ( .D(n731), .CK(clk), .RN(n1521),
.QN(n1072) );
DFFRXLTS reg_shift_y_Q_reg_18_ ( .D(n730), .CK(clk), .RN(n1187), .Q(
d_ff3_sh_y_out[18]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_19_ ( .D(n729), .CK(clk), .RN(n1514),
.QN(n1061) );
DFFRXLTS reg_shift_y_Q_reg_19_ ( .D(n728), .CK(clk), .RN(n1514), .Q(
d_ff3_sh_y_out[19]) );
DFFRXLTS reg_shift_y_Q_reg_20_ ( .D(n726), .CK(clk), .RN(n1512), .Q(
d_ff3_sh_y_out[20]) );
DFFRXLTS reg_shift_y_Q_reg_21_ ( .D(n724), .CK(clk), .RN(n1510), .Q(
d_ff3_sh_y_out[21]) );
DFFRXLTS reg_shift_y_Q_reg_22_ ( .D(n722), .CK(clk), .RN(n1512), .Q(
d_ff3_sh_y_out[22]) );
DFFRXLTS reg_shift_y_Q_reg_31_ ( .D(n704), .CK(clk), .RN(n1512), .Q(
d_ff3_sh_y_out[31]) );
DFFRXLTS reg_shift_x_Q_reg_0_ ( .D(n702), .CK(clk), .RN(n1510), .Q(
d_ff3_sh_x_out[0]) );
DFFRXLTS reg_shift_x_Q_reg_1_ ( .D(n700), .CK(clk), .RN(n1512), .Q(
d_ff3_sh_x_out[1]) );
DFFRXLTS reg_shift_x_Q_reg_2_ ( .D(n698), .CK(clk), .RN(n1510), .Q(
d_ff3_sh_x_out[2]) );
DFFRXLTS reg_shift_x_Q_reg_3_ ( .D(n696), .CK(clk), .RN(n1512), .Q(
d_ff3_sh_x_out[3]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_4_ ( .D(n695), .CK(clk), .RN(n1511), .QN(
n1077) );
DFFRXLTS reg_shift_x_Q_reg_4_ ( .D(n694), .CK(clk), .RN(n1509), .Q(
d_ff3_sh_x_out[4]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_5_ ( .D(n693), .CK(clk), .RN(n1533), .QN(
n1074) );
DFFRXLTS reg_shift_x_Q_reg_5_ ( .D(n692), .CK(clk), .RN(n1533), .Q(
d_ff3_sh_x_out[5]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_6_ ( .D(n691), .CK(clk), .RN(n1509), .QN(
n1075) );
DFFRXLTS reg_shift_x_Q_reg_6_ ( .D(n690), .CK(clk), .RN(n1511), .Q(
d_ff3_sh_x_out[6]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_7_ ( .D(n689), .CK(clk), .RN(n1511), .QN(
n1076) );
DFFRXLTS reg_shift_x_Q_reg_7_ ( .D(n688), .CK(clk), .RN(n1509), .Q(
d_ff3_sh_x_out[7]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_8_ ( .D(n687), .CK(clk), .RN(n1533), .QN(
n1078) );
DFFRXLTS reg_shift_x_Q_reg_8_ ( .D(n686), .CK(clk), .RN(n1511), .Q(
d_ff3_sh_x_out[8]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_9_ ( .D(n685), .CK(clk), .RN(n1509), .QN(
n1079) );
DFFRXLTS reg_shift_x_Q_reg_9_ ( .D(n684), .CK(clk), .RN(n1533), .Q(
d_ff3_sh_x_out[9]) );
DFFRXLTS reg_shift_x_Q_reg_10_ ( .D(n682), .CK(clk), .RN(n1510), .Q(
d_ff3_sh_x_out[10]) );
DFFRXLTS reg_shift_x_Q_reg_11_ ( .D(n680), .CK(clk), .RN(n1512), .Q(
d_ff3_sh_x_out[11]) );
DFFRXLTS reg_shift_x_Q_reg_12_ ( .D(n678), .CK(clk), .RN(n1512), .Q(
d_ff3_sh_x_out[12]) );
DFFRXLTS reg_shift_x_Q_reg_13_ ( .D(n676), .CK(clk), .RN(n1510), .Q(
d_ff3_sh_x_out[13]) );
DFFRXLTS reg_shift_x_Q_reg_14_ ( .D(n674), .CK(clk), .RN(n1512), .Q(
d_ff3_sh_x_out[14]) );
DFFRXLTS reg_shift_x_Q_reg_15_ ( .D(n672), .CK(clk), .RN(n1510), .Q(
d_ff3_sh_x_out[15]) );
DFFRXLTS reg_shift_x_Q_reg_16_ ( .D(n670), .CK(clk), .RN(n1509), .Q(
d_ff3_sh_x_out[16]) );
DFFRXLTS reg_shift_x_Q_reg_17_ ( .D(n668), .CK(clk), .RN(n1189), .Q(
d_ff3_sh_x_out[17]) );
DFFRXLTS reg_shift_x_Q_reg_18_ ( .D(n666), .CK(clk), .RN(n281), .Q(
d_ff3_sh_x_out[18]) );
DFFRXLTS reg_shift_x_Q_reg_19_ ( .D(n664), .CK(clk), .RN(n281), .Q(
d_ff3_sh_x_out[19]) );
DFFRXLTS reg_shift_x_Q_reg_20_ ( .D(n662), .CK(clk), .RN(n1189), .Q(
d_ff3_sh_x_out[20]) );
DFFRXLTS reg_shift_x_Q_reg_21_ ( .D(n660), .CK(clk), .RN(n1511), .Q(
d_ff3_sh_x_out[21]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_22_ ( .D(n659), .CK(clk), .RN(n1511),
.QN(n1080) );
DFFRXLTS reg_shift_x_Q_reg_22_ ( .D(n658), .CK(clk), .RN(n1509), .Q(
d_ff3_sh_x_out[22]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_23_ ( .D(n657), .CK(clk), .RN(n1509),
.QN(n1069) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_25_ ( .D(n655), .CK(clk), .RN(n1511),
.QN(n1070) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_26_ ( .D(n654), .CK(clk), .RN(n1533),
.QN(n1071) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_30_ ( .D(n650), .CK(clk), .RN(n1533),
.QN(n1082) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_31_ ( .D(n641), .CK(clk), .RN(n1511),
.QN(n1081) );
DFFRXLTS reg_shift_x_Q_reg_31_ ( .D(n640), .CK(clk), .RN(n1509), .Q(
d_ff3_sh_x_out[31]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_28_ ( .D(n716), .CK(clk), .RN(n1513), .Q(
d_ff2_Y[28]), .QN(n1505) );
DFFRX1TS reg_LUT_Q_reg_15_ ( .D(n808), .CK(clk), .RN(n1187), .QN(n1503) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_23_ ( .D(n721), .CK(clk), .RN(n1513), .Q(
d_ff2_Y[23]), .QN(n1502) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_24_ ( .D(n656), .CK(clk), .RN(n1511), .Q(
d_ff2_X[24]), .QN(n1500) );
DFFRX2TS ITER_CONT_temp_reg_1_ ( .D(n988), .CK(clk), .RN(n1187), .Q(
cont_iter_out[1]), .QN(n1499) );
DFFRX1TS inst_CORDIC_FSM_v3_state_reg_reg_6_ ( .D(
inst_CORDIC_FSM_v3_state_next[6]), .CK(clk), .RN(n1519), .Q(
inst_CORDIC_FSM_v3_state_reg[6]), .QN(n1498) );
DFFRX2TS ITER_CONT_temp_reg_3_ ( .D(n986), .CK(clk), .RN(n1189), .Q(
cont_iter_out[3]), .QN(n1496) );
DFFRX1TS VAR_CONT_temp_reg_1_ ( .D(n990), .CK(clk), .RN(n1520), .Q(
cont_var_out[1]), .QN(n1494) );
DFFRX2TS VAR_CONT_temp_reg_0_ ( .D(n985), .CK(clk), .RN(n1532), .Q(
cont_var_out[0]), .QN(n1493) );
DFFRXLTS d_ff5_data_out_Q_reg_0_ ( .D(n853), .CK(clk), .RN(n1531), .Q(
data_output[0]) );
DFFRXLTS d_ff5_data_out_Q_reg_1_ ( .D(n852), .CK(clk), .RN(n1532), .Q(
data_output[1]) );
DFFRXLTS d_ff5_data_out_Q_reg_2_ ( .D(n851), .CK(clk), .RN(n1530), .Q(
data_output[2]) );
DFFRXLTS d_ff5_data_out_Q_reg_3_ ( .D(n850), .CK(clk), .RN(n1516), .Q(
data_output[3]) );
DFFRXLTS d_ff5_data_out_Q_reg_4_ ( .D(n849), .CK(clk), .RN(n1518), .Q(
data_output[4]) );
DFFRXLTS d_ff5_data_out_Q_reg_5_ ( .D(n848), .CK(clk), .RN(n1525), .Q(
data_output[5]) );
DFFRXLTS d_ff5_data_out_Q_reg_6_ ( .D(n847), .CK(clk), .RN(n1519), .Q(
data_output[6]) );
DFFRXLTS d_ff5_data_out_Q_reg_7_ ( .D(n846), .CK(clk), .RN(n1513), .Q(
data_output[7]) );
DFFRXLTS d_ff5_data_out_Q_reg_8_ ( .D(n845), .CK(clk), .RN(n1520), .Q(
data_output[8]) );
DFFRXLTS d_ff5_data_out_Q_reg_9_ ( .D(n844), .CK(clk), .RN(n1189), .Q(
data_output[9]) );
DFFRXLTS d_ff5_data_out_Q_reg_10_ ( .D(n843), .CK(clk), .RN(n1525), .Q(
data_output[10]) );
DFFRXLTS d_ff5_data_out_Q_reg_11_ ( .D(n842), .CK(clk), .RN(n1189), .Q(
data_output[11]) );
DFFRXLTS d_ff5_data_out_Q_reg_12_ ( .D(n841), .CK(clk), .RN(n1513), .Q(
data_output[12]) );
DFFRXLTS d_ff5_data_out_Q_reg_13_ ( .D(n840), .CK(clk), .RN(n1516), .Q(
data_output[13]) );
DFFRXLTS d_ff5_data_out_Q_reg_14_ ( .D(n839), .CK(clk), .RN(n1531), .Q(
data_output[14]) );
DFFRXLTS d_ff5_data_out_Q_reg_15_ ( .D(n838), .CK(clk), .RN(n1524), .Q(
data_output[15]) );
DFFRXLTS d_ff5_data_out_Q_reg_16_ ( .D(n837), .CK(clk), .RN(n1517), .Q(
data_output[16]) );
DFFRXLTS d_ff5_data_out_Q_reg_17_ ( .D(n836), .CK(clk), .RN(n1515), .Q(
data_output[17]) );
DFFRXLTS d_ff5_data_out_Q_reg_18_ ( .D(n835), .CK(clk), .RN(n1514), .Q(
data_output[18]) );
DFFRXLTS d_ff5_data_out_Q_reg_19_ ( .D(n834), .CK(clk), .RN(n1521), .Q(
data_output[19]) );
DFFRXLTS d_ff5_data_out_Q_reg_20_ ( .D(n833), .CK(clk), .RN(n1524), .Q(
data_output[20]) );
DFFRXLTS d_ff5_data_out_Q_reg_21_ ( .D(n832), .CK(clk), .RN(n1520), .Q(
data_output[21]) );
DFFRXLTS d_ff5_data_out_Q_reg_22_ ( .D(n831), .CK(clk), .RN(n1522), .Q(
data_output[22]) );
DFFRXLTS d_ff5_data_out_Q_reg_23_ ( .D(n830), .CK(clk), .RN(n1516), .Q(
data_output[23]) );
DFFRXLTS d_ff5_data_out_Q_reg_24_ ( .D(n829), .CK(clk), .RN(n1523), .Q(
data_output[24]) );
DFFRXLTS d_ff5_data_out_Q_reg_25_ ( .D(n828), .CK(clk), .RN(n1188), .Q(
data_output[25]) );
DFFRXLTS d_ff5_data_out_Q_reg_26_ ( .D(n827), .CK(clk), .RN(n1188), .Q(
data_output[26]) );
DFFRXLTS d_ff5_data_out_Q_reg_27_ ( .D(n826), .CK(clk), .RN(n1188), .Q(
data_output[27]) );
DFFRXLTS d_ff5_data_out_Q_reg_28_ ( .D(n825), .CK(clk), .RN(n1518), .Q(
data_output[28]) );
DFFRXLTS d_ff5_data_out_Q_reg_29_ ( .D(n824), .CK(clk), .RN(n1519), .Q(
data_output[29]) );
DFFRXLTS d_ff5_data_out_Q_reg_30_ ( .D(n823), .CK(clk), .RN(n1522), .Q(
data_output[30]) );
DFFRXLTS d_ff5_data_out_Q_reg_31_ ( .D(n822), .CK(clk), .RN(n1516), .Q(
data_output[31]) );
DFFRX1TS reg_sign_Q_reg_0_ ( .D(n768), .CK(clk), .RN(n1514), .Q(
d_ff3_sign_out) );
DFFSX2TS inst_CORDIC_FSM_v3_state_reg_reg_0_ ( .D(
inst_CORDIC_FSM_v3_state_next[0]), .CK(clk), .SN(n1189), .Q(
inst_CORDIC_FSM_v3_state_reg[0]) );
DFFRX2TS inst_CORDIC_FSM_v3_state_reg_reg_5_ ( .D(
inst_CORDIC_FSM_v3_state_next[5]), .CK(clk), .RN(n1522), .Q(
inst_CORDIC_FSM_v3_state_reg[5]) );
DFFRX1TS inst_CORDIC_FSM_v3_state_reg_reg_3_ ( .D(n1508), .CK(clk), .RN(
n1531), .Q(inst_CORDIC_FSM_v3_state_reg[3]) );
DFFRX1TS inst_CORDIC_FSM_v3_state_reg_reg_1_ ( .D(
inst_CORDIC_FSM_v3_state_next[1]), .CK(clk), .RN(n1530), .Q(
inst_CORDIC_FSM_v3_state_reg[1]) );
DFFRX1TS inst_CORDIC_FSM_v3_state_reg_reg_4_ ( .D(
inst_CORDIC_FSM_v3_state_next[4]), .CK(clk), .RN(n1522), .Q(
inst_CORDIC_FSM_v3_state_reg[4]) );
DFFRX1TS inst_CORDIC_FSM_v3_state_reg_reg_2_ ( .D(
inst_CORDIC_FSM_v3_state_next[2]), .CK(clk), .RN(n1530), .Q(
inst_CORDIC_FSM_v3_state_reg[2]) );
DFFRX2TS ITER_CONT_temp_reg_2_ ( .D(n987), .CK(clk), .RN(n1525), .Q(n1506),
.QN(intadd_365_B_1_) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_28_ ( .D(n652), .CK(clk), .RN(n1533), .Q(
d_ff2_X[28]), .QN(n1501) );
DFFRX2TS reg_val_muxY_2stage_Q_reg_27_ ( .D(n717), .CK(clk), .RN(n1513), .Q(
d_ff2_Y[27]) );
DFFRX2TS reg_val_muxX_2stage_Q_reg_27_ ( .D(n653), .CK(clk), .RN(n1509), .Q(
d_ff2_X[27]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_29_ ( .D(n715), .CK(clk), .RN(n1510), .Q(
d_ff2_Y[29]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_29_ ( .D(n651), .CK(clk), .RN(n1533), .Q(
d_ff2_X[29]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_26_ ( .D(n718), .CK(clk), .RN(n1513), .Q(
d_ff2_Y[26]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_25_ ( .D(n719), .CK(clk), .RN(n1513), .Q(
d_ff2_Y[25]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_24_ ( .D(n720), .CK(clk), .RN(n1513), .Q(
d_ff2_Y[24]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_31_ ( .D(n769), .CK(clk), .RN(n1521), .Q(
d_ff2_Z[31]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_30_ ( .D(n714), .CK(clk), .RN(n1512), .Q(
d_ff2_Y[30]) );
DFFRX1TS reg_LUT_Q_reg_27_ ( .D(n801), .CK(clk), .RN(n1520), .Q(
d_ff3_LUT_out[27]) );
DFFRX1TS d_ff4_Xn_Q_reg_26_ ( .D(n859), .CK(clk), .RN(n1518), .Q(d_ff_Xn[26]) );
DFFRX1TS d_ff4_Xn_Q_reg_25_ ( .D(n860), .CK(clk), .RN(n1519), .Q(d_ff_Xn[25]) );
DFFRX1TS d_ff4_Xn_Q_reg_10_ ( .D(n875), .CK(clk), .RN(n1523), .Q(d_ff_Xn[10]) );
DFFRX1TS d_ff4_Xn_Q_reg_7_ ( .D(n878), .CK(clk), .RN(n1518), .Q(d_ff_Xn[7])
);
DFFRX1TS d_ff4_Xn_Q_reg_6_ ( .D(n879), .CK(clk), .RN(n1525), .Q(d_ff_Xn[6])
);
DFFRX1TS d_ff4_Xn_Q_reg_5_ ( .D(n880), .CK(clk), .RN(n1189), .Q(d_ff_Xn[5])
);
DFFRX1TS d_ff4_Xn_Q_reg_3_ ( .D(n882), .CK(clk), .RN(n1190), .Q(d_ff_Xn[3])
);
DFFRX1TS d_ff4_Xn_Q_reg_2_ ( .D(n883), .CK(clk), .RN(n1527), .Q(d_ff_Xn[2])
);
DFFRX1TS d_ff4_Xn_Q_reg_1_ ( .D(n884), .CK(clk), .RN(n1529), .Q(d_ff_Xn[1])
);
DFFRX1TS d_ff4_Xn_Q_reg_28_ ( .D(n857), .CK(clk), .RN(n1516), .Q(d_ff_Xn[28]) );
DFFRX1TS d_ff4_Xn_Q_reg_24_ ( .D(n861), .CK(clk), .RN(n1520), .Q(d_ff_Xn[24]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_22_ ( .D(n723), .CK(clk), .RN(n1513), .Q(
d_ff2_Y[22]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_21_ ( .D(n725), .CK(clk), .RN(n1513), .Q(
d_ff2_Y[21]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_20_ ( .D(n727), .CK(clk), .RN(n1513), .Q(
d_ff2_Y[20]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_15_ ( .D(n737), .CK(clk), .RN(n1524), .Q(
d_ff2_Y[15]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_7_ ( .D(n753), .CK(clk), .RN(n1190), .Q(
d_ff2_Y[7]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_5_ ( .D(n757), .CK(clk), .RN(n1518), .Q(
d_ff2_Y[5]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_4_ ( .D(n759), .CK(clk), .RN(n1519), .Q(
d_ff2_Y[4]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_3_ ( .D(n761), .CK(clk), .RN(n1520), .Q(
d_ff2_Y[3]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_2_ ( .D(n763), .CK(clk), .RN(n1522), .Q(
d_ff2_Y[2]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_1_ ( .D(n765), .CK(clk), .RN(n1524), .Q(
d_ff2_Y[1]) );
DFFRX1TS d_ff4_Xn_Q_reg_11_ ( .D(n874), .CK(clk), .RN(n1189), .Q(d_ff_Xn[11]) );
DFFRX1TS d_ff4_Xn_Q_reg_9_ ( .D(n876), .CK(clk), .RN(n1187), .Q(d_ff_Xn[9])
);
DFFRX1TS d_ff4_Xn_Q_reg_8_ ( .D(n877), .CK(clk), .RN(n1531), .Q(d_ff_Xn[8])
);
DFFRX1TS d_ff4_Xn_Q_reg_4_ ( .D(n881), .CK(clk), .RN(n1520), .Q(d_ff_Xn[4])
);
DFFRX1TS d_ff4_Xn_Q_reg_0_ ( .D(n885), .CK(clk), .RN(n1529), .Q(d_ff_Xn[0])
);
DFFRX1TS d_ff4_Yn_Q_reg_31_ ( .D(n886), .CK(clk), .RN(n1529), .Q(d_ff_Yn_31_) );
DFFRX1TS d_ff4_Xn_Q_reg_31_ ( .D(n854), .CK(clk), .RN(n1523), .Q(d_ff_Xn[31]) );
DFFRX1TS reg_LUT_Q_reg_7_ ( .D(n814), .CK(clk), .RN(n1514), .Q(
d_ff3_LUT_out[7]) );
DFFRX1TS reg_LUT_Q_reg_5_ ( .D(n816), .CK(clk), .RN(n1521), .Q(
d_ff3_LUT_out[5]) );
DFFRX1TS reg_LUT_Q_reg_19_ ( .D(n807), .CK(clk), .RN(n1523), .Q(
d_ff3_LUT_out[19]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_16_ ( .D(n671), .CK(clk), .RN(n1509), .Q(
d_ff2_X[16]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_17_ ( .D(n669), .CK(clk), .RN(n1533), .Q(
d_ff2_X[17]) );
DFFRX1TS reg_region_flag_Q_reg_1_ ( .D(n982), .CK(clk), .RN(n1532), .Q(
d_ff1_shift_region_flag_out[1]), .QN(n1497) );
DFFRX1TS d_ff4_Xn_Q_reg_19_ ( .D(n866), .CK(clk), .RN(n1517), .Q(d_ff_Xn[19]) );
DFFRX1TS d_ff4_Xn_Q_reg_20_ ( .D(n865), .CK(clk), .RN(n1515), .Q(d_ff_Xn[20]) );
DFFRX1TS d_ff4_Xn_Q_reg_27_ ( .D(n858), .CK(clk), .RN(n1188), .Q(d_ff_Xn[27]) );
DFFRX1TS d_ff4_Xn_Q_reg_29_ ( .D(n856), .CK(clk), .RN(n1518), .Q(d_ff_Xn[29]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_9_ ( .D(n749), .CK(clk), .RN(n1521), .Q(
d_ff2_Y[9]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_10_ ( .D(n747), .CK(clk), .RN(n1524), .Q(
d_ff2_Y[10]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_11_ ( .D(n745), .CK(clk), .RN(n1517), .Q(
d_ff2_Y[11]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_12_ ( .D(n743), .CK(clk), .RN(n1515), .Q(
d_ff2_Y[12]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_13_ ( .D(n741), .CK(clk), .RN(n1187), .Q(
d_ff2_Y[13]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_14_ ( .D(n739), .CK(clk), .RN(n1517), .Q(
d_ff2_Y[14]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_16_ ( .D(n735), .CK(clk), .RN(n1515), .Q(
d_ff2_Y[16]) );
DFFRX1TS d_ff4_Xn_Q_reg_21_ ( .D(n864), .CK(clk), .RN(n1522), .Q(d_ff_Xn[21]) );
DFFRX1TS d_ff4_Xn_Q_reg_22_ ( .D(n863), .CK(clk), .RN(n1516), .Q(d_ff_Xn[22]) );
DFFRX1TS d_ff4_Xn_Q_reg_23_ ( .D(n862), .CK(clk), .RN(n1523), .Q(d_ff_Xn[23]) );
DFFRX1TS d_ff4_Xn_Q_reg_30_ ( .D(n855), .CK(clk), .RN(n1519), .Q(d_ff_Xn[30]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_31_ ( .D(n705), .CK(clk), .RN(n1510), .Q(
d_ff2_Y[31]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_1_ ( .D(n701), .CK(clk), .RN(n1512), .Q(
d_ff2_X[1]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_2_ ( .D(n699), .CK(clk), .RN(n1510), .Q(
d_ff2_X[2]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_3_ ( .D(n697), .CK(clk), .RN(n1512), .Q(
d_ff2_X[3]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_10_ ( .D(n683), .CK(clk), .RN(n1512), .Q(
d_ff2_X[10]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_12_ ( .D(n679), .CK(clk), .RN(n1510), .Q(
d_ff2_X[12]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_13_ ( .D(n677), .CK(clk), .RN(n1512), .Q(
d_ff2_X[13]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_14_ ( .D(n675), .CK(clk), .RN(n1510), .Q(
d_ff2_X[14]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_19_ ( .D(n665), .CK(clk), .RN(n281), .Q(
d_ff2_X[19]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_20_ ( .D(n663), .CK(clk), .RN(n281), .Q(
d_ff2_X[20]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_0_ ( .D(n703), .CK(clk), .RN(n1510), .Q(
d_ff2_X[0]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_11_ ( .D(n681), .CK(clk), .RN(n1512), .Q(
d_ff2_X[11]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_15_ ( .D(n673), .CK(clk), .RN(n1510), .Q(
d_ff2_X[15]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_18_ ( .D(n667), .CK(clk), .RN(n281), .Q(
d_ff2_X[18]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_21_ ( .D(n661), .CK(clk), .RN(n1189), .Q(
d_ff2_X[21]) );
DFFRX2TS inst_CORDIC_FSM_v3_state_reg_reg_7_ ( .D(
inst_CORDIC_FSM_v3_state_next[7]), .CK(clk), .RN(n1525), .Q(
inst_CORDIC_FSM_v3_state_reg[7]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_17_ ( .D(n783), .CK(clk), .RN(n1188), .Q(
d_ff2_Z[17]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_24_ ( .D(n776), .CK(clk), .RN(n1190), .Q(
d_ff2_Z[24]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_0_ ( .D(n800), .CK(clk), .RN(n1523), .Q(
d_ff2_Z[0]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_13_ ( .D(n787), .CK(clk), .RN(n1523), .Q(
d_ff2_Z[13]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_14_ ( .D(n786), .CK(clk), .RN(n1520), .Q(
d_ff2_Z[14]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_15_ ( .D(n785), .CK(clk), .RN(n1519), .Q(
d_ff2_Z[15]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_16_ ( .D(n784), .CK(clk), .RN(n1518), .Q(
d_ff2_Z[16]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_18_ ( .D(n782), .CK(clk), .RN(n1516), .Q(
d_ff2_Z[18]) );
DFFRXLTS ITER_CONT_temp_reg_0_ ( .D(n989), .CK(clk), .RN(n1532), .Q(n1182),
.QN(n1507) );
ADDFX1TS intadd_365_U4 ( .A(d_ff2_Y[24]), .B(n1499), .CI(intadd_365_CI),
.CO(intadd_365_n3), .S(intadd_365_SUM_0_) );
CMPR32X2TS intadd_365_U3 ( .A(d_ff2_Y[25]), .B(intadd_365_B_1_), .C(
intadd_365_n3), .CO(intadd_365_n2), .S(intadd_365_SUM_1_) );
CMPR32X2TS intadd_365_U2 ( .A(d_ff2_Y[26]), .B(n1496), .C(intadd_365_n2),
.CO(intadd_365_n1), .S(intadd_365_SUM_2_) );
AOI222X1TS U705 ( .A0(n1313), .A1(d_ff2_Z[29]), .B0(n1317), .B1(d_ff1_Z[29]),
.C0(d_ff_Zn[29]), .C1(n1463), .Y(n1303) );
AOI222X1TS U706 ( .A0(n1318), .A1(d_ff2_Z[28]), .B0(n1317), .B1(d_ff1_Z[28]),
.C0(d_ff_Zn[28]), .C1(n1463), .Y(n1307) );
AOI222X1TS U707 ( .A0(n1318), .A1(d_ff2_Z[27]), .B0(n1317), .B1(d_ff1_Z[27]),
.C0(d_ff_Zn[27]), .C1(n1463), .Y(n1309) );
AOI222X1TS U708 ( .A0(n1467), .A1(d_ff2_Z[30]), .B0(n1315), .B1(d_ff1_Z[30]),
.C0(d_ff_Zn[30]), .C1(n1463), .Y(n1316) );
AOI222X1TS U709 ( .A0(n1318), .A1(d_ff2_Z[23]), .B0(n1315), .B1(d_ff1_Z[23]),
.C0(d_ff_Zn[23]), .C1(n1443), .Y(n1306) );
AOI211X1TS U710 ( .A0(d_ff3_LUT_out[6]), .A1(n1442), .B0(n1202), .C0(n1201),
.Y(n1203) );
AOI222X1TS U711 ( .A0(n1376), .A1(d_ff3_sh_x_out[10]), .B0(n1223), .B1(
d_ff3_sh_y_out[10]), .C0(n1263), .C1(d_ff3_LUT_out[10]), .Y(n1280) );
AOI222X1TS U712 ( .A0(n1376), .A1(d_ff3_sh_x_out[26]), .B0(n1223), .B1(
d_ff3_sh_y_out[26]), .C0(n1263), .C1(d_ff3_LUT_out[26]), .Y(n1279) );
AOI222X1TS U713 ( .A0(n1376), .A1(d_ff3_sh_x_out[23]), .B0(n1223), .B1(
d_ff3_sh_y_out[23]), .C0(n1263), .C1(d_ff3_LUT_out[23]), .Y(n1272) );
AOI222X1TS U714 ( .A0(n1390), .A1(n1169), .B0(n1408), .B1(n1158), .C0(
d_ff2_Z[6]), .C1(n1276), .Y(n1270) );
AOI222X1TS U715 ( .A0(n1390), .A1(d_ff2_Y[1]), .B0(n1408), .B1(d_ff2_X[1]),
.C0(d_ff2_Z[1]), .C1(n1276), .Y(n1267) );
AOI222X1TS U716 ( .A0(n1265), .A1(d_ff2_Y[2]), .B0(n1408), .B1(d_ff2_X[2]),
.C0(d_ff2_Z[2]), .C1(n1276), .Y(n1266) );
AOI222X1TS U717 ( .A0(n1265), .A1(d_ff2_Y[3]), .B0(n1408), .B1(d_ff2_X[3]),
.C0(d_ff2_Z[3]), .C1(n1276), .Y(n1252) );
AOI222X1TS U718 ( .A0(n1265), .A1(d_ff2_Y[7]), .B0(n1408), .B1(n1157), .C0(
d_ff2_Z[7]), .C1(n1276), .Y(n1260) );
AOI222X1TS U719 ( .A0(n1376), .A1(d_ff3_sh_x_out[25]), .B0(n1223), .B1(
d_ff3_sh_y_out[25]), .C0(d_ff3_LUT_out[25]), .C1(n1276), .Y(n1275) );
AOI222X1TS U720 ( .A0(n1376), .A1(d_ff3_sh_x_out[24]), .B0(n1223), .B1(
d_ff3_sh_y_out[24]), .C0(n1387), .C1(d_ff3_LUT_out[24]), .Y(n1278) );
AOI222X1TS U721 ( .A0(n1250), .A1(d_ff2_Y[22]), .B0(n1273), .B1(n1153), .C0(
d_ff2_Z[22]), .C1(n1115), .Y(n1249) );
AOI222X1TS U722 ( .A0(n1250), .A1(d_ff2_Y[20]), .B0(n1273), .B1(d_ff2_X[20]),
.C0(d_ff2_Z[20]), .C1(n1115), .Y(n1247) );
AOI222X1TS U723 ( .A0(n1376), .A1(d_ff3_sh_x_out[6]), .B0(n1273), .B1(
d_ff3_sh_y_out[6]), .C0(d_ff3_LUT_out[6]), .C1(n1116), .Y(n1271) );
AOI222X1TS U724 ( .A0(n1250), .A1(d_ff2_Y[25]), .B0(n1273), .B1(n1175), .C0(
d_ff2_Z[25]), .C1(n1116), .Y(n1244) );
AOI222X1TS U725 ( .A0(n1250), .A1(n1165), .B0(n1273), .B1(d_ff2_X[19]), .C0(
d_ff2_Z[19]), .C1(n1116), .Y(n1248) );
AOI222X1TS U726 ( .A0(n1250), .A1(d_ff3_sh_x_out[2]), .B0(n1273), .B1(
d_ff3_sh_y_out[2]), .C0(n1116), .C1(d_ff3_LUT_out[2]), .Y(n1245) );
AOI222X1TS U727 ( .A0(n1250), .A1(d_ff3_sh_x_out[0]), .B0(n1273), .B1(
d_ff3_sh_y_out[0]), .C0(n1116), .C1(d_ff3_LUT_out[0]), .Y(n1243) );
AOI222X1TS U728 ( .A0(n1376), .A1(d_ff3_sh_x_out[4]), .B0(n1273), .B1(
d_ff3_sh_y_out[4]), .C0(n1387), .C1(d_ff3_LUT_out[4]), .Y(n1274) );
AOI222X1TS U729 ( .A0(n1250), .A1(d_ff3_sh_x_out[1]), .B0(n1273), .B1(
d_ff3_sh_y_out[1]), .C0(n1387), .C1(d_ff3_LUT_out[1]), .Y(n1246) );
AOI222X1TS U730 ( .A0(n1250), .A1(d_ff2_Y[21]), .B0(n1273), .B1(d_ff2_X[21]),
.C0(d_ff2_Z[21]), .C1(n1387), .Y(n1251) );
AOI222X1TS U731 ( .A0(n1390), .A1(d_ff2_Y[26]), .B0(n1273), .B1(n1174), .C0(
d_ff2_Z[26]), .C1(n1387), .Y(n1241) );
AOI222X1TS U732 ( .A0(n1265), .A1(d_ff2_Y[12]), .B0(n1268), .B1(d_ff2_X[12]),
.C0(d_ff2_Z[12]), .C1(n1387), .Y(n1256) );
AOI222X1TS U733 ( .A0(n1265), .A1(n1168), .B0(n1268), .B1(n1155), .C0(
d_ff2_Z[8]), .C1(n1276), .Y(n1261) );
AOI222X1TS U734 ( .A0(n1390), .A1(d_ff2_Y[5]), .B0(n1268), .B1(n1159), .C0(
d_ff2_Z[5]), .C1(n1276), .Y(n1269) );
AOI222X1TS U735 ( .A0(n1265), .A1(d_ff2_Y[4]), .B0(n1268), .B1(n1156), .C0(
d_ff2_Z[4]), .C1(n1387), .Y(n1254) );
AOI222X1TS U736 ( .A0(n1265), .A1(d_ff2_Y[11]), .B0(n1268), .B1(d_ff2_X[11]),
.C0(d_ff2_Z[11]), .C1(n1115), .Y(n1262) );
AOI222X1TS U737 ( .A0(n1265), .A1(d_ff2_Y[10]), .B0(n1268), .B1(d_ff2_X[10]),
.C0(d_ff2_Z[10]), .C1(n1115), .Y(n1257) );
AOI222X1TS U738 ( .A0(n1265), .A1(d_ff2_Y[9]), .B0(n1268), .B1(n1154), .C0(
d_ff2_Z[9]), .C1(n1115), .Y(n1258) );
NAND2X4TS U739 ( .A(n1281), .B(n1508), .Y(n1194) );
NOR2X6TS U740 ( .A(ready_cordic), .B(n1322), .Y(n1323) );
CLKBUFX3TS U741 ( .A(n1057), .Y(n1412) );
CLKBUFX3TS U742 ( .A(n1056), .Y(n1402) );
AOI222X1TS U743 ( .A0(n1364), .A1(data_output[28]), .B0(n1363), .B1(n1119),
.C0(n1366), .C1(d_ff_Xn[28]), .Y(n1333) );
AOI222X1TS U744 ( .A0(n1364), .A1(data_output[21]), .B0(n1363), .B1(n1131),
.C0(n1366), .C1(d_ff_Xn[21]), .Y(n1339) );
AOI222X1TS U745 ( .A0(n1364), .A1(data_output[22]), .B0(n1363), .B1(n1130),
.C0(n1366), .C1(d_ff_Xn[22]), .Y(n1362) );
AOI222X1TS U746 ( .A0(n1364), .A1(data_output[26]), .B0(n1363), .B1(n1127),
.C0(n1366), .C1(d_ff_Xn[26]), .Y(n1365) );
AOI222X1TS U747 ( .A0(n1364), .A1(data_output[29]), .B0(n1363), .B1(n1125),
.C0(n1366), .C1(d_ff_Xn[29]), .Y(n1351) );
AOI222X1TS U748 ( .A0(n1364), .A1(data_output[24]), .B0(n1363), .B1(n1129),
.C0(n1366), .C1(d_ff_Xn[24]), .Y(n1344) );
AOI222X1TS U749 ( .A0(n1313), .A1(d_ff2_Z[31]), .B0(n1317), .B1(d_ff1_Z[31]),
.C0(d_ff_Zn[31]), .C1(n1463), .Y(n1310) );
NOR2BX2TS U750 ( .AN(n1325), .B(n1368), .Y(n1326) );
AOI222X1TS U751 ( .A0(n1313), .A1(d_ff2_Z[0]), .B0(n1444), .B1(d_ff_Zn[0]),
.C0(n1315), .C1(d_ff1_Z[0]), .Y(n1319) );
AOI222X1TS U752 ( .A0(n1313), .A1(d_ff2_Z[14]), .B0(n1315), .B1(d_ff1_Z[14]),
.C0(d_ff_Zn[14]), .C1(n1443), .Y(n1296) );
AOI222X1TS U753 ( .A0(n1467), .A1(d_ff2_Z[16]), .B0(n1315), .B1(d_ff1_Z[16]),
.C0(d_ff_Zn[16]), .C1(n1443), .Y(n1288) );
AOI222X1TS U754 ( .A0(n1318), .A1(d_ff2_Z[13]), .B0(n1315), .B1(d_ff1_Z[13]),
.C0(d_ff_Zn[13]), .C1(n1443), .Y(n1289) );
AOI222X1TS U755 ( .A0(n1313), .A1(d_ff2_Z[15]), .B0(n1315), .B1(d_ff1_Z[15]),
.C0(d_ff_Zn[15]), .C1(n1443), .Y(n1290) );
AOI222X1TS U756 ( .A0(n1467), .A1(d_ff2_Z[18]), .B0(n1315), .B1(d_ff1_Z[18]),
.C0(d_ff_Zn[18]), .C1(n1443), .Y(n1292) );
INVX3TS U757 ( .A(n1398), .Y(n1396) );
XOR2XLTS U758 ( .A(n1171), .B(n1487), .Y(n1489) );
INVX3TS U759 ( .A(n1398), .Y(n1399) );
XOR2XLTS U760 ( .A(d_ff2_Y[30]), .B(n1453), .Y(n1454) );
NOR2X1TS U761 ( .A(n1462), .B(n1281), .Y(n1282) );
INVX2TS U762 ( .A(n1194), .Y(n1466) );
AO22XLTS U763 ( .A0(n1176), .A1(n1155), .B0(n1491), .B1(d_ff3_sh_x_out[8]),
.Y(n686) );
AOI32X1TS U764 ( .A0(n1320), .A1(n1176), .A2(n1434), .B0(d_ff3_LUT_out[23]),
.B1(n1442), .Y(n1196) );
INVX4TS U765 ( .A(n1209), .Y(n1397) );
NOR2X1TS U766 ( .A(n1392), .B(n1374), .Y(n1322) );
CLKBUFX3TS U767 ( .A(n1508), .Y(n1464) );
AO22XLTS U768 ( .A0(n1486), .A1(intadd_365_B_1_), .B0(n1484), .B1(
d_ff3_LUT_out[8]), .Y(n813) );
INVX3TS U769 ( .A(n1484), .Y(n1456) );
INVX3TS U770 ( .A(n1455), .Y(n1195) );
AOI222X1TS U771 ( .A0(n1250), .A1(d_ff2_Y[31]), .B0(n1273), .B1(n1152), .C0(
d_ff2_Z[31]), .C1(n1116), .Y(n1240) );
BUFX3TS U772 ( .A(n1404), .Y(n1056) );
BUFX3TS U773 ( .A(n1410), .Y(n1057) );
CLKBUFX2TS U774 ( .A(n1371), .Y(n1118) );
AOI222X1TS U775 ( .A0(n1250), .A1(n1167), .B0(n1268), .B1(d_ff2_X[17]), .C0(
d_ff2_Z[17]), .C1(n1387), .Y(n1222) );
OAI211X2TS U776 ( .A0(n1506), .A1(n1320), .B0(n1216), .C0(n1432), .Y(n1425)
);
NAND3BX1TS U777 ( .AN(inst_CORDIC_FSM_v3_state_reg[4]), .B(
inst_CORDIC_FSM_v3_state_reg[2]), .C(n1184), .Y(n1183) );
BUFX3TS U778 ( .A(n1416), .Y(n1419) );
INVX3TS U779 ( .A(n1226), .Y(n1218) );
INVX3TS U780 ( .A(n1242), .Y(n1263) );
INVX3TS U781 ( .A(n1320), .Y(n1437) );
INVX3TS U782 ( .A(n1239), .Y(n1223) );
CLKBUFX2TS U783 ( .A(d_ff1_operation_out), .Y(n1172) );
CLKBUFX2TS U784 ( .A(d_ff1_shift_region_flag_out[0]), .Y(n1173) );
NAND4XLTS U785 ( .A(n1496), .B(intadd_365_B_1_), .C(n1437), .D(n1499), .Y(
n1281) );
NAND2BXLTS U786 ( .AN(inst_CORDIC_FSM_v3_state_reg[7]), .B(n1207), .Y(n1208)
);
INVX2TS U787 ( .A(n1183), .Y(n1455) );
BUFX3TS U788 ( .A(n1300), .Y(n1315) );
INVX2TS U789 ( .A(d_ff3_LUT_out[3]), .Y(n1235) );
AO22XLTS U790 ( .A0(n1463), .A1(d_ff_Xn[21]), .B0(d_ff2_X[21]), .B1(n1313),
.Y(n661) );
AO22XLTS U791 ( .A0(n1463), .A1(n1121), .B0(d_ff2_X[18]), .B1(n1313), .Y(
n667) );
AO22XLTS U792 ( .A0(n1463), .A1(n1122), .B0(d_ff2_X[15]), .B1(n1318), .Y(
n673) );
AO22XLTS U793 ( .A0(n1463), .A1(d_ff_Xn[11]), .B0(d_ff2_X[11]), .B1(n1462),
.Y(n681) );
AO22XLTS U794 ( .A0(n1457), .A1(d_ff_Xn[0]), .B0(d_ff2_X[0]), .B1(n1318),
.Y(n703) );
AO22XLTS U795 ( .A0(n1457), .A1(d_ff_Yn_31_), .B0(d_ff2_Y[31]), .B1(n1467),
.Y(n705) );
AO22XLTS U796 ( .A0(n1420), .A1(result_add_subt[30]), .B0(n1416), .B1(
d_ff_Xn[30]), .Y(n855) );
AO22XLTS U797 ( .A0(n1418), .A1(result_add_subt[23]), .B0(n1419), .B1(
d_ff_Xn[23]), .Y(n862) );
AO22XLTS U798 ( .A0(n1418), .A1(result_add_subt[22]), .B0(n1417), .B1(
d_ff_Xn[22]), .Y(n863) );
AO22XLTS U799 ( .A0(n1418), .A1(result_add_subt[21]), .B0(n1417), .B1(
d_ff_Xn[21]), .Y(n864) );
AO22XLTS U800 ( .A0(n1446), .A1(n1136), .B0(d_ff2_Y[16]), .B1(n1195), .Y(
n735) );
AO22XLTS U801 ( .A0(n1446), .A1(n1138), .B0(d_ff2_Y[14]), .B1(n1195), .Y(
n739) );
AO22XLTS U802 ( .A0(n1446), .A1(n1139), .B0(d_ff2_Y[13]), .B1(n1195), .Y(
n741) );
AO22XLTS U803 ( .A0(n1446), .A1(n1140), .B0(d_ff2_Y[12]), .B1(n1195), .Y(
n743) );
AO22XLTS U804 ( .A0(n1446), .A1(n1141), .B0(d_ff2_Y[11]), .B1(n1195), .Y(
n745) );
AO22XLTS U805 ( .A0(n1446), .A1(n1142), .B0(d_ff2_Y[10]), .B1(n1445), .Y(
n747) );
AO22XLTS U806 ( .A0(n1444), .A1(n1143), .B0(d_ff2_Y[9]), .B1(n1445), .Y(n749) );
AO22XLTS U807 ( .A0(n1420), .A1(result_add_subt[29]), .B0(n1416), .B1(
d_ff_Xn[29]), .Y(n856) );
AO22XLTS U808 ( .A0(n1420), .A1(result_add_subt[27]), .B0(n1416), .B1(
d_ff_Xn[27]), .Y(n858) );
AO22XLTS U809 ( .A0(n1418), .A1(result_add_subt[20]), .B0(n1417), .B1(
d_ff_Xn[20]), .Y(n865) );
AO22XLTS U810 ( .A0(n1418), .A1(result_add_subt[19]), .B0(n1417), .B1(
d_ff_Xn[19]), .Y(n866) );
AO22XLTS U811 ( .A0(n1396), .A1(d_ff1_shift_region_flag_out[1]), .B0(n1398),
.B1(shift_region_flag[1]), .Y(n982) );
AO22XLTS U812 ( .A0(n1477), .A1(n1434), .B0(n1458), .B1(d_ff3_LUT_out[19]),
.Y(n807) );
AO22XLTS U813 ( .A0(n1420), .A1(result_add_subt[31]), .B0(n1416), .B1(
d_ff_Xn[31]), .Y(n854) );
AO22XLTS U814 ( .A0(n1411), .A1(result_add_subt[31]), .B0(n1413), .B1(
d_ff_Yn_31_), .Y(n886) );
AO22XLTS U815 ( .A0(n1415), .A1(result_add_subt[0]), .B0(n1417), .B1(
d_ff_Xn[0]), .Y(n885) );
AO22XLTS U816 ( .A0(n1415), .A1(result_add_subt[4]), .B0(n1419), .B1(
d_ff_Xn[4]), .Y(n881) );
AO22XLTS U817 ( .A0(n1415), .A1(result_add_subt[8]), .B0(n1419), .B1(
d_ff_Xn[8]), .Y(n877) );
AO22XLTS U818 ( .A0(n1415), .A1(result_add_subt[9]), .B0(n1419), .B1(
d_ff_Xn[9]), .Y(n876) );
AO22XLTS U819 ( .A0(n1415), .A1(result_add_subt[11]), .B0(n1419), .B1(
d_ff_Xn[11]), .Y(n874) );
AO22XLTS U820 ( .A0(n1446), .A1(n1151), .B0(d_ff2_Y[1]), .B1(n1445), .Y(n765) );
AO22XLTS U821 ( .A0(n1466), .A1(n1150), .B0(d_ff2_Y[2]), .B1(n1445), .Y(n763) );
AO22XLTS U822 ( .A0(n1466), .A1(n1149), .B0(d_ff2_Y[3]), .B1(n1445), .Y(n761) );
AO22XLTS U823 ( .A0(n1466), .A1(n1148), .B0(d_ff2_Y[4]), .B1(n1445), .Y(n759) );
AO22XLTS U824 ( .A0(n1466), .A1(n1147), .B0(d_ff2_Y[5]), .B1(n1445), .Y(n757) );
AO22XLTS U825 ( .A0(n1444), .A1(n1145), .B0(d_ff2_Y[7]), .B1(n1445), .Y(n753) );
AO22XLTS U826 ( .A0(n1446), .A1(n1137), .B0(d_ff2_Y[15]), .B1(n1195), .Y(
n737) );
AO22XLTS U827 ( .A0(n1446), .A1(n1132), .B0(d_ff2_Y[20]), .B1(n1195), .Y(
n727) );
AO22XLTS U828 ( .A0(n1457), .A1(n1131), .B0(d_ff2_Y[21]), .B1(n1195), .Y(
n725) );
AO22XLTS U829 ( .A0(n1457), .A1(n1130), .B0(d_ff2_Y[22]), .B1(n1195), .Y(
n723) );
AO22XLTS U830 ( .A0(n1420), .A1(result_add_subt[24]), .B0(n1416), .B1(
d_ff_Xn[24]), .Y(n861) );
AO22XLTS U831 ( .A0(n1420), .A1(result_add_subt[28]), .B0(n1416), .B1(
d_ff_Xn[28]), .Y(n857) );
AO22XLTS U832 ( .A0(n1415), .A1(result_add_subt[1]), .B0(n1419), .B1(
d_ff_Xn[1]), .Y(n884) );
AO22XLTS U833 ( .A0(n1415), .A1(result_add_subt[2]), .B0(n1419), .B1(
d_ff_Xn[2]), .Y(n883) );
AO22XLTS U834 ( .A0(n1415), .A1(result_add_subt[3]), .B0(n1419), .B1(
d_ff_Xn[3]), .Y(n882) );
AO22XLTS U835 ( .A0(n1415), .A1(result_add_subt[5]), .B0(n1419), .B1(
d_ff_Xn[5]), .Y(n880) );
AO22XLTS U836 ( .A0(n1415), .A1(result_add_subt[6]), .B0(n1419), .B1(
d_ff_Xn[6]), .Y(n879) );
AO22XLTS U837 ( .A0(n1415), .A1(result_add_subt[7]), .B0(n1419), .B1(
d_ff_Xn[7]), .Y(n878) );
AO22XLTS U838 ( .A0(n1415), .A1(result_add_subt[10]), .B0(n1419), .B1(
d_ff_Xn[10]), .Y(n875) );
AO22XLTS U839 ( .A0(n1420), .A1(result_add_subt[25]), .B0(n1416), .B1(
d_ff_Xn[25]), .Y(n860) );
AO22XLTS U840 ( .A0(n1420), .A1(result_add_subt[26]), .B0(n1416), .B1(
d_ff_Xn[26]), .Y(n859) );
NAND2BXLTS U841 ( .AN(d_ff3_LUT_out[27]), .B(n1442), .Y(n801) );
AO22XLTS U842 ( .A0(n1457), .A1(n1124), .B0(d_ff2_Y[30]), .B1(n1462), .Y(
n714) );
AO22XLTS U843 ( .A0(n1457), .A1(n1129), .B0(d_ff2_Y[24]), .B1(n1195), .Y(
n720) );
AO22XLTS U844 ( .A0(n1457), .A1(n1128), .B0(d_ff2_Y[25]), .B1(n1462), .Y(
n719) );
AO22XLTS U845 ( .A0(n1457), .A1(n1127), .B0(d_ff2_Y[26]), .B1(n1462), .Y(
n718) );
AO22XLTS U846 ( .A0(n1457), .A1(n1125), .B0(d_ff2_Y[29]), .B1(n1462), .Y(
n715) );
AO22XLTS U847 ( .A0(n1457), .A1(n1126), .B0(d_ff2_Y[27]), .B1(n1462), .Y(
n717) );
AOI2BB2XLTS U848 ( .B0(n1506), .B1(n1393), .A0N(n1393), .A1N(n1506), .Y(n987) );
OAI21XLTS U849 ( .A0(beg_fsm_cordic), .A1(n1370), .B0(n1211), .Y(
inst_CORDIC_FSM_v3_state_next[0]) );
AO22XLTS U850 ( .A0(n1481), .A1(d_ff3_sign_out), .B0(n1176), .B1(d_ff2_Z[31]), .Y(n768) );
OAI21XLTS U851 ( .A0(n1330), .A1(n1337), .B0(n1329), .Y(n822) );
AOI222X1TS U852 ( .A0(n1323), .A1(data_output[23]), .B0(n1363), .B1(n1120),
.C0(n1366), .C1(d_ff_Xn[23]), .Y(n1345) );
AOI222X1TS U853 ( .A0(n1364), .A1(data_output[19]), .B0(n1363), .B1(n1133),
.C0(n1366), .C1(d_ff_Xn[19]), .Y(n1336) );
AOI222X1TS U854 ( .A0(n1323), .A1(data_output[18]), .B0(n1367), .B1(n1134),
.C0(n1360), .C1(n1121), .Y(n1338) );
AOI222X1TS U855 ( .A0(n1323), .A1(data_output[17]), .B0(n1367), .B1(n1135),
.C0(n1360), .C1(n1160), .Y(n1346) );
AOI222X1TS U856 ( .A0(n1323), .A1(data_output[16]), .B0(n1367), .B1(n1136),
.C0(n1360), .C1(n1161), .Y(n1340) );
AOI222X1TS U857 ( .A0(n1323), .A1(data_output[15]), .B0(n1367), .B1(n1137),
.C0(n1360), .C1(n1122), .Y(n1341) );
AOI222X1TS U858 ( .A0(n1323), .A1(data_output[14]), .B0(n1367), .B1(n1138),
.C0(n1360), .C1(n1162), .Y(n1342) );
AOI222X1TS U859 ( .A0(n1323), .A1(data_output[13]), .B0(n1367), .B1(n1139),
.C0(n1360), .C1(n1163), .Y(n1359) );
AOI222X1TS U860 ( .A0(n1323), .A1(data_output[12]), .B0(n1367), .B1(n1140),
.C0(n1360), .C1(n1164), .Y(n1361) );
AOI222X1TS U861 ( .A0(n1323), .A1(data_output[11]), .B0(n1367), .B1(n1141),
.C0(n1360), .C1(d_ff_Xn[11]), .Y(n1358) );
AOI222X1TS U862 ( .A0(n1323), .A1(data_output[10]), .B0(n1367), .B1(n1142),
.C0(n1360), .C1(d_ff_Xn[10]), .Y(n1347) );
AOI222X1TS U863 ( .A0(n1368), .A1(data_output[9]), .B0(n1367), .B1(n1143),
.C0(n1360), .C1(d_ff_Xn[9]), .Y(n1348) );
AOI222X1TS U864 ( .A0(n1368), .A1(data_output[8]), .B0(n1367), .B1(n1144),
.C0(n1360), .C1(d_ff_Xn[8]), .Y(n1349) );
AOI222X1TS U865 ( .A0(n1368), .A1(data_output[7]), .B0(n1367), .B1(n1145),
.C0(n1360), .C1(d_ff_Xn[7]), .Y(n1350) );
AOI222X1TS U866 ( .A0(n1368), .A1(data_output[6]), .B0(n1367), .B1(n1146),
.C0(n1331), .C1(d_ff_Xn[6]), .Y(n1332) );
AOI222X1TS U867 ( .A0(n1368), .A1(data_output[5]), .B0(n1326), .B1(n1147),
.C0(n1360), .C1(d_ff_Xn[5]), .Y(n1352) );
AOI222X1TS U868 ( .A0(n1368), .A1(data_output[4]), .B0(n1326), .B1(n1148),
.C0(n1360), .C1(d_ff_Xn[4]), .Y(n1353) );
AOI222X1TS U869 ( .A0(n1368), .A1(data_output[3]), .B0(n1326), .B1(n1149),
.C0(n1360), .C1(d_ff_Xn[3]), .Y(n1354) );
AOI222X1TS U870 ( .A0(n1368), .A1(data_output[2]), .B0(n1367), .B1(n1150),
.C0(n1366), .C1(d_ff_Xn[2]), .Y(n1355) );
AOI222X1TS U871 ( .A0(n1368), .A1(data_output[1]), .B0(n1363), .B1(n1151),
.C0(n1366), .C1(d_ff_Xn[1]), .Y(n1356) );
AOI222X1TS U872 ( .A0(n1368), .A1(data_output[0]), .B0(n1123), .B1(n1363),
.C0(d_ff_Xn[0]), .C1(n1366), .Y(n1369) );
AOI2BB2XLTS U873 ( .B0(n1395), .B1(n1493), .A0N(n1493), .A1N(n1395), .Y(n985) );
OAI211XLTS U874 ( .A0(n1395), .A1(n1239), .B0(n1226), .C0(n1185), .Y(n990)
);
NOR2XLTS U875 ( .A(n1373), .B(n1402), .Y(inst_CORDIC_FSM_v3_state_next[6])
);
AO22XLTS U876 ( .A0(d_ff2_Y[23]), .A1(n1318), .B0(n1466), .B1(n1120), .Y(
n721) );
OAI211XLTS U877 ( .A0(n1176), .A1(n1503), .B0(n1421), .C0(n1435), .Y(n808)
);
AO22XLTS U878 ( .A0(d_ff2_Y[28]), .A1(n1313), .B0(n1466), .B1(n1119), .Y(
n716) );
AO22XLTS U879 ( .A0(n1490), .A1(n1152), .B0(n1491), .B1(d_ff3_sh_x_out[31]),
.Y(n640) );
AO22XLTS U880 ( .A0(n1446), .A1(d_ff_Xn[31]), .B0(n1152), .B1(n1195), .Y(
n641) );
AO22XLTS U881 ( .A0(n1171), .A1(n1467), .B0(n1466), .B1(d_ff_Xn[30]), .Y(
n650) );
AO22XLTS U882 ( .A0(n1463), .A1(d_ff_Xn[23]), .B0(n1177), .B1(n1467), .Y(
n657) );
AO22XLTS U883 ( .A0(n1490), .A1(n1153), .B0(n1488), .B1(d_ff3_sh_x_out[22]),
.Y(n658) );
AO22XLTS U884 ( .A0(n1463), .A1(d_ff_Xn[22]), .B0(n1153), .B1(n1313), .Y(
n659) );
AO22XLTS U885 ( .A0(n1486), .A1(d_ff2_X[21]), .B0(n1481), .B1(
d_ff3_sh_x_out[21]), .Y(n660) );
AO22XLTS U886 ( .A0(n1490), .A1(d_ff2_X[20]), .B0(n1488), .B1(
d_ff3_sh_x_out[20]), .Y(n662) );
AO22XLTS U887 ( .A0(n1486), .A1(d_ff2_X[19]), .B0(n1461), .B1(
d_ff3_sh_x_out[19]), .Y(n664) );
AO22XLTS U888 ( .A0(n1176), .A1(d_ff2_X[18]), .B0(n1459), .B1(
d_ff3_sh_x_out[18]), .Y(n666) );
AO22XLTS U889 ( .A0(n1490), .A1(d_ff2_X[17]), .B0(n1488), .B1(
d_ff3_sh_x_out[17]), .Y(n668) );
AO22XLTS U890 ( .A0(n1460), .A1(d_ff2_X[16]), .B0(n1458), .B1(
d_ff3_sh_x_out[16]), .Y(n670) );
AO22XLTS U891 ( .A0(n1456), .A1(d_ff2_X[15]), .B0(n1491), .B1(
d_ff3_sh_x_out[15]), .Y(n672) );
AO22XLTS U892 ( .A0(n1492), .A1(d_ff2_X[14]), .B0(n1459), .B1(
d_ff3_sh_x_out[14]), .Y(n674) );
AO22XLTS U893 ( .A0(n1486), .A1(d_ff2_X[13]), .B0(n1488), .B1(
d_ff3_sh_x_out[13]), .Y(n676) );
AO22XLTS U894 ( .A0(n1492), .A1(d_ff2_X[12]), .B0(n1488), .B1(
d_ff3_sh_x_out[12]), .Y(n678) );
AO22XLTS U895 ( .A0(n1477), .A1(d_ff2_X[11]), .B0(n1491), .B1(
d_ff3_sh_x_out[11]), .Y(n680) );
AO22XLTS U896 ( .A0(n1456), .A1(d_ff2_X[10]), .B0(n1459), .B1(
d_ff3_sh_x_out[10]), .Y(n682) );
AO22XLTS U897 ( .A0(n1460), .A1(n1154), .B0(n1458), .B1(d_ff3_sh_x_out[9]),
.Y(n684) );
AO22XLTS U898 ( .A0(n1457), .A1(d_ff_Xn[9]), .B0(n1154), .B1(n1462), .Y(n685) );
AO22XLTS U899 ( .A0(n1457), .A1(d_ff_Xn[8]), .B0(n1155), .B1(n1467), .Y(n687) );
AO22XLTS U900 ( .A0(n1486), .A1(n1157), .B0(n1491), .B1(d_ff3_sh_x_out[7]),
.Y(n688) );
AO22XLTS U901 ( .A0(n1477), .A1(n1158), .B0(n1491), .B1(d_ff3_sh_x_out[6]),
.Y(n690) );
AO22XLTS U902 ( .A0(n1456), .A1(n1159), .B0(n1458), .B1(d_ff3_sh_x_out[5]),
.Y(n692) );
AO22XLTS U903 ( .A0(n1456), .A1(n1156), .B0(n1491), .B1(d_ff3_sh_x_out[4]),
.Y(n694) );
AO22XLTS U904 ( .A0(n1457), .A1(d_ff_Xn[4]), .B0(n1156), .B1(n1313), .Y(n695) );
AO22XLTS U905 ( .A0(n1490), .A1(d_ff2_X[3]), .B0(n1491), .B1(
d_ff3_sh_x_out[3]), .Y(n696) );
AO22XLTS U906 ( .A0(n1490), .A1(d_ff2_X[2]), .B0(n1491), .B1(
d_ff3_sh_x_out[2]), .Y(n698) );
AO22XLTS U907 ( .A0(n1490), .A1(d_ff2_X[1]), .B0(n1491), .B1(
d_ff3_sh_x_out[1]), .Y(n700) );
AO22XLTS U908 ( .A0(n1490), .A1(d_ff2_X[0]), .B0(n1491), .B1(
d_ff3_sh_x_out[0]), .Y(n702) );
AO22XLTS U909 ( .A0(n1492), .A1(d_ff2_Y[31]), .B0(n1491), .B1(
d_ff3_sh_y_out[31]), .Y(n704) );
AO22XLTS U910 ( .A0(n1490), .A1(d_ff2_Y[22]), .B0(n1459), .B1(
d_ff3_sh_y_out[22]), .Y(n722) );
AO22XLTS U911 ( .A0(n1460), .A1(d_ff2_Y[21]), .B0(n1459), .B1(
d_ff3_sh_y_out[21]), .Y(n724) );
AO22XLTS U912 ( .A0(n1456), .A1(d_ff2_Y[20]), .B0(n1459), .B1(
d_ff3_sh_y_out[20]), .Y(n726) );
AO22XLTS U913 ( .A0(n1456), .A1(n1165), .B0(n1459), .B1(d_ff3_sh_y_out[19]),
.Y(n728) );
AO22XLTS U914 ( .A0(n1446), .A1(n1133), .B0(n1165), .B1(n1195), .Y(n729) );
AO22XLTS U915 ( .A0(n1456), .A1(n1166), .B0(n1459), .B1(d_ff3_sh_y_out[18]),
.Y(n730) );
AO22XLTS U916 ( .A0(n1446), .A1(n1134), .B0(n1166), .B1(n1195), .Y(n731) );
AO22XLTS U917 ( .A0(n1486), .A1(n1167), .B0(n1459), .B1(d_ff3_sh_y_out[17]),
.Y(n732) );
AO22XLTS U918 ( .A0(n1446), .A1(n1135), .B0(n1167), .B1(n1195), .Y(n733) );
AO22XLTS U919 ( .A0(n1492), .A1(d_ff2_Y[16]), .B0(n1459), .B1(
d_ff3_sh_y_out[16]), .Y(n734) );
AO22XLTS U920 ( .A0(n1477), .A1(d_ff2_Y[15]), .B0(n1459), .B1(
d_ff3_sh_y_out[15]), .Y(n736) );
AO22XLTS U921 ( .A0(n1176), .A1(d_ff2_Y[14]), .B0(n1458), .B1(
d_ff3_sh_y_out[14]), .Y(n738) );
AO22XLTS U922 ( .A0(n1477), .A1(d_ff2_Y[13]), .B0(n1458), .B1(
d_ff3_sh_y_out[13]), .Y(n740) );
AO22XLTS U923 ( .A0(n1460), .A1(d_ff2_Y[12]), .B0(n1458), .B1(
d_ff3_sh_y_out[12]), .Y(n742) );
AO22XLTS U924 ( .A0(n1492), .A1(d_ff2_Y[11]), .B0(n1458), .B1(
d_ff3_sh_y_out[11]), .Y(n744) );
AO22XLTS U925 ( .A0(n1492), .A1(d_ff2_Y[10]), .B0(n1458), .B1(
d_ff3_sh_y_out[10]), .Y(n746) );
AO22XLTS U926 ( .A0(n1456), .A1(d_ff2_Y[9]), .B0(n1458), .B1(
d_ff3_sh_y_out[9]), .Y(n748) );
AO22XLTS U927 ( .A0(n1490), .A1(n1168), .B0(n1458), .B1(d_ff3_sh_y_out[8]),
.Y(n750) );
AO22XLTS U928 ( .A0(n1443), .A1(n1144), .B0(n1168), .B1(n1445), .Y(n751) );
AO22XLTS U929 ( .A0(n1456), .A1(d_ff2_Y[7]), .B0(n1458), .B1(
d_ff3_sh_y_out[7]), .Y(n752) );
AO22XLTS U930 ( .A0(n1486), .A1(n1169), .B0(n1458), .B1(d_ff3_sh_y_out[6]),
.Y(n754) );
AO22XLTS U931 ( .A0(n1443), .A1(n1146), .B0(n1169), .B1(n1445), .Y(n755) );
AO22XLTS U932 ( .A0(n1456), .A1(d_ff2_Y[5]), .B0(n1458), .B1(
d_ff3_sh_y_out[5]), .Y(n756) );
AO22XLTS U933 ( .A0(n1486), .A1(d_ff2_Y[4]), .B0(n1488), .B1(
d_ff3_sh_y_out[4]), .Y(n758) );
AO22XLTS U934 ( .A0(n1456), .A1(d_ff2_Y[3]), .B0(n1488), .B1(
d_ff3_sh_y_out[3]), .Y(n760) );
AO22XLTS U935 ( .A0(n1486), .A1(d_ff2_Y[2]), .B0(n1488), .B1(
d_ff3_sh_y_out[2]), .Y(n762) );
AO22XLTS U936 ( .A0(n1456), .A1(d_ff2_Y[1]), .B0(n1488), .B1(
d_ff3_sh_y_out[1]), .Y(n764) );
AO22XLTS U937 ( .A0(n1486), .A1(n1170), .B0(n1488), .B1(d_ff3_sh_y_out[0]),
.Y(n766) );
AO22XLTS U938 ( .A0(n1463), .A1(n1123), .B0(n1170), .B1(n1318), .Y(n767) );
AO22XLTS U939 ( .A0(n1486), .A1(n1489), .B0(n1488), .B1(d_ff3_sh_x_out[30]),
.Y(n642) );
AO22XLTS U940 ( .A0(n1486), .A1(n1482), .B0(n1481), .B1(d_ff3_sh_x_out[28]),
.Y(n644) );
OAI21XLTS U941 ( .A0(n1480), .A1(n1501), .B0(n1483), .Y(n1482) );
AOI2BB2XLTS U942 ( .B0(n1176), .B1(n1478), .A0N(d_ff3_sh_x_out[27]), .A1N(
n1460), .Y(n645) );
AO22XLTS U943 ( .A0(n1486), .A1(n1475), .B0(n1488), .B1(d_ff3_sh_x_out[26]),
.Y(n646) );
AO22XLTS U944 ( .A0(n1486), .A1(n1473), .B0(n1488), .B1(d_ff3_sh_x_out[25]),
.Y(n647) );
AO21XLTS U945 ( .A0(d_ff3_sh_x_out[24]), .A1(n1488), .B0(n1471), .Y(n648) );
AO22XLTS U946 ( .A0(n1490), .A1(n1454), .B0(n1491), .B1(d_ff3_sh_y_out[30]),
.Y(n706) );
AOI2BB2XLTS U947 ( .B0(n1492), .B1(n1452), .A0N(d_ff3_sh_y_out[29]), .A1N(
n1477), .Y(n707) );
AO22XLTS U948 ( .A0(n1490), .A1(n1450), .B0(n1491), .B1(d_ff3_sh_y_out[28]),
.Y(n708) );
OAI21XLTS U949 ( .A0(n1448), .A1(n1505), .B0(n1451), .Y(n1450) );
AOI2BB2XLTS U950 ( .B0(n1176), .B1(n1447), .A0N(d_ff3_sh_y_out[27]), .A1N(
n1477), .Y(n709) );
AO22XLTS U951 ( .A0(n1490), .A1(intadd_365_SUM_2_), .B0(n1459), .B1(
d_ff3_sh_y_out[26]), .Y(n710) );
AO22XLTS U952 ( .A0(n1490), .A1(intadd_365_SUM_1_), .B0(n1459), .B1(
d_ff3_sh_y_out[25]), .Y(n711) );
AO22XLTS U953 ( .A0(n1477), .A1(intadd_365_SUM_0_), .B0(n1459), .B1(
d_ff3_sh_y_out[24]), .Y(n712) );
OAI21XLTS U954 ( .A0(n1442), .A1(intadd_365_CI), .B0(n1198), .Y(n713) );
OAI21XLTS U955 ( .A0(cont_iter_out[3]), .A1(n1469), .B0(n1199), .Y(n802) );
NOR2XLTS U956 ( .A(n1437), .B(n1470), .Y(n1438) );
OAI21XLTS U957 ( .A0(n1437), .A1(n1435), .B0(n1213), .Y(n804) );
OAI21XLTS U958 ( .A0(n1434), .A1(n1440), .B0(n1196), .Y(n805) );
NAND2BXLTS U959 ( .AN(n1430), .B(n1429), .Y(n811) );
OAI211XLTS U960 ( .A0(n1477), .A1(n1178), .B0(n1217), .C0(n1431), .Y(n812)
);
OAI21XLTS U961 ( .A0(n1506), .A1(n1470), .B0(n1215), .Y(n817) );
OAI211XLTS U962 ( .A0(n1460), .A1(n1235), .B0(n1421), .C0(n1217), .Y(n818)
);
OAI21XLTS U963 ( .A0(n1469), .A1(n1216), .B0(n1200), .Y(n819) );
AO22XLTS U964 ( .A0(n1418), .A1(result_add_subt[18]), .B0(n1417), .B1(n1121),
.Y(n867) );
AO22XLTS U965 ( .A0(n1418), .A1(result_add_subt[17]), .B0(n1417), .B1(n1160),
.Y(n868) );
AO22XLTS U966 ( .A0(n1418), .A1(result_add_subt[16]), .B0(n1417), .B1(n1161),
.Y(n869) );
AO22XLTS U967 ( .A0(n1418), .A1(result_add_subt[15]), .B0(n1417), .B1(n1122),
.Y(n870) );
AO22XLTS U968 ( .A0(n1418), .A1(result_add_subt[14]), .B0(n1417), .B1(n1162),
.Y(n871) );
AO22XLTS U969 ( .A0(n1418), .A1(result_add_subt[13]), .B0(n1417), .B1(n1163),
.Y(n872) );
AO22XLTS U970 ( .A0(n1418), .A1(result_add_subt[12]), .B0(n1417), .B1(n1164),
.Y(n873) );
AO22XLTS U971 ( .A0(n1411), .A1(result_add_subt[30]), .B0(n1413), .B1(n1124),
.Y(n887) );
AO22XLTS U972 ( .A0(n1411), .A1(result_add_subt[29]), .B0(n1413), .B1(n1125),
.Y(n888) );
AO22XLTS U973 ( .A0(n1414), .A1(result_add_subt[28]), .B0(n1413), .B1(n1119),
.Y(n889) );
AO22XLTS U974 ( .A0(n1414), .A1(result_add_subt[27]), .B0(n1413), .B1(n1126),
.Y(n890) );
AO22XLTS U975 ( .A0(n1411), .A1(result_add_subt[26]), .B0(n1413), .B1(n1127),
.Y(n891) );
AO22XLTS U976 ( .A0(n1411), .A1(result_add_subt[25]), .B0(n1413), .B1(n1128),
.Y(n892) );
AO22XLTS U977 ( .A0(n1414), .A1(result_add_subt[24]), .B0(n1413), .B1(n1129),
.Y(n893) );
AO22XLTS U978 ( .A0(n1411), .A1(result_add_subt[23]), .B0(n1413), .B1(n1120),
.Y(n894) );
AO22XLTS U979 ( .A0(n1414), .A1(result_add_subt[22]), .B0(n1413), .B1(n1130),
.Y(n895) );
AO22XLTS U980 ( .A0(n1411), .A1(result_add_subt[21]), .B0(n1057), .B1(n1131),
.Y(n896) );
AO22XLTS U981 ( .A0(n1411), .A1(result_add_subt[20]), .B0(n1057), .B1(n1132),
.Y(n897) );
AO22XLTS U982 ( .A0(n1414), .A1(result_add_subt[19]), .B0(n1057), .B1(n1133),
.Y(n898) );
AO22XLTS U983 ( .A0(n1411), .A1(result_add_subt[18]), .B0(n1057), .B1(n1134),
.Y(n899) );
AO22XLTS U984 ( .A0(n1411), .A1(result_add_subt[17]), .B0(n1057), .B1(n1135),
.Y(n900) );
AO22XLTS U985 ( .A0(n1414), .A1(result_add_subt[16]), .B0(n1057), .B1(n1136),
.Y(n901) );
AO22XLTS U986 ( .A0(n1414), .A1(result_add_subt[15]), .B0(n1410), .B1(n1137),
.Y(n902) );
AO22XLTS U987 ( .A0(n1411), .A1(result_add_subt[14]), .B0(n1410), .B1(n1138),
.Y(n903) );
AO22XLTS U988 ( .A0(n1411), .A1(result_add_subt[13]), .B0(n1413), .B1(n1139),
.Y(n904) );
AO22XLTS U989 ( .A0(n1411), .A1(result_add_subt[12]), .B0(n1413), .B1(n1140),
.Y(n905) );
AO22XLTS U990 ( .A0(n1411), .A1(result_add_subt[11]), .B0(n1412), .B1(n1141),
.Y(n906) );
AO22XLTS U991 ( .A0(n1414), .A1(result_add_subt[10]), .B0(n1057), .B1(n1142),
.Y(n907) );
AO22XLTS U992 ( .A0(n1411), .A1(result_add_subt[9]), .B0(n1057), .B1(n1143),
.Y(n908) );
AO22XLTS U993 ( .A0(n1409), .A1(result_add_subt[8]), .B0(n1057), .B1(n1144),
.Y(n909) );
AO22XLTS U994 ( .A0(n1409), .A1(result_add_subt[7]), .B0(n1057), .B1(n1145),
.Y(n910) );
AO22XLTS U995 ( .A0(n1409), .A1(result_add_subt[6]), .B0(n1057), .B1(n1146),
.Y(n911) );
AO22XLTS U996 ( .A0(n1409), .A1(result_add_subt[5]), .B0(n1057), .B1(n1147),
.Y(n912) );
AO22XLTS U997 ( .A0(n1409), .A1(result_add_subt[4]), .B0(n1412), .B1(n1148),
.Y(n913) );
AO22XLTS U998 ( .A0(n1409), .A1(result_add_subt[3]), .B0(n1412), .B1(n1149),
.Y(n914) );
AO22XLTS U999 ( .A0(n1409), .A1(result_add_subt[2]), .B0(n1412), .B1(n1150),
.Y(n915) );
AO22XLTS U1000 ( .A0(n1409), .A1(result_add_subt[1]), .B0(n1412), .B1(n1151),
.Y(n916) );
AO22XLTS U1001 ( .A0(n1409), .A1(result_add_subt[0]), .B0(n1412), .B1(n1123),
.Y(n917) );
AO22XLTS U1002 ( .A0(n1407), .A1(result_add_subt[31]), .B0(n1406), .B1(
d_ff_Zn[31]), .Y(n918) );
AO22XLTS U1003 ( .A0(n1407), .A1(result_add_subt[30]), .B0(n1056), .B1(
d_ff_Zn[30]), .Y(n919) );
AO22XLTS U1004 ( .A0(n1407), .A1(result_add_subt[29]), .B0(n1056), .B1(
d_ff_Zn[29]), .Y(n920) );
AO22XLTS U1005 ( .A0(n1403), .A1(result_add_subt[28]), .B0(n1056), .B1(
d_ff_Zn[28]), .Y(n921) );
AO22XLTS U1006 ( .A0(n1407), .A1(result_add_subt[27]), .B0(n1056), .B1(
d_ff_Zn[27]), .Y(n922) );
AO22XLTS U1007 ( .A0(n1407), .A1(result_add_subt[26]), .B0(n1056), .B1(
d_ff_Zn[26]), .Y(n923) );
AO22XLTS U1008 ( .A0(n1403), .A1(result_add_subt[25]), .B0(n1056), .B1(
d_ff_Zn[25]), .Y(n924) );
AO22XLTS U1009 ( .A0(n1407), .A1(result_add_subt[24]), .B0(n1406), .B1(
d_ff_Zn[24]), .Y(n925) );
AO22XLTS U1010 ( .A0(n1403), .A1(result_add_subt[23]), .B0(n1406), .B1(
d_ff_Zn[23]), .Y(n926) );
AO22XLTS U1011 ( .A0(n1405), .A1(result_add_subt[22]), .B0(n1404), .B1(
d_ff_Zn[22]), .Y(n927) );
AO22XLTS U1012 ( .A0(n1405), .A1(result_add_subt[21]), .B0(n1406), .B1(
d_ff_Zn[21]), .Y(n928) );
AO22XLTS U1013 ( .A0(n1403), .A1(result_add_subt[20]), .B0(n1406), .B1(
d_ff_Zn[20]), .Y(n929) );
AO22XLTS U1014 ( .A0(n1407), .A1(result_add_subt[19]), .B0(n1406), .B1(
d_ff_Zn[19]), .Y(n930) );
AO22XLTS U1015 ( .A0(n1403), .A1(result_add_subt[18]), .B0(n1406), .B1(
d_ff_Zn[18]), .Y(n931) );
AO22XLTS U1016 ( .A0(n1407), .A1(result_add_subt[17]), .B0(n1406), .B1(
d_ff_Zn[17]), .Y(n932) );
AO22XLTS U1017 ( .A0(n1407), .A1(result_add_subt[16]), .B0(n1406), .B1(
d_ff_Zn[16]), .Y(n933) );
AO22XLTS U1018 ( .A0(n1403), .A1(result_add_subt[15]), .B0(n1406), .B1(
d_ff_Zn[15]), .Y(n934) );
AO22XLTS U1019 ( .A0(n1407), .A1(result_add_subt[14]), .B0(n1406), .B1(
d_ff_Zn[14]), .Y(n935) );
AO22XLTS U1020 ( .A0(n1407), .A1(result_add_subt[13]), .B0(n1406), .B1(
d_ff_Zn[13]), .Y(n936) );
AO22XLTS U1021 ( .A0(n1403), .A1(result_add_subt[12]), .B0(n1406), .B1(
d_ff_Zn[12]), .Y(n937) );
AO22XLTS U1022 ( .A0(n1403), .A1(result_add_subt[11]), .B0(n1406), .B1(
d_ff_Zn[11]), .Y(n938) );
AO22XLTS U1023 ( .A0(n1407), .A1(result_add_subt[10]), .B0(n1402), .B1(
d_ff_Zn[10]), .Y(n939) );
AO22XLTS U1024 ( .A0(n1407), .A1(result_add_subt[9]), .B0(n1056), .B1(
d_ff_Zn[9]), .Y(n940) );
AO22XLTS U1025 ( .A0(n1403), .A1(result_add_subt[8]), .B0(n1056), .B1(
d_ff_Zn[8]), .Y(n941) );
AO22XLTS U1026 ( .A0(n1407), .A1(result_add_subt[7]), .B0(n1404), .B1(
d_ff_Zn[7]), .Y(n942) );
AO22XLTS U1027 ( .A0(n1405), .A1(result_add_subt[6]), .B0(n1056), .B1(
d_ff_Zn[6]), .Y(n943) );
AO22XLTS U1028 ( .A0(n1405), .A1(result_add_subt[5]), .B0(n1056), .B1(
d_ff_Zn[5]), .Y(n944) );
AO22XLTS U1029 ( .A0(n1405), .A1(result_add_subt[4]), .B0(n1056), .B1(
d_ff_Zn[4]), .Y(n945) );
AO22XLTS U1030 ( .A0(n1405), .A1(result_add_subt[3]), .B0(n1056), .B1(
d_ff_Zn[3]), .Y(n946) );
AO22XLTS U1031 ( .A0(n1405), .A1(result_add_subt[2]), .B0(n1402), .B1(
d_ff_Zn[2]), .Y(n947) );
AO22XLTS U1032 ( .A0(n1405), .A1(result_add_subt[1]), .B0(n1402), .B1(
d_ff_Zn[1]), .Y(n948) );
AO22XLTS U1033 ( .A0(n1405), .A1(result_add_subt[0]), .B0(n1402), .B1(
d_ff_Zn[0]), .Y(n949) );
AO22XLTS U1034 ( .A0(n1401), .A1(d_ff1_Z[31]), .B0(n1400), .B1(data_in[31]),
.Y(n950) );
AO22XLTS U1035 ( .A0(n1401), .A1(d_ff1_Z[30]), .B0(n1400), .B1(data_in[30]),
.Y(n951) );
AO22XLTS U1036 ( .A0(n1401), .A1(d_ff1_Z[29]), .B0(n1400), .B1(data_in[29]),
.Y(n952) );
AO22XLTS U1037 ( .A0(n1401), .A1(d_ff1_Z[28]), .B0(n1400), .B1(data_in[28]),
.Y(n953) );
AO22XLTS U1038 ( .A0(n1401), .A1(d_ff1_Z[27]), .B0(n1400), .B1(data_in[27]),
.Y(n954) );
AO22XLTS U1039 ( .A0(n1401), .A1(d_ff1_Z[26]), .B0(n1400), .B1(data_in[26]),
.Y(n955) );
AO22XLTS U1040 ( .A0(n1401), .A1(d_ff1_Z[25]), .B0(n1400), .B1(data_in[25]),
.Y(n956) );
AO22XLTS U1041 ( .A0(n1401), .A1(d_ff1_Z[24]), .B0(n1400), .B1(data_in[24]),
.Y(n957) );
AO22XLTS U1042 ( .A0(n1399), .A1(d_ff1_Z[23]), .B0(n1400), .B1(data_in[23]),
.Y(n958) );
AO22XLTS U1043 ( .A0(n1399), .A1(d_ff1_Z[22]), .B0(n1400), .B1(data_in[22]),
.Y(n959) );
AO22XLTS U1044 ( .A0(n1399), .A1(d_ff1_Z[21]), .B0(n1400), .B1(data_in[21]),
.Y(n960) );
AO22XLTS U1045 ( .A0(n1399), .A1(d_ff1_Z[20]), .B0(n1400), .B1(data_in[20]),
.Y(n961) );
AO22XLTS U1046 ( .A0(n1399), .A1(d_ff1_Z[19]), .B0(n1397), .B1(data_in[19]),
.Y(n962) );
AO22XLTS U1047 ( .A0(n1399), .A1(d_ff1_Z[18]), .B0(n1397), .B1(data_in[18]),
.Y(n963) );
AO22XLTS U1048 ( .A0(n1399), .A1(d_ff1_Z[17]), .B0(n1397), .B1(data_in[17]),
.Y(n964) );
AO22XLTS U1049 ( .A0(n1399), .A1(d_ff1_Z[16]), .B0(n1397), .B1(data_in[16]),
.Y(n965) );
AO22XLTS U1050 ( .A0(n1399), .A1(d_ff1_Z[15]), .B0(n1397), .B1(data_in[15]),
.Y(n966) );
AO22XLTS U1051 ( .A0(n1399), .A1(d_ff1_Z[14]), .B0(n1397), .B1(data_in[14]),
.Y(n967) );
AO22XLTS U1052 ( .A0(n1399), .A1(d_ff1_Z[13]), .B0(n1397), .B1(data_in[13]),
.Y(n968) );
AO22XLTS U1053 ( .A0(n1399), .A1(d_ff1_Z[12]), .B0(n1397), .B1(data_in[12]),
.Y(n969) );
AO22XLTS U1054 ( .A0(n1399), .A1(d_ff1_Z[11]), .B0(n1397), .B1(data_in[11]),
.Y(n970) );
AO22XLTS U1055 ( .A0(n1399), .A1(d_ff1_Z[10]), .B0(n1397), .B1(data_in[10]),
.Y(n971) );
AO22XLTS U1056 ( .A0(n1396), .A1(d_ff1_Z[9]), .B0(n1397), .B1(data_in[9]),
.Y(n972) );
AO22XLTS U1057 ( .A0(n1396), .A1(d_ff1_Z[8]), .B0(n1397), .B1(data_in[8]),
.Y(n973) );
AO22XLTS U1058 ( .A0(n1396), .A1(d_ff1_Z[7]), .B0(n1397), .B1(data_in[7]),
.Y(n974) );
AO22XLTS U1059 ( .A0(n1396), .A1(d_ff1_Z[6]), .B0(n1398), .B1(data_in[6]),
.Y(n975) );
AO22XLTS U1060 ( .A0(n1396), .A1(d_ff1_Z[5]), .B0(n1398), .B1(data_in[5]),
.Y(n976) );
AO22XLTS U1061 ( .A0(n1396), .A1(d_ff1_Z[4]), .B0(n1398), .B1(data_in[4]),
.Y(n977) );
AO22XLTS U1062 ( .A0(n1396), .A1(d_ff1_Z[3]), .B0(n1398), .B1(data_in[3]),
.Y(n978) );
AO22XLTS U1063 ( .A0(n1396), .A1(d_ff1_Z[2]), .B0(n1398), .B1(data_in[2]),
.Y(n979) );
AO22XLTS U1064 ( .A0(n1396), .A1(d_ff1_Z[1]), .B0(n1398), .B1(data_in[1]),
.Y(n980) );
AO22XLTS U1065 ( .A0(n1396), .A1(d_ff1_Z[0]), .B0(n1398), .B1(data_in[0]),
.Y(n981) );
AO22XLTS U1066 ( .A0(n1396), .A1(n1173), .B0(n1398), .B1(
shift_region_flag[0]), .Y(n983) );
AO22XLTS U1067 ( .A0(n1396), .A1(n1172), .B0(n1397), .B1(operation), .Y(n984) );
INVX2TS U1068 ( .A(n1263), .Y(n1114) );
CLKINVX3TS U1069 ( .A(n1114), .Y(n1115) );
INVX2TS U1070 ( .A(n1114), .Y(n1116) );
CLKBUFX2TS U1071 ( .A(n1194), .Y(n1117) );
AOI222X4TS U1072 ( .A0(n1313), .A1(d_ff2_Z[22]), .B0(n1315), .B1(d_ff1_Z[22]), .C0(d_ff_Zn[22]), .C1(n1443), .Y(n1308) );
AOI222X4TS U1073 ( .A0(n1467), .A1(d_ff2_Z[21]), .B0(n1315), .B1(d_ff1_Z[21]), .C0(d_ff_Zn[21]), .C1(n1443), .Y(n1314) );
AOI222X4TS U1074 ( .A0(n1467), .A1(d_ff2_Z[20]), .B0(n1315), .B1(d_ff1_Z[20]), .C0(d_ff_Zn[20]), .C1(n1443), .Y(n1305) );
AOI222X4TS U1075 ( .A0(n1318), .A1(d_ff2_Z[19]), .B0(n1315), .B1(d_ff1_Z[19]), .C0(d_ff_Zn[19]), .C1(n1443), .Y(n1301) );
AOI222X1TS U1076 ( .A0(n1250), .A1(n1166), .B0(n1268), .B1(d_ff2_X[18]),
.C0(d_ff2_Z[18]), .C1(n1115), .Y(n1220) );
AOI222X1TS U1077 ( .A0(n1265), .A1(d_ff2_Y[16]), .B0(n1268), .B1(d_ff2_X[16]), .C0(d_ff2_Z[16]), .C1(n1115), .Y(n1264) );
AOI222X1TS U1078 ( .A0(n1265), .A1(d_ff2_Y[15]), .B0(n1268), .B1(d_ff2_X[15]), .C0(d_ff2_Z[15]), .C1(n1115), .Y(n1253) );
AOI222X1TS U1079 ( .A0(n1265), .A1(d_ff2_Y[14]), .B0(n1268), .B1(d_ff2_X[14]), .C0(d_ff2_Z[14]), .C1(n1115), .Y(n1255) );
AOI222X1TS U1080 ( .A0(n1265), .A1(d_ff2_Y[13]), .B0(n1273), .B1(d_ff2_X[13]), .C0(d_ff2_Z[13]), .C1(n1387), .Y(n1259) );
AOI222X1TS U1081 ( .A0(n1250), .A1(n1170), .B0(n1268), .B1(d_ff2_X[0]), .C0(
d_ff2_Z[0]), .C1(n1115), .Y(n1221) );
NOR3X1TS U1082 ( .A(inst_CORDIC_FSM_v3_state_reg[6]), .B(
inst_CORDIC_FSM_v3_state_reg[5]), .C(inst_CORDIC_FSM_v3_state_reg[0]),
.Y(n1192) );
OAI21XLTS U1083 ( .A0(n1263), .A1(n1372), .B0(n1481), .Y(
inst_CORDIC_FSM_v3_state_next[4]) );
OAI32X1TS U1084 ( .A0(n1393), .A1(n1437), .A2(n1392), .B0(n1499), .B1(n1393),
.Y(n988) );
BUFX4TS U1085 ( .A(n1187), .Y(n1522) );
BUFX4TS U1086 ( .A(n1187), .Y(n1516) );
BUFX4TS U1087 ( .A(n281), .Y(n1188) );
BUFX3TS U1088 ( .A(n281), .Y(n1190) );
BUFX3TS U1089 ( .A(n1188), .Y(n1189) );
BUFX3TS U1090 ( .A(n1190), .Y(n1187) );
BUFX4TS U1091 ( .A(n1525), .Y(n1530) );
BUFX4TS U1092 ( .A(n1525), .Y(n1529) );
BUFX4TS U1093 ( .A(n1188), .Y(n1532) );
BUFX4TS U1094 ( .A(n1190), .Y(n1531) );
BUFX4TS U1095 ( .A(n1190), .Y(n1515) );
BUFX4TS U1096 ( .A(n1188), .Y(n1525) );
BUFX4TS U1097 ( .A(n1515), .Y(n1523) );
BUFX4TS U1098 ( .A(n1515), .Y(n1520) );
BUFX4TS U1099 ( .A(n1515), .Y(n1519) );
BUFX4TS U1100 ( .A(n1521), .Y(n1518) );
BUFX4TS U1101 ( .A(n1223), .Y(n1408) );
NOR2X2TS U1102 ( .A(n1496), .B(intadd_365_B_1_), .Y(n1321) );
BUFX4TS U1103 ( .A(n1300), .Y(n1317) );
INVX2TS U1104 ( .A(n1242), .Y(n1276) );
OR2X2TS U1105 ( .A(n1494), .B(n1493), .Y(n1242) );
NOR3X2TS U1106 ( .A(inst_CORDIC_FSM_v3_state_reg[2]), .B(
inst_CORDIC_FSM_v3_state_reg[4]), .C(inst_CORDIC_FSM_v3_state_reg[1]),
.Y(n1191) );
AOI211X1TS U1107 ( .A0(n1437), .A1(n1499), .B0(n1442), .C0(n1432), .Y(n1202)
);
NAND2X2TS U1108 ( .A(cont_iter_out[3]), .B(intadd_365_B_1_), .Y(n1432) );
INVX2TS U1109 ( .A(n1108), .Y(n1119) );
INVX2TS U1110 ( .A(n1107), .Y(n1120) );
INVX2TS U1111 ( .A(n1106), .Y(n1121) );
INVX2TS U1112 ( .A(n1105), .Y(n1122) );
INVX2TS U1113 ( .A(n1104), .Y(n1123) );
INVX2TS U1114 ( .A(n1103), .Y(n1124) );
INVX2TS U1115 ( .A(n1102), .Y(n1125) );
INVX2TS U1116 ( .A(n1101), .Y(n1126) );
INVX2TS U1117 ( .A(n1100), .Y(n1127) );
INVX2TS U1118 ( .A(n1099), .Y(n1128) );
INVX2TS U1119 ( .A(n1088), .Y(n1129) );
INVX2TS U1120 ( .A(n1087), .Y(n1130) );
INVX2TS U1121 ( .A(n1086), .Y(n1131) );
INVX2TS U1122 ( .A(n1085), .Y(n1132) );
INVX2TS U1123 ( .A(n1084), .Y(n1133) );
INVX2TS U1124 ( .A(n1068), .Y(n1134) );
INVX2TS U1125 ( .A(n1067), .Y(n1135) );
INVX2TS U1126 ( .A(n1066), .Y(n1136) );
INVX2TS U1127 ( .A(n1065), .Y(n1137) );
INVX2TS U1128 ( .A(n1064), .Y(n1138) );
INVX2TS U1129 ( .A(n1063), .Y(n1139) );
INVX2TS U1130 ( .A(n1062), .Y(n1140) );
INVX2TS U1131 ( .A(n1083), .Y(n1141) );
INVX2TS U1132 ( .A(n1098), .Y(n1142) );
INVX2TS U1133 ( .A(n1097), .Y(n1143) );
INVX2TS U1134 ( .A(n1096), .Y(n1144) );
INVX2TS U1135 ( .A(n1095), .Y(n1145) );
INVX2TS U1136 ( .A(n1094), .Y(n1146) );
INVX2TS U1137 ( .A(n1093), .Y(n1147) );
INVX2TS U1138 ( .A(n1092), .Y(n1148) );
INVX2TS U1139 ( .A(n1091), .Y(n1149) );
INVX2TS U1140 ( .A(n1090), .Y(n1150) );
INVX2TS U1141 ( .A(n1089), .Y(n1151) );
INVX2TS U1142 ( .A(n1081), .Y(n1152) );
INVX2TS U1143 ( .A(n1080), .Y(n1153) );
INVX2TS U1144 ( .A(n1079), .Y(n1154) );
INVX2TS U1145 ( .A(n1078), .Y(n1155) );
INVX2TS U1146 ( .A(n1077), .Y(n1156) );
INVX2TS U1147 ( .A(n1076), .Y(n1157) );
INVX2TS U1148 ( .A(n1075), .Y(n1158) );
INVX2TS U1149 ( .A(n1074), .Y(n1159) );
INVX2TS U1150 ( .A(n1113), .Y(n1160) );
INVX2TS U1151 ( .A(n1112), .Y(n1161) );
INVX2TS U1152 ( .A(n1111), .Y(n1162) );
INVX2TS U1153 ( .A(n1110), .Y(n1163) );
INVX2TS U1154 ( .A(n1109), .Y(n1164) );
INVX2TS U1155 ( .A(n1061), .Y(n1165) );
INVX2TS U1156 ( .A(n1072), .Y(n1166) );
INVX2TS U1157 ( .A(n1073), .Y(n1167) );
INVX2TS U1158 ( .A(n1060), .Y(n1168) );
INVX2TS U1159 ( .A(n1059), .Y(n1169) );
INVX2TS U1160 ( .A(n1058), .Y(n1170) );
INVX2TS U1161 ( .A(n1082), .Y(n1171) );
AOI222X4TS U1162 ( .A0(n1364), .A1(data_output[30]), .B0(n1363), .B1(n1124),
.C0(n1366), .C1(d_ff_Xn[30]), .Y(n1335) );
AOI222X4TS U1163 ( .A0(n1364), .A1(data_output[27]), .B0(n1363), .B1(n1126),
.C0(n1366), .C1(d_ff_Xn[27]), .Y(n1357) );
AOI222X4TS U1164 ( .A0(n1364), .A1(data_output[20]), .B0(n1363), .B1(n1132),
.C0(n1366), .C1(d_ff_Xn[20]), .Y(n1334) );
OAI33X4TS U1165 ( .A0(d_ff1_shift_region_flag_out[1]), .A1(n1172), .A2(n1504), .B0(n1497), .B1(n1495), .B2(n1173), .Y(n1327) );
INVX2TS U1166 ( .A(n1071), .Y(n1174) );
INVX2TS U1167 ( .A(n1070), .Y(n1175) );
AOI222X4TS U1168 ( .A0(n1318), .A1(d_ff2_Z[4]), .B0(n1300), .B1(d_ff1_Z[4]),
.C0(d_ff_Zn[4]), .C1(n1444), .Y(n1286) );
AOI222X4TS U1169 ( .A0(n1313), .A1(d_ff2_Z[10]), .B0(n1317), .B1(d_ff1_Z[10]), .C0(d_ff_Zn[10]), .C1(n1444), .Y(n1287) );
AOI222X4TS U1170 ( .A0(n1467), .A1(d_ff2_Z[9]), .B0(n1317), .B1(d_ff1_Z[9]),
.C0(d_ff_Zn[9]), .C1(n1444), .Y(n1291) );
AOI222X4TS U1171 ( .A0(n1318), .A1(d_ff2_Z[12]), .B0(n1317), .B1(d_ff1_Z[12]), .C0(d_ff_Zn[12]), .C1(n1444), .Y(n1294) );
AOI222X4TS U1172 ( .A0(n1318), .A1(d_ff2_Z[11]), .B0(n1317), .B1(d_ff1_Z[11]), .C0(d_ff_Zn[11]), .C1(n1444), .Y(n1295) );
BUFX4TS U1173 ( .A(n1463), .Y(n1444) );
BUFX4TS U1174 ( .A(n1449), .Y(n1442) );
CLKINVX3TS U1175 ( .A(n1416), .Y(n1415) );
NOR3X4TS U1176 ( .A(inst_CORDIC_FSM_v3_state_reg[5]), .B(n1498), .C(n1186),
.Y(enab_cont_iter) );
CLKINVX3TS U1177 ( .A(n1242), .Y(n1387) );
INVX2TS U1178 ( .A(n1484), .Y(n1176) );
CLKINVX3TS U1179 ( .A(n1484), .Y(n1477) );
INVX4TS U1180 ( .A(n1484), .Y(n1486) );
INVX2TS U1181 ( .A(n1069), .Y(n1177) );
AOI222X4TS U1182 ( .A0(n1318), .A1(d_ff2_Z[1]), .B0(n1317), .B1(d_ff1_Z[1]),
.C0(d_ff_Zn[1]), .C1(n1444), .Y(n1304) );
AOI222X4TS U1183 ( .A0(n1313), .A1(d_ff2_Z[2]), .B0(n1300), .B1(d_ff1_Z[2]),
.C0(d_ff_Zn[2]), .C1(n1444), .Y(n1283) );
AOI222X4TS U1184 ( .A0(n1467), .A1(d_ff2_Z[3]), .B0(n1300), .B1(d_ff1_Z[3]),
.C0(d_ff_Zn[3]), .C1(n1444), .Y(n1285) );
AOI222X4TS U1185 ( .A0(n1318), .A1(d_ff2_Z[5]), .B0(n1300), .B1(d_ff1_Z[5]),
.C0(d_ff_Zn[5]), .C1(n1444), .Y(n1284) );
AOI222X4TS U1186 ( .A0(n1318), .A1(d_ff2_Z[6]), .B0(n1317), .B1(d_ff1_Z[6]),
.C0(d_ff_Zn[6]), .C1(n1444), .Y(n1299) );
AOI222X4TS U1187 ( .A0(n1313), .A1(d_ff2_Z[7]), .B0(n1317), .B1(d_ff1_Z[7]),
.C0(d_ff_Zn[7]), .C1(n1444), .Y(n1297) );
AOI222X4TS U1188 ( .A0(n1467), .A1(d_ff2_Z[8]), .B0(n1317), .B1(d_ff1_Z[8]),
.C0(d_ff_Zn[8]), .C1(n1444), .Y(n1293) );
NOR2X2TS U1189 ( .A(n1439), .B(n1427), .Y(n1436) );
NOR2X2TS U1190 ( .A(cont_iter_out[3]), .B(intadd_365_B_1_), .Y(n1439) );
BUFX4TS U1191 ( .A(n1511), .Y(n1510) );
BUFX4TS U1192 ( .A(n1533), .Y(n1512) );
BUFX3TS U1193 ( .A(n1189), .Y(n1533) );
AOI222X4TS U1194 ( .A0(n1364), .A1(data_output[25]), .B0(n1363), .B1(n1128),
.C0(n1366), .C1(d_ff_Xn[25]), .Y(n1343) );
NOR4X2TS U1195 ( .A(inst_CORDIC_FSM_v3_state_reg[6]), .B(
inst_CORDIC_FSM_v3_state_reg[5]), .C(inst_CORDIC_FSM_v3_state_reg[3]),
.D(inst_CORDIC_FSM_v3_state_reg[0]), .Y(n1207) );
INVX4TS U1196 ( .A(n1412), .Y(n1411) );
CLKINVX3TS U1197 ( .A(n1416), .Y(n1418) );
NAND3X4TS U1198 ( .A(n1494), .B(n1493), .C(ready_add_subt), .Y(n1416) );
OAI21X2TS U1199 ( .A0(n1321), .A1(n1437), .B0(n1432), .Y(n1427) );
NOR3X4TS U1200 ( .A(n1392), .B(n1437), .C(n1499), .Y(n1393) );
BUFX4TS U1201 ( .A(n1463), .Y(n1443) );
BUFX4TS U1202 ( .A(n1466), .Y(n1463) );
BUFX4TS U1203 ( .A(n1326), .Y(n1363) );
BUFX4TS U1204 ( .A(n1326), .Y(n1367) );
BUFX4TS U1205 ( .A(n1218), .Y(n1265) );
BUFX4TS U1206 ( .A(n1218), .Y(n1390) );
AOI222X4TS U1207 ( .A0(n1467), .A1(d_ff2_Z[25]), .B0(n1317), .B1(d_ff1_Z[25]), .C0(d_ff_Zn[25]), .C1(n1443), .Y(n1311) );
AOI222X4TS U1208 ( .A0(n1467), .A1(d_ff2_Z[26]), .B0(n1317), .B1(d_ff1_Z[26]), .C0(d_ff_Zn[26]), .C1(n1463), .Y(n1312) );
INVX4TS U1209 ( .A(n1464), .Y(n1467) );
INVX4TS U1210 ( .A(n1402), .Y(n1407) );
INVX4TS U1211 ( .A(n1484), .Y(n1490) );
INVX2TS U1212 ( .A(d_ff3_LUT_out[13]), .Y(n1433) );
OAI21XLTS U1213 ( .A0(n1436), .A1(n1470), .B0(n1204), .Y(n821) );
OAI21XLTS U1214 ( .A0(n1114), .A1(n1178), .B0(n1231), .Y(add_subt_dataB[9])
);
OAI21XLTS U1215 ( .A0(n1242), .A1(n1503), .B0(n1228), .Y(add_subt_dataB[20])
);
OAI21XLTS U1216 ( .A0(n1226), .A1(n1502), .B0(n1225), .Y(add_subt_dataA[23])
);
NOR3BX1TS U1217 ( .AN(n1191), .B(inst_CORDIC_FSM_v3_state_reg[7]), .C(
inst_CORDIC_FSM_v3_state_reg[3]), .Y(n1205) );
NAND2BX1TS U1218 ( .AN(inst_CORDIC_FSM_v3_state_reg[0]), .B(n1205), .Y(n1186) );
NOR3BX1TS U1219 ( .AN(n1207), .B(inst_CORDIC_FSM_v3_state_reg[7]), .C(
inst_CORDIC_FSM_v3_state_reg[1]), .Y(n1184) );
BUFX3TS U1220 ( .A(n1455), .Y(n1508) );
NAND3X1TS U1221 ( .A(inst_CORDIC_FSM_v3_state_reg[7]), .B(n1207), .C(n1191),
.Y(n1375) );
INVX2TS U1222 ( .A(n1375), .Y(ready_cordic) );
NAND3BX1TS U1223 ( .AN(inst_CORDIC_FSM_v3_state_reg[2]), .B(
inst_CORDIC_FSM_v3_state_reg[4]), .C(n1184), .Y(n1372) );
NOR3BX2TS U1224 ( .AN(n1372), .B(enab_cont_iter), .C(ready_add_subt), .Y(
n1395) );
NAND2X1TS U1225 ( .A(cont_var_out[0]), .B(n1494), .Y(n1239) );
NAND2X1TS U1226 ( .A(cont_var_out[1]), .B(n1493), .Y(n1226) );
NAND2X1TS U1227 ( .A(n1395), .B(cont_var_out[1]), .Y(n1185) );
INVX2TS U1228 ( .A(enab_cont_iter), .Y(n1392) );
INVX2TS U1229 ( .A(n1507), .Y(n1320) );
NAND3BX1TS U1230 ( .AN(n1186), .B(inst_CORDIC_FSM_v3_state_reg[5]), .C(n1498), .Y(n1373) );
NAND2X1TS U1231 ( .A(n1372), .B(n1373), .Y(beg_add_subt) );
INVX2TS U1232 ( .A(rst), .Y(n281) );
BUFX3TS U1233 ( .A(n1525), .Y(n1528) );
BUFX3TS U1234 ( .A(n1525), .Y(n1527) );
BUFX3TS U1235 ( .A(n1190), .Y(n1517) );
BUFX3TS U1236 ( .A(n1190), .Y(n1524) );
BUFX3TS U1237 ( .A(n1525), .Y(n1526) );
BUFX3TS U1238 ( .A(n1190), .Y(n1521) );
BUFX3TS U1239 ( .A(n1189), .Y(n1509) );
BUFX3TS U1240 ( .A(n1187), .Y(n1511) );
BUFX3TS U1241 ( .A(n1190), .Y(n1514) );
BUFX3TS U1242 ( .A(n1509), .Y(n1513) );
NAND4BX1TS U1243 ( .AN(inst_CORDIC_FSM_v3_state_reg[7]), .B(
inst_CORDIC_FSM_v3_state_reg[3]), .C(n1192), .D(n1191), .Y(n1461) );
CLKBUFX2TS U1244 ( .A(n1461), .Y(n1481) );
BUFX3TS U1245 ( .A(n1481), .Y(n1484) );
NOR2X2TS U1246 ( .A(n1177), .B(n1437), .Y(n1472) );
NAND2X1TS U1247 ( .A(n1490), .B(n1437), .Y(n1440) );
INVX2TS U1248 ( .A(n1440), .Y(n1197) );
CLKBUFX2TS U1249 ( .A(n1484), .Y(n1449) );
AOI22X1TS U1250 ( .A0(n1197), .A1(n1177), .B0(d_ff3_sh_x_out[23]), .B1(n1442), .Y(n1193) );
OAI2BB1X1TS U1251 ( .A0N(n1492), .A1N(n1472), .B0(n1193), .Y(n649) );
BUFX3TS U1252 ( .A(n1466), .Y(n1446) );
BUFX3TS U1253 ( .A(n1466), .Y(n1457) );
INVX2TS U1254 ( .A(n1321), .Y(n1434) );
NAND2X1TS U1255 ( .A(n1320), .B(n1502), .Y(intadd_365_CI) );
AOI22X1TS U1256 ( .A0(d_ff2_Y[23]), .A1(n1197), .B0(d_ff3_sh_y_out[23]),
.B1(n1442), .Y(n1198) );
NAND2X2TS U1257 ( .A(n1486), .B(n1499), .Y(n1469) );
AOI21X1TS U1258 ( .A0(n1506), .A1(n1320), .B0(cont_iter_out[3]), .Y(n1214)
);
AOI22X1TS U1259 ( .A0(n1460), .A1(n1214), .B0(d_ff3_LUT_out[26]), .B1(n1442),
.Y(n1199) );
INVX2TS U1260 ( .A(n1439), .Y(n1216) );
NAND2X2TS U1261 ( .A(n1456), .B(cont_iter_out[1]), .Y(n1470) );
NOR3X1TS U1262 ( .A(n1506), .B(n1437), .C(n1470), .Y(n1201) );
AOI21X1TS U1263 ( .A0(d_ff3_LUT_out[2]), .A1(n1442), .B0(n1201), .Y(n1200)
);
OAI31X1TS U1264 ( .A0(cont_iter_out[3]), .A1(n1320), .A2(n1469), .B0(n1203),
.Y(n815) );
BUFX3TS U1265 ( .A(n1218), .Y(n1376) );
NAND2X1TS U1266 ( .A(n1376), .B(ready_add_subt), .Y(n1404) );
AOI211X1TS U1267 ( .A0(n1320), .A1(n1496), .B0(n1506), .C0(n1469), .Y(n1430)
);
AOI21X1TS U1268 ( .A0(d_ff3_LUT_out[0]), .A1(n1484), .B0(n1430), .Y(n1204)
);
NOR2XLTS U1269 ( .A(inst_CORDIC_FSM_v3_state_reg[6]), .B(
inst_CORDIC_FSM_v3_state_reg[5]), .Y(n1206) );
NAND3X1TS U1270 ( .A(n1206), .B(inst_CORDIC_FSM_v3_state_reg[0]), .C(n1205),
.Y(n1370) );
NOR4BX1TS U1271 ( .AN(inst_CORDIC_FSM_v3_state_reg[1]), .B(
inst_CORDIC_FSM_v3_state_reg[2]), .C(inst_CORDIC_FSM_v3_state_reg[4]),
.D(n1208), .Y(n1371) );
NOR2BX1TS U1272 ( .AN(n1370), .B(n1118), .Y(n1209) );
NOR4X1TS U1273 ( .A(enab_cont_iter), .B(n1477), .C(n1508), .D(beg_add_subt),
.Y(n1210) );
AOI32X1TS U1274 ( .A0(n1396), .A1(n1375), .A2(n1210), .B0(ready_cordic),
.B1(ack_cordic), .Y(n1211) );
OAI2BB1X1TS U1275 ( .A0N(n1432), .A1N(n1216), .B0(n1492), .Y(n1421) );
INVX2TS U1276 ( .A(n1470), .Y(n1428) );
NAND2X1TS U1277 ( .A(n1428), .B(n1434), .Y(n1435) );
INVX2TS U1278 ( .A(n1469), .Y(n1423) );
NAND2X1TS U1279 ( .A(n1320), .B(n1434), .Y(n1212) );
AOI22X1TS U1280 ( .A0(n1423), .A1(n1212), .B0(d_ff3_LUT_out[24]), .B1(n1442),
.Y(n1213) );
AOI22X1TS U1281 ( .A0(n1214), .A1(n1423), .B0(d_ff3_LUT_out[4]), .B1(n1442),
.Y(n1215) );
NAND2X1TS U1282 ( .A(n1423), .B(n1434), .Y(n1217) );
NAND2X1TS U1283 ( .A(n1428), .B(n1425), .Y(n1431) );
BUFX3TS U1284 ( .A(n1218), .Y(n1250) );
AOI22X1TS U1285 ( .A0(n1250), .A1(d_ff3_sh_x_out[16]), .B0(n1408), .B1(
d_ff3_sh_y_out[16]), .Y(n1219) );
OAI21XLTS U1286 ( .A0(n1242), .A1(n1235), .B0(n1219), .Y(add_subt_dataB[16])
);
BUFX3TS U1287 ( .A(n1223), .Y(n1268) );
INVX2TS U1288 ( .A(n1220), .Y(add_subt_dataA[18]) );
INVX2TS U1289 ( .A(n1221), .Y(add_subt_dataA[0]) );
INVX2TS U1290 ( .A(n1222), .Y(add_subt_dataA[17]) );
BUFX3TS U1291 ( .A(n1223), .Y(n1384) );
AOI22X1TS U1292 ( .A0(n1384), .A1(d_ff3_sh_y_out[29]), .B0(n1263), .B1(
d_ff3_LUT_out[27]), .Y(n1224) );
OAI21XLTS U1293 ( .A0(n1226), .A1(n1179), .B0(n1224), .Y(add_subt_dataB[29])
);
AOI22X1TS U1294 ( .A0(n1384), .A1(n1177), .B0(d_ff2_Z[23]), .B1(n1263), .Y(
n1225) );
AOI22X1TS U1295 ( .A0(n1265), .A1(d_ff3_sh_x_out[18]), .B0(n1384), .B1(
d_ff3_sh_y_out[18]), .Y(n1227) );
OAI21XLTS U1296 ( .A0(n1242), .A1(n1433), .B0(n1227), .Y(add_subt_dataB[18])
);
AOI22X1TS U1297 ( .A0(n1218), .A1(d_ff3_sh_x_out[20]), .B0(n1384), .B1(
d_ff3_sh_y_out[20]), .Y(n1228) );
AOI22X1TS U1298 ( .A0(n1265), .A1(d_ff3_sh_x_out[21]), .B0(n1384), .B1(
d_ff3_sh_y_out[21]), .Y(n1229) );
OAI21XLTS U1299 ( .A0(n1242), .A1(n1181), .B0(n1229), .Y(add_subt_dataB[21])
);
AOI22X1TS U1300 ( .A0(n1390), .A1(d_ff3_sh_x_out[15]), .B0(n1384), .B1(
d_ff3_sh_y_out[15]), .Y(n1230) );
OAI21XLTS U1301 ( .A0(n1242), .A1(n1503), .B0(n1230), .Y(add_subt_dataB[15])
);
AOI22X1TS U1302 ( .A0(n1390), .A1(d_ff3_sh_x_out[9]), .B0(n1384), .B1(
d_ff3_sh_y_out[9]), .Y(n1231) );
AOI22X1TS U1303 ( .A0(n1390), .A1(d_ff3_sh_x_out[12]), .B0(n1384), .B1(
d_ff3_sh_y_out[12]), .Y(n1232) );
OAI21XLTS U1304 ( .A0(n1114), .A1(n1180), .B0(n1232), .Y(add_subt_dataB[12])
);
AOI22X1TS U1305 ( .A0(n1390), .A1(d_ff3_sh_x_out[17]), .B0(n1408), .B1(
d_ff3_sh_y_out[17]), .Y(n1233) );
OAI21XLTS U1306 ( .A0(n1114), .A1(n1503), .B0(n1233), .Y(add_subt_dataB[17])
);
AOI22X1TS U1307 ( .A0(n1390), .A1(d_ff3_sh_x_out[3]), .B0(n1408), .B1(
d_ff3_sh_y_out[3]), .Y(n1234) );
OAI21XLTS U1308 ( .A0(n1114), .A1(n1235), .B0(n1234), .Y(add_subt_dataB[3])
);
AOI22X1TS U1309 ( .A0(n1390), .A1(d_ff3_sh_x_out[13]), .B0(n1408), .B1(
d_ff3_sh_y_out[13]), .Y(n1236) );
OAI21XLTS U1310 ( .A0(n1114), .A1(n1433), .B0(n1236), .Y(add_subt_dataB[13])
);
AOI22X1TS U1311 ( .A0(n1390), .A1(d_ff2_Y[24]), .B0(d_ff2_Z[24]), .B1(n1263),
.Y(n1237) );
OAI21XLTS U1312 ( .A0(n1239), .A1(n1500), .B0(n1237), .Y(add_subt_dataA[24])
);
AOI22X1TS U1313 ( .A0(n1390), .A1(d_ff2_Y[28]), .B0(d_ff2_Z[28]), .B1(n1263),
.Y(n1238) );
OAI21XLTS U1314 ( .A0(n1239), .A1(n1501), .B0(n1238), .Y(add_subt_dataA[28])
);
BUFX3TS U1315 ( .A(n1408), .Y(n1273) );
INVX2TS U1316 ( .A(n1240), .Y(add_subt_dataA[31]) );
INVX2TS U1317 ( .A(n1241), .Y(add_subt_dataA[26]) );
INVX2TS U1318 ( .A(n1243), .Y(add_subt_dataB[0]) );
INVX2TS U1319 ( .A(n1244), .Y(add_subt_dataA[25]) );
INVX2TS U1320 ( .A(n1245), .Y(add_subt_dataB[2]) );
INVX2TS U1321 ( .A(n1246), .Y(add_subt_dataB[1]) );
INVX2TS U1322 ( .A(n1247), .Y(add_subt_dataA[20]) );
INVX2TS U1323 ( .A(n1248), .Y(add_subt_dataA[19]) );
INVX2TS U1324 ( .A(n1249), .Y(add_subt_dataA[22]) );
INVX2TS U1325 ( .A(n1251), .Y(add_subt_dataA[21]) );
INVX2TS U1326 ( .A(n1252), .Y(add_subt_dataA[3]) );
INVX2TS U1327 ( .A(n1253), .Y(add_subt_dataA[15]) );
INVX2TS U1328 ( .A(n1254), .Y(add_subt_dataA[4]) );
INVX2TS U1329 ( .A(n1255), .Y(add_subt_dataA[14]) );
INVX2TS U1330 ( .A(n1256), .Y(add_subt_dataA[12]) );
INVX2TS U1331 ( .A(n1257), .Y(add_subt_dataA[10]) );
INVX2TS U1332 ( .A(n1258), .Y(add_subt_dataA[9]) );
INVX2TS U1333 ( .A(n1259), .Y(add_subt_dataA[13]) );
INVX2TS U1334 ( .A(n1260), .Y(add_subt_dataA[7]) );
INVX2TS U1335 ( .A(n1261), .Y(add_subt_dataA[8]) );
INVX2TS U1336 ( .A(n1262), .Y(add_subt_dataA[11]) );
INVX2TS U1337 ( .A(n1264), .Y(add_subt_dataA[16]) );
INVX2TS U1338 ( .A(n1266), .Y(add_subt_dataA[2]) );
INVX2TS U1339 ( .A(n1267), .Y(add_subt_dataA[1]) );
INVX2TS U1340 ( .A(n1269), .Y(add_subt_dataA[5]) );
INVX2TS U1341 ( .A(n1270), .Y(add_subt_dataA[6]) );
INVX2TS U1342 ( .A(n1271), .Y(add_subt_dataB[6]) );
INVX2TS U1343 ( .A(n1272), .Y(add_subt_dataB[23]) );
INVX2TS U1344 ( .A(n1274), .Y(add_subt_dataB[4]) );
INVX2TS U1345 ( .A(n1275), .Y(add_subt_dataB[25]) );
AOI222X1TS U1346 ( .A0(n1376), .A1(d_ff3_sh_x_out[8]), .B0(n1223), .B1(
d_ff3_sh_y_out[8]), .C0(n1276), .C1(d_ff3_LUT_out[8]), .Y(n1277) );
INVX2TS U1347 ( .A(n1277), .Y(add_subt_dataB[8]) );
INVX2TS U1348 ( .A(n1278), .Y(add_subt_dataB[24]) );
INVX2TS U1349 ( .A(n1279), .Y(add_subt_dataB[26]) );
INVX2TS U1350 ( .A(n1280), .Y(add_subt_dataB[10]) );
INVX4TS U1351 ( .A(n1464), .Y(n1318) );
CLKBUFX2TS U1352 ( .A(n1282), .Y(n1300) );
INVX2TS U1353 ( .A(n1283), .Y(n798) );
INVX2TS U1354 ( .A(n1284), .Y(n795) );
INVX2TS U1355 ( .A(n1285), .Y(n797) );
INVX2TS U1356 ( .A(n1286), .Y(n796) );
INVX2TS U1357 ( .A(n1287), .Y(n790) );
INVX4TS U1358 ( .A(n1464), .Y(n1313) );
INVX2TS U1359 ( .A(n1288), .Y(n784) );
INVX2TS U1360 ( .A(n1289), .Y(n787) );
INVX2TS U1361 ( .A(n1290), .Y(n785) );
INVX2TS U1362 ( .A(n1291), .Y(n791) );
INVX2TS U1363 ( .A(n1292), .Y(n782) );
INVX2TS U1364 ( .A(n1293), .Y(n792) );
INVX2TS U1365 ( .A(n1294), .Y(n788) );
INVX2TS U1366 ( .A(n1295), .Y(n789) );
INVX2TS U1367 ( .A(n1296), .Y(n786) );
INVX2TS U1368 ( .A(n1297), .Y(n793) );
AOI222X1TS U1369 ( .A0(n1467), .A1(d_ff2_Z[17]), .B0(n1317), .B1(d_ff1_Z[17]), .C0(d_ff_Zn[17]), .C1(n1443), .Y(n1298) );
INVX2TS U1370 ( .A(n1298), .Y(n783) );
INVX2TS U1371 ( .A(n1299), .Y(n794) );
INVX2TS U1372 ( .A(n1301), .Y(n781) );
AOI222X1TS U1373 ( .A0(n1313), .A1(d_ff2_Z[24]), .B0(n1315), .B1(d_ff1_Z[24]), .C0(d_ff_Zn[24]), .C1(n1443), .Y(n1302) );
INVX2TS U1374 ( .A(n1302), .Y(n776) );
INVX2TS U1375 ( .A(n1303), .Y(n771) );
INVX2TS U1376 ( .A(n1304), .Y(n799) );
INVX2TS U1377 ( .A(n1305), .Y(n780) );
INVX2TS U1378 ( .A(n1306), .Y(n777) );
INVX2TS U1379 ( .A(n1307), .Y(n772) );
INVX2TS U1380 ( .A(n1308), .Y(n778) );
INVX2TS U1381 ( .A(n1309), .Y(n773) );
INVX2TS U1382 ( .A(n1310), .Y(n769) );
INVX2TS U1383 ( .A(n1311), .Y(n775) );
INVX2TS U1384 ( .A(n1312), .Y(n774) );
INVX2TS U1385 ( .A(n1314), .Y(n779) );
INVX2TS U1386 ( .A(n1316), .Y(n770) );
INVX2TS U1387 ( .A(n1319), .Y(n800) );
XNOR2X1TS U1388 ( .A(n1327), .B(d_ff_Xn[31]), .Y(n1330) );
NAND3X1TS U1389 ( .A(n1321), .B(n1320), .C(cont_iter_out[1]), .Y(n1374) );
BUFX3TS U1390 ( .A(n1323), .Y(n1368) );
BUFX3TS U1391 ( .A(n1368), .Y(n1364) );
XNOR2X1TS U1392 ( .A(d_ff1_shift_region_flag_out[1]), .B(n1172), .Y(n1324)
);
XNOR2X1TS U1393 ( .A(n1173), .B(n1324), .Y(n1325) );
NOR2X1TS U1394 ( .A(n1364), .B(n1325), .Y(n1331) );
INVX2TS U1395 ( .A(n1331), .Y(n1337) );
XOR2XLTS U1396 ( .A(d_ff_Yn_31_), .B(n1327), .Y(n1328) );
AOI22X1TS U1397 ( .A0(n1364), .A1(data_output[31]), .B0(n1363), .B1(n1328),
.Y(n1329) );
INVX2TS U1398 ( .A(n1332), .Y(n847) );
INVX4TS U1399 ( .A(n1337), .Y(n1366) );
INVX2TS U1400 ( .A(n1333), .Y(n825) );
INVX2TS U1401 ( .A(n1334), .Y(n833) );
INVX2TS U1402 ( .A(n1335), .Y(n823) );
INVX2TS U1403 ( .A(n1336), .Y(n834) );
INVX4TS U1404 ( .A(n1337), .Y(n1360) );
INVX2TS U1405 ( .A(n1338), .Y(n835) );
INVX2TS U1406 ( .A(n1339), .Y(n832) );
INVX2TS U1407 ( .A(n1340), .Y(n837) );
INVX2TS U1408 ( .A(n1341), .Y(n838) );
INVX2TS U1409 ( .A(n1342), .Y(n839) );
INVX2TS U1410 ( .A(n1343), .Y(n828) );
INVX2TS U1411 ( .A(n1344), .Y(n829) );
INVX2TS U1412 ( .A(n1345), .Y(n830) );
INVX2TS U1413 ( .A(n1346), .Y(n836) );
INVX2TS U1414 ( .A(n1347), .Y(n843) );
INVX2TS U1415 ( .A(n1348), .Y(n844) );
INVX2TS U1416 ( .A(n1349), .Y(n845) );
INVX2TS U1417 ( .A(n1350), .Y(n846) );
INVX2TS U1418 ( .A(n1351), .Y(n824) );
INVX2TS U1419 ( .A(n1352), .Y(n848) );
INVX2TS U1420 ( .A(n1353), .Y(n849) );
INVX2TS U1421 ( .A(n1354), .Y(n850) );
INVX2TS U1422 ( .A(n1355), .Y(n851) );
INVX2TS U1423 ( .A(n1356), .Y(n852) );
INVX2TS U1424 ( .A(n1357), .Y(n826) );
INVX2TS U1425 ( .A(n1358), .Y(n842) );
INVX2TS U1426 ( .A(n1359), .Y(n840) );
INVX2TS U1427 ( .A(n1361), .Y(n841) );
INVX2TS U1428 ( .A(n1362), .Y(n831) );
INVX2TS U1429 ( .A(n1365), .Y(n827) );
INVX2TS U1430 ( .A(n1369), .Y(n853) );
NOR2BX1TS U1431 ( .AN(beg_fsm_cordic), .B(n1370), .Y(
inst_CORDIC_FSM_v3_state_next[1]) );
AO21XLTS U1432 ( .A0(enab_cont_iter), .A1(n1374), .B0(n1118), .Y(
inst_CORDIC_FSM_v3_state_next[2]) );
OAI22X1TS U1433 ( .A0(n1407), .A1(n1373), .B0(n1372), .B1(n1114), .Y(
inst_CORDIC_FSM_v3_state_next[5]) );
OAI22X1TS U1434 ( .A0(ack_cordic), .A1(n1375), .B0(n1392), .B1(n1374), .Y(
inst_CORDIC_FSM_v3_state_next[7]) );
AOI2BB2XLTS U1435 ( .B0(cont_var_out[0]), .B1(d_ff3_sign_out), .A0N(
d_ff3_sign_out), .A1N(cont_var_out[0]), .Y(op_add_subt) );
AO22XLTS U1436 ( .A0(n1376), .A1(d_ff3_sh_x_out[31]), .B0(n1223), .B1(
d_ff3_sh_y_out[31]), .Y(add_subt_dataB[31]) );
AO22XLTS U1437 ( .A0(n1376), .A1(d_ff3_sh_x_out[30]), .B0(n1223), .B1(
d_ff3_sh_y_out[30]), .Y(add_subt_dataB[30]) );
AOI22X1TS U1438 ( .A0(n1218), .A1(d_ff3_sh_x_out[28]), .B0(n1384), .B1(
d_ff3_sh_y_out[28]), .Y(n1377) );
NAND2X1TS U1439 ( .A(n1263), .B(d_ff3_LUT_out[27]), .Y(n1378) );
NAND2X1TS U1440 ( .A(n1377), .B(n1378), .Y(add_subt_dataB[28]) );
AOI22X1TS U1441 ( .A0(n1218), .A1(d_ff3_sh_x_out[27]), .B0(n1384), .B1(
d_ff3_sh_y_out[27]), .Y(n1379) );
NAND2X1TS U1442 ( .A(n1379), .B(n1378), .Y(add_subt_dataB[27]) );
AOI22X1TS U1443 ( .A0(n1218), .A1(d_ff3_sh_x_out[22]), .B0(n1384), .B1(
d_ff3_sh_y_out[22]), .Y(n1380) );
OAI2BB1X1TS U1444 ( .A0N(n1387), .A1N(d_ff3_LUT_out[19]), .B0(n1380), .Y(
add_subt_dataB[22]) );
AOI22X1TS U1445 ( .A0(n1218), .A1(d_ff3_sh_x_out[19]), .B0(n1384), .B1(
d_ff3_sh_y_out[19]), .Y(n1381) );
OAI2BB1X1TS U1446 ( .A0N(n1116), .A1N(d_ff3_LUT_out[19]), .B0(n1381), .Y(
add_subt_dataB[19]) );
AOI22X1TS U1447 ( .A0(n1218), .A1(d_ff3_sh_x_out[14]), .B0(n1408), .B1(
d_ff3_sh_y_out[14]), .Y(n1382) );
OAI2BB1X1TS U1448 ( .A0N(n1116), .A1N(d_ff3_LUT_out[5]), .B0(n1382), .Y(
add_subt_dataB[14]) );
AOI22X1TS U1449 ( .A0(n1218), .A1(d_ff3_sh_x_out[11]), .B0(n1408), .B1(
d_ff3_sh_y_out[11]), .Y(n1383) );
OAI2BB1X1TS U1450 ( .A0N(n1387), .A1N(d_ff3_LUT_out[7]), .B0(n1383), .Y(
add_subt_dataB[11]) );
AOI22X1TS U1451 ( .A0(n1390), .A1(d_ff3_sh_x_out[7]), .B0(n1384), .B1(
d_ff3_sh_y_out[7]), .Y(n1385) );
OAI2BB1X1TS U1452 ( .A0N(n1116), .A1N(d_ff3_LUT_out[7]), .B0(n1385), .Y(
add_subt_dataB[7]) );
AOI22X1TS U1453 ( .A0(n1218), .A1(d_ff3_sh_x_out[5]), .B0(n1408), .B1(
d_ff3_sh_y_out[5]), .Y(n1386) );
OAI2BB1X1TS U1454 ( .A0N(n1116), .A1N(d_ff3_LUT_out[5]), .B0(n1386), .Y(
add_subt_dataB[5]) );
AOI22X1TS U1455 ( .A0(n1218), .A1(d_ff2_Y[30]), .B0(d_ff2_Z[30]), .B1(n1263),
.Y(n1388) );
OAI2BB1X1TS U1456 ( .A0N(n1223), .A1N(n1171), .B0(n1388), .Y(
add_subt_dataA[30]) );
AOI22X1TS U1457 ( .A0(n1390), .A1(d_ff2_Y[29]), .B0(d_ff2_Z[29]), .B1(n1263),
.Y(n1389) );
OAI2BB1X1TS U1458 ( .A0N(n1223), .A1N(d_ff2_X[29]), .B0(n1389), .Y(
add_subt_dataA[29]) );
AOI22X1TS U1459 ( .A0(n1390), .A1(d_ff2_Y[27]), .B0(d_ff2_Z[27]), .B1(n1263),
.Y(n1391) );
OAI2BB1X1TS U1460 ( .A0N(n1223), .A1N(d_ff2_X[27]), .B0(n1391), .Y(
add_subt_dataA[27]) );
AOI22X1TS U1461 ( .A0(enab_cont_iter), .A1(n1182), .B0(n1437), .B1(n1392),
.Y(n989) );
NAND2X1TS U1462 ( .A(n1506), .B(n1393), .Y(n1394) );
XNOR2X1TS U1463 ( .A(cont_iter_out[3]), .B(n1394), .Y(n986) );
BUFX3TS U1464 ( .A(n1397), .Y(n1398) );
BUFX3TS U1465 ( .A(n1398), .Y(n1400) );
INVX2TS U1466 ( .A(n1398), .Y(n1401) );
INVX2TS U1467 ( .A(n1402), .Y(n1405) );
INVX2TS U1468 ( .A(n1402), .Y(n1403) );
BUFX3TS U1469 ( .A(n1056), .Y(n1406) );
NAND2X1TS U1470 ( .A(n1408), .B(ready_add_subt), .Y(n1410) );
INVX2TS U1471 ( .A(n1412), .Y(n1409) );
BUFX3TS U1472 ( .A(n1057), .Y(n1413) );
INVX2TS U1473 ( .A(n1412), .Y(n1414) );
BUFX3TS U1474 ( .A(n1419), .Y(n1417) );
INVX2TS U1475 ( .A(n1419), .Y(n1420) );
AOI22X1TS U1476 ( .A0(n1423), .A1(n1425), .B0(d_ff3_LUT_out[1]), .B1(n1442),
.Y(n1422) );
NAND2X1TS U1477 ( .A(n1422), .B(n1421), .Y(n820) );
AOI22X1TS U1478 ( .A0(n1423), .A1(n1427), .B0(d_ff3_LUT_out[5]), .B1(n1449),
.Y(n1424) );
NAND2X1TS U1479 ( .A(n1424), .B(n1431), .Y(n816) );
AOI22X1TS U1480 ( .A0(n1460), .A1(n1425), .B0(d_ff3_LUT_out[7]), .B1(n1442),
.Y(n1426) );
NAND2X1TS U1481 ( .A(n1426), .B(n1435), .Y(n814) );
AOI22X1TS U1482 ( .A0(n1428), .A1(n1427), .B0(d_ff3_LUT_out[10]), .B1(n1449),
.Y(n1429) );
OAI221XLTS U1483 ( .A0(n1460), .A1(n1180), .B0(n1461), .B1(n1432), .C0(n1431), .Y(n810) );
AOI22X1TS U1484 ( .A0(n1176), .A1(n1436), .B0(n1433), .B1(n1442), .Y(n809)
);
BUFX3TS U1485 ( .A(n1449), .Y(n1458) );
OAI221XLTS U1486 ( .A0(n1477), .A1(n1181), .B0(n1481), .B1(n1436), .C0(n1435), .Y(n806) );
AOI22X1TS U1487 ( .A0(n1439), .A1(n1438), .B0(d_ff3_LUT_out[25]), .B1(n1442),
.Y(n1441) );
AOI32X1TS U1488 ( .A0(n1469), .A1(n1441), .A2(n1440), .B0(n1506), .B1(n1441),
.Y(n803) );
BUFX3TS U1489 ( .A(n1481), .Y(n1488) );
INVX2TS U1490 ( .A(n1455), .Y(n1445) );
INVX2TS U1491 ( .A(n1484), .Y(n1460) );
INVX2TS U1492 ( .A(n1484), .Y(n1492) );
BUFX3TS U1493 ( .A(n1449), .Y(n1459) );
INVX2TS U1494 ( .A(n1464), .Y(n1462) );
NOR2X1TS U1495 ( .A(d_ff2_Y[27]), .B(intadd_365_n1), .Y(n1448) );
AOI21X1TS U1496 ( .A0(intadd_365_n1), .A1(d_ff2_Y[27]), .B0(n1448), .Y(n1447) );
OR3X1TS U1497 ( .A(d_ff2_Y[27]), .B(d_ff2_Y[28]), .C(intadd_365_n1), .Y(
n1451) );
BUFX3TS U1498 ( .A(n1449), .Y(n1491) );
NOR2X1TS U1499 ( .A(d_ff2_Y[29]), .B(n1451), .Y(n1453) );
AOI21X1TS U1500 ( .A0(d_ff2_Y[29]), .A1(n1451), .B0(n1453), .Y(n1452) );
OA22X1TS U1501 ( .A0(d_ff_Xn[1]), .A1(n1194), .B0(n1455), .B1(d_ff2_X[1]),
.Y(n701) );
OA22X1TS U1502 ( .A0(d_ff_Xn[2]), .A1(n1194), .B0(n1464), .B1(d_ff2_X[2]),
.Y(n699) );
OA22X1TS U1503 ( .A0(d_ff_Xn[3]), .A1(n1194), .B0(n1455), .B1(d_ff2_X[3]),
.Y(n697) );
OA22X1TS U1504 ( .A0(d_ff_Xn[5]), .A1(n1117), .B0(n1455), .B1(n1159), .Y(
n693) );
OA22X1TS U1505 ( .A0(d_ff_Xn[6]), .A1(n1117), .B0(n1508), .B1(n1158), .Y(
n691) );
OA22X1TS U1506 ( .A0(d_ff_Xn[7]), .A1(n1117), .B0(n1508), .B1(n1157), .Y(
n689) );
OA22X1TS U1507 ( .A0(d_ff_Xn[10]), .A1(n1194), .B0(n1508), .B1(d_ff2_X[10]),
.Y(n683) );
OA22X1TS U1508 ( .A0(n1164), .A1(n1194), .B0(n1508), .B1(d_ff2_X[12]), .Y(
n679) );
OA22X1TS U1509 ( .A0(n1163), .A1(n1194), .B0(n1508), .B1(d_ff2_X[13]), .Y(
n677) );
OA22X1TS U1510 ( .A0(n1162), .A1(n1194), .B0(n1508), .B1(d_ff2_X[14]), .Y(
n675) );
OA22X1TS U1511 ( .A0(n1161), .A1(n1194), .B0(n1508), .B1(d_ff2_X[16]), .Y(
n671) );
OA22X1TS U1512 ( .A0(n1160), .A1(n1194), .B0(n1464), .B1(d_ff2_X[17]), .Y(
n669) );
OA22X1TS U1513 ( .A0(d_ff_Xn[19]), .A1(n1117), .B0(n1464), .B1(d_ff2_X[19]),
.Y(n665) );
OA22X1TS U1514 ( .A0(d_ff_Xn[20]), .A1(n1117), .B0(n1464), .B1(d_ff2_X[20]),
.Y(n663) );
OA22X1TS U1515 ( .A0(n1508), .A1(d_ff2_X[24]), .B0(d_ff_Xn[24]), .B1(n1194),
.Y(n656) );
OA22X1TS U1516 ( .A0(d_ff_Xn[25]), .A1(n1117), .B0(n1455), .B1(n1175), .Y(
n655) );
OA22X1TS U1517 ( .A0(d_ff_Xn[26]), .A1(n1117), .B0(n1508), .B1(n1174), .Y(
n654) );
OA22X1TS U1518 ( .A0(n1508), .A1(d_ff2_X[27]), .B0(d_ff_Xn[27]), .B1(n1194),
.Y(n653) );
OA22X1TS U1519 ( .A0(n1464), .A1(d_ff2_X[28]), .B0(d_ff_Xn[28]), .B1(n1194),
.Y(n652) );
OA22X1TS U1520 ( .A0(n1455), .A1(d_ff2_X[29]), .B0(d_ff_Xn[29]), .B1(n1194),
.Y(n651) );
XOR2X1TS U1521 ( .A(n1472), .B(d_ff2_X[24]), .Y(n1468) );
MXI2X1TS U1522 ( .A(n1470), .B(n1469), .S0(n1468), .Y(n1471) );
AOI222X1TS U1523 ( .A0(cont_iter_out[1]), .A1(n1472), .B0(cont_iter_out[1]),
.B1(n1500), .C0(n1472), .C1(n1500), .Y(n1474) );
CMPR32X2TS U1524 ( .A(intadd_365_B_1_), .B(n1175), .C(n1474), .CO(n1476),
.S(n1473) );
CMPR32X2TS U1525 ( .A(n1496), .B(n1174), .C(n1476), .CO(n1479), .S(n1475) );
NOR2X1TS U1526 ( .A(d_ff2_X[27]), .B(n1479), .Y(n1480) );
AOI21X1TS U1527 ( .A0(n1479), .A1(d_ff2_X[27]), .B0(n1480), .Y(n1478) );
OR3X1TS U1528 ( .A(n1479), .B(d_ff2_X[27]), .C(d_ff2_X[28]), .Y(n1483) );
NOR2X1TS U1529 ( .A(d_ff2_X[29]), .B(n1483), .Y(n1487) );
AOI21X1TS U1530 ( .A0(d_ff2_X[29]), .A1(n1483), .B0(n1487), .Y(n1485) );
AOI22X1TS U1531 ( .A0(n1492), .A1(n1485), .B0(n1179), .B1(n1484), .Y(n643)
);
initial $sdf_annotate("CORDIC_Arch3v1_ASIC_fpu_syn_constraints_clk20.tcl_syn.sdf");
endmodule |
module system_util_vector_logic_0_0(Op1, Op2, Res)
/* synthesis syn_black_box black_box_pad_pin="Op1[0:0],Op2[0:0],Res[0:0]" */;
input [0:0]Op1;
input [0:0]Op2;
output [0:0]Res;
endmodule |
module MMCME4_BASE #(
`ifdef XIL_TIMING
parameter LOC = "UNPLACED",
`endif
parameter BANDWIDTH = "OPTIMIZED",
parameter real CLKFBOUT_MULT_F = 5.000,
parameter real CLKFBOUT_PHASE = 0.000,
parameter real CLKIN1_PERIOD = 0.000,
parameter real CLKOUT0_DIVIDE_F = 1.000,
parameter real CLKOUT0_DUTY_CYCLE = 0.500,
parameter real CLKOUT0_PHASE = 0.000,
parameter integer CLKOUT1_DIVIDE = 1,
parameter real CLKOUT1_DUTY_CYCLE = 0.500,
parameter real CLKOUT1_PHASE = 0.000,
parameter integer CLKOUT2_DIVIDE = 1,
parameter real CLKOUT2_DUTY_CYCLE = 0.500,
parameter real CLKOUT2_PHASE = 0.000,
parameter integer CLKOUT3_DIVIDE = 1,
parameter real CLKOUT3_DUTY_CYCLE = 0.500,
parameter real CLKOUT3_PHASE = 0.000,
parameter CLKOUT4_CASCADE = "FALSE",
parameter integer CLKOUT4_DIVIDE = 1,
parameter real CLKOUT4_DUTY_CYCLE = 0.500,
parameter real CLKOUT4_PHASE = 0.000,
parameter integer CLKOUT5_DIVIDE = 1,
parameter real CLKOUT5_DUTY_CYCLE = 0.500,
parameter real CLKOUT5_PHASE = 0.000,
parameter integer CLKOUT6_DIVIDE = 1,
parameter real CLKOUT6_DUTY_CYCLE = 0.500,
parameter real CLKOUT6_PHASE = 0.000,
parameter integer DIVCLK_DIVIDE = 1,
parameter [0:0] IS_CLKFBIN_INVERTED = 1'b0,
parameter [0:0] IS_CLKIN1_INVERTED = 1'b0,
parameter [0:0] IS_PWRDWN_INVERTED = 1'b0,
parameter [0:0] IS_RST_INVERTED = 1'b0,
parameter real REF_JITTER1 = 0.010,
parameter STARTUP_WAIT = "FALSE"
)(
output CLKFBOUT,
output CLKFBOUTB,
output CLKOUT0,
output CLKOUT0B,
output CLKOUT1,
output CLKOUT1B,
output CLKOUT2,
output CLKOUT2B,
output CLKOUT3,
output CLKOUT3B,
output CLKOUT4,
output CLKOUT5,
output CLKOUT6,
output LOCKED,
input CLKFBIN,
input CLKIN1,
input PWRDWN,
input RST
);
// define constants
localparam MODULE_NAME = "MMCME4_BASE";
reg trig_attr = 1'b0;
localparam [0:0] IS_CLKFBIN_INVERTED_REG = IS_CLKFBIN_INVERTED;
localparam [0:0] IS_CLKIN1_INVERTED_REG = IS_CLKIN1_INVERTED;
localparam [0:0] IS_PWRDWN_INVERTED_REG = IS_PWRDWN_INVERTED;
localparam [0:0] IS_RST_INVERTED_REG = IS_RST_INVERTED;
`ifdef XIL_ATTR_TEST
reg attr_test = 1'b1;
`else
reg attr_test = 1'b0;
`endif
reg attr_err = 1'b0;
wire CLKFBIN_in;
wire CLKIN1_in;
wire PWRDWN_in;
wire RST_in;
assign CLKFBIN_in = (CLKFBIN !== 1'bz) && (CLKFBIN ^ IS_CLKFBIN_INVERTED_REG); // rv 0
assign CLKIN1_in = (CLKIN1 !== 1'bz) && (CLKIN1 ^ IS_CLKIN1_INVERTED_REG); // rv 0
assign PWRDWN_in = (PWRDWN !== 1'bz) && (PWRDWN ^ IS_PWRDWN_INVERTED_REG); // rv 0
assign RST_in = (RST !== 1'bz) && (RST ^ IS_RST_INVERTED_REG); // rv 0
initial begin
#1;
trig_attr = ~trig_attr;
end
`ifndef XIL_XECLIB
always @ (trig_attr) begin
#1;
if ((attr_test == 1'b1) ||
((IS_CLKFBIN_INVERTED_REG !== 1'b0) && (IS_CLKFBIN_INVERTED_REG !== 1'b1))) begin
$display("Error: [Unisim %s-142] IS_CLKFBIN_INVERTED attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, IS_CLKFBIN_INVERTED_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((IS_CLKIN1_INVERTED_REG !== 1'b0) && (IS_CLKIN1_INVERTED_REG !== 1'b1))) begin
$display("Error: [Unisim %s-143] IS_CLKIN1_INVERTED attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, IS_CLKIN1_INVERTED_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((IS_PWRDWN_INVERTED_REG !== 1'b0) && (IS_PWRDWN_INVERTED_REG !== 1'b1))) begin
$display("Error: [Unisim %s-148] IS_PWRDWN_INVERTED attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, IS_PWRDWN_INVERTED_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((IS_RST_INVERTED_REG !== 1'b0) && (IS_RST_INVERTED_REG !== 1'b1))) begin
$display("Error: [Unisim %s-149] IS_RST_INVERTED attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, IS_RST_INVERTED_REG);
attr_err = 1'b1;
end
if (attr_err == 1'b1) #1 $finish;
end
`endif
`ifndef XIL_XECLIB
initial begin
#1;
if ($realtime == 0) begin
$display ("Error: [Unisim %s-1] Simulator resolution is set to a value greater than 1 ps. ", MODULE_NAME);
$display ("The simulator resolution must be set to 1ps or smaller. Instance %m");
#1 $finish;
end
end
`endif
wire CDDCDONE;
wire DRDY;
wire PSDONE;
wire CLKFBSTOPPED;
wire CLKINSTOPPED;
wire [15:0] DO;
MMCME4_ADV #(
.BANDWIDTH(BANDWIDTH),
.CLKFBOUT_MULT_F(CLKFBOUT_MULT_F),
.CLKFBOUT_PHASE(CLKFBOUT_PHASE),
.CLKIN1_PERIOD(CLKIN1_PERIOD),
.CLKIN2_PERIOD(10),
.CLKOUT0_DIVIDE_F(CLKOUT0_DIVIDE_F),
.CLKOUT0_DUTY_CYCLE(CLKOUT0_DUTY_CYCLE),
.CLKOUT0_PHASE(CLKOUT0_PHASE),
.CLKOUT1_DIVIDE(CLKOUT1_DIVIDE),
.CLKOUT1_DUTY_CYCLE(CLKOUT1_DUTY_CYCLE),
.CLKOUT1_PHASE(CLKOUT1_PHASE),
.CLKOUT2_DIVIDE(CLKOUT2_DIVIDE),
.CLKOUT2_DUTY_CYCLE(CLKOUT2_DUTY_CYCLE),
.CLKOUT2_PHASE(CLKOUT2_PHASE),
.CLKOUT3_DIVIDE(CLKOUT3_DIVIDE),
.CLKOUT3_DUTY_CYCLE(CLKOUT3_DUTY_CYCLE),
.CLKOUT3_PHASE(CLKOUT3_PHASE),
.CLKOUT4_CASCADE(CLKOUT4_CASCADE),
.CLKOUT4_DIVIDE(CLKOUT4_DIVIDE),
.CLKOUT4_DUTY_CYCLE(CLKOUT4_DUTY_CYCLE),
.CLKOUT4_PHASE(CLKOUT4_PHASE),
.CLKOUT5_DIVIDE(CLKOUT5_DIVIDE),
.CLKOUT5_DUTY_CYCLE(CLKOUT5_DUTY_CYCLE),
.CLKOUT5_PHASE(CLKOUT5_PHASE),
.CLKOUT6_DIVIDE(CLKOUT6_DIVIDE),
.CLKOUT6_DUTY_CYCLE(CLKOUT6_DUTY_CYCLE),
.CLKOUT6_PHASE(CLKOUT6_PHASE),
.DIVCLK_DIVIDE(DIVCLK_DIVIDE),
.REF_JITTER1(REF_JITTER1),
.STARTUP_WAIT(STARTUP_WAIT)
) mmcm_adv_1 (
.CDDCDONE (CDDCDONE),
.CLKFBOUT (CLKFBOUT),
.CLKFBOUTB (CLKFBOUTB),
.CLKFBSTOPPED(CLKFBSTOPPED),
.CLKINSTOPPED(CLKINSTOPPED),
.CLKOUT0 (CLKOUT0),
.CLKOUT0B (CLKOUT0B),
.CLKOUT1 (CLKOUT1),
.CLKOUT1B (CLKOUT1B),
.CLKOUT2 (CLKOUT2),
.CLKOUT2B (CLKOUT2B),
.CLKOUT3 (CLKOUT3),
.CLKOUT3B (CLKOUT3B),
.CLKOUT4 (CLKOUT4),
.CLKOUT5 (CLKOUT5),
.CLKOUT6 (CLKOUT6),
.DO (DO),
.DRDY (DRDY),
.LOCKED (LOCKED),
.PSDONE(PSDONE),
.CDDCREQ (1'b0),
.CLKFBIN (CLKFBIN_in),
.CLKIN1 (CLKIN1_in),
.CLKIN2 (1'b0),
.CLKINSEL(1'b1),
.DADDR (7'b0),
.DCLK (1'b0),
.DEN (1'b0),
.DI (16'b0),
.DWE (1'b0),
.PSCLK(1'b0),
.PSEN(1'b0),
.PSINCDEC(1'b0),
.PWRDWN(PWRDWN_in),
.RST (RST_in)
);
`ifndef XIL_XECLIB
`ifdef XIL_TIMING
reg notifier;
`endif
specify
(negedge RST => (LOCKED +: 0)) = (100:100:100, 100:100:100);
(posedge RST => (LOCKED +: 0)) = (100:100:100, 100:100:100);
`ifdef XIL_TIMING
$period (negedge CLKFBIN, 0:0:0, notifier);
$period (negedge CLKFBOUT, 0:0:0, notifier);
$period (negedge CLKFBOUTB, 0:0:0, notifier);
$period (negedge CLKIN1, 0:0:0, notifier);
$period (negedge CLKOUT0, 0:0:0, notifier);
$period (negedge CLKOUT0B, 0:0:0, notifier);
$period (negedge CLKOUT1, 0:0:0, notifier);
$period (negedge CLKOUT1B, 0:0:0, notifier);
$period (negedge CLKOUT2, 0:0:0, notifier);
$period (negedge CLKOUT2B, 0:0:0, notifier);
$period (negedge CLKOUT3, 0:0:0, notifier);
$period (negedge CLKOUT3B, 0:0:0, notifier);
$period (negedge CLKOUT4, 0:0:0, notifier);
$period (negedge CLKOUT5, 0:0:0, notifier);
$period (negedge CLKOUT6, 0:0:0, notifier);
$period (posedge CLKFBIN, 0:0:0, notifier);
$period (posedge CLKFBOUT, 0:0:0, notifier);
$period (posedge CLKFBOUTB, 0:0:0, notifier);
$period (posedge CLKIN1, 0:0:0, notifier);
$period (posedge CLKOUT0, 0:0:0, notifier);
$period (posedge CLKOUT0B, 0:0:0, notifier);
$period (posedge CLKOUT1, 0:0:0, notifier);
$period (posedge CLKOUT1B, 0:0:0, notifier);
$period (posedge CLKOUT2, 0:0:0, notifier);
$period (posedge CLKOUT2B, 0:0:0, notifier);
$period (posedge CLKOUT3, 0:0:0, notifier);
$period (posedge CLKOUT3B, 0:0:0, notifier);
$period (posedge CLKOUT4, 0:0:0, notifier);
$period (posedge CLKOUT5, 0:0:0, notifier);
$period (posedge CLKOUT6, 0:0:0, notifier);
$width (negedge CLKIN1, 0:0:0, 0, notifier);
$width (negedge PWRDWN, 0:0:0, 0, notifier);
$width (negedge RST, 0:0:0, 0, notifier);
$width (posedge CLKIN1, 0:0:0, 0, notifier);
$width (posedge PWRDWN, 0:0:0, 0, notifier);
$width (posedge RST, 0:0:0, 0, notifier);
`endif
specparam PATHPULSE$ = 0;
endspecify
`endif
endmodule |
module ddr3_s4_uniphy_example_sim_ddr3_s4_uniphy_example_sim_e0_if0_p0_hr_to_fr(
clk,
d_h0,
d_h1,
d_l0,
d_l1,
q0,
q1
);
input clk;
input d_h0;
input d_h1;
input d_l0;
input d_l1;
output q0;
output q1;
reg q_h0;
reg q_h1;
reg q_l0;
reg q_l1;
reg q_l0_neg;
reg q_l1_neg;
always @(posedge clk)
begin
q_h0 <= d_h0;
q_l0 <= d_l0;
q_h1 <= d_h1;
q_l1 <= d_l1;
end
always @(negedge clk)
begin
q_l0_neg <= q_l0;
q_l1_neg <= q_l1;
end
assign q0 = clk ? q_l0_neg : q_h0;
assign q1 = clk ? q_l1_neg : q_h1;
endmodule |
module dma_loopback_auto_us_1 (
s_axi_aclk,
s_axi_aresetn,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awlock,
s_axi_awcache,
s_axi_awprot,
s_axi_awregion,
s_axi_awqos,
s_axi_awvalid,
s_axi_awready,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wvalid,
s_axi_wready,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
m_axi_awaddr,
m_axi_awlen,
m_axi_awsize,
m_axi_awburst,
m_axi_awlock,
m_axi_awcache,
m_axi_awprot,
m_axi_awregion,
m_axi_awqos,
m_axi_awvalid,
m_axi_awready,
m_axi_wdata,
m_axi_wstrb,
m_axi_wlast,
m_axi_wvalid,
m_axi_wready,
m_axi_bresp,
m_axi_bvalid,
m_axi_bready
);
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 SI_CLK CLK" *)
input wire s_axi_aclk;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 SI_RST RST" *)
input wire s_axi_aresetn;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *)
input wire [31 : 0] s_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLEN" *)
input wire [7 : 0] s_axi_awlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE" *)
input wire [2 : 0] s_axi_awsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWBURST" *)
input wire [1 : 0] s_axi_awburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK" *)
input wire [0 : 0] s_axi_awlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE" *)
input wire [3 : 0] s_axi_awcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWPROT" *)
input wire [2 : 0] s_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREGION" *)
input wire [3 : 0] s_axi_awregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWQOS" *)
input wire [3 : 0] s_axi_awqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWVALID" *)
input wire s_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREADY" *)
output wire s_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WDATA" *)
input wire [31 : 0] s_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WSTRB" *)
input wire [3 : 0] s_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WLAST" *)
input wire s_axi_wlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WVALID" *)
input wire s_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *)
output wire s_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *)
output wire [1 : 0] s_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *)
output wire s_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *)
input wire s_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWADDR" *)
output wire [31 : 0] m_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWLEN" *)
output wire [7 : 0] m_axi_awlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWSIZE" *)
output wire [2 : 0] m_axi_awsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWBURST" *)
output wire [1 : 0] m_axi_awburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWLOCK" *)
output wire [0 : 0] m_axi_awlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWCACHE" *)
output wire [3 : 0] m_axi_awcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWPROT" *)
output wire [2 : 0] m_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREGION" *)
output wire [3 : 0] m_axi_awregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWQOS" *)
output wire [3 : 0] m_axi_awqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWVALID" *)
output wire m_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREADY" *)
input wire m_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WDATA" *)
output wire [63 : 0] m_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WSTRB" *)
output wire [7 : 0] m_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WLAST" *)
output wire m_axi_wlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WVALID" *)
output wire m_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WREADY" *)
input wire m_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BRESP" *)
input wire [1 : 0] m_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BVALID" *)
input wire m_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BREADY" *)
output wire m_axi_bready;
axi_dwidth_converter_v2_1_9_top #(
.C_FAMILY("zynq"),
.C_AXI_PROTOCOL(0),
.C_S_AXI_ID_WIDTH(1),
.C_SUPPORTS_ID(0),
.C_AXI_ADDR_WIDTH(32),
.C_S_AXI_DATA_WIDTH(32),
.C_M_AXI_DATA_WIDTH(64),
.C_AXI_SUPPORTS_WRITE(1),
.C_AXI_SUPPORTS_READ(0),
.C_FIFO_MODE(0),
.C_S_AXI_ACLK_RATIO(1),
.C_M_AXI_ACLK_RATIO(2),
.C_AXI_IS_ACLK_ASYNC(0),
.C_MAX_SPLIT_BEATS(16),
.C_PACKING_LEVEL(1),
.C_SYNCHRONIZER_STAGE(3)
) inst (
.s_axi_aclk(s_axi_aclk),
.s_axi_aresetn(s_axi_aresetn),
.s_axi_awid(1'H0),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awlen(s_axi_awlen),
.s_axi_awsize(s_axi_awsize),
.s_axi_awburst(s_axi_awburst),
.s_axi_awlock(s_axi_awlock),
.s_axi_awcache(s_axi_awcache),
.s_axi_awprot(s_axi_awprot),
.s_axi_awregion(s_axi_awregion),
.s_axi_awqos(s_axi_awqos),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_awready(s_axi_awready),
.s_axi_wdata(s_axi_wdata),
.s_axi_wstrb(s_axi_wstrb),
.s_axi_wlast(s_axi_wlast),
.s_axi_wvalid(s_axi_wvalid),
.s_axi_wready(s_axi_wready),
.s_axi_bid(),
.s_axi_bresp(s_axi_bresp),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_bready(s_axi_bready),
.s_axi_arid(1'H0),
.s_axi_araddr(32'H00000000),
.s_axi_arlen(8'H00),
.s_axi_arsize(3'H0),
.s_axi_arburst(2'H1),
.s_axi_arlock(1'H0),
.s_axi_arcache(4'H0),
.s_axi_arprot(3'H0),
.s_axi_arregion(4'H0),
.s_axi_arqos(4'H0),
.s_axi_arvalid(1'H0),
.s_axi_arready(),
.s_axi_rid(),
.s_axi_rdata(),
.s_axi_rresp(),
.s_axi_rlast(),
.s_axi_rvalid(),
.s_axi_rready(1'H0),
.m_axi_aclk(1'H0),
.m_axi_aresetn(1'H0),
.m_axi_awaddr(m_axi_awaddr),
.m_axi_awlen(m_axi_awlen),
.m_axi_awsize(m_axi_awsize),
.m_axi_awburst(m_axi_awburst),
.m_axi_awlock(m_axi_awlock),
.m_axi_awcache(m_axi_awcache),
.m_axi_awprot(m_axi_awprot),
.m_axi_awregion(m_axi_awregion),
.m_axi_awqos(m_axi_awqos),
.m_axi_awvalid(m_axi_awvalid),
.m_axi_awready(m_axi_awready),
.m_axi_wdata(m_axi_wdata),
.m_axi_wstrb(m_axi_wstrb),
.m_axi_wlast(m_axi_wlast),
.m_axi_wvalid(m_axi_wvalid),
.m_axi_wready(m_axi_wready),
.m_axi_bresp(m_axi_bresp),
.m_axi_bvalid(m_axi_bvalid),
.m_axi_bready(m_axi_bready),
.m_axi_araddr(),
.m_axi_arlen(),
.m_axi_arsize(),
.m_axi_arburst(),
.m_axi_arlock(),
.m_axi_arcache(),
.m_axi_arprot(),
.m_axi_arregion(),
.m_axi_arqos(),
.m_axi_arvalid(),
.m_axi_arready(1'H0),
.m_axi_rdata(64'H0000000000000000),
.m_axi_rresp(2'H0),
.m_axi_rlast(1'H1),
.m_axi_rvalid(1'H0),
.m_axi_rready()
);
endmodule |
module gcm(
// Clock and reset.
input wire clk,
input wire reset_n,
input wire cs,
input wire we,
input wire [7 : 0] address,
input wire [31 : 0] write_data,
output wire [31 : 0] read_data
);
//----------------------------------------------------------------
// Internal constant and parameter definitions.
//----------------------------------------------------------------
localparam ADDR_NAME0 = 8'h00;
localparam ADDR_NAME1 = 8'h01;
localparam ADDR_VERSION = 8'h02;
localparam ADDR_CTRL = 8'h08;
localparam CTRL_INIT_BIT = 0;
localparam CTRL_NEXT_BIT = 1;
localparam CTRL_DONE_BIT = 2;
localparam ADDR_STATUS = 8'h09;
localparam STATUS_READY_BIT = 0;
localparam STATUS_VALID_BIT = 1;
localparam STATUS_CORRECT_ICV = 2;
localparam ADDR_CONFIG = 8'h0a;
localparam CONFIG_ENCDEC_BIT = 0;
localparam CONFIG_KEYLEN_BIT = 1;
localparam CONFIG_TAGLEN_START = 4;
localparam CONFIG_TAGLEN_END = 5;
localparam ADDR_KEY0 = 8'h10;
localparam ADDR_KEY7 = 8'h17;
localparam KEY_WORDS = 8;
localparam ADDR_BLOCK0 = 8'h20;
localparam ADDR_BLOCK3 = 8'h23;
localparam BLOCK_WORDS = 4;
localparam ADDR_NONCE0 = 8'h30;
localparam ADDR_NONCE3 = 8'h33;
localparam NONCE_WORDS = 4;
localparam ADDR_TAG0 = 8'h40;
localparam ADDR_TAG3 = 8'h43;
localparam TAG_WORDS = 4;
localparam WSIZE = 32;
localparam CORE_NAME0 = 32'h67636d2d; // "gcm-"
localparam CORE_NAME1 = 32'h61657320; // "aes "
localparam CORE_VERSION = 32'h302e3032; // "0.02"
//----------------------------------------------------------------
// Registers including update variables and write enable.
//----------------------------------------------------------------
reg init_reg;
reg init_new;
reg next_reg;
reg next_new;
reg done_reg;
reg done_new;
reg encdec_reg;
reg encdec_new;
reg encdec_we;
reg valid_reg;
reg ready_reg;
reg tag_correct_reg;
reg [31 : 0] block_reg [0 : 3];
reg block_we;
reg [1 : 0] block_address;
reg keylen_reg;
reg keylen_new;
reg keylen_we;
reg [31 : 0] key_reg [0 : 7];
reg key_we;
reg [2 : 0] key_address;
reg [1 : 0] taglen_reg;
reg [1 : 0] taglen_new;
reg taglen_we;
reg [31 : 0] nonce_reg [0 : 3];
reg nonce_we;
reg [1 : 0] nonce_address;
reg [31 : 0] tag_reg [0 : 3];
reg tag_we;
reg [1 : 0] tag_address;
//----------------------------------------------------------------
// Wires.
//----------------------------------------------------------------
reg [31 : 0] tmp_read_data;
reg core_encdec;
wire core_ready;
wire core_valid;
wire core_tag_correct;
wire [127 : 0] core_block_in;
wire [127 : 0] core_block_out;
wire [127 : 0] core_tag_in;
wire [127 : 0] core_tag_out;
wire [255 : 0] core_key;
wire [127 : 0] core_nonce;
wire core_keylen;
wire [127 : 0] core_result;
reg config_we;
//----------------------------------------------------------------
// Concurrent connectivity for ports etc.
//----------------------------------------------------------------
assign read_data = tmp_read_data;
assign core_block_in = {block_reg[0], block_reg[1], block_reg[2], block_reg[3]};
assign core_key = {key_reg[0], key_reg[1], key_reg[2], key_reg[3],
key_reg[4], key_reg[5], key_reg[6], key_reg[7]};
//----------------------------------------------------------------
// GCM core instantiation.
//----------------------------------------------------------------
gcm_core core(
.clk(clk),
.reset_n(reset_n),
.init(init_reg),
.next(next_reg),
.done(done_reg),
.enc_dec(encdec_reg),
.keylen(keylen_reg),
.taglen(taglen_reg),
.ready(core_ready),
.valid(core_valid),
.tag_correct(core_tag_correct),
.key(core_key),
.nonce(core_nonce),
.block_in(core_block_in),
.block_out(core_block_out),
.tag_in(core_tag_in),
.tag_out(core_tag_out)
);
//----------------------------------------------------------------
// reg_update
//
// Update functionality for all registers in the core.
// All registers are positive edge triggered with synchronous
// active low reset.
//----------------------------------------------------------------
always @ (posedge clk)
begin : reg_update
integer i;
if (!reset_n)
begin
for (i = 0 ; i < 4 ; i = i + 1)
begin
block_reg[i] <= 32'h0;
nonce_reg[i] <= 32'h0;
tag_reg[i] <= 32'h0;
end
for (i = 0 ; i < 8 ; i = i + 1)
key_reg[i] <= 32'h0;
init_reg <= 0;
next_reg <= 0;
done_reg <= 0;
encdec_reg <= 0;
keylen_reg <= 0;
taglen_reg <= 2'h0;
valid_reg <= 0;
ready_reg <= 0;
end
else
begin
ready_reg <= core_ready;
valid_reg <= core_valid;
init_reg <= init_new;
next_reg <= next_new;
done_reg <= done_new;
if (config_we)
begin
encdec_reg <= write_data[CONFIG_ENCDEC_BIT];
keylen_reg <= write_data[CONFIG_KEYLEN_BIT];
taglen_reg <= write_data[CONFIG_TAGLEN_END : CONFIG_TAGLEN_START];
end
if (keylen_we)
keylen_reg <= keylen_new;
if (taglen_we)
taglen_reg <= taglen_new;
if (encdec_we)
encdec_reg <= encdec_new;
if (block_we)
block_reg[block_address] <= write_data;
if (key_we)
key_reg[key_address] <= write_data;
if (nonce_we)
key_reg[nonce_address] <= write_data;
if (tag_we)
key_reg[tag_address] <= write_data;
end
end // reg_update
//----------------------------------------------------------------
// api
//
// The interface command decoding logic.
//----------------------------------------------------------------
always @*
begin : api
init_new = 0;
next_new = 0;
done_new = 0;
config_we = 0;
key_we = 0;
block_we = 0;
nonce_we = 0;
tag_we = 0;
keylen_new = 0;
keylen_we = 0;
taglen_new = 0;
taglen_we = 0;
encdec_new = 0;
encdec_we = 0;
tmp_read_data = 32'h0;
key_address = address[2 : 0];
block_address = address[1 : 0];
nonce_address = address[1 : 0];
tag_address = address[1 : 0];
if (cs)
begin
if (we)
begin
if (address == ADDR_CTRL)
begin
init_new = write_data[CTRL_INIT_BIT];
next_new = write_data[CTRL_NEXT_BIT];
done_new = write_data[CTRL_DONE_BIT];
end
if (address == ADDR_CONFIG)
config_we = 1;
if ((address >= ADDR_KEY0) && (address <= ADDR_KEY7))
key_we = 1;
if ((address >= ADDR_BLOCK0) && (address <= ADDR_BLOCK3))
block_we = 1;
if ((address >= ADDR_NONCE0) && (address <= ADDR_NONCE3))
nonce_we = 1;
if ((address >= ADDR_TAG0) && (address <= ADDR_TAG3))
tag_we = 1;
end // if (we)
else
begin
if (address == ADDR_NAME0)
tmp_read_data = CORE_NAME0;
if (address == ADDR_NAME1)
tmp_read_data = CORE_NAME1;
if (address == ADDR_VERSION)
tmp_read_data = CORE_VERSION;
if (address == ADDR_CTRL)
tmp_read_data = {30'h0, next_reg, init_reg};
if (address == ADDR_STATUS)
tmp_read_data = {30'h0, valid_reg, ready_reg};
if (address == ADDR_CONFIG)
tmp_read_data = {30'h0, valid_reg, ready_reg};
if ((address >= ADDR_KEY0) && (address <= ADDR_KEY7))
tmp_read_data = key_reg[key_address];
if ((address >= ADDR_BLOCK0) && (address <= ADDR_BLOCK3))
tmp_read_data = block_reg[block_address];
if ((address >= ADDR_NONCE0) && (address <= ADDR_NONCE3))
tmp_read_data = block_reg[nonce_address];
if ((address >= ADDR_TAG0) && (address <= ADDR_TAG3))
tmp_read_data = block_reg[tag_address];
end
end
end // addr_decoder
endmodule |
module uart_sync_flops
(
// internal signals
rst_i,
clk_i,
stage1_rst_i,
stage1_clk_en_i,
async_dat_i,
sync_dat_o
);
parameter Tp = 1;
parameter width = 1;
parameter init_value = 1'b0;
input rst_i; // reset input
input clk_i; // clock input
input stage1_rst_i; // synchronous reset for stage 1 FF
input stage1_clk_en_i; // synchronous clock enable for stage 1 FF
input [width-1:0] async_dat_i; // asynchronous data input
output [width-1:0] sync_dat_o; // synchronous data output
//
// Interal signal declarations
//
reg [width-1:0] sync_dat_o;
reg [width-1:0] flop_0;
// first stage
always @ (posedge clk_i or posedge rst_i)
begin
if (rst_i)
flop_0 <= #Tp {width{init_value}};
else
flop_0 <= #Tp async_dat_i;
end
// second stage
always @ (posedge clk_i or posedge rst_i)
begin
if (rst_i)
sync_dat_o <= #Tp {width{init_value}};
else if (stage1_rst_i)
sync_dat_o <= #Tp {width{init_value}};
else if (stage1_clk_en_i)
sync_dat_o <= #Tp flop_0;
end
endmodule |
module sky130_fd_sc_ls__a311o (
X ,
A1,
A2,
A3,
B1,
C1
);
// Module ports
output X ;
input A1;
input A2;
input A3;
input B1;
input C1;
// Local signals
wire and0_out ;
wire or0_out_X;
// Name Output Other arguments
and and0 (and0_out , A3, A1, A2 );
or or0 (or0_out_X, and0_out, C1, B1);
buf buf0 (X , or0_out_X );
endmodule |
module arria2gx_dmem (
address,
byteena,
clken,
clock,
data,
wren,
q);
input [9:0] address;
input [1:0] byteena;
input clken;
input clock;
input [15:0] data;
input wren;
output [15:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 [1:0] byteena;
tri1 clken;
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [15:0] sub_wire0;
wire [15:0] q = sub_wire0[15:0];
altsyncram altsyncram_component (
.clocken0 (clken),
.wren_a (wren),
.clock0 (clock),
.byteena_a (byteena),
.address_a (address),
.data_a (data),
.q_a (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.address_b (1'b1),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_b (1'b1),
.eccstatus (),
.q_b (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_b (1'b0));
defparam
altsyncram_component.byte_size = 8,
altsyncram_component.clock_enable_input_a = "NORMAL",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.intended_device_family = "Arria II GX",
altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 1024,
altsyncram_component.operation_mode = "SINGLE_PORT",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_reg_a = "UNREGISTERED",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.read_during_write_mode_port_a = "NEW_DATA_NO_NBE_READ",
altsyncram_component.widthad_a = 10,
altsyncram_component.width_a = 16,
altsyncram_component.width_byteena_a = 2;
endmodule |
module sky130_fd_sc_hdll__probe_p_8 (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__probe_p base (
.X(X),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule |
module sky130_fd_sc_hdll__probe_p_8 (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__probe_p base (
.X(X),
.A(A)
);
endmodule |
module sky130_fd_sc_ms__clkdlyinv3sd1 (
Y,
A
);
// Module ports
output Y;
input A;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire not0_out_Y;
// Name Output Other arguments
not not0 (not0_out_Y, A );
buf buf0 (Y , not0_out_Y );
endmodule |
module mig_7series_v1_8_memc_ui_top_std #
(
parameter TCQ = 100,
parameter PAYLOAD_WIDTH = 64,
parameter ADDR_CMD_MODE = "UNBUF",
parameter AL = "0", // Additive Latency option
parameter BANK_WIDTH = 3, // # of bank bits
parameter BM_CNT_WIDTH = 2, // Bank machine counter width
parameter BURST_MODE = "8", // Burst length
parameter BURST_TYPE = "SEQ", // Burst type
parameter CA_MIRROR = "OFF", // C/A mirror opt for DDR3 dual rank
parameter CK_WIDTH = 1, // # of CK/CK# outputs to memory
parameter CL = 5,
parameter COL_WIDTH = 12, // column address width
parameter CMD_PIPE_PLUS1 = "ON", // add pipeline stage between MC and PHY
parameter CS_WIDTH = 1, // # of unique CS outputs
parameter CKE_WIDTH = 1, // # of cke outputs
parameter CWL = 5,
parameter DATA_WIDTH = 64,
parameter DATA_BUF_ADDR_WIDTH = 5,
parameter DATA_BUF_OFFSET_WIDTH = 1,
parameter DDR2_DQSN_ENABLE = "YES", // Enable differential DQS for DDR2
parameter DM_WIDTH = 8, // # of DM (data mask)
parameter DQ_CNT_WIDTH = 6, // = ceil(log2(DQ_WIDTH))
parameter DQ_WIDTH = 64, // # of DQ (data)
parameter DQS_CNT_WIDTH = 3, // = ceil(log2(DQS_WIDTH))
parameter DQS_WIDTH = 8, // # of DQS (strobe)
parameter DRAM_TYPE = "DDR3",
parameter DRAM_WIDTH = 8, // # of DQ per DQS
parameter ECC = "OFF",
parameter ECC_WIDTH = 8,
parameter ECC_TEST = "OFF",
parameter MC_ERR_ADDR_WIDTH = 31,
parameter MASTER_PHY_CTL = 0, // The bank number where master PHY_CONTROL resides
parameter nAL = 0, // Additive latency (in clk cyc)
parameter nBANK_MACHS = 4,
parameter nCK_PER_CLK = 2, // # of memory CKs per fabric CLK
parameter nCS_PER_RANK = 1, // # of unique CS outputs per rank
parameter ORDERING = "NORM",
parameter IBUF_LPWR_MODE = "OFF",
parameter IODELAY_HP_MODE = "ON",
parameter BANK_TYPE = "HP_IO", // # = "HP_IO", "HPL_IO", "HR_IO", "HRL_IO"
parameter DATA_IO_PRIM_TYPE = "DEFAULT", // # = "HP_LP", "HR_LP", "DEFAULT"
parameter DATA_IO_IDLE_PWRDWN = "ON", // "ON" or "OFF"
parameter IODELAY_GRP = "IODELAY_MIG",
parameter OUTPUT_DRV = "HIGH",
parameter REG_CTRL = "OFF",
parameter RTT_NOM = "60",
parameter RTT_WR = "120",
parameter STARVE_LIMIT = 2,
parameter tCK = 2500, // pS
parameter tCKE = 10000, // pS
parameter tFAW = 40000, // pS
parameter tPRDI = 1_000_000, // pS
parameter tRAS = 37500, // pS
parameter tRCD = 12500, // pS
parameter tREFI = 7800000, // pS
parameter tRFC = 110000, // pS
parameter tRP = 12500, // pS
parameter tRRD = 10000, // pS
parameter tRTP = 7500, // pS
parameter tWTR = 7500, // pS
parameter tZQI = 128_000_000, // nS
parameter tZQCS = 64, // CKs
parameter USER_REFRESH = "OFF", // Whether user manages REF
parameter TEMP_MON_EN = "ON", // Enable/Disable tempmon
parameter WRLVL = "OFF",
parameter DEBUG_PORT = "OFF",
parameter CAL_WIDTH = "HALF",
parameter RANK_WIDTH = 1,
parameter RANKS = 4,
parameter ODT_WIDTH = 1,
parameter ROW_WIDTH = 16, // DRAM address bus width
parameter ADDR_WIDTH = 32,
parameter APP_MASK_WIDTH = 8,
parameter APP_DATA_WIDTH = 64,
parameter [3:0] BYTE_LANES_B0 = 4'hF,
parameter [3:0] BYTE_LANES_B1 = 4'hF,
parameter [3:0] BYTE_LANES_B2 = 4'hF,
parameter [3:0] BYTE_LANES_B3 = 4'hF,
parameter [3:0] BYTE_LANES_B4 = 4'hF,
parameter [3:0] DATA_CTL_B0 = 4'hc,
parameter [3:0] DATA_CTL_B1 = 4'hf,
parameter [3:0] DATA_CTL_B2 = 4'hf,
parameter [3:0] DATA_CTL_B3 = 4'h0,
parameter [3:0] DATA_CTL_B4 = 4'h0,
parameter [47:0] PHY_0_BITLANES = 48'h0000_0000_0000,
parameter [47:0] PHY_1_BITLANES = 48'h0000_0000_0000,
parameter [47:0] PHY_2_BITLANES = 48'h0000_0000_0000,
// control/address/data pin mapping parameters
parameter [143:0] CK_BYTE_MAP
= 144'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00,
parameter [191:0] ADDR_MAP
= 192'h000_000_000_000_000_000_000_000_000_000_000_000_000_000_000_000,
parameter [35:0] BANK_MAP = 36'h000_000_000,
parameter [11:0] CAS_MAP = 12'h000,
parameter [7:0] CKE_ODT_BYTE_MAP = 8'h00,
parameter [95:0] CKE_MAP = 96'h000_000_000_000_000_000_000_000,
parameter [95:0] ODT_MAP = 96'h000_000_000_000_000_000_000_000,
parameter CKE_ODT_AUX = "FALSE",
parameter [119:0] CS_MAP = 120'h000_000_000_000_000_000_000_000_000_000,
parameter [11:0] PARITY_MAP = 12'h000,
parameter [11:0] RAS_MAP = 12'h000,
parameter [11:0] WE_MAP = 12'h000,
parameter [143:0] DQS_BYTE_MAP
= 144'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00,
parameter [95:0] DATA0_MAP = 96'h000_000_000_000_000_000_000_000,
parameter [95:0] DATA1_MAP = 96'h000_000_000_000_000_000_000_000,
parameter [95:0] DATA2_MAP = 96'h000_000_000_000_000_000_000_000,
parameter [95:0] DATA3_MAP = 96'h000_000_000_000_000_000_000_000,
parameter [95:0] DATA4_MAP = 96'h000_000_000_000_000_000_000_000,
parameter [95:0] DATA5_MAP = 96'h000_000_000_000_000_000_000_000,
parameter [95:0] DATA6_MAP = 96'h000_000_000_000_000_000_000_000,
parameter [95:0] DATA7_MAP = 96'h000_000_000_000_000_000_000_000,
parameter [95:0] DATA8_MAP = 96'h000_000_000_000_000_000_000_000,
parameter [95:0] DATA9_MAP = 96'h000_000_000_000_000_000_000_000,
parameter [95:0] DATA10_MAP = 96'h000_000_000_000_000_000_000_000,
parameter [95:0] DATA11_MAP = 96'h000_000_000_000_000_000_000_000,
parameter [95:0] DATA12_MAP = 96'h000_000_000_000_000_000_000_000,
parameter [95:0] DATA13_MAP = 96'h000_000_000_000_000_000_000_000,
parameter [95:0] DATA14_MAP = 96'h000_000_000_000_000_000_000_000,
parameter [95:0] DATA15_MAP = 96'h000_000_000_000_000_000_000_000,
parameter [95:0] DATA16_MAP = 96'h000_000_000_000_000_000_000_000,
parameter [95:0] DATA17_MAP = 96'h000_000_000_000_000_000_000_000,
parameter [107:0] MASK0_MAP = 108'h000_000_000_000_000_000_000_000_000,
parameter [107:0] MASK1_MAP = 108'h000_000_000_000_000_000_000_000_000,
parameter [7:0] SLOT_0_CONFIG = 8'b0000_0001,
parameter [7:0] SLOT_1_CONFIG = 8'b0000_0000,
parameter MEM_ADDR_ORDER = "BANK_ROW_COLUMN",
// calibration Address. The address given below will be used for calibration
// read and write operations.
parameter [15:0] CALIB_ROW_ADD = 16'h0000, // Calibration row address
parameter [11:0] CALIB_COL_ADD = 12'h000, // Calibration column address
parameter [2:0] CALIB_BA_ADD = 3'h0, // Calibration bank address
parameter SIM_BYPASS_INIT_CAL = "OFF",
parameter REFCLK_FREQ = 300.0,
parameter USE_CS_PORT = 1, // Support chip select output
parameter USE_DM_PORT = 1, // Support data mask output
parameter USE_ODT_PORT = 1 // Support ODT output
)
(
// Clock and reset ports
input clk,
input clk_ref,
input mem_refclk ,
input freq_refclk ,
input pll_lock,
input sync_pulse ,
input rst,
// memory interface ports
inout [DQ_WIDTH-1:0] ddr_dq,
inout [DQS_WIDTH-1:0] ddr_dqs_n,
inout [DQS_WIDTH-1:0] ddr_dqs,
output [ROW_WIDTH-1:0] ddr_addr,
output [BANK_WIDTH-1:0] ddr_ba,
output ddr_cas_n,
output [CK_WIDTH-1:0] ddr_ck_n,
output [CK_WIDTH-1:0] ddr_ck,
output [CKE_WIDTH-1:0] ddr_cke,
output [CS_WIDTH*nCS_PER_RANK-1:0] ddr_cs_n,
output [DM_WIDTH-1:0] ddr_dm,
output [ODT_WIDTH-1:0] ddr_odt,
output ddr_ras_n,
output ddr_reset_n,
output ddr_parity,
output ddr_we_n,
output [BM_CNT_WIDTH-1:0] bank_mach_next,
// user interface ports
input [ADDR_WIDTH-1:0] app_addr,
input [2:0] app_cmd,
input app_en,
input app_hi_pri,
input [APP_DATA_WIDTH-1:0] app_wdf_data,
input app_wdf_end,
input [APP_MASK_WIDTH-1:0] app_wdf_mask,
input app_wdf_wren,
input app_correct_en_i,
input [2*nCK_PER_CLK-1:0] app_raw_not_ecc,
output [2*nCK_PER_CLK-1:0] app_ecc_multiple_err,
output [APP_DATA_WIDTH-1:0] app_rd_data,
output app_rd_data_end,
output app_rd_data_valid,
output app_rdy,
output app_wdf_rdy,
input app_sr_req,
output app_sr_active,
input app_ref_req,
output app_ref_ack,
input app_zq_req,
output app_zq_ack,
// temperature monitor ports
input [11:0] device_temp,
// debug logic ports
input dbg_idel_down_all,
input dbg_idel_down_cpt,
input dbg_idel_up_all,
input dbg_idel_up_cpt,
input dbg_sel_all_idel_cpt,
input [DQS_CNT_WIDTH-1:0] dbg_sel_idel_cpt,
output [6*DQS_WIDTH*RANKS-1:0] dbg_cpt_first_edge_cnt,
output [6*DQS_WIDTH*RANKS-1:0] dbg_cpt_second_edge_cnt,
output [DQS_WIDTH-1:0] dbg_rd_data_edge_detect,
output [2*nCK_PER_CLK*DQ_WIDTH-1:0] dbg_rddata,
output [1:0] dbg_rdlvl_done,
output [1:0] dbg_rdlvl_err,
output [1:0] dbg_rdlvl_start,
output [5:0] dbg_tap_cnt_during_wrlvl,
output dbg_wl_edge_detect_valid,
output dbg_wrlvl_done,
output dbg_wrlvl_err,
output dbg_wrlvl_start,
output [6*DQS_WIDTH-1:0] dbg_final_po_fine_tap_cnt,
output [3*DQS_WIDTH-1:0] dbg_final_po_coarse_tap_cnt,
output init_calib_complete,
input dbg_sel_pi_incdec,
input dbg_sel_po_incdec,
input [DQS_CNT_WIDTH:0] dbg_byte_sel,
input dbg_pi_f_inc,
input dbg_pi_f_dec,
input dbg_po_f_inc,
input dbg_po_f_stg23_sel,
input dbg_po_f_dec,
output [6*DQS_WIDTH*RANKS-1:0] dbg_cpt_tap_cnt,
output [5*DQS_WIDTH*RANKS-1:0] dbg_dq_idelay_tap_cnt,
output dbg_rddata_valid,
output [6*DQS_WIDTH-1:0] dbg_wrlvl_fine_tap_cnt,
output [3*DQS_WIDTH-1:0] dbg_wrlvl_coarse_tap_cnt,
output ref_dll_lock,
input rst_phaser_ref,
output [6*RANKS-1:0] dbg_rd_data_offset,
output [255:0] dbg_calib_top,
output [255:0] dbg_phy_wrlvl,
output [255:0] dbg_phy_rdlvl,
output [99:0] dbg_phy_wrcal,
output [255:0] dbg_phy_init,
output [255:0] dbg_prbs_rdlvl,
output [255:0] dbg_dqs_found_cal,
output [5:0] dbg_pi_counter_read_val,
output [8:0] dbg_po_counter_read_val,
output dbg_pi_phaselock_start,
output dbg_pi_phaselocked_done,
output dbg_pi_phaselock_err,
output dbg_pi_dqsfound_start,
output dbg_pi_dqsfound_done,
output dbg_pi_dqsfound_err,
output dbg_wrcal_start,
output dbg_wrcal_done,
output dbg_wrcal_err,
output [11:0] dbg_pi_dqs_found_lanes_phy4lanes,
output [11:0] dbg_pi_phase_locked_phy4lanes,
output [6*RANKS-1:0] dbg_calib_rd_data_offset_1,
output [6*RANKS-1:0] dbg_calib_rd_data_offset_2,
output [5:0] dbg_data_offset,
output [5:0] dbg_data_offset_1,
output [5:0] dbg_data_offset_2,
output dbg_oclkdelay_calib_start,
output dbg_oclkdelay_calib_done,
output [255:0] dbg_phy_oclkdelay_cal,
output [DRAM_WIDTH*16 -1:0] dbg_oclkdelay_rd_data
);
wire correct_en;
wire [2*nCK_PER_CLK-1:0] raw_not_ecc;
wire [2*nCK_PER_CLK-1:0] ecc_single;
wire [2*nCK_PER_CLK-1:0] ecc_multiple;
wire [MC_ERR_ADDR_WIDTH-1:0] ecc_err_addr;
wire [DATA_BUF_OFFSET_WIDTH-1:0] wr_data_offset;
wire wr_data_en;
wire [DATA_BUF_ADDR_WIDTH-1:0] wr_data_addr;
wire [DATA_BUF_OFFSET_WIDTH-1:0] rd_data_offset;
wire rd_data_en;
wire [DATA_BUF_ADDR_WIDTH-1:0] rd_data_addr;
wire accept;
wire accept_ns;
wire [2*nCK_PER_CLK*PAYLOAD_WIDTH-1:0] rd_data;
wire rd_data_end;
wire use_addr;
wire size;
wire [ROW_WIDTH-1:0] row;
wire [RANK_WIDTH-1:0] rank;
wire hi_priority;
wire [DATA_BUF_ADDR_WIDTH-1:0] data_buf_addr;
wire [COL_WIDTH-1:0] col;
wire [2:0] cmd;
wire [BANK_WIDTH-1:0] bank;
wire [2*nCK_PER_CLK*PAYLOAD_WIDTH-1:0] wr_data;
wire [2*nCK_PER_CLK*DATA_WIDTH/8-1:0] wr_data_mask;
wire app_sr_req_i;
wire app_sr_active_i;
wire app_ref_req_i;
wire app_ref_ack_i;
wire app_zq_req_i;
wire app_zq_ack_i;
wire rst_tg_mc;
wire error;
wire init_wrcal_complete;
(* keep = "true", max_fanout = 30 *) reg reset;
//***************************************************************************
always @(posedge clk)
reset <= #TCQ (rst | rst_tg_mc);
mig_7series_v1_8_mem_intfc #
(
.TCQ (TCQ),
.PAYLOAD_WIDTH (PAYLOAD_WIDTH),
.ADDR_CMD_MODE (ADDR_CMD_MODE),
.AL (AL),
.BANK_WIDTH (BANK_WIDTH),
.BM_CNT_WIDTH (BM_CNT_WIDTH),
.BURST_MODE (BURST_MODE),
.BURST_TYPE (BURST_TYPE),
.CA_MIRROR (CA_MIRROR),
.CK_WIDTH (CK_WIDTH),
.COL_WIDTH (COL_WIDTH),
.CMD_PIPE_PLUS1 (CMD_PIPE_PLUS1),
.CS_WIDTH (CS_WIDTH),
.nCS_PER_RANK (nCS_PER_RANK),
.CKE_WIDTH (CKE_WIDTH),
.DATA_WIDTH (DATA_WIDTH),
.DATA_BUF_ADDR_WIDTH (DATA_BUF_ADDR_WIDTH),
.MASTER_PHY_CTL (MASTER_PHY_CTL),
.DATA_BUF_OFFSET_WIDTH (DATA_BUF_OFFSET_WIDTH),
.DDR2_DQSN_ENABLE (DDR2_DQSN_ENABLE),
.DM_WIDTH (DM_WIDTH),
.DQ_CNT_WIDTH (DQ_CNT_WIDTH),
.DQ_WIDTH (DQ_WIDTH),
.DQS_CNT_WIDTH (DQS_CNT_WIDTH),
.DQS_WIDTH (DQS_WIDTH),
.DRAM_TYPE (DRAM_TYPE),
.DRAM_WIDTH (DRAM_WIDTH),
.ECC (ECC),
.ECC_WIDTH (ECC_WIDTH),
.MC_ERR_ADDR_WIDTH (MC_ERR_ADDR_WIDTH),
.REFCLK_FREQ (REFCLK_FREQ),
.nAL (nAL),
.nBANK_MACHS (nBANK_MACHS),
.nCK_PER_CLK (nCK_PER_CLK),
.ORDERING (ORDERING),
.OUTPUT_DRV (OUTPUT_DRV),
.IBUF_LPWR_MODE (IBUF_LPWR_MODE),
.IODELAY_HP_MODE (IODELAY_HP_MODE),
.BANK_TYPE (BANK_TYPE),
.DATA_IO_PRIM_TYPE (DATA_IO_PRIM_TYPE),
.DATA_IO_IDLE_PWRDWN (DATA_IO_IDLE_PWRDWN),
.IODELAY_GRP (IODELAY_GRP),
.REG_CTRL (REG_CTRL),
.RTT_NOM (RTT_NOM),
.RTT_WR (RTT_WR),
.CL (CL),
.CWL (CWL),
.tCK (tCK),
.tCKE (tCKE),
.tFAW (tFAW),
.tPRDI (tPRDI),
.tRAS (tRAS),
.tRCD (tRCD),
.tREFI (tREFI),
.tRFC (tRFC),
.tRP (tRP),
.tRRD (tRRD),
.tRTP (tRTP),
.tWTR (tWTR),
.tZQI (tZQI),
.tZQCS (tZQCS),
.USER_REFRESH (USER_REFRESH),
.TEMP_MON_EN (TEMP_MON_EN),
.WRLVL (WRLVL),
.DEBUG_PORT (DEBUG_PORT),
.CAL_WIDTH (CAL_WIDTH),
.RANK_WIDTH (RANK_WIDTH),
.RANKS (RANKS),
.ODT_WIDTH (ODT_WIDTH),
.ROW_WIDTH (ROW_WIDTH),
.SIM_BYPASS_INIT_CAL (SIM_BYPASS_INIT_CAL),
.BYTE_LANES_B0 (BYTE_LANES_B0),
.BYTE_LANES_B1 (BYTE_LANES_B1),
.BYTE_LANES_B2 (BYTE_LANES_B2),
.BYTE_LANES_B3 (BYTE_LANES_B3),
.BYTE_LANES_B4 (BYTE_LANES_B4),
.DATA_CTL_B0 (DATA_CTL_B0),
.DATA_CTL_B1 (DATA_CTL_B1),
.DATA_CTL_B2 (DATA_CTL_B2),
.DATA_CTL_B3 (DATA_CTL_B3),
.DATA_CTL_B4 (DATA_CTL_B4),
.PHY_0_BITLANES (PHY_0_BITLANES),
.PHY_1_BITLANES (PHY_1_BITLANES),
.PHY_2_BITLANES (PHY_2_BITLANES),
.CK_BYTE_MAP (CK_BYTE_MAP),
.ADDR_MAP (ADDR_MAP),
.BANK_MAP (BANK_MAP),
.CAS_MAP (CAS_MAP),
.CKE_ODT_BYTE_MAP (CKE_ODT_BYTE_MAP),
.CKE_MAP (CKE_MAP),
.ODT_MAP (ODT_MAP),
.CKE_ODT_AUX (CKE_ODT_AUX),
.CS_MAP (CS_MAP),
.PARITY_MAP (PARITY_MAP),
.RAS_MAP (RAS_MAP),
.WE_MAP (WE_MAP),
.DQS_BYTE_MAP (DQS_BYTE_MAP),
.DATA0_MAP (DATA0_MAP),
.DATA1_MAP (DATA1_MAP),
.DATA2_MAP (DATA2_MAP),
.DATA3_MAP (DATA3_MAP),
.DATA4_MAP (DATA4_MAP),
.DATA5_MAP (DATA5_MAP),
.DATA6_MAP (DATA6_MAP),
.DATA7_MAP (DATA7_MAP),
.DATA8_MAP (DATA8_MAP),
.DATA9_MAP (DATA9_MAP),
.DATA10_MAP (DATA10_MAP),
.DATA11_MAP (DATA11_MAP),
.DATA12_MAP (DATA12_MAP),
.DATA13_MAP (DATA13_MAP),
.DATA14_MAP (DATA14_MAP),
.DATA15_MAP (DATA15_MAP),
.DATA16_MAP (DATA16_MAP),
.DATA17_MAP (DATA17_MAP),
.MASK0_MAP (MASK0_MAP),
.MASK1_MAP (MASK1_MAP),
.SLOT_0_CONFIG (SLOT_0_CONFIG),
.SLOT_1_CONFIG (SLOT_1_CONFIG),
.CALIB_ROW_ADD (CALIB_ROW_ADD),
.CALIB_COL_ADD (CALIB_COL_ADD),
.CALIB_BA_ADD (CALIB_BA_ADD),
.STARVE_LIMIT (STARVE_LIMIT),
.USE_CS_PORT (USE_CS_PORT),
.USE_DM_PORT (USE_DM_PORT),
.USE_ODT_PORT (USE_ODT_PORT)
)
mem_intfc0
(
.clk (clk),
.clk_ref (clk_ref),
.mem_refclk (mem_refclk), //memory clock
.freq_refclk (freq_refclk),
.pll_lock (pll_lock),
.sync_pulse (sync_pulse),
.rst (rst),
.error (error),
.reset (reset),
.rst_tg_mc (rst_tg_mc),
.ddr_dq (ddr_dq),
.ddr_dqs_n (ddr_dqs_n),
.ddr_dqs (ddr_dqs),
.ddr_addr (ddr_addr),
.ddr_ba (ddr_ba),
.ddr_cas_n (ddr_cas_n),
.ddr_ck_n (ddr_ck_n),
.ddr_ck (ddr_ck),
.ddr_cke (ddr_cke),
.ddr_cs_n (ddr_cs_n),
.ddr_dm (ddr_dm),
.ddr_odt (ddr_odt),
.ddr_ras_n (ddr_ras_n),
.ddr_reset_n (ddr_reset_n),
.ddr_parity (ddr_parity),
.ddr_we_n (ddr_we_n),
.slot_0_present (SLOT_0_CONFIG),
.slot_1_present (SLOT_1_CONFIG),
.correct_en (correct_en),
.bank (bank),
.cmd (cmd),
.col (col),
.data_buf_addr (data_buf_addr),
.wr_data (wr_data),
.wr_data_mask (wr_data_mask),
.rank (rank),
.raw_not_ecc (raw_not_ecc),
.row (row),
.hi_priority (hi_priority),
.size (size),
.use_addr (use_addr),
.accept (accept),
.accept_ns (accept_ns),
.ecc_single (ecc_single),
.ecc_multiple (ecc_multiple),
.ecc_err_addr (ecc_err_addr),
.rd_data (rd_data),
.rd_data_addr (rd_data_addr),
.rd_data_en (rd_data_en),
.rd_data_end (rd_data_end),
.rd_data_offset (rd_data_offset),
.wr_data_addr (wr_data_addr),
.wr_data_en (wr_data_en),
.wr_data_offset (wr_data_offset),
.bank_mach_next (bank_mach_next),
.init_calib_complete (init_calib_complete),
.init_wrcal_complete (init_wrcal_complete),
.app_sr_req (app_sr_req_i),
.app_sr_active (app_sr_active_i),
.app_ref_req (app_ref_req_i),
.app_ref_ack (app_ref_ack_i),
.app_zq_req (app_zq_req_i),
.app_zq_ack (app_zq_ack_i),
.device_temp (device_temp),
.dbg_idel_up_all (dbg_idel_up_all),
.dbg_idel_down_all (dbg_idel_down_all),
.dbg_idel_up_cpt (dbg_idel_up_cpt),
.dbg_idel_down_cpt (dbg_idel_down_cpt),
.dbg_sel_idel_cpt (dbg_sel_idel_cpt),
.dbg_sel_all_idel_cpt (dbg_sel_all_idel_cpt),
.dbg_calib_top (dbg_calib_top),
.dbg_cpt_first_edge_cnt (dbg_cpt_first_edge_cnt),
.dbg_cpt_second_edge_cnt (dbg_cpt_second_edge_cnt),
.dbg_phy_rdlvl (dbg_phy_rdlvl),
.dbg_phy_wrcal (dbg_phy_wrcal),
.dbg_final_po_fine_tap_cnt (dbg_final_po_fine_tap_cnt),
.dbg_final_po_coarse_tap_cnt (dbg_final_po_coarse_tap_cnt),
.dbg_rd_data_edge_detect (dbg_rd_data_edge_detect),
.dbg_rddata (dbg_rddata),
.dbg_rdlvl_done (dbg_rdlvl_done),
.dbg_rdlvl_err (dbg_rdlvl_err),
.dbg_rdlvl_start (dbg_rdlvl_start),
.dbg_tap_cnt_during_wrlvl (dbg_tap_cnt_during_wrlvl),
.dbg_wl_edge_detect_valid (dbg_wl_edge_detect_valid),
.dbg_wrlvl_done (dbg_wrlvl_done),
.dbg_wrlvl_err (dbg_wrlvl_err),
.dbg_wrlvl_start (dbg_wrlvl_start),
.dbg_sel_pi_incdec (dbg_sel_pi_incdec),
.dbg_sel_po_incdec (dbg_sel_po_incdec),
.dbg_byte_sel (dbg_byte_sel),
.dbg_pi_f_inc (dbg_pi_f_inc),
.dbg_pi_f_dec (dbg_pi_f_dec),
.dbg_po_f_inc (dbg_po_f_inc),
.dbg_po_f_stg23_sel (dbg_po_f_stg23_sel),
.dbg_po_f_dec (dbg_po_f_dec),
.dbg_cpt_tap_cnt (dbg_cpt_tap_cnt),
.dbg_dq_idelay_tap_cnt (dbg_dq_idelay_tap_cnt),
.dbg_rddata_valid (dbg_rddata_valid),
.dbg_wrlvl_fine_tap_cnt (dbg_wrlvl_fine_tap_cnt),
.dbg_wrlvl_coarse_tap_cnt (dbg_wrlvl_coarse_tap_cnt),
.dbg_phy_wrlvl (dbg_phy_wrlvl),
.dbg_pi_counter_read_val (dbg_pi_counter_read_val),
.dbg_po_counter_read_val (dbg_po_counter_read_val),
.ref_dll_lock (ref_dll_lock),
.rst_phaser_ref (rst_phaser_ref),
.dbg_rd_data_offset (dbg_rd_data_offset),
.dbg_phy_init (dbg_phy_init),
.dbg_prbs_rdlvl (dbg_prbs_rdlvl),
.dbg_dqs_found_cal (dbg_dqs_found_cal),
.dbg_pi_phaselock_start (dbg_pi_phaselock_start),
.dbg_pi_phaselocked_done (dbg_pi_phaselocked_done),
.dbg_pi_phaselock_err (dbg_pi_phaselock_err),
.dbg_pi_dqsfound_start (dbg_pi_dqsfound_start),
.dbg_pi_dqsfound_done (dbg_pi_dqsfound_done),
.dbg_pi_dqsfound_err (dbg_pi_dqsfound_err),
.dbg_wrcal_start (dbg_wrcal_start),
.dbg_wrcal_done (dbg_wrcal_done),
.dbg_wrcal_err (dbg_wrcal_err),
.dbg_pi_dqs_found_lanes_phy4lanes (dbg_pi_dqs_found_lanes_phy4lanes),
.dbg_pi_phase_locked_phy4lanes (dbg_pi_phase_locked_phy4lanes),
.dbg_calib_rd_data_offset_1 (dbg_calib_rd_data_offset_1),
.dbg_calib_rd_data_offset_2 (dbg_calib_rd_data_offset_2),
.dbg_data_offset (dbg_data_offset),
.dbg_data_offset_1 (dbg_data_offset_1),
.dbg_data_offset_2 (dbg_data_offset_2),
.dbg_phy_oclkdelay_cal (dbg_phy_oclkdelay_cal),
.dbg_oclkdelay_rd_data (dbg_oclkdelay_rd_data),
.dbg_oclkdelay_calib_start (dbg_oclkdelay_calib_start),
.dbg_oclkdelay_calib_done (dbg_oclkdelay_calib_done)
);
mig_7series_v1_8_ui_top #
(
.TCQ (TCQ),
.APP_DATA_WIDTH (APP_DATA_WIDTH),
.APP_MASK_WIDTH (APP_MASK_WIDTH),
.BANK_WIDTH (BANK_WIDTH),
.COL_WIDTH (COL_WIDTH),
.CWL (CWL),
.DATA_BUF_ADDR_WIDTH (DATA_BUF_ADDR_WIDTH),
.ECC (ECC),
.ECC_TEST (ECC_TEST),
.nCK_PER_CLK (nCK_PER_CLK),
.ORDERING (ORDERING),
.RANKS (RANKS),
.RANK_WIDTH (RANK_WIDTH),
.ROW_WIDTH (ROW_WIDTH),
.MEM_ADDR_ORDER (MEM_ADDR_ORDER)
)
u_ui_top
(
.wr_data_mask (wr_data_mask[APP_MASK_WIDTH-1:0]),
.wr_data (wr_data[APP_DATA_WIDTH-1:0]),
.use_addr (use_addr),
.size (size),
.row (row),
.raw_not_ecc (raw_not_ecc),
.rank (rank),
.hi_priority (hi_priority),
.data_buf_addr (data_buf_addr),
.col (col),
.cmd (cmd),
.bank (bank),
.app_wdf_rdy (app_wdf_rdy),
.app_rdy (app_rdy),
.app_rd_data_valid (app_rd_data_valid),
.app_rd_data_end (app_rd_data_end),
.app_rd_data (app_rd_data),
.app_ecc_multiple_err (app_ecc_multiple_err),
.correct_en (correct_en),
.wr_data_offset (wr_data_offset),
.wr_data_en (wr_data_en),
.wr_data_addr (wr_data_addr),
.rst (reset),
.rd_data_offset (rd_data_offset),
.rd_data_end (rd_data_end),
.rd_data_en (rd_data_en),
.rd_data_addr (rd_data_addr),
.rd_data (rd_data[APP_DATA_WIDTH-1:0]),
.ecc_multiple (ecc_multiple),
.clk (clk),
.app_wdf_wren (app_wdf_wren),
.app_wdf_mask (app_wdf_mask),
.app_wdf_end (app_wdf_end),
.app_wdf_data (app_wdf_data),
.app_sz (1'b1),
.app_raw_not_ecc (app_raw_not_ecc),
.app_hi_pri (app_hi_pri),
.app_en (app_en),
.app_cmd (app_cmd),
.app_addr (app_addr),
.accept_ns (accept_ns),
.accept (accept),
.app_correct_en (app_correct_en_i),
.app_sr_req (app_sr_req),
.sr_req (app_sr_req_i),
.sr_active (app_sr_active_i),
.app_sr_active (app_sr_active),
.app_ref_req (app_ref_req),
.ref_req (app_ref_req_i),
.ref_ack (app_ref_ack_i),
.app_ref_ack (app_ref_ack),
.app_zq_req (app_zq_req),
.zq_req (app_zq_req_i),
.zq_ack (app_zq_ack_i),
.app_zq_ack (app_zq_ack)
);
endmodule |
module AXIvideo2Mat (
ap_clk,
ap_rst,
ap_start,
start_full_n,
ap_done,
ap_continue,
ap_idle,
ap_ready,
start_out,
start_write,
stream_in_TDATA,
stream_in_TVALID,
stream_in_TREADY,
stream_in_TKEEP,
stream_in_TSTRB,
stream_in_TUSER,
stream_in_TLAST,
stream_in_TID,
stream_in_TDEST,
img_rows_V_dout,
img_rows_V_empty_n,
img_rows_V_read,
img_cols_V_dout,
img_cols_V_empty_n,
img_cols_V_read,
img_data_stream_0_V_din,
img_data_stream_0_V_full_n,
img_data_stream_0_V_write,
img_data_stream_1_V_din,
img_data_stream_1_V_full_n,
img_data_stream_1_V_write,
img_data_stream_2_V_din,
img_data_stream_2_V_full_n,
img_data_stream_2_V_write,
img_rows_V_out_din,
img_rows_V_out_full_n,
img_rows_V_out_write,
img_cols_V_out_din,
img_cols_V_out_full_n,
img_cols_V_out_write
);
parameter ap_ST_fsm_state1 = 8'd1;
parameter ap_ST_fsm_state2 = 8'd2;
parameter ap_ST_fsm_state3 = 8'd4;
parameter ap_ST_fsm_state4 = 8'd8;
parameter ap_ST_fsm_pp1_stage0 = 8'd16;
parameter ap_ST_fsm_state7 = 8'd32;
parameter ap_ST_fsm_pp2_stage0 = 8'd64;
parameter ap_ST_fsm_state10 = 8'd128;
input ap_clk;
input ap_rst;
input ap_start;
input start_full_n;
output ap_done;
input ap_continue;
output ap_idle;
output ap_ready;
output start_out;
output start_write;
input [23:0] stream_in_TDATA;
input stream_in_TVALID;
output stream_in_TREADY;
input [2:0] stream_in_TKEEP;
input [2:0] stream_in_TSTRB;
input [0:0] stream_in_TUSER;
input [0:0] stream_in_TLAST;
input [0:0] stream_in_TID;
input [0:0] stream_in_TDEST;
input [15:0] img_rows_V_dout;
input img_rows_V_empty_n;
output img_rows_V_read;
input [15:0] img_cols_V_dout;
input img_cols_V_empty_n;
output img_cols_V_read;
output [7:0] img_data_stream_0_V_din;
input img_data_stream_0_V_full_n;
output img_data_stream_0_V_write;
output [7:0] img_data_stream_1_V_din;
input img_data_stream_1_V_full_n;
output img_data_stream_1_V_write;
output [7:0] img_data_stream_2_V_din;
input img_data_stream_2_V_full_n;
output img_data_stream_2_V_write;
output [15:0] img_rows_V_out_din;
input img_rows_V_out_full_n;
output img_rows_V_out_write;
output [15:0] img_cols_V_out_din;
input img_cols_V_out_full_n;
output img_cols_V_out_write;
reg ap_done;
reg ap_idle;
reg start_write;
reg img_rows_V_read;
reg img_cols_V_read;
reg img_data_stream_0_V_write;
reg img_data_stream_1_V_write;
reg img_data_stream_2_V_write;
reg img_rows_V_out_write;
reg img_cols_V_out_write;
reg real_start;
reg start_once_reg;
reg ap_done_reg;
(* fsm_encoding = "none" *) reg [7:0] ap_CS_fsm;
wire ap_CS_fsm_state1;
reg internal_ap_ready;
reg [23:0] AXI_video_strm_V_data_V_0_data_out;
wire AXI_video_strm_V_data_V_0_vld_in;
wire AXI_video_strm_V_data_V_0_vld_out;
wire AXI_video_strm_V_data_V_0_ack_in;
reg AXI_video_strm_V_data_V_0_ack_out;
reg [23:0] AXI_video_strm_V_data_V_0_payload_A;
reg [23:0] AXI_video_strm_V_data_V_0_payload_B;
reg AXI_video_strm_V_data_V_0_sel_rd;
reg AXI_video_strm_V_data_V_0_sel_wr;
wire AXI_video_strm_V_data_V_0_sel;
wire AXI_video_strm_V_data_V_0_load_A;
wire AXI_video_strm_V_data_V_0_load_B;
reg [1:0] AXI_video_strm_V_data_V_0_state;
wire AXI_video_strm_V_data_V_0_state_cmp_full;
reg [0:0] AXI_video_strm_V_user_V_0_data_out;
wire AXI_video_strm_V_user_V_0_vld_in;
wire AXI_video_strm_V_user_V_0_vld_out;
wire AXI_video_strm_V_user_V_0_ack_in;
reg AXI_video_strm_V_user_V_0_ack_out;
reg [0:0] AXI_video_strm_V_user_V_0_payload_A;
reg [0:0] AXI_video_strm_V_user_V_0_payload_B;
reg AXI_video_strm_V_user_V_0_sel_rd;
reg AXI_video_strm_V_user_V_0_sel_wr;
wire AXI_video_strm_V_user_V_0_sel;
wire AXI_video_strm_V_user_V_0_load_A;
wire AXI_video_strm_V_user_V_0_load_B;
reg [1:0] AXI_video_strm_V_user_V_0_state;
wire AXI_video_strm_V_user_V_0_state_cmp_full;
reg [0:0] AXI_video_strm_V_last_V_0_data_out;
wire AXI_video_strm_V_last_V_0_vld_in;
wire AXI_video_strm_V_last_V_0_vld_out;
wire AXI_video_strm_V_last_V_0_ack_in;
reg AXI_video_strm_V_last_V_0_ack_out;
reg [0:0] AXI_video_strm_V_last_V_0_payload_A;
reg [0:0] AXI_video_strm_V_last_V_0_payload_B;
reg AXI_video_strm_V_last_V_0_sel_rd;
reg AXI_video_strm_V_last_V_0_sel_wr;
wire AXI_video_strm_V_last_V_0_sel;
wire AXI_video_strm_V_last_V_0_load_A;
wire AXI_video_strm_V_last_V_0_load_B;
reg [1:0] AXI_video_strm_V_last_V_0_state;
wire AXI_video_strm_V_last_V_0_state_cmp_full;
wire AXI_video_strm_V_dest_V_0_vld_in;
reg AXI_video_strm_V_dest_V_0_ack_out;
reg [1:0] AXI_video_strm_V_dest_V_0_state;
reg stream_in_TDATA_blk_n;
wire ap_CS_fsm_state2;
wire ap_CS_fsm_pp1_stage0;
reg ap_enable_reg_pp1_iter1;
wire ap_block_pp1_stage0;
reg [0:0] exitcond_i_reg_442;
reg [0:0] brmerge_i_reg_451;
wire ap_CS_fsm_pp2_stage0;
reg ap_enable_reg_pp2_iter1;
wire ap_block_pp2_stage0;
reg [0:0] eol_2_i_reg_270;
reg img_rows_V_blk_n;
reg img_cols_V_blk_n;
reg img_data_stream_0_V_blk_n;
reg img_data_stream_1_V_blk_n;
reg img_data_stream_2_V_blk_n;
reg img_rows_V_out_blk_n;
reg img_cols_V_out_blk_n;
reg [10:0] t_V_2_reg_200;
reg [0:0] eol_i_reg_211;
reg [0:0] eol_reg_223;
reg [23:0] axi_data_V_1_i_reg_234;
reg [0:0] axi_last_V_3_i_reg_281;
reg [23:0] axi_data_V_3_i_reg_293;
wire [11:0] tmp_fu_315_p1;
reg [11:0] tmp_reg_403;
reg ap_block_state1;
wire [11:0] tmp_44_fu_319_p1;
reg [11:0] tmp_44_reg_408;
reg [23:0] tmp_data_V_reg_413;
reg [0:0] tmp_last_V_reg_421;
wire [0:0] exitcond2_i_fu_336_p2;
wire ap_CS_fsm_state4;
wire [10:0] i_V_fu_341_p2;
reg [10:0] i_V_reg_437;
wire [0:0] exitcond_i_fu_351_p2;
wire ap_block_state5_pp1_stage0_iter0;
reg ap_predicate_op75_read_state6;
reg ap_block_state6_pp1_stage0_iter1;
reg ap_block_pp1_stage0_11001;
wire [10:0] j_V_fu_356_p2;
reg ap_enable_reg_pp1_iter0;
wire [0:0] brmerge_i_fu_365_p2;
wire ap_block_state8_pp2_stage0_iter0;
reg ap_block_state9_pp2_stage0_iter1;
reg ap_block_pp2_stage0_11001;
reg ap_block_pp1_stage0_subdone;
reg ap_enable_reg_pp2_iter0;
wire ap_CS_fsm_state7;
reg ap_block_pp2_stage0_subdone;
reg [0:0] ap_phi_mux_eol_2_i_phi_fu_273_p4;
reg [0:0] axi_last_V1_i_reg_169;
wire ap_CS_fsm_state10;
wire ap_CS_fsm_state3;
reg [23:0] axi_data_V1_i_reg_179;
reg [10:0] t_V_reg_189;
reg [0:0] ap_phi_mux_eol_i_phi_fu_215_p4;
reg [0:0] ap_phi_mux_axi_last_V_2_i_phi_fu_250_p4;
reg [23:0] ap_phi_mux_p_Val2_s_phi_fu_262_p4;
wire [0:0] ap_phi_reg_pp1_iter1_axi_last_V_2_i_reg_245;
wire [23:0] ap_phi_reg_pp1_iter1_p_Val2_s_reg_258;
reg ap_block_pp1_stage0_01001;
reg [0:0] sof_1_i_fu_98;
wire [11:0] t_V_cast_i_fu_332_p1;
wire [11:0] t_V_3_cast_i_fu_347_p1;
wire [0:0] tmp_user_V_fu_323_p1;
reg [7:0] ap_NS_fsm;
reg ap_idle_pp1;
wire ap_enable_pp1;
reg ap_idle_pp2;
wire ap_enable_pp2;
reg ap_condition_529;
// power-on initialization
initial begin
#0 start_once_reg = 1'b0;
#0 ap_done_reg = 1'b0;
#0 ap_CS_fsm = 8'd1;
#0 AXI_video_strm_V_data_V_0_sel_rd = 1'b0;
#0 AXI_video_strm_V_data_V_0_sel_wr = 1'b0;
#0 AXI_video_strm_V_data_V_0_state = 2'd0;
#0 AXI_video_strm_V_user_V_0_sel_rd = 1'b0;
#0 AXI_video_strm_V_user_V_0_sel_wr = 1'b0;
#0 AXI_video_strm_V_user_V_0_state = 2'd0;
#0 AXI_video_strm_V_last_V_0_sel_rd = 1'b0;
#0 AXI_video_strm_V_last_V_0_sel_wr = 1'b0;
#0 AXI_video_strm_V_last_V_0_state = 2'd0;
#0 AXI_video_strm_V_dest_V_0_state = 2'd0;
#0 ap_enable_reg_pp1_iter1 = 1'b0;
#0 ap_enable_reg_pp2_iter1 = 1'b0;
#0 ap_enable_reg_pp1_iter0 = 1'b0;
#0 ap_enable_reg_pp2_iter0 = 1'b0;
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
AXI_video_strm_V_data_V_0_sel_rd <= 1'b0;
end else begin
if (((1'b1 == AXI_video_strm_V_data_V_0_ack_out) & (1'b1 == AXI_video_strm_V_data_V_0_vld_out))) begin
AXI_video_strm_V_data_V_0_sel_rd <= ~AXI_video_strm_V_data_V_0_sel_rd;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
AXI_video_strm_V_data_V_0_sel_wr <= 1'b0;
end else begin
if (((1'b1 == AXI_video_strm_V_data_V_0_ack_in) & (1'b1 == AXI_video_strm_V_data_V_0_vld_in))) begin
AXI_video_strm_V_data_V_0_sel_wr <= ~AXI_video_strm_V_data_V_0_sel_wr;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
AXI_video_strm_V_data_V_0_state <= 2'd0;
end else begin
if ((((2'd2 == AXI_video_strm_V_data_V_0_state) & (1'b0 == AXI_video_strm_V_data_V_0_vld_in)) | ((2'd3 == AXI_video_strm_V_data_V_0_state) & (1'b0 == AXI_video_strm_V_data_V_0_vld_in) & (1'b1 == AXI_video_strm_V_data_V_0_ack_out)))) begin
AXI_video_strm_V_data_V_0_state <= 2'd2;
end else if ((((2'd1 == AXI_video_strm_V_data_V_0_state) & (1'b0 == AXI_video_strm_V_data_V_0_ack_out)) | ((2'd3 == AXI_video_strm_V_data_V_0_state) & (1'b0 == AXI_video_strm_V_data_V_0_ack_out) & (1'b1 == AXI_video_strm_V_data_V_0_vld_in)))) begin
AXI_video_strm_V_data_V_0_state <= 2'd1;
end else if (((~((1'b0 == AXI_video_strm_V_data_V_0_vld_in) & (1'b1 == AXI_video_strm_V_data_V_0_ack_out)) & ~((1'b0 == AXI_video_strm_V_data_V_0_ack_out) & (1'b1 == AXI_video_strm_V_data_V_0_vld_in)) & (2'd3 == AXI_video_strm_V_data_V_0_state)) | ((2'd1 == AXI_video_strm_V_data_V_0_state) & (1'b1 == AXI_video_strm_V_data_V_0_ack_out)) | ((2'd2 == AXI_video_strm_V_data_V_0_state) & (1'b1 == AXI_video_strm_V_data_V_0_vld_in)))) begin
AXI_video_strm_V_data_V_0_state <= 2'd3;
end else begin
AXI_video_strm_V_data_V_0_state <= 2'd2;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
AXI_video_strm_V_dest_V_0_state <= 2'd0;
end else begin
if ((((2'd2 == AXI_video_strm_V_dest_V_0_state) & (1'b0 == AXI_video_strm_V_dest_V_0_vld_in)) | ((2'd3 == AXI_video_strm_V_dest_V_0_state) & (1'b0 == AXI_video_strm_V_dest_V_0_vld_in) & (1'b1 == AXI_video_strm_V_dest_V_0_ack_out)))) begin
AXI_video_strm_V_dest_V_0_state <= 2'd2;
end else if ((((2'd1 == AXI_video_strm_V_dest_V_0_state) & (1'b0 == AXI_video_strm_V_dest_V_0_ack_out)) | ((2'd3 == AXI_video_strm_V_dest_V_0_state) & (1'b0 == AXI_video_strm_V_dest_V_0_ack_out) & (1'b1 == AXI_video_strm_V_dest_V_0_vld_in)))) begin
AXI_video_strm_V_dest_V_0_state <= 2'd1;
end else if (((~((1'b0 == AXI_video_strm_V_dest_V_0_vld_in) & (1'b1 == AXI_video_strm_V_dest_V_0_ack_out)) & ~((1'b0 == AXI_video_strm_V_dest_V_0_ack_out) & (1'b1 == AXI_video_strm_V_dest_V_0_vld_in)) & (2'd3 == AXI_video_strm_V_dest_V_0_state)) | ((2'd1 == AXI_video_strm_V_dest_V_0_state) & (1'b1 == AXI_video_strm_V_dest_V_0_ack_out)) | ((2'd2 == AXI_video_strm_V_dest_V_0_state) & (1'b1 == AXI_video_strm_V_dest_V_0_vld_in)))) begin
AXI_video_strm_V_dest_V_0_state <= 2'd3;
end else begin
AXI_video_strm_V_dest_V_0_state <= 2'd2;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
AXI_video_strm_V_last_V_0_sel_rd <= 1'b0;
end else begin
if (((1'b1 == AXI_video_strm_V_last_V_0_ack_out) & (1'b1 == AXI_video_strm_V_last_V_0_vld_out))) begin
AXI_video_strm_V_last_V_0_sel_rd <= ~AXI_video_strm_V_last_V_0_sel_rd;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
AXI_video_strm_V_last_V_0_sel_wr <= 1'b0;
end else begin
if (((1'b1 == AXI_video_strm_V_last_V_0_ack_in) & (1'b1 == AXI_video_strm_V_last_V_0_vld_in))) begin
AXI_video_strm_V_last_V_0_sel_wr <= ~AXI_video_strm_V_last_V_0_sel_wr;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
AXI_video_strm_V_last_V_0_state <= 2'd0;
end else begin
if ((((2'd2 == AXI_video_strm_V_last_V_0_state) & (1'b0 == AXI_video_strm_V_last_V_0_vld_in)) | ((2'd3 == AXI_video_strm_V_last_V_0_state) & (1'b0 == AXI_video_strm_V_last_V_0_vld_in) & (1'b1 == AXI_video_strm_V_last_V_0_ack_out)))) begin
AXI_video_strm_V_last_V_0_state <= 2'd2;
end else if ((((2'd1 == AXI_video_strm_V_last_V_0_state) & (1'b0 == AXI_video_strm_V_last_V_0_ack_out)) | ((2'd3 == AXI_video_strm_V_last_V_0_state) & (1'b0 == AXI_video_strm_V_last_V_0_ack_out) & (1'b1 == AXI_video_strm_V_last_V_0_vld_in)))) begin
AXI_video_strm_V_last_V_0_state <= 2'd1;
end else if (((~((1'b0 == AXI_video_strm_V_last_V_0_vld_in) & (1'b1 == AXI_video_strm_V_last_V_0_ack_out)) & ~((1'b0 == AXI_video_strm_V_last_V_0_ack_out) & (1'b1 == AXI_video_strm_V_last_V_0_vld_in)) & (2'd3 == AXI_video_strm_V_last_V_0_state)) | ((2'd1 == AXI_video_strm_V_last_V_0_state) & (1'b1 == AXI_video_strm_V_last_V_0_ack_out)) | ((2'd2 == AXI_video_strm_V_last_V_0_state) & (1'b1 == AXI_video_strm_V_last_V_0_vld_in)))) begin
AXI_video_strm_V_last_V_0_state <= 2'd3;
end else begin
AXI_video_strm_V_last_V_0_state <= 2'd2;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
AXI_video_strm_V_user_V_0_sel_rd <= 1'b0;
end else begin
if (((1'b1 == AXI_video_strm_V_user_V_0_ack_out) & (1'b1 == AXI_video_strm_V_user_V_0_vld_out))) begin
AXI_video_strm_V_user_V_0_sel_rd <= ~AXI_video_strm_V_user_V_0_sel_rd;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
AXI_video_strm_V_user_V_0_sel_wr <= 1'b0;
end else begin
if (((1'b1 == AXI_video_strm_V_user_V_0_ack_in) & (1'b1 == AXI_video_strm_V_user_V_0_vld_in))) begin
AXI_video_strm_V_user_V_0_sel_wr <= ~AXI_video_strm_V_user_V_0_sel_wr;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
AXI_video_strm_V_user_V_0_state <= 2'd0;
end else begin
if ((((2'd2 == AXI_video_strm_V_user_V_0_state) & (1'b0 == AXI_video_strm_V_user_V_0_vld_in)) | ((2'd3 == AXI_video_strm_V_user_V_0_state) & (1'b0 == AXI_video_strm_V_user_V_0_vld_in) & (1'b1 == AXI_video_strm_V_user_V_0_ack_out)))) begin
AXI_video_strm_V_user_V_0_state <= 2'd2;
end else if ((((2'd1 == AXI_video_strm_V_user_V_0_state) & (1'b0 == AXI_video_strm_V_user_V_0_ack_out)) | ((2'd3 == AXI_video_strm_V_user_V_0_state) & (1'b0 == AXI_video_strm_V_user_V_0_ack_out) & (1'b1 == AXI_video_strm_V_user_V_0_vld_in)))) begin
AXI_video_strm_V_user_V_0_state <= 2'd1;
end else if (((~((1'b0 == AXI_video_strm_V_user_V_0_vld_in) & (1'b1 == AXI_video_strm_V_user_V_0_ack_out)) & ~((1'b0 == AXI_video_strm_V_user_V_0_ack_out) & (1'b1 == AXI_video_strm_V_user_V_0_vld_in)) & (2'd3 == AXI_video_strm_V_user_V_0_state)) | ((2'd1 == AXI_video_strm_V_user_V_0_state) & (1'b1 == AXI_video_strm_V_user_V_0_ack_out)) | ((2'd2 == AXI_video_strm_V_user_V_0_state) & (1'b1 == AXI_video_strm_V_user_V_0_vld_in)))) begin
AXI_video_strm_V_user_V_0_state <= 2'd3;
end else begin
AXI_video_strm_V_user_V_0_state <= 2'd2;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_CS_fsm <= ap_ST_fsm_state1;
end else begin
ap_CS_fsm <= ap_NS_fsm;
end
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_done_reg <= 1'b0;
end else begin
if ((ap_continue == 1'b1)) begin
ap_done_reg <= 1'b0;
end else if (((exitcond2_i_fu_336_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state4))) begin
ap_done_reg <= 1'b1;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_enable_reg_pp1_iter0 <= 1'b0;
end else begin
if (((exitcond_i_fu_351_p2 == 1'd1) & (1'b0 == ap_block_pp1_stage0_subdone) & (1'b1 == ap_CS_fsm_pp1_stage0))) begin
ap_enable_reg_pp1_iter0 <= 1'b0;
end else if (((exitcond2_i_fu_336_p2 == 1'd0) & (1'b1 == ap_CS_fsm_state4))) begin
ap_enable_reg_pp1_iter0 <= 1'b1;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_enable_reg_pp1_iter1 <= 1'b0;
end else begin
if ((1'b0 == ap_block_pp1_stage0_subdone)) begin
ap_enable_reg_pp1_iter1 <= ap_enable_reg_pp1_iter0;
end else if (((exitcond2_i_fu_336_p2 == 1'd0) & (1'b1 == ap_CS_fsm_state4))) begin
ap_enable_reg_pp1_iter1 <= 1'b0;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_enable_reg_pp2_iter0 <= 1'b0;
end else begin
if (((ap_phi_mux_eol_2_i_phi_fu_273_p4 == 1'd1) & (1'b0 == ap_block_pp2_stage0_subdone) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
ap_enable_reg_pp2_iter0 <= 1'b0;
end else if ((1'b1 == ap_CS_fsm_state7)) begin
ap_enable_reg_pp2_iter0 <= 1'b1;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_enable_reg_pp2_iter1 <= 1'b0;
end else begin
if ((1'b0 == ap_block_pp2_stage0_subdone)) begin
ap_enable_reg_pp2_iter1 <= ap_enable_reg_pp2_iter0;
end else if ((1'b1 == ap_CS_fsm_state7)) begin
ap_enable_reg_pp2_iter1 <= 1'b0;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
start_once_reg <= 1'b0;
end else begin
if (((internal_ap_ready == 1'b0) & (real_start == 1'b1))) begin
start_once_reg <= 1'b1;
end else if ((internal_ap_ready == 1'b1)) begin
start_once_reg <= 1'b0;
end
end
end
always @ (posedge ap_clk) begin
if ((1'b1 == ap_CS_fsm_state3)) begin
axi_data_V1_i_reg_179 <= tmp_data_V_reg_413;
end else if ((1'b1 == ap_CS_fsm_state10)) begin
axi_data_V1_i_reg_179 <= axi_data_V_3_i_reg_293;
end
end
always @ (posedge ap_clk) begin
if (((exitcond_i_reg_442 == 1'd0) & (1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp1_stage0))) begin
axi_data_V_1_i_reg_234 <= ap_phi_mux_p_Val2_s_phi_fu_262_p4;
end else if (((exitcond2_i_fu_336_p2 == 1'd0) & (1'b1 == ap_CS_fsm_state4))) begin
axi_data_V_1_i_reg_234 <= axi_data_V1_i_reg_179;
end
end
always @ (posedge ap_clk) begin
if ((1'b1 == ap_CS_fsm_state7)) begin
axi_data_V_3_i_reg_293 <= axi_data_V_1_i_reg_234;
end else if (((eol_2_i_reg_270 == 1'd0) & (1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
axi_data_V_3_i_reg_293 <= AXI_video_strm_V_data_V_0_data_out;
end
end
always @ (posedge ap_clk) begin
if ((1'b1 == ap_CS_fsm_state3)) begin
axi_last_V1_i_reg_169 <= tmp_last_V_reg_421;
end else if ((1'b1 == ap_CS_fsm_state10)) begin
axi_last_V1_i_reg_169 <= axi_last_V_3_i_reg_281;
end
end
always @ (posedge ap_clk) begin
if ((1'b1 == ap_CS_fsm_state7)) begin
axi_last_V_3_i_reg_281 <= eol_reg_223;
end else if (((eol_2_i_reg_270 == 1'd0) & (1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
axi_last_V_3_i_reg_281 <= AXI_video_strm_V_last_V_0_data_out;
end
end
always @ (posedge ap_clk) begin
if ((1'b1 == ap_CS_fsm_state7)) begin
eol_2_i_reg_270 <= eol_i_reg_211;
end else if (((eol_2_i_reg_270 == 1'd0) & (1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
eol_2_i_reg_270 <= AXI_video_strm_V_last_V_0_data_out;
end
end
always @ (posedge ap_clk) begin
if (((exitcond_i_reg_442 == 1'd0) & (1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp1_stage0))) begin
eol_i_reg_211 <= ap_phi_mux_axi_last_V_2_i_phi_fu_250_p4;
end else if (((exitcond2_i_fu_336_p2 == 1'd0) & (1'b1 == ap_CS_fsm_state4))) begin
eol_i_reg_211 <= 1'd0;
end
end
always @ (posedge ap_clk) begin
if (((exitcond_i_reg_442 == 1'd0) & (1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp1_stage0))) begin
eol_reg_223 <= ap_phi_mux_axi_last_V_2_i_phi_fu_250_p4;
end else if (((exitcond2_i_fu_336_p2 == 1'd0) & (1'b1 == ap_CS_fsm_state4))) begin
eol_reg_223 <= axi_last_V1_i_reg_169;
end
end
always @ (posedge ap_clk) begin
if (((exitcond_i_fu_351_p2 == 1'd0) & (1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp1_stage0))) begin
sof_1_i_fu_98 <= 1'd0;
end else if ((1'b1 == ap_CS_fsm_state3)) begin
sof_1_i_fu_98 <= 1'd1;
end
end
always @ (posedge ap_clk) begin
if (((exitcond_i_fu_351_p2 == 1'd0) & (1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp1_stage0))) begin
t_V_2_reg_200 <= j_V_fu_356_p2;
end else if (((exitcond2_i_fu_336_p2 == 1'd0) & (1'b1 == ap_CS_fsm_state4))) begin
t_V_2_reg_200 <= 11'd0;
end
end
always @ (posedge ap_clk) begin
if ((1'b1 == ap_CS_fsm_state3)) begin
t_V_reg_189 <= 11'd0;
end else if ((1'b1 == ap_CS_fsm_state10)) begin
t_V_reg_189 <= i_V_reg_437;
end
end
always @ (posedge ap_clk) begin
if ((1'b1 == AXI_video_strm_V_data_V_0_load_A)) begin
AXI_video_strm_V_data_V_0_payload_A <= stream_in_TDATA;
end
end
always @ (posedge ap_clk) begin
if ((1'b1 == AXI_video_strm_V_data_V_0_load_B)) begin
AXI_video_strm_V_data_V_0_payload_B <= stream_in_TDATA;
end
end
always @ (posedge ap_clk) begin
if ((1'b1 == AXI_video_strm_V_last_V_0_load_A)) begin
AXI_video_strm_V_last_V_0_payload_A <= stream_in_TLAST;
end
end
always @ (posedge ap_clk) begin
if ((1'b1 == AXI_video_strm_V_last_V_0_load_B)) begin
AXI_video_strm_V_last_V_0_payload_B <= stream_in_TLAST;
end
end
always @ (posedge ap_clk) begin
if ((1'b1 == AXI_video_strm_V_user_V_0_load_A)) begin
AXI_video_strm_V_user_V_0_payload_A <= stream_in_TUSER;
end
end
always @ (posedge ap_clk) begin
if ((1'b1 == AXI_video_strm_V_user_V_0_load_B)) begin
AXI_video_strm_V_user_V_0_payload_B <= stream_in_TUSER;
end
end
always @ (posedge ap_clk) begin
if (((exitcond_i_fu_351_p2 == 1'd0) & (1'b0 == ap_block_pp1_stage0_11001) & (1'b1 == ap_CS_fsm_pp1_stage0))) begin
brmerge_i_reg_451 <= brmerge_i_fu_365_p2;
end
end
always @ (posedge ap_clk) begin
if (((1'b0 == ap_block_pp1_stage0_11001) & (1'b1 == ap_CS_fsm_pp1_stage0))) begin
exitcond_i_reg_442 <= exitcond_i_fu_351_p2;
end
end
always @ (posedge ap_clk) begin
if ((1'b1 == ap_CS_fsm_state4)) begin
i_V_reg_437 <= i_V_fu_341_p2;
end
end
always @ (posedge ap_clk) begin
if ((~((img_cols_V_out_full_n == 1'b0) | (img_rows_V_out_full_n == 1'b0) | (img_cols_V_empty_n == 1'b0) | (img_rows_V_empty_n == 1'b0) | (real_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
tmp_44_reg_408 <= tmp_44_fu_319_p1;
tmp_reg_403 <= tmp_fu_315_p1;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == AXI_video_strm_V_data_V_0_vld_out) & (1'b1 == ap_CS_fsm_state2))) begin
tmp_data_V_reg_413 <= AXI_video_strm_V_data_V_0_data_out;
tmp_last_V_reg_421 <= AXI_video_strm_V_last_V_0_data_out;
end
end
always @ (*) begin
if ((((eol_2_i_reg_270 == 1'd0) & (1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0)) | ((1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp1_stage0) & (ap_predicate_op75_read_state6 == 1'b1)) | ((1'b1 == AXI_video_strm_V_data_V_0_vld_out) & (1'b1 == ap_CS_fsm_state2)))) begin
AXI_video_strm_V_data_V_0_ack_out = 1'b1;
end else begin
AXI_video_strm_V_data_V_0_ack_out = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == AXI_video_strm_V_data_V_0_sel)) begin
AXI_video_strm_V_data_V_0_data_out = AXI_video_strm_V_data_V_0_payload_B;
end else begin
AXI_video_strm_V_data_V_0_data_out = AXI_video_strm_V_data_V_0_payload_A;
end
end
always @ (*) begin
if ((((eol_2_i_reg_270 == 1'd0) & (1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0)) | ((1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp1_stage0) & (ap_predicate_op75_read_state6 == 1'b1)) | ((1'b1 == AXI_video_strm_V_data_V_0_vld_out) & (1'b1 == ap_CS_fsm_state2)))) begin
AXI_video_strm_V_dest_V_0_ack_out = 1'b1;
end else begin
AXI_video_strm_V_dest_V_0_ack_out = 1'b0;
end
end
always @ (*) begin
if ((((eol_2_i_reg_270 == 1'd0) & (1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0)) | ((1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp1_stage0) & (ap_predicate_op75_read_state6 == 1'b1)) | ((1'b1 == AXI_video_strm_V_data_V_0_vld_out) & (1'b1 == ap_CS_fsm_state2)))) begin
AXI_video_strm_V_last_V_0_ack_out = 1'b1;
end else begin
AXI_video_strm_V_last_V_0_ack_out = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == AXI_video_strm_V_last_V_0_sel)) begin
AXI_video_strm_V_last_V_0_data_out = AXI_video_strm_V_last_V_0_payload_B;
end else begin
AXI_video_strm_V_last_V_0_data_out = AXI_video_strm_V_last_V_0_payload_A;
end
end
always @ (*) begin
if ((((eol_2_i_reg_270 == 1'd0) & (1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0)) | ((1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp1_stage0) & (ap_predicate_op75_read_state6 == 1'b1)) | ((1'b1 == AXI_video_strm_V_data_V_0_vld_out) & (1'b1 == ap_CS_fsm_state2)))) begin
AXI_video_strm_V_user_V_0_ack_out = 1'b1;
end else begin
AXI_video_strm_V_user_V_0_ack_out = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == AXI_video_strm_V_user_V_0_sel)) begin
AXI_video_strm_V_user_V_0_data_out = AXI_video_strm_V_user_V_0_payload_B;
end else begin
AXI_video_strm_V_user_V_0_data_out = AXI_video_strm_V_user_V_0_payload_A;
end
end
always @ (*) begin
if (((exitcond2_i_fu_336_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state4))) begin
ap_done = 1'b1;
end else begin
ap_done = ap_done_reg;
end
end
always @ (*) begin
if (((real_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin
ap_idle = 1'b1;
end else begin
ap_idle = 1'b0;
end
end
always @ (*) begin
if (((ap_enable_reg_pp1_iter0 == 1'b0) & (ap_enable_reg_pp1_iter1 == 1'b0))) begin
ap_idle_pp1 = 1'b1;
end else begin
ap_idle_pp1 = 1'b0;
end
end
always @ (*) begin
if (((ap_enable_reg_pp2_iter0 == 1'b0) & (ap_enable_reg_pp2_iter1 == 1'b0))) begin
ap_idle_pp2 = 1'b1;
end else begin
ap_idle_pp2 = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_condition_529)) begin
if ((brmerge_i_reg_451 == 1'd1)) begin
ap_phi_mux_axi_last_V_2_i_phi_fu_250_p4 = eol_reg_223;
end else if ((brmerge_i_reg_451 == 1'd0)) begin
ap_phi_mux_axi_last_V_2_i_phi_fu_250_p4 = AXI_video_strm_V_last_V_0_data_out;
end else begin
ap_phi_mux_axi_last_V_2_i_phi_fu_250_p4 = ap_phi_reg_pp1_iter1_axi_last_V_2_i_reg_245;
end
end else begin
ap_phi_mux_axi_last_V_2_i_phi_fu_250_p4 = ap_phi_reg_pp1_iter1_axi_last_V_2_i_reg_245;
end
end
always @ (*) begin
if (((eol_2_i_reg_270 == 1'd0) & (1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
ap_phi_mux_eol_2_i_phi_fu_273_p4 = AXI_video_strm_V_last_V_0_data_out;
end else begin
ap_phi_mux_eol_2_i_phi_fu_273_p4 = eol_2_i_reg_270;
end
end
always @ (*) begin
if (((exitcond_i_reg_442 == 1'd0) & (1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp1_stage0))) begin
ap_phi_mux_eol_i_phi_fu_215_p4 = ap_phi_mux_axi_last_V_2_i_phi_fu_250_p4;
end else begin
ap_phi_mux_eol_i_phi_fu_215_p4 = eol_i_reg_211;
end
end
always @ (*) begin
if ((1'b1 == ap_condition_529)) begin
if ((brmerge_i_reg_451 == 1'd1)) begin
ap_phi_mux_p_Val2_s_phi_fu_262_p4 = axi_data_V_1_i_reg_234;
end else if ((brmerge_i_reg_451 == 1'd0)) begin
ap_phi_mux_p_Val2_s_phi_fu_262_p4 = AXI_video_strm_V_data_V_0_data_out;
end else begin
ap_phi_mux_p_Val2_s_phi_fu_262_p4 = ap_phi_reg_pp1_iter1_p_Val2_s_reg_258;
end
end else begin
ap_phi_mux_p_Val2_s_phi_fu_262_p4 = ap_phi_reg_pp1_iter1_p_Val2_s_reg_258;
end
end
always @ (*) begin
if ((~((real_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
img_cols_V_blk_n = img_cols_V_empty_n;
end else begin
img_cols_V_blk_n = 1'b1;
end
end
always @ (*) begin
if ((~((real_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
img_cols_V_out_blk_n = img_cols_V_out_full_n;
end else begin
img_cols_V_out_blk_n = 1'b1;
end
end
always @ (*) begin
if ((~((img_cols_V_out_full_n == 1'b0) | (img_rows_V_out_full_n == 1'b0) | (img_cols_V_empty_n == 1'b0) | (img_rows_V_empty_n == 1'b0) | (real_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
img_cols_V_out_write = 1'b1;
end else begin
img_cols_V_out_write = 1'b0;
end
end
always @ (*) begin
if ((~((img_cols_V_out_full_n == 1'b0) | (img_rows_V_out_full_n == 1'b0) | (img_cols_V_empty_n == 1'b0) | (img_rows_V_empty_n == 1'b0) | (real_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
img_cols_V_read = 1'b1;
end else begin
img_cols_V_read = 1'b0;
end
end
always @ (*) begin
if (((exitcond_i_reg_442 == 1'd0) & (1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp1_stage0))) begin
img_data_stream_0_V_blk_n = img_data_stream_0_V_full_n;
end else begin
img_data_stream_0_V_blk_n = 1'b1;
end
end
always @ (*) begin
if (((exitcond_i_reg_442 == 1'd0) & (1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp1_stage0))) begin
img_data_stream_0_V_write = 1'b1;
end else begin
img_data_stream_0_V_write = 1'b0;
end
end
always @ (*) begin
if (((exitcond_i_reg_442 == 1'd0) & (1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp1_stage0))) begin
img_data_stream_1_V_blk_n = img_data_stream_1_V_full_n;
end else begin
img_data_stream_1_V_blk_n = 1'b1;
end
end
always @ (*) begin
if (((exitcond_i_reg_442 == 1'd0) & (1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp1_stage0))) begin
img_data_stream_1_V_write = 1'b1;
end else begin
img_data_stream_1_V_write = 1'b0;
end
end
always @ (*) begin
if (((exitcond_i_reg_442 == 1'd0) & (1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp1_stage0))) begin
img_data_stream_2_V_blk_n = img_data_stream_2_V_full_n;
end else begin
img_data_stream_2_V_blk_n = 1'b1;
end
end
always @ (*) begin
if (((exitcond_i_reg_442 == 1'd0) & (1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp1_stage0))) begin
img_data_stream_2_V_write = 1'b1;
end else begin
img_data_stream_2_V_write = 1'b0;
end
end
always @ (*) begin
if ((~((real_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
img_rows_V_blk_n = img_rows_V_empty_n;
end else begin
img_rows_V_blk_n = 1'b1;
end
end
always @ (*) begin
if ((~((real_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
img_rows_V_out_blk_n = img_rows_V_out_full_n;
end else begin
img_rows_V_out_blk_n = 1'b1;
end
end
always @ (*) begin
if ((~((img_cols_V_out_full_n == 1'b0) | (img_rows_V_out_full_n == 1'b0) | (img_cols_V_empty_n == 1'b0) | (img_rows_V_empty_n == 1'b0) | (real_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
img_rows_V_out_write = 1'b1;
end else begin
img_rows_V_out_write = 1'b0;
end
end
always @ (*) begin
if ((~((img_cols_V_out_full_n == 1'b0) | (img_rows_V_out_full_n == 1'b0) | (img_cols_V_empty_n == 1'b0) | (img_rows_V_empty_n == 1'b0) | (real_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
img_rows_V_read = 1'b1;
end else begin
img_rows_V_read = 1'b0;
end
end
always @ (*) begin
if (((exitcond2_i_fu_336_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state4))) begin
internal_ap_ready = 1'b1;
end else begin
internal_ap_ready = 1'b0;
end
end
always @ (*) begin
if (((start_once_reg == 1'b0) & (start_full_n == 1'b0))) begin
real_start = 1'b0;
end else begin
real_start = ap_start;
end
end
always @ (*) begin
if (((start_once_reg == 1'b0) & (real_start == 1'b1))) begin
start_write = 1'b1;
end else begin
start_write = 1'b0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state2) | ((eol_2_i_reg_270 == 1'd0) & (1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0)) | ((brmerge_i_reg_451 == 1'd0) & (exitcond_i_reg_442 == 1'd0) & (1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp1_stage0)))) begin
stream_in_TDATA_blk_n = AXI_video_strm_V_data_V_0_state[1'd0];
end else begin
stream_in_TDATA_blk_n = 1'b1;
end
end
always @ (*) begin
case (ap_CS_fsm)
ap_ST_fsm_state1 : begin
if ((~((img_cols_V_out_full_n == 1'b0) | (img_rows_V_out_full_n == 1'b0) | (img_cols_V_empty_n == 1'b0) | (img_rows_V_empty_n == 1'b0) | (real_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
ap_NS_fsm = ap_ST_fsm_state2;
end else begin
ap_NS_fsm = ap_ST_fsm_state1;
end
end
ap_ST_fsm_state2 : begin
if (((tmp_user_V_fu_323_p1 == 1'd0) & (1'b1 == AXI_video_strm_V_data_V_0_vld_out) & (1'b1 == ap_CS_fsm_state2))) begin
ap_NS_fsm = ap_ST_fsm_state2;
end else if (((tmp_user_V_fu_323_p1 == 1'd1) & (1'b1 == AXI_video_strm_V_data_V_0_vld_out) & (1'b1 == ap_CS_fsm_state2))) begin
ap_NS_fsm = ap_ST_fsm_state3;
end else begin
ap_NS_fsm = ap_ST_fsm_state2;
end
end
ap_ST_fsm_state3 : begin
ap_NS_fsm = ap_ST_fsm_state4;
end
ap_ST_fsm_state4 : begin
if (((exitcond2_i_fu_336_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state4))) begin
ap_NS_fsm = ap_ST_fsm_state1;
end else begin
ap_NS_fsm = ap_ST_fsm_pp1_stage0;
end
end
ap_ST_fsm_pp1_stage0 : begin
if (~((1'b0 == ap_block_pp1_stage0_subdone) & (ap_enable_reg_pp1_iter0 == 1'b0) & (ap_enable_reg_pp1_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp1_stage0))) begin
ap_NS_fsm = ap_ST_fsm_pp1_stage0;
end else if (((1'b0 == ap_block_pp1_stage0_subdone) & (ap_enable_reg_pp1_iter0 == 1'b0) & (ap_enable_reg_pp1_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp1_stage0))) begin
ap_NS_fsm = ap_ST_fsm_state7;
end else begin
ap_NS_fsm = ap_ST_fsm_pp1_stage0;
end
end
ap_ST_fsm_state7 : begin
ap_NS_fsm = ap_ST_fsm_pp2_stage0;
end
ap_ST_fsm_pp2_stage0 : begin
if (~((1'b0 == ap_block_pp2_stage0_subdone) & (ap_enable_reg_pp2_iter0 == 1'b0) & (ap_enable_reg_pp2_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
ap_NS_fsm = ap_ST_fsm_pp2_stage0;
end else if (((1'b0 == ap_block_pp2_stage0_subdone) & (ap_enable_reg_pp2_iter0 == 1'b0) & (ap_enable_reg_pp2_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
ap_NS_fsm = ap_ST_fsm_state10;
end else begin
ap_NS_fsm = ap_ST_fsm_pp2_stage0;
end
end
ap_ST_fsm_state10 : begin
ap_NS_fsm = ap_ST_fsm_state4;
end
default : begin
ap_NS_fsm = 'bx;
end
endcase
end
assign AXI_video_strm_V_data_V_0_ack_in = AXI_video_strm_V_data_V_0_state[1'd1];
assign AXI_video_strm_V_data_V_0_load_A = (~AXI_video_strm_V_data_V_0_sel_wr & AXI_video_strm_V_data_V_0_state_cmp_full);
assign AXI_video_strm_V_data_V_0_load_B = (AXI_video_strm_V_data_V_0_state_cmp_full & AXI_video_strm_V_data_V_0_sel_wr);
assign AXI_video_strm_V_data_V_0_sel = AXI_video_strm_V_data_V_0_sel_rd;
assign AXI_video_strm_V_data_V_0_state_cmp_full = ((AXI_video_strm_V_data_V_0_state != 2'd1) ? 1'b1 : 1'b0);
assign AXI_video_strm_V_data_V_0_vld_in = stream_in_TVALID;
assign AXI_video_strm_V_data_V_0_vld_out = AXI_video_strm_V_data_V_0_state[1'd0];
assign AXI_video_strm_V_dest_V_0_vld_in = stream_in_TVALID;
assign AXI_video_strm_V_last_V_0_ack_in = AXI_video_strm_V_last_V_0_state[1'd1];
assign AXI_video_strm_V_last_V_0_load_A = (~AXI_video_strm_V_last_V_0_sel_wr & AXI_video_strm_V_last_V_0_state_cmp_full);
assign AXI_video_strm_V_last_V_0_load_B = (AXI_video_strm_V_last_V_0_state_cmp_full & AXI_video_strm_V_last_V_0_sel_wr);
assign AXI_video_strm_V_last_V_0_sel = AXI_video_strm_V_last_V_0_sel_rd;
assign AXI_video_strm_V_last_V_0_state_cmp_full = ((AXI_video_strm_V_last_V_0_state != 2'd1) ? 1'b1 : 1'b0);
assign AXI_video_strm_V_last_V_0_vld_in = stream_in_TVALID;
assign AXI_video_strm_V_last_V_0_vld_out = AXI_video_strm_V_last_V_0_state[1'd0];
assign AXI_video_strm_V_user_V_0_ack_in = AXI_video_strm_V_user_V_0_state[1'd1];
assign AXI_video_strm_V_user_V_0_load_A = (~AXI_video_strm_V_user_V_0_sel_wr & AXI_video_strm_V_user_V_0_state_cmp_full);
assign AXI_video_strm_V_user_V_0_load_B = (AXI_video_strm_V_user_V_0_state_cmp_full & AXI_video_strm_V_user_V_0_sel_wr);
assign AXI_video_strm_V_user_V_0_sel = AXI_video_strm_V_user_V_0_sel_rd;
assign AXI_video_strm_V_user_V_0_state_cmp_full = ((AXI_video_strm_V_user_V_0_state != 2'd1) ? 1'b1 : 1'b0);
assign AXI_video_strm_V_user_V_0_vld_in = stream_in_TVALID;
assign AXI_video_strm_V_user_V_0_vld_out = AXI_video_strm_V_user_V_0_state[1'd0];
assign ap_CS_fsm_pp1_stage0 = ap_CS_fsm[32'd4];
assign ap_CS_fsm_pp2_stage0 = ap_CS_fsm[32'd6];
assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0];
assign ap_CS_fsm_state10 = ap_CS_fsm[32'd7];
assign ap_CS_fsm_state2 = ap_CS_fsm[32'd1];
assign ap_CS_fsm_state3 = ap_CS_fsm[32'd2];
assign ap_CS_fsm_state4 = ap_CS_fsm[32'd3];
assign ap_CS_fsm_state7 = ap_CS_fsm[32'd5];
assign ap_block_pp1_stage0 = ~(1'b1 == 1'b1);
always @ (*) begin
ap_block_pp1_stage0_01001 = ((ap_enable_reg_pp1_iter1 == 1'b1) & (((1'b0 == AXI_video_strm_V_data_V_0_vld_out) & (ap_predicate_op75_read_state6 == 1'b1)) | ((exitcond_i_reg_442 == 1'd0) & (img_data_stream_2_V_full_n == 1'b0)) | ((exitcond_i_reg_442 == 1'd0) & (img_data_stream_1_V_full_n == 1'b0)) | ((exitcond_i_reg_442 == 1'd0) & (img_data_stream_0_V_full_n == 1'b0))));
end
always @ (*) begin
ap_block_pp1_stage0_11001 = ((ap_enable_reg_pp1_iter1 == 1'b1) & (((1'b0 == AXI_video_strm_V_data_V_0_vld_out) & (ap_predicate_op75_read_state6 == 1'b1)) | ((exitcond_i_reg_442 == 1'd0) & (img_data_stream_2_V_full_n == 1'b0)) | ((exitcond_i_reg_442 == 1'd0) & (img_data_stream_1_V_full_n == 1'b0)) | ((exitcond_i_reg_442 == 1'd0) & (img_data_stream_0_V_full_n == 1'b0))));
end
always @ (*) begin
ap_block_pp1_stage0_subdone = ((ap_enable_reg_pp1_iter1 == 1'b1) & (((1'b0 == AXI_video_strm_V_data_V_0_vld_out) & (ap_predicate_op75_read_state6 == 1'b1)) | ((exitcond_i_reg_442 == 1'd0) & (img_data_stream_2_V_full_n == 1'b0)) | ((exitcond_i_reg_442 == 1'd0) & (img_data_stream_1_V_full_n == 1'b0)) | ((exitcond_i_reg_442 == 1'd0) & (img_data_stream_0_V_full_n == 1'b0))));
end
assign ap_block_pp2_stage0 = ~(1'b1 == 1'b1);
always @ (*) begin
ap_block_pp2_stage0_11001 = ((eol_2_i_reg_270 == 1'd0) & (1'b0 == AXI_video_strm_V_data_V_0_vld_out) & (ap_enable_reg_pp2_iter1 == 1'b1));
end
always @ (*) begin
ap_block_pp2_stage0_subdone = ((eol_2_i_reg_270 == 1'd0) & (1'b0 == AXI_video_strm_V_data_V_0_vld_out) & (ap_enable_reg_pp2_iter1 == 1'b1));
end
always @ (*) begin
ap_block_state1 = ((img_cols_V_out_full_n == 1'b0) | (img_rows_V_out_full_n == 1'b0) | (img_cols_V_empty_n == 1'b0) | (img_rows_V_empty_n == 1'b0) | (real_start == 1'b0) | (ap_done_reg == 1'b1));
end
assign ap_block_state5_pp1_stage0_iter0 = ~(1'b1 == 1'b1);
always @ (*) begin
ap_block_state6_pp1_stage0_iter1 = (((1'b0 == AXI_video_strm_V_data_V_0_vld_out) & (ap_predicate_op75_read_state6 == 1'b1)) | ((exitcond_i_reg_442 == 1'd0) & (img_data_stream_2_V_full_n == 1'b0)) | ((exitcond_i_reg_442 == 1'd0) & (img_data_stream_1_V_full_n == 1'b0)) | ((exitcond_i_reg_442 == 1'd0) & (img_data_stream_0_V_full_n == 1'b0)));
end
assign ap_block_state8_pp2_stage0_iter0 = ~(1'b1 == 1'b1);
always @ (*) begin
ap_block_state9_pp2_stage0_iter1 = ((eol_2_i_reg_270 == 1'd0) & (1'b0 == AXI_video_strm_V_data_V_0_vld_out));
end
always @ (*) begin
ap_condition_529 = ((exitcond_i_reg_442 == 1'd0) & (1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp1_stage0));
end
assign ap_enable_pp1 = (ap_idle_pp1 ^ 1'b1);
assign ap_enable_pp2 = (ap_idle_pp2 ^ 1'b1);
assign ap_phi_reg_pp1_iter1_axi_last_V_2_i_reg_245 = 'bx;
assign ap_phi_reg_pp1_iter1_p_Val2_s_reg_258 = 'bx;
always @ (*) begin
ap_predicate_op75_read_state6 = ((brmerge_i_reg_451 == 1'd0) & (exitcond_i_reg_442 == 1'd0));
end
assign ap_ready = internal_ap_ready;
assign brmerge_i_fu_365_p2 = (sof_1_i_fu_98 | ap_phi_mux_eol_i_phi_fu_215_p4);
assign exitcond2_i_fu_336_p2 = ((t_V_cast_i_fu_332_p1 == tmp_reg_403) ? 1'b1 : 1'b0);
assign exitcond_i_fu_351_p2 = ((t_V_3_cast_i_fu_347_p1 == tmp_44_reg_408) ? 1'b1 : 1'b0);
assign i_V_fu_341_p2 = (t_V_reg_189 + 11'd1);
assign img_cols_V_out_din = img_cols_V_dout;
assign img_data_stream_0_V_din = ap_phi_mux_p_Val2_s_phi_fu_262_p4[7:0];
assign img_data_stream_1_V_din = {{ap_phi_mux_p_Val2_s_phi_fu_262_p4[15:8]}};
assign img_data_stream_2_V_din = {{ap_phi_mux_p_Val2_s_phi_fu_262_p4[23:16]}};
assign img_rows_V_out_din = img_rows_V_dout;
assign j_V_fu_356_p2 = (t_V_2_reg_200 + 11'd1);
assign start_out = real_start;
assign stream_in_TREADY = AXI_video_strm_V_dest_V_0_state[1'd1];
assign t_V_3_cast_i_fu_347_p1 = t_V_2_reg_200;
assign t_V_cast_i_fu_332_p1 = t_V_reg_189;
assign tmp_44_fu_319_p1 = img_cols_V_dout[11:0];
assign tmp_fu_315_p1 = img_rows_V_dout[11:0];
assign tmp_user_V_fu_323_p1 = AXI_video_strm_V_user_V_0_data_out;
endmodule |
module outputs
wire [511 : 0] dma_server_rdata;
wire [63 : 0] dmem_st_amo_val,
dmem_word64,
imem_master_araddr,
imem_master_awaddr,
imem_master_wdata,
imem_pc,
imem_tval,
mem_master_araddr,
mem_master_awaddr,
mem_master_wdata,
mv_tohost_value;
wire [31 : 0] imem_instr;
wire [15 : 0] dma_server_bid, dma_server_rid;
wire [7 : 0] imem_master_arlen,
imem_master_awlen,
imem_master_wstrb,
mem_master_arlen,
mem_master_awlen,
mem_master_wstrb,
mv_status;
wire [3 : 0] dmem_exc_code,
imem_exc_code,
imem_master_arcache,
imem_master_arid,
imem_master_arqos,
imem_master_arregion,
imem_master_awcache,
imem_master_awid,
imem_master_awqos,
imem_master_awregion,
mem_master_arcache,
mem_master_arid,
mem_master_arqos,
mem_master_arregion,
mem_master_awcache,
mem_master_awid,
mem_master_awqos,
mem_master_awregion;
wire [2 : 0] imem_master_arprot,
imem_master_arsize,
imem_master_awprot,
imem_master_awsize,
mem_master_arprot,
mem_master_arsize,
mem_master_awprot,
mem_master_awsize;
wire [1 : 0] dma_server_bresp,
dma_server_rresp,
imem_master_arburst,
imem_master_awburst,
mem_master_arburst,
mem_master_awburst;
wire RDY_ma_ddr4_ready,
RDY_mv_tohost_value,
RDY_server_fence_i_request_put,
RDY_server_fence_i_response_get,
RDY_server_fence_request_put,
RDY_server_fence_response_get,
RDY_server_reset_request_put,
RDY_server_reset_response_get,
RDY_set_watch_tohost,
RDY_sfence_vma_server_request_put,
RDY_sfence_vma_server_response_get,
dma_server_arready,
dma_server_awready,
dma_server_bvalid,
dma_server_rlast,
dma_server_rvalid,
dma_server_wready,
dmem_exc,
dmem_valid,
imem_exc,
imem_is_i32_not_i16,
imem_master_arlock,
imem_master_arvalid,
imem_master_awlock,
imem_master_awvalid,
imem_master_bready,
imem_master_rready,
imem_master_wlast,
imem_master_wvalid,
imem_valid,
mem_master_arlock,
mem_master_arvalid,
mem_master_awlock,
mem_master_awvalid,
mem_master_bready,
mem_master_rready,
mem_master_wlast,
mem_master_wvalid;
// register cfg_verbosity
reg [3 : 0] cfg_verbosity;
wire [3 : 0] cfg_verbosity$D_IN;
wire cfg_verbosity$EN;
// register rg_state
reg [1 : 0] rg_state;
reg [1 : 0] rg_state$D_IN;
wire rg_state$EN;
// ports of submodule dcache
wire [63 : 0] dcache$cword,
dcache$mem_master_araddr,
dcache$mem_master_awaddr,
dcache$mem_master_rdata,
dcache$mem_master_wdata,
dcache$mv_tohost_value,
dcache$req_addr,
dcache$req_satp,
dcache$req_st_value,
dcache$set_watch_tohost_tohost_addr,
dcache$st_amo_val;
wire [7 : 0] dcache$mem_master_arlen,
dcache$mem_master_awlen,
dcache$mem_master_wstrb,
dcache$mv_status;
wire [6 : 0] dcache$req_amo_funct7;
wire [3 : 0] dcache$exc_code,
dcache$mem_master_arcache,
dcache$mem_master_arid,
dcache$mem_master_arqos,
dcache$mem_master_arregion,
dcache$mem_master_awcache,
dcache$mem_master_awid,
dcache$mem_master_awqos,
dcache$mem_master_awregion,
dcache$mem_master_bid,
dcache$mem_master_rid,
dcache$set_verbosity_verbosity;
wire [2 : 0] dcache$mem_master_arprot,
dcache$mem_master_arsize,
dcache$mem_master_awprot,
dcache$mem_master_awsize,
dcache$req_f3;
wire [1 : 0] dcache$mem_master_arburst,
dcache$mem_master_awburst,
dcache$mem_master_bresp,
dcache$mem_master_rresp,
dcache$req_op,
dcache$req_priv;
wire dcache$EN_ma_ddr4_ready,
dcache$EN_req,
dcache$EN_server_flush_request_put,
dcache$EN_server_flush_response_get,
dcache$EN_server_reset_request_put,
dcache$EN_server_reset_response_get,
dcache$EN_set_verbosity,
dcache$EN_set_watch_tohost,
dcache$EN_tlb_flush,
dcache$RDY_server_flush_request_put,
dcache$RDY_server_flush_response_get,
dcache$RDY_server_reset_request_put,
dcache$RDY_server_reset_response_get,
dcache$exc,
dcache$mem_master_arlock,
dcache$mem_master_arready,
dcache$mem_master_arvalid,
dcache$mem_master_awlock,
dcache$mem_master_awready,
dcache$mem_master_awvalid,
dcache$mem_master_bready,
dcache$mem_master_bvalid,
dcache$mem_master_rlast,
dcache$mem_master_rready,
dcache$mem_master_rvalid,
dcache$mem_master_wlast,
dcache$mem_master_wready,
dcache$mem_master_wvalid,
dcache$req_mstatus_MXR,
dcache$req_sstatus_SUM,
dcache$set_watch_tohost_watch_tohost,
dcache$valid;
// ports of submodule f_reset_rsps
wire f_reset_rsps$CLR,
f_reset_rsps$DEQ,
f_reset_rsps$EMPTY_N,
f_reset_rsps$ENQ,
f_reset_rsps$FULL_N;
// ports of submodule f_sfence_vma_reqs
wire f_sfence_vma_reqs$CLR,
f_sfence_vma_reqs$DEQ,
f_sfence_vma_reqs$EMPTY_N,
f_sfence_vma_reqs$ENQ,
f_sfence_vma_reqs$FULL_N;
// ports of submodule f_sfence_vma_rsps
wire f_sfence_vma_rsps$CLR,
f_sfence_vma_rsps$DEQ,
f_sfence_vma_rsps$EMPTY_N,
f_sfence_vma_rsps$ENQ,
f_sfence_vma_rsps$FULL_N;
// ports of submodule icache
wire [63 : 0] icache$addr,
icache$cword,
icache$mem_master_araddr,
icache$mem_master_awaddr,
icache$mem_master_rdata,
icache$mem_master_wdata,
icache$req_addr,
icache$req_satp,
icache$req_st_value,
icache$set_watch_tohost_tohost_addr;
wire [7 : 0] icache$mem_master_arlen,
icache$mem_master_awlen,
icache$mem_master_wstrb;
wire [6 : 0] icache$req_amo_funct7;
wire [3 : 0] icache$exc_code,
icache$mem_master_arcache,
icache$mem_master_arid,
icache$mem_master_arqos,
icache$mem_master_arregion,
icache$mem_master_awcache,
icache$mem_master_awid,
icache$mem_master_awqos,
icache$mem_master_awregion,
icache$mem_master_bid,
icache$mem_master_rid,
icache$set_verbosity_verbosity;
wire [2 : 0] icache$mem_master_arprot,
icache$mem_master_arsize,
icache$mem_master_awprot,
icache$mem_master_awsize,
icache$req_f3;
wire [1 : 0] icache$mem_master_arburst,
icache$mem_master_awburst,
icache$mem_master_bresp,
icache$mem_master_rresp,
icache$req_op,
icache$req_priv;
wire icache$EN_ma_ddr4_ready,
icache$EN_req,
icache$EN_server_flush_request_put,
icache$EN_server_flush_response_get,
icache$EN_server_reset_request_put,
icache$EN_server_reset_response_get,
icache$EN_set_verbosity,
icache$EN_set_watch_tohost,
icache$EN_tlb_flush,
icache$RDY_server_flush_request_put,
icache$RDY_server_flush_response_get,
icache$RDY_server_reset_request_put,
icache$RDY_server_reset_response_get,
icache$exc,
icache$mem_master_arlock,
icache$mem_master_arready,
icache$mem_master_arvalid,
icache$mem_master_awlock,
icache$mem_master_awready,
icache$mem_master_awvalid,
icache$mem_master_bready,
icache$mem_master_bvalid,
icache$mem_master_rlast,
icache$mem_master_rready,
icache$mem_master_rvalid,
icache$mem_master_wlast,
icache$mem_master_wready,
icache$mem_master_wvalid,
icache$req_mstatus_MXR,
icache$req_sstatus_SUM,
icache$set_watch_tohost_watch_tohost,
icache$valid;
// ports of submodule soc_map
wire [63 : 0] soc_map$m_is_IO_addr_addr,
soc_map$m_is_mem_addr_addr,
soc_map$m_is_near_mem_IO_addr_addr;
// rule scheduling signals
wire CAN_FIRE_RL_rl_reset,
CAN_FIRE_RL_rl_reset_complete,
CAN_FIRE_RL_rl_sfence_vma,
CAN_FIRE_dma_server_m_arvalid,
CAN_FIRE_dma_server_m_awvalid,
CAN_FIRE_dma_server_m_bready,
CAN_FIRE_dma_server_m_rready,
CAN_FIRE_dma_server_m_wvalid,
CAN_FIRE_dmem_req,
CAN_FIRE_imem_master_m_arready,
CAN_FIRE_imem_master_m_awready,
CAN_FIRE_imem_master_m_bvalid,
CAN_FIRE_imem_master_m_rvalid,
CAN_FIRE_imem_master_m_wready,
CAN_FIRE_imem_req,
CAN_FIRE_ma_ddr4_ready,
CAN_FIRE_mem_master_m_arready,
CAN_FIRE_mem_master_m_awready,
CAN_FIRE_mem_master_m_bvalid,
CAN_FIRE_mem_master_m_rvalid,
CAN_FIRE_mem_master_m_wready,
CAN_FIRE_server_fence_i_request_put,
CAN_FIRE_server_fence_i_response_get,
CAN_FIRE_server_fence_request_put,
CAN_FIRE_server_fence_response_get,
CAN_FIRE_server_reset_request_put,
CAN_FIRE_server_reset_response_get,
CAN_FIRE_set_watch_tohost,
CAN_FIRE_sfence_vma_server_request_put,
CAN_FIRE_sfence_vma_server_response_get,
WILL_FIRE_RL_rl_reset,
WILL_FIRE_RL_rl_reset_complete,
WILL_FIRE_RL_rl_sfence_vma,
WILL_FIRE_dma_server_m_arvalid,
WILL_FIRE_dma_server_m_awvalid,
WILL_FIRE_dma_server_m_bready,
WILL_FIRE_dma_server_m_rready,
WILL_FIRE_dma_server_m_wvalid,
WILL_FIRE_dmem_req,
WILL_FIRE_imem_master_m_arready,
WILL_FIRE_imem_master_m_awready,
WILL_FIRE_imem_master_m_bvalid,
WILL_FIRE_imem_master_m_rvalid,
WILL_FIRE_imem_master_m_wready,
WILL_FIRE_imem_req,
WILL_FIRE_ma_ddr4_ready,
WILL_FIRE_mem_master_m_arready,
WILL_FIRE_mem_master_m_awready,
WILL_FIRE_mem_master_m_bvalid,
WILL_FIRE_mem_master_m_rvalid,
WILL_FIRE_mem_master_m_wready,
WILL_FIRE_server_fence_i_request_put,
WILL_FIRE_server_fence_i_response_get,
WILL_FIRE_server_fence_request_put,
WILL_FIRE_server_fence_response_get,
WILL_FIRE_server_reset_request_put,
WILL_FIRE_server_reset_response_get,
WILL_FIRE_set_watch_tohost,
WILL_FIRE_sfence_vma_server_request_put,
WILL_FIRE_sfence_vma_server_response_get;
// inputs to muxes for submodule ports
wire MUX_rg_state$write_1__SEL_2, MUX_rg_state$write_1__SEL_3;
// declarations used by system tasks
// synopsys translate_off
reg [31 : 0] v__h1730;
reg [31 : 0] v__h1884;
reg [31 : 0] v__h1724;
reg [31 : 0] v__h1878;
// synopsys translate_on
// remaining internal signals
wire NOT_cfg_verbosity_read_ULE_1___d9;
// action method server_reset_request_put
assign RDY_server_reset_request_put = rg_state == 2'd2 ;
assign CAN_FIRE_server_reset_request_put = rg_state == 2'd2 ;
assign WILL_FIRE_server_reset_request_put = EN_server_reset_request_put ;
// action method server_reset_response_get
assign RDY_server_reset_response_get = f_reset_rsps$EMPTY_N ;
assign CAN_FIRE_server_reset_response_get = f_reset_rsps$EMPTY_N ;
assign WILL_FIRE_server_reset_response_get = EN_server_reset_response_get ;
// action method imem_req
assign CAN_FIRE_imem_req = 1'd1 ;
assign WILL_FIRE_imem_req = EN_imem_req ;
// value method imem_valid
assign imem_valid = icache$valid ;
// value method imem_is_i32_not_i16
assign imem_is_i32_not_i16 = 1'd1 ;
// value method imem_pc
assign imem_pc = icache$addr ;
// value method imem_instr
assign imem_instr = icache$cword[31:0] ;
// value method imem_exc
assign imem_exc = icache$exc ;
// value method imem_exc_code
assign imem_exc_code = icache$exc_code ;
// value method imem_tval
assign imem_tval = icache$addr ;
// value method imem_master_m_awvalid
assign imem_master_awvalid = icache$mem_master_awvalid ;
// value method imem_master_m_awid
assign imem_master_awid = icache$mem_master_awid ;
// value method imem_master_m_awaddr
assign imem_master_awaddr = icache$mem_master_awaddr ;
// value method imem_master_m_awlen
assign imem_master_awlen = icache$mem_master_awlen ;
// value method imem_master_m_awsize
assign imem_master_awsize = icache$mem_master_awsize ;
// value method imem_master_m_awburst
assign imem_master_awburst = icache$mem_master_awburst ;
// value method imem_master_m_awlock
assign imem_master_awlock = icache$mem_master_awlock ;
// value method imem_master_m_awcache
assign imem_master_awcache = icache$mem_master_awcache ;
// value method imem_master_m_awprot
assign imem_master_awprot = icache$mem_master_awprot ;
// value method imem_master_m_awqos
assign imem_master_awqos = icache$mem_master_awqos ;
// value method imem_master_m_awregion
assign imem_master_awregion = icache$mem_master_awregion ;
// action method imem_master_m_awready
assign CAN_FIRE_imem_master_m_awready = 1'd1 ;
assign WILL_FIRE_imem_master_m_awready = 1'd1 ;
// value method imem_master_m_wvalid
assign imem_master_wvalid = icache$mem_master_wvalid ;
// value method imem_master_m_wdata
assign imem_master_wdata = icache$mem_master_wdata ;
// value method imem_master_m_wstrb
assign imem_master_wstrb = icache$mem_master_wstrb ;
// value method imem_master_m_wlast
assign imem_master_wlast = icache$mem_master_wlast ;
// action method imem_master_m_wready
assign CAN_FIRE_imem_master_m_wready = 1'd1 ;
assign WILL_FIRE_imem_master_m_wready = 1'd1 ;
// action method imem_master_m_bvalid
assign CAN_FIRE_imem_master_m_bvalid = 1'd1 ;
assign WILL_FIRE_imem_master_m_bvalid = 1'd1 ;
// value method imem_master_m_bready
assign imem_master_bready = icache$mem_master_bready ;
// value method imem_master_m_arvalid
assign imem_master_arvalid = icache$mem_master_arvalid ;
// value method imem_master_m_arid
assign imem_master_arid = icache$mem_master_arid ;
// value method imem_master_m_araddr
assign imem_master_araddr = icache$mem_master_araddr ;
// value method imem_master_m_arlen
assign imem_master_arlen = icache$mem_master_arlen ;
// value method imem_master_m_arsize
assign imem_master_arsize = icache$mem_master_arsize ;
// value method imem_master_m_arburst
assign imem_master_arburst = icache$mem_master_arburst ;
// value method imem_master_m_arlock
assign imem_master_arlock = icache$mem_master_arlock ;
// value method imem_master_m_arcache
assign imem_master_arcache = icache$mem_master_arcache ;
// value method imem_master_m_arprot
assign imem_master_arprot = icache$mem_master_arprot ;
// value method imem_master_m_arqos
assign imem_master_arqos = icache$mem_master_arqos ;
// value method imem_master_m_arregion
assign imem_master_arregion = icache$mem_master_arregion ;
// action method imem_master_m_arready
assign CAN_FIRE_imem_master_m_arready = 1'd1 ;
assign WILL_FIRE_imem_master_m_arready = 1'd1 ;
// action method imem_master_m_rvalid
assign CAN_FIRE_imem_master_m_rvalid = 1'd1 ;
assign WILL_FIRE_imem_master_m_rvalid = 1'd1 ;
// value method imem_master_m_rready
assign imem_master_rready = icache$mem_master_rready ;
// action method dmem_req
assign CAN_FIRE_dmem_req = 1'd1 ;
assign WILL_FIRE_dmem_req = EN_dmem_req ;
// value method dmem_valid
assign dmem_valid = dcache$valid ;
// value method dmem_word64
assign dmem_word64 = dcache$cword ;
// value method dmem_st_amo_val
assign dmem_st_amo_val = dcache$st_amo_val ;
// value method dmem_exc
assign dmem_exc = dcache$exc ;
// value method dmem_exc_code
assign dmem_exc_code = dcache$exc_code ;
// value method mem_master_m_awvalid
assign mem_master_awvalid = dcache$mem_master_awvalid ;
// value method mem_master_m_awid
assign mem_master_awid = dcache$mem_master_awid ;
// value method mem_master_m_awaddr
assign mem_master_awaddr = dcache$mem_master_awaddr ;
// value method mem_master_m_awlen
assign mem_master_awlen = dcache$mem_master_awlen ;
// value method mem_master_m_awsize
assign mem_master_awsize = dcache$mem_master_awsize ;
// value method mem_master_m_awburst
assign mem_master_awburst = dcache$mem_master_awburst ;
// value method mem_master_m_awlock
assign mem_master_awlock = dcache$mem_master_awlock ;
// value method mem_master_m_awcache
assign mem_master_awcache = dcache$mem_master_awcache ;
// value method mem_master_m_awprot
assign mem_master_awprot = dcache$mem_master_awprot ;
// value method mem_master_m_awqos
assign mem_master_awqos = dcache$mem_master_awqos ;
// value method mem_master_m_awregion
assign mem_master_awregion = dcache$mem_master_awregion ;
// action method mem_master_m_awready
assign CAN_FIRE_mem_master_m_awready = 1'd1 ;
assign WILL_FIRE_mem_master_m_awready = 1'd1 ;
// value method mem_master_m_wvalid
assign mem_master_wvalid = dcache$mem_master_wvalid ;
// value method mem_master_m_wdata
assign mem_master_wdata = dcache$mem_master_wdata ;
// value method mem_master_m_wstrb
assign mem_master_wstrb = dcache$mem_master_wstrb ;
// value method mem_master_m_wlast
assign mem_master_wlast = dcache$mem_master_wlast ;
// action method mem_master_m_wready
assign CAN_FIRE_mem_master_m_wready = 1'd1 ;
assign WILL_FIRE_mem_master_m_wready = 1'd1 ;
// action method mem_master_m_bvalid
assign CAN_FIRE_mem_master_m_bvalid = 1'd1 ;
assign WILL_FIRE_mem_master_m_bvalid = 1'd1 ;
// value method mem_master_m_bready
assign mem_master_bready = dcache$mem_master_bready ;
// value method mem_master_m_arvalid
assign mem_master_arvalid = dcache$mem_master_arvalid ;
// value method mem_master_m_arid
assign mem_master_arid = dcache$mem_master_arid ;
// value method mem_master_m_araddr
assign mem_master_araddr = dcache$mem_master_araddr ;
// value method mem_master_m_arlen
assign mem_master_arlen = dcache$mem_master_arlen ;
// value method mem_master_m_arsize
assign mem_master_arsize = dcache$mem_master_arsize ;
// value method mem_master_m_arburst
assign mem_master_arburst = dcache$mem_master_arburst ;
// value method mem_master_m_arlock
assign mem_master_arlock = dcache$mem_master_arlock ;
// value method mem_master_m_arcache
assign mem_master_arcache = dcache$mem_master_arcache ;
// value method mem_master_m_arprot
assign mem_master_arprot = dcache$mem_master_arprot ;
// value method mem_master_m_arqos
assign mem_master_arqos = dcache$mem_master_arqos ;
// value method mem_master_m_arregion
assign mem_master_arregion = dcache$mem_master_arregion ;
// action method mem_master_m_arready
assign CAN_FIRE_mem_master_m_arready = 1'd1 ;
assign WILL_FIRE_mem_master_m_arready = 1'd1 ;
// action method mem_master_m_rvalid
assign CAN_FIRE_mem_master_m_rvalid = 1'd1 ;
assign WILL_FIRE_mem_master_m_rvalid = 1'd1 ;
// value method mem_master_m_rready
assign mem_master_rready = dcache$mem_master_rready ;
// action method server_fence_i_request_put
assign RDY_server_fence_i_request_put =
dcache$RDY_server_flush_request_put &&
icache$RDY_server_flush_request_put ;
assign CAN_FIRE_server_fence_i_request_put =
dcache$RDY_server_flush_request_put &&
icache$RDY_server_flush_request_put ;
assign WILL_FIRE_server_fence_i_request_put =
EN_server_fence_i_request_put ;
// action method server_fence_i_response_get
assign RDY_server_fence_i_response_get =
dcache$RDY_server_flush_response_get &&
icache$RDY_server_flush_response_get ;
assign CAN_FIRE_server_fence_i_response_get =
dcache$RDY_server_flush_response_get &&
icache$RDY_server_flush_response_get ;
assign WILL_FIRE_server_fence_i_response_get =
EN_server_fence_i_response_get ;
// action method server_fence_request_put
assign RDY_server_fence_request_put = dcache$RDY_server_flush_request_put ;
assign CAN_FIRE_server_fence_request_put =
dcache$RDY_server_flush_request_put ;
assign WILL_FIRE_server_fence_request_put = EN_server_fence_request_put ;
// action method server_fence_response_get
assign RDY_server_fence_response_get =
dcache$RDY_server_flush_response_get ;
assign CAN_FIRE_server_fence_response_get =
dcache$RDY_server_flush_response_get ;
assign WILL_FIRE_server_fence_response_get = EN_server_fence_response_get ;
// action method sfence_vma_server_request_put
assign RDY_sfence_vma_server_request_put = f_sfence_vma_reqs$FULL_N ;
assign CAN_FIRE_sfence_vma_server_request_put = f_sfence_vma_reqs$FULL_N ;
assign WILL_FIRE_sfence_vma_server_request_put =
EN_sfence_vma_server_request_put ;
// action method sfence_vma_server_response_get
assign RDY_sfence_vma_server_response_get = f_sfence_vma_rsps$EMPTY_N ;
assign CAN_FIRE_sfence_vma_server_response_get = f_sfence_vma_rsps$EMPTY_N ;
assign WILL_FIRE_sfence_vma_server_response_get =
EN_sfence_vma_server_response_get ;
// action method dma_server_m_awvalid
assign CAN_FIRE_dma_server_m_awvalid = 1'd1 ;
assign WILL_FIRE_dma_server_m_awvalid = 1'd1 ;
// value method dma_server_m_awready
assign dma_server_awready = 1'd0 ;
// action method dma_server_m_wvalid
assign CAN_FIRE_dma_server_m_wvalid = 1'd1 ;
assign WILL_FIRE_dma_server_m_wvalid = 1'd1 ;
// value method dma_server_m_wready
assign dma_server_wready = 1'd0 ;
// value method dma_server_m_bvalid
assign dma_server_bvalid = 1'd0 ;
// value method dma_server_m_bid
assign dma_server_bid = 16'hAAAA ;
// value method dma_server_m_bresp
assign dma_server_bresp = 2'd0 ;
// action method dma_server_m_bready
assign CAN_FIRE_dma_server_m_bready = 1'd1 ;
assign WILL_FIRE_dma_server_m_bready = 1'd1 ;
// action method dma_server_m_arvalid
assign CAN_FIRE_dma_server_m_arvalid = 1'd1 ;
assign WILL_FIRE_dma_server_m_arvalid = 1'd1 ;
// value method dma_server_m_arready
assign dma_server_arready = 1'd0 ;
// value method dma_server_m_rvalid
assign dma_server_rvalid = 1'd0 ;
// value method dma_server_m_rid
assign dma_server_rid = 16'd0 ;
// value method dma_server_m_rdata
assign dma_server_rdata = 512'd0 ;
// value method dma_server_m_rresp
assign dma_server_rresp = 2'd0 ;
// value method dma_server_m_rlast
assign dma_server_rlast = 1'd1 ;
// action method dma_server_m_rready
assign CAN_FIRE_dma_server_m_rready = 1'd1 ;
assign WILL_FIRE_dma_server_m_rready = 1'd1 ;
// action method set_watch_tohost
assign RDY_set_watch_tohost = 1'd1 ;
assign CAN_FIRE_set_watch_tohost = 1'd1 ;
assign WILL_FIRE_set_watch_tohost = EN_set_watch_tohost ;
// value method mv_tohost_value
assign mv_tohost_value = dcache$mv_tohost_value ;
assign RDY_mv_tohost_value = 1'd1 ;
// action method ma_ddr4_ready
assign RDY_ma_ddr4_ready = 1'd1 ;
assign CAN_FIRE_ma_ddr4_ready = 1'd1 ;
assign WILL_FIRE_ma_ddr4_ready = EN_ma_ddr4_ready ;
// value method mv_status
assign mv_status = dcache$mv_status ;
// submodule dcache
mkMMU_Cache #(.dmem_not_imem(1'd1)) dcache(.CLK(CLK),
.RST_N(RST_N),
.mem_master_arready(dcache$mem_master_arready),
.mem_master_awready(dcache$mem_master_awready),
.mem_master_bid(dcache$mem_master_bid),
.mem_master_bresp(dcache$mem_master_bresp),
.mem_master_bvalid(dcache$mem_master_bvalid),
.mem_master_rdata(dcache$mem_master_rdata),
.mem_master_rid(dcache$mem_master_rid),
.mem_master_rlast(dcache$mem_master_rlast),
.mem_master_rresp(dcache$mem_master_rresp),
.mem_master_rvalid(dcache$mem_master_rvalid),
.mem_master_wready(dcache$mem_master_wready),
.req_addr(dcache$req_addr),
.req_amo_funct7(dcache$req_amo_funct7),
.req_f3(dcache$req_f3),
.req_mstatus_MXR(dcache$req_mstatus_MXR),
.req_op(dcache$req_op),
.req_priv(dcache$req_priv),
.req_satp(dcache$req_satp),
.req_sstatus_SUM(dcache$req_sstatus_SUM),
.req_st_value(dcache$req_st_value),
.set_verbosity_verbosity(dcache$set_verbosity_verbosity),
.set_watch_tohost_tohost_addr(dcache$set_watch_tohost_tohost_addr),
.set_watch_tohost_watch_tohost(dcache$set_watch_tohost_watch_tohost),
.EN_set_verbosity(dcache$EN_set_verbosity),
.EN_server_reset_request_put(dcache$EN_server_reset_request_put),
.EN_server_reset_response_get(dcache$EN_server_reset_response_get),
.EN_req(dcache$EN_req),
.EN_server_flush_request_put(dcache$EN_server_flush_request_put),
.EN_server_flush_response_get(dcache$EN_server_flush_response_get),
.EN_tlb_flush(dcache$EN_tlb_flush),
.EN_set_watch_tohost(dcache$EN_set_watch_tohost),
.EN_ma_ddr4_ready(dcache$EN_ma_ddr4_ready),
.RDY_set_verbosity(),
.RDY_server_reset_request_put(dcache$RDY_server_reset_request_put),
.RDY_server_reset_response_get(dcache$RDY_server_reset_response_get),
.valid(dcache$valid),
.addr(),
.cword(dcache$cword),
.st_amo_val(dcache$st_amo_val),
.exc(dcache$exc),
.exc_code(dcache$exc_code),
.RDY_server_flush_request_put(dcache$RDY_server_flush_request_put),
.RDY_server_flush_response_get(dcache$RDY_server_flush_response_get),
.RDY_tlb_flush(),
.mem_master_awvalid(dcache$mem_master_awvalid),
.mem_master_awid(dcache$mem_master_awid),
.mem_master_awaddr(dcache$mem_master_awaddr),
.mem_master_awlen(dcache$mem_master_awlen),
.mem_master_awsize(dcache$mem_master_awsize),
.mem_master_awburst(dcache$mem_master_awburst),
.mem_master_awlock(dcache$mem_master_awlock),
.mem_master_awcache(dcache$mem_master_awcache),
.mem_master_awprot(dcache$mem_master_awprot),
.mem_master_awqos(dcache$mem_master_awqos),
.mem_master_awregion(dcache$mem_master_awregion),
.mem_master_wvalid(dcache$mem_master_wvalid),
.mem_master_wdata(dcache$mem_master_wdata),
.mem_master_wstrb(dcache$mem_master_wstrb),
.mem_master_wlast(dcache$mem_master_wlast),
.mem_master_bready(dcache$mem_master_bready),
.mem_master_arvalid(dcache$mem_master_arvalid),
.mem_master_arid(dcache$mem_master_arid),
.mem_master_araddr(dcache$mem_master_araddr),
.mem_master_arlen(dcache$mem_master_arlen),
.mem_master_arsize(dcache$mem_master_arsize),
.mem_master_arburst(dcache$mem_master_arburst),
.mem_master_arlock(dcache$mem_master_arlock),
.mem_master_arcache(dcache$mem_master_arcache),
.mem_master_arprot(dcache$mem_master_arprot),
.mem_master_arqos(dcache$mem_master_arqos),
.mem_master_arregion(dcache$mem_master_arregion),
.mem_master_rready(dcache$mem_master_rready),
.RDY_set_watch_tohost(),
.mv_tohost_value(dcache$mv_tohost_value),
.RDY_mv_tohost_value(),
.RDY_ma_ddr4_ready(),
.mv_status(dcache$mv_status));
// submodule f_reset_rsps
FIFO20 #(.guarded(1'd1)) f_reset_rsps(.RST(RST_N),
.CLK(CLK),
.ENQ(f_reset_rsps$ENQ),
.DEQ(f_reset_rsps$DEQ),
.CLR(f_reset_rsps$CLR),
.FULL_N(f_reset_rsps$FULL_N),
.EMPTY_N(f_reset_rsps$EMPTY_N));
// submodule f_sfence_vma_reqs
FIFO20 #(.guarded(1'd1)) f_sfence_vma_reqs(.RST(RST_N),
.CLK(CLK),
.ENQ(f_sfence_vma_reqs$ENQ),
.DEQ(f_sfence_vma_reqs$DEQ),
.CLR(f_sfence_vma_reqs$CLR),
.FULL_N(f_sfence_vma_reqs$FULL_N),
.EMPTY_N(f_sfence_vma_reqs$EMPTY_N));
// submodule f_sfence_vma_rsps
FIFO20 #(.guarded(1'd1)) f_sfence_vma_rsps(.RST(RST_N),
.CLK(CLK),
.ENQ(f_sfence_vma_rsps$ENQ),
.DEQ(f_sfence_vma_rsps$DEQ),
.CLR(f_sfence_vma_rsps$CLR),
.FULL_N(f_sfence_vma_rsps$FULL_N),
.EMPTY_N(f_sfence_vma_rsps$EMPTY_N));
// submodule icache
mkMMU_Cache #(.dmem_not_imem(1'd0)) icache(.CLK(CLK),
.RST_N(RST_N),
.mem_master_arready(icache$mem_master_arready),
.mem_master_awready(icache$mem_master_awready),
.mem_master_bid(icache$mem_master_bid),
.mem_master_bresp(icache$mem_master_bresp),
.mem_master_bvalid(icache$mem_master_bvalid),
.mem_master_rdata(icache$mem_master_rdata),
.mem_master_rid(icache$mem_master_rid),
.mem_master_rlast(icache$mem_master_rlast),
.mem_master_rresp(icache$mem_master_rresp),
.mem_master_rvalid(icache$mem_master_rvalid),
.mem_master_wready(icache$mem_master_wready),
.req_addr(icache$req_addr),
.req_amo_funct7(icache$req_amo_funct7),
.req_f3(icache$req_f3),
.req_mstatus_MXR(icache$req_mstatus_MXR),
.req_op(icache$req_op),
.req_priv(icache$req_priv),
.req_satp(icache$req_satp),
.req_sstatus_SUM(icache$req_sstatus_SUM),
.req_st_value(icache$req_st_value),
.set_verbosity_verbosity(icache$set_verbosity_verbosity),
.set_watch_tohost_tohost_addr(icache$set_watch_tohost_tohost_addr),
.set_watch_tohost_watch_tohost(icache$set_watch_tohost_watch_tohost),
.EN_set_verbosity(icache$EN_set_verbosity),
.EN_server_reset_request_put(icache$EN_server_reset_request_put),
.EN_server_reset_response_get(icache$EN_server_reset_response_get),
.EN_req(icache$EN_req),
.EN_server_flush_request_put(icache$EN_server_flush_request_put),
.EN_server_flush_response_get(icache$EN_server_flush_response_get),
.EN_tlb_flush(icache$EN_tlb_flush),
.EN_set_watch_tohost(icache$EN_set_watch_tohost),
.EN_ma_ddr4_ready(icache$EN_ma_ddr4_ready),
.RDY_set_verbosity(),
.RDY_server_reset_request_put(icache$RDY_server_reset_request_put),
.RDY_server_reset_response_get(icache$RDY_server_reset_response_get),
.valid(icache$valid),
.addr(icache$addr),
.cword(icache$cword),
.st_amo_val(),
.exc(icache$exc),
.exc_code(icache$exc_code),
.RDY_server_flush_request_put(icache$RDY_server_flush_request_put),
.RDY_server_flush_response_get(icache$RDY_server_flush_response_get),
.RDY_tlb_flush(),
.mem_master_awvalid(icache$mem_master_awvalid),
.mem_master_awid(icache$mem_master_awid),
.mem_master_awaddr(icache$mem_master_awaddr),
.mem_master_awlen(icache$mem_master_awlen),
.mem_master_awsize(icache$mem_master_awsize),
.mem_master_awburst(icache$mem_master_awburst),
.mem_master_awlock(icache$mem_master_awlock),
.mem_master_awcache(icache$mem_master_awcache),
.mem_master_awprot(icache$mem_master_awprot),
.mem_master_awqos(icache$mem_master_awqos),
.mem_master_awregion(icache$mem_master_awregion),
.mem_master_wvalid(icache$mem_master_wvalid),
.mem_master_wdata(icache$mem_master_wdata),
.mem_master_wstrb(icache$mem_master_wstrb),
.mem_master_wlast(icache$mem_master_wlast),
.mem_master_bready(icache$mem_master_bready),
.mem_master_arvalid(icache$mem_master_arvalid),
.mem_master_arid(icache$mem_master_arid),
.mem_master_araddr(icache$mem_master_araddr),
.mem_master_arlen(icache$mem_master_arlen),
.mem_master_arsize(icache$mem_master_arsize),
.mem_master_arburst(icache$mem_master_arburst),
.mem_master_arlock(icache$mem_master_arlock),
.mem_master_arcache(icache$mem_master_arcache),
.mem_master_arprot(icache$mem_master_arprot),
.mem_master_arqos(icache$mem_master_arqos),
.mem_master_arregion(icache$mem_master_arregion),
.mem_master_rready(icache$mem_master_rready),
.RDY_set_watch_tohost(),
.mv_tohost_value(),
.RDY_mv_tohost_value(),
.RDY_ma_ddr4_ready(),
.mv_status());
// submodule soc_map
mkSoC_Map soc_map(.CLK(CLK),
.RST_N(RST_N),
.m_is_IO_addr_addr(soc_map$m_is_IO_addr_addr),
.m_is_mem_addr_addr(soc_map$m_is_mem_addr_addr),
.m_is_near_mem_IO_addr_addr(soc_map$m_is_near_mem_IO_addr_addr),
.m_near_mem_io_addr_base(),
.m_near_mem_io_addr_size(),
.m_near_mem_io_addr_lim(),
.m_plic_addr_base(),
.m_plic_addr_size(),
.m_plic_addr_lim(),
.m_uart0_addr_base(),
.m_uart0_addr_size(),
.m_uart0_addr_lim(),
.m_boot_rom_addr_base(),
.m_boot_rom_addr_size(),
.m_boot_rom_addr_lim(),
.m_mem0_controller_addr_base(),
.m_mem0_controller_addr_size(),
.m_mem0_controller_addr_lim(),
.m_tcm_addr_base(),
.m_tcm_addr_size(),
.m_tcm_addr_lim(),
.m_is_mem_addr(),
.m_is_IO_addr(),
.m_is_near_mem_IO_addr(),
.m_pc_reset_value(),
.m_mtvec_reset_value(),
.m_nmivec_reset_value());
// rule RL_rl_reset
assign CAN_FIRE_RL_rl_reset =
dcache$RDY_server_reset_request_put &&
icache$RDY_server_reset_request_put &&
rg_state == 2'd0 ;
assign WILL_FIRE_RL_rl_reset = MUX_rg_state$write_1__SEL_2 ;
// rule RL_rl_reset_complete
assign CAN_FIRE_RL_rl_reset_complete = MUX_rg_state$write_1__SEL_3 ;
assign WILL_FIRE_RL_rl_reset_complete = MUX_rg_state$write_1__SEL_3 ;
// rule RL_rl_sfence_vma
assign CAN_FIRE_RL_rl_sfence_vma =
f_sfence_vma_reqs$EMPTY_N && f_sfence_vma_rsps$FULL_N ;
assign WILL_FIRE_RL_rl_sfence_vma = CAN_FIRE_RL_rl_sfence_vma ;
// inputs to muxes for submodule ports
assign MUX_rg_state$write_1__SEL_2 =
CAN_FIRE_RL_rl_reset && !EN_server_fence_request_put &&
!EN_server_fence_i_request_put ;
assign MUX_rg_state$write_1__SEL_3 =
dcache$RDY_server_reset_response_get &&
icache$RDY_server_reset_response_get &&
f_reset_rsps$FULL_N &&
rg_state == 2'd1 ;
// register cfg_verbosity
assign cfg_verbosity$D_IN = 4'h0 ;
assign cfg_verbosity$EN = 1'b0 ;
// register rg_state
always@(EN_server_reset_request_put or
WILL_FIRE_RL_rl_reset or WILL_FIRE_RL_rl_reset_complete)
begin
case (1'b1) // synopsys parallel_case
EN_server_reset_request_put: rg_state$D_IN = 2'd0;
WILL_FIRE_RL_rl_reset: rg_state$D_IN = 2'd1;
WILL_FIRE_RL_rl_reset_complete: rg_state$D_IN = 2'd2;
default: rg_state$D_IN = 2'b10 /* unspecified value */ ;
endcase
end
assign rg_state$EN =
EN_server_reset_request_put || WILL_FIRE_RL_rl_reset ||
WILL_FIRE_RL_rl_reset_complete ;
// submodule dcache
assign dcache$mem_master_arready = mem_master_arready ;
assign dcache$mem_master_awready = mem_master_awready ;
assign dcache$mem_master_bid = mem_master_bid ;
assign dcache$mem_master_bresp = mem_master_bresp ;
assign dcache$mem_master_bvalid = mem_master_bvalid ;
assign dcache$mem_master_rdata = mem_master_rdata ;
assign dcache$mem_master_rid = mem_master_rid ;
assign dcache$mem_master_rlast = mem_master_rlast ;
assign dcache$mem_master_rresp = mem_master_rresp ;
assign dcache$mem_master_rvalid = mem_master_rvalid ;
assign dcache$mem_master_wready = mem_master_wready ;
assign dcache$req_addr = dmem_req_addr ;
assign dcache$req_amo_funct7 = dmem_req_amo_funct7 ;
assign dcache$req_f3 = dmem_req_f3 ;
assign dcache$req_mstatus_MXR = dmem_req_mstatus_MXR ;
assign dcache$req_op = dmem_req_op ;
assign dcache$req_priv = dmem_req_priv ;
assign dcache$req_satp = dmem_req_satp ;
assign dcache$req_sstatus_SUM = dmem_req_sstatus_SUM ;
assign dcache$req_st_value = dmem_req_store_value ;
assign dcache$set_verbosity_verbosity = 4'h0 ;
assign dcache$set_watch_tohost_tohost_addr = set_watch_tohost_tohost_addr ;
assign dcache$set_watch_tohost_watch_tohost =
set_watch_tohost_watch_tohost ;
assign dcache$EN_set_verbosity = 1'b0 ;
assign dcache$EN_server_reset_request_put = MUX_rg_state$write_1__SEL_2 ;
assign dcache$EN_server_reset_response_get = MUX_rg_state$write_1__SEL_3 ;
assign dcache$EN_req = EN_dmem_req ;
assign dcache$EN_server_flush_request_put =
EN_server_fence_i_request_put || EN_server_fence_request_put ;
assign dcache$EN_server_flush_response_get =
EN_server_fence_i_response_get || EN_server_fence_response_get ;
assign dcache$EN_tlb_flush = CAN_FIRE_RL_rl_sfence_vma ;
assign dcache$EN_set_watch_tohost = EN_set_watch_tohost ;
assign dcache$EN_ma_ddr4_ready = EN_ma_ddr4_ready ;
// submodule f_reset_rsps
assign f_reset_rsps$ENQ = MUX_rg_state$write_1__SEL_3 ;
assign f_reset_rsps$DEQ = EN_server_reset_response_get ;
assign f_reset_rsps$CLR = 1'b0 ;
// submodule f_sfence_vma_reqs
assign f_sfence_vma_reqs$ENQ = EN_sfence_vma_server_request_put ;
assign f_sfence_vma_reqs$DEQ = CAN_FIRE_RL_rl_sfence_vma ;
assign f_sfence_vma_reqs$CLR = 1'b0 ;
// submodule f_sfence_vma_rsps
assign f_sfence_vma_rsps$ENQ = CAN_FIRE_RL_rl_sfence_vma ;
assign f_sfence_vma_rsps$DEQ = EN_sfence_vma_server_response_get ;
assign f_sfence_vma_rsps$CLR = 1'b0 ;
// submodule icache
assign icache$mem_master_arready = imem_master_arready ;
assign icache$mem_master_awready = imem_master_awready ;
assign icache$mem_master_bid = imem_master_bid ;
assign icache$mem_master_bresp = imem_master_bresp ;
assign icache$mem_master_bvalid = imem_master_bvalid ;
assign icache$mem_master_rdata = imem_master_rdata ;
assign icache$mem_master_rid = imem_master_rid ;
assign icache$mem_master_rlast = imem_master_rlast ;
assign icache$mem_master_rresp = imem_master_rresp ;
assign icache$mem_master_rvalid = imem_master_rvalid ;
assign icache$mem_master_wready = imem_master_wready ;
assign icache$req_addr = imem_req_addr ;
assign icache$req_amo_funct7 = 7'b0101010 /* unspecified value */ ;
assign icache$req_f3 = imem_req_f3 ;
assign icache$req_mstatus_MXR = imem_req_mstatus_MXR ;
assign icache$req_op = 2'd0 ;
assign icache$req_priv = imem_req_priv ;
assign icache$req_satp = imem_req_satp ;
assign icache$req_sstatus_SUM = imem_req_sstatus_SUM ;
assign icache$req_st_value = 64'hAAAAAAAAAAAAAAAA /* unspecified value */ ;
assign icache$set_verbosity_verbosity = 4'h0 ;
assign icache$set_watch_tohost_tohost_addr = 64'h0 ;
assign icache$set_watch_tohost_watch_tohost = 1'b0 ;
assign icache$EN_set_verbosity = 1'b0 ;
assign icache$EN_server_reset_request_put = MUX_rg_state$write_1__SEL_2 ;
assign icache$EN_server_reset_response_get = MUX_rg_state$write_1__SEL_3 ;
assign icache$EN_req = EN_imem_req ;
assign icache$EN_server_flush_request_put = EN_server_fence_i_request_put ;
assign icache$EN_server_flush_response_get =
EN_server_fence_i_response_get ;
assign icache$EN_tlb_flush = CAN_FIRE_RL_rl_sfence_vma ;
assign icache$EN_set_watch_tohost = 1'b0 ;
assign icache$EN_ma_ddr4_ready = EN_ma_ddr4_ready ;
// submodule soc_map
assign soc_map$m_is_IO_addr_addr = 64'h0 ;
assign soc_map$m_is_mem_addr_addr = 64'h0 ;
assign soc_map$m_is_near_mem_IO_addr_addr = 64'h0 ;
// remaining internal signals
assign NOT_cfg_verbosity_read_ULE_1___d9 = cfg_verbosity > 4'd1 ;
// handling of inlined registers
always@(posedge CLK)
begin
if (RST_N == `BSV_RESET_VALUE)
begin
cfg_verbosity <= `BSV_ASSIGNMENT_DELAY 4'd0;
rg_state <= `BSV_ASSIGNMENT_DELAY 2'd2;
end
else
begin
if (cfg_verbosity$EN)
cfg_verbosity <= `BSV_ASSIGNMENT_DELAY cfg_verbosity$D_IN;
if (rg_state$EN) rg_state <= `BSV_ASSIGNMENT_DELAY rg_state$D_IN;
end
end
// synopsys translate_off
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
initial
begin
cfg_verbosity = 4'hA;
rg_state = 2'h2;
end
`endif // BSV_NO_INITIAL_BLOCKS
// synopsys translate_on
// handling of system tasks
// synopsys translate_off
always@(negedge CLK)
begin
#0;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_reset && NOT_cfg_verbosity_read_ULE_1___d9)
begin
v__h1730 = $stime;
#0;
end
v__h1724 = v__h1730 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_reset && NOT_cfg_verbosity_read_ULE_1___d9)
$display("%0d: Near_Mem.rl_reset", v__h1724);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_reset_complete && NOT_cfg_verbosity_read_ULE_1___d9)
begin
v__h1884 = $stime;
#0;
end
v__h1878 = v__h1884 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_reset_complete && NOT_cfg_verbosity_read_ULE_1___d9)
$display("%0d: Near_Mem.rl_reset_complete", v__h1878);
end
// synopsys translate_on
endmodule |
module sky130_fd_sc_hdll__conb (
HI ,
LO ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output HI ;
output LO ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire pullup0_out_HI ;
wire pulldown0_out_LO;
// Name Output Other arguments
pullup pullup0 (pullup0_out_HI );
sky130_fd_sc_hdll__udp_pwrgood_pp$P pwrgood_pp0 (HI , pullup0_out_HI, VPWR );
pulldown pulldown0 (pulldown0_out_LO);
sky130_fd_sc_hdll__udp_pwrgood_pp$G pwrgood_pp1 (LO , pulldown0_out_LO, VGND);
endmodule |
module hs_demo #(
parameter BUFFER_WIDTH = 10,
parameter FIFO_WIDTH = 10
)(
input clk,
input rst,
output o_idle,
//DEMO CODE START
input i_bram_wea,
input [BUFFER_WIDTH - 1:0] i_bram_addr,
input [31:0] i_bram_din,
output [31:0] o_bram_dout,
//DEMO CODE END
//Write Side
input i_write_enable,
input [63:0] i_write_addr,
input i_write_addr_inc,
input i_write_addr_dec,
output o_write_finished,
input [23:0] i_write_count,
input i_write_flush,
output [1:0] o_write_ready,
input [1:0] i_write_activate,
output [23:0] o_write_size,
input i_write_strobe,
input [31:0] i_write_data,
//Read Side
input i_read_enable,
input [63:0] i_read_addr,
input i_read_addr_inc,
input i_read_addr_dec,
output o_read_busy,
output o_read_error,
input [23:0] i_read_count,
input i_read_flush,
output o_read_ready,
input i_read_activate,
output [23:0] o_read_size,
output [31:0] o_read_data,
input i_read_strobe
);
//local parameters
localparam IDLE = 0;
localparam INGRESS_DMA_EN = 1;
localparam INGRESS_DMA_ACT = 2;
localparam INGRESS_DMA_FLUSH = 3;
localparam EGRESS_DMA_EN = 4;
localparam EGRESS_DMA_ACT = 5;
localparam EGRESS_DMA_FLUSH = 6;
//registes/wires
reg [23:0] r_count;
reg [3:0] state;
reg r_ingress_rd_stb;
wire w_ingress_rd_rdy;
reg r_ingress_rd_act;
wire [23:0] w_ingress_rd_size;
wire [31:0] w_ingress_rd_data;
wire [1:0] w_egress_wr_rdy;
reg [1:0] r_egress_wr_act;
wire [23:0] w_egress_wr_size;
reg r_egress_wr_stb;
//reg [31:0] w_egress_wr_data;
wire [31:0] w_egress_wr_data;
wire usr_clk;
reg [23:0] r_transfer_size;
//Demo Application Signals
reg r_wea_a;
reg [BUFFER_WIDTH - 1:0] r_addr_a;
//reg [31:0] w_din_a;
wire [31:0] w_din_a;
wire [31:0] w_dout_a;
//submodules
ppfifo #(
.DATA_WIDTH (32 ),
.ADDRESS_WIDTH (FIFO_WIDTH )
)ingress(
//universal input
.reset (rst ),
//write side
.write_clock (clk ),
.write_ready (o_write_ready ),
.write_activate (i_write_activate ),
.write_fifo_size(o_write_size ),
.write_strobe (i_write_strobe ),
.write_data (i_write_data ),
.starved ( ),
//read side
.read_clock (usr_clk ), //This does not have to be the same clock for write side
.read_strobe (r_ingress_rd_stb ),
.read_ready (w_ingress_rd_rdy ),
.read_activate (r_ingress_rd_act ),
.read_count (w_ingress_rd_size ),
.read_data (w_ingress_rd_data ),
.inactive ( )
);
ppfifo #(
.DATA_WIDTH (32 ),
.ADDRESS_WIDTH (FIFO_WIDTH )
) egress (
//universal input
.reset (rst ),
//write side
.write_clock (usr_clk ), //This does not have to be the same clock for read side
.write_ready (w_egress_wr_rdy ),
.write_activate (r_egress_wr_act ),
.write_fifo_size(w_egress_wr_size ),
.write_strobe (r_egress_wr_stb ),
.write_data (w_egress_wr_data ),
.starved ( ),
//read side
.read_clock (clk ),
.read_strobe (i_read_strobe ),
.read_ready (o_read_ready ),
.read_activate (i_read_activate ),
.read_count (o_read_size ),
.read_data (o_read_data ),
.inactive ( )
);
/*
DEMO Application (Local Dual Port Buffer)
right now the dual port buffer is connected to both sides of the ping pong
FIFOs The output of the PPFIFOs can be used to attach to any interface such
as:
CSI Camera Reader
If this core were to control a CSI camera the output data would go into
the EGRESS PPFIFO
DSI Video Writer
If this core were to control a DSI display, the input would come from
the INGRESS PPFIFO
*/
//Read/Write Data to a local buffer
dpb #(
.DATA_WIDTH (32 ),
.ADDR_WIDTH (BUFFER_WIDTH )
) local_buffer (
.clka (usr_clk ),
.wea (r_wea_a ),
.addra (r_addr_a ),
.dina (w_din_a ),
.douta (w_dout_a ),
.clkb (clk ),
.web (i_bram_wea ),
.addrb (i_bram_addr ),
.dinb (i_bram_din ),
.doutb (o_bram_dout )
);
//asynchronous logic
assign usr_clk = clk; //The usr_clk does not need to be the same as the system clock
assign o_read_error = 1'b0;
assign w_din_a = w_ingress_rd_data;
assign w_egress_wr_data = w_dout_a;
//synchronous logic
always @ (posedge clk) begin
//De-assert Strobes
if (rst) begin
//State Machine
state <= IDLE;
//PPFIFO
r_ingress_rd_act <= 0;
r_egress_wr_act <= 0;
//w_egress_wr_data <= 0;
r_transfer_size <= 0;
//Demo Application Buffer
/* DEMO CODE START */
r_wea_a <= 0;
r_addr_a <= 0;
//w_din_a <= 0;
/* DEMO CODE END */
end
else begin
r_ingress_rd_stb <= 0;
r_egress_wr_stb <= 0;
case (state)
IDLE: begin
r_ingress_rd_act <= 0;
r_egress_wr_act <= 0;
//w_egress_wr_data <= 0;
r_count <= 0;
/* DEMO CODE START */
r_wea_a <= 0;
r_addr_a <= 0;
//w_din_a <= 0;
/* DEMO CODE END */
//if (i_write_enable || w_ingress_rd_rdy) begin
if (w_ingress_rd_rdy) begin
state <= INGRESS_DMA_EN;
r_addr_a <= i_write_addr;
r_transfer_size <= i_write_count;
end
else if (i_read_enable) begin
state <= EGRESS_DMA_EN;
r_addr_a <= i_read_addr;
r_transfer_size <= i_read_count;
end
end
//Incomming Data
INGRESS_DMA_EN: begin
if (w_ingress_rd_rdy && !r_ingress_rd_act) begin
//Activate a FIFO
r_ingress_rd_act <= 1;
r_count <= 0;
/* DEMO CODE START */
//r_wea_a <= 1;
//w_din_a <= 0;
/* DEMO CODE END */
state <= INGRESS_DMA_ACT;
end
if (i_write_flush) begin
state <= INGRESS_DMA_FLUSH;
end
//if (!i_write_enable && !w_ingress_rd_rdy) begin
if (!w_ingress_rd_rdy) begin
//This is the only place where we can return to IDLE state
state <= IDLE;
end
end
INGRESS_DMA_ACT: begin
//Read everything from the FIFO and put it into the dual port RAM
if (r_ingress_rd_stb) begin
if (i_write_addr_inc) begin
r_addr_a <= r_addr_a + 1;
end
else if (i_write_addr_dec) begin
r_addr_a <= r_addr_a - 1;
end
end
if (r_count < w_ingress_rd_size) begin
//w_din_a <= w_ingress_rd_data;
r_ingress_rd_stb <= 1;
r_wea_a <= 1;
r_count <= r_count + 1;
end
else begin
r_wea_a <= 0;
r_ingress_rd_act <= 0;
state <= INGRESS_DMA_EN;
end
end
INGRESS_DMA_FLUSH: begin
//Flush the ingress FIFO
if (w_ingress_rd_rdy && !r_ingress_rd_act) begin
//If there is a buffer available activate it
r_ingress_rd_act <= 1;
r_count <= 0;
end
else if(r_ingress_rd_act) begin
//Eat it all
if (r_count < w_ingress_rd_size) begin
r_ingress_rd_stb<= 1;
r_count <= r_count + 1;
end
else begin
//No more left
r_ingress_rd_act <= 0;
end
end
else begin
//Go back to wait for more instruction from the controller
state <= INGRESS_DMA_EN;
end
end
//Outgoing Data
EGRESS_DMA_EN: begin
//User wants to read data from the local buffer
if (i_read_enable) begin
if ((w_egress_wr_rdy > 0) && (r_egress_wr_act == 0)) begin
r_count <= 0;
if (w_egress_wr_rdy[0]) begin
r_egress_wr_act[0] <= 1;
end
else begin
r_egress_wr_act[1] <= 1;
end
state <= EGRESS_DMA_ACT;
end
end
else begin
state <= IDLE;
end
end
EGRESS_DMA_ACT: begin
if (r_egress_wr_act > 0) begin
if (r_count < w_egress_wr_size) begin
r_count <= r_count + 1;
r_egress_wr_stb <= 1;
//w_egress_wr_data <= w_dout_a;
if (i_read_addr_inc) begin
r_addr_a <= r_addr_a + 1;
end
else if (i_read_addr_dec) begin
r_addr_a <= r_addr_a - 1;
end
end
else begin
r_egress_wr_act <= 0;
end
end
else begin
state <= EGRESS_DMA_EN;
end
if (i_read_flush) begin
state <= EGRESS_DMA_FLUSH;
end
end
EGRESS_DMA_FLUSH: begin
if (r_egress_wr_act > 0) begin
if (r_count < w_egress_wr_size) begin
//w_egress_wr_data <= 32'h00000000;
r_count <= r_count + 1;
end
else begin
r_egress_wr_act <= 0;
end
end
else begin
state <= EGRESS_DMA_EN;
end
end
default: begin
end
endcase
end
end
endmodule |
module riffa_wrapper_de4
#(// Number of RIFFA Channels
parameter C_NUM_CHNL = 1,
// Bit-Width from Quartus IP Generator
parameter C_PCI_DATA_WIDTH = 128,
parameter C_MAX_PAYLOAD_BYTES = 256,
parameter C_LOG_NUM_TAGS = 5,
parameter C_FPGA_ID = "ADE4")
(// Interface: Altera RX
input [C_PCI_DATA_WIDTH-1:0] RX_ST_DATA,
input [0:0] RX_ST_EOP,
input [0:0] RX_ST_SOP,
input [0:0] RX_ST_VALID,
output RX_ST_READY,
input [0:0] RX_ST_EMPTY,
// Interface: Altera TX
output [C_PCI_DATA_WIDTH-1:0] TX_ST_DATA,
output [0:0] TX_ST_VALID,
input TX_ST_READY,
output [0:0] TX_ST_EOP,
output [0:0] TX_ST_SOP,
output [0:0] TX_ST_EMPTY,
// Interface: Altera Config
input [`SIG_CFG_CTL_W-1:0] TL_CFG_CTL,
input [`SIG_CFG_ADD_W-1:0] TL_CFG_ADD,
input [`SIG_CFG_STS_W-1:0] TL_CFG_STS,
// Interface: Altera Flow Control
input [`SIG_KO_CPLH_W-1:0] KO_CPL_SPC_HEADER,
input [`SIG_KO_CPLD_W-1:0] KO_CPL_SPC_DATA,
// Interface: Altera Interrupt
input APP_MSI_ACK,
output APP_MSI_REQ,
// Interface: Altera CLK/RESET
input PLD_CLK,
input RESET_STATUS,
// RIFFA Interface Signals
output RST_OUT,
input [C_NUM_CHNL-1:0] CHNL_RX_CLK, // Channel read clock
output [C_NUM_CHNL-1:0] CHNL_RX, // Channel read receive signal
input [C_NUM_CHNL-1:0] CHNL_RX_ACK, // Channel read received signal
output [C_NUM_CHNL-1:0] CHNL_RX_LAST, // Channel last read
output [(C_NUM_CHNL*`SIG_CHNL_LENGTH_W)-1:0] CHNL_RX_LEN, // Channel read length
output [(C_NUM_CHNL*`SIG_CHNL_OFFSET_W)-1:0] CHNL_RX_OFF, // Channel read offset
output [(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0] CHNL_RX_DATA, // Channel read data
output [C_NUM_CHNL-1:0] CHNL_RX_DATA_VALID, // Channel read data valid
input [C_NUM_CHNL-1:0] CHNL_RX_DATA_REN, // Channel read data has been recieved
input [C_NUM_CHNL-1:0] CHNL_TX_CLK, // Channel write clock
input [C_NUM_CHNL-1:0] CHNL_TX, // Channel write receive signal
output [C_NUM_CHNL-1:0] CHNL_TX_ACK, // Channel write acknowledgement signal
input [C_NUM_CHNL-1:0] CHNL_TX_LAST, // Channel last write
input [(C_NUM_CHNL*`SIG_CHNL_LENGTH_W)-1:0] CHNL_TX_LEN, // Channel write length (in 32 bit words)
input [(C_NUM_CHNL*`SIG_CHNL_OFFSET_W)-1:0] CHNL_TX_OFF, // Channel write offset
input [(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0] CHNL_TX_DATA, // Channel write data
input [C_NUM_CHNL-1:0] CHNL_TX_DATA_VALID, // Channel write data valid
output [C_NUM_CHNL-1:0] CHNL_TX_DATA_REN); // Channel write data has been recieved
localparam C_FPGA_NAME = "REGT"; // This is not yet exposed in the driver
localparam C_MAX_READ_REQ_BYTES = C_MAX_PAYLOAD_BYTES * 2;
localparam C_VENDOR = "ALTERA";
localparam C_ALTERA_TX_READY_LATENCY = 2;
localparam C_KEEP_WIDTH = C_PCI_DATA_WIDTH / 32;
localparam C_PIPELINE_OUTPUT = 1;
localparam C_PIPELINE_INPUT = 1;
localparam C_DEPTH_PACKETS = 4;
wire clk;
wire rst_in;
wire done_txc_rst;
wire done_txr_rst;
wire done_rxr_rst;
wire done_rxc_rst;
// Interface: RXC Engine
wire [C_PCI_DATA_WIDTH-1:0] rxc_data;
wire rxc_data_valid;
wire rxc_data_start_flag;
wire [(C_PCI_DATA_WIDTH/32)-1:0] rxc_data_word_enable;
wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] rxc_data_start_offset;
wire [`SIG_FBE_W-1:0] rxc_meta_fdwbe;
wire rxc_data_end_flag;
wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] rxc_data_end_offset;
wire [`SIG_LBE_W-1:0] rxc_meta_ldwbe;
wire [`SIG_TAG_W-1:0] rxc_meta_tag;
wire [`SIG_LOWADDR_W-1:0] rxc_meta_addr;
wire [`SIG_TYPE_W-1:0] rxc_meta_type;
wire [`SIG_LEN_W-1:0] rxc_meta_length;
wire [`SIG_BYTECNT_W-1:0] rxc_meta_bytes_remaining;
wire [`SIG_CPLID_W-1:0] rxc_meta_completer_id;
wire rxc_meta_ep;
// Interface: RXR Engine
wire [C_PCI_DATA_WIDTH-1:0] rxr_data;
wire rxr_data_valid;
wire [(C_PCI_DATA_WIDTH/32)-1:0] rxr_data_word_enable;
wire rxr_data_start_flag;
wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] rxr_data_start_offset;
wire [`SIG_FBE_W-1:0] rxr_meta_fdwbe;
wire rxr_data_end_flag;
wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] rxr_data_end_offset;
wire [`SIG_LBE_W-1:0] rxr_meta_ldwbe;
wire [`SIG_TC_W-1:0] rxr_meta_tc;
wire [`SIG_ATTR_W-1:0] rxr_meta_attr;
wire [`SIG_TAG_W-1:0] rxr_meta_tag;
wire [`SIG_TYPE_W-1:0] rxr_meta_type;
wire [`SIG_ADDR_W-1:0] rxr_meta_addr;
wire [`SIG_BARDECODE_W-1:0] rxr_meta_bar_decoded;
wire [`SIG_REQID_W-1:0] rxr_meta_requester_id;
wire [`SIG_LEN_W-1:0] rxr_meta_length;
wire rxr_meta_ep;
// interface: TXC Engine
wire txc_data_valid;
wire [C_PCI_DATA_WIDTH-1:0] txc_data;
wire txc_data_start_flag;
wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] txc_data_start_offset;
wire txc_data_end_flag;
wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] txc_data_end_offset;
wire txc_data_ready;
wire txc_meta_valid;
wire [`SIG_FBE_W-1:0] txc_meta_fdwbe;
wire [`SIG_LBE_W-1:0] txc_meta_ldwbe;
wire [`SIG_LOWADDR_W-1:0] txc_meta_addr;
wire [`SIG_TYPE_W-1:0] txc_meta_type;
wire [`SIG_LEN_W-1:0] txc_meta_length;
wire [`SIG_BYTECNT_W-1:0] txc_meta_byte_count;
wire [`SIG_TAG_W-1:0] txc_meta_tag;
wire [`SIG_REQID_W-1:0] txc_meta_requester_id;
wire [`SIG_TC_W-1:0] txc_meta_tc;
wire [`SIG_ATTR_W-1:0] txc_meta_attr;
wire txc_meta_ep;
wire txc_meta_ready;
wire txc_sent;
// Interface: TXR Engine
wire txr_data_valid;
wire [C_PCI_DATA_WIDTH-1:0] txr_data;
wire txr_data_start_flag;
wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] txr_data_start_offset;
wire txr_data_end_flag;
wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] txr_data_end_offset;
wire txr_data_ready;
wire txr_meta_valid;
wire [`SIG_FBE_W-1:0] txr_meta_fdwbe;
wire [`SIG_LBE_W-1:0] txr_meta_ldwbe;
wire [`SIG_ADDR_W-1:0] txr_meta_addr;
wire [`SIG_LEN_W-1:0] txr_meta_length;
wire [`SIG_TAG_W-1:0] txr_meta_tag;
wire [`SIG_TC_W-1:0] txr_meta_tc;
wire [`SIG_ATTR_W-1:0] txr_meta_attr;
wire [`SIG_TYPE_W-1:0] txr_meta_type;
wire txr_meta_ep;
wire txr_meta_ready;
wire txr_sent;
// Classic Interface Wires
wire rx_tlp_ready;
wire [C_PCI_DATA_WIDTH-1:0] rx_tlp;
wire rx_tlp_end_flag;
wire [`SIG_OFFSET_W-1:0] rx_tlp_end_offset;
wire rx_tlp_start_flag;
wire [`SIG_OFFSET_W-1:0] rx_tlp_start_offset;
wire rx_tlp_valid;
wire [`SIG_BARDECODE_W-1:0] rx_tlp_bar_decode;
wire tx_tlp_ready;
wire [C_PCI_DATA_WIDTH-1:0] tx_tlp;
wire tx_tlp_end_flag;
wire [`SIG_OFFSET_W-1:0] tx_tlp_end_offset;
wire tx_tlp_start_flag;
wire [`SIG_OFFSET_W-1:0] tx_tlp_start_offset;
wire tx_tlp_valid;
// Unconnected Wires (Used in ultrascale interface)
// Interface: RQ (TXC)
wire s_axis_rq_tlast_nc;
wire [C_PCI_DATA_WIDTH-1:0] s_axis_rq_tdata_nc;
wire [`SIG_RQ_TUSER_W-1:0] s_axis_rq_tuser_nc;
wire [(C_PCI_DATA_WIDTH/32)-1:0] s_axis_rq_tkeep_nc;
wire s_axis_rq_tready_nc = 0;
wire s_axis_rq_tvalid_nc;
// Interface: RC (RXC)
wire [C_PCI_DATA_WIDTH-1:0] m_axis_rc_tdata_nc = 0;
wire [`SIG_RC_TUSER_W-1:0] m_axis_rc_tuser_nc = 0;
wire m_axis_rc_tlast_nc = 0;
wire [(C_PCI_DATA_WIDTH/32)-1:0] m_axis_rc_tkeep_nc = 0;
wire m_axis_rc_tvalid_nc = 0;
wire m_axis_rc_tready_nc;
// Interface: CQ (RXR)
wire [C_PCI_DATA_WIDTH-1:0] m_axis_cq_tdata_nc = 0;
wire [`SIG_CQ_TUSER_W-1:0] m_axis_cq_tuser_nc = 0;
wire m_axis_cq_tlast_nc = 0;
wire [(C_PCI_DATA_WIDTH/32)-1:0] m_axis_cq_tkeep_nc = 0;
wire m_axis_cq_tvalid_nc = 0;
wire m_axis_cq_tready_nc = 0;
// Interface: CC (TXC)
wire [C_PCI_DATA_WIDTH-1:0] s_axis_cc_tdata_nc;
wire [`SIG_CC_TUSER_W-1:0] s_axis_cc_tuser_nc;
wire s_axis_cc_tlast_nc;
wire [(C_PCI_DATA_WIDTH/32)-1:0] s_axis_cc_tkeep_nc;
wire s_axis_cc_tvalid_nc;
wire s_axis_cc_tready_nc = 0;
// Interface: Configuration
wire config_bus_master_enable;
wire [`SIG_CPLID_W-1:0] config_completer_id;
wire config_cpl_boundary_sel;
wire config_interrupt_msienable;
wire [`SIG_LINKRATE_W-1:0] config_link_rate;
wire [`SIG_LINKWIDTH_W-1:0] config_link_width;
wire [`SIG_MAXPAYLOAD_W-1:0] config_max_payload_size;
wire [`SIG_MAXREAD_W-1:0] config_max_read_request_size;
wire [`SIG_FC_CPLD_W-1:0] config_max_cpl_data;
wire [`SIG_FC_CPLH_W-1:0] config_max_cpl_hdr;
wire intr_msi_request;
wire intr_msi_rdy;
genvar chnl;
assign clk = PLD_CLK;
assign rst_in = RESET_STATUS;
translation_altera
#(/*AUTOINSTPARAM*/
// Parameters
.C_PCI_DATA_WIDTH (C_PCI_DATA_WIDTH))
trans
(
// Outputs
.RX_TLP (rx_tlp[C_PCI_DATA_WIDTH-1:0]),
.RX_TLP_VALID (rx_tlp_valid),
.RX_TLP_START_FLAG (rx_tlp_start_flag),
.RX_TLP_START_OFFSET (rx_tlp_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.RX_TLP_END_FLAG (rx_tlp_end_flag),
.RX_TLP_END_OFFSET (rx_tlp_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.RX_TLP_BAR_DECODE (rx_tlp_bar_decode[`SIG_BARDECODE_W-1:0]),
.TX_TLP_READY (tx_tlp_ready),
.CONFIG_COMPLETER_ID (config_completer_id[`SIG_CPLID_W-1:0]),
.CONFIG_BUS_MASTER_ENABLE (config_bus_master_enable),
.CONFIG_LINK_WIDTH (config_link_width[`SIG_LINKWIDTH_W-1:0]),
.CONFIG_LINK_RATE (config_link_rate[`SIG_LINKRATE_W-1:0]),
.CONFIG_MAX_READ_REQUEST_SIZE (config_max_read_request_size[`SIG_MAXREAD_W-1:0]),
.CONFIG_MAX_PAYLOAD_SIZE (config_max_payload_size[`SIG_MAXPAYLOAD_W-1:0]),
.CONFIG_INTERRUPT_MSIENABLE (config_interrupt_msienable),
.CONFIG_CPL_BOUNDARY_SEL (config_cpl_boundary_sel),
.CONFIG_MAX_CPL_DATA (config_max_cpl_data[`SIG_FC_CPLD_W-1:0]),
.CONFIG_MAX_CPL_HDR (config_max_cpl_hdr[`SIG_FC_CPLH_W-1:0]),
.INTR_MSI_RDY (intr_msi_rdy),
// Inputs
.CLK (clk),
.RST_IN (rst_in),
.RX_TLP_READY (rx_tlp_ready),
.TX_TLP (tx_tlp[C_PCI_DATA_WIDTH-1:0]),
.TX_TLP_VALID (tx_tlp_valid),
.TX_TLP_START_FLAG (tx_tlp_start_flag),
.TX_TLP_START_OFFSET (tx_tlp_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.TX_TLP_END_FLAG (tx_tlp_end_flag),
.TX_TLP_END_OFFSET (tx_tlp_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.INTR_MSI_REQUEST (intr_msi_request),
/*AUTOINST*/
// Outputs
.RX_ST_READY (RX_ST_READY),
.TX_ST_DATA (TX_ST_DATA[C_PCI_DATA_WIDTH-1:0]),
.TX_ST_VALID (TX_ST_VALID[0:0]),
.TX_ST_EOP (TX_ST_EOP[0:0]),
.TX_ST_SOP (TX_ST_SOP[0:0]),
.TX_ST_EMPTY (TX_ST_EMPTY[0:0]),
.APP_MSI_REQ (APP_MSI_REQ),
// Inputs
.RX_ST_DATA (RX_ST_DATA[C_PCI_DATA_WIDTH-1:0]),
.RX_ST_EOP (RX_ST_EOP[0:0]),
.RX_ST_SOP (RX_ST_SOP[0:0]),
.RX_ST_VALID (RX_ST_VALID[0:0]),
.RX_ST_EMPTY (RX_ST_EMPTY[0:0]),
.TX_ST_READY (TX_ST_READY),
.TL_CFG_CTL (TL_CFG_CTL[`SIG_CFG_CTL_W-1:0]),
.TL_CFG_ADD (TL_CFG_ADD[`SIG_CFG_ADD_W-1:0]),
.TL_CFG_STS (TL_CFG_STS[`SIG_CFG_STS_W-1:0]),
.KO_CPL_SPC_HEADER (KO_CPL_SPC_HEADER[`SIG_FC_CPLH_W-1:0]),
.KO_CPL_SPC_DATA (KO_CPL_SPC_DATA[`SIG_FC_CPLD_W-1:0]),
.APP_MSI_ACK (APP_MSI_ACK));
engine_layer
#(// Parameters
.C_MAX_PAYLOAD_DWORDS (C_MAX_PAYLOAD_BYTES/4),
/*AUTOINSTPARAM*/
// Parameters
.C_PCI_DATA_WIDTH (C_PCI_DATA_WIDTH),
.C_LOG_NUM_TAGS (C_LOG_NUM_TAGS),
.C_PIPELINE_INPUT (C_PIPELINE_INPUT),
.C_PIPELINE_OUTPUT (C_PIPELINE_OUTPUT),
.C_VENDOR (C_VENDOR))
engine_layer_inst
(// Outputs
.RXC_DATA (rxc_data[C_PCI_DATA_WIDTH-1:0]),
.RXC_DATA_WORD_ENABLE (rxc_data_word_enable[(C_PCI_DATA_WIDTH/32)-1:0]),
.RXC_DATA_VALID (rxc_data_valid),
.RXC_DATA_START_FLAG (rxc_data_start_flag),
.RXC_DATA_START_OFFSET (rxc_data_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.RXC_META_FDWBE (rxc_meta_fdwbe[`SIG_FBE_W-1:0]),
.RXC_DATA_END_FLAG (rxc_data_end_flag),
.RXC_DATA_END_OFFSET (rxc_data_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.RXC_META_LDWBE (rxc_meta_ldwbe[`SIG_LBE_W-1:0]),
.RXC_META_TAG (rxc_meta_tag[`SIG_TAG_W-1:0]),
.RXC_META_ADDR (rxc_meta_addr[`SIG_LOWADDR_W-1:0]),
.RXC_META_TYPE (rxc_meta_type[`SIG_TYPE_W-1:0]),
.RXC_META_LENGTH (rxc_meta_length[`SIG_LEN_W-1:0]),
.RXC_META_BYTES_REMAINING (rxc_meta_bytes_remaining[`SIG_BYTECNT_W-1:0]),
.RXC_META_COMPLETER_ID (rxc_meta_completer_id[`SIG_CPLID_W-1:0]),
.RXC_META_EP (rxc_meta_ep),
.RXR_DATA (rxr_data[C_PCI_DATA_WIDTH-1:0]),
.RXR_DATA_WORD_ENABLE (rxr_data_word_enable[(C_PCI_DATA_WIDTH/32)-1:0]),
.RXR_DATA_VALID (rxr_data_valid),
.RXR_DATA_START_FLAG (rxr_data_start_flag),
.RXR_DATA_START_OFFSET (rxr_data_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.RXR_DATA_END_FLAG (rxr_data_end_flag),
.RXR_DATA_END_OFFSET (rxr_data_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.RXR_META_FDWBE (rxr_meta_fdwbe[`SIG_FBE_W-1:0]),
.RXR_META_LDWBE (rxr_meta_ldwbe[`SIG_LBE_W-1:0]),
.RXR_META_TC (rxr_meta_tc[`SIG_TC_W-1:0]),
.RXR_META_ATTR (rxr_meta_attr[`SIG_ATTR_W-1:0]),
.RXR_META_TAG (rxr_meta_tag[`SIG_TAG_W-1:0]),
.RXR_META_TYPE (rxr_meta_type[`SIG_TYPE_W-1:0]),
.RXR_META_ADDR (rxr_meta_addr[`SIG_ADDR_W-1:0]),
.RXR_META_BAR_DECODED (rxr_meta_bar_decoded[`SIG_BARDECODE_W-1:0]),
.RXR_META_REQUESTER_ID (rxr_meta_requester_id[`SIG_REQID_W-1:0]),
.RXR_META_LENGTH (rxr_meta_length[`SIG_LEN_W-1:0]),
.RXR_META_EP (rxr_meta_ep),
.TXC_DATA_READY (txc_data_ready),
.TXC_META_READY (txc_meta_ready),
.TXC_SENT (txc_sent),
.TXR_DATA_READY (txr_data_ready),
.TXR_META_READY (txr_meta_ready),
.TXR_SENT (txr_sent),
.RST_LOGIC (RST_OUT),
// Unconnected Outputs
.TX_TLP (tx_tlp),
.TX_TLP_VALID (tx_tlp_valid),
.TX_TLP_START_FLAG (tx_tlp_start_flag),
.TX_TLP_START_OFFSET (tx_tlp_start_offset),
.TX_TLP_END_FLAG (tx_tlp_end_flag),
.TX_TLP_END_OFFSET (tx_tlp_end_offset),
.RX_TLP_READY (rx_tlp_ready),
// Inputs
.CLK_BUS (clk),
.RST_BUS (rst_in),
.CONFIG_COMPLETER_ID (config_completer_id[`SIG_CPLID_W-1:0]),
.TXC_DATA_VALID (txc_data_valid),
.TXC_DATA (txc_data[C_PCI_DATA_WIDTH-1:0]),
.TXC_DATA_START_FLAG (txc_data_start_flag),
.TXC_DATA_START_OFFSET (txc_data_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.TXC_DATA_END_FLAG (txc_data_end_flag),
.TXC_DATA_END_OFFSET (txc_data_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.TXC_META_VALID (txc_meta_valid),
.TXC_META_FDWBE (txc_meta_fdwbe[`SIG_FBE_W-1:0]),
.TXC_META_LDWBE (txc_meta_ldwbe[`SIG_LBE_W-1:0]),
.TXC_META_ADDR (txc_meta_addr[`SIG_LOWADDR_W-1:0]),
.TXC_META_TYPE (txc_meta_type[`SIG_TYPE_W-1:0]),
.TXC_META_LENGTH (txc_meta_length[`SIG_LEN_W-1:0]),
.TXC_META_BYTE_COUNT (txc_meta_byte_count[`SIG_BYTECNT_W-1:0]),
.TXC_META_TAG (txc_meta_tag[`SIG_TAG_W-1:0]),
.TXC_META_REQUESTER_ID (txc_meta_requester_id[`SIG_REQID_W-1:0]),
.TXC_META_TC (txc_meta_tc[`SIG_TC_W-1:0]),
.TXC_META_ATTR (txc_meta_attr[`SIG_ATTR_W-1:0]),
.TXC_META_EP (txc_meta_ep),
.TXR_DATA_VALID (txr_data_valid),
.TXR_DATA (txr_data[C_PCI_DATA_WIDTH-1:0]),
.TXR_DATA_START_FLAG (txr_data_start_flag),
.TXR_DATA_START_OFFSET (txr_data_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.TXR_DATA_END_FLAG (txr_data_end_flag),
.TXR_DATA_END_OFFSET (txr_data_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.TXR_META_VALID (txr_meta_valid),
.TXR_META_FDWBE (txr_meta_fdwbe[`SIG_FBE_W-1:0]),
.TXR_META_LDWBE (txr_meta_ldwbe[`SIG_LBE_W-1:0]),
.TXR_META_ADDR (txr_meta_addr[`SIG_ADDR_W-1:0]),
.TXR_META_LENGTH (txr_meta_length[`SIG_LEN_W-1:0]),
.TXR_META_TAG (txr_meta_tag[`SIG_TAG_W-1:0]),
.TXR_META_TC (txr_meta_tc[`SIG_TC_W-1:0]),
.TXR_META_ATTR (txr_meta_attr[`SIG_ATTR_W-1:0]),
.TXR_META_TYPE (txr_meta_type[`SIG_TYPE_W-1:0]),
.TXR_META_EP (txr_meta_ep),
// Unconnected Inputs
.RX_TLP (rx_tlp),
.RX_TLP_VALID (rx_tlp_valid),
.RX_TLP_START_FLAG (rx_tlp_start_flag),
.RX_TLP_START_OFFSET (rx_tlp_start_offset),
.RX_TLP_END_FLAG (rx_tlp_end_flag),
.RX_TLP_END_OFFSET (rx_tlp_end_offset),
.RX_TLP_BAR_DECODE (rx_tlp_bar_decode),
.TX_TLP_READY (tx_tlp_ready),
.DONE_TXC_RST (done_txc_rst),
.DONE_TXR_RST (done_txr_rst),
.DONE_RXR_RST (done_rxc_rst),
.DONE_RXC_RST (done_rxr_rst),
// Outputs
.M_AXIS_CQ_TREADY (m_axis_cq_tready_nc),
.M_AXIS_RC_TREADY (m_axis_rc_tready_nc),
.S_AXIS_CC_TVALID (s_axis_cc_tvalid_nc),
.S_AXIS_CC_TLAST (s_axis_cc_tlast_nc),
.S_AXIS_CC_TDATA (s_axis_cc_tdata_nc[C_PCI_DATA_WIDTH-1:0]),
.S_AXIS_CC_TKEEP (s_axis_cc_tkeep_nc[(C_PCI_DATA_WIDTH/32)-1:0]),
.S_AXIS_CC_TUSER (s_axis_cc_tuser_nc[`SIG_CC_TUSER_W-1:0]),
.S_AXIS_RQ_TVALID (s_axis_rq_tvalid_nc),
.S_AXIS_RQ_TLAST (s_axis_rq_tlast_nc),
.S_AXIS_RQ_TDATA (s_axis_rq_tdata_nc[C_PCI_DATA_WIDTH-1:0]),
.S_AXIS_RQ_TKEEP (s_axis_rq_tkeep_nc[(C_PCI_DATA_WIDTH/32)-1:0]),
.S_AXIS_RQ_TUSER (s_axis_rq_tuser_nc[`SIG_RQ_TUSER_W-1:0]),
// Inputs
.M_AXIS_CQ_TVALID (m_axis_cq_tvalid_nc),
.M_AXIS_CQ_TLAST (m_axis_cq_tlast_nc),
.M_AXIS_CQ_TDATA (m_axis_cq_tdata_nc[C_PCI_DATA_WIDTH-1:0]),
.M_AXIS_CQ_TKEEP (m_axis_cq_tkeep_nc[(C_PCI_DATA_WIDTH/32)-1:0]),
.M_AXIS_CQ_TUSER (m_axis_cq_tuser_nc[`SIG_CQ_TUSER_W-1:0]),
.M_AXIS_RC_TVALID (m_axis_rc_tvalid_nc),
.M_AXIS_RC_TLAST (m_axis_rc_tlast_nc),
.M_AXIS_RC_TDATA (m_axis_rc_tdata_nc[C_PCI_DATA_WIDTH-1:0]),
.M_AXIS_RC_TKEEP (m_axis_rc_tkeep_nc[(C_PCI_DATA_WIDTH/32)-1:0]),
.M_AXIS_RC_TUSER (m_axis_rc_tuser_nc[`SIG_RC_TUSER_W-1:0]),
.S_AXIS_CC_TREADY (s_axis_cc_tready_nc),
.S_AXIS_RQ_TREADY (s_axis_rq_tready_nc)
/*AUTOINST*/);
riffa
#(.C_TAG_WIDTH (C_LOG_NUM_TAGS),/* TODO: Standardize declaration*/
/*AUTOINSTPARAM*/
// Parameters
.C_PCI_DATA_WIDTH (C_PCI_DATA_WIDTH),
.C_NUM_CHNL (C_NUM_CHNL),
.C_MAX_READ_REQ_BYTES (C_MAX_READ_REQ_BYTES),
.C_VENDOR (C_VENDOR),
.C_FPGA_NAME (C_FPGA_NAME),
.C_FPGA_ID (C_FPGA_ID),
.C_DEPTH_PACKETS (C_DEPTH_PACKETS))
riffa_inst
(// Outputs
.TXC_DATA (txc_data[C_PCI_DATA_WIDTH-1:0]),
.TXC_DATA_VALID (txc_data_valid),
.TXC_DATA_START_FLAG (txc_data_start_flag),
.TXC_DATA_START_OFFSET (txc_data_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.TXC_DATA_END_FLAG (txc_data_end_flag),
.TXC_DATA_END_OFFSET (txc_data_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.TXC_META_VALID (txc_meta_valid),
.TXC_META_FDWBE (txc_meta_fdwbe[`SIG_FBE_W-1:0]),
.TXC_META_LDWBE (txc_meta_ldwbe[`SIG_LBE_W-1:0]),
.TXC_META_ADDR (txc_meta_addr[`SIG_LOWADDR_W-1:0]),
.TXC_META_TYPE (txc_meta_type[`SIG_TYPE_W-1:0]),
.TXC_META_LENGTH (txc_meta_length[`SIG_LEN_W-1:0]),
.TXC_META_BYTE_COUNT (txc_meta_byte_count[`SIG_BYTECNT_W-1:0]),
.TXC_META_TAG (txc_meta_tag[`SIG_TAG_W-1:0]),
.TXC_META_REQUESTER_ID (txc_meta_requester_id[`SIG_REQID_W-1:0]),
.TXC_META_TC (txc_meta_tc[`SIG_TC_W-1:0]),
.TXC_META_ATTR (txc_meta_attr[`SIG_ATTR_W-1:0]),
.TXC_META_EP (txc_meta_ep),
.TXR_DATA_VALID (txr_data_valid),
.TXR_DATA (txr_data[C_PCI_DATA_WIDTH-1:0]),
.TXR_DATA_START_FLAG (txr_data_start_flag),
.TXR_DATA_START_OFFSET (txr_data_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.TXR_DATA_END_FLAG (txr_data_end_flag),
.TXR_DATA_END_OFFSET (txr_data_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.TXR_META_VALID (txr_meta_valid),
.TXR_META_FDWBE (txr_meta_fdwbe[`SIG_FBE_W-1:0]),
.TXR_META_LDWBE (txr_meta_ldwbe[`SIG_LBE_W-1:0]),
.TXR_META_ADDR (txr_meta_addr[`SIG_ADDR_W-1:0]),
.TXR_META_LENGTH (txr_meta_length[`SIG_LEN_W-1:0]),
.TXR_META_TAG (txr_meta_tag[`SIG_TAG_W-1:0]),
.TXR_META_TC (txr_meta_tc[`SIG_TC_W-1:0]),
.TXR_META_ATTR (txr_meta_attr[`SIG_ATTR_W-1:0]),
.TXR_META_TYPE (txr_meta_type[`SIG_TYPE_W-1:0]),
.TXR_META_EP (txr_meta_ep),
.INTR_MSI_REQUEST (intr_msi_request),
// Inputs
.CLK (clk),
.RXR_DATA (rxr_data[C_PCI_DATA_WIDTH-1:0]),
.RXR_DATA_VALID (rxr_data_valid),
.RXR_DATA_START_FLAG (rxr_data_start_flag),
.RXR_DATA_START_OFFSET (rxr_data_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.RXR_DATA_WORD_ENABLE (rxr_data_word_enable[(C_PCI_DATA_WIDTH/32)-1:0]),
.RXR_DATA_END_FLAG (rxr_data_end_flag),
.RXR_DATA_END_OFFSET (rxr_data_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.RXR_META_FDWBE (rxr_meta_fdwbe[`SIG_FBE_W-1:0]),
.RXR_META_LDWBE (rxr_meta_ldwbe[`SIG_LBE_W-1:0]),
.RXR_META_TC (rxr_meta_tc[`SIG_TC_W-1:0]),
.RXR_META_ATTR (rxr_meta_attr[`SIG_ATTR_W-1:0]),
.RXR_META_TAG (rxr_meta_tag[`SIG_TAG_W-1:0]),
.RXR_META_TYPE (rxr_meta_type[`SIG_TYPE_W-1:0]),
.RXR_META_ADDR (rxr_meta_addr[`SIG_ADDR_W-1:0]),
.RXR_META_BAR_DECODED (rxr_meta_bar_decoded[`SIG_BARDECODE_W-1:0]),
.RXR_META_REQUESTER_ID (rxr_meta_requester_id[`SIG_REQID_W-1:0]),
.RXR_META_LENGTH (rxr_meta_length[`SIG_LEN_W-1:0]),
.RXR_META_EP (rxr_meta_ep),
.RXC_DATA_VALID (rxc_data_valid),
.RXC_DATA (rxc_data[C_PCI_DATA_WIDTH-1:0]),
.RXC_DATA_START_FLAG (rxc_data_start_flag),
.RXC_DATA_START_OFFSET (rxc_data_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.RXC_DATA_WORD_ENABLE (rxc_data_word_enable[(C_PCI_DATA_WIDTH/32)-1:0]),
.RXC_DATA_END_FLAG (rxc_data_end_flag),
.RXC_DATA_END_OFFSET (rxc_data_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.RXC_META_FDWBE (rxc_meta_fdwbe[`SIG_FBE_W-1:0]),
.RXC_META_LDWBE (rxc_meta_ldwbe[`SIG_LBE_W-1:0]),
.RXC_META_TAG (rxc_meta_tag[`SIG_TAG_W-1:0]),
.RXC_META_ADDR (rxc_meta_addr[`SIG_LOWADDR_W-1:0]),
.RXC_META_TYPE (rxc_meta_type[`SIG_TYPE_W-1:0]),
.RXC_META_LENGTH (rxc_meta_length[`SIG_LEN_W-1:0]),
.RXC_META_BYTES_REMAINING (rxc_meta_bytes_remaining[`SIG_BYTECNT_W-1:0]),
.RXC_META_COMPLETER_ID (rxc_meta_completer_id[`SIG_CPLID_W-1:0]),
.RXC_META_EP (rxc_meta_ep),
.TXC_DATA_READY (txc_data_ready),
.TXC_META_READY (txc_meta_ready),
.TXC_SENT (txc_sent),
.TXR_DATA_READY (txr_data_ready),
.TXR_META_READY (txr_meta_ready),
.TXR_SENT (txr_sent),
.CONFIG_COMPLETER_ID (config_completer_id[`SIG_CPLID_W-1:0]),
.CONFIG_BUS_MASTER_ENABLE (config_bus_master_enable),
.CONFIG_LINK_WIDTH (config_link_width[`SIG_LINKWIDTH_W-1:0]),
.CONFIG_LINK_RATE (config_link_rate[`SIG_LINKRATE_W-1:0]),
.CONFIG_MAX_READ_REQUEST_SIZE (config_max_read_request_size[`SIG_MAXREAD_W-1:0]),
.CONFIG_MAX_PAYLOAD_SIZE (config_max_payload_size[`SIG_MAXPAYLOAD_W-1:0]),
.CONFIG_INTERRUPT_MSIENABLE (config_interrupt_msienable),
.CONFIG_CPL_BOUNDARY_SEL (config_cpl_boundary_sel),
.CONFIG_MAX_CPL_DATA (config_max_cpl_data[`SIG_FC_CPLD_W-1:0]),
.CONFIG_MAX_CPL_HDR (config_max_cpl_hdr[`SIG_FC_CPLH_W-1:0]),
.INTR_MSI_RDY (intr_msi_rdy),
.DONE_TXC_RST (done_txc_rst),
.DONE_TXR_RST (done_txr_rst),
.RST_BUS (rst_in),
/*AUTOINST*/
// Outputs
.RST_OUT (RST_OUT),
.CHNL_RX (CHNL_RX[C_NUM_CHNL-1:0]),
.CHNL_RX_LAST (CHNL_RX_LAST[C_NUM_CHNL-1:0]),
.CHNL_RX_LEN (CHNL_RX_LEN[(C_NUM_CHNL*32)-1:0]),
.CHNL_RX_OFF (CHNL_RX_OFF[(C_NUM_CHNL*31)-1:0]),
.CHNL_RX_DATA (CHNL_RX_DATA[(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0]),
.CHNL_RX_DATA_VALID (CHNL_RX_DATA_VALID[C_NUM_CHNL-1:0]),
.CHNL_TX_ACK (CHNL_TX_ACK[C_NUM_CHNL-1:0]),
.CHNL_TX_DATA_REN (CHNL_TX_DATA_REN[C_NUM_CHNL-1:0]),
// Inputs
.CHNL_RX_CLK (CHNL_RX_CLK[C_NUM_CHNL-1:0]),
.CHNL_RX_ACK (CHNL_RX_ACK[C_NUM_CHNL-1:0]),
.CHNL_RX_DATA_REN (CHNL_RX_DATA_REN[C_NUM_CHNL-1:0]),
.CHNL_TX_CLK (CHNL_TX_CLK[C_NUM_CHNL-1:0]),
.CHNL_TX (CHNL_TX[C_NUM_CHNL-1:0]),
.CHNL_TX_LAST (CHNL_TX_LAST[C_NUM_CHNL-1:0]),
.CHNL_TX_LEN (CHNL_TX_LEN[(C_NUM_CHNL*32)-1:0]),
.CHNL_TX_OFF (CHNL_TX_OFF[(C_NUM_CHNL*31)-1:0]),
.CHNL_TX_DATA (CHNL_TX_DATA[(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0]),
.CHNL_TX_DATA_VALID (CHNL_TX_DATA_VALID[C_NUM_CHNL-1:0]));
endmodule |
module alu (
op,
a,
b,
y,
cin,
cout,
zout
);
input [3:0] op; // ALU Operation
input [7:0] a; // 8-bit Input a
input [7:0] b; // 8-bit Input b
output [7:0] y; // 8-bit Output
input cin;
output cout;
output zout;
//
// Copyright (c) 1999 Thomas Coonan ([email protected])
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// Reg declarations for outputs
reg cout;
reg zout;
reg [7:0] y;
// Internal declarations
reg addercout; // Carry out straight from the adder itself.
parameter [3:0] ALUOP_ADD = 4'b0000;
parameter [3:0] ALUOP_SUB = 4'b1000;
parameter [3:0] ALUOP_AND = 4'b0001;
parameter [3:0] ALUOP_OR = 4'b0010;
parameter [3:0] ALUOP_XOR = 4'b0011;
parameter [3:0] ALUOP_COM = 4'b0100;
parameter [3:0] ALUOP_ROR = 4'b0101;
parameter [3:0] ALUOP_ROL = 4'b0110;
parameter [3:0] ALUOP_SWAP = 4'b0111;
always @(a or b or cin or op) begin
case (op) // synopsys parallel_case
ALUOP_ADD: {addercout, y} = a + b;
ALUOP_SUB: {addercout, y} = a - b; // Carry out is really "borrow"
ALUOP_AND: {addercout, y} = {1'b0, a & b};
ALUOP_OR: {addercout, y} = {1'b0, a | b};
ALUOP_XOR: {addercout, y} = {1'b0, a ^ b};
ALUOP_COM: {addercout, y} = {1'b0, ~a};
ALUOP_ROR: {addercout, y} = {a[0], cin, a[7:1]};
ALUOP_ROL: {addercout, y} = {a[7], a[6:0], cin};
ALUOP_SWAP: {addercout, y} = {1'b0, a[3:0], a[7:4]};
default: {addercout, y} = {1'b0, 8'h00};
endcase
end
always @(y)
zout = (y == 8'h00);
always @(addercout or op)
if (op == ALUOP_SUB) cout = ~addercout; // Invert adder's carry to get borrow
else cout = addercout;
endmodule |
module sky130_fd_sc_hs__fahcin (
COUT,
SUM ,
A ,
B ,
CIN ,
VPWR,
VGND
);
// Module ports
output COUT;
output SUM ;
input A ;
input B ;
input CIN ;
input VPWR;
input VGND;
// Local signals
wire ci ;
wire xor0_out_SUM ;
wire u_vpwr_vgnd0_out_SUM ;
wire a_b ;
wire a_ci ;
wire b_ci ;
wire or0_out_COUT ;
wire u_vpwr_vgnd1_out_COUT;
// Name Output Other arguments
not not0 (ci , CIN );
xor xor0 (xor0_out_SUM , A, B, ci );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_SUM , xor0_out_SUM, VPWR, VGND);
buf buf0 (SUM , u_vpwr_vgnd0_out_SUM );
and and0 (a_b , A, B );
and and1 (a_ci , A, ci );
and and2 (b_ci , B, ci );
or or0 (or0_out_COUT , a_b, a_ci, b_ci );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd1 (u_vpwr_vgnd1_out_COUT, or0_out_COUT, VPWR, VGND);
buf buf1 (COUT , u_vpwr_vgnd1_out_COUT );
endmodule |
module axi_hdmi_rx_es (
// hdmi interface
hdmi_clk,
hdmi_data,
hdmi_vs_de,
hdmi_hs_de,
hdmi_data_de);
// parameters
parameter DATA_WIDTH = 32;
localparam BYTE_WIDTH = DATA_WIDTH/8;
// hdmi interface
input hdmi_clk;
input [(DATA_WIDTH-1):0] hdmi_data;
// dma interface
output hdmi_vs_de;
output hdmi_hs_de;
output [(DATA_WIDTH-1):0] hdmi_data_de;
// internal registers
reg [(DATA_WIDTH-1):0] hdmi_data_d = 'd0;
reg hdmi_hs_de_rcv_d = 'd0;
reg hdmi_vs_de_rcv_d = 'd0;
reg [(DATA_WIDTH-1):0] hdmi_data_2d = 'd0;
reg hdmi_hs_de_rcv_2d = 'd0;
reg hdmi_vs_de_rcv_2d = 'd0;
reg [(DATA_WIDTH-1):0] hdmi_data_3d = 'd0;
reg hdmi_hs_de_rcv_3d = 'd0;
reg hdmi_vs_de_rcv_3d = 'd0;
reg [(DATA_WIDTH-1):0] hdmi_data_4d = 'd0;
reg hdmi_hs_de_rcv_4d = 'd0;
reg hdmi_vs_de_rcv_4d = 'd0;
reg [(DATA_WIDTH-1):0] hdmi_data_de = 'd0;
reg hdmi_hs_de = 'd0;
reg hdmi_vs_de = 'd0;
reg [ 1:0] hdmi_preamble_cnt = 'd0;
reg hdmi_hs_de_rcv = 'd0;
reg hdmi_vs_de_rcv = 'd0;
// internal signals
wire [(DATA_WIDTH-1):0] hdmi_ff_s;
wire [(DATA_WIDTH-1):0] hdmi_00_s;
wire [(DATA_WIDTH-1):0] hdmi_b6_s;
wire [(DATA_WIDTH-1):0] hdmi_9d_s;
wire [(DATA_WIDTH-1):0] hdmi_ab_s;
wire [(DATA_WIDTH-1):0] hdmi_80_s;
// es constants
assign hdmi_ff_s = {BYTE_WIDTH{8'hff}};
assign hdmi_00_s = {BYTE_WIDTH{8'h00}};
assign hdmi_b6_s = {BYTE_WIDTH{8'hb6}};
assign hdmi_9d_s = {BYTE_WIDTH{8'h9d}};
assign hdmi_ab_s = {BYTE_WIDTH{8'hab}};
assign hdmi_80_s = {BYTE_WIDTH{8'h80}};
// delay to get rid of eav's 4 bytes
always @(posedge hdmi_clk) begin
hdmi_data_d <= hdmi_data;
hdmi_hs_de_rcv_d <= hdmi_hs_de_rcv;
hdmi_vs_de_rcv_d <= hdmi_vs_de_rcv;
hdmi_data_2d <= hdmi_data_d;
hdmi_hs_de_rcv_2d <= hdmi_hs_de_rcv_d;
hdmi_vs_de_rcv_2d <= hdmi_vs_de_rcv_d;
hdmi_data_3d <= hdmi_data_2d;
hdmi_hs_de_rcv_3d <= hdmi_hs_de_rcv_2d;
hdmi_vs_de_rcv_3d <= hdmi_vs_de_rcv_2d;
hdmi_data_4d <= hdmi_data_3d;
hdmi_hs_de_rcv_4d <= hdmi_hs_de_rcv_3d;
hdmi_vs_de_rcv_4d <= hdmi_vs_de_rcv_3d;
hdmi_data_de <= hdmi_data_4d;
hdmi_hs_de <= hdmi_hs_de_rcv & hdmi_hs_de_rcv_4d;
hdmi_vs_de <= hdmi_vs_de_rcv & hdmi_vs_de_rcv_4d;
end
// check for sav and eav and generate the corresponding enables
always @(posedge hdmi_clk) begin
if ((hdmi_data == hdmi_ff_s) || (hdmi_data == hdmi_00_s)) begin
hdmi_preamble_cnt <= hdmi_preamble_cnt + 1'b1;
end else begin
hdmi_preamble_cnt <= 'd0;
end
if (hdmi_preamble_cnt == 3'b11) begin
if ((hdmi_data == hdmi_b6_s) || (hdmi_data == hdmi_9d_s)) begin
hdmi_hs_de_rcv <= 1'b0;
end else if ((hdmi_data == hdmi_ab_s) || (hdmi_data == hdmi_80_s)) begin
hdmi_hs_de_rcv <= 1'b1;
end
if (hdmi_data == hdmi_b6_s) begin
hdmi_vs_de_rcv <= 1'b0;
end else if (hdmi_data == hdmi_9d_s) begin
hdmi_vs_de_rcv <= 1'b1;
end
end
end
endmodule |
module clk_divider_test;
// Inputs
reg rst;
reg clk;
// Outputs
wire div_clk_2, div_clk_3, div_clk_4;
// Instantiate the Unit Under Test (UUT)
clk_divider #(.DIV(2)) uut2 (
.rst(rst),
.clk(clk),
.div_clk(div_clk_2)
);
clk_divider #(.DIV(3)) uut3 (
.rst(rst),
.clk(clk),
.div_clk(div_clk_3)
);
clk_divider #(.DIV(500)) uut4 (
.rst(rst),
.clk(clk),
.div_clk(div_clk_4)
);
reg [31:0] ctr_d, ctr_q;
always @(*) begin
ctr_d = ctr_q;
if(div_clk_4) begin
ctr_d = ctr_q + 1;
end
end
always @(posedge clk) begin
if (rst) begin
ctr_q <= 0;
end else begin
ctr_q <= ctr_d;
end
end
initial begin
// Initialize Inputs
clk = 0;
rst = 1'b1;
repeat(4) #10 clk = ~clk;
rst = 1'b0;
forever #10 clk = ~clk; // generate a clock
end
initial begin
@(negedge rst); // wait for reset
repeat(5000) @(posedge clk); //wait for trigger to finish, 10us
$finish;
end
endmodule |
module inputs)
reg clk; // To dut of mult_27x27.v
reg [26:0] opa; // To dut of mult_27x27.v
reg [26:0] opb; // To dut of mult_27x27.v
// End of automatics
mult_27x27 #(.LATENCY(LATENCY))
dut(/*AUTOINST*/
// Outputs
.res (res[53:0]),
// Inputs
.clk (clk),
.opa (opa[26:0]),
.opb (opb[26:0]));
reg running = 1;
initial while(running) begin
clk = 0;
#10;
clk = 1;
#10;
end
reg [53:0] expected_res;
reg res_is_valid = 0;
always @(posedge clk) begin
expected_res <= repeat(LATENCY-1) @(posedge clk) $unsigned(opa)*$unsigned(opb);
end
integer state = 10; // FIXME: Remove the unused state variable
initial begin
opa = 0;
opb = 0;
expected_res = 0;
repeat(100) @(posedge clk);
repeat(10000) @(posedge clk) begin : FOO
reg [26:0] restricted_opa;
//
if(1 || !state) begin
restricted_opa = {$random,$random} ;
if(restricted_opa[26]) begin
restricted_opa[2:0] = 3'b000;
end
opa <= restricted_opa;
opb <= {$random,$random};
opb <= $random;
state = 10;
end else begin
state = state - 1;
end
if(expected_res !== res) begin
$display("expected_res !== res!");
@(posedge clk);
@(posedge clk);
@(posedge clk);
@(posedge clk);
@(posedge clk);
@(posedge clk);
@(posedge clk);
@(posedge clk);
$stop;
// Note: We don't check the last few values, but it
// doesn't really matter as they are randomly generated
// anyway.
end
end
running = 0;
#10;
$display("");
$display("*** Multiplier test PASSED ***");
$display("");
end
initial begin
while(1) begin
$display(" opa opb res expected_res res^expected");
repeat(20) begin
@(posedge clk);
$display("%x %x %x %x %x ",opa,opb,res, expected_res, res^expected_res);
end
end
end
endmodule |
module EX_MEM(input clk,
input reset,
input [1:0] WB_in,
input [1:0] M_in,
input [31:0] ALU_in,
input [4:0] instruction_mux_in,
input [31:0] RDdata2_in,
input hold_i,
output reg MemWrite,
output reg MemRead,
output reg[1:0] WB_out,
output reg[31:0] ALU_out,
output reg[4:0] instruction_mux_out,
output reg[31:0] RDdata2_out);
always@(posedge reset)begin
MemWrite = 0;
MemRead = 0;
WB_out = 0;
ALU_out = 0;
RDdata2_out = 0;
instruction_mux_out = 0;
end
always@(posedge clk)begin
if(hold_i)begin
WB_out <= WB_out;
MemWrite <= MemWrite;
MemRead <= MemRead;
ALU_out <= ALU_out;
RDdata2_out <= RDdata2_out;
instruction_mux_out <= instruction_mux_out;
end
else begin
WB_out <= WB_in;
MemWrite <= M_in[1];
MemRead <= M_in[0];
ALU_out <= ALU_in;
RDdata2_out <= RDdata2_in;
instruction_mux_out <= instruction_mux_in;
end
end
endmodule |
module sky130_fd_sc_hd__dfxbp (
Q ,
Q_N,
CLK,
D
);
// Module ports
output Q ;
output Q_N;
input CLK;
input D ;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire buf_Q ;
reg notifier ;
wire D_delayed ;
wire CLK_delayed;
wire awake ;
// Name Output Other arguments
sky130_fd_sc_hd__udp_dff$P_pp$PG$N dff0 (buf_Q , D_delayed, CLK_delayed, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
buf buf0 (Q , buf_Q );
not not0 (Q_N , buf_Q );
endmodule |
module sky130_fd_sc_hd__o311a (
X ,
A1 ,
A2 ,
A3 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule |
module cpu_tb();
reg clk = 0;
//
// ROM
//
localparam MEM_ADDR = 3;
localparam MEM_EXTRA = 4;
reg [ MEM_ADDR :0] mem_addr;
reg [ MEM_EXTRA-1:0] mem_extra;
reg [ MEM_ADDR :0] rom_lower_bound = 0;
reg [ MEM_ADDR :0] rom_upper_bound = ~0;
wire [2**MEM_EXTRA*8-1:0] mem_data;
wire mem_error;
genrom #(
.ROMFILE("i64.eqz1.hex"),
.AW(MEM_ADDR),
.DW(8),
.EXTRA(MEM_EXTRA)
)
ROM (
.clk(clk),
.addr(mem_addr),
.extra(mem_extra),
.lower_bound(rom_lower_bound),
.upper_bound(rom_upper_bound),
.data(mem_data),
.error(mem_error)
);
//
// CPU
//
reg reset = 0;
wire [63:0] result;
wire result_empty;
wire [ 3:0] trap;
cpu #(
.MEM_DEPTH(MEM_ADDR)
)
dut
(
.clk(clk),
.reset(reset),
.result(result),
.result_empty(result_empty),
.trap(trap),
.mem_addr(mem_addr),
.mem_extra(mem_extra),
.mem_data(mem_data),
.mem_error(mem_error)
);
always #1 clk = ~clk;
initial begin
$dumpfile("i64.eqz1_tb.vcd");
$dumpvars(0, cpu_tb);
#18
`assert(result, 1);
`assert(result_empty, 0);
$finish;
end
endmodule |
module sky130_fd_sc_ls__o22a_1 (
X ,
A1 ,
A2 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__o22a base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule |
module sky130_fd_sc_ls__o22a_1 (
X ,
A1,
A2,
B1,
B2
);
output X ;
input A1;
input A2;
input B1;
input B2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__o22a base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2)
);
endmodule |
module eth_mac_10g #
(
parameter DATA_WIDTH = 64,
parameter KEEP_WIDTH = (DATA_WIDTH/8),
parameter CTRL_WIDTH = (DATA_WIDTH/8),
parameter ENABLE_PADDING = 1,
parameter ENABLE_DIC = 1,
parameter MIN_FRAME_LENGTH = 64,
parameter PTP_PERIOD_NS = 4'h6,
parameter PTP_PERIOD_FNS = 16'h6666,
parameter TX_PTP_TS_ENABLE = 0,
parameter TX_PTP_TS_WIDTH = 96,
parameter TX_PTP_TAG_ENABLE = TX_PTP_TS_ENABLE,
parameter TX_PTP_TAG_WIDTH = 16,
parameter RX_PTP_TS_ENABLE = 0,
parameter RX_PTP_TS_WIDTH = 96,
parameter TX_USER_WIDTH = (TX_PTP_TAG_ENABLE ? TX_PTP_TAG_WIDTH : 0) + 1,
parameter RX_USER_WIDTH = (RX_PTP_TS_ENABLE ? RX_PTP_TS_WIDTH : 0) + 1
)
(
input wire rx_clk,
input wire rx_rst,
input wire tx_clk,
input wire tx_rst,
/*
* AXI input
*/
input wire [DATA_WIDTH-1:0] tx_axis_tdata,
input wire [KEEP_WIDTH-1:0] tx_axis_tkeep,
input wire tx_axis_tvalid,
output wire tx_axis_tready,
input wire tx_axis_tlast,
input wire [TX_USER_WIDTH-1:0] tx_axis_tuser,
/*
* AXI output
*/
output wire [DATA_WIDTH-1:0] rx_axis_tdata,
output wire [KEEP_WIDTH-1:0] rx_axis_tkeep,
output wire rx_axis_tvalid,
output wire rx_axis_tlast,
output wire [RX_USER_WIDTH-1:0] rx_axis_tuser,
/*
* XGMII interface
*/
input wire [DATA_WIDTH-1:0] xgmii_rxd,
input wire [CTRL_WIDTH-1:0] xgmii_rxc,
output wire [DATA_WIDTH-1:0] xgmii_txd,
output wire [CTRL_WIDTH-1:0] xgmii_txc,
/*
* PTP
*/
input wire [TX_PTP_TS_WIDTH-1:0] tx_ptp_ts,
input wire [RX_PTP_TS_WIDTH-1:0] rx_ptp_ts,
output wire [TX_PTP_TS_WIDTH-1:0] tx_axis_ptp_ts,
output wire [TX_PTP_TAG_WIDTH-1:0] tx_axis_ptp_ts_tag,
output wire tx_axis_ptp_ts_valid,
/*
* Status
*/
output wire [1:0] tx_start_packet,
output wire tx_error_underflow,
output wire [1:0] rx_start_packet,
output wire rx_error_bad_frame,
output wire rx_error_bad_fcs,
/*
* Configuration
*/
input wire [7:0] ifg_delay
);
// bus width assertions
initial begin
if (DATA_WIDTH != 32 && DATA_WIDTH != 64) begin
$error("Error: Interface width must be 32 or 64");
$finish;
end
if (KEEP_WIDTH * 8 != DATA_WIDTH || CTRL_WIDTH * 8 != DATA_WIDTH) begin
$error("Error: Interface requires byte (8-bit) granularity");
$finish;
end
end
generate
if (DATA_WIDTH == 64) begin
axis_xgmii_rx_64 #(
.DATA_WIDTH(DATA_WIDTH),
.KEEP_WIDTH(KEEP_WIDTH),
.CTRL_WIDTH(CTRL_WIDTH),
.PTP_PERIOD_NS(PTP_PERIOD_NS),
.PTP_PERIOD_FNS(PTP_PERIOD_FNS),
.PTP_TS_ENABLE(RX_PTP_TS_ENABLE),
.PTP_TS_WIDTH(RX_PTP_TS_WIDTH),
.USER_WIDTH(RX_USER_WIDTH)
)
axis_xgmii_rx_inst (
.clk(rx_clk),
.rst(rx_rst),
.xgmii_rxd(xgmii_rxd),
.xgmii_rxc(xgmii_rxc),
.m_axis_tdata(rx_axis_tdata),
.m_axis_tkeep(rx_axis_tkeep),
.m_axis_tvalid(rx_axis_tvalid),
.m_axis_tlast(rx_axis_tlast),
.m_axis_tuser(rx_axis_tuser),
.ptp_ts(rx_ptp_ts),
.start_packet(rx_start_packet),
.error_bad_frame(rx_error_bad_frame),
.error_bad_fcs(rx_error_bad_fcs)
);
axis_xgmii_tx_64 #(
.DATA_WIDTH(DATA_WIDTH),
.KEEP_WIDTH(KEEP_WIDTH),
.CTRL_WIDTH(CTRL_WIDTH),
.ENABLE_PADDING(ENABLE_PADDING),
.ENABLE_DIC(ENABLE_DIC),
.MIN_FRAME_LENGTH(MIN_FRAME_LENGTH),
.PTP_PERIOD_NS(PTP_PERIOD_NS),
.PTP_PERIOD_FNS(PTP_PERIOD_FNS),
.PTP_TS_ENABLE(TX_PTP_TS_ENABLE),
.PTP_TS_WIDTH(TX_PTP_TS_WIDTH),
.PTP_TAG_ENABLE(TX_PTP_TAG_ENABLE),
.PTP_TAG_WIDTH(TX_PTP_TAG_WIDTH),
.USER_WIDTH(TX_USER_WIDTH)
)
axis_xgmii_tx_inst (
.clk(tx_clk),
.rst(tx_rst),
.s_axis_tdata(tx_axis_tdata),
.s_axis_tkeep(tx_axis_tkeep),
.s_axis_tvalid(tx_axis_tvalid),
.s_axis_tready(tx_axis_tready),
.s_axis_tlast(tx_axis_tlast),
.s_axis_tuser(tx_axis_tuser),
.xgmii_txd(xgmii_txd),
.xgmii_txc(xgmii_txc),
.ptp_ts(tx_ptp_ts),
.m_axis_ptp_ts(tx_axis_ptp_ts),
.m_axis_ptp_ts_tag(tx_axis_ptp_ts_tag),
.m_axis_ptp_ts_valid(tx_axis_ptp_ts_valid),
.ifg_delay(ifg_delay),
.start_packet(tx_start_packet),
.error_underflow(tx_error_underflow)
);
end else begin
axis_xgmii_rx_32 #(
.DATA_WIDTH(DATA_WIDTH),
.KEEP_WIDTH(KEEP_WIDTH),
.CTRL_WIDTH(CTRL_WIDTH),
.PTP_TS_ENABLE(RX_PTP_TS_ENABLE),
.PTP_TS_WIDTH(RX_PTP_TS_WIDTH),
.USER_WIDTH(RX_USER_WIDTH)
)
axis_xgmii_rx_inst (
.clk(rx_clk),
.rst(rx_rst),
.xgmii_rxd(xgmii_rxd),
.xgmii_rxc(xgmii_rxc),
.m_axis_tdata(rx_axis_tdata),
.m_axis_tkeep(rx_axis_tkeep),
.m_axis_tvalid(rx_axis_tvalid),
.m_axis_tlast(rx_axis_tlast),
.m_axis_tuser(rx_axis_tuser),
.ptp_ts(rx_ptp_ts),
.start_packet(rx_start_packet[0]),
.error_bad_frame(rx_error_bad_frame),
.error_bad_fcs(rx_error_bad_fcs)
);
assign rx_start_packet[1] = 1'b0;
axis_xgmii_tx_32 #(
.DATA_WIDTH(DATA_WIDTH),
.KEEP_WIDTH(KEEP_WIDTH),
.CTRL_WIDTH(CTRL_WIDTH),
.ENABLE_PADDING(ENABLE_PADDING),
.ENABLE_DIC(ENABLE_DIC),
.MIN_FRAME_LENGTH(MIN_FRAME_LENGTH),
.PTP_TS_ENABLE(TX_PTP_TS_ENABLE),
.PTP_TS_WIDTH(TX_PTP_TS_WIDTH),
.PTP_TAG_ENABLE(TX_PTP_TAG_ENABLE),
.PTP_TAG_WIDTH(TX_PTP_TAG_WIDTH),
.USER_WIDTH(TX_USER_WIDTH)
)
axis_xgmii_tx_inst (
.clk(tx_clk),
.rst(tx_rst),
.s_axis_tdata(tx_axis_tdata),
.s_axis_tkeep(tx_axis_tkeep),
.s_axis_tvalid(tx_axis_tvalid),
.s_axis_tready(tx_axis_tready),
.s_axis_tlast(tx_axis_tlast),
.s_axis_tuser(tx_axis_tuser),
.xgmii_txd(xgmii_txd),
.xgmii_txc(xgmii_txc),
.ptp_ts(tx_ptp_ts),
.m_axis_ptp_ts(tx_axis_ptp_ts),
.m_axis_ptp_ts_tag(tx_axis_ptp_ts_tag),
.m_axis_ptp_ts_valid(tx_axis_ptp_ts_valid),
.ifg_delay(ifg_delay),
.start_packet(tx_start_packet[0])
);
assign tx_start_packet[1] = 1'b0;
end
endgenerate
endmodule |
module vgafb_graycounter
#(parameter COUNTER_WIDTH = 2)
(output reg [COUNTER_WIDTH-1:0] GrayCount_out, //'Gray' code count output.
input wire Enable_in, //Count enable.
input wire Clear_in, //Count reset.
input wire Clk);
/////////Internal connections & variables///////
reg [COUNTER_WIDTH-1:0] BinaryCount;
/////////Code///////////////////////
always @ (posedge Clk)
if (Clear_in) begin
BinaryCount <= {COUNTER_WIDTH{1'b 0}} + 1; //Gray count begins @ '1' with
GrayCount_out <= {COUNTER_WIDTH{1'b 0}}; // first 'Enable_in'.
end
else if (Enable_in) begin
BinaryCount <= BinaryCount + 1;
GrayCount_out <= {BinaryCount[COUNTER_WIDTH-1],
BinaryCount[COUNTER_WIDTH-2:0] ^ BinaryCount[COUNTER_WIDTH-1:1]};
end
endmodule |
module FSM_C_CORDIC(
//INPUTS
input wire CLK, //system clock
input wire RST_EX, //system reset
input wire ACK_ADD_SUBTX, //RECIBE SI LA SUMA EN FLOTANTE X SE EJECUTO
input wire ACK_ADD_SUBTY, //RECIBE SI LA SUMA EN FLOTANTE Y SE EJECUTO
input wire ACK_ADD_SUBTZ, //RECIBE SI LA SUMA EN FLOTANTE Z SE EJECUTO
input wire Begin_FSM_EX, //inicia la maquina de estados
input wire [4:0] CONT_ITER,//LLEVA LA CUENTA DE LA ITERACIONES
//OUTPUT SIGNALS
output reg RST, //REALIZA EL RESET DE LOS REGISTROS
output reg MS_1, //SELECCION DEL MUX 1
output reg EN_REG3, //ENABLE PARA EL REGISTRO 3 CON EL VALOR DEL EXP = COSH + SIN H
//output reg EN_REGMult, //ENABLE REG MULT
output reg ADD_SUBT, //SELECCION DE OPERACION PARA EL ADD/SUBT FLOTANTE
output reg Begin_SUMX, //INICIA ADD/SUM FLOTANTE X
output reg Begin_SUMY, //INICIA ADD/SUM FLOTANTE Y
output reg Begin_SUMZ, //INICIA ADD/SUM FLOTANTE Z
output reg EN_REG1X, //ENABLE PARA LOS REGISTROS X,Y,Z DE LA PRIMERA ETAPA
output reg EN_REG1Y, //ENABLE PARA LOS REGISTROS X,Y,Z DE LA PRIMERA ETAPA
output reg EN_REG1Z, //ENABLE PARA LOS REGISTROS X,Y,Z DE LA PRIMERA ETAPA
output reg MS_2, //SELECCION DEL MUX 2
output reg EN_REG2, //ENABLE PARA EL REGISTRO CON LOS VALORES DESPLAZADOS DE LA SEGUNDA ETAPA
output reg CLK_CDIR, //CLK PARA EL CONTADOR DE ITERACIONES
output reg EN_REG2XYZ, //ENABLE PARA EL VALOR ANTERIOR DE XYZ DE SEGUNDA ETAPA
output reg ACK_EX, //ACK PARA SABER SI LA OPERACION EX YA SE REALIZO
//registros de selectores
output reg EN_ADDSUBT,
output reg EN_MS1,
output reg EN_MS2
);
parameter [5:0]
//se definen los estados que se utilizaran en la maquina
a = 6'd0,
b = 6'd1,
c = 6'd2,
d = 6'd3,
e = 6'd4,
f = 6'd5,
g = 6'd6,
h = 6'd7,
i = 6'd8,
j = 6'd9,
k = 6'd10,
l = 6'd11,
m = 6'd12,
n = 6'd13,
o = 6'd14,
p = 6'd15,
q = 6'd16,
r = 6'd17,
s = 6'd18,
t = 6'd19;
reg [5:0] state_reg, state_next ; //state registers declaration
////
always @(posedge CLK, posedge RST_EX)
if (RST_EX) begin
state_reg <= a;
end
else begin
state_reg <= state_next;
end
//assign State = state_reg;
///
always @*
begin
state_next = state_reg;
EN_REG2 = 0;
EN_REG3 = 0;
//EN_REGMult = 0;
EN_REG1X = 0;
EN_REG1Y = 0;
EN_REG1Z = 0;
EN_REG2XYZ = 0;
Begin_SUMX = 0;
Begin_SUMY = 0;
Begin_SUMZ = 0;
ACK_EX = 0;
CLK_CDIR = 0;
RST = 0;
MS_1 = 0;
MS_2 = 0;
ADD_SUBT = 0;
EN_ADDSUBT = 0;
EN_MS1 = 0;
EN_MS2 = 0;
//nuevos estados
case(state_reg)
a:
begin
if(Begin_FSM_EX)
begin
RST = 1;
state_next = b;
end
else
state_next = a;
end
b:
begin
ADD_SUBT = 0;
EN_ADDSUBT = 1;
MS_1 = 1;
EN_MS1 = 1;
MS_2 = 1;
EN_MS2 = 1;
state_next = c;
end
c:
begin
EN_REG1X = 1;
EN_REG1Y = 1;
EN_REG1Z = 1;
MS_1 = 0;
EN_MS1= 1;
state_next = d;
end
d:
begin
state_next = e;
end
e:
begin
EN_REG2 = 1;
EN_REG2XYZ = 1;
state_next = f;
end
f:
begin
Begin_SUMX = 1;
Begin_SUMY = 1;
CLK_CDIR = 1;
state_next = g;
end
g:
begin
state_next = h;
end
h:
begin
Begin_SUMZ = 1;
if(ACK_ADD_SUBTX & ACK_ADD_SUBTY)
begin
EN_REG1X = 1;
EN_REG1Y = 1;
state_next = i;
end
else
state_next = h;
end
i:
begin
if(ACK_ADD_SUBTZ)
begin
EN_REG1Z = 1;
state_next = j;
end
else
state_next = i;
end
j:
begin
if(CONT_ITER == 5'b10001)//if(CONT_ITER == 5'b01111 ) //15 iteraciones
begin
MS_2 = 0;
EN_MS2 = 1;
ADD_SUBT = 0;
EN_ADDSUBT = 1;
state_next = k;
end
else
state_next = d;
end
k:
begin
Begin_SUMZ = 1;
state_next = l;
end
l:
begin
if(ACK_ADD_SUBTZ)
begin
EN_REG3 = 1;
state_next = m;
end
else
state_next = l;
end
m:
begin
ACK_EX = 1;
if(RST_EX)
begin
RST = 1;
state_next = a;
end
end
endcase
end
endmodule |
module system_nfa_accept_samples_generic_hw_top_5_wrapper
(
aclk,
aresetn,
indices_MPLB_Clk,
indices_MPLB_Rst,
indices_M_request,
indices_M_priority,
indices_M_busLock,
indices_M_RNW,
indices_M_BE,
indices_M_MSize,
indices_M_size,
indices_M_type,
indices_M_TAttribute,
indices_M_lockErr,
indices_M_abort,
indices_M_UABus,
indices_M_ABus,
indices_M_wrDBus,
indices_M_wrBurst,
indices_M_rdBurst,
indices_PLB_MAddrAck,
indices_PLB_MSSize,
indices_PLB_MRearbitrate,
indices_PLB_MTimeout,
indices_PLB_MBusy,
indices_PLB_MRdErr,
indices_PLB_MWrErr,
indices_PLB_MIRQ,
indices_PLB_MRdDBus,
indices_PLB_MRdWdAddr,
indices_PLB_MRdDAck,
indices_PLB_MRdBTerm,
indices_PLB_MWrDAck,
indices_PLB_MWrBTerm,
nfa_finals_buckets_MPLB_Clk,
nfa_finals_buckets_MPLB_Rst,
nfa_finals_buckets_M_request,
nfa_finals_buckets_M_priority,
nfa_finals_buckets_M_busLock,
nfa_finals_buckets_M_RNW,
nfa_finals_buckets_M_BE,
nfa_finals_buckets_M_MSize,
nfa_finals_buckets_M_size,
nfa_finals_buckets_M_type,
nfa_finals_buckets_M_TAttribute,
nfa_finals_buckets_M_lockErr,
nfa_finals_buckets_M_abort,
nfa_finals_buckets_M_UABus,
nfa_finals_buckets_M_ABus,
nfa_finals_buckets_M_wrDBus,
nfa_finals_buckets_M_wrBurst,
nfa_finals_buckets_M_rdBurst,
nfa_finals_buckets_PLB_MAddrAck,
nfa_finals_buckets_PLB_MSSize,
nfa_finals_buckets_PLB_MRearbitrate,
nfa_finals_buckets_PLB_MTimeout,
nfa_finals_buckets_PLB_MBusy,
nfa_finals_buckets_PLB_MRdErr,
nfa_finals_buckets_PLB_MWrErr,
nfa_finals_buckets_PLB_MIRQ,
nfa_finals_buckets_PLB_MRdDBus,
nfa_finals_buckets_PLB_MRdWdAddr,
nfa_finals_buckets_PLB_MRdDAck,
nfa_finals_buckets_PLB_MRdBTerm,
nfa_finals_buckets_PLB_MWrDAck,
nfa_finals_buckets_PLB_MWrBTerm,
nfa_forward_buckets_MPLB_Clk,
nfa_forward_buckets_MPLB_Rst,
nfa_forward_buckets_M_request,
nfa_forward_buckets_M_priority,
nfa_forward_buckets_M_busLock,
nfa_forward_buckets_M_RNW,
nfa_forward_buckets_M_BE,
nfa_forward_buckets_M_MSize,
nfa_forward_buckets_M_size,
nfa_forward_buckets_M_type,
nfa_forward_buckets_M_TAttribute,
nfa_forward_buckets_M_lockErr,
nfa_forward_buckets_M_abort,
nfa_forward_buckets_M_UABus,
nfa_forward_buckets_M_ABus,
nfa_forward_buckets_M_wrDBus,
nfa_forward_buckets_M_wrBurst,
nfa_forward_buckets_M_rdBurst,
nfa_forward_buckets_PLB_MAddrAck,
nfa_forward_buckets_PLB_MSSize,
nfa_forward_buckets_PLB_MRearbitrate,
nfa_forward_buckets_PLB_MTimeout,
nfa_forward_buckets_PLB_MBusy,
nfa_forward_buckets_PLB_MRdErr,
nfa_forward_buckets_PLB_MWrErr,
nfa_forward_buckets_PLB_MIRQ,
nfa_forward_buckets_PLB_MRdDBus,
nfa_forward_buckets_PLB_MRdWdAddr,
nfa_forward_buckets_PLB_MRdDAck,
nfa_forward_buckets_PLB_MRdBTerm,
nfa_forward_buckets_PLB_MWrDAck,
nfa_forward_buckets_PLB_MWrBTerm,
nfa_initials_buckets_MPLB_Clk,
nfa_initials_buckets_MPLB_Rst,
nfa_initials_buckets_M_request,
nfa_initials_buckets_M_priority,
nfa_initials_buckets_M_busLock,
nfa_initials_buckets_M_RNW,
nfa_initials_buckets_M_BE,
nfa_initials_buckets_M_MSize,
nfa_initials_buckets_M_size,
nfa_initials_buckets_M_type,
nfa_initials_buckets_M_TAttribute,
nfa_initials_buckets_M_lockErr,
nfa_initials_buckets_M_abort,
nfa_initials_buckets_M_UABus,
nfa_initials_buckets_M_ABus,
nfa_initials_buckets_M_wrDBus,
nfa_initials_buckets_M_wrBurst,
nfa_initials_buckets_M_rdBurst,
nfa_initials_buckets_PLB_MAddrAck,
nfa_initials_buckets_PLB_MSSize,
nfa_initials_buckets_PLB_MRearbitrate,
nfa_initials_buckets_PLB_MTimeout,
nfa_initials_buckets_PLB_MBusy,
nfa_initials_buckets_PLB_MRdErr,
nfa_initials_buckets_PLB_MWrErr,
nfa_initials_buckets_PLB_MIRQ,
nfa_initials_buckets_PLB_MRdDBus,
nfa_initials_buckets_PLB_MRdWdAddr,
nfa_initials_buckets_PLB_MRdDAck,
nfa_initials_buckets_PLB_MRdBTerm,
nfa_initials_buckets_PLB_MWrDAck,
nfa_initials_buckets_PLB_MWrBTerm,
sample_buffer_MPLB_Clk,
sample_buffer_MPLB_Rst,
sample_buffer_M_request,
sample_buffer_M_priority,
sample_buffer_M_busLock,
sample_buffer_M_RNW,
sample_buffer_M_BE,
sample_buffer_M_MSize,
sample_buffer_M_size,
sample_buffer_M_type,
sample_buffer_M_TAttribute,
sample_buffer_M_lockErr,
sample_buffer_M_abort,
sample_buffer_M_UABus,
sample_buffer_M_ABus,
sample_buffer_M_wrDBus,
sample_buffer_M_wrBurst,
sample_buffer_M_rdBurst,
sample_buffer_PLB_MAddrAck,
sample_buffer_PLB_MSSize,
sample_buffer_PLB_MRearbitrate,
sample_buffer_PLB_MTimeout,
sample_buffer_PLB_MBusy,
sample_buffer_PLB_MRdErr,
sample_buffer_PLB_MWrErr,
sample_buffer_PLB_MIRQ,
sample_buffer_PLB_MRdDBus,
sample_buffer_PLB_MRdWdAddr,
sample_buffer_PLB_MRdDAck,
sample_buffer_PLB_MRdBTerm,
sample_buffer_PLB_MWrDAck,
sample_buffer_PLB_MWrBTerm,
splb_slv0_SPLB_Clk,
splb_slv0_SPLB_Rst,
splb_slv0_PLB_ABus,
splb_slv0_PLB_UABus,
splb_slv0_PLB_PAValid,
splb_slv0_PLB_SAValid,
splb_slv0_PLB_rdPrim,
splb_slv0_PLB_wrPrim,
splb_slv0_PLB_masterID,
splb_slv0_PLB_abort,
splb_slv0_PLB_busLock,
splb_slv0_PLB_RNW,
splb_slv0_PLB_BE,
splb_slv0_PLB_MSize,
splb_slv0_PLB_size,
splb_slv0_PLB_type,
splb_slv0_PLB_lockErr,
splb_slv0_PLB_wrDBus,
splb_slv0_PLB_wrBurst,
splb_slv0_PLB_rdBurst,
splb_slv0_PLB_wrPendReq,
splb_slv0_PLB_rdPendReq,
splb_slv0_PLB_wrPendPri,
splb_slv0_PLB_rdPendPri,
splb_slv0_PLB_reqPri,
splb_slv0_PLB_TAttribute,
splb_slv0_Sl_addrAck,
splb_slv0_Sl_SSize,
splb_slv0_Sl_wait,
splb_slv0_Sl_rearbitrate,
splb_slv0_Sl_wrDAck,
splb_slv0_Sl_wrComp,
splb_slv0_Sl_wrBTerm,
splb_slv0_Sl_rdDBus,
splb_slv0_Sl_rdWdAddr,
splb_slv0_Sl_rdDAck,
splb_slv0_Sl_rdComp,
splb_slv0_Sl_rdBTerm,
splb_slv0_Sl_MBusy,
splb_slv0_Sl_MWrErr,
splb_slv0_Sl_MRdErr,
splb_slv0_Sl_MIRQ
);
input aclk;
input aresetn;
input indices_MPLB_Clk;
input indices_MPLB_Rst;
output indices_M_request;
output [0:1] indices_M_priority;
output indices_M_busLock;
output indices_M_RNW;
output [0:7] indices_M_BE;
output [0:1] indices_M_MSize;
output [0:3] indices_M_size;
output [0:2] indices_M_type;
output [0:15] indices_M_TAttribute;
output indices_M_lockErr;
output indices_M_abort;
output [0:31] indices_M_UABus;
output [0:31] indices_M_ABus;
output [0:63] indices_M_wrDBus;
output indices_M_wrBurst;
output indices_M_rdBurst;
input indices_PLB_MAddrAck;
input [0:1] indices_PLB_MSSize;
input indices_PLB_MRearbitrate;
input indices_PLB_MTimeout;
input indices_PLB_MBusy;
input indices_PLB_MRdErr;
input indices_PLB_MWrErr;
input indices_PLB_MIRQ;
input [0:63] indices_PLB_MRdDBus;
input [0:3] indices_PLB_MRdWdAddr;
input indices_PLB_MRdDAck;
input indices_PLB_MRdBTerm;
input indices_PLB_MWrDAck;
input indices_PLB_MWrBTerm;
input nfa_finals_buckets_MPLB_Clk;
input nfa_finals_buckets_MPLB_Rst;
output nfa_finals_buckets_M_request;
output [0:1] nfa_finals_buckets_M_priority;
output nfa_finals_buckets_M_busLock;
output nfa_finals_buckets_M_RNW;
output [0:7] nfa_finals_buckets_M_BE;
output [0:1] nfa_finals_buckets_M_MSize;
output [0:3] nfa_finals_buckets_M_size;
output [0:2] nfa_finals_buckets_M_type;
output [0:15] nfa_finals_buckets_M_TAttribute;
output nfa_finals_buckets_M_lockErr;
output nfa_finals_buckets_M_abort;
output [0:31] nfa_finals_buckets_M_UABus;
output [0:31] nfa_finals_buckets_M_ABus;
output [0:63] nfa_finals_buckets_M_wrDBus;
output nfa_finals_buckets_M_wrBurst;
output nfa_finals_buckets_M_rdBurst;
input nfa_finals_buckets_PLB_MAddrAck;
input [0:1] nfa_finals_buckets_PLB_MSSize;
input nfa_finals_buckets_PLB_MRearbitrate;
input nfa_finals_buckets_PLB_MTimeout;
input nfa_finals_buckets_PLB_MBusy;
input nfa_finals_buckets_PLB_MRdErr;
input nfa_finals_buckets_PLB_MWrErr;
input nfa_finals_buckets_PLB_MIRQ;
input [0:63] nfa_finals_buckets_PLB_MRdDBus;
input [0:3] nfa_finals_buckets_PLB_MRdWdAddr;
input nfa_finals_buckets_PLB_MRdDAck;
input nfa_finals_buckets_PLB_MRdBTerm;
input nfa_finals_buckets_PLB_MWrDAck;
input nfa_finals_buckets_PLB_MWrBTerm;
input nfa_forward_buckets_MPLB_Clk;
input nfa_forward_buckets_MPLB_Rst;
output nfa_forward_buckets_M_request;
output [0:1] nfa_forward_buckets_M_priority;
output nfa_forward_buckets_M_busLock;
output nfa_forward_buckets_M_RNW;
output [0:7] nfa_forward_buckets_M_BE;
output [0:1] nfa_forward_buckets_M_MSize;
output [0:3] nfa_forward_buckets_M_size;
output [0:2] nfa_forward_buckets_M_type;
output [0:15] nfa_forward_buckets_M_TAttribute;
output nfa_forward_buckets_M_lockErr;
output nfa_forward_buckets_M_abort;
output [0:31] nfa_forward_buckets_M_UABus;
output [0:31] nfa_forward_buckets_M_ABus;
output [0:63] nfa_forward_buckets_M_wrDBus;
output nfa_forward_buckets_M_wrBurst;
output nfa_forward_buckets_M_rdBurst;
input nfa_forward_buckets_PLB_MAddrAck;
input [0:1] nfa_forward_buckets_PLB_MSSize;
input nfa_forward_buckets_PLB_MRearbitrate;
input nfa_forward_buckets_PLB_MTimeout;
input nfa_forward_buckets_PLB_MBusy;
input nfa_forward_buckets_PLB_MRdErr;
input nfa_forward_buckets_PLB_MWrErr;
input nfa_forward_buckets_PLB_MIRQ;
input [0:63] nfa_forward_buckets_PLB_MRdDBus;
input [0:3] nfa_forward_buckets_PLB_MRdWdAddr;
input nfa_forward_buckets_PLB_MRdDAck;
input nfa_forward_buckets_PLB_MRdBTerm;
input nfa_forward_buckets_PLB_MWrDAck;
input nfa_forward_buckets_PLB_MWrBTerm;
input nfa_initials_buckets_MPLB_Clk;
input nfa_initials_buckets_MPLB_Rst;
output nfa_initials_buckets_M_request;
output [0:1] nfa_initials_buckets_M_priority;
output nfa_initials_buckets_M_busLock;
output nfa_initials_buckets_M_RNW;
output [0:7] nfa_initials_buckets_M_BE;
output [0:1] nfa_initials_buckets_M_MSize;
output [0:3] nfa_initials_buckets_M_size;
output [0:2] nfa_initials_buckets_M_type;
output [0:15] nfa_initials_buckets_M_TAttribute;
output nfa_initials_buckets_M_lockErr;
output nfa_initials_buckets_M_abort;
output [0:31] nfa_initials_buckets_M_UABus;
output [0:31] nfa_initials_buckets_M_ABus;
output [0:63] nfa_initials_buckets_M_wrDBus;
output nfa_initials_buckets_M_wrBurst;
output nfa_initials_buckets_M_rdBurst;
input nfa_initials_buckets_PLB_MAddrAck;
input [0:1] nfa_initials_buckets_PLB_MSSize;
input nfa_initials_buckets_PLB_MRearbitrate;
input nfa_initials_buckets_PLB_MTimeout;
input nfa_initials_buckets_PLB_MBusy;
input nfa_initials_buckets_PLB_MRdErr;
input nfa_initials_buckets_PLB_MWrErr;
input nfa_initials_buckets_PLB_MIRQ;
input [0:63] nfa_initials_buckets_PLB_MRdDBus;
input [0:3] nfa_initials_buckets_PLB_MRdWdAddr;
input nfa_initials_buckets_PLB_MRdDAck;
input nfa_initials_buckets_PLB_MRdBTerm;
input nfa_initials_buckets_PLB_MWrDAck;
input nfa_initials_buckets_PLB_MWrBTerm;
input sample_buffer_MPLB_Clk;
input sample_buffer_MPLB_Rst;
output sample_buffer_M_request;
output [0:1] sample_buffer_M_priority;
output sample_buffer_M_busLock;
output sample_buffer_M_RNW;
output [0:7] sample_buffer_M_BE;
output [0:1] sample_buffer_M_MSize;
output [0:3] sample_buffer_M_size;
output [0:2] sample_buffer_M_type;
output [0:15] sample_buffer_M_TAttribute;
output sample_buffer_M_lockErr;
output sample_buffer_M_abort;
output [0:31] sample_buffer_M_UABus;
output [0:31] sample_buffer_M_ABus;
output [0:63] sample_buffer_M_wrDBus;
output sample_buffer_M_wrBurst;
output sample_buffer_M_rdBurst;
input sample_buffer_PLB_MAddrAck;
input [0:1] sample_buffer_PLB_MSSize;
input sample_buffer_PLB_MRearbitrate;
input sample_buffer_PLB_MTimeout;
input sample_buffer_PLB_MBusy;
input sample_buffer_PLB_MRdErr;
input sample_buffer_PLB_MWrErr;
input sample_buffer_PLB_MIRQ;
input [0:63] sample_buffer_PLB_MRdDBus;
input [0:3] sample_buffer_PLB_MRdWdAddr;
input sample_buffer_PLB_MRdDAck;
input sample_buffer_PLB_MRdBTerm;
input sample_buffer_PLB_MWrDAck;
input sample_buffer_PLB_MWrBTerm;
input splb_slv0_SPLB_Clk;
input splb_slv0_SPLB_Rst;
input [0:31] splb_slv0_PLB_ABus;
input [0:31] splb_slv0_PLB_UABus;
input splb_slv0_PLB_PAValid;
input splb_slv0_PLB_SAValid;
input splb_slv0_PLB_rdPrim;
input splb_slv0_PLB_wrPrim;
input [0:2] splb_slv0_PLB_masterID;
input splb_slv0_PLB_abort;
input splb_slv0_PLB_busLock;
input splb_slv0_PLB_RNW;
input [0:7] splb_slv0_PLB_BE;
input [0:1] splb_slv0_PLB_MSize;
input [0:3] splb_slv0_PLB_size;
input [0:2] splb_slv0_PLB_type;
input splb_slv0_PLB_lockErr;
input [0:63] splb_slv0_PLB_wrDBus;
input splb_slv0_PLB_wrBurst;
input splb_slv0_PLB_rdBurst;
input splb_slv0_PLB_wrPendReq;
input splb_slv0_PLB_rdPendReq;
input [0:1] splb_slv0_PLB_wrPendPri;
input [0:1] splb_slv0_PLB_rdPendPri;
input [0:1] splb_slv0_PLB_reqPri;
input [0:15] splb_slv0_PLB_TAttribute;
output splb_slv0_Sl_addrAck;
output [0:1] splb_slv0_Sl_SSize;
output splb_slv0_Sl_wait;
output splb_slv0_Sl_rearbitrate;
output splb_slv0_Sl_wrDAck;
output splb_slv0_Sl_wrComp;
output splb_slv0_Sl_wrBTerm;
output [0:63] splb_slv0_Sl_rdDBus;
output [0:3] splb_slv0_Sl_rdWdAddr;
output splb_slv0_Sl_rdDAck;
output splb_slv0_Sl_rdComp;
output splb_slv0_Sl_rdBTerm;
output [0:5] splb_slv0_Sl_MBusy;
output [0:5] splb_slv0_Sl_MWrErr;
output [0:5] splb_slv0_Sl_MRdErr;
output [0:5] splb_slv0_Sl_MIRQ;
nfa_accept_samples_generic_hw_top
#(
.RESET_ACTIVE_LOW ( 1 ),
.C_indices_REMOTE_DESTINATION_ADDRESS ( 32'h00000000 ),
.C_indices_AWIDTH ( 32 ),
.C_indices_DWIDTH ( 64 ),
.C_indices_NATIVE_DWIDTH ( 64 ),
.C_nfa_finals_buckets_REMOTE_DESTINATION_ADDRESS ( 32'h00000000 ),
.C_nfa_finals_buckets_AWIDTH ( 32 ),
.C_nfa_finals_buckets_DWIDTH ( 64 ),
.C_nfa_finals_buckets_NATIVE_DWIDTH ( 64 ),
.C_nfa_forward_buckets_REMOTE_DESTINATION_ADDRESS ( 32'h00000000 ),
.C_nfa_forward_buckets_AWIDTH ( 32 ),
.C_nfa_forward_buckets_DWIDTH ( 64 ),
.C_nfa_forward_buckets_NATIVE_DWIDTH ( 64 ),
.C_nfa_initials_buckets_REMOTE_DESTINATION_ADDRESS ( 32'h00000000 ),
.C_nfa_initials_buckets_AWIDTH ( 32 ),
.C_nfa_initials_buckets_DWIDTH ( 64 ),
.C_nfa_initials_buckets_NATIVE_DWIDTH ( 64 ),
.C_sample_buffer_REMOTE_DESTINATION_ADDRESS ( 32'h00000000 ),
.C_sample_buffer_AWIDTH ( 32 ),
.C_sample_buffer_DWIDTH ( 64 ),
.C_sample_buffer_NATIVE_DWIDTH ( 64 ),
.C_SPLB_SLV0_BASEADDR ( 32'hD5000000 ),
.C_SPLB_SLV0_HIGHADDR ( 32'hD50000FF ),
.C_SPLB_SLV0_AWIDTH ( 32 ),
.C_SPLB_SLV0_DWIDTH ( 64 ),
.C_SPLB_SLV0_NUM_MASTERS ( 6 ),
.C_SPLB_SLV0_MID_WIDTH ( 3 ),
.C_SPLB_SLV0_NATIVE_DWIDTH ( 32 ),
.C_SPLB_SLV0_P2P ( 0 ),
.C_SPLB_SLV0_SUPPORT_BURSTS ( 0 ),
.C_SPLB_SLV0_SMALLEST_MASTER ( 32 ),
.C_SPLB_SLV0_INCLUDE_DPHASE_TIMER ( 0 )
)
nfa_accept_samples_generic_hw_top_5 (
.aclk ( aclk ),
.aresetn ( aresetn ),
.indices_MPLB_Clk ( indices_MPLB_Clk ),
.indices_MPLB_Rst ( indices_MPLB_Rst ),
.indices_M_request ( indices_M_request ),
.indices_M_priority ( indices_M_priority ),
.indices_M_busLock ( indices_M_busLock ),
.indices_M_RNW ( indices_M_RNW ),
.indices_M_BE ( indices_M_BE ),
.indices_M_MSize ( indices_M_MSize ),
.indices_M_size ( indices_M_size ),
.indices_M_type ( indices_M_type ),
.indices_M_TAttribute ( indices_M_TAttribute ),
.indices_M_lockErr ( indices_M_lockErr ),
.indices_M_abort ( indices_M_abort ),
.indices_M_UABus ( indices_M_UABus ),
.indices_M_ABus ( indices_M_ABus ),
.indices_M_wrDBus ( indices_M_wrDBus ),
.indices_M_wrBurst ( indices_M_wrBurst ),
.indices_M_rdBurst ( indices_M_rdBurst ),
.indices_PLB_MAddrAck ( indices_PLB_MAddrAck ),
.indices_PLB_MSSize ( indices_PLB_MSSize ),
.indices_PLB_MRearbitrate ( indices_PLB_MRearbitrate ),
.indices_PLB_MTimeout ( indices_PLB_MTimeout ),
.indices_PLB_MBusy ( indices_PLB_MBusy ),
.indices_PLB_MRdErr ( indices_PLB_MRdErr ),
.indices_PLB_MWrErr ( indices_PLB_MWrErr ),
.indices_PLB_MIRQ ( indices_PLB_MIRQ ),
.indices_PLB_MRdDBus ( indices_PLB_MRdDBus ),
.indices_PLB_MRdWdAddr ( indices_PLB_MRdWdAddr ),
.indices_PLB_MRdDAck ( indices_PLB_MRdDAck ),
.indices_PLB_MRdBTerm ( indices_PLB_MRdBTerm ),
.indices_PLB_MWrDAck ( indices_PLB_MWrDAck ),
.indices_PLB_MWrBTerm ( indices_PLB_MWrBTerm ),
.nfa_finals_buckets_MPLB_Clk ( nfa_finals_buckets_MPLB_Clk ),
.nfa_finals_buckets_MPLB_Rst ( nfa_finals_buckets_MPLB_Rst ),
.nfa_finals_buckets_M_request ( nfa_finals_buckets_M_request ),
.nfa_finals_buckets_M_priority ( nfa_finals_buckets_M_priority ),
.nfa_finals_buckets_M_busLock ( nfa_finals_buckets_M_busLock ),
.nfa_finals_buckets_M_RNW ( nfa_finals_buckets_M_RNW ),
.nfa_finals_buckets_M_BE ( nfa_finals_buckets_M_BE ),
.nfa_finals_buckets_M_MSize ( nfa_finals_buckets_M_MSize ),
.nfa_finals_buckets_M_size ( nfa_finals_buckets_M_size ),
.nfa_finals_buckets_M_type ( nfa_finals_buckets_M_type ),
.nfa_finals_buckets_M_TAttribute ( nfa_finals_buckets_M_TAttribute ),
.nfa_finals_buckets_M_lockErr ( nfa_finals_buckets_M_lockErr ),
.nfa_finals_buckets_M_abort ( nfa_finals_buckets_M_abort ),
.nfa_finals_buckets_M_UABus ( nfa_finals_buckets_M_UABus ),
.nfa_finals_buckets_M_ABus ( nfa_finals_buckets_M_ABus ),
.nfa_finals_buckets_M_wrDBus ( nfa_finals_buckets_M_wrDBus ),
.nfa_finals_buckets_M_wrBurst ( nfa_finals_buckets_M_wrBurst ),
.nfa_finals_buckets_M_rdBurst ( nfa_finals_buckets_M_rdBurst ),
.nfa_finals_buckets_PLB_MAddrAck ( nfa_finals_buckets_PLB_MAddrAck ),
.nfa_finals_buckets_PLB_MSSize ( nfa_finals_buckets_PLB_MSSize ),
.nfa_finals_buckets_PLB_MRearbitrate ( nfa_finals_buckets_PLB_MRearbitrate ),
.nfa_finals_buckets_PLB_MTimeout ( nfa_finals_buckets_PLB_MTimeout ),
.nfa_finals_buckets_PLB_MBusy ( nfa_finals_buckets_PLB_MBusy ),
.nfa_finals_buckets_PLB_MRdErr ( nfa_finals_buckets_PLB_MRdErr ),
.nfa_finals_buckets_PLB_MWrErr ( nfa_finals_buckets_PLB_MWrErr ),
.nfa_finals_buckets_PLB_MIRQ ( nfa_finals_buckets_PLB_MIRQ ),
.nfa_finals_buckets_PLB_MRdDBus ( nfa_finals_buckets_PLB_MRdDBus ),
.nfa_finals_buckets_PLB_MRdWdAddr ( nfa_finals_buckets_PLB_MRdWdAddr ),
.nfa_finals_buckets_PLB_MRdDAck ( nfa_finals_buckets_PLB_MRdDAck ),
.nfa_finals_buckets_PLB_MRdBTerm ( nfa_finals_buckets_PLB_MRdBTerm ),
.nfa_finals_buckets_PLB_MWrDAck ( nfa_finals_buckets_PLB_MWrDAck ),
.nfa_finals_buckets_PLB_MWrBTerm ( nfa_finals_buckets_PLB_MWrBTerm ),
.nfa_forward_buckets_MPLB_Clk ( nfa_forward_buckets_MPLB_Clk ),
.nfa_forward_buckets_MPLB_Rst ( nfa_forward_buckets_MPLB_Rst ),
.nfa_forward_buckets_M_request ( nfa_forward_buckets_M_request ),
.nfa_forward_buckets_M_priority ( nfa_forward_buckets_M_priority ),
.nfa_forward_buckets_M_busLock ( nfa_forward_buckets_M_busLock ),
.nfa_forward_buckets_M_RNW ( nfa_forward_buckets_M_RNW ),
.nfa_forward_buckets_M_BE ( nfa_forward_buckets_M_BE ),
.nfa_forward_buckets_M_MSize ( nfa_forward_buckets_M_MSize ),
.nfa_forward_buckets_M_size ( nfa_forward_buckets_M_size ),
.nfa_forward_buckets_M_type ( nfa_forward_buckets_M_type ),
.nfa_forward_buckets_M_TAttribute ( nfa_forward_buckets_M_TAttribute ),
.nfa_forward_buckets_M_lockErr ( nfa_forward_buckets_M_lockErr ),
.nfa_forward_buckets_M_abort ( nfa_forward_buckets_M_abort ),
.nfa_forward_buckets_M_UABus ( nfa_forward_buckets_M_UABus ),
.nfa_forward_buckets_M_ABus ( nfa_forward_buckets_M_ABus ),
.nfa_forward_buckets_M_wrDBus ( nfa_forward_buckets_M_wrDBus ),
.nfa_forward_buckets_M_wrBurst ( nfa_forward_buckets_M_wrBurst ),
.nfa_forward_buckets_M_rdBurst ( nfa_forward_buckets_M_rdBurst ),
.nfa_forward_buckets_PLB_MAddrAck ( nfa_forward_buckets_PLB_MAddrAck ),
.nfa_forward_buckets_PLB_MSSize ( nfa_forward_buckets_PLB_MSSize ),
.nfa_forward_buckets_PLB_MRearbitrate ( nfa_forward_buckets_PLB_MRearbitrate ),
.nfa_forward_buckets_PLB_MTimeout ( nfa_forward_buckets_PLB_MTimeout ),
.nfa_forward_buckets_PLB_MBusy ( nfa_forward_buckets_PLB_MBusy ),
.nfa_forward_buckets_PLB_MRdErr ( nfa_forward_buckets_PLB_MRdErr ),
.nfa_forward_buckets_PLB_MWrErr ( nfa_forward_buckets_PLB_MWrErr ),
.nfa_forward_buckets_PLB_MIRQ ( nfa_forward_buckets_PLB_MIRQ ),
.nfa_forward_buckets_PLB_MRdDBus ( nfa_forward_buckets_PLB_MRdDBus ),
.nfa_forward_buckets_PLB_MRdWdAddr ( nfa_forward_buckets_PLB_MRdWdAddr ),
.nfa_forward_buckets_PLB_MRdDAck ( nfa_forward_buckets_PLB_MRdDAck ),
.nfa_forward_buckets_PLB_MRdBTerm ( nfa_forward_buckets_PLB_MRdBTerm ),
.nfa_forward_buckets_PLB_MWrDAck ( nfa_forward_buckets_PLB_MWrDAck ),
.nfa_forward_buckets_PLB_MWrBTerm ( nfa_forward_buckets_PLB_MWrBTerm ),
.nfa_initials_buckets_MPLB_Clk ( nfa_initials_buckets_MPLB_Clk ),
.nfa_initials_buckets_MPLB_Rst ( nfa_initials_buckets_MPLB_Rst ),
.nfa_initials_buckets_M_request ( nfa_initials_buckets_M_request ),
.nfa_initials_buckets_M_priority ( nfa_initials_buckets_M_priority ),
.nfa_initials_buckets_M_busLock ( nfa_initials_buckets_M_busLock ),
.nfa_initials_buckets_M_RNW ( nfa_initials_buckets_M_RNW ),
.nfa_initials_buckets_M_BE ( nfa_initials_buckets_M_BE ),
.nfa_initials_buckets_M_MSize ( nfa_initials_buckets_M_MSize ),
.nfa_initials_buckets_M_size ( nfa_initials_buckets_M_size ),
.nfa_initials_buckets_M_type ( nfa_initials_buckets_M_type ),
.nfa_initials_buckets_M_TAttribute ( nfa_initials_buckets_M_TAttribute ),
.nfa_initials_buckets_M_lockErr ( nfa_initials_buckets_M_lockErr ),
.nfa_initials_buckets_M_abort ( nfa_initials_buckets_M_abort ),
.nfa_initials_buckets_M_UABus ( nfa_initials_buckets_M_UABus ),
.nfa_initials_buckets_M_ABus ( nfa_initials_buckets_M_ABus ),
.nfa_initials_buckets_M_wrDBus ( nfa_initials_buckets_M_wrDBus ),
.nfa_initials_buckets_M_wrBurst ( nfa_initials_buckets_M_wrBurst ),
.nfa_initials_buckets_M_rdBurst ( nfa_initials_buckets_M_rdBurst ),
.nfa_initials_buckets_PLB_MAddrAck ( nfa_initials_buckets_PLB_MAddrAck ),
.nfa_initials_buckets_PLB_MSSize ( nfa_initials_buckets_PLB_MSSize ),
.nfa_initials_buckets_PLB_MRearbitrate ( nfa_initials_buckets_PLB_MRearbitrate ),
.nfa_initials_buckets_PLB_MTimeout ( nfa_initials_buckets_PLB_MTimeout ),
.nfa_initials_buckets_PLB_MBusy ( nfa_initials_buckets_PLB_MBusy ),
.nfa_initials_buckets_PLB_MRdErr ( nfa_initials_buckets_PLB_MRdErr ),
.nfa_initials_buckets_PLB_MWrErr ( nfa_initials_buckets_PLB_MWrErr ),
.nfa_initials_buckets_PLB_MIRQ ( nfa_initials_buckets_PLB_MIRQ ),
.nfa_initials_buckets_PLB_MRdDBus ( nfa_initials_buckets_PLB_MRdDBus ),
.nfa_initials_buckets_PLB_MRdWdAddr ( nfa_initials_buckets_PLB_MRdWdAddr ),
.nfa_initials_buckets_PLB_MRdDAck ( nfa_initials_buckets_PLB_MRdDAck ),
.nfa_initials_buckets_PLB_MRdBTerm ( nfa_initials_buckets_PLB_MRdBTerm ),
.nfa_initials_buckets_PLB_MWrDAck ( nfa_initials_buckets_PLB_MWrDAck ),
.nfa_initials_buckets_PLB_MWrBTerm ( nfa_initials_buckets_PLB_MWrBTerm ),
.sample_buffer_MPLB_Clk ( sample_buffer_MPLB_Clk ),
.sample_buffer_MPLB_Rst ( sample_buffer_MPLB_Rst ),
.sample_buffer_M_request ( sample_buffer_M_request ),
.sample_buffer_M_priority ( sample_buffer_M_priority ),
.sample_buffer_M_busLock ( sample_buffer_M_busLock ),
.sample_buffer_M_RNW ( sample_buffer_M_RNW ),
.sample_buffer_M_BE ( sample_buffer_M_BE ),
.sample_buffer_M_MSize ( sample_buffer_M_MSize ),
.sample_buffer_M_size ( sample_buffer_M_size ),
.sample_buffer_M_type ( sample_buffer_M_type ),
.sample_buffer_M_TAttribute ( sample_buffer_M_TAttribute ),
.sample_buffer_M_lockErr ( sample_buffer_M_lockErr ),
.sample_buffer_M_abort ( sample_buffer_M_abort ),
.sample_buffer_M_UABus ( sample_buffer_M_UABus ),
.sample_buffer_M_ABus ( sample_buffer_M_ABus ),
.sample_buffer_M_wrDBus ( sample_buffer_M_wrDBus ),
.sample_buffer_M_wrBurst ( sample_buffer_M_wrBurst ),
.sample_buffer_M_rdBurst ( sample_buffer_M_rdBurst ),
.sample_buffer_PLB_MAddrAck ( sample_buffer_PLB_MAddrAck ),
.sample_buffer_PLB_MSSize ( sample_buffer_PLB_MSSize ),
.sample_buffer_PLB_MRearbitrate ( sample_buffer_PLB_MRearbitrate ),
.sample_buffer_PLB_MTimeout ( sample_buffer_PLB_MTimeout ),
.sample_buffer_PLB_MBusy ( sample_buffer_PLB_MBusy ),
.sample_buffer_PLB_MRdErr ( sample_buffer_PLB_MRdErr ),
.sample_buffer_PLB_MWrErr ( sample_buffer_PLB_MWrErr ),
.sample_buffer_PLB_MIRQ ( sample_buffer_PLB_MIRQ ),
.sample_buffer_PLB_MRdDBus ( sample_buffer_PLB_MRdDBus ),
.sample_buffer_PLB_MRdWdAddr ( sample_buffer_PLB_MRdWdAddr ),
.sample_buffer_PLB_MRdDAck ( sample_buffer_PLB_MRdDAck ),
.sample_buffer_PLB_MRdBTerm ( sample_buffer_PLB_MRdBTerm ),
.sample_buffer_PLB_MWrDAck ( sample_buffer_PLB_MWrDAck ),
.sample_buffer_PLB_MWrBTerm ( sample_buffer_PLB_MWrBTerm ),
.splb_slv0_SPLB_Clk ( splb_slv0_SPLB_Clk ),
.splb_slv0_SPLB_Rst ( splb_slv0_SPLB_Rst ),
.splb_slv0_PLB_ABus ( splb_slv0_PLB_ABus ),
.splb_slv0_PLB_UABus ( splb_slv0_PLB_UABus ),
.splb_slv0_PLB_PAValid ( splb_slv0_PLB_PAValid ),
.splb_slv0_PLB_SAValid ( splb_slv0_PLB_SAValid ),
.splb_slv0_PLB_rdPrim ( splb_slv0_PLB_rdPrim ),
.splb_slv0_PLB_wrPrim ( splb_slv0_PLB_wrPrim ),
.splb_slv0_PLB_masterID ( splb_slv0_PLB_masterID ),
.splb_slv0_PLB_abort ( splb_slv0_PLB_abort ),
.splb_slv0_PLB_busLock ( splb_slv0_PLB_busLock ),
.splb_slv0_PLB_RNW ( splb_slv0_PLB_RNW ),
.splb_slv0_PLB_BE ( splb_slv0_PLB_BE ),
.splb_slv0_PLB_MSize ( splb_slv0_PLB_MSize ),
.splb_slv0_PLB_size ( splb_slv0_PLB_size ),
.splb_slv0_PLB_type ( splb_slv0_PLB_type ),
.splb_slv0_PLB_lockErr ( splb_slv0_PLB_lockErr ),
.splb_slv0_PLB_wrDBus ( splb_slv0_PLB_wrDBus ),
.splb_slv0_PLB_wrBurst ( splb_slv0_PLB_wrBurst ),
.splb_slv0_PLB_rdBurst ( splb_slv0_PLB_rdBurst ),
.splb_slv0_PLB_wrPendReq ( splb_slv0_PLB_wrPendReq ),
.splb_slv0_PLB_rdPendReq ( splb_slv0_PLB_rdPendReq ),
.splb_slv0_PLB_wrPendPri ( splb_slv0_PLB_wrPendPri ),
.splb_slv0_PLB_rdPendPri ( splb_slv0_PLB_rdPendPri ),
.splb_slv0_PLB_reqPri ( splb_slv0_PLB_reqPri ),
.splb_slv0_PLB_TAttribute ( splb_slv0_PLB_TAttribute ),
.splb_slv0_Sl_addrAck ( splb_slv0_Sl_addrAck ),
.splb_slv0_Sl_SSize ( splb_slv0_Sl_SSize ),
.splb_slv0_Sl_wait ( splb_slv0_Sl_wait ),
.splb_slv0_Sl_rearbitrate ( splb_slv0_Sl_rearbitrate ),
.splb_slv0_Sl_wrDAck ( splb_slv0_Sl_wrDAck ),
.splb_slv0_Sl_wrComp ( splb_slv0_Sl_wrComp ),
.splb_slv0_Sl_wrBTerm ( splb_slv0_Sl_wrBTerm ),
.splb_slv0_Sl_rdDBus ( splb_slv0_Sl_rdDBus ),
.splb_slv0_Sl_rdWdAddr ( splb_slv0_Sl_rdWdAddr ),
.splb_slv0_Sl_rdDAck ( splb_slv0_Sl_rdDAck ),
.splb_slv0_Sl_rdComp ( splb_slv0_Sl_rdComp ),
.splb_slv0_Sl_rdBTerm ( splb_slv0_Sl_rdBTerm ),
.splb_slv0_Sl_MBusy ( splb_slv0_Sl_MBusy ),
.splb_slv0_Sl_MWrErr ( splb_slv0_Sl_MWrErr ),
.splb_slv0_Sl_MRdErr ( splb_slv0_Sl_MRdErr ),
.splb_slv0_Sl_MIRQ ( splb_slv0_Sl_MIRQ )
);
endmodule |
module sky130_fd_sc_hs__sdfxbp (
//# {{data|Data Signals}}
input D ,
output Q ,
output Q_N,
//# {{scanchain|Scan Chain}}
input SCD,
input SCE,
//# {{clocks|Clocking}}
input CLK
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule |
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(aclk, aresetn, s_axi_awid, s_axi_awaddr,
s_axi_awlen, s_axi_awsize, s_axi_awburst, s_axi_awlock, s_axi_awcache, s_axi_awprot,
s_axi_awqos, s_axi_awvalid, s_axi_awready, s_axi_wdata, s_axi_wstrb, s_axi_wlast,
s_axi_wvalid, s_axi_wready, s_axi_bid, s_axi_bresp, s_axi_bvalid, s_axi_bready, s_axi_arid,
s_axi_araddr, s_axi_arlen, s_axi_arsize, s_axi_arburst, s_axi_arlock, s_axi_arcache,
s_axi_arprot, s_axi_arqos, s_axi_arvalid, s_axi_arready, s_axi_rid, s_axi_rdata, s_axi_rresp,
s_axi_rlast, s_axi_rvalid, s_axi_rready, m_axi_awaddr, m_axi_awlen, m_axi_awsize,
m_axi_awburst, m_axi_awlock, m_axi_awcache, m_axi_awprot, m_axi_awregion, m_axi_awqos,
m_axi_awvalid, m_axi_awready, m_axi_wdata, m_axi_wstrb, m_axi_wlast, m_axi_wvalid,
m_axi_wready, m_axi_bresp, m_axi_bvalid, m_axi_bready, m_axi_araddr, m_axi_arlen,
m_axi_arsize, m_axi_arburst, m_axi_arlock, m_axi_arcache, m_axi_arprot, m_axi_arregion,
m_axi_arqos, m_axi_arvalid, m_axi_arready, m_axi_rdata, m_axi_rresp, m_axi_rlast,
m_axi_rvalid, m_axi_rready)
/* synthesis syn_black_box black_box_pad_pin="aclk,aresetn,s_axi_awid[11:0],s_axi_awaddr[31:0],s_axi_awlen[7:0],s_axi_awsize[2:0],s_axi_awburst[1:0],s_axi_awlock[0:0],s_axi_awcache[3:0],s_axi_awprot[2:0],s_axi_awqos[3:0],s_axi_awvalid[0:0],s_axi_awready[0:0],s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wlast[0:0],s_axi_wvalid[0:0],s_axi_wready[0:0],s_axi_bid[11:0],s_axi_bresp[1:0],s_axi_bvalid[0:0],s_axi_bready[0:0],s_axi_arid[11:0],s_axi_araddr[31:0],s_axi_arlen[7:0],s_axi_arsize[2:0],s_axi_arburst[1:0],s_axi_arlock[0:0],s_axi_arcache[3:0],s_axi_arprot[2:0],s_axi_arqos[3:0],s_axi_arvalid[0:0],s_axi_arready[0:0],s_axi_rid[11:0],s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rlast[0:0],s_axi_rvalid[0:0],s_axi_rready[0:0],m_axi_awaddr[127:0],m_axi_awlen[31:0],m_axi_awsize[11:0],m_axi_awburst[7:0],m_axi_awlock[3:0],m_axi_awcache[15:0],m_axi_awprot[11:0],m_axi_awregion[15:0],m_axi_awqos[15:0],m_axi_awvalid[3:0],m_axi_awready[3:0],m_axi_wdata[127:0],m_axi_wstrb[15:0],m_axi_wlast[3:0],m_axi_wvalid[3:0],m_axi_wready[3:0],m_axi_bresp[7:0],m_axi_bvalid[3:0],m_axi_bready[3:0],m_axi_araddr[127:0],m_axi_arlen[31:0],m_axi_arsize[11:0],m_axi_arburst[7:0],m_axi_arlock[3:0],m_axi_arcache[15:0],m_axi_arprot[11:0],m_axi_arregion[15:0],m_axi_arqos[15:0],m_axi_arvalid[3:0],m_axi_arready[3:0],m_axi_rdata[127:0],m_axi_rresp[7:0],m_axi_rlast[3:0],m_axi_rvalid[3:0],m_axi_rready[3:0]" */;
input aclk;
input aresetn;
input [11:0]s_axi_awid;
input [31:0]s_axi_awaddr;
input [7:0]s_axi_awlen;
input [2:0]s_axi_awsize;
input [1:0]s_axi_awburst;
input [0:0]s_axi_awlock;
input [3:0]s_axi_awcache;
input [2:0]s_axi_awprot;
input [3:0]s_axi_awqos;
input [0:0]s_axi_awvalid;
output [0:0]s_axi_awready;
input [31:0]s_axi_wdata;
input [3:0]s_axi_wstrb;
input [0:0]s_axi_wlast;
input [0:0]s_axi_wvalid;
output [0:0]s_axi_wready;
output [11:0]s_axi_bid;
output [1:0]s_axi_bresp;
output [0:0]s_axi_bvalid;
input [0:0]s_axi_bready;
input [11:0]s_axi_arid;
input [31:0]s_axi_araddr;
input [7:0]s_axi_arlen;
input [2:0]s_axi_arsize;
input [1:0]s_axi_arburst;
input [0:0]s_axi_arlock;
input [3:0]s_axi_arcache;
input [2:0]s_axi_arprot;
input [3:0]s_axi_arqos;
input [0:0]s_axi_arvalid;
output [0:0]s_axi_arready;
output [11:0]s_axi_rid;
output [31:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output [0:0]s_axi_rlast;
output [0:0]s_axi_rvalid;
input [0:0]s_axi_rready;
output [127:0]m_axi_awaddr;
output [31:0]m_axi_awlen;
output [11:0]m_axi_awsize;
output [7:0]m_axi_awburst;
output [3:0]m_axi_awlock;
output [15:0]m_axi_awcache;
output [11:0]m_axi_awprot;
output [15:0]m_axi_awregion;
output [15:0]m_axi_awqos;
output [3:0]m_axi_awvalid;
input [3:0]m_axi_awready;
output [127:0]m_axi_wdata;
output [15:0]m_axi_wstrb;
output [3:0]m_axi_wlast;
output [3:0]m_axi_wvalid;
input [3:0]m_axi_wready;
input [7:0]m_axi_bresp;
input [3:0]m_axi_bvalid;
output [3:0]m_axi_bready;
output [127:0]m_axi_araddr;
output [31:0]m_axi_arlen;
output [11:0]m_axi_arsize;
output [7:0]m_axi_arburst;
output [3:0]m_axi_arlock;
output [15:0]m_axi_arcache;
output [11:0]m_axi_arprot;
output [15:0]m_axi_arregion;
output [15:0]m_axi_arqos;
output [3:0]m_axi_arvalid;
input [3:0]m_axi_arready;
input [127:0]m_axi_rdata;
input [7:0]m_axi_rresp;
input [3:0]m_axi_rlast;
input [3:0]m_axi_rvalid;
output [3:0]m_axi_rready;
endmodule |
module _4bit_binary_counter_tb(
);
parameter COUNT = 85;
parameter DELAY = 10;
reg CP, M, LD_n, CLR_n;
reg [3:0] D;
wire [3:0] Q;
wire Qcc_n;
integer i;
_4bit_binary_counter DUT (.CP(CP), .M(M), .D(D), .LD_n(LD_n), .CLR_n(CLR_n), .Q(Q), .Qcc_n(Qcc_n));
initial begin
#(COUNT * DELAY) $finish;
end
initial begin
CP = 0;
for (i = 0; i < COUNT; i = i + 1) begin
#DELAY CP = ~CP;
end
end
initial begin
M = 1;
#(COUNT*DELAY/2) M = 0;
end
initial begin
D = 4'b1111; LD_n = 1; CLR_n = 0;
#DELAY CLR_n = 1;
#(5*DELAY) CLR_n = 0;
#(3*DELAY) CLR_n = 1;
#(5*DELAY) LD_n = 0;
#(2*DELAY) D = 4'b0111;
#(4*DELAY) LD_n = 1;
end
endmodule |
module mult_add_fix8bx2 (
output wire [16:0] result, // result.result
input wire [7:0] dataa_0, // dataa_0.dataa_0
input wire [7:0] dataa_1, // dataa_1.dataa_1
input wire [7:0] datab_0, // datab_0.datab_0
input wire [7:0] datab_1, // datab_1.datab_1
input wire clock0 // clock0.clock0
);
mult_add_fix8bx2_0002 mult_add_fix8bx2_inst (
.result (result), // result.result
.dataa_0 (dataa_0), // dataa_0.dataa_0
.dataa_1 (dataa_1), // dataa_1.dataa_1
.datab_0 (datab_0), // datab_0.datab_0
.datab_1 (datab_1), // datab_1.datab_1
.clock0 (clock0) // clock0.clock0
);
endmodule |
module ee201_debouncer(CLK, RESET, PB, DPB, SCEN, MCEN, CCEN);
//inputs
input CLK, RESET;
input PB;
//outputs
output DPB;
output SCEN, MCEN, CCEN;
//parameters
parameter N_dc = 7;
(* fsm_encoding = "user" *)
reg [5:0] state;
// other items not controlledd by the special atribute
reg [N_dc-1:0] debounce_count;
reg [3:0] MCEN_count;
//concurrent signal assignment statements
// The following is possible because of the output coding used by us.
assign {DPB, SCEN, MCEN, CCEN} = state[5:2];
//constants used for state naming // the don't cares are replaced here with zeros
localparam
INI = 6'b000000,
W84 = 6'b000001,
SCEN_st = 6'b111100,
WS = 6'b100000,
MCEN_st = 6'b101100,
CCEN_st = 6'b100100,
MCEN_cont = 6'b101101,
CCR = 6'b100001,
WFCR = 6'b100010;
//logic
always @ (posedge CLK, posedge RESET)
begin : State_Machine
if (RESET)
begin
state <= INI;
debounce_count <= 'bx;
MCEN_count <= 4'bx;
end
else
begin
case (state)
INI: begin
debounce_count <= 0;
MCEN_count <= 0;
if (PB)
begin
state <= W84;
end
end
W84: begin
debounce_count <= debounce_count + 1;
if (!PB)
begin
state <= INI;
end
else if (debounce_count[N_dc-5])// for N_dc of 28, it is debounce_count[23], i.e T = 0.084 sec for f = 100MHz
begin
state <= SCEN_st;
end
end
SCEN_st: begin
debounce_count <= 0;
MCEN_count <= MCEN_count + 1;
state <= WS;
end
WS: begin
debounce_count <= debounce_count + 1;
if (!PB)
begin
state <= CCR;
end
else if (debounce_count[N_dc-1])// for N_dc of 28, it is debounce_count[27], i.e T = 1.342 sec for f = 100MHz
begin
state <= MCEN_st;
end
end
MCEN_st: begin
debounce_count <= 0;
MCEN_count <= MCEN_count + 1;
state <= CCEN_st;
end
CCEN_st: begin
debounce_count <= debounce_count + 1;
if (!PB)
begin
state <= CCR;
end
else if (debounce_count[N_dc-1])// for N_dc of 28, it is debounce_count[27], i.e T = 1.342 sec for f = 100MHz
begin
if (MCEN_count == 4'b1000)
begin
state <= MCEN_cont;
end
else
begin
state <= MCEN_st;
end
end
end
MCEN_cont: begin
if (!PB)
begin
state <= CCR;
end
end
CCR: begin
debounce_count <= 0;
MCEN_count <= 0;
state <= WFCR;
end
WFCR: begin
debounce_count <= debounce_count + 1;
if (PB)
begin
state <= WS;
end
else if (debounce_count[N_dc-5])// for N_dc of 28, it is debounce_count[23], i.e T = 0.084 sec for f = 100MHz
begin
state <= INI;
end
end
endcase
end
end // State_Machine
endmodule |
module nios_system_CPU_jtag_debug_module_tck (
// inputs:
MonDReg,
break_readreg,
dbrk_hit0_latch,
dbrk_hit1_latch,
dbrk_hit2_latch,
dbrk_hit3_latch,
debugack,
ir_in,
jtag_state_rti,
monitor_error,
monitor_ready,
reset_n,
resetlatch,
tck,
tdi,
tracemem_on,
tracemem_trcdata,
tracemem_tw,
trc_im_addr,
trc_on,
trc_wrap,
trigbrktype,
trigger_state_1,
vs_cdr,
vs_sdr,
vs_uir,
// outputs:
ir_out,
jrst_n,
sr,
st_ready_test_idle,
tdo
)
;
output [ 1: 0] ir_out;
output jrst_n;
output [ 37: 0] sr;
output st_ready_test_idle;
output tdo;
input [ 31: 0] MonDReg;
input [ 31: 0] break_readreg;
input dbrk_hit0_latch;
input dbrk_hit1_latch;
input dbrk_hit2_latch;
input dbrk_hit3_latch;
input debugack;
input [ 1: 0] ir_in;
input jtag_state_rti;
input monitor_error;
input monitor_ready;
input reset_n;
input resetlatch;
input tck;
input tdi;
input tracemem_on;
input [ 35: 0] tracemem_trcdata;
input tracemem_tw;
input [ 6: 0] trc_im_addr;
input trc_on;
input trc_wrap;
input trigbrktype;
input trigger_state_1;
input vs_cdr;
input vs_sdr;
input vs_uir;
reg [ 2: 0] DRsize /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
wire debugack_sync;
reg [ 1: 0] ir_out;
wire jrst_n;
wire monitor_ready_sync;
reg [ 37: 0] sr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
wire st_ready_test_idle;
wire tdo;
wire unxcomplemented_resetxx0;
wire unxcomplemented_resetxx1;
always @(posedge tck)
begin
if (vs_cdr)
case (ir_in)
2'b00: begin
sr[35] <= debugack_sync;
sr[34] <= monitor_error;
sr[33] <= resetlatch;
sr[32 : 1] <= MonDReg;
sr[0] <= monitor_ready_sync;
end // 2'b00
2'b01: begin
sr[35 : 0] <= tracemem_trcdata;
sr[37] <= tracemem_tw;
sr[36] <= tracemem_on;
end // 2'b01
2'b10: begin
sr[37] <= trigger_state_1;
sr[36] <= dbrk_hit3_latch;
sr[35] <= dbrk_hit2_latch;
sr[34] <= dbrk_hit1_latch;
sr[33] <= dbrk_hit0_latch;
sr[32 : 1] <= break_readreg;
sr[0] <= trigbrktype;
end // 2'b10
2'b11: begin
sr[15 : 12] <= 1'b0;
sr[11 : 2] <= trc_im_addr;
sr[1] <= trc_wrap;
sr[0] <= trc_on;
end // 2'b11
endcase // ir_in
if (vs_sdr)
case (DRsize)
3'b000: begin
sr <= {tdi, sr[37 : 2], tdi};
end // 3'b000
3'b001: begin
sr <= {tdi, sr[37 : 9], tdi, sr[7 : 1]};
end // 3'b001
3'b010: begin
sr <= {tdi, sr[37 : 17], tdi, sr[15 : 1]};
end // 3'b010
3'b011: begin
sr <= {tdi, sr[37 : 33], tdi, sr[31 : 1]};
end // 3'b011
3'b100: begin
sr <= {tdi, sr[37], tdi, sr[35 : 1]};
end // 3'b100
3'b101: begin
sr <= {tdi, sr[37 : 1]};
end // 3'b101
default: begin
sr <= {tdi, sr[37 : 2], tdi};
end // default
endcase // DRsize
if (vs_uir)
case (ir_in)
2'b00: begin
DRsize <= 3'b100;
end // 2'b00
2'b01: begin
DRsize <= 3'b101;
end // 2'b01
2'b10: begin
DRsize <= 3'b101;
end // 2'b10
2'b11: begin
DRsize <= 3'b010;
end // 2'b11
endcase // ir_in
end
assign tdo = sr[0];
assign st_ready_test_idle = jtag_state_rti;
assign unxcomplemented_resetxx0 = jrst_n;
altera_std_synchronizer the_altera_std_synchronizer
(
.clk (tck),
.din (debugack),
.dout (debugack_sync),
.reset_n (unxcomplemented_resetxx0)
);
defparam the_altera_std_synchronizer.depth = 2;
assign unxcomplemented_resetxx1 = jrst_n;
altera_std_synchronizer the_altera_std_synchronizer1
(
.clk (tck),
.din (monitor_ready),
.dout (monitor_ready_sync),
.reset_n (unxcomplemented_resetxx1)
);
defparam the_altera_std_synchronizer1.depth = 2;
always @(posedge tck or negedge jrst_n)
begin
if (jrst_n == 0)
ir_out <= 2'b0;
else
ir_out <= {debugack_sync, monitor_ready_sync};
end
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
assign jrst_n = reset_n;
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// assign jrst_n = 1;
//synthesis read_comments_as_HDL off
endmodule |
module sky130_fd_sc_lp__iso1p_lp (
X ,
A ,
SLEEP,
KAPWR,
VGND ,
VPB ,
VNB
);
output X ;
input A ;
input SLEEP;
input KAPWR;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_lp__iso1p base (
.X(X),
.A(A),
.SLEEP(SLEEP),
.KAPWR(KAPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule |
module sky130_fd_sc_lp__iso1p_lp (
X ,
A ,
SLEEP
);
output X ;
input A ;
input SLEEP;
// Voltage supply signals
supply1 KAPWR;
supply0 VGND ;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__iso1p base (
.X(X),
.A(A),
.SLEEP(SLEEP)
);
endmodule |
module top();
// Inputs are registered
reg D;
reg RESET_B;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Q;
wire Q_N;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
RESET_B = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 D = 1'b0;
#40 RESET_B = 1'b0;
#60 VGND = 1'b0;
#80 VNB = 1'b0;
#100 VPB = 1'b0;
#120 VPWR = 1'b0;
#140 D = 1'b1;
#160 RESET_B = 1'b1;
#180 VGND = 1'b1;
#200 VNB = 1'b1;
#220 VPB = 1'b1;
#240 VPWR = 1'b1;
#260 D = 1'b0;
#280 RESET_B = 1'b0;
#300 VGND = 1'b0;
#320 VNB = 1'b0;
#340 VPB = 1'b0;
#360 VPWR = 1'b0;
#380 VPWR = 1'b1;
#400 VPB = 1'b1;
#420 VNB = 1'b1;
#440 VGND = 1'b1;
#460 RESET_B = 1'b1;
#480 D = 1'b1;
#500 VPWR = 1'bx;
#520 VPB = 1'bx;
#540 VNB = 1'bx;
#560 VGND = 1'bx;
#580 RESET_B = 1'bx;
#600 D = 1'bx;
end
// Create a clock
reg CLK;
initial
begin
CLK = 1'b0;
end
always
begin
#5 CLK = ~CLK;
end
sky130_fd_sc_hd__dfrbp dut (.D(D), .RESET_B(RESET_B), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Q(Q), .Q_N(Q_N), .CLK(CLK));
endmodule |
module sctag_tagdp( /*AUTOARG*/
// Outputs
tagdp_evict_tag_c4, tagdp_diag_data_c7, tagdp_lkup_addr_c4,
lkup_row_addr_dcd_c3, lkup_row_addr_icd_c3, tagdp_lkup_addr11_c4,
mbdata_inst_tecc_c8, so, lkup_tag_c1, arbdp_tag_idx_px2_buf,
mbist_l2t_index_buf, arbctl_tag_way_px2_buf,
mbist_l2t_dec_way_buf, arbctl_tag_rd_px2_buf, mbist_l2t_read_buf,
arbctl_tag_wr_px2_buf, mbist_l2t_write_buf, tag_wrdata_px2_buf,
mbist_write_data_buf,
// Inputs
dir_cam_addr_c3, arbaddr_idx_c3, arbdp_tagdata_px2, tag_triad0_c3,
tag_triad1_c3, tag_triad2_c3, tag_triad3_c3, tag_quad_muxsel_c3,
arbdp_tag_idx_px2, mbist_l2t_index, arbctl_tag_way_px2,
mbist_l2t_dec_way, arbctl_tag_rd_px2, mbist_l2t_read,
arbctl_tag_wr_px2, mbist_l2t_write, tag_wrdata_px2,
mbist_write_data, arbctl_evict_c3, rclk, si, se, sehold
);
input [39:8] dir_cam_addr_c3; // from arbaddr
input [9:0] arbaddr_idx_c3; // from arbaddr
input [`TAG_WIDTH-1:6] arbdp_tagdata_px2 ; // write data for tag.
input [`TAG_WIDTH-1:0] tag_triad0_c3;
input [`TAG_WIDTH-1:0] tag_triad1_c3;
input [`TAG_WIDTH-1:0] tag_triad2_c3;
input [`TAG_WIDTH-1:0] tag_triad3_c3;
input [3:0] tag_quad_muxsel_c3 ; // to tagdp
output [`TAG_WIDTH-1:0] tagdp_evict_tag_c4; // to wbdata.
output [`TAG_WIDTH-1:0] tagdp_diag_data_c7; // to oqdp
output [39:10] tagdp_lkup_addr_c4; // to the directory
output [2:0] lkup_row_addr_dcd_c3, lkup_row_addr_icd_c3;
output tagdp_lkup_addr11_c4; // to dirrep. // NEW_PIN POST_4.2
output [5:0] mbdata_inst_tecc_c8; // to miss buffer data.
output so;
// lkup_tag_c1[`TAG_WIDTH-1:6] replaces wrdata_tag_c1;
output [`TAG_WIDTH-1:1] lkup_tag_c1; // to tag.
input [9:0] arbdp_tag_idx_px2;
input [9:0] mbist_l2t_index;
input [11:0] arbctl_tag_way_px2;
input [11:0] mbist_l2t_dec_way;
input arbctl_tag_rd_px2;
input mbist_l2t_read;
input arbctl_tag_wr_px2;
input mbist_l2t_write;
input [27:0] tag_wrdata_px2;
input [7:0] mbist_write_data;
output [9:0] arbdp_tag_idx_px2_buf;
output [9:0] mbist_l2t_index_buf;
output [11:0] arbctl_tag_way_px2_buf;
output [11:0] mbist_l2t_dec_way_buf;
output arbctl_tag_rd_px2_buf;
output mbist_l2t_read_buf;
output arbctl_tag_wr_px2_buf;
output mbist_l2t_write_buf;
output [27:0] tag_wrdata_px2_buf;
output [7:0] mbist_write_data_buf;
input arbctl_evict_c3;
input rclk;
input si,se;
input sehold; // POST_4.1
wire [29:6] tmp_lkup_tag_c1 ;
wire [5:0] parity_c1;
wire [5:0] tag_acc_ecc_c1, tag_acc_ecc_c2, tag_acc_ecc_c3;
wire [5:0] tag_acc_ecc_c4, tag_acc_ecc_c5, tag_acc_ecc_c6;
wire [5:0] tag_acc_ecc_c7;
wire [`TAG_WIDTH-1:0] tagdp_evict_tag_c3, tagdp_diag_data_c6; // to oqdp
wire [39:8] evict_addr_c3;
wire [39:8] lkup_addr_c3;
wire [39:10] tagdp_lkup_addr_c3;
wire [`TAG_WIDTH-1:6] wrdata_tag_c1;
// New functionality POST_4.1
// sehold will make ff_wrdata_tag_c1 non-transparent.
wire clk_1;
clken_buf clk_buf (.clk(clk_1), .rclk(rclk), .enb_l(sehold), .tmb_l(~se));
// reduced the width of this flop.
dff_s #(`TAG_WIDTH-6) ff_wrdata_tag_c1
(.din(arbdp_tagdata_px2[`TAG_WIDTH-1:6]), .clk(clk_1),
.q(wrdata_tag_c1[`TAG_WIDTH-1:6]), .se(se), .si(), .so());
zzecc_sctag_24b_gen tagecc0 (.din({2'b0,wrdata_tag_c1[`TAG_WIDTH-1:6]}),
.dout(tmp_lkup_tag_c1[29:6]),
.parity(parity_c1[5:0]));
assign tag_acc_ecc_c1 = { parity_c1[4:0], parity_c1[5] } ;
/////////////////////////////////////////////////////////
// To prevent the tag_acc_ecc_c1 bits from being
// part of the critical path in the tag compare operation,
// the overall parity bit P is not compared
//
// The check bits in tag_acc_ecc_c1 take 4 levels of XOR
// to compute whereas the overall parity P takes 5 levels.
//
// Not comparing P means that a hit could be signalled
// inspite of an error in the P bit. This requires the
// parity computation in C2 to account for this case
// and not cause any Miss Buffer insertions.
/////////////////////////////////////////////////////////
assign lkup_tag_c1[`TAG_WIDTH-1:6] = wrdata_tag_c1[`TAG_WIDTH-1:6] ;
assign lkup_tag_c1[5:1] = tag_acc_ecc_c1[5:1] ;
/////////////////////////////////////////////
// Directory lkup address
/////////////////////////////////////////////
assign evict_addr_c3[39:8] = { tagdp_evict_tag_c3[`TAG_WIDTH-1:6],
arbaddr_idx_c3[9:0] } ;
mux2ds #(32) mux_cam_addr_c3 ( .dout (lkup_addr_c3[39:8]),
.in0(dir_cam_addr_c3[39:8]), .in1(evict_addr_c3[39:8]),
.sel0(~arbctl_evict_c3), .sel1(arbctl_evict_c3));
assign tagdp_lkup_addr_c3[39:10] = lkup_addr_c3[39:10] ;
dff_s #(30) ff_tagdp_lkup_addr_c4 (.din(tagdp_lkup_addr_c3[39:10]), .clk(rclk),
.q(tagdp_lkup_addr_c4[39:10]), .se(se), .si(), .so());
/////////////////////////////////////////////
// LRU mux.
/////////////////////////////////////////////
mux4ds #(`TAG_WIDTH) mux_lru_tag (.dout (tagdp_evict_tag_c3[`TAG_WIDTH-1:0]),
.in0(tag_triad0_c3[`TAG_WIDTH-1:0]),
.in1(tag_triad1_c3[`TAG_WIDTH-1:0]),
.in2(tag_triad2_c3[`TAG_WIDTH-1:0]),
.in3(tag_triad3_c3[`TAG_WIDTH-1:0]),
.sel0(tag_quad_muxsel_c3[0]),
.sel1(tag_quad_muxsel_c3[1]),
.sel2(tag_quad_muxsel_c3[2]),
.sel3(tag_quad_muxsel_c3[3]));
//////////////////////////////////////////////////////////////////////////////////////////////
// Tag Diagnostic data pipeline
//------------------------------------------------------------------------------------------
// C1 C2 C3 C4 C5 C6 C7 C8 C9
//------------------------------------------------------------------------------------------
// diag px2 rd tag prepare mux flop flop mux data ret.
// decode idx mux way mux out tag with
// sels and flop other
// diag data
//------------------------------------------------------------------------------------------
//////////////////////////////////////////////////////////////////////////////////////////////
dff_s #(`TAG_WIDTH) ff_tagdp_evict_tag_c4 (.din(tagdp_evict_tag_c3[`TAG_WIDTH-1:0]), .clk(rclk),
.q(tagdp_evict_tag_c4[`TAG_WIDTH-1:0]), .se(se), .si(), .so());
dff_s #(`TAG_WIDTH) ff_tagdp_diag_data_c6 (.din(tagdp_evict_tag_c4[`TAG_WIDTH-1:0]), .clk(rclk),
.q(tagdp_diag_data_c6[`TAG_WIDTH-1:0]), .se(se), .si(), .so());
dff_s #(`TAG_WIDTH) ff_tagdp_diag_data_c7 (.din(tagdp_diag_data_c6[`TAG_WIDTH-1:0]), .clk(rclk),
.q(tagdp_diag_data_c7[`TAG_WIDTH-1:0]), .se(se), .si(), .so());
/////////////////////////////////////////////
// DP is 32 bits wide. The following
// logic and flops are pushed to one side.
/////////////////////////////////////////////
dff_s #(6) ff_ecc_c2 (.din(tag_acc_ecc_c1[5:0]), .clk(rclk),
.q(tag_acc_ecc_c2[5:0]), .se(se), .si(), .so());
dff_s #(6) ff_ecc_c3 (.din(tag_acc_ecc_c2[5:0]), .clk(rclk),
.q(tag_acc_ecc_c3[5:0]), .se(se), .si(), .so());
dff_s #(6) ff_ecc_c4 (.din(tag_acc_ecc_c3[5:0]), .clk(rclk),
.q(tag_acc_ecc_c4[5:0]), .se(se), .si(), .so());
dff_s #(6) ff_ecc_c5 (.din(tag_acc_ecc_c4[5:0]), .clk(rclk),
.q(tag_acc_ecc_c5[5:0]), .se(se), .si(), .so());
dff_s #(6) ff_ecc_c6 (.din(tag_acc_ecc_c5[5:0]), .clk(rclk),
.q(tag_acc_ecc_c6[5:0]), .se(se), .si(), .so());
dff_s #(6) ff_ecc_c7 (.din(tag_acc_ecc_c6[5:0]), .clk(rclk),
.q(tag_acc_ecc_c7[5:0]), .se(se), .si(), .so());
dff_s #(6) ff_ecc_c8 (.din(tag_acc_ecc_c7[5:0]), .clk(rclk),
.q(mbdata_inst_tecc_c8[5:0]), .se(se), .si(), .so());
assign lkup_row_addr_dcd_c3[2:0] = lkup_addr_c3[10:8];
assign lkup_row_addr_icd_c3[2:0] = lkup_addr_c3[10:8];
dff_s #(1) ff_addr11_c4 (.din(lkup_addr_c3[11]), .clk(rclk),
.q(tagdp_lkup_addr11_c4), .se(se), .si(), .so());
////////////////////////////////////////////////////////////
// The following signals need to be bufferred before
// the tag.
// INput pins are arranged on the top.
// Try to align with the data path cell placement information
// provided below.
////////////////////////////////////////////////////////////
// repeater row1 ( 24 bits wide ) arranged as follows from left to right.
// index [0 ..... 9]
// way [11 .... 0 ]
// rd
// wr
assign arbdp_tag_idx_px2_buf[9:0] = arbdp_tag_idx_px2[9:0] ;
assign arbctl_tag_way_px2_buf[11:0] = arbctl_tag_way_px2[11:0] ;
assign arbctl_tag_rd_px2_buf = arbctl_tag_rd_px2;
assign arbctl_tag_wr_px2_buf = arbctl_tag_wr_px2;
// repeater row2 ( 24 bits wide ) arranged as follows from left to right.
// index [0 ..... 9]
// way [11 .... 0 ]
// rd
// wr
assign mbist_l2t_index_buf[9:0] = mbist_l2t_index[9:0] ;
assign mbist_l2t_dec_way_buf[11:0] = mbist_l2t_dec_way[11:0] ;
assign mbist_l2t_read_buf = mbist_l2t_read;
assign mbist_l2t_write_buf = mbist_l2t_write;
// repeater row 3 ( 28 bits wide ) arranged as follows from left to right.
// wr_data [0 .. 27]
assign tag_wrdata_px2_buf = tag_wrdata_px2 ;
// repeater row 4 ( 8 bits wide ) arranged as follows from left to right.
assign mbist_write_data_buf = mbist_write_data;
endmodule |
module sky130_fd_sc_hdll__dlygate4sd3 (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire buf0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X , A );
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, buf0_out_X, VPWR, VGND);
buf buf1 (X , pwrgood_pp0_out_X );
endmodule |
module alt_mem_ddrx_ecc_decoder_64_decode
(
data,
eq) /* synthesis synthesis_clearbox=1 */;
input [6:0] data;
output [127:0] eq;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 [6:0] data;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [5:0] data_wire;
wire enable_wire1;
wire enable_wire2;
wire [127:0] eq_node;
wire [63:0] eq_wire1;
wire [63:0] eq_wire2;
wire [3:0] w_anode1006w;
wire [3:0] w_anode1018w;
wire [3:0] w_anode1029w;
wire [3:0] w_anode1040w;
wire [3:0] w_anode1050w;
wire [3:0] w_anode1060w;
wire [3:0] w_anode1070w;
wire [3:0] w_anode1080w;
wire [3:0] w_anode1090w;
wire [3:0] w_anode1100w;
wire [3:0] w_anode1111w;
wire [3:0] w_anode1122w;
wire [3:0] w_anode1133w;
wire [3:0] w_anode1143w;
wire [3:0] w_anode1153w;
wire [3:0] w_anode1163w;
wire [3:0] w_anode1173w;
wire [3:0] w_anode1183w;
wire [3:0] w_anode1193w;
wire [3:0] w_anode1204w;
wire [3:0] w_anode1215w;
wire [3:0] w_anode1226w;
wire [3:0] w_anode1236w;
wire [3:0] w_anode1246w;
wire [3:0] w_anode1256w;
wire [3:0] w_anode1266w;
wire [3:0] w_anode1276w;
wire [3:0] w_anode1286w;
wire [3:0] w_anode1297w;
wire [3:0] w_anode1308w;
wire [3:0] w_anode1319w;
wire [3:0] w_anode1329w;
wire [3:0] w_anode1339w;
wire [3:0] w_anode1349w;
wire [3:0] w_anode1359w;
wire [3:0] w_anode1369w;
wire [3:0] w_anode1379w;
wire [3:0] w_anode1390w;
wire [3:0] w_anode1401w;
wire [3:0] w_anode1412w;
wire [3:0] w_anode1422w;
wire [3:0] w_anode1432w;
wire [3:0] w_anode1442w;
wire [3:0] w_anode1452w;
wire [3:0] w_anode1462w;
wire [3:0] w_anode1472w;
wire [3:0] w_anode1483w;
wire [3:0] w_anode1494w;
wire [3:0] w_anode1505w;
wire [3:0] w_anode1515w;
wire [3:0] w_anode1525w;
wire [3:0] w_anode1535w;
wire [3:0] w_anode1545w;
wire [3:0] w_anode1555w;
wire [3:0] w_anode1565w;
wire [3:0] w_anode1576w;
wire [3:0] w_anode1587w;
wire [3:0] w_anode1598w;
wire [3:0] w_anode1608w;
wire [3:0] w_anode1618w;
wire [3:0] w_anode1628w;
wire [3:0] w_anode1638w;
wire [3:0] w_anode1648w;
wire [3:0] w_anode1658w;
wire [3:0] w_anode1670w;
wire [3:0] w_anode1681w;
wire [3:0] w_anode1698w;
wire [3:0] w_anode1708w;
wire [3:0] w_anode1718w;
wire [3:0] w_anode1728w;
wire [3:0] w_anode1738w;
wire [3:0] w_anode1748w;
wire [3:0] w_anode1758w;
wire [3:0] w_anode1770w;
wire [3:0] w_anode1781w;
wire [3:0] w_anode1792w;
wire [3:0] w_anode1802w;
wire [3:0] w_anode1812w;
wire [3:0] w_anode1822w;
wire [3:0] w_anode1832w;
wire [3:0] w_anode1842w;
wire [3:0] w_anode1852w;
wire [3:0] w_anode1863w;
wire [3:0] w_anode1874w;
wire [3:0] w_anode1885w;
wire [3:0] w_anode1895w;
wire [3:0] w_anode1905w;
wire [3:0] w_anode1915w;
wire [3:0] w_anode1925w;
wire [3:0] w_anode1935w;
wire [3:0] w_anode1945w;
wire [3:0] w_anode1956w;
wire [3:0] w_anode1967w;
wire [3:0] w_anode1978w;
wire [3:0] w_anode1988w;
wire [3:0] w_anode1998w;
wire [3:0] w_anode2008w;
wire [3:0] w_anode2018w;
wire [3:0] w_anode2028w;
wire [3:0] w_anode2038w;
wire [3:0] w_anode2049w;
wire [3:0] w_anode2060w;
wire [3:0] w_anode2071w;
wire [3:0] w_anode2081w;
wire [3:0] w_anode2091w;
wire [3:0] w_anode2101w;
wire [3:0] w_anode2111w;
wire [3:0] w_anode2121w;
wire [3:0] w_anode2131w;
wire [3:0] w_anode2142w;
wire [3:0] w_anode2153w;
wire [3:0] w_anode2164w;
wire [3:0] w_anode2174w;
wire [3:0] w_anode2184w;
wire [3:0] w_anode2194w;
wire [3:0] w_anode2204w;
wire [3:0] w_anode2214w;
wire [3:0] w_anode2224w;
wire [3:0] w_anode2235w;
wire [3:0] w_anode2246w;
wire [3:0] w_anode2257w;
wire [3:0] w_anode2267w;
wire [3:0] w_anode2277w;
wire [3:0] w_anode2287w;
wire [3:0] w_anode2297w;
wire [3:0] w_anode2307w;
wire [3:0] w_anode2317w;
wire [3:0] w_anode2328w;
wire [3:0] w_anode2339w;
wire [3:0] w_anode2350w;
wire [3:0] w_anode2360w;
wire [3:0] w_anode2370w;
wire [3:0] w_anode2380w;
wire [3:0] w_anode2390w;
wire [3:0] w_anode2400w;
wire [3:0] w_anode2410w;
wire [3:0] w_anode912w;
wire [3:0] w_anode929w;
wire [3:0] w_anode946w;
wire [3:0] w_anode956w;
wire [3:0] w_anode966w;
wire [3:0] w_anode976w;
wire [3:0] w_anode986w;
wire [3:0] w_anode996w;
wire [2:0] w_data1669w;
wire [2:0] w_data910w;
assign
data_wire = data[5:0],
enable_wire1 = (~ data[6]),
enable_wire2 = data[6],
eq = eq_node,
eq_node = {eq_wire2[63:0], eq_wire1},
eq_wire1 = {{w_anode1658w[3], w_anode1648w[3], w_anode1638w[3], w_anode1628w[3], w_anode1618w[3], w_anode1608w[3], w_anode1598w[3], w_anode1587w[3]}, {w_anode1565w[3], w_anode1555w[3], w_anode1545w[3], w_anode1535w[3], w_anode1525w[3], w_anode1515w[3], w_anode1505w[3], w_anode1494w[3]}, {w_anode1472w[3], w_anode1462w[3], w_anode1452w[3], w_anode1442w[3], w_anode1432w[3], w_anode1422w[3], w_anode1412w[3], w_anode1401w[3]}, {w_anode1379w[3], w_anode1369w[3], w_anode1359w[3], w_anode1349w[3], w_anode1339w[3], w_anode1329w[3], w_anode1319w[3], w_anode1308w[3]}, {w_anode1286w[3], w_anode1276w[3], w_anode1266w[3], w_anode1256w[3], w_anode1246w[3], w_anode1236w[3], w_anode1226w[3], w_anode1215w[3]}, {w_anode1193w[3], w_anode1183w[3], w_anode1173w[3], w_anode1163w[3], w_anode1153w[3], w_anode1143w[3], w_anode1133w[3], w_anode1122w[3]}, {w_anode1100w[3], w_anode1090w[3], w_anode1080w[3], w_anode1070w[3], w_anode1060w[3], w_anode1050w[3], w_anode1040w[3], w_anode1029w[3]}, {w_anode1006w[3], w_anode996w[3], w_anode986w[3], w_anode976w[3], w_anode966w[3], w_anode956w[3], w_anode946w[3], w_anode929w[3]}},
eq_wire2 = {{w_anode2410w[3], w_anode2400w[3], w_anode2390w[3], w_anode2380w[3], w_anode2370w[3], w_anode2360w[3], w_anode2350w[3], w_anode2339w[3]}, {w_anode2317w[3], w_anode2307w[3], w_anode2297w[3], w_anode2287w[3], w_anode2277w[3], w_anode2267w[3], w_anode2257w[3], w_anode2246w[3]}, {w_anode2224w[3], w_anode2214w[3], w_anode2204w[3], w_anode2194w[3], w_anode2184w[3], w_anode2174w[3], w_anode2164w[3], w_anode2153w[3]}, {w_anode2131w[3], w_anode2121w[3], w_anode2111w[3], w_anode2101w[3], w_anode2091w[3], w_anode2081w[3], w_anode2071w[3], w_anode2060w[3]}, {w_anode2038w[3], w_anode2028w[3], w_anode2018w[3], w_anode2008w[3], w_anode1998w[3], w_anode1988w[3], w_anode1978w[3], w_anode1967w[3]}, {w_anode1945w[3], w_anode1935w[3], w_anode1925w[3], w_anode1915w[3], w_anode1905w[3], w_anode1895w[3], w_anode1885w[3], w_anode1874w[3]}, {w_anode1852w[3], w_anode1842w[3], w_anode1832w[3], w_anode1822w[3], w_anode1812w[3], w_anode1802w[3], w_anode1792w[3], w_anode1781w[3]}, {w_anode1758w[3], w_anode1748w[3], w_anode1738w[3], w_anode1728w[3], w_anode1718w[3], w_anode1708w[3], w_anode1698w[3], w_anode1681w[3]}},
w_anode1006w = {(w_anode1006w[2] & w_data910w[2]), (w_anode1006w[1] & w_data910w[1]), (w_anode1006w[0] & w_data910w[0]), w_anode912w[3]},
w_anode1018w = {(w_anode1018w[2] & (~ data_wire[5])), (w_anode1018w[1] & (~ data_wire[4])), (w_anode1018w[0] & data_wire[3]), enable_wire1},
w_anode1029w = {(w_anode1029w[2] & (~ w_data910w[2])), (w_anode1029w[1] & (~ w_data910w[1])), (w_anode1029w[0] & (~ w_data910w[0])), w_anode1018w[3]},
w_anode1040w = {(w_anode1040w[2] & (~ w_data910w[2])), (w_anode1040w[1] & (~ w_data910w[1])), (w_anode1040w[0] & w_data910w[0]), w_anode1018w[3]},
w_anode1050w = {(w_anode1050w[2] & (~ w_data910w[2])), (w_anode1050w[1] & w_data910w[1]), (w_anode1050w[0] & (~ w_data910w[0])), w_anode1018w[3]},
w_anode1060w = {(w_anode1060w[2] & (~ w_data910w[2])), (w_anode1060w[1] & w_data910w[1]), (w_anode1060w[0] & w_data910w[0]), w_anode1018w[3]},
w_anode1070w = {(w_anode1070w[2] & w_data910w[2]), (w_anode1070w[1] & (~ w_data910w[1])), (w_anode1070w[0] & (~ w_data910w[0])), w_anode1018w[3]},
w_anode1080w = {(w_anode1080w[2] & w_data910w[2]), (w_anode1080w[1] & (~ w_data910w[1])), (w_anode1080w[0] & w_data910w[0]), w_anode1018w[3]},
w_anode1090w = {(w_anode1090w[2] & w_data910w[2]), (w_anode1090w[1] & w_data910w[1]), (w_anode1090w[0] & (~ w_data910w[0])), w_anode1018w[3]},
w_anode1100w = {(w_anode1100w[2] & w_data910w[2]), (w_anode1100w[1] & w_data910w[1]), (w_anode1100w[0] & w_data910w[0]), w_anode1018w[3]},
w_anode1111w = {(w_anode1111w[2] & (~ data_wire[5])), (w_anode1111w[1] & data_wire[4]), (w_anode1111w[0] & (~ data_wire[3])), enable_wire1},
w_anode1122w = {(w_anode1122w[2] & (~ w_data910w[2])), (w_anode1122w[1] & (~ w_data910w[1])), (w_anode1122w[0] & (~ w_data910w[0])), w_anode1111w[3]},
w_anode1133w = {(w_anode1133w[2] & (~ w_data910w[2])), (w_anode1133w[1] & (~ w_data910w[1])), (w_anode1133w[0] & w_data910w[0]), w_anode1111w[3]},
w_anode1143w = {(w_anode1143w[2] & (~ w_data910w[2])), (w_anode1143w[1] & w_data910w[1]), (w_anode1143w[0] & (~ w_data910w[0])), w_anode1111w[3]},
w_anode1153w = {(w_anode1153w[2] & (~ w_data910w[2])), (w_anode1153w[1] & w_data910w[1]), (w_anode1153w[0] & w_data910w[0]), w_anode1111w[3]},
w_anode1163w = {(w_anode1163w[2] & w_data910w[2]), (w_anode1163w[1] & (~ w_data910w[1])), (w_anode1163w[0] & (~ w_data910w[0])), w_anode1111w[3]},
w_anode1173w = {(w_anode1173w[2] & w_data910w[2]), (w_anode1173w[1] & (~ w_data910w[1])), (w_anode1173w[0] & w_data910w[0]), w_anode1111w[3]},
w_anode1183w = {(w_anode1183w[2] & w_data910w[2]), (w_anode1183w[1] & w_data910w[1]), (w_anode1183w[0] & (~ w_data910w[0])), w_anode1111w[3]},
w_anode1193w = {(w_anode1193w[2] & w_data910w[2]), (w_anode1193w[1] & w_data910w[1]), (w_anode1193w[0] & w_data910w[0]), w_anode1111w[3]},
w_anode1204w = {(w_anode1204w[2] & (~ data_wire[5])), (w_anode1204w[1] & data_wire[4]), (w_anode1204w[0] & data_wire[3]), enable_wire1},
w_anode1215w = {(w_anode1215w[2] & (~ w_data910w[2])), (w_anode1215w[1] & (~ w_data910w[1])), (w_anode1215w[0] & (~ w_data910w[0])), w_anode1204w[3]},
w_anode1226w = {(w_anode1226w[2] & (~ w_data910w[2])), (w_anode1226w[1] & (~ w_data910w[1])), (w_anode1226w[0] & w_data910w[0]), w_anode1204w[3]},
w_anode1236w = {(w_anode1236w[2] & (~ w_data910w[2])), (w_anode1236w[1] & w_data910w[1]), (w_anode1236w[0] & (~ w_data910w[0])), w_anode1204w[3]},
w_anode1246w = {(w_anode1246w[2] & (~ w_data910w[2])), (w_anode1246w[1] & w_data910w[1]), (w_anode1246w[0] & w_data910w[0]), w_anode1204w[3]},
w_anode1256w = {(w_anode1256w[2] & w_data910w[2]), (w_anode1256w[1] & (~ w_data910w[1])), (w_anode1256w[0] & (~ w_data910w[0])), w_anode1204w[3]},
w_anode1266w = {(w_anode1266w[2] & w_data910w[2]), (w_anode1266w[1] & (~ w_data910w[1])), (w_anode1266w[0] & w_data910w[0]), w_anode1204w[3]},
w_anode1276w = {(w_anode1276w[2] & w_data910w[2]), (w_anode1276w[1] & w_data910w[1]), (w_anode1276w[0] & (~ w_data910w[0])), w_anode1204w[3]},
w_anode1286w = {(w_anode1286w[2] & w_data910w[2]), (w_anode1286w[1] & w_data910w[1]), (w_anode1286w[0] & w_data910w[0]), w_anode1204w[3]},
w_anode1297w = {(w_anode1297w[2] & data_wire[5]), (w_anode1297w[1] & (~ data_wire[4])), (w_anode1297w[0] & (~ data_wire[3])), enable_wire1},
w_anode1308w = {(w_anode1308w[2] & (~ w_data910w[2])), (w_anode1308w[1] & (~ w_data910w[1])), (w_anode1308w[0] & (~ w_data910w[0])), w_anode1297w[3]},
w_anode1319w = {(w_anode1319w[2] & (~ w_data910w[2])), (w_anode1319w[1] & (~ w_data910w[1])), (w_anode1319w[0] & w_data910w[0]), w_anode1297w[3]},
w_anode1329w = {(w_anode1329w[2] & (~ w_data910w[2])), (w_anode1329w[1] & w_data910w[1]), (w_anode1329w[0] & (~ w_data910w[0])), w_anode1297w[3]},
w_anode1339w = {(w_anode1339w[2] & (~ w_data910w[2])), (w_anode1339w[1] & w_data910w[1]), (w_anode1339w[0] & w_data910w[0]), w_anode1297w[3]},
w_anode1349w = {(w_anode1349w[2] & w_data910w[2]), (w_anode1349w[1] & (~ w_data910w[1])), (w_anode1349w[0] & (~ w_data910w[0])), w_anode1297w[3]},
w_anode1359w = {(w_anode1359w[2] & w_data910w[2]), (w_anode1359w[1] & (~ w_data910w[1])), (w_anode1359w[0] & w_data910w[0]), w_anode1297w[3]},
w_anode1369w = {(w_anode1369w[2] & w_data910w[2]), (w_anode1369w[1] & w_data910w[1]), (w_anode1369w[0] & (~ w_data910w[0])), w_anode1297w[3]},
w_anode1379w = {(w_anode1379w[2] & w_data910w[2]), (w_anode1379w[1] & w_data910w[1]), (w_anode1379w[0] & w_data910w[0]), w_anode1297w[3]},
w_anode1390w = {(w_anode1390w[2] & data_wire[5]), (w_anode1390w[1] & (~ data_wire[4])), (w_anode1390w[0] & data_wire[3]), enable_wire1},
w_anode1401w = {(w_anode1401w[2] & (~ w_data910w[2])), (w_anode1401w[1] & (~ w_data910w[1])), (w_anode1401w[0] & (~ w_data910w[0])), w_anode1390w[3]},
w_anode1412w = {(w_anode1412w[2] & (~ w_data910w[2])), (w_anode1412w[1] & (~ w_data910w[1])), (w_anode1412w[0] & w_data910w[0]), w_anode1390w[3]},
w_anode1422w = {(w_anode1422w[2] & (~ w_data910w[2])), (w_anode1422w[1] & w_data910w[1]), (w_anode1422w[0] & (~ w_data910w[0])), w_anode1390w[3]},
w_anode1432w = {(w_anode1432w[2] & (~ w_data910w[2])), (w_anode1432w[1] & w_data910w[1]), (w_anode1432w[0] & w_data910w[0]), w_anode1390w[3]},
w_anode1442w = {(w_anode1442w[2] & w_data910w[2]), (w_anode1442w[1] & (~ w_data910w[1])), (w_anode1442w[0] & (~ w_data910w[0])), w_anode1390w[3]},
w_anode1452w = {(w_anode1452w[2] & w_data910w[2]), (w_anode1452w[1] & (~ w_data910w[1])), (w_anode1452w[0] & w_data910w[0]), w_anode1390w[3]},
w_anode1462w = {(w_anode1462w[2] & w_data910w[2]), (w_anode1462w[1] & w_data910w[1]), (w_anode1462w[0] & (~ w_data910w[0])), w_anode1390w[3]},
w_anode1472w = {(w_anode1472w[2] & w_data910w[2]), (w_anode1472w[1] & w_data910w[1]), (w_anode1472w[0] & w_data910w[0]), w_anode1390w[3]},
w_anode1483w = {(w_anode1483w[2] & data_wire[5]), (w_anode1483w[1] & data_wire[4]), (w_anode1483w[0] & (~ data_wire[3])), enable_wire1},
w_anode1494w = {(w_anode1494w[2] & (~ w_data910w[2])), (w_anode1494w[1] & (~ w_data910w[1])), (w_anode1494w[0] & (~ w_data910w[0])), w_anode1483w[3]},
w_anode1505w = {(w_anode1505w[2] & (~ w_data910w[2])), (w_anode1505w[1] & (~ w_data910w[1])), (w_anode1505w[0] & w_data910w[0]), w_anode1483w[3]},
w_anode1515w = {(w_anode1515w[2] & (~ w_data910w[2])), (w_anode1515w[1] & w_data910w[1]), (w_anode1515w[0] & (~ w_data910w[0])), w_anode1483w[3]},
w_anode1525w = {(w_anode1525w[2] & (~ w_data910w[2])), (w_anode1525w[1] & w_data910w[1]), (w_anode1525w[0] & w_data910w[0]), w_anode1483w[3]},
w_anode1535w = {(w_anode1535w[2] & w_data910w[2]), (w_anode1535w[1] & (~ w_data910w[1])), (w_anode1535w[0] & (~ w_data910w[0])), w_anode1483w[3]},
w_anode1545w = {(w_anode1545w[2] & w_data910w[2]), (w_anode1545w[1] & (~ w_data910w[1])), (w_anode1545w[0] & w_data910w[0]), w_anode1483w[3]},
w_anode1555w = {(w_anode1555w[2] & w_data910w[2]), (w_anode1555w[1] & w_data910w[1]), (w_anode1555w[0] & (~ w_data910w[0])), w_anode1483w[3]},
w_anode1565w = {(w_anode1565w[2] & w_data910w[2]), (w_anode1565w[1] & w_data910w[1]), (w_anode1565w[0] & w_data910w[0]), w_anode1483w[3]},
w_anode1576w = {(w_anode1576w[2] & data_wire[5]), (w_anode1576w[1] & data_wire[4]), (w_anode1576w[0] & data_wire[3]), enable_wire1},
w_anode1587w = {(w_anode1587w[2] & (~ w_data910w[2])), (w_anode1587w[1] & (~ w_data910w[1])), (w_anode1587w[0] & (~ w_data910w[0])), w_anode1576w[3]},
w_anode1598w = {(w_anode1598w[2] & (~ w_data910w[2])), (w_anode1598w[1] & (~ w_data910w[1])), (w_anode1598w[0] & w_data910w[0]), w_anode1576w[3]},
w_anode1608w = {(w_anode1608w[2] & (~ w_data910w[2])), (w_anode1608w[1] & w_data910w[1]), (w_anode1608w[0] & (~ w_data910w[0])), w_anode1576w[3]},
w_anode1618w = {(w_anode1618w[2] & (~ w_data910w[2])), (w_anode1618w[1] & w_data910w[1]), (w_anode1618w[0] & w_data910w[0]), w_anode1576w[3]},
w_anode1628w = {(w_anode1628w[2] & w_data910w[2]), (w_anode1628w[1] & (~ w_data910w[1])), (w_anode1628w[0] & (~ w_data910w[0])), w_anode1576w[3]},
w_anode1638w = {(w_anode1638w[2] & w_data910w[2]), (w_anode1638w[1] & (~ w_data910w[1])), (w_anode1638w[0] & w_data910w[0]), w_anode1576w[3]},
w_anode1648w = {(w_anode1648w[2] & w_data910w[2]), (w_anode1648w[1] & w_data910w[1]), (w_anode1648w[0] & (~ w_data910w[0])), w_anode1576w[3]},
w_anode1658w = {(w_anode1658w[2] & w_data910w[2]), (w_anode1658w[1] & w_data910w[1]), (w_anode1658w[0] & w_data910w[0]), w_anode1576w[3]},
w_anode1670w = {(w_anode1670w[2] & (~ data_wire[5])), (w_anode1670w[1] & (~ data_wire[4])), (w_anode1670w[0] & (~ data_wire[3])), enable_wire2},
w_anode1681w = {(w_anode1681w[2] & (~ w_data1669w[2])), (w_anode1681w[1] & (~ w_data1669w[1])), (w_anode1681w[0] & (~ w_data1669w[0])), w_anode1670w[3]},
w_anode1698w = {(w_anode1698w[2] & (~ w_data1669w[2])), (w_anode1698w[1] & (~ w_data1669w[1])), (w_anode1698w[0] & w_data1669w[0]), w_anode1670w[3]},
w_anode1708w = {(w_anode1708w[2] & (~ w_data1669w[2])), (w_anode1708w[1] & w_data1669w[1]), (w_anode1708w[0] & (~ w_data1669w[0])), w_anode1670w[3]},
w_anode1718w = {(w_anode1718w[2] & (~ w_data1669w[2])), (w_anode1718w[1] & w_data1669w[1]), (w_anode1718w[0] & w_data1669w[0]), w_anode1670w[3]},
w_anode1728w = {(w_anode1728w[2] & w_data1669w[2]), (w_anode1728w[1] & (~ w_data1669w[1])), (w_anode1728w[0] & (~ w_data1669w[0])), w_anode1670w[3]},
w_anode1738w = {(w_anode1738w[2] & w_data1669w[2]), (w_anode1738w[1] & (~ w_data1669w[1])), (w_anode1738w[0] & w_data1669w[0]), w_anode1670w[3]},
w_anode1748w = {(w_anode1748w[2] & w_data1669w[2]), (w_anode1748w[1] & w_data1669w[1]), (w_anode1748w[0] & (~ w_data1669w[0])), w_anode1670w[3]},
w_anode1758w = {(w_anode1758w[2] & w_data1669w[2]), (w_anode1758w[1] & w_data1669w[1]), (w_anode1758w[0] & w_data1669w[0]), w_anode1670w[3]},
w_anode1770w = {(w_anode1770w[2] & (~ data_wire[5])), (w_anode1770w[1] & (~ data_wire[4])), (w_anode1770w[0] & data_wire[3]), enable_wire2},
w_anode1781w = {(w_anode1781w[2] & (~ w_data1669w[2])), (w_anode1781w[1] & (~ w_data1669w[1])), (w_anode1781w[0] & (~ w_data1669w[0])), w_anode1770w[3]},
w_anode1792w = {(w_anode1792w[2] & (~ w_data1669w[2])), (w_anode1792w[1] & (~ w_data1669w[1])), (w_anode1792w[0] & w_data1669w[0]), w_anode1770w[3]},
w_anode1802w = {(w_anode1802w[2] & (~ w_data1669w[2])), (w_anode1802w[1] & w_data1669w[1]), (w_anode1802w[0] & (~ w_data1669w[0])), w_anode1770w[3]},
w_anode1812w = {(w_anode1812w[2] & (~ w_data1669w[2])), (w_anode1812w[1] & w_data1669w[1]), (w_anode1812w[0] & w_data1669w[0]), w_anode1770w[3]},
w_anode1822w = {(w_anode1822w[2] & w_data1669w[2]), (w_anode1822w[1] & (~ w_data1669w[1])), (w_anode1822w[0] & (~ w_data1669w[0])), w_anode1770w[3]},
w_anode1832w = {(w_anode1832w[2] & w_data1669w[2]), (w_anode1832w[1] & (~ w_data1669w[1])), (w_anode1832w[0] & w_data1669w[0]), w_anode1770w[3]},
w_anode1842w = {(w_anode1842w[2] & w_data1669w[2]), (w_anode1842w[1] & w_data1669w[1]), (w_anode1842w[0] & (~ w_data1669w[0])), w_anode1770w[3]},
w_anode1852w = {(w_anode1852w[2] & w_data1669w[2]), (w_anode1852w[1] & w_data1669w[1]), (w_anode1852w[0] & w_data1669w[0]), w_anode1770w[3]},
w_anode1863w = {(w_anode1863w[2] & (~ data_wire[5])), (w_anode1863w[1] & data_wire[4]), (w_anode1863w[0] & (~ data_wire[3])), enable_wire2},
w_anode1874w = {(w_anode1874w[2] & (~ w_data1669w[2])), (w_anode1874w[1] & (~ w_data1669w[1])), (w_anode1874w[0] & (~ w_data1669w[0])), w_anode1863w[3]},
w_anode1885w = {(w_anode1885w[2] & (~ w_data1669w[2])), (w_anode1885w[1] & (~ w_data1669w[1])), (w_anode1885w[0] & w_data1669w[0]), w_anode1863w[3]},
w_anode1895w = {(w_anode1895w[2] & (~ w_data1669w[2])), (w_anode1895w[1] & w_data1669w[1]), (w_anode1895w[0] & (~ w_data1669w[0])), w_anode1863w[3]},
w_anode1905w = {(w_anode1905w[2] & (~ w_data1669w[2])), (w_anode1905w[1] & w_data1669w[1]), (w_anode1905w[0] & w_data1669w[0]), w_anode1863w[3]},
w_anode1915w = {(w_anode1915w[2] & w_data1669w[2]), (w_anode1915w[1] & (~ w_data1669w[1])), (w_anode1915w[0] & (~ w_data1669w[0])), w_anode1863w[3]},
w_anode1925w = {(w_anode1925w[2] & w_data1669w[2]), (w_anode1925w[1] & (~ w_data1669w[1])), (w_anode1925w[0] & w_data1669w[0]), w_anode1863w[3]},
w_anode1935w = {(w_anode1935w[2] & w_data1669w[2]), (w_anode1935w[1] & w_data1669w[1]), (w_anode1935w[0] & (~ w_data1669w[0])), w_anode1863w[3]},
w_anode1945w = {(w_anode1945w[2] & w_data1669w[2]), (w_anode1945w[1] & w_data1669w[1]), (w_anode1945w[0] & w_data1669w[0]), w_anode1863w[3]},
w_anode1956w = {(w_anode1956w[2] & (~ data_wire[5])), (w_anode1956w[1] & data_wire[4]), (w_anode1956w[0] & data_wire[3]), enable_wire2},
w_anode1967w = {(w_anode1967w[2] & (~ w_data1669w[2])), (w_anode1967w[1] & (~ w_data1669w[1])), (w_anode1967w[0] & (~ w_data1669w[0])), w_anode1956w[3]},
w_anode1978w = {(w_anode1978w[2] & (~ w_data1669w[2])), (w_anode1978w[1] & (~ w_data1669w[1])), (w_anode1978w[0] & w_data1669w[0]), w_anode1956w[3]},
w_anode1988w = {(w_anode1988w[2] & (~ w_data1669w[2])), (w_anode1988w[1] & w_data1669w[1]), (w_anode1988w[0] & (~ w_data1669w[0])), w_anode1956w[3]},
w_anode1998w = {(w_anode1998w[2] & (~ w_data1669w[2])), (w_anode1998w[1] & w_data1669w[1]), (w_anode1998w[0] & w_data1669w[0]), w_anode1956w[3]},
w_anode2008w = {(w_anode2008w[2] & w_data1669w[2]), (w_anode2008w[1] & (~ w_data1669w[1])), (w_anode2008w[0] & (~ w_data1669w[0])), w_anode1956w[3]},
w_anode2018w = {(w_anode2018w[2] & w_data1669w[2]), (w_anode2018w[1] & (~ w_data1669w[1])), (w_anode2018w[0] & w_data1669w[0]), w_anode1956w[3]},
w_anode2028w = {(w_anode2028w[2] & w_data1669w[2]), (w_anode2028w[1] & w_data1669w[1]), (w_anode2028w[0] & (~ w_data1669w[0])), w_anode1956w[3]},
w_anode2038w = {(w_anode2038w[2] & w_data1669w[2]), (w_anode2038w[1] & w_data1669w[1]), (w_anode2038w[0] & w_data1669w[0]), w_anode1956w[3]},
w_anode2049w = {(w_anode2049w[2] & data_wire[5]), (w_anode2049w[1] & (~ data_wire[4])), (w_anode2049w[0] & (~ data_wire[3])), enable_wire2},
w_anode2060w = {(w_anode2060w[2] & (~ w_data1669w[2])), (w_anode2060w[1] & (~ w_data1669w[1])), (w_anode2060w[0] & (~ w_data1669w[0])), w_anode2049w[3]},
w_anode2071w = {(w_anode2071w[2] & (~ w_data1669w[2])), (w_anode2071w[1] & (~ w_data1669w[1])), (w_anode2071w[0] & w_data1669w[0]), w_anode2049w[3]},
w_anode2081w = {(w_anode2081w[2] & (~ w_data1669w[2])), (w_anode2081w[1] & w_data1669w[1]), (w_anode2081w[0] & (~ w_data1669w[0])), w_anode2049w[3]},
w_anode2091w = {(w_anode2091w[2] & (~ w_data1669w[2])), (w_anode2091w[1] & w_data1669w[1]), (w_anode2091w[0] & w_data1669w[0]), w_anode2049w[3]},
w_anode2101w = {(w_anode2101w[2] & w_data1669w[2]), (w_anode2101w[1] & (~ w_data1669w[1])), (w_anode2101w[0] & (~ w_data1669w[0])), w_anode2049w[3]},
w_anode2111w = {(w_anode2111w[2] & w_data1669w[2]), (w_anode2111w[1] & (~ w_data1669w[1])), (w_anode2111w[0] & w_data1669w[0]), w_anode2049w[3]},
w_anode2121w = {(w_anode2121w[2] & w_data1669w[2]), (w_anode2121w[1] & w_data1669w[1]), (w_anode2121w[0] & (~ w_data1669w[0])), w_anode2049w[3]},
w_anode2131w = {(w_anode2131w[2] & w_data1669w[2]), (w_anode2131w[1] & w_data1669w[1]), (w_anode2131w[0] & w_data1669w[0]), w_anode2049w[3]},
w_anode2142w = {(w_anode2142w[2] & data_wire[5]), (w_anode2142w[1] & (~ data_wire[4])), (w_anode2142w[0] & data_wire[3]), enable_wire2},
w_anode2153w = {(w_anode2153w[2] & (~ w_data1669w[2])), (w_anode2153w[1] & (~ w_data1669w[1])), (w_anode2153w[0] & (~ w_data1669w[0])), w_anode2142w[3]},
w_anode2164w = {(w_anode2164w[2] & (~ w_data1669w[2])), (w_anode2164w[1] & (~ w_data1669w[1])), (w_anode2164w[0] & w_data1669w[0]), w_anode2142w[3]},
w_anode2174w = {(w_anode2174w[2] & (~ w_data1669w[2])), (w_anode2174w[1] & w_data1669w[1]), (w_anode2174w[0] & (~ w_data1669w[0])), w_anode2142w[3]},
w_anode2184w = {(w_anode2184w[2] & (~ w_data1669w[2])), (w_anode2184w[1] & w_data1669w[1]), (w_anode2184w[0] & w_data1669w[0]), w_anode2142w[3]},
w_anode2194w = {(w_anode2194w[2] & w_data1669w[2]), (w_anode2194w[1] & (~ w_data1669w[1])), (w_anode2194w[0] & (~ w_data1669w[0])), w_anode2142w[3]},
w_anode2204w = {(w_anode2204w[2] & w_data1669w[2]), (w_anode2204w[1] & (~ w_data1669w[1])), (w_anode2204w[0] & w_data1669w[0]), w_anode2142w[3]},
w_anode2214w = {(w_anode2214w[2] & w_data1669w[2]), (w_anode2214w[1] & w_data1669w[1]), (w_anode2214w[0] & (~ w_data1669w[0])), w_anode2142w[3]},
w_anode2224w = {(w_anode2224w[2] & w_data1669w[2]), (w_anode2224w[1] & w_data1669w[1]), (w_anode2224w[0] & w_data1669w[0]), w_anode2142w[3]},
w_anode2235w = {(w_anode2235w[2] & data_wire[5]), (w_anode2235w[1] & data_wire[4]), (w_anode2235w[0] & (~ data_wire[3])), enable_wire2},
w_anode2246w = {(w_anode2246w[2] & (~ w_data1669w[2])), (w_anode2246w[1] & (~ w_data1669w[1])), (w_anode2246w[0] & (~ w_data1669w[0])), w_anode2235w[3]},
w_anode2257w = {(w_anode2257w[2] & (~ w_data1669w[2])), (w_anode2257w[1] & (~ w_data1669w[1])), (w_anode2257w[0] & w_data1669w[0]), w_anode2235w[3]},
w_anode2267w = {(w_anode2267w[2] & (~ w_data1669w[2])), (w_anode2267w[1] & w_data1669w[1]), (w_anode2267w[0] & (~ w_data1669w[0])), w_anode2235w[3]},
w_anode2277w = {(w_anode2277w[2] & (~ w_data1669w[2])), (w_anode2277w[1] & w_data1669w[1]), (w_anode2277w[0] & w_data1669w[0]), w_anode2235w[3]},
w_anode2287w = {(w_anode2287w[2] & w_data1669w[2]), (w_anode2287w[1] & (~ w_data1669w[1])), (w_anode2287w[0] & (~ w_data1669w[0])), w_anode2235w[3]},
w_anode2297w = {(w_anode2297w[2] & w_data1669w[2]), (w_anode2297w[1] & (~ w_data1669w[1])), (w_anode2297w[0] & w_data1669w[0]), w_anode2235w[3]},
w_anode2307w = {(w_anode2307w[2] & w_data1669w[2]), (w_anode2307w[1] & w_data1669w[1]), (w_anode2307w[0] & (~ w_data1669w[0])), w_anode2235w[3]},
w_anode2317w = {(w_anode2317w[2] & w_data1669w[2]), (w_anode2317w[1] & w_data1669w[1]), (w_anode2317w[0] & w_data1669w[0]), w_anode2235w[3]},
w_anode2328w = {(w_anode2328w[2] & data_wire[5]), (w_anode2328w[1] & data_wire[4]), (w_anode2328w[0] & data_wire[3]), enable_wire2},
w_anode2339w = {(w_anode2339w[2] & (~ w_data1669w[2])), (w_anode2339w[1] & (~ w_data1669w[1])), (w_anode2339w[0] & (~ w_data1669w[0])), w_anode2328w[3]},
w_anode2350w = {(w_anode2350w[2] & (~ w_data1669w[2])), (w_anode2350w[1] & (~ w_data1669w[1])), (w_anode2350w[0] & w_data1669w[0]), w_anode2328w[3]},
w_anode2360w = {(w_anode2360w[2] & (~ w_data1669w[2])), (w_anode2360w[1] & w_data1669w[1]), (w_anode2360w[0] & (~ w_data1669w[0])), w_anode2328w[3]},
w_anode2370w = {(w_anode2370w[2] & (~ w_data1669w[2])), (w_anode2370w[1] & w_data1669w[1]), (w_anode2370w[0] & w_data1669w[0]), w_anode2328w[3]},
w_anode2380w = {(w_anode2380w[2] & w_data1669w[2]), (w_anode2380w[1] & (~ w_data1669w[1])), (w_anode2380w[0] & (~ w_data1669w[0])), w_anode2328w[3]},
w_anode2390w = {(w_anode2390w[2] & w_data1669w[2]), (w_anode2390w[1] & (~ w_data1669w[1])), (w_anode2390w[0] & w_data1669w[0]), w_anode2328w[3]},
w_anode2400w = {(w_anode2400w[2] & w_data1669w[2]), (w_anode2400w[1] & w_data1669w[1]), (w_anode2400w[0] & (~ w_data1669w[0])), w_anode2328w[3]},
w_anode2410w = {(w_anode2410w[2] & w_data1669w[2]), (w_anode2410w[1] & w_data1669w[1]), (w_anode2410w[0] & w_data1669w[0]), w_anode2328w[3]},
w_anode912w = {(w_anode912w[2] & (~ data_wire[5])), (w_anode912w[1] & (~ data_wire[4])), (w_anode912w[0] & (~ data_wire[3])), enable_wire1},
w_anode929w = {(w_anode929w[2] & (~ w_data910w[2])), (w_anode929w[1] & (~ w_data910w[1])), (w_anode929w[0] & (~ w_data910w[0])), w_anode912w[3]},
w_anode946w = {(w_anode946w[2] & (~ w_data910w[2])), (w_anode946w[1] & (~ w_data910w[1])), (w_anode946w[0] & w_data910w[0]), w_anode912w[3]},
w_anode956w = {(w_anode956w[2] & (~ w_data910w[2])), (w_anode956w[1] & w_data910w[1]), (w_anode956w[0] & (~ w_data910w[0])), w_anode912w[3]},
w_anode966w = {(w_anode966w[2] & (~ w_data910w[2])), (w_anode966w[1] & w_data910w[1]), (w_anode966w[0] & w_data910w[0]), w_anode912w[3]},
w_anode976w = {(w_anode976w[2] & w_data910w[2]), (w_anode976w[1] & (~ w_data910w[1])), (w_anode976w[0] & (~ w_data910w[0])), w_anode912w[3]},
w_anode986w = {(w_anode986w[2] & w_data910w[2]), (w_anode986w[1] & (~ w_data910w[1])), (w_anode986w[0] & w_data910w[0]), w_anode912w[3]},
w_anode996w = {(w_anode996w[2] & w_data910w[2]), (w_anode996w[1] & w_data910w[1]), (w_anode996w[0] & (~ w_data910w[0])), w_anode912w[3]},
w_data1669w = data_wire[2:0],
w_data910w = data_wire[2:0];
endmodule |
module alt_mem_ddrx_ecc_decoder_64_altecc_decoder
(
clk,
reset_n,
data,
err_corrected,
err_detected,
err_fatal,
err_sbe,
q) /* synthesis synthesis_clearbox=1 */;
input clk;
input reset_n;
input [71:0] data;
output err_corrected;
output err_detected;
output err_fatal;
output err_sbe;
output [63:0] q;
parameter CFG_ECC_DECODER_REG = 0;
wire [127:0] wire_error_bit_decoder_eq;
wire wire_mux21_0_dataout;
wire wire_mux21_1_dataout;
wire wire_mux21_10_dataout;
wire wire_mux21_11_dataout;
wire wire_mux21_12_dataout;
wire wire_mux21_13_dataout;
wire wire_mux21_14_dataout;
wire wire_mux21_15_dataout;
wire wire_mux21_16_dataout;
wire wire_mux21_17_dataout;
wire wire_mux21_18_dataout;
wire wire_mux21_19_dataout;
wire wire_mux21_2_dataout;
wire wire_mux21_20_dataout;
wire wire_mux21_21_dataout;
wire wire_mux21_22_dataout;
wire wire_mux21_23_dataout;
wire wire_mux21_24_dataout;
wire wire_mux21_25_dataout;
wire wire_mux21_26_dataout;
wire wire_mux21_27_dataout;
wire wire_mux21_28_dataout;
wire wire_mux21_29_dataout;
wire wire_mux21_3_dataout;
wire wire_mux21_30_dataout;
wire wire_mux21_31_dataout;
wire wire_mux21_32_dataout;
wire wire_mux21_33_dataout;
wire wire_mux21_34_dataout;
wire wire_mux21_35_dataout;
wire wire_mux21_36_dataout;
wire wire_mux21_37_dataout;
wire wire_mux21_38_dataout;
wire wire_mux21_39_dataout;
wire wire_mux21_4_dataout;
wire wire_mux21_40_dataout;
wire wire_mux21_41_dataout;
wire wire_mux21_42_dataout;
wire wire_mux21_43_dataout;
wire wire_mux21_44_dataout;
wire wire_mux21_45_dataout;
wire wire_mux21_46_dataout;
wire wire_mux21_47_dataout;
wire wire_mux21_48_dataout;
wire wire_mux21_49_dataout;
wire wire_mux21_5_dataout;
wire wire_mux21_50_dataout;
wire wire_mux21_51_dataout;
wire wire_mux21_52_dataout;
wire wire_mux21_53_dataout;
wire wire_mux21_54_dataout;
wire wire_mux21_55_dataout;
wire wire_mux21_56_dataout;
wire wire_mux21_57_dataout;
wire wire_mux21_58_dataout;
wire wire_mux21_59_dataout;
wire wire_mux21_6_dataout;
wire wire_mux21_60_dataout;
wire wire_mux21_61_dataout;
wire wire_mux21_62_dataout;
wire wire_mux21_63_dataout;
wire wire_mux21_7_dataout;
wire wire_mux21_8_dataout;
wire wire_mux21_9_dataout;
wire data_bit;
wire [63:0] data_t;
wire [71:0] data_wire;
wire [127:0] decode_output;
wire err_corrected_wire;
wire err_detected_wire;
wire err_fatal_wire;
wire [35:0] parity_01_wire;
wire [17:0] parity_02_wire;
wire [8:0] parity_03_wire;
wire [3:0] parity_04_wire;
wire [1:0] parity_05_wire;
wire [30:0] parity_06_wire;
wire [6:0] parity_07_wire;
wire parity_bit;
wire [70:0] parity_final_wire;
wire [6:0] parity_t;
wire [63:0] q_wire;
wire syn_bit;
wire syn_e;
wire [5:0] syn_t;
wire [7:0] syndrome_wire;
reg [7:0] syndrome;
reg [71:0] data_reg;
generate
if (CFG_ECC_DECODER_REG == 1)
begin
always @ (posedge clk or negedge reset_n)
begin
if (!reset_n)
begin
syndrome <= {8{1'b0}};
data_reg <= {72{1'b0}};
end else
begin
syndrome <= syndrome_wire;
data_reg <= data_wire;
end
end
end else
begin
always @ (*)
begin
syndrome = syndrome_wire;
data_reg = data_wire;
end
end
endgenerate
alt_mem_ddrx_ecc_decoder_64_decode error_bit_decoder
(
.data(syndrome[6:0]),
.eq(wire_error_bit_decoder_eq));
assign wire_mux21_0_dataout = (syndrome[7] == 1'b1) ? (decode_output[3] ^ data_reg[0]) : data_reg[0];
assign wire_mux21_1_dataout = (syndrome[7] == 1'b1) ? (decode_output[5] ^ data_reg[1]) : data_reg[1];
assign wire_mux21_10_dataout = (syndrome[7] == 1'b1) ? (decode_output[15] ^ data_reg[10]) : data_reg[10];
assign wire_mux21_11_dataout = (syndrome[7] == 1'b1) ? (decode_output[17] ^ data_reg[11]) : data_reg[11];
assign wire_mux21_12_dataout = (syndrome[7] == 1'b1) ? (decode_output[18] ^ data_reg[12]) : data_reg[12];
assign wire_mux21_13_dataout = (syndrome[7] == 1'b1) ? (decode_output[19] ^ data_reg[13]) : data_reg[13];
assign wire_mux21_14_dataout = (syndrome[7] == 1'b1) ? (decode_output[20] ^ data_reg[14]) : data_reg[14];
assign wire_mux21_15_dataout = (syndrome[7] == 1'b1) ? (decode_output[21] ^ data_reg[15]) : data_reg[15];
assign wire_mux21_16_dataout = (syndrome[7] == 1'b1) ? (decode_output[22] ^ data_reg[16]) : data_reg[16];
assign wire_mux21_17_dataout = (syndrome[7] == 1'b1) ? (decode_output[23] ^ data_reg[17]) : data_reg[17];
assign wire_mux21_18_dataout = (syndrome[7] == 1'b1) ? (decode_output[24] ^ data_reg[18]) : data_reg[18];
assign wire_mux21_19_dataout = (syndrome[7] == 1'b1) ? (decode_output[25] ^ data_reg[19]) : data_reg[19];
assign wire_mux21_2_dataout = (syndrome[7] == 1'b1) ? (decode_output[6] ^ data_reg[2]) : data_reg[2];
assign wire_mux21_20_dataout = (syndrome[7] == 1'b1) ? (decode_output[26] ^ data_reg[20]) : data_reg[20];
assign wire_mux21_21_dataout = (syndrome[7] == 1'b1) ? (decode_output[27] ^ data_reg[21]) : data_reg[21];
assign wire_mux21_22_dataout = (syndrome[7] == 1'b1) ? (decode_output[28] ^ data_reg[22]) : data_reg[22];
assign wire_mux21_23_dataout = (syndrome[7] == 1'b1) ? (decode_output[29] ^ data_reg[23]) : data_reg[23];
assign wire_mux21_24_dataout = (syndrome[7] == 1'b1) ? (decode_output[30] ^ data_reg[24]) : data_reg[24];
assign wire_mux21_25_dataout = (syndrome[7] == 1'b1) ? (decode_output[31] ^ data_reg[25]) : data_reg[25];
assign wire_mux21_26_dataout = (syndrome[7] == 1'b1) ? (decode_output[33] ^ data_reg[26]) : data_reg[26];
assign wire_mux21_27_dataout = (syndrome[7] == 1'b1) ? (decode_output[34] ^ data_reg[27]) : data_reg[27];
assign wire_mux21_28_dataout = (syndrome[7] == 1'b1) ? (decode_output[35] ^ data_reg[28]) : data_reg[28];
assign wire_mux21_29_dataout = (syndrome[7] == 1'b1) ? (decode_output[36] ^ data_reg[29]) : data_reg[29];
assign wire_mux21_3_dataout = (syndrome[7] == 1'b1) ? (decode_output[7] ^ data_reg[3]) : data_reg[3];
assign wire_mux21_30_dataout = (syndrome[7] == 1'b1) ? (decode_output[37] ^ data_reg[30]) : data_reg[30];
assign wire_mux21_31_dataout = (syndrome[7] == 1'b1) ? (decode_output[38] ^ data_reg[31]) : data_reg[31];
assign wire_mux21_32_dataout = (syndrome[7] == 1'b1) ? (decode_output[39] ^ data_reg[32]) : data_reg[32];
assign wire_mux21_33_dataout = (syndrome[7] == 1'b1) ? (decode_output[40] ^ data_reg[33]) : data_reg[33];
assign wire_mux21_34_dataout = (syndrome[7] == 1'b1) ? (decode_output[41] ^ data_reg[34]) : data_reg[34];
assign wire_mux21_35_dataout = (syndrome[7] == 1'b1) ? (decode_output[42] ^ data_reg[35]) : data_reg[35];
assign wire_mux21_36_dataout = (syndrome[7] == 1'b1) ? (decode_output[43] ^ data_reg[36]) : data_reg[36];
assign wire_mux21_37_dataout = (syndrome[7] == 1'b1) ? (decode_output[44] ^ data_reg[37]) : data_reg[37];
assign wire_mux21_38_dataout = (syndrome[7] == 1'b1) ? (decode_output[45] ^ data_reg[38]) : data_reg[38];
assign wire_mux21_39_dataout = (syndrome[7] == 1'b1) ? (decode_output[46] ^ data_reg[39]) : data_reg[39];
assign wire_mux21_4_dataout = (syndrome[7] == 1'b1) ? (decode_output[9] ^ data_reg[4]) : data_reg[4];
assign wire_mux21_40_dataout = (syndrome[7] == 1'b1) ? (decode_output[47] ^ data_reg[40]) : data_reg[40];
assign wire_mux21_41_dataout = (syndrome[7] == 1'b1) ? (decode_output[48] ^ data_reg[41]) : data_reg[41];
assign wire_mux21_42_dataout = (syndrome[7] == 1'b1) ? (decode_output[49] ^ data_reg[42]) : data_reg[42];
assign wire_mux21_43_dataout = (syndrome[7] == 1'b1) ? (decode_output[50] ^ data_reg[43]) : data_reg[43];
assign wire_mux21_44_dataout = (syndrome[7] == 1'b1) ? (decode_output[51] ^ data_reg[44]) : data_reg[44];
assign wire_mux21_45_dataout = (syndrome[7] == 1'b1) ? (decode_output[52] ^ data_reg[45]) : data_reg[45];
assign wire_mux21_46_dataout = (syndrome[7] == 1'b1) ? (decode_output[53] ^ data_reg[46]) : data_reg[46];
assign wire_mux21_47_dataout = (syndrome[7] == 1'b1) ? (decode_output[54] ^ data_reg[47]) : data_reg[47];
assign wire_mux21_48_dataout = (syndrome[7] == 1'b1) ? (decode_output[55] ^ data_reg[48]) : data_reg[48];
assign wire_mux21_49_dataout = (syndrome[7] == 1'b1) ? (decode_output[56] ^ data_reg[49]) : data_reg[49];
assign wire_mux21_5_dataout = (syndrome[7] == 1'b1) ? (decode_output[10] ^ data_reg[5]) : data_reg[5];
assign wire_mux21_50_dataout = (syndrome[7] == 1'b1) ? (decode_output[57] ^ data_reg[50]) : data_reg[50];
assign wire_mux21_51_dataout = (syndrome[7] == 1'b1) ? (decode_output[58] ^ data_reg[51]) : data_reg[51];
assign wire_mux21_52_dataout = (syndrome[7] == 1'b1) ? (decode_output[59] ^ data_reg[52]) : data_reg[52];
assign wire_mux21_53_dataout = (syndrome[7] == 1'b1) ? (decode_output[60] ^ data_reg[53]) : data_reg[53];
assign wire_mux21_54_dataout = (syndrome[7] == 1'b1) ? (decode_output[61] ^ data_reg[54]) : data_reg[54];
assign wire_mux21_55_dataout = (syndrome[7] == 1'b1) ? (decode_output[62] ^ data_reg[55]) : data_reg[55];
assign wire_mux21_56_dataout = (syndrome[7] == 1'b1) ? (decode_output[63] ^ data_reg[56]) : data_reg[56];
assign wire_mux21_57_dataout = (syndrome[7] == 1'b1) ? (decode_output[65] ^ data_reg[57]) : data_reg[57];
assign wire_mux21_58_dataout = (syndrome[7] == 1'b1) ? (decode_output[66] ^ data_reg[58]) : data_reg[58];
assign wire_mux21_59_dataout = (syndrome[7] == 1'b1) ? (decode_output[67] ^ data_reg[59]) : data_reg[59];
assign wire_mux21_6_dataout = (syndrome[7] == 1'b1) ? (decode_output[11] ^ data_reg[6]) : data_reg[6];
assign wire_mux21_60_dataout = (syndrome[7] == 1'b1) ? (decode_output[68] ^ data_reg[60]) : data_reg[60];
assign wire_mux21_61_dataout = (syndrome[7] == 1'b1) ? (decode_output[69] ^ data_reg[61]) : data_reg[61];
assign wire_mux21_62_dataout = (syndrome[7] == 1'b1) ? (decode_output[70] ^ data_reg[62]) : data_reg[62];
assign wire_mux21_63_dataout = (syndrome[7] == 1'b1) ? (decode_output[71] ^ data_reg[63]) : data_reg[63];
assign wire_mux21_7_dataout = (syndrome[7] == 1'b1) ? (decode_output[12] ^ data_reg[7]) : data_reg[7];
assign wire_mux21_8_dataout = (syndrome[7] == 1'b1) ? (decode_output[13] ^ data_reg[8]) : data_reg[8];
assign wire_mux21_9_dataout = (syndrome[7] == 1'b1) ? (decode_output[14] ^ data_reg[9]) : data_reg[9];
assign
data_bit = data_t[63],
data_t = {(data_t[62] | decode_output[71]), (data_t[61] | decode_output[70]), (data_t[60] | decode_output[69]), (data_t[59] | decode_output[68]), (data_t[58] | decode_output[67]), (data_t[57] | decode_output[66]), (data_t[56] | decode_output[65]), (data_t[55] | decode_output[63]), (data_t[54] | decode_output[62]), (data_t[53] | decode_output[61]), (data_t[52] | decode_output[60]), (data_t[51] | decode_output[59]), (data_t[50] | decode_output[58]), (data_t[49] | decode_output[57]), (data_t[48] | decode_output[56]), (data_t[47] | decode_output[55]), (data_t[46] | decode_output[54]), (data_t[45] | decode_output[53]), (data_t[44] | decode_output[52]), (data_t[43] | decode_output[51]), (data_t[42] | decode_output[50]), (data_t[41] | decode_output[49]), (data_t[40] | decode_output[48]), (data_t[39] | decode_output[47]), (data_t[38] | decode_output[46]), (data_t[37] | decode_output[45]), (data_t[36] | decode_output[44]), (data_t[35] | decode_output[43]), (data_t[34] | decode_output[42]), (data_t[33] | decode_output[41]), (data_t[32] | decode_output[40]), (data_t[31] | decode_output[39]), (data_t[30] | decode_output[38]), (data_t[29] | decode_output[37]), (data_t[28] | decode_output[36]), (data_t[27] | decode_output[35]), (data_t[26] | decode_output[34]), (data_t[25] | decode_output[33]), (data_t[24] | decode_output[31]), (data_t[23] | decode_output[30]), (data_t[22] | decode_output[29]), (data_t[21] | decode_output[28]), (data_t[20] | decode_output[27]), (data_t[19] | decode_output[26]), (data_t[18] | decode_output[25]), (data_t[17] | decode_output[24]), (data_t[16] | decode_output[23]), (data_t[15] | decode_output[22]), (data_t[14] | decode_output[21]), (data_t[13] | decode_output[20]), (data_t[12] | decode_output[19]), (data_t[11] | decode_output[18]), (data_t[10] | decode_output[17]), (data_t[9] | decode_output[15]), (data_t[8] | decode_output[14]), (data_t[7] | decode_output[13]), (data_t[6] | decode_output[12]), (data_t[5] | decode_output[11]), (data_t[4] | decode_output[10]), (data_t[3] | decode_output[9]), (data_t[2]
| decode_output[7]), (data_t[1] | decode_output[6]), (data_t[0] | decode_output[5]), decode_output[3]},
data_wire = data,
decode_output = wire_error_bit_decoder_eq,
err_corrected = err_corrected_wire,
err_corrected_wire = ((syn_bit & syn_e) & data_bit),
err_detected = err_detected_wire,
err_detected_wire = (syn_bit & (~ (syn_e & parity_bit))),
err_fatal = err_fatal_wire,
err_sbe = syn_e,
err_fatal_wire = (err_detected_wire & (~ err_corrected_wire)),
parity_01_wire = {(data_wire[63] ^ parity_01_wire[34]), (data_wire[61] ^ parity_01_wire[33]), (data_wire[59] ^ parity_01_wire[32]), (data_wire[57] ^ parity_01_wire[31]), (data_wire[56] ^ parity_01_wire[30]), (data_wire[54] ^ parity_01_wire[29]), (data_wire[52] ^ parity_01_wire[28]), (data_wire[50] ^ parity_01_wire[27]), (data_wire[48] ^ parity_01_wire[26]), (data_wire[46] ^ parity_01_wire[25]), (data_wire[44] ^ parity_01_wire[24]), (data_wire[42] ^ parity_01_wire[23]), (data_wire[40] ^ parity_01_wire[22]), (data_wire[38] ^ parity_01_wire[21]), (data_wire[36] ^ parity_01_wire[20]), (data_wire[34] ^ parity_01_wire[19]), (data_wire[32] ^ parity_01_wire[18]), (data_wire[30] ^ parity_01_wire[17]), (data_wire[28] ^ parity_01_wire[16]), (data_wire[26] ^ parity_01_wire[15]), (data_wire[25] ^ parity_01_wire[14]), (data_wire[23] ^ parity_01_wire[13]), (data_wire[21] ^ parity_01_wire[12]), (data_wire[19] ^ parity_01_wire[11]), (data_wire[17] ^ parity_01_wire[10]), (data_wire[15] ^ parity_01_wire[9]), (data_wire[13] ^ parity_01_wire[8]), (data_wire[11] ^ parity_01_wire[7]), (data_wire[10] ^ parity_01_wire[6]), (data_wire[8] ^ parity_01_wire[5]), (data_wire[6] ^ parity_01_wire[4]), (data_wire[4] ^ parity_01_wire[3]), (data_wire[3] ^ parity_01_wire[2]), (data_wire[1] ^ parity_01_wire[1]), (data_wire[0] ^ parity_01_wire[0]), data_wire[64]},
parity_02_wire = {((data_wire[62] ^ data_wire[63]) ^ parity_02_wire[16]), ((data_wire[58] ^ data_wire[59]) ^ parity_02_wire[15]), ((data_wire[55] ^ data_wire[56]) ^ parity_02_wire[14]), ((data_wire[51] ^ data_wire[52]) ^ parity_02_wire[13]), ((data_wire[47] ^ data_wire[48]) ^ parity_02_wire[12]), ((data_wire[43] ^ data_wire[44]) ^ parity_02_wire[11]), ((data_wire[39] ^ data_wire[40]) ^ parity_02_wire[10]), ((data_wire[35] ^ data_wire[36]) ^ parity_02_wire[9]), ((data_wire[31] ^ data_wire[32]) ^ parity_02_wire[8]), ((data_wire[27] ^ data_wire[28]) ^ parity_02_wire[7]), ((data_wire[24] ^ data_wire[25]) ^ parity_02_wire[6]), ((data_wire[20] ^ data_wire[21]) ^ parity_02_wire[5]), ((data_wire[16] ^ data_wire[17]) ^ parity_02_wire[4]), ((data_wire[12] ^ data_wire[13]) ^ parity_02_wire[3]), ((data_wire[9] ^ data_wire[10]) ^ parity_02_wire[2]), ((data_wire[5] ^ data_wire[6]) ^ parity_02_wire[1]), ((data_wire[2] ^ data_wire[3]) ^ parity_02_wire[0]), (data_wire[65] ^ data_wire[0])},
parity_03_wire = {((((data_wire[60] ^ data_wire[61]) ^ data_wire[62]) ^ data_wire[63]) ^ parity_03_wire[7]), ((((data_wire[53] ^ data_wire[54]) ^ data_wire[55]) ^ data_wire[56]) ^ parity_03_wire[6]), ((((data_wire[45] ^ data_wire[46]) ^ data_wire[47]) ^ data_wire[48]) ^ parity_03_wire[5]), ((((data_wire[37] ^ data_wire[38]) ^ data_wire[39]) ^ data_wire[40]) ^ parity_03_wire[4]), ((((data_wire[29] ^ data_wire[30]) ^ data_wire[31]) ^ data_wire[32]) ^ parity_03_wire[3]), ((((data_wire[22] ^ data_wire[23]) ^ data_wire[24]) ^ data_wire[25]) ^ parity_03_wire[2]), ((((data_wire[14] ^ data_wire[15]) ^ data_wire[16]) ^ data_wire[17]) ^ parity_03_wire[1]), ((((data_wire[7] ^ data_wire[8]) ^ data_wire[9]) ^ data_wire[10]) ^ parity_03_wire[0]), (((data_wire[66] ^ data_wire[1]) ^ data_wire[2]) ^ data_wire[3])},
parity_04_wire = {((((((((data_wire[49] ^ data_wire[50]) ^ data_wire[51]) ^ data_wire[52]) ^ data_wire[53]) ^ data_wire[54]) ^ data_wire[55]) ^ data_wire[56]) ^ parity_04_wire[2]), ((((((((data_wire[33] ^ data_wire[34]) ^ data_wire[35]) ^ data_wire[36]) ^ data_wire[37]) ^ data_wire[38]) ^ data_wire[39]) ^ data_wire[40]) ^ parity_04_wire[1]), ((((((((data_wire[18] ^ data_wire[19]) ^ data_wire[20]) ^ data_wire[21]) ^ data_wire[22]) ^ data_wire[23]) ^ data_wire[24]) ^ data_wire[25]) ^ parity_04_wire[0]), (((((((data_wire[67] ^ data_wire[4]) ^ data_wire[5]) ^ data_wire[6]) ^ data_wire[7]) ^ data_wire[8]) ^ data_wire[9]) ^ data_wire[10])},
parity_05_wire = {((((((((((((((((data_wire[41] ^ data_wire[42]) ^ data_wire[43]) ^ data_wire[44]) ^ data_wire[45]) ^ data_wire[46]) ^ data_wire[47]) ^ data_wire[48]) ^ data_wire[49]) ^ data_wire[50]) ^ data_wire[51]) ^ data_wire[52]) ^ data_wire[53]) ^ data_wire[54]) ^ data_wire[55]) ^ data_wire[56]) ^ parity_05_wire[0]), (((((((((((((((data_wire[68] ^ data_wire[11]) ^ data_wire[12]) ^ data_wire[13]) ^ data_wire[14]) ^ data_wire[15]) ^ data_wire[16]) ^ data_wire[17]) ^ data_wire[18]) ^ data_wire[19]) ^ data_wire[20]) ^ data_wire[21]) ^ data_wire[22]) ^ data_wire[23]) ^ data_wire[24]) ^ data_wire[25])},
parity_06_wire = {(data_wire[56] ^ parity_06_wire[29]), (data_wire[55] ^ parity_06_wire[28]), (data_wire[54] ^ parity_06_wire[27]), (data_wire[53] ^ parity_06_wire[26]), (data_wire[52] ^ parity_06_wire[25]), (data_wire[51] ^ parity_06_wire[24]), (data_wire[50] ^ parity_06_wire[23]), (data_wire[49] ^ parity_06_wire[22]), (data_wire[48] ^ parity_06_wire[21]), (data_wire[47] ^ parity_06_wire[20]), (data_wire[46] ^ parity_06_wire[19]), (data_wire[45] ^ parity_06_wire[18]), (data_wire[44] ^ parity_06_wire[17]), (data_wire[43] ^ parity_06_wire[16]), (data_wire[42] ^ parity_06_wire[15]), (data_wire[41] ^ parity_06_wire[14]), (data_wire[40] ^ parity_06_wire[13]), (data_wire[39] ^ parity_06_wire[12]), (data_wire[38] ^ parity_06_wire[11]), (data_wire[37] ^ parity_06_wire[10]), (data_wire[36] ^ parity_06_wire[9]), (data_wire[35] ^ parity_06_wire[8]), (data_wire[34] ^ parity_06_wire[7]), (data_wire[33] ^ parity_06_wire[6]), (data_wire[32] ^ parity_06_wire[5]), (data_wire[31] ^ parity_06_wire[4]), (data_wire[30] ^ parity_06_wire[3]), (data_wire[29] ^ parity_06_wire[2]), (data_wire[28] ^ parity_06_wire[1]), (data_wire[27] ^ parity_06_wire[0]), (data_wire[69] ^ data_wire[26])},
parity_07_wire = {(data_wire[63] ^ parity_07_wire[5]), (data_wire[62] ^ parity_07_wire[4]), (data_wire[61] ^ parity_07_wire[3]), (data_wire[60] ^ parity_07_wire[2]), (data_wire[59] ^ parity_07_wire[1]), (data_wire[58] ^ parity_07_wire[0]), (data_wire[70] ^ data_wire[57])},
parity_bit = parity_t[6],
parity_final_wire = {(data_wire[70] ^ parity_final_wire[69]), (data_wire[69] ^ parity_final_wire[68]), (data_wire[68] ^ parity_final_wire[67]), (data_wire[67] ^ parity_final_wire[66]), (data_wire[66] ^ parity_final_wire[65]), (data_wire[65] ^ parity_final_wire[64]), (data_wire[64] ^ parity_final_wire[63]), (data_wire[63] ^ parity_final_wire[62]), (data_wire[62] ^ parity_final_wire[61]), (data_wire[61] ^ parity_final_wire[60]), (data_wire[60] ^ parity_final_wire[59]), (data_wire[59] ^ parity_final_wire[58]), (data_wire[58] ^ parity_final_wire[57]), (data_wire[57] ^ parity_final_wire[56]), (data_wire[56] ^ parity_final_wire[55]), (data_wire[55] ^ parity_final_wire[54]), (data_wire[54] ^ parity_final_wire[53]), (data_wire[53] ^ parity_final_wire[52]), (data_wire[52] ^ parity_final_wire[51]), (data_wire[51] ^ parity_final_wire[50]), (data_wire[50] ^ parity_final_wire[49]), (data_wire[49] ^ parity_final_wire[48]), (data_wire[48] ^ parity_final_wire[47]), (data_wire[47] ^ parity_final_wire[46]), (data_wire[46] ^ parity_final_wire[45]), (data_wire[45] ^ parity_final_wire[44]), (data_wire[44] ^ parity_final_wire[43]), (data_wire[43] ^ parity_final_wire[42]), (data_wire[42] ^ parity_final_wire[41]), (data_wire[41] ^ parity_final_wire[40]), (data_wire[40] ^ parity_final_wire[39]), (data_wire[39] ^ parity_final_wire[38]), (data_wire[38] ^ parity_final_wire[37]), (data_wire[37] ^ parity_final_wire[36]), (data_wire[36] ^ parity_final_wire[35]), (data_wire[35] ^ parity_final_wire[34]), (data_wire[34] ^ parity_final_wire[33]), (data_wire[33] ^ parity_final_wire[32]), (data_wire[32] ^ parity_final_wire[31]), (data_wire[31] ^ parity_final_wire[30]), (data_wire[30] ^ parity_final_wire[29]), (data_wire[29] ^ parity_final_wire[28]), (data_wire[28] ^ parity_final_wire[27]), (data_wire[27] ^ parity_final_wire[26]), (data_wire[26] ^ parity_final_wire[25]), (data_wire[25] ^ parity_final_wire[24]), (data_wire[24] ^ parity_final_wire[23]), (data_wire[23] ^ parity_final_wire[22]), (data_wire[22] ^ parity_final_wire[21]), (data_wire[21] ^
parity_final_wire[20]), (data_wire[20] ^ parity_final_wire[19]), (data_wire[19] ^ parity_final_wire[18]), (data_wire[18] ^ parity_final_wire[17]), (data_wire[17] ^ parity_final_wire[16]), (data_wire[16] ^ parity_final_wire[15]), (data_wire[15] ^ parity_final_wire[14]), (data_wire[14] ^ parity_final_wire[13]), (data_wire[13] ^ parity_final_wire[12]), (data_wire[12] ^ parity_final_wire[11]), (data_wire[11] ^ parity_final_wire[10]), (data_wire[10] ^ parity_final_wire[9]), (data_wire[9] ^ parity_final_wire[8]), (data_wire[8] ^ parity_final_wire[7]), (data_wire[7] ^ parity_final_wire[6]), (data_wire[6] ^ parity_final_wire[5]), (data_wire[5] ^ parity_final_wire[4]), (data_wire[4] ^ parity_final_wire[3]), (data_wire[3] ^ parity_final_wire[2]), (data_wire[2] ^ parity_final_wire[1]), (data_wire[1] ^ parity_final_wire[0]), (data_wire[71] ^ data_wire[0])},
parity_t = {(parity_t[5] | decode_output[64]), (parity_t[4] | decode_output[32]), (parity_t[3] | decode_output[16]), (parity_t[2] | decode_output[8]), (parity_t[1] | decode_output[4]), (parity_t[0] | decode_output[2]), decode_output[1]},
q = q_wire,
q_wire = {wire_mux21_63_dataout, wire_mux21_62_dataout, wire_mux21_61_dataout, wire_mux21_60_dataout, wire_mux21_59_dataout, wire_mux21_58_dataout, wire_mux21_57_dataout, wire_mux21_56_dataout, wire_mux21_55_dataout, wire_mux21_54_dataout, wire_mux21_53_dataout, wire_mux21_52_dataout, wire_mux21_51_dataout, wire_mux21_50_dataout, wire_mux21_49_dataout, wire_mux21_48_dataout, wire_mux21_47_dataout, wire_mux21_46_dataout, wire_mux21_45_dataout, wire_mux21_44_dataout, wire_mux21_43_dataout, wire_mux21_42_dataout, wire_mux21_41_dataout, wire_mux21_40_dataout, wire_mux21_39_dataout, wire_mux21_38_dataout, wire_mux21_37_dataout, wire_mux21_36_dataout, wire_mux21_35_dataout, wire_mux21_34_dataout, wire_mux21_33_dataout, wire_mux21_32_dataout, wire_mux21_31_dataout, wire_mux21_30_dataout, wire_mux21_29_dataout, wire_mux21_28_dataout, wire_mux21_27_dataout, wire_mux21_26_dataout, wire_mux21_25_dataout, wire_mux21_24_dataout, wire_mux21_23_dataout, wire_mux21_22_dataout, wire_mux21_21_dataout, wire_mux21_20_dataout, wire_mux21_19_dataout, wire_mux21_18_dataout, wire_mux21_17_dataout, wire_mux21_16_dataout, wire_mux21_15_dataout, wire_mux21_14_dataout, wire_mux21_13_dataout, wire_mux21_12_dataout, wire_mux21_11_dataout, wire_mux21_10_dataout, wire_mux21_9_dataout, wire_mux21_8_dataout, wire_mux21_7_dataout, wire_mux21_6_dataout, wire_mux21_5_dataout, wire_mux21_4_dataout, wire_mux21_3_dataout, wire_mux21_2_dataout, wire_mux21_1_dataout, wire_mux21_0_dataout},
syn_bit = syn_t[5],
syn_e = syndrome[7],
syn_t = {(syn_t[4] | syndrome[6]), (syn_t[3] | syndrome[5]), (syn_t[2] | syndrome[4]), (syn_t[1] | syndrome[3]), (syn_t[0] | syndrome[2]), (syndrome[0] | syndrome[1])},
syndrome_wire = {parity_final_wire[70], parity_07_wire[6], parity_06_wire[30], parity_05_wire[1], parity_04_wire[3], parity_03_wire[8], parity_02_wire[17], parity_01_wire[35]};
endmodule |
module alt_mem_ddrx_ecc_decoder_64
#(
parameter
CFG_ECC_DECODER_REG = 1
)
(
clk,
reset_n,
data,
err_corrected,
err_detected,
err_fatal,
err_sbe,
q)/* synthesis synthesis_clearbox = 1 */;
input clk;
input reset_n;
input [71:0] data;
output err_corrected;
output err_detected;
output err_fatal;
output err_sbe;
output [63:0] q;
wire sub_wire0;
wire sub_wire1;
wire sub_wire2;
wire sub_wire4;
wire [63:0] sub_wire3;
wire err_detected = sub_wire0;
wire err_fatal = sub_wire1;
wire err_corrected = sub_wire2;
wire err_sbe = sub_wire4;
wire [63:0] q = sub_wire3[63:0];
alt_mem_ddrx_ecc_decoder_64_altecc_decoder
# (
.CFG_ECC_DECODER_REG (CFG_ECC_DECODER_REG)
)
alt_mem_ddrx_ecc_decoder_64_altecc_decoder_component (
.clk (clk),
.reset_n (reset_n),
.data (data),
.err_detected (sub_wire0),
.err_fatal (sub_wire1),
.err_corrected (sub_wire2),
.err_sbe (sub_wire4),
.q (sub_wire3));
endmodule |
module sparc_exu_ecc_dec (/*AUTOARG*/
// Outputs
e,
// Inputs
q
) ;
input [6:0] q;
output [63:0] e;
assign e[0] = ~q[6] & ~q[5] & ~q[4] & ~q[3] & ~q[2] & q[1] & q[0];
assign e[1] = ~q[6] & ~q[5] & ~q[4] & ~q[3] & q[2] & ~q[1] & q[0];
assign e[2] = ~q[6] & ~q[5] & ~q[4] & ~q[3] & q[2] & q[1] & ~q[0];
assign e[3] = ~q[6] & ~q[5] & ~q[4] & ~q[3] & q[2] & q[1] & q[0];
assign e[4] = ~q[6] & ~q[5] & ~q[4] & q[3] & ~q[2] & ~q[1] & q[0];
assign e[5] = ~q[6] & ~q[5] & ~q[4] & q[3] & ~q[2] & q[1] & ~q[0];
assign e[6] = ~q[6] & ~q[5] & ~q[4] & q[3] & ~q[2] & q[1] & q[0];
assign e[7] = ~q[6] & ~q[5] & ~q[4] & q[3] & q[2] & ~q[1] & ~q[0];
assign e[8] = ~q[6] & ~q[5] & ~q[4] & q[3] & q[2] & ~q[1] & q[0];
assign e[9] = ~q[6] & ~q[5] & ~q[4] & q[3] & q[2] & q[1] & ~q[0];
assign e[10] = ~q[6] & ~q[5] & ~q[4] & q[3] & q[2] & q[1] & q[0];
assign e[11] = ~q[6] & ~q[5] & q[4] & ~q[3] & ~q[2] & ~q[1] & q[0];
assign e[12] = ~q[6] & ~q[5] & q[4] & ~q[3] & ~q[2] & q[1] & ~q[0];
assign e[13] = ~q[6] & ~q[5] & q[4] & ~q[3] & ~q[2] & q[1] & q[0];
assign e[14] = ~q[6] & ~q[5] & q[4] & ~q[3] & q[2] & ~q[1] & ~q[0];
assign e[15] = ~q[6] & ~q[5] & q[4] & ~q[3] & q[2] & ~q[1] & q[0];
assign e[16] = ~q[6] & ~q[5] & q[4] & ~q[3] & q[2] & q[1] & ~q[0];
assign e[17] = ~q[6] & ~q[5] & q[4] & ~q[3] & q[2] & q[1] & q[0];
assign e[18] = ~q[6] & ~q[5] & q[4] & q[3] & ~q[2] & ~q[1] & ~q[0];
assign e[19] = ~q[6] & ~q[5] & q[4] & q[3] & ~q[2] & ~q[1] & q[0];
assign e[20] = ~q[6] & ~q[5] & q[4] & q[3] & ~q[2] & q[1] & ~q[0];
assign e[21] = ~q[6] & ~q[5] & q[4] & q[3] & ~q[2] & q[1] & q[0];
assign e[22] = ~q[6] & ~q[5] & q[4] & q[3] & q[2] & ~q[1] & ~q[0];
assign e[23] = ~q[6] & ~q[5] & q[4] & q[3] & q[2] & ~q[1] & q[0];
assign e[24] = ~q[6] & ~q[5] & q[4] & q[3] & q[2] & q[1] & ~q[0];
assign e[25] = ~q[6] & ~q[5] & q[4] & q[3] & q[2] & q[1] & q[0];
assign e[26] = ~q[6] & q[5] & ~q[4] & ~q[3] & ~q[2] & ~q[1] & q[0];
assign e[27] = ~q[6] & q[5] & ~q[4] & ~q[3] & ~q[2] & q[1] & ~q[0];
assign e[28] = ~q[6] & q[5] & ~q[4] & ~q[3] & ~q[2] & q[1] & q[0];
assign e[29] = ~q[6] & q[5] & ~q[4] & ~q[3] & q[2] & ~q[1] & ~q[0];
assign e[30] = ~q[6] & q[5] & ~q[4] & ~q[3] & q[2] & ~q[1] & q[0];
assign e[31] = ~q[6] & q[5] & ~q[4] & ~q[3] & q[2] & q[1] & ~q[0];
assign e[32] = ~q[6] & q[5] & ~q[4] & ~q[3] & q[2] & q[1] & q[0];
assign e[33] = ~q[6] & q[5] & ~q[4] & q[3] & ~q[2] & ~q[1] & ~q[0];
assign e[34] = ~q[6] & q[5] & ~q[4] & q[3] & ~q[2] & ~q[1] & q[0];
assign e[35] = ~q[6] & q[5] & ~q[4] & q[3] & ~q[2] & q[1] & ~q[0];
assign e[36] = ~q[6] & q[5] & ~q[4] & q[3] & ~q[2] & q[1] & q[0];
assign e[37] = ~q[6] & q[5] & ~q[4] & q[3] & q[2] & ~q[1] & ~q[0];
assign e[38] = ~q[6] & q[5] & ~q[4] & q[3] & q[2] & ~q[1] & q[0];
assign e[39] = ~q[6] & q[5] & ~q[4] & q[3] & q[2] & q[1] & ~q[0];
assign e[40] = ~q[6] & q[5] & ~q[4] & q[3] & q[2] & q[1] & q[0];
assign e[41] = ~q[6] & q[5] & q[4] & ~q[3] & ~q[2] & ~q[1] & ~q[0];
assign e[42] = ~q[6] & q[5] & q[4] & ~q[3] & ~q[2] & ~q[1] & q[0];
assign e[43] = ~q[6] & q[5] & q[4] & ~q[3] & ~q[2] & q[1] & ~q[0];
assign e[44] = ~q[6] & q[5] & q[4] & ~q[3] & ~q[2] & q[1] & q[0];
assign e[45] = ~q[6] & q[5] & q[4] & ~q[3] & q[2] & ~q[1] & ~q[0];
assign e[46] = ~q[6] & q[5] & q[4] & ~q[3] & q[2] & ~q[1] & q[0];
assign e[47] = ~q[6] & q[5] & q[4] & ~q[3] & q[2] & q[1] & ~q[0];
assign e[48] = ~q[6] & q[5] & q[4] & ~q[3] & q[2] & q[1] & q[0];
assign e[49] = ~q[6] & q[5] & q[4] & q[3] & ~q[2] & ~q[1] & ~q[0];
assign e[50] = ~q[6] & q[5] & q[4] & q[3] & ~q[2] & ~q[1] & q[0];
assign e[51] = ~q[6] & q[5] & q[4] & q[3] & ~q[2] & q[1] & ~q[0];
assign e[52] = ~q[6] & q[5] & q[4] & q[3] & ~q[2] & q[1] & q[0];
assign e[53] = ~q[6] & q[5] & q[4] & q[3] & q[2] & ~q[1] & ~q[0];
assign e[54] = ~q[6] & q[5] & q[4] & q[3] & q[2] & ~q[1] & q[0];
assign e[55] = ~q[6] & q[5] & q[4] & q[3] & q[2] & q[1] & ~q[0];
assign e[56] = ~q[6] & q[5] & q[4] & q[3] & q[2] & q[1] & q[0];
assign e[57] = q[6] & ~q[5] & ~q[4] & ~q[3] & ~q[2] & ~q[1] & q[0];
assign e[58] = q[6] & ~q[5] & ~q[4] & ~q[3] & ~q[2] & q[1] & ~q[0];
assign e[59] = q[6] & ~q[5] & ~q[4] & ~q[3] & ~q[2] & q[1] & q[0];
assign e[60] = q[6] & ~q[5] & ~q[4] & ~q[3] & q[2] & ~q[1] & ~q[0];
assign e[61] = q[6] & ~q[5] & ~q[4] & ~q[3] & q[2] & ~q[1] & q[0];
assign e[62] = q[6] & ~q[5] & ~q[4] & ~q[3] & q[2] & q[1] & ~q[0];
assign e[63] = q[6] & ~q[5] & ~q[4] & ~q[3] & q[2] & q[1] & q[0];
endmodule |
module sky130_fd_sc_hs__o211ai (
Y ,
A1 ,
A2 ,
B1 ,
C1 ,
VPWR,
VGND
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
// Local signals
wire C1 or0_out ;
wire nand0_out_Y ;
wire u_vpwr_vgnd0_out_Y;
// Name Output Other arguments
or or0 (or0_out , A2, A1 );
nand nand0 (nand0_out_Y , C1, or0_out, B1 );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_Y, nand0_out_Y, VPWR, VGND);
buf buf0 (Y , u_vpwr_vgnd0_out_Y );
endmodule |
module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
fifo_depths_check ( .error(1'b1) );
end
endgenerate
altera_avalon_st_jtag_interface #(
.PURPOSE (1),
.UPSTREAM_FIFO_SIZE (0),
.DOWNSTREAM_FIFO_SIZE (64),
.MGMT_CHANNEL_WIDTH (-1),
.USE_PLI (0),
.PLI_PORT (50000)
) jtag_phy_embedded_in_jtag_master (
.clk (clk_clk), // clock.clk
.reset_n (~rst_controller_reset_out_reset), // clock_reset.reset_n
.source_data (jtag_phy_embedded_in_jtag_master_src_data), // src.data
.source_valid (jtag_phy_embedded_in_jtag_master_src_valid), // .valid
.sink_data (p2b_out_bytes_stream_data), // sink.data
.sink_valid (p2b_out_bytes_stream_valid), // .valid
.sink_ready (p2b_out_bytes_stream_ready), // .ready
.resetrequest (master_reset_reset) // resetrequest.reset
);
ik_swift_master_0_timing_adt timing_adt (
.clk (clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.in_valid (jtag_phy_embedded_in_jtag_master_src_valid), // in.valid
.in_data (jtag_phy_embedded_in_jtag_master_src_data), // .data
.out_valid (timing_adt_out_valid), // out.valid
.out_data (timing_adt_out_data), // .data
.out_ready (timing_adt_out_ready) // .ready
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (8),
.FIFO_DEPTH (64),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (0),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (3),
.USE_MEMORY_BLOCKS (1),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) fifo (
.clk (clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.in_data (timing_adt_out_data), // in.data
.in_valid (timing_adt_out_valid), // .valid
.in_ready (timing_adt_out_ready), // .ready
.out_data (fifo_out_data), // out.data
.out_valid (fifo_out_valid), // .valid
.out_ready (fifo_out_ready), // .ready
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_startofpacket (1'b0), // (terminated)
.in_endofpacket (1'b0), // (terminated)
.out_startofpacket (), // (terminated)
.out_endofpacket (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_avalon_st_bytes_to_packets #(
.CHANNEL_WIDTH (8),
.ENCODING (0)
) b2p (
.clk (clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // clk_reset.reset_n
.out_channel (b2p_out_packets_stream_channel), // out_packets_stream.channel
.out_ready (b2p_out_packets_stream_ready), // .ready
.out_valid (b2p_out_packets_stream_valid), // .valid
.out_data (b2p_out_packets_stream_data), // .data
.out_startofpacket (b2p_out_packets_stream_startofpacket), // .startofpacket
.out_endofpacket (b2p_out_packets_stream_endofpacket), // .endofpacket
.in_ready (fifo_out_ready), // in_bytes_stream.ready
.in_valid (fifo_out_valid), // .valid
.in_data (fifo_out_data) // .data
);
altera_avalon_st_packets_to_bytes #(
.CHANNEL_WIDTH (8),
.ENCODING (0)
) p2b (
.clk (clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // clk_reset.reset_n
.in_ready (p2b_adapter_out_ready), // in_packets_stream.ready
.in_valid (p2b_adapter_out_valid), // .valid
.in_data (p2b_adapter_out_data), // .data
.in_channel (p2b_adapter_out_channel), // .channel
.in_startofpacket (p2b_adapter_out_startofpacket), // .startofpacket
.in_endofpacket (p2b_adapter_out_endofpacket), // .endofpacket
.out_ready (p2b_out_bytes_stream_ready), // out_bytes_stream.ready
.out_valid (p2b_out_bytes_stream_valid), // .valid
.out_data (p2b_out_bytes_stream_data) // .data
);
altera_avalon_packets_to_master #(
.FAST_VER (0),
.FIFO_DEPTHS (2),
.FIFO_WIDTHU (1)
) transacto (
.clk (clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // clk_reset.reset_n
.out_ready (transacto_out_stream_ready), // out_stream.ready
.out_valid (transacto_out_stream_valid), // .valid
.out_data (transacto_out_stream_data), // .data
.out_startofpacket (transacto_out_stream_startofpacket), // .startofpacket
.out_endofpacket (transacto_out_stream_endofpacket), // .endofpacket
.in_ready (b2p_adapter_out_ready), // in_stream.ready
.in_valid (b2p_adapter_out_valid), // .valid
.in_data (b2p_adapter_out_data), // .data
.in_startofpacket (b2p_adapter_out_startofpacket), // .startofpacket
.in_endofpacket (b2p_adapter_out_endofpacket), // .endofpacket
.address (master_address), // avalon_master.address
.readdata (master_readdata), // .readdata
.read (master_read), // .read
.write (master_write), // .write
.writedata (master_writedata), // .writedata
.waitrequest (master_waitrequest), // .waitrequest
.readdatavalid (master_readdatavalid), // .readdatavalid
.byteenable (master_byteenable) // .byteenable
);
ik_swift_master_0_b2p_adapter b2p_adapter (
.clk (clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.in_ready (b2p_out_packets_stream_ready), // in.ready
.in_valid (b2p_out_packets_stream_valid), // .valid
.in_data (b2p_out_packets_stream_data), // .data
.in_channel (b2p_out_packets_stream_channel), // .channel
.in_startofpacket (b2p_out_packets_stream_startofpacket), // .startofpacket
.in_endofpacket (b2p_out_packets_stream_endofpacket), // .endofpacket
.out_ready (b2p_adapter_out_ready), // out.ready
.out_valid (b2p_adapter_out_valid), // .valid
.out_data (b2p_adapter_out_data), // .data
.out_startofpacket (b2p_adapter_out_startofpacket), // .startofpacket
.out_endofpacket (b2p_adapter_out_endofpacket) // .endofpacket
);
ik_swift_master_0_p2b_adapter p2b_adapter (
.clk (clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.in_ready (transacto_out_stream_ready), // in.ready
.in_valid (transacto_out_stream_valid), // .valid
.in_data (transacto_out_stream_data), // .data
.in_startofpacket (transacto_out_stream_startofpacket), // .startofpacket
.in_endofpacket (transacto_out_stream_endofpacket), // .endofpacket
.out_ready (p2b_adapter_out_ready), // out.ready
.out_valid (p2b_adapter_out_valid), // .valid
.out_data (p2b_adapter_out_data), // .data
.out_startofpacket (p2b_adapter_out_startofpacket), // .startofpacket
.out_endofpacket (p2b_adapter_out_endofpacket), // .endofpacket
.out_channel (p2b_adapter_out_channel) // .channel
);
altera_reset_controller #(
.NUM_RESET_INPUTS (1),
.OUTPUT_RESET_SYNC_EDGES ("deassert"),
.SYNC_DEPTH (2),
.RESET_REQUEST_PRESENT (0),
.RESET_REQ_WAIT_TIME (1),
.MIN_RST_ASSERTION_TIME (3),
.RESET_REQ_EARLY_DSRT_TIME (1),
.USE_RESET_REQUEST_IN0 (0),
.USE_RESET_REQUEST_IN1 (0),
.USE_RESET_REQUEST_IN2 (0),
.USE_RESET_REQUEST_IN3 (0),
.USE_RESET_REQUEST_IN4 (0),
.USE_RESET_REQUEST_IN5 (0),
.USE_RESET_REQUEST_IN6 (0),
.USE_RESET_REQUEST_IN7 (0),
.USE_RESET_REQUEST_IN8 (0),
.USE_RESET_REQUEST_IN9 (0),
.USE_RESET_REQUEST_IN10 (0),
.USE_RESET_REQUEST_IN11 (0),
.USE_RESET_REQUEST_IN12 (0),
.USE_RESET_REQUEST_IN13 (0),
.USE_RESET_REQUEST_IN14 (0),
.USE_RESET_REQUEST_IN15 (0),
.ADAPT_RESET_REQUEST (0)
) rst_controller (
.reset_in0 (clk_reset_reset), // reset_in0.reset
.clk (clk_clk), // clk.clk
.reset_out (rst_controller_reset_out_reset), // reset_out.reset
.reset_req (), // (terminated)
.reset_req_in0 (1'b0), // (terminated)
.reset_in1 (1'b0), // (terminated)
.reset_req_in1 (1'b0), // (terminated)
.reset_in2 (1'b0), // (terminated)
.reset_req_in2 (1'b0), // (terminated)
.reset_in3 (1'b0), // (terminated)
.reset_req_in3 (1'b0), // (terminated)
.reset_in4 (1'b0), // (terminated)
.reset_req_in4 (1'b0), // (terminated)
.reset_in5 (1'b0), // (terminated)
.reset_req_in5 (1'b0), // (terminated)
.reset_in6 (1'b0), // (terminated)
.reset_req_in6 (1'b0), // (terminated)
.reset_in7 (1'b0), // (terminated)
.reset_req_in7 (1'b0), // (terminated)
.reset_in8 (1'b0), // (terminated)
.reset_req_in8 (1'b0), // (terminated)
.reset_in9 (1'b0), // (terminated)
.reset_req_in9 (1'b0), // (terminated)
.reset_in10 (1'b0), // (terminated)
.reset_req_in10 (1'b0), // (terminated)
.reset_in11 (1'b0), // (terminated)
.reset_req_in11 (1'b0), // (terminated)
.reset_in12 (1'b0), // (terminated)
.reset_req_in12 (1'b0), // (terminated)
.reset_in13 (1'b0), // (terminated)
.reset_req_in13 (1'b0), // (terminated)
.reset_in14 (1'b0), // (terminated)
.reset_req_in14 (1'b0), // (terminated)
.reset_in15 (1'b0), // (terminated)
.reset_req_in15 (1'b0) // (terminated)
);
endmodule |
module sky130_fd_sc_ls__fahcin (
//# {{data|Data Signals}}
input A ,
input B ,
input CIN ,
output COUT,
output SUM
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule |
module sky130_fd_sc_ls__clkdlyinv3sd3 (
Y ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire not0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
not not0 (not0_out_Y , A );
sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, not0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule |
module uart3_rx #(parameter real CLK_FREQ = 357e6, parameter real BAUD = 9600, parameter WIDTH = 8, parameter PARITY = 0, parameter STOP_BITS = 1) (
//input reset,
input clk,
input uld_rx_data,
output reg [WIDTH-1:0] rx_data = {WIDTH{1'b0}},
//input rx_enable,
input rx_in,
output reg byte_rdy = 1'b0
);
//Variable/custom Baud rate little-endian 8N1 UART-RX
`include "bits_to_fit.v"
//`ifdef ML505 localparam real CLK_FREQ = 100e6;
//`else localparam real CLK_FREQ = 40e6;
//`endif
localparam CLK16X_CNT_SIZE = bits_to_fit(CLK_FREQ/(16*BAUD));
localparam BIT_CNT_SIZE = bits_to_fit(WIDTH+PARITY+STOP_BITS+1);
localparam [CLK16X_CNT_SIZE-1:0] CLK16X_WIDTH = CLK_FREQ/(16*BAUD);
//localparam [BAUD_CNT_SIZE-1:0] FRAME_MIDPOINT = FRAME_WIDTH/2;
// Internal registers
reg [WIDTH-1:0] rx_reg = {WIDTH{1'b0}};
reg [CLK16X_CNT_SIZE-1:0] rx_sample_cnt = {CLK16X_CNT_SIZE{1'b0}};
reg [BIT_CNT_SIZE-1:0] rx_cnt = {BIT_CNT_SIZE{1'b0}};
reg [3:0] Baud_ctr = 4'd0;
(* ASYNC_REG = "true" *) reg rx_da = 1'b1, rx_db = 1'b1;
reg rx_busy = 1'b0;
// UART RX Logic - with 16X Baud Clock
always @ (posedge clk) begin
// Synchronize the asynch signal
rx_da <= rx_in;
rx_db <= rx_da;
// drive the ouptut register when requested
rx_data <= (uld_rx_data) ? rx_reg : rx_data;
/*if (reset) begin
rx_sample_cnt <= {BAUD_CNT_SIZE{1'b0}};
rx_cnt <= {BIT_CNT_SIZE{1'b0}};
byte_rdy <= 1'b0;
rx_busy <= 1'b0;
end else begin // if (~reset)*/
if (rx_busy) begin //drive logic, counters etc
if (rx_sample_cnt == CLK16X_WIDTH) begin
rx_sample_cnt <= {CLK16X_CNT_SIZE{1'b0}};
Baud_ctr <= Baud_ctr + 1'b1;
rx_cnt <= (Baud_ctr == 4'd15) ? rx_cnt + 1'b1 : rx_cnt;
if (Baud_ctr == 4'd7)
case(rx_cnt)
{BIT_CNT_SIZE{1'b0}}: begin
rx_busy <= ~rx_db;
byte_rdy <= (uld_rx_data) ? 1'b0 : byte_rdy;
end
WIDTH+PARITY+STOP_BITS: begin
rx_busy <= 1'b0;
byte_rdy <= rx_db;
end
default: begin
rx_reg[rx_cnt - 1'b1] <= rx_db;
byte_rdy <= (uld_rx_data) ? 1'b0 : byte_rdy;
end
endcase
else /*if (Baud_ctr!=7) */ byte_rdy <= (uld_rx_data) ? 1'b0 : byte_rdy;
end else begin // if (rx_sample_cnt != CLK16X_WIDTH)
rx_sample_cnt <= rx_sample_cnt + 1'b1;
byte_rdy <= (uld_rx_data) ? 1'b0 : byte_rdy;
end
end else begin //if (~rx_busy)
rx_busy <= ~rx_db; //detect space on line as start of START bit
rx_sample_cnt <= {CLK16X_CNT_SIZE{1'b0}};
Baud_ctr <= 4'd0;
rx_cnt <= 1'b0;
byte_rdy <= (uld_rx_data) ? 1'b0 : byte_rdy;
end // if (~rx_busy)
//end //if (~reset)
end //always
endmodule |
module embedded_sync_decoder(
input clk,
input [15:0] data_in,
output reg hs_de,
output reg vs_de,
output reg [15:0] data_out
);
reg [15:0] data_d = 'd0;
reg hs_de_rcv_d = 'd0;
reg vs_de_rcv_d = 'd0;
reg [15:0] data_2d = 'd0;
reg hs_de_rcv_2d = 'd0;
reg vs_de_rcv_2d = 'd0;
reg [15:0] data_3d = 'd0;
reg hs_de_rcv_3d = 'd0;
reg vs_de_rcv_3d = 'd0;
reg [15:0] data_4d = 'd0;
reg hs_de_rcv_4d = 'd0;
reg vs_de_rcv_4d = 'd0;
reg hs_de_rcv = 'd0;
reg vs_de_rcv = 'd0;
// delay to get rid of eav's 4 bytes
always @(posedge clk) begin
data_d <= data_in;
data_2d <= data_d;
data_3d <= data_2d;
data_4d <= data_3d;
data_out <= data_4d;
hs_de_rcv_d <= hs_de_rcv;
vs_de_rcv_d <= vs_de_rcv;
hs_de_rcv_2d <= hs_de_rcv_d;
vs_de_rcv_2d <= vs_de_rcv_d;
hs_de_rcv_3d <= hs_de_rcv_2d;
vs_de_rcv_3d <= vs_de_rcv_2d;
hs_de_rcv_4d <= hs_de_rcv_3d;
vs_de_rcv_4d <= vs_de_rcv_3d;
hs_de <= hs_de_rcv & hs_de_rcv_4d;
vs_de <= vs_de_rcv & vs_de_rcv_4d;
end
reg [1:0] preamble_cnt = 'd0;
// check for sav and eav and generate the corresponding enables
always @(posedge clk) begin
if ((data_in == 16'hffff) || (data_in == 16'h0000)) begin
preamble_cnt <= preamble_cnt + 1'b1;
end else begin
preamble_cnt <= 'd0;
end
if (preamble_cnt == 3'h3) begin
if ((data_in == 16'hb6b6) || (data_in == 16'h9d9d)) begin
hs_de_rcv <= 1'b0;
vs_de_rcv <= ~data_in[13];
end else if ((data_in == 16'habab) || (data_in == 16'h8080)) begin
hs_de_rcv <= 1'b1;
vs_de_rcv <= ~data_in[13];
end
end
end
endmodule |
module sky130_fd_sc_hd__sdfrbp (
Q ,
Q_N ,
CLK ,
D ,
SCD ,
SCE ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
output Q_N ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire buf_Q ;
wire RESET ;
wire mux_out ;
reg notifier ;
wire D_delayed ;
wire SCD_delayed ;
wire SCE_delayed ;
wire RESET_B_delayed;
wire CLK_delayed ;
wire awake ;
wire cond0 ;
wire cond1 ;
wire cond2 ;
wire cond3 ;
wire cond4 ;
// Name Output Other arguments
not not0 (RESET , RESET_B_delayed );
sky130_fd_sc_hd__udp_mux_2to1 mux_2to10 (mux_out, D_delayed, SCD_delayed, SCE_delayed );
sky130_fd_sc_hd__udp_dff$PR_pp$PG$N dff0 (buf_Q , mux_out, CLK_delayed, RESET, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond0 = ( ( RESET_B_delayed === 1'b1 ) && awake );
assign cond1 = ( ( SCE_delayed === 1'b0 ) && cond0 );
assign cond2 = ( ( SCE_delayed === 1'b1 ) && cond0 );
assign cond3 = ( ( D_delayed !== SCD_delayed ) && cond0 );
assign cond4 = ( ( RESET_B === 1'b1 ) && awake );
buf buf0 (Q , buf_Q );
not not1 (Q_N , buf_Q );
endmodule |
module LDCE #(
`ifdef XIL_TIMING //Simprim
parameter LOC = "UNPLACED",
parameter MSGON = "TRUE",
parameter XON = "TRUE",
`endif
parameter [0:0] INIT = 1'b0,
parameter [0:0] IS_CLR_INVERTED = 1'b0,
parameter [0:0] IS_G_INVERTED = 1'b0
)(
output Q,
input CLR,
input D,
input G,
input GE
);
wire [0:0] IS_CLR_INVERTED_BIN;
wire [0:0] IS_G_INVERTED_BIN;
reg Q_out = INIT;
wire CLR_in;
wire D_in;
wire GE_in;
wire G_in;
assign IS_CLR_INVERTED_BIN = IS_CLR_INVERTED;
assign IS_G_INVERTED_BIN = IS_G_INVERTED;
`ifdef XIL_TIMING
wire CLR_dly;
wire D_dly;
wire GE_dly;
wire G_dly;
assign CLR_in = (CLR !== 1'bz) && (CLR_dly ^ IS_CLR_INVERTED_BIN); // rv 0
assign D_in = D_dly;
assign G_in = G_dly ^ IS_G_INVERTED_BIN;
assign GE_in = (GE === 1'bz) || GE_dly; // rv 1
`else
assign CLR_in = (CLR !== 1'bz) && (CLR ^ IS_CLR_INVERTED_BIN); // rv 0
assign D_in = D;
assign G_in = G ^ IS_G_INVERTED_BIN;
assign GE_in = (GE === 1'bz) || GE; // rv 1
`endif
assign Q = Q_out;
reg notifier;
wire notifier1;
reg rst_int, set_int;
wire o_out;
`ifdef XIL_TIMING
wire ngsr, in_out;
wire nrst;
wire in_clk_enable, in_clk_enable_n, in_clk_enable_p;
wire ce_clk_enable, ce_clk_enable_n, ce_clk_enable_p;
wire rst_clk_enable, rst_clk_enable1;
wire tl_enable, tl_enable_n, tl_enable_p;
wire clk_en_n, clk_en_p;
`endif
tri0 GSR = glbl.GSR;
`ifdef XIL_TIMING
not (nrst, CLR_in);
not (ngsr, GSR);
xor (in_out, D_dly, Q);
and (in_clk_enable, ngsr, nrst, GE_in);
and (ce_clk_enable, ngsr, nrst, in_out);
and (rst_clk_enable, ngsr, GE_in);
and (tl_enable, ngsr, nrst);
assign notifier1 = (XON == "FALSE") ? 1'bx : notifier;
assign in_clk_enable_n = (MSGON =="TRUE") && in_clk_enable && IS_G_INVERTED_BIN;
assign in_clk_enable_p = (MSGON =="TRUE") && in_clk_enable && ~IS_G_INVERTED_BIN;
assign ce_clk_enable_n = (MSGON =="TRUE") && ce_clk_enable && IS_G_INVERTED_BIN;
assign ce_clk_enable_p = (MSGON =="TRUE") && ce_clk_enable && ~IS_G_INVERTED_BIN;
assign rst_clk_enable1 = (MSGON =="FALSE") ? 1'b0 : rst_clk_enable;
assign tl_enable_n = (MSGON =="TRUE") && tl_enable && IS_G_INVERTED_BIN;
assign tl_enable_p = (MSGON =="TRUE") && tl_enable && ~IS_G_INVERTED_BIN;
assign clk_en_n = (MSGON =="TRUE") && IS_G_INVERTED_BIN;
assign clk_en_p = (MSGON =="TRUE") && ~IS_G_INVERTED_BIN;
`else
assign notifier1 = 1'bx;
`endif
always @(GSR or CLR_in) begin
if (GSR) begin
if (INIT) begin
rst_int = 1'b0;
set_int = 1'b1;
end
else begin
rst_int = 1'b1;
set_int = 1'b0;
end
end
else begin
rst_int = CLR_in;
set_int = 1'b0;
end
end
latchsre_ldce (o_out, G_in, D_in, set_int, rst_int, GE_in, notifier1);
always @(o_out)
Q_out = o_out;
specify
(D => Q) = (100:100:100, 100:100:100);
(G => Q) = (100:100:100, 100:100:100);
(GE => Q) = (0:0:0, 0:0:0);
`ifdef XIL_TIMING
(CLR => Q) = (0:0:0, 0:0:0);
(negedge CLR => (Q +: 0)) = (0:0:0, 0:0:0);
(posedge CLR => (Q +: 0)) = (0:0:0, 0:0:0);
$period (negedge G, 0:0:0, notifier);
$period (posedge G, 0:0:0, notifier);
$recrem (negedge CLR, negedge G, 0:0:0, 0:0:0, notifier,tl_enable_n,tl_enable_n,CLR_dly, G_dly);
$recrem (negedge CLR, posedge G, 0:0:0, 0:0:0, notifier,tl_enable_p,tl_enable_p,CLR_dly, G_dly);
$recrem (negedge GE, negedge G, 0:0:0, 0:0:0, notifier,tl_enable_n,tl_enable_n,GE_dly, G_dly);
$recrem (negedge GE, posedge G, 0:0:0, 0:0:0, notifier,tl_enable_p,tl_enable_p,GE_dly, G_dly);
$recrem (posedge CLR, negedge G, 0:0:0, 0:0:0, notifier,tl_enable_n,tl_enable_n,CLR_dly, G_dly);
$recrem (posedge CLR, posedge G, 0:0:0, 0:0:0, notifier,tl_enable_p,tl_enable_p,CLR_dly, G_dly);
$setuphold (negedge G, negedge CLR, 0:0:0, 0:0:0, notifier,clk_en_n,clk_en_n, G_dly, CLR_dly);
$setuphold (negedge G, negedge D, 0:0:0, 0:0:0, notifier,in_clk_enable_n,in_clk_enable_n,G_dly,D_dly);
$setuphold (negedge G, negedge GE, 0:0:0, 0:0:0, notifier,ce_clk_enable_n,ce_clk_enable_n,G_dly,GE_dly);
$setuphold (negedge G, posedge CLR, 0:0:0, 0:0:0, notifier,clk_en_n,clk_en_n, G_dly, CLR_dly);
$setuphold (negedge G, posedge D, 0:0:0, 0:0:0, notifier,in_clk_enable_n,in_clk_enable_n,G_dly,D_dly);
$setuphold (negedge G, posedge GE, 0:0:0, 0:0:0, notifier,ce_clk_enable_n,ce_clk_enable_n,G_dly,GE_dly);
$setuphold (posedge G, negedge CLR, 0:0:0, 0:0:0, notifier,clk_en_p,clk_en_p, G_dly, CLR_dly);
$setuphold (posedge G, negedge D, 0:0:0, 0:0:0, notifier,in_clk_enable_p,in_clk_enable_p,G_dly,D_dly);
$setuphold (posedge G, negedge GE, 0:0:0, 0:0:0, notifier,ce_clk_enable_p,ce_clk_enable_p,G_dly,GE_dly);
$setuphold (posedge G, posedge CLR, 0:0:0, 0:0:0, notifier,clk_en_p,clk_en_p, G_dly, CLR_dly);
$setuphold (posedge G, posedge D, 0:0:0, 0:0:0, notifier,in_clk_enable_p,in_clk_enable_p,G_dly,D_dly);
$setuphold (posedge G, posedge GE, 0:0:0, 0:0:0, notifier,ce_clk_enable_p,ce_clk_enable_p,G_dly,GE_dly);
$width (negedge CLR, 0:0:0, 0, notifier);
$width (negedge G, 0:0:0, 0, notifier);
$width (posedge CLR, 0:0:0, 0, notifier);
$width (posedge G, 0:0:0, 0, notifier);
$width (posedge GE, 0:0:0, 0, notifier);
`endif
specparam PATHPULSE$ = 0;
endspecify
endmodule |
module omsp_mem_backbone (
// OUTPUTs
dbg_mem_din, // Debug unit Memory data input
dmem_addr, // Data Memory address
dmem_cen, // Data Memory chip enable (low active)
dmem_din, // Data Memory data input
dmem_wen, // Data Memory write enable (low active)
eu_mdb_in, // Execution Unit Memory data bus input
fe_mdb_in, // Frontend Memory data bus input
fe_pmem_wait, // Frontend wait for Instruction fetch
per_addr, // Peripheral address
per_din, // Peripheral data input
per_wen, // Peripheral write enable (high active)
per_en, // Peripheral enable (high active)
pmem_addr, // Program Memory address
pmem_cen, // Program Memory chip enable (low active)
pmem_din, // Program Memory data input (optional)
pmem_wen, // Program Memory write enable (low active) (optional)
// INPUTs
dbg_halt_st, // Halt/Run status from CPU
dbg_mem_addr, // Debug address for rd/wr access
dbg_mem_dout, // Debug unit data output
dbg_mem_en, // Debug unit memory enable
dbg_mem_wr, // Debug unit memory write
dmem_dout, // Data Memory data output
eu_mab, // Execution Unit Memory address bus
eu_mb_en, // Execution Unit Memory bus enable
eu_mb_wr, // Execution Unit Memory bus write transfer
eu_mdb_out, // Execution Unit Memory data bus output
fe_mab, // Frontend Memory address bus
fe_mb_en, // Frontend Memory bus enable
mclk, // Main system clock
per_dout, // Peripheral data output
pmem_dout, // Program Memory data output
puc // Main system reset
);
// OUTPUTs
//=========
output [15:0] dbg_mem_din; // Debug unit Memory data input
output [`DMEM_MSB:0] dmem_addr; // Data Memory address
output dmem_cen; // Data Memory chip enable (low active)
output [15:0] dmem_din; // Data Memory data input
output [1:0] dmem_wen; // Data Memory write enable (low active)
output [15:0] eu_mdb_in; // Execution Unit Memory data bus input
output [15:0] fe_mdb_in; // Frontend Memory data bus input
output fe_pmem_wait; // Frontend wait for Instruction fetch
output [7:0] per_addr; // Peripheral address
output [15:0] per_din; // Peripheral data input
output [1:0] per_wen; // Peripheral write enable (high active)
output per_en; // Peripheral enable (high active)
output [`PMEM_MSB:0] pmem_addr; // Program Memory address
output pmem_cen; // Program Memory chip enable (low active)
output [15:0] pmem_din; // Program Memory data input (optional)
output [1:0] pmem_wen; // Program Memory write enable (low active) (optional)
// INPUTs
//=========
input dbg_halt_st; // Halt/Run status from CPU
input [15:0] dbg_mem_addr; // Debug address for rd/wr access
input [15:0] dbg_mem_dout; // Debug unit data output
input dbg_mem_en; // Debug unit memory enable
input [1:0] dbg_mem_wr; // Debug unit memory write
input [15:0] dmem_dout; // Data Memory data output
input [14:0] eu_mab; // Execution Unit Memory address bus
input eu_mb_en; // Execution Unit Memory bus enable
input [1:0] eu_mb_wr; // Execution Unit Memory bus write transfer
input [15:0] eu_mdb_out; // Execution Unit Memory data bus output
input [14:0] fe_mab; // Frontend Memory address bus
input fe_mb_en; // Frontend Memory bus enable
input mclk; // Main system clock
input [15:0] per_dout; // Peripheral data output
input [15:0] pmem_dout; // Program Memory data output
input puc; // Main system reset
//=============================================================================
// 1) DECODER
//=============================================================================
// RAM Interface
//------------------
// Execution unit access
wire eu_dmem_cen = ~(eu_mb_en & (eu_mab>=(`DMEM_BASE>>1)) &
(eu_mab<((`DMEM_BASE+`DMEM_SIZE)>>1)));
wire [15:0] eu_dmem_addr = eu_mab-(`DMEM_BASE>>1);
// Debug interface access
wire dbg_dmem_cen = ~(dbg_mem_en & (dbg_mem_addr[15:1]>=(`DMEM_BASE>>1)) &
(dbg_mem_addr[15:1]<((`DMEM_BASE+`DMEM_SIZE)>>1)));
wire [15:0] dbg_dmem_addr = dbg_mem_addr[15:1]-(`DMEM_BASE>>1);
// RAM Interface
wire [`DMEM_MSB:0] dmem_addr = ~dbg_dmem_cen ? dbg_dmem_addr[`DMEM_MSB:0] : eu_dmem_addr[`DMEM_MSB:0];
wire dmem_cen = dbg_dmem_cen & eu_dmem_cen;
wire [1:0] dmem_wen = ~(dbg_mem_wr | eu_mb_wr);
wire [15:0] dmem_din = ~dbg_dmem_cen ? dbg_mem_dout : eu_mdb_out;
// ROM Interface
//------------------
parameter PMEM_OFFSET = (16'hFFFF-`PMEM_SIZE+1);
// Execution unit access (only read access are accepted)
wire eu_pmem_cen = ~(eu_mb_en & ~|eu_mb_wr & (eu_mab>=(PMEM_OFFSET>>1)));
wire [15:0] eu_pmem_addr = eu_mab-(PMEM_OFFSET>>1);
// Front-end access
wire fe_pmem_cen = ~(fe_mb_en & (fe_mab>=(PMEM_OFFSET>>1)));
wire [15:0] fe_pmem_addr = fe_mab-(PMEM_OFFSET>>1);
// Debug interface access
wire dbg_pmem_cen = ~(dbg_mem_en & (dbg_mem_addr[15:1]>=(PMEM_OFFSET>>1)));
wire [15:0] dbg_pmem_addr = dbg_mem_addr[15:1]-(PMEM_OFFSET>>1);
// ROM Interface (Execution unit has priority)
wire [`PMEM_MSB:0] pmem_addr = ~dbg_pmem_cen ? dbg_pmem_addr[`PMEM_MSB:0] :
~eu_pmem_cen ? eu_pmem_addr[`PMEM_MSB:0] : fe_pmem_addr[`PMEM_MSB:0];
wire pmem_cen = fe_pmem_cen & eu_pmem_cen & dbg_pmem_cen;
wire [1:0] pmem_wen = ~dbg_mem_wr;
wire [15:0] pmem_din = dbg_mem_dout;
wire fe_pmem_wait = (~fe_pmem_cen & ~eu_pmem_cen);
// Peripherals
//--------------------
wire dbg_per_en = dbg_mem_en & (dbg_mem_addr[15:9]==7'h00);
wire eu_per_en = eu_mb_en & (eu_mab[14:8]==7'h00);
wire [7:0] per_addr = dbg_mem_en ? dbg_mem_addr[8:1] : eu_mab[7:0];
wire [15:0] per_din = dbg_mem_en ? dbg_mem_dout : eu_mdb_out;
wire [1:0] per_wen = dbg_mem_en ? dbg_mem_wr : eu_mb_wr;
wire per_en = dbg_mem_en ? dbg_per_en : eu_per_en;
reg [15:0] per_dout_val;
always @ (posedge mclk or posedge puc)
if (puc) per_dout_val <= 16'h0000;
else per_dout_val <= per_dout;
// Frontend data Mux
//---------------------------------
// Whenever the frontend doesn't access the ROM, backup the data
// Detect whenever the data should be backuped and restored
reg fe_pmem_cen_dly;
always @(posedge mclk or posedge puc)
if (puc) fe_pmem_cen_dly <= 1'b0;
else fe_pmem_cen_dly <= fe_pmem_cen;
wire fe_pmem_save = ( fe_pmem_cen & ~fe_pmem_cen_dly) & ~dbg_halt_st;
wire fe_pmem_restore = (~fe_pmem_cen & fe_pmem_cen_dly) | dbg_halt_st;
reg [15:0] pmem_dout_bckup;
always @(posedge mclk or posedge puc)
if (puc) pmem_dout_bckup <= 16'h0000;
else if (fe_pmem_save) pmem_dout_bckup <= pmem_dout;
// Mux between the ROM data and the backup
reg pmem_dout_bckup_sel;
always @(posedge mclk or posedge puc)
if (puc) pmem_dout_bckup_sel <= 1'b0;
else if (fe_pmem_save) pmem_dout_bckup_sel <= 1'b1;
else if (fe_pmem_restore) pmem_dout_bckup_sel <= 1'b0;
assign fe_mdb_in = pmem_dout_bckup_sel ? pmem_dout_bckup : pmem_dout;
// Execution-Unit data Mux
//---------------------------------
// Select between peripherals, RAM and ROM
reg [1:0] eu_mdb_in_sel;
always @(posedge mclk or posedge puc)
if (puc) eu_mdb_in_sel <= 2'b00;
else eu_mdb_in_sel <= {~eu_pmem_cen, per_en};
// Mux
assign eu_mdb_in = eu_mdb_in_sel[1] ? pmem_dout :
eu_mdb_in_sel[0] ? per_dout_val : dmem_dout;
// Debug interface data Mux
//---------------------------------
// Select between peripherals, RAM and ROM
reg [1:0] dbg_mem_din_sel;
always @(posedge mclk or posedge puc)
if (puc) dbg_mem_din_sel <= 2'b00;
else dbg_mem_din_sel <= {~dbg_pmem_cen, dbg_per_en};
// Mux
assign dbg_mem_din = dbg_mem_din_sel[1] ? pmem_dout :
dbg_mem_din_sel[0] ? per_dout_val : dmem_dout;
endmodule |
module sky130_fd_sc_lp__dlxtp (
Q ,
D ,
GATE
);
// Module ports
output Q ;
input D ;
input GATE;
// Local signals
wire buf_Q ;
wire GATE_delayed;
wire D_delayed ;
// Delay Name Output Other arguments
sky130_fd_sc_lp__udp_dlatch$P `UNIT_DELAY dlatch0 (buf_Q , D, GATE );
buf buf0 (Q , buf_Q );
endmodule |
module LAG_mesh_network (din, dout,
input_full_flag,
cntrl_in,
clk, rst_n);
parameter XS=network_x;
parameter YS=network_y;
parameter NT=router_radix;
parameter NPL=router_num_pls;
// parameter channel_latency = 0; // number of registers in router to router link or channel
input clk, rst_n;
input [XS*YS*$bits(chan_cntrl_t) - 1 : 0] cntrl_in;
input [XS*YS*$bits(flit_t) - 1 : 0] din;
output [XS*YS*router_num_pls_on_exit*$bits(flit_t) - 1 : 0] dout;
output [XS*YS*router_num_pls_on_entry - 1 : 0] input_full_flag;
// network connections
flit_t i_flit_in [XS-1:0][YS-1:0][NT-1:0][NPL-1:0];
flit_t i_flit_in_ [XS-1:0][YS-1:0][NT-1:0][NPL-1:0];
flit_t i_flit_out [XS-1:0][YS-1:0][NT-1:0][NPL-1:0];
flit_t i_flit_out_ [XS-1:0][YS-1:0][NT-1:0][NPL-1:0];
flit_t terminator [NPL-1:0];
chan_cntrl_t i_cntrl_in [XS-1:0][YS-1:0][NT-1:0];
chan_cntrl_t i_cntrl_out [XS-1:0][YS-1:0][NT-1:0];
reg clk_g [XS-1:0][YS-1:0];
genvar x,y,p,c;
// *********************************************************
// implement router-level clock gating if requested
// *********************************************************
//
generate
for (y=0; y<YS; y=y+1) begin:ycg
for (x=0; x<XS; x=x+1) begin:xcg
//
// no router level clock gating, router clock = global clock
//
always@(clk) begin
clk_g[x][y]<=clk;
end
end // block: xcg
end // block: ycg
endgenerate
// *********************************************************
generate
for (y=0; y<YS; y=y+1) begin:yl
for (x=0; x<XS; x=x+1) begin:xl
//
// make network connections
//
// tile port - external interface
always_comb
begin
i_flit_in[x][y][`TILE] = terminator;
i_flit_in[x][y][`TILE][0] = din[$bits(flit_t)*(x*YS + y + 1) - 1 : $bits(flit_t)*(x*YS + y)]; ;
end
assign i_cntrl_in[x][y][`TILE] = cntrl_in[$bits(chan_cntrl_t)*(x*YS + y + 1) - 1 : $bits(chan_cntrl_t)*(x*YS + y)];
for (c=0; c<router_num_pls_on_exit; c++) begin:network_out_to_sink
assign dout[$bits(flit_t)*(x*YS*router_num_pls_on_exit + y*router_num_pls_on_exit + c + 1) - 1 : $bits(flit_t)*(x*YS*router_num_pls_on_exit + y*router_num_pls_on_exit + c)] = i_flit_out[x][y][`TILE][c];
end
// north port
if (y==0) begin
assign i_flit_in[x][y][`NORTH] = terminator;
assign i_cntrl_in[x][y][`NORTH] = '0;
end else begin
assign i_flit_in[x][y][`NORTH] = i_flit_out[x][y-1][`SOUTH];
assign i_cntrl_in[x][y][`NORTH] = i_cntrl_out[x][y-1][`SOUTH];
end
// east port
if (x==XS-1) begin
assign i_flit_in[x][y][`EAST] = terminator;
assign i_cntrl_in[x][y][`EAST] = '0;
end else begin
assign i_flit_in[x][y][`EAST] = i_flit_out[x+1][y][`WEST];
assign i_cntrl_in[x][y][`EAST] = i_cntrl_out[x+1][y][`WEST];
end
// south port
if (y==YS-1) begin
assign i_flit_in[x][y][`SOUTH] = terminator;
assign i_cntrl_in[x][y][`SOUTH] = '0;
end else begin
assign i_flit_in[x][y][`SOUTH] = i_flit_out[x][y+1][`NORTH];
assign i_cntrl_in[x][y][`SOUTH] = i_cntrl_out[x][y+1][`NORTH];
end
// west port
if (x==0) begin
assign i_flit_in[x][y][`WEST] = terminator;
assign i_cntrl_in[x][y][`WEST] = '0;
end else begin
assign i_flit_in[x][y][`WEST] = i_flit_out[x-1][y][`EAST];
assign i_cntrl_in[x][y][`WEST] = i_cntrl_out[x-1][y][`EAST];
end
for (p=0; p<NT; p++) begin:prts
for (c=0; c<NPL; c++) begin:channels2
always_comb
begin
i_flit_in_[x][y][p][c] = i_flit_in[x][y][p][c];
end
end
end
// ###################################
// Channel (link) between routers - ** NOT FROM ROUTER TO TILE **
// ###################################
// i_flit_out_ -> CHANNEL -> i_flit_out
//
/*for (p=0; p<NT; p++) begin:prts2
assign i_flit_out[x][y][p]=i_flit_out_[x][y][p];
end*/
for (p=0; p<NT; p++) begin:prts2
if (p==`TILE) begin
// router to tile is a local connection
assign i_flit_out[x][y][p]=i_flit_out_[x][y][p];
end else begin
LAG_pipelined_channel #(.nPC(NPL), .stages(channel_latency)) channel
(.data_in(i_flit_out_[x][y][p]),
.data_out(i_flit_out[x][y][p]), .clk, .rst_n);
end
end
// ###################################
// Router
// ###################################
// # parameters for router are read from parameters.v
LAG_router #(
.buf_len(router_buf_len),
.network_x(network_x),
.network_y(network_y),
.NT(router_radix),
.NPL(router_num_pls),
.alloc_stages(router_alloc_stages),
.router_num_pls_on_entry(router_num_pls_on_entry),
.router_num_pls_on_exit(router_num_pls_on_exit)
) node
(i_flit_in_[x][y],
i_flit_out_[x][y],
i_cntrl_in[x][y],
i_cntrl_out[x][y],
input_full_flag[router_num_pls_on_entry*(x*YS + y + 1) - 1 : router_num_pls_on_entry*(x*YS + y)],
clk_g[x][y],
rst_n);
end //x
end //y
endgenerate
endmodule |
module mux16x8(data0, data1, data2, data3, data4, data5, data6, data7, selectInput, out); // 8-16bit-input mux
output reg [15:0] out;
input [15:0] data0, data1, data2, data3, data4, data5, data6, data7;
input [2:0] selectInput;
always@(data0 or data1 or data2 or data3 or data4 or data5 or data6 or data7 or selectInput) begin
case(selectInput)
0: out = data0;
1: out = data1;
2: out = data2;
3: out = data3;
4: out = data4;
5: out = data5;
6: out = data6;
7: out = data7;
endcase
end
endmodule |
module mux16x4(data0, data1, data2, data3, selectInput, out); // 4-16bit-input mux
output reg [15:0] out;
input [15:0] data0, data1, data2, data3;
input [1:0] selectInput;
always@(data0 or data1 or data2 or data3 or selectInput) begin
case(selectInput)
0: out = data0;
1: out = data1;
2: out = data2;
3: out = data3;
endcase
end
endmodule |
module mux2x4(data0, data1, data2, data3, selectInput, out); // 4-16bit-input mux
output reg [1:0] out;
input [1:0] data0, data1, data2, data3;
input [1:0] selectInput;
always@(data0 or data1 or data2 or data3 or selectInput) begin
case(selectInput)
0: out = data0;
1: out = data1;
2: out = data2;
3: out = data3;
endcase
end
endmodule |
module mux16x2(data0, data1, selectInput, out); // 2-16bit-input mux
output reg [15:0] out;
input [15:0] data0, data1;
input selectInput;
always@(data0 or data1 or selectInput) begin
case(selectInput)
0: out = data0;
1: out = data1;
endcase
end
endmodule |
module ip_demux #
(
parameter M_COUNT = 4,
parameter DATA_WIDTH = 8,
parameter KEEP_ENABLE = (DATA_WIDTH>8),
parameter KEEP_WIDTH = (DATA_WIDTH/8),
parameter ID_ENABLE = 0,
parameter ID_WIDTH = 8,
parameter DEST_ENABLE = 0,
parameter DEST_WIDTH = 8,
parameter USER_ENABLE = 1,
parameter USER_WIDTH = 1
)
(
input wire clk,
input wire rst,
/*
* IP frame input
*/
input wire s_ip_hdr_valid,
output wire s_ip_hdr_ready,
input wire [47:0] s_eth_dest_mac,
input wire [47:0] s_eth_src_mac,
input wire [15:0] s_eth_type,
input wire [3:0] s_ip_version,
input wire [3:0] s_ip_ihl,
input wire [5:0] s_ip_dscp,
input wire [1:0] s_ip_ecn,
input wire [15:0] s_ip_length,
input wire [15:0] s_ip_identification,
input wire [2:0] s_ip_flags,
input wire [12:0] s_ip_fragment_offset,
input wire [7:0] s_ip_ttl,
input wire [7:0] s_ip_protocol,
input wire [15:0] s_ip_header_checksum,
input wire [31:0] s_ip_source_ip,
input wire [31:0] s_ip_dest_ip,
input wire [DATA_WIDTH-1:0] s_ip_payload_axis_tdata,
input wire [KEEP_WIDTH-1:0] s_ip_payload_axis_tkeep,
input wire s_ip_payload_axis_tvalid,
output wire s_ip_payload_axis_tready,
input wire s_ip_payload_axis_tlast,
input wire [ID_WIDTH-1:0] s_ip_payload_axis_tid,
input wire [DEST_WIDTH-1:0] s_ip_payload_axis_tdest,
input wire [USER_WIDTH-1:0] s_ip_payload_axis_tuser,
/*
* IP frame outputs
*/
output wire [M_COUNT-1:0] m_ip_hdr_valid,
input wire [M_COUNT-1:0] m_ip_hdr_ready,
output wire [M_COUNT*48-1:0] m_eth_dest_mac,
output wire [M_COUNT*48-1:0] m_eth_src_mac,
output wire [M_COUNT*16-1:0] m_eth_type,
output wire [M_COUNT*4-1:0] m_ip_version,
output wire [M_COUNT*4-1:0] m_ip_ihl,
output wire [M_COUNT*6-1:0] m_ip_dscp,
output wire [M_COUNT*2-1:0] m_ip_ecn,
output wire [M_COUNT*16-1:0] m_ip_length,
output wire [M_COUNT*16-1:0] m_ip_identification,
output wire [M_COUNT*3-1:0] m_ip_flags,
output wire [M_COUNT*13-1:0] m_ip_fragment_offset,
output wire [M_COUNT*8-1:0] m_ip_ttl,
output wire [M_COUNT*8-1:0] m_ip_protocol,
output wire [M_COUNT*16-1:0] m_ip_header_checksum,
output wire [M_COUNT*32-1:0] m_ip_source_ip,
output wire [M_COUNT*32-1:0] m_ip_dest_ip,
output wire [M_COUNT*DATA_WIDTH-1:0] m_ip_payload_axis_tdata,
output wire [M_COUNT*KEEP_WIDTH-1:0] m_ip_payload_axis_tkeep,
output wire [M_COUNT-1:0] m_ip_payload_axis_tvalid,
input wire [M_COUNT-1:0] m_ip_payload_axis_tready,
output wire [M_COUNT-1:0] m_ip_payload_axis_tlast,
output wire [M_COUNT*ID_WIDTH-1:0] m_ip_payload_axis_tid,
output wire [M_COUNT*DEST_WIDTH-1:0] m_ip_payload_axis_tdest,
output wire [M_COUNT*USER_WIDTH-1:0] m_ip_payload_axis_tuser,
/*
* Control
*/
input wire enable,
input wire drop,
input wire [$clog2(M_COUNT)-1:0] select
);
parameter CL_M_COUNT = $clog2(M_COUNT);
reg [CL_M_COUNT-1:0] select_reg = {CL_M_COUNT{1'b0}}, select_ctl, select_next;
reg drop_reg = 1'b0, drop_ctl, drop_next;
reg frame_reg = 1'b0, frame_ctl, frame_next;
reg s_ip_hdr_ready_reg = 1'b0, s_ip_hdr_ready_next;
reg s_ip_payload_axis_tready_reg = 1'b0, s_ip_payload_axis_tready_next;
reg [M_COUNT-1:0] m_ip_hdr_valid_reg = 0, m_ip_hdr_valid_next;
reg [47:0] m_eth_dest_mac_reg = 48'd0, m_eth_dest_mac_next;
reg [47:0] m_eth_src_mac_reg = 48'd0, m_eth_src_mac_next;
reg [15:0] m_eth_type_reg = 16'd0, m_eth_type_next;
reg [3:0] m_ip_version_reg = 4'd0, m_ip_version_next;
reg [3:0] m_ip_ihl_reg = 4'd0, m_ip_ihl_next;
reg [5:0] m_ip_dscp_reg = 6'd0, m_ip_dscp_next;
reg [1:0] m_ip_ecn_reg = 2'd0, m_ip_ecn_next;
reg [15:0] m_ip_length_reg = 16'd0, m_ip_length_next;
reg [15:0] m_ip_identification_reg = 16'd0, m_ip_identification_next;
reg [2:0] m_ip_flags_reg = 3'd0, m_ip_flags_next;
reg [12:0] m_ip_fragment_offset_reg = 13'd0, m_ip_fragment_offset_next;
reg [7:0] m_ip_ttl_reg = 8'd0, m_ip_ttl_next;
reg [7:0] m_ip_protocol_reg = 8'd0, m_ip_protocol_next;
reg [15:0] m_ip_header_checksum_reg = 16'd0, m_ip_header_checksum_next;
reg [31:0] m_ip_source_ip_reg = 32'd0, m_ip_source_ip_next;
reg [31:0] m_ip_dest_ip_reg = 32'd0, m_ip_dest_ip_next;
// internal datapath
reg [DATA_WIDTH-1:0] m_ip_payload_axis_tdata_int;
reg [KEEP_WIDTH-1:0] m_ip_payload_axis_tkeep_int;
reg [M_COUNT-1:0] m_ip_payload_axis_tvalid_int;
reg m_ip_payload_axis_tready_int_reg = 1'b0;
reg m_ip_payload_axis_tlast_int;
reg [ID_WIDTH-1:0] m_ip_payload_axis_tid_int;
reg [DEST_WIDTH-1:0] m_ip_payload_axis_tdest_int;
reg [USER_WIDTH-1:0] m_ip_payload_axis_tuser_int;
wire m_ip_payload_axis_tready_int_early;
assign s_ip_hdr_ready = s_ip_hdr_ready_reg && enable;
assign s_ip_payload_axis_tready = s_ip_payload_axis_tready_reg && enable;
assign m_ip_hdr_valid = m_ip_hdr_valid_reg;
assign m_eth_dest_mac = {M_COUNT{m_eth_dest_mac_reg}};
assign m_eth_src_mac = {M_COUNT{m_eth_src_mac_reg}};
assign m_eth_type = {M_COUNT{m_eth_type_reg}};
assign m_ip_version = {M_COUNT{m_ip_version_reg}};
assign m_ip_ihl = {M_COUNT{m_ip_ihl_reg}};
assign m_ip_dscp = {M_COUNT{m_ip_dscp_reg}};
assign m_ip_ecn = {M_COUNT{m_ip_ecn_reg}};
assign m_ip_length = {M_COUNT{m_ip_length_reg}};
assign m_ip_identification = {M_COUNT{m_ip_identification_reg}};
assign m_ip_flags = {M_COUNT{m_ip_flags_reg}};
assign m_ip_fragment_offset = {M_COUNT{m_ip_fragment_offset_reg}};
assign m_ip_ttl = {M_COUNT{m_ip_ttl_reg}};
assign m_ip_protocol = {M_COUNT{m_ip_protocol_reg}};
assign m_ip_header_checksum = {M_COUNT{m_ip_header_checksum_reg}};
assign m_ip_source_ip = {M_COUNT{m_ip_source_ip_reg}};
assign m_ip_dest_ip = {M_COUNT{m_ip_dest_ip_reg}};
integer i;
always @* begin
select_next = select_reg;
select_ctl = select_reg;
drop_next = drop_reg;
drop_ctl = drop_reg;
frame_next = frame_reg;
frame_ctl = frame_reg;
s_ip_hdr_ready_next = 1'b0;
s_ip_payload_axis_tready_next = 1'b0;
m_ip_hdr_valid_next = m_ip_hdr_valid_reg & ~m_ip_hdr_ready;
m_eth_dest_mac_next = m_eth_dest_mac_reg;
m_eth_src_mac_next = m_eth_src_mac_reg;
m_eth_type_next = m_eth_type_reg;
m_ip_version_next = m_ip_version_reg;
m_ip_ihl_next = m_ip_ihl_reg;
m_ip_dscp_next = m_ip_dscp_reg;
m_ip_ecn_next = m_ip_ecn_reg;
m_ip_length_next = m_ip_length_reg;
m_ip_identification_next = m_ip_identification_reg;
m_ip_flags_next = m_ip_flags_reg;
m_ip_fragment_offset_next = m_ip_fragment_offset_reg;
m_ip_ttl_next = m_ip_ttl_reg;
m_ip_protocol_next = m_ip_protocol_reg;
m_ip_header_checksum_next = m_ip_header_checksum_reg;
m_ip_source_ip_next = m_ip_source_ip_reg;
m_ip_dest_ip_next = m_ip_dest_ip_reg;
if (s_ip_payload_axis_tvalid && s_ip_payload_axis_tready) begin
// end of frame detection
if (s_ip_payload_axis_tlast) begin
frame_next = 1'b0;
drop_next = 1'b0;
end
end
if (!frame_reg && s_ip_hdr_valid && s_ip_hdr_ready) begin
// start of frame, grab select value
select_ctl = select;
drop_ctl = drop;
frame_ctl = 1'b1;
select_next = select_ctl;
drop_next = drop_ctl;
frame_next = frame_ctl;
s_ip_hdr_ready_next = 1'b0;
m_ip_hdr_valid_next = (!drop_ctl) << select_ctl;
m_eth_dest_mac_next = s_eth_dest_mac;
m_eth_src_mac_next = s_eth_src_mac;
m_eth_type_next = s_eth_type;
m_ip_version_next = s_ip_version;
m_ip_ihl_next = s_ip_ihl;
m_ip_dscp_next = s_ip_dscp;
m_ip_ecn_next = s_ip_ecn;
m_ip_length_next = s_ip_length;
m_ip_identification_next = s_ip_identification;
m_ip_flags_next = s_ip_flags;
m_ip_fragment_offset_next = s_ip_fragment_offset;
m_ip_ttl_next = s_ip_ttl;
m_ip_protocol_next = s_ip_protocol;
m_ip_header_checksum_next = s_ip_header_checksum;
m_ip_source_ip_next = s_ip_source_ip;
m_ip_dest_ip_next = s_ip_dest_ip;
end
s_ip_hdr_ready_next = !frame_next && !m_ip_hdr_valid_next;
s_ip_payload_axis_tready_next = (m_ip_payload_axis_tready_int_early || drop_ctl) && frame_ctl;
m_ip_payload_axis_tdata_int = s_ip_payload_axis_tdata;
m_ip_payload_axis_tkeep_int = s_ip_payload_axis_tkeep;
m_ip_payload_axis_tvalid_int = (s_ip_payload_axis_tvalid && s_ip_payload_axis_tready && !drop_ctl) << select_ctl;
m_ip_payload_axis_tlast_int = s_ip_payload_axis_tlast;
m_ip_payload_axis_tid_int = s_ip_payload_axis_tid;
m_ip_payload_axis_tdest_int = s_ip_payload_axis_tdest;
m_ip_payload_axis_tuser_int = s_ip_payload_axis_tuser;
end
always @(posedge clk) begin
if (rst) begin
select_reg <= 2'd0;
drop_reg <= 1'b0;
frame_reg <= 1'b0;
s_ip_hdr_ready_reg <= 1'b0;
s_ip_payload_axis_tready_reg <= 1'b0;
m_ip_hdr_valid_reg <= 0;
end else begin
select_reg <= select_next;
drop_reg <= drop_next;
frame_reg <= frame_next;
s_ip_hdr_ready_reg <= s_ip_hdr_ready_next;
s_ip_payload_axis_tready_reg <= s_ip_payload_axis_tready_next;
m_ip_hdr_valid_reg <= m_ip_hdr_valid_next;
end
m_eth_dest_mac_reg <= m_eth_dest_mac_next;
m_eth_src_mac_reg <= m_eth_src_mac_next;
m_eth_type_reg <= m_eth_type_next;
m_ip_version_reg <= m_ip_version_next;
m_ip_ihl_reg <= m_ip_ihl_next;
m_ip_dscp_reg <= m_ip_dscp_next;
m_ip_ecn_reg <= m_ip_ecn_next;
m_ip_length_reg <= m_ip_length_next;
m_ip_identification_reg <= m_ip_identification_next;
m_ip_flags_reg <= m_ip_flags_next;
m_ip_fragment_offset_reg <= m_ip_fragment_offset_next;
m_ip_ttl_reg <= m_ip_ttl_next;
m_ip_protocol_reg <= m_ip_protocol_next;
m_ip_header_checksum_reg <= m_ip_header_checksum_next;
m_ip_source_ip_reg <= m_ip_source_ip_next;
m_ip_dest_ip_reg <= m_ip_dest_ip_next;
end
// output datapath logic
reg [DATA_WIDTH-1:0] m_ip_payload_axis_tdata_reg = {DATA_WIDTH{1'b0}};
reg [KEEP_WIDTH-1:0] m_ip_payload_axis_tkeep_reg = {KEEP_WIDTH{1'b0}};
reg [M_COUNT-1:0] m_ip_payload_axis_tvalid_reg = {M_COUNT{1'b0}}, m_ip_payload_axis_tvalid_next;
reg m_ip_payload_axis_tlast_reg = 1'b0;
reg [ID_WIDTH-1:0] m_ip_payload_axis_tid_reg = {ID_WIDTH{1'b0}};
reg [DEST_WIDTH-1:0] m_ip_payload_axis_tdest_reg = {DEST_WIDTH{1'b0}};
reg [USER_WIDTH-1:0] m_ip_payload_axis_tuser_reg = {USER_WIDTH{1'b0}};
reg [DATA_WIDTH-1:0] temp_m_ip_payload_axis_tdata_reg = {DATA_WIDTH{1'b0}};
reg [KEEP_WIDTH-1:0] temp_m_ip_payload_axis_tkeep_reg = {KEEP_WIDTH{1'b0}};
reg [M_COUNT-1:0] temp_m_ip_payload_axis_tvalid_reg = {M_COUNT{1'b0}}, temp_m_ip_payload_axis_tvalid_next;
reg temp_m_ip_payload_axis_tlast_reg = 1'b0;
reg [ID_WIDTH-1:0] temp_m_ip_payload_axis_tid_reg = {ID_WIDTH{1'b0}};
reg [DEST_WIDTH-1:0] temp_m_ip_payload_axis_tdest_reg = {DEST_WIDTH{1'b0}};
reg [USER_WIDTH-1:0] temp_m_ip_payload_axis_tuser_reg = {USER_WIDTH{1'b0}};
// datapath control
reg store_axis_int_to_output;
reg store_axis_int_to_temp;
reg store_ip_payload_axis_temp_to_output;
assign m_ip_payload_axis_tdata = {M_COUNT{m_ip_payload_axis_tdata_reg}};
assign m_ip_payload_axis_tkeep = KEEP_ENABLE ? {M_COUNT{m_ip_payload_axis_tkeep_reg}} : {M_COUNT*KEEP_WIDTH{1'b1}};
assign m_ip_payload_axis_tvalid = m_ip_payload_axis_tvalid_reg;
assign m_ip_payload_axis_tlast = {M_COUNT{m_ip_payload_axis_tlast_reg}};
assign m_ip_payload_axis_tid = ID_ENABLE ? {M_COUNT{m_ip_payload_axis_tid_reg}} : {M_COUNT*ID_WIDTH{1'b0}};
assign m_ip_payload_axis_tdest = DEST_ENABLE ? {M_COUNT{m_ip_payload_axis_tdest_reg}} : {M_COUNT*DEST_WIDTH{1'b0}};
assign m_ip_payload_axis_tuser = USER_ENABLE ? {M_COUNT{m_ip_payload_axis_tuser_reg}} : {M_COUNT*USER_WIDTH{1'b0}};
// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
assign m_ip_payload_axis_tready_int_early = (m_ip_payload_axis_tready & m_ip_payload_axis_tvalid) || (!temp_m_ip_payload_axis_tvalid_reg && (!m_ip_payload_axis_tvalid || !m_ip_payload_axis_tvalid_int));
always @* begin
// transfer sink ready state to source
m_ip_payload_axis_tvalid_next = m_ip_payload_axis_tvalid_reg;
temp_m_ip_payload_axis_tvalid_next = temp_m_ip_payload_axis_tvalid_reg;
store_axis_int_to_output = 1'b0;
store_axis_int_to_temp = 1'b0;
store_ip_payload_axis_temp_to_output = 1'b0;
if (m_ip_payload_axis_tready_int_reg) begin
// input is ready
if ((m_ip_payload_axis_tready & m_ip_payload_axis_tvalid) || !m_ip_payload_axis_tvalid) begin
// output is ready or currently not valid, transfer data to output
m_ip_payload_axis_tvalid_next = m_ip_payload_axis_tvalid_int;
store_axis_int_to_output = 1'b1;
end else begin
// output is not ready, store input in temp
temp_m_ip_payload_axis_tvalid_next = m_ip_payload_axis_tvalid_int;
store_axis_int_to_temp = 1'b1;
end
end else if (m_ip_payload_axis_tready & m_ip_payload_axis_tvalid) begin
// input is not ready, but output is ready
m_ip_payload_axis_tvalid_next = temp_m_ip_payload_axis_tvalid_reg;
temp_m_ip_payload_axis_tvalid_next = 1'b0;
store_ip_payload_axis_temp_to_output = 1'b1;
end
end
always @(posedge clk) begin
if (rst) begin
m_ip_payload_axis_tvalid_reg <= {M_COUNT{1'b0}};
m_ip_payload_axis_tready_int_reg <= 1'b0;
temp_m_ip_payload_axis_tvalid_reg <= 1'b0;
end else begin
m_ip_payload_axis_tvalid_reg <= m_ip_payload_axis_tvalid_next;
m_ip_payload_axis_tready_int_reg <= m_ip_payload_axis_tready_int_early;
temp_m_ip_payload_axis_tvalid_reg <= temp_m_ip_payload_axis_tvalid_next;
end
// datapath
if (store_axis_int_to_output) begin
m_ip_payload_axis_tdata_reg <= m_ip_payload_axis_tdata_int;
m_ip_payload_axis_tkeep_reg <= m_ip_payload_axis_tkeep_int;
m_ip_payload_axis_tlast_reg <= m_ip_payload_axis_tlast_int;
m_ip_payload_axis_tid_reg <= m_ip_payload_axis_tid_int;
m_ip_payload_axis_tdest_reg <= m_ip_payload_axis_tdest_int;
m_ip_payload_axis_tuser_reg <= m_ip_payload_axis_tuser_int;
end else if (store_ip_payload_axis_temp_to_output) begin
m_ip_payload_axis_tdata_reg <= temp_m_ip_payload_axis_tdata_reg;
m_ip_payload_axis_tkeep_reg <= temp_m_ip_payload_axis_tkeep_reg;
m_ip_payload_axis_tlast_reg <= temp_m_ip_payload_axis_tlast_reg;
m_ip_payload_axis_tid_reg <= temp_m_ip_payload_axis_tid_reg;
m_ip_payload_axis_tdest_reg <= temp_m_ip_payload_axis_tdest_reg;
m_ip_payload_axis_tuser_reg <= temp_m_ip_payload_axis_tuser_reg;
end
if (store_axis_int_to_temp) begin
temp_m_ip_payload_axis_tdata_reg <= m_ip_payload_axis_tdata_int;
temp_m_ip_payload_axis_tkeep_reg <= m_ip_payload_axis_tkeep_int;
temp_m_ip_payload_axis_tlast_reg <= m_ip_payload_axis_tlast_int;
temp_m_ip_payload_axis_tid_reg <= m_ip_payload_axis_tid_int;
temp_m_ip_payload_axis_tdest_reg <= m_ip_payload_axis_tdest_int;
temp_m_ip_payload_axis_tuser_reg <= m_ip_payload_axis_tuser_int;
end
end
endmodule |
module sky130_fd_sc_ls__o31a (
X ,
A1,
A2,
A3,
B1
);
// Module ports
output X ;
input A1;
input A2;
input A3;
input B1;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire or0_out ;
wire and0_out_X;
// Name Output Other arguments
or or0 (or0_out , A2, A1, A3 );
and and0 (and0_out_X, or0_out, B1 );
buf buf0 (X , and0_out_X );
endmodule |
module sky130_fd_sc_hvl__a22o (
X ,
A1,
A2,
B1,
B2
);
// Module ports
output X ;
input A1;
input A2;
input B1;
input B2;
// Local signals
wire and0_out ;
wire and1_out ;
wire or0_out_X;
// Name Output Other arguments
and and0 (and0_out , B1, B2 );
and and1 (and1_out , A1, A2 );
or or0 (or0_out_X, and1_out, and0_out);
buf buf0 (X , or0_out_X );
endmodule |
module control_fsm
(
input clk, reset, run_n,
input [15:0] sram_d, regA, regB, alu_status, alu_out,
output reg sram_we_n, reg_we,
output reg [2:0] alu_op,
output reg [3:0] reg_addr_a, reg_addr_b, reg_addr_c,
output [15:0] alu_op_a, reg_data_c,
output reg [15:0] sram_addr, sram_q
);
// Define bit widths
`define alu_op_size 3
//===========================================================================
// Parameter Declarations
//===========================================================================
// Declare states
parameter ADD = 5'd0;
parameter ADDI = 5'd1;
parameter SUB = 5'd2;
parameter SUBI = 5'd3;
parameter MULT = 5'd4;
parameter SW = 5'd5;
parameter LW = 5'd6;
parameter LT = 5'd7;
parameter NAND = 4'd8;
parameter DIV = 5'd9;
parameter MOD = 5'd10;
parameter LTE = 5'd11;
parameter BLT = 5'd12;
parameter BLE = 5'd13;
parameter BEQ = 5'd14;
parameter JUMP = 5'd15;
parameter FETCH = 5'd16;
parameter BLT2 = 5'd17;
parameter BLE2 = 5'd18;
parameter BEQ2 = 5'd19;
parameter SW2 = 5'd20;
parameter DECODE = 5'd21;
parameter LW2 = 5'd22;
parameter LW3 = 5'd23;
parameter SW3 = 5'd24;
parameter SW4 = 5'd25;
parameter JUMP2 = 5'd26;
parameter BLE3 = 5'd27;
parameter BLT3 = 5'd28;
parameter BEQ3 = 5'd29;
reg im_en;
reg [4:0] state;
reg [15:0] instruction,pc, regC;
wire ram_to_reg;
wire [3:0] op_code, op1, op2, op3, im;
wire [11:0] jump;
//wire [15:0] alu_op_a;
// assign the different fields of the instruction
assign op_code = instruction[15:12];
assign op1 = instruction[3:0];
assign op2 = instruction[7:4];
assign op3 = instruction[11:8];
assign im = instruction[3:0];
assign jump = instruction[11:0];
assign alu_op_a = im_en ? {12'd0, im} : regA;
assign ram_to_reg = (state == LW) | (state == LW2) | (state == LW3);
assign reg_data_c = ram_to_reg ? sram_d : alu_out;
// Determine the next state synchronously, based on the
// current state and the input
always @ (posedge clk or negedge reset) begin
if (reset == 1'b0) begin
state <= FETCH;
end else if(!run_n)
case (state)
FETCH:
state <= DECODE;
DECODE:
state <= {1'b0, op_code};
ADD:
state <= FETCH;
ADDI:
state <= FETCH;
SUB:
state <= FETCH;
SUBI:
state <= FETCH;
MULT:
state <= FETCH;
SW:
state <= SW2;
SW2:
state <= SW3;
SW3:
state <= SW4;
SW4:
state <= FETCH;
LW:
state <= LW2;
LW2:
state <= LW3;
LW3:
state <= FETCH;
LT:
state <= FETCH;
NAND:
state <= FETCH;
DIV:
state <= FETCH;
MOD:
state <= FETCH;
LTE:
state <= FETCH;
BLT:
state <= BLT2;
BLE:
state <= BLE2;
BEQ:
state <= BEQ2;
JUMP:
state <= JUMP2;
JUMP2:
state <= FETCH;
BLT2:
state <= BLT3;
BLT3:
state <= FETCH;
BLE2:
state <= BLE3;
BLE3:
state <= FETCH;
BEQ2:
state <= BEQ3;
BEQ3:
state <= FETCH;
default:
state <= FETCH;
endcase
end
// Determine the output based only on the current state
// and the input (do not wait for a clock edge).
always @ (posedge clk or negedge reset) begin
if(reset == 1'b0) begin
pc <= 16'h0000;
instruction <= 16'hf000; // jump to 0
sram_addr <= 16'h0000;
sram_we_n <= 1'b1;
sram_q <= 16'h0000;
end else begin
case (state)
FETCH: begin
instruction <= sram_d;
sram_addr <= pc;
sram_we_n <= 1'b1;
pc <= pc;
sram_q <= 16'hffff;
end
DECODE: begin
pc <= pc;
instruction <= instruction;
sram_we_n <= 1'b1;
sram_q <= 16'hffff;
sram_addr <= sram_addr;// infered latch
end
ADD: begin
pc <= pc + 16'd1;
instruction <= instruction;
sram_we_n <= 1'b1;
sram_q <= 16'hffff;
sram_addr <= sram_addr;// infered latch
end
ADDI: begin
pc <= pc + 16'd1;
instruction <= instruction;
sram_we_n <= 1'b1;
sram_q <= 16'hffff;
sram_addr <= sram_addr;// infered latch
end
SUB: begin
pc <= pc + 16'd1;
instruction <= instruction;
sram_we_n <= 1'b1;
sram_q <= 16'hffff;
sram_addr <= sram_addr;// infered latch
end
SUBI: begin
pc <= pc + 16'd1;
instruction <= instruction;
sram_we_n <= 1'b1;
sram_q <= 16'hffff;
sram_addr <= sram_addr;// infered latch
end
MULT: begin
pc <= pc + 16'd1;
instruction <= instruction;
sram_we_n <= 1'b1;
sram_q <= 16'hffff;
sram_addr <= sram_addr;// infered latch
end
SW: begin
sram_we_n <= 1'b1;// should work
sram_q <= regA;// port A
sram_addr <= alu_out;
pc <= pc;
instruction <= instruction;
end
SW2: begin
sram_we_n <= 1'b0;
sram_q <= regA;// port A
sram_addr <= alu_out;
pc <= pc;
instruction <= instruction;
end
SW3: begin
sram_we_n <= 1'b1;
sram_q <= regA;// port A
sram_addr <= pc;// for fetch cycle
pc <= pc;
instruction <= instruction;
end
SW4: begin
sram_we_n <= 1'b1;
sram_q <= regA;// port A
sram_addr <= pc;// for fetch cycle
pc <= pc + 16'd1;
instruction <= instruction;
end
LW:begin
sram_we_n <= 1'b1;
sram_addr <= alu_out;
pc <= pc;
instruction <= instruction;
sram_q <= 16'hffff;
end
LW2:begin
sram_we_n <= 1'b1;
sram_addr <= pc;
pc <= pc;
instruction <= instruction;
sram_q <= 16'hffff;
end
LW3:begin
sram_we_n <= 1'b1;
sram_addr <= pc;
pc <= pc + 16'd1;
instruction <= instruction;
sram_q <= 16'hffff;
end
LT: begin
pc <= pc + 16'd1;
instruction <= instruction;
sram_we_n <= 1'b1;
sram_q <= 16'hffff;
sram_addr <= sram_addr;// infered latch
end
NAND: begin
pc <= pc + 16'd1;
instruction <= instruction;
sram_we_n <= 1'b1;
sram_q <= 16'hffff;
sram_addr <= sram_addr;// infered latch
end
DIV: begin
pc <= pc + 16'd1;
instruction <= instruction;
sram_we_n <= 1'b1;
sram_q <= 16'hffff;
sram_addr <= sram_addr;// infered latch
end
MOD: begin
pc <= pc + 16'd1;
instruction <= instruction;
sram_we_n <= 1'b1;
sram_q <= 16'hffff;
sram_addr <= sram_addr;// infered latch
end
LTE: begin
pc <= pc + 16'd1;
instruction <= instruction;
sram_we_n <= 1'b1;
sram_q <= 16'hffff;
sram_addr <= sram_addr;// infered latch
end
BLT: begin
pc <= pc;
instruction <= instruction;
sram_we_n <= 1'b1;
sram_q <= 16'hffff;
sram_addr <= sram_addr;// infered latch
end
BLE: begin
pc <= pc;
instruction <= instruction;
sram_we_n <= 1'b1;
sram_q <= 16'hffff;
sram_addr <= sram_addr;// infered latch
end
BEQ: begin
pc <= pc;
instruction <= instruction;
sram_we_n <= 1'b1;
sram_q <= 16'hffff;
sram_addr <= sram_addr;// infered latch
end
JUMP: begin
// move back 1 because previous instruction adds 1 to pc
// extend MSB beacuse jump is signed
pc <= pc + {jump[11],jump[11],jump[11],jump[11],jump} - 16'd1;
instruction <= instruction;
sram_we_n <= 1'b1;
sram_q <= 16'hffff;
// shortcut to save a clock cycle, no need to wait for pc to update
sram_addr <= pc + {jump[11],jump[11],jump[11],jump[11],jump} - 16'd1;// extend MSB beacuse jump is signed
end
JUMP2: begin
pc <= pc + 16'd1;
instruction <= instruction;
sram_we_n <= 1'b1;
sram_q <= 16'hffff;
// pc should be updated now
sram_addr <= pc;
end
BLT2: begin
if(alu_status == 16'd1) begin
pc <= pc + {12'd0, im};
sram_addr <= pc + {12'd0, im};
end else begin
pc <= pc;
sram_addr <= sram_addr;
end
instruction <= instruction;
sram_we_n <= 1'b1;
sram_q <= 16'hffff;
end
BLT3: begin
// made to look like BLE3
pc <= pc + 16'd1;
instruction <= instruction;
sram_we_n <= 1'b1;
sram_q <= 16'hffff;
sram_addr <= sram_addr;
end
BLE2: begin
if(alu_status == 16'd1) begin
pc <= pc + {12'd0, im};
sram_addr <= pc + {12'd0, im};
end else begin
pc <= pc; // + 16'd1;
sram_addr <= sram_addr;
end
instruction <= instruction;
sram_we_n <= 1'b1;
sram_q <= 16'hffff;
end
BLE3: begin
pc <= pc + 16'd1;
instruction <= instruction;
sram_we_n <= 1'b1;
sram_q <= 16'hffff;
sram_addr <= sram_addr;
end
BEQ2: begin
if(alu_status == 16'd0) begin
pc <= pc + {12'd0, im};
sram_addr <= pc + {12'd0, im};
end else begin
pc <= pc; // + 16'd1;
sram_addr <= sram_addr; //pc + 16'd1;
end
instruction <= instruction;
sram_we_n <= 1'b1;
sram_q <= 16'hffff;
end
BEQ3: begin
// made to look like BLE3
pc <= pc + 16'd1;
instruction <= instruction;
sram_we_n <= 1'b1;
sram_q <= 16'hffff;
sram_addr <= sram_addr;
end
default: begin
pc <= 16'd0; // reset program
instruction <= instruction;
sram_we_n <= 1'b1;
sram_q <= 16'hffff;
sram_addr <= sram_addr;// infered latch
end
endcase
end
end
always@(*) begin
case (state)
FETCH: begin
reg_addr_a = 4'hf;
reg_addr_b = 4'hf;
reg_addr_c = 4'hf;
reg_we = 1'b0;
alu_op = `alu_op_size'h0;
im_en = 1'b0;
end
DECODE: begin
reg_addr_a = 4'hf;
reg_addr_b = 4'hf;
reg_addr_c = 4'hf;
reg_we = 1'b0;
alu_op = `alu_op_size'h0;
im_en = 1'b0;
end
ADD: begin
reg_addr_a = op1;
reg_addr_b = op2;
reg_addr_c = op3;
reg_we = 1'b1;
alu_op = `alu_op_size'h0;
im_en = 1'b0;
end
ADDI: begin
reg_addr_a = 4'hx; // dont care
reg_addr_b = op2;
reg_addr_c = op3;
reg_we = 1'b1;
alu_op = `alu_op_size'h0;
im_en = 1'b1;
end
SUB: begin
reg_addr_a = op1;
reg_addr_b = op2;
reg_addr_c = op3;
reg_we = 1'b1;
alu_op = `alu_op_size'h1;
im_en = 1'b0;
end
SUBI: begin
reg_addr_a = 4'hx; // dont care
reg_addr_b = op2;
reg_addr_c = op3;
reg_we = 1'b1;
alu_op = `alu_op_size'h1;
im_en = 1'b1;
end
MULT: begin
reg_addr_a = op1;
reg_addr_b = op2;
reg_addr_c = op3;
reg_we = 1'b1;
alu_op = `alu_op_size'h2;
im_en = 1'b0;
end
SW: begin
reg_addr_a = op3; // output the data, will not go throguh alu because of immed field
reg_addr_b = op2; // op2 is the pointer
reg_addr_c = 4'hx; // dont care
reg_we = 1'b0;
alu_op = `alu_op_size'h0;
im_en = 1'b1;
end
SW2: begin
reg_addr_a = op3; // output the data, will not go throguh alu because of immed field
reg_addr_b = op2; // op2 is the pointer
reg_addr_c = 4'hx; // dont care
reg_we = 1'b0;
alu_op = `alu_op_size'h0;
im_en = 1'b1;
reg_we = 1'b0;
end
SW3: begin
reg_addr_a = op3; // output the data, will not go throguh alu because of immed field
reg_addr_b = op2; // op2 is the pointer
reg_addr_c = 4'hx; // dont care
reg_we = 1'b0;
alu_op = `alu_op_size'h0;
im_en = 1'b1;
reg_we = 1'b0;
end
SW4: begin
reg_addr_a = op3; // output the data, will not go throguh alu because of immed field
reg_addr_b = op2; // op2 is the pointer
reg_addr_c = 4'hx; // dont care
reg_we = 1'b0;
alu_op = `alu_op_size'h0;
im_en = 1'b1;
reg_we = 1'b0;
end
LW:begin
reg_addr_a = 4'hx; // dont care, the immed field is used
reg_addr_b = op2; // op2 is the pointer
reg_addr_c = op3; // op3 is the register addr to load into
alu_op = `alu_op_size'h0;
im_en = 1'b1;
reg_we = 1'b0;
end
LW2:begin
reg_addr_a = 4'hx; // dont care, the immed field is used
reg_addr_b = op2; // op2 is the pointer
reg_addr_c = op3; // op3 is the register addr to load into
alu_op = `alu_op_size'h0;
im_en = 1'b1;
reg_we = 1'b0;
end
LW3:begin
reg_addr_a = 4'hx; // dont care, the immed field is used
reg_addr_b = op2; // op2 is the pointer
reg_addr_c = op3; // op3 is the register addr to load into
reg_we = 1'b1;
alu_op = `alu_op_size'h0;
im_en = 1'b1;
end
LT: begin
reg_addr_a = op1;
reg_addr_b = op2;
reg_addr_c = op3;
reg_we = 1'b1;
alu_op = `alu_op_size'h6;
im_en = 1'b0;
end
NAND: begin
reg_addr_a = op1;
reg_addr_b = op2;
reg_addr_c = op3;
reg_we = 1'b1;
alu_op = `alu_op_size'h3;
im_en = 1'b0;
end
DIV: begin
reg_addr_a = op1;
reg_addr_b = op2;
reg_addr_c = op3;
reg_we = 1'b1;
alu_op = `alu_op_size'h4;
im_en = 1'b0;
end
MOD: begin
reg_addr_a = op1;
reg_addr_b = op2;
reg_addr_c = op3;
reg_we = 1'b1;
alu_op = `alu_op_size'h5;
im_en = 1'b0;
end
LTE: begin
reg_addr_a = op1;
reg_addr_b = op2;
reg_addr_c = op3;
reg_we = 1'b1;
alu_op = `alu_op_size'h7;
im_en = 1'b0;
end
BLT: begin
reg_addr_a = op3;
reg_addr_b = op2;
reg_addr_c = 4'hx;
reg_we = 1'b0;
alu_op = `alu_op_size'h6;
im_en = 1'b0;
end
BLE: begin
reg_addr_a = op3;
reg_addr_b = op2;
reg_addr_c = 4'hx;
reg_we = 1'b0;
alu_op = `alu_op_size'h7;
im_en = 1'b0;
end
BEQ: begin
reg_addr_a = op3;
reg_addr_b = op2;
reg_addr_c = 4'hx;
reg_we = 1'b0;
alu_op = `alu_op_size'h1;
im_en = 1'b0;
end
JUMP: begin
reg_addr_a = 4'hf;
reg_addr_b = 4'hf;
reg_addr_c = 4'hf;
reg_we = 1'b0;
alu_op = `alu_op_size'h0;
im_en = 1'b0;
end
JUMP2: begin
reg_addr_a = 4'hf;
reg_addr_b = 4'hf;
reg_addr_c = 4'hf;
reg_we = 1'b0;
alu_op = `alu_op_size'h0;
im_en = 1'b0;
end
BLT2: begin
reg_addr_a = 4'hf;
reg_addr_b = 4'hf;
reg_addr_c = 4'hf;
reg_we = 1'b0;
alu_op = `alu_op_size'h0;
im_en = 1'b0;
end
BLE2: begin
reg_addr_a = 4'hf;
reg_addr_b = 4'hf;
reg_addr_c = 4'hf;
reg_we = 1'b0;
alu_op = `alu_op_size'h0;
im_en = 1'b0;
end
BEQ2: begin
reg_addr_a = 4'hf;
reg_addr_b = 4'hf;
reg_addr_c = 4'hf;
reg_we = 1'b0;
alu_op = `alu_op_size'h0;
im_en = 1'b0;
end
BLT3: begin
reg_addr_a = 4'hf;
reg_addr_b = 4'hf;
reg_addr_c = 4'hf;
reg_we = 1'b0;
alu_op = `alu_op_size'h0;
im_en = 1'b0;
end
BLE3: begin
reg_addr_a = 4'hf;
reg_addr_b = 4'hf;
reg_addr_c = 4'hf;
reg_we = 1'b0;
alu_op = `alu_op_size'h0;
im_en = 1'b0;
end
BEQ3: begin
reg_addr_a = 4'hf;
reg_addr_b = 4'hf;
reg_addr_c = 4'hf;
reg_we = 1'b0;
alu_op = `alu_op_size'h0;
im_en = 1'b0;
end
default: begin
reg_addr_a = 4'hf;
reg_addr_b = 4'hf;
reg_addr_c = 4'hf;
reg_we = 1'b0;
alu_op = `alu_op_size'h0;
im_en = 1'b0;
end
endcase
end
endmodule |
module main(
input [7:0] pc,
output [7:0] pb,
output [7:0] pd,
input CS,
input CLK,
input RESET,
input RESET2,
input WR,
input RD,
input SLOWCLK,
input [1:0] fpgaID // Can be used to differentiate between FPGA's on single board
);
wire CLK1_internal;
wire CLK2_internal;
wire [7:0] pc_internal;
wire [7:0] pb_internal;
wire [7:0] pb_out;
wire [7:0] pd_internal;
wire [7:0] pb_out_delayed;
wire [7:0] pd_out;
wire input_full;
wire input_empty;
wire output_full;
wire output_empty;
wire locked;
wire input_empty_delay;
wire SLOW;
clock_generator clock_generator_instance
(// Clock in ports
.CLK_IN1(CLK), // IN
// Clock out ports
.CLK_OUT1(CLK1_internal), // OUT
.CLK_OUT2(CLK2_internal), // OUT
// Status and control signals
.RESET(RESET), // IN
.LOCKED(locked) // OUT
);
slower slower_instance
(
.CLK(CLK1_internal), //input CLK,
.SLOWCLK(SLOWCLK), //input SLOWCLK,
.RESET(RESET2), //input RESET,
.EN_OUT(SLOW) //output EN_OUT
);
io_queue input_queue (
.rst(RESET2), // input rst
.wr_clk(CLK1_internal), // input wr_clk
.rd_clk(CLK2_internal), // input rd_clk
.din(pc), // input [7 : 0] din
// .wr_en(CS && WR && SLOW), // input wr_en
.wr_en(WR && SLOW), // input wr_en
.rd_en(1'b1), // input rd_en
.dout(pc_internal), // output [7 : 0] dout
.full(input_full), // output full
.empty(input_empty) // output empty
);
wire [63:0] pc_internal_64;
wire [63:0] pb_internal_64;
wire [63:0] pb_internal_64_out;
wire srl_ready;
srl8_to_64 srl8_to_64_instance(
.clk(CLK2_internal), .enable(input_empty), .reset(RESET2), .dataIn(pc_internal), .ready(srl_ready), .result(pc_internal_64)
);
wire [67:0] Ktest;
descrypt_salt des_core(
.Din(64'h0),
.K(pc_internal_64 << 1),
.salt(12'b111001101111), // Static salt for now
.Kout(Ktest),
.CLK(CLK2_internal),
.L_out(pb_internal_64[63:32]),
.R_out(pb_internal_64[31:0])
);
wire converter_empty;
wire converter_empty_delay;
// For now tests only against non-zero key
// Exchanging pb_internal_64 and test value will create bruter
comparer comparer_instance(
//.Din({8'b0, Ktest[55:0]}),// input [width:0] Din,
//.test(pb_internal_64),
.Din(pb_internal_64),// input [width:0] Din,
.test({8'b0, Ktest[55:0]}),
.CLK(CLK2_internal),// input CLK,
.reset(RESET2),// input reset,
.Dout(pb_internal_64_out), // output [width:0] Dout,
.good(input_empty_delay)// output good
);
queue64_to_8 size_conversion (
.rst(RESET2), // input rst
.wr_clk(CLK2_internal), // input wr_clk
.rd_clk(CLK2_internal), // input rd_clk
.din(pb_internal_64_out), // input [63 : 0] din
.wr_en(~input_empty_delay), // input wr_en
.rd_en(1'b1), // input rd_en
.dout(pb_internal), // output [7 : 0] dout
.full(), // output full
.empty(converter_empty) // output empty
);
//srl Delay2_instance(
// CLK2_internal, 1'b1, input_empty, input_empty_delay, 4'b0001
// CLK2_internal, 1'b1, converter_empty, converter_empty_delay, 4'b0000
//);
io_queue output_queue (
.rst(RESET2), // input rst
.wr_clk(CLK2_internal), // input wr_clk
.rd_clk(CLK1_internal), // input rd_clk
.din(pb_internal), // input [7 : 0] din
.wr_en(~converter_empty), // input wr_en
.rd_en((CS && RD && SLOW)), // input rd_en
.dout(pb_out), // output [7 : 0] dout
.full(output_full), // output full
.empty(output_empty) // output empty
// .rd_data_count(pd_out)
);
///*
assign pd_out[7] = input_full;
assign pd_out[6] = input_empty;
assign pd_out[5] = output_full;
assign pd_out[4] = output_empty;
assign pd_out[3] = 1'b0;
assign pd_out[2] = 1'b0;
assign pd_out[1] = 1'b0;
assign pd_out[0] = locked;
//*/
assign pb = (CS==1) ? pb_out : 8'bZ;
assign pd = (CS==1) ? pd_out : 8'bZ;
endmodule |
module sky130_fd_sc_hdll__o22ai (
Y ,
A1,
A2,
B1,
B2
);
// Module ports
output Y ;
input A1;
input A2;
input B1;
input B2;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire nor0_out ;
wire nor1_out ;
wire or0_out_Y;
// Name Output Other arguments
nor nor0 (nor0_out , B1, B2 );
nor nor1 (nor1_out , A1, A2 );
or or0 (or0_out_Y, nor1_out, nor0_out);
buf buf0 (Y , or0_out_Y );
endmodule |
module outputs
wire [127 : 0] wsiM0_MData;
wire [31 : 0] wciS0_SData;
wire [15 : 0] wsiM0_MByteEn;
wire [11 : 0] wsiM0_MBurstLength;
wire [7 : 0] wsiM0_MReqInfo;
wire [2 : 0] wsiM0_MCmd;
wire [1 : 0] wciS0_SFlag, wciS0_SResp;
wire wciS0_SThreadBusy,
wsiM0_MBurstPrecise,
wsiM0_MReqLast,
wsiM0_MReset_n,
wsiS0_SReset_n,
wsiS0_SThreadBusy;
// inlined wires
wire [168 : 0] wsiM_reqFifo_x_wire_wget, wsiS_wsiReq_wget;
wire [127 : 0] wsi_Es_mData_w_wget;
wire [95 : 0] wsiM_extStatusW_wget, wsiS_extStatusW_wget;
wire [71 : 0] wci_wslv_wciReq_wget;
wire [33 : 0] wci_wslv_respF_x_wire_wget;
wire [31 : 0] wci_wci_Es_mAddr_w_wget, wci_wci_Es_mData_w_wget;
wire [15 : 0] wsi_Es_mByteEn_w_wget;
wire [11 : 0] wsi_Es_mBurstLength_w_wget;
wire [7 : 0] wsi_Es_mReqInfo_w_wget;
wire [3 : 0] wci_wci_Es_mByteEn_w_wget;
wire [2 : 0] wci_wci_Es_mCmd_w_wget,
wci_wslv_wEdge_wget,
wsi_Es_mCmd_w_wget;
wire wci_wci_Es_mAddrSpace_w_wget,
wci_wci_Es_mAddrSpace_w_whas,
wci_wci_Es_mAddr_w_whas,
wci_wci_Es_mByteEn_w_whas,
wci_wci_Es_mCmd_w_whas,
wci_wci_Es_mData_w_whas,
wci_wslv_ctlAckReg_1_wget,
wci_wslv_ctlAckReg_1_whas,
wci_wslv_reqF_r_clr_whas,
wci_wslv_reqF_r_deq_whas,
wci_wslv_reqF_r_enq_whas,
wci_wslv_respF_dequeueing_whas,
wci_wslv_respF_enqueueing_whas,
wci_wslv_respF_x_wire_whas,
wci_wslv_sFlagReg_1_wget,
wci_wslv_sFlagReg_1_whas,
wci_wslv_sThreadBusy_pw_whas,
wci_wslv_wEdge_whas,
wci_wslv_wciReq_whas,
wci_wslv_wci_cfrd_pw_whas,
wci_wslv_wci_cfwr_pw_whas,
wci_wslv_wci_ctrl_pw_whas,
wsiM_operateD_1_wget,
wsiM_operateD_1_whas,
wsiM_peerIsReady_1_wget,
wsiM_peerIsReady_1_whas,
wsiM_reqFifo_dequeueing_whas,
wsiM_reqFifo_enqueueing_whas,
wsiM_reqFifo_x_wire_whas,
wsiM_sThreadBusy_pw_whas,
wsiS_operateD_1_wget,
wsiS_operateD_1_whas,
wsiS_peerIsReady_1_wget,
wsiS_peerIsReady_1_whas,
wsiS_reqFifo_doResetClr_whas,
wsiS_reqFifo_doResetDeq_whas,
wsiS_reqFifo_doResetEnq_whas,
wsiS_reqFifo_r_clr_whas,
wsiS_reqFifo_r_deq_whas,
wsiS_reqFifo_r_enq_whas,
wsiS_sThreadBusy_dw_wget,
wsiS_sThreadBusy_dw_whas,
wsiS_wsiReq_whas,
wsi_Es_mBurstLength_w_whas,
wsi_Es_mBurstPrecise_w_whas,
wsi_Es_mByteEn_w_whas,
wsi_Es_mCmd_w_whas,
wsi_Es_mDataInfo_w_whas,
wsi_Es_mData_w_whas,
wsi_Es_mReqInfo_w_whas,
wsi_Es_mReqLast_w_whas;
// register biasValue
reg [31 : 0] biasValue;
wire [31 : 0] biasValue_D_IN;
wire biasValue_EN;
// register controlReg
reg [31 : 0] controlReg;
wire [31 : 0] controlReg_D_IN;
wire controlReg_EN;
// register wci_wslv_cEdge
reg [2 : 0] wci_wslv_cEdge;
wire [2 : 0] wci_wslv_cEdge_D_IN;
wire wci_wslv_cEdge_EN;
// register wci_wslv_cState
reg [2 : 0] wci_wslv_cState;
wire [2 : 0] wci_wslv_cState_D_IN;
wire wci_wslv_cState_EN;
// register wci_wslv_ctlAckReg
reg wci_wslv_ctlAckReg;
wire wci_wslv_ctlAckReg_D_IN, wci_wslv_ctlAckReg_EN;
// register wci_wslv_ctlOpActive
reg wci_wslv_ctlOpActive;
wire wci_wslv_ctlOpActive_D_IN, wci_wslv_ctlOpActive_EN;
// register wci_wslv_illegalEdge
reg wci_wslv_illegalEdge;
wire wci_wslv_illegalEdge_D_IN, wci_wslv_illegalEdge_EN;
// register wci_wslv_isReset_isInReset
reg wci_wslv_isReset_isInReset;
wire wci_wslv_isReset_isInReset_D_IN, wci_wslv_isReset_isInReset_EN;
// register wci_wslv_nState
reg [2 : 0] wci_wslv_nState;
reg [2 : 0] wci_wslv_nState_D_IN;
wire wci_wslv_nState_EN;
// register wci_wslv_reqF_countReg
reg [1 : 0] wci_wslv_reqF_countReg;
wire [1 : 0] wci_wslv_reqF_countReg_D_IN;
wire wci_wslv_reqF_countReg_EN;
// register wci_wslv_respF_cntr_r
reg [1 : 0] wci_wslv_respF_cntr_r;
wire [1 : 0] wci_wslv_respF_cntr_r_D_IN;
wire wci_wslv_respF_cntr_r_EN;
// register wci_wslv_respF_q_0
reg [33 : 0] wci_wslv_respF_q_0;
reg [33 : 0] wci_wslv_respF_q_0_D_IN;
wire wci_wslv_respF_q_0_EN;
// register wci_wslv_respF_q_1
reg [33 : 0] wci_wslv_respF_q_1;
reg [33 : 0] wci_wslv_respF_q_1_D_IN;
wire wci_wslv_respF_q_1_EN;
// register wci_wslv_sFlagReg
reg wci_wslv_sFlagReg;
wire wci_wslv_sFlagReg_D_IN, wci_wslv_sFlagReg_EN;
// register wci_wslv_sThreadBusy_d
reg wci_wslv_sThreadBusy_d;
wire wci_wslv_sThreadBusy_d_D_IN, wci_wslv_sThreadBusy_d_EN;
// register wsiM_burstKind
reg [1 : 0] wsiM_burstKind;
wire [1 : 0] wsiM_burstKind_D_IN;
wire wsiM_burstKind_EN;
// register wsiM_errorSticky
reg wsiM_errorSticky;
wire wsiM_errorSticky_D_IN, wsiM_errorSticky_EN;
// register wsiM_iMesgCount
reg [31 : 0] wsiM_iMesgCount;
wire [31 : 0] wsiM_iMesgCount_D_IN;
wire wsiM_iMesgCount_EN;
// register wsiM_isReset_isInReset
reg wsiM_isReset_isInReset;
wire wsiM_isReset_isInReset_D_IN, wsiM_isReset_isInReset_EN;
// register wsiM_operateD
reg wsiM_operateD;
wire wsiM_operateD_D_IN, wsiM_operateD_EN;
// register wsiM_pMesgCount
reg [31 : 0] wsiM_pMesgCount;
wire [31 : 0] wsiM_pMesgCount_D_IN;
wire wsiM_pMesgCount_EN;
// register wsiM_peerIsReady
reg wsiM_peerIsReady;
wire wsiM_peerIsReady_D_IN, wsiM_peerIsReady_EN;
// register wsiM_reqFifo_cntr_r
reg [1 : 0] wsiM_reqFifo_cntr_r;
wire [1 : 0] wsiM_reqFifo_cntr_r_D_IN;
wire wsiM_reqFifo_cntr_r_EN;
// register wsiM_reqFifo_q_0
reg [168 : 0] wsiM_reqFifo_q_0;
reg [168 : 0] wsiM_reqFifo_q_0_D_IN;
wire wsiM_reqFifo_q_0_EN;
// register wsiM_reqFifo_q_1
reg [168 : 0] wsiM_reqFifo_q_1;
reg [168 : 0] wsiM_reqFifo_q_1_D_IN;
wire wsiM_reqFifo_q_1_EN;
// register wsiM_sThreadBusy_d
reg wsiM_sThreadBusy_d;
wire wsiM_sThreadBusy_d_D_IN, wsiM_sThreadBusy_d_EN;
// register wsiM_statusR
reg [7 : 0] wsiM_statusR;
wire [7 : 0] wsiM_statusR_D_IN;
wire wsiM_statusR_EN;
// register wsiM_tBusyCount
reg [31 : 0] wsiM_tBusyCount;
wire [31 : 0] wsiM_tBusyCount_D_IN;
wire wsiM_tBusyCount_EN;
// register wsiM_trafficSticky
reg wsiM_trafficSticky;
wire wsiM_trafficSticky_D_IN, wsiM_trafficSticky_EN;
// register wsiS_burstKind
reg [1 : 0] wsiS_burstKind;
wire [1 : 0] wsiS_burstKind_D_IN;
wire wsiS_burstKind_EN;
// register wsiS_errorSticky
reg wsiS_errorSticky;
wire wsiS_errorSticky_D_IN, wsiS_errorSticky_EN;
// register wsiS_iMesgCount
reg [31 : 0] wsiS_iMesgCount;
wire [31 : 0] wsiS_iMesgCount_D_IN;
wire wsiS_iMesgCount_EN;
// register wsiS_isReset_isInReset
reg wsiS_isReset_isInReset;
wire wsiS_isReset_isInReset_D_IN, wsiS_isReset_isInReset_EN;
// register wsiS_mesgWordLength
reg [11 : 0] wsiS_mesgWordLength;
wire [11 : 0] wsiS_mesgWordLength_D_IN;
wire wsiS_mesgWordLength_EN;
// register wsiS_operateD
reg wsiS_operateD;
wire wsiS_operateD_D_IN, wsiS_operateD_EN;
// register wsiS_pMesgCount
reg [31 : 0] wsiS_pMesgCount;
wire [31 : 0] wsiS_pMesgCount_D_IN;
wire wsiS_pMesgCount_EN;
// register wsiS_peerIsReady
reg wsiS_peerIsReady;
wire wsiS_peerIsReady_D_IN, wsiS_peerIsReady_EN;
// register wsiS_reqFifo_countReg
reg [1 : 0] wsiS_reqFifo_countReg;
wire [1 : 0] wsiS_reqFifo_countReg_D_IN;
wire wsiS_reqFifo_countReg_EN;
// register wsiS_reqFifo_levelsValid
reg wsiS_reqFifo_levelsValid;
wire wsiS_reqFifo_levelsValid_D_IN, wsiS_reqFifo_levelsValid_EN;
// register wsiS_statusR
reg [7 : 0] wsiS_statusR;
wire [7 : 0] wsiS_statusR_D_IN;
wire wsiS_statusR_EN;
// register wsiS_tBusyCount
reg [31 : 0] wsiS_tBusyCount;
wire [31 : 0] wsiS_tBusyCount_D_IN;
wire wsiS_tBusyCount_EN;
// register wsiS_trafficSticky
reg wsiS_trafficSticky;
wire wsiS_trafficSticky_D_IN, wsiS_trafficSticky_EN;
// register wsiS_wordCount
reg [11 : 0] wsiS_wordCount;
wire [11 : 0] wsiS_wordCount_D_IN;
wire wsiS_wordCount_EN;
// ports of submodule wci_wslv_reqF
wire [71 : 0] wci_wslv_reqF_D_IN, wci_wslv_reqF_D_OUT;
wire wci_wslv_reqF_CLR,
wci_wslv_reqF_DEQ,
wci_wslv_reqF_EMPTY_N,
wci_wslv_reqF_ENQ;
// ports of submodule wsiS_reqFifo
wire [168 : 0] wsiS_reqFifo_D_IN, wsiS_reqFifo_D_OUT;
wire wsiS_reqFifo_CLR,
wsiS_reqFifo_DEQ,
wsiS_reqFifo_EMPTY_N,
wsiS_reqFifo_ENQ,
wsiS_reqFifo_FULL_N;
// rule scheduling signals
wire WILL_FIRE_RL_wci_cfrd,
WILL_FIRE_RL_wci_cfwr,
WILL_FIRE_RL_wci_ctrl_IsO,
WILL_FIRE_RL_wci_ctrl_OrE,
WILL_FIRE_RL_wci_wslv_ctl_op_complete,
WILL_FIRE_RL_wci_wslv_ctl_op_start,
WILL_FIRE_RL_wci_wslv_respF_both,
WILL_FIRE_RL_wci_wslv_respF_decCtr,
WILL_FIRE_RL_wci_wslv_respF_incCtr,
WILL_FIRE_RL_wsiM_reqFifo_both,
WILL_FIRE_RL_wsiM_reqFifo_decCtr,
WILL_FIRE_RL_wsiM_reqFifo_deq,
WILL_FIRE_RL_wsiM_reqFifo_incCtr,
WILL_FIRE_RL_wsiS_reqFifo_enq,
WILL_FIRE_RL_wsiS_reqFifo_reset;
// inputs to muxes for submodule ports
reg [33 : 0] MUX_wci_wslv_respF_q_0_write_1__VAL_2;
wire [168 : 0] MUX_wsiM_reqFifo_q_0_write_1__VAL_1,
MUX_wsiM_reqFifo_q_0_write_1__VAL_2,
MUX_wsiM_reqFifo_q_1_write_1__VAL_1;
wire [33 : 0] MUX_wci_wslv_respF_q_0_write_1__VAL_1,
MUX_wci_wslv_respF_q_1_write_1__VAL_1,
MUX_wci_wslv_respF_x_wire_wset_1__VAL_1,
MUX_wci_wslv_respF_x_wire_wset_1__VAL_2;
wire [1 : 0] MUX_wci_wslv_respF_cntr_r_write_1__VAL_2,
MUX_wsiM_reqFifo_cntr_r_write_1__VAL_1,
MUX_wsiM_reqFifo_cntr_r_write_1__VAL_2;
wire MUX_biasValue_write_1__SEL_1,
MUX_biasValue_write_1__SEL_2,
MUX_controlReg_write_1__SEL_1,
MUX_wci_wslv_illegalEdge_write_1__SEL_1,
MUX_wci_wslv_illegalEdge_write_1__VAL_1,
MUX_wci_wslv_respF_q_0_write_1__SEL_1,
MUX_wci_wslv_respF_q_0_write_1__SEL_2,
MUX_wci_wslv_respF_q_1_write_1__SEL_1,
MUX_wci_wslv_respF_q_1_write_1__SEL_2,
MUX_wsiM_reqFifo_q_0_write_1__SEL_1,
MUX_wsiM_reqFifo_q_0_write_1__SEL_2,
MUX_wsiM_reqFifo_q_1_write_1__SEL_1,
MUX_wsiM_reqFifo_q_1_write_1__SEL_2,
MUX_wsiS_reqFifo_levelsValid_write_1__SEL_3;
// remaining internal signals
reg [63 : 0] v__h11230, v__h11385, v__h3574, v__h3749, v__h3893;
reg [31 : 0] _theResult____h11369;
wire [127 : 0] x_data__h10099;
wire [31 : 0] rdat__h11459,
rdat__h11559,
rdat__h11573,
rdat__h11581,
rdat__h11587,
rdat__h11601,
rdat__h11609;
wire [15 : 0] x__h11463;
wire [1 : 0] wci_wslv_respF_cntr_r_8_MINUS_1___d27;
wire _dfoo1, _dfoo3, _dfoo5, _dfoo7;
// value method wciS0_sResp
assign wciS0_SResp = wci_wslv_respF_q_0[33:32] ;
// value method wciS0_sData
assign wciS0_SData = wci_wslv_respF_q_0[31:0] ;
// value method wciS0_sThreadBusy
assign wciS0_SThreadBusy =
wci_wslv_reqF_countReg > 2'd1 || wci_wslv_isReset_isInReset ;
// value method wciS0_sFlag
assign wciS0_SFlag = { 1'd1, wci_wslv_sFlagReg } ;
// value method wsiS0_sThreadBusy
assign wsiS0_SThreadBusy =
!wsiS_sThreadBusy_dw_whas || wsiS_sThreadBusy_dw_wget ;
// value method wsiS0_sReset_n
assign wsiS0_SReset_n = !wsiS_isReset_isInReset && wsiS_operateD ;
// value method wsiM0_mCmd
assign wsiM0_MCmd = wsiM_sThreadBusy_d ? 3'd0 : wsiM_reqFifo_q_0[168:166] ;
// value method wsiM0_mReqLast
assign wsiM0_MReqLast = !wsiM_sThreadBusy_d && wsiM_reqFifo_q_0[165] ;
// value method wsiM0_mBurstPrecise
assign wsiM0_MBurstPrecise = !wsiM_sThreadBusy_d && wsiM_reqFifo_q_0[164] ;
// value method wsiM0_mBurstLength
assign wsiM0_MBurstLength =
wsiM_sThreadBusy_d ? 12'd0 : wsiM_reqFifo_q_0[163:152] ;
// value method wsiM0_mData
assign wsiM0_MData = wsiM_reqFifo_q_0[151:24] ;
// value method wsiM0_mByteEn
assign wsiM0_MByteEn = wsiM_reqFifo_q_0[23:8] ;
// value method wsiM0_mReqInfo
assign wsiM0_MReqInfo = wsiM_sThreadBusy_d ? 8'd0 : wsiM_reqFifo_q_0[7:0] ;
// value method wsiM0_mReset_n
assign wsiM0_MReset_n = !wsiM_isReset_isInReset && wsiM_operateD ;
// submodule wci_wslv_reqF
SizedFIFO #(.p1width(32'd72),
.p2depth(32'd3),
.p3cntr_width(32'd1),
.guarded(32'd1)) wci_wslv_reqF(.RST(wciS0_MReset_n),
.CLK(wciS0_Clk),
.D_IN(wci_wslv_reqF_D_IN),
.ENQ(wci_wslv_reqF_ENQ),
.DEQ(wci_wslv_reqF_DEQ),
.CLR(wci_wslv_reqF_CLR),
.D_OUT(wci_wslv_reqF_D_OUT),
.FULL_N(),
.EMPTY_N(wci_wslv_reqF_EMPTY_N));
// submodule wsiS_reqFifo
SizedFIFO #(.p1width(32'd169),
.p2depth(32'd3),
.p3cntr_width(32'd1),
.guarded(32'd1)) wsiS_reqFifo(.RST(wciS0_MReset_n),
.CLK(wciS0_Clk),
.D_IN(wsiS_reqFifo_D_IN),
.ENQ(wsiS_reqFifo_ENQ),
.DEQ(wsiS_reqFifo_DEQ),
.CLR(wsiS_reqFifo_CLR),
.D_OUT(wsiS_reqFifo_D_OUT),
.FULL_N(wsiS_reqFifo_FULL_N),
.EMPTY_N(wsiS_reqFifo_EMPTY_N));
// rule RL_wci_wslv_ctl_op_start
assign WILL_FIRE_RL_wci_wslv_ctl_op_start =
wci_wslv_reqF_EMPTY_N && wci_wslv_wci_ctrl_pw_whas &&
!WILL_FIRE_RL_wci_wslv_ctl_op_complete ;
// rule RL_wci_ctrl_IsO
assign WILL_FIRE_RL_wci_ctrl_IsO =
wci_wslv_wci_ctrl_pw_whas &&
WILL_FIRE_RL_wci_wslv_ctl_op_start &&
wci_wslv_cState == 3'd1 &&
wci_wslv_reqF_D_OUT[36:34] == 3'd1 ;
// rule RL_wci_ctrl_OrE
assign WILL_FIRE_RL_wci_ctrl_OrE =
wci_wslv_wci_ctrl_pw_whas &&
WILL_FIRE_RL_wci_wslv_ctl_op_start &&
wci_wslv_cState == 3'd2 &&
wci_wslv_reqF_D_OUT[36:34] == 3'd3 ;
// rule RL_wci_cfwr
assign WILL_FIRE_RL_wci_cfwr =
wci_wslv_respF_cntr_r != 2'd2 && wci_wslv_reqF_EMPTY_N &&
wci_wslv_wci_cfwr_pw_whas &&
!WILL_FIRE_RL_wci_wslv_ctl_op_start &&
!WILL_FIRE_RL_wci_wslv_ctl_op_complete ;
// rule RL_wci_wslv_ctl_op_complete
assign WILL_FIRE_RL_wci_wslv_ctl_op_complete =
wci_wslv_respF_cntr_r != 2'd2 && wci_wslv_ctlOpActive &&
wci_wslv_ctlAckReg ;
// rule RL_wci_cfrd
assign WILL_FIRE_RL_wci_cfrd =
wci_wslv_respF_cntr_r != 2'd2 && wci_wslv_reqF_EMPTY_N &&
wci_wslv_wci_cfrd_pw_whas &&
!WILL_FIRE_RL_wci_wslv_ctl_op_start &&
!WILL_FIRE_RL_wci_wslv_ctl_op_complete ;
// rule RL_wci_wslv_respF_incCtr
assign WILL_FIRE_RL_wci_wslv_respF_incCtr =
wci_wslv_respF_x_wire_whas && wci_wslv_respF_enqueueing_whas &&
!(wci_wslv_respF_cntr_r != 2'd0) ;
// rule RL_wci_wslv_respF_decCtr
assign WILL_FIRE_RL_wci_wslv_respF_decCtr =
wci_wslv_respF_cntr_r != 2'd0 &&
!wci_wslv_respF_enqueueing_whas ;
// rule RL_wci_wslv_respF_both
assign WILL_FIRE_RL_wci_wslv_respF_both =
wci_wslv_respF_x_wire_whas && wci_wslv_respF_cntr_r != 2'd0 &&
wci_wslv_respF_enqueueing_whas ;
// rule RL_wsiM_reqFifo_deq
assign WILL_FIRE_RL_wsiM_reqFifo_deq =
wsiM_reqFifo_cntr_r != 2'd0 && !wsiM_sThreadBusy_d ;
// rule RL_wsiM_reqFifo_incCtr
assign WILL_FIRE_RL_wsiM_reqFifo_incCtr =
MUX_wsiS_reqFifo_levelsValid_write_1__SEL_3 &&
MUX_wsiS_reqFifo_levelsValid_write_1__SEL_3 &&
!WILL_FIRE_RL_wsiM_reqFifo_deq ;
// rule RL_wsiM_reqFifo_decCtr
assign WILL_FIRE_RL_wsiM_reqFifo_decCtr =
WILL_FIRE_RL_wsiM_reqFifo_deq &&
!MUX_wsiS_reqFifo_levelsValid_write_1__SEL_3 ;
// rule RL_wsiM_reqFifo_both
assign WILL_FIRE_RL_wsiM_reqFifo_both =
MUX_wsiS_reqFifo_levelsValid_write_1__SEL_3 &&
WILL_FIRE_RL_wsiM_reqFifo_deq &&
MUX_wsiS_reqFifo_levelsValid_write_1__SEL_3 ;
// rule RL_wsiS_reqFifo_enq
assign WILL_FIRE_RL_wsiS_reqFifo_enq =
wsiS_reqFifo_FULL_N && wsiS_operateD && wsiS_peerIsReady &&
wsiS_wsiReq_wget[168:166] == 3'd1 ;
// rule RL_wsiS_reqFifo_reset
assign WILL_FIRE_RL_wsiS_reqFifo_reset =
WILL_FIRE_RL_wsiS_reqFifo_enq ||
MUX_wsiS_reqFifo_levelsValid_write_1__SEL_3 ;
// inputs to muxes for submodule ports
assign MUX_biasValue_write_1__SEL_1 =
WILL_FIRE_RL_wci_cfwr && wci_wslv_reqF_D_OUT[39:32] == 8'h0 ;
assign MUX_biasValue_write_1__SEL_2 =
wci_wslv_wci_ctrl_pw_whas &&
WILL_FIRE_RL_wci_wslv_ctl_op_start &&
wci_wslv_cState == 3'd0 &&
wci_wslv_reqF_D_OUT[36:34] == 3'd0 ;
assign MUX_controlReg_write_1__SEL_1 =
WILL_FIRE_RL_wci_cfwr && wci_wslv_reqF_D_OUT[39:32] == 8'h04 ;
assign MUX_wci_wslv_illegalEdge_write_1__SEL_1 =
WILL_FIRE_RL_wci_wslv_ctl_op_start &&
(wci_wslv_reqF_D_OUT[36:34] == 3'd0 && wci_wslv_cState != 3'd0 ||
wci_wslv_reqF_D_OUT[36:34] == 3'd1 && wci_wslv_cState != 3'd1 &&
wci_wslv_cState != 3'd3 ||
wci_wslv_reqF_D_OUT[36:34] == 3'd2 && wci_wslv_cState != 3'd2 ||
wci_wslv_reqF_D_OUT[36:34] == 3'd3 && wci_wslv_cState != 3'd3 &&
wci_wslv_cState != 3'd2 &&
wci_wslv_cState != 3'd1 ||
wci_wslv_reqF_D_OUT[36:34] == 3'd4 ||
wci_wslv_reqF_D_OUT[36:34] == 3'd5 ||
wci_wslv_reqF_D_OUT[36:34] == 3'd6 ||
wci_wslv_reqF_D_OUT[36:34] == 3'd7) ;
assign MUX_wci_wslv_respF_q_0_write_1__SEL_1 =
WILL_FIRE_RL_wci_wslv_respF_both && _dfoo3 ;
assign MUX_wci_wslv_respF_q_0_write_1__SEL_2 =
WILL_FIRE_RL_wci_wslv_respF_incCtr &&
wci_wslv_respF_cntr_r == 2'd0 ;
assign MUX_wci_wslv_respF_q_1_write_1__SEL_1 =
WILL_FIRE_RL_wci_wslv_respF_both && _dfoo1 ;
assign MUX_wci_wslv_respF_q_1_write_1__SEL_2 =
WILL_FIRE_RL_wci_wslv_respF_incCtr &&
wci_wslv_respF_cntr_r == 2'd1 ;
assign MUX_wsiM_reqFifo_q_0_write_1__SEL_1 =
WILL_FIRE_RL_wsiM_reqFifo_both && _dfoo7 ;
assign MUX_wsiM_reqFifo_q_0_write_1__SEL_2 =
WILL_FIRE_RL_wsiM_reqFifo_incCtr && wsiM_reqFifo_cntr_r == 2'd0 ;
assign MUX_wsiM_reqFifo_q_1_write_1__SEL_1 =
WILL_FIRE_RL_wsiM_reqFifo_both && _dfoo5 ;
assign MUX_wsiM_reqFifo_q_1_write_1__SEL_2 =
WILL_FIRE_RL_wsiM_reqFifo_incCtr && wsiM_reqFifo_cntr_r == 2'd1 ;
assign MUX_wsiS_reqFifo_levelsValid_write_1__SEL_3 =
wsiM_reqFifo_cntr_r != 2'd2 && wsiS_reqFifo_EMPTY_N &&
wci_wslv_cState == 3'd2 ;
assign MUX_wci_wslv_illegalEdge_write_1__VAL_1 =
wci_wslv_reqF_D_OUT[36:34] != 3'd4 &&
wci_wslv_reqF_D_OUT[36:34] != 3'd5 &&
wci_wslv_reqF_D_OUT[36:34] != 3'd6 ;
assign MUX_wci_wslv_respF_cntr_r_write_1__VAL_2 =
wci_wslv_respF_cntr_r + 2'd1 ;
assign MUX_wci_wslv_respF_q_0_write_1__VAL_1 =
(wci_wslv_respF_cntr_r == 2'd1) ?
MUX_wci_wslv_respF_q_0_write_1__VAL_2 :
wci_wslv_respF_q_1 ;
always@(WILL_FIRE_RL_wci_wslv_ctl_op_complete or
MUX_wci_wslv_respF_x_wire_wset_1__VAL_1 or
WILL_FIRE_RL_wci_cfrd or
MUX_wci_wslv_respF_x_wire_wset_1__VAL_2 or WILL_FIRE_RL_wci_cfwr)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_wci_wslv_ctl_op_complete:
MUX_wci_wslv_respF_q_0_write_1__VAL_2 =
MUX_wci_wslv_respF_x_wire_wset_1__VAL_1;
WILL_FIRE_RL_wci_cfrd:
MUX_wci_wslv_respF_q_0_write_1__VAL_2 =
MUX_wci_wslv_respF_x_wire_wset_1__VAL_2;
WILL_FIRE_RL_wci_cfwr:
MUX_wci_wslv_respF_q_0_write_1__VAL_2 = 34'h1C0DE4201;
default: MUX_wci_wslv_respF_q_0_write_1__VAL_2 =
34'h2AAAAAAAA /* unspecified value */ ;
endcase
end
assign MUX_wci_wslv_respF_q_1_write_1__VAL_1 =
(wci_wslv_respF_cntr_r == 2'd2) ?
MUX_wci_wslv_respF_q_0_write_1__VAL_2 :
34'h0AAAAAAAA ;
assign MUX_wci_wslv_respF_x_wire_wset_1__VAL_1 =
wci_wslv_illegalEdge ? 34'h3C0DE4202 : 34'h1C0DE4201 ;
assign MUX_wci_wslv_respF_x_wire_wset_1__VAL_2 =
{ 2'd1, _theResult____h11369 } ;
assign MUX_wsiM_reqFifo_cntr_r_write_1__VAL_1 = wsiM_reqFifo_cntr_r - 2'd1 ;
assign MUX_wsiM_reqFifo_cntr_r_write_1__VAL_2 = wsiM_reqFifo_cntr_r + 2'd1 ;
assign MUX_wsiM_reqFifo_q_0_write_1__VAL_1 =
(wsiM_reqFifo_cntr_r == 2'd1) ?
MUX_wsiM_reqFifo_q_0_write_1__VAL_2 :
wsiM_reqFifo_q_1 ;
assign MUX_wsiM_reqFifo_q_0_write_1__VAL_2 =
{ wsiS_reqFifo_D_OUT[168:152],
x_data__h10099,
wsiS_reqFifo_D_OUT[23:0] } ;
assign MUX_wsiM_reqFifo_q_1_write_1__VAL_1 =
(wsiM_reqFifo_cntr_r == 2'd2) ?
MUX_wsiM_reqFifo_q_0_write_1__VAL_2 :
169'h00000AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA00 ;
// inlined wires
assign wci_wslv_wciReq_wget =
{ wciS0_MCmd,
wciS0_MAddrSpace,
wciS0_MByteEn,
wciS0_MAddr,
wciS0_MData } ;
assign wci_wslv_wciReq_whas = 1'd1 ;
assign wci_wslv_respF_x_wire_wget = MUX_wci_wslv_respF_q_0_write_1__VAL_2 ;
assign wci_wslv_respF_x_wire_whas =
WILL_FIRE_RL_wci_wslv_ctl_op_complete || WILL_FIRE_RL_wci_cfrd ||
WILL_FIRE_RL_wci_cfwr ;
assign wci_wslv_wEdge_wget = wci_wslv_reqF_D_OUT[36:34] ;
assign wci_wslv_wEdge_whas = WILL_FIRE_RL_wci_wslv_ctl_op_start ;
assign wci_wslv_sFlagReg_1_wget = 1'b0 ;
assign wci_wslv_sFlagReg_1_whas = 1'b0 ;
assign wci_wslv_ctlAckReg_1_wget = 1'd1 ;
assign wci_wslv_ctlAckReg_1_whas =
WILL_FIRE_RL_wci_ctrl_OrE || WILL_FIRE_RL_wci_ctrl_IsO ||
MUX_biasValue_write_1__SEL_2 ;
assign wci_wci_Es_mCmd_w_wget = wciS0_MCmd ;
assign wci_wci_Es_mCmd_w_whas = 1'd1 ;
assign wci_wci_Es_mAddrSpace_w_wget = wciS0_MAddrSpace ;
assign wci_wci_Es_mAddrSpace_w_whas = 1'd1 ;
assign wci_wci_Es_mByteEn_w_wget = wciS0_MByteEn ;
assign wci_wci_Es_mByteEn_w_whas = 1'd1 ;
assign wci_wci_Es_mAddr_w_wget = wciS0_MAddr ;
assign wci_wci_Es_mAddr_w_whas = 1'd1 ;
assign wci_wci_Es_mData_w_wget = wciS0_MData ;
assign wci_wci_Es_mData_w_whas = 1'd1 ;
assign wsiS_wsiReq_wget =
{ wsiS0_MCmd,
wsiS0_MReqLast,
wsiS0_MBurstPrecise,
wsiS0_MBurstLength,
wsiS0_MData,
wsiS0_MByteEn,
wsiS0_MReqInfo } ;
assign wsiS_wsiReq_whas = 1'd1 ;
assign wsiS_operateD_1_wget = 1'd1 ;
assign wsiS_operateD_1_whas = wci_wslv_cState == 3'd2 ;
assign wsiS_peerIsReady_1_wget = 1'd1 ;
assign wsiS_peerIsReady_1_whas = wsiS0_MReset_n ;
assign wsiS_sThreadBusy_dw_wget = wsiS_reqFifo_countReg > 2'd1 ;
assign wsiS_sThreadBusy_dw_whas =
wsiS_reqFifo_levelsValid && wsiS_operateD && wsiS_peerIsReady ;
assign wsiM_reqFifo_x_wire_wget = MUX_wsiM_reqFifo_q_0_write_1__VAL_2 ;
assign wsiM_reqFifo_x_wire_whas =
MUX_wsiS_reqFifo_levelsValid_write_1__SEL_3 ;
assign wsiM_operateD_1_wget = 1'd1 ;
assign wsiM_operateD_1_whas = wci_wslv_cState == 3'd2 ;
assign wsiM_peerIsReady_1_wget = 1'd1 ;
assign wsiM_peerIsReady_1_whas = wsiM0_SReset_n ;
assign wsi_Es_mCmd_w_wget = wsiS0_MCmd ;
assign wsi_Es_mCmd_w_whas = 1'd1 ;
assign wsi_Es_mBurstLength_w_wget = wsiS0_MBurstLength ;
assign wsi_Es_mBurstLength_w_whas = 1'd1 ;
assign wsi_Es_mData_w_wget = wsiS0_MData ;
assign wsi_Es_mData_w_whas = 1'd1 ;
assign wsi_Es_mByteEn_w_wget = wsiS0_MByteEn ;
assign wsi_Es_mByteEn_w_whas = 1'd1 ;
assign wsi_Es_mReqInfo_w_wget = wsiS0_MReqInfo ;
assign wsi_Es_mReqInfo_w_whas = 1'd1 ;
assign wci_wslv_reqF_r_enq_whas = wci_wslv_wciReq_wget[71:69] != 3'd0 ;
assign wci_wslv_reqF_r_deq_whas =
WILL_FIRE_RL_wci_cfrd || WILL_FIRE_RL_wci_cfwr ||
WILL_FIRE_RL_wci_wslv_ctl_op_start ;
assign wci_wslv_reqF_r_clr_whas = 1'b0 ;
assign wci_wslv_respF_enqueueing_whas =
WILL_FIRE_RL_wci_cfrd || WILL_FIRE_RL_wci_cfwr ||
WILL_FIRE_RL_wci_wslv_ctl_op_complete ;
assign wci_wslv_respF_dequeueing_whas = wci_wslv_respF_cntr_r != 2'd0 ;
assign wci_wslv_sThreadBusy_pw_whas = 1'b0 ;
assign wci_wslv_wci_cfwr_pw_whas =
wci_wslv_reqF_EMPTY_N && wci_wslv_reqF_D_OUT[68] &&
wci_wslv_reqF_D_OUT[71:69] == 3'd1 ;
assign wci_wslv_wci_cfrd_pw_whas =
wci_wslv_reqF_EMPTY_N && wci_wslv_reqF_D_OUT[68] &&
wci_wslv_reqF_D_OUT[71:69] == 3'd2 ;
assign wci_wslv_wci_ctrl_pw_whas =
wci_wslv_reqF_EMPTY_N && !wci_wslv_reqF_D_OUT[68] &&
wci_wslv_reqF_D_OUT[71:69] == 3'd2 ;
assign wsiS_reqFifo_r_enq_whas = WILL_FIRE_RL_wsiS_reqFifo_enq ;
assign wsiS_reqFifo_r_deq_whas =
MUX_wsiS_reqFifo_levelsValid_write_1__SEL_3 ;
assign wsiS_reqFifo_r_clr_whas = 1'b0 ;
assign wsiS_reqFifo_doResetEnq_whas = WILL_FIRE_RL_wsiS_reqFifo_enq ;
assign wsiS_reqFifo_doResetDeq_whas =
MUX_wsiS_reqFifo_levelsValid_write_1__SEL_3 ;
assign wsiS_reqFifo_doResetClr_whas = 1'b0 ;
assign wsiM_reqFifo_enqueueing_whas =
MUX_wsiS_reqFifo_levelsValid_write_1__SEL_3 ;
assign wsiM_reqFifo_dequeueing_whas = WILL_FIRE_RL_wsiM_reqFifo_deq ;
assign wsiM_sThreadBusy_pw_whas = wsiM0_SThreadBusy ;
assign wsi_Es_mReqLast_w_whas = wsiS0_MReqLast ;
assign wsi_Es_mBurstPrecise_w_whas = wsiS0_MBurstPrecise ;
assign wsi_Es_mDataInfo_w_whas = 1'd1 ;
assign wsiS_extStatusW_wget =
{ wsiS_pMesgCount, wsiS_iMesgCount, wsiS_tBusyCount } ;
assign wsiM_extStatusW_wget =
{ wsiM_pMesgCount, wsiM_iMesgCount, wsiM_tBusyCount } ;
// register biasValue
assign biasValue_D_IN =
MUX_biasValue_write_1__SEL_1 ?
wci_wslv_reqF_D_OUT[31:0] :
32'd0 ;
assign biasValue_EN =
WILL_FIRE_RL_wci_cfwr && wci_wslv_reqF_D_OUT[39:32] == 8'h0 ||
MUX_biasValue_write_1__SEL_2 ;
// register controlReg
assign controlReg_D_IN =
MUX_controlReg_write_1__SEL_1 ?
wci_wslv_reqF_D_OUT[31:0] :
32'd0 ;
assign controlReg_EN =
WILL_FIRE_RL_wci_cfwr && wci_wslv_reqF_D_OUT[39:32] == 8'h04 ||
MUX_biasValue_write_1__SEL_2 ;
// register wci_wslv_cEdge
assign wci_wslv_cEdge_D_IN = wci_wslv_reqF_D_OUT[36:34] ;
assign wci_wslv_cEdge_EN = WILL_FIRE_RL_wci_wslv_ctl_op_start ;
// register wci_wslv_cState
assign wci_wslv_cState_D_IN = wci_wslv_nState ;
assign wci_wslv_cState_EN =
WILL_FIRE_RL_wci_wslv_ctl_op_complete && !wci_wslv_illegalEdge ;
// register wci_wslv_ctlAckReg
assign wci_wslv_ctlAckReg_D_IN = wci_wslv_ctlAckReg_1_whas ;
assign wci_wslv_ctlAckReg_EN = 1'd1 ;
// register wci_wslv_ctlOpActive
assign wci_wslv_ctlOpActive_D_IN = !WILL_FIRE_RL_wci_wslv_ctl_op_complete ;
assign wci_wslv_ctlOpActive_EN =
WILL_FIRE_RL_wci_wslv_ctl_op_complete ||
WILL_FIRE_RL_wci_wslv_ctl_op_start ;
// register wci_wslv_illegalEdge
assign wci_wslv_illegalEdge_D_IN =
MUX_wci_wslv_illegalEdge_write_1__SEL_1 &&
MUX_wci_wslv_illegalEdge_write_1__VAL_1 ;
assign wci_wslv_illegalEdge_EN =
MUX_wci_wslv_illegalEdge_write_1__SEL_1 ||
WILL_FIRE_RL_wci_wslv_ctl_op_complete && wci_wslv_illegalEdge ;
// register wci_wslv_isReset_isInReset
assign wci_wslv_isReset_isInReset_D_IN = 1'd0 ;
assign wci_wslv_isReset_isInReset_EN = wci_wslv_isReset_isInReset ;
// register wci_wslv_nState
always@(wci_wslv_reqF_D_OUT)
begin
case (wci_wslv_reqF_D_OUT[36:34])
3'd0: wci_wslv_nState_D_IN = 3'd1;
3'd1: wci_wslv_nState_D_IN = 3'd2;
3'd2: wci_wslv_nState_D_IN = 3'd3;
default: wci_wslv_nState_D_IN = 3'd0;
endcase
end
assign wci_wslv_nState_EN =
WILL_FIRE_RL_wci_wslv_ctl_op_start &&
(wci_wslv_reqF_D_OUT[36:34] == 3'd0 && wci_wslv_cState == 3'd0 ||
wci_wslv_reqF_D_OUT[36:34] == 3'd1 &&
(wci_wslv_cState == 3'd1 || wci_wslv_cState == 3'd3) ||
wci_wslv_reqF_D_OUT[36:34] == 3'd2 && wci_wslv_cState == 3'd2 ||
wci_wslv_reqF_D_OUT[36:34] == 3'd3 &&
(wci_wslv_cState == 3'd3 || wci_wslv_cState == 3'd2 ||
wci_wslv_cState == 3'd1)) ;
// register wci_wslv_reqF_countReg
assign wci_wslv_reqF_countReg_D_IN =
(wci_wslv_wciReq_wget[71:69] != 3'd0) ?
wci_wslv_reqF_countReg + 2'd1 :
wci_wslv_reqF_countReg - 2'd1 ;
assign wci_wslv_reqF_countReg_EN =
(wci_wslv_wciReq_wget[71:69] != 3'd0) !=
wci_wslv_reqF_r_deq_whas ;
// register wci_wslv_respF_cntr_r
assign wci_wslv_respF_cntr_r_D_IN =
WILL_FIRE_RL_wci_wslv_respF_decCtr ?
wci_wslv_respF_cntr_r_8_MINUS_1___d27 :
MUX_wci_wslv_respF_cntr_r_write_1__VAL_2 ;
assign wci_wslv_respF_cntr_r_EN =
WILL_FIRE_RL_wci_wslv_respF_decCtr ||
WILL_FIRE_RL_wci_wslv_respF_incCtr ;
// register wci_wslv_respF_q_0
always@(MUX_wci_wslv_respF_q_0_write_1__SEL_1 or
MUX_wci_wslv_respF_q_0_write_1__VAL_1 or
MUX_wci_wslv_respF_q_0_write_1__SEL_2 or
MUX_wci_wslv_respF_q_0_write_1__VAL_2 or
WILL_FIRE_RL_wci_wslv_respF_decCtr or wci_wslv_respF_q_1)
begin
case (1'b1) // synopsys parallel_case
MUX_wci_wslv_respF_q_0_write_1__SEL_1:
wci_wslv_respF_q_0_D_IN = MUX_wci_wslv_respF_q_0_write_1__VAL_1;
MUX_wci_wslv_respF_q_0_write_1__SEL_2:
wci_wslv_respF_q_0_D_IN = MUX_wci_wslv_respF_q_0_write_1__VAL_2;
WILL_FIRE_RL_wci_wslv_respF_decCtr:
wci_wslv_respF_q_0_D_IN = wci_wslv_respF_q_1;
default: wci_wslv_respF_q_0_D_IN =
34'h2AAAAAAAA /* unspecified value */ ;
endcase
end
assign wci_wslv_respF_q_0_EN =
WILL_FIRE_RL_wci_wslv_respF_both && _dfoo3 ||
WILL_FIRE_RL_wci_wslv_respF_incCtr &&
wci_wslv_respF_cntr_r == 2'd0 ||
WILL_FIRE_RL_wci_wslv_respF_decCtr ;
// register wci_wslv_respF_q_1
always@(MUX_wci_wslv_respF_q_1_write_1__SEL_1 or
MUX_wci_wslv_respF_q_1_write_1__VAL_1 or
MUX_wci_wslv_respF_q_1_write_1__SEL_2 or
MUX_wci_wslv_respF_q_0_write_1__VAL_2 or
WILL_FIRE_RL_wci_wslv_respF_decCtr)
begin
case (1'b1) // synopsys parallel_case
MUX_wci_wslv_respF_q_1_write_1__SEL_1:
wci_wslv_respF_q_1_D_IN = MUX_wci_wslv_respF_q_1_write_1__VAL_1;
MUX_wci_wslv_respF_q_1_write_1__SEL_2:
wci_wslv_respF_q_1_D_IN = MUX_wci_wslv_respF_q_0_write_1__VAL_2;
WILL_FIRE_RL_wci_wslv_respF_decCtr:
wci_wslv_respF_q_1_D_IN = 34'h0AAAAAAAA;
default: wci_wslv_respF_q_1_D_IN =
34'h2AAAAAAAA /* unspecified value */ ;
endcase
end
assign wci_wslv_respF_q_1_EN =
WILL_FIRE_RL_wci_wslv_respF_both && _dfoo1 ||
WILL_FIRE_RL_wci_wslv_respF_incCtr &&
wci_wslv_respF_cntr_r == 2'd1 ||
WILL_FIRE_RL_wci_wslv_respF_decCtr ;
// register wci_wslv_sFlagReg
assign wci_wslv_sFlagReg_D_IN = 1'b0 ;
assign wci_wslv_sFlagReg_EN = 1'd1 ;
// register wci_wslv_sThreadBusy_d
assign wci_wslv_sThreadBusy_d_D_IN = 1'b0 ;
assign wci_wslv_sThreadBusy_d_EN = 1'd1 ;
// register wsiM_burstKind
assign wsiM_burstKind_D_IN =
(wsiM_burstKind == 2'd0) ?
(wsiM_reqFifo_q_0[164] ? 2'd1 : 2'd2) :
2'd0 ;
assign wsiM_burstKind_EN =
WILL_FIRE_RL_wsiM_reqFifo_deq &&
wsiM_reqFifo_q_0[168:166] == 3'd1 &&
(wsiM_burstKind == 2'd0 ||
(wsiM_burstKind == 2'd1 || wsiM_burstKind == 2'd2) &&
wsiM_reqFifo_q_0[165]) ;
// register wsiM_errorSticky
assign wsiM_errorSticky_D_IN = 1'b0 ;
assign wsiM_errorSticky_EN = 1'b0 ;
// register wsiM_iMesgCount
assign wsiM_iMesgCount_D_IN = wsiM_iMesgCount + 32'd1 ;
assign wsiM_iMesgCount_EN =
WILL_FIRE_RL_wsiM_reqFifo_deq &&
wsiM_reqFifo_q_0[168:166] == 3'd1 &&
wsiM_burstKind == 2'd2 &&
wsiM_reqFifo_q_0[165] ;
// register wsiM_isReset_isInReset
assign wsiM_isReset_isInReset_D_IN = 1'd0 ;
assign wsiM_isReset_isInReset_EN = wsiM_isReset_isInReset ;
// register wsiM_operateD
assign wsiM_operateD_D_IN = wci_wslv_cState == 3'd2 ;
assign wsiM_operateD_EN = 1'd1 ;
// register wsiM_pMesgCount
assign wsiM_pMesgCount_D_IN = wsiM_pMesgCount + 32'd1 ;
assign wsiM_pMesgCount_EN =
WILL_FIRE_RL_wsiM_reqFifo_deq &&
wsiM_reqFifo_q_0[168:166] == 3'd1 &&
wsiM_burstKind == 2'd1 &&
wsiM_reqFifo_q_0[165] ;
// register wsiM_peerIsReady
assign wsiM_peerIsReady_D_IN = wsiM0_SReset_n ;
assign wsiM_peerIsReady_EN = 1'd1 ;
// register wsiM_reqFifo_cntr_r
assign wsiM_reqFifo_cntr_r_D_IN =
WILL_FIRE_RL_wsiM_reqFifo_decCtr ?
MUX_wsiM_reqFifo_cntr_r_write_1__VAL_1 :
MUX_wsiM_reqFifo_cntr_r_write_1__VAL_2 ;
assign wsiM_reqFifo_cntr_r_EN =
WILL_FIRE_RL_wsiM_reqFifo_decCtr ||
WILL_FIRE_RL_wsiM_reqFifo_incCtr ;
// register wsiM_reqFifo_q_0
always@(MUX_wsiM_reqFifo_q_0_write_1__SEL_1 or
MUX_wsiM_reqFifo_q_0_write_1__VAL_1 or
MUX_wsiM_reqFifo_q_0_write_1__SEL_2 or
MUX_wsiM_reqFifo_q_0_write_1__VAL_2 or
WILL_FIRE_RL_wsiM_reqFifo_decCtr or wsiM_reqFifo_q_1)
begin
case (1'b1) // synopsys parallel_case
MUX_wsiM_reqFifo_q_0_write_1__SEL_1:
wsiM_reqFifo_q_0_D_IN = MUX_wsiM_reqFifo_q_0_write_1__VAL_1;
MUX_wsiM_reqFifo_q_0_write_1__SEL_2:
wsiM_reqFifo_q_0_D_IN = MUX_wsiM_reqFifo_q_0_write_1__VAL_2;
WILL_FIRE_RL_wsiM_reqFifo_decCtr:
wsiM_reqFifo_q_0_D_IN = wsiM_reqFifo_q_1;
default: wsiM_reqFifo_q_0_D_IN =
169'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
assign wsiM_reqFifo_q_0_EN =
WILL_FIRE_RL_wsiM_reqFifo_both && _dfoo7 ||
WILL_FIRE_RL_wsiM_reqFifo_incCtr &&
wsiM_reqFifo_cntr_r == 2'd0 ||
WILL_FIRE_RL_wsiM_reqFifo_decCtr ;
// register wsiM_reqFifo_q_1
always@(MUX_wsiM_reqFifo_q_1_write_1__SEL_1 or
MUX_wsiM_reqFifo_q_1_write_1__VAL_1 or
MUX_wsiM_reqFifo_q_1_write_1__SEL_2 or
MUX_wsiM_reqFifo_q_0_write_1__VAL_2 or
WILL_FIRE_RL_wsiM_reqFifo_decCtr)
begin
case (1'b1) // synopsys parallel_case
MUX_wsiM_reqFifo_q_1_write_1__SEL_1:
wsiM_reqFifo_q_1_D_IN = MUX_wsiM_reqFifo_q_1_write_1__VAL_1;
MUX_wsiM_reqFifo_q_1_write_1__SEL_2:
wsiM_reqFifo_q_1_D_IN = MUX_wsiM_reqFifo_q_0_write_1__VAL_2;
WILL_FIRE_RL_wsiM_reqFifo_decCtr:
wsiM_reqFifo_q_1_D_IN =
169'h00000AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA00;
default: wsiM_reqFifo_q_1_D_IN =
169'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
assign wsiM_reqFifo_q_1_EN =
WILL_FIRE_RL_wsiM_reqFifo_both && _dfoo5 ||
WILL_FIRE_RL_wsiM_reqFifo_incCtr &&
wsiM_reqFifo_cntr_r == 2'd1 ||
WILL_FIRE_RL_wsiM_reqFifo_decCtr ;
// register wsiM_sThreadBusy_d
assign wsiM_sThreadBusy_d_D_IN = wsiM0_SThreadBusy ;
assign wsiM_sThreadBusy_d_EN = 1'd1 ;
// register wsiM_statusR
assign wsiM_statusR_D_IN =
{ wsiM_isReset_isInReset,
!wsiM_peerIsReady,
!wsiM_operateD,
wsiM_errorSticky,
wsiM_burstKind != 2'd0,
wsiM_sThreadBusy_d,
1'd0,
wsiM_trafficSticky } ;
assign wsiM_statusR_EN = 1'd1 ;
// register wsiM_tBusyCount
assign wsiM_tBusyCount_D_IN = wsiM_tBusyCount + 32'd1 ;
assign wsiM_tBusyCount_EN =
wsiM_operateD && wsiM_peerIsReady && wsiM_sThreadBusy_d ;
// register wsiM_trafficSticky
assign wsiM_trafficSticky_D_IN = 1'd1 ;
assign wsiM_trafficSticky_EN =
WILL_FIRE_RL_wsiM_reqFifo_deq &&
wsiM_reqFifo_q_0[168:166] == 3'd1 ;
// register wsiS_burstKind
assign wsiS_burstKind_D_IN =
(wsiS_burstKind == 2'd0) ?
(wsiS_wsiReq_wget[164] ? 2'd1 : 2'd2) :
2'd0 ;
assign wsiS_burstKind_EN =
WILL_FIRE_RL_wsiS_reqFifo_enq &&
(wsiS_burstKind == 2'd0 ||
(wsiS_burstKind == 2'd1 || wsiS_burstKind == 2'd2) &&
wsiS_wsiReq_wget[165]) ;
// register wsiS_errorSticky
assign wsiS_errorSticky_D_IN = 1'b0 ;
assign wsiS_errorSticky_EN = 1'b0 ;
// register wsiS_iMesgCount
assign wsiS_iMesgCount_D_IN = wsiS_iMesgCount + 32'd1 ;
assign wsiS_iMesgCount_EN =
WILL_FIRE_RL_wsiS_reqFifo_enq && wsiS_burstKind == 2'd2 &&
wsiS_wsiReq_wget[165] ;
// register wsiS_isReset_isInReset
assign wsiS_isReset_isInReset_D_IN = 1'd0 ;
assign wsiS_isReset_isInReset_EN = wsiS_isReset_isInReset ;
// register wsiS_mesgWordLength
assign wsiS_mesgWordLength_D_IN = wsiS_wordCount ;
assign wsiS_mesgWordLength_EN =
WILL_FIRE_RL_wsiS_reqFifo_enq && wsiS_wsiReq_wget[165] ;
// register wsiS_operateD
assign wsiS_operateD_D_IN = wci_wslv_cState == 3'd2 ;
assign wsiS_operateD_EN = 1'd1 ;
// register wsiS_pMesgCount
assign wsiS_pMesgCount_D_IN = wsiS_pMesgCount + 32'd1 ;
assign wsiS_pMesgCount_EN =
WILL_FIRE_RL_wsiS_reqFifo_enq && wsiS_burstKind == 2'd1 &&
wsiS_wsiReq_wget[165] ;
// register wsiS_peerIsReady
assign wsiS_peerIsReady_D_IN = wsiS0_MReset_n ;
assign wsiS_peerIsReady_EN = 1'd1 ;
// register wsiS_reqFifo_countReg
assign wsiS_reqFifo_countReg_D_IN =
WILL_FIRE_RL_wsiS_reqFifo_enq ?
wsiS_reqFifo_countReg + 2'd1 :
wsiS_reqFifo_countReg - 2'd1 ;
assign wsiS_reqFifo_countReg_EN =
WILL_FIRE_RL_wsiS_reqFifo_enq !=
MUX_wsiS_reqFifo_levelsValid_write_1__SEL_3 ;
// register wsiS_reqFifo_levelsValid
assign wsiS_reqFifo_levelsValid_D_IN = WILL_FIRE_RL_wsiS_reqFifo_reset ;
assign wsiS_reqFifo_levelsValid_EN =
wsiM_reqFifo_cntr_r != 2'd2 && wsiS_reqFifo_EMPTY_N &&
wci_wslv_cState == 3'd2 ||
WILL_FIRE_RL_wsiS_reqFifo_enq ||
WILL_FIRE_RL_wsiS_reqFifo_reset ;
// register wsiS_statusR
assign wsiS_statusR_D_IN =
{ wsiS_isReset_isInReset,
!wsiS_peerIsReady,
!wsiS_operateD,
wsiS_errorSticky,
wsiS_burstKind != 2'd0,
!wsiS_sThreadBusy_dw_whas || wsiS_sThreadBusy_dw_wget,
1'd0,
wsiS_trafficSticky } ;
assign wsiS_statusR_EN = 1'd1 ;
// register wsiS_tBusyCount
assign wsiS_tBusyCount_D_IN = wsiS_tBusyCount + 32'd1 ;
assign wsiS_tBusyCount_EN =
wsiS_operateD && wsiS_peerIsReady &&
(!wsiS_sThreadBusy_dw_whas || wsiS_sThreadBusy_dw_wget) ;
// register wsiS_trafficSticky
assign wsiS_trafficSticky_D_IN = 1'd1 ;
assign wsiS_trafficSticky_EN = WILL_FIRE_RL_wsiS_reqFifo_enq ;
// register wsiS_wordCount
assign wsiS_wordCount_D_IN =
wsiS_wsiReq_wget[165] ? 12'd1 : wsiS_wordCount + 12'd1 ;
assign wsiS_wordCount_EN = WILL_FIRE_RL_wsiS_reqFifo_enq ;
// submodule wci_wslv_reqF
assign wci_wslv_reqF_D_IN = wci_wslv_wciReq_wget ;
assign wci_wslv_reqF_ENQ = wci_wslv_wciReq_wget[71:69] != 3'd0 ;
assign wci_wslv_reqF_DEQ = wci_wslv_reqF_r_deq_whas ;
assign wci_wslv_reqF_CLR = 1'b0 ;
// submodule wsiS_reqFifo
assign wsiS_reqFifo_D_IN = wsiS_wsiReq_wget ;
assign wsiS_reqFifo_ENQ = WILL_FIRE_RL_wsiS_reqFifo_enq ;
assign wsiS_reqFifo_DEQ = MUX_wsiS_reqFifo_levelsValid_write_1__SEL_3 ;
assign wsiS_reqFifo_CLR = 1'b0 ;
// remaining internal signals
assign _dfoo1 =
wci_wslv_respF_cntr_r != 2'd2 ||
wci_wslv_respF_cntr_r_8_MINUS_1___d27 == 2'd1 ;
assign _dfoo3 =
wci_wslv_respF_cntr_r != 2'd1 ||
wci_wslv_respF_cntr_r_8_MINUS_1___d27 == 2'd0 ;
assign _dfoo5 =
wsiM_reqFifo_cntr_r != 2'd2 ||
MUX_wsiM_reqFifo_cntr_r_write_1__VAL_1 == 2'd1 ;
assign _dfoo7 =
wsiM_reqFifo_cntr_r != 2'd1 ||
MUX_wsiM_reqFifo_cntr_r_write_1__VAL_1 == 2'd0 ;
assign rdat__h11459 = hasDebugLogic ? { 16'd0, x__h11463 } : 32'd0 ;
assign rdat__h11559 = hasDebugLogic ? wsiS_extStatusW_wget[95:64] : 32'd0 ;
assign rdat__h11573 = hasDebugLogic ? wsiS_extStatusW_wget[63:32] : 32'd0 ;
assign rdat__h11581 = hasDebugLogic ? wsiS_extStatusW_wget[31:0] : 32'd0 ;
assign rdat__h11587 = hasDebugLogic ? wsiM_extStatusW_wget[95:64] : 32'd0 ;
assign rdat__h11601 = hasDebugLogic ? wsiM_extStatusW_wget[63:32] : 32'd0 ;
assign rdat__h11609 = hasDebugLogic ? wsiM_extStatusW_wget[31:0] : 32'd0 ;
assign wci_wslv_respF_cntr_r_8_MINUS_1___d27 =
wci_wslv_respF_cntr_r - 2'd1 ;
assign x__h11463 = { wsiS_statusR, wsiM_statusR } ;
assign x_data__h10099 =
{ wsiS_reqFifo_D_OUT[151:120] + biasValue,
wsiS_reqFifo_D_OUT[119:88] + biasValue,
wsiS_reqFifo_D_OUT[87:56] + biasValue,
wsiS_reqFifo_D_OUT[55:24] + biasValue } ;
always@(wci_wslv_reqF_D_OUT or
biasValue or
controlReg or
rdat__h11459 or
rdat__h11559 or
rdat__h11573 or
rdat__h11581 or rdat__h11587 or rdat__h11601 or rdat__h11609)
begin
case (wci_wslv_reqF_D_OUT[39:32])
8'h0: _theResult____h11369 = biasValue;
8'h04: _theResult____h11369 = controlReg;
8'h20: _theResult____h11369 = rdat__h11459;
8'h24: _theResult____h11369 = rdat__h11559;
8'h28: _theResult____h11369 = rdat__h11573;
8'h2C: _theResult____h11369 = rdat__h11581;
8'h30: _theResult____h11369 = rdat__h11587;
8'h34: _theResult____h11369 = rdat__h11601;
8'h38: _theResult____h11369 = rdat__h11609;
default: _theResult____h11369 = 32'd0;
endcase
end
// handling of inlined registers
always@(posedge wciS0_Clk)
begin
if (wciS0_MReset_n == `BSV_RESET_VALUE)
begin
wci_wslv_cEdge <= `BSV_ASSIGNMENT_DELAY 3'h2;
wci_wslv_cState <= `BSV_ASSIGNMENT_DELAY 3'd0;
wci_wslv_ctlAckReg <= `BSV_ASSIGNMENT_DELAY 1'd0;
wci_wslv_ctlOpActive <= `BSV_ASSIGNMENT_DELAY 1'd0;
wci_wslv_illegalEdge <= `BSV_ASSIGNMENT_DELAY 1'd0;
wci_wslv_nState <= `BSV_ASSIGNMENT_DELAY 3'd0;
wci_wslv_reqF_countReg <= `BSV_ASSIGNMENT_DELAY 2'd0;
wci_wslv_respF_cntr_r <= `BSV_ASSIGNMENT_DELAY 2'd0;
wci_wslv_respF_q_0 <= `BSV_ASSIGNMENT_DELAY 34'h0AAAAAAAA;
wci_wslv_respF_q_1 <= `BSV_ASSIGNMENT_DELAY 34'h0AAAAAAAA;
wci_wslv_sFlagReg <= `BSV_ASSIGNMENT_DELAY 1'd0;
wci_wslv_sThreadBusy_d <= `BSV_ASSIGNMENT_DELAY 1'd1;
wsiM_burstKind <= `BSV_ASSIGNMENT_DELAY 2'd0;
wsiM_errorSticky <= `BSV_ASSIGNMENT_DELAY 1'd0;
wsiM_iMesgCount <= `BSV_ASSIGNMENT_DELAY 32'd0;
wsiM_operateD <= `BSV_ASSIGNMENT_DELAY 1'd0;
wsiM_pMesgCount <= `BSV_ASSIGNMENT_DELAY 32'd0;
wsiM_peerIsReady <= `BSV_ASSIGNMENT_DELAY 1'd0;
wsiM_reqFifo_cntr_r <= `BSV_ASSIGNMENT_DELAY 2'd0;
wsiM_reqFifo_q_0 <= `BSV_ASSIGNMENT_DELAY
169'h00000AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA00;
wsiM_reqFifo_q_1 <= `BSV_ASSIGNMENT_DELAY
169'h00000AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA00;
wsiM_sThreadBusy_d <= `BSV_ASSIGNMENT_DELAY 1'd1;
wsiM_tBusyCount <= `BSV_ASSIGNMENT_DELAY 32'd0;
wsiM_trafficSticky <= `BSV_ASSIGNMENT_DELAY 1'd0;
wsiS_burstKind <= `BSV_ASSIGNMENT_DELAY 2'd0;
wsiS_errorSticky <= `BSV_ASSIGNMENT_DELAY 1'd0;
wsiS_iMesgCount <= `BSV_ASSIGNMENT_DELAY 32'd0;
wsiS_operateD <= `BSV_ASSIGNMENT_DELAY 1'd0;
wsiS_pMesgCount <= `BSV_ASSIGNMENT_DELAY 32'd0;
wsiS_peerIsReady <= `BSV_ASSIGNMENT_DELAY 1'd0;
wsiS_reqFifo_countReg <= `BSV_ASSIGNMENT_DELAY 2'd0;
wsiS_reqFifo_levelsValid <= `BSV_ASSIGNMENT_DELAY 1'd1;
wsiS_tBusyCount <= `BSV_ASSIGNMENT_DELAY 32'd0;
wsiS_trafficSticky <= `BSV_ASSIGNMENT_DELAY 1'd0;
wsiS_wordCount <= `BSV_ASSIGNMENT_DELAY 12'd1;
end
else
begin
if (wci_wslv_cEdge_EN)
wci_wslv_cEdge <= `BSV_ASSIGNMENT_DELAY wci_wslv_cEdge_D_IN;
if (wci_wslv_cState_EN)
wci_wslv_cState <= `BSV_ASSIGNMENT_DELAY wci_wslv_cState_D_IN;
if (wci_wslv_ctlAckReg_EN)
wci_wslv_ctlAckReg <= `BSV_ASSIGNMENT_DELAY wci_wslv_ctlAckReg_D_IN;
if (wci_wslv_ctlOpActive_EN)
wci_wslv_ctlOpActive <= `BSV_ASSIGNMENT_DELAY
wci_wslv_ctlOpActive_D_IN;
if (wci_wslv_illegalEdge_EN)
wci_wslv_illegalEdge <= `BSV_ASSIGNMENT_DELAY
wci_wslv_illegalEdge_D_IN;
if (wci_wslv_nState_EN)
wci_wslv_nState <= `BSV_ASSIGNMENT_DELAY wci_wslv_nState_D_IN;
if (wci_wslv_reqF_countReg_EN)
wci_wslv_reqF_countReg <= `BSV_ASSIGNMENT_DELAY
wci_wslv_reqF_countReg_D_IN;
if (wci_wslv_respF_cntr_r_EN)
wci_wslv_respF_cntr_r <= `BSV_ASSIGNMENT_DELAY
wci_wslv_respF_cntr_r_D_IN;
if (wci_wslv_respF_q_0_EN)
wci_wslv_respF_q_0 <= `BSV_ASSIGNMENT_DELAY wci_wslv_respF_q_0_D_IN;
if (wci_wslv_respF_q_1_EN)
wci_wslv_respF_q_1 <= `BSV_ASSIGNMENT_DELAY wci_wslv_respF_q_1_D_IN;
if (wci_wslv_sFlagReg_EN)
wci_wslv_sFlagReg <= `BSV_ASSIGNMENT_DELAY wci_wslv_sFlagReg_D_IN;
if (wci_wslv_sThreadBusy_d_EN)
wci_wslv_sThreadBusy_d <= `BSV_ASSIGNMENT_DELAY
wci_wslv_sThreadBusy_d_D_IN;
if (wsiM_burstKind_EN)
wsiM_burstKind <= `BSV_ASSIGNMENT_DELAY wsiM_burstKind_D_IN;
if (wsiM_errorSticky_EN)
wsiM_errorSticky <= `BSV_ASSIGNMENT_DELAY wsiM_errorSticky_D_IN;
if (wsiM_iMesgCount_EN)
wsiM_iMesgCount <= `BSV_ASSIGNMENT_DELAY wsiM_iMesgCount_D_IN;
if (wsiM_operateD_EN)
wsiM_operateD <= `BSV_ASSIGNMENT_DELAY wsiM_operateD_D_IN;
if (wsiM_pMesgCount_EN)
wsiM_pMesgCount <= `BSV_ASSIGNMENT_DELAY wsiM_pMesgCount_D_IN;
if (wsiM_peerIsReady_EN)
wsiM_peerIsReady <= `BSV_ASSIGNMENT_DELAY wsiM_peerIsReady_D_IN;
if (wsiM_reqFifo_cntr_r_EN)
wsiM_reqFifo_cntr_r <= `BSV_ASSIGNMENT_DELAY
wsiM_reqFifo_cntr_r_D_IN;
if (wsiM_reqFifo_q_0_EN)
wsiM_reqFifo_q_0 <= `BSV_ASSIGNMENT_DELAY wsiM_reqFifo_q_0_D_IN;
if (wsiM_reqFifo_q_1_EN)
wsiM_reqFifo_q_1 <= `BSV_ASSIGNMENT_DELAY wsiM_reqFifo_q_1_D_IN;
if (wsiM_sThreadBusy_d_EN)
wsiM_sThreadBusy_d <= `BSV_ASSIGNMENT_DELAY wsiM_sThreadBusy_d_D_IN;
if (wsiM_tBusyCount_EN)
wsiM_tBusyCount <= `BSV_ASSIGNMENT_DELAY wsiM_tBusyCount_D_IN;
if (wsiM_trafficSticky_EN)
wsiM_trafficSticky <= `BSV_ASSIGNMENT_DELAY wsiM_trafficSticky_D_IN;
if (wsiS_burstKind_EN)
wsiS_burstKind <= `BSV_ASSIGNMENT_DELAY wsiS_burstKind_D_IN;
if (wsiS_errorSticky_EN)
wsiS_errorSticky <= `BSV_ASSIGNMENT_DELAY wsiS_errorSticky_D_IN;
if (wsiS_iMesgCount_EN)
wsiS_iMesgCount <= `BSV_ASSIGNMENT_DELAY wsiS_iMesgCount_D_IN;
if (wsiS_operateD_EN)
wsiS_operateD <= `BSV_ASSIGNMENT_DELAY wsiS_operateD_D_IN;
if (wsiS_pMesgCount_EN)
wsiS_pMesgCount <= `BSV_ASSIGNMENT_DELAY wsiS_pMesgCount_D_IN;
if (wsiS_peerIsReady_EN)
wsiS_peerIsReady <= `BSV_ASSIGNMENT_DELAY wsiS_peerIsReady_D_IN;
if (wsiS_reqFifo_countReg_EN)
wsiS_reqFifo_countReg <= `BSV_ASSIGNMENT_DELAY
wsiS_reqFifo_countReg_D_IN;
if (wsiS_reqFifo_levelsValid_EN)
wsiS_reqFifo_levelsValid <= `BSV_ASSIGNMENT_DELAY
wsiS_reqFifo_levelsValid_D_IN;
if (wsiS_tBusyCount_EN)
wsiS_tBusyCount <= `BSV_ASSIGNMENT_DELAY wsiS_tBusyCount_D_IN;
if (wsiS_trafficSticky_EN)
wsiS_trafficSticky <= `BSV_ASSIGNMENT_DELAY wsiS_trafficSticky_D_IN;
if (wsiS_wordCount_EN)
wsiS_wordCount <= `BSV_ASSIGNMENT_DELAY wsiS_wordCount_D_IN;
end
if (biasValue_EN) biasValue <= `BSV_ASSIGNMENT_DELAY biasValue_D_IN;
if (controlReg_EN) controlReg <= `BSV_ASSIGNMENT_DELAY controlReg_D_IN;
if (wsiM_statusR_EN)
wsiM_statusR <= `BSV_ASSIGNMENT_DELAY wsiM_statusR_D_IN;
if (wsiS_mesgWordLength_EN)
wsiS_mesgWordLength <= `BSV_ASSIGNMENT_DELAY wsiS_mesgWordLength_D_IN;
if (wsiS_statusR_EN)
wsiS_statusR <= `BSV_ASSIGNMENT_DELAY wsiS_statusR_D_IN;
end
always@(posedge wciS0_Clk or `BSV_RESET_EDGE wciS0_MReset_n)
if (wciS0_MReset_n == `BSV_RESET_VALUE)
begin
wci_wslv_isReset_isInReset <= `BSV_ASSIGNMENT_DELAY 1'd1;
wsiM_isReset_isInReset <= `BSV_ASSIGNMENT_DELAY 1'd1;
wsiS_isReset_isInReset <= `BSV_ASSIGNMENT_DELAY 1'd1;
end
else
begin
if (wci_wslv_isReset_isInReset_EN)
wci_wslv_isReset_isInReset <= `BSV_ASSIGNMENT_DELAY
wci_wslv_isReset_isInReset_D_IN;
if (wsiM_isReset_isInReset_EN)
wsiM_isReset_isInReset <= `BSV_ASSIGNMENT_DELAY
wsiM_isReset_isInReset_D_IN;
if (wsiS_isReset_isInReset_EN)
wsiS_isReset_isInReset <= `BSV_ASSIGNMENT_DELAY
wsiS_isReset_isInReset_D_IN;
end
// synopsys translate_off
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
initial
begin
biasValue = 32'hAAAAAAAA;
controlReg = 32'hAAAAAAAA;
wci_wslv_cEdge = 3'h2;
wci_wslv_cState = 3'h2;
wci_wslv_ctlAckReg = 1'h0;
wci_wslv_ctlOpActive = 1'h0;
wci_wslv_illegalEdge = 1'h0;
wci_wslv_isReset_isInReset = 1'h0;
wci_wslv_nState = 3'h2;
wci_wslv_reqF_countReg = 2'h2;
wci_wslv_respF_cntr_r = 2'h2;
wci_wslv_respF_q_0 = 34'h2AAAAAAAA;
wci_wslv_respF_q_1 = 34'h2AAAAAAAA;
wci_wslv_sFlagReg = 1'h0;
wci_wslv_sThreadBusy_d = 1'h0;
wsiM_burstKind = 2'h2;
wsiM_errorSticky = 1'h0;
wsiM_iMesgCount = 32'hAAAAAAAA;
wsiM_isReset_isInReset = 1'h0;
wsiM_operateD = 1'h0;
wsiM_pMesgCount = 32'hAAAAAAAA;
wsiM_peerIsReady = 1'h0;
wsiM_reqFifo_cntr_r = 2'h2;
wsiM_reqFifo_q_0 = 169'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
wsiM_reqFifo_q_1 = 169'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
wsiM_sThreadBusy_d = 1'h0;
wsiM_statusR = 8'hAA;
wsiM_tBusyCount = 32'hAAAAAAAA;
wsiM_trafficSticky = 1'h0;
wsiS_burstKind = 2'h2;
wsiS_errorSticky = 1'h0;
wsiS_iMesgCount = 32'hAAAAAAAA;
wsiS_isReset_isInReset = 1'h0;
wsiS_mesgWordLength = 12'hAAA;
wsiS_operateD = 1'h0;
wsiS_pMesgCount = 32'hAAAAAAAA;
wsiS_peerIsReady = 1'h0;
wsiS_reqFifo_countReg = 2'h2;
wsiS_reqFifo_levelsValid = 1'h0;
wsiS_statusR = 8'hAA;
wsiS_tBusyCount = 32'hAAAAAAAA;
wsiS_trafficSticky = 1'h0;
wsiS_wordCount = 12'hAAA;
end
`endif // BSV_NO_INITIAL_BLOCKS
// synopsys translate_on
// handling of system tasks
// synopsys translate_off
always@(negedge wciS0_Clk)
begin
#0;
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_wslv_ctl_op_start)
begin
v__h3574 = $time;
#0;
end
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_wslv_ctl_op_start)
$display("[%0d]: %m: WCI ControlOp: Starting-transition edge:%x from:%x",
v__h3574,
wci_wslv_reqF_D_OUT[36:34],
wci_wslv_cState);
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (MUX_biasValue_write_1__SEL_2 && WILL_FIRE_RL_wci_ctrl_OrE)
$display("Error: \"bsv/wrk/BiasWorker.bsv\", line 67, column 48: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_ctrl_EiI] and\n [RL_wci_ctrl_OrE] ) fired in the same clock cycle.\n");
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (MUX_biasValue_write_1__SEL_2 && WILL_FIRE_RL_wci_ctrl_IsO)
$display("Error: \"bsv/wrk/BiasWorker.bsv\", line 67, column 48: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_ctrl_EiI] and\n [RL_wci_ctrl_IsO] ) fired in the same clock cycle.\n");
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_ctrl_IsO && WILL_FIRE_RL_wci_ctrl_OrE)
$display("Error: \"bsv/wrk/BiasWorker.bsv\", line 67, column 62: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_ctrl_IsO] and\n [RL_wci_ctrl_OrE] ) fired in the same clock cycle.\n");
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_cfwr)
begin
v__h11230 = $time;
#0;
end
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_cfwr)
$display("[%0d]: %m: WCI CONFIG WRITE Addr:%0x BE:%0x Data:%0x",
v__h11230,
wci_wslv_reqF_D_OUT[63:32],
wci_wslv_reqF_D_OUT[67:64],
wci_wslv_reqF_D_OUT[31:0]);
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_wslv_ctl_op_complete && wci_wslv_illegalEdge)
begin
v__h3893 = $time;
#0;
end
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_wslv_ctl_op_complete && wci_wslv_illegalEdge)
$display("[%0d]: %m: WCI ControlOp: ILLEGAL-EDGE Completed-transition edge:%x from:%x",
v__h3893,
wci_wslv_cEdge,
wci_wslv_cState);
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_wslv_ctl_op_complete && !wci_wslv_illegalEdge)
begin
v__h3749 = $time;
#0;
end
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_wslv_ctl_op_complete && !wci_wslv_illegalEdge)
$display("[%0d]: %m: WCI ControlOp: Completed-transition edge:%x from:%x to:%x",
v__h3749,
wci_wslv_cEdge,
wci_wslv_cState,
wci_wslv_nState);
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_cfrd)
begin
v__h11385 = $time;
#0;
end
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_cfrd)
$display("[%0d]: %m: WCI CONFIG READ Addr:%0x BE:%0x Data:%0x",
v__h11385,
wci_wslv_reqF_D_OUT[63:32],
wci_wslv_reqF_D_OUT[67:64],
_theResult____h11369);
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_cfwr && WILL_FIRE_RL_wci_ctrl_OrE)
$display("Error: \"bsv/wrk/BiasWorker.bsv\", line 67, column 28: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfwr] and\n [RL_wci_ctrl_OrE] ) fired in the same clock cycle.\n");
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_cfwr && WILL_FIRE_RL_wci_ctrl_IsO)
$display("Error: \"bsv/wrk/BiasWorker.bsv\", line 67, column 28: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfwr] and\n [RL_wci_ctrl_IsO] ) fired in the same clock cycle.\n");
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_cfwr && MUX_biasValue_write_1__SEL_2)
$display("Error: \"bsv/wrk/BiasWorker.bsv\", line 67, column 28: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfwr] and\n [RL_wci_ctrl_EiI] ) fired in the same clock cycle.\n");
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_cfwr && WILL_FIRE_RL_wci_cfrd)
$display("Error: \"bsv/wrk/BiasWorker.bsv\", line 67, column 28: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfwr] and [RL_wci_cfrd] )\n fired in the same clock cycle.\n");
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_cfrd && WILL_FIRE_RL_wci_ctrl_OrE)
$display("Error: \"bsv/wrk/BiasWorker.bsv\", line 67, column 38: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfrd] and\n [RL_wci_ctrl_OrE] ) fired in the same clock cycle.\n");
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_cfrd && WILL_FIRE_RL_wci_ctrl_IsO)
$display("Error: \"bsv/wrk/BiasWorker.bsv\", line 67, column 38: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfrd] and\n [RL_wci_ctrl_IsO] ) fired in the same clock cycle.\n");
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_cfrd && MUX_biasValue_write_1__SEL_2)
$display("Error: \"bsv/wrk/BiasWorker.bsv\", line 67, column 38: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfrd] and\n [RL_wci_ctrl_EiI] ) fired in the same clock cycle.\n");
end
// synopsys translate_on
endmodule |
module \$__ICE40_CARRY_WRAPPER (
(* abc9_carry *)
output CO,
output O,
input A, B,
(* abc9_carry *)
input CI,
input I0, I3
);
parameter LUT = 0;
parameter I3_IS_CI = 0;
wire I3_OR_CI = I3_IS_CI ? CI : I3;
SB_CARRY carry (
.I0(A),
.I1(B),
.CI(CI),
.CO(CO)
);
SB_LUT4 #(
.LUT_INIT(LUT)
) adder (
.I0(I0),
.I1(A),
.I2(B),
.I3(I3_OR_CI),
.O(O)
);
`ifdef ICE40_HX
specify
// https://github.com/cliffordwolf/icestorm/blob/be0bca0230d6fe1102e0a360b953fbb0d273a39f/icefuzz/timings_hx1k.txt#L79
(CI => CO) = (126, 105);
// https://github.com/cliffordwolf/icestorm/blob/be0bca0230d6fe1102e0a360b953fbb0d273a39f/icefuzz/timings_hx1k.txt#L80
(I0 => O) = (449, 386);
// https://github.com/cliffordwolf/icestorm/blob/be0bca0230d6fe1102e0a360b953fbb0d273a39f/icefuzz/timings_hx1k.txt#L82
(A => CO) = (259, 245);
// https://github.com/cliffordwolf/icestorm/blob/be0bca0230d6fe1102e0a360b953fbb0d273a39f/icefuzz/timings_hx1k.txt#L83
(A => O) = (400, 379);
// https://github.com/cliffordwolf/icestorm/blob/be0bca0230d6fe1102e0a360b953fbb0d273a39f/icefuzz/timings_hx1k.txt#L85
(B => CO) = (231, 133);
// https://github.com/cliffordwolf/icestorm/blob/be0bca0230d6fe1102e0a360b953fbb0d273a39f/icefuzz/timings_hx1k.txt#L86
(B => O) = (379, 351);
// https://github.com/cliffordwolf/icestorm/blob/be0bca0230d6fe1102e0a360b953fbb0d273a39f/icefuzz/timings_hx1k.txt#L88
(I3 => O) = (316, 288);
(CI => O) = (316, 288);
endspecify
`endif
`ifdef ICE40_LP
specify
// https://github.com/cliffordwolf/icestorm/blob/be0bca0230d6fe1102e0a360b953fbb0d273a39f/icefuzz/timings_lp1k.txt#L79
(CI => CO) = (186, 155);
// https://github.com/cliffordwolf/icestorm/blob/be0bca0230d6fe1102e0a360b953fbb0d273a39f/icefuzz/timings_lp1k.txt#L80
(I0 => O) = (662, 569);
// https://github.com/cliffordwolf/icestorm/blob/be0bca0230d6fe1102e0a360b953fbb0d273a39f/icefuzz/timings_lp1k.txt#L82
(A => CO) = (382, 362);
// https://github.com/cliffordwolf/icestorm/blob/be0bca0230d6fe1102e0a360b953fbb0d273a39f/icefuzz/timings_lp1k.txt#L83
(A => O) = (589, 558);
// https://github.com/cliffordwolf/icestorm/blob/be0bca0230d6fe1102e0a360b953fbb0d273a39f/icefuzz/timings_lp1k.txt#L85
(B => CO) = (341, 196);
// https://github.com/cliffordwolf/icestorm/blob/be0bca0230d6fe1102e0a360b953fbb0d273a39f/icefuzz/timings_lp1k.txt#L86
(B => O) = (558, 517);
// https://github.com/cliffordwolf/icestorm/blob/be0bca0230d6fe1102e0a360b953fbb0d273a39f/icefuzz/timings_lp1k.txt#L88
(I3 => O) = (465, 423);
(CI => O) = (465, 423);
endspecify
`endif
`ifdef ICE40_U
specify
// https://github.com/cliffordwolf/icestorm/blob/be0bca0230d6fe1102e0a360b953fbb0d273a39f/icefuzz/timings_up5k.txt#L91
(CI => CO) = (278, 278);
// https://github.com/cliffordwolf/icestorm/blob/be0bca0230d6fe1102e0a360b953fbb0d273a39f/icefuzz/timings_up5k.txt#L92
(I0 => O) = (1245, 1285);
// https://github.com/cliffordwolf/icestorm/blob/be0bca0230d6fe1102e0a360b953fbb0d273a39f/icefuzz/timings_up5k.txt#L94
(A => CO) = (675, 662);
// https://github.com/cliffordwolf/icestorm/blob/be0bca0230d6fe1102e0a360b953fbb0d273a39f/icefuzz/timings_up5k.txt#L95
(A => O) = (1179, 1232);
// https://github.com/cliffordwolf/icestorm/blob/be0bca0230d6fe1102e0a360b953fbb0d273a39f/icefuzz/timings_up5k.txt#L97
(B => CO) = (609, 358);
// https://github.com/cliffordwolf/icestorm/blob/be0bca0230d6fe1102e0a360b953fbb0d273a39f/icefuzz/timings_up5k.txt#L98
(B => O) = (1179, 1205);
// https://github.com/cliffordwolf/icestorm/blob/be0bca0230d6fe1102e0a360b953fbb0d273a39f/icefuzz/timings_up5k.txt#L100
(I3 => O) = (861, 874);
(CI => O) = (861, 874);
endspecify
`endif
endmodule |
module ps2_rx
(
input wire clk, reset,
inout wire ps2d, ps2c,
input wire rx_en,
output reg rx_done_tick,
output wire [7:0] dout
);
// symbolic state declaration
localparam [1:0]
idle = 2'b00,
dps = 2'b01,
load = 2'b10;
// signal declaration
reg [1:0] state_reg, state_next;
reg [7:0] filter_reg;
wire [7:0] filter_next;
reg f_ps2c_reg;
wire f_ps2c_next;
reg [3:0] n_reg, n_next;
reg [10:0] b_reg, b_next;
wire fall_edge;
// body
//=================================================
// filter and falling-edge tick generation for ps2c
//=================================================
always @(posedge clk, posedge reset)
if (reset)
begin
filter_reg <= 0;
f_ps2c_reg <= 0;
end
else
begin
filter_reg <= filter_next;
f_ps2c_reg <= f_ps2c_next;
end
assign filter_next = {ps2c, filter_reg[7:1]};
assign f_ps2c_next = (filter_reg==8'b11111111) ? 1'b1 :
(filter_reg==8'b00000000) ? 1'b0 :
f_ps2c_reg;
assign fall_edge = f_ps2c_reg & ~f_ps2c_next;
//=================================================
// FSMD
//=================================================
// FSMD state & data registers
always @(posedge clk, posedge reset)
if (reset)
begin
state_reg <= idle;
n_reg <= 0;
b_reg <= 0;
end
else
begin
state_reg <= state_next;
n_reg <= n_next;
b_reg <= b_next;
end
// FSMD next-state logic
always @*
begin
state_next = state_reg;
rx_done_tick = 1'b0;
n_next = n_reg;
b_next = b_reg;
case (state_reg)
idle:
if (fall_edge & rx_en)
begin
// shift in start bit
b_next = {ps2d, b_reg[10:1]};
n_next = 4'b1001;
state_next = dps;
end
dps: // 8 data + 1 parity + 1 stop
if (fall_edge)
begin
b_next = {ps2d, b_reg[10:1]};
if (n_reg==0)
state_next = load;
else
n_next = n_reg - 1'b1;
end
load: // 1 extra clock to complete the last shift
begin
state_next = idle;
rx_done_tick = 1'b1;
end
endcase
end
// output
assign dout = b_reg[8:1]; // data bits
endmodule |
module cpu(
input wire clk);
parameter NMEM = 20; // number in instruction memory
parameter IM_DATA = "im_data.txt";
wire regwrite_s5;
wire [4:0] wrreg_s5;
wire [31:0] wrdata_s5;
reg stall_s1_s2;
// {{{ diagnostic outputs
initial begin
if (`DEBUG_CPU_STAGES) begin
$display("if_pc, if_instr, id_regrs, id_regrt, ex_alua, ex_alub, ex_aluctl, mem_memdata, mem_memread, mem_memwrite, wb_regdata, wb_regwrite");
$monitor("%x, %x, %x, %x, %x, %x, %x, %x, %x, %x, %x, %x",
pc, /* if_pc */
inst, /* if_instr */
data1, /* id_regrs */
data2, /* id_regrt */
data1_s3, /* data1_s3 */
alusrc_data2, /* alusrc_data2 */
aluctl, /* ex_aluctl */
data2_s4, /* mem_memdata */
memread_s4, /* mem_memread */
memwrite_s4, /* mem_memwrite */
wrdata_s5, /* wb_regdata */
regwrite_s5 /* wb_regwrite */
);
end
end
// }}}
// {{{ flush control
reg flush_s1, flush_s2, flush_s3;
always @(*) begin
flush_s1 <= 1'b0;
flush_s2 <= 1'b0;
flush_s3 <= 1'b0;
if (pcsrc | jump_s4) begin
flush_s1 <= 1'b1;
flush_s2 <= 1'b1;
flush_s3 <= 1'b1;
end
end
// }}}
// {{{ stage 1, IF (fetch)
reg [31:0] pc;
initial begin
pc <= 32'd0;
end
wire [31:0] pc4; // PC + 4
assign pc4 = pc + 4;
always @(posedge clk) begin
if (stall_s1_s2)
pc <= pc;
else if (pcsrc == 1'b1)
pc <= baddr_s4;
else if (jump_s4 == 1'b1)
pc <= jaddr_s4;
else
pc <= pc4;
end
// pass PC + 4 to stage 2
wire [31:0] pc4_s2;
regr #(.N(32)) regr_pc4_s2(.clk(clk),
.hold(stall_s1_s2), .clear(flush_s1),
.in(pc4), .out(pc4_s2));
// instruction memory
wire [31:0] inst;
wire [31:0] inst_s2;
im #(.NMEM(NMEM), .IM_DATA(IM_DATA))
im1(.clk(clk), .addr(pc), .data(inst));
regr #(.N(32)) regr_im_s2(.clk(clk),
.hold(stall_s1_s2), .clear(flush_s1),
.in(inst), .out(inst_s2));
// }}}
// {{{ stage 2, ID (decode)
// decode instruction
wire [5:0] opcode;
wire [4:0] rs;
wire [4:0] rt;
wire [4:0] rd;
wire [15:0] imm;
wire [4:0] shamt;
wire [31:0] jaddr_s2;
wire [31:0] seimm; // sign extended immediate
//
assign opcode = inst_s2[31:26];
assign rs = inst_s2[25:21];
assign rt = inst_s2[20:16];
assign rd = inst_s2[15:11];
assign imm = inst_s2[15:0];
assign shamt = inst_s2[10:6];
assign jaddr_s2 = {pc[31:28], inst_s2[25:0], {2{1'b0}}};
assign seimm = {{16{inst_s2[15]}}, inst_s2[15:0]};
// register memory
wire [31:0] data1, data2;
regm regm1(.clk(clk), .read1(rs), .read2(rt),
.data1(data1), .data2(data2),
.regwrite(regwrite_s5), .wrreg(wrreg_s5),
.wrdata(wrdata_s5));
// pass rs to stage 3 (for forwarding)
wire [4:0] rs_s3;
regr #(.N(5)) regr_s2_rs(.clk(clk), .clear(1'b0), .hold(stall_s1_s2),
.in(rs), .out(rs_s3));
// transfer register data to stage 3
wire [31:0] data1_s3, data2_s3;
regr #(.N(64)) reg_s2_mem(.clk(clk), .clear(flush_s2), .hold(stall_s1_s2),
.in({data1, data2}),
.out({data1_s3, data2_s3}));
// transfer seimm, rt, and rd to stage 3
wire [31:0] seimm_s3;
wire [4:0] rt_s3;
wire [4:0] rd_s3;
regr #(.N(32)) reg_s2_seimm(.clk(clk), .clear(flush_s2), .hold(stall_s1_s2),
.in(seimm), .out(seimm_s3));
regr #(.N(10)) reg_s2_rt_rd(.clk(clk), .clear(flush_s2), .hold(stall_s1_s2),
.in({rt, rd}), .out({rt_s3, rd_s3}));
// transfer PC + 4 to stage 3
wire [31:0] pc4_s3;
regr #(.N(32)) reg_pc4_s2(.clk(clk), .clear(1'b0), .hold(stall_s1_s2),
.in(pc4_s2), .out(pc4_s3));
// control (opcode -> ...)
wire regdst;
wire branch_eq_s2;
wire branch_ne_s2;
wire memread;
wire memwrite;
wire memtoreg;
wire [1:0] aluop;
wire regwrite;
wire alusrc;
wire jump_s2;
//
control ctl1(.opcode(opcode), .regdst(regdst),
.branch_eq(branch_eq_s2), .branch_ne(branch_ne_s2),
.memread(memread),
.memtoreg(memtoreg), .aluop(aluop),
.memwrite(memwrite), .alusrc(alusrc),
.regwrite(regwrite), .jump(jump_s2));
// shift left, seimm
wire [31:0] seimm_sl2;
assign seimm_sl2 = {seimm[29:0], 2'b0}; // shift left 2 bits
// branch address
wire [31:0] baddr_s2;
assign baddr_s2 = pc4_s2 + seimm_sl2;
// transfer the control signals to stage 3
wire regdst_s3;
wire memread_s3;
wire memwrite_s3;
wire memtoreg_s3;
wire [1:0] aluop_s3;
wire regwrite_s3;
wire alusrc_s3;
// A bubble is inserted by setting all the control signals
// to zero (stall_s1_s2).
regr #(.N(8)) reg_s2_control(.clk(clk), .clear(stall_s1_s2), .hold(1'b0),
.in({regdst, memread, memwrite,
memtoreg, aluop, regwrite, alusrc}),
.out({regdst_s3, memread_s3, memwrite_s3,
memtoreg_s3, aluop_s3, regwrite_s3, alusrc_s3}));
wire branch_eq_s3, branch_ne_s3;
regr #(.N(2)) branch_s2_s3(.clk(clk), .clear(flush_s2), .hold(1'b0),
.in({branch_eq_s2, branch_ne_s2}),
.out({branch_eq_s3, branch_ne_s3}));
wire [31:0] baddr_s3;
regr #(.N(32)) baddr_s2_s3(.clk(clk), .clear(flush_s2), .hold(1'b0),
.in(baddr_s2), .out(baddr_s3));
wire jump_s3;
regr #(.N(1)) reg_jump_s3(.clk(clk), .clear(flush_s2), .hold(1'b0),
.in(jump_s2),
.out(jump_s3));
wire [31:0] jaddr_s3;
regr #(.N(32)) reg_jaddr_s3(.clk(clk), .clear(flush_s2), .hold(1'b0),
.in(jaddr_s2), .out(jaddr_s3));
// }}}
// {{{ stage 3, EX (execute)
// pass through some control signals to stage 4
wire regwrite_s4;
wire memtoreg_s4;
wire memread_s4;
wire memwrite_s4;
regr #(.N(4)) reg_s3(.clk(clk), .clear(flush_s2), .hold(1'b0),
.in({regwrite_s3, memtoreg_s3, memread_s3,
memwrite_s3}),
.out({regwrite_s4, memtoreg_s4, memread_s4,
memwrite_s4}));
// ALU
// second ALU input can come from an immediate value or data
wire [31:0] alusrc_data2;
assign alusrc_data2 = (alusrc_s3) ? seimm_s3 : fw_data2_s3;
// ALU control
wire [3:0] aluctl;
wire [5:0] funct;
assign funct = seimm_s3[5:0];
alu_control alu_ctl1(.funct(funct), .aluop(aluop_s3), .aluctl(aluctl));
// ALU
wire [31:0] alurslt;
reg [31:0] fw_data1_s3;
always @(*)
case (forward_a)
2'd1: fw_data1_s3 = alurslt_s4;
2'd2: fw_data1_s3 = wrdata_s5;
default: fw_data1_s3 = data1_s3;
endcase
wire zero_s3;
alu alu1(.ctl(aluctl), .a(fw_data1_s3), .b(alusrc_data2), .out(alurslt),
.zero(zero_s3));
wire zero_s4;
regr #(.N(1)) reg_zero_s3_s4(.clk(clk), .clear(1'b0), .hold(1'b0),
.in(zero_s3), .out(zero_s4));
// pass ALU result and zero to stage 4
wire [31:0] alurslt_s4;
regr #(.N(32)) reg_alurslt(.clk(clk), .clear(flush_s3), .hold(1'b0),
.in({alurslt}),
.out({alurslt_s4}));
// pass data2 to stage 4
wire [31:0] data2_s4;
reg [31:0] fw_data2_s3;
always @(*)
case (forward_b)
2'd1: fw_data2_s3 = alurslt_s4;
2'd2: fw_data2_s3 = wrdata_s5;
default: fw_data2_s3 = data2_s3;
endcase
regr #(.N(32)) reg_data2_s3(.clk(clk), .clear(flush_s3), .hold(1'b0),
.in(fw_data2_s3), .out(data2_s4));
// write register
wire [4:0] wrreg;
wire [4:0] wrreg_s4;
assign wrreg = (regdst_s3) ? rd_s3 : rt_s3;
// pass to stage 4
regr #(.N(5)) reg_wrreg(.clk(clk), .clear(flush_s3), .hold(1'b0),
.in(wrreg), .out(wrreg_s4));
wire branch_eq_s4, branch_ne_s4;
regr #(.N(2)) branch_s3_s4(.clk(clk), .clear(flush_s3), .hold(1'b0),
.in({branch_eq_s3, branch_ne_s3}),
.out({branch_eq_s4, branch_ne_s4}));
wire [31:0] baddr_s4;
regr #(.N(32)) baddr_s3_s4(.clk(clk), .clear(flush_s3), .hold(1'b0),
.in(baddr_s3), .out(baddr_s4));
wire jump_s4;
regr #(.N(1)) reg_jump_s4(.clk(clk), .clear(flush_s3), .hold(1'b0),
.in(jump_s3),
.out(jump_s4));
wire [31:0] jaddr_s4;
regr #(.N(32)) reg_jaddr_s4(.clk(clk), .clear(flush_s3), .hold(1'b0),
.in(jaddr_s3), .out(jaddr_s4));
// }}}
// {{{ stage 4, MEM (memory)
// pass regwrite and memtoreg to stage 5
wire memtoreg_s5;
regr #(.N(2)) reg_regwrite_s4(.clk(clk), .clear(1'b0), .hold(1'b0),
.in({regwrite_s4, memtoreg_s4}),
.out({regwrite_s5, memtoreg_s5}));
// data memory
wire [31:0] rdata;
dm dm1(.clk(clk), .addr(alurslt_s4[8:2]), .rd(memread_s4), .wr(memwrite_s4),
.wdata(data2_s4), .rdata(rdata));
// pass read data to stage 5
wire [31:0] rdata_s5;
regr #(.N(32)) reg_rdata_s4(.clk(clk), .clear(1'b0), .hold(1'b0),
.in(rdata),
.out(rdata_s5));
// pass alurslt to stage 5
wire [31:0] alurslt_s5;
regr #(.N(32)) reg_alurslt_s4(.clk(clk), .clear(1'b0), .hold(1'b0),
.in(alurslt_s4),
.out(alurslt_s5));
// pass wrreg to stage 5
regr #(.N(5)) reg_wrreg_s4(.clk(clk), .clear(1'b0), .hold(1'b0),
.in(wrreg_s4),
.out(wrreg_s5));
// branch
reg pcsrc;
always @(*) begin
case (1'b1)
branch_eq_s4: pcsrc <= zero_s4;
branch_ne_s4: pcsrc <= ~(zero_s4);
default: pcsrc <= 1'b0;
endcase
end
// }}}
// {{{ stage 5, WB (write back)
assign wrdata_s5 = (memtoreg_s5 == 1'b1) ? rdata_s5 : alurslt_s5;
// }}}
// {{{ forwarding
// stage 3 (MEM) -> stage 2 (EX)
// stage 4 (WB) -> stage 2 (EX)
reg [1:0] forward_a;
reg [1:0] forward_b;
always @(*) begin
// If the previous instruction (stage 4) would write,
// and it is a value we want to read (stage 3), forward it.
// data1 input to ALU
if ((regwrite_s4 == 1'b1) && (wrreg_s4 == rs_s3)) begin
forward_a <= 2'd1; // stage 4
end else if ((regwrite_s5 == 1'b1) && (wrreg_s5 == rs_s3)) begin
forward_a <= 2'd2; // stage 5
end else
forward_a <= 2'd0; // no forwarding
// data2 input to ALU
if ((regwrite_s4 == 1'b1) & (wrreg_s4 == rt_s3)) begin
forward_b <= 2'd1; // stage 5
end else if ((regwrite_s5 == 1'b1) && (wrreg_s5 == rt_s3)) begin
forward_b <= 2'd2; // stage 5
end else
forward_b <= 2'd0; // no forwarding
end
// }}}
// {{{ load use data hazard detection, signal stall
/* If an operation in stage 4 (MEM) loads from memory (e.g. lw)
* and the operation in stage 3 (EX) depends on this value,
* a stall must be performed. The memory read cannot
* be forwarded because memory access is too slow. It can
* be forwarded from stage 5 (WB) after a stall.
*
* lw $1, 16($10) ; I-type, rt_s3 = $1, memread_s3 = 1
* sw $1, 32($12) ; I-type, rt_s2 = $1, memread_s2 = 0
*
* lw $1, 16($3) ; I-type, rt_s3 = $1, memread_s3 = 1
* sw $2, 32($1) ; I-type, rt_s2 = $2, rs_s2 = $1, memread_s2 = 0
*
* lw $1, 16($3) ; I-type, rt_s3 = $1, memread_s3 = 1
* add $2, $1, $1 ; R-type, rs_s2 = $1, rt_s2 = $1, memread_s2 = 0
*/
always @(*) begin
if (memread_s3 == 1'b1 && ((rt == rt_s3) || (rs == rt_s3)) ) begin
stall_s1_s2 <= 1'b1; // perform a stall
end else
stall_s1_s2 <= 1'b0; // no stall
end
// }}}
endmodule |
module flash_dump (
input sys_clk_in,
output trx,
output [20:0] flash_addr,
input [15:0] flash_data,
output flash_we_n,
output flash_oe_n,
output flash_ce2
);
reg clk_9600;
reg [11:0] count_uart;
reg [ 6:0] dada_wr;
reg [ 7:0] estat;
reg [ 7:0] addr;
reg [ 2:0] espacios;
reg [ 6:0] char;
reg [ 3:0] nibble;
reg [ 7:0] col;
reg trx_req;
reg [ 7:0] adr0;
wire clk_60M;
wire rst, lock;
wire trx_ack;
wire [15:0] rd_data;
reg [15:0] ram[0:255];
reg [15:0] dades;
reg [ 3:0] count;
// Instanciacions de mòduls
clocks c0 (
.CLKIN_IN (sys_clk_in),
.CLKFX_OUT (clk_60M),
.LOCKED_OUT (lock)
);
uart_ctrl u0 (dada_wr, trx_req, trx_ack, trx,
rst, clk_9600);
// Assignacions contínues
assign rst = ~lock;
assign flash_addr = { `HIGH_BIOS, adr0 };
assign rd_data = flash_data;
assign flash_we_n = 1'b1;
assign flash_oe_n = 1'b0;
assign flash_ce2 = 1'b1;
// Descripció del comportament
// count_uart
always @(posedge clk_60M)
if (rst) count_uart <= 12'h0;
else count_uart <= (count_uart==12'd3124) ?
12'd0 : count_uart + 12'd1;
// clk_9600
always @(posedge clk_60M)
if (rst) clk_9600 <= 1'b0;
else clk_9600 <= (count_uart==12'd0) ?
!clk_9600 : clk_9600;
// adr0
always @(posedge clk_60M)
if (rst) adr0 <= 8'h00;
else adr0 <= (adr0==8'hff || count!=4'hf) ? adr0
: (adr0 + 8'h01);
// count
always @(posedge clk_60M)
if (rst) count <= 4'h0;
else count <= count + 4'h1;
// ram
always @(posedge clk_60M) ram[adr0] <= rd_data;
// dades
always @(posedge clk_60M)
if (rst) dades <= 16'h0;
else dades <= ram[addr];
always @(posedge clk_60M)
if (adr0!=8'hff)
begin
dada_wr <= 7'h30;
trx_req <= 0;
estat <= 8'd0;
addr <= 8'h00;
espacios <= 3'd2;
char <= 7'd00;
nibble <= 4'd0;
col <= 8'd79;
end
else
case (estat)
8'd00: if (~trx_ack)
begin estat <= 8'd01;
if (espacios > 3'd0)
begin char <= 7'h20; espacios <= espacios - 3'd1; end
else
begin
char <= ascii(nibble); espacios <= 3'd4;
nibble <= nibble + 4'd1;
end
end
8'd01: begin dada_wr <= char; trx_req <= 1; estat <= 8'd2; end
8'd02: if (trx_ack) begin trx_req <= 0; estat <= 8'd3; end
8'd03: if (col > 8'd0) begin col <= col - 8'd1; estat <= 8'd0; end
else estat <= 8'd04;
8'd04: if (~trx_ack) estat <= 8'd05;
8'd05: begin dada_wr <= ascii(addr[7:4]); trx_req <= 1; estat <= 8'd10; end
8'd10: if (trx_ack) begin trx_req <= 0; estat <= 8'd15; end
8'd15: if (~trx_ack) estat <= 8'd20;
8'd20: begin dada_wr <= ascii(dades[15:12]); trx_req <= 1; estat <= 8'd25; end
8'd25: if (trx_ack) begin trx_req <= 0; estat <= 8'd30; end
8'd30: if (~trx_ack) estat <= 8'd35;
8'd35: begin dada_wr <= ascii(dades[11:8]); trx_req <= 1; estat <= 8'd40; end
8'd40: if (trx_ack) begin trx_req <= 0; estat <= 8'd45; end
8'd45: if (~trx_ack) estat <= 8'd50;
8'd50: begin dada_wr <= ascii(dades[7:4]); trx_req <= 1; estat <= 8'd55; end
8'd55: if (trx_ack) begin trx_req <= 0; estat <= 8'd60; end
8'd60: if (~trx_ack) estat <= 8'd65;
8'd65: begin dada_wr <= ascii(dades[3:0]); trx_req <= 1; estat <= 8'd70; end
8'd70: if (trx_ack) begin trx_req <= 0; estat <= 8'd75; end
8'd75: if (addr[3:0] == 4'hf) estat <= 8'd90;
else if (~trx_ack) estat <= 8'd80;
8'd80: begin dada_wr <= 7'h20; trx_req <= 1; estat <= 8'd85; end
8'd85: if (trx_ack) begin trx_req <= 0; estat <= 8'd90; end
8'd90: if (addr < 9'h0ff) begin addr <= addr + 8'd1; estat <= 8'd91; end
else estat <= 8'd95;
8'd91: estat <= (addr[3:0]==4'h0) ? 8'd4 : 8'd15;
endcase
function [6:0] ascii(input [3:0] num);
if (num <= 4'd9) ascii = 7'h30 + num;
else ascii = 7'd87 + num;
endfunction
endmodule |
module tb_alu();
// ============================================================
/**
* Declare signal types for testbench to drive and monitor
* signals during the simulation of the ALU
*
* The reg data type holds a value until a new value is driven
* onto it in an "initial" or "always" block. It can only be
* assigned a value in an "always" or "initial" block, and is
* used to apply stimulus to the inputs of the DUT.
*
* The wire type is a passive data type that holds a value driven
* onto it by a port, assign statement or reg type. Wires cannot be
* assigned values inside "always" and "initial" blocks. They can
* be used to hold the values of the DUT's outputs
*/
// Declare "wire" signals: outputs from the DUT
// result output signal
wire [0:127] res;
// ============================================================
// Declare "reg" signals: inputs to the DUT
// reg_A
reg [0:127] r_A;
// reg_B
reg [0:127] r_B;
// Control signal bits - ppp; ctrl_ppp
reg [0:2] c_ppp;
// Control signal bits - ww; ctrl_ww
reg [0:1] c_ww;
/**
* Control signal bits - determine which arithmetic or logic
* operation to perform; alu_op
*/
reg [0:4] a_op;
// Bus/Signal to contain the expected output/result
reg [0:127] e_r;
// wrbyteen
reg [0:15] wbt;
// Dummy registers
//reg [0:15] a,b,c;
// ============================================================
// Defining constants: parameter [name_of_constant] = value;
//parameter size_of_input = 6'd32;
// ============================================================
/**
* Instantiate an instance of alu() so that
* inputs can be passed to the Device Under Test (DUT)
* Given instance name is "rg"
*/
alu a_l_u (
// instance_name(signal name),
// Signal name can be the same as the instance name
// alu (reg_A,reg_B,ctrl_ppp,ctrl_ww,alu_op,result)
r_A,r_B,c_ppp,c_ww,a_op,res,wbt);
// ============================================================
/**
* Initial block start executing sequentially @ t=0
* If and when a delay is encountered, the execution of this block
* pauses or waits until the delay time has passed, before resuming
* execution
*
* Each intial or always block executes concurrently; that is,
* multiple "always" or "initial" blocks will execute simultaneously
*
* E.g.
* always
* begin
* #10 clk_50 = ~clk_50; // Invert clock signal every 10 ns
* // Clock signal has a period of 20 ns or 50 MHz
* end
*/
initial
begin
// "$time" indicates the current time in the simulation
$display($time, " << Starting the simulation >>");
// aluwadd AND aa AND w8
r_A=128'h0102030405060708090a0b0c0d0e0f10;
r_B=128'h01020304010203040507070809050607;
e_r=128'h0204060806080a0c0e11121416131517;
c_ppp=`aa;
c_ww=`w8;
a_op=`aluwadd;
wbt=16'd0;
#10
// aluwadd AND aa AND w8
r_A=128'hfffffffffffffffffffffffffffffff9;
r_B=128'h00000000000000000000000000000008;
e_r=128'hffffffffffffffffffffffffffffff01;
c_ppp=`aa;
c_ww=`w8;
a_op=`aluwadd;
#10
// aluwadd AND aa AND w16
r_A=128'h00010002000300040005000600070008;
r_B=128'h0002000400060008000c001000120014;
e_r=128'h000300060009000c001100160019001c;
c_ppp=`aa;
c_ww=`w16;
a_op=`aluwadd;
#10
// aluwadd AND aa AND w32
r_A=128'h00000001000000020000000300000004;
r_B=128'h00000005000000060000000700000008;
e_r=128'h00000006000000080000000a0000000c;
c_ppp=`aa;
c_ww=`w32;
a_op=`aluwadd;
// ======================================
#10 //TIME=40
// aluwadd AND uu AND w8
r_A=128'h0102030405060708090a0b0c0d0f1011;
r_B=128'h01010202030303030405060104050601;
e_r=128'h0203050608090a0b0d10130d11141612;
// hhhhHHHHhhhhHHHHllllLLLLllllLLLL
c_ppp=`uu;
c_ww=`w8;
a_op=`aluwadd;
#10
// aluwadd AND uu AND w32
r_A=128'h00010002000300040005000600070008;
r_B=128'h00020002000300030001000100010003;
e_r=128'h0003000400060007000600070008000b;
// hhhhHHHHhhhhHHHHllllLLLLllllLLLL
c_ppp=`uu;
c_ww=`w16;
a_op=`aluwadd;
#10
// aluwadd AND uu AND w32
r_A=128'h00000001000000020000000300000004;
r_B=128'h00000005000000060000000700000008;
e_r=128'h00000006000000080000000100000002;
// hhhhHHHHhhhhHHHHllllLLLLllllLLLL
c_ppp=`uu;
c_ww=`w32;
a_op=`aluwadd;
// ======================================
#10 //TIME=70
// aluwadd AND dd AND w8
r_A=128'h090a0b0c0d0f10110102030405060708;
r_B=128'h04050601040506010101020203030303;
e_r=128'h0d10130d111416120203050608090a0b;
// hhhhHHHHhhhhHHHHllllLLLLllllLLLL
c_ppp=`dd;
c_ww=`w8;
a_op=`aluwadd;
#10
// aluwadd AND dd AND w32
r_A=128'h00050006000700080001000200030004;
r_B=128'h00010001000100030002000200030003;
e_r=128'h000600070008000b0003000400060007;
// hhhhHHHHhhhhHHHHllllLLLLllllLLLL
c_ppp=`dd;
c_ww=`w16;
a_op=`aluwadd;
#10
// aluwadd AND dd AND w32
r_A=128'h00000003000000040000000100000002;
r_B=128'h00000007000000080000000500000006;
e_r=128'h00000001000000020000000600000008;
// hhhhHHHHhhhhHHHHllllLLLLllllLLLL
c_ppp=`dd;
c_ww=`w32;
a_op=`aluwadd;
// ======================================
#10 //TIME=100
// aluwadd AND oo AND w8
r_A=128'h090a0b0c0d0f10110102030405060708;
r_B=128'h04050601040506010101020203030303;
e_r=128'hff0ffe0dfd14fc12fb03fa06f909f80b;
// hhhhHHHHhhhhHHHHllllLLLLllllLLLL
c_ppp=`oo;
c_ww=`w8;
a_op=`aluwadd;
#10
// aluwadd AND oo AND w32
r_A=128'h00050006000700080001000200030004;
r_B=128'h00010001000100030002000200030003;
e_r=128'he0010007e002000be0030004e0040007;
// hhhhHHHHhhhhHHHHllllLLLLllllLLLL
c_ppp=`oo;
c_ww=`w16;
a_op=`aluwadd;
#10
// aluwadd AND oo AND w32
r_A=128'h00000003000000040000000100000002;
r_B=128'h00000007000000080000000500000006;
e_r=128'hff0000f10000000cff0000f200000008;
// hhhhHHHHhhhhHHHHllllLLLLllllLLLL
c_ppp=`oo;
c_ww=`w32;
a_op=`aluwadd;
// ======================================
#10 //TIME=130
// aluwadd AND ee AND w8
r_A=128'h090a0b0c0d0f10110102030405060708;
r_B=128'h04050601040506010101020203030303;
e_r=128'h0dff11fe11fd16fc02fb05fa08f90afb;
// hhhhHHHHhhhhHHHHllllLLLLllllLLLL
c_ppp=`ee;
c_ww=`w8;
a_op=`aluwadd;
#10
// aluwadd AND ee AND w32
r_A=128'h00050006000700080001000200030004;
r_B=128'h00010001000100030002000200030003;
e_r=128'h0006e0010008e0020003e0030006e004;
// hhhhHHHHhhhhHHHHllllLLLLllllLLLL
c_ppp=`ee;
c_ww=`w16;
a_op=`aluwadd;
#10
// aluwadd AND ee AND w32
r_A=128'h00000003000000040000000100000002;
r_B=128'h00000007000000080000000500000006;
e_r=128'h0000000aff0000f100000006f200000d;
// hhhhHHHHhhhhHHHHllllLLLLllllLLLL
c_ppp=`ee;
c_ww=`w32;
a_op=`aluwadd;
// ======================================
#10 //TIME=160
// aluwadd AND mm AND w8
r_A=128'h090a0b0c0d0f10110102030405060708;
r_B=128'h04050601040506010101020203030303;
e_r=128'h0dff11ffdd004499bb7733ccdd221199;
// hhhhHHHHhhhhHHHHllllLLLLllllLLLL
c_ppp=`mm;
c_ww=`w8;
a_op=`aluwadd;
#10
// aluwadd AND mm AND w32
r_A=128'h00050006000700080001000200030004;
r_B=128'h00010001000100030002000200030003;
e_r=128'h0006e00e0008e002e003e003e006e004;
// hhhhHHHHhhhhHHHHllllLLLLllllLLLL
c_ppp=`mm;
c_ww=`w16;
a_op=`aluwadd;
#10
// aluwadd AND mm AND w32
r_A=128'h00000003000000040000000100000002;
r_B=128'h00000007000000080000000500000006;
e_r=128'h0000000aff0000f1ff000006ff00000d;
// hhhhHHHHhhhhHHHHllllLLLLllllLLLL
c_ppp=`mm;
c_ww=`w32;
a_op=`aluwadd;
// ======================================
#10 //TIME=190
// aluwadd AND ll AND w8
r_A=128'h090a0b0c0d0f10110102030405060708;
r_B=128'h04050601040506010101020203030303;
e_r=128'hcdff11ffdd004499bb7733ccdd22110b;
// hhhhHHHHhhhhHHHHllllLLLLllllLLLL
c_ppp=`ll;
c_ww=`w8;
a_op=`aluwadd;
#10
// aluwadd AND ll AND w32
r_A=128'h00050006000700080001000200000004;
r_B=128'h00010001000100030002000200000003;
e_r=128'hc006e00e0008e002e003e003e0000007;
// hhhhHHHHhhhhHHHHllllLLLLllllLLLL
c_ppp=`ll;
c_ww=`w16;
a_op=`aluwadd;
#10
// aluwadd AND ll AND w32
r_A=128'h00000003000000040000000100000002;
r_B=128'h00000007000000080000000500000006;
e_r=128'hc000000dff0000f1ff00000600000008;
// hhhhHHHHhhhhHHHHllllLLLLllllLLLL
c_ppp=`ll;
c_ww=`w32;
a_op=`aluwadd;
/**
* ========================================
* ========================================
*
* AND INSTRUCTION
*
* ========================================
* ========================================
*/
#10 //TIME=220
// aluwand AND aa AND w8
r_A=128'h5b76abfdedbe9389ddcf35f657afebb6;
r_B=128'h9389ddcf35f65b76abfdedbe98dc3f39;
e_r=128'h130089cd25b6130089cd25b6108c2b30;
c_ppp=`aa;
c_ww=`w8;
a_op=`aluwand;
#10
// aluwand AND aa AND w16
r_A=128'h00050007000d000e001e00d600170018;
r_B=128'h0009000800050006001300f600180017;
e_r=128'h0001000000050006001200d600100010;
c_ppp=`aa;
c_ww=`w16;
a_op=`aluwand;
#10
// aluwand AND aa AND w32
r_A=128'h0000000f0000000e0000000b0000000a;
r_B=128'h0000000c000000030000000d0000000d;
e_r=128'h0000000c000000020000000900000008;
c_ppp=`aa;
c_ww=`w32;
a_op=`aluwand;
// ======================================
#10 //TIME=250
// aluwand AND uu AND w8
r_A=128'h0e0a0d0d0b0e0d0b090a0b0c0d0f1011;
r_B=128'h030d0f050f060b030405060104050601;
e_r=128'h02080d050b0609030d10130d11141612;
// hhhhHHHHhhhhHHHHllllLLLLllllLLLL
c_ppp=`uu;
c_ww=`w8;
a_op=`aluwand;
#10
// aluwadd AND uu AND w32
r_A=128'h000d000d000e000b0006000f000a000d;
r_B=128'h000f00050006000f0009000c000d000b;
e_r=128'h000d00050006000b0000000c00080009;
// hhhhHHHHhhhhHHHHllllLLLLllllLLLL
c_ppp=`uu;
c_ww=`w16;
a_op=`aluwand;
#10
// aluwadd AND uu AND w32
r_A=128'h00000001000000020000000300000004;
r_B=128'h00000005000000060000000700000008;
e_r=128'h00000001000000020000000100000002;
// hhhhHHHHhhhhHHHHllllLLLLllllLLLL
c_ppp=`uu;
c_ww=`w32;
a_op=`aluwand;
// ======================================
#10 //TIME=280
// aluwand AND dd AND w8
r_A=128'h090a0b0c0d0f1011010e0b02050b070a;
r_B=128'h040506010405060101060d020d0d080d;
e_r=128'h0d10130d111416120106090205090008;
// hhhhHHHHhhhhHHHHllllLLLLllllLLLL
c_ppp=`dd;
c_ww=`w8;
a_op=`aluwand;
#10
// aluwand AND dd AND w32
r_A=128'h000500060007000800020002000e000d;
r_B=128'h0001000100010003000d000200030005;
e_r=128'h000600070008000b0000000200020005;
// hhhhHHHHhhhhHHHHllllLLLLllllLLLL
c_ppp=`dd;
c_ww=`w16;
a_op=`aluwand;
#10
// aluwand AND dd AND w32
r_A=128'h00000003000000040000000b0000000e;
r_B=128'h00000007000000080000000f00000003;
e_r=128'h00000001000000020000000b00000002;
// hhhhHHHHhhhhHHHHllllLLLLllllLLLL
c_ppp=`dd;
c_ww=`w32;
a_op=`aluwand;
// ======================================
#10 //TIME=310
// aluwand AND oo AND w8
r_A=128'h090a0b0c0d0f1011010e030b05060708;
r_B=128'h040d060f040d06110103020d03060307;
e_r=128'hff08fe0cfd0dfc11fb02fa09f906f800;
// hhhhHHHHhhhhHHHHllllLLLLllllLLLL
c_ppp=`oo;
c_ww=`w8;
a_op=`aluwand;
/**
* Stop exhaustive testing of the ALU at
* AND, ppp==oo, and ww=w8
*/
// ======================================
#10 //TIME=320
// aluwnot AND aa AND w8
r_A=128'h090a0b0c0d0f1011010e030b05060708;
r_B=128'h040d060f040d06110103020d03060307;
e_r=128'hf6f5f4f3f2f0efeefef1fcf4faf9f8f7;
// hhhhHHHHhhhhHHHHllllLLLLllllLLLL
c_ppp=`aa;
c_ww=`w8;
a_op=`aluwnot;
#10
// aluwnot AND ee AND w8
r_A=128'h44ff55ff22ff33ff66009900cc00bb00;
r_B=128'h040d060f040d06110103020d03060307;
e_r=128'hbb00aa00dd00cc0099ff66ff33ff44ff;
// hhhhHHHHhhhhHHHHllllLLLLllllLLLL
c_ppp=`ee;
c_ww=`w8;
a_op=`aluwnot;
#10
// aluwnot AND mm AND w32
r_A=128'hba98fedc0d0f1011010e030b05060708;
r_B=128'h040d060f040d06110103020d03060307;
e_r=128'h45670123f2f0efeefef1fcf4faf9f8f7;
// hhhhHHHHhhhhHHHHllllLLLLllllLLLL
c_ppp=`mm;
c_ww=`w32;
a_op=`aluwnot;
#10
// aluwnot AND uu AND w16
r_A=128'h0123456789abcdeeffffffffffffffff;
r_B=128'h040d060f040d06110103020d03060307;
e_r=128'hfedcba98765432110000000000000000;
// hhhhHHHHhhhhHHHHllllLLLLllllLLLL
c_ppp=`uu;
c_ww=`w16;
a_op=`aluwnot;
// ======================================
#10 //TIME=360
// aluwor AND aa AND w8
r_A=128'h5b4924086211598192408624b5268261;
r_B=128'hac8241a24596a229241a2458ca442446;
e_r=128'hffcb65aa6797fba9b65aa67cff66a667;
// hhhhHHHHhhhhHHHHllllLLLLllllLLLL
c_ppp=`aa;
c_ww=`w8;
a_op=`aluwor;
#10
// aluwor AND oo AND w16
r_A=128'hffff0004ffff0000ffff0002ffff000b;
r_B=128'h33330001333300aa333300053333000c;
e_r=128'h44440005444400aa444400074444000f;
// hhhhHHHHhhhhHHHHllllLLLLllllLLLL
c_ppp=`oo;
c_ww=`w16;
a_op=`aluwor;
#10
// aluwor AND dd AND w32
r_A=128'h88888888888888880000000500000004;
r_B=128'h33333333333333330000000a00000008;
e_r=128'hcccccccccccccccc0000000f0000000c;
// hhhhHHHHhhhhHHHHllllLLLLllllLLLL
c_ppp=`dd;
c_ww=`w32;
a_op=`aluwor;
// ======================================
#10 //TIME=390
// aluwxor AND aa AND w8
r_A=128'h01409d09085ac63511c098c340900a6c;
r_B=128'h6820a4020741489211e6a7492020018e;
e_r=128'h6960390b0f1b8ea700263f8a60b00be2;
// hhhhHHHHhhhhHHHHllllLLLLllllLLLL
c_ppp=`aa;
c_ww=`w8;
a_op=`aluwxor;
#10
// aluwxor AND oo AND w16
r_A=128'hffff0009ffff000dffff000cffff0006;
r_B=128'heeee0002eeee0004eeee0004eeee0008;
e_r=128'haaaa000baaaa0009aaaa0008aaaa000e;
// hhhhHHHHhhhhHHHHllllLLLLllllLLLL
c_ppp=`oo;
c_ww=`w16;
a_op=`aluwxor;
#10
// aluwxor AND dd AND w32
r_A=128'heeeeeeeeaaaaaaaa000000030000000c;
r_B=128'hbbbbbbbbcccccccc0000000900000004;
e_r=128'hddddddddffffffff0000000a00000008;
// hhhhHHHHhhhhHHHHllllLLLLllllLLLL
c_ppp=`dd;
c_ww=`w32;
a_op=`aluwxor;
// ======================================
#10 //TIME=420
// aluwsub AND aa AND w8
r_A=128'h15141312111021222a2212b2a2941827;
r_B=128'h0102030405060708090a010202020516;
e_r=128'h1412100e0c0a1a1a211811b0a0921311;
// hhhhHHHHhhhhHHHHllllLLLLllllLLLL
c_ppp=`aa;
c_ww=`w8;
a_op=`aluwsub;
#10
// aluwsub AND oo AND w16
r_A=128'hffff000dffff000effff000cffff0006;
r_B=128'heeee0004eeee0008eeee0004eeee0005;
e_r=128'haaaa0009aaaa0006aaaa0008aaaa0001;
// hhhhHHHHhhhhHHHHllllLLLLllllLLLL
c_ppp=`oo;
c_ww=`w16;
a_op=`aluwsub;
#10
// aluwsub AND dd AND w32
r_A=128'heeeeeeeeaaaaaaaa0000000e0000000c;
r_B=128'hbbbbbbbbcccccccc0000000a00000005;
e_r=128'hddddddddffffffff0000000400000007;
// hhhhHHHHhhhhHHHHllllLLLLllllLLLL
c_ppp=`dd;
c_ww=`w32;
a_op=`aluwsub;
#20
/**
* =====================================================
* =====================================================
* =====================================================
* =====================================================
* =====================================================
* =====================================================
* =====================================================
* =====================================================
* =====================================================
* =====================================================
* =====================================================
*/
//PRM TEST COMMANDS - Andrew
// aluwprm PRM aa
r_A=128'h0123456789abcdef0123456789abcdef;
r_B=128'h000102030405060708090a0b0c0d0e0f;
e_r=128'h0123456789abcdef0123456789abcdef;
c_ppp=`aa;
c_ww=`w8; // this does not matter, but must be specified
a_op=`aluwprm;
#10;
// aluwprm PRM aa
r_A=128'h0123456789abcdef0123456789abcdef;
r_B=128'h0102030405060708090a0b0c0d0e0f00;
e_r=128'h23456789abcdef0123456789abcdef01;
c_ppp=`aa;
c_ww=`w8; // this does not matter, but must be specified
a_op=`aluwprm;
#10;
// aluwprm PRM uu
r_A=128'h0123456789abcdef0123456789abcdef;
r_B=128'h0102030405060708090a0b0c0d0e0f00;
e_r=128'h23456789abcdef010000000000000000;
c_ppp=`uu;
c_ww=`w8; // this does not matter, but must be specified
a_op=`aluwprm;
#10;
// aluwprm PRM dd
r_A=128'h0123456789abcdef0123456789abcdef;
r_B=128'h0102030405060708090a0b0c0d0e0f00;
e_r=128'h000000000000000023456789abcdef01;
c_ppp=`dd;
c_ww=`w8; // this does not matter, but must be specified
a_op=`aluwprm;
#10;
// aluwprm PRM ee
r_A=128'h0123456789abcdef0123456789abcdef;
r_B=128'h0102030405060708090a0b0c0d0e0f00;
e_r=128'h23006700ab00ef0023006700ab00ef00;
c_ppp=`ee;
c_ww=`w8; // this does not matter, but must be specified
a_op=`aluwprm;
#10;
// aluwprm PRM oo
r_A=128'h0123456789abcdef0123456789abcdef;
r_B=128'h0102030405060708090a0b0c0d0e0f00;
e_r=128'h0045008900cd00010045008900cd0001;
c_ppp=`oo;
c_ww=`w8; // this does not matter, but must be specified
a_op=`aluwprm;
#10;
// aluwprm PRM mm
r_A=128'h0123456789abcdef0123456789abcdef;
r_B=128'h0102030405060708090a0b0c0d0e0f00;
e_r=128'h23000000000000000000000000000000;
c_ppp=`mm;
c_ww=`w8; // this does not matter, but must be specified
a_op=`aluwprm;
#10;
// aluwprm PRM ll
r_A=128'h0123456789abcdef0123456789abcdef;
r_B=128'h0102030405060708090a0b0c0d0e0f00;
e_r=128'h00000000000000000000000000000001;
c_ppp=`ll;
c_ww=`w8; // this does not matter, but must be specified
a_op=`aluwprm;
#10;
/**
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
*/
/**
a=16'd51267;
b=16'd11;
c=a>>b[11:15];
$display ("c ===========", c);
#10
a=16'd60123;
b=16'd5;
c=a>>b[11:15];
$display ("c ===========", c);
**/
//SLLI TEST COMMANDS - Andrew
// aluwslli SLLI aa
r_A=128'h11111111111111111111111111111111;
r_B=128'h00000000000000000000000000000000;//no shift
e_r=128'h11111111111111111111111111111111;
c_ppp=`aa;
c_ww=`w8;
a_op=`aluwslli;
#10;
// aluwslli SLLI aa
r_A=128'h0f0f0f0f0f0f0f0f0f0f0f0f0f0f0f0f;
r_B=128'h08000000000000000000000000000000;//shift 1 (00"001"000)
e_r=128'h1e1e1e1e1e1e1e1e1e1e1e1e1e1e1e1e;
c_ppp=`aa;
c_ww=`w8; // byte style
a_op=`aluwslli;
#10;
// aluwslli SLLI aa
r_A=128'h0f0f0f0f0f0f0f0f0f0f0f0f0f0f0f0f;
r_B=128'h08000000000000000000000000000000;//shift 1 (0"0001"000)
e_r=128'h1e1e1e1e1e1e1e1e1e1e1e1e1e1e1e1e;
c_ppp=`aa;
c_ww=`w16; // 2 byte style
a_op=`aluwslli;
#10;
// aluwslli SLLI aa
r_A=128'h000f000f000f000f000f000f000f000f;
r_B=128'h08000000000000000000000000000000;//shift 1 ("00001"000)
e_r=128'h001e001e001e001e001e001e001e001e;
c_ppp=`aa;
c_ww=`w32; // 2 byte style
a_op=`aluwslli;
#10;
// ======================================
#10 //TIME=420
// aluwsrl AND aa AND w8
r_A=128'h12345678941234567891234567891234;
r_B=128'h04040404040404040404040404040404;
e_r=128'h01030507090103050709020406080103;
// hhhhHHHHhhhhHHHHllllLLLLllllLLLL
c_ppp=`aa;
c_ww=`w8;
a_op=`aluwsrl;
#10
// aluwsrl AND oo AND w16
r_A=128'hffff1234ffff5678ffff9abcffffdef0;
r_B=128'heeee0004eeee0008eeee0004eeee0008;
e_r=128'haaaa0123aaaa0056aaaa09abaaaa00de;
// hhhhHHHHhhhhHHHHllllLLLLllllLLLL
c_ppp=`oo;
c_ww=`w16;
a_op=`aluwsrl;
#10
// aluwsrl AND dd AND w32
r_A=128'heeeeeeeeaaaaaaaa00001234006789ab;
r_B=128'hbbbbbbbbcccccccc0000000800000010;
e_r=128'hddddddddffffffff0000001200000067;
// hhhhHHHHhhhhHHHHllllLLLLllllLLLL
c_ppp=`dd;
c_ww=`w32;
a_op=`aluwsrl;
// ======================================
#10 //TIME=420
// aluwsll AND aa AND w8
r_A=128'h12345678941234567891234567891234;
r_B=128'h04040404040404040404040404040404;
e_r=128'h20406080402040608010305070902040;
// hhhhHHHHhhhhHHHHllllLLLLllllLLLL
c_ppp=`aa;
c_ww=`w8;
a_op=`aluwsll;
#10
// aluwsll AND oo AND w16
r_A=128'hffff1234ffff5678ffff9abcffffdefa;
r_B=128'heeee0004eeee0008eeee0004eeee0008;
e_r=128'haaaa2340aaaa7800aaaaabc0aaaafa00;
// hhhhHHHHhhhhHHHHllllLLLLllllLLLL
c_ppp=`oo;
c_ww=`w16;
a_op=`aluwsll;
#10
// aluwsll AND dd AND w32
r_A=128'heeeeeeeeaaaaaaaa00001234006789ab;
r_B=128'hbbbbbbbbcccccccc0000000800000010;
e_r=128'hddddddddffffffff0012340089ab0000;
// hhhhHHHHhhhhHHHHllllLLLLllllLLLL
c_ppp=`dd;
c_ww=`w32;
a_op=`aluwsll;
// =======================================
#10 //TIME=420
// aluwsra AND w8
r_A=128'h123456789abcdef89abcdef89abcdef8;
r_B=128'h04040404040404040404040404040404;
//e_r=128'hf1f3f5f7f9f1f3f5f7f9f2f4f6f8f1f3;
e_r=128'hf1f3f5f7f9f1f3f5f7f9f2f4f6f8f1f3;
// hhhhHHHHhhhhHHHHllllLLLLllllLLLL
c_ppp=`aa;
c_ww=`w8;
a_op=`aluwsra;
#10
// aluwsra AND w16
r_A=128'hffff1234ffff5678ffff9abcffffdefa;
r_B=128'heeee0004eeee0008eeee0004eeee0008;
e_r=128'haaaa2340aaaa7800aaaaabc0aaaafa00;
// hhhhHHHHhhhhHHHHllllLLLLllllLLLL
c_ppp=`oo;
c_ww=`w16;
a_op=`aluwsra;
#10
// aluwsra AND w32
r_A=128'heeeeeeeeaaaaaaaa00001234006789ab;
r_B=128'hbbbbbbbbcccccccc0000000800000010;
e_r=128'hddddddddffffffff0012340089ab0000;
// hhhhHHHHhhhhHHHHllllLLLLllllLLLL
c_ppp=`dd;
c_ww=`w32;
a_op=`aluwsra;
// end simulation
#30
$display($time, " << Finishing the simulation >>");
$finish;
end
endmodule |
module sky130_fd_sc_hd__dlrbp_2 (
Q ,
Q_N ,
RESET_B,
D ,
GATE ,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
output Q_N ;
input RESET_B;
input D ;
input GATE ;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_hd__dlrbp base (
.Q(Q),
.Q_N(Q_N),
.RESET_B(RESET_B),
.D(D),
.GATE(GATE),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule |
module sky130_fd_sc_hd__dlrbp_2 (
Q ,
Q_N ,
RESET_B,
D ,
GATE
);
output Q ;
output Q_N ;
input RESET_B;
input D ;
input GATE ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__dlrbp base (
.Q(Q),
.Q_N(Q_N),
.RESET_B(RESET_B),
.D(D),
.GATE(GATE)
);
endmodule |
module pikachu_down_pixel
(clka,
wea,
addra,
dina,
douta);
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK" *) input clka;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA WE" *) input [0:0]wea;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR" *) input [12:0]addra;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN" *) input [11:0]dina;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT" *) output [11:0]douta;
wire [12:0]addra;
wire clka;
wire [11:0]dina;
wire [11:0]douta;
wire [0:0]wea;
wire NLW_U0_dbiterr_UNCONNECTED;
wire NLW_U0_rsta_busy_UNCONNECTED;
wire NLW_U0_rstb_busy_UNCONNECTED;
wire NLW_U0_s_axi_arready_UNCONNECTED;
wire NLW_U0_s_axi_awready_UNCONNECTED;
wire NLW_U0_s_axi_bvalid_UNCONNECTED;
wire NLW_U0_s_axi_dbiterr_UNCONNECTED;
wire NLW_U0_s_axi_rlast_UNCONNECTED;
wire NLW_U0_s_axi_rvalid_UNCONNECTED;
wire NLW_U0_s_axi_sbiterr_UNCONNECTED;
wire NLW_U0_s_axi_wready_UNCONNECTED;
wire NLW_U0_sbiterr_UNCONNECTED;
wire [11:0]NLW_U0_doutb_UNCONNECTED;
wire [12:0]NLW_U0_rdaddrecc_UNCONNECTED;
wire [3:0]NLW_U0_s_axi_bid_UNCONNECTED;
wire [1:0]NLW_U0_s_axi_bresp_UNCONNECTED;
wire [12:0]NLW_U0_s_axi_rdaddrecc_UNCONNECTED;
wire [11:0]NLW_U0_s_axi_rdata_UNCONNECTED;
wire [3:0]NLW_U0_s_axi_rid_UNCONNECTED;
wire [1:0]NLW_U0_s_axi_rresp_UNCONNECTED;
(* C_ADDRA_WIDTH = "13" *)
(* C_ADDRB_WIDTH = "13" *)
(* C_ALGORITHM = "1" *)
(* C_AXI_ID_WIDTH = "4" *)
(* C_AXI_SLAVE_TYPE = "0" *)
(* C_AXI_TYPE = "1" *)
(* C_BYTE_SIZE = "9" *)
(* C_COMMON_CLK = "0" *)
(* C_COUNT_18K_BRAM = "1" *)
(* C_COUNT_36K_BRAM = "2" *)
(* C_CTRL_ECC_ALGO = "NONE" *)
(* C_DEFAULT_DATA = "0" *)
(* C_DISABLE_WARN_BHV_COLL = "0" *)
(* C_DISABLE_WARN_BHV_RANGE = "0" *)
(* C_ELABORATION_DIR = "./" *)
(* C_ENABLE_32BIT_ADDRESS = "0" *)
(* C_EN_DEEPSLEEP_PIN = "0" *)
(* C_EN_ECC_PIPE = "0" *)
(* C_EN_RDADDRA_CHG = "0" *)
(* C_EN_RDADDRB_CHG = "0" *)
(* C_EN_SAFETY_CKT = "0" *)
(* C_EN_SHUTDOWN_PIN = "0" *)
(* C_EN_SLEEP_PIN = "0" *)
(* C_EST_POWER_SUMMARY = "Estimated Power for IP : 4.681258 mW" *)
(* C_FAMILY = "artix7" *)
(* C_HAS_AXI_ID = "0" *)
(* C_HAS_ENA = "0" *)
(* C_HAS_ENB = "0" *)
(* C_HAS_INJECTERR = "0" *)
(* C_HAS_MEM_OUTPUT_REGS_A = "1" *)
(* C_HAS_MEM_OUTPUT_REGS_B = "0" *)
(* C_HAS_MUX_OUTPUT_REGS_A = "0" *)
(* C_HAS_MUX_OUTPUT_REGS_B = "0" *)
(* C_HAS_REGCEA = "0" *)
(* C_HAS_REGCEB = "0" *)
(* C_HAS_RSTA = "0" *)
(* C_HAS_RSTB = "0" *)
(* C_HAS_SOFTECC_INPUT_REGS_A = "0" *)
(* C_HAS_SOFTECC_OUTPUT_REGS_B = "0" *)
(* C_INITA_VAL = "0" *)
(* C_INITB_VAL = "0" *)
(* C_INIT_FILE = "pikachu_down_pixel.mem" *)
(* C_INIT_FILE_NAME = "pikachu_down_pixel.mif" *)
(* C_INTERFACE_TYPE = "0" *)
(* C_LOAD_INIT_FILE = "1" *)
(* C_MEM_TYPE = "0" *)
(* C_MUX_PIPELINE_STAGES = "0" *)
(* C_PRIM_TYPE = "1" *)
(* C_READ_DEPTH_A = "5589" *)
(* C_READ_DEPTH_B = "5589" *)
(* C_READ_WIDTH_A = "12" *)
(* C_READ_WIDTH_B = "12" *)
(* C_RSTRAM_A = "0" *)
(* C_RSTRAM_B = "0" *)
(* C_RST_PRIORITY_A = "CE" *)
(* C_RST_PRIORITY_B = "CE" *)
(* C_SIM_COLLISION_CHECK = "ALL" *)
(* C_USE_BRAM_BLOCK = "0" *)
(* C_USE_BYTE_WEA = "0" *)
(* C_USE_BYTE_WEB = "0" *)
(* C_USE_DEFAULT_DATA = "0" *)
(* C_USE_ECC = "0" *)
(* C_USE_SOFTECC = "0" *)
(* C_USE_URAM = "0" *)
(* C_WEA_WIDTH = "1" *)
(* C_WEB_WIDTH = "1" *)
(* C_WRITE_DEPTH_A = "5589" *)
(* C_WRITE_DEPTH_B = "5589" *)
(* C_WRITE_MODE_A = "WRITE_FIRST" *)
(* C_WRITE_MODE_B = "WRITE_FIRST" *)
(* C_WRITE_WIDTH_A = "12" *)
(* C_WRITE_WIDTH_B = "12" *)
(* C_XDEVICEFAMILY = "artix7" *)
(* downgradeipidentifiedwarnings = "yes" *)
pikachu_down_pixel_blk_mem_gen_v8_3_5 U0
(.addra(addra),
.addrb({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.clka(clka),
.clkb(1'b0),
.dbiterr(NLW_U0_dbiterr_UNCONNECTED),
.deepsleep(1'b0),
.dina(dina),
.dinb({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.douta(douta),
.doutb(NLW_U0_doutb_UNCONNECTED[11:0]),
.eccpipece(1'b0),
.ena(1'b0),
.enb(1'b0),
.injectdbiterr(1'b0),
.injectsbiterr(1'b0),
.rdaddrecc(NLW_U0_rdaddrecc_UNCONNECTED[12:0]),
.regcea(1'b0),
.regceb(1'b0),
.rsta(1'b0),
.rsta_busy(NLW_U0_rsta_busy_UNCONNECTED),
.rstb(1'b0),
.rstb_busy(NLW_U0_rstb_busy_UNCONNECTED),
.s_aclk(1'b0),
.s_aresetn(1'b0),
.s_axi_araddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_arburst({1'b0,1'b0}),
.s_axi_arid({1'b0,1'b0,1'b0,1'b0}),
.s_axi_arlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_arready(NLW_U0_s_axi_arready_UNCONNECTED),
.s_axi_arsize({1'b0,1'b0,1'b0}),
.s_axi_arvalid(1'b0),
.s_axi_awaddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_awburst({1'b0,1'b0}),
.s_axi_awid({1'b0,1'b0,1'b0,1'b0}),
.s_axi_awlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_awready(NLW_U0_s_axi_awready_UNCONNECTED),
.s_axi_awsize({1'b0,1'b0,1'b0}),
.s_axi_awvalid(1'b0),
.s_axi_bid(NLW_U0_s_axi_bid_UNCONNECTED[3:0]),
.s_axi_bready(1'b0),
.s_axi_bresp(NLW_U0_s_axi_bresp_UNCONNECTED[1:0]),
.s_axi_bvalid(NLW_U0_s_axi_bvalid_UNCONNECTED),
.s_axi_dbiterr(NLW_U0_s_axi_dbiterr_UNCONNECTED),
.s_axi_injectdbiterr(1'b0),
.s_axi_injectsbiterr(1'b0),
.s_axi_rdaddrecc(NLW_U0_s_axi_rdaddrecc_UNCONNECTED[12:0]),
.s_axi_rdata(NLW_U0_s_axi_rdata_UNCONNECTED[11:0]),
.s_axi_rid(NLW_U0_s_axi_rid_UNCONNECTED[3:0]),
.s_axi_rlast(NLW_U0_s_axi_rlast_UNCONNECTED),
.s_axi_rready(1'b0),
.s_axi_rresp(NLW_U0_s_axi_rresp_UNCONNECTED[1:0]),
.s_axi_rvalid(NLW_U0_s_axi_rvalid_UNCONNECTED),
.s_axi_sbiterr(NLW_U0_s_axi_sbiterr_UNCONNECTED),
.s_axi_wdata({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_wlast(1'b0),
.s_axi_wready(NLW_U0_s_axi_wready_UNCONNECTED),
.s_axi_wstrb(1'b0),
.s_axi_wvalid(1'b0),
.sbiterr(NLW_U0_sbiterr_UNCONNECTED),
.shutdown(1'b0),
.sleep(1'b0),
.wea(wea),
.web(1'b0));
endmodule |
module pikachu_down_pixel_blk_mem_gen_generic_cstr
(douta,
addra,
clka,
dina,
wea);
output [11:0]douta;
input [12:0]addra;
input clka;
input [11:0]dina;
input [0:0]wea;
wire [12:0]addra;
wire clka;
wire [11:0]dina;
wire [11:0]douta;
wire [8:0]p_7_out;
wire [8:0]ram_douta;
wire [0:0]wea;
pikachu_down_pixel_blk_mem_gen_mux \has_mux_a.A
(.addra(addra[12:11]),
.clka(clka),
.douta(douta[8:0]),
.p_7_out(p_7_out),
.ram_douta(ram_douta));
pikachu_down_pixel_blk_mem_gen_prim_width \ramloop[0].ram.r
(.addra(addra),
.clka(clka),
.dina(dina[8:0]),
.ram_douta(ram_douta),
.wea(wea));
pikachu_down_pixel_blk_mem_gen_prim_width__parameterized0 \ramloop[1].ram.r
(.addra(addra),
.clka(clka),
.dina(dina[8:0]),
.p_7_out(p_7_out),
.wea(wea));
pikachu_down_pixel_blk_mem_gen_prim_width__parameterized1 \ramloop[2].ram.r
(.addra(addra),
.clka(clka),
.dina(dina[11:9]),
.douta(douta[11:9]),
.wea(wea));
endmodule |
module pikachu_down_pixel_blk_mem_gen_mux
(douta,
addra,
clka,
p_7_out,
ram_douta);
output [8:0]douta;
input [1:0]addra;
input clka;
input [8:0]p_7_out;
input [8:0]ram_douta;
wire [1:0]addra;
wire clka;
wire [8:0]douta;
wire [8:0]p_7_out;
wire [8:0]ram_douta;
wire [1:0]sel_pipe;
wire [1:0]sel_pipe_d1;
LUT4 #(
.INIT(16'h2F20))
\douta[0]_INST_0
(.I0(p_7_out[0]),
.I1(sel_pipe_d1[0]),
.I2(sel_pipe_d1[1]),
.I3(ram_douta[0]),
.O(douta[0]));
LUT4 #(
.INIT(16'h2F20))
\douta[1]_INST_0
(.I0(p_7_out[1]),
.I1(sel_pipe_d1[0]),
.I2(sel_pipe_d1[1]),
.I3(ram_douta[1]),
.O(douta[1]));
LUT4 #(
.INIT(16'h2F20))
\douta[2]_INST_0
(.I0(p_7_out[2]),
.I1(sel_pipe_d1[0]),
.I2(sel_pipe_d1[1]),
.I3(ram_douta[2]),
.O(douta[2]));
LUT4 #(
.INIT(16'h2F20))
\douta[3]_INST_0
(.I0(p_7_out[3]),
.I1(sel_pipe_d1[0]),
.I2(sel_pipe_d1[1]),
.I3(ram_douta[3]),
.O(douta[3]));
LUT4 #(
.INIT(16'h2F20))
\douta[4]_INST_0
(.I0(p_7_out[4]),
.I1(sel_pipe_d1[0]),
.I2(sel_pipe_d1[1]),
.I3(ram_douta[4]),
.O(douta[4]));
LUT4 #(
.INIT(16'h2F20))
\douta[5]_INST_0
(.I0(p_7_out[5]),
.I1(sel_pipe_d1[0]),
.I2(sel_pipe_d1[1]),
.I3(ram_douta[5]),
.O(douta[5]));
LUT4 #(
.INIT(16'h2F20))
\douta[6]_INST_0
(.I0(p_7_out[6]),
.I1(sel_pipe_d1[0]),
.I2(sel_pipe_d1[1]),
.I3(ram_douta[6]),
.O(douta[6]));
LUT4 #(
.INIT(16'h2F20))
\douta[7]_INST_0
(.I0(p_7_out[7]),
.I1(sel_pipe_d1[0]),
.I2(sel_pipe_d1[1]),
.I3(ram_douta[7]),
.O(douta[7]));
LUT4 #(
.INIT(16'h2F20))
\douta[8]_INST_0
(.I0(p_7_out[8]),
.I1(sel_pipe_d1[0]),
.I2(sel_pipe_d1[1]),
.I3(ram_douta[8]),
.O(douta[8]));
FDRE #(
.INIT(1'b0))
\no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg[0]
(.C(clka),
.CE(1'b1),
.D(sel_pipe[0]),
.Q(sel_pipe_d1[0]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg[1]
(.C(clka),
.CE(1'b1),
.D(sel_pipe[1]),
.Q(sel_pipe_d1[1]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\no_softecc_sel_reg.ce_pri.sel_pipe_reg[0]
(.C(clka),
.CE(1'b1),
.D(addra[0]),
.Q(sel_pipe[0]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\no_softecc_sel_reg.ce_pri.sel_pipe_reg[1]
(.C(clka),
.CE(1'b1),
.D(addra[1]),
.Q(sel_pipe[1]),
.R(1'b0));
endmodule |
module pikachu_down_pixel_blk_mem_gen_prim_width
(ram_douta,
clka,
addra,
dina,
wea);
output [8:0]ram_douta;
input clka;
input [12:0]addra;
input [8:0]dina;
input [0:0]wea;
wire [12:0]addra;
wire clka;
wire [8:0]dina;
wire [8:0]ram_douta;
wire [0:0]wea;
pikachu_down_pixel_blk_mem_gen_prim_wrapper_init \prim_init.ram
(.addra(addra),
.clka(clka),
.dina(dina),
.ram_douta(ram_douta),
.wea(wea));
endmodule |
module pikachu_down_pixel_blk_mem_gen_prim_width__parameterized0
(p_7_out,
clka,
addra,
dina,
wea);
output [8:0]p_7_out;
input clka;
input [12:0]addra;
input [8:0]dina;
input [0:0]wea;
wire [12:0]addra;
wire clka;
wire [8:0]dina;
wire [8:0]p_7_out;
wire [0:0]wea;
pikachu_down_pixel_blk_mem_gen_prim_wrapper_init__parameterized0 \prim_init.ram
(.addra(addra),
.clka(clka),
.dina(dina),
.p_7_out(p_7_out),
.wea(wea));
endmodule |
module pikachu_down_pixel_blk_mem_gen_prim_width__parameterized1
(douta,
clka,
addra,
dina,
wea);
output [2:0]douta;
input clka;
input [12:0]addra;
input [2:0]dina;
input [0:0]wea;
wire [12:0]addra;
wire clka;
wire [2:0]dina;
wire [2:0]douta;
wire [0:0]wea;
pikachu_down_pixel_blk_mem_gen_prim_wrapper_init__parameterized1 \prim_init.ram
(.addra(addra),
.clka(clka),
.dina(dina),
.douta(douta),
.wea(wea));
endmodule |
module pikachu_down_pixel_blk_mem_gen_prim_wrapper_init
(ram_douta,
clka,
addra,
dina,
wea);
output [8:0]ram_douta;
input clka;
input [12:0]addra;
input [8:0]dina;
input [0:0]wea;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_i_1_n_0 ;
wire [12:0]addra;
wire clka;
wire [8:0]dina;
wire [8:0]ram_douta;
wire [0:0]wea;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* CLOCK_DOMAINS = "COMMON" *)
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000380000000000000000000400000000000000000000000000),
.INITP_01(256'h0000000000000000003F0000000000000000003F8000000000000000000FA000),
.INITP_02(256'hFFE000000000000000001FE0000000000000000007F8000000000000000000FA),
.INITP_03(256'h1FFFF8000000000000000E0FF8000000000000000305FC000000000000000200),
.INITP_04(256'h0001FFFE0000000000000001FFFFC000000000000000FFFFD000000000000000),
.INITP_05(256'h000000821E00000000000000004E81E00000000000000011BF6C000000000000),
.INITP_06(256'h000000005A023FFC0FF8000000001881BFFE0000000000000030F87000000000),
.INITP_07(256'hFFFF00000023002C777FFFFC00000007801E3F83FFF9000000009C043FFBDFFC),
.INITP_08(256'hFFFFFD3A0010C1800FFFFFFFFD7E0000009007C01FFFFFFC0000001000E00FFF),
.INITP_09(256'hD3FFFFFFE4E8000E077FFBFFFFFFF07800830B0F95FFFFFFFC38001F8FFDFDFF),
.INITP_0A(256'hFBFF47FFFFFFE7F03FFFFD99B3FFFFFFE3FC07EFFDFFF9FFFFFF83F603EBFFFE),
.INITP_0B(256'hFFFFF3FEFFFFFFFFFF8FFFFFFFE71FFFFFFFFFC1FFFFF7FECFFFFFFFDFE0FFFF),
.INITP_0C(256'hF807FFFFFFEFFFFFFFFFFA79FFFFFFF7FFFFFFFFFF1CFFFFEFFBFFFFFFFFFF1E),
.INITP_0D(256'hFFFC803FFFFFFF8FFFFFFFFF001FFFFFFF8FFFFFFFFFE00FFFFFFFFFFFFFFFFF),
.INITP_0E(256'hFFFFFFF001FFFFFFFFBFFFFFFFFA00FFFFFFFE7FFFFFFFFE007FFFFFFF9FFFFF),
.INITP_0F(256'hFFFFFFFFFC000FFFFFFFFFFFFFFFFF0007FFFFFFFFFFFFFFFFC003FFFFFFFFFF),
.INIT_00(256'hF0F0F00000000102F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0),
.INIT_01(256'hF0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0),
.INIT_02(256'hF0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0),
.INIT_03(256'hF0F0F0F0F0F0F0F0F0F0F0F0F0F00000010080A0A0B02000F0F0F0F0F0F0F0F0),
.INIT_04(256'hF0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0),
.INIT_05(256'h60E0F0F0B02000F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0),
.INIT_06(256'hF0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F000406061),
.INIT_07(256'hF0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0),
.INIT_08(256'hF0F0F0F0F0F0F0F0F0F00120B0F0F0F0F0E0B000F0F0F0F0F0F0F0F0F0F0F0F0),
.INIT_09(256'hF0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0),
.INIT_0A(256'h9000F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0),
.INIT_0B(256'hF0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F00101D0F0F0F0F0F0),
.INIT_0C(256'hF0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0),
.INIT_0D(256'hF0F0F0F0F0F0F00000E0F0F0F0F0F09000F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0),
.INIT_0E(256'hF0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0),
.INIT_0F(256'hF0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0),
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.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(clka),
.CLKBWRCLK(clka),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dina[7:0]}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,dina[8]}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:8],ram_douta[7:0]}),
.DOBDO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:0]),
.DOPADOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:1],ram_douta[8]}),
.DOPBDOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:0]),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_i_1_n_0 ),
.ENBWREN(1'b0),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b1),
.REGCEB(1'b0),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({wea,wea,wea,wea}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
LUT1 #(
.INIT(2'h1))
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_i_1
(.I0(addra[12]),
.O(\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_i_1_n_0 ));
endmodule |
module pikachu_down_pixel_blk_mem_gen_prim_wrapper_init__parameterized0
(p_7_out,
clka,
addra,
dina,
wea);
output [8:0]p_7_out;
input clka;
input [12:0]addra;
input [8:0]dina;
input [0:0]wea;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_i_1_n_0 ;
wire [12:0]addra;
wire clka;
wire [8:0]dina;
wire [8:0]p_7_out;
wire [0:0]wea;
wire [15:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOADO_UNCONNECTED ;
wire [15:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOBDO_UNCONNECTED ;
wire [1:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOPADOP_UNCONNECTED ;
wire [1:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOPBDOP_UNCONNECTED ;
(* CLOCK_DOMAINS = "COMMON" *)
(* box_type = "PRIMITIVE" *)
RAMB18E1 #(
.DOA_REG(1),
.DOB_REG(0),
.INITP_00(256'hFFFFFFFFFFFE80005FFFFFFFFFFFFFFF88003FFFFFFFFFFFFFFFF8001FFFFFFF),
.INITP_01(256'hFFFFFFFFF0FFFF8000013FFFFFFFFCFFFFE00000FFFFFFFFFBFFFFF800003FFF),
.INITP_02(256'h00001FFFFFFFFFBFE84000006FFFFFFFFF1FFD000000BFFFFFFFE1FFFE800001),
.INITP_03(256'h020000000FFFFF03FF4F3F0000001FFFFFFFFEA7FF8000001FFFFFFFFF0F8F80),
.INITP_04(256'h20E200000000001FFF902FF80000000001FFFFF81FE00000000008FFFF040FE0),
.INITP_05(256'h0000000000000000000000000000000000000000000001E40000000000100000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'hF0F00070F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0),
.INIT_01(256'hF0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F02000F0F0F0F0F0F0F0F0F0),
.INIT_02(256'hF0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0),
.INIT_03(256'hF0A0202010F0F0F0F0F0F0F0F0F0F0F0F00070F0F0F0F0F0F0F0F0F0F0F0F0F0),
.INIT_04(256'hF0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0),
.INIT_05(256'hF01040F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0),
.INIT_06(256'hF0F0F0F0F0F0F0F0F0F0F0F0F0F0F080300000F0F0F0F0F0F0F0F0F0F0F0F0F0),
.INIT_07(256'hF0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0),
.INIT_08(256'hF0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F00020F0F0F0F0F0F0F0F0F0F0F0F0F0F0),
.INIT_09(256'hF0F0F0F0F0C0B0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0A02000),
.INIT_0A(256'h30F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0),
.INIT_0B(256'hF0F0F0F0F0F0F0F0F0F0F0C00000F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F000),
.INIT_0C(256'hF0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F05030E0E0F0F0F0F0F0F0F0F0),
.INIT_0D(256'hF0F0F0F0F0F0F0F0F0F0F0F0F0F00030E0E0F0F0F0F0F0F0F0F0F0F0F0F0F0F0),
.INIT_0E(256'hF0F0F0F0A00000A0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0A000F0F0F0F0F0),
.INIT_0F(256'h1090F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0),
.INIT_10(256'hF0F0F0F0F0F0F0801000F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F00010),
.INIT_11(256'hF0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0E0A0A0603050F0F0F0F0F0F0F0),
.INIT_12(256'hF0F0F0F0F0F0F0F0F0F0F0F0F0F000003080F0F0F0F0F0F0F0F0F0F0F0F0F0F0),
.INIT_13(256'hF0F0F0F0F09050508080C0F0F0F0F0F0F0F0F0F0F09060300000F0F0F0F0F0F0),
.INIT_14(256'h209090E0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0),
.INIT_15(256'hF0F0F0C010C0C0202010F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F000),
.INIT_16(256'hF0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0101060D0D0F0F0F0F0),
.INIT_17(256'hF0F0F0F0F0F0F0F0F0F0F0F0F0F0F000000080D0D0F0F0F0F0F0F0F0F0F0F0F0),
.INIT_18(256'hF0F0F0F0F0F0F0F0800000C0F0F0F0F0F0A000E0F0F0F0F03000F0F0F0F0F0F0),
.INIT_19(256'hF0000010F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0),
.INIT_1A(256'h50D0F0F0F0F0F0D07000F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0),
.INIT_1B(256'hF0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0E09000102060F0F070),
.INIT_1C(256'hF0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F00000303090F0F0F0F0F0F0F0F0F0F0),
.INIT_1D(256'hF0F0F0F0F0F0F0F08070200070701010808070B0F0F0F09000F0F0F0F0F0F0F0),
.INIT_1E(256'hF0F000003090F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F080606060606090F0),
.INIT_1F(256'h000040C0C0C07000F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0),
.INIT_20(256'hF0F0F0F0F0F0F050202020202050C0C0C0C0C0C0F0F0F0F0F090302000000000),
.INIT_21(256'hF0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F00010C0C0C0D0F0F0F0F0F0F0F0),
.INIT_22(256'h000000B0F0F0F0F0F0F0F0200000F0F0F00000000000F0F0F0F0F0F0F0F0F0F0),
.INIT_23(256'hF0F0F0F000000030F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0B0000000),
.INIT_24(256'hF0F0F00000F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0),
.INIT_25(256'hF0F0F0F0F0F0F0F0F04020100000000000001080F0F0F0F0F0F0D0D090000000),
.INIT_26(256'hF0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0000000002020202030F0F0F0F0),
.INIT_27(256'h0000306060606080F0F0F0C0000000F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0),
.INIT_28(256'hF0F0F0F0F0F0000000000050606060606060606060606060000000F0F0F000F0),
.INIT_29(256'hF0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0),
.INIT_2A(256'h00000000000000F00000F0F0F0F0F0F0F0000000000020B0B0B070000000F0F0),
.INIT_2B(256'hF0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0000000000000),
.INIT_2C(256'hF0F0F0F0F0000000000000F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0),
.INIT_2D(256'hF0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0),
.INIT_2E(256'h0000000000000000000000F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(18'h00000),
.INIT_B(18'h00000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("PERFORMANCE"),
.READ_WIDTH_A(9),
.READ_WIDTH_B(9),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(18'h00000),
.SRVAL_B(18'h00000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(9),
.WRITE_WIDTH_B(9))
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram
(.ADDRARDADDR({addra[10:0],1'b0,1'b0,1'b0}),
.ADDRBWRADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.CLKARDCLK(clka),
.CLKBWRCLK(clka),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dina[7:0]}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,dina[8]}),
.DIPBDIP({1'b0,1'b0}),
.DOADO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOADO_UNCONNECTED [15:8],p_7_out[7:0]}),
.DOBDO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOBDO_UNCONNECTED [15:0]),
.DOPADOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOPADOP_UNCONNECTED [1],p_7_out[8]}),
.DOPBDOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOPBDOP_UNCONNECTED [1:0]),
.ENARDEN(\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_i_1_n_0 ),
.ENBWREN(1'b0),
.REGCEAREGCE(1'b1),
.REGCEB(1'b0),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.WEA({wea,wea}),
.WEBWE({1'b0,1'b0,1'b0,1'b0}));
LUT2 #(
.INIT(4'h2))
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_i_1
(.I0(addra[12]),
.I1(addra[11]),
.O(\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_i_1_n_0 ));
endmodule |
module pikachu_down_pixel_blk_mem_gen_prim_wrapper_init__parameterized1
(douta,
clka,
addra,
dina,
wea);
output [2:0]douta;
input clka;
input [12:0]addra;
input [2:0]dina;
input [0:0]wea;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_49 ;
wire [12:0]addra;
wire clka;
wire [2:0]dina;
wire [2:0]douta;
wire [0:0]wea;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:4]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* CLOCK_DOMAINS = "COMMON" *)
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h2222222222222222222222222222222222200000222222222222222222222222),
.INIT_01(256'h2222222222222200004555102222222222222222222222222222222222222222),
.INIT_02(256'h3777510222222222222222222222222222222222222222222222222222222222),
.INIT_03(256'h2222222222222222222222222222222222222222222222222222222222220233),
.INIT_04(256'h2222222222222222222222222222222222222222220157777750222222222222),
.INIT_05(256'h2222222222222222222222220067777740222222222222222222222222222222),
.INIT_06(256'h2222222007777774022222222222222222222222222222222222222222222222),
.INIT_07(256'h2222222222222222222222222222222222222222222222222222222222222222),
.INIT_08(256'h2222222222222222222222222222222222222222222222222222201477777520),
.INIT_09(256'h2222222222222222222222222022222222001377777710222222222222222222),
.INIT_0A(256'h2222222002222222000477777772022222222222222222222222222222222222),
.INIT_0B(256'h6677777771022222222222222222222222222222222222222222222222222222),
.INIT_0C(256'h2222222222222222222222222222222222222222222222222222202600222201),
.INIT_0D(256'h2222222222222222222222222222222222203674100002577777776302222222),
.INIT_0E(256'h2222222222222222220577742222577777777502222222222222222222222222),
.INIT_0F(256'h2057777777777777777740222222222222222222222222222222222222222222),
.INIT_10(256'h7730222222222222222222222222222222222222222222222222222222222222),
.INIT_11(256'h2222222222222222222222222222222222222222222222006777777777777777),
.INIT_12(256'h2222222222222222222222222222000777777777777777777202222222222222),
.INIT_13(256'h2222222222000267777777777777777520222222222222222222222222222222),
.INIT_14(256'h7766666677776600222222222222222222222222222222222222222222222222),
.INIT_15(256'h2222222222222222222222222222222222222222222222222222222220015577),
.INIT_16(256'h2222222222222222222222222222222222222220025577770000000177300222),
.INIT_17(256'h2222222222222222222222034556321000055541100000222222222222222222),
.INIT_18(256'h2200004555400000147777333333100022222000000000022222222222222222),
.INIT_19(256'h6677777777731111000011111111110022222222222222222222222222222222),
.INIT_1A(256'h0004777777774000222222222222222222222222222222222000045542200013),
.INIT_1B(256'h0222222222222222222222222222222001444542220006400677777777777720),
.INIT_1C(256'h2222222222222203455100222200676614777777775000266677777777776610),
.INIT_1D(256'h4200020000015775347776222344467777777777777775430222222222222222),
.INIT_1E(256'h0555411147777777777777777777777202222222222222222222222222200245),
.INIT_1F(256'h7777777777777771022222222222222222222222200255420000000002135562),
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.INIT_2E(256'h7777777775005777777777777777777777776467777766753477777777777777),
.INIT_2F(256'h6777777777777777777756777777773077777777777777777777777777777777),
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.INIT_3B(256'h7777777777777777777777777775022222222067777777777777777777777777),
.INIT_3C(256'h7777777774102222222206777777777777777777777777777777777777777777),
.INIT_3D(256'h2200677777777777777777777777777777777777777777777777777777777777),
.INIT_3E(256'h7777777777777777777777777777777777777777777777777777777420222222),
.INIT_3F(256'h7777777777777777777777777777777777777710222222222203577777777777),
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.INIT_42(256'h2027777777777777777777777777777777777777777777777777777777777777),
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.INIT_4A(256'h7776066110222222222222222222222014477777777777777777777777777777),
.INIT_4B(256'h2222222222222220004667777777777777777777777777777777777003667777),
.INIT_4C(256'h2000777777777777777777777777777777777777400677777507777710222222),
.INIT_4D(256'h7777777777777777777777774001377326777776302222222222222222222222),
.INIT_4E(256'h7777777743103300443577740222222222222222222222222001147777777777),
.INIT_4F(256'h0026663022222222222222222222222222001477777777777777777743333347),
.INIT_50(256'h2222222222222222222006666777777777777772111112666666777774110000),
.INIT_51(256'h2222000177777777777777777777500000057777777100222000002222222222),
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.INIT_53(256'h0013333477760002222222222222222222222222222222222220000111117777),
.INIT_54(256'h2222222222222222222222222222222222222200000233333333333300022202),
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.INIT_57(256'h0000000000000000000000000000000000000000000222222222222222222222),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("PERFORMANCE"),
.READ_WIDTH_A(4),
.READ_WIDTH_B(4),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(4),
.WRITE_WIDTH_B(4))
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,addra,1'b1,1'b1}),
.ADDRBWRADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(clka),
.CLKBWRCLK(clka),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dina}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:4],\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_49 ,douta}),
.DOBDO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:0]),
.DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]),
.DOPBDOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:0]),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(1'b1),
.ENBWREN(1'b0),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b1),
.REGCEB(1'b0),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({wea,wea,wea,wea}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule |
module pikachu_down_pixel_blk_mem_gen_top
(douta,
addra,
clka,
dina,
wea);
output [11:0]douta;
input [12:0]addra;
input clka;
input [11:0]dina;
input [0:0]wea;
wire [12:0]addra;
wire clka;
wire [11:0]dina;
wire [11:0]douta;
wire [0:0]wea;
pikachu_down_pixel_blk_mem_gen_generic_cstr \valid.cstr
(.addra(addra),
.clka(clka),
.dina(dina),
.douta(douta),
.wea(wea));
endmodule |
module pikachu_down_pixel_blk_mem_gen_v8_3_5
(clka,
rsta,
ena,
regcea,
wea,
addra,
dina,
douta,
clkb,
rstb,
enb,
regceb,
web,
addrb,
dinb,
doutb,
injectsbiterr,
injectdbiterr,
eccpipece,
sbiterr,
dbiterr,
rdaddrecc,
sleep,
deepsleep,
shutdown,
rsta_busy,
rstb_busy,
s_aclk,
s_aresetn,
s_axi_awid,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awvalid,
s_axi_awready,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wvalid,
s_axi_wready,
s_axi_bid,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_arid,
s_axi_araddr,
s_axi_arlen,
s_axi_arsize,
s_axi_arburst,
s_axi_arvalid,
s_axi_arready,
s_axi_rid,
s_axi_rdata,
s_axi_rresp,
s_axi_rlast,
s_axi_rvalid,
s_axi_rready,
s_axi_injectsbiterr,
s_axi_injectdbiterr,
s_axi_sbiterr,
s_axi_dbiterr,
s_axi_rdaddrecc);
input clka;
input rsta;
input ena;
input regcea;
input [0:0]wea;
input [12:0]addra;
input [11:0]dina;
output [11:0]douta;
input clkb;
input rstb;
input enb;
input regceb;
input [0:0]web;
input [12:0]addrb;
input [11:0]dinb;
output [11:0]doutb;
input injectsbiterr;
input injectdbiterr;
input eccpipece;
output sbiterr;
output dbiterr;
output [12:0]rdaddrecc;
input sleep;
input deepsleep;
input shutdown;
output rsta_busy;
output rstb_busy;
input s_aclk;
input s_aresetn;
input [3:0]s_axi_awid;
input [31:0]s_axi_awaddr;
input [7:0]s_axi_awlen;
input [2:0]s_axi_awsize;
input [1:0]s_axi_awburst;
input s_axi_awvalid;
output s_axi_awready;
input [11:0]s_axi_wdata;
input [0:0]s_axi_wstrb;
input s_axi_wlast;
input s_axi_wvalid;
output s_axi_wready;
output [3:0]s_axi_bid;
output [1:0]s_axi_bresp;
output s_axi_bvalid;
input s_axi_bready;
input [3:0]s_axi_arid;
input [31:0]s_axi_araddr;
input [7:0]s_axi_arlen;
input [2:0]s_axi_arsize;
input [1:0]s_axi_arburst;
input s_axi_arvalid;
output s_axi_arready;
output [3:0]s_axi_rid;
output [11:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output s_axi_rlast;
output s_axi_rvalid;
input s_axi_rready;
input s_axi_injectsbiterr;
input s_axi_injectdbiterr;
output s_axi_sbiterr;
output s_axi_dbiterr;
output [12:0]s_axi_rdaddrecc;
wire \<const0> ;
wire [12:0]addra;
wire clka;
wire [11:0]dina;
wire [11:0]douta;
wire [0:0]wea;
assign dbiterr = \<const0> ;
assign doutb[11] = \<const0> ;
assign doutb[10] = \<const0> ;
assign doutb[9] = \<const0> ;
assign doutb[8] = \<const0> ;
assign doutb[7] = \<const0> ;
assign doutb[6] = \<const0> ;
assign doutb[5] = \<const0> ;
assign doutb[4] = \<const0> ;
assign doutb[3] = \<const0> ;
assign doutb[2] = \<const0> ;
assign doutb[1] = \<const0> ;
assign doutb[0] = \<const0> ;
assign rdaddrecc[12] = \<const0> ;
assign rdaddrecc[11] = \<const0> ;
assign rdaddrecc[10] = \<const0> ;
assign rdaddrecc[9] = \<const0> ;
assign rdaddrecc[8] = \<const0> ;
assign rdaddrecc[7] = \<const0> ;
assign rdaddrecc[6] = \<const0> ;
assign rdaddrecc[5] = \<const0> ;
assign rdaddrecc[4] = \<const0> ;
assign rdaddrecc[3] = \<const0> ;
assign rdaddrecc[2] = \<const0> ;
assign rdaddrecc[1] = \<const0> ;
assign rdaddrecc[0] = \<const0> ;
assign rsta_busy = \<const0> ;
assign rstb_busy = \<const0> ;
assign s_axi_arready = \<const0> ;
assign s_axi_awready = \<const0> ;
assign s_axi_bid[3] = \<const0> ;
assign s_axi_bid[2] = \<const0> ;
assign s_axi_bid[1] = \<const0> ;
assign s_axi_bid[0] = \<const0> ;
assign s_axi_bresp[1] = \<const0> ;
assign s_axi_bresp[0] = \<const0> ;
assign s_axi_bvalid = \<const0> ;
assign s_axi_dbiterr = \<const0> ;
assign s_axi_rdaddrecc[12] = \<const0> ;
assign s_axi_rdaddrecc[11] = \<const0> ;
assign s_axi_rdaddrecc[10] = \<const0> ;
assign s_axi_rdaddrecc[9] = \<const0> ;
assign s_axi_rdaddrecc[8] = \<const0> ;
assign s_axi_rdaddrecc[7] = \<const0> ;
assign s_axi_rdaddrecc[6] = \<const0> ;
assign s_axi_rdaddrecc[5] = \<const0> ;
assign s_axi_rdaddrecc[4] = \<const0> ;
assign s_axi_rdaddrecc[3] = \<const0> ;
assign s_axi_rdaddrecc[2] = \<const0> ;
assign s_axi_rdaddrecc[1] = \<const0> ;
assign s_axi_rdaddrecc[0] = \<const0> ;
assign s_axi_rdata[11] = \<const0> ;
assign s_axi_rdata[10] = \<const0> ;
assign s_axi_rdata[9] = \<const0> ;
assign s_axi_rdata[8] = \<const0> ;
assign s_axi_rdata[7] = \<const0> ;
assign s_axi_rdata[6] = \<const0> ;
assign s_axi_rdata[5] = \<const0> ;
assign s_axi_rdata[4] = \<const0> ;
assign s_axi_rdata[3] = \<const0> ;
assign s_axi_rdata[2] = \<const0> ;
assign s_axi_rdata[1] = \<const0> ;
assign s_axi_rdata[0] = \<const0> ;
assign s_axi_rid[3] = \<const0> ;
assign s_axi_rid[2] = \<const0> ;
assign s_axi_rid[1] = \<const0> ;
assign s_axi_rid[0] = \<const0> ;
assign s_axi_rlast = \<const0> ;
assign s_axi_rresp[1] = \<const0> ;
assign s_axi_rresp[0] = \<const0> ;
assign s_axi_rvalid = \<const0> ;
assign s_axi_sbiterr = \<const0> ;
assign s_axi_wready = \<const0> ;
assign sbiterr = \<const0> ;
GND GND
(.G(\<const0> ));
pikachu_down_pixel_blk_mem_gen_v8_3_5_synth inst_blk_mem_gen
(.addra(addra),
.clka(clka),
.dina(dina),
.douta(douta),
.wea(wea));
endmodule |
module pikachu_down_pixel_blk_mem_gen_v8_3_5_synth
(douta,
addra,
clka,
dina,
wea);
output [11:0]douta;
input [12:0]addra;
input clka;
input [11:0]dina;
input [0:0]wea;
wire [12:0]addra;
wire clka;
wire [11:0]dina;
wire [11:0]douta;
wire [0:0]wea;
pikachu_down_pixel_blk_mem_gen_top \gnbram.gnativebmg.native_blk_mem_gen
(.addra(addra),
.clka(clka),
.dina(dina),
.douta(douta),
.wea(wea));
endmodule |
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule |
module dds_compiler_0(aclk, s_axis_phase_tvalid,
s_axis_phase_tdata, m_axis_data_tvalid, m_axis_data_tdata)
/* synthesis syn_black_box black_box_pad_pin="aclk,s_axis_phase_tvalid,s_axis_phase_tdata[23:0],m_axis_data_tvalid,m_axis_data_tdata[15:0]" */;
input aclk;
input s_axis_phase_tvalid;
input [23:0]s_axis_phase_tdata;
output m_axis_data_tvalid;
output [15:0]m_axis_data_tdata;
endmodule |
module */
always@(posedge clk_proc or negedge reset_n)
if (reset_n == 0)
data_d <= 0;
else
begin
dir_d <= d_max;
if (token_s[7])
if (m_max[((COEF_WIDTH + IN_SIZE)+1):0] > threshold[((COEF_WIDTH + IN_SIZE)+1):0])
if(binarize_bit)
data_d <= {(COEF_WIDTH + IN_SIZE - NORM_FACTOR){1'b1}};
else
data_d <= m_max[(COEF_WIDTH + IN_SIZE):NORM_FACTOR-1];
else
if(binarize_bit)
data_d <= {(COEF_WIDTH + IN_SIZE - NORM_FACTOR){1'b0}};
else
data_d <= {(COEF_WIDTH + IN_SIZE - NORM_FACTOR){1'b0}};
end
assign magnitude_data = data_d;
assign angle_data = dir_d;
assign magnitude_dv = token_s[8];
assign angle_dv = token_s[8];
assign magnitude_fv = (token_d[8]) ? 1'b1 : 1'b0;
assign angle_fv = (token_d[8]) ? 1'b1 : 1'b0;
/* ######### Avalon-MM Slave Interface ##############
CONFIG_SETUP - R/W
THRESHOLD - R/W
*/
/* Write operation */
always @ (*)
if (wr_i)
case(addr_rel_i)
1'd0:
begin
config_setup_new = datawr_i;
threshold_new = threshold;
end
1'd1:
begin
config_setup_new = config_setup;
threshold_new = datawr_i;
end
default:
begin
config_setup_new = config_setup;
threshold_new = threshold;
end
endcase
else /* wr_i does not enabled */
begin
config_setup_new = config_setup;
threshold_new = threshold;
end
/* Read operation */
always @ (*)
if (rd_i)
case(addr_rel_i)
1'd0: readdata_new = config_setup;
1'd1: readdata_new = threshold;
default:
readdata_new = datard_o;
endcase
else
readdata_new = datard_o;
/* Internal register */
always @ (posedge clk_proc or negedge reset_n)
if (reset_n == 1'b0)
begin
config_setup <= DEFAULT_SCR;
threshold <= DEFAULT_TH;
datard_o <= 32'b0;
end
else
begin
config_setup <= config_setup_new;
threshold <= threshold_new;
datard_o <= readdata_new;
end
/* ##################################### */
endmodule |
module pad_ddr2(ddr2_dll_bypass_l ,ddr2_bypass_data ,clk_ddr2_cken ,
spare_ddr2_pin ,bscan_mode_ctl_in ,spare_ddr2_pad ,bscan_hiz_l_in ,
ddr_si ,tck ,pad_ddr2_sscan_out ,dram2_io_bank ,dram2_dq ,dram2_cb
,dram2_ba ,dram2_cas_l ,dram2_ras_l ,dram2_cke ,pad_ddr2_sscan_in
,ddr_testmode_l ,ctu_ddr2_dll_delayctr ,dram2_io_cs_l ,afo ,
bypass_enable ,bypass_enable_out ,bscan_shift_dr_out ,
bscan_clock_dr_out ,bscan_hiz_l_out ,ps_select_out ,
bscan_update_dr_out ,serial_out ,afi ,vdd18 ,ddr2_ctu_dll_overflow
,bscan_mode_ctl_out ,pad_ddr2_bsi ,dram_arst_l ,dram_grst_l ,
dram_gclk ,dram2_ck_p ,ctu_global_snap ,dram_gdbginit_l ,
ctu_ddr2_iodll_rst_l ,test_mode ,bscan_clock_dr_in ,serial_in ,
dram2_io_ptr_clk_inv ,ctu_io_sscan_update ,ctu_io_sscan_se ,
spare_ddr2_paddata ,dram23_p_ref_res ,ddr2_ddr3_cbd ,ddr_so ,
ps_select ,dram23_n_ref_res ,dram2_dqs ,pad_ddr2_bso ,ddr_se ,
dram2_addr ,dram2_we_l ,dram2_ck_n ,dram_adbginit_l
,ddr2_ddr3_cbu ,bscan_shift_dr_in ,ddr2_ctu_dll_lock ,
dram2_io_pad_enable ,bscan_update_dr_in ,dram2_io_drive_enable ,
dram2_io_write_en_l ,dram2_io_cas_l ,dram2_io_ras_l ,
dram2_io_clk_enable ,io_dram2_data_valid ,dram2_io_addr ,
io_dram2_data_in ,dram2_io_channel_disabled ,io_dram2_ecc_in ,
dram2_io_drive_data ,dram2_io_data_out ,dram2_io_cke ,
dram2_io_pad_clk_inv ,dram2_cs_l ,spare_ddr2_pindata, ddr2_lpf_code );
output [4:0] ddr2_lpf_code ;
output [2:0] dram2_ba ;
output [143:0] serial_out ;
output [143:0] afi ;
output [3:0] dram2_ck_p ;
output [8:1] ddr2_ddr3_cbd ;
output [14:0] dram2_addr ;
output [3:0] dram2_ck_n ;
output [8:1] ddr2_ddr3_cbu ;
output [255:0] io_dram2_data_in ;
output [31:0] io_dram2_ecc_in ;
output [3:0] dram2_cs_l ;
input [4:0] ddr2_bypass_data ;
input [2:0] dram2_io_bank ;
input [2:0] ctu_ddr2_dll_delayctr ;
input [3:0] dram2_io_cs_l ;
input [143:0] afo ;
input [1:0] dram_gclk ;
input [143:0] serial_in ;
input [4:0] dram2_io_ptr_clk_inv ;
input [6:0] spare_ddr2_paddata ;
input [14:0] dram2_io_addr ;
input [287:0] dram2_io_data_out ;
input [2:0] spare_ddr2_pindata ;
inout [2:0] spare_ddr2_pin ;
inout [6:0] spare_ddr2_pad ;
inout [127:0] dram2_dq ;
inout [15:0] dram2_cb ;
inout [35:0] dram2_dqs ;
output pad_ddr2_sscan_out ;
output dram2_cas_l ;
output dram2_ras_l ;
output dram2_cke ;
output bypass_enable_out ;
output bscan_shift_dr_out ;
output bscan_clock_dr_out ;
output bscan_hiz_l_out ;
output ps_select_out ;
output bscan_update_dr_out ;
output ddr2_ctu_dll_overflow ;
output bscan_mode_ctl_out ;
output ddr_so ;
output pad_ddr2_bso ;
output dram2_we_l ;
output ddr2_ctu_dll_lock ;
output io_dram2_data_valid ;
input ddr2_dll_bypass_l ;
input clk_ddr2_cken ;
input bscan_mode_ctl_in ;
input bscan_hiz_l_in ;
input ddr_si ;
input tck ;
input pad_ddr2_sscan_in ;
input ddr_testmode_l ;
input bypass_enable ;
input vdd18 ;
input pad_ddr2_bsi ;
input dram_arst_l ;
input dram_grst_l ;
input ctu_global_snap ;
input dram_gdbginit_l ;
input ctu_ddr2_iodll_rst_l ;
input test_mode ;
input bscan_clock_dr_in ;
input ctu_io_sscan_update ;
input ctu_io_sscan_se ;
input dram23_p_ref_res ;
input ps_select ;
input dram23_n_ref_res ;
input ddr_se ;
input dram_adbginit_l ;
input bscan_shift_dr_in ;
input dram2_io_pad_enable ;
input bscan_update_dr_in ;
input dram2_io_drive_enable ;
input dram2_io_write_en_l ;
input dram2_io_cas_l ;
input dram2_io_ras_l ;
input dram2_io_clk_enable ;
input dram2_io_channel_disabled ;
input dram2_io_drive_data ;
input dram2_io_cke ;
input dram2_io_pad_clk_inv ;
supply1 vdd ;
supply0 vss ;
wire [7:0] net227 ;
wire [7:0] net246 ;
wire net0204 ;
wire net196 ;
wire rst_l ;
wire sscan0 ;
wire net228 ;
wire scan0 ;
wire scan1 ;
wire scan2 ;
wire scan3 ;
wire clk_ddr2_cken_buf ;
wire net247 ;
wire ddr_se_buf ;
wire rclk ;
wire arst2_l ;
bw_io_ddr_impctl_pulldown ddr2_impctl_pulldown (
.z ({ddr2_ddr3_cbd } ),
.from_csr ({vss ,vss ,vss ,vss ,vss ,vss ,vss ,vss } ),
.to_csr ({net246[0] ,net246[1] ,net246[2] ,net246[3] ,
net246[4] ,net246[5] ,net246[6] ,net246[7] } ),
.tclk (tck ),
.ctu_global_snap (ctu_global_snap ),
.ctu_io_sscan_in (sscan0 ),
.ctu_io_sscan_se (ctu_io_sscan_se ),
.ctu_io_sscan_update (ctu_io_sscan_update ),
.ctu_io_sscan_out (pad_ddr2_sscan_out ),
.rclk (rclk ),
.deltabit (net247 ),
.hard_reset_n (rst_l ),
.clk_dis_l (clk_ddr2_cken_buf ),
.we_csr (vss ),
.si (scan1 ),
.se (ddr_se_buf ),
.vdd18 (vdd18 ),
.pad (dram23_n_ref_res ),
.so (scan2 ) );
bw_io_ddr_impctl_pullup ddr2_impctl_pullup (
.z ({ddr2_ddr3_cbu } ),
.from_csr ({vss ,vss ,vss ,vss ,vss ,vss ,vss ,vss } ),
.to_csr ({net227[0] ,net227[1] ,net227[2] ,net227[3] ,
net227[4] ,net227[5] ,net227[6] ,net227[7] } ),
.rclk (rclk ),
.so (scan1 ),
.deltabit (net228 ),
.hard_reset_n (rst_l ),
.clk_dis_l (clk_ddr2_cken_buf ),
.we_csr (vss ),
.si (scan0 ),
.se (ddr_se_buf ),
.ctu_io_sscan_se (ctu_io_sscan_se ),
.vdd18 (vdd18 ),
.ctu_io_sscan_in (pad_ddr2_sscan_in ),
.ctu_io_sscan_out (sscan0 ),
.ctu_io_sscan_update (ctu_io_sscan_update ),
.pad (dram23_p_ref_res ),
.ctu_global_snap (ctu_global_snap ),
.tclk (tck ) );
// ECO 7016: added instance ddr2_iodll_code_adjust 10/11/04
// ECO 7016: Changed so, lpf_out connections on ddr2_master_dll
wire [4:0] ddr2_lpf_code_pre;
wire scan3_pre;
bw_iodll_code_adjust ddr2_iodll_code_adjust (
.bypass_data (ddr2_bypass_data[4:0]),
.ddr_clk_in (rclk),
.delay_ctrl (ctu_ddr2_dll_delayctr[2:0]),
.io_dll_bypass_l (ddr2_dll_bypass_l),
.iodll_reset_l (ctu_ddr2_iodll_rst_l),
.s_controller_out (ddr2_lpf_code_pre[4:0]),
.s_percent_ctrl_out (ddr2_lpf_code[4:0]),
.se (ddr_se_buf),
.si (scan3_pre),
.so (scan3));
bw_iodll ddr2_master_dll (
.ddr_testmode_l (ddr_testmode_l ),
.bypass_data ({ddr2_bypass_data } ),
.lpf_out (ddr2_lpf_code_pre ),
.delay_ctrl ({ctu_ddr2_dll_delayctr } ),
.so (scan3_pre ),
.io_dll_bypass_l (ddr2_dll_bypass_l ),
.io_dll_reset_l (ctu_ddr2_iodll_rst_l ),
.se (ddr_se_buf ),
.si (scan2 ),
.ddr_clk_in (rclk ),
.iodll_lock (ddr2_ctu_dll_lock ),
.overflow (ddr2_ctu_dll_overflow ),
.strobe (net0204 ) );
// End ECO 7016
bw_clk_cl_ddr_ddr pad_ddr2_header (
.gclk ({dram_gclk } ),
.ddr_rclk (rclk ),
.so (ddr_so_pre_latch ),
.si (scan3 ),
.gdbginit_l (dram_gdbginit_l ),
.grst_l (dram_grst_l ),
.cluster_grst_l (rst_l ),
.dbginit_l (net196 ),
.rclk (rclk ),
.se (ddr_se_buf ),
.adbginit_l (dram_adbginit_l ),
.arst2_l (arst2_l ),
.arst_l (dram_arst_l ),
.cluster_cken (clk_ddr2_cken_buf ) );
bw_u1_buf_40x I223 (
.z (ddr_se_buf ),
.a (ddr_se ) );
ddr_ch ddr2_ddr_ch (
.arst_l_out (arst2_l ),
.afo ({afo } ),
.serial_in ({serial_in } ),
.afi ({afi } ),
.serial_out ({serial_out } ),
.dram_io_data_out ({dram2_io_data_out } ),
.spare_ddr_pin ({spare_ddr2_pin[2] ,spare_ddr2_pad[6:0] ,
spare_ddr2_pin[1:0] } ),
.spare_ddr_data ({spare_ddr2_pindata[2] ,spare_ddr2_paddata[6:0] ,
spare_ddr2_pindata[1:0] } ),
.dram_io_ptr_clk_inv ({dram2_io_ptr_clk_inv } ),
.io_dram_data_in ({io_dram2_data_in } ),
.io_dram_ecc_in ({io_dram2_ecc_in } ),
.dram_io_addr ({dram2_io_addr } ),
.dram_io_bank ({dram2_io_bank } ),
.dram_io_cs_l ({dram2_io_cs_l } ),
.dram_dq ({dram2_dq } ),
.dram_addr ({dram2_addr } ),
.dram_cb ({dram2_cb } ),
.dram_dqs ({dram2_dqs } ),
.dram_ba ({dram2_ba } ),
.dram_ck_n ({dram2_ck_n } ),
.dram_ck_p ({dram2_ck_p } ),
.dram_cs_l ({dram2_cs_l } ),
.lpf_code (ddr2_lpf_code ),
.cbu ({ddr2_ddr3_cbu } ),
.cbd ({ddr2_ddr3_cbd } ),
.update_dr_in (bscan_update_dr_in ),
.mode_ctrl_in (bscan_mode_ctl_in ),
.shift_dr_in (bscan_shift_dr_in ),
.clock_dr_in (bscan_clock_dr_in ),
.hiz_n_in (bscan_hiz_l_in ),
.testmode_l (ddr_testmode_l ),
.test_mode (test_mode ),
.bypass_enable_out (bypass_enable_out ),
.ps_select_out (ps_select_out ),
.rclk (rclk ),
.se (ddr_se_buf ),
.pad_clk_so (scan0 ),
.pad_clk_si (ddr_si ),
.bso (pad_ddr2_bso ),
.bsi (pad_ddr2_bsi ),
.mode_ctrl_out (bscan_mode_ctl_out ),
.update_dr_out (bscan_update_dr_out ),
.shift_dr_out (bscan_shift_dr_out ),
.clock_dr_out (bscan_clock_dr_out ),
.hiz_n_out (bscan_hiz_l_out ),
.bypass_enable_in (bypass_enable ),
.ps_select_in (ps_select ),
.strobe (net0204 ),
.dram_io_clk_enable (dram2_io_clk_enable ),
.dram_io_cke (dram2_io_cke ),
.dram_io_ras_l (dram2_io_ras_l ),
.dram_io_write_en_l (dram2_io_write_en_l ),
.dram_io_cas_l (dram2_io_cas_l ),
.dram_cke (dram2_cke ),
.io_dram_data_valid (io_dram2_data_valid ),
.dram_ras_l (dram2_ras_l ),
.dram_we_l (dram2_we_l ),
.dram_cas_l (dram2_cas_l ),
.burst_length_four (vdd ),
.dram_io_pad_clk_inv (dram2_io_pad_clk_inv ),
.dram_io_pad_enable (dram2_io_pad_enable ),
.dram_io_drive_enable (dram2_io_drive_enable ),
.rst_l (rst_l ),
.dram_arst_l (dram_arst_l ),
.dram_io_channel_disabled (dram2_io_channel_disabled ),
.dram_io_drive_data (dram2_io_drive_data ),
.vdd_h (vdd18 ) );
bw_u1_buf_40x I225 (
.z (clk_ddr2_cken_buf ),
.a (clk_ddr2_cken ) );
bw_u1_scanl_2x lockup_latch(
.so(ddr_so),
.sd(ddr_so_pre_latch),
.ck(rclk));
endmodule |
module header
// Internal signals
//
// Generated Signal List
//
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
//
// Generated Signal Assignments
//
//
// Generated Instances and Port Mappings
//
endmodule |
module asyn_64_1 (
aclr,
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
rdempty);
input aclr;
input [0:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [0:0] q;
output rdempty;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [0:0] sub_wire0;
wire sub_wire1;
wire [0:0] q = sub_wire0[0:0];
wire rdempty = sub_wire1;
dcfifo dcfifo_component (
.aclr (aclr),
.data (data),
.rdclk (rdclk),
.rdreq (rdreq),
.wrclk (wrclk),
.wrreq (wrreq),
.q (sub_wire0),
.rdempty (sub_wire1),
.rdfull (),
.rdusedw (),
.wrempty (),
.wrfull (),
.wrusedw ());
defparam
dcfifo_component.intended_device_family = "Stratix V",
dcfifo_component.lpm_numwords = 64,
dcfifo_component.lpm_showahead = "ON",
dcfifo_component.lpm_type = "dcfifo",
dcfifo_component.lpm_width = 1,
dcfifo_component.lpm_widthu = 6,
dcfifo_component.overflow_checking = "ON",
dcfifo_component.rdsync_delaypipe = 5,
dcfifo_component.read_aclr_synch = "OFF",
dcfifo_component.underflow_checking = "ON",
dcfifo_component.use_eab = "ON",
dcfifo_component.write_aclr_synch = "OFF",
dcfifo_component.wrsync_delaypipe = 5;
endmodule |
module
.writenum(writenum),
.write(write),
.mdata(mdata),
.sximm5(sximm5),
.sximm8(sximm8),
// outputs
.status(LEDR[9:7]),
.B(B),
.C(C)
);
decoder decoderInstantiate(
.instruction(instruction),
.nsel(nsel),
.opcode(opcode),
.readnum(readnum),
.writenum(writenum),
.ALUop(ALUop),
.op(op),
.shift(shift),
.sximm5(sximm5),
.sximm8(sximm8)
);
instructionReg instrRegInstantiate(
.clk(~KEY[0]),
.mdata(mdata),
.loadir(loadir),
.instruction(instruction)
);
RAM #(16,8,"data.txt") RAMInstantiate(
.clk(~KEY[0]),
.readAddress(address),
.writeAddress(address),
.mwrite(mwrite),
.in(B), //B is what is being written in
.out(mdata) //output is both instructions as well as values in the addresses
);
counter counterInstantiate(
.clk(~KEY[0]),
.reset(~KEY[1]),
.loadpc(loadpc),
.msel(msel),
.C(C),
.address(address) //output of counter is the read address
);
controller controllerInstantiate(
.clk(~KEY[0]),
.ALUop(ALUop),
.op(op),
.shift(shift),
.opcode(opcode),
.readnum(readnum),
.writenum(writenum),
.loada(loada),
.loadb(loadb),
.write(write),
.asel(asel),
.bsel(bsel),
.loadc(loadc),
.loads(loads),
.reset(~KEY[1]),
.loadpc(loadpc),
.msel(msel),
.mwrite(mwrite),
.loadir(loadir),
.nsel(nsel),
.vsel(vsel)
);
// assigned HEX display to datapath_out values
// HEXDisplay HEX0Instantiate(datapath_out[3:0], HEX0);
// HEXDisplay HEX1Instantiate(datapath_out[7:4], HEX1);
// HEXDisplay HEX2Instantiate(datapath_out[11:8], HEX2);
// HEXDisplay HEX3Instantiate(datapath_out[15:12], HEX3);
// assign HEX4 = 7'b1111111; // disabled
// assign HEX5 = 7'b1111111; // disabled
endmodule |
module sky130_fd_sc_hs__dlxtp_1 (
Q ,
D ,
GATE,
VPWR,
VGND
);
output Q ;
input D ;
input GATE;
input VPWR;
input VGND;
sky130_fd_sc_hs__dlxtp base (
.Q(Q),
.D(D),
.GATE(GATE),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule |
module sky130_fd_sc_hs__dlxtp_1 (
Q ,
D ,
GATE
);
output Q ;
input D ;
input GATE;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__dlxtp base (
.Q(Q),
.D(D),
.GATE(GATE)
);
endmodule |
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