module_content
stringlengths 18
1.05M
|
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module UDivider(Quotient, Remainder, Dividend, Divisor);
output [31:0] Quotient;
output [31:0] Remainder;
input [31:0] Divisor;
input [31:0] Dividend;
wire [31:0] TR[0:32];
wire cin;
wire cout;
wire garbage;
stepof32 myStep1(TR[0], garbage, 0, Dividend[31], Divisor, 1);
stepof32 myStep2(TR[1], Quotient[31], TR[0], Dividend[30], Divisor, garbage);
stepof32 myStep3(TR[2], Quotient[30], TR[1], Dividend[29], Divisor, Quotient[31]);
stepof32 myStep4(TR[3], Quotient[29], TR[2], Dividend[28], Divisor, Quotient[30]);
stepof32 myStep5(TR[4], Quotient[28], TR[3], Dividend[27], Divisor, Quotient[29]);
stepof32 myStep6(TR[5], Quotient[27], TR[4], Dividend[26], Divisor, Quotient[28]);
stepof32 myStep7(TR[6], Quotient[26], TR[5], Dividend[25], Divisor, Quotient[27]);
stepof32 myStep8(TR[7], Quotient[25], TR[6], Dividend[24], Divisor, Quotient[26]);
stepof32 myStep9(TR[8], Quotient[24], TR[7], Dividend[23], Divisor, Quotient[25]);
stepof32 myStep10(TR[9], Quotient[23], TR[8], Dividend[22], Divisor, Quotient[24]);
stepof32 myStep11(TR[10], Quotient[22], TR[9], Dividend[21], Divisor, Quotient[23]);
stepof32 myStep12(TR[11], Quotient[21], TR[10], Dividend[20], Divisor, Quotient[22]);
stepof32 myStep13(TR[12], Quotient[20], TR[11], Dividend[19], Divisor, Quotient[21]);
stepof32 myStep14(TR[13], Quotient[19], TR[12], Dividend[18], Divisor, Quotient[20]);
stepof32 myStep15(TR[14], Quotient[18], TR[13], Dividend[17], Divisor, Quotient[19]);
stepof32 myStep16(TR[15], Quotient[17], TR[14], Dividend[16], Divisor, Quotient[18]);
stepof32 myStep17(TR[16], Quotient[16], TR[15], Dividend[15], Divisor, Quotient[17]);
stepof32 myStep18(TR[17], Quotient[15], TR[16], Dividend[14], Divisor, Quotient[16]);
stepof32 myStep19(TR[18], Quotient[14], TR[17], Dividend[13], Divisor, Quotient[15]);
stepof32 myStep20(TR[19], Quotient[13], TR[18], Dividend[12], Divisor, Quotient[14]);
stepof32 myStep21(TR[20], Quotient[12], TR[19], Dividend[11], Divisor, Quotient[13]);
stepof32 myStep22(TR[21], Quotient[11], TR[20], Dividend[10], Divisor, Quotient[12]);
stepof32 myStep23(TR[22], Quotient[10], TR[21], Dividend[9], Divisor, Quotient[11]);
stepof32 myStep24(TR[23], Quotient[9], TR[22], Dividend[8], Divisor, Quotient[10]);
stepof32 myStep25(TR[24], Quotient[8], TR[23], Dividend[7], Divisor, Quotient[9]);
stepof32 myStep26(TR[25], Quotient[7], TR[24], Dividend[6], Divisor, Quotient[8]);
stepof32 myStep27(TR[26], Quotient[6], TR[25], Dividend[5], Divisor, Quotient[7]);
stepof32 myStep28(TR[27], Quotient[5], TR[26], Dividend[4], Divisor, Quotient[6]);
stepof32 myStep29(TR[28], Quotient[4], TR[27], Dividend[3], Divisor, Quotient[5]);
stepof32 myStep30(TR[29], Quotient[3], TR[28], Dividend[2], Divisor, Quotient[4]);
stepof32 myStep31(TR[30], Quotient[2], TR[29], Dividend[1], Divisor, Quotient[3]);
stepof32 myStep32(TR[31], Quotient[1], TR[30], Dividend[0], Divisor, Quotient[2]);
laststepof32 myStep33(Remainder,Quotient[0],TR[31],Divisor,Quotient[1]); //Includes a step similar to stepof32
//$display ("HEllo");
endmodule
|
module sky130_fd_sc_hs__dlrtn (
RESET_B,
D ,
GATE_N ,
Q ,
VPWR ,
VGND
);
// Module ports
input RESET_B;
input D ;
input GATE_N ;
output Q ;
input VPWR ;
input VGND ;
// Local signals
wire RESET ;
wire intgate ;
reg notifier ;
wire D_delayed ;
wire GATE_N_delayed ;
wire RESET_delayed ;
wire RESET_B_delayed;
wire buf_Q ;
wire awake ;
wire cond0 ;
wire cond1 ;
// Name Output Other arguments
not not0 (RESET , RESET_B_delayed );
not not1 (intgate, GATE_N_delayed );
sky130_fd_sc_hs__u_dl_p_r_no_pg u_dl_p_r_no_pg0 (buf_Q , D_delayed, intgate, RESET, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond0 = ( awake && ( RESET_B_delayed === 1'b1 ) );
assign cond1 = ( awake && ( RESET_B === 1'b1 ) );
buf buf0 (Q , buf_Q );
endmodule
|
module sky130_fd_sc_ms__o22a (
X ,
A1,
A2,
B1,
B2
);
output X ;
input A1;
input A2;
input B1;
input B2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
|
module sky130_fd_sc_hs__edfxtp (
Q ,
CLK ,
D ,
DE ,
VPWR,
VGND
);
// Module ports
output Q ;
input CLK ;
input D ;
input DE ;
input VPWR;
input VGND;
// Local signals
wire buf_Q;
// Delay Name Output Other arguments
sky130_fd_sc_hs__u_edf_p_pg `UNIT_DELAY u_edf_p_pg0 (buf_Q , D, CLK, DE, VPWR, VGND);
buf buf0 (Q , buf_Q );
endmodule
|
module
// and do not propogate out to other modules that may be attached, complicating
// timing assertions.
//
bsg_two_fifo #(.width_p(channel_width_p)) twofer
(.clk_i(core_clk_i)
,.reset_i(core_reset_i)
// we feed this into the local yumi, but only if it is valid
,.ready_o(core_twofer_ready)
,.data_i(core_data_o_pre_twofer)
,.v_i(core_valid_o_pre_twofer)
,.v_o(core_valid_o)
,.data_o(core_data_o)
,.yumi_i(core_yumi_i)
);
// a word was transferred to the two input fifo if ...
wire core_transfer_success = core_valid_o_tmp & core_twofer_ready;
/*
// deque if there was an actual transfer, AND (
assign core_actual_deque = core_transfer_success
// we sent the 0th word already,
// and just sent the 1st word, OR
& ((core_sent_0_want_to_send_1_r & core_valid_1)
// we sent the 0th word and there is no 1st word OR
// we sent the 1st word, and there is no 0th word
| (core_valid_0 ^ core_valid_1));
*/
assign core_actual_deque = core_transfer_success & ~(~core_sent_0_want_to_send_1_r & core_valid_1 & core_valid_0);
always @(posedge core_clk_i)
begin
if (core_reset_i)
core_sent_0_want_to_send_1_r <= 0;
else
// if we transferred data, but do not deque, we must have another word to
// transfer. mbt fixme: this was originally:
// core_transfer_success & ~core_actual_deque
// but had a bug. review further.
core_sent_0_want_to_send_1_r <= core_transfer_success
? ~core_actual_deque
: core_sent_0_want_to_send_1_r;
end
// **********************************************
// credit return
//
// these are credits coming from the receive end of the async fifo in the core clk
// domain and passing to the io clk domain and out of the chip.
//
logic [lg_fifo_depth_p+1-1:0] core_credits_gray_r_iosync
, core_credits_binary_r_iosync
, io_credits_sent_r, io_credits_sent_r_gray
, io_credits_sent_r_p1, io_credits_sent_r_p2;
bsg_async_ptr_gray #(.lg_size_p(lg_fifo_depth_p+1)) bapg
(.w_clk_i (core_clk_i)
,.w_reset_i(core_reset_i)
,.w_inc_i (core_transfer_success)
,.r_clk_i (io_clk_i)
,.w_ptr_binary_r_o() // not needed
,.w_ptr_gray_r_o() // not needed
,.w_ptr_gray_r_rsync_o(core_credits_gray_r_iosync)
);
// this logic allows us to return two credits at a time
// note: generally relies on power-of-twoness of io_credits_sent_r
// to do correct wrap around.
always_comb io_credits_sent_r_p1 = io_credits_sent_r+1;
always_comb io_credits_sent_r_p2 = io_credits_sent_r+2;
// which bit of the io_credits_sent_r counter we use determines
// the value of the token line in credits
//
//
// this signal's register should be placed right next to the I/O pad:
// glitch sensitive.
assign io_token_r_o = io_credits_sent_r[lg_credit_to_token_decimation_p];
// we actually absorb credits one or two at a time rather as fast as we can.
// this because otherwise we would not be slowing transition rates on the token
// signal, which is the whole point of tokens! this is slightly suboptimal,
// because if enough cycles have passed from the last
// time we sent a token, we could actually acknowledge things faster if we
// absorbed more than one credit at a time.
// that's okay. we skip this optimization.
// during token bypass mode, we hardwire the credit signal to the trigger mode signals;
// this gives the output channel control over the credit signal which
// allows it to toggle and reset the credit logic.
// the use of this trigger signal means that we should avoid the use of these
// two signals for calibration codes, so that we do not mix calibration codes
// when reset goes low with token reset operation, which would be difficult to avoid
// since generally we cannot control the timing of these reset signals when
// they cross asynchronous boundaries
// this is an optimized token increment system
// we actually gray code two options and compare against
// the incoming greycoded pointer. this is because it's cheaper
// to grey code than to de-gray code. moreover, we theorize it's cheaper
// to compute an incremented gray code than to add one to a pointer.
assign io_credits_sent_r_gray = (io_credits_sent_r >> 1) ^ io_credits_sent_r;
logic [lg_fifo_depth_p+1-1:0] io_credits_sent_p1_r_gray;
bsg_binary_plus_one_to_gray #(.width_p(lg_fifo_depth_p+1)) bsg_bp1_2g
(.binary_i(io_credits_sent_r)
,.gray_o(io_credits_sent_p1_r_gray)
);
wire empty_1 = (core_credits_gray_r_iosync != io_credits_sent_p1_r_gray);
wire empty_0 = (core_credits_gray_r_iosync != io_credits_sent_r_gray);
always @(posedge io_clk_i)
begin
if (io_token_bypass_i)
io_credits_sent_r <= { lg_fifo_depth_p+1
{ io_trigger_mode_1 & io_trigger_mode_0 } };
else
// we absorb up to two credits per cycles, since we receive at DDR,
// we need this to rate match the incoming data
// code is written like this because empty_1 is late relative to empty_0
io_credits_sent_r <= (empty_1
? (empty_0 ? io_credits_sent_r_p2 : io_credits_sent_r)
: (empty_0 ? io_credits_sent_r_p1 : io_credits_sent_r));
end
endmodule
|
module sky130_fd_sc_lp__a22oi (
//# {{data|Data Signals}}
input A1,
input A2,
input B1,
input B2,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
|
module I2S_DAC(clk50M, sck, ws, sd,
//DAC_L, DAC_R
dac_dat,
outr,
sw1
);
//general
input wire clk50M;
//i2s
input wire sck, ws, sd;
//custom dac
//output wire DAC_L, DAC_R;
//r2r 8bit dac
output wire [7:0] dac_dat;
output wire outr;
input wire sw1;
//i2s receiver
wire [31:0] data_left;
wire [31:0] data_right;
i2s_receive2 rcv(.sck(sck),
.ws(ws),
.sd(sd),
.data_left(data_left),
.data_right(data_right));
assign outr = (data_left==data_right);
wire [31:0] us_data_left = data_left + 32'b10000000000000000000000000000000; //signed data in unsigned register. this is conversion
wire [31:0] us_data_right = data_right + 32'b10000000000000000000000000000000; //signed data in unsigned register. this is conversion
//assign dac_dat = us_data_right[31:31-7];
//dac regs cross domain
reg [31:0] word_l_;
//reg [31:0] word_r_;
reg [31:0] word_l__;
//reg [31:0] word_r__;
reg [7:0] word_l;
//reg [7:0] word_r;
wire clk200M;
pll200M pll(.inclk0(clk50M),
.c0(clk200M));
always @(posedge clk200M) begin
word_l_ <= (us_data_left);
//word_r_ <= (us_data_left);
word_l__ <= word_l_;
//word_r__ <= word_r_;
word_l <= word_l__[31:31-7];
//word_r <= word_r__[31:31-7];
end
//dacs
wire DAC_L, DAC_R;
ds8dac1 /*#(.width(8))*/ dac_l(.clk(clk200M),
.DACin(word_l),
.DACout(DAC_L));
//pwm8dac1 dac_r(.clk(clk200M),
// .in_data(word_r),
// .sout(DAC_R));
//standart 8 bit pwm dac
assign dac_dat = (sw1) ? {DAC_L,DAC_L,DAC_L,DAC_L,DAC_L,DAC_L,DAC_L,DAC_L} : word_l;
//assign dac_dat = us_data_right[31:31-7];
//hi pwm, lo r2r
//assign dac_dat = {word_l__[23],word_l__[22],word_l__[21],word_l__[20],word_l__[19],word_l__[18],word_l__[17],word_l__[16]};
endmodule
|
module bw_sys(/*AUTOARG*/
// Outputs
ssi_miso, ext_int_l, clk_stretch, warm_rst_l, temp_trig,
// Inputs
j_rst_l, jbus_gclk, ssi_sck, ssi_mosi
);
//input to system.
input j_rst_l;
input jbus_gclk;
input ssi_sck;
input ssi_mosi;
//output to ciop.
output ssi_miso;
output ext_int_l;
output clk_stretch;
output warm_rst_l;
output temp_trig;
//temp. registers
reg ssi_miso_r;
reg ext_int_l_r;
reg temp_trig_r;
reg clk_stretch_r;
//ok push button rst
reg ok_io, ok_reset, rst_val;
// initial values for all reg
initial begin
rst_val = 1 ;
ext_int_l_r = 1 ;
temp_trig_r = 0 ;
clk_stretch_r = 0;
end
//create wramrest signal.
assign warm_rst_l = rst_val ;
initial begin
ok_reset = 1;
end
//how many cores are turned on.
//assign and drive
assign ext_int_l = ext_int_l_r;
assign ssi_miso = ssi_miso_r;
assign temp_trig = temp_trig_r;
assign clk_stretch = clk_stretch_r;
initial
begin
ok_io = 0;
ext_int_l_r = 1;
ssi_miso_r = 0;
temp_trig_r = 0;
while (j_rst_l !== 0) @(posedge jbus_gclk) ;
@(posedge j_rst_l);//wait for the push button reset.
ok_io = 1;
end
//interface between ssi bus and io.
always @(posedge ssi_sck)begin
if(ok_io)$ssi_drive(
//input
ssi_mosi,
//ouput
ssi_miso_r,
);
end // always @ (posedge ssi_sck)
// jbus clk domain here.
// 2). warm reset
// 3). external interrupt
always @(posedge jbus_gclk)begin
if(ok_reset)begin
$pc_trigger_event(3,
rst_val,
ext_int_l_r,
temp_trig_r,
clk_stretch_r
);
end
end
endmodule
|
module system_xlconstant_0_1
(dout);
output [31:0]dout;
wire \<const0> ;
wire \<const1> ;
assign dout[31] = \<const0> ;
assign dout[30] = \<const0> ;
assign dout[29] = \<const0> ;
assign dout[28] = \<const0> ;
assign dout[27] = \<const0> ;
assign dout[26] = \<const0> ;
assign dout[25] = \<const0> ;
assign dout[24] = \<const0> ;
assign dout[23] = \<const0> ;
assign dout[22] = \<const0> ;
assign dout[21] = \<const0> ;
assign dout[20] = \<const0> ;
assign dout[19] = \<const0> ;
assign dout[18] = \<const0> ;
assign dout[17] = \<const0> ;
assign dout[16] = \<const0> ;
assign dout[15] = \<const0> ;
assign dout[14] = \<const0> ;
assign dout[13] = \<const1> ;
assign dout[12] = \<const0> ;
assign dout[11] = \<const0> ;
assign dout[10] = \<const1> ;
assign dout[9] = \<const1> ;
assign dout[8] = \<const1> ;
assign dout[7] = \<const0> ;
assign dout[6] = \<const0> ;
assign dout[5] = \<const0> ;
assign dout[4] = \<const1> ;
assign dout[3] = \<const0> ;
assign dout[2] = \<const0> ;
assign dout[1] = \<const0> ;
assign dout[0] = \<const0> ;
GND GND
(.G(\<const0> ));
VCC VCC
(.P(\<const1> ));
endmodule
|
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
|
module nukv_Read #(
parameter KEY_WIDTH = 128,
parameter META_WIDTH = 96,
parameter HASHADDR_WIDTH = 32,
parameter MEMADDR_WIDTH = 20
)
(
// Clock
input wire clk,
input wire rst,
input wire [KEY_WIDTH+META_WIDTH+HASHADDR_WIDTH-1:0] input_data,
input wire input_valid,
output wire input_ready,
input wire [KEY_WIDTH+META_WIDTH+HASHADDR_WIDTH-1:0] feedback_data,
input wire feedback_valid,
output wire feedback_ready,
output reg [KEY_WIDTH+META_WIDTH+HASHADDR_WIDTH-1:0] output_data,
output reg output_valid,
input wire output_ready,
output reg [31:0] rdcmd_data,
output reg rdcmd_valid,
input wire rdcmd_ready
);
reg selectInputNext;
reg selectInput; //1 == input, 0==feedback
localparam [2:0]
ST_IDLE = 0,
ST_ISSUE_READ = 3,
ST_OUTPUT_KEY = 4;
reg [2:0] state;
wire[HASHADDR_WIDTH+KEY_WIDTH+META_WIDTH-1:0] in_data;
wire in_valid;
reg in_ready;
wire[31:0] hash_data;
assign in_data = (selectInput==1) ? input_data : feedback_data;
assign in_valid = (selectInput==1) ? input_valid : feedback_valid;
assign input_ready = (selectInput==1) ? in_ready : 0;
assign feedback_ready = (selectInput==1) ? 0 : in_ready;
assign hash_data = (selectInput==1) ? input_data[KEY_WIDTH+META_WIDTH+HASHADDR_WIDTH-1:KEY_WIDTH+META_WIDTH] : feedback_data[KEY_WIDTH+META_WIDTH+HASHADDR_WIDTH-1:KEY_WIDTH+META_WIDTH];
wire[MEMADDR_WIDTH-1:0] addr;
assign addr = hash_data[31:32 - MEMADDR_WIDTH] ^ hash_data[MEMADDR_WIDTH-1:0];
always @(posedge clk) begin
if (rst) begin
selectInput <= 1;
selectInputNext <= 0;
state <= ST_IDLE;
in_ready <= 0;
rdcmd_valid <= 0;
output_valid <= 0;
end
else begin
if (rdcmd_ready==1 && rdcmd_valid==1) begin
rdcmd_valid <= 0;
end
if (output_ready==1 && output_valid==1) begin
output_valid <= 0;
end
in_ready <= 0;
case (state)
ST_IDLE : begin
if (output_ready==1 && rdcmd_ready==1) begin
selectInput <= selectInputNext;
selectInputNext <= ~selectInputNext;
if (selectInputNext==1 && input_valid==0 && feedback_valid==1) begin
selectInput <= 0;
selectInputNext <= 1;
end
if (selectInputNext==0 && input_valid==1 && feedback_valid==0) begin
selectInput <= 1;
selectInputNext <= 0;
end
if (selectInput==1 && input_valid==1) begin
state <= ST_ISSUE_READ;
end
if (selectInput==0 && feedback_valid==1) begin
state <= ST_ISSUE_READ;
end
end
end
ST_ISSUE_READ: begin
if (in_data[KEY_WIDTH+META_WIDTH-4]==1) begin
// ignore this and don't send read!
end else begin
rdcmd_data <= addr;
rdcmd_valid <= 1;
rdcmd_data[31:MEMADDR_WIDTH] <= 0;
end
state <= ST_OUTPUT_KEY;
output_data <= in_data;
output_data[KEY_WIDTH+META_WIDTH+HASHADDR_WIDTH-1:KEY_WIDTH+META_WIDTH] <= addr; //(in_data[KEY_WIDTH+META_WIDTH-1]==0) ? addr1 : addr2;
in_ready <= 1;
end
ST_OUTPUT_KEY: begin
if (output_ready==1) begin
output_valid <= 1;
state <= ST_IDLE;
end
end
endcase
end
end
endmodule
|
module sky130_fd_sc_lp__dlrtn (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{control|Control Signals}}
input RESET_B,
//# {{clocks|Clocking}}
input GATE_N ,
//# {{power|Power}}
input VPB ,
input VPWR ,
input VGND ,
input VNB
);
endmodule
|
module sky130_fd_sc_hvl__udp_dff$P (
Q ,
D ,
CLK
);
output Q ;
input D ;
input CLK;
endmodule
|
module jfsmMooreWithOverlap(dataout, clock, reset, datain);
output reg dataout;
input clock, reset, datain;
reg[2:0] cs, ns;
parameter a = 3'b000;
parameter b = 3'b001;
parameter c = 3'b010;
parameter d = 3'b011;
parameter e = 3'b100;
parameter f = 3'b101;
always @(posedge clock)
begin
if(reset)
cs <= a;
else
cs <= ns;
end
always @(cs, datain)
begin
case(cs)
a:
begin
if(datain)
ns <= b;
else
ns <= a;
end
b:
begin
if(datain)
ns <= c;
else
ns <= b;
end
c:
begin
if(datain)
ns <= d;
else
ns <= a;
end
d:
begin
if(datain)
ns <= d;
else
ns <= e;
end
e:
begin
if(datain)
ns <= f;
else
ns <= a;
end
f:
begin
if(datain)
ns <= c; // This has to be ns <= a; if we have to consider with overlap
else
ns <= a;
end
endcase
end
// This will assign the correct status to the dataout bit
always @(cs, datain)
begin
if ( cs == e && datain == 1 )
dataout <= 1;
else
dataout <= 0;
end
endmodule
|
module arbiter(/*AUTOARG*/
// Outputs
wb_m0_vcache_dat_o, wb_m0_vcache_ack_o, wb_m1_cpu_dat_o,
wb_m1_cpu_ack_o, wb_s0_cellram_wb_adr_o, wb_s0_cellram_wb_dat_o,
wb_s0_cellram_wb_sel_o, wb_s0_cellram_wb_stb_o,
wb_s0_cellram_wb_cyc_o, wb_s0_cellram_wb_we_o,
// Inputs
wb_clk, wb_rst, wb_m0_vcache_adr_i, wb_m0_vcache_dat_i,
wb_m0_vcache_sel_i, wb_m0_vcache_cyc_i, wb_m0_vcache_stb_i,
wb_m0_vcache_we_i, wb_m1_cpu_adr_i, wb_m1_cpu_dat_i,
wb_m1_cpu_sel_i, wb_m1_cpu_cyc_i, wb_m1_cpu_stb_i, wb_m1_cpu_we_i,
wb_s0_cellram_wb_dat_i, wb_s0_cellram_wb_ack_i
//
,cellram_mst_sel
);
input wire wb_clk, wb_rst;
input wire [31:0] wb_m0_vcache_adr_i;
input wire [31:0] wb_m0_vcache_dat_i;
input wire [3:0] wb_m0_vcache_sel_i;
input wire wb_m0_vcache_cyc_i;
input wire wb_m0_vcache_stb_i;
input wire wb_m0_vcache_we_i;
output wire [31:0] wb_m0_vcache_dat_o;
output wire wb_m0_vcache_ack_o;
input wire [31:0] wb_m1_cpu_adr_i;
input wire [31:0] wb_m1_cpu_dat_i;
input wire [3:0] wb_m1_cpu_sel_i;
input wire wb_m1_cpu_cyc_i;
input wire wb_m1_cpu_stb_i;
input wire wb_m1_cpu_we_i;
output wire [31:0] wb_m1_cpu_dat_o;
output wire wb_m1_cpu_ack_o;
output wire [31:0] wb_s0_cellram_wb_adr_o;
output wire [31:0] wb_s0_cellram_wb_dat_o;
output wire [3:0] wb_s0_cellram_wb_sel_o;
output wire wb_s0_cellram_wb_stb_o;
output wire wb_s0_cellram_wb_cyc_o;
output wire wb_s0_cellram_wb_we_o;
input wire [31:0] wb_s0_cellram_wb_dat_i;
input wire wb_s0_cellram_wb_ack_i;
//output wire wb_m1_cpu_gnt;
//output wire wb_m0_vcache_gnt;
output reg [1:0] cellram_mst_sel;
//assign cellram_mst_sel[1] = wb_m0_vcache_cyc_i & wb_m0_vcache_stb_i
//& !(cellram_mst_sel[1] & (wb_s0_cellram_wb_ack_i | cellram_arb_reset))
// ;
//assign cellram_mst_sel[0] = !cellram_mst_sel[1] & wb_m1_cpu_cyc_i & wb_m1_cpu_stb_i
//& !(cellram_mst_sel[0] & (wb_s0_cellram_wb_ack_i | cellram_arb_reset))
// ;
reg [9:0] cellram_arb_timeout;
wire cellram_arb_reset;
//assign wb_m1_cpu_gnt = cellram_mst_sel[0];
//assign wb_m0_vcache_gnt = cellram_mst_sel[1];
always @(posedge wb_clk)
if (wb_rst)
cellram_mst_sel <= 0;
else begin
if (cellram_mst_sel==2'b00) begin
/* wait for new access from masters. vcache takes priority */
if (wb_m0_vcache_cyc_i & wb_m0_vcache_stb_i) //if (wbs_d_cellram_cyc_i & wbs_d_cellram_stb_i)
cellram_mst_sel[1] <= 1;
else if (wb_m1_cpu_cyc_i & wb_m1_cpu_stb_i) //else if (wbs_i_cellram_cyc_i & wbs_i_cellram_stb_i)
cellram_mst_sel[0] <= 1;
end
else begin
if (wb_s0_cellram_wb_ack_i) //| cellram_arb_reset) //TODO: reset
cellram_mst_sel <= 0;
end // else: !if(cellram_mst_sel==2'b00)
end // else: !if(wb_rst)
reg [3:0] cellram_rst_counter;
always @(posedge wb_clk or posedge wb_rst)
if (wb_rst)
cellram_rst_counter <= 4'hf;
else if (|cellram_rst_counter)
cellram_rst_counter <= cellram_rst_counter - 1;
assign wb_s0_cellram_wb_adr_o = cellram_mst_sel[0] ? wb_m1_cpu_adr_i :
wb_m0_vcache_adr_i;
assign wb_s0_cellram_wb_dat_o = cellram_mst_sel[0] ? wb_m1_cpu_dat_i :
wb_m0_vcache_dat_i;
assign wb_s0_cellram_wb_stb_o = (cellram_mst_sel[0] ? wb_m1_cpu_stb_i :
cellram_mst_sel[1] ? wb_m0_vcache_stb_i : 0) &
!(|cellram_rst_counter);
assign wb_s0_cellram_wb_cyc_o = cellram_mst_sel[0] ? wb_m1_cpu_cyc_i :
cellram_mst_sel[1] ? wb_m0_vcache_cyc_i : 0;
assign wb_s0_cellram_wb_we_o = cellram_mst_sel[0] ? wb_m1_cpu_we_i :
wb_m0_vcache_we_i;
assign wb_s0_cellram_wb_sel_o = cellram_mst_sel[0] ? wb_m1_cpu_sel_i :
wb_m0_vcache_sel_i;
assign wb_m1_cpu_dat_o = wb_s0_cellram_wb_dat_i;
assign wb_m0_vcache_dat_o = wb_s0_cellram_wb_dat_i;
assign wb_m1_cpu_ack_o = wb_s0_cellram_wb_ack_i & cellram_mst_sel[0];
assign wb_m0_vcache_ack_o = wb_s0_cellram_wb_ack_i & cellram_mst_sel[1];
assign wb_m1_cpu_err_o = cellram_arb_reset & cellram_mst_sel[0];
assign wb_m1_cpu_rty_o = 0;
assign wb_m0_vcache_err_o = cellram_arb_reset & cellram_mst_sel[1];
assign wb_m0_vcache_rty_o = 0;
always @(posedge wb_clk)
if (wb_rst)
cellram_arb_timeout <= 0;
else if (wb_s0_cellram_wb_ack_i)
cellram_arb_timeout <= 0;
else if (wb_s0_cellram_wb_stb_o & wb_s0_cellram_wb_cyc_o)
cellram_arb_timeout <= cellram_arb_timeout + 1;
assign cellram_arb_reset = (&cellram_arb_timeout);
endmodule
|
module aurora_64b66b_25p4G_gt_gtye4_common_wrapper (
input [0:0] GTYE4_COMMON_BGBYPASSB,
input [0:0] GTYE4_COMMON_BGMONITORENB,
input [0:0] GTYE4_COMMON_BGPDB,
input [4:0] GTYE4_COMMON_BGRCALOVRD,
input [0:0] GTYE4_COMMON_BGRCALOVRDENB,
input [15:0] GTYE4_COMMON_DRPADDR,
input [0:0] GTYE4_COMMON_DRPCLK,
input [15:0] GTYE4_COMMON_DRPDI,
input [0:0] GTYE4_COMMON_DRPEN,
input [0:0] GTYE4_COMMON_DRPWE,
input [0:0] GTYE4_COMMON_GTGREFCLK0,
input [0:0] GTYE4_COMMON_GTGREFCLK1,
input [0:0] GTYE4_COMMON_GTNORTHREFCLK00,
input [0:0] GTYE4_COMMON_GTNORTHREFCLK01,
input [0:0] GTYE4_COMMON_GTNORTHREFCLK10,
input [0:0] GTYE4_COMMON_GTNORTHREFCLK11,
input [0:0] GTYE4_COMMON_GTREFCLK00,
input [0:0] GTYE4_COMMON_GTREFCLK01,
input [0:0] GTYE4_COMMON_GTREFCLK10,
input [0:0] GTYE4_COMMON_GTREFCLK11,
input [0:0] GTYE4_COMMON_GTSOUTHREFCLK00,
input [0:0] GTYE4_COMMON_GTSOUTHREFCLK01,
input [0:0] GTYE4_COMMON_GTSOUTHREFCLK10,
input [0:0] GTYE4_COMMON_GTSOUTHREFCLK11,
input [2:0] GTYE4_COMMON_PCIERATEQPLL0,
input [2:0] GTYE4_COMMON_PCIERATEQPLL1,
input [7:0] GTYE4_COMMON_PMARSVD0,
input [7:0] GTYE4_COMMON_PMARSVD1,
input [0:0] GTYE4_COMMON_QPLL0CLKRSVD0,
input [0:0] GTYE4_COMMON_QPLL0CLKRSVD1,
input [7:0] GTYE4_COMMON_QPLL0FBDIV,
input [0:0] GTYE4_COMMON_QPLL0LOCKDETCLK,
input [0:0] GTYE4_COMMON_QPLL0LOCKEN,
input [0:0] GTYE4_COMMON_QPLL0PD,
input [2:0] GTYE4_COMMON_QPLL0REFCLKSEL,
input [0:0] GTYE4_COMMON_QPLL0RESET,
input [0:0] GTYE4_COMMON_QPLL1CLKRSVD0,
input [0:0] GTYE4_COMMON_QPLL1CLKRSVD1,
input [7:0] GTYE4_COMMON_QPLL1FBDIV,
input [0:0] GTYE4_COMMON_QPLL1LOCKDETCLK,
input [0:0] GTYE4_COMMON_QPLL1LOCKEN,
input [0:0] GTYE4_COMMON_QPLL1PD,
input [2:0] GTYE4_COMMON_QPLL1REFCLKSEL,
input [0:0] GTYE4_COMMON_QPLL1RESET,
input [7:0] GTYE4_COMMON_QPLLRSVD1,
input [4:0] GTYE4_COMMON_QPLLRSVD2,
input [4:0] GTYE4_COMMON_QPLLRSVD3,
input [7:0] GTYE4_COMMON_QPLLRSVD4,
input [0:0] GTYE4_COMMON_RCALENB,
input [24:0] GTYE4_COMMON_SDM0DATA,
input [0:0] GTYE4_COMMON_SDM0RESET,
input [0:0] GTYE4_COMMON_SDM0TOGGLE,
input [1:0] GTYE4_COMMON_SDM0WIDTH,
input [24:0] GTYE4_COMMON_SDM1DATA,
input [0:0] GTYE4_COMMON_SDM1RESET,
input [0:0] GTYE4_COMMON_SDM1TOGGLE,
input [1:0] GTYE4_COMMON_SDM1WIDTH,
input [0:0] GTYE4_COMMON_UBCFGSTREAMEN,
input [15:0] GTYE4_COMMON_UBDO,
input [0:0] GTYE4_COMMON_UBDRDY,
input [0:0] GTYE4_COMMON_UBENABLE,
input [1:0] GTYE4_COMMON_UBGPI,
input [1:0] GTYE4_COMMON_UBINTR,
input [0:0] GTYE4_COMMON_UBIOLMBRST,
input [0:0] GTYE4_COMMON_UBMBRST,
input [0:0] GTYE4_COMMON_UBMDMCAPTURE,
input [0:0] GTYE4_COMMON_UBMDMDBGRST,
input [0:0] GTYE4_COMMON_UBMDMDBGUPDATE,
input [3:0] GTYE4_COMMON_UBMDMREGEN,
input [0:0] GTYE4_COMMON_UBMDMSHIFT,
input [0:0] GTYE4_COMMON_UBMDMSYSRST,
input [0:0] GTYE4_COMMON_UBMDMTCK,
input [0:0] GTYE4_COMMON_UBMDMTDI,
output [15:0] GTYE4_COMMON_DRPDO,
output [0:0] GTYE4_COMMON_DRPRDY,
output [7:0] GTYE4_COMMON_PMARSVDOUT0,
output [7:0] GTYE4_COMMON_PMARSVDOUT1,
output [0:0] GTYE4_COMMON_QPLL0FBCLKLOST,
output [0:0] GTYE4_COMMON_QPLL0LOCK,
output [0:0] GTYE4_COMMON_QPLL0OUTCLK,
output [0:0] GTYE4_COMMON_QPLL0OUTREFCLK,
output [0:0] GTYE4_COMMON_QPLL0REFCLKLOST,
output [0:0] GTYE4_COMMON_QPLL1FBCLKLOST,
output [0:0] GTYE4_COMMON_QPLL1LOCK,
output [0:0] GTYE4_COMMON_QPLL1OUTCLK,
output [0:0] GTYE4_COMMON_QPLL1OUTREFCLK,
output [0:0] GTYE4_COMMON_QPLL1REFCLKLOST,
output [7:0] GTYE4_COMMON_QPLLDMONITOR0,
output [7:0] GTYE4_COMMON_QPLLDMONITOR1,
output [0:0] GTYE4_COMMON_REFCLKOUTMONITOR0,
output [0:0] GTYE4_COMMON_REFCLKOUTMONITOR1,
output [1:0] GTYE4_COMMON_RXRECCLK0SEL,
output [1:0] GTYE4_COMMON_RXRECCLK1SEL,
output [3:0] GTYE4_COMMON_SDM0FINALOUT,
output [14:0] GTYE4_COMMON_SDM0TESTDATA,
output [3:0] GTYE4_COMMON_SDM1FINALOUT,
output [14:0] GTYE4_COMMON_SDM1TESTDATA,
output [15:0] GTYE4_COMMON_UBDADDR,
output [0:0] GTYE4_COMMON_UBDEN,
output [15:0] GTYE4_COMMON_UBDI,
output [0:0] GTYE4_COMMON_UBDWE,
output [0:0] GTYE4_COMMON_UBMDMTDO,
output [0:0] GTYE4_COMMON_UBRSVDOUT,
output [0:0] GTYE4_COMMON_UBTXUART
);
gtwizard_ultrascale_v1_7_1_gtye4_common #(
.GTYE4_COMMON_AEN_QPLL0_FBDIV (1'b1),
.GTYE4_COMMON_AEN_QPLL1_FBDIV (1'b1),
.GTYE4_COMMON_AEN_SDM0TOGGLE (1'b0),
.GTYE4_COMMON_AEN_SDM1TOGGLE (1'b0),
.GTYE4_COMMON_A_SDM0TOGGLE (1'b0),
.GTYE4_COMMON_A_SDM1DATA_HIGH (9'b000000000),
.GTYE4_COMMON_A_SDM1DATA_LOW (16'b0000000000000000),
.GTYE4_COMMON_A_SDM1TOGGLE (1'b0),
.GTYE4_COMMON_BGBYPASSB_TIE_EN (1'b0),
.GTYE4_COMMON_BGBYPASSB_VAL (1'b1),
.GTYE4_COMMON_BGMONITORENB_TIE_EN (1'b0),
.GTYE4_COMMON_BGMONITORENB_VAL (1'b1),
.GTYE4_COMMON_BGPDB_TIE_EN (1'b0),
.GTYE4_COMMON_BGPDB_VAL (1'b1),
.GTYE4_COMMON_BGRCALOVRDENB_TIE_EN (1'b0),
.GTYE4_COMMON_BGRCALOVRDENB_VAL (1'b1),
.GTYE4_COMMON_BGRCALOVRD_TIE_EN (1'b0),
.GTYE4_COMMON_BGRCALOVRD_VAL (5'b10000),
.GTYE4_COMMON_BIAS_CFG0 (16'b0000000000000000),
.GTYE4_COMMON_BIAS_CFG1 (16'b0000000000000000),
.GTYE4_COMMON_BIAS_CFG2 (16'b0000010100100100),
.GTYE4_COMMON_BIAS_CFG3 (16'b0000000001000001),
.GTYE4_COMMON_BIAS_CFG4 (16'b0000000000010000),
.GTYE4_COMMON_BIAS_CFG_RSVD (16'b0000000000000000),
.GTYE4_COMMON_COMMON_CFG0 (16'b0000000000000000),
.GTYE4_COMMON_COMMON_CFG1 (16'b0000000000000000),
.GTYE4_COMMON_DRPADDR_TIE_EN (1'b0),
.GTYE4_COMMON_DRPADDR_VAL (16'b0000000000000000),
.GTYE4_COMMON_DRPCLK_TIE_EN (1'b0),
.GTYE4_COMMON_DRPCLK_VAL (1'b0),
.GTYE4_COMMON_DRPDI_TIE_EN (1'b0),
.GTYE4_COMMON_DRPDI_VAL (16'b0000000000000000),
.GTYE4_COMMON_DRPEN_TIE_EN (1'b0),
.GTYE4_COMMON_DRPEN_VAL (1'b0),
.GTYE4_COMMON_DRPWE_TIE_EN (1'b0),
.GTYE4_COMMON_DRPWE_VAL (1'b0),
.GTYE4_COMMON_GTGREFCLK0_TIE_EN (1'b0),
.GTYE4_COMMON_GTGREFCLK0_VAL (1'b0),
.GTYE4_COMMON_GTGREFCLK1_TIE_EN (1'b0),
.GTYE4_COMMON_GTGREFCLK1_VAL (1'b0),
.GTYE4_COMMON_GTNORTHREFCLK00_TIE_EN (1'b0),
.GTYE4_COMMON_GTNORTHREFCLK00_VAL (1'b0),
.GTYE4_COMMON_GTNORTHREFCLK01_TIE_EN (1'b0),
.GTYE4_COMMON_GTNORTHREFCLK01_VAL (1'b0),
.GTYE4_COMMON_GTNORTHREFCLK10_TIE_EN (1'b0),
.GTYE4_COMMON_GTNORTHREFCLK10_VAL (1'b0),
.GTYE4_COMMON_GTNORTHREFCLK11_TIE_EN (1'b0),
.GTYE4_COMMON_GTNORTHREFCLK11_VAL (1'b0),
.GTYE4_COMMON_GTREFCLK00_TIE_EN (1'b0),
.GTYE4_COMMON_GTREFCLK00_VAL (1'b0),
.GTYE4_COMMON_GTREFCLK01_TIE_EN (1'b0),
.GTYE4_COMMON_GTREFCLK01_VAL (1'b0),
.GTYE4_COMMON_GTREFCLK10_TIE_EN (1'b0),
.GTYE4_COMMON_GTREFCLK10_VAL (1'b0),
.GTYE4_COMMON_GTREFCLK11_TIE_EN (1'b0),
.GTYE4_COMMON_GTREFCLK11_VAL (1'b0),
.GTYE4_COMMON_GTSOUTHREFCLK00_TIE_EN (1'b0),
.GTYE4_COMMON_GTSOUTHREFCLK00_VAL (1'b0),
.GTYE4_COMMON_GTSOUTHREFCLK01_TIE_EN (1'b0),
.GTYE4_COMMON_GTSOUTHREFCLK01_VAL (1'b0),
.GTYE4_COMMON_GTSOUTHREFCLK10_TIE_EN (1'b0),
.GTYE4_COMMON_GTSOUTHREFCLK10_VAL (1'b0),
.GTYE4_COMMON_GTSOUTHREFCLK11_TIE_EN (1'b0),
.GTYE4_COMMON_GTSOUTHREFCLK11_VAL (1'b0),
.GTYE4_COMMON_PCIERATEQPLL0_TIE_EN (1'b0),
.GTYE4_COMMON_PCIERATEQPLL0_VAL (3'b000),
.GTYE4_COMMON_PCIERATEQPLL1_TIE_EN (1'b0),
.GTYE4_COMMON_PCIERATEQPLL1_VAL (3'b000),
.GTYE4_COMMON_PMARSVD0_TIE_EN (1'b0),
.GTYE4_COMMON_PMARSVD0_VAL (8'b00000000),
.GTYE4_COMMON_PMARSVD1_TIE_EN (1'b0),
.GTYE4_COMMON_PMARSVD1_VAL (8'b00000000),
.GTYE4_COMMON_POR_CFG (16'b0000000000000000),
.GTYE4_COMMON_PPF0_CFG (16'b0000100000000000),
.GTYE4_COMMON_PPF1_CFG (16'b0000011000000000),
.GTYE4_COMMON_QPLL0CLKOUT_RATE ("FULL"),
.GTYE4_COMMON_QPLL0CLKRSVD0_TIE_EN (1'b0),
.GTYE4_COMMON_QPLL0CLKRSVD0_VAL (1'b0),
.GTYE4_COMMON_QPLL0CLKRSVD1_TIE_EN (1'b0),
.GTYE4_COMMON_QPLL0CLKRSVD1_VAL (1'b0),
.GTYE4_COMMON_QPLL0FBDIV_TIE_EN (1'b0),
.GTYE4_COMMON_QPLL0FBDIV_VAL (8'b00000000),
.GTYE4_COMMON_QPLL0LOCKDETCLK_TIE_EN (1'b0),
.GTYE4_COMMON_QPLL0LOCKDETCLK_VAL (1'b0),
.GTYE4_COMMON_QPLL0LOCKEN_TIE_EN (1'b0),
.GTYE4_COMMON_QPLL0LOCKEN_VAL (1'b1),
.GTYE4_COMMON_QPLL0PD_TIE_EN (1'b0),
.GTYE4_COMMON_QPLL0PD_VAL (1'b0),
.GTYE4_COMMON_QPLL0REFCLKSEL_TIE_EN (1'b0),
.GTYE4_COMMON_QPLL0REFCLKSEL_VAL (3'b001),
.GTYE4_COMMON_QPLL0RESET_TIE_EN (1'b0),
.GTYE4_COMMON_QPLL0RESET_VAL (1'b0),
.GTYE4_COMMON_QPLL0_CFG0 (16'b0011001100011100),
.GTYE4_COMMON_QPLL0_CFG1 (16'b1101000000111000),
.GTYE4_COMMON_QPLL0_CFG1_G3 (16'b1101000000111000),
.GTYE4_COMMON_QPLL0_CFG2 (16'b0000111111000011),
.GTYE4_COMMON_QPLL0_CFG2_G3 (16'b0000111111000011),
.GTYE4_COMMON_QPLL0_CFG3 (16'b0000000100100000),
.GTYE4_COMMON_QPLL0_CFG4 (16'b0000000010000100),
.GTYE4_COMMON_QPLL0_CP (10'b0011111111),
.GTYE4_COMMON_QPLL0_CP_G3 (10'b0000001111),
.GTYE4_COMMON_QPLL0_FBDIV (127),
.GTYE4_COMMON_QPLL0_FBDIV_G3 (160),
.GTYE4_COMMON_QPLL0_INIT_CFG0 (16'b0000001010110010),
.GTYE4_COMMON_QPLL0_INIT_CFG1 (8'b00000000),
.GTYE4_COMMON_QPLL0_LOCK_CFG (16'b0010010111101000),
.GTYE4_COMMON_QPLL0_LOCK_CFG_G3 (16'b0010010111101000),
.GTYE4_COMMON_QPLL0_LPF (10'b1000011111),
.GTYE4_COMMON_QPLL0_LPF_G3 (10'b0111010101),
.GTYE4_COMMON_QPLL0_PCI_EN (1'b0),
.GTYE4_COMMON_QPLL0_RATE_SW_USE_DRP (1'b1),
.GTYE4_COMMON_QPLL0_REFCLK_DIV (1),
.GTYE4_COMMON_QPLL0_SDM_CFG0 (16'b0000000010000000),
.GTYE4_COMMON_QPLL0_SDM_CFG1 (16'b0000000000000000),
.GTYE4_COMMON_QPLL0_SDM_CFG2 (16'b0000000000000000),
.GTYE4_COMMON_QPLL1CLKOUT_RATE ("HALF"),
.GTYE4_COMMON_QPLL1CLKRSVD0_TIE_EN (1'b0),
.GTYE4_COMMON_QPLL1CLKRSVD0_VAL (1'b0),
.GTYE4_COMMON_QPLL1CLKRSVD1_TIE_EN (1'b0),
.GTYE4_COMMON_QPLL1CLKRSVD1_VAL (1'b0),
.GTYE4_COMMON_QPLL1FBDIV_TIE_EN (1'b0),
.GTYE4_COMMON_QPLL1FBDIV_VAL (8'b00000000),
.GTYE4_COMMON_QPLL1LOCKDETCLK_TIE_EN (1'b0),
.GTYE4_COMMON_QPLL1LOCKDETCLK_VAL (1'b0),
.GTYE4_COMMON_QPLL1LOCKEN_TIE_EN (1'b0),
.GTYE4_COMMON_QPLL1LOCKEN_VAL (1'b0),
.GTYE4_COMMON_QPLL1PD_TIE_EN (1'b0),
.GTYE4_COMMON_QPLL1PD_VAL (1'b1),
.GTYE4_COMMON_QPLL1REFCLKSEL_TIE_EN (1'b0),
.GTYE4_COMMON_QPLL1REFCLKSEL_VAL (3'b001),
.GTYE4_COMMON_QPLL1RESET_TIE_EN (1'b0),
.GTYE4_COMMON_QPLL1RESET_VAL (1'b1),
.GTYE4_COMMON_QPLL1_CFG0 (16'b0011001100011100),
.GTYE4_COMMON_QPLL1_CFG1 (16'b1101000000111000),
.GTYE4_COMMON_QPLL1_CFG1_G3 (16'b1101000000111000),
.GTYE4_COMMON_QPLL1_CFG2 (16'b0000111111000011),
.GTYE4_COMMON_QPLL1_CFG2_G3 (16'b0000111111000011),
.GTYE4_COMMON_QPLL1_CFG3 (16'b0000000100100000),
.GTYE4_COMMON_QPLL1_CFG4 (16'b0000000000000010),
.GTYE4_COMMON_QPLL1_CP (10'b0011111111),
.GTYE4_COMMON_QPLL1_CP_G3 (10'b0001111111),
.GTYE4_COMMON_QPLL1_FBDIV (66),
.GTYE4_COMMON_QPLL1_FBDIV_G3 (80),
.GTYE4_COMMON_QPLL1_INIT_CFG0 (16'b0000001010110010),
.GTYE4_COMMON_QPLL1_INIT_CFG1 (8'b00000000),
.GTYE4_COMMON_QPLL1_LOCK_CFG (16'b0010010111101000),
.GTYE4_COMMON_QPLL1_LOCK_CFG_G3 (16'b0010010111101000),
.GTYE4_COMMON_QPLL1_LPF (10'b1000011111),
.GTYE4_COMMON_QPLL1_LPF_G3 (10'b0111010100),
.GTYE4_COMMON_QPLL1_PCI_EN (1'b0),
.GTYE4_COMMON_QPLL1_RATE_SW_USE_DRP (1'b1),
.GTYE4_COMMON_QPLL1_REFCLK_DIV (1),
.GTYE4_COMMON_QPLL1_SDM_CFG0 (16'b0000000010000000),
.GTYE4_COMMON_QPLL1_SDM_CFG1 (16'b0000000000000000),
.GTYE4_COMMON_QPLL1_SDM_CFG2 (16'b0000000000000000),
.GTYE4_COMMON_QPLLRSVD1_TIE_EN (1'b0),
.GTYE4_COMMON_QPLLRSVD1_VAL (8'b00000000),
.GTYE4_COMMON_QPLLRSVD2_TIE_EN (1'b0),
.GTYE4_COMMON_QPLLRSVD2_VAL (5'b00000),
.GTYE4_COMMON_QPLLRSVD3_TIE_EN (1'b0),
.GTYE4_COMMON_QPLLRSVD3_VAL (5'b00000),
.GTYE4_COMMON_QPLLRSVD4_TIE_EN (1'b0),
.GTYE4_COMMON_QPLLRSVD4_VAL (8'b00000000),
.GTYE4_COMMON_RCALENB_TIE_EN (1'b0),
.GTYE4_COMMON_RCALENB_VAL (1'b1),
.GTYE4_COMMON_RSVD_ATTR0 (16'b0000000000000000),
.GTYE4_COMMON_RSVD_ATTR1 (16'b0000000000000000),
.GTYE4_COMMON_RSVD_ATTR2 (16'b0000000000000000),
.GTYE4_COMMON_RSVD_ATTR3 (16'b0000000000000000),
.GTYE4_COMMON_RXRECCLKOUT0_SEL (2'b00),
.GTYE4_COMMON_RXRECCLKOUT1_SEL (2'b00),
.GTYE4_COMMON_SARC_ENB (1'b0),
.GTYE4_COMMON_SARC_SEL (1'b0),
.GTYE4_COMMON_SDM0DATA_TIE_EN (1'b0),
.GTYE4_COMMON_SDM0DATA_VAL (25'b0000000000000000000000000),
.GTYE4_COMMON_SDM0INITSEED0_0 (16'b0000000100010001),
.GTYE4_COMMON_SDM0INITSEED0_1 (9'b000010001),
.GTYE4_COMMON_SDM0RESET_TIE_EN (1'b0),
.GTYE4_COMMON_SDM0RESET_VAL (1'b0),
.GTYE4_COMMON_SDM0TOGGLE_TIE_EN (1'b0),
.GTYE4_COMMON_SDM0TOGGLE_VAL (1'b0),
.GTYE4_COMMON_SDM0WIDTH_TIE_EN (1'b0),
.GTYE4_COMMON_SDM0WIDTH_VAL (2'b00),
.GTYE4_COMMON_SDM1DATA_TIE_EN (1'b0),
.GTYE4_COMMON_SDM1DATA_VAL (25'b0000000000000000000000000),
.GTYE4_COMMON_SDM1INITSEED0_0 (16'b0000000100010001),
.GTYE4_COMMON_SDM1INITSEED0_1 (9'b000010001),
.GTYE4_COMMON_SDM1RESET_TIE_EN (1'b0),
.GTYE4_COMMON_SDM1RESET_VAL (1'b0),
.GTYE4_COMMON_SDM1TOGGLE_TIE_EN (1'b0),
.GTYE4_COMMON_SDM1TOGGLE_VAL (1'b0),
.GTYE4_COMMON_SDM1WIDTH_TIE_EN (1'b0),
.GTYE4_COMMON_SDM1WIDTH_VAL (2'b00),
.GTYE4_COMMON_SIM_DEVICE ("ULTRASCALE_PLUS"),
.GTYE4_COMMON_SIM_MODE ("FAST"),
.GTYE4_COMMON_SIM_RESET_SPEEDUP ("TRUE"),
.GTYE4_COMMON_UBCFGSTREAMEN_TIE_EN (1'b0),
.GTYE4_COMMON_UBCFGSTREAMEN_VAL (1'b0),
.GTYE4_COMMON_UBDO_TIE_EN (1'b0),
.GTYE4_COMMON_UBDO_VAL (16'b0000000000000000),
.GTYE4_COMMON_UBDRDY_TIE_EN (1'b0),
.GTYE4_COMMON_UBDRDY_VAL (1'b0),
.GTYE4_COMMON_UBENABLE_TIE_EN (1'b0),
.GTYE4_COMMON_UBENABLE_VAL (1'b0),
.GTYE4_COMMON_UBGPI_TIE_EN (1'b0),
.GTYE4_COMMON_UBGPI_VAL (2'b00),
.GTYE4_COMMON_UBINTR_TIE_EN (1'b0),
.GTYE4_COMMON_UBINTR_VAL (2'b00),
.GTYE4_COMMON_UBIOLMBRST_TIE_EN (1'b0),
.GTYE4_COMMON_UBIOLMBRST_VAL (1'b0),
.GTYE4_COMMON_UBMBRST_TIE_EN (1'b0),
.GTYE4_COMMON_UBMBRST_VAL (1'b0),
.GTYE4_COMMON_UBMDMCAPTURE_TIE_EN (1'b0),
.GTYE4_COMMON_UBMDMCAPTURE_VAL (1'b0),
.GTYE4_COMMON_UBMDMDBGRST_TIE_EN (1'b0),
.GTYE4_COMMON_UBMDMDBGRST_VAL (1'b0),
.GTYE4_COMMON_UBMDMDBGUPDATE_TIE_EN (1'b0),
.GTYE4_COMMON_UBMDMDBGUPDATE_VAL (1'b0),
.GTYE4_COMMON_UBMDMREGEN_TIE_EN (1'b0),
.GTYE4_COMMON_UBMDMREGEN_VAL (4'b0000),
.GTYE4_COMMON_UBMDMSHIFT_TIE_EN (1'b0),
.GTYE4_COMMON_UBMDMSHIFT_VAL (1'b0),
.GTYE4_COMMON_UBMDMSYSRST_TIE_EN (1'b0),
.GTYE4_COMMON_UBMDMSYSRST_VAL (1'b0),
.GTYE4_COMMON_UBMDMTCK_TIE_EN (1'b0),
.GTYE4_COMMON_UBMDMTCK_VAL (1'b0),
.GTYE4_COMMON_UBMDMTDI_TIE_EN (1'b0),
.GTYE4_COMMON_UBMDMTDI_VAL (1'b0),
.GTYE4_COMMON_UB_CFG0 (16'b0000000000000000),
.GTYE4_COMMON_UB_CFG1 (16'b0000000000000000),
.GTYE4_COMMON_UB_CFG2 (16'b0000000000000000),
.GTYE4_COMMON_UB_CFG3 (16'b0000000000000000),
.GTYE4_COMMON_UB_CFG4 (16'b0000000000000000),
.GTYE4_COMMON_UB_CFG5 (16'b0000010000000000),
.GTYE4_COMMON_UB_CFG6 (16'b0000000000000000)
) common_inst (
// inputs
.GTYE4_COMMON_BGBYPASSB (GTYE4_COMMON_BGBYPASSB),
.GTYE4_COMMON_BGMONITORENB (GTYE4_COMMON_BGMONITORENB),
.GTYE4_COMMON_BGPDB (GTYE4_COMMON_BGPDB),
.GTYE4_COMMON_BGRCALOVRD (GTYE4_COMMON_BGRCALOVRD),
.GTYE4_COMMON_BGRCALOVRDENB (GTYE4_COMMON_BGRCALOVRDENB),
.GTYE4_COMMON_DRPADDR (GTYE4_COMMON_DRPADDR),
.GTYE4_COMMON_DRPCLK (GTYE4_COMMON_DRPCLK),
.GTYE4_COMMON_DRPDI (GTYE4_COMMON_DRPDI),
.GTYE4_COMMON_DRPEN (GTYE4_COMMON_DRPEN),
.GTYE4_COMMON_DRPWE (GTYE4_COMMON_DRPWE),
.GTYE4_COMMON_GTGREFCLK0 (GTYE4_COMMON_GTGREFCLK0),
.GTYE4_COMMON_GTGREFCLK1 (GTYE4_COMMON_GTGREFCLK1),
.GTYE4_COMMON_GTNORTHREFCLK00 (GTYE4_COMMON_GTNORTHREFCLK00),
.GTYE4_COMMON_GTNORTHREFCLK01 (GTYE4_COMMON_GTNORTHREFCLK01),
.GTYE4_COMMON_GTNORTHREFCLK10 (GTYE4_COMMON_GTNORTHREFCLK10),
.GTYE4_COMMON_GTNORTHREFCLK11 (GTYE4_COMMON_GTNORTHREFCLK11),
.GTYE4_COMMON_GTREFCLK00 (GTYE4_COMMON_GTREFCLK00),
.GTYE4_COMMON_GTREFCLK01 (GTYE4_COMMON_GTREFCLK01),
.GTYE4_COMMON_GTREFCLK10 (GTYE4_COMMON_GTREFCLK10),
.GTYE4_COMMON_GTREFCLK11 (GTYE4_COMMON_GTREFCLK11),
.GTYE4_COMMON_GTSOUTHREFCLK00 (GTYE4_COMMON_GTSOUTHREFCLK00),
.GTYE4_COMMON_GTSOUTHREFCLK01 (GTYE4_COMMON_GTSOUTHREFCLK01),
.GTYE4_COMMON_GTSOUTHREFCLK10 (GTYE4_COMMON_GTSOUTHREFCLK10),
.GTYE4_COMMON_GTSOUTHREFCLK11 (GTYE4_COMMON_GTSOUTHREFCLK11),
.GTYE4_COMMON_PCIERATEQPLL0 (GTYE4_COMMON_PCIERATEQPLL0),
.GTYE4_COMMON_PCIERATEQPLL1 (GTYE4_COMMON_PCIERATEQPLL1),
.GTYE4_COMMON_PMARSVD0 (GTYE4_COMMON_PMARSVD0),
.GTYE4_COMMON_PMARSVD1 (GTYE4_COMMON_PMARSVD1),
.GTYE4_COMMON_QPLL0CLKRSVD0 (GTYE4_COMMON_QPLL0CLKRSVD0),
.GTYE4_COMMON_QPLL0CLKRSVD1 (GTYE4_COMMON_QPLL0CLKRSVD1),
.GTYE4_COMMON_QPLL0FBDIV (GTYE4_COMMON_QPLL0FBDIV),
.GTYE4_COMMON_QPLL0LOCKDETCLK (GTYE4_COMMON_QPLL0LOCKDETCLK),
.GTYE4_COMMON_QPLL0LOCKEN (GTYE4_COMMON_QPLL0LOCKEN),
.GTYE4_COMMON_QPLL0PD (GTYE4_COMMON_QPLL0PD),
.GTYE4_COMMON_QPLL0REFCLKSEL (GTYE4_COMMON_QPLL0REFCLKSEL),
.GTYE4_COMMON_QPLL0RESET (GTYE4_COMMON_QPLL0RESET),
.GTYE4_COMMON_QPLL1CLKRSVD0 (GTYE4_COMMON_QPLL1CLKRSVD0),
.GTYE4_COMMON_QPLL1CLKRSVD1 (GTYE4_COMMON_QPLL1CLKRSVD1),
.GTYE4_COMMON_QPLL1FBDIV (GTYE4_COMMON_QPLL1FBDIV),
.GTYE4_COMMON_QPLL1LOCKDETCLK (GTYE4_COMMON_QPLL1LOCKDETCLK),
.GTYE4_COMMON_QPLL1LOCKEN (GTYE4_COMMON_QPLL1LOCKEN),
.GTYE4_COMMON_QPLL1PD (GTYE4_COMMON_QPLL1PD),
.GTYE4_COMMON_QPLL1REFCLKSEL (GTYE4_COMMON_QPLL1REFCLKSEL),
.GTYE4_COMMON_QPLL1RESET (GTYE4_COMMON_QPLL1RESET),
.GTYE4_COMMON_QPLLRSVD1 (GTYE4_COMMON_QPLLRSVD1),
.GTYE4_COMMON_QPLLRSVD2 (GTYE4_COMMON_QPLLRSVD2),
.GTYE4_COMMON_QPLLRSVD3 (GTYE4_COMMON_QPLLRSVD3),
.GTYE4_COMMON_QPLLRSVD4 (GTYE4_COMMON_QPLLRSVD4),
.GTYE4_COMMON_RCALENB (GTYE4_COMMON_RCALENB),
.GTYE4_COMMON_SDM0DATA (GTYE4_COMMON_SDM0DATA),
.GTYE4_COMMON_SDM0RESET (GTYE4_COMMON_SDM0RESET),
.GTYE4_COMMON_SDM0TOGGLE (GTYE4_COMMON_SDM0TOGGLE),
.GTYE4_COMMON_SDM0WIDTH (GTYE4_COMMON_SDM0WIDTH),
.GTYE4_COMMON_SDM1DATA (GTYE4_COMMON_SDM1DATA),
.GTYE4_COMMON_SDM1RESET (GTYE4_COMMON_SDM1RESET),
.GTYE4_COMMON_SDM1TOGGLE (GTYE4_COMMON_SDM1TOGGLE),
.GTYE4_COMMON_SDM1WIDTH (GTYE4_COMMON_SDM1WIDTH),
.GTYE4_COMMON_UBCFGSTREAMEN (GTYE4_COMMON_UBCFGSTREAMEN),
.GTYE4_COMMON_UBDO (GTYE4_COMMON_UBDO),
.GTYE4_COMMON_UBDRDY (GTYE4_COMMON_UBDRDY),
.GTYE4_COMMON_UBENABLE (GTYE4_COMMON_UBENABLE),
.GTYE4_COMMON_UBGPI (GTYE4_COMMON_UBGPI),
.GTYE4_COMMON_UBINTR (GTYE4_COMMON_UBINTR),
.GTYE4_COMMON_UBIOLMBRST (GTYE4_COMMON_UBIOLMBRST),
.GTYE4_COMMON_UBMBRST (GTYE4_COMMON_UBMBRST),
.GTYE4_COMMON_UBMDMCAPTURE (GTYE4_COMMON_UBMDMCAPTURE),
.GTYE4_COMMON_UBMDMDBGRST (GTYE4_COMMON_UBMDMDBGRST),
.GTYE4_COMMON_UBMDMDBGUPDATE (GTYE4_COMMON_UBMDMDBGUPDATE),
.GTYE4_COMMON_UBMDMREGEN (GTYE4_COMMON_UBMDMREGEN),
.GTYE4_COMMON_UBMDMSHIFT (GTYE4_COMMON_UBMDMSHIFT),
.GTYE4_COMMON_UBMDMSYSRST (GTYE4_COMMON_UBMDMSYSRST),
.GTYE4_COMMON_UBMDMTCK (GTYE4_COMMON_UBMDMTCK),
.GTYE4_COMMON_UBMDMTDI (GTYE4_COMMON_UBMDMTDI),
// outputs
.GTYE4_COMMON_DRPDO (GTYE4_COMMON_DRPDO),
.GTYE4_COMMON_DRPRDY (GTYE4_COMMON_DRPRDY),
.GTYE4_COMMON_PMARSVDOUT0 (GTYE4_COMMON_PMARSVDOUT0),
.GTYE4_COMMON_PMARSVDOUT1 (GTYE4_COMMON_PMARSVDOUT1),
.GTYE4_COMMON_QPLL0FBCLKLOST (GTYE4_COMMON_QPLL0FBCLKLOST),
.GTYE4_COMMON_QPLL0LOCK (GTYE4_COMMON_QPLL0LOCK),
.GTYE4_COMMON_QPLL0OUTCLK (GTYE4_COMMON_QPLL0OUTCLK),
.GTYE4_COMMON_QPLL0OUTREFCLK (GTYE4_COMMON_QPLL0OUTREFCLK),
.GTYE4_COMMON_QPLL0REFCLKLOST (GTYE4_COMMON_QPLL0REFCLKLOST),
.GTYE4_COMMON_QPLL1FBCLKLOST (GTYE4_COMMON_QPLL1FBCLKLOST),
.GTYE4_COMMON_QPLL1LOCK (GTYE4_COMMON_QPLL1LOCK),
.GTYE4_COMMON_QPLL1OUTCLK (GTYE4_COMMON_QPLL1OUTCLK),
.GTYE4_COMMON_QPLL1OUTREFCLK (GTYE4_COMMON_QPLL1OUTREFCLK),
.GTYE4_COMMON_QPLL1REFCLKLOST (GTYE4_COMMON_QPLL1REFCLKLOST),
.GTYE4_COMMON_QPLLDMONITOR0 (GTYE4_COMMON_QPLLDMONITOR0),
.GTYE4_COMMON_QPLLDMONITOR1 (GTYE4_COMMON_QPLLDMONITOR1),
.GTYE4_COMMON_REFCLKOUTMONITOR0 (GTYE4_COMMON_REFCLKOUTMONITOR0),
.GTYE4_COMMON_REFCLKOUTMONITOR1 (GTYE4_COMMON_REFCLKOUTMONITOR1),
.GTYE4_COMMON_RXRECCLK0SEL (GTYE4_COMMON_RXRECCLK0SEL),
.GTYE4_COMMON_RXRECCLK1SEL (GTYE4_COMMON_RXRECCLK1SEL),
.GTYE4_COMMON_SDM0FINALOUT (GTYE4_COMMON_SDM0FINALOUT),
.GTYE4_COMMON_SDM0TESTDATA (GTYE4_COMMON_SDM0TESTDATA),
.GTYE4_COMMON_SDM1FINALOUT (GTYE4_COMMON_SDM1FINALOUT),
.GTYE4_COMMON_SDM1TESTDATA (GTYE4_COMMON_SDM1TESTDATA),
.GTYE4_COMMON_UBDADDR (GTYE4_COMMON_UBDADDR),
.GTYE4_COMMON_UBDEN (GTYE4_COMMON_UBDEN),
.GTYE4_COMMON_UBDI (GTYE4_COMMON_UBDI),
.GTYE4_COMMON_UBDWE (GTYE4_COMMON_UBDWE),
.GTYE4_COMMON_UBMDMTDO (GTYE4_COMMON_UBMDMTDO),
.GTYE4_COMMON_UBRSVDOUT (GTYE4_COMMON_UBRSVDOUT),
.GTYE4_COMMON_UBTXUART (GTYE4_COMMON_UBTXUART)
);
endmodule
|
module sky130_fd_sc_ls__o211ai (
Y ,
A1 ,
A2 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire or0_out ;
wire nand0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
or or0 (or0_out , A2, A1 );
nand nand0 (nand0_out_Y , C1, or0_out, B1 );
sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nand0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
|
module sky130_fd_sc_ls__dlygate4sd1 (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire buf0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X , A );
sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, buf0_out_X, VPWR, VGND);
buf buf1 (X , pwrgood_pp0_out_X );
endmodule
|
module mgtTop # // ROCKETIO_WRAPPER_TILE_top #
(
parameter EXAMPLE_CONFIG_INDEPENDENT_LANES = 1,//configuration for frame gen and check
parameter EXAMPLE_LANE_WITH_START_CHAR = 0, // specifies lane with unique start frame char
parameter EXAMPLE_WORDS_IN_BRAM = 512, // specifies amount of data in BRAM
parameter EXAMPLE_SIM_GTRESET_SPEEDUP = "TRUE", // simulation setting for GT SecureIP model
parameter EXAMPLE_USE_CHIPSCOPE = 0 // Set to 1 to use Chipscope to drive resets
)
(
input wire Q0_CLK0_GTREFCLK_PAD_N_IN,
input wire Q0_CLK0_GTREFCLK_PAD_P_IN,
input wire Q0_CLK1_GTREFCLK_PAD_N_IN,
input wire Q0_CLK1_GTREFCLK_PAD_P_IN,
input wire Q1_CLK0_GTREFCLK_PAD_N_IN,
input wire Q1_CLK0_GTREFCLK_PAD_P_IN,
input wire Q1_CLK1_GTREFCLK_PAD_N_IN,
input wire Q1_CLK1_GTREFCLK_PAD_P_IN,
input wire SYSCLK_IN,
input wire GTTXRESET_IN,
input wire GTRXRESET_IN,
output wire TRACK_DATA_OUT,
input wire [7:0] RXN_IN,
input wire [7:0] RXP_IN,
output wire [7:0] TXN_OUT,
output wire [7:0] TXP_OUT,
// Wishbone Interface
input wire wb_clk,
input wire wb_reset,
input wire wb_stb_i,
output reg [31:0] wb_dat_o,
input wire [31:0] wb_dat_i,
output reg wb_ack_o,
input wire [31:0] wb_adr_i,
input wire wb_we_i,
input wire wb_cyc_i,
input wire [3:0] wb_sel_i,
output wire wb_err_o,
output reg wb_rty_o
);
//************************** Register Declarations ****************************
reg gt0_txuserrdy_r;
reg gt0_txresetdone_r;
reg gt0_txresetdone_r2;
reg gt0_rxuserrdy_r;
reg gt0_rxresetdone_r;
reg gt0_rxresetdone_r2;
reg gt0_rxresetdone_r3;
reg gt1_txuserrdy_r;
reg gt1_txresetdone_r;
reg gt1_txresetdone_r2;
reg gt1_rxuserrdy_r;
reg gt1_rxresetdone_r;
reg gt1_rxresetdone_r2;
reg gt1_rxresetdone_r3;
reg gt2_txuserrdy_r;
reg gt2_txresetdone_r;
reg gt2_txresetdone_r2;
reg gt2_rxuserrdy_r;
reg gt2_rxresetdone_r;
reg gt2_rxresetdone_r2;
reg gt2_rxresetdone_r3;
reg gt3_txuserrdy_r;
reg gt3_txresetdone_r;
reg gt3_txresetdone_r2;
reg gt3_rxuserrdy_r;
reg gt3_rxresetdone_r;
reg gt3_rxresetdone_r2;
reg gt3_rxresetdone_r3;
reg gt4_txuserrdy_r;
reg gt4_txresetdone_r;
reg gt4_txresetdone_r2;
reg gt4_rxuserrdy_r;
reg gt4_rxresetdone_r;
reg gt4_rxresetdone_r2;
reg gt4_rxresetdone_r3;
reg gt5_txuserrdy_r;
reg gt5_txresetdone_r;
reg gt5_txresetdone_r2;
reg gt5_rxuserrdy_r;
reg gt5_rxresetdone_r;
reg gt5_rxresetdone_r2;
reg gt5_rxresetdone_r3;
reg gt6_txuserrdy_r;
reg gt6_txresetdone_r;
reg gt6_txresetdone_r2;
reg gt6_rxuserrdy_r;
reg gt6_rxresetdone_r;
reg gt6_rxresetdone_r2;
reg gt6_rxresetdone_r3;
reg gt7_txuserrdy_r;
reg gt7_txresetdone_r;
reg gt7_txresetdone_r2;
reg gt7_rxuserrdy_r;
reg gt7_rxresetdone_r;
reg gt7_rxresetdone_r2;
reg gt7_rxresetdone_r3;
//**************************** Wire Declarations ******************************//
//------------------------ GT Wrapper Wires ------------------------------
//________________________________________________________________________
//________________________________________________________________________
//GT0 (X0Y0)
//------------------------------ Channel PLL -------------------------------
wire gt0_cpllfbclklost_i;
wire gt0_cplllock_i;
wire gt0_cpllrefclklost_i;
wire gt0_cpllreset_i;
//----------------------------- Eye Scan Ports -----------------------------
wire gt0_eyescandataerror_i;
//---------------------- Loopback and Powerdown Ports ----------------------
wire [2:0] gt0_loopback_i;
wire [1:0] gt0_rxpd_i;
wire [1:0] gt0_txpd_i;
//----------------------------- Receive Ports ------------------------------
wire gt0_rxuserrdy_i;
//----------------- Receive Ports - Clock Correction Ports -----------------
wire [1:0] gt0_rxclkcorcnt_i;
//------------- Receive Ports - Comma Detection and Alignment --------------
wire gt0_rxbyteisaligned_i;
wire gt0_rxbyterealign_i;
wire gt0_rxcommadet_i;
wire gt0_rxslide_i;
//----------------- Receive Ports - RX Data Path interface -----------------
wire gt0_gtrxreset_i;
wire [15:0] gt0_rxdata_i;
wire gt0_rxoutclk_i;
wire gt0_rxpcsreset_i;
//----- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
wire gt0_gtxrxn_i;
wire gt0_gtxrxp_i;
wire gt0_rxcdrlock_i;
wire gt0_rxelecidle_i;
//------ Receive Ports - RX Elastic Buffer and Phase Alignment Ports -------
wire gt0_rxbufreset_i;
wire [2:0] gt0_rxbufstatus_i;
//---------------------- Receive Ports - RX PLL Ports ----------------------
wire gt0_rxresetdone_i;
//------------ Receive Ports - RX Pipe Control for PCI Express -------------
wire gt0_rxvalid_i;
//----------------------------- Transmit Ports -----------------------------
wire gt0_txprecursorinv_i;
wire gt0_txuserrdy_i;
//---------------- Transmit Ports - TX Data Path interface -----------------
wire gt0_gttxreset_i;
wire [15:0] gt0_txdata_i;
wire gt0_txoutclk_i;
wire gt0_txoutclkfabric_i;
wire gt0_txoutclkpcs_i;
wire gt0_txpcsreset_i;
//-------------- Transmit Ports - TX Driver and OOB signaling --------------
wire gt0_gtxtxn_i;
wire gt0_gtxtxp_i;
//--------- Transmit Ports - TX Elastic Buffer and Phase Alignment ---------
wire [1:0] gt0_txbufstatus_i;
//--------------------- Transmit Ports - TX PLL Ports ----------------------
wire gt0_txresetdone_i;
//________________________________________________________________________
//________________________________________________________________________
//GT1 (X0Y1)
//------------------------------ Channel PLL -------------------------------
wire gt1_cpllfbclklost_i;
wire gt1_cplllock_i;
wire gt1_cpllrefclklost_i;
wire gt1_cpllreset_i;
//----------------------------- Eye Scan Ports -----------------------------
wire gt1_eyescandataerror_i;
//---------------------- Loopback and Powerdown Ports ----------------------
wire [2:0] gt1_loopback_i;
wire [1:0] gt1_rxpd_i;
wire [1:0] gt1_txpd_i;
//----------------------------- Receive Ports ------------------------------
wire gt1_rxuserrdy_i;
//----------------- Receive Ports - Clock Correction Ports -----------------
wire [1:0] gt1_rxclkcorcnt_i;
//------------- Receive Ports - Comma Detection and Alignment --------------
wire gt1_rxbyteisaligned_i;
wire gt1_rxbyterealign_i;
wire gt1_rxcommadet_i;
wire gt1_rxslide_i;
//----------------- Receive Ports - RX Data Path interface -----------------
wire gt1_gtrxreset_i;
wire [15:0] gt1_rxdata_i;
wire gt1_rxoutclk_i;
wire gt1_rxpcsreset_i;
//----- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
wire gt1_gtxrxn_i;
wire gt1_gtxrxp_i;
wire gt1_rxcdrlock_i;
wire gt1_rxelecidle_i;
//------ Receive Ports - RX Elastic Buffer and Phase Alignment Ports -------
wire gt1_rxbufreset_i;
wire [2:0] gt1_rxbufstatus_i;
//---------------------- Receive Ports - RX PLL Ports ----------------------
wire gt1_rxresetdone_i;
//------------ Receive Ports - RX Pipe Control for PCI Express -------------
wire gt1_rxvalid_i;
//----------------------------- Transmit Ports -----------------------------
wire gt1_txprecursorinv_i;
wire gt1_txuserrdy_i;
//---------------- Transmit Ports - TX Data Path interface -----------------
wire gt1_gttxreset_i;
wire [15:0] gt1_txdata_i;
wire gt1_txoutclk_i;
wire gt1_txoutclkfabric_i;
wire gt1_txoutclkpcs_i;
wire gt1_txpcsreset_i;
//-------------- Transmit Ports - TX Driver and OOB signaling --------------
wire gt1_gtxtxn_i;
wire gt1_gtxtxp_i;
//--------- Transmit Ports - TX Elastic Buffer and Phase Alignment ---------
wire [1:0] gt1_txbufstatus_i;
//--------------------- Transmit Ports - TX PLL Ports ----------------------
wire gt1_txresetdone_i;
//________________________________________________________________________
//________________________________________________________________________
//GT2 (X0Y2)
//------------------------------ Channel PLL -------------------------------
wire gt2_cpllfbclklost_i;
wire gt2_cplllock_i;
wire gt2_cpllrefclklost_i;
wire gt2_cpllreset_i;
//----------------------------- Eye Scan Ports -----------------------------
wire gt2_eyescandataerror_i;
//---------------------- Loopback and Powerdown Ports ----------------------
wire [2:0] gt2_loopback_i;
wire [1:0] gt2_rxpd_i;
wire [1:0] gt2_txpd_i;
//----------------------------- Receive Ports ------------------------------
wire gt2_rxuserrdy_i;
//----------------- Receive Ports - Clock Correction Ports -----------------
wire [1:0] gt2_rxclkcorcnt_i;
//------------- Receive Ports - Comma Detection and Alignment --------------
wire gt2_rxbyteisaligned_i;
wire gt2_rxbyterealign_i;
wire gt2_rxcommadet_i;
wire gt2_rxslide_i;
//----------------- Receive Ports - RX Data Path interface -----------------
wire gt2_gtrxreset_i;
wire [15:0] gt2_rxdata_i;
wire gt2_rxoutclk_i;
wire gt2_rxpcsreset_i;
//----- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
wire gt2_gtxrxn_i;
wire gt2_gtxrxp_i;
wire gt2_rxcdrlock_i;
wire gt2_rxelecidle_i;
//------ Receive Ports - RX Elastic Buffer and Phase Alignment Ports -------
wire gt2_rxbufreset_i;
wire [2:0] gt2_rxbufstatus_i;
//---------------------- Receive Ports - RX PLL Ports ----------------------
wire gt2_rxresetdone_i;
//------------ Receive Ports - RX Pipe Control for PCI Express -------------
wire gt2_rxvalid_i;
//----------------------------- Transmit Ports -----------------------------
wire gt2_txprecursorinv_i;
wire gt2_txuserrdy_i;
//---------------- Transmit Ports - TX Data Path interface -----------------
wire gt2_gttxreset_i;
wire [15:0] gt2_txdata_i;
wire gt2_txoutclk_i;
wire gt2_txoutclkfabric_i;
wire gt2_txoutclkpcs_i;
wire gt2_txpcsreset_i;
//-------------- Transmit Ports - TX Driver and OOB signaling --------------
wire gt2_gtxtxn_i;
wire gt2_gtxtxp_i;
//--------- Transmit Ports - TX Elastic Buffer and Phase Alignment ---------
wire [1:0] gt2_txbufstatus_i;
//--------------------- Transmit Ports - TX PLL Ports ----------------------
wire gt2_txresetdone_i;
//________________________________________________________________________
//________________________________________________________________________
//GT3 (X0Y3)
//------------------------------ Channel PLL -------------------------------
wire gt3_cpllfbclklost_i;
wire gt3_cplllock_i;
wire gt3_cpllrefclklost_i;
wire gt3_cpllreset_i;
//----------------------------- Eye Scan Ports -----------------------------
wire gt3_eyescandataerror_i;
//---------------------- Loopback and Powerdown Ports ----------------------
wire [2:0] gt3_loopback_i;
wire [1:0] gt3_rxpd_i;
wire [1:0] gt3_txpd_i;
//----------------------------- Receive Ports ------------------------------
wire gt3_rxuserrdy_i;
//----------------- Receive Ports - Clock Correction Ports -----------------
wire [1:0] gt3_rxclkcorcnt_i;
//------------- Receive Ports - Comma Detection and Alignment --------------
wire gt3_rxbyteisaligned_i;
wire gt3_rxbyterealign_i;
wire gt3_rxcommadet_i;
wire gt3_rxslide_i;
//----------------- Receive Ports - RX Data Path interface -----------------
wire gt3_gtrxreset_i;
wire [15:0] gt3_rxdata_i;
wire gt3_rxoutclk_i;
wire gt3_rxpcsreset_i;
//----- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
wire gt3_gtxrxn_i;
wire gt3_gtxrxp_i;
wire gt3_rxcdrlock_i;
wire gt3_rxelecidle_i;
//------ Receive Ports - RX Elastic Buffer and Phase Alignment Ports -------
wire gt3_rxbufreset_i;
wire [2:0] gt3_rxbufstatus_i;
//---------------------- Receive Ports - RX PLL Ports ----------------------
wire gt3_rxresetdone_i;
//------------ Receive Ports - RX Pipe Control for PCI Express -------------
wire gt3_rxvalid_i;
//----------------------------- Transmit Ports -----------------------------
wire gt3_txprecursorinv_i;
wire gt3_txuserrdy_i;
//---------------- Transmit Ports - TX Data Path interface -----------------
wire gt3_gttxreset_i;
wire [15:0] gt3_txdata_i;
wire gt3_txoutclk_i;
wire gt3_txoutclkfabric_i;
wire gt3_txoutclkpcs_i;
wire gt3_txpcsreset_i;
//-------------- Transmit Ports - TX Driver and OOB signaling --------------
wire gt3_gtxtxn_i;
wire gt3_gtxtxp_i;
//--------- Transmit Ports - TX Elastic Buffer and Phase Alignment ---------
wire [1:0] gt3_txbufstatus_i;
//--------------------- Transmit Ports - TX PLL Ports ----------------------
wire gt3_txresetdone_i;
//________________________________________________________________________
//________________________________________________________________________
//GT4 (X0Y4)
//------------------------------ Channel PLL -------------------------------
wire gt4_cpllfbclklost_i;
wire gt4_cplllock_i;
wire gt4_cpllrefclklost_i;
wire gt4_cpllreset_i;
//----------------------------- Eye Scan Ports -----------------------------
wire gt4_eyescandataerror_i;
//---------------------- Loopback and Powerdown Ports ----------------------
wire [2:0] gt4_loopback_i;
wire [1:0] gt4_rxpd_i;
wire [1:0] gt4_txpd_i;
//----------------------------- Receive Ports ------------------------------
wire gt4_rxuserrdy_i;
//----------------- Receive Ports - Clock Correction Ports -----------------
wire [1:0] gt4_rxclkcorcnt_i;
//------------- Receive Ports - Comma Detection and Alignment --------------
wire gt4_rxbyteisaligned_i;
wire gt4_rxbyterealign_i;
wire gt4_rxcommadet_i;
wire gt4_rxslide_i;
//----------------- Receive Ports - RX Data Path interface -----------------
wire gt4_gtrxreset_i;
wire [15:0] gt4_rxdata_i;
wire gt4_rxoutclk_i;
wire gt4_rxpcsreset_i;
//----- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
wire gt4_gtxrxn_i;
wire gt4_gtxrxp_i;
wire gt4_rxcdrlock_i;
wire gt4_rxelecidle_i;
//------ Receive Ports - RX Elastic Buffer and Phase Alignment Ports -------
wire gt4_rxbufreset_i;
wire [2:0] gt4_rxbufstatus_i;
//---------------------- Receive Ports - RX PLL Ports ----------------------
wire gt4_rxresetdone_i;
//------------ Receive Ports - RX Pipe Control for PCI Express -------------
wire gt4_rxvalid_i;
//----------------------------- Transmit Ports -----------------------------
wire gt4_txprecursorinv_i;
wire gt4_txuserrdy_i;
//---------------- Transmit Ports - TX Data Path interface -----------------
wire gt4_gttxreset_i;
wire [15:0] gt4_txdata_i;
wire gt4_txoutclk_i;
wire gt4_txoutclkfabric_i;
wire gt4_txoutclkpcs_i;
wire gt4_txpcsreset_i;
//-------------- Transmit Ports - TX Driver and OOB signaling --------------
wire gt4_gtxtxn_i;
wire gt4_gtxtxp_i;
//--------- Transmit Ports - TX Elastic Buffer and Phase Alignment ---------
wire [1:0] gt4_txbufstatus_i;
//--------------------- Transmit Ports - TX PLL Ports ----------------------
wire gt4_txresetdone_i;
//________________________________________________________________________
//________________________________________________________________________
//GT5 (X0Y5)
//------------------------------ Channel PLL -------------------------------
wire gt5_cpllfbclklost_i;
wire gt5_cplllock_i;
wire gt5_cpllrefclklost_i;
wire gt5_cpllreset_i;
//----------------------------- Eye Scan Ports -----------------------------
wire gt5_eyescandataerror_i;
//---------------------- Loopback and Powerdown Ports ----------------------
wire [2:0] gt5_loopback_i;
wire [1:0] gt5_rxpd_i;
wire [1:0] gt5_txpd_i;
//----------------------------- Receive Ports ------------------------------
wire gt5_rxuserrdy_i;
//----------------- Receive Ports - Clock Correction Ports -----------------
wire [1:0] gt5_rxclkcorcnt_i;
//------------- Receive Ports - Comma Detection and Alignment --------------
wire gt5_rxbyteisaligned_i;
wire gt5_rxbyterealign_i;
wire gt5_rxcommadet_i;
wire gt5_rxslide_i;
//----------------- Receive Ports - RX Data Path interface -----------------
wire gt5_gtrxreset_i;
wire [15:0] gt5_rxdata_i;
wire gt5_rxoutclk_i;
wire gt5_rxpcsreset_i;
//----- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
wire gt5_gtxrxn_i;
wire gt5_gtxrxp_i;
wire gt5_rxcdrlock_i;
wire gt5_rxelecidle_i;
//------ Receive Ports - RX Elastic Buffer and Phase Alignment Ports -------
wire gt5_rxbufreset_i;
wire [2:0] gt5_rxbufstatus_i;
//---------------------- Receive Ports - RX PLL Ports ----------------------
wire gt5_rxresetdone_i;
//------------ Receive Ports - RX Pipe Control for PCI Express -------------
wire gt5_rxvalid_i;
//----------------------------- Transmit Ports -----------------------------
wire gt5_txprecursorinv_i;
wire gt5_txuserrdy_i;
//---------------- Transmit Ports - TX Data Path interface -----------------
wire gt5_gttxreset_i;
wire [15:0] gt5_txdata_i;
wire gt5_txoutclk_i;
wire gt5_txoutclkfabric_i;
wire gt5_txoutclkpcs_i;
wire gt5_txpcsreset_i;
//-------------- Transmit Ports - TX Driver and OOB signaling --------------
wire gt5_gtxtxn_i;
wire gt5_gtxtxp_i;
//--------- Transmit Ports - TX Elastic Buffer and Phase Alignment ---------
wire [1:0] gt5_txbufstatus_i;
//--------------------- Transmit Ports - TX PLL Ports ----------------------
wire gt5_txresetdone_i;
//________________________________________________________________________
//________________________________________________________________________
//GT6 (X0Y6)
//------------------------------ Channel PLL -------------------------------
wire gt6_cpllfbclklost_i;
wire gt6_cplllock_i;
wire gt6_cpllrefclklost_i;
wire gt6_cpllreset_i;
//----------------------------- Eye Scan Ports -----------------------------
wire gt6_eyescandataerror_i;
//---------------------- Loopback and Powerdown Ports ----------------------
wire [2:0] gt6_loopback_i;
wire [1:0] gt6_rxpd_i;
wire [1:0] gt6_txpd_i;
//----------------------------- Receive Ports ------------------------------
wire gt6_rxuserrdy_i;
//----------------- Receive Ports - Clock Correction Ports -----------------
wire [1:0] gt6_rxclkcorcnt_i;
//------------- Receive Ports - Comma Detection and Alignment --------------
wire gt6_rxbyteisaligned_i;
wire gt6_rxbyterealign_i;
wire gt6_rxcommadet_i;
wire gt6_rxslide_i;
//----------------- Receive Ports - RX Data Path interface -----------------
wire gt6_gtrxreset_i;
wire [15:0] gt6_rxdata_i;
wire gt6_rxoutclk_i;
wire gt6_rxpcsreset_i;
//----- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
wire gt6_gtxrxn_i;
wire gt6_gtxrxp_i;
wire gt6_rxcdrlock_i;
wire gt6_rxelecidle_i;
//------ Receive Ports - RX Elastic Buffer and Phase Alignment Ports -------
wire gt6_rxbufreset_i;
wire [2:0] gt6_rxbufstatus_i;
//---------------------- Receive Ports - RX PLL Ports ----------------------
wire gt6_rxresetdone_i;
//------------ Receive Ports - RX Pipe Control for PCI Express -------------
wire gt6_rxvalid_i;
//----------------------------- Transmit Ports -----------------------------
wire gt6_txprecursorinv_i;
wire gt6_txuserrdy_i;
//---------------- Transmit Ports - TX Data Path interface -----------------
wire gt6_gttxreset_i;
wire [15:0] gt6_txdata_i;
wire gt6_txoutclk_i;
wire gt6_txoutclkfabric_i;
wire gt6_txoutclkpcs_i;
wire gt6_txpcsreset_i;
//-------------- Transmit Ports - TX Driver and OOB signaling --------------
wire gt6_gtxtxn_i;
wire gt6_gtxtxp_i;
//--------- Transmit Ports - TX Elastic Buffer and Phase Alignment ---------
wire [1:0] gt6_txbufstatus_i;
//--------------------- Transmit Ports - TX PLL Ports ----------------------
wire gt6_txresetdone_i;
//________________________________________________________________________
//________________________________________________________________________
//GT7 (X0Y7)
//------------------------------ Channel PLL -------------------------------
wire gt7_cpllfbclklost_i;
wire gt7_cplllock_i;
wire gt7_cpllrefclklost_i;
wire gt7_cpllreset_i;
//----------------------------- Eye Scan Ports -----------------------------
wire gt7_eyescandataerror_i;
//---------------------- Loopback and Powerdown Ports ----------------------
wire [2:0] gt7_loopback_i;
wire [1:0] gt7_rxpd_i;
wire [1:0] gt7_txpd_i;
//----------------------------- Receive Ports ------------------------------
wire gt7_rxuserrdy_i;
//----------------- Receive Ports - Clock Correction Ports -----------------
wire [1:0] gt7_rxclkcorcnt_i;
//------------- Receive Ports - Comma Detection and Alignment --------------
wire gt7_rxbyteisaligned_i;
wire gt7_rxbyterealign_i;
wire gt7_rxcommadet_i;
wire gt7_rxslide_i;
//----------------- Receive Ports - RX Data Path interface -----------------
wire gt7_gtrxreset_i;
wire [15:0] gt7_rxdata_i;
wire gt7_rxoutclk_i;
wire gt7_rxpcsreset_i;
//----- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
wire gt7_gtxrxn_i;
wire gt7_gtxrxp_i;
wire gt7_rxcdrlock_i;
wire gt7_rxelecidle_i;
//------ Receive Ports - RX Elastic Buffer and Phase Alignment Ports -------
wire gt7_rxbufreset_i;
wire [2:0] gt7_rxbufstatus_i;
//---------------------- Receive Ports - RX PLL Ports ----------------------
wire gt7_rxresetdone_i;
//------------ Receive Ports - RX Pipe Control for PCI Express -------------
wire gt7_rxvalid_i;
//----------------------------- Transmit Ports -----------------------------
wire gt7_txprecursorinv_i;
wire gt7_txuserrdy_i;
//---------------- Transmit Ports - TX Data Path interface -----------------
wire gt7_gttxreset_i;
wire [15:0] gt7_txdata_i;
wire gt7_txoutclk_i;
wire gt7_txoutclkfabric_i;
wire gt7_txoutclkpcs_i;
wire gt7_txpcsreset_i;
//-------------- Transmit Ports - TX Driver and OOB signaling --------------
wire gt7_gtxtxn_i;
wire gt7_gtxtxp_i;
//--------- Transmit Ports - TX Elastic Buffer and Phase Alignment ---------
wire [1:0] gt7_txbufstatus_i;
//--------------------- Transmit Ports - TX PLL Ports ----------------------
wire gt7_txresetdone_i;
//----------------------------- Global Signals -----------------------------
wire drpclk_in_i;
wire gt0_tx_system_reset_c;
wire gt0_rx_system_reset_c;
wire gt1_tx_system_reset_c;
wire gt1_rx_system_reset_c;
wire gt2_tx_system_reset_c;
wire gt2_rx_system_reset_c;
wire gt3_tx_system_reset_c;
wire gt3_rx_system_reset_c;
wire gt4_tx_system_reset_c;
wire gt4_rx_system_reset_c;
wire gt5_tx_system_reset_c;
wire gt5_rx_system_reset_c;
wire gt6_tx_system_reset_c;
wire gt6_rx_system_reset_c;
wire gt7_tx_system_reset_c;
wire gt7_rx_system_reset_c;
wire tied_to_ground_i;
wire [63:0] tied_to_ground_vec_i;
wire tied_to_vcc_i;
wire [7:0] tied_to_vcc_vec_i;
//--------------------------- User Clocks ---------------------------------
wire gt0_txusrclk_i;
wire gt0_txusrclk2_i;
wire gt0_txclk_lock_out_i;
wire gt0_rxusrclk_i;
wire gt0_rxusrclk2_i;
wire gt0_rxclk_lock_out_i;
wire gt1_txusrclk_i;
wire gt1_txusrclk2_i;
wire gt1_txclk_lock_out_i;
wire gt1_rxusrclk_i;
wire gt1_rxusrclk2_i;
wire gt1_rxclk_lock_out_i;
wire gt2_txusrclk_i;
wire gt2_txusrclk2_i;
wire gt2_txclk_lock_out_i;
wire gt2_rxusrclk_i;
wire gt2_rxusrclk2_i;
wire gt2_rxclk_lock_out_i;
wire gt3_txusrclk_i;
wire gt3_txusrclk2_i;
wire gt3_txclk_lock_out_i;
wire gt3_rxusrclk_i;
wire gt3_rxusrclk2_i;
wire gt3_rxclk_lock_out_i;
wire gt4_txusrclk_i;
wire gt4_txusrclk2_i;
wire gt4_txclk_lock_out_i;
wire gt4_rxusrclk_i;
wire gt4_rxusrclk2_i;
wire gt4_rxclk_lock_out_i;
wire gt5_txusrclk_i;
wire gt5_txusrclk2_i;
wire gt5_txclk_lock_out_i;
wire gt5_rxusrclk_i;
wire gt5_rxusrclk2_i;
wire gt5_rxclk_lock_out_i;
wire gt6_txusrclk_i;
wire gt6_txusrclk2_i;
wire gt6_txclk_lock_out_i;
wire gt6_rxusrclk_i;
wire gt6_rxusrclk2_i;
wire gt6_rxclk_lock_out_i;
wire gt7_txusrclk_i;
wire gt7_txusrclk2_i;
wire gt7_txclk_lock_out_i;
wire gt7_rxusrclk_i;
wire gt7_rxusrclk2_i;
wire gt7_rxclk_lock_out_i;
//--------------------------- Reference Clocks ----------------------------
wire q0_clk0_refclk_i;
wire q0_clk1_refclk_i;
wire q1_clk0_refclk_i;
wire q1_clk1_refclk_i;
//--------------------- Frame check/gen Module Signals --------------------
wire gt0_matchn_i;
wire [5:0] gt0_txcharisk_float_i;
wire [15:0] gt0_txdata_float16_i;
wire [47:0] gt0_txdata_float_i;
wire gt0_block_sync_i;
wire gt0_track_data_i;
wire [7:0] gt0_error_count_i;
wire gt0_frame_check_reset_i;
wire gt0_inc_in_i;
wire gt0_inc_out_i;
wire [15:0] gt0_unscrambled_data_i;
wire gt1_matchn_i;
wire [5:0] gt1_txcharisk_float_i;
wire [15:0] gt1_txdata_float16_i;
wire [47:0] gt1_txdata_float_i;
wire gt1_block_sync_i;
wire gt1_track_data_i;
wire [7:0] gt1_error_count_i;
wire gt1_frame_check_reset_i;
wire gt1_inc_in_i;
wire gt1_inc_out_i;
wire [15:0] gt1_unscrambled_data_i;
wire gt2_matchn_i;
wire [5:0] gt2_txcharisk_float_i;
wire [15:0] gt2_txdata_float16_i;
wire [47:0] gt2_txdata_float_i;
wire gt2_block_sync_i;
wire gt2_track_data_i;
wire [7:0] gt2_error_count_i;
wire gt2_frame_check_reset_i;
wire gt2_inc_in_i;
wire gt2_inc_out_i;
wire [15:0] gt2_unscrambled_data_i;
wire gt3_matchn_i;
wire [5:0] gt3_txcharisk_float_i;
wire [15:0] gt3_txdata_float16_i;
wire [47:0] gt3_txdata_float_i;
wire gt3_block_sync_i;
wire gt3_track_data_i;
wire [7:0] gt3_error_count_i;
wire gt3_frame_check_reset_i;
wire gt3_inc_in_i;
wire gt3_inc_out_i;
wire [15:0] gt3_unscrambled_data_i;
wire gt4_matchn_i;
wire [5:0] gt4_txcharisk_float_i;
wire [15:0] gt4_txdata_float16_i;
wire [47:0] gt4_txdata_float_i;
wire gt4_block_sync_i;
wire gt4_track_data_i;
wire [7:0] gt4_error_count_i;
wire gt4_frame_check_reset_i;
wire gt4_inc_in_i;
wire gt4_inc_out_i;
wire [15:0] gt4_unscrambled_data_i;
wire gt5_matchn_i;
wire [5:0] gt5_txcharisk_float_i;
wire [15:0] gt5_txdata_float16_i;
wire [47:0] gt5_txdata_float_i;
wire gt5_block_sync_i;
wire gt5_track_data_i;
wire [7:0] gt5_error_count_i;
wire gt5_frame_check_reset_i;
wire gt5_inc_in_i;
wire gt5_inc_out_i;
wire [15:0] gt5_unscrambled_data_i;
wire gt6_matchn_i;
wire [5:0] gt6_txcharisk_float_i;
wire [15:0] gt6_txdata_float16_i;
wire [47:0] gt6_txdata_float_i;
wire gt6_block_sync_i;
wire gt6_track_data_i;
wire [7:0] gt6_error_count_i;
wire gt6_frame_check_reset_i;
wire gt6_inc_in_i;
wire gt6_inc_out_i;
wire [15:0] gt6_unscrambled_data_i;
wire gt7_matchn_i;
wire [5:0] gt7_txcharisk_float_i;
wire [15:0] gt7_txdata_float16_i;
wire [47:0] gt7_txdata_float_i;
wire gt7_block_sync_i;
wire gt7_track_data_i;
wire [7:0] gt7_error_count_i;
wire gt7_frame_check_reset_i;
wire gt7_inc_in_i;
wire gt7_inc_out_i;
wire [15:0] gt7_unscrambled_data_i;
wire reset_on_data_error_i;
wire track_data_out_i;
//--------------------- Chipscope Signals ---------------------------------
wire [35:0] tx_data_vio_control_i;
wire [35:0] rx_data_vio_control_i;
wire [35:0] shared_vio_control_i;
wire [35:0] ila_control_i;
wire [31:0] tx_data_vio_async_in_i;
wire [31:0] tx_data_vio_sync_in_i;
wire [31:0] tx_data_vio_async_out_i;
wire [31:0] tx_data_vio_sync_out_i;
wire [31:0] rx_data_vio_async_in_i;
wire [31:0] rx_data_vio_sync_in_i;
wire [31:0] rx_data_vio_async_out_i;
wire [31:0] rx_data_vio_sync_out_i;
wire [31:0] shared_vio_in_i;
wire [31:0] shared_vio_out_i;
wire [163:0] ila_in_i;
wire [31:0] gt0_tx_data_vio_async_in_i;
wire [31:0] gt0_tx_data_vio_sync_in_i;
wire [31:0] gt0_tx_data_vio_async_out_i;
wire [31:0] gt0_tx_data_vio_sync_out_i;
wire [31:0] gt0_rx_data_vio_async_in_i;
wire [31:0] gt0_rx_data_vio_sync_in_i;
wire [31:0] gt0_rx_data_vio_async_out_i;
wire [31:0] gt0_rx_data_vio_sync_out_i;
wire [163:0] gt0_ila_in_i;
wire [31:0] gt1_tx_data_vio_async_in_i;
wire [31:0] gt1_tx_data_vio_sync_in_i;
wire [31:0] gt1_tx_data_vio_async_out_i;
wire [31:0] gt1_tx_data_vio_sync_out_i;
wire [31:0] gt1_rx_data_vio_async_in_i;
wire [31:0] gt1_rx_data_vio_sync_in_i;
wire [31:0] gt1_rx_data_vio_async_out_i;
wire [31:0] gt1_rx_data_vio_sync_out_i;
wire [163:0] gt1_ila_in_i;
wire [31:0] gt2_tx_data_vio_async_in_i;
wire [31:0] gt2_tx_data_vio_sync_in_i;
wire [31:0] gt2_tx_data_vio_async_out_i;
wire [31:0] gt2_tx_data_vio_sync_out_i;
wire [31:0] gt2_rx_data_vio_async_in_i;
wire [31:0] gt2_rx_data_vio_sync_in_i;
wire [31:0] gt2_rx_data_vio_async_out_i;
wire [31:0] gt2_rx_data_vio_sync_out_i;
wire [163:0] gt2_ila_in_i;
wire [31:0] gt3_tx_data_vio_async_in_i;
wire [31:0] gt3_tx_data_vio_sync_in_i;
wire [31:0] gt3_tx_data_vio_async_out_i;
wire [31:0] gt3_tx_data_vio_sync_out_i;
wire [31:0] gt3_rx_data_vio_async_in_i;
wire [31:0] gt3_rx_data_vio_sync_in_i;
wire [31:0] gt3_rx_data_vio_async_out_i;
wire [31:0] gt3_rx_data_vio_sync_out_i;
wire [163:0] gt3_ila_in_i;
wire [31:0] gt4_tx_data_vio_async_in_i;
wire [31:0] gt4_tx_data_vio_sync_in_i;
wire [31:0] gt4_tx_data_vio_async_out_i;
wire [31:0] gt4_tx_data_vio_sync_out_i;
wire [31:0] gt4_rx_data_vio_async_in_i;
wire [31:0] gt4_rx_data_vio_sync_in_i;
wire [31:0] gt4_rx_data_vio_async_out_i;
wire [31:0] gt4_rx_data_vio_sync_out_i;
wire [163:0] gt4_ila_in_i;
wire [31:0] gt5_tx_data_vio_async_in_i;
wire [31:0] gt5_tx_data_vio_sync_in_i;
wire [31:0] gt5_tx_data_vio_async_out_i;
wire [31:0] gt5_tx_data_vio_sync_out_i;
wire [31:0] gt5_rx_data_vio_async_in_i;
wire [31:0] gt5_rx_data_vio_sync_in_i;
wire [31:0] gt5_rx_data_vio_async_out_i;
wire [31:0] gt5_rx_data_vio_sync_out_i;
wire [163:0] gt5_ila_in_i;
wire [31:0] gt6_tx_data_vio_async_in_i;
wire [31:0] gt6_tx_data_vio_sync_in_i;
wire [31:0] gt6_tx_data_vio_async_out_i;
wire [31:0] gt6_tx_data_vio_sync_out_i;
wire [31:0] gt6_rx_data_vio_async_in_i;
wire [31:0] gt6_rx_data_vio_sync_in_i;
wire [31:0] gt6_rx_data_vio_async_out_i;
wire [31:0] gt6_rx_data_vio_sync_out_i;
wire [163:0] gt6_ila_in_i;
wire [31:0] gt7_tx_data_vio_async_in_i;
wire [31:0] gt7_tx_data_vio_sync_in_i;
wire [31:0] gt7_tx_data_vio_async_out_i;
wire [31:0] gt7_tx_data_vio_sync_out_i;
wire [31:0] gt7_rx_data_vio_async_in_i;
wire [31:0] gt7_rx_data_vio_sync_in_i;
wire [31:0] gt7_rx_data_vio_async_out_i;
wire [31:0] gt7_rx_data_vio_sync_out_i;
wire [163:0] gt7_ila_in_i;
// WishBone interface
reg [127:0] data_o;
reg [31:0] control_reg;
reg [127:0] data_reg;
reg [127:0] data_i;
reg ready_i;
wire gttxreset_i;
wire gtrxreset_i;
wire [2:0] mux_sel_i;
wire user_tx_reset_i;
wire user_rx_reset_i;
wire tx_vio_clk_i;
wire tx_vio_clk_mux_out_i;
wire rx_vio_ila_clk_i;
wire rx_vio_ila_clk_mux_out_i;
wire cpllreset_i;
//--------------------- Wishbone Interface ---------------
always @(posedge wb_clk or posedge wb_reset) begin
if(wb_reset==1) begin
wb_ack_o <= #1 0;
wb_dat_o <= #1 0;
control_reg <= #1 32'h0;
data_reg <= #1 127'h0;
data_o <= #1 127'h0;
end
else begin
if(ready_i) begin
control_reg[1] <= #1 1'b1;
data_reg <= #1 data_i;
end
else if(wb_stb_i && wb_cyc_i && wb_we_i && ~wb_ack_o) begin
wb_ack_o<=#1 1;
case(wb_adr_i[7:0])
8'h0: begin
//Writing control register
control_reg<= #1 wb_dat_i;
end
8'h4: begin
data_o[127:96]<= #1 wb_dat_i;
end
8'h8: begin
data_o[95:64]<= #1 wb_dat_i;
end
8'hC: begin
data_o[63:32]<= #1 wb_dat_i;
end
8'h10:begin
data_o[31:0]<= #1 wb_dat_i;
end
endcase
end
else if(wb_stb_i && wb_cyc_i && ~wb_we_i && ~wb_ack_o) begin
wb_ack_o<=#1 1;
case(wb_adr_i[7:0])
8'h0: begin
wb_dat_o<= #1 control_reg;
control_reg[1]<=1'b0;
end
8'h24: begin
wb_dat_o<= #1 data_reg[127:96];
end
8'h28: begin
wb_dat_o<= #1 data_reg[95:64];
end
8'h2C: begin
wb_dat_o<= #1 data_reg[63:32];
end
8'h30: begin
wb_dat_o<= #1 data_reg[31:0];
end
endcase
end
else begin
wb_ack_o<=#1 0;
control_reg[0]<= #1 1'b0;
end
end
end
// Xilinx add in an output register
always @(posedge wb_clk) begin
//wb_rty_o <= tile0_rxlossofsync0_i & tile0_rxlossofsync1_i & tile1_rxlossofsync0_i & tile1_rxlossofsync1_i & tile2_rxlossofsync0_i & tile2_rxlossofsync1_i & tile3_rxlossofsync0_i & tile3_rxlossofsync1_i ;
wb_rty_o <= gt0_cpllrefclklost_i & gt1_cpllrefclklost_i & gt2_cpllrefclklost_i & gt3_cpllrefclklost_i &
gt4_cpllrefclklost_i & gt5_cpllrefclklost_i & gt6_cpllrefclklost_i & gt7_cpllrefclklost_i;
end
//**************************** Main Body of GT Code *******************************
// Static signal Assigments
assign tied_to_ground_i = 1'b0;
assign tied_to_ground_vec_i = 64'h0000000000000000;
assign tied_to_vcc_i = 1'b1;
assign tied_to_vcc_vec_i = 8'hff;
ROCKETIO_WRAPPER_TILE_GT_USRCLK_SOURCE gt_usrclk_source
(
.Q0_CLK0_GTREFCLK_PAD_N_IN (Q0_CLK0_GTREFCLK_PAD_N_IN),
.Q0_CLK0_GTREFCLK_PAD_P_IN (Q0_CLK0_GTREFCLK_PAD_P_IN),
.Q0_CLK0_GTREFCLK_OUT (q0_clk0_refclk_i),
.Q0_CLK1_GTREFCLK_PAD_N_IN (Q0_CLK1_GTREFCLK_PAD_N_IN),
.Q0_CLK1_GTREFCLK_PAD_P_IN (Q0_CLK1_GTREFCLK_PAD_P_IN),
.Q0_CLK1_GTREFCLK_OUT (q0_clk1_refclk_i),
.Q1_CLK0_GTREFCLK_PAD_N_IN (Q1_CLK0_GTREFCLK_PAD_N_IN),
.Q1_CLK0_GTREFCLK_PAD_P_IN (Q1_CLK0_GTREFCLK_PAD_P_IN),
.Q1_CLK0_GTREFCLK_OUT (q1_clk0_refclk_i),
.Q1_CLK1_GTREFCLK_PAD_N_IN (Q1_CLK1_GTREFCLK_PAD_N_IN),
.Q1_CLK1_GTREFCLK_PAD_P_IN (Q1_CLK1_GTREFCLK_PAD_P_IN),
.Q1_CLK1_GTREFCLK_OUT (q1_clk1_refclk_i),
.GT0_TXUSRCLK_OUT (gt0_txusrclk_i),
.GT0_TXUSRCLK2_OUT (gt0_txusrclk2_i),
.GT0_TXOUTCLK_IN (gt0_txoutclk_i),
.GT0_RXUSRCLK_OUT (gt0_rxusrclk_i),
.GT0_RXUSRCLK2_OUT (gt0_rxusrclk2_i),
.GT0_RXOUTCLK_IN (gt0_rxoutclk_i),
.GT1_TXUSRCLK_OUT (gt1_txusrclk_i),
.GT1_TXUSRCLK2_OUT (gt1_txusrclk2_i),
.GT1_TXOUTCLK_IN (gt1_txoutclk_i),
.GT1_RXUSRCLK_OUT (gt1_rxusrclk_i),
.GT1_RXUSRCLK2_OUT (gt1_rxusrclk2_i),
.GT1_RXOUTCLK_IN (gt1_rxoutclk_i),
.GT2_TXUSRCLK_OUT (gt2_txusrclk_i),
.GT2_TXUSRCLK2_OUT (gt2_txusrclk2_i),
.GT2_TXOUTCLK_IN (gt2_txoutclk_i),
.GT2_RXUSRCLK_OUT (gt2_rxusrclk_i),
.GT2_RXUSRCLK2_OUT (gt2_rxusrclk2_i),
.GT2_RXOUTCLK_IN (gt2_rxoutclk_i),
.GT3_TXUSRCLK_OUT (gt3_txusrclk_i),
.GT3_TXUSRCLK2_OUT (gt3_txusrclk2_i),
.GT3_TXOUTCLK_IN (gt3_txoutclk_i),
.GT3_RXUSRCLK_OUT (gt3_rxusrclk_i),
.GT3_RXUSRCLK2_OUT (gt3_rxusrclk2_i),
.GT3_RXOUTCLK_IN (gt3_rxoutclk_i),
.GT4_TXUSRCLK_OUT (gt4_txusrclk_i),
.GT4_TXUSRCLK2_OUT (gt4_txusrclk2_i),
.GT4_TXOUTCLK_IN (gt4_txoutclk_i),
.GT4_RXUSRCLK_OUT (gt4_rxusrclk_i),
.GT4_RXUSRCLK2_OUT (gt4_rxusrclk2_i),
.GT4_RXOUTCLK_IN (gt4_rxoutclk_i),
.GT5_TXUSRCLK_OUT (gt5_txusrclk_i),
.GT5_TXUSRCLK2_OUT (gt5_txusrclk2_i),
.GT5_TXOUTCLK_IN (gt5_txoutclk_i),
.GT5_RXUSRCLK_OUT (gt5_rxusrclk_i),
.GT5_RXUSRCLK2_OUT (gt5_rxusrclk2_i),
.GT5_RXOUTCLK_IN (gt5_rxoutclk_i),
.GT6_TXUSRCLK_OUT (gt6_txusrclk_i),
.GT6_TXUSRCLK2_OUT (gt6_txusrclk2_i),
.GT6_TXOUTCLK_IN (gt6_txoutclk_i),
.GT6_RXUSRCLK_OUT (gt6_rxusrclk_i),
.GT6_RXUSRCLK2_OUT (gt6_rxusrclk2_i),
.GT6_RXOUTCLK_IN (gt6_rxoutclk_i),
.GT7_TXUSRCLK_OUT (gt7_txusrclk_i),
.GT7_TXUSRCLK2_OUT (gt7_txusrclk2_i),
.GT7_TXOUTCLK_IN (gt7_txoutclk_i),
.GT7_RXUSRCLK_OUT (gt7_rxusrclk_i),
.GT7_RXUSRCLK2_OUT (gt7_rxusrclk2_i),
.GT7_RXOUTCLK_IN (gt7_rxoutclk_i),
.DRPCLK_IN (SYSCLK_IN),
.DRPCLK_OUT(drpclk_in_i)
);
//***********************************************************************//
// //
//--------------------------- The GT Wrapper ----------------------------//
// //
//***********************************************************************//
// Use the instantiation template in the example directory to add the GT wrapper to your design.
// In this example, the wrapper is wired up for basic operation with a frame generator and frame
// checker. The GTs will reset, then attempt to align and transmit data. If channel bonding is
// enabled, bonding should occur after alignment.
ROCKETIO_WRAPPER_TILE #
(
.WRAPPER_SIM_GTRESET_SPEEDUP (EXAMPLE_SIM_GTRESET_SPEEDUP)
)
ROCKETIO_WRAPPER_TILE_i
(
//_____________________________________________________________________
//_____________________________________________________________________
//GT0 (X0Y0)
//----------------------- Channel - Ref Clock Ports ------------------------
.GT0_GTREFCLK0_IN (q0_clk0_refclk_i),
//------------------------------ Channel PLL -------------------------------
.GT0_CPLLFBCLKLOST_OUT (gt0_cpllfbclklost_i),
.GT0_CPLLLOCK_OUT (gt0_cplllock_i),
.GT0_CPLLLOCKDETCLK_IN (drpclk_in_i),
.GT0_CPLLREFCLKLOST_OUT (gt0_cpllrefclklost_i),
.GT0_CPLLRESET_IN (gt0_cpllreset_i),
//----------------------------- Eye Scan Ports -----------------------------
.GT0_EYESCANDATAERROR_OUT (gt0_eyescandataerror_i),
//---------------------- Loopback and Powerdown Ports ----------------------
.GT0_LOOPBACK_IN (gt0_loopback_i),
.GT0_RXPD_IN (gt0_rxpd_i),
.GT0_TXPD_IN (gt0_txpd_i),
//----------------------------- Receive Ports ------------------------------
.GT0_RXUSERRDY_IN (gt0_rxuserrdy_i),
//----------------- Receive Ports - Clock Correction Ports -----------------
.GT0_RXCLKCORCNT_OUT (gt0_rxclkcorcnt_i),
//------------- Receive Ports - Comma Detection and Alignment --------------
.GT0_RXBYTEISALIGNED_OUT (gt0_rxbyteisaligned_i),
.GT0_RXBYTEREALIGN_OUT (gt0_rxbyterealign_i),
.GT0_RXCOMMADET_OUT (gt0_rxcommadet_i),
.GT0_RXSLIDE_IN (gt0_rxslide_i),
//----------------- Receive Ports - RX Data Path interface -----------------
.GT0_GTRXRESET_IN (gt0_gtrxreset_i),
.GT0_RXDATA_OUT (gt0_rxdata_i),
.GT0_RXOUTCLK_OUT (gt0_rxoutclk_i),
.GT0_RXPCSRESET_IN (gt0_rxpcsreset_i),
.GT0_RXUSRCLK_IN (gt0_txusrclk_i),
.GT0_RXUSRCLK2_IN (gt0_txusrclk_i),
//----- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
.GT0_GTXRXN_IN (RXN_IN[0]),
.GT0_GTXRXP_IN (RXP_IN[0]),
.GT0_RXCDRLOCK_OUT (gt0_rxcdrlock_i),
.GT0_RXELECIDLE_OUT (gt0_rxelecidle_i),
//------ Receive Ports - RX Elastic Buffer and Phase Alignment Ports -------
.GT0_RXBUFRESET_IN (gt0_rxbufreset_i),
.GT0_RXBUFSTATUS_OUT (gt0_rxbufstatus_i),
//---------------------- Receive Ports - RX PLL Ports ----------------------
.GT0_RXRESETDONE_OUT (gt0_rxresetdone_i),
//------------ Receive Ports - RX Pipe Control for PCI Express -------------
.GT0_RXVALID_OUT (gt0_rxvalid_i),
//----------------------------- Transmit Ports -----------------------------
.GT0_TXPRECURSORINV_IN (gt0_txprecursorinv_i),
.GT0_TXUSERRDY_IN (gt0_txuserrdy_i),
//---------------- Transmit Ports - TX Data Path interface -----------------
.GT0_GTTXRESET_IN (gt0_gttxreset_i),
.GT0_TXDATA_IN (gt0_txdata_i),
.GT0_TXOUTCLK_OUT (gt0_txoutclk_i),
.GT0_TXOUTCLKFABRIC_OUT (gt0_txoutclkfabric_i),
.GT0_TXOUTCLKPCS_OUT (gt0_txoutclkpcs_i),
.GT0_TXPCSRESET_IN (gt0_txpcsreset_i),
.GT0_TXUSRCLK_IN (gt0_txusrclk_i),
.GT0_TXUSRCLK2_IN (gt0_txusrclk_i),
//-------------- Transmit Ports - TX Driver and OOB signaling --------------
.GT0_GTXTXN_OUT (TXN_OUT[0]),
.GT0_GTXTXP_OUT (TXP_OUT[0]),
//--------- Transmit Ports - TX Elastic Buffer and Phase Alignment ---------
.GT0_TXBUFSTATUS_OUT (gt0_txbufstatus_i),
//--------------------- Transmit Ports - TX PLL Ports ----------------------
.GT0_TXRESETDONE_OUT (gt0_txresetdone_i),
//_____________________________________________________________________
//_____________________________________________________________________
//GT1 (X0Y1)
//----------------------- Channel - Ref Clock Ports ------------------------
.GT1_GTREFCLK0_IN (q0_clk0_refclk_i),
//------------------------------ Channel PLL -------------------------------
.GT1_CPLLFBCLKLOST_OUT (gt1_cpllfbclklost_i),
.GT1_CPLLLOCK_OUT (gt1_cplllock_i),
.GT1_CPLLLOCKDETCLK_IN (drpclk_in_i),
.GT1_CPLLREFCLKLOST_OUT (gt1_cpllrefclklost_i),
.GT1_CPLLRESET_IN (gt1_cpllreset_i),
//----------------------------- Eye Scan Ports -----------------------------
.GT1_EYESCANDATAERROR_OUT (gt1_eyescandataerror_i),
//---------------------- Loopback and Powerdown Ports ----------------------
.GT1_LOOPBACK_IN (gt1_loopback_i),
.GT1_RXPD_IN (gt1_rxpd_i),
.GT1_TXPD_IN (gt1_txpd_i),
//----------------------------- Receive Ports ------------------------------
.GT1_RXUSERRDY_IN (gt1_rxuserrdy_i),
//----------------- Receive Ports - Clock Correction Ports -----------------
.GT1_RXCLKCORCNT_OUT (gt1_rxclkcorcnt_i),
//------------- Receive Ports - Comma Detection and Alignment --------------
.GT1_RXBYTEISALIGNED_OUT (gt1_rxbyteisaligned_i),
.GT1_RXBYTEREALIGN_OUT (gt1_rxbyterealign_i),
.GT1_RXCOMMADET_OUT (gt1_rxcommadet_i),
.GT1_RXSLIDE_IN (gt1_rxslide_i),
//----------------- Receive Ports - RX Data Path interface -----------------
.GT1_GTRXRESET_IN (gt1_gtrxreset_i),
.GT1_RXDATA_OUT (gt1_rxdata_i),
.GT1_RXOUTCLK_OUT (gt1_rxoutclk_i),
.GT1_RXPCSRESET_IN (gt1_rxpcsreset_i),
.GT1_RXUSRCLK_IN (gt0_txusrclk_i),
.GT1_RXUSRCLK2_IN (gt0_txusrclk_i),
//----- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
.GT1_GTXRXN_IN (RXN_IN[1]),
.GT1_GTXRXP_IN (RXP_IN[1]),
.GT1_RXCDRLOCK_OUT (gt1_rxcdrlock_i),
.GT1_RXELECIDLE_OUT (gt1_rxelecidle_i),
//------ Receive Ports - RX Elastic Buffer and Phase Alignment Ports -------
.GT1_RXBUFRESET_IN (gt1_rxbufreset_i),
.GT1_RXBUFSTATUS_OUT (gt1_rxbufstatus_i),
//---------------------- Receive Ports - RX PLL Ports ----------------------
.GT1_RXRESETDONE_OUT (gt1_rxresetdone_i),
//------------ Receive Ports - RX Pipe Control for PCI Express -------------
.GT1_RXVALID_OUT (gt1_rxvalid_i),
//----------------------------- Transmit Ports -----------------------------
.GT1_TXPRECURSORINV_IN (gt1_txprecursorinv_i),
.GT1_TXUSERRDY_IN (gt1_txuserrdy_i),
//---------------- Transmit Ports - TX Data Path interface -----------------
.GT1_GTTXRESET_IN (gt1_gttxreset_i),
.GT1_TXDATA_IN (gt1_txdata_i),
.GT1_TXOUTCLK_OUT (gt1_txoutclk_i),
.GT1_TXOUTCLKFABRIC_OUT (gt1_txoutclkfabric_i),
.GT1_TXOUTCLKPCS_OUT (gt1_txoutclkpcs_i),
.GT1_TXPCSRESET_IN (gt1_txpcsreset_i),
.GT1_TXUSRCLK_IN (gt0_txusrclk_i),
.GT1_TXUSRCLK2_IN (gt0_txusrclk_i),
//-------------- Transmit Ports - TX Driver and OOB signaling --------------
.GT1_GTXTXN_OUT (TXN_OUT[1]),
.GT1_GTXTXP_OUT (TXP_OUT[1]),
//--------- Transmit Ports - TX Elastic Buffer and Phase Alignment ---------
.GT1_TXBUFSTATUS_OUT (gt1_txbufstatus_i),
//--------------------- Transmit Ports - TX PLL Ports ----------------------
.GT1_TXRESETDONE_OUT (gt1_txresetdone_i),
//_____________________________________________________________________
//_____________________________________________________________________
//GT2 (X0Y2)
//----------------------- Channel - Ref Clock Ports ------------------------
.GT2_GTREFCLK0_IN (q0_clk1_refclk_i),
//------------------------------ Channel PLL -------------------------------
.GT2_CPLLFBCLKLOST_OUT (gt2_cpllfbclklost_i),
.GT2_CPLLLOCK_OUT (gt2_cplllock_i),
.GT2_CPLLLOCKDETCLK_IN (drpclk_in_i),
.GT2_CPLLREFCLKLOST_OUT (gt2_cpllrefclklost_i),
.GT2_CPLLRESET_IN (gt2_cpllreset_i),
//----------------------------- Eye Scan Ports -----------------------------
.GT2_EYESCANDATAERROR_OUT (gt2_eyescandataerror_i),
//---------------------- Loopback and Powerdown Ports ----------------------
.GT2_LOOPBACK_IN (gt2_loopback_i),
.GT2_RXPD_IN (gt2_rxpd_i),
.GT2_TXPD_IN (gt2_txpd_i),
//----------------------------- Receive Ports ------------------------------
.GT2_RXUSERRDY_IN (gt2_rxuserrdy_i),
//----------------- Receive Ports - Clock Correction Ports -----------------
.GT2_RXCLKCORCNT_OUT (gt2_rxclkcorcnt_i),
//------------- Receive Ports - Comma Detection and Alignment --------------
.GT2_RXBYTEISALIGNED_OUT (gt2_rxbyteisaligned_i),
.GT2_RXBYTEREALIGN_OUT (gt2_rxbyterealign_i),
.GT2_RXCOMMADET_OUT (gt2_rxcommadet_i),
.GT2_RXSLIDE_IN (gt2_rxslide_i),
//----------------- Receive Ports - RX Data Path interface -----------------
.GT2_GTRXRESET_IN (gt2_gtrxreset_i),
.GT2_RXDATA_OUT (gt2_rxdata_i),
.GT2_RXOUTCLK_OUT (gt2_rxoutclk_i),
.GT2_RXPCSRESET_IN (gt2_rxpcsreset_i),
.GT2_RXUSRCLK_IN (gt2_txusrclk_i),
.GT2_RXUSRCLK2_IN (gt2_txusrclk_i),
//----- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
.GT2_GTXRXN_IN (RXN_IN[2]),
.GT2_GTXRXP_IN (RXP_IN[2]),
.GT2_RXCDRLOCK_OUT (gt2_rxcdrlock_i),
.GT2_RXELECIDLE_OUT (gt2_rxelecidle_i),
//------ Receive Ports - RX Elastic Buffer and Phase Alignment Ports -------
.GT2_RXBUFRESET_IN (gt2_rxbufreset_i),
.GT2_RXBUFSTATUS_OUT (gt2_rxbufstatus_i),
//---------------------- Receive Ports - RX PLL Ports ----------------------
.GT2_RXRESETDONE_OUT (gt2_rxresetdone_i),
//------------ Receive Ports - RX Pipe Control for PCI Express -------------
.GT2_RXVALID_OUT (gt2_rxvalid_i),
//----------------------------- Transmit Ports -----------------------------
.GT2_TXPRECURSORINV_IN (gt2_txprecursorinv_i),
.GT2_TXUSERRDY_IN (gt2_txuserrdy_i),
//---------------- Transmit Ports - TX Data Path interface -----------------
.GT2_GTTXRESET_IN (gt2_gttxreset_i),
.GT2_TXDATA_IN (gt2_txdata_i),
.GT2_TXOUTCLK_OUT (gt2_txoutclk_i),
.GT2_TXOUTCLKFABRIC_OUT (gt2_txoutclkfabric_i),
.GT2_TXOUTCLKPCS_OUT (gt2_txoutclkpcs_i),
.GT2_TXPCSRESET_IN (gt2_txpcsreset_i),
.GT2_TXUSRCLK_IN (gt2_txusrclk_i),
.GT2_TXUSRCLK2_IN (gt2_txusrclk_i),
//-------------- Transmit Ports - TX Driver and OOB signaling --------------
.GT2_GTXTXN_OUT (TXN_OUT[2]),
.GT2_GTXTXP_OUT (TXP_OUT[2]),
//--------- Transmit Ports - TX Elastic Buffer and Phase Alignment ---------
.GT2_TXBUFSTATUS_OUT (gt2_txbufstatus_i),
//--------------------- Transmit Ports - TX PLL Ports ----------------------
.GT2_TXRESETDONE_OUT (gt2_txresetdone_i),
//_____________________________________________________________________
//_____________________________________________________________________
//GT3 (X0Y3)
//----------------------- Channel - Ref Clock Ports ------------------------
.GT3_GTREFCLK0_IN (q0_clk1_refclk_i),
//------------------------------ Channel PLL -------------------------------
.GT3_CPLLFBCLKLOST_OUT (gt3_cpllfbclklost_i),
.GT3_CPLLLOCK_OUT (gt3_cplllock_i),
.GT3_CPLLLOCKDETCLK_IN (drpclk_in_i),
.GT3_CPLLREFCLKLOST_OUT (gt3_cpllrefclklost_i),
.GT3_CPLLRESET_IN (gt3_cpllreset_i),
//----------------------------- Eye Scan Ports -----------------------------
.GT3_EYESCANDATAERROR_OUT (gt3_eyescandataerror_i),
//---------------------- Loopback and Powerdown Ports ----------------------
.GT3_LOOPBACK_IN (gt3_loopback_i),
.GT3_RXPD_IN (gt3_rxpd_i),
.GT3_TXPD_IN (gt3_txpd_i),
//----------------------------- Receive Ports ------------------------------
.GT3_RXUSERRDY_IN (gt3_rxuserrdy_i),
//----------------- Receive Ports - Clock Correction Ports -----------------
.GT3_RXCLKCORCNT_OUT (gt3_rxclkcorcnt_i),
//------------- Receive Ports - Comma Detection and Alignment --------------
.GT3_RXBYTEISALIGNED_OUT (gt3_rxbyteisaligned_i),
.GT3_RXBYTEREALIGN_OUT (gt3_rxbyterealign_i),
.GT3_RXCOMMADET_OUT (gt3_rxcommadet_i),
.GT3_RXSLIDE_IN (gt3_rxslide_i),
//----------------- Receive Ports - RX Data Path interface -----------------
.GT3_GTRXRESET_IN (gt3_gtrxreset_i),
.GT3_RXDATA_OUT (gt3_rxdata_i),
.GT3_RXOUTCLK_OUT (gt3_rxoutclk_i),
.GT3_RXPCSRESET_IN (gt3_rxpcsreset_i),
.GT3_RXUSRCLK_IN (gt2_txusrclk_i),
.GT3_RXUSRCLK2_IN (gt2_txusrclk_i),
//----- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
.GT3_GTXRXN_IN (RXN_IN[3]),
.GT3_GTXRXP_IN (RXP_IN[3]),
.GT3_RXCDRLOCK_OUT (gt3_rxcdrlock_i),
.GT3_RXELECIDLE_OUT (gt3_rxelecidle_i),
//------ Receive Ports - RX Elastic Buffer and Phase Alignment Ports -------
.GT3_RXBUFRESET_IN (gt3_rxbufreset_i),
.GT3_RXBUFSTATUS_OUT (gt3_rxbufstatus_i),
//---------------------- Receive Ports - RX PLL Ports ----------------------
.GT3_RXRESETDONE_OUT (gt3_rxresetdone_i),
//------------ Receive Ports - RX Pipe Control for PCI Express -------------
.GT3_RXVALID_OUT (gt3_rxvalid_i),
//----------------------------- Transmit Ports -----------------------------
.GT3_TXPRECURSORINV_IN (gt3_txprecursorinv_i),
.GT3_TXUSERRDY_IN (gt3_txuserrdy_i),
//---------------- Transmit Ports - TX Data Path interface -----------------
.GT3_GTTXRESET_IN (gt3_gttxreset_i),
.GT3_TXDATA_IN (gt3_txdata_i),
.GT3_TXOUTCLK_OUT (gt3_txoutclk_i),
.GT3_TXOUTCLKFABRIC_OUT (gt3_txoutclkfabric_i),
.GT3_TXOUTCLKPCS_OUT (gt3_txoutclkpcs_i),
.GT3_TXPCSRESET_IN (gt3_txpcsreset_i),
.GT3_TXUSRCLK_IN (gt2_txusrclk_i),
.GT3_TXUSRCLK2_IN (gt2_txusrclk_i),
//-------------- Transmit Ports - TX Driver and OOB signaling --------------
.GT3_GTXTXN_OUT (TXN_OUT[3]),
.GT3_GTXTXP_OUT (TXP_OUT[3]),
//--------- Transmit Ports - TX Elastic Buffer and Phase Alignment ---------
.GT3_TXBUFSTATUS_OUT (gt3_txbufstatus_i),
//--------------------- Transmit Ports - TX PLL Ports ----------------------
.GT3_TXRESETDONE_OUT (gt3_txresetdone_i),
//_____________________________________________________________________
//_____________________________________________________________________
//GT4 (X0Y4)
//----------------------- Channel - Ref Clock Ports ------------------------
.GT4_GTREFCLK0_IN (q1_clk0_refclk_i),
//------------------------------ Channel PLL -------------------------------
.GT4_CPLLFBCLKLOST_OUT (gt4_cpllfbclklost_i),
.GT4_CPLLLOCK_OUT (gt4_cplllock_i),
.GT4_CPLLLOCKDETCLK_IN (drpclk_in_i),
.GT4_CPLLREFCLKLOST_OUT (gt4_cpllrefclklost_i),
.GT4_CPLLRESET_IN (gt4_cpllreset_i),
//----------------------------- Eye Scan Ports -----------------------------
.GT4_EYESCANDATAERROR_OUT (gt4_eyescandataerror_i),
//---------------------- Loopback and Powerdown Ports ----------------------
.GT4_LOOPBACK_IN (gt4_loopback_i),
.GT4_RXPD_IN (gt4_rxpd_i),
.GT4_TXPD_IN (gt4_txpd_i),
//----------------------------- Receive Ports ------------------------------
.GT4_RXUSERRDY_IN (gt4_rxuserrdy_i),
//----------------- Receive Ports - Clock Correction Ports -----------------
.GT4_RXCLKCORCNT_OUT (gt4_rxclkcorcnt_i),
//------------- Receive Ports - Comma Detection and Alignment --------------
.GT4_RXBYTEISALIGNED_OUT (gt4_rxbyteisaligned_i),
.GT4_RXBYTEREALIGN_OUT (gt4_rxbyterealign_i),
.GT4_RXCOMMADET_OUT (gt4_rxcommadet_i),
.GT4_RXSLIDE_IN (gt4_rxslide_i),
//----------------- Receive Ports - RX Data Path interface -----------------
.GT4_GTRXRESET_IN (gt4_gtrxreset_i),
.GT4_RXDATA_OUT (gt4_rxdata_i),
.GT4_RXOUTCLK_OUT (gt4_rxoutclk_i),
.GT4_RXPCSRESET_IN (gt4_rxpcsreset_i),
.GT4_RXUSRCLK_IN (gt4_txusrclk_i),
.GT4_RXUSRCLK2_IN (gt4_txusrclk_i),
//----- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
.GT4_GTXRXN_IN (RXN_IN[4]),
.GT4_GTXRXP_IN (RXP_IN[4]),
.GT4_RXCDRLOCK_OUT (gt4_rxcdrlock_i),
.GT4_RXELECIDLE_OUT (gt4_rxelecidle_i),
//------ Receive Ports - RX Elastic Buffer and Phase Alignment Ports -------
.GT4_RXBUFRESET_IN (gt4_rxbufreset_i),
.GT4_RXBUFSTATUS_OUT (gt4_rxbufstatus_i),
//---------------------- Receive Ports - RX PLL Ports ----------------------
.GT4_RXRESETDONE_OUT (gt4_rxresetdone_i),
//------------ Receive Ports - RX Pipe Control for PCI Express -------------
.GT4_RXVALID_OUT (gt4_rxvalid_i),
//----------------------------- Transmit Ports -----------------------------
.GT4_TXPRECURSORINV_IN (gt4_txprecursorinv_i),
.GT4_TXUSERRDY_IN (gt4_txuserrdy_i),
//---------------- Transmit Ports - TX Data Path interface -----------------
.GT4_GTTXRESET_IN (gt4_gttxreset_i),
.GT4_TXDATA_IN (gt4_txdata_i),
.GT4_TXOUTCLK_OUT (gt4_txoutclk_i),
.GT4_TXOUTCLKFABRIC_OUT (gt4_txoutclkfabric_i),
.GT4_TXOUTCLKPCS_OUT (gt4_txoutclkpcs_i),
.GT4_TXPCSRESET_IN (gt4_txpcsreset_i),
.GT4_TXUSRCLK_IN (gt4_txusrclk_i),
.GT4_TXUSRCLK2_IN (gt4_txusrclk_i),
//-------------- Transmit Ports - TX Driver and OOB signaling --------------
.GT4_GTXTXN_OUT (TXN_OUT[4]),
.GT4_GTXTXP_OUT (TXP_OUT[4]),
//--------- Transmit Ports - TX Elastic Buffer and Phase Alignment ---------
.GT4_TXBUFSTATUS_OUT (gt4_txbufstatus_i),
//--------------------- Transmit Ports - TX PLL Ports ----------------------
.GT4_TXRESETDONE_OUT (gt4_txresetdone_i),
//_____________________________________________________________________
//_____________________________________________________________________
//GT5 (X0Y5)
//----------------------- Channel - Ref Clock Ports ------------------------
.GT5_GTREFCLK0_IN (q1_clk0_refclk_i),
//------------------------------ Channel PLL -------------------------------
.GT5_CPLLFBCLKLOST_OUT (gt5_cpllfbclklost_i),
.GT5_CPLLLOCK_OUT (gt5_cplllock_i),
.GT5_CPLLLOCKDETCLK_IN (drpclk_in_i),
.GT5_CPLLREFCLKLOST_OUT (gt5_cpllrefclklost_i),
.GT5_CPLLRESET_IN (gt5_cpllreset_i),
//----------------------------- Eye Scan Ports -----------------------------
.GT5_EYESCANDATAERROR_OUT (gt5_eyescandataerror_i),
//---------------------- Loopback and Powerdown Ports ----------------------
.GT5_LOOPBACK_IN (gt5_loopback_i),
.GT5_RXPD_IN (gt5_rxpd_i),
.GT5_TXPD_IN (gt5_txpd_i),
//----------------------------- Receive Ports ------------------------------
.GT5_RXUSERRDY_IN (gt5_rxuserrdy_i),
//----------------- Receive Ports - Clock Correction Ports -----------------
.GT5_RXCLKCORCNT_OUT (gt5_rxclkcorcnt_i),
//------------- Receive Ports - Comma Detection and Alignment --------------
.GT5_RXBYTEISALIGNED_OUT (gt5_rxbyteisaligned_i),
.GT5_RXBYTEREALIGN_OUT (gt5_rxbyterealign_i),
.GT5_RXCOMMADET_OUT (gt5_rxcommadet_i),
.GT5_RXSLIDE_IN (gt5_rxslide_i),
//----------------- Receive Ports - RX Data Path interface -----------------
.GT5_GTRXRESET_IN (gt5_gtrxreset_i),
.GT5_RXDATA_OUT (gt5_rxdata_i),
.GT5_RXOUTCLK_OUT (gt5_rxoutclk_i),
.GT5_RXPCSRESET_IN (gt5_rxpcsreset_i),
.GT5_RXUSRCLK_IN (gt4_txusrclk_i),
.GT5_RXUSRCLK2_IN (gt4_txusrclk_i),
//----- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
.GT5_GTXRXN_IN (RXN_IN[5]),
.GT5_GTXRXP_IN (RXP_IN[5]),
.GT5_RXCDRLOCK_OUT (gt5_rxcdrlock_i),
.GT5_RXELECIDLE_OUT (gt5_rxelecidle_i),
//------ Receive Ports - RX Elastic Buffer and Phase Alignment Ports -------
.GT5_RXBUFRESET_IN (gt5_rxbufreset_i),
.GT5_RXBUFSTATUS_OUT (gt5_rxbufstatus_i),
//---------------------- Receive Ports - RX PLL Ports ----------------------
.GT5_RXRESETDONE_OUT (gt5_rxresetdone_i),
//------------ Receive Ports - RX Pipe Control for PCI Express -------------
.GT5_RXVALID_OUT (gt5_rxvalid_i),
//----------------------------- Transmit Ports -----------------------------
.GT5_TXPRECURSORINV_IN (gt5_txprecursorinv_i),
.GT5_TXUSERRDY_IN (gt5_txuserrdy_i),
//---------------- Transmit Ports - TX Data Path interface -----------------
.GT5_GTTXRESET_IN (gt5_gttxreset_i),
.GT5_TXDATA_IN (gt5_txdata_i),
.GT5_TXOUTCLK_OUT (gt5_txoutclk_i),
.GT5_TXOUTCLKFABRIC_OUT (gt5_txoutclkfabric_i),
.GT5_TXOUTCLKPCS_OUT (gt5_txoutclkpcs_i),
.GT5_TXPCSRESET_IN (gt5_txpcsreset_i),
.GT5_TXUSRCLK_IN (gt4_txusrclk_i),
.GT5_TXUSRCLK2_IN (gt4_txusrclk_i),
//-------------- Transmit Ports - TX Driver and OOB signaling --------------
.GT5_GTXTXN_OUT (TXN_OUT[5]),
.GT5_GTXTXP_OUT (TXP_OUT[5]),
//--------- Transmit Ports - TX Elastic Buffer and Phase Alignment ---------
.GT5_TXBUFSTATUS_OUT (gt5_txbufstatus_i),
//--------------------- Transmit Ports - TX PLL Ports ----------------------
.GT5_TXRESETDONE_OUT (gt5_txresetdone_i),
//_____________________________________________________________________
//_____________________________________________________________________
//GT6 (X0Y6)
//----------------------- Channel - Ref Clock Ports ------------------------
.GT6_GTREFCLK0_IN (q1_clk1_refclk_i),
//------------------------------ Channel PLL -------------------------------
.GT6_CPLLFBCLKLOST_OUT (gt6_cpllfbclklost_i),
.GT6_CPLLLOCK_OUT (gt6_cplllock_i),
.GT6_CPLLLOCKDETCLK_IN (drpclk_in_i),
.GT6_CPLLREFCLKLOST_OUT (gt6_cpllrefclklost_i),
.GT6_CPLLRESET_IN (gt6_cpllreset_i),
//----------------------------- Eye Scan Ports -----------------------------
.GT6_EYESCANDATAERROR_OUT (gt6_eyescandataerror_i),
//---------------------- Loopback and Powerdown Ports ----------------------
.GT6_LOOPBACK_IN (gt6_loopback_i),
.GT6_RXPD_IN (gt6_rxpd_i),
.GT6_TXPD_IN (gt6_txpd_i),
//----------------------------- Receive Ports ------------------------------
.GT6_RXUSERRDY_IN (gt6_rxuserrdy_i),
//----------------- Receive Ports - Clock Correction Ports -----------------
.GT6_RXCLKCORCNT_OUT (gt6_rxclkcorcnt_i),
//------------- Receive Ports - Comma Detection and Alignment --------------
.GT6_RXBYTEISALIGNED_OUT (gt6_rxbyteisaligned_i),
.GT6_RXBYTEREALIGN_OUT (gt6_rxbyterealign_i),
.GT6_RXCOMMADET_OUT (gt6_rxcommadet_i),
.GT6_RXSLIDE_IN (gt6_rxslide_i),
//----------------- Receive Ports - RX Data Path interface -----------------
.GT6_GTRXRESET_IN (gt6_gtrxreset_i),
.GT6_RXDATA_OUT (gt6_rxdata_i),
.GT6_RXOUTCLK_OUT (gt6_rxoutclk_i),
.GT6_RXPCSRESET_IN (gt6_rxpcsreset_i),
.GT6_RXUSRCLK_IN (gt6_txusrclk_i),
.GT6_RXUSRCLK2_IN (gt6_txusrclk_i),
//----- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
.GT6_GTXRXN_IN (RXN_IN[6]),
.GT6_GTXRXP_IN (RXP_IN[6]),
.GT6_RXCDRLOCK_OUT (gt6_rxcdrlock_i),
.GT6_RXELECIDLE_OUT (gt6_rxelecidle_i),
//------ Receive Ports - RX Elastic Buffer and Phase Alignment Ports -------
.GT6_RXBUFRESET_IN (gt6_rxbufreset_i),
.GT6_RXBUFSTATUS_OUT (gt6_rxbufstatus_i),
//---------------------- Receive Ports - RX PLL Ports ----------------------
.GT6_RXRESETDONE_OUT (gt6_rxresetdone_i),
//------------ Receive Ports - RX Pipe Control for PCI Express -------------
.GT6_RXVALID_OUT (gt6_rxvalid_i),
//----------------------------- Transmit Ports -----------------------------
.GT6_TXPRECURSORINV_IN (gt6_txprecursorinv_i),
.GT6_TXUSERRDY_IN (gt6_txuserrdy_i),
//---------------- Transmit Ports - TX Data Path interface -----------------
.GT6_GTTXRESET_IN (gt6_gttxreset_i),
.GT6_TXDATA_IN (gt6_txdata_i),
.GT6_TXOUTCLK_OUT (gt6_txoutclk_i),
.GT6_TXOUTCLKFABRIC_OUT (gt6_txoutclkfabric_i),
.GT6_TXOUTCLKPCS_OUT (gt6_txoutclkpcs_i),
.GT6_TXPCSRESET_IN (gt6_txpcsreset_i),
.GT6_TXUSRCLK_IN (gt6_txusrclk_i),
.GT6_TXUSRCLK2_IN (gt6_txusrclk_i),
//-------------- Transmit Ports - TX Driver and OOB signaling --------------
.GT6_GTXTXN_OUT (TXN_OUT[6]),
.GT6_GTXTXP_OUT (TXP_OUT[6]),
//--------- Transmit Ports - TX Elastic Buffer and Phase Alignment ---------
.GT6_TXBUFSTATUS_OUT (gt6_txbufstatus_i),
//--------------------- Transmit Ports - TX PLL Ports ----------------------
.GT6_TXRESETDONE_OUT (gt6_txresetdone_i),
//_____________________________________________________________________
//_____________________________________________________________________
//GT7 (X0Y7)
//----------------------- Channel - Ref Clock Ports ------------------------
.GT7_GTREFCLK0_IN (q1_clk1_refclk_i),
//------------------------------ Channel PLL -------------------------------
.GT7_CPLLFBCLKLOST_OUT (gt7_cpllfbclklost_i),
.GT7_CPLLLOCK_OUT (gt7_cplllock_i),
.GT7_CPLLLOCKDETCLK_IN (drpclk_in_i),
.GT7_CPLLREFCLKLOST_OUT (gt7_cpllrefclklost_i),
.GT7_CPLLRESET_IN (gt7_cpllreset_i),
//----------------------------- Eye Scan Ports -----------------------------
.GT7_EYESCANDATAERROR_OUT (gt7_eyescandataerror_i),
//---------------------- Loopback and Powerdown Ports ----------------------
.GT7_LOOPBACK_IN (gt7_loopback_i),
.GT7_RXPD_IN (gt7_rxpd_i),
.GT7_TXPD_IN (gt7_txpd_i),
//----------------------------- Receive Ports ------------------------------
.GT7_RXUSERRDY_IN (gt7_rxuserrdy_i),
//----------------- Receive Ports - Clock Correction Ports -----------------
.GT7_RXCLKCORCNT_OUT (gt7_rxclkcorcnt_i),
//------------- Receive Ports - Comma Detection and Alignment --------------
.GT7_RXBYTEISALIGNED_OUT (gt7_rxbyteisaligned_i),
.GT7_RXBYTEREALIGN_OUT (gt7_rxbyterealign_i),
.GT7_RXCOMMADET_OUT (gt7_rxcommadet_i),
.GT7_RXSLIDE_IN (gt7_rxslide_i),
//----------------- Receive Ports - RX Data Path interface -----------------
.GT7_GTRXRESET_IN (gt7_gtrxreset_i),
.GT7_RXDATA_OUT (gt7_rxdata_i),
.GT7_RXOUTCLK_OUT (gt7_rxoutclk_i),
.GT7_RXPCSRESET_IN (gt7_rxpcsreset_i),
.GT7_RXUSRCLK_IN (gt6_txusrclk_i),
.GT7_RXUSRCLK2_IN (gt6_txusrclk_i),
//----- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
.GT7_GTXRXN_IN (RXN_IN[7]),
.GT7_GTXRXP_IN (RXP_IN[7]),
.GT7_RXCDRLOCK_OUT (gt7_rxcdrlock_i),
.GT7_RXELECIDLE_OUT (gt7_rxelecidle_i),
//------ Receive Ports - RX Elastic Buffer and Phase Alignment Ports -------
.GT7_RXBUFRESET_IN (gt7_rxbufreset_i),
.GT7_RXBUFSTATUS_OUT (gt7_rxbufstatus_i),
//---------------------- Receive Ports - RX PLL Ports ----------------------
.GT7_RXRESETDONE_OUT (gt7_rxresetdone_i),
//------------ Receive Ports - RX Pipe Control for PCI Express -------------
.GT7_RXVALID_OUT (gt7_rxvalid_i),
//----------------------------- Transmit Ports -----------------------------
.GT7_TXPRECURSORINV_IN (gt7_txprecursorinv_i),
.GT7_TXUSERRDY_IN (gt7_txuserrdy_i),
//---------------- Transmit Ports - TX Data Path interface -----------------
.GT7_GTTXRESET_IN (gt7_gttxreset_i),
.GT7_TXDATA_IN (gt7_txdata_i),
.GT7_TXOUTCLK_OUT (gt7_txoutclk_i),
.GT7_TXOUTCLKFABRIC_OUT (gt7_txoutclkfabric_i),
.GT7_TXOUTCLKPCS_OUT (gt7_txoutclkpcs_i),
.GT7_TXPCSRESET_IN (gt7_txpcsreset_i),
.GT7_TXUSRCLK_IN (gt6_txusrclk_i),
.GT7_TXUSRCLK2_IN (gt6_txusrclk_i),
//-------------- Transmit Ports - TX Driver and OOB signaling --------------
.GT7_GTXTXN_OUT (TXN_OUT[7]),
.GT7_GTXTXP_OUT (TXP_OUT[7]),
//--------- Transmit Ports - TX Elastic Buffer and Phase Alignment ---------
.GT7_TXBUFSTATUS_OUT (gt7_txbufstatus_i),
//--------------------- Transmit Ports - TX PLL Ports ----------------------
.GT7_TXRESETDONE_OUT (gt7_txresetdone_i)
);
//***********************************************************************//
// //
//--------------------------- User Module Resets-------------------------//
// //
//***********************************************************************//
// All the User Modules i.e. FRAME_GEN, FRAME_CHECK and the sync modules
// are held in reset till the RESETDONE goes high.
// The RESETDONE is registered a couple of times on *USRCLK2 and connected
// to the reset of the modules
always @(posedge gt0_txusrclk_i or negedge gt0_rxresetdone_i)
begin
if (!gt0_rxresetdone_i)
begin
gt0_rxresetdone_r <= `DLY 1'b0;
gt0_rxresetdone_r2 <= `DLY 1'b0;
end
else
begin
gt0_rxresetdone_r <= `DLY gt0_rxresetdone_i;
gt0_rxresetdone_r2 <= `DLY gt0_rxresetdone_r;
end
end
always @(posedge gt0_txusrclk_i)
gt0_rxresetdone_r3 <= `DLY gt0_rxresetdone_r2;
always @(posedge gt0_txusrclk_i or negedge gt0_txresetdone_i)
begin
if (!gt0_txresetdone_i)
begin
gt0_txresetdone_r <= `DLY 1'b0;
gt0_txresetdone_r2 <= `DLY 1'b0;
end
else
begin
gt0_txresetdone_r <= `DLY gt0_txresetdone_i;
gt0_txresetdone_r2 <= `DLY gt0_txresetdone_r;
end
end
always @(posedge gt0_txusrclk_i or negedge gt1_rxresetdone_i)
begin
if (!gt1_rxresetdone_i)
begin
gt1_rxresetdone_r <= `DLY 1'b0;
gt1_rxresetdone_r2 <= `DLY 1'b0;
end
else
begin
gt1_rxresetdone_r <= `DLY gt1_rxresetdone_i;
gt1_rxresetdone_r2 <= `DLY gt1_rxresetdone_r;
end
end
always @(posedge gt0_txusrclk_i)
gt1_rxresetdone_r3 <= `DLY gt1_rxresetdone_r2;
always @(posedge gt0_txusrclk_i or negedge gt1_txresetdone_i)
begin
if (!gt1_txresetdone_i)
begin
gt1_txresetdone_r <= `DLY 1'b0;
gt1_txresetdone_r2 <= `DLY 1'b0;
end
else
begin
gt1_txresetdone_r <= `DLY gt1_txresetdone_i;
gt1_txresetdone_r2 <= `DLY gt1_txresetdone_r;
end
end
always @(posedge gt2_txusrclk_i or negedge gt2_rxresetdone_i)
begin
if (!gt2_rxresetdone_i)
begin
gt2_rxresetdone_r <= `DLY 1'b0;
gt2_rxresetdone_r2 <= `DLY 1'b0;
end
else
begin
gt2_rxresetdone_r <= `DLY gt2_rxresetdone_i;
gt2_rxresetdone_r2 <= `DLY gt2_rxresetdone_r;
end
end
always @(posedge gt2_txusrclk_i)
gt2_rxresetdone_r3 <= `DLY gt2_rxresetdone_r2;
always @(posedge gt2_txusrclk_i or negedge gt2_txresetdone_i)
begin
if (!gt2_txresetdone_i)
begin
gt2_txresetdone_r <= `DLY 1'b0;
gt2_txresetdone_r2 <= `DLY 1'b0;
end
else
begin
gt2_txresetdone_r <= `DLY gt2_txresetdone_i;
gt2_txresetdone_r2 <= `DLY gt2_txresetdone_r;
end
end
always @(posedge gt2_txusrclk_i or negedge gt3_rxresetdone_i)
begin
if (!gt3_rxresetdone_i)
begin
gt3_rxresetdone_r <= `DLY 1'b0;
gt3_rxresetdone_r2 <= `DLY 1'b0;
end
else
begin
gt3_rxresetdone_r <= `DLY gt3_rxresetdone_i;
gt3_rxresetdone_r2 <= `DLY gt3_rxresetdone_r;
end
end
always @(posedge gt2_txusrclk_i)
gt3_rxresetdone_r3 <= `DLY gt3_rxresetdone_r2;
always @(posedge gt2_txusrclk_i or negedge gt3_txresetdone_i)
begin
if (!gt3_txresetdone_i)
begin
gt3_txresetdone_r <= `DLY 1'b0;
gt3_txresetdone_r2 <= `DLY 1'b0;
end
else
begin
gt3_txresetdone_r <= `DLY gt3_txresetdone_i;
gt3_txresetdone_r2 <= `DLY gt3_txresetdone_r;
end
end
always @(posedge gt4_txusrclk_i or negedge gt4_rxresetdone_i)
begin
if (!gt4_rxresetdone_i)
begin
gt4_rxresetdone_r <= `DLY 1'b0;
gt4_rxresetdone_r2 <= `DLY 1'b0;
end
else
begin
gt4_rxresetdone_r <= `DLY gt4_rxresetdone_i;
gt4_rxresetdone_r2 <= `DLY gt4_rxresetdone_r;
end
end
always @(posedge gt4_txusrclk_i)
gt4_rxresetdone_r3 <= `DLY gt4_rxresetdone_r2;
always @(posedge gt4_txusrclk_i or negedge gt4_txresetdone_i)
begin
if (!gt4_txresetdone_i)
begin
gt4_txresetdone_r <= `DLY 1'b0;
gt4_txresetdone_r2 <= `DLY 1'b0;
end
else
begin
gt4_txresetdone_r <= `DLY gt4_txresetdone_i;
gt4_txresetdone_r2 <= `DLY gt4_txresetdone_r;
end
end
always @(posedge gt4_txusrclk_i or negedge gt5_rxresetdone_i)
begin
if (!gt5_rxresetdone_i)
begin
gt5_rxresetdone_r <= `DLY 1'b0;
gt5_rxresetdone_r2 <= `DLY 1'b0;
end
else
begin
gt5_rxresetdone_r <= `DLY gt5_rxresetdone_i;
gt5_rxresetdone_r2 <= `DLY gt5_rxresetdone_r;
end
end
always @(posedge gt4_txusrclk_i)
gt5_rxresetdone_r3 <= `DLY gt5_rxresetdone_r2;
always @(posedge gt4_txusrclk_i or negedge gt5_txresetdone_i)
begin
if (!gt5_txresetdone_i)
begin
gt5_txresetdone_r <= `DLY 1'b0;
gt5_txresetdone_r2 <= `DLY 1'b0;
end
else
begin
gt5_txresetdone_r <= `DLY gt5_txresetdone_i;
gt5_txresetdone_r2 <= `DLY gt5_txresetdone_r;
end
end
always @(posedge gt6_txusrclk_i or negedge gt6_rxresetdone_i)
begin
if (!gt6_rxresetdone_i)
begin
gt6_rxresetdone_r <= `DLY 1'b0;
gt6_rxresetdone_r2 <= `DLY 1'b0;
end
else
begin
gt6_rxresetdone_r <= `DLY gt6_rxresetdone_i;
gt6_rxresetdone_r2 <= `DLY gt6_rxresetdone_r;
end
end
always @(posedge gt6_txusrclk_i)
gt6_rxresetdone_r3 <= `DLY gt6_rxresetdone_r2;
always @(posedge gt6_txusrclk_i or negedge gt6_txresetdone_i)
begin
if (!gt6_txresetdone_i)
begin
gt6_txresetdone_r <= `DLY 1'b0;
gt6_txresetdone_r2 <= `DLY 1'b0;
end
else
begin
gt6_txresetdone_r <= `DLY gt6_txresetdone_i;
gt6_txresetdone_r2 <= `DLY gt6_txresetdone_r;
end
end
always @(posedge gt6_txusrclk_i or negedge gt7_rxresetdone_i)
begin
if (!gt7_rxresetdone_i)
begin
gt7_rxresetdone_r <= `DLY 1'b0;
gt7_rxresetdone_r2 <= `DLY 1'b0;
end
else
begin
gt7_rxresetdone_r <= `DLY gt7_rxresetdone_i;
gt7_rxresetdone_r2 <= `DLY gt7_rxresetdone_r;
end
end
always @(posedge gt6_txusrclk_i)
gt7_rxresetdone_r3 <= `DLY gt7_rxresetdone_r2;
always @(posedge gt6_txusrclk_i or negedge gt7_txresetdone_i)
begin
if (!gt7_txresetdone_i)
begin
gt7_txresetdone_r <= `DLY 1'b0;
gt7_txresetdone_r2 <= `DLY 1'b0;
end
else
begin
gt7_txresetdone_r <= `DLY gt7_txresetdone_i;
gt7_txresetdone_r2 <= `DLY gt7_txresetdone_r;
end
end
//***********************************************************************//
// //
//------------------------ Frame Generators ---------------------------//
// //
//***********************************************************************//
// The example design uses Block RAM based frame generators to provide test
// data to the GTs for transmission. By default the frame generators are
// loaded with an incrementing data sequence that includes commas/alignment
// characters for alignment. If your protocol uses channel bonding, the
// frame generator will also be preloaded with a channel bonding sequence.
// You can modify the data transmitted by changing the INIT values of the frame
// generator in this file. Pay careful attention to bit order and the spacing
// of your control and alignment characters.
ROCKETIO_WRAPPER_TILE_GT_FRAME_GEN #
(
.WORDS_IN_BRAM(EXAMPLE_WORDS_IN_BRAM)
)
gt0_frame_gen
(
// User Interface
.TX_DATA_OUT ({gt0_txdata_float_i,gt0_txdata_i,gt0_txdata_float16_i}),
.TXCTRL_OUT (),
// System Interface
.USER_CLK (gt0_txusrclk_i),
.SYSTEM_RESET (gt0_tx_system_reset_c)
);
ROCKETIO_WRAPPER_TILE_GT_FRAME_GEN #
(
.WORDS_IN_BRAM(EXAMPLE_WORDS_IN_BRAM)
)
gt1_frame_gen
(
// User Interface
.TX_DATA_OUT ({gt1_txdata_float_i,gt1_txdata_i,gt1_txdata_float16_i}),
.TXCTRL_OUT (),
// System Interface
.USER_CLK (gt0_txusrclk_i),
.SYSTEM_RESET (gt1_tx_system_reset_c)
);
ROCKETIO_WRAPPER_TILE_GT_FRAME_GEN #
(
.WORDS_IN_BRAM(EXAMPLE_WORDS_IN_BRAM)
)
gt2_frame_gen
(
// User Interface
.TX_DATA_OUT ({gt2_txdata_float_i,gt2_txdata_i,gt2_txdata_float16_i}),
.TXCTRL_OUT (),
// System Interface
.USER_CLK (gt2_txusrclk_i),
.SYSTEM_RESET (gt2_tx_system_reset_c)
);
ROCKETIO_WRAPPER_TILE_GT_FRAME_GEN #
(
.WORDS_IN_BRAM(EXAMPLE_WORDS_IN_BRAM)
)
gt3_frame_gen
(
// User Interface
.TX_DATA_OUT ({gt3_txdata_float_i,gt3_txdata_i,gt3_txdata_float16_i}),
.TXCTRL_OUT (),
// System Interface
.USER_CLK (gt2_txusrclk_i),
.SYSTEM_RESET (gt3_tx_system_reset_c)
);
ROCKETIO_WRAPPER_TILE_GT_FRAME_GEN #
(
.WORDS_IN_BRAM(EXAMPLE_WORDS_IN_BRAM)
)
gt4_frame_gen
(
// User Interface
.TX_DATA_OUT ({gt4_txdata_float_i,gt4_txdata_i,gt4_txdata_float16_i}),
.TXCTRL_OUT (),
// System Interface
.USER_CLK (gt4_txusrclk_i),
.SYSTEM_RESET (gt4_tx_system_reset_c)
);
ROCKETIO_WRAPPER_TILE_GT_FRAME_GEN #
(
.WORDS_IN_BRAM(EXAMPLE_WORDS_IN_BRAM)
)
gt5_frame_gen
(
// User Interface
.TX_DATA_OUT ({gt5_txdata_float_i,gt5_txdata_i,gt5_txdata_float16_i}),
.TXCTRL_OUT (),
// System Interface
.USER_CLK (gt4_txusrclk_i),
.SYSTEM_RESET (gt5_tx_system_reset_c)
);
ROCKETIO_WRAPPER_TILE_GT_FRAME_GEN #
(
.WORDS_IN_BRAM(EXAMPLE_WORDS_IN_BRAM)
)
gt6_frame_gen
(
// User Interface
.TX_DATA_OUT ({gt6_txdata_float_i,gt6_txdata_i,gt6_txdata_float16_i}),
.TXCTRL_OUT (),
// System Interface
.USER_CLK (gt6_txusrclk_i),
.SYSTEM_RESET (gt6_tx_system_reset_c)
);
ROCKETIO_WRAPPER_TILE_GT_FRAME_GEN #
(
.WORDS_IN_BRAM(EXAMPLE_WORDS_IN_BRAM)
)
gt7_frame_gen
(
// User Interface
.TX_DATA_OUT ({gt7_txdata_float_i,gt7_txdata_i,gt7_txdata_float16_i}),
.TXCTRL_OUT (),
// System Interface
.USER_CLK (gt6_txusrclk_i),
.SYSTEM_RESET (gt7_tx_system_reset_c)
);
//***********************************************************************//
// //
//------------------------ Frame Checkers -----------------------------//
// //
//***********************************************************************//
// The example design uses Block RAM based frame checkers to verify incoming
// data. By default the frame generators are loaded with a data sequence that
// matches the outgoing sequence of the frame generators for the TX ports.
// You can modify the expected data sequence by changing the INIT values of the frame
// checkers in this file. Pay careful attention to bit order and the spacing
// of your control and alignment characters.
// When the frame checker receives data, it attempts to synchronise to the
// incoming pattern by looking for the first sequence in the pattern. Once it
// finds the first sequence, it increments through the sequence, and indicates an
// error whenever the next value received does not match the expected value.
assign gt0_frame_check_reset_i = (EXAMPLE_CONFIG_INDEPENDENT_LANES==0)?reset_on_data_error_i:gt0_matchn_i;
// gt0_frame_check0 is always connected to the lane with the start of char
// and this lane starts off the data checking on all the other lanes. The INC_IN port is tied off
assign gt0_inc_in_i = 1'b0;
ROCKETIO_WRAPPER_TILE_GT_FRAME_CHECK #
(
.RX_DATA_WIDTH(16),
.RXCTRL_WIDTH(2),
.WORDS_IN_BRAM(EXAMPLE_WORDS_IN_BRAM),
.START_OF_PACKET_CHAR(16'h027c)
)
gt0_frame_check
(
// GT Interface
.RX_DATA_IN (gt0_rxdata_i),
.RXENMCOMMADET_OUT ( ),
.RXENPCOMMADET_OUT ( ),
// System Interface
.USER_CLK (gt0_txusrclk_i),
.SYSTEM_RESET (gt0_rx_system_reset_c),
.ERROR_COUNT_OUT (gt0_error_count_i),
.RX_SLIDE (gt0_rxslide_i),
.TRACK_DATA_OUT (gt0_track_data_i)
);
assign gt1_frame_check_reset_i = (EXAMPLE_CONFIG_INDEPENDENT_LANES==0)?reset_on_data_error_i:gt1_matchn_i;
// in the "independent lanes" configuration, each of the lanes looks for the unique start char and
// in this case, the INC_IN port is tied off.
// Else, the data checking is triggered by the "master" lane
assign gt1_inc_in_i = (EXAMPLE_CONFIG_INDEPENDENT_LANES==0)?gt0_inc_out_i:1'b0;
ROCKETIO_WRAPPER_TILE_GT_FRAME_CHECK #
(
.RX_DATA_WIDTH(16),
.RXCTRL_WIDTH(2),
.WORDS_IN_BRAM(EXAMPLE_WORDS_IN_BRAM),
.START_OF_PACKET_CHAR(16'h027c)
)
gt1_frame_check
(
// GT Interface
.RX_DATA_IN (gt1_rxdata_i),
.RXENMCOMMADET_OUT ( ),
.RXENPCOMMADET_OUT ( ),
// System Interface
.USER_CLK (gt0_txusrclk_i),
.SYSTEM_RESET (gt1_rx_system_reset_c),
.ERROR_COUNT_OUT (gt1_error_count_i),
.RX_SLIDE (gt1_rxslide_i),
.TRACK_DATA_OUT (gt1_track_data_i)
);
assign gt2_frame_check_reset_i = (EXAMPLE_CONFIG_INDEPENDENT_LANES==0)?reset_on_data_error_i:gt2_matchn_i;
// in the "independent lanes" configuration, each of the lanes looks for the unique start char and
// in this case, the INC_IN port is tied off.
// Else, the data checking is triggered by the "master" lane
assign gt2_inc_in_i = (EXAMPLE_CONFIG_INDEPENDENT_LANES==0)?gt0_inc_out_i:1'b0;
ROCKETIO_WRAPPER_TILE_GT_FRAME_CHECK #
(
.RX_DATA_WIDTH(16),
.RXCTRL_WIDTH(2),
.WORDS_IN_BRAM(EXAMPLE_WORDS_IN_BRAM),
.START_OF_PACKET_CHAR(16'h027c)
)
gt2_frame_check
(
// GT Interface
.RX_DATA_IN (gt2_rxdata_i),
.RXENMCOMMADET_OUT ( ),
.RXENPCOMMADET_OUT ( ),
// System Interface
.USER_CLK (gt2_txusrclk_i),
.SYSTEM_RESET (gt2_rx_system_reset_c),
.ERROR_COUNT_OUT (gt2_error_count_i),
.RX_SLIDE (gt2_rxslide_i),
.TRACK_DATA_OUT (gt2_track_data_i)
);
assign gt3_frame_check_reset_i = (EXAMPLE_CONFIG_INDEPENDENT_LANES==0)?reset_on_data_error_i:gt3_matchn_i;
// in the "independent lanes" configuration, each of the lanes looks for the unique start char and
// in this case, the INC_IN port is tied off.
// Else, the data checking is triggered by the "master" lane
assign gt3_inc_in_i = (EXAMPLE_CONFIG_INDEPENDENT_LANES==0)?gt0_inc_out_i:1'b0;
ROCKETIO_WRAPPER_TILE_GT_FRAME_CHECK #
(
.RX_DATA_WIDTH(16),
.RXCTRL_WIDTH(2),
.WORDS_IN_BRAM(EXAMPLE_WORDS_IN_BRAM),
.START_OF_PACKET_CHAR(16'h027c)
)
gt3_frame_check
(
// GT Interface
.RX_DATA_IN (gt3_rxdata_i),
.RXENMCOMMADET_OUT ( ),
.RXENPCOMMADET_OUT ( ),
// System Interface
.USER_CLK (gt2_txusrclk_i),
.SYSTEM_RESET (gt3_rx_system_reset_c),
.ERROR_COUNT_OUT (gt3_error_count_i),
.RX_SLIDE (gt3_rxslide_i),
.TRACK_DATA_OUT (gt3_track_data_i)
);
assign gt4_frame_check_reset_i = (EXAMPLE_CONFIG_INDEPENDENT_LANES==0)?reset_on_data_error_i:gt4_matchn_i;
// in the "independent lanes" configuration, each of the lanes looks for the unique start char and
// in this case, the INC_IN port is tied off.
// Else, the data checking is triggered by the "master" lane
assign gt4_inc_in_i = (EXAMPLE_CONFIG_INDEPENDENT_LANES==0)?gt0_inc_out_i:1'b0;
ROCKETIO_WRAPPER_TILE_GT_FRAME_CHECK #
(
.RX_DATA_WIDTH(16),
.RXCTRL_WIDTH(2),
.WORDS_IN_BRAM(EXAMPLE_WORDS_IN_BRAM),
.START_OF_PACKET_CHAR(16'h027c)
)
gt4_frame_check
(
// GT Interface
.RX_DATA_IN (gt4_rxdata_i),
.RXENMCOMMADET_OUT ( ),
.RXENPCOMMADET_OUT ( ),
// System Interface
.USER_CLK (gt4_txusrclk_i),
.SYSTEM_RESET (gt4_rx_system_reset_c),
.ERROR_COUNT_OUT (gt4_error_count_i),
.RX_SLIDE (gt4_rxslide_i),
.TRACK_DATA_OUT (gt4_track_data_i)
);
assign gt5_frame_check_reset_i = (EXAMPLE_CONFIG_INDEPENDENT_LANES==0)?reset_on_data_error_i:gt5_matchn_i;
// in the "independent lanes" configuration, each of the lanes looks for the unique start char and
// in this case, the INC_IN port is tied off.
// Else, the data checking is triggered by the "master" lane
assign gt5_inc_in_i = (EXAMPLE_CONFIG_INDEPENDENT_LANES==0)?gt0_inc_out_i:1'b0;
ROCKETIO_WRAPPER_TILE_GT_FRAME_CHECK #
(
.RX_DATA_WIDTH(16),
.RXCTRL_WIDTH(2),
.WORDS_IN_BRAM(EXAMPLE_WORDS_IN_BRAM),
.START_OF_PACKET_CHAR(16'h027c)
)
gt5_frame_check
(
// GT Interface
.RX_DATA_IN (gt5_rxdata_i),
.RXENMCOMMADET_OUT ( ),
.RXENPCOMMADET_OUT ( ),
// System Interface
.USER_CLK (gt4_txusrclk_i),
.SYSTEM_RESET (gt5_rx_system_reset_c),
.ERROR_COUNT_OUT (gt5_error_count_i),
.RX_SLIDE (gt5_rxslide_i),
.TRACK_DATA_OUT (gt5_track_data_i)
);
assign gt6_frame_check_reset_i = (EXAMPLE_CONFIG_INDEPENDENT_LANES==0)?reset_on_data_error_i:gt6_matchn_i;
// in the "independent lanes" configuration, each of the lanes looks for the unique start char and
// in this case, the INC_IN port is tied off.
// Else, the data checking is triggered by the "master" lane
assign gt6_inc_in_i = (EXAMPLE_CONFIG_INDEPENDENT_LANES==0)?gt0_inc_out_i:1'b0;
ROCKETIO_WRAPPER_TILE_GT_FRAME_CHECK #
(
.RX_DATA_WIDTH(16),
.RXCTRL_WIDTH(2),
.WORDS_IN_BRAM(EXAMPLE_WORDS_IN_BRAM),
.START_OF_PACKET_CHAR(16'h027c)
)
gt6_frame_check
(
// GT Interface
.RX_DATA_IN (gt6_rxdata_i),
.RXENMCOMMADET_OUT ( ),
.RXENPCOMMADET_OUT ( ),
// System Interface
.USER_CLK (gt6_txusrclk_i),
.SYSTEM_RESET (gt6_rx_system_reset_c),
.ERROR_COUNT_OUT (gt6_error_count_i),
.RX_SLIDE (gt6_rxslide_i),
.TRACK_DATA_OUT (gt6_track_data_i)
);
assign gt7_frame_check_reset_i = (EXAMPLE_CONFIG_INDEPENDENT_LANES==0)?reset_on_data_error_i:gt7_matchn_i;
// in the "independent lanes" configuration, each of the lanes looks for the unique start char and
// in this case, the INC_IN port is tied off.
// Else, the data checking is triggered by the "master" lane
assign gt7_inc_in_i = (EXAMPLE_CONFIG_INDEPENDENT_LANES==0)?gt0_inc_out_i:1'b0;
ROCKETIO_WRAPPER_TILE_GT_FRAME_CHECK #
(
.RX_DATA_WIDTH(16),
.RXCTRL_WIDTH(2),
.WORDS_IN_BRAM(EXAMPLE_WORDS_IN_BRAM),
.START_OF_PACKET_CHAR(16'h027c)
)
gt7_frame_check
(
// GT Interface
.RX_DATA_IN (gt7_rxdata_i),
.RXENMCOMMADET_OUT ( ),
.RXENPCOMMADET_OUT ( ),
// System Interface
.USER_CLK (gt6_txusrclk_i),
.SYSTEM_RESET (gt7_rx_system_reset_c),
.ERROR_COUNT_OUT (gt7_error_count_i),
.RX_SLIDE (gt7_rxslide_i),
.TRACK_DATA_OUT (gt7_track_data_i)
);
assign TRACK_DATA_OUT = track_data_out_i;
assign track_data_out_i =
gt0_track_data_i &
gt1_track_data_i &
gt2_track_data_i &
gt3_track_data_i &
gt4_track_data_i &
gt5_track_data_i &
gt6_track_data_i &
gt7_track_data_i ;
//-------------------------------------------------------------------------------------
//***********************************************************************//
// //
//--------------------- Chipscope Connections ---------------------------//
// //
//***********************************************************************//
// When the example design is run in hardware, it uses chipscope to allow the
// example design and GT wrapper to be controlled and monitored. The
// EXAMPLE_USE_CHIPSCOPE parameter allows chipscope to be removed for simulation.
generate
if (EXAMPLE_USE_CHIPSCOPE==1)
begin : chipscope
// Shared VIO for all GTs
data_vio shared_vio_i
(
.control (shared_vio_control_i),
.async_in (shared_vio_in_i),
.async_out (shared_vio_out_i),
.sync_in (tied_to_ground_vec_i[31:0]),
.sync_out (),
.clk (tied_to_ground_i)
);
// ICON for all VIOs
icon icon_i
(
.control0 (shared_vio_control_i),
.control1 (tx_data_vio_control_i),
.control2 (rx_data_vio_control_i),
.control3 (ila_control_i)
);
// TX VIO
data_vio tx_data_vio_i
(
.control (tx_data_vio_control_i),
.async_in (tx_data_vio_async_in_i),
.async_out (tx_data_vio_async_out_i),
.sync_in (tx_data_vio_sync_in_i),
.sync_out (tx_data_vio_sync_out_i),
.clk (tx_vio_clk_i)
);
// RX VIO
data_vio rx_data_vio_i
(
.control (rx_data_vio_control_i),
.async_in (rx_data_vio_async_in_i),
.async_out (rx_data_vio_async_out_i),
.sync_in (rx_data_vio_sync_in_i),
.sync_out (rx_data_vio_sync_out_i),
.clk (rx_vio_ila_clk_i)
);
// RX ILA
ila ila_i
(
.control (ila_control_i),
.clk (rx_vio_ila_clk_i),
.trig0 (ila_in_i)
);
// The TX VIO uses GT0's TXUSRCLK2
assign tx_vio_clk_i = gt0_txusrclk_i;
// The RX VIO and ILA uses GT0's RXUSRCLK2
assign rx_vio_ila_clk_i = gt0_txusrclk_i;
// assign resets for frame_gen modules
assign gt0_tx_system_reset_c = !gt0_txresetdone_r2 || user_tx_reset_i;
assign gt1_tx_system_reset_c = !gt1_txresetdone_r2 || user_tx_reset_i;
assign gt2_tx_system_reset_c = !gt2_txresetdone_r2 || user_tx_reset_i;
assign gt3_tx_system_reset_c = !gt3_txresetdone_r2 || user_tx_reset_i;
assign gt4_tx_system_reset_c = !gt4_txresetdone_r2 || user_tx_reset_i;
assign gt5_tx_system_reset_c = !gt5_txresetdone_r2 || user_tx_reset_i;
assign gt6_tx_system_reset_c = !gt6_txresetdone_r2 || user_tx_reset_i;
assign gt7_tx_system_reset_c = !gt7_txresetdone_r2 || user_tx_reset_i;
// assign resets for frame_check modules
assign gt0_rx_system_reset_c = !gt0_rxresetdone_r3 || user_rx_reset_i;
assign gt1_rx_system_reset_c = !gt1_rxresetdone_r3 || user_rx_reset_i;
assign gt2_rx_system_reset_c = !gt2_rxresetdone_r3 || user_rx_reset_i;
assign gt3_rx_system_reset_c = !gt3_rxresetdone_r3 || user_rx_reset_i;
assign gt4_rx_system_reset_c = !gt4_rxresetdone_r3 || user_rx_reset_i;
assign gt5_rx_system_reset_c = !gt5_rxresetdone_r3 || user_rx_reset_i;
assign gt6_rx_system_reset_c = !gt6_rxresetdone_r3 || user_rx_reset_i;
assign gt7_rx_system_reset_c = !gt7_rxresetdone_r3 || user_rx_reset_i;
assign gt0_gtrxreset_i = gtrxreset_i || !gt0_cplllock_i;
assign gt0_gttxreset_i = gttxreset_i || !gt0_cplllock_i;
assign gt1_gtrxreset_i = gtrxreset_i || !gt1_cplllock_i;
assign gt1_gttxreset_i = gttxreset_i || !gt1_cplllock_i;
assign gt2_gtrxreset_i = gtrxreset_i || !gt2_cplllock_i;
assign gt2_gttxreset_i = gttxreset_i || !gt2_cplllock_i;
assign gt3_gtrxreset_i = gtrxreset_i || !gt3_cplllock_i;
assign gt3_gttxreset_i = gttxreset_i || !gt3_cplllock_i;
assign gt4_gtrxreset_i = gtrxreset_i || !gt4_cplllock_i;
assign gt4_gttxreset_i = gttxreset_i || !gt4_cplllock_i;
assign gt5_gtrxreset_i = gtrxreset_i || !gt5_cplllock_i;
assign gt5_gttxreset_i = gttxreset_i || !gt5_cplllock_i;
assign gt6_gtrxreset_i = gtrxreset_i || !gt6_cplllock_i;
assign gt6_gttxreset_i = gttxreset_i || !gt6_cplllock_i;
assign gt7_gtrxreset_i = gtrxreset_i || !gt7_cplllock_i;
assign gt7_gttxreset_i = gttxreset_i || !gt7_cplllock_i;
assign gt0_cpllreset_i = cpllreset_i;
assign gt1_cpllreset_i = cpllreset_i;
assign gt2_cpllreset_i = cpllreset_i;
assign gt3_cpllreset_i = cpllreset_i;
assign gt4_cpllreset_i = cpllreset_i;
assign gt5_cpllreset_i = cpllreset_i;
assign gt6_cpllreset_i = cpllreset_i;
assign gt7_cpllreset_i = cpllreset_i;
// Shared VIO Outputs
assign gttxreset_i = shared_vio_out_i[31];
assign gtrxreset_i = shared_vio_out_i[30];
assign user_tx_reset_i = shared_vio_out_i[29];
assign user_rx_reset_i = shared_vio_out_i[28];
assign mux_sel_i = shared_vio_out_i[27:25];
assign cpllreset_i = shared_vio_out_i[24];
// Shared VIO Inputs
assign shared_vio_in_i[31:0] = 32'b00000000000000000000000000000000;
// Chipscope connections on GT 0
assign gt0_tx_data_vio_async_in_i[31:0] = 32'b00000000000000000000000000000000;
assign gt0_tx_data_vio_sync_in_i[31] = gt0_txresetdone_i;
assign gt0_tx_data_vio_sync_in_i[30:29] = gt0_txbufstatus_i;
assign gt0_tx_data_vio_sync_in_i[28:0] = 29'b00000000000000000000000000000;
assign gt0_loopback_i = tx_data_vio_async_out_i[31:29];
assign gt0_txprecursorinv_i = tx_data_vio_async_out_i[28];
assign gt0_txuserrdy_i = tx_data_vio_sync_out_i[31];
assign gt0_txpd_i = tx_data_vio_sync_out_i[30:29];
assign gt0_rx_data_vio_async_in_i[31:0] = 32'b00000000000000000000000000000000;
assign gt0_rx_data_vio_sync_in_i[31] = gt0_rxresetdone_i;
assign gt0_rx_data_vio_sync_in_i[30:0] = 31'b0000000000000000000000000000000;
assign gt0_rxuserrdy_i = rx_data_vio_async_out_i[31];
assign gt0_rxpd_i = rx_data_vio_async_out_i[30:29];
assign gt0_rxbufreset_i = rx_data_vio_async_out_i[28];
assign gt0_ila_in_i[163:162] = gt0_rxclkcorcnt_i;
assign gt0_ila_in_i[161] = gt0_rxbyteisaligned_i;
assign gt0_ila_in_i[160] = gt0_rxbyterealign_i;
assign gt0_ila_in_i[159] = gt0_rxcommadet_i;
assign gt0_ila_in_i[158:143] = gt0_rxdata_i;
assign gt0_ila_in_i[142:140] = gt0_rxbufstatus_i;
assign gt0_ila_in_i[139] = gt0_rxvalid_i;
assign gt0_ila_in_i[138:131] = gt0_error_count_i;
assign gt0_ila_in_i[130] = gt0_track_data_i;
assign gt0_ila_in_i[129:0] = 130'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
// Chipscope connections on GT 1
assign gt1_tx_data_vio_async_in_i[31:0] = 32'b00000000000000000000000000000000;
assign gt1_tx_data_vio_sync_in_i[31] = gt1_txresetdone_i;
assign gt1_tx_data_vio_sync_in_i[30:29] = gt1_txbufstatus_i;
assign gt1_tx_data_vio_sync_in_i[28:0] = 29'b00000000000000000000000000000;
assign gt1_loopback_i = tx_data_vio_async_out_i[31:29];
assign gt1_txprecursorinv_i = tx_data_vio_async_out_i[28];
assign gt1_txuserrdy_i = tx_data_vio_sync_out_i[31];
assign gt1_txpd_i = tx_data_vio_sync_out_i[30:29];
assign gt1_rx_data_vio_async_in_i[31:0] = 32'b00000000000000000000000000000000;
assign gt1_rx_data_vio_sync_in_i[31] = gt1_rxresetdone_i;
assign gt1_rx_data_vio_sync_in_i[30:0] = 31'b0000000000000000000000000000000;
assign gt1_rxuserrdy_i = rx_data_vio_async_out_i[31];
assign gt1_rxpd_i = rx_data_vio_async_out_i[30:29];
assign gt1_rxbufreset_i = rx_data_vio_async_out_i[28];
assign gt1_ila_in_i[163:162] = gt1_rxclkcorcnt_i;
assign gt1_ila_in_i[161] = gt1_rxbyteisaligned_i;
assign gt1_ila_in_i[160] = gt1_rxbyterealign_i;
assign gt1_ila_in_i[159] = gt1_rxcommadet_i;
assign gt1_ila_in_i[158:143] = gt1_rxdata_i;
assign gt1_ila_in_i[142:140] = gt1_rxbufstatus_i;
assign gt1_ila_in_i[139] = gt1_rxvalid_i;
assign gt1_ila_in_i[138:131] = gt1_error_count_i;
assign gt1_ila_in_i[130] = gt1_track_data_i;
assign gt1_ila_in_i[129:0] = 130'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
// Chipscope connections on GT 2
assign gt2_tx_data_vio_async_in_i[31:0] = 32'b00000000000000000000000000000000;
assign gt2_tx_data_vio_sync_in_i[31] = gt2_txresetdone_i;
assign gt2_tx_data_vio_sync_in_i[30:29] = gt2_txbufstatus_i;
assign gt2_tx_data_vio_sync_in_i[28:0] = 29'b00000000000000000000000000000;
assign gt2_loopback_i = tx_data_vio_async_out_i[31:29];
assign gt2_txprecursorinv_i = tx_data_vio_async_out_i[28];
assign gt2_txuserrdy_i = tx_data_vio_sync_out_i[31];
assign gt2_txpd_i = tx_data_vio_sync_out_i[30:29];
assign gt2_rx_data_vio_async_in_i[31:0] = 32'b00000000000000000000000000000000;
assign gt2_rx_data_vio_sync_in_i[31] = gt2_rxresetdone_i;
assign gt2_rx_data_vio_sync_in_i[30:0] = 31'b0000000000000000000000000000000;
assign gt2_rxuserrdy_i = rx_data_vio_async_out_i[31];
assign gt2_rxpd_i = rx_data_vio_async_out_i[30:29];
assign gt2_rxbufreset_i = rx_data_vio_async_out_i[28];
assign gt2_ila_in_i[163:162] = gt2_rxclkcorcnt_i;
assign gt2_ila_in_i[161] = gt2_rxbyteisaligned_i;
assign gt2_ila_in_i[160] = gt2_rxbyterealign_i;
assign gt2_ila_in_i[159] = gt2_rxcommadet_i;
assign gt2_ila_in_i[158:143] = gt2_rxdata_i;
assign gt2_ila_in_i[142:140] = gt2_rxbufstatus_i;
assign gt2_ila_in_i[139] = gt2_rxvalid_i;
assign gt2_ila_in_i[138:131] = gt2_error_count_i;
assign gt2_ila_in_i[130] = gt2_track_data_i;
assign gt2_ila_in_i[129:0] = 130'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
// Chipscope connections on GT 3
assign gt3_tx_data_vio_async_in_i[31:0] = 32'b00000000000000000000000000000000;
assign gt3_tx_data_vio_sync_in_i[31] = gt3_txresetdone_i;
assign gt3_tx_data_vio_sync_in_i[30:29] = gt3_txbufstatus_i;
assign gt3_tx_data_vio_sync_in_i[28:0] = 29'b00000000000000000000000000000;
assign gt3_loopback_i = tx_data_vio_async_out_i[31:29];
assign gt3_txprecursorinv_i = tx_data_vio_async_out_i[28];
assign gt3_txuserrdy_i = tx_data_vio_sync_out_i[31];
assign gt3_txpd_i = tx_data_vio_sync_out_i[30:29];
assign gt3_rx_data_vio_async_in_i[31:0] = 32'b00000000000000000000000000000000;
assign gt3_rx_data_vio_sync_in_i[31] = gt3_rxresetdone_i;
assign gt3_rx_data_vio_sync_in_i[30:0] = 31'b0000000000000000000000000000000;
assign gt3_rxuserrdy_i = rx_data_vio_async_out_i[31];
assign gt3_rxpd_i = rx_data_vio_async_out_i[30:29];
assign gt3_rxbufreset_i = rx_data_vio_async_out_i[28];
assign gt3_ila_in_i[163:162] = gt3_rxclkcorcnt_i;
assign gt3_ila_in_i[161] = gt3_rxbyteisaligned_i;
assign gt3_ila_in_i[160] = gt3_rxbyterealign_i;
assign gt3_ila_in_i[159] = gt3_rxcommadet_i;
assign gt3_ila_in_i[158:143] = gt3_rxdata_i;
assign gt3_ila_in_i[142:140] = gt3_rxbufstatus_i;
assign gt3_ila_in_i[139] = gt3_rxvalid_i;
assign gt3_ila_in_i[138:131] = gt3_error_count_i;
assign gt3_ila_in_i[130] = gt3_track_data_i;
assign gt3_ila_in_i[129:0] = 130'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
// Chipscope connections on GT 4
assign gt4_tx_data_vio_async_in_i[31:0] = 32'b00000000000000000000000000000000;
assign gt4_tx_data_vio_sync_in_i[31] = gt4_txresetdone_i;
assign gt4_tx_data_vio_sync_in_i[30:29] = gt4_txbufstatus_i;
assign gt4_tx_data_vio_sync_in_i[28:0] = 29'b00000000000000000000000000000;
assign gt4_loopback_i = tx_data_vio_async_out_i[31:29];
assign gt4_txprecursorinv_i = tx_data_vio_async_out_i[28];
assign gt4_txuserrdy_i = tx_data_vio_sync_out_i[31];
assign gt4_txpd_i = tx_data_vio_sync_out_i[30:29];
assign gt4_rx_data_vio_async_in_i[31:0] = 32'b00000000000000000000000000000000;
assign gt4_rx_data_vio_sync_in_i[31] = gt4_rxresetdone_i;
assign gt4_rx_data_vio_sync_in_i[30:0] = 31'b0000000000000000000000000000000;
assign gt4_rxuserrdy_i = rx_data_vio_async_out_i[31];
assign gt4_rxpd_i = rx_data_vio_async_out_i[30:29];
assign gt4_rxbufreset_i = rx_data_vio_async_out_i[28];
assign gt4_ila_in_i[163:162] = gt4_rxclkcorcnt_i;
assign gt4_ila_in_i[161] = gt4_rxbyteisaligned_i;
assign gt4_ila_in_i[160] = gt4_rxbyterealign_i;
assign gt4_ila_in_i[159] = gt4_rxcommadet_i;
assign gt4_ila_in_i[158:143] = gt4_rxdata_i;
assign gt4_ila_in_i[142:140] = gt4_rxbufstatus_i;
assign gt4_ila_in_i[139] = gt4_rxvalid_i;
assign gt4_ila_in_i[138:131] = gt4_error_count_i;
assign gt4_ila_in_i[130] = gt4_track_data_i;
assign gt4_ila_in_i[129:0] = 130'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
// Chipscope connections on GT 5
assign gt5_tx_data_vio_async_in_i[31:0] = 32'b00000000000000000000000000000000;
assign gt5_tx_data_vio_sync_in_i[31] = gt5_txresetdone_i;
assign gt5_tx_data_vio_sync_in_i[30:29] = gt5_txbufstatus_i;
assign gt5_tx_data_vio_sync_in_i[28:0] = 29'b00000000000000000000000000000;
assign gt5_loopback_i = tx_data_vio_async_out_i[31:29];
assign gt5_txprecursorinv_i = tx_data_vio_async_out_i[28];
assign gt5_txuserrdy_i = tx_data_vio_sync_out_i[31];
assign gt5_txpd_i = tx_data_vio_sync_out_i[30:29];
assign gt5_rx_data_vio_async_in_i[31:0] = 32'b00000000000000000000000000000000;
assign gt5_rx_data_vio_sync_in_i[31] = gt5_rxresetdone_i;
assign gt5_rx_data_vio_sync_in_i[30:0] = 31'b0000000000000000000000000000000;
assign gt5_rxuserrdy_i = rx_data_vio_async_out_i[31];
assign gt5_rxpd_i = rx_data_vio_async_out_i[30:29];
assign gt5_rxbufreset_i = rx_data_vio_async_out_i[28];
assign gt5_ila_in_i[163:162] = gt5_rxclkcorcnt_i;
assign gt5_ila_in_i[161] = gt5_rxbyteisaligned_i;
assign gt5_ila_in_i[160] = gt5_rxbyterealign_i;
assign gt5_ila_in_i[159] = gt5_rxcommadet_i;
assign gt5_ila_in_i[158:143] = gt5_rxdata_i;
assign gt5_ila_in_i[142:140] = gt5_rxbufstatus_i;
assign gt5_ila_in_i[139] = gt5_rxvalid_i;
assign gt5_ila_in_i[138:131] = gt5_error_count_i;
assign gt5_ila_in_i[130] = gt5_track_data_i;
assign gt5_ila_in_i[129:0] = 130'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
// Chipscope connections on GT 6
assign gt6_tx_data_vio_async_in_i[31:0] = 32'b00000000000000000000000000000000;
assign gt6_tx_data_vio_sync_in_i[31] = gt6_txresetdone_i;
assign gt6_tx_data_vio_sync_in_i[30:29] = gt6_txbufstatus_i;
assign gt6_tx_data_vio_sync_in_i[28:0] = 29'b00000000000000000000000000000;
assign gt6_loopback_i = tx_data_vio_async_out_i[31:29];
assign gt6_txprecursorinv_i = tx_data_vio_async_out_i[28];
assign gt6_txuserrdy_i = tx_data_vio_sync_out_i[31];
assign gt6_txpd_i = tx_data_vio_sync_out_i[30:29];
assign gt6_rx_data_vio_async_in_i[31:0] = 32'b00000000000000000000000000000000;
assign gt6_rx_data_vio_sync_in_i[31] = gt6_rxresetdone_i;
assign gt6_rx_data_vio_sync_in_i[30:0] = 31'b0000000000000000000000000000000;
assign gt6_rxuserrdy_i = rx_data_vio_async_out_i[31];
assign gt6_rxpd_i = rx_data_vio_async_out_i[30:29];
assign gt6_rxbufreset_i = rx_data_vio_async_out_i[28];
assign gt6_ila_in_i[163:162] = gt6_rxclkcorcnt_i;
assign gt6_ila_in_i[161] = gt6_rxbyteisaligned_i;
assign gt6_ila_in_i[160] = gt6_rxbyterealign_i;
assign gt6_ila_in_i[159] = gt6_rxcommadet_i;
assign gt6_ila_in_i[158:143] = gt6_rxdata_i;
assign gt6_ila_in_i[142:140] = gt6_rxbufstatus_i;
assign gt6_ila_in_i[139] = gt6_rxvalid_i;
assign gt6_ila_in_i[138:131] = gt6_error_count_i;
assign gt6_ila_in_i[130] = gt6_track_data_i;
assign gt6_ila_in_i[129:0] = 130'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
// Chipscope connections on GT 7
assign gt7_tx_data_vio_async_in_i[31:0] = 32'b00000000000000000000000000000000;
assign gt7_tx_data_vio_sync_in_i[31] = gt7_txresetdone_i;
assign gt7_tx_data_vio_sync_in_i[30:29] = gt7_txbufstatus_i;
assign gt7_tx_data_vio_sync_in_i[28:0] = 29'b00000000000000000000000000000;
assign gt7_loopback_i = tx_data_vio_async_out_i[31:29];
assign gt7_txprecursorinv_i = tx_data_vio_async_out_i[28];
assign gt7_txuserrdy_i = tx_data_vio_sync_out_i[31];
assign gt7_txpd_i = tx_data_vio_sync_out_i[30:29];
assign gt7_rx_data_vio_async_in_i[31:0] = 32'b00000000000000000000000000000000;
assign gt7_rx_data_vio_sync_in_i[31] = gt7_rxresetdone_i;
assign gt7_rx_data_vio_sync_in_i[30:0] = 31'b0000000000000000000000000000000;
assign gt7_rxuserrdy_i = rx_data_vio_async_out_i[31];
assign gt7_rxpd_i = rx_data_vio_async_out_i[30:29];
assign gt7_rxbufreset_i = rx_data_vio_async_out_i[28];
assign gt7_ila_in_i[163:162] = gt7_rxclkcorcnt_i;
assign gt7_ila_in_i[161] = gt7_rxbyteisaligned_i;
assign gt7_ila_in_i[160] = gt7_rxbyterealign_i;
assign gt7_ila_in_i[159] = gt7_rxcommadet_i;
assign gt7_ila_in_i[158:143] = gt7_rxdata_i;
assign gt7_ila_in_i[142:140] = gt7_rxbufstatus_i;
assign gt7_ila_in_i[139] = gt7_rxvalid_i;
assign gt7_ila_in_i[138:131] = gt7_error_count_i;
assign gt7_ila_in_i[130] = gt7_track_data_i;
assign gt7_ila_in_i[129:0] = 130'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
assign tx_data_vio_async_in_i = (mux_sel_i == 3'b000)?gt0_tx_data_vio_async_in_i:
(mux_sel_i == 3'b001)?gt1_tx_data_vio_async_in_i:
(mux_sel_i == 3'b010)?gt2_tx_data_vio_async_in_i:
(mux_sel_i == 3'b011)?gt3_tx_data_vio_async_in_i:
(mux_sel_i == 3'b100)?gt4_tx_data_vio_async_in_i:
(mux_sel_i == 3'b101)?gt5_tx_data_vio_async_in_i:
(mux_sel_i == 3'b110)?gt6_tx_data_vio_async_in_i:
gt7_tx_data_vio_async_in_i;
assign tx_data_vio_sync_in_i = (mux_sel_i == 3'b000)?gt0_tx_data_vio_sync_in_i:
(mux_sel_i == 3'b001)?gt1_tx_data_vio_sync_in_i:
(mux_sel_i == 3'b010)?gt2_tx_data_vio_sync_in_i:
(mux_sel_i == 3'b011)?gt3_tx_data_vio_sync_in_i:
(mux_sel_i == 3'b100)?gt4_tx_data_vio_sync_in_i:
(mux_sel_i == 3'b101)?gt5_tx_data_vio_sync_in_i:
(mux_sel_i == 3'b110)?gt6_tx_data_vio_sync_in_i:
gt7_tx_data_vio_sync_in_i;
assign rx_data_vio_async_in_i = (mux_sel_i == 3'b000)?gt0_rx_data_vio_async_in_i:
(mux_sel_i == 3'b001)?gt1_rx_data_vio_async_in_i:
(mux_sel_i == 3'b010)?gt2_rx_data_vio_async_in_i:
(mux_sel_i == 3'b011)?gt3_rx_data_vio_async_in_i:
(mux_sel_i == 3'b100)?gt4_rx_data_vio_async_in_i:
(mux_sel_i == 3'b101)?gt5_rx_data_vio_async_in_i:
(mux_sel_i == 3'b110)?gt6_rx_data_vio_async_in_i:
gt7_rx_data_vio_async_in_i;
assign rx_data_vio_sync_in_i = (mux_sel_i == 3'b000)?gt0_rx_data_vio_sync_in_i:
(mux_sel_i == 3'b001)?gt1_rx_data_vio_sync_in_i:
(mux_sel_i == 3'b010)?gt2_rx_data_vio_sync_in_i:
(mux_sel_i == 3'b011)?gt3_rx_data_vio_sync_in_i:
(mux_sel_i == 3'b100)?gt4_rx_data_vio_sync_in_i:
(mux_sel_i == 3'b101)?gt5_rx_data_vio_sync_in_i:
(mux_sel_i == 3'b110)?gt6_rx_data_vio_sync_in_i:
gt7_rx_data_vio_sync_in_i;
assign ila_in_i = (mux_sel_i == 3'b000)?gt0_ila_in_i:
(mux_sel_i == 3'b001)?gt1_ila_in_i:
(mux_sel_i == 3'b010)?gt2_ila_in_i:
(mux_sel_i == 3'b011)?gt3_ila_in_i:
(mux_sel_i == 3'b100)?gt4_ila_in_i:
(mux_sel_i == 3'b101)?gt5_ila_in_i:
(mux_sel_i == 3'b110)?gt6_ila_in_i:
gt7_ila_in_i;
end //end EXAMPLE_USE_CHIPSCOPE=1 generate section
else
begin: no_chipscope
// If Chipscope is not being used, drive GT reset signal
// from the top level ports
//***********************************************************************//
// //
//--------------------- Reset Logic -----------------------------------//
// //
//***********************************************************************//
// The Example design supports Sequence Mode; hence PCS and PMA resets
// are tied to ground. In Single mode, the user needs to follow the
// reset sequencing given in the user guide.
assign gt0_rxuserrdy_i = gt0_rxuserrdy_r;
assign gt0_txuserrdy_i = gt0_txuserrdy_r;
assign gt1_rxuserrdy_i = gt1_rxuserrdy_r;
assign gt1_txuserrdy_i = gt1_txuserrdy_r;
assign gt2_rxuserrdy_i = gt2_rxuserrdy_r;
assign gt2_txuserrdy_i = gt2_txuserrdy_r;
assign gt3_rxuserrdy_i = gt3_rxuserrdy_r;
assign gt3_txuserrdy_i = gt3_txuserrdy_r;
assign gt4_rxuserrdy_i = gt4_rxuserrdy_r;
assign gt4_txuserrdy_i = gt4_txuserrdy_r;
assign gt5_rxuserrdy_i = gt5_rxuserrdy_r;
assign gt5_txuserrdy_i = gt5_txuserrdy_r;
assign gt6_rxuserrdy_i = gt6_rxuserrdy_r;
assign gt6_txuserrdy_i = gt6_txuserrdy_r;
assign gt7_rxuserrdy_i = gt7_rxuserrdy_r;
assign gt7_txuserrdy_i = gt7_txuserrdy_r;
always @(posedge gt0_txusrclk_i or posedge GTRXRESET_IN)
begin
if(GTRXRESET_IN)
gt0_rxuserrdy_r <= `DLY 1'b0;
else
gt0_rxuserrdy_r <= `DLY gt0_cplllock_i;
end
always @(posedge gt0_txusrclk_i or posedge GTTXRESET_IN)
begin
if(GTTXRESET_IN)
gt0_txuserrdy_r <= `DLY 1'b0;
else
gt0_txuserrdy_r <= `DLY gt0_cplllock_i;
end
always @(posedge gt0_txusrclk_i or posedge GTRXRESET_IN)
begin
if(GTRXRESET_IN)
gt1_rxuserrdy_r <= `DLY 1'b0;
else
gt1_rxuserrdy_r <= `DLY gt1_cplllock_i;
end
always @(posedge gt0_txusrclk_i or posedge GTTXRESET_IN)
begin
if(GTTXRESET_IN)
gt1_txuserrdy_r <= `DLY 1'b0;
else
gt1_txuserrdy_r <= `DLY gt1_cplllock_i;
end
always @(posedge gt2_txusrclk_i or posedge GTRXRESET_IN)
begin
if(GTRXRESET_IN)
gt2_rxuserrdy_r <= `DLY 1'b0;
else
gt2_rxuserrdy_r <= `DLY gt2_cplllock_i;
end
always @(posedge gt2_txusrclk_i or posedge GTTXRESET_IN)
begin
if(GTTXRESET_IN)
gt2_txuserrdy_r <= `DLY 1'b0;
else
gt2_txuserrdy_r <= `DLY gt2_cplllock_i;
end
always @(posedge gt2_txusrclk_i or posedge GTRXRESET_IN)
begin
if(GTRXRESET_IN)
gt3_rxuserrdy_r <= `DLY 1'b0;
else
gt3_rxuserrdy_r <= `DLY gt3_cplllock_i;
end
always @(posedge gt2_txusrclk_i or posedge GTTXRESET_IN)
begin
if(GTTXRESET_IN)
gt3_txuserrdy_r <= `DLY 1'b0;
else
gt3_txuserrdy_r <= `DLY gt3_cplllock_i;
end
always @(posedge gt4_txusrclk_i or posedge GTRXRESET_IN)
begin
if(GTRXRESET_IN)
gt4_rxuserrdy_r <= `DLY 1'b0;
else
gt4_rxuserrdy_r <= `DLY gt4_cplllock_i;
end
always @(posedge gt4_txusrclk_i or posedge GTTXRESET_IN)
begin
if(GTTXRESET_IN)
gt4_txuserrdy_r <= `DLY 1'b0;
else
gt4_txuserrdy_r <= `DLY gt4_cplllock_i;
end
always @(posedge gt4_txusrclk_i or posedge GTRXRESET_IN)
begin
if(GTRXRESET_IN)
gt5_rxuserrdy_r <= `DLY 1'b0;
else
gt5_rxuserrdy_r <= `DLY gt5_cplllock_i;
end
always @(posedge gt4_txusrclk_i or posedge GTTXRESET_IN)
begin
if(GTTXRESET_IN)
gt5_txuserrdy_r <= `DLY 1'b0;
else
gt5_txuserrdy_r <= `DLY gt5_cplllock_i;
end
always @(posedge gt6_txusrclk_i or posedge GTRXRESET_IN)
begin
if(GTRXRESET_IN)
gt6_rxuserrdy_r <= `DLY 1'b0;
else
gt6_rxuserrdy_r <= `DLY gt6_cplllock_i;
end
always @(posedge gt6_txusrclk_i or posedge GTTXRESET_IN)
begin
if(GTTXRESET_IN)
gt6_txuserrdy_r <= `DLY 1'b0;
else
gt6_txuserrdy_r <= `DLY gt6_cplllock_i;
end
always @(posedge gt6_txusrclk_i or posedge GTRXRESET_IN)
begin
if(GTRXRESET_IN)
gt7_rxuserrdy_r <= `DLY 1'b0;
else
gt7_rxuserrdy_r <= `DLY gt7_cplllock_i;
end
always @(posedge gt6_txusrclk_i or posedge GTTXRESET_IN)
begin
if(GTTXRESET_IN)
gt7_txuserrdy_r <= `DLY 1'b0;
else
gt7_txuserrdy_r <= `DLY gt7_cplllock_i;
end
assign gt0_gtrxreset_i = GTRXRESET_IN || !gt0_cplllock_i;
assign gt0_gttxreset_i = GTTXRESET_IN || !gt0_cplllock_i;
assign gt0_cpllreset_i = GTTXRESET_IN;
assign gt1_gtrxreset_i = GTRXRESET_IN || !gt1_cplllock_i;
assign gt1_gttxreset_i = GTTXRESET_IN || !gt1_cplllock_i;
assign gt1_cpllreset_i = GTTXRESET_IN;
assign gt2_gtrxreset_i = GTRXRESET_IN || !gt2_cplllock_i;
assign gt2_gttxreset_i = GTTXRESET_IN || !gt2_cplllock_i;
assign gt2_cpllreset_i = GTTXRESET_IN;
assign gt3_gtrxreset_i = GTRXRESET_IN || !gt3_cplllock_i;
assign gt3_gttxreset_i = GTTXRESET_IN || !gt3_cplllock_i;
assign gt3_cpllreset_i = GTTXRESET_IN;
assign gt4_gtrxreset_i = GTRXRESET_IN || !gt4_cplllock_i;
assign gt4_gttxreset_i = GTTXRESET_IN || !gt4_cplllock_i;
assign gt4_cpllreset_i = GTTXRESET_IN;
assign gt5_gtrxreset_i = GTRXRESET_IN || !gt5_cplllock_i;
assign gt5_gttxreset_i = GTTXRESET_IN || !gt5_cplllock_i;
assign gt5_cpllreset_i = GTTXRESET_IN;
assign gt6_gtrxreset_i = GTRXRESET_IN || !gt6_cplllock_i;
assign gt6_gttxreset_i = GTTXRESET_IN || !gt6_cplllock_i;
assign gt6_cpllreset_i = GTTXRESET_IN;
assign gt7_gtrxreset_i = GTRXRESET_IN || !gt7_cplllock_i;
assign gt7_gttxreset_i = GTTXRESET_IN || !gt7_cplllock_i;
assign gt7_cpllreset_i = GTTXRESET_IN;
assign gt0_rxpcsreset_i = tied_to_ground_i;
assign gt0_txpcsreset_i = tied_to_ground_i;
assign gt1_rxpcsreset_i = tied_to_ground_i;
assign gt1_txpcsreset_i = tied_to_ground_i;
assign gt2_rxpcsreset_i = tied_to_ground_i;
assign gt2_txpcsreset_i = tied_to_ground_i;
assign gt3_rxpcsreset_i = tied_to_ground_i;
assign gt3_txpcsreset_i = tied_to_ground_i;
assign gt4_rxpcsreset_i = tied_to_ground_i;
assign gt4_txpcsreset_i = tied_to_ground_i;
assign gt5_rxpcsreset_i = tied_to_ground_i;
assign gt5_txpcsreset_i = tied_to_ground_i;
assign gt6_rxpcsreset_i = tied_to_ground_i;
assign gt6_txpcsreset_i = tied_to_ground_i;
assign gt7_rxpcsreset_i = tied_to_ground_i;
assign gt7_txpcsreset_i = tied_to_ground_i;
// assign resets for frame_gen modules
assign gt0_tx_system_reset_c = !gt0_txresetdone_r2;
assign gt1_tx_system_reset_c = !gt1_txresetdone_r2;
assign gt2_tx_system_reset_c = !gt2_txresetdone_r2;
assign gt3_tx_system_reset_c = !gt3_txresetdone_r2;
assign gt4_tx_system_reset_c = !gt4_txresetdone_r2;
assign gt5_tx_system_reset_c = !gt5_txresetdone_r2;
assign gt6_tx_system_reset_c = !gt6_txresetdone_r2;
assign gt7_tx_system_reset_c = !gt7_txresetdone_r2;
// assign resets for frame_check modules
assign gt0_rx_system_reset_c = !gt0_rxresetdone_r3;
assign gt1_rx_system_reset_c = !gt1_rxresetdone_r3;
assign gt2_rx_system_reset_c = !gt2_rxresetdone_r3;
assign gt3_rx_system_reset_c = !gt3_rxresetdone_r3;
assign gt4_rx_system_reset_c = !gt4_rxresetdone_r3;
assign gt5_rx_system_reset_c = !gt5_rxresetdone_r3;
assign gt6_rx_system_reset_c = !gt6_rxresetdone_r3;
assign gt7_rx_system_reset_c = !gt7_rxresetdone_r3;
//-------------------------------------------------------------
assign gttxreset_i = tied_to_ground_i;
assign gtrxreset_i = tied_to_ground_i;
assign user_tx_reset_i = tied_to_ground_i;
assign user_rx_reset_i = tied_to_ground_i;
assign mux_sel_i = tied_to_ground_vec_i[2:0];
assign gt0_loopback_i = tied_to_ground_vec_i[2:0];
assign gt0_txprecursorinv_i = tied_to_ground_i;
assign gt0_txpd_i = tied_to_ground_vec_i[1:0];
assign gt0_rxpd_i = tied_to_ground_vec_i[1:0];
assign gt0_rxbufreset_i = tied_to_ground_i;
assign gt1_loopback_i = tied_to_ground_vec_i[2:0];
assign gt1_txprecursorinv_i = tied_to_ground_i;
assign gt1_txpd_i = tied_to_ground_vec_i[1:0];
assign gt1_rxpd_i = tied_to_ground_vec_i[1:0];
assign gt1_rxbufreset_i = tied_to_ground_i;
assign gt2_loopback_i = tied_to_ground_vec_i[2:0];
assign gt2_txprecursorinv_i = tied_to_ground_i;
assign gt2_txpd_i = tied_to_ground_vec_i[1:0];
assign gt2_rxpd_i = tied_to_ground_vec_i[1:0];
assign gt2_rxbufreset_i = tied_to_ground_i;
assign gt3_loopback_i = tied_to_ground_vec_i[2:0];
assign gt3_txprecursorinv_i = tied_to_ground_i;
assign gt3_txpd_i = tied_to_ground_vec_i[1:0];
assign gt3_rxpd_i = tied_to_ground_vec_i[1:0];
assign gt3_rxbufreset_i = tied_to_ground_i;
assign gt4_loopback_i = tied_to_ground_vec_i[2:0];
assign gt4_txprecursorinv_i = tied_to_ground_i;
assign gt4_txpd_i = tied_to_ground_vec_i[1:0];
assign gt4_rxpd_i = tied_to_ground_vec_i[1:0];
assign gt4_rxbufreset_i = tied_to_ground_i;
assign gt5_loopback_i = tied_to_ground_vec_i[2:0];
assign gt5_txprecursorinv_i = tied_to_ground_i;
assign gt5_txpd_i = tied_to_ground_vec_i[1:0];
assign gt5_rxpd_i = tied_to_ground_vec_i[1:0];
assign gt5_rxbufreset_i = tied_to_ground_i;
assign gt6_loopback_i = tied_to_ground_vec_i[2:0];
assign gt6_txprecursorinv_i = tied_to_ground_i;
assign gt6_txpd_i = tied_to_ground_vec_i[1:0];
assign gt6_rxpd_i = tied_to_ground_vec_i[1:0];
assign gt6_rxbufreset_i = tied_to_ground_i;
assign gt7_loopback_i = tied_to_ground_vec_i[2:0];
assign gt7_txprecursorinv_i = tied_to_ground_i;
assign gt7_txpd_i = tied_to_ground_vec_i[1:0];
assign gt7_rxpd_i = tied_to_ground_vec_i[1:0];
assign gt7_rxbufreset_i = tied_to_ground_i;
end
endgenerate //End generate for EXAMPLE_USE_CHIPSCOPE
endmodule
|
module data_vio
(
control,
clk,
async_in,
async_out,
sync_in,
sync_out
);
inout [35:0] control;
input clk;
input [31:0] async_in;
output [31:0] async_out;
input [31:0] sync_in;
output [31:0] sync_out;
endmodule
|
module icon
(
control0,
control1,
control2,
control3
);
inout [35:0] control0;
inout [35:0] control1;
inout [35:0] control2;
inout [35:0] control3;
endmodule
|
module ila
(
control,
clk,
trig0
);
inout [35:0] control;
input clk ;
input [163:0] trig0 ;
endmodule
|
module VexRiscv (
input [31:0] externalResetVector,
input timerInterrupt,
input softwareInterrupt,
input [31:0] externalInterruptArray,
input debug_bus_cmd_valid,
output reg debug_bus_cmd_ready,
input debug_bus_cmd_payload_wr,
input [7:0] debug_bus_cmd_payload_address,
input [31:0] debug_bus_cmd_payload_data,
output reg [31:0] debug_bus_rsp_data,
output debug_resetOut,
output CfuPlugin_bus_cmd_valid,
input CfuPlugin_bus_cmd_ready,
output [9:0] CfuPlugin_bus_cmd_payload_function_id,
output [31:0] CfuPlugin_bus_cmd_payload_inputs_0,
output [31:0] CfuPlugin_bus_cmd_payload_inputs_1,
input CfuPlugin_bus_rsp_valid,
output CfuPlugin_bus_rsp_ready,
input [31:0] CfuPlugin_bus_rsp_payload_outputs_0,
output reg iBusWishbone_CYC,
output reg iBusWishbone_STB,
input iBusWishbone_ACK,
output iBusWishbone_WE,
output [29:0] iBusWishbone_ADR,
input [31:0] iBusWishbone_DAT_MISO,
output [31:0] iBusWishbone_DAT_MOSI,
output [3:0] iBusWishbone_SEL,
input iBusWishbone_ERR,
output [2:0] iBusWishbone_CTI,
output [1:0] iBusWishbone_BTE,
output dBusWishbone_CYC,
output dBusWishbone_STB,
input dBusWishbone_ACK,
output dBusWishbone_WE,
output [29:0] dBusWishbone_ADR,
input [31:0] dBusWishbone_DAT_MISO,
output [31:0] dBusWishbone_DAT_MOSI,
output [3:0] dBusWishbone_SEL,
input dBusWishbone_ERR,
output [2:0] dBusWishbone_CTI,
output [1:0] dBusWishbone_BTE,
input clk,
input reset,
input debugReset
);
wire IBusCachedPlugin_cache_io_flush;
wire IBusCachedPlugin_cache_io_cpu_prefetch_isValid;
wire IBusCachedPlugin_cache_io_cpu_fetch_isValid;
wire IBusCachedPlugin_cache_io_cpu_fetch_isStuck;
wire IBusCachedPlugin_cache_io_cpu_fetch_isRemoved;
wire IBusCachedPlugin_cache_io_cpu_decode_isValid;
wire IBusCachedPlugin_cache_io_cpu_decode_isStuck;
wire IBusCachedPlugin_cache_io_cpu_decode_isUser;
reg IBusCachedPlugin_cache_io_cpu_fill_valid;
wire dataCache_1_io_cpu_execute_isValid;
wire [31:0] dataCache_1_io_cpu_execute_address;
wire dataCache_1_io_cpu_memory_isValid;
wire [31:0] dataCache_1_io_cpu_memory_address;
reg dataCache_1_io_cpu_memory_mmuRsp_isIoAccess;
reg dataCache_1_io_cpu_writeBack_isValid;
wire dataCache_1_io_cpu_writeBack_isUser;
wire [31:0] dataCache_1_io_cpu_writeBack_storeData;
wire [31:0] dataCache_1_io_cpu_writeBack_address;
wire dataCache_1_io_cpu_writeBack_fence_SW;
wire dataCache_1_io_cpu_writeBack_fence_SR;
wire dataCache_1_io_cpu_writeBack_fence_SO;
wire dataCache_1_io_cpu_writeBack_fence_SI;
wire dataCache_1_io_cpu_writeBack_fence_PW;
wire dataCache_1_io_cpu_writeBack_fence_PR;
wire dataCache_1_io_cpu_writeBack_fence_PO;
wire dataCache_1_io_cpu_writeBack_fence_PI;
wire [3:0] dataCache_1_io_cpu_writeBack_fence_FM;
wire dataCache_1_io_cpu_flush_valid;
wire dataCache_1_io_mem_cmd_ready;
reg [31:0] _zz_RegFilePlugin_regFile_port0;
reg [31:0] _zz_RegFilePlugin_regFile_port1;
wire IBusCachedPlugin_cache_io_cpu_prefetch_haltIt;
wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_data;
wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress;
wire IBusCachedPlugin_cache_io_cpu_decode_error;
wire IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling;
wire IBusCachedPlugin_cache_io_cpu_decode_mmuException;
wire [31:0] IBusCachedPlugin_cache_io_cpu_decode_data;
wire IBusCachedPlugin_cache_io_cpu_decode_cacheMiss;
wire [31:0] IBusCachedPlugin_cache_io_cpu_decode_physicalAddress;
wire IBusCachedPlugin_cache_io_mem_cmd_valid;
wire [31:0] IBusCachedPlugin_cache_io_mem_cmd_payload_address;
wire [2:0] IBusCachedPlugin_cache_io_mem_cmd_payload_size;
wire dataCache_1_io_cpu_execute_haltIt;
wire dataCache_1_io_cpu_execute_refilling;
wire dataCache_1_io_cpu_memory_isWrite;
wire dataCache_1_io_cpu_writeBack_haltIt;
wire [31:0] dataCache_1_io_cpu_writeBack_data;
wire dataCache_1_io_cpu_writeBack_mmuException;
wire dataCache_1_io_cpu_writeBack_unalignedAccess;
wire dataCache_1_io_cpu_writeBack_accessError;
wire dataCache_1_io_cpu_writeBack_isWrite;
wire dataCache_1_io_cpu_writeBack_keepMemRspData;
wire dataCache_1_io_cpu_writeBack_exclusiveOk;
wire dataCache_1_io_cpu_flush_ready;
wire dataCache_1_io_cpu_redo;
wire dataCache_1_io_mem_cmd_valid;
wire dataCache_1_io_mem_cmd_payload_wr;
wire dataCache_1_io_mem_cmd_payload_uncached;
wire [31:0] dataCache_1_io_mem_cmd_payload_address;
wire [31:0] dataCache_1_io_mem_cmd_payload_data;
wire [3:0] dataCache_1_io_mem_cmd_payload_mask;
wire [2:0] dataCache_1_io_mem_cmd_payload_size;
wire dataCache_1_io_mem_cmd_payload_last;
wire [51:0] _zz_memory_MUL_LOW;
wire [51:0] _zz_memory_MUL_LOW_1;
wire [51:0] _zz_memory_MUL_LOW_2;
wire [51:0] _zz_memory_MUL_LOW_3;
wire [32:0] _zz_memory_MUL_LOW_4;
wire [51:0] _zz_memory_MUL_LOW_5;
wire [49:0] _zz_memory_MUL_LOW_6;
wire [51:0] _zz_memory_MUL_LOW_7;
wire [49:0] _zz_memory_MUL_LOW_8;
wire [31:0] _zz_execute_SHIFT_RIGHT;
wire [32:0] _zz_execute_SHIFT_RIGHT_1;
wire [32:0] _zz_execute_SHIFT_RIGHT_2;
wire [31:0] _zz_decode_LEGAL_INSTRUCTION;
wire [31:0] _zz_decode_LEGAL_INSTRUCTION_1;
wire [31:0] _zz_decode_LEGAL_INSTRUCTION_2;
wire _zz_decode_LEGAL_INSTRUCTION_3;
wire [0:0] _zz_decode_LEGAL_INSTRUCTION_4;
wire [14:0] _zz_decode_LEGAL_INSTRUCTION_5;
wire [31:0] _zz_decode_LEGAL_INSTRUCTION_6;
wire [31:0] _zz_decode_LEGAL_INSTRUCTION_7;
wire [31:0] _zz_decode_LEGAL_INSTRUCTION_8;
wire _zz_decode_LEGAL_INSTRUCTION_9;
wire [0:0] _zz_decode_LEGAL_INSTRUCTION_10;
wire [8:0] _zz_decode_LEGAL_INSTRUCTION_11;
wire [31:0] _zz_decode_LEGAL_INSTRUCTION_12;
wire [31:0] _zz_decode_LEGAL_INSTRUCTION_13;
wire [31:0] _zz_decode_LEGAL_INSTRUCTION_14;
wire _zz_decode_LEGAL_INSTRUCTION_15;
wire [0:0] _zz_decode_LEGAL_INSTRUCTION_16;
wire [2:0] _zz_decode_LEGAL_INSTRUCTION_17;
wire [3:0] _zz__zz_IBusCachedPlugin_jump_pcLoad_payload_1;
reg [31:0] _zz_IBusCachedPlugin_jump_pcLoad_payload_5;
wire [1:0] _zz_IBusCachedPlugin_jump_pcLoad_payload_6;
wire [31:0] _zz_IBusCachedPlugin_fetchPc_pc;
wire [2:0] _zz_IBusCachedPlugin_fetchPc_pc_1;
wire [11:0] _zz__zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch;
wire [31:0] _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_2;
wire [19:0] _zz__zz_2;
wire [11:0] _zz__zz_4;
wire [31:0] _zz__zz_6;
wire [31:0] _zz__zz_6_1;
wire [19:0] _zz__zz_IBusCachedPlugin_predictionJumpInterface_payload;
wire [11:0] _zz__zz_IBusCachedPlugin_predictionJumpInterface_payload_2;
wire _zz_IBusCachedPlugin_predictionJumpInterface_payload_4;
wire _zz_IBusCachedPlugin_predictionJumpInterface_payload_5;
wire _zz_IBusCachedPlugin_predictionJumpInterface_payload_6;
wire [2:0] _zz_DBusCachedPlugin_exceptionBus_payload_code;
wire [2:0] _zz_DBusCachedPlugin_exceptionBus_payload_code_1;
reg [7:0] _zz_writeBack_DBusCachedPlugin_rspShifted;
wire [1:0] _zz_writeBack_DBusCachedPlugin_rspShifted_1;
reg [7:0] _zz_writeBack_DBusCachedPlugin_rspShifted_2;
wire [0:0] _zz_writeBack_DBusCachedPlugin_rspShifted_3;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_1;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_2;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_3;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_4;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_5;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_6;
wire [27:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_7;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_8;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_9;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_10;
wire [1:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_11;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_12;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_13;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_14;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_15;
wire [1:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_16;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_17;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_18;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_19;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_20;
wire [22:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_21;
wire [1:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_22;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_23;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_24;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_25;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_26;
wire [1:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_27;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_28;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_29;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_30;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_31;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_32;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_33;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_34;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_35;
wire [19:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_36;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_37;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_38;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_39;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_40;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_41;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_42;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_43;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_44;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_45;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_46;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_47;
wire [16:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_48;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_49;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_50;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_51;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_52;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_53;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_54;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_55;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_56;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_57;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_58;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_59;
wire [3:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_60;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_61;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_62;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_63;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_64;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_65;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_66;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_67;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_68;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_69;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_70;
wire [13:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_71;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_72;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_73;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_74;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_75;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_76;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_77;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_78;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_79;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_80;
wire [3:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_81;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_82;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_83;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_84;
wire [1:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_85;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_86;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_87;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_88;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_89;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_90;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_91;
wire [3:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_92;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_93;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_94;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_95;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_96;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_97;
wire [1:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_98;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_99;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_100;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_101;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_102;
wire [10:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_103;
wire [5:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_104;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_105;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_106;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_107;
wire [3:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_108;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_109;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_110;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_111;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_112;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_113;
wire [1:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_114;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_115;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_116;
wire [5:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_117;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_118;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_119;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_120;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_121;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_122;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_123;
wire [1:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_124;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_125;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_126;
wire [1:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_127;
wire [7:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_128;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_129;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_130;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_131;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_132;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_133;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_134;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_135;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_136;
wire [5:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_137;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_138;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_139;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_140;
wire [2:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_141;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_142;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_143;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_144;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_145;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_146;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_147;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_148;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_149;
wire [3:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_150;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_151;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_152;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_153;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_154;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_155;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_156;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_157;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_158;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_159;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_160;
wire [1:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_161;
wire [1:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_162;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_163;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_164;
wire [1:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_165;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_166;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_167;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_168;
wire _zz_RegFilePlugin_regFile_port;
wire _zz_decode_RegFilePlugin_rs1Data;
wire _zz_RegFilePlugin_regFile_port_1;
wire _zz_decode_RegFilePlugin_rs2Data;
wire [0:0] _zz__zz_execute_REGFILE_WRITE_DATA;
wire [2:0] _zz__zz_execute_SRC1;
wire [4:0] _zz__zz_execute_SRC1_1;
wire [11:0] _zz__zz_execute_SRC2_3;
wire [31:0] _zz_execute_SrcPlugin_addSub;
wire [31:0] _zz_execute_SrcPlugin_addSub_1;
wire [31:0] _zz_execute_SrcPlugin_addSub_2;
wire [31:0] _zz_execute_SrcPlugin_addSub_3;
wire [31:0] _zz_execute_SrcPlugin_addSub_4;
wire [31:0] _zz_execute_SrcPlugin_addSub_5;
wire [31:0] _zz_execute_SrcPlugin_addSub_6;
wire [19:0] _zz__zz_execute_BranchPlugin_missAlignedTarget_2;
wire [11:0] _zz__zz_execute_BranchPlugin_missAlignedTarget_4;
wire [31:0] _zz__zz_execute_BranchPlugin_missAlignedTarget_6;
wire [31:0] _zz__zz_execute_BranchPlugin_missAlignedTarget_6_1;
wire [31:0] _zz__zz_execute_BranchPlugin_missAlignedTarget_6_2;
wire [19:0] _zz__zz_execute_BranchPlugin_branch_src2_2;
wire [11:0] _zz__zz_execute_BranchPlugin_branch_src2_4;
wire _zz_execute_BranchPlugin_branch_src2_6;
wire _zz_execute_BranchPlugin_branch_src2_7;
wire _zz_execute_BranchPlugin_branch_src2_8;
wire [2:0] _zz_execute_BranchPlugin_branch_src2_9;
wire [1:0] _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1;
wire [1:0] _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1_1;
wire [1:0] _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_3;
wire [1:0] _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_3_1;
wire _zz_when;
wire _zz_when_1;
wire [65:0] _zz_writeBack_MulPlugin_result;
wire [65:0] _zz_writeBack_MulPlugin_result_1;
wire [31:0] _zz__zz_decode_RS2_2;
wire [31:0] _zz__zz_decode_RS2_2_1;
wire [5:0] _zz_memory_DivPlugin_div_counter_valueNext;
wire [0:0] _zz_memory_DivPlugin_div_counter_valueNext_1;
wire [32:0] _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator;
wire [31:0] _zz_memory_DivPlugin_div_stage_0_outRemainder;
wire [31:0] _zz_memory_DivPlugin_div_stage_0_outRemainder_1;
wire [32:0] _zz_memory_DivPlugin_div_stage_0_outNumerator;
wire [32:0] _zz_memory_DivPlugin_div_result_1;
wire [32:0] _zz_memory_DivPlugin_div_result_2;
wire [32:0] _zz_memory_DivPlugin_div_result_3;
wire [32:0] _zz_memory_DivPlugin_div_result_4;
wire [0:0] _zz_memory_DivPlugin_div_result_5;
wire [32:0] _zz_memory_DivPlugin_rs1_2;
wire [0:0] _zz_memory_DivPlugin_rs1_3;
wire [31:0] _zz_memory_DivPlugin_rs2_1;
wire [0:0] _zz_memory_DivPlugin_rs2_2;
wire [9:0] _zz_execute_CfuPlugin_functionsIds_0;
wire [31:0] _zz_CsrPlugin_csrMapping_readDataInit_25;
wire [26:0] _zz_iBusWishbone_ADR_1;
wire [51:0] memory_MUL_LOW;
wire writeBack_CfuPlugin_CFU_IN_FLIGHT;
wire execute_CfuPlugin_CFU_IN_FLIGHT;
wire [33:0] memory_MUL_HH;
wire [33:0] execute_MUL_HH;
wire [33:0] execute_MUL_HL;
wire [33:0] execute_MUL_LH;
wire [31:0] execute_MUL_LL;
wire [31:0] execute_SHIFT_RIGHT;
wire [31:0] execute_REGFILE_WRITE_DATA;
wire [31:0] memory_MEMORY_STORE_DATA_RF;
wire [31:0] execute_MEMORY_STORE_DATA_RF;
wire decode_DO_EBREAK;
wire decode_CSR_READ_OPCODE;
wire decode_CSR_WRITE_OPCODE;
wire decode_PREDICTION_HAD_BRANCHED2;
wire decode_SRC2_FORCE_ZERO;
wire `Input2Kind_binary_sequential_type decode_CfuPlugin_CFU_INPUT_2_KIND;
wire `Input2Kind_binary_sequential_type _zz_decode_CfuPlugin_CFU_INPUT_2_KIND;
wire `Input2Kind_binary_sequential_type _zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND;
wire `Input2Kind_binary_sequential_type _zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_1;
wire decode_CfuPlugin_CFU_ENABLE;
wire decode_IS_RS2_SIGNED;
wire decode_IS_RS1_SIGNED;
wire decode_IS_DIV;
wire memory_IS_MUL;
wire execute_IS_MUL;
wire decode_IS_MUL;
wire `EnvCtrlEnum_binary_sequential_type _zz_memory_to_writeBack_ENV_CTRL;
wire `EnvCtrlEnum_binary_sequential_type _zz_memory_to_writeBack_ENV_CTRL_1;
wire `EnvCtrlEnum_binary_sequential_type _zz_execute_to_memory_ENV_CTRL;
wire `EnvCtrlEnum_binary_sequential_type _zz_execute_to_memory_ENV_CTRL_1;
wire `EnvCtrlEnum_binary_sequential_type decode_ENV_CTRL;
wire `EnvCtrlEnum_binary_sequential_type _zz_decode_ENV_CTRL;
wire `EnvCtrlEnum_binary_sequential_type _zz_decode_to_execute_ENV_CTRL;
wire `EnvCtrlEnum_binary_sequential_type _zz_decode_to_execute_ENV_CTRL_1;
wire decode_IS_CSR;
wire `BranchCtrlEnum_binary_sequential_type _zz_decode_to_execute_BRANCH_CTRL;
wire `BranchCtrlEnum_binary_sequential_type _zz_decode_to_execute_BRANCH_CTRL_1;
wire `ShiftCtrlEnum_binary_sequential_type _zz_execute_to_memory_SHIFT_CTRL;
wire `ShiftCtrlEnum_binary_sequential_type _zz_execute_to_memory_SHIFT_CTRL_1;
wire `ShiftCtrlEnum_binary_sequential_type decode_SHIFT_CTRL;
wire `ShiftCtrlEnum_binary_sequential_type _zz_decode_SHIFT_CTRL;
wire `ShiftCtrlEnum_binary_sequential_type _zz_decode_to_execute_SHIFT_CTRL;
wire `ShiftCtrlEnum_binary_sequential_type _zz_decode_to_execute_SHIFT_CTRL_1;
wire `AluBitwiseCtrlEnum_binary_sequential_type decode_ALU_BITWISE_CTRL;
wire `AluBitwiseCtrlEnum_binary_sequential_type _zz_decode_ALU_BITWISE_CTRL;
wire `AluBitwiseCtrlEnum_binary_sequential_type _zz_decode_to_execute_ALU_BITWISE_CTRL;
wire `AluBitwiseCtrlEnum_binary_sequential_type _zz_decode_to_execute_ALU_BITWISE_CTRL_1;
wire decode_SRC_LESS_UNSIGNED;
wire decode_MEMORY_MANAGMENT;
wire memory_MEMORY_WR;
wire decode_MEMORY_WR;
wire execute_BYPASSABLE_MEMORY_STAGE;
wire decode_BYPASSABLE_MEMORY_STAGE;
wire decode_BYPASSABLE_EXECUTE_STAGE;
wire `Src2CtrlEnum_binary_sequential_type decode_SRC2_CTRL;
wire `Src2CtrlEnum_binary_sequential_type _zz_decode_SRC2_CTRL;
wire `Src2CtrlEnum_binary_sequential_type _zz_decode_to_execute_SRC2_CTRL;
wire `Src2CtrlEnum_binary_sequential_type _zz_decode_to_execute_SRC2_CTRL_1;
wire `AluCtrlEnum_binary_sequential_type decode_ALU_CTRL;
wire `AluCtrlEnum_binary_sequential_type _zz_decode_ALU_CTRL;
wire `AluCtrlEnum_binary_sequential_type _zz_decode_to_execute_ALU_CTRL;
wire `AluCtrlEnum_binary_sequential_type _zz_decode_to_execute_ALU_CTRL_1;
wire `Src1CtrlEnum_binary_sequential_type decode_SRC1_CTRL;
wire `Src1CtrlEnum_binary_sequential_type _zz_decode_SRC1_CTRL;
wire `Src1CtrlEnum_binary_sequential_type _zz_decode_to_execute_SRC1_CTRL;
wire `Src1CtrlEnum_binary_sequential_type _zz_decode_to_execute_SRC1_CTRL_1;
wire decode_MEMORY_FORCE_CONSTISTENCY;
wire [31:0] writeBack_FORMAL_PC_NEXT;
wire [31:0] memory_FORMAL_PC_NEXT;
wire [31:0] execute_FORMAL_PC_NEXT;
wire [31:0] decode_FORMAL_PC_NEXT;
wire [31:0] memory_PC;
reg _zz_memory_to_writeBack_CfuPlugin_CFU_IN_FLIGHT;
reg _zz_execute_to_memory_CfuPlugin_CFU_IN_FLIGHT;
wire memory_CfuPlugin_CFU_IN_FLIGHT;
wire `Input2Kind_binary_sequential_type execute_CfuPlugin_CFU_INPUT_2_KIND;
wire `Input2Kind_binary_sequential_type _zz_execute_CfuPlugin_CFU_INPUT_2_KIND;
wire execute_CfuPlugin_CFU_ENABLE;
wire execute_DO_EBREAK;
wire decode_IS_EBREAK;
wire execute_IS_RS1_SIGNED;
wire execute_IS_DIV;
wire execute_IS_RS2_SIGNED;
wire memory_IS_DIV;
wire writeBack_IS_MUL;
wire [33:0] writeBack_MUL_HH;
wire [51:0] writeBack_MUL_LOW;
wire [33:0] memory_MUL_HL;
wire [33:0] memory_MUL_LH;
wire [31:0] memory_MUL_LL;
wire execute_CSR_READ_OPCODE;
wire execute_CSR_WRITE_OPCODE;
wire execute_IS_CSR;
wire `EnvCtrlEnum_binary_sequential_type memory_ENV_CTRL;
wire `EnvCtrlEnum_binary_sequential_type _zz_memory_ENV_CTRL;
wire `EnvCtrlEnum_binary_sequential_type execute_ENV_CTRL;
wire `EnvCtrlEnum_binary_sequential_type _zz_execute_ENV_CTRL;
wire `EnvCtrlEnum_binary_sequential_type writeBack_ENV_CTRL;
wire `EnvCtrlEnum_binary_sequential_type _zz_writeBack_ENV_CTRL;
wire [31:0] execute_BRANCH_CALC;
wire execute_BRANCH_DO;
wire [31:0] execute_PC;
wire execute_PREDICTION_HAD_BRANCHED2;
(* keep , syn_keep *) wire [31:0] execute_RS1 /* synthesis syn_keep = 1 */ ;
wire execute_BRANCH_COND_RESULT;
wire `BranchCtrlEnum_binary_sequential_type execute_BRANCH_CTRL;
wire `BranchCtrlEnum_binary_sequential_type _zz_execute_BRANCH_CTRL;
wire decode_RS2_USE;
wire decode_RS1_USE;
reg [31:0] _zz_decode_RS2;
wire execute_REGFILE_WRITE_VALID;
wire execute_BYPASSABLE_EXECUTE_STAGE;
wire memory_REGFILE_WRITE_VALID;
wire [31:0] memory_INSTRUCTION;
wire memory_BYPASSABLE_MEMORY_STAGE;
wire writeBack_REGFILE_WRITE_VALID;
reg [31:0] decode_RS2;
reg [31:0] decode_RS1;
wire [31:0] memory_SHIFT_RIGHT;
reg [31:0] _zz_decode_RS2_1;
wire `ShiftCtrlEnum_binary_sequential_type memory_SHIFT_CTRL;
wire `ShiftCtrlEnum_binary_sequential_type _zz_memory_SHIFT_CTRL;
wire `ShiftCtrlEnum_binary_sequential_type execute_SHIFT_CTRL;
wire `ShiftCtrlEnum_binary_sequential_type _zz_execute_SHIFT_CTRL;
wire execute_SRC_LESS_UNSIGNED;
wire execute_SRC2_FORCE_ZERO;
wire execute_SRC_USE_SUB_LESS;
wire [31:0] _zz_execute_SRC2;
wire `Src2CtrlEnum_binary_sequential_type execute_SRC2_CTRL;
wire `Src2CtrlEnum_binary_sequential_type _zz_execute_SRC2_CTRL;
wire `Src1CtrlEnum_binary_sequential_type execute_SRC1_CTRL;
wire `Src1CtrlEnum_binary_sequential_type _zz_execute_SRC1_CTRL;
wire decode_SRC_USE_SUB_LESS;
wire decode_SRC_ADD_ZERO;
wire [31:0] execute_SRC_ADD_SUB;
wire execute_SRC_LESS;
wire `AluCtrlEnum_binary_sequential_type execute_ALU_CTRL;
wire `AluCtrlEnum_binary_sequential_type _zz_execute_ALU_CTRL;
wire [31:0] execute_SRC2;
wire [31:0] execute_SRC1;
wire `AluBitwiseCtrlEnum_binary_sequential_type execute_ALU_BITWISE_CTRL;
wire `AluBitwiseCtrlEnum_binary_sequential_type _zz_execute_ALU_BITWISE_CTRL;
wire [31:0] _zz_lastStageRegFileWrite_payload_address;
wire _zz_lastStageRegFileWrite_valid;
reg _zz_1;
wire [31:0] decode_INSTRUCTION_ANTICIPATED;
reg decode_REGFILE_WRITE_VALID;
wire decode_LEGAL_INSTRUCTION;
wire `Input2Kind_binary_sequential_type _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_1;
wire `EnvCtrlEnum_binary_sequential_type _zz_decode_ENV_CTRL_1;
wire `BranchCtrlEnum_binary_sequential_type _zz_decode_BRANCH_CTRL;
wire `ShiftCtrlEnum_binary_sequential_type _zz_decode_SHIFT_CTRL_1;
wire `AluBitwiseCtrlEnum_binary_sequential_type _zz_decode_ALU_BITWISE_CTRL_1;
wire `Src2CtrlEnum_binary_sequential_type _zz_decode_SRC2_CTRL_1;
wire `AluCtrlEnum_binary_sequential_type _zz_decode_ALU_CTRL_1;
wire `Src1CtrlEnum_binary_sequential_type _zz_decode_SRC1_CTRL_1;
reg [31:0] _zz_decode_RS2_2;
wire writeBack_MEMORY_WR;
wire [31:0] writeBack_MEMORY_STORE_DATA_RF;
wire [31:0] writeBack_REGFILE_WRITE_DATA;
wire writeBack_MEMORY_ENABLE;
wire [31:0] memory_REGFILE_WRITE_DATA;
wire memory_MEMORY_ENABLE;
wire execute_MEMORY_FORCE_CONSTISTENCY;
wire execute_MEMORY_MANAGMENT;
(* keep , syn_keep *) wire [31:0] execute_RS2 /* synthesis syn_keep = 1 */ ;
wire execute_MEMORY_WR;
wire [31:0] execute_SRC_ADD;
wire execute_MEMORY_ENABLE;
wire [31:0] execute_INSTRUCTION;
wire decode_MEMORY_ENABLE;
wire decode_FLUSH_ALL;
reg IBusCachedPlugin_rsp_issueDetected_4;
reg IBusCachedPlugin_rsp_issueDetected_3;
reg IBusCachedPlugin_rsp_issueDetected_2;
reg IBusCachedPlugin_rsp_issueDetected_1;
wire `BranchCtrlEnum_binary_sequential_type decode_BRANCH_CTRL;
wire `BranchCtrlEnum_binary_sequential_type _zz_decode_BRANCH_CTRL_1;
wire [31:0] decode_INSTRUCTION;
reg [31:0] _zz_execute_to_memory_FORMAL_PC_NEXT;
reg [31:0] _zz_decode_to_execute_FORMAL_PC_NEXT;
wire [31:0] decode_PC;
wire [31:0] writeBack_PC;
wire [31:0] writeBack_INSTRUCTION;
reg decode_arbitration_haltItself;
reg decode_arbitration_haltByOther;
reg decode_arbitration_removeIt;
wire decode_arbitration_flushIt;
reg decode_arbitration_flushNext;
reg decode_arbitration_isValid;
wire decode_arbitration_isStuck;
wire decode_arbitration_isStuckByOthers;
wire decode_arbitration_isFlushed;
wire decode_arbitration_isMoving;
wire decode_arbitration_isFiring;
reg execute_arbitration_haltItself;
reg execute_arbitration_haltByOther;
reg execute_arbitration_removeIt;
reg execute_arbitration_flushIt;
reg execute_arbitration_flushNext;
reg execute_arbitration_isValid;
wire execute_arbitration_isStuck;
wire execute_arbitration_isStuckByOthers;
wire execute_arbitration_isFlushed;
wire execute_arbitration_isMoving;
wire execute_arbitration_isFiring;
reg memory_arbitration_haltItself;
wire memory_arbitration_haltByOther;
reg memory_arbitration_removeIt;
wire memory_arbitration_flushIt;
wire memory_arbitration_flushNext;
reg memory_arbitration_isValid;
wire memory_arbitration_isStuck;
wire memory_arbitration_isStuckByOthers;
wire memory_arbitration_isFlushed;
wire memory_arbitration_isMoving;
wire memory_arbitration_isFiring;
reg writeBack_arbitration_haltItself;
wire writeBack_arbitration_haltByOther;
reg writeBack_arbitration_removeIt;
reg writeBack_arbitration_flushIt;
reg writeBack_arbitration_flushNext;
reg writeBack_arbitration_isValid;
wire writeBack_arbitration_isStuck;
wire writeBack_arbitration_isStuckByOthers;
wire writeBack_arbitration_isFlushed;
wire writeBack_arbitration_isMoving;
wire writeBack_arbitration_isFiring;
wire [31:0] lastStageInstruction /* verilator public */ ;
wire [31:0] lastStagePc /* verilator public */ ;
wire lastStageIsValid /* verilator public */ ;
wire lastStageIsFiring /* verilator public */ ;
reg IBusCachedPlugin_fetcherHalt;
reg IBusCachedPlugin_incomingInstruction;
wire IBusCachedPlugin_predictionJumpInterface_valid;
(* keep , syn_keep *) wire [31:0] IBusCachedPlugin_predictionJumpInterface_payload /* synthesis syn_keep = 1 */ ;
reg IBusCachedPlugin_decodePrediction_cmd_hadBranch;
wire IBusCachedPlugin_decodePrediction_rsp_wasWrong;
wire IBusCachedPlugin_pcValids_0;
wire IBusCachedPlugin_pcValids_1;
wire IBusCachedPlugin_pcValids_2;
wire IBusCachedPlugin_pcValids_3;
reg IBusCachedPlugin_decodeExceptionPort_valid;
reg [3:0] IBusCachedPlugin_decodeExceptionPort_payload_code;
wire [31:0] IBusCachedPlugin_decodeExceptionPort_payload_badAddr;
wire IBusCachedPlugin_mmuBus_cmd_0_isValid;
wire IBusCachedPlugin_mmuBus_cmd_0_isStuck;
wire [31:0] IBusCachedPlugin_mmuBus_cmd_0_virtualAddress;
wire IBusCachedPlugin_mmuBus_cmd_0_bypassTranslation;
wire [31:0] IBusCachedPlugin_mmuBus_rsp_physicalAddress;
wire IBusCachedPlugin_mmuBus_rsp_isIoAccess;
wire IBusCachedPlugin_mmuBus_rsp_isPaging;
wire IBusCachedPlugin_mmuBus_rsp_allowRead;
wire IBusCachedPlugin_mmuBus_rsp_allowWrite;
wire IBusCachedPlugin_mmuBus_rsp_allowExecute;
wire IBusCachedPlugin_mmuBus_rsp_exception;
wire IBusCachedPlugin_mmuBus_rsp_refilling;
wire IBusCachedPlugin_mmuBus_rsp_bypassTranslation;
wire IBusCachedPlugin_mmuBus_end;
wire IBusCachedPlugin_mmuBus_busy;
wire dBus_cmd_valid;
wire dBus_cmd_ready;
wire dBus_cmd_payload_wr;
wire dBus_cmd_payload_uncached;
wire [31:0] dBus_cmd_payload_address;
wire [31:0] dBus_cmd_payload_data;
wire [3:0] dBus_cmd_payload_mask;
wire [2:0] dBus_cmd_payload_size;
wire dBus_cmd_payload_last;
wire dBus_rsp_valid;
wire dBus_rsp_payload_last;
wire [31:0] dBus_rsp_payload_data;
wire dBus_rsp_payload_error;
wire DBusCachedPlugin_mmuBus_cmd_0_isValid;
wire DBusCachedPlugin_mmuBus_cmd_0_isStuck;
wire [31:0] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress;
wire DBusCachedPlugin_mmuBus_cmd_0_bypassTranslation;
wire [31:0] DBusCachedPlugin_mmuBus_rsp_physicalAddress;
wire DBusCachedPlugin_mmuBus_rsp_isIoAccess;
wire DBusCachedPlugin_mmuBus_rsp_isPaging;
wire DBusCachedPlugin_mmuBus_rsp_allowRead;
wire DBusCachedPlugin_mmuBus_rsp_allowWrite;
wire DBusCachedPlugin_mmuBus_rsp_allowExecute;
wire DBusCachedPlugin_mmuBus_rsp_exception;
wire DBusCachedPlugin_mmuBus_rsp_refilling;
wire DBusCachedPlugin_mmuBus_rsp_bypassTranslation;
wire DBusCachedPlugin_mmuBus_end;
wire DBusCachedPlugin_mmuBus_busy;
reg DBusCachedPlugin_redoBranch_valid;
wire [31:0] DBusCachedPlugin_redoBranch_payload;
reg DBusCachedPlugin_exceptionBus_valid;
reg [3:0] DBusCachedPlugin_exceptionBus_payload_code;
wire [31:0] DBusCachedPlugin_exceptionBus_payload_badAddr;
reg _zz_when_DBusCachedPlugin_l386;
wire decodeExceptionPort_valid;
wire [3:0] decodeExceptionPort_payload_code;
wire [31:0] decodeExceptionPort_payload_badAddr;
wire BranchPlugin_jumpInterface_valid;
wire [31:0] BranchPlugin_jumpInterface_payload;
reg BranchPlugin_branchExceptionPort_valid;
wire [3:0] BranchPlugin_branchExceptionPort_payload_code;
wire [31:0] BranchPlugin_branchExceptionPort_payload_badAddr;
wire [31:0] CsrPlugin_csrMapping_readDataSignal;
wire [31:0] CsrPlugin_csrMapping_readDataInit;
wire [31:0] CsrPlugin_csrMapping_writeDataSignal;
wire CsrPlugin_csrMapping_allowCsrSignal;
wire CsrPlugin_csrMapping_hazardFree;
reg CsrPlugin_inWfi /* verilator public */ ;
reg CsrPlugin_thirdPartyWake;
reg CsrPlugin_jumpInterface_valid;
reg [31:0] CsrPlugin_jumpInterface_payload;
wire CsrPlugin_exceptionPendings_0;
wire CsrPlugin_exceptionPendings_1;
wire CsrPlugin_exceptionPendings_2;
wire CsrPlugin_exceptionPendings_3;
wire externalInterrupt;
wire contextSwitching;
reg [1:0] CsrPlugin_privilege;
reg CsrPlugin_forceMachineWire;
reg CsrPlugin_selfException_valid;
reg [3:0] CsrPlugin_selfException_payload_code;
wire [31:0] CsrPlugin_selfException_payload_badAddr;
reg CsrPlugin_allowInterrupts;
reg CsrPlugin_allowException;
reg CsrPlugin_allowEbreakException;
reg IBusCachedPlugin_injectionPort_valid;
reg IBusCachedPlugin_injectionPort_ready;
wire [31:0] IBusCachedPlugin_injectionPort_payload;
wire IBusCachedPlugin_externalFlush;
wire IBusCachedPlugin_jump_pcLoad_valid;
wire [31:0] IBusCachedPlugin_jump_pcLoad_payload;
wire [3:0] _zz_IBusCachedPlugin_jump_pcLoad_payload;
wire [3:0] _zz_IBusCachedPlugin_jump_pcLoad_payload_1;
wire _zz_IBusCachedPlugin_jump_pcLoad_payload_2;
wire _zz_IBusCachedPlugin_jump_pcLoad_payload_3;
wire _zz_IBusCachedPlugin_jump_pcLoad_payload_4;
wire IBusCachedPlugin_fetchPc_output_valid;
wire IBusCachedPlugin_fetchPc_output_ready;
wire [31:0] IBusCachedPlugin_fetchPc_output_payload;
reg [31:0] IBusCachedPlugin_fetchPc_pcReg /* verilator public */ ;
reg IBusCachedPlugin_fetchPc_correction;
reg IBusCachedPlugin_fetchPc_correctionReg;
wire IBusCachedPlugin_fetchPc_output_fire;
wire IBusCachedPlugin_fetchPc_corrected;
reg IBusCachedPlugin_fetchPc_pcRegPropagate;
reg IBusCachedPlugin_fetchPc_booted;
reg IBusCachedPlugin_fetchPc_inc;
wire when_Fetcher_l131;
wire IBusCachedPlugin_fetchPc_output_fire_1;
wire when_Fetcher_l131_1;
reg [31:0] IBusCachedPlugin_fetchPc_pc;
wire IBusCachedPlugin_fetchPc_redo_valid;
wire [31:0] IBusCachedPlugin_fetchPc_redo_payload;
reg IBusCachedPlugin_fetchPc_flushed;
wire when_Fetcher_l158;
reg IBusCachedPlugin_iBusRsp_redoFetch;
wire IBusCachedPlugin_iBusRsp_stages_0_input_valid;
wire IBusCachedPlugin_iBusRsp_stages_0_input_ready;
wire [31:0] IBusCachedPlugin_iBusRsp_stages_0_input_payload;
wire IBusCachedPlugin_iBusRsp_stages_0_output_valid;
wire IBusCachedPlugin_iBusRsp_stages_0_output_ready;
wire [31:0] IBusCachedPlugin_iBusRsp_stages_0_output_payload;
reg IBusCachedPlugin_iBusRsp_stages_0_halt;
wire IBusCachedPlugin_iBusRsp_stages_1_input_valid;
wire IBusCachedPlugin_iBusRsp_stages_1_input_ready;
wire [31:0] IBusCachedPlugin_iBusRsp_stages_1_input_payload;
wire IBusCachedPlugin_iBusRsp_stages_1_output_valid;
wire IBusCachedPlugin_iBusRsp_stages_1_output_ready;
wire [31:0] IBusCachedPlugin_iBusRsp_stages_1_output_payload;
reg IBusCachedPlugin_iBusRsp_stages_1_halt;
wire IBusCachedPlugin_iBusRsp_stages_2_input_valid;
wire IBusCachedPlugin_iBusRsp_stages_2_input_ready;
wire [31:0] IBusCachedPlugin_iBusRsp_stages_2_input_payload;
wire IBusCachedPlugin_iBusRsp_stages_2_output_valid;
wire IBusCachedPlugin_iBusRsp_stages_2_output_ready;
wire [31:0] IBusCachedPlugin_iBusRsp_stages_2_output_payload;
reg IBusCachedPlugin_iBusRsp_stages_2_halt;
wire _zz_IBusCachedPlugin_iBusRsp_stages_0_input_ready;
wire _zz_IBusCachedPlugin_iBusRsp_stages_1_input_ready;
wire _zz_IBusCachedPlugin_iBusRsp_stages_2_input_ready;
wire IBusCachedPlugin_iBusRsp_flush;
wire _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready;
wire _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_1;
reg _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_2;
wire IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid;
wire IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_ready;
wire [31:0] IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_payload;
reg _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid;
reg [31:0] _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_payload;
reg IBusCachedPlugin_iBusRsp_readyForError;
wire IBusCachedPlugin_iBusRsp_output_valid;
wire IBusCachedPlugin_iBusRsp_output_ready;
wire [31:0] IBusCachedPlugin_iBusRsp_output_payload_pc;
wire IBusCachedPlugin_iBusRsp_output_payload_rsp_error;
wire [31:0] IBusCachedPlugin_iBusRsp_output_payload_rsp_inst;
wire IBusCachedPlugin_iBusRsp_output_payload_isRvc;
wire when_Fetcher_l240;
wire when_Fetcher_l320;
reg IBusCachedPlugin_injector_nextPcCalc_valids_0;
wire when_Fetcher_l329;
reg IBusCachedPlugin_injector_nextPcCalc_valids_1;
wire when_Fetcher_l329_1;
reg IBusCachedPlugin_injector_nextPcCalc_valids_2;
wire when_Fetcher_l329_2;
reg IBusCachedPlugin_injector_nextPcCalc_valids_3;
wire when_Fetcher_l329_3;
reg IBusCachedPlugin_injector_nextPcCalc_valids_4;
wire when_Fetcher_l329_4;
wire _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch;
reg [18:0] _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1;
wire _zz_2;
reg [10:0] _zz_3;
wire _zz_4;
reg [18:0] _zz_5;
reg _zz_6;
wire _zz_IBusCachedPlugin_predictionJumpInterface_payload;
reg [10:0] _zz_IBusCachedPlugin_predictionJumpInterface_payload_1;
wire _zz_IBusCachedPlugin_predictionJumpInterface_payload_2;
reg [18:0] _zz_IBusCachedPlugin_predictionJumpInterface_payload_3;
wire iBus_cmd_valid;
wire iBus_cmd_ready;
reg [31:0] iBus_cmd_payload_address;
wire [2:0] iBus_cmd_payload_size;
wire iBus_rsp_valid;
wire [31:0] iBus_rsp_payload_data;
wire iBus_rsp_payload_error;
wire [31:0] _zz_IBusCachedPlugin_rspCounter;
reg [31:0] IBusCachedPlugin_rspCounter;
wire IBusCachedPlugin_s0_tightlyCoupledHit;
reg IBusCachedPlugin_s1_tightlyCoupledHit;
reg IBusCachedPlugin_s2_tightlyCoupledHit;
wire IBusCachedPlugin_rsp_iBusRspOutputHalt;
wire IBusCachedPlugin_rsp_issueDetected;
reg IBusCachedPlugin_rsp_redoFetch;
wire when_IBusCachedPlugin_l239;
wire when_IBusCachedPlugin_l244;
wire when_IBusCachedPlugin_l250;
wire when_IBusCachedPlugin_l256;
wire when_IBusCachedPlugin_l267;
wire dataCache_1_io_mem_cmd_s2mPipe_valid;
reg dataCache_1_io_mem_cmd_s2mPipe_ready;
wire dataCache_1_io_mem_cmd_s2mPipe_payload_wr;
wire dataCache_1_io_mem_cmd_s2mPipe_payload_uncached;
wire [31:0] dataCache_1_io_mem_cmd_s2mPipe_payload_address;
wire [31:0] dataCache_1_io_mem_cmd_s2mPipe_payload_data;
wire [3:0] dataCache_1_io_mem_cmd_s2mPipe_payload_mask;
wire [2:0] dataCache_1_io_mem_cmd_s2mPipe_payload_size;
wire dataCache_1_io_mem_cmd_s2mPipe_payload_last;
reg dataCache_1_io_mem_cmd_rValid;
reg dataCache_1_io_mem_cmd_rData_wr;
reg dataCache_1_io_mem_cmd_rData_uncached;
reg [31:0] dataCache_1_io_mem_cmd_rData_address;
reg [31:0] dataCache_1_io_mem_cmd_rData_data;
reg [3:0] dataCache_1_io_mem_cmd_rData_mask;
reg [2:0] dataCache_1_io_mem_cmd_rData_size;
reg dataCache_1_io_mem_cmd_rData_last;
wire dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_valid;
wire dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_ready;
wire dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_wr;
wire dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_uncached;
wire [31:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_address;
wire [31:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_data;
wire [3:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_mask;
wire [2:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_size;
wire dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_last;
reg dataCache_1_io_mem_cmd_s2mPipe_rValid;
reg dataCache_1_io_mem_cmd_s2mPipe_rData_wr;
reg dataCache_1_io_mem_cmd_s2mPipe_rData_uncached;
reg [31:0] dataCache_1_io_mem_cmd_s2mPipe_rData_address;
reg [31:0] dataCache_1_io_mem_cmd_s2mPipe_rData_data;
reg [3:0] dataCache_1_io_mem_cmd_s2mPipe_rData_mask;
reg [2:0] dataCache_1_io_mem_cmd_s2mPipe_rData_size;
reg dataCache_1_io_mem_cmd_s2mPipe_rData_last;
wire when_Stream_l342;
wire [31:0] _zz_DBusCachedPlugin_rspCounter;
reg [31:0] DBusCachedPlugin_rspCounter;
wire when_DBusCachedPlugin_l303;
wire [1:0] execute_DBusCachedPlugin_size;
reg [31:0] _zz_execute_MEMORY_STORE_DATA_RF;
wire dataCache_1_io_cpu_flush_isStall;
wire when_DBusCachedPlugin_l343;
wire when_DBusCachedPlugin_l359;
wire when_DBusCachedPlugin_l386;
wire when_DBusCachedPlugin_l438;
wire when_DBusCachedPlugin_l458;
wire [7:0] writeBack_DBusCachedPlugin_rspSplits_0;
wire [7:0] writeBack_DBusCachedPlugin_rspSplits_1;
wire [7:0] writeBack_DBusCachedPlugin_rspSplits_2;
wire [7:0] writeBack_DBusCachedPlugin_rspSplits_3;
reg [31:0] writeBack_DBusCachedPlugin_rspShifted;
wire [31:0] writeBack_DBusCachedPlugin_rspRf;
wire [1:0] switch_Misc_l200;
wire _zz_writeBack_DBusCachedPlugin_rspFormated;
reg [31:0] _zz_writeBack_DBusCachedPlugin_rspFormated_1;
wire _zz_writeBack_DBusCachedPlugin_rspFormated_2;
reg [31:0] _zz_writeBack_DBusCachedPlugin_rspFormated_3;
reg [31:0] writeBack_DBusCachedPlugin_rspFormated;
wire when_DBusCachedPlugin_l484;
wire [34:0] _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2;
wire _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_3;
wire _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_4;
wire _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_5;
wire _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_6;
wire _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_7;
wire `Src1CtrlEnum_binary_sequential_type _zz_decode_SRC1_CTRL_2;
wire `AluCtrlEnum_binary_sequential_type _zz_decode_ALU_CTRL_2;
wire `Src2CtrlEnum_binary_sequential_type _zz_decode_SRC2_CTRL_2;
wire `AluBitwiseCtrlEnum_binary_sequential_type _zz_decode_ALU_BITWISE_CTRL_2;
wire `ShiftCtrlEnum_binary_sequential_type _zz_decode_SHIFT_CTRL_2;
wire `BranchCtrlEnum_binary_sequential_type _zz_decode_BRANCH_CTRL_2;
wire `EnvCtrlEnum_binary_sequential_type _zz_decode_ENV_CTRL_2;
wire `Input2Kind_binary_sequential_type _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_8;
wire when_RegFilePlugin_l63;
wire [4:0] decode_RegFilePlugin_regFileReadAddress1;
wire [4:0] decode_RegFilePlugin_regFileReadAddress2;
wire [31:0] decode_RegFilePlugin_rs1Data;
wire [31:0] decode_RegFilePlugin_rs2Data;
reg lastStageRegFileWrite_valid /* verilator public */ ;
reg [4:0] lastStageRegFileWrite_payload_address /* verilator public */ ;
reg [31:0] lastStageRegFileWrite_payload_data /* verilator public */ ;
reg _zz_7;
reg [31:0] execute_IntAluPlugin_bitwise;
reg [31:0] _zz_execute_REGFILE_WRITE_DATA;
reg [31:0] _zz_execute_SRC1;
wire _zz_execute_SRC2_1;
reg [19:0] _zz_execute_SRC2_2;
wire _zz_execute_SRC2_3;
reg [19:0] _zz_execute_SRC2_4;
reg [31:0] _zz_execute_SRC2_5;
reg [31:0] execute_SrcPlugin_addSub;
wire execute_SrcPlugin_less;
wire [4:0] execute_FullBarrelShifterPlugin_amplitude;
reg [31:0] _zz_execute_FullBarrelShifterPlugin_reversed;
wire [31:0] execute_FullBarrelShifterPlugin_reversed;
reg [31:0] _zz_decode_RS2_3;
reg HazardSimplePlugin_src0Hazard;
reg HazardSimplePlugin_src1Hazard;
wire HazardSimplePlugin_writeBackWrites_valid;
wire [4:0] HazardSimplePlugin_writeBackWrites_payload_address;
wire [31:0] HazardSimplePlugin_writeBackWrites_payload_data;
reg HazardSimplePlugin_writeBackBuffer_valid;
reg [4:0] HazardSimplePlugin_writeBackBuffer_payload_address;
reg [31:0] HazardSimplePlugin_writeBackBuffer_payload_data;
wire HazardSimplePlugin_addr0Match;
wire HazardSimplePlugin_addr1Match;
wire when_HazardSimplePlugin_l47;
wire when_HazardSimplePlugin_l48;
wire when_HazardSimplePlugin_l51;
wire when_HazardSimplePlugin_l45;
wire when_HazardSimplePlugin_l57;
wire when_HazardSimplePlugin_l58;
wire when_HazardSimplePlugin_l48_1;
wire when_HazardSimplePlugin_l51_1;
wire when_HazardSimplePlugin_l45_1;
wire when_HazardSimplePlugin_l57_1;
wire when_HazardSimplePlugin_l58_1;
wire when_HazardSimplePlugin_l48_2;
wire when_HazardSimplePlugin_l51_2;
wire when_HazardSimplePlugin_l45_2;
wire when_HazardSimplePlugin_l57_2;
wire when_HazardSimplePlugin_l58_2;
wire when_HazardSimplePlugin_l105;
wire when_HazardSimplePlugin_l108;
wire when_HazardSimplePlugin_l113;
wire execute_BranchPlugin_eq;
wire [2:0] switch_Misc_l200_1;
reg _zz_execute_BRANCH_COND_RESULT;
reg _zz_execute_BRANCH_COND_RESULT_1;
wire _zz_execute_BranchPlugin_missAlignedTarget;
reg [19:0] _zz_execute_BranchPlugin_missAlignedTarget_1;
wire _zz_execute_BranchPlugin_missAlignedTarget_2;
reg [10:0] _zz_execute_BranchPlugin_missAlignedTarget_3;
wire _zz_execute_BranchPlugin_missAlignedTarget_4;
reg [18:0] _zz_execute_BranchPlugin_missAlignedTarget_5;
reg _zz_execute_BranchPlugin_missAlignedTarget_6;
wire execute_BranchPlugin_missAlignedTarget;
reg [31:0] execute_BranchPlugin_branch_src1;
reg [31:0] execute_BranchPlugin_branch_src2;
wire _zz_execute_BranchPlugin_branch_src2;
reg [19:0] _zz_execute_BranchPlugin_branch_src2_1;
wire _zz_execute_BranchPlugin_branch_src2_2;
reg [10:0] _zz_execute_BranchPlugin_branch_src2_3;
wire _zz_execute_BranchPlugin_branch_src2_4;
reg [18:0] _zz_execute_BranchPlugin_branch_src2_5;
wire [31:0] execute_BranchPlugin_branchAdder;
wire when_BranchPlugin_l296;
reg [1:0] CsrPlugin_misa_base;
reg [25:0] CsrPlugin_misa_extensions;
reg [1:0] CsrPlugin_mtvec_mode;
reg [29:0] CsrPlugin_mtvec_base;
reg [31:0] CsrPlugin_mepc;
reg CsrPlugin_mstatus_MIE;
reg CsrPlugin_mstatus_MPIE;
reg [1:0] CsrPlugin_mstatus_MPP;
reg CsrPlugin_mip_MEIP;
reg CsrPlugin_mip_MTIP;
reg CsrPlugin_mip_MSIP;
reg CsrPlugin_mie_MEIE;
reg CsrPlugin_mie_MTIE;
reg CsrPlugin_mie_MSIE;
reg [31:0] CsrPlugin_mscratch;
reg CsrPlugin_mcause_interrupt;
reg [3:0] CsrPlugin_mcause_exceptionCode;
reg [31:0] CsrPlugin_mtval;
reg [63:0] CsrPlugin_mcycle = 64'b0000000000000000000000000000000000000000000000000000000000000000;
reg [63:0] CsrPlugin_minstret = 64'b0000000000000000000000000000000000000000000000000000000000000000;
wire _zz_when_CsrPlugin_l952;
wire _zz_when_CsrPlugin_l952_1;
wire _zz_when_CsrPlugin_l952_2;
reg CsrPlugin_exceptionPortCtrl_exceptionValids_decode;
reg CsrPlugin_exceptionPortCtrl_exceptionValids_execute;
reg CsrPlugin_exceptionPortCtrl_exceptionValids_memory;
reg CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack;
reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode;
reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute;
reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory;
reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack;
reg [3:0] CsrPlugin_exceptionPortCtrl_exceptionContext_code;
reg [31:0] CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr;
wire [1:0] CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped;
wire [1:0] CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege;
wire [1:0] _zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code;
wire _zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1;
wire [1:0] _zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_2;
wire _zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_3;
wire when_CsrPlugin_l909;
wire when_CsrPlugin_l909_1;
wire when_CsrPlugin_l909_2;
wire when_CsrPlugin_l909_3;
wire when_CsrPlugin_l922;
reg CsrPlugin_interrupt_valid;
reg [3:0] CsrPlugin_interrupt_code /* verilator public */ ;
reg [1:0] CsrPlugin_interrupt_targetPrivilege;
wire when_CsrPlugin_l946;
wire when_CsrPlugin_l952;
wire when_CsrPlugin_l952_1;
wire when_CsrPlugin_l952_2;
wire CsrPlugin_exception;
reg CsrPlugin_lastStageWasWfi;
reg CsrPlugin_pipelineLiberator_pcValids_0;
reg CsrPlugin_pipelineLiberator_pcValids_1;
reg CsrPlugin_pipelineLiberator_pcValids_2;
wire CsrPlugin_pipelineLiberator_active;
wire when_CsrPlugin_l980;
wire when_CsrPlugin_l980_1;
wire when_CsrPlugin_l980_2;
wire when_CsrPlugin_l985;
reg CsrPlugin_pipelineLiberator_done;
wire when_CsrPlugin_l991;
wire CsrPlugin_interruptJump /* verilator public */ ;
reg CsrPlugin_hadException /* verilator public */ ;
reg [1:0] CsrPlugin_targetPrivilege;
reg [3:0] CsrPlugin_trapCause;
reg [1:0] CsrPlugin_xtvec_mode;
reg [29:0] CsrPlugin_xtvec_base;
wire when_CsrPlugin_l1019;
wire when_CsrPlugin_l1064;
wire [1:0] switch_CsrPlugin_l1068;
reg execute_CsrPlugin_wfiWake;
wire when_CsrPlugin_l1108;
wire when_CsrPlugin_l1110;
wire when_CsrPlugin_l1116;
wire execute_CsrPlugin_blockedBySideEffects;
reg execute_CsrPlugin_illegalAccess;
reg execute_CsrPlugin_illegalInstruction;
wire when_CsrPlugin_l1129;
wire when_CsrPlugin_l1136;
wire when_CsrPlugin_l1137;
wire when_CsrPlugin_l1144;
reg execute_CsrPlugin_writeInstruction;
reg execute_CsrPlugin_readInstruction;
wire execute_CsrPlugin_writeEnable;
wire execute_CsrPlugin_readEnable;
wire [31:0] execute_CsrPlugin_readToWriteData;
wire switch_Misc_l200_2;
reg [31:0] _zz_CsrPlugin_csrMapping_writeDataSignal;
wire when_CsrPlugin_l1176;
wire when_CsrPlugin_l1180;
wire [11:0] execute_CsrPlugin_csrAddress;
reg execute_MulPlugin_aSigned;
reg execute_MulPlugin_bSigned;
wire [31:0] execute_MulPlugin_a;
wire [31:0] execute_MulPlugin_b;
wire [1:0] switch_MulPlugin_l87;
wire [15:0] execute_MulPlugin_aULow;
wire [15:0] execute_MulPlugin_bULow;
wire [16:0] execute_MulPlugin_aSLow;
wire [16:0] execute_MulPlugin_bSLow;
wire [16:0] execute_MulPlugin_aHigh;
wire [16:0] execute_MulPlugin_bHigh;
wire [65:0] writeBack_MulPlugin_result;
wire when_MulPlugin_l147;
wire [1:0] switch_MulPlugin_l148;
reg [32:0] memory_DivPlugin_rs1;
reg [31:0] memory_DivPlugin_rs2;
reg [64:0] memory_DivPlugin_accumulator;
wire memory_DivPlugin_frontendOk;
reg memory_DivPlugin_div_needRevert;
reg memory_DivPlugin_div_counter_willIncrement;
reg memory_DivPlugin_div_counter_willClear;
reg [5:0] memory_DivPlugin_div_counter_valueNext;
reg [5:0] memory_DivPlugin_div_counter_value;
wire memory_DivPlugin_div_counter_willOverflowIfInc;
wire memory_DivPlugin_div_counter_willOverflow;
reg memory_DivPlugin_div_done;
wire when_MulDivIterativePlugin_l126;
wire when_MulDivIterativePlugin_l126_1;
reg [31:0] memory_DivPlugin_div_result;
wire when_MulDivIterativePlugin_l128;
wire when_MulDivIterativePlugin_l129;
wire when_MulDivIterativePlugin_l132;
wire [31:0] _zz_memory_DivPlugin_div_stage_0_remainderShifted;
wire [32:0] memory_DivPlugin_div_stage_0_remainderShifted;
wire [32:0] memory_DivPlugin_div_stage_0_remainderMinusDenominator;
wire [31:0] memory_DivPlugin_div_stage_0_outRemainder;
wire [31:0] memory_DivPlugin_div_stage_0_outNumerator;
wire when_MulDivIterativePlugin_l151;
wire [31:0] _zz_memory_DivPlugin_div_result;
wire when_MulDivIterativePlugin_l162;
wire _zz_memory_DivPlugin_rs2;
wire _zz_memory_DivPlugin_rs1;
reg [32:0] _zz_memory_DivPlugin_rs1_1;
reg [31:0] externalInterruptArray_regNext;
reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit;
wire [31:0] _zz_CsrPlugin_csrMapping_readDataInit_1;
reg DebugPlugin_firstCycle;
reg DebugPlugin_secondCycle;
reg DebugPlugin_resetIt;
reg DebugPlugin_haltIt;
reg DebugPlugin_stepIt;
reg DebugPlugin_isPipBusy;
reg DebugPlugin_godmode;
wire when_DebugPlugin_l225;
reg DebugPlugin_haltedByBreak;
reg DebugPlugin_debugUsed /* verilator public */ ;
reg DebugPlugin_disableEbreak;
wire DebugPlugin_allowEBreak;
reg [31:0] DebugPlugin_busReadDataReg;
reg _zz_when_DebugPlugin_l244;
wire when_DebugPlugin_l244;
wire [5:0] switch_DebugPlugin_l256;
wire when_DebugPlugin_l260;
wire when_DebugPlugin_l260_1;
wire when_DebugPlugin_l261;
wire when_DebugPlugin_l261_1;
wire when_DebugPlugin_l262;
wire when_DebugPlugin_l263;
wire when_DebugPlugin_l264;
wire when_DebugPlugin_l264_1;
wire when_DebugPlugin_l284;
wire when_DebugPlugin_l287;
wire when_DebugPlugin_l300;
reg DebugPlugin_resetIt_regNext;
wire when_DebugPlugin_l316;
wire execute_CfuPlugin_schedule;
reg execute_CfuPlugin_hold;
reg execute_CfuPlugin_fired;
wire CfuPlugin_bus_cmd_fire;
wire when_CfuPlugin_l171;
wire when_CfuPlugin_l175;
wire [9:0] execute_CfuPlugin_functionsIds_0;
wire _zz_CfuPlugin_bus_cmd_payload_inputs_1;
reg [23:0] _zz_CfuPlugin_bus_cmd_payload_inputs_1_1;
reg [31:0] _zz_CfuPlugin_bus_cmd_payload_inputs_1_2;
wire CfuPlugin_bus_rsp_rsp_valid;
reg CfuPlugin_bus_rsp_rsp_ready;
wire [31:0] CfuPlugin_bus_rsp_rsp_payload_outputs_0;
reg CfuPlugin_bus_rsp_rValid;
reg [31:0] CfuPlugin_bus_rsp_rData_outputs_0;
wire when_CfuPlugin_l208;
wire when_Pipeline_l124;
reg [31:0] decode_to_execute_PC;
wire when_Pipeline_l124_1;
reg [31:0] execute_to_memory_PC;
wire when_Pipeline_l124_2;
reg [31:0] memory_to_writeBack_PC;
wire when_Pipeline_l124_3;
reg [31:0] decode_to_execute_INSTRUCTION;
wire when_Pipeline_l124_4;
reg [31:0] execute_to_memory_INSTRUCTION;
wire when_Pipeline_l124_5;
reg [31:0] memory_to_writeBack_INSTRUCTION;
wire when_Pipeline_l124_6;
reg [31:0] decode_to_execute_FORMAL_PC_NEXT;
wire when_Pipeline_l124_7;
reg [31:0] execute_to_memory_FORMAL_PC_NEXT;
wire when_Pipeline_l124_8;
reg [31:0] memory_to_writeBack_FORMAL_PC_NEXT;
wire when_Pipeline_l124_9;
reg decode_to_execute_MEMORY_FORCE_CONSTISTENCY;
wire when_Pipeline_l124_10;
reg `Src1CtrlEnum_binary_sequential_type decode_to_execute_SRC1_CTRL;
wire when_Pipeline_l124_11;
reg decode_to_execute_SRC_USE_SUB_LESS;
wire when_Pipeline_l124_12;
reg decode_to_execute_MEMORY_ENABLE;
wire when_Pipeline_l124_13;
reg execute_to_memory_MEMORY_ENABLE;
wire when_Pipeline_l124_14;
reg memory_to_writeBack_MEMORY_ENABLE;
wire when_Pipeline_l124_15;
reg `AluCtrlEnum_binary_sequential_type decode_to_execute_ALU_CTRL;
wire when_Pipeline_l124_16;
reg `Src2CtrlEnum_binary_sequential_type decode_to_execute_SRC2_CTRL;
wire when_Pipeline_l124_17;
reg decode_to_execute_REGFILE_WRITE_VALID;
wire when_Pipeline_l124_18;
reg execute_to_memory_REGFILE_WRITE_VALID;
wire when_Pipeline_l124_19;
reg memory_to_writeBack_REGFILE_WRITE_VALID;
wire when_Pipeline_l124_20;
reg decode_to_execute_BYPASSABLE_EXECUTE_STAGE;
wire when_Pipeline_l124_21;
reg decode_to_execute_BYPASSABLE_MEMORY_STAGE;
wire when_Pipeline_l124_22;
reg execute_to_memory_BYPASSABLE_MEMORY_STAGE;
wire when_Pipeline_l124_23;
reg decode_to_execute_MEMORY_WR;
wire when_Pipeline_l124_24;
reg execute_to_memory_MEMORY_WR;
wire when_Pipeline_l124_25;
reg memory_to_writeBack_MEMORY_WR;
wire when_Pipeline_l124_26;
reg decode_to_execute_MEMORY_MANAGMENT;
wire when_Pipeline_l124_27;
reg decode_to_execute_SRC_LESS_UNSIGNED;
wire when_Pipeline_l124_28;
reg `AluBitwiseCtrlEnum_binary_sequential_type decode_to_execute_ALU_BITWISE_CTRL;
wire when_Pipeline_l124_29;
reg `ShiftCtrlEnum_binary_sequential_type decode_to_execute_SHIFT_CTRL;
wire when_Pipeline_l124_30;
reg `ShiftCtrlEnum_binary_sequential_type execute_to_memory_SHIFT_CTRL;
wire when_Pipeline_l124_31;
reg `BranchCtrlEnum_binary_sequential_type decode_to_execute_BRANCH_CTRL;
wire when_Pipeline_l124_32;
reg decode_to_execute_IS_CSR;
wire when_Pipeline_l124_33;
reg `EnvCtrlEnum_binary_sequential_type decode_to_execute_ENV_CTRL;
wire when_Pipeline_l124_34;
reg `EnvCtrlEnum_binary_sequential_type execute_to_memory_ENV_CTRL;
wire when_Pipeline_l124_35;
reg `EnvCtrlEnum_binary_sequential_type memory_to_writeBack_ENV_CTRL;
wire when_Pipeline_l124_36;
reg decode_to_execute_IS_MUL;
wire when_Pipeline_l124_37;
reg execute_to_memory_IS_MUL;
wire when_Pipeline_l124_38;
reg memory_to_writeBack_IS_MUL;
wire when_Pipeline_l124_39;
reg decode_to_execute_IS_DIV;
wire when_Pipeline_l124_40;
reg execute_to_memory_IS_DIV;
wire when_Pipeline_l124_41;
reg decode_to_execute_IS_RS1_SIGNED;
wire when_Pipeline_l124_42;
reg decode_to_execute_IS_RS2_SIGNED;
wire when_Pipeline_l124_43;
reg decode_to_execute_CfuPlugin_CFU_ENABLE;
wire when_Pipeline_l124_44;
reg `Input2Kind_binary_sequential_type decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND;
wire when_Pipeline_l124_45;
reg [31:0] decode_to_execute_RS1;
wire when_Pipeline_l124_46;
reg [31:0] decode_to_execute_RS2;
wire when_Pipeline_l124_47;
reg decode_to_execute_SRC2_FORCE_ZERO;
wire when_Pipeline_l124_48;
reg decode_to_execute_PREDICTION_HAD_BRANCHED2;
wire when_Pipeline_l124_49;
reg decode_to_execute_CSR_WRITE_OPCODE;
wire when_Pipeline_l124_50;
reg decode_to_execute_CSR_READ_OPCODE;
wire when_Pipeline_l124_51;
reg decode_to_execute_DO_EBREAK;
wire when_Pipeline_l124_52;
reg [31:0] execute_to_memory_MEMORY_STORE_DATA_RF;
wire when_Pipeline_l124_53;
reg [31:0] memory_to_writeBack_MEMORY_STORE_DATA_RF;
wire when_Pipeline_l124_54;
reg [31:0] execute_to_memory_REGFILE_WRITE_DATA;
wire when_Pipeline_l124_55;
reg [31:0] memory_to_writeBack_REGFILE_WRITE_DATA;
wire when_Pipeline_l124_56;
reg [31:0] execute_to_memory_SHIFT_RIGHT;
wire when_Pipeline_l124_57;
reg [31:0] execute_to_memory_MUL_LL;
wire when_Pipeline_l124_58;
reg [33:0] execute_to_memory_MUL_LH;
wire when_Pipeline_l124_59;
reg [33:0] execute_to_memory_MUL_HL;
wire when_Pipeline_l124_60;
reg [33:0] execute_to_memory_MUL_HH;
wire when_Pipeline_l124_61;
reg [33:0] memory_to_writeBack_MUL_HH;
wire when_Pipeline_l124_62;
reg execute_to_memory_CfuPlugin_CFU_IN_FLIGHT;
wire when_Pipeline_l124_63;
reg memory_to_writeBack_CfuPlugin_CFU_IN_FLIGHT;
wire when_Pipeline_l124_64;
reg [51:0] memory_to_writeBack_MUL_LOW;
wire when_Pipeline_l151;
wire when_Pipeline_l154;
wire when_Pipeline_l151_1;
wire when_Pipeline_l154_1;
wire when_Pipeline_l151_2;
wire when_Pipeline_l154_2;
reg [2:0] switch_Fetcher_l362;
wire when_Fetcher_l378;
wire when_CsrPlugin_l1264;
reg execute_CsrPlugin_csr_3264;
wire when_CsrPlugin_l1264_1;
reg execute_CsrPlugin_csr_3857;
wire when_CsrPlugin_l1264_2;
reg execute_CsrPlugin_csr_3858;
wire when_CsrPlugin_l1264_3;
reg execute_CsrPlugin_csr_3859;
wire when_CsrPlugin_l1264_4;
reg execute_CsrPlugin_csr_3860;
wire when_CsrPlugin_l1264_5;
reg execute_CsrPlugin_csr_769;
wire when_CsrPlugin_l1264_6;
reg execute_CsrPlugin_csr_768;
wire when_CsrPlugin_l1264_7;
reg execute_CsrPlugin_csr_836;
wire when_CsrPlugin_l1264_8;
reg execute_CsrPlugin_csr_772;
wire when_CsrPlugin_l1264_9;
reg execute_CsrPlugin_csr_773;
wire when_CsrPlugin_l1264_10;
reg execute_CsrPlugin_csr_833;
wire when_CsrPlugin_l1264_11;
reg execute_CsrPlugin_csr_832;
wire when_CsrPlugin_l1264_12;
reg execute_CsrPlugin_csr_834;
wire when_CsrPlugin_l1264_13;
reg execute_CsrPlugin_csr_835;
wire when_CsrPlugin_l1264_14;
reg execute_CsrPlugin_csr_2816;
wire when_CsrPlugin_l1264_15;
reg execute_CsrPlugin_csr_2944;
wire when_CsrPlugin_l1264_16;
reg execute_CsrPlugin_csr_2818;
wire when_CsrPlugin_l1264_17;
reg execute_CsrPlugin_csr_2946;
wire when_CsrPlugin_l1264_18;
reg execute_CsrPlugin_csr_3072;
wire when_CsrPlugin_l1264_19;
reg execute_CsrPlugin_csr_3200;
wire when_CsrPlugin_l1264_20;
reg execute_CsrPlugin_csr_3074;
wire when_CsrPlugin_l1264_21;
reg execute_CsrPlugin_csr_3202;
wire when_CsrPlugin_l1264_22;
reg execute_CsrPlugin_csr_3008;
wire when_CsrPlugin_l1264_23;
reg execute_CsrPlugin_csr_4032;
reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_2;
reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_3;
reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_4;
reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_5;
reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_6;
reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_7;
reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_8;
reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_9;
reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_10;
reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_11;
reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_12;
reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_13;
reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_14;
reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_15;
reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_16;
reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_17;
reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_18;
reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_19;
reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_20;
reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_21;
reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_22;
reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_23;
reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_24;
wire when_CsrPlugin_l1297;
wire when_CsrPlugin_l1302;
reg [2:0] _zz_iBusWishbone_ADR;
wire when_InstructionCache_l239;
reg _zz_iBus_rsp_valid;
reg [31:0] iBusWishbone_DAT_MISO_regNext;
reg [2:0] _zz_dBus_cmd_ready;
wire _zz_dBus_cmd_ready_1;
wire _zz_dBus_cmd_ready_2;
wire _zz_dBus_cmd_ready_3;
wire _zz_dBus_cmd_ready_4;
wire _zz_dBus_cmd_ready_5;
reg _zz_dBus_rsp_valid;
reg [31:0] dBusWishbone_DAT_MISO_regNext;
`ifndef SYNTHESIS
reg [39:0] decode_CfuPlugin_CFU_INPUT_2_KIND_string;
reg [39:0] _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_string;
reg [39:0] _zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_string;
reg [39:0] _zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_1_string;
reg [39:0] _zz_memory_to_writeBack_ENV_CTRL_string;
reg [39:0] _zz_memory_to_writeBack_ENV_CTRL_1_string;
reg [39:0] _zz_execute_to_memory_ENV_CTRL_string;
reg [39:0] _zz_execute_to_memory_ENV_CTRL_1_string;
reg [39:0] decode_ENV_CTRL_string;
reg [39:0] _zz_decode_ENV_CTRL_string;
reg [39:0] _zz_decode_to_execute_ENV_CTRL_string;
reg [39:0] _zz_decode_to_execute_ENV_CTRL_1_string;
reg [31:0] _zz_decode_to_execute_BRANCH_CTRL_string;
reg [31:0] _zz_decode_to_execute_BRANCH_CTRL_1_string;
reg [71:0] _zz_execute_to_memory_SHIFT_CTRL_string;
reg [71:0] _zz_execute_to_memory_SHIFT_CTRL_1_string;
reg [71:0] decode_SHIFT_CTRL_string;
reg [71:0] _zz_decode_SHIFT_CTRL_string;
reg [71:0] _zz_decode_to_execute_SHIFT_CTRL_string;
reg [71:0] _zz_decode_to_execute_SHIFT_CTRL_1_string;
reg [39:0] decode_ALU_BITWISE_CTRL_string;
reg [39:0] _zz_decode_ALU_BITWISE_CTRL_string;
reg [39:0] _zz_decode_to_execute_ALU_BITWISE_CTRL_string;
reg [39:0] _zz_decode_to_execute_ALU_BITWISE_CTRL_1_string;
reg [23:0] decode_SRC2_CTRL_string;
reg [23:0] _zz_decode_SRC2_CTRL_string;
reg [23:0] _zz_decode_to_execute_SRC2_CTRL_string;
reg [23:0] _zz_decode_to_execute_SRC2_CTRL_1_string;
reg [63:0] decode_ALU_CTRL_string;
reg [63:0] _zz_decode_ALU_CTRL_string;
reg [63:0] _zz_decode_to_execute_ALU_CTRL_string;
reg [63:0] _zz_decode_to_execute_ALU_CTRL_1_string;
reg [95:0] decode_SRC1_CTRL_string;
reg [95:0] _zz_decode_SRC1_CTRL_string;
reg [95:0] _zz_decode_to_execute_SRC1_CTRL_string;
reg [95:0] _zz_decode_to_execute_SRC1_CTRL_1_string;
reg [39:0] execute_CfuPlugin_CFU_INPUT_2_KIND_string;
reg [39:0] _zz_execute_CfuPlugin_CFU_INPUT_2_KIND_string;
reg [39:0] memory_ENV_CTRL_string;
reg [39:0] _zz_memory_ENV_CTRL_string;
reg [39:0] execute_ENV_CTRL_string;
reg [39:0] _zz_execute_ENV_CTRL_string;
reg [39:0] writeBack_ENV_CTRL_string;
reg [39:0] _zz_writeBack_ENV_CTRL_string;
reg [31:0] execute_BRANCH_CTRL_string;
reg [31:0] _zz_execute_BRANCH_CTRL_string;
reg [71:0] memory_SHIFT_CTRL_string;
reg [71:0] _zz_memory_SHIFT_CTRL_string;
reg [71:0] execute_SHIFT_CTRL_string;
reg [71:0] _zz_execute_SHIFT_CTRL_string;
reg [23:0] execute_SRC2_CTRL_string;
reg [23:0] _zz_execute_SRC2_CTRL_string;
reg [95:0] execute_SRC1_CTRL_string;
reg [95:0] _zz_execute_SRC1_CTRL_string;
reg [63:0] execute_ALU_CTRL_string;
reg [63:0] _zz_execute_ALU_CTRL_string;
reg [39:0] execute_ALU_BITWISE_CTRL_string;
reg [39:0] _zz_execute_ALU_BITWISE_CTRL_string;
reg [39:0] _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_1_string;
reg [39:0] _zz_decode_ENV_CTRL_1_string;
reg [31:0] _zz_decode_BRANCH_CTRL_string;
reg [71:0] _zz_decode_SHIFT_CTRL_1_string;
reg [39:0] _zz_decode_ALU_BITWISE_CTRL_1_string;
reg [23:0] _zz_decode_SRC2_CTRL_1_string;
reg [63:0] _zz_decode_ALU_CTRL_1_string;
reg [95:0] _zz_decode_SRC1_CTRL_1_string;
reg [31:0] decode_BRANCH_CTRL_string;
reg [31:0] _zz_decode_BRANCH_CTRL_1_string;
reg [95:0] _zz_decode_SRC1_CTRL_2_string;
reg [63:0] _zz_decode_ALU_CTRL_2_string;
reg [23:0] _zz_decode_SRC2_CTRL_2_string;
reg [39:0] _zz_decode_ALU_BITWISE_CTRL_2_string;
reg [71:0] _zz_decode_SHIFT_CTRL_2_string;
reg [31:0] _zz_decode_BRANCH_CTRL_2_string;
reg [39:0] _zz_decode_ENV_CTRL_2_string;
reg [39:0] _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_8_string;
reg [95:0] decode_to_execute_SRC1_CTRL_string;
reg [63:0] decode_to_execute_ALU_CTRL_string;
reg [23:0] decode_to_execute_SRC2_CTRL_string;
reg [39:0] decode_to_execute_ALU_BITWISE_CTRL_string;
reg [71:0] decode_to_execute_SHIFT_CTRL_string;
reg [71:0] execute_to_memory_SHIFT_CTRL_string;
reg [31:0] decode_to_execute_BRANCH_CTRL_string;
reg [39:0] decode_to_execute_ENV_CTRL_string;
reg [39:0] execute_to_memory_ENV_CTRL_string;
reg [39:0] memory_to_writeBack_ENV_CTRL_string;
reg [39:0] decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_string;
`endif
(* ram_style = "block" *) reg [31:0] RegFilePlugin_regFile [0:31] /* verilator public */ ;
assign _zz_when = ({decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid} != 2'b00);
assign _zz_when_1 = ({CsrPlugin_selfException_valid,BranchPlugin_branchExceptionPort_valid} != 2'b00);
assign _zz_memory_MUL_LOW = ($signed(_zz_memory_MUL_LOW_1) + $signed(_zz_memory_MUL_LOW_5));
assign _zz_memory_MUL_LOW_1 = ($signed(_zz_memory_MUL_LOW_2) + $signed(_zz_memory_MUL_LOW_3));
assign _zz_memory_MUL_LOW_2 = 52'h0;
assign _zz_memory_MUL_LOW_4 = {1'b0,memory_MUL_LL};
assign _zz_memory_MUL_LOW_3 = {{19{_zz_memory_MUL_LOW_4[32]}}, _zz_memory_MUL_LOW_4};
assign _zz_memory_MUL_LOW_6 = ({16'd0,memory_MUL_LH} <<< 16);
assign _zz_memory_MUL_LOW_5 = {{2{_zz_memory_MUL_LOW_6[49]}}, _zz_memory_MUL_LOW_6};
assign _zz_memory_MUL_LOW_8 = ({16'd0,memory_MUL_HL} <<< 16);
assign _zz_memory_MUL_LOW_7 = {{2{_zz_memory_MUL_LOW_8[49]}}, _zz_memory_MUL_LOW_8};
assign _zz_execute_SHIFT_RIGHT_1 = ($signed(_zz_execute_SHIFT_RIGHT_2) >>> execute_FullBarrelShifterPlugin_amplitude);
assign _zz_execute_SHIFT_RIGHT = _zz_execute_SHIFT_RIGHT_1[31 : 0];
assign _zz_execute_SHIFT_RIGHT_2 = {((execute_SHIFT_CTRL == `ShiftCtrlEnum_binary_sequential_SRA_1) && execute_FullBarrelShifterPlugin_reversed[31]),execute_FullBarrelShifterPlugin_reversed};
assign _zz__zz_IBusCachedPlugin_jump_pcLoad_payload_1 = (_zz_IBusCachedPlugin_jump_pcLoad_payload - 4'b0001);
assign _zz_IBusCachedPlugin_fetchPc_pc_1 = {IBusCachedPlugin_fetchPc_inc,2'b00};
assign _zz_IBusCachedPlugin_fetchPc_pc = {29'd0, _zz_IBusCachedPlugin_fetchPc_pc_1};
assign _zz__zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]};
assign _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_2 = {{_zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0};
assign _zz__zz_2 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]};
assign _zz__zz_4 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]};
assign _zz__zz_6 = {{_zz_3,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}},1'b0};
assign _zz__zz_6_1 = {{_zz_5,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0};
assign _zz__zz_IBusCachedPlugin_predictionJumpInterface_payload = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]};
assign _zz__zz_IBusCachedPlugin_predictionJumpInterface_payload_2 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]};
assign _zz_DBusCachedPlugin_exceptionBus_payload_code = (writeBack_MEMORY_WR ? 3'b111 : 3'b101);
assign _zz_DBusCachedPlugin_exceptionBus_payload_code_1 = (writeBack_MEMORY_WR ? 3'b110 : 3'b100);
assign _zz__zz_execute_REGFILE_WRITE_DATA = execute_SRC_LESS;
assign _zz__zz_execute_SRC1 = 3'b100;
assign _zz__zz_execute_SRC1_1 = execute_INSTRUCTION[19 : 15];
assign _zz__zz_execute_SRC2_3 = {execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]};
assign _zz_execute_SrcPlugin_addSub = ($signed(_zz_execute_SrcPlugin_addSub_1) + $signed(_zz_execute_SrcPlugin_addSub_4));
assign _zz_execute_SrcPlugin_addSub_1 = ($signed(_zz_execute_SrcPlugin_addSub_2) + $signed(_zz_execute_SrcPlugin_addSub_3));
assign _zz_execute_SrcPlugin_addSub_2 = execute_SRC1;
assign _zz_execute_SrcPlugin_addSub_3 = (execute_SRC_USE_SUB_LESS ? (~ execute_SRC2) : execute_SRC2);
assign _zz_execute_SrcPlugin_addSub_4 = (execute_SRC_USE_SUB_LESS ? _zz_execute_SrcPlugin_addSub_5 : _zz_execute_SrcPlugin_addSub_6);
assign _zz_execute_SrcPlugin_addSub_5 = 32'h00000001;
assign _zz_execute_SrcPlugin_addSub_6 = 32'h0;
assign _zz__zz_execute_BranchPlugin_missAlignedTarget_2 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]};
assign _zz__zz_execute_BranchPlugin_missAlignedTarget_4 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]};
assign _zz__zz_execute_BranchPlugin_missAlignedTarget_6 = {_zz_execute_BranchPlugin_missAlignedTarget_1,execute_INSTRUCTION[31 : 20]};
assign _zz__zz_execute_BranchPlugin_missAlignedTarget_6_1 = {{_zz_execute_BranchPlugin_missAlignedTarget_3,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0};
assign _zz__zz_execute_BranchPlugin_missAlignedTarget_6_2 = {{_zz_execute_BranchPlugin_missAlignedTarget_5,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0};
assign _zz__zz_execute_BranchPlugin_branch_src2_2 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]};
assign _zz__zz_execute_BranchPlugin_branch_src2_4 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]};
assign _zz_execute_BranchPlugin_branch_src2_9 = 3'b100;
assign _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1 = (_zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code & (~ _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1_1));
assign _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1_1 = (_zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code - 2'b01);
assign _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_3 = (_zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_2 & (~ _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_3_1));
assign _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_3_1 = (_zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_2 - 2'b01);
assign _zz_writeBack_MulPlugin_result = {{14{writeBack_MUL_LOW[51]}}, writeBack_MUL_LOW};
assign _zz_writeBack_MulPlugin_result_1 = ({32'd0,writeBack_MUL_HH} <<< 32);
assign _zz__zz_decode_RS2_2 = writeBack_MUL_LOW[31 : 0];
assign _zz__zz_decode_RS2_2_1 = writeBack_MulPlugin_result[63 : 32];
assign _zz_memory_DivPlugin_div_counter_valueNext_1 = memory_DivPlugin_div_counter_willIncrement;
assign _zz_memory_DivPlugin_div_counter_valueNext = {5'd0, _zz_memory_DivPlugin_div_counter_valueNext_1};
assign _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator = {1'd0, memory_DivPlugin_rs2};
assign _zz_memory_DivPlugin_div_stage_0_outRemainder = memory_DivPlugin_div_stage_0_remainderMinusDenominator[31:0];
assign _zz_memory_DivPlugin_div_stage_0_outRemainder_1 = memory_DivPlugin_div_stage_0_remainderShifted[31:0];
assign _zz_memory_DivPlugin_div_stage_0_outNumerator = {_zz_memory_DivPlugin_div_stage_0_remainderShifted,(! memory_DivPlugin_div_stage_0_remainderMinusDenominator[32])};
assign _zz_memory_DivPlugin_div_result_1 = _zz_memory_DivPlugin_div_result_2;
assign _zz_memory_DivPlugin_div_result_2 = _zz_memory_DivPlugin_div_result_3;
assign _zz_memory_DivPlugin_div_result_3 = ({memory_DivPlugin_div_needRevert,(memory_DivPlugin_div_needRevert ? (~ _zz_memory_DivPlugin_div_result) : _zz_memory_DivPlugin_div_result)} + _zz_memory_DivPlugin_div_result_4);
assign _zz_memory_DivPlugin_div_result_5 = memory_DivPlugin_div_needRevert;
assign _zz_memory_DivPlugin_div_result_4 = {32'd0, _zz_memory_DivPlugin_div_result_5};
assign _zz_memory_DivPlugin_rs1_3 = _zz_memory_DivPlugin_rs1;
assign _zz_memory_DivPlugin_rs1_2 = {32'd0, _zz_memory_DivPlugin_rs1_3};
assign _zz_memory_DivPlugin_rs2_2 = _zz_memory_DivPlugin_rs2;
assign _zz_memory_DivPlugin_rs2_1 = {31'd0, _zz_memory_DivPlugin_rs2_2};
assign _zz_execute_CfuPlugin_functionsIds_0 = {execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[14 : 12]};
assign _zz_iBusWishbone_ADR_1 = (iBus_cmd_payload_address >>> 5);
assign _zz_decode_RegFilePlugin_rs1Data = 1'b1;
assign _zz_decode_RegFilePlugin_rs2Data = 1'b1;
assign _zz_IBusCachedPlugin_jump_pcLoad_payload_6 = {_zz_IBusCachedPlugin_jump_pcLoad_payload_4,_zz_IBusCachedPlugin_jump_pcLoad_payload_3};
assign _zz_writeBack_DBusCachedPlugin_rspShifted_1 = dataCache_1_io_cpu_writeBack_address[1 : 0];
assign _zz_writeBack_DBusCachedPlugin_rspShifted_3 = dataCache_1_io_cpu_writeBack_address[1 : 1];
assign _zz_decode_LEGAL_INSTRUCTION = 32'h0000106f;
assign _zz_decode_LEGAL_INSTRUCTION_1 = (decode_INSTRUCTION & 32'h0000107f);
assign _zz_decode_LEGAL_INSTRUCTION_2 = 32'h00001073;
assign _zz_decode_LEGAL_INSTRUCTION_3 = ((decode_INSTRUCTION & 32'h0000207f) == 32'h00002073);
assign _zz_decode_LEGAL_INSTRUCTION_4 = ((decode_INSTRUCTION & 32'h0000407f) == 32'h00004063);
assign _zz_decode_LEGAL_INSTRUCTION_5 = {((decode_INSTRUCTION & 32'h0000207f) == 32'h00002013),{((decode_INSTRUCTION & 32'h0000603f) == 32'h00000023),{((decode_INSTRUCTION & _zz_decode_LEGAL_INSTRUCTION_6) == 32'h00000003),{(_zz_decode_LEGAL_INSTRUCTION_7 == _zz_decode_LEGAL_INSTRUCTION_8),{_zz_decode_LEGAL_INSTRUCTION_9,{_zz_decode_LEGAL_INSTRUCTION_10,_zz_decode_LEGAL_INSTRUCTION_11}}}}}};
assign _zz_decode_LEGAL_INSTRUCTION_6 = 32'h0000207f;
assign _zz_decode_LEGAL_INSTRUCTION_7 = (decode_INSTRUCTION & 32'h0000505f);
assign _zz_decode_LEGAL_INSTRUCTION_8 = 32'h00000003;
assign _zz_decode_LEGAL_INSTRUCTION_9 = ((decode_INSTRUCTION & 32'h0000707b) == 32'h00000063);
assign _zz_decode_LEGAL_INSTRUCTION_10 = ((decode_INSTRUCTION & 32'h0000607f) == 32'h0000000f);
assign _zz_decode_LEGAL_INSTRUCTION_11 = {((decode_INSTRUCTION & 32'hfc00007f) == 32'h00000033),{((decode_INSTRUCTION & 32'h01f0707f) == 32'h0000500f),{((decode_INSTRUCTION & _zz_decode_LEGAL_INSTRUCTION_12) == 32'h00005013),{(_zz_decode_LEGAL_INSTRUCTION_13 == _zz_decode_LEGAL_INSTRUCTION_14),{_zz_decode_LEGAL_INSTRUCTION_15,{_zz_decode_LEGAL_INSTRUCTION_16,_zz_decode_LEGAL_INSTRUCTION_17}}}}}};
assign _zz_decode_LEGAL_INSTRUCTION_12 = 32'hbc00707f;
assign _zz_decode_LEGAL_INSTRUCTION_13 = (decode_INSTRUCTION & 32'hfc00307f);
assign _zz_decode_LEGAL_INSTRUCTION_14 = 32'h00001013;
assign _zz_decode_LEGAL_INSTRUCTION_15 = ((decode_INSTRUCTION & 32'hbe00707f) == 32'h00005033);
assign _zz_decode_LEGAL_INSTRUCTION_16 = ((decode_INSTRUCTION & 32'hbe00707f) == 32'h00000033);
assign _zz_decode_LEGAL_INSTRUCTION_17 = {((decode_INSTRUCTION & 32'hdfffffff) == 32'h10200073),{((decode_INSTRUCTION & 32'hffefffff) == 32'h00000073),((decode_INSTRUCTION & 32'hffffffff) == 32'h10500073)}};
assign _zz_IBusCachedPlugin_predictionJumpInterface_payload_4 = decode_INSTRUCTION[31];
assign _zz_IBusCachedPlugin_predictionJumpInterface_payload_5 = decode_INSTRUCTION[31];
assign _zz_IBusCachedPlugin_predictionJumpInterface_payload_6 = decode_INSTRUCTION[7];
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2 = (decode_INSTRUCTION & 32'h10103050);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_1 = 32'h00100050;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_2 = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_7;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_3 = 1'b0;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_4 = (((decode_INSTRUCTION & 32'h02004064) == 32'h02004020) != 1'b0);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_5 = (((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_6) == 32'h02000030) != 1'b0);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_7 = {({_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_8,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_9} != 2'b00),{(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_10 != 1'b0),{(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_11 != _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_16),{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_17,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_19,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_21}}}}};
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_6 = 32'h02004074;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_8 = ((decode_INSTRUCTION & 32'h10203050) == 32'h10000050);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_9 = ((decode_INSTRUCTION & 32'h10103050) == 32'h00000050);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_10 = ((decode_INSTRUCTION & 32'h00103050) == 32'h00000050);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_11 = {(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_12 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_13),(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_14 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_15)};
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_16 = 2'b00;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_17 = ({_zz_decode_CfuPlugin_CFU_INPUT_2_KIND_5,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_18} != 2'b00);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_19 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_20 != 1'b0);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_21 = {(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_22 != _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_27),{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_28,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_34,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_36}}};
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_12 = (decode_INSTRUCTION & 32'h00001050);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_13 = 32'h00001050;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_14 = (decode_INSTRUCTION & 32'h00002050);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_15 = 32'h00002050;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_18 = ((decode_INSTRUCTION & 32'h0000001c) == 32'h00000004);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_20 = ((decode_INSTRUCTION & 32'h00000058) == 32'h00000040);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_22 = {(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_23 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_24),(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_25 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_26)};
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_27 = 2'b00;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_28 = ({_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_29,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_30,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_32}} != 3'b000);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_34 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_35 != 1'b0);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_36 = {(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_37 != _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_39),{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_40,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_43,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_48}}};
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_23 = (decode_INSTRUCTION & 32'h00007034);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_24 = 32'h00005010;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_25 = (decode_INSTRUCTION & 32'h02007064);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_26 = 32'h00005020;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_29 = ((decode_INSTRUCTION & 32'h40003054) == 32'h40001010);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_30 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_31) == 32'h00001010);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_32 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_33) == 32'h00001010);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_35 = ((decode_INSTRUCTION & 32'h00000064) == 32'h00000024);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_37 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_38) == 32'h00001000);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_39 = 1'b0;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_40 = ((_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_41 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_42) != 1'b0);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_43 = ({_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_44,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_46} != 2'b00);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_48 = {(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_49 != _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_51),{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_52,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_57,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_71}}};
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_31 = 32'h00007034;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_33 = 32'h02007054;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_38 = 32'h00001000;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_41 = (decode_INSTRUCTION & 32'h00003000);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_42 = 32'h00002000;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_44 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_45) == 32'h00002000);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_46 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_47) == 32'h00001000);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_49 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_50) == 32'h00004004);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_51 = 1'b0;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_52 = ({_zz_decode_CfuPlugin_CFU_INPUT_2_KIND_6,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_53,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_55}} != 3'b000);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_57 = ({_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_58,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_60} != 5'h0);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_71 = {(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_72 != _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_74),{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_75,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_90,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_103}}};
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_45 = 32'h00002010;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_47 = 32'h00005000;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_50 = 32'h00004054;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_53 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_54) == 32'h00000020);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_55 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_56) == 32'h00000020);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_58 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_59) == 32'h00002040);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_60 = {(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_61 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_62),{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_63,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_65,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_68}}};
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_72 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_73) == 32'h00000020);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_74 = 1'b0;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_75 = ({_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_76,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_78,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_81}} != 6'h0);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_90 = ({_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_91,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_92} != 5'h0);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_103 = {(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_104 != _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_117),{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_118,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_123,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_128}}};
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_54 = 32'h00000034;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_56 = 32'h00000064;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_59 = 32'h00002040;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_61 = (decode_INSTRUCTION & 32'h00001040);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_62 = 32'h00001040;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_63 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_64) == 32'h00000040);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_65 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_66 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_67);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_68 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_69 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_70);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_73 = 32'h00000020;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_76 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_77) == 32'h00000008);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_78 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_79 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_80);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_81 = {_zz_decode_CfuPlugin_CFU_INPUT_2_KIND_4,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_82,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_85}};
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_91 = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_4;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_92 = {_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_93,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_95,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_98}};
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_104 = {_zz_decode_CfuPlugin_CFU_INPUT_2_KIND_5,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_105,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_108}};
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_117 = 6'h0;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_118 = ({_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_119,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_120} != 2'b00);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_123 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_124 != _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_127);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_128 = {_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_129,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_132,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_137}};
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_64 = 32'h00100040;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_66 = (decode_INSTRUCTION & 32'h00000050);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_67 = 32'h00000040;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_69 = (decode_INSTRUCTION & 32'h00000038);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_70 = 32'h0;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_77 = 32'h00000008;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_79 = (decode_INSTRUCTION & 32'h00000040);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_80 = 32'h00000040;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_82 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_83 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_84);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_85 = {_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_86,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_88};
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_93 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_94) == 32'h00002010);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_95 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_96 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_97);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_98 = {_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_99,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_101};
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_105 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_106 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_107);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_108 = {_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_109,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_111,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_114}};
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_119 = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_4;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_120 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_121 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_122);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_124 = {_zz_decode_CfuPlugin_CFU_INPUT_2_KIND_4,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_125};
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_127 = 2'b00;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_129 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_130 != 1'b0);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_132 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_133 != _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_136);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_137 = {_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_138,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_146,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_150}};
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_83 = (decode_INSTRUCTION & 32'h00004020);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_84 = 32'h00004020;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_86 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_87) == 32'h00000010);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_88 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_89) == 32'h00000020);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_94 = 32'h00002030;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_96 = (decode_INSTRUCTION & 32'h00001030);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_97 = 32'h00000010;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_99 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_100) == 32'h00002020);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_101 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_102) == 32'h00000020);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_106 = (decode_INSTRUCTION & 32'h00001010);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_107 = 32'h00001010;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_109 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_110) == 32'h00002010);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_111 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_112 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_113);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_114 = {_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_115,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_116};
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_121 = (decode_INSTRUCTION & 32'h00000070);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_122 = 32'h00000020;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_125 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_126) == 32'h0);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_130 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_131) == 32'h00004010);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_133 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_134 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_135);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_136 = 1'b0;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_138 = ({_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_139,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_141} != 4'b0000);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_146 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_147 != _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_149);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_150 = {_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_151,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_157,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_161}};
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_87 = 32'h00000030;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_89 = 32'h02000020;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_100 = 32'h02002060;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_102 = 32'h02003020;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_110 = 32'h00002010;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_112 = (decode_INSTRUCTION & 32'h00000050);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_113 = 32'h00000010;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_115 = ((decode_INSTRUCTION & 32'h0000000c) == 32'h00000004);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_116 = ((decode_INSTRUCTION & 32'h00000024) == 32'h0);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_126 = 32'h00000020;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_131 = 32'h00004014;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_134 = (decode_INSTRUCTION & 32'h00006014);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_135 = 32'h00002010;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_139 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_140) == 32'h0);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_141 = {(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_142 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_143),{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_144,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_145}};
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_147 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_148) == 32'h0);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_149 = 1'b0;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_151 = ({_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_152,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_153,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_155}} != 3'b000);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_157 = ({_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_158,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_160} != 2'b00);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_161 = {(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_162 != _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_165),(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_166 != _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_168)};
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_140 = 32'h00000044;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_142 = (decode_INSTRUCTION & 32'h00000018);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_143 = 32'h0;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_144 = ((decode_INSTRUCTION & 32'h00006004) == 32'h00002000);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_145 = ((decode_INSTRUCTION & 32'h00005004) == 32'h00001000);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_148 = 32'h00000058;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_152 = ((decode_INSTRUCTION & 32'h00000044) == 32'h00000040);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_153 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_154) == 32'h00002010);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_155 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_156) == 32'h40000030);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_158 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_159) == 32'h00000004);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_160 = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_3;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_162 = {(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_163 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_164),_zz_decode_CfuPlugin_CFU_INPUT_2_KIND_3};
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_165 = 2'b00;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_166 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_167) == 32'h00001004);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_168 = 1'b0;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_154 = 32'h00002014;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_156 = 32'h40000034;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_159 = 32'h00000014;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_163 = (decode_INSTRUCTION & 32'h00000044);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_164 = 32'h00000004;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_167 = 32'h00005054;
assign _zz_execute_BranchPlugin_branch_src2_6 = execute_INSTRUCTION[31];
assign _zz_execute_BranchPlugin_branch_src2_7 = execute_INSTRUCTION[31];
assign _zz_execute_BranchPlugin_branch_src2_8 = execute_INSTRUCTION[7];
assign _zz_CsrPlugin_csrMapping_readDataInit_25 = 32'h0;
always @(posedge clk) begin
if(_zz_decode_RegFilePlugin_rs1Data) begin
_zz_RegFilePlugin_regFile_port0 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress1];
end
end
always @(posedge clk) begin
if(_zz_decode_RegFilePlugin_rs2Data) begin
_zz_RegFilePlugin_regFile_port1 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress2];
end
end
always @(posedge clk) begin
if(_zz_1) begin
RegFilePlugin_regFile[lastStageRegFileWrite_payload_address] <= lastStageRegFileWrite_payload_data;
end
end
InstructionCache IBusCachedPlugin_cache (
.io_flush (IBusCachedPlugin_cache_io_flush ), //i
.io_cpu_prefetch_isValid (IBusCachedPlugin_cache_io_cpu_prefetch_isValid ), //i
.io_cpu_prefetch_haltIt (IBusCachedPlugin_cache_io_cpu_prefetch_haltIt ), //o
.io_cpu_prefetch_pc (IBusCachedPlugin_iBusRsp_stages_0_input_payload ), //i
.io_cpu_fetch_isValid (IBusCachedPlugin_cache_io_cpu_fetch_isValid ), //i
.io_cpu_fetch_isStuck (IBusCachedPlugin_cache_io_cpu_fetch_isStuck ), //i
.io_cpu_fetch_isRemoved (IBusCachedPlugin_cache_io_cpu_fetch_isRemoved ), //i
.io_cpu_fetch_pc (IBusCachedPlugin_iBusRsp_stages_1_input_payload ), //i
.io_cpu_fetch_data (IBusCachedPlugin_cache_io_cpu_fetch_data ), //o
.io_cpu_fetch_mmuRsp_physicalAddress (IBusCachedPlugin_mmuBus_rsp_physicalAddress ), //i
.io_cpu_fetch_mmuRsp_isIoAccess (IBusCachedPlugin_mmuBus_rsp_isIoAccess ), //i
.io_cpu_fetch_mmuRsp_isPaging (IBusCachedPlugin_mmuBus_rsp_isPaging ), //i
.io_cpu_fetch_mmuRsp_allowRead (IBusCachedPlugin_mmuBus_rsp_allowRead ), //i
.io_cpu_fetch_mmuRsp_allowWrite (IBusCachedPlugin_mmuBus_rsp_allowWrite ), //i
.io_cpu_fetch_mmuRsp_allowExecute (IBusCachedPlugin_mmuBus_rsp_allowExecute ), //i
.io_cpu_fetch_mmuRsp_exception (IBusCachedPlugin_mmuBus_rsp_exception ), //i
.io_cpu_fetch_mmuRsp_refilling (IBusCachedPlugin_mmuBus_rsp_refilling ), //i
.io_cpu_fetch_mmuRsp_bypassTranslation (IBusCachedPlugin_mmuBus_rsp_bypassTranslation ), //i
.io_cpu_fetch_physicalAddress (IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress ), //o
.io_cpu_decode_isValid (IBusCachedPlugin_cache_io_cpu_decode_isValid ), //i
.io_cpu_decode_isStuck (IBusCachedPlugin_cache_io_cpu_decode_isStuck ), //i
.io_cpu_decode_pc (IBusCachedPlugin_iBusRsp_stages_2_input_payload ), //i
.io_cpu_decode_physicalAddress (IBusCachedPlugin_cache_io_cpu_decode_physicalAddress ), //o
.io_cpu_decode_data (IBusCachedPlugin_cache_io_cpu_decode_data ), //o
.io_cpu_decode_cacheMiss (IBusCachedPlugin_cache_io_cpu_decode_cacheMiss ), //o
.io_cpu_decode_error (IBusCachedPlugin_cache_io_cpu_decode_error ), //o
.io_cpu_decode_mmuRefilling (IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling ), //o
.io_cpu_decode_mmuException (IBusCachedPlugin_cache_io_cpu_decode_mmuException ), //o
.io_cpu_decode_isUser (IBusCachedPlugin_cache_io_cpu_decode_isUser ), //i
.io_cpu_fill_valid (IBusCachedPlugin_cache_io_cpu_fill_valid ), //i
.io_cpu_fill_payload (IBusCachedPlugin_cache_io_cpu_decode_physicalAddress ), //i
.io_mem_cmd_valid (IBusCachedPlugin_cache_io_mem_cmd_valid ), //o
.io_mem_cmd_ready (iBus_cmd_ready ), //i
.io_mem_cmd_payload_address (IBusCachedPlugin_cache_io_mem_cmd_payload_address ), //o
.io_mem_cmd_payload_size (IBusCachedPlugin_cache_io_mem_cmd_payload_size ), //o
.io_mem_rsp_valid (iBus_rsp_valid ), //i
.io_mem_rsp_payload_data (iBus_rsp_payload_data ), //i
.io_mem_rsp_payload_error (iBus_rsp_payload_error ), //i
._zz_when_Fetcher_l398 (switch_Fetcher_l362 ), //i
._zz_io_cpu_fetch_data_regNextWhen (IBusCachedPlugin_injectionPort_payload ), //i
.clk (clk ), //i
.reset (reset ) //i
);
DataCache dataCache_1 (
.io_cpu_execute_isValid (dataCache_1_io_cpu_execute_isValid ), //i
.io_cpu_execute_address (dataCache_1_io_cpu_execute_address ), //i
.io_cpu_execute_haltIt (dataCache_1_io_cpu_execute_haltIt ), //o
.io_cpu_execute_args_wr (execute_MEMORY_WR ), //i
.io_cpu_execute_args_size (execute_DBusCachedPlugin_size ), //i
.io_cpu_execute_args_totalyConsistent (execute_MEMORY_FORCE_CONSTISTENCY ), //i
.io_cpu_execute_refilling (dataCache_1_io_cpu_execute_refilling ), //o
.io_cpu_memory_isValid (dataCache_1_io_cpu_memory_isValid ), //i
.io_cpu_memory_isStuck (memory_arbitration_isStuck ), //i
.io_cpu_memory_isWrite (dataCache_1_io_cpu_memory_isWrite ), //o
.io_cpu_memory_address (dataCache_1_io_cpu_memory_address ), //i
.io_cpu_memory_mmuRsp_physicalAddress (DBusCachedPlugin_mmuBus_rsp_physicalAddress ), //i
.io_cpu_memory_mmuRsp_isIoAccess (dataCache_1_io_cpu_memory_mmuRsp_isIoAccess ), //i
.io_cpu_memory_mmuRsp_isPaging (DBusCachedPlugin_mmuBus_rsp_isPaging ), //i
.io_cpu_memory_mmuRsp_allowRead (DBusCachedPlugin_mmuBus_rsp_allowRead ), //i
.io_cpu_memory_mmuRsp_allowWrite (DBusCachedPlugin_mmuBus_rsp_allowWrite ), //i
.io_cpu_memory_mmuRsp_allowExecute (DBusCachedPlugin_mmuBus_rsp_allowExecute ), //i
.io_cpu_memory_mmuRsp_exception (DBusCachedPlugin_mmuBus_rsp_exception ), //i
.io_cpu_memory_mmuRsp_refilling (DBusCachedPlugin_mmuBus_rsp_refilling ), //i
.io_cpu_memory_mmuRsp_bypassTranslation (DBusCachedPlugin_mmuBus_rsp_bypassTranslation ), //i
.io_cpu_writeBack_isValid (dataCache_1_io_cpu_writeBack_isValid ), //i
.io_cpu_writeBack_isStuck (writeBack_arbitration_isStuck ), //i
.io_cpu_writeBack_isUser (dataCache_1_io_cpu_writeBack_isUser ), //i
.io_cpu_writeBack_haltIt (dataCache_1_io_cpu_writeBack_haltIt ), //o
.io_cpu_writeBack_isWrite (dataCache_1_io_cpu_writeBack_isWrite ), //o
.io_cpu_writeBack_storeData (dataCache_1_io_cpu_writeBack_storeData ), //i
.io_cpu_writeBack_data (dataCache_1_io_cpu_writeBack_data ), //o
.io_cpu_writeBack_address (dataCache_1_io_cpu_writeBack_address ), //i
.io_cpu_writeBack_mmuException (dataCache_1_io_cpu_writeBack_mmuException ), //o
.io_cpu_writeBack_unalignedAccess (dataCache_1_io_cpu_writeBack_unalignedAccess ), //o
.io_cpu_writeBack_accessError (dataCache_1_io_cpu_writeBack_accessError ), //o
.io_cpu_writeBack_keepMemRspData (dataCache_1_io_cpu_writeBack_keepMemRspData ), //o
.io_cpu_writeBack_fence_SW (dataCache_1_io_cpu_writeBack_fence_SW ), //i
.io_cpu_writeBack_fence_SR (dataCache_1_io_cpu_writeBack_fence_SR ), //i
.io_cpu_writeBack_fence_SO (dataCache_1_io_cpu_writeBack_fence_SO ), //i
.io_cpu_writeBack_fence_SI (dataCache_1_io_cpu_writeBack_fence_SI ), //i
.io_cpu_writeBack_fence_PW (dataCache_1_io_cpu_writeBack_fence_PW ), //i
.io_cpu_writeBack_fence_PR (dataCache_1_io_cpu_writeBack_fence_PR ), //i
.io_cpu_writeBack_fence_PO (dataCache_1_io_cpu_writeBack_fence_PO ), //i
.io_cpu_writeBack_fence_PI (dataCache_1_io_cpu_writeBack_fence_PI ), //i
.io_cpu_writeBack_fence_FM (dataCache_1_io_cpu_writeBack_fence_FM ), //i
.io_cpu_writeBack_exclusiveOk (dataCache_1_io_cpu_writeBack_exclusiveOk ), //o
.io_cpu_redo (dataCache_1_io_cpu_redo ), //o
.io_cpu_flush_valid (dataCache_1_io_cpu_flush_valid ), //i
.io_cpu_flush_ready (dataCache_1_io_cpu_flush_ready ), //o
.io_mem_cmd_valid (dataCache_1_io_mem_cmd_valid ), //o
.io_mem_cmd_ready (dataCache_1_io_mem_cmd_ready ), //i
.io_mem_cmd_payload_wr (dataCache_1_io_mem_cmd_payload_wr ), //o
.io_mem_cmd_payload_uncached (dataCache_1_io_mem_cmd_payload_uncached ), //o
.io_mem_cmd_payload_address (dataCache_1_io_mem_cmd_payload_address ), //o
.io_mem_cmd_payload_data (dataCache_1_io_mem_cmd_payload_data ), //o
.io_mem_cmd_payload_mask (dataCache_1_io_mem_cmd_payload_mask ), //o
.io_mem_cmd_payload_size (dataCache_1_io_mem_cmd_payload_size ), //o
.io_mem_cmd_payload_last (dataCache_1_io_mem_cmd_payload_last ), //o
.io_mem_rsp_valid (dBus_rsp_valid ), //i
.io_mem_rsp_payload_last (dBus_rsp_payload_last ), //i
.io_mem_rsp_payload_data (dBus_rsp_payload_data ), //i
.io_mem_rsp_payload_error (dBus_rsp_payload_error ), //i
.clk (clk ), //i
.reset (reset ) //i
);
always @(*) begin
case(_zz_IBusCachedPlugin_jump_pcLoad_payload_6)
2'b00 : begin
_zz_IBusCachedPlugin_jump_pcLoad_payload_5 = DBusCachedPlugin_redoBranch_payload;
end
2'b01 : begin
_zz_IBusCachedPlugin_jump_pcLoad_payload_5 = CsrPlugin_jumpInterface_payload;
end
2'b10 : begin
_zz_IBusCachedPlugin_jump_pcLoad_payload_5 = BranchPlugin_jumpInterface_payload;
end
default : begin
_zz_IBusCachedPlugin_jump_pcLoad_payload_5 = IBusCachedPlugin_predictionJumpInterface_payload;
end
endcase
end
always @(*) begin
case(_zz_writeBack_DBusCachedPlugin_rspShifted_1)
2'b00 : begin
_zz_writeBack_DBusCachedPlugin_rspShifted = writeBack_DBusCachedPlugin_rspSplits_0;
end
2'b01 : begin
_zz_writeBack_DBusCachedPlugin_rspShifted = writeBack_DBusCachedPlugin_rspSplits_1;
end
2'b10 : begin
_zz_writeBack_DBusCachedPlugin_rspShifted = writeBack_DBusCachedPlugin_rspSplits_2;
end
default : begin
_zz_writeBack_DBusCachedPlugin_rspShifted = writeBack_DBusCachedPlugin_rspSplits_3;
end
endcase
end
always @(*) begin
case(_zz_writeBack_DBusCachedPlugin_rspShifted_3)
1'b0 : begin
_zz_writeBack_DBusCachedPlugin_rspShifted_2 = writeBack_DBusCachedPlugin_rspSplits_1;
end
default : begin
_zz_writeBack_DBusCachedPlugin_rspShifted_2 = writeBack_DBusCachedPlugin_rspSplits_3;
end
endcase
end
`ifndef SYNTHESIS
always @(*) begin
case(decode_CfuPlugin_CFU_INPUT_2_KIND)
`Input2Kind_binary_sequential_RS : decode_CfuPlugin_CFU_INPUT_2_KIND_string = "RS ";
`Input2Kind_binary_sequential_IMM_I : decode_CfuPlugin_CFU_INPUT_2_KIND_string = "IMM_I";
default : decode_CfuPlugin_CFU_INPUT_2_KIND_string = "?????";
endcase
end
always @(*) begin
case(_zz_decode_CfuPlugin_CFU_INPUT_2_KIND)
`Input2Kind_binary_sequential_RS : _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_string = "RS ";
`Input2Kind_binary_sequential_IMM_I : _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_string = "IMM_I";
default : _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_string = "?????";
endcase
end
always @(*) begin
case(_zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND)
`Input2Kind_binary_sequential_RS : _zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_string = "RS ";
`Input2Kind_binary_sequential_IMM_I : _zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_string = "IMM_I";
default : _zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_string = "?????";
endcase
end
always @(*) begin
case(_zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_1)
`Input2Kind_binary_sequential_RS : _zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_1_string = "RS ";
`Input2Kind_binary_sequential_IMM_I : _zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_1_string = "IMM_I";
default : _zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_1_string = "?????";
endcase
end
always @(*) begin
case(_zz_memory_to_writeBack_ENV_CTRL)
`EnvCtrlEnum_binary_sequential_NONE : _zz_memory_to_writeBack_ENV_CTRL_string = "NONE ";
`EnvCtrlEnum_binary_sequential_XRET : _zz_memory_to_writeBack_ENV_CTRL_string = "XRET ";
`EnvCtrlEnum_binary_sequential_WFI : _zz_memory_to_writeBack_ENV_CTRL_string = "WFI ";
`EnvCtrlEnum_binary_sequential_ECALL : _zz_memory_to_writeBack_ENV_CTRL_string = "ECALL";
default : _zz_memory_to_writeBack_ENV_CTRL_string = "?????";
endcase
end
always @(*) begin
case(_zz_memory_to_writeBack_ENV_CTRL_1)
`EnvCtrlEnum_binary_sequential_NONE : _zz_memory_to_writeBack_ENV_CTRL_1_string = "NONE ";
`EnvCtrlEnum_binary_sequential_XRET : _zz_memory_to_writeBack_ENV_CTRL_1_string = "XRET ";
`EnvCtrlEnum_binary_sequential_WFI : _zz_memory_to_writeBack_ENV_CTRL_1_string = "WFI ";
`EnvCtrlEnum_binary_sequential_ECALL : _zz_memory_to_writeBack_ENV_CTRL_1_string = "ECALL";
default : _zz_memory_to_writeBack_ENV_CTRL_1_string = "?????";
endcase
end
always @(*) begin
case(_zz_execute_to_memory_ENV_CTRL)
`EnvCtrlEnum_binary_sequential_NONE : _zz_execute_to_memory_ENV_CTRL_string = "NONE ";
`EnvCtrlEnum_binary_sequential_XRET : _zz_execute_to_memory_ENV_CTRL_string = "XRET ";
`EnvCtrlEnum_binary_sequential_WFI : _zz_execute_to_memory_ENV_CTRL_string = "WFI ";
`EnvCtrlEnum_binary_sequential_ECALL : _zz_execute_to_memory_ENV_CTRL_string = "ECALL";
default : _zz_execute_to_memory_ENV_CTRL_string = "?????";
endcase
end
always @(*) begin
case(_zz_execute_to_memory_ENV_CTRL_1)
`EnvCtrlEnum_binary_sequential_NONE : _zz_execute_to_memory_ENV_CTRL_1_string = "NONE ";
`EnvCtrlEnum_binary_sequential_XRET : _zz_execute_to_memory_ENV_CTRL_1_string = "XRET ";
`EnvCtrlEnum_binary_sequential_WFI : _zz_execute_to_memory_ENV_CTRL_1_string = "WFI ";
`EnvCtrlEnum_binary_sequential_ECALL : _zz_execute_to_memory_ENV_CTRL_1_string = "ECALL";
default : _zz_execute_to_memory_ENV_CTRL_1_string = "?????";
endcase
end
always @(*) begin
case(decode_ENV_CTRL)
`EnvCtrlEnum_binary_sequential_NONE : decode_ENV_CTRL_string = "NONE ";
`EnvCtrlEnum_binary_sequential_XRET : decode_ENV_CTRL_string = "XRET ";
`EnvCtrlEnum_binary_sequential_WFI : decode_ENV_CTRL_string = "WFI ";
`EnvCtrlEnum_binary_sequential_ECALL : decode_ENV_CTRL_string = "ECALL";
default : decode_ENV_CTRL_string = "?????";
endcase
end
always @(*) begin
case(_zz_decode_ENV_CTRL)
`EnvCtrlEnum_binary_sequential_NONE : _zz_decode_ENV_CTRL_string = "NONE ";
`EnvCtrlEnum_binary_sequential_XRET : _zz_decode_ENV_CTRL_string = "XRET ";
`EnvCtrlEnum_binary_sequential_WFI : _zz_decode_ENV_CTRL_string = "WFI ";
`EnvCtrlEnum_binary_sequential_ECALL : _zz_decode_ENV_CTRL_string = "ECALL";
default : _zz_decode_ENV_CTRL_string = "?????";
endcase
end
always @(*) begin
case(_zz_decode_to_execute_ENV_CTRL)
`EnvCtrlEnum_binary_sequential_NONE : _zz_decode_to_execute_ENV_CTRL_string = "NONE ";
`EnvCtrlEnum_binary_sequential_XRET : _zz_decode_to_execute_ENV_CTRL_string = "XRET ";
`EnvCtrlEnum_binary_sequential_WFI : _zz_decode_to_execute_ENV_CTRL_string = "WFI ";
`EnvCtrlEnum_binary_sequential_ECALL : _zz_decode_to_execute_ENV_CTRL_string = "ECALL";
default : _zz_decode_to_execute_ENV_CTRL_string = "?????";
endcase
end
always @(*) begin
case(_zz_decode_to_execute_ENV_CTRL_1)
`EnvCtrlEnum_binary_sequential_NONE : _zz_decode_to_execute_ENV_CTRL_1_string = "NONE ";
`EnvCtrlEnum_binary_sequential_XRET : _zz_decode_to_execute_ENV_CTRL_1_string = "XRET ";
`EnvCtrlEnum_binary_sequential_WFI : _zz_decode_to_execute_ENV_CTRL_1_string = "WFI ";
`EnvCtrlEnum_binary_sequential_ECALL : _zz_decode_to_execute_ENV_CTRL_1_string = "ECALL";
default : _zz_decode_to_execute_ENV_CTRL_1_string = "?????";
endcase
end
always @(*) begin
case(_zz_decode_to_execute_BRANCH_CTRL)
`BranchCtrlEnum_binary_sequential_INC : _zz_decode_to_execute_BRANCH_CTRL_string = "INC ";
`BranchCtrlEnum_binary_sequential_B : _zz_decode_to_execute_BRANCH_CTRL_string = "B ";
`BranchCtrlEnum_binary_sequential_JAL : _zz_decode_to_execute_BRANCH_CTRL_string = "JAL ";
`BranchCtrlEnum_binary_sequential_JALR : _zz_decode_to_execute_BRANCH_CTRL_string = "JALR";
default : _zz_decode_to_execute_BRANCH_CTRL_string = "????";
endcase
end
always @(*) begin
case(_zz_decode_to_execute_BRANCH_CTRL_1)
`BranchCtrlEnum_binary_sequential_INC : _zz_decode_to_execute_BRANCH_CTRL_1_string = "INC ";
`BranchCtrlEnum_binary_sequential_B : _zz_decode_to_execute_BRANCH_CTRL_1_string = "B ";
`BranchCtrlEnum_binary_sequential_JAL : _zz_decode_to_execute_BRANCH_CTRL_1_string = "JAL ";
`BranchCtrlEnum_binary_sequential_JALR : _zz_decode_to_execute_BRANCH_CTRL_1_string = "JALR";
default : _zz_decode_to_execute_BRANCH_CTRL_1_string = "????";
endcase
end
always @(*) begin
case(_zz_execute_to_memory_SHIFT_CTRL)
`ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_execute_to_memory_SHIFT_CTRL_string = "DISABLE_1";
`ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_execute_to_memory_SHIFT_CTRL_string = "SLL_1 ";
`ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_execute_to_memory_SHIFT_CTRL_string = "SRL_1 ";
`ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_execute_to_memory_SHIFT_CTRL_string = "SRA_1 ";
default : _zz_execute_to_memory_SHIFT_CTRL_string = "?????????";
endcase
end
always @(*) begin
case(_zz_execute_to_memory_SHIFT_CTRL_1)
`ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_execute_to_memory_SHIFT_CTRL_1_string = "DISABLE_1";
`ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_execute_to_memory_SHIFT_CTRL_1_string = "SLL_1 ";
`ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_execute_to_memory_SHIFT_CTRL_1_string = "SRL_1 ";
`ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_execute_to_memory_SHIFT_CTRL_1_string = "SRA_1 ";
default : _zz_execute_to_memory_SHIFT_CTRL_1_string = "?????????";
endcase
end
always @(*) begin
case(decode_SHIFT_CTRL)
`ShiftCtrlEnum_binary_sequential_DISABLE_1 : decode_SHIFT_CTRL_string = "DISABLE_1";
`ShiftCtrlEnum_binary_sequential_SLL_1 : decode_SHIFT_CTRL_string = "SLL_1 ";
`ShiftCtrlEnum_binary_sequential_SRL_1 : decode_SHIFT_CTRL_string = "SRL_1 ";
`ShiftCtrlEnum_binary_sequential_SRA_1 : decode_SHIFT_CTRL_string = "SRA_1 ";
default : decode_SHIFT_CTRL_string = "?????????";
endcase
end
always @(*) begin
case(_zz_decode_SHIFT_CTRL)
`ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_decode_SHIFT_CTRL_string = "DISABLE_1";
`ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_decode_SHIFT_CTRL_string = "SLL_1 ";
`ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_decode_SHIFT_CTRL_string = "SRL_1 ";
`ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_decode_SHIFT_CTRL_string = "SRA_1 ";
default : _zz_decode_SHIFT_CTRL_string = "?????????";
endcase
end
always @(*) begin
case(_zz_decode_to_execute_SHIFT_CTRL)
`ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_decode_to_execute_SHIFT_CTRL_string = "DISABLE_1";
`ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_decode_to_execute_SHIFT_CTRL_string = "SLL_1 ";
`ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_decode_to_execute_SHIFT_CTRL_string = "SRL_1 ";
`ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_decode_to_execute_SHIFT_CTRL_string = "SRA_1 ";
default : _zz_decode_to_execute_SHIFT_CTRL_string = "?????????";
endcase
end
always @(*) begin
case(_zz_decode_to_execute_SHIFT_CTRL_1)
`ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_decode_to_execute_SHIFT_CTRL_1_string = "DISABLE_1";
`ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_decode_to_execute_SHIFT_CTRL_1_string = "SLL_1 ";
`ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_decode_to_execute_SHIFT_CTRL_1_string = "SRL_1 ";
`ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_decode_to_execute_SHIFT_CTRL_1_string = "SRA_1 ";
default : _zz_decode_to_execute_SHIFT_CTRL_1_string = "?????????";
endcase
end
always @(*) begin
case(decode_ALU_BITWISE_CTRL)
`AluBitwiseCtrlEnum_binary_sequential_XOR_1 : decode_ALU_BITWISE_CTRL_string = "XOR_1";
`AluBitwiseCtrlEnum_binary_sequential_OR_1 : decode_ALU_BITWISE_CTRL_string = "OR_1 ";
`AluBitwiseCtrlEnum_binary_sequential_AND_1 : decode_ALU_BITWISE_CTRL_string = "AND_1";
default : decode_ALU_BITWISE_CTRL_string = "?????";
endcase
end
always @(*) begin
case(_zz_decode_ALU_BITWISE_CTRL)
`AluBitwiseCtrlEnum_binary_sequential_XOR_1 : _zz_decode_ALU_BITWISE_CTRL_string = "XOR_1";
`AluBitwiseCtrlEnum_binary_sequential_OR_1 : _zz_decode_ALU_BITWISE_CTRL_string = "OR_1 ";
`AluBitwiseCtrlEnum_binary_sequential_AND_1 : _zz_decode_ALU_BITWISE_CTRL_string = "AND_1";
default : _zz_decode_ALU_BITWISE_CTRL_string = "?????";
endcase
end
always @(*) begin
case(_zz_decode_to_execute_ALU_BITWISE_CTRL)
`AluBitwiseCtrlEnum_binary_sequential_XOR_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_string = "XOR_1";
`AluBitwiseCtrlEnum_binary_sequential_OR_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_string = "OR_1 ";
`AluBitwiseCtrlEnum_binary_sequential_AND_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_string = "AND_1";
default : _zz_decode_to_execute_ALU_BITWISE_CTRL_string = "?????";
endcase
end
always @(*) begin
case(_zz_decode_to_execute_ALU_BITWISE_CTRL_1)
`AluBitwiseCtrlEnum_binary_sequential_XOR_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_1_string = "XOR_1";
`AluBitwiseCtrlEnum_binary_sequential_OR_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_1_string = "OR_1 ";
`AluBitwiseCtrlEnum_binary_sequential_AND_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_1_string = "AND_1";
default : _zz_decode_to_execute_ALU_BITWISE_CTRL_1_string = "?????";
endcase
end
always @(*) begin
case(decode_SRC2_CTRL)
`Src2CtrlEnum_binary_sequential_RS : decode_SRC2_CTRL_string = "RS ";
`Src2CtrlEnum_binary_sequential_IMI : decode_SRC2_CTRL_string = "IMI";
`Src2CtrlEnum_binary_sequential_IMS : decode_SRC2_CTRL_string = "IMS";
`Src2CtrlEnum_binary_sequential_PC : decode_SRC2_CTRL_string = "PC ";
default : decode_SRC2_CTRL_string = "???";
endcase
end
always @(*) begin
case(_zz_decode_SRC2_CTRL)
`Src2CtrlEnum_binary_sequential_RS : _zz_decode_SRC2_CTRL_string = "RS ";
`Src2CtrlEnum_binary_sequential_IMI : _zz_decode_SRC2_CTRL_string = "IMI";
`Src2CtrlEnum_binary_sequential_IMS : _zz_decode_SRC2_CTRL_string = "IMS";
`Src2CtrlEnum_binary_sequential_PC : _zz_decode_SRC2_CTRL_string = "PC ";
default : _zz_decode_SRC2_CTRL_string = "???";
endcase
end
always @(*) begin
case(_zz_decode_to_execute_SRC2_CTRL)
`Src2CtrlEnum_binary_sequential_RS : _zz_decode_to_execute_SRC2_CTRL_string = "RS ";
`Src2CtrlEnum_binary_sequential_IMI : _zz_decode_to_execute_SRC2_CTRL_string = "IMI";
`Src2CtrlEnum_binary_sequential_IMS : _zz_decode_to_execute_SRC2_CTRL_string = "IMS";
`Src2CtrlEnum_binary_sequential_PC : _zz_decode_to_execute_SRC2_CTRL_string = "PC ";
default : _zz_decode_to_execute_SRC2_CTRL_string = "???";
endcase
end
always @(*) begin
case(_zz_decode_to_execute_SRC2_CTRL_1)
`Src2CtrlEnum_binary_sequential_RS : _zz_decode_to_execute_SRC2_CTRL_1_string = "RS ";
`Src2CtrlEnum_binary_sequential_IMI : _zz_decode_to_execute_SRC2_CTRL_1_string = "IMI";
`Src2CtrlEnum_binary_sequential_IMS : _zz_decode_to_execute_SRC2_CTRL_1_string = "IMS";
`Src2CtrlEnum_binary_sequential_PC : _zz_decode_to_execute_SRC2_CTRL_1_string = "PC ";
default : _zz_decode_to_execute_SRC2_CTRL_1_string = "???";
endcase
end
always @(*) begin
case(decode_ALU_CTRL)
`AluCtrlEnum_binary_sequential_ADD_SUB : decode_ALU_CTRL_string = "ADD_SUB ";
`AluCtrlEnum_binary_sequential_SLT_SLTU : decode_ALU_CTRL_string = "SLT_SLTU";
`AluCtrlEnum_binary_sequential_BITWISE : decode_ALU_CTRL_string = "BITWISE ";
default : decode_ALU_CTRL_string = "????????";
endcase
end
always @(*) begin
case(_zz_decode_ALU_CTRL)
`AluCtrlEnum_binary_sequential_ADD_SUB : _zz_decode_ALU_CTRL_string = "ADD_SUB ";
`AluCtrlEnum_binary_sequential_SLT_SLTU : _zz_decode_ALU_CTRL_string = "SLT_SLTU";
`AluCtrlEnum_binary_sequential_BITWISE : _zz_decode_ALU_CTRL_string = "BITWISE ";
default : _zz_decode_ALU_CTRL_string = "????????";
endcase
end
always @(*) begin
case(_zz_decode_to_execute_ALU_CTRL)
`AluCtrlEnum_binary_sequential_ADD_SUB : _zz_decode_to_execute_ALU_CTRL_string = "ADD_SUB ";
`AluCtrlEnum_binary_sequential_SLT_SLTU : _zz_decode_to_execute_ALU_CTRL_string = "SLT_SLTU";
`AluCtrlEnum_binary_sequential_BITWISE : _zz_decode_to_execute_ALU_CTRL_string = "BITWISE ";
default : _zz_decode_to_execute_ALU_CTRL_string = "????????";
endcase
end
always @(*) begin
case(_zz_decode_to_execute_ALU_CTRL_1)
`AluCtrlEnum_binary_sequential_ADD_SUB : _zz_decode_to_execute_ALU_CTRL_1_string = "ADD_SUB ";
`AluCtrlEnum_binary_sequential_SLT_SLTU : _zz_decode_to_execute_ALU_CTRL_1_string = "SLT_SLTU";
`AluCtrlEnum_binary_sequential_BITWISE : _zz_decode_to_execute_ALU_CTRL_1_string = "BITWISE ";
default : _zz_decode_to_execute_ALU_CTRL_1_string = "????????";
endcase
end
always @(*) begin
case(decode_SRC1_CTRL)
`Src1CtrlEnum_binary_sequential_RS : decode_SRC1_CTRL_string = "RS ";
`Src1CtrlEnum_binary_sequential_IMU : decode_SRC1_CTRL_string = "IMU ";
`Src1CtrlEnum_binary_sequential_PC_INCREMENT : decode_SRC1_CTRL_string = "PC_INCREMENT";
`Src1CtrlEnum_binary_sequential_URS1 : decode_SRC1_CTRL_string = "URS1 ";
default : decode_SRC1_CTRL_string = "????????????";
endcase
end
always @(*) begin
case(_zz_decode_SRC1_CTRL)
`Src1CtrlEnum_binary_sequential_RS : _zz_decode_SRC1_CTRL_string = "RS ";
`Src1CtrlEnum_binary_sequential_IMU : _zz_decode_SRC1_CTRL_string = "IMU ";
`Src1CtrlEnum_binary_sequential_PC_INCREMENT : _zz_decode_SRC1_CTRL_string = "PC_INCREMENT";
`Src1CtrlEnum_binary_sequential_URS1 : _zz_decode_SRC1_CTRL_string = "URS1 ";
default : _zz_decode_SRC1_CTRL_string = "????????????";
endcase
end
always @(*) begin
case(_zz_decode_to_execute_SRC1_CTRL)
`Src1CtrlEnum_binary_sequential_RS : _zz_decode_to_execute_SRC1_CTRL_string = "RS ";
`Src1CtrlEnum_binary_sequential_IMU : _zz_decode_to_execute_SRC1_CTRL_string = "IMU ";
`Src1CtrlEnum_binary_sequential_PC_INCREMENT : _zz_decode_to_execute_SRC1_CTRL_string = "PC_INCREMENT";
`Src1CtrlEnum_binary_sequential_URS1 : _zz_decode_to_execute_SRC1_CTRL_string = "URS1 ";
default : _zz_decode_to_execute_SRC1_CTRL_string = "????????????";
endcase
end
always @(*) begin
case(_zz_decode_to_execute_SRC1_CTRL_1)
`Src1CtrlEnum_binary_sequential_RS : _zz_decode_to_execute_SRC1_CTRL_1_string = "RS ";
`Src1CtrlEnum_binary_sequential_IMU : _zz_decode_to_execute_SRC1_CTRL_1_string = "IMU ";
`Src1CtrlEnum_binary_sequential_PC_INCREMENT : _zz_decode_to_execute_SRC1_CTRL_1_string = "PC_INCREMENT";
`Src1CtrlEnum_binary_sequential_URS1 : _zz_decode_to_execute_SRC1_CTRL_1_string = "URS1 ";
default : _zz_decode_to_execute_SRC1_CTRL_1_string = "????????????";
endcase
end
always @(*) begin
case(execute_CfuPlugin_CFU_INPUT_2_KIND)
`Input2Kind_binary_sequential_RS : execute_CfuPlugin_CFU_INPUT_2_KIND_string = "RS ";
`Input2Kind_binary_sequential_IMM_I : execute_CfuPlugin_CFU_INPUT_2_KIND_string = "IMM_I";
default : execute_CfuPlugin_CFU_INPUT_2_KIND_string = "?????";
endcase
end
always @(*) begin
case(_zz_execute_CfuPlugin_CFU_INPUT_2_KIND)
`Input2Kind_binary_sequential_RS : _zz_execute_CfuPlugin_CFU_INPUT_2_KIND_string = "RS ";
`Input2Kind_binary_sequential_IMM_I : _zz_execute_CfuPlugin_CFU_INPUT_2_KIND_string = "IMM_I";
default : _zz_execute_CfuPlugin_CFU_INPUT_2_KIND_string = "?????";
endcase
end
always @(*) begin
case(memory_ENV_CTRL)
`EnvCtrlEnum_binary_sequential_NONE : memory_ENV_CTRL_string = "NONE ";
`EnvCtrlEnum_binary_sequential_XRET : memory_ENV_CTRL_string = "XRET ";
`EnvCtrlEnum_binary_sequential_WFI : memory_ENV_CTRL_string = "WFI ";
`EnvCtrlEnum_binary_sequential_ECALL : memory_ENV_CTRL_string = "ECALL";
default : memory_ENV_CTRL_string = "?????";
endcase
end
always @(*) begin
case(_zz_memory_ENV_CTRL)
`EnvCtrlEnum_binary_sequential_NONE : _zz_memory_ENV_CTRL_string = "NONE ";
`EnvCtrlEnum_binary_sequential_XRET : _zz_memory_ENV_CTRL_string = "XRET ";
`EnvCtrlEnum_binary_sequential_WFI : _zz_memory_ENV_CTRL_string = "WFI ";
`EnvCtrlEnum_binary_sequential_ECALL : _zz_memory_ENV_CTRL_string = "ECALL";
default : _zz_memory_ENV_CTRL_string = "?????";
endcase
end
always @(*) begin
case(execute_ENV_CTRL)
`EnvCtrlEnum_binary_sequential_NONE : execute_ENV_CTRL_string = "NONE ";
`EnvCtrlEnum_binary_sequential_XRET : execute_ENV_CTRL_string = "XRET ";
`EnvCtrlEnum_binary_sequential_WFI : execute_ENV_CTRL_string = "WFI ";
`EnvCtrlEnum_binary_sequential_ECALL : execute_ENV_CTRL_string = "ECALL";
default : execute_ENV_CTRL_string = "?????";
endcase
end
always @(*) begin
case(_zz_execute_ENV_CTRL)
`EnvCtrlEnum_binary_sequential_NONE : _zz_execute_ENV_CTRL_string = "NONE ";
`EnvCtrlEnum_binary_sequential_XRET : _zz_execute_ENV_CTRL_string = "XRET ";
`EnvCtrlEnum_binary_sequential_WFI : _zz_execute_ENV_CTRL_string = "WFI ";
`EnvCtrlEnum_binary_sequential_ECALL : _zz_execute_ENV_CTRL_string = "ECALL";
default : _zz_execute_ENV_CTRL_string = "?????";
endcase
end
always @(*) begin
case(writeBack_ENV_CTRL)
`EnvCtrlEnum_binary_sequential_NONE : writeBack_ENV_CTRL_string = "NONE ";
`EnvCtrlEnum_binary_sequential_XRET : writeBack_ENV_CTRL_string = "XRET ";
`EnvCtrlEnum_binary_sequential_WFI : writeBack_ENV_CTRL_string = "WFI ";
`EnvCtrlEnum_binary_sequential_ECALL : writeBack_ENV_CTRL_string = "ECALL";
default : writeBack_ENV_CTRL_string = "?????";
endcase
end
always @(*) begin
case(_zz_writeBack_ENV_CTRL)
`EnvCtrlEnum_binary_sequential_NONE : _zz_writeBack_ENV_CTRL_string = "NONE ";
`EnvCtrlEnum_binary_sequential_XRET : _zz_writeBack_ENV_CTRL_string = "XRET ";
`EnvCtrlEnum_binary_sequential_WFI : _zz_writeBack_ENV_CTRL_string = "WFI ";
`EnvCtrlEnum_binary_sequential_ECALL : _zz_writeBack_ENV_CTRL_string = "ECALL";
default : _zz_writeBack_ENV_CTRL_string = "?????";
endcase
end
always @(*) begin
case(execute_BRANCH_CTRL)
`BranchCtrlEnum_binary_sequential_INC : execute_BRANCH_CTRL_string = "INC ";
`BranchCtrlEnum_binary_sequential_B : execute_BRANCH_CTRL_string = "B ";
`BranchCtrlEnum_binary_sequential_JAL : execute_BRANCH_CTRL_string = "JAL ";
`BranchCtrlEnum_binary_sequential_JALR : execute_BRANCH_CTRL_string = "JALR";
default : execute_BRANCH_CTRL_string = "????";
endcase
end
always @(*) begin
case(_zz_execute_BRANCH_CTRL)
`BranchCtrlEnum_binary_sequential_INC : _zz_execute_BRANCH_CTRL_string = "INC ";
`BranchCtrlEnum_binary_sequential_B : _zz_execute_BRANCH_CTRL_string = "B ";
`BranchCtrlEnum_binary_sequential_JAL : _zz_execute_BRANCH_CTRL_string = "JAL ";
`BranchCtrlEnum_binary_sequential_JALR : _zz_execute_BRANCH_CTRL_string = "JALR";
default : _zz_execute_BRANCH_CTRL_string = "????";
endcase
end
always @(*) begin
case(memory_SHIFT_CTRL)
`ShiftCtrlEnum_binary_sequential_DISABLE_1 : memory_SHIFT_CTRL_string = "DISABLE_1";
`ShiftCtrlEnum_binary_sequential_SLL_1 : memory_SHIFT_CTRL_string = "SLL_1 ";
`ShiftCtrlEnum_binary_sequential_SRL_1 : memory_SHIFT_CTRL_string = "SRL_1 ";
`ShiftCtrlEnum_binary_sequential_SRA_1 : memory_SHIFT_CTRL_string = "SRA_1 ";
default : memory_SHIFT_CTRL_string = "?????????";
endcase
end
always @(*) begin
case(_zz_memory_SHIFT_CTRL)
`ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_memory_SHIFT_CTRL_string = "DISABLE_1";
`ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_memory_SHIFT_CTRL_string = "SLL_1 ";
`ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_memory_SHIFT_CTRL_string = "SRL_1 ";
`ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_memory_SHIFT_CTRL_string = "SRA_1 ";
default : _zz_memory_SHIFT_CTRL_string = "?????????";
endcase
end
always @(*) begin
case(execute_SHIFT_CTRL)
`ShiftCtrlEnum_binary_sequential_DISABLE_1 : execute_SHIFT_CTRL_string = "DISABLE_1";
`ShiftCtrlEnum_binary_sequential_SLL_1 : execute_SHIFT_CTRL_string = "SLL_1 ";
`ShiftCtrlEnum_binary_sequential_SRL_1 : execute_SHIFT_CTRL_string = "SRL_1 ";
`ShiftCtrlEnum_binary_sequential_SRA_1 : execute_SHIFT_CTRL_string = "SRA_1 ";
default : execute_SHIFT_CTRL_string = "?????????";
endcase
end
always @(*) begin
case(_zz_execute_SHIFT_CTRL)
`ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_execute_SHIFT_CTRL_string = "DISABLE_1";
`ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_execute_SHIFT_CTRL_string = "SLL_1 ";
`ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_execute_SHIFT_CTRL_string = "SRL_1 ";
`ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_execute_SHIFT_CTRL_string = "SRA_1 ";
default : _zz_execute_SHIFT_CTRL_string = "?????????";
endcase
end
always @(*) begin
case(execute_SRC2_CTRL)
`Src2CtrlEnum_binary_sequential_RS : execute_SRC2_CTRL_string = "RS ";
`Src2CtrlEnum_binary_sequential_IMI : execute_SRC2_CTRL_string = "IMI";
`Src2CtrlEnum_binary_sequential_IMS : execute_SRC2_CTRL_string = "IMS";
`Src2CtrlEnum_binary_sequential_PC : execute_SRC2_CTRL_string = "PC ";
default : execute_SRC2_CTRL_string = "???";
endcase
end
always @(*) begin
case(_zz_execute_SRC2_CTRL)
`Src2CtrlEnum_binary_sequential_RS : _zz_execute_SRC2_CTRL_string = "RS ";
`Src2CtrlEnum_binary_sequential_IMI : _zz_execute_SRC2_CTRL_string = "IMI";
`Src2CtrlEnum_binary_sequential_IMS : _zz_execute_SRC2_CTRL_string = "IMS";
`Src2CtrlEnum_binary_sequential_PC : _zz_execute_SRC2_CTRL_string = "PC ";
default : _zz_execute_SRC2_CTRL_string = "???";
endcase
end
always @(*) begin
case(execute_SRC1_CTRL)
`Src1CtrlEnum_binary_sequential_RS : execute_SRC1_CTRL_string = "RS ";
`Src1CtrlEnum_binary_sequential_IMU : execute_SRC1_CTRL_string = "IMU ";
`Src1CtrlEnum_binary_sequential_PC_INCREMENT : execute_SRC1_CTRL_string = "PC_INCREMENT";
`Src1CtrlEnum_binary_sequential_URS1 : execute_SRC1_CTRL_string = "URS1 ";
default : execute_SRC1_CTRL_string = "????????????";
endcase
end
always @(*) begin
case(_zz_execute_SRC1_CTRL)
`Src1CtrlEnum_binary_sequential_RS : _zz_execute_SRC1_CTRL_string = "RS ";
`Src1CtrlEnum_binary_sequential_IMU : _zz_execute_SRC1_CTRL_string = "IMU ";
`Src1CtrlEnum_binary_sequential_PC_INCREMENT : _zz_execute_SRC1_CTRL_string = "PC_INCREMENT";
`Src1CtrlEnum_binary_sequential_URS1 : _zz_execute_SRC1_CTRL_string = "URS1 ";
default : _zz_execute_SRC1_CTRL_string = "????????????";
endcase
end
always @(*) begin
case(execute_ALU_CTRL)
`AluCtrlEnum_binary_sequential_ADD_SUB : execute_ALU_CTRL_string = "ADD_SUB ";
`AluCtrlEnum_binary_sequential_SLT_SLTU : execute_ALU_CTRL_string = "SLT_SLTU";
`AluCtrlEnum_binary_sequential_BITWISE : execute_ALU_CTRL_string = "BITWISE ";
default : execute_ALU_CTRL_string = "????????";
endcase
end
always @(*) begin
case(_zz_execute_ALU_CTRL)
`AluCtrlEnum_binary_sequential_ADD_SUB : _zz_execute_ALU_CTRL_string = "ADD_SUB ";
`AluCtrlEnum_binary_sequential_SLT_SLTU : _zz_execute_ALU_CTRL_string = "SLT_SLTU";
`AluCtrlEnum_binary_sequential_BITWISE : _zz_execute_ALU_CTRL_string = "BITWISE ";
default : _zz_execute_ALU_CTRL_string = "????????";
endcase
end
always @(*) begin
case(execute_ALU_BITWISE_CTRL)
`AluBitwiseCtrlEnum_binary_sequential_XOR_1 : execute_ALU_BITWISE_CTRL_string = "XOR_1";
`AluBitwiseCtrlEnum_binary_sequential_OR_1 : execute_ALU_BITWISE_CTRL_string = "OR_1 ";
`AluBitwiseCtrlEnum_binary_sequential_AND_1 : execute_ALU_BITWISE_CTRL_string = "AND_1";
default : execute_ALU_BITWISE_CTRL_string = "?????";
endcase
end
always @(*) begin
case(_zz_execute_ALU_BITWISE_CTRL)
`AluBitwiseCtrlEnum_binary_sequential_XOR_1 : _zz_execute_ALU_BITWISE_CTRL_string = "XOR_1";
`AluBitwiseCtrlEnum_binary_sequential_OR_1 : _zz_execute_ALU_BITWISE_CTRL_string = "OR_1 ";
`AluBitwiseCtrlEnum_binary_sequential_AND_1 : _zz_execute_ALU_BITWISE_CTRL_string = "AND_1";
default : _zz_execute_ALU_BITWISE_CTRL_string = "?????";
endcase
end
always @(*) begin
case(_zz_decode_CfuPlugin_CFU_INPUT_2_KIND_1)
`Input2Kind_binary_sequential_RS : _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_1_string = "RS ";
`Input2Kind_binary_sequential_IMM_I : _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_1_string = "IMM_I";
default : _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_1_string = "?????";
endcase
end
always @(*) begin
case(_zz_decode_ENV_CTRL_1)
`EnvCtrlEnum_binary_sequential_NONE : _zz_decode_ENV_CTRL_1_string = "NONE ";
`EnvCtrlEnum_binary_sequential_XRET : _zz_decode_ENV_CTRL_1_string = "XRET ";
`EnvCtrlEnum_binary_sequential_WFI : _zz_decode_ENV_CTRL_1_string = "WFI ";
`EnvCtrlEnum_binary_sequential_ECALL : _zz_decode_ENV_CTRL_1_string = "ECALL";
default : _zz_decode_ENV_CTRL_1_string = "?????";
endcase
end
always @(*) begin
case(_zz_decode_BRANCH_CTRL)
`BranchCtrlEnum_binary_sequential_INC : _zz_decode_BRANCH_CTRL_string = "INC ";
`BranchCtrlEnum_binary_sequential_B : _zz_decode_BRANCH_CTRL_string = "B ";
`BranchCtrlEnum_binary_sequential_JAL : _zz_decode_BRANCH_CTRL_string = "JAL ";
`BranchCtrlEnum_binary_sequential_JALR : _zz_decode_BRANCH_CTRL_string = "JALR";
default : _zz_decode_BRANCH_CTRL_string = "????";
endcase
end
always @(*) begin
case(_zz_decode_SHIFT_CTRL_1)
`ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_decode_SHIFT_CTRL_1_string = "DISABLE_1";
`ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_decode_SHIFT_CTRL_1_string = "SLL_1 ";
`ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_decode_SHIFT_CTRL_1_string = "SRL_1 ";
`ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_decode_SHIFT_CTRL_1_string = "SRA_1 ";
default : _zz_decode_SHIFT_CTRL_1_string = "?????????";
endcase
end
always @(*) begin
case(_zz_decode_ALU_BITWISE_CTRL_1)
`AluBitwiseCtrlEnum_binary_sequential_XOR_1 : _zz_decode_ALU_BITWISE_CTRL_1_string = "XOR_1";
`AluBitwiseCtrlEnum_binary_sequential_OR_1 : _zz_decode_ALU_BITWISE_CTRL_1_string = "OR_1 ";
`AluBitwiseCtrlEnum_binary_sequential_AND_1 : _zz_decode_ALU_BITWISE_CTRL_1_string = "AND_1";
default : _zz_decode_ALU_BITWISE_CTRL_1_string = "?????";
endcase
end
always @(*) begin
case(_zz_decode_SRC2_CTRL_1)
`Src2CtrlEnum_binary_sequential_RS : _zz_decode_SRC2_CTRL_1_string = "RS ";
`Src2CtrlEnum_binary_sequential_IMI : _zz_decode_SRC2_CTRL_1_string = "IMI";
`Src2CtrlEnum_binary_sequential_IMS : _zz_decode_SRC2_CTRL_1_string = "IMS";
`Src2CtrlEnum_binary_sequential_PC : _zz_decode_SRC2_CTRL_1_string = "PC ";
default : _zz_decode_SRC2_CTRL_1_string = "???";
endcase
end
always @(*) begin
case(_zz_decode_ALU_CTRL_1)
`AluCtrlEnum_binary_sequential_ADD_SUB : _zz_decode_ALU_CTRL_1_string = "ADD_SUB ";
`AluCtrlEnum_binary_sequential_SLT_SLTU : _zz_decode_ALU_CTRL_1_string = "SLT_SLTU";
`AluCtrlEnum_binary_sequential_BITWISE : _zz_decode_ALU_CTRL_1_string = "BITWISE ";
default : _zz_decode_ALU_CTRL_1_string = "????????";
endcase
end
always @(*) begin
case(_zz_decode_SRC1_CTRL_1)
`Src1CtrlEnum_binary_sequential_RS : _zz_decode_SRC1_CTRL_1_string = "RS ";
`Src1CtrlEnum_binary_sequential_IMU : _zz_decode_SRC1_CTRL_1_string = "IMU ";
`Src1CtrlEnum_binary_sequential_PC_INCREMENT : _zz_decode_SRC1_CTRL_1_string = "PC_INCREMENT";
`Src1CtrlEnum_binary_sequential_URS1 : _zz_decode_SRC1_CTRL_1_string = "URS1 ";
default : _zz_decode_SRC1_CTRL_1_string = "????????????";
endcase
end
always @(*) begin
case(decode_BRANCH_CTRL)
`BranchCtrlEnum_binary_sequential_INC : decode_BRANCH_CTRL_string = "INC ";
`BranchCtrlEnum_binary_sequential_B : decode_BRANCH_CTRL_string = "B ";
`BranchCtrlEnum_binary_sequential_JAL : decode_BRANCH_CTRL_string = "JAL ";
`BranchCtrlEnum_binary_sequential_JALR : decode_BRANCH_CTRL_string = "JALR";
default : decode_BRANCH_CTRL_string = "????";
endcase
end
always @(*) begin
case(_zz_decode_BRANCH_CTRL_1)
`BranchCtrlEnum_binary_sequential_INC : _zz_decode_BRANCH_CTRL_1_string = "INC ";
`BranchCtrlEnum_binary_sequential_B : _zz_decode_BRANCH_CTRL_1_string = "B ";
`BranchCtrlEnum_binary_sequential_JAL : _zz_decode_BRANCH_CTRL_1_string = "JAL ";
`BranchCtrlEnum_binary_sequential_JALR : _zz_decode_BRANCH_CTRL_1_string = "JALR";
default : _zz_decode_BRANCH_CTRL_1_string = "????";
endcase
end
always @(*) begin
case(_zz_decode_SRC1_CTRL_2)
`Src1CtrlEnum_binary_sequential_RS : _zz_decode_SRC1_CTRL_2_string = "RS ";
`Src1CtrlEnum_binary_sequential_IMU : _zz_decode_SRC1_CTRL_2_string = "IMU ";
`Src1CtrlEnum_binary_sequential_PC_INCREMENT : _zz_decode_SRC1_CTRL_2_string = "PC_INCREMENT";
`Src1CtrlEnum_binary_sequential_URS1 : _zz_decode_SRC1_CTRL_2_string = "URS1 ";
default : _zz_decode_SRC1_CTRL_2_string = "????????????";
endcase
end
always @(*) begin
case(_zz_decode_ALU_CTRL_2)
`AluCtrlEnum_binary_sequential_ADD_SUB : _zz_decode_ALU_CTRL_2_string = "ADD_SUB ";
`AluCtrlEnum_binary_sequential_SLT_SLTU : _zz_decode_ALU_CTRL_2_string = "SLT_SLTU";
`AluCtrlEnum_binary_sequential_BITWISE : _zz_decode_ALU_CTRL_2_string = "BITWISE ";
default : _zz_decode_ALU_CTRL_2_string = "????????";
endcase
end
always @(*) begin
case(_zz_decode_SRC2_CTRL_2)
`Src2CtrlEnum_binary_sequential_RS : _zz_decode_SRC2_CTRL_2_string = "RS ";
`Src2CtrlEnum_binary_sequential_IMI : _zz_decode_SRC2_CTRL_2_string = "IMI";
`Src2CtrlEnum_binary_sequential_IMS : _zz_decode_SRC2_CTRL_2_string = "IMS";
`Src2CtrlEnum_binary_sequential_PC : _zz_decode_SRC2_CTRL_2_string = "PC ";
default : _zz_decode_SRC2_CTRL_2_string = "???";
endcase
end
always @(*) begin
case(_zz_decode_ALU_BITWISE_CTRL_2)
`AluBitwiseCtrlEnum_binary_sequential_XOR_1 : _zz_decode_ALU_BITWISE_CTRL_2_string = "XOR_1";
`AluBitwiseCtrlEnum_binary_sequential_OR_1 : _zz_decode_ALU_BITWISE_CTRL_2_string = "OR_1 ";
`AluBitwiseCtrlEnum_binary_sequential_AND_1 : _zz_decode_ALU_BITWISE_CTRL_2_string = "AND_1";
default : _zz_decode_ALU_BITWISE_CTRL_2_string = "?????";
endcase
end
always @(*) begin
case(_zz_decode_SHIFT_CTRL_2)
`ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_decode_SHIFT_CTRL_2_string = "DISABLE_1";
`ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_decode_SHIFT_CTRL_2_string = "SLL_1 ";
`ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_decode_SHIFT_CTRL_2_string = "SRL_1 ";
`ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_decode_SHIFT_CTRL_2_string = "SRA_1 ";
default : _zz_decode_SHIFT_CTRL_2_string = "?????????";
endcase
end
always @(*) begin
case(_zz_decode_BRANCH_CTRL_2)
`BranchCtrlEnum_binary_sequential_INC : _zz_decode_BRANCH_CTRL_2_string = "INC ";
`BranchCtrlEnum_binary_sequential_B : _zz_decode_BRANCH_CTRL_2_string = "B ";
`BranchCtrlEnum_binary_sequential_JAL : _zz_decode_BRANCH_CTRL_2_string = "JAL ";
`BranchCtrlEnum_binary_sequential_JALR : _zz_decode_BRANCH_CTRL_2_string = "JALR";
default : _zz_decode_BRANCH_CTRL_2_string = "????";
endcase
end
always @(*) begin
case(_zz_decode_ENV_CTRL_2)
`EnvCtrlEnum_binary_sequential_NONE : _zz_decode_ENV_CTRL_2_string = "NONE ";
`EnvCtrlEnum_binary_sequential_XRET : _zz_decode_ENV_CTRL_2_string = "XRET ";
`EnvCtrlEnum_binary_sequential_WFI : _zz_decode_ENV_CTRL_2_string = "WFI ";
`EnvCtrlEnum_binary_sequential_ECALL : _zz_decode_ENV_CTRL_2_string = "ECALL";
default : _zz_decode_ENV_CTRL_2_string = "?????";
endcase
end
always @(*) begin
case(_zz_decode_CfuPlugin_CFU_INPUT_2_KIND_8)
`Input2Kind_binary_sequential_RS : _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_8_string = "RS ";
`Input2Kind_binary_sequential_IMM_I : _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_8_string = "IMM_I";
default : _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_8_string = "?????";
endcase
end
always @(*) begin
case(decode_to_execute_SRC1_CTRL)
`Src1CtrlEnum_binary_sequential_RS : decode_to_execute_SRC1_CTRL_string = "RS ";
`Src1CtrlEnum_binary_sequential_IMU : decode_to_execute_SRC1_CTRL_string = "IMU ";
`Src1CtrlEnum_binary_sequential_PC_INCREMENT : decode_to_execute_SRC1_CTRL_string = "PC_INCREMENT";
`Src1CtrlEnum_binary_sequential_URS1 : decode_to_execute_SRC1_CTRL_string = "URS1 ";
default : decode_to_execute_SRC1_CTRL_string = "????????????";
endcase
end
always @(*) begin
case(decode_to_execute_ALU_CTRL)
`AluCtrlEnum_binary_sequential_ADD_SUB : decode_to_execute_ALU_CTRL_string = "ADD_SUB ";
`AluCtrlEnum_binary_sequential_SLT_SLTU : decode_to_execute_ALU_CTRL_string = "SLT_SLTU";
`AluCtrlEnum_binary_sequential_BITWISE : decode_to_execute_ALU_CTRL_string = "BITWISE ";
default : decode_to_execute_ALU_CTRL_string = "????????";
endcase
end
always @(*) begin
case(decode_to_execute_SRC2_CTRL)
`Src2CtrlEnum_binary_sequential_RS : decode_to_execute_SRC2_CTRL_string = "RS ";
`Src2CtrlEnum_binary_sequential_IMI : decode_to_execute_SRC2_CTRL_string = "IMI";
`Src2CtrlEnum_binary_sequential_IMS : decode_to_execute_SRC2_CTRL_string = "IMS";
`Src2CtrlEnum_binary_sequential_PC : decode_to_execute_SRC2_CTRL_string = "PC ";
default : decode_to_execute_SRC2_CTRL_string = "???";
endcase
end
always @(*) begin
case(decode_to_execute_ALU_BITWISE_CTRL)
`AluBitwiseCtrlEnum_binary_sequential_XOR_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "XOR_1";
`AluBitwiseCtrlEnum_binary_sequential_OR_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "OR_1 ";
`AluBitwiseCtrlEnum_binary_sequential_AND_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "AND_1";
default : decode_to_execute_ALU_BITWISE_CTRL_string = "?????";
endcase
end
always @(*) begin
case(decode_to_execute_SHIFT_CTRL)
`ShiftCtrlEnum_binary_sequential_DISABLE_1 : decode_to_execute_SHIFT_CTRL_string = "DISABLE_1";
`ShiftCtrlEnum_binary_sequential_SLL_1 : decode_to_execute_SHIFT_CTRL_string = "SLL_1 ";
`ShiftCtrlEnum_binary_sequential_SRL_1 : decode_to_execute_SHIFT_CTRL_string = "SRL_1 ";
`ShiftCtrlEnum_binary_sequential_SRA_1 : decode_to_execute_SHIFT_CTRL_string = "SRA_1 ";
default : decode_to_execute_SHIFT_CTRL_string = "?????????";
endcase
end
always @(*) begin
case(execute_to_memory_SHIFT_CTRL)
`ShiftCtrlEnum_binary_sequential_DISABLE_1 : execute_to_memory_SHIFT_CTRL_string = "DISABLE_1";
`ShiftCtrlEnum_binary_sequential_SLL_1 : execute_to_memory_SHIFT_CTRL_string = "SLL_1 ";
`ShiftCtrlEnum_binary_sequential_SRL_1 : execute_to_memory_SHIFT_CTRL_string = "SRL_1 ";
`ShiftCtrlEnum_binary_sequential_SRA_1 : execute_to_memory_SHIFT_CTRL_string = "SRA_1 ";
default : execute_to_memory_SHIFT_CTRL_string = "?????????";
endcase
end
always @(*) begin
case(decode_to_execute_BRANCH_CTRL)
`BranchCtrlEnum_binary_sequential_INC : decode_to_execute_BRANCH_CTRL_string = "INC ";
`BranchCtrlEnum_binary_sequential_B : decode_to_execute_BRANCH_CTRL_string = "B ";
`BranchCtrlEnum_binary_sequential_JAL : decode_to_execute_BRANCH_CTRL_string = "JAL ";
`BranchCtrlEnum_binary_sequential_JALR : decode_to_execute_BRANCH_CTRL_string = "JALR";
default : decode_to_execute_BRANCH_CTRL_string = "????";
endcase
end
always @(*) begin
case(decode_to_execute_ENV_CTRL)
`EnvCtrlEnum_binary_sequential_NONE : decode_to_execute_ENV_CTRL_string = "NONE ";
`EnvCtrlEnum_binary_sequential_XRET : decode_to_execute_ENV_CTRL_string = "XRET ";
`EnvCtrlEnum_binary_sequential_WFI : decode_to_execute_ENV_CTRL_string = "WFI ";
`EnvCtrlEnum_binary_sequential_ECALL : decode_to_execute_ENV_CTRL_string = "ECALL";
default : decode_to_execute_ENV_CTRL_string = "?????";
endcase
end
always @(*) begin
case(execute_to_memory_ENV_CTRL)
`EnvCtrlEnum_binary_sequential_NONE : execute_to_memory_ENV_CTRL_string = "NONE ";
`EnvCtrlEnum_binary_sequential_XRET : execute_to_memory_ENV_CTRL_string = "XRET ";
`EnvCtrlEnum_binary_sequential_WFI : execute_to_memory_ENV_CTRL_string = "WFI ";
`EnvCtrlEnum_binary_sequential_ECALL : execute_to_memory_ENV_CTRL_string = "ECALL";
default : execute_to_memory_ENV_CTRL_string = "?????";
endcase
end
always @(*) begin
case(memory_to_writeBack_ENV_CTRL)
`EnvCtrlEnum_binary_sequential_NONE : memory_to_writeBack_ENV_CTRL_string = "NONE ";
`EnvCtrlEnum_binary_sequential_XRET : memory_to_writeBack_ENV_CTRL_string = "XRET ";
`EnvCtrlEnum_binary_sequential_WFI : memory_to_writeBack_ENV_CTRL_string = "WFI ";
`EnvCtrlEnum_binary_sequential_ECALL : memory_to_writeBack_ENV_CTRL_string = "ECALL";
default : memory_to_writeBack_ENV_CTRL_string = "?????";
endcase
end
always @(*) begin
case(decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND)
`Input2Kind_binary_sequential_RS : decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_string = "RS ";
`Input2Kind_binary_sequential_IMM_I : decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_string = "IMM_I";
default : decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_string = "?????";
endcase
end
`endif
assign memory_MUL_LOW = ($signed(_zz_memory_MUL_LOW) + $signed(_zz_memory_MUL_LOW_7));
assign writeBack_CfuPlugin_CFU_IN_FLIGHT = memory_to_writeBack_CfuPlugin_CFU_IN_FLIGHT;
assign execute_CfuPlugin_CFU_IN_FLIGHT = ((execute_CfuPlugin_schedule || execute_CfuPlugin_hold) || execute_CfuPlugin_fired);
assign memory_MUL_HH = execute_to_memory_MUL_HH;
assign execute_MUL_HH = ($signed(execute_MulPlugin_aHigh) * $signed(execute_MulPlugin_bHigh));
assign execute_MUL_HL = ($signed(execute_MulPlugin_aHigh) * $signed(execute_MulPlugin_bSLow));
assign execute_MUL_LH = ($signed(execute_MulPlugin_aSLow) * $signed(execute_MulPlugin_bHigh));
assign execute_MUL_LL = (execute_MulPlugin_aULow * execute_MulPlugin_bULow);
assign execute_SHIFT_RIGHT = _zz_execute_SHIFT_RIGHT;
assign execute_REGFILE_WRITE_DATA = _zz_execute_REGFILE_WRITE_DATA;
assign memory_MEMORY_STORE_DATA_RF = execute_to_memory_MEMORY_STORE_DATA_RF;
assign execute_MEMORY_STORE_DATA_RF = _zz_execute_MEMORY_STORE_DATA_RF;
assign decode_DO_EBREAK = (((! DebugPlugin_haltIt) && (decode_IS_EBREAK || 1'b0)) && DebugPlugin_allowEBreak);
assign decode_CSR_READ_OPCODE = (decode_INSTRUCTION[13 : 7] != 7'h20);
assign decode_CSR_WRITE_OPCODE = (! (((decode_INSTRUCTION[14 : 13] == 2'b01) && (decode_INSTRUCTION[19 : 15] == 5'h0)) || ((decode_INSTRUCTION[14 : 13] == 2'b11) && (decode_INSTRUCTION[19 : 15] == 5'h0))));
assign decode_PREDICTION_HAD_BRANCHED2 = IBusCachedPlugin_decodePrediction_cmd_hadBranch;
assign decode_SRC2_FORCE_ZERO = (decode_SRC_ADD_ZERO && (! decode_SRC_USE_SUB_LESS));
assign decode_CfuPlugin_CFU_INPUT_2_KIND = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND;
assign _zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND = _zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_1;
assign decode_CfuPlugin_CFU_ENABLE = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[33];
assign decode_IS_RS2_SIGNED = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[31];
assign decode_IS_RS1_SIGNED = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[30];
assign decode_IS_DIV = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[29];
assign memory_IS_MUL = execute_to_memory_IS_MUL;
assign execute_IS_MUL = decode_to_execute_IS_MUL;
assign decode_IS_MUL = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[28];
assign _zz_memory_to_writeBack_ENV_CTRL = _zz_memory_to_writeBack_ENV_CTRL_1;
assign _zz_execute_to_memory_ENV_CTRL = _zz_execute_to_memory_ENV_CTRL_1;
assign decode_ENV_CTRL = _zz_decode_ENV_CTRL;
assign _zz_decode_to_execute_ENV_CTRL = _zz_decode_to_execute_ENV_CTRL_1;
assign decode_IS_CSR = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[25];
assign _zz_decode_to_execute_BRANCH_CTRL = _zz_decode_to_execute_BRANCH_CTRL_1;
assign _zz_execute_to_memory_SHIFT_CTRL = _zz_execute_to_memory_SHIFT_CTRL_1;
assign decode_SHIFT_CTRL = _zz_decode_SHIFT_CTRL;
assign _zz_decode_to_execute_SHIFT_CTRL = _zz_decode_to_execute_SHIFT_CTRL_1;
assign decode_ALU_BITWISE_CTRL = _zz_decode_ALU_BITWISE_CTRL;
assign _zz_decode_to_execute_ALU_BITWISE_CTRL = _zz_decode_to_execute_ALU_BITWISE_CTRL_1;
assign decode_SRC_LESS_UNSIGNED = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[17];
assign decode_MEMORY_MANAGMENT = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[16];
assign memory_MEMORY_WR = execute_to_memory_MEMORY_WR;
assign decode_MEMORY_WR = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[13];
assign execute_BYPASSABLE_MEMORY_STAGE = decode_to_execute_BYPASSABLE_MEMORY_STAGE;
assign decode_BYPASSABLE_MEMORY_STAGE = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[12];
assign decode_BYPASSABLE_EXECUTE_STAGE = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[11];
assign decode_SRC2_CTRL = _zz_decode_SRC2_CTRL;
assign _zz_decode_to_execute_SRC2_CTRL = _zz_decode_to_execute_SRC2_CTRL_1;
assign decode_ALU_CTRL = _zz_decode_ALU_CTRL;
assign _zz_decode_to_execute_ALU_CTRL = _zz_decode_to_execute_ALU_CTRL_1;
assign decode_SRC1_CTRL = _zz_decode_SRC1_CTRL;
assign _zz_decode_to_execute_SRC1_CTRL = _zz_decode_to_execute_SRC1_CTRL_1;
assign decode_MEMORY_FORCE_CONSTISTENCY = 1'b0;
assign writeBack_FORMAL_PC_NEXT = memory_to_writeBack_FORMAL_PC_NEXT;
assign memory_FORMAL_PC_NEXT = execute_to_memory_FORMAL_PC_NEXT;
assign execute_FORMAL_PC_NEXT = decode_to_execute_FORMAL_PC_NEXT;
assign decode_FORMAL_PC_NEXT = (decode_PC + 32'h00000004);
assign memory_PC = execute_to_memory_PC;
always @(*) begin
_zz_memory_to_writeBack_CfuPlugin_CFU_IN_FLIGHT = memory_CfuPlugin_CFU_IN_FLIGHT;
if(memory_arbitration_isStuck) begin
_zz_memory_to_writeBack_CfuPlugin_CFU_IN_FLIGHT = 1'b0;
end
end
always @(*) begin
_zz_execute_to_memory_CfuPlugin_CFU_IN_FLIGHT = execute_CfuPlugin_CFU_IN_FLIGHT;
if(execute_arbitration_isStuck) begin
_zz_execute_to_memory_CfuPlugin_CFU_IN_FLIGHT = 1'b0;
end
end
assign memory_CfuPlugin_CFU_IN_FLIGHT = execute_to_memory_CfuPlugin_CFU_IN_FLIGHT;
assign execute_CfuPlugin_CFU_INPUT_2_KIND = _zz_execute_CfuPlugin_CFU_INPUT_2_KIND;
assign execute_CfuPlugin_CFU_ENABLE = decode_to_execute_CfuPlugin_CFU_ENABLE;
assign execute_DO_EBREAK = decode_to_execute_DO_EBREAK;
assign decode_IS_EBREAK = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[32];
assign execute_IS_RS1_SIGNED = decode_to_execute_IS_RS1_SIGNED;
assign execute_IS_DIV = decode_to_execute_IS_DIV;
assign execute_IS_RS2_SIGNED = decode_to_execute_IS_RS2_SIGNED;
assign memory_IS_DIV = execute_to_memory_IS_DIV;
assign writeBack_IS_MUL = memory_to_writeBack_IS_MUL;
assign writeBack_MUL_HH = memory_to_writeBack_MUL_HH;
assign writeBack_MUL_LOW = memory_to_writeBack_MUL_LOW;
assign memory_MUL_HL = execute_to_memory_MUL_HL;
assign memory_MUL_LH = execute_to_memory_MUL_LH;
assign memory_MUL_LL = execute_to_memory_MUL_LL;
assign execute_CSR_READ_OPCODE = decode_to_execute_CSR_READ_OPCODE;
assign execute_CSR_WRITE_OPCODE = decode_to_execute_CSR_WRITE_OPCODE;
assign execute_IS_CSR = decode_to_execute_IS_CSR;
assign memory_ENV_CTRL = _zz_memory_ENV_CTRL;
assign execute_ENV_CTRL = _zz_execute_ENV_CTRL;
assign writeBack_ENV_CTRL = _zz_writeBack_ENV_CTRL;
assign execute_BRANCH_CALC = {execute_BranchPlugin_branchAdder[31 : 1],1'b0};
assign execute_BRANCH_DO = ((execute_PREDICTION_HAD_BRANCHED2 != execute_BRANCH_COND_RESULT) || execute_BranchPlugin_missAlignedTarget);
assign execute_PC = decode_to_execute_PC;
assign execute_PREDICTION_HAD_BRANCHED2 = decode_to_execute_PREDICTION_HAD_BRANCHED2;
assign execute_RS1 = decode_to_execute_RS1;
assign execute_BRANCH_COND_RESULT = _zz_execute_BRANCH_COND_RESULT_1;
assign execute_BRANCH_CTRL = _zz_execute_BRANCH_CTRL;
assign decode_RS2_USE = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[15];
assign decode_RS1_USE = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[5];
always @(*) begin
_zz_decode_RS2 = execute_REGFILE_WRITE_DATA;
if(when_CsrPlugin_l1176) begin
_zz_decode_RS2 = CsrPlugin_csrMapping_readDataSignal;
end
end
assign execute_REGFILE_WRITE_VALID = decode_to_execute_REGFILE_WRITE_VALID;
assign execute_BYPASSABLE_EXECUTE_STAGE = decode_to_execute_BYPASSABLE_EXECUTE_STAGE;
assign memory_REGFILE_WRITE_VALID = execute_to_memory_REGFILE_WRITE_VALID;
assign memory_INSTRUCTION = execute_to_memory_INSTRUCTION;
assign memory_BYPASSABLE_MEMORY_STAGE = execute_to_memory_BYPASSABLE_MEMORY_STAGE;
assign writeBack_REGFILE_WRITE_VALID = memory_to_writeBack_REGFILE_WRITE_VALID;
always @(*) begin
decode_RS2 = decode_RegFilePlugin_rs2Data;
if(HazardSimplePlugin_writeBackBuffer_valid) begin
if(HazardSimplePlugin_addr1Match) begin
decode_RS2 = HazardSimplePlugin_writeBackBuffer_payload_data;
end
end
if(when_HazardSimplePlugin_l45) begin
if(when_HazardSimplePlugin_l47) begin
if(when_HazardSimplePlugin_l51) begin
decode_RS2 = _zz_decode_RS2_2;
end
end
end
if(when_HazardSimplePlugin_l45_1) begin
if(memory_BYPASSABLE_MEMORY_STAGE) begin
if(when_HazardSimplePlugin_l51_1) begin
decode_RS2 = _zz_decode_RS2_1;
end
end
end
if(when_HazardSimplePlugin_l45_2) begin
if(execute_BYPASSABLE_EXECUTE_STAGE) begin
if(when_HazardSimplePlugin_l51_2) begin
decode_RS2 = _zz_decode_RS2;
end
end
end
end
always @(*) begin
decode_RS1 = decode_RegFilePlugin_rs1Data;
if(HazardSimplePlugin_writeBackBuffer_valid) begin
if(HazardSimplePlugin_addr0Match) begin
decode_RS1 = HazardSimplePlugin_writeBackBuffer_payload_data;
end
end
if(when_HazardSimplePlugin_l45) begin
if(when_HazardSimplePlugin_l47) begin
if(when_HazardSimplePlugin_l48) begin
decode_RS1 = _zz_decode_RS2_2;
end
end
end
if(when_HazardSimplePlugin_l45_1) begin
if(memory_BYPASSABLE_MEMORY_STAGE) begin
if(when_HazardSimplePlugin_l48_1) begin
decode_RS1 = _zz_decode_RS2_1;
end
end
end
if(when_HazardSimplePlugin_l45_2) begin
if(execute_BYPASSABLE_EXECUTE_STAGE) begin
if(when_HazardSimplePlugin_l48_2) begin
decode_RS1 = _zz_decode_RS2;
end
end
end
end
assign memory_SHIFT_RIGHT = execute_to_memory_SHIFT_RIGHT;
always @(*) begin
_zz_decode_RS2_1 = memory_REGFILE_WRITE_DATA;
if(memory_arbitration_isValid) begin
case(memory_SHIFT_CTRL)
`ShiftCtrlEnum_binary_sequential_SLL_1 : begin
_zz_decode_RS2_1 = _zz_decode_RS2_3;
end
`ShiftCtrlEnum_binary_sequential_SRL_1, `ShiftCtrlEnum_binary_sequential_SRA_1 : begin
_zz_decode_RS2_1 = memory_SHIFT_RIGHT;
end
default : begin
end
endcase
end
if(when_MulDivIterativePlugin_l128) begin
_zz_decode_RS2_1 = memory_DivPlugin_div_result;
end
if(memory_CfuPlugin_CFU_IN_FLIGHT) begin
_zz_decode_RS2_1 = CfuPlugin_bus_rsp_rsp_payload_outputs_0;
end
end
assign memory_SHIFT_CTRL = _zz_memory_SHIFT_CTRL;
assign execute_SHIFT_CTRL = _zz_execute_SHIFT_CTRL;
assign execute_SRC_LESS_UNSIGNED = decode_to_execute_SRC_LESS_UNSIGNED;
assign execute_SRC2_FORCE_ZERO = decode_to_execute_SRC2_FORCE_ZERO;
assign execute_SRC_USE_SUB_LESS = decode_to_execute_SRC_USE_SUB_LESS;
assign _zz_execute_SRC2 = execute_PC;
assign execute_SRC2_CTRL = _zz_execute_SRC2_CTRL;
assign execute_SRC1_CTRL = _zz_execute_SRC1_CTRL;
assign decode_SRC_USE_SUB_LESS = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[3];
assign decode_SRC_ADD_ZERO = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[20];
assign execute_SRC_ADD_SUB = execute_SrcPlugin_addSub;
assign execute_SRC_LESS = execute_SrcPlugin_less;
assign execute_ALU_CTRL = _zz_execute_ALU_CTRL;
assign execute_SRC2 = _zz_execute_SRC2_5;
assign execute_SRC1 = _zz_execute_SRC1;
assign execute_ALU_BITWISE_CTRL = _zz_execute_ALU_BITWISE_CTRL;
assign _zz_lastStageRegFileWrite_payload_address = writeBack_INSTRUCTION;
assign _zz_lastStageRegFileWrite_valid = writeBack_REGFILE_WRITE_VALID;
always @(*) begin
_zz_1 = 1'b0;
if(lastStageRegFileWrite_valid) begin
_zz_1 = 1'b1;
end
end
assign decode_INSTRUCTION_ANTICIPATED = (decode_arbitration_isStuck ? decode_INSTRUCTION : IBusCachedPlugin_cache_io_cpu_fetch_data);
always @(*) begin
decode_REGFILE_WRITE_VALID = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[10];
if(when_RegFilePlugin_l63) begin
decode_REGFILE_WRITE_VALID = 1'b0;
end
end
assign decode_LEGAL_INSTRUCTION = ({((decode_INSTRUCTION & 32'h0000005f) == 32'h00000017),{((decode_INSTRUCTION & 32'h0000007f) == 32'h0000006f),{((decode_INSTRUCTION & 32'h0000007f) == 32'h0000000b),{((decode_INSTRUCTION & _zz_decode_LEGAL_INSTRUCTION) == 32'h00000003),{(_zz_decode_LEGAL_INSTRUCTION_1 == _zz_decode_LEGAL_INSTRUCTION_2),{_zz_decode_LEGAL_INSTRUCTION_3,{_zz_decode_LEGAL_INSTRUCTION_4,_zz_decode_LEGAL_INSTRUCTION_5}}}}}}} != 22'h0);
always @(*) begin
_zz_decode_RS2_2 = writeBack_REGFILE_WRITE_DATA;
if(when_DBusCachedPlugin_l484) begin
_zz_decode_RS2_2 = writeBack_DBusCachedPlugin_rspFormated;
end
if(when_MulPlugin_l147) begin
case(switch_MulPlugin_l148)
2'b00 : begin
_zz_decode_RS2_2 = _zz__zz_decode_RS2_2;
end
default : begin
_zz_decode_RS2_2 = _zz__zz_decode_RS2_2_1;
end
endcase
end
end
assign writeBack_MEMORY_WR = memory_to_writeBack_MEMORY_WR;
assign writeBack_MEMORY_STORE_DATA_RF = memory_to_writeBack_MEMORY_STORE_DATA_RF;
assign writeBack_REGFILE_WRITE_DATA = memory_to_writeBack_REGFILE_WRITE_DATA;
assign writeBack_MEMORY_ENABLE = memory_to_writeBack_MEMORY_ENABLE;
assign memory_REGFILE_WRITE_DATA = execute_to_memory_REGFILE_WRITE_DATA;
assign memory_MEMORY_ENABLE = execute_to_memory_MEMORY_ENABLE;
assign execute_MEMORY_FORCE_CONSTISTENCY = decode_to_execute_MEMORY_FORCE_CONSTISTENCY;
assign execute_MEMORY_MANAGMENT = decode_to_execute_MEMORY_MANAGMENT;
assign execute_RS2 = decode_to_execute_RS2;
assign execute_MEMORY_WR = decode_to_execute_MEMORY_WR;
assign execute_SRC_ADD = execute_SrcPlugin_addSub;
assign execute_MEMORY_ENABLE = decode_to_execute_MEMORY_ENABLE;
assign execute_INSTRUCTION = decode_to_execute_INSTRUCTION;
assign decode_MEMORY_ENABLE = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[4];
assign decode_FLUSH_ALL = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[0];
always @(*) begin
IBusCachedPlugin_rsp_issueDetected_4 = IBusCachedPlugin_rsp_issueDetected_3;
if(when_IBusCachedPlugin_l256) begin
IBusCachedPlugin_rsp_issueDetected_4 = 1'b1;
end
end
always @(*) begin
IBusCachedPlugin_rsp_issueDetected_3 = IBusCachedPlugin_rsp_issueDetected_2;
if(when_IBusCachedPlugin_l250) begin
IBusCachedPlugin_rsp_issueDetected_3 = 1'b1;
end
end
always @(*) begin
IBusCachedPlugin_rsp_issueDetected_2 = IBusCachedPlugin_rsp_issueDetected_1;
if(when_IBusCachedPlugin_l244) begin
IBusCachedPlugin_rsp_issueDetected_2 = 1'b1;
end
end
always @(*) begin
IBusCachedPlugin_rsp_issueDetected_1 = IBusCachedPlugin_rsp_issueDetected;
if(when_IBusCachedPlugin_l239) begin
IBusCachedPlugin_rsp_issueDetected_1 = 1'b1;
end
end
assign decode_BRANCH_CTRL = _zz_decode_BRANCH_CTRL_1;
assign decode_INSTRUCTION = IBusCachedPlugin_iBusRsp_output_payload_rsp_inst;
always @(*) begin
_zz_execute_to_memory_FORMAL_PC_NEXT = execute_FORMAL_PC_NEXT;
if(BranchPlugin_jumpInterface_valid) begin
_zz_execute_to_memory_FORMAL_PC_NEXT = BranchPlugin_jumpInterface_payload;
end
end
always @(*) begin
_zz_decode_to_execute_FORMAL_PC_NEXT = decode_FORMAL_PC_NEXT;
if(IBusCachedPlugin_predictionJumpInterface_valid) begin
_zz_decode_to_execute_FORMAL_PC_NEXT = IBusCachedPlugin_predictionJumpInterface_payload;
end
end
assign decode_PC = IBusCachedPlugin_iBusRsp_output_payload_pc;
assign writeBack_PC = memory_to_writeBack_PC;
assign writeBack_INSTRUCTION = memory_to_writeBack_INSTRUCTION;
always @(*) begin
decode_arbitration_haltItself = 1'b0;
if(when_DBusCachedPlugin_l303) begin
decode_arbitration_haltItself = 1'b1;
end
case(switch_Fetcher_l362)
3'b010 : begin
decode_arbitration_haltItself = 1'b1;
end
default : begin
end
endcase
end
always @(*) begin
decode_arbitration_haltByOther = 1'b0;
if(when_HazardSimplePlugin_l113) begin
decode_arbitration_haltByOther = 1'b1;
end
if(CsrPlugin_pipelineLiberator_active) begin
decode_arbitration_haltByOther = 1'b1;
end
if(when_CsrPlugin_l1116) begin
decode_arbitration_haltByOther = 1'b1;
end
end
always @(*) begin
decode_arbitration_removeIt = 1'b0;
if(_zz_when) begin
decode_arbitration_removeIt = 1'b1;
end
if(decode_arbitration_isFlushed) begin
decode_arbitration_removeIt = 1'b1;
end
end
assign decode_arbitration_flushIt = 1'b0;
always @(*) begin
decode_arbitration_flushNext = 1'b0;
if(IBusCachedPlugin_predictionJumpInterface_valid) begin
decode_arbitration_flushNext = 1'b1;
end
if(_zz_when) begin
decode_arbitration_flushNext = 1'b1;
end
end
always @(*) begin
execute_arbitration_haltItself = 1'b0;
if(when_DBusCachedPlugin_l343) begin
execute_arbitration_haltItself = 1'b1;
end
if(when_CsrPlugin_l1108) begin
if(when_CsrPlugin_l1110) begin
execute_arbitration_haltItself = 1'b1;
end
end
if(when_CsrPlugin_l1180) begin
if(execute_CsrPlugin_blockedBySideEffects) begin
execute_arbitration_haltItself = 1'b1;
end
end
if(when_CfuPlugin_l175) begin
execute_arbitration_haltItself = 1'b1;
end
end
always @(*) begin
execute_arbitration_haltByOther = 1'b0;
if(when_DBusCachedPlugin_l359) begin
execute_arbitration_haltByOther = 1'b1;
end
if(when_DebugPlugin_l284) begin
execute_arbitration_haltByOther = 1'b1;
end
end
always @(*) begin
execute_arbitration_removeIt = 1'b0;
if(_zz_when_1) begin
execute_arbitration_removeIt = 1'b1;
end
if(execute_arbitration_isFlushed) begin
execute_arbitration_removeIt = 1'b1;
end
end
always @(*) begin
execute_arbitration_flushIt = 1'b0;
if(when_DebugPlugin_l284) begin
if(when_DebugPlugin_l287) begin
execute_arbitration_flushIt = 1'b1;
end
end
end
always @(*) begin
execute_arbitration_flushNext = 1'b0;
if(BranchPlugin_jumpInterface_valid) begin
execute_arbitration_flushNext = 1'b1;
end
if(_zz_when_1) begin
execute_arbitration_flushNext = 1'b1;
end
if(when_DebugPlugin_l284) begin
if(when_DebugPlugin_l287) begin
execute_arbitration_flushNext = 1'b1;
end
end
end
always @(*) begin
memory_arbitration_haltItself = 1'b0;
if(when_MulDivIterativePlugin_l128) begin
if(when_MulDivIterativePlugin_l129) begin
memory_arbitration_haltItself = 1'b1;
end
end
if(memory_CfuPlugin_CFU_IN_FLIGHT) begin
if(when_CfuPlugin_l208) begin
memory_arbitration_haltItself = 1'b1;
end
end
end
assign memory_arbitration_haltByOther = 1'b0;
always @(*) begin
memory_arbitration_removeIt = 1'b0;
if(memory_arbitration_isFlushed) begin
memory_arbitration_removeIt = 1'b1;
end
end
assign memory_arbitration_flushIt = 1'b0;
assign memory_arbitration_flushNext = 1'b0;
always @(*) begin
writeBack_arbitration_haltItself = 1'b0;
if(when_DBusCachedPlugin_l458) begin
writeBack_arbitration_haltItself = 1'b1;
end
end
assign writeBack_arbitration_haltByOther = 1'b0;
always @(*) begin
writeBack_arbitration_removeIt = 1'b0;
if(DBusCachedPlugin_exceptionBus_valid) begin
writeBack_arbitration_removeIt = 1'b1;
end
if(writeBack_arbitration_isFlushed) begin
writeBack_arbitration_removeIt = 1'b1;
end
end
always @(*) begin
writeBack_arbitration_flushIt = 1'b0;
if(DBusCachedPlugin_redoBranch_valid) begin
writeBack_arbitration_flushIt = 1'b1;
end
end
always @(*) begin
writeBack_arbitration_flushNext = 1'b0;
if(DBusCachedPlugin_redoBranch_valid) begin
writeBack_arbitration_flushNext = 1'b1;
end
if(DBusCachedPlugin_exceptionBus_valid) begin
writeBack_arbitration_flushNext = 1'b1;
end
if(when_CsrPlugin_l1019) begin
writeBack_arbitration_flushNext = 1'b1;
end
if(when_CsrPlugin_l1064) begin
writeBack_arbitration_flushNext = 1'b1;
end
end
assign lastStageInstruction = writeBack_INSTRUCTION;
assign lastStagePc = writeBack_PC;
assign lastStageIsValid = writeBack_arbitration_isValid;
assign lastStageIsFiring = writeBack_arbitration_isFiring;
always @(*) begin
IBusCachedPlugin_fetcherHalt = 1'b0;
if(when_CsrPlugin_l922) begin
IBusCachedPlugin_fetcherHalt = 1'b1;
end
if(when_CsrPlugin_l1019) begin
IBusCachedPlugin_fetcherHalt = 1'b1;
end
if(when_CsrPlugin_l1064) begin
IBusCachedPlugin_fetcherHalt = 1'b1;
end
if(when_DebugPlugin_l284) begin
if(when_DebugPlugin_l287) begin
IBusCachedPlugin_fetcherHalt = 1'b1;
end
end
if(DebugPlugin_haltIt) begin
IBusCachedPlugin_fetcherHalt = 1'b1;
end
if(when_DebugPlugin_l300) begin
IBusCachedPlugin_fetcherHalt = 1'b1;
end
end
always @(*) begin
IBusCachedPlugin_incomingInstruction = 1'b0;
if(when_Fetcher_l240) begin
IBusCachedPlugin_incomingInstruction = 1'b1;
end
end
always @(*) begin
_zz_when_DBusCachedPlugin_l386 = 1'b0;
if(DebugPlugin_godmode) begin
_zz_when_DBusCachedPlugin_l386 = 1'b1;
end
end
assign CsrPlugin_csrMapping_allowCsrSignal = 1'b0;
assign CsrPlugin_csrMapping_readDataSignal = CsrPlugin_csrMapping_readDataInit;
always @(*) begin
CsrPlugin_inWfi = 1'b0;
if(when_CsrPlugin_l1108) begin
CsrPlugin_inWfi = 1'b1;
end
end
always @(*) begin
CsrPlugin_thirdPartyWake = 1'b0;
if(DebugPlugin_haltIt) begin
CsrPlugin_thirdPartyWake = 1'b1;
end
end
always @(*) begin
CsrPlugin_jumpInterface_valid = 1'b0;
if(when_CsrPlugin_l1019) begin
CsrPlugin_jumpInterface_valid = 1'b1;
end
if(when_CsrPlugin_l1064) begin
CsrPlugin_jumpInterface_valid = 1'b1;
end
end
always @(*) begin
CsrPlugin_jumpInterface_payload = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx;
if(when_CsrPlugin_l1019) begin
CsrPlugin_jumpInterface_payload = {CsrPlugin_xtvec_base,2'b00};
end
if(when_CsrPlugin_l1064) begin
case(switch_CsrPlugin_l1068)
2'b11 : begin
CsrPlugin_jumpInterface_payload = CsrPlugin_mepc;
end
default : begin
end
endcase
end
end
always @(*) begin
CsrPlugin_forceMachineWire = 1'b0;
if(DebugPlugin_godmode) begin
CsrPlugin_forceMachineWire = 1'b1;
end
end
always @(*) begin
CsrPlugin_allowInterrupts = 1'b1;
if(when_DebugPlugin_l316) begin
CsrPlugin_allowInterrupts = 1'b0;
end
end
always @(*) begin
CsrPlugin_allowException = 1'b1;
if(DebugPlugin_godmode) begin
CsrPlugin_allowException = 1'b0;
end
end
always @(*) begin
CsrPlugin_allowEbreakException = 1'b1;
if(DebugPlugin_allowEBreak) begin
CsrPlugin_allowEbreakException = 1'b0;
end
end
assign IBusCachedPlugin_externalFlush = ({writeBack_arbitration_flushNext,{memory_arbitration_flushNext,{execute_arbitration_flushNext,decode_arbitration_flushNext}}} != 4'b0000);
assign IBusCachedPlugin_jump_pcLoad_valid = ({CsrPlugin_jumpInterface_valid,{BranchPlugin_jumpInterface_valid,{DBusCachedPlugin_redoBranch_valid,IBusCachedPlugin_predictionJumpInterface_valid}}} != 4'b0000);
assign _zz_IBusCachedPlugin_jump_pcLoad_payload = {IBusCachedPlugin_predictionJumpInterface_valid,{BranchPlugin_jumpInterface_valid,{CsrPlugin_jumpInterface_valid,DBusCachedPlugin_redoBranch_valid}}};
assign _zz_IBusCachedPlugin_jump_pcLoad_payload_1 = (_zz_IBusCachedPlugin_jump_pcLoad_payload & (~ _zz__zz_IBusCachedPlugin_jump_pcLoad_payload_1));
assign _zz_IBusCachedPlugin_jump_pcLoad_payload_2 = _zz_IBusCachedPlugin_jump_pcLoad_payload_1[3];
assign _zz_IBusCachedPlugin_jump_pcLoad_payload_3 = (_zz_IBusCachedPlugin_jump_pcLoad_payload_1[1] || _zz_IBusCachedPlugin_jump_pcLoad_payload_2);
assign _zz_IBusCachedPlugin_jump_pcLoad_payload_4 = (_zz_IBusCachedPlugin_jump_pcLoad_payload_1[2] || _zz_IBusCachedPlugin_jump_pcLoad_payload_2);
assign IBusCachedPlugin_jump_pcLoad_payload = _zz_IBusCachedPlugin_jump_pcLoad_payload_5;
always @(*) begin
IBusCachedPlugin_fetchPc_correction = 1'b0;
if(IBusCachedPlugin_fetchPc_redo_valid) begin
IBusCachedPlugin_fetchPc_correction = 1'b1;
end
if(IBusCachedPlugin_jump_pcLoad_valid) begin
IBusCachedPlugin_fetchPc_correction = 1'b1;
end
end
assign IBusCachedPlugin_fetchPc_output_fire = (IBusCachedPlugin_fetchPc_output_valid && IBusCachedPlugin_fetchPc_output_ready);
assign IBusCachedPlugin_fetchPc_corrected = (IBusCachedPlugin_fetchPc_correction || IBusCachedPlugin_fetchPc_correctionReg);
always @(*) begin
IBusCachedPlugin_fetchPc_pcRegPropagate = 1'b0;
if(IBusCachedPlugin_iBusRsp_stages_1_input_ready) begin
IBusCachedPlugin_fetchPc_pcRegPropagate = 1'b1;
end
end
assign when_Fetcher_l131 = (IBusCachedPlugin_fetchPc_correction || IBusCachedPlugin_fetchPc_pcRegPropagate);
assign IBusCachedPlugin_fetchPc_output_fire_1 = (IBusCachedPlugin_fetchPc_output_valid && IBusCachedPlugin_fetchPc_output_ready);
assign when_Fetcher_l131_1 = ((! IBusCachedPlugin_fetchPc_output_valid) && IBusCachedPlugin_fetchPc_output_ready);
always @(*) begin
IBusCachedPlugin_fetchPc_pc = (IBusCachedPlugin_fetchPc_pcReg + _zz_IBusCachedPlugin_fetchPc_pc);
if(IBusCachedPlugin_fetchPc_redo_valid) begin
IBusCachedPlugin_fetchPc_pc = IBusCachedPlugin_fetchPc_redo_payload;
end
if(IBusCachedPlugin_jump_pcLoad_valid) begin
IBusCachedPlugin_fetchPc_pc = IBusCachedPlugin_jump_pcLoad_payload;
end
IBusCachedPlugin_fetchPc_pc[0] = 1'b0;
IBusCachedPlugin_fetchPc_pc[1] = 1'b0;
end
always @(*) begin
IBusCachedPlugin_fetchPc_flushed = 1'b0;
if(IBusCachedPlugin_fetchPc_redo_valid) begin
IBusCachedPlugin_fetchPc_flushed = 1'b1;
end
if(IBusCachedPlugin_jump_pcLoad_valid) begin
IBusCachedPlugin_fetchPc_flushed = 1'b1;
end
end
assign when_Fetcher_l158 = (IBusCachedPlugin_fetchPc_booted && ((IBusCachedPlugin_fetchPc_output_ready || IBusCachedPlugin_fetchPc_correction) || IBusCachedPlugin_fetchPc_pcRegPropagate));
assign IBusCachedPlugin_fetchPc_output_valid = ((! IBusCachedPlugin_fetcherHalt) && IBusCachedPlugin_fetchPc_booted);
assign IBusCachedPlugin_fetchPc_output_payload = IBusCachedPlugin_fetchPc_pc;
always @(*) begin
IBusCachedPlugin_iBusRsp_redoFetch = 1'b0;
if(IBusCachedPlugin_rsp_redoFetch) begin
IBusCachedPlugin_iBusRsp_redoFetch = 1'b1;
end
end
assign IBusCachedPlugin_iBusRsp_stages_0_input_valid = IBusCachedPlugin_fetchPc_output_valid;
assign IBusCachedPlugin_fetchPc_output_ready = IBusCachedPlugin_iBusRsp_stages_0_input_ready;
assign IBusCachedPlugin_iBusRsp_stages_0_input_payload = IBusCachedPlugin_fetchPc_output_payload;
always @(*) begin
IBusCachedPlugin_iBusRsp_stages_0_halt = 1'b0;
if(IBusCachedPlugin_cache_io_cpu_prefetch_haltIt) begin
IBusCachedPlugin_iBusRsp_stages_0_halt = 1'b1;
end
end
assign _zz_IBusCachedPlugin_iBusRsp_stages_0_input_ready = (! IBusCachedPlugin_iBusRsp_stages_0_halt);
assign IBusCachedPlugin_iBusRsp_stages_0_input_ready = (IBusCachedPlugin_iBusRsp_stages_0_output_ready && _zz_IBusCachedPlugin_iBusRsp_stages_0_input_ready);
assign IBusCachedPlugin_iBusRsp_stages_0_output_valid = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && _zz_IBusCachedPlugin_iBusRsp_stages_0_input_ready);
assign IBusCachedPlugin_iBusRsp_stages_0_output_payload = IBusCachedPlugin_iBusRsp_stages_0_input_payload;
always @(*) begin
IBusCachedPlugin_iBusRsp_stages_1_halt = 1'b0;
if(IBusCachedPlugin_mmuBus_busy) begin
IBusCachedPlugin_iBusRsp_stages_1_halt = 1'b1;
end
end
assign _zz_IBusCachedPlugin_iBusRsp_stages_1_input_ready = (! IBusCachedPlugin_iBusRsp_stages_1_halt);
assign IBusCachedPlugin_iBusRsp_stages_1_input_ready = (IBusCachedPlugin_iBusRsp_stages_1_output_ready && _zz_IBusCachedPlugin_iBusRsp_stages_1_input_ready);
assign IBusCachedPlugin_iBusRsp_stages_1_output_valid = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && _zz_IBusCachedPlugin_iBusRsp_stages_1_input_ready);
assign IBusCachedPlugin_iBusRsp_stages_1_output_payload = IBusCachedPlugin_iBusRsp_stages_1_input_payload;
always @(*) begin
IBusCachedPlugin_iBusRsp_stages_2_halt = 1'b0;
if(when_IBusCachedPlugin_l267) begin
IBusCachedPlugin_iBusRsp_stages_2_halt = 1'b1;
end
end
assign _zz_IBusCachedPlugin_iBusRsp_stages_2_input_ready = (! IBusCachedPlugin_iBusRsp_stages_2_halt);
assign IBusCachedPlugin_iBusRsp_stages_2_input_ready = (IBusCachedPlugin_iBusRsp_stages_2_output_ready && _zz_IBusCachedPlugin_iBusRsp_stages_2_input_ready);
assign IBusCachedPlugin_iBusRsp_stages_2_output_valid = (IBusCachedPlugin_iBusRsp_stages_2_input_valid && _zz_IBusCachedPlugin_iBusRsp_stages_2_input_ready);
assign IBusCachedPlugin_iBusRsp_stages_2_output_payload = IBusCachedPlugin_iBusRsp_stages_2_input_payload;
assign IBusCachedPlugin_fetchPc_redo_valid = IBusCachedPlugin_iBusRsp_redoFetch;
assign IBusCachedPlugin_fetchPc_redo_payload = IBusCachedPlugin_iBusRsp_stages_2_input_payload;
assign IBusCachedPlugin_iBusRsp_flush = ((decode_arbitration_removeIt || (decode_arbitration_flushNext && (! decode_arbitration_isStuck))) || IBusCachedPlugin_iBusRsp_redoFetch);
assign IBusCachedPlugin_iBusRsp_stages_0_output_ready = _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready;
assign _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready = ((1'b0 && (! _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_1)) || IBusCachedPlugin_iBusRsp_stages_1_input_ready);
assign _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_1 = _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_2;
assign IBusCachedPlugin_iBusRsp_stages_1_input_valid = _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_1;
assign IBusCachedPlugin_iBusRsp_stages_1_input_payload = IBusCachedPlugin_fetchPc_pcReg;
assign IBusCachedPlugin_iBusRsp_stages_1_output_ready = ((1'b0 && (! IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid)) || IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_ready);
assign IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid = _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid;
assign IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_payload = _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_payload;
assign IBusCachedPlugin_iBusRsp_stages_2_input_valid = IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid;
assign IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_ready = IBusCachedPlugin_iBusRsp_stages_2_input_ready;
assign IBusCachedPlugin_iBusRsp_stages_2_input_payload = IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_payload;
always @(*) begin
IBusCachedPlugin_iBusRsp_readyForError = 1'b1;
if(when_Fetcher_l320) begin
IBusCachedPlugin_iBusRsp_readyForError = 1'b0;
end
end
assign when_Fetcher_l240 = (IBusCachedPlugin_iBusRsp_stages_1_input_valid || IBusCachedPlugin_iBusRsp_stages_2_input_valid);
assign when_Fetcher_l320 = (! IBusCachedPlugin_pcValids_0);
assign when_Fetcher_l329 = (! (! IBusCachedPlugin_iBusRsp_stages_1_input_ready));
assign when_Fetcher_l329_1 = (! (! IBusCachedPlugin_iBusRsp_stages_2_input_ready));
assign when_Fetcher_l329_2 = (! execute_arbitration_isStuck);
assign when_Fetcher_l329_3 = (! memory_arbitration_isStuck);
assign when_Fetcher_l329_4 = (! writeBack_arbitration_isStuck);
assign IBusCachedPlugin_pcValids_0 = IBusCachedPlugin_injector_nextPcCalc_valids_1;
assign IBusCachedPlugin_pcValids_1 = IBusCachedPlugin_injector_nextPcCalc_valids_2;
assign IBusCachedPlugin_pcValids_2 = IBusCachedPlugin_injector_nextPcCalc_valids_3;
assign IBusCachedPlugin_pcValids_3 = IBusCachedPlugin_injector_nextPcCalc_valids_4;
assign IBusCachedPlugin_iBusRsp_output_ready = (! decode_arbitration_isStuck);
always @(*) begin
decode_arbitration_isValid = IBusCachedPlugin_iBusRsp_output_valid;
case(switch_Fetcher_l362)
3'b010 : begin
decode_arbitration_isValid = 1'b1;
end
3'b011 : begin
decode_arbitration_isValid = 1'b1;
end
default : begin
end
endcase
end
assign _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch = _zz__zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch[11];
always @(*) begin
_zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[18] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch;
_zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[17] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch;
_zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[16] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch;
_zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[15] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch;
_zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[14] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch;
_zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[13] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch;
_zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[12] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch;
_zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[11] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch;
_zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[10] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch;
_zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[9] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch;
_zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[8] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch;
_zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[7] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch;
_zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[6] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch;
_zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[5] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch;
_zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[4] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch;
_zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[3] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch;
_zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[2] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch;
_zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[1] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch;
_zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[0] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch;
end
always @(*) begin
IBusCachedPlugin_decodePrediction_cmd_hadBranch = ((decode_BRANCH_CTRL == `BranchCtrlEnum_binary_sequential_JAL) || ((decode_BRANCH_CTRL == `BranchCtrlEnum_binary_sequential_B) && _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_2[31]));
if(_zz_6) begin
IBusCachedPlugin_decodePrediction_cmd_hadBranch = 1'b0;
end
end
assign _zz_2 = _zz__zz_2[19];
always @(*) begin
_zz_3[10] = _zz_2;
_zz_3[9] = _zz_2;
_zz_3[8] = _zz_2;
_zz_3[7] = _zz_2;
_zz_3[6] = _zz_2;
_zz_3[5] = _zz_2;
_zz_3[4] = _zz_2;
_zz_3[3] = _zz_2;
_zz_3[2] = _zz_2;
_zz_3[1] = _zz_2;
_zz_3[0] = _zz_2;
end
assign _zz_4 = _zz__zz_4[11];
always @(*) begin
_zz_5[18] = _zz_4;
_zz_5[17] = _zz_4;
_zz_5[16] = _zz_4;
_zz_5[15] = _zz_4;
_zz_5[14] = _zz_4;
_zz_5[13] = _zz_4;
_zz_5[12] = _zz_4;
_zz_5[11] = _zz_4;
_zz_5[10] = _zz_4;
_zz_5[9] = _zz_4;
_zz_5[8] = _zz_4;
_zz_5[7] = _zz_4;
_zz_5[6] = _zz_4;
_zz_5[5] = _zz_4;
_zz_5[4] = _zz_4;
_zz_5[3] = _zz_4;
_zz_5[2] = _zz_4;
_zz_5[1] = _zz_4;
_zz_5[0] = _zz_4;
end
always @(*) begin
case(decode_BRANCH_CTRL)
`BranchCtrlEnum_binary_sequential_JAL : begin
_zz_6 = _zz__zz_6[1];
end
default : begin
_zz_6 = _zz__zz_6_1[1];
end
endcase
end
assign IBusCachedPlugin_predictionJumpInterface_valid = (decode_arbitration_isValid && IBusCachedPlugin_decodePrediction_cmd_hadBranch);
assign _zz_IBusCachedPlugin_predictionJumpInterface_payload = _zz__zz_IBusCachedPlugin_predictionJumpInterface_payload[19];
always @(*) begin
_zz_IBusCachedPlugin_predictionJumpInterface_payload_1[10] = _zz_IBusCachedPlugin_predictionJumpInterface_payload;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_1[9] = _zz_IBusCachedPlugin_predictionJumpInterface_payload;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_1[8] = _zz_IBusCachedPlugin_predictionJumpInterface_payload;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_1[7] = _zz_IBusCachedPlugin_predictionJumpInterface_payload;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_1[6] = _zz_IBusCachedPlugin_predictionJumpInterface_payload;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_1[5] = _zz_IBusCachedPlugin_predictionJumpInterface_payload;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_1[4] = _zz_IBusCachedPlugin_predictionJumpInterface_payload;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_1[3] = _zz_IBusCachedPlugin_predictionJumpInterface_payload;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_1[2] = _zz_IBusCachedPlugin_predictionJumpInterface_payload;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_1[1] = _zz_IBusCachedPlugin_predictionJumpInterface_payload;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_1[0] = _zz_IBusCachedPlugin_predictionJumpInterface_payload;
end
assign _zz_IBusCachedPlugin_predictionJumpInterface_payload_2 = _zz__zz_IBusCachedPlugin_predictionJumpInterface_payload_2[11];
always @(*) begin
_zz_IBusCachedPlugin_predictionJumpInterface_payload_3[18] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_3[17] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_3[16] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_3[15] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_3[14] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_3[13] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_3[12] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_3[11] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_3[10] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_3[9] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_3[8] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_3[7] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_3[6] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_3[5] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_3[4] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_3[3] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_3[2] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_3[1] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_3[0] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2;
end
assign IBusCachedPlugin_predictionJumpInterface_payload = (decode_PC + ((decode_BRANCH_CTRL == `BranchCtrlEnum_binary_sequential_JAL) ? {{_zz_IBusCachedPlugin_predictionJumpInterface_payload_1,{{{_zz_IBusCachedPlugin_predictionJumpInterface_payload_4,decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_IBusCachedPlugin_predictionJumpInterface_payload_3,{{{_zz_IBusCachedPlugin_predictionJumpInterface_payload_5,_zz_IBusCachedPlugin_predictionJumpInterface_payload_6},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0}));
assign iBus_cmd_valid = IBusCachedPlugin_cache_io_mem_cmd_valid;
always @(*) begin
iBus_cmd_payload_address = IBusCachedPlugin_cache_io_mem_cmd_payload_address;
iBus_cmd_payload_address = IBusCachedPlugin_cache_io_mem_cmd_payload_address;
end
assign iBus_cmd_payload_size = IBusCachedPlugin_cache_io_mem_cmd_payload_size;
assign IBusCachedPlugin_s0_tightlyCoupledHit = 1'b0;
assign IBusCachedPlugin_cache_io_cpu_prefetch_isValid = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && (! IBusCachedPlugin_s0_tightlyCoupledHit));
assign IBusCachedPlugin_cache_io_cpu_fetch_isValid = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && (! IBusCachedPlugin_s1_tightlyCoupledHit));
assign IBusCachedPlugin_cache_io_cpu_fetch_isStuck = (! IBusCachedPlugin_iBusRsp_stages_1_input_ready);
assign IBusCachedPlugin_mmuBus_cmd_0_isValid = IBusCachedPlugin_cache_io_cpu_fetch_isValid;
assign IBusCachedPlugin_mmuBus_cmd_0_isStuck = (! IBusCachedPlugin_iBusRsp_stages_1_input_ready);
assign IBusCachedPlugin_mmuBus_cmd_0_virtualAddress = IBusCachedPlugin_iBusRsp_stages_1_input_payload;
assign IBusCachedPlugin_mmuBus_cmd_0_bypassTranslation = 1'b0;
assign IBusCachedPlugin_mmuBus_end = (IBusCachedPlugin_iBusRsp_stages_1_input_ready || IBusCachedPlugin_externalFlush);
assign IBusCachedPlugin_cache_io_cpu_decode_isValid = (IBusCachedPlugin_iBusRsp_stages_2_input_valid && (! IBusCachedPlugin_s2_tightlyCoupledHit));
assign IBusCachedPlugin_cache_io_cpu_decode_isStuck = (! IBusCachedPlugin_iBusRsp_stages_2_input_ready);
assign IBusCachedPlugin_cache_io_cpu_decode_isUser = (CsrPlugin_privilege == 2'b00);
assign IBusCachedPlugin_rsp_iBusRspOutputHalt = 1'b0;
assign IBusCachedPlugin_rsp_issueDetected = 1'b0;
always @(*) begin
IBusCachedPlugin_rsp_redoFetch = 1'b0;
if(when_IBusCachedPlugin_l239) begin
IBusCachedPlugin_rsp_redoFetch = 1'b1;
end
if(when_IBusCachedPlugin_l250) begin
IBusCachedPlugin_rsp_redoFetch = 1'b1;
end
end
always @(*) begin
IBusCachedPlugin_cache_io_cpu_fill_valid = (IBusCachedPlugin_rsp_redoFetch && (! IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling));
if(when_IBusCachedPlugin_l250) begin
IBusCachedPlugin_cache_io_cpu_fill_valid = 1'b1;
end
end
always @(*) begin
IBusCachedPlugin_decodeExceptionPort_valid = 1'b0;
if(when_IBusCachedPlugin_l244) begin
IBusCachedPlugin_decodeExceptionPort_valid = IBusCachedPlugin_iBusRsp_readyForError;
end
if(when_IBusCachedPlugin_l256) begin
IBusCachedPlugin_decodeExceptionPort_valid = IBusCachedPlugin_iBusRsp_readyForError;
end
end
always @(*) begin
IBusCachedPlugin_decodeExceptionPort_payload_code = 4'bxxxx;
if(when_IBusCachedPlugin_l244) begin
IBusCachedPlugin_decodeExceptionPort_payload_code = 4'b1100;
end
if(when_IBusCachedPlugin_l256) begin
IBusCachedPlugin_decodeExceptionPort_payload_code = 4'b0001;
end
end
assign IBusCachedPlugin_decodeExceptionPort_payload_badAddr = {IBusCachedPlugin_iBusRsp_stages_2_input_payload[31 : 2],2'b00};
assign when_IBusCachedPlugin_l239 = ((IBusCachedPlugin_cache_io_cpu_decode_isValid && IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling) && (! IBusCachedPlugin_rsp_issueDetected));
assign when_IBusCachedPlugin_l244 = ((IBusCachedPlugin_cache_io_cpu_decode_isValid && IBusCachedPlugin_cache_io_cpu_decode_mmuException) && (! IBusCachedPlugin_rsp_issueDetected_1));
assign when_IBusCachedPlugin_l250 = ((IBusCachedPlugin_cache_io_cpu_decode_isValid && IBusCachedPlugin_cache_io_cpu_decode_cacheMiss) && (! IBusCachedPlugin_rsp_issueDetected_2));
assign when_IBusCachedPlugin_l256 = ((IBusCachedPlugin_cache_io_cpu_decode_isValid && IBusCachedPlugin_cache_io_cpu_decode_error) && (! IBusCachedPlugin_rsp_issueDetected_3));
assign when_IBusCachedPlugin_l267 = (IBusCachedPlugin_rsp_issueDetected_4 || IBusCachedPlugin_rsp_iBusRspOutputHalt);
assign IBusCachedPlugin_iBusRsp_output_valid = IBusCachedPlugin_iBusRsp_stages_2_output_valid;
assign IBusCachedPlugin_iBusRsp_stages_2_output_ready = IBusCachedPlugin_iBusRsp_output_ready;
assign IBusCachedPlugin_iBusRsp_output_payload_rsp_inst = IBusCachedPlugin_cache_io_cpu_decode_data;
assign IBusCachedPlugin_iBusRsp_output_payload_pc = IBusCachedPlugin_iBusRsp_stages_2_output_payload;
assign IBusCachedPlugin_cache_io_flush = (decode_arbitration_isValid && decode_FLUSH_ALL);
assign dataCache_1_io_mem_cmd_ready = (! dataCache_1_io_mem_cmd_rValid);
assign dataCache_1_io_mem_cmd_s2mPipe_valid = (dataCache_1_io_mem_cmd_valid || dataCache_1_io_mem_cmd_rValid);
assign dataCache_1_io_mem_cmd_s2mPipe_payload_wr = (dataCache_1_io_mem_cmd_rValid ? dataCache_1_io_mem_cmd_rData_wr : dataCache_1_io_mem_cmd_payload_wr);
assign dataCache_1_io_mem_cmd_s2mPipe_payload_uncached = (dataCache_1_io_mem_cmd_rValid ? dataCache_1_io_mem_cmd_rData_uncached : dataCache_1_io_mem_cmd_payload_uncached);
assign dataCache_1_io_mem_cmd_s2mPipe_payload_address = (dataCache_1_io_mem_cmd_rValid ? dataCache_1_io_mem_cmd_rData_address : dataCache_1_io_mem_cmd_payload_address);
assign dataCache_1_io_mem_cmd_s2mPipe_payload_data = (dataCache_1_io_mem_cmd_rValid ? dataCache_1_io_mem_cmd_rData_data : dataCache_1_io_mem_cmd_payload_data);
assign dataCache_1_io_mem_cmd_s2mPipe_payload_mask = (dataCache_1_io_mem_cmd_rValid ? dataCache_1_io_mem_cmd_rData_mask : dataCache_1_io_mem_cmd_payload_mask);
assign dataCache_1_io_mem_cmd_s2mPipe_payload_size = (dataCache_1_io_mem_cmd_rValid ? dataCache_1_io_mem_cmd_rData_size : dataCache_1_io_mem_cmd_payload_size);
assign dataCache_1_io_mem_cmd_s2mPipe_payload_last = (dataCache_1_io_mem_cmd_rValid ? dataCache_1_io_mem_cmd_rData_last : dataCache_1_io_mem_cmd_payload_last);
always @(*) begin
dataCache_1_io_mem_cmd_s2mPipe_ready = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_ready;
if(when_Stream_l342) begin
dataCache_1_io_mem_cmd_s2mPipe_ready = 1'b1;
end
end
assign when_Stream_l342 = (! dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_valid);
assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_valid = dataCache_1_io_mem_cmd_s2mPipe_rValid;
assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_wr = dataCache_1_io_mem_cmd_s2mPipe_rData_wr;
assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_uncached = dataCache_1_io_mem_cmd_s2mPipe_rData_uncached;
assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_address = dataCache_1_io_mem_cmd_s2mPipe_rData_address;
assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_data = dataCache_1_io_mem_cmd_s2mPipe_rData_data;
assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_mask = dataCache_1_io_mem_cmd_s2mPipe_rData_mask;
assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_size = dataCache_1_io_mem_cmd_s2mPipe_rData_size;
assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_last = dataCache_1_io_mem_cmd_s2mPipe_rData_last;
assign dBus_cmd_valid = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_valid;
assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_ready = dBus_cmd_ready;
assign dBus_cmd_payload_wr = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_wr;
assign dBus_cmd_payload_uncached = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_uncached;
assign dBus_cmd_payload_address = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_address;
assign dBus_cmd_payload_data = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_data;
assign dBus_cmd_payload_mask = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_mask;
assign dBus_cmd_payload_size = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_size;
assign dBus_cmd_payload_last = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_last;
assign when_DBusCachedPlugin_l303 = ((DBusCachedPlugin_mmuBus_busy && decode_arbitration_isValid) && decode_MEMORY_ENABLE);
assign execute_DBusCachedPlugin_size = execute_INSTRUCTION[13 : 12];
assign dataCache_1_io_cpu_execute_isValid = (execute_arbitration_isValid && execute_MEMORY_ENABLE);
assign dataCache_1_io_cpu_execute_address = execute_SRC_ADD;
always @(*) begin
case(execute_DBusCachedPlugin_size)
2'b00 : begin
_zz_execute_MEMORY_STORE_DATA_RF = {{{execute_RS2[7 : 0],execute_RS2[7 : 0]},execute_RS2[7 : 0]},execute_RS2[7 : 0]};
end
2'b01 : begin
_zz_execute_MEMORY_STORE_DATA_RF = {execute_RS2[15 : 0],execute_RS2[15 : 0]};
end
default : begin
_zz_execute_MEMORY_STORE_DATA_RF = execute_RS2[31 : 0];
end
endcase
end
assign dataCache_1_io_cpu_flush_valid = (execute_arbitration_isValid && execute_MEMORY_MANAGMENT);
assign dataCache_1_io_cpu_flush_isStall = (dataCache_1_io_cpu_flush_valid && (! dataCache_1_io_cpu_flush_ready));
assign when_DBusCachedPlugin_l343 = (dataCache_1_io_cpu_flush_isStall || dataCache_1_io_cpu_execute_haltIt);
assign when_DBusCachedPlugin_l359 = (dataCache_1_io_cpu_execute_refilling && execute_arbitration_isValid);
assign dataCache_1_io_cpu_memory_isValid = (memory_arbitration_isValid && memory_MEMORY_ENABLE);
assign dataCache_1_io_cpu_memory_address = memory_REGFILE_WRITE_DATA;
assign DBusCachedPlugin_mmuBus_cmd_0_isValid = dataCache_1_io_cpu_memory_isValid;
assign DBusCachedPlugin_mmuBus_cmd_0_isStuck = memory_arbitration_isStuck;
assign DBusCachedPlugin_mmuBus_cmd_0_virtualAddress = dataCache_1_io_cpu_memory_address;
assign DBusCachedPlugin_mmuBus_cmd_0_bypassTranslation = 1'b0;
assign DBusCachedPlugin_mmuBus_end = ((! memory_arbitration_isStuck) || memory_arbitration_removeIt);
always @(*) begin
dataCache_1_io_cpu_memory_mmuRsp_isIoAccess = DBusCachedPlugin_mmuBus_rsp_isIoAccess;
if(when_DBusCachedPlugin_l386) begin
dataCache_1_io_cpu_memory_mmuRsp_isIoAccess = 1'b1;
end
end
assign when_DBusCachedPlugin_l386 = (_zz_when_DBusCachedPlugin_l386 && (! dataCache_1_io_cpu_memory_isWrite));
always @(*) begin
dataCache_1_io_cpu_writeBack_isValid = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE);
if(writeBack_arbitration_haltByOther) begin
dataCache_1_io_cpu_writeBack_isValid = 1'b0;
end
end
assign dataCache_1_io_cpu_writeBack_isUser = (CsrPlugin_privilege == 2'b00);
assign dataCache_1_io_cpu_writeBack_address = writeBack_REGFILE_WRITE_DATA;
assign dataCache_1_io_cpu_writeBack_storeData[31 : 0] = writeBack_MEMORY_STORE_DATA_RF;
always @(*) begin
DBusCachedPlugin_redoBranch_valid = 1'b0;
if(when_DBusCachedPlugin_l438) begin
if(dataCache_1_io_cpu_redo) begin
DBusCachedPlugin_redoBranch_valid = 1'b1;
end
end
end
assign DBusCachedPlugin_redoBranch_payload = writeBack_PC;
always @(*) begin
DBusCachedPlugin_exceptionBus_valid = 1'b0;
if(when_DBusCachedPlugin_l438) begin
if(dataCache_1_io_cpu_writeBack_accessError) begin
DBusCachedPlugin_exceptionBus_valid = 1'b1;
end
if(dataCache_1_io_cpu_writeBack_mmuException) begin
DBusCachedPlugin_exceptionBus_valid = 1'b1;
end
if(dataCache_1_io_cpu_writeBack_unalignedAccess) begin
DBusCachedPlugin_exceptionBus_valid = 1'b1;
end
if(dataCache_1_io_cpu_redo) begin
DBusCachedPlugin_exceptionBus_valid = 1'b0;
end
end
end
assign DBusCachedPlugin_exceptionBus_payload_badAddr = writeBack_REGFILE_WRITE_DATA;
always @(*) begin
DBusCachedPlugin_exceptionBus_payload_code = 4'bxxxx;
if(when_DBusCachedPlugin_l438) begin
if(dataCache_1_io_cpu_writeBack_accessError) begin
DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_DBusCachedPlugin_exceptionBus_payload_code};
end
if(dataCache_1_io_cpu_writeBack_mmuException) begin
DBusCachedPlugin_exceptionBus_payload_code = (writeBack_MEMORY_WR ? 4'b1111 : 4'b1101);
end
if(dataCache_1_io_cpu_writeBack_unalignedAccess) begin
DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_DBusCachedPlugin_exceptionBus_payload_code_1};
end
end
end
assign when_DBusCachedPlugin_l438 = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE);
assign when_DBusCachedPlugin_l458 = (dataCache_1_io_cpu_writeBack_isValid && dataCache_1_io_cpu_writeBack_haltIt);
assign writeBack_DBusCachedPlugin_rspSplits_0 = dataCache_1_io_cpu_writeBack_data[7 : 0];
assign writeBack_DBusCachedPlugin_rspSplits_1 = dataCache_1_io_cpu_writeBack_data[15 : 8];
assign writeBack_DBusCachedPlugin_rspSplits_2 = dataCache_1_io_cpu_writeBack_data[23 : 16];
assign writeBack_DBusCachedPlugin_rspSplits_3 = dataCache_1_io_cpu_writeBack_data[31 : 24];
always @(*) begin
writeBack_DBusCachedPlugin_rspShifted[7 : 0] = _zz_writeBack_DBusCachedPlugin_rspShifted;
writeBack_DBusCachedPlugin_rspShifted[15 : 8] = _zz_writeBack_DBusCachedPlugin_rspShifted_2;
writeBack_DBusCachedPlugin_rspShifted[23 : 16] = writeBack_DBusCachedPlugin_rspSplits_2;
writeBack_DBusCachedPlugin_rspShifted[31 : 24] = writeBack_DBusCachedPlugin_rspSplits_3;
end
assign writeBack_DBusCachedPlugin_rspRf = writeBack_DBusCachedPlugin_rspShifted[31 : 0];
assign switch_Misc_l200 = writeBack_INSTRUCTION[13 : 12];
assign _zz_writeBack_DBusCachedPlugin_rspFormated = (writeBack_DBusCachedPlugin_rspRf[7] && (! writeBack_INSTRUCTION[14]));
always @(*) begin
_zz_writeBack_DBusCachedPlugin_rspFormated_1[31] = _zz_writeBack_DBusCachedPlugin_rspFormated;
_zz_writeBack_DBusCachedPlugin_rspFormated_1[30] = _zz_writeBack_DBusCachedPlugin_rspFormated;
_zz_writeBack_DBusCachedPlugin_rspFormated_1[29] = _zz_writeBack_DBusCachedPlugin_rspFormated;
_zz_writeBack_DBusCachedPlugin_rspFormated_1[28] = _zz_writeBack_DBusCachedPlugin_rspFormated;
_zz_writeBack_DBusCachedPlugin_rspFormated_1[27] = _zz_writeBack_DBusCachedPlugin_rspFormated;
_zz_writeBack_DBusCachedPlugin_rspFormated_1[26] = _zz_writeBack_DBusCachedPlugin_rspFormated;
_zz_writeBack_DBusCachedPlugin_rspFormated_1[25] = _zz_writeBack_DBusCachedPlugin_rspFormated;
_zz_writeBack_DBusCachedPlugin_rspFormated_1[24] = _zz_writeBack_DBusCachedPlugin_rspFormated;
_zz_writeBack_DBusCachedPlugin_rspFormated_1[23] = _zz_writeBack_DBusCachedPlugin_rspFormated;
_zz_writeBack_DBusCachedPlugin_rspFormated_1[22] = _zz_writeBack_DBusCachedPlugin_rspFormated;
_zz_writeBack_DBusCachedPlugin_rspFormated_1[21] = _zz_writeBack_DBusCachedPlugin_rspFormated;
_zz_writeBack_DBusCachedPlugin_rspFormated_1[20] = _zz_writeBack_DBusCachedPlugin_rspFormated;
_zz_writeBack_DBusCachedPlugin_rspFormated_1[19] = _zz_writeBack_DBusCachedPlugin_rspFormated;
_zz_writeBack_DBusCachedPlugin_rspFormated_1[18] = _zz_writeBack_DBusCachedPlugin_rspFormated;
_zz_writeBack_DBusCachedPlugin_rspFormated_1[17] = _zz_writeBack_DBusCachedPlugin_rspFormated;
_zz_writeBack_DBusCachedPlugin_rspFormated_1[16] = _zz_writeBack_DBusCachedPlugin_rspFormated;
_zz_writeBack_DBusCachedPlugin_rspFormated_1[15] = _zz_writeBack_DBusCachedPlugin_rspFormated;
_zz_writeBack_DBusCachedPlugin_rspFormated_1[14] = _zz_writeBack_DBusCachedPlugin_rspFormated;
_zz_writeBack_DBusCachedPlugin_rspFormated_1[13] = _zz_writeBack_DBusCachedPlugin_rspFormated;
_zz_writeBack_DBusCachedPlugin_rspFormated_1[12] = _zz_writeBack_DBusCachedPlugin_rspFormated;
_zz_writeBack_DBusCachedPlugin_rspFormated_1[11] = _zz_writeBack_DBusCachedPlugin_rspFormated;
_zz_writeBack_DBusCachedPlugin_rspFormated_1[10] = _zz_writeBack_DBusCachedPlugin_rspFormated;
_zz_writeBack_DBusCachedPlugin_rspFormated_1[9] = _zz_writeBack_DBusCachedPlugin_rspFormated;
_zz_writeBack_DBusCachedPlugin_rspFormated_1[8] = _zz_writeBack_DBusCachedPlugin_rspFormated;
_zz_writeBack_DBusCachedPlugin_rspFormated_1[7 : 0] = writeBack_DBusCachedPlugin_rspRf[7 : 0];
end
assign _zz_writeBack_DBusCachedPlugin_rspFormated_2 = (writeBack_DBusCachedPlugin_rspRf[15] && (! writeBack_INSTRUCTION[14]));
always @(*) begin
_zz_writeBack_DBusCachedPlugin_rspFormated_3[31] = _zz_writeBack_DBusCachedPlugin_rspFormated_2;
_zz_writeBack_DBusCachedPlugin_rspFormated_3[30] = _zz_writeBack_DBusCachedPlugin_rspFormated_2;
_zz_writeBack_DBusCachedPlugin_rspFormated_3[29] = _zz_writeBack_DBusCachedPlugin_rspFormated_2;
_zz_writeBack_DBusCachedPlugin_rspFormated_3[28] = _zz_writeBack_DBusCachedPlugin_rspFormated_2;
_zz_writeBack_DBusCachedPlugin_rspFormated_3[27] = _zz_writeBack_DBusCachedPlugin_rspFormated_2;
_zz_writeBack_DBusCachedPlugin_rspFormated_3[26] = _zz_writeBack_DBusCachedPlugin_rspFormated_2;
_zz_writeBack_DBusCachedPlugin_rspFormated_3[25] = _zz_writeBack_DBusCachedPlugin_rspFormated_2;
_zz_writeBack_DBusCachedPlugin_rspFormated_3[24] = _zz_writeBack_DBusCachedPlugin_rspFormated_2;
_zz_writeBack_DBusCachedPlugin_rspFormated_3[23] = _zz_writeBack_DBusCachedPlugin_rspFormated_2;
_zz_writeBack_DBusCachedPlugin_rspFormated_3[22] = _zz_writeBack_DBusCachedPlugin_rspFormated_2;
_zz_writeBack_DBusCachedPlugin_rspFormated_3[21] = _zz_writeBack_DBusCachedPlugin_rspFormated_2;
_zz_writeBack_DBusCachedPlugin_rspFormated_3[20] = _zz_writeBack_DBusCachedPlugin_rspFormated_2;
_zz_writeBack_DBusCachedPlugin_rspFormated_3[19] = _zz_writeBack_DBusCachedPlugin_rspFormated_2;
_zz_writeBack_DBusCachedPlugin_rspFormated_3[18] = _zz_writeBack_DBusCachedPlugin_rspFormated_2;
_zz_writeBack_DBusCachedPlugin_rspFormated_3[17] = _zz_writeBack_DBusCachedPlugin_rspFormated_2;
_zz_writeBack_DBusCachedPlugin_rspFormated_3[16] = _zz_writeBack_DBusCachedPlugin_rspFormated_2;
_zz_writeBack_DBusCachedPlugin_rspFormated_3[15 : 0] = writeBack_DBusCachedPlugin_rspRf[15 : 0];
end
always @(*) begin
case(switch_Misc_l200)
2'b00 : begin
writeBack_DBusCachedPlugin_rspFormated = _zz_writeBack_DBusCachedPlugin_rspFormated_1;
end
2'b01 : begin
writeBack_DBusCachedPlugin_rspFormated = _zz_writeBack_DBusCachedPlugin_rspFormated_3;
end
default : begin
writeBack_DBusCachedPlugin_rspFormated = writeBack_DBusCachedPlugin_rspRf;
end
endcase
end
assign when_DBusCachedPlugin_l484 = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE);
assign IBusCachedPlugin_mmuBus_rsp_physicalAddress = IBusCachedPlugin_mmuBus_cmd_0_virtualAddress;
assign IBusCachedPlugin_mmuBus_rsp_allowRead = 1'b1;
assign IBusCachedPlugin_mmuBus_rsp_allowWrite = 1'b1;
assign IBusCachedPlugin_mmuBus_rsp_allowExecute = 1'b1;
assign IBusCachedPlugin_mmuBus_rsp_isIoAccess = IBusCachedPlugin_mmuBus_rsp_physicalAddress[31];
assign IBusCachedPlugin_mmuBus_rsp_isPaging = 1'b0;
assign IBusCachedPlugin_mmuBus_rsp_exception = 1'b0;
assign IBusCachedPlugin_mmuBus_rsp_refilling = 1'b0;
assign IBusCachedPlugin_mmuBus_busy = 1'b0;
assign DBusCachedPlugin_mmuBus_rsp_physicalAddress = DBusCachedPlugin_mmuBus_cmd_0_virtualAddress;
assign DBusCachedPlugin_mmuBus_rsp_allowRead = 1'b1;
assign DBusCachedPlugin_mmuBus_rsp_allowWrite = 1'b1;
assign DBusCachedPlugin_mmuBus_rsp_allowExecute = 1'b1;
assign DBusCachedPlugin_mmuBus_rsp_isIoAccess = DBusCachedPlugin_mmuBus_rsp_physicalAddress[31];
assign DBusCachedPlugin_mmuBus_rsp_isPaging = 1'b0;
assign DBusCachedPlugin_mmuBus_rsp_exception = 1'b0;
assign DBusCachedPlugin_mmuBus_rsp_refilling = 1'b0;
assign DBusCachedPlugin_mmuBus_busy = 1'b0;
assign _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_3 = ((decode_INSTRUCTION & 32'h00004050) == 32'h00004050);
assign _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_4 = ((decode_INSTRUCTION & 32'h00000004) == 32'h00000004);
assign _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_5 = ((decode_INSTRUCTION & 32'h00000048) == 32'h00000048);
assign _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_6 = ((decode_INSTRUCTION & 32'h0000000c) == 32'h00000008);
assign _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_7 = ((decode_INSTRUCTION & 32'h00001000) == 32'h0);
assign _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2 = {1'b0,{(_zz_decode_CfuPlugin_CFU_INPUT_2_KIND_6 != 1'b0),{((_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_1) != 1'b0),{(_zz_decode_CfuPlugin_CFU_INPUT_2_KIND_7 != 1'b0),{(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_2 != _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_3),{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_4,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_5,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_7}}}}}}};
assign _zz_decode_SRC1_CTRL_2 = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[2 : 1];
assign _zz_decode_SRC1_CTRL_1 = _zz_decode_SRC1_CTRL_2;
assign _zz_decode_ALU_CTRL_2 = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[7 : 6];
assign _zz_decode_ALU_CTRL_1 = _zz_decode_ALU_CTRL_2;
assign _zz_decode_SRC2_CTRL_2 = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[9 : 8];
assign _zz_decode_SRC2_CTRL_1 = _zz_decode_SRC2_CTRL_2;
assign _zz_decode_ALU_BITWISE_CTRL_2 = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[19 : 18];
assign _zz_decode_ALU_BITWISE_CTRL_1 = _zz_decode_ALU_BITWISE_CTRL_2;
assign _zz_decode_SHIFT_CTRL_2 = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[22 : 21];
assign _zz_decode_SHIFT_CTRL_1 = _zz_decode_SHIFT_CTRL_2;
assign _zz_decode_BRANCH_CTRL_2 = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[24 : 23];
assign _zz_decode_BRANCH_CTRL = _zz_decode_BRANCH_CTRL_2;
assign _zz_decode_ENV_CTRL_2 = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[27 : 26];
assign _zz_decode_ENV_CTRL_1 = _zz_decode_ENV_CTRL_2;
assign _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_8 = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[34 : 34];
assign _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_1 = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_8;
assign decodeExceptionPort_valid = (decode_arbitration_isValid && (! decode_LEGAL_INSTRUCTION));
assign decodeExceptionPort_payload_code = 4'b0010;
assign decodeExceptionPort_payload_badAddr = decode_INSTRUCTION;
assign when_RegFilePlugin_l63 = (decode_INSTRUCTION[11 : 7] == 5'h0);
assign decode_RegFilePlugin_regFileReadAddress1 = decode_INSTRUCTION_ANTICIPATED[19 : 15];
assign decode_RegFilePlugin_regFileReadAddress2 = decode_INSTRUCTION_ANTICIPATED[24 : 20];
assign decode_RegFilePlugin_rs1Data = _zz_RegFilePlugin_regFile_port0;
assign decode_RegFilePlugin_rs2Data = _zz_RegFilePlugin_regFile_port1;
always @(*) begin
lastStageRegFileWrite_valid = (_zz_lastStageRegFileWrite_valid && writeBack_arbitration_isFiring);
if(_zz_7) begin
lastStageRegFileWrite_valid = 1'b1;
end
end
always @(*) begin
lastStageRegFileWrite_payload_address = _zz_lastStageRegFileWrite_payload_address[11 : 7];
if(_zz_7) begin
lastStageRegFileWrite_payload_address = 5'h0;
end
end
always @(*) begin
lastStageRegFileWrite_payload_data = _zz_decode_RS2_2;
if(_zz_7) begin
lastStageRegFileWrite_payload_data = 32'h0;
end
end
always @(*) begin
case(execute_ALU_BITWISE_CTRL)
`AluBitwiseCtrlEnum_binary_sequential_AND_1 : begin
execute_IntAluPlugin_bitwise = (execute_SRC1 & execute_SRC2);
end
`AluBitwiseCtrlEnum_binary_sequential_OR_1 : begin
execute_IntAluPlugin_bitwise = (execute_SRC1 | execute_SRC2);
end
default : begin
execute_IntAluPlugin_bitwise = (execute_SRC1 ^ execute_SRC2);
end
endcase
end
always @(*) begin
case(execute_ALU_CTRL)
`AluCtrlEnum_binary_sequential_BITWISE : begin
_zz_execute_REGFILE_WRITE_DATA = execute_IntAluPlugin_bitwise;
end
`AluCtrlEnum_binary_sequential_SLT_SLTU : begin
_zz_execute_REGFILE_WRITE_DATA = {31'd0, _zz__zz_execute_REGFILE_WRITE_DATA};
end
default : begin
_zz_execute_REGFILE_WRITE_DATA = execute_SRC_ADD_SUB;
end
endcase
end
always @(*) begin
case(execute_SRC1_CTRL)
`Src1CtrlEnum_binary_sequential_RS : begin
_zz_execute_SRC1 = execute_RS1;
end
`Src1CtrlEnum_binary_sequential_PC_INCREMENT : begin
_zz_execute_SRC1 = {29'd0, _zz__zz_execute_SRC1};
end
`Src1CtrlEnum_binary_sequential_IMU : begin
_zz_execute_SRC1 = {execute_INSTRUCTION[31 : 12],12'h0};
end
default : begin
_zz_execute_SRC1 = {27'd0, _zz__zz_execute_SRC1_1};
end
endcase
end
assign _zz_execute_SRC2_1 = execute_INSTRUCTION[31];
always @(*) begin
_zz_execute_SRC2_2[19] = _zz_execute_SRC2_1;
_zz_execute_SRC2_2[18] = _zz_execute_SRC2_1;
_zz_execute_SRC2_2[17] = _zz_execute_SRC2_1;
_zz_execute_SRC2_2[16] = _zz_execute_SRC2_1;
_zz_execute_SRC2_2[15] = _zz_execute_SRC2_1;
_zz_execute_SRC2_2[14] = _zz_execute_SRC2_1;
_zz_execute_SRC2_2[13] = _zz_execute_SRC2_1;
_zz_execute_SRC2_2[12] = _zz_execute_SRC2_1;
_zz_execute_SRC2_2[11] = _zz_execute_SRC2_1;
_zz_execute_SRC2_2[10] = _zz_execute_SRC2_1;
_zz_execute_SRC2_2[9] = _zz_execute_SRC2_1;
_zz_execute_SRC2_2[8] = _zz_execute_SRC2_1;
_zz_execute_SRC2_2[7] = _zz_execute_SRC2_1;
_zz_execute_SRC2_2[6] = _zz_execute_SRC2_1;
_zz_execute_SRC2_2[5] = _zz_execute_SRC2_1;
_zz_execute_SRC2_2[4] = _zz_execute_SRC2_1;
_zz_execute_SRC2_2[3] = _zz_execute_SRC2_1;
_zz_execute_SRC2_2[2] = _zz_execute_SRC2_1;
_zz_execute_SRC2_2[1] = _zz_execute_SRC2_1;
_zz_execute_SRC2_2[0] = _zz_execute_SRC2_1;
end
assign _zz_execute_SRC2_3 = _zz__zz_execute_SRC2_3[11];
always @(*) begin
_zz_execute_SRC2_4[19] = _zz_execute_SRC2_3;
_zz_execute_SRC2_4[18] = _zz_execute_SRC2_3;
_zz_execute_SRC2_4[17] = _zz_execute_SRC2_3;
_zz_execute_SRC2_4[16] = _zz_execute_SRC2_3;
_zz_execute_SRC2_4[15] = _zz_execute_SRC2_3;
_zz_execute_SRC2_4[14] = _zz_execute_SRC2_3;
_zz_execute_SRC2_4[13] = _zz_execute_SRC2_3;
_zz_execute_SRC2_4[12] = _zz_execute_SRC2_3;
_zz_execute_SRC2_4[11] = _zz_execute_SRC2_3;
_zz_execute_SRC2_4[10] = _zz_execute_SRC2_3;
_zz_execute_SRC2_4[9] = _zz_execute_SRC2_3;
_zz_execute_SRC2_4[8] = _zz_execute_SRC2_3;
_zz_execute_SRC2_4[7] = _zz_execute_SRC2_3;
_zz_execute_SRC2_4[6] = _zz_execute_SRC2_3;
_zz_execute_SRC2_4[5] = _zz_execute_SRC2_3;
_zz_execute_SRC2_4[4] = _zz_execute_SRC2_3;
_zz_execute_SRC2_4[3] = _zz_execute_SRC2_3;
_zz_execute_SRC2_4[2] = _zz_execute_SRC2_3;
_zz_execute_SRC2_4[1] = _zz_execute_SRC2_3;
_zz_execute_SRC2_4[0] = _zz_execute_SRC2_3;
end
always @(*) begin
case(execute_SRC2_CTRL)
`Src2CtrlEnum_binary_sequential_RS : begin
_zz_execute_SRC2_5 = execute_RS2;
end
`Src2CtrlEnum_binary_sequential_IMI : begin
_zz_execute_SRC2_5 = {_zz_execute_SRC2_2,execute_INSTRUCTION[31 : 20]};
end
`Src2CtrlEnum_binary_sequential_IMS : begin
_zz_execute_SRC2_5 = {_zz_execute_SRC2_4,{execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}};
end
default : begin
_zz_execute_SRC2_5 = _zz_execute_SRC2;
end
endcase
end
always @(*) begin
execute_SrcPlugin_addSub = _zz_execute_SrcPlugin_addSub;
if(execute_SRC2_FORCE_ZERO) begin
execute_SrcPlugin_addSub = execute_SRC1;
end
end
assign execute_SrcPlugin_less = ((execute_SRC1[31] == execute_SRC2[31]) ? execute_SrcPlugin_addSub[31] : (execute_SRC_LESS_UNSIGNED ? execute_SRC2[31] : execute_SRC1[31]));
assign execute_FullBarrelShifterPlugin_amplitude = execute_SRC2[4 : 0];
always @(*) begin
_zz_execute_FullBarrelShifterPlugin_reversed[0] = execute_SRC1[31];
_zz_execute_FullBarrelShifterPlugin_reversed[1] = execute_SRC1[30];
_zz_execute_FullBarrelShifterPlugin_reversed[2] = execute_SRC1[29];
_zz_execute_FullBarrelShifterPlugin_reversed[3] = execute_SRC1[28];
_zz_execute_FullBarrelShifterPlugin_reversed[4] = execute_SRC1[27];
_zz_execute_FullBarrelShifterPlugin_reversed[5] = execute_SRC1[26];
_zz_execute_FullBarrelShifterPlugin_reversed[6] = execute_SRC1[25];
_zz_execute_FullBarrelShifterPlugin_reversed[7] = execute_SRC1[24];
_zz_execute_FullBarrelShifterPlugin_reversed[8] = execute_SRC1[23];
_zz_execute_FullBarrelShifterPlugin_reversed[9] = execute_SRC1[22];
_zz_execute_FullBarrelShifterPlugin_reversed[10] = execute_SRC1[21];
_zz_execute_FullBarrelShifterPlugin_reversed[11] = execute_SRC1[20];
_zz_execute_FullBarrelShifterPlugin_reversed[12] = execute_SRC1[19];
_zz_execute_FullBarrelShifterPlugin_reversed[13] = execute_SRC1[18];
_zz_execute_FullBarrelShifterPlugin_reversed[14] = execute_SRC1[17];
_zz_execute_FullBarrelShifterPlugin_reversed[15] = execute_SRC1[16];
_zz_execute_FullBarrelShifterPlugin_reversed[16] = execute_SRC1[15];
_zz_execute_FullBarrelShifterPlugin_reversed[17] = execute_SRC1[14];
_zz_execute_FullBarrelShifterPlugin_reversed[18] = execute_SRC1[13];
_zz_execute_FullBarrelShifterPlugin_reversed[19] = execute_SRC1[12];
_zz_execute_FullBarrelShifterPlugin_reversed[20] = execute_SRC1[11];
_zz_execute_FullBarrelShifterPlugin_reversed[21] = execute_SRC1[10];
_zz_execute_FullBarrelShifterPlugin_reversed[22] = execute_SRC1[9];
_zz_execute_FullBarrelShifterPlugin_reversed[23] = execute_SRC1[8];
_zz_execute_FullBarrelShifterPlugin_reversed[24] = execute_SRC1[7];
_zz_execute_FullBarrelShifterPlugin_reversed[25] = execute_SRC1[6];
_zz_execute_FullBarrelShifterPlugin_reversed[26] = execute_SRC1[5];
_zz_execute_FullBarrelShifterPlugin_reversed[27] = execute_SRC1[4];
_zz_execute_FullBarrelShifterPlugin_reversed[28] = execute_SRC1[3];
_zz_execute_FullBarrelShifterPlugin_reversed[29] = execute_SRC1[2];
_zz_execute_FullBarrelShifterPlugin_reversed[30] = execute_SRC1[1];
_zz_execute_FullBarrelShifterPlugin_reversed[31] = execute_SRC1[0];
end
assign execute_FullBarrelShifterPlugin_reversed = ((execute_SHIFT_CTRL == `ShiftCtrlEnum_binary_sequential_SLL_1) ? _zz_execute_FullBarrelShifterPlugin_reversed : execute_SRC1);
always @(*) begin
_zz_decode_RS2_3[0] = memory_SHIFT_RIGHT[31];
_zz_decode_RS2_3[1] = memory_SHIFT_RIGHT[30];
_zz_decode_RS2_3[2] = memory_SHIFT_RIGHT[29];
_zz_decode_RS2_3[3] = memory_SHIFT_RIGHT[28];
_zz_decode_RS2_3[4] = memory_SHIFT_RIGHT[27];
_zz_decode_RS2_3[5] = memory_SHIFT_RIGHT[26];
_zz_decode_RS2_3[6] = memory_SHIFT_RIGHT[25];
_zz_decode_RS2_3[7] = memory_SHIFT_RIGHT[24];
_zz_decode_RS2_3[8] = memory_SHIFT_RIGHT[23];
_zz_decode_RS2_3[9] = memory_SHIFT_RIGHT[22];
_zz_decode_RS2_3[10] = memory_SHIFT_RIGHT[21];
_zz_decode_RS2_3[11] = memory_SHIFT_RIGHT[20];
_zz_decode_RS2_3[12] = memory_SHIFT_RIGHT[19];
_zz_decode_RS2_3[13] = memory_SHIFT_RIGHT[18];
_zz_decode_RS2_3[14] = memory_SHIFT_RIGHT[17];
_zz_decode_RS2_3[15] = memory_SHIFT_RIGHT[16];
_zz_decode_RS2_3[16] = memory_SHIFT_RIGHT[15];
_zz_decode_RS2_3[17] = memory_SHIFT_RIGHT[14];
_zz_decode_RS2_3[18] = memory_SHIFT_RIGHT[13];
_zz_decode_RS2_3[19] = memory_SHIFT_RIGHT[12];
_zz_decode_RS2_3[20] = memory_SHIFT_RIGHT[11];
_zz_decode_RS2_3[21] = memory_SHIFT_RIGHT[10];
_zz_decode_RS2_3[22] = memory_SHIFT_RIGHT[9];
_zz_decode_RS2_3[23] = memory_SHIFT_RIGHT[8];
_zz_decode_RS2_3[24] = memory_SHIFT_RIGHT[7];
_zz_decode_RS2_3[25] = memory_SHIFT_RIGHT[6];
_zz_decode_RS2_3[26] = memory_SHIFT_RIGHT[5];
_zz_decode_RS2_3[27] = memory_SHIFT_RIGHT[4];
_zz_decode_RS2_3[28] = memory_SHIFT_RIGHT[3];
_zz_decode_RS2_3[29] = memory_SHIFT_RIGHT[2];
_zz_decode_RS2_3[30] = memory_SHIFT_RIGHT[1];
_zz_decode_RS2_3[31] = memory_SHIFT_RIGHT[0];
end
always @(*) begin
HazardSimplePlugin_src0Hazard = 1'b0;
if(when_HazardSimplePlugin_l57) begin
if(when_HazardSimplePlugin_l58) begin
if(when_HazardSimplePlugin_l48) begin
HazardSimplePlugin_src0Hazard = 1'b1;
end
end
end
if(when_HazardSimplePlugin_l57_1) begin
if(when_HazardSimplePlugin_l58_1) begin
if(when_HazardSimplePlugin_l48_1) begin
HazardSimplePlugin_src0Hazard = 1'b1;
end
end
end
if(when_HazardSimplePlugin_l57_2) begin
if(when_HazardSimplePlugin_l58_2) begin
if(when_HazardSimplePlugin_l48_2) begin
HazardSimplePlugin_src0Hazard = 1'b1;
end
end
end
if(when_HazardSimplePlugin_l105) begin
HazardSimplePlugin_src0Hazard = 1'b0;
end
end
always @(*) begin
HazardSimplePlugin_src1Hazard = 1'b0;
if(when_HazardSimplePlugin_l57) begin
if(when_HazardSimplePlugin_l58) begin
if(when_HazardSimplePlugin_l51) begin
HazardSimplePlugin_src1Hazard = 1'b1;
end
end
end
if(when_HazardSimplePlugin_l57_1) begin
if(when_HazardSimplePlugin_l58_1) begin
if(when_HazardSimplePlugin_l51_1) begin
HazardSimplePlugin_src1Hazard = 1'b1;
end
end
end
if(when_HazardSimplePlugin_l57_2) begin
if(when_HazardSimplePlugin_l58_2) begin
if(when_HazardSimplePlugin_l51_2) begin
HazardSimplePlugin_src1Hazard = 1'b1;
end
end
end
if(when_HazardSimplePlugin_l108) begin
HazardSimplePlugin_src1Hazard = 1'b0;
end
end
assign HazardSimplePlugin_writeBackWrites_valid = (_zz_lastStageRegFileWrite_valid && writeBack_arbitration_isFiring);
assign HazardSimplePlugin_writeBackWrites_payload_address = _zz_lastStageRegFileWrite_payload_address[11 : 7];
assign HazardSimplePlugin_writeBackWrites_payload_data = _zz_decode_RS2_2;
assign HazardSimplePlugin_addr0Match = (HazardSimplePlugin_writeBackBuffer_payload_address == decode_INSTRUCTION[19 : 15]);
assign HazardSimplePlugin_addr1Match = (HazardSimplePlugin_writeBackBuffer_payload_address == decode_INSTRUCTION[24 : 20]);
assign when_HazardSimplePlugin_l47 = 1'b1;
assign when_HazardSimplePlugin_l48 = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]);
assign when_HazardSimplePlugin_l51 = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]);
assign when_HazardSimplePlugin_l45 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID);
assign when_HazardSimplePlugin_l57 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID);
assign when_HazardSimplePlugin_l58 = (1'b0 || (! when_HazardSimplePlugin_l47));
assign when_HazardSimplePlugin_l48_1 = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]);
assign when_HazardSimplePlugin_l51_1 = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]);
assign when_HazardSimplePlugin_l45_1 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID);
assign when_HazardSimplePlugin_l57_1 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID);
assign when_HazardSimplePlugin_l58_1 = (1'b0 || (! memory_BYPASSABLE_MEMORY_STAGE));
assign when_HazardSimplePlugin_l48_2 = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]);
assign when_HazardSimplePlugin_l51_2 = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]);
assign when_HazardSimplePlugin_l45_2 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID);
assign when_HazardSimplePlugin_l57_2 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID);
assign when_HazardSimplePlugin_l58_2 = (1'b0 || (! execute_BYPASSABLE_EXECUTE_STAGE));
assign when_HazardSimplePlugin_l105 = (! decode_RS1_USE);
assign when_HazardSimplePlugin_l108 = (! decode_RS2_USE);
assign when_HazardSimplePlugin_l113 = (decode_arbitration_isValid && (HazardSimplePlugin_src0Hazard || HazardSimplePlugin_src1Hazard));
assign execute_BranchPlugin_eq = (execute_SRC1 == execute_SRC2);
assign switch_Misc_l200_1 = execute_INSTRUCTION[14 : 12];
always @(*) begin
casez(switch_Misc_l200_1)
3'b000 : begin
_zz_execute_BRANCH_COND_RESULT = execute_BranchPlugin_eq;
end
3'b001 : begin
_zz_execute_BRANCH_COND_RESULT = (! execute_BranchPlugin_eq);
end
3'b1?1 : begin
_zz_execute_BRANCH_COND_RESULT = (! execute_SRC_LESS);
end
default : begin
_zz_execute_BRANCH_COND_RESULT = execute_SRC_LESS;
end
endcase
end
always @(*) begin
case(execute_BRANCH_CTRL)
`BranchCtrlEnum_binary_sequential_INC : begin
_zz_execute_BRANCH_COND_RESULT_1 = 1'b0;
end
`BranchCtrlEnum_binary_sequential_JAL : begin
_zz_execute_BRANCH_COND_RESULT_1 = 1'b1;
end
`BranchCtrlEnum_binary_sequential_JALR : begin
_zz_execute_BRANCH_COND_RESULT_1 = 1'b1;
end
default : begin
_zz_execute_BRANCH_COND_RESULT_1 = _zz_execute_BRANCH_COND_RESULT;
end
endcase
end
assign _zz_execute_BranchPlugin_missAlignedTarget = execute_INSTRUCTION[31];
always @(*) begin
_zz_execute_BranchPlugin_missAlignedTarget_1[19] = _zz_execute_BranchPlugin_missAlignedTarget;
_zz_execute_BranchPlugin_missAlignedTarget_1[18] = _zz_execute_BranchPlugin_missAlignedTarget;
_zz_execute_BranchPlugin_missAlignedTarget_1[17] = _zz_execute_BranchPlugin_missAlignedTarget;
_zz_execute_BranchPlugin_missAlignedTarget_1[16] = _zz_execute_BranchPlugin_missAlignedTarget;
_zz_execute_BranchPlugin_missAlignedTarget_1[15] = _zz_execute_BranchPlugin_missAlignedTarget;
_zz_execute_BranchPlugin_missAlignedTarget_1[14] = _zz_execute_BranchPlugin_missAlignedTarget;
_zz_execute_BranchPlugin_missAlignedTarget_1[13] = _zz_execute_BranchPlugin_missAlignedTarget;
_zz_execute_BranchPlugin_missAlignedTarget_1[12] = _zz_execute_BranchPlugin_missAlignedTarget;
_zz_execute_BranchPlugin_missAlignedTarget_1[11] = _zz_execute_BranchPlugin_missAlignedTarget;
_zz_execute_BranchPlugin_missAlignedTarget_1[10] = _zz_execute_BranchPlugin_missAlignedTarget;
_zz_execute_BranchPlugin_missAlignedTarget_1[9] = _zz_execute_BranchPlugin_missAlignedTarget;
_zz_execute_BranchPlugin_missAlignedTarget_1[8] = _zz_execute_BranchPlugin_missAlignedTarget;
_zz_execute_BranchPlugin_missAlignedTarget_1[7] = _zz_execute_BranchPlugin_missAlignedTarget;
_zz_execute_BranchPlugin_missAlignedTarget_1[6] = _zz_execute_BranchPlugin_missAlignedTarget;
_zz_execute_BranchPlugin_missAlignedTarget_1[5] = _zz_execute_BranchPlugin_missAlignedTarget;
_zz_execute_BranchPlugin_missAlignedTarget_1[4] = _zz_execute_BranchPlugin_missAlignedTarget;
_zz_execute_BranchPlugin_missAlignedTarget_1[3] = _zz_execute_BranchPlugin_missAlignedTarget;
_zz_execute_BranchPlugin_missAlignedTarget_1[2] = _zz_execute_BranchPlugin_missAlignedTarget;
_zz_execute_BranchPlugin_missAlignedTarget_1[1] = _zz_execute_BranchPlugin_missAlignedTarget;
_zz_execute_BranchPlugin_missAlignedTarget_1[0] = _zz_execute_BranchPlugin_missAlignedTarget;
end
assign _zz_execute_BranchPlugin_missAlignedTarget_2 = _zz__zz_execute_BranchPlugin_missAlignedTarget_2[19];
always @(*) begin
_zz_execute_BranchPlugin_missAlignedTarget_3[10] = _zz_execute_BranchPlugin_missAlignedTarget_2;
_zz_execute_BranchPlugin_missAlignedTarget_3[9] = _zz_execute_BranchPlugin_missAlignedTarget_2;
_zz_execute_BranchPlugin_missAlignedTarget_3[8] = _zz_execute_BranchPlugin_missAlignedTarget_2;
_zz_execute_BranchPlugin_missAlignedTarget_3[7] = _zz_execute_BranchPlugin_missAlignedTarget_2;
_zz_execute_BranchPlugin_missAlignedTarget_3[6] = _zz_execute_BranchPlugin_missAlignedTarget_2;
_zz_execute_BranchPlugin_missAlignedTarget_3[5] = _zz_execute_BranchPlugin_missAlignedTarget_2;
_zz_execute_BranchPlugin_missAlignedTarget_3[4] = _zz_execute_BranchPlugin_missAlignedTarget_2;
_zz_execute_BranchPlugin_missAlignedTarget_3[3] = _zz_execute_BranchPlugin_missAlignedTarget_2;
_zz_execute_BranchPlugin_missAlignedTarget_3[2] = _zz_execute_BranchPlugin_missAlignedTarget_2;
_zz_execute_BranchPlugin_missAlignedTarget_3[1] = _zz_execute_BranchPlugin_missAlignedTarget_2;
_zz_execute_BranchPlugin_missAlignedTarget_3[0] = _zz_execute_BranchPlugin_missAlignedTarget_2;
end
assign _zz_execute_BranchPlugin_missAlignedTarget_4 = _zz__zz_execute_BranchPlugin_missAlignedTarget_4[11];
always @(*) begin
_zz_execute_BranchPlugin_missAlignedTarget_5[18] = _zz_execute_BranchPlugin_missAlignedTarget_4;
_zz_execute_BranchPlugin_missAlignedTarget_5[17] = _zz_execute_BranchPlugin_missAlignedTarget_4;
_zz_execute_BranchPlugin_missAlignedTarget_5[16] = _zz_execute_BranchPlugin_missAlignedTarget_4;
_zz_execute_BranchPlugin_missAlignedTarget_5[15] = _zz_execute_BranchPlugin_missAlignedTarget_4;
_zz_execute_BranchPlugin_missAlignedTarget_5[14] = _zz_execute_BranchPlugin_missAlignedTarget_4;
_zz_execute_BranchPlugin_missAlignedTarget_5[13] = _zz_execute_BranchPlugin_missAlignedTarget_4;
_zz_execute_BranchPlugin_missAlignedTarget_5[12] = _zz_execute_BranchPlugin_missAlignedTarget_4;
_zz_execute_BranchPlugin_missAlignedTarget_5[11] = _zz_execute_BranchPlugin_missAlignedTarget_4;
_zz_execute_BranchPlugin_missAlignedTarget_5[10] = _zz_execute_BranchPlugin_missAlignedTarget_4;
_zz_execute_BranchPlugin_missAlignedTarget_5[9] = _zz_execute_BranchPlugin_missAlignedTarget_4;
_zz_execute_BranchPlugin_missAlignedTarget_5[8] = _zz_execute_BranchPlugin_missAlignedTarget_4;
_zz_execute_BranchPlugin_missAlignedTarget_5[7] = _zz_execute_BranchPlugin_missAlignedTarget_4;
_zz_execute_BranchPlugin_missAlignedTarget_5[6] = _zz_execute_BranchPlugin_missAlignedTarget_4;
_zz_execute_BranchPlugin_missAlignedTarget_5[5] = _zz_execute_BranchPlugin_missAlignedTarget_4;
_zz_execute_BranchPlugin_missAlignedTarget_5[4] = _zz_execute_BranchPlugin_missAlignedTarget_4;
_zz_execute_BranchPlugin_missAlignedTarget_5[3] = _zz_execute_BranchPlugin_missAlignedTarget_4;
_zz_execute_BranchPlugin_missAlignedTarget_5[2] = _zz_execute_BranchPlugin_missAlignedTarget_4;
_zz_execute_BranchPlugin_missAlignedTarget_5[1] = _zz_execute_BranchPlugin_missAlignedTarget_4;
_zz_execute_BranchPlugin_missAlignedTarget_5[0] = _zz_execute_BranchPlugin_missAlignedTarget_4;
end
always @(*) begin
case(execute_BRANCH_CTRL)
`BranchCtrlEnum_binary_sequential_JALR : begin
_zz_execute_BranchPlugin_missAlignedTarget_6 = (_zz__zz_execute_BranchPlugin_missAlignedTarget_6[1] ^ execute_RS1[1]);
end
`BranchCtrlEnum_binary_sequential_JAL : begin
_zz_execute_BranchPlugin_missAlignedTarget_6 = _zz__zz_execute_BranchPlugin_missAlignedTarget_6_1[1];
end
default : begin
_zz_execute_BranchPlugin_missAlignedTarget_6 = _zz__zz_execute_BranchPlugin_missAlignedTarget_6_2[1];
end
endcase
end
assign execute_BranchPlugin_missAlignedTarget = (execute_BRANCH_COND_RESULT && _zz_execute_BranchPlugin_missAlignedTarget_6);
always @(*) begin
case(execute_BRANCH_CTRL)
`BranchCtrlEnum_binary_sequential_JALR : begin
execute_BranchPlugin_branch_src1 = execute_RS1;
end
default : begin
execute_BranchPlugin_branch_src1 = execute_PC;
end
endcase
end
assign _zz_execute_BranchPlugin_branch_src2 = execute_INSTRUCTION[31];
always @(*) begin
_zz_execute_BranchPlugin_branch_src2_1[19] = _zz_execute_BranchPlugin_branch_src2;
_zz_execute_BranchPlugin_branch_src2_1[18] = _zz_execute_BranchPlugin_branch_src2;
_zz_execute_BranchPlugin_branch_src2_1[17] = _zz_execute_BranchPlugin_branch_src2;
_zz_execute_BranchPlugin_branch_src2_1[16] = _zz_execute_BranchPlugin_branch_src2;
_zz_execute_BranchPlugin_branch_src2_1[15] = _zz_execute_BranchPlugin_branch_src2;
_zz_execute_BranchPlugin_branch_src2_1[14] = _zz_execute_BranchPlugin_branch_src2;
_zz_execute_BranchPlugin_branch_src2_1[13] = _zz_execute_BranchPlugin_branch_src2;
_zz_execute_BranchPlugin_branch_src2_1[12] = _zz_execute_BranchPlugin_branch_src2;
_zz_execute_BranchPlugin_branch_src2_1[11] = _zz_execute_BranchPlugin_branch_src2;
_zz_execute_BranchPlugin_branch_src2_1[10] = _zz_execute_BranchPlugin_branch_src2;
_zz_execute_BranchPlugin_branch_src2_1[9] = _zz_execute_BranchPlugin_branch_src2;
_zz_execute_BranchPlugin_branch_src2_1[8] = _zz_execute_BranchPlugin_branch_src2;
_zz_execute_BranchPlugin_branch_src2_1[7] = _zz_execute_BranchPlugin_branch_src2;
_zz_execute_BranchPlugin_branch_src2_1[6] = _zz_execute_BranchPlugin_branch_src2;
_zz_execute_BranchPlugin_branch_src2_1[5] = _zz_execute_BranchPlugin_branch_src2;
_zz_execute_BranchPlugin_branch_src2_1[4] = _zz_execute_BranchPlugin_branch_src2;
_zz_execute_BranchPlugin_branch_src2_1[3] = _zz_execute_BranchPlugin_branch_src2;
_zz_execute_BranchPlugin_branch_src2_1[2] = _zz_execute_BranchPlugin_branch_src2;
_zz_execute_BranchPlugin_branch_src2_1[1] = _zz_execute_BranchPlugin_branch_src2;
_zz_execute_BranchPlugin_branch_src2_1[0] = _zz_execute_BranchPlugin_branch_src2;
end
always @(*) begin
case(execute_BRANCH_CTRL)
`BranchCtrlEnum_binary_sequential_JALR : begin
execute_BranchPlugin_branch_src2 = {_zz_execute_BranchPlugin_branch_src2_1,execute_INSTRUCTION[31 : 20]};
end
default : begin
execute_BranchPlugin_branch_src2 = ((execute_BRANCH_CTRL == `BranchCtrlEnum_binary_sequential_JAL) ? {{_zz_execute_BranchPlugin_branch_src2_3,{{{_zz_execute_BranchPlugin_branch_src2_6,execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_execute_BranchPlugin_branch_src2_5,{{{_zz_execute_BranchPlugin_branch_src2_7,_zz_execute_BranchPlugin_branch_src2_8},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0});
if(execute_PREDICTION_HAD_BRANCHED2) begin
execute_BranchPlugin_branch_src2 = {29'd0, _zz_execute_BranchPlugin_branch_src2_9};
end
end
endcase
end
assign _zz_execute_BranchPlugin_branch_src2_2 = _zz__zz_execute_BranchPlugin_branch_src2_2[19];
always @(*) begin
_zz_execute_BranchPlugin_branch_src2_3[10] = _zz_execute_BranchPlugin_branch_src2_2;
_zz_execute_BranchPlugin_branch_src2_3[9] = _zz_execute_BranchPlugin_branch_src2_2;
_zz_execute_BranchPlugin_branch_src2_3[8] = _zz_execute_BranchPlugin_branch_src2_2;
_zz_execute_BranchPlugin_branch_src2_3[7] = _zz_execute_BranchPlugin_branch_src2_2;
_zz_execute_BranchPlugin_branch_src2_3[6] = _zz_execute_BranchPlugin_branch_src2_2;
_zz_execute_BranchPlugin_branch_src2_3[5] = _zz_execute_BranchPlugin_branch_src2_2;
_zz_execute_BranchPlugin_branch_src2_3[4] = _zz_execute_BranchPlugin_branch_src2_2;
_zz_execute_BranchPlugin_branch_src2_3[3] = _zz_execute_BranchPlugin_branch_src2_2;
_zz_execute_BranchPlugin_branch_src2_3[2] = _zz_execute_BranchPlugin_branch_src2_2;
_zz_execute_BranchPlugin_branch_src2_3[1] = _zz_execute_BranchPlugin_branch_src2_2;
_zz_execute_BranchPlugin_branch_src2_3[0] = _zz_execute_BranchPlugin_branch_src2_2;
end
assign _zz_execute_BranchPlugin_branch_src2_4 = _zz__zz_execute_BranchPlugin_branch_src2_4[11];
always @(*) begin
_zz_execute_BranchPlugin_branch_src2_5[18] = _zz_execute_BranchPlugin_branch_src2_4;
_zz_execute_BranchPlugin_branch_src2_5[17] = _zz_execute_BranchPlugin_branch_src2_4;
_zz_execute_BranchPlugin_branch_src2_5[16] = _zz_execute_BranchPlugin_branch_src2_4;
_zz_execute_BranchPlugin_branch_src2_5[15] = _zz_execute_BranchPlugin_branch_src2_4;
_zz_execute_BranchPlugin_branch_src2_5[14] = _zz_execute_BranchPlugin_branch_src2_4;
_zz_execute_BranchPlugin_branch_src2_5[13] = _zz_execute_BranchPlugin_branch_src2_4;
_zz_execute_BranchPlugin_branch_src2_5[12] = _zz_execute_BranchPlugin_branch_src2_4;
_zz_execute_BranchPlugin_branch_src2_5[11] = _zz_execute_BranchPlugin_branch_src2_4;
_zz_execute_BranchPlugin_branch_src2_5[10] = _zz_execute_BranchPlugin_branch_src2_4;
_zz_execute_BranchPlugin_branch_src2_5[9] = _zz_execute_BranchPlugin_branch_src2_4;
_zz_execute_BranchPlugin_branch_src2_5[8] = _zz_execute_BranchPlugin_branch_src2_4;
_zz_execute_BranchPlugin_branch_src2_5[7] = _zz_execute_BranchPlugin_branch_src2_4;
_zz_execute_BranchPlugin_branch_src2_5[6] = _zz_execute_BranchPlugin_branch_src2_4;
_zz_execute_BranchPlugin_branch_src2_5[5] = _zz_execute_BranchPlugin_branch_src2_4;
_zz_execute_BranchPlugin_branch_src2_5[4] = _zz_execute_BranchPlugin_branch_src2_4;
_zz_execute_BranchPlugin_branch_src2_5[3] = _zz_execute_BranchPlugin_branch_src2_4;
_zz_execute_BranchPlugin_branch_src2_5[2] = _zz_execute_BranchPlugin_branch_src2_4;
_zz_execute_BranchPlugin_branch_src2_5[1] = _zz_execute_BranchPlugin_branch_src2_4;
_zz_execute_BranchPlugin_branch_src2_5[0] = _zz_execute_BranchPlugin_branch_src2_4;
end
assign execute_BranchPlugin_branchAdder = (execute_BranchPlugin_branch_src1 + execute_BranchPlugin_branch_src2);
assign BranchPlugin_jumpInterface_valid = ((execute_arbitration_isValid && execute_BRANCH_DO) && (! 1'b0));
assign BranchPlugin_jumpInterface_payload = execute_BRANCH_CALC;
always @(*) begin
BranchPlugin_branchExceptionPort_valid = (execute_arbitration_isValid && (execute_BRANCH_DO && execute_BRANCH_CALC[1]));
if(when_BranchPlugin_l296) begin
BranchPlugin_branchExceptionPort_valid = 1'b0;
end
end
assign BranchPlugin_branchExceptionPort_payload_code = 4'b0000;
assign BranchPlugin_branchExceptionPort_payload_badAddr = execute_BRANCH_CALC;
assign when_BranchPlugin_l296 = 1'b0;
assign IBusCachedPlugin_decodePrediction_rsp_wasWrong = BranchPlugin_jumpInterface_valid;
always @(*) begin
CsrPlugin_privilege = 2'b11;
if(CsrPlugin_forceMachineWire) begin
CsrPlugin_privilege = 2'b11;
end
end
assign _zz_when_CsrPlugin_l952 = (CsrPlugin_mip_MTIP && CsrPlugin_mie_MTIE);
assign _zz_when_CsrPlugin_l952_1 = (CsrPlugin_mip_MSIP && CsrPlugin_mie_MSIE);
assign _zz_when_CsrPlugin_l952_2 = (CsrPlugin_mip_MEIP && CsrPlugin_mie_MEIE);
assign CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = 2'b11;
assign CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege = ((CsrPlugin_privilege < CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped) ? CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped : CsrPlugin_privilege);
assign _zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code = {decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid};
assign _zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1 = _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1[0];
assign _zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_2 = {CsrPlugin_selfException_valid,BranchPlugin_branchExceptionPort_valid};
assign _zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_3 = _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_3[0];
always @(*) begin
CsrPlugin_exceptionPortCtrl_exceptionValids_decode = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode;
if(_zz_when) begin
CsrPlugin_exceptionPortCtrl_exceptionValids_decode = 1'b1;
end
if(decode_arbitration_isFlushed) begin
CsrPlugin_exceptionPortCtrl_exceptionValids_decode = 1'b0;
end
end
always @(*) begin
CsrPlugin_exceptionPortCtrl_exceptionValids_execute = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute;
if(_zz_when_1) begin
CsrPlugin_exceptionPortCtrl_exceptionValids_execute = 1'b1;
end
if(execute_arbitration_isFlushed) begin
CsrPlugin_exceptionPortCtrl_exceptionValids_execute = 1'b0;
end
end
always @(*) begin
CsrPlugin_exceptionPortCtrl_exceptionValids_memory = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory;
if(memory_arbitration_isFlushed) begin
CsrPlugin_exceptionPortCtrl_exceptionValids_memory = 1'b0;
end
end
always @(*) begin
CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack;
if(DBusCachedPlugin_exceptionBus_valid) begin
CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack = 1'b1;
end
if(writeBack_arbitration_isFlushed) begin
CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack = 1'b0;
end
end
assign when_CsrPlugin_l909 = (! decode_arbitration_isStuck);
assign when_CsrPlugin_l909_1 = (! execute_arbitration_isStuck);
assign when_CsrPlugin_l909_2 = (! memory_arbitration_isStuck);
assign when_CsrPlugin_l909_3 = (! writeBack_arbitration_isStuck);
assign when_CsrPlugin_l922 = ({CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValids_memory,{CsrPlugin_exceptionPortCtrl_exceptionValids_execute,CsrPlugin_exceptionPortCtrl_exceptionValids_decode}}} != 4'b0000);
assign CsrPlugin_exceptionPendings_0 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode;
assign CsrPlugin_exceptionPendings_1 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute;
assign CsrPlugin_exceptionPendings_2 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory;
assign CsrPlugin_exceptionPendings_3 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack;
assign when_CsrPlugin_l946 = (CsrPlugin_mstatus_MIE || (CsrPlugin_privilege < 2'b11));
assign when_CsrPlugin_l952 = ((_zz_when_CsrPlugin_l952 && 1'b1) && (! 1'b0));
assign when_CsrPlugin_l952_1 = ((_zz_when_CsrPlugin_l952_1 && 1'b1) && (! 1'b0));
assign when_CsrPlugin_l952_2 = ((_zz_when_CsrPlugin_l952_2 && 1'b1) && (! 1'b0));
assign CsrPlugin_exception = (CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack && CsrPlugin_allowException);
assign CsrPlugin_pipelineLiberator_active = ((CsrPlugin_interrupt_valid && CsrPlugin_allowInterrupts) && decode_arbitration_isValid);
assign when_CsrPlugin_l980 = (! execute_arbitration_isStuck);
assign when_CsrPlugin_l980_1 = (! memory_arbitration_isStuck);
assign when_CsrPlugin_l980_2 = (! writeBack_arbitration_isStuck);
assign when_CsrPlugin_l985 = ((! CsrPlugin_pipelineLiberator_active) || decode_arbitration_removeIt);
always @(*) begin
CsrPlugin_pipelineLiberator_done = CsrPlugin_pipelineLiberator_pcValids_2;
if(when_CsrPlugin_l991) begin
CsrPlugin_pipelineLiberator_done = 1'b0;
end
if(CsrPlugin_hadException) begin
CsrPlugin_pipelineLiberator_done = 1'b0;
end
end
assign when_CsrPlugin_l991 = ({CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory,CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute}} != 3'b000);
assign CsrPlugin_interruptJump = ((CsrPlugin_interrupt_valid && CsrPlugin_pipelineLiberator_done) && CsrPlugin_allowInterrupts);
always @(*) begin
CsrPlugin_targetPrivilege = CsrPlugin_interrupt_targetPrivilege;
if(CsrPlugin_hadException) begin
CsrPlugin_targetPrivilege = CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege;
end
end
always @(*) begin
CsrPlugin_trapCause = CsrPlugin_interrupt_code;
if(CsrPlugin_hadException) begin
CsrPlugin_trapCause = CsrPlugin_exceptionPortCtrl_exceptionContext_code;
end
end
always @(*) begin
CsrPlugin_xtvec_mode = 2'bxx;
case(CsrPlugin_targetPrivilege)
2'b11 : begin
CsrPlugin_xtvec_mode = CsrPlugin_mtvec_mode;
end
default : begin
end
endcase
end
always @(*) begin
CsrPlugin_xtvec_base = 30'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx;
case(CsrPlugin_targetPrivilege)
2'b11 : begin
CsrPlugin_xtvec_base = CsrPlugin_mtvec_base;
end
default : begin
end
endcase
end
assign when_CsrPlugin_l1019 = (CsrPlugin_hadException || CsrPlugin_interruptJump);
assign when_CsrPlugin_l1064 = (writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_binary_sequential_XRET));
assign switch_CsrPlugin_l1068 = writeBack_INSTRUCTION[29 : 28];
assign contextSwitching = CsrPlugin_jumpInterface_valid;
assign when_CsrPlugin_l1108 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_binary_sequential_WFI));
assign when_CsrPlugin_l1110 = (! execute_CsrPlugin_wfiWake);
assign when_CsrPlugin_l1116 = ({(writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_binary_sequential_XRET)),{(memory_arbitration_isValid && (memory_ENV_CTRL == `EnvCtrlEnum_binary_sequential_XRET)),(execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_binary_sequential_XRET))}} != 3'b000);
assign execute_CsrPlugin_blockedBySideEffects = (({writeBack_arbitration_isValid,memory_arbitration_isValid} != 2'b00) || 1'b0);
always @(*) begin
execute_CsrPlugin_illegalAccess = 1'b1;
if(execute_CsrPlugin_csr_3264) begin
if(execute_CSR_READ_OPCODE) begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
end
if(execute_CsrPlugin_csr_3857) begin
if(execute_CSR_READ_OPCODE) begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
end
if(execute_CsrPlugin_csr_3858) begin
if(execute_CSR_READ_OPCODE) begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
end
if(execute_CsrPlugin_csr_3859) begin
if(execute_CSR_READ_OPCODE) begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
end
if(execute_CsrPlugin_csr_3860) begin
if(execute_CSR_READ_OPCODE) begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
end
if(execute_CsrPlugin_csr_769) begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
if(execute_CsrPlugin_csr_768) begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
if(execute_CsrPlugin_csr_836) begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
if(execute_CsrPlugin_csr_772) begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
if(execute_CsrPlugin_csr_773) begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
if(execute_CsrPlugin_csr_833) begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
if(execute_CsrPlugin_csr_832) begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
if(execute_CsrPlugin_csr_834) begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
if(execute_CsrPlugin_csr_835) begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
if(execute_CsrPlugin_csr_2816) begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
if(execute_CsrPlugin_csr_2944) begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
if(execute_CsrPlugin_csr_2818) begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
if(execute_CsrPlugin_csr_2946) begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
if(execute_CsrPlugin_csr_3072) begin
if(execute_CSR_READ_OPCODE) begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
end
if(execute_CsrPlugin_csr_3200) begin
if(execute_CSR_READ_OPCODE) begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
end
if(execute_CsrPlugin_csr_3074) begin
if(execute_CSR_READ_OPCODE) begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
end
if(execute_CsrPlugin_csr_3202) begin
if(execute_CSR_READ_OPCODE) begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
end
if(execute_CsrPlugin_csr_3008) begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
if(execute_CsrPlugin_csr_4032) begin
if(execute_CSR_READ_OPCODE) begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
end
if(CsrPlugin_csrMapping_allowCsrSignal) begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
if(when_CsrPlugin_l1297) begin
execute_CsrPlugin_illegalAccess = 1'b1;
end
if(when_CsrPlugin_l1302) begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
end
always @(*) begin
execute_CsrPlugin_illegalInstruction = 1'b0;
if(when_CsrPlugin_l1136) begin
if(when_CsrPlugin_l1137) begin
execute_CsrPlugin_illegalInstruction = 1'b1;
end
end
end
always @(*) begin
CsrPlugin_selfException_valid = 1'b0;
if(when_CsrPlugin_l1129) begin
CsrPlugin_selfException_valid = 1'b1;
end
if(when_CsrPlugin_l1144) begin
CsrPlugin_selfException_valid = 1'b1;
end
end
always @(*) begin
CsrPlugin_selfException_payload_code = 4'bxxxx;
if(when_CsrPlugin_l1129) begin
CsrPlugin_selfException_payload_code = 4'b0010;
end
if(when_CsrPlugin_l1144) begin
case(CsrPlugin_privilege)
2'b00 : begin
CsrPlugin_selfException_payload_code = 4'b1000;
end
default : begin
CsrPlugin_selfException_payload_code = 4'b1011;
end
endcase
end
end
assign CsrPlugin_selfException_payload_badAddr = execute_INSTRUCTION;
assign when_CsrPlugin_l1129 = (execute_CsrPlugin_illegalAccess || execute_CsrPlugin_illegalInstruction);
assign when_CsrPlugin_l1136 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_binary_sequential_XRET));
assign when_CsrPlugin_l1137 = (CsrPlugin_privilege < execute_INSTRUCTION[29 : 28]);
assign when_CsrPlugin_l1144 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_binary_sequential_ECALL));
always @(*) begin
execute_CsrPlugin_writeInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_WRITE_OPCODE);
if(when_CsrPlugin_l1297) begin
execute_CsrPlugin_writeInstruction = 1'b0;
end
end
always @(*) begin
execute_CsrPlugin_readInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_READ_OPCODE);
if(when_CsrPlugin_l1297) begin
execute_CsrPlugin_readInstruction = 1'b0;
end
end
assign execute_CsrPlugin_writeEnable = (execute_CsrPlugin_writeInstruction && (! execute_arbitration_isStuck));
assign execute_CsrPlugin_readEnable = (execute_CsrPlugin_readInstruction && (! execute_arbitration_isStuck));
assign CsrPlugin_csrMapping_hazardFree = (! execute_CsrPlugin_blockedBySideEffects);
assign execute_CsrPlugin_readToWriteData = CsrPlugin_csrMapping_readDataSignal;
assign switch_Misc_l200_2 = execute_INSTRUCTION[13];
always @(*) begin
case(switch_Misc_l200_2)
1'b0 : begin
_zz_CsrPlugin_csrMapping_writeDataSignal = execute_SRC1;
end
default : begin
_zz_CsrPlugin_csrMapping_writeDataSignal = (execute_INSTRUCTION[12] ? (execute_CsrPlugin_readToWriteData & (~ execute_SRC1)) : (execute_CsrPlugin_readToWriteData | execute_SRC1));
end
endcase
end
assign CsrPlugin_csrMapping_writeDataSignal = _zz_CsrPlugin_csrMapping_writeDataSignal;
assign when_CsrPlugin_l1176 = (execute_arbitration_isValid && execute_IS_CSR);
assign when_CsrPlugin_l1180 = (execute_arbitration_isValid && (execute_IS_CSR || 1'b0));
assign execute_CsrPlugin_csrAddress = execute_INSTRUCTION[31 : 20];
assign execute_MulPlugin_a = execute_RS1;
assign execute_MulPlugin_b = execute_RS2;
assign switch_MulPlugin_l87 = execute_INSTRUCTION[13 : 12];
always @(*) begin
case(switch_MulPlugin_l87)
2'b01 : begin
execute_MulPlugin_aSigned = 1'b1;
end
2'b10 : begin
execute_MulPlugin_aSigned = 1'b1;
end
default : begin
execute_MulPlugin_aSigned = 1'b0;
end
endcase
end
always @(*) begin
case(switch_MulPlugin_l87)
2'b01 : begin
execute_MulPlugin_bSigned = 1'b1;
end
2'b10 : begin
execute_MulPlugin_bSigned = 1'b0;
end
default : begin
execute_MulPlugin_bSigned = 1'b0;
end
endcase
end
assign execute_MulPlugin_aULow = execute_MulPlugin_a[15 : 0];
assign execute_MulPlugin_bULow = execute_MulPlugin_b[15 : 0];
assign execute_MulPlugin_aSLow = {1'b0,execute_MulPlugin_a[15 : 0]};
assign execute_MulPlugin_bSLow = {1'b0,execute_MulPlugin_b[15 : 0]};
assign execute_MulPlugin_aHigh = {(execute_MulPlugin_aSigned && execute_MulPlugin_a[31]),execute_MulPlugin_a[31 : 16]};
assign execute_MulPlugin_bHigh = {(execute_MulPlugin_bSigned && execute_MulPlugin_b[31]),execute_MulPlugin_b[31 : 16]};
assign writeBack_MulPlugin_result = ($signed(_zz_writeBack_MulPlugin_result) + $signed(_zz_writeBack_MulPlugin_result_1));
assign when_MulPlugin_l147 = (writeBack_arbitration_isValid && writeBack_IS_MUL);
assign switch_MulPlugin_l148 = writeBack_INSTRUCTION[13 : 12];
assign memory_DivPlugin_frontendOk = 1'b1;
always @(*) begin
memory_DivPlugin_div_counter_willIncrement = 1'b0;
if(when_MulDivIterativePlugin_l128) begin
if(when_MulDivIterativePlugin_l132) begin
memory_DivPlugin_div_counter_willIncrement = 1'b1;
end
end
end
always @(*) begin
memory_DivPlugin_div_counter_willClear = 1'b0;
if(when_MulDivIterativePlugin_l162) begin
memory_DivPlugin_div_counter_willClear = 1'b1;
end
end
assign memory_DivPlugin_div_counter_willOverflowIfInc = (memory_DivPlugin_div_counter_value == 6'h21);
assign memory_DivPlugin_div_counter_willOverflow = (memory_DivPlugin_div_counter_willOverflowIfInc && memory_DivPlugin_div_counter_willIncrement);
always @(*) begin
if(memory_DivPlugin_div_counter_willOverflow) begin
memory_DivPlugin_div_counter_valueNext = 6'h0;
end else begin
memory_DivPlugin_div_counter_valueNext = (memory_DivPlugin_div_counter_value + _zz_memory_DivPlugin_div_counter_valueNext);
end
if(memory_DivPlugin_div_counter_willClear) begin
memory_DivPlugin_div_counter_valueNext = 6'h0;
end
end
assign when_MulDivIterativePlugin_l126 = (memory_DivPlugin_div_counter_value == 6'h20);
assign when_MulDivIterativePlugin_l126_1 = (! memory_arbitration_isStuck);
assign when_MulDivIterativePlugin_l128 = (memory_arbitration_isValid && memory_IS_DIV);
assign when_MulDivIterativePlugin_l129 = ((! memory_DivPlugin_frontendOk) || (! memory_DivPlugin_div_done));
assign when_MulDivIterativePlugin_l132 = (memory_DivPlugin_frontendOk && (! memory_DivPlugin_div_done));
assign _zz_memory_DivPlugin_div_stage_0_remainderShifted = memory_DivPlugin_rs1[31 : 0];
assign memory_DivPlugin_div_stage_0_remainderShifted = {memory_DivPlugin_accumulator[31 : 0],_zz_memory_DivPlugin_div_stage_0_remainderShifted[31]};
assign memory_DivPlugin_div_stage_0_remainderMinusDenominator = (memory_DivPlugin_div_stage_0_remainderShifted - _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator);
assign memory_DivPlugin_div_stage_0_outRemainder = ((! memory_DivPlugin_div_stage_0_remainderMinusDenominator[32]) ? _zz_memory_DivPlugin_div_stage_0_outRemainder : _zz_memory_DivPlugin_div_stage_0_outRemainder_1);
assign memory_DivPlugin_div_stage_0_outNumerator = _zz_memory_DivPlugin_div_stage_0_outNumerator[31:0];
assign when_MulDivIterativePlugin_l151 = (memory_DivPlugin_div_counter_value == 6'h20);
assign _zz_memory_DivPlugin_div_result = (memory_INSTRUCTION[13] ? memory_DivPlugin_accumulator[31 : 0] : memory_DivPlugin_rs1[31 : 0]);
assign when_MulDivIterativePlugin_l162 = (! memory_arbitration_isStuck);
assign _zz_memory_DivPlugin_rs2 = (execute_RS2[31] && execute_IS_RS2_SIGNED);
assign _zz_memory_DivPlugin_rs1 = (1'b0 || ((execute_IS_DIV && execute_RS1[31]) && execute_IS_RS1_SIGNED));
always @(*) begin
_zz_memory_DivPlugin_rs1_1[32] = (execute_IS_RS1_SIGNED && execute_RS1[31]);
_zz_memory_DivPlugin_rs1_1[31 : 0] = execute_RS1;
end
assign _zz_CsrPlugin_csrMapping_readDataInit_1 = (_zz_CsrPlugin_csrMapping_readDataInit & externalInterruptArray_regNext);
assign externalInterrupt = (_zz_CsrPlugin_csrMapping_readDataInit_1 != 32'h0);
assign when_DebugPlugin_l225 = (DebugPlugin_haltIt && (! DebugPlugin_isPipBusy));
assign DebugPlugin_allowEBreak = (DebugPlugin_debugUsed && (! DebugPlugin_disableEbreak));
always @(*) begin
debug_bus_cmd_ready = 1'b1;
if(debug_bus_cmd_valid) begin
case(switch_DebugPlugin_l256)
6'h01 : begin
if(debug_bus_cmd_payload_wr) begin
debug_bus_cmd_ready = IBusCachedPlugin_injectionPort_ready;
end
end
default : begin
end
endcase
end
end
always @(*) begin
debug_bus_rsp_data = DebugPlugin_busReadDataReg;
if(when_DebugPlugin_l244) begin
debug_bus_rsp_data[0] = DebugPlugin_resetIt;
debug_bus_rsp_data[1] = DebugPlugin_haltIt;
debug_bus_rsp_data[2] = DebugPlugin_isPipBusy;
debug_bus_rsp_data[3] = DebugPlugin_haltedByBreak;
debug_bus_rsp_data[4] = DebugPlugin_stepIt;
end
end
assign when_DebugPlugin_l244 = (! _zz_when_DebugPlugin_l244);
always @(*) begin
IBusCachedPlugin_injectionPort_valid = 1'b0;
if(debug_bus_cmd_valid) begin
case(switch_DebugPlugin_l256)
6'h01 : begin
if(debug_bus_cmd_payload_wr) begin
IBusCachedPlugin_injectionPort_valid = 1'b1;
end
end
default : begin
end
endcase
end
end
assign IBusCachedPlugin_injectionPort_payload = debug_bus_cmd_payload_data;
assign switch_DebugPlugin_l256 = debug_bus_cmd_payload_address[7 : 2];
assign when_DebugPlugin_l260 = debug_bus_cmd_payload_data[16];
assign when_DebugPlugin_l260_1 = debug_bus_cmd_payload_data[24];
assign when_DebugPlugin_l261 = debug_bus_cmd_payload_data[17];
assign when_DebugPlugin_l261_1 = debug_bus_cmd_payload_data[25];
assign when_DebugPlugin_l262 = debug_bus_cmd_payload_data[25];
assign when_DebugPlugin_l263 = debug_bus_cmd_payload_data[25];
assign when_DebugPlugin_l264 = debug_bus_cmd_payload_data[18];
assign when_DebugPlugin_l264_1 = debug_bus_cmd_payload_data[26];
assign when_DebugPlugin_l284 = (execute_arbitration_isValid && execute_DO_EBREAK);
assign when_DebugPlugin_l287 = (({writeBack_arbitration_isValid,memory_arbitration_isValid} != 2'b00) == 1'b0);
assign when_DebugPlugin_l300 = (DebugPlugin_stepIt && IBusCachedPlugin_incomingInstruction);
assign debug_resetOut = DebugPlugin_resetIt_regNext;
assign when_DebugPlugin_l316 = (DebugPlugin_haltIt || DebugPlugin_stepIt);
assign execute_CfuPlugin_schedule = (execute_arbitration_isValid && execute_CfuPlugin_CFU_ENABLE);
assign CfuPlugin_bus_cmd_fire = (CfuPlugin_bus_cmd_valid && CfuPlugin_bus_cmd_ready);
assign when_CfuPlugin_l171 = (! execute_arbitration_isStuckByOthers);
assign CfuPlugin_bus_cmd_valid = ((execute_CfuPlugin_schedule || execute_CfuPlugin_hold) && (! execute_CfuPlugin_fired));
assign when_CfuPlugin_l175 = (CfuPlugin_bus_cmd_valid && (! CfuPlugin_bus_cmd_ready));
assign execute_CfuPlugin_functionsIds_0 = _zz_execute_CfuPlugin_functionsIds_0;
assign CfuPlugin_bus_cmd_payload_function_id = execute_CfuPlugin_functionsIds_0;
assign CfuPlugin_bus_cmd_payload_inputs_0 = execute_RS1;
assign _zz_CfuPlugin_bus_cmd_payload_inputs_1 = execute_INSTRUCTION[31];
always @(*) begin
_zz_CfuPlugin_bus_cmd_payload_inputs_1_1[23] = _zz_CfuPlugin_bus_cmd_payload_inputs_1;
_zz_CfuPlugin_bus_cmd_payload_inputs_1_1[22] = _zz_CfuPlugin_bus_cmd_payload_inputs_1;
_zz_CfuPlugin_bus_cmd_payload_inputs_1_1[21] = _zz_CfuPlugin_bus_cmd_payload_inputs_1;
_zz_CfuPlugin_bus_cmd_payload_inputs_1_1[20] = _zz_CfuPlugin_bus_cmd_payload_inputs_1;
_zz_CfuPlugin_bus_cmd_payload_inputs_1_1[19] = _zz_CfuPlugin_bus_cmd_payload_inputs_1;
_zz_CfuPlugin_bus_cmd_payload_inputs_1_1[18] = _zz_CfuPlugin_bus_cmd_payload_inputs_1;
_zz_CfuPlugin_bus_cmd_payload_inputs_1_1[17] = _zz_CfuPlugin_bus_cmd_payload_inputs_1;
_zz_CfuPlugin_bus_cmd_payload_inputs_1_1[16] = _zz_CfuPlugin_bus_cmd_payload_inputs_1;
_zz_CfuPlugin_bus_cmd_payload_inputs_1_1[15] = _zz_CfuPlugin_bus_cmd_payload_inputs_1;
_zz_CfuPlugin_bus_cmd_payload_inputs_1_1[14] = _zz_CfuPlugin_bus_cmd_payload_inputs_1;
_zz_CfuPlugin_bus_cmd_payload_inputs_1_1[13] = _zz_CfuPlugin_bus_cmd_payload_inputs_1;
_zz_CfuPlugin_bus_cmd_payload_inputs_1_1[12] = _zz_CfuPlugin_bus_cmd_payload_inputs_1;
_zz_CfuPlugin_bus_cmd_payload_inputs_1_1[11] = _zz_CfuPlugin_bus_cmd_payload_inputs_1;
_zz_CfuPlugin_bus_cmd_payload_inputs_1_1[10] = _zz_CfuPlugin_bus_cmd_payload_inputs_1;
_zz_CfuPlugin_bus_cmd_payload_inputs_1_1[9] = _zz_CfuPlugin_bus_cmd_payload_inputs_1;
_zz_CfuPlugin_bus_cmd_payload_inputs_1_1[8] = _zz_CfuPlugin_bus_cmd_payload_inputs_1;
_zz_CfuPlugin_bus_cmd_payload_inputs_1_1[7] = _zz_CfuPlugin_bus_cmd_payload_inputs_1;
_zz_CfuPlugin_bus_cmd_payload_inputs_1_1[6] = _zz_CfuPlugin_bus_cmd_payload_inputs_1;
_zz_CfuPlugin_bus_cmd_payload_inputs_1_1[5] = _zz_CfuPlugin_bus_cmd_payload_inputs_1;
_zz_CfuPlugin_bus_cmd_payload_inputs_1_1[4] = _zz_CfuPlugin_bus_cmd_payload_inputs_1;
_zz_CfuPlugin_bus_cmd_payload_inputs_1_1[3] = _zz_CfuPlugin_bus_cmd_payload_inputs_1;
_zz_CfuPlugin_bus_cmd_payload_inputs_1_1[2] = _zz_CfuPlugin_bus_cmd_payload_inputs_1;
_zz_CfuPlugin_bus_cmd_payload_inputs_1_1[1] = _zz_CfuPlugin_bus_cmd_payload_inputs_1;
_zz_CfuPlugin_bus_cmd_payload_inputs_1_1[0] = _zz_CfuPlugin_bus_cmd_payload_inputs_1;
end
always @(*) begin
case(execute_CfuPlugin_CFU_INPUT_2_KIND)
`Input2Kind_binary_sequential_RS : begin
_zz_CfuPlugin_bus_cmd_payload_inputs_1_2 = execute_RS2;
end
default : begin
_zz_CfuPlugin_bus_cmd_payload_inputs_1_2 = {_zz_CfuPlugin_bus_cmd_payload_inputs_1_1,execute_INSTRUCTION[31 : 24]};
end
endcase
end
assign CfuPlugin_bus_cmd_payload_inputs_1 = _zz_CfuPlugin_bus_cmd_payload_inputs_1_2;
assign CfuPlugin_bus_rsp_ready = (! CfuPlugin_bus_rsp_rValid);
assign CfuPlugin_bus_rsp_rsp_valid = (CfuPlugin_bus_rsp_valid || CfuPlugin_bus_rsp_rValid);
assign CfuPlugin_bus_rsp_rsp_payload_outputs_0 = (CfuPlugin_bus_rsp_rValid ? CfuPlugin_bus_rsp_rData_outputs_0 : CfuPlugin_bus_rsp_payload_outputs_0);
always @(*) begin
CfuPlugin_bus_rsp_rsp_ready = 1'b0;
if(memory_CfuPlugin_CFU_IN_FLIGHT) begin
CfuPlugin_bus_rsp_rsp_ready = (! memory_arbitration_isStuckByOthers);
end
end
assign when_CfuPlugin_l208 = (! CfuPlugin_bus_rsp_rsp_valid);
assign when_Pipeline_l124 = (! execute_arbitration_isStuck);
assign when_Pipeline_l124_1 = (! memory_arbitration_isStuck);
assign when_Pipeline_l124_2 = ((! writeBack_arbitration_isStuck) && (! CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack));
assign when_Pipeline_l124_3 = (! execute_arbitration_isStuck);
assign when_Pipeline_l124_4 = (! memory_arbitration_isStuck);
assign when_Pipeline_l124_5 = (! writeBack_arbitration_isStuck);
assign when_Pipeline_l124_6 = (! execute_arbitration_isStuck);
assign when_Pipeline_l124_7 = (! memory_arbitration_isStuck);
assign when_Pipeline_l124_8 = (! writeBack_arbitration_isStuck);
assign when_Pipeline_l124_9 = (! execute_arbitration_isStuck);
assign _zz_decode_to_execute_SRC1_CTRL_1 = decode_SRC1_CTRL;
assign _zz_decode_SRC1_CTRL = _zz_decode_SRC1_CTRL_1;
assign when_Pipeline_l124_10 = (! execute_arbitration_isStuck);
assign _zz_execute_SRC1_CTRL = decode_to_execute_SRC1_CTRL;
assign when_Pipeline_l124_11 = (! execute_arbitration_isStuck);
assign when_Pipeline_l124_12 = (! execute_arbitration_isStuck);
assign when_Pipeline_l124_13 = (! memory_arbitration_isStuck);
assign when_Pipeline_l124_14 = (! writeBack_arbitration_isStuck);
assign _zz_decode_to_execute_ALU_CTRL_1 = decode_ALU_CTRL;
assign _zz_decode_ALU_CTRL = _zz_decode_ALU_CTRL_1;
assign when_Pipeline_l124_15 = (! execute_arbitration_isStuck);
assign _zz_execute_ALU_CTRL = decode_to_execute_ALU_CTRL;
assign _zz_decode_to_execute_SRC2_CTRL_1 = decode_SRC2_CTRL;
assign _zz_decode_SRC2_CTRL = _zz_decode_SRC2_CTRL_1;
assign when_Pipeline_l124_16 = (! execute_arbitration_isStuck);
assign _zz_execute_SRC2_CTRL = decode_to_execute_SRC2_CTRL;
assign when_Pipeline_l124_17 = (! execute_arbitration_isStuck);
assign when_Pipeline_l124_18 = (! memory_arbitration_isStuck);
assign when_Pipeline_l124_19 = (! writeBack_arbitration_isStuck);
assign when_Pipeline_l124_20 = (! execute_arbitration_isStuck);
assign when_Pipeline_l124_21 = (! execute_arbitration_isStuck);
assign when_Pipeline_l124_22 = (! memory_arbitration_isStuck);
assign when_Pipeline_l124_23 = (! execute_arbitration_isStuck);
assign when_Pipeline_l124_24 = (! memory_arbitration_isStuck);
assign when_Pipeline_l124_25 = (! writeBack_arbitration_isStuck);
assign when_Pipeline_l124_26 = (! execute_arbitration_isStuck);
assign when_Pipeline_l124_27 = (! execute_arbitration_isStuck);
assign _zz_decode_to_execute_ALU_BITWISE_CTRL_1 = decode_ALU_BITWISE_CTRL;
assign _zz_decode_ALU_BITWISE_CTRL = _zz_decode_ALU_BITWISE_CTRL_1;
assign when_Pipeline_l124_28 = (! execute_arbitration_isStuck);
assign _zz_execute_ALU_BITWISE_CTRL = decode_to_execute_ALU_BITWISE_CTRL;
assign _zz_decode_to_execute_SHIFT_CTRL_1 = decode_SHIFT_CTRL;
assign _zz_execute_to_memory_SHIFT_CTRL_1 = execute_SHIFT_CTRL;
assign _zz_decode_SHIFT_CTRL = _zz_decode_SHIFT_CTRL_1;
assign when_Pipeline_l124_29 = (! execute_arbitration_isStuck);
assign _zz_execute_SHIFT_CTRL = decode_to_execute_SHIFT_CTRL;
assign when_Pipeline_l124_30 = (! memory_arbitration_isStuck);
assign _zz_memory_SHIFT_CTRL = execute_to_memory_SHIFT_CTRL;
assign _zz_decode_to_execute_BRANCH_CTRL_1 = decode_BRANCH_CTRL;
assign _zz_decode_BRANCH_CTRL_1 = _zz_decode_BRANCH_CTRL;
assign when_Pipeline_l124_31 = (! execute_arbitration_isStuck);
assign _zz_execute_BRANCH_CTRL = decode_to_execute_BRANCH_CTRL;
assign when_Pipeline_l124_32 = (! execute_arbitration_isStuck);
assign _zz_decode_to_execute_ENV_CTRL_1 = decode_ENV_CTRL;
assign _zz_execute_to_memory_ENV_CTRL_1 = execute_ENV_CTRL;
assign _zz_memory_to_writeBack_ENV_CTRL_1 = memory_ENV_CTRL;
assign _zz_decode_ENV_CTRL = _zz_decode_ENV_CTRL_1;
assign when_Pipeline_l124_33 = (! execute_arbitration_isStuck);
assign _zz_execute_ENV_CTRL = decode_to_execute_ENV_CTRL;
assign when_Pipeline_l124_34 = (! memory_arbitration_isStuck);
assign _zz_memory_ENV_CTRL = execute_to_memory_ENV_CTRL;
assign when_Pipeline_l124_35 = (! writeBack_arbitration_isStuck);
assign _zz_writeBack_ENV_CTRL = memory_to_writeBack_ENV_CTRL;
assign when_Pipeline_l124_36 = (! execute_arbitration_isStuck);
assign when_Pipeline_l124_37 = (! memory_arbitration_isStuck);
assign when_Pipeline_l124_38 = (! writeBack_arbitration_isStuck);
assign when_Pipeline_l124_39 = (! execute_arbitration_isStuck);
assign when_Pipeline_l124_40 = (! memory_arbitration_isStuck);
assign when_Pipeline_l124_41 = (! execute_arbitration_isStuck);
assign when_Pipeline_l124_42 = (! execute_arbitration_isStuck);
assign when_Pipeline_l124_43 = (! execute_arbitration_isStuck);
assign _zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_1 = decode_CfuPlugin_CFU_INPUT_2_KIND;
assign _zz_decode_CfuPlugin_CFU_INPUT_2_KIND = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_1;
assign when_Pipeline_l124_44 = (! execute_arbitration_isStuck);
assign _zz_execute_CfuPlugin_CFU_INPUT_2_KIND = decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND;
assign when_Pipeline_l124_45 = (! execute_arbitration_isStuck);
assign when_Pipeline_l124_46 = (! execute_arbitration_isStuck);
assign when_Pipeline_l124_47 = (! execute_arbitration_isStuck);
assign when_Pipeline_l124_48 = (! execute_arbitration_isStuck);
assign when_Pipeline_l124_49 = (! execute_arbitration_isStuck);
assign when_Pipeline_l124_50 = (! execute_arbitration_isStuck);
assign when_Pipeline_l124_51 = (! execute_arbitration_isStuck);
assign when_Pipeline_l124_52 = (! memory_arbitration_isStuck);
assign when_Pipeline_l124_53 = (! writeBack_arbitration_isStuck);
assign when_Pipeline_l124_54 = (! memory_arbitration_isStuck);
assign when_Pipeline_l124_55 = (! writeBack_arbitration_isStuck);
assign when_Pipeline_l124_56 = (! memory_arbitration_isStuck);
assign when_Pipeline_l124_57 = (! memory_arbitration_isStuck);
assign when_Pipeline_l124_58 = (! memory_arbitration_isStuck);
assign when_Pipeline_l124_59 = (! memory_arbitration_isStuck);
assign when_Pipeline_l124_60 = (! memory_arbitration_isStuck);
assign when_Pipeline_l124_61 = (! writeBack_arbitration_isStuck);
assign when_Pipeline_l124_62 = (! memory_arbitration_isStuck);
assign when_Pipeline_l124_63 = (! writeBack_arbitration_isStuck);
assign when_Pipeline_l124_64 = (! writeBack_arbitration_isStuck);
assign decode_arbitration_isFlushed = (({writeBack_arbitration_flushNext,{memory_arbitration_flushNext,execute_arbitration_flushNext}} != 3'b000) || ({writeBack_arbitration_flushIt,{memory_arbitration_flushIt,{execute_arbitration_flushIt,decode_arbitration_flushIt}}} != 4'b0000));
assign execute_arbitration_isFlushed = (({writeBack_arbitration_flushNext,memory_arbitration_flushNext} != 2'b00) || ({writeBack_arbitration_flushIt,{memory_arbitration_flushIt,execute_arbitration_flushIt}} != 3'b000));
assign memory_arbitration_isFlushed = ((writeBack_arbitration_flushNext != 1'b0) || ({writeBack_arbitration_flushIt,memory_arbitration_flushIt} != 2'b00));
assign writeBack_arbitration_isFlushed = (1'b0 || (writeBack_arbitration_flushIt != 1'b0));
assign decode_arbitration_isStuckByOthers = (decode_arbitration_haltByOther || (((1'b0 || execute_arbitration_isStuck) || memory_arbitration_isStuck) || writeBack_arbitration_isStuck));
assign decode_arbitration_isStuck = (decode_arbitration_haltItself || decode_arbitration_isStuckByOthers);
assign decode_arbitration_isMoving = ((! decode_arbitration_isStuck) && (! decode_arbitration_removeIt));
assign decode_arbitration_isFiring = ((decode_arbitration_isValid && (! decode_arbitration_isStuck)) && (! decode_arbitration_removeIt));
assign execute_arbitration_isStuckByOthers = (execute_arbitration_haltByOther || ((1'b0 || memory_arbitration_isStuck) || writeBack_arbitration_isStuck));
assign execute_arbitration_isStuck = (execute_arbitration_haltItself || execute_arbitration_isStuckByOthers);
assign execute_arbitration_isMoving = ((! execute_arbitration_isStuck) && (! execute_arbitration_removeIt));
assign execute_arbitration_isFiring = ((execute_arbitration_isValid && (! execute_arbitration_isStuck)) && (! execute_arbitration_removeIt));
assign memory_arbitration_isStuckByOthers = (memory_arbitration_haltByOther || (1'b0 || writeBack_arbitration_isStuck));
assign memory_arbitration_isStuck = (memory_arbitration_haltItself || memory_arbitration_isStuckByOthers);
assign memory_arbitration_isMoving = ((! memory_arbitration_isStuck) && (! memory_arbitration_removeIt));
assign memory_arbitration_isFiring = ((memory_arbitration_isValid && (! memory_arbitration_isStuck)) && (! memory_arbitration_removeIt));
assign writeBack_arbitration_isStuckByOthers = (writeBack_arbitration_haltByOther || 1'b0);
assign writeBack_arbitration_isStuck = (writeBack_arbitration_haltItself || writeBack_arbitration_isStuckByOthers);
assign writeBack_arbitration_isMoving = ((! writeBack_arbitration_isStuck) && (! writeBack_arbitration_removeIt));
assign writeBack_arbitration_isFiring = ((writeBack_arbitration_isValid && (! writeBack_arbitration_isStuck)) && (! writeBack_arbitration_removeIt));
assign when_Pipeline_l151 = ((! execute_arbitration_isStuck) || execute_arbitration_removeIt);
assign when_Pipeline_l154 = ((! decode_arbitration_isStuck) && (! decode_arbitration_removeIt));
assign when_Pipeline_l151_1 = ((! memory_arbitration_isStuck) || memory_arbitration_removeIt);
assign when_Pipeline_l154_1 = ((! execute_arbitration_isStuck) && (! execute_arbitration_removeIt));
assign when_Pipeline_l151_2 = ((! writeBack_arbitration_isStuck) || writeBack_arbitration_removeIt);
assign when_Pipeline_l154_2 = ((! memory_arbitration_isStuck) && (! memory_arbitration_removeIt));
always @(*) begin
IBusCachedPlugin_injectionPort_ready = 1'b0;
case(switch_Fetcher_l362)
3'b100 : begin
IBusCachedPlugin_injectionPort_ready = 1'b1;
end
default : begin
end
endcase
end
assign when_Fetcher_l378 = (! decode_arbitration_isStuck);
assign when_CsrPlugin_l1264 = (! execute_arbitration_isStuck);
assign when_CsrPlugin_l1264_1 = (! execute_arbitration_isStuck);
assign when_CsrPlugin_l1264_2 = (! execute_arbitration_isStuck);
assign when_CsrPlugin_l1264_3 = (! execute_arbitration_isStuck);
assign when_CsrPlugin_l1264_4 = (! execute_arbitration_isStuck);
assign when_CsrPlugin_l1264_5 = (! execute_arbitration_isStuck);
assign when_CsrPlugin_l1264_6 = (! execute_arbitration_isStuck);
assign when_CsrPlugin_l1264_7 = (! execute_arbitration_isStuck);
assign when_CsrPlugin_l1264_8 = (! execute_arbitration_isStuck);
assign when_CsrPlugin_l1264_9 = (! execute_arbitration_isStuck);
assign when_CsrPlugin_l1264_10 = (! execute_arbitration_isStuck);
assign when_CsrPlugin_l1264_11 = (! execute_arbitration_isStuck);
assign when_CsrPlugin_l1264_12 = (! execute_arbitration_isStuck);
assign when_CsrPlugin_l1264_13 = (! execute_arbitration_isStuck);
assign when_CsrPlugin_l1264_14 = (! execute_arbitration_isStuck);
assign when_CsrPlugin_l1264_15 = (! execute_arbitration_isStuck);
assign when_CsrPlugin_l1264_16 = (! execute_arbitration_isStuck);
assign when_CsrPlugin_l1264_17 = (! execute_arbitration_isStuck);
assign when_CsrPlugin_l1264_18 = (! execute_arbitration_isStuck);
assign when_CsrPlugin_l1264_19 = (! execute_arbitration_isStuck);
assign when_CsrPlugin_l1264_20 = (! execute_arbitration_isStuck);
assign when_CsrPlugin_l1264_21 = (! execute_arbitration_isStuck);
assign when_CsrPlugin_l1264_22 = (! execute_arbitration_isStuck);
assign when_CsrPlugin_l1264_23 = (! execute_arbitration_isStuck);
always @(*) begin
_zz_CsrPlugin_csrMapping_readDataInit_2 = 32'h0;
if(execute_CsrPlugin_csr_3264) begin
_zz_CsrPlugin_csrMapping_readDataInit_2[12 : 0] = 13'h1000;
_zz_CsrPlugin_csrMapping_readDataInit_2[25 : 20] = 6'h20;
end
end
always @(*) begin
_zz_CsrPlugin_csrMapping_readDataInit_3 = 32'h0;
if(execute_CsrPlugin_csr_3857) begin
_zz_CsrPlugin_csrMapping_readDataInit_3[3 : 0] = 4'b1011;
end
end
always @(*) begin
_zz_CsrPlugin_csrMapping_readDataInit_4 = 32'h0;
if(execute_CsrPlugin_csr_3858) begin
_zz_CsrPlugin_csrMapping_readDataInit_4[4 : 0] = 5'h16;
end
end
always @(*) begin
_zz_CsrPlugin_csrMapping_readDataInit_5 = 32'h0;
if(execute_CsrPlugin_csr_3859) begin
_zz_CsrPlugin_csrMapping_readDataInit_5[5 : 0] = 6'h21;
end
end
always @(*) begin
_zz_CsrPlugin_csrMapping_readDataInit_6 = 32'h0;
if(execute_CsrPlugin_csr_769) begin
_zz_CsrPlugin_csrMapping_readDataInit_6[31 : 30] = CsrPlugin_misa_base;
_zz_CsrPlugin_csrMapping_readDataInit_6[25 : 0] = CsrPlugin_misa_extensions;
end
end
always @(*) begin
_zz_CsrPlugin_csrMapping_readDataInit_7 = 32'h0;
if(execute_CsrPlugin_csr_768) begin
_zz_CsrPlugin_csrMapping_readDataInit_7[12 : 11] = CsrPlugin_mstatus_MPP;
_zz_CsrPlugin_csrMapping_readDataInit_7[7 : 7] = CsrPlugin_mstatus_MPIE;
_zz_CsrPlugin_csrMapping_readDataInit_7[3 : 3] = CsrPlugin_mstatus_MIE;
end
end
always @(*) begin
_zz_CsrPlugin_csrMapping_readDataInit_8 = 32'h0;
if(execute_CsrPlugin_csr_836) begin
_zz_CsrPlugin_csrMapping_readDataInit_8[11 : 11] = CsrPlugin_mip_MEIP;
_zz_CsrPlugin_csrMapping_readDataInit_8[7 : 7] = CsrPlugin_mip_MTIP;
_zz_CsrPlugin_csrMapping_readDataInit_8[3 : 3] = CsrPlugin_mip_MSIP;
end
end
always @(*) begin
_zz_CsrPlugin_csrMapping_readDataInit_9 = 32'h0;
if(execute_CsrPlugin_csr_772) begin
_zz_CsrPlugin_csrMapping_readDataInit_9[11 : 11] = CsrPlugin_mie_MEIE;
_zz_CsrPlugin_csrMapping_readDataInit_9[7 : 7] = CsrPlugin_mie_MTIE;
_zz_CsrPlugin_csrMapping_readDataInit_9[3 : 3] = CsrPlugin_mie_MSIE;
end
end
always @(*) begin
_zz_CsrPlugin_csrMapping_readDataInit_10 = 32'h0;
if(execute_CsrPlugin_csr_773) begin
_zz_CsrPlugin_csrMapping_readDataInit_10[31 : 2] = CsrPlugin_mtvec_base;
_zz_CsrPlugin_csrMapping_readDataInit_10[1 : 0] = CsrPlugin_mtvec_mode;
end
end
always @(*) begin
_zz_CsrPlugin_csrMapping_readDataInit_11 = 32'h0;
if(execute_CsrPlugin_csr_833) begin
_zz_CsrPlugin_csrMapping_readDataInit_11[31 : 0] = CsrPlugin_mepc;
end
end
always @(*) begin
_zz_CsrPlugin_csrMapping_readDataInit_12 = 32'h0;
if(execute_CsrPlugin_csr_832) begin
_zz_CsrPlugin_csrMapping_readDataInit_12[31 : 0] = CsrPlugin_mscratch;
end
end
always @(*) begin
_zz_CsrPlugin_csrMapping_readDataInit_13 = 32'h0;
if(execute_CsrPlugin_csr_834) begin
_zz_CsrPlugin_csrMapping_readDataInit_13[31 : 31] = CsrPlugin_mcause_interrupt;
_zz_CsrPlugin_csrMapping_readDataInit_13[3 : 0] = CsrPlugin_mcause_exceptionCode;
end
end
always @(*) begin
_zz_CsrPlugin_csrMapping_readDataInit_14 = 32'h0;
if(execute_CsrPlugin_csr_835) begin
_zz_CsrPlugin_csrMapping_readDataInit_14[31 : 0] = CsrPlugin_mtval;
end
end
always @(*) begin
_zz_CsrPlugin_csrMapping_readDataInit_15 = 32'h0;
if(execute_CsrPlugin_csr_2816) begin
_zz_CsrPlugin_csrMapping_readDataInit_15[31 : 0] = CsrPlugin_mcycle[31 : 0];
end
end
always @(*) begin
_zz_CsrPlugin_csrMapping_readDataInit_16 = 32'h0;
if(execute_CsrPlugin_csr_2944) begin
_zz_CsrPlugin_csrMapping_readDataInit_16[31 : 0] = CsrPlugin_mcycle[63 : 32];
end
end
always @(*) begin
_zz_CsrPlugin_csrMapping_readDataInit_17 = 32'h0;
if(execute_CsrPlugin_csr_2818) begin
_zz_CsrPlugin_csrMapping_readDataInit_17[31 : 0] = CsrPlugin_minstret[31 : 0];
end
end
always @(*) begin
_zz_CsrPlugin_csrMapping_readDataInit_18 = 32'h0;
if(execute_CsrPlugin_csr_2946) begin
_zz_CsrPlugin_csrMapping_readDataInit_18[31 : 0] = CsrPlugin_minstret[63 : 32];
end
end
always @(*) begin
_zz_CsrPlugin_csrMapping_readDataInit_19 = 32'h0;
if(execute_CsrPlugin_csr_3072) begin
_zz_CsrPlugin_csrMapping_readDataInit_19[31 : 0] = CsrPlugin_mcycle[31 : 0];
end
end
always @(*) begin
_zz_CsrPlugin_csrMapping_readDataInit_20 = 32'h0;
if(execute_CsrPlugin_csr_3200) begin
_zz_CsrPlugin_csrMapping_readDataInit_20[31 : 0] = CsrPlugin_mcycle[63 : 32];
end
end
always @(*) begin
_zz_CsrPlugin_csrMapping_readDataInit_21 = 32'h0;
if(execute_CsrPlugin_csr_3074) begin
_zz_CsrPlugin_csrMapping_readDataInit_21[31 : 0] = CsrPlugin_minstret[31 : 0];
end
end
always @(*) begin
_zz_CsrPlugin_csrMapping_readDataInit_22 = 32'h0;
if(execute_CsrPlugin_csr_3202) begin
_zz_CsrPlugin_csrMapping_readDataInit_22[31 : 0] = CsrPlugin_minstret[63 : 32];
end
end
always @(*) begin
_zz_CsrPlugin_csrMapping_readDataInit_23 = 32'h0;
if(execute_CsrPlugin_csr_3008) begin
_zz_CsrPlugin_csrMapping_readDataInit_23[31 : 0] = _zz_CsrPlugin_csrMapping_readDataInit;
end
end
always @(*) begin
_zz_CsrPlugin_csrMapping_readDataInit_24 = 32'h0;
if(execute_CsrPlugin_csr_4032) begin
_zz_CsrPlugin_csrMapping_readDataInit_24[31 : 0] = _zz_CsrPlugin_csrMapping_readDataInit_1;
end
end
assign CsrPlugin_csrMapping_readDataInit = (((((_zz_CsrPlugin_csrMapping_readDataInit_2 | _zz_CsrPlugin_csrMapping_readDataInit_3) | (_zz_CsrPlugin_csrMapping_readDataInit_4 | _zz_CsrPlugin_csrMapping_readDataInit_5)) | ((_zz_CsrPlugin_csrMapping_readDataInit_25 | _zz_CsrPlugin_csrMapping_readDataInit_6) | (_zz_CsrPlugin_csrMapping_readDataInit_7 | _zz_CsrPlugin_csrMapping_readDataInit_8))) | (((_zz_CsrPlugin_csrMapping_readDataInit_9 | _zz_CsrPlugin_csrMapping_readDataInit_10) | (_zz_CsrPlugin_csrMapping_readDataInit_11 | _zz_CsrPlugin_csrMapping_readDataInit_12)) | ((_zz_CsrPlugin_csrMapping_readDataInit_13 | _zz_CsrPlugin_csrMapping_readDataInit_14) | (_zz_CsrPlugin_csrMapping_readDataInit_15 | _zz_CsrPlugin_csrMapping_readDataInit_16)))) | (((_zz_CsrPlugin_csrMapping_readDataInit_17 | _zz_CsrPlugin_csrMapping_readDataInit_18) | (_zz_CsrPlugin_csrMapping_readDataInit_19 | _zz_CsrPlugin_csrMapping_readDataInit_20)) | ((_zz_CsrPlugin_csrMapping_readDataInit_21 | _zz_CsrPlugin_csrMapping_readDataInit_22) | (_zz_CsrPlugin_csrMapping_readDataInit_23 | _zz_CsrPlugin_csrMapping_readDataInit_24))));
assign when_CsrPlugin_l1297 = (CsrPlugin_privilege < execute_CsrPlugin_csrAddress[9 : 8]);
assign when_CsrPlugin_l1302 = ((! execute_arbitration_isValid) || (! execute_IS_CSR));
assign iBusWishbone_ADR = {_zz_iBusWishbone_ADR_1,_zz_iBusWishbone_ADR};
assign iBusWishbone_CTI = ((_zz_iBusWishbone_ADR == 3'b111) ? 3'b111 : 3'b010);
assign iBusWishbone_BTE = 2'b00;
assign iBusWishbone_SEL = 4'b1111;
assign iBusWishbone_WE = 1'b0;
assign iBusWishbone_DAT_MOSI = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx;
always @(*) begin
iBusWishbone_CYC = 1'b0;
if(when_InstructionCache_l239) begin
iBusWishbone_CYC = 1'b1;
end
end
always @(*) begin
iBusWishbone_STB = 1'b0;
if(when_InstructionCache_l239) begin
iBusWishbone_STB = 1'b1;
end
end
assign when_InstructionCache_l239 = (iBus_cmd_valid || (_zz_iBusWishbone_ADR != 3'b000));
assign iBus_cmd_ready = (iBus_cmd_valid && iBusWishbone_ACK);
assign iBus_rsp_valid = _zz_iBus_rsp_valid;
assign iBus_rsp_payload_data = iBusWishbone_DAT_MISO_regNext;
assign iBus_rsp_payload_error = 1'b0;
assign _zz_dBus_cmd_ready_5 = (dBus_cmd_payload_size == 3'b101);
assign _zz_dBus_cmd_ready_1 = dBus_cmd_valid;
assign _zz_dBus_cmd_ready_3 = dBus_cmd_payload_wr;
assign _zz_dBus_cmd_ready_4 = ((! _zz_dBus_cmd_ready_5) || (_zz_dBus_cmd_ready == 3'b111));
assign dBus_cmd_ready = (_zz_dBus_cmd_ready_2 && (_zz_dBus_cmd_ready_3 || _zz_dBus_cmd_ready_4));
assign dBusWishbone_ADR = ((_zz_dBus_cmd_ready_5 ? {{dBus_cmd_payload_address[31 : 5],_zz_dBus_cmd_ready},2'b00} : {dBus_cmd_payload_address[31 : 2],2'b00}) >>> 2);
assign dBusWishbone_CTI = (_zz_dBus_cmd_ready_5 ? (_zz_dBus_cmd_ready_4 ? 3'b111 : 3'b010) : 3'b000);
assign dBusWishbone_BTE = 2'b00;
assign dBusWishbone_SEL = (_zz_dBus_cmd_ready_3 ? dBus_cmd_payload_mask : 4'b1111);
assign dBusWishbone_WE = _zz_dBus_cmd_ready_3;
assign dBusWishbone_DAT_MOSI = dBus_cmd_payload_data;
assign _zz_dBus_cmd_ready_2 = (_zz_dBus_cmd_ready_1 && dBusWishbone_ACK);
assign dBusWishbone_CYC = _zz_dBus_cmd_ready_1;
assign dBusWishbone_STB = _zz_dBus_cmd_ready_1;
assign dBus_rsp_valid = _zz_dBus_rsp_valid;
assign dBus_rsp_payload_data = dBusWishbone_DAT_MISO_regNext;
assign dBus_rsp_payload_error = 1'b0;
always @(posedge clk) begin
if(reset) begin
IBusCachedPlugin_fetchPc_pcReg <= externalResetVector;
IBusCachedPlugin_fetchPc_correctionReg <= 1'b0;
IBusCachedPlugin_fetchPc_booted <= 1'b0;
IBusCachedPlugin_fetchPc_inc <= 1'b0;
_zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_2 <= 1'b0;
_zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid <= 1'b0;
IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b0;
IBusCachedPlugin_injector_nextPcCalc_valids_1 <= 1'b0;
IBusCachedPlugin_injector_nextPcCalc_valids_2 <= 1'b0;
IBusCachedPlugin_injector_nextPcCalc_valids_3 <= 1'b0;
IBusCachedPlugin_injector_nextPcCalc_valids_4 <= 1'b0;
IBusCachedPlugin_rspCounter <= _zz_IBusCachedPlugin_rspCounter;
IBusCachedPlugin_rspCounter <= 32'h0;
dataCache_1_io_mem_cmd_rValid <= 1'b0;
dataCache_1_io_mem_cmd_s2mPipe_rValid <= 1'b0;
DBusCachedPlugin_rspCounter <= _zz_DBusCachedPlugin_rspCounter;
DBusCachedPlugin_rspCounter <= 32'h0;
_zz_7 <= 1'b1;
HazardSimplePlugin_writeBackBuffer_valid <= 1'b0;
CsrPlugin_misa_base <= 2'b01;
CsrPlugin_misa_extensions <= 26'h0000042;
CsrPlugin_mstatus_MIE <= 1'b0;
CsrPlugin_mstatus_MPIE <= 1'b0;
CsrPlugin_mstatus_MPP <= 2'b11;
CsrPlugin_mie_MEIE <= 1'b0;
CsrPlugin_mie_MTIE <= 1'b0;
CsrPlugin_mie_MSIE <= 1'b0;
CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode <= 1'b0;
CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute <= 1'b0;
CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory <= 1'b0;
CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= 1'b0;
CsrPlugin_interrupt_valid <= 1'b0;
CsrPlugin_lastStageWasWfi <= 1'b0;
CsrPlugin_pipelineLiberator_pcValids_0 <= 1'b0;
CsrPlugin_pipelineLiberator_pcValids_1 <= 1'b0;
CsrPlugin_pipelineLiberator_pcValids_2 <= 1'b0;
CsrPlugin_hadException <= 1'b0;
execute_CsrPlugin_wfiWake <= 1'b0;
memory_DivPlugin_div_counter_value <= 6'h0;
_zz_CsrPlugin_csrMapping_readDataInit <= 32'h0;
execute_CfuPlugin_hold <= 1'b0;
execute_CfuPlugin_fired <= 1'b0;
CfuPlugin_bus_rsp_rValid <= 1'b0;
execute_arbitration_isValid <= 1'b0;
memory_arbitration_isValid <= 1'b0;
writeBack_arbitration_isValid <= 1'b0;
switch_Fetcher_l362 <= 3'b000;
execute_to_memory_CfuPlugin_CFU_IN_FLIGHT <= 1'b0;
_zz_iBusWishbone_ADR <= 3'b000;
_zz_iBus_rsp_valid <= 1'b0;
_zz_dBus_cmd_ready <= 3'b000;
_zz_dBus_rsp_valid <= 1'b0;
end else begin
if(IBusCachedPlugin_fetchPc_correction) begin
IBusCachedPlugin_fetchPc_correctionReg <= 1'b1;
end
if(IBusCachedPlugin_fetchPc_output_fire) begin
IBusCachedPlugin_fetchPc_correctionReg <= 1'b0;
end
IBusCachedPlugin_fetchPc_booted <= 1'b1;
if(when_Fetcher_l131) begin
IBusCachedPlugin_fetchPc_inc <= 1'b0;
end
if(IBusCachedPlugin_fetchPc_output_fire_1) begin
IBusCachedPlugin_fetchPc_inc <= 1'b1;
end
if(when_Fetcher_l131_1) begin
IBusCachedPlugin_fetchPc_inc <= 1'b0;
end
if(when_Fetcher_l158) begin
IBusCachedPlugin_fetchPc_pcReg <= IBusCachedPlugin_fetchPc_pc;
end
if(IBusCachedPlugin_iBusRsp_flush) begin
_zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_2 <= 1'b0;
end
if(_zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready) begin
_zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_2 <= (IBusCachedPlugin_iBusRsp_stages_0_output_valid && (! 1'b0));
end
if(IBusCachedPlugin_iBusRsp_flush) begin
_zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid <= 1'b0;
end
if(IBusCachedPlugin_iBusRsp_stages_1_output_ready) begin
_zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid <= (IBusCachedPlugin_iBusRsp_stages_1_output_valid && (! IBusCachedPlugin_iBusRsp_flush));
end
if(IBusCachedPlugin_fetchPc_flushed) begin
IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b0;
end
if(when_Fetcher_l329) begin
IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b1;
end
if(IBusCachedPlugin_fetchPc_flushed) begin
IBusCachedPlugin_injector_nextPcCalc_valids_1 <= 1'b0;
end
if(when_Fetcher_l329_1) begin
IBusCachedPlugin_injector_nextPcCalc_valids_1 <= IBusCachedPlugin_injector_nextPcCalc_valids_0;
end
if(IBusCachedPlugin_fetchPc_flushed) begin
IBusCachedPlugin_injector_nextPcCalc_valids_1 <= 1'b0;
end
if(IBusCachedPlugin_fetchPc_flushed) begin
IBusCachedPlugin_injector_nextPcCalc_valids_2 <= 1'b0;
end
if(when_Fetcher_l329_2) begin
IBusCachedPlugin_injector_nextPcCalc_valids_2 <= IBusCachedPlugin_injector_nextPcCalc_valids_1;
end
if(IBusCachedPlugin_fetchPc_flushed) begin
IBusCachedPlugin_injector_nextPcCalc_valids_2 <= 1'b0;
end
if(IBusCachedPlugin_fetchPc_flushed) begin
IBusCachedPlugin_injector_nextPcCalc_valids_3 <= 1'b0;
end
if(when_Fetcher_l329_3) begin
IBusCachedPlugin_injector_nextPcCalc_valids_3 <= IBusCachedPlugin_injector_nextPcCalc_valids_2;
end
if(IBusCachedPlugin_fetchPc_flushed) begin
IBusCachedPlugin_injector_nextPcCalc_valids_3 <= 1'b0;
end
if(IBusCachedPlugin_fetchPc_flushed) begin
IBusCachedPlugin_injector_nextPcCalc_valids_4 <= 1'b0;
end
if(when_Fetcher_l329_4) begin
IBusCachedPlugin_injector_nextPcCalc_valids_4 <= IBusCachedPlugin_injector_nextPcCalc_valids_3;
end
if(IBusCachedPlugin_fetchPc_flushed) begin
IBusCachedPlugin_injector_nextPcCalc_valids_4 <= 1'b0;
end
if(iBus_rsp_valid) begin
IBusCachedPlugin_rspCounter <= (IBusCachedPlugin_rspCounter + 32'h00000001);
end
if(dataCache_1_io_mem_cmd_valid) begin
dataCache_1_io_mem_cmd_rValid <= 1'b1;
end
if(dataCache_1_io_mem_cmd_s2mPipe_ready) begin
dataCache_1_io_mem_cmd_rValid <= 1'b0;
end
if(dataCache_1_io_mem_cmd_s2mPipe_ready) begin
dataCache_1_io_mem_cmd_s2mPipe_rValid <= dataCache_1_io_mem_cmd_s2mPipe_valid;
end
if(dBus_rsp_valid) begin
DBusCachedPlugin_rspCounter <= (DBusCachedPlugin_rspCounter + 32'h00000001);
end
_zz_7 <= 1'b0;
HazardSimplePlugin_writeBackBuffer_valid <= HazardSimplePlugin_writeBackWrites_valid;
if(when_CsrPlugin_l909) begin
CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode <= 1'b0;
end else begin
CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode <= CsrPlugin_exceptionPortCtrl_exceptionValids_decode;
end
if(when_CsrPlugin_l909_1) begin
CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute <= (CsrPlugin_exceptionPortCtrl_exceptionValids_decode && (! decode_arbitration_isStuck));
end else begin
CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute <= CsrPlugin_exceptionPortCtrl_exceptionValids_execute;
end
if(when_CsrPlugin_l909_2) begin
CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory <= (CsrPlugin_exceptionPortCtrl_exceptionValids_execute && (! execute_arbitration_isStuck));
end else begin
CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory <= CsrPlugin_exceptionPortCtrl_exceptionValids_memory;
end
if(when_CsrPlugin_l909_3) begin
CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= (CsrPlugin_exceptionPortCtrl_exceptionValids_memory && (! memory_arbitration_isStuck));
end else begin
CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= 1'b0;
end
CsrPlugin_interrupt_valid <= 1'b0;
if(when_CsrPlugin_l946) begin
if(when_CsrPlugin_l952) begin
CsrPlugin_interrupt_valid <= 1'b1;
end
if(when_CsrPlugin_l952_1) begin
CsrPlugin_interrupt_valid <= 1'b1;
end
if(when_CsrPlugin_l952_2) begin
CsrPlugin_interrupt_valid <= 1'b1;
end
end
CsrPlugin_lastStageWasWfi <= (writeBack_arbitration_isFiring && (writeBack_ENV_CTRL == `EnvCtrlEnum_binary_sequential_WFI));
if(CsrPlugin_pipelineLiberator_active) begin
if(when_CsrPlugin_l980) begin
CsrPlugin_pipelineLiberator_pcValids_0 <= 1'b1;
end
if(when_CsrPlugin_l980_1) begin
CsrPlugin_pipelineLiberator_pcValids_1 <= CsrPlugin_pipelineLiberator_pcValids_0;
end
if(when_CsrPlugin_l980_2) begin
CsrPlugin_pipelineLiberator_pcValids_2 <= CsrPlugin_pipelineLiberator_pcValids_1;
end
end
if(when_CsrPlugin_l985) begin
CsrPlugin_pipelineLiberator_pcValids_0 <= 1'b0;
CsrPlugin_pipelineLiberator_pcValids_1 <= 1'b0;
CsrPlugin_pipelineLiberator_pcValids_2 <= 1'b0;
end
if(CsrPlugin_interruptJump) begin
CsrPlugin_interrupt_valid <= 1'b0;
end
CsrPlugin_hadException <= CsrPlugin_exception;
if(when_CsrPlugin_l1019) begin
case(CsrPlugin_targetPrivilege)
2'b11 : begin
CsrPlugin_mstatus_MIE <= 1'b0;
CsrPlugin_mstatus_MPIE <= CsrPlugin_mstatus_MIE;
CsrPlugin_mstatus_MPP <= CsrPlugin_privilege;
end
default : begin
end
endcase
end
if(when_CsrPlugin_l1064) begin
case(switch_CsrPlugin_l1068)
2'b11 : begin
CsrPlugin_mstatus_MPP <= 2'b00;
CsrPlugin_mstatus_MIE <= CsrPlugin_mstatus_MPIE;
CsrPlugin_mstatus_MPIE <= 1'b1;
end
default : begin
end
endcase
end
execute_CsrPlugin_wfiWake <= (({_zz_when_CsrPlugin_l952_2,{_zz_when_CsrPlugin_l952_1,_zz_when_CsrPlugin_l952}} != 3'b000) || CsrPlugin_thirdPartyWake);
memory_DivPlugin_div_counter_value <= memory_DivPlugin_div_counter_valueNext;
if(execute_CfuPlugin_schedule) begin
execute_CfuPlugin_hold <= 1'b1;
end
if(CfuPlugin_bus_cmd_ready) begin
execute_CfuPlugin_hold <= 1'b0;
end
if(CfuPlugin_bus_cmd_fire) begin
execute_CfuPlugin_fired <= 1'b1;
end
if(when_CfuPlugin_l171) begin
execute_CfuPlugin_fired <= 1'b0;
end
if(CfuPlugin_bus_rsp_valid) begin
CfuPlugin_bus_rsp_rValid <= 1'b1;
end
if(CfuPlugin_bus_rsp_rsp_ready) begin
CfuPlugin_bus_rsp_rValid <= 1'b0;
end
if(when_Pipeline_l124_62) begin
execute_to_memory_CfuPlugin_CFU_IN_FLIGHT <= _zz_execute_to_memory_CfuPlugin_CFU_IN_FLIGHT;
end
if(when_Pipeline_l151) begin
execute_arbitration_isValid <= 1'b0;
end
if(when_Pipeline_l154) begin
execute_arbitration_isValid <= decode_arbitration_isValid;
end
if(when_Pipeline_l151_1) begin
memory_arbitration_isValid <= 1'b0;
end
if(when_Pipeline_l154_1) begin
memory_arbitration_isValid <= execute_arbitration_isValid;
end
if(when_Pipeline_l151_2) begin
writeBack_arbitration_isValid <= 1'b0;
end
if(when_Pipeline_l154_2) begin
writeBack_arbitration_isValid <= memory_arbitration_isValid;
end
case(switch_Fetcher_l362)
3'b000 : begin
if(IBusCachedPlugin_injectionPort_valid) begin
switch_Fetcher_l362 <= 3'b001;
end
end
3'b001 : begin
switch_Fetcher_l362 <= 3'b010;
end
3'b010 : begin
switch_Fetcher_l362 <= 3'b011;
end
3'b011 : begin
if(when_Fetcher_l378) begin
switch_Fetcher_l362 <= 3'b100;
end
end
3'b100 : begin
switch_Fetcher_l362 <= 3'b000;
end
default : begin
end
endcase
if(execute_CsrPlugin_csr_769) begin
if(execute_CsrPlugin_writeEnable) begin
CsrPlugin_misa_base <= CsrPlugin_csrMapping_writeDataSignal[31 : 30];
CsrPlugin_misa_extensions <= CsrPlugin_csrMapping_writeDataSignal[25 : 0];
end
end
if(execute_CsrPlugin_csr_768) begin
if(execute_CsrPlugin_writeEnable) begin
CsrPlugin_mstatus_MPP <= CsrPlugin_csrMapping_writeDataSignal[12 : 11];
CsrPlugin_mstatus_MPIE <= CsrPlugin_csrMapping_writeDataSignal[7];
CsrPlugin_mstatus_MIE <= CsrPlugin_csrMapping_writeDataSignal[3];
end
end
if(execute_CsrPlugin_csr_772) begin
if(execute_CsrPlugin_writeEnable) begin
CsrPlugin_mie_MEIE <= CsrPlugin_csrMapping_writeDataSignal[11];
CsrPlugin_mie_MTIE <= CsrPlugin_csrMapping_writeDataSignal[7];
CsrPlugin_mie_MSIE <= CsrPlugin_csrMapping_writeDataSignal[3];
end
end
if(execute_CsrPlugin_csr_3008) begin
if(execute_CsrPlugin_writeEnable) begin
_zz_CsrPlugin_csrMapping_readDataInit <= CsrPlugin_csrMapping_writeDataSignal[31 : 0];
end
end
if(when_InstructionCache_l239) begin
if(iBusWishbone_ACK) begin
_zz_iBusWishbone_ADR <= (_zz_iBusWishbone_ADR + 3'b001);
end
end
_zz_iBus_rsp_valid <= (iBusWishbone_CYC && iBusWishbone_ACK);
if((_zz_dBus_cmd_ready_1 && _zz_dBus_cmd_ready_2)) begin
_zz_dBus_cmd_ready <= (_zz_dBus_cmd_ready + 3'b001);
if(_zz_dBus_cmd_ready_4) begin
_zz_dBus_cmd_ready <= 3'b000;
end
end
_zz_dBus_rsp_valid <= ((_zz_dBus_cmd_ready_1 && (! dBusWishbone_WE)) && dBusWishbone_ACK);
end
end
always @(posedge clk) begin
if(IBusCachedPlugin_iBusRsp_stages_1_output_ready) begin
_zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_payload <= IBusCachedPlugin_iBusRsp_stages_1_output_payload;
end
if(IBusCachedPlugin_iBusRsp_stages_1_input_ready) begin
IBusCachedPlugin_s1_tightlyCoupledHit <= IBusCachedPlugin_s0_tightlyCoupledHit;
end
if(IBusCachedPlugin_iBusRsp_stages_2_input_ready) begin
IBusCachedPlugin_s2_tightlyCoupledHit <= IBusCachedPlugin_s1_tightlyCoupledHit;
end
if(dataCache_1_io_mem_cmd_ready) begin
dataCache_1_io_mem_cmd_rData_wr <= dataCache_1_io_mem_cmd_payload_wr;
dataCache_1_io_mem_cmd_rData_uncached <= dataCache_1_io_mem_cmd_payload_uncached;
dataCache_1_io_mem_cmd_rData_address <= dataCache_1_io_mem_cmd_payload_address;
dataCache_1_io_mem_cmd_rData_data <= dataCache_1_io_mem_cmd_payload_data;
dataCache_1_io_mem_cmd_rData_mask <= dataCache_1_io_mem_cmd_payload_mask;
dataCache_1_io_mem_cmd_rData_size <= dataCache_1_io_mem_cmd_payload_size;
dataCache_1_io_mem_cmd_rData_last <= dataCache_1_io_mem_cmd_payload_last;
end
if(dataCache_1_io_mem_cmd_s2mPipe_ready) begin
dataCache_1_io_mem_cmd_s2mPipe_rData_wr <= dataCache_1_io_mem_cmd_s2mPipe_payload_wr;
dataCache_1_io_mem_cmd_s2mPipe_rData_uncached <= dataCache_1_io_mem_cmd_s2mPipe_payload_uncached;
dataCache_1_io_mem_cmd_s2mPipe_rData_address <= dataCache_1_io_mem_cmd_s2mPipe_payload_address;
dataCache_1_io_mem_cmd_s2mPipe_rData_data <= dataCache_1_io_mem_cmd_s2mPipe_payload_data;
dataCache_1_io_mem_cmd_s2mPipe_rData_mask <= dataCache_1_io_mem_cmd_s2mPipe_payload_mask;
dataCache_1_io_mem_cmd_s2mPipe_rData_size <= dataCache_1_io_mem_cmd_s2mPipe_payload_size;
dataCache_1_io_mem_cmd_s2mPipe_rData_last <= dataCache_1_io_mem_cmd_s2mPipe_payload_last;
end
HazardSimplePlugin_writeBackBuffer_payload_address <= HazardSimplePlugin_writeBackWrites_payload_address;
HazardSimplePlugin_writeBackBuffer_payload_data <= HazardSimplePlugin_writeBackWrites_payload_data;
CsrPlugin_mip_MEIP <= externalInterrupt;
CsrPlugin_mip_MTIP <= timerInterrupt;
CsrPlugin_mip_MSIP <= softwareInterrupt;
CsrPlugin_mcycle <= (CsrPlugin_mcycle + 64'h0000000000000001);
if(writeBack_arbitration_isFiring) begin
CsrPlugin_minstret <= (CsrPlugin_minstret + 64'h0000000000000001);
end
if(_zz_when) begin
CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1 ? IBusCachedPlugin_decodeExceptionPort_payload_code : decodeExceptionPort_payload_code);
CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1 ? IBusCachedPlugin_decodeExceptionPort_payload_badAddr : decodeExceptionPort_payload_badAddr);
end
if(_zz_when_1) begin
CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_3 ? BranchPlugin_branchExceptionPort_payload_code : CsrPlugin_selfException_payload_code);
CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_3 ? BranchPlugin_branchExceptionPort_payload_badAddr : CsrPlugin_selfException_payload_badAddr);
end
if(DBusCachedPlugin_exceptionBus_valid) begin
CsrPlugin_exceptionPortCtrl_exceptionContext_code <= DBusCachedPlugin_exceptionBus_payload_code;
CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= DBusCachedPlugin_exceptionBus_payload_badAddr;
end
if(when_CsrPlugin_l946) begin
if(when_CsrPlugin_l952) begin
CsrPlugin_interrupt_code <= 4'b0111;
CsrPlugin_interrupt_targetPrivilege <= 2'b11;
end
if(when_CsrPlugin_l952_1) begin
CsrPlugin_interrupt_code <= 4'b0011;
CsrPlugin_interrupt_targetPrivilege <= 2'b11;
end
if(when_CsrPlugin_l952_2) begin
CsrPlugin_interrupt_code <= 4'b1011;
CsrPlugin_interrupt_targetPrivilege <= 2'b11;
end
end
if(when_CsrPlugin_l1019) begin
case(CsrPlugin_targetPrivilege)
2'b11 : begin
CsrPlugin_mcause_interrupt <= (! CsrPlugin_hadException);
CsrPlugin_mcause_exceptionCode <= CsrPlugin_trapCause;
CsrPlugin_mepc <= writeBack_PC;
if(CsrPlugin_hadException) begin
CsrPlugin_mtval <= CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr;
end
end
default : begin
end
endcase
end
if(when_MulDivIterativePlugin_l126) begin
memory_DivPlugin_div_done <= 1'b1;
end
if(when_MulDivIterativePlugin_l126_1) begin
memory_DivPlugin_div_done <= 1'b0;
end
if(when_MulDivIterativePlugin_l128) begin
if(when_MulDivIterativePlugin_l132) begin
memory_DivPlugin_rs1[31 : 0] <= memory_DivPlugin_div_stage_0_outNumerator;
memory_DivPlugin_accumulator[31 : 0] <= memory_DivPlugin_div_stage_0_outRemainder;
if(when_MulDivIterativePlugin_l151) begin
memory_DivPlugin_div_result <= _zz_memory_DivPlugin_div_result_1[31:0];
end
end
end
if(when_MulDivIterativePlugin_l162) begin
memory_DivPlugin_accumulator <= 65'h0;
memory_DivPlugin_rs1 <= ((_zz_memory_DivPlugin_rs1 ? (~ _zz_memory_DivPlugin_rs1_1) : _zz_memory_DivPlugin_rs1_1) + _zz_memory_DivPlugin_rs1_2);
memory_DivPlugin_rs2 <= ((_zz_memory_DivPlugin_rs2 ? (~ execute_RS2) : execute_RS2) + _zz_memory_DivPlugin_rs2_1);
memory_DivPlugin_div_needRevert <= ((_zz_memory_DivPlugin_rs1 ^ (_zz_memory_DivPlugin_rs2 && (! execute_INSTRUCTION[13]))) && (! (((execute_RS2 == 32'h0) && execute_IS_RS2_SIGNED) && (! execute_INSTRUCTION[13]))));
end
externalInterruptArray_regNext <= externalInterruptArray;
if(CfuPlugin_bus_rsp_ready) begin
CfuPlugin_bus_rsp_rData_outputs_0 <= CfuPlugin_bus_rsp_payload_outputs_0;
end
if(when_Pipeline_l124) begin
decode_to_execute_PC <= decode_PC;
end
if(when_Pipeline_l124_1) begin
execute_to_memory_PC <= _zz_execute_SRC2;
end
if(when_Pipeline_l124_2) begin
memory_to_writeBack_PC <= memory_PC;
end
if(when_Pipeline_l124_3) begin
decode_to_execute_INSTRUCTION <= decode_INSTRUCTION;
end
if(when_Pipeline_l124_4) begin
execute_to_memory_INSTRUCTION <= execute_INSTRUCTION;
end
if(when_Pipeline_l124_5) begin
memory_to_writeBack_INSTRUCTION <= memory_INSTRUCTION;
end
if(when_Pipeline_l124_6) begin
decode_to_execute_FORMAL_PC_NEXT <= _zz_decode_to_execute_FORMAL_PC_NEXT;
end
if(when_Pipeline_l124_7) begin
execute_to_memory_FORMAL_PC_NEXT <= _zz_execute_to_memory_FORMAL_PC_NEXT;
end
if(when_Pipeline_l124_8) begin
memory_to_writeBack_FORMAL_PC_NEXT <= memory_FORMAL_PC_NEXT;
end
if(when_Pipeline_l124_9) begin
decode_to_execute_MEMORY_FORCE_CONSTISTENCY <= decode_MEMORY_FORCE_CONSTISTENCY;
end
if(when_Pipeline_l124_10) begin
decode_to_execute_SRC1_CTRL <= _zz_decode_to_execute_SRC1_CTRL;
end
if(when_Pipeline_l124_11) begin
decode_to_execute_SRC_USE_SUB_LESS <= decode_SRC_USE_SUB_LESS;
end
if(when_Pipeline_l124_12) begin
decode_to_execute_MEMORY_ENABLE <= decode_MEMORY_ENABLE;
end
if(when_Pipeline_l124_13) begin
execute_to_memory_MEMORY_ENABLE <= execute_MEMORY_ENABLE;
end
if(when_Pipeline_l124_14) begin
memory_to_writeBack_MEMORY_ENABLE <= memory_MEMORY_ENABLE;
end
if(when_Pipeline_l124_15) begin
decode_to_execute_ALU_CTRL <= _zz_decode_to_execute_ALU_CTRL;
end
if(when_Pipeline_l124_16) begin
decode_to_execute_SRC2_CTRL <= _zz_decode_to_execute_SRC2_CTRL;
end
if(when_Pipeline_l124_17) begin
decode_to_execute_REGFILE_WRITE_VALID <= decode_REGFILE_WRITE_VALID;
end
if(when_Pipeline_l124_18) begin
execute_to_memory_REGFILE_WRITE_VALID <= execute_REGFILE_WRITE_VALID;
end
if(when_Pipeline_l124_19) begin
memory_to_writeBack_REGFILE_WRITE_VALID <= memory_REGFILE_WRITE_VALID;
end
if(when_Pipeline_l124_20) begin
decode_to_execute_BYPASSABLE_EXECUTE_STAGE <= decode_BYPASSABLE_EXECUTE_STAGE;
end
if(when_Pipeline_l124_21) begin
decode_to_execute_BYPASSABLE_MEMORY_STAGE <= decode_BYPASSABLE_MEMORY_STAGE;
end
if(when_Pipeline_l124_22) begin
execute_to_memory_BYPASSABLE_MEMORY_STAGE <= execute_BYPASSABLE_MEMORY_STAGE;
end
if(when_Pipeline_l124_23) begin
decode_to_execute_MEMORY_WR <= decode_MEMORY_WR;
end
if(when_Pipeline_l124_24) begin
execute_to_memory_MEMORY_WR <= execute_MEMORY_WR;
end
if(when_Pipeline_l124_25) begin
memory_to_writeBack_MEMORY_WR <= memory_MEMORY_WR;
end
if(when_Pipeline_l124_26) begin
decode_to_execute_MEMORY_MANAGMENT <= decode_MEMORY_MANAGMENT;
end
if(when_Pipeline_l124_27) begin
decode_to_execute_SRC_LESS_UNSIGNED <= decode_SRC_LESS_UNSIGNED;
end
if(when_Pipeline_l124_28) begin
decode_to_execute_ALU_BITWISE_CTRL <= _zz_decode_to_execute_ALU_BITWISE_CTRL;
end
if(when_Pipeline_l124_29) begin
decode_to_execute_SHIFT_CTRL <= _zz_decode_to_execute_SHIFT_CTRL;
end
if(when_Pipeline_l124_30) begin
execute_to_memory_SHIFT_CTRL <= _zz_execute_to_memory_SHIFT_CTRL;
end
if(when_Pipeline_l124_31) begin
decode_to_execute_BRANCH_CTRL <= _zz_decode_to_execute_BRANCH_CTRL;
end
if(when_Pipeline_l124_32) begin
decode_to_execute_IS_CSR <= decode_IS_CSR;
end
if(when_Pipeline_l124_33) begin
decode_to_execute_ENV_CTRL <= _zz_decode_to_execute_ENV_CTRL;
end
if(when_Pipeline_l124_34) begin
execute_to_memory_ENV_CTRL <= _zz_execute_to_memory_ENV_CTRL;
end
if(when_Pipeline_l124_35) begin
memory_to_writeBack_ENV_CTRL <= _zz_memory_to_writeBack_ENV_CTRL;
end
if(when_Pipeline_l124_36) begin
decode_to_execute_IS_MUL <= decode_IS_MUL;
end
if(when_Pipeline_l124_37) begin
execute_to_memory_IS_MUL <= execute_IS_MUL;
end
if(when_Pipeline_l124_38) begin
memory_to_writeBack_IS_MUL <= memory_IS_MUL;
end
if(when_Pipeline_l124_39) begin
decode_to_execute_IS_DIV <= decode_IS_DIV;
end
if(when_Pipeline_l124_40) begin
execute_to_memory_IS_DIV <= execute_IS_DIV;
end
if(when_Pipeline_l124_41) begin
decode_to_execute_IS_RS1_SIGNED <= decode_IS_RS1_SIGNED;
end
if(when_Pipeline_l124_42) begin
decode_to_execute_IS_RS2_SIGNED <= decode_IS_RS2_SIGNED;
end
if(when_Pipeline_l124_43) begin
decode_to_execute_CfuPlugin_CFU_ENABLE <= decode_CfuPlugin_CFU_ENABLE;
end
if(when_Pipeline_l124_44) begin
decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND <= _zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND;
end
if(when_Pipeline_l124_45) begin
decode_to_execute_RS1 <= decode_RS1;
end
if(when_Pipeline_l124_46) begin
decode_to_execute_RS2 <= decode_RS2;
end
if(when_Pipeline_l124_47) begin
decode_to_execute_SRC2_FORCE_ZERO <= decode_SRC2_FORCE_ZERO;
end
if(when_Pipeline_l124_48) begin
decode_to_execute_PREDICTION_HAD_BRANCHED2 <= decode_PREDICTION_HAD_BRANCHED2;
end
if(when_Pipeline_l124_49) begin
decode_to_execute_CSR_WRITE_OPCODE <= decode_CSR_WRITE_OPCODE;
end
if(when_Pipeline_l124_50) begin
decode_to_execute_CSR_READ_OPCODE <= decode_CSR_READ_OPCODE;
end
if(when_Pipeline_l124_51) begin
decode_to_execute_DO_EBREAK <= decode_DO_EBREAK;
end
if(when_Pipeline_l124_52) begin
execute_to_memory_MEMORY_STORE_DATA_RF <= execute_MEMORY_STORE_DATA_RF;
end
if(when_Pipeline_l124_53) begin
memory_to_writeBack_MEMORY_STORE_DATA_RF <= memory_MEMORY_STORE_DATA_RF;
end
if(when_Pipeline_l124_54) begin
execute_to_memory_REGFILE_WRITE_DATA <= _zz_decode_RS2;
end
if(when_Pipeline_l124_55) begin
memory_to_writeBack_REGFILE_WRITE_DATA <= _zz_decode_RS2_1;
end
if(when_Pipeline_l124_56) begin
execute_to_memory_SHIFT_RIGHT <= execute_SHIFT_RIGHT;
end
if(when_Pipeline_l124_57) begin
execute_to_memory_MUL_LL <= execute_MUL_LL;
end
if(when_Pipeline_l124_58) begin
execute_to_memory_MUL_LH <= execute_MUL_LH;
end
if(when_Pipeline_l124_59) begin
execute_to_memory_MUL_HL <= execute_MUL_HL;
end
if(when_Pipeline_l124_60) begin
execute_to_memory_MUL_HH <= execute_MUL_HH;
end
if(when_Pipeline_l124_61) begin
memory_to_writeBack_MUL_HH <= memory_MUL_HH;
end
if(when_Pipeline_l124_63) begin
memory_to_writeBack_CfuPlugin_CFU_IN_FLIGHT <= _zz_memory_to_writeBack_CfuPlugin_CFU_IN_FLIGHT;
end
if(when_Pipeline_l124_64) begin
memory_to_writeBack_MUL_LOW <= memory_MUL_LOW;
end
if(when_CsrPlugin_l1264) begin
execute_CsrPlugin_csr_3264 <= (decode_INSTRUCTION[31 : 20] == 12'hcc0);
end
if(when_CsrPlugin_l1264_1) begin
execute_CsrPlugin_csr_3857 <= (decode_INSTRUCTION[31 : 20] == 12'hf11);
end
if(when_CsrPlugin_l1264_2) begin
execute_CsrPlugin_csr_3858 <= (decode_INSTRUCTION[31 : 20] == 12'hf12);
end
if(when_CsrPlugin_l1264_3) begin
execute_CsrPlugin_csr_3859 <= (decode_INSTRUCTION[31 : 20] == 12'hf13);
end
if(when_CsrPlugin_l1264_4) begin
execute_CsrPlugin_csr_3860 <= (decode_INSTRUCTION[31 : 20] == 12'hf14);
end
if(when_CsrPlugin_l1264_5) begin
execute_CsrPlugin_csr_769 <= (decode_INSTRUCTION[31 : 20] == 12'h301);
end
if(when_CsrPlugin_l1264_6) begin
execute_CsrPlugin_csr_768 <= (decode_INSTRUCTION[31 : 20] == 12'h300);
end
if(when_CsrPlugin_l1264_7) begin
execute_CsrPlugin_csr_836 <= (decode_INSTRUCTION[31 : 20] == 12'h344);
end
if(when_CsrPlugin_l1264_8) begin
execute_CsrPlugin_csr_772 <= (decode_INSTRUCTION[31 : 20] == 12'h304);
end
if(when_CsrPlugin_l1264_9) begin
execute_CsrPlugin_csr_773 <= (decode_INSTRUCTION[31 : 20] == 12'h305);
end
if(when_CsrPlugin_l1264_10) begin
execute_CsrPlugin_csr_833 <= (decode_INSTRUCTION[31 : 20] == 12'h341);
end
if(when_CsrPlugin_l1264_11) begin
execute_CsrPlugin_csr_832 <= (decode_INSTRUCTION[31 : 20] == 12'h340);
end
if(when_CsrPlugin_l1264_12) begin
execute_CsrPlugin_csr_834 <= (decode_INSTRUCTION[31 : 20] == 12'h342);
end
if(when_CsrPlugin_l1264_13) begin
execute_CsrPlugin_csr_835 <= (decode_INSTRUCTION[31 : 20] == 12'h343);
end
if(when_CsrPlugin_l1264_14) begin
execute_CsrPlugin_csr_2816 <= (decode_INSTRUCTION[31 : 20] == 12'hb00);
end
if(when_CsrPlugin_l1264_15) begin
execute_CsrPlugin_csr_2944 <= (decode_INSTRUCTION[31 : 20] == 12'hb80);
end
if(when_CsrPlugin_l1264_16) begin
execute_CsrPlugin_csr_2818 <= (decode_INSTRUCTION[31 : 20] == 12'hb02);
end
if(when_CsrPlugin_l1264_17) begin
execute_CsrPlugin_csr_2946 <= (decode_INSTRUCTION[31 : 20] == 12'hb82);
end
if(when_CsrPlugin_l1264_18) begin
execute_CsrPlugin_csr_3072 <= (decode_INSTRUCTION[31 : 20] == 12'hc00);
end
if(when_CsrPlugin_l1264_19) begin
execute_CsrPlugin_csr_3200 <= (decode_INSTRUCTION[31 : 20] == 12'hc80);
end
if(when_CsrPlugin_l1264_20) begin
execute_CsrPlugin_csr_3074 <= (decode_INSTRUCTION[31 : 20] == 12'hc02);
end
if(when_CsrPlugin_l1264_21) begin
execute_CsrPlugin_csr_3202 <= (decode_INSTRUCTION[31 : 20] == 12'hc82);
end
if(when_CsrPlugin_l1264_22) begin
execute_CsrPlugin_csr_3008 <= (decode_INSTRUCTION[31 : 20] == 12'hbc0);
end
if(when_CsrPlugin_l1264_23) begin
execute_CsrPlugin_csr_4032 <= (decode_INSTRUCTION[31 : 20] == 12'hfc0);
end
if(execute_CsrPlugin_csr_836) begin
if(execute_CsrPlugin_writeEnable) begin
CsrPlugin_mip_MSIP <= CsrPlugin_csrMapping_writeDataSignal[3];
end
end
if(execute_CsrPlugin_csr_773) begin
if(execute_CsrPlugin_writeEnable) begin
CsrPlugin_mtvec_base <= CsrPlugin_csrMapping_writeDataSignal[31 : 2];
CsrPlugin_mtvec_mode <= CsrPlugin_csrMapping_writeDataSignal[1 : 0];
end
end
if(execute_CsrPlugin_csr_833) begin
if(execute_CsrPlugin_writeEnable) begin
CsrPlugin_mepc <= CsrPlugin_csrMapping_writeDataSignal[31 : 0];
end
end
if(execute_CsrPlugin_csr_832) begin
if(execute_CsrPlugin_writeEnable) begin
CsrPlugin_mscratch <= CsrPlugin_csrMapping_writeDataSignal[31 : 0];
end
end
if(execute_CsrPlugin_csr_834) begin
if(execute_CsrPlugin_writeEnable) begin
CsrPlugin_mcause_interrupt <= CsrPlugin_csrMapping_writeDataSignal[31];
CsrPlugin_mcause_exceptionCode <= CsrPlugin_csrMapping_writeDataSignal[3 : 0];
end
end
if(execute_CsrPlugin_csr_835) begin
if(execute_CsrPlugin_writeEnable) begin
CsrPlugin_mtval <= CsrPlugin_csrMapping_writeDataSignal[31 : 0];
end
end
if(execute_CsrPlugin_csr_2816) begin
if(execute_CsrPlugin_writeEnable) begin
CsrPlugin_mcycle[31 : 0] <= CsrPlugin_csrMapping_writeDataSignal[31 : 0];
end
end
if(execute_CsrPlugin_csr_2944) begin
if(execute_CsrPlugin_writeEnable) begin
CsrPlugin_mcycle[63 : 32] <= CsrPlugin_csrMapping_writeDataSignal[31 : 0];
end
end
if(execute_CsrPlugin_csr_2818) begin
if(execute_CsrPlugin_writeEnable) begin
CsrPlugin_minstret[31 : 0] <= CsrPlugin_csrMapping_writeDataSignal[31 : 0];
end
end
if(execute_CsrPlugin_csr_2946) begin
if(execute_CsrPlugin_writeEnable) begin
CsrPlugin_minstret[63 : 32] <= CsrPlugin_csrMapping_writeDataSignal[31 : 0];
end
end
iBusWishbone_DAT_MISO_regNext <= iBusWishbone_DAT_MISO;
dBusWishbone_DAT_MISO_regNext <= dBusWishbone_DAT_MISO;
end
always @(posedge clk) begin
DebugPlugin_firstCycle <= 1'b0;
if(debug_bus_cmd_ready) begin
DebugPlugin_firstCycle <= 1'b1;
end
DebugPlugin_secondCycle <= DebugPlugin_firstCycle;
DebugPlugin_isPipBusy <= (({writeBack_arbitration_isValid,{memory_arbitration_isValid,{execute_arbitration_isValid,decode_arbitration_isValid}}} != 4'b0000) || IBusCachedPlugin_incomingInstruction);
if(writeBack_arbitration_isValid) begin
DebugPlugin_busReadDataReg <= _zz_decode_RS2_2;
end
_zz_when_DebugPlugin_l244 <= debug_bus_cmd_payload_address[2];
if(when_DebugPlugin_l284) begin
DebugPlugin_busReadDataReg <= execute_PC;
end
DebugPlugin_resetIt_regNext <= DebugPlugin_resetIt;
end
always @(posedge clk) begin
if(debugReset) begin
DebugPlugin_resetIt <= 1'b0;
DebugPlugin_haltIt <= 1'b0;
DebugPlugin_stepIt <= 1'b0;
DebugPlugin_godmode <= 1'b0;
DebugPlugin_haltedByBreak <= 1'b0;
DebugPlugin_debugUsed <= 1'b0;
DebugPlugin_disableEbreak <= 1'b0;
end else begin
if(when_DebugPlugin_l225) begin
DebugPlugin_godmode <= 1'b1;
end
if(debug_bus_cmd_valid) begin
DebugPlugin_debugUsed <= 1'b1;
end
if(debug_bus_cmd_valid) begin
case(switch_DebugPlugin_l256)
6'h0 : begin
if(debug_bus_cmd_payload_wr) begin
DebugPlugin_stepIt <= debug_bus_cmd_payload_data[4];
if(when_DebugPlugin_l260) begin
DebugPlugin_resetIt <= 1'b1;
end
if(when_DebugPlugin_l260_1) begin
DebugPlugin_resetIt <= 1'b0;
end
if(when_DebugPlugin_l261) begin
DebugPlugin_haltIt <= 1'b1;
end
if(when_DebugPlugin_l261_1) begin
DebugPlugin_haltIt <= 1'b0;
end
if(when_DebugPlugin_l262) begin
DebugPlugin_haltedByBreak <= 1'b0;
end
if(when_DebugPlugin_l263) begin
DebugPlugin_godmode <= 1'b0;
end
if(when_DebugPlugin_l264) begin
DebugPlugin_disableEbreak <= 1'b1;
end
if(when_DebugPlugin_l264_1) begin
DebugPlugin_disableEbreak <= 1'b0;
end
end
end
default : begin
end
endcase
end
if(when_DebugPlugin_l284) begin
if(when_DebugPlugin_l287) begin
DebugPlugin_haltIt <= 1'b1;
DebugPlugin_haltedByBreak <= 1'b1;
end
end
if(when_DebugPlugin_l300) begin
if(decode_arbitration_isValid) begin
DebugPlugin_haltIt <= 1'b1;
end
end
end
end
endmodule
|
module DataCache (
input io_cpu_execute_isValid,
input [31:0] io_cpu_execute_address,
output reg io_cpu_execute_haltIt,
input io_cpu_execute_args_wr,
input [1:0] io_cpu_execute_args_size,
input io_cpu_execute_args_totalyConsistent,
output io_cpu_execute_refilling,
input io_cpu_memory_isValid,
input io_cpu_memory_isStuck,
output io_cpu_memory_isWrite,
input [31:0] io_cpu_memory_address,
input [31:0] io_cpu_memory_mmuRsp_physicalAddress,
input io_cpu_memory_mmuRsp_isIoAccess,
input io_cpu_memory_mmuRsp_isPaging,
input io_cpu_memory_mmuRsp_allowRead,
input io_cpu_memory_mmuRsp_allowWrite,
input io_cpu_memory_mmuRsp_allowExecute,
input io_cpu_memory_mmuRsp_exception,
input io_cpu_memory_mmuRsp_refilling,
input io_cpu_memory_mmuRsp_bypassTranslation,
input io_cpu_writeBack_isValid,
input io_cpu_writeBack_isStuck,
input io_cpu_writeBack_isUser,
output reg io_cpu_writeBack_haltIt,
output io_cpu_writeBack_isWrite,
input [31:0] io_cpu_writeBack_storeData,
output reg [31:0] io_cpu_writeBack_data,
input [31:0] io_cpu_writeBack_address,
output io_cpu_writeBack_mmuException,
output io_cpu_writeBack_unalignedAccess,
output reg io_cpu_writeBack_accessError,
output io_cpu_writeBack_keepMemRspData,
input io_cpu_writeBack_fence_SW,
input io_cpu_writeBack_fence_SR,
input io_cpu_writeBack_fence_SO,
input io_cpu_writeBack_fence_SI,
input io_cpu_writeBack_fence_PW,
input io_cpu_writeBack_fence_PR,
input io_cpu_writeBack_fence_PO,
input io_cpu_writeBack_fence_PI,
input [3:0] io_cpu_writeBack_fence_FM,
output io_cpu_writeBack_exclusiveOk,
output reg io_cpu_redo,
input io_cpu_flush_valid,
output io_cpu_flush_ready,
output reg io_mem_cmd_valid,
input io_mem_cmd_ready,
output reg io_mem_cmd_payload_wr,
output io_mem_cmd_payload_uncached,
output reg [31:0] io_mem_cmd_payload_address,
output [31:0] io_mem_cmd_payload_data,
output [3:0] io_mem_cmd_payload_mask,
output reg [2:0] io_mem_cmd_payload_size,
output io_mem_cmd_payload_last,
input io_mem_rsp_valid,
input io_mem_rsp_payload_last,
input [31:0] io_mem_rsp_payload_data,
input io_mem_rsp_payload_error,
input clk,
input reset
);
reg [21:0] _zz_ways_0_tags_port0;
reg [31:0] _zz_ways_0_data_port0;
wire [21:0] _zz_ways_0_tags_port;
wire [9:0] _zz_stage0_dataColisions;
wire [9:0] _zz__zz_stageA_dataColisions;
wire [0:0] _zz_when;
wire [2:0] _zz_loader_counter_valueNext;
wire [0:0] _zz_loader_counter_valueNext_1;
wire [1:0] _zz_loader_waysAllocator;
reg _zz_1;
reg _zz_2;
wire haltCpu;
reg tagsReadCmd_valid;
reg [6:0] tagsReadCmd_payload;
reg tagsWriteCmd_valid;
reg [0:0] tagsWriteCmd_payload_way;
reg [6:0] tagsWriteCmd_payload_address;
reg tagsWriteCmd_payload_data_valid;
reg tagsWriteCmd_payload_data_error;
reg [19:0] tagsWriteCmd_payload_data_address;
reg tagsWriteLastCmd_valid;
reg [0:0] tagsWriteLastCmd_payload_way;
reg [6:0] tagsWriteLastCmd_payload_address;
reg tagsWriteLastCmd_payload_data_valid;
reg tagsWriteLastCmd_payload_data_error;
reg [19:0] tagsWriteLastCmd_payload_data_address;
reg dataReadCmd_valid;
reg [9:0] dataReadCmd_payload;
reg dataWriteCmd_valid;
reg [0:0] dataWriteCmd_payload_way;
reg [9:0] dataWriteCmd_payload_address;
reg [31:0] dataWriteCmd_payload_data;
reg [3:0] dataWriteCmd_payload_mask;
wire _zz_ways_0_tagsReadRsp_valid;
wire ways_0_tagsReadRsp_valid;
wire ways_0_tagsReadRsp_error;
wire [19:0] ways_0_tagsReadRsp_address;
wire [21:0] _zz_ways_0_tagsReadRsp_valid_1;
wire _zz_ways_0_dataReadRspMem;
wire [31:0] ways_0_dataReadRspMem;
wire [31:0] ways_0_dataReadRsp;
wire when_DataCache_l634;
wire when_DataCache_l637;
wire when_DataCache_l656;
wire rspSync;
wire rspLast;
reg memCmdSent;
wire io_mem_cmd_fire;
wire when_DataCache_l678;
reg [3:0] _zz_stage0_mask;
wire [3:0] stage0_mask;
wire [0:0] stage0_dataColisions;
wire [0:0] stage0_wayInvalidate;
wire stage0_isAmo;
wire when_DataCache_l763;
reg stageA_request_wr;
reg [1:0] stageA_request_size;
reg stageA_request_totalyConsistent;
wire when_DataCache_l763_1;
reg [3:0] stageA_mask;
wire stageA_isAmo;
wire stageA_isLrsc;
wire [0:0] stageA_wayHits;
wire when_DataCache_l763_2;
reg [0:0] stageA_wayInvalidate;
wire when_DataCache_l763_3;
reg [0:0] stage0_dataColisions_regNextWhen;
wire [0:0] _zz_stageA_dataColisions;
wire [0:0] stageA_dataColisions;
wire when_DataCache_l814;
reg stageB_request_wr;
reg [1:0] stageB_request_size;
reg stageB_request_totalyConsistent;
reg stageB_mmuRspFreeze;
wire when_DataCache_l816;
reg [31:0] stageB_mmuRsp_physicalAddress;
reg stageB_mmuRsp_isIoAccess;
reg stageB_mmuRsp_isPaging;
reg stageB_mmuRsp_allowRead;
reg stageB_mmuRsp_allowWrite;
reg stageB_mmuRsp_allowExecute;
reg stageB_mmuRsp_exception;
reg stageB_mmuRsp_refilling;
reg stageB_mmuRsp_bypassTranslation;
wire when_DataCache_l813;
reg stageB_tagsReadRsp_0_valid;
reg stageB_tagsReadRsp_0_error;
reg [19:0] stageB_tagsReadRsp_0_address;
wire when_DataCache_l813_1;
reg [31:0] stageB_dataReadRsp_0;
wire when_DataCache_l812;
reg [0:0] stageB_wayInvalidate;
wire stageB_consistancyHazard;
wire when_DataCache_l812_1;
reg [0:0] stageB_dataColisions;
wire when_DataCache_l812_2;
reg stageB_unaligned;
wire when_DataCache_l812_3;
reg [0:0] stageB_waysHitsBeforeInvalidate;
wire [0:0] stageB_waysHits;
wire stageB_waysHit;
wire [31:0] stageB_dataMux;
wire when_DataCache_l812_4;
reg [3:0] stageB_mask;
reg stageB_loaderValid;
wire [31:0] stageB_ioMemRspMuxed;
reg stageB_flusher_waitDone;
wire stageB_flusher_hold;
reg [7:0] stageB_flusher_counter;
wire when_DataCache_l842;
wire when_DataCache_l848;
reg stageB_flusher_start;
wire stageB_isAmo;
wire stageB_isAmoCached;
wire stageB_isExternalLsrc;
wire stageB_isExternalAmo;
wire [31:0] stageB_requestDataBypass;
reg stageB_cpuWriteToCache;
wire when_DataCache_l911;
wire stageB_badPermissions;
wire stageB_loadStoreFault;
wire stageB_bypassCache;
wire when_DataCache_l980;
wire when_DataCache_l989;
wire when_DataCache_l994;
wire when_DataCache_l1005;
wire when_DataCache_l1017;
wire when_DataCache_l976;
wire when_DataCache_l1051;
wire when_DataCache_l1060;
reg loader_valid;
reg loader_counter_willIncrement;
wire loader_counter_willClear;
reg [2:0] loader_counter_valueNext;
reg [2:0] loader_counter_value;
wire loader_counter_willOverflowIfInc;
wire loader_counter_willOverflow;
reg [0:0] loader_waysAllocator;
reg loader_error;
wire loader_kill;
reg loader_killReg;
wire when_DataCache_l1075;
wire loader_done;
wire when_DataCache_l1103;
reg loader_valid_regNext;
wire when_DataCache_l1107;
wire when_DataCache_l1110;
(* ram_style = "block" *) reg [21:0] ways_0_tags [0:127];
(* ram_style = "block" *) reg [7:0] ways_0_data_symbol0 [0:1023];
(* ram_style = "block" *) reg [7:0] ways_0_data_symbol1 [0:1023];
(* ram_style = "block" *) reg [7:0] ways_0_data_symbol2 [0:1023];
(* ram_style = "block" *) reg [7:0] ways_0_data_symbol3 [0:1023];
reg [7:0] _zz_ways_0_datasymbol_read;
reg [7:0] _zz_ways_0_datasymbol_read_1;
reg [7:0] _zz_ways_0_datasymbol_read_2;
reg [7:0] _zz_ways_0_datasymbol_read_3;
assign _zz_stage0_dataColisions = (io_cpu_execute_address[11 : 2] >>> 0);
assign _zz__zz_stageA_dataColisions = (io_cpu_memory_address[11 : 2] >>> 0);
assign _zz_when = 1'b1;
assign _zz_loader_counter_valueNext_1 = loader_counter_willIncrement;
assign _zz_loader_counter_valueNext = {2'd0, _zz_loader_counter_valueNext_1};
assign _zz_loader_waysAllocator = {loader_waysAllocator,loader_waysAllocator[0]};
assign _zz_ways_0_tags_port = {tagsWriteCmd_payload_data_address,{tagsWriteCmd_payload_data_error,tagsWriteCmd_payload_data_valid}};
always @(posedge clk) begin
if(_zz_ways_0_tagsReadRsp_valid) begin
_zz_ways_0_tags_port0 <= ways_0_tags[tagsReadCmd_payload];
end
end
always @(posedge clk) begin
if(_zz_2) begin
ways_0_tags[tagsWriteCmd_payload_address] <= _zz_ways_0_tags_port;
end
end
always @(*) begin
_zz_ways_0_data_port0 = {_zz_ways_0_datasymbol_read_3, _zz_ways_0_datasymbol_read_2, _zz_ways_0_datasymbol_read_1, _zz_ways_0_datasymbol_read};
end
always @(posedge clk) begin
if(_zz_ways_0_dataReadRspMem) begin
_zz_ways_0_datasymbol_read <= ways_0_data_symbol0[dataReadCmd_payload];
_zz_ways_0_datasymbol_read_1 <= ways_0_data_symbol1[dataReadCmd_payload];
_zz_ways_0_datasymbol_read_2 <= ways_0_data_symbol2[dataReadCmd_payload];
_zz_ways_0_datasymbol_read_3 <= ways_0_data_symbol3[dataReadCmd_payload];
end
end
always @(posedge clk) begin
if(dataWriteCmd_payload_mask[0] && _zz_1) begin
ways_0_data_symbol0[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[7 : 0];
end
if(dataWriteCmd_payload_mask[1] && _zz_1) begin
ways_0_data_symbol1[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[15 : 8];
end
if(dataWriteCmd_payload_mask[2] && _zz_1) begin
ways_0_data_symbol2[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[23 : 16];
end
if(dataWriteCmd_payload_mask[3] && _zz_1) begin
ways_0_data_symbol3[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[31 : 24];
end
end
always @(*) begin
_zz_1 = 1'b0;
if(when_DataCache_l637) begin
_zz_1 = 1'b1;
end
end
always @(*) begin
_zz_2 = 1'b0;
if(when_DataCache_l634) begin
_zz_2 = 1'b1;
end
end
assign haltCpu = 1'b0;
assign _zz_ways_0_tagsReadRsp_valid = (tagsReadCmd_valid && (! io_cpu_memory_isStuck));
assign _zz_ways_0_tagsReadRsp_valid_1 = _zz_ways_0_tags_port0;
assign ways_0_tagsReadRsp_valid = _zz_ways_0_tagsReadRsp_valid_1[0];
assign ways_0_tagsReadRsp_error = _zz_ways_0_tagsReadRsp_valid_1[1];
assign ways_0_tagsReadRsp_address = _zz_ways_0_tagsReadRsp_valid_1[21 : 2];
assign _zz_ways_0_dataReadRspMem = (dataReadCmd_valid && (! io_cpu_memory_isStuck));
assign ways_0_dataReadRspMem = _zz_ways_0_data_port0;
assign ways_0_dataReadRsp = ways_0_dataReadRspMem[31 : 0];
assign when_DataCache_l634 = (tagsWriteCmd_valid && tagsWriteCmd_payload_way[0]);
assign when_DataCache_l637 = (dataWriteCmd_valid && dataWriteCmd_payload_way[0]);
always @(*) begin
tagsReadCmd_valid = 1'b0;
if(when_DataCache_l656) begin
tagsReadCmd_valid = 1'b1;
end
end
always @(*) begin
tagsReadCmd_payload = 7'bxxxxxxx;
if(when_DataCache_l656) begin
tagsReadCmd_payload = io_cpu_execute_address[11 : 5];
end
end
always @(*) begin
dataReadCmd_valid = 1'b0;
if(when_DataCache_l656) begin
dataReadCmd_valid = 1'b1;
end
end
always @(*) begin
dataReadCmd_payload = 10'bxxxxxxxxxx;
if(when_DataCache_l656) begin
dataReadCmd_payload = io_cpu_execute_address[11 : 2];
end
end
always @(*) begin
tagsWriteCmd_valid = 1'b0;
if(when_DataCache_l842) begin
tagsWriteCmd_valid = 1'b1;
end
if(when_DataCache_l1051) begin
tagsWriteCmd_valid = 1'b0;
end
if(loader_done) begin
tagsWriteCmd_valid = 1'b1;
end
end
always @(*) begin
tagsWriteCmd_payload_way = 1'bx;
if(when_DataCache_l842) begin
tagsWriteCmd_payload_way = 1'b1;
end
if(loader_done) begin
tagsWriteCmd_payload_way = loader_waysAllocator;
end
end
always @(*) begin
tagsWriteCmd_payload_address = 7'bxxxxxxx;
if(when_DataCache_l842) begin
tagsWriteCmd_payload_address = stageB_flusher_counter[6:0];
end
if(loader_done) begin
tagsWriteCmd_payload_address = stageB_mmuRsp_physicalAddress[11 : 5];
end
end
always @(*) begin
tagsWriteCmd_payload_data_valid = 1'bx;
if(when_DataCache_l842) begin
tagsWriteCmd_payload_data_valid = 1'b0;
end
if(loader_done) begin
tagsWriteCmd_payload_data_valid = (! (loader_kill || loader_killReg));
end
end
always @(*) begin
tagsWriteCmd_payload_data_error = 1'bx;
if(loader_done) begin
tagsWriteCmd_payload_data_error = (loader_error || (io_mem_rsp_valid && io_mem_rsp_payload_error));
end
end
always @(*) begin
tagsWriteCmd_payload_data_address = 20'bxxxxxxxxxxxxxxxxxxxx;
if(loader_done) begin
tagsWriteCmd_payload_data_address = stageB_mmuRsp_physicalAddress[31 : 12];
end
end
always @(*) begin
dataWriteCmd_valid = 1'b0;
if(stageB_cpuWriteToCache) begin
if(when_DataCache_l911) begin
dataWriteCmd_valid = 1'b1;
end
end
if(when_DataCache_l1051) begin
dataWriteCmd_valid = 1'b0;
end
if(when_DataCache_l1075) begin
dataWriteCmd_valid = 1'b1;
end
end
always @(*) begin
dataWriteCmd_payload_way = 1'bx;
if(stageB_cpuWriteToCache) begin
dataWriteCmd_payload_way = stageB_waysHits;
end
if(when_DataCache_l1075) begin
dataWriteCmd_payload_way = loader_waysAllocator;
end
end
always @(*) begin
dataWriteCmd_payload_address = 10'bxxxxxxxxxx;
if(stageB_cpuWriteToCache) begin
dataWriteCmd_payload_address = stageB_mmuRsp_physicalAddress[11 : 2];
end
if(when_DataCache_l1075) begin
dataWriteCmd_payload_address = {stageB_mmuRsp_physicalAddress[11 : 5],loader_counter_value};
end
end
always @(*) begin
dataWriteCmd_payload_data = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx;
if(stageB_cpuWriteToCache) begin
dataWriteCmd_payload_data[31 : 0] = stageB_requestDataBypass;
end
if(when_DataCache_l1075) begin
dataWriteCmd_payload_data = io_mem_rsp_payload_data;
end
end
always @(*) begin
dataWriteCmd_payload_mask = 4'bxxxx;
if(stageB_cpuWriteToCache) begin
dataWriteCmd_payload_mask = 4'b0000;
if(_zz_when[0]) begin
dataWriteCmd_payload_mask[3 : 0] = stageB_mask;
end
end
if(when_DataCache_l1075) begin
dataWriteCmd_payload_mask = 4'b1111;
end
end
assign when_DataCache_l656 = (io_cpu_execute_isValid && (! io_cpu_memory_isStuck));
always @(*) begin
io_cpu_execute_haltIt = 1'b0;
if(when_DataCache_l842) begin
io_cpu_execute_haltIt = 1'b1;
end
end
assign rspSync = 1'b1;
assign rspLast = 1'b1;
assign io_mem_cmd_fire = (io_mem_cmd_valid && io_mem_cmd_ready);
assign when_DataCache_l678 = (! io_cpu_writeBack_isStuck);
always @(*) begin
_zz_stage0_mask = 4'bxxxx;
case(io_cpu_execute_args_size)
2'b00 : begin
_zz_stage0_mask = 4'b0001;
end
2'b01 : begin
_zz_stage0_mask = 4'b0011;
end
2'b10 : begin
_zz_stage0_mask = 4'b1111;
end
default : begin
end
endcase
end
assign stage0_mask = (_zz_stage0_mask <<< io_cpu_execute_address[1 : 0]);
assign stage0_dataColisions[0] = (((dataWriteCmd_valid && dataWriteCmd_payload_way[0]) && (dataWriteCmd_payload_address == _zz_stage0_dataColisions)) && ((stage0_mask & dataWriteCmd_payload_mask[3 : 0]) != 4'b0000));
assign stage0_wayInvalidate = 1'b0;
assign stage0_isAmo = 1'b0;
assign when_DataCache_l763 = (! io_cpu_memory_isStuck);
assign when_DataCache_l763_1 = (! io_cpu_memory_isStuck);
assign io_cpu_memory_isWrite = stageA_request_wr;
assign stageA_isAmo = 1'b0;
assign stageA_isLrsc = 1'b0;
assign stageA_wayHits = ((io_cpu_memory_mmuRsp_physicalAddress[31 : 12] == ways_0_tagsReadRsp_address) && ways_0_tagsReadRsp_valid);
assign when_DataCache_l763_2 = (! io_cpu_memory_isStuck);
assign when_DataCache_l763_3 = (! io_cpu_memory_isStuck);
assign _zz_stageA_dataColisions[0] = (((dataWriteCmd_valid && dataWriteCmd_payload_way[0]) && (dataWriteCmd_payload_address == _zz__zz_stageA_dataColisions)) && ((stageA_mask & dataWriteCmd_payload_mask[3 : 0]) != 4'b0000));
assign stageA_dataColisions = (stage0_dataColisions_regNextWhen | _zz_stageA_dataColisions);
assign when_DataCache_l814 = (! io_cpu_writeBack_isStuck);
always @(*) begin
stageB_mmuRspFreeze = 1'b0;
if(when_DataCache_l1110) begin
stageB_mmuRspFreeze = 1'b1;
end
end
assign when_DataCache_l816 = ((! io_cpu_writeBack_isStuck) && (! stageB_mmuRspFreeze));
assign when_DataCache_l813 = (! io_cpu_writeBack_isStuck);
assign when_DataCache_l813_1 = (! io_cpu_writeBack_isStuck);
assign when_DataCache_l812 = (! io_cpu_writeBack_isStuck);
assign stageB_consistancyHazard = 1'b0;
assign when_DataCache_l812_1 = (! io_cpu_writeBack_isStuck);
assign when_DataCache_l812_2 = (! io_cpu_writeBack_isStuck);
assign when_DataCache_l812_3 = (! io_cpu_writeBack_isStuck);
assign stageB_waysHits = (stageB_waysHitsBeforeInvalidate & (~ stageB_wayInvalidate));
assign stageB_waysHit = (stageB_waysHits != 1'b0);
assign stageB_dataMux = stageB_dataReadRsp_0;
assign when_DataCache_l812_4 = (! io_cpu_writeBack_isStuck);
always @(*) begin
stageB_loaderValid = 1'b0;
if(io_cpu_writeBack_isValid) begin
if(!stageB_isExternalAmo) begin
if(!when_DataCache_l976) begin
if(!when_DataCache_l989) begin
if(io_mem_cmd_ready) begin
stageB_loaderValid = 1'b1;
end
end
end
end
end
if(when_DataCache_l1051) begin
stageB_loaderValid = 1'b0;
end
end
assign stageB_ioMemRspMuxed = io_mem_rsp_payload_data[31 : 0];
always @(*) begin
io_cpu_writeBack_haltIt = 1'b1;
if(io_cpu_writeBack_isValid) begin
if(!stageB_isExternalAmo) begin
if(when_DataCache_l976) begin
if(when_DataCache_l980) begin
io_cpu_writeBack_haltIt = 1'b0;
end
end else begin
if(when_DataCache_l989) begin
if(when_DataCache_l994) begin
io_cpu_writeBack_haltIt = 1'b0;
end
end
end
end
end
if(when_DataCache_l1051) begin
io_cpu_writeBack_haltIt = 1'b0;
end
end
assign stageB_flusher_hold = 1'b0;
assign when_DataCache_l842 = (! stageB_flusher_counter[7]);
assign when_DataCache_l848 = (! stageB_flusher_hold);
assign io_cpu_flush_ready = (stageB_flusher_waitDone && stageB_flusher_counter[7]);
assign stageB_isAmo = 1'b0;
assign stageB_isAmoCached = 1'b0;
assign stageB_isExternalLsrc = 1'b0;
assign stageB_isExternalAmo = 1'b0;
assign stageB_requestDataBypass = io_cpu_writeBack_storeData;
always @(*) begin
stageB_cpuWriteToCache = 1'b0;
if(io_cpu_writeBack_isValid) begin
if(!stageB_isExternalAmo) begin
if(!when_DataCache_l976) begin
if(when_DataCache_l989) begin
stageB_cpuWriteToCache = 1'b1;
end
end
end
end
end
assign when_DataCache_l911 = (stageB_request_wr && stageB_waysHit);
assign stageB_badPermissions = (((! stageB_mmuRsp_allowWrite) && stageB_request_wr) || ((! stageB_mmuRsp_allowRead) && ((! stageB_request_wr) || stageB_isAmo)));
assign stageB_loadStoreFault = (io_cpu_writeBack_isValid && (stageB_mmuRsp_exception || stageB_badPermissions));
always @(*) begin
io_cpu_redo = 1'b0;
if(io_cpu_writeBack_isValid) begin
if(!stageB_isExternalAmo) begin
if(!when_DataCache_l976) begin
if(when_DataCache_l989) begin
if(when_DataCache_l1005) begin
io_cpu_redo = 1'b1;
end
end
end
end
end
if(when_DataCache_l1060) begin
io_cpu_redo = 1'b1;
end
if(when_DataCache_l1107) begin
io_cpu_redo = 1'b1;
end
end
always @(*) begin
io_cpu_writeBack_accessError = 1'b0;
if(stageB_bypassCache) begin
io_cpu_writeBack_accessError = ((((! stageB_request_wr) && 1'b1) && io_mem_rsp_valid) && io_mem_rsp_payload_error);
end else begin
io_cpu_writeBack_accessError = (((stageB_waysHits & stageB_tagsReadRsp_0_error) != 1'b0) || (stageB_loadStoreFault && (! stageB_mmuRsp_isPaging)));
end
end
assign io_cpu_writeBack_mmuException = (stageB_loadStoreFault && stageB_mmuRsp_isPaging);
assign io_cpu_writeBack_unalignedAccess = (io_cpu_writeBack_isValid && stageB_unaligned);
assign io_cpu_writeBack_isWrite = stageB_request_wr;
always @(*) begin
io_mem_cmd_valid = 1'b0;
if(io_cpu_writeBack_isValid) begin
if(!stageB_isExternalAmo) begin
if(when_DataCache_l976) begin
io_mem_cmd_valid = (! memCmdSent);
end else begin
if(when_DataCache_l989) begin
if(stageB_request_wr) begin
io_mem_cmd_valid = 1'b1;
end
end else begin
if(when_DataCache_l1017) begin
io_mem_cmd_valid = 1'b1;
end
end
end
end
end
if(when_DataCache_l1051) begin
io_mem_cmd_valid = 1'b0;
end
end
always @(*) begin
io_mem_cmd_payload_address = stageB_mmuRsp_physicalAddress;
if(io_cpu_writeBack_isValid) begin
if(!stageB_isExternalAmo) begin
if(!when_DataCache_l976) begin
if(!when_DataCache_l989) begin
io_mem_cmd_payload_address[4 : 0] = 5'h0;
end
end
end
end
end
assign io_mem_cmd_payload_last = 1'b1;
always @(*) begin
io_mem_cmd_payload_wr = stageB_request_wr;
if(io_cpu_writeBack_isValid) begin
if(!stageB_isExternalAmo) begin
if(!when_DataCache_l976) begin
if(!when_DataCache_l989) begin
io_mem_cmd_payload_wr = 1'b0;
end
end
end
end
end
assign io_mem_cmd_payload_mask = stageB_mask;
assign io_mem_cmd_payload_data = stageB_requestDataBypass;
assign io_mem_cmd_payload_uncached = stageB_mmuRsp_isIoAccess;
always @(*) begin
io_mem_cmd_payload_size = {1'd0, stageB_request_size};
if(io_cpu_writeBack_isValid) begin
if(!stageB_isExternalAmo) begin
if(!when_DataCache_l976) begin
if(!when_DataCache_l989) begin
io_mem_cmd_payload_size = 3'b101;
end
end
end
end
end
assign stageB_bypassCache = ((stageB_mmuRsp_isIoAccess || stageB_isExternalLsrc) || stageB_isExternalAmo);
assign io_cpu_writeBack_keepMemRspData = 1'b0;
assign when_DataCache_l980 = ((! stageB_request_wr) ? (io_mem_rsp_valid && rspSync) : io_mem_cmd_ready);
assign when_DataCache_l989 = (stageB_waysHit || (stageB_request_wr && (! stageB_isAmoCached)));
assign when_DataCache_l994 = ((! stageB_request_wr) || io_mem_cmd_ready);
assign when_DataCache_l1005 = (((! stageB_request_wr) || stageB_isAmoCached) && ((stageB_dataColisions & stageB_waysHits) != 1'b0));
assign when_DataCache_l1017 = (! memCmdSent);
assign when_DataCache_l976 = (stageB_mmuRsp_isIoAccess || stageB_isExternalLsrc);
always @(*) begin
if(stageB_bypassCache) begin
io_cpu_writeBack_data = stageB_ioMemRspMuxed;
end else begin
io_cpu_writeBack_data = stageB_dataMux;
end
end
assign when_DataCache_l1051 = ((((stageB_consistancyHazard || stageB_mmuRsp_refilling) || io_cpu_writeBack_accessError) || io_cpu_writeBack_mmuException) || io_cpu_writeBack_unalignedAccess);
assign when_DataCache_l1060 = (io_cpu_writeBack_isValid && (stageB_mmuRsp_refilling || stageB_consistancyHazard));
always @(*) begin
loader_counter_willIncrement = 1'b0;
if(when_DataCache_l1075) begin
loader_counter_willIncrement = 1'b1;
end
end
assign loader_counter_willClear = 1'b0;
assign loader_counter_willOverflowIfInc = (loader_counter_value == 3'b111);
assign loader_counter_willOverflow = (loader_counter_willOverflowIfInc && loader_counter_willIncrement);
always @(*) begin
loader_counter_valueNext = (loader_counter_value + _zz_loader_counter_valueNext);
if(loader_counter_willClear) begin
loader_counter_valueNext = 3'b000;
end
end
assign loader_kill = 1'b0;
assign when_DataCache_l1075 = ((loader_valid && io_mem_rsp_valid) && rspLast);
assign loader_done = loader_counter_willOverflow;
assign when_DataCache_l1103 = (! loader_valid);
assign when_DataCache_l1107 = (loader_valid && (! loader_valid_regNext));
assign io_cpu_execute_refilling = loader_valid;
assign when_DataCache_l1110 = (stageB_loaderValid || loader_valid);
always @(posedge clk) begin
tagsWriteLastCmd_valid <= tagsWriteCmd_valid;
tagsWriteLastCmd_payload_way <= tagsWriteCmd_payload_way;
tagsWriteLastCmd_payload_address <= tagsWriteCmd_payload_address;
tagsWriteLastCmd_payload_data_valid <= tagsWriteCmd_payload_data_valid;
tagsWriteLastCmd_payload_data_error <= tagsWriteCmd_payload_data_error;
tagsWriteLastCmd_payload_data_address <= tagsWriteCmd_payload_data_address;
if(when_DataCache_l763) begin
stageA_request_wr <= io_cpu_execute_args_wr;
stageA_request_size <= io_cpu_execute_args_size;
stageA_request_totalyConsistent <= io_cpu_execute_args_totalyConsistent;
end
if(when_DataCache_l763_1) begin
stageA_mask <= stage0_mask;
end
if(when_DataCache_l763_2) begin
stageA_wayInvalidate <= stage0_wayInvalidate;
end
if(when_DataCache_l763_3) begin
stage0_dataColisions_regNextWhen <= stage0_dataColisions;
end
if(when_DataCache_l814) begin
stageB_request_wr <= stageA_request_wr;
stageB_request_size <= stageA_request_size;
stageB_request_totalyConsistent <= stageA_request_totalyConsistent;
end
if(when_DataCache_l816) begin
stageB_mmuRsp_physicalAddress <= io_cpu_memory_mmuRsp_physicalAddress;
stageB_mmuRsp_isIoAccess <= io_cpu_memory_mmuRsp_isIoAccess;
stageB_mmuRsp_isPaging <= io_cpu_memory_mmuRsp_isPaging;
stageB_mmuRsp_allowRead <= io_cpu_memory_mmuRsp_allowRead;
stageB_mmuRsp_allowWrite <= io_cpu_memory_mmuRsp_allowWrite;
stageB_mmuRsp_allowExecute <= io_cpu_memory_mmuRsp_allowExecute;
stageB_mmuRsp_exception <= io_cpu_memory_mmuRsp_exception;
stageB_mmuRsp_refilling <= io_cpu_memory_mmuRsp_refilling;
stageB_mmuRsp_bypassTranslation <= io_cpu_memory_mmuRsp_bypassTranslation;
end
if(when_DataCache_l813) begin
stageB_tagsReadRsp_0_valid <= ways_0_tagsReadRsp_valid;
stageB_tagsReadRsp_0_error <= ways_0_tagsReadRsp_error;
stageB_tagsReadRsp_0_address <= ways_0_tagsReadRsp_address;
end
if(when_DataCache_l813_1) begin
stageB_dataReadRsp_0 <= ways_0_dataReadRsp;
end
if(when_DataCache_l812) begin
stageB_wayInvalidate <= stageA_wayInvalidate;
end
if(when_DataCache_l812_1) begin
stageB_dataColisions <= stageA_dataColisions;
end
if(when_DataCache_l812_2) begin
stageB_unaligned <= ({((stageA_request_size == 2'b10) && (io_cpu_memory_address[1 : 0] != 2'b00)),((stageA_request_size == 2'b01) && (io_cpu_memory_address[0 : 0] != 1'b0))} != 2'b00);
end
if(when_DataCache_l812_3) begin
stageB_waysHitsBeforeInvalidate <= stageA_wayHits;
end
if(when_DataCache_l812_4) begin
stageB_mask <= stageA_mask;
end
loader_valid_regNext <= loader_valid;
end
always @(posedge clk) begin
if(reset) begin
memCmdSent <= 1'b0;
stageB_flusher_waitDone <= 1'b0;
stageB_flusher_counter <= 8'h0;
stageB_flusher_start <= 1'b1;
loader_valid <= 1'b0;
loader_counter_value <= 3'b000;
loader_waysAllocator <= 1'b1;
loader_error <= 1'b0;
loader_killReg <= 1'b0;
end else begin
if(io_mem_cmd_fire) begin
memCmdSent <= 1'b1;
end
if(when_DataCache_l678) begin
memCmdSent <= 1'b0;
end
if(io_cpu_flush_ready) begin
stageB_flusher_waitDone <= 1'b0;
end
if(when_DataCache_l842) begin
if(when_DataCache_l848) begin
stageB_flusher_counter <= (stageB_flusher_counter + 8'h01);
end
end
stageB_flusher_start <= (((((((! stageB_flusher_waitDone) && (! stageB_flusher_start)) && io_cpu_flush_valid) && (! io_cpu_execute_isValid)) && (! io_cpu_memory_isValid)) && (! io_cpu_writeBack_isValid)) && (! io_cpu_redo));
if(stageB_flusher_start) begin
stageB_flusher_waitDone <= 1'b1;
stageB_flusher_counter <= 8'h0;
end
`ifndef SYNTHESIS
`ifdef FORMAL
assert((! ((io_cpu_writeBack_isValid && (! io_cpu_writeBack_haltIt)) && io_cpu_writeBack_isStuck)));
`else
if(!(! ((io_cpu_writeBack_isValid && (! io_cpu_writeBack_haltIt)) && io_cpu_writeBack_isStuck))) begin
$display("ERROR writeBack stuck by another plugin is not allowed");
end
`endif
`endif
if(stageB_loaderValid) begin
loader_valid <= 1'b1;
end
loader_counter_value <= loader_counter_valueNext;
if(loader_kill) begin
loader_killReg <= 1'b1;
end
if(when_DataCache_l1075) begin
loader_error <= (loader_error || io_mem_rsp_payload_error);
end
if(loader_done) begin
loader_valid <= 1'b0;
loader_error <= 1'b0;
loader_killReg <= 1'b0;
end
if(when_DataCache_l1103) begin
loader_waysAllocator <= _zz_loader_waysAllocator[0:0];
end
end
end
endmodule
|
module InstructionCache (
input io_flush,
input io_cpu_prefetch_isValid,
output reg io_cpu_prefetch_haltIt,
input [31:0] io_cpu_prefetch_pc,
input io_cpu_fetch_isValid,
input io_cpu_fetch_isStuck,
input io_cpu_fetch_isRemoved,
input [31:0] io_cpu_fetch_pc,
output [31:0] io_cpu_fetch_data,
input [31:0] io_cpu_fetch_mmuRsp_physicalAddress,
input io_cpu_fetch_mmuRsp_isIoAccess,
input io_cpu_fetch_mmuRsp_isPaging,
input io_cpu_fetch_mmuRsp_allowRead,
input io_cpu_fetch_mmuRsp_allowWrite,
input io_cpu_fetch_mmuRsp_allowExecute,
input io_cpu_fetch_mmuRsp_exception,
input io_cpu_fetch_mmuRsp_refilling,
input io_cpu_fetch_mmuRsp_bypassTranslation,
output [31:0] io_cpu_fetch_physicalAddress,
input io_cpu_decode_isValid,
input io_cpu_decode_isStuck,
input [31:0] io_cpu_decode_pc,
output [31:0] io_cpu_decode_physicalAddress,
output [31:0] io_cpu_decode_data,
output io_cpu_decode_cacheMiss,
output io_cpu_decode_error,
output io_cpu_decode_mmuRefilling,
output io_cpu_decode_mmuException,
input io_cpu_decode_isUser,
input io_cpu_fill_valid,
input [31:0] io_cpu_fill_payload,
output io_mem_cmd_valid,
input io_mem_cmd_ready,
output [31:0] io_mem_cmd_payload_address,
output [2:0] io_mem_cmd_payload_size,
input io_mem_rsp_valid,
input [31:0] io_mem_rsp_payload_data,
input io_mem_rsp_payload_error,
input [2:0] _zz_when_Fetcher_l398,
input [31:0] _zz_io_cpu_fetch_data_regNextWhen,
input clk,
input reset
);
reg [31:0] _zz_banks_0_port1;
reg [22:0] _zz_ways_0_tags_port1;
wire [22:0] _zz_ways_0_tags_port;
reg _zz_1;
reg _zz_2;
reg lineLoader_fire;
reg lineLoader_valid;
(* keep , syn_keep *) reg [31:0] lineLoader_address /* synthesis syn_keep = 1 */ ;
reg lineLoader_hadError;
reg lineLoader_flushPending;
reg [6:0] lineLoader_flushCounter;
wire when_InstructionCache_l338;
reg _zz_when_InstructionCache_l342;
wire when_InstructionCache_l342;
wire when_InstructionCache_l351;
reg lineLoader_cmdSent;
wire io_mem_cmd_fire;
wire when_Utils_l357;
reg lineLoader_wayToAllocate_willIncrement;
wire lineLoader_wayToAllocate_willClear;
wire lineLoader_wayToAllocate_willOverflowIfInc;
wire lineLoader_wayToAllocate_willOverflow;
(* keep , syn_keep *) reg [2:0] lineLoader_wordIndex /* synthesis syn_keep = 1 */ ;
wire lineLoader_write_tag_0_valid;
wire [5:0] lineLoader_write_tag_0_payload_address;
wire lineLoader_write_tag_0_payload_data_valid;
wire lineLoader_write_tag_0_payload_data_error;
wire [20:0] lineLoader_write_tag_0_payload_data_address;
wire lineLoader_write_data_0_valid;
wire [8:0] lineLoader_write_data_0_payload_address;
wire [31:0] lineLoader_write_data_0_payload_data;
wire when_InstructionCache_l401;
wire [8:0] _zz_fetchStage_read_banksValue_0_dataMem;
wire _zz_fetchStage_read_banksValue_0_dataMem_1;
wire [31:0] fetchStage_read_banksValue_0_dataMem;
wire [31:0] fetchStage_read_banksValue_0_data;
wire [5:0] _zz_fetchStage_read_waysValues_0_tag_valid;
wire _zz_fetchStage_read_waysValues_0_tag_valid_1;
wire fetchStage_read_waysValues_0_tag_valid;
wire fetchStage_read_waysValues_0_tag_error;
wire [20:0] fetchStage_read_waysValues_0_tag_address;
wire [22:0] _zz_fetchStage_read_waysValues_0_tag_valid_2;
wire fetchStage_hit_hits_0;
wire fetchStage_hit_valid;
wire fetchStage_hit_error;
wire [31:0] fetchStage_hit_data;
wire [31:0] fetchStage_hit_word;
wire when_InstructionCache_l435;
reg [31:0] io_cpu_fetch_data_regNextWhen;
wire when_InstructionCache_l459;
reg [31:0] decodeStage_mmuRsp_physicalAddress;
reg decodeStage_mmuRsp_isIoAccess;
reg decodeStage_mmuRsp_isPaging;
reg decodeStage_mmuRsp_allowRead;
reg decodeStage_mmuRsp_allowWrite;
reg decodeStage_mmuRsp_allowExecute;
reg decodeStage_mmuRsp_exception;
reg decodeStage_mmuRsp_refilling;
reg decodeStage_mmuRsp_bypassTranslation;
wire when_InstructionCache_l459_1;
reg decodeStage_hit_valid;
wire when_InstructionCache_l459_2;
reg decodeStage_hit_error;
wire when_Fetcher_l398;
(* ram_style = "block" *) reg [31:0] banks_0 [0:511];
(* ram_style = "block" *) reg [22:0] ways_0_tags [0:63];
assign _zz_ways_0_tags_port = {lineLoader_write_tag_0_payload_data_address,{lineLoader_write_tag_0_payload_data_error,lineLoader_write_tag_0_payload_data_valid}};
always @(posedge clk) begin
if(_zz_1) begin
banks_0[lineLoader_write_data_0_payload_address] <= lineLoader_write_data_0_payload_data;
end
end
always @(posedge clk) begin
if(_zz_fetchStage_read_banksValue_0_dataMem_1) begin
_zz_banks_0_port1 <= banks_0[_zz_fetchStage_read_banksValue_0_dataMem];
end
end
always @(posedge clk) begin
if(_zz_2) begin
ways_0_tags[lineLoader_write_tag_0_payload_address] <= _zz_ways_0_tags_port;
end
end
always @(posedge clk) begin
if(_zz_fetchStage_read_waysValues_0_tag_valid_1) begin
_zz_ways_0_tags_port1 <= ways_0_tags[_zz_fetchStage_read_waysValues_0_tag_valid];
end
end
always @(*) begin
_zz_1 = 1'b0;
if(lineLoader_write_data_0_valid) begin
_zz_1 = 1'b1;
end
end
always @(*) begin
_zz_2 = 1'b0;
if(lineLoader_write_tag_0_valid) begin
_zz_2 = 1'b1;
end
end
always @(*) begin
lineLoader_fire = 1'b0;
if(io_mem_rsp_valid) begin
if(when_InstructionCache_l401) begin
lineLoader_fire = 1'b1;
end
end
end
always @(*) begin
io_cpu_prefetch_haltIt = (lineLoader_valid || lineLoader_flushPending);
if(when_InstructionCache_l338) begin
io_cpu_prefetch_haltIt = 1'b1;
end
if(when_InstructionCache_l342) begin
io_cpu_prefetch_haltIt = 1'b1;
end
if(io_flush) begin
io_cpu_prefetch_haltIt = 1'b1;
end
end
assign when_InstructionCache_l338 = (! lineLoader_flushCounter[6]);
assign when_InstructionCache_l342 = (! _zz_when_InstructionCache_l342);
assign when_InstructionCache_l351 = (lineLoader_flushPending && (! (lineLoader_valid || io_cpu_fetch_isValid)));
assign io_mem_cmd_fire = (io_mem_cmd_valid && io_mem_cmd_ready);
assign io_mem_cmd_valid = (lineLoader_valid && (! lineLoader_cmdSent));
assign io_mem_cmd_payload_address = {lineLoader_address[31 : 5],5'h0};
assign io_mem_cmd_payload_size = 3'b101;
assign when_Utils_l357 = (! lineLoader_valid);
always @(*) begin
lineLoader_wayToAllocate_willIncrement = 1'b0;
if(when_Utils_l357) begin
lineLoader_wayToAllocate_willIncrement = 1'b1;
end
end
assign lineLoader_wayToAllocate_willClear = 1'b0;
assign lineLoader_wayToAllocate_willOverflowIfInc = 1'b1;
assign lineLoader_wayToAllocate_willOverflow = (lineLoader_wayToAllocate_willOverflowIfInc && lineLoader_wayToAllocate_willIncrement);
assign lineLoader_write_tag_0_valid = ((1'b1 && lineLoader_fire) || (! lineLoader_flushCounter[6]));
assign lineLoader_write_tag_0_payload_address = (lineLoader_flushCounter[6] ? lineLoader_address[10 : 5] : lineLoader_flushCounter[5 : 0]);
assign lineLoader_write_tag_0_payload_data_valid = lineLoader_flushCounter[6];
assign lineLoader_write_tag_0_payload_data_error = (lineLoader_hadError || io_mem_rsp_payload_error);
assign lineLoader_write_tag_0_payload_data_address = lineLoader_address[31 : 11];
assign lineLoader_write_data_0_valid = (io_mem_rsp_valid && 1'b1);
assign lineLoader_write_data_0_payload_address = {lineLoader_address[10 : 5],lineLoader_wordIndex};
assign lineLoader_write_data_0_payload_data = io_mem_rsp_payload_data;
assign when_InstructionCache_l401 = (lineLoader_wordIndex == 3'b111);
assign _zz_fetchStage_read_banksValue_0_dataMem = io_cpu_prefetch_pc[10 : 2];
assign _zz_fetchStage_read_banksValue_0_dataMem_1 = (! io_cpu_fetch_isStuck);
assign fetchStage_read_banksValue_0_dataMem = _zz_banks_0_port1;
assign fetchStage_read_banksValue_0_data = fetchStage_read_banksValue_0_dataMem[31 : 0];
assign _zz_fetchStage_read_waysValues_0_tag_valid = io_cpu_prefetch_pc[10 : 5];
assign _zz_fetchStage_read_waysValues_0_tag_valid_1 = (! io_cpu_fetch_isStuck);
assign _zz_fetchStage_read_waysValues_0_tag_valid_2 = _zz_ways_0_tags_port1;
assign fetchStage_read_waysValues_0_tag_valid = _zz_fetchStage_read_waysValues_0_tag_valid_2[0];
assign fetchStage_read_waysValues_0_tag_error = _zz_fetchStage_read_waysValues_0_tag_valid_2[1];
assign fetchStage_read_waysValues_0_tag_address = _zz_fetchStage_read_waysValues_0_tag_valid_2[22 : 2];
assign fetchStage_hit_hits_0 = (fetchStage_read_waysValues_0_tag_valid && (fetchStage_read_waysValues_0_tag_address == io_cpu_fetch_mmuRsp_physicalAddress[31 : 11]));
assign fetchStage_hit_valid = (fetchStage_hit_hits_0 != 1'b0);
assign fetchStage_hit_error = fetchStage_read_waysValues_0_tag_error;
assign fetchStage_hit_data = fetchStage_read_banksValue_0_data;
assign fetchStage_hit_word = fetchStage_hit_data;
assign io_cpu_fetch_data = fetchStage_hit_word;
assign when_InstructionCache_l435 = (! io_cpu_decode_isStuck);
assign io_cpu_decode_data = io_cpu_fetch_data_regNextWhen;
assign io_cpu_fetch_physicalAddress = io_cpu_fetch_mmuRsp_physicalAddress;
assign when_InstructionCache_l459 = (! io_cpu_decode_isStuck);
assign when_InstructionCache_l459_1 = (! io_cpu_decode_isStuck);
assign when_InstructionCache_l459_2 = (! io_cpu_decode_isStuck);
assign io_cpu_decode_cacheMiss = (! decodeStage_hit_valid);
assign io_cpu_decode_error = (decodeStage_hit_error || ((! decodeStage_mmuRsp_isPaging) && (decodeStage_mmuRsp_exception || (! decodeStage_mmuRsp_allowExecute))));
assign io_cpu_decode_mmuRefilling = decodeStage_mmuRsp_refilling;
assign io_cpu_decode_mmuException = (((! decodeStage_mmuRsp_refilling) && decodeStage_mmuRsp_isPaging) && (decodeStage_mmuRsp_exception || (! decodeStage_mmuRsp_allowExecute)));
assign io_cpu_decode_physicalAddress = decodeStage_mmuRsp_physicalAddress;
assign when_Fetcher_l398 = (_zz_when_Fetcher_l398 != 3'b000);
always @(posedge clk) begin
if(reset) begin
lineLoader_valid <= 1'b0;
lineLoader_hadError <= 1'b0;
lineLoader_flushPending <= 1'b1;
lineLoader_cmdSent <= 1'b0;
lineLoader_wordIndex <= 3'b000;
end else begin
if(lineLoader_fire) begin
lineLoader_valid <= 1'b0;
end
if(lineLoader_fire) begin
lineLoader_hadError <= 1'b0;
end
if(io_cpu_fill_valid) begin
lineLoader_valid <= 1'b1;
end
if(io_flush) begin
lineLoader_flushPending <= 1'b1;
end
if(when_InstructionCache_l351) begin
lineLoader_flushPending <= 1'b0;
end
if(io_mem_cmd_fire) begin
lineLoader_cmdSent <= 1'b1;
end
if(lineLoader_fire) begin
lineLoader_cmdSent <= 1'b0;
end
if(io_mem_rsp_valid) begin
lineLoader_wordIndex <= (lineLoader_wordIndex + 3'b001);
if(io_mem_rsp_payload_error) begin
lineLoader_hadError <= 1'b1;
end
end
end
end
always @(posedge clk) begin
if(io_cpu_fill_valid) begin
lineLoader_address <= io_cpu_fill_payload;
end
if(when_InstructionCache_l338) begin
lineLoader_flushCounter <= (lineLoader_flushCounter + 7'h01);
end
_zz_when_InstructionCache_l342 <= lineLoader_flushCounter[6];
if(when_InstructionCache_l351) begin
lineLoader_flushCounter <= 7'h0;
end
if(when_InstructionCache_l435) begin
io_cpu_fetch_data_regNextWhen <= io_cpu_fetch_data;
end
if(when_InstructionCache_l459) begin
decodeStage_mmuRsp_physicalAddress <= io_cpu_fetch_mmuRsp_physicalAddress;
decodeStage_mmuRsp_isIoAccess <= io_cpu_fetch_mmuRsp_isIoAccess;
decodeStage_mmuRsp_isPaging <= io_cpu_fetch_mmuRsp_isPaging;
decodeStage_mmuRsp_allowRead <= io_cpu_fetch_mmuRsp_allowRead;
decodeStage_mmuRsp_allowWrite <= io_cpu_fetch_mmuRsp_allowWrite;
decodeStage_mmuRsp_allowExecute <= io_cpu_fetch_mmuRsp_allowExecute;
decodeStage_mmuRsp_exception <= io_cpu_fetch_mmuRsp_exception;
decodeStage_mmuRsp_refilling <= io_cpu_fetch_mmuRsp_refilling;
decodeStage_mmuRsp_bypassTranslation <= io_cpu_fetch_mmuRsp_bypassTranslation;
end
if(when_InstructionCache_l459_1) begin
decodeStage_hit_valid <= fetchStage_hit_valid;
end
if(when_InstructionCache_l459_2) begin
decodeStage_hit_error <= fetchStage_hit_error;
end
if(when_Fetcher_l398) begin
io_cpu_fetch_data_regNextWhen <= _zz_io_cpu_fetch_data_regNextWhen;
end
end
endmodule
|
module system_processing_system7_0_0 (
SDIO0_WP,
TTC0_WAVE0_OUT,
TTC0_WAVE1_OUT,
TTC0_WAVE2_OUT,
USB0_PORT_INDCTL,
USB0_VBUS_PWRSELECT,
USB0_VBUS_PWRFAULT,
M_AXI_GP0_ARVALID,
M_AXI_GP0_AWVALID,
M_AXI_GP0_BREADY,
M_AXI_GP0_RREADY,
M_AXI_GP0_WLAST,
M_AXI_GP0_WVALID,
M_AXI_GP0_ARID,
M_AXI_GP0_AWID,
M_AXI_GP0_WID,
M_AXI_GP0_ARBURST,
M_AXI_GP0_ARLOCK,
M_AXI_GP0_ARSIZE,
M_AXI_GP0_AWBURST,
M_AXI_GP0_AWLOCK,
M_AXI_GP0_AWSIZE,
M_AXI_GP0_ARPROT,
M_AXI_GP0_AWPROT,
M_AXI_GP0_ARADDR,
M_AXI_GP0_AWADDR,
M_AXI_GP0_WDATA,
M_AXI_GP0_ARCACHE,
M_AXI_GP0_ARLEN,
M_AXI_GP0_ARQOS,
M_AXI_GP0_AWCACHE,
M_AXI_GP0_AWLEN,
M_AXI_GP0_AWQOS,
M_AXI_GP0_WSTRB,
M_AXI_GP0_ACLK,
M_AXI_GP0_ARREADY,
M_AXI_GP0_AWREADY,
M_AXI_GP0_BVALID,
M_AXI_GP0_RLAST,
M_AXI_GP0_RVALID,
M_AXI_GP0_WREADY,
M_AXI_GP0_BID,
M_AXI_GP0_RID,
M_AXI_GP0_BRESP,
M_AXI_GP0_RRESP,
M_AXI_GP0_RDATA,
FCLK_CLK0,
FCLK_RESET0_N,
MIO,
DDR_CAS_n,
DDR_CKE,
DDR_Clk_n,
DDR_Clk,
DDR_CS_n,
DDR_DRSTB,
DDR_ODT,
DDR_RAS_n,
DDR_WEB,
DDR_BankAddr,
DDR_Addr,
DDR_VRN,
DDR_VRP,
DDR_DM,
DDR_DQ,
DDR_DQS_n,
DDR_DQS,
PS_SRSTB,
PS_CLK,
PS_PORB
);
input SDIO0_WP;
output TTC0_WAVE0_OUT;
output TTC0_WAVE1_OUT;
output TTC0_WAVE2_OUT;
output [1 : 0] USB0_PORT_INDCTL;
output USB0_VBUS_PWRSELECT;
input USB0_VBUS_PWRFAULT;
output M_AXI_GP0_ARVALID;
output M_AXI_GP0_AWVALID;
output M_AXI_GP0_BREADY;
output M_AXI_GP0_RREADY;
output M_AXI_GP0_WLAST;
output M_AXI_GP0_WVALID;
output [11 : 0] M_AXI_GP0_ARID;
output [11 : 0] M_AXI_GP0_AWID;
output [11 : 0] M_AXI_GP0_WID;
output [1 : 0] M_AXI_GP0_ARBURST;
output [1 : 0] M_AXI_GP0_ARLOCK;
output [2 : 0] M_AXI_GP0_ARSIZE;
output [1 : 0] M_AXI_GP0_AWBURST;
output [1 : 0] M_AXI_GP0_AWLOCK;
output [2 : 0] M_AXI_GP0_AWSIZE;
output [2 : 0] M_AXI_GP0_ARPROT;
output [2 : 0] M_AXI_GP0_AWPROT;
output [31 : 0] M_AXI_GP0_ARADDR;
output [31 : 0] M_AXI_GP0_AWADDR;
output [31 : 0] M_AXI_GP0_WDATA;
output [3 : 0] M_AXI_GP0_ARCACHE;
output [3 : 0] M_AXI_GP0_ARLEN;
output [3 : 0] M_AXI_GP0_ARQOS;
output [3 : 0] M_AXI_GP0_AWCACHE;
output [3 : 0] M_AXI_GP0_AWLEN;
output [3 : 0] M_AXI_GP0_AWQOS;
output [3 : 0] M_AXI_GP0_WSTRB;
input M_AXI_GP0_ACLK;
input M_AXI_GP0_ARREADY;
input M_AXI_GP0_AWREADY;
input M_AXI_GP0_BVALID;
input M_AXI_GP0_RLAST;
input M_AXI_GP0_RVALID;
input M_AXI_GP0_WREADY;
input [11 : 0] M_AXI_GP0_BID;
input [11 : 0] M_AXI_GP0_RID;
input [1 : 0] M_AXI_GP0_BRESP;
input [1 : 0] M_AXI_GP0_RRESP;
input [31 : 0] M_AXI_GP0_RDATA;
output FCLK_CLK0;
output FCLK_RESET0_N;
input [53 : 0] MIO;
input DDR_CAS_n;
input DDR_CKE;
input DDR_Clk_n;
input DDR_Clk;
input DDR_CS_n;
input DDR_DRSTB;
input DDR_ODT;
input DDR_RAS_n;
input DDR_WEB;
input [2 : 0] DDR_BankAddr;
input [14 : 0] DDR_Addr;
input DDR_VRN;
input DDR_VRP;
input [3 : 0] DDR_DM;
input [31 : 0] DDR_DQ;
input [3 : 0] DDR_DQS_n;
input [3 : 0] DDR_DQS;
input PS_SRSTB;
input PS_CLK;
input PS_PORB;
processing_system7_bfm_v2_0_5_processing_system7_bfm #(
.C_USE_M_AXI_GP0(1),
.C_USE_M_AXI_GP1(0),
.C_USE_S_AXI_ACP(0),
.C_USE_S_AXI_GP0(0),
.C_USE_S_AXI_GP1(0),
.C_USE_S_AXI_HP0(0),
.C_USE_S_AXI_HP1(0),
.C_USE_S_AXI_HP2(0),
.C_USE_S_AXI_HP3(0),
.C_S_AXI_HP0_DATA_WIDTH(64),
.C_S_AXI_HP1_DATA_WIDTH(64),
.C_S_AXI_HP2_DATA_WIDTH(64),
.C_S_AXI_HP3_DATA_WIDTH(64),
.C_HIGH_OCM_EN(0),
.C_FCLK_CLK0_FREQ(100.0),
.C_FCLK_CLK1_FREQ(50.0),
.C_FCLK_CLK2_FREQ(50.0),
.C_FCLK_CLK3_FREQ(50.0),
.C_M_AXI_GP0_ENABLE_STATIC_REMAP(0),
.C_M_AXI_GP1_ENABLE_STATIC_REMAP(0),
.C_M_AXI_GP0_THREAD_ID_WIDTH (12),
.C_M_AXI_GP1_THREAD_ID_WIDTH (12)
) inst (
.M_AXI_GP0_ARVALID(M_AXI_GP0_ARVALID),
.M_AXI_GP0_AWVALID(M_AXI_GP0_AWVALID),
.M_AXI_GP0_BREADY(M_AXI_GP0_BREADY),
.M_AXI_GP0_RREADY(M_AXI_GP0_RREADY),
.M_AXI_GP0_WLAST(M_AXI_GP0_WLAST),
.M_AXI_GP0_WVALID(M_AXI_GP0_WVALID),
.M_AXI_GP0_ARID(M_AXI_GP0_ARID),
.M_AXI_GP0_AWID(M_AXI_GP0_AWID),
.M_AXI_GP0_WID(M_AXI_GP0_WID),
.M_AXI_GP0_ARBURST(M_AXI_GP0_ARBURST),
.M_AXI_GP0_ARLOCK(M_AXI_GP0_ARLOCK),
.M_AXI_GP0_ARSIZE(M_AXI_GP0_ARSIZE),
.M_AXI_GP0_AWBURST(M_AXI_GP0_AWBURST),
.M_AXI_GP0_AWLOCK(M_AXI_GP0_AWLOCK),
.M_AXI_GP0_AWSIZE(M_AXI_GP0_AWSIZE),
.M_AXI_GP0_ARPROT(M_AXI_GP0_ARPROT),
.M_AXI_GP0_AWPROT(M_AXI_GP0_AWPROT),
.M_AXI_GP0_ARADDR(M_AXI_GP0_ARADDR),
.M_AXI_GP0_AWADDR(M_AXI_GP0_AWADDR),
.M_AXI_GP0_WDATA(M_AXI_GP0_WDATA),
.M_AXI_GP0_ARCACHE(M_AXI_GP0_ARCACHE),
.M_AXI_GP0_ARLEN(M_AXI_GP0_ARLEN),
.M_AXI_GP0_ARQOS(M_AXI_GP0_ARQOS),
.M_AXI_GP0_AWCACHE(M_AXI_GP0_AWCACHE),
.M_AXI_GP0_AWLEN(M_AXI_GP0_AWLEN),
.M_AXI_GP0_AWQOS(M_AXI_GP0_AWQOS),
.M_AXI_GP0_WSTRB(M_AXI_GP0_WSTRB),
.M_AXI_GP0_ACLK(M_AXI_GP0_ACLK),
.M_AXI_GP0_ARREADY(M_AXI_GP0_ARREADY),
.M_AXI_GP0_AWREADY(M_AXI_GP0_AWREADY),
.M_AXI_GP0_BVALID(M_AXI_GP0_BVALID),
.M_AXI_GP0_RLAST(M_AXI_GP0_RLAST),
.M_AXI_GP0_RVALID(M_AXI_GP0_RVALID),
.M_AXI_GP0_WREADY(M_AXI_GP0_WREADY),
.M_AXI_GP0_BID(M_AXI_GP0_BID),
.M_AXI_GP0_RID(M_AXI_GP0_RID),
.M_AXI_GP0_BRESP(M_AXI_GP0_BRESP),
.M_AXI_GP0_RRESP(M_AXI_GP0_RRESP),
.M_AXI_GP0_RDATA(M_AXI_GP0_RDATA),
.M_AXI_GP1_ARVALID(),
.M_AXI_GP1_AWVALID(),
.M_AXI_GP1_BREADY(),
.M_AXI_GP1_RREADY(),
.M_AXI_GP1_WLAST(),
.M_AXI_GP1_WVALID(),
.M_AXI_GP1_ARID(),
.M_AXI_GP1_AWID(),
.M_AXI_GP1_WID(),
.M_AXI_GP1_ARBURST(),
.M_AXI_GP1_ARLOCK(),
.M_AXI_GP1_ARSIZE(),
.M_AXI_GP1_AWBURST(),
.M_AXI_GP1_AWLOCK(),
.M_AXI_GP1_AWSIZE(),
.M_AXI_GP1_ARPROT(),
.M_AXI_GP1_AWPROT(),
.M_AXI_GP1_ARADDR(),
.M_AXI_GP1_AWADDR(),
.M_AXI_GP1_WDATA(),
.M_AXI_GP1_ARCACHE(),
.M_AXI_GP1_ARLEN(),
.M_AXI_GP1_ARQOS(),
.M_AXI_GP1_AWCACHE(),
.M_AXI_GP1_AWLEN(),
.M_AXI_GP1_AWQOS(),
.M_AXI_GP1_WSTRB(),
.M_AXI_GP1_ACLK(1'B0),
.M_AXI_GP1_ARREADY(1'B0),
.M_AXI_GP1_AWREADY(1'B0),
.M_AXI_GP1_BVALID(1'B0),
.M_AXI_GP1_RLAST(1'B0),
.M_AXI_GP1_RVALID(1'B0),
.M_AXI_GP1_WREADY(1'B0),
.M_AXI_GP1_BID(12'B0),
.M_AXI_GP1_RID(12'B0),
.M_AXI_GP1_BRESP(2'B0),
.M_AXI_GP1_RRESP(2'B0),
.M_AXI_GP1_RDATA(32'B0),
.S_AXI_GP0_ARREADY(),
.S_AXI_GP0_AWREADY(),
.S_AXI_GP0_BVALID(),
.S_AXI_GP0_RLAST(),
.S_AXI_GP0_RVALID(),
.S_AXI_GP0_WREADY(),
.S_AXI_GP0_BRESP(),
.S_AXI_GP0_RRESP(),
.S_AXI_GP0_RDATA(),
.S_AXI_GP0_BID(),
.S_AXI_GP0_RID(),
.S_AXI_GP0_ACLK(1'B0),
.S_AXI_GP0_ARVALID(1'B0),
.S_AXI_GP0_AWVALID(1'B0),
.S_AXI_GP0_BREADY(1'B0),
.S_AXI_GP0_RREADY(1'B0),
.S_AXI_GP0_WLAST(1'B0),
.S_AXI_GP0_WVALID(1'B0),
.S_AXI_GP0_ARBURST(2'B0),
.S_AXI_GP0_ARLOCK(2'B0),
.S_AXI_GP0_ARSIZE(3'B0),
.S_AXI_GP0_AWBURST(2'B0),
.S_AXI_GP0_AWLOCK(2'B0),
.S_AXI_GP0_AWSIZE(3'B0),
.S_AXI_GP0_ARPROT(3'B0),
.S_AXI_GP0_AWPROT(3'B0),
.S_AXI_GP0_ARADDR(32'B0),
.S_AXI_GP0_AWADDR(32'B0),
.S_AXI_GP0_WDATA(32'B0),
.S_AXI_GP0_ARCACHE(4'B0),
.S_AXI_GP0_ARLEN(4'B0),
.S_AXI_GP0_ARQOS(4'B0),
.S_AXI_GP0_AWCACHE(4'B0),
.S_AXI_GP0_AWLEN(4'B0),
.S_AXI_GP0_AWQOS(4'B0),
.S_AXI_GP0_WSTRB(4'B0),
.S_AXI_GP0_ARID(6'B0),
.S_AXI_GP0_AWID(6'B0),
.S_AXI_GP0_WID(6'B0),
.S_AXI_GP1_ARREADY(),
.S_AXI_GP1_AWREADY(),
.S_AXI_GP1_BVALID(),
.S_AXI_GP1_RLAST(),
.S_AXI_GP1_RVALID(),
.S_AXI_GP1_WREADY(),
.S_AXI_GP1_BRESP(),
.S_AXI_GP1_RRESP(),
.S_AXI_GP1_RDATA(),
.S_AXI_GP1_BID(),
.S_AXI_GP1_RID(),
.S_AXI_GP1_ACLK(1'B0),
.S_AXI_GP1_ARVALID(1'B0),
.S_AXI_GP1_AWVALID(1'B0),
.S_AXI_GP1_BREADY(1'B0),
.S_AXI_GP1_RREADY(1'B0),
.S_AXI_GP1_WLAST(1'B0),
.S_AXI_GP1_WVALID(1'B0),
.S_AXI_GP1_ARBURST(2'B0),
.S_AXI_GP1_ARLOCK(2'B0),
.S_AXI_GP1_ARSIZE(3'B0),
.S_AXI_GP1_AWBURST(2'B0),
.S_AXI_GP1_AWLOCK(2'B0),
.S_AXI_GP1_AWSIZE(3'B0),
.S_AXI_GP1_ARPROT(3'B0),
.S_AXI_GP1_AWPROT(3'B0),
.S_AXI_GP1_ARADDR(32'B0),
.S_AXI_GP1_AWADDR(32'B0),
.S_AXI_GP1_WDATA(32'B0),
.S_AXI_GP1_ARCACHE(4'B0),
.S_AXI_GP1_ARLEN(4'B0),
.S_AXI_GP1_ARQOS(4'B0),
.S_AXI_GP1_AWCACHE(4'B0),
.S_AXI_GP1_AWLEN(4'B0),
.S_AXI_GP1_AWQOS(4'B0),
.S_AXI_GP1_WSTRB(4'B0),
.S_AXI_GP1_ARID(6'B0),
.S_AXI_GP1_AWID(6'B0),
.S_AXI_GP1_WID(6'B0),
.S_AXI_ACP_ARREADY(),
.S_AXI_ACP_AWREADY(),
.S_AXI_ACP_BVALID(),
.S_AXI_ACP_RLAST(),
.S_AXI_ACP_RVALID(),
.S_AXI_ACP_WREADY(),
.S_AXI_ACP_BRESP(),
.S_AXI_ACP_RRESP(),
.S_AXI_ACP_BID(),
.S_AXI_ACP_RID(),
.S_AXI_ACP_RDATA(),
.S_AXI_ACP_ACLK(1'B0),
.S_AXI_ACP_ARVALID(1'B0),
.S_AXI_ACP_AWVALID(1'B0),
.S_AXI_ACP_BREADY(1'B0),
.S_AXI_ACP_RREADY(1'B0),
.S_AXI_ACP_WLAST(1'B0),
.S_AXI_ACP_WVALID(1'B0),
.S_AXI_ACP_ARID(3'B0),
.S_AXI_ACP_ARPROT(3'B0),
.S_AXI_ACP_AWID(3'B0),
.S_AXI_ACP_AWPROT(3'B0),
.S_AXI_ACP_WID(3'B0),
.S_AXI_ACP_ARADDR(32'B0),
.S_AXI_ACP_AWADDR(32'B0),
.S_AXI_ACP_ARCACHE(4'B0),
.S_AXI_ACP_ARLEN(4'B0),
.S_AXI_ACP_ARQOS(4'B0),
.S_AXI_ACP_AWCACHE(4'B0),
.S_AXI_ACP_AWLEN(4'B0),
.S_AXI_ACP_AWQOS(4'B0),
.S_AXI_ACP_ARBURST(2'B0),
.S_AXI_ACP_ARLOCK(2'B0),
.S_AXI_ACP_ARSIZE(3'B0),
.S_AXI_ACP_AWBURST(2'B0),
.S_AXI_ACP_AWLOCK(2'B0),
.S_AXI_ACP_AWSIZE(3'B0),
.S_AXI_ACP_ARUSER(5'B0),
.S_AXI_ACP_AWUSER(5'B0),
.S_AXI_ACP_WDATA(64'B0),
.S_AXI_ACP_WSTRB(8'B0),
.S_AXI_HP0_ARREADY(),
.S_AXI_HP0_AWREADY(),
.S_AXI_HP0_BVALID(),
.S_AXI_HP0_RLAST(),
.S_AXI_HP0_RVALID(),
.S_AXI_HP0_WREADY(),
.S_AXI_HP0_BRESP(),
.S_AXI_HP0_RRESP(),
.S_AXI_HP0_BID(),
.S_AXI_HP0_RID(),
.S_AXI_HP0_RDATA(),
.S_AXI_HP0_ACLK(1'B0),
.S_AXI_HP0_ARVALID(1'B0),
.S_AXI_HP0_AWVALID(1'B0),
.S_AXI_HP0_BREADY(1'B0),
.S_AXI_HP0_RREADY(1'B0),
.S_AXI_HP0_WLAST(1'B0),
.S_AXI_HP0_WVALID(1'B0),
.S_AXI_HP0_ARBURST(2'B0),
.S_AXI_HP0_ARLOCK(2'B0),
.S_AXI_HP0_ARSIZE(3'B0),
.S_AXI_HP0_AWBURST(2'B0),
.S_AXI_HP0_AWLOCK(2'B0),
.S_AXI_HP0_AWSIZE(3'B0),
.S_AXI_HP0_ARPROT(3'B0),
.S_AXI_HP0_AWPROT(3'B0),
.S_AXI_HP0_ARADDR(32'B0),
.S_AXI_HP0_AWADDR(32'B0),
.S_AXI_HP0_ARCACHE(4'B0),
.S_AXI_HP0_ARLEN(4'B0),
.S_AXI_HP0_ARQOS(4'B0),
.S_AXI_HP0_AWCACHE(4'B0),
.S_AXI_HP0_AWLEN(4'B0),
.S_AXI_HP0_AWQOS(4'B0),
.S_AXI_HP0_ARID(6'B0),
.S_AXI_HP0_AWID(6'B0),
.S_AXI_HP0_WID(6'B0),
.S_AXI_HP0_WDATA(64'B0),
.S_AXI_HP0_WSTRB(8'B0),
.S_AXI_HP1_ARREADY(),
.S_AXI_HP1_AWREADY(),
.S_AXI_HP1_BVALID(),
.S_AXI_HP1_RLAST(),
.S_AXI_HP1_RVALID(),
.S_AXI_HP1_WREADY(),
.S_AXI_HP1_BRESP(),
.S_AXI_HP1_RRESP(),
.S_AXI_HP1_BID(),
.S_AXI_HP1_RID(),
.S_AXI_HP1_RDATA(),
.S_AXI_HP1_ACLK(1'B0),
.S_AXI_HP1_ARVALID(1'B0),
.S_AXI_HP1_AWVALID(1'B0),
.S_AXI_HP1_BREADY(1'B0),
.S_AXI_HP1_RREADY(1'B0),
.S_AXI_HP1_WLAST(1'B0),
.S_AXI_HP1_WVALID(1'B0),
.S_AXI_HP1_ARBURST(2'B0),
.S_AXI_HP1_ARLOCK(2'B0),
.S_AXI_HP1_ARSIZE(3'B0),
.S_AXI_HP1_AWBURST(2'B0),
.S_AXI_HP1_AWLOCK(2'B0),
.S_AXI_HP1_AWSIZE(3'B0),
.S_AXI_HP1_ARPROT(3'B0),
.S_AXI_HP1_AWPROT(3'B0),
.S_AXI_HP1_ARADDR(32'B0),
.S_AXI_HP1_AWADDR(32'B0),
.S_AXI_HP1_ARCACHE(4'B0),
.S_AXI_HP1_ARLEN(4'B0),
.S_AXI_HP1_ARQOS(4'B0),
.S_AXI_HP1_AWCACHE(4'B0),
.S_AXI_HP1_AWLEN(4'B0),
.S_AXI_HP1_AWQOS(4'B0),
.S_AXI_HP1_ARID(6'B0),
.S_AXI_HP1_AWID(6'B0),
.S_AXI_HP1_WID(6'B0),
.S_AXI_HP1_WDATA(64'B0),
.S_AXI_HP1_WSTRB(8'B0),
.S_AXI_HP2_ARREADY(),
.S_AXI_HP2_AWREADY(),
.S_AXI_HP2_BVALID(),
.S_AXI_HP2_RLAST(),
.S_AXI_HP2_RVALID(),
.S_AXI_HP2_WREADY(),
.S_AXI_HP2_BRESP(),
.S_AXI_HP2_RRESP(),
.S_AXI_HP2_BID(),
.S_AXI_HP2_RID(),
.S_AXI_HP2_RDATA(),
.S_AXI_HP2_ACLK(1'B0),
.S_AXI_HP2_ARVALID(1'B0),
.S_AXI_HP2_AWVALID(1'B0),
.S_AXI_HP2_BREADY(1'B0),
.S_AXI_HP2_RREADY(1'B0),
.S_AXI_HP2_WLAST(1'B0),
.S_AXI_HP2_WVALID(1'B0),
.S_AXI_HP2_ARBURST(2'B0),
.S_AXI_HP2_ARLOCK(2'B0),
.S_AXI_HP2_ARSIZE(3'B0),
.S_AXI_HP2_AWBURST(2'B0),
.S_AXI_HP2_AWLOCK(2'B0),
.S_AXI_HP2_AWSIZE(3'B0),
.S_AXI_HP2_ARPROT(3'B0),
.S_AXI_HP2_AWPROT(3'B0),
.S_AXI_HP2_ARADDR(32'B0),
.S_AXI_HP2_AWADDR(32'B0),
.S_AXI_HP2_ARCACHE(4'B0),
.S_AXI_HP2_ARLEN(4'B0),
.S_AXI_HP2_ARQOS(4'B0),
.S_AXI_HP2_AWCACHE(4'B0),
.S_AXI_HP2_AWLEN(4'B0),
.S_AXI_HP2_AWQOS(4'B0),
.S_AXI_HP2_ARID(6'B0),
.S_AXI_HP2_AWID(6'B0),
.S_AXI_HP2_WID(6'B0),
.S_AXI_HP2_WDATA(64'B0),
.S_AXI_HP2_WSTRB(8'B0),
.S_AXI_HP3_ARREADY(),
.S_AXI_HP3_AWREADY(),
.S_AXI_HP3_BVALID(),
.S_AXI_HP3_RLAST(),
.S_AXI_HP3_RVALID(),
.S_AXI_HP3_WREADY(),
.S_AXI_HP3_BRESP(),
.S_AXI_HP3_RRESP(),
.S_AXI_HP3_BID(),
.S_AXI_HP3_RID(),
.S_AXI_HP3_RDATA(),
.S_AXI_HP3_ACLK(1'B0),
.S_AXI_HP3_ARVALID(1'B0),
.S_AXI_HP3_AWVALID(1'B0),
.S_AXI_HP3_BREADY(1'B0),
.S_AXI_HP3_RREADY(1'B0),
.S_AXI_HP3_WLAST(1'B0),
.S_AXI_HP3_WVALID(1'B0),
.S_AXI_HP3_ARBURST(2'B0),
.S_AXI_HP3_ARLOCK(2'B0),
.S_AXI_HP3_ARSIZE(3'B0),
.S_AXI_HP3_AWBURST(2'B0),
.S_AXI_HP3_AWLOCK(2'B0),
.S_AXI_HP3_AWSIZE(3'B0),
.S_AXI_HP3_ARPROT(3'B0),
.S_AXI_HP3_AWPROT(3'B0),
.S_AXI_HP3_ARADDR(32'B0),
.S_AXI_HP3_AWADDR(32'B0),
.S_AXI_HP3_ARCACHE(4'B0),
.S_AXI_HP3_ARLEN(4'B0),
.S_AXI_HP3_ARQOS(4'B0),
.S_AXI_HP3_AWCACHE(4'B0),
.S_AXI_HP3_AWLEN(4'B0),
.S_AXI_HP3_AWQOS(4'B0),
.S_AXI_HP3_ARID(6'B0),
.S_AXI_HP3_AWID(6'B0),
.S_AXI_HP3_WID(6'B0),
.S_AXI_HP3_WDATA(64'B0),
.S_AXI_HP3_WSTRB(8'B0),
.FCLK_CLK0(FCLK_CLK0),
.FCLK_CLK1(),
.FCLK_CLK2(),
.FCLK_CLK3(),
.FCLK_RESET0_N(FCLK_RESET0_N),
.FCLK_RESET1_N(),
.FCLK_RESET2_N(),
.FCLK_RESET3_N(),
.IRQ_F2P(16'B0),
.PS_SRSTB(PS_SRSTB),
.PS_CLK(PS_CLK),
.PS_PORB(PS_PORB)
);
endmodule
|
module map9v3(clock, reset, start, N, dp, done, counter, sr);
input clock;
input start; // run at rising edge of start
input reset; // high is reset case ( run after reset)
input [8:0] N; // the number to divide by
output [8:0] dp; // these outputs drive an LFSR counter
output done;
output [7:0] counter;
output [7:0] sr;
reg [8:0] dp;
reg [7:0] sr;
reg [7:0] counter;
reg [1:0] startbuf;
reg done;
reg [2:0] state;
parameter INIT = 3'b000;
parameter RUN = 3'b001;
parameter ALMOSTDONE = 3'b010;
parameter DONE = 3'b011;
parameter WAIT = 3'b100;
always @(posedge clock or posedge reset) begin
if (reset == 1) begin
dp <= 9'b0;
sr <= 8'b0;
counter <= 8'b0;
startbuf <= 2'b00;
done <= 0;
state <= INIT;
end else begin
if (state == INIT) begin
counter <= 255 - N[8:1] + 3;
sr <= 8'b0;
done <= 0;
state <= RUN;
end else if (state == RUN) begin
sr[7] <= sr[6];
sr[6] <= sr[5];
sr[5] <= sr[4];
sr[4] <= sr[3];
sr[3] <= sr[2];
sr[2] <= sr[1];
sr[1] <= sr[0];
sr[0] <= ~(sr[7] ^ sr[5] ^ sr[4] ^ sr[3]);
counter <= counter - 1;
if (counter == 0) begin
state <= ALMOSTDONE;
end
end else if (state == ALMOSTDONE) begin
dp[0] <= N[0];
dp[8:1] <= sr[7:0];
state <= DONE;
end else if (state == DONE) begin
done <= 1;
state <= WAIT;
end else if (state == WAIT) begin
if (startbuf == 2'b01) begin
state <= INIT;
end
end
startbuf <= {startbuf[0], start};
end
end
endmodule
|
module plus_data_flow_fixture;
// Inputs
reg [3:0] a;
reg [3:0] b;
reg cin;
// Outputs
wire [3:0] q;
wire cout;
// Instantiate the Unit Under Test (UUT)
plus_data_flow uut (
.q(q),
.cout(cout),
.a(a),
.b(b),
.cin(cin)
);
initial begin
// Initialize Inputs
a = 0;
b = 0;
cin = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
end
endmodule
|
module jhash_in(/*AUTOARG*/
// Outputs
m_src_getn, stream_data0, stream_data1, stream_data2,
stream_valid, stream_done, stream_left,
// Inputs
ce, clk, fi, fo_full, m_last, rst, src_empty, stream_ack
);
input ce;
input clk;
input [63:0] fi;
input fo_full;
input m_last;
input rst;
input src_empty;
output m_src_getn;
input stream_ack;
output [31:0] stream_data0,
stream_data1,
stream_data2;
output stream_valid;
output stream_done;
output [1:0] stream_left;
/*AUTOREG*/
reg pull_n;
assign m_src_getn = ce ? ~(pull_n) : 1'bz;
reg [31:0] stream_data0_n,
stream_data1_n,
stream_data2_n;
reg [2:0] state,
state_n;
reg stream_valid_n;
parameter [2:0]
S_IDLE = 3'b100,
S_RUN_01 = 3'b001,
S_RUN_01_N= 3'b101,
S_RUN_10 = 3'b010,
S_RUN_10_N= 3'b110,
S_DONE = 3'b111;
always @(posedge clk or posedge rst)
begin
if (rst)
state <= #1 S_IDLE;
else
state <= #1 state_n;
end
reg [1:0] dstart, dstart_n;
reg [31:0] d0, d1,
d0_n, d1_n;
always @(posedge clk)
begin
d0 <= #1 d0_n;
d1 <= #1 d1_n;
dstart <= #1 dstart_n;
end
always @(/*AS*/ce or d0 or d1 or dstart or fi or m_last
or src_empty or state or stream_ack)
begin
state_n = state;
pull_n = 1'b0;
d0_n = d0;
d1_n = d1;
dstart_n = dstart;
case (state)
S_IDLE: if (~src_empty && ce) begin
d0_n = fi[31:00];
d1_n = fi[63:32];
pull_n = 1'b1;
dstart_n= 2'b10;
state_n = S_RUN_10;
end
S_RUN_10_N: if (m_last)
state_n = S_DONE;
else if (~src_empty) begin
d0_n = fi[31:00];
d1_n = fi[63:32];
pull_n = 1'b1;
dstart_n= 2'b10;
state_n = S_RUN_10;
end
S_RUN_10: if (stream_ack) begin
if (~src_empty && ~m_last) begin
d0_n = fi[63:32];
pull_n = 1'b1;
dstart_n = 2'b01;
state_n = S_RUN_01;
end else
state_n = S_RUN_01_N;
end
S_RUN_01_N: if (m_last)
state_n = S_DONE;
else if (~src_empty) begin
d0_n = fi[63:32];
pull_n = 1'b1;
dstart_n = 2'b01;
state_n = S_RUN_01;
end
S_RUN_01: if (stream_ack) begin
if (~src_empty && ~m_last) begin
state_n = S_RUN_10_N;
pull_n = 1'b1;
end if (m_last)
state_n = S_DONE;
end
S_DONE: ;
endcase
end // always @ (...
assign stream_left = dstart;
assign stream_valid= ~state[2] && ~src_empty;
assign stream_data0= d0;
assign stream_data1= state[1] ? d1 : fi[31:00];
assign stream_data2= state[1] ? fi[31:0]: fi[63:32];
assign stream_done = m_last;
endmodule
|
module
reg drun_rd;
reg drun_wr; //3 cycles ahead of data out available inside FPGA (before DDR resyncing)
reg dlast;
reg dqs_re;
// internals
reg [24:3] fullAddr; // full SDRAM address;
reg [24:3] nextAddr; // full SDRAM address for the next 10-word block (in next line)
// reg [24:9] nextPageAddr; // used only for the the second access in mode1
reg [24:10] nextPageAddr; // used only for the the second access in mode1
reg start_m1; // start in mode1 - both first and next lines
reg startf_m1; // start in mode1 - only first line !
reg start_m0r; // start in mode0 - read
reg start_m0w; // start in mode0 - write
// wire pre6prech_m; // 6 cycles ahead of precmd "precharge" mode1, single access or second in dual
reg pre6prech_m; // 6 cycles ahead of precmd "precharge" mode1, single access or second in dual
reg [1:0] pre7prech_m; // 7 cycles ahead of precmd "precharge", [0] - read, [1] - write
wire pre2prech_m; // 2 cycles ahead of precmd "precharge" mode1, single access or second in dual
wire pre2prech_m1d1; // 2 cycles ahead of precmd "precharge" mode1, dual access, first cycle
wire pre2act_m1d2; // 2 cycles ahead of precmd "activate" mode1, dual access, second cycle
wire prenext_m1s; // 1 cycle ahead of possible "next" - mode1, single access - starts from start_m1
wire prenext_m1d; // 1 cycle ahead of possible "next" - mode1, dual access
wire precontinue_m1; // 3 cycles ahead of "activate" of continuation cycle
reg continue_m1; // 2 cycles ahead of "activate" of continuation cycle
wire continue_m0; // 2 cycles ahead of "activate" of continuation cycle
reg possible_dual; // lower bits in full address are all ones - possible two acccesses will be needed in the current line
reg setNextAddr; // update nextAddr
reg decLeft;
wire prenext_m0r;
wire prenext_m0w1;
wire prenext_m0;
wire pre2refr;
wire prenext_refr;
reg prerefr;
reg preact;
reg preprech;
reg preread;
reg prewrite;
reg prerw; // for address multiplexor
reg pre1act_m1d2;
wire pre2read;
wire pre2write;
reg predrun_wr;
reg pre4drun_rd;
wire predrun_rd;
wire pre4drun_rd_abort; // in second access of dual-access, where precharge command is later (to meet activate-to-precharge time)
wire predrun_wr_abort; // write nneeds extra NOP befrore precharge
wire predmask;
wire predlast_rd;
wire predlast_wr;
wire predqs_re;
reg repeat_r;
wire repeat_r_end;
reg repeat_w;
wire pre2read_next8;
wire pre2write_next8;
reg prefirstdrun; // to sample cs in bufCntr256
wire pre2firstdrun_rd;
reg rollover; //photofinish hack
reg prenext_wr; // same timing as it was "next" earlier
wire pre_next_old=(left==5'h1) && (prenext_m1s || prenext_m1d || prenext_m0);
always @ (negedge clk0)
if (rst) begin
mode_r <= 1'b0;
end else if (xfer) begin
mode_r <= mode;
end
always @ (negedge clk0) begin
rollover <= (left[4:0]==5'h4) && rovr;
if (first) fullAddr[ 9:3] <= sa[ 9:3];
else if (pre2act_m1d2) fullAddr[ 9:3] <= 7'h0;
else if (prerw) fullAddr[ 9:3] <= fullAddr[ 9:3]+1;
else if (continue_m1) fullAddr[ 9:3] <= {rollover?sfa[9:8]:nextAddr[9:8],nextAddr[ 7:3]}; // stored from sa[7:3]
if (first) fullAddr[24:10] <= sa[24:10];
else if (continue_m1) fullAddr[24:10] <= rollover?sfa[24:10]:nextAddr[24:10];
else if (pre2act_m1d2) fullAddr[24:10] <= nextPageAddr[24:10];
if (pre2prech_m1d1) nextPageAddr[24:10] <= fullAddr[24:10]+1;
if (rst) possible_dual <= 0;
else if (first) possible_dual <= (sa[ 7:3] == 5'h1f);
start_m1 <= !rst && ((first && mode_r) || continue_m1);
startf_m1 <= !rst && (first && mode_r);
start_m0r <= first && !mode_r && !wnr;
start_m0w <= first && !mode_r && wnr;
setNextAddr <= start_m1;
if (setNextAddr) nextAddr[24:8] <= fullAddr[24:8]+param[5:0]; // 2 cycles after fullAddr was set
if (first) nextAddr[ 7:3] <= sa [7:3];
prenext_wr <= drun_wr && pre_next_old;
next <= prenext_refr || prenext_wr || (!drun_wr && pre_next_old); // add m0 and refr here too
decLeft <= (prenext_m1s || prenext_m1d || prenext_m0); // add m0 and refr here too
if (first) left[4:0] <= (mode)? 5'h14:((param[4:0]==5'b0)?5'h1f:param[4:0]);
else if (decLeft) left[4:0] <= left[4:0] -1;
end
// aHa! Here was the bug!!
// MSRL16_1 i_prenext_m1s (.Q(prenext_m1s), .A(4'h0), .CLK(clk0), .D(start_m1 && ~(possible_dual && fullAddr[8])));
MSRL16_1 i_prenext_m1s (.Q(prenext_m1s), .A(4'h0), .CLK(clk0), .D(start_m1 && ~(possible_dual && &fullAddr[9:8])));
// modified to match tWR (delay precharge after write)
// MSRL16_1 i_pre6prech_m (.Q(pre6prech_m), .A(4'h1), .CLK(clk0), .D(prenext_m1s ||
// prenext_m1d ||
// ((left==5'h1) && prenext_m0)));
MSRL16_1 i_pre2prech_m (.Q(pre2prech_m), .A(4'h3), .CLK(clk0), .D(pre6prech_m));
// MSRL16_1 i_pre2prech_m1d1 (.Q(pre2prech_m1d1), .A(4'h5), .CLK(clk0), .D(start_m1 && (possible_dual && fullAddr[8])));
MSRL16_1 i_pre2prech_m1d1 (.Q(pre2prech_m1d1), .A(4'h5), .CLK(clk0), .D(start_m1 && (possible_dual && &fullAddr[9:8])));
MSRL16_1 i_prenext_m1d (.Q(prenext_m1d), .A(4'h1), .CLK(clk0), .D(pre2prech_m1d1));
MSRL16_1 i_pre2act_m1d2 (.Q(pre2act_m1d2), .A(4'h0), .CLK(clk0), .D(prenext_m1d));
MSRL16_1 i_precontinue_m1 (.Q(precontinue_m1), .A(4'h1), .CLK(clk0), .D((left!=5'h0) && pre2prech_m));
MSRL16_1 i_prenext_m0r (.Q(prenext_m0r), .A((param[4:0]==5'b0)?4'h3:4'h0), .CLK(clk0), .D(start_m0r));
MSRL16_1 i_prenext_m0w1 (.Q(prenext_m0w1), .A((param[4:0]==5'b0)?4'h6:4'h3), .CLK(clk0), .D(start_m0w));
assign prenext_m0=prenext_m0r || prenext_m0w1 || continue_m0;
MSRL16_1 i_continue_m0 (.Q(continue_m0), .A(4'h3), .CLK(clk0), .D(!rst && (left!=5'h1) && prenext_m0));
MSRL16_1 i_pre2refr (.Q(pre2refr), .A(4'h6), .CLK(clk0), .D(refr));
MSRL16_1 i_prenext_refr (.Q(prenext_refr), .A(4'h2), .CLK(clk0), .D(pre2refr));
// secondary signals (just delays from the primary ones)
MSRL16_1 i_pre2read (.Q(pre2read), .A(4'h1), .CLK(clk0), .D(start_m0r || start_m1 || pre1act_m1d2));
MSRL16_1 i_pre2write (.Q(pre2write), .A(4'h1), .CLK(clk0), .D(start_m0w));
MSRL16_1 i_predrun_rd (.Q(predrun_rd), .A(4'h2), .CLK(clk0), .D(pre4drun_rd));
MSRL16_1 i_pre4drun_rd_abort (.Q(pre4drun_rd_abort), .A(4'h4), .CLK(clk0), .D(pre2act_m1d2));
MSRL16_1 i_predrun_wr_abort (.Q(predrun_wr_abort), .A(4'h0), .CLK(clk0), .D((prenext_m0w1 || continue_m0) && (left==5'h1)));
MSRL16_1 i_predlast_rd (.Q(predlast_rd), .A(4'h2), .CLK(clk0), .D(pre4drun_rd && (preprech || pre4drun_rd_abort)));
MSRL16_1 i_predlast_wr (.Q(predlast_wr), .A(4'h0), .CLK(clk0), .D(predrun_wr && predrun_wr_abort));
MSRL16_1 i_predmask (.Q(predmask), .A(4'h2), .CLK(clk0), .D(!predrun_wr));
MSRL16_1 i_predqs_re (.Q(predqs_re), .A(4'h1), .CLK(clk0), .D(pre4drun_rd));
MSRL16_1 i_pre2read_next8 (.Q(pre2read_next8), .A(4'h2), .CLK(clk0), .D(preread));
MSRL16_1 i_pre2write_next8 (.Q(pre2write_next8), .A(4'h2), .CLK(clk0), .D(prewrite));
assign repeat_r_end= pre2prech_m || pre2prech_m1d1; // will work for read - add for write
MSRL16_1 i_pre2firstdrun_rd (.Q(pre2firstdrun_rd), .A(4'h5), .CLK(clk0), .D(start_m0r || startf_m1));
always @ (negedge clk0) begin
pre7prech_m[1:0] <= {pre7prech_m[0],prenext_m1s ||
prenext_m1d ||
(prenext_m0 && (left==5'h1))};
pre6prech_m <= drun_wr?pre7prech_m[1]:pre7prech_m[0];
prefirstdrun <= start_m0w || pre2firstdrun_rd;
continue_m1 <= precontinue_m1;
repeat_r <= !rst && !repeat_r_end && (repeat_r || first || continue_m1);
repeat_w <= !rst && !pre6prech_m && (repeat_w || first);
prefirst <= xfer;
first <= prefirst;
pre1act_m1d2 <= !rst && pre2act_m1d2;
prerefr <= !rst && pre2refr;
preact <= !rst && (first || continue_m1 || pre2act_m1d2);
preprech <= !rst && (pre2prech_m || pre2prech_m1d1);
preread <= !rst && ~(pre2prech_m || pre2prech_m1d1) && (pre2read || (pre2read_next8 && repeat_r));
prewrite <= !rst && (pre2write || (pre2write_next8 && repeat_w));
prerw <= (~(pre2prech_m || pre2prech_m1d1) && (pre2read || (pre2read_next8 && repeat_r))) ||
(pre2write || (pre2write_next8 && repeat_w));
// prea[12:0] <= rst? mancmd[12:0] : (prerw? {4'b0,fullAddr[8:3],3'b0} :(first?sa[21:9] :fullAddr[21:9]));
// preb[ 1:0] <= rst? mancmd[14:13] : (first?sa[23:22]:fullAddr[23:22]);
prea[12:0] <= rst?
mancmd[12:0] :
(prerw?
{3'b0,fullAddr[9:3],3'b0} :
(first?
sa[22:10] :
fullAddr[22:10]));
preb[ 1:0] <= rst?
mancmd[14:13] :
(first?
sa[24:23]:
fullAddr[24:23]);
if (start_m0w) dsel[1:0] <= chsel[1:0];
predrun_wr <= start_m0w || (!rst && predrun_wr && ~predrun_wr_abort);
pre4drun_rd <= preread || (!rst && pre4drun_rd && ~(preprech || pre4drun_rd_abort));
drun_rd <= predrun_rd;
drun_wr <= predrun_wr;
dlast <= (left==5'h0 ) && (predlast_rd || predlast_wr) && !pre1act_m1d2; // !pre1act_m1d2 removes first pulse in dual access lines
dmask <={predmask,predmask};
pre2trist<=rst || preprech || (pre2trist && ~prewrite);
predqt <=rst || (pre2trist && ~prewrite);
dqs_re <=predqs_re;
end
// Use FF for cas, ras, we for correct simulation
FD_1 #(.INIT(1'b1)) i_precmd_0 (.D(mancmd[15] && ~(prewrite | preprech)), .C(clk0),.Q(precmd[0])); //WE
FD_1 #(.INIT(1'b1)) i_precmd_1 (.D(mancmd[16] && ~(prerefr | preread | prewrite)),.C(clk0),.Q(precmd[1])); //CAS
FD_1 #(.INIT(1'b1)) i_precmd_2 (.D(mancmd[17] && ~(prerefr | preact | preprech)), .C(clk0),.Q(precmd[2])); //RAS
endmodule
|
module IceBreaker (nreset,
clk12Mhz,
extInt,
leds,
pwmLeds,
pButtons,
pmodA,
rx,
tx,
uartLed);
// Input ports
input nreset;
input clk12Mhz;
input [0:0] extInt;
input [1:0] pButtons;
input rx;
// Output ports
output [3:0] leds;
output [0:0] pwmLeds;
output tx;
output uartLed;
// Bidirectional port
inout [7:0] pmodA;
// Clock generation
wire boardClk;
wire boardClkLocked;
// Internal wiring
wire [7:0] pmodA_read;
wire [7:0] pmodA_write;
wire [7:0] pmodA_writeEnable;
// Internal wire for reset
wire reset;
// Instantiate a PLL to make a 18Mhz clock
PLL makeClk (.clkIn (clk12Mhz),
.clkOut (boardClk),
.isLocked (boardClkLocked));
// Instantiate the J1SoC core generated by Spinal
J1Ice core (.reset (reset),
.boardClk (boardClk),
.boardClkLocked (boardClkLocked),
.extInt (extInt),
.leds (leds),
.pwmLeds (pwmLeds),
.pButtons (pButtons),
.pmodA_read (pmodA_read),
.pmodA_write (pmodA_write),
.pmodA_writeEnable (pmodA_writeEnable),
.rx (rx),
.tx (tx),
.uartLed (uartLed));
// Invert the negative reset
assign reset = !nreset;
// Generate the write port and equip it with tristate functionality
genvar i;
generate
for (i = 0; i < 8; i = i + 1) begin
// Instantiate the ith tristate buffer
SB_IO #(.PIN_TYPE(6'b 1010_01),
.PULLUP(1'b 0)
) iobuf (
.PACKAGE_PIN(pmodA[i]),
.OUTPUT_ENABLE(pmodA_writeEnable[i]),
.D_OUT_0(pmodA_write[i]),
.D_IN_0(pmodA_read[i]));
end
endgenerate
endmodule
|
module sounds_module(input lrck, input reset, input[2:0] sound_code,
output reg[15:0] left_data, output reg[15:0] right_data);
/** Variable para recorrer el arreglo de la data de cada sonido */
reg [2:0] position;
/** Matriz que contiene los datos de un sonido */
parameter [15:0] sample_sound_left [2:0];
parameter [15:0] sample_sound_right [2:0];
initial
begin
/** Position empieza en cero */
position <= 1;
/** Se debe guardar los datos de los sonidos */
sample_sound_left[0] <= 16'd1;
sample_sound_right[0] <= 16'd2;
sample_sound_left[1] <= 16'd3;
sample_sound_right[1] <= 16'd4;
sample_sound_left[2] <= 16'd5;
sample_sound_right[2] <= 16'd6;
end
always @ (negedge lrck)
begin
case(sound_code)
3'b000:
begin
left_data <= sample_sound_left[position];
right_data <= sample_sound_right[position];
end
default:
begin
left_data <= sample_sound_left[position];
right_data <= sample_sound_right[position];
end
endcase
position <= position + 1;
end
endmodule
|
module sky130_fd_sc_hdll__nor4b_1 (
Y ,
A ,
B ,
C ,
D_N ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input C ;
input D_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__nor4b base (
.Y(Y),
.A(A),
.B(B),
.C(C),
.D_N(D_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
|
module sky130_fd_sc_hdll__nor4b_1 (
Y ,
A ,
B ,
C ,
D_N
);
output Y ;
input A ;
input B ;
input C ;
input D_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__nor4b base (
.Y(Y),
.A(A),
.B(B),
.C(C),
.D_N(D_N)
);
endmodule
|
module top();
// Inputs are registered
reg D;
reg SCD;
reg SCE;
reg VPWR;
reg VGND;
// Outputs are wires
wire Q;
wire Q_N;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
SCD = 1'bX;
SCE = 1'bX;
VGND = 1'bX;
VPWR = 1'bX;
#20 D = 1'b0;
#40 SCD = 1'b0;
#60 SCE = 1'b0;
#80 VGND = 1'b0;
#100 VPWR = 1'b0;
#120 D = 1'b1;
#140 SCD = 1'b1;
#160 SCE = 1'b1;
#180 VGND = 1'b1;
#200 VPWR = 1'b1;
#220 D = 1'b0;
#240 SCD = 1'b0;
#260 SCE = 1'b0;
#280 VGND = 1'b0;
#300 VPWR = 1'b0;
#320 VPWR = 1'b1;
#340 VGND = 1'b1;
#360 SCE = 1'b1;
#380 SCD = 1'b1;
#400 D = 1'b1;
#420 VPWR = 1'bx;
#440 VGND = 1'bx;
#460 SCE = 1'bx;
#480 SCD = 1'bx;
#500 D = 1'bx;
end
// Create a clock
reg CLK;
initial
begin
CLK = 1'b0;
end
always
begin
#5 CLK = ~CLK;
end
sky130_fd_sc_hs__sdfxbp dut (.D(D), .SCD(SCD), .SCE(SCE), .VPWR(VPWR), .VGND(VGND), .Q(Q), .Q_N(Q_N), .CLK(CLK));
endmodule
|
module sky130_fd_sc_lp__nand4bb (
//# {{data|Data Signals}}
input A_N,
input B_N,
input C ,
input D ,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
|
module convolve_kernel_fbkb
#(parameter
ID = 0,
NUM_STAGE = 5,
din0_WIDTH = 32,
din1_WIDTH = 32,
dout_WIDTH = 32
)(
input wire clk,
input wire reset,
input wire ce,
input wire [din0_WIDTH-1:0] din0,
input wire [din1_WIDTH-1:0] din1,
output wire [dout_WIDTH-1:0] dout
);
//------------------------Local signal-------------------
wire aclk;
wire aclken;
wire a_tvalid;
wire [31:0] a_tdata;
wire b_tvalid;
wire [31:0] b_tdata;
wire r_tvalid;
wire [31:0] r_tdata;
reg [din0_WIDTH-1:0] din0_buf1;
reg [din1_WIDTH-1:0] din1_buf1;
//------------------------Instantiation------------------
convolve_kernel_ap_fadd_3_full_dsp_32 convolve_kernel_ap_fadd_3_full_dsp_32_u (
.aclk ( aclk ),
.aclken ( aclken ),
.s_axis_a_tvalid ( a_tvalid ),
.s_axis_a_tdata ( a_tdata ),
.s_axis_b_tvalid ( b_tvalid ),
.s_axis_b_tdata ( b_tdata ),
.m_axis_result_tvalid ( r_tvalid ),
.m_axis_result_tdata ( r_tdata )
);
//------------------------Body---------------------------
assign aclk = clk;
assign aclken = ce;
assign a_tvalid = 1'b1;
assign a_tdata = din0_buf1;
assign b_tvalid = 1'b1;
assign b_tdata = din1_buf1;
assign dout = r_tdata;
always @(posedge clk) begin
if (ce) begin
din0_buf1 <= din0;
din1_buf1 <= din1;
end
end
endmodule
|
module red_pitaya_hk #(
parameter DWL = 8, // data width for LED
parameter DWE = 8, // data width for extension
parameter [57-1:0] DNA = 57'h0823456789ABCDE
)(
// system signals
input clk_i , // clock
input rstn_i , // reset - active low
// LED
output reg [DWL-1:0] led_o , // LED output
// global configuration
output reg digital_loop,
// Expansion connector
input [DWE-1:0] exp_p_dat_i, // exp. con. input data
output reg [DWE-1:0] exp_p_dat_o, // exp. con. output data
output reg [DWE-1:0] exp_p_dir_o, // exp. con. 1-output enable
input [DWE-1:0] exp_n_dat_i, //
output reg [DWE-1:0] exp_n_dat_o, //
output reg [DWE-1:0] exp_n_dir_o, //
// System bus
input [ 32-1:0] sys_addr , // bus address
input [ 32-1:0] sys_wdata , // bus write data
input [ 4-1:0] sys_sel , // bus write byte select
input sys_wen , // bus write enable
input sys_ren , // bus read enable
output reg [ 32-1:0] sys_rdata , // bus read data
output reg sys_err , // bus error indicator
output reg sys_ack // bus acknowledge signal
);
//---------------------------------------------------------------------------------
//
// Read device DNA
wire dna_dout ;
reg dna_clk ;
reg dna_read ;
reg dna_shift;
reg [ 9-1: 0] dna_cnt ;
reg [57-1: 0] dna_value;
reg dna_done ;
always @(posedge clk_i)
if (rstn_i == 1'b0) begin
dna_clk <= 1'b0;
dna_read <= 1'b0;
dna_shift <= 1'b0;
dna_cnt <= 9'd0;
dna_value <= 57'd0;
dna_done <= 1'b0;
end else begin
if (!dna_done)
dna_cnt <= dna_cnt + 1'd1;
dna_clk <= dna_cnt[2] ;
dna_read <= (dna_cnt < 9'd10);
dna_shift <= (dna_cnt > 9'd18);
if ((dna_cnt[2:0]==3'h0) && !dna_done)
dna_value <= {dna_value[57-2:0], dna_dout};
if (dna_cnt > 9'd465)
dna_done <= 1'b1;
end
// parameter specifies a sample 57-bit DNA value for simulation
DNA_PORT #(.SIM_DNA_VALUE (DNA)) i_DNA (
.DOUT ( dna_dout ), // 1-bit output: DNA output data.
.CLK ( dna_clk ), // 1-bit input: Clock input.
.DIN ( 1'b0 ), // 1-bit input: User data input pin.
.READ ( dna_read ), // 1-bit input: Active high load DNA, active low read input.
.SHIFT ( dna_shift ) // 1-bit input: Active high shift enable input.
);
//---------------------------------------------------------------------------------
//
// Design identification
wire [32-1: 0] id_value;
assign id_value[31: 4] = 28'h0; // reserved
assign id_value[ 3: 0] = 4'h1; // board type 1 - release 1
//---------------------------------------------------------------------------------
//
// System bus connection
always @(posedge clk_i)
if (rstn_i == 1'b0) begin
led_o <= {DWL{1'b0}};
exp_p_dat_o <= {DWE{1'b0}};
exp_p_dir_o <= {DWE{1'b0}};
exp_n_dat_o <= {DWE{1'b0}};
exp_n_dir_o <= {DWE{1'b0}};
end else if (sys_wen) begin
if (sys_addr[19:0]==20'h0c) digital_loop <= sys_wdata[0];
if (sys_addr[19:0]==20'h10) exp_p_dir_o <= sys_wdata[DWE-1:0];
if (sys_addr[19:0]==20'h14) exp_n_dir_o <= sys_wdata[DWE-1:0];
if (sys_addr[19:0]==20'h18) exp_p_dat_o <= sys_wdata[DWE-1:0];
if (sys_addr[19:0]==20'h1C) exp_n_dat_o <= sys_wdata[DWE-1:0];
if (sys_addr[19:0]==20'h30) led_o <= sys_wdata[DWL-1:0];
end
wire sys_en;
assign sys_en = sys_wen | sys_ren;
always @(posedge clk_i)
if (rstn_i == 1'b0) begin
sys_err <= 1'b0;
sys_ack <= 1'b0;
end else begin
sys_err <= 1'b0;
casez (sys_addr[19:0])
20'h00000: begin sys_ack <= sys_en; sys_rdata <= { id_value }; end
20'h00004: begin sys_ack <= sys_en; sys_rdata <= { dna_value[32-1: 0]}; end
20'h00008: begin sys_ack <= sys_en; sys_rdata <= {{64- 57{1'b0}}, dna_value[57-1:32]}; end
20'h0000c: begin sys_ack <= sys_en; sys_rdata <= {{32- 1{1'b0}}, digital_loop }; end
20'h00010: begin sys_ack <= sys_en; sys_rdata <= {{32-DWE{1'b0}}, exp_p_dir_o} ; end
20'h00014: begin sys_ack <= sys_en; sys_rdata <= {{32-DWE{1'b0}}, exp_n_dir_o} ; end
20'h00018: begin sys_ack <= sys_en; sys_rdata <= {{32-DWE{1'b0}}, exp_p_dat_o} ; end
20'h0001C: begin sys_ack <= sys_en; sys_rdata <= {{32-DWE{1'b0}}, exp_n_dat_o} ; end
20'h00020: begin sys_ack <= sys_en; sys_rdata <= {{32-DWE{1'b0}}, exp_p_dat_i} ; end
20'h00024: begin sys_ack <= sys_en; sys_rdata <= {{32-DWE{1'b0}}, exp_n_dat_i} ; end
20'h00030: begin sys_ack <= sys_en; sys_rdata <= {{32-DWL{1'b0}}, led_o} ; end
default: begin sys_ack <= sys_en; sys_rdata <= 32'h0 ; end
endcase
end
endmodule
|
module sky130_fd_sc_hd__lpflow_clkbufkapwr (
X ,
A ,
KAPWR,
VPWR ,
VGND ,
VPB ,
VNB
);
output X ;
input A ;
input KAPWR;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
endmodule
|
module raminfr
(clk, we, a, dpra, di, dpo);
parameter addr_width = 4;
parameter data_width = 8;
parameter depth = 16;
input clk;
input we;
input [addr_width-1:0] a;
input [addr_width-1:0] dpra;
input [data_width-1:0] di;
//output [data_width-1:0] spo;
output [data_width-1:0] dpo;
reg [data_width-1:0] ram [depth-1:0];
wire [data_width-1:0] dpo;
wire [data_width-1:0] di;
wire [addr_width-1:0] a;
wire [addr_width-1:0] dpra;
always @(posedge clk) begin
if (we)
ram[a] <= di;
end
// assign spo = ram[a];
assign dpo = ram[dpra];
endmodule
|
module MemoryUnit
#(
parameter DATA_WIDTH = 32,
parameter MEMORY_ADDR_WIDTH = 13,
parameter BIOS_ADDRESS_WIDTH = 8,
parameter STORAGE_ADDR_WIDTH = 15,
parameter INSTRUCTION_SIZE = 16
)(
input allow_write_on_memory, slow_clock, fast_clock,
input [(DATA_WIDTH -1):0] original_address,
original_instruction_address,
MemOut,
input is_bios,
output [(INSTRUCTION_SIZE -1):0] output_instruction,
output [(DATA_WIDTH-1):0] data_read_from_memory
);
wire [(STORAGE_ADDR_WIDTH - 1) : 0] storage_addr;
wire [(DATA_WIDTH -1): 0] memory_data, storage_data;
wire is_storage;
wire [(INSTRUCTION_SIZE -1) : 0] memory_instruction,
bios_instruction;
MemoryController controller(
original_address,
is_storage,
storage_addr
);
Memory main_memory(
MemOut,
original_instruction_address[(MEMORY_ADDR_WIDTH - 1) : 0],
original_address[(MEMORY_ADDR_WIDTH - 1) : 0],
allow_write_on_memory, fast_clock, slow_clock,
memory_instruction,
memory_data
);
StorageDrive hd(
storage_addr,
MemOut,
is_storage && allow_write_on_memory , fast_clock, slow_clock,
storage_data
);
MemoryDataHandler poolMux(
is_storage,
storage_data, memory_data,
data_read_from_memory
);
BIOS bios(
fast_clock,
original_instruction_address[(BIOS_ADDRESS_WIDTH - 1):0],
bios_instruction
);
MemoryDataHandler #(.DATA_WIDTH(INSTRUCTION_SIZE))
instructionMUX(
is_bios,
bios_instruction,
memory_instruction,
output_instruction
);
endmodule
|
module hps_sdram_p0_acv_hard_addr_cmd_pads(
/*
config_data_in,
config_clock_in,
config_io_ena,
config_update,
*/
reset_n,
reset_n_afi_clk,
pll_hr_clk,
pll_avl_phy_clk,
pll_afi_clk,
pll_mem_clk,
pll_write_clk,
phy_ddio_address,
dll_delayctrl_in,
phy_ddio_bank,
phy_ddio_cs_n,
phy_ddio_cke,
phy_ddio_odt,
phy_ddio_we_n,
phy_ddio_ras_n,
phy_ddio_cas_n,
phy_ddio_ck,
phy_ddio_reset_n,
phy_mem_address,
phy_mem_bank,
phy_mem_cs_n,
phy_mem_cke,
phy_mem_odt,
phy_mem_we_n,
phy_mem_ras_n,
phy_mem_cas_n,
phy_mem_reset_n,
phy_mem_ck,
phy_mem_ck_n
);
parameter DEVICE_FAMILY = "";
parameter MEM_ADDRESS_WIDTH = "";
parameter MEM_BANK_WIDTH = "";
parameter MEM_CHIP_SELECT_WIDTH = "";
parameter MEM_CLK_EN_WIDTH = "";
parameter MEM_CK_WIDTH = "";
parameter MEM_ODT_WIDTH = "";
parameter MEM_CONTROL_WIDTH = "";
parameter AFI_ADDRESS_WIDTH = "";
parameter AFI_BANK_WIDTH = "";
parameter AFI_CHIP_SELECT_WIDTH = "";
parameter AFI_CLK_EN_WIDTH = "";
parameter AFI_ODT_WIDTH = "";
parameter AFI_CONTROL_WIDTH = "";
parameter DLL_WIDTH = "";
parameter ADC_PHASE_SETTING = "";
parameter ADC_INVERT_PHASE = "";
parameter IS_HHP_HPS = "";
/*
input config_data_in;
input config_clock_in;
input config_io_ena;
input config_update;
*/
input reset_n;
input reset_n_afi_clk;
input pll_afi_clk;
input pll_hr_clk;
input pll_avl_phy_clk;
input pll_mem_clk;
input pll_write_clk;
input [DLL_WIDTH-1:0] dll_delayctrl_in;
input [AFI_ADDRESS_WIDTH-1:0] phy_ddio_address;
input [AFI_BANK_WIDTH-1:0] phy_ddio_bank;
input [AFI_CHIP_SELECT_WIDTH-1:0] phy_ddio_cs_n;
input [AFI_CLK_EN_WIDTH-1:0] phy_ddio_cke;
input [AFI_ODT_WIDTH-1:0] phy_ddio_odt;
input [AFI_CONTROL_WIDTH-1:0] phy_ddio_ras_n;
input [AFI_CONTROL_WIDTH-1:0] phy_ddio_cas_n;
input [AFI_CONTROL_WIDTH-1:0] phy_ddio_ck;
input [AFI_CONTROL_WIDTH-1:0] phy_ddio_we_n;
input [AFI_CONTROL_WIDTH-1:0] phy_ddio_reset_n;
output [MEM_ADDRESS_WIDTH-1:0] phy_mem_address;
output [MEM_BANK_WIDTH-1:0] phy_mem_bank;
output [MEM_CHIP_SELECT_WIDTH-1:0] phy_mem_cs_n;
output [MEM_CLK_EN_WIDTH-1:0] phy_mem_cke;
output [MEM_ODT_WIDTH-1:0] phy_mem_odt;
output [MEM_CONTROL_WIDTH-1:0] phy_mem_we_n;
output [MEM_CONTROL_WIDTH-1:0] phy_mem_ras_n;
output [MEM_CONTROL_WIDTH-1:0] phy_mem_cas_n;
output phy_mem_reset_n;
output [MEM_CK_WIDTH-1:0] phy_mem_ck;
output [MEM_CK_WIDTH-1:0] phy_mem_ck_n;
/* ********* *
* A/C Logic *
* ********* */
localparam CMD_WIDTH =
MEM_CHIP_SELECT_WIDTH +
MEM_CLK_EN_WIDTH +
MEM_ODT_WIDTH +
MEM_CONTROL_WIDTH +
MEM_CONTROL_WIDTH +
MEM_CONTROL_WIDTH;
localparam AC_CLK_WIDTH = MEM_ADDRESS_WIDTH + MEM_BANK_WIDTH + CMD_WIDTH + 1;
localparam IMPLEMENT_MEM_CLK_IN_SOFT_LOGIC = "false";
wire [AC_CLK_WIDTH-1:0] ac_clk;
generate
genvar i;
for (i = 0; i < AC_CLK_WIDTH; i = i + 1)
begin: address_gen
wire addr_cmd_clk;
hps_sdram_p0_acv_ldc # (
.DLL_DELAY_CTRL_WIDTH(DLL_WIDTH),
.ADC_PHASE_SETTING(ADC_PHASE_SETTING),
.ADC_INVERT_PHASE(ADC_INVERT_PHASE),
.IS_HHP_HPS(IS_HHP_HPS)
) acv_ac_ldc (
.pll_hr_clk(pll_avl_phy_clk),
.pll_dq_clk(pll_write_clk),
.pll_dqs_clk (pll_mem_clk),
.dll_phy_delayctrl(dll_delayctrl_in),
.adc_clk_cps(ac_clk[i])
);
end
endgenerate
hps_sdram_p0_generic_ddio uaddress_pad(
.datain(phy_ddio_address),
.halfratebypass(1'b1),
.dataout(phy_mem_address),
.clk_hr({MEM_ADDRESS_WIDTH{pll_hr_clk}}),
.clk_fr(ac_clk[MEM_ADDRESS_WIDTH-1:0])
);
defparam uaddress_pad.WIDTH = MEM_ADDRESS_WIDTH;
hps_sdram_p0_generic_ddio ubank_pad(
.datain(phy_ddio_bank),
.halfratebypass(1'b1),
.dataout(phy_mem_bank),
.clk_hr({MEM_BANK_WIDTH{pll_hr_clk}}),
.clk_fr(ac_clk[MEM_ADDRESS_WIDTH + MEM_BANK_WIDTH - 1: MEM_ADDRESS_WIDTH])
);
defparam ubank_pad.WIDTH = MEM_BANK_WIDTH;
hps_sdram_p0_generic_ddio ucmd_pad(
.datain({
phy_ddio_we_n,
phy_ddio_cas_n,
phy_ddio_ras_n,
phy_ddio_odt,
phy_ddio_cke,
phy_ddio_cs_n
}),
.halfratebypass(1'b1),
.dataout({
phy_mem_we_n,
phy_mem_cas_n,
phy_mem_ras_n,
phy_mem_odt,
phy_mem_cke,
phy_mem_cs_n
}),
.clk_hr({CMD_WIDTH{pll_hr_clk}}),
.clk_fr(ac_clk[MEM_ADDRESS_WIDTH + MEM_BANK_WIDTH + CMD_WIDTH - 1: MEM_ADDRESS_WIDTH + MEM_BANK_WIDTH])
);
defparam ucmd_pad.WIDTH = CMD_WIDTH;
hps_sdram_p0_generic_ddio ureset_n_pad(
.datain(phy_ddio_reset_n),
.halfratebypass(1'b1),
.dataout(phy_mem_reset_n),
.clk_hr(pll_hr_clk),
.clk_fr(ac_clk[MEM_ADDRESS_WIDTH + MEM_BANK_WIDTH + CMD_WIDTH])
);
defparam ureset_n_pad.WIDTH = 1;
/* ************ *
* Config Logic *
* ************ */
wire [4:0] outputdelaysetting;
wire [4:0] outputenabledelaysetting;
wire outputhalfratebypass;
wire [4:0] inputdelaysetting;
wire [1:0] rfifo_clock_select;
wire [2:0] rfifo_mode;
/*
cyclonev_io_config ioconfig (
.datain(config_data_in),
.clk(config_clock_in),
.ena(config_io_ena),
.update(config_update),
.outputregdelaysetting(outputdelaysetting),
.outputenabledelaysetting(outputenabledelaysetting),
.outputhalfratebypass(outputhalfratebypass),
.readfiforeadclockselect(rfifo_clock_select),
.readfifomode(rfifo_mode),
.padtoinputregisterdelaysetting(inputdelaysetting),
.dataout()
);
*/
/* *************** *
* Mem Clock Logic *
* *************** */
wire [MEM_CK_WIDTH-1:0] mem_ck_source;
wire [MEM_CK_WIDTH-1:0] mem_ck;
generate
genvar clock_width;
for (clock_width=0; clock_width<MEM_CK_WIDTH; clock_width=clock_width+1)
begin: clock_gen
if(IMPLEMENT_MEM_CLK_IN_SOFT_LOGIC == "true")
begin
hps_sdram_p0_acv_ldc # (
.DLL_DELAY_CTRL_WIDTH(DLL_WIDTH),
.ADC_PHASE_SETTING(ADC_PHASE_SETTING),
.ADC_INVERT_PHASE(ADC_INVERT_PHASE),
.IS_HHP_HPS(IS_HHP_HPS)
) acv_ck_ldc (
.pll_hr_clk(pll_avl_phy_clk),
.pll_dq_clk(pll_write_clk),
.pll_dqs_clk (pll_mem_clk),
.dll_phy_delayctrl(dll_delayctrl_in),
.adc_clk_cps(mem_ck_source[clock_width])
);
end
else
begin
wire [3:0] phy_clk_in;
wire [3:0] phy_clk_out;
assign phy_clk_in = {pll_avl_phy_clk,pll_write_clk,pll_mem_clk,1'b0};
if (IS_HHP_HPS == "true") begin
assign phy_clk_out = phy_clk_in;
end else begin
cyclonev_phy_clkbuf phy_clkbuf (
.inclk (phy_clk_in),
.outclk (phy_clk_out)
);
end
wire [3:0] leveled_dqs_clocks;
cyclonev_leveling_delay_chain leveling_delay_chain_dqs (
.clkin (phy_clk_out[1]),
.delayctrlin (dll_delayctrl_in),
.clkout(leveled_dqs_clocks)
);
defparam leveling_delay_chain_dqs.physical_clock_source = "DQS";
cyclonev_clk_phase_select clk_phase_select_dqs (
`ifndef SIMGEN
.clkin (leveled_dqs_clocks[0]),
`else
.clkin (leveled_dqs_clocks),
`endif
.clkout (mem_ck_source[clock_width])
);
defparam clk_phase_select_dqs.physical_clock_source = "DQS";
defparam clk_phase_select_dqs.use_phasectrlin = "false";
defparam clk_phase_select_dqs.phase_setting = 0;
end
wire mem_ck_hi;
wire mem_ck_lo;
if(IMPLEMENT_MEM_CLK_IN_SOFT_LOGIC == "true")
begin
assign mem_ck_hi = 1'b0;
assign mem_ck_lo = 1'b1;
end
else
begin
assign mem_ck_hi = phy_ddio_ck[0];
assign mem_ck_lo = phy_ddio_ck[1];
end
altddio_out umem_ck_pad(
.aclr (1'b0),
.aset (1'b0),
.datain_h (mem_ck_hi),
.datain_l (mem_ck_lo),
.dataout (mem_ck[clock_width]),
.oe (1'b1),
.outclock (mem_ck_source[clock_width]),
.outclocken (1'b1)
);
defparam
umem_ck_pad.extend_oe_disable = "UNUSED",
umem_ck_pad.intended_device_family = DEVICE_FAMILY,
umem_ck_pad.invert_output = "OFF",
umem_ck_pad.lpm_hint = "UNUSED",
umem_ck_pad.lpm_type = "altddio_out",
umem_ck_pad.oe_reg = "UNUSED",
umem_ck_pad.power_up_high = "OFF",
umem_ck_pad.width = 1;
wire mem_ck_temp;
assign mem_ck_temp = mem_ck[clock_width];
hps_sdram_p0_clock_pair_generator uclk_generator(
.datain (mem_ck_temp),
.dataout (phy_mem_ck[clock_width]),
.dataout_b (phy_mem_ck_n[clock_width])
);
end
endgenerate
endmodule
|
module Fetch_Crude(
input [98:0] InstructionPacket,
input clock,
input stall,
output reg [31:0] x_input = 32'h00000000,
output reg [31:0] y_input = 32'h00000000,
output reg [31:0] z_input = 32'h00000000,
output reg [1:0] mode,
output reg operation,
output reg load = 1'b0
);
wire [3:0] Opcode;
wire [31:0] x_processor;
wire [31:0] y_processor;
wire [31:0] z_processor;
assign Opcode = InstructionPacket[98:96];
assign x_processor = InstructionPacket[31:0];
assign y_processor = InstructionPacket[63:32];
assign z_processor = InstructionPacket[95:64];
parameter sin_cos = 4'd0,
sinh_cosh = 4'd1,
arctan = 4'd2,
arctanh = 4'd3,
exp = 4'd4,
sqr_root = 4'd5, // This requires pre processing. x = (a+1)/4 and y = (a-1)/4
division = 4'd6,
tan = 4'd7, // This is iterative. sin_cos followed by division.
tanh = 4'd8, // This is iterative. sinh_cosh followed by division.
nat_log = 4'd9, // This requires pre processing. x = (a+1) and y = (a-1)
hypotenuse = 4'd10;
parameter vectoring = 1'b0,
rotation = 1'b1;
parameter circular = 2'b01,
linear = 2'b00,
hyperbolic = 2'b11;
always @ (posedge clock)
begin
if (stall == 1'b0) begin
case(Opcode)
sin_cos:
begin
mode <= circular;
operation <= rotation;
x_input <= 32'h3F800000;
y_input <= 32'h00000000;
z_input <= z_processor;
load <= 1'b1;
end
sinh_cosh:
begin
mode <= hyperbolic;
operation <= rotation;
x_input <= 32'h3F800000;
y_input <= 32'h00000000;
z_input <= z_processor;
load <= 1'b1;
end
arctan:
begin
mode <= circular;
operation <= vectoring;
x_input <= 32'h3F800000;
y_input <= y_processor;
z_input <= 32'h00000000;
load <= 1'b1;
end
arctanh:
begin
mode <= hyperbolic;
operation <= vectoring;
x_input <= 32'h3F800000;
y_input <= y_processor;
z_input <= 32'h00000000;
load <= 1'b1;
end
exp:
begin
mode <= hyperbolic;
operation <= rotation;
x_input <= 32'h3F800000;
y_input <= 32'h3F800000;
z_input <= z_processor;
load <= 1'b1;
end
sqr_root:
begin
mode <= hyperbolic;
operation <= vectoring;
x_input <= Register_File[x_address];
y_input <= Register_File[y_address];
z_input <= 32'h00000000;
load <= 1'b1;
end
division:
begin
mode <= linear;
operation <= vectoring;
x_input <= x_processor;
y_input <= y_processor;
z_input <= 32'h00000000;
load <= 1'b1;
end
hypotenuse:
begin
mode <= circular;
operation <= vectoring;
x_input <= x_processor;
y_input <= y_processor;
z_input <= 32'h00000000;
load <= 1'b1;
end
endcase
end
else begin
load <= 1'b0;
end
end
endmodule
|
module system_m04_regslice_12 (
aclk,
aresetn,
s_axi_awaddr,
s_axi_awprot,
s_axi_awvalid,
s_axi_awready,
s_axi_wdata,
s_axi_wstrb,
s_axi_wvalid,
s_axi_wready,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_araddr,
s_axi_arprot,
s_axi_arvalid,
s_axi_arready,
s_axi_rdata,
s_axi_rresp,
s_axi_rvalid,
s_axi_rready,
m_axi_awaddr,
m_axi_awprot,
m_axi_awvalid,
m_axi_awready,
m_axi_wdata,
m_axi_wstrb,
m_axi_wvalid,
m_axi_wready,
m_axi_bresp,
m_axi_bvalid,
m_axi_bready,
m_axi_araddr,
m_axi_arprot,
m_axi_arvalid,
m_axi_arready,
m_axi_rdata,
m_axi_rresp,
m_axi_rvalid,
m_axi_rready
);
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLK CLK" *)
input wire aclk;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RST RST" *)
input wire aresetn;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *)
input wire [8 : 0] s_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWPROT" *)
input wire [2 : 0] s_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWVALID" *)
input wire s_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREADY" *)
output wire s_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WDATA" *)
input wire [31 : 0] s_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WSTRB" *)
input wire [3 : 0] s_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WVALID" *)
input wire s_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *)
output wire s_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *)
output wire [1 : 0] s_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *)
output wire s_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *)
input wire s_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARADDR" *)
input wire [8 : 0] s_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARPROT" *)
input wire [2 : 0] s_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARVALID" *)
input wire s_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREADY" *)
output wire s_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RDATA" *)
output wire [31 : 0] s_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RRESP" *)
output wire [1 : 0] s_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RVALID" *)
output wire s_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *)
input wire s_axi_rready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWADDR" *)
output wire [8 : 0] m_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWPROT" *)
output wire [2 : 0] m_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWVALID" *)
output wire m_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREADY" *)
input wire m_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WDATA" *)
output wire [31 : 0] m_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WSTRB" *)
output wire [3 : 0] m_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WVALID" *)
output wire m_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WREADY" *)
input wire m_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BRESP" *)
input wire [1 : 0] m_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BVALID" *)
input wire m_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BREADY" *)
output wire m_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARADDR" *)
output wire [8 : 0] m_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARPROT" *)
output wire [2 : 0] m_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARVALID" *)
output wire m_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREADY" *)
input wire m_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RDATA" *)
input wire [31 : 0] m_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RRESP" *)
input wire [1 : 0] m_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RVALID" *)
input wire m_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RREADY" *)
output wire m_axi_rready;
axi_register_slice_v2_1_axi_register_slice #(
.C_FAMILY("zynq"),
.C_AXI_PROTOCOL(2),
.C_AXI_ID_WIDTH(1),
.C_AXI_ADDR_WIDTH(9),
.C_AXI_DATA_WIDTH(32),
.C_AXI_SUPPORTS_USER_SIGNALS(0),
.C_AXI_AWUSER_WIDTH(1),
.C_AXI_ARUSER_WIDTH(1),
.C_AXI_WUSER_WIDTH(1),
.C_AXI_RUSER_WIDTH(1),
.C_AXI_BUSER_WIDTH(1),
.C_REG_CONFIG_AW(7),
.C_REG_CONFIG_W(7),
.C_REG_CONFIG_B(7),
.C_REG_CONFIG_AR(7),
.C_REG_CONFIG_R(7)
) inst (
.aclk(aclk),
.aresetn(aresetn),
.s_axi_awid(1'H0),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awlen(8'H00),
.s_axi_awsize(3'H0),
.s_axi_awburst(2'H0),
.s_axi_awlock(1'H0),
.s_axi_awcache(4'H0),
.s_axi_awprot(s_axi_awprot),
.s_axi_awregion(4'H0),
.s_axi_awqos(4'H0),
.s_axi_awuser(1'H0),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_awready(s_axi_awready),
.s_axi_wid(1'H0),
.s_axi_wdata(s_axi_wdata),
.s_axi_wstrb(s_axi_wstrb),
.s_axi_wlast(1'H1),
.s_axi_wuser(1'H0),
.s_axi_wvalid(s_axi_wvalid),
.s_axi_wready(s_axi_wready),
.s_axi_bid(),
.s_axi_bresp(s_axi_bresp),
.s_axi_buser(),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_bready(s_axi_bready),
.s_axi_arid(1'H0),
.s_axi_araddr(s_axi_araddr),
.s_axi_arlen(8'H00),
.s_axi_arsize(3'H0),
.s_axi_arburst(2'H0),
.s_axi_arlock(1'H0),
.s_axi_arcache(4'H0),
.s_axi_arprot(s_axi_arprot),
.s_axi_arregion(4'H0),
.s_axi_arqos(4'H0),
.s_axi_aruser(1'H0),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_arready(s_axi_arready),
.s_axi_rid(),
.s_axi_rdata(s_axi_rdata),
.s_axi_rresp(s_axi_rresp),
.s_axi_rlast(),
.s_axi_ruser(),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_rready(s_axi_rready),
.m_axi_awid(),
.m_axi_awaddr(m_axi_awaddr),
.m_axi_awlen(),
.m_axi_awsize(),
.m_axi_awburst(),
.m_axi_awlock(),
.m_axi_awcache(),
.m_axi_awprot(m_axi_awprot),
.m_axi_awregion(),
.m_axi_awqos(),
.m_axi_awuser(),
.m_axi_awvalid(m_axi_awvalid),
.m_axi_awready(m_axi_awready),
.m_axi_wid(),
.m_axi_wdata(m_axi_wdata),
.m_axi_wstrb(m_axi_wstrb),
.m_axi_wlast(),
.m_axi_wuser(),
.m_axi_wvalid(m_axi_wvalid),
.m_axi_wready(m_axi_wready),
.m_axi_bid(1'H0),
.m_axi_bresp(m_axi_bresp),
.m_axi_buser(1'H0),
.m_axi_bvalid(m_axi_bvalid),
.m_axi_bready(m_axi_bready),
.m_axi_arid(),
.m_axi_araddr(m_axi_araddr),
.m_axi_arlen(),
.m_axi_arsize(),
.m_axi_arburst(),
.m_axi_arlock(),
.m_axi_arcache(),
.m_axi_arprot(m_axi_arprot),
.m_axi_arregion(),
.m_axi_arqos(),
.m_axi_aruser(),
.m_axi_arvalid(m_axi_arvalid),
.m_axi_arready(m_axi_arready),
.m_axi_rid(1'H0),
.m_axi_rdata(m_axi_rdata),
.m_axi_rresp(m_axi_rresp),
.m_axi_rlast(1'H1),
.m_axi_ruser(1'H0),
.m_axi_rvalid(m_axi_rvalid),
.m_axi_rready(m_axi_rready)
);
endmodule
|
module header
// Internal signals
//
// Generated Signal List
//
wire [4:0] top_rs_selclk_out2_par;
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
// Generated Signal Assignments
assign top_rs_selclk_out2_par[4:4] = `top_rs_selclk_out2_par_c;
//
// Generated Instances
// wiring ...
// Generated Instances and Port Mappings
// Generated Instance Port Map for i_avfb_cgu
cgu i_avfb_cgu (
.selclk_out2_par_i(top_rs_selclk_out2_par)
);
// End of Generated Instance Port Map for i_avfb_cgu
// Generated Instance Port Map for i_avfb_logic
avfb_logic i_avfb_logic (
.top_rs_selclk_out2_par_go(top_rs_selclk_out2_par)
);
// End of Generated Instance Port Map for i_avfb_logic
endmodule
|
module axi_axis_tx_core (
// dac interface
dac_clk,
dac_rd,
dac_valid,
dac_data,
// dma interface
dma_clk,
dma_fs,
dma_valid,
dma_data,
dma_ready,
// processor interface
up_rstn,
up_clk,
up_sel,
up_wr,
up_addr,
up_wdata,
up_rdata,
up_ack);
// parameters
parameter DATA_WIDTH = 64;
localparam DW = DATA_WIDTH - 1;
// dac interface
input dac_clk;
input dac_rd;
output dac_valid;
output [DW:0] dac_data;
// dma interface
input dma_clk;
output dma_fs;
input dma_valid;
input [63:0] dma_data;
output dma_ready;
// processor interface
input up_rstn;
input up_clk;
input up_sel;
input up_wr;
input [13:0] up_addr;
input [31:0] up_wdata;
output [31:0] up_rdata;
output up_ack;
// internal clock and resets
wire dac_rst;
wire dma_rst;
// internal signals
wire dma_ovf_s;
wire dma_unf_s;
wire [31:0] dma_frmcnt_s;
// dma interface
ad_axis_dma_tx #(.DATA_WIDTH(DATA_WIDTH)) i_axis_dma_tx (
.dma_clk (dma_clk),
.dma_rst (dma_rst),
.dma_fs (dma_fs),
.dma_valid (dma_valid),
.dma_data (dma_data),
.dma_ready (dma_ready),
.dma_ovf (dma_ovf_s),
.dma_unf (dma_unf_s),
.dac_clk (dac_clk),
.dac_rst (dac_rst),
.dac_rd (dac_rd),
.dac_valid (dac_valid),
.dac_data (dac_data),
.dma_frmcnt (dma_frmcnt_s));
// processor interface
up_axis_dma_tx i_up_axis_dma_tx (
.dac_clk (dac_clk),
.dac_rst (dac_rst),
.dma_clk (dma_clk),
.dma_rst (dma_rst),
.dma_frmcnt (dma_frmcnt_s),
.dma_ovf (dma_ovf_s),
.dma_unf (dma_unf_s),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_sel (up_sel),
.up_wr (up_wr),
.up_addr (up_addr),
.up_wdata (up_wdata),
.up_rdata (up_rdata),
.up_ack (up_ack));
endmodule
|
module sky130_fd_sc_hdll__nor4b (
Y ,
A ,
B ,
C ,
D_N ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input C ;
input D_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
|
module display_logic( input pxl_clk,
input [9:0] hcount,
input [9:0] vcount,
input [9:0] ball_y,
input [9:0] ball_x,
input [5:0] player_position,
input [3:0] block_num,
input vsync,
input lose,
input win,
output reg drawing_player,
output reg drawing_block,
output reg [2:0] rgb );
`include "defines.v"
reg [2:0] flash;
reg [3:0] flash_time;
reg flash_hold;
always @ (hcount, vcount, ball_y, ball_x, player_position, block_num, lose, win, flash)
begin : display_decoder
drawing_player = 0;
drawing_block = 0;
if (hcount > `screen_right || vcount > `screen_bottom) rgb <= 3'b000;
else if (win) rgb <= flash;
else if (lose) rgb <= `red;
else if (vcount < `bottom_edge && hcount < `left_edge) rgb <= `green;
else if (vcount < `bottom_edge && hcount > `right_edge) rgb <= `green;
else if (vcount < `top_edge ) rgb <= `green;
else if (vcount > `bottom_edge) rgb <= `red;
else if (vcount < ball_y + 3 && vcount > ball_y - 3 &&
hcount < ball_x + 3 && hcount > ball_x - 3) rgb <= `white;
else if ( vcount > `player_vstart && vcount < (`player_vstart + `player_width ) &&
hcount > (player_position << 5) - `player_hlength + `left_edge &&
hcount < ((player_position << 5) + `player_hlength + `left_edge) )
begin
rgb <= `white;
drawing_player <= 1;
end
else if (vcount > `blocks_vstart && vcount <= `blocks_vend && hcount > `blocks_hstart && hcount <= `blocks_hend && |block_num)
begin
drawing_block <= 1;
if ( |block_num[2:0] ) rgb <= block_num[2:0];
else rgb <= block_num[2:0] + 3;
// rgb <= ~|block_num[3:0] ? block_num[2:0] : block_num[2:0] + 3'd3;
end
else rgb <= `black;
end
always @ (posedge pxl_clk)
begin
if (!vsync)
begin
if (!flash_hold) flash_time <= flash_time + 1;
flash_hold <= 1;
end
else
begin
flash_hold <= 0;
end
if (flash_time == 0)
begin
flash <= `black;
end
else if (flash_time == 3)
begin
if (win) flash <= `white;
else if (lose) flash <= `red;
end
else if (flash_time >= 6)
begin
flash_time <= 0;
end
end
endmodule
|
module sparc_ifu_wseldp (/*AUTOARG*/
// Outputs
wsel_fdp_fetdata_s1, wsel_fdp_topdata_s1, wsel_mbist_icache_data,
so,
// Inputs
rclk, se, si, icd_wsel_fetdata_s1, icd_wsel_topdata_s1,
itlb_wsel_waysel_s1, ifq_erb_asiway_f
);
input rclk,
se,
si;
input [135:0] icd_wsel_fetdata_s1,
icd_wsel_topdata_s1;
input [3:0] itlb_wsel_waysel_s1;
input [1:0] ifq_erb_asiway_f;
output [33:0] wsel_fdp_fetdata_s1;
output [33:0] wsel_fdp_topdata_s1;
output [67:0] wsel_mbist_icache_data;
output so;
// local signals
wire [3:0] dec_asiway_s_l,
waysel_buf_s1;
wire [1:0] asiway_s;
wire [33:0] rdc_fetdata_s1,
rdc_topdata_s1,
erb_asidata_s,
asi_topdata_s;
wire clk;
//
// Code begins here
//
//------------------
// Control Portion
//------------------
assign clk = rclk;
// flop and decode waysel
dff_s #(2) asiway_reg(.din (ifq_erb_asiway_f),
.q (asiway_s),
.clk (clk), .se(se), .si(), .so());
assign dec_asiway_s_l[0] = ~(~asiway_s[1] & ~asiway_s[0]);
assign dec_asiway_s_l[1] = ~(~asiway_s[1] & asiway_s[0]);
assign dec_asiway_s_l[2] = ~( asiway_s[1] & ~asiway_s[0]);
assign dec_asiway_s_l[3] = ~( asiway_s[1] & asiway_s[0]);
//--------------------------
// Datapath Section
//--------------------------
// buffer wayselect from itlb
// align these buffers with the corresponding pins in itlb
assign waysel_buf_s1 = itlb_wsel_waysel_s1;
// Very Timing Critical Wayselect Muxes
// !!Cannot be a one-hot mux!!
// use ao2222
// bw_u1_ao2222_2x #(34) fetway_mx(.z (rdc_fetdata_s1[33:0]),
// .a2 (icd_wsel_fetdata_s1[33:0]),
// .b2 (icd_wsel_fetdata_s1[67:34]),
// .c2 (icd_wsel_fetdata_s1[101:68]),
// .d2 (icd_wsel_fetdata_s1[135:102]),
// .a1 (waysel_buf_s1[0]),
// .b1 (waysel_buf_s1[1]),
// .c1 (waysel_buf_s1[2]),
// .d1 (waysel_buf_s1[3]));
// bw_u1_ao2222_2x #(34) topway_mx(.z (rdc_topdata_s1[33:0]),
// .a2 (icd_wsel_topdata_s1[33:0]),
// .b2 (icd_wsel_topdata_s1[67:34]),
// .c2 (icd_wsel_topdata_s1[101:68]),
// .d2 (icd_wsel_topdata_s1[135:102]),
// .a1 (waysel_buf_s1[0]),
// .b1 (waysel_buf_s1[1]),
// .c1 (waysel_buf_s1[2]),
// .d1 (waysel_buf_s1[3]));
assign rdc_fetdata_s1 = icd_wsel_fetdata_s1[33:0] & {34{waysel_buf_s1[0]}} |
icd_wsel_fetdata_s1[67:34] & {34{waysel_buf_s1[1]}} |
icd_wsel_fetdata_s1[101:68] & {34{waysel_buf_s1[2]}} |
icd_wsel_fetdata_s1[135:102] & {34{waysel_buf_s1[3]}};
assign rdc_topdata_s1 = icd_wsel_topdata_s1[33:0] & {34{waysel_buf_s1[0]}} |
icd_wsel_topdata_s1[67:34] & {34{waysel_buf_s1[1]}} |
icd_wsel_topdata_s1[101:68] & {34{waysel_buf_s1[2]}} |
icd_wsel_topdata_s1[135:102] & {34{waysel_buf_s1[3]}};
// buffer and send to fdp
assign wsel_fdp_fetdata_s1 = rdc_fetdata_s1;
assign wsel_fdp_topdata_s1 = rdc_topdata_s1;
// mux for asi data, not critical
dp_mux4ds #(34) asid_mx(.dout (erb_asidata_s[33:0]),
.in0 (icd_wsel_fetdata_s1[33:0]),
.in1 (icd_wsel_fetdata_s1[67:34]),
.in2 (icd_wsel_fetdata_s1[101:68]),
.in3 (icd_wsel_fetdata_s1[135:102]),
.sel0_l (dec_asiway_s_l[0]),
.sel1_l (dec_asiway_s_l[1]),
.sel2_l (dec_asiway_s_l[2]),
.sel3_l (dec_asiway_s_l[3]));
dp_mux4ds #(34) asitop_mx(.dout (asi_topdata_s[33:0]),
.in0 (icd_wsel_topdata_s1[33:0]),
.in1 (icd_wsel_topdata_s1[67:34]),
.in2 (icd_wsel_topdata_s1[101:68]),
.in3 (icd_wsel_topdata_s1[135:102]),
.sel0_l (dec_asiway_s_l[0]),
.sel1_l (dec_asiway_s_l[1]),
.sel2_l (dec_asiway_s_l[2]),
.sel3_l (dec_asiway_s_l[3]));
// buffer before sending to bist/errdp
assign wsel_mbist_icache_data = {asi_topdata_s[33:32],
erb_asidata_s[33:32],
asi_topdata_s[31:0],
erb_asidata_s[31:0]};
// Everything below can be ignored for physical implementation
// monitor for waysel -- moved here from itlb
// Keeping this around for 0-in. cmp level check is in icache_mutex_mon.v
`ifdef DEFINE_0IN
always @ (negedge clk)
begin
if (!((waysel_buf_s1 == 4'b0001) ||
(waysel_buf_s1 == 4'b0010) ||
(waysel_buf_s1 == 4'b0100) ||
(waysel_buf_s1 == 4'b1000) ||
(waysel_buf_s1 == 4'b0000)))
begin
// 0in <fire -message "FATAL ERROR: icache waysel not mutex"
//$error("IC_WAYSEL", "FATAL ERROR: icache waysel not mutex %b",
// waysel_buf_s1);
end
end // always @ (negedge clk)
`endif
endmodule
|
module
altpciexpav_stif_rx_resp
# (
.CG_COMMON_CLOCK_MODE(CG_COMMON_CLOCK_MODE)
)
rxavl_resp
( .Clk_i(Clk_i),
.AvlClk_i(AvlClk_i),
.Rstn_i(Rstn_i),
.RxmRstn_i(RxmRstn_i),
// Interface to Transaction layer
.CplReq_i(cpl_req),
.CplDesc_i(cpl_desc),
/// interface to completion buffer
.CplRdAddr_o(cplram_rdaddr),
.CplBufData_i(cplram_data_out),
// interface to tx control
.TagRelease_o(CplTagRelease_o),
// interface to Avalon slave
//.TxsReadData_o(TxReadData_o),
.TxsReadDataValid_o(TxReadDataValid_o)
);
// Muxing the tag ram read address
// from the two reading sources : main control and read response
//// instantiate the Rx Completion data ram
generate if(CB_PCIE_MODE == 0)
begin
altsyncram
#(
.intended_device_family("Stratix"),
.operation_mode("DUAL_PORT"),
.width_a(66),
.widthad_a(RX_CPL_BUFF_ADDR_WIDTH),
.numwords_a(CB_RX_CPL_BUFFER_DEPTH),
.width_b(66),
.widthad_b(RX_CPL_BUFF_ADDR_WIDTH),
.numwords_b(CB_RX_CPL_BUFFER_DEPTH),
.lpm_type("altsyncram"),
.width_byteena_a(1),
.outdata_reg_b("UNREGISTERED"),
.indata_aclr_a("NONE"),
.wrcontrol_aclr_a("NONE"),
.address_aclr_a("NONE"),
.address_reg_b("CLOCK0"),
.address_aclr_b("NONE"),
.outdata_aclr_b("NONE"),
.read_during_write_mode_mixed_ports("DONT_CARE"),
.power_up_uninitialized("FALSE")
)
cpl_ram (
.wren_a (cplram_wr_ena),
.clock0 (AvlClk_i),
.address_a (cplram_wraddr),
.address_b (cplram_rdaddr),
.data_a (cplram_wrdat),
.q_b (cplram_data_out),
.aclr0 (),
.aclr1 (),
.addressstall_a (),
.addressstall_b (),
.byteena_a (),
.byteena_b (),
.clock1 (),
.clocken0 (),
.clocken1 (),
.data_b (),
.q_a (),
.rden_b (),
.wren_b ()
);
assign TxReadData_o = cplram_data_out[63:0];
end
else
begin
assign TxReadData_o = 64'h0;
end
endgenerate
endmodule
|
module wishbone_master_tb (
);
//Virtual Host Interface Signals
reg clk = 0;
reg rst = 0;
wire w_master_ready;
reg r_in_ready = 0;
reg [31:0] r_in_command = 32'h00000000;
reg [31:0] r_in_address = 32'h00000000;
reg [31:0] r_in_data = 32'h00000000;
reg [27:0] r_in_data_count = 0;
reg r_out_ready = 0;
wire w_out_en;
wire [31:0] w_out_status;
wire [31:0] w_out_address;
wire [31:0] w_out_data;
wire [27:0] w_out_data_count;
reg r_ih_reset = 0;
//wishbone signals
wire w_wbm_we;
wire w_wbm_cyc;
wire w_wbm_stb;
wire [3:0] w_wbm_sel;
wire [31:0] w_wbm_adr;
wire [31:0] w_wbm_dat_o;
wire [31:0] w_wbm_dat_i;
wire w_wbm_ack;
wire w_wbm_int;
//Wishbone Slave 0 (SDB) signals
wire w_wbs0_we;
wire w_wbs0_cyc;
wire [31:0] w_wbs0_dat_o;
wire w_wbs0_stb;
wire [3:0] w_wbs0_sel;
wire w_wbs0_ack;
wire [31:0] w_wbs0_dat_i;
wire [31:0] w_wbs0_adr;
wire w_wbs0_int;
//wishbone slave 1 (Unit Under Test) signals
wire w_wbs1_we;
wire w_wbs1_cyc;
wire w_wbs1_stb;
wire [3:0] w_wbs1_sel;
wire w_wbs1_ack;
wire [31:0] w_wbs1_dat_i;
wire [31:0] w_wbs1_dat_o;
wire [31:0] w_wbs1_adr;
wire w_wbs1_int;
//Local Parameters
localparam WAIT_FOR_SDRAM = 8'h00;
localparam IDLE = 8'h01;
localparam SEND_COMMAND = 8'h02;
localparam MASTER_READ_COMMAND = 8'h03;
localparam RESET = 8'h04;
localparam PING_RESPONSE = 8'h05;
localparam WRITE_DATA = 8'h06;
localparam WRITE_RESPONSE = 8'h07;
localparam GET_WRITE_DATA = 8'h08;
localparam READ_RESPONSE = 8'h09;
localparam READ_MORE_DATA = 8'h0A;
localparam FINISHED = 8'h0B;
//Registers/Wires/Simulation Integers
integer fd_in;
integer fd_out;
integer read_count;
integer timeout_count;
integer ch;
integer data_count;
reg [3:0] state = IDLE;
reg prev_int = 0;
wire start;
reg execute_command;
reg command_finished;
reg request_more_data;
reg request_more_data_ack;
reg [27:0] data_write_count;
reg [27:0] data_read_count;
//Submodules
wishbone_master wm (
.clk (clk ),
.rst (rst ),
.i_ih_rst (r_ih_reset ),
.i_ready (r_in_ready ),
.i_command (r_in_command ),
.i_address (r_in_address ),
.i_data (r_in_data ),
.i_data_count (r_in_data_count ),
.i_out_ready (r_out_ready ),
.o_en (w_out_en ),
.o_status (w_out_status ),
.o_address (w_out_address ),
.o_data (w_out_data ),
.o_data_count (w_out_data_count ),
.o_master_ready (w_master_ready ),
.o_per_we (w_wbm_we ),
.o_per_adr (w_wbm_adr ),
.o_per_dat (w_wbm_dat_i ),
.i_per_dat (w_wbm_dat_o ),
.o_per_stb (w_wbm_stb ),
.o_per_cyc (w_wbm_cyc ),
.o_per_msk (w_wbm_msk ),
.o_per_sel (w_wbm_sel ),
.i_per_ack (w_wbm_ack ),
.i_per_int (w_wbm_int )
);
//slave 1
wb_artemis_pcie_platform s1 (
.clk (clk ),
.rst (rst ),
.i_wbs_we (w_wbs1_we ),
.i_wbs_cyc (w_wbs1_cyc ),
.i_wbs_dat (w_wbs1_dat_i ),
.i_wbs_stb (w_wbs1_stb ),
.o_wbs_ack (w_wbs1_ack ),
.o_wbs_dat (w_wbs1_dat_o ),
.i_wbs_adr (w_wbs1_adr ),
.o_wbs_int (w_wbs1_int )
);
wishbone_interconnect wi (
.clk (clk ),
.rst (rst ),
.i_m_we (w_wbm_we ),
.i_m_cyc (w_wbm_cyc ),
.i_m_stb (w_wbm_stb ),
.o_m_ack (w_wbm_ack ),
.i_m_dat (w_wbm_dat_i ),
.o_m_dat (w_wbm_dat_o ),
.i_m_adr (w_wbm_adr ),
.o_m_int (w_wbm_int ),
.o_s0_we (w_wbs0_we ),
.o_s0_cyc (w_wbs0_cyc ),
.o_s0_stb (w_wbs0_stb ),
.i_s0_ack (w_wbs0_ack ),
.o_s0_dat (w_wbs0_dat_i ),
.i_s0_dat (w_wbs0_dat_o ),
.o_s0_adr (w_wbs0_adr ),
.i_s0_int (w_wbs0_int ),
.o_s1_we (w_wbs1_we ),
.o_s1_cyc (w_wbs1_cyc ),
.o_s1_stb (w_wbs1_stb ),
.i_s1_ack (w_wbs1_ack ),
.o_s1_dat (w_wbs1_dat_i ),
.i_s1_dat (w_wbs1_dat_o ),
.o_s1_adr (w_wbs1_adr ),
.i_s1_int (w_wbs1_int )
);
assign w_wbs0_ack = 0;
assign w_wbs0_dat_o = 0;
assign start = 1;
always #`CLK_HALF_PERIOD clk = ~clk;
initial begin
fd_out = 0;
read_count = 0;
data_count = 0;
timeout_count = 0;
request_more_data_ack <= 0;
execute_command <= 0;
$dumpfile ("design.vcd");
$dumpvars (0, wishbone_master_tb);
fd_in = $fopen(`INPUT_FILE, "r");
fd_out = $fopen(`OUTPUT_FILE, "w");
`SLEEP_HALF_CLK;
rst <= 0;
`SLEEP_CLK(100);
rst <= 1;
//clear the handler signals
r_in_ready <= 0;
r_in_command <= 0;
r_in_address <= 32'h0;
r_in_data <= 32'h0;
r_in_data_count <= 0;
r_out_ready <= 0;
//clear wishbone signals
`SLEEP_CLK(10);
rst <= 0;
r_out_ready <= 1;
if (fd_in == 0) begin
$display ("TB: input stimulus file was not found");
end
else begin
//while there is still data to be read from the file
while (!$feof(fd_in)) begin
//read in a command
read_count = $fscanf (fd_in, "%h:%h:%h:%h\n",
r_in_data_count,
r_in_command,
r_in_address,
r_in_data);
//Handle Frindge commands/comments
if (read_count != 4) begin
if (read_count == 0) begin
ch = $fgetc(fd_in);
if (ch == "\#") begin
//$display ("Eat a comment");
//Eat the line
while (ch != "\n") begin
ch = $fgetc(fd_in);
end
`ifdef VERBOSE $display (""); `endif
end
else begin
`ifdef VERBOSE $display ("Error unrecognized line: %h" % ch); `endif
//Eat the line
while (ch != "\n") begin
ch = $fgetc(fd_in);
end
end
end
else if (read_count == 1) begin
`ifdef VERBOSE $display ("Sleep for %h Clock cycles", r_in_data_count); `endif
`SLEEP_CLK(r_in_data_count);
`ifdef VERBOSE $display ("Sleep Finished"); `endif
end
else begin
`ifdef VERBOSE $display ("Error: read_count = %h != 4", read_count); `endif
`ifdef VERBOSE $display ("Character: %h", ch); `endif
end
end
else begin
`ifdef VERBOSE
case (r_in_command)
0: $display ("TB: Executing PING commad");
1: $display ("TB: Executing WRITE command");
2: $display ("TB: Executing READ command");
3: $display ("TB: Executing RESET command");
endcase
`endif
`ifdef VERBOSE $display ("Execute Command"); `endif
execute_command <= 1;
`SLEEP_CLK(1);
while (~command_finished) begin
request_more_data_ack <= 0;
if ((r_in_command & 32'h0000FFFF) == 1) begin
if (request_more_data && ~request_more_data_ack) begin
read_count = $fscanf(fd_in, "%h\n", r_in_data);
`ifdef VERBOSE $display ("TB: reading a new double word: %h", r_in_data); `endif
request_more_data_ack <= 1;
end
end
//so time porgresses wait a tick
`SLEEP_CLK(1);
//this doesn't need to be here, but there is a weird behavior in iverilog
//that wont allow me to put a delay in right before an 'end' statement
//execute_command <= 1;
end //while command is not finished
execute_command <= 0;
while (command_finished) begin
`ifdef VERBOSE $display ("Command Finished"); `endif
`SLEEP_CLK(1);
execute_command <= 0;
end
`SLEEP_CLK(50);
`ifdef VERBOSE $display ("TB: finished command"); `endif
end //end read_count == 4
end //end while ! eof
end //end not reset
`SLEEP_CLK(50);
$fclose (fd_in);
$fclose (fd_out);
$finish();
end
//initial begin
// $monitor("%t, state: %h", $time, state);
//end
//initial begin
// $monitor("%t, data: %h, state: %h, execute command: %h", $time, w_wbm_dat_o, state, execute_command);
//end
//initial begin
//$monitor("%t, state: %h, execute: %h, cmd_fin: %h", $time, state, execute_command, command_finished);
//$monitor("%t, state: %h, write_size: %d, write_count: %d, execute: %h", $time, state, r_in_data_count, data_write_count, execute_command);
//end
always @ (posedge clk) begin
if (rst) begin
state <= WAIT_FOR_SDRAM;
request_more_data <= 0;
timeout_count <= 0;
prev_int <= 0;
r_ih_reset <= 0;
data_write_count <= 0;
data_read_count <= 1;
command_finished <= 0;
end
else begin
r_ih_reset <= 0;
r_in_ready <= 0;
r_out_ready <= 1;
command_finished <= 0;
//Countdown the NACK timeout
if (execute_command && timeout_count < `TIMEOUT_COUNT) begin
timeout_count <= timeout_count + 1;
end
if (execute_command && timeout_count >= `TIMEOUT_COUNT) begin
`ifdef VERBOSE
case (r_in_command)
0: $display ("TB: Master timed out while executing PING commad");
1: $display ("TB: Master timed out while executing WRITE command");
2: $display ("TB: Master timed out while executing READ command");
3: $display ("TB: Master timed out while executing RESET command");
endcase
`endif
command_finished <= 1;
state <= IDLE;
timeout_count <= 0;
end //end reached the end of a timeout
case (state)
WAIT_FOR_SDRAM: begin
timeout_count <= 0;
r_in_ready <= 0;
//Uncomment 'start' conditional to wait for SDRAM to finish starting
//up
if (start) begin
`ifdef VERBOSE $display ("TB: sdram is ready"); `endif
state <= IDLE;
end
end
IDLE: begin
timeout_count <= 0;
command_finished <= 0;
data_write_count <= 1;
if (execute_command && !command_finished) begin
state <= SEND_COMMAND;
end
data_read_count <= 1;
end
SEND_COMMAND: begin
timeout_count <= 0;
if (w_master_ready) begin
r_in_ready <= 1;
state <= MASTER_READ_COMMAND;
end
end
MASTER_READ_COMMAND: begin
r_in_ready <= 1;
if (!w_master_ready) begin
r_in_ready <= 0;
case (r_in_command & 32'h0000FFFF)
0: begin
state <= PING_RESPONSE;
end
1: begin
if (r_in_data_count > 1) begin
`ifdef VERBOSE $display ("TB:\tWrote Double Word %d: %h", data_write_count, r_in_data); `endif
if (data_write_count < r_in_data_count) begin
state <= WRITE_DATA;
timeout_count <= 0;
data_write_count<= data_write_count + 1;
end
else begin
`ifdef VERBOSE $display ("TB: Finished Writing: %d 32bit words of %d size", r_in_data_count, data_write_count); `endif
state <= WRITE_RESPONSE;
end
end
else begin
`ifdef VERBOSE $display ("TB:\tWrote Double Word %d: %h", data_write_count, r_in_data); `endif
`ifdef VERBOSE $display ("TB: Finished Writing: %d 32bit words of %d size", r_in_data_count, data_write_count); `endif
state <= WRITE_RESPONSE;
end
end
2: begin
state <= READ_RESPONSE;
end
3: begin
state <= RESET;
end
endcase
end
end
RESET: begin
r_ih_reset <= 1;
state <= RESET;
end
PING_RESPONSE: begin
if (w_out_en) begin
if (w_out_status[7:0] == 8'hFF) begin
`ifdef VERBOSE $display ("TB: Ping Response Good"); `endif
end
else begin
`ifdef VERBOSE $display ("TB: Ping Response Bad (Malformed response: %h)", w_out_status); `endif
end
`ifdef VERBOSE $display ("TB: \tS:A:D = %h:%h:%h\n", w_out_status, w_out_address, w_out_data); `endif
state <= FINISHED;
end
end
WRITE_DATA: begin
if (!r_in_ready && w_master_ready) begin
state <= GET_WRITE_DATA;
request_more_data <= 1;
end
end
WRITE_RESPONSE: begin
`ifdef VERBOSE $display ("In Write Response"); `endif
if (w_out_en) begin
if (w_out_status[7:0] == (~(8'h01))) begin
`ifdef VERBOSE $display ("TB: Write Response Good"); `endif
end
else begin
`ifdef VERBOSE $display ("TB: Write Response Bad (Malformed response: %h)", w_out_status); `endif
end
`ifdef VERBOSE $display ("TB: \tS:A:D = %h:%h:%h\n", w_out_status, w_out_address, w_out_data); `endif
state <= FINISHED;
end
end
GET_WRITE_DATA: begin
if (request_more_data_ack) begin
request_more_data <= 0;
r_in_ready <= 1;
state <= SEND_COMMAND;
end
end
READ_RESPONSE: begin
if (w_out_en) begin
if (w_out_status[7:0] == (~(8'h02))) begin
`ifdef VERBOSE $display ("TB: Read Response Good"); `endif
if (w_out_data_count > 0) begin
if (data_read_count < w_out_data_count) begin
state <= READ_MORE_DATA;
timeout_count <= 0;
data_read_count <= data_read_count + 1;
end
else begin
state <= FINISHED;
end
end
end
else begin
`ifdef VERBOSE $display ("TB: Read Response Bad (Malformed response: %h)", w_out_status); `endif
state <= FINISHED;
end
`ifdef VERBOSE $display ("TB: \tS:A:D = %h:%h:%h\n", w_out_status, w_out_address, w_out_data); `endif
end
end
READ_MORE_DATA: begin
if (w_out_en) begin
timeout_count <= 0;
r_out_ready <= 0;
`ifdef VERBOSE $display ("TB: Read a 32bit data packet"); `endif
`ifdef VERBOSE $display ("TB: \tRead Data: %h", w_out_data); `endif
data_read_count <= data_read_count + 1;
end
if (data_read_count >= r_in_data_count) begin
state <= FINISHED;
end
end
FINISHED: begin
command_finished <= 1;
if (!execute_command) begin
`ifdef VERBOSE $display ("Execute Command is low"); `endif
command_finished <= 0;
state <= IDLE;
end
end
endcase
if (w_out_en && w_out_status == `PERIPH_INTERRUPT) begin
`ifdef VERBOSE $display("TB: Output Handler Recieved interrupt"); `endif
`ifdef VERBOSE $display("TB:\tcommand: %h", w_out_status); `endif
`ifdef VERBOSE $display("TB:\taddress: %h", w_out_address); `endif
`ifdef VERBOSE $display("TB:\tdata: %h", w_out_data); `endif
end
end//not reset
end
endmodule
|
module alu(
input [3:0] ctl,
input [31:0] a, b,
output reg [31:0] out,
output zero);
wire [31:0] sub_ab;
wire [31:0] add_ab;
wire oflow_add;
wire oflow_sub;
wire oflow;
wire slt;
assign zero = (0 == out);
assign sub_ab = a - b;
assign add_ab = a + b;
/*rc_adder #(.N(32)) add0(.a(a), .b(b), .s(add_ab));*/
// overflow occurs (with 2s complement numbers) when
// the operands have the same sign, but the sign of the result is
// different. The actual sign is the opposite of the result.
// It is also dependent on whether addition or subtraction is performed.
assign oflow_add = (a[31] == b[31] && add_ab[31] != a[31]) ? 1 : 0;
assign oflow_sub = (a[31] == b[31] && sub_ab[31] != a[31]) ? 1 : 0;
assign oflow = (ctl == 4'b0010) ? oflow_add : oflow_sub;
// set if less than, 2s compliment 32-bit numbers
assign slt = oflow_sub ? ~(a[31]) : a[31];
always @(*) begin
case (ctl)
4'd2: out <= add_ab; /* add */
4'd0: out <= a & b; /* and */
4'd12: out <= ~(a | b); /* nor */
4'd1: out <= a | b; /* or */
4'd7: out <= {{31{1'b0}}, slt}; /* slt */
4'd6: out <= sub_ab; /* sub */
4'd13: out <= a ^ b; /* xor */
default: out <= 0;
endcase
end
endmodule
|
module ym_timer #(parameter cnt_width = 8, mult_width = 1) (
input CLK,
input TICK_144,
input nRESET,
input [cnt_width-1:0] LOAD_VALUE,
input LOAD,
input CLR_FLAG,
input SET_RUN,
input CLR_RUN,
output reg OVF_FLAG,
output reg OVF
);
reg RUN;
reg [mult_width-1:0] MULT;
reg [cnt_width-1:0] CNT;
reg [mult_width+cnt_width-1:0] NEXT, INIT;
always @(posedge CLK)
begin
if (CLR_RUN || !nRESET)
RUN <= 0;
else if (SET_RUN || LOAD)
RUN <= 1;
if (CLR_FLAG || !nRESET)
OVF_FLAG <= 0;
else if (OVF)
OVF_FLAG <= 1;
if (TICK_144)
begin
if (LOAD)
begin
MULT <= { (mult_width){1'b0} };
CNT <= LOAD_VALUE;
end
else if (RUN)
{ CNT, MULT } <= OVF ? INIT : NEXT;
end
end
always @(*)
begin
{ OVF, NEXT } <= { 1'b0, CNT, MULT } + 1'b1;
INIT <= { LOAD_VALUE, { (mult_width){1'b0} } };
end
endmodule
|
module sky130_fd_sc_ls__sdfstp (
Q ,
CLK ,
D ,
SCD ,
SCE ,
SET_B
);
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input SET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
|
module sky130_fd_sc_ls__or3b_1 (
X ,
A ,
B ,
C_N ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input C_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__or3b base (
.X(X),
.A(A),
.B(B),
.C_N(C_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
|
module sky130_fd_sc_ls__or3b_1 (
X ,
A ,
B ,
C_N
);
output X ;
input A ;
input B ;
input C_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__or3b base (
.X(X),
.A(A),
.B(B),
.C_N(C_N)
);
endmodule
|
module rbo_test
(
input clk,
output reg CAL,
output CS,
output reg IS1,
output reg IS2,
output reg LE,
output reg R12,
output reg RBI,
output reg RESET,
output reg RPHI1,
output reg RPHI2,
output reg SBI,
output reg SEB,
output reg SPHI1,
output reg SPHI2,
output reg SR,
output [15:0]Aref,
output [15:0]RG,
output [15:0]Vana,
output [15:0]Vthr,
input reset_gen
);
reg [31:0]counter;
reg [7:0]stage;
reg [15:0]stage_iter;
assign CS=0;
assign Vthr=16'H0025;
assign Aref=16'H0033;
assign Vana=16'H0066;
assign RG=16'H0033;
always @(posedge clk) begin
if(reset_gen == 1) begin
counter <= 0;
stage <= 0;
stage_iter <= 0;
end
else begin
if(stage == 0) begin
if(counter == 0) begin
CAL <= 0;
SBI <= 0;
SPHI1 <= 0;
SPHI2 <= 0;
SEB <= 1;
IS1 <= 1;
IS2 <= 0;
SR <= 1;
RESET <= 1;
R12 <= 1;
RBI <= 0;
RPHI1 <= 1;
RPHI2 <= 1;
LE <= 0;
end
if(counter == 7) begin
RBI <= 1;
end
if(counter == 16) begin
RBI <= 0;
end
if(counter == 22) begin
RPHI1 <= 0;
RPHI2 <= 0;
end
if(counter == 24) begin
RBI <= 1;
end
if(counter == 25) begin
RPHI1 <= 1;
end
if(counter == 26) begin
RPHI1 <= 0;
end
if(counter == 27) begin
RBI <= 0;
end
if(counter == 28) begin
RPHI2 <= 1;
end
if(counter == 29) begin
RPHI2 <= 0;
end
if(counter == 29) begin
if(stage_iter == 0) begin
stage <= (stage + 1) % 2;
stage_iter <= 0;
end
else begin
stage_iter <= stage_iter + 1;
end
counter <= 0;
end
else begin
counter <= counter + 1;
end
end
if(stage == 1) begin
if(counter == 0) begin
CAL <= 0;
SBI <= 0;
SPHI1 <= 0;
SPHI2 <= 0;
SEB <= 1;
IS1 <= 1;
IS2 <= 0;
SR <= 1;
RESET <= 1;
R12 <= 1;
RBI <= 0;
RPHI1 <= 1;
RPHI2 <= 0;
LE <= 0;
end
if(counter == 1) begin
RPHI1 <= 0;
end
if(counter == 2) begin
RPHI2 <= 1;
end
if(counter == 3) begin
RPHI2 <= 0;
end
if(counter == 3) begin
if(stage_iter == 128) begin
stage <= (stage + 1) % 2;
stage_iter <= 0;
end
else begin
stage_iter <= stage_iter + 1;
end
counter <= 0;
end
else begin
counter <= counter + 1;
end
end
end
end
endmodule
|
module test_processor();
reg clk,reset;
wire [15:0] IR,ALUreg_wire,A_out_wire,B_out_wire,PC_out_wire,ALU_out_wire;
wire N, Z, P,Mux11,wrf,wpc,wir,lccr,wmem,wa,wb, lalu;
wire [1:0] Mux2,Mux4,Mux5,Mux6,Mux7,aluop,alushop;
wire [2:0] Mux3;
wire [4:0] StateID;
lc_3b_processor processor1(clk,reset,IR,N,Z,P,StateID,Mux1,Mux2,Mux3,Mux4,Mux5,Mux6,Mux7,Mux11,wrf,wpc,wir,lccr,aluop,alushop,
wmem,ALUreg_wire,A_out_wire,B_out_wire,PC_out_wire,ALU_out_wire,wa,wb, lalu);
initial begin
$dumpfile("test.vcd");
$dumpvars(0);
clk = 0;
reset = 0;
#15
reset = 1;
#500
$finish;
end
always begin
#5
clk = ~clk;
end
endmodule
|
module lc_3b_processor(clk,reset,IR,N,Z,P,StateID,Mux1,Mux2,Mux3,Mux4,Mux5,Mux6,Mux7,Mux11,wrf,wpc,wir,lccr,aluop,alushop,
wmem,ALUreg_wire,A_out_wire,B_out_wire,PC_out_wire,ALU_out_wire,wa,wb, lalu);
input clk,reset;
output [15:0] IR;
output N, Z, P;
output [4:0] StateID;
output Mux1;
output [1:0] Mux2;
output [2:0] Mux3;
output [1:0] Mux4;
output [1:0] Mux5;
output [1:0] Mux6;
output [1:0] Mux7;
output Mux11;
output wrf;
output wpc;
output wir;
output lccr;
output [1:0] aluop;
output [1:0] alushop;
output wmem;
output wire wa,wb, lalu;
output [15:0]ALUreg_wire,A_out_wire,B_out_wire,PC_out_wire,ALU_out_wire;
datapath d1(.reset(reset),.clk(clk),.IR(IR),.N(N), .P(P), .Z(Z), .Mux1(Mux1), .Mux2(Mux2), .Mux3(Mux3), .Mux4(Mux4),
.Mux5(Mux5), .Mux6(Mux6), .Mux7(Mux7), .Mux11(Mux11), .wrf(wrf), .wpc(wpc), .wir(wir), .lccr(lccr), .aluop(aluop),
.alushop(alushop), .wmem(wmem), .ALUreg_wire(ALUreg_wire), .A_out_wire(A_out_wire), .B_out_wire(B_out_wire),
.PC_out_wire(PC_out_wire), .ALU_out_wire(ALU_out_wire),.wa(wa),.wb(wb), .lalu(lalu));
controller c1(.reset(reset),.clk(clk), .IR(IR), .N(N), .Z(Z), .P(P), .StateID(StateID), .Mux1(Mux1), .Mux2(Mux2), .Mux3(Mux3),
.Mux4(Mux4), .Mux5(Mux5), .Mux6(Mux6), .Mux7(Mux7), .Mux11(Mux11), .wrf(wrf), .wpc(wpc), .wir(wir),
.lccr(lccr), .aluop(aluop), .alushop(alushop), .wmem(wmem),.wa(wa),.wb(wb), .lalu(lalu));
endmodule
|
module controller(reset,clk, IR, N, Z, P, StateID, Mux1, Mux2, Mux3, Mux4, Mux5, Mux6, Mux7, Mux11, wrf, wpc, wir,wa,wb, lccr, aluop, alushop, wmem, nextStateID, lalu); // Implements the designed controller for LC-3b.
input [15:0] IR;
input clk, N, Z, P,reset;
output reg [4:0] StateID;
output reg Mux1;
output reg [1:0] Mux2;
output reg [2:0] Mux3;
output reg [1:0] Mux4;
output reg [1:0] Mux5;
output reg [1:0] Mux6;
output reg [1:0] Mux7;
output reg Mux11;
output reg wrf;
output reg wpc;
output reg wir;
output reg wa;
output reg wb;
output reg lalu;
output reg lccr;
output reg [1:0] aluop;
output reg [1:0] alushop;
output reg wmem;
output reg [4:0] nextStateID;
always@(negedge clk) begin
case(StateID)
1: begin
Mux1 = 1'b1;
Mux2 = 2'b11;
Mux3 = 3'b111;
Mux4 = 2'b01;
Mux5 = 2'b01;
Mux6 = 2'b10;
Mux7 = 2'b10;
Mux11 = 1'b1;
wrf = 1'b1;
wpc = 1'b0;
wir = 1'b0;
lccr = 1'b1;
aluop = 2'b00;
alushop = 2'b11;
wmem = 1'b1;
wa = 1'b1;
wb = 1'b1;
lalu = 1'b1;
end
2: begin
Mux1 = 1'b1;
Mux2 = 2'b11;
Mux3 = 3'b000;
Mux4 = 2'b11;
Mux5 = 2'b11;
Mux6 = 2'b11;
Mux7 = 2'b11;
Mux11 = 1'b1;
wrf = 1'b1;
wpc = 1'b1;
wir = 1'b1;
lccr = 1'b1;
aluop = 2'b11;
alushop = 2'b11;
wmem = 1'b1;
wa = 1'b0;
wb = 1'b0;
lalu = 1'b1;
end
3: begin
Mux1 = 1'b1;
Mux2 = 2'b11;
Mux3 = 3'b000;
Mux4 = 2'b00;
Mux5 = 2'b00;
Mux6 = 2'b11;
Mux7 = 2'b11;
Mux11 = 1'b1;
wrf = 1'b1;
wpc = 1'b1;
wir = 1'b1;
lccr = 1'b0;
aluop = {IR[15], IR[14]};
alushop = {IR[5], IR[4]};
wmem = 1'b1;
wa = 1'b1;
wb = 1'b1;
lalu = 1'b0;
end
4: begin
Mux1 = 1'b1;
Mux2 = 2'b01;
Mux3 = 3'b111;
Mux4 = 2'b11;
Mux5 = 2'b11;
Mux6 = 2'b11;
Mux7 = 2'b11;
Mux11 = 1'b0;
wrf = 1'b0;
wpc = 1'b1;
wir = 1'b1;
lccr = 1'b1;
aluop = 2'b11;
alushop = 2'b11;
wmem = 1'b1;
wa = 1'b1;
wb = 1'b1;
lalu = 1'b1;
end
5: begin
Mux1 = 1'b1;
Mux2 = 2'b11;
Mux3 = 3'b011;
Mux4 = 2'b01;
Mux5 = 2'b00;
Mux6 = 2'b00;
Mux7 = 2'b11;
Mux11 = 1'b1;
wrf = 1'b1;
wpc = 1'b0;
wir = 1'b1;
lccr = 1'b1;
aluop = 2'b00;
alushop = 2'b11;
wmem = 1'b1;
wa = 1'b1;
wb = 1'b1;
lalu = 1'b1;
end
6: begin
Mux1 = 1'b1;
Mux2 = 2'b11;
Mux3 = 3'b111;
Mux4 = 2'b11;
Mux5 = 2'b11;
Mux6 = 2'b11;
Mux7 = 2'b11;
Mux11 = 1'b1;
wrf = 1'b1;
wpc = 1'b0;
wir = 1'b1;
lccr = 1'b1;
aluop = 2'b11;
alushop = 2'b11;
wmem = 1'b1;
wa = 1'b1;
wb = 1'b1;
lalu = 1'b1;
end
7: begin
Mux1 = 1'b1;
Mux2 = 2'b10;
Mux3 = 3'b111;
Mux4 = 2'b11;
Mux5 = 2'b11;
Mux6 = 2'b11;
Mux7 = 2'b11;
Mux11 = 1'b1;
wrf = 1'b0;
wpc = 1'b1;
wir = 1'b1;
lccr = 1'b1;
aluop = 2'b11;
alushop = 2'b11;
wmem = 1'b1;
wa = 1'b1;
wb = 1'b1;
lalu = 1'b1;
end
8: begin
Mux1 = 1'b1;
Mux2 = 2'b11;
Mux3 = 3'b001;
Mux4 = 2'b01;
Mux5 = 2'b00;
Mux6 = 2'b01;
Mux7 = 2'b11;
Mux11 = 1'b1;
wrf = 1'b1;
wpc = 1'b0;
wir = 1'b1;
lccr = 1'b1;
aluop = 2'b00;
alushop = 2'b11;
wmem = 1'b1;
wa = 1'b1;
wb = 1'b1;
lalu = 1'b1;
end
9: begin
Mux1 = 1'b1;
Mux2 = 2'b11;
Mux3 = 3'b101;
Mux4 = 2'b00;
Mux5 = 2'b00;
Mux6 = 2'b11;
Mux7 = 2'b11;
Mux11 = 1'b1;
wrf = 1'b1;
wpc = 1'b1;
wir = 1'b1;
lccr = 1'b1;
aluop = 2'b00;
alushop = 2'b11;
wmem = 1'b1;
wa = 1'b1;
wb = 1'b1;
lalu = 1'b0;
end
10: begin
Mux1 = 1'b1;
Mux2 = 2'b11;
Mux3 = 3'b111;
Mux4 = 2'b11;
Mux5 = 2'b11;
Mux6 = 2'b11;
Mux7 = 2'b01;
Mux11 = 1'b1;
wrf = 1'b1;
wpc = 1'b1;
wir = 1'b1;
lccr = 1'b1;
aluop = 2'b11;
alushop = 2'b11;
wmem = 1'b1;
wa = 1'b1;
wb = 1'b1;
lalu = 1'b1;
end
11: begin
Mux1 = 1'b1;
Mux2 = 2'b00;
Mux3 = 3'b111;
Mux4 = 2'b10;
Mux5 = 2'b10;
Mux6 = 2'b11;
Mux7 = 2'b11;
Mux11 = 1'b0;
wrf = 1'b0;
wpc = 1'b1;
wir = 1'b1;
lccr = 1'b0;
aluop = 2'b00;
alushop = 2'b11;
wmem = 1'b1;
wa = 1'b1;
wb = 1'b1;
lalu = 1'b1;
end
12: begin
Mux1 = 1'b1;
Mux2 = 2'b11;
Mux3 = 3'b010;
Mux4 = 2'b00;
Mux5 = 2'b00;
Mux6 = 2'b11;
Mux7 = 2'b11;
Mux11 = 1'b1;
wrf = 1'b1;
wpc = 1'b1;
wir = 1'b1;
lccr = 1'b1;
aluop = 2'b00;
alushop = 2'b11;
wmem = 1'b1;
wa = 1'b1;
wb = 1'b1;
lalu = 1'b0;
end
13: begin
Mux1 = 1'b1;
Mux2 = 2'b11;
Mux3 = 3'b011;
Mux4 = 2'b01;
Mux5 = 2'b00;
Mux6 = 2'b11;
Mux7 = 2'b11;
Mux11 = 1'b1;
wrf = 1'b1;
wpc = 1'b1;
wir = 1'b1;
lccr = 1'b0;
aluop = 2'b00;
alushop = 2'b11;
wmem = 1'b1;
wa = 1'b1;
wb = 1'b1;
lalu = 1'b0;
end
14: begin
Mux1 = 1'b1;
Mux2 = 2'b01;
Mux3 = 3'b111;
Mux4 = 2'b11;
Mux5 = 2'b11;
Mux6 = 2'b11;
Mux7 = 2'b11;
Mux11 = 1'b0;
wrf = 1'b0;
wpc = 1'b1;
wir = 1'b1;
lccr = 1'b1;
aluop = 2'b11;
alushop = 2'b11;
wmem = 1'b1;
wa = 1'b1;
wb = 1'b1;
lalu = 1'b1;
end
15: begin
Mux1 = 1'b0;
Mux2 = 2'b11;
Mux3 = 3'b111;
Mux4 = 2'b11;
Mux5 = 2'b11;
Mux6 = 2'b11;
Mux7 = 2'b11;
Mux11 = 1'b1;
wrf = 1'b1;
wpc = 1'b1;
wir = 1'b1;
lccr = 1'b1;
aluop = 2'b11;
alushop = 2'b11;
wmem = 1'b1;
wa = 1'b0;
wb = 1'b0;
lalu = 1'b1;
end
16: begin
Mux1 = 1'b0;
Mux2 = 2'b11;
Mux3 = 3'b101;
Mux4 = 2'b00;
Mux5 = 2'b00;
Mux6 = 2'b11;
Mux7 = 2'b11;
Mux11 = 1'b1;
wrf = 1'b1;
wpc = 1'b1;
wir = 1'b1;
lccr = 1'b1;
aluop = 2'b00;
alushop = 2'b11;
wmem = 1'b1;
wa = 1'b1;
wb = 1'b1;
end
17: begin
Mux1 = 1'b1;
Mux2 = 2'b11;
Mux3 = 3'b111;
Mux4 = 2'b11;
Mux5 = 2'b11;
Mux6 = 2'b11;
Mux7 = 2'b01;
Mux11 = 1'b1;
wrf = 1'b1;
wpc = 1'b1;
wir = 1'b1;
lccr = 1'b1;
aluop = 2'b11;
alushop = 2'b11;
wmem = 1'b0;
wa = 1'b1;
wb = 1'b1;
end
18: begin
Mux1 = 1'b1;
Mux2 = 2'b11;
Mux3 = 3'b010;
Mux4 = 2'b00;
Mux5 = 2'b00;
Mux6 = 2'b11;
Mux7 = 2'b11;
Mux11 = 1'b1;
wrf = 1'b1;
wpc = 1'b1;
wir = 1'b1;
lccr = 1'b1;
aluop = 2'b00;
alushop = 2'b11;
wmem = 1'b1;
wa = 1'b1;
wb = 1'b1;
end
default: begin
Mux1 = 1'b0;
Mux2 = 2'b00;
Mux3 = 3'b000;
Mux4 = 2'b00;
Mux5 = 2'b00;
Mux6 = 2'b00;
Mux7 = 2'b00;
Mux11 = 1'b0;
wrf = 1'b1;
wpc = 1'b0;
wir = 1'b0;
lccr = 1'b1;
aluop = 2'b00;
alushop = 2'b00;
wmem = 1'b1;
wa = 1'b1;
wb = 1'b1;
end
endcase
StateID = nextStateID;
end
always@(*) begin
if(reset ==0)
StateID = 0;
else
begin
case(StateID)
0: nextStateID=1;
1: begin
case(IR[15:12])
0: nextStateID=5;
4: nextStateID=7;
3: nextStateID=15;
7: nextStateID=15;
default: nextStateID=2;
endcase
end
2: begin
case(IR[15:12])
12: nextStateID=6;
2: nextStateID=9;
6: nextStateID=12;
4: nextStateID=8;
14: nextStateID=13;
default: nextStateID=3;
endcase
end
3: nextStateID=4;
4: nextStateID=1;
5: nextStateID=1;
6: nextStateID=1;
7: nextStateID=2;
8: nextStateID=1;
9: nextStateID=10;
10: nextStateID=11;
11: nextStateID=1;
12: nextStateID=10;
13: nextStateID=14;
14: nextStateID=1;
15: begin
case(IR[15:12])
3: StateID = 16;
7: StateID = 18;
default: nextStateID=1;
endcase
end
16: nextStateID=17;
17: nextStateID=1;
18: nextStateID=17;
default: nextStateID=1;
endcase
end
end
endmodule
|
module datapath(reset,clk,IR,N,P,Z,Mux1,Mux2,Mux3,Mux4,Mux5,Mux6,Mux7,Mux11,wrf, wpc, wir, wa,wb,lccr, aluop, alushop, wmem
,ALUreg_wire,A_out_wire,B_out_wire,PC_out_wire,ALU_out_wire, mem_out_wire, mdr_wire, lalu);
input clk,reset;
output [15:0]IR;
input Mux1,Mux11;
input [1:0] Mux2,Mux4,Mux5,Mux6,Mux7;
input [2:0]Mux3;
output N,P,Z;
input wrf, wpc, wir, lccr, wmem,wa,wb, lalu;
input[1:0] aluop, alushop;
output [15:0]ALUreg_wire,A_out_wire,B_out_wire,PC_out_wire,ALU_out_wire;//
wire [15:0] A_out_wire,ALUreg_wire,PC_out_wire,mem_address_wire;
wire[15:0] mux6_in_1_wire,mux6_in_0_wire;
output wire[15:0] mem_out_wire, mdr_wire,outir;
mux16x2 m7(.data0(A_out_wire),.data1(ALUreg_wire),.data2(PC_out_wire),.data3(PC_out_wire),.selectinput(Mux7),.out(mem_address_wire));//data3 is never slelcted(just done this to prevent latch formation
mem16 memory(.outir(outir),.address(mem_address_wire), .write(wmem),.clk(clk), .in(A_out_wire),.out(mem_out_wire),.ir14(IR[14]), .reset(reset));
latch16 inst_reg(.in(outir),.out(IR),.write(wir));
latch16 mdr(.in(mem_out_wire),.out(mdr_wire),.write(1'b0));
wire [2:0] IA1_wire,WA_wire;
mux3x1 m1(.data0(IR[11:9]),.data1(IR[8:6]),.selectinput(Mux1),.out(IA1_wire));
mux3x1 m11(.data0(IR[11:9]),.data1(3'd7),.selectinput(Mux11),.out(WA_wire)); // Is this right ?
wire [15:0]reg_file_data_in_wire;
mux16x2 m2(.data0(mdr_wire),.data1(ALUreg_wire),.data2(PC_out_wire),.data3(PC_out_wire),.selectinput(Mux2),.out(reg_file_data_in_wire));
wire[15:0] A_in_wire,B_in_wire,regfile_out2_wire;
register_file rf1(.clk(clk), .out1(A_in_wire), .out2(regfile_out2_wire),
.readAdd1(IA1_wire),.readAdd2(IR[2:0]),.write(wrf),.writeAdd(WA_wire),.in(reg_file_data_in_wire), .reset(reset));
wire[15:0] sext11_0_wire, sext8_0_wire,sext5_0_wire;
sext12 s11_0(.in(IR[11:0]),.out(sext11_0_wire));
sext9 s8_0(.in(IR[8:0]),.out(sext8_0_wire));
sext6 s5_0(.in(IR[5:0]),.out(sext5_0_wire));
wire[15:0] lshf11_0_wire, lshf8_0_wire,lshf5_0_wire;
lshift1 lshf11_0(.in(sext11_0_wire),.out(lshf11_0_wire));
lshift1 lshf8_0(.in(sext8_0_wire),.out(lshf8_0_wire));
lshift1 lshf5_0(.in(sext5_0_wire),.out(lshf5_0_wire));
wire [15:0] mux3_in_0_wire;
mux16x1 m8(.data0(regfile_out2_wire),.data1(sext5_0_wire),.selectinput(IR[5]),.out(mux3_in_0_wire));
mux16x3 m3(.data0(mux3_in_0_wire),.data1(lshf11_0_wire),.data2(lshf5_0_wire),.data3(lshf8_0_wire),.data4(sext11_0_wire),.data5(sext5_0_wire),.selectinput(Mux3),.out(B_in_wire));
wire[15:0] B_out_wire;
register16 A (.clk(clk), .out(A_out_wire),.in(A_in_wire),.write(wa),.reset(reset));
register16 B (.clk(clk), .out(B_out_wire),.in(B_in_wire),.write(wb),.reset(reset));
wire[15:0] ALU_in_1_wire,ALU_in_2_wire;
mux16x2 m4(.data0(A_out_wire),.data1(PC_out_wire),.data2(mdr_wire),.data3(mdr_wire),.selectinput(Mux4),.out(ALU_in_1_wire));
mux16x2 m5 (.data0(B_out_wire),.data1(16'd2),.data2(16'd0),.data3(16'd0),.selectinput(Mux5),.out(ALU_in_2_wire));
wire[15:0]ALU_out_wire;
wire zero,negative,positive;
alu ALU(.in1(ALU_in_1_wire), .in2(ALU_in_2_wire),.op(aluop), .shop(alushop),.shift(IR[3:0]), .out(ALU_out_wire), .zero(zero),.positive(positive),.negative(negative));
register1b neg_reg(.clk(clk),.out(N),.in(negative),.write(lccr),.reset(reset));
register1b pos_reg(.clk(clk),.out(P),.in(positive),.write(lccr),.reset(reset));
register1b zero_reg(.clk(clk),.out(Z),.in(zero),.write(lccr),.reset(reset));
wire[15:0] PC_in_wire;
register16 PC (.clk(clk), .out(PC_out_wire),.in(PC_in_wire),.write(wpc),.reset(reset));
wire hc;
assign hc =( (IR[11]&&N)|| (IR[10]&&Z)||(IR[9]&&P));
mux16x1 m9(.data0(PC_out_wire),.data1(ALU_out_wire),.selectinput(hc),.out(mux6_in_0_wire));
register16 ALUreg(.clk(clk),.out(ALUreg_wire),.in(ALU_out_wire),.write(lalu),.reset(reset));
mux16x1 m10(.data0(ALU_out_wire),.data1(A_out_wire),.selectinput(IR[11]),.out(mux6_in_1_wire));
mux16x2 m6(.data0(mux6_in_0_wire),.data1(mux6_in_1_wire),.data2(ALU_out_wire),.data3(A_out_wire),.selectinput(Mux6),.out(PC_in_wire));
endmodule
|
module sext9(in,out);
input [8:0] in;
output[15:0] out;
assign out= {{7{in[8]}},in[8:0]};
endmodule
|
module sext12(in,out);
input [11:0] in;
output[15:0] out;
assign out= {{4{in[11]}},in[11:0]};
endmodule
|
module sext6(in,out);
input [5:0] in;
output[15:0] out;
assign out= {{10{in[5]}},in[5:0]};
endmodule
|
module register16(clk, out, in, write, reset); // Negedge-triggered flipflop register with active-low write signal and reset
output reg [15:0] out;
input [15:0] in;
input clk, write, reset;
always@(posedge clk) begin
if(reset==0) begin
out = 16'b0;
end
else if(write == 1'b0) begin
out = in;
end
end
endmodule
|
module register1b(clk, out, in, write, reset); // Negedge-triggered 1 bit flipflop register for with active-low write signal and reset
output reg out;
input in;
input clk, write, reset;
always@(posedge clk) begin
if(reset==0) begin
out = 1'b0;
end
else if(write == 1'b0) begin
out = in;
end
end
endmodule
|
module register_file(clk, out1, out2, readAdd1, readAdd2, write, writeAdd, in, reset);
output [15:0] out1, out2;
input [15:0] in;
input [2:0] readAdd1, readAdd2, writeAdd;
input write, clk, reset;
wire [15:0] data0, data1, data2, data3, data4, data5, data6, data7;
wire [7:0] writeLinesInit, writeLines;
demux8 dem(writeAdd, writeLinesInit);
mux16x8 mux1(data0, data1, data2, data3, data4, data5, data6, data7, readAdd1, out1);
mux16x8 mux2(data0, data1, data2, data3, data4, data5, data6, data7, readAdd2, out2);
or a0(writeLines[0], write, ~writeLinesInit[0]);
or a1(writeLines[1], write, ~writeLinesInit[1]);
or a2(writeLines[2], write, ~writeLinesInit[2]);
or a3(writeLines[3], write, ~writeLinesInit[3]);
or a4(writeLines[4], write, ~writeLinesInit[4]);
or a5(writeLines[5], write, ~writeLinesInit[5]);
or a6(writeLines[6], write, ~writeLinesInit[6]);
or a7(writeLines[7], write, ~writeLinesInit[7]);
register16 r0(clk, data0, in, writeLines[0], reset);
register16 r1(clk, data1, in, writeLines[1], reset);
register16 r2(clk, data2, in, writeLines[2], reset);
register16 r3(clk, data3, in, writeLines[3], reset);
register16 r4(clk, data4, in, writeLines[4], reset);
register16 r5(clk, data5, in, writeLines[5], reset);
register16 r6(clk, data6, in, writeLines[6], reset);
register16 r7(clk, data7, in, writeLines[7], reset);
endmodule
|
module mux16x1(data0,data1,selectinput,out);//used in mux 1,8,9,10,11
input [15:0] data0,data1;
input selectinput;
output reg [15:0] out;
always @(*)
begin
case (selectinput)
0:
out = data0;
1:
out = data1;
default:
out = data0;
endcase
end
endmodule
|
module mux3x1(data0,data1,selectinput,out);//used in mux 1,8,9,10,11
input [2:0] data0,data1;
input selectinput;
output reg [2:0] out;
always @(*)
begin
case (selectinput)
0:
out = data0;
1:
out = data1;
default:
out = data0;
endcase
end
endmodule
|
module mux16x2(data0,data1,data2,data3,selectinput,out);//used in mux 2,4,5,6,7
input [15:0] data0,data1,data2,data3;
input [1:0]selectinput;
output reg [15:0] out;
always @(*)
begin
case (selectinput)
0:
out = data0;
1:
out = data1;
2:
out = data2;
3:
out = data3;
default:
out = data0;
endcase
end
endmodule
|
module mux16x3(data0,data1,data2,data3,data4,data5,selectinput,out);//used in mux 2,4,5,6,7
input [15:0] data0,data1,data2,data3,data4,data5;
input [2:0]selectinput;
output reg [15:0] out;
always @(*)
begin
case (selectinput)
0:
out = data0;
1:
out = data1;
2:
out = data2;
3:
out = data3;
4:
out = data4;
5:
out = data5;
default:
out = data0;
endcase
end
endmodule
|
module muxalu(data0, data1, data2, data3, data4, data5, op, shop, out); // 8-16bit-input mux
output reg [15:0] out;
input [15:0] data0, data1, data2, data3, data4, data5;
input [1:0] op;
input [1:0]shop;
always@(*) begin
case(op)
0: out = data0;
1: out = data1;
2: out = data2;
default:
case(shop)
0: out = data3;
1: out = data4;
3: out = data5;
default: out = data5;
endcase
endcase
end
endmodule
|
module mux16x8(data0, data1, data2, data3, data4, data5, data6, data7, selectInput, out); // 8-16bit-input mux
output reg [15:0] out;
input [15:0] data0, data1, data2, data3, data4, data5, data6, data7;
input [2:0] selectInput;
always@(data0 or data1 or data2 or data3 or data4 or data5 or data6 or data7 or selectInput) begin
case(selectInput)
0: out = data0;
1: out = data1;
2: out = data2;
3: out = data3;
4: out = data4;
5: out = data5;
6: out = data6;
7: out = data7;
endcase
end
endmodule
|
module memory1(reset,address,in,out,write,clk, testWire); // LSB
input [7:0] in;
input clk,write,reset;
input [14:0] address;
output reg [7:0] out;
output wire [7:0] testWire;
reg [7:0] mem [0:255];
integer i;
assign testWire = mem[0];
always @(negedge clk)
begin
out = mem[address];
if(reset== 1'b0)
begin
for(i=0;i<256;i=i+1)
mem [i] = 0;
mem[0] = 8'b00111111;
mem[1] = 8'b00000000;
mem[2] = 8'b10000001;
end
else
if(write ==1'b0)
begin
mem[address] <= in;
end
end
endmodule
|
module memory2(reset,address,in,out,write,clk, testWire); // MSB
input [7:0] in;
input clk,write,reset;
input [14:0] address;
output reg [7:0] out;
output wire [7:0] testWire;
reg [7:0] mem [0:255];
integer i;
assign testWire = mem[0];
always @(negedge clk)
begin
out = mem[address];
if(reset== 1'b0)
begin
for(i=0;i<256;i=i+1)
mem [i] = 0;
mem[0] = 8'b10010010;
mem[1] = 8'b01100100;
mem[2] = 8'b00010110;
end
if(write ==1'b0)
begin
mem[address] <= in;
end
end
endmodule
|
module mem16(reset,address, write,clk, in, out,ir14,outir);
input [15:0] in;
input [15:0] address;
input write,clk,ir14,reset;
output reg [15:0] out;
output [15:0]outir;
reg wreven,wrodd;
wire [7:0] outeven,outodd;
reg [7:0] ineven,inodd;
memory1 even(.reset(reset),.address(address[15:1]),.in(ineven),.out(outeven),.clk(clk),.write(wreven));
memory2 odd (.reset(reset),.address(address[15:1]),.in(inodd),.out(outodd),.clk(clk),.write(wrodd));
//for in signals of individual memories
always @(*)
begin
if(ir14==0)
begin
ineven<=in[7:0];
inodd<=in[7:0];
end
else
begin
ineven<= in[7:0];
inodd<=in[15:8];
end
end
//-----------------------------------------------
assign outir[15:8] = outodd;
assign outir[7:0] = outeven;
//for out signals of individual memories
always @(*)
begin
if(ir14 ==1'b1)
begin
out[15:8]<=outodd;
out[7:0]<=outeven;
end
else
if(address[0]==0)
begin
out<= {{8{outeven[7]}},outeven[7:0]};
end
else
begin
out<= {{8{outodd[7]}},outodd[7:0]};
end
end
//-------------------------------------------------
//for write signal
always @(*)
begin
if(ir14==0&&address[0]==1'b1)
begin
wreven<=1'b1;
end
else
begin
wreven<=write;
end
end
always @(*)
begin
if(ir14==0&&address[0]==1'b0)
begin
wrodd<=1'b1;
end
else
begin
wrodd<=write;
end
end
endmodule
|
module lshift1(in,out);
input [15:0] in;
output [15:0] out;
assign out = {in[14:0],1'b0};
endmodule
|
module latch16(in,out,write);
input [15:0]in;
input write;//active low wrie
output reg [15:0] out;
always @(*)
begin
if(write == 1'b0)
out = in;
else
out = out;
end
endmodule
|
module demux8(selectInput, out); // 8-output demux
output reg [7:0] out;
input [2:0] selectInput;
always@(selectInput) begin
case(selectInput)
0: out = 8'b00000001;
1: out = 8'b00000010;
2: out = 8'b00000100;
3: out = 8'b00001000;
4: out = 8'b00010000;
5: out = 8'b00100000;
6: out = 8'b01000000;
7: out = 8'b10000000;
endcase
end
endmodule
|
module alu(in1, in2, op,shop,shift, out, zero, positive, negative);
output [15:0] out;
input [15:0] in1, in2;
input [1:0] op,shop;
input [3:0] shift;
output zero, positive,negative;
nor n1(zero,out[0],out[1],out[2],out[3],out[4],out[5],out[6],out[7],out[8],out[9],out[10],out[11],out[12],out[13],out[14],out[15]);
assign positive = (~out[15])&(~zero);
assign negative = out[15];
wire [15:0] outAdd, outAnd, outXor, outLshf, outRshfl, outRshfa;
muxalu m1(outAdd, outAnd, outXor, outLshf, outRshfl, outRshfa, op, shop, out);
adder16 add1(in1, in2, outAdd);
and16 and1(in1, in2, outAnd);
xor16 xor1(in1, in2, outXor);
left_shift lshf1(in1, outLshf, shift);
right_shift_logical rshfl1(in1, outRshfl, shift);
right_shift_arithmetic rshfa1(in1, outRshfa, shift);
endmodule
|
module adder16(in1, in2 , out); // Implements a full 16-bit adder
input [15:0] in1, in2;
output [15:0] out;
assign out = in1 + in2;
endmodule
|
module and16(in1, in2, out); // Implements bitwise AND for two 16-bit numbers
input [15:0] in1, in2;
output [15:0] out;
assign out = in1 & in2;
endmodule
|
module left_shift(in, out, shift);
output [15:0] out;
input [15:0] in;
input [3:0] shift;
assign out = in << shift;
endmodule
|
module right_shift_arithmetic(in, out, shift);
output reg [15:0] out;
input [15:0] in;
input [3:0] shift;
always @(*) begin
case(shift)
4'd0: out=in;
4'd1: out={in[15],in[15:1]};
4'd2: out={{2{in[15]}},in[15:2]};
4'd3: out={{3{in[15]}},in[15:3]};
4'd4: out={{4{in[15]}},in[15:4]};
4'd5: out={{5{in[15]}},in[15:5]};
4'd6: out={{6{in[15]}},in[15:6]};
4'd7: out={{7{in[15]}},in[15:7]};
4'd8: out={{8{in[15]}},in[15:8]};
4'd9: out={{9{in[15]}},in[15:9]};
4'd10: out={{10{in[15]}},in[15:10]};
4'd11: out={{11{in[15]}},in[15:11]};
4'd12: out={{12{in[15]}},in[15:12]};
4'd13: out={{13{in[15]}},in[15:13]};
4'd14: out={{14{in[15]}},in[15:14]};
4'd15: out={16{in[15]}};
endcase
end
endmodule
|
module right_shift_logical(in, out, shift);
output [15:0] out;
input [15:0] in;
input [3:0] shift;
assign out = in >> shift;
endmodule
|
module xor16(in1, in2, out); // Implements bitwise XOR for two 16-bit numbers
input [15:0] in1, in2;
output [15:0] out;
assign out = in1 ^ in2;
endmodule
|
module top();
// Inputs are registered
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
initial
begin
// Initial state is x for all inputs.
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 VGND = 1'b0;
#40 VNB = 1'b0;
#60 VPB = 1'b0;
#80 VPWR = 1'b0;
#100 VGND = 1'b1;
#120 VNB = 1'b1;
#140 VPB = 1'b1;
#160 VPWR = 1'b1;
#180 VGND = 1'b0;
#200 VNB = 1'b0;
#220 VPB = 1'b0;
#240 VPWR = 1'b0;
#260 VPWR = 1'b1;
#280 VPB = 1'b1;
#300 VNB = 1'b1;
#320 VGND = 1'b1;
#340 VPWR = 1'bx;
#360 VPB = 1'bx;
#380 VNB = 1'bx;
#400 VGND = 1'bx;
end
sky130_fd_sc_ls__fill dut (.VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB));
endmodule
|
module PS2_Controller #(parameter INITIALIZE_MOUSE = 0) (
// Inputs
CLOCK_50,
reset,
the_command,
send_command,
// Bidirectionals
PS2_CLK, // PS2 Clock
PS2_DAT, // PS2 Data
// Outputs
command_was_sent,
error_communication_timed_out,
received_data,
received_data_en // If 1 - new data has been received
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input CLOCK_50;
input reset;
input [7:0] the_command;
input send_command;
// Bidirectionals
inout PS2_CLK;
inout PS2_DAT;
// Outputs
output command_was_sent;
output error_communication_timed_out;
output [7:0] received_data;
output received_data_en;
wire [7:0] the_command_w;
wire send_command_w, command_was_sent_w, error_communication_timed_out_w;
generate
if(INITIALIZE_MOUSE) begin
assign the_command_w = init_done ? the_command : 8'hf4;
assign send_command_w = init_done ? send_command : (!command_was_sent_w && !error_communication_timed_out_w);
assign command_was_sent = init_done ? command_was_sent_w : 0;
assign error_communication_timed_out = init_done ? error_communication_timed_out_w : 1;
reg init_done;
always @(posedge CLOCK_50)
if(reset) init_done <= 0;
else if(command_was_sent_w) init_done <= 1;
end else begin
assign the_command_w = the_command;
assign send_command_w = send_command;
assign command_was_sent = command_was_sent_w;
assign error_communication_timed_out = error_communication_timed_out_w;
end
endgenerate
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
// states
localparam PS2_STATE_0_IDLE = 3'h0,
PS2_STATE_1_DATA_IN = 3'h1,
PS2_STATE_2_COMMAND_OUT = 3'h2,
PS2_STATE_3_END_TRANSFER = 3'h3,
PS2_STATE_4_END_DELAYED = 3'h4;
/*****************************************************************************
* Internal wires and registers Declarations *
*****************************************************************************/
// Internal Wires
wire ps2_clk_posedge;
wire ps2_clk_negedge;
wire start_receiving_data;
wire wait_for_incoming_data;
// Internal Registers
reg [7:0] idle_counter;
reg ps2_clk_reg;
reg ps2_data_reg;
reg last_ps2_clk;
// State Machine Registers
reg [2:0] ns_ps2_transceiver;
reg [2:0] s_ps2_transceiver;
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
always @(posedge CLOCK_50)
begin
if (reset == 1'b1)
s_ps2_transceiver <= PS2_STATE_0_IDLE;
else
s_ps2_transceiver <= ns_ps2_transceiver;
end
always @(*)
begin
// Defaults
ns_ps2_transceiver = PS2_STATE_0_IDLE;
case (s_ps2_transceiver)
PS2_STATE_0_IDLE:
begin
if ((idle_counter == 8'hFF) &&
(send_command == 1'b1))
ns_ps2_transceiver = PS2_STATE_2_COMMAND_OUT;
else if ((ps2_data_reg == 1'b0) && (ps2_clk_posedge == 1'b1))
ns_ps2_transceiver = PS2_STATE_1_DATA_IN;
else
ns_ps2_transceiver = PS2_STATE_0_IDLE;
end
PS2_STATE_1_DATA_IN:
begin
if ((received_data_en == 1'b1)/* && (ps2_clk_posedge == 1'b1)*/)
ns_ps2_transceiver = PS2_STATE_0_IDLE;
else
ns_ps2_transceiver = PS2_STATE_1_DATA_IN;
end
PS2_STATE_2_COMMAND_OUT:
begin
if ((command_was_sent == 1'b1) ||
(error_communication_timed_out == 1'b1))
ns_ps2_transceiver = PS2_STATE_3_END_TRANSFER;
else
ns_ps2_transceiver = PS2_STATE_2_COMMAND_OUT;
end
PS2_STATE_3_END_TRANSFER:
begin
if (send_command == 1'b0)
ns_ps2_transceiver = PS2_STATE_0_IDLE;
else if ((ps2_data_reg == 1'b0) && (ps2_clk_posedge == 1'b1))
ns_ps2_transceiver = PS2_STATE_4_END_DELAYED;
else
ns_ps2_transceiver = PS2_STATE_3_END_TRANSFER;
end
PS2_STATE_4_END_DELAYED:
begin
if (received_data_en == 1'b1)
begin
if (send_command == 1'b0)
ns_ps2_transceiver = PS2_STATE_0_IDLE;
else
ns_ps2_transceiver = PS2_STATE_3_END_TRANSFER;
end
else
ns_ps2_transceiver = PS2_STATE_4_END_DELAYED;
end
default:
ns_ps2_transceiver = PS2_STATE_0_IDLE;
endcase
end
/*****************************************************************************
* Sequential logic *
*****************************************************************************/
always @(posedge CLOCK_50)
begin
if (reset == 1'b1)
begin
last_ps2_clk <= 1'b1;
ps2_clk_reg <= 1'b1;
ps2_data_reg <= 1'b1;
end
else
begin
last_ps2_clk <= ps2_clk_reg;
ps2_clk_reg <= PS2_CLK;
ps2_data_reg <= PS2_DAT;
end
end
always @(posedge CLOCK_50)
begin
if (reset == 1'b1)
idle_counter <= 6'h00;
else if ((s_ps2_transceiver == PS2_STATE_0_IDLE) &&
(idle_counter != 8'hFF))
idle_counter <= idle_counter + 6'h01;
else if (s_ps2_transceiver != PS2_STATE_0_IDLE)
idle_counter <= 6'h00;
end
/*****************************************************************************
* Combinational logic *
*****************************************************************************/
assign ps2_clk_posedge =
((ps2_clk_reg == 1'b1) && (last_ps2_clk == 1'b0)) ? 1'b1 : 1'b0;
assign ps2_clk_negedge =
((ps2_clk_reg == 1'b0) && (last_ps2_clk == 1'b1)) ? 1'b1 : 1'b0;
assign start_receiving_data = (s_ps2_transceiver == PS2_STATE_1_DATA_IN);
assign wait_for_incoming_data =
(s_ps2_transceiver == PS2_STATE_3_END_TRANSFER);
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
Altera_UP_PS2_Data_In PS2_Data_In (
// Inputs
.clk (CLOCK_50),
.reset (reset),
.wait_for_incoming_data (wait_for_incoming_data),
.start_receiving_data (start_receiving_data),
.ps2_clk_posedge (ps2_clk_posedge),
.ps2_clk_negedge (ps2_clk_negedge),
.ps2_data (ps2_data_reg),
// Bidirectionals
// Outputs
.received_data (received_data),
.received_data_en (received_data_en)
);
Altera_UP_PS2_Command_Out PS2_Command_Out (
// Inputs
.clk (CLOCK_50),
.reset (reset),
.the_command (the_command_w),
.send_command (send_command_w),
.ps2_clk_posedge (ps2_clk_posedge),
.ps2_clk_negedge (ps2_clk_negedge),
// Bidirectionals
.PS2_CLK (PS2_CLK),
.PS2_DAT (PS2_DAT),
// Outputs
.command_was_sent (command_was_sent_w),
.error_communication_timed_out (error_communication_timed_out_w)
);
endmodule
|
module zl_lfsr #
(
parameter LFSR_poly = 0,
parameter LFSR_width = 0,
parameter LFSR_init_value = 0,
parameter PRBS_width = 0
)
(
input clk,
input rst_n,
//
input stall,
input clear,
output [LFSR_width-1:0] lfsr_state,
output [PRBS_width-1:0] prbs
);
reg [LFSR_width-1:0] state_reg;
reg [LFSR_width-1:0] state_next;
reg [PRBS_width-1:0] prbs_internal;
integer i;
function [LFSR_width-1:0] lfsr_state_next_serial;
input [LFSR_width-1:0] cur_state;
begin
lfsr_state_next_serial = {cur_state[LFSR_width-2:0],
^(cur_state & LFSR_poly[LFSR_width:1])};
end
endfunction
always @(*) begin
state_next = state_reg;
for(i=0;i<PRBS_width;i=i+1) begin
state_next = lfsr_state_next_serial(state_next);
prbs_internal[PRBS_width-i-1] = state_next[0];
end
end
always @(posedge clk or negedge rst_n) begin
if(!rst_n) begin
state_reg <= LFSR_init_value;
end
else if (clear && !stall) begin
state_reg <= LFSR_init_value;
end
else if (!stall) begin
state_reg <= state_next;
end
end
assign lfsr_state = state_reg;
assign prbs = prbs_internal;
endmodule
|
module csr_block (
clk,
reset,
csr_writedata,
csr_write,
csr_byteenable,
csr_readdata,
csr_read,
csr_address,
csr_irq,
done_strobe,
busy,
descriptor_buffer_empty,
descriptor_buffer_full,
stop_state,
stopped_on_error,
stopped_on_early_termination,
reset_stalled,
stop,
sw_reset,
stop_on_error,
stop_on_early_termination,
stop_descriptors,
sequence_number,
descriptor_watermark,
response_watermark,
response_buffer_empty,
response_buffer_full,
transfer_complete_IRQ_mask,
error_IRQ_mask,
early_termination_IRQ_mask,
error,
early_termination
);
parameter ADDRESS_WIDTH = 3;
localparam CONTROL_REGISTER_ADDRESS = 3'b001;
input clk;
input reset;
input [31:0] csr_writedata;
input csr_write;
input [3:0] csr_byteenable;
output wire [31:0] csr_readdata;
input csr_read;
input [ADDRESS_WIDTH-1:0] csr_address;
output wire csr_irq;
input done_strobe;
input busy;
input descriptor_buffer_empty;
input descriptor_buffer_full;
input stop_state; // when the DMA runs into some error condition and you have enabled the stop on error (or when the stop control bit is written to)
input reset_stalled; // the read or write master could be in the middle of a transfer/burst so it might take a while to flush the buffers
output wire stop;
output reg stopped_on_error;
output reg stopped_on_early_termination;
output reg sw_reset;
output wire stop_on_error;
output wire stop_on_early_termination;
output wire stop_descriptors;
input [31:0] sequence_number;
input [31:0] descriptor_watermark;
input [15:0] response_watermark;
input response_buffer_empty;
input response_buffer_full;
input transfer_complete_IRQ_mask;
input [7:0] error_IRQ_mask;
input early_termination_IRQ_mask;
input [7:0] error;
input early_termination;
/* Internal wires and registers */
wire [31:0] status;
reg [31:0] control;
reg [31:0] readdata;
reg [31:0] readdata_d1;
reg irq; // writing to the status register clears the irq bit
wire set_irq;
wire clear_irq;
reg [15:0] irq_count; // writing to bit 0 clears the counter
wire clear_irq_count;
wire incr_irq_count;
wire set_stopped_on_error;
wire set_stopped_on_early_termination;
wire set_stop;
wire clear_stop;
wire global_interrupt_enable;
wire sw_reset_strobe; // this strobe will be one cycle earlier than sw_reset
wire set_sw_reset;
wire clear_sw_reset;
/********************************************** Registers ***************************************************/
// read latency is 1 cycle
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
readdata_d1 <= 0;
end
else if (csr_read == 1)
begin
readdata_d1 <= readdata;
end
end
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
control[31:1] <= 0;
end
else
begin
if (sw_reset_strobe == 1) // reset strobe is a strobe due to this sync reset
begin
control[31:1] <= 0;
end
else
begin
if ((csr_address == CONTROL_REGISTER_ADDRESS) & (csr_write == 1) & (csr_byteenable[0] == 1))
begin
control[7:1] <= csr_writedata[7:1]; // stop bit will be handled seperately since it can be set by the csr slave port access or the SGDMA hitting an error condition
end
if ((csr_address == CONTROL_REGISTER_ADDRESS) & (csr_write == 1) & (csr_byteenable[1] == 1))
begin
control[15:8] <= csr_writedata[15:8];
end
if ((csr_address == CONTROL_REGISTER_ADDRESS) & (csr_write == 1) & (csr_byteenable[2] == 1))
begin
control[23:16] <= csr_writedata[23:16];
end
if ((csr_address == CONTROL_REGISTER_ADDRESS) & (csr_write == 1) & (csr_byteenable[3] == 1))
begin
control[31:24] <= csr_writedata[31:24];
end
end
end
end
// control bit 0 (stop) is set by different sources so handling it seperately
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
control[0] <= 0;
end
else
begin
if (sw_reset_strobe == 1)
begin
control[0] <= 0;
end
else
begin
case ({set_stop, clear_stop})
2'b00: control[0] <= control[0];
2'b01: control[0] <= 1'b0;
2'b10: control[0] <= 1'b1;
2'b11: control[0] <= 1'b1; // setting will win, this case happens control[0] is being set to 0 (resume) at the same time an error/early termination stop condition occurs
endcase
end
end
end
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
sw_reset <= 0;
end
else
begin
if (set_sw_reset == 1)
begin
sw_reset <= 1;
end
else if (clear_sw_reset == 1)
begin
sw_reset <= 0;
end
end
end
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
stopped_on_error <= 0;
end
else
begin
case ({set_stopped_on_error, clear_stop})
2'b00: stopped_on_error <= stopped_on_error;
2'b01: stopped_on_error <= 1'b0;
2'b10: stopped_on_error <= 1'b1;
2'b11: stopped_on_error <= 1'b0;
endcase
end
end
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
stopped_on_early_termination <= 0;
end
else
begin
case ({set_stopped_on_early_termination, clear_stop})
2'b00: stopped_on_early_termination <= stopped_on_early_termination;
2'b01: stopped_on_early_termination <= 1'b0;
2'b10: stopped_on_early_termination <= 1'b1;
2'b11: stopped_on_early_termination <= 1'b0;
endcase
end
end
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
irq <= 0;
end
else
begin
if (sw_reset_strobe == 1)
begin
irq <= 0;
end
else
begin
case ({clear_irq, set_irq})
2'b00: irq <= irq;
2'b01: irq <= 1'b1;
2'b10: irq <= 1'b0;
2'b11: irq <= 1'b1; // setting will win over a clear
endcase
end
end
end
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
irq_count <= {16{1'b0}};
end
else
begin
if (sw_reset_strobe == 1)
begin
irq_count <= {16{1'b0}};
end
else
begin
case ({clear_irq_count, incr_irq_count})
2'b00: irq_count <= irq_count;
2'b01: irq_count <= irq_count + 1;
2'b10: irq_count <= {16{1'b0}};
2'b11: irq_count <= {{15{1'b0}}, 1'b1};
endcase
end
end
end
/******************************************** End Registers *************************************************/
/**************************************** Combinational Signals *********************************************/
generate
if (ADDRESS_WIDTH == 3)
begin
always @ (csr_address or status or control or descriptor_watermark or response_watermark or sequence_number)
begin
case (csr_address)
3'b000: readdata = status;
3'b001: readdata = control;
3'b010: readdata = descriptor_watermark;
3'b011: readdata = response_watermark;
default: readdata = sequence_number; // all other addresses will decode to the sequence number
endcase
end
end
else
begin
always @ (csr_address or status or control or descriptor_watermark or response_watermark)
begin
case (csr_address)
3'b000: readdata = status;
3'b001: readdata = control;
3'b010: readdata = descriptor_watermark;
default: readdata = response_watermark; // all other addresses will decode to the response watermark
endcase
end
end
endgenerate
assign clear_irq = (csr_address == 0) & (csr_write == 1) & (csr_byteenable[1] == 1) & (csr_writedata[9] == 1); // this is the IRQ bit
assign set_irq = (global_interrupt_enable == 1) & (done_strobe == 1) & // transfer ended and interrupts are enabled
((transfer_complete_IRQ_mask == 1) | // transfer ended and the transfer complete IRQ is enabled
((error & error_IRQ_mask) != 0) | // transfer ended with an error and this IRQ is enabled
((early_termination & early_termination_IRQ_mask) == 1)); // transfer ended early due to early termination and this IRQ is enabled
assign csr_irq = irq;
// Done count
assign incr_irq_count = set_irq; // Done count just counts the number of interrupts since the last reset
assign clear_irq_count = (csr_address == 0) & (csr_write == 1) & (csr_byteenable[2] == 1) & (csr_writedata[16] == 1); // the LSB irq_count bit
assign clear_stop = (csr_address == CONTROL_REGISTER_ADDRESS) & (csr_write == 1) & (csr_byteenable[0] == 1) & (csr_writedata[0] == 0);
assign set_stopped_on_error = (done_strobe == 1) & (stop_on_error == 1) & (error != 0); // when clear_stop is set then the stopped_on_error register will be cleared
assign set_stopped_on_early_termination = (done_strobe == 1) & (stop_on_early_termination == 1) & (early_termination == 1); // when clear_stop is set then the stopped_on_early_termination register will be cleared
assign set_stop = ((csr_address == CONTROL_REGISTER_ADDRESS) & (csr_write == 1) & (csr_byteenable[0] == 1) & (csr_writedata[0] == 1)) | // host set the stop bit
(set_stopped_on_error == 1) | // SGDMA setup to stop when an error occurs from the write master
(set_stopped_on_early_termination == 1) ; // SGDMA setup to stop when the write master overflows
assign stop = control[0];
assign set_sw_reset = (csr_address == CONTROL_REGISTER_ADDRESS) & (csr_write == 1) & (csr_byteenable[0] == 1) & (csr_writedata[1] == 1);
assign clear_sw_reset = (sw_reset == 1) & (reset_stalled == 0);
assign sw_reset_strobe = control[1];
assign stop_on_error = control[2];
assign stop_on_early_termination = control[3];
assign global_interrupt_enable = control[4];
assign stop_descriptors = control[5];
assign csr_readdata = readdata_d1;
assign status = {irq_count, {6{1'b0}}, irq, stopped_on_early_termination, stopped_on_error, sw_reset, stop_state, response_buffer_full, response_buffer_empty, descriptor_buffer_full, descriptor_buffer_empty, busy}; // writing to the lower byte of the status register clears the irq bit
/**************************************** Combinational Signals *********************************************/
endmodule
|
module sky130_fd_sc_hs__udp_dff$NSR_pp$PG$N (
Q ,
SET ,
RESET ,
CLK_N ,
D ,
NOTIFIER,
VPWR ,
VGND
);
output Q ;
input SET ;
input RESET ;
input CLK_N ;
input D ;
input NOTIFIER;
input VPWR ;
input VGND ;
endmodule
|
module bd_auto_cc_0(s_axi_aclk, s_axi_aresetn, s_axi_awid,
s_axi_awaddr, s_axi_awlen, s_axi_awsize, s_axi_awburst, s_axi_awlock, s_axi_awcache,
s_axi_awprot, s_axi_awregion, s_axi_awqos, s_axi_awvalid, s_axi_awready, s_axi_wdata,
s_axi_wstrb, s_axi_wlast, s_axi_wvalid, s_axi_wready, s_axi_bid, s_axi_bresp, s_axi_bvalid,
s_axi_bready, s_axi_arid, s_axi_araddr, s_axi_arlen, s_axi_arsize, s_axi_arburst,
s_axi_arlock, s_axi_arcache, s_axi_arprot, s_axi_arregion, s_axi_arqos, s_axi_arvalid,
s_axi_arready, s_axi_rid, s_axi_rdata, s_axi_rresp, s_axi_rlast, s_axi_rvalid, s_axi_rready,
m_axi_aclk, m_axi_aresetn, m_axi_awid, m_axi_awaddr, m_axi_awlen, m_axi_awsize,
m_axi_awburst, m_axi_awlock, m_axi_awcache, m_axi_awprot, m_axi_awregion, m_axi_awqos,
m_axi_awvalid, m_axi_awready, m_axi_wdata, m_axi_wstrb, m_axi_wlast, m_axi_wvalid,
m_axi_wready, m_axi_bid, m_axi_bresp, m_axi_bvalid, m_axi_bready, m_axi_arid, m_axi_araddr,
m_axi_arlen, m_axi_arsize, m_axi_arburst, m_axi_arlock, m_axi_arcache, m_axi_arprot,
m_axi_arregion, m_axi_arqos, m_axi_arvalid, m_axi_arready, m_axi_rid, m_axi_rdata,
m_axi_rresp, m_axi_rlast, m_axi_rvalid, m_axi_rready)
/* synthesis syn_black_box black_box_pad_pin="s_axi_aclk,s_axi_aresetn,s_axi_awid[3:0],s_axi_awaddr[31:0],s_axi_awlen[7:0],s_axi_awsize[2:0],s_axi_awburst[1:0],s_axi_awlock[0:0],s_axi_awcache[3:0],s_axi_awprot[2:0],s_axi_awregion[3:0],s_axi_awqos[3:0],s_axi_awvalid,s_axi_awready,s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wlast,s_axi_wvalid,s_axi_wready,s_axi_bid[3:0],s_axi_bresp[1:0],s_axi_bvalid,s_axi_bready,s_axi_arid[3:0],s_axi_araddr[31:0],s_axi_arlen[7:0],s_axi_arsize[2:0],s_axi_arburst[1:0],s_axi_arlock[0:0],s_axi_arcache[3:0],s_axi_arprot[2:0],s_axi_arregion[3:0],s_axi_arqos[3:0],s_axi_arvalid,s_axi_arready,s_axi_rid[3:0],s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rlast,s_axi_rvalid,s_axi_rready,m_axi_aclk,m_axi_aresetn,m_axi_awid[3:0],m_axi_awaddr[31:0],m_axi_awlen[7:0],m_axi_awsize[2:0],m_axi_awburst[1:0],m_axi_awlock[0:0],m_axi_awcache[3:0],m_axi_awprot[2:0],m_axi_awregion[3:0],m_axi_awqos[3:0],m_axi_awvalid,m_axi_awready,m_axi_wdata[31:0],m_axi_wstrb[3:0],m_axi_wlast,m_axi_wvalid,m_axi_wready,m_axi_bid[3:0],m_axi_bresp[1:0],m_axi_bvalid,m_axi_bready,m_axi_arid[3:0],m_axi_araddr[31:0],m_axi_arlen[7:0],m_axi_arsize[2:0],m_axi_arburst[1:0],m_axi_arlock[0:0],m_axi_arcache[3:0],m_axi_arprot[2:0],m_axi_arregion[3:0],m_axi_arqos[3:0],m_axi_arvalid,m_axi_arready,m_axi_rid[3:0],m_axi_rdata[31:0],m_axi_rresp[1:0],m_axi_rlast,m_axi_rvalid,m_axi_rready" */;
input s_axi_aclk;
input s_axi_aresetn;
input [3:0]s_axi_awid;
input [31:0]s_axi_awaddr;
input [7:0]s_axi_awlen;
input [2:0]s_axi_awsize;
input [1:0]s_axi_awburst;
input [0:0]s_axi_awlock;
input [3:0]s_axi_awcache;
input [2:0]s_axi_awprot;
input [3:0]s_axi_awregion;
input [3:0]s_axi_awqos;
input s_axi_awvalid;
output s_axi_awready;
input [31:0]s_axi_wdata;
input [3:0]s_axi_wstrb;
input s_axi_wlast;
input s_axi_wvalid;
output s_axi_wready;
output [3:0]s_axi_bid;
output [1:0]s_axi_bresp;
output s_axi_bvalid;
input s_axi_bready;
input [3:0]s_axi_arid;
input [31:0]s_axi_araddr;
input [7:0]s_axi_arlen;
input [2:0]s_axi_arsize;
input [1:0]s_axi_arburst;
input [0:0]s_axi_arlock;
input [3:0]s_axi_arcache;
input [2:0]s_axi_arprot;
input [3:0]s_axi_arregion;
input [3:0]s_axi_arqos;
input s_axi_arvalid;
output s_axi_arready;
output [3:0]s_axi_rid;
output [31:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output s_axi_rlast;
output s_axi_rvalid;
input s_axi_rready;
input m_axi_aclk;
input m_axi_aresetn;
output [3:0]m_axi_awid;
output [31:0]m_axi_awaddr;
output [7:0]m_axi_awlen;
output [2:0]m_axi_awsize;
output [1:0]m_axi_awburst;
output [0:0]m_axi_awlock;
output [3:0]m_axi_awcache;
output [2:0]m_axi_awprot;
output [3:0]m_axi_awregion;
output [3:0]m_axi_awqos;
output m_axi_awvalid;
input m_axi_awready;
output [31:0]m_axi_wdata;
output [3:0]m_axi_wstrb;
output m_axi_wlast;
output m_axi_wvalid;
input m_axi_wready;
input [3:0]m_axi_bid;
input [1:0]m_axi_bresp;
input m_axi_bvalid;
output m_axi_bready;
output [3:0]m_axi_arid;
output [31:0]m_axi_araddr;
output [7:0]m_axi_arlen;
output [2:0]m_axi_arsize;
output [1:0]m_axi_arburst;
output [0:0]m_axi_arlock;
output [3:0]m_axi_arcache;
output [2:0]m_axi_arprot;
output [3:0]m_axi_arregion;
output [3:0]m_axi_arqos;
output m_axi_arvalid;
input m_axi_arready;
input [3:0]m_axi_rid;
input [31:0]m_axi_rdata;
input [1:0]m_axi_rresp;
input m_axi_rlast;
input m_axi_rvalid;
output m_axi_rready;
endmodule
|
module keyed_permutation #(
parameter UNIT_WIDTH = 1
)(
input wire i_clk,
input wire [`$NUNITS`*UNIT_WIDTH-1:0] i_dat,
input wire [`$NUNITS`*INDEX_WIDTH-1:0] i_key,
input wire i_inverse,
output reg [`$NUNITS`*UNIT_WIDTH-1:0] o_dat
);
localparam NUNITS = `$NUNITS`;
localparam INDEX_WIDTH = `$INDEX_WIDTH`;
localparam KEY_WIDTH = `$KEY_WIDTH`;
function [INDEX_WIDTH-1:0] get_nth_zero_index;
input [NUNITS-1:0] in;
input [INDEX_WIDTH-1:0] index;
integer i;
reg [INDEX_WIDTH-1:0] zero_index;
reg [INDEX_WIDTH-1:0] out;
begin
out = {INDEX_WIDTH{1'bx}};
zero_index = 0;
for(i=0;i<NUNITS;i=i+1) begin
if(~in[i]) begin
if(index==zero_index) begin
out = i;
end
zero_index = zero_index + 1;
end
end
get_nth_zero_index = out;
end
endfunction
function [NUNITS*INDEX_WIDTH-1:0] compute_map;
input [KEY_WIDTH-1:0] key;
reg [NUNITS*INDEX_WIDTH-1:0] map;
reg [NUNITS-1:0] done;
reg [INDEX_WIDTH-1:0] outPos;
reg [NUNITS-1:0] outDone;
reg [8:0] pos;
reg [INDEX_WIDTH-1:0] index;
``if {$COMPACT_KEY} {``
begin
outDone = {NUNITS{1'b0}};
pos = 0;
outPos = 0;
``
set remaining [expr $NUNITS-1]
for {set i 0} {$i<$NUNITS} {incr i} {
set indexWidth [binWidth $remaining]
``
index = {INDEX_WIDTH{1'b0}};
``if {$i!=$NUNITS-1} {``
index = key[pos+:`$indexWidth`] % `expr $remaining + 1`;
pos = pos + `$indexWidth`;
``}``
outPos = get_nth_zero_index(outDone,index);
outDone[outPos]=1'b1;
//map[outPos*INDEX_WIDTH+:INDEX_WIDTH]=`$i`;
map[`$i`*INDEX_WIDTH+:INDEX_WIDTH]=outPos;//better synthesis results on FPGA
``
incr remaining -1
}``
``} else {``
integer i;
reg [INDEX_WIDTH:0] remaining;
begin
outDone = {NUNITS{1'b0}};
pos = 0;
outPos = 0;
remaining = NUNITS;
for(i=0;i<NUNITS;i=i+1) begin
index = {INDEX_WIDTH{1'b0}};
if(i!=NUNITS-1) begin
index = key[pos+:INDEX_WIDTH] % remaining;
remaining = remaining - 1;
pos = pos + INDEX_WIDTH;
end
outPos = get_nth_zero_index(outDone,index);
outDone[outPos]=1'b1;
map[i*INDEX_WIDTH+:INDEX_WIDTH]=outPos;
end
``}``
compute_map = map;
end
endfunction
function [NUNITS*UNIT_WIDTH-1:0] permute;
input [NUNITS*UNIT_WIDTH-1:0] in;
input [NUNITS*INDEX_WIDTH-1:0] map;
reg [NUNITS*UNIT_WIDTH-1:0] out;
integer i;
reg [INDEX_WIDTH-1:0] index;
begin
for(i=0;i<NUNITS;i=i+1) begin
index = map[i*INDEX_WIDTH+:INDEX_WIDTH];
out[i*UNIT_WIDTH+:UNIT_WIDTH] = in[index*UNIT_WIDTH+:UNIT_WIDTH];
end
permute = out;
end
endfunction
function [NUNITS*UNIT_WIDTH-1:0] unpermute;
input [NUNITS*UNIT_WIDTH-1:0] in;
input [NUNITS*INDEX_WIDTH-1:0] map;
reg [NUNITS*UNIT_WIDTH-1:0] out;
integer i;
reg [INDEX_WIDTH-1:0] index;
begin
for(i=0;i<NUNITS;i=i+1) begin
index = map[i*INDEX_WIDTH+:INDEX_WIDTH];
out[index*UNIT_WIDTH+:UNIT_WIDTH] = in[i*UNIT_WIDTH+:UNIT_WIDTH];
end
unpermute = out;
end
endfunction
reg [NUNITS*INDEX_WIDTH-1:0] map;
always @(posedge i_clk) begin
map <= compute_map(i_key);
o_dat <= i_inverse ? unpermute(i_dat,map) : permute(i_dat,map);
end
endmodule
|
module integration_2core2dr(
/* verilator lint_off UNUSED */
/* verilator lint_off UNDRIVEN */
input logic clk
,input logic reset
//******************************************
//* CORE 0 *
//******************************************//
// icache core 0
,input logic core0_coretoic_pc_valid
,output logic core0_coretoic_pc_retry
// ,input I_coretoic_pc_type core0_coretoic_pc
,input CORE_reqid_type core0_coretoic_pc_coreid
,input SC_poffset_type core0_coretoic_pc_poffset
,output logic core0_ictocore_valid
,input logic core0_ictocore_retry
// ,output I_ictocore_type core0_ictocore
,output CORE_reqid_type core0_ictocore_coreid
,output SC_fault_type core0_ictocore_fault
,output IC_fwidth_type core0_ictocore_data
// dcache core 0, slice 0
,input logic core0_slice0_coretodc_ld_valid
,output logic core0_slice0_coretodc_ld_retry
// ,input I_coretodc_ld_type core0_slice0_coretodc_ld
,input DC_ckpid_type core0_slice0_coretodc_ld_ckpid
,input CORE_reqid_type core0_slice0_coretodc_ld_coreid
,input CORE_lop_type core0_slice0_coretodc_ld_lop
,input logic core0_slice0_coretodc_ld_pnr
,input SC_pcsign_type core0_slice0_coretodc_ld_pcsign
,input SC_poffset_type core0_slice0_coretodc_ld_poffset
,input SC_imm_type core0_slice0_coretodc_ld_imm
,output logic core0_slice0_dctocore_ld_valid
,input logic core0_slice0_dctocore_ld_retry
// ,output I_dctocore_ld_type core0_slice0_dctocore_ld
,output CORE_reqid_type core0_slice0_dctocore_ld_coreid
,output SC_fault_type core0_slice0_dctocore_ld_fault
,output SC_line_type core0_slice0_dctocore_ld_data
,input logic core0_slice0_coretodc_std_valid
,output logic core0_slice0_coretodc_std_retry
// ,input I_coretodc_std_type core0_slice0_coretodc_std
,input DC_ckpid_type core0_slice0_coretodc_std_ckpid
,input CORE_reqid_type core0_slice0_coretodc_std_coreid
,input CORE_mop_type core0_slice0_coretodc_std_mop
,input logic core0_slice0_coretodc_std_pnr
,input SC_pcsign_type core0_slice0_coretodc_std_pcsign
,input SC_poffset_type core0_slice0_coretodc_std_poffset
,input SC_imm_type core0_slice0_coretodc_std_imm
,input SC_line_type core0_slice0_coretodc_std_data
,output logic core0_slice0_dctocore_std_ack_valid
,input logic core0_slice0_dctocore_std_ack_retry
// ,output I_dctocore_std_ack_type core0_slice0_dctocore_std_ack
,output SC_fault_type core0_slice0_dctocore_std_ack_fault
,output CORE_reqid_type core0_slice0_dctocore_std_ack_coreid
,input logic c0_s0_coretodctlb_ld_valid
,output logic c0_s0_coretodctlb_ld_retry
// ,input I_coretodctlb_ld_type c0_s0_coretodctlb_ld
,input DC_ckpid_type c0_s0_coretodctlb_ld_ckpid
,input CORE_reqid_type c0_s0_coretodctlb_ld_coreid
,input CORE_lop_type c0_s0_coretodctlb_ld_lop
,input logic c0_s0_coretodctlb_ld_pnr
,input SC_laddr_type c0_s0_coretodctlb_ld_laddr
,input SC_imm_type c0_s0_coretodctlb_ld_imm
,input SC_sptbr_type c0_s0_coretodctlb_ld_sptbr
,input logic c0_s0_coretodctlb_ld_user
,input logic c0_s0_coretodctlb_st_valid
,output logic c0_s0_coretodctlb_st_retry
// ,input I_coretodctlb_st_type c0_s0_coretodctlb_st
,input DC_ckpid_type c0_s0_coretodctlb_st_ckpid
,input CORE_reqid_type c0_s0_coretodctlb_st_coreid
,input CORE_mop_type c0_s0_coretodctlb_st_mop
,input logic c0_s0_coretodctlb_st_pnr
,input SC_laddr_type c0_s0_coretodctlb_st_laddr
,input SC_imm_type c0_s0_coretodctlb_st_imm
,input SC_sptbr_type c0_s0_coretodctlb_st_sptbr
,input logic c0_s0_coretodctlb_st_user
// dcache core 0, slice 1
,input logic core0_slice1_coretodc_ld_valid
,output logic core0_slice1_coretodc_ld_retry
// ,input I_coretodc_ld_type core0_slice1_coretodc_ld
,input DC_ckpid_type core0_slice1_coretodc_ld_ckpid
,input CORE_reqid_type core0_slice1_coretodc_ld_coreid
,input CORE_lop_type core0_slice1_coretodc_ld_lop
,input logic core0_slice1_coretodc_ld_pnr
,input SC_pcsign_type core0_slice1_coretodc_ld_pcsign
,input SC_poffset_type core0_slice1_coretodc_ld_poffset
,input SC_imm_type core0_slice1_coretodc_ld_imm
,output logic core0_slice1_dctocore_ld_valid
,input logic core0_slice1_dctocore_ld_retry
// ,output I_dctocore_ld_type core0_slice1_dctocore_ld
,output CORE_reqid_type core0_slice1_dctocore_ld_coreid
,output SC_fault_type core0_slice1_dctocore_ld_fault
,output SC_line_type core0_slice1_dctocore_ld_data
,input logic core0_slice1_coretodc_std_valid
,output logic core0_slice1_coretodc_std_retry
// ,input I_coretodc_std_type core0_slice1_coretodc_std
,input DC_ckpid_type core0_slice1_coretodc_std_ckpid
,input CORE_reqid_type core0_slice1_coretodc_std_coreid
,input CORE_mop_type core0_slice1_coretodc_std_mop
,input logic core0_slice1_coretodc_std_pnr
,input SC_pcsign_type core0_slice1_coretodc_std_pcsign
,input SC_poffset_type core0_slice1_coretodc_std_poffset
,input SC_imm_type core0_slice1_coretodc_std_imm
,input SC_line_type core0_slice1_coretodc_std_data
,output logic core0_slice1_dctocore_std_ack_valid
,input logic core0_slice1_dctocore_std_ack_retry
// ,output I_dctocore_std_ack_type core0_slice1_dctocore_std_ack
,output SC_fault_type core0_slice1_dctocore_std_ack_fault
,output CORE_reqid_type core0_slice1_dctocore_std_ack_coreid
,input logic c0_s1_coretodctlb_ld_valid
,output logic c0_s1_coretodctlb_ld_retry
// ,input I_coretodctlb_ld_type c0_s1_coretodctlb_ld
,input DC_ckpid_type c0_s1_coretodctlb_ld_ckpid
,input CORE_reqid_type c0_s1_coretodctlb_ld_coreid
,input CORE_lop_type c0_s1_coretodctlb_ld_lop
,input logic c0_s1_coretodctlb_ld_pnr
,input SC_laddr_type c0_s1_coretodctlb_ld_laddr
,input SC_imm_type c0_s1_coretodctlb_ld_imm
,input SC_sptbr_type c0_s1_coretodctlb_ld_sptbr
,input logic c0_s1_coretodctlb_ld_user
,input logic c0_s1_coretodctlb_st_valid
,output logic c0_s1_coretodctlb_st_retry
// ,input I_coretodctlb_st_type c0_s1_coretodctlb_st
,input DC_ckpid_type c0_s1_coretodctlb_st_ckpid
,input CORE_reqid_type c0_s1_coretodctlb_st_coreid
,input CORE_mop_type c0_s1_coretodctlb_st_mop
,input logic c0_s1_coretodctlb_st_pnr
,input SC_laddr_type c0_s1_coretodctlb_st_laddr
,input SC_imm_type c0_s1_coretodctlb_st_imm
,input SC_sptbr_type c0_s1_coretodctlb_st_sptbr
,input logic c0_s1_coretodctlb_st_user
`ifdef SC_4PIPE
// dcache core 0, slice 2
,input logic core0_slice2_coretodc_ld_valid
,output logic core0_slice2_coretodc_ld_retry
// ,input I_coretodc_ld_type core0_slice2_coretodc_ld
,input DC_ckpid_type core0_slice2_coretodc_ld_ckpid
,input CORE_reqid_type core0_slice2_coretodc_ld_coreid
,input CORE_lop_type core0_slice2_coretodc_ld_lop
,input logic core0_slice2_coretodc_ld_pnr
,input SC_pcsign_type core0_slice2_coretodc_ld_pcsign
,input SC_poffset_type core0_slice2_coretodc_ld_poffset
,input SC_imm_type core0_slice2_coretodc_ld_imm
,output logic core0_slice2_dctocore_ld_valid
,input logic core0_slice2_dctocore_ld_retry
// ,output I_dctocore_ld_type core0_slice2_dctocore_ld
,output CORE_reqid_type core0_slice2_dctocore_ld_coreid
,output SC_fault_type core0_slice2_dctocore_ld_fault
,output SC_line_type core0_slice2_dctocore_ld_data
,input logic core0_slice2_coretodc_std_valid
,output logic core0_slice2_coretodc_std_retry
// ,input I_coretodc_std_type core0_slice2_coretodc_std
,input DC_ckpid_type core0_slice2_coretodc_std_ckpid
,input CORE_reqid_type core0_slice2_coretodc_std_coreid
,input CORE_mop_type core0_slice2_coretodc_std_mop
,input logic core0_slice2_coretodc_std_pnr
,input SC_pcsign_type core0_slice2_coretodc_std_pcsign
,input SC_poffset_type core0_slice2_coretodc_std_poffset
,input SC_imm_type core0_slice2_coretodc_std_imm
,input SC_line_type core0_slice2_coretodc_std_data
,output logic core0_slice2_dctocore_std_ack_valid
,input logic core0_slice2_dctocore_std_ack_retry
// ,output I_dctocore_std_ack_type core0_slice2_dctocore_std_ack
,output SC_fault_type core0_slice2_dctocore_std_ack_fault
,output CORE_reqid_type core0_slice2_dctocore_std_ack_coreid
,input logic c0_s2_coretodctlb_ld_valid
,output logic c0_s2_coretodctlb_ld_retry
// ,input I_coretodctlb_ld_type c0_s2_coretodctlb_ld
,input DC_ckpid_type c0_s2_coretodctlb_ld_ckpid
,input CORE_reqid_type c0_s2_coretodctlb_ld_coreid
,input CORE_lop_type c0_s2_coretodctlb_ld_lop
,input logic c0_s2_coretodctlb_ld_pnr
,input SC_laddr_type c0_s2_coretodctlb_ld_laddr
,input SC_imm_type c0_s2_coretodctlb_ld_imm
,input SC_sptbr_type c0_s2_coretodctlb_ld_sptbr
,input logic c0_s2_coretodctlb_ld_user
,input logic c0_s2_coretodctlb_st_valid
,output logic c0_s2_coretodctlb_st_retry
// ,input I_coretodctlb_st_type c0_s2_coretodctlb_st
,input DC_ckpid_type c0_s2_coretodctlb_st_ckpid
,input CORE_reqid_type c0_s2_coretodctlb_st_coreid
,input CORE_mop_type c0_s2_coretodctlb_st_mop
,input logic c0_s2_coretodctlb_st_pnr
,input SC_laddr_type c0_s2_coretodctlb_st_laddr
,input SC_imm_type c0_s2_coretodctlb_st_imm
,input SC_sptbr_type c0_s2_coretodctlb_st_sptbr
,input logic c0_s2_coretodctlb_st_user
// dcache core 0, slice 3
,input logic core0_slice3_coretodc_ld_valid
,output logic core0_slice3_coretodc_ld_retry
// ,input I_coretodc_ld_type core0_slice3_coretodc_ld
,input DC_ckpid_type core0_slice3_coretodc_ld_ckpid
,input CORE_reqid_type core0_slice3_coretodc_ld_coreid
,input CORE_lop_type core0_slice3_coretodc_ld_lop
,input logic core0_slice3_coretodc_ld_pnr
,input SC_pcsign_type core0_slice3_coretodc_ld_pcsign
,input SC_poffset_type core0_slice3_coretodc_ld_poffset
,input SC_imm_type core0_slice3_coretodc_ld_imm
,output logic core0_slice3_dctocore_ld_valid
,input logic core0_slice3_dctocore_ld_retry
// ,output I_dctocore_ld_type core0_slice3_dctocore_ld
,output CORE_reqid_type core0_slice3_dctocore_ld_coreid
,output SC_fault_type core0_slice3_dctocore_ld_fault
,output SC_line_type core0_slice3_dctocore_ld_data
,input logic core0_slice3_coretodc_std_valid
,output logic core0_slice3_coretodc_std_retry
// ,input I_coretodc_std_type core0_slice3_coretodc_std
,input DC_ckpid_type core0_slice3_coretodc_std_ckpid
,input CORE_reqid_type core0_slice3_coretodc_std_coreid
,input CORE_mop_type core0_slice3_coretodc_std_mop
,input logic core0_slice3_coretodc_std_pnr
,input SC_pcsign_type core0_slice3_coretodc_std_pcsign
,input SC_poffset_type core0_slice3_coretodc_std_poffset
,input SC_imm_type core0_slice3_coretodc_std_imm
,input SC_line_type core0_slice3_coretodc_std_data
,output logic core0_slice3_dctocore_std_ack_valid
,input logic core0_slice3_dctocore_std_ack_retry
// ,output I_dctocore_std_ack_type core0_slice3_dctocore_std_ack
,output SC_fault_type core0_slice3_dctocore_std_ack_fault
,output CORE_reqid_type core0_slice3_dctocore_std_ack_coreid
,input logic c0_s3_coretodctlb_ld_valid
,output logic c0_s3_coretodctlb_ld_retry
// ,input I_coretodctlb_ld_type c0_s3_coretodctlb_ld
,input DC_ckpid_type c0_s3_coretodctlb_ld_ckpid
,input CORE_reqid_type c0_s3_coretodctlb_ld_coreid
,input CORE_lop_type c0_s3_coretodctlb_ld_lop
,input logic c0_s3_coretodctlb_ld_pnr
,input SC_laddr_type c0_s3_coretodctlb_ld_laddr
,input SC_imm_type c0_s3_coretodctlb_ld_imm
,input SC_sptbr_type c0_s3_coretodctlb_ld_sptbr
,input logic c0_s3_coretodctlb_ld_user
,input logic c0_s3_coretodctlb_st_valid
,output logic c0_s3_coretodctlb_st_retry
// ,input I_coretodctlb_st_type c0_s3_coretodctlb_st
,input DC_ckpid_type c0_s3_coretodctlb_st_ckpid
,input CORE_reqid_type c0_s3_coretodctlb_st_coreid
,input CORE_mop_type c0_s3_coretodctlb_st_mop
,input logic c0_s3_coretodctlb_st_pnr
,input SC_laddr_type c0_s3_coretodctlb_st_laddr
,input SC_imm_type c0_s3_coretodctlb_st_imm
,input SC_sptbr_type c0_s3_coretodctlb_st_sptbr
,input logic c0_s3_coretodctlb_st_user
`endif
// core 0 prefetch
,input logic core0_pfgtopfe_op_valid
,output logic core0_pfgtopfe_op_retry
// ,input I_pfgtopfe_op_type core0_pfgtopfe_op
,input PF_delta_type core0_pfgtopfe_op_delta
,input PF_weigth_type core0_pfgtopfe_op_w1
,input PF_weigth_type core0_pfgtopfe_op_w2
,input SC_pcsign_type core0_pfgtopfe_op_pcsign
,input SC_laddr_type core0_pfgtopfe_op_laddr
,input SC_sptbr_type core0_pfgtopfe_op_sptbr
//******************************************
//* CORE 1 *
//******************************************//
// icache core 1
,input logic core1_coretoic_pc_valid
,output logic core1_coretoic_pc_retry
// ,input I_coretoic_pc_type core1_coretoic_pc
,input CORE_reqid_type core1_coretoic_pc_coreid
,input SC_poffset_type core1_coretoic_pc_poffset
,output logic core1_ictocore_valid
,input logic core1_ictocore_retry
// ,output I_ictocore_type core1_ictocore
,output CORE_reqid_type core1_ictocore_coreid
,output SC_fault_type core1_ictocore_fault
,output IC_fwidth_type core1_ictocore_data
// dcache core 1, slice 0
,input logic core1_slice0_coretodc_ld_valid
,output logic core1_slice0_coretodc_ld_retry
// ,input I_coretodc_ld_type core1_slice0_coretodc_ld
,input DC_ckpid_type core1_slice0_coretodc_ld_ckpid
,input CORE_reqid_type core1_slice0_coretodc_ld_coreid
,input CORE_lop_type core1_slice0_coretodc_ld_lop
,input logic core1_slice0_coretodc_ld_pnr
,input SC_pcsign_type core1_slice0_coretodc_ld_pcsign
,input SC_poffset_type core1_slice0_coretodc_ld_poffset
,input SC_imm_type core1_slice0_coretodc_ld_imm
,output logic core1_slice0_dctocore_ld_valid
,input logic core1_slice0_dctocore_ld_retry
// ,output I_dctocore_ld_type core1_slice0_dctocore_ld
,output CORE_reqid_type core1_slice0_dctocore_ld_coreid
,output SC_fault_type core1_slice0_dctocore_ld_fault
,output SC_line_type core1_slice0_dctocore_ld_data
,input logic core1_slice0_coretodc_std_valid
,output logic core1_slice0_coretodc_std_retry
// ,input I_coretodc_std_type core1_slice0_coretodc_std
,input DC_ckpid_type core1_slice0_coretodc_std_ckpid
,input CORE_reqid_type core1_slice0_coretodc_std_coreid
,input CORE_mop_type core1_slice0_coretodc_std_mop
,input logic core1_slice0_coretodc_std_pnr
,input SC_pcsign_type core1_slice0_coretodc_std_pcsign
,input SC_poffset_type core1_slice0_coretodc_std_poffset
,input SC_imm_type core1_slice0_coretodc_std_imm
,input SC_line_type core1_slice0_coretodc_std_data
,output logic core1_slice0_dctocore_std_ack_valid
,input logic core1_slice0_dctocore_std_ack_retry
// ,output I_dctocore_std_ack_type core1_slice0_dctocore_std_ack
,output SC_fault_type core1_slice0_dctocore_std_ack_fault
,output CORE_reqid_type core1_slice0_dctocore_std_ack_coreid
,input logic c1_s0_coretodctlb_ld_valid
,output logic c1_s0_coretodctlb_ld_retry
// ,input I_coretodctlb_ld_type c1_s0_coretodctlb_ld
,input DC_ckpid_type c1_s0_coretodctlb_ld_ckpid
,input CORE_reqid_type c1_s0_coretodctlb_ld_coreid
,input CORE_lop_type c1_s0_coretodctlb_ld_lop
,input logic c1_s0_coretodctlb_ld_pnr
,input SC_laddr_type c1_s0_coretodctlb_ld_laddr
,input SC_imm_type c1_s0_coretodctlb_ld_imm
,input SC_sptbr_type c1_s0_coretodctlb_ld_sptbr
,input logic c1_s0_coretodctlb_ld_user
,input logic c1_s0_coretodctlb_st_valid
,output logic c1_s0_coretodctlb_st_retry
// ,input I_coretodctlb_st_type c1_s0_coretodctlb_st
,input DC_ckpid_type c1_s0_coretodctlb_st_ckpid
,input CORE_reqid_type c1_s0_coretodctlb_st_coreid
,input CORE_mop_type c1_s0_coretodctlb_st_mop
,input logic c1_s0_coretodctlb_st_pnr
,input SC_laddr_type c1_s0_coretodctlb_st_laddr
,input SC_imm_type c1_s0_coretodctlb_st_imm
,input SC_sptbr_type c1_s0_coretodctlb_st_sptbr
,input logic c1_s0_coretodctlb_st_user
// dcache core 1, slice 1
,input logic core1_slice1_coretodc_ld_valid
,output logic core1_slice1_coretodc_ld_retry
// ,input I_coretodc_ld_type core1_slice1_coretodc_ld
,input DC_ckpid_type core1_slice1_coretodc_ld_ckpid
,input CORE_reqid_type core1_slice1_coretodc_ld_coreid
,input CORE_lop_type core1_slice1_coretodc_ld_lop
,input logic core1_slice1_coretodc_ld_pnr
,input SC_pcsign_type core1_slice1_coretodc_ld_pcsign
,input SC_poffset_type core1_slice1_coretodc_ld_poffset
,input SC_imm_type core1_slice1_coretodc_ld_imm
,output logic core1_slice1_dctocore_ld_valid
,input logic core1_slice1_dctocore_ld_retry
// ,output I_dctocore_ld_type core1_slice1_dctocore_ld
,output CORE_reqid_type core1_slice1_dctocore_ld_coreid
,output SC_fault_type core1_slice1_dctocore_ld_fault
,output SC_line_type core1_slice1_dctocore_ld_data
,input logic core1_slice1_coretodc_std_valid
,output logic core1_slice1_coretodc_std_retry
// ,input I_coretodc_std_type core1_slice1_coretodc_std
,input DC_ckpid_type core1_slice1_coretodc_std_ckpid
,input CORE_reqid_type core1_slice1_coretodc_std_coreid
,input CORE_mop_type core1_slice1_coretodc_std_mop
,input logic core1_slice1_coretodc_std_pnr
,input SC_pcsign_type core1_slice1_coretodc_std_pcsign
,input SC_poffset_type core1_slice1_coretodc_std_poffset
,input SC_imm_type core1_slice1_coretodc_std_imm
,input SC_line_type core1_slice1_coretodc_std_data
,output logic core1_slice1_dctocore_std_ack_valid
,input logic core1_slice1_dctocore_std_ack_retry
// ,output I_dctocore_std_ack_type core1_slice1_dctocore_std_ack
,output SC_fault_type core1_slice1_dctocore_std_ack_fault
,output CORE_reqid_type core1_slice1_dctocore_std_ack_coreid
,input logic c1_s1_coretodctlb_ld_valid
,output logic c1_s1_coretodctlb_ld_retry
// ,input I_coretodctlb_ld_type c1_s1_coretodctlb_ld
,input DC_ckpid_type c1_s1_coretodctlb_ld_ckpid
,input CORE_reqid_type c1_s1_coretodctlb_ld_coreid
,input CORE_lop_type c1_s1_coretodctlb_ld_lop
,input logic c1_s1_coretodctlb_ld_pnr
,input SC_laddr_type c1_s1_coretodctlb_ld_laddr
,input SC_imm_type c1_s1_coretodctlb_ld_imm
,input SC_sptbr_type c1_s1_coretodctlb_ld_sptbr
,input logic c1_s1_coretodctlb_ld_user
,input logic c1_s1_coretodctlb_st_valid
,output logic c1_s1_coretodctlb_st_retry
// ,input I_coretodctlb_st_type c1_s1_coretodctlb_st
,input DC_ckpid_type c1_s1_coretodctlb_st_ckpid
,input CORE_reqid_type c1_s1_coretodctlb_st_coreid
,input CORE_mop_type c1_s1_coretodctlb_st_mop
,input logic c1_s1_coretodctlb_st_pnr
,input SC_laddr_type c1_s1_coretodctlb_st_laddr
,input SC_imm_type c1_s1_coretodctlb_st_imm
,input SC_sptbr_type c1_s1_coretodctlb_st_sptbr
,input logic c1_s1_coretodctlb_st_user
`ifdef SC_4PIPE
// dcache core 1, slice 2
,input logic core1_slice2_coretodc_ld_valid
,output logic core1_slice2_coretodc_ld_retry
// ,input I_coretodc_ld_type core1_slice2_coretodc_ld
,input DC_ckpid_type core1_slice2_coretodc_ld_ckpid
,input CORE_reqid_type core1_slice2_coretodc_ld_coreid
,input CORE_lop_type core1_slice2_coretodc_ld_lop
,input logic core1_slice2_coretodc_ld_pnr
,input SC_pcsign_type core1_slice2_coretodc_ld_pcsign
,input SC_poffset_type core1_slice2_coretodc_ld_poffset
,input SC_imm_type core1_slice2_coretodc_ld_imm
,output logic core1_slice2_dctocore_ld_valid
,input logic core1_slice2_dctocore_ld_retry
// ,output I_dctocore_ld_type core1_slice2_dctocore_ld
,output CORE_reqid_type core1_slice2_dctocore_ld_coreid
,output SC_fault_type core1_slice2_dctocore_ld_fault
,output SC_line_type core1_slice2_dctocore_ld_data
,input logic core1_slice2_coretodc_std_valid
,output logic core1_slice2_coretodc_std_retry
// ,input I_coretodc_std_type core1_slice2_coretodc_std
,input DC_ckpid_type core1_slice2_coretodc_std_ckpid
,input CORE_reqid_type core1_slice2_coretodc_std_coreid
,input CORE_mop_type core1_slice2_coretodc_std_mop
,input logic core1_slice2_coretodc_std_pnr
,input SC_pcsign_type core1_slice2_coretodc_std_pcsign
,input SC_poffset_type core1_slice2_coretodc_std_poffset
,input SC_imm_type core1_slice2_coretodc_std_imm
,input SC_line_type core1_slice2_coretodc_std_data
,output logic core1_slice2_dctocore_std_ack_valid
,input logic core1_slice2_dctocore_std_ack_retry
// ,output I_dctocore_std_ack_type core1_slice2_dctocore_std_ack
,output SC_fault_type core1_slice2_dctocore_std_ack_fault
,output CORE_reqid_type core1_slice2_dctocore_std_ack_coreid
,input logic c1_s2_coretodctlb_ld_valid
,output logic c1_s2_coretodctlb_ld_retry
// ,input I_coretodctlb_ld_type c1_s2_coretodctlb_ld
,input DC_ckpid_type c1_s2_coretodctlb_ld_ckpid
,input CORE_reqid_type c1_s2_coretodctlb_ld_coreid
,input CORE_lop_type c1_s2_coretodctlb_ld_lop
,input logic c1_s2_coretodctlb_ld_pnr
,input SC_laddr_type c1_s2_coretodctlb_ld_laddr
,input SC_imm_type c1_s2_coretodctlb_ld_imm
,input SC_sptbr_type c1_s2_coretodctlb_ld_sptbr
,input logic c1_s2_coretodctlb_ld_user
,input logic c1_s2_coretodctlb_st_valid
,output logic c1_s2_coretodctlb_st_retry
// ,input I_coretodctlb_st_type c1_s2_coretodctlb_st
,input DC_ckpid_type c1_s2_coretodctlb_st_ckpid
,input CORE_reqid_type c1_s2_coretodctlb_st_coreid
,input CORE_mop_type c1_s2_coretodctlb_st_mop
,input logic c1_s2_coretodctlb_st_pnr
,input SC_laddr_type c1_s2_coretodctlb_st_laddr
,input SC_imm_type c1_s2_coretodctlb_st_imm
,input SC_sptbr_type c1_s2_coretodctlb_st_sptbr
,input logic c1_s2_coretodctlb_st_user
// dcache core 1, slice 3
,input logic core1_slice3_coretodc_ld_valid
,output logic core1_slice3_coretodc_ld_retry
// ,input I_coretodc_ld_type core1_slice3_coretodc_ld
,input DC_ckpid_type core1_slice3_coretodc_ld_ckpid
,input CORE_reqid_type core1_slice3_coretodc_ld_coreid
,input CORE_lop_type core1_slice3_coretodc_ld_lop
,input logic core1_slice3_coretodc_ld_pnr
,input SC_pcsign_type core1_slice3_coretodc_ld_pcsign
,input SC_poffset_type core1_slice3_coretodc_ld_poffset
,input SC_imm_type core1_slice3_coretodc_ld_imm
,output logic core1_slice3_dctocore_ld_valid
,input logic core1_slice3_dctocore_ld_retry
// ,output I_dctocore_ld_type core1_slice3_dctocore_ld
,output CORE_reqid_type core1_slice3_dctocore_ld_coreid
,output SC_fault_type core1_slice3_dctocore_ld_fault
,output SC_line_type core1_slice3_dctocore_ld_data
,input logic core1_slice3_coretodc_std_valid
,output logic core1_slice3_coretodc_std_retry
// ,input I_coretodc_std_type core1_slice3_coretodc_std
,input DC_ckpid_type core1_slice3_coretodc_std_ckpid
,input CORE_reqid_type core1_slice3_coretodc_std_coreid
,input CORE_mop_type core1_slice3_coretodc_std_mop
,input logic core1_slice3_coretodc_std_pnr
,input SC_pcsign_type core1_slice3_coretodc_std_pcsign
,input SC_poffset_type core1_slice3_coretodc_std_poffset
,input SC_imm_type core1_slice3_coretodc_std_imm
,input SC_line_type core1_slice3_coretodc_std_data
,output logic core1_slice3_dctocore_std_ack_valid
,input logic core1_slice3_dctocore_std_ack_retry
// ,output I_dctocore_std_ack_type core1_slice3_dctocore_std_ack
,output SC_fault_type core1_slice3_dctocore_std_ack_fault
,output CORE_reqid_type core1_slice3_dctocore_std_ack_coreid
,input logic c1_s3_coretodctlb_ld_valid
,output logic c1_s3_coretodctlb_ld_retry
// ,input I_coretodctlb_ld_type c1_s3_coretodctlb_ld
,input DC_ckpid_type c1_s3_coretodctlb_ld_ckpid
,input CORE_reqid_type c1_s3_coretodctlb_ld_coreid
,input CORE_lop_type c1_s3_coretodctlb_ld_lop
,input logic c1_s3_coretodctlb_ld_pnr
,input SC_laddr_type c1_s3_coretodctlb_ld_laddr
,input SC_imm_type c1_s3_coretodctlb_ld_imm
,input SC_sptbr_type c1_s3_coretodctlb_ld_sptbr
,input logic c1_s3_coretodctlb_ld_user
,input logic c1_s3_coretodctlb_st_valid
,output logic c1_s3_coretodctlb_st_retry
// ,input I_coretodctlb_st_type c1_s3_coretodctlb_st
,input DC_ckpid_type c1_s3_coretodctlb_st_ckpid
,input CORE_reqid_type c1_s3_coretodctlb_st_coreid
,input CORE_mop_type c1_s3_coretodctlb_st_mop
,input logic c1_s3_coretodctlb_st_pnr
,input SC_laddr_type c1_s3_coretodctlb_st_laddr
,input SC_imm_type c1_s3_coretodctlb_st_imm
,input SC_sptbr_type c1_s3_coretodctlb_st_sptbr
,input logic c1_s3_coretodctlb_st_user
`endif
// core 1 prefetch
,input logic core1_pfgtopfe_op_valid
,output logic core1_pfgtopfe_op_retry
// ,input I_pfgtopfe_op_type core1_pfgtopfe_op
,input PF_delta_type core1_pfgtopfe_op_delta
,input PF_weigth_type core1_pfgtopfe_op_w1
,input PF_weigth_type core1_pfgtopfe_op_w2
,input SC_pcsign_type core1_pfgtopfe_op_pcsign
,input SC_laddr_type core1_pfgtopfe_op_laddr
,input SC_sptbr_type core1_pfgtopfe_op_sptbr
//******************************************
//* Directory 0 *
//******************************************//
,output logic dr0_drtomem_req_valid
,input logic dr0_drtomem_req_retry
// ,output I_drtomem_req_type dr0_drtomem_req
,output DR_reqid_type dr0_drtomem_req_drid
,output SC_cmd_type dr0_drtomem_req_cmd
,output SC_paddr_type dr0_drtomem_req_paddr
,input logic dr0_memtodr_ack_valid
,output logic dr0_memtodr_ack_retry
// ,input I_memtodr_ack_type dr0_memtodr_ack
,input DR_reqid_type dr0_memtodr_ack_drid
,input SC_nodeid_type dr0_memtodr_ack_nid
,input SC_paddr_type dr0_memtodr_ack_paddr
,input SC_snack_type dr0_memtodr_ack_ack
,input SC_line_type dr0_memtodr_ack_line
,output logic dr0_drtomem_wb_valid
,input logic dr0_drtomem_wb_retry
// ,output I_drtomem_wb_type dr0_drtomem_wb
,output SC_line_type dr0_drtomem_wb_line
,output SC_paddr_type dr0_drtomem_wb_paddr
,output logic dr0_drtomem_pfreq_valid
,input logic dr0_drtomem_pfreq_retry
// ,output I_drtomem_pfreq_type dr0_drtomem_pfreq
,output SC_nodeid_type dr0_drtomem_pfreq_nid
,output SC_paddr_type dr0_drtomem_pfreq_paddr
//******************************************
//* Directory 1 *
//******************************************//
,output logic dr1_drtomem_req_valid
,input logic dr1_drtomem_req_retry
// ,output I_drtomem_req_type dr1_drtomem_req
,output DR_reqid_type dr1_drtomem_req_drid
,output SC_cmd_type dr1_drtomem_req_cmd
,output SC_paddr_type dr1_drtomem_req_paddr
,input logic dr1_memtodr_ack_valid
,output logic dr1_memtodr_ack_retry
// ,input I_memtodr_ack_type dr1_memtodr_ack
,input DR_reqid_type dr1_memtodr_ack_drid
,input SC_nodeid_type dr1_memtodr_ack_nid
,input SC_paddr_type dr1_memtodr_ack_paddr
,input SC_snack_type dr1_memtodr_ack_ack
,input SC_line_type dr1_memtodr_ack_line
,output logic dr1_drtomem_wb_valid
,input logic dr1_drtomem_wb_retry
// ,output I_drtomem_wb_type dr1_drtomem_wb
,output SC_line_type dr1_drtomem_wb_line
,output SC_paddr_type dr1_drtomem_wb_paddr
,output logic dr1_drtomem_pfreq_valid
,input logic dr1_drtomem_pfreq_retry
// ,output I_drtomem_pfreq_type dr1_drtomem_pfreq
,output SC_nodeid_type dr1_drtomem_pfreq_nid
,output SC_paddr_type dr1_drtomem_pfreq_paddr
);
I_coretoic_pc_type core0_coretoic_pc;
assign core0_coretoic_pc.coreid = core0_coretoic_pc_coreid;
assign core0_coretoic_pc.poffset = core0_coretoic_pc_poffset;
I_ictocore_type core0_ictocore;
assign core0_ictocore_coreid = core0_ictocore.coreid;
assign core0_ictocore_fault = core0_ictocore.fault;
assign core0_ictocore_data = core0_ictocore.data;
I_coretodc_ld_type core0_slice0_coretodc_ld;
assign core0_slice0_coretodc_ld.ckpid = core0_slice0_coretodc_ld_ckpid;
assign core0_slice0_coretodc_ld.coreid = core0_slice0_coretodc_ld_coreid;
assign core0_slice0_coretodc_ld.lop = core0_slice0_coretodc_ld_lop;
assign core0_slice0_coretodc_ld.pnr = core0_slice0_coretodc_ld_pnr;
assign core0_slice0_coretodc_ld.pcsign = core0_slice0_coretodc_ld_pcsign;
assign core0_slice0_coretodc_ld.poffset = core0_slice0_coretodc_ld_poffset;
assign core0_slice0_coretodc_ld.imm = core0_slice0_coretodc_ld_imm;
I_dctocore_ld_type core0_slice0_dctocore_ld;
assign core0_slice0_dctocore_ld_coreid = core0_slice0_dctocore_ld.coreid;
assign core0_slice0_dctocore_ld_fault = core0_slice0_dctocore_ld.fault;
assign core0_slice0_dctocore_ld_data = core0_slice0_dctocore_ld.data;
I_coretodc_std_type core0_slice0_coretodc_std;
assign core0_slice0_coretodc_std.ckpid = core0_slice0_coretodc_std_ckpid;
assign core0_slice0_coretodc_std.coreid = core0_slice0_coretodc_std_coreid;
assign core0_slice0_coretodc_std.mop = core0_slice0_coretodc_std_mop;
assign core0_slice0_coretodc_std.pnr = core0_slice0_coretodc_std_pnr;
assign core0_slice0_coretodc_std.pcsign = core0_slice0_coretodc_std_pcsign;
assign core0_slice0_coretodc_std.poffset = core0_slice0_coretodc_std_poffset;
assign core0_slice0_coretodc_std.imm = core0_slice0_coretodc_std_imm;
assign core0_slice0_coretodc_std.data = core0_slice0_coretodc_std_data;
I_dctocore_std_ack_type core0_slice0_dctocore_std_ack;
assign core0_slice0_dctocore_std_ack_fault = core0_slice0_dctocore_std_ack.fault;
assign core0_slice0_dctocore_std_ack_coreid = core0_slice0_dctocore_std_ack.coreid;
I_coretodctlb_ld_type c0_s0_coretodctlb_ld;
assign c0_s0_coretodctlb_ld.ckpid = c0_s0_coretodctlb_ld_ckpid;
assign c0_s0_coretodctlb_ld.coreid = c0_s0_coretodctlb_ld_coreid;
assign c0_s0_coretodctlb_ld.lop = c0_s0_coretodctlb_ld_lop;
assign c0_s0_coretodctlb_ld.pnr = c0_s0_coretodctlb_ld_pnr;
assign c0_s0_coretodctlb_ld.laddr = c0_s0_coretodctlb_ld_laddr;
assign c0_s0_coretodctlb_ld.imm = c0_s0_coretodctlb_ld_imm;
assign c0_s0_coretodctlb_ld.sptbr = c0_s0_coretodctlb_ld_sptbr;
assign c0_s0_coretodctlb_ld.user = c0_s0_coretodctlb_ld_user;
I_coretodctlb_st_type c0_s0_coretodctlb_st;
assign c0_s0_coretodctlb_st.ckpid = c0_s0_coretodctlb_st_ckpid;
assign c0_s0_coretodctlb_st.coreid = c0_s0_coretodctlb_st_coreid;
assign c0_s0_coretodctlb_st.mop = c0_s0_coretodctlb_st_mop;
assign c0_s0_coretodctlb_st.pnr = c0_s0_coretodctlb_st_pnr;
assign c0_s0_coretodctlb_st.laddr = c0_s0_coretodctlb_st_laddr;
assign c0_s0_coretodctlb_st.imm = c0_s0_coretodctlb_st_imm;
assign c0_s0_coretodctlb_st.sptbr = c0_s0_coretodctlb_st_sptbr;
assign c0_s0_coretodctlb_st.user = c0_s0_coretodctlb_st_user;
I_coretodc_ld_type core0_slice1_coretodc_ld;
assign core0_slice1_coretodc_ld.ckpid = core0_slice1_coretodc_ld_ckpid;
assign core0_slice1_coretodc_ld.coreid = core0_slice1_coretodc_ld_coreid;
assign core0_slice1_coretodc_ld.lop = core0_slice1_coretodc_ld_lop;
assign core0_slice1_coretodc_ld.pnr = core0_slice1_coretodc_ld_pnr;
assign core0_slice1_coretodc_ld.pcsign = core0_slice1_coretodc_ld_pcsign;
assign core0_slice1_coretodc_ld.poffset = core0_slice1_coretodc_ld_poffset;
assign core0_slice1_coretodc_ld.imm = core0_slice1_coretodc_ld_imm;
I_dctocore_ld_type core0_slice1_dctocore_ld;
assign core0_slice1_dctocore_ld_coreid = core0_slice1_dctocore_ld.coreid;
assign core0_slice1_dctocore_ld_fault = core0_slice1_dctocore_ld.fault;
assign core0_slice1_dctocore_ld_data = core0_slice1_dctocore_ld.data;
I_coretodc_std_type core0_slice1_coretodc_std;
assign core0_slice1_coretodc_std.ckpid = core0_slice1_coretodc_std_ckpid;
assign core0_slice1_coretodc_std.coreid = core0_slice1_coretodc_std_coreid;
assign core0_slice1_coretodc_std.mop = core0_slice1_coretodc_std_mop;
assign core0_slice1_coretodc_std.pnr = core0_slice1_coretodc_std_pnr;
assign core0_slice1_coretodc_std.pcsign = core0_slice1_coretodc_std_pcsign;
assign core0_slice1_coretodc_std.poffset = core0_slice1_coretodc_std_poffset;
assign core0_slice1_coretodc_std.imm = core0_slice1_coretodc_std_imm;
assign core0_slice1_coretodc_std.data = core0_slice1_coretodc_std_data;
I_dctocore_std_ack_type core0_slice1_dctocore_std_ack;
assign core0_slice1_dctocore_std_ack_fault = core0_slice1_dctocore_std_ack.fault;
assign core0_slice1_dctocore_std_ack_coreid = core0_slice1_dctocore_std_ack.coreid;
I_coretodctlb_ld_type c0_s1_coretodctlb_ld;
assign c0_s1_coretodctlb_ld.ckpid = c0_s1_coretodctlb_ld_ckpid;
assign c0_s1_coretodctlb_ld.coreid = c0_s1_coretodctlb_ld_coreid;
assign c0_s1_coretodctlb_ld.lop = c0_s1_coretodctlb_ld_lop;
assign c0_s1_coretodctlb_ld.pnr = c0_s1_coretodctlb_ld_pnr;
assign c0_s1_coretodctlb_ld.laddr = c0_s1_coretodctlb_ld_laddr;
assign c0_s1_coretodctlb_ld.imm = c0_s1_coretodctlb_ld_imm;
assign c0_s1_coretodctlb_ld.sptbr = c0_s1_coretodctlb_ld_sptbr;
assign c0_s1_coretodctlb_ld.user = c0_s1_coretodctlb_ld_user;
I_coretodctlb_st_type c0_s1_coretodctlb_st;
assign c0_s1_coretodctlb_st.ckpid = c0_s1_coretodctlb_st_ckpid;
assign c0_s1_coretodctlb_st.coreid = c0_s1_coretodctlb_st_coreid;
assign c0_s1_coretodctlb_st.mop = c0_s1_coretodctlb_st_mop;
assign c0_s1_coretodctlb_st.pnr = c0_s1_coretodctlb_st_pnr;
assign c0_s1_coretodctlb_st.laddr = c0_s1_coretodctlb_st_laddr;
assign c0_s1_coretodctlb_st.imm = c0_s1_coretodctlb_st_imm;
assign c0_s1_coretodctlb_st.sptbr = c0_s1_coretodctlb_st_sptbr;
assign c0_s1_coretodctlb_st.user = c0_s1_coretodctlb_st_user;
`ifdef SC_4PIPE
I_coretodc_ld_type core0_slice2_coretodc_ld;
assign core0_slice2_coretodc_ld.ckpid = core0_slice2_coretodc_ld_ckpid;
assign core0_slice2_coretodc_ld.coreid = core0_slice2_coretodc_ld_coreid;
assign core0_slice2_coretodc_ld.lop = core0_slice2_coretodc_ld_lop;
assign core0_slice2_coretodc_ld.pnr = core0_slice2_coretodc_ld_pnr;
assign core0_slice2_coretodc_ld.pcsign = core0_slice2_coretodc_ld_pcsign;
assign core0_slice2_coretodc_ld.poffset = core0_slice2_coretodc_ld_poffset;
assign core0_slice2_coretodc_ld.imm = core0_slice2_coretodc_ld_imm;
I_dctocore_ld_type core0_slice2_dctocore_ld;
assign core0_slice2_dctocore_ld_coreid = core0_slice2_dctocore_ld.coreid;
assign core0_slice2_dctocore_ld_fault = core0_slice2_dctocore_ld.fault;
assign core0_slice2_dctocore_ld_data = core0_slice2_dctocore_ld.data;
I_coretodc_std_type core0_slice2_coretodc_std;
assign core0_slice2_coretodc_std.ckpid = core0_slice2_coretodc_std_ckpid;
assign core0_slice2_coretodc_std.coreid = core0_slice2_coretodc_std_coreid;
assign core0_slice2_coretodc_std.mop = core0_slice2_coretodc_std_mop;
assign core0_slice2_coretodc_std.pnr = core0_slice2_coretodc_std_pnr;
assign core0_slice2_coretodc_std.pcsign = core0_slice2_coretodc_std_pcsign;
assign core0_slice2_coretodc_std.poffset = core0_slice2_coretodc_std_poffset;
assign core0_slice2_coretodc_std.imm = core0_slice2_coretodc_std_imm;
assign core0_slice2_coretodc_std.data = core0_slice2_coretodc_std_data;
I_dctocore_std_ack_type core0_slice2_dctocore_std_ack;
assign core0_slice2_dctocore_std_ack_fault = core0_slice2_dctocore_std_ack.fault;
assign core0_slice2_dctocore_std_ack_coreid = core0_slice2_dctocore_std_ack.coreid;
I_coretodctlb_ld_type c0_s2_coretodctlb_ld;
assign c0_s2_coretodctlb_ld.ckpid = c0_s2_coretodctlb_ld_ckpid;
assign c0_s2_coretodctlb_ld.coreid = c0_s2_coretodctlb_ld_coreid;
assign c0_s2_coretodctlb_ld.lop = c0_s2_coretodctlb_ld_lop;
assign c0_s2_coretodctlb_ld.pnr = c0_s2_coretodctlb_ld_pnr;
assign c0_s2_coretodctlb_ld.laddr = c0_s2_coretodctlb_ld_laddr;
assign c0_s2_coretodctlb_ld.imm = c0_s2_coretodctlb_ld_imm;
assign c0_s2_coretodctlb_ld.sptbr = c0_s2_coretodctlb_ld_sptbr;
assign c0_s2_coretodctlb_ld.user = c0_s2_coretodctlb_ld_user;
I_coretodctlb_st_type c0_s2_coretodctlb_st;
assign c0_s2_coretodctlb_st.ckpid = c0_s2_coretodctlb_st_ckpid;
assign c0_s2_coretodctlb_st.coreid = c0_s2_coretodctlb_st_coreid;
assign c0_s2_coretodctlb_st.mop = c0_s2_coretodctlb_st_mop;
assign c0_s2_coretodctlb_st.pnr = c0_s2_coretodctlb_st_pnr;
assign c0_s2_coretodctlb_st.laddr = c0_s2_coretodctlb_st_laddr;
assign c0_s2_coretodctlb_st.imm = c0_s2_coretodctlb_st_imm;
assign c0_s2_coretodctlb_st.sptbr = c0_s2_coretodctlb_st_sptbr;
assign c0_s2_coretodctlb_st.user = c0_s2_coretodctlb_st_user;
I_coretodc_ld_type core0_slice3_coretodc_ld;
assign core0_slice3_coretodc_ld.ckpid = core0_slice3_coretodc_ld_ckpid;
assign core0_slice3_coretodc_ld.coreid = core0_slice3_coretodc_ld_coreid;
assign core0_slice3_coretodc_ld.lop = core0_slice3_coretodc_ld_lop;
assign core0_slice3_coretodc_ld.pnr = core0_slice3_coretodc_ld_pnr;
assign core0_slice3_coretodc_ld.pcsign = core0_slice3_coretodc_ld_pcsign;
assign core0_slice3_coretodc_ld.poffset = core0_slice3_coretodc_ld_poffset;
assign core0_slice3_coretodc_ld.imm = core0_slice3_coretodc_ld_imm;
I_dctocore_ld_type core0_slice3_dctocore_ld;
assign core0_slice3_dctocore_ld_coreid = core0_slice3_dctocore_ld.coreid;
assign core0_slice3_dctocore_ld_fault = core0_slice3_dctocore_ld.fault;
assign core0_slice3_dctocore_ld_data = core0_slice3_dctocore_ld.data;
I_coretodc_std_type core0_slice3_coretodc_std;
assign core0_slice3_coretodc_std.ckpid = core0_slice3_coretodc_std_ckpid;
assign core0_slice3_coretodc_std.coreid = core0_slice3_coretodc_std_coreid;
assign core0_slice3_coretodc_std.mop = core0_slice3_coretodc_std_mop;
assign core0_slice3_coretodc_std.pnr = core0_slice3_coretodc_std_pnr;
assign core0_slice3_coretodc_std.pcsign = core0_slice3_coretodc_std_pcsign;
assign core0_slice3_coretodc_std.poffset = core0_slice3_coretodc_std_poffset;
assign core0_slice3_coretodc_std.imm = core0_slice3_coretodc_std_imm;
assign core0_slice3_coretodc_std.data = core0_slice3_coretodc_std_data;
I_dctocore_std_ack_type core0_slice3_dctocore_std_ack;
assign core0_slice3_dctocore_std_ack_fault = core0_slice3_dctocore_std_ack.fault;
assign core0_slice3_dctocore_std_ack_coreid = core0_slice3_dctocore_std_ack.coreid;
I_coretodctlb_ld_type c0_s3_coretodctlb_ld;
assign c0_s3_coretodctlb_ld.ckpid = c0_s3_coretodctlb_ld_ckpid;
assign c0_s3_coretodctlb_ld.coreid = c0_s3_coretodctlb_ld_coreid;
assign c0_s3_coretodctlb_ld.lop = c0_s3_coretodctlb_ld_lop;
assign c0_s3_coretodctlb_ld.pnr = c0_s3_coretodctlb_ld_pnr;
assign c0_s3_coretodctlb_ld.laddr = c0_s3_coretodctlb_ld_laddr;
assign c0_s3_coretodctlb_ld.imm = c0_s3_coretodctlb_ld_imm;
assign c0_s3_coretodctlb_ld.sptbr = c0_s3_coretodctlb_ld_sptbr;
assign c0_s3_coretodctlb_ld.user = c0_s3_coretodctlb_ld_user;
I_coretodctlb_st_type c0_s3_coretodctlb_st;
assign c0_s3_coretodctlb_st.ckpid = c0_s3_coretodctlb_st_ckpid;
assign c0_s3_coretodctlb_st.coreid = c0_s3_coretodctlb_st_coreid;
assign c0_s3_coretodctlb_st.mop = c0_s3_coretodctlb_st_mop;
assign c0_s3_coretodctlb_st.pnr = c0_s3_coretodctlb_st_pnr;
assign c0_s3_coretodctlb_st.laddr = c0_s3_coretodctlb_st_laddr;
assign c0_s3_coretodctlb_st.imm = c0_s3_coretodctlb_st_imm;
assign c0_s3_coretodctlb_st.sptbr = c0_s3_coretodctlb_st_sptbr;
assign c0_s3_coretodctlb_st.user = c0_s3_coretodctlb_st_user;
`endif
I_pfgtopfe_op_type core0_pfgtopfe_op;
assign core0_pfgtopfe_op.delta = core0_pfgtopfe_op_delta;
assign core0_pfgtopfe_op.w1 = core0_pfgtopfe_op_w1;
assign core0_pfgtopfe_op.w2 = core0_pfgtopfe_op_w2;
assign core0_pfgtopfe_op.pcsign = core0_pfgtopfe_op_pcsign;
assign core0_pfgtopfe_op.laddr = core0_pfgtopfe_op_laddr;
assign core0_pfgtopfe_op.sptbr = core0_pfgtopfe_op_sptbr;
I_coretoic_pc_type core1_coretoic_pc;
assign core1_coretoic_pc.coreid = core1_coretoic_pc_coreid;
assign core1_coretoic_pc.poffset = core1_coretoic_pc_poffset;
I_ictocore_type core1_ictocore;
assign core1_ictocore_coreid = core1_ictocore.coreid;
assign core1_ictocore_fault = core1_ictocore.fault;
assign core1_ictocore_data = core1_ictocore.data;
I_coretodc_ld_type core1_slice0_coretodc_ld;
assign core1_slice0_coretodc_ld.ckpid = core1_slice0_coretodc_ld_ckpid;
assign core1_slice0_coretodc_ld.coreid = core1_slice0_coretodc_ld_coreid;
assign core1_slice0_coretodc_ld.lop = core1_slice0_coretodc_ld_lop;
assign core1_slice0_coretodc_ld.pnr = core1_slice0_coretodc_ld_pnr;
assign core1_slice0_coretodc_ld.pcsign = core1_slice0_coretodc_ld_pcsign;
assign core1_slice0_coretodc_ld.poffset = core1_slice0_coretodc_ld_poffset;
assign core1_slice0_coretodc_ld.imm = core1_slice0_coretodc_ld_imm;
I_dctocore_ld_type core1_slice0_dctocore_ld;
assign core1_slice0_dctocore_ld_coreid = core1_slice0_dctocore_ld.coreid;
assign core1_slice0_dctocore_ld_fault = core1_slice0_dctocore_ld.fault;
assign core1_slice0_dctocore_ld_data = core1_slice0_dctocore_ld.data;
I_coretodc_std_type core1_slice0_coretodc_std;
assign core1_slice0_coretodc_std.ckpid = core1_slice0_coretodc_std_ckpid;
assign core1_slice0_coretodc_std.coreid = core1_slice0_coretodc_std_coreid;
assign core1_slice0_coretodc_std.mop = core1_slice0_coretodc_std_mop;
assign core1_slice0_coretodc_std.pnr = core1_slice0_coretodc_std_pnr;
assign core1_slice0_coretodc_std.pcsign = core1_slice0_coretodc_std_pcsign;
assign core1_slice0_coretodc_std.poffset = core1_slice0_coretodc_std_poffset;
assign core1_slice0_coretodc_std.imm = core1_slice0_coretodc_std_imm;
assign core1_slice0_coretodc_std.data = core1_slice0_coretodc_std_data;
I_dctocore_std_ack_type core1_slice0_dctocore_std_ack;
assign core1_slice0_dctocore_std_ack_fault = core1_slice0_dctocore_std_ack.fault;
assign core1_slice0_dctocore_std_ack_coreid = core1_slice0_dctocore_std_ack.coreid;
I_coretodctlb_ld_type c1_s0_coretodctlb_ld;
assign c1_s0_coretodctlb_ld.ckpid = c1_s0_coretodctlb_ld_ckpid;
assign c1_s0_coretodctlb_ld.coreid = c1_s0_coretodctlb_ld_coreid;
assign c1_s0_coretodctlb_ld.lop = c1_s0_coretodctlb_ld_lop;
assign c1_s0_coretodctlb_ld.pnr = c1_s0_coretodctlb_ld_pnr;
assign c1_s0_coretodctlb_ld.laddr = c1_s0_coretodctlb_ld_laddr;
assign c1_s0_coretodctlb_ld.imm = c1_s0_coretodctlb_ld_imm;
assign c1_s0_coretodctlb_ld.sptbr = c1_s0_coretodctlb_ld_sptbr;
assign c1_s0_coretodctlb_ld.user = c1_s0_coretodctlb_ld_user;
I_coretodctlb_st_type c1_s0_coretodctlb_st;
assign c1_s0_coretodctlb_st.ckpid = c1_s0_coretodctlb_st_ckpid;
assign c1_s0_coretodctlb_st.coreid = c1_s0_coretodctlb_st_coreid;
assign c1_s0_coretodctlb_st.mop = c1_s0_coretodctlb_st_mop;
assign c1_s0_coretodctlb_st.pnr = c1_s0_coretodctlb_st_pnr;
assign c1_s0_coretodctlb_st.laddr = c1_s0_coretodctlb_st_laddr;
assign c1_s0_coretodctlb_st.imm = c1_s0_coretodctlb_st_imm;
assign c1_s0_coretodctlb_st.sptbr = c1_s0_coretodctlb_st_sptbr;
assign c1_s0_coretodctlb_st.user = c1_s0_coretodctlb_st_user;
I_coretodc_ld_type core1_slice1_coretodc_ld;
assign core1_slice1_coretodc_ld.ckpid = core1_slice1_coretodc_ld_ckpid;
assign core1_slice1_coretodc_ld.coreid = core1_slice1_coretodc_ld_coreid;
assign core1_slice1_coretodc_ld.lop = core1_slice1_coretodc_ld_lop;
assign core1_slice1_coretodc_ld.pnr = core1_slice1_coretodc_ld_pnr;
assign core1_slice1_coretodc_ld.pcsign = core1_slice1_coretodc_ld_pcsign;
assign core1_slice1_coretodc_ld.poffset = core1_slice1_coretodc_ld_poffset;
assign core1_slice1_coretodc_ld.imm = core1_slice1_coretodc_ld_imm;
I_dctocore_ld_type core1_slice1_dctocore_ld;
assign core1_slice1_dctocore_ld_coreid = core1_slice1_dctocore_ld.coreid;
assign core1_slice1_dctocore_ld_fault = core1_slice1_dctocore_ld.fault;
assign core1_slice1_dctocore_ld_data = core1_slice1_dctocore_ld.data;
I_coretodc_std_type core1_slice1_coretodc_std;
assign core1_slice1_coretodc_std.ckpid = core1_slice1_coretodc_std_ckpid;
assign core1_slice1_coretodc_std.coreid = core1_slice1_coretodc_std_coreid;
assign core1_slice1_coretodc_std.mop = core1_slice1_coretodc_std_mop;
assign core1_slice1_coretodc_std.pnr = core1_slice1_coretodc_std_pnr;
assign core1_slice1_coretodc_std.pcsign = core1_slice1_coretodc_std_pcsign;
assign core1_slice1_coretodc_std.poffset = core1_slice1_coretodc_std_poffset;
assign core1_slice1_coretodc_std.imm = core1_slice1_coretodc_std_imm;
assign core1_slice1_coretodc_std.data = core1_slice1_coretodc_std_data;
I_dctocore_std_ack_type core1_slice1_dctocore_std_ack;
assign core1_slice1_dctocore_std_ack_fault = core1_slice1_dctocore_std_ack.fault;
assign core1_slice1_dctocore_std_ack_coreid = core1_slice1_dctocore_std_ack.coreid;
I_coretodctlb_ld_type c1_s1_coretodctlb_ld;
assign c1_s1_coretodctlb_ld.ckpid = c1_s1_coretodctlb_ld_ckpid;
assign c1_s1_coretodctlb_ld.coreid = c1_s1_coretodctlb_ld_coreid;
assign c1_s1_coretodctlb_ld.lop = c1_s1_coretodctlb_ld_lop;
assign c1_s1_coretodctlb_ld.pnr = c1_s1_coretodctlb_ld_pnr;
assign c1_s1_coretodctlb_ld.laddr = c1_s1_coretodctlb_ld_laddr;
assign c1_s1_coretodctlb_ld.imm = c1_s1_coretodctlb_ld_imm;
assign c1_s1_coretodctlb_ld.sptbr = c1_s1_coretodctlb_ld_sptbr;
assign c1_s1_coretodctlb_ld.user = c1_s1_coretodctlb_ld_user;
I_coretodctlb_st_type c1_s1_coretodctlb_st;
assign c1_s1_coretodctlb_st.ckpid = c1_s1_coretodctlb_st_ckpid;
assign c1_s1_coretodctlb_st.coreid = c1_s1_coretodctlb_st_coreid;
assign c1_s1_coretodctlb_st.mop = c1_s1_coretodctlb_st_mop;
assign c1_s1_coretodctlb_st.pnr = c1_s1_coretodctlb_st_pnr;
assign c1_s1_coretodctlb_st.laddr = c1_s1_coretodctlb_st_laddr;
assign c1_s1_coretodctlb_st.imm = c1_s1_coretodctlb_st_imm;
assign c1_s1_coretodctlb_st.sptbr = c1_s1_coretodctlb_st_sptbr;
assign c1_s1_coretodctlb_st.user = c1_s1_coretodctlb_st_user;
`ifdef SC_4PIPE
I_coretodc_ld_type core1_slice2_coretodc_ld;
assign core1_slice2_coretodc_ld.ckpid = core1_slice2_coretodc_ld_ckpid;
assign core1_slice2_coretodc_ld.coreid = core1_slice2_coretodc_ld_coreid;
assign core1_slice2_coretodc_ld.lop = core1_slice2_coretodc_ld_lop;
assign core1_slice2_coretodc_ld.pnr = core1_slice2_coretodc_ld_pnr;
assign core1_slice2_coretodc_ld.pcsign = core1_slice2_coretodc_ld_pcsign;
assign core1_slice2_coretodc_ld.poffset = core1_slice2_coretodc_ld_poffset;
assign core1_slice2_coretodc_ld.imm = core1_slice2_coretodc_ld_imm;
I_dctocore_ld_type core1_slice2_dctocore_ld;
assign core1_slice2_dctocore_ld_coreid = core1_slice2_dctocore_ld.coreid;
assign core1_slice2_dctocore_ld_fault = core1_slice2_dctocore_ld.fault;
assign core1_slice2_dctocore_ld_data = core1_slice2_dctocore_ld.data;
I_coretodc_std_type core1_slice2_coretodc_std;
assign core1_slice2_coretodc_std.ckpid = core1_slice2_coretodc_std_ckpid;
assign core1_slice2_coretodc_std.coreid = core1_slice2_coretodc_std_coreid;
assign core1_slice2_coretodc_std.mop = core1_slice2_coretodc_std_mop;
assign core1_slice2_coretodc_std.pnr = core1_slice2_coretodc_std_pnr;
assign core1_slice2_coretodc_std.pcsign = core1_slice2_coretodc_std_pcsign;
assign core1_slice2_coretodc_std.poffset = core1_slice2_coretodc_std_poffset;
assign core1_slice2_coretodc_std.imm = core1_slice2_coretodc_std_imm;
assign core1_slice2_coretodc_std.data = core1_slice2_coretodc_std_data;
I_dctocore_std_ack_type core1_slice2_dctocore_std_ack;
assign core1_slice2_dctocore_std_ack_fault = core1_slice2_dctocore_std_ack.fault;
assign core1_slice2_dctocore_std_ack_coreid = core1_slice2_dctocore_std_ack.coreid;
I_coretodctlb_ld_type c1_s2_coretodctlb_ld;
assign c1_s2_coretodctlb_ld.ckpid = c1_s2_coretodctlb_ld_ckpid;
assign c1_s2_coretodctlb_ld.coreid = c1_s2_coretodctlb_ld_coreid;
assign c1_s2_coretodctlb_ld.lop = c1_s2_coretodctlb_ld_lop;
assign c1_s2_coretodctlb_ld.pnr = c1_s2_coretodctlb_ld_pnr;
assign c1_s2_coretodctlb_ld.laddr = c1_s2_coretodctlb_ld_laddr;
assign c1_s2_coretodctlb_ld.imm = c1_s2_coretodctlb_ld_imm;
assign c1_s2_coretodctlb_ld.sptbr = c1_s2_coretodctlb_ld_sptbr;
assign c1_s2_coretodctlb_ld.user = c1_s2_coretodctlb_ld_user;
I_coretodctlb_st_type c1_s2_coretodctlb_st;
assign c1_s2_coretodctlb_st.ckpid = c1_s2_coretodctlb_st_ckpid;
assign c1_s2_coretodctlb_st.coreid = c1_s2_coretodctlb_st_coreid;
assign c1_s2_coretodctlb_st.mop = c1_s2_coretodctlb_st_mop;
assign c1_s2_coretodctlb_st.pnr = c1_s2_coretodctlb_st_pnr;
assign c1_s2_coretodctlb_st.laddr = c1_s2_coretodctlb_st_laddr;
assign c1_s2_coretodctlb_st.imm = c1_s2_coretodctlb_st_imm;
assign c1_s2_coretodctlb_st.sptbr = c1_s2_coretodctlb_st_sptbr;
assign c1_s2_coretodctlb_st.user = c1_s2_coretodctlb_st_user;
I_coretodc_ld_type core1_slice3_coretodc_ld;
assign core1_slice3_coretodc_ld.ckpid = core1_slice3_coretodc_ld_ckpid;
assign core1_slice3_coretodc_ld.coreid = core1_slice3_coretodc_ld_coreid;
assign core1_slice3_coretodc_ld.lop = core1_slice3_coretodc_ld_lop;
assign core1_slice3_coretodc_ld.pnr = core1_slice3_coretodc_ld_pnr;
assign core1_slice3_coretodc_ld.pcsign = core1_slice3_coretodc_ld_pcsign;
assign core1_slice3_coretodc_ld.poffset = core1_slice3_coretodc_ld_poffset;
assign core1_slice3_coretodc_ld.imm = core1_slice3_coretodc_ld_imm;
I_dctocore_ld_type core1_slice3_dctocore_ld;
assign core1_slice3_dctocore_ld_coreid = core1_slice3_dctocore_ld.coreid;
assign core1_slice3_dctocore_ld_fault = core1_slice3_dctocore_ld.fault;
assign core1_slice3_dctocore_ld_data = core1_slice3_dctocore_ld.data;
I_coretodc_std_type core1_slice3_coretodc_std;
assign core1_slice3_coretodc_std.ckpid = core1_slice3_coretodc_std_ckpid;
assign core1_slice3_coretodc_std.coreid = core1_slice3_coretodc_std_coreid;
assign core1_slice3_coretodc_std.mop = core1_slice3_coretodc_std_mop;
assign core1_slice3_coretodc_std.pnr = core1_slice3_coretodc_std_pnr;
assign core1_slice3_coretodc_std.pcsign = core1_slice3_coretodc_std_pcsign;
assign core1_slice3_coretodc_std.poffset = core1_slice3_coretodc_std_poffset;
assign core1_slice3_coretodc_std.imm = core1_slice3_coretodc_std_imm;
assign core1_slice3_coretodc_std.data = core1_slice3_coretodc_std_data;
I_dctocore_std_ack_type core1_slice3_dctocore_std_ack;
assign core1_slice3_dctocore_std_ack_fault = core1_slice3_dctocore_std_ack.fault;
assign core1_slice3_dctocore_std_ack_coreid = core1_slice3_dctocore_std_ack.coreid;
I_coretodctlb_ld_type c1_s3_coretodctlb_ld;
assign c1_s3_coretodctlb_ld.ckpid = c1_s3_coretodctlb_ld_ckpid;
assign c1_s3_coretodctlb_ld.coreid = c1_s3_coretodctlb_ld_coreid;
assign c1_s3_coretodctlb_ld.lop = c1_s3_coretodctlb_ld_lop;
assign c1_s3_coretodctlb_ld.pnr = c1_s3_coretodctlb_ld_pnr;
assign c1_s3_coretodctlb_ld.laddr = c1_s3_coretodctlb_ld_laddr;
assign c1_s3_coretodctlb_ld.imm = c1_s3_coretodctlb_ld_imm;
assign c1_s3_coretodctlb_ld.sptbr = c1_s3_coretodctlb_ld_sptbr;
assign c1_s3_coretodctlb_ld.user = c1_s3_coretodctlb_ld_user;
I_coretodctlb_st_type c1_s3_coretodctlb_st;
assign c1_s3_coretodctlb_st.ckpid = c1_s3_coretodctlb_st_ckpid;
assign c1_s3_coretodctlb_st.coreid = c1_s3_coretodctlb_st_coreid;
assign c1_s3_coretodctlb_st.mop = c1_s3_coretodctlb_st_mop;
assign c1_s3_coretodctlb_st.pnr = c1_s3_coretodctlb_st_pnr;
assign c1_s3_coretodctlb_st.laddr = c1_s3_coretodctlb_st_laddr;
assign c1_s3_coretodctlb_st.imm = c1_s3_coretodctlb_st_imm;
assign c1_s3_coretodctlb_st.sptbr = c1_s3_coretodctlb_st_sptbr;
assign c1_s3_coretodctlb_st.user = c1_s3_coretodctlb_st_user;
`endif
I_pfgtopfe_op_type core1_pfgtopfe_op;
assign core1_pfgtopfe_op.delta = core1_pfgtopfe_op_delta;
assign core1_pfgtopfe_op.w1 = core1_pfgtopfe_op_w1;
assign core1_pfgtopfe_op.w2 = core1_pfgtopfe_op_w2;
assign core1_pfgtopfe_op.pcsign = core1_pfgtopfe_op_pcsign;
assign core1_pfgtopfe_op.laddr = core1_pfgtopfe_op_laddr;
assign core1_pfgtopfe_op.sptbr = core1_pfgtopfe_op_sptbr;
I_drtomem_req_type dr0_drtomem_req;
assign dr0_drtomem_req_drid = dr0_drtomem_req.drid;
assign dr0_drtomem_req_cmd = dr0_drtomem_req.cmd;
assign dr0_drtomem_req_paddr = dr0_drtomem_req.paddr;
I_memtodr_ack_type dr0_memtodr_ack;
assign dr0_memtodr_ack.drid = dr0_memtodr_ack_drid;
assign dr0_memtodr_ack.nid = dr0_memtodr_ack_nid;
assign dr0_memtodr_ack.paddr = dr0_memtodr_ack_paddr;
assign dr0_memtodr_ack.ack = dr0_memtodr_ack_ack;
assign dr0_memtodr_ack.line = dr0_memtodr_ack_line;
I_drtomem_wb_type dr0_drtomem_wb;
assign dr0_drtomem_wb_line = dr0_drtomem_wb.line;
assign dr0_drtomem_wb_paddr = dr0_drtomem_wb.paddr;
I_drtomem_pfreq_type dr0_drtomem_pfreq;
assign dr0_drtomem_pfreq_nid = dr0_drtomem_pfreq.nid;
assign dr0_drtomem_pfreq_paddr = dr0_drtomem_pfreq.paddr;
I_drtomem_req_type dr1_drtomem_req;
assign dr1_drtomem_req_drid = dr1_drtomem_req.drid;
assign dr1_drtomem_req_cmd = dr1_drtomem_req.cmd;
assign dr1_drtomem_req_paddr = dr1_drtomem_req.paddr;
I_memtodr_ack_type dr1_memtodr_ack;
assign dr1_memtodr_ack.drid = dr1_memtodr_ack_drid;
assign dr1_memtodr_ack.nid = dr1_memtodr_ack_nid;
assign dr1_memtodr_ack.paddr = dr1_memtodr_ack_paddr;
assign dr1_memtodr_ack.ack = dr1_memtodr_ack_ack;
assign dr1_memtodr_ack.line = dr1_memtodr_ack_line;
I_drtomem_wb_type dr1_drtomem_wb;
assign dr1_drtomem_wb_line = dr1_drtomem_wb.line;
assign dr1_drtomem_wb_paddr = dr1_drtomem_wb.paddr;
I_drtomem_pfreq_type dr1_drtomem_pfreq;
assign dr1_drtomem_pfreq_nid = dr1_drtomem_pfreq.nid;
assign dr1_drtomem_pfreq_paddr = dr1_drtomem_pfreq.paddr;
top_2core2dr top(.*);
endmodule
|
module top();
// Inputs are registered
reg VPWR;
reg VGND;
// Outputs are wires
initial
begin
// Initial state is x for all inputs.
VGND = 1'bX;
VPWR = 1'bX;
#20 VGND = 1'b0;
#40 VPWR = 1'b0;
#60 VGND = 1'b1;
#80 VPWR = 1'b1;
#100 VGND = 1'b0;
#120 VPWR = 1'b0;
#140 VPWR = 1'b1;
#160 VGND = 1'b1;
#180 VPWR = 1'bx;
#200 VGND = 1'bx;
end
sky130_fd_sc_hs__tap dut (.VPWR(VPWR), .VGND(VGND));
endmodule
|
module slaveRxStatusMonitor(connectStateIn, connectStateOut, resumeDetectedIn, resetEventOut, resumeIntOut, clk, rst);
input [1:0] connectStateIn;
input resumeDetectedIn;
input clk;
input rst;
output resetEventOut;
output [1:0] connectStateOut;
output resumeIntOut;
wire [1:0] connectStateIn;
wire resumeDetectedIn;
reg resetEventOut;
reg [1:0] connectStateOut;
reg resumeIntOut;
wire clk;
wire rst;
reg [1:0]oldConnectState;
reg oldResumeDetected;
always @(connectStateIn)
begin
connectStateOut <= connectStateIn;
end
always @(posedge clk)
begin
if (rst == 1'b1)
begin
oldConnectState <= connectStateIn;
oldResumeDetected <= resumeDetectedIn;
end
else
begin
oldConnectState <= connectStateIn;
oldResumeDetected <= resumeDetectedIn;
if (oldConnectState != connectStateIn)
resetEventOut <= 1'b1;
else
resetEventOut <= 1'b0;
if (resumeDetectedIn == 1'b1 && oldResumeDetected == 1'b0)
resumeIntOut <= 1'b1;
else
resumeIntOut <= 1'b0;
end
end
endmodule
|
module fifo_26x256 (
clock,
data,
rdreq,
wrreq,
empty,
full,
q,
usedw);
input clock;
input [25:0] data;
input rdreq;
input wrreq;
output empty;
output full;
output [25:0] q;
output [7:0] usedw;
wire [7:0] sub_wire0;
wire sub_wire1;
wire [25:0] sub_wire2;
wire sub_wire3;
wire [7:0] usedw = sub_wire0[7:0];
wire empty = sub_wire1;
wire [25:0] q = sub_wire2[25:0];
wire full = sub_wire3;
scfifo scfifo_component (
.rdreq (rdreq),
.clock (clock),
.wrreq (wrreq),
.data (data),
.usedw (sub_wire0),
.empty (sub_wire1),
.q (sub_wire2),
.full (sub_wire3)
// synopsys translate_off
,
.aclr (),
.almost_empty (),
.almost_full (),
.sclr ()
// synopsys translate_on
);
defparam
scfifo_component.add_ram_output_register = "OFF",
scfifo_component.intended_device_family = "Cyclone III",
scfifo_component.lpm_hint = "RAM_BLOCK_TYPE=M9K",
scfifo_component.lpm_numwords = 256,
scfifo_component.lpm_showahead = "OFF",
scfifo_component.lpm_type = "scfifo",
scfifo_component.lpm_width = 26,
scfifo_component.lpm_widthu = 8,
scfifo_component.overflow_checking = "OFF",
scfifo_component.underflow_checking = "OFF",
scfifo_component.use_eab = "ON";
endmodule
|
module DcTile3(
/* verilator lint_off UNUSED */
clock, reset,
regInData, regOutData,
regInAddr, regOutOK,
regInOE, regInWR,
regInOp,
memPcData, memOutData,
memPcAddr, memPcOK,
memPcOE, memPcWR,
memPcOp
);
input clock;
input reset;
input[63:0] regInAddr; //input PC address
input[63:0] regInData; //input data (store)
input regInOE; //Load
input regInWR; //Store
input[4:0] regInOp; //Operation Size/Type
output[63:0] regOutData; //output data (load)
output[1:0] regOutOK; //set if operation suceeds
input[127:0] memPcData; //memory data in
output[127:0] memOutData; //memory data out
output[63:0] memPcAddr; //memory address
output memPcOE; //memory load
output memPcWR; //memory store
input[1:0] memPcOK; //memory OK
output[4:0] memPcOp; //memory PC operation
// reg[31:0] icBlkLo[511:0]; //Block Low DWord
// reg[31:0] icBlkHi[511:0]; //Block High DWord
(* ram_style="block" *) reg[31:0] icBlkA[255:0]; //Block DWord A
(* ram_style="block" *) reg[31:0] icBlkB[255:0]; //Block DWord B
(* ram_style="block" *) reg[31:0] icBlkC[255:0]; //Block DWord C
(* ram_style="block" *) reg[31:0] icBlkD[255:0]; //Block DWord D
(* ram_style="block" *) reg[31:0] icBlkE[255:0]; //Block DWord E
(* ram_style="block" *) reg[27:0] icBlkAd[255:0]; //Block Addresses
(* ram_style="block" *) reg[3:0] icBlkFl[255:0]; //Block Addresses
reg[31:0] tRegInPc1;
reg[31:0] tRegInPc2;
reg[27:0] tBlkNeedAd1;
reg[27:0] tBlkNeedAd2;
reg[27:0] tBlkNeedAd3;
reg[27:0] tBlkNeedAd4;
reg[31:0] tRegInPc3;
reg[31:0] tRegInPc4;
reg[63:0] tBlkData1;
reg[63:0] tBlkData2;
reg[63:0] tBlkData2B;
reg[63:0] tBlkData3;
reg[63:0] tBlkData4;
reg[63:0] tRegOutData;
reg[1:0] tRegOutOK;
reg tRdZx;
reg[63:0] tRegInData;
reg[63:0] tMemPcAddr; //memory address
reg tMemPcOE; //memory load
reg tMemPcWR; //memory store
reg[127:0] tMemOutData; //memory data
reg[4:0] tMemPcOp; //memory operation
assign memPcAddr = tMemPcAddr;
assign memOutData = tMemOutData;
assign memPcOE = tMemPcOE;
assign memPcWR = tMemPcWR;
assign memPcOp = tMemPcOp;
reg[27:0] reqNeedAd;
reg[27:0] nReqNeedAd;
assign regOutData = tRegOutData;
assign regOutOK = tRegOutOK;
assign memPcAddr = tMemPcAddr;
assign memPcOE = tMemPcOE;
reg[63:0] tRegOutDataB;
reg[3:0] isReqTileSt;
reg[27:0] isReqNeedAd;
reg[3:0] nxtReqTileSt;
reg[27:0] nxtReqNeedAd;
reg nxtReqCommit;
reg[27:0] nxtReqCommitAd1;
reg[27:0] nxtReqCommitAd2;
reg[3:0] nxtReqCommitFl;
reg[159:0] reqTempBlk;
reg[159:0] nxtReqTempBlk;
reg[159:0] accTempBlk;
reg accHit;
reg accNoCache;
reg nxtAccHit;
reg accCommitOK;
reg nxtAccCommitOK;
always @*
begin
tRegInPc1=regInAddr[31:0];
tRegInPc2=regInAddr[31:0]+4;
tBlkNeedAd1=tRegInPc1[31:4];
tBlkNeedAd2=tRegInPc2[31:4];
tRegOutData=0;
tRegOutOK=0;
nReqNeedAd=0;
tBlkNeedAd3=tBlkNeedAd1;
tBlkNeedAd4=tBlkNeedAd2;
nxtReqTempBlk=reqTempBlk;
nxtReqCommitFl=0;
tBlkData2=UV64_XX;
nxtReqCommitAd1=28'hXXXXXXX;
nxtReqCommitAd2=28'hXXXXXXX;
nxtAccCommitOK=0;
nxtReqNeedAd=0;
// tMemPcAddr=32'hX;
tMemPcAddr=0;
tMemOutData=128'hX;
tMemPcOE=0;
tMemPcWR=0;
tMemPcOp=0;
nxtAccHit=0;
// accHit=0;
accNoCache=0;
if(regInAddr[31:29]==3'b101)
accNoCache=1;
if(regInAddr[31:29]==3'b110)
accNoCache=1;
if(regInAddr[31:29]==3'b111)
accNoCache=1;
if((regInOE || regInWR) &&
(isReqTileSt==0))
begin
if(accNoCache)
begin
nxtAccHit=0;
// accTempBlk=160'hX;
tMemPcAddr[29:2]=regInAddr[29:2];
tMemOutData={96'h0, regInData[31:0]};
tMemPcOE=regInOE;
tMemPcWR=regInWR;
tMemPcOp=1;
tRegOutOK=memPcOK;
end
else
begin
if((tBlkNeedAd1==icBlkAd[tBlkNeedAd1[7:0]]) &&
(tBlkNeedAd2==icBlkAd[tBlkNeedAd2[7:0]]))
begin
nxtAccHit=1;
end
else if(tBlkNeedAd1==icBlkAd[tBlkNeedAd1[7:0]])
begin
nReqNeedAd=tBlkNeedAd2;
tBlkNeedAd3=tBlkNeedAd2;
end
else
begin
nReqNeedAd=tBlkNeedAd1;
tBlkNeedAd3=tBlkNeedAd1;
end
end
if(nxtAccHit)
begin
/* Read Stage */
case(regInAddr[3:2])
2'b00: tBlkData2=accTempBlk[ 63: 0];
2'b01: tBlkData2=accTempBlk[ 95: 32];
2'b10: tBlkData2=accTempBlk[127: 64];
2'b11: tBlkData2=accTempBlk[159: 96];
endcase
tRdZx = (regInOp[4:2]==3'b011);
case(regInOp[1:0])
2'b00: begin
case(regInAddr[1:0])
2'b00: tRegOutData={
(tBlkData2[ 7] && !tRdZx) ? 56'hF : 56'h0,
tBlkData2[ 7: 0] };
2'b01: tRegOutData={
(tBlkData2[15] && !tRdZx) ? 56'hF : 56'h0,
tBlkData2[15: 8]};
2'b10: tRegOutData={
(tBlkData2[23] && !tRdZx) ? 56'hF : 56'h0,
tBlkData2[23:16]};
2'b11: tRegOutData={
(tBlkData2[31] && !tRdZx) ? 56'hF : 56'h0,
tBlkData2[31:24]};
endcase
end
2'b01: begin
case(regInAddr[1:0])
2'b00: tRegOutData={
(tBlkData2[15] && !tRdZx) ? 48'hF : 48'h0,
tBlkData2[ 15: 0] };
2'b01: tRegOutData={
(tBlkData2[23] && !tRdZx) ? 48'hF : 48'h0,
tBlkData2[23: 8]};
2'b10: tRegOutData={
(tBlkData2[31] && !tRdZx) ? 48'hF : 48'h0,
tBlkData2[31:16]};
2'b11: tRegOutData={
(tBlkData2[39] && !tRdZx) ? 48'hF : 48'h0,
tBlkData2[39:24]};
endcase
end
2'b10: begin
case(regInAddr[1:0])
2'b00: tRegOutData={
(tBlkData2[31] && !tRdZx) ? 32'hF : 32'h0,
tBlkData2[ 31: 0] };
2'b01: tRegOutData={
(tBlkData2[39] && !tRdZx) ? 32'hF : 32'h0,
tBlkData2[39: 8]};
2'b10: tRegOutData={
(tBlkData2[47] && !tRdZx) ? 32'hF : 32'h0,
tBlkData2[47:16]};
2'b11: tRegOutData={
(tBlkData2[55] && !tRdZx) ? 32'hF : 32'h0,
tBlkData2[55:24]};
endcase
end
2'b11: tRegOutData= tBlkData2[63: 0] ;
endcase
/* Write Stage */
tRegInData = regInData;
case(regInOp[4:2])
3'b000: tRegInData = regInData;
3'b001: tRegInData = tRegOutDataB + regInData;
3'b010: tRegInData = tRegOutDataB - regInData;
3'b011: tRegInData = regInData;
3'b100: tRegInData = tRegOutDataB & regInData;
3'b101: tRegInData = tRegOutDataB | regInData;
3'b110: tRegInData = tRegOutDataB ^ regInData;
3'b111: tRegInData = regInData;
endcase
case(regInOp[1:0])
2'b00: begin
case(regInAddr[1:0])
2'b00: begin
tBlkData3[ 7:0]=tRegInData[ 7:0];
tBlkData3[63:8]=tBlkData2B[63:8];
end
2'b01: begin
tBlkData3[ 7: 0]=tBlkData2B[ 7: 0];
tBlkData3[15: 8]=tRegInData[ 7: 0];
tBlkData3[63:16]=tBlkData2B[63:16];
end
2'b10: begin
tBlkData3[15: 0]=tBlkData2B[15: 0];
tBlkData3[23:16]=tRegInData[ 7: 0];
tBlkData3[63:24]=tBlkData2B[63:24];
end
2'b11: begin
tBlkData3[23: 0]=tBlkData2B[23: 0];
tBlkData3[31:24]=tRegInData[ 7: 0];
tBlkData3[63:32]=tBlkData2B[63:32];
end
endcase
end
2'b01: begin
case(regInAddr[1:0])
2'b00: begin
tBlkData3[15: 0]=tRegInData[15: 0];
tBlkData3[63:16]=tBlkData2B[63:16];
end
2'b01: begin
tBlkData3[ 7: 0]=tBlkData2B[ 7: 0];
tBlkData3[23: 8]=tRegInData[15: 0];
tBlkData3[63:24]=tBlkData2B[63:24];
end
2'b10: begin
tBlkData3[15: 0]=tBlkData2B[15: 0];
tBlkData3[31:16]=tRegInData[15: 0];
tBlkData3[63:32]=tBlkData2B[63:32];
end
2'b11: begin
tBlkData3[23: 0]=tBlkData2B[23: 0];
tBlkData3[39:24]=tRegInData[15: 0];
tBlkData3[63:40]=tBlkData2B[63:40];
end
endcase
end
2'b10: begin
case(regInAddr[1:0])
2'b00: begin
tBlkData3[31: 0]=tRegInData[31: 0];
tBlkData3[63:32]=tBlkData2B[63:32];
end
2'b01: begin
tBlkData3[ 7: 0]=tBlkData2B[ 7: 0];
tBlkData3[39: 8]=tRegInData[31: 0];
tBlkData3[63:40]=tBlkData2B[63:40];
end
2'b10: begin
tBlkData3[15: 0]=tBlkData2B[15: 0];
tBlkData3[47:16]=tRegInData[31: 0];
tBlkData3[63:48]=tBlkData2B[63:48];
end
2'b11: begin
tBlkData3[23: 0]=tBlkData2B[23: 0];
tBlkData3[55:24]=tRegInData[31: 0];
tBlkData3[63:56]=tBlkData2B[63:56];
end
endcase
end
2'b11: begin
tBlkData3[63: 0]=tRegInData[63: 0];
end
endcase
// tBlkData4[31: 0]=regInPc[2]?tBlkData3[63:32]:tBlkData3[31: 0];
// tBlkData4[63:32]=regInPc[2]?tBlkData3[31: 0]:tBlkData3[63:32];
nxtReqTempBlk=accTempBlk;
case(regInAddr[3:2])
2'b00: nxtReqTempBlk[ 63: 0]=tBlkData3;
2'b01: nxtReqTempBlk[ 95: 32]=tBlkData3;
2'b10: nxtReqTempBlk[127: 64]=tBlkData3;
2'b11: nxtReqTempBlk[159: 96]=tBlkData3;
endcase
nxtReqCommit=regInWR && accHit;
nxtReqCommitAd1=tBlkNeedAd3;
nxtReqCommitAd2=tBlkNeedAd4;
nxtReqCommitFl=1;
nxtAccCommitOK = regInWR && accHit;
/* Output */
tRegOutOK=((accHit && !regInWR) || accCommitOK) ?
UMEM_OK_OK : UMEM_OK_HOLD;
end
end
nxtReqTileSt=isReqTileSt;
nxtReqCommit=0;
case(isReqTileSt)
4'h0: begin
if(reqNeedAd!=0)
begin
nxtReqNeedAd=reqNeedAd;
nxtReqTileSt=4;
if(icBlkFl[reqNeedAd[7:0]][0])
begin
nxtReqTempBlk=accTempBlk;
nxtReqTileSt=8;
end
end
end
4'h1: begin
nxtReqTileSt=0;
end
4'h2: begin
nxtReqTempBlk[127: 0]=memPcData[127:0];
nxtReqTempBlk[159:128]=memPcData[ 31:0];
tMemPcAddr[31:4]=isReqNeedAd;
tMemPcAddr[3:2]=0;
tMemPcOE=1;
tMemPcWR=0;
tMemPcOp=1;
nxtReqTileSt=4'h1;
nxtReqCommit=1;
nxtReqCommitAd1=isReqNeedAd;
nxtReqCommitAd2=isReqNeedAd;
nxtReqCommitFl=0;
end
4'h3: begin
tMemPcAddr[31:4]=icBlkAd[reqNeedAd[7:0]];
tMemPcAddr[3:2]=0;
tMemOutData[127:0] = nxtReqTempBlk[127: 0];
tMemPcOE=0;
tMemPcWR=1;
tMemPcOp=1;
nxtReqTileSt=4'h1;
end
4'h4: begin
tMemPcAddr[31:4]=isReqNeedAd;
tMemPcAddr[3:2]=isReqTileSt[1:0];
tMemPcOE=1;
tMemPcOp=2;
nxtReqTileSt=5;
nxtReqTempBlk[ 31: 0]=memPcData[31:0];
nxtReqTempBlk[159:128]=memPcData[31:0];
end
4'h5: begin
tMemPcAddr[31:4]=isReqNeedAd;
tMemPcAddr[3:2]=isReqTileSt[1:0];
tMemPcOE=1;
tMemPcOp=2;
nxtReqTileSt=6;
nxtReqTempBlk[63:32]=memPcData[31:0];
end
4'h6: begin
tMemPcAddr[31:4]=isReqNeedAd;
tMemPcAddr[3:2]=isReqTileSt[1:0];
tMemPcOE=1;
tMemPcOp=2;
nxtReqTileSt=7;
nxtReqTempBlk[95:64]=memPcData[31:0];
end
4'h7: begin
tMemPcAddr[31:4]=isReqNeedAd;
tMemPcAddr[3:2]=isReqTileSt[1:0];
tMemPcOE=1;
tMemPcOp=2;
nxtReqTileSt=1;
nxtReqTempBlk[127:96]=memPcData[31:0];
nxtReqCommit=1;
nxtReqCommitAd1=isReqNeedAd;
nxtReqCommitAd2=isReqNeedAd;
nxtReqCommitFl=0;
end
4'h8: begin
tMemPcAddr[31:4]=icBlkAd[reqNeedAd[7:0]];
tMemPcAddr[3:2]=isReqTileSt[1:0];
tMemOutData[31:0] = nxtReqTempBlk[ 31: 0];
tMemPcWR=1;
tMemPcOp=2;
nxtReqTileSt=4'h9;
end
4'h9: begin
tMemPcAddr[31:4]=icBlkAd[reqNeedAd[7:0]];
tMemPcAddr[3:2]=isReqTileSt[1:0];
tMemOutData[31:0] = nxtReqTempBlk[ 63: 32];
tMemPcWR=1;
tMemPcOp=2;
nxtReqTileSt=4'hA;
end
4'hA: begin
tMemPcAddr[31:4]=icBlkAd[reqNeedAd[7:0]];
tMemPcAddr[3:2]=isReqTileSt[1:0];
tMemOutData[31:0] = nxtReqTempBlk[ 95: 64];
tMemPcWR=1;
tMemPcOp=2;
nxtReqTileSt=4'hB;
end
4'hB: begin
tMemPcAddr[31:4]=icBlkAd[reqNeedAd[7:0]];
tMemPcAddr[3:2]=isReqTileSt[1:0];
tMemOutData[31:0] = nxtReqTempBlk[127: 96];
tMemPcWR=1;
tMemPcOp=2;
nxtReqTileSt=4'h1;
end
default: begin end
endcase
end
always @ (posedge clock)
begin
reqNeedAd <= nReqNeedAd;
isReqNeedAd <= nxtReqNeedAd;
reqTempBlk <= nxtReqTempBlk;
accTempBlk[ 31: 0] <= icBlkA[tBlkNeedAd3[7:0]];
accTempBlk[ 63: 32] <= icBlkB[tBlkNeedAd3[7:0]];
accTempBlk[ 95: 64] <= icBlkC[tBlkNeedAd3[7:0]];
accTempBlk[127: 96] <= icBlkD[tBlkNeedAd3[7:0]];
accTempBlk[159:128] <= icBlkE[tBlkNeedAd4[7:0]];
accHit <= nxtAccHit;
accCommitOK <= nxtAccCommitOK;
tBlkData2B <= tBlkData2;
tRegOutDataB <= tRegOutData;
if(nxtReqCommit)
begin
icBlkA[nxtReqCommitAd1[7:0]] <= nxtReqTempBlk[ 31: 0];
icBlkB[nxtReqCommitAd1[7:0]] <= nxtReqTempBlk[ 63: 32];
icBlkC[nxtReqCommitAd1[7:0]] <= nxtReqTempBlk[ 95: 64];
icBlkD[nxtReqCommitAd1[7:0]] <= nxtReqTempBlk[127: 96];
icBlkE[nxtReqCommitAd2[7:0]] <= nxtReqTempBlk[159:128];
icBlkAd[nxtReqCommitAd1[7:0]] <= nxtReqCommitAd1;
icBlkFl[nxtReqCommitAd1[7:0]] <= nxtReqCommitFl;
end
if(memPcOK==UMEM_OK_OK)
begin
isReqTileSt <= nxtReqTileSt;
end
else if(memPcOK==UMEM_OK_READY)
begin
case(isReqTileSt)
4'h0: begin
isReqTileSt <= nxtReqTileSt;
end
4'h1: begin
isReqTileSt <= nxtReqTileSt;
end
default: begin end
endcase
end
end
endmodule
|
module MC6502MemoryController(
clk,
rst_x,
i_rdy,
i_db,
o_db,
o_ab,
o_rw,
o_sync,
// InterruptLogic interfaces
il2mc_addr,
il2mc_read,
il2mc_write,
il2mc_data,
mc2il_data,
mc2il_brk,
// RegisterFile interfaces
rf2mc_pc,
rf2mc_a,
rf2mc_x,
rf2mc_y,
rf2mc_s,
rf2mc_psr,
mc2rf_fetched,
mc2rf_pushed,
mc2rf_pull,
mc2rf_pc,
mc2rf_set_pc,
mc2rf_psr,
mc2rf_set_psr,
// InstructionDecode interfaces
id2mc_fetch,
id2mc_sync,
id2mc_operand,
id2mc_modex,
id2mc_mode,
id2mc_reg,
id2mc_store,
id2mc_push,
id2mc_pop,
id2mc_p_reg,
id2mc_jump,
mc2id_data,
mc2id_valid,
// ExecutionController interfaces
ec2mc_data,
ec2mc_store);
input clk;
input rst_x;
input i_rdy;
input [ 7:0] i_db;
output [ 7:0] o_db;
output [15:0] o_ab;
output o_rw;
output o_sync;
input [15:0] il2mc_addr;
input il2mc_read;
input il2mc_write;
input [ 7:0] il2mc_data;
output [ 7:0] mc2il_data;
output mc2il_brk;
input [15:0] rf2mc_pc;
input [ 7:0] rf2mc_a;
input [ 7:0] rf2mc_x;
input [ 7:0] rf2mc_y;
input [ 7:0] rf2mc_s;
input [ 7:0] rf2mc_psr;
output mc2rf_fetched;
output mc2rf_pushed;
output mc2rf_pull;
output [15:0] mc2rf_pc;
output mc2rf_set_pc;
output [ 7:0] mc2rf_psr;
output mc2rf_set_psr;
input id2mc_fetch;
input id2mc_sync;
input id2mc_operand;
input [ 2:0] id2mc_mode;
input id2mc_modex;
input [ 1:0] id2mc_reg;
input id2mc_store;
input id2mc_push;
input id2mc_pop;
input id2mc_p_reg;
input id2mc_jump;
output [ 7:0] mc2id_data;
output mc2id_valid;
input [ 7:0] ec2mc_data;
input ec2mc_store;
reg [ 2:0] r_operand;
reg r_modex;
reg [ 2:0] r_mode;
reg [15:0] r_data;
reg [ 1:0] r_reg;
reg r_carry;
reg r_store;
reg r_push;
reg r_pop;
reg r_jump;
wire w_adder_valid;
wire [ 8:0] w_adder_sum;
wire [ 7:0] w_adder_in_a;
wire [ 7:0] w_adder_in_b;
wire w_write;
wire w_push_cycle;
wire w_pop_cycle;
wire w_il_active;
wire [15:0] w_il_addr;
wire w_id_active;
wire [15:0] w_id_addr;
wire w_1t_mode;
wire w_2t_mode;
wire w_3t_mode;
wire w_4t_mode;
wire w_5t_mode;
wire w_6t_mode;
wire w_fetch_opcode;
wire w_fetch_next;
wire w_register;
wire w_immediate;
wire w_absolute;
wire w_absolute_pc;
wire w_indirect_pc;
wire w_abs_idx;
wire w_abs_idx_x;
wire w_abs_idx_y;
wire w_zero_page;
wire w_zero_idx;
wire w_zero_idx_x;
wire w_zero_idx_y;
wire w_indirect;
wire w_indirect_x;
wire w_indirect_y;
wire [15:0] w_immediate_addr;
wire [15:0] w_absolute_addr;
wire [15:0] w_abs_idx_addr;
wire [15:0] w_zero_page_addr;
wire [15:0] w_zero_idx_addr;
wire [15:0] w_indirect_addr;
wire [15:0] w_idx_ind_addr;
wire [15:0] w_ind_idx_addr;
wire w_abs_idx_add;
wire w_zero_idx_add;
wire w_idx_ind_add;
wire w_ind_idx_add;
wire [ 7:0] w_register_data;
wire [ 7:0] w_jsr_data;
wire w_jmp;
wire w_jsr;
wire w_brk;
wire w_rts;
wire w_rti;
`include "MC6502Common.vh"
assign o_db = ec2mc_store ? ec2mc_data :
il2mc_write ? il2mc_data :
(r_push & r_jump) ? w_jsr_data :
(r_reg == REG_A) ? rf2mc_a :
(r_reg == REG_Y) ? rf2mc_y :
(r_push & !r_jump) ? rf2mc_psr : rf2mc_x;
assign o_ab = w_il_active ? w_il_addr :
ec2mc_store ? r_data :
w_push_cycle ? { 8'h01, rf2mc_s } :
w_pop_cycle ? { 8'h01, rf2mc_s } : w_id_addr;
assign o_rw = !w_write;
assign o_sync = w_id_active & id2mc_sync;
assign mc2il_data = il2mc_read ? i_db : 8'hxx;
assign mc2il_brk = w_brk & (r_operand == 3'b101);
assign mc2rf_fetched = w_fetch_opcode | w_fetch_next;
assign mc2rf_pushed = w_push_cycle;
assign mc2rf_pull = ((w_rts | w_rti) & ((r_operand == 3'b101) |
(r_operand == 3'b100))) |
(!w_rts & r_pop & (r_operand == 3'b011));
assign mc2rf_pc = (w_jsr | w_rts | w_rti) ? r_data :
{ i_db, r_data[15:8] };
assign mc2rf_set_pc = (w_jmp & ((r_operand == 3'b001) |
((r_operand == 3'b11) & w_indirect_pc))) |
((w_jsr | w_rti)& (r_operand == 3'b001)) |
(w_rts & (r_operand == 3'b010));
assign mc2rf_psr = mc2rf_set_psr ? i_db : 8'hxx;
assign mc2rf_set_psr = w_rti & (r_operand == 3'b100);
assign mc2id_data = (!mc2id_valid | w_write) ? 8'hxx :
(!w_fetch_opcode & w_register) ? w_register_data :
i_db;
assign mc2id_valid = w_fetch_opcode | (r_operand == 3'b001);
assign w_write = (r_store & (r_operand == 3'b001)) |
ec2mc_store | w_push_cycle | il2mc_write;
assign w_push_cycle = (r_push & !r_jump & (r_operand == 3'b010)) |
(w_jsr & ((r_operand == 3'b011) |
(r_operand == 3'b010)));
assign w_pop_cycle = r_pop & ((!r_jump & ((r_operand == 3'b010) |
(r_operand == 3'b001))) |
(r_jump & ((r_operand == 3'b100) |
(r_operand == 3'b011))) |
(w_rti & (r_operand == 3'b010)));
assign w_il_active = il2mc_read | il2mc_write;
assign w_il_addr = il2mc_addr;
assign w_id_active = !w_il_active;
assign w_id_addr = (r_operand == 3'b000) ? rf2mc_pc :
w_immediate ? w_immediate_addr :
w_absolute ? w_absolute_addr :
w_abs_idx ? w_abs_idx_addr :
w_zero_page ? w_zero_page_addr :
w_zero_idx ? w_zero_idx_addr :
w_indirect ? w_indirect_addr : rf2mc_pc;
assign w_1t_mode = !id2mc_push & !id2mc_pop &
((id2mc_modex & (id2mc_mode == MODEX_IMMEDIATE)) |
(!id2mc_modex & (id2mc_mode == MODE_IMMEDIATE)) |
(id2mc_modex & (id2mc_mode == MODEX_REGISTER)));
assign w_2t_mode = (id2mc_mode == MODE_ZERO_PAGE) |
((id2mc_mode == MODEX_ABSOLUTE_PC) & id2mc_jump &
!id2mc_push) |
(id2mc_push & !id2mc_jump);
assign w_3t_mode = ((id2mc_mode == MODE_ABSOLUTE) & !id2mc_jump) |
(id2mc_pop & !id2mc_jump) |
(id2mc_mode == MODE_ZERO_PAGE_INDEX_X) |
(id2mc_mode == MODE_ABSOLUTE_INDEXED_X) |
(id2mc_mode == MODE_ABSOLUTE_INDEXED_Y);
assign w_4t_mode = id2mc_mode == MODE_INDIRECT_INDEX;
assign w_5t_mode = !id2mc_jump & !id2mc_modex &
(id2mc_mode == MODE_INDEXED_INDIRECT) |
(id2mc_jump & id2mc_push & !id2mc_p_reg) |
(id2mc_jump & id2mc_pop);
assign w_6t_mode = (id2mc_jump & id2mc_push & id2mc_p_reg);
assign w_register = r_modex & (r_mode == MODEX_REGISTER);
assign w_immediate = (r_modex & (r_mode == MODEX_IMMEDIATE)) |
(!r_modex & (r_mode == MODE_IMMEDIATE));
assign w_absolute = (r_mode == MODEX_ABSOLUTE) & !r_jump;
assign w_absolute_pc = (r_mode == MODEX_ABSOLUTE_PC) &
(w_jmp | (r_jump & r_push));
assign w_indirect_pc = (r_mode == MODEX_INDIRECT_PC) & w_jmp;
assign w_abs_idx = (r_mode == MODE_ABSOLUTE_INDEXED_X) |
(r_mode == MODE_ABSOLUTE_INDEXED_Y);
assign w_abs_idx_x = !r_modex && (r_mode == MODE_ABSOLUTE_INDEXED_X);
assign w_abs_idx_y = w_abs_idx & !w_abs_idx_x;
assign w_zero_page = r_mode == MODEX_ZERO_PAGE;
assign w_zero_idx = r_mode == MODE_ZERO_PAGE_INDEX_X;
assign w_zero_idx_x = !r_modex & w_zero_idx;
assign w_zero_idx_y = r_modex & w_zero_idx;
assign w_indirect = !r_modex & ((r_mode == MODE_INDEXED_INDIRECT) |
(r_mode == MODE_INDIRECT_INDEX));
assign w_indirect_x = !r_modex & (r_mode == MODE_INDEXED_INDIRECT);
assign w_indirect_y = !r_modex & (r_mode == MODE_INDIRECT_INDEX);
assign w_immediate_addr = rf2mc_pc;
assign w_absolute_addr = (r_operand != 3'b001) ? rf2mc_pc : r_data;
assign w_abs_idx_addr = ((r_operand == 3'b010) && r_carry) ? r_data :
(r_operand == 3'b001) ? r_data : rf2mc_pc;
assign w_zero_page_addr = (r_operand == 3'b010) ? rf2mc_pc :
{ 8'h00, r_data[15:8] };
assign w_zero_idx_addr = (r_operand == 3'b010) ? { 8'h00, r_data[15:8] } :
(r_operand == 3'b001) ? { 8'h00, r_data[7:0] } :
rf2mc_pc;
assign w_idx_ind_addr = (r_operand == 3'b100) ? { 8'h00, r_data[15:8] } :
(r_operand == 3'b011) ? { 8'h00, r_data[7:0] } :
(r_operand == 3'b010) ? { 8'h00, r_data[7:0] } :
(r_operand == 3'b001) ? { 8'h00, r_data[7:0] } :
rf2mc_pc;
assign w_ind_idx_addr = (r_operand == 3'b011) ? { 8'h00, r_data[15:8] } :
(r_operand == 3'b010) ? { 8'h00, r_data[7:0] } :
(r_operand == 3'b001) ? r_data : rf2mc_pc;
assign w_indirect_addr = w_indirect_x ? w_idx_ind_addr : w_ind_idx_addr;
assign w_abs_idx_add = w_abs_idx & (r_operand == 3'b010);
assign w_zero_idx_add = w_zero_idx & (r_operand == 3'b010);
assign w_idx_ind_add = w_indirect_x & ((r_operand == 3'b100) |
(r_operand == 3'b011));
assign w_ind_idx_add = w_indirect_y & ((r_operand == 3'b011) |
(r_operand == 3'b010));
assign w_fetch_opcode = w_id_active & id2mc_fetch & i_rdy;
assign w_fetch_next = ((w_absolute | w_abs_idx) & (r_operand == 3'b011)) |
(w_jmp & (r_operand == 3'b010)) |
(w_indirect_pc & (r_operand == 3'b100)) |
(w_absolute_pc & (r_operand == 3'b010)) |
(!w_register & !r_jump & !r_push & !r_pop &
(r_operand == 3'b001)) |
(w_brk & (r_operand == 3'b110)) |
(w_jsr & (r_operand == 3'b101)) |
(w_rts & (r_operand == 3'b001));
assign w_adder_in_a = (w_idx_ind_add & (r_operand == 3'b011)) ?
r_data[7:0] :
w_adder_valid ? r_data[15:8] : 8'h00;
assign w_adder_in_b = !w_adder_valid ? 8'h00 :
r_carry ? 8'h01 :
(w_idx_ind_add & (r_operand == 3'b011)) ? 8'h01 :
(w_ind_idx_add & (r_operand == 3'b011)) ? 8'h01 :
(w_abs_idx_x | w_zero_idx_x | w_indirect_x) ?
rf2mc_x : rf2mc_y;
assign w_adder_sum = w_adder_in_a + w_adder_in_b;
assign w_adder_valid = (w_abs_idx_add | w_zero_idx_add | w_idx_ind_add |
w_ind_idx_add);
assign w_register_data = (r_reg == REG_A) ? rf2mc_a :
(r_reg == REG_X) ? rf2mc_x :
(r_reg == REG_Y) ? rf2mc_y : rf2mc_s;
assign w_jsr_data = (r_operand == 3'b011) ? rf2mc_pc[15:8] :
rf2mc_pc[7:0];
assign w_jmp = r_jump & !r_push & !r_pop;
assign w_jsr = r_jump & r_push & !r_reg[0];
assign w_brk = r_jump & r_push & r_reg[0];
assign w_rts = r_jump & r_pop & !r_reg[0];
assign w_rti = r_jump & r_pop & r_reg[0];
always @ (posedge clk or negedge rst_x) begin
if (!rst_x) begin
r_operand <= 3'b000;
r_modex <= 1'b0;
r_mode <= 3'b000;
r_data <= 16'h00;
r_reg <= 2'b00;
r_carry <= 1'b0;
r_store <= 1'b0;
r_push <= 1'b0;
r_pop <= 1'b0;
r_jump <= 1'b0;
end else if (id2mc_operand) begin
r_operand <= w_1t_mode ? 3'b001 :
w_2t_mode ? 3'b010 :
w_3t_mode ? 3'b011 :
w_4t_mode ? 3'b100 :
w_5t_mode ? 3'b101 :
w_6t_mode ? 3'b110 : 3'bxxx;
r_modex <= id2mc_modex;
r_mode <= id2mc_mode;
r_reg <= (id2mc_push | id2mc_pop) ? { 1'b0, id2mc_p_reg } : id2mc_reg;
r_store <= id2mc_store;
r_push <= id2mc_push;
r_pop <= id2mc_pop;
r_jump <= id2mc_jump;
end else if (r_operand != 3'b000) begin
if ((w_abs_idx | w_indirect_y) & w_adder_sum[8] & !r_carry) begin
r_carry <= 1'b1;
end else begin
r_operand <= r_operand - 3'b001;
r_carry <= 1'b0;
end
if (r_carry) begin
r_data <= { w_adder_sum[7:0], r_data[7:0] };
end else if (w_adder_valid) begin
r_data <= { i_db, w_adder_sum[7:0] };
end else if (w_jsr & ((r_operand == 3'b011) |
(r_operand == 3'b010))) begin
r_data <= r_data;
end else if (r_operand == 3'b001) begin
r_data <= o_ab;
end else begin
r_data <= { i_db, r_data[15:8] };
end
end
end
endmodule
|
module fpga_core
(
/*
* Clock: 156.25 MHz
* Synchronous reset
*/
input wire clk,
input wire rst,
/*
* GPIO
*/
input wire [1:0] sw,
input wire [3:0] jp,
output wire [3:0] led,
/*
* Silicon Labs CP2102 USB UART
*/
output wire uart_rst,
input wire uart_suspend,
output wire uart_ri,
output wire uart_dcd,
input wire uart_dtr,
output wire uart_dsr,
input wire uart_txd,
output wire uart_rxd,
input wire uart_rts,
output wire uart_cts,
/*
* AirMax I/O
*/
output wire amh_right_mdc,
input wire amh_right_mdio_i,
output wire amh_right_mdio_o,
output wire amh_right_mdio_t,
output wire amh_left_mdc,
input wire amh_left_mdio_i,
output wire amh_left_mdio_o,
output wire amh_left_mdio_t,
/*
* 10G Ethernet
*/
output wire [63:0] eth_r0_txd,
output wire [7:0] eth_r0_txc,
input wire [63:0] eth_r0_rxd,
input wire [7:0] eth_r0_rxc,
output wire [63:0] eth_r1_txd,
output wire [7:0] eth_r1_txc,
input wire [63:0] eth_r1_rxd,
input wire [7:0] eth_r1_rxc,
output wire [63:0] eth_r2_txd,
output wire [7:0] eth_r2_txc,
input wire [63:0] eth_r2_rxd,
input wire [7:0] eth_r2_rxc,
output wire [63:0] eth_r3_txd,
output wire [7:0] eth_r3_txc,
input wire [63:0] eth_r3_rxd,
input wire [7:0] eth_r3_rxc,
output wire [63:0] eth_r4_txd,
output wire [7:0] eth_r4_txc,
input wire [63:0] eth_r4_rxd,
input wire [7:0] eth_r4_rxc,
output wire [63:0] eth_r5_txd,
output wire [7:0] eth_r5_txc,
input wire [63:0] eth_r5_rxd,
input wire [7:0] eth_r5_rxc,
output wire [63:0] eth_r6_txd,
output wire [7:0] eth_r6_txc,
input wire [63:0] eth_r6_rxd,
input wire [7:0] eth_r6_rxc,
output wire [63:0] eth_r7_txd,
output wire [7:0] eth_r7_txc,
input wire [63:0] eth_r7_rxd,
input wire [7:0] eth_r7_rxc,
output wire [63:0] eth_r8_txd,
output wire [7:0] eth_r8_txc,
input wire [63:0] eth_r8_rxd,
input wire [7:0] eth_r8_rxc,
output wire [63:0] eth_r9_txd,
output wire [7:0] eth_r9_txc,
input wire [63:0] eth_r9_rxd,
input wire [7:0] eth_r9_rxc,
output wire [63:0] eth_r10_txd,
output wire [7:0] eth_r10_txc,
input wire [63:0] eth_r10_rxd,
input wire [7:0] eth_r10_rxc,
output wire [63:0] eth_r11_txd,
output wire [7:0] eth_r11_txc,
input wire [63:0] eth_r11_rxd,
input wire [7:0] eth_r11_rxc,
output wire [63:0] eth_l0_txd,
output wire [7:0] eth_l0_txc,
input wire [63:0] eth_l0_rxd,
input wire [7:0] eth_l0_rxc,
output wire [63:0] eth_l1_txd,
output wire [7:0] eth_l1_txc,
input wire [63:0] eth_l1_rxd,
input wire [7:0] eth_l1_rxc,
output wire [63:0] eth_l2_txd,
output wire [7:0] eth_l2_txc,
input wire [63:0] eth_l2_rxd,
input wire [7:0] eth_l2_rxc,
output wire [63:0] eth_l3_txd,
output wire [7:0] eth_l3_txc,
input wire [63:0] eth_l3_rxd,
input wire [7:0] eth_l3_rxc,
output wire [63:0] eth_l4_txd,
output wire [7:0] eth_l4_txc,
input wire [63:0] eth_l4_rxd,
input wire [7:0] eth_l4_rxc,
output wire [63:0] eth_l5_txd,
output wire [7:0] eth_l5_txc,
input wire [63:0] eth_l5_rxd,
input wire [7:0] eth_l5_rxc,
output wire [63:0] eth_l6_txd,
output wire [7:0] eth_l6_txc,
input wire [63:0] eth_l6_rxd,
input wire [7:0] eth_l6_rxc,
output wire [63:0] eth_l7_txd,
output wire [7:0] eth_l7_txc,
input wire [63:0] eth_l7_rxd,
input wire [7:0] eth_l7_rxc,
output wire [63:0] eth_l8_txd,
output wire [7:0] eth_l8_txc,
input wire [63:0] eth_l8_rxd,
input wire [7:0] eth_l8_rxc,
output wire [63:0] eth_l9_txd,
output wire [7:0] eth_l9_txc,
input wire [63:0] eth_l9_rxd,
input wire [7:0] eth_l9_rxc,
output wire [63:0] eth_l10_txd,
output wire [7:0] eth_l10_txc,
input wire [63:0] eth_l10_rxd,
input wire [7:0] eth_l10_rxc,
output wire [63:0] eth_l11_txd,
output wire [7:0] eth_l11_txc,
input wire [63:0] eth_l11_rxd,
input wire [7:0] eth_l11_rxc
);
// UART
assign uart_rst = 1'b1;
assign uart_txd = 1'b1;
// AirMax I/O
assign amh_right_mdc = 1'b1;
assign amh_right_mdio_o = 1'b1;
assign amh_right_mdio_t = 1'b1;
assign amh_left_mdc = 1'b1;
assign amh_left_mdio_o = 1'b1;
assign amh_left_mdio_t = 1'b1;
assign eth_l8_txd = 64'h0707070707070707;
assign eth_l8_txc = 8'hff;
assign eth_l9_txd = 64'h0707070707070707;
assign eth_l9_txc = 8'hff;
assign eth_l10_txd = 64'h0707070707070707;
assign eth_l10_txc = 8'hff;
//assign eth_l11_txd = 64'h0707070707070707;
//assign eth_l11_txc = 8'hff;
assign eth_r8_txd = 64'h0707070707070707;
assign eth_r8_txc = 8'hff;
assign eth_r9_txd = 64'h0707070707070707;
assign eth_r9_txc = 8'hff;
assign eth_r10_txd = 64'h0707070707070707;
assign eth_r10_txc = 8'hff;
assign eth_r11_txd = 64'h0707070707070707;
assign eth_r11_txc = 8'hff;
reg [7:0] select_reg_0 = 0;
reg [7:0] select_reg_1 = 1;
reg [7:0] select_reg_2 = 2;
reg [7:0] select_reg_3 = 3;
reg [7:0] select_reg_4 = 4;
reg [7:0] select_reg_5 = 5;
reg [7:0] select_reg_6 = 6;
reg [7:0] select_reg_7 = 7;
reg [7:0] select_reg_8 = 8;
reg [7:0] select_reg_9 = 9;
reg [7:0] select_reg_10 = 10;
reg [7:0] select_reg_11 = 11;
reg [7:0] select_reg_12 = 12;
reg [7:0] select_reg_13 = 13;
reg [7:0] select_reg_14 = 14;
reg [7:0] select_reg_15 = 15;
axis_crosspoint #(
.S_COUNT(16),
.M_COUNT(16),
.DATA_WIDTH(64),
.KEEP_ENABLE(1),
.KEEP_WIDTH(8),
.LAST_ENABLE(0),
.ID_ENABLE(0),
.DEST_ENABLE(0),
.USER_ENABLE(0)
)
axis_crosspoint_inst (
.clk(clk),
.rst(rst),
.s_axis_tdata({eth_r7_rxd, eth_r6_rxd, eth_r5_rxd, eth_r4_rxd, eth_r3_rxd, eth_r2_rxd, eth_r1_rxd, eth_r0_rxd, eth_l7_rxd, eth_l6_rxd, eth_l5_rxd, eth_l4_rxd, eth_l3_rxd, eth_l2_rxd, eth_l1_rxd, eth_l0_rxd}),
.s_axis_tkeep({eth_r7_rxc, eth_r6_rxc, eth_r5_rxc, eth_r4_rxc, eth_r3_rxc, eth_r2_rxc, eth_r1_rxc, eth_r0_rxc, eth_l7_rxc, eth_l6_rxc, eth_l5_rxc, eth_l4_rxc, eth_l3_rxc, eth_l2_rxc, eth_l1_rxc, eth_l0_rxc}),
.s_axis_tvalid(16'hffff),
.s_axis_tlast(0),
.s_axis_tid(0),
.s_axis_tdest(0),
.s_axis_tuser(0),
.m_axis_tdata({eth_r7_txd, eth_r6_txd, eth_r5_txd, eth_r4_txd, eth_r3_txd, eth_r2_txd, eth_r1_txd, eth_r0_txd, eth_l7_txd, eth_l6_txd, eth_l5_txd, eth_l4_txd, eth_l3_txd, eth_l2_txd, eth_l1_txd, eth_l0_txd}),
.m_axis_tkeep({eth_r7_txc, eth_r6_txc, eth_r5_txc, eth_r4_txc, eth_r3_txc, eth_r2_txc, eth_r1_txc, eth_r0_txc, eth_l7_txc, eth_l6_txc, eth_l5_txc, eth_l4_txc, eth_l3_txc, eth_l2_txc, eth_l1_txc, eth_l0_txc}),
.m_axis_tvalid(),
.m_axis_tlast(),
.m_axis_tid(),
.m_axis_tdest(),
.m_axis_tuser(),
.select({select_reg_15[3:0], select_reg_14[3:0], select_reg_13[3:0], select_reg_12[3:0], select_reg_11[3:0], select_reg_10[3:0], select_reg_9[3:0], select_reg_8[3:0], select_reg_7[3:0], select_reg_6[3:0], select_reg_5[3:0], select_reg_4[3:0], select_reg_3[3:0], select_reg_2[3:0], select_reg_1[3:0], select_reg_0[3:0]})
);
wire [63:0] eth_rx_axis_tdata;
wire [7:0] eth_rx_axis_tkeep;
wire eth_rx_axis_tvalid;
wire eth_rx_axis_tready;
wire eth_rx_axis_tlast;
wire eth_rx_axis_tuser;
wire eth_rx_hdr_valid;
wire eth_rx_hdr_ready;
wire [47:0] eth_rx_dest_mac;
wire [47:0] eth_rx_src_mac;
wire [15:0] eth_rx_type;
wire [63:0] eth_rx_payload_axis_tdata;
wire [7:0] eth_rx_payload_axis_tkeep;
wire eth_rx_payload_axis_tvalid;
wire eth_rx_payload_axis_tready;
wire eth_rx_payload_axis_tlast;
wire eth_rx_payload_axis_tuser;
eth_mac_10g_fifo #(
.ENABLE_PADDING(1),
.ENABLE_DIC(1),
.MIN_FRAME_LENGTH(64),
.TX_FIFO_DEPTH(4096),
.TX_FRAME_FIFO(1),
.RX_FIFO_DEPTH(4096),
.RX_FRAME_FIFO(1)
)
eth_mac_fifo_inst (
.rx_clk(clk),
.rx_rst(rst),
.tx_clk(clk),
.tx_rst(rst),
.logic_clk(clk),
.logic_rst(rst),
.tx_axis_tdata(0),
.tx_axis_tkeep(0),
.tx_axis_tvalid(0),
.tx_axis_tready(),
.tx_axis_tlast(0),
.tx_axis_tuser(0),
.rx_axis_tdata(eth_rx_axis_tdata),
.rx_axis_tkeep(eth_rx_axis_tkeep),
.rx_axis_tvalid(eth_rx_axis_tvalid),
.rx_axis_tready(eth_rx_axis_tready),
.rx_axis_tlast(eth_rx_axis_tlast),
.rx_axis_tuser(eth_rx_axis_tuser),
.xgmii_rxd(eth_l11_rxd),
.xgmii_rxc(eth_l11_rxc),
.xgmii_txd(eth_l11_txd),
.xgmii_txc(eth_l11_txc),
.tx_fifo_overflow(),
.tx_fifo_bad_frame(),
.tx_fifo_good_frame(),
.rx_error_bad_frame(),
.rx_error_bad_fcs(),
.rx_fifo_overflow(),
.rx_fifo_bad_frame(),
.rx_fifo_good_frame(),
.ifg_delay(12)
);
eth_axis_rx #(
.DATA_WIDTH(64),
.KEEP_WIDTH(8)
)
eth_axis_rxinst (
.clk(clk),
.rst(rst),
// AXI input
.s_axis_tdata(eth_rx_axis_tdata),
.s_axis_tkeep(eth_rx_axis_tkeep),
.s_axis_tvalid(eth_rx_axis_tvalid),
.s_axis_tready(eth_rx_axis_tready),
.s_axis_tlast(eth_rx_axis_tlast),
.s_axis_tuser(eth_rx_axis_tuser),
// Ethernet frame output
.m_eth_hdr_valid(eth_rx_hdr_valid),
.m_eth_hdr_ready(eth_rx_hdr_ready),
.m_eth_dest_mac(eth_rx_dest_mac),
.m_eth_src_mac(eth_rx_src_mac),
.m_eth_type(eth_rx_type),
.m_eth_payload_axis_tdata(eth_rx_payload_axis_tdata),
.m_eth_payload_axis_tkeep(eth_rx_payload_axis_tkeep),
.m_eth_payload_axis_tvalid(eth_rx_payload_axis_tvalid),
.m_eth_payload_axis_tready(eth_rx_payload_axis_tready),
.m_eth_payload_axis_tlast(eth_rx_payload_axis_tlast),
.m_eth_payload_axis_tuser(eth_rx_payload_axis_tuser),
// Status signals
.busy(),
.error_header_early_termination()
);
// interpret config packet
localparam [2:0]
STATE_IDLE = 3'd0,
STATE_WORD_0 = 3'd1,
STATE_WORD_1 = 3'd2,
STATE_WAIT = 3'd3;
reg [2:0] state_reg = STATE_IDLE;
reg eth_rx_hdr_ready_reg = 0;
reg eth_rx_payload_axis_tready_reg = 0;
assign eth_rx_hdr_ready = eth_rx_hdr_ready_reg;
assign eth_rx_payload_axis_tready = eth_rx_payload_axis_tready_reg;
always @(posedge clk) begin
if (rst) begin
state_reg <= STATE_IDLE;
eth_rx_hdr_ready_reg <= 0;
eth_rx_payload_axis_tready_reg <= 0;
select_reg_0 <= 0;
select_reg_1 <= 1;
select_reg_2 <= 2;
select_reg_3 <= 3;
select_reg_4 <= 4;
select_reg_5 <= 5;
select_reg_6 <= 6;
select_reg_7 <= 7;
select_reg_8 <= 8;
select_reg_9 <= 9;
select_reg_10 <= 10;
select_reg_11 <= 11;
select_reg_12 <= 12;
select_reg_13 <= 13;
select_reg_14 <= 14;
select_reg_15 <= 15;
end else begin
case (state_reg)
STATE_IDLE: begin
eth_rx_hdr_ready_reg <= 1;
eth_rx_payload_axis_tready_reg <= 0;
if (eth_rx_hdr_ready && eth_rx_hdr_valid) begin
if (eth_rx_type == 16'h8099) begin
state_reg <= STATE_WORD_0;
eth_rx_hdr_ready_reg <= 0;
eth_rx_payload_axis_tready_reg <= 1;
end else begin
state_reg <= STATE_WAIT;
eth_rx_hdr_ready_reg <= 0;
eth_rx_payload_axis_tready_reg <= 1;
end
end
end
STATE_WORD_0: begin
eth_rx_hdr_ready_reg <= 0;
eth_rx_payload_axis_tready_reg <= 1;
if (eth_rx_payload_axis_tready && eth_rx_payload_axis_tvalid) begin
if (eth_rx_payload_axis_tlast) begin
state_reg <= STATE_IDLE;
eth_rx_hdr_ready_reg <= 1;
eth_rx_payload_axis_tready_reg <= 0;
end else begin
select_reg_0 <= eth_rx_payload_axis_tdata[7:0];
select_reg_1 <= eth_rx_payload_axis_tdata[15:8];
select_reg_2 <= eth_rx_payload_axis_tdata[23:16];
select_reg_3 <= eth_rx_payload_axis_tdata[31:24];
select_reg_4 <= eth_rx_payload_axis_tdata[39:32];
select_reg_5 <= eth_rx_payload_axis_tdata[47:40];
select_reg_6 <= eth_rx_payload_axis_tdata[55:48];
select_reg_7 <= eth_rx_payload_axis_tdata[63:56];
state_reg <= STATE_WORD_1;
eth_rx_hdr_ready_reg <= 0;
eth_rx_payload_axis_tready_reg <= 1;
end
end
end
STATE_WORD_1: begin
eth_rx_hdr_ready_reg <= 0;
eth_rx_payload_axis_tready_reg <= 1;
if (eth_rx_payload_axis_tready && eth_rx_payload_axis_tvalid) begin
if (eth_rx_payload_axis_tlast) begin
state_reg <= STATE_IDLE;
eth_rx_hdr_ready_reg <= 1;
eth_rx_payload_axis_tready_reg <= 0;
end else begin
select_reg_8 <= eth_rx_payload_axis_tdata[7:0];
select_reg_9 <= eth_rx_payload_axis_tdata[15:8];
select_reg_10 <= eth_rx_payload_axis_tdata[23:16];
select_reg_11 <= eth_rx_payload_axis_tdata[31:24];
select_reg_12 <= eth_rx_payload_axis_tdata[39:32];
select_reg_13 <= eth_rx_payload_axis_tdata[47:40];
select_reg_14 <= eth_rx_payload_axis_tdata[55:48];
select_reg_15 <= eth_rx_payload_axis_tdata[63:56];
state_reg <= STATE_WAIT;
eth_rx_hdr_ready_reg <= 0;
eth_rx_payload_axis_tready_reg <= 1;
end
end
end
STATE_WAIT: begin
eth_rx_hdr_ready_reg <= 0;
eth_rx_payload_axis_tready_reg <= 1;
if (eth_rx_payload_axis_tready && eth_rx_payload_axis_tvalid) begin
if (eth_rx_payload_axis_tlast) begin
state_reg <= STATE_IDLE;
eth_rx_hdr_ready_reg <= 1;
eth_rx_payload_axis_tready_reg <= 0;
end else begin
state_reg <= STATE_WAIT;
eth_rx_hdr_ready_reg <= 0;
eth_rx_payload_axis_tready_reg <= 1;
end
end
end
endcase
end
end
endmodule
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